prototype works

riscv-ac.srcs/sources_1/new/if_id.v

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: IF/ID register
+// Module Name: if_id
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Register between IF/ID stages
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module if_id (
+    input clk,
+    input rst,
+    input en,
+    input clr,
+    input [31:0] npc_in,
+    input [31:0] pc4_in,
+    input [31:0] ir_in,
+    output reg [31:0] npc_out,
+    output reg [31:0] pc4_out,
+    output reg [31:0] ir_out
+);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            npc_out <= 32'b0;
+            pc4_out <= 32'b0;
+            ir_out  <= 32'b0;
+        end else if (clr) begin
+            npc_out <= 32'b0;
+            pc4_out <= 32'b0;
+            ir_out  <= 32'b0; 
+        end else if (en) begin
+            npc_out <= npc_in;
+            pc4_out <= pc4_in;
+            ir_out  <= ir_in;
+        end
+    end
+endmodule