prototype works

riscv-ac.srcs/sources_1/new/id_ex.v

@@ -0,0 +1,57 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: ID/EX register
+// Module Name: id_ex
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Register between ID/EX stages
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module id_ex (
+    input clk, rst, clr, 
+
+    // señales de la UC y ALU
+    input we_reg_in, we_mem_in, mem_to_reg_in, alu_src_in, branch_in, jump_in,
+    input [3:0] alu_op_in,
+    
+    output reg we_reg_out, we_mem_out, mem_to_reg_out, alu_src_out, branch_out, jump_out,
+    output reg [3:0] alu_op_out,
+
+    // PC4, A, B, C, Rd
+    input [31:0] pc4_in, regA_in, regB_in, regC_in,
+    input [4:0] rs1_in, rs2_in, rd_in,
+    
+    output reg [31:0] pc4_out, regA_out, regB_out, regC_out,
+    output reg [4:0] rs1_out, rs2_out, rd_out
+);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst || clr) begin
+            we_reg_out <= 0; we_mem_out <= 0; mem_to_reg_out <= 0;
+            alu_src_out <= 0; branch_out <= 0; jump_out <= 0; alu_op_out <= 4'b0;
+            pc4_out <= 0; regA_out <= 0; regB_out <= 0; regC_out <= 0;
+            rs1_out <= 0; rs2_out <= 0; rd_out <= 0;
+        end 
+        else begin
+            we_reg_out <= we_reg_in; we_mem_out <= we_mem_in; 
+            mem_to_reg_out <= mem_to_reg_in; alu_src_out <= alu_src_in;
+            branch_out <= branch_in; jump_out <= jump_in; alu_op_out <= alu_op_in;
+            pc4_out <= pc4_in; 
+            regA_out <= regA_in; regB_out <= regB_in; regC_out <= regC_in;
+            rs1_out <= rs1_in; rs2_out <= rs2_in; rd_out <= rd_in;
+        end
+    end
+endmodule