prototype works

riscv-ac.srcs/sources_1/new/hazard.v

@@ -0,0 +1,62 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: Hazard Unit
+// Module Name: hazard
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Manages hazards between memory instructions and any other
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module hazard (
+    input [4:0] IF_ID_Rs1,
+    input [4:0] IF_ID_Rs2,
+    input [4:0] ID_EX_Rd,
+    input       ID_EX_MemRead,
+    input       Branch_Taken,
+    output reg PC_En,
+    output reg IF_ID_En,
+    output reg IF_ID_Clr,
+    output reg ID_EX_Clr
+);
+
+    always @(*) begin
+        PC_En     = 1'b1;
+        IF_ID_En  = 1'b1;
+        IF_ID_Clr = 1'b0;
+        ID_EX_Clr = 1'b0;
+
+        // si:
+        // - se lee de memoria
+        // - el Rd no es x0
+        // - el Rd es Rs1 o Rs2
+        // entonces: 
+        //   bloqueamos para que el dato generado en ME lo pueda coger EX
+        if (ID_EX_MemRead && (ID_EX_Rd != 5'b0) && 
+           ((ID_EX_Rd == IF_ID_Rs1) || (ID_EX_Rd == IF_ID_Rs2))) begin
+            PC_En     = 1'b0;
+            IF_ID_En  = 1'b0;
+            ID_EX_Clr = 1'b1;
+        end
+        // si:
+        // - salto tomado
+        // entonces:
+        //   flush síncrono al reg IF/ID
+        else if (Branch_Taken) begin
+            IF_ID_Clr = 1'b1; 
+        end
+    end
+
+endmodule