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prototype works

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Jose
2026-03-02 23:20:54 +01:00
parent 8f2b31259c
commit e7cd451e7e
62 changed files with 8924 additions and 220 deletions
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riscv-ac.srcs/sources_1/new/forwarding.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
//
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: Forwarding
// Module Name: forwarding
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Manages forwarding MUXes selection inputs
//
// Dependencies:
//
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module forwarding (
input [4:0] ID_EX_Rs1,
input [4:0] ID_EX_Rs2,
input [4:0] IF_ID_Rs1,
input [4:0] IF_ID_Rs2,
input [4:0] EX_ME_Rd,
input EX_ME_RegWrite,
input [4:0] ME_WB_Rd,
input ME_WB_RegWrite,
output reg [1:0] EX_ForwardA,
output reg [1:0] EX_ForwardB,
output reg [1:0] ID_ForwardA,
output reg [1:0] ID_ForwardB
);
always @(*) begin
EX_ForwardA = 2'b00;
EX_ForwardB = 2'b00;
ID_ForwardA = 2'b00;
ID_ForwardB = 2'b00;
// Bypass A (EX)
if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == ID_EX_Rs1))
EX_ForwardA = 2'b10;
else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == ID_EX_Rs1))
EX_ForwardA = 2'b01;
// Bypass B (EX)
if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == ID_EX_Rs2))
EX_ForwardB = 2'b10;
else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == ID_EX_Rs2))
EX_ForwardB = 2'b01;
// Bypass A (ID)
if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == IF_ID_Rs1))
ID_ForwardA = 2'b10;
else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == IF_ID_Rs1))
ID_ForwardA = 2'b01;
// Bypass B (ID)
if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == IF_ID_Rs2))
ID_ForwardB = 2'b10;
else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == IF_ID_Rs2))
ID_ForwardB = 2'b01;
end
endmodule