prototype works

riscv-ac.srcs/sources_1/new/dmem.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Data Memory
 // Module Name: dmem
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Stores data
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
@@ -29,12 +29,21 @@ module dmem(
 );
 
 reg [31:0] memory[0:255];
+reg [31:0] data;
+
+integer i;
+initial begin
+    for (i = 0; i < 256; i = i + 1) begin
+        memory[i] = 32'b0;
+    end
+end
 
 always @(posedge clk) begin
     if (we)
         memory[address[9:2]] <= write_data;
+    data <= memory[address[9:2]];
 end
 
-assign read_data = memory[address[9:2]];
+assign read_data = data;
 
 endmodule