prototype works

riscv-ac.srcs/sources_1/new/alu.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Arithmetic-Logic Unit
 // Module Name: alu
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Main functional unit of the EX stage
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
@@ -29,18 +29,18 @@ module alu(
 
 always @(*) begin
     case(sel)
-        4'b0000: R <= A + B;               // add
-        4'b0001: R <= A - B;               // sub
-        4'b0010: R <= A & B;               // and
-        4'b0011: R <= A | B;               // or
-        4'b0100: R <= A ^ B;               // xor
-        4'b0101: R <= A << B[4:0];         // sll (shamt = 5 bits)
-        4'b0110: R <= A >> B[4:0];         // srl (logical)
-        4'b0111: R <= ($signed(A) < $signed(B)) ? 1 : 0; // slt signed
-        4'b1000: R <= (A < B) ? 1 : 0;     // sltu unsigned
-        4'b1001: R <= $signed(A) >>> B[4:0]; // sra arithmetic right
-        4'b1010: R <= 32'b0;               // default / nop opcional
-        default: R <= 32'b0;
+        4'b0000: R = A + B;                             // add
+        4'b0001: R = A - B;                             // sub
+        4'b0010: R = A & B;                             // and
+        4'b0011: R = A | B;                             // or
+        4'b0100: R = A ^ B;                             // xor
+        4'b0101: R = A << B[4:0];                       // sll
+        4'b0110: R = A >> B[4:0];                       // srl
+        4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt (shift if less than signed)
+        4'b1000: R = (A < B) ? 1 : 0;                   // sltu (shift if less than unsigned)
+        4'b1001: R = $signed(A) >>> B[4:0];             // sra (shift right arithmetic)
+        4'b1010: R = 32'b0;                             // nop
+        default: R = 32'b0;                             // default: nop
     endcase
 end