prototype works

riscv-ac.srcs/sim_1/new/program.mem

@@ -0,0 +1,3 @@
+000000B3
+00810113
+002080B3

riscv-ac.srcs/sim_1/new/tb_top.v

@@ -0,0 +1,58 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/01/2026 07:26:34 PM
+// Design Name: 
+// Module Name: tb_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+`timescale 1ns / 1ps
+
+module tb_top();
+    reg clk;
+    reg rst;
+    wire [1:0] leds;
+    wire [31:0] debug;
+
+    top uut (
+        .clk(clk),
+        .rst(rst),
+        .leds(leds),
+        .debug(debug)
+    );
+    
+    // T_CLK = 10ns
+    always #5 clk = ~clk;
+
+    initial begin
+        // inicializamos señales
+        clk = 0;
+        rst = 1;
+
+        // cargamos programa
+        $readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory);
+
+        // activamos reset 20ns
+        #20;
+        rst = 0;
+
+        // ejecución de 100 ciclos
+        #150;
+
+        $finish;
+    end
+endmodule