prototype works

riscv-ac.sim/sim_1/behav/xsim/compile.sh

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+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2025.2 (64-bit)
+#
+# Filename    : compile.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Mon Mar 02 22:22:56 CET 2026
+# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+export SIM_VER_XSIM=2025.2
+export GCC_VER_XSIM=9.3.0
+
+# catch pipeline exit status
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj tb_top_vlog.prj"
+xvlog --incr --relax -prj tb_top_vlog.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."