prototype works

riscv-ac.sim/sim_1/behav/xsim/compile.sh

@@ -0,0 +1,28 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2025.2 (64-bit)
+#
+# Filename    : compile.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Mon Mar 02 22:22:56 CET 2026
+# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+export SIM_VER_XSIM=2025.2
+export GCC_VER_XSIM=9.3.0
+
+# catch pipeline exit status
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj tb_top_vlog.prj"
+xvlog --incr --relax -prj tb_top_vlog.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."

riscv-ac.sim/sim_1/behav/xsim/elaborate.sh

@@ -0,0 +1,26 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2025.2 (64-bit)
+#
+# Filename    : elaborate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Mon Mar 02 22:22:58 CET 2026
+# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+export SIM_VER_XSIM=2025.2
+export GCC_VER_XSIM=9.3.0
+
+# catch pipeline exit status
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log
+

riscv-ac.sim/sim_1/behav/xsim/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

riscv-ac.sim/sim_1/behav/xsim/program.mem

@@ -0,0 +1,3 @@
+000000B3
+00810113
+002080B3

riscv-ac.sim/sim_1/behav/xsim/simulate.sh

@@ -0,0 +1,26 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2025.2 (64-bit)
+#
+# Filename    : simulate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Mon Mar 02 22:16:52 CET 2026
+# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+export SIM_VER_XSIM=2025.2
+export GCC_VER_XSIM=9.3.0
+
+# catch pipeline exit status
+set -Eeuo pipefail
+# simulate design
+echo "xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log"
+xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log
+

riscv-ac.sim/sim_1/behav/xsim/tb_top.tcl

@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj

@@ -0,0 +1,23 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  --include "../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef" \
+"../../../../riscv-ac.srcs/sources_1/new/alu.v" \
+"../../../../riscv-ac.srcs/sources_1/new/control.v" \
+"../../../../riscv-ac.srcs/sources_1/new/dmem.v" \
+"../../../../riscv-ac.srcs/sources_1/new/ex_me.v" \
+"../../../../riscv-ac.srcs/sources_1/new/forwarding.v" \
+"../../../../riscv-ac.srcs/sources_1/new/hazard.v" \
+"../../../../riscv-ac.srcs/sources_1/new/id_ex.v" \
+"../../../../riscv-ac.srcs/sources_1/new/if_id.v" \
+"../../../../riscv-ac.srcs/sources_1/new/imem.v" \
+"../../../../riscv-ac.srcs/sources_1/new/imm_gen.v" \
+"../../../../riscv-ac.srcs/sources_1/new/me_wb.v" \
+"../../../../riscv-ac.srcs/sources_1/new/pc.v" \
+"../../../../riscv-ac.srcs/sources_1/new/regfile.v" \
+"../../../../riscv-ac.srcs/sources_1/new/top.v" \
+"../../../../riscv-ac.srcs/sim_1/new/tb_top.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/Compile_Options.txt

@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_top_behav" "xil_defaultlib.tb_top" "xil_defaultlib.glbl" -log "elaborate.log" 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/TempBreakPointFile.txt

@@ -0,0 +1 @@
+Breakpoint File Version 1.0

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx

@@ -0,0 +1,12 @@
+
+{ 
+    crc :  1048859293793588504  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl" , 
+    buildDate : "Nov 14 2025" , 
+    buildTime : "12:36:23" , 
+    linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/tb_top_behav/xsimk\"   \"xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel    -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.version

@@ -0,0 +1 @@
+hjhoth

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=93
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
+OBJECT_NAME_COLUMN_WIDTH=121
+OBJECT_VALUE_COLUMN_WIDTH=72
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -0,0 +1,20 @@
+0.7
+2020.2
+Nov 14 2025
+12:36:23
+/home/jomaa/git/riscv-ac/riscv-ac.sim/sim_1/behav/xsim/glbl.v,1756381829,verilog,,,,glbl,,,,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,1772486573,verilog,,,,tb_top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772483312,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772483371,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772485582,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,1772468735,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,,ex_me,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,1772467332,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,,forwarding,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,1772467244,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,,hazard,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772472446,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,1772468688,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,,if_id,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772485445,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772470571,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772468767,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772289140,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,1772486142,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,,top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xsim.version

@@ -0,0 +1 @@
+hjhoth

riscv-ac.sim/sim_1/behav/xsim/xsim.ini

@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib