refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00
parent a4b158d6a8
commit d7e166ca6f
50 changed files with 10662 additions and 48 deletions
--- a/riscv-ac.srcs/sim_1/new/tb_riscv.v
+++ b/riscv-ac.srcs/sim_1/new/tb_riscv.v
@@ -5,7 +5,7 @@
 // 
 // Create Date: 02/20/2026 09:21:52 AM
 // Design Name: RISCV AC Processor Simulation
-// Module Name: tb_top
+// Module Name: tb_riscv
 // Project Name: riscv-ac
 // Target Devices: Artix 7
 // Tool Versions: 2025.2
@@ -23,7 +23,7 @@

 `timescale 1ns / 1ps

-module tb_top();
+module tb_riscv();
    reg clk;
    reg rst;
    
@@ -33,7 +33,7 @@ module tb_top();
    reg rx;
    wire tx;

-    top uut (
+    riscv uut (
        .clk(clk),
        .rst(rst),
        .rx(rx),