diff --git a/riscv-ac.runs/impl_1/riscv.bit b/riscv-ac.runs/impl_1/riscv.bit new file mode 100644 index 0000000..db9f809 Binary files /dev/null and b/riscv-ac.runs/impl_1/riscv.bit differ diff --git a/riscv-ac.runs/impl_1/riscv_clock_utilization_routed.rpt b/riscv-ac.runs/impl_1/riscv_clock_utilization_routed.rpt new file mode 100644 index 0000000..e8c5487 --- /dev/null +++ b/riscv-ac.runs/impl_1/riscv_clock_utilization_routed.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +| Date : Tue Mar 3 03:57:33 2026 +| Host : odin running 64-bit Arch Linux +| Command : report_clock_utilization -file riscv_clock_utilization_routed.rpt +| Design : riscv +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y2 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 563 | 0 | 83.330 | sys_clk_pin | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | 83.330 | sys_clk_pin | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 547 | 1800 | 166 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | sys_clk_pin | 83.330 | {0.000 41.660} | 549 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+---------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+------+----+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+------+----+-----------------------+ +| Y2 | 549 | 0 | 0 | +| Y1 | 0 | 0 | - | +| Y0 | 0 | 0 | - | ++----+------+----+-----------------------+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y2 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 549 | 0 | 547 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2} +#endgroup diff --git a/riscv-ac.runs/impl_1/riscv_utilization_placed.rpt b/riscv-ac.runs/impl_1/riscv_utilization_placed.rpt new file mode 100644 index 0000000..b82249a --- /dev/null +++ b/riscv-ac.runs/impl_1/riscv_utilization_placed.rpt @@ -0,0 +1,224 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +| Date : Tue Mar 3 03:57:20 2026 +| Host : odin running 64-bit Arch Linux +| Command : report_utilization -file riscv_utilization_placed.rpt -pb riscv_utilization_placed.pb +| Design : riscv +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs | 1172 | 0 | 0 | 20800 | 5.63 | +| LUT as Logic | 1128 | 0 | 0 | 20800 | 5.42 | +| LUT as Memory | 44 | 0 | 0 | 9600 | 0.46 | +| LUT as Distributed RAM | 44 | 0 | | | | +| LUT as Shift Register | 0 | 0 | | | | +| Slice Registers | 547 | 0 | 0 | 41600 | 1.31 | +| Register as Flip Flop | 547 | 0 | 0 | 41600 | 1.31 | +| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 | +| Unique Control Sets | 19 | | 0 | 8150 | 0.23 | ++----------------------------+------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. +** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 419 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 128 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+------+-------+------------+-----------+-------+ +| Slice | 357 | 0 | 0 | 8150 | 4.38 | +| SLICEL | 271 | 0 | | | | +| SLICEM | 86 | 0 | | | | +| LUT as Logic | 1128 | 0 | 0 | 20800 | 5.42 | +| using O5 output only | 0 | | | | | +| using O6 output only | 859 | | | | | +| using O5 and O6 | 269 | | | | | +| LUT as Memory | 44 | 0 | 0 | 9600 | 0.46 | +| LUT as Distributed RAM | 44 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 0 | | | | | +| using O5 and O6 | 44 | | | | | +| LUT as Shift Register | 0 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 0 | | | | | +| using O5 and O6 | 0 | | | | | +| Slice Registers | 547 | 0 | 0 | 41600 | 1.31 | +| Register driven from within the Slice | 389 | | | | | +| Register driven from outside the Slice | 158 | | | | | +| LUT in front of the register is unused | 57 | | | | | +| LUT in front of the register is used | 101 | | | | | ++--------------------------------------------+------+-------+------------+-----------+-------+ + + +3. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 1 | 0 | 0 | 50 | 2.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 | +| RAMB18 | 2 | 0 | 0 | 100 | 2.00 | +| RAMB18E1 only | 2 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 6 | 6 | 0 | 106 | 5.66 | +| IOB Master Pads | 3 | | | | | +| IOB Slave Pads | 3 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 0 | 20 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT6 | 484 | LUT | +| FDCE | 419 | Flop & Latch | +| LUT5 | 295 | LUT | +| LUT2 | 229 | LUT | +| LUT3 | 207 | LUT | +| LUT4 | 179 | LUT | +| FDRE | 128 | Flop & Latch | +| RAMD32 | 68 | Distributed Memory | +| CARRY4 | 59 | CarryLogic | +| RAMS32 | 20 | Distributed Memory | +| OBUF | 3 | IO | +| LUT1 | 3 | LUT | +| IBUF | 3 | IO | +| RAMB18E1 | 2 | Block Memory | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/riscv-ac.runs/synth_1/__synthesis_is_complete__ b/riscv-ac.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/riscv-ac.runs/synth_1/riscv_utilization_synth.rpt b/riscv-ac.runs/synth_1/riscv_utilization_synth.rpt new file mode 100644 index 0000000..4fdf95f --- /dev/null +++ b/riscv-ac.runs/synth_1/riscv_utilization_synth.rpt @@ -0,0 +1,193 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +| Date : Tue Mar 3 03:57:03 2026 +| Host : odin running 64-bit Arch Linux +| Command : report_utilization -file riscv_utilization_synth.rpt -pb riscv_utilization_synth.pb +| Design : riscv +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 1237 | 0 | 0 | 20800 | 5.95 | +| LUT as Logic | 1189 | 0 | 0 | 20800 | 5.72 | +| LUT as Memory | 48 | 0 | 0 | 9600 | 0.50 | +| LUT as Distributed RAM | 48 | 0 | | | | +| LUT as Shift Register | 0 | 0 | | | | +| Slice Registers | 547 | 0 | 0 | 41600 | 1.31 | +| Register as Flip Flop | 547 | 0 | 0 | 41600 | 1.31 | +| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 | +| Unique Control Sets | 19 | | 0 | 8150 | 0.23 | ++----------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances +** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 419 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 128 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 1 | 0 | 0 | 50 | 2.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 | +| RAMB18 | 2 | 0 | 0 | 100 | 2.00 | +| RAMB18E1 only | 2 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 6 | 0 | 0 | 106 | 5.66 | +| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 0 | 20 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT6 | 484 | LUT | +| FDCE | 419 | Flop & Latch | +| LUT5 | 295 | LUT | +| LUT2 | 229 | LUT | +| LUT3 | 207 | LUT | +| LUT4 | 179 | LUT | +| FDRE | 128 | Flop & Latch | +| RAMD32 | 68 | Distributed Memory | +| CARRY4 | 59 | CarryLogic | +| LUT1 | 37 | LUT | +| RAMS32 | 20 | Distributed Memory | +| OBUF | 3 | IO | +| IBUF | 3 | IO | +| RAMB18E1 | 2 | Block Memory | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/riscv-ac.sim/sim_1/behav/xsim/compile.sh b/riscv-ac.sim/sim_1/behav/xsim/compile.sh index 6eb26ec..f2897c9 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/compile.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/compile.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for compiling the simulation design source files # -# Generated by Vivado on Tue Mar 03 03:38:48 CET 2026 +# Generated by Vivado on Tue Mar 03 03:46:01 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. @@ -21,8 +21,8 @@ export GCC_VER_XSIM=9.3.0 # catch pipeline exit status set -Eeuo pipefail # compile Verilog/System Verilog design sources -echo "xvlog --incr --relax -prj tb_top_vlog.prj" -xvlog --incr --relax -prj tb_top_vlog.prj 2>&1 | tee compile.log +echo "xvlog --incr --relax -prj tb_riscv_vlog.prj" +xvlog --incr --relax -prj tb_riscv_vlog.prj 2>&1 | tee compile.log echo "Waiting for jobs to finish..." echo "No pending jobs, compilation finished." diff --git a/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh b/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh index 036c318..2e65c17 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for elaborating the compiled design # -# Generated by Vivado on Tue Mar 03 03:38:49 CET 2026 +# Generated by Vivado on Tue Mar 03 03:46:03 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. @@ -21,6 +21,6 @@ export GCC_VER_XSIM=9.3.0 # catch pipeline exit status set -Eeuo pipefail # elaborate design -echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log" -xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log +echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl -log elaborate.log" +xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl -log elaborate.log diff --git a/riscv-ac.sim/sim_1/behav/xsim/simulate.sh b/riscv-ac.sim/sim_1/behav/xsim/simulate.sh index 94c0d98..16c889f 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/simulate.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/simulate.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for simulating the design by launching the simulator # -# Generated by Vivado on Tue Mar 03 03:38:51 CET 2026 +# Generated by Vivado on Tue Mar 03 03:46:04 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. @@ -21,6 +21,6 @@ export GCC_VER_XSIM=9.3.0 # catch pipeline exit status set -Eeuo pipefail # simulate design -echo "xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log" -xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log +echo "xsim tb_riscv_behav -key {Behavioral:sim_1:Functional:tb_riscv} -tclbatch tb_riscv.tcl -log simulate.log" +xsim tb_riscv_behav -key {Behavioral:sim_1:Functional:tb_riscv} -tclbatch tb_riscv.tcl -log simulate.log diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_riscv.tcl b/riscv-ac.sim/sim_1/behav/xsim/tb_riscv.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/tb_riscv.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_riscv_behav.wdb b/riscv-ac.sim/sim_1/behav/xsim/tb_riscv_behav.wdb new file mode 100644 index 0000000..e390cb8 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/tb_riscv_behav.wdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj b/riscv-ac.sim/sim_1/behav/xsim/tb_riscv_vlog.prj similarity index 90% rename from riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj rename to riscv-ac.sim/sim_1/behav/xsim/tb_riscv_vlog.prj index bf86398..1e455e4 100644 --- a/riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj +++ b/riscv-ac.sim/sim_1/behav/xsim/tb_riscv_vlog.prj @@ -13,10 +13,10 @@ verilog xil_defaultlib --include "../../../../../../../../opt/Xilinx/2025.2/dat "../../../../riscv-ac.srcs/sources_1/new/me_wb.v" \ "../../../../riscv-ac.srcs/sources_1/new/pc.v" \ "../../../../riscv-ac.srcs/sources_1/new/regfile.v" \ -"../../../../riscv-ac.srcs/sources_1/new/top.v" \ +"../../../../riscv-ac.srcs/sources_1/new/riscv.v" \ "../../../../riscv-ac.srcs/sources_1/new/uart_bootloader.v" \ "../../../../riscv-ac.srcs/sources_1/new/uart_tx.v" \ -"../../../../riscv-ac.srcs/sim_1/new/tb_top.v" \ +"../../../../riscv-ac.srcs/sim_1/new/tb_riscv.v" \ # compile glbl module verilog xil_defaultlib "glbl.v" diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb b/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb index e8aea32..9e78cdf 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb and b/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/Compile_Options.txt b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/Compile_Options.txt new file mode 100644 index 0000000..6ea1444 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_riscv_behav" "xil_defaultlib.tb_riscv" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/TempBreakPointFile.txt b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/obj/xsim_0.lnx64.o b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..e7dc459 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/obj/xsim_0.lnx64.o differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/obj/xsim_1.lnx64.o b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..7721a88 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/obj/xsim_1.lnx64.o differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.dbg b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.dbg new file mode 100644 index 0000000..61a46fd Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.dbg differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.mem b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.mem new file mode 100644 index 0000000..f77a386 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.mem differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.reloc b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.reloc new file mode 100644 index 0000000..af6acbd Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.reloc differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rlx b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rlx new file mode 100644 index 0000000..b45561c --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 16958966524678923290 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_riscv_behav/xsimk\" \"xsim.dir/tb_riscv_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_riscv_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rtti b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rtti new file mode 100644 index 0000000..03aac72 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rtti differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.svtype b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.svtype new file mode 100644 index 0000000..10f09ab Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.svtype differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.type b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.type new file mode 100644 index 0000000..14a09a2 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.type differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.version b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.xdbg b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.xdbg new file mode 100644 index 0000000..1920ddd Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.xdbg differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimSettings.ini b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimSettings.ini new file mode 100644 index 0000000..fb69b5e --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=100 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103 +OBJECT_NAME_COLUMN_WIDTH=147 +OBJECT_VALUE_COLUMN_WIDTH=49 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimk b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimk new file mode 100755 index 0000000..9b1d16b Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimk differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini index ebaf2b7..6f7b2a1 100644 --- a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini @@ -25,11 +25,11 @@ INOUT_PROTOINST_FILTER=true INTERNAL_PROTOINST_FILTER=true CONSTANT_PROTOINST_FILTER=true VARIABLE_PROTOINST_FILTER=true -SCOPE_NAME_COLUMN_WIDTH=93 -SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83 +SCOPE_NAME_COLUMN_WIDTH=159 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=108 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103 -OBJECT_NAME_COLUMN_WIDTH=147 -OBJECT_VALUE_COLUMN_WIDTH=49 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 OBJECT_DATA_TYPE_COLUMN_WIDTH=75 PROCESS_NAME_COLUMN_WIDTH=75 PROCESS_TYPE_COLUMN_WIDTH=75 diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb index 727b4c9..a30eb9f 100644 Binary files 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a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_bootloader.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_bootloader.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_tx.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_tx.sdb index be3f65d..129b986 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_tx.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_tx.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index 2bc4182..426cfac 100644 --- a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -3,7 +3,8 @@ Nov 14 2025 12:36:23 /home/jomaa/git/riscv-ac/riscv-ac.sim/sim_1/behav/xsim/glbl.v,1756381829,verilog,,,,glbl,,,,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,1772504151,verilog,,,,tb_top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +,,,,,,tb_riscv,,,,,,,, +,,,,,,,,,,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772490502,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772486779,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772490163,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, @@ -16,7 +17,7 @@ Nov 14 2025 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772490121,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772490599,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772490088,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, 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+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/riscv.v,1772505870,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,,riscv,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,1772505678,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,,uart_bootloader,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,1772503459,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_riscv.v,,uart_tx,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, diff --git a/riscv-ac.srcs/sim_1/new/tb_top.v b/riscv-ac.srcs/sim_1/new/tb_riscv.v similarity index 97% rename from riscv-ac.srcs/sim_1/new/tb_top.v rename to riscv-ac.srcs/sim_1/new/tb_riscv.v index 9ae76aa..3e825ed 100644 --- a/riscv-ac.srcs/sim_1/new/tb_top.v +++ b/riscv-ac.srcs/sim_1/new/tb_riscv.v @@ -5,7 +5,7 @@ // // Create Date: 02/20/2026 09:21:52 AM // Design Name: RISCV AC Processor Simulation -// Module Name: tb_top +// Module Name: tb_riscv // Project Name: riscv-ac // Target Devices: Artix 7 // Tool Versions: 2025.2 @@ -23,7 +23,7 @@ `timescale 1ns / 1ps -module tb_top(); +module tb_riscv(); reg clk; reg rst; @@ -33,7 +33,7 @@ module tb_top(); reg rx; wire tx; - top uut ( + riscv uut ( .clk(clk), .rst(rst), .rx(rx), diff --git a/riscv-ac.srcs/sources_1/new/top.v b/riscv-ac.srcs/sources_1/new/riscv.v similarity index 96% rename from riscv-ac.srcs/sources_1/new/top.v rename to riscv-ac.srcs/sources_1/new/riscv.v index 000fae3..2f853f7 100644 --- a/riscv-ac.srcs/sources_1/new/top.v +++ b/riscv-ac.srcs/sources_1/new/riscv.v @@ -5,7 +5,7 @@ // // Create Date: 02/20/2026 09:21:52 AM // Design Name: RISCV AC Processor Implementation -// Module Name: top +// Module Name: riscv // Project Name: riscv-ac // Target Devices: Artix 7 // Tool Versions: 2025.2 @@ -20,21 +20,14 @@ // ////////////////////////////////////////////////////////////////////////////////// -module top ( - input clk, - input rst, - - // Programacion - input [31:0] prog_data, - input [31:0] prog_addr, - input prog_we, - - // Debug & UART - input rx, - output tx, - output [1:0] leds, - output [7:0] uart_tx_data, - output uart_tx_en +module riscv ( + input wire clk, + input wire rst, + input wire rx, + output wire tx, + output wire [1:0] leds + // output wire [7:0] uart_tx_data, // SOLO SIMULACION + // output wire uart_tx_en // SOLO SIMULACION ); // ========================================== @@ -219,7 +212,9 @@ module top ( // --- hacemos un apaño pa poder sacar cosas a la UART (MMIO) --- wire is_uart = (alu_res_ME == 32'hFFFFFFFC); wire dmem_we = we_mem_ME & ~is_uart; // si va pa la UART no escribimos en memoria - + wire [7:0] uart_tx_data; + wire uart_tx_en; + assign uart_tx_en = we_mem_ME & is_uart; assign uart_tx_data = regB_ME[7:0]; diff --git a/riscv-ac.xpr b/riscv-ac.xpr index f2e3cf4..50655ae 100644 --- a/riscv-ac.xpr +++ b/riscv-ac.xpr @@ -61,7 +61,7 @@