refactor: renamed top.v to riscv.v

riscv-ac.srcs/sim_1/new/tb_riscv.v

@@ -5,7 +5,7 @@
 // 
 // Create Date: 02/20/2026 09:21:52 AM
 // Design Name: RISCV AC Processor Simulation
-// Module Name: tb_top
+// Module Name: tb_riscv
 // Project Name: riscv-ac
 // Target Devices: Artix 7
 // Tool Versions: 2025.2
@@ -23,7 +23,7 @@
 
 `timescale 1ns / 1ps
 
-module tb_top();
+module tb_riscv();
     reg clk;
     reg rst;
     
@@ -33,7 +33,7 @@ module tb_top();
     reg rx;
     wire tx;
 
-    top uut (
+    riscv uut (
         .clk(clk),
         .rst(rst),
         .rx(rx),

riscv-ac.srcs/sources_1/new/riscv.v

@@ -5,7 +5,7 @@
 // 
 // Create Date: 02/20/2026 09:21:52 AM
 // Design Name: RISCV AC Processor Implementation
-// Module Name: top
+// Module Name: riscv
 // Project Name: riscv-ac
 // Target Devices: Artix 7
 // Tool Versions: 2025.2
@@ -20,21 +20,14 @@
 // 
 //////////////////////////////////////////////////////////////////////////////////
 
-module top (
-    input clk,
-    input rst,
-    
-    // Programacion
-    input [31:0] prog_data,
-    input [31:0] prog_addr,
-    input prog_we,
-    
-    // Debug & UART
-    input rx,
-    output tx,
-    output [1:0] leds,
-    output [7:0] uart_tx_data,
-    output uart_tx_en
+module riscv (
+    input wire clk,
+    input wire rst,
+    input wire rx,
+    output wire tx,    
+    output wire [1:0] leds
+    // output wire [7:0] uart_tx_data, // SOLO SIMULACION
+    // output wire uart_tx_en // SOLO SIMULACION
 );
 
     // ==========================================
@@ -219,7 +212,9 @@ module top (
     // --- hacemos un apaño pa poder sacar cosas a la UART (MMIO) ---
     wire is_uart = (alu_res_ME == 32'hFFFFFFFC);
     wire dmem_we = we_mem_ME & ~is_uart; // si va pa la UART no escribimos en memoria
-    
+    wire [7:0] uart_tx_data;
+    wire uart_tx_en;
+
     assign uart_tx_en = we_mem_ME & is_uart;
     assign uart_tx_data = regB_ME[7:0];