Gallardo7761/riscv-ac
1
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

refactor: renamed top.v to riscv.v

Browse Source
This commit is contained in:
Jose
2026-03-03 04:05:49 +01:00
parent a4b158d6a8
commit d7e166ca6f
50 changed files with 10662 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
riscv-ac.sim/sim_1/behav/xsim/simulate.sh
View File

@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
# Generated by Vivado on Tue Mar 03 03:38:51 CET 2026
# Generated by Vivado on Tue Mar 03 03:46:04 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -21,6 +21,6 @@ export GCC_VER_XSIM=9.3.0
# catch pipeline exit status
set -Eeuo pipefail
# simulate design
echo "xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log"
xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log
echo "xsim tb_riscv_behav -key {Behavioral:sim_1:Functional:tb_riscv} -tclbatch tb_riscv.tcl -log simulate.log"
xsim tb_riscv_behav -key {Behavioral:sim_1:Functional:tb_riscv} -tclbatch tb_riscv.tcl -log simulate.log