Gallardo7761/riscv-ac
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refactor: renamed top.v to riscv.v

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Jose
2026-03-03 04:05:49 +01:00
parent a4b158d6a8
commit d7e166ca6f
50 changed files with 10662 additions and 48 deletions
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6
riscv-ac.sim/sim_1/behav/xsim/elaborate.sh
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@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
# Generated by Vivado on Tue Mar 03 03:38:49 CET 2026
# Generated by Vivado on Tue Mar 03 03:46:03 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -21,6 +21,6 @@ export GCC_VER_XSIM=9.3.0
# catch pipeline exit status
set -Eeuo pipefail
# elaborate design
echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log"
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log
echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl -log elaborate.log"
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl -log elaborate.log