Gallardo7761/riscv-ac
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refactor: renamed top.v to riscv.v

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Jose
2026-03-03 04:05:49 +01:00
parent a4b158d6a8
commit d7e166ca6f
50 changed files with 10662 additions and 48 deletions
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6
riscv-ac.sim/sim_1/behav/xsim/compile.sh
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@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Tue Mar 03 03:38:48 CET 2026
# Generated by Vivado on Tue Mar 03 03:46:01 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -21,8 +21,8 @@ export GCC_VER_XSIM=9.3.0
# catch pipeline exit status
set -Eeuo pipefail
# compile Verilog/System Verilog design sources
echo "xvlog --incr --relax -prj tb_top_vlog.prj"
xvlog --incr --relax -prj tb_top_vlog.prj 2>&1 | tee compile.log
echo "xvlog --incr --relax -prj tb_riscv_vlog.prj"
xvlog --incr --relax -prj tb_riscv_vlog.prj 2>&1 | tee compile.log
echo "Waiting for jobs to finish..."
echo "No pending jobs, compilation finished."