refactor: renamed top.v to riscv.v

riscv-ac.sim/sim_1/behav/xsim/compile.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for compiling the simulation design source files
 #
-# Generated by Vivado on Tue Mar 03 03:38:48 CET 2026
+# Generated by Vivado on Tue Mar 03 03:46:01 CET 2026
 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -21,8 +21,8 @@ export GCC_VER_XSIM=9.3.0
 # catch pipeline exit status
 set -Eeuo pipefail
 # compile Verilog/System Verilog design sources
-echo "xvlog --incr --relax -prj tb_top_vlog.prj"
-xvlog --incr --relax -prj tb_top_vlog.prj 2>&1 | tee compile.log
+echo "xvlog --incr --relax -prj tb_riscv_vlog.prj"
+xvlog --incr --relax -prj tb_riscv_vlog.prj 2>&1 | tee compile.log
 
 echo "Waiting for jobs to finish..."
 echo "No pending jobs, compilation finished."

riscv-ac.sim/sim_1/behav/xsim/elaborate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for elaborating the compiled design
 #
-# Generated by Vivado on Tue Mar 03 03:38:49 CET 2026
+# Generated by Vivado on Tue Mar 03 03:46:03 CET 2026
 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -21,6 +21,6 @@ export GCC_VER_XSIM=9.3.0
 # catch pipeline exit status
 set -Eeuo pipefail
 # elaborate design
-echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log"
-xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl -log elaborate.log
 

riscv-ac.sim/sim_1/behav/xsim/simulate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for simulating the design by launching the simulator
 #
-# Generated by Vivado on Tue Mar 03 03:38:51 CET 2026
+# Generated by Vivado on Tue Mar 03 03:46:04 CET 2026
 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -21,6 +21,6 @@ export GCC_VER_XSIM=9.3.0
 # catch pipeline exit status
 set -Eeuo pipefail
 # simulate design
-echo "xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log"
-xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log
+echo "xsim tb_riscv_behav -key {Behavioral:sim_1:Functional:tb_riscv} -tclbatch tb_riscv.tcl -log simulate.log"
+xsim tb_riscv_behav -key {Behavioral:sim_1:Functional:tb_riscv} -tclbatch tb_riscv.tcl -log simulate.log
 

riscv-ac.sim/sim_1/behav/xsim/tb_riscv.tcl

@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

riscv-ac.sim/sim_1/behav/xsim/tb_riscv_vlog.prj

@@ -13,10 +13,10 @@ verilog xil_defaultlib  --include "../../../../../../../../opt/Xilinx/2025.2/dat
 "../../../../riscv-ac.srcs/sources_1/new/me_wb.v" \
 "../../../../riscv-ac.srcs/sources_1/new/pc.v" \
 "../../../../riscv-ac.srcs/sources_1/new/regfile.v" \
-"../../../../riscv-ac.srcs/sources_1/new/top.v" \
+"../../../../riscv-ac.srcs/sources_1/new/riscv.v" \
 "../../../../riscv-ac.srcs/sources_1/new/uart_bootloader.v" \
 "../../../../riscv-ac.srcs/sources_1/new/uart_tx.v" \
-"../../../../riscv-ac.srcs/sim_1/new/tb_top.v" \
+"../../../../riscv-ac.srcs/sim_1/new/tb_riscv.v" \
 
 # compile glbl module
 verilog xil_defaultlib "glbl.v"

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/Compile_Options.txt

@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_riscv_behav" "xil_defaultlib.tb_riscv" "xil_defaultlib.glbl" -log "elaborate.log" 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/TempBreakPointFile.txt

@@ -0,0 +1 @@
+Breakpoint File Version 1.0

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rlx

@@ -0,0 +1,12 @@
+
+{ 
+    crc :  16958966524678923290  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl" , 
+    buildDate : "Nov 14 2025" , 
+    buildTime : "12:36:23" , 
+    linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/tb_riscv_behav/xsimk\"   \"xsim.dir/tb_riscv_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_riscv_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel    -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.version

@@ -0,0 +1 @@
+hjhoth

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=100
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
+OBJECT_NAME_COLUMN_WIDTH=147
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini

@@ -25,11 +25,11 @@ INOUT_PROTOINST_FILTER=true
 INTERNAL_PROTOINST_FILTER=true
 CONSTANT_PROTOINST_FILTER=true
 VARIABLE_PROTOINST_FILTER=true
-SCOPE_NAME_COLUMN_WIDTH=93
-SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83
+SCOPE_NAME_COLUMN_WIDTH=159
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=108
 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
-OBJECT_NAME_COLUMN_WIDTH=147
-OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
 OBJECT_DATA_TYPE_COLUMN_WIDTH=75
 PROCESS_NAME_COLUMN_WIDTH=75
 PROCESS_TYPE_COLUMN_WIDTH=75

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -3,7 +3,8 @@
 Nov 14 2025
 12:36:23
 /home/jomaa/git/riscv-ac/riscv-ac.sim/sim_1/behav/xsim/glbl.v,1756381829,verilog,,,,glbl,,,,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,1772504151,verilog,,,,tb_top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+,,,,,,tb_riscv,,,,,,,,
+,,,,,,,,,,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772490502,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772486779,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772490163,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
@@ -16,7 +17,7 @@ Nov 14 2025
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772490121,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772490599,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772490088,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,1772503421,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,,top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,1772505234,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,,uart_bootloader,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,1772503459,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,,uart_tx,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/riscv.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/riscv.v,1772505870,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,,riscv,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,1772505678,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,,uart_bootloader,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,1772503459,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_riscv.v,,uart_tx,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,