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refactor: renamed top.v to riscv.v

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Jose
2026-03-03 04:05:49 +01:00
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riscv-ac.runs/impl_1/riscv.bit Normal file
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riscv-ac.runs/impl_1/riscv_clock_utilization_routed.rpt Normal file
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date : Tue Mar 3 03:57:33 2026
| Host : odin running 64-bit Arch Linux
| Command : report_clock_utilization -file riscv_clock_utilization_routed.rpt
| Design : riscv
| Device : 7a35t-cpg236
| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Routed
---------------------------------------------------------------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y2
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 72 | 0 | 0 | 0 |
| BUFIO | 0 | 20 | 0 | 0 | 0 |
| BUFMR | 0 | 10 | 0 | 0 | 0 |
| BUFR | 0 | 20 | 0 | 0 | 0 |
| MMCM | 0 | 5 | 0 | 0 | 0 |
| PLL | 0 | 5 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 563 | 0 | 83.330 | sys_clk_pin | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | 83.330 | sys_clk_pin | clk_IBUF_inst/O | clk_IBUF |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 547 | 1800 | 166 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | sys_clk_pin | 83.330 | {0.000 41.660} | 549 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+---------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+------+----+-----------------------+
| | X0 | X1 | HORIZONTAL PROG DELAY |
+----+------+----+-----------------------+
| Y2 | 549 | 0 | 0 |
| Y1 | 0 | 0 | - |
| Y0 | 0 | 0 | - |
+----+------+----+-----------------------+
7. Clock Region Cell Placement per Global Clock: Region X0Y2
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 549 | 0 | 547 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y26 [get_ports clk]
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}
#endgroup

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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date : Tue Mar 3 03:57:20 2026
| Host : odin running 64-bit Arch Linux
| Command : report_utilization -file riscv_utilization_placed.rpt -pb riscv_utilization_placed.pb
| Design : riscv
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Fully Placed
---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs | 1172 | 0 | 0 | 20800 | 5.63 |
| LUT as Logic | 1128 | 0 | 0 | 20800 | 5.42 |
| LUT as Memory | 44 | 0 | 0 | 9600 | 0.46 |
| LUT as Distributed RAM | 44 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | | |
| Slice Registers | 547 | 0 | 0 | 41600 | 1.31 |
| Register as Flip Flop | 547 | 0 | 0 | 41600 | 1.31 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 |
| Unique Control Sets | 19 | | 0 | 8150 | 0.23 |
+----------------------------+------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.
** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 419 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 128 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+------+-------+------------+-----------+-------+
| Slice | 357 | 0 | 0 | 8150 | 4.38 |
| SLICEL | 271 | 0 | | | |
| SLICEM | 86 | 0 | | | |
| LUT as Logic | 1128 | 0 | 0 | 20800 | 5.42 |
| using O5 output only | 0 | | | | |
| using O6 output only | 859 | | | | |
| using O5 and O6 | 269 | | | | |
| LUT as Memory | 44 | 0 | 0 | 9600 | 0.46 |
| LUT as Distributed RAM | 44 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 0 | | | | |
| using O5 and O6 | 44 | | | | |
| LUT as Shift Register | 0 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 0 | | | | |
| using O5 and O6 | 0 | | | | |
| Slice Registers | 547 | 0 | 0 | 41600 | 1.31 |
| Register driven from within the Slice | 389 | | | | |
| Register driven from outside the Slice | 158 | | | | |
| LUT in front of the register is unused | 57 | | | | |
| LUT in front of the register is used | 101 | | | | |
+--------------------------------------------+------+-------+------------+-----------+-------+
3. Memory
---------
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 1 | 0 | 0 | 50 | 2.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
| RAMB18 | 2 | 0 | 0 | 100 | 2.00 |
| RAMB18E1 only | 2 | | | | |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 6 | 6 | 0 | 106 | 5.66 |
| IOB Master Pads | 3 | | | | |
| IOB Slave Pads | 3 | | | | |
| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 104 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 106 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 106 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 20 | 0.00 |
+------------+------+-------+------------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 484 | LUT |
| FDCE | 419 | Flop & Latch |
| LUT5 | 295 | LUT |
| LUT2 | 229 | LUT |
| LUT3 | 207 | LUT |
| LUT4 | 179 | LUT |
| FDRE | 128 | Flop & Latch |
| RAMD32 | 68 | Distributed Memory |
| CARRY4 | 59 | CarryLogic |
| RAMS32 | 20 | Distributed Memory |
| OBUF | 3 | IO |
| LUT1 | 3 | LUT |
| IBUF | 3 | IO |
| RAMB18E1 | 2 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date : Tue Mar 3 03:57:03 2026
| Host : odin running 64-bit Arch Linux
| Command : report_utilization -file riscv_utilization_synth.rpt -pb riscv_utilization_synth.pb
| Design : riscv
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 1237 | 0 | 0 | 20800 | 5.95 |
| LUT as Logic | 1189 | 0 | 0 | 20800 | 5.72 |
| LUT as Memory | 48 | 0 | 0 | 9600 | 0.50 |
| LUT as Distributed RAM | 48 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | | |
| Slice Registers | 547 | 0 | 0 | 41600 | 1.31 |
| Register as Flip Flop | 547 | 0 | 0 | 41600 | 1.31 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 |
| Unique Control Sets | 19 | | 0 | 8150 | 0.23 |
+----------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
Warning! For any ECO changes, please run place_design if there are unplaced instances
** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 419 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 128 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 1 | 0 | 0 | 50 | 2.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
| RAMB18 | 2 | 0 | 0 | 100 | 2.00 |
| RAMB18E1 only | 2 | | | | |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 6 | 0 | 0 | 106 | 5.66 |
| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 104 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 106 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 106 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 20 | 0.00 |
+------------+------+-------+------------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 484 | LUT |
| FDCE | 419 | Flop & Latch |
| LUT5 | 295 | LUT |
| LUT2 | 229 | LUT |
| LUT3 | 207 | LUT |
| LUT4 | 179 | LUT |
| FDRE | 128 | Flop & Latch |
| RAMD32 | 68 | Distributed Memory |
| CARRY4 | 59 | CarryLogic |
| LUT1 | 37 | LUT |
| RAMS32 | 20 | Distributed Memory |
| OBUF | 3 | IO |
| IBUF | 3 | IO |
| RAMB18E1 | 2 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+