add: dual port imem and uart

riscv-ac.srcs/sources_1/new/top.v

@@ -1,11 +1,38 @@
 `timescale 1ns / 1ps
-`default_nettype none
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: RISCV AC Processor Implementation
+// Module Name: top
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Top module for interconnection
+// 
+// Dependencies: 
+// 
+// Revision: 2.0 - MMIO
+// Revision: 1.0 - Basic structure
+// Revision: 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 
 module top (
     input clk,
     input rst,
+    
+    // Programacion
+    input [31:0] prog_data,
+    input [31:0] prog_addr,
+    input prog_we,
+    
+    // Debug & UART
     output [1:0] leds,
-    output [31:0] debug
+    output [31:0] uart_tx_data,
+    output uart_tx_en
 );
 
     // ==========================================
@@ -26,8 +53,14 @@ module top (
     );
 
     imem u_imem (
-        .clk(clk), .address(npc_IF), .we(1'b0), 
-        .write_data(32'b0), .write_addr(8'b0), .inst_out(ir_IF)
+        .clk(clk), 
+        // por aqui lee la CPU
+        .read_addr(pc_IF), 
+        .inst_out(ir_IF),
+        // por aqui meto el programa
+        .we_ext(prog_we),
+        .write_addr_ext(prog_addr),
+        .write_data_ext(prog_data)
     );
 
     // ==========================================
@@ -161,9 +194,18 @@ module top (
     // ==========================================
     // ETAPA ME & WB
     // ==========================================
+    
+    // --- hacemos un apaño pa poder sacar cosas a la UART (MMIO) ---
+    wire is_uart = (alu_res_ME == 32'hFFFFFFFC);
+    wire dmem_we = we_mem_ME & ~is_uart; // si va pa la UART no escribimos en memoria
+    
+    assign uart_tx_en = we_mem_ME & is_uart;
+    assign uart_tx_data = regB_ME;
+    // -------------------------------------------------------------- 
+    
     wire [31:0] mem_data_ME;
     dmem u_dmem (
-        .clk(clk), .we(we_mem_ME), .address(alu_res_ME), 
+        .clk(clk), .we(dmem_we), .address(alu_res_ME), 
         .write_data(regB_ME), .mem_data_out(mem_data_ME)
     );
 
@@ -186,12 +228,5 @@ module top (
     // ==========================================
     assign leds[0] = Branch_Taken; // se enciende cuando hay salto
     assign leds[1] = ID_EX_Clr; // se enciende en bloqueos
-       
-    assign debug = {
-        alu_res_EX[15:0],
-        rd_WB,
-        rs1_ID,
-        npc_IF[7:2]
-    };
     
 endmodule