diff --git a/riscv-ac.sim/sim_1/behav/xsim/compile.sh b/riscv-ac.sim/sim_1/behav/xsim/compile.sh index d93bf08..9937498 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/compile.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/compile.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for compiling the simulation design source files # -# Generated by Vivado on Mon Mar 02 23:30:40 CET 2026 +# Generated by Vivado on Tue Mar 03 01:07:16 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh b/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh index 5b325c1..4244220 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for elaborating the compiled design # -# Generated by Vivado on Mon Mar 02 23:30:41 CET 2026 +# Generated by Vivado on Tue Mar 03 01:07:19 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/riscv-ac.sim/sim_1/behav/xsim/program.mem b/riscv-ac.sim/sim_1/behav/xsim/program.mem index 3571c71..6e7042a 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/program.mem +++ b/riscv-ac.sim/sim_1/behav/xsim/program.mem @@ -1,3 +1,4 @@ -000000B3 -00810113 -002080B3 \ No newline at end of file +04100293 +FFFFF337 +FFC30313 +00532023 \ No newline at end of file diff --git a/riscv-ac.sim/sim_1/behav/xsim/simulate.sh b/riscv-ac.sim/sim_1/behav/xsim/simulate.sh index 2bd0207..3428f55 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/simulate.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/simulate.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for simulating the design by launching the simulator # -# Generated by Vivado on Mon Mar 02 23:30:42 CET 2026 +# Generated by Vivado on Tue Mar 03 01:04:08 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb b/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb index e14a2cb..6cffc27 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb and b/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o index eeca82b..491a3da 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o index fc30c61..7e8f39d 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg index 5e8e182..5fbba82 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem index 72de886..7abeb59 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.reloc b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.reloc index 49a6444..d573b49 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.reloc and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.reloc differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx index 1cccd46..72dedca 100644 --- a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx @@ -1,6 +1,6 @@ { - crc : 5732162227090726530 , + crc : 899746931471304080 , ccp_crc : 0 , cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl" , buildDate : "Nov 14 2025" , diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rtti b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rtti index 1aa37c4..de8b1bb 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rtti and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rtti differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.xdbg b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.xdbg index 12121d5..1128940 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.xdbg and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.xdbg differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini index 5bc733c..a3736b3 100644 --- a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini @@ -25,11 +25,11 @@ INOUT_PROTOINST_FILTER=true INTERNAL_PROTOINST_FILTER=true CONSTANT_PROTOINST_FILTER=true VARIABLE_PROTOINST_FILTER=true -SCOPE_NAME_COLUMN_WIDTH=93 +SCOPE_NAME_COLUMN_WIDTH=159 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103 -OBJECT_NAME_COLUMN_WIDTH=121 -OBJECT_VALUE_COLUMN_WIDTH=72 +OBJECT_NAME_COLUMN_WIDTH=154 +OBJECT_VALUE_COLUMN_WIDTH=1904 OBJECT_DATA_TYPE_COLUMN_WIDTH=75 PROCESS_NAME_COLUMN_WIDTH=75 PROCESS_TYPE_COLUMN_WIDTH=75 diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimk b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimk index e64ba17..ce710db 100755 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimk and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimk differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb index 3d8bb86..398e045 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/control.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/control.sdb index cd6e32a..dee4a80 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/control.sdb and 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b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/me_wb.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb index 92582d2..717f036 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb index be5532a..510b80f 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb index e91c0b0..d026977 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb index 6ccbee6..3b98438 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index ba3c676..03a11fe 100644 --- a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -12,8 +12,8 @@ Nov 14 2025 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,1772467244,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,,hazard,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772490462,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,1772490110,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,,if_id,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772485445,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772470571,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772490099,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772490121,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772468767,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772289140,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, diff --git a/riscv-ac.srcs/sim_1/new/program.mem b/riscv-ac.srcs/sim_1/new/program.mem index 3571c71..6e7042a 100644 --- a/riscv-ac.srcs/sim_1/new/program.mem +++ b/riscv-ac.srcs/sim_1/new/program.mem @@ -1,3 +1,4 @@ -000000B3 -00810113 -002080B3 \ No newline at end of file +04100293 +FFFFF337 +FFC30313 +00532023 \ No newline at end of file diff --git a/riscv-ac.srcs/sim_1/new/tb_top.v b/riscv-ac.srcs/sim_1/new/tb_top.v index 6b4c1d2..94e228a 100644 --- a/riscv-ac.srcs/sim_1/new/tb_top.v +++ b/riscv-ac.srcs/sim_1/new/tb_top.v @@ -1,20 +1,21 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: nope +// Engineer: Jose // -// Create Date: 03/01/2026 07:26:34 PM -// Design Name: +// Create Date: 02/20/2026 09:21:52 AM +// Design Name: RISCV AC Processor Simulation // Module Name: tb_top -// Project Name: -// Target Devices: -// Tool Versions: -// Description: +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Testbench for simulation + MMIO // // Dependencies: // -// Revision: -// Revision 0.01 - File Created +// Revision: 2.0 - MMIO +// Revision: 1.0 - Basic structure +// Revision: 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// @@ -26,13 +27,15 @@ module tb_top(); reg clk; reg rst; wire [1:0] leds; - wire [31:0] debug; + wire [31:0] uart_tx_data; + wire uart_tx_en; top uut ( .clk(clk), .rst(rst), .leds(leds), - .debug(debug) + .uart_tx_data(uart_tx_data), + .uart_tx_en(uart_tx_en) ); // T_CLK = 10ns diff --git a/riscv-ac.srcs/sources_1/new/imem.v b/riscv-ac.srcs/sources_1/new/imem.v index 7bc58aa..da1d346 100644 --- a/riscv-ac.srcs/sources_1/new/imem.v +++ b/riscv-ac.srcs/sources_1/new/imem.v @@ -13,19 +13,24 @@ // // Dependencies: // -// Revision: 1.0 -// Revision 0.01 - File Created +// Revision: 2.0 - Dual port for UART programming +// Revision: 1.0 - Basic structure +// Revision: 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module imem( input clk, - input [31:0] address, - input we, - input [31:0] write_data, - input [7:0] write_addr, - output [31:0] inst_out + + // puerto 1 + input [31:0] read_addr, + output [31:0] inst_out, + + // puerto 2 + input we_ext, + input [31:0] write_addr_ext, + input [31:0] write_data_ext ); reg [31:0] memory[0:255]; @@ -39,9 +44,11 @@ initial begin end always @(posedge clk) begin - if(we) - memory[write_addr] <= write_data; - inst_reg <= memory[address[9:2]]; + if(we_ext) begin + memory[write_addr_ext[9:2]] <= write_data_ext; + end + + inst_reg <= memory[read_addr[9:2]]; end assign inst_out = inst_reg; diff --git a/riscv-ac.srcs/sources_1/new/top.v b/riscv-ac.srcs/sources_1/new/top.v index 3efa593..7137bcd 100644 --- a/riscv-ac.srcs/sources_1/new/top.v +++ b/riscv-ac.srcs/sources_1/new/top.v @@ -1,11 +1,38 @@ `timescale 1ns / 1ps -`default_nettype none +////////////////////////////////////////////////////////////////////////////////// +// Company: nope +// Engineer: Jose +// +// Create Date: 02/20/2026 09:21:52 AM +// Design Name: RISCV AC Processor Implementation +// Module Name: top +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Top module for interconnection +// +// Dependencies: +// +// Revision: 2.0 - MMIO +// Revision: 1.0 - Basic structure +// Revision: 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// module top ( input clk, input rst, + + // Programacion + input [31:0] prog_data, + input [31:0] prog_addr, + input prog_we, + + // Debug & UART output [1:0] leds, - output [31:0] debug + output [31:0] uart_tx_data, + output uart_tx_en ); // ========================================== @@ -26,8 +53,14 @@ module top ( ); imem u_imem ( - .clk(clk), .address(npc_IF), .we(1'b0), - .write_data(32'b0), .write_addr(8'b0), .inst_out(ir_IF) + .clk(clk), + // por aqui lee la CPU + .read_addr(pc_IF), + .inst_out(ir_IF), + // por aqui meto el programa + .we_ext(prog_we), + .write_addr_ext(prog_addr), + .write_data_ext(prog_data) ); // ========================================== @@ -161,9 +194,18 @@ module top ( // ========================================== // ETAPA ME & WB // ========================================== + + // --- hacemos un apaño pa poder sacar cosas a la UART (MMIO) --- + wire is_uart = (alu_res_ME == 32'hFFFFFFFC); + wire dmem_we = we_mem_ME & ~is_uart; // si va pa la UART no escribimos en memoria + + assign uart_tx_en = we_mem_ME & is_uart; + assign uart_tx_data = regB_ME; + // -------------------------------------------------------------- + wire [31:0] mem_data_ME; dmem u_dmem ( - .clk(clk), .we(we_mem_ME), .address(alu_res_ME), + .clk(clk), .we(dmem_we), .address(alu_res_ME), .write_data(regB_ME), .mem_data_out(mem_data_ME) ); @@ -186,12 +228,5 @@ module top ( // ========================================== assign leds[0] = Branch_Taken; // se enciende cuando hay salto assign leds[1] = ID_EX_Clr; // se enciende en bloqueos - - assign debug = { - alu_res_EX[15:0], - rd_WB, - rs1_ID, - npc_IF[7:2] - }; endmodule \ No newline at end of file diff --git a/riscv-ac.xpr b/riscv-ac.xpr index 0b30c65..3bf66e4 100644 --- a/riscv-ac.xpr +++ b/riscv-ac.xpr @@ -61,7 +61,7 @@