add: dual port imem and uart

riscv-ac.srcs/sources_1/new/imem.v

@@ -13,19 +13,24 @@
 // 
 // Dependencies: 
 // 
-// Revision: 1.0
-// Revision 0.01 - File Created
+// Revision: 2.0 - Dual port for UART programming
+// Revision: 1.0 - Basic structure
+// Revision: 0.01 - File Created
 // Additional Comments:
 // 
 //////////////////////////////////////////////////////////////////////////////////
 
 module imem(
     input clk,
-    input [31:0] address,
-    input we,
-    input [31:0] write_data,
-    input [7:0] write_addr,
-    output [31:0] inst_out
+    
+    // puerto 1
+    input [31:0] read_addr,
+    output [31:0] inst_out,
+    
+    // puerto 2
+    input we_ext,
+    input [31:0] write_addr_ext,
+    input [31:0] write_data_ext
 );
 
 reg [31:0] memory[0:255];
@@ -39,9 +44,11 @@ initial begin
 end
 
 always @(posedge clk) begin
-    if(we)
-        memory[write_addr] <= write_data;
-    inst_reg <= memory[address[9:2]];
+    if(we_ext) begin 
+        memory[write_addr_ext[9:2]] <= write_data_ext;
+    end
+        
+    inst_reg <= memory[read_addr[9:2]];
 end
 
 assign inst_out = inst_reg;