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add: dual port imem and uart

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Jose
2026-03-03 01:44:27 +01:00
parent 98f948ab18
commit a890b031a7
36 changed files with 97 additions and 50 deletions
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7
riscv-ac.srcs/sim_1/new/program.mem
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@@ -1,3 +1,4 @@
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27
riscv-ac.srcs/sim_1/new/tb_top.v
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@@ -1,20 +1,21 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// Company: nope
// Engineer: Jose
//
// Create Date: 03/01/2026 07:26:34 PM
// Design Name:
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: RISCV AC Processor Simulation
// Module Name: tb_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Testbench for simulation + MMIO
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Revision: 2.0 - MMIO
// Revision: 1.0 - Basic structure
// Revision: 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
@@ -26,13 +27,15 @@ module tb_top();
reg clk;
reg rst;
wire [1:0] leds;
wire [31:0] debug;
wire [31:0] uart_tx_data;
wire uart_tx_en;
top uut (
.clk(clk),
.rst(rst),
.leds(leds),
.debug(debug)
.uart_tx_data(uart_tx_data),
.uart_tx_en(uart_tx_en)
);
// T_CLK = 10ns