Gallardo7761/riscv-ac
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add: dual port imem and uart

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Jose
2026-03-03 01:44:27 +01:00
parent 98f948ab18
commit a890b031a7
36 changed files with 97 additions and 50 deletions
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riscv-ac.sim/sim_1/behav/xsim/elaborate.sh
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@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
# Generated by Vivado on Mon Mar 02 23:30:41 CET 2026
# Generated by Vivado on Tue Mar 03 01:07:19 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.