add: dual port imem and uart

riscv-ac.sim/sim_1/behav/xsim/compile.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for compiling the simulation design source files
 #
-# Generated by Vivado on Mon Mar 02 23:30:40 CET 2026
+# Generated by Vivado on Tue Mar 03 01:07:16 CET 2026
 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

riscv-ac.sim/sim_1/behav/xsim/elaborate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for elaborating the compiled design
 #
-# Generated by Vivado on Mon Mar 02 23:30:41 CET 2026
+# Generated by Vivado on Tue Mar 03 01:07:19 CET 2026
 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

riscv-ac.sim/sim_1/behav/xsim/program.mem

@@ -1,3 +1,4 @@
-000000B3
-00810113
-002080B3
+04100293
+FFFFF337
+FFC30313
+00532023

riscv-ac.sim/sim_1/behav/xsim/simulate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for simulating the design by launching the simulator
 #
-# Generated by Vivado on Mon Mar 02 23:30:42 CET 2026
+# Generated by Vivado on Tue Mar 03 01:04:08 CET 2026
 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx

@@ -1,6 +1,6 @@
 
 { 
-    crc :  5732162227090726530  , 
+    crc :  899746931471304080  , 
     ccp_crc :  0  , 
     cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl" , 
     buildDate : "Nov 14 2025" , 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini

@@ -25,11 +25,11 @@ INOUT_PROTOINST_FILTER=true
 INTERNAL_PROTOINST_FILTER=true
 CONSTANT_PROTOINST_FILTER=true
 VARIABLE_PROTOINST_FILTER=true
-SCOPE_NAME_COLUMN_WIDTH=93
+SCOPE_NAME_COLUMN_WIDTH=159
 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83
 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
-OBJECT_NAME_COLUMN_WIDTH=121
-OBJECT_VALUE_COLUMN_WIDTH=72
+OBJECT_NAME_COLUMN_WIDTH=154
+OBJECT_VALUE_COLUMN_WIDTH=1904
 OBJECT_DATA_TYPE_COLUMN_WIDTH=75
 PROCESS_NAME_COLUMN_WIDTH=75
 PROCESS_TYPE_COLUMN_WIDTH=75

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -12,8 +12,8 @@ Nov 14 2025
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,1772467244,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,,hazard,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772490462,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,1772490110,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,,if_id,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772485445,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772470571,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772490099,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772490121,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772468767,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772289140,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,