Initial commit

riscv-ac.srcs/sources_1/new/top.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: 
+// Module Name: top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top(
+    input clk, rst,
+    input [31:0] uart_data,
+    output [31:0] pc_out, alu_out, mem_data
+);
+
+// = PC ===================================
+wire [31:0] pc_next, pc;
+wire branch_taken;
+
+pc pc_inst(
+    .clk(clk),
+    .rst(rst),
+    .next_pc(pc_next),
+    .imem_addr(pc_curr)
+);
+
+assign pc_out = pc_curr;
+// ========================================
+
+// = IMEM =================================
+wire [31:0] instr;
+
+imem imem_inst(
+    .address(pc_curr),
+    .instruction(instr)
+);
+// ========================================
+
+// = DECODE ===============================
+wire [6:0] opcode = instr[6:0];
+wire [4:0] rd     = instr[11:7];
+wire [2:0] funct3 = instr[14:12];
+wire [4:0] rs1    = instr[19:15];
+wire [4:0] rs2    = instr[24:20];
+wire [6:0] funct7 = instr[31:25];
+// ========================================
+
+// regfile mux
+wire [31:0] reg_write_data;
+assign reg_write_data = mem_to_reg ? dmem_read_data : alu_out;
+
+// = REGFILE ===============================
+wire [31:0] reg_r1, reg_r2;
+wire we_reg;
+
+regfile regfile_inst(
+    .clk(clk),
+    .regwrite(we_reg),
+    .rs1(rs1),
+    .rs2(rs2),
+    .rd(rd),
+    .write_data(reg_write_data),
+    .read_data_1(reg_r1),
+    .read_data_2(reg_r2)
+);
+// ========================================
+
+// = IMMGEN ===============================
+wire [31:0] imm_out;
+
+imm_gen imm_gen_inst(
+    .instr(instr),
+    .imm_out(imm_out)
+);
+// ========================================
+
+// = CONTROL ===============================
+wire we_mem, mem_to_reg, alu_src;
+wire [3:0] alu_op;
+
+control control_inst(
+    .opcode(opcode),
+    .funct3(funct3),
+    .funct7(funct7),
+    .we_reg(we_reg),
+    .we_mem(we_mem),
+    .mem_to_reg(mem_to_reg),
+    .alu_src(alu_src),
+    .alu_op(alu_op),
+    .branch(branch_taken)
+);
+// ========================================
+
+// = ALU ==================================
+wire [31:0] alu_b = alu_src ? imm_out : reg_r2;
+
+alu alu_inst(
+    .A(reg_r1),
+    .B(alu_b),
+    .sel(alu_op),
+    .R(alu_out)
+);
+// ========================================
+
+// = DMEM =================================
+wire [31:0] dmem_read_data;
+
+dmem dmem_inst(
+    .clk(clk),
+    .we(we_mem),
+    .address(alu_out),
+    .write_data(reg_r2),
+    .read_data(dmem_read_data)
+);
+
+assign mem_data = dmem_read_data;
+// ========================================
+
+// PC increment
+assign pc_next = branch_taken ? (pc_curr + imm_out) : (pc_curr + 4);
+
+endmodule