Initial commit

riscv-ac.srcs/sources_1/new/dmem.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: 
+// Module Name: dmem
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module dmem(
+    input clk,
+    input we,
+    input [31:0] address,
+    input [31:0] write_data,
+    output [31:0] read_data
+);
+
+reg [31:0] memory[0:255];
+
+always @(posedge clk) begin
+    if (we)
+        memory[address[9:2]] <= write_data;
+end
+
+assign read_data = memory[address[9:2]];
+
+endmodule