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Jose
2026-02-20 11:33:05 +01:00
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riscv-ac.srcs/sources_1/new/control.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/20/2026 09:21:52 AM
// Design Name:
// Module Name: control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module control(
input [6:0] opcode,
input [2:0] funct3,
input [6:0] funct7,
output reg we_reg,
output reg we_mem,
output reg mem_to_reg,
output reg alu_src,
output reg [3:0] alu_op,
output reg branch
);
localparam OP_R = 7'b0110011;
localparam OP_I = 7'b0010011;
localparam OP_LOAD= 7'b0000011;
localparam OP_STORE=7'b0100011;
localparam OP_BRANCH=7'b1100011;
localparam OP_JAL = 7'b1101111;
always @(*) begin
we_reg = 0;
we_mem = 0;
mem_to_reg = 0;
alu_src = 0;
alu_op = 4'b0000;
branch = 0;
case(opcode)
OP_R: begin
we_reg = 1;
alu_src = 0;
case({funct7,funct3})
10'b0000000000: alu_op = 4'b0000; // ADD
10'b0100000000: alu_op = 4'b0001; // SUB
10'b0000000111: alu_op = 4'b0010; // AND
10'b0000000110: alu_op = 4'b0011; // OR
10'b0000000100: alu_op = 4'b0100; // XOR
10'b0000000001: alu_op = 4'b0101; // SLL
10'b0000000101: alu_op = 4'b0110; // SRL
10'b0100000101: alu_op = 4'b0111; // SRA
10'b0000000010: alu_op = 4'b1000; // SLT
10'b0000000011: alu_op = 4'b1001; // SLTU
endcase
end
OP_I: begin
we_reg = 1;
alu_src = 1;
case(funct3)
3'b000: alu_op = 4'b0000; // ADDI
3'b111: alu_op = 4'b0010; // ANDI
3'b110: alu_op = 4'b0011; // ORI
3'b100: alu_op = 4'b0100; // XORI
3'b001: alu_op = 4'b0101; // SLLI
3'b101: alu_op = (funct7==7'b0000000)?4'b0110:4'b0111; // SRLI/SRAI
3'b010: alu_op = 4'b1000; // SLTI
3'b011: alu_op = 4'b1001; // SLTIU
endcase
end
OP_LOAD: begin
we_reg = 1;
we_mem = 0;
mem_to_reg = 1;
alu_src = 1; // addr = rs1 + immediate
alu_op = 4'b0000;
end
OP_STORE: begin
we_mem = 1;
alu_src = 1; // addr = rs1 + immediate
alu_op = 4'b0000;
end
OP_BRANCH: begin
branch = 1;
alu_src = 0;
alu_op = 4'b0001;
end
OP_JAL: begin
we_reg = 1; // rd <- PC+4
alu_src = 1;
alu_op = 4'b0000;
end
default: begin end
endcase
end
endmodule