fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00
parent d7e166ca6f
commit 534cb00c42
35 changed files with 24 additions and 143 deletions
--- a/riscv-ac.srcs/sources_1/new/uart_tx.v
+++ b/riscv-ac.srcs/sources_1/new/uart_tx.v
@@ -28,7 +28,7 @@ module uart_tx (
 );

    // 12e6 / 115200 = 104 ciclos
-    localparam CLKS_PER_BIT =  104; // 104;
+    localparam CLKS_PER_BIT =  868; // 104;
    
    localparam S_IDLE  = 2'b00;
    localparam S_START = 2'b01;