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fixed: uart module and simulation-only signals handling

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Jose
2026-03-07 21:53:09 +01:00
parent d7e166ca6f
commit 534cb00c42
35 changed files with 24 additions and 143 deletions
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13
riscv-ac.srcs/sources_1/new/riscv.v
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@@ -25,9 +25,9 @@ module riscv (
input wire rst,
input wire rx,
output wire tx,
output wire [1:0] leds
// output wire [7:0] uart_tx_data, // SOLO SIMULACION
// output wire uart_tx_en // SOLO SIMULACION
output wire [1:0] leds,
output wire [7:0] uart_tx_data, // SOLO SIMULACION
output wire uart_tx_en // SOLO SIMULACION
);
// ==========================================
@@ -53,7 +53,7 @@ module riscv (
// ETAPA IF
// ==========================================
wire [31:0] npc_IF, pc4_IF, ir_IF, next_pc_IF, pc_stall;
wire PC_En, IF_ID_En, IF_ID_Clr;
wire PC_En, IF_ID_En, IF_ID_Clr, Branch_Taken;
assign next_pc_IF = (Branch_Taken) ? branch_target_ID : pc4_IF;
assign pc4_IF = npc_IF + 4;
@@ -99,7 +99,6 @@ module riscv (
// Señales de Control
wire we_reg_ID, we_mem_ID, mem_to_reg_ID, alu_src_ID, branch_ID, jump_ID;
wire [3:0] alu_op_ID;
wire Branch_Taken;
wire [31:0] branch_target_ID;
control u_control (
@@ -212,8 +211,8 @@ module riscv (
// --- hacemos un apaño pa poder sacar cosas a la UART (MMIO) ---
wire is_uart = (alu_res_ME == 32'hFFFFFFFC);
wire dmem_we = we_mem_ME & ~is_uart; // si va pa la UART no escribimos en memoria
wire [7:0] uart_tx_data;
wire uart_tx_en;
//wire [7:0] uart_tx_data;
//wire uart_tx_en;
assign uart_tx_en = we_mem_ME & is_uart;
assign uart_tx_data = regB_ME[7:0];