fixed: uart module and simulation-only signals handling

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rlx

@@ -1,6 +1,6 @@
 
 { 
-    crc :  16958966524678923290  , 
+    crc :  8975882019563799446  , 
     ccp_crc :  0  , 
     cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl" , 
     buildDate : "Nov 14 2025" , 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimSettings.ini

@@ -28,8 +28,8 @@ VARIABLE_PROTOINST_FILTER=true
 SCOPE_NAME_COLUMN_WIDTH=100
 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83
 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
-OBJECT_NAME_COLUMN_WIDTH=147
-OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
 OBJECT_DATA_TYPE_COLUMN_WIDTH=75
 PROCESS_NAME_COLUMN_WIDTH=75
 PROCESS_TYPE_COLUMN_WIDTH=75