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fixed: uart module and simulation-only signals handling

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Jose
2026-03-07 21:53:09 +01:00
parent d7e166ca6f
commit 534cb00c42
35 changed files with 24 additions and 143 deletions
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riscv-ac.sim/sim_1/behav/xsim/compile.sh
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@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Tue Mar 03 03:46:01 CET 2026
# Generated by Vivado on Wed Mar 04 01:36:45 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.