48946 lines
1.8 MiB
48946 lines
1.8 MiB
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P5_SETR2.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00013b00 08000190 08000190 00001190 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000f7c 08013c90 08013c90 00014c90 2**3
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08014c0c 08014c0c 0001629c 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 08014c0c 08014c0c 00015c0c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08014c14 08014c14 0001629c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08014c14 08014c14 00015c14 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08014c18 08014c18 00015c18 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 0000029c 20000000 08014c1c 00016000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 0000343c 2000029c 08014eb8 0001629c 2**2
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ALLOC
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10 ._user_heap_stack 00000600 200036d8 08014eb8 000166d8 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0001629c 2**0
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CONTENTS, READONLY
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12 .debug_info 000325c3 00000000 00000000 000162cc 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00007360 00000000 00000000 0004888f 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00002cf0 00000000 00000000 0004fbf0 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 000022a2 00000000 00000000 000528e0 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 000302c4 00000000 00000000 00054b82 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 000354bb 00000000 00000000 00084e46 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 00112dc8 00000000 00000000 000ba301 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 001cd0c9 2**0
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CONTENTS, READONLY
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20 .debug_frame 0000d368 00000000 00000000 001cd10c 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000061 00000000 00000000 001da474 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000190 <__do_global_dtors_aux>:
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8000190: b510 push {r4, lr}
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8000192: 4c05 ldr r4, [pc, #20] @ (80001a8 <__do_global_dtors_aux+0x18>)
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8000194: 7823 ldrb r3, [r4, #0]
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8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16>
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8000198: 4b04 ldr r3, [pc, #16] @ (80001ac <__do_global_dtors_aux+0x1c>)
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800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12>
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800019c: 4804 ldr r0, [pc, #16] @ (80001b0 <__do_global_dtors_aux+0x20>)
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800019e: f3af 8000 nop.w
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80001a2: 2301 movs r3, #1
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80001a4: 7023 strb r3, [r4, #0]
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80001a6: bd10 pop {r4, pc}
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80001a8: 2000029c .word 0x2000029c
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80001ac: 00000000 .word 0x00000000
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80001b0: 08013c78 .word 0x08013c78
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080001b4 <frame_dummy>:
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80001b4: b508 push {r3, lr}
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80001b6: 4b03 ldr r3, [pc, #12] @ (80001c4 <frame_dummy+0x10>)
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80001b8: b11b cbz r3, 80001c2 <frame_dummy+0xe>
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80001ba: 4903 ldr r1, [pc, #12] @ (80001c8 <frame_dummy+0x14>)
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80001bc: 4803 ldr r0, [pc, #12] @ (80001cc <frame_dummy+0x18>)
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80001be: f3af 8000 nop.w
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80001c2: bd08 pop {r3, pc}
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80001c4: 00000000 .word 0x00000000
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80001c8: 200002a0 .word 0x200002a0
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80001cc: 08013c78 .word 0x08013c78
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080001d0 <memchr>:
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80001d0: f001 01ff and.w r1, r1, #255 @ 0xff
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80001d4: 2a10 cmp r2, #16
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80001d6: db2b blt.n 8000230 <memchr+0x60>
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80001d8: f010 0f07 tst.w r0, #7
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80001dc: d008 beq.n 80001f0 <memchr+0x20>
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80001de: f810 3b01 ldrb.w r3, [r0], #1
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80001e2: 3a01 subs r2, #1
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80001e4: 428b cmp r3, r1
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80001e6: d02d beq.n 8000244 <memchr+0x74>
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80001e8: f010 0f07 tst.w r0, #7
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80001ec: b342 cbz r2, 8000240 <memchr+0x70>
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80001ee: d1f6 bne.n 80001de <memchr+0xe>
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80001f0: b4f0 push {r4, r5, r6, r7}
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80001f2: ea41 2101 orr.w r1, r1, r1, lsl #8
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80001f6: ea41 4101 orr.w r1, r1, r1, lsl #16
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80001fa: f022 0407 bic.w r4, r2, #7
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80001fe: f07f 0700 mvns.w r7, #0
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8000202: 2300 movs r3, #0
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8000204: e8f0 5602 ldrd r5, r6, [r0], #8
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8000208: 3c08 subs r4, #8
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800020a: ea85 0501 eor.w r5, r5, r1
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800020e: ea86 0601 eor.w r6, r6, r1
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8000212: fa85 f547 uadd8 r5, r5, r7
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8000216: faa3 f587 sel r5, r3, r7
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800021a: fa86 f647 uadd8 r6, r6, r7
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800021e: faa5 f687 sel r6, r5, r7
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8000222: b98e cbnz r6, 8000248 <memchr+0x78>
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8000224: d1ee bne.n 8000204 <memchr+0x34>
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8000226: bcf0 pop {r4, r5, r6, r7}
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8000228: f001 01ff and.w r1, r1, #255 @ 0xff
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800022c: f002 0207 and.w r2, r2, #7
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8000230: b132 cbz r2, 8000240 <memchr+0x70>
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8000232: f810 3b01 ldrb.w r3, [r0], #1
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8000236: 3a01 subs r2, #1
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8000238: ea83 0301 eor.w r3, r3, r1
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800023c: b113 cbz r3, 8000244 <memchr+0x74>
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800023e: d1f8 bne.n 8000232 <memchr+0x62>
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8000240: 2000 movs r0, #0
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8000242: 4770 bx lr
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8000244: 3801 subs r0, #1
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8000246: 4770 bx lr
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8000248: 2d00 cmp r5, #0
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800024a: bf06 itte eq
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800024c: 4635 moveq r5, r6
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800024e: 3803 subeq r0, #3
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8000250: 3807 subne r0, #7
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8000252: f015 0f01 tst.w r5, #1
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8000256: d107 bne.n 8000268 <memchr+0x98>
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8000258: 3001 adds r0, #1
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800025a: f415 7f80 tst.w r5, #256 @ 0x100
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800025e: bf02 ittt eq
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8000260: 3001 addeq r0, #1
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8000262: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
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8000266: 3001 addeq r0, #1
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8000268: bcf0 pop {r4, r5, r6, r7}
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800026a: 3801 subs r0, #1
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800026c: 4770 bx lr
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800026e: bf00 nop
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08000270 <strlen>:
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8000270: 4603 mov r3, r0
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8000272: f813 2b01 ldrb.w r2, [r3], #1
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8000276: 2a00 cmp r2, #0
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8000278: d1fb bne.n 8000272 <strlen+0x2>
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800027a: 1a18 subs r0, r3, r0
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800027c: 3801 subs r0, #1
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800027e: 4770 bx lr
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08000280 <__aeabi_drsub>:
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8000280: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
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8000284: e002 b.n 800028c <__adddf3>
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8000286: bf00 nop
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08000288 <__aeabi_dsub>:
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8000288: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
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0800028c <__adddf3>:
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800028c: b530 push {r4, r5, lr}
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800028e: ea4f 0441 mov.w r4, r1, lsl #1
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8000292: ea4f 0543 mov.w r5, r3, lsl #1
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8000296: ea94 0f05 teq r4, r5
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800029a: bf08 it eq
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800029c: ea90 0f02 teqeq r0, r2
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80002a0: bf1f itttt ne
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80002a2: ea54 0c00 orrsne.w ip, r4, r0
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80002a6: ea55 0c02 orrsne.w ip, r5, r2
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80002aa: ea7f 5c64 mvnsne.w ip, r4, asr #21
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80002ae: ea7f 5c65 mvnsne.w ip, r5, asr #21
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80002b2: f000 80e2 beq.w 800047a <__adddf3+0x1ee>
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80002b6: ea4f 5454 mov.w r4, r4, lsr #21
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80002ba: ebd4 5555 rsbs r5, r4, r5, lsr #21
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80002be: bfb8 it lt
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80002c0: 426d neglt r5, r5
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80002c2: dd0c ble.n 80002de <__adddf3+0x52>
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80002c4: 442c add r4, r5
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80002c6: ea80 0202 eor.w r2, r0, r2
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80002ca: ea81 0303 eor.w r3, r1, r3
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80002ce: ea82 0000 eor.w r0, r2, r0
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80002d2: ea83 0101 eor.w r1, r3, r1
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80002d6: ea80 0202 eor.w r2, r0, r2
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80002da: ea81 0303 eor.w r3, r1, r3
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80002de: 2d36 cmp r5, #54 @ 0x36
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80002e0: bf88 it hi
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80002e2: bd30 pophi {r4, r5, pc}
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80002e4: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
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80002e8: ea4f 3101 mov.w r1, r1, lsl #12
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80002ec: f44f 1c80 mov.w ip, #1048576 @ 0x100000
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80002f0: ea4c 3111 orr.w r1, ip, r1, lsr #12
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80002f4: d002 beq.n 80002fc <__adddf3+0x70>
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80002f6: 4240 negs r0, r0
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80002f8: eb61 0141 sbc.w r1, r1, r1, lsl #1
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80002fc: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
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8000300: ea4f 3303 mov.w r3, r3, lsl #12
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8000304: ea4c 3313 orr.w r3, ip, r3, lsr #12
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8000308: d002 beq.n 8000310 <__adddf3+0x84>
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800030a: 4252 negs r2, r2
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800030c: eb63 0343 sbc.w r3, r3, r3, lsl #1
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8000310: ea94 0f05 teq r4, r5
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8000314: f000 80a7 beq.w 8000466 <__adddf3+0x1da>
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8000318: f1a4 0401 sub.w r4, r4, #1
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800031c: f1d5 0e20 rsbs lr, r5, #32
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8000320: db0d blt.n 800033e <__adddf3+0xb2>
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8000322: fa02 fc0e lsl.w ip, r2, lr
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8000326: fa22 f205 lsr.w r2, r2, r5
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800032a: 1880 adds r0, r0, r2
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800032c: f141 0100 adc.w r1, r1, #0
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8000330: fa03 f20e lsl.w r2, r3, lr
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8000334: 1880 adds r0, r0, r2
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8000336: fa43 f305 asr.w r3, r3, r5
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800033a: 4159 adcs r1, r3
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800033c: e00e b.n 800035c <__adddf3+0xd0>
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800033e: f1a5 0520 sub.w r5, r5, #32
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8000342: f10e 0e20 add.w lr, lr, #32
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8000346: 2a01 cmp r2, #1
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8000348: fa03 fc0e lsl.w ip, r3, lr
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800034c: bf28 it cs
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800034e: f04c 0c02 orrcs.w ip, ip, #2
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8000352: fa43 f305 asr.w r3, r3, r5
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8000356: 18c0 adds r0, r0, r3
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8000358: eb51 71e3 adcs.w r1, r1, r3, asr #31
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800035c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
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8000360: d507 bpl.n 8000372 <__adddf3+0xe6>
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8000362: f04f 0e00 mov.w lr, #0
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8000366: f1dc 0c00 rsbs ip, ip, #0
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800036a: eb7e 0000 sbcs.w r0, lr, r0
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800036e: eb6e 0101 sbc.w r1, lr, r1
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8000372: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
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8000376: d31b bcc.n 80003b0 <__adddf3+0x124>
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8000378: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
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800037c: d30c bcc.n 8000398 <__adddf3+0x10c>
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800037e: 0849 lsrs r1, r1, #1
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8000380: ea5f 0030 movs.w r0, r0, rrx
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8000384: ea4f 0c3c mov.w ip, ip, rrx
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8000388: f104 0401 add.w r4, r4, #1
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800038c: ea4f 5244 mov.w r2, r4, lsl #21
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8000390: f512 0f80 cmn.w r2, #4194304 @ 0x400000
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8000394: f080 809a bcs.w 80004cc <__adddf3+0x240>
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8000398: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
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800039c: bf08 it eq
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800039e: ea5f 0c50 movseq.w ip, r0, lsr #1
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80003a2: f150 0000 adcs.w r0, r0, #0
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80003a6: eb41 5104 adc.w r1, r1, r4, lsl #20
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80003aa: ea41 0105 orr.w r1, r1, r5
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80003ae: bd30 pop {r4, r5, pc}
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80003b0: ea5f 0c4c movs.w ip, ip, lsl #1
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80003b4: 4140 adcs r0, r0
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80003b6: eb41 0101 adc.w r1, r1, r1
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80003ba: 3c01 subs r4, #1
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80003bc: bf28 it cs
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80003be: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
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80003c2: d2e9 bcs.n 8000398 <__adddf3+0x10c>
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80003c4: f091 0f00 teq r1, #0
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80003c8: bf04 itt eq
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80003ca: 4601 moveq r1, r0
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80003cc: 2000 moveq r0, #0
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80003ce: fab1 f381 clz r3, r1
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80003d2: bf08 it eq
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80003d4: 3320 addeq r3, #32
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80003d6: f1a3 030b sub.w r3, r3, #11
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80003da: f1b3 0220 subs.w r2, r3, #32
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80003de: da0c bge.n 80003fa <__adddf3+0x16e>
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80003e0: 320c adds r2, #12
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80003e2: dd08 ble.n 80003f6 <__adddf3+0x16a>
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80003e4: f102 0c14 add.w ip, r2, #20
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80003e8: f1c2 020c rsb r2, r2, #12
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80003ec: fa01 f00c lsl.w r0, r1, ip
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80003f0: fa21 f102 lsr.w r1, r1, r2
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80003f4: e00c b.n 8000410 <__adddf3+0x184>
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80003f6: f102 0214 add.w r2, r2, #20
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80003fa: bfd8 it le
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80003fc: f1c2 0c20 rsble ip, r2, #32
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8000400: fa01 f102 lsl.w r1, r1, r2
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8000404: fa20 fc0c lsr.w ip, r0, ip
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8000408: bfdc itt le
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800040a: ea41 010c orrle.w r1, r1, ip
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800040e: 4090 lslle r0, r2
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8000410: 1ae4 subs r4, r4, r3
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8000412: bfa2 ittt ge
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8000414: eb01 5104 addge.w r1, r1, r4, lsl #20
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8000418: 4329 orrge r1, r5
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800041a: bd30 popge {r4, r5, pc}
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800041c: ea6f 0404 mvn.w r4, r4
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8000420: 3c1f subs r4, #31
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8000422: da1c bge.n 800045e <__adddf3+0x1d2>
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8000424: 340c adds r4, #12
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8000426: dc0e bgt.n 8000446 <__adddf3+0x1ba>
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8000428: f104 0414 add.w r4, r4, #20
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800042c: f1c4 0220 rsb r2, r4, #32
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8000430: fa20 f004 lsr.w r0, r0, r4
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8000434: fa01 f302 lsl.w r3, r1, r2
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8000438: ea40 0003 orr.w r0, r0, r3
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800043c: fa21 f304 lsr.w r3, r1, r4
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8000440: ea45 0103 orr.w r1, r5, r3
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8000444: bd30 pop {r4, r5, pc}
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8000446: f1c4 040c rsb r4, r4, #12
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800044a: f1c4 0220 rsb r2, r4, #32
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800044e: fa20 f002 lsr.w r0, r0, r2
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8000452: fa01 f304 lsl.w r3, r1, r4
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8000456: ea40 0003 orr.w r0, r0, r3
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800045a: 4629 mov r1, r5
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800045c: bd30 pop {r4, r5, pc}
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800045e: fa21 f004 lsr.w r0, r1, r4
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8000462: 4629 mov r1, r5
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8000464: bd30 pop {r4, r5, pc}
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8000466: f094 0f00 teq r4, #0
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800046a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
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800046e: bf06 itte eq
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8000470: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
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8000474: 3401 addeq r4, #1
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8000476: 3d01 subne r5, #1
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8000478: e74e b.n 8000318 <__adddf3+0x8c>
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800047a: ea7f 5c64 mvns.w ip, r4, asr #21
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800047e: bf18 it ne
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8000480: ea7f 5c65 mvnsne.w ip, r5, asr #21
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8000484: d029 beq.n 80004da <__adddf3+0x24e>
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8000486: ea94 0f05 teq r4, r5
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800048a: bf08 it eq
|
|
800048c: ea90 0f02 teqeq r0, r2
|
|
8000490: d005 beq.n 800049e <__adddf3+0x212>
|
|
8000492: ea54 0c00 orrs.w ip, r4, r0
|
|
8000496: bf04 itt eq
|
|
8000498: 4619 moveq r1, r3
|
|
800049a: 4610 moveq r0, r2
|
|
800049c: bd30 pop {r4, r5, pc}
|
|
800049e: ea91 0f03 teq r1, r3
|
|
80004a2: bf1e ittt ne
|
|
80004a4: 2100 movne r1, #0
|
|
80004a6: 2000 movne r0, #0
|
|
80004a8: bd30 popne {r4, r5, pc}
|
|
80004aa: ea5f 5c54 movs.w ip, r4, lsr #21
|
|
80004ae: d105 bne.n 80004bc <__adddf3+0x230>
|
|
80004b0: 0040 lsls r0, r0, #1
|
|
80004b2: 4149 adcs r1, r1
|
|
80004b4: bf28 it cs
|
|
80004b6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
|
|
80004ba: bd30 pop {r4, r5, pc}
|
|
80004bc: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
|
|
80004c0: bf3c itt cc
|
|
80004c2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
|
|
80004c6: bd30 popcc {r4, r5, pc}
|
|
80004c8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
80004cc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
|
|
80004d0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
80004d4: f04f 0000 mov.w r0, #0
|
|
80004d8: bd30 pop {r4, r5, pc}
|
|
80004da: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
80004de: bf1a itte ne
|
|
80004e0: 4619 movne r1, r3
|
|
80004e2: 4610 movne r0, r2
|
|
80004e4: ea7f 5c65 mvnseq.w ip, r5, asr #21
|
|
80004e8: bf1c itt ne
|
|
80004ea: 460b movne r3, r1
|
|
80004ec: 4602 movne r2, r0
|
|
80004ee: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80004f2: bf06 itte eq
|
|
80004f4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
|
|
80004f8: ea91 0f03 teqeq r1, r3
|
|
80004fc: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
|
|
8000500: bd30 pop {r4, r5, pc}
|
|
8000502: bf00 nop
|
|
|
|
08000504 <__aeabi_ui2d>:
|
|
8000504: f090 0f00 teq r0, #0
|
|
8000508: bf04 itt eq
|
|
800050a: 2100 moveq r1, #0
|
|
800050c: 4770 bxeq lr
|
|
800050e: b530 push {r4, r5, lr}
|
|
8000510: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000514: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000518: f04f 0500 mov.w r5, #0
|
|
800051c: f04f 0100 mov.w r1, #0
|
|
8000520: e750 b.n 80003c4 <__adddf3+0x138>
|
|
8000522: bf00 nop
|
|
|
|
08000524 <__aeabi_i2d>:
|
|
8000524: f090 0f00 teq r0, #0
|
|
8000528: bf04 itt eq
|
|
800052a: 2100 moveq r1, #0
|
|
800052c: 4770 bxeq lr
|
|
800052e: b530 push {r4, r5, lr}
|
|
8000530: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000534: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000538: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
|
|
800053c: bf48 it mi
|
|
800053e: 4240 negmi r0, r0
|
|
8000540: f04f 0100 mov.w r1, #0
|
|
8000544: e73e b.n 80003c4 <__adddf3+0x138>
|
|
8000546: bf00 nop
|
|
|
|
08000548 <__aeabi_f2d>:
|
|
8000548: 0042 lsls r2, r0, #1
|
|
800054a: ea4f 01e2 mov.w r1, r2, asr #3
|
|
800054e: ea4f 0131 mov.w r1, r1, rrx
|
|
8000552: ea4f 7002 mov.w r0, r2, lsl #28
|
|
8000556: bf1f itttt ne
|
|
8000558: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
|
|
800055c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
|
|
8000560: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
|
|
8000564: 4770 bxne lr
|
|
8000566: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
|
|
800056a: bf08 it eq
|
|
800056c: 4770 bxeq lr
|
|
800056e: f093 4f7f teq r3, #4278190080 @ 0xff000000
|
|
8000572: bf04 itt eq
|
|
8000574: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
|
|
8000578: 4770 bxeq lr
|
|
800057a: b530 push {r4, r5, lr}
|
|
800057c: f44f 7460 mov.w r4, #896 @ 0x380
|
|
8000580: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
8000584: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000588: e71c b.n 80003c4 <__adddf3+0x138>
|
|
800058a: bf00 nop
|
|
|
|
0800058c <__aeabi_ul2d>:
|
|
800058c: ea50 0201 orrs.w r2, r0, r1
|
|
8000590: bf08 it eq
|
|
8000592: 4770 bxeq lr
|
|
8000594: b530 push {r4, r5, lr}
|
|
8000596: f04f 0500 mov.w r5, #0
|
|
800059a: e00a b.n 80005b2 <__aeabi_l2d+0x16>
|
|
|
|
0800059c <__aeabi_l2d>:
|
|
800059c: ea50 0201 orrs.w r2, r0, r1
|
|
80005a0: bf08 it eq
|
|
80005a2: 4770 bxeq lr
|
|
80005a4: b530 push {r4, r5, lr}
|
|
80005a6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
|
|
80005aa: d502 bpl.n 80005b2 <__aeabi_l2d+0x16>
|
|
80005ac: 4240 negs r0, r0
|
|
80005ae: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
80005b2: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80005b6: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80005ba: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
80005be: f43f aed8 beq.w 8000372 <__adddf3+0xe6>
|
|
80005c2: f04f 0203 mov.w r2, #3
|
|
80005c6: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005ca: bf18 it ne
|
|
80005cc: 3203 addne r2, #3
|
|
80005ce: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005d2: bf18 it ne
|
|
80005d4: 3203 addne r2, #3
|
|
80005d6: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
80005da: f1c2 0320 rsb r3, r2, #32
|
|
80005de: fa00 fc03 lsl.w ip, r0, r3
|
|
80005e2: fa20 f002 lsr.w r0, r0, r2
|
|
80005e6: fa01 fe03 lsl.w lr, r1, r3
|
|
80005ea: ea40 000e orr.w r0, r0, lr
|
|
80005ee: fa21 f102 lsr.w r1, r1, r2
|
|
80005f2: 4414 add r4, r2
|
|
80005f4: e6bd b.n 8000372 <__adddf3+0xe6>
|
|
80005f6: bf00 nop
|
|
|
|
080005f8 <__aeabi_dmul>:
|
|
80005f8: b570 push {r4, r5, r6, lr}
|
|
80005fa: f04f 0cff mov.w ip, #255 @ 0xff
|
|
80005fe: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000602: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
8000606: bf1d ittte ne
|
|
8000608: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
800060c: ea94 0f0c teqne r4, ip
|
|
8000610: ea95 0f0c teqne r5, ip
|
|
8000614: f000 f8de bleq 80007d4 <__aeabi_dmul+0x1dc>
|
|
8000618: 442c add r4, r5
|
|
800061a: ea81 0603 eor.w r6, r1, r3
|
|
800061e: ea21 514c bic.w r1, r1, ip, lsl #21
|
|
8000622: ea23 534c bic.w r3, r3, ip, lsl #21
|
|
8000626: ea50 3501 orrs.w r5, r0, r1, lsl #12
|
|
800062a: bf18 it ne
|
|
800062c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
|
|
8000630: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
8000634: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8000638: d038 beq.n 80006ac <__aeabi_dmul+0xb4>
|
|
800063a: fba0 ce02 umull ip, lr, r0, r2
|
|
800063e: f04f 0500 mov.w r5, #0
|
|
8000642: fbe1 e502 umlal lr, r5, r1, r2
|
|
8000646: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
|
|
800064a: fbe0 e503 umlal lr, r5, r0, r3
|
|
800064e: f04f 0600 mov.w r6, #0
|
|
8000652: fbe1 5603 umlal r5, r6, r1, r3
|
|
8000656: f09c 0f00 teq ip, #0
|
|
800065a: bf18 it ne
|
|
800065c: f04e 0e01 orrne.w lr, lr, #1
|
|
8000660: f1a4 04ff sub.w r4, r4, #255 @ 0xff
|
|
8000664: f5b6 7f00 cmp.w r6, #512 @ 0x200
|
|
8000668: f564 7440 sbc.w r4, r4, #768 @ 0x300
|
|
800066c: d204 bcs.n 8000678 <__aeabi_dmul+0x80>
|
|
800066e: ea5f 0e4e movs.w lr, lr, lsl #1
|
|
8000672: 416d adcs r5, r5
|
|
8000674: eb46 0606 adc.w r6, r6, r6
|
|
8000678: ea42 21c6 orr.w r1, r2, r6, lsl #11
|
|
800067c: ea41 5155 orr.w r1, r1, r5, lsr #21
|
|
8000680: ea4f 20c5 mov.w r0, r5, lsl #11
|
|
8000684: ea40 505e orr.w r0, r0, lr, lsr #21
|
|
8000688: ea4f 2ece mov.w lr, lr, lsl #11
|
|
800068c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
8000690: bf88 it hi
|
|
8000692: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000696: d81e bhi.n 80006d6 <__aeabi_dmul+0xde>
|
|
8000698: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
|
|
800069c: bf08 it eq
|
|
800069e: ea5f 0e50 movseq.w lr, r0, lsr #1
|
|
80006a2: f150 0000 adcs.w r0, r0, #0
|
|
80006a6: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
80006aa: bd70 pop {r4, r5, r6, pc}
|
|
80006ac: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
|
|
80006b0: ea46 0101 orr.w r1, r6, r1
|
|
80006b4: ea40 0002 orr.w r0, r0, r2
|
|
80006b8: ea81 0103 eor.w r1, r1, r3
|
|
80006bc: ebb4 045c subs.w r4, r4, ip, lsr #1
|
|
80006c0: bfc2 ittt gt
|
|
80006c2: ebd4 050c rsbsgt r5, r4, ip
|
|
80006c6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80006ca: bd70 popgt {r4, r5, r6, pc}
|
|
80006cc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80006d0: f04f 0e00 mov.w lr, #0
|
|
80006d4: 3c01 subs r4, #1
|
|
80006d6: f300 80ab bgt.w 8000830 <__aeabi_dmul+0x238>
|
|
80006da: f114 0f36 cmn.w r4, #54 @ 0x36
|
|
80006de: bfde ittt le
|
|
80006e0: 2000 movle r0, #0
|
|
80006e2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
|
|
80006e6: bd70 pople {r4, r5, r6, pc}
|
|
80006e8: f1c4 0400 rsb r4, r4, #0
|
|
80006ec: 3c20 subs r4, #32
|
|
80006ee: da35 bge.n 800075c <__aeabi_dmul+0x164>
|
|
80006f0: 340c adds r4, #12
|
|
80006f2: dc1b bgt.n 800072c <__aeabi_dmul+0x134>
|
|
80006f4: f104 0414 add.w r4, r4, #20
|
|
80006f8: f1c4 0520 rsb r5, r4, #32
|
|
80006fc: fa00 f305 lsl.w r3, r0, r5
|
|
8000700: fa20 f004 lsr.w r0, r0, r4
|
|
8000704: fa01 f205 lsl.w r2, r1, r5
|
|
8000708: ea40 0002 orr.w r0, r0, r2
|
|
800070c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
|
|
8000710: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
8000718: fa21 f604 lsr.w r6, r1, r4
|
|
800071c: eb42 0106 adc.w r1, r2, r6
|
|
8000720: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000724: bf08 it eq
|
|
8000726: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800072a: bd70 pop {r4, r5, r6, pc}
|
|
800072c: f1c4 040c rsb r4, r4, #12
|
|
8000730: f1c4 0520 rsb r5, r4, #32
|
|
8000734: fa00 f304 lsl.w r3, r0, r4
|
|
8000738: fa20 f005 lsr.w r0, r0, r5
|
|
800073c: fa01 f204 lsl.w r2, r1, r4
|
|
8000740: ea40 0002 orr.w r0, r0, r2
|
|
8000744: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
8000748: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
800074c: f141 0100 adc.w r1, r1, #0
|
|
8000750: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000754: bf08 it eq
|
|
8000756: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800075a: bd70 pop {r4, r5, r6, pc}
|
|
800075c: f1c4 0520 rsb r5, r4, #32
|
|
8000760: fa00 f205 lsl.w r2, r0, r5
|
|
8000764: ea4e 0e02 orr.w lr, lr, r2
|
|
8000768: fa20 f304 lsr.w r3, r0, r4
|
|
800076c: fa01 f205 lsl.w r2, r1, r5
|
|
8000770: ea43 0302 orr.w r3, r3, r2
|
|
8000774: fa21 f004 lsr.w r0, r1, r4
|
|
8000778: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
800077c: fa21 f204 lsr.w r2, r1, r4
|
|
8000780: ea20 0002 bic.w r0, r0, r2
|
|
8000784: eb00 70d3 add.w r0, r0, r3, lsr #31
|
|
8000788: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
800078c: bf08 it eq
|
|
800078e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
8000792: bd70 pop {r4, r5, r6, pc}
|
|
8000794: f094 0f00 teq r4, #0
|
|
8000798: d10f bne.n 80007ba <__aeabi_dmul+0x1c2>
|
|
800079a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
|
|
800079e: 0040 lsls r0, r0, #1
|
|
80007a0: eb41 0101 adc.w r1, r1, r1
|
|
80007a4: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
80007a8: bf08 it eq
|
|
80007aa: 3c01 subeq r4, #1
|
|
80007ac: d0f7 beq.n 800079e <__aeabi_dmul+0x1a6>
|
|
80007ae: ea41 0106 orr.w r1, r1, r6
|
|
80007b2: f095 0f00 teq r5, #0
|
|
80007b6: bf18 it ne
|
|
80007b8: 4770 bxne lr
|
|
80007ba: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
|
|
80007be: 0052 lsls r2, r2, #1
|
|
80007c0: eb43 0303 adc.w r3, r3, r3
|
|
80007c4: f413 1f80 tst.w r3, #1048576 @ 0x100000
|
|
80007c8: bf08 it eq
|
|
80007ca: 3d01 subeq r5, #1
|
|
80007cc: d0f7 beq.n 80007be <__aeabi_dmul+0x1c6>
|
|
80007ce: ea43 0306 orr.w r3, r3, r6
|
|
80007d2: 4770 bx lr
|
|
80007d4: ea94 0f0c teq r4, ip
|
|
80007d8: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80007dc: bf18 it ne
|
|
80007de: ea95 0f0c teqne r5, ip
|
|
80007e2: d00c beq.n 80007fe <__aeabi_dmul+0x206>
|
|
80007e4: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
80007e8: bf18 it ne
|
|
80007ea: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
80007ee: d1d1 bne.n 8000794 <__aeabi_dmul+0x19c>
|
|
80007f0: ea81 0103 eor.w r1, r1, r3
|
|
80007f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
80007f8: f04f 0000 mov.w r0, #0
|
|
80007fc: bd70 pop {r4, r5, r6, pc}
|
|
80007fe: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000802: bf06 itte eq
|
|
8000804: 4610 moveq r0, r2
|
|
8000806: 4619 moveq r1, r3
|
|
8000808: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
800080c: d019 beq.n 8000842 <__aeabi_dmul+0x24a>
|
|
800080e: ea94 0f0c teq r4, ip
|
|
8000812: d102 bne.n 800081a <__aeabi_dmul+0x222>
|
|
8000814: ea50 3601 orrs.w r6, r0, r1, lsl #12
|
|
8000818: d113 bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800081a: ea95 0f0c teq r5, ip
|
|
800081e: d105 bne.n 800082c <__aeabi_dmul+0x234>
|
|
8000820: ea52 3603 orrs.w r6, r2, r3, lsl #12
|
|
8000824: bf1c itt ne
|
|
8000826: 4610 movne r0, r2
|
|
8000828: 4619 movne r1, r3
|
|
800082a: d10a bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800082c: ea81 0103 eor.w r1, r1, r3
|
|
8000830: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
8000834: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
8000838: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
800083c: f04f 0000 mov.w r0, #0
|
|
8000840: bd70 pop {r4, r5, r6, pc}
|
|
8000842: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
8000846: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
|
|
800084a: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0800084c <__aeabi_ddiv>:
|
|
800084c: b570 push {r4, r5, r6, lr}
|
|
800084e: f04f 0cff mov.w ip, #255 @ 0xff
|
|
8000852: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000856: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
800085a: bf1d ittte ne
|
|
800085c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
8000860: ea94 0f0c teqne r4, ip
|
|
8000864: ea95 0f0c teqne r5, ip
|
|
8000868: f000 f8a7 bleq 80009ba <__aeabi_ddiv+0x16e>
|
|
800086c: eba4 0405 sub.w r4, r4, r5
|
|
8000870: ea81 0e03 eor.w lr, r1, r3
|
|
8000874: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
8000878: ea4f 3101 mov.w r1, r1, lsl #12
|
|
800087c: f000 8088 beq.w 8000990 <__aeabi_ddiv+0x144>
|
|
8000880: ea4f 3303 mov.w r3, r3, lsl #12
|
|
8000884: f04f 5580 mov.w r5, #268435456 @ 0x10000000
|
|
8000888: ea45 1313 orr.w r3, r5, r3, lsr #4
|
|
800088c: ea43 6312 orr.w r3, r3, r2, lsr #24
|
|
8000890: ea4f 2202 mov.w r2, r2, lsl #8
|
|
8000894: ea45 1511 orr.w r5, r5, r1, lsr #4
|
|
8000898: ea45 6510 orr.w r5, r5, r0, lsr #24
|
|
800089c: ea4f 2600 mov.w r6, r0, lsl #8
|
|
80008a0: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
|
|
80008a4: 429d cmp r5, r3
|
|
80008a6: bf08 it eq
|
|
80008a8: 4296 cmpeq r6, r2
|
|
80008aa: f144 04fd adc.w r4, r4, #253 @ 0xfd
|
|
80008ae: f504 7440 add.w r4, r4, #768 @ 0x300
|
|
80008b2: d202 bcs.n 80008ba <__aeabi_ddiv+0x6e>
|
|
80008b4: 085b lsrs r3, r3, #1
|
|
80008b6: ea4f 0232 mov.w r2, r2, rrx
|
|
80008ba: 1ab6 subs r6, r6, r2
|
|
80008bc: eb65 0503 sbc.w r5, r5, r3
|
|
80008c0: 085b lsrs r3, r3, #1
|
|
80008c2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008c6: f44f 1080 mov.w r0, #1048576 @ 0x100000
|
|
80008ca: f44f 2c00 mov.w ip, #524288 @ 0x80000
|
|
80008ce: ebb6 0e02 subs.w lr, r6, r2
|
|
80008d2: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008d6: bf22 ittt cs
|
|
80008d8: 1ab6 subcs r6, r6, r2
|
|
80008da: 4675 movcs r5, lr
|
|
80008dc: ea40 000c orrcs.w r0, r0, ip
|
|
80008e0: 085b lsrs r3, r3, #1
|
|
80008e2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008e6: ebb6 0e02 subs.w lr, r6, r2
|
|
80008ea: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008ee: bf22 ittt cs
|
|
80008f0: 1ab6 subcs r6, r6, r2
|
|
80008f2: 4675 movcs r5, lr
|
|
80008f4: ea40 005c orrcs.w r0, r0, ip, lsr #1
|
|
80008f8: 085b lsrs r3, r3, #1
|
|
80008fa: ea4f 0232 mov.w r2, r2, rrx
|
|
80008fe: ebb6 0e02 subs.w lr, r6, r2
|
|
8000902: eb75 0e03 sbcs.w lr, r5, r3
|
|
8000906: bf22 ittt cs
|
|
8000908: 1ab6 subcs r6, r6, r2
|
|
800090a: 4675 movcs r5, lr
|
|
800090c: ea40 009c orrcs.w r0, r0, ip, lsr #2
|
|
8000910: 085b lsrs r3, r3, #1
|
|
8000912: ea4f 0232 mov.w r2, r2, rrx
|
|
8000916: ebb6 0e02 subs.w lr, r6, r2
|
|
800091a: eb75 0e03 sbcs.w lr, r5, r3
|
|
800091e: bf22 ittt cs
|
|
8000920: 1ab6 subcs r6, r6, r2
|
|
8000922: 4675 movcs r5, lr
|
|
8000924: ea40 00dc orrcs.w r0, r0, ip, lsr #3
|
|
8000928: ea55 0e06 orrs.w lr, r5, r6
|
|
800092c: d018 beq.n 8000960 <__aeabi_ddiv+0x114>
|
|
800092e: ea4f 1505 mov.w r5, r5, lsl #4
|
|
8000932: ea45 7516 orr.w r5, r5, r6, lsr #28
|
|
8000936: ea4f 1606 mov.w r6, r6, lsl #4
|
|
800093a: ea4f 03c3 mov.w r3, r3, lsl #3
|
|
800093e: ea43 7352 orr.w r3, r3, r2, lsr #29
|
|
8000942: ea4f 02c2 mov.w r2, r2, lsl #3
|
|
8000946: ea5f 1c1c movs.w ip, ip, lsr #4
|
|
800094a: d1c0 bne.n 80008ce <__aeabi_ddiv+0x82>
|
|
800094c: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000950: d10b bne.n 800096a <__aeabi_ddiv+0x11e>
|
|
8000952: ea41 0100 orr.w r1, r1, r0
|
|
8000956: f04f 0000 mov.w r0, #0
|
|
800095a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
|
|
800095e: e7b6 b.n 80008ce <__aeabi_ddiv+0x82>
|
|
8000960: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000964: bf04 itt eq
|
|
8000966: 4301 orreq r1, r0
|
|
8000968: 2000 moveq r0, #0
|
|
800096a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
800096e: bf88 it hi
|
|
8000970: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000974: f63f aeaf bhi.w 80006d6 <__aeabi_dmul+0xde>
|
|
8000978: ebb5 0c03 subs.w ip, r5, r3
|
|
800097c: bf04 itt eq
|
|
800097e: ebb6 0c02 subseq.w ip, r6, r2
|
|
8000982: ea5f 0c50 movseq.w ip, r0, lsr #1
|
|
8000986: f150 0000 adcs.w r0, r0, #0
|
|
800098a: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
800098e: bd70 pop {r4, r5, r6, pc}
|
|
8000990: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
|
|
8000994: ea4e 3111 orr.w r1, lr, r1, lsr #12
|
|
8000998: eb14 045c adds.w r4, r4, ip, lsr #1
|
|
800099c: bfc2 ittt gt
|
|
800099e: ebd4 050c rsbsgt r5, r4, ip
|
|
80009a2: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80009a6: bd70 popgt {r4, r5, r6, pc}
|
|
80009a8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80009ac: f04f 0e00 mov.w lr, #0
|
|
80009b0: 3c01 subs r4, #1
|
|
80009b2: e690 b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009b4: ea45 0e06 orr.w lr, r5, r6
|
|
80009b8: e68d b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009ba: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80009be: ea94 0f0c teq r4, ip
|
|
80009c2: bf08 it eq
|
|
80009c4: ea95 0f0c teqeq r5, ip
|
|
80009c8: f43f af3b beq.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009cc: ea94 0f0c teq r4, ip
|
|
80009d0: d10a bne.n 80009e8 <__aeabi_ddiv+0x19c>
|
|
80009d2: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80009d6: f47f af34 bne.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009da: ea95 0f0c teq r5, ip
|
|
80009de: f47f af25 bne.w 800082c <__aeabi_dmul+0x234>
|
|
80009e2: 4610 mov r0, r2
|
|
80009e4: 4619 mov r1, r3
|
|
80009e6: e72c b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009e8: ea95 0f0c teq r5, ip
|
|
80009ec: d106 bne.n 80009fc <__aeabi_ddiv+0x1b0>
|
|
80009ee: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
80009f2: f43f aefd beq.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
80009f6: 4610 mov r0, r2
|
|
80009f8: 4619 mov r1, r3
|
|
80009fa: e722 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009fc: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000a00: bf18 it ne
|
|
8000a02: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
8000a06: f47f aec5 bne.w 8000794 <__aeabi_dmul+0x19c>
|
|
8000a0a: ea50 0441 orrs.w r4, r0, r1, lsl #1
|
|
8000a0e: f47f af0d bne.w 800082c <__aeabi_dmul+0x234>
|
|
8000a12: ea52 0543 orrs.w r5, r2, r3, lsl #1
|
|
8000a16: f47f aeeb bne.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
8000a1a: e712 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
|
|
08000a1c <__gedf2>:
|
|
8000a1c: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff
|
|
8000a20: e006 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a22: bf00 nop
|
|
|
|
08000a24 <__ledf2>:
|
|
8000a24: f04f 0c01 mov.w ip, #1
|
|
8000a28: e002 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a2a: bf00 nop
|
|
|
|
08000a2c <__cmpdf2>:
|
|
8000a2c: f04f 0c01 mov.w ip, #1
|
|
8000a30: f84d cd04 str.w ip, [sp, #-4]!
|
|
8000a34: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a38: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a40: bf18 it ne
|
|
8000a42: ea7f 5c6c mvnsne.w ip, ip, asr #21
|
|
8000a46: d01b beq.n 8000a80 <__cmpdf2+0x54>
|
|
8000a48: b001 add sp, #4
|
|
8000a4a: ea50 0c41 orrs.w ip, r0, r1, lsl #1
|
|
8000a4e: bf0c ite eq
|
|
8000a50: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
|
|
8000a54: ea91 0f03 teqne r1, r3
|
|
8000a58: bf02 ittt eq
|
|
8000a5a: ea90 0f02 teqeq r0, r2
|
|
8000a5e: 2000 moveq r0, #0
|
|
8000a60: 4770 bxeq lr
|
|
8000a62: f110 0f00 cmn.w r0, #0
|
|
8000a66: ea91 0f03 teq r1, r3
|
|
8000a6a: bf58 it pl
|
|
8000a6c: 4299 cmppl r1, r3
|
|
8000a6e: bf08 it eq
|
|
8000a70: 4290 cmpeq r0, r2
|
|
8000a72: bf2c ite cs
|
|
8000a74: 17d8 asrcs r0, r3, #31
|
|
8000a76: ea6f 70e3 mvncc.w r0, r3, asr #31
|
|
8000a7a: f040 0001 orr.w r0, r0, #1
|
|
8000a7e: 4770 bx lr
|
|
8000a80: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a84: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a88: d102 bne.n 8000a90 <__cmpdf2+0x64>
|
|
8000a8a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000a8e: d107 bne.n 8000aa0 <__cmpdf2+0x74>
|
|
8000a90: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a94: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a98: d1d6 bne.n 8000a48 <__cmpdf2+0x1c>
|
|
8000a9a: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000a9e: d0d3 beq.n 8000a48 <__cmpdf2+0x1c>
|
|
8000aa0: f85d 0b04 ldr.w r0, [sp], #4
|
|
8000aa4: 4770 bx lr
|
|
8000aa6: bf00 nop
|
|
|
|
08000aa8 <__aeabi_cdrcmple>:
|
|
8000aa8: 4684 mov ip, r0
|
|
8000aaa: 4610 mov r0, r2
|
|
8000aac: 4662 mov r2, ip
|
|
8000aae: 468c mov ip, r1
|
|
8000ab0: 4619 mov r1, r3
|
|
8000ab2: 4663 mov r3, ip
|
|
8000ab4: e000 b.n 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ab6: bf00 nop
|
|
|
|
08000ab8 <__aeabi_cdcmpeq>:
|
|
8000ab8: b501 push {r0, lr}
|
|
8000aba: f7ff ffb7 bl 8000a2c <__cmpdf2>
|
|
8000abe: 2800 cmp r0, #0
|
|
8000ac0: bf48 it mi
|
|
8000ac2: f110 0f00 cmnmi.w r0, #0
|
|
8000ac6: bd01 pop {r0, pc}
|
|
|
|
08000ac8 <__aeabi_dcmpeq>:
|
|
8000ac8: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000acc: f7ff fff4 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ad0: bf0c ite eq
|
|
8000ad2: 2001 moveq r0, #1
|
|
8000ad4: 2000 movne r0, #0
|
|
8000ad6: f85d fb08 ldr.w pc, [sp], #8
|
|
8000ada: bf00 nop
|
|
|
|
08000adc <__aeabi_dcmplt>:
|
|
8000adc: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000ae0: f7ff ffea bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ae4: bf34 ite cc
|
|
8000ae6: 2001 movcc r0, #1
|
|
8000ae8: 2000 movcs r0, #0
|
|
8000aea: f85d fb08 ldr.w pc, [sp], #8
|
|
8000aee: bf00 nop
|
|
|
|
08000af0 <__aeabi_dcmple>:
|
|
8000af0: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000af4: f7ff ffe0 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000af8: bf94 ite ls
|
|
8000afa: 2001 movls r0, #1
|
|
8000afc: 2000 movhi r0, #0
|
|
8000afe: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b02: bf00 nop
|
|
|
|
08000b04 <__aeabi_dcmpge>:
|
|
8000b04: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b08: f7ff ffce bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b0c: bf94 ite ls
|
|
8000b0e: 2001 movls r0, #1
|
|
8000b10: 2000 movhi r0, #0
|
|
8000b12: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b16: bf00 nop
|
|
|
|
08000b18 <__aeabi_dcmpgt>:
|
|
8000b18: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b1c: f7ff ffc4 bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b20: bf34 ite cc
|
|
8000b22: 2001 movcc r0, #1
|
|
8000b24: 2000 movcs r0, #0
|
|
8000b26: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b2a: bf00 nop
|
|
|
|
08000b2c <__aeabi_dcmpun>:
|
|
8000b2c: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000b30: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b34: d102 bne.n 8000b3c <__aeabi_dcmpun+0x10>
|
|
8000b36: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000b3a: d10a bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000b40: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x20>
|
|
8000b46: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000b4a: d102 bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b4c: f04f 0000 mov.w r0, #0
|
|
8000b50: 4770 bx lr
|
|
8000b52: f04f 0001 mov.w r0, #1
|
|
8000b56: 4770 bx lr
|
|
|
|
08000b58 <__aeabi_d2iz>:
|
|
8000b58: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
8000b60: d215 bcs.n 8000b8e <__aeabi_d2iz+0x36>
|
|
8000b62: d511 bpl.n 8000b88 <__aeabi_d2iz+0x30>
|
|
8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
8000b6c: d912 bls.n 8000b94 <__aeabi_d2iz+0x3c>
|
|
8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
8000b7a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
|
|
8000b7e: fa23 f002 lsr.w r0, r3, r2
|
|
8000b82: bf18 it ne
|
|
8000b84: 4240 negne r0, r0
|
|
8000b86: 4770 bx lr
|
|
8000b88: f04f 0000 mov.w r0, #0
|
|
8000b8c: 4770 bx lr
|
|
8000b8e: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000b92: d105 bne.n 8000ba0 <__aeabi_d2iz+0x48>
|
|
8000b94: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
|
|
8000b98: bf08 it eq
|
|
8000b9a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
|
|
8000b9e: 4770 bx lr
|
|
8000ba0: f04f 0000 mov.w r0, #0
|
|
8000ba4: 4770 bx lr
|
|
8000ba6: bf00 nop
|
|
|
|
08000ba8 <__aeabi_d2uiz>:
|
|
8000ba8: 004a lsls r2, r1, #1
|
|
8000baa: d211 bcs.n 8000bd0 <__aeabi_d2uiz+0x28>
|
|
8000bac: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
8000bb0: d211 bcs.n 8000bd6 <__aeabi_d2uiz+0x2e>
|
|
8000bb2: d50d bpl.n 8000bd0 <__aeabi_d2uiz+0x28>
|
|
8000bb4: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
8000bb8: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
8000bbc: d40e bmi.n 8000bdc <__aeabi_d2uiz+0x34>
|
|
8000bbe: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000bc2: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000bc6: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
8000bca: fa23 f002 lsr.w r0, r3, r2
|
|
8000bce: 4770 bx lr
|
|
8000bd0: f04f 0000 mov.w r0, #0
|
|
8000bd4: 4770 bx lr
|
|
8000bd6: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000bda: d102 bne.n 8000be2 <__aeabi_d2uiz+0x3a>
|
|
8000bdc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8000be0: 4770 bx lr
|
|
8000be2: f04f 0000 mov.w r0, #0
|
|
8000be6: 4770 bx lr
|
|
|
|
08000be8 <__aeabi_d2f>:
|
|
8000be8: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000bec: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000
|
|
8000bf0: bf24 itt cs
|
|
8000bf2: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000
|
|
8000bf6: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000
|
|
8000bfa: d90d bls.n 8000c18 <__aeabi_d2f+0x30>
|
|
8000bfc: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
|
|
8000c00: ea4f 02c0 mov.w r2, r0, lsl #3
|
|
8000c04: ea4c 7050 orr.w r0, ip, r0, lsr #29
|
|
8000c08: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000
|
|
8000c0c: eb40 0083 adc.w r0, r0, r3, lsl #2
|
|
8000c10: bf08 it eq
|
|
8000c12: f020 0001 biceq.w r0, r0, #1
|
|
8000c16: 4770 bx lr
|
|
8000c18: f011 4f80 tst.w r1, #1073741824 @ 0x40000000
|
|
8000c1c: d121 bne.n 8000c62 <__aeabi_d2f+0x7a>
|
|
8000c1e: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000
|
|
8000c22: bfbc itt lt
|
|
8000c24: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000
|
|
8000c28: 4770 bxlt lr
|
|
8000c2a: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
8000c2e: ea4f 5252 mov.w r2, r2, lsr #21
|
|
8000c32: f1c2 0218 rsb r2, r2, #24
|
|
8000c36: f1c2 0c20 rsb ip, r2, #32
|
|
8000c3a: fa10 f30c lsls.w r3, r0, ip
|
|
8000c3e: fa20 f002 lsr.w r0, r0, r2
|
|
8000c42: bf18 it ne
|
|
8000c44: f040 0001 orrne.w r0, r0, #1
|
|
8000c48: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000c4c: ea4f 23d3 mov.w r3, r3, lsr #11
|
|
8000c50: fa03 fc0c lsl.w ip, r3, ip
|
|
8000c54: ea40 000c orr.w r0, r0, ip
|
|
8000c58: fa23 f302 lsr.w r3, r3, r2
|
|
8000c5c: ea4f 0343 mov.w r3, r3, lsl #1
|
|
8000c60: e7cc b.n 8000bfc <__aeabi_d2f+0x14>
|
|
8000c62: ea7f 5362 mvns.w r3, r2, asr #21
|
|
8000c66: d107 bne.n 8000c78 <__aeabi_d2f+0x90>
|
|
8000c68: ea50 3301 orrs.w r3, r0, r1, lsl #12
|
|
8000c6c: bf1e ittt ne
|
|
8000c6e: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000
|
|
8000c72: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000
|
|
8000c76: 4770 bxne lr
|
|
8000c78: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000
|
|
8000c7c: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
|
|
8000c80: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
|
|
8000c84: 4770 bx lr
|
|
8000c86: bf00 nop
|
|
|
|
08000c88 <__aeabi_uldivmod>:
|
|
8000c88: b953 cbnz r3, 8000ca0 <__aeabi_uldivmod+0x18>
|
|
8000c8a: b94a cbnz r2, 8000ca0 <__aeabi_uldivmod+0x18>
|
|
8000c8c: 2900 cmp r1, #0
|
|
8000c8e: bf08 it eq
|
|
8000c90: 2800 cmpeq r0, #0
|
|
8000c92: bf1c itt ne
|
|
8000c94: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
|
|
8000c98: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
|
|
8000c9c: f000 b9be b.w 800101c <__aeabi_idiv0>
|
|
8000ca0: f1ad 0c08 sub.w ip, sp, #8
|
|
8000ca4: e96d ce04 strd ip, lr, [sp, #-16]!
|
|
8000ca8: f000 f83c bl 8000d24 <__udivmoddi4>
|
|
8000cac: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000cb0: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000cb4: b004 add sp, #16
|
|
8000cb6: 4770 bx lr
|
|
|
|
08000cb8 <__aeabi_d2lz>:
|
|
8000cb8: b538 push {r3, r4, r5, lr}
|
|
8000cba: 2200 movs r2, #0
|
|
8000cbc: 2300 movs r3, #0
|
|
8000cbe: 4604 mov r4, r0
|
|
8000cc0: 460d mov r5, r1
|
|
8000cc2: f7ff ff0b bl 8000adc <__aeabi_dcmplt>
|
|
8000cc6: b928 cbnz r0, 8000cd4 <__aeabi_d2lz+0x1c>
|
|
8000cc8: 4620 mov r0, r4
|
|
8000cca: 4629 mov r1, r5
|
|
8000ccc: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8000cd0: f000 b80a b.w 8000ce8 <__aeabi_d2ulz>
|
|
8000cd4: 4620 mov r0, r4
|
|
8000cd6: f105 4100 add.w r1, r5, #2147483648 @ 0x80000000
|
|
8000cda: f000 f805 bl 8000ce8 <__aeabi_d2ulz>
|
|
8000cde: 4240 negs r0, r0
|
|
8000ce0: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
8000ce4: bd38 pop {r3, r4, r5, pc}
|
|
8000ce6: bf00 nop
|
|
|
|
08000ce8 <__aeabi_d2ulz>:
|
|
8000ce8: b5d0 push {r4, r6, r7, lr}
|
|
8000cea: 4b0c ldr r3, [pc, #48] @ (8000d1c <__aeabi_d2ulz+0x34>)
|
|
8000cec: 2200 movs r2, #0
|
|
8000cee: 4606 mov r6, r0
|
|
8000cf0: 460f mov r7, r1
|
|
8000cf2: f7ff fc81 bl 80005f8 <__aeabi_dmul>
|
|
8000cf6: f7ff ff57 bl 8000ba8 <__aeabi_d2uiz>
|
|
8000cfa: 4604 mov r4, r0
|
|
8000cfc: f7ff fc02 bl 8000504 <__aeabi_ui2d>
|
|
8000d00: 4b07 ldr r3, [pc, #28] @ (8000d20 <__aeabi_d2ulz+0x38>)
|
|
8000d02: 2200 movs r2, #0
|
|
8000d04: f7ff fc78 bl 80005f8 <__aeabi_dmul>
|
|
8000d08: 4602 mov r2, r0
|
|
8000d0a: 460b mov r3, r1
|
|
8000d0c: 4630 mov r0, r6
|
|
8000d0e: 4639 mov r1, r7
|
|
8000d10: f7ff faba bl 8000288 <__aeabi_dsub>
|
|
8000d14: f7ff ff48 bl 8000ba8 <__aeabi_d2uiz>
|
|
8000d18: 4621 mov r1, r4
|
|
8000d1a: bdd0 pop {r4, r6, r7, pc}
|
|
8000d1c: 3df00000 .word 0x3df00000
|
|
8000d20: 41f00000 .word 0x41f00000
|
|
|
|
08000d24 <__udivmoddi4>:
|
|
8000d24: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8000d28: 9d08 ldr r5, [sp, #32]
|
|
8000d2a: 468e mov lr, r1
|
|
8000d2c: 4604 mov r4, r0
|
|
8000d2e: 4688 mov r8, r1
|
|
8000d30: 2b00 cmp r3, #0
|
|
8000d32: d14a bne.n 8000dca <__udivmoddi4+0xa6>
|
|
8000d34: 428a cmp r2, r1
|
|
8000d36: 4617 mov r7, r2
|
|
8000d38: d962 bls.n 8000e00 <__udivmoddi4+0xdc>
|
|
8000d3a: fab2 f682 clz r6, r2
|
|
8000d3e: b14e cbz r6, 8000d54 <__udivmoddi4+0x30>
|
|
8000d40: f1c6 0320 rsb r3, r6, #32
|
|
8000d44: fa01 f806 lsl.w r8, r1, r6
|
|
8000d48: fa20 f303 lsr.w r3, r0, r3
|
|
8000d4c: 40b7 lsls r7, r6
|
|
8000d4e: ea43 0808 orr.w r8, r3, r8
|
|
8000d52: 40b4 lsls r4, r6
|
|
8000d54: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000d58: fa1f fc87 uxth.w ip, r7
|
|
8000d5c: fbb8 f1fe udiv r1, r8, lr
|
|
8000d60: 0c23 lsrs r3, r4, #16
|
|
8000d62: fb0e 8811 mls r8, lr, r1, r8
|
|
8000d66: ea43 4308 orr.w r3, r3, r8, lsl #16
|
|
8000d6a: fb01 f20c mul.w r2, r1, ip
|
|
8000d6e: 429a cmp r2, r3
|
|
8000d70: d909 bls.n 8000d86 <__udivmoddi4+0x62>
|
|
8000d72: 18fb adds r3, r7, r3
|
|
8000d74: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
|
|
8000d78: f080 80ea bcs.w 8000f50 <__udivmoddi4+0x22c>
|
|
8000d7c: 429a cmp r2, r3
|
|
8000d7e: f240 80e7 bls.w 8000f50 <__udivmoddi4+0x22c>
|
|
8000d82: 3902 subs r1, #2
|
|
8000d84: 443b add r3, r7
|
|
8000d86: 1a9a subs r2, r3, r2
|
|
8000d88: b2a3 uxth r3, r4
|
|
8000d8a: fbb2 f0fe udiv r0, r2, lr
|
|
8000d8e: fb0e 2210 mls r2, lr, r0, r2
|
|
8000d92: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8000d96: fb00 fc0c mul.w ip, r0, ip
|
|
8000d9a: 459c cmp ip, r3
|
|
8000d9c: d909 bls.n 8000db2 <__udivmoddi4+0x8e>
|
|
8000d9e: 18fb adds r3, r7, r3
|
|
8000da0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
|
|
8000da4: f080 80d6 bcs.w 8000f54 <__udivmoddi4+0x230>
|
|
8000da8: 459c cmp ip, r3
|
|
8000daa: f240 80d3 bls.w 8000f54 <__udivmoddi4+0x230>
|
|
8000dae: 443b add r3, r7
|
|
8000db0: 3802 subs r0, #2
|
|
8000db2: ea40 4001 orr.w r0, r0, r1, lsl #16
|
|
8000db6: eba3 030c sub.w r3, r3, ip
|
|
8000dba: 2100 movs r1, #0
|
|
8000dbc: b11d cbz r5, 8000dc6 <__udivmoddi4+0xa2>
|
|
8000dbe: 40f3 lsrs r3, r6
|
|
8000dc0: 2200 movs r2, #0
|
|
8000dc2: e9c5 3200 strd r3, r2, [r5]
|
|
8000dc6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8000dca: 428b cmp r3, r1
|
|
8000dcc: d905 bls.n 8000dda <__udivmoddi4+0xb6>
|
|
8000dce: b10d cbz r5, 8000dd4 <__udivmoddi4+0xb0>
|
|
8000dd0: e9c5 0100 strd r0, r1, [r5]
|
|
8000dd4: 2100 movs r1, #0
|
|
8000dd6: 4608 mov r0, r1
|
|
8000dd8: e7f5 b.n 8000dc6 <__udivmoddi4+0xa2>
|
|
8000dda: fab3 f183 clz r1, r3
|
|
8000dde: 2900 cmp r1, #0
|
|
8000de0: d146 bne.n 8000e70 <__udivmoddi4+0x14c>
|
|
8000de2: 4573 cmp r3, lr
|
|
8000de4: d302 bcc.n 8000dec <__udivmoddi4+0xc8>
|
|
8000de6: 4282 cmp r2, r0
|
|
8000de8: f200 8105 bhi.w 8000ff6 <__udivmoddi4+0x2d2>
|
|
8000dec: 1a84 subs r4, r0, r2
|
|
8000dee: eb6e 0203 sbc.w r2, lr, r3
|
|
8000df2: 2001 movs r0, #1
|
|
8000df4: 4690 mov r8, r2
|
|
8000df6: 2d00 cmp r5, #0
|
|
8000df8: d0e5 beq.n 8000dc6 <__udivmoddi4+0xa2>
|
|
8000dfa: e9c5 4800 strd r4, r8, [r5]
|
|
8000dfe: e7e2 b.n 8000dc6 <__udivmoddi4+0xa2>
|
|
8000e00: 2a00 cmp r2, #0
|
|
8000e02: f000 8090 beq.w 8000f26 <__udivmoddi4+0x202>
|
|
8000e06: fab2 f682 clz r6, r2
|
|
8000e0a: 2e00 cmp r6, #0
|
|
8000e0c: f040 80a4 bne.w 8000f58 <__udivmoddi4+0x234>
|
|
8000e10: 1a8a subs r2, r1, r2
|
|
8000e12: 0c03 lsrs r3, r0, #16
|
|
8000e14: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000e18: b280 uxth r0, r0
|
|
8000e1a: b2bc uxth r4, r7
|
|
8000e1c: 2101 movs r1, #1
|
|
8000e1e: fbb2 fcfe udiv ip, r2, lr
|
|
8000e22: fb0e 221c mls r2, lr, ip, r2
|
|
8000e26: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8000e2a: fb04 f20c mul.w r2, r4, ip
|
|
8000e2e: 429a cmp r2, r3
|
|
8000e30: d907 bls.n 8000e42 <__udivmoddi4+0x11e>
|
|
8000e32: 18fb adds r3, r7, r3
|
|
8000e34: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
|
|
8000e38: d202 bcs.n 8000e40 <__udivmoddi4+0x11c>
|
|
8000e3a: 429a cmp r2, r3
|
|
8000e3c: f200 80e0 bhi.w 8001000 <__udivmoddi4+0x2dc>
|
|
8000e40: 46c4 mov ip, r8
|
|
8000e42: 1a9b subs r3, r3, r2
|
|
8000e44: fbb3 f2fe udiv r2, r3, lr
|
|
8000e48: fb0e 3312 mls r3, lr, r2, r3
|
|
8000e4c: ea40 4303 orr.w r3, r0, r3, lsl #16
|
|
8000e50: fb02 f404 mul.w r4, r2, r4
|
|
8000e54: 429c cmp r4, r3
|
|
8000e56: d907 bls.n 8000e68 <__udivmoddi4+0x144>
|
|
8000e58: 18fb adds r3, r7, r3
|
|
8000e5a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
|
|
8000e5e: d202 bcs.n 8000e66 <__udivmoddi4+0x142>
|
|
8000e60: 429c cmp r4, r3
|
|
8000e62: f200 80ca bhi.w 8000ffa <__udivmoddi4+0x2d6>
|
|
8000e66: 4602 mov r2, r0
|
|
8000e68: 1b1b subs r3, r3, r4
|
|
8000e6a: ea42 400c orr.w r0, r2, ip, lsl #16
|
|
8000e6e: e7a5 b.n 8000dbc <__udivmoddi4+0x98>
|
|
8000e70: f1c1 0620 rsb r6, r1, #32
|
|
8000e74: 408b lsls r3, r1
|
|
8000e76: fa22 f706 lsr.w r7, r2, r6
|
|
8000e7a: 431f orrs r7, r3
|
|
8000e7c: fa0e f401 lsl.w r4, lr, r1
|
|
8000e80: fa20 f306 lsr.w r3, r0, r6
|
|
8000e84: fa2e fe06 lsr.w lr, lr, r6
|
|
8000e88: ea4f 4917 mov.w r9, r7, lsr #16
|
|
8000e8c: 4323 orrs r3, r4
|
|
8000e8e: fa00 f801 lsl.w r8, r0, r1
|
|
8000e92: fa1f fc87 uxth.w ip, r7
|
|
8000e96: fbbe f0f9 udiv r0, lr, r9
|
|
8000e9a: 0c1c lsrs r4, r3, #16
|
|
8000e9c: fb09 ee10 mls lr, r9, r0, lr
|
|
8000ea0: ea44 440e orr.w r4, r4, lr, lsl #16
|
|
8000ea4: fb00 fe0c mul.w lr, r0, ip
|
|
8000ea8: 45a6 cmp lr, r4
|
|
8000eaa: fa02 f201 lsl.w r2, r2, r1
|
|
8000eae: d909 bls.n 8000ec4 <__udivmoddi4+0x1a0>
|
|
8000eb0: 193c adds r4, r7, r4
|
|
8000eb2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
|
|
8000eb6: f080 809c bcs.w 8000ff2 <__udivmoddi4+0x2ce>
|
|
8000eba: 45a6 cmp lr, r4
|
|
8000ebc: f240 8099 bls.w 8000ff2 <__udivmoddi4+0x2ce>
|
|
8000ec0: 3802 subs r0, #2
|
|
8000ec2: 443c add r4, r7
|
|
8000ec4: eba4 040e sub.w r4, r4, lr
|
|
8000ec8: fa1f fe83 uxth.w lr, r3
|
|
8000ecc: fbb4 f3f9 udiv r3, r4, r9
|
|
8000ed0: fb09 4413 mls r4, r9, r3, r4
|
|
8000ed4: ea4e 4404 orr.w r4, lr, r4, lsl #16
|
|
8000ed8: fb03 fc0c mul.w ip, r3, ip
|
|
8000edc: 45a4 cmp ip, r4
|
|
8000ede: d908 bls.n 8000ef2 <__udivmoddi4+0x1ce>
|
|
8000ee0: 193c adds r4, r7, r4
|
|
8000ee2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
|
|
8000ee6: f080 8082 bcs.w 8000fee <__udivmoddi4+0x2ca>
|
|
8000eea: 45a4 cmp ip, r4
|
|
8000eec: d97f bls.n 8000fee <__udivmoddi4+0x2ca>
|
|
8000eee: 3b02 subs r3, #2
|
|
8000ef0: 443c add r4, r7
|
|
8000ef2: ea43 4000 orr.w r0, r3, r0, lsl #16
|
|
8000ef6: eba4 040c sub.w r4, r4, ip
|
|
8000efa: fba0 ec02 umull lr, ip, r0, r2
|
|
8000efe: 4564 cmp r4, ip
|
|
8000f00: 4673 mov r3, lr
|
|
8000f02: 46e1 mov r9, ip
|
|
8000f04: d362 bcc.n 8000fcc <__udivmoddi4+0x2a8>
|
|
8000f06: d05f beq.n 8000fc8 <__udivmoddi4+0x2a4>
|
|
8000f08: b15d cbz r5, 8000f22 <__udivmoddi4+0x1fe>
|
|
8000f0a: ebb8 0203 subs.w r2, r8, r3
|
|
8000f0e: eb64 0409 sbc.w r4, r4, r9
|
|
8000f12: fa04 f606 lsl.w r6, r4, r6
|
|
8000f16: fa22 f301 lsr.w r3, r2, r1
|
|
8000f1a: 431e orrs r6, r3
|
|
8000f1c: 40cc lsrs r4, r1
|
|
8000f1e: e9c5 6400 strd r6, r4, [r5]
|
|
8000f22: 2100 movs r1, #0
|
|
8000f24: e74f b.n 8000dc6 <__udivmoddi4+0xa2>
|
|
8000f26: fbb1 fcf2 udiv ip, r1, r2
|
|
8000f2a: 0c01 lsrs r1, r0, #16
|
|
8000f2c: ea41 410e orr.w r1, r1, lr, lsl #16
|
|
8000f30: b280 uxth r0, r0
|
|
8000f32: ea40 4201 orr.w r2, r0, r1, lsl #16
|
|
8000f36: 463b mov r3, r7
|
|
8000f38: 4638 mov r0, r7
|
|
8000f3a: 463c mov r4, r7
|
|
8000f3c: 46b8 mov r8, r7
|
|
8000f3e: 46be mov lr, r7
|
|
8000f40: 2620 movs r6, #32
|
|
8000f42: fbb1 f1f7 udiv r1, r1, r7
|
|
8000f46: eba2 0208 sub.w r2, r2, r8
|
|
8000f4a: ea41 410c orr.w r1, r1, ip, lsl #16
|
|
8000f4e: e766 b.n 8000e1e <__udivmoddi4+0xfa>
|
|
8000f50: 4601 mov r1, r0
|
|
8000f52: e718 b.n 8000d86 <__udivmoddi4+0x62>
|
|
8000f54: 4610 mov r0, r2
|
|
8000f56: e72c b.n 8000db2 <__udivmoddi4+0x8e>
|
|
8000f58: f1c6 0220 rsb r2, r6, #32
|
|
8000f5c: fa2e f302 lsr.w r3, lr, r2
|
|
8000f60: 40b7 lsls r7, r6
|
|
8000f62: 40b1 lsls r1, r6
|
|
8000f64: fa20 f202 lsr.w r2, r0, r2
|
|
8000f68: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000f6c: 430a orrs r2, r1
|
|
8000f6e: fbb3 f8fe udiv r8, r3, lr
|
|
8000f72: b2bc uxth r4, r7
|
|
8000f74: fb0e 3318 mls r3, lr, r8, r3
|
|
8000f78: 0c11 lsrs r1, r2, #16
|
|
8000f7a: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
8000f7e: fb08 f904 mul.w r9, r8, r4
|
|
8000f82: 40b0 lsls r0, r6
|
|
8000f84: 4589 cmp r9, r1
|
|
8000f86: ea4f 4310 mov.w r3, r0, lsr #16
|
|
8000f8a: b280 uxth r0, r0
|
|
8000f8c: d93e bls.n 800100c <__udivmoddi4+0x2e8>
|
|
8000f8e: 1879 adds r1, r7, r1
|
|
8000f90: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
8000f94: d201 bcs.n 8000f9a <__udivmoddi4+0x276>
|
|
8000f96: 4589 cmp r9, r1
|
|
8000f98: d81f bhi.n 8000fda <__udivmoddi4+0x2b6>
|
|
8000f9a: eba1 0109 sub.w r1, r1, r9
|
|
8000f9e: fbb1 f9fe udiv r9, r1, lr
|
|
8000fa2: fb09 f804 mul.w r8, r9, r4
|
|
8000fa6: fb0e 1119 mls r1, lr, r9, r1
|
|
8000faa: b292 uxth r2, r2
|
|
8000fac: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
8000fb0: 4542 cmp r2, r8
|
|
8000fb2: d229 bcs.n 8001008 <__udivmoddi4+0x2e4>
|
|
8000fb4: 18ba adds r2, r7, r2
|
|
8000fb6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
8000fba: d2c4 bcs.n 8000f46 <__udivmoddi4+0x222>
|
|
8000fbc: 4542 cmp r2, r8
|
|
8000fbe: d2c2 bcs.n 8000f46 <__udivmoddi4+0x222>
|
|
8000fc0: f1a9 0102 sub.w r1, r9, #2
|
|
8000fc4: 443a add r2, r7
|
|
8000fc6: e7be b.n 8000f46 <__udivmoddi4+0x222>
|
|
8000fc8: 45f0 cmp r8, lr
|
|
8000fca: d29d bcs.n 8000f08 <__udivmoddi4+0x1e4>
|
|
8000fcc: ebbe 0302 subs.w r3, lr, r2
|
|
8000fd0: eb6c 0c07 sbc.w ip, ip, r7
|
|
8000fd4: 3801 subs r0, #1
|
|
8000fd6: 46e1 mov r9, ip
|
|
8000fd8: e796 b.n 8000f08 <__udivmoddi4+0x1e4>
|
|
8000fda: eba7 0909 sub.w r9, r7, r9
|
|
8000fde: 4449 add r1, r9
|
|
8000fe0: f1a8 0c02 sub.w ip, r8, #2
|
|
8000fe4: fbb1 f9fe udiv r9, r1, lr
|
|
8000fe8: fb09 f804 mul.w r8, r9, r4
|
|
8000fec: e7db b.n 8000fa6 <__udivmoddi4+0x282>
|
|
8000fee: 4673 mov r3, lr
|
|
8000ff0: e77f b.n 8000ef2 <__udivmoddi4+0x1ce>
|
|
8000ff2: 4650 mov r0, sl
|
|
8000ff4: e766 b.n 8000ec4 <__udivmoddi4+0x1a0>
|
|
8000ff6: 4608 mov r0, r1
|
|
8000ff8: e6fd b.n 8000df6 <__udivmoddi4+0xd2>
|
|
8000ffa: 443b add r3, r7
|
|
8000ffc: 3a02 subs r2, #2
|
|
8000ffe: e733 b.n 8000e68 <__udivmoddi4+0x144>
|
|
8001000: f1ac 0c02 sub.w ip, ip, #2
|
|
8001004: 443b add r3, r7
|
|
8001006: e71c b.n 8000e42 <__udivmoddi4+0x11e>
|
|
8001008: 4649 mov r1, r9
|
|
800100a: e79c b.n 8000f46 <__udivmoddi4+0x222>
|
|
800100c: eba1 0109 sub.w r1, r1, r9
|
|
8001010: 46c4 mov ip, r8
|
|
8001012: fbb1 f9fe udiv r9, r1, lr
|
|
8001016: fb09 f804 mul.w r8, r9, r4
|
|
800101a: e7c4 b.n 8000fa6 <__udivmoddi4+0x282>
|
|
|
|
0800101c <__aeabi_idiv0>:
|
|
800101c: 4770 bx lr
|
|
800101e: bf00 nop
|
|
|
|
08001020 <I2Cx_MspInit>:
|
|
* @brief Initializes I2C MSP.
|
|
* @param i2c_handler I2C handler
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler)
|
|
{
|
|
8001020: b580 push {r7, lr}
|
|
8001022: b08a sub sp, #40 @ 0x28
|
|
8001024: af00 add r7, sp, #0
|
|
8001026: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef gpio_init_structure;
|
|
|
|
/*** Configure the GPIOs ***/
|
|
/* Enable GPIO clock */
|
|
DISCOVERY_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
|
|
8001028: 4b27 ldr r3, [pc, #156] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
800102a: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800102c: 4a26 ldr r2, [pc, #152] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
800102e: f043 0302 orr.w r3, r3, #2
|
|
8001032: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001034: 4b24 ldr r3, [pc, #144] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
8001036: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001038: f003 0302 and.w r3, r3, #2
|
|
800103c: 613b str r3, [r7, #16]
|
|
800103e: 693b ldr r3, [r7, #16]
|
|
|
|
/* Configure I2C Tx, Rx as alternate function */
|
|
gpio_init_structure.Pin = DISCOVERY_I2Cx_SCL_PIN | DISCOVERY_I2Cx_SDA_PIN;
|
|
8001040: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
8001044: 617b str r3, [r7, #20]
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
|
|
8001046: 2312 movs r3, #18
|
|
8001048: 61bb str r3, [r7, #24]
|
|
gpio_init_structure.Pull = GPIO_PULLUP;
|
|
800104a: 2301 movs r3, #1
|
|
800104c: 61fb str r3, [r7, #28]
|
|
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800104e: 2303 movs r3, #3
|
|
8001050: 623b str r3, [r7, #32]
|
|
gpio_init_structure.Alternate = DISCOVERY_I2Cx_SCL_SDA_AF;
|
|
8001052: 2304 movs r3, #4
|
|
8001054: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
|
8001056: f107 0314 add.w r3, r7, #20
|
|
800105a: 4619 mov r1, r3
|
|
800105c: 481b ldr r0, [pc, #108] @ (80010cc <I2Cx_MspInit+0xac>)
|
|
800105e: f003 f8ed bl 800423c <HAL_GPIO_Init>
|
|
|
|
HAL_GPIO_Init(DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
|
8001062: f107 0314 add.w r3, r7, #20
|
|
8001066: 4619 mov r1, r3
|
|
8001068: 4818 ldr r0, [pc, #96] @ (80010cc <I2Cx_MspInit+0xac>)
|
|
800106a: f003 f8e7 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*** Configure the I2C peripheral ***/
|
|
/* Enable I2C clock */
|
|
DISCOVERY_I2Cx_CLK_ENABLE();
|
|
800106e: 4b16 ldr r3, [pc, #88] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
8001070: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001072: 4a15 ldr r2, [pc, #84] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
8001074: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8001078: 6593 str r3, [r2, #88] @ 0x58
|
|
800107a: 4b13 ldr r3, [pc, #76] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
800107c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800107e: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8001082: 60fb str r3, [r7, #12]
|
|
8001084: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Force the I2C peripheral clock reset */
|
|
DISCOVERY_I2Cx_FORCE_RESET();
|
|
8001086: 4b10 ldr r3, [pc, #64] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
8001088: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800108a: 4a0f ldr r2, [pc, #60] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
800108c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8001090: 6393 str r3, [r2, #56] @ 0x38
|
|
|
|
/* Release the I2C peripheral clock reset */
|
|
DISCOVERY_I2Cx_RELEASE_RESET();
|
|
8001092: 4b0d ldr r3, [pc, #52] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
8001094: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8001096: 4a0c ldr r2, [pc, #48] @ (80010c8 <I2Cx_MspInit+0xa8>)
|
|
8001098: f423 0380 bic.w r3, r3, #4194304 @ 0x400000
|
|
800109c: 6393 str r3, [r2, #56] @ 0x38
|
|
|
|
/* Enable and set I2Cx Interrupt to a lower priority */
|
|
HAL_NVIC_SetPriority(DISCOVERY_I2Cx_EV_IRQn, 0x0F, 0);
|
|
800109e: 2200 movs r2, #0
|
|
80010a0: 210f movs r1, #15
|
|
80010a2: 2021 movs r0, #33 @ 0x21
|
|
80010a4: f002 ff14 bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_EV_IRQn);
|
|
80010a8: 2021 movs r0, #33 @ 0x21
|
|
80010aa: f002 ff2d bl 8003f08 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* Enable and set I2Cx Interrupt to a lower priority */
|
|
HAL_NVIC_SetPriority(DISCOVERY_I2Cx_ER_IRQn, 0x0F, 0);
|
|
80010ae: 2200 movs r2, #0
|
|
80010b0: 210f movs r1, #15
|
|
80010b2: 2022 movs r0, #34 @ 0x22
|
|
80010b4: f002 ff0c bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_ER_IRQn);
|
|
80010b8: 2022 movs r0, #34 @ 0x22
|
|
80010ba: f002 ff25 bl 8003f08 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
80010be: bf00 nop
|
|
80010c0: 3728 adds r7, #40 @ 0x28
|
|
80010c2: 46bd mov sp, r7
|
|
80010c4: bd80 pop {r7, pc}
|
|
80010c6: bf00 nop
|
|
80010c8: 40021000 .word 0x40021000
|
|
80010cc: 48000400 .word 0x48000400
|
|
|
|
080010d0 <I2Cx_Init>:
|
|
* @brief Initializes I2C HAL.
|
|
* @param i2c_handler I2C handler
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler)
|
|
{
|
|
80010d0: b580 push {r7, lr}
|
|
80010d2: b082 sub sp, #8
|
|
80010d4: af00 add r7, sp, #0
|
|
80010d6: 6078 str r0, [r7, #4]
|
|
/* I2C configuration */
|
|
i2c_handler->Instance = DISCOVERY_I2Cx;
|
|
80010d8: 687b ldr r3, [r7, #4]
|
|
80010da: 4a12 ldr r2, [pc, #72] @ (8001124 <I2Cx_Init+0x54>)
|
|
80010dc: 601a str r2, [r3, #0]
|
|
i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING;
|
|
80010de: 687b ldr r3, [r7, #4]
|
|
80010e0: 4a11 ldr r2, [pc, #68] @ (8001128 <I2Cx_Init+0x58>)
|
|
80010e2: 605a str r2, [r3, #4]
|
|
i2c_handler->Init.OwnAddress1 = 0;
|
|
80010e4: 687b ldr r3, [r7, #4]
|
|
80010e6: 2200 movs r2, #0
|
|
80010e8: 609a str r2, [r3, #8]
|
|
i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
80010ea: 687b ldr r3, [r7, #4]
|
|
80010ec: 2201 movs r2, #1
|
|
80010ee: 60da str r2, [r3, #12]
|
|
i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
80010f0: 687b ldr r3, [r7, #4]
|
|
80010f2: 2200 movs r2, #0
|
|
80010f4: 611a str r2, [r3, #16]
|
|
i2c_handler->Init.OwnAddress2 = 0;
|
|
80010f6: 687b ldr r3, [r7, #4]
|
|
80010f8: 2200 movs r2, #0
|
|
80010fa: 615a str r2, [r3, #20]
|
|
i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
80010fc: 687b ldr r3, [r7, #4]
|
|
80010fe: 2200 movs r2, #0
|
|
8001100: 61da str r2, [r3, #28]
|
|
i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8001102: 687b ldr r3, [r7, #4]
|
|
8001104: 2200 movs r2, #0
|
|
8001106: 621a str r2, [r3, #32]
|
|
|
|
/* Init the I2C */
|
|
I2Cx_MspInit(i2c_handler);
|
|
8001108: 6878 ldr r0, [r7, #4]
|
|
800110a: f7ff ff89 bl 8001020 <I2Cx_MspInit>
|
|
HAL_I2C_Init(i2c_handler);
|
|
800110e: 6878 ldr r0, [r7, #4]
|
|
8001110: f003 fb7a bl 8004808 <HAL_I2C_Init>
|
|
|
|
/**Configure Analogue filter */
|
|
HAL_I2CEx_ConfigAnalogFilter(i2c_handler, I2C_ANALOGFILTER_ENABLE);
|
|
8001114: 2100 movs r1, #0
|
|
8001116: 6878 ldr r0, [r7, #4]
|
|
8001118: f004 f930 bl 800537c <HAL_I2CEx_ConfigAnalogFilter>
|
|
}
|
|
800111c: bf00 nop
|
|
800111e: 3708 adds r7, #8
|
|
8001120: 46bd mov sp, r7
|
|
8001122: bd80 pop {r7, pc}
|
|
8001124: 40005800 .word 0x40005800
|
|
8001128: 00702681 .word 0x00702681
|
|
|
|
0800112c <I2Cx_ReadMultiple>:
|
|
* @param Buffer Pointer to data buffer
|
|
* @param Length Length of the data
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2Cx_ReadMultiple(I2C_HandleTypeDef *i2c_handler, uint8_t Addr, uint16_t Reg, uint16_t MemAddress, uint8_t *Buffer, uint16_t Length)
|
|
{
|
|
800112c: b580 push {r7, lr}
|
|
800112e: b08a sub sp, #40 @ 0x28
|
|
8001130: af04 add r7, sp, #16
|
|
8001132: 60f8 str r0, [r7, #12]
|
|
8001134: 4608 mov r0, r1
|
|
8001136: 4611 mov r1, r2
|
|
8001138: 461a mov r2, r3
|
|
800113a: 4603 mov r3, r0
|
|
800113c: 72fb strb r3, [r7, #11]
|
|
800113e: 460b mov r3, r1
|
|
8001140: 813b strh r3, [r7, #8]
|
|
8001142: 4613 mov r3, r2
|
|
8001144: 80fb strh r3, [r7, #6]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001146: 2300 movs r3, #0
|
|
8001148: 75fb strb r3, [r7, #23]
|
|
|
|
status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
|
|
800114a: 7afb ldrb r3, [r7, #11]
|
|
800114c: b299 uxth r1, r3
|
|
800114e: 88f8 ldrh r0, [r7, #6]
|
|
8001150: 893a ldrh r2, [r7, #8]
|
|
8001152: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001156: 9302 str r3, [sp, #8]
|
|
8001158: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
800115a: 9301 str r3, [sp, #4]
|
|
800115c: 6a3b ldr r3, [r7, #32]
|
|
800115e: 9300 str r3, [sp, #0]
|
|
8001160: 4603 mov r3, r0
|
|
8001162: 68f8 ldr r0, [r7, #12]
|
|
8001164: f003 fd2e bl 8004bc4 <HAL_I2C_Mem_Read>
|
|
8001168: 4603 mov r3, r0
|
|
800116a: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the communication status */
|
|
if(status != HAL_OK)
|
|
800116c: 7dfb ldrb r3, [r7, #23]
|
|
800116e: 2b00 cmp r3, #0
|
|
8001170: d004 beq.n 800117c <I2Cx_ReadMultiple+0x50>
|
|
{
|
|
/* I2C error occured */
|
|
I2Cx_Error(i2c_handler, Addr);
|
|
8001172: 7afb ldrb r3, [r7, #11]
|
|
8001174: 4619 mov r1, r3
|
|
8001176: 68f8 ldr r0, [r7, #12]
|
|
8001178: f000 f832 bl 80011e0 <I2Cx_Error>
|
|
}
|
|
return status;
|
|
800117c: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800117e: 4618 mov r0, r3
|
|
8001180: 3718 adds r7, #24
|
|
8001182: 46bd mov sp, r7
|
|
8001184: bd80 pop {r7, pc}
|
|
|
|
08001186 <I2Cx_WriteMultiple>:
|
|
* @param Buffer The target register value to be written
|
|
* @param Length buffer size to be written
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2Cx_WriteMultiple(I2C_HandleTypeDef *i2c_handler, uint8_t Addr, uint16_t Reg, uint16_t MemAddress, uint8_t *Buffer, uint16_t Length)
|
|
{
|
|
8001186: b580 push {r7, lr}
|
|
8001188: b08a sub sp, #40 @ 0x28
|
|
800118a: af04 add r7, sp, #16
|
|
800118c: 60f8 str r0, [r7, #12]
|
|
800118e: 4608 mov r0, r1
|
|
8001190: 4611 mov r1, r2
|
|
8001192: 461a mov r2, r3
|
|
8001194: 4603 mov r3, r0
|
|
8001196: 72fb strb r3, [r7, #11]
|
|
8001198: 460b mov r3, r1
|
|
800119a: 813b strh r3, [r7, #8]
|
|
800119c: 4613 mov r3, r2
|
|
800119e: 80fb strh r3, [r7, #6]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80011a0: 2300 movs r3, #0
|
|
80011a2: 75fb strb r3, [r7, #23]
|
|
|
|
status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
|
|
80011a4: 7afb ldrb r3, [r7, #11]
|
|
80011a6: b299 uxth r1, r3
|
|
80011a8: 88f8 ldrh r0, [r7, #6]
|
|
80011aa: 893a ldrh r2, [r7, #8]
|
|
80011ac: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80011b0: 9302 str r3, [sp, #8]
|
|
80011b2: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
80011b4: 9301 str r3, [sp, #4]
|
|
80011b6: 6a3b ldr r3, [r7, #32]
|
|
80011b8: 9300 str r3, [sp, #0]
|
|
80011ba: 4603 mov r3, r0
|
|
80011bc: 68f8 ldr r0, [r7, #12]
|
|
80011be: f003 fbed bl 800499c <HAL_I2C_Mem_Write>
|
|
80011c2: 4603 mov r3, r0
|
|
80011c4: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the communication status */
|
|
if(status != HAL_OK)
|
|
80011c6: 7dfb ldrb r3, [r7, #23]
|
|
80011c8: 2b00 cmp r3, #0
|
|
80011ca: d004 beq.n 80011d6 <I2Cx_WriteMultiple+0x50>
|
|
{
|
|
/* Re-Initiaize the I2C Bus */
|
|
I2Cx_Error(i2c_handler, Addr);
|
|
80011cc: 7afb ldrb r3, [r7, #11]
|
|
80011ce: 4619 mov r1, r3
|
|
80011d0: 68f8 ldr r0, [r7, #12]
|
|
80011d2: f000 f805 bl 80011e0 <I2Cx_Error>
|
|
}
|
|
return status;
|
|
80011d6: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80011d8: 4618 mov r0, r3
|
|
80011da: 3718 adds r7, #24
|
|
80011dc: 46bd mov sp, r7
|
|
80011de: bd80 pop {r7, pc}
|
|
|
|
080011e0 <I2Cx_Error>:
|
|
* @param i2c_handler I2C handler
|
|
* @param Addr I2C Address
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr)
|
|
{
|
|
80011e0: b580 push {r7, lr}
|
|
80011e2: b082 sub sp, #8
|
|
80011e4: af00 add r7, sp, #0
|
|
80011e6: 6078 str r0, [r7, #4]
|
|
80011e8: 460b mov r3, r1
|
|
80011ea: 70fb strb r3, [r7, #3]
|
|
/* De-initialize the I2C communication bus */
|
|
HAL_I2C_DeInit(i2c_handler);
|
|
80011ec: 6878 ldr r0, [r7, #4]
|
|
80011ee: f003 fba6 bl 800493e <HAL_I2C_DeInit>
|
|
|
|
/* Re-Initialize the I2C communication bus */
|
|
I2Cx_Init(i2c_handler);
|
|
80011f2: 6878 ldr r0, [r7, #4]
|
|
80011f4: f7ff ff6c bl 80010d0 <I2Cx_Init>
|
|
}
|
|
80011f8: bf00 nop
|
|
80011fa: 3708 adds r7, #8
|
|
80011fc: 46bd mov sp, r7
|
|
80011fe: bd80 pop {r7, pc}
|
|
|
|
08001200 <SENSOR_IO_Init>:
|
|
/**
|
|
* @brief Initializes Sensors low level.
|
|
* @retval None
|
|
*/
|
|
void SENSOR_IO_Init(void)
|
|
{
|
|
8001200: b580 push {r7, lr}
|
|
8001202: af00 add r7, sp, #0
|
|
I2Cx_Init(&hI2cHandler);
|
|
8001204: 4802 ldr r0, [pc, #8] @ (8001210 <SENSOR_IO_Init+0x10>)
|
|
8001206: f7ff ff63 bl 80010d0 <I2Cx_Init>
|
|
}
|
|
800120a: bf00 nop
|
|
800120c: bd80 pop {r7, pc}
|
|
800120e: bf00 nop
|
|
8001210: 200002b8 .word 0x200002b8
|
|
|
|
08001214 <SENSOR_IO_Write>:
|
|
* @param Reg Reg address
|
|
* @param Value Data to be written
|
|
* @retval None
|
|
*/
|
|
void SENSOR_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
|
|
{
|
|
8001214: b580 push {r7, lr}
|
|
8001216: b084 sub sp, #16
|
|
8001218: af02 add r7, sp, #8
|
|
800121a: 4603 mov r3, r0
|
|
800121c: 71fb strb r3, [r7, #7]
|
|
800121e: 460b mov r3, r1
|
|
8001220: 71bb strb r3, [r7, #6]
|
|
8001222: 4613 mov r3, r2
|
|
8001224: 717b strb r3, [r7, #5]
|
|
I2Cx_WriteMultiple(&hI2cHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1);
|
|
8001226: 79bb ldrb r3, [r7, #6]
|
|
8001228: b29a uxth r2, r3
|
|
800122a: 79f9 ldrb r1, [r7, #7]
|
|
800122c: 2301 movs r3, #1
|
|
800122e: 9301 str r3, [sp, #4]
|
|
8001230: 1d7b adds r3, r7, #5
|
|
8001232: 9300 str r3, [sp, #0]
|
|
8001234: 2301 movs r3, #1
|
|
8001236: 4803 ldr r0, [pc, #12] @ (8001244 <SENSOR_IO_Write+0x30>)
|
|
8001238: f7ff ffa5 bl 8001186 <I2Cx_WriteMultiple>
|
|
}
|
|
800123c: bf00 nop
|
|
800123e: 3708 adds r7, #8
|
|
8001240: 46bd mov sp, r7
|
|
8001242: bd80 pop {r7, pc}
|
|
8001244: 200002b8 .word 0x200002b8
|
|
|
|
08001248 <SENSOR_IO_Read>:
|
|
* @param Addr I2C address
|
|
* @param Reg Reg address
|
|
* @retval Data to be read
|
|
*/
|
|
uint8_t SENSOR_IO_Read(uint8_t Addr, uint8_t Reg)
|
|
{
|
|
8001248: b580 push {r7, lr}
|
|
800124a: b086 sub sp, #24
|
|
800124c: af02 add r7, sp, #8
|
|
800124e: 4603 mov r3, r0
|
|
8001250: 460a mov r2, r1
|
|
8001252: 71fb strb r3, [r7, #7]
|
|
8001254: 4613 mov r3, r2
|
|
8001256: 71bb strb r3, [r7, #6]
|
|
uint8_t read_value = 0;
|
|
8001258: 2300 movs r3, #0
|
|
800125a: 73fb strb r3, [r7, #15]
|
|
|
|
I2Cx_ReadMultiple(&hI2cHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1);
|
|
800125c: 79bb ldrb r3, [r7, #6]
|
|
800125e: b29a uxth r2, r3
|
|
8001260: 79f9 ldrb r1, [r7, #7]
|
|
8001262: 2301 movs r3, #1
|
|
8001264: 9301 str r3, [sp, #4]
|
|
8001266: f107 030f add.w r3, r7, #15
|
|
800126a: 9300 str r3, [sp, #0]
|
|
800126c: 2301 movs r3, #1
|
|
800126e: 4804 ldr r0, [pc, #16] @ (8001280 <SENSOR_IO_Read+0x38>)
|
|
8001270: f7ff ff5c bl 800112c <I2Cx_ReadMultiple>
|
|
|
|
return read_value;
|
|
8001274: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001276: 4618 mov r0, r3
|
|
8001278: 3710 adds r7, #16
|
|
800127a: 46bd mov sp, r7
|
|
800127c: bd80 pop {r7, pc}
|
|
800127e: bf00 nop
|
|
8001280: 200002b8 .word 0x200002b8
|
|
|
|
08001284 <SENSOR_IO_ReadMultiple>:
|
|
* @param Buffer Pointer to data buffer
|
|
* @param Length Length of the data
|
|
* @retval HAL status
|
|
*/
|
|
uint16_t SENSOR_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length)
|
|
{
|
|
8001284: b580 push {r7, lr}
|
|
8001286: b084 sub sp, #16
|
|
8001288: af02 add r7, sp, #8
|
|
800128a: 603a str r2, [r7, #0]
|
|
800128c: 461a mov r2, r3
|
|
800128e: 4603 mov r3, r0
|
|
8001290: 71fb strb r3, [r7, #7]
|
|
8001292: 460b mov r3, r1
|
|
8001294: 71bb strb r3, [r7, #6]
|
|
8001296: 4613 mov r3, r2
|
|
8001298: 80bb strh r3, [r7, #4]
|
|
return I2Cx_ReadMultiple(&hI2cHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, Buffer, Length);
|
|
800129a: 79bb ldrb r3, [r7, #6]
|
|
800129c: b29a uxth r2, r3
|
|
800129e: 79f9 ldrb r1, [r7, #7]
|
|
80012a0: 88bb ldrh r3, [r7, #4]
|
|
80012a2: 9301 str r3, [sp, #4]
|
|
80012a4: 683b ldr r3, [r7, #0]
|
|
80012a6: 9300 str r3, [sp, #0]
|
|
80012a8: 2301 movs r3, #1
|
|
80012aa: 4804 ldr r0, [pc, #16] @ (80012bc <SENSOR_IO_ReadMultiple+0x38>)
|
|
80012ac: f7ff ff3e bl 800112c <I2Cx_ReadMultiple>
|
|
80012b0: 4603 mov r3, r0
|
|
}
|
|
80012b2: 4618 mov r0, r3
|
|
80012b4: 3708 adds r7, #8
|
|
80012b6: 46bd mov sp, r7
|
|
80012b8: bd80 pop {r7, pc}
|
|
80012ba: bf00 nop
|
|
80012bc: 200002b8 .word 0x200002b8
|
|
|
|
080012c0 <BSP_ACCELERO_Init>:
|
|
/**
|
|
* @brief Initialize the ACCELERO.
|
|
* @retval ACCELERO_OK or ACCELERO_ERROR
|
|
*/
|
|
ACCELERO_StatusTypeDef BSP_ACCELERO_Init(void)
|
|
{
|
|
80012c0: b580 push {r7, lr}
|
|
80012c2: b084 sub sp, #16
|
|
80012c4: af00 add r7, sp, #0
|
|
ACCELERO_StatusTypeDef ret = ACCELERO_OK;
|
|
80012c6: 2300 movs r3, #0
|
|
80012c8: 73fb strb r3, [r7, #15]
|
|
uint16_t ctrl = 0x0000;
|
|
80012ca: 2300 movs r3, #0
|
|
80012cc: 81bb strh r3, [r7, #12]
|
|
ACCELERO_InitTypeDef LSM6DSL_InitStructure;
|
|
|
|
if(Lsm6dslAccDrv.ReadID() != LSM6DSL_ACC_GYRO_WHO_AM_I)
|
|
80012ce: 4b1a ldr r3, [pc, #104] @ (8001338 <BSP_ACCELERO_Init+0x78>)
|
|
80012d0: 689b ldr r3, [r3, #8]
|
|
80012d2: 4798 blx r3
|
|
80012d4: 4603 mov r3, r0
|
|
80012d6: 2b6a cmp r3, #106 @ 0x6a
|
|
80012d8: d002 beq.n 80012e0 <BSP_ACCELERO_Init+0x20>
|
|
{
|
|
ret = ACCELERO_ERROR;
|
|
80012da: 2301 movs r3, #1
|
|
80012dc: 73fb strb r3, [r7, #15]
|
|
80012de: e025 b.n 800132c <BSP_ACCELERO_Init+0x6c>
|
|
}
|
|
else
|
|
{
|
|
/* Initialize the ACCELERO accelerometer driver structure */
|
|
AccelerometerDrv = &Lsm6dslAccDrv;
|
|
80012e0: 4b16 ldr r3, [pc, #88] @ (800133c <BSP_ACCELERO_Init+0x7c>)
|
|
80012e2: 4a15 ldr r2, [pc, #84] @ (8001338 <BSP_ACCELERO_Init+0x78>)
|
|
80012e4: 601a str r2, [r3, #0]
|
|
|
|
/* MEMS configuration ------------------------------------------------------*/
|
|
/* Fill the ACCELERO accelerometer structure */
|
|
LSM6DSL_InitStructure.AccOutput_DataRate = LSM6DSL_ODR_52Hz;
|
|
80012e6: 2330 movs r3, #48 @ 0x30
|
|
80012e8: 717b strb r3, [r7, #5]
|
|
LSM6DSL_InitStructure.Axes_Enable = 0;
|
|
80012ea: 2300 movs r3, #0
|
|
80012ec: 71bb strb r3, [r7, #6]
|
|
LSM6DSL_InitStructure.AccFull_Scale = LSM6DSL_ACC_FULLSCALE_2G;
|
|
80012ee: 2300 movs r3, #0
|
|
80012f0: 72bb strb r3, [r7, #10]
|
|
LSM6DSL_InitStructure.BlockData_Update = LSM6DSL_BDU_BLOCK_UPDATE;
|
|
80012f2: 2340 movs r3, #64 @ 0x40
|
|
80012f4: 723b strb r3, [r7, #8]
|
|
LSM6DSL_InitStructure.High_Resolution = 0;
|
|
80012f6: 2300 movs r3, #0
|
|
80012f8: 71fb strb r3, [r7, #7]
|
|
LSM6DSL_InitStructure.Communication_Mode = 0;
|
|
80012fa: 2300 movs r3, #0
|
|
80012fc: 72fb strb r3, [r7, #11]
|
|
|
|
/* Configure MEMS: data rate, full scale */
|
|
ctrl = (LSM6DSL_InitStructure.AccOutput_DataRate | LSM6DSL_InitStructure.AccFull_Scale);
|
|
80012fe: 797a ldrb r2, [r7, #5]
|
|
8001300: 7abb ldrb r3, [r7, #10]
|
|
8001302: 4313 orrs r3, r2
|
|
8001304: b2db uxtb r3, r3
|
|
8001306: 81bb strh r3, [r7, #12]
|
|
|
|
/* Configure MEMS: BDU and Auto-increment for multi read/write */
|
|
ctrl |= ((LSM6DSL_InitStructure.BlockData_Update | LSM6DSL_ACC_GYRO_IF_INC_ENABLED) << 8);
|
|
8001308: 7a3b ldrb r3, [r7, #8]
|
|
800130a: f043 0304 orr.w r3, r3, #4
|
|
800130e: b2db uxtb r3, r3
|
|
8001310: b21b sxth r3, r3
|
|
8001312: 021b lsls r3, r3, #8
|
|
8001314: b21a sxth r2, r3
|
|
8001316: f9b7 300c ldrsh.w r3, [r7, #12]
|
|
800131a: 4313 orrs r3, r2
|
|
800131c: b21b sxth r3, r3
|
|
800131e: 81bb strh r3, [r7, #12]
|
|
|
|
/* Configure the ACCELERO accelerometer main parameters */
|
|
AccelerometerDrv->Init(ctrl);
|
|
8001320: 4b06 ldr r3, [pc, #24] @ (800133c <BSP_ACCELERO_Init+0x7c>)
|
|
8001322: 681b ldr r3, [r3, #0]
|
|
8001324: 681b ldr r3, [r3, #0]
|
|
8001326: 89ba ldrh r2, [r7, #12]
|
|
8001328: 4610 mov r0, r2
|
|
800132a: 4798 blx r3
|
|
}
|
|
|
|
return ret;
|
|
800132c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800132e: 4618 mov r0, r3
|
|
8001330: 3710 adds r7, #16
|
|
8001332: 46bd mov sp, r7
|
|
8001334: bd80 pop {r7, pc}
|
|
8001336: bf00 nop
|
|
8001338: 2000005c .word 0x2000005c
|
|
800133c: 2000030c .word 0x2000030c
|
|
|
|
08001340 <BSP_ACCELERO_AccGetXYZ>:
|
|
* @param pDataXYZ Pointer on 3 angular accelerations table with
|
|
* pDataXYZ[0] = X axis, pDataXYZ[1] = Y axis, pDataXYZ[2] = Z axis
|
|
* @retval None
|
|
*/
|
|
void BSP_ACCELERO_AccGetXYZ(int16_t *pDataXYZ)
|
|
{
|
|
8001340: b580 push {r7, lr}
|
|
8001342: b082 sub sp, #8
|
|
8001344: af00 add r7, sp, #0
|
|
8001346: 6078 str r0, [r7, #4]
|
|
if(AccelerometerDrv != NULL)
|
|
8001348: 4b08 ldr r3, [pc, #32] @ (800136c <BSP_ACCELERO_AccGetXYZ+0x2c>)
|
|
800134a: 681b ldr r3, [r3, #0]
|
|
800134c: 2b00 cmp r3, #0
|
|
800134e: d009 beq.n 8001364 <BSP_ACCELERO_AccGetXYZ+0x24>
|
|
{
|
|
if(AccelerometerDrv->GetXYZ != NULL)
|
|
8001350: 4b06 ldr r3, [pc, #24] @ (800136c <BSP_ACCELERO_AccGetXYZ+0x2c>)
|
|
8001352: 681b ldr r3, [r3, #0]
|
|
8001354: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001356: 2b00 cmp r3, #0
|
|
8001358: d004 beq.n 8001364 <BSP_ACCELERO_AccGetXYZ+0x24>
|
|
{
|
|
AccelerometerDrv->GetXYZ(pDataXYZ);
|
|
800135a: 4b04 ldr r3, [pc, #16] @ (800136c <BSP_ACCELERO_AccGetXYZ+0x2c>)
|
|
800135c: 681b ldr r3, [r3, #0]
|
|
800135e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001360: 6878 ldr r0, [r7, #4]
|
|
8001362: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
8001364: bf00 nop
|
|
8001366: 3708 adds r7, #8
|
|
8001368: 46bd mov sp, r7
|
|
800136a: bd80 pop {r7, pc}
|
|
800136c: 2000030c .word 0x2000030c
|
|
|
|
08001370 <BSP_GYRO_Init>:
|
|
/**
|
|
* @brief Initialize Gyroscope.
|
|
* @retval GYRO_OK or GYRO_ERROR
|
|
*/
|
|
uint8_t BSP_GYRO_Init(void)
|
|
{
|
|
8001370: b580 push {r7, lr}
|
|
8001372: b084 sub sp, #16
|
|
8001374: af00 add r7, sp, #0
|
|
uint8_t ret = GYRO_ERROR;
|
|
8001376: 2301 movs r3, #1
|
|
8001378: 73fb strb r3, [r7, #15]
|
|
uint16_t ctrl = 0x0000;
|
|
800137a: 2300 movs r3, #0
|
|
800137c: 81bb strh r3, [r7, #12]
|
|
GYRO_InitTypeDef LSM6DSL_InitStructure;
|
|
|
|
if(Lsm6dslGyroDrv.ReadID() != LSM6DSL_ACC_GYRO_WHO_AM_I)
|
|
800137e: 4b1c ldr r3, [pc, #112] @ (80013f0 <BSP_GYRO_Init+0x80>)
|
|
8001380: 689b ldr r3, [r3, #8]
|
|
8001382: 4798 blx r3
|
|
8001384: 4603 mov r3, r0
|
|
8001386: 2b6a cmp r3, #106 @ 0x6a
|
|
8001388: d002 beq.n 8001390 <BSP_GYRO_Init+0x20>
|
|
{
|
|
ret = GYRO_ERROR;
|
|
800138a: 2301 movs r3, #1
|
|
800138c: 73fb strb r3, [r7, #15]
|
|
800138e: e029 b.n 80013e4 <BSP_GYRO_Init+0x74>
|
|
}
|
|
else
|
|
{
|
|
/* Initialize the gyroscope driver structure */
|
|
GyroscopeDrv = &Lsm6dslGyroDrv;
|
|
8001390: 4b18 ldr r3, [pc, #96] @ (80013f4 <BSP_GYRO_Init+0x84>)
|
|
8001392: 4a17 ldr r2, [pc, #92] @ (80013f0 <BSP_GYRO_Init+0x80>)
|
|
8001394: 601a str r2, [r3, #0]
|
|
|
|
/* Configure Mems : data rate, power mode, full scale and axes */
|
|
LSM6DSL_InitStructure.Power_Mode = 0;
|
|
8001396: 2300 movs r3, #0
|
|
8001398: 713b strb r3, [r7, #4]
|
|
LSM6DSL_InitStructure.Output_DataRate = LSM6DSL_ODR_52Hz;
|
|
800139a: 2330 movs r3, #48 @ 0x30
|
|
800139c: 717b strb r3, [r7, #5]
|
|
LSM6DSL_InitStructure.Axes_Enable = 0;
|
|
800139e: 2300 movs r3, #0
|
|
80013a0: 71bb strb r3, [r7, #6]
|
|
LSM6DSL_InitStructure.Band_Width = 0;
|
|
80013a2: 2300 movs r3, #0
|
|
80013a4: 71fb strb r3, [r7, #7]
|
|
LSM6DSL_InitStructure.BlockData_Update = LSM6DSL_BDU_BLOCK_UPDATE;
|
|
80013a6: 2340 movs r3, #64 @ 0x40
|
|
80013a8: 723b strb r3, [r7, #8]
|
|
LSM6DSL_InitStructure.Endianness = 0;
|
|
80013aa: 2300 movs r3, #0
|
|
80013ac: 727b strb r3, [r7, #9]
|
|
LSM6DSL_InitStructure.Full_Scale = LSM6DSL_GYRO_FS_2000;
|
|
80013ae: 230c movs r3, #12
|
|
80013b0: 72bb strb r3, [r7, #10]
|
|
|
|
/* Configure MEMS: data rate, full scale */
|
|
ctrl = (LSM6DSL_InitStructure.Full_Scale | LSM6DSL_InitStructure.Output_DataRate);
|
|
80013b2: 7aba ldrb r2, [r7, #10]
|
|
80013b4: 797b ldrb r3, [r7, #5]
|
|
80013b6: 4313 orrs r3, r2
|
|
80013b8: b2db uxtb r3, r3
|
|
80013ba: 81bb strh r3, [r7, #12]
|
|
|
|
/* Configure MEMS: BDU and Auto-increment for multi read/write */
|
|
ctrl |= ((LSM6DSL_InitStructure.BlockData_Update | LSM6DSL_ACC_GYRO_IF_INC_ENABLED) << 8);
|
|
80013bc: 7a3b ldrb r3, [r7, #8]
|
|
80013be: f043 0304 orr.w r3, r3, #4
|
|
80013c2: b2db uxtb r3, r3
|
|
80013c4: b21b sxth r3, r3
|
|
80013c6: 021b lsls r3, r3, #8
|
|
80013c8: b21a sxth r2, r3
|
|
80013ca: f9b7 300c ldrsh.w r3, [r7, #12]
|
|
80013ce: 4313 orrs r3, r2
|
|
80013d0: b21b sxth r3, r3
|
|
80013d2: 81bb strh r3, [r7, #12]
|
|
|
|
/* Initialize component */
|
|
GyroscopeDrv->Init(ctrl);
|
|
80013d4: 4b07 ldr r3, [pc, #28] @ (80013f4 <BSP_GYRO_Init+0x84>)
|
|
80013d6: 681b ldr r3, [r3, #0]
|
|
80013d8: 681b ldr r3, [r3, #0]
|
|
80013da: 89ba ldrh r2, [r7, #12]
|
|
80013dc: 4610 mov r0, r2
|
|
80013de: 4798 blx r3
|
|
|
|
ret = GYRO_OK;
|
|
80013e0: 2300 movs r3, #0
|
|
80013e2: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return ret;
|
|
80013e4: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80013e6: 4618 mov r0, r3
|
|
80013e8: 3710 adds r7, #16
|
|
80013ea: 46bd mov sp, r7
|
|
80013ec: bd80 pop {r7, pc}
|
|
80013ee: bf00 nop
|
|
80013f0: 20000090 .word 0x20000090
|
|
80013f4: 20000310 .word 0x20000310
|
|
|
|
080013f8 <BSP_GYRO_GetXYZ>:
|
|
/**
|
|
* @brief Get XYZ angular acceleration from the Gyroscope.
|
|
* @param pfData: pointer on floating array
|
|
*/
|
|
void BSP_GYRO_GetXYZ(float* pfData)
|
|
{
|
|
80013f8: b580 push {r7, lr}
|
|
80013fa: b082 sub sp, #8
|
|
80013fc: af00 add r7, sp, #0
|
|
80013fe: 6078 str r0, [r7, #4]
|
|
if(GyroscopeDrv != NULL)
|
|
8001400: 4b08 ldr r3, [pc, #32] @ (8001424 <BSP_GYRO_GetXYZ+0x2c>)
|
|
8001402: 681b ldr r3, [r3, #0]
|
|
8001404: 2b00 cmp r3, #0
|
|
8001406: d009 beq.n 800141c <BSP_GYRO_GetXYZ+0x24>
|
|
{
|
|
if(GyroscopeDrv->GetXYZ!= NULL)
|
|
8001408: 4b06 ldr r3, [pc, #24] @ (8001424 <BSP_GYRO_GetXYZ+0x2c>)
|
|
800140a: 681b ldr r3, [r3, #0]
|
|
800140c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800140e: 2b00 cmp r3, #0
|
|
8001410: d004 beq.n 800141c <BSP_GYRO_GetXYZ+0x24>
|
|
{
|
|
GyroscopeDrv->GetXYZ(pfData);
|
|
8001412: 4b04 ldr r3, [pc, #16] @ (8001424 <BSP_GYRO_GetXYZ+0x2c>)
|
|
8001414: 681b ldr r3, [r3, #0]
|
|
8001416: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001418: 6878 ldr r0, [r7, #4]
|
|
800141a: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
800141c: bf00 nop
|
|
800141e: 3708 adds r7, #8
|
|
8001420: 46bd mov sp, r7
|
|
8001422: bd80 pop {r7, pc}
|
|
8001424: 20000310 .word 0x20000310
|
|
|
|
08001428 <BSP_HSENSOR_Init>:
|
|
/**
|
|
* @brief Initializes peripherals used by the I2C Humidity Sensor driver.
|
|
* @retval HSENSOR status
|
|
*/
|
|
uint32_t BSP_HSENSOR_Init(void)
|
|
{
|
|
8001428: b580 push {r7, lr}
|
|
800142a: b082 sub sp, #8
|
|
800142c: af00 add r7, sp, #0
|
|
uint32_t ret;
|
|
|
|
if(HTS221_H_Drv.ReadID(HTS221_I2C_ADDRESS) != HTS221_WHO_AM_I_VAL)
|
|
800142e: 4b0c ldr r3, [pc, #48] @ (8001460 <BSP_HSENSOR_Init+0x38>)
|
|
8001430: 685b ldr r3, [r3, #4]
|
|
8001432: 20be movs r0, #190 @ 0xbe
|
|
8001434: 4798 blx r3
|
|
8001436: 4603 mov r3, r0
|
|
8001438: 2bbc cmp r3, #188 @ 0xbc
|
|
800143a: d002 beq.n 8001442 <BSP_HSENSOR_Init+0x1a>
|
|
{
|
|
ret = HSENSOR_ERROR;
|
|
800143c: 2301 movs r3, #1
|
|
800143e: 607b str r3, [r7, #4]
|
|
8001440: e009 b.n 8001456 <BSP_HSENSOR_Init+0x2e>
|
|
}
|
|
else
|
|
{
|
|
Hsensor_drv = &HTS221_H_Drv;
|
|
8001442: 4b08 ldr r3, [pc, #32] @ (8001464 <BSP_HSENSOR_Init+0x3c>)
|
|
8001444: 4a06 ldr r2, [pc, #24] @ (8001460 <BSP_HSENSOR_Init+0x38>)
|
|
8001446: 601a str r2, [r3, #0]
|
|
/* HSENSOR Init */
|
|
Hsensor_drv->Init(HTS221_I2C_ADDRESS);
|
|
8001448: 4b06 ldr r3, [pc, #24] @ (8001464 <BSP_HSENSOR_Init+0x3c>)
|
|
800144a: 681b ldr r3, [r3, #0]
|
|
800144c: 681b ldr r3, [r3, #0]
|
|
800144e: 20be movs r0, #190 @ 0xbe
|
|
8001450: 4798 blx r3
|
|
ret = HSENSOR_OK;
|
|
8001452: 2300 movs r3, #0
|
|
8001454: 607b str r3, [r7, #4]
|
|
}
|
|
|
|
return ret;
|
|
8001456: 687b ldr r3, [r7, #4]
|
|
}
|
|
8001458: 4618 mov r0, r3
|
|
800145a: 3708 adds r7, #8
|
|
800145c: 46bd mov sp, r7
|
|
800145e: bd80 pop {r7, pc}
|
|
8001460: 20000000 .word 0x20000000
|
|
8001464: 20000314 .word 0x20000314
|
|
|
|
08001468 <BSP_HSENSOR_ReadHumidity>:
|
|
/**
|
|
* @brief Read Humidity register of HTS221.
|
|
* @retval HTS221 measured humidity value.
|
|
*/
|
|
float BSP_HSENSOR_ReadHumidity(void)
|
|
{
|
|
8001468: b580 push {r7, lr}
|
|
800146a: af00 add r7, sp, #0
|
|
return Hsensor_drv->ReadHumidity(HTS221_I2C_ADDRESS);
|
|
800146c: 4b04 ldr r3, [pc, #16] @ (8001480 <BSP_HSENSOR_ReadHumidity+0x18>)
|
|
800146e: 681b ldr r3, [r3, #0]
|
|
8001470: 689b ldr r3, [r3, #8]
|
|
8001472: 20be movs r0, #190 @ 0xbe
|
|
8001474: 4798 blx r3
|
|
8001476: eef0 7a40 vmov.f32 s15, s0
|
|
}
|
|
800147a: eeb0 0a67 vmov.f32 s0, s15
|
|
800147e: bd80 pop {r7, pc}
|
|
8001480: 20000314 .word 0x20000314
|
|
|
|
08001484 <BSP_MAGNETO_Init>:
|
|
/**
|
|
* @brief Initialize a magnetometer sensor
|
|
* @retval COMPONENT_ERROR in case of failure
|
|
*/
|
|
MAGNETO_StatusTypeDef BSP_MAGNETO_Init(void)
|
|
{
|
|
8001484: b580 push {r7, lr}
|
|
8001486: b082 sub sp, #8
|
|
8001488: af00 add r7, sp, #0
|
|
MAGNETO_StatusTypeDef ret = MAGNETO_OK;
|
|
800148a: 2300 movs r3, #0
|
|
800148c: 71fb strb r3, [r7, #7]
|
|
MAGNETO_InitTypeDef LIS3MDL_InitStructureMag;
|
|
|
|
if(Lis3mdlMagDrv.ReadID() != I_AM_LIS3MDL)
|
|
800148e: 4b11 ldr r3, [pc, #68] @ (80014d4 <BSP_MAGNETO_Init+0x50>)
|
|
8001490: 689b ldr r3, [r3, #8]
|
|
8001492: 4798 blx r3
|
|
8001494: 4603 mov r3, r0
|
|
8001496: 2b3d cmp r3, #61 @ 0x3d
|
|
8001498: d002 beq.n 80014a0 <BSP_MAGNETO_Init+0x1c>
|
|
{
|
|
ret = MAGNETO_ERROR;
|
|
800149a: 2301 movs r3, #1
|
|
800149c: 71fb strb r3, [r7, #7]
|
|
800149e: e013 b.n 80014c8 <BSP_MAGNETO_Init+0x44>
|
|
}
|
|
else
|
|
{
|
|
/* Initialize the MAGNETO magnetometer driver structure */
|
|
MagnetoDrv = &Lis3mdlMagDrv;
|
|
80014a0: 4b0d ldr r3, [pc, #52] @ (80014d8 <BSP_MAGNETO_Init+0x54>)
|
|
80014a2: 4a0c ldr r2, [pc, #48] @ (80014d4 <BSP_MAGNETO_Init+0x50>)
|
|
80014a4: 601a str r2, [r3, #0]
|
|
|
|
/* MEMS configuration ------------------------------------------------------*/
|
|
/* Fill the MAGNETO magnetometer structure */
|
|
LIS3MDL_InitStructureMag.Register1 = LIS3MDL_MAG_TEMPSENSOR_DISABLE | LIS3MDL_MAG_OM_XY_HIGH | LIS3MDL_MAG_ODR_40_HZ;
|
|
80014a6: 2358 movs r3, #88 @ 0x58
|
|
80014a8: 703b strb r3, [r7, #0]
|
|
LIS3MDL_InitStructureMag.Register2 = LIS3MDL_MAG_FS_4_GA | LIS3MDL_MAG_REBOOT_DEFAULT | LIS3MDL_MAG_SOFT_RESET_DEFAULT;
|
|
80014aa: 2300 movs r3, #0
|
|
80014ac: 707b strb r3, [r7, #1]
|
|
LIS3MDL_InitStructureMag.Register3 = LIS3MDL_MAG_CONFIG_NORMAL_MODE | LIS3MDL_MAG_CONTINUOUS_MODE;
|
|
80014ae: 2300 movs r3, #0
|
|
80014b0: 70bb strb r3, [r7, #2]
|
|
LIS3MDL_InitStructureMag.Register4 = LIS3MDL_MAG_OM_Z_HIGH | LIS3MDL_MAG_BLE_LSB;
|
|
80014b2: 2308 movs r3, #8
|
|
80014b4: 70fb strb r3, [r7, #3]
|
|
LIS3MDL_InitStructureMag.Register5 = LIS3MDL_MAG_BDU_MSBLSB;
|
|
80014b6: 2340 movs r3, #64 @ 0x40
|
|
80014b8: 713b strb r3, [r7, #4]
|
|
/* Configure the MAGNETO magnetometer main parameters */
|
|
MagnetoDrv->Init(LIS3MDL_InitStructureMag);
|
|
80014ba: 4b07 ldr r3, [pc, #28] @ (80014d8 <BSP_MAGNETO_Init+0x54>)
|
|
80014bc: 681b ldr r3, [r3, #0]
|
|
80014be: 681b ldr r3, [r3, #0]
|
|
80014c0: 463a mov r2, r7
|
|
80014c2: e892 0003 ldmia.w r2, {r0, r1}
|
|
80014c6: 4798 blx r3
|
|
}
|
|
|
|
return ret;
|
|
80014c8: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
80014ca: 4618 mov r0, r3
|
|
80014cc: 3708 adds r7, #8
|
|
80014ce: 46bd mov sp, r7
|
|
80014d0: bd80 pop {r7, pc}
|
|
80014d2: bf00 nop
|
|
80014d4: 2000001c .word 0x2000001c
|
|
80014d8: 20000318 .word 0x20000318
|
|
|
|
080014dc <BSP_MAGNETO_GetXYZ>:
|
|
* @brief Get XYZ magnetometer values.
|
|
* @param pDataXYZ Pointer on 3 magnetometer values table with
|
|
* pDataXYZ[0] = X axis, pDataXYZ[1] = Y axis, pDataXYZ[2] = Z axis
|
|
*/
|
|
void BSP_MAGNETO_GetXYZ(int16_t *pDataXYZ)
|
|
{
|
|
80014dc: b580 push {r7, lr}
|
|
80014de: b082 sub sp, #8
|
|
80014e0: af00 add r7, sp, #0
|
|
80014e2: 6078 str r0, [r7, #4]
|
|
if(MagnetoDrv != NULL)
|
|
80014e4: 4b08 ldr r3, [pc, #32] @ (8001508 <BSP_MAGNETO_GetXYZ+0x2c>)
|
|
80014e6: 681b ldr r3, [r3, #0]
|
|
80014e8: 2b00 cmp r3, #0
|
|
80014ea: d009 beq.n 8001500 <BSP_MAGNETO_GetXYZ+0x24>
|
|
{
|
|
if(MagnetoDrv->GetXYZ != NULL)
|
|
80014ec: 4b06 ldr r3, [pc, #24] @ (8001508 <BSP_MAGNETO_GetXYZ+0x2c>)
|
|
80014ee: 681b ldr r3, [r3, #0]
|
|
80014f0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80014f2: 2b00 cmp r3, #0
|
|
80014f4: d004 beq.n 8001500 <BSP_MAGNETO_GetXYZ+0x24>
|
|
{
|
|
MagnetoDrv->GetXYZ(pDataXYZ);
|
|
80014f6: 4b04 ldr r3, [pc, #16] @ (8001508 <BSP_MAGNETO_GetXYZ+0x2c>)
|
|
80014f8: 681b ldr r3, [r3, #0]
|
|
80014fa: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80014fc: 6878 ldr r0, [r7, #4]
|
|
80014fe: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
8001500: bf00 nop
|
|
8001502: 3708 adds r7, #8
|
|
8001504: 46bd mov sp, r7
|
|
8001506: bd80 pop {r7, pc}
|
|
8001508: 20000318 .word 0x20000318
|
|
|
|
0800150c <BSP_PSENSOR_Init>:
|
|
/**
|
|
* @brief Initializes peripherals used by the I2C Pressure Sensor driver.
|
|
* @retval PSENSOR status
|
|
*/
|
|
uint32_t BSP_PSENSOR_Init(void)
|
|
{
|
|
800150c: b580 push {r7, lr}
|
|
800150e: b082 sub sp, #8
|
|
8001510: af00 add r7, sp, #0
|
|
uint32_t ret;
|
|
|
|
if(LPS22HB_P_Drv.ReadID(LPS22HB_I2C_ADDRESS) != LPS22HB_WHO_AM_I_VAL)
|
|
8001512: 4b0c ldr r3, [pc, #48] @ (8001544 <BSP_PSENSOR_Init+0x38>)
|
|
8001514: 685b ldr r3, [r3, #4]
|
|
8001516: 20ba movs r0, #186 @ 0xba
|
|
8001518: 4798 blx r3
|
|
800151a: 4603 mov r3, r0
|
|
800151c: 2bb1 cmp r3, #177 @ 0xb1
|
|
800151e: d002 beq.n 8001526 <BSP_PSENSOR_Init+0x1a>
|
|
{
|
|
ret = PSENSOR_ERROR;
|
|
8001520: 2301 movs r3, #1
|
|
8001522: 607b str r3, [r7, #4]
|
|
8001524: e009 b.n 800153a <BSP_PSENSOR_Init+0x2e>
|
|
}
|
|
else
|
|
{
|
|
Psensor_drv = &LPS22HB_P_Drv;
|
|
8001526: 4b08 ldr r3, [pc, #32] @ (8001548 <BSP_PSENSOR_Init+0x3c>)
|
|
8001528: 4a06 ldr r2, [pc, #24] @ (8001544 <BSP_PSENSOR_Init+0x38>)
|
|
800152a: 601a str r2, [r3, #0]
|
|
|
|
/* PSENSOR Init */
|
|
Psensor_drv->Init(LPS22HB_I2C_ADDRESS);
|
|
800152c: 4b06 ldr r3, [pc, #24] @ (8001548 <BSP_PSENSOR_Init+0x3c>)
|
|
800152e: 681b ldr r3, [r3, #0]
|
|
8001530: 681b ldr r3, [r3, #0]
|
|
8001532: 20ba movs r0, #186 @ 0xba
|
|
8001534: 4798 blx r3
|
|
ret = PSENSOR_OK;
|
|
8001536: 2300 movs r3, #0
|
|
8001538: 607b str r3, [r7, #4]
|
|
}
|
|
|
|
return ret;
|
|
800153a: 687b ldr r3, [r7, #4]
|
|
}
|
|
800153c: 4618 mov r0, r3
|
|
800153e: 3708 adds r7, #8
|
|
8001540: 46bd mov sp, r7
|
|
8001542: bd80 pop {r7, pc}
|
|
8001544: 20000050 .word 0x20000050
|
|
8001548: 2000031c .word 0x2000031c
|
|
|
|
0800154c <BSP_PSENSOR_ReadPressure>:
|
|
/**
|
|
* @brief Read Pressure register of LPS22HB.
|
|
* @retval LPS22HB measured pressure value.
|
|
*/
|
|
float BSP_PSENSOR_ReadPressure(void)
|
|
{
|
|
800154c: b580 push {r7, lr}
|
|
800154e: af00 add r7, sp, #0
|
|
return Psensor_drv->ReadPressure(LPS22HB_I2C_ADDRESS);
|
|
8001550: 4b04 ldr r3, [pc, #16] @ (8001564 <BSP_PSENSOR_ReadPressure+0x18>)
|
|
8001552: 681b ldr r3, [r3, #0]
|
|
8001554: 689b ldr r3, [r3, #8]
|
|
8001556: 20ba movs r0, #186 @ 0xba
|
|
8001558: 4798 blx r3
|
|
800155a: eef0 7a40 vmov.f32 s15, s0
|
|
}
|
|
800155e: eeb0 0a67 vmov.f32 s0, s15
|
|
8001562: bd80 pop {r7, pc}
|
|
8001564: 2000031c .word 0x2000031c
|
|
|
|
08001568 <BSP_TSENSOR_Init>:
|
|
/**
|
|
* @brief Initializes peripherals used by the I2C Temperature Sensor driver.
|
|
* @retval TSENSOR status
|
|
*/
|
|
uint32_t BSP_TSENSOR_Init(void)
|
|
{
|
|
8001568: b580 push {r7, lr}
|
|
800156a: b082 sub sp, #8
|
|
800156c: af00 add r7, sp, #0
|
|
uint8_t ret = TSENSOR_ERROR;
|
|
800156e: 2301 movs r3, #1
|
|
8001570: 71fb strb r3, [r7, #7]
|
|
|
|
#ifdef USE_LPS22HB_TEMP
|
|
tsensor_drv = &LPS22HB_T_Drv;
|
|
#else /* USE_HTS221_TEMP */
|
|
tsensor_drv = &HTS221_T_Drv;
|
|
8001572: 4b09 ldr r3, [pc, #36] @ (8001598 <BSP_TSENSOR_Init+0x30>)
|
|
8001574: 4a09 ldr r2, [pc, #36] @ (800159c <BSP_TSENSOR_Init+0x34>)
|
|
8001576: 601a str r2, [r3, #0]
|
|
#endif
|
|
|
|
/* Low level init */
|
|
SENSOR_IO_Init();
|
|
8001578: f7ff fe42 bl 8001200 <SENSOR_IO_Init>
|
|
|
|
/* TSENSOR Init */
|
|
tsensor_drv->Init(TSENSOR_I2C_ADDRESS, NULL);
|
|
800157c: 4b06 ldr r3, [pc, #24] @ (8001598 <BSP_TSENSOR_Init+0x30>)
|
|
800157e: 681b ldr r3, [r3, #0]
|
|
8001580: 681b ldr r3, [r3, #0]
|
|
8001582: 2100 movs r1, #0
|
|
8001584: 20be movs r0, #190 @ 0xbe
|
|
8001586: 4798 blx r3
|
|
|
|
ret = TSENSOR_OK;
|
|
8001588: 2300 movs r3, #0
|
|
800158a: 71fb strb r3, [r7, #7]
|
|
|
|
return ret;
|
|
800158c: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
800158e: 4618 mov r0, r3
|
|
8001590: 3708 adds r7, #8
|
|
8001592: 46bd mov sp, r7
|
|
8001594: bd80 pop {r7, pc}
|
|
8001596: bf00 nop
|
|
8001598: 20000320 .word 0x20000320
|
|
800159c: 2000000c .word 0x2000000c
|
|
|
|
080015a0 <BSP_TSENSOR_ReadTemp>:
|
|
/**
|
|
* @brief Read Temperature register of TS751.
|
|
* @retval STTS751 measured temperature value.
|
|
*/
|
|
float BSP_TSENSOR_ReadTemp(void)
|
|
{
|
|
80015a0: b580 push {r7, lr}
|
|
80015a2: af00 add r7, sp, #0
|
|
return tsensor_drv->ReadTemp(TSENSOR_I2C_ADDRESS);
|
|
80015a4: 4b04 ldr r3, [pc, #16] @ (80015b8 <BSP_TSENSOR_ReadTemp+0x18>)
|
|
80015a6: 681b ldr r3, [r3, #0]
|
|
80015a8: 68db ldr r3, [r3, #12]
|
|
80015aa: 20be movs r0, #190 @ 0xbe
|
|
80015ac: 4798 blx r3
|
|
80015ae: eef0 7a40 vmov.f32 s15, s0
|
|
}
|
|
80015b2: eeb0 0a67 vmov.f32 s0, s15
|
|
80015b6: bd80 pop {r7, pc}
|
|
80015b8: 20000320 .word 0x20000320
|
|
|
|
080015bc <HTS221_H_Init>:
|
|
*/
|
|
/**
|
|
* @brief Set HTS221 humidity sensor Initialization.
|
|
*/
|
|
void HTS221_H_Init(uint16_t DeviceAddr)
|
|
{
|
|
80015bc: b580 push {r7, lr}
|
|
80015be: b084 sub sp, #16
|
|
80015c0: af00 add r7, sp, #0
|
|
80015c2: 4603 mov r3, r0
|
|
80015c4: 80fb strh r3, [r7, #6]
|
|
uint8_t tmp;
|
|
|
|
/* Read CTRL_REG1 */
|
|
tmp = SENSOR_IO_Read(DeviceAddr, HTS221_CTRL_REG1);
|
|
80015c6: 88fb ldrh r3, [r7, #6]
|
|
80015c8: b2db uxtb r3, r3
|
|
80015ca: 2120 movs r1, #32
|
|
80015cc: 4618 mov r0, r3
|
|
80015ce: f7ff fe3b bl 8001248 <SENSOR_IO_Read>
|
|
80015d2: 4603 mov r3, r0
|
|
80015d4: 73fb strb r3, [r7, #15]
|
|
|
|
/* Enable BDU */
|
|
tmp &= ~HTS221_BDU_MASK;
|
|
80015d6: 7bfb ldrb r3, [r7, #15]
|
|
80015d8: f023 0304 bic.w r3, r3, #4
|
|
80015dc: 73fb strb r3, [r7, #15]
|
|
tmp |= (1 << HTS221_BDU_BIT);
|
|
80015de: 7bfb ldrb r3, [r7, #15]
|
|
80015e0: f043 0304 orr.w r3, r3, #4
|
|
80015e4: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set default ODR */
|
|
tmp &= ~HTS221_ODR_MASK;
|
|
80015e6: 7bfb ldrb r3, [r7, #15]
|
|
80015e8: f023 0303 bic.w r3, r3, #3
|
|
80015ec: 73fb strb r3, [r7, #15]
|
|
tmp |= (uint8_t)0x01; /* Set ODR to 1Hz */
|
|
80015ee: 7bfb ldrb r3, [r7, #15]
|
|
80015f0: f043 0301 orr.w r3, r3, #1
|
|
80015f4: 73fb strb r3, [r7, #15]
|
|
|
|
/* Activate the device */
|
|
tmp |= HTS221_PD_MASK;
|
|
80015f6: 7bfb ldrb r3, [r7, #15]
|
|
80015f8: f063 037f orn r3, r3, #127 @ 0x7f
|
|
80015fc: 73fb strb r3, [r7, #15]
|
|
|
|
/* Apply settings to CTRL_REG1 */
|
|
SENSOR_IO_Write(DeviceAddr, HTS221_CTRL_REG1, tmp);
|
|
80015fe: 88fb ldrh r3, [r7, #6]
|
|
8001600: b2db uxtb r3, r3
|
|
8001602: 7bfa ldrb r2, [r7, #15]
|
|
8001604: 2120 movs r1, #32
|
|
8001606: 4618 mov r0, r3
|
|
8001608: f7ff fe04 bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
800160c: bf00 nop
|
|
800160e: 3710 adds r7, #16
|
|
8001610: 46bd mov sp, r7
|
|
8001612: bd80 pop {r7, pc}
|
|
|
|
08001614 <HTS221_H_ReadID>:
|
|
/**
|
|
* @brief Read HTS221 ID.
|
|
* @retval ID
|
|
*/
|
|
uint8_t HTS221_H_ReadID(uint16_t DeviceAddr)
|
|
{
|
|
8001614: b580 push {r7, lr}
|
|
8001616: b084 sub sp, #16
|
|
8001618: af00 add r7, sp, #0
|
|
800161a: 4603 mov r3, r0
|
|
800161c: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
800161e: 2300 movs r3, #0
|
|
8001620: 73fb strb r3, [r7, #15]
|
|
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
8001622: f7ff fded bl 8001200 <SENSOR_IO_Init>
|
|
|
|
/* Read value at Who am I register address */
|
|
ctrl = SENSOR_IO_Read(DeviceAddr, HTS221_WHO_AM_I_REG);
|
|
8001626: 88fb ldrh r3, [r7, #6]
|
|
8001628: b2db uxtb r3, r3
|
|
800162a: 210f movs r1, #15
|
|
800162c: 4618 mov r0, r3
|
|
800162e: f7ff fe0b bl 8001248 <SENSOR_IO_Read>
|
|
8001632: 4603 mov r3, r0
|
|
8001634: 73fb strb r3, [r7, #15]
|
|
|
|
return ctrl;
|
|
8001636: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001638: 4618 mov r0, r3
|
|
800163a: 3710 adds r7, #16
|
|
800163c: 46bd mov sp, r7
|
|
800163e: bd80 pop {r7, pc}
|
|
|
|
08001640 <HTS221_H_ReadHumidity>:
|
|
/**
|
|
* @brief Read humidity value of HTS221
|
|
* @retval humidity value;
|
|
*/
|
|
float HTS221_H_ReadHumidity(uint16_t DeviceAddr)
|
|
{
|
|
8001640: b580 push {r7, lr}
|
|
8001642: b088 sub sp, #32
|
|
8001644: af00 add r7, sp, #0
|
|
8001646: 4603 mov r3, r0
|
|
8001648: 80fb strh r3, [r7, #6]
|
|
int16_t H0_T0_out, H1_T0_out, H_T_out;
|
|
int16_t H0_rh, H1_rh;
|
|
uint8_t buffer[2];
|
|
float tmp_f;
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_H0_RH_X2 | 0x80), buffer, 2);
|
|
800164a: 88fb ldrh r3, [r7, #6]
|
|
800164c: b2d8 uxtb r0, r3
|
|
800164e: f107 020c add.w r2, r7, #12
|
|
8001652: 2302 movs r3, #2
|
|
8001654: 21b0 movs r1, #176 @ 0xb0
|
|
8001656: f7ff fe15 bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
H0_rh = buffer[0] >> 1;
|
|
800165a: 7b3b ldrb r3, [r7, #12]
|
|
800165c: 085b lsrs r3, r3, #1
|
|
800165e: b2db uxtb r3, r3
|
|
8001660: 83fb strh r3, [r7, #30]
|
|
H1_rh = buffer[1] >> 1;
|
|
8001662: 7b7b ldrb r3, [r7, #13]
|
|
8001664: 085b lsrs r3, r3, #1
|
|
8001666: b2db uxtb r3, r3
|
|
8001668: 83bb strh r3, [r7, #28]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_H0_T0_OUT_L | 0x80), buffer, 2);
|
|
800166a: 88fb ldrh r3, [r7, #6]
|
|
800166c: b2d8 uxtb r0, r3
|
|
800166e: f107 020c add.w r2, r7, #12
|
|
8001672: 2302 movs r3, #2
|
|
8001674: 21b6 movs r1, #182 @ 0xb6
|
|
8001676: f7ff fe05 bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
H0_T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
800167a: 7b7b ldrb r3, [r7, #13]
|
|
800167c: b21b sxth r3, r3
|
|
800167e: 021b lsls r3, r3, #8
|
|
8001680: b21a sxth r2, r3
|
|
8001682: 7b3b ldrb r3, [r7, #12]
|
|
8001684: b21b sxth r3, r3
|
|
8001686: 4313 orrs r3, r2
|
|
8001688: 837b strh r3, [r7, #26]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_H1_T0_OUT_L | 0x80), buffer, 2);
|
|
800168a: 88fb ldrh r3, [r7, #6]
|
|
800168c: b2d8 uxtb r0, r3
|
|
800168e: f107 020c add.w r2, r7, #12
|
|
8001692: 2302 movs r3, #2
|
|
8001694: 21ba movs r1, #186 @ 0xba
|
|
8001696: f7ff fdf5 bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
H1_T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
800169a: 7b7b ldrb r3, [r7, #13]
|
|
800169c: b21b sxth r3, r3
|
|
800169e: 021b lsls r3, r3, #8
|
|
80016a0: b21a sxth r2, r3
|
|
80016a2: 7b3b ldrb r3, [r7, #12]
|
|
80016a4: b21b sxth r3, r3
|
|
80016a6: 4313 orrs r3, r2
|
|
80016a8: 833b strh r3, [r7, #24]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_HR_OUT_L_REG | 0x80), buffer, 2);
|
|
80016aa: 88fb ldrh r3, [r7, #6]
|
|
80016ac: b2d8 uxtb r0, r3
|
|
80016ae: f107 020c add.w r2, r7, #12
|
|
80016b2: 2302 movs r3, #2
|
|
80016b4: 21a8 movs r1, #168 @ 0xa8
|
|
80016b6: f7ff fde5 bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
H_T_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
80016ba: 7b7b ldrb r3, [r7, #13]
|
|
80016bc: b21b sxth r3, r3
|
|
80016be: 021b lsls r3, r3, #8
|
|
80016c0: b21a sxth r2, r3
|
|
80016c2: 7b3b ldrb r3, [r7, #12]
|
|
80016c4: b21b sxth r3, r3
|
|
80016c6: 4313 orrs r3, r2
|
|
80016c8: 82fb strh r3, [r7, #22]
|
|
|
|
tmp_f = (float)(H_T_out - H0_T0_out) * (float)(H1_rh - H0_rh) / (float)(H1_T0_out - H0_T0_out) + H0_rh;
|
|
80016ca: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80016ce: f9b7 301a ldrsh.w r3, [r7, #26]
|
|
80016d2: 1ad3 subs r3, r2, r3
|
|
80016d4: ee07 3a90 vmov s15, r3
|
|
80016d8: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80016dc: f9b7 201c ldrsh.w r2, [r7, #28]
|
|
80016e0: f9b7 301e ldrsh.w r3, [r7, #30]
|
|
80016e4: 1ad3 subs r3, r2, r3
|
|
80016e6: ee07 3a90 vmov s15, r3
|
|
80016ea: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80016ee: ee67 6a27 vmul.f32 s13, s14, s15
|
|
80016f2: f9b7 2018 ldrsh.w r2, [r7, #24]
|
|
80016f6: f9b7 301a ldrsh.w r3, [r7, #26]
|
|
80016fa: 1ad3 subs r3, r2, r3
|
|
80016fc: ee07 3a90 vmov s15, r3
|
|
8001700: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001704: ee86 7aa7 vdiv.f32 s14, s13, s15
|
|
8001708: f9b7 301e ldrsh.w r3, [r7, #30]
|
|
800170c: ee07 3a90 vmov s15, r3
|
|
8001710: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001714: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001718: edc7 7a04 vstr s15, [r7, #16]
|
|
tmp_f *= 10.0f;
|
|
800171c: edd7 7a04 vldr s15, [r7, #16]
|
|
8001720: eeb2 7a04 vmov.f32 s14, #36 @ 0x41200000 10.0
|
|
8001724: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001728: edc7 7a04 vstr s15, [r7, #16]
|
|
|
|
tmp_f = ( tmp_f > 1000.0f ) ? 1000.0f
|
|
: ( tmp_f < 0.0f ) ? 0.0f
|
|
800172c: edd7 7a04 vldr s15, [r7, #16]
|
|
8001730: ed9f 7a10 vldr s14, [pc, #64] @ 8001774 <HTS221_H_ReadHumidity+0x134>
|
|
8001734: eef4 7ac7 vcmpe.f32 s15, s14
|
|
8001738: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
800173c: dd01 ble.n 8001742 <HTS221_H_ReadHumidity+0x102>
|
|
800173e: 4b0e ldr r3, [pc, #56] @ (8001778 <HTS221_H_ReadHumidity+0x138>)
|
|
8001740: e00a b.n 8001758 <HTS221_H_ReadHumidity+0x118>
|
|
: tmp_f;
|
|
8001742: edd7 7a04 vldr s15, [r7, #16]
|
|
8001746: eef5 7ac0 vcmpe.f32 s15, #0.0
|
|
800174a: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
800174e: d502 bpl.n 8001756 <HTS221_H_ReadHumidity+0x116>
|
|
8001750: f04f 0300 mov.w r3, #0
|
|
8001754: e000 b.n 8001758 <HTS221_H_ReadHumidity+0x118>
|
|
8001756: 693b ldr r3, [r7, #16]
|
|
tmp_f = ( tmp_f > 1000.0f ) ? 1000.0f
|
|
8001758: 613b str r3, [r7, #16]
|
|
|
|
return (tmp_f / 10.0f);
|
|
800175a: edd7 7a04 vldr s15, [r7, #16]
|
|
800175e: eeb2 7a04 vmov.f32 s14, #36 @ 0x41200000 10.0
|
|
8001762: eec7 6a87 vdiv.f32 s13, s15, s14
|
|
8001766: eef0 7a66 vmov.f32 s15, s13
|
|
}
|
|
800176a: eeb0 0a67 vmov.f32 s0, s15
|
|
800176e: 3720 adds r7, #32
|
|
8001770: 46bd mov sp, r7
|
|
8001772: bd80 pop {r7, pc}
|
|
8001774: 447a0000 .word 0x447a0000
|
|
8001778: 447a0000 .word 0x447a0000
|
|
|
|
0800177c <HTS221_T_Init>:
|
|
* @param DeviceAddr: I2C device address
|
|
* @param InitStruct: pointer to a TSENSOR_InitTypeDef structure
|
|
* that contains the configuration setting for the HTS221.
|
|
*/
|
|
void HTS221_T_Init(uint16_t DeviceAddr, TSENSOR_InitTypeDef *pInitStruct)
|
|
{
|
|
800177c: b580 push {r7, lr}
|
|
800177e: b084 sub sp, #16
|
|
8001780: af00 add r7, sp, #0
|
|
8001782: 4603 mov r3, r0
|
|
8001784: 6039 str r1, [r7, #0]
|
|
8001786: 80fb strh r3, [r7, #6]
|
|
uint8_t tmp;
|
|
|
|
/* Read CTRL_REG1 */
|
|
tmp = SENSOR_IO_Read(DeviceAddr, HTS221_CTRL_REG1);
|
|
8001788: 88fb ldrh r3, [r7, #6]
|
|
800178a: b2db uxtb r3, r3
|
|
800178c: 2120 movs r1, #32
|
|
800178e: 4618 mov r0, r3
|
|
8001790: f7ff fd5a bl 8001248 <SENSOR_IO_Read>
|
|
8001794: 4603 mov r3, r0
|
|
8001796: 73fb strb r3, [r7, #15]
|
|
|
|
/* Enable BDU */
|
|
tmp &= ~HTS221_BDU_MASK;
|
|
8001798: 7bfb ldrb r3, [r7, #15]
|
|
800179a: f023 0304 bic.w r3, r3, #4
|
|
800179e: 73fb strb r3, [r7, #15]
|
|
tmp |= (1 << HTS221_BDU_BIT);
|
|
80017a0: 7bfb ldrb r3, [r7, #15]
|
|
80017a2: f043 0304 orr.w r3, r3, #4
|
|
80017a6: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set default ODR */
|
|
tmp &= ~HTS221_ODR_MASK;
|
|
80017a8: 7bfb ldrb r3, [r7, #15]
|
|
80017aa: f023 0303 bic.w r3, r3, #3
|
|
80017ae: 73fb strb r3, [r7, #15]
|
|
tmp |= (uint8_t)0x01; /* Set ODR to 1Hz */
|
|
80017b0: 7bfb ldrb r3, [r7, #15]
|
|
80017b2: f043 0301 orr.w r3, r3, #1
|
|
80017b6: 73fb strb r3, [r7, #15]
|
|
|
|
/* Activate the device */
|
|
tmp |= HTS221_PD_MASK;
|
|
80017b8: 7bfb ldrb r3, [r7, #15]
|
|
80017ba: f063 037f orn r3, r3, #127 @ 0x7f
|
|
80017be: 73fb strb r3, [r7, #15]
|
|
|
|
/* Apply settings to CTRL_REG1 */
|
|
SENSOR_IO_Write(DeviceAddr, HTS221_CTRL_REG1, tmp);
|
|
80017c0: 88fb ldrh r3, [r7, #6]
|
|
80017c2: b2db uxtb r3, r3
|
|
80017c4: 7bfa ldrb r2, [r7, #15]
|
|
80017c6: 2120 movs r1, #32
|
|
80017c8: 4618 mov r0, r3
|
|
80017ca: f7ff fd23 bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
80017ce: bf00 nop
|
|
80017d0: 3710 adds r7, #16
|
|
80017d2: 46bd mov sp, r7
|
|
80017d4: bd80 pop {r7, pc}
|
|
|
|
080017d6 <HTS221_T_ReadTemp>:
|
|
* @brief Read temperature value of HTS221
|
|
* @param DeviceAddr: I2C device address
|
|
* @retval temperature value
|
|
*/
|
|
float HTS221_T_ReadTemp(uint16_t DeviceAddr)
|
|
{
|
|
80017d6: b580 push {r7, lr}
|
|
80017d8: b088 sub sp, #32
|
|
80017da: af00 add r7, sp, #0
|
|
80017dc: 4603 mov r3, r0
|
|
80017de: 80fb strh r3, [r7, #6]
|
|
int16_t T0_out, T1_out, T_out, T0_degC_x8_u16, T1_degC_x8_u16;
|
|
int16_t T0_degC, T1_degC;
|
|
uint8_t buffer[4], tmp;
|
|
float tmp_f;
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_T0_DEGC_X8 | 0x80), buffer, 2);
|
|
80017e0: 88fb ldrh r3, [r7, #6]
|
|
80017e2: b2d8 uxtb r0, r3
|
|
80017e4: f107 0208 add.w r2, r7, #8
|
|
80017e8: 2302 movs r3, #2
|
|
80017ea: 21b2 movs r1, #178 @ 0xb2
|
|
80017ec: f7ff fd4a bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
tmp = SENSOR_IO_Read(DeviceAddr, HTS221_T0_T1_DEGC_H2);
|
|
80017f0: 88fb ldrh r3, [r7, #6]
|
|
80017f2: b2db uxtb r3, r3
|
|
80017f4: 2135 movs r1, #53 @ 0x35
|
|
80017f6: 4618 mov r0, r3
|
|
80017f8: f7ff fd26 bl 8001248 <SENSOR_IO_Read>
|
|
80017fc: 4603 mov r3, r0
|
|
80017fe: 77fb strb r3, [r7, #31]
|
|
|
|
T0_degC_x8_u16 = (((uint16_t)(tmp & 0x03)) << 8) | ((uint16_t)buffer[0]);
|
|
8001800: 7ffb ldrb r3, [r7, #31]
|
|
8001802: b21b sxth r3, r3
|
|
8001804: 021b lsls r3, r3, #8
|
|
8001806: b21b sxth r3, r3
|
|
8001808: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800180c: b21a sxth r2, r3
|
|
800180e: 7a3b ldrb r3, [r7, #8]
|
|
8001810: b21b sxth r3, r3
|
|
8001812: 4313 orrs r3, r2
|
|
8001814: 83bb strh r3, [r7, #28]
|
|
T1_degC_x8_u16 = (((uint16_t)(tmp & 0x0C)) << 6) | ((uint16_t)buffer[1]);
|
|
8001816: 7ffb ldrb r3, [r7, #31]
|
|
8001818: b21b sxth r3, r3
|
|
800181a: 019b lsls r3, r3, #6
|
|
800181c: b21b sxth r3, r3
|
|
800181e: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8001822: b21a sxth r2, r3
|
|
8001824: 7a7b ldrb r3, [r7, #9]
|
|
8001826: b21b sxth r3, r3
|
|
8001828: 4313 orrs r3, r2
|
|
800182a: 837b strh r3, [r7, #26]
|
|
T0_degC = T0_degC_x8_u16 >> 3;
|
|
800182c: f9b7 301c ldrsh.w r3, [r7, #28]
|
|
8001830: 10db asrs r3, r3, #3
|
|
8001832: 833b strh r3, [r7, #24]
|
|
T1_degC = T1_degC_x8_u16 >> 3;
|
|
8001834: f9b7 301a ldrsh.w r3, [r7, #26]
|
|
8001838: 10db asrs r3, r3, #3
|
|
800183a: 82fb strh r3, [r7, #22]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_T0_OUT_L | 0x80), buffer, 4);
|
|
800183c: 88fb ldrh r3, [r7, #6]
|
|
800183e: b2d8 uxtb r0, r3
|
|
8001840: f107 0208 add.w r2, r7, #8
|
|
8001844: 2304 movs r3, #4
|
|
8001846: 21bc movs r1, #188 @ 0xbc
|
|
8001848: f7ff fd1c bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
800184c: 7a7b ldrb r3, [r7, #9]
|
|
800184e: b21b sxth r3, r3
|
|
8001850: 021b lsls r3, r3, #8
|
|
8001852: b21a sxth r2, r3
|
|
8001854: 7a3b ldrb r3, [r7, #8]
|
|
8001856: b21b sxth r3, r3
|
|
8001858: 4313 orrs r3, r2
|
|
800185a: 82bb strh r3, [r7, #20]
|
|
T1_out = (((uint16_t)buffer[3]) << 8) | (uint16_t)buffer[2];
|
|
800185c: 7afb ldrb r3, [r7, #11]
|
|
800185e: b21b sxth r3, r3
|
|
8001860: 021b lsls r3, r3, #8
|
|
8001862: b21a sxth r2, r3
|
|
8001864: 7abb ldrb r3, [r7, #10]
|
|
8001866: b21b sxth r3, r3
|
|
8001868: 4313 orrs r3, r2
|
|
800186a: 827b strh r3, [r7, #18]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_TEMP_OUT_L_REG | 0x80), buffer, 2);
|
|
800186c: 88fb ldrh r3, [r7, #6]
|
|
800186e: b2d8 uxtb r0, r3
|
|
8001870: f107 0208 add.w r2, r7, #8
|
|
8001874: 2302 movs r3, #2
|
|
8001876: 21aa movs r1, #170 @ 0xaa
|
|
8001878: f7ff fd04 bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
T_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
800187c: 7a7b ldrb r3, [r7, #9]
|
|
800187e: b21b sxth r3, r3
|
|
8001880: 021b lsls r3, r3, #8
|
|
8001882: b21a sxth r2, r3
|
|
8001884: 7a3b ldrb r3, [r7, #8]
|
|
8001886: b21b sxth r3, r3
|
|
8001888: 4313 orrs r3, r2
|
|
800188a: 823b strh r3, [r7, #16]
|
|
|
|
tmp_f = (float)(T_out - T0_out) * (float)(T1_degC - T0_degC) / (float)(T1_out - T0_out) + T0_degC;
|
|
800188c: f9b7 2010 ldrsh.w r2, [r7, #16]
|
|
8001890: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
8001894: 1ad3 subs r3, r2, r3
|
|
8001896: ee07 3a90 vmov s15, r3
|
|
800189a: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
800189e: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80018a2: f9b7 3018 ldrsh.w r3, [r7, #24]
|
|
80018a6: 1ad3 subs r3, r2, r3
|
|
80018a8: ee07 3a90 vmov s15, r3
|
|
80018ac: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80018b0: ee67 6a27 vmul.f32 s13, s14, s15
|
|
80018b4: f9b7 2012 ldrsh.w r2, [r7, #18]
|
|
80018b8: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
80018bc: 1ad3 subs r3, r2, r3
|
|
80018be: ee07 3a90 vmov s15, r3
|
|
80018c2: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80018c6: ee86 7aa7 vdiv.f32 s14, s13, s15
|
|
80018ca: f9b7 3018 ldrsh.w r3, [r7, #24]
|
|
80018ce: ee07 3a90 vmov s15, r3
|
|
80018d2: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80018d6: ee77 7a27 vadd.f32 s15, s14, s15
|
|
80018da: edc7 7a03 vstr s15, [r7, #12]
|
|
|
|
return tmp_f;
|
|
80018de: 68fb ldr r3, [r7, #12]
|
|
80018e0: ee07 3a90 vmov s15, r3
|
|
}
|
|
80018e4: eeb0 0a67 vmov.f32 s0, s15
|
|
80018e8: 3720 adds r7, #32
|
|
80018ea: 46bd mov sp, r7
|
|
80018ec: bd80 pop {r7, pc}
|
|
|
|
080018ee <LIS3MDL_MagInit>:
|
|
* @brief Set LIS3MDL Magnetometer Initialization.
|
|
* @param LIS3MDL_InitStruct: pointer to a LIS3MDL_MagInitTypeDef structure
|
|
* that contains the configuration setting for the LIS3MDL.
|
|
*/
|
|
void LIS3MDL_MagInit(MAGNETO_InitTypeDef LIS3MDL_InitStruct)
|
|
{
|
|
80018ee: b580 push {r7, lr}
|
|
80018f0: b082 sub sp, #8
|
|
80018f2: af00 add r7, sp, #0
|
|
80018f4: 463b mov r3, r7
|
|
80018f6: e883 0003 stmia.w r3, {r0, r1}
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG1, LIS3MDL_InitStruct.Register1);
|
|
80018fa: 783b ldrb r3, [r7, #0]
|
|
80018fc: 461a mov r2, r3
|
|
80018fe: 2120 movs r1, #32
|
|
8001900: 203c movs r0, #60 @ 0x3c
|
|
8001902: f7ff fc87 bl 8001214 <SENSOR_IO_Write>
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG2, LIS3MDL_InitStruct.Register2);
|
|
8001906: 787b ldrb r3, [r7, #1]
|
|
8001908: 461a mov r2, r3
|
|
800190a: 2121 movs r1, #33 @ 0x21
|
|
800190c: 203c movs r0, #60 @ 0x3c
|
|
800190e: f7ff fc81 bl 8001214 <SENSOR_IO_Write>
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3, LIS3MDL_InitStruct.Register3);
|
|
8001912: 78bb ldrb r3, [r7, #2]
|
|
8001914: 461a mov r2, r3
|
|
8001916: 2122 movs r1, #34 @ 0x22
|
|
8001918: 203c movs r0, #60 @ 0x3c
|
|
800191a: f7ff fc7b bl 8001214 <SENSOR_IO_Write>
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG4, LIS3MDL_InitStruct.Register4);
|
|
800191e: 78fb ldrb r3, [r7, #3]
|
|
8001920: 461a mov r2, r3
|
|
8001922: 2123 movs r1, #35 @ 0x23
|
|
8001924: 203c movs r0, #60 @ 0x3c
|
|
8001926: f7ff fc75 bl 8001214 <SENSOR_IO_Write>
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG5, LIS3MDL_InitStruct.Register5);
|
|
800192a: 793b ldrb r3, [r7, #4]
|
|
800192c: 461a mov r2, r3
|
|
800192e: 2124 movs r1, #36 @ 0x24
|
|
8001930: 203c movs r0, #60 @ 0x3c
|
|
8001932: f7ff fc6f bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001936: bf00 nop
|
|
8001938: 3708 adds r7, #8
|
|
800193a: 46bd mov sp, r7
|
|
800193c: bd80 pop {r7, pc}
|
|
|
|
0800193e <LIS3MDL_MagDeInit>:
|
|
|
|
/**
|
|
* @brief LIS3MDL Magnetometer De-initialization.
|
|
*/
|
|
void LIS3MDL_MagDeInit(void)
|
|
{
|
|
800193e: b580 push {r7, lr}
|
|
8001940: b082 sub sp, #8
|
|
8001942: af00 add r7, sp, #0
|
|
uint8_t ctrl = 0x00;
|
|
8001944: 2300 movs r3, #0
|
|
8001946: 71fb strb r3, [r7, #7]
|
|
|
|
/* Read control register 1 value */
|
|
ctrl = SENSOR_IO_Read(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3);
|
|
8001948: 2122 movs r1, #34 @ 0x22
|
|
800194a: 203c movs r0, #60 @ 0x3c
|
|
800194c: f7ff fc7c bl 8001248 <SENSOR_IO_Read>
|
|
8001950: 4603 mov r3, r0
|
|
8001952: 71fb strb r3, [r7, #7]
|
|
|
|
/* Clear Selection Mode bits */
|
|
ctrl &= ~(LIS3MDL_MAG_SELECTION_MODE);
|
|
8001954: 79fb ldrb r3, [r7, #7]
|
|
8001956: f023 0303 bic.w r3, r3, #3
|
|
800195a: 71fb strb r3, [r7, #7]
|
|
|
|
/* Set Power down */
|
|
ctrl |= LIS3MDL_MAG_POWERDOWN2_MODE;
|
|
800195c: 79fb ldrb r3, [r7, #7]
|
|
800195e: f043 0303 orr.w r3, r3, #3
|
|
8001962: 71fb strb r3, [r7, #7]
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3, ctrl);
|
|
8001964: 79fb ldrb r3, [r7, #7]
|
|
8001966: 461a mov r2, r3
|
|
8001968: 2122 movs r1, #34 @ 0x22
|
|
800196a: 203c movs r0, #60 @ 0x3c
|
|
800196c: f7ff fc52 bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001970: bf00 nop
|
|
8001972: 3708 adds r7, #8
|
|
8001974: 46bd mov sp, r7
|
|
8001976: bd80 pop {r7, pc}
|
|
|
|
08001978 <LIS3MDL_MagReadID>:
|
|
/**
|
|
* @brief Read LIS3MDL ID.
|
|
* @retval ID
|
|
*/
|
|
uint8_t LIS3MDL_MagReadID(void)
|
|
{
|
|
8001978: b580 push {r7, lr}
|
|
800197a: af00 add r7, sp, #0
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
800197c: f7ff fc40 bl 8001200 <SENSOR_IO_Init>
|
|
/* Read value at Who am I register address */
|
|
return (SENSOR_IO_Read(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_WHO_AM_I_REG));
|
|
8001980: 210f movs r1, #15
|
|
8001982: 203c movs r0, #60 @ 0x3c
|
|
8001984: f7ff fc60 bl 8001248 <SENSOR_IO_Read>
|
|
8001988: 4603 mov r3, r0
|
|
}
|
|
800198a: 4618 mov r0, r3
|
|
800198c: bd80 pop {r7, pc}
|
|
|
|
0800198e <LIS3MDL_MagLowPower>:
|
|
/**
|
|
* @brief Set/Unset Magnetometer in low power mode.
|
|
* @param status 0 means disable Low Power Mode, otherwise Low Power Mode is enabled
|
|
*/
|
|
void LIS3MDL_MagLowPower(uint16_t status)
|
|
{
|
|
800198e: b580 push {r7, lr}
|
|
8001990: b084 sub sp, #16
|
|
8001992: af00 add r7, sp, #0
|
|
8001994: 4603 mov r3, r0
|
|
8001996: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0;
|
|
8001998: 2300 movs r3, #0
|
|
800199a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Read control register 1 value */
|
|
ctrl = SENSOR_IO_Read(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3);
|
|
800199c: 2122 movs r1, #34 @ 0x22
|
|
800199e: 203c movs r0, #60 @ 0x3c
|
|
80019a0: f7ff fc52 bl 8001248 <SENSOR_IO_Read>
|
|
80019a4: 4603 mov r3, r0
|
|
80019a6: 73fb strb r3, [r7, #15]
|
|
|
|
/* Clear Low Power Mode bit */
|
|
ctrl &= ~(0x20);
|
|
80019a8: 7bfb ldrb r3, [r7, #15]
|
|
80019aa: f023 0320 bic.w r3, r3, #32
|
|
80019ae: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set Low Power Mode */
|
|
if(status)
|
|
80019b0: 88fb ldrh r3, [r7, #6]
|
|
80019b2: 2b00 cmp r3, #0
|
|
80019b4: d003 beq.n 80019be <LIS3MDL_MagLowPower+0x30>
|
|
{
|
|
ctrl |= LIS3MDL_MAG_CONFIG_LOWPOWER_MODE;
|
|
80019b6: 7bfb ldrb r3, [r7, #15]
|
|
80019b8: f043 0320 orr.w r3, r3, #32
|
|
80019bc: 73fb strb r3, [r7, #15]
|
|
{
|
|
ctrl |= LIS3MDL_MAG_CONFIG_NORMAL_MODE;
|
|
}
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3, ctrl);
|
|
80019be: 7bfb ldrb r3, [r7, #15]
|
|
80019c0: 461a mov r2, r3
|
|
80019c2: 2122 movs r1, #34 @ 0x22
|
|
80019c4: 203c movs r0, #60 @ 0x3c
|
|
80019c6: f7ff fc25 bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
80019ca: bf00 nop
|
|
80019cc: 3710 adds r7, #16
|
|
80019ce: 46bd mov sp, r7
|
|
80019d0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080019d4 <LIS3MDL_MagReadXYZ>:
|
|
/**
|
|
* @brief Read X, Y & Z Magnetometer values
|
|
* @param pData: Data out pointer
|
|
*/
|
|
void LIS3MDL_MagReadXYZ(int16_t* pData)
|
|
{
|
|
80019d4: b580 push {r7, lr}
|
|
80019d6: b088 sub sp, #32
|
|
80019d8: af00 add r7, sp, #0
|
|
80019da: 6078 str r0, [r7, #4]
|
|
int16_t pnRawData[3];
|
|
uint8_t ctrlm= 0;
|
|
80019dc: 2300 movs r3, #0
|
|
80019de: 75fb strb r3, [r7, #23]
|
|
uint8_t buffer[6];
|
|
uint8_t i = 0;
|
|
80019e0: 2300 movs r3, #0
|
|
80019e2: 77fb strb r3, [r7, #31]
|
|
float sensitivity = 0;
|
|
80019e4: f04f 0300 mov.w r3, #0
|
|
80019e8: 61bb str r3, [r7, #24]
|
|
|
|
/* Read the magnetometer control register content */
|
|
ctrlm = SENSOR_IO_Read(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG2);
|
|
80019ea: 2121 movs r1, #33 @ 0x21
|
|
80019ec: 203c movs r0, #60 @ 0x3c
|
|
80019ee: f7ff fc2b bl 8001248 <SENSOR_IO_Read>
|
|
80019f2: 4603 mov r3, r0
|
|
80019f4: 75fb strb r3, [r7, #23]
|
|
|
|
/* Read output register X, Y & Z acceleration */
|
|
SENSOR_IO_ReadMultiple(LIS3MDL_MAG_I2C_ADDRESS_HIGH, (LIS3MDL_MAG_OUTX_L | 0x80), buffer, 6);
|
|
80019f6: f107 0208 add.w r2, r7, #8
|
|
80019fa: 2306 movs r3, #6
|
|
80019fc: 21a8 movs r1, #168 @ 0xa8
|
|
80019fe: 203c movs r0, #60 @ 0x3c
|
|
8001a00: f7ff fc40 bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
for(i=0; i<3; i++)
|
|
8001a04: 2300 movs r3, #0
|
|
8001a06: 77fb strb r3, [r7, #31]
|
|
8001a08: e01a b.n 8001a40 <LIS3MDL_MagReadXYZ+0x6c>
|
|
{
|
|
pnRawData[i]=((((uint16_t)buffer[2*i+1]) << 8) + (uint16_t)buffer[2*i]);
|
|
8001a0a: 7ffb ldrb r3, [r7, #31]
|
|
8001a0c: 005b lsls r3, r3, #1
|
|
8001a0e: 3301 adds r3, #1
|
|
8001a10: 3320 adds r3, #32
|
|
8001a12: 443b add r3, r7
|
|
8001a14: f813 3c18 ldrb.w r3, [r3, #-24]
|
|
8001a18: 021b lsls r3, r3, #8
|
|
8001a1a: b29b uxth r3, r3
|
|
8001a1c: 7ffa ldrb r2, [r7, #31]
|
|
8001a1e: 0052 lsls r2, r2, #1
|
|
8001a20: 3220 adds r2, #32
|
|
8001a22: 443a add r2, r7
|
|
8001a24: f812 2c18 ldrb.w r2, [r2, #-24]
|
|
8001a28: 4413 add r3, r2
|
|
8001a2a: b29a uxth r2, r3
|
|
8001a2c: 7ffb ldrb r3, [r7, #31]
|
|
8001a2e: b212 sxth r2, r2
|
|
8001a30: 005b lsls r3, r3, #1
|
|
8001a32: 3320 adds r3, #32
|
|
8001a34: 443b add r3, r7
|
|
8001a36: f823 2c10 strh.w r2, [r3, #-16]
|
|
for(i=0; i<3; i++)
|
|
8001a3a: 7ffb ldrb r3, [r7, #31]
|
|
8001a3c: 3301 adds r3, #1
|
|
8001a3e: 77fb strb r3, [r7, #31]
|
|
8001a40: 7ffb ldrb r3, [r7, #31]
|
|
8001a42: 2b02 cmp r3, #2
|
|
8001a44: d9e1 bls.n 8001a0a <LIS3MDL_MagReadXYZ+0x36>
|
|
}
|
|
|
|
/* Normal mode */
|
|
/* Switch the sensitivity value set in the CRTL_REG2 */
|
|
switch(ctrlm & 0x60)
|
|
8001a46: 7dfb ldrb r3, [r7, #23]
|
|
8001a48: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8001a4c: 2b60 cmp r3, #96 @ 0x60
|
|
8001a4e: d013 beq.n 8001a78 <LIS3MDL_MagReadXYZ+0xa4>
|
|
8001a50: 2b60 cmp r3, #96 @ 0x60
|
|
8001a52: dc14 bgt.n 8001a7e <LIS3MDL_MagReadXYZ+0xaa>
|
|
8001a54: 2b40 cmp r3, #64 @ 0x40
|
|
8001a56: d00c beq.n 8001a72 <LIS3MDL_MagReadXYZ+0x9e>
|
|
8001a58: 2b40 cmp r3, #64 @ 0x40
|
|
8001a5a: dc10 bgt.n 8001a7e <LIS3MDL_MagReadXYZ+0xaa>
|
|
8001a5c: 2b00 cmp r3, #0
|
|
8001a5e: d002 beq.n 8001a66 <LIS3MDL_MagReadXYZ+0x92>
|
|
8001a60: 2b20 cmp r3, #32
|
|
8001a62: d003 beq.n 8001a6c <LIS3MDL_MagReadXYZ+0x98>
|
|
8001a64: e00b b.n 8001a7e <LIS3MDL_MagReadXYZ+0xaa>
|
|
{
|
|
case LIS3MDL_MAG_FS_4_GA:
|
|
sensitivity = LIS3MDL_MAG_SENSITIVITY_FOR_FS_4GA;
|
|
8001a66: 4b19 ldr r3, [pc, #100] @ (8001acc <LIS3MDL_MagReadXYZ+0xf8>)
|
|
8001a68: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001a6a: e008 b.n 8001a7e <LIS3MDL_MagReadXYZ+0xaa>
|
|
case LIS3MDL_MAG_FS_8_GA:
|
|
sensitivity = LIS3MDL_MAG_SENSITIVITY_FOR_FS_8GA;
|
|
8001a6c: 4b18 ldr r3, [pc, #96] @ (8001ad0 <LIS3MDL_MagReadXYZ+0xfc>)
|
|
8001a6e: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001a70: e005 b.n 8001a7e <LIS3MDL_MagReadXYZ+0xaa>
|
|
case LIS3MDL_MAG_FS_12_GA:
|
|
sensitivity = LIS3MDL_MAG_SENSITIVITY_FOR_FS_12GA;
|
|
8001a72: 4b18 ldr r3, [pc, #96] @ (8001ad4 <LIS3MDL_MagReadXYZ+0x100>)
|
|
8001a74: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001a76: e002 b.n 8001a7e <LIS3MDL_MagReadXYZ+0xaa>
|
|
case LIS3MDL_MAG_FS_16_GA:
|
|
sensitivity = LIS3MDL_MAG_SENSITIVITY_FOR_FS_16GA;
|
|
8001a78: 4b17 ldr r3, [pc, #92] @ (8001ad8 <LIS3MDL_MagReadXYZ+0x104>)
|
|
8001a7a: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001a7c: bf00 nop
|
|
}
|
|
|
|
/* Obtain the mGauss value for the three axis */
|
|
for(i=0; i<3; i++)
|
|
8001a7e: 2300 movs r3, #0
|
|
8001a80: 77fb strb r3, [r7, #31]
|
|
8001a82: e01a b.n 8001aba <LIS3MDL_MagReadXYZ+0xe6>
|
|
{
|
|
pData[i]=( int16_t )(pnRawData[i] * sensitivity);
|
|
8001a84: 7ffb ldrb r3, [r7, #31]
|
|
8001a86: 005b lsls r3, r3, #1
|
|
8001a88: 3320 adds r3, #32
|
|
8001a8a: 443b add r3, r7
|
|
8001a8c: f933 3c10 ldrsh.w r3, [r3, #-16]
|
|
8001a90: ee07 3a90 vmov s15, r3
|
|
8001a94: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8001a98: edd7 7a06 vldr s15, [r7, #24]
|
|
8001a9c: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001aa0: 7ffb ldrb r3, [r7, #31]
|
|
8001aa2: 005b lsls r3, r3, #1
|
|
8001aa4: 687a ldr r2, [r7, #4]
|
|
8001aa6: 4413 add r3, r2
|
|
8001aa8: eefd 7ae7 vcvt.s32.f32 s15, s15
|
|
8001aac: ee17 2a90 vmov r2, s15
|
|
8001ab0: b212 sxth r2, r2
|
|
8001ab2: 801a strh r2, [r3, #0]
|
|
for(i=0; i<3; i++)
|
|
8001ab4: 7ffb ldrb r3, [r7, #31]
|
|
8001ab6: 3301 adds r3, #1
|
|
8001ab8: 77fb strb r3, [r7, #31]
|
|
8001aba: 7ffb ldrb r3, [r7, #31]
|
|
8001abc: 2b02 cmp r3, #2
|
|
8001abe: d9e1 bls.n 8001a84 <LIS3MDL_MagReadXYZ+0xb0>
|
|
}
|
|
}
|
|
8001ac0: bf00 nop
|
|
8001ac2: bf00 nop
|
|
8001ac4: 3720 adds r7, #32
|
|
8001ac6: 46bd mov sp, r7
|
|
8001ac8: bd80 pop {r7, pc}
|
|
8001aca: bf00 nop
|
|
8001acc: 3e0f5c29 .word 0x3e0f5c29
|
|
8001ad0: 3e947ae1 .word 0x3e947ae1
|
|
8001ad4: 3edc28f6 .word 0x3edc28f6
|
|
8001ad8: 3f147ae1 .word 0x3f147ae1
|
|
|
|
08001adc <LPS22HB_P_Init>:
|
|
*/
|
|
/**
|
|
* @brief Set LPS22HB pressure sensor Initialization.
|
|
*/
|
|
void LPS22HB_P_Init(uint16_t DeviceAddr)
|
|
{
|
|
8001adc: b580 push {r7, lr}
|
|
8001ade: b082 sub sp, #8
|
|
8001ae0: af00 add r7, sp, #0
|
|
8001ae2: 4603 mov r3, r0
|
|
8001ae4: 80fb strh r3, [r7, #6]
|
|
LPS22HB_Init(DeviceAddr);
|
|
8001ae6: 88fb ldrh r3, [r7, #6]
|
|
8001ae8: 4618 mov r0, r3
|
|
8001aea: f000 f879 bl 8001be0 <LPS22HB_Init>
|
|
}
|
|
8001aee: bf00 nop
|
|
8001af0: 3708 adds r7, #8
|
|
8001af2: 46bd mov sp, r7
|
|
8001af4: bd80 pop {r7, pc}
|
|
|
|
08001af6 <LPS22HB_P_ReadID>:
|
|
/**
|
|
* @brief Read LPS22HB ID.
|
|
* @retval ID
|
|
*/
|
|
uint8_t LPS22HB_P_ReadID(uint16_t DeviceAddr)
|
|
{
|
|
8001af6: b580 push {r7, lr}
|
|
8001af8: b084 sub sp, #16
|
|
8001afa: af00 add r7, sp, #0
|
|
8001afc: 4603 mov r3, r0
|
|
8001afe: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001b00: 2300 movs r3, #0
|
|
8001b02: 73fb strb r3, [r7, #15]
|
|
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
8001b04: f7ff fb7c bl 8001200 <SENSOR_IO_Init>
|
|
|
|
/* Read value at Who am I register address */
|
|
ctrl = SENSOR_IO_Read(DeviceAddr, LPS22HB_WHO_AM_I_REG);
|
|
8001b08: 88fb ldrh r3, [r7, #6]
|
|
8001b0a: b2db uxtb r3, r3
|
|
8001b0c: 210f movs r1, #15
|
|
8001b0e: 4618 mov r0, r3
|
|
8001b10: f7ff fb9a bl 8001248 <SENSOR_IO_Read>
|
|
8001b14: 4603 mov r3, r0
|
|
8001b16: 73fb strb r3, [r7, #15]
|
|
|
|
return ctrl;
|
|
8001b18: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001b1a: 4618 mov r0, r3
|
|
8001b1c: 3710 adds r7, #16
|
|
8001b1e: 46bd mov sp, r7
|
|
8001b20: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001b24 <LPS22HB_P_ReadPressure>:
|
|
/**
|
|
* @brief Read pressure value of LPS22HB
|
|
* @retval pressure value
|
|
*/
|
|
float LPS22HB_P_ReadPressure(uint16_t DeviceAddr)
|
|
{
|
|
8001b24: b590 push {r4, r7, lr}
|
|
8001b26: b087 sub sp, #28
|
|
8001b28: af00 add r7, sp, #0
|
|
8001b2a: 4603 mov r3, r0
|
|
8001b2c: 80fb strh r3, [r7, #6]
|
|
int32_t raw_press;
|
|
uint8_t buffer[3];
|
|
uint32_t tmp = 0;
|
|
8001b2e: 2300 movs r3, #0
|
|
8001b30: 617b str r3, [r7, #20]
|
|
uint8_t i;
|
|
|
|
for(i = 0; i < 3; i++)
|
|
8001b32: 2300 movs r3, #0
|
|
8001b34: 74fb strb r3, [r7, #19]
|
|
8001b36: e013 b.n 8001b60 <LPS22HB_P_ReadPressure+0x3c>
|
|
{
|
|
buffer[i] = SENSOR_IO_Read(DeviceAddr, (LPS22HB_PRESS_OUT_XL_REG + i));
|
|
8001b38: 88fb ldrh r3, [r7, #6]
|
|
8001b3a: b2da uxtb r2, r3
|
|
8001b3c: 7cfb ldrb r3, [r7, #19]
|
|
8001b3e: 3328 adds r3, #40 @ 0x28
|
|
8001b40: b2db uxtb r3, r3
|
|
8001b42: 7cfc ldrb r4, [r7, #19]
|
|
8001b44: 4619 mov r1, r3
|
|
8001b46: 4610 mov r0, r2
|
|
8001b48: f7ff fb7e bl 8001248 <SENSOR_IO_Read>
|
|
8001b4c: 4603 mov r3, r0
|
|
8001b4e: 461a mov r2, r3
|
|
8001b50: f104 0318 add.w r3, r4, #24
|
|
8001b54: 443b add r3, r7
|
|
8001b56: f803 2c10 strb.w r2, [r3, #-16]
|
|
for(i = 0; i < 3; i++)
|
|
8001b5a: 7cfb ldrb r3, [r7, #19]
|
|
8001b5c: 3301 adds r3, #1
|
|
8001b5e: 74fb strb r3, [r7, #19]
|
|
8001b60: 7cfb ldrb r3, [r7, #19]
|
|
8001b62: 2b02 cmp r3, #2
|
|
8001b64: d9e8 bls.n 8001b38 <LPS22HB_P_ReadPressure+0x14>
|
|
}
|
|
|
|
/* Build the raw data */
|
|
for(i = 0; i < 3; i++)
|
|
8001b66: 2300 movs r3, #0
|
|
8001b68: 74fb strb r3, [r7, #19]
|
|
8001b6a: e00f b.n 8001b8c <LPS22HB_P_ReadPressure+0x68>
|
|
tmp |= (((uint32_t)buffer[i]) << (8 * i));
|
|
8001b6c: 7cfb ldrb r3, [r7, #19]
|
|
8001b6e: 3318 adds r3, #24
|
|
8001b70: 443b add r3, r7
|
|
8001b72: f813 3c10 ldrb.w r3, [r3, #-16]
|
|
8001b76: 461a mov r2, r3
|
|
8001b78: 7cfb ldrb r3, [r7, #19]
|
|
8001b7a: 00db lsls r3, r3, #3
|
|
8001b7c: fa02 f303 lsl.w r3, r2, r3
|
|
8001b80: 697a ldr r2, [r7, #20]
|
|
8001b82: 4313 orrs r3, r2
|
|
8001b84: 617b str r3, [r7, #20]
|
|
for(i = 0; i < 3; i++)
|
|
8001b86: 7cfb ldrb r3, [r7, #19]
|
|
8001b88: 3301 adds r3, #1
|
|
8001b8a: 74fb strb r3, [r7, #19]
|
|
8001b8c: 7cfb ldrb r3, [r7, #19]
|
|
8001b8e: 2b02 cmp r3, #2
|
|
8001b90: d9ec bls.n 8001b6c <LPS22HB_P_ReadPressure+0x48>
|
|
|
|
/* convert the 2's complement 24 bit to 2's complement 32 bit */
|
|
if(tmp & 0x00800000)
|
|
8001b92: 697b ldr r3, [r7, #20]
|
|
8001b94: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8001b98: 2b00 cmp r3, #0
|
|
8001b9a: d003 beq.n 8001ba4 <LPS22HB_P_ReadPressure+0x80>
|
|
tmp |= 0xFF000000;
|
|
8001b9c: 697b ldr r3, [r7, #20]
|
|
8001b9e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8001ba2: 617b str r3, [r7, #20]
|
|
|
|
raw_press = ((int32_t)tmp);
|
|
8001ba4: 697b ldr r3, [r7, #20]
|
|
8001ba6: 60fb str r3, [r7, #12]
|
|
|
|
raw_press = (raw_press * 100) / 4096;
|
|
8001ba8: 68fb ldr r3, [r7, #12]
|
|
8001baa: 2264 movs r2, #100 @ 0x64
|
|
8001bac: fb02 f303 mul.w r3, r2, r3
|
|
8001bb0: 2b00 cmp r3, #0
|
|
8001bb2: da01 bge.n 8001bb8 <LPS22HB_P_ReadPressure+0x94>
|
|
8001bb4: f603 73ff addw r3, r3, #4095 @ 0xfff
|
|
8001bb8: 131b asrs r3, r3, #12
|
|
8001bba: 60fb str r3, [r7, #12]
|
|
|
|
return (float)((float)raw_press / 100.0f);
|
|
8001bbc: 68fb ldr r3, [r7, #12]
|
|
8001bbe: ee07 3a90 vmov s15, r3
|
|
8001bc2: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001bc6: ed9f 7a05 vldr s14, [pc, #20] @ 8001bdc <LPS22HB_P_ReadPressure+0xb8>
|
|
8001bca: eec7 6a87 vdiv.f32 s13, s15, s14
|
|
8001bce: eef0 7a66 vmov.f32 s15, s13
|
|
}
|
|
8001bd2: eeb0 0a67 vmov.f32 s0, s15
|
|
8001bd6: 371c adds r7, #28
|
|
8001bd8: 46bd mov sp, r7
|
|
8001bda: bd90 pop {r4, r7, pc}
|
|
8001bdc: 42c80000 .word 0x42c80000
|
|
|
|
08001be0 <LPS22HB_Init>:
|
|
* @brief Set LPS22HB Initialization.
|
|
* @param DeviceAddr: I2C device address
|
|
* @retval None
|
|
*/
|
|
static void LPS22HB_Init(uint16_t DeviceAddr)
|
|
{
|
|
8001be0: b580 push {r7, lr}
|
|
8001be2: b084 sub sp, #16
|
|
8001be4: af00 add r7, sp, #0
|
|
8001be6: 4603 mov r3, r0
|
|
8001be8: 80fb strh r3, [r7, #6]
|
|
uint8_t tmp;
|
|
|
|
/* Set Power mode */
|
|
tmp = SENSOR_IO_Read(DeviceAddr, LPS22HB_RES_CONF_REG);
|
|
8001bea: 88fb ldrh r3, [r7, #6]
|
|
8001bec: b2db uxtb r3, r3
|
|
8001bee: 211a movs r1, #26
|
|
8001bf0: 4618 mov r0, r3
|
|
8001bf2: f7ff fb29 bl 8001248 <SENSOR_IO_Read>
|
|
8001bf6: 4603 mov r3, r0
|
|
8001bf8: 73fb strb r3, [r7, #15]
|
|
|
|
tmp &= ~LPS22HB_LCEN_MASK;
|
|
8001bfa: 7bfb ldrb r3, [r7, #15]
|
|
8001bfc: f023 0301 bic.w r3, r3, #1
|
|
8001c00: 73fb strb r3, [r7, #15]
|
|
tmp |= (uint8_t)0x01; /* Set low current mode */
|
|
8001c02: 7bfb ldrb r3, [r7, #15]
|
|
8001c04: f043 0301 orr.w r3, r3, #1
|
|
8001c08: 73fb strb r3, [r7, #15]
|
|
|
|
SENSOR_IO_Write(DeviceAddr, LPS22HB_RES_CONF_REG, tmp);
|
|
8001c0a: 88fb ldrh r3, [r7, #6]
|
|
8001c0c: b2db uxtb r3, r3
|
|
8001c0e: 7bfa ldrb r2, [r7, #15]
|
|
8001c10: 211a movs r1, #26
|
|
8001c12: 4618 mov r0, r3
|
|
8001c14: f7ff fafe bl 8001214 <SENSOR_IO_Write>
|
|
|
|
/* Read CTRL_REG1 */
|
|
tmp = SENSOR_IO_Read(DeviceAddr, LPS22HB_CTRL_REG1);
|
|
8001c18: 88fb ldrh r3, [r7, #6]
|
|
8001c1a: b2db uxtb r3, r3
|
|
8001c1c: 2110 movs r1, #16
|
|
8001c1e: 4618 mov r0, r3
|
|
8001c20: f7ff fb12 bl 8001248 <SENSOR_IO_Read>
|
|
8001c24: 4603 mov r3, r0
|
|
8001c26: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set default ODR */
|
|
tmp &= ~LPS22HB_ODR_MASK;
|
|
8001c28: 7bfb ldrb r3, [r7, #15]
|
|
8001c2a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8001c2e: 73fb strb r3, [r7, #15]
|
|
tmp |= (uint8_t)0x30; /* Set ODR to 25Hz */
|
|
8001c30: 7bfb ldrb r3, [r7, #15]
|
|
8001c32: f043 0330 orr.w r3, r3, #48 @ 0x30
|
|
8001c36: 73fb strb r3, [r7, #15]
|
|
|
|
/* Enable BDU */
|
|
tmp &= ~LPS22HB_BDU_MASK;
|
|
8001c38: 7bfb ldrb r3, [r7, #15]
|
|
8001c3a: f023 0302 bic.w r3, r3, #2
|
|
8001c3e: 73fb strb r3, [r7, #15]
|
|
tmp |= ((uint8_t)0x02);
|
|
8001c40: 7bfb ldrb r3, [r7, #15]
|
|
8001c42: f043 0302 orr.w r3, r3, #2
|
|
8001c46: 73fb strb r3, [r7, #15]
|
|
|
|
/* Apply settings to CTRL_REG1 */
|
|
SENSOR_IO_Write(DeviceAddr, LPS22HB_CTRL_REG1, tmp);
|
|
8001c48: 88fb ldrh r3, [r7, #6]
|
|
8001c4a: b2db uxtb r3, r3
|
|
8001c4c: 7bfa ldrb r2, [r7, #15]
|
|
8001c4e: 2110 movs r1, #16
|
|
8001c50: 4618 mov r0, r3
|
|
8001c52: f7ff fadf bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001c56: bf00 nop
|
|
8001c58: 3710 adds r7, #16
|
|
8001c5a: 46bd mov sp, r7
|
|
8001c5c: bd80 pop {r7, pc}
|
|
|
|
08001c5e <LSM6DSL_AccInit>:
|
|
/**
|
|
* @brief Set LSM6DSL Accelerometer Initialization.
|
|
* @param InitStruct: Init parameters
|
|
*/
|
|
void LSM6DSL_AccInit(uint16_t InitStruct)
|
|
{
|
|
8001c5e: b580 push {r7, lr}
|
|
8001c60: b084 sub sp, #16
|
|
8001c62: af00 add r7, sp, #0
|
|
8001c64: 4603 mov r3, r0
|
|
8001c66: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001c68: 2300 movs r3, #0
|
|
8001c6a: 73fb strb r3, [r7, #15]
|
|
uint8_t tmp;
|
|
|
|
/* Read CTRL1_XL */
|
|
tmp = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL);
|
|
8001c6c: 2110 movs r1, #16
|
|
8001c6e: 20d4 movs r0, #212 @ 0xd4
|
|
8001c70: f7ff faea bl 8001248 <SENSOR_IO_Read>
|
|
8001c74: 4603 mov r3, r0
|
|
8001c76: 73bb strb r3, [r7, #14]
|
|
|
|
/* Write value to ACC MEMS CTRL1_XL register: FS and Data Rate */
|
|
ctrl = (uint8_t) InitStruct;
|
|
8001c78: 88fb ldrh r3, [r7, #6]
|
|
8001c7a: 73fb strb r3, [r7, #15]
|
|
tmp &= ~(0xFC);
|
|
8001c7c: 7bbb ldrb r3, [r7, #14]
|
|
8001c7e: f003 0303 and.w r3, r3, #3
|
|
8001c82: 73bb strb r3, [r7, #14]
|
|
tmp |= ctrl;
|
|
8001c84: 7bba ldrb r2, [r7, #14]
|
|
8001c86: 7bfb ldrb r3, [r7, #15]
|
|
8001c88: 4313 orrs r3, r2
|
|
8001c8a: 73bb strb r3, [r7, #14]
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL, tmp);
|
|
8001c8c: 7bbb ldrb r3, [r7, #14]
|
|
8001c8e: 461a mov r2, r3
|
|
8001c90: 2110 movs r1, #16
|
|
8001c92: 20d4 movs r0, #212 @ 0xd4
|
|
8001c94: f7ff fabe bl 8001214 <SENSOR_IO_Write>
|
|
|
|
/* Read CTRL3_C */
|
|
tmp = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL3_C);
|
|
8001c98: 2112 movs r1, #18
|
|
8001c9a: 20d4 movs r0, #212 @ 0xd4
|
|
8001c9c: f7ff fad4 bl 8001248 <SENSOR_IO_Read>
|
|
8001ca0: 4603 mov r3, r0
|
|
8001ca2: 73bb strb r3, [r7, #14]
|
|
|
|
/* Write value to ACC MEMS CTRL3_C register: BDU and Auto-increment */
|
|
ctrl = ((uint8_t) (InitStruct >> 8));
|
|
8001ca4: 88fb ldrh r3, [r7, #6]
|
|
8001ca6: 0a1b lsrs r3, r3, #8
|
|
8001ca8: b29b uxth r3, r3
|
|
8001caa: 73fb strb r3, [r7, #15]
|
|
tmp &= ~(0x44);
|
|
8001cac: 7bbb ldrb r3, [r7, #14]
|
|
8001cae: f023 0344 bic.w r3, r3, #68 @ 0x44
|
|
8001cb2: 73bb strb r3, [r7, #14]
|
|
tmp |= ctrl;
|
|
8001cb4: 7bba ldrb r2, [r7, #14]
|
|
8001cb6: 7bfb ldrb r3, [r7, #15]
|
|
8001cb8: 4313 orrs r3, r2
|
|
8001cba: 73bb strb r3, [r7, #14]
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL3_C, tmp);
|
|
8001cbc: 7bbb ldrb r3, [r7, #14]
|
|
8001cbe: 461a mov r2, r3
|
|
8001cc0: 2112 movs r1, #18
|
|
8001cc2: 20d4 movs r0, #212 @ 0xd4
|
|
8001cc4: f7ff faa6 bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001cc8: bf00 nop
|
|
8001cca: 3710 adds r7, #16
|
|
8001ccc: 46bd mov sp, r7
|
|
8001cce: bd80 pop {r7, pc}
|
|
|
|
08001cd0 <LSM6DSL_AccDeInit>:
|
|
|
|
/**
|
|
* @brief LSM6DSL Accelerometer De-initialization.
|
|
*/
|
|
void LSM6DSL_AccDeInit(void)
|
|
{
|
|
8001cd0: b580 push {r7, lr}
|
|
8001cd2: b082 sub sp, #8
|
|
8001cd4: af00 add r7, sp, #0
|
|
uint8_t ctrl = 0x00;
|
|
8001cd6: 2300 movs r3, #0
|
|
8001cd8: 71fb strb r3, [r7, #7]
|
|
|
|
/* Read control register 1 value */
|
|
ctrl = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL);
|
|
8001cda: 2110 movs r1, #16
|
|
8001cdc: 20d4 movs r0, #212 @ 0xd4
|
|
8001cde: f7ff fab3 bl 8001248 <SENSOR_IO_Read>
|
|
8001ce2: 4603 mov r3, r0
|
|
8001ce4: 71fb strb r3, [r7, #7]
|
|
|
|
/* Clear ODR bits */
|
|
ctrl &= ~(LSM6DSL_ODR_BITPOSITION);
|
|
8001ce6: 79fb ldrb r3, [r7, #7]
|
|
8001ce8: f003 030f and.w r3, r3, #15
|
|
8001cec: 71fb strb r3, [r7, #7]
|
|
|
|
/* Set Power down */
|
|
ctrl |= LSM6DSL_ODR_POWER_DOWN;
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL, ctrl);
|
|
8001cee: 79fb ldrb r3, [r7, #7]
|
|
8001cf0: 461a mov r2, r3
|
|
8001cf2: 2110 movs r1, #16
|
|
8001cf4: 20d4 movs r0, #212 @ 0xd4
|
|
8001cf6: f7ff fa8d bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001cfa: bf00 nop
|
|
8001cfc: 3708 adds r7, #8
|
|
8001cfe: 46bd mov sp, r7
|
|
8001d00: bd80 pop {r7, pc}
|
|
|
|
08001d02 <LSM6DSL_AccReadID>:
|
|
/**
|
|
* @brief Read LSM6DSL ID.
|
|
* @retval ID
|
|
*/
|
|
uint8_t LSM6DSL_AccReadID(void)
|
|
{
|
|
8001d02: b580 push {r7, lr}
|
|
8001d04: af00 add r7, sp, #0
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
8001d06: f7ff fa7b bl 8001200 <SENSOR_IO_Init>
|
|
/* Read value at Who am I register address */
|
|
return (SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_WHO_AM_I_REG));
|
|
8001d0a: 210f movs r1, #15
|
|
8001d0c: 20d4 movs r0, #212 @ 0xd4
|
|
8001d0e: f7ff fa9b bl 8001248 <SENSOR_IO_Read>
|
|
8001d12: 4603 mov r3, r0
|
|
}
|
|
8001d14: 4618 mov r0, r3
|
|
8001d16: bd80 pop {r7, pc}
|
|
|
|
08001d18 <LSM6DSL_AccLowPower>:
|
|
/**
|
|
* @brief Set/Unset Accelerometer in low power mode.
|
|
* @param status 0 means disable Low Power Mode, otherwise Low Power Mode is enabled
|
|
*/
|
|
void LSM6DSL_AccLowPower(uint16_t status)
|
|
{
|
|
8001d18: b580 push {r7, lr}
|
|
8001d1a: b084 sub sp, #16
|
|
8001d1c: af00 add r7, sp, #0
|
|
8001d1e: 4603 mov r3, r0
|
|
8001d20: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001d22: 2300 movs r3, #0
|
|
8001d24: 73fb strb r3, [r7, #15]
|
|
|
|
/* Read CTRL6_C value */
|
|
ctrl = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL6_C);
|
|
8001d26: 2115 movs r1, #21
|
|
8001d28: 20d4 movs r0, #212 @ 0xd4
|
|
8001d2a: f7ff fa8d bl 8001248 <SENSOR_IO_Read>
|
|
8001d2e: 4603 mov r3, r0
|
|
8001d30: 73fb strb r3, [r7, #15]
|
|
|
|
/* Clear Low Power Mode bit */
|
|
ctrl &= ~(0x10);
|
|
8001d32: 7bfb ldrb r3, [r7, #15]
|
|
8001d34: f023 0310 bic.w r3, r3, #16
|
|
8001d38: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set Low Power Mode */
|
|
if(status)
|
|
8001d3a: 88fb ldrh r3, [r7, #6]
|
|
8001d3c: 2b00 cmp r3, #0
|
|
8001d3e: d003 beq.n 8001d48 <LSM6DSL_AccLowPower+0x30>
|
|
{
|
|
ctrl |= LSM6DSL_ACC_GYRO_LP_XL_ENABLED;
|
|
8001d40: 7bfb ldrb r3, [r7, #15]
|
|
8001d42: f043 0310 orr.w r3, r3, #16
|
|
8001d46: 73fb strb r3, [r7, #15]
|
|
{
|
|
ctrl |= LSM6DSL_ACC_GYRO_LP_XL_DISABLED;
|
|
}
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL6_C, ctrl);
|
|
8001d48: 7bfb ldrb r3, [r7, #15]
|
|
8001d4a: 461a mov r2, r3
|
|
8001d4c: 2115 movs r1, #21
|
|
8001d4e: 20d4 movs r0, #212 @ 0xd4
|
|
8001d50: f7ff fa60 bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001d54: bf00 nop
|
|
8001d56: 3710 adds r7, #16
|
|
8001d58: 46bd mov sp, r7
|
|
8001d5a: bd80 pop {r7, pc}
|
|
|
|
08001d5c <LSM6DSL_AccReadXYZ>:
|
|
/**
|
|
* @brief Read X, Y & Z Acceleration values
|
|
* @param pData: Data out pointer
|
|
*/
|
|
void LSM6DSL_AccReadXYZ(int16_t* pData)
|
|
{
|
|
8001d5c: b580 push {r7, lr}
|
|
8001d5e: b088 sub sp, #32
|
|
8001d60: af00 add r7, sp, #0
|
|
8001d62: 6078 str r0, [r7, #4]
|
|
int16_t pnRawData[3];
|
|
uint8_t ctrlx= 0;
|
|
8001d64: 2300 movs r3, #0
|
|
8001d66: 75fb strb r3, [r7, #23]
|
|
uint8_t buffer[6];
|
|
uint8_t i = 0;
|
|
8001d68: 2300 movs r3, #0
|
|
8001d6a: 77fb strb r3, [r7, #31]
|
|
float sensitivity = 0;
|
|
8001d6c: f04f 0300 mov.w r3, #0
|
|
8001d70: 61bb str r3, [r7, #24]
|
|
|
|
/* Read the acceleration control register content */
|
|
ctrlx = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL);
|
|
8001d72: 2110 movs r1, #16
|
|
8001d74: 20d4 movs r0, #212 @ 0xd4
|
|
8001d76: f7ff fa67 bl 8001248 <SENSOR_IO_Read>
|
|
8001d7a: 4603 mov r3, r0
|
|
8001d7c: 75fb strb r3, [r7, #23]
|
|
|
|
/* Read output register X, Y & Z acceleration */
|
|
SENSOR_IO_ReadMultiple(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_OUTX_L_XL, buffer, 6);
|
|
8001d7e: f107 0208 add.w r2, r7, #8
|
|
8001d82: 2306 movs r3, #6
|
|
8001d84: 2128 movs r1, #40 @ 0x28
|
|
8001d86: 20d4 movs r0, #212 @ 0xd4
|
|
8001d88: f7ff fa7c bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
for(i=0; i<3; i++)
|
|
8001d8c: 2300 movs r3, #0
|
|
8001d8e: 77fb strb r3, [r7, #31]
|
|
8001d90: e01a b.n 8001dc8 <LSM6DSL_AccReadXYZ+0x6c>
|
|
{
|
|
pnRawData[i]=((((uint16_t)buffer[2*i+1]) << 8) + (uint16_t)buffer[2*i]);
|
|
8001d92: 7ffb ldrb r3, [r7, #31]
|
|
8001d94: 005b lsls r3, r3, #1
|
|
8001d96: 3301 adds r3, #1
|
|
8001d98: 3320 adds r3, #32
|
|
8001d9a: 443b add r3, r7
|
|
8001d9c: f813 3c18 ldrb.w r3, [r3, #-24]
|
|
8001da0: 021b lsls r3, r3, #8
|
|
8001da2: b29b uxth r3, r3
|
|
8001da4: 7ffa ldrb r2, [r7, #31]
|
|
8001da6: 0052 lsls r2, r2, #1
|
|
8001da8: 3220 adds r2, #32
|
|
8001daa: 443a add r2, r7
|
|
8001dac: f812 2c18 ldrb.w r2, [r2, #-24]
|
|
8001db0: 4413 add r3, r2
|
|
8001db2: b29a uxth r2, r3
|
|
8001db4: 7ffb ldrb r3, [r7, #31]
|
|
8001db6: b212 sxth r2, r2
|
|
8001db8: 005b lsls r3, r3, #1
|
|
8001dba: 3320 adds r3, #32
|
|
8001dbc: 443b add r3, r7
|
|
8001dbe: f823 2c10 strh.w r2, [r3, #-16]
|
|
for(i=0; i<3; i++)
|
|
8001dc2: 7ffb ldrb r3, [r7, #31]
|
|
8001dc4: 3301 adds r3, #1
|
|
8001dc6: 77fb strb r3, [r7, #31]
|
|
8001dc8: 7ffb ldrb r3, [r7, #31]
|
|
8001dca: 2b02 cmp r3, #2
|
|
8001dcc: d9e1 bls.n 8001d92 <LSM6DSL_AccReadXYZ+0x36>
|
|
}
|
|
|
|
/* Normal mode */
|
|
/* Switch the sensitivity value set in the CRTL1_XL */
|
|
switch(ctrlx & 0x0C)
|
|
8001dce: 7dfb ldrb r3, [r7, #23]
|
|
8001dd0: f003 030c and.w r3, r3, #12
|
|
8001dd4: 2b0c cmp r3, #12
|
|
8001dd6: d829 bhi.n 8001e2c <LSM6DSL_AccReadXYZ+0xd0>
|
|
8001dd8: a201 add r2, pc, #4 @ (adr r2, 8001de0 <LSM6DSL_AccReadXYZ+0x84>)
|
|
8001dda: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8001dde: bf00 nop
|
|
8001de0: 08001e15 .word 0x08001e15
|
|
8001de4: 08001e2d .word 0x08001e2d
|
|
8001de8: 08001e2d .word 0x08001e2d
|
|
8001dec: 08001e2d .word 0x08001e2d
|
|
8001df0: 08001e27 .word 0x08001e27
|
|
8001df4: 08001e2d .word 0x08001e2d
|
|
8001df8: 08001e2d .word 0x08001e2d
|
|
8001dfc: 08001e2d .word 0x08001e2d
|
|
8001e00: 08001e1b .word 0x08001e1b
|
|
8001e04: 08001e2d .word 0x08001e2d
|
|
8001e08: 08001e2d .word 0x08001e2d
|
|
8001e0c: 08001e2d .word 0x08001e2d
|
|
8001e10: 08001e21 .word 0x08001e21
|
|
{
|
|
case LSM6DSL_ACC_FULLSCALE_2G:
|
|
sensitivity = LSM6DSL_ACC_SENSITIVITY_2G;
|
|
8001e14: 4b18 ldr r3, [pc, #96] @ (8001e78 <LSM6DSL_AccReadXYZ+0x11c>)
|
|
8001e16: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001e18: e008 b.n 8001e2c <LSM6DSL_AccReadXYZ+0xd0>
|
|
case LSM6DSL_ACC_FULLSCALE_4G:
|
|
sensitivity = LSM6DSL_ACC_SENSITIVITY_4G;
|
|
8001e1a: 4b18 ldr r3, [pc, #96] @ (8001e7c <LSM6DSL_AccReadXYZ+0x120>)
|
|
8001e1c: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001e1e: e005 b.n 8001e2c <LSM6DSL_AccReadXYZ+0xd0>
|
|
case LSM6DSL_ACC_FULLSCALE_8G:
|
|
sensitivity = LSM6DSL_ACC_SENSITIVITY_8G;
|
|
8001e20: 4b17 ldr r3, [pc, #92] @ (8001e80 <LSM6DSL_AccReadXYZ+0x124>)
|
|
8001e22: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001e24: e002 b.n 8001e2c <LSM6DSL_AccReadXYZ+0xd0>
|
|
case LSM6DSL_ACC_FULLSCALE_16G:
|
|
sensitivity = LSM6DSL_ACC_SENSITIVITY_16G;
|
|
8001e26: 4b17 ldr r3, [pc, #92] @ (8001e84 <LSM6DSL_AccReadXYZ+0x128>)
|
|
8001e28: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001e2a: bf00 nop
|
|
}
|
|
|
|
/* Obtain the mg value for the three axis */
|
|
for(i=0; i<3; i++)
|
|
8001e2c: 2300 movs r3, #0
|
|
8001e2e: 77fb strb r3, [r7, #31]
|
|
8001e30: e01a b.n 8001e68 <LSM6DSL_AccReadXYZ+0x10c>
|
|
{
|
|
pData[i]=( int16_t )(pnRawData[i] * sensitivity);
|
|
8001e32: 7ffb ldrb r3, [r7, #31]
|
|
8001e34: 005b lsls r3, r3, #1
|
|
8001e36: 3320 adds r3, #32
|
|
8001e38: 443b add r3, r7
|
|
8001e3a: f933 3c10 ldrsh.w r3, [r3, #-16]
|
|
8001e3e: ee07 3a90 vmov s15, r3
|
|
8001e42: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8001e46: edd7 7a06 vldr s15, [r7, #24]
|
|
8001e4a: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001e4e: 7ffb ldrb r3, [r7, #31]
|
|
8001e50: 005b lsls r3, r3, #1
|
|
8001e52: 687a ldr r2, [r7, #4]
|
|
8001e54: 4413 add r3, r2
|
|
8001e56: eefd 7ae7 vcvt.s32.f32 s15, s15
|
|
8001e5a: ee17 2a90 vmov r2, s15
|
|
8001e5e: b212 sxth r2, r2
|
|
8001e60: 801a strh r2, [r3, #0]
|
|
for(i=0; i<3; i++)
|
|
8001e62: 7ffb ldrb r3, [r7, #31]
|
|
8001e64: 3301 adds r3, #1
|
|
8001e66: 77fb strb r3, [r7, #31]
|
|
8001e68: 7ffb ldrb r3, [r7, #31]
|
|
8001e6a: 2b02 cmp r3, #2
|
|
8001e6c: d9e1 bls.n 8001e32 <LSM6DSL_AccReadXYZ+0xd6>
|
|
}
|
|
}
|
|
8001e6e: bf00 nop
|
|
8001e70: bf00 nop
|
|
8001e72: 3720 adds r7, #32
|
|
8001e74: 46bd mov sp, r7
|
|
8001e76: bd80 pop {r7, pc}
|
|
8001e78: 3d79db23 .word 0x3d79db23
|
|
8001e7c: 3df9db23 .word 0x3df9db23
|
|
8001e80: 3e79db23 .word 0x3e79db23
|
|
8001e84: 3ef9db23 .word 0x3ef9db23
|
|
|
|
08001e88 <LSM6DSL_GyroInit>:
|
|
* @brief Set LSM6DSL Gyroscope Initialization.
|
|
* @param InitStruct: pointer to a LSM6DSL_InitTypeDef structure
|
|
* that contains the configuration setting for the LSM6DSL.
|
|
*/
|
|
void LSM6DSL_GyroInit(uint16_t InitStruct)
|
|
{
|
|
8001e88: b580 push {r7, lr}
|
|
8001e8a: b084 sub sp, #16
|
|
8001e8c: af00 add r7, sp, #0
|
|
8001e8e: 4603 mov r3, r0
|
|
8001e90: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001e92: 2300 movs r3, #0
|
|
8001e94: 73fb strb r3, [r7, #15]
|
|
uint8_t tmp;
|
|
|
|
/* Read CTRL2_G */
|
|
tmp = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G);
|
|
8001e96: 2111 movs r1, #17
|
|
8001e98: 20d4 movs r0, #212 @ 0xd4
|
|
8001e9a: f7ff f9d5 bl 8001248 <SENSOR_IO_Read>
|
|
8001e9e: 4603 mov r3, r0
|
|
8001ea0: 73bb strb r3, [r7, #14]
|
|
|
|
/* Write value to GYRO MEMS CTRL2_G register: FS and Data Rate */
|
|
ctrl = (uint8_t) InitStruct;
|
|
8001ea2: 88fb ldrh r3, [r7, #6]
|
|
8001ea4: 73fb strb r3, [r7, #15]
|
|
tmp &= ~(0xFC);
|
|
8001ea6: 7bbb ldrb r3, [r7, #14]
|
|
8001ea8: f003 0303 and.w r3, r3, #3
|
|
8001eac: 73bb strb r3, [r7, #14]
|
|
tmp |= ctrl;
|
|
8001eae: 7bba ldrb r2, [r7, #14]
|
|
8001eb0: 7bfb ldrb r3, [r7, #15]
|
|
8001eb2: 4313 orrs r3, r2
|
|
8001eb4: 73bb strb r3, [r7, #14]
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G, tmp);
|
|
8001eb6: 7bbb ldrb r3, [r7, #14]
|
|
8001eb8: 461a mov r2, r3
|
|
8001eba: 2111 movs r1, #17
|
|
8001ebc: 20d4 movs r0, #212 @ 0xd4
|
|
8001ebe: f7ff f9a9 bl 8001214 <SENSOR_IO_Write>
|
|
|
|
/* Read CTRL3_C */
|
|
tmp = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL3_C);
|
|
8001ec2: 2112 movs r1, #18
|
|
8001ec4: 20d4 movs r0, #212 @ 0xd4
|
|
8001ec6: f7ff f9bf bl 8001248 <SENSOR_IO_Read>
|
|
8001eca: 4603 mov r3, r0
|
|
8001ecc: 73bb strb r3, [r7, #14]
|
|
|
|
/* Write value to GYRO MEMS CTRL3_C register: BDU and Auto-increment */
|
|
ctrl = ((uint8_t) (InitStruct >> 8));
|
|
8001ece: 88fb ldrh r3, [r7, #6]
|
|
8001ed0: 0a1b lsrs r3, r3, #8
|
|
8001ed2: b29b uxth r3, r3
|
|
8001ed4: 73fb strb r3, [r7, #15]
|
|
tmp &= ~(0x44);
|
|
8001ed6: 7bbb ldrb r3, [r7, #14]
|
|
8001ed8: f023 0344 bic.w r3, r3, #68 @ 0x44
|
|
8001edc: 73bb strb r3, [r7, #14]
|
|
tmp |= ctrl;
|
|
8001ede: 7bba ldrb r2, [r7, #14]
|
|
8001ee0: 7bfb ldrb r3, [r7, #15]
|
|
8001ee2: 4313 orrs r3, r2
|
|
8001ee4: 73bb strb r3, [r7, #14]
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL3_C, tmp);
|
|
8001ee6: 7bbb ldrb r3, [r7, #14]
|
|
8001ee8: 461a mov r2, r3
|
|
8001eea: 2112 movs r1, #18
|
|
8001eec: 20d4 movs r0, #212 @ 0xd4
|
|
8001eee: f7ff f991 bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001ef2: bf00 nop
|
|
8001ef4: 3710 adds r7, #16
|
|
8001ef6: 46bd mov sp, r7
|
|
8001ef8: bd80 pop {r7, pc}
|
|
|
|
08001efa <LSM6DSL_GyroDeInit>:
|
|
|
|
/**
|
|
* @brief LSM6DSL Gyroscope De-initialization
|
|
*/
|
|
void LSM6DSL_GyroDeInit(void)
|
|
{
|
|
8001efa: b580 push {r7, lr}
|
|
8001efc: b082 sub sp, #8
|
|
8001efe: af00 add r7, sp, #0
|
|
uint8_t ctrl = 0x00;
|
|
8001f00: 2300 movs r3, #0
|
|
8001f02: 71fb strb r3, [r7, #7]
|
|
|
|
/* Read control register 1 value */
|
|
ctrl = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G);
|
|
8001f04: 2111 movs r1, #17
|
|
8001f06: 20d4 movs r0, #212 @ 0xd4
|
|
8001f08: f7ff f99e bl 8001248 <SENSOR_IO_Read>
|
|
8001f0c: 4603 mov r3, r0
|
|
8001f0e: 71fb strb r3, [r7, #7]
|
|
|
|
/* Clear ODR bits */
|
|
ctrl &= ~(LSM6DSL_ODR_BITPOSITION);
|
|
8001f10: 79fb ldrb r3, [r7, #7]
|
|
8001f12: f003 030f and.w r3, r3, #15
|
|
8001f16: 71fb strb r3, [r7, #7]
|
|
|
|
/* Set Power down */
|
|
ctrl |= LSM6DSL_ODR_POWER_DOWN;
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G, ctrl);
|
|
8001f18: 79fb ldrb r3, [r7, #7]
|
|
8001f1a: 461a mov r2, r3
|
|
8001f1c: 2111 movs r1, #17
|
|
8001f1e: 20d4 movs r0, #212 @ 0xd4
|
|
8001f20: f7ff f978 bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001f24: bf00 nop
|
|
8001f26: 3708 adds r7, #8
|
|
8001f28: 46bd mov sp, r7
|
|
8001f2a: bd80 pop {r7, pc}
|
|
|
|
08001f2c <LSM6DSL_GyroReadID>:
|
|
/**
|
|
* @brief Read ID address of LSM6DSL
|
|
* @retval ID
|
|
*/
|
|
uint8_t LSM6DSL_GyroReadID(void)
|
|
{
|
|
8001f2c: b580 push {r7, lr}
|
|
8001f2e: af00 add r7, sp, #0
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
8001f30: f7ff f966 bl 8001200 <SENSOR_IO_Init>
|
|
/* Read value at Who am I register address */
|
|
return SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_WHO_AM_I_REG);
|
|
8001f34: 210f movs r1, #15
|
|
8001f36: 20d4 movs r0, #212 @ 0xd4
|
|
8001f38: f7ff f986 bl 8001248 <SENSOR_IO_Read>
|
|
8001f3c: 4603 mov r3, r0
|
|
}
|
|
8001f3e: 4618 mov r0, r3
|
|
8001f40: bd80 pop {r7, pc}
|
|
|
|
08001f42 <LSM6DSL_GyroLowPower>:
|
|
/**
|
|
* @brief Set/Unset LSM6DSL Gyroscope in low power mode
|
|
* @param status 0 means disable Low Power Mode, otherwise Low Power Mode is enabled
|
|
*/
|
|
void LSM6DSL_GyroLowPower(uint16_t status)
|
|
{
|
|
8001f42: b580 push {r7, lr}
|
|
8001f44: b084 sub sp, #16
|
|
8001f46: af00 add r7, sp, #0
|
|
8001f48: 4603 mov r3, r0
|
|
8001f4a: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001f4c: 2300 movs r3, #0
|
|
8001f4e: 73fb strb r3, [r7, #15]
|
|
|
|
/* Read CTRL7_G value */
|
|
ctrl = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL7_G);
|
|
8001f50: 2116 movs r1, #22
|
|
8001f52: 20d4 movs r0, #212 @ 0xd4
|
|
8001f54: f7ff f978 bl 8001248 <SENSOR_IO_Read>
|
|
8001f58: 4603 mov r3, r0
|
|
8001f5a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Clear Low Power Mode bit */
|
|
ctrl &= ~(0x80);
|
|
8001f5c: 7bfb ldrb r3, [r7, #15]
|
|
8001f5e: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8001f62: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set Low Power Mode */
|
|
if(status)
|
|
8001f64: 88fb ldrh r3, [r7, #6]
|
|
8001f66: 2b00 cmp r3, #0
|
|
8001f68: d003 beq.n 8001f72 <LSM6DSL_GyroLowPower+0x30>
|
|
{
|
|
ctrl |= LSM6DSL_ACC_GYRO_LP_G_ENABLED;
|
|
8001f6a: 7bfb ldrb r3, [r7, #15]
|
|
8001f6c: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8001f70: 73fb strb r3, [r7, #15]
|
|
{
|
|
ctrl |= LSM6DSL_ACC_GYRO_LP_G_DISABLED;
|
|
}
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL7_G, ctrl);
|
|
8001f72: 7bfb ldrb r3, [r7, #15]
|
|
8001f74: 461a mov r2, r3
|
|
8001f76: 2116 movs r1, #22
|
|
8001f78: 20d4 movs r0, #212 @ 0xd4
|
|
8001f7a: f7ff f94b bl 8001214 <SENSOR_IO_Write>
|
|
}
|
|
8001f7e: bf00 nop
|
|
8001f80: 3710 adds r7, #16
|
|
8001f82: 46bd mov sp, r7
|
|
8001f84: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001f88 <LSM6DSL_GyroReadXYZAngRate>:
|
|
/**
|
|
* @brief Calculate the LSM6DSL angular data.
|
|
* @param pfData: Data out pointer
|
|
*/
|
|
void LSM6DSL_GyroReadXYZAngRate(float *pfData)
|
|
{
|
|
8001f88: b580 push {r7, lr}
|
|
8001f8a: b088 sub sp, #32
|
|
8001f8c: af00 add r7, sp, #0
|
|
8001f8e: 6078 str r0, [r7, #4]
|
|
int16_t pnRawData[3];
|
|
uint8_t ctrlg= 0;
|
|
8001f90: 2300 movs r3, #0
|
|
8001f92: 75fb strb r3, [r7, #23]
|
|
uint8_t buffer[6];
|
|
uint8_t i = 0;
|
|
8001f94: 2300 movs r3, #0
|
|
8001f96: 77fb strb r3, [r7, #31]
|
|
float sensitivity = 0;
|
|
8001f98: f04f 0300 mov.w r3, #0
|
|
8001f9c: 61bb str r3, [r7, #24]
|
|
|
|
/* Read the gyro control register content */
|
|
ctrlg = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G);
|
|
8001f9e: 2111 movs r1, #17
|
|
8001fa0: 20d4 movs r0, #212 @ 0xd4
|
|
8001fa2: f7ff f951 bl 8001248 <SENSOR_IO_Read>
|
|
8001fa6: 4603 mov r3, r0
|
|
8001fa8: 75fb strb r3, [r7, #23]
|
|
|
|
/* Read output register X, Y & Z acceleration */
|
|
SENSOR_IO_ReadMultiple(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_OUTX_L_G, buffer, 6);
|
|
8001faa: f107 0208 add.w r2, r7, #8
|
|
8001fae: 2306 movs r3, #6
|
|
8001fb0: 2122 movs r1, #34 @ 0x22
|
|
8001fb2: 20d4 movs r0, #212 @ 0xd4
|
|
8001fb4: f7ff f966 bl 8001284 <SENSOR_IO_ReadMultiple>
|
|
|
|
for(i=0; i<3; i++)
|
|
8001fb8: 2300 movs r3, #0
|
|
8001fba: 77fb strb r3, [r7, #31]
|
|
8001fbc: e01a b.n 8001ff4 <LSM6DSL_GyroReadXYZAngRate+0x6c>
|
|
{
|
|
pnRawData[i]=((((uint16_t)buffer[2*i+1]) << 8) + (uint16_t)buffer[2*i]);
|
|
8001fbe: 7ffb ldrb r3, [r7, #31]
|
|
8001fc0: 005b lsls r3, r3, #1
|
|
8001fc2: 3301 adds r3, #1
|
|
8001fc4: 3320 adds r3, #32
|
|
8001fc6: 443b add r3, r7
|
|
8001fc8: f813 3c18 ldrb.w r3, [r3, #-24]
|
|
8001fcc: 021b lsls r3, r3, #8
|
|
8001fce: b29b uxth r3, r3
|
|
8001fd0: 7ffa ldrb r2, [r7, #31]
|
|
8001fd2: 0052 lsls r2, r2, #1
|
|
8001fd4: 3220 adds r2, #32
|
|
8001fd6: 443a add r2, r7
|
|
8001fd8: f812 2c18 ldrb.w r2, [r2, #-24]
|
|
8001fdc: 4413 add r3, r2
|
|
8001fde: b29a uxth r2, r3
|
|
8001fe0: 7ffb ldrb r3, [r7, #31]
|
|
8001fe2: b212 sxth r2, r2
|
|
8001fe4: 005b lsls r3, r3, #1
|
|
8001fe6: 3320 adds r3, #32
|
|
8001fe8: 443b add r3, r7
|
|
8001fea: f823 2c10 strh.w r2, [r3, #-16]
|
|
for(i=0; i<3; i++)
|
|
8001fee: 7ffb ldrb r3, [r7, #31]
|
|
8001ff0: 3301 adds r3, #1
|
|
8001ff2: 77fb strb r3, [r7, #31]
|
|
8001ff4: 7ffb ldrb r3, [r7, #31]
|
|
8001ff6: 2b02 cmp r3, #2
|
|
8001ff8: d9e1 bls.n 8001fbe <LSM6DSL_GyroReadXYZAngRate+0x36>
|
|
}
|
|
|
|
/* Normal mode */
|
|
/* Switch the sensitivity value set in the CRTL2_G */
|
|
switch(ctrlg & 0x0C)
|
|
8001ffa: 7dfb ldrb r3, [r7, #23]
|
|
8001ffc: f003 030c and.w r3, r3, #12
|
|
8002000: 2b0c cmp r3, #12
|
|
8002002: d829 bhi.n 8002058 <LSM6DSL_GyroReadXYZAngRate+0xd0>
|
|
8002004: a201 add r2, pc, #4 @ (adr r2, 800200c <LSM6DSL_GyroReadXYZAngRate+0x84>)
|
|
8002006: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800200a: bf00 nop
|
|
800200c: 08002041 .word 0x08002041
|
|
8002010: 08002059 .word 0x08002059
|
|
8002014: 08002059 .word 0x08002059
|
|
8002018: 08002059 .word 0x08002059
|
|
800201c: 08002047 .word 0x08002047
|
|
8002020: 08002059 .word 0x08002059
|
|
8002024: 08002059 .word 0x08002059
|
|
8002028: 08002059 .word 0x08002059
|
|
800202c: 0800204d .word 0x0800204d
|
|
8002030: 08002059 .word 0x08002059
|
|
8002034: 08002059 .word 0x08002059
|
|
8002038: 08002059 .word 0x08002059
|
|
800203c: 08002053 .word 0x08002053
|
|
{
|
|
case LSM6DSL_GYRO_FS_245:
|
|
sensitivity = LSM6DSL_GYRO_SENSITIVITY_245DPS;
|
|
8002040: 4b16 ldr r3, [pc, #88] @ (800209c <LSM6DSL_GyroReadXYZAngRate+0x114>)
|
|
8002042: 61bb str r3, [r7, #24]
|
|
break;
|
|
8002044: e008 b.n 8002058 <LSM6DSL_GyroReadXYZAngRate+0xd0>
|
|
case LSM6DSL_GYRO_FS_500:
|
|
sensitivity = LSM6DSL_GYRO_SENSITIVITY_500DPS;
|
|
8002046: 4b16 ldr r3, [pc, #88] @ (80020a0 <LSM6DSL_GyroReadXYZAngRate+0x118>)
|
|
8002048: 61bb str r3, [r7, #24]
|
|
break;
|
|
800204a: e005 b.n 8002058 <LSM6DSL_GyroReadXYZAngRate+0xd0>
|
|
case LSM6DSL_GYRO_FS_1000:
|
|
sensitivity = LSM6DSL_GYRO_SENSITIVITY_1000DPS;
|
|
800204c: 4b15 ldr r3, [pc, #84] @ (80020a4 <LSM6DSL_GyroReadXYZAngRate+0x11c>)
|
|
800204e: 61bb str r3, [r7, #24]
|
|
break;
|
|
8002050: e002 b.n 8002058 <LSM6DSL_GyroReadXYZAngRate+0xd0>
|
|
case LSM6DSL_GYRO_FS_2000:
|
|
sensitivity = LSM6DSL_GYRO_SENSITIVITY_2000DPS;
|
|
8002052: 4b15 ldr r3, [pc, #84] @ (80020a8 <LSM6DSL_GyroReadXYZAngRate+0x120>)
|
|
8002054: 61bb str r3, [r7, #24]
|
|
break;
|
|
8002056: bf00 nop
|
|
}
|
|
|
|
/* Obtain the mg value for the three axis */
|
|
for(i=0; i<3; i++)
|
|
8002058: 2300 movs r3, #0
|
|
800205a: 77fb strb r3, [r7, #31]
|
|
800205c: e016 b.n 800208c <LSM6DSL_GyroReadXYZAngRate+0x104>
|
|
{
|
|
pfData[i]=( float )(pnRawData[i] * sensitivity);
|
|
800205e: 7ffb ldrb r3, [r7, #31]
|
|
8002060: 005b lsls r3, r3, #1
|
|
8002062: 3320 adds r3, #32
|
|
8002064: 443b add r3, r7
|
|
8002066: f933 3c10 ldrsh.w r3, [r3, #-16]
|
|
800206a: ee07 3a90 vmov s15, r3
|
|
800206e: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8002072: 7ffb ldrb r3, [r7, #31]
|
|
8002074: 009b lsls r3, r3, #2
|
|
8002076: 687a ldr r2, [r7, #4]
|
|
8002078: 4413 add r3, r2
|
|
800207a: edd7 7a06 vldr s15, [r7, #24]
|
|
800207e: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8002082: edc3 7a00 vstr s15, [r3]
|
|
for(i=0; i<3; i++)
|
|
8002086: 7ffb ldrb r3, [r7, #31]
|
|
8002088: 3301 adds r3, #1
|
|
800208a: 77fb strb r3, [r7, #31]
|
|
800208c: 7ffb ldrb r3, [r7, #31]
|
|
800208e: 2b02 cmp r3, #2
|
|
8002090: d9e5 bls.n 800205e <LSM6DSL_GyroReadXYZAngRate+0xd6>
|
|
}
|
|
}
|
|
8002092: bf00 nop
|
|
8002094: bf00 nop
|
|
8002096: 3720 adds r7, #32
|
|
8002098: 46bd mov sp, r7
|
|
800209a: bd80 pop {r7, pc}
|
|
800209c: 410c0000 .word 0x410c0000
|
|
80020a0: 418c0000 .word 0x418c0000
|
|
80020a4: 420c0000 .word 0x420c0000
|
|
80020a8: 428c0000 .word 0x428c0000
|
|
|
|
080020ac <InitSensors>:
|
|
TickType_t sensor_period = 100;
|
|
SensorData_t sensor_data;
|
|
extern QueueHandle_t xQueueSensors;
|
|
|
|
void InitSensors()
|
|
{
|
|
80020ac: b580 push {r7, lr}
|
|
80020ae: af00 add r7, sp, #0
|
|
BSP_HSENSOR_Init();
|
|
80020b0: f7ff f9ba bl 8001428 <BSP_HSENSOR_Init>
|
|
BSP_PSENSOR_Init();
|
|
80020b4: f7ff fa2a bl 800150c <BSP_PSENSOR_Init>
|
|
BSP_TSENSOR_Init();
|
|
80020b8: f7ff fa56 bl 8001568 <BSP_TSENSOR_Init>
|
|
|
|
BSP_ACCELERO_Init();
|
|
80020bc: f7ff f900 bl 80012c0 <BSP_ACCELERO_Init>
|
|
BSP_GYRO_Init();
|
|
80020c0: f7ff f956 bl 8001370 <BSP_GYRO_Init>
|
|
BSP_MAGNETO_Init();
|
|
80020c4: f7ff f9de bl 8001484 <BSP_MAGNETO_Init>
|
|
}
|
|
80020c8: bf00 nop
|
|
80020ca: bd80 pop {r7, pc}
|
|
|
|
080020cc <ReadSensors>:
|
|
|
|
void ReadSensors()
|
|
{
|
|
80020cc: b580 push {r7, lr}
|
|
80020ce: af00 add r7, sp, #0
|
|
sensor_data.humidity = BSP_HSENSOR_ReadHumidity();
|
|
80020d0: f7ff f9ca bl 8001468 <BSP_HSENSOR_ReadHumidity>
|
|
80020d4: eef0 7a40 vmov.f32 s15, s0
|
|
80020d8: 4b0d ldr r3, [pc, #52] @ (8002110 <ReadSensors+0x44>)
|
|
80020da: edc3 7a00 vstr s15, [r3]
|
|
sensor_data.pressure = BSP_PSENSOR_ReadPressure();
|
|
80020de: f7ff fa35 bl 800154c <BSP_PSENSOR_ReadPressure>
|
|
80020e2: eef0 7a40 vmov.f32 s15, s0
|
|
80020e6: 4b0a ldr r3, [pc, #40] @ (8002110 <ReadSensors+0x44>)
|
|
80020e8: edc3 7a02 vstr s15, [r3, #8]
|
|
sensor_data.temperature = BSP_TSENSOR_ReadTemp();
|
|
80020ec: f7ff fa58 bl 80015a0 <BSP_TSENSOR_ReadTemp>
|
|
80020f0: eef0 7a40 vmov.f32 s15, s0
|
|
80020f4: 4b06 ldr r3, [pc, #24] @ (8002110 <ReadSensors+0x44>)
|
|
80020f6: edc3 7a01 vstr s15, [r3, #4]
|
|
|
|
BSP_ACCELERO_AccGetXYZ(sensor_data.accelerometer);
|
|
80020fa: 4806 ldr r0, [pc, #24] @ (8002114 <ReadSensors+0x48>)
|
|
80020fc: f7ff f920 bl 8001340 <BSP_ACCELERO_AccGetXYZ>
|
|
BSP_GYRO_GetXYZ(sensor_data.gyroscope);
|
|
8002100: 4805 ldr r0, [pc, #20] @ (8002118 <ReadSensors+0x4c>)
|
|
8002102: f7ff f979 bl 80013f8 <BSP_GYRO_GetXYZ>
|
|
BSP_MAGNETO_GetXYZ(sensor_data.magnetometer);
|
|
8002106: 4805 ldr r0, [pc, #20] @ (800211c <ReadSensors+0x50>)
|
|
8002108: f7ff f9e8 bl 80014dc <BSP_MAGNETO_GetXYZ>
|
|
}
|
|
800210c: bf00 nop
|
|
800210e: bd80 pop {r7, pc}
|
|
8002110: 20000324 .word 0x20000324
|
|
8002114: 20000330 .word 0x20000330
|
|
8002118: 20000338 .word 0x20000338
|
|
800211c: 20000344 .word 0x20000344
|
|
|
|
08002120 <CreateSerialObjects>:
|
|
QueueHandle_t xQueue;
|
|
QueueHandle_t xQueueLED;
|
|
QueueHandle_t xQueueSensors;
|
|
|
|
void CreateSerialObjects()
|
|
{
|
|
8002120: b580 push {r7, lr}
|
|
8002122: af00 add r7, sp, #0
|
|
xSemaphore = xSemaphoreCreateBinary();
|
|
8002124: 2203 movs r2, #3
|
|
8002126: 2100 movs r1, #0
|
|
8002128: 2001 movs r0, #1
|
|
800212a: f00a fab4 bl 800c696 <xQueueGenericCreate>
|
|
800212e: 4603 mov r3, r0
|
|
8002130: 4a11 ldr r2, [pc, #68] @ (8002178 <CreateSerialObjects+0x58>)
|
|
8002132: 6013 str r3, [r2, #0]
|
|
xSemaphoreGive (xSemaphore);
|
|
8002134: 4b10 ldr r3, [pc, #64] @ (8002178 <CreateSerialObjects+0x58>)
|
|
8002136: 6818 ldr r0, [r3, #0]
|
|
8002138: 2300 movs r3, #0
|
|
800213a: 2200 movs r2, #0
|
|
800213c: 2100 movs r1, #0
|
|
800213e: f00a fb09 bl 800c754 <xQueueGenericSend>
|
|
|
|
xQueue = xQueueCreate(5, sizeof (char*));
|
|
8002142: 2200 movs r2, #0
|
|
8002144: 2104 movs r1, #4
|
|
8002146: 2005 movs r0, #5
|
|
8002148: f00a faa5 bl 800c696 <xQueueGenericCreate>
|
|
800214c: 4603 mov r3, r0
|
|
800214e: 4a0b ldr r2, [pc, #44] @ (800217c <CreateSerialObjects+0x5c>)
|
|
8002150: 6013 str r3, [r2, #0]
|
|
xQueueLED = xQueueCreate(1, sizeof (char*));
|
|
8002152: 2200 movs r2, #0
|
|
8002154: 2104 movs r1, #4
|
|
8002156: 2001 movs r0, #1
|
|
8002158: f00a fa9d bl 800c696 <xQueueGenericCreate>
|
|
800215c: 4603 mov r3, r0
|
|
800215e: 4a08 ldr r2, [pc, #32] @ (8002180 <CreateSerialObjects+0x60>)
|
|
8002160: 6013 str r3, [r2, #0]
|
|
xQueueSensors = xQueueCreate(1, sizeof (SensorData_t));
|
|
8002162: 2200 movs r2, #0
|
|
8002164: 2128 movs r1, #40 @ 0x28
|
|
8002166: 2001 movs r0, #1
|
|
8002168: f00a fa95 bl 800c696 <xQueueGenericCreate>
|
|
800216c: 4603 mov r3, r0
|
|
800216e: 4a05 ldr r2, [pc, #20] @ (8002184 <CreateSerialObjects+0x64>)
|
|
8002170: 6013 str r3, [r2, #0]
|
|
}
|
|
8002172: bf00 nop
|
|
8002174: bd80 pop {r7, pc}
|
|
8002176: bf00 nop
|
|
8002178: 20000350 .word 0x20000350
|
|
800217c: 20000354 .word 0x20000354
|
|
8002180: 20000358 .word 0x20000358
|
|
8002184: 2000035c .word 0x2000035c
|
|
|
|
08002188 <QueueLed>:
|
|
|
|
void QueueLed(char ch)
|
|
{
|
|
8002188: b580 push {r7, lr}
|
|
800218a: b082 sub sp, #8
|
|
800218c: af00 add r7, sp, #0
|
|
800218e: 4603 mov r3, r0
|
|
8002190: 71fb strb r3, [r7, #7]
|
|
xQueueSend(xQueueLED,&ch, portMAX_DELAY);
|
|
8002192: 4b06 ldr r3, [pc, #24] @ (80021ac <QueueLed+0x24>)
|
|
8002194: 6818 ldr r0, [r3, #0]
|
|
8002196: 1df9 adds r1, r7, #7
|
|
8002198: 2300 movs r3, #0
|
|
800219a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800219e: f00a fad9 bl 800c754 <xQueueGenericSend>
|
|
}
|
|
80021a2: bf00 nop
|
|
80021a4: 3708 adds r7, #8
|
|
80021a6: 46bd mov sp, r7
|
|
80021a8: bd80 pop {r7, pc}
|
|
80021aa: bf00 nop
|
|
80021ac: 20000358 .word 0x20000358
|
|
|
|
080021b0 <GetSensors>:
|
|
|
|
SensorData_t GetSensors()
|
|
{
|
|
80021b0: b5b0 push {r4, r5, r7, lr}
|
|
80021b2: b08c sub sp, #48 @ 0x30
|
|
80021b4: af00 add r7, sp, #0
|
|
80021b6: 6078 str r0, [r7, #4]
|
|
SensorData_t aux;
|
|
xTaskNotifyGive(sensorTaskHandle);
|
|
80021b8: 4b0f ldr r3, [pc, #60] @ (80021f8 <GetSensors+0x48>)
|
|
80021ba: 6818 ldr r0, [r3, #0]
|
|
80021bc: 2300 movs r3, #0
|
|
80021be: 2202 movs r2, #2
|
|
80021c0: 2100 movs r1, #0
|
|
80021c2: f00c f839 bl 800e238 <xTaskGenericNotify>
|
|
xQueueReceive(xQueueSensors, &aux, portMAX_DELAY);
|
|
80021c6: 4b0d ldr r3, [pc, #52] @ (80021fc <GetSensors+0x4c>)
|
|
80021c8: 681b ldr r3, [r3, #0]
|
|
80021ca: f107 0108 add.w r1, r7, #8
|
|
80021ce: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80021d2: 4618 mov r0, r3
|
|
80021d4: f00a fcee bl 800cbb4 <xQueueReceive>
|
|
return aux;
|
|
80021d8: 687b ldr r3, [r7, #4]
|
|
80021da: 461d mov r5, r3
|
|
80021dc: f107 0408 add.w r4, r7, #8
|
|
80021e0: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
80021e2: c50f stmia r5!, {r0, r1, r2, r3}
|
|
80021e4: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
80021e6: c50f stmia r5!, {r0, r1, r2, r3}
|
|
80021e8: e894 0003 ldmia.w r4, {r0, r1}
|
|
80021ec: e885 0003 stmia.w r5, {r0, r1}
|
|
}
|
|
80021f0: 6878 ldr r0, [r7, #4]
|
|
80021f2: 3730 adds r7, #48 @ 0x30
|
|
80021f4: 46bd mov sp, r7
|
|
80021f6: bdb0 pop {r4, r5, r7, pc}
|
|
80021f8: 2000034c .word 0x2000034c
|
|
80021fc: 2000035c .word 0x2000035c
|
|
|
|
08002200 <CreateTasks>:
|
|
|
|
void CreateTasks()
|
|
{
|
|
8002200: b580 push {r7, lr}
|
|
8002202: b082 sub sp, #8
|
|
8002204: af02 add r7, sp, #8
|
|
xTaskCreate(
|
|
8002206: 4b11 ldr r3, [pc, #68] @ (800224c <CreateTasks+0x4c>)
|
|
8002208: 9301 str r3, [sp, #4]
|
|
800220a: 2301 movs r3, #1
|
|
800220c: 9300 str r3, [sp, #0]
|
|
800220e: 2300 movs r3, #0
|
|
8002210: 2280 movs r2, #128 @ 0x80
|
|
8002212: 490f ldr r1, [pc, #60] @ (8002250 <CreateTasks+0x50>)
|
|
8002214: 480f ldr r0, [pc, #60] @ (8002254 <CreateTasks+0x54>)
|
|
8002216: f00b f8a5 bl 800d364 <xTaskCreate>
|
|
NULL,
|
|
1,
|
|
&sensorTaskHandle
|
|
);
|
|
|
|
xTaskCreate(
|
|
800221a: 2300 movs r3, #0
|
|
800221c: 9301 str r3, [sp, #4]
|
|
800221e: 2301 movs r3, #1
|
|
8002220: 9300 str r3, [sp, #0]
|
|
8002222: 2300 movs r3, #0
|
|
8002224: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8002228: 490b ldr r1, [pc, #44] @ (8002258 <CreateTasks+0x58>)
|
|
800222a: 480c ldr r0, [pc, #48] @ (800225c <CreateTasks+0x5c>)
|
|
800222c: f00b f89a bl 800d364 <xTaskCreate>
|
|
NULL,
|
|
1,
|
|
NULL
|
|
);
|
|
|
|
xTaskCreate(
|
|
8002230: 2300 movs r3, #0
|
|
8002232: 9301 str r3, [sp, #4]
|
|
8002234: 2301 movs r3, #1
|
|
8002236: 9300 str r3, [sp, #0]
|
|
8002238: 2300 movs r3, #0
|
|
800223a: 2280 movs r2, #128 @ 0x80
|
|
800223c: 4908 ldr r1, [pc, #32] @ (8002260 <CreateTasks+0x60>)
|
|
800223e: 4809 ldr r0, [pc, #36] @ (8002264 <CreateTasks+0x64>)
|
|
8002240: f00b f890 bl 800d364 <xTaskCreate>
|
|
128,
|
|
NULL,
|
|
1,
|
|
NULL
|
|
);
|
|
}
|
|
8002244: bf00 nop
|
|
8002246: 46bd mov sp, r7
|
|
8002248: bd80 pop {r7, pc}
|
|
800224a: bf00 nop
|
|
800224c: 2000034c .word 0x2000034c
|
|
8002250: 08013c90 .word 0x08013c90
|
|
8002254: 08002269 .word 0x08002269
|
|
8002258: 08013c9c .word 0x08013c9c
|
|
800225c: 0800229d .word 0x0800229d
|
|
8002260: 08013cac .word 0x08013cac
|
|
8002264: 080022b1 .word 0x080022b1
|
|
|
|
08002268 <TaskSensors>:
|
|
|
|
void TaskSensors(void* pArg)
|
|
{
|
|
8002268: b580 push {r7, lr}
|
|
800226a: b082 sub sp, #8
|
|
800226c: af00 add r7, sp, #0
|
|
800226e: 6078 str r0, [r7, #4]
|
|
InitSensors();
|
|
8002270: f7ff ff1c bl 80020ac <InitSensors>
|
|
while(1)
|
|
{
|
|
ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
|
|
8002274: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8002278: 2001 movs r0, #1
|
|
800227a: f00b ff95 bl 800e1a8 <ulTaskNotifyTake>
|
|
ReadSensors();
|
|
800227e: f7ff ff25 bl 80020cc <ReadSensors>
|
|
xQueueSend(xQueueSensors, (SensorData_t*) pArg, portMAX_DELAY);
|
|
8002282: 4b05 ldr r3, [pc, #20] @ (8002298 <TaskSensors+0x30>)
|
|
8002284: 6818 ldr r0, [r3, #0]
|
|
8002286: 2300 movs r3, #0
|
|
8002288: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800228c: 6879 ldr r1, [r7, #4]
|
|
800228e: f00a fa61 bl 800c754 <xQueueGenericSend>
|
|
ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
|
|
8002292: bf00 nop
|
|
8002294: e7ee b.n 8002274 <TaskSensors+0xc>
|
|
8002296: bf00 nop
|
|
8002298: 2000035c .word 0x2000035c
|
|
|
|
0800229c <TaskWebServer>:
|
|
}
|
|
}
|
|
|
|
void TaskWebServer(void* pArg)
|
|
{
|
|
800229c: b580 push {r7, lr}
|
|
800229e: b082 sub sp, #8
|
|
80022a0: af00 add r7, sp, #0
|
|
80022a2: 6078 str r0, [r7, #4]
|
|
WifiServer();
|
|
80022a4: f000 f89c bl 80023e0 <WifiServer>
|
|
}
|
|
80022a8: bf00 nop
|
|
80022aa: 3708 adds r7, #8
|
|
80022ac: 46bd mov sp, r7
|
|
80022ae: bd80 pop {r7, pc}
|
|
|
|
080022b0 <TaskLed>:
|
|
|
|
void TaskLed(void* pArg)
|
|
{
|
|
80022b0: b580 push {r7, lr}
|
|
80022b2: b084 sub sp, #16
|
|
80022b4: af00 add r7, sp, #0
|
|
80022b6: 6078 str r0, [r7, #4]
|
|
char ch;
|
|
while(1)
|
|
{
|
|
xQueueReceive(xQueueLED, &ch, portMAX_DELAY);
|
|
80022b8: 4b08 ldr r3, [pc, #32] @ (80022dc <TaskLed+0x2c>)
|
|
80022ba: 681b ldr r3, [r3, #0]
|
|
80022bc: f107 010f add.w r1, r7, #15
|
|
80022c0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80022c4: 4618 mov r0, r3
|
|
80022c6: f00a fc75 bl 800cbb4 <xQueueReceive>
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, ch);
|
|
80022ca: 7bfb ldrb r3, [r7, #15]
|
|
80022cc: 461a mov r2, r3
|
|
80022ce: f44f 4180 mov.w r1, #16384 @ 0x4000
|
|
80022d2: 4803 ldr r0, [pc, #12] @ (80022e0 <TaskLed+0x30>)
|
|
80022d4: f002 fa68 bl 80047a8 <HAL_GPIO_WritePin>
|
|
xQueueReceive(xQueueLED, &ch, portMAX_DELAY);
|
|
80022d8: bf00 nop
|
|
80022da: e7ed b.n 80022b8 <TaskLed+0x8>
|
|
80022dc: 20000358 .word 0x20000358
|
|
80022e0: 48000400 .word 0x48000400
|
|
|
|
080022e4 <WifiStart>:
|
|
/* Private defines -----------------------------------------------------------*/
|
|
|
|
static uint8_t http[1024];
|
|
static uint8_t IP_Addr[4];
|
|
|
|
static int WifiStart(void) {
|
|
80022e4: b5b0 push {r4, r5, r7, lr}
|
|
80022e6: b086 sub sp, #24
|
|
80022e8: af04 add r7, sp, #16
|
|
uint8_t MAC_Addr[6];
|
|
|
|
/*Initialize and use WIFI module */
|
|
if (WIFI_Init() == WIFI_STATUS_OK) {
|
|
80022ea: f009 fe11 bl 800bf10 <WIFI_Init>
|
|
80022ee: 4603 mov r3, r0
|
|
80022f0: 2b00 cmp r3, #0
|
|
80022f2: d123 bne.n 800233c <WifiStart+0x58>
|
|
LOG(("ES-WIFI Initialized.\n"));
|
|
80022f4: 4814 ldr r0, [pc, #80] @ (8002348 <WifiStart+0x64>)
|
|
80022f6: f00d ffd5 bl 80102a4 <puts>
|
|
if (WIFI_GetMAC_Address(MAC_Addr) == WIFI_STATUS_OK) {
|
|
80022fa: 463b mov r3, r7
|
|
80022fc: 4618 mov r0, r3
|
|
80022fe: f009 fe55 bl 800bfac <WIFI_GetMAC_Address>
|
|
8002302: 4603 mov r3, r0
|
|
8002304: 2b00 cmp r3, #0
|
|
8002306: d113 bne.n 8002330 <WifiStart+0x4c>
|
|
LOG(
|
|
8002308: 783b ldrb r3, [r7, #0]
|
|
800230a: 4618 mov r0, r3
|
|
800230c: 787b ldrb r3, [r7, #1]
|
|
800230e: 461c mov r4, r3
|
|
8002310: 78bb ldrb r3, [r7, #2]
|
|
8002312: 461d mov r5, r3
|
|
8002314: 78fb ldrb r3, [r7, #3]
|
|
8002316: 793a ldrb r2, [r7, #4]
|
|
8002318: 7979 ldrb r1, [r7, #5]
|
|
800231a: 9102 str r1, [sp, #8]
|
|
800231c: 9201 str r2, [sp, #4]
|
|
800231e: 9300 str r3, [sp, #0]
|
|
8002320: 462b mov r3, r5
|
|
8002322: 4622 mov r2, r4
|
|
8002324: 4601 mov r1, r0
|
|
8002326: 4809 ldr r0, [pc, #36] @ (800234c <WifiStart+0x68>)
|
|
8002328: f00d ff54 bl 80101d4 <iprintf>
|
|
return -1;
|
|
}
|
|
} else {
|
|
return -1;
|
|
}
|
|
return 0;
|
|
800232c: 2300 movs r3, #0
|
|
800232e: e007 b.n 8002340 <WifiStart+0x5c>
|
|
LOG(("> ERROR : CANNOT get MAC address\n"));
|
|
8002330: 4807 ldr r0, [pc, #28] @ (8002350 <WifiStart+0x6c>)
|
|
8002332: f00d ffb7 bl 80102a4 <puts>
|
|
return -1;
|
|
8002336: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800233a: e001 b.n 8002340 <WifiStart+0x5c>
|
|
return -1;
|
|
800233c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
8002340: 4618 mov r0, r3
|
|
8002342: 3708 adds r7, #8
|
|
8002344: 46bd mov sp, r7
|
|
8002346: bdb0 pop {r4, r5, r7, pc}
|
|
8002348: 08013cb4 .word 0x08013cb4
|
|
800234c: 08013ccc .word 0x08013ccc
|
|
8002350: 08013d00 .word 0x08013d00
|
|
|
|
08002354 <WifiConnect>:
|
|
|
|
int WifiConnect(void) {
|
|
8002354: b580 push {r7, lr}
|
|
8002356: b082 sub sp, #8
|
|
8002358: af02 add r7, sp, #8
|
|
|
|
WifiStart();
|
|
800235a: f7ff ffc3 bl 80022e4 <WifiStart>
|
|
|
|
LOG(("\nConnecting to %s , %s\n",SSID,PASSWORD));
|
|
800235e: 4a19 ldr r2, [pc, #100] @ (80023c4 <WifiConnect+0x70>)
|
|
8002360: 4919 ldr r1, [pc, #100] @ (80023c8 <WifiConnect+0x74>)
|
|
8002362: 481a ldr r0, [pc, #104] @ (80023cc <WifiConnect+0x78>)
|
|
8002364: f00d ff36 bl 80101d4 <iprintf>
|
|
if (WIFI_Connect(SSID, PASSWORD, WIFI_ECN_WPA2_PSK) == WIFI_STATUS_OK) {
|
|
8002368: 2203 movs r2, #3
|
|
800236a: 4916 ldr r1, [pc, #88] @ (80023c4 <WifiConnect+0x70>)
|
|
800236c: 4816 ldr r0, [pc, #88] @ (80023c8 <WifiConnect+0x74>)
|
|
800236e: f009 fdfb bl 800bf68 <WIFI_Connect>
|
|
8002372: 4603 mov r3, r0
|
|
8002374: 2b00 cmp r3, #0
|
|
8002376: d11d bne.n 80023b4 <WifiConnect+0x60>
|
|
if (WIFI_GetIP_Address(IP_Addr) == WIFI_STATUS_OK) {
|
|
8002378: 4815 ldr r0, [pc, #84] @ (80023d0 <WifiConnect+0x7c>)
|
|
800237a: f009 fe2d bl 800bfd8 <WIFI_GetIP_Address>
|
|
800237e: 4603 mov r3, r0
|
|
8002380: 2b00 cmp r3, #0
|
|
8002382: d111 bne.n 80023a8 <WifiConnect+0x54>
|
|
LOG(
|
|
8002384: 4b12 ldr r3, [pc, #72] @ (80023d0 <WifiConnect+0x7c>)
|
|
8002386: 781b ldrb r3, [r3, #0]
|
|
8002388: 4619 mov r1, r3
|
|
800238a: 4b11 ldr r3, [pc, #68] @ (80023d0 <WifiConnect+0x7c>)
|
|
800238c: 785b ldrb r3, [r3, #1]
|
|
800238e: 461a mov r2, r3
|
|
8002390: 4b0f ldr r3, [pc, #60] @ (80023d0 <WifiConnect+0x7c>)
|
|
8002392: 789b ldrb r3, [r3, #2]
|
|
8002394: 4618 mov r0, r3
|
|
8002396: 4b0e ldr r3, [pc, #56] @ (80023d0 <WifiConnect+0x7c>)
|
|
8002398: 78db ldrb r3, [r3, #3]
|
|
800239a: 9300 str r3, [sp, #0]
|
|
800239c: 4603 mov r3, r0
|
|
800239e: 480d ldr r0, [pc, #52] @ (80023d4 <WifiConnect+0x80>)
|
|
80023a0: f00d ff18 bl 80101d4 <iprintf>
|
|
}
|
|
} else {
|
|
LOG(("ERROR : es-wifi module NOT connected\n"));
|
|
return -1;
|
|
}
|
|
return 0;
|
|
80023a4: 2300 movs r3, #0
|
|
80023a6: e00a b.n 80023be <WifiConnect+0x6a>
|
|
LOG((" ERROR : es-wifi module CANNOT get IP address\n"));
|
|
80023a8: 480b ldr r0, [pc, #44] @ (80023d8 <WifiConnect+0x84>)
|
|
80023aa: f00d ff7b bl 80102a4 <puts>
|
|
return -1;
|
|
80023ae: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80023b2: e004 b.n 80023be <WifiConnect+0x6a>
|
|
LOG(("ERROR : es-wifi module NOT connected\n"));
|
|
80023b4: 4809 ldr r0, [pc, #36] @ (80023dc <WifiConnect+0x88>)
|
|
80023b6: f00d ff75 bl 80102a4 <puts>
|
|
return -1;
|
|
80023ba: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
80023be: 4618 mov r0, r3
|
|
80023c0: 46bd mov sp, r7
|
|
80023c2: bd80 pop {r7, pc}
|
|
80023c4: 08013d24 .word 0x08013d24
|
|
80023c8: 08013d34 .word 0x08013d34
|
|
80023cc: 08013d40 .word 0x08013d40
|
|
80023d0: 20000760 .word 0x20000760
|
|
80023d4: 08013d58 .word 0x08013d58
|
|
80023d8: 08013d94 .word 0x08013d94
|
|
80023dc: 08013dc4 .word 0x08013dc4
|
|
|
|
080023e0 <WifiServer>:
|
|
|
|
int WifiServer(void) {
|
|
80023e0: b590 push {r4, r7, lr}
|
|
80023e2: b087 sub sp, #28
|
|
80023e4: af02 add r7, sp, #8
|
|
bool StopServer = false;
|
|
80023e6: 2300 movs r3, #0
|
|
80023e8: 73fb strb r3, [r7, #15]
|
|
|
|
LOG(("\nRunning HTML Server test\n"));
|
|
80023ea: 483d ldr r0, [pc, #244] @ (80024e0 <WifiServer+0x100>)
|
|
80023ec: f00d ff5a bl 80102a4 <puts>
|
|
if (WifiConnect() != 0)
|
|
80023f0: f7ff ffb0 bl 8002354 <WifiConnect>
|
|
80023f4: 4603 mov r3, r0
|
|
80023f6: 2b00 cmp r3, #0
|
|
80023f8: d002 beq.n 8002400 <WifiServer+0x20>
|
|
return -1;
|
|
80023fa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80023fe: e06b b.n 80024d8 <WifiServer+0xf8>
|
|
|
|
if (WIFI_STATUS_OK
|
|
!= WIFI_StartServer(SOCKET, WIFI_TCP_PROTOCOL, 1, "", PORT)) {
|
|
8002400: 2350 movs r3, #80 @ 0x50
|
|
8002402: 9300 str r3, [sp, #0]
|
|
8002404: 4b37 ldr r3, [pc, #220] @ (80024e4 <WifiServer+0x104>)
|
|
8002406: 2201 movs r2, #1
|
|
8002408: 2100 movs r1, #0
|
|
800240a: 2000 movs r0, #0
|
|
800240c: f009 fe00 bl 800c010 <WIFI_StartServer>
|
|
8002410: 4603 mov r3, r0
|
|
if (WIFI_STATUS_OK
|
|
8002412: 2b00 cmp r3, #0
|
|
8002414: d002 beq.n 800241c <WifiServer+0x3c>
|
|
LOG(("ERROR: Cannot start server.\n"));
|
|
8002416: 4834 ldr r0, [pc, #208] @ (80024e8 <WifiServer+0x108>)
|
|
8002418: f00d ff44 bl 80102a4 <puts>
|
|
}
|
|
|
|
LOG(
|
|
800241c: 4b33 ldr r3, [pc, #204] @ (80024ec <WifiServer+0x10c>)
|
|
800241e: 781b ldrb r3, [r3, #0]
|
|
8002420: 4619 mov r1, r3
|
|
8002422: 4b32 ldr r3, [pc, #200] @ (80024ec <WifiServer+0x10c>)
|
|
8002424: 785b ldrb r3, [r3, #1]
|
|
8002426: 461a mov r2, r3
|
|
8002428: 4b30 ldr r3, [pc, #192] @ (80024ec <WifiServer+0x10c>)
|
|
800242a: 789b ldrb r3, [r3, #2]
|
|
800242c: 4618 mov r0, r3
|
|
800242e: 4b2f ldr r3, [pc, #188] @ (80024ec <WifiServer+0x10c>)
|
|
8002430: 78db ldrb r3, [r3, #3]
|
|
8002432: 9300 str r3, [sp, #0]
|
|
8002434: 4603 mov r3, r0
|
|
8002436: 482e ldr r0, [pc, #184] @ (80024f0 <WifiServer+0x110>)
|
|
8002438: f00d fecc bl 80101d4 <iprintf>
|
|
|
|
do {
|
|
uint8_t RemoteIP[4];
|
|
uint16_t RemotePort;
|
|
|
|
while (WIFI_STATUS_OK
|
|
800243c: e00f b.n 800245e <WifiServer+0x7e>
|
|
!= WIFI_WaitServerConnection(SOCKET, 1000, RemoteIP,
|
|
&RemotePort)) {
|
|
LOG(
|
|
800243e: 4b2b ldr r3, [pc, #172] @ (80024ec <WifiServer+0x10c>)
|
|
8002440: 781b ldrb r3, [r3, #0]
|
|
8002442: 4619 mov r1, r3
|
|
8002444: 4b29 ldr r3, [pc, #164] @ (80024ec <WifiServer+0x10c>)
|
|
8002446: 785b ldrb r3, [r3, #1]
|
|
8002448: 461a mov r2, r3
|
|
800244a: 4b28 ldr r3, [pc, #160] @ (80024ec <WifiServer+0x10c>)
|
|
800244c: 789b ldrb r3, [r3, #2]
|
|
800244e: 4618 mov r0, r3
|
|
8002450: 4b26 ldr r3, [pc, #152] @ (80024ec <WifiServer+0x10c>)
|
|
8002452: 78db ldrb r3, [r3, #3]
|
|
8002454: 9300 str r3, [sp, #0]
|
|
8002456: 4603 mov r3, r0
|
|
8002458: 4826 ldr r0, [pc, #152] @ (80024f4 <WifiServer+0x114>)
|
|
800245a: f00d febb bl 80101d4 <iprintf>
|
|
!= WIFI_WaitServerConnection(SOCKET, 1000, RemoteIP,
|
|
800245e: 1dbb adds r3, r7, #6
|
|
8002460: f107 0208 add.w r2, r7, #8
|
|
8002464: f44f 717a mov.w r1, #1000 @ 0x3e8
|
|
8002468: 2000 movs r0, #0
|
|
800246a: f009 fe01 bl 800c070 <WIFI_WaitServerConnection>
|
|
800246e: 4603 mov r3, r0
|
|
8002470: 2b00 cmp r3, #0
|
|
8002472: d1e4 bne.n 800243e <WifiServer+0x5e>
|
|
("Waiting connection to %d.%d.%d.%d\n",IP_Addr[0],IP_Addr[1],IP_Addr[2],IP_Addr[3]));
|
|
|
|
}
|
|
|
|
LOG(
|
|
8002474: 7a3b ldrb r3, [r7, #8]
|
|
8002476: 4619 mov r1, r3
|
|
8002478: 7a7b ldrb r3, [r7, #9]
|
|
800247a: 4618 mov r0, r3
|
|
800247c: 7abb ldrb r3, [r7, #10]
|
|
800247e: 461c mov r4, r3
|
|
8002480: 7afb ldrb r3, [r7, #11]
|
|
8002482: 88fa ldrh r2, [r7, #6]
|
|
8002484: 9201 str r2, [sp, #4]
|
|
8002486: 9300 str r3, [sp, #0]
|
|
8002488: 4623 mov r3, r4
|
|
800248a: 4602 mov r2, r0
|
|
800248c: 481a ldr r0, [pc, #104] @ (80024f8 <WifiServer+0x118>)
|
|
800248e: f00d fea1 bl 80101d4 <iprintf>
|
|
("Client connected %d.%d.%d.%d:%d\n",RemoteIP[0],RemoteIP[1],RemoteIP[2],RemoteIP[3],RemotePort));
|
|
|
|
StopServer = WebServerProcess();
|
|
8002492: f000 f839 bl 8002508 <WebServerProcess>
|
|
8002496: 4603 mov r3, r0
|
|
8002498: 73fb strb r3, [r7, #15]
|
|
|
|
if (WIFI_CloseServerConnection(SOCKET) != WIFI_STATUS_OK) {
|
|
800249a: 2000 movs r0, #0
|
|
800249c: f009 fe2c bl 800c0f8 <WIFI_CloseServerConnection>
|
|
80024a0: 4603 mov r3, r0
|
|
80024a2: 2b00 cmp r3, #0
|
|
80024a4: d005 beq.n 80024b2 <WifiServer+0xd2>
|
|
LOG(("ERROR: failed to close current Server connection\n"));
|
|
80024a6: 4815 ldr r0, [pc, #84] @ (80024fc <WifiServer+0x11c>)
|
|
80024a8: f00d fefc bl 80102a4 <puts>
|
|
return -1;
|
|
80024ac: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80024b0: e012 b.n 80024d8 <WifiServer+0xf8>
|
|
}
|
|
} while (StopServer == false);
|
|
80024b2: 7bfb ldrb r3, [r7, #15]
|
|
80024b4: f083 0301 eor.w r3, r3, #1
|
|
80024b8: b2db uxtb r3, r3
|
|
80024ba: 2b00 cmp r3, #0
|
|
80024bc: d1cf bne.n 800245e <WifiServer+0x7e>
|
|
|
|
if (WIFI_STATUS_OK != WIFI_StopServer(SOCKET)) {
|
|
80024be: 2000 movs r0, #0
|
|
80024c0: f009 fe30 bl 800c124 <WIFI_StopServer>
|
|
80024c4: 4603 mov r3, r0
|
|
80024c6: 2b00 cmp r3, #0
|
|
80024c8: d002 beq.n 80024d0 <WifiServer+0xf0>
|
|
LOG(("ERROR: Cannot stop server.\n"));
|
|
80024ca: 480d ldr r0, [pc, #52] @ (8002500 <WifiServer+0x120>)
|
|
80024cc: f00d feea bl 80102a4 <puts>
|
|
}
|
|
|
|
LOG(("Server is stop\n"));
|
|
80024d0: 480c ldr r0, [pc, #48] @ (8002504 <WifiServer+0x124>)
|
|
80024d2: f00d fee7 bl 80102a4 <puts>
|
|
return 0;
|
|
80024d6: 2300 movs r3, #0
|
|
}
|
|
80024d8: 4618 mov r0, r3
|
|
80024da: 3714 adds r7, #20
|
|
80024dc: 46bd mov sp, r7
|
|
80024de: bd90 pop {r4, r7, pc}
|
|
80024e0: 08013dec .word 0x08013dec
|
|
80024e4: 08013e08 .word 0x08013e08
|
|
80024e8: 08013e0c .word 0x08013e0c
|
|
80024ec: 20000760 .word 0x20000760
|
|
80024f0: 08013e28 .word 0x08013e28
|
|
80024f4: 08013e78 .word 0x08013e78
|
|
80024f8: 08013e9c .word 0x08013e9c
|
|
80024fc: 08013ec0 .word 0x08013ec0
|
|
8002500: 08013ef4 .word 0x08013ef4
|
|
8002504: 08013f10 .word 0x08013f10
|
|
|
|
08002508 <WebServerProcess>:
|
|
|
|
static bool WebServerProcess(void)
|
|
{
|
|
8002508: b5f0 push {r4, r5, r6, r7, lr}
|
|
800250a: b09f sub sp, #124 @ 0x7c
|
|
800250c: af08 add r7, sp, #32
|
|
uint8_t LedState = 1;
|
|
800250e: 2301 movs r3, #1
|
|
8002510: f887 3057 strb.w r3, [r7, #87] @ 0x57
|
|
SensorData_t aux;
|
|
uint16_t respLen;
|
|
static uint8_t resp[1024];
|
|
bool stopserver = false;
|
|
8002514: 2300 movs r3, #0
|
|
8002516: f887 3056 strb.w r3, [r7, #86] @ 0x56
|
|
|
|
if (WIFI_STATUS_OK
|
|
== WIFI_ReceiveData(SOCKET, resp, 1000, &respLen,
|
|
800251a: f107 032a add.w r3, r7, #42 @ 0x2a
|
|
800251e: f242 7210 movw r2, #10000 @ 0x2710
|
|
8002522: 9200 str r2, [sp, #0]
|
|
8002524: f44f 727a mov.w r2, #1000 @ 0x3e8
|
|
8002528: 4964 ldr r1, [pc, #400] @ (80026bc <WebServerProcess+0x1b4>)
|
|
800252a: 2000 movs r0, #0
|
|
800252c: f009 fe34 bl 800c198 <WIFI_ReceiveData>
|
|
8002530: 4603 mov r3, r0
|
|
if (WIFI_STATUS_OK
|
|
8002532: 2b00 cmp r3, #0
|
|
8002534: f040 80b8 bne.w 80026a8 <WebServerProcess+0x1a0>
|
|
WIFI_READ_TIMEOUT)) {
|
|
LOG(("get %d byte from server\n",respLen));
|
|
8002538: 8d7b ldrh r3, [r7, #42] @ 0x2a
|
|
800253a: 4619 mov r1, r3
|
|
800253c: 4860 ldr r0, [pc, #384] @ (80026c0 <WebServerProcess+0x1b8>)
|
|
800253e: f00d fe49 bl 80101d4 <iprintf>
|
|
|
|
if (respLen > 0) {
|
|
8002542: 8d7b ldrh r3, [r7, #42] @ 0x2a
|
|
8002544: 2b00 cmp r3, #0
|
|
8002546: f000 80b2 beq.w 80026ae <WebServerProcess+0x1a6>
|
|
if (strstr((char*) resp, "GET")) /* GET: put web page */
|
|
800254a: 495e ldr r1, [pc, #376] @ (80026c4 <WebServerProcess+0x1bc>)
|
|
800254c: 485b ldr r0, [pc, #364] @ (80026bc <WebServerProcess+0x1b4>)
|
|
800254e: f00e f853 bl 80105f8 <strstr>
|
|
8002552: 4603 mov r3, r0
|
|
8002554: 2b00 cmp r3, #0
|
|
8002556: d020 beq.n 800259a <WebServerProcess+0x92>
|
|
{
|
|
aux = GetSensors(); //BSP_TSENSOR_ReadTemp();
|
|
8002558: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
800255c: 4618 mov r0, r3
|
|
800255e: f7ff fe27 bl 80021b0 <GetSensors>
|
|
if (SendWebPage(LedState, aux) != WIFI_STATUS_OK) {
|
|
8002562: f897 6057 ldrb.w r6, [r7, #87] @ 0x57
|
|
8002566: 466d mov r5, sp
|
|
8002568: f107 0438 add.w r4, r7, #56 @ 0x38
|
|
800256c: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
800256e: c50f stmia r5!, {r0, r1, r2, r3}
|
|
8002570: e894 0007 ldmia.w r4, {r0, r1, r2}
|
|
8002574: e885 0007 stmia.w r5, {r0, r1, r2}
|
|
8002578: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
800257c: cb0e ldmia r3, {r1, r2, r3}
|
|
800257e: 4630 mov r0, r6
|
|
8002580: f000 f8ba bl 80026f8 <SendWebPage>
|
|
8002584: 4603 mov r3, r0
|
|
8002586: 2b00 cmp r3, #0
|
|
8002588: d003 beq.n 8002592 <WebServerProcess+0x8a>
|
|
LOG(("> ERROR : Cannot send web page\n"));
|
|
800258a: 484f ldr r0, [pc, #316] @ (80026c8 <WebServerProcess+0x1c0>)
|
|
800258c: f00d fe8a bl 80102a4 <puts>
|
|
8002590: e08d b.n 80026ae <WebServerProcess+0x1a6>
|
|
} else {
|
|
LOG(("Send page after GET command\n"));
|
|
8002592: 484e ldr r0, [pc, #312] @ (80026cc <WebServerProcess+0x1c4>)
|
|
8002594: f00d fe86 bl 80102a4 <puts>
|
|
8002598: e089 b.n 80026ae <WebServerProcess+0x1a6>
|
|
}
|
|
} else if (strstr((char*) resp, "POST"))/* POST: received info */
|
|
800259a: 494d ldr r1, [pc, #308] @ (80026d0 <WebServerProcess+0x1c8>)
|
|
800259c: 4847 ldr r0, [pc, #284] @ (80026bc <WebServerProcess+0x1b4>)
|
|
800259e: f00e f82b bl 80105f8 <strstr>
|
|
80025a2: 4603 mov r3, r0
|
|
80025a4: 2b00 cmp r3, #0
|
|
80025a6: f000 8082 beq.w 80026ae <WebServerProcess+0x1a6>
|
|
{
|
|
LOG(("Post request\n"));
|
|
80025aa: 484a ldr r0, [pc, #296] @ (80026d4 <WebServerProcess+0x1cc>)
|
|
80025ac: f00d fe7a bl 80102a4 <puts>
|
|
|
|
if (strstr((char*) resp, "radio")) {
|
|
80025b0: 4949 ldr r1, [pc, #292] @ (80026d8 <WebServerProcess+0x1d0>)
|
|
80025b2: 4842 ldr r0, [pc, #264] @ (80026bc <WebServerProcess+0x1b4>)
|
|
80025b4: f00e f820 bl 80105f8 <strstr>
|
|
80025b8: 4603 mov r3, r0
|
|
80025ba: 2b00 cmp r3, #0
|
|
80025bc: d02d beq.n 800261a <WebServerProcess+0x112>
|
|
if (strstr((char*) resp, "radio=0")) {
|
|
80025be: 4947 ldr r1, [pc, #284] @ (80026dc <WebServerProcess+0x1d4>)
|
|
80025c0: 483e ldr r0, [pc, #248] @ (80026bc <WebServerProcess+0x1b4>)
|
|
80025c2: f00e f819 bl 80105f8 <strstr>
|
|
80025c6: 4603 mov r3, r0
|
|
80025c8: 2b00 cmp r3, #0
|
|
80025ca: d008 beq.n 80025de <WebServerProcess+0xd6>
|
|
LedState = 0;
|
|
80025cc: 2300 movs r3, #0
|
|
80025ce: f887 3057 strb.w r3, [r7, #87] @ 0x57
|
|
QueueLed(LedState);
|
|
80025d2: f897 3057 ldrb.w r3, [r7, #87] @ 0x57
|
|
80025d6: 4618 mov r0, r3
|
|
80025d8: f7ff fdd6 bl 8002188 <QueueLed>
|
|
80025dc: e00e b.n 80025fc <WebServerProcess+0xf4>
|
|
} else if (strstr((char*) resp, "radio=1")) {
|
|
80025de: 4940 ldr r1, [pc, #256] @ (80026e0 <WebServerProcess+0x1d8>)
|
|
80025e0: 4836 ldr r0, [pc, #216] @ (80026bc <WebServerProcess+0x1b4>)
|
|
80025e2: f00e f809 bl 80105f8 <strstr>
|
|
80025e6: 4603 mov r3, r0
|
|
80025e8: 2b00 cmp r3, #0
|
|
80025ea: d007 beq.n 80025fc <WebServerProcess+0xf4>
|
|
LedState = 1;
|
|
80025ec: 2301 movs r3, #1
|
|
80025ee: f887 3057 strb.w r3, [r7, #87] @ 0x57
|
|
QueueLed(LedState);
|
|
80025f2: f897 3057 ldrb.w r3, [r7, #87] @ 0x57
|
|
80025f6: 4618 mov r0, r3
|
|
80025f8: f7ff fdc6 bl 8002188 <QueueLed>
|
|
}
|
|
aux = GetSensors(); //BSP_TSENSOR_ReadTemp();
|
|
80025fc: 463b mov r3, r7
|
|
80025fe: 4618 mov r0, r3
|
|
8002600: f7ff fdd6 bl 80021b0 <GetSensors>
|
|
8002604: f107 042c add.w r4, r7, #44 @ 0x2c
|
|
8002608: 463d mov r5, r7
|
|
800260a: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
800260c: c40f stmia r4!, {r0, r1, r2, r3}
|
|
800260e: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8002610: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8002612: e895 0003 ldmia.w r5, {r0, r1}
|
|
8002616: e884 0003 stmia.w r4, {r0, r1}
|
|
}
|
|
if (strstr((char*) resp, "stop_server")) {
|
|
800261a: 4932 ldr r1, [pc, #200] @ (80026e4 <WebServerProcess+0x1dc>)
|
|
800261c: 4827 ldr r0, [pc, #156] @ (80026bc <WebServerProcess+0x1b4>)
|
|
800261e: f00d ffeb bl 80105f8 <strstr>
|
|
8002622: 4603 mov r3, r0
|
|
8002624: 2b00 cmp r3, #0
|
|
8002626: d014 beq.n 8002652 <WebServerProcess+0x14a>
|
|
if (strstr((char*) resp, "stop_server=0")) {
|
|
8002628: 492f ldr r1, [pc, #188] @ (80026e8 <WebServerProcess+0x1e0>)
|
|
800262a: 4824 ldr r0, [pc, #144] @ (80026bc <WebServerProcess+0x1b4>)
|
|
800262c: f00d ffe4 bl 80105f8 <strstr>
|
|
8002630: 4603 mov r3, r0
|
|
8002632: 2b00 cmp r3, #0
|
|
8002634: d003 beq.n 800263e <WebServerProcess+0x136>
|
|
stopserver = false;
|
|
8002636: 2300 movs r3, #0
|
|
8002638: f887 3056 strb.w r3, [r7, #86] @ 0x56
|
|
800263c: e009 b.n 8002652 <WebServerProcess+0x14a>
|
|
} else if (strstr((char*) resp, "stop_server=1")) {
|
|
800263e: 492b ldr r1, [pc, #172] @ (80026ec <WebServerProcess+0x1e4>)
|
|
8002640: 481e ldr r0, [pc, #120] @ (80026bc <WebServerProcess+0x1b4>)
|
|
8002642: f00d ffd9 bl 80105f8 <strstr>
|
|
8002646: 4603 mov r3, r0
|
|
8002648: 2b00 cmp r3, #0
|
|
800264a: d002 beq.n 8002652 <WebServerProcess+0x14a>
|
|
stopserver = true;
|
|
800264c: 2301 movs r3, #1
|
|
800264e: f887 3056 strb.w r3, [r7, #86] @ 0x56
|
|
}
|
|
}
|
|
aux = GetSensors(); //BSP_TSENSOR_ReadTemp();
|
|
8002652: 463b mov r3, r7
|
|
8002654: 4618 mov r0, r3
|
|
8002656: f7ff fdab bl 80021b0 <GetSensors>
|
|
800265a: f107 042c add.w r4, r7, #44 @ 0x2c
|
|
800265e: 463d mov r5, r7
|
|
8002660: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8002662: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8002664: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8002666: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8002668: e895 0003 ldmia.w r5, {r0, r1}
|
|
800266c: e884 0003 stmia.w r4, {r0, r1}
|
|
if (SendWebPage(LedState, aux) != WIFI_STATUS_OK) {
|
|
8002670: f897 6057 ldrb.w r6, [r7, #87] @ 0x57
|
|
8002674: 466d mov r5, sp
|
|
8002676: f107 0438 add.w r4, r7, #56 @ 0x38
|
|
800267a: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
800267c: c50f stmia r5!, {r0, r1, r2, r3}
|
|
800267e: e894 0007 ldmia.w r4, {r0, r1, r2}
|
|
8002682: e885 0007 stmia.w r5, {r0, r1, r2}
|
|
8002686: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
800268a: cb0e ldmia r3, {r1, r2, r3}
|
|
800268c: 4630 mov r0, r6
|
|
800268e: f000 f833 bl 80026f8 <SendWebPage>
|
|
8002692: 4603 mov r3, r0
|
|
8002694: 2b00 cmp r3, #0
|
|
8002696: d003 beq.n 80026a0 <WebServerProcess+0x198>
|
|
LOG(("> ERROR : Cannot send web page\n"));
|
|
8002698: 480b ldr r0, [pc, #44] @ (80026c8 <WebServerProcess+0x1c0>)
|
|
800269a: f00d fe03 bl 80102a4 <puts>
|
|
800269e: e006 b.n 80026ae <WebServerProcess+0x1a6>
|
|
} else {
|
|
LOG(("Send Page after POST command\n"));
|
|
80026a0: 4813 ldr r0, [pc, #76] @ (80026f0 <WebServerProcess+0x1e8>)
|
|
80026a2: f00d fdff bl 80102a4 <puts>
|
|
80026a6: e002 b.n 80026ae <WebServerProcess+0x1a6>
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
LOG(("Client close connection\n"));
|
|
80026a8: 4812 ldr r0, [pc, #72] @ (80026f4 <WebServerProcess+0x1ec>)
|
|
80026aa: f00d fdfb bl 80102a4 <puts>
|
|
}
|
|
return stopserver;
|
|
80026ae: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
|
|
}
|
|
80026b2: 4618 mov r0, r3
|
|
80026b4: 375c adds r7, #92 @ 0x5c
|
|
80026b6: 46bd mov sp, r7
|
|
80026b8: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80026ba: bf00 nop
|
|
80026bc: 20000764 .word 0x20000764
|
|
80026c0: 08013f20 .word 0x08013f20
|
|
80026c4: 08013f3c .word 0x08013f3c
|
|
80026c8: 08013f40 .word 0x08013f40
|
|
80026cc: 08013f60 .word 0x08013f60
|
|
80026d0: 08013f80 .word 0x08013f80
|
|
80026d4: 08013f88 .word 0x08013f88
|
|
80026d8: 08013f98 .word 0x08013f98
|
|
80026dc: 08013fa0 .word 0x08013fa0
|
|
80026e0: 08013fa8 .word 0x08013fa8
|
|
80026e4: 08013fb0 .word 0x08013fb0
|
|
80026e8: 08013fbc .word 0x08013fbc
|
|
80026ec: 08013fcc .word 0x08013fcc
|
|
80026f0: 08013fdc .word 0x08013fdc
|
|
80026f4: 08013ffc .word 0x08013ffc
|
|
|
|
080026f8 <SendWebPage>:
|
|
/**
|
|
* @brief Send HTML page
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static WIFI_Status_t SendWebPage(uint8_t ledIsOn, SensorData_t payload) {
|
|
80026f8: b084 sub sp, #16
|
|
80026fa: b5f0 push {r4, r5, r6, r7, lr}
|
|
80026fc: b093 sub sp, #76 @ 0x4c
|
|
80026fe: af02 add r7, sp, #8
|
|
8002700: 4604 mov r4, r0
|
|
8002702: f107 005c add.w r0, r7, #92 @ 0x5c
|
|
8002706: e880 000e stmia.w r0, {r1, r2, r3}
|
|
800270a: 4623 mov r3, r4
|
|
800270c: 71fb strb r3, [r7, #7]
|
|
uint8_t temp[50];
|
|
uint16_t SentDataLength;
|
|
WIFI_Status_t ret;
|
|
|
|
/* construct web page content */
|
|
strcpy((char*) http,
|
|
800270e: 4ac0 ldr r2, [pc, #768] @ (8002a10 <SendWebPage+0x318>)
|
|
8002710: 4bc0 ldr r3, [pc, #768] @ (8002a14 <SendWebPage+0x31c>)
|
|
8002712: 4614 mov r4, r2
|
|
8002714: 461d mov r5, r3
|
|
8002716: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8002718: c40f stmia r4!, {r0, r1, r2, r3}
|
|
800271a: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
800271c: c40f stmia r4!, {r0, r1, r2, r3}
|
|
800271e: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8002720: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8002722: e895 000f ldmia.w r5, {r0, r1, r2, r3}
|
|
8002726: c407 stmia r4!, {r0, r1, r2}
|
|
8002728: 8023 strh r3, [r4, #0]
|
|
800272a: 3402 adds r4, #2
|
|
800272c: 0c1b lsrs r3, r3, #16
|
|
800272e: 7023 strb r3, [r4, #0]
|
|
(char*) "HTTP/1.0 200 OK\r\nContent-Type: text/html\r\nPragma: no-cache\r\n\r\n");
|
|
strcat((char*) http, (char*) "<html>\r\n<body>\r\n");
|
|
8002730: 48b7 ldr r0, [pc, #732] @ (8002a10 <SendWebPage+0x318>)
|
|
8002732: f7fd fd9d bl 8000270 <strlen>
|
|
8002736: 4603 mov r3, r0
|
|
8002738: 461a mov r2, r3
|
|
800273a: 4bb5 ldr r3, [pc, #724] @ (8002a10 <SendWebPage+0x318>)
|
|
800273c: 4413 add r3, r2
|
|
800273e: 4ab6 ldr r2, [pc, #728] @ (8002a18 <SendWebPage+0x320>)
|
|
8002740: 461d mov r5, r3
|
|
8002742: 4614 mov r4, r2
|
|
8002744: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
8002746: 6028 str r0, [r5, #0]
|
|
8002748: 6069 str r1, [r5, #4]
|
|
800274a: 60aa str r2, [r5, #8]
|
|
800274c: 60eb str r3, [r5, #12]
|
|
800274e: 7823 ldrb r3, [r4, #0]
|
|
8002750: 742b strb r3, [r5, #16]
|
|
strcat((char*) http, (char*) "<title>STM32 Web Server</title>\r\n");
|
|
8002752: 48af ldr r0, [pc, #700] @ (8002a10 <SendWebPage+0x318>)
|
|
8002754: f7fd fd8c bl 8000270 <strlen>
|
|
8002758: 4603 mov r3, r0
|
|
800275a: 461a mov r2, r3
|
|
800275c: 4bac ldr r3, [pc, #688] @ (8002a10 <SendWebPage+0x318>)
|
|
800275e: 4413 add r3, r2
|
|
8002760: 4aae ldr r2, [pc, #696] @ (8002a1c <SendWebPage+0x324>)
|
|
8002762: 4614 mov r4, r2
|
|
8002764: 469c mov ip, r3
|
|
8002766: f104 0e20 add.w lr, r4, #32
|
|
800276a: 4665 mov r5, ip
|
|
800276c: 4626 mov r6, r4
|
|
800276e: ce0f ldmia r6!, {r0, r1, r2, r3}
|
|
8002770: 6028 str r0, [r5, #0]
|
|
8002772: 6069 str r1, [r5, #4]
|
|
8002774: 60aa str r2, [r5, #8]
|
|
8002776: 60eb str r3, [r5, #12]
|
|
8002778: 3410 adds r4, #16
|
|
800277a: f10c 0c10 add.w ip, ip, #16
|
|
800277e: 4574 cmp r4, lr
|
|
8002780: d1f3 bne.n 800276a <SendWebPage+0x72>
|
|
8002782: 4662 mov r2, ip
|
|
8002784: 4623 mov r3, r4
|
|
8002786: 881b ldrh r3, [r3, #0]
|
|
8002788: 8013 strh r3, [r2, #0]
|
|
strcat((char*) http,
|
|
800278a: 48a1 ldr r0, [pc, #644] @ (8002a10 <SendWebPage+0x318>)
|
|
800278c: f7fd fd70 bl 8000270 <strlen>
|
|
8002790: 4603 mov r3, r0
|
|
8002792: 461a mov r2, r3
|
|
8002794: 4b9e ldr r3, [pc, #632] @ (8002a10 <SendWebPage+0x318>)
|
|
8002796: 4413 add r3, r2
|
|
8002798: 4aa1 ldr r2, [pc, #644] @ (8002a20 <SendWebPage+0x328>)
|
|
800279a: 4614 mov r4, r2
|
|
800279c: 469c mov ip, r3
|
|
800279e: f104 0e30 add.w lr, r4, #48 @ 0x30
|
|
80027a2: 4665 mov r5, ip
|
|
80027a4: 4626 mov r6, r4
|
|
80027a6: ce0f ldmia r6!, {r0, r1, r2, r3}
|
|
80027a8: 6028 str r0, [r5, #0]
|
|
80027aa: 6069 str r1, [r5, #4]
|
|
80027ac: 60aa str r2, [r5, #8]
|
|
80027ae: 60eb str r3, [r5, #12]
|
|
80027b0: 3410 adds r4, #16
|
|
80027b2: f10c 0c10 add.w ip, ip, #16
|
|
80027b6: 4574 cmp r4, lr
|
|
80027b8: d1f3 bne.n 80027a2 <SendWebPage+0xaa>
|
|
80027ba: 4665 mov r5, ip
|
|
80027bc: 4623 mov r3, r4
|
|
80027be: cb07 ldmia r3!, {r0, r1, r2}
|
|
80027c0: 6028 str r0, [r5, #0]
|
|
80027c2: 6069 str r1, [r5, #4]
|
|
80027c4: 60aa str r2, [r5, #8]
|
|
80027c6: 781b ldrb r3, [r3, #0]
|
|
80027c8: 732b strb r3, [r5, #12]
|
|
(char*) "<h2>InventekSys : Web Server using Es-Wifi with STM32</h2>\r\n");
|
|
strcat((char*) http, (char*) "<br /><hr>\r\n");
|
|
80027ca: 4891 ldr r0, [pc, #580] @ (8002a10 <SendWebPage+0x318>)
|
|
80027cc: f7fd fd50 bl 8000270 <strlen>
|
|
80027d0: 4603 mov r3, r0
|
|
80027d2: 461a mov r2, r3
|
|
80027d4: 4b8e ldr r3, [pc, #568] @ (8002a10 <SendWebPage+0x318>)
|
|
80027d6: 4413 add r3, r2
|
|
80027d8: 4a92 ldr r2, [pc, #584] @ (8002a24 <SendWebPage+0x32c>)
|
|
80027da: 461c mov r4, r3
|
|
80027dc: 4613 mov r3, r2
|
|
80027de: cb07 ldmia r3!, {r0, r1, r2}
|
|
80027e0: 6020 str r0, [r4, #0]
|
|
80027e2: 6061 str r1, [r4, #4]
|
|
80027e4: 60a2 str r2, [r4, #8]
|
|
80027e6: 781b ldrb r3, [r3, #0]
|
|
80027e8: 7323 strb r3, [r4, #12]
|
|
strcat((char*) http,
|
|
80027ea: 4889 ldr r0, [pc, #548] @ (8002a10 <SendWebPage+0x318>)
|
|
80027ec: f7fd fd40 bl 8000270 <strlen>
|
|
80027f0: 4603 mov r3, r0
|
|
80027f2: 461a mov r2, r3
|
|
80027f4: 4b86 ldr r3, [pc, #536] @ (8002a10 <SendWebPage+0x318>)
|
|
80027f6: 4413 add r3, r2
|
|
80027f8: 4a8b ldr r2, [pc, #556] @ (8002a28 <SendWebPage+0x330>)
|
|
80027fa: 4614 mov r4, r2
|
|
80027fc: 469c mov ip, r3
|
|
80027fe: f104 0e40 add.w lr, r4, #64 @ 0x40
|
|
8002802: 4665 mov r5, ip
|
|
8002804: 4626 mov r6, r4
|
|
8002806: ce0f ldmia r6!, {r0, r1, r2, r3}
|
|
8002808: 6028 str r0, [r5, #0]
|
|
800280a: 6069 str r1, [r5, #4]
|
|
800280c: 60aa str r2, [r5, #8]
|
|
800280e: 60eb str r3, [r5, #12]
|
|
8002810: 3410 adds r4, #16
|
|
8002812: f10c 0c10 add.w ip, ip, #16
|
|
8002816: 4574 cmp r4, lr
|
|
8002818: d1f3 bne.n 8002802 <SendWebPage+0x10a>
|
|
(char*) "<p><form method=\"POST\"><strong>Temp: <input type=\"text\" value=\"");
|
|
sprintf((char*) temp, "%f", payload.temperature);
|
|
800281a: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800281c: 4618 mov r0, r3
|
|
800281e: f7fd fe93 bl 8000548 <__aeabi_f2d>
|
|
8002822: 4602 mov r2, r0
|
|
8002824: 460b mov r3, r1
|
|
8002826: f107 000c add.w r0, r7, #12
|
|
800282a: 4980 ldr r1, [pc, #512] @ (8002a2c <SendWebPage+0x334>)
|
|
800282c: f00d fd42 bl 80102b4 <siprintf>
|
|
strcat((char*) http, (char*) temp);
|
|
8002830: f107 030c add.w r3, r7, #12
|
|
8002834: 4619 mov r1, r3
|
|
8002836: 4876 ldr r0, [pc, #472] @ (8002a10 <SendWebPage+0x318>)
|
|
8002838: f00d fe4e bl 80104d8 <strcat>
|
|
strcat((char*) http, (char*) "\"> <sup>O</sup>C");
|
|
800283c: 4874 ldr r0, [pc, #464] @ (8002a10 <SendWebPage+0x318>)
|
|
800283e: f7fd fd17 bl 8000270 <strlen>
|
|
8002842: 4603 mov r3, r0
|
|
8002844: 461a mov r2, r3
|
|
8002846: 4b72 ldr r3, [pc, #456] @ (8002a10 <SendWebPage+0x318>)
|
|
8002848: 4413 add r3, r2
|
|
800284a: 4a79 ldr r2, [pc, #484] @ (8002a30 <SendWebPage+0x338>)
|
|
800284c: 461d mov r5, r3
|
|
800284e: 4614 mov r4, r2
|
|
8002850: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
8002852: 6028 str r0, [r5, #0]
|
|
8002854: 6069 str r1, [r5, #4]
|
|
8002856: 60aa str r2, [r5, #8]
|
|
8002858: 60eb str r3, [r5, #12]
|
|
800285a: 7823 ldrb r3, [r4, #0]
|
|
800285c: 742b strb r3, [r5, #16]
|
|
|
|
if (ledIsOn) {
|
|
800285e: 79fb ldrb r3, [r7, #7]
|
|
8002860: 2b00 cmp r3, #0
|
|
8002862: d040 beq.n 80028e6 <SendWebPage+0x1ee>
|
|
strcat((char*) http,
|
|
8002864: 486a ldr r0, [pc, #424] @ (8002a10 <SendWebPage+0x318>)
|
|
8002866: f7fd fd03 bl 8000270 <strlen>
|
|
800286a: 4603 mov r3, r0
|
|
800286c: 461a mov r2, r3
|
|
800286e: 4b68 ldr r3, [pc, #416] @ (8002a10 <SendWebPage+0x318>)
|
|
8002870: 4413 add r3, r2
|
|
8002872: 4a70 ldr r2, [pc, #448] @ (8002a34 <SendWebPage+0x33c>)
|
|
8002874: 4614 mov r4, r2
|
|
8002876: 469c mov ip, r3
|
|
8002878: f104 0e30 add.w lr, r4, #48 @ 0x30
|
|
800287c: 4665 mov r5, ip
|
|
800287e: 4626 mov r6, r4
|
|
8002880: ce0f ldmia r6!, {r0, r1, r2, r3}
|
|
8002882: 6028 str r0, [r5, #0]
|
|
8002884: 6069 str r1, [r5, #4]
|
|
8002886: 60aa str r2, [r5, #8]
|
|
8002888: 60eb str r3, [r5, #12]
|
|
800288a: 3410 adds r4, #16
|
|
800288c: f10c 0c10 add.w ip, ip, #16
|
|
8002890: 4574 cmp r4, lr
|
|
8002892: d1f3 bne.n 800287c <SendWebPage+0x184>
|
|
8002894: 4663 mov r3, ip
|
|
8002896: 4622 mov r2, r4
|
|
8002898: 6810 ldr r0, [r2, #0]
|
|
800289a: 6018 str r0, [r3, #0]
|
|
800289c: 8891 ldrh r1, [r2, #4]
|
|
800289e: 7992 ldrb r2, [r2, #6]
|
|
80028a0: 8099 strh r1, [r3, #4]
|
|
80028a2: 719a strb r2, [r3, #6]
|
|
(char*) "<p><input type=\"radio\" name=\"radio\" value=\"0\" >LED off");
|
|
strcat((char*) http,
|
|
80028a4: 485a ldr r0, [pc, #360] @ (8002a10 <SendWebPage+0x318>)
|
|
80028a6: f7fd fce3 bl 8000270 <strlen>
|
|
80028aa: 4603 mov r3, r0
|
|
80028ac: 461a mov r2, r3
|
|
80028ae: 4b58 ldr r3, [pc, #352] @ (8002a10 <SendWebPage+0x318>)
|
|
80028b0: 4413 add r3, r2
|
|
80028b2: 4a61 ldr r2, [pc, #388] @ (8002a38 <SendWebPage+0x340>)
|
|
80028b4: 4614 mov r4, r2
|
|
80028b6: 469c mov ip, r3
|
|
80028b8: f104 0e30 add.w lr, r4, #48 @ 0x30
|
|
80028bc: 4665 mov r5, ip
|
|
80028be: 4626 mov r6, r4
|
|
80028c0: ce0f ldmia r6!, {r0, r1, r2, r3}
|
|
80028c2: 6028 str r0, [r5, #0]
|
|
80028c4: 6069 str r1, [r5, #4]
|
|
80028c6: 60aa str r2, [r5, #8]
|
|
80028c8: 60eb str r3, [r5, #12]
|
|
80028ca: 3410 adds r4, #16
|
|
80028cc: f10c 0c10 add.w ip, ip, #16
|
|
80028d0: 4574 cmp r4, lr
|
|
80028d2: d1f3 bne.n 80028bc <SendWebPage+0x1c4>
|
|
80028d4: 4665 mov r5, ip
|
|
80028d6: 4623 mov r3, r4
|
|
80028d8: cb07 ldmia r3!, {r0, r1, r2}
|
|
80028da: 6028 str r0, [r5, #0]
|
|
80028dc: 6069 str r1, [r5, #4]
|
|
80028de: 60aa str r2, [r5, #8]
|
|
80028e0: 881b ldrh r3, [r3, #0]
|
|
80028e2: 81ab strh r3, [r5, #12]
|
|
80028e4: e03f b.n 8002966 <SendWebPage+0x26e>
|
|
(char*) "<br><input type=\"radio\" name=\"radio\" value=\"1\" checked>LED on");
|
|
} else {
|
|
strcat((char*) http,
|
|
80028e6: 484a ldr r0, [pc, #296] @ (8002a10 <SendWebPage+0x318>)
|
|
80028e8: f7fd fcc2 bl 8000270 <strlen>
|
|
80028ec: 4603 mov r3, r0
|
|
80028ee: 461a mov r2, r3
|
|
80028f0: 4b47 ldr r3, [pc, #284] @ (8002a10 <SendWebPage+0x318>)
|
|
80028f2: 4413 add r3, r2
|
|
80028f4: 4a51 ldr r2, [pc, #324] @ (8002a3c <SendWebPage+0x344>)
|
|
80028f6: 4614 mov r4, r2
|
|
80028f8: 469c mov ip, r3
|
|
80028fa: f104 0e30 add.w lr, r4, #48 @ 0x30
|
|
80028fe: 4665 mov r5, ip
|
|
8002900: 4626 mov r6, r4
|
|
8002902: ce0f ldmia r6!, {r0, r1, r2, r3}
|
|
8002904: 6028 str r0, [r5, #0]
|
|
8002906: 6069 str r1, [r5, #4]
|
|
8002908: 60aa str r2, [r5, #8]
|
|
800290a: 60eb str r3, [r5, #12]
|
|
800290c: 3410 adds r4, #16
|
|
800290e: f10c 0c10 add.w ip, ip, #16
|
|
8002912: 4574 cmp r4, lr
|
|
8002914: d1f3 bne.n 80028fe <SendWebPage+0x206>
|
|
8002916: 4665 mov r5, ip
|
|
8002918: 4623 mov r3, r4
|
|
800291a: cb07 ldmia r3!, {r0, r1, r2}
|
|
800291c: 6028 str r0, [r5, #0]
|
|
800291e: 6069 str r1, [r5, #4]
|
|
8002920: 60aa str r2, [r5, #8]
|
|
8002922: 881b ldrh r3, [r3, #0]
|
|
8002924: 81ab strh r3, [r5, #12]
|
|
(char*) "<p><input type=\"radio\" name=\"radio\" value=\"0\" checked>LED off");
|
|
strcat((char*) http,
|
|
8002926: 483a ldr r0, [pc, #232] @ (8002a10 <SendWebPage+0x318>)
|
|
8002928: f7fd fca2 bl 8000270 <strlen>
|
|
800292c: 4603 mov r3, r0
|
|
800292e: 461a mov r2, r3
|
|
8002930: 4b37 ldr r3, [pc, #220] @ (8002a10 <SendWebPage+0x318>)
|
|
8002932: 4413 add r3, r2
|
|
8002934: 4a42 ldr r2, [pc, #264] @ (8002a40 <SendWebPage+0x348>)
|
|
8002936: 4614 mov r4, r2
|
|
8002938: 469c mov ip, r3
|
|
800293a: f104 0e30 add.w lr, r4, #48 @ 0x30
|
|
800293e: 4665 mov r5, ip
|
|
8002940: 4626 mov r6, r4
|
|
8002942: ce0f ldmia r6!, {r0, r1, r2, r3}
|
|
8002944: 6028 str r0, [r5, #0]
|
|
8002946: 6069 str r1, [r5, #4]
|
|
8002948: 60aa str r2, [r5, #8]
|
|
800294a: 60eb str r3, [r5, #12]
|
|
800294c: 3410 adds r4, #16
|
|
800294e: f10c 0c10 add.w ip, ip, #16
|
|
8002952: 4574 cmp r4, lr
|
|
8002954: d1f3 bne.n 800293e <SendWebPage+0x246>
|
|
8002956: 4663 mov r3, ip
|
|
8002958: 4622 mov r2, r4
|
|
800295a: 6810 ldr r0, [r2, #0]
|
|
800295c: 6018 str r0, [r3, #0]
|
|
800295e: 8891 ldrh r1, [r2, #4]
|
|
8002960: 7992 ldrb r2, [r2, #6]
|
|
8002962: 8099 strh r1, [r3, #4]
|
|
8002964: 719a strb r2, [r3, #6]
|
|
(char*) "<br><input type=\"radio\" name=\"radio\" value=\"1\" >LED on");
|
|
}
|
|
|
|
strcat((char*) http,
|
|
8002966: 482a ldr r0, [pc, #168] @ (8002a10 <SendWebPage+0x318>)
|
|
8002968: f7fd fc82 bl 8000270 <strlen>
|
|
800296c: 4603 mov r3, r0
|
|
800296e: 461a mov r2, r3
|
|
8002970: 4b27 ldr r3, [pc, #156] @ (8002a10 <SendWebPage+0x318>)
|
|
8002972: 4413 add r3, r2
|
|
8002974: 4a33 ldr r2, [pc, #204] @ (8002a44 <SendWebPage+0x34c>)
|
|
8002976: 4614 mov r4, r2
|
|
8002978: 469c mov ip, r3
|
|
800297a: f104 0e30 add.w lr, r4, #48 @ 0x30
|
|
800297e: 4665 mov r5, ip
|
|
8002980: 4626 mov r6, r4
|
|
8002982: ce0f ldmia r6!, {r0, r1, r2, r3}
|
|
8002984: 6028 str r0, [r5, #0]
|
|
8002986: 6069 str r1, [r5, #4]
|
|
8002988: 60aa str r2, [r5, #8]
|
|
800298a: 60eb str r3, [r5, #12]
|
|
800298c: 3410 adds r4, #16
|
|
800298e: f10c 0c10 add.w ip, ip, #16
|
|
8002992: 4574 cmp r4, lr
|
|
8002994: d1f3 bne.n 800297e <SendWebPage+0x286>
|
|
(char*) "</strong><p><input type=\"submit\"></form></span>");
|
|
strcat((char*) http, (char*) "</body>\r\n</html>\r\n");
|
|
8002996: 481e ldr r0, [pc, #120] @ (8002a10 <SendWebPage+0x318>)
|
|
8002998: f7fd fc6a bl 8000270 <strlen>
|
|
800299c: 4603 mov r3, r0
|
|
800299e: 461a mov r2, r3
|
|
80029a0: 4b1b ldr r3, [pc, #108] @ (8002a10 <SendWebPage+0x318>)
|
|
80029a2: 4413 add r3, r2
|
|
80029a4: 4a28 ldr r2, [pc, #160] @ (8002a48 <SendWebPage+0x350>)
|
|
80029a6: 461d mov r5, r3
|
|
80029a8: 4614 mov r4, r2
|
|
80029aa: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
80029ac: 6028 str r0, [r5, #0]
|
|
80029ae: 6069 str r1, [r5, #4]
|
|
80029b0: 60aa str r2, [r5, #8]
|
|
80029b2: 60eb str r3, [r5, #12]
|
|
80029b4: 8823 ldrh r3, [r4, #0]
|
|
80029b6: 78a2 ldrb r2, [r4, #2]
|
|
80029b8: 822b strh r3, [r5, #16]
|
|
80029ba: 4613 mov r3, r2
|
|
80029bc: 74ab strb r3, [r5, #18]
|
|
|
|
ret = WIFI_SendData(0, (uint8_t*) http, strlen((char*) http),
|
|
80029be: 4814 ldr r0, [pc, #80] @ (8002a10 <SendWebPage+0x318>)
|
|
80029c0: f7fd fc56 bl 8000270 <strlen>
|
|
80029c4: 4603 mov r3, r0
|
|
80029c6: b29a uxth r2, r3
|
|
80029c8: f107 030a add.w r3, r7, #10
|
|
80029cc: f242 7110 movw r1, #10000 @ 0x2710
|
|
80029d0: 9100 str r1, [sp, #0]
|
|
80029d2: 490f ldr r1, [pc, #60] @ (8002a10 <SendWebPage+0x318>)
|
|
80029d4: 2000 movs r0, #0
|
|
80029d6: f009 fbbd bl 800c154 <WIFI_SendData>
|
|
80029da: 4603 mov r3, r0
|
|
80029dc: f887 303f strb.w r3, [r7, #63] @ 0x3f
|
|
&SentDataLength, WIFI_WRITE_TIMEOUT);
|
|
|
|
if ((ret == WIFI_STATUS_OK) && (SentDataLength != strlen((char*) http))) {
|
|
80029e0: f897 303f ldrb.w r3, [r7, #63] @ 0x3f
|
|
80029e4: 2b00 cmp r3, #0
|
|
80029e6: d10a bne.n 80029fe <SendWebPage+0x306>
|
|
80029e8: 897b ldrh r3, [r7, #10]
|
|
80029ea: 461c mov r4, r3
|
|
80029ec: 4808 ldr r0, [pc, #32] @ (8002a10 <SendWebPage+0x318>)
|
|
80029ee: f7fd fc3f bl 8000270 <strlen>
|
|
80029f2: 4603 mov r3, r0
|
|
80029f4: 429c cmp r4, r3
|
|
80029f6: d002 beq.n 80029fe <SendWebPage+0x306>
|
|
ret = WIFI_STATUS_ERROR;
|
|
80029f8: 2301 movs r3, #1
|
|
80029fa: f887 303f strb.w r3, [r7, #63] @ 0x3f
|
|
}
|
|
|
|
return ret;
|
|
80029fe: f897 303f ldrb.w r3, [r7, #63] @ 0x3f
|
|
}
|
|
8002a02: 4618 mov r0, r3
|
|
8002a04: 3744 adds r7, #68 @ 0x44
|
|
8002a06: 46bd mov sp, r7
|
|
8002a08: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr}
|
|
8002a0c: b004 add sp, #16
|
|
8002a0e: 4770 bx lr
|
|
8002a10: 20000360 .word 0x20000360
|
|
8002a14: 08014014 .word 0x08014014
|
|
8002a18: 08014054 .word 0x08014054
|
|
8002a1c: 08014068 .word 0x08014068
|
|
8002a20: 0801408c .word 0x0801408c
|
|
8002a24: 080140cc .word 0x080140cc
|
|
8002a28: 080140dc .word 0x080140dc
|
|
8002a2c: 0801411c .word 0x0801411c
|
|
8002a30: 08014120 .word 0x08014120
|
|
8002a34: 08014134 .word 0x08014134
|
|
8002a38: 0801416c .word 0x0801416c
|
|
8002a3c: 080141ac .word 0x080141ac
|
|
8002a40: 080141ec .word 0x080141ec
|
|
8002a44: 08014224 .word 0x08014224
|
|
8002a48: 08014254 .word 0x08014254
|
|
|
|
08002a4c <EXTI1_IRQHandler>:
|
|
/**
|
|
* @brief This function handles external lines 1interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void EXTI1_IRQHandler(void) {
|
|
8002a4c: b580 push {r7, lr}
|
|
8002a4e: af00 add r7, sp, #0
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
|
8002a50: 2002 movs r0, #2
|
|
8002a52: f001 fec1 bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
portYIELD_FROM_ISR(pdFALSE);
|
|
}
|
|
8002a56: bf00 nop
|
|
8002a58: bd80 pop {r7, pc}
|
|
|
|
08002a5a <HAL_GPIO_EXTI_Callback>:
|
|
/**
|
|
* @brief EXTI line detection callback.
|
|
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
|
|
8002a5a: b580 push {r7, lr}
|
|
8002a5c: b082 sub sp, #8
|
|
8002a5e: af00 add r7, sp, #0
|
|
8002a60: 4603 mov r3, r0
|
|
8002a62: 80fb strh r3, [r7, #6]
|
|
switch (GPIO_Pin) {
|
|
8002a64: 88fb ldrh r3, [r7, #6]
|
|
8002a66: 2b02 cmp r3, #2
|
|
8002a68: d102 bne.n 8002a70 <HAL_GPIO_EXTI_Callback+0x16>
|
|
case (GPIO_PIN_1): {
|
|
SPI_WIFI_ISR();
|
|
8002a6a: f009 fa41 bl 800bef0 <SPI_WIFI_ISR>
|
|
break;
|
|
8002a6e: e000 b.n 8002a72 <HAL_GPIO_EXTI_Callback+0x18>
|
|
}
|
|
default: {
|
|
break;
|
|
8002a70: bf00 nop
|
|
}
|
|
}
|
|
portYIELD_FROM_ISR(pdFALSE);
|
|
}
|
|
8002a72: bf00 nop
|
|
8002a74: 3708 adds r7, #8
|
|
8002a76: 46bd mov sp, r7
|
|
8002a78: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08002a7c <SPI3_IRQHandler>:
|
|
* @brief SPI3 line detection callback.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
extern SPI_HandleTypeDef hspi;
|
|
void SPI3_IRQHandler(void) {
|
|
8002a7c: b580 push {r7, lr}
|
|
8002a7e: af00 add r7, sp, #0
|
|
HAL_SPI_IRQHandler(&hspi);
|
|
8002a80: 4802 ldr r0, [pc, #8] @ (8002a8c <SPI3_IRQHandler+0x10>)
|
|
8002a82: f005 f881 bl 8007b88 <HAL_SPI_IRQHandler>
|
|
portYIELD_FROM_ISR(pdFALSE);
|
|
}
|
|
8002a86: bf00 nop
|
|
8002a88: bd80 pop {r7, pc}
|
|
8002a8a: bf00 nop
|
|
8002a8c: 20001310 .word 0x20001310
|
|
|
|
08002a90 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8002a90: b580 push {r7, lr}
|
|
8002a92: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8002a94: f001 f907 bl 8003ca6 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8002a98: f000 f81a bl 8002ad0 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8002a9c: f000 fa24 bl 8002ee8 <MX_GPIO_Init>
|
|
MX_DFSDM1_Init();
|
|
8002aa0: f000 f8ba bl 8002c18 <MX_DFSDM1_Init>
|
|
MX_I2C2_Init();
|
|
8002aa4: f000 f8f0 bl 8002c88 <MX_I2C2_Init>
|
|
MX_QUADSPI_Init();
|
|
8002aa8: f000 f92c bl 8002d04 <MX_QUADSPI_Init>
|
|
MX_SPI3_Init();
|
|
8002aac: f000 f950 bl 8002d50 <MX_SPI3_Init>
|
|
MX_USART1_UART_Init();
|
|
8002ab0: f000 f98c bl 8002dcc <MX_USART1_UART_Init>
|
|
MX_USART3_UART_Init();
|
|
8002ab4: f000 f9ba bl 8002e2c <MX_USART3_UART_Init>
|
|
MX_USB_OTG_FS_PCD_Init();
|
|
8002ab8: f000 f9e8 bl 8002e8c <MX_USB_OTG_FS_PCD_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
/* USER CODE END 2 */
|
|
|
|
/* Init scheduler */
|
|
osKernelInitialize();
|
|
8002abc: f009 fbd2 bl 800c264 <osKernelInitialize>
|
|
/* creation of defaultTask */
|
|
//defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
|
|
|
|
/* USER CODE BEGIN RTOS_THREADS */
|
|
/* add threads, ... */
|
|
CreateSerialObjects();
|
|
8002ac0: f7ff fb2e bl 8002120 <CreateSerialObjects>
|
|
CreateTasks();
|
|
8002ac4: f7ff fb9c bl 8002200 <CreateTasks>
|
|
/* USER CODE END RTOS_THREADS */
|
|
|
|
/* Start scheduler */
|
|
osKernelStart();
|
|
8002ac8: f009 fbf0 bl 800c2ac <osKernelStart>
|
|
|
|
/* We should never get here as control is now taken by the scheduler */
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
|
|
while (1)
|
|
8002acc: bf00 nop
|
|
8002ace: e7fd b.n 8002acc <main+0x3c>
|
|
|
|
08002ad0 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8002ad0: b580 push {r7, lr}
|
|
8002ad2: b0b8 sub sp, #224 @ 0xe0
|
|
8002ad4: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8002ad6: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002ada: 2244 movs r2, #68 @ 0x44
|
|
8002adc: 2100 movs r1, #0
|
|
8002ade: 4618 mov r0, r3
|
|
8002ae0: f00d fcf2 bl 80104c8 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8002ae4: f107 0388 add.w r3, r7, #136 @ 0x88
|
|
8002ae8: 2200 movs r2, #0
|
|
8002aea: 601a str r2, [r3, #0]
|
|
8002aec: 605a str r2, [r3, #4]
|
|
8002aee: 609a str r2, [r3, #8]
|
|
8002af0: 60da str r2, [r3, #12]
|
|
8002af2: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002af4: 463b mov r3, r7
|
|
8002af6: 2288 movs r2, #136 @ 0x88
|
|
8002af8: 2100 movs r1, #0
|
|
8002afa: 4618 mov r0, r3
|
|
8002afc: f00d fce4 bl 80104c8 <memset>
|
|
|
|
/** Configure LSE Drive Capability
|
|
*/
|
|
HAL_PWR_EnableBkUpAccess();
|
|
8002b00: f002 fe06 bl 8005710 <HAL_PWR_EnableBkUpAccess>
|
|
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
|
|
8002b04: 4b42 ldr r3, [pc, #264] @ (8002c10 <SystemClock_Config+0x140>)
|
|
8002b06: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002b0a: 4a41 ldr r2, [pc, #260] @ (8002c10 <SystemClock_Config+0x140>)
|
|
8002b0c: f023 0318 bic.w r3, r3, #24
|
|
8002b10: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
|
|
8002b14: 2314 movs r3, #20
|
|
8002b16: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
|
8002b1a: 2301 movs r3, #1
|
|
8002b1c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
|
8002b20: 2301 movs r3, #1
|
|
8002b22: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
RCC_OscInitStruct.MSICalibrationValue = 0;
|
|
8002b26: 2300 movs r3, #0
|
|
8002b28: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
|
8002b2c: 2360 movs r3, #96 @ 0x60
|
|
8002b2e: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8002b32: 2302 movs r3, #2
|
|
8002b34: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
|
8002b38: 2301 movs r3, #1
|
|
8002b3a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
RCC_OscInitStruct.PLL.PLLM = 1;
|
|
8002b3e: 2301 movs r3, #1
|
|
8002b40: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
RCC_OscInitStruct.PLL.PLLN = 40;
|
|
8002b44: 2328 movs r3, #40 @ 0x28
|
|
8002b46: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
|
8002b4a: 2307 movs r3, #7
|
|
8002b4c: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
8002b50: 2302 movs r3, #2
|
|
8002b52: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
8002b56: 2302 movs r3, #2
|
|
8002b58: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8002b5c: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002b60: 4618 mov r0, r3
|
|
8002b62: f002 ff15 bl 8005990 <HAL_RCC_OscConfig>
|
|
8002b66: 4603 mov r3, r0
|
|
8002b68: 2b00 cmp r3, #0
|
|
8002b6a: d001 beq.n 8002b70 <SystemClock_Config+0xa0>
|
|
{
|
|
Error_Handler();
|
|
8002b6c: f000 fb80 bl 8003270 <Error_Handler>
|
|
}
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8002b70: 230f movs r3, #15
|
|
8002b72: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8002b76: 2303 movs r3, #3
|
|
8002b78: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8002b7c: 2300 movs r3, #0
|
|
8002b7e: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8002b82: 2300 movs r3, #0
|
|
8002b84: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8002b88: 2300 movs r3, #0
|
|
8002b8a: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
|
8002b8e: f107 0388 add.w r3, r7, #136 @ 0x88
|
|
8002b92: 2104 movs r1, #4
|
|
8002b94: 4618 mov r0, r3
|
|
8002b96: f003 fad7 bl 8006148 <HAL_RCC_ClockConfig>
|
|
8002b9a: 4603 mov r3, r0
|
|
8002b9c: 2b00 cmp r3, #0
|
|
8002b9e: d001 beq.n 8002ba4 <SystemClock_Config+0xd4>
|
|
{
|
|
Error_Handler();
|
|
8002ba0: f000 fb66 bl 8003270 <Error_Handler>
|
|
}
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART3
|
|
8002ba4: 4b1b ldr r3, [pc, #108] @ (8002c14 <SystemClock_Config+0x144>)
|
|
8002ba6: 603b str r3, [r7, #0]
|
|
|RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_DFSDM1
|
|
|RCC_PERIPHCLK_USB;
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|
8002ba8: 2300 movs r3, #0
|
|
8002baa: 63bb str r3, [r7, #56] @ 0x38
|
|
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
|
|
8002bac: 2300 movs r3, #0
|
|
8002bae: 643b str r3, [r7, #64] @ 0x40
|
|
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
|
|
8002bb0: 2300 movs r3, #0
|
|
8002bb2: 657b str r3, [r7, #84] @ 0x54
|
|
PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
|
|
8002bb4: 2300 movs r3, #0
|
|
8002bb6: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
|
8002bba: f04f 6380 mov.w r3, #67108864 @ 0x4000000
|
|
8002bbe: 66fb str r3, [r7, #108] @ 0x6c
|
|
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
|
|
8002bc0: 2301 movs r3, #1
|
|
8002bc2: 607b str r3, [r7, #4]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
|
8002bc4: 2301 movs r3, #1
|
|
8002bc6: 60bb str r3, [r7, #8]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
|
|
8002bc8: 2318 movs r3, #24
|
|
8002bca: 60fb str r3, [r7, #12]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
|
8002bcc: 2307 movs r3, #7
|
|
8002bce: 613b str r3, [r7, #16]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
|
8002bd0: 2302 movs r3, #2
|
|
8002bd2: 617b str r3, [r7, #20]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
|
8002bd4: 2302 movs r3, #2
|
|
8002bd6: 61bb str r3, [r7, #24]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
|
8002bd8: f44f 1380 mov.w r3, #1048576 @ 0x100000
|
|
8002bdc: 61fb str r3, [r7, #28]
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002bde: 463b mov r3, r7
|
|
8002be0: 4618 mov r0, r3
|
|
8002be2: f003 fd07 bl 80065f4 <HAL_RCCEx_PeriphCLKConfig>
|
|
8002be6: 4603 mov r3, r0
|
|
8002be8: 2b00 cmp r3, #0
|
|
8002bea: d001 beq.n 8002bf0 <SystemClock_Config+0x120>
|
|
{
|
|
Error_Handler();
|
|
8002bec: f000 fb40 bl 8003270 <Error_Handler>
|
|
}
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
|
|
8002bf0: f44f 7000 mov.w r0, #512 @ 0x200
|
|
8002bf4: f002 fdaa bl 800574c <HAL_PWREx_ControlVoltageScaling>
|
|
8002bf8: 4603 mov r3, r0
|
|
8002bfa: 2b00 cmp r3, #0
|
|
8002bfc: d001 beq.n 8002c02 <SystemClock_Config+0x132>
|
|
{
|
|
Error_Handler();
|
|
8002bfe: f000 fb37 bl 8003270 <Error_Handler>
|
|
}
|
|
/** Enable MSI Auto calibration
|
|
*/
|
|
HAL_RCCEx_EnableMSIPLLMode();
|
|
8002c02: f003 ffe1 bl 8006bc8 <HAL_RCCEx_EnableMSIPLLMode>
|
|
}
|
|
8002c06: bf00 nop
|
|
8002c08: 37e0 adds r7, #224 @ 0xe0
|
|
8002c0a: 46bd mov sp, r7
|
|
8002c0c: bd80 pop {r7, pc}
|
|
8002c0e: bf00 nop
|
|
8002c10: 40021000 .word 0x40021000
|
|
8002c14: 00012085 .word 0x00012085
|
|
|
|
08002c18 <MX_DFSDM1_Init>:
|
|
* @brief DFSDM1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_DFSDM1_Init(void)
|
|
{
|
|
8002c18: b580 push {r7, lr}
|
|
8002c1a: af00 add r7, sp, #0
|
|
/* USER CODE END DFSDM1_Init 0 */
|
|
|
|
/* USER CODE BEGIN DFSDM1_Init 1 */
|
|
|
|
/* USER CODE END DFSDM1_Init 1 */
|
|
hdfsdm1_channel1.Instance = DFSDM1_Channel1;
|
|
8002c1c: 4b18 ldr r3, [pc, #96] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c1e: 4a19 ldr r2, [pc, #100] @ (8002c84 <MX_DFSDM1_Init+0x6c>)
|
|
8002c20: 601a str r2, [r3, #0]
|
|
hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;
|
|
8002c22: 4b17 ldr r3, [pc, #92] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c24: 2201 movs r2, #1
|
|
8002c26: 711a strb r2, [r3, #4]
|
|
hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;
|
|
8002c28: 4b15 ldr r3, [pc, #84] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c2a: 2200 movs r2, #0
|
|
8002c2c: 609a str r2, [r3, #8]
|
|
hdfsdm1_channel1.Init.OutputClock.Divider = 2;
|
|
8002c2e: 4b14 ldr r3, [pc, #80] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c30: 2202 movs r2, #2
|
|
8002c32: 60da str r2, [r3, #12]
|
|
hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
|
|
8002c34: 4b12 ldr r3, [pc, #72] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c36: 2200 movs r2, #0
|
|
8002c38: 611a str r2, [r3, #16]
|
|
hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
|
|
8002c3a: 4b11 ldr r3, [pc, #68] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c3c: 2200 movs r2, #0
|
|
8002c3e: 615a str r2, [r3, #20]
|
|
hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;
|
|
8002c40: 4b0f ldr r3, [pc, #60] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c42: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8002c46: 619a str r2, [r3, #24]
|
|
hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
|
|
8002c48: 4b0d ldr r3, [pc, #52] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c4a: 2200 movs r2, #0
|
|
8002c4c: 61da str r2, [r3, #28]
|
|
hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
|
|
8002c4e: 4b0c ldr r3, [pc, #48] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c50: 2204 movs r2, #4
|
|
8002c52: 621a str r2, [r3, #32]
|
|
hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
|
|
8002c54: 4b0a ldr r3, [pc, #40] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c56: 2200 movs r2, #0
|
|
8002c58: 625a str r2, [r3, #36] @ 0x24
|
|
hdfsdm1_channel1.Init.Awd.Oversampling = 1;
|
|
8002c5a: 4b09 ldr r3, [pc, #36] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c5c: 2201 movs r2, #1
|
|
8002c5e: 629a str r2, [r3, #40] @ 0x28
|
|
hdfsdm1_channel1.Init.Offset = 0;
|
|
8002c60: 4b07 ldr r3, [pc, #28] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c62: 2200 movs r2, #0
|
|
8002c64: 62da str r2, [r3, #44] @ 0x2c
|
|
hdfsdm1_channel1.Init.RightBitShift = 0x00;
|
|
8002c66: 4b06 ldr r3, [pc, #24] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c68: 2200 movs r2, #0
|
|
8002c6a: 631a str r2, [r3, #48] @ 0x30
|
|
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)
|
|
8002c6c: 4804 ldr r0, [pc, #16] @ (8002c80 <MX_DFSDM1_Init+0x68>)
|
|
8002c6e: f001 f959 bl 8003f24 <HAL_DFSDM_ChannelInit>
|
|
8002c72: 4603 mov r3, r0
|
|
8002c74: 2b00 cmp r3, #0
|
|
8002c76: d001 beq.n 8002c7c <MX_DFSDM1_Init+0x64>
|
|
{
|
|
Error_Handler();
|
|
8002c78: f000 fafa bl 8003270 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN DFSDM1_Init 2 */
|
|
|
|
/* USER CODE END DFSDM1_Init 2 */
|
|
|
|
}
|
|
8002c7c: bf00 nop
|
|
8002c7e: bd80 pop {r7, pc}
|
|
8002c80: 20000b64 .word 0x20000b64
|
|
8002c84: 40016020 .word 0x40016020
|
|
|
|
08002c88 <MX_I2C2_Init>:
|
|
* @brief I2C2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C2_Init(void)
|
|
{
|
|
8002c88: b580 push {r7, lr}
|
|
8002c8a: af00 add r7, sp, #0
|
|
/* USER CODE END I2C2_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C2_Init 1 */
|
|
|
|
/* USER CODE END I2C2_Init 1 */
|
|
hi2c2.Instance = I2C2;
|
|
8002c8c: 4b1b ldr r3, [pc, #108] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002c8e: 4a1c ldr r2, [pc, #112] @ (8002d00 <MX_I2C2_Init+0x78>)
|
|
8002c90: 601a str r2, [r3, #0]
|
|
hi2c2.Init.Timing = 0x00000E14;
|
|
8002c92: 4b1a ldr r3, [pc, #104] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002c94: f640 6214 movw r2, #3604 @ 0xe14
|
|
8002c98: 605a str r2, [r3, #4]
|
|
hi2c2.Init.OwnAddress1 = 0;
|
|
8002c9a: 4b18 ldr r3, [pc, #96] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002c9c: 2200 movs r2, #0
|
|
8002c9e: 609a str r2, [r3, #8]
|
|
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8002ca0: 4b16 ldr r3, [pc, #88] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002ca2: 2201 movs r2, #1
|
|
8002ca4: 60da str r2, [r3, #12]
|
|
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8002ca6: 4b15 ldr r3, [pc, #84] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002ca8: 2200 movs r2, #0
|
|
8002caa: 611a str r2, [r3, #16]
|
|
hi2c2.Init.OwnAddress2 = 0;
|
|
8002cac: 4b13 ldr r3, [pc, #76] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002cae: 2200 movs r2, #0
|
|
8002cb0: 615a str r2, [r3, #20]
|
|
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
8002cb2: 4b12 ldr r3, [pc, #72] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002cb4: 2200 movs r2, #0
|
|
8002cb6: 619a str r2, [r3, #24]
|
|
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8002cb8: 4b10 ldr r3, [pc, #64] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002cba: 2200 movs r2, #0
|
|
8002cbc: 61da str r2, [r3, #28]
|
|
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8002cbe: 4b0f ldr r3, [pc, #60] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002cc0: 2200 movs r2, #0
|
|
8002cc2: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
|
|
8002cc4: 480d ldr r0, [pc, #52] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002cc6: f001 fd9f bl 8004808 <HAL_I2C_Init>
|
|
8002cca: 4603 mov r3, r0
|
|
8002ccc: 2b00 cmp r3, #0
|
|
8002cce: d001 beq.n 8002cd4 <MX_I2C2_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8002cd0: f000 face bl 8003270 <Error_Handler>
|
|
}
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
8002cd4: 2100 movs r1, #0
|
|
8002cd6: 4809 ldr r0, [pc, #36] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002cd8: f002 fb50 bl 800537c <HAL_I2CEx_ConfigAnalogFilter>
|
|
8002cdc: 4603 mov r3, r0
|
|
8002cde: 2b00 cmp r3, #0
|
|
8002ce0: d001 beq.n 8002ce6 <MX_I2C2_Init+0x5e>
|
|
{
|
|
Error_Handler();
|
|
8002ce2: f000 fac5 bl 8003270 <Error_Handler>
|
|
}
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
|
|
8002ce6: 2100 movs r1, #0
|
|
8002ce8: 4804 ldr r0, [pc, #16] @ (8002cfc <MX_I2C2_Init+0x74>)
|
|
8002cea: f002 fb92 bl 8005412 <HAL_I2CEx_ConfigDigitalFilter>
|
|
8002cee: 4603 mov r3, r0
|
|
8002cf0: 2b00 cmp r3, #0
|
|
8002cf2: d001 beq.n 8002cf8 <MX_I2C2_Init+0x70>
|
|
{
|
|
Error_Handler();
|
|
8002cf4: f000 fabc bl 8003270 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C2_Init 2 */
|
|
|
|
/* USER CODE END I2C2_Init 2 */
|
|
|
|
}
|
|
8002cf8: bf00 nop
|
|
8002cfa: bd80 pop {r7, pc}
|
|
8002cfc: 20000b9c .word 0x20000b9c
|
|
8002d00: 40005800 .word 0x40005800
|
|
|
|
08002d04 <MX_QUADSPI_Init>:
|
|
* @brief QUADSPI Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_QUADSPI_Init(void)
|
|
{
|
|
8002d04: b580 push {r7, lr}
|
|
8002d06: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN QUADSPI_Init 1 */
|
|
|
|
/* USER CODE END QUADSPI_Init 1 */
|
|
/* QUADSPI parameter configuration*/
|
|
hqspi.Instance = QUADSPI;
|
|
8002d08: 4b0f ldr r3, [pc, #60] @ (8002d48 <MX_QUADSPI_Init+0x44>)
|
|
8002d0a: 4a10 ldr r2, [pc, #64] @ (8002d4c <MX_QUADSPI_Init+0x48>)
|
|
8002d0c: 601a str r2, [r3, #0]
|
|
hqspi.Init.ClockPrescaler = 255;
|
|
8002d0e: 4b0e ldr r3, [pc, #56] @ (8002d48 <MX_QUADSPI_Init+0x44>)
|
|
8002d10: 22ff movs r2, #255 @ 0xff
|
|
8002d12: 605a str r2, [r3, #4]
|
|
hqspi.Init.FifoThreshold = 1;
|
|
8002d14: 4b0c ldr r3, [pc, #48] @ (8002d48 <MX_QUADSPI_Init+0x44>)
|
|
8002d16: 2201 movs r2, #1
|
|
8002d18: 609a str r2, [r3, #8]
|
|
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE;
|
|
8002d1a: 4b0b ldr r3, [pc, #44] @ (8002d48 <MX_QUADSPI_Init+0x44>)
|
|
8002d1c: 2200 movs r2, #0
|
|
8002d1e: 60da str r2, [r3, #12]
|
|
hqspi.Init.FlashSize = 1;
|
|
8002d20: 4b09 ldr r3, [pc, #36] @ (8002d48 <MX_QUADSPI_Init+0x44>)
|
|
8002d22: 2201 movs r2, #1
|
|
8002d24: 611a str r2, [r3, #16]
|
|
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
|
|
8002d26: 4b08 ldr r3, [pc, #32] @ (8002d48 <MX_QUADSPI_Init+0x44>)
|
|
8002d28: 2200 movs r2, #0
|
|
8002d2a: 615a str r2, [r3, #20]
|
|
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
|
|
8002d2c: 4b06 ldr r3, [pc, #24] @ (8002d48 <MX_QUADSPI_Init+0x44>)
|
|
8002d2e: 2200 movs r2, #0
|
|
8002d30: 619a str r2, [r3, #24]
|
|
if (HAL_QSPI_Init(&hqspi) != HAL_OK)
|
|
8002d32: 4805 ldr r0, [pc, #20] @ (8002d48 <MX_QUADSPI_Init+0x44>)
|
|
8002d34: f002 fd70 bl 8005818 <HAL_QSPI_Init>
|
|
8002d38: 4603 mov r3, r0
|
|
8002d3a: 2b00 cmp r3, #0
|
|
8002d3c: d001 beq.n 8002d42 <MX_QUADSPI_Init+0x3e>
|
|
{
|
|
Error_Handler();
|
|
8002d3e: f000 fa97 bl 8003270 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN QUADSPI_Init 2 */
|
|
|
|
/* USER CODE END QUADSPI_Init 2 */
|
|
|
|
}
|
|
8002d42: bf00 nop
|
|
8002d44: bd80 pop {r7, pc}
|
|
8002d46: bf00 nop
|
|
8002d48: 20000bf0 .word 0x20000bf0
|
|
8002d4c: a0001000 .word 0xa0001000
|
|
|
|
08002d50 <MX_SPI3_Init>:
|
|
* @brief SPI3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_SPI3_Init(void)
|
|
{
|
|
8002d50: b580 push {r7, lr}
|
|
8002d52: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN SPI3_Init 1 */
|
|
|
|
/* USER CODE END SPI3_Init 1 */
|
|
/* SPI3 parameter configuration*/
|
|
hspi3.Instance = SPI3;
|
|
8002d54: 4b1b ldr r3, [pc, #108] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d56: 4a1c ldr r2, [pc, #112] @ (8002dc8 <MX_SPI3_Init+0x78>)
|
|
8002d58: 601a str r2, [r3, #0]
|
|
hspi3.Init.Mode = SPI_MODE_MASTER;
|
|
8002d5a: 4b1a ldr r3, [pc, #104] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d5c: f44f 7282 mov.w r2, #260 @ 0x104
|
|
8002d60: 605a str r2, [r3, #4]
|
|
hspi3.Init.Direction = SPI_DIRECTION_2LINES;
|
|
8002d62: 4b18 ldr r3, [pc, #96] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d64: 2200 movs r2, #0
|
|
8002d66: 609a str r2, [r3, #8]
|
|
hspi3.Init.DataSize = SPI_DATASIZE_4BIT;
|
|
8002d68: 4b16 ldr r3, [pc, #88] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d6a: f44f 7240 mov.w r2, #768 @ 0x300
|
|
8002d6e: 60da str r2, [r3, #12]
|
|
hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
8002d70: 4b14 ldr r3, [pc, #80] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d72: 2200 movs r2, #0
|
|
8002d74: 611a str r2, [r3, #16]
|
|
hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8002d76: 4b13 ldr r3, [pc, #76] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d78: 2200 movs r2, #0
|
|
8002d7a: 615a str r2, [r3, #20]
|
|
hspi3.Init.NSS = SPI_NSS_SOFT;
|
|
8002d7c: 4b11 ldr r3, [pc, #68] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d7e: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8002d82: 619a str r2, [r3, #24]
|
|
hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
8002d84: 4b0f ldr r3, [pc, #60] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d86: 2200 movs r2, #0
|
|
8002d88: 61da str r2, [r3, #28]
|
|
hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
8002d8a: 4b0e ldr r3, [pc, #56] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d8c: 2200 movs r2, #0
|
|
8002d8e: 621a str r2, [r3, #32]
|
|
hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
8002d90: 4b0c ldr r3, [pc, #48] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d92: 2200 movs r2, #0
|
|
8002d94: 625a str r2, [r3, #36] @ 0x24
|
|
hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8002d96: 4b0b ldr r3, [pc, #44] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d98: 2200 movs r2, #0
|
|
8002d9a: 629a str r2, [r3, #40] @ 0x28
|
|
hspi3.Init.CRCPolynomial = 7;
|
|
8002d9c: 4b09 ldr r3, [pc, #36] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002d9e: 2207 movs r2, #7
|
|
8002da0: 62da str r2, [r3, #44] @ 0x2c
|
|
hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
|
|
8002da2: 4b08 ldr r3, [pc, #32] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002da4: 2200 movs r2, #0
|
|
8002da6: 631a str r2, [r3, #48] @ 0x30
|
|
hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
|
8002da8: 4b06 ldr r3, [pc, #24] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002daa: 2208 movs r2, #8
|
|
8002dac: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_SPI_Init(&hspi3) != HAL_OK)
|
|
8002dae: 4805 ldr r0, [pc, #20] @ (8002dc4 <MX_SPI3_Init+0x74>)
|
|
8002db0: f004 f8ec bl 8006f8c <HAL_SPI_Init>
|
|
8002db4: 4603 mov r3, r0
|
|
8002db6: 2b00 cmp r3, #0
|
|
8002db8: d001 beq.n 8002dbe <MX_SPI3_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
8002dba: f000 fa59 bl 8003270 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SPI3_Init 2 */
|
|
|
|
/* USER CODE END SPI3_Init 2 */
|
|
|
|
}
|
|
8002dbe: bf00 nop
|
|
8002dc0: bd80 pop {r7, pc}
|
|
8002dc2: bf00 nop
|
|
8002dc4: 20000c34 .word 0x20000c34
|
|
8002dc8: 40003c00 .word 0x40003c00
|
|
|
|
08002dcc <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
8002dcc: b580 push {r7, lr}
|
|
8002dce: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8002dd0: 4b14 ldr r3, [pc, #80] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002dd2: 4a15 ldr r2, [pc, #84] @ (8002e28 <MX_USART1_UART_Init+0x5c>)
|
|
8002dd4: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8002dd6: 4b13 ldr r3, [pc, #76] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002dd8: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8002ddc: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8002dde: 4b11 ldr r3, [pc, #68] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002de0: 2200 movs r2, #0
|
|
8002de2: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8002de4: 4b0f ldr r3, [pc, #60] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002de6: 2200 movs r2, #0
|
|
8002de8: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8002dea: 4b0e ldr r3, [pc, #56] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002dec: 2200 movs r2, #0
|
|
8002dee: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8002df0: 4b0c ldr r3, [pc, #48] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002df2: 220c movs r2, #12
|
|
8002df4: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8002df6: 4b0b ldr r3, [pc, #44] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002df8: 2200 movs r2, #0
|
|
8002dfa: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8002dfc: 4b09 ldr r3, [pc, #36] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002dfe: 2200 movs r2, #0
|
|
8002e00: 61da str r2, [r3, #28]
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8002e02: 4b08 ldr r3, [pc, #32] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002e04: 2200 movs r2, #0
|
|
8002e06: 621a str r2, [r3, #32]
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8002e08: 4b06 ldr r3, [pc, #24] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002e0a: 2200 movs r2, #0
|
|
8002e0c: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8002e0e: 4805 ldr r0, [pc, #20] @ (8002e24 <MX_USART1_UART_Init+0x58>)
|
|
8002e10: f005 feb4 bl 8008b7c <HAL_UART_Init>
|
|
8002e14: 4603 mov r3, r0
|
|
8002e16: 2b00 cmp r3, #0
|
|
8002e18: d001 beq.n 8002e1e <MX_USART1_UART_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
8002e1a: f000 fa29 bl 8003270 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
8002e1e: bf00 nop
|
|
8002e20: bd80 pop {r7, pc}
|
|
8002e22: bf00 nop
|
|
8002e24: 20000c98 .word 0x20000c98
|
|
8002e28: 40013800 .word 0x40013800
|
|
|
|
08002e2c <MX_USART3_UART_Init>:
|
|
* @brief USART3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART3_UART_Init(void)
|
|
{
|
|
8002e2c: b580 push {r7, lr}
|
|
8002e2e: af00 add r7, sp, #0
|
|
/* USER CODE END USART3_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART3_Init 1 */
|
|
|
|
/* USER CODE END USART3_Init 1 */
|
|
huart3.Instance = USART3;
|
|
8002e30: 4b14 ldr r3, [pc, #80] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e32: 4a15 ldr r2, [pc, #84] @ (8002e88 <MX_USART3_UART_Init+0x5c>)
|
|
8002e34: 601a str r2, [r3, #0]
|
|
huart3.Init.BaudRate = 115200;
|
|
8002e36: 4b13 ldr r3, [pc, #76] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e38: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8002e3c: 605a str r2, [r3, #4]
|
|
huart3.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8002e3e: 4b11 ldr r3, [pc, #68] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e40: 2200 movs r2, #0
|
|
8002e42: 609a str r2, [r3, #8]
|
|
huart3.Init.StopBits = UART_STOPBITS_1;
|
|
8002e44: 4b0f ldr r3, [pc, #60] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e46: 2200 movs r2, #0
|
|
8002e48: 60da str r2, [r3, #12]
|
|
huart3.Init.Parity = UART_PARITY_NONE;
|
|
8002e4a: 4b0e ldr r3, [pc, #56] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e4c: 2200 movs r2, #0
|
|
8002e4e: 611a str r2, [r3, #16]
|
|
huart3.Init.Mode = UART_MODE_TX_RX;
|
|
8002e50: 4b0c ldr r3, [pc, #48] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e52: 220c movs r2, #12
|
|
8002e54: 615a str r2, [r3, #20]
|
|
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8002e56: 4b0b ldr r3, [pc, #44] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e58: 2200 movs r2, #0
|
|
8002e5a: 619a str r2, [r3, #24]
|
|
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8002e5c: 4b09 ldr r3, [pc, #36] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e5e: 2200 movs r2, #0
|
|
8002e60: 61da str r2, [r3, #28]
|
|
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8002e62: 4b08 ldr r3, [pc, #32] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e64: 2200 movs r2, #0
|
|
8002e66: 621a str r2, [r3, #32]
|
|
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8002e68: 4b06 ldr r3, [pc, #24] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e6a: 2200 movs r2, #0
|
|
8002e6c: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_UART_Init(&huart3) != HAL_OK)
|
|
8002e6e: 4805 ldr r0, [pc, #20] @ (8002e84 <MX_USART3_UART_Init+0x58>)
|
|
8002e70: f005 fe84 bl 8008b7c <HAL_UART_Init>
|
|
8002e74: 4603 mov r3, r0
|
|
8002e76: 2b00 cmp r3, #0
|
|
8002e78: d001 beq.n 8002e7e <MX_USART3_UART_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
8002e7a: f000 f9f9 bl 8003270 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART3_Init 2 */
|
|
|
|
/* USER CODE END USART3_Init 2 */
|
|
|
|
}
|
|
8002e7e: bf00 nop
|
|
8002e80: bd80 pop {r7, pc}
|
|
8002e82: bf00 nop
|
|
8002e84: 20000d20 .word 0x20000d20
|
|
8002e88: 40004800 .word 0x40004800
|
|
|
|
08002e8c <MX_USB_OTG_FS_PCD_Init>:
|
|
* @brief USB_OTG_FS Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USB_OTG_FS_PCD_Init(void)
|
|
{
|
|
8002e8c: b580 push {r7, lr}
|
|
8002e8e: af00 add r7, sp, #0
|
|
/* USER CODE END USB_OTG_FS_Init 0 */
|
|
|
|
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
|
|
|
|
/* USER CODE END USB_OTG_FS_Init 1 */
|
|
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
|
8002e90: 4b14 ldr r3, [pc, #80] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002e92: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
8002e96: 601a str r2, [r3, #0]
|
|
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
|
|
8002e98: 4b12 ldr r3, [pc, #72] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002e9a: 2206 movs r2, #6
|
|
8002e9c: 711a strb r2, [r3, #4]
|
|
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
|
|
8002e9e: 4b11 ldr r3, [pc, #68] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002ea0: 2202 movs r2, #2
|
|
8002ea2: 71da strb r2, [r3, #7]
|
|
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
|
8002ea4: 4b0f ldr r3, [pc, #60] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002ea6: 2202 movs r2, #2
|
|
8002ea8: 725a strb r2, [r3, #9]
|
|
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
|
|
8002eaa: 4b0e ldr r3, [pc, #56] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002eac: 2200 movs r2, #0
|
|
8002eae: 729a strb r2, [r3, #10]
|
|
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
|
8002eb0: 4b0c ldr r3, [pc, #48] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002eb2: 2200 movs r2, #0
|
|
8002eb4: 72da strb r2, [r3, #11]
|
|
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
|
8002eb6: 4b0b ldr r3, [pc, #44] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002eb8: 2200 movs r2, #0
|
|
8002eba: 731a strb r2, [r3, #12]
|
|
hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
|
|
8002ebc: 4b09 ldr r3, [pc, #36] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002ebe: 2200 movs r2, #0
|
|
8002ec0: 735a strb r2, [r3, #13]
|
|
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
|
8002ec2: 4b08 ldr r3, [pc, #32] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002ec4: 2200 movs r2, #0
|
|
8002ec6: 73da strb r2, [r3, #15]
|
|
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
|
8002ec8: 4b06 ldr r3, [pc, #24] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002eca: 2200 movs r2, #0
|
|
8002ecc: 739a strb r2, [r3, #14]
|
|
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
|
|
8002ece: 4805 ldr r0, [pc, #20] @ (8002ee4 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002ed0: f002 faeb bl 80054aa <HAL_PCD_Init>
|
|
8002ed4: 4603 mov r3, r0
|
|
8002ed6: 2b00 cmp r3, #0
|
|
8002ed8: d001 beq.n 8002ede <MX_USB_OTG_FS_PCD_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
8002eda: f000 f9c9 bl 8003270 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
|
|
|
|
/* USER CODE END USB_OTG_FS_Init 2 */
|
|
|
|
}
|
|
8002ede: bf00 nop
|
|
8002ee0: bd80 pop {r7, pc}
|
|
8002ee2: bf00 nop
|
|
8002ee4: 20000da8 .word 0x20000da8
|
|
|
|
08002ee8 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8002ee8: b580 push {r7, lr}
|
|
8002eea: b08a sub sp, #40 @ 0x28
|
|
8002eec: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002eee: f107 0314 add.w r3, r7, #20
|
|
8002ef2: 2200 movs r2, #0
|
|
8002ef4: 601a str r2, [r3, #0]
|
|
8002ef6: 605a str r2, [r3, #4]
|
|
8002ef8: 609a str r2, [r3, #8]
|
|
8002efa: 60da str r2, [r3, #12]
|
|
8002efc: 611a str r2, [r3, #16]
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8002efe: 4bbd ldr r3, [pc, #756] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f00: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f02: 4abc ldr r2, [pc, #752] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f04: f043 0310 orr.w r3, r3, #16
|
|
8002f08: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002f0a: 4bba ldr r3, [pc, #744] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f0c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f0e: f003 0310 and.w r3, r3, #16
|
|
8002f12: 613b str r3, [r7, #16]
|
|
8002f14: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8002f16: 4bb7 ldr r3, [pc, #732] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f18: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f1a: 4ab6 ldr r2, [pc, #728] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f1c: f043 0304 orr.w r3, r3, #4
|
|
8002f20: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002f22: 4bb4 ldr r3, [pc, #720] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f24: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f26: f003 0304 and.w r3, r3, #4
|
|
8002f2a: 60fb str r3, [r7, #12]
|
|
8002f2c: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002f2e: 4bb1 ldr r3, [pc, #708] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f30: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f32: 4ab0 ldr r2, [pc, #704] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f34: f043 0301 orr.w r3, r3, #1
|
|
8002f38: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002f3a: 4bae ldr r3, [pc, #696] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f3c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f3e: f003 0301 and.w r3, r3, #1
|
|
8002f42: 60bb str r3, [r7, #8]
|
|
8002f44: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8002f46: 4bab ldr r3, [pc, #684] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f48: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f4a: 4aaa ldr r2, [pc, #680] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f4c: f043 0302 orr.w r3, r3, #2
|
|
8002f50: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002f52: 4ba8 ldr r3, [pc, #672] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f54: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f56: f003 0302 and.w r3, r3, #2
|
|
8002f5a: 607b str r3, [r7, #4]
|
|
8002f5c: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8002f5e: 4ba5 ldr r3, [pc, #660] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f60: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f62: 4aa4 ldr r2, [pc, #656] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f64: f043 0308 orr.w r3, r3, #8
|
|
8002f68: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002f6a: 4ba2 ldr r3, [pc, #648] @ (80031f4 <MX_GPIO_Init+0x30c>)
|
|
8002f6c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002f6e: f003 0308 and.w r3, r3, #8
|
|
8002f72: 603b str r3, [r7, #0]
|
|
8002f74: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET);
|
|
8002f76: 2200 movs r2, #0
|
|
8002f78: f44f 718a mov.w r1, #276 @ 0x114
|
|
8002f7c: 489e ldr r0, [pc, #632] @ (80031f8 <MX_GPIO_Init+0x310>)
|
|
8002f7e: f001 fc13 bl 80047a8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET);
|
|
8002f82: 2200 movs r2, #0
|
|
8002f84: f248 1104 movw r1, #33028 @ 0x8104
|
|
8002f88: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8002f8c: f001 fc0c bl 80047a8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
|
|
8002f90: 2200 movs r2, #0
|
|
8002f92: f24f 0114 movw r1, #61460 @ 0xf014
|
|
8002f96: 4899 ldr r0, [pc, #612] @ (80031fc <MX_GPIO_Init+0x314>)
|
|
8002f98: f001 fc06 bl 80047a8 <HAL_GPIO_WritePin>
|
|
|SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET);
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET);
|
|
8002f9c: 2200 movs r2, #0
|
|
8002f9e: f241 0181 movw r1, #4225 @ 0x1081
|
|
8002fa2: 4897 ldr r0, [pc, #604] @ (8003200 <MX_GPIO_Init+0x318>)
|
|
8002fa4: f001 fc00 bl 80047a8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET);
|
|
8002fa8: 2201 movs r2, #1
|
|
8002faa: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
8002fae: 4894 ldr r0, [pc, #592] @ (8003200 <MX_GPIO_Init+0x318>)
|
|
8002fb0: f001 fbfa bl 80047a8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET);
|
|
8002fb4: 2200 movs r2, #0
|
|
8002fb6: f44f 7110 mov.w r1, #576 @ 0x240
|
|
8002fba: 4892 ldr r0, [pc, #584] @ (8003204 <MX_GPIO_Init+0x31c>)
|
|
8002fbc: f001 fbf4 bl 80047a8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET);
|
|
8002fc0: 2201 movs r2, #1
|
|
8002fc2: 2120 movs r1, #32
|
|
8002fc4: 488d ldr r0, [pc, #564] @ (80031fc <MX_GPIO_Init+0x314>)
|
|
8002fc6: f001 fbef bl 80047a8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET);
|
|
8002fca: 2201 movs r2, #1
|
|
8002fcc: 2101 movs r1, #1
|
|
8002fce: 488a ldr r0, [pc, #552] @ (80031f8 <MX_GPIO_Init+0x310>)
|
|
8002fd0: f001 fbea bl 80047a8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */
|
|
GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin;
|
|
8002fd4: f240 1315 movw r3, #277 @ 0x115
|
|
8002fd8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8002fda: 2301 movs r3, #1
|
|
8002fdc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002fde: 2300 movs r3, #0
|
|
8002fe0: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8002fe2: 2300 movs r3, #0
|
|
8002fe4: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8002fe6: f107 0314 add.w r3, r7, #20
|
|
8002fea: 4619 mov r1, r3
|
|
8002fec: 4882 ldr r0, [pc, #520] @ (80031f8 <MX_GPIO_Init+0x310>)
|
|
8002fee: f001 f925 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */
|
|
GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin;
|
|
8002ff2: 236a movs r3, #106 @ 0x6a
|
|
8002ff4: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
8002ff6: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
8002ffa: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002ffc: 2300 movs r3, #0
|
|
8002ffe: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8003000: f107 0314 add.w r3, r7, #20
|
|
8003004: 4619 mov r1, r3
|
|
8003006: 487c ldr r0, [pc, #496] @ (80031f8 <MX_GPIO_Init+0x310>)
|
|
8003008: f001 f918 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : BUTTON_EXTI13_Pin */
|
|
GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin;
|
|
800300c: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8003010: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
8003012: f44f 1304 mov.w r3, #2162688 @ 0x210000
|
|
8003016: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003018: 2300 movs r3, #0
|
|
800301a: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct);
|
|
800301c: f107 0314 add.w r3, r7, #20
|
|
8003020: 4619 mov r1, r3
|
|
8003022: 4878 ldr r0, [pc, #480] @ (8003204 <MX_GPIO_Init+0x31c>)
|
|
8003024: f001 f90a bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin
|
|
ARD_A1_Pin ARD_A0_Pin */
|
|
GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin
|
|
8003028: 233f movs r3, #63 @ 0x3f
|
|
800302a: 617b str r3, [r7, #20]
|
|
|ARD_A1_Pin|ARD_A0_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
|
|
800302c: 230b movs r3, #11
|
|
800302e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003030: 2300 movs r3, #0
|
|
8003032: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8003034: f107 0314 add.w r3, r7, #20
|
|
8003038: 4619 mov r1, r3
|
|
800303a: 4872 ldr r0, [pc, #456] @ (8003204 <MX_GPIO_Init+0x31c>)
|
|
800303c: f001 f8fe bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin;
|
|
8003040: 2303 movs r3, #3
|
|
8003042: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8003044: 2302 movs r3, #2
|
|
8003046: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003048: 2300 movs r3, #0
|
|
800304a: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800304c: 2303 movs r3, #3
|
|
800304e: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
|
|
8003050: 2308 movs r3, #8
|
|
8003052: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8003054: f107 0314 add.w r3, r7, #20
|
|
8003058: 4619 mov r1, r3
|
|
800305a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800305e: f001 f8ed bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D10_Pin SPBTLE_RF_RST_Pin ARD_D9_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin;
|
|
8003062: f248 1304 movw r3, #33028 @ 0x8104
|
|
8003066: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8003068: 2301 movs r3, #1
|
|
800306a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800306c: 2300 movs r3, #0
|
|
800306e: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8003070: 2300 movs r3, #0
|
|
8003072: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8003074: f107 0314 add.w r3, r7, #20
|
|
8003078: 4619 mov r1, r3
|
|
800307a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800307e: f001 f8dd bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ARD_D4_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D4_Pin;
|
|
8003082: 2308 movs r3, #8
|
|
8003084: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8003086: 2302 movs r3, #2
|
|
8003088: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800308a: 2300 movs r3, #0
|
|
800308c: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800308e: 2300 movs r3, #0
|
|
8003090: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
8003092: 2301 movs r3, #1
|
|
8003094: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct);
|
|
8003096: f107 0314 add.w r3, r7, #20
|
|
800309a: 4619 mov r1, r3
|
|
800309c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80030a0: f001 f8cc bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ARD_D7_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D7_Pin;
|
|
80030a4: 2310 movs r3, #16
|
|
80030a6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
|
|
80030a8: 230b movs r3, #11
|
|
80030aa: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80030ac: 2300 movs r3, #0
|
|
80030ae: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct);
|
|
80030b0: f107 0314 add.w r3, r7, #20
|
|
80030b4: 4619 mov r1, r3
|
|
80030b6: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80030ba: f001 f8bf bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D13_Pin ARD_D12_Pin ARD_D11_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D13_Pin|ARD_D12_Pin|ARD_D11_Pin;
|
|
80030be: 23e0 movs r3, #224 @ 0xe0
|
|
80030c0: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80030c2: 2302 movs r3, #2
|
|
80030c4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80030c6: 2300 movs r3, #0
|
|
80030c8: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80030ca: 2303 movs r3, #3
|
|
80030cc: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
|
|
80030ce: 2305 movs r3, #5
|
|
80030d0: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80030d2: f107 0314 add.w r3, r7, #20
|
|
80030d6: 4619 mov r1, r3
|
|
80030d8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80030dc: f001 f8ae bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ARD_D3_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D3_Pin;
|
|
80030e0: 2301 movs r3, #1
|
|
80030e2: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
80030e4: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
80030e8: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80030ea: 2300 movs r3, #0
|
|
80030ec: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct);
|
|
80030ee: f107 0314 add.w r3, r7, #20
|
|
80030f2: 4619 mov r1, r3
|
|
80030f4: 4841 ldr r0, [pc, #260] @ (80031fc <MX_GPIO_Init+0x314>)
|
|
80030f6: f001 f8a1 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ARD_D6_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D6_Pin;
|
|
80030fa: 2302 movs r3, #2
|
|
80030fc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
|
|
80030fe: 230b movs r3, #11
|
|
8003100: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003102: 2300 movs r3, #0
|
|
8003104: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct);
|
|
8003106: f107 0314 add.w r3, r7, #20
|
|
800310a: 4619 mov r1, r3
|
|
800310c: 483b ldr r0, [pc, #236] @ (80031fc <MX_GPIO_Init+0x314>)
|
|
800310e: f001 f895 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin
|
|
SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
|
|
8003112: f24f 0334 movw r3, #61492 @ 0xf034
|
|
8003116: 617b str r3, [r7, #20]
|
|
|SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8003118: 2301 movs r3, #1
|
|
800311a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800311c: 2300 movs r3, #0
|
|
800311e: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8003120: 2300 movs r3, #0
|
|
8003122: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8003124: f107 0314 add.w r3, r7, #20
|
|
8003128: 4619 mov r1, r3
|
|
800312a: 4834 ldr r0, [pc, #208] @ (80031fc <MX_GPIO_Init+0x314>)
|
|
800312c: f001 f886 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin
|
|
PMOD_IRQ_EXTI12_Pin */
|
|
GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin
|
|
8003130: f64c 4304 movw r3, #52228 @ 0xcc04
|
|
8003134: 617b str r3, [r7, #20]
|
|
|PMOD_IRQ_EXTI12_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
8003136: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
800313a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800313c: 2300 movs r3, #0
|
|
800313e: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8003140: f107 0314 add.w r3, r7, #20
|
|
8003144: 4619 mov r1, r3
|
|
8003146: 482e ldr r0, [pc, #184] @ (8003200 <MX_GPIO_Init+0x318>)
|
|
8003148: f001 f878 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */
|
|
GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin;
|
|
800314c: f243 0381 movw r3, #12417 @ 0x3081
|
|
8003150: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8003152: 2301 movs r3, #1
|
|
8003154: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003156: 2300 movs r3, #0
|
|
8003158: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800315a: 2300 movs r3, #0
|
|
800315c: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
800315e: f107 0314 add.w r3, r7, #20
|
|
8003162: 4619 mov r1, r3
|
|
8003164: 4826 ldr r0, [pc, #152] @ (8003200 <MX_GPIO_Init+0x318>)
|
|
8003166: f001 f869 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */
|
|
GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin;
|
|
800316a: f44f 7310 mov.w r3, #576 @ 0x240
|
|
800316e: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8003170: 2301 movs r3, #1
|
|
8003172: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003174: 2300 movs r3, #0
|
|
8003176: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8003178: 2300 movs r3, #0
|
|
800317a: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
800317c: f107 0314 add.w r3, r7, #20
|
|
8003180: 4619 mov r1, r3
|
|
8003182: 4820 ldr r0, [pc, #128] @ (8003204 <MX_GPIO_Init+0x31c>)
|
|
8003184: f001 f85a bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */
|
|
GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin;
|
|
8003188: f44f 73c0 mov.w r3, #384 @ 0x180
|
|
800318c: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
800318e: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
8003192: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003194: 2300 movs r3, #0
|
|
8003196: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8003198: f107 0314 add.w r3, r7, #20
|
|
800319c: 4619 mov r1, r3
|
|
800319e: 4819 ldr r0, [pc, #100] @ (8003204 <MX_GPIO_Init+0x31c>)
|
|
80031a0: f001 f84c bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PMOD_SPI2_SCK_Pin */
|
|
GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin;
|
|
80031a4: 2302 movs r3, #2
|
|
80031a6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80031a8: 2302 movs r3, #2
|
|
80031aa: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80031ac: 2300 movs r3, #0
|
|
80031ae: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80031b0: 2303 movs r3, #3
|
|
80031b2: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
80031b4: 2305 movs r3, #5
|
|
80031b6: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct);
|
|
80031b8: f107 0314 add.w r3, r7, #20
|
|
80031bc: 4619 mov r1, r3
|
|
80031be: 4810 ldr r0, [pc, #64] @ (8003200 <MX_GPIO_Init+0x318>)
|
|
80031c0: f001 f83c bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */
|
|
GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin;
|
|
80031c4: 2378 movs r3, #120 @ 0x78
|
|
80031c6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80031c8: 2302 movs r3, #2
|
|
80031ca: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80031cc: 2300 movs r3, #0
|
|
80031ce: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80031d0: 2303 movs r3, #3
|
|
80031d2: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
80031d4: 2307 movs r3, #7
|
|
80031d6: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
80031d8: f107 0314 add.w r3, r7, #20
|
|
80031dc: 4619 mov r1, r3
|
|
80031de: 4808 ldr r0, [pc, #32] @ (8003200 <MX_GPIO_Init+0x318>)
|
|
80031e0: f001 f82c bl 800423c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin;
|
|
80031e4: f44f 7340 mov.w r3, #768 @ 0x300
|
|
80031e8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
80031ea: 2312 movs r3, #18
|
|
80031ec: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
80031ee: 2301 movs r3, #1
|
|
80031f0: e00a b.n 8003208 <MX_GPIO_Init+0x320>
|
|
80031f2: bf00 nop
|
|
80031f4: 40021000 .word 0x40021000
|
|
80031f8: 48001000 .word 0x48001000
|
|
80031fc: 48000400 .word 0x48000400
|
|
8003200: 48000c00 .word 0x48000c00
|
|
8003204: 48000800 .word 0x48000800
|
|
8003208: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800320a: 2303 movs r3, #3
|
|
800320c: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
800320e: 2304 movs r3, #4
|
|
8003210: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8003212: f107 0314 add.w r3, r7, #20
|
|
8003216: 4619 mov r1, r3
|
|
8003218: 480b ldr r0, [pc, #44] @ (8003248 <MX_GPIO_Init+0x360>)
|
|
800321a: f001 f80f bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* EXTI interrupt init*/
|
|
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
|
|
800321e: 2200 movs r2, #0
|
|
8003220: 2105 movs r1, #5
|
|
8003222: 2017 movs r0, #23
|
|
8003224: f000 fe54 bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
|
|
8003228: 2017 movs r0, #23
|
|
800322a: f000 fe6d bl 8003f08 <HAL_NVIC_EnableIRQ>
|
|
|
|
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
|
|
800322e: 2200 movs r2, #0
|
|
8003230: 2105 movs r1, #5
|
|
8003232: 2028 movs r0, #40 @ 0x28
|
|
8003234: f000 fe4c bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
|
|
8003238: 2028 movs r0, #40 @ 0x28
|
|
800323a: f000 fe65 bl 8003f08 <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
800323e: bf00 nop
|
|
8003240: 3728 adds r7, #40 @ 0x28
|
|
8003242: 46bd mov sp, r7
|
|
8003244: bd80 pop {r7, pc}
|
|
8003246: bf00 nop
|
|
8003248: 48000400 .word 0x48000400
|
|
|
|
0800324c <HAL_TIM_PeriodElapsedCallback>:
|
|
* a global variable "uwTick" used as application time base.
|
|
* @param htim : TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800324c: b580 push {r7, lr}
|
|
800324e: b082 sub sp, #8
|
|
8003250: af00 add r7, sp, #0
|
|
8003252: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN Callback 0 */
|
|
|
|
/* USER CODE END Callback 0 */
|
|
if (htim->Instance == TIM17) {
|
|
8003254: 687b ldr r3, [r7, #4]
|
|
8003256: 681b ldr r3, [r3, #0]
|
|
8003258: 4a04 ldr r2, [pc, #16] @ (800326c <HAL_TIM_PeriodElapsedCallback+0x20>)
|
|
800325a: 4293 cmp r3, r2
|
|
800325c: d101 bne.n 8003262 <HAL_TIM_PeriodElapsedCallback+0x16>
|
|
HAL_IncTick();
|
|
800325e: f000 fd3b bl 8003cd8 <HAL_IncTick>
|
|
}
|
|
/* USER CODE BEGIN Callback 1 */
|
|
|
|
/* USER CODE END Callback 1 */
|
|
}
|
|
8003262: bf00 nop
|
|
8003264: 3708 adds r7, #8
|
|
8003266: 46bd mov sp, r7
|
|
8003268: bd80 pop {r7, pc}
|
|
800326a: bf00 nop
|
|
800326c: 40014800 .word 0x40014800
|
|
|
|
08003270 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8003270: b480 push {r7}
|
|
8003272: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
|
|
/* USER CODE END Error_Handler_Debug */
|
|
}
|
|
8003274: bf00 nop
|
|
8003276: 46bd mov sp, r7
|
|
8003278: f85d 7b04 ldr.w r7, [sp], #4
|
|
800327c: 4770 bx lr
|
|
...
|
|
|
|
08003280 <HAL_UART_TxCpltCallback>:
|
|
|
|
extern UART_HandleTypeDef huart1;
|
|
extern SemaphoreHandle_t xSemaphore;
|
|
|
|
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8003280: b580 push {r7, lr}
|
|
8003282: b082 sub sp, #8
|
|
8003284: af00 add r7, sp, #0
|
|
8003286: 6078 str r0, [r7, #4]
|
|
static signed long xHigherPriorityTaskWoken = pdFALSE;
|
|
|
|
xSemaphoreGiveFromISR(xSemaphore, xHigherPriorityTaskWoken);
|
|
8003288: 4b0b ldr r3, [pc, #44] @ (80032b8 <HAL_UART_TxCpltCallback+0x38>)
|
|
800328a: 681b ldr r3, [r3, #0]
|
|
800328c: 4a0b ldr r2, [pc, #44] @ (80032bc <HAL_UART_TxCpltCallback+0x3c>)
|
|
800328e: 6812 ldr r2, [r2, #0]
|
|
8003290: 4611 mov r1, r2
|
|
8003292: 4618 mov r0, r3
|
|
8003294: f009 fbfe bl 800ca94 <xQueueGiveFromISR>
|
|
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
|
8003298: 4b08 ldr r3, [pc, #32] @ (80032bc <HAL_UART_TxCpltCallback+0x3c>)
|
|
800329a: 681b ldr r3, [r3, #0]
|
|
800329c: 2b00 cmp r3, #0
|
|
800329e: d007 beq.n 80032b0 <HAL_UART_TxCpltCallback+0x30>
|
|
80032a0: 4b07 ldr r3, [pc, #28] @ (80032c0 <HAL_UART_TxCpltCallback+0x40>)
|
|
80032a2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80032a6: 601a str r2, [r3, #0]
|
|
80032a8: f3bf 8f4f dsb sy
|
|
80032ac: f3bf 8f6f isb sy
|
|
|
|
}
|
|
80032b0: bf00 nop
|
|
80032b2: 3708 adds r7, #8
|
|
80032b4: 46bd mov sp, r7
|
|
80032b6: bd80 pop {r7, pc}
|
|
80032b8: 20000350 .word 0x20000350
|
|
80032bc: 2000128c .word 0x2000128c
|
|
80032c0: e000ed04 .word 0xe000ed04
|
|
|
|
080032c4 <__io_putchar>:
|
|
|
|
int __io_putchar(int ch)
|
|
{
|
|
80032c4: b580 push {r7, lr}
|
|
80032c6: b084 sub sp, #16
|
|
80032c8: af00 add r7, sp, #0
|
|
80032ca: 6078 str r0, [r7, #4]
|
|
BaseType_t status = xSemaphoreTake(xSemaphore, 0xffff);
|
|
80032cc: 4b09 ldr r3, [pc, #36] @ (80032f4 <__io_putchar+0x30>)
|
|
80032ce: 681b ldr r3, [r3, #0]
|
|
80032d0: f64f 71ff movw r1, #65535 @ 0xffff
|
|
80032d4: 4618 mov r0, r3
|
|
80032d6: f009 fd4f bl 800cd78 <xQueueSemaphoreTake>
|
|
80032da: 60f8 str r0, [r7, #12]
|
|
|
|
HAL_UART_Transmit_IT(&huart1, (uint8_t*) &ch, 1);
|
|
80032dc: 1d3b adds r3, r7, #4
|
|
80032de: 2201 movs r2, #1
|
|
80032e0: 4619 mov r1, r3
|
|
80032e2: 4805 ldr r0, [pc, #20] @ (80032f8 <__io_putchar+0x34>)
|
|
80032e4: f005 fd62 bl 8008dac <HAL_UART_Transmit_IT>
|
|
|
|
//while(HAL_OK != HAL_UART_Transmit(&huart1, (uint8_t*)&ch, 1, 30000))
|
|
//{
|
|
// ;
|
|
//}
|
|
return ch;
|
|
80032e8: 687b ldr r3, [r7, #4]
|
|
}
|
|
80032ea: 4618 mov r0, r3
|
|
80032ec: 3710 adds r7, #16
|
|
80032ee: 46bd mov sp, r7
|
|
80032f0: bd80 pop {r7, pc}
|
|
80032f2: bf00 nop
|
|
80032f4: 20000350 .word 0x20000350
|
|
80032f8: 20000c98 .word 0x20000c98
|
|
|
|
080032fc <__io_getchar>:
|
|
|
|
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
|
}
|
|
|
|
int __io_getchar(void)
|
|
{
|
|
80032fc: b580 push {r7, lr}
|
|
80032fe: b082 sub sp, #8
|
|
8003300: af00 add r7, sp, #0
|
|
uint8_t ch = 0;
|
|
8003302: 2300 movs r3, #0
|
|
8003304: 71fb strb r3, [r7, #7]
|
|
|
|
//while(HAL_OK != HAL_UART_Receive(&huart1, &ch, 1, 30000))
|
|
//{
|
|
// ;
|
|
//}
|
|
HAL_UART_Receive(&huart1, &ch, 1, 0);
|
|
8003306: 1df9 adds r1, r7, #7
|
|
8003308: 2300 movs r3, #0
|
|
800330a: 2201 movs r2, #1
|
|
800330c: 4803 ldr r0, [pc, #12] @ (800331c <__io_getchar+0x20>)
|
|
800330e: f005 fc83 bl 8008c18 <HAL_UART_Receive>
|
|
|
|
return ch;
|
|
8003312: 79fb ldrb r3, [r7, #7]
|
|
|
|
|
|
}
|
|
8003314: 4618 mov r0, r3
|
|
8003316: 3708 adds r7, #8
|
|
8003318: 46bd mov sp, r7
|
|
800331a: bd80 pop {r7, pc}
|
|
800331c: 20000c98 .word 0x20000c98
|
|
|
|
08003320 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8003320: b580 push {r7, lr}
|
|
8003322: b082 sub sp, #8
|
|
8003324: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8003326: 4b11 ldr r3, [pc, #68] @ (800336c <HAL_MspInit+0x4c>)
|
|
8003328: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800332a: 4a10 ldr r2, [pc, #64] @ (800336c <HAL_MspInit+0x4c>)
|
|
800332c: f043 0301 orr.w r3, r3, #1
|
|
8003330: 6613 str r3, [r2, #96] @ 0x60
|
|
8003332: 4b0e ldr r3, [pc, #56] @ (800336c <HAL_MspInit+0x4c>)
|
|
8003334: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8003336: f003 0301 and.w r3, r3, #1
|
|
800333a: 607b str r3, [r7, #4]
|
|
800333c: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800333e: 4b0b ldr r3, [pc, #44] @ (800336c <HAL_MspInit+0x4c>)
|
|
8003340: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003342: 4a0a ldr r2, [pc, #40] @ (800336c <HAL_MspInit+0x4c>)
|
|
8003344: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003348: 6593 str r3, [r2, #88] @ 0x58
|
|
800334a: 4b08 ldr r3, [pc, #32] @ (800336c <HAL_MspInit+0x4c>)
|
|
800334c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800334e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003352: 603b str r3, [r7, #0]
|
|
8003354: 683b ldr r3, [r7, #0]
|
|
|
|
/* System interrupt init*/
|
|
/* PendSV_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
|
|
8003356: 2200 movs r2, #0
|
|
8003358: 210f movs r1, #15
|
|
800335a: f06f 0001 mvn.w r0, #1
|
|
800335e: f000 fdb7 bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8003362: bf00 nop
|
|
8003364: 3708 adds r7, #8
|
|
8003366: 46bd mov sp, r7
|
|
8003368: bd80 pop {r7, pc}
|
|
800336a: bf00 nop
|
|
800336c: 40021000 .word 0x40021000
|
|
|
|
08003370 <HAL_DFSDM_ChannelMspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hdfsdm_channel: DFSDM_Channel handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)
|
|
{
|
|
8003370: b580 push {r7, lr}
|
|
8003372: b0ac sub sp, #176 @ 0xb0
|
|
8003374: af00 add r7, sp, #0
|
|
8003376: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8003378: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
800337c: 2200 movs r2, #0
|
|
800337e: 601a str r2, [r3, #0]
|
|
8003380: 605a str r2, [r3, #4]
|
|
8003382: 609a str r2, [r3, #8]
|
|
8003384: 60da str r2, [r3, #12]
|
|
8003386: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8003388: f107 0314 add.w r3, r7, #20
|
|
800338c: 2288 movs r2, #136 @ 0x88
|
|
800338e: 2100 movs r1, #0
|
|
8003390: 4618 mov r0, r3
|
|
8003392: f00d f899 bl 80104c8 <memset>
|
|
if(DFSDM1_Init == 0)
|
|
8003396: 4b25 ldr r3, [pc, #148] @ (800342c <HAL_DFSDM_ChannelMspInit+0xbc>)
|
|
8003398: 681b ldr r3, [r3, #0]
|
|
800339a: 2b00 cmp r3, #0
|
|
800339c: d142 bne.n 8003424 <HAL_DFSDM_ChannelMspInit+0xb4>
|
|
|
|
/* USER CODE END DFSDM1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1;
|
|
800339e: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80033a2: 617b str r3, [r7, #20]
|
|
PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
|
|
80033a4: 2300 movs r3, #0
|
|
80033a6: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
80033aa: f107 0314 add.w r3, r7, #20
|
|
80033ae: 4618 mov r0, r3
|
|
80033b0: f003 f920 bl 80065f4 <HAL_RCCEx_PeriphCLKConfig>
|
|
80033b4: 4603 mov r3, r0
|
|
80033b6: 2b00 cmp r3, #0
|
|
80033b8: d001 beq.n 80033be <HAL_DFSDM_ChannelMspInit+0x4e>
|
|
{
|
|
Error_Handler();
|
|
80033ba: f7ff ff59 bl 8003270 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_DFSDM1_CLK_ENABLE();
|
|
80033be: 4b1c ldr r3, [pc, #112] @ (8003430 <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
80033c0: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80033c2: 4a1b ldr r2, [pc, #108] @ (8003430 <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
80033c4: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
80033c8: 6613 str r3, [r2, #96] @ 0x60
|
|
80033ca: 4b19 ldr r3, [pc, #100] @ (8003430 <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
80033cc: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80033ce: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
80033d2: 613b str r3, [r7, #16]
|
|
80033d4: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
80033d6: 4b16 ldr r3, [pc, #88] @ (8003430 <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
80033d8: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80033da: 4a15 ldr r2, [pc, #84] @ (8003430 <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
80033dc: f043 0310 orr.w r3, r3, #16
|
|
80033e0: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80033e2: 4b13 ldr r3, [pc, #76] @ (8003430 <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
80033e4: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80033e6: f003 0310 and.w r3, r3, #16
|
|
80033ea: 60fb str r3, [r7, #12]
|
|
80033ec: 68fb ldr r3, [r7, #12]
|
|
/**DFSDM1 GPIO Configuration
|
|
PE7 ------> DFSDM1_DATIN2
|
|
PE9 ------> DFSDM1_CKOUT
|
|
*/
|
|
GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin;
|
|
80033ee: f44f 7320 mov.w r3, #640 @ 0x280
|
|
80033f2: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80033f6: 2302 movs r3, #2
|
|
80033f8: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80033fc: 2300 movs r3, #0
|
|
80033fe: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8003402: 2300 movs r3, #0
|
|
8003404: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1;
|
|
8003408: 2306 movs r3, #6
|
|
800340a: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
800340e: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8003412: 4619 mov r1, r3
|
|
8003414: 4807 ldr r0, [pc, #28] @ (8003434 <HAL_DFSDM_ChannelMspInit+0xc4>)
|
|
8003416: f000 ff11 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN DFSDM1_MspInit 1 */
|
|
|
|
/* USER CODE END DFSDM1_MspInit 1 */
|
|
|
|
DFSDM1_Init++;
|
|
800341a: 4b04 ldr r3, [pc, #16] @ (800342c <HAL_DFSDM_ChannelMspInit+0xbc>)
|
|
800341c: 681b ldr r3, [r3, #0]
|
|
800341e: 3301 adds r3, #1
|
|
8003420: 4a02 ldr r2, [pc, #8] @ (800342c <HAL_DFSDM_ChannelMspInit+0xbc>)
|
|
8003422: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
}
|
|
8003424: bf00 nop
|
|
8003426: 37b0 adds r7, #176 @ 0xb0
|
|
8003428: 46bd mov sp, r7
|
|
800342a: bd80 pop {r7, pc}
|
|
800342c: 20001290 .word 0x20001290
|
|
8003430: 40021000 .word 0x40021000
|
|
8003434: 48001000 .word 0x48001000
|
|
|
|
08003438 <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8003438: b580 push {r7, lr}
|
|
800343a: b0ac sub sp, #176 @ 0xb0
|
|
800343c: af00 add r7, sp, #0
|
|
800343e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8003440: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8003444: 2200 movs r2, #0
|
|
8003446: 601a str r2, [r3, #0]
|
|
8003448: 605a str r2, [r3, #4]
|
|
800344a: 609a str r2, [r3, #8]
|
|
800344c: 60da str r2, [r3, #12]
|
|
800344e: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8003450: f107 0314 add.w r3, r7, #20
|
|
8003454: 2288 movs r2, #136 @ 0x88
|
|
8003456: 2100 movs r1, #0
|
|
8003458: 4618 mov r0, r3
|
|
800345a: f00d f835 bl 80104c8 <memset>
|
|
if(hi2c->Instance==I2C2)
|
|
800345e: 687b ldr r3, [r7, #4]
|
|
8003460: 681b ldr r3, [r3, #0]
|
|
8003462: 4a21 ldr r2, [pc, #132] @ (80034e8 <HAL_I2C_MspInit+0xb0>)
|
|
8003464: 4293 cmp r3, r2
|
|
8003466: d13b bne.n 80034e0 <HAL_I2C_MspInit+0xa8>
|
|
|
|
/* USER CODE END I2C2_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
|
|
8003468: 2380 movs r3, #128 @ 0x80
|
|
800346a: 617b str r3, [r7, #20]
|
|
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
|
|
800346c: 2300 movs r3, #0
|
|
800346e: 66bb str r3, [r7, #104] @ 0x68
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8003470: f107 0314 add.w r3, r7, #20
|
|
8003474: 4618 mov r0, r3
|
|
8003476: f003 f8bd bl 80065f4 <HAL_RCCEx_PeriphCLKConfig>
|
|
800347a: 4603 mov r3, r0
|
|
800347c: 2b00 cmp r3, #0
|
|
800347e: d001 beq.n 8003484 <HAL_I2C_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8003480: f7ff fef6 bl 8003270 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8003484: 4b19 ldr r3, [pc, #100] @ (80034ec <HAL_I2C_MspInit+0xb4>)
|
|
8003486: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003488: 4a18 ldr r2, [pc, #96] @ (80034ec <HAL_I2C_MspInit+0xb4>)
|
|
800348a: f043 0302 orr.w r3, r3, #2
|
|
800348e: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8003490: 4b16 ldr r3, [pc, #88] @ (80034ec <HAL_I2C_MspInit+0xb4>)
|
|
8003492: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003494: f003 0302 and.w r3, r3, #2
|
|
8003498: 613b str r3, [r7, #16]
|
|
800349a: 693b ldr r3, [r7, #16]
|
|
/**I2C2 GPIO Configuration
|
|
PB10 ------> I2C2_SCL
|
|
PB11 ------> I2C2_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin;
|
|
800349c: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
80034a0: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
80034a4: 2312 movs r3, #18
|
|
80034a6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
80034aa: 2301 movs r3, #1
|
|
80034ac: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80034b0: 2303 movs r3, #3
|
|
80034b2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
|
|
80034b6: 2304 movs r3, #4
|
|
80034b8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80034bc: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
80034c0: 4619 mov r1, r3
|
|
80034c2: 480b ldr r0, [pc, #44] @ (80034f0 <HAL_I2C_MspInit+0xb8>)
|
|
80034c4: f000 feba bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C2_CLK_ENABLE();
|
|
80034c8: 4b08 ldr r3, [pc, #32] @ (80034ec <HAL_I2C_MspInit+0xb4>)
|
|
80034ca: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80034cc: 4a07 ldr r2, [pc, #28] @ (80034ec <HAL_I2C_MspInit+0xb4>)
|
|
80034ce: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
80034d2: 6593 str r3, [r2, #88] @ 0x58
|
|
80034d4: 4b05 ldr r3, [pc, #20] @ (80034ec <HAL_I2C_MspInit+0xb4>)
|
|
80034d6: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80034d8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80034dc: 60fb str r3, [r7, #12]
|
|
80034de: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END I2C2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80034e0: bf00 nop
|
|
80034e2: 37b0 adds r7, #176 @ 0xb0
|
|
80034e4: 46bd mov sp, r7
|
|
80034e6: bd80 pop {r7, pc}
|
|
80034e8: 40005800 .word 0x40005800
|
|
80034ec: 40021000 .word 0x40021000
|
|
80034f0: 48000400 .word 0x48000400
|
|
|
|
080034f4 <HAL_I2C_MspDeInit>:
|
|
* This function freeze the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
80034f4: b580 push {r7, lr}
|
|
80034f6: b082 sub sp, #8
|
|
80034f8: af00 add r7, sp, #0
|
|
80034fa: 6078 str r0, [r7, #4]
|
|
if(hi2c->Instance==I2C2)
|
|
80034fc: 687b ldr r3, [r7, #4]
|
|
80034fe: 681b ldr r3, [r3, #0]
|
|
8003500: 4a0b ldr r2, [pc, #44] @ (8003530 <HAL_I2C_MspDeInit+0x3c>)
|
|
8003502: 4293 cmp r3, r2
|
|
8003504: d10f bne.n 8003526 <HAL_I2C_MspDeInit+0x32>
|
|
{
|
|
/* USER CODE BEGIN I2C2_MspDeInit 0 */
|
|
|
|
/* USER CODE END I2C2_MspDeInit 0 */
|
|
/* Peripheral clock disable */
|
|
__HAL_RCC_I2C2_CLK_DISABLE();
|
|
8003506: 4b0b ldr r3, [pc, #44] @ (8003534 <HAL_I2C_MspDeInit+0x40>)
|
|
8003508: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800350a: 4a0a ldr r2, [pc, #40] @ (8003534 <HAL_I2C_MspDeInit+0x40>)
|
|
800350c: f423 0380 bic.w r3, r3, #4194304 @ 0x400000
|
|
8003510: 6593 str r3, [r2, #88] @ 0x58
|
|
|
|
/**I2C2 GPIO Configuration
|
|
PB10 ------> I2C2_SCL
|
|
PB11 ------> I2C2_SDA
|
|
*/
|
|
HAL_GPIO_DeInit(INTERNAL_I2C2_SCL_GPIO_Port, INTERNAL_I2C2_SCL_Pin);
|
|
8003512: f44f 6180 mov.w r1, #1024 @ 0x400
|
|
8003516: 4808 ldr r0, [pc, #32] @ (8003538 <HAL_I2C_MspDeInit+0x44>)
|
|
8003518: f001 f83a bl 8004590 <HAL_GPIO_DeInit>
|
|
|
|
HAL_GPIO_DeInit(INTERNAL_I2C2_SDA_GPIO_Port, INTERNAL_I2C2_SDA_Pin);
|
|
800351c: f44f 6100 mov.w r1, #2048 @ 0x800
|
|
8003520: 4805 ldr r0, [pc, #20] @ (8003538 <HAL_I2C_MspDeInit+0x44>)
|
|
8003522: f001 f835 bl 8004590 <HAL_GPIO_DeInit>
|
|
/* USER CODE BEGIN I2C2_MspDeInit 1 */
|
|
|
|
/* USER CODE END I2C2_MspDeInit 1 */
|
|
}
|
|
|
|
}
|
|
8003526: bf00 nop
|
|
8003528: 3708 adds r7, #8
|
|
800352a: 46bd mov sp, r7
|
|
800352c: bd80 pop {r7, pc}
|
|
800352e: bf00 nop
|
|
8003530: 40005800 .word 0x40005800
|
|
8003534: 40021000 .word 0x40021000
|
|
8003538: 48000400 .word 0x48000400
|
|
|
|
0800353c <HAL_QSPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hqspi: QSPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
|
|
{
|
|
800353c: b580 push {r7, lr}
|
|
800353e: b08a sub sp, #40 @ 0x28
|
|
8003540: af00 add r7, sp, #0
|
|
8003542: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8003544: f107 0314 add.w r3, r7, #20
|
|
8003548: 2200 movs r2, #0
|
|
800354a: 601a str r2, [r3, #0]
|
|
800354c: 605a str r2, [r3, #4]
|
|
800354e: 609a str r2, [r3, #8]
|
|
8003550: 60da str r2, [r3, #12]
|
|
8003552: 611a str r2, [r3, #16]
|
|
if(hqspi->Instance==QUADSPI)
|
|
8003554: 687b ldr r3, [r7, #4]
|
|
8003556: 681b ldr r3, [r3, #0]
|
|
8003558: 4a17 ldr r2, [pc, #92] @ (80035b8 <HAL_QSPI_MspInit+0x7c>)
|
|
800355a: 4293 cmp r3, r2
|
|
800355c: d128 bne.n 80035b0 <HAL_QSPI_MspInit+0x74>
|
|
{
|
|
/* USER CODE BEGIN QUADSPI_MspInit 0 */
|
|
|
|
/* USER CODE END QUADSPI_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_QSPI_CLK_ENABLE();
|
|
800355e: 4b17 ldr r3, [pc, #92] @ (80035bc <HAL_QSPI_MspInit+0x80>)
|
|
8003560: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8003562: 4a16 ldr r2, [pc, #88] @ (80035bc <HAL_QSPI_MspInit+0x80>)
|
|
8003564: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003568: 6513 str r3, [r2, #80] @ 0x50
|
|
800356a: 4b14 ldr r3, [pc, #80] @ (80035bc <HAL_QSPI_MspInit+0x80>)
|
|
800356c: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800356e: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003572: 613b str r3, [r7, #16]
|
|
8003574: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8003576: 4b11 ldr r3, [pc, #68] @ (80035bc <HAL_QSPI_MspInit+0x80>)
|
|
8003578: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800357a: 4a10 ldr r2, [pc, #64] @ (80035bc <HAL_QSPI_MspInit+0x80>)
|
|
800357c: f043 0310 orr.w r3, r3, #16
|
|
8003580: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8003582: 4b0e ldr r3, [pc, #56] @ (80035bc <HAL_QSPI_MspInit+0x80>)
|
|
8003584: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003586: f003 0310 and.w r3, r3, #16
|
|
800358a: 60fb str r3, [r7, #12]
|
|
800358c: 68fb ldr r3, [r7, #12]
|
|
PE12 ------> QUADSPI_BK1_IO0
|
|
PE13 ------> QUADSPI_BK1_IO1
|
|
PE14 ------> QUADSPI_BK1_IO2
|
|
PE15 ------> QUADSPI_BK1_IO3
|
|
*/
|
|
GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin
|
|
800358e: f44f 437c mov.w r3, #64512 @ 0xfc00
|
|
8003592: 617b str r3, [r7, #20]
|
|
|QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8003594: 2302 movs r3, #2
|
|
8003596: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003598: 2300 movs r3, #0
|
|
800359a: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800359c: 2303 movs r3, #3
|
|
800359e: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
|
|
80035a0: 230a movs r3, #10
|
|
80035a2: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
80035a4: f107 0314 add.w r3, r7, #20
|
|
80035a8: 4619 mov r1, r3
|
|
80035aa: 4805 ldr r0, [pc, #20] @ (80035c0 <HAL_QSPI_MspInit+0x84>)
|
|
80035ac: f000 fe46 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END QUADSPI_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80035b0: bf00 nop
|
|
80035b2: 3728 adds r7, #40 @ 0x28
|
|
80035b4: 46bd mov sp, r7
|
|
80035b6: bd80 pop {r7, pc}
|
|
80035b8: a0001000 .word 0xa0001000
|
|
80035bc: 40021000 .word 0x40021000
|
|
80035c0: 48001000 .word 0x48001000
|
|
|
|
080035c4 <HAL_SPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
80035c4: b580 push {r7, lr}
|
|
80035c6: b08a sub sp, #40 @ 0x28
|
|
80035c8: af00 add r7, sp, #0
|
|
80035ca: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80035cc: f107 0314 add.w r3, r7, #20
|
|
80035d0: 2200 movs r2, #0
|
|
80035d2: 601a str r2, [r3, #0]
|
|
80035d4: 605a str r2, [r3, #4]
|
|
80035d6: 609a str r2, [r3, #8]
|
|
80035d8: 60da str r2, [r3, #12]
|
|
80035da: 611a str r2, [r3, #16]
|
|
if(hspi->Instance==SPI3)
|
|
80035dc: 687b ldr r3, [r7, #4]
|
|
80035de: 681b ldr r3, [r3, #0]
|
|
80035e0: 4a17 ldr r2, [pc, #92] @ (8003640 <HAL_SPI_MspInit+0x7c>)
|
|
80035e2: 4293 cmp r3, r2
|
|
80035e4: d128 bne.n 8003638 <HAL_SPI_MspInit+0x74>
|
|
{
|
|
/* USER CODE BEGIN SPI3_MspInit 0 */
|
|
|
|
/* USER CODE END SPI3_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_SPI3_CLK_ENABLE();
|
|
80035e6: 4b17 ldr r3, [pc, #92] @ (8003644 <HAL_SPI_MspInit+0x80>)
|
|
80035e8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80035ea: 4a16 ldr r2, [pc, #88] @ (8003644 <HAL_SPI_MspInit+0x80>)
|
|
80035ec: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80035f0: 6593 str r3, [r2, #88] @ 0x58
|
|
80035f2: 4b14 ldr r3, [pc, #80] @ (8003644 <HAL_SPI_MspInit+0x80>)
|
|
80035f4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80035f6: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80035fa: 613b str r3, [r7, #16]
|
|
80035fc: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80035fe: 4b11 ldr r3, [pc, #68] @ (8003644 <HAL_SPI_MspInit+0x80>)
|
|
8003600: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003602: 4a10 ldr r2, [pc, #64] @ (8003644 <HAL_SPI_MspInit+0x80>)
|
|
8003604: f043 0304 orr.w r3, r3, #4
|
|
8003608: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800360a: 4b0e ldr r3, [pc, #56] @ (8003644 <HAL_SPI_MspInit+0x80>)
|
|
800360c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800360e: f003 0304 and.w r3, r3, #4
|
|
8003612: 60fb str r3, [r7, #12]
|
|
8003614: 68fb ldr r3, [r7, #12]
|
|
/**SPI3 GPIO Configuration
|
|
PC10 ------> SPI3_SCK
|
|
PC11 ------> SPI3_MISO
|
|
PC12 ------> SPI3_MOSI
|
|
*/
|
|
GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin;
|
|
8003616: f44f 53e0 mov.w r3, #7168 @ 0x1c00
|
|
800361a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800361c: 2302 movs r3, #2
|
|
800361e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003620: 2300 movs r3, #0
|
|
8003622: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8003624: 2303 movs r3, #3
|
|
8003626: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
|
|
8003628: 2306 movs r3, #6
|
|
800362a: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
800362c: f107 0314 add.w r3, r7, #20
|
|
8003630: 4619 mov r1, r3
|
|
8003632: 4805 ldr r0, [pc, #20] @ (8003648 <HAL_SPI_MspInit+0x84>)
|
|
8003634: f000 fe02 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END SPI3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8003638: bf00 nop
|
|
800363a: 3728 adds r7, #40 @ 0x28
|
|
800363c: 46bd mov sp, r7
|
|
800363e: bd80 pop {r7, pc}
|
|
8003640: 40003c00 .word 0x40003c00
|
|
8003644: 40021000 .word 0x40021000
|
|
8003648: 48000800 .word 0x48000800
|
|
|
|
0800364c <HAL_SPI_MspDeInit>:
|
|
* This function freeze the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
800364c: b580 push {r7, lr}
|
|
800364e: b082 sub sp, #8
|
|
8003650: af00 add r7, sp, #0
|
|
8003652: 6078 str r0, [r7, #4]
|
|
if(hspi->Instance==SPI3)
|
|
8003654: 687b ldr r3, [r7, #4]
|
|
8003656: 681b ldr r3, [r3, #0]
|
|
8003658: 4a08 ldr r2, [pc, #32] @ (800367c <HAL_SPI_MspDeInit+0x30>)
|
|
800365a: 4293 cmp r3, r2
|
|
800365c: d10a bne.n 8003674 <HAL_SPI_MspDeInit+0x28>
|
|
{
|
|
/* USER CODE BEGIN SPI3_MspDeInit 0 */
|
|
|
|
/* USER CODE END SPI3_MspDeInit 0 */
|
|
/* Peripheral clock disable */
|
|
__HAL_RCC_SPI3_CLK_DISABLE();
|
|
800365e: 4b08 ldr r3, [pc, #32] @ (8003680 <HAL_SPI_MspDeInit+0x34>)
|
|
8003660: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003662: 4a07 ldr r2, [pc, #28] @ (8003680 <HAL_SPI_MspDeInit+0x34>)
|
|
8003664: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
8003668: 6593 str r3, [r2, #88] @ 0x58
|
|
/**SPI3 GPIO Configuration
|
|
PC10 ------> SPI3_SCK
|
|
PC11 ------> SPI3_MISO
|
|
PC12 ------> SPI3_MOSI
|
|
*/
|
|
HAL_GPIO_DeInit(GPIOC, INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin);
|
|
800366a: f44f 51e0 mov.w r1, #7168 @ 0x1c00
|
|
800366e: 4805 ldr r0, [pc, #20] @ (8003684 <HAL_SPI_MspDeInit+0x38>)
|
|
8003670: f000 ff8e bl 8004590 <HAL_GPIO_DeInit>
|
|
/* USER CODE BEGIN SPI3_MspDeInit 1 */
|
|
|
|
/* USER CODE END SPI3_MspDeInit 1 */
|
|
}
|
|
|
|
}
|
|
8003674: bf00 nop
|
|
8003676: 3708 adds r7, #8
|
|
8003678: 46bd mov sp, r7
|
|
800367a: bd80 pop {r7, pc}
|
|
800367c: 40003c00 .word 0x40003c00
|
|
8003680: 40021000 .word 0x40021000
|
|
8003684: 48000800 .word 0x48000800
|
|
|
|
08003688 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8003688: b580 push {r7, lr}
|
|
800368a: b0ae sub sp, #184 @ 0xb8
|
|
800368c: af00 add r7, sp, #0
|
|
800368e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8003690: f107 03a4 add.w r3, r7, #164 @ 0xa4
|
|
8003694: 2200 movs r2, #0
|
|
8003696: 601a str r2, [r3, #0]
|
|
8003698: 605a str r2, [r3, #4]
|
|
800369a: 609a str r2, [r3, #8]
|
|
800369c: 60da str r2, [r3, #12]
|
|
800369e: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
80036a0: f107 031c add.w r3, r7, #28
|
|
80036a4: 2288 movs r2, #136 @ 0x88
|
|
80036a6: 2100 movs r1, #0
|
|
80036a8: 4618 mov r0, r3
|
|
80036aa: f00c ff0d bl 80104c8 <memset>
|
|
if(huart->Instance==USART1)
|
|
80036ae: 687b ldr r3, [r7, #4]
|
|
80036b0: 681b ldr r3, [r3, #0]
|
|
80036b2: 4a46 ldr r2, [pc, #280] @ (80037cc <HAL_UART_MspInit+0x144>)
|
|
80036b4: 4293 cmp r3, r2
|
|
80036b6: d143 bne.n 8003740 <HAL_UART_MspInit+0xb8>
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|
80036b8: 2301 movs r3, #1
|
|
80036ba: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|
80036bc: 2300 movs r3, #0
|
|
80036be: 657b str r3, [r7, #84] @ 0x54
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
80036c0: f107 031c add.w r3, r7, #28
|
|
80036c4: 4618 mov r0, r3
|
|
80036c6: f002 ff95 bl 80065f4 <HAL_RCCEx_PeriphCLKConfig>
|
|
80036ca: 4603 mov r3, r0
|
|
80036cc: 2b00 cmp r3, #0
|
|
80036ce: d001 beq.n 80036d4 <HAL_UART_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
80036d0: f7ff fdce bl 8003270 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
80036d4: 4b3e ldr r3, [pc, #248] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
80036d6: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80036d8: 4a3d ldr r2, [pc, #244] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
80036da: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
80036de: 6613 str r3, [r2, #96] @ 0x60
|
|
80036e0: 4b3b ldr r3, [pc, #236] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
80036e2: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80036e4: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80036e8: 61bb str r3, [r7, #24]
|
|
80036ea: 69bb ldr r3, [r7, #24]
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80036ec: 4b38 ldr r3, [pc, #224] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
80036ee: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80036f0: 4a37 ldr r2, [pc, #220] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
80036f2: f043 0302 orr.w r3, r3, #2
|
|
80036f6: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80036f8: 4b35 ldr r3, [pc, #212] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
80036fa: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80036fc: f003 0302 and.w r3, r3, #2
|
|
8003700: 617b str r3, [r7, #20]
|
|
8003702: 697b ldr r3, [r7, #20]
|
|
/**USART1 GPIO Configuration
|
|
PB6 ------> USART1_TX
|
|
PB7 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin;
|
|
8003704: 23c0 movs r3, #192 @ 0xc0
|
|
8003706: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800370a: 2302 movs r3, #2
|
|
800370c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003710: 2300 movs r3, #0
|
|
8003712: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8003716: 2303 movs r3, #3
|
|
8003718: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
800371c: 2307 movs r3, #7
|
|
800371e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8003722: f107 03a4 add.w r3, r7, #164 @ 0xa4
|
|
8003726: 4619 mov r1, r3
|
|
8003728: 482a ldr r0, [pc, #168] @ (80037d4 <HAL_UART_MspInit+0x14c>)
|
|
800372a: f000 fd87 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* USART1 interrupt Init */
|
|
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
|
|
800372e: 2200 movs r2, #0
|
|
8003730: 2105 movs r1, #5
|
|
8003732: 2025 movs r0, #37 @ 0x25
|
|
8003734: f000 fbcc bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
|
8003738: 2025 movs r0, #37 @ 0x25
|
|
800373a: f000 fbe5 bl 8003f08 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USART3_MspInit 1 */
|
|
|
|
/* USER CODE END USART3_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
800373e: e040 b.n 80037c2 <HAL_UART_MspInit+0x13a>
|
|
else if(huart->Instance==USART3)
|
|
8003740: 687b ldr r3, [r7, #4]
|
|
8003742: 681b ldr r3, [r3, #0]
|
|
8003744: 4a24 ldr r2, [pc, #144] @ (80037d8 <HAL_UART_MspInit+0x150>)
|
|
8003746: 4293 cmp r3, r2
|
|
8003748: d13b bne.n 80037c2 <HAL_UART_MspInit+0x13a>
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3;
|
|
800374a: 2304 movs r3, #4
|
|
800374c: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
|
|
800374e: 2300 movs r3, #0
|
|
8003750: 65fb str r3, [r7, #92] @ 0x5c
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8003752: f107 031c add.w r3, r7, #28
|
|
8003756: 4618 mov r0, r3
|
|
8003758: f002 ff4c bl 80065f4 <HAL_RCCEx_PeriphCLKConfig>
|
|
800375c: 4603 mov r3, r0
|
|
800375e: 2b00 cmp r3, #0
|
|
8003760: d001 beq.n 8003766 <HAL_UART_MspInit+0xde>
|
|
Error_Handler();
|
|
8003762: f7ff fd85 bl 8003270 <Error_Handler>
|
|
__HAL_RCC_USART3_CLK_ENABLE();
|
|
8003766: 4b1a ldr r3, [pc, #104] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
8003768: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800376a: 4a19 ldr r2, [pc, #100] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
800376c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8003770: 6593 str r3, [r2, #88] @ 0x58
|
|
8003772: 4b17 ldr r3, [pc, #92] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
8003774: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003776: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
800377a: 613b str r3, [r7, #16]
|
|
800377c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
800377e: 4b14 ldr r3, [pc, #80] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
8003780: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003782: 4a13 ldr r2, [pc, #76] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
8003784: f043 0308 orr.w r3, r3, #8
|
|
8003788: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800378a: 4b11 ldr r3, [pc, #68] @ (80037d0 <HAL_UART_MspInit+0x148>)
|
|
800378c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800378e: f003 0308 and.w r3, r3, #8
|
|
8003792: 60fb str r3, [r7, #12]
|
|
8003794: 68fb ldr r3, [r7, #12]
|
|
GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin;
|
|
8003796: f44f 7340 mov.w r3, #768 @ 0x300
|
|
800379a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800379e: 2302 movs r3, #2
|
|
80037a0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80037a4: 2300 movs r3, #0
|
|
80037a6: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80037aa: 2303 movs r3, #3
|
|
80037ac: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
|
|
80037b0: 2307 movs r3, #7
|
|
80037b2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
80037b6: f107 03a4 add.w r3, r7, #164 @ 0xa4
|
|
80037ba: 4619 mov r1, r3
|
|
80037bc: 4807 ldr r0, [pc, #28] @ (80037dc <HAL_UART_MspInit+0x154>)
|
|
80037be: f000 fd3d bl 800423c <HAL_GPIO_Init>
|
|
}
|
|
80037c2: bf00 nop
|
|
80037c4: 37b8 adds r7, #184 @ 0xb8
|
|
80037c6: 46bd mov sp, r7
|
|
80037c8: bd80 pop {r7, pc}
|
|
80037ca: bf00 nop
|
|
80037cc: 40013800 .word 0x40013800
|
|
80037d0: 40021000 .word 0x40021000
|
|
80037d4: 48000400 .word 0x48000400
|
|
80037d8: 40004800 .word 0x40004800
|
|
80037dc: 48000c00 .word 0x48000c00
|
|
|
|
080037e0 <HAL_PCD_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hpcd: PCD handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
|
{
|
|
80037e0: b580 push {r7, lr}
|
|
80037e2: b0ac sub sp, #176 @ 0xb0
|
|
80037e4: af00 add r7, sp, #0
|
|
80037e6: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80037e8: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
80037ec: 2200 movs r2, #0
|
|
80037ee: 601a str r2, [r3, #0]
|
|
80037f0: 605a str r2, [r3, #4]
|
|
80037f2: 609a str r2, [r3, #8]
|
|
80037f4: 60da str r2, [r3, #12]
|
|
80037f6: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
80037f8: f107 0314 add.w r3, r7, #20
|
|
80037fc: 2288 movs r2, #136 @ 0x88
|
|
80037fe: 2100 movs r1, #0
|
|
8003800: 4618 mov r0, r3
|
|
8003802: f00c fe61 bl 80104c8 <memset>
|
|
if(hpcd->Instance==USB_OTG_FS)
|
|
8003806: 687b ldr r3, [r7, #4]
|
|
8003808: 681b ldr r3, [r3, #0]
|
|
800380a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
800380e: d17c bne.n 800390a <HAL_PCD_MspInit+0x12a>
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
|
8003810: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8003814: 617b str r3, [r7, #20]
|
|
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
|
8003816: f04f 6380 mov.w r3, #67108864 @ 0x4000000
|
|
800381a: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
|
|
800381e: 2301 movs r3, #1
|
|
8003820: 61bb str r3, [r7, #24]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
|
8003822: 2301 movs r3, #1
|
|
8003824: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
|
|
8003826: 2318 movs r3, #24
|
|
8003828: 623b str r3, [r7, #32]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
|
800382a: 2307 movs r3, #7
|
|
800382c: 627b str r3, [r7, #36] @ 0x24
|
|
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
|
800382e: 2302 movs r3, #2
|
|
8003830: 62bb str r3, [r7, #40] @ 0x28
|
|
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
|
8003832: 2302 movs r3, #2
|
|
8003834: 62fb str r3, [r7, #44] @ 0x2c
|
|
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
|
8003836: f44f 1380 mov.w r3, #1048576 @ 0x100000
|
|
800383a: 633b str r3, [r7, #48] @ 0x30
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
800383c: f107 0314 add.w r3, r7, #20
|
|
8003840: 4618 mov r0, r3
|
|
8003842: f002 fed7 bl 80065f4 <HAL_RCCEx_PeriphCLKConfig>
|
|
8003846: 4603 mov r3, r0
|
|
8003848: 2b00 cmp r3, #0
|
|
800384a: d001 beq.n 8003850 <HAL_PCD_MspInit+0x70>
|
|
{
|
|
Error_Handler();
|
|
800384c: f7ff fd10 bl 8003270 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8003850: 4b30 ldr r3, [pc, #192] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
8003852: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003854: 4a2f ldr r2, [pc, #188] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
8003856: f043 0301 orr.w r3, r3, #1
|
|
800385a: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800385c: 4b2d ldr r3, [pc, #180] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
800385e: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003860: f003 0301 and.w r3, r3, #1
|
|
8003864: 613b str r3, [r7, #16]
|
|
8003866: 693b ldr r3, [r7, #16]
|
|
PA9 ------> USB_OTG_FS_VBUS
|
|
PA10 ------> USB_OTG_FS_ID
|
|
PA11 ------> USB_OTG_FS_DM
|
|
PA12 ------> USB_OTG_FS_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin;
|
|
8003868: f44f 7300 mov.w r3, #512 @ 0x200
|
|
800386c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8003870: 2300 movs r3, #0
|
|
8003872: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003876: 2300 movs r3, #0
|
|
8003878: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
|
|
800387c: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8003880: 4619 mov r1, r3
|
|
8003882: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8003886: f000 fcd9 bl 800423c <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin;
|
|
800388a: f44f 53e0 mov.w r3, #7168 @ 0x1c00
|
|
800388e: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8003892: 2302 movs r3, #2
|
|
8003894: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8003898: 2300 movs r3, #0
|
|
800389a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800389e: 2303 movs r3, #3
|
|
80038a0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
|
80038a4: 230a movs r3, #10
|
|
80038a6: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80038aa: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
80038ae: 4619 mov r1, r3
|
|
80038b0: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80038b4: f000 fcc2 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
|
80038b8: 4b16 ldr r3, [pc, #88] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038ba: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80038bc: 4a15 ldr r2, [pc, #84] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038be: f443 5380 orr.w r3, r3, #4096 @ 0x1000
|
|
80038c2: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80038c4: 4b13 ldr r3, [pc, #76] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038c6: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80038c8: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80038cc: 60fb str r3, [r7, #12]
|
|
80038ce: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Enable VDDUSB */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
80038d0: 4b10 ldr r3, [pc, #64] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038d2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80038d4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80038d8: 2b00 cmp r3, #0
|
|
80038da: d114 bne.n 8003906 <HAL_PCD_MspInit+0x126>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80038dc: 4b0d ldr r3, [pc, #52] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038de: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80038e0: 4a0c ldr r2, [pc, #48] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038e2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80038e6: 6593 str r3, [r2, #88] @ 0x58
|
|
80038e8: 4b0a ldr r3, [pc, #40] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038ea: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80038ec: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80038f0: 60bb str r3, [r7, #8]
|
|
80038f2: 68bb ldr r3, [r7, #8]
|
|
HAL_PWREx_EnableVddUSB();
|
|
80038f4: f001 ff80 bl 80057f8 <HAL_PWREx_EnableVddUSB>
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80038f8: 4b06 ldr r3, [pc, #24] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038fa: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80038fc: 4a05 ldr r2, [pc, #20] @ (8003914 <HAL_PCD_MspInit+0x134>)
|
|
80038fe: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8003902: 6593 str r3, [r2, #88] @ 0x58
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8003904: e001 b.n 800390a <HAL_PCD_MspInit+0x12a>
|
|
HAL_PWREx_EnableVddUSB();
|
|
8003906: f001 ff77 bl 80057f8 <HAL_PWREx_EnableVddUSB>
|
|
}
|
|
800390a: bf00 nop
|
|
800390c: 37b0 adds r7, #176 @ 0xb0
|
|
800390e: 46bd mov sp, r7
|
|
8003910: bd80 pop {r7, pc}
|
|
8003912: bf00 nop
|
|
8003914: 40021000 .word 0x40021000
|
|
|
|
08003918 <HAL_InitTick>:
|
|
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
|
* @param TickPriority: Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8003918: b580 push {r7, lr}
|
|
800391a: b08c sub sp, #48 @ 0x30
|
|
800391c: af00 add r7, sp, #0
|
|
800391e: 6078 str r0, [r7, #4]
|
|
RCC_ClkInitTypeDef clkconfig;
|
|
uint32_t uwTimclock;
|
|
uint32_t uwPrescalerValue;
|
|
uint32_t pFLatency;
|
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003920: 2300 movs r3, #0
|
|
8003922: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
/* Enable TIM17 clock */
|
|
__HAL_RCC_TIM17_CLK_ENABLE();
|
|
8003926: 4b2e ldr r3, [pc, #184] @ (80039e0 <HAL_InitTick+0xc8>)
|
|
8003928: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800392a: 4a2d ldr r2, [pc, #180] @ (80039e0 <HAL_InitTick+0xc8>)
|
|
800392c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8003930: 6613 str r3, [r2, #96] @ 0x60
|
|
8003932: 4b2b ldr r3, [pc, #172] @ (80039e0 <HAL_InitTick+0xc8>)
|
|
8003934: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8003936: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
800393a: 60bb str r3, [r7, #8]
|
|
800393c: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Get clock configuration */
|
|
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
|
800393e: f107 020c add.w r2, r7, #12
|
|
8003942: f107 0310 add.w r3, r7, #16
|
|
8003946: 4611 mov r1, r2
|
|
8003948: 4618 mov r0, r3
|
|
800394a: f002 fdc1 bl 80064d0 <HAL_RCC_GetClockConfig>
|
|
|
|
/* Compute TIM17 clock */
|
|
uwTimclock = HAL_RCC_GetPCLK2Freq();
|
|
800394e: f002 fda9 bl 80064a4 <HAL_RCC_GetPCLK2Freq>
|
|
8003952: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
/* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
|
|
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
|
8003954: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003956: 4a23 ldr r2, [pc, #140] @ (80039e4 <HAL_InitTick+0xcc>)
|
|
8003958: fba2 2303 umull r2, r3, r2, r3
|
|
800395c: 0c9b lsrs r3, r3, #18
|
|
800395e: 3b01 subs r3, #1
|
|
8003960: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Initialize TIM17 */
|
|
htim17.Instance = TIM17;
|
|
8003962: 4b21 ldr r3, [pc, #132] @ (80039e8 <HAL_InitTick+0xd0>)
|
|
8003964: 4a21 ldr r2, [pc, #132] @ (80039ec <HAL_InitTick+0xd4>)
|
|
8003966: 601a str r2, [r3, #0]
|
|
* Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
|
|
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
|
* ClockDivision = 0
|
|
* Counter direction = Up
|
|
*/
|
|
htim17.Init.Period = (1000000U / 1000U) - 1U;
|
|
8003968: 4b1f ldr r3, [pc, #124] @ (80039e8 <HAL_InitTick+0xd0>)
|
|
800396a: f240 32e7 movw r2, #999 @ 0x3e7
|
|
800396e: 60da str r2, [r3, #12]
|
|
htim17.Init.Prescaler = uwPrescalerValue;
|
|
8003970: 4a1d ldr r2, [pc, #116] @ (80039e8 <HAL_InitTick+0xd0>)
|
|
8003972: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003974: 6053 str r3, [r2, #4]
|
|
htim17.Init.ClockDivision = 0;
|
|
8003976: 4b1c ldr r3, [pc, #112] @ (80039e8 <HAL_InitTick+0xd0>)
|
|
8003978: 2200 movs r2, #0
|
|
800397a: 611a str r2, [r3, #16]
|
|
htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800397c: 4b1a ldr r3, [pc, #104] @ (80039e8 <HAL_InitTick+0xd0>)
|
|
800397e: 2200 movs r2, #0
|
|
8003980: 609a str r2, [r3, #8]
|
|
htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8003982: 4b19 ldr r3, [pc, #100] @ (80039e8 <HAL_InitTick+0xd0>)
|
|
8003984: 2200 movs r2, #0
|
|
8003986: 619a str r2, [r3, #24]
|
|
|
|
status = HAL_TIM_Base_Init(&htim17);
|
|
8003988: 4817 ldr r0, [pc, #92] @ (80039e8 <HAL_InitTick+0xd0>)
|
|
800398a: f004 fe32 bl 80085f2 <HAL_TIM_Base_Init>
|
|
800398e: 4603 mov r3, r0
|
|
8003990: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
if (status == HAL_OK)
|
|
8003994: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
8003998: 2b00 cmp r3, #0
|
|
800399a: d11b bne.n 80039d4 <HAL_InitTick+0xbc>
|
|
{
|
|
/* Start the TIM time Base generation in interrupt mode */
|
|
status = HAL_TIM_Base_Start_IT(&htim17);
|
|
800399c: 4812 ldr r0, [pc, #72] @ (80039e8 <HAL_InitTick+0xd0>)
|
|
800399e: f004 fe89 bl 80086b4 <HAL_TIM_Base_Start_IT>
|
|
80039a2: 4603 mov r3, r0
|
|
80039a4: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
if (status == HAL_OK)
|
|
80039a8: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
80039ac: 2b00 cmp r3, #0
|
|
80039ae: d111 bne.n 80039d4 <HAL_InitTick+0xbc>
|
|
{
|
|
/* Enable the TIM17 global Interrupt */
|
|
HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn);
|
|
80039b0: 201a movs r0, #26
|
|
80039b2: f000 faa9 bl 8003f08 <HAL_NVIC_EnableIRQ>
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80039b6: 687b ldr r3, [r7, #4]
|
|
80039b8: 2b0f cmp r3, #15
|
|
80039ba: d808 bhi.n 80039ce <HAL_InitTick+0xb6>
|
|
{
|
|
/* Configure the TIM IRQ priority */
|
|
HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority, 0U);
|
|
80039bc: 2200 movs r2, #0
|
|
80039be: 6879 ldr r1, [r7, #4]
|
|
80039c0: 201a movs r0, #26
|
|
80039c2: f000 fa85 bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80039c6: 4a0a ldr r2, [pc, #40] @ (80039f0 <HAL_InitTick+0xd8>)
|
|
80039c8: 687b ldr r3, [r7, #4]
|
|
80039ca: 6013 str r3, [r2, #0]
|
|
80039cc: e002 b.n 80039d4 <HAL_InitTick+0xbc>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
80039ce: 2301 movs r3, #1
|
|
80039d0: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
80039d4: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
}
|
|
80039d8: 4618 mov r0, r3
|
|
80039da: 3730 adds r7, #48 @ 0x30
|
|
80039dc: 46bd mov sp, r7
|
|
80039de: bd80 pop {r7, pc}
|
|
80039e0: 40021000 .word 0x40021000
|
|
80039e4: 431bde83 .word 0x431bde83
|
|
80039e8: 20001294 .word 0x20001294
|
|
80039ec: 40014800 .word 0x40014800
|
|
80039f0: 200000c8 .word 0x200000c8
|
|
|
|
080039f4 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80039f4: b480 push {r7}
|
|
80039f6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80039f8: bf00 nop
|
|
80039fa: e7fd b.n 80039f8 <NMI_Handler+0x4>
|
|
|
|
080039fc <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80039fc: b480 push {r7}
|
|
80039fe: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8003a00: bf00 nop
|
|
8003a02: e7fd b.n 8003a00 <HardFault_Handler+0x4>
|
|
|
|
08003a04 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8003a04: b480 push {r7}
|
|
8003a06: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8003a08: bf00 nop
|
|
8003a0a: e7fd b.n 8003a08 <MemManage_Handler+0x4>
|
|
|
|
08003a0c <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8003a0c: b480 push {r7}
|
|
8003a0e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8003a10: bf00 nop
|
|
8003a12: e7fd b.n 8003a10 <BusFault_Handler+0x4>
|
|
|
|
08003a14 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8003a14: b480 push {r7}
|
|
8003a16: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8003a18: bf00 nop
|
|
8003a1a: e7fd b.n 8003a18 <UsageFault_Handler+0x4>
|
|
|
|
08003a1c <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8003a1c: b480 push {r7}
|
|
8003a1e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8003a20: bf00 nop
|
|
8003a22: 46bd mov sp, r7
|
|
8003a24: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003a28: 4770 bx lr
|
|
|
|
08003a2a <EXTI9_5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI line[9:5] interrupts.
|
|
*/
|
|
void EXTI9_5_IRQHandler(void)
|
|
{
|
|
8003a2a: b580 push {r7, lr}
|
|
8003a2c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI9_5_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI9_5_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(SPSGRF_915_GPIO3_EXTI5_Pin);
|
|
8003a2e: 2020 movs r0, #32
|
|
8003a30: f000 fed2 bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(SPBTLE_RF_IRQ_EXTI6_Pin);
|
|
8003a34: 2040 movs r0, #64 @ 0x40
|
|
8003a36: f000 fecf bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(VL53L0X_GPIO1_EXTI7_Pin);
|
|
8003a3a: 2080 movs r0, #128 @ 0x80
|
|
8003a3c: f000 fecc bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(LSM3MDL_DRDY_EXTI8_Pin);
|
|
8003a40: f44f 7080 mov.w r0, #256 @ 0x100
|
|
8003a44: f000 fec8 bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI9_5_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI9_5_IRQn 1 */
|
|
}
|
|
8003a48: bf00 nop
|
|
8003a4a: bd80 pop {r7, pc}
|
|
|
|
08003a4c <TIM1_TRG_COM_TIM17_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
|
|
*/
|
|
void TIM1_TRG_COM_TIM17_IRQHandler(void)
|
|
{
|
|
8003a4c: b580 push {r7, lr}
|
|
8003a4e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
|
|
|
|
/* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim17);
|
|
8003a50: 4802 ldr r0, [pc, #8] @ (8003a5c <TIM1_TRG_COM_TIM17_IRQHandler+0x10>)
|
|
8003a52: f004 fe9f bl 8008794 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
|
|
|
|
/* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
|
|
}
|
|
8003a56: bf00 nop
|
|
8003a58: bd80 pop {r7, pc}
|
|
8003a5a: bf00 nop
|
|
8003a5c: 20001294 .word 0x20001294
|
|
|
|
08003a60 <USART1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART1 global interrupt.
|
|
*/
|
|
void USART1_IRQHandler(void)
|
|
{
|
|
8003a60: b580 push {r7, lr}
|
|
8003a62: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART1_IRQn 0 */
|
|
|
|
/* USER CODE END USART1_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart1);
|
|
8003a64: 4802 ldr r0, [pc, #8] @ (8003a70 <USART1_IRQHandler+0x10>)
|
|
8003a66: f005 f9ff bl 8008e68 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART1_IRQn 1 */
|
|
|
|
/* USER CODE END USART1_IRQn 1 */
|
|
}
|
|
8003a6a: bf00 nop
|
|
8003a6c: bd80 pop {r7, pc}
|
|
8003a6e: bf00 nop
|
|
8003a70: 20000c98 .word 0x20000c98
|
|
|
|
08003a74 <EXTI15_10_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI line[15:10] interrupts.
|
|
*/
|
|
void EXTI15_10_IRQHandler(void)
|
|
{
|
|
8003a74: b580 push {r7, lr}
|
|
8003a76: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI15_10_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(LPS22HB_INT_DRDY_EXTI0_Pin);
|
|
8003a78: f44f 6080 mov.w r0, #1024 @ 0x400
|
|
8003a7c: f000 feac bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(LSM6DSL_INT1_EXTI11_Pin);
|
|
8003a80: f44f 6000 mov.w r0, #2048 @ 0x800
|
|
8003a84: f000 fea8 bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(BUTTON_EXTI13_Pin);
|
|
8003a88: f44f 5000 mov.w r0, #8192 @ 0x2000
|
|
8003a8c: f000 fea4 bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(ARD_D2_Pin);
|
|
8003a90: f44f 4080 mov.w r0, #16384 @ 0x4000
|
|
8003a94: f000 fea0 bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(HTS221_DRDY_EXTI15_Pin);
|
|
8003a98: f44f 4000 mov.w r0, #32768 @ 0x8000
|
|
8003a9c: f000 fe9c bl 80047d8 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI15_10_IRQn 1 */
|
|
}
|
|
8003aa0: bf00 nop
|
|
8003aa2: bd80 pop {r7, pc}
|
|
|
|
08003aa4 <_getpid>:
|
|
void initialise_monitor_handles()
|
|
{
|
|
}
|
|
|
|
int _getpid(void)
|
|
{
|
|
8003aa4: b480 push {r7}
|
|
8003aa6: af00 add r7, sp, #0
|
|
return 1;
|
|
8003aa8: 2301 movs r3, #1
|
|
}
|
|
8003aaa: 4618 mov r0, r3
|
|
8003aac: 46bd mov sp, r7
|
|
8003aae: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003ab2: 4770 bx lr
|
|
|
|
08003ab4 <_kill>:
|
|
|
|
int _kill(int pid, int sig)
|
|
{
|
|
8003ab4: b580 push {r7, lr}
|
|
8003ab6: b082 sub sp, #8
|
|
8003ab8: af00 add r7, sp, #0
|
|
8003aba: 6078 str r0, [r7, #4]
|
|
8003abc: 6039 str r1, [r7, #0]
|
|
(void)pid;
|
|
(void)sig;
|
|
errno = EINVAL;
|
|
8003abe: f00c fdfb bl 80106b8 <__errno>
|
|
8003ac2: 4603 mov r3, r0
|
|
8003ac4: 2216 movs r2, #22
|
|
8003ac6: 601a str r2, [r3, #0]
|
|
return -1;
|
|
8003ac8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
8003acc: 4618 mov r0, r3
|
|
8003ace: 3708 adds r7, #8
|
|
8003ad0: 46bd mov sp, r7
|
|
8003ad2: bd80 pop {r7, pc}
|
|
|
|
08003ad4 <_exit>:
|
|
|
|
void _exit (int status)
|
|
{
|
|
8003ad4: b580 push {r7, lr}
|
|
8003ad6: b082 sub sp, #8
|
|
8003ad8: af00 add r7, sp, #0
|
|
8003ada: 6078 str r0, [r7, #4]
|
|
_kill(status, -1);
|
|
8003adc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8003ae0: 6878 ldr r0, [r7, #4]
|
|
8003ae2: f7ff ffe7 bl 8003ab4 <_kill>
|
|
while (1) {} /* Make sure we hang here */
|
|
8003ae6: bf00 nop
|
|
8003ae8: e7fd b.n 8003ae6 <_exit+0x12>
|
|
|
|
08003aea <_read>:
|
|
}
|
|
|
|
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
|
{
|
|
8003aea: b580 push {r7, lr}
|
|
8003aec: b086 sub sp, #24
|
|
8003aee: af00 add r7, sp, #0
|
|
8003af0: 60f8 str r0, [r7, #12]
|
|
8003af2: 60b9 str r1, [r7, #8]
|
|
8003af4: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8003af6: 2300 movs r3, #0
|
|
8003af8: 617b str r3, [r7, #20]
|
|
8003afa: e00a b.n 8003b12 <_read+0x28>
|
|
{
|
|
*ptr++ = __io_getchar();
|
|
8003afc: f7ff fbfe bl 80032fc <__io_getchar>
|
|
8003b00: 4601 mov r1, r0
|
|
8003b02: 68bb ldr r3, [r7, #8]
|
|
8003b04: 1c5a adds r2, r3, #1
|
|
8003b06: 60ba str r2, [r7, #8]
|
|
8003b08: b2ca uxtb r2, r1
|
|
8003b0a: 701a strb r2, [r3, #0]
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8003b0c: 697b ldr r3, [r7, #20]
|
|
8003b0e: 3301 adds r3, #1
|
|
8003b10: 617b str r3, [r7, #20]
|
|
8003b12: 697a ldr r2, [r7, #20]
|
|
8003b14: 687b ldr r3, [r7, #4]
|
|
8003b16: 429a cmp r2, r3
|
|
8003b18: dbf0 blt.n 8003afc <_read+0x12>
|
|
}
|
|
|
|
return len;
|
|
8003b1a: 687b ldr r3, [r7, #4]
|
|
}
|
|
8003b1c: 4618 mov r0, r3
|
|
8003b1e: 3718 adds r7, #24
|
|
8003b20: 46bd mov sp, r7
|
|
8003b22: bd80 pop {r7, pc}
|
|
|
|
08003b24 <_write>:
|
|
|
|
__attribute__((weak)) int _write(int file, char *ptr, int len)
|
|
{
|
|
8003b24: b580 push {r7, lr}
|
|
8003b26: b086 sub sp, #24
|
|
8003b28: af00 add r7, sp, #0
|
|
8003b2a: 60f8 str r0, [r7, #12]
|
|
8003b2c: 60b9 str r1, [r7, #8]
|
|
8003b2e: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8003b30: 2300 movs r3, #0
|
|
8003b32: 617b str r3, [r7, #20]
|
|
8003b34: e009 b.n 8003b4a <_write+0x26>
|
|
{
|
|
__io_putchar(*ptr++);
|
|
8003b36: 68bb ldr r3, [r7, #8]
|
|
8003b38: 1c5a adds r2, r3, #1
|
|
8003b3a: 60ba str r2, [r7, #8]
|
|
8003b3c: 781b ldrb r3, [r3, #0]
|
|
8003b3e: 4618 mov r0, r3
|
|
8003b40: f7ff fbc0 bl 80032c4 <__io_putchar>
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8003b44: 697b ldr r3, [r7, #20]
|
|
8003b46: 3301 adds r3, #1
|
|
8003b48: 617b str r3, [r7, #20]
|
|
8003b4a: 697a ldr r2, [r7, #20]
|
|
8003b4c: 687b ldr r3, [r7, #4]
|
|
8003b4e: 429a cmp r2, r3
|
|
8003b50: dbf1 blt.n 8003b36 <_write+0x12>
|
|
}
|
|
return len;
|
|
8003b52: 687b ldr r3, [r7, #4]
|
|
}
|
|
8003b54: 4618 mov r0, r3
|
|
8003b56: 3718 adds r7, #24
|
|
8003b58: 46bd mov sp, r7
|
|
8003b5a: bd80 pop {r7, pc}
|
|
|
|
08003b5c <_close>:
|
|
|
|
int _close(int file)
|
|
{
|
|
8003b5c: b480 push {r7}
|
|
8003b5e: b083 sub sp, #12
|
|
8003b60: af00 add r7, sp, #0
|
|
8003b62: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return -1;
|
|
8003b64: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
8003b68: 4618 mov r0, r3
|
|
8003b6a: 370c adds r7, #12
|
|
8003b6c: 46bd mov sp, r7
|
|
8003b6e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003b72: 4770 bx lr
|
|
|
|
08003b74 <_fstat>:
|
|
|
|
|
|
int _fstat(int file, struct stat *st)
|
|
{
|
|
8003b74: b480 push {r7}
|
|
8003b76: b083 sub sp, #12
|
|
8003b78: af00 add r7, sp, #0
|
|
8003b7a: 6078 str r0, [r7, #4]
|
|
8003b7c: 6039 str r1, [r7, #0]
|
|
(void)file;
|
|
st->st_mode = S_IFCHR;
|
|
8003b7e: 683b ldr r3, [r7, #0]
|
|
8003b80: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
8003b84: 605a str r2, [r3, #4]
|
|
return 0;
|
|
8003b86: 2300 movs r3, #0
|
|
}
|
|
8003b88: 4618 mov r0, r3
|
|
8003b8a: 370c adds r7, #12
|
|
8003b8c: 46bd mov sp, r7
|
|
8003b8e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003b92: 4770 bx lr
|
|
|
|
08003b94 <_isatty>:
|
|
|
|
int _isatty(int file)
|
|
{
|
|
8003b94: b480 push {r7}
|
|
8003b96: b083 sub sp, #12
|
|
8003b98: af00 add r7, sp, #0
|
|
8003b9a: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return 1;
|
|
8003b9c: 2301 movs r3, #1
|
|
}
|
|
8003b9e: 4618 mov r0, r3
|
|
8003ba0: 370c adds r7, #12
|
|
8003ba2: 46bd mov sp, r7
|
|
8003ba4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003ba8: 4770 bx lr
|
|
|
|
08003baa <_lseek>:
|
|
|
|
int _lseek(int file, int ptr, int dir)
|
|
{
|
|
8003baa: b480 push {r7}
|
|
8003bac: b085 sub sp, #20
|
|
8003bae: af00 add r7, sp, #0
|
|
8003bb0: 60f8 str r0, [r7, #12]
|
|
8003bb2: 60b9 str r1, [r7, #8]
|
|
8003bb4: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
(void)ptr;
|
|
(void)dir;
|
|
return 0;
|
|
8003bb6: 2300 movs r3, #0
|
|
}
|
|
8003bb8: 4618 mov r0, r3
|
|
8003bba: 3714 adds r7, #20
|
|
8003bbc: 46bd mov sp, r7
|
|
8003bbe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003bc2: 4770 bx lr
|
|
|
|
08003bc4 <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
8003bc4: b580 push {r7, lr}
|
|
8003bc6: b086 sub sp, #24
|
|
8003bc8: af00 add r7, sp, #0
|
|
8003bca: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
8003bcc: 4a14 ldr r2, [pc, #80] @ (8003c20 <_sbrk+0x5c>)
|
|
8003bce: 4b15 ldr r3, [pc, #84] @ (8003c24 <_sbrk+0x60>)
|
|
8003bd0: 1ad3 subs r3, r2, r3
|
|
8003bd2: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
8003bd4: 697b ldr r3, [r7, #20]
|
|
8003bd6: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
8003bd8: 4b13 ldr r3, [pc, #76] @ (8003c28 <_sbrk+0x64>)
|
|
8003bda: 681b ldr r3, [r3, #0]
|
|
8003bdc: 2b00 cmp r3, #0
|
|
8003bde: d102 bne.n 8003be6 <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
8003be0: 4b11 ldr r3, [pc, #68] @ (8003c28 <_sbrk+0x64>)
|
|
8003be2: 4a12 ldr r2, [pc, #72] @ (8003c2c <_sbrk+0x68>)
|
|
8003be4: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
8003be6: 4b10 ldr r3, [pc, #64] @ (8003c28 <_sbrk+0x64>)
|
|
8003be8: 681a ldr r2, [r3, #0]
|
|
8003bea: 687b ldr r3, [r7, #4]
|
|
8003bec: 4413 add r3, r2
|
|
8003bee: 693a ldr r2, [r7, #16]
|
|
8003bf0: 429a cmp r2, r3
|
|
8003bf2: d207 bcs.n 8003c04 <_sbrk+0x40>
|
|
{
|
|
errno = ENOMEM;
|
|
8003bf4: f00c fd60 bl 80106b8 <__errno>
|
|
8003bf8: 4603 mov r3, r0
|
|
8003bfa: 220c movs r2, #12
|
|
8003bfc: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
8003bfe: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8003c02: e009 b.n 8003c18 <_sbrk+0x54>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
8003c04: 4b08 ldr r3, [pc, #32] @ (8003c28 <_sbrk+0x64>)
|
|
8003c06: 681b ldr r3, [r3, #0]
|
|
8003c08: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
8003c0a: 4b07 ldr r3, [pc, #28] @ (8003c28 <_sbrk+0x64>)
|
|
8003c0c: 681a ldr r2, [r3, #0]
|
|
8003c0e: 687b ldr r3, [r7, #4]
|
|
8003c10: 4413 add r3, r2
|
|
8003c12: 4a05 ldr r2, [pc, #20] @ (8003c28 <_sbrk+0x64>)
|
|
8003c14: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
8003c16: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8003c18: 4618 mov r0, r3
|
|
8003c1a: 3718 adds r7, #24
|
|
8003c1c: 46bd mov sp, r7
|
|
8003c1e: bd80 pop {r7, pc}
|
|
8003c20: 20018000 .word 0x20018000
|
|
8003c24: 00000400 .word 0x00000400
|
|
8003c28: 200012e0 .word 0x200012e0
|
|
8003c2c: 200036d8 .word 0x200036d8
|
|
|
|
08003c30 <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
8003c30: b480 push {r7}
|
|
8003c32: af00 add r7, sp, #0
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
|
#endif
|
|
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
|
8003c34: 4b06 ldr r3, [pc, #24] @ (8003c50 <SystemInit+0x20>)
|
|
8003c36: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003c3a: 4a05 ldr r2, [pc, #20] @ (8003c50 <SystemInit+0x20>)
|
|
8003c3c: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8003c40: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
#endif
|
|
}
|
|
8003c44: bf00 nop
|
|
8003c46: 46bd mov sp, r7
|
|
8003c48: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003c4c: 4770 bx lr
|
|
8003c4e: bf00 nop
|
|
8003c50: e000ed00 .word 0xe000ed00
|
|
|
|
08003c54 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8003c54: f8df d034 ldr.w sp, [pc, #52] @ 8003c8c <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8003c58: f7ff ffea bl 8003c30 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8003c5c: 480c ldr r0, [pc, #48] @ (8003c90 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
8003c5e: 490d ldr r1, [pc, #52] @ (8003c94 <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8003c60: 4a0d ldr r2, [pc, #52] @ (8003c98 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
8003c62: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8003c64: e002 b.n 8003c6c <LoopCopyDataInit>
|
|
|
|
08003c66 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8003c66: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8003c68: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8003c6a: 3304 adds r3, #4
|
|
|
|
08003c6c <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8003c6c: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8003c6e: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8003c70: d3f9 bcc.n 8003c66 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8003c72: 4a0a ldr r2, [pc, #40] @ (8003c9c <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
8003c74: 4c0a ldr r4, [pc, #40] @ (8003ca0 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
8003c76: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8003c78: e001 b.n 8003c7e <LoopFillZerobss>
|
|
|
|
08003c7a <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8003c7a: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8003c7c: 3204 adds r2, #4
|
|
|
|
08003c7e <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8003c7e: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8003c80: d3fb bcc.n 8003c7a <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8003c82: f00c fd1f bl 80106c4 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8003c86: f7fe ff03 bl 8002a90 <main>
|
|
|
|
08003c8a <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
8003c8a: e7fe b.n 8003c8a <LoopForever>
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8003c8c: 20018000 .word 0x20018000
|
|
ldr r0, =_sdata
|
|
8003c90: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8003c94: 2000029c .word 0x2000029c
|
|
ldr r2, =_sidata
|
|
8003c98: 08014c1c .word 0x08014c1c
|
|
ldr r2, =_sbss
|
|
8003c9c: 2000029c .word 0x2000029c
|
|
ldr r4, =_ebss
|
|
8003ca0: 200036d8 .word 0x200036d8
|
|
|
|
08003ca4 <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8003ca4: e7fe b.n 8003ca4 <ADC1_2_IRQHandler>
|
|
|
|
08003ca6 <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8003ca6: b580 push {r7, lr}
|
|
8003ca8: b082 sub sp, #8
|
|
8003caa: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003cac: 2300 movs r3, #0
|
|
8003cae: 71fb strb r3, [r7, #7]
|
|
#if (PREFETCH_ENABLE != 0)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8003cb0: 2003 movs r0, #3
|
|
8003cb2: f000 f902 bl 8003eba <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
8003cb6: 2000 movs r0, #0
|
|
8003cb8: f7ff fe2e bl 8003918 <HAL_InitTick>
|
|
8003cbc: 4603 mov r3, r0
|
|
8003cbe: 2b00 cmp r3, #0
|
|
8003cc0: d002 beq.n 8003cc8 <HAL_Init+0x22>
|
|
{
|
|
status = HAL_ERROR;
|
|
8003cc2: 2301 movs r3, #1
|
|
8003cc4: 71fb strb r3, [r7, #7]
|
|
8003cc6: e001 b.n 8003ccc <HAL_Init+0x26>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8003cc8: f7ff fb2a bl 8003320 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8003ccc: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8003cce: 4618 mov r0, r3
|
|
8003cd0: 3708 adds r7, #8
|
|
8003cd2: 46bd mov sp, r7
|
|
8003cd4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08003cd8 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8003cd8: b480 push {r7}
|
|
8003cda: af00 add r7, sp, #0
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
8003cdc: 4b06 ldr r3, [pc, #24] @ (8003cf8 <HAL_IncTick+0x20>)
|
|
8003cde: 781b ldrb r3, [r3, #0]
|
|
8003ce0: 461a mov r2, r3
|
|
8003ce2: 4b06 ldr r3, [pc, #24] @ (8003cfc <HAL_IncTick+0x24>)
|
|
8003ce4: 681b ldr r3, [r3, #0]
|
|
8003ce6: 4413 add r3, r2
|
|
8003ce8: 4a04 ldr r2, [pc, #16] @ (8003cfc <HAL_IncTick+0x24>)
|
|
8003cea: 6013 str r3, [r2, #0]
|
|
}
|
|
8003cec: bf00 nop
|
|
8003cee: 46bd mov sp, r7
|
|
8003cf0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003cf4: 4770 bx lr
|
|
8003cf6: bf00 nop
|
|
8003cf8: 200000cc .word 0x200000cc
|
|
8003cfc: 200012e4 .word 0x200012e4
|
|
|
|
08003d00 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8003d00: b480 push {r7}
|
|
8003d02: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8003d04: 4b03 ldr r3, [pc, #12] @ (8003d14 <HAL_GetTick+0x14>)
|
|
8003d06: 681b ldr r3, [r3, #0]
|
|
}
|
|
8003d08: 4618 mov r0, r3
|
|
8003d0a: 46bd mov sp, r7
|
|
8003d0c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003d10: 4770 bx lr
|
|
8003d12: bf00 nop
|
|
8003d14: 200012e4 .word 0x200012e4
|
|
|
|
08003d18 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8003d18: b580 push {r7, lr}
|
|
8003d1a: b084 sub sp, #16
|
|
8003d1c: af00 add r7, sp, #0
|
|
8003d1e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8003d20: f7ff ffee bl 8003d00 <HAL_GetTick>
|
|
8003d24: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8003d26: 687b ldr r3, [r7, #4]
|
|
8003d28: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a period to guaranty minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8003d2a: 68fb ldr r3, [r7, #12]
|
|
8003d2c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8003d30: d005 beq.n 8003d3e <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)uwTickFreq;
|
|
8003d32: 4b0a ldr r3, [pc, #40] @ (8003d5c <HAL_Delay+0x44>)
|
|
8003d34: 781b ldrb r3, [r3, #0]
|
|
8003d36: 461a mov r2, r3
|
|
8003d38: 68fb ldr r3, [r7, #12]
|
|
8003d3a: 4413 add r3, r2
|
|
8003d3c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
8003d3e: bf00 nop
|
|
8003d40: f7ff ffde bl 8003d00 <HAL_GetTick>
|
|
8003d44: 4602 mov r2, r0
|
|
8003d46: 68bb ldr r3, [r7, #8]
|
|
8003d48: 1ad3 subs r3, r2, r3
|
|
8003d4a: 68fa ldr r2, [r7, #12]
|
|
8003d4c: 429a cmp r2, r3
|
|
8003d4e: d8f7 bhi.n 8003d40 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8003d50: bf00 nop
|
|
8003d52: bf00 nop
|
|
8003d54: 3710 adds r7, #16
|
|
8003d56: 46bd mov sp, r7
|
|
8003d58: bd80 pop {r7, pc}
|
|
8003d5a: bf00 nop
|
|
8003d5c: 200000cc .word 0x200000cc
|
|
|
|
08003d60 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8003d60: b480 push {r7}
|
|
8003d62: b085 sub sp, #20
|
|
8003d64: af00 add r7, sp, #0
|
|
8003d66: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8003d68: 687b ldr r3, [r7, #4]
|
|
8003d6a: f003 0307 and.w r3, r3, #7
|
|
8003d6e: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8003d70: 4b0c ldr r3, [pc, #48] @ (8003da4 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8003d72: 68db ldr r3, [r3, #12]
|
|
8003d74: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8003d76: 68ba ldr r2, [r7, #8]
|
|
8003d78: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8003d7c: 4013 ands r3, r2
|
|
8003d7e: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
8003d80: 68fb ldr r3, [r7, #12]
|
|
8003d82: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8003d84: 68bb ldr r3, [r7, #8]
|
|
8003d86: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8003d88: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
8003d8c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8003d90: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
8003d92: 4a04 ldr r2, [pc, #16] @ (8003da4 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8003d94: 68bb ldr r3, [r7, #8]
|
|
8003d96: 60d3 str r3, [r2, #12]
|
|
}
|
|
8003d98: bf00 nop
|
|
8003d9a: 3714 adds r7, #20
|
|
8003d9c: 46bd mov sp, r7
|
|
8003d9e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003da2: 4770 bx lr
|
|
8003da4: e000ed00 .word 0xe000ed00
|
|
|
|
08003da8 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8003da8: b480 push {r7}
|
|
8003daa: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8003dac: 4b04 ldr r3, [pc, #16] @ (8003dc0 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8003dae: 68db ldr r3, [r3, #12]
|
|
8003db0: 0a1b lsrs r3, r3, #8
|
|
8003db2: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8003db6: 4618 mov r0, r3
|
|
8003db8: 46bd mov sp, r7
|
|
8003dba: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003dbe: 4770 bx lr
|
|
8003dc0: e000ed00 .word 0xe000ed00
|
|
|
|
08003dc4 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8003dc4: b480 push {r7}
|
|
8003dc6: b083 sub sp, #12
|
|
8003dc8: af00 add r7, sp, #0
|
|
8003dca: 4603 mov r3, r0
|
|
8003dcc: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8003dce: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003dd2: 2b00 cmp r3, #0
|
|
8003dd4: db0b blt.n 8003dee <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8003dd6: 79fb ldrb r3, [r7, #7]
|
|
8003dd8: f003 021f and.w r2, r3, #31
|
|
8003ddc: 4907 ldr r1, [pc, #28] @ (8003dfc <__NVIC_EnableIRQ+0x38>)
|
|
8003dde: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003de2: 095b lsrs r3, r3, #5
|
|
8003de4: 2001 movs r0, #1
|
|
8003de6: fa00 f202 lsl.w r2, r0, r2
|
|
8003dea: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
8003dee: bf00 nop
|
|
8003df0: 370c adds r7, #12
|
|
8003df2: 46bd mov sp, r7
|
|
8003df4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003df8: 4770 bx lr
|
|
8003dfa: bf00 nop
|
|
8003dfc: e000e100 .word 0xe000e100
|
|
|
|
08003e00 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8003e00: b480 push {r7}
|
|
8003e02: b083 sub sp, #12
|
|
8003e04: af00 add r7, sp, #0
|
|
8003e06: 4603 mov r3, r0
|
|
8003e08: 6039 str r1, [r7, #0]
|
|
8003e0a: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8003e0c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003e10: 2b00 cmp r3, #0
|
|
8003e12: db0a blt.n 8003e2a <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8003e14: 683b ldr r3, [r7, #0]
|
|
8003e16: b2da uxtb r2, r3
|
|
8003e18: 490c ldr r1, [pc, #48] @ (8003e4c <__NVIC_SetPriority+0x4c>)
|
|
8003e1a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003e1e: 0112 lsls r2, r2, #4
|
|
8003e20: b2d2 uxtb r2, r2
|
|
8003e22: 440b add r3, r1
|
|
8003e24: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8003e28: e00a b.n 8003e40 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8003e2a: 683b ldr r3, [r7, #0]
|
|
8003e2c: b2da uxtb r2, r3
|
|
8003e2e: 4908 ldr r1, [pc, #32] @ (8003e50 <__NVIC_SetPriority+0x50>)
|
|
8003e30: 79fb ldrb r3, [r7, #7]
|
|
8003e32: f003 030f and.w r3, r3, #15
|
|
8003e36: 3b04 subs r3, #4
|
|
8003e38: 0112 lsls r2, r2, #4
|
|
8003e3a: b2d2 uxtb r2, r2
|
|
8003e3c: 440b add r3, r1
|
|
8003e3e: 761a strb r2, [r3, #24]
|
|
}
|
|
8003e40: bf00 nop
|
|
8003e42: 370c adds r7, #12
|
|
8003e44: 46bd mov sp, r7
|
|
8003e46: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003e4a: 4770 bx lr
|
|
8003e4c: e000e100 .word 0xe000e100
|
|
8003e50: e000ed00 .word 0xe000ed00
|
|
|
|
08003e54 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8003e54: b480 push {r7}
|
|
8003e56: b089 sub sp, #36 @ 0x24
|
|
8003e58: af00 add r7, sp, #0
|
|
8003e5a: 60f8 str r0, [r7, #12]
|
|
8003e5c: 60b9 str r1, [r7, #8]
|
|
8003e5e: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8003e60: 68fb ldr r3, [r7, #12]
|
|
8003e62: f003 0307 and.w r3, r3, #7
|
|
8003e66: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8003e68: 69fb ldr r3, [r7, #28]
|
|
8003e6a: f1c3 0307 rsb r3, r3, #7
|
|
8003e6e: 2b04 cmp r3, #4
|
|
8003e70: bf28 it cs
|
|
8003e72: 2304 movcs r3, #4
|
|
8003e74: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8003e76: 69fb ldr r3, [r7, #28]
|
|
8003e78: 3304 adds r3, #4
|
|
8003e7a: 2b06 cmp r3, #6
|
|
8003e7c: d902 bls.n 8003e84 <NVIC_EncodePriority+0x30>
|
|
8003e7e: 69fb ldr r3, [r7, #28]
|
|
8003e80: 3b03 subs r3, #3
|
|
8003e82: e000 b.n 8003e86 <NVIC_EncodePriority+0x32>
|
|
8003e84: 2300 movs r3, #0
|
|
8003e86: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8003e88: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8003e8c: 69bb ldr r3, [r7, #24]
|
|
8003e8e: fa02 f303 lsl.w r3, r2, r3
|
|
8003e92: 43da mvns r2, r3
|
|
8003e94: 68bb ldr r3, [r7, #8]
|
|
8003e96: 401a ands r2, r3
|
|
8003e98: 697b ldr r3, [r7, #20]
|
|
8003e9a: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8003e9c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8003ea0: 697b ldr r3, [r7, #20]
|
|
8003ea2: fa01 f303 lsl.w r3, r1, r3
|
|
8003ea6: 43d9 mvns r1, r3
|
|
8003ea8: 687b ldr r3, [r7, #4]
|
|
8003eaa: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8003eac: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8003eae: 4618 mov r0, r3
|
|
8003eb0: 3724 adds r7, #36 @ 0x24
|
|
8003eb2: 46bd mov sp, r7
|
|
8003eb4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003eb8: 4770 bx lr
|
|
|
|
08003eba <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8003eba: b580 push {r7, lr}
|
|
8003ebc: b082 sub sp, #8
|
|
8003ebe: af00 add r7, sp, #0
|
|
8003ec0: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8003ec2: 6878 ldr r0, [r7, #4]
|
|
8003ec4: f7ff ff4c bl 8003d60 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8003ec8: bf00 nop
|
|
8003eca: 3708 adds r7, #8
|
|
8003ecc: 46bd mov sp, r7
|
|
8003ece: bd80 pop {r7, pc}
|
|
|
|
08003ed0 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8003ed0: b580 push {r7, lr}
|
|
8003ed2: b086 sub sp, #24
|
|
8003ed4: af00 add r7, sp, #0
|
|
8003ed6: 4603 mov r3, r0
|
|
8003ed8: 60b9 str r1, [r7, #8]
|
|
8003eda: 607a str r2, [r7, #4]
|
|
8003edc: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8003ede: 2300 movs r3, #0
|
|
8003ee0: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8003ee2: f7ff ff61 bl 8003da8 <__NVIC_GetPriorityGrouping>
|
|
8003ee6: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8003ee8: 687a ldr r2, [r7, #4]
|
|
8003eea: 68b9 ldr r1, [r7, #8]
|
|
8003eec: 6978 ldr r0, [r7, #20]
|
|
8003eee: f7ff ffb1 bl 8003e54 <NVIC_EncodePriority>
|
|
8003ef2: 4602 mov r2, r0
|
|
8003ef4: f997 300f ldrsb.w r3, [r7, #15]
|
|
8003ef8: 4611 mov r1, r2
|
|
8003efa: 4618 mov r0, r3
|
|
8003efc: f7ff ff80 bl 8003e00 <__NVIC_SetPriority>
|
|
}
|
|
8003f00: bf00 nop
|
|
8003f02: 3718 adds r7, #24
|
|
8003f04: 46bd mov sp, r7
|
|
8003f06: bd80 pop {r7, pc}
|
|
|
|
08003f08 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8003f08: b580 push {r7, lr}
|
|
8003f0a: b082 sub sp, #8
|
|
8003f0c: af00 add r7, sp, #0
|
|
8003f0e: 4603 mov r3, r0
|
|
8003f10: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8003f12: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003f16: 4618 mov r0, r3
|
|
8003f18: f7ff ff54 bl 8003dc4 <__NVIC_EnableIRQ>
|
|
}
|
|
8003f1c: bf00 nop
|
|
8003f1e: 3708 adds r7, #8
|
|
8003f20: 46bd mov sp, r7
|
|
8003f22: bd80 pop {r7, pc}
|
|
|
|
08003f24 <HAL_DFSDM_ChannelInit>:
|
|
* in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
|
|
* @param hdfsdm_channel DFSDM channel handle.
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
|
|
{
|
|
8003f24: b580 push {r7, lr}
|
|
8003f26: b082 sub sp, #8
|
|
8003f28: af00 add r7, sp, #0
|
|
8003f2a: 6078 str r0, [r7, #4]
|
|
/* Check DFSDM Channel handle */
|
|
if (hdfsdm_channel == NULL)
|
|
8003f2c: 687b ldr r3, [r7, #4]
|
|
8003f2e: 2b00 cmp r3, #0
|
|
8003f30: d101 bne.n 8003f36 <HAL_DFSDM_ChannelInit+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003f32: 2301 movs r3, #1
|
|
8003f34: e0ac b.n 8004090 <HAL_DFSDM_ChannelInit+0x16c>
|
|
assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
|
|
assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
|
|
assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
|
|
|
|
/* Check that channel has not been already initialized */
|
|
if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
|
|
8003f36: 687b ldr r3, [r7, #4]
|
|
8003f38: 681b ldr r3, [r3, #0]
|
|
8003f3a: 4618 mov r0, r3
|
|
8003f3c: f000 f8b2 bl 80040a4 <DFSDM_GetChannelFromInstance>
|
|
8003f40: 4603 mov r3, r0
|
|
8003f42: 4a55 ldr r2, [pc, #340] @ (8004098 <HAL_DFSDM_ChannelInit+0x174>)
|
|
8003f44: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8003f48: 2b00 cmp r3, #0
|
|
8003f4a: d001 beq.n 8003f50 <HAL_DFSDM_ChannelInit+0x2c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003f4c: 2301 movs r3, #1
|
|
8003f4e: e09f b.n 8004090 <HAL_DFSDM_ChannelInit+0x16c>
|
|
hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
|
|
}
|
|
hdfsdm_channel->MspInitCallback(hdfsdm_channel);
|
|
#else
|
|
/* Call MSP init function */
|
|
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
|
|
8003f50: 6878 ldr r0, [r7, #4]
|
|
8003f52: f7ff fa0d bl 8003370 <HAL_DFSDM_ChannelMspInit>
|
|
#endif
|
|
|
|
/* Update the channel counter */
|
|
v_dfsdm1ChannelCounter++;
|
|
8003f56: 4b51 ldr r3, [pc, #324] @ (800409c <HAL_DFSDM_ChannelInit+0x178>)
|
|
8003f58: 681b ldr r3, [r3, #0]
|
|
8003f5a: 3301 adds r3, #1
|
|
8003f5c: 4a4f ldr r2, [pc, #316] @ (800409c <HAL_DFSDM_ChannelInit+0x178>)
|
|
8003f5e: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure output serial clock and enable global DFSDM interface only for first channel */
|
|
if (v_dfsdm1ChannelCounter == 1U)
|
|
8003f60: 4b4e ldr r3, [pc, #312] @ (800409c <HAL_DFSDM_ChannelInit+0x178>)
|
|
8003f62: 681b ldr r3, [r3, #0]
|
|
8003f64: 2b01 cmp r3, #1
|
|
8003f66: d125 bne.n 8003fb4 <HAL_DFSDM_ChannelInit+0x90>
|
|
{
|
|
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
|
|
/* Set the output serial clock source */
|
|
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
|
|
8003f68: 4b4d ldr r3, [pc, #308] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003f6a: 681b ldr r3, [r3, #0]
|
|
8003f6c: 4a4c ldr r2, [pc, #304] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003f6e: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8003f72: 6013 str r3, [r2, #0]
|
|
DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
|
|
8003f74: 4b4a ldr r3, [pc, #296] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003f76: 681a ldr r2, [r3, #0]
|
|
8003f78: 687b ldr r3, [r7, #4]
|
|
8003f7a: 689b ldr r3, [r3, #8]
|
|
8003f7c: 4948 ldr r1, [pc, #288] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003f7e: 4313 orrs r3, r2
|
|
8003f80: 600b str r3, [r1, #0]
|
|
|
|
/* Reset clock divider */
|
|
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
|
|
8003f82: 4b47 ldr r3, [pc, #284] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003f84: 681b ldr r3, [r3, #0]
|
|
8003f86: 4a46 ldr r2, [pc, #280] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003f88: f423 037f bic.w r3, r3, #16711680 @ 0xff0000
|
|
8003f8c: 6013 str r3, [r2, #0]
|
|
if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
|
|
8003f8e: 687b ldr r3, [r7, #4]
|
|
8003f90: 791b ldrb r3, [r3, #4]
|
|
8003f92: 2b01 cmp r3, #1
|
|
8003f94: d108 bne.n 8003fa8 <HAL_DFSDM_ChannelInit+0x84>
|
|
{
|
|
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
|
|
/* Set the output clock divider */
|
|
DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
|
|
8003f96: 4b42 ldr r3, [pc, #264] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003f98: 681a ldr r2, [r3, #0]
|
|
8003f9a: 687b ldr r3, [r7, #4]
|
|
8003f9c: 68db ldr r3, [r3, #12]
|
|
8003f9e: 3b01 subs r3, #1
|
|
8003fa0: 041b lsls r3, r3, #16
|
|
8003fa2: 493f ldr r1, [pc, #252] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003fa4: 4313 orrs r3, r2
|
|
8003fa6: 600b str r3, [r1, #0]
|
|
DFSDM_CHCFGR1_CKOUTDIV_Pos);
|
|
}
|
|
|
|
/* enable the DFSDM global interface */
|
|
DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
|
|
8003fa8: 4b3d ldr r3, [pc, #244] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003faa: 681b ldr r3, [r3, #0]
|
|
8003fac: 4a3c ldr r2, [pc, #240] @ (80040a0 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003fae: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8003fb2: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
/* Set channel input parameters */
|
|
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
|
|
8003fb4: 687b ldr r3, [r7, #4]
|
|
8003fb6: 681b ldr r3, [r3, #0]
|
|
8003fb8: 681a ldr r2, [r3, #0]
|
|
8003fba: 687b ldr r3, [r7, #4]
|
|
8003fbc: 681b ldr r3, [r3, #0]
|
|
8003fbe: f422 4271 bic.w r2, r2, #61696 @ 0xf100
|
|
8003fc2: 601a str r2, [r3, #0]
|
|
DFSDM_CHCFGR1_CHINSEL);
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
|
|
8003fc4: 687b ldr r3, [r7, #4]
|
|
8003fc6: 681b ldr r3, [r3, #0]
|
|
8003fc8: 6819 ldr r1, [r3, #0]
|
|
8003fca: 687b ldr r3, [r7, #4]
|
|
8003fcc: 691a ldr r2, [r3, #16]
|
|
hdfsdm_channel->Init.Input.DataPacking |
|
|
8003fce: 687b ldr r3, [r7, #4]
|
|
8003fd0: 695b ldr r3, [r3, #20]
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
|
|
8003fd2: 431a orrs r2, r3
|
|
hdfsdm_channel->Init.Input.Pins);
|
|
8003fd4: 687b ldr r3, [r7, #4]
|
|
8003fd6: 699b ldr r3, [r3, #24]
|
|
hdfsdm_channel->Init.Input.DataPacking |
|
|
8003fd8: 431a orrs r2, r3
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
|
|
8003fda: 687b ldr r3, [r7, #4]
|
|
8003fdc: 681b ldr r3, [r3, #0]
|
|
8003fde: 430a orrs r2, r1
|
|
8003fe0: 601a str r2, [r3, #0]
|
|
|
|
/* Set serial interface parameters */
|
|
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
|
|
8003fe2: 687b ldr r3, [r7, #4]
|
|
8003fe4: 681b ldr r3, [r3, #0]
|
|
8003fe6: 681a ldr r2, [r3, #0]
|
|
8003fe8: 687b ldr r3, [r7, #4]
|
|
8003fea: 681b ldr r3, [r3, #0]
|
|
8003fec: f022 020f bic.w r2, r2, #15
|
|
8003ff0: 601a str r2, [r3, #0]
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
|
|
8003ff2: 687b ldr r3, [r7, #4]
|
|
8003ff4: 681b ldr r3, [r3, #0]
|
|
8003ff6: 6819 ldr r1, [r3, #0]
|
|
8003ff8: 687b ldr r3, [r7, #4]
|
|
8003ffa: 69da ldr r2, [r3, #28]
|
|
hdfsdm_channel->Init.SerialInterface.SpiClock);
|
|
8003ffc: 687b ldr r3, [r7, #4]
|
|
8003ffe: 6a1b ldr r3, [r3, #32]
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
|
|
8004000: 431a orrs r2, r3
|
|
8004002: 687b ldr r3, [r7, #4]
|
|
8004004: 681b ldr r3, [r3, #0]
|
|
8004006: 430a orrs r2, r1
|
|
8004008: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog watchdog parameters */
|
|
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
|
|
800400a: 687b ldr r3, [r7, #4]
|
|
800400c: 681b ldr r3, [r3, #0]
|
|
800400e: 689a ldr r2, [r3, #8]
|
|
8004010: 687b ldr r3, [r7, #4]
|
|
8004012: 681b ldr r3, [r3, #0]
|
|
8004014: f422 025f bic.w r2, r2, #14614528 @ 0xdf0000
|
|
8004018: 609a str r2, [r3, #8]
|
|
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
|
|
800401a: 687b ldr r3, [r7, #4]
|
|
800401c: 681b ldr r3, [r3, #0]
|
|
800401e: 6899 ldr r1, [r3, #8]
|
|
8004020: 687b ldr r3, [r7, #4]
|
|
8004022: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
|
|
8004024: 687b ldr r3, [r7, #4]
|
|
8004026: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004028: 3b01 subs r3, #1
|
|
800402a: 041b lsls r3, r3, #16
|
|
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
|
|
800402c: 431a orrs r2, r3
|
|
800402e: 687b ldr r3, [r7, #4]
|
|
8004030: 681b ldr r3, [r3, #0]
|
|
8004032: 430a orrs r2, r1
|
|
8004034: 609a str r2, [r3, #8]
|
|
|
|
/* Set channel offset and right bit shift */
|
|
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
|
|
8004036: 687b ldr r3, [r7, #4]
|
|
8004038: 681b ldr r3, [r3, #0]
|
|
800403a: 685a ldr r2, [r3, #4]
|
|
800403c: 687b ldr r3, [r7, #4]
|
|
800403e: 681b ldr r3, [r3, #0]
|
|
8004040: f002 0207 and.w r2, r2, #7
|
|
8004044: 605a str r2, [r3, #4]
|
|
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
|
|
8004046: 687b ldr r3, [r7, #4]
|
|
8004048: 681b ldr r3, [r3, #0]
|
|
800404a: 6859 ldr r1, [r3, #4]
|
|
800404c: 687b ldr r3, [r7, #4]
|
|
800404e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004050: 021a lsls r2, r3, #8
|
|
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
|
|
8004052: 687b ldr r3, [r7, #4]
|
|
8004054: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004056: 00db lsls r3, r3, #3
|
|
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
|
|
8004058: 431a orrs r2, r3
|
|
800405a: 687b ldr r3, [r7, #4]
|
|
800405c: 681b ldr r3, [r3, #0]
|
|
800405e: 430a orrs r2, r1
|
|
8004060: 605a str r2, [r3, #4]
|
|
|
|
/* Enable DFSDM channel */
|
|
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
|
|
8004062: 687b ldr r3, [r7, #4]
|
|
8004064: 681b ldr r3, [r3, #0]
|
|
8004066: 681a ldr r2, [r3, #0]
|
|
8004068: 687b ldr r3, [r7, #4]
|
|
800406a: 681b ldr r3, [r3, #0]
|
|
800406c: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
8004070: 601a str r2, [r3, #0]
|
|
|
|
/* Set DFSDM Channel to ready state */
|
|
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
|
|
8004072: 687b ldr r3, [r7, #4]
|
|
8004074: 2201 movs r2, #1
|
|
8004076: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
/* Store channel handle in DFSDM channel handle table */
|
|
a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
|
|
800407a: 687b ldr r3, [r7, #4]
|
|
800407c: 681b ldr r3, [r3, #0]
|
|
800407e: 4618 mov r0, r3
|
|
8004080: f000 f810 bl 80040a4 <DFSDM_GetChannelFromInstance>
|
|
8004084: 4602 mov r2, r0
|
|
8004086: 4904 ldr r1, [pc, #16] @ (8004098 <HAL_DFSDM_ChannelInit+0x174>)
|
|
8004088: 687b ldr r3, [r7, #4]
|
|
800408a: f841 3022 str.w r3, [r1, r2, lsl #2]
|
|
|
|
return HAL_OK;
|
|
800408e: 2300 movs r3, #0
|
|
}
|
|
8004090: 4618 mov r0, r3
|
|
8004092: 3708 adds r7, #8
|
|
8004094: 46bd mov sp, r7
|
|
8004096: bd80 pop {r7, pc}
|
|
8004098: 200012ec .word 0x200012ec
|
|
800409c: 200012e8 .word 0x200012e8
|
|
80040a0: 40016000 .word 0x40016000
|
|
|
|
080040a4 <DFSDM_GetChannelFromInstance>:
|
|
* @brief This function allows to get the channel number from channel instance.
|
|
* @param Instance DFSDM channel instance.
|
|
* @retval Channel number.
|
|
*/
|
|
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
|
|
{
|
|
80040a4: b480 push {r7}
|
|
80040a6: b085 sub sp, #20
|
|
80040a8: af00 add r7, sp, #0
|
|
80040aa: 6078 str r0, [r7, #4]
|
|
uint32_t channel;
|
|
|
|
/* Get channel from instance */
|
|
if (Instance == DFSDM1_Channel0)
|
|
80040ac: 687b ldr r3, [r7, #4]
|
|
80040ae: 4a1c ldr r2, [pc, #112] @ (8004120 <DFSDM_GetChannelFromInstance+0x7c>)
|
|
80040b0: 4293 cmp r3, r2
|
|
80040b2: d102 bne.n 80040ba <DFSDM_GetChannelFromInstance+0x16>
|
|
{
|
|
channel = 0;
|
|
80040b4: 2300 movs r3, #0
|
|
80040b6: 60fb str r3, [r7, #12]
|
|
80040b8: e02b b.n 8004112 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel1)
|
|
80040ba: 687b ldr r3, [r7, #4]
|
|
80040bc: 4a19 ldr r2, [pc, #100] @ (8004124 <DFSDM_GetChannelFromInstance+0x80>)
|
|
80040be: 4293 cmp r3, r2
|
|
80040c0: d102 bne.n 80040c8 <DFSDM_GetChannelFromInstance+0x24>
|
|
{
|
|
channel = 1;
|
|
80040c2: 2301 movs r3, #1
|
|
80040c4: 60fb str r3, [r7, #12]
|
|
80040c6: e024 b.n 8004112 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel2)
|
|
80040c8: 687b ldr r3, [r7, #4]
|
|
80040ca: 4a17 ldr r2, [pc, #92] @ (8004128 <DFSDM_GetChannelFromInstance+0x84>)
|
|
80040cc: 4293 cmp r3, r2
|
|
80040ce: d102 bne.n 80040d6 <DFSDM_GetChannelFromInstance+0x32>
|
|
{
|
|
channel = 2;
|
|
80040d0: 2302 movs r3, #2
|
|
80040d2: 60fb str r3, [r7, #12]
|
|
80040d4: e01d b.n 8004112 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
|
|
defined(STM32L496xx) || defined(STM32L4A6xx) || \
|
|
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
|
else if (Instance == DFSDM1_Channel4)
|
|
80040d6: 687b ldr r3, [r7, #4]
|
|
80040d8: 4a14 ldr r2, [pc, #80] @ (800412c <DFSDM_GetChannelFromInstance+0x88>)
|
|
80040da: 4293 cmp r3, r2
|
|
80040dc: d102 bne.n 80040e4 <DFSDM_GetChannelFromInstance+0x40>
|
|
{
|
|
channel = 4;
|
|
80040de: 2304 movs r3, #4
|
|
80040e0: 60fb str r3, [r7, #12]
|
|
80040e2: e016 b.n 8004112 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel5)
|
|
80040e4: 687b ldr r3, [r7, #4]
|
|
80040e6: 4a12 ldr r2, [pc, #72] @ (8004130 <DFSDM_GetChannelFromInstance+0x8c>)
|
|
80040e8: 4293 cmp r3, r2
|
|
80040ea: d102 bne.n 80040f2 <DFSDM_GetChannelFromInstance+0x4e>
|
|
{
|
|
channel = 5;
|
|
80040ec: 2305 movs r3, #5
|
|
80040ee: 60fb str r3, [r7, #12]
|
|
80040f0: e00f b.n 8004112 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel6)
|
|
80040f2: 687b ldr r3, [r7, #4]
|
|
80040f4: 4a0f ldr r2, [pc, #60] @ (8004134 <DFSDM_GetChannelFromInstance+0x90>)
|
|
80040f6: 4293 cmp r3, r2
|
|
80040f8: d102 bne.n 8004100 <DFSDM_GetChannelFromInstance+0x5c>
|
|
{
|
|
channel = 6;
|
|
80040fa: 2306 movs r3, #6
|
|
80040fc: 60fb str r3, [r7, #12]
|
|
80040fe: e008 b.n 8004112 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel7)
|
|
8004100: 687b ldr r3, [r7, #4]
|
|
8004102: 4a0d ldr r2, [pc, #52] @ (8004138 <DFSDM_GetChannelFromInstance+0x94>)
|
|
8004104: 4293 cmp r3, r2
|
|
8004106: d102 bne.n 800410e <DFSDM_GetChannelFromInstance+0x6a>
|
|
{
|
|
channel = 7;
|
|
8004108: 2307 movs r3, #7
|
|
800410a: 60fb str r3, [r7, #12]
|
|
800410c: e001 b.n 8004112 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
else /* DFSDM1_Channel3 */
|
|
{
|
|
channel = 3;
|
|
800410e: 2303 movs r3, #3
|
|
8004110: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return channel;
|
|
8004112: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8004114: 4618 mov r0, r3
|
|
8004116: 3714 adds r7, #20
|
|
8004118: 46bd mov sp, r7
|
|
800411a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800411e: 4770 bx lr
|
|
8004120: 40016000 .word 0x40016000
|
|
8004124: 40016020 .word 0x40016020
|
|
8004128: 40016040 .word 0x40016040
|
|
800412c: 40016080 .word 0x40016080
|
|
8004130: 400160a0 .word 0x400160a0
|
|
8004134: 400160c0 .word 0x400160c0
|
|
8004138: 400160e0 .word 0x400160e0
|
|
|
|
0800413c <HAL_DMA_Abort>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800413c: b480 push {r7}
|
|
800413e: b085 sub sp, #20
|
|
8004140: af00 add r7, sp, #0
|
|
8004142: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004144: 2300 movs r3, #0
|
|
8004146: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the DMA peripheral state */
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
|
8004148: 687b ldr r3, [r7, #4]
|
|
800414a: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
800414e: b2db uxtb r3, r3
|
|
8004150: 2b02 cmp r3, #2
|
|
8004152: d008 beq.n 8004166 <HAL_DMA_Abort+0x2a>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8004154: 687b ldr r3, [r7, #4]
|
|
8004156: 2204 movs r2, #4
|
|
8004158: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
800415a: 687b ldr r3, [r7, #4]
|
|
800415c: 2200 movs r2, #0
|
|
800415e: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8004162: 2301 movs r3, #1
|
|
8004164: e022 b.n 80041ac <HAL_DMA_Abort+0x70>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8004166: 687b ldr r3, [r7, #4]
|
|
8004168: 681b ldr r3, [r3, #0]
|
|
800416a: 681a ldr r2, [r3, #0]
|
|
800416c: 687b ldr r3, [r7, #4]
|
|
800416e: 681b ldr r3, [r3, #0]
|
|
8004170: f022 020e bic.w r2, r2, #14
|
|
8004174: 601a str r2, [r3, #0]
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8004176: 687b ldr r3, [r7, #4]
|
|
8004178: 681b ldr r3, [r3, #0]
|
|
800417a: 681a ldr r2, [r3, #0]
|
|
800417c: 687b ldr r3, [r7, #4]
|
|
800417e: 681b ldr r3, [r3, #0]
|
|
8004180: f022 0201 bic.w r2, r2, #1
|
|
8004184: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
8004186: 687b ldr r3, [r7, #4]
|
|
8004188: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800418a: f003 021c and.w r2, r3, #28
|
|
800418e: 687b ldr r3, [r7, #4]
|
|
8004190: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004192: 2101 movs r1, #1
|
|
8004194: fa01 f202 lsl.w r2, r1, r2
|
|
8004198: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800419a: 687b ldr r3, [r7, #4]
|
|
800419c: 2201 movs r2, #1
|
|
800419e: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80041a2: 687b ldr r3, [r7, #4]
|
|
80041a4: 2200 movs r2, #0
|
|
80041a6: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return status;
|
|
80041aa: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
}
|
|
80041ac: 4618 mov r0, r3
|
|
80041ae: 3714 adds r7, #20
|
|
80041b0: 46bd mov sp, r7
|
|
80041b2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80041b6: 4770 bx lr
|
|
|
|
080041b8 <HAL_DMA_Abort_IT>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80041b8: b580 push {r7, lr}
|
|
80041ba: b084 sub sp, #16
|
|
80041bc: af00 add r7, sp, #0
|
|
80041be: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80041c0: 2300 movs r3, #0
|
|
80041c2: 73fb strb r3, [r7, #15]
|
|
|
|
if (HAL_DMA_STATE_BUSY != hdma->State)
|
|
80041c4: 687b ldr r3, [r7, #4]
|
|
80041c6: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
80041ca: b2db uxtb r3, r3
|
|
80041cc: 2b02 cmp r3, #2
|
|
80041ce: d005 beq.n 80041dc <HAL_DMA_Abort_IT+0x24>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
80041d0: 687b ldr r3, [r7, #4]
|
|
80041d2: 2204 movs r2, #4
|
|
80041d4: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
status = HAL_ERROR;
|
|
80041d6: 2301 movs r3, #1
|
|
80041d8: 73fb strb r3, [r7, #15]
|
|
80041da: e029 b.n 8004230 <HAL_DMA_Abort_IT+0x78>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
80041dc: 687b ldr r3, [r7, #4]
|
|
80041de: 681b ldr r3, [r3, #0]
|
|
80041e0: 681a ldr r2, [r3, #0]
|
|
80041e2: 687b ldr r3, [r7, #4]
|
|
80041e4: 681b ldr r3, [r3, #0]
|
|
80041e6: f022 020e bic.w r2, r2, #14
|
|
80041ea: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
80041ec: 687b ldr r3, [r7, #4]
|
|
80041ee: 681b ldr r3, [r3, #0]
|
|
80041f0: 681a ldr r2, [r3, #0]
|
|
80041f2: 687b ldr r3, [r7, #4]
|
|
80041f4: 681b ldr r3, [r3, #0]
|
|
80041f6: f022 0201 bic.w r2, r2, #1
|
|
80041fa: 601a str r2, [r3, #0]
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
}
|
|
|
|
#else
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
80041fc: 687b ldr r3, [r7, #4]
|
|
80041fe: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8004200: f003 021c and.w r2, r3, #28
|
|
8004204: 687b ldr r3, [r7, #4]
|
|
8004206: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004208: 2101 movs r1, #1
|
|
800420a: fa01 f202 lsl.w r2, r1, r2
|
|
800420e: 605a str r2, [r3, #4]
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8004210: 687b ldr r3, [r7, #4]
|
|
8004212: 2201 movs r2, #1
|
|
8004214: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8004218: 687b ldr r3, [r7, #4]
|
|
800421a: 2200 movs r2, #0
|
|
800421c: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Call User Abort callback */
|
|
if (hdma->XferAbortCallback != NULL)
|
|
8004220: 687b ldr r3, [r7, #4]
|
|
8004222: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004224: 2b00 cmp r3, #0
|
|
8004226: d003 beq.n 8004230 <HAL_DMA_Abort_IT+0x78>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
8004228: 687b ldr r3, [r7, #4]
|
|
800422a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800422c: 6878 ldr r0, [r7, #4]
|
|
800422e: 4798 blx r3
|
|
}
|
|
}
|
|
return status;
|
|
8004230: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004232: 4618 mov r0, r3
|
|
8004234: 3710 adds r7, #16
|
|
8004236: 46bd mov sp, r7
|
|
8004238: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800423c <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
800423c: b480 push {r7}
|
|
800423e: b087 sub sp, #28
|
|
8004240: af00 add r7, sp, #0
|
|
8004242: 6078 str r0, [r7, #4]
|
|
8004244: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8004246: 2300 movs r3, #0
|
|
8004248: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
800424a: e17f b.n 800454c <HAL_GPIO_Init+0x310>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
800424c: 683b ldr r3, [r7, #0]
|
|
800424e: 681a ldr r2, [r3, #0]
|
|
8004250: 2101 movs r1, #1
|
|
8004252: 697b ldr r3, [r7, #20]
|
|
8004254: fa01 f303 lsl.w r3, r1, r3
|
|
8004258: 4013 ands r3, r2
|
|
800425a: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
800425c: 68fb ldr r3, [r7, #12]
|
|
800425e: 2b00 cmp r3, #0
|
|
8004260: f000 8171 beq.w 8004546 <HAL_GPIO_Init+0x30a>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
8004264: 683b ldr r3, [r7, #0]
|
|
8004266: 685b ldr r3, [r3, #4]
|
|
8004268: f003 0303 and.w r3, r3, #3
|
|
800426c: 2b01 cmp r3, #1
|
|
800426e: d005 beq.n 800427c <HAL_GPIO_Init+0x40>
|
|
8004270: 683b ldr r3, [r7, #0]
|
|
8004272: 685b ldr r3, [r3, #4]
|
|
8004274: f003 0303 and.w r3, r3, #3
|
|
8004278: 2b02 cmp r3, #2
|
|
800427a: d130 bne.n 80042de <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
800427c: 687b ldr r3, [r7, #4]
|
|
800427e: 689b ldr r3, [r3, #8]
|
|
8004280: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
8004282: 697b ldr r3, [r7, #20]
|
|
8004284: 005b lsls r3, r3, #1
|
|
8004286: 2203 movs r2, #3
|
|
8004288: fa02 f303 lsl.w r3, r2, r3
|
|
800428c: 43db mvns r3, r3
|
|
800428e: 693a ldr r2, [r7, #16]
|
|
8004290: 4013 ands r3, r2
|
|
8004292: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
8004294: 683b ldr r3, [r7, #0]
|
|
8004296: 68da ldr r2, [r3, #12]
|
|
8004298: 697b ldr r3, [r7, #20]
|
|
800429a: 005b lsls r3, r3, #1
|
|
800429c: fa02 f303 lsl.w r3, r2, r3
|
|
80042a0: 693a ldr r2, [r7, #16]
|
|
80042a2: 4313 orrs r3, r2
|
|
80042a4: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
80042a6: 687b ldr r3, [r7, #4]
|
|
80042a8: 693a ldr r2, [r7, #16]
|
|
80042aa: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
80042ac: 687b ldr r3, [r7, #4]
|
|
80042ae: 685b ldr r3, [r3, #4]
|
|
80042b0: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
80042b2: 2201 movs r2, #1
|
|
80042b4: 697b ldr r3, [r7, #20]
|
|
80042b6: fa02 f303 lsl.w r3, r2, r3
|
|
80042ba: 43db mvns r3, r3
|
|
80042bc: 693a ldr r2, [r7, #16]
|
|
80042be: 4013 ands r3, r2
|
|
80042c0: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
80042c2: 683b ldr r3, [r7, #0]
|
|
80042c4: 685b ldr r3, [r3, #4]
|
|
80042c6: 091b lsrs r3, r3, #4
|
|
80042c8: f003 0201 and.w r2, r3, #1
|
|
80042cc: 697b ldr r3, [r7, #20]
|
|
80042ce: fa02 f303 lsl.w r3, r2, r3
|
|
80042d2: 693a ldr r2, [r7, #16]
|
|
80042d4: 4313 orrs r3, r2
|
|
80042d6: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
80042d8: 687b ldr r3, [r7, #4]
|
|
80042da: 693a ldr r2, [r7, #16]
|
|
80042dc: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
|
/* In case of Analog mode, check if ADC control mode is selected */
|
|
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
|
|
80042de: 683b ldr r3, [r7, #0]
|
|
80042e0: 685b ldr r3, [r3, #4]
|
|
80042e2: f003 0303 and.w r3, r3, #3
|
|
80042e6: 2b03 cmp r3, #3
|
|
80042e8: d118 bne.n 800431c <HAL_GPIO_Init+0xe0>
|
|
{
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->ASCR;
|
|
80042ea: 687b ldr r3, [r7, #4]
|
|
80042ec: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80042ee: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_ASCR_ASC0 << position) ;
|
|
80042f0: 2201 movs r2, #1
|
|
80042f2: 697b ldr r3, [r7, #20]
|
|
80042f4: fa02 f303 lsl.w r3, r2, r3
|
|
80042f8: 43db mvns r3, r3
|
|
80042fa: 693a ldr r2, [r7, #16]
|
|
80042fc: 4013 ands r3, r2
|
|
80042fe: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
|
|
8004300: 683b ldr r3, [r7, #0]
|
|
8004302: 685b ldr r3, [r3, #4]
|
|
8004304: 08db lsrs r3, r3, #3
|
|
8004306: f003 0201 and.w r2, r3, #1
|
|
800430a: 697b ldr r3, [r7, #20]
|
|
800430c: fa02 f303 lsl.w r3, r2, r3
|
|
8004310: 693a ldr r2, [r7, #16]
|
|
8004312: 4313 orrs r3, r2
|
|
8004314: 613b str r3, [r7, #16]
|
|
GPIOx->ASCR = temp;
|
|
8004316: 687b ldr r3, [r7, #4]
|
|
8004318: 693a ldr r2, [r7, #16]
|
|
800431a: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
800431c: 683b ldr r3, [r7, #0]
|
|
800431e: 685b ldr r3, [r3, #4]
|
|
8004320: f003 0303 and.w r3, r3, #3
|
|
8004324: 2b03 cmp r3, #3
|
|
8004326: d017 beq.n 8004358 <HAL_GPIO_Init+0x11c>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
temp = GPIOx->PUPDR;
|
|
8004328: 687b ldr r3, [r7, #4]
|
|
800432a: 68db ldr r3, [r3, #12]
|
|
800432c: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
800432e: 697b ldr r3, [r7, #20]
|
|
8004330: 005b lsls r3, r3, #1
|
|
8004332: 2203 movs r2, #3
|
|
8004334: fa02 f303 lsl.w r3, r2, r3
|
|
8004338: 43db mvns r3, r3
|
|
800433a: 693a ldr r2, [r7, #16]
|
|
800433c: 4013 ands r3, r2
|
|
800433e: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8004340: 683b ldr r3, [r7, #0]
|
|
8004342: 689a ldr r2, [r3, #8]
|
|
8004344: 697b ldr r3, [r7, #20]
|
|
8004346: 005b lsls r3, r3, #1
|
|
8004348: fa02 f303 lsl.w r3, r2, r3
|
|
800434c: 693a ldr r2, [r7, #16]
|
|
800434e: 4313 orrs r3, r2
|
|
8004350: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8004352: 687b ldr r3, [r7, #4]
|
|
8004354: 693a ldr r2, [r7, #16]
|
|
8004356: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8004358: 683b ldr r3, [r7, #0]
|
|
800435a: 685b ldr r3, [r3, #4]
|
|
800435c: f003 0303 and.w r3, r3, #3
|
|
8004360: 2b02 cmp r3, #2
|
|
8004362: d123 bne.n 80043ac <HAL_GPIO_Init+0x170>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
8004364: 697b ldr r3, [r7, #20]
|
|
8004366: 08da lsrs r2, r3, #3
|
|
8004368: 687b ldr r3, [r7, #4]
|
|
800436a: 3208 adds r2, #8
|
|
800436c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8004370: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8004372: 697b ldr r3, [r7, #20]
|
|
8004374: f003 0307 and.w r3, r3, #7
|
|
8004378: 009b lsls r3, r3, #2
|
|
800437a: 220f movs r2, #15
|
|
800437c: fa02 f303 lsl.w r3, r2, r3
|
|
8004380: 43db mvns r3, r3
|
|
8004382: 693a ldr r2, [r7, #16]
|
|
8004384: 4013 ands r3, r2
|
|
8004386: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
8004388: 683b ldr r3, [r7, #0]
|
|
800438a: 691a ldr r2, [r3, #16]
|
|
800438c: 697b ldr r3, [r7, #20]
|
|
800438e: f003 0307 and.w r3, r3, #7
|
|
8004392: 009b lsls r3, r3, #2
|
|
8004394: fa02 f303 lsl.w r3, r2, r3
|
|
8004398: 693a ldr r2, [r7, #16]
|
|
800439a: 4313 orrs r3, r2
|
|
800439c: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
800439e: 697b ldr r3, [r7, #20]
|
|
80043a0: 08da lsrs r2, r3, #3
|
|
80043a2: 687b ldr r3, [r7, #4]
|
|
80043a4: 3208 adds r2, #8
|
|
80043a6: 6939 ldr r1, [r7, #16]
|
|
80043a8: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80043ac: 687b ldr r3, [r7, #4]
|
|
80043ae: 681b ldr r3, [r3, #0]
|
|
80043b0: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
80043b2: 697b ldr r3, [r7, #20]
|
|
80043b4: 005b lsls r3, r3, #1
|
|
80043b6: 2203 movs r2, #3
|
|
80043b8: fa02 f303 lsl.w r3, r2, r3
|
|
80043bc: 43db mvns r3, r3
|
|
80043be: 693a ldr r2, [r7, #16]
|
|
80043c0: 4013 ands r3, r2
|
|
80043c2: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
80043c4: 683b ldr r3, [r7, #0]
|
|
80043c6: 685b ldr r3, [r3, #4]
|
|
80043c8: f003 0203 and.w r2, r3, #3
|
|
80043cc: 697b ldr r3, [r7, #20]
|
|
80043ce: 005b lsls r3, r3, #1
|
|
80043d0: fa02 f303 lsl.w r3, r2, r3
|
|
80043d4: 693a ldr r2, [r7, #16]
|
|
80043d6: 4313 orrs r3, r2
|
|
80043d8: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
80043da: 687b ldr r3, [r7, #4]
|
|
80043dc: 693a ldr r2, [r7, #16]
|
|
80043de: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
80043e0: 683b ldr r3, [r7, #0]
|
|
80043e2: 685b ldr r3, [r3, #4]
|
|
80043e4: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
80043e8: 2b00 cmp r3, #0
|
|
80043ea: f000 80ac beq.w 8004546 <HAL_GPIO_Init+0x30a>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80043ee: 4b5f ldr r3, [pc, #380] @ (800456c <HAL_GPIO_Init+0x330>)
|
|
80043f0: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80043f2: 4a5e ldr r2, [pc, #376] @ (800456c <HAL_GPIO_Init+0x330>)
|
|
80043f4: f043 0301 orr.w r3, r3, #1
|
|
80043f8: 6613 str r3, [r2, #96] @ 0x60
|
|
80043fa: 4b5c ldr r3, [pc, #368] @ (800456c <HAL_GPIO_Init+0x330>)
|
|
80043fc: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80043fe: f003 0301 and.w r3, r3, #1
|
|
8004402: 60bb str r3, [r7, #8]
|
|
8004404: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
8004406: 4a5a ldr r2, [pc, #360] @ (8004570 <HAL_GPIO_Init+0x334>)
|
|
8004408: 697b ldr r3, [r7, #20]
|
|
800440a: 089b lsrs r3, r3, #2
|
|
800440c: 3302 adds r3, #2
|
|
800440e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8004412: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
8004414: 697b ldr r3, [r7, #20]
|
|
8004416: f003 0303 and.w r3, r3, #3
|
|
800441a: 009b lsls r3, r3, #2
|
|
800441c: 220f movs r2, #15
|
|
800441e: fa02 f303 lsl.w r3, r2, r3
|
|
8004422: 43db mvns r3, r3
|
|
8004424: 693a ldr r2, [r7, #16]
|
|
8004426: 4013 ands r3, r2
|
|
8004428: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
800442a: 687b ldr r3, [r7, #4]
|
|
800442c: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
8004430: d025 beq.n 800447e <HAL_GPIO_Init+0x242>
|
|
8004432: 687b ldr r3, [r7, #4]
|
|
8004434: 4a4f ldr r2, [pc, #316] @ (8004574 <HAL_GPIO_Init+0x338>)
|
|
8004436: 4293 cmp r3, r2
|
|
8004438: d01f beq.n 800447a <HAL_GPIO_Init+0x23e>
|
|
800443a: 687b ldr r3, [r7, #4]
|
|
800443c: 4a4e ldr r2, [pc, #312] @ (8004578 <HAL_GPIO_Init+0x33c>)
|
|
800443e: 4293 cmp r3, r2
|
|
8004440: d019 beq.n 8004476 <HAL_GPIO_Init+0x23a>
|
|
8004442: 687b ldr r3, [r7, #4]
|
|
8004444: 4a4d ldr r2, [pc, #308] @ (800457c <HAL_GPIO_Init+0x340>)
|
|
8004446: 4293 cmp r3, r2
|
|
8004448: d013 beq.n 8004472 <HAL_GPIO_Init+0x236>
|
|
800444a: 687b ldr r3, [r7, #4]
|
|
800444c: 4a4c ldr r2, [pc, #304] @ (8004580 <HAL_GPIO_Init+0x344>)
|
|
800444e: 4293 cmp r3, r2
|
|
8004450: d00d beq.n 800446e <HAL_GPIO_Init+0x232>
|
|
8004452: 687b ldr r3, [r7, #4]
|
|
8004454: 4a4b ldr r2, [pc, #300] @ (8004584 <HAL_GPIO_Init+0x348>)
|
|
8004456: 4293 cmp r3, r2
|
|
8004458: d007 beq.n 800446a <HAL_GPIO_Init+0x22e>
|
|
800445a: 687b ldr r3, [r7, #4]
|
|
800445c: 4a4a ldr r2, [pc, #296] @ (8004588 <HAL_GPIO_Init+0x34c>)
|
|
800445e: 4293 cmp r3, r2
|
|
8004460: d101 bne.n 8004466 <HAL_GPIO_Init+0x22a>
|
|
8004462: 2306 movs r3, #6
|
|
8004464: e00c b.n 8004480 <HAL_GPIO_Init+0x244>
|
|
8004466: 2307 movs r3, #7
|
|
8004468: e00a b.n 8004480 <HAL_GPIO_Init+0x244>
|
|
800446a: 2305 movs r3, #5
|
|
800446c: e008 b.n 8004480 <HAL_GPIO_Init+0x244>
|
|
800446e: 2304 movs r3, #4
|
|
8004470: e006 b.n 8004480 <HAL_GPIO_Init+0x244>
|
|
8004472: 2303 movs r3, #3
|
|
8004474: e004 b.n 8004480 <HAL_GPIO_Init+0x244>
|
|
8004476: 2302 movs r3, #2
|
|
8004478: e002 b.n 8004480 <HAL_GPIO_Init+0x244>
|
|
800447a: 2301 movs r3, #1
|
|
800447c: e000 b.n 8004480 <HAL_GPIO_Init+0x244>
|
|
800447e: 2300 movs r3, #0
|
|
8004480: 697a ldr r2, [r7, #20]
|
|
8004482: f002 0203 and.w r2, r2, #3
|
|
8004486: 0092 lsls r2, r2, #2
|
|
8004488: 4093 lsls r3, r2
|
|
800448a: 693a ldr r2, [r7, #16]
|
|
800448c: 4313 orrs r3, r2
|
|
800448e: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
8004490: 4937 ldr r1, [pc, #220] @ (8004570 <HAL_GPIO_Init+0x334>)
|
|
8004492: 697b ldr r3, [r7, #20]
|
|
8004494: 089b lsrs r3, r3, #2
|
|
8004496: 3302 adds r3, #2
|
|
8004498: 693a ldr r2, [r7, #16]
|
|
800449a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
800449e: 4b3b ldr r3, [pc, #236] @ (800458c <HAL_GPIO_Init+0x350>)
|
|
80044a0: 689b ldr r3, [r3, #8]
|
|
80044a2: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80044a4: 68fb ldr r3, [r7, #12]
|
|
80044a6: 43db mvns r3, r3
|
|
80044a8: 693a ldr r2, [r7, #16]
|
|
80044aa: 4013 ands r3, r2
|
|
80044ac: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
80044ae: 683b ldr r3, [r7, #0]
|
|
80044b0: 685b ldr r3, [r3, #4]
|
|
80044b2: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80044b6: 2b00 cmp r3, #0
|
|
80044b8: d003 beq.n 80044c2 <HAL_GPIO_Init+0x286>
|
|
{
|
|
temp |= iocurrent;
|
|
80044ba: 693a ldr r2, [r7, #16]
|
|
80044bc: 68fb ldr r3, [r7, #12]
|
|
80044be: 4313 orrs r3, r2
|
|
80044c0: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
80044c2: 4a32 ldr r2, [pc, #200] @ (800458c <HAL_GPIO_Init+0x350>)
|
|
80044c4: 693b ldr r3, [r7, #16]
|
|
80044c6: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR1;
|
|
80044c8: 4b30 ldr r3, [pc, #192] @ (800458c <HAL_GPIO_Init+0x350>)
|
|
80044ca: 68db ldr r3, [r3, #12]
|
|
80044cc: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80044ce: 68fb ldr r3, [r7, #12]
|
|
80044d0: 43db mvns r3, r3
|
|
80044d2: 693a ldr r2, [r7, #16]
|
|
80044d4: 4013 ands r3, r2
|
|
80044d6: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
80044d8: 683b ldr r3, [r7, #0]
|
|
80044da: 685b ldr r3, [r3, #4]
|
|
80044dc: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
80044e0: 2b00 cmp r3, #0
|
|
80044e2: d003 beq.n 80044ec <HAL_GPIO_Init+0x2b0>
|
|
{
|
|
temp |= iocurrent;
|
|
80044e4: 693a ldr r2, [r7, #16]
|
|
80044e6: 68fb ldr r3, [r7, #12]
|
|
80044e8: 4313 orrs r3, r2
|
|
80044ea: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
80044ec: 4a27 ldr r2, [pc, #156] @ (800458c <HAL_GPIO_Init+0x350>)
|
|
80044ee: 693b ldr r3, [r7, #16]
|
|
80044f0: 60d3 str r3, [r2, #12]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->EMR1;
|
|
80044f2: 4b26 ldr r3, [pc, #152] @ (800458c <HAL_GPIO_Init+0x350>)
|
|
80044f4: 685b ldr r3, [r3, #4]
|
|
80044f6: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80044f8: 68fb ldr r3, [r7, #12]
|
|
80044fa: 43db mvns r3, r3
|
|
80044fc: 693a ldr r2, [r7, #16]
|
|
80044fe: 4013 ands r3, r2
|
|
8004500: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
8004502: 683b ldr r3, [r7, #0]
|
|
8004504: 685b ldr r3, [r3, #4]
|
|
8004506: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800450a: 2b00 cmp r3, #0
|
|
800450c: d003 beq.n 8004516 <HAL_GPIO_Init+0x2da>
|
|
{
|
|
temp |= iocurrent;
|
|
800450e: 693a ldr r2, [r7, #16]
|
|
8004510: 68fb ldr r3, [r7, #12]
|
|
8004512: 4313 orrs r3, r2
|
|
8004514: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
8004516: 4a1d ldr r2, [pc, #116] @ (800458c <HAL_GPIO_Init+0x350>)
|
|
8004518: 693b ldr r3, [r7, #16]
|
|
800451a: 6053 str r3, [r2, #4]
|
|
|
|
temp = EXTI->IMR1;
|
|
800451c: 4b1b ldr r3, [pc, #108] @ (800458c <HAL_GPIO_Init+0x350>)
|
|
800451e: 681b ldr r3, [r3, #0]
|
|
8004520: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8004522: 68fb ldr r3, [r7, #12]
|
|
8004524: 43db mvns r3, r3
|
|
8004526: 693a ldr r2, [r7, #16]
|
|
8004528: 4013 ands r3, r2
|
|
800452a: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
800452c: 683b ldr r3, [r7, #0]
|
|
800452e: 685b ldr r3, [r3, #4]
|
|
8004530: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8004534: 2b00 cmp r3, #0
|
|
8004536: d003 beq.n 8004540 <HAL_GPIO_Init+0x304>
|
|
{
|
|
temp |= iocurrent;
|
|
8004538: 693a ldr r2, [r7, #16]
|
|
800453a: 68fb ldr r3, [r7, #12]
|
|
800453c: 4313 orrs r3, r2
|
|
800453e: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
8004540: 4a12 ldr r2, [pc, #72] @ (800458c <HAL_GPIO_Init+0x350>)
|
|
8004542: 693b ldr r3, [r7, #16]
|
|
8004544: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8004546: 697b ldr r3, [r7, #20]
|
|
8004548: 3301 adds r3, #1
|
|
800454a: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
800454c: 683b ldr r3, [r7, #0]
|
|
800454e: 681a ldr r2, [r3, #0]
|
|
8004550: 697b ldr r3, [r7, #20]
|
|
8004552: fa22 f303 lsr.w r3, r2, r3
|
|
8004556: 2b00 cmp r3, #0
|
|
8004558: f47f ae78 bne.w 800424c <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
800455c: bf00 nop
|
|
800455e: bf00 nop
|
|
8004560: 371c adds r7, #28
|
|
8004562: 46bd mov sp, r7
|
|
8004564: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004568: 4770 bx lr
|
|
800456a: bf00 nop
|
|
800456c: 40021000 .word 0x40021000
|
|
8004570: 40010000 .word 0x40010000
|
|
8004574: 48000400 .word 0x48000400
|
|
8004578: 48000800 .word 0x48000800
|
|
800457c: 48000c00 .word 0x48000c00
|
|
8004580: 48001000 .word 0x48001000
|
|
8004584: 48001400 .word 0x48001400
|
|
8004588: 48001800 .word 0x48001800
|
|
800458c: 40010400 .word 0x40010400
|
|
|
|
08004590 <HAL_GPIO_DeInit>:
|
|
* @param GPIO_Pin specifies the port bit to be written.
|
|
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|
{
|
|
8004590: b480 push {r7}
|
|
8004592: b087 sub sp, #28
|
|
8004594: af00 add r7, sp, #0
|
|
8004596: 6078 str r0, [r7, #4]
|
|
8004598: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
800459a: 2300 movs r3, #0
|
|
800459c: 617b str r3, [r7, #20]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* Configure the port pins */
|
|
while ((GPIO_Pin >> position) != 0x00u)
|
|
800459e: e0cd b.n 800473c <HAL_GPIO_DeInit+0x1ac>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Pin) & (1uL << position);
|
|
80045a0: 2201 movs r2, #1
|
|
80045a2: 697b ldr r3, [r7, #20]
|
|
80045a4: fa02 f303 lsl.w r3, r2, r3
|
|
80045a8: 683a ldr r2, [r7, #0]
|
|
80045aa: 4013 ands r3, r2
|
|
80045ac: 613b str r3, [r7, #16]
|
|
|
|
if (iocurrent != 0x00u)
|
|
80045ae: 693b ldr r3, [r7, #16]
|
|
80045b0: 2b00 cmp r3, #0
|
|
80045b2: f000 80c0 beq.w 8004736 <HAL_GPIO_DeInit+0x1a6>
|
|
{
|
|
/*------------------------- EXTI Mode Configuration --------------------*/
|
|
/* Clear the External Interrupt or Event for the current IO */
|
|
|
|
tmp = SYSCFG->EXTICR[position >> 2u];
|
|
80045b6: 4a68 ldr r2, [pc, #416] @ (8004758 <HAL_GPIO_DeInit+0x1c8>)
|
|
80045b8: 697b ldr r3, [r7, #20]
|
|
80045ba: 089b lsrs r3, r3, #2
|
|
80045bc: 3302 adds r3, #2
|
|
80045be: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80045c2: 60fb str r3, [r7, #12]
|
|
tmp &= (0x0FuL << (4u * (position & 0x03u)));
|
|
80045c4: 697b ldr r3, [r7, #20]
|
|
80045c6: f003 0303 and.w r3, r3, #3
|
|
80045ca: 009b lsls r3, r3, #2
|
|
80045cc: 220f movs r2, #15
|
|
80045ce: fa02 f303 lsl.w r3, r2, r3
|
|
80045d2: 68fa ldr r2, [r7, #12]
|
|
80045d4: 4013 ands r3, r2
|
|
80045d6: 60fb str r3, [r7, #12]
|
|
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
|
|
80045d8: 687b ldr r3, [r7, #4]
|
|
80045da: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
80045de: d025 beq.n 800462c <HAL_GPIO_DeInit+0x9c>
|
|
80045e0: 687b ldr r3, [r7, #4]
|
|
80045e2: 4a5e ldr r2, [pc, #376] @ (800475c <HAL_GPIO_DeInit+0x1cc>)
|
|
80045e4: 4293 cmp r3, r2
|
|
80045e6: d01f beq.n 8004628 <HAL_GPIO_DeInit+0x98>
|
|
80045e8: 687b ldr r3, [r7, #4]
|
|
80045ea: 4a5d ldr r2, [pc, #372] @ (8004760 <HAL_GPIO_DeInit+0x1d0>)
|
|
80045ec: 4293 cmp r3, r2
|
|
80045ee: d019 beq.n 8004624 <HAL_GPIO_DeInit+0x94>
|
|
80045f0: 687b ldr r3, [r7, #4]
|
|
80045f2: 4a5c ldr r2, [pc, #368] @ (8004764 <HAL_GPIO_DeInit+0x1d4>)
|
|
80045f4: 4293 cmp r3, r2
|
|
80045f6: d013 beq.n 8004620 <HAL_GPIO_DeInit+0x90>
|
|
80045f8: 687b ldr r3, [r7, #4]
|
|
80045fa: 4a5b ldr r2, [pc, #364] @ (8004768 <HAL_GPIO_DeInit+0x1d8>)
|
|
80045fc: 4293 cmp r3, r2
|
|
80045fe: d00d beq.n 800461c <HAL_GPIO_DeInit+0x8c>
|
|
8004600: 687b ldr r3, [r7, #4]
|
|
8004602: 4a5a ldr r2, [pc, #360] @ (800476c <HAL_GPIO_DeInit+0x1dc>)
|
|
8004604: 4293 cmp r3, r2
|
|
8004606: d007 beq.n 8004618 <HAL_GPIO_DeInit+0x88>
|
|
8004608: 687b ldr r3, [r7, #4]
|
|
800460a: 4a59 ldr r2, [pc, #356] @ (8004770 <HAL_GPIO_DeInit+0x1e0>)
|
|
800460c: 4293 cmp r3, r2
|
|
800460e: d101 bne.n 8004614 <HAL_GPIO_DeInit+0x84>
|
|
8004610: 2306 movs r3, #6
|
|
8004612: e00c b.n 800462e <HAL_GPIO_DeInit+0x9e>
|
|
8004614: 2307 movs r3, #7
|
|
8004616: e00a b.n 800462e <HAL_GPIO_DeInit+0x9e>
|
|
8004618: 2305 movs r3, #5
|
|
800461a: e008 b.n 800462e <HAL_GPIO_DeInit+0x9e>
|
|
800461c: 2304 movs r3, #4
|
|
800461e: e006 b.n 800462e <HAL_GPIO_DeInit+0x9e>
|
|
8004620: 2303 movs r3, #3
|
|
8004622: e004 b.n 800462e <HAL_GPIO_DeInit+0x9e>
|
|
8004624: 2302 movs r3, #2
|
|
8004626: e002 b.n 800462e <HAL_GPIO_DeInit+0x9e>
|
|
8004628: 2301 movs r3, #1
|
|
800462a: e000 b.n 800462e <HAL_GPIO_DeInit+0x9e>
|
|
800462c: 2300 movs r3, #0
|
|
800462e: 697a ldr r2, [r7, #20]
|
|
8004630: f002 0203 and.w r2, r2, #3
|
|
8004634: 0092 lsls r2, r2, #2
|
|
8004636: 4093 lsls r3, r2
|
|
8004638: 68fa ldr r2, [r7, #12]
|
|
800463a: 429a cmp r2, r3
|
|
800463c: d132 bne.n 80046a4 <HAL_GPIO_DeInit+0x114>
|
|
{
|
|
/* Clear EXTI line configuration */
|
|
EXTI->IMR1 &= ~(iocurrent);
|
|
800463e: 4b4d ldr r3, [pc, #308] @ (8004774 <HAL_GPIO_DeInit+0x1e4>)
|
|
8004640: 681a ldr r2, [r3, #0]
|
|
8004642: 693b ldr r3, [r7, #16]
|
|
8004644: 43db mvns r3, r3
|
|
8004646: 494b ldr r1, [pc, #300] @ (8004774 <HAL_GPIO_DeInit+0x1e4>)
|
|
8004648: 4013 ands r3, r2
|
|
800464a: 600b str r3, [r1, #0]
|
|
EXTI->EMR1 &= ~(iocurrent);
|
|
800464c: 4b49 ldr r3, [pc, #292] @ (8004774 <HAL_GPIO_DeInit+0x1e4>)
|
|
800464e: 685a ldr r2, [r3, #4]
|
|
8004650: 693b ldr r3, [r7, #16]
|
|
8004652: 43db mvns r3, r3
|
|
8004654: 4947 ldr r1, [pc, #284] @ (8004774 <HAL_GPIO_DeInit+0x1e4>)
|
|
8004656: 4013 ands r3, r2
|
|
8004658: 604b str r3, [r1, #4]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
EXTI->FTSR1 &= ~(iocurrent);
|
|
800465a: 4b46 ldr r3, [pc, #280] @ (8004774 <HAL_GPIO_DeInit+0x1e4>)
|
|
800465c: 68da ldr r2, [r3, #12]
|
|
800465e: 693b ldr r3, [r7, #16]
|
|
8004660: 43db mvns r3, r3
|
|
8004662: 4944 ldr r1, [pc, #272] @ (8004774 <HAL_GPIO_DeInit+0x1e4>)
|
|
8004664: 4013 ands r3, r2
|
|
8004666: 60cb str r3, [r1, #12]
|
|
EXTI->RTSR1 &= ~(iocurrent);
|
|
8004668: 4b42 ldr r3, [pc, #264] @ (8004774 <HAL_GPIO_DeInit+0x1e4>)
|
|
800466a: 689a ldr r2, [r3, #8]
|
|
800466c: 693b ldr r3, [r7, #16]
|
|
800466e: 43db mvns r3, r3
|
|
8004670: 4940 ldr r1, [pc, #256] @ (8004774 <HAL_GPIO_DeInit+0x1e4>)
|
|
8004672: 4013 ands r3, r2
|
|
8004674: 608b str r3, [r1, #8]
|
|
|
|
tmp = 0x0FuL << (4u * (position & 0x03u));
|
|
8004676: 697b ldr r3, [r7, #20]
|
|
8004678: f003 0303 and.w r3, r3, #3
|
|
800467c: 009b lsls r3, r3, #2
|
|
800467e: 220f movs r2, #15
|
|
8004680: fa02 f303 lsl.w r3, r2, r3
|
|
8004684: 60fb str r3, [r7, #12]
|
|
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
|
|
8004686: 4a34 ldr r2, [pc, #208] @ (8004758 <HAL_GPIO_DeInit+0x1c8>)
|
|
8004688: 697b ldr r3, [r7, #20]
|
|
800468a: 089b lsrs r3, r3, #2
|
|
800468c: 3302 adds r3, #2
|
|
800468e: f852 1023 ldr.w r1, [r2, r3, lsl #2]
|
|
8004692: 68fb ldr r3, [r7, #12]
|
|
8004694: 43da mvns r2, r3
|
|
8004696: 4830 ldr r0, [pc, #192] @ (8004758 <HAL_GPIO_DeInit+0x1c8>)
|
|
8004698: 697b ldr r3, [r7, #20]
|
|
800469a: 089b lsrs r3, r3, #2
|
|
800469c: 400a ands r2, r1
|
|
800469e: 3302 adds r3, #2
|
|
80046a0: f840 2023 str.w r2, [r0, r3, lsl #2]
|
|
}
|
|
|
|
/*------------------------- GPIO Mode Configuration --------------------*/
|
|
/* Configure IO in Analog Mode */
|
|
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
|
|
80046a4: 687b ldr r3, [r7, #4]
|
|
80046a6: 681a ldr r2, [r3, #0]
|
|
80046a8: 697b ldr r3, [r7, #20]
|
|
80046aa: 005b lsls r3, r3, #1
|
|
80046ac: 2103 movs r1, #3
|
|
80046ae: fa01 f303 lsl.w r3, r1, r3
|
|
80046b2: 431a orrs r2, r3
|
|
80046b4: 687b ldr r3, [r7, #4]
|
|
80046b6: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the default Alternate Function in current IO */
|
|
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
|
|
80046b8: 697b ldr r3, [r7, #20]
|
|
80046ba: 08da lsrs r2, r3, #3
|
|
80046bc: 687b ldr r3, [r7, #4]
|
|
80046be: 3208 adds r2, #8
|
|
80046c0: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
80046c4: 697b ldr r3, [r7, #20]
|
|
80046c6: f003 0307 and.w r3, r3, #7
|
|
80046ca: 009b lsls r3, r3, #2
|
|
80046cc: 220f movs r2, #15
|
|
80046ce: fa02 f303 lsl.w r3, r2, r3
|
|
80046d2: 43db mvns r3, r3
|
|
80046d4: 697a ldr r2, [r7, #20]
|
|
80046d6: 08d2 lsrs r2, r2, #3
|
|
80046d8: 4019 ands r1, r3
|
|
80046da: 687b ldr r3, [r7, #4]
|
|
80046dc: 3208 adds r2, #8
|
|
80046de: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
|
|
/* Configure the default value for IO Speed */
|
|
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
80046e2: 687b ldr r3, [r7, #4]
|
|
80046e4: 689a ldr r2, [r3, #8]
|
|
80046e6: 697b ldr r3, [r7, #20]
|
|
80046e8: 005b lsls r3, r3, #1
|
|
80046ea: 2103 movs r1, #3
|
|
80046ec: fa01 f303 lsl.w r3, r1, r3
|
|
80046f0: 43db mvns r3, r3
|
|
80046f2: 401a ands r2, r3
|
|
80046f4: 687b ldr r3, [r7, #4]
|
|
80046f6: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the default value IO Output Type */
|
|
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
80046f8: 687b ldr r3, [r7, #4]
|
|
80046fa: 685a ldr r2, [r3, #4]
|
|
80046fc: 2101 movs r1, #1
|
|
80046fe: 697b ldr r3, [r7, #20]
|
|
8004700: fa01 f303 lsl.w r3, r1, r3
|
|
8004704: 43db mvns r3, r3
|
|
8004706: 401a ands r2, r3
|
|
8004708: 687b ldr r3, [r7, #4]
|
|
800470a: 605a str r2, [r3, #4]
|
|
|
|
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
|
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
|
800470c: 687b ldr r3, [r7, #4]
|
|
800470e: 68da ldr r2, [r3, #12]
|
|
8004710: 697b ldr r3, [r7, #20]
|
|
8004712: 005b lsls r3, r3, #1
|
|
8004714: 2103 movs r1, #3
|
|
8004716: fa01 f303 lsl.w r3, r1, r3
|
|
800471a: 43db mvns r3, r3
|
|
800471c: 401a ands r2, r3
|
|
800471e: 687b ldr r3, [r7, #4]
|
|
8004720: 60da str r2, [r3, #12]
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
/* Deactivate the Control bit of Analog mode for the current IO */
|
|
GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
|
|
8004722: 687b ldr r3, [r7, #4]
|
|
8004724: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8004726: 2101 movs r1, #1
|
|
8004728: 697b ldr r3, [r7, #20]
|
|
800472a: fa01 f303 lsl.w r3, r1, r3
|
|
800472e: 43db mvns r3, r3
|
|
8004730: 401a ands r2, r3
|
|
8004732: 687b ldr r3, [r7, #4]
|
|
8004734: 62da str r2, [r3, #44] @ 0x2c
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
}
|
|
|
|
position++;
|
|
8004736: 697b ldr r3, [r7, #20]
|
|
8004738: 3301 adds r3, #1
|
|
800473a: 617b str r3, [r7, #20]
|
|
while ((GPIO_Pin >> position) != 0x00u)
|
|
800473c: 683a ldr r2, [r7, #0]
|
|
800473e: 697b ldr r3, [r7, #20]
|
|
8004740: fa22 f303 lsr.w r3, r2, r3
|
|
8004744: 2b00 cmp r3, #0
|
|
8004746: f47f af2b bne.w 80045a0 <HAL_GPIO_DeInit+0x10>
|
|
}
|
|
}
|
|
800474a: bf00 nop
|
|
800474c: bf00 nop
|
|
800474e: 371c adds r7, #28
|
|
8004750: 46bd mov sp, r7
|
|
8004752: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004756: 4770 bx lr
|
|
8004758: 40010000 .word 0x40010000
|
|
800475c: 48000400 .word 0x48000400
|
|
8004760: 48000800 .word 0x48000800
|
|
8004764: 48000c00 .word 0x48000c00
|
|
8004768: 48001000 .word 0x48001000
|
|
800476c: 48001400 .word 0x48001400
|
|
8004770: 48001800 .word 0x48001800
|
|
8004774: 40010400 .word 0x40010400
|
|
|
|
08004778 <HAL_GPIO_ReadPin>:
|
|
* @param GPIO_Pin specifies the port bit to read.
|
|
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
|
* @retval The input port pin value.
|
|
*/
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8004778: b480 push {r7}
|
|
800477a: b085 sub sp, #20
|
|
800477c: af00 add r7, sp, #0
|
|
800477e: 6078 str r0, [r7, #4]
|
|
8004780: 460b mov r3, r1
|
|
8004782: 807b strh r3, [r7, #2]
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
|
|
8004784: 687b ldr r3, [r7, #4]
|
|
8004786: 691a ldr r2, [r3, #16]
|
|
8004788: 887b ldrh r3, [r7, #2]
|
|
800478a: 4013 ands r3, r2
|
|
800478c: 2b00 cmp r3, #0
|
|
800478e: d002 beq.n 8004796 <HAL_GPIO_ReadPin+0x1e>
|
|
{
|
|
bitstatus = GPIO_PIN_SET;
|
|
8004790: 2301 movs r3, #1
|
|
8004792: 73fb strb r3, [r7, #15]
|
|
8004794: e001 b.n 800479a <HAL_GPIO_ReadPin+0x22>
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
8004796: 2300 movs r3, #0
|
|
8004798: 73fb strb r3, [r7, #15]
|
|
}
|
|
return bitstatus;
|
|
800479a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800479c: 4618 mov r0, r3
|
|
800479e: 3714 adds r7, #20
|
|
80047a0: 46bd mov sp, r7
|
|
80047a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80047a6: 4770 bx lr
|
|
|
|
080047a8 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
80047a8: b480 push {r7}
|
|
80047aa: b083 sub sp, #12
|
|
80047ac: af00 add r7, sp, #0
|
|
80047ae: 6078 str r0, [r7, #4]
|
|
80047b0: 460b mov r3, r1
|
|
80047b2: 807b strh r3, [r7, #2]
|
|
80047b4: 4613 mov r3, r2
|
|
80047b6: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
80047b8: 787b ldrb r3, [r7, #1]
|
|
80047ba: 2b00 cmp r3, #0
|
|
80047bc: d003 beq.n 80047c6 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
80047be: 887a ldrh r2, [r7, #2]
|
|
80047c0: 687b ldr r3, [r7, #4]
|
|
80047c2: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
80047c4: e002 b.n 80047cc <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
80047c6: 887a ldrh r2, [r7, #2]
|
|
80047c8: 687b ldr r3, [r7, #4]
|
|
80047ca: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
80047cc: bf00 nop
|
|
80047ce: 370c adds r7, #12
|
|
80047d0: 46bd mov sp, r7
|
|
80047d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80047d6: 4770 bx lr
|
|
|
|
080047d8 <HAL_GPIO_EXTI_IRQHandler>:
|
|
* @brief Handle EXTI interrupt request.
|
|
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
|
{
|
|
80047d8: b580 push {r7, lr}
|
|
80047da: b082 sub sp, #8
|
|
80047dc: af00 add r7, sp, #0
|
|
80047de: 4603 mov r3, r0
|
|
80047e0: 80fb strh r3, [r7, #6]
|
|
/* EXTI line interrupt detected */
|
|
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
|
80047e2: 4b08 ldr r3, [pc, #32] @ (8004804 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
|
|
80047e4: 695a ldr r2, [r3, #20]
|
|
80047e6: 88fb ldrh r3, [r7, #6]
|
|
80047e8: 4013 ands r3, r2
|
|
80047ea: 2b00 cmp r3, #0
|
|
80047ec: d006 beq.n 80047fc <HAL_GPIO_EXTI_IRQHandler+0x24>
|
|
{
|
|
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
|
80047ee: 4a05 ldr r2, [pc, #20] @ (8004804 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
|
|
80047f0: 88fb ldrh r3, [r7, #6]
|
|
80047f2: 6153 str r3, [r2, #20]
|
|
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
|
80047f4: 88fb ldrh r3, [r7, #6]
|
|
80047f6: 4618 mov r0, r3
|
|
80047f8: f7fe f92f bl 8002a5a <HAL_GPIO_EXTI_Callback>
|
|
}
|
|
}
|
|
80047fc: bf00 nop
|
|
80047fe: 3708 adds r7, #8
|
|
8004800: 46bd mov sp, r7
|
|
8004802: bd80 pop {r7, pc}
|
|
8004804: 40010400 .word 0x40010400
|
|
|
|
08004808 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8004808: b580 push {r7, lr}
|
|
800480a: b082 sub sp, #8
|
|
800480c: af00 add r7, sp, #0
|
|
800480e: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8004810: 687b ldr r3, [r7, #4]
|
|
8004812: 2b00 cmp r3, #0
|
|
8004814: d101 bne.n 800481a <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004816: 2301 movs r3, #1
|
|
8004818: e08d b.n 8004936 <HAL_I2C_Init+0x12e>
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
800481a: 687b ldr r3, [r7, #4]
|
|
800481c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004820: b2db uxtb r3, r3
|
|
8004822: 2b00 cmp r3, #0
|
|
8004824: d106 bne.n 8004834 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8004826: 687b ldr r3, [r7, #4]
|
|
8004828: 2200 movs r2, #0
|
|
800482a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
HAL_I2C_MspInit(hi2c);
|
|
800482e: 6878 ldr r0, [r7, #4]
|
|
8004830: f7fe fe02 bl 8003438 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8004834: 687b ldr r3, [r7, #4]
|
|
8004836: 2224 movs r2, #36 @ 0x24
|
|
8004838: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
800483c: 687b ldr r3, [r7, #4]
|
|
800483e: 681b ldr r3, [r3, #0]
|
|
8004840: 681a ldr r2, [r3, #0]
|
|
8004842: 687b ldr r3, [r7, #4]
|
|
8004844: 681b ldr r3, [r3, #0]
|
|
8004846: f022 0201 bic.w r2, r2, #1
|
|
800484a: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
|
|
800484c: 687b ldr r3, [r7, #4]
|
|
800484e: 685a ldr r2, [r3, #4]
|
|
8004850: 687b ldr r3, [r7, #4]
|
|
8004852: 681b ldr r3, [r3, #0]
|
|
8004854: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
|
|
8004858: 611a str r2, [r3, #16]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Disable Own Address1 before set the Own Address1 configuration */
|
|
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
|
|
800485a: 687b ldr r3, [r7, #4]
|
|
800485c: 681b ldr r3, [r3, #0]
|
|
800485e: 689a ldr r2, [r3, #8]
|
|
8004860: 687b ldr r3, [r7, #4]
|
|
8004862: 681b ldr r3, [r3, #0]
|
|
8004864: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8004868: 609a str r2, [r3, #8]
|
|
|
|
/* Configure I2Cx: Own Address1 and ack own address1 mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
800486a: 687b ldr r3, [r7, #4]
|
|
800486c: 68db ldr r3, [r3, #12]
|
|
800486e: 2b01 cmp r3, #1
|
|
8004870: d107 bne.n 8004882 <HAL_I2C_Init+0x7a>
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
|
|
8004872: 687b ldr r3, [r7, #4]
|
|
8004874: 689a ldr r2, [r3, #8]
|
|
8004876: 687b ldr r3, [r7, #4]
|
|
8004878: 681b ldr r3, [r3, #0]
|
|
800487a: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
800487e: 609a str r2, [r3, #8]
|
|
8004880: e006 b.n 8004890 <HAL_I2C_Init+0x88>
|
|
}
|
|
else /* I2C_ADDRESSINGMODE_10BIT */
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
|
|
8004882: 687b ldr r3, [r7, #4]
|
|
8004884: 689a ldr r2, [r3, #8]
|
|
8004886: 687b ldr r3, [r7, #4]
|
|
8004888: 681b ldr r3, [r3, #0]
|
|
800488a: f442 4204 orr.w r2, r2, #33792 @ 0x8400
|
|
800488e: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Addressing Master mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
8004890: 687b ldr r3, [r7, #4]
|
|
8004892: 68db ldr r3, [r3, #12]
|
|
8004894: 2b02 cmp r3, #2
|
|
8004896: d108 bne.n 80048aa <HAL_I2C_Init+0xa2>
|
|
{
|
|
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
8004898: 687b ldr r3, [r7, #4]
|
|
800489a: 681b ldr r3, [r3, #0]
|
|
800489c: 685a ldr r2, [r3, #4]
|
|
800489e: 687b ldr r3, [r7, #4]
|
|
80048a0: 681b ldr r3, [r3, #0]
|
|
80048a2: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
80048a6: 605a str r2, [r3, #4]
|
|
80048a8: e007 b.n 80048ba <HAL_I2C_Init+0xb2>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the I2C ADD10 bit */
|
|
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
80048aa: 687b ldr r3, [r7, #4]
|
|
80048ac: 681b ldr r3, [r3, #0]
|
|
80048ae: 685a ldr r2, [r3, #4]
|
|
80048b0: 687b ldr r3, [r7, #4]
|
|
80048b2: 681b ldr r3, [r3, #0]
|
|
80048b4: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
80048b8: 605a str r2, [r3, #4]
|
|
}
|
|
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
|
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
|
80048ba: 687b ldr r3, [r7, #4]
|
|
80048bc: 681b ldr r3, [r3, #0]
|
|
80048be: 685b ldr r3, [r3, #4]
|
|
80048c0: 687a ldr r2, [r7, #4]
|
|
80048c2: 6812 ldr r2, [r2, #0]
|
|
80048c4: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
80048c8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80048cc: 6053 str r3, [r2, #4]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Disable Own Address2 before set the Own Address2 configuration */
|
|
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
|
|
80048ce: 687b ldr r3, [r7, #4]
|
|
80048d0: 681b ldr r3, [r3, #0]
|
|
80048d2: 68da ldr r2, [r3, #12]
|
|
80048d4: 687b ldr r3, [r7, #4]
|
|
80048d6: 681b ldr r3, [r3, #0]
|
|
80048d8: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
80048dc: 60da str r2, [r3, #12]
|
|
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
80048de: 687b ldr r3, [r7, #4]
|
|
80048e0: 691a ldr r2, [r3, #16]
|
|
80048e2: 687b ldr r3, [r7, #4]
|
|
80048e4: 695b ldr r3, [r3, #20]
|
|
80048e6: ea42 0103 orr.w r1, r2, r3
|
|
(hi2c->Init.OwnAddress2Masks << 8));
|
|
80048ea: 687b ldr r3, [r7, #4]
|
|
80048ec: 699b ldr r3, [r3, #24]
|
|
80048ee: 021a lsls r2, r3, #8
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
80048f0: 687b ldr r3, [r7, #4]
|
|
80048f2: 681b ldr r3, [r3, #0]
|
|
80048f4: 430a orrs r2, r1
|
|
80048f6: 60da str r2, [r3, #12]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
|
|
80048f8: 687b ldr r3, [r7, #4]
|
|
80048fa: 69d9 ldr r1, [r3, #28]
|
|
80048fc: 687b ldr r3, [r7, #4]
|
|
80048fe: 6a1a ldr r2, [r3, #32]
|
|
8004900: 687b ldr r3, [r7, #4]
|
|
8004902: 681b ldr r3, [r3, #0]
|
|
8004904: 430a orrs r2, r1
|
|
8004906: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8004908: 687b ldr r3, [r7, #4]
|
|
800490a: 681b ldr r3, [r3, #0]
|
|
800490c: 681a ldr r2, [r3, #0]
|
|
800490e: 687b ldr r3, [r7, #4]
|
|
8004910: 681b ldr r3, [r3, #0]
|
|
8004912: f042 0201 orr.w r2, r2, #1
|
|
8004916: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8004918: 687b ldr r3, [r7, #4]
|
|
800491a: 2200 movs r2, #0
|
|
800491c: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800491e: 687b ldr r3, [r7, #4]
|
|
8004920: 2220 movs r2, #32
|
|
8004922: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8004926: 687b ldr r3, [r7, #4]
|
|
8004928: 2200 movs r2, #0
|
|
800492a: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800492c: 687b ldr r3, [r7, #4]
|
|
800492e: 2200 movs r2, #0
|
|
8004930: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_OK;
|
|
8004934: 2300 movs r3, #0
|
|
}
|
|
8004936: 4618 mov r0, r3
|
|
8004938: 3708 adds r7, #8
|
|
800493a: 46bd mov sp, r7
|
|
800493c: bd80 pop {r7, pc}
|
|
|
|
0800493e <HAL_I2C_DeInit>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
800493e: b580 push {r7, lr}
|
|
8004940: b082 sub sp, #8
|
|
8004942: af00 add r7, sp, #0
|
|
8004944: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8004946: 687b ldr r3, [r7, #4]
|
|
8004948: 2b00 cmp r3, #0
|
|
800494a: d101 bne.n 8004950 <HAL_I2C_DeInit+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800494c: 2301 movs r3, #1
|
|
800494e: e021 b.n 8004994 <HAL_I2C_DeInit+0x56>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8004950: 687b ldr r3, [r7, #4]
|
|
8004952: 2224 movs r2, #36 @ 0x24
|
|
8004954: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the I2C Peripheral Clock */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8004958: 687b ldr r3, [r7, #4]
|
|
800495a: 681b ldr r3, [r3, #0]
|
|
800495c: 681a ldr r2, [r3, #0]
|
|
800495e: 687b ldr r3, [r7, #4]
|
|
8004960: 681b ldr r3, [r3, #0]
|
|
8004962: f022 0201 bic.w r2, r2, #1
|
|
8004966: 601a str r2, [r3, #0]
|
|
|
|
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
hi2c->MspDeInitCallback(hi2c);
|
|
#else
|
|
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspDeInit(hi2c);
|
|
8004968: 6878 ldr r0, [r7, #4]
|
|
800496a: f7fe fdc3 bl 80034f4 <HAL_I2C_MspDeInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
800496e: 687b ldr r3, [r7, #4]
|
|
8004970: 2200 movs r2, #0
|
|
8004972: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_RESET;
|
|
8004974: 687b ldr r3, [r7, #4]
|
|
8004976: 2200 movs r2, #0
|
|
8004978: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
800497c: 687b ldr r3, [r7, #4]
|
|
800497e: 2200 movs r2, #0
|
|
8004980: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004982: 687b ldr r3, [r7, #4]
|
|
8004984: 2200 movs r2, #0
|
|
8004986: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hi2c);
|
|
800498a: 687b ldr r3, [r7, #4]
|
|
800498c: 2200 movs r2, #0
|
|
800498e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8004992: 2300 movs r3, #0
|
|
}
|
|
8004994: 4618 mov r0, r3
|
|
8004996: 3708 adds r7, #8
|
|
8004998: 46bd mov sp, r7
|
|
800499a: bd80 pop {r7, pc}
|
|
|
|
0800499c <HAL_I2C_Mem_Write>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
800499c: b580 push {r7, lr}
|
|
800499e: b088 sub sp, #32
|
|
80049a0: af02 add r7, sp, #8
|
|
80049a2: 60f8 str r0, [r7, #12]
|
|
80049a4: 4608 mov r0, r1
|
|
80049a6: 4611 mov r1, r2
|
|
80049a8: 461a mov r2, r3
|
|
80049aa: 4603 mov r3, r0
|
|
80049ac: 817b strh r3, [r7, #10]
|
|
80049ae: 460b mov r3, r1
|
|
80049b0: 813b strh r3, [r7, #8]
|
|
80049b2: 4613 mov r3, r2
|
|
80049b4: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
80049b6: 68fb ldr r3, [r7, #12]
|
|
80049b8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80049bc: b2db uxtb r3, r3
|
|
80049be: 2b20 cmp r3, #32
|
|
80049c0: f040 80f9 bne.w 8004bb6 <HAL_I2C_Mem_Write+0x21a>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80049c4: 6a3b ldr r3, [r7, #32]
|
|
80049c6: 2b00 cmp r3, #0
|
|
80049c8: d002 beq.n 80049d0 <HAL_I2C_Mem_Write+0x34>
|
|
80049ca: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
80049cc: 2b00 cmp r3, #0
|
|
80049ce: d105 bne.n 80049dc <HAL_I2C_Mem_Write+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
80049d0: 68fb ldr r3, [r7, #12]
|
|
80049d2: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80049d6: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
80049d8: 2301 movs r3, #1
|
|
80049da: e0ed b.n 8004bb8 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80049dc: 68fb ldr r3, [r7, #12]
|
|
80049de: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
80049e2: 2b01 cmp r3, #1
|
|
80049e4: d101 bne.n 80049ea <HAL_I2C_Mem_Write+0x4e>
|
|
80049e6: 2302 movs r3, #2
|
|
80049e8: e0e6 b.n 8004bb8 <HAL_I2C_Mem_Write+0x21c>
|
|
80049ea: 68fb ldr r3, [r7, #12]
|
|
80049ec: 2201 movs r2, #1
|
|
80049ee: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
80049f2: f7ff f985 bl 8003d00 <HAL_GetTick>
|
|
80049f6: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
80049f8: 697b ldr r3, [r7, #20]
|
|
80049fa: 9300 str r3, [sp, #0]
|
|
80049fc: 2319 movs r3, #25
|
|
80049fe: 2201 movs r2, #1
|
|
8004a00: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
8004a04: 68f8 ldr r0, [r7, #12]
|
|
8004a06: f000 fac3 bl 8004f90 <I2C_WaitOnFlagUntilTimeout>
|
|
8004a0a: 4603 mov r3, r0
|
|
8004a0c: 2b00 cmp r3, #0
|
|
8004a0e: d001 beq.n 8004a14 <HAL_I2C_Mem_Write+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8004a10: 2301 movs r3, #1
|
|
8004a12: e0d1 b.n 8004bb8 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
8004a14: 68fb ldr r3, [r7, #12]
|
|
8004a16: 2221 movs r2, #33 @ 0x21
|
|
8004a18: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8004a1c: 68fb ldr r3, [r7, #12]
|
|
8004a1e: 2240 movs r2, #64 @ 0x40
|
|
8004a20: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8004a24: 68fb ldr r3, [r7, #12]
|
|
8004a26: 2200 movs r2, #0
|
|
8004a28: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8004a2a: 68fb ldr r3, [r7, #12]
|
|
8004a2c: 6a3a ldr r2, [r7, #32]
|
|
8004a2e: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8004a30: 68fb ldr r3, [r7, #12]
|
|
8004a32: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
8004a34: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8004a36: 68fb ldr r3, [r7, #12]
|
|
8004a38: 2200 movs r2, #0
|
|
8004a3a: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8004a3c: 88f8 ldrh r0, [r7, #6]
|
|
8004a3e: 893a ldrh r2, [r7, #8]
|
|
8004a40: 8979 ldrh r1, [r7, #10]
|
|
8004a42: 697b ldr r3, [r7, #20]
|
|
8004a44: 9301 str r3, [sp, #4]
|
|
8004a46: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004a48: 9300 str r3, [sp, #0]
|
|
8004a4a: 4603 mov r3, r0
|
|
8004a4c: 68f8 ldr r0, [r7, #12]
|
|
8004a4e: f000 f9d3 bl 8004df8 <I2C_RequestMemoryWrite>
|
|
8004a52: 4603 mov r3, r0
|
|
8004a54: 2b00 cmp r3, #0
|
|
8004a56: d005 beq.n 8004a64 <HAL_I2C_Mem_Write+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004a58: 68fb ldr r3, [r7, #12]
|
|
8004a5a: 2200 movs r2, #0
|
|
8004a5c: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8004a60: 2301 movs r3, #1
|
|
8004a62: e0a9 b.n 8004bb8 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8004a64: 68fb ldr r3, [r7, #12]
|
|
8004a66: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004a68: b29b uxth r3, r3
|
|
8004a6a: 2bff cmp r3, #255 @ 0xff
|
|
8004a6c: d90e bls.n 8004a8c <HAL_I2C_Mem_Write+0xf0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8004a6e: 68fb ldr r3, [r7, #12]
|
|
8004a70: 22ff movs r2, #255 @ 0xff
|
|
8004a72: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
8004a74: 68fb ldr r3, [r7, #12]
|
|
8004a76: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004a78: b2da uxtb r2, r3
|
|
8004a7a: 8979 ldrh r1, [r7, #10]
|
|
8004a7c: 2300 movs r3, #0
|
|
8004a7e: 9300 str r3, [sp, #0]
|
|
8004a80: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8004a84: 68f8 ldr r0, [r7, #12]
|
|
8004a86: f000 fc47 bl 8005318 <I2C_TransferConfig>
|
|
8004a8a: e00f b.n 8004aac <HAL_I2C_Mem_Write+0x110>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8004a8c: 68fb ldr r3, [r7, #12]
|
|
8004a8e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004a90: b29a uxth r2, r3
|
|
8004a92: 68fb ldr r3, [r7, #12]
|
|
8004a94: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
8004a96: 68fb ldr r3, [r7, #12]
|
|
8004a98: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004a9a: b2da uxtb r2, r3
|
|
8004a9c: 8979 ldrh r1, [r7, #10]
|
|
8004a9e: 2300 movs r3, #0
|
|
8004aa0: 9300 str r3, [sp, #0]
|
|
8004aa2: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8004aa6: 68f8 ldr r0, [r7, #12]
|
|
8004aa8: f000 fc36 bl 8005318 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8004aac: 697a ldr r2, [r7, #20]
|
|
8004aae: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8004ab0: 68f8 ldr r0, [r7, #12]
|
|
8004ab2: f000 fac6 bl 8005042 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8004ab6: 4603 mov r3, r0
|
|
8004ab8: 2b00 cmp r3, #0
|
|
8004aba: d001 beq.n 8004ac0 <HAL_I2C_Mem_Write+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
8004abc: 2301 movs r3, #1
|
|
8004abe: e07b b.n 8004bb8 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Write data to TXDR */
|
|
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
|
8004ac0: 68fb ldr r3, [r7, #12]
|
|
8004ac2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004ac4: 781a ldrb r2, [r3, #0]
|
|
8004ac6: 68fb ldr r3, [r7, #12]
|
|
8004ac8: 681b ldr r3, [r3, #0]
|
|
8004aca: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8004acc: 68fb ldr r3, [r7, #12]
|
|
8004ace: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004ad0: 1c5a adds r2, r3, #1
|
|
8004ad2: 68fb ldr r3, [r7, #12]
|
|
8004ad4: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferCount--;
|
|
8004ad6: 68fb ldr r3, [r7, #12]
|
|
8004ad8: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004ada: b29b uxth r3, r3
|
|
8004adc: 3b01 subs r3, #1
|
|
8004ade: b29a uxth r2, r3
|
|
8004ae0: 68fb ldr r3, [r7, #12]
|
|
8004ae2: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize--;
|
|
8004ae4: 68fb ldr r3, [r7, #12]
|
|
8004ae6: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004ae8: 3b01 subs r3, #1
|
|
8004aea: b29a uxth r2, r3
|
|
8004aec: 68fb ldr r3, [r7, #12]
|
|
8004aee: 851a strh r2, [r3, #40] @ 0x28
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8004af0: 68fb ldr r3, [r7, #12]
|
|
8004af2: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004af4: b29b uxth r3, r3
|
|
8004af6: 2b00 cmp r3, #0
|
|
8004af8: d034 beq.n 8004b64 <HAL_I2C_Mem_Write+0x1c8>
|
|
8004afa: 68fb ldr r3, [r7, #12]
|
|
8004afc: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004afe: 2b00 cmp r3, #0
|
|
8004b00: d130 bne.n 8004b64 <HAL_I2C_Mem_Write+0x1c8>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8004b02: 697b ldr r3, [r7, #20]
|
|
8004b04: 9300 str r3, [sp, #0]
|
|
8004b06: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004b08: 2200 movs r2, #0
|
|
8004b0a: 2180 movs r1, #128 @ 0x80
|
|
8004b0c: 68f8 ldr r0, [r7, #12]
|
|
8004b0e: f000 fa3f bl 8004f90 <I2C_WaitOnFlagUntilTimeout>
|
|
8004b12: 4603 mov r3, r0
|
|
8004b14: 2b00 cmp r3, #0
|
|
8004b16: d001 beq.n 8004b1c <HAL_I2C_Mem_Write+0x180>
|
|
{
|
|
return HAL_ERROR;
|
|
8004b18: 2301 movs r3, #1
|
|
8004b1a: e04d b.n 8004bb8 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8004b1c: 68fb ldr r3, [r7, #12]
|
|
8004b1e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004b20: b29b uxth r3, r3
|
|
8004b22: 2bff cmp r3, #255 @ 0xff
|
|
8004b24: d90e bls.n 8004b44 <HAL_I2C_Mem_Write+0x1a8>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8004b26: 68fb ldr r3, [r7, #12]
|
|
8004b28: 22ff movs r2, #255 @ 0xff
|
|
8004b2a: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8004b2c: 68fb ldr r3, [r7, #12]
|
|
8004b2e: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004b30: b2da uxtb r2, r3
|
|
8004b32: 8979 ldrh r1, [r7, #10]
|
|
8004b34: 2300 movs r3, #0
|
|
8004b36: 9300 str r3, [sp, #0]
|
|
8004b38: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8004b3c: 68f8 ldr r0, [r7, #12]
|
|
8004b3e: f000 fbeb bl 8005318 <I2C_TransferConfig>
|
|
8004b42: e00f b.n 8004b64 <HAL_I2C_Mem_Write+0x1c8>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8004b44: 68fb ldr r3, [r7, #12]
|
|
8004b46: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004b48: b29a uxth r2, r3
|
|
8004b4a: 68fb ldr r3, [r7, #12]
|
|
8004b4c: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8004b4e: 68fb ldr r3, [r7, #12]
|
|
8004b50: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004b52: b2da uxtb r2, r3
|
|
8004b54: 8979 ldrh r1, [r7, #10]
|
|
8004b56: 2300 movs r3, #0
|
|
8004b58: 9300 str r3, [sp, #0]
|
|
8004b5a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8004b5e: 68f8 ldr r0, [r7, #12]
|
|
8004b60: f000 fbda bl 8005318 <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
|
|
} while (hi2c->XferCount > 0U);
|
|
8004b64: 68fb ldr r3, [r7, #12]
|
|
8004b66: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004b68: b29b uxth r3, r3
|
|
8004b6a: 2b00 cmp r3, #0
|
|
8004b6c: d19e bne.n 8004aac <HAL_I2C_Mem_Write+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8004b6e: 697a ldr r2, [r7, #20]
|
|
8004b70: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8004b72: 68f8 ldr r0, [r7, #12]
|
|
8004b74: f000 faac bl 80050d0 <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8004b78: 4603 mov r3, r0
|
|
8004b7a: 2b00 cmp r3, #0
|
|
8004b7c: d001 beq.n 8004b82 <HAL_I2C_Mem_Write+0x1e6>
|
|
{
|
|
return HAL_ERROR;
|
|
8004b7e: 2301 movs r3, #1
|
|
8004b80: e01a b.n 8004bb8 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8004b82: 68fb ldr r3, [r7, #12]
|
|
8004b84: 681b ldr r3, [r3, #0]
|
|
8004b86: 2220 movs r2, #32
|
|
8004b88: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8004b8a: 68fb ldr r3, [r7, #12]
|
|
8004b8c: 681b ldr r3, [r3, #0]
|
|
8004b8e: 6859 ldr r1, [r3, #4]
|
|
8004b90: 68fb ldr r3, [r7, #12]
|
|
8004b92: 681a ldr r2, [r3, #0]
|
|
8004b94: 4b0a ldr r3, [pc, #40] @ (8004bc0 <HAL_I2C_Mem_Write+0x224>)
|
|
8004b96: 400b ands r3, r1
|
|
8004b98: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004b9a: 68fb ldr r3, [r7, #12]
|
|
8004b9c: 2220 movs r2, #32
|
|
8004b9e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004ba2: 68fb ldr r3, [r7, #12]
|
|
8004ba4: 2200 movs r2, #0
|
|
8004ba6: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004baa: 68fb ldr r3, [r7, #12]
|
|
8004bac: 2200 movs r2, #0
|
|
8004bae: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8004bb2: 2300 movs r3, #0
|
|
8004bb4: e000 b.n 8004bb8 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004bb6: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004bb8: 4618 mov r0, r3
|
|
8004bba: 3718 adds r7, #24
|
|
8004bbc: 46bd mov sp, r7
|
|
8004bbe: bd80 pop {r7, pc}
|
|
8004bc0: fe00e800 .word 0xfe00e800
|
|
|
|
08004bc4 <HAL_I2C_Mem_Read>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8004bc4: b580 push {r7, lr}
|
|
8004bc6: b088 sub sp, #32
|
|
8004bc8: af02 add r7, sp, #8
|
|
8004bca: 60f8 str r0, [r7, #12]
|
|
8004bcc: 4608 mov r0, r1
|
|
8004bce: 4611 mov r1, r2
|
|
8004bd0: 461a mov r2, r3
|
|
8004bd2: 4603 mov r3, r0
|
|
8004bd4: 817b strh r3, [r7, #10]
|
|
8004bd6: 460b mov r3, r1
|
|
8004bd8: 813b strh r3, [r7, #8]
|
|
8004bda: 4613 mov r3, r2
|
|
8004bdc: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8004bde: 68fb ldr r3, [r7, #12]
|
|
8004be0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004be4: b2db uxtb r3, r3
|
|
8004be6: 2b20 cmp r3, #32
|
|
8004be8: f040 80fd bne.w 8004de6 <HAL_I2C_Mem_Read+0x222>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004bec: 6a3b ldr r3, [r7, #32]
|
|
8004bee: 2b00 cmp r3, #0
|
|
8004bf0: d002 beq.n 8004bf8 <HAL_I2C_Mem_Read+0x34>
|
|
8004bf2: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
8004bf4: 2b00 cmp r3, #0
|
|
8004bf6: d105 bne.n 8004c04 <HAL_I2C_Mem_Read+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8004bf8: 68fb ldr r3, [r7, #12]
|
|
8004bfa: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8004bfe: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
8004c00: 2301 movs r3, #1
|
|
8004c02: e0f1 b.n 8004de8 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8004c04: 68fb ldr r3, [r7, #12]
|
|
8004c06: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8004c0a: 2b01 cmp r3, #1
|
|
8004c0c: d101 bne.n 8004c12 <HAL_I2C_Mem_Read+0x4e>
|
|
8004c0e: 2302 movs r3, #2
|
|
8004c10: e0ea b.n 8004de8 <HAL_I2C_Mem_Read+0x224>
|
|
8004c12: 68fb ldr r3, [r7, #12]
|
|
8004c14: 2201 movs r2, #1
|
|
8004c16: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8004c1a: f7ff f871 bl 8003d00 <HAL_GetTick>
|
|
8004c1e: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8004c20: 697b ldr r3, [r7, #20]
|
|
8004c22: 9300 str r3, [sp, #0]
|
|
8004c24: 2319 movs r3, #25
|
|
8004c26: 2201 movs r2, #1
|
|
8004c28: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
8004c2c: 68f8 ldr r0, [r7, #12]
|
|
8004c2e: f000 f9af bl 8004f90 <I2C_WaitOnFlagUntilTimeout>
|
|
8004c32: 4603 mov r3, r0
|
|
8004c34: 2b00 cmp r3, #0
|
|
8004c36: d001 beq.n 8004c3c <HAL_I2C_Mem_Read+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8004c38: 2301 movs r3, #1
|
|
8004c3a: e0d5 b.n 8004de8 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
8004c3c: 68fb ldr r3, [r7, #12]
|
|
8004c3e: 2222 movs r2, #34 @ 0x22
|
|
8004c40: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8004c44: 68fb ldr r3, [r7, #12]
|
|
8004c46: 2240 movs r2, #64 @ 0x40
|
|
8004c48: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8004c4c: 68fb ldr r3, [r7, #12]
|
|
8004c4e: 2200 movs r2, #0
|
|
8004c50: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8004c52: 68fb ldr r3, [r7, #12]
|
|
8004c54: 6a3a ldr r2, [r7, #32]
|
|
8004c56: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8004c58: 68fb ldr r3, [r7, #12]
|
|
8004c5a: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
8004c5c: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8004c5e: 68fb ldr r3, [r7, #12]
|
|
8004c60: 2200 movs r2, #0
|
|
8004c62: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8004c64: 88f8 ldrh r0, [r7, #6]
|
|
8004c66: 893a ldrh r2, [r7, #8]
|
|
8004c68: 8979 ldrh r1, [r7, #10]
|
|
8004c6a: 697b ldr r3, [r7, #20]
|
|
8004c6c: 9301 str r3, [sp, #4]
|
|
8004c6e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004c70: 9300 str r3, [sp, #0]
|
|
8004c72: 4603 mov r3, r0
|
|
8004c74: 68f8 ldr r0, [r7, #12]
|
|
8004c76: f000 f913 bl 8004ea0 <I2C_RequestMemoryRead>
|
|
8004c7a: 4603 mov r3, r0
|
|
8004c7c: 2b00 cmp r3, #0
|
|
8004c7e: d005 beq.n 8004c8c <HAL_I2C_Mem_Read+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004c80: 68fb ldr r3, [r7, #12]
|
|
8004c82: 2200 movs r2, #0
|
|
8004c84: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8004c88: 2301 movs r3, #1
|
|
8004c8a: e0ad b.n 8004de8 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Send Slave Address */
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8004c8c: 68fb ldr r3, [r7, #12]
|
|
8004c8e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004c90: b29b uxth r3, r3
|
|
8004c92: 2bff cmp r3, #255 @ 0xff
|
|
8004c94: d90e bls.n 8004cb4 <HAL_I2C_Mem_Read+0xf0>
|
|
{
|
|
hi2c->XferSize = 1U;
|
|
8004c96: 68fb ldr r3, [r7, #12]
|
|
8004c98: 2201 movs r2, #1
|
|
8004c9a: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8004c9c: 68fb ldr r3, [r7, #12]
|
|
8004c9e: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004ca0: b2da uxtb r2, r3
|
|
8004ca2: 8979 ldrh r1, [r7, #10]
|
|
8004ca4: 4b52 ldr r3, [pc, #328] @ (8004df0 <HAL_I2C_Mem_Read+0x22c>)
|
|
8004ca6: 9300 str r3, [sp, #0]
|
|
8004ca8: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8004cac: 68f8 ldr r0, [r7, #12]
|
|
8004cae: f000 fb33 bl 8005318 <I2C_TransferConfig>
|
|
8004cb2: e00f b.n 8004cd4 <HAL_I2C_Mem_Read+0x110>
|
|
I2C_GENERATE_START_READ);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8004cb4: 68fb ldr r3, [r7, #12]
|
|
8004cb6: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004cb8: b29a uxth r2, r3
|
|
8004cba: 68fb ldr r3, [r7, #12]
|
|
8004cbc: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8004cbe: 68fb ldr r3, [r7, #12]
|
|
8004cc0: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004cc2: b2da uxtb r2, r3
|
|
8004cc4: 8979 ldrh r1, [r7, #10]
|
|
8004cc6: 4b4a ldr r3, [pc, #296] @ (8004df0 <HAL_I2C_Mem_Read+0x22c>)
|
|
8004cc8: 9300 str r3, [sp, #0]
|
|
8004cca: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8004cce: 68f8 ldr r0, [r7, #12]
|
|
8004cd0: f000 fb22 bl 8005318 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
|
|
8004cd4: 697b ldr r3, [r7, #20]
|
|
8004cd6: 9300 str r3, [sp, #0]
|
|
8004cd8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004cda: 2200 movs r2, #0
|
|
8004cdc: 2104 movs r1, #4
|
|
8004cde: 68f8 ldr r0, [r7, #12]
|
|
8004ce0: f000 f956 bl 8004f90 <I2C_WaitOnFlagUntilTimeout>
|
|
8004ce4: 4603 mov r3, r0
|
|
8004ce6: 2b00 cmp r3, #0
|
|
8004ce8: d001 beq.n 8004cee <HAL_I2C_Mem_Read+0x12a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004cea: 2301 movs r3, #1
|
|
8004cec: e07c b.n 8004de8 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
8004cee: 68fb ldr r3, [r7, #12]
|
|
8004cf0: 681b ldr r3, [r3, #0]
|
|
8004cf2: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8004cf4: 68fb ldr r3, [r7, #12]
|
|
8004cf6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004cf8: b2d2 uxtb r2, r2
|
|
8004cfa: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8004cfc: 68fb ldr r3, [r7, #12]
|
|
8004cfe: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004d00: 1c5a adds r2, r3, #1
|
|
8004d02: 68fb ldr r3, [r7, #12]
|
|
8004d04: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferSize--;
|
|
8004d06: 68fb ldr r3, [r7, #12]
|
|
8004d08: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004d0a: 3b01 subs r3, #1
|
|
8004d0c: b29a uxth r2, r3
|
|
8004d0e: 68fb ldr r3, [r7, #12]
|
|
8004d10: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
8004d12: 68fb ldr r3, [r7, #12]
|
|
8004d14: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004d16: b29b uxth r3, r3
|
|
8004d18: 3b01 subs r3, #1
|
|
8004d1a: b29a uxth r2, r3
|
|
8004d1c: 68fb ldr r3, [r7, #12]
|
|
8004d1e: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8004d20: 68fb ldr r3, [r7, #12]
|
|
8004d22: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004d24: b29b uxth r3, r3
|
|
8004d26: 2b00 cmp r3, #0
|
|
8004d28: d034 beq.n 8004d94 <HAL_I2C_Mem_Read+0x1d0>
|
|
8004d2a: 68fb ldr r3, [r7, #12]
|
|
8004d2c: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004d2e: 2b00 cmp r3, #0
|
|
8004d30: d130 bne.n 8004d94 <HAL_I2C_Mem_Read+0x1d0>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8004d32: 697b ldr r3, [r7, #20]
|
|
8004d34: 9300 str r3, [sp, #0]
|
|
8004d36: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004d38: 2200 movs r2, #0
|
|
8004d3a: 2180 movs r1, #128 @ 0x80
|
|
8004d3c: 68f8 ldr r0, [r7, #12]
|
|
8004d3e: f000 f927 bl 8004f90 <I2C_WaitOnFlagUntilTimeout>
|
|
8004d42: 4603 mov r3, r0
|
|
8004d44: 2b00 cmp r3, #0
|
|
8004d46: d001 beq.n 8004d4c <HAL_I2C_Mem_Read+0x188>
|
|
{
|
|
return HAL_ERROR;
|
|
8004d48: 2301 movs r3, #1
|
|
8004d4a: e04d b.n 8004de8 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8004d4c: 68fb ldr r3, [r7, #12]
|
|
8004d4e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004d50: b29b uxth r3, r3
|
|
8004d52: 2bff cmp r3, #255 @ 0xff
|
|
8004d54: d90e bls.n 8004d74 <HAL_I2C_Mem_Read+0x1b0>
|
|
{
|
|
hi2c->XferSize = 1U;
|
|
8004d56: 68fb ldr r3, [r7, #12]
|
|
8004d58: 2201 movs r2, #1
|
|
8004d5a: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8004d5c: 68fb ldr r3, [r7, #12]
|
|
8004d5e: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004d60: b2da uxtb r2, r3
|
|
8004d62: 8979 ldrh r1, [r7, #10]
|
|
8004d64: 2300 movs r3, #0
|
|
8004d66: 9300 str r3, [sp, #0]
|
|
8004d68: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8004d6c: 68f8 ldr r0, [r7, #12]
|
|
8004d6e: f000 fad3 bl 8005318 <I2C_TransferConfig>
|
|
8004d72: e00f b.n 8004d94 <HAL_I2C_Mem_Read+0x1d0>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8004d74: 68fb ldr r3, [r7, #12]
|
|
8004d76: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004d78: b29a uxth r2, r3
|
|
8004d7a: 68fb ldr r3, [r7, #12]
|
|
8004d7c: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8004d7e: 68fb ldr r3, [r7, #12]
|
|
8004d80: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004d82: b2da uxtb r2, r3
|
|
8004d84: 8979 ldrh r1, [r7, #10]
|
|
8004d86: 2300 movs r3, #0
|
|
8004d88: 9300 str r3, [sp, #0]
|
|
8004d8a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8004d8e: 68f8 ldr r0, [r7, #12]
|
|
8004d90: f000 fac2 bl 8005318 <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
} while (hi2c->XferCount > 0U);
|
|
8004d94: 68fb ldr r3, [r7, #12]
|
|
8004d96: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004d98: b29b uxth r3, r3
|
|
8004d9a: 2b00 cmp r3, #0
|
|
8004d9c: d19a bne.n 8004cd4 <HAL_I2C_Mem_Read+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8004d9e: 697a ldr r2, [r7, #20]
|
|
8004da0: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8004da2: 68f8 ldr r0, [r7, #12]
|
|
8004da4: f000 f994 bl 80050d0 <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8004da8: 4603 mov r3, r0
|
|
8004daa: 2b00 cmp r3, #0
|
|
8004dac: d001 beq.n 8004db2 <HAL_I2C_Mem_Read+0x1ee>
|
|
{
|
|
return HAL_ERROR;
|
|
8004dae: 2301 movs r3, #1
|
|
8004db0: e01a b.n 8004de8 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8004db2: 68fb ldr r3, [r7, #12]
|
|
8004db4: 681b ldr r3, [r3, #0]
|
|
8004db6: 2220 movs r2, #32
|
|
8004db8: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8004dba: 68fb ldr r3, [r7, #12]
|
|
8004dbc: 681b ldr r3, [r3, #0]
|
|
8004dbe: 6859 ldr r1, [r3, #4]
|
|
8004dc0: 68fb ldr r3, [r7, #12]
|
|
8004dc2: 681a ldr r2, [r3, #0]
|
|
8004dc4: 4b0b ldr r3, [pc, #44] @ (8004df4 <HAL_I2C_Mem_Read+0x230>)
|
|
8004dc6: 400b ands r3, r1
|
|
8004dc8: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004dca: 68fb ldr r3, [r7, #12]
|
|
8004dcc: 2220 movs r2, #32
|
|
8004dce: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004dd2: 68fb ldr r3, [r7, #12]
|
|
8004dd4: 2200 movs r2, #0
|
|
8004dd6: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004dda: 68fb ldr r3, [r7, #12]
|
|
8004ddc: 2200 movs r2, #0
|
|
8004dde: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8004de2: 2300 movs r3, #0
|
|
8004de4: e000 b.n 8004de8 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004de6: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004de8: 4618 mov r0, r3
|
|
8004dea: 3718 adds r7, #24
|
|
8004dec: 46bd mov sp, r7
|
|
8004dee: bd80 pop {r7, pc}
|
|
8004df0: 80002400 .word 0x80002400
|
|
8004df4: fe00e800 .word 0xfe00e800
|
|
|
|
08004df8 <I2C_RequestMemoryWrite>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8004df8: b580 push {r7, lr}
|
|
8004dfa: b086 sub sp, #24
|
|
8004dfc: af02 add r7, sp, #8
|
|
8004dfe: 60f8 str r0, [r7, #12]
|
|
8004e00: 4608 mov r0, r1
|
|
8004e02: 4611 mov r1, r2
|
|
8004e04: 461a mov r2, r3
|
|
8004e06: 4603 mov r3, r0
|
|
8004e08: 817b strh r3, [r7, #10]
|
|
8004e0a: 460b mov r3, r1
|
|
8004e0c: 813b strh r3, [r7, #8]
|
|
8004e0e: 4613 mov r3, r2
|
|
8004e10: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
|
8004e12: 88fb ldrh r3, [r7, #6]
|
|
8004e14: b2da uxtb r2, r3
|
|
8004e16: 8979 ldrh r1, [r7, #10]
|
|
8004e18: 4b20 ldr r3, [pc, #128] @ (8004e9c <I2C_RequestMemoryWrite+0xa4>)
|
|
8004e1a: 9300 str r3, [sp, #0]
|
|
8004e1c: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8004e20: 68f8 ldr r0, [r7, #12]
|
|
8004e22: f000 fa79 bl 8005318 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8004e26: 69fa ldr r2, [r7, #28]
|
|
8004e28: 69b9 ldr r1, [r7, #24]
|
|
8004e2a: 68f8 ldr r0, [r7, #12]
|
|
8004e2c: f000 f909 bl 8005042 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8004e30: 4603 mov r3, r0
|
|
8004e32: 2b00 cmp r3, #0
|
|
8004e34: d001 beq.n 8004e3a <I2C_RequestMemoryWrite+0x42>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e36: 2301 movs r3, #1
|
|
8004e38: e02c b.n 8004e94 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
8004e3a: 88fb ldrh r3, [r7, #6]
|
|
8004e3c: 2b01 cmp r3, #1
|
|
8004e3e: d105 bne.n 8004e4c <I2C_RequestMemoryWrite+0x54>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8004e40: 893b ldrh r3, [r7, #8]
|
|
8004e42: b2da uxtb r2, r3
|
|
8004e44: 68fb ldr r3, [r7, #12]
|
|
8004e46: 681b ldr r3, [r3, #0]
|
|
8004e48: 629a str r2, [r3, #40] @ 0x28
|
|
8004e4a: e015 b.n 8004e78 <I2C_RequestMemoryWrite+0x80>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
8004e4c: 893b ldrh r3, [r7, #8]
|
|
8004e4e: 0a1b lsrs r3, r3, #8
|
|
8004e50: b29b uxth r3, r3
|
|
8004e52: b2da uxtb r2, r3
|
|
8004e54: 68fb ldr r3, [r7, #12]
|
|
8004e56: 681b ldr r3, [r3, #0]
|
|
8004e58: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8004e5a: 69fa ldr r2, [r7, #28]
|
|
8004e5c: 69b9 ldr r1, [r7, #24]
|
|
8004e5e: 68f8 ldr r0, [r7, #12]
|
|
8004e60: f000 f8ef bl 8005042 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8004e64: 4603 mov r3, r0
|
|
8004e66: 2b00 cmp r3, #0
|
|
8004e68: d001 beq.n 8004e6e <I2C_RequestMemoryWrite+0x76>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e6a: 2301 movs r3, #1
|
|
8004e6c: e012 b.n 8004e94 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8004e6e: 893b ldrh r3, [r7, #8]
|
|
8004e70: b2da uxtb r2, r3
|
|
8004e72: 68fb ldr r3, [r7, #12]
|
|
8004e74: 681b ldr r3, [r3, #0]
|
|
8004e76: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8004e78: 69fb ldr r3, [r7, #28]
|
|
8004e7a: 9300 str r3, [sp, #0]
|
|
8004e7c: 69bb ldr r3, [r7, #24]
|
|
8004e7e: 2200 movs r2, #0
|
|
8004e80: 2180 movs r1, #128 @ 0x80
|
|
8004e82: 68f8 ldr r0, [r7, #12]
|
|
8004e84: f000 f884 bl 8004f90 <I2C_WaitOnFlagUntilTimeout>
|
|
8004e88: 4603 mov r3, r0
|
|
8004e8a: 2b00 cmp r3, #0
|
|
8004e8c: d001 beq.n 8004e92 <I2C_RequestMemoryWrite+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e8e: 2301 movs r3, #1
|
|
8004e90: e000 b.n 8004e94 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8004e92: 2300 movs r3, #0
|
|
}
|
|
8004e94: 4618 mov r0, r3
|
|
8004e96: 3710 adds r7, #16
|
|
8004e98: 46bd mov sp, r7
|
|
8004e9a: bd80 pop {r7, pc}
|
|
8004e9c: 80002000 .word 0x80002000
|
|
|
|
08004ea0 <I2C_RequestMemoryRead>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8004ea0: b580 push {r7, lr}
|
|
8004ea2: b086 sub sp, #24
|
|
8004ea4: af02 add r7, sp, #8
|
|
8004ea6: 60f8 str r0, [r7, #12]
|
|
8004ea8: 4608 mov r0, r1
|
|
8004eaa: 4611 mov r1, r2
|
|
8004eac: 461a mov r2, r3
|
|
8004eae: 4603 mov r3, r0
|
|
8004eb0: 817b strh r3, [r7, #10]
|
|
8004eb2: 460b mov r3, r1
|
|
8004eb4: 813b strh r3, [r7, #8]
|
|
8004eb6: 4613 mov r3, r2
|
|
8004eb8: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
|
8004eba: 88fb ldrh r3, [r7, #6]
|
|
8004ebc: b2da uxtb r2, r3
|
|
8004ebe: 8979 ldrh r1, [r7, #10]
|
|
8004ec0: 4b20 ldr r3, [pc, #128] @ (8004f44 <I2C_RequestMemoryRead+0xa4>)
|
|
8004ec2: 9300 str r3, [sp, #0]
|
|
8004ec4: 2300 movs r3, #0
|
|
8004ec6: 68f8 ldr r0, [r7, #12]
|
|
8004ec8: f000 fa26 bl 8005318 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8004ecc: 69fa ldr r2, [r7, #28]
|
|
8004ece: 69b9 ldr r1, [r7, #24]
|
|
8004ed0: 68f8 ldr r0, [r7, #12]
|
|
8004ed2: f000 f8b6 bl 8005042 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8004ed6: 4603 mov r3, r0
|
|
8004ed8: 2b00 cmp r3, #0
|
|
8004eda: d001 beq.n 8004ee0 <I2C_RequestMemoryRead+0x40>
|
|
{
|
|
return HAL_ERROR;
|
|
8004edc: 2301 movs r3, #1
|
|
8004ede: e02c b.n 8004f3a <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
8004ee0: 88fb ldrh r3, [r7, #6]
|
|
8004ee2: 2b01 cmp r3, #1
|
|
8004ee4: d105 bne.n 8004ef2 <I2C_RequestMemoryRead+0x52>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8004ee6: 893b ldrh r3, [r7, #8]
|
|
8004ee8: b2da uxtb r2, r3
|
|
8004eea: 68fb ldr r3, [r7, #12]
|
|
8004eec: 681b ldr r3, [r3, #0]
|
|
8004eee: 629a str r2, [r3, #40] @ 0x28
|
|
8004ef0: e015 b.n 8004f1e <I2C_RequestMemoryRead+0x7e>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
8004ef2: 893b ldrh r3, [r7, #8]
|
|
8004ef4: 0a1b lsrs r3, r3, #8
|
|
8004ef6: b29b uxth r3, r3
|
|
8004ef8: b2da uxtb r2, r3
|
|
8004efa: 68fb ldr r3, [r7, #12]
|
|
8004efc: 681b ldr r3, [r3, #0]
|
|
8004efe: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8004f00: 69fa ldr r2, [r7, #28]
|
|
8004f02: 69b9 ldr r1, [r7, #24]
|
|
8004f04: 68f8 ldr r0, [r7, #12]
|
|
8004f06: f000 f89c bl 8005042 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8004f0a: 4603 mov r3, r0
|
|
8004f0c: 2b00 cmp r3, #0
|
|
8004f0e: d001 beq.n 8004f14 <I2C_RequestMemoryRead+0x74>
|
|
{
|
|
return HAL_ERROR;
|
|
8004f10: 2301 movs r3, #1
|
|
8004f12: e012 b.n 8004f3a <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8004f14: 893b ldrh r3, [r7, #8]
|
|
8004f16: b2da uxtb r2, r3
|
|
8004f18: 68fb ldr r3, [r7, #12]
|
|
8004f1a: 681b ldr r3, [r3, #0]
|
|
8004f1c: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until TC flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8004f1e: 69fb ldr r3, [r7, #28]
|
|
8004f20: 9300 str r3, [sp, #0]
|
|
8004f22: 69bb ldr r3, [r7, #24]
|
|
8004f24: 2200 movs r2, #0
|
|
8004f26: 2140 movs r1, #64 @ 0x40
|
|
8004f28: 68f8 ldr r0, [r7, #12]
|
|
8004f2a: f000 f831 bl 8004f90 <I2C_WaitOnFlagUntilTimeout>
|
|
8004f2e: 4603 mov r3, r0
|
|
8004f30: 2b00 cmp r3, #0
|
|
8004f32: d001 beq.n 8004f38 <I2C_RequestMemoryRead+0x98>
|
|
{
|
|
return HAL_ERROR;
|
|
8004f34: 2301 movs r3, #1
|
|
8004f36: e000 b.n 8004f3a <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8004f38: 2300 movs r3, #0
|
|
}
|
|
8004f3a: 4618 mov r0, r3
|
|
8004f3c: 3710 adds r7, #16
|
|
8004f3e: 46bd mov sp, r7
|
|
8004f40: bd80 pop {r7, pc}
|
|
8004f42: bf00 nop
|
|
8004f44: 80002000 .word 0x80002000
|
|
|
|
08004f48 <I2C_Flush_TXDR>:
|
|
* @brief I2C Tx data register flush process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8004f48: b480 push {r7}
|
|
8004f4a: b083 sub sp, #12
|
|
8004f4c: af00 add r7, sp, #0
|
|
8004f4e: 6078 str r0, [r7, #4]
|
|
/* If a pending TXIS flag is set */
|
|
/* Write a dummy data in TXDR to clear it */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
|
|
8004f50: 687b ldr r3, [r7, #4]
|
|
8004f52: 681b ldr r3, [r3, #0]
|
|
8004f54: 699b ldr r3, [r3, #24]
|
|
8004f56: f003 0302 and.w r3, r3, #2
|
|
8004f5a: 2b02 cmp r3, #2
|
|
8004f5c: d103 bne.n 8004f66 <I2C_Flush_TXDR+0x1e>
|
|
{
|
|
hi2c->Instance->TXDR = 0x00U;
|
|
8004f5e: 687b ldr r3, [r7, #4]
|
|
8004f60: 681b ldr r3, [r3, #0]
|
|
8004f62: 2200 movs r2, #0
|
|
8004f64: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Flush TX register if not empty */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
8004f66: 687b ldr r3, [r7, #4]
|
|
8004f68: 681b ldr r3, [r3, #0]
|
|
8004f6a: 699b ldr r3, [r3, #24]
|
|
8004f6c: f003 0301 and.w r3, r3, #1
|
|
8004f70: 2b01 cmp r3, #1
|
|
8004f72: d007 beq.n 8004f84 <I2C_Flush_TXDR+0x3c>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
|
|
8004f74: 687b ldr r3, [r7, #4]
|
|
8004f76: 681b ldr r3, [r3, #0]
|
|
8004f78: 699a ldr r2, [r3, #24]
|
|
8004f7a: 687b ldr r3, [r7, #4]
|
|
8004f7c: 681b ldr r3, [r3, #0]
|
|
8004f7e: f042 0201 orr.w r2, r2, #1
|
|
8004f82: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
8004f84: bf00 nop
|
|
8004f86: 370c adds r7, #12
|
|
8004f88: 46bd mov sp, r7
|
|
8004f8a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004f8e: 4770 bx lr
|
|
|
|
08004f90 <I2C_WaitOnFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8004f90: b580 push {r7, lr}
|
|
8004f92: b084 sub sp, #16
|
|
8004f94: af00 add r7, sp, #0
|
|
8004f96: 60f8 str r0, [r7, #12]
|
|
8004f98: 60b9 str r1, [r7, #8]
|
|
8004f9a: 603b str r3, [r7, #0]
|
|
8004f9c: 4613 mov r3, r2
|
|
8004f9e: 71fb strb r3, [r7, #7]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
8004fa0: e03b b.n 800501a <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8004fa2: 69ba ldr r2, [r7, #24]
|
|
8004fa4: 6839 ldr r1, [r7, #0]
|
|
8004fa6: 68f8 ldr r0, [r7, #12]
|
|
8004fa8: f000 f8d6 bl 8005158 <I2C_IsErrorOccurred>
|
|
8004fac: 4603 mov r3, r0
|
|
8004fae: 2b00 cmp r3, #0
|
|
8004fb0: d001 beq.n 8004fb6 <I2C_WaitOnFlagUntilTimeout+0x26>
|
|
{
|
|
return HAL_ERROR;
|
|
8004fb2: 2301 movs r3, #1
|
|
8004fb4: e041 b.n 800503a <I2C_WaitOnFlagUntilTimeout+0xaa>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8004fb6: 683b ldr r3, [r7, #0]
|
|
8004fb8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8004fbc: d02d beq.n 800501a <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8004fbe: f7fe fe9f bl 8003d00 <HAL_GetTick>
|
|
8004fc2: 4602 mov r2, r0
|
|
8004fc4: 69bb ldr r3, [r7, #24]
|
|
8004fc6: 1ad3 subs r3, r2, r3
|
|
8004fc8: 683a ldr r2, [r7, #0]
|
|
8004fca: 429a cmp r2, r3
|
|
8004fcc: d302 bcc.n 8004fd4 <I2C_WaitOnFlagUntilTimeout+0x44>
|
|
8004fce: 683b ldr r3, [r7, #0]
|
|
8004fd0: 2b00 cmp r3, #0
|
|
8004fd2: d122 bne.n 800501a <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
|
|
8004fd4: 68fb ldr r3, [r7, #12]
|
|
8004fd6: 681b ldr r3, [r3, #0]
|
|
8004fd8: 699a ldr r2, [r3, #24]
|
|
8004fda: 68bb ldr r3, [r7, #8]
|
|
8004fdc: 4013 ands r3, r2
|
|
8004fde: 68ba ldr r2, [r7, #8]
|
|
8004fe0: 429a cmp r2, r3
|
|
8004fe2: bf0c ite eq
|
|
8004fe4: 2301 moveq r3, #1
|
|
8004fe6: 2300 movne r3, #0
|
|
8004fe8: b2db uxtb r3, r3
|
|
8004fea: 461a mov r2, r3
|
|
8004fec: 79fb ldrb r3, [r7, #7]
|
|
8004fee: 429a cmp r2, r3
|
|
8004ff0: d113 bne.n 800501a <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8004ff2: 68fb ldr r3, [r7, #12]
|
|
8004ff4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8004ff6: f043 0220 orr.w r2, r3, #32
|
|
8004ffa: 68fb ldr r3, [r7, #12]
|
|
8004ffc: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004ffe: 68fb ldr r3, [r7, #12]
|
|
8005000: 2220 movs r2, #32
|
|
8005002: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8005006: 68fb ldr r3, [r7, #12]
|
|
8005008: 2200 movs r2, #0
|
|
800500a: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800500e: 68fb ldr r3, [r7, #12]
|
|
8005010: 2200 movs r2, #0
|
|
8005012: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8005016: 2301 movs r3, #1
|
|
8005018: e00f b.n 800503a <I2C_WaitOnFlagUntilTimeout+0xaa>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
800501a: 68fb ldr r3, [r7, #12]
|
|
800501c: 681b ldr r3, [r3, #0]
|
|
800501e: 699a ldr r2, [r3, #24]
|
|
8005020: 68bb ldr r3, [r7, #8]
|
|
8005022: 4013 ands r3, r2
|
|
8005024: 68ba ldr r2, [r7, #8]
|
|
8005026: 429a cmp r2, r3
|
|
8005028: bf0c ite eq
|
|
800502a: 2301 moveq r3, #1
|
|
800502c: 2300 movne r3, #0
|
|
800502e: b2db uxtb r3, r3
|
|
8005030: 461a mov r2, r3
|
|
8005032: 79fb ldrb r3, [r7, #7]
|
|
8005034: 429a cmp r2, r3
|
|
8005036: d0b4 beq.n 8004fa2 <I2C_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8005038: 2300 movs r3, #0
|
|
}
|
|
800503a: 4618 mov r0, r3
|
|
800503c: 3710 adds r7, #16
|
|
800503e: 46bd mov sp, r7
|
|
8005040: bd80 pop {r7, pc}
|
|
|
|
08005042 <I2C_WaitOnTXISFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8005042: b580 push {r7, lr}
|
|
8005044: b084 sub sp, #16
|
|
8005046: af00 add r7, sp, #0
|
|
8005048: 60f8 str r0, [r7, #12]
|
|
800504a: 60b9 str r1, [r7, #8]
|
|
800504c: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
800504e: e033 b.n 80050b8 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8005050: 687a ldr r2, [r7, #4]
|
|
8005052: 68b9 ldr r1, [r7, #8]
|
|
8005054: 68f8 ldr r0, [r7, #12]
|
|
8005056: f000 f87f bl 8005158 <I2C_IsErrorOccurred>
|
|
800505a: 4603 mov r3, r0
|
|
800505c: 2b00 cmp r3, #0
|
|
800505e: d001 beq.n 8005064 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
8005060: 2301 movs r3, #1
|
|
8005062: e031 b.n 80050c8 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8005064: 68bb ldr r3, [r7, #8]
|
|
8005066: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800506a: d025 beq.n 80050b8 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
800506c: f7fe fe48 bl 8003d00 <HAL_GetTick>
|
|
8005070: 4602 mov r2, r0
|
|
8005072: 687b ldr r3, [r7, #4]
|
|
8005074: 1ad3 subs r3, r2, r3
|
|
8005076: 68ba ldr r2, [r7, #8]
|
|
8005078: 429a cmp r2, r3
|
|
800507a: d302 bcc.n 8005082 <I2C_WaitOnTXISFlagUntilTimeout+0x40>
|
|
800507c: 68bb ldr r3, [r7, #8]
|
|
800507e: 2b00 cmp r3, #0
|
|
8005080: d11a bne.n 80050b8 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
|
|
8005082: 68fb ldr r3, [r7, #12]
|
|
8005084: 681b ldr r3, [r3, #0]
|
|
8005086: 699b ldr r3, [r3, #24]
|
|
8005088: f003 0302 and.w r3, r3, #2
|
|
800508c: 2b02 cmp r3, #2
|
|
800508e: d013 beq.n 80050b8 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8005090: 68fb ldr r3, [r7, #12]
|
|
8005092: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005094: f043 0220 orr.w r2, r3, #32
|
|
8005098: 68fb ldr r3, [r7, #12]
|
|
800509a: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800509c: 68fb ldr r3, [r7, #12]
|
|
800509e: 2220 movs r2, #32
|
|
80050a0: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80050a4: 68fb ldr r3, [r7, #12]
|
|
80050a6: 2200 movs r2, #0
|
|
80050a8: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80050ac: 68fb ldr r3, [r7, #12]
|
|
80050ae: 2200 movs r2, #0
|
|
80050b0: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
80050b4: 2301 movs r3, #1
|
|
80050b6: e007 b.n 80050c8 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
80050b8: 68fb ldr r3, [r7, #12]
|
|
80050ba: 681b ldr r3, [r3, #0]
|
|
80050bc: 699b ldr r3, [r3, #24]
|
|
80050be: f003 0302 and.w r3, r3, #2
|
|
80050c2: 2b02 cmp r3, #2
|
|
80050c4: d1c4 bne.n 8005050 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80050c6: 2300 movs r3, #0
|
|
}
|
|
80050c8: 4618 mov r0, r3
|
|
80050ca: 3710 adds r7, #16
|
|
80050cc: 46bd mov sp, r7
|
|
80050ce: bd80 pop {r7, pc}
|
|
|
|
080050d0 <I2C_WaitOnSTOPFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
80050d0: b580 push {r7, lr}
|
|
80050d2: b084 sub sp, #16
|
|
80050d4: af00 add r7, sp, #0
|
|
80050d6: 60f8 str r0, [r7, #12]
|
|
80050d8: 60b9 str r1, [r7, #8]
|
|
80050da: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80050dc: e02f b.n 800513e <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80050de: 687a ldr r2, [r7, #4]
|
|
80050e0: 68b9 ldr r1, [r7, #8]
|
|
80050e2: 68f8 ldr r0, [r7, #12]
|
|
80050e4: f000 f838 bl 8005158 <I2C_IsErrorOccurred>
|
|
80050e8: 4603 mov r3, r0
|
|
80050ea: 2b00 cmp r3, #0
|
|
80050ec: d001 beq.n 80050f2 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
80050ee: 2301 movs r3, #1
|
|
80050f0: e02d b.n 800514e <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80050f2: f7fe fe05 bl 8003d00 <HAL_GetTick>
|
|
80050f6: 4602 mov r2, r0
|
|
80050f8: 687b ldr r3, [r7, #4]
|
|
80050fa: 1ad3 subs r3, r2, r3
|
|
80050fc: 68ba ldr r2, [r7, #8]
|
|
80050fe: 429a cmp r2, r3
|
|
8005100: d302 bcc.n 8005108 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
|
|
8005102: 68bb ldr r3, [r7, #8]
|
|
8005104: 2b00 cmp r3, #0
|
|
8005106: d11a bne.n 800513e <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
|
|
8005108: 68fb ldr r3, [r7, #12]
|
|
800510a: 681b ldr r3, [r3, #0]
|
|
800510c: 699b ldr r3, [r3, #24]
|
|
800510e: f003 0320 and.w r3, r3, #32
|
|
8005112: 2b20 cmp r3, #32
|
|
8005114: d013 beq.n 800513e <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8005116: 68fb ldr r3, [r7, #12]
|
|
8005118: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800511a: f043 0220 orr.w r2, r3, #32
|
|
800511e: 68fb ldr r3, [r7, #12]
|
|
8005120: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8005122: 68fb ldr r3, [r7, #12]
|
|
8005124: 2220 movs r2, #32
|
|
8005126: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800512a: 68fb ldr r3, [r7, #12]
|
|
800512c: 2200 movs r2, #0
|
|
800512e: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8005132: 68fb ldr r3, [r7, #12]
|
|
8005134: 2200 movs r2, #0
|
|
8005136: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
800513a: 2301 movs r3, #1
|
|
800513c: e007 b.n 800514e <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
800513e: 68fb ldr r3, [r7, #12]
|
|
8005140: 681b ldr r3, [r3, #0]
|
|
8005142: 699b ldr r3, [r3, #24]
|
|
8005144: f003 0320 and.w r3, r3, #32
|
|
8005148: 2b20 cmp r3, #32
|
|
800514a: d1c8 bne.n 80050de <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800514c: 2300 movs r3, #0
|
|
}
|
|
800514e: 4618 mov r0, r3
|
|
8005150: 3710 adds r7, #16
|
|
8005152: 46bd mov sp, r7
|
|
8005154: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08005158 <I2C_IsErrorOccurred>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8005158: b580 push {r7, lr}
|
|
800515a: b08a sub sp, #40 @ 0x28
|
|
800515c: af00 add r7, sp, #0
|
|
800515e: 60f8 str r0, [r7, #12]
|
|
8005160: 60b9 str r1, [r7, #8]
|
|
8005162: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8005164: 2300 movs r3, #0
|
|
8005166: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
uint32_t itflag = hi2c->Instance->ISR;
|
|
800516a: 68fb ldr r3, [r7, #12]
|
|
800516c: 681b ldr r3, [r3, #0]
|
|
800516e: 699b ldr r3, [r3, #24]
|
|
8005170: 61bb str r3, [r7, #24]
|
|
uint32_t error_code = 0;
|
|
8005172: 2300 movs r3, #0
|
|
8005174: 623b str r3, [r7, #32]
|
|
uint32_t tickstart = Tickstart;
|
|
8005176: 687b ldr r3, [r7, #4]
|
|
8005178: 61fb str r3, [r7, #28]
|
|
uint32_t tmp1;
|
|
HAL_I2C_ModeTypeDef tmp2;
|
|
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
|
|
800517a: 69bb ldr r3, [r7, #24]
|
|
800517c: f003 0310 and.w r3, r3, #16
|
|
8005180: 2b00 cmp r3, #0
|
|
8005182: d068 beq.n 8005256 <I2C_IsErrorOccurred+0xfe>
|
|
{
|
|
/* Clear NACKF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8005184: 68fb ldr r3, [r7, #12]
|
|
8005186: 681b ldr r3, [r3, #0]
|
|
8005188: 2210 movs r2, #16
|
|
800518a: 61da str r2, [r3, #28]
|
|
|
|
/* Wait until STOP Flag is set or timeout occurred */
|
|
/* AutoEnd should be initiate after AF */
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
800518c: e049 b.n 8005222 <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800518e: 68bb ldr r3, [r7, #8]
|
|
8005190: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8005194: d045 beq.n 8005222 <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
|
8005196: f7fe fdb3 bl 8003d00 <HAL_GetTick>
|
|
800519a: 4602 mov r2, r0
|
|
800519c: 69fb ldr r3, [r7, #28]
|
|
800519e: 1ad3 subs r3, r2, r3
|
|
80051a0: 68ba ldr r2, [r7, #8]
|
|
80051a2: 429a cmp r2, r3
|
|
80051a4: d302 bcc.n 80051ac <I2C_IsErrorOccurred+0x54>
|
|
80051a6: 68bb ldr r3, [r7, #8]
|
|
80051a8: 2b00 cmp r3, #0
|
|
80051aa: d13a bne.n 8005222 <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
|
|
80051ac: 68fb ldr r3, [r7, #12]
|
|
80051ae: 681b ldr r3, [r3, #0]
|
|
80051b0: 685b ldr r3, [r3, #4]
|
|
80051b2: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80051b6: 617b str r3, [r7, #20]
|
|
tmp2 = hi2c->Mode;
|
|
80051b8: 68fb ldr r3, [r7, #12]
|
|
80051ba: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
80051be: 74fb strb r3, [r7, #19]
|
|
|
|
/* In case of I2C still busy, try to regenerate a STOP manually */
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
|
|
80051c0: 68fb ldr r3, [r7, #12]
|
|
80051c2: 681b ldr r3, [r3, #0]
|
|
80051c4: 699b ldr r3, [r3, #24]
|
|
80051c6: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80051ca: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80051ce: d121 bne.n 8005214 <I2C_IsErrorOccurred+0xbc>
|
|
80051d0: 697b ldr r3, [r7, #20]
|
|
80051d2: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
80051d6: d01d beq.n 8005214 <I2C_IsErrorOccurred+0xbc>
|
|
(tmp1 != I2C_CR2_STOP) && \
|
|
80051d8: 7cfb ldrb r3, [r7, #19]
|
|
80051da: 2b20 cmp r3, #32
|
|
80051dc: d01a beq.n 8005214 <I2C_IsErrorOccurred+0xbc>
|
|
(tmp2 != HAL_I2C_MODE_SLAVE))
|
|
{
|
|
/* Generate Stop */
|
|
hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
|
80051de: 68fb ldr r3, [r7, #12]
|
|
80051e0: 681b ldr r3, [r3, #0]
|
|
80051e2: 685a ldr r2, [r3, #4]
|
|
80051e4: 68fb ldr r3, [r7, #12]
|
|
80051e6: 681b ldr r3, [r3, #0]
|
|
80051e8: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
80051ec: 605a str r2, [r3, #4]
|
|
|
|
/* Update Tick with new reference */
|
|
tickstart = HAL_GetTick();
|
|
80051ee: f7fe fd87 bl 8003d00 <HAL_GetTick>
|
|
80051f2: 61f8 str r0, [r7, #28]
|
|
}
|
|
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80051f4: e00e b.n 8005214 <I2C_IsErrorOccurred+0xbc>
|
|
{
|
|
/* Check for the Timeout */
|
|
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
|
|
80051f6: f7fe fd83 bl 8003d00 <HAL_GetTick>
|
|
80051fa: 4602 mov r2, r0
|
|
80051fc: 69fb ldr r3, [r7, #28]
|
|
80051fe: 1ad3 subs r3, r2, r3
|
|
8005200: 2b19 cmp r3, #25
|
|
8005202: d907 bls.n 8005214 <I2C_IsErrorOccurred+0xbc>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_TIMEOUT;
|
|
8005204: 6a3b ldr r3, [r7, #32]
|
|
8005206: f043 0320 orr.w r3, r3, #32
|
|
800520a: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
800520c: 2301 movs r3, #1
|
|
800520e: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
|
|
break;
|
|
8005212: e006 b.n 8005222 <I2C_IsErrorOccurred+0xca>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8005214: 68fb ldr r3, [r7, #12]
|
|
8005216: 681b ldr r3, [r3, #0]
|
|
8005218: 699b ldr r3, [r3, #24]
|
|
800521a: f003 0320 and.w r3, r3, #32
|
|
800521e: 2b20 cmp r3, #32
|
|
8005220: d1e9 bne.n 80051f6 <I2C_IsErrorOccurred+0x9e>
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
8005222: 68fb ldr r3, [r7, #12]
|
|
8005224: 681b ldr r3, [r3, #0]
|
|
8005226: 699b ldr r3, [r3, #24]
|
|
8005228: f003 0320 and.w r3, r3, #32
|
|
800522c: 2b20 cmp r3, #32
|
|
800522e: d003 beq.n 8005238 <I2C_IsErrorOccurred+0xe0>
|
|
8005230: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8005234: 2b00 cmp r3, #0
|
|
8005236: d0aa beq.n 800518e <I2C_IsErrorOccurred+0x36>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* In case STOP Flag is detected, clear it */
|
|
if (status == HAL_OK)
|
|
8005238: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800523c: 2b00 cmp r3, #0
|
|
800523e: d103 bne.n 8005248 <I2C_IsErrorOccurred+0xf0>
|
|
{
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8005240: 68fb ldr r3, [r7, #12]
|
|
8005242: 681b ldr r3, [r3, #0]
|
|
8005244: 2220 movs r2, #32
|
|
8005246: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
error_code |= HAL_I2C_ERROR_AF;
|
|
8005248: 6a3b ldr r3, [r7, #32]
|
|
800524a: f043 0304 orr.w r3, r3, #4
|
|
800524e: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
8005250: 2301 movs r3, #1
|
|
8005252: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Refresh Content of Status register */
|
|
itflag = hi2c->Instance->ISR;
|
|
8005256: 68fb ldr r3, [r7, #12]
|
|
8005258: 681b ldr r3, [r3, #0]
|
|
800525a: 699b ldr r3, [r3, #24]
|
|
800525c: 61bb str r3, [r7, #24]
|
|
|
|
/* Then verify if an additional errors occurs */
|
|
/* Check if a Bus error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
|
|
800525e: 69bb ldr r3, [r7, #24]
|
|
8005260: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005264: 2b00 cmp r3, #0
|
|
8005266: d00b beq.n 8005280 <I2C_IsErrorOccurred+0x128>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_BERR;
|
|
8005268: 6a3b ldr r3, [r7, #32]
|
|
800526a: f043 0301 orr.w r3, r3, #1
|
|
800526e: 623b str r3, [r7, #32]
|
|
|
|
/* Clear BERR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
|
|
8005270: 68fb ldr r3, [r7, #12]
|
|
8005272: 681b ldr r3, [r3, #0]
|
|
8005274: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8005278: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
800527a: 2301 movs r3, #1
|
|
800527c: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Check if an Over-Run/Under-Run error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
|
|
8005280: 69bb ldr r3, [r7, #24]
|
|
8005282: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8005286: 2b00 cmp r3, #0
|
|
8005288: d00b beq.n 80052a2 <I2C_IsErrorOccurred+0x14a>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_OVR;
|
|
800528a: 6a3b ldr r3, [r7, #32]
|
|
800528c: f043 0308 orr.w r3, r3, #8
|
|
8005290: 623b str r3, [r7, #32]
|
|
|
|
/* Clear OVR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
|
|
8005292: 68fb ldr r3, [r7, #12]
|
|
8005294: 681b ldr r3, [r3, #0]
|
|
8005296: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
800529a: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
800529c: 2301 movs r3, #1
|
|
800529e: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Check if an Arbitration Loss error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
|
|
80052a2: 69bb ldr r3, [r7, #24]
|
|
80052a4: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80052a8: 2b00 cmp r3, #0
|
|
80052aa: d00b beq.n 80052c4 <I2C_IsErrorOccurred+0x16c>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_ARLO;
|
|
80052ac: 6a3b ldr r3, [r7, #32]
|
|
80052ae: f043 0302 orr.w r3, r3, #2
|
|
80052b2: 623b str r3, [r7, #32]
|
|
|
|
/* Clear ARLO flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
|
|
80052b4: 68fb ldr r3, [r7, #12]
|
|
80052b6: 681b ldr r3, [r3, #0]
|
|
80052b8: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80052bc: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
80052be: 2301 movs r3, #1
|
|
80052c0: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
if (status != HAL_OK)
|
|
80052c4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80052c8: 2b00 cmp r3, #0
|
|
80052ca: d01c beq.n 8005306 <I2C_IsErrorOccurred+0x1ae>
|
|
{
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
80052cc: 68f8 ldr r0, [r7, #12]
|
|
80052ce: f7ff fe3b bl 8004f48 <I2C_Flush_TXDR>
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
80052d2: 68fb ldr r3, [r7, #12]
|
|
80052d4: 681b ldr r3, [r3, #0]
|
|
80052d6: 6859 ldr r1, [r3, #4]
|
|
80052d8: 68fb ldr r3, [r7, #12]
|
|
80052da: 681a ldr r2, [r3, #0]
|
|
80052dc: 4b0d ldr r3, [pc, #52] @ (8005314 <I2C_IsErrorOccurred+0x1bc>)
|
|
80052de: 400b ands r3, r1
|
|
80052e0: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->ErrorCode |= error_code;
|
|
80052e2: 68fb ldr r3, [r7, #12]
|
|
80052e4: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
80052e6: 6a3b ldr r3, [r7, #32]
|
|
80052e8: 431a orrs r2, r3
|
|
80052ea: 68fb ldr r3, [r7, #12]
|
|
80052ec: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80052ee: 68fb ldr r3, [r7, #12]
|
|
80052f0: 2220 movs r2, #32
|
|
80052f2: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80052f6: 68fb ldr r3, [r7, #12]
|
|
80052f8: 2200 movs r2, #0
|
|
80052fa: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80052fe: 68fb ldr r3, [r7, #12]
|
|
8005300: 2200 movs r2, #0
|
|
8005302: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
}
|
|
|
|
return status;
|
|
8005306: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
800530a: 4618 mov r0, r3
|
|
800530c: 3728 adds r7, #40 @ 0x28
|
|
800530e: 46bd mov sp, r7
|
|
8005310: bd80 pop {r7, pc}
|
|
8005312: bf00 nop
|
|
8005314: fe00e800 .word 0xfe00e800
|
|
|
|
08005318 <I2C_TransferConfig>:
|
|
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
|
uint32_t Request)
|
|
{
|
|
8005318: b480 push {r7}
|
|
800531a: b087 sub sp, #28
|
|
800531c: af00 add r7, sp, #0
|
|
800531e: 60f8 str r0, [r7, #12]
|
|
8005320: 607b str r3, [r7, #4]
|
|
8005322: 460b mov r3, r1
|
|
8005324: 817b strh r3, [r7, #10]
|
|
8005326: 4613 mov r3, r2
|
|
8005328: 727b strb r3, [r7, #9]
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_TRANSFER_MODE(Mode));
|
|
assert_param(IS_TRANSFER_REQUEST(Request));
|
|
|
|
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
800532a: 897b ldrh r3, [r7, #10]
|
|
800532c: f3c3 0209 ubfx r2, r3, #0, #10
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
8005330: 7a7b ldrb r3, [r7, #9]
|
|
8005332: 041b lsls r3, r3, #16
|
|
8005334: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
8005338: 431a orrs r2, r3
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
800533a: 687b ldr r3, [r7, #4]
|
|
800533c: 431a orrs r2, r3
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
800533e: 6a3b ldr r3, [r7, #32]
|
|
8005340: 4313 orrs r3, r2
|
|
8005342: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8005346: 617b str r3, [r7, #20]
|
|
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
|
|
|
|
/* update CR2 register */
|
|
MODIFY_REG(hi2c->Instance->CR2, \
|
|
8005348: 68fb ldr r3, [r7, #12]
|
|
800534a: 681b ldr r3, [r3, #0]
|
|
800534c: 685a ldr r2, [r3, #4]
|
|
800534e: 6a3b ldr r3, [r7, #32]
|
|
8005350: 0d5b lsrs r3, r3, #21
|
|
8005352: f403 6180 and.w r1, r3, #1024 @ 0x400
|
|
8005356: 4b08 ldr r3, [pc, #32] @ (8005378 <I2C_TransferConfig+0x60>)
|
|
8005358: 430b orrs r3, r1
|
|
800535a: 43db mvns r3, r3
|
|
800535c: ea02 0103 and.w r1, r2, r3
|
|
8005360: 68fb ldr r3, [r7, #12]
|
|
8005362: 681b ldr r3, [r3, #0]
|
|
8005364: 697a ldr r2, [r7, #20]
|
|
8005366: 430a orrs r2, r1
|
|
8005368: 605a str r2, [r3, #4]
|
|
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
|
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
|
|
I2C_CR2_START | I2C_CR2_STOP)), tmp);
|
|
}
|
|
800536a: bf00 nop
|
|
800536c: 371c adds r7, #28
|
|
800536e: 46bd mov sp, r7
|
|
8005370: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005374: 4770 bx lr
|
|
8005376: bf00 nop
|
|
8005378: 03ff63ff .word 0x03ff63ff
|
|
|
|
0800537c <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter New state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
800537c: b480 push {r7}
|
|
800537e: b083 sub sp, #12
|
|
8005380: af00 add r7, sp, #0
|
|
8005382: 6078 str r0, [r7, #4]
|
|
8005384: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8005386: 687b ldr r3, [r7, #4]
|
|
8005388: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800538c: b2db uxtb r3, r3
|
|
800538e: 2b20 cmp r3, #32
|
|
8005390: d138 bne.n 8005404 <HAL_I2CEx_ConfigAnalogFilter+0x88>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8005392: 687b ldr r3, [r7, #4]
|
|
8005394: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8005398: 2b01 cmp r3, #1
|
|
800539a: d101 bne.n 80053a0 <HAL_I2CEx_ConfigAnalogFilter+0x24>
|
|
800539c: 2302 movs r3, #2
|
|
800539e: e032 b.n 8005406 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
80053a0: 687b ldr r3, [r7, #4]
|
|
80053a2: 2201 movs r2, #1
|
|
80053a4: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80053a8: 687b ldr r3, [r7, #4]
|
|
80053aa: 2224 movs r2, #36 @ 0x24
|
|
80053ac: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80053b0: 687b ldr r3, [r7, #4]
|
|
80053b2: 681b ldr r3, [r3, #0]
|
|
80053b4: 681a ldr r2, [r3, #0]
|
|
80053b6: 687b ldr r3, [r7, #4]
|
|
80053b8: 681b ldr r3, [r3, #0]
|
|
80053ba: f022 0201 bic.w r2, r2, #1
|
|
80053be: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
|
80053c0: 687b ldr r3, [r7, #4]
|
|
80053c2: 681b ldr r3, [r3, #0]
|
|
80053c4: 681a ldr r2, [r3, #0]
|
|
80053c6: 687b ldr r3, [r7, #4]
|
|
80053c8: 681b ldr r3, [r3, #0]
|
|
80053ca: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
80053ce: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog filter bit*/
|
|
hi2c->Instance->CR1 |= AnalogFilter;
|
|
80053d0: 687b ldr r3, [r7, #4]
|
|
80053d2: 681b ldr r3, [r3, #0]
|
|
80053d4: 6819 ldr r1, [r3, #0]
|
|
80053d6: 687b ldr r3, [r7, #4]
|
|
80053d8: 681b ldr r3, [r3, #0]
|
|
80053da: 683a ldr r2, [r7, #0]
|
|
80053dc: 430a orrs r2, r1
|
|
80053de: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
80053e0: 687b ldr r3, [r7, #4]
|
|
80053e2: 681b ldr r3, [r3, #0]
|
|
80053e4: 681a ldr r2, [r3, #0]
|
|
80053e6: 687b ldr r3, [r7, #4]
|
|
80053e8: 681b ldr r3, [r3, #0]
|
|
80053ea: f042 0201 orr.w r2, r2, #1
|
|
80053ee: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80053f0: 687b ldr r3, [r7, #4]
|
|
80053f2: 2220 movs r2, #32
|
|
80053f4: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80053f8: 687b ldr r3, [r7, #4]
|
|
80053fa: 2200 movs r2, #0
|
|
80053fc: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8005400: 2300 movs r3, #0
|
|
8005402: e000 b.n 8005406 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005404: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005406: 4618 mov r0, r3
|
|
8005408: 370c adds r7, #12
|
|
800540a: 46bd mov sp, r7
|
|
800540c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005410: 4770 bx lr
|
|
|
|
08005412 <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
8005412: b480 push {r7}
|
|
8005414: b085 sub sp, #20
|
|
8005416: af00 add r7, sp, #0
|
|
8005418: 6078 str r0, [r7, #4]
|
|
800541a: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
800541c: 687b ldr r3, [r7, #4]
|
|
800541e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8005422: b2db uxtb r3, r3
|
|
8005424: 2b20 cmp r3, #32
|
|
8005426: d139 bne.n 800549c <HAL_I2CEx_ConfigDigitalFilter+0x8a>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8005428: 687b ldr r3, [r7, #4]
|
|
800542a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
800542e: 2b01 cmp r3, #1
|
|
8005430: d101 bne.n 8005436 <HAL_I2CEx_ConfigDigitalFilter+0x24>
|
|
8005432: 2302 movs r3, #2
|
|
8005434: e033 b.n 800549e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
8005436: 687b ldr r3, [r7, #4]
|
|
8005438: 2201 movs r2, #1
|
|
800543a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
800543e: 687b ldr r3, [r7, #4]
|
|
8005440: 2224 movs r2, #36 @ 0x24
|
|
8005442: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8005446: 687b ldr r3, [r7, #4]
|
|
8005448: 681b ldr r3, [r3, #0]
|
|
800544a: 681a ldr r2, [r3, #0]
|
|
800544c: 687b ldr r3, [r7, #4]
|
|
800544e: 681b ldr r3, [r3, #0]
|
|
8005450: f022 0201 bic.w r2, r2, #1
|
|
8005454: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->CR1;
|
|
8005456: 687b ldr r3, [r7, #4]
|
|
8005458: 681b ldr r3, [r3, #0]
|
|
800545a: 681b ldr r3, [r3, #0]
|
|
800545c: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2Cx DNF bits [11:8] */
|
|
tmpreg &= ~(I2C_CR1_DNF);
|
|
800545e: 68fb ldr r3, [r7, #12]
|
|
8005460: f423 6370 bic.w r3, r3, #3840 @ 0xf00
|
|
8005464: 60fb str r3, [r7, #12]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter << 8U;
|
|
8005466: 683b ldr r3, [r7, #0]
|
|
8005468: 021b lsls r3, r3, #8
|
|
800546a: 68fa ldr r2, [r7, #12]
|
|
800546c: 4313 orrs r3, r2
|
|
800546e: 60fb str r3, [r7, #12]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->CR1 = tmpreg;
|
|
8005470: 687b ldr r3, [r7, #4]
|
|
8005472: 681b ldr r3, [r3, #0]
|
|
8005474: 68fa ldr r2, [r7, #12]
|
|
8005476: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8005478: 687b ldr r3, [r7, #4]
|
|
800547a: 681b ldr r3, [r3, #0]
|
|
800547c: 681a ldr r2, [r3, #0]
|
|
800547e: 687b ldr r3, [r7, #4]
|
|
8005480: 681b ldr r3, [r3, #0]
|
|
8005482: f042 0201 orr.w r2, r2, #1
|
|
8005486: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8005488: 687b ldr r3, [r7, #4]
|
|
800548a: 2220 movs r2, #32
|
|
800548c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8005490: 687b ldr r3, [r7, #4]
|
|
8005492: 2200 movs r2, #0
|
|
8005494: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8005498: 2300 movs r3, #0
|
|
800549a: e000 b.n 800549e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800549c: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800549e: 4618 mov r0, r3
|
|
80054a0: 3714 adds r7, #20
|
|
80054a2: 46bd mov sp, r7
|
|
80054a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80054a8: 4770 bx lr
|
|
|
|
080054aa <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
80054aa: b580 push {r7, lr}
|
|
80054ac: b086 sub sp, #24
|
|
80054ae: af02 add r7, sp, #8
|
|
80054b0: 6078 str r0, [r7, #4]
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
80054b2: 687b ldr r3, [r7, #4]
|
|
80054b4: 2b00 cmp r3, #0
|
|
80054b6: d101 bne.n 80054bc <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80054b8: 2301 movs r3, #1
|
|
80054ba: e101 b.n 80056c0 <HAL_PCD_Init+0x216>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
80054bc: 687b ldr r3, [r7, #4]
|
|
80054be: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
|
|
80054c2: b2db uxtb r3, r3
|
|
80054c4: 2b00 cmp r3, #0
|
|
80054c6: d106 bne.n 80054d6 <HAL_PCD_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
80054c8: 687b ldr r3, [r7, #4]
|
|
80054ca: 2200 movs r2, #0
|
|
80054cc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
80054d0: 6878 ldr r0, [r7, #4]
|
|
80054d2: f7fe f985 bl 80037e0 <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
80054d6: 687b ldr r3, [r7, #4]
|
|
80054d8: 2203 movs r2, #3
|
|
80054da: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
/* Disable DMA mode for FS instance */
|
|
hpcd->Init.dma_enable = 0U;
|
|
80054de: 687b ldr r3, [r7, #4]
|
|
80054e0: 2200 movs r2, #0
|
|
80054e2: 719a strb r2, [r3, #6]
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
80054e4: 687b ldr r3, [r7, #4]
|
|
80054e6: 681b ldr r3, [r3, #0]
|
|
80054e8: 4618 mov r0, r3
|
|
80054ea: f004 fdde bl 800a0aa <USB_DisableGlobalInt>
|
|
|
|
/*Init the Core (common init.) */
|
|
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
80054ee: 687b ldr r3, [r7, #4]
|
|
80054f0: 6818 ldr r0, [r3, #0]
|
|
80054f2: 687b ldr r3, [r7, #4]
|
|
80054f4: 7c1a ldrb r2, [r3, #16]
|
|
80054f6: f88d 2000 strb.w r2, [sp]
|
|
80054fa: 3304 adds r3, #4
|
|
80054fc: cb0e ldmia r3, {r1, r2, r3}
|
|
80054fe: f004 fda7 bl 800a050 <USB_CoreInit>
|
|
8005502: 4603 mov r3, r0
|
|
8005504: 2b00 cmp r3, #0
|
|
8005506: d005 beq.n 8005514 <HAL_PCD_Init+0x6a>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8005508: 687b ldr r3, [r7, #4]
|
|
800550a: 2202 movs r2, #2
|
|
800550c: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8005510: 2301 movs r3, #1
|
|
8005512: e0d5 b.n 80056c0 <HAL_PCD_Init+0x216>
|
|
}
|
|
|
|
/* Force Device Mode */
|
|
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
|
|
8005514: 687b ldr r3, [r7, #4]
|
|
8005516: 681b ldr r3, [r3, #0]
|
|
8005518: 2100 movs r1, #0
|
|
800551a: 4618 mov r0, r3
|
|
800551c: f004 fdd6 bl 800a0cc <USB_SetCurrentMode>
|
|
8005520: 4603 mov r3, r0
|
|
8005522: 2b00 cmp r3, #0
|
|
8005524: d005 beq.n 8005532 <HAL_PCD_Init+0x88>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8005526: 687b ldr r3, [r7, #4]
|
|
8005528: 2202 movs r2, #2
|
|
800552a: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
800552e: 2301 movs r3, #1
|
|
8005530: e0c6 b.n 80056c0 <HAL_PCD_Init+0x216>
|
|
}
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8005532: 2300 movs r3, #0
|
|
8005534: 73fb strb r3, [r7, #15]
|
|
8005536: e04a b.n 80055ce <HAL_PCD_Init+0x124>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
8005538: 7bfa ldrb r2, [r7, #15]
|
|
800553a: 6879 ldr r1, [r7, #4]
|
|
800553c: 4613 mov r3, r2
|
|
800553e: 00db lsls r3, r3, #3
|
|
8005540: 4413 add r3, r2
|
|
8005542: 009b lsls r3, r3, #2
|
|
8005544: 440b add r3, r1
|
|
8005546: 3315 adds r3, #21
|
|
8005548: 2201 movs r2, #1
|
|
800554a: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
800554c: 7bfa ldrb r2, [r7, #15]
|
|
800554e: 6879 ldr r1, [r7, #4]
|
|
8005550: 4613 mov r3, r2
|
|
8005552: 00db lsls r3, r3, #3
|
|
8005554: 4413 add r3, r2
|
|
8005556: 009b lsls r3, r3, #2
|
|
8005558: 440b add r3, r1
|
|
800555a: 3314 adds r3, #20
|
|
800555c: 7bfa ldrb r2, [r7, #15]
|
|
800555e: 701a strb r2, [r3, #0]
|
|
#if defined (USB_OTG_FS)
|
|
hpcd->IN_ep[i].tx_fifo_num = i;
|
|
8005560: 7bfa ldrb r2, [r7, #15]
|
|
8005562: 7bfb ldrb r3, [r7, #15]
|
|
8005564: b298 uxth r0, r3
|
|
8005566: 6879 ldr r1, [r7, #4]
|
|
8005568: 4613 mov r3, r2
|
|
800556a: 00db lsls r3, r3, #3
|
|
800556c: 4413 add r3, r2
|
|
800556e: 009b lsls r3, r3, #2
|
|
8005570: 440b add r3, r1
|
|
8005572: 332e adds r3, #46 @ 0x2e
|
|
8005574: 4602 mov r2, r0
|
|
8005576: 801a strh r2, [r3, #0]
|
|
#endif /* defined (USB_OTG_FS) */
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8005578: 7bfa ldrb r2, [r7, #15]
|
|
800557a: 6879 ldr r1, [r7, #4]
|
|
800557c: 4613 mov r3, r2
|
|
800557e: 00db lsls r3, r3, #3
|
|
8005580: 4413 add r3, r2
|
|
8005582: 009b lsls r3, r3, #2
|
|
8005584: 440b add r3, r1
|
|
8005586: 3318 adds r3, #24
|
|
8005588: 2200 movs r2, #0
|
|
800558a: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
800558c: 7bfa ldrb r2, [r7, #15]
|
|
800558e: 6879 ldr r1, [r7, #4]
|
|
8005590: 4613 mov r3, r2
|
|
8005592: 00db lsls r3, r3, #3
|
|
8005594: 4413 add r3, r2
|
|
8005596: 009b lsls r3, r3, #2
|
|
8005598: 440b add r3, r1
|
|
800559a: 331c adds r3, #28
|
|
800559c: 2200 movs r2, #0
|
|
800559e: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
80055a0: 7bfa ldrb r2, [r7, #15]
|
|
80055a2: 6879 ldr r1, [r7, #4]
|
|
80055a4: 4613 mov r3, r2
|
|
80055a6: 00db lsls r3, r3, #3
|
|
80055a8: 4413 add r3, r2
|
|
80055aa: 009b lsls r3, r3, #2
|
|
80055ac: 440b add r3, r1
|
|
80055ae: 3320 adds r3, #32
|
|
80055b0: 2200 movs r2, #0
|
|
80055b2: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
80055b4: 7bfa ldrb r2, [r7, #15]
|
|
80055b6: 6879 ldr r1, [r7, #4]
|
|
80055b8: 4613 mov r3, r2
|
|
80055ba: 00db lsls r3, r3, #3
|
|
80055bc: 4413 add r3, r2
|
|
80055be: 009b lsls r3, r3, #2
|
|
80055c0: 440b add r3, r1
|
|
80055c2: 3324 adds r3, #36 @ 0x24
|
|
80055c4: 2200 movs r2, #0
|
|
80055c6: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80055c8: 7bfb ldrb r3, [r7, #15]
|
|
80055ca: 3301 adds r3, #1
|
|
80055cc: 73fb strb r3, [r7, #15]
|
|
80055ce: 687b ldr r3, [r7, #4]
|
|
80055d0: 791b ldrb r3, [r3, #4]
|
|
80055d2: 7bfa ldrb r2, [r7, #15]
|
|
80055d4: 429a cmp r2, r3
|
|
80055d6: d3af bcc.n 8005538 <HAL_PCD_Init+0x8e>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80055d8: 2300 movs r3, #0
|
|
80055da: 73fb strb r3, [r7, #15]
|
|
80055dc: e044 b.n 8005668 <HAL_PCD_Init+0x1be>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
80055de: 7bfa ldrb r2, [r7, #15]
|
|
80055e0: 6879 ldr r1, [r7, #4]
|
|
80055e2: 4613 mov r3, r2
|
|
80055e4: 00db lsls r3, r3, #3
|
|
80055e6: 4413 add r3, r2
|
|
80055e8: 009b lsls r3, r3, #2
|
|
80055ea: 440b add r3, r1
|
|
80055ec: f203 2355 addw r3, r3, #597 @ 0x255
|
|
80055f0: 2200 movs r2, #0
|
|
80055f2: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
80055f4: 7bfa ldrb r2, [r7, #15]
|
|
80055f6: 6879 ldr r1, [r7, #4]
|
|
80055f8: 4613 mov r3, r2
|
|
80055fa: 00db lsls r3, r3, #3
|
|
80055fc: 4413 add r3, r2
|
|
80055fe: 009b lsls r3, r3, #2
|
|
8005600: 440b add r3, r1
|
|
8005602: f503 7315 add.w r3, r3, #596 @ 0x254
|
|
8005606: 7bfa ldrb r2, [r7, #15]
|
|
8005608: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
800560a: 7bfa ldrb r2, [r7, #15]
|
|
800560c: 6879 ldr r1, [r7, #4]
|
|
800560e: 4613 mov r3, r2
|
|
8005610: 00db lsls r3, r3, #3
|
|
8005612: 4413 add r3, r2
|
|
8005614: 009b lsls r3, r3, #2
|
|
8005616: 440b add r3, r1
|
|
8005618: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
800561c: 2200 movs r2, #0
|
|
800561e: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
8005620: 7bfa ldrb r2, [r7, #15]
|
|
8005622: 6879 ldr r1, [r7, #4]
|
|
8005624: 4613 mov r3, r2
|
|
8005626: 00db lsls r3, r3, #3
|
|
8005628: 4413 add r3, r2
|
|
800562a: 009b lsls r3, r3, #2
|
|
800562c: 440b add r3, r1
|
|
800562e: f503 7317 add.w r3, r3, #604 @ 0x25c
|
|
8005632: 2200 movs r2, #0
|
|
8005634: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
8005636: 7bfa ldrb r2, [r7, #15]
|
|
8005638: 6879 ldr r1, [r7, #4]
|
|
800563a: 4613 mov r3, r2
|
|
800563c: 00db lsls r3, r3, #3
|
|
800563e: 4413 add r3, r2
|
|
8005640: 009b lsls r3, r3, #2
|
|
8005642: 440b add r3, r1
|
|
8005644: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
8005648: 2200 movs r2, #0
|
|
800564a: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
800564c: 7bfa ldrb r2, [r7, #15]
|
|
800564e: 6879 ldr r1, [r7, #4]
|
|
8005650: 4613 mov r3, r2
|
|
8005652: 00db lsls r3, r3, #3
|
|
8005654: 4413 add r3, r2
|
|
8005656: 009b lsls r3, r3, #2
|
|
8005658: 440b add r3, r1
|
|
800565a: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
800565e: 2200 movs r2, #0
|
|
8005660: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8005662: 7bfb ldrb r3, [r7, #15]
|
|
8005664: 3301 adds r3, #1
|
|
8005666: 73fb strb r3, [r7, #15]
|
|
8005668: 687b ldr r3, [r7, #4]
|
|
800566a: 791b ldrb r3, [r3, #4]
|
|
800566c: 7bfa ldrb r2, [r7, #15]
|
|
800566e: 429a cmp r2, r3
|
|
8005670: d3b5 bcc.n 80055de <HAL_PCD_Init+0x134>
|
|
}
|
|
|
|
/* Init Device */
|
|
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8005672: 687b ldr r3, [r7, #4]
|
|
8005674: 6818 ldr r0, [r3, #0]
|
|
8005676: 687b ldr r3, [r7, #4]
|
|
8005678: 7c1a ldrb r2, [r3, #16]
|
|
800567a: f88d 2000 strb.w r2, [sp]
|
|
800567e: 3304 adds r3, #4
|
|
8005680: cb0e ldmia r3, {r1, r2, r3}
|
|
8005682: f004 fd6f bl 800a164 <USB_DevInit>
|
|
8005686: 4603 mov r3, r0
|
|
8005688: 2b00 cmp r3, #0
|
|
800568a: d005 beq.n 8005698 <HAL_PCD_Init+0x1ee>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
800568c: 687b ldr r3, [r7, #4]
|
|
800568e: 2202 movs r2, #2
|
|
8005690: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8005694: 2301 movs r3, #1
|
|
8005696: e013 b.n 80056c0 <HAL_PCD_Init+0x216>
|
|
}
|
|
|
|
hpcd->USB_Address = 0U;
|
|
8005698: 687b ldr r3, [r7, #4]
|
|
800569a: 2200 movs r2, #0
|
|
800569c: 745a strb r2, [r3, #17]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
800569e: 687b ldr r3, [r7, #4]
|
|
80056a0: 2201 movs r2, #1
|
|
80056a2: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
/* Activate LPM */
|
|
if (hpcd->Init.lpm_enable == 1U)
|
|
80056a6: 687b ldr r3, [r7, #4]
|
|
80056a8: 7b1b ldrb r3, [r3, #12]
|
|
80056aa: 2b01 cmp r3, #1
|
|
80056ac: d102 bne.n 80056b4 <HAL_PCD_Init+0x20a>
|
|
{
|
|
(void)HAL_PCDEx_ActivateLPM(hpcd);
|
|
80056ae: 6878 ldr r0, [r7, #4]
|
|
80056b0: f000 f80a bl 80056c8 <HAL_PCDEx_ActivateLPM>
|
|
}
|
|
|
|
(void)USB_DevDisconnect(hpcd->Instance);
|
|
80056b4: 687b ldr r3, [r7, #4]
|
|
80056b6: 681b ldr r3, [r3, #0]
|
|
80056b8: 4618 mov r0, r3
|
|
80056ba: f004 ff14 bl 800a4e6 <USB_DevDisconnect>
|
|
|
|
return HAL_OK;
|
|
80056be: 2300 movs r3, #0
|
|
}
|
|
80056c0: 4618 mov r0, r3
|
|
80056c2: 3710 adds r7, #16
|
|
80056c4: 46bd mov sp, r7
|
|
80056c6: bd80 pop {r7, pc}
|
|
|
|
080056c8 <HAL_PCDEx_ActivateLPM>:
|
|
* @brief Activate LPM feature.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
80056c8: b480 push {r7}
|
|
80056ca: b085 sub sp, #20
|
|
80056cc: af00 add r7, sp, #0
|
|
80056ce: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
80056d0: 687b ldr r3, [r7, #4]
|
|
80056d2: 681b ldr r3, [r3, #0]
|
|
80056d4: 60fb str r3, [r7, #12]
|
|
|
|
hpcd->lpm_active = 1U;
|
|
80056d6: 687b ldr r3, [r7, #4]
|
|
80056d8: 2201 movs r2, #1
|
|
80056da: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
|
|
hpcd->LPM_State = LPM_L0;
|
|
80056de: 687b ldr r3, [r7, #4]
|
|
80056e0: 2200 movs r2, #0
|
|
80056e2: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
|
80056e6: 68fb ldr r3, [r7, #12]
|
|
80056e8: 699b ldr r3, [r3, #24]
|
|
80056ea: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
|
|
80056ee: 68fb ldr r3, [r7, #12]
|
|
80056f0: 619a str r2, [r3, #24]
|
|
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
|
80056f2: 68fb ldr r3, [r7, #12]
|
|
80056f4: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80056f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80056fa: f043 0303 orr.w r3, r3, #3
|
|
80056fe: 68fa ldr r2, [r7, #12]
|
|
8005700: 6553 str r3, [r2, #84] @ 0x54
|
|
|
|
return HAL_OK;
|
|
8005702: 2300 movs r3, #0
|
|
}
|
|
8005704: 4618 mov r0, r3
|
|
8005706: 3714 adds r7, #20
|
|
8005708: 46bd mov sp, r7
|
|
800570a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800570e: 4770 bx lr
|
|
|
|
08005710 <HAL_PWR_EnableBkUpAccess>:
|
|
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
|
|
* back-up domain.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_EnableBkUpAccess(void)
|
|
{
|
|
8005710: b480 push {r7}
|
|
8005712: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8005714: 4b05 ldr r3, [pc, #20] @ (800572c <HAL_PWR_EnableBkUpAccess+0x1c>)
|
|
8005716: 681b ldr r3, [r3, #0]
|
|
8005718: 4a04 ldr r2, [pc, #16] @ (800572c <HAL_PWR_EnableBkUpAccess+0x1c>)
|
|
800571a: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
800571e: 6013 str r3, [r2, #0]
|
|
}
|
|
8005720: bf00 nop
|
|
8005722: 46bd mov sp, r7
|
|
8005724: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005728: 4770 bx lr
|
|
800572a: bf00 nop
|
|
800572c: 40007000 .word 0x40007000
|
|
|
|
08005730 <HAL_PWREx_GetVoltageRange>:
|
|
* @brief Return Voltage Scaling Range.
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
|
|
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
|
|
*/
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
|
{
|
|
8005730: b480 push {r7}
|
|
8005732: af00 add r7, sp, #0
|
|
else
|
|
{
|
|
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
|
|
}
|
|
#else
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
|
8005734: 4b04 ldr r3, [pc, #16] @ (8005748 <HAL_PWREx_GetVoltageRange+0x18>)
|
|
8005736: 681b ldr r3, [r3, #0]
|
|
8005738: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
#endif
|
|
}
|
|
800573c: 4618 mov r0, r3
|
|
800573e: 46bd mov sp, r7
|
|
8005740: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005744: 4770 bx lr
|
|
8005746: bf00 nop
|
|
8005748: 40007000 .word 0x40007000
|
|
|
|
0800574c <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
800574c: b480 push {r7}
|
|
800574e: b085 sub sp, #20
|
|
8005750: af00 add r7, sp, #0
|
|
8005752: 6078 str r0, [r7, #4]
|
|
}
|
|
|
|
#else
|
|
|
|
/* If Set Range 1 */
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8005754: 687b ldr r3, [r7, #4]
|
|
8005756: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
800575a: d130 bne.n 80057be <HAL_PWREx_ControlVoltageScaling+0x72>
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
800575c: 4b23 ldr r3, [pc, #140] @ (80057ec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
800575e: 681b ldr r3, [r3, #0]
|
|
8005760: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8005764: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8005768: d038 beq.n 80057dc <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
800576a: 4b20 ldr r3, [pc, #128] @ (80057ec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
800576c: 681b ldr r3, [r3, #0]
|
|
800576e: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8005772: 4a1e ldr r2, [pc, #120] @ (80057ec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8005774: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8005778: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
800577a: 4b1d ldr r3, [pc, #116] @ (80057f0 <HAL_PWREx_ControlVoltageScaling+0xa4>)
|
|
800577c: 681b ldr r3, [r3, #0]
|
|
800577e: 2232 movs r2, #50 @ 0x32
|
|
8005780: fb02 f303 mul.w r3, r2, r3
|
|
8005784: 4a1b ldr r2, [pc, #108] @ (80057f4 <HAL_PWREx_ControlVoltageScaling+0xa8>)
|
|
8005786: fba2 2303 umull r2, r3, r2, r3
|
|
800578a: 0c9b lsrs r3, r3, #18
|
|
800578c: 3301 adds r3, #1
|
|
800578e: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8005790: e002 b.n 8005798 <HAL_PWREx_ControlVoltageScaling+0x4c>
|
|
{
|
|
wait_loop_index--;
|
|
8005792: 68fb ldr r3, [r7, #12]
|
|
8005794: 3b01 subs r3, #1
|
|
8005796: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8005798: 4b14 ldr r3, [pc, #80] @ (80057ec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
800579a: 695b ldr r3, [r3, #20]
|
|
800579c: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80057a0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80057a4: d102 bne.n 80057ac <HAL_PWREx_ControlVoltageScaling+0x60>
|
|
80057a6: 68fb ldr r3, [r7, #12]
|
|
80057a8: 2b00 cmp r3, #0
|
|
80057aa: d1f2 bne.n 8005792 <HAL_PWREx_ControlVoltageScaling+0x46>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
80057ac: 4b0f ldr r3, [pc, #60] @ (80057ec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80057ae: 695b ldr r3, [r3, #20]
|
|
80057b0: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80057b4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80057b8: d110 bne.n 80057dc <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80057ba: 2303 movs r3, #3
|
|
80057bc: e00f b.n 80057de <HAL_PWREx_ControlVoltageScaling+0x92>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
80057be: 4b0b ldr r3, [pc, #44] @ (80057ec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80057c0: 681b ldr r3, [r3, #0]
|
|
80057c2: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
80057c6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80057ca: d007 beq.n 80057dc <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
/* Set Range 2 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
|
80057cc: 4b07 ldr r3, [pc, #28] @ (80057ec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80057ce: 681b ldr r3, [r3, #0]
|
|
80057d0: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
80057d4: 4a05 ldr r2, [pc, #20] @ (80057ec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80057d6: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
80057da: 6013 str r3, [r2, #0]
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return HAL_OK;
|
|
80057dc: 2300 movs r3, #0
|
|
}
|
|
80057de: 4618 mov r0, r3
|
|
80057e0: 3714 adds r7, #20
|
|
80057e2: 46bd mov sp, r7
|
|
80057e4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80057e8: 4770 bx lr
|
|
80057ea: bf00 nop
|
|
80057ec: 40007000 .word 0x40007000
|
|
80057f0: 200000c4 .word 0x200000c4
|
|
80057f4: 431bde83 .word 0x431bde83
|
|
|
|
080057f8 <HAL_PWREx_EnableVddUSB>:
|
|
* @brief Enable VDDUSB supply.
|
|
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_EnableVddUSB(void)
|
|
{
|
|
80057f8: b480 push {r7}
|
|
80057fa: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR2, PWR_CR2_USV);
|
|
80057fc: 4b05 ldr r3, [pc, #20] @ (8005814 <HAL_PWREx_EnableVddUSB+0x1c>)
|
|
80057fe: 685b ldr r3, [r3, #4]
|
|
8005800: 4a04 ldr r2, [pc, #16] @ (8005814 <HAL_PWREx_EnableVddUSB+0x1c>)
|
|
8005802: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8005806: 6053 str r3, [r2, #4]
|
|
}
|
|
8005808: bf00 nop
|
|
800580a: 46bd mov sp, r7
|
|
800580c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005810: 4770 bx lr
|
|
8005812: bf00 nop
|
|
8005814: 40007000 .word 0x40007000
|
|
|
|
08005818 <HAL_QSPI_Init>:
|
|
* in the QSPI_InitTypeDef and initialize the associated handle.
|
|
* @param hqspi QSPI handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
|
|
{
|
|
8005818: b580 push {r7, lr}
|
|
800581a: b086 sub sp, #24
|
|
800581c: af02 add r7, sp, #8
|
|
800581e: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status;
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8005820: f7fe fa6e bl 8003d00 <HAL_GetTick>
|
|
8005824: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the QSPI handle allocation */
|
|
if(hqspi == NULL)
|
|
8005826: 687b ldr r3, [r7, #4]
|
|
8005828: 2b00 cmp r3, #0
|
|
800582a: d101 bne.n 8005830 <HAL_QSPI_Init+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
800582c: 2301 movs r3, #1
|
|
800582e: e063 b.n 80058f8 <HAL_QSPI_Init+0xe0>
|
|
{
|
|
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
|
|
}
|
|
#endif
|
|
|
|
if(hqspi->State == HAL_QSPI_STATE_RESET)
|
|
8005830: 687b ldr r3, [r7, #4]
|
|
8005832: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
|
|
8005836: b2db uxtb r3, r3
|
|
8005838: 2b00 cmp r3, #0
|
|
800583a: d10b bne.n 8005854 <HAL_QSPI_Init+0x3c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hqspi->Lock = HAL_UNLOCKED;
|
|
800583c: 687b ldr r3, [r7, #4]
|
|
800583e: 2200 movs r2, #0
|
|
8005840: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
/* Init the low level hardware */
|
|
hqspi->MspInitCallback(hqspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_QSPI_MspInit(hqspi);
|
|
8005844: 6878 ldr r0, [r7, #4]
|
|
8005846: f7fd fe79 bl 800353c <HAL_QSPI_MspInit>
|
|
#endif
|
|
|
|
/* Configure the default timeout for the QSPI memory access */
|
|
HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
|
|
800584a: f241 3188 movw r1, #5000 @ 0x1388
|
|
800584e: 6878 ldr r0, [r7, #4]
|
|
8005850: f000 f858 bl 8005904 <HAL_QSPI_SetTimeout>
|
|
}
|
|
|
|
/* Configure QSPI FIFO Threshold */
|
|
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
|
|
8005854: 687b ldr r3, [r7, #4]
|
|
8005856: 681b ldr r3, [r3, #0]
|
|
8005858: 681b ldr r3, [r3, #0]
|
|
800585a: f423 6170 bic.w r1, r3, #3840 @ 0xf00
|
|
800585e: 687b ldr r3, [r7, #4]
|
|
8005860: 689b ldr r3, [r3, #8]
|
|
8005862: 3b01 subs r3, #1
|
|
8005864: 021a lsls r2, r3, #8
|
|
8005866: 687b ldr r3, [r7, #4]
|
|
8005868: 681b ldr r3, [r3, #0]
|
|
800586a: 430a orrs r2, r1
|
|
800586c: 601a str r2, [r3, #0]
|
|
((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
|
|
|
|
/* Wait till BUSY flag reset */
|
|
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
|
|
800586e: 687b ldr r3, [r7, #4]
|
|
8005870: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005872: 9300 str r3, [sp, #0]
|
|
8005874: 68fb ldr r3, [r7, #12]
|
|
8005876: 2200 movs r2, #0
|
|
8005878: 2120 movs r1, #32
|
|
800587a: 6878 ldr r0, [r7, #4]
|
|
800587c: f000 f850 bl 8005920 <QSPI_WaitFlagStateUntilTimeout>
|
|
8005880: 4603 mov r3, r0
|
|
8005882: 72fb strb r3, [r7, #11]
|
|
|
|
if(status == HAL_OK)
|
|
8005884: 7afb ldrb r3, [r7, #11]
|
|
8005886: 2b00 cmp r3, #0
|
|
8005888: d131 bne.n 80058ee <HAL_QSPI_Init+0xd6>
|
|
#if defined(QUADSPI_CR_DFM)
|
|
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
|
|
((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
|
|
hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
|
|
#else
|
|
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
|
|
800588a: 687b ldr r3, [r7, #4]
|
|
800588c: 681b ldr r3, [r3, #0]
|
|
800588e: 681b ldr r3, [r3, #0]
|
|
8005890: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000
|
|
8005894: f023 0310 bic.w r3, r3, #16
|
|
8005898: 687a ldr r2, [r7, #4]
|
|
800589a: 6852 ldr r2, [r2, #4]
|
|
800589c: 0611 lsls r1, r2, #24
|
|
800589e: 687a ldr r2, [r7, #4]
|
|
80058a0: 68d2 ldr r2, [r2, #12]
|
|
80058a2: 4311 orrs r1, r2
|
|
80058a4: 687a ldr r2, [r7, #4]
|
|
80058a6: 6812 ldr r2, [r2, #0]
|
|
80058a8: 430b orrs r3, r1
|
|
80058aa: 6013 str r3, [r2, #0]
|
|
((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
|
|
hqspi->Init.SampleShifting));
|
|
#endif
|
|
|
|
/* Configure QSPI Flash Size, CS High Time and Clock Mode */
|
|
MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
|
|
80058ac: 687b ldr r3, [r7, #4]
|
|
80058ae: 681b ldr r3, [r3, #0]
|
|
80058b0: 685a ldr r2, [r3, #4]
|
|
80058b2: 4b13 ldr r3, [pc, #76] @ (8005900 <HAL_QSPI_Init+0xe8>)
|
|
80058b4: 4013 ands r3, r2
|
|
80058b6: 687a ldr r2, [r7, #4]
|
|
80058b8: 6912 ldr r2, [r2, #16]
|
|
80058ba: 0411 lsls r1, r2, #16
|
|
80058bc: 687a ldr r2, [r7, #4]
|
|
80058be: 6952 ldr r2, [r2, #20]
|
|
80058c0: 4311 orrs r1, r2
|
|
80058c2: 687a ldr r2, [r7, #4]
|
|
80058c4: 6992 ldr r2, [r2, #24]
|
|
80058c6: 4311 orrs r1, r2
|
|
80058c8: 687a ldr r2, [r7, #4]
|
|
80058ca: 6812 ldr r2, [r2, #0]
|
|
80058cc: 430b orrs r3, r1
|
|
80058ce: 6053 str r3, [r2, #4]
|
|
((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
|
|
hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
|
|
|
|
/* Enable the QSPI peripheral */
|
|
__HAL_QSPI_ENABLE(hqspi);
|
|
80058d0: 687b ldr r3, [r7, #4]
|
|
80058d2: 681b ldr r3, [r3, #0]
|
|
80058d4: 681a ldr r2, [r3, #0]
|
|
80058d6: 687b ldr r3, [r7, #4]
|
|
80058d8: 681b ldr r3, [r3, #0]
|
|
80058da: f042 0201 orr.w r2, r2, #1
|
|
80058de: 601a str r2, [r3, #0]
|
|
|
|
/* Set QSPI error code to none */
|
|
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
|
|
80058e0: 687b ldr r3, [r7, #4]
|
|
80058e2: 2200 movs r2, #0
|
|
80058e4: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Initialize the QSPI state */
|
|
hqspi->State = HAL_QSPI_STATE_READY;
|
|
80058e6: 687b ldr r3, [r7, #4]
|
|
80058e8: 2201 movs r2, #1
|
|
80058ea: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hqspi);
|
|
80058ee: 687b ldr r3, [r7, #4]
|
|
80058f0: 2200 movs r2, #0
|
|
80058f2: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
/* Return function status */
|
|
return status;
|
|
80058f6: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
80058f8: 4618 mov r0, r3
|
|
80058fa: 3710 adds r7, #16
|
|
80058fc: 46bd mov sp, r7
|
|
80058fe: bd80 pop {r7, pc}
|
|
8005900: ffe0f8fe .word 0xffe0f8fe
|
|
|
|
08005904 <HAL_QSPI_SetTimeout>:
|
|
* @param hqspi QSPI handle.
|
|
* @param Timeout Timeout for the QSPI memory access.
|
|
* @retval None
|
|
*/
|
|
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
|
|
{
|
|
8005904: b480 push {r7}
|
|
8005906: b083 sub sp, #12
|
|
8005908: af00 add r7, sp, #0
|
|
800590a: 6078 str r0, [r7, #4]
|
|
800590c: 6039 str r1, [r7, #0]
|
|
hqspi->Timeout = Timeout;
|
|
800590e: 687b ldr r3, [r7, #4]
|
|
8005910: 683a ldr r2, [r7, #0]
|
|
8005912: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
8005914: bf00 nop
|
|
8005916: 370c adds r7, #12
|
|
8005918: 46bd mov sp, r7
|
|
800591a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800591e: 4770 bx lr
|
|
|
|
08005920 <QSPI_WaitFlagStateUntilTimeout>:
|
|
* @param Timeout Duration of the timeout
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
|
|
FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8005920: b580 push {r7, lr}
|
|
8005922: b084 sub sp, #16
|
|
8005924: af00 add r7, sp, #0
|
|
8005926: 60f8 str r0, [r7, #12]
|
|
8005928: 60b9 str r1, [r7, #8]
|
|
800592a: 603b str r3, [r7, #0]
|
|
800592c: 4613 mov r3, r2
|
|
800592e: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is in expected state */
|
|
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
|
|
8005930: e01a b.n 8005968 <QSPI_WaitFlagStateUntilTimeout+0x48>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8005932: 69bb ldr r3, [r7, #24]
|
|
8005934: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8005938: d016 beq.n 8005968 <QSPI_WaitFlagStateUntilTimeout+0x48>
|
|
{
|
|
if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
800593a: f7fe f9e1 bl 8003d00 <HAL_GetTick>
|
|
800593e: 4602 mov r2, r0
|
|
8005940: 683b ldr r3, [r7, #0]
|
|
8005942: 1ad3 subs r3, r2, r3
|
|
8005944: 69ba ldr r2, [r7, #24]
|
|
8005946: 429a cmp r2, r3
|
|
8005948: d302 bcc.n 8005950 <QSPI_WaitFlagStateUntilTimeout+0x30>
|
|
800594a: 69bb ldr r3, [r7, #24]
|
|
800594c: 2b00 cmp r3, #0
|
|
800594e: d10b bne.n 8005968 <QSPI_WaitFlagStateUntilTimeout+0x48>
|
|
{
|
|
hqspi->State = HAL_QSPI_STATE_ERROR;
|
|
8005950: 68fb ldr r3, [r7, #12]
|
|
8005952: 2204 movs r2, #4
|
|
8005954: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
|
|
8005958: 68fb ldr r3, [r7, #12]
|
|
800595a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800595c: f043 0201 orr.w r2, r3, #1
|
|
8005960: 68fb ldr r3, [r7, #12]
|
|
8005962: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
8005964: 2301 movs r3, #1
|
|
8005966: e00e b.n 8005986 <QSPI_WaitFlagStateUntilTimeout+0x66>
|
|
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
|
|
8005968: 68fb ldr r3, [r7, #12]
|
|
800596a: 681b ldr r3, [r3, #0]
|
|
800596c: 689a ldr r2, [r3, #8]
|
|
800596e: 68bb ldr r3, [r7, #8]
|
|
8005970: 4013 ands r3, r2
|
|
8005972: 2b00 cmp r3, #0
|
|
8005974: bf14 ite ne
|
|
8005976: 2301 movne r3, #1
|
|
8005978: 2300 moveq r3, #0
|
|
800597a: b2db uxtb r3, r3
|
|
800597c: 461a mov r2, r3
|
|
800597e: 79fb ldrb r3, [r7, #7]
|
|
8005980: 429a cmp r2, r3
|
|
8005982: d1d6 bne.n 8005932 <QSPI_WaitFlagStateUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8005984: 2300 movs r3, #0
|
|
}
|
|
8005986: 4618 mov r0, r3
|
|
8005988: 3710 adds r7, #16
|
|
800598a: 46bd mov sp, r7
|
|
800598c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08005990 <HAL_RCC_OscConfig>:
|
|
* @note If HSE failed to start, HSE should be disabled before recalling
|
|
HAL_RCC_OscConfig().
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8005990: b580 push {r7, lr}
|
|
8005992: b088 sub sp, #32
|
|
8005994: af00 add r7, sp, #0
|
|
8005996: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status;
|
|
uint32_t sysclk_source, pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8005998: 687b ldr r3, [r7, #4]
|
|
800599a: 2b00 cmp r3, #0
|
|
800599c: d101 bne.n 80059a2 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800599e: 2301 movs r3, #1
|
|
80059a0: e3ca b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
80059a2: 4b97 ldr r3, [pc, #604] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
80059a4: 689b ldr r3, [r3, #8]
|
|
80059a6: f003 030c and.w r3, r3, #12
|
|
80059aa: 61bb str r3, [r7, #24]
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
80059ac: 4b94 ldr r3, [pc, #592] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
80059ae: 68db ldr r3, [r3, #12]
|
|
80059b0: f003 0303 and.w r3, r3, #3
|
|
80059b4: 617b str r3, [r7, #20]
|
|
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
80059b6: 687b ldr r3, [r7, #4]
|
|
80059b8: 681b ldr r3, [r3, #0]
|
|
80059ba: f003 0310 and.w r3, r3, #16
|
|
80059be: 2b00 cmp r3, #0
|
|
80059c0: f000 80e4 beq.w 8005b8c <HAL_RCC_OscConfig+0x1fc>
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
80059c4: 69bb ldr r3, [r7, #24]
|
|
80059c6: 2b00 cmp r3, #0
|
|
80059c8: d007 beq.n 80059da <HAL_RCC_OscConfig+0x4a>
|
|
80059ca: 69bb ldr r3, [r7, #24]
|
|
80059cc: 2b0c cmp r3, #12
|
|
80059ce: f040 808b bne.w 8005ae8 <HAL_RCC_OscConfig+0x158>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
|
|
80059d2: 697b ldr r3, [r7, #20]
|
|
80059d4: 2b01 cmp r3, #1
|
|
80059d6: f040 8087 bne.w 8005ae8 <HAL_RCC_OscConfig+0x158>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
80059da: 4b89 ldr r3, [pc, #548] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
80059dc: 681b ldr r3, [r3, #0]
|
|
80059de: f003 0302 and.w r3, r3, #2
|
|
80059e2: 2b00 cmp r3, #0
|
|
80059e4: d005 beq.n 80059f2 <HAL_RCC_OscConfig+0x62>
|
|
80059e6: 687b ldr r3, [r7, #4]
|
|
80059e8: 699b ldr r3, [r3, #24]
|
|
80059ea: 2b00 cmp r3, #0
|
|
80059ec: d101 bne.n 80059f2 <HAL_RCC_OscConfig+0x62>
|
|
{
|
|
return HAL_ERROR;
|
|
80059ee: 2301 movs r3, #1
|
|
80059f0: e3a2 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
else
|
|
{
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
80059f2: 687b ldr r3, [r7, #4]
|
|
80059f4: 6a1a ldr r2, [r3, #32]
|
|
80059f6: 4b82 ldr r3, [pc, #520] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
80059f8: 681b ldr r3, [r3, #0]
|
|
80059fa: f003 0308 and.w r3, r3, #8
|
|
80059fe: 2b00 cmp r3, #0
|
|
8005a00: d004 beq.n 8005a0c <HAL_RCC_OscConfig+0x7c>
|
|
8005a02: 4b7f ldr r3, [pc, #508] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a04: 681b ldr r3, [r3, #0]
|
|
8005a06: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8005a0a: e005 b.n 8005a18 <HAL_RCC_OscConfig+0x88>
|
|
8005a0c: 4b7c ldr r3, [pc, #496] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a0e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8005a12: 091b lsrs r3, r3, #4
|
|
8005a14: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8005a18: 4293 cmp r3, r2
|
|
8005a1a: d223 bcs.n 8005a64 <HAL_RCC_OscConfig+0xd4>
|
|
{
|
|
/* First increase number of wait states update if necessary */
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8005a1c: 687b ldr r3, [r7, #4]
|
|
8005a1e: 6a1b ldr r3, [r3, #32]
|
|
8005a20: 4618 mov r0, r3
|
|
8005a22: f000 fd87 bl 8006534 <RCC_SetFlashLatencyFromMSIRange>
|
|
8005a26: 4603 mov r3, r0
|
|
8005a28: 2b00 cmp r3, #0
|
|
8005a2a: d001 beq.n 8005a30 <HAL_RCC_OscConfig+0xa0>
|
|
{
|
|
return HAL_ERROR;
|
|
8005a2c: 2301 movs r3, #1
|
|
8005a2e: e383 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8005a30: 4b73 ldr r3, [pc, #460] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a32: 681b ldr r3, [r3, #0]
|
|
8005a34: 4a72 ldr r2, [pc, #456] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a36: f043 0308 orr.w r3, r3, #8
|
|
8005a3a: 6013 str r3, [r2, #0]
|
|
8005a3c: 4b70 ldr r3, [pc, #448] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a3e: 681b ldr r3, [r3, #0]
|
|
8005a40: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8005a44: 687b ldr r3, [r7, #4]
|
|
8005a46: 6a1b ldr r3, [r3, #32]
|
|
8005a48: 496d ldr r1, [pc, #436] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a4a: 4313 orrs r3, r2
|
|
8005a4c: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8005a4e: 4b6c ldr r3, [pc, #432] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a50: 685b ldr r3, [r3, #4]
|
|
8005a52: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8005a56: 687b ldr r3, [r7, #4]
|
|
8005a58: 69db ldr r3, [r3, #28]
|
|
8005a5a: 021b lsls r3, r3, #8
|
|
8005a5c: 4968 ldr r1, [pc, #416] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a5e: 4313 orrs r3, r2
|
|
8005a60: 604b str r3, [r1, #4]
|
|
8005a62: e025 b.n 8005ab0 <HAL_RCC_OscConfig+0x120>
|
|
}
|
|
else
|
|
{
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8005a64: 4b66 ldr r3, [pc, #408] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a66: 681b ldr r3, [r3, #0]
|
|
8005a68: 4a65 ldr r2, [pc, #404] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a6a: f043 0308 orr.w r3, r3, #8
|
|
8005a6e: 6013 str r3, [r2, #0]
|
|
8005a70: 4b63 ldr r3, [pc, #396] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a72: 681b ldr r3, [r3, #0]
|
|
8005a74: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8005a78: 687b ldr r3, [r7, #4]
|
|
8005a7a: 6a1b ldr r3, [r3, #32]
|
|
8005a7c: 4960 ldr r1, [pc, #384] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a7e: 4313 orrs r3, r2
|
|
8005a80: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8005a82: 4b5f ldr r3, [pc, #380] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a84: 685b ldr r3, [r3, #4]
|
|
8005a86: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8005a8a: 687b ldr r3, [r7, #4]
|
|
8005a8c: 69db ldr r3, [r3, #28]
|
|
8005a8e: 021b lsls r3, r3, #8
|
|
8005a90: 495b ldr r1, [pc, #364] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005a92: 4313 orrs r3, r2
|
|
8005a94: 604b str r3, [r1, #4]
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
/* Only possible when MSI is the System clock source */
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8005a96: 69bb ldr r3, [r7, #24]
|
|
8005a98: 2b00 cmp r3, #0
|
|
8005a9a: d109 bne.n 8005ab0 <HAL_RCC_OscConfig+0x120>
|
|
{
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8005a9c: 687b ldr r3, [r7, #4]
|
|
8005a9e: 6a1b ldr r3, [r3, #32]
|
|
8005aa0: 4618 mov r0, r3
|
|
8005aa2: f000 fd47 bl 8006534 <RCC_SetFlashLatencyFromMSIRange>
|
|
8005aa6: 4603 mov r3, r0
|
|
8005aa8: 2b00 cmp r3, #0
|
|
8005aaa: d001 beq.n 8005ab0 <HAL_RCC_OscConfig+0x120>
|
|
{
|
|
return HAL_ERROR;
|
|
8005aac: 2301 movs r3, #1
|
|
8005aae: e343 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8005ab0: f000 fc4a bl 8006348 <HAL_RCC_GetSysClockFreq>
|
|
8005ab4: 4602 mov r2, r0
|
|
8005ab6: 4b52 ldr r3, [pc, #328] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005ab8: 689b ldr r3, [r3, #8]
|
|
8005aba: 091b lsrs r3, r3, #4
|
|
8005abc: f003 030f and.w r3, r3, #15
|
|
8005ac0: 4950 ldr r1, [pc, #320] @ (8005c04 <HAL_RCC_OscConfig+0x274>)
|
|
8005ac2: 5ccb ldrb r3, [r1, r3]
|
|
8005ac4: f003 031f and.w r3, r3, #31
|
|
8005ac8: fa22 f303 lsr.w r3, r2, r3
|
|
8005acc: 4a4e ldr r2, [pc, #312] @ (8005c08 <HAL_RCC_OscConfig+0x278>)
|
|
8005ace: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
8005ad0: 4b4e ldr r3, [pc, #312] @ (8005c0c <HAL_RCC_OscConfig+0x27c>)
|
|
8005ad2: 681b ldr r3, [r3, #0]
|
|
8005ad4: 4618 mov r0, r3
|
|
8005ad6: f7fd ff1f bl 8003918 <HAL_InitTick>
|
|
8005ada: 4603 mov r3, r0
|
|
8005adc: 73fb strb r3, [r7, #15]
|
|
if(status != HAL_OK)
|
|
8005ade: 7bfb ldrb r3, [r7, #15]
|
|
8005ae0: 2b00 cmp r3, #0
|
|
8005ae2: d052 beq.n 8005b8a <HAL_RCC_OscConfig+0x1fa>
|
|
{
|
|
return status;
|
|
8005ae4: 7bfb ldrb r3, [r7, #15]
|
|
8005ae6: e327 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the MSI State */
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
8005ae8: 687b ldr r3, [r7, #4]
|
|
8005aea: 699b ldr r3, [r3, #24]
|
|
8005aec: 2b00 cmp r3, #0
|
|
8005aee: d032 beq.n 8005b56 <HAL_RCC_OscConfig+0x1c6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_ENABLE();
|
|
8005af0: 4b43 ldr r3, [pc, #268] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005af2: 681b ldr r3, [r3, #0]
|
|
8005af4: 4a42 ldr r2, [pc, #264] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005af6: f043 0301 orr.w r3, r3, #1
|
|
8005afa: 6013 str r3, [r2, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8005afc: f7fe f900 bl 8003d00 <HAL_GetTick>
|
|
8005b00: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8005b02: e008 b.n 8005b16 <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8005b04: f7fe f8fc bl 8003d00 <HAL_GetTick>
|
|
8005b08: 4602 mov r2, r0
|
|
8005b0a: 693b ldr r3, [r7, #16]
|
|
8005b0c: 1ad3 subs r3, r2, r3
|
|
8005b0e: 2b02 cmp r3, #2
|
|
8005b10: d901 bls.n 8005b16 <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005b12: 2303 movs r3, #3
|
|
8005b14: e310 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8005b16: 4b3a ldr r3, [pc, #232] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b18: 681b ldr r3, [r3, #0]
|
|
8005b1a: f003 0302 and.w r3, r3, #2
|
|
8005b1e: 2b00 cmp r3, #0
|
|
8005b20: d0f0 beq.n 8005b04 <HAL_RCC_OscConfig+0x174>
|
|
}
|
|
}
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8005b22: 4b37 ldr r3, [pc, #220] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b24: 681b ldr r3, [r3, #0]
|
|
8005b26: 4a36 ldr r2, [pc, #216] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b28: f043 0308 orr.w r3, r3, #8
|
|
8005b2c: 6013 str r3, [r2, #0]
|
|
8005b2e: 4b34 ldr r3, [pc, #208] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b30: 681b ldr r3, [r3, #0]
|
|
8005b32: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8005b36: 687b ldr r3, [r7, #4]
|
|
8005b38: 6a1b ldr r3, [r3, #32]
|
|
8005b3a: 4931 ldr r1, [pc, #196] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b3c: 4313 orrs r3, r2
|
|
8005b3e: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8005b40: 4b2f ldr r3, [pc, #188] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b42: 685b ldr r3, [r3, #4]
|
|
8005b44: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8005b48: 687b ldr r3, [r7, #4]
|
|
8005b4a: 69db ldr r3, [r3, #28]
|
|
8005b4c: 021b lsls r3, r3, #8
|
|
8005b4e: 492c ldr r1, [pc, #176] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b50: 4313 orrs r3, r2
|
|
8005b52: 604b str r3, [r1, #4]
|
|
8005b54: e01a b.n 8005b8c <HAL_RCC_OscConfig+0x1fc>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_DISABLE();
|
|
8005b56: 4b2a ldr r3, [pc, #168] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b58: 681b ldr r3, [r3, #0]
|
|
8005b5a: 4a29 ldr r2, [pc, #164] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b5c: f023 0301 bic.w r3, r3, #1
|
|
8005b60: 6013 str r3, [r2, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8005b62: f7fe f8cd bl 8003d00 <HAL_GetTick>
|
|
8005b66: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
8005b68: e008 b.n 8005b7c <HAL_RCC_OscConfig+0x1ec>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8005b6a: f7fe f8c9 bl 8003d00 <HAL_GetTick>
|
|
8005b6e: 4602 mov r2, r0
|
|
8005b70: 693b ldr r3, [r7, #16]
|
|
8005b72: 1ad3 subs r3, r2, r3
|
|
8005b74: 2b02 cmp r3, #2
|
|
8005b76: d901 bls.n 8005b7c <HAL_RCC_OscConfig+0x1ec>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005b78: 2303 movs r3, #3
|
|
8005b7a: e2dd b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
8005b7c: 4b20 ldr r3, [pc, #128] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005b7e: 681b ldr r3, [r3, #0]
|
|
8005b80: f003 0302 and.w r3, r3, #2
|
|
8005b84: 2b00 cmp r3, #0
|
|
8005b86: d1f0 bne.n 8005b6a <HAL_RCC_OscConfig+0x1da>
|
|
8005b88: e000 b.n 8005b8c <HAL_RCC_OscConfig+0x1fc>
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8005b8a: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8005b8c: 687b ldr r3, [r7, #4]
|
|
8005b8e: 681b ldr r3, [r3, #0]
|
|
8005b90: f003 0301 and.w r3, r3, #1
|
|
8005b94: 2b00 cmp r3, #0
|
|
8005b96: d074 beq.n 8005c82 <HAL_RCC_OscConfig+0x2f2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
|
|
8005b98: 69bb ldr r3, [r7, #24]
|
|
8005b9a: 2b08 cmp r3, #8
|
|
8005b9c: d005 beq.n 8005baa <HAL_RCC_OscConfig+0x21a>
|
|
8005b9e: 69bb ldr r3, [r7, #24]
|
|
8005ba0: 2b0c cmp r3, #12
|
|
8005ba2: d10e bne.n 8005bc2 <HAL_RCC_OscConfig+0x232>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
8005ba4: 697b ldr r3, [r7, #20]
|
|
8005ba6: 2b03 cmp r3, #3
|
|
8005ba8: d10b bne.n 8005bc2 <HAL_RCC_OscConfig+0x232>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8005baa: 4b15 ldr r3, [pc, #84] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005bac: 681b ldr r3, [r3, #0]
|
|
8005bae: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005bb2: 2b00 cmp r3, #0
|
|
8005bb4: d064 beq.n 8005c80 <HAL_RCC_OscConfig+0x2f0>
|
|
8005bb6: 687b ldr r3, [r7, #4]
|
|
8005bb8: 685b ldr r3, [r3, #4]
|
|
8005bba: 2b00 cmp r3, #0
|
|
8005bbc: d160 bne.n 8005c80 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_ERROR;
|
|
8005bbe: 2301 movs r3, #1
|
|
8005bc0: e2ba b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8005bc2: 687b ldr r3, [r7, #4]
|
|
8005bc4: 685b ldr r3, [r3, #4]
|
|
8005bc6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8005bca: d106 bne.n 8005bda <HAL_RCC_OscConfig+0x24a>
|
|
8005bcc: 4b0c ldr r3, [pc, #48] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005bce: 681b ldr r3, [r3, #0]
|
|
8005bd0: 4a0b ldr r2, [pc, #44] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005bd2: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8005bd6: 6013 str r3, [r2, #0]
|
|
8005bd8: e026 b.n 8005c28 <HAL_RCC_OscConfig+0x298>
|
|
8005bda: 687b ldr r3, [r7, #4]
|
|
8005bdc: 685b ldr r3, [r3, #4]
|
|
8005bde: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8005be2: d115 bne.n 8005c10 <HAL_RCC_OscConfig+0x280>
|
|
8005be4: 4b06 ldr r3, [pc, #24] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005be6: 681b ldr r3, [r3, #0]
|
|
8005be8: 4a05 ldr r2, [pc, #20] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005bea: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8005bee: 6013 str r3, [r2, #0]
|
|
8005bf0: 4b03 ldr r3, [pc, #12] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005bf2: 681b ldr r3, [r3, #0]
|
|
8005bf4: 4a02 ldr r2, [pc, #8] @ (8005c00 <HAL_RCC_OscConfig+0x270>)
|
|
8005bf6: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8005bfa: 6013 str r3, [r2, #0]
|
|
8005bfc: e014 b.n 8005c28 <HAL_RCC_OscConfig+0x298>
|
|
8005bfe: bf00 nop
|
|
8005c00: 40021000 .word 0x40021000
|
|
8005c04: 08014744 .word 0x08014744
|
|
8005c08: 200000c4 .word 0x200000c4
|
|
8005c0c: 200000c8 .word 0x200000c8
|
|
8005c10: 4ba0 ldr r3, [pc, #640] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005c12: 681b ldr r3, [r3, #0]
|
|
8005c14: 4a9f ldr r2, [pc, #636] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005c16: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8005c1a: 6013 str r3, [r2, #0]
|
|
8005c1c: 4b9d ldr r3, [pc, #628] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005c1e: 681b ldr r3, [r3, #0]
|
|
8005c20: 4a9c ldr r2, [pc, #624] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005c22: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8005c26: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8005c28: 687b ldr r3, [r7, #4]
|
|
8005c2a: 685b ldr r3, [r3, #4]
|
|
8005c2c: 2b00 cmp r3, #0
|
|
8005c2e: d013 beq.n 8005c58 <HAL_RCC_OscConfig+0x2c8>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005c30: f7fe f866 bl 8003d00 <HAL_GetTick>
|
|
8005c34: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8005c36: e008 b.n 8005c4a <HAL_RCC_OscConfig+0x2ba>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8005c38: f7fe f862 bl 8003d00 <HAL_GetTick>
|
|
8005c3c: 4602 mov r2, r0
|
|
8005c3e: 693b ldr r3, [r7, #16]
|
|
8005c40: 1ad3 subs r3, r2, r3
|
|
8005c42: 2b64 cmp r3, #100 @ 0x64
|
|
8005c44: d901 bls.n 8005c4a <HAL_RCC_OscConfig+0x2ba>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005c46: 2303 movs r3, #3
|
|
8005c48: e276 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8005c4a: 4b92 ldr r3, [pc, #584] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005c4c: 681b ldr r3, [r3, #0]
|
|
8005c4e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005c52: 2b00 cmp r3, #0
|
|
8005c54: d0f0 beq.n 8005c38 <HAL_RCC_OscConfig+0x2a8>
|
|
8005c56: e014 b.n 8005c82 <HAL_RCC_OscConfig+0x2f2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005c58: f7fe f852 bl 8003d00 <HAL_GetTick>
|
|
8005c5c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8005c5e: e008 b.n 8005c72 <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8005c60: f7fe f84e bl 8003d00 <HAL_GetTick>
|
|
8005c64: 4602 mov r2, r0
|
|
8005c66: 693b ldr r3, [r7, #16]
|
|
8005c68: 1ad3 subs r3, r2, r3
|
|
8005c6a: 2b64 cmp r3, #100 @ 0x64
|
|
8005c6c: d901 bls.n 8005c72 <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005c6e: 2303 movs r3, #3
|
|
8005c70: e262 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8005c72: 4b88 ldr r3, [pc, #544] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005c74: 681b ldr r3, [r3, #0]
|
|
8005c76: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005c7a: 2b00 cmp r3, #0
|
|
8005c7c: d1f0 bne.n 8005c60 <HAL_RCC_OscConfig+0x2d0>
|
|
8005c7e: e000 b.n 8005c82 <HAL_RCC_OscConfig+0x2f2>
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8005c80: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8005c82: 687b ldr r3, [r7, #4]
|
|
8005c84: 681b ldr r3, [r3, #0]
|
|
8005c86: f003 0302 and.w r3, r3, #2
|
|
8005c8a: 2b00 cmp r3, #0
|
|
8005c8c: d060 beq.n 8005d50 <HAL_RCC_OscConfig+0x3c0>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
|
|
8005c8e: 69bb ldr r3, [r7, #24]
|
|
8005c90: 2b04 cmp r3, #4
|
|
8005c92: d005 beq.n 8005ca0 <HAL_RCC_OscConfig+0x310>
|
|
8005c94: 69bb ldr r3, [r7, #24]
|
|
8005c96: 2b0c cmp r3, #12
|
|
8005c98: d119 bne.n 8005cce <HAL_RCC_OscConfig+0x33e>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
8005c9a: 697b ldr r3, [r7, #20]
|
|
8005c9c: 2b02 cmp r3, #2
|
|
8005c9e: d116 bne.n 8005cce <HAL_RCC_OscConfig+0x33e>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8005ca0: 4b7c ldr r3, [pc, #496] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005ca2: 681b ldr r3, [r3, #0]
|
|
8005ca4: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8005ca8: 2b00 cmp r3, #0
|
|
8005caa: d005 beq.n 8005cb8 <HAL_RCC_OscConfig+0x328>
|
|
8005cac: 687b ldr r3, [r7, #4]
|
|
8005cae: 68db ldr r3, [r3, #12]
|
|
8005cb0: 2b00 cmp r3, #0
|
|
8005cb2: d101 bne.n 8005cb8 <HAL_RCC_OscConfig+0x328>
|
|
{
|
|
return HAL_ERROR;
|
|
8005cb4: 2301 movs r3, #1
|
|
8005cb6: e23f b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8005cb8: 4b76 ldr r3, [pc, #472] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005cba: 685b ldr r3, [r3, #4]
|
|
8005cbc: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
|
|
8005cc0: 687b ldr r3, [r7, #4]
|
|
8005cc2: 691b ldr r3, [r3, #16]
|
|
8005cc4: 061b lsls r3, r3, #24
|
|
8005cc6: 4973 ldr r1, [pc, #460] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005cc8: 4313 orrs r3, r2
|
|
8005cca: 604b str r3, [r1, #4]
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8005ccc: e040 b.n 8005d50 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8005cce: 687b ldr r3, [r7, #4]
|
|
8005cd0: 68db ldr r3, [r3, #12]
|
|
8005cd2: 2b00 cmp r3, #0
|
|
8005cd4: d023 beq.n 8005d1e <HAL_RCC_OscConfig+0x38e>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8005cd6: 4b6f ldr r3, [pc, #444] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005cd8: 681b ldr r3, [r3, #0]
|
|
8005cda: 4a6e ldr r2, [pc, #440] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005cdc: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8005ce0: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005ce2: f7fe f80d bl 8003d00 <HAL_GetTick>
|
|
8005ce6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8005ce8: e008 b.n 8005cfc <HAL_RCC_OscConfig+0x36c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8005cea: f7fe f809 bl 8003d00 <HAL_GetTick>
|
|
8005cee: 4602 mov r2, r0
|
|
8005cf0: 693b ldr r3, [r7, #16]
|
|
8005cf2: 1ad3 subs r3, r2, r3
|
|
8005cf4: 2b02 cmp r3, #2
|
|
8005cf6: d901 bls.n 8005cfc <HAL_RCC_OscConfig+0x36c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005cf8: 2303 movs r3, #3
|
|
8005cfa: e21d b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8005cfc: 4b65 ldr r3, [pc, #404] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005cfe: 681b ldr r3, [r3, #0]
|
|
8005d00: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8005d04: 2b00 cmp r3, #0
|
|
8005d06: d0f0 beq.n 8005cea <HAL_RCC_OscConfig+0x35a>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8005d08: 4b62 ldr r3, [pc, #392] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005d0a: 685b ldr r3, [r3, #4]
|
|
8005d0c: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
|
|
8005d10: 687b ldr r3, [r7, #4]
|
|
8005d12: 691b ldr r3, [r3, #16]
|
|
8005d14: 061b lsls r3, r3, #24
|
|
8005d16: 495f ldr r1, [pc, #380] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005d18: 4313 orrs r3, r2
|
|
8005d1a: 604b str r3, [r1, #4]
|
|
8005d1c: e018 b.n 8005d50 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8005d1e: 4b5d ldr r3, [pc, #372] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005d20: 681b ldr r3, [r3, #0]
|
|
8005d22: 4a5c ldr r2, [pc, #368] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005d24: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005d28: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005d2a: f7fd ffe9 bl 8003d00 <HAL_GetTick>
|
|
8005d2e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8005d30: e008 b.n 8005d44 <HAL_RCC_OscConfig+0x3b4>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8005d32: f7fd ffe5 bl 8003d00 <HAL_GetTick>
|
|
8005d36: 4602 mov r2, r0
|
|
8005d38: 693b ldr r3, [r7, #16]
|
|
8005d3a: 1ad3 subs r3, r2, r3
|
|
8005d3c: 2b02 cmp r3, #2
|
|
8005d3e: d901 bls.n 8005d44 <HAL_RCC_OscConfig+0x3b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005d40: 2303 movs r3, #3
|
|
8005d42: e1f9 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8005d44: 4b53 ldr r3, [pc, #332] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005d46: 681b ldr r3, [r3, #0]
|
|
8005d48: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8005d4c: 2b00 cmp r3, #0
|
|
8005d4e: d1f0 bne.n 8005d32 <HAL_RCC_OscConfig+0x3a2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8005d50: 687b ldr r3, [r7, #4]
|
|
8005d52: 681b ldr r3, [r3, #0]
|
|
8005d54: f003 0308 and.w r3, r3, #8
|
|
8005d58: 2b00 cmp r3, #0
|
|
8005d5a: d03c beq.n 8005dd6 <HAL_RCC_OscConfig+0x446>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8005d5c: 687b ldr r3, [r7, #4]
|
|
8005d5e: 695b ldr r3, [r3, #20]
|
|
8005d60: 2b00 cmp r3, #0
|
|
8005d62: d01c beq.n 8005d9e <HAL_RCC_OscConfig+0x40e>
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
|
|
}
|
|
#endif /* RCC_CSR_LSIPREDIV */
|
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8005d64: 4b4b ldr r3, [pc, #300] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005d66: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8005d6a: 4a4a ldr r2, [pc, #296] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005d6c: f043 0301 orr.w r3, r3, #1
|
|
8005d70: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005d74: f7fd ffc4 bl 8003d00 <HAL_GetTick>
|
|
8005d78: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8005d7a: e008 b.n 8005d8e <HAL_RCC_OscConfig+0x3fe>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8005d7c: f7fd ffc0 bl 8003d00 <HAL_GetTick>
|
|
8005d80: 4602 mov r2, r0
|
|
8005d82: 693b ldr r3, [r7, #16]
|
|
8005d84: 1ad3 subs r3, r2, r3
|
|
8005d86: 2b02 cmp r3, #2
|
|
8005d88: d901 bls.n 8005d8e <HAL_RCC_OscConfig+0x3fe>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005d8a: 2303 movs r3, #3
|
|
8005d8c: e1d4 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8005d8e: 4b41 ldr r3, [pc, #260] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005d90: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8005d94: f003 0302 and.w r3, r3, #2
|
|
8005d98: 2b00 cmp r3, #0
|
|
8005d9a: d0ef beq.n 8005d7c <HAL_RCC_OscConfig+0x3ec>
|
|
8005d9c: e01b b.n 8005dd6 <HAL_RCC_OscConfig+0x446>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8005d9e: 4b3d ldr r3, [pc, #244] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005da0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8005da4: 4a3b ldr r2, [pc, #236] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005da6: f023 0301 bic.w r3, r3, #1
|
|
8005daa: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005dae: f7fd ffa7 bl 8003d00 <HAL_GetTick>
|
|
8005db2: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8005db4: e008 b.n 8005dc8 <HAL_RCC_OscConfig+0x438>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8005db6: f7fd ffa3 bl 8003d00 <HAL_GetTick>
|
|
8005dba: 4602 mov r2, r0
|
|
8005dbc: 693b ldr r3, [r7, #16]
|
|
8005dbe: 1ad3 subs r3, r2, r3
|
|
8005dc0: 2b02 cmp r3, #2
|
|
8005dc2: d901 bls.n 8005dc8 <HAL_RCC_OscConfig+0x438>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005dc4: 2303 movs r3, #3
|
|
8005dc6: e1b7 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8005dc8: 4b32 ldr r3, [pc, #200] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005dca: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8005dce: f003 0302 and.w r3, r3, #2
|
|
8005dd2: 2b00 cmp r3, #0
|
|
8005dd4: d1ef bne.n 8005db6 <HAL_RCC_OscConfig+0x426>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8005dd6: 687b ldr r3, [r7, #4]
|
|
8005dd8: 681b ldr r3, [r3, #0]
|
|
8005dda: f003 0304 and.w r3, r3, #4
|
|
8005dde: 2b00 cmp r3, #0
|
|
8005de0: f000 80a6 beq.w 8005f30 <HAL_RCC_OscConfig+0x5a0>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8005de4: 2300 movs r3, #0
|
|
8005de6: 77fb strb r3, [r7, #31]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
|
|
8005de8: 4b2a ldr r3, [pc, #168] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005dea: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005dec: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005df0: 2b00 cmp r3, #0
|
|
8005df2: d10d bne.n 8005e10 <HAL_RCC_OscConfig+0x480>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8005df4: 4b27 ldr r3, [pc, #156] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005df6: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005df8: 4a26 ldr r2, [pc, #152] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005dfa: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005dfe: 6593 str r3, [r2, #88] @ 0x58
|
|
8005e00: 4b24 ldr r3, [pc, #144] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005e02: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005e04: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005e08: 60bb str r3, [r7, #8]
|
|
8005e0a: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8005e0c: 2301 movs r3, #1
|
|
8005e0e: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8005e10: 4b21 ldr r3, [pc, #132] @ (8005e98 <HAL_RCC_OscConfig+0x508>)
|
|
8005e12: 681b ldr r3, [r3, #0]
|
|
8005e14: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005e18: 2b00 cmp r3, #0
|
|
8005e1a: d118 bne.n 8005e4e <HAL_RCC_OscConfig+0x4be>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8005e1c: 4b1e ldr r3, [pc, #120] @ (8005e98 <HAL_RCC_OscConfig+0x508>)
|
|
8005e1e: 681b ldr r3, [r3, #0]
|
|
8005e20: 4a1d ldr r2, [pc, #116] @ (8005e98 <HAL_RCC_OscConfig+0x508>)
|
|
8005e22: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8005e26: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8005e28: f7fd ff6a bl 8003d00 <HAL_GetTick>
|
|
8005e2c: 6138 str r0, [r7, #16]
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8005e2e: e008 b.n 8005e42 <HAL_RCC_OscConfig+0x4b2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8005e30: f7fd ff66 bl 8003d00 <HAL_GetTick>
|
|
8005e34: 4602 mov r2, r0
|
|
8005e36: 693b ldr r3, [r7, #16]
|
|
8005e38: 1ad3 subs r3, r2, r3
|
|
8005e3a: 2b02 cmp r3, #2
|
|
8005e3c: d901 bls.n 8005e42 <HAL_RCC_OscConfig+0x4b2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005e3e: 2303 movs r3, #3
|
|
8005e40: e17a b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8005e42: 4b15 ldr r3, [pc, #84] @ (8005e98 <HAL_RCC_OscConfig+0x508>)
|
|
8005e44: 681b ldr r3, [r3, #0]
|
|
8005e46: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005e4a: 2b00 cmp r3, #0
|
|
8005e4c: d0f0 beq.n 8005e30 <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
}
|
|
#else
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8005e4e: 687b ldr r3, [r7, #4]
|
|
8005e50: 689b ldr r3, [r3, #8]
|
|
8005e52: 2b01 cmp r3, #1
|
|
8005e54: d108 bne.n 8005e68 <HAL_RCC_OscConfig+0x4d8>
|
|
8005e56: 4b0f ldr r3, [pc, #60] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005e58: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005e5c: 4a0d ldr r2, [pc, #52] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005e5e: f043 0301 orr.w r3, r3, #1
|
|
8005e62: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8005e66: e029 b.n 8005ebc <HAL_RCC_OscConfig+0x52c>
|
|
8005e68: 687b ldr r3, [r7, #4]
|
|
8005e6a: 689b ldr r3, [r3, #8]
|
|
8005e6c: 2b05 cmp r3, #5
|
|
8005e6e: d115 bne.n 8005e9c <HAL_RCC_OscConfig+0x50c>
|
|
8005e70: 4b08 ldr r3, [pc, #32] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005e72: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005e76: 4a07 ldr r2, [pc, #28] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005e78: f043 0304 orr.w r3, r3, #4
|
|
8005e7c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8005e80: 4b04 ldr r3, [pc, #16] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005e82: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005e86: 4a03 ldr r2, [pc, #12] @ (8005e94 <HAL_RCC_OscConfig+0x504>)
|
|
8005e88: f043 0301 orr.w r3, r3, #1
|
|
8005e8c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8005e90: e014 b.n 8005ebc <HAL_RCC_OscConfig+0x52c>
|
|
8005e92: bf00 nop
|
|
8005e94: 40021000 .word 0x40021000
|
|
8005e98: 40007000 .word 0x40007000
|
|
8005e9c: 4b9c ldr r3, [pc, #624] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005e9e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005ea2: 4a9b ldr r2, [pc, #620] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005ea4: f023 0301 bic.w r3, r3, #1
|
|
8005ea8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8005eac: 4b98 ldr r3, [pc, #608] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005eae: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005eb2: 4a97 ldr r2, [pc, #604] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005eb4: f023 0304 bic.w r3, r3, #4
|
|
8005eb8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8005ebc: 687b ldr r3, [r7, #4]
|
|
8005ebe: 689b ldr r3, [r3, #8]
|
|
8005ec0: 2b00 cmp r3, #0
|
|
8005ec2: d016 beq.n 8005ef2 <HAL_RCC_OscConfig+0x562>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005ec4: f7fd ff1c bl 8003d00 <HAL_GetTick>
|
|
8005ec8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8005eca: e00a b.n 8005ee2 <HAL_RCC_OscConfig+0x552>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005ecc: f7fd ff18 bl 8003d00 <HAL_GetTick>
|
|
8005ed0: 4602 mov r2, r0
|
|
8005ed2: 693b ldr r3, [r7, #16]
|
|
8005ed4: 1ad3 subs r3, r2, r3
|
|
8005ed6: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005eda: 4293 cmp r3, r2
|
|
8005edc: d901 bls.n 8005ee2 <HAL_RCC_OscConfig+0x552>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005ede: 2303 movs r3, #3
|
|
8005ee0: e12a b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8005ee2: 4b8b ldr r3, [pc, #556] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005ee4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005ee8: f003 0302 and.w r3, r3, #2
|
|
8005eec: 2b00 cmp r3, #0
|
|
8005eee: d0ed beq.n 8005ecc <HAL_RCC_OscConfig+0x53c>
|
|
8005ef0: e015 b.n 8005f1e <HAL_RCC_OscConfig+0x58e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005ef2: f7fd ff05 bl 8003d00 <HAL_GetTick>
|
|
8005ef6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8005ef8: e00a b.n 8005f10 <HAL_RCC_OscConfig+0x580>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005efa: f7fd ff01 bl 8003d00 <HAL_GetTick>
|
|
8005efe: 4602 mov r2, r0
|
|
8005f00: 693b ldr r3, [r7, #16]
|
|
8005f02: 1ad3 subs r3, r2, r3
|
|
8005f04: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005f08: 4293 cmp r3, r2
|
|
8005f0a: d901 bls.n 8005f10 <HAL_RCC_OscConfig+0x580>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005f0c: 2303 movs r3, #3
|
|
8005f0e: e113 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8005f10: 4b7f ldr r3, [pc, #508] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005f12: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005f16: f003 0302 and.w r3, r3, #2
|
|
8005f1a: 2b00 cmp r3, #0
|
|
8005f1c: d1ed bne.n 8005efa <HAL_RCC_OscConfig+0x56a>
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
8005f1e: 7ffb ldrb r3, [r7, #31]
|
|
8005f20: 2b01 cmp r3, #1
|
|
8005f22: d105 bne.n 8005f30 <HAL_RCC_OscConfig+0x5a0>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8005f24: 4b7a ldr r3, [pc, #488] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005f26: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005f28: 4a79 ldr r2, [pc, #484] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005f2a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8005f2e: 6593 str r3, [r2, #88] @ 0x58
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
8005f30: 687b ldr r3, [r7, #4]
|
|
8005f32: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005f34: 2b00 cmp r3, #0
|
|
8005f36: f000 80fe beq.w 8006136 <HAL_RCC_OscConfig+0x7a6>
|
|
{
|
|
/* PLL On ? */
|
|
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8005f3a: 687b ldr r3, [r7, #4]
|
|
8005f3c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005f3e: 2b02 cmp r3, #2
|
|
8005f40: f040 80d0 bne.w 80060e4 <HAL_RCC_OscConfig+0x754>
|
|
#endif /* RCC_PLLP_SUPPORT */
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Do nothing if PLL configuration is the unchanged */
|
|
pll_config = RCC->PLLCFGR;
|
|
8005f44: 4b72 ldr r3, [pc, #456] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005f46: 68db ldr r3, [r3, #12]
|
|
8005f48: 617b str r3, [r7, #20]
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8005f4a: 697b ldr r3, [r7, #20]
|
|
8005f4c: f003 0203 and.w r2, r3, #3
|
|
8005f50: 687b ldr r3, [r7, #4]
|
|
8005f52: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8005f54: 429a cmp r2, r3
|
|
8005f56: d130 bne.n 8005fba <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8005f58: 697b ldr r3, [r7, #20]
|
|
8005f5a: f003 0270 and.w r2, r3, #112 @ 0x70
|
|
8005f5e: 687b ldr r3, [r7, #4]
|
|
8005f60: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005f62: 3b01 subs r3, #1
|
|
8005f64: 011b lsls r3, r3, #4
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8005f66: 429a cmp r2, r3
|
|
8005f68: d127 bne.n 8005fba <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8005f6a: 697b ldr r3, [r7, #20]
|
|
8005f6c: f403 42fe and.w r2, r3, #32512 @ 0x7f00
|
|
8005f70: 687b ldr r3, [r7, #4]
|
|
8005f72: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8005f74: 021b lsls r3, r3, #8
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8005f76: 429a cmp r2, r3
|
|
8005f78: d11f bne.n 8005fba <HAL_RCC_OscConfig+0x62a>
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
#else
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
8005f7a: 697b ldr r3, [r7, #20]
|
|
8005f7c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005f80: 687a ldr r2, [r7, #4]
|
|
8005f82: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
8005f84: 2a07 cmp r2, #7
|
|
8005f86: bf14 ite ne
|
|
8005f88: 2201 movne r2, #1
|
|
8005f8a: 2200 moveq r2, #0
|
|
8005f8c: b2d2 uxtb r2, r2
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8005f8e: 4293 cmp r3, r2
|
|
8005f90: d113 bne.n 8005fba <HAL_RCC_OscConfig+0x62a>
|
|
#endif
|
|
#endif
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8005f92: 697b ldr r3, [r7, #20]
|
|
8005f94: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
|
|
8005f98: 687b ldr r3, [r7, #4]
|
|
8005f9a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005f9c: 085b lsrs r3, r3, #1
|
|
8005f9e: 3b01 subs r3, #1
|
|
8005fa0: 055b lsls r3, r3, #21
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
8005fa2: 429a cmp r2, r3
|
|
8005fa4: d109 bne.n 8005fba <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
|
8005fa6: 697b ldr r3, [r7, #20]
|
|
8005fa8: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
|
|
8005fac: 687b ldr r3, [r7, #4]
|
|
8005fae: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005fb0: 085b lsrs r3, r3, #1
|
|
8005fb2: 3b01 subs r3, #1
|
|
8005fb4: 065b lsls r3, r3, #25
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8005fb6: 429a cmp r2, r3
|
|
8005fb8: d06e beq.n 8006098 <HAL_RCC_OscConfig+0x708>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
8005fba: 69bb ldr r3, [r7, #24]
|
|
8005fbc: 2b0c cmp r3, #12
|
|
8005fbe: d069 beq.n 8006094 <HAL_RCC_OscConfig+0x704>
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
|
|
/* Check if main PLL can be updated */
|
|
/* Not possible if the source is shared by other enabled PLLSAIx */
|
|
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
|
|
8005fc0: 4b53 ldr r3, [pc, #332] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005fc2: 681b ldr r3, [r3, #0]
|
|
8005fc4: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8005fc8: 2b00 cmp r3, #0
|
|
8005fca: d105 bne.n 8005fd8 <HAL_RCC_OscConfig+0x648>
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
|
|
8005fcc: 4b50 ldr r3, [pc, #320] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005fce: 681b ldr r3, [r3, #0]
|
|
8005fd0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005fd4: 2b00 cmp r3, #0
|
|
8005fd6: d001 beq.n 8005fdc <HAL_RCC_OscConfig+0x64c>
|
|
#endif
|
|
)
|
|
{
|
|
return HAL_ERROR;
|
|
8005fd8: 2301 movs r3, #1
|
|
8005fda: e0ad b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
else
|
|
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8005fdc: 4b4c ldr r3, [pc, #304] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005fde: 681b ldr r3, [r3, #0]
|
|
8005fe0: 4a4b ldr r2, [pc, #300] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8005fe2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
8005fe6: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005fe8: f7fd fe8a bl 8003d00 <HAL_GetTick>
|
|
8005fec: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8005fee: e008 b.n 8006002 <HAL_RCC_OscConfig+0x672>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8005ff0: f7fd fe86 bl 8003d00 <HAL_GetTick>
|
|
8005ff4: 4602 mov r2, r0
|
|
8005ff6: 693b ldr r3, [r7, #16]
|
|
8005ff8: 1ad3 subs r3, r2, r3
|
|
8005ffa: 2b02 cmp r3, #2
|
|
8005ffc: d901 bls.n 8006002 <HAL_RCC_OscConfig+0x672>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005ffe: 2303 movs r3, #3
|
|
8006000: e09a b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8006002: 4b43 ldr r3, [pc, #268] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8006004: 681b ldr r3, [r3, #0]
|
|
8006006: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800600a: 2b00 cmp r3, #0
|
|
800600c: d1f0 bne.n 8005ff0 <HAL_RCC_OscConfig+0x660>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
800600e: 4b40 ldr r3, [pc, #256] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8006010: 68da ldr r2, [r3, #12]
|
|
8006012: 4b40 ldr r3, [pc, #256] @ (8006114 <HAL_RCC_OscConfig+0x784>)
|
|
8006014: 4013 ands r3, r2
|
|
8006016: 687a ldr r2, [r7, #4]
|
|
8006018: 6ad1 ldr r1, [r2, #44] @ 0x2c
|
|
800601a: 687a ldr r2, [r7, #4]
|
|
800601c: 6b12 ldr r2, [r2, #48] @ 0x30
|
|
800601e: 3a01 subs r2, #1
|
|
8006020: 0112 lsls r2, r2, #4
|
|
8006022: 4311 orrs r1, r2
|
|
8006024: 687a ldr r2, [r7, #4]
|
|
8006026: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
8006028: 0212 lsls r2, r2, #8
|
|
800602a: 4311 orrs r1, r2
|
|
800602c: 687a ldr r2, [r7, #4]
|
|
800602e: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
8006030: 0852 lsrs r2, r2, #1
|
|
8006032: 3a01 subs r2, #1
|
|
8006034: 0552 lsls r2, r2, #21
|
|
8006036: 4311 orrs r1, r2
|
|
8006038: 687a ldr r2, [r7, #4]
|
|
800603a: 6c12 ldr r2, [r2, #64] @ 0x40
|
|
800603c: 0852 lsrs r2, r2, #1
|
|
800603e: 3a01 subs r2, #1
|
|
8006040: 0652 lsls r2, r2, #25
|
|
8006042: 4311 orrs r1, r2
|
|
8006044: 687a ldr r2, [r7, #4]
|
|
8006046: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
8006048: 0912 lsrs r2, r2, #4
|
|
800604a: 0452 lsls r2, r2, #17
|
|
800604c: 430a orrs r2, r1
|
|
800604e: 4930 ldr r1, [pc, #192] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8006050: 4313 orrs r3, r2
|
|
8006052: 60cb str r3, [r1, #12]
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
#endif
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8006054: 4b2e ldr r3, [pc, #184] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8006056: 681b ldr r3, [r3, #0]
|
|
8006058: 4a2d ldr r2, [pc, #180] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
800605a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
800605e: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
8006060: 4b2b ldr r3, [pc, #172] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8006062: 68db ldr r3, [r3, #12]
|
|
8006064: 4a2a ldr r2, [pc, #168] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8006066: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
800606a: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800606c: f7fd fe48 bl 8003d00 <HAL_GetTick>
|
|
8006070: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8006072: e008 b.n 8006086 <HAL_RCC_OscConfig+0x6f6>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8006074: f7fd fe44 bl 8003d00 <HAL_GetTick>
|
|
8006078: 4602 mov r2, r0
|
|
800607a: 693b ldr r3, [r7, #16]
|
|
800607c: 1ad3 subs r3, r2, r3
|
|
800607e: 2b02 cmp r3, #2
|
|
8006080: d901 bls.n 8006086 <HAL_RCC_OscConfig+0x6f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006082: 2303 movs r3, #3
|
|
8006084: e058 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8006086: 4b22 ldr r3, [pc, #136] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
8006088: 681b ldr r3, [r3, #0]
|
|
800608a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800608e: 2b00 cmp r3, #0
|
|
8006090: d0f0 beq.n 8006074 <HAL_RCC_OscConfig+0x6e4>
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
8006092: e050 b.n 8006136 <HAL_RCC_OscConfig+0x7a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
8006094: 2301 movs r3, #1
|
|
8006096: e04f b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
else
|
|
{
|
|
/* PLL configuration is unchanged */
|
|
/* Re-enable PLL if it was disabled (ie. low power mode) */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8006098: 4b1d ldr r3, [pc, #116] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
800609a: 681b ldr r3, [r3, #0]
|
|
800609c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80060a0: 2b00 cmp r3, #0
|
|
80060a2: d148 bne.n 8006136 <HAL_RCC_OscConfig+0x7a6>
|
|
{
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80060a4: 4b1a ldr r3, [pc, #104] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
80060a6: 681b ldr r3, [r3, #0]
|
|
80060a8: 4a19 ldr r2, [pc, #100] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
80060aa: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
80060ae: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
80060b0: 4b17 ldr r3, [pc, #92] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
80060b2: 68db ldr r3, [r3, #12]
|
|
80060b4: 4a16 ldr r2, [pc, #88] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
80060b6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
80060ba: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80060bc: f7fd fe20 bl 8003d00 <HAL_GetTick>
|
|
80060c0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80060c2: e008 b.n 80060d6 <HAL_RCC_OscConfig+0x746>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80060c4: f7fd fe1c bl 8003d00 <HAL_GetTick>
|
|
80060c8: 4602 mov r2, r0
|
|
80060ca: 693b ldr r3, [r7, #16]
|
|
80060cc: 1ad3 subs r3, r2, r3
|
|
80060ce: 2b02 cmp r3, #2
|
|
80060d0: d901 bls.n 80060d6 <HAL_RCC_OscConfig+0x746>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80060d2: 2303 movs r3, #3
|
|
80060d4: e030 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80060d6: 4b0e ldr r3, [pc, #56] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
80060d8: 681b ldr r3, [r3, #0]
|
|
80060da: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80060de: 2b00 cmp r3, #0
|
|
80060e0: d0f0 beq.n 80060c4 <HAL_RCC_OscConfig+0x734>
|
|
80060e2: e028 b.n 8006136 <HAL_RCC_OscConfig+0x7a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check that PLL is not used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
80060e4: 69bb ldr r3, [r7, #24]
|
|
80060e6: 2b0c cmp r3, #12
|
|
80060e8: d023 beq.n 8006132 <HAL_RCC_OscConfig+0x7a2>
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80060ea: 4b09 ldr r3, [pc, #36] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
80060ec: 681b ldr r3, [r3, #0]
|
|
80060ee: 4a08 ldr r2, [pc, #32] @ (8006110 <HAL_RCC_OscConfig+0x780>)
|
|
80060f0: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
80060f4: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80060f6: f7fd fe03 bl 8003d00 <HAL_GetTick>
|
|
80060fa: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
80060fc: e00c b.n 8006118 <HAL_RCC_OscConfig+0x788>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80060fe: f7fd fdff bl 8003d00 <HAL_GetTick>
|
|
8006102: 4602 mov r2, r0
|
|
8006104: 693b ldr r3, [r7, #16]
|
|
8006106: 1ad3 subs r3, r2, r3
|
|
8006108: 2b02 cmp r3, #2
|
|
800610a: d905 bls.n 8006118 <HAL_RCC_OscConfig+0x788>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800610c: 2303 movs r3, #3
|
|
800610e: e013 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
8006110: 40021000 .word 0x40021000
|
|
8006114: f99d808c .word 0xf99d808c
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8006118: 4b09 ldr r3, [pc, #36] @ (8006140 <HAL_RCC_OscConfig+0x7b0>)
|
|
800611a: 681b ldr r3, [r3, #0]
|
|
800611c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8006120: 2b00 cmp r3, #0
|
|
8006122: d1ec bne.n 80060fe <HAL_RCC_OscConfig+0x76e>
|
|
}
|
|
}
|
|
/* Unselect main PLL clock source and disable main PLL outputs to save power */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
|
|
8006124: 4b06 ldr r3, [pc, #24] @ (8006140 <HAL_RCC_OscConfig+0x7b0>)
|
|
8006126: 68da ldr r2, [r3, #12]
|
|
8006128: 4905 ldr r1, [pc, #20] @ (8006140 <HAL_RCC_OscConfig+0x7b0>)
|
|
800612a: 4b06 ldr r3, [pc, #24] @ (8006144 <HAL_RCC_OscConfig+0x7b4>)
|
|
800612c: 4013 ands r3, r2
|
|
800612e: 60cb str r3, [r1, #12]
|
|
8006130: e001 b.n 8006136 <HAL_RCC_OscConfig+0x7a6>
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
8006132: 2301 movs r3, #1
|
|
8006134: e000 b.n 8006138 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8006136: 2300 movs r3, #0
|
|
}
|
|
8006138: 4618 mov r0, r3
|
|
800613a: 3720 adds r7, #32
|
|
800613c: 46bd mov sp, r7
|
|
800613e: bd80 pop {r7, pc}
|
|
8006140: 40021000 .word 0x40021000
|
|
8006144: feeefffc .word 0xfeeefffc
|
|
|
|
08006148 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8006148: b580 push {r7, lr}
|
|
800614a: b084 sub sp, #16
|
|
800614c: af00 add r7, sp, #0
|
|
800614e: 6078 str r0, [r7, #4]
|
|
8006150: 6039 str r1, [r7, #0]
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
|
#endif
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
8006152: 687b ldr r3, [r7, #4]
|
|
8006154: 2b00 cmp r3, #0
|
|
8006156: d101 bne.n 800615c <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8006158: 2301 movs r3, #1
|
|
800615a: e0e7 b.n 800632c <HAL_RCC_ClockConfig+0x1e4>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
800615c: 4b75 ldr r3, [pc, #468] @ (8006334 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800615e: 681b ldr r3, [r3, #0]
|
|
8006160: f003 0307 and.w r3, r3, #7
|
|
8006164: 683a ldr r2, [r7, #0]
|
|
8006166: 429a cmp r2, r3
|
|
8006168: d910 bls.n 800618c <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800616a: 4b72 ldr r3, [pc, #456] @ (8006334 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800616c: 681b ldr r3, [r3, #0]
|
|
800616e: f023 0207 bic.w r2, r3, #7
|
|
8006172: 4970 ldr r1, [pc, #448] @ (8006334 <HAL_RCC_ClockConfig+0x1ec>)
|
|
8006174: 683b ldr r3, [r7, #0]
|
|
8006176: 4313 orrs r3, r2
|
|
8006178: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800617a: 4b6e ldr r3, [pc, #440] @ (8006334 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800617c: 681b ldr r3, [r3, #0]
|
|
800617e: f003 0307 and.w r3, r3, #7
|
|
8006182: 683a ldr r2, [r7, #0]
|
|
8006184: 429a cmp r2, r3
|
|
8006186: d001 beq.n 800618c <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8006188: 2301 movs r3, #1
|
|
800618a: e0cf b.n 800632c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
|
|
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
|
|
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
800618c: 687b ldr r3, [r7, #4]
|
|
800618e: 681b ldr r3, [r3, #0]
|
|
8006190: f003 0302 and.w r3, r3, #2
|
|
8006194: 2b00 cmp r3, #0
|
|
8006196: d010 beq.n 80061ba <HAL_RCC_ClockConfig+0x72>
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
|
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
8006198: 687b ldr r3, [r7, #4]
|
|
800619a: 689a ldr r2, [r3, #8]
|
|
800619c: 4b66 ldr r3, [pc, #408] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800619e: 689b ldr r3, [r3, #8]
|
|
80061a0: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
80061a4: 429a cmp r2, r3
|
|
80061a6: d908 bls.n 80061ba <HAL_RCC_ClockConfig+0x72>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
80061a8: 4b63 ldr r3, [pc, #396] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80061aa: 689b ldr r3, [r3, #8]
|
|
80061ac: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
80061b0: 687b ldr r3, [r7, #4]
|
|
80061b2: 689b ldr r3, [r3, #8]
|
|
80061b4: 4960 ldr r1, [pc, #384] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80061b6: 4313 orrs r3, r2
|
|
80061b8: 608b str r3, [r1, #8]
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
80061ba: 687b ldr r3, [r7, #4]
|
|
80061bc: 681b ldr r3, [r3, #0]
|
|
80061be: f003 0301 and.w r3, r3, #1
|
|
80061c2: 2b00 cmp r3, #0
|
|
80061c4: d04c beq.n 8006260 <HAL_RCC_ClockConfig+0x118>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
80061c6: 687b ldr r3, [r7, #4]
|
|
80061c8: 685b ldr r3, [r3, #4]
|
|
80061ca: 2b03 cmp r3, #3
|
|
80061cc: d107 bne.n 80061de <HAL_RCC_ClockConfig+0x96>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80061ce: 4b5a ldr r3, [pc, #360] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80061d0: 681b ldr r3, [r3, #0]
|
|
80061d2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80061d6: 2b00 cmp r3, #0
|
|
80061d8: d121 bne.n 800621e <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80061da: 2301 movs r3, #1
|
|
80061dc: e0a6 b.n 800632c <HAL_RCC_ClockConfig+0x1e4>
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
80061de: 687b ldr r3, [r7, #4]
|
|
80061e0: 685b ldr r3, [r3, #4]
|
|
80061e2: 2b02 cmp r3, #2
|
|
80061e4: d107 bne.n 80061f6 <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80061e6: 4b54 ldr r3, [pc, #336] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80061e8: 681b ldr r3, [r3, #0]
|
|
80061ea: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80061ee: 2b00 cmp r3, #0
|
|
80061f0: d115 bne.n 800621e <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80061f2: 2301 movs r3, #1
|
|
80061f4: e09a b.n 800632c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
80061f6: 687b ldr r3, [r7, #4]
|
|
80061f8: 685b ldr r3, [r3, #4]
|
|
80061fa: 2b00 cmp r3, #0
|
|
80061fc: d107 bne.n 800620e <HAL_RCC_ClockConfig+0xc6>
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
80061fe: 4b4e ldr r3, [pc, #312] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8006200: 681b ldr r3, [r3, #0]
|
|
8006202: f003 0302 and.w r3, r3, #2
|
|
8006206: 2b00 cmp r3, #0
|
|
8006208: d109 bne.n 800621e <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
800620a: 2301 movs r3, #1
|
|
800620c: e08e b.n 800632c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
800620e: 4b4a ldr r3, [pc, #296] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8006210: 681b ldr r3, [r3, #0]
|
|
8006212: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8006216: 2b00 cmp r3, #0
|
|
8006218: d101 bne.n 800621e <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
800621a: 2301 movs r3, #1
|
|
800621c: e086 b.n 800632c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
800621e: 4b46 ldr r3, [pc, #280] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8006220: 689b ldr r3, [r3, #8]
|
|
8006222: f023 0203 bic.w r2, r3, #3
|
|
8006226: 687b ldr r3, [r7, #4]
|
|
8006228: 685b ldr r3, [r3, #4]
|
|
800622a: 4943 ldr r1, [pc, #268] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800622c: 4313 orrs r3, r2
|
|
800622e: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8006230: f7fd fd66 bl 8003d00 <HAL_GetTick>
|
|
8006234: 60f8 str r0, [r7, #12]
|
|
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8006236: e00a b.n 800624e <HAL_RCC_ClockConfig+0x106>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8006238: f7fd fd62 bl 8003d00 <HAL_GetTick>
|
|
800623c: 4602 mov r2, r0
|
|
800623e: 68fb ldr r3, [r7, #12]
|
|
8006240: 1ad3 subs r3, r2, r3
|
|
8006242: f241 3288 movw r2, #5000 @ 0x1388
|
|
8006246: 4293 cmp r3, r2
|
|
8006248: d901 bls.n 800624e <HAL_RCC_ClockConfig+0x106>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800624a: 2303 movs r3, #3
|
|
800624c: e06e b.n 800632c <HAL_RCC_ClockConfig+0x1e4>
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800624e: 4b3a ldr r3, [pc, #232] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8006250: 689b ldr r3, [r3, #8]
|
|
8006252: f003 020c and.w r2, r3, #12
|
|
8006256: 687b ldr r3, [r7, #4]
|
|
8006258: 685b ldr r3, [r3, #4]
|
|
800625a: 009b lsls r3, r3, #2
|
|
800625c: 429a cmp r2, r3
|
|
800625e: d1eb bne.n 8006238 <HAL_RCC_ClockConfig+0xf0>
|
|
}
|
|
#endif
|
|
|
|
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
|
|
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8006260: 687b ldr r3, [r7, #4]
|
|
8006262: 681b ldr r3, [r3, #0]
|
|
8006264: f003 0302 and.w r3, r3, #2
|
|
8006268: 2b00 cmp r3, #0
|
|
800626a: d010 beq.n 800628e <HAL_RCC_ClockConfig+0x146>
|
|
{
|
|
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
800626c: 687b ldr r3, [r7, #4]
|
|
800626e: 689a ldr r2, [r3, #8]
|
|
8006270: 4b31 ldr r3, [pc, #196] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8006272: 689b ldr r3, [r3, #8]
|
|
8006274: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8006278: 429a cmp r2, r3
|
|
800627a: d208 bcs.n 800628e <HAL_RCC_ClockConfig+0x146>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
800627c: 4b2e ldr r3, [pc, #184] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800627e: 689b ldr r3, [r3, #8]
|
|
8006280: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8006284: 687b ldr r3, [r7, #4]
|
|
8006286: 689b ldr r3, [r3, #8]
|
|
8006288: 492b ldr r1, [pc, #172] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800628a: 4313 orrs r3, r2
|
|
800628c: 608b str r3, [r1, #8]
|
|
}
|
|
}
|
|
|
|
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
800628e: 4b29 ldr r3, [pc, #164] @ (8006334 <HAL_RCC_ClockConfig+0x1ec>)
|
|
8006290: 681b ldr r3, [r3, #0]
|
|
8006292: f003 0307 and.w r3, r3, #7
|
|
8006296: 683a ldr r2, [r7, #0]
|
|
8006298: 429a cmp r2, r3
|
|
800629a: d210 bcs.n 80062be <HAL_RCC_ClockConfig+0x176>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800629c: 4b25 ldr r3, [pc, #148] @ (8006334 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800629e: 681b ldr r3, [r3, #0]
|
|
80062a0: f023 0207 bic.w r2, r3, #7
|
|
80062a4: 4923 ldr r1, [pc, #140] @ (8006334 <HAL_RCC_ClockConfig+0x1ec>)
|
|
80062a6: 683b ldr r3, [r7, #0]
|
|
80062a8: 4313 orrs r3, r2
|
|
80062aa: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80062ac: 4b21 ldr r3, [pc, #132] @ (8006334 <HAL_RCC_ClockConfig+0x1ec>)
|
|
80062ae: 681b ldr r3, [r3, #0]
|
|
80062b0: f003 0307 and.w r3, r3, #7
|
|
80062b4: 683a ldr r2, [r7, #0]
|
|
80062b6: 429a cmp r2, r3
|
|
80062b8: d001 beq.n 80062be <HAL_RCC_ClockConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
80062ba: 2301 movs r3, #1
|
|
80062bc: e036 b.n 800632c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
80062be: 687b ldr r3, [r7, #4]
|
|
80062c0: 681b ldr r3, [r3, #0]
|
|
80062c2: f003 0304 and.w r3, r3, #4
|
|
80062c6: 2b00 cmp r3, #0
|
|
80062c8: d008 beq.n 80062dc <HAL_RCC_ClockConfig+0x194>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
80062ca: 4b1b ldr r3, [pc, #108] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80062cc: 689b ldr r3, [r3, #8]
|
|
80062ce: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
80062d2: 687b ldr r3, [r7, #4]
|
|
80062d4: 68db ldr r3, [r3, #12]
|
|
80062d6: 4918 ldr r1, [pc, #96] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80062d8: 4313 orrs r3, r2
|
|
80062da: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
80062dc: 687b ldr r3, [r7, #4]
|
|
80062de: 681b ldr r3, [r3, #0]
|
|
80062e0: f003 0308 and.w r3, r3, #8
|
|
80062e4: 2b00 cmp r3, #0
|
|
80062e6: d009 beq.n 80062fc <HAL_RCC_ClockConfig+0x1b4>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
80062e8: 4b13 ldr r3, [pc, #76] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80062ea: 689b ldr r3, [r3, #8]
|
|
80062ec: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
80062f0: 687b ldr r3, [r7, #4]
|
|
80062f2: 691b ldr r3, [r3, #16]
|
|
80062f4: 00db lsls r3, r3, #3
|
|
80062f6: 4910 ldr r1, [pc, #64] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80062f8: 4313 orrs r3, r2
|
|
80062fa: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
80062fc: f000 f824 bl 8006348 <HAL_RCC_GetSysClockFreq>
|
|
8006300: 4602 mov r2, r0
|
|
8006302: 4b0d ldr r3, [pc, #52] @ (8006338 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8006304: 689b ldr r3, [r3, #8]
|
|
8006306: 091b lsrs r3, r3, #4
|
|
8006308: f003 030f and.w r3, r3, #15
|
|
800630c: 490b ldr r1, [pc, #44] @ (800633c <HAL_RCC_ClockConfig+0x1f4>)
|
|
800630e: 5ccb ldrb r3, [r1, r3]
|
|
8006310: f003 031f and.w r3, r3, #31
|
|
8006314: fa22 f303 lsr.w r3, r2, r3
|
|
8006318: 4a09 ldr r2, [pc, #36] @ (8006340 <HAL_RCC_ClockConfig+0x1f8>)
|
|
800631a: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
800631c: 4b09 ldr r3, [pc, #36] @ (8006344 <HAL_RCC_ClockConfig+0x1fc>)
|
|
800631e: 681b ldr r3, [r3, #0]
|
|
8006320: 4618 mov r0, r3
|
|
8006322: f7fd faf9 bl 8003918 <HAL_InitTick>
|
|
8006326: 4603 mov r3, r0
|
|
8006328: 72fb strb r3, [r7, #11]
|
|
|
|
return status;
|
|
800632a: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
800632c: 4618 mov r0, r3
|
|
800632e: 3710 adds r7, #16
|
|
8006330: 46bd mov sp, r7
|
|
8006332: bd80 pop {r7, pc}
|
|
8006334: 40022000 .word 0x40022000
|
|
8006338: 40021000 .word 0x40021000
|
|
800633c: 08014744 .word 0x08014744
|
|
8006340: 200000c4 .word 0x200000c4
|
|
8006344: 200000c8 .word 0x200000c8
|
|
|
|
08006348 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8006348: b480 push {r7}
|
|
800634a: b089 sub sp, #36 @ 0x24
|
|
800634c: af00 add r7, sp, #0
|
|
uint32_t msirange = 0U, sysclockfreq = 0U;
|
|
800634e: 2300 movs r3, #0
|
|
8006350: 61fb str r3, [r7, #28]
|
|
8006352: 2300 movs r3, #0
|
|
8006354: 61bb str r3, [r7, #24]
|
|
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
|
|
uint32_t sysclk_source, pll_oscsource;
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8006356: 4b3e ldr r3, [pc, #248] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8006358: 689b ldr r3, [r3, #8]
|
|
800635a: f003 030c and.w r3, r3, #12
|
|
800635e: 613b str r3, [r7, #16]
|
|
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8006360: 4b3b ldr r3, [pc, #236] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8006362: 68db ldr r3, [r3, #12]
|
|
8006364: f003 0303 and.w r3, r3, #3
|
|
8006368: 60fb str r3, [r7, #12]
|
|
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
800636a: 693b ldr r3, [r7, #16]
|
|
800636c: 2b00 cmp r3, #0
|
|
800636e: d005 beq.n 800637c <HAL_RCC_GetSysClockFreq+0x34>
|
|
8006370: 693b ldr r3, [r7, #16]
|
|
8006372: 2b0c cmp r3, #12
|
|
8006374: d121 bne.n 80063ba <HAL_RCC_GetSysClockFreq+0x72>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
|
|
8006376: 68fb ldr r3, [r7, #12]
|
|
8006378: 2b01 cmp r3, #1
|
|
800637a: d11e bne.n 80063ba <HAL_RCC_GetSysClockFreq+0x72>
|
|
{
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
|
|
/* Get SYSCLK source */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
|
|
800637c: 4b34 ldr r3, [pc, #208] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
800637e: 681b ldr r3, [r3, #0]
|
|
8006380: f003 0308 and.w r3, r3, #8
|
|
8006384: 2b00 cmp r3, #0
|
|
8006386: d107 bne.n 8006398 <HAL_RCC_GetSysClockFreq+0x50>
|
|
{ /* MSISRANGE from RCC_CSR applies */
|
|
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
|
|
8006388: 4b31 ldr r3, [pc, #196] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
800638a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800638e: 0a1b lsrs r3, r3, #8
|
|
8006390: f003 030f and.w r3, r3, #15
|
|
8006394: 61fb str r3, [r7, #28]
|
|
8006396: e005 b.n 80063a4 <HAL_RCC_GetSysClockFreq+0x5c>
|
|
}
|
|
else
|
|
{ /* MSIRANGE from RCC_CR applies */
|
|
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
|
|
8006398: 4b2d ldr r3, [pc, #180] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
800639a: 681b ldr r3, [r3, #0]
|
|
800639c: 091b lsrs r3, r3, #4
|
|
800639e: f003 030f and.w r3, r3, #15
|
|
80063a2: 61fb str r3, [r7, #28]
|
|
}
|
|
/*MSI frequency range in HZ*/
|
|
msirange = MSIRangeTable[msirange];
|
|
80063a4: 4a2b ldr r2, [pc, #172] @ (8006454 <HAL_RCC_GetSysClockFreq+0x10c>)
|
|
80063a6: 69fb ldr r3, [r7, #28]
|
|
80063a8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80063ac: 61fb str r3, [r7, #28]
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
80063ae: 693b ldr r3, [r7, #16]
|
|
80063b0: 2b00 cmp r3, #0
|
|
80063b2: d10d bne.n 80063d0 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = msirange;
|
|
80063b4: 69fb ldr r3, [r7, #28]
|
|
80063b6: 61bb str r3, [r7, #24]
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
80063b8: e00a b.n 80063d0 <HAL_RCC_GetSysClockFreq+0x88>
|
|
}
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSI)
|
|
80063ba: 693b ldr r3, [r7, #16]
|
|
80063bc: 2b04 cmp r3, #4
|
|
80063be: d102 bne.n 80063c6 <HAL_RCC_GetSysClockFreq+0x7e>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
80063c0: 4b25 ldr r3, [pc, #148] @ (8006458 <HAL_RCC_GetSysClockFreq+0x110>)
|
|
80063c2: 61bb str r3, [r7, #24]
|
|
80063c4: e004 b.n 80063d0 <HAL_RCC_GetSysClockFreq+0x88>
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSE)
|
|
80063c6: 693b ldr r3, [r7, #16]
|
|
80063c8: 2b08 cmp r3, #8
|
|
80063ca: d101 bne.n 80063d0 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
80063cc: 4b23 ldr r3, [pc, #140] @ (800645c <HAL_RCC_GetSysClockFreq+0x114>)
|
|
80063ce: 61bb str r3, [r7, #24]
|
|
else
|
|
{
|
|
/* unexpected case: sysclockfreq at 0 */
|
|
}
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_PLL)
|
|
80063d0: 693b ldr r3, [r7, #16]
|
|
80063d2: 2b0c cmp r3, #12
|
|
80063d4: d134 bne.n 8006440 <HAL_RCC_GetSysClockFreq+0xf8>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
80063d6: 4b1e ldr r3, [pc, #120] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80063d8: 68db ldr r3, [r3, #12]
|
|
80063da: f003 0303 and.w r3, r3, #3
|
|
80063de: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
80063e0: 68bb ldr r3, [r7, #8]
|
|
80063e2: 2b02 cmp r3, #2
|
|
80063e4: d003 beq.n 80063ee <HAL_RCC_GetSysClockFreq+0xa6>
|
|
80063e6: 68bb ldr r3, [r7, #8]
|
|
80063e8: 2b03 cmp r3, #3
|
|
80063ea: d003 beq.n 80063f4 <HAL_RCC_GetSysClockFreq+0xac>
|
|
80063ec: e005 b.n 80063fa <HAL_RCC_GetSysClockFreq+0xb2>
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllvco = HSI_VALUE;
|
|
80063ee: 4b1a ldr r3, [pc, #104] @ (8006458 <HAL_RCC_GetSysClockFreq+0x110>)
|
|
80063f0: 617b str r3, [r7, #20]
|
|
break;
|
|
80063f2: e005 b.n 8006400 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = HSE_VALUE;
|
|
80063f4: 4b19 ldr r3, [pc, #100] @ (800645c <HAL_RCC_GetSysClockFreq+0x114>)
|
|
80063f6: 617b str r3, [r7, #20]
|
|
break;
|
|
80063f8: e002 b.n 8006400 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllvco = msirange;
|
|
80063fa: 69fb ldr r3, [r7, #28]
|
|
80063fc: 617b str r3, [r7, #20]
|
|
break;
|
|
80063fe: bf00 nop
|
|
}
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8006400: 4b13 ldr r3, [pc, #76] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8006402: 68db ldr r3, [r3, #12]
|
|
8006404: 091b lsrs r3, r3, #4
|
|
8006406: f003 0307 and.w r3, r3, #7
|
|
800640a: 3301 adds r3, #1
|
|
800640c: 607b str r3, [r7, #4]
|
|
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
|
|
800640e: 4b10 ldr r3, [pc, #64] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8006410: 68db ldr r3, [r3, #12]
|
|
8006412: 0a1b lsrs r3, r3, #8
|
|
8006414: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8006418: 697a ldr r2, [r7, #20]
|
|
800641a: fb03 f202 mul.w r2, r3, r2
|
|
800641e: 687b ldr r3, [r7, #4]
|
|
8006420: fbb2 f3f3 udiv r3, r2, r3
|
|
8006424: 617b str r3, [r7, #20]
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
8006426: 4b0a ldr r3, [pc, #40] @ (8006450 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8006428: 68db ldr r3, [r3, #12]
|
|
800642a: 0e5b lsrs r3, r3, #25
|
|
800642c: f003 0303 and.w r3, r3, #3
|
|
8006430: 3301 adds r3, #1
|
|
8006432: 005b lsls r3, r3, #1
|
|
8006434: 603b str r3, [r7, #0]
|
|
sysclockfreq = pllvco / pllr;
|
|
8006436: 697a ldr r2, [r7, #20]
|
|
8006438: 683b ldr r3, [r7, #0]
|
|
800643a: fbb2 f3f3 udiv r3, r2, r3
|
|
800643e: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
8006440: 69bb ldr r3, [r7, #24]
|
|
}
|
|
8006442: 4618 mov r0, r3
|
|
8006444: 3724 adds r7, #36 @ 0x24
|
|
8006446: 46bd mov sp, r7
|
|
8006448: f85d 7b04 ldr.w r7, [sp], #4
|
|
800644c: 4770 bx lr
|
|
800644e: bf00 nop
|
|
8006450: 40021000 .word 0x40021000
|
|
8006454: 0801475c .word 0x0801475c
|
|
8006458: 00f42400 .word 0x00f42400
|
|
800645c: 007a1200 .word 0x007a1200
|
|
|
|
08006460 <HAL_RCC_GetHCLKFreq>:
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8006460: b480 push {r7}
|
|
8006462: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8006464: 4b03 ldr r3, [pc, #12] @ (8006474 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
8006466: 681b ldr r3, [r3, #0]
|
|
}
|
|
8006468: 4618 mov r0, r3
|
|
800646a: 46bd mov sp, r7
|
|
800646c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006470: 4770 bx lr
|
|
8006472: bf00 nop
|
|
8006474: 200000c4 .word 0x200000c4
|
|
|
|
08006478 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8006478: b580 push {r7, lr}
|
|
800647a: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
|
800647c: f7ff fff0 bl 8006460 <HAL_RCC_GetHCLKFreq>
|
|
8006480: 4602 mov r2, r0
|
|
8006482: 4b06 ldr r3, [pc, #24] @ (800649c <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
8006484: 689b ldr r3, [r3, #8]
|
|
8006486: 0a1b lsrs r3, r3, #8
|
|
8006488: f003 0307 and.w r3, r3, #7
|
|
800648c: 4904 ldr r1, [pc, #16] @ (80064a0 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|
800648e: 5ccb ldrb r3, [r1, r3]
|
|
8006490: f003 031f and.w r3, r3, #31
|
|
8006494: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8006498: 4618 mov r0, r3
|
|
800649a: bd80 pop {r7, pc}
|
|
800649c: 40021000 .word 0x40021000
|
|
80064a0: 08014754 .word 0x08014754
|
|
|
|
080064a4 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80064a4: b580 push {r7, lr}
|
|
80064a6: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
|
80064a8: f7ff ffda bl 8006460 <HAL_RCC_GetHCLKFreq>
|
|
80064ac: 4602 mov r2, r0
|
|
80064ae: 4b06 ldr r3, [pc, #24] @ (80064c8 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80064b0: 689b ldr r3, [r3, #8]
|
|
80064b2: 0adb lsrs r3, r3, #11
|
|
80064b4: f003 0307 and.w r3, r3, #7
|
|
80064b8: 4904 ldr r1, [pc, #16] @ (80064cc <HAL_RCC_GetPCLK2Freq+0x28>)
|
|
80064ba: 5ccb ldrb r3, [r1, r3]
|
|
80064bc: f003 031f and.w r3, r3, #31
|
|
80064c0: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80064c4: 4618 mov r0, r3
|
|
80064c6: bd80 pop {r7, pc}
|
|
80064c8: 40021000 .word 0x40021000
|
|
80064cc: 08014754 .word 0x08014754
|
|
|
|
080064d0 <HAL_RCC_GetClockConfig>:
|
|
* will be configured.
|
|
* @param pFLatency Pointer on the Flash Latency.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
80064d0: b480 push {r7}
|
|
80064d2: b083 sub sp, #12
|
|
80064d4: af00 add r7, sp, #0
|
|
80064d6: 6078 str r0, [r7, #4]
|
|
80064d8: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(RCC_ClkInitStruct != (void *)NULL);
|
|
assert_param(pFLatency != (void *)NULL);
|
|
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
|
80064da: 687b ldr r3, [r7, #4]
|
|
80064dc: 220f movs r2, #15
|
|
80064de: 601a str r2, [r3, #0]
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
|
|
80064e0: 4b12 ldr r3, [pc, #72] @ (800652c <HAL_RCC_GetClockConfig+0x5c>)
|
|
80064e2: 689b ldr r3, [r3, #8]
|
|
80064e4: f003 0203 and.w r2, r3, #3
|
|
80064e8: 687b ldr r3, [r7, #4]
|
|
80064ea: 605a str r2, [r3, #4]
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
|
|
80064ec: 4b0f ldr r3, [pc, #60] @ (800652c <HAL_RCC_GetClockConfig+0x5c>)
|
|
80064ee: 689b ldr r3, [r3, #8]
|
|
80064f0: f003 02f0 and.w r2, r3, #240 @ 0xf0
|
|
80064f4: 687b ldr r3, [r7, #4]
|
|
80064f6: 609a str r2, [r3, #8]
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
|
|
80064f8: 4b0c ldr r3, [pc, #48] @ (800652c <HAL_RCC_GetClockConfig+0x5c>)
|
|
80064fa: 689b ldr r3, [r3, #8]
|
|
80064fc: f403 62e0 and.w r2, r3, #1792 @ 0x700
|
|
8006500: 687b ldr r3, [r7, #4]
|
|
8006502: 60da str r2, [r3, #12]
|
|
|
|
/* Get the APB2 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
|
|
8006504: 4b09 ldr r3, [pc, #36] @ (800652c <HAL_RCC_GetClockConfig+0x5c>)
|
|
8006506: 689b ldr r3, [r3, #8]
|
|
8006508: 08db lsrs r3, r3, #3
|
|
800650a: f403 62e0 and.w r2, r3, #1792 @ 0x700
|
|
800650e: 687b ldr r3, [r7, #4]
|
|
8006510: 611a str r2, [r3, #16]
|
|
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = __HAL_FLASH_GET_LATENCY();
|
|
8006512: 4b07 ldr r3, [pc, #28] @ (8006530 <HAL_RCC_GetClockConfig+0x60>)
|
|
8006514: 681b ldr r3, [r3, #0]
|
|
8006516: f003 0207 and.w r2, r3, #7
|
|
800651a: 683b ldr r3, [r7, #0]
|
|
800651c: 601a str r2, [r3, #0]
|
|
}
|
|
800651e: bf00 nop
|
|
8006520: 370c adds r7, #12
|
|
8006522: 46bd mov sp, r7
|
|
8006524: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006528: 4770 bx lr
|
|
800652a: bf00 nop
|
|
800652c: 40021000 .word 0x40021000
|
|
8006530: 40022000 .word 0x40022000
|
|
|
|
08006534 <RCC_SetFlashLatencyFromMSIRange>:
|
|
voltage range.
|
|
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
|
{
|
|
8006534: b580 push {r7, lr}
|
|
8006536: b086 sub sp, #24
|
|
8006538: af00 add r7, sp, #0
|
|
800653a: 6078 str r0, [r7, #4]
|
|
uint32_t vos;
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
800653c: 2300 movs r3, #0
|
|
800653e: 613b str r3, [r7, #16]
|
|
|
|
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
|
8006540: 4b2a ldr r3, [pc, #168] @ (80065ec <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8006542: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006544: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8006548: 2b00 cmp r3, #0
|
|
800654a: d003 beq.n 8006554 <RCC_SetFlashLatencyFromMSIRange+0x20>
|
|
{
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
800654c: f7ff f8f0 bl 8005730 <HAL_PWREx_GetVoltageRange>
|
|
8006550: 6178 str r0, [r7, #20]
|
|
8006552: e014 b.n 800657e <RCC_SetFlashLatencyFromMSIRange+0x4a>
|
|
}
|
|
else
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8006554: 4b25 ldr r3, [pc, #148] @ (80065ec <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8006556: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006558: 4a24 ldr r2, [pc, #144] @ (80065ec <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
800655a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800655e: 6593 str r3, [r2, #88] @ 0x58
|
|
8006560: 4b22 ldr r3, [pc, #136] @ (80065ec <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8006562: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006564: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8006568: 60fb str r3, [r7, #12]
|
|
800656a: 68fb ldr r3, [r7, #12]
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
800656c: f7ff f8e0 bl 8005730 <HAL_PWREx_GetVoltageRange>
|
|
8006570: 6178 str r0, [r7, #20]
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8006572: 4b1e ldr r3, [pc, #120] @ (80065ec <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8006574: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006576: 4a1d ldr r2, [pc, #116] @ (80065ec <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8006578: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800657c: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
|
|
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
800657e: 697b ldr r3, [r7, #20]
|
|
8006580: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8006584: d10b bne.n 800659e <RCC_SetFlashLatencyFromMSIRange+0x6a>
|
|
{
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
8006586: 687b ldr r3, [r7, #4]
|
|
8006588: 2b80 cmp r3, #128 @ 0x80
|
|
800658a: d919 bls.n 80065c0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
if(msirange > RCC_MSIRANGE_10)
|
|
800658c: 687b ldr r3, [r7, #4]
|
|
800658e: 2ba0 cmp r3, #160 @ 0xa0
|
|
8006590: d902 bls.n 8006598 <RCC_SetFlashLatencyFromMSIRange+0x64>
|
|
{
|
|
/* MSI 48Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
8006592: 2302 movs r3, #2
|
|
8006594: 613b str r3, [r7, #16]
|
|
8006596: e013 b.n 80065c0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else
|
|
{
|
|
/* MSI 24Mhz or 32Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
8006598: 2301 movs r3, #1
|
|
800659a: 613b str r3, [r7, #16]
|
|
800659c: e010 b.n 80065c0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
}
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
}
|
|
#else
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
800659e: 687b ldr r3, [r7, #4]
|
|
80065a0: 2b80 cmp r3, #128 @ 0x80
|
|
80065a2: d902 bls.n 80065aa <RCC_SetFlashLatencyFromMSIRange+0x76>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
latency = FLASH_LATENCY_3; /* 3WS */
|
|
80065a4: 2303 movs r3, #3
|
|
80065a6: 613b str r3, [r7, #16]
|
|
80065a8: e00a b.n 80065c0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else
|
|
{
|
|
if(msirange == RCC_MSIRANGE_8)
|
|
80065aa: 687b ldr r3, [r7, #4]
|
|
80065ac: 2b80 cmp r3, #128 @ 0x80
|
|
80065ae: d102 bne.n 80065b6 <RCC_SetFlashLatencyFromMSIRange+0x82>
|
|
{
|
|
/* MSI 16Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
80065b0: 2302 movs r3, #2
|
|
80065b2: 613b str r3, [r7, #16]
|
|
80065b4: e004 b.n 80065c0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else if(msirange == RCC_MSIRANGE_7)
|
|
80065b6: 687b ldr r3, [r7, #4]
|
|
80065b8: 2b70 cmp r3, #112 @ 0x70
|
|
80065ba: d101 bne.n 80065c0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
{
|
|
/* MSI 8Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
80065bc: 2301 movs r3, #1
|
|
80065be: 613b str r3, [r7, #16]
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
80065c0: 4b0b ldr r3, [pc, #44] @ (80065f0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
80065c2: 681b ldr r3, [r3, #0]
|
|
80065c4: f023 0207 bic.w r2, r3, #7
|
|
80065c8: 4909 ldr r1, [pc, #36] @ (80065f0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
80065ca: 693b ldr r3, [r7, #16]
|
|
80065cc: 4313 orrs r3, r2
|
|
80065ce: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != latency)
|
|
80065d0: 4b07 ldr r3, [pc, #28] @ (80065f0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
80065d2: 681b ldr r3, [r3, #0]
|
|
80065d4: f003 0307 and.w r3, r3, #7
|
|
80065d8: 693a ldr r2, [r7, #16]
|
|
80065da: 429a cmp r2, r3
|
|
80065dc: d001 beq.n 80065e2 <RCC_SetFlashLatencyFromMSIRange+0xae>
|
|
{
|
|
return HAL_ERROR;
|
|
80065de: 2301 movs r3, #1
|
|
80065e0: e000 b.n 80065e4 <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80065e2: 2300 movs r3, #0
|
|
}
|
|
80065e4: 4618 mov r0, r3
|
|
80065e6: 3718 adds r7, #24
|
|
80065e8: 46bd mov sp, r7
|
|
80065ea: bd80 pop {r7, pc}
|
|
80065ec: 40021000 .word 0x40021000
|
|
80065f0: 40022000 .word 0x40022000
|
|
|
|
080065f4 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
80065f4: b580 push {r7, lr}
|
|
80065f6: b086 sub sp, #24
|
|
80065f8: af00 add r7, sp, #0
|
|
80065fa: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister, tickstart; /* no init needed */
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
80065fc: 2300 movs r3, #0
|
|
80065fe: 74fb strb r3, [r7, #19]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
8006600: 2300 movs r3, #0
|
|
8006602: 74bb strb r3, [r7, #18]
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
#if defined(SAI1)
|
|
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
|
|
8006604: 687b ldr r3, [r7, #4]
|
|
8006606: 681b ldr r3, [r3, #0]
|
|
8006608: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
800660c: 2b00 cmp r3, #0
|
|
800660e: d041 beq.n 8006694 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai1ClockSelection)
|
|
8006610: 687b ldr r3, [r7, #4]
|
|
8006612: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8006614: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
8006618: d02a beq.n 8006670 <HAL_RCCEx_PeriphCLKConfig+0x7c>
|
|
800661a: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
800661e: d824 bhi.n 800666a <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
8006620: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
8006624: d008 beq.n 8006638 <HAL_RCCEx_PeriphCLKConfig+0x44>
|
|
8006626: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
800662a: d81e bhi.n 800666a <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
800662c: 2b00 cmp r3, #0
|
|
800662e: d00a beq.n 8006646 <HAL_RCCEx_PeriphCLKConfig+0x52>
|
|
8006630: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8006634: d010 beq.n 8006658 <HAL_RCCEx_PeriphCLKConfig+0x64>
|
|
8006636: e018 b.n 800666a <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
{
|
|
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
8006638: 4b86 ldr r3, [pc, #536] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800663a: 68db ldr r3, [r3, #12]
|
|
800663c: 4a85 ldr r2, [pc, #532] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800663e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8006642: 60d3 str r3, [r2, #12]
|
|
#else
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8006644: e015 b.n 8006672 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
8006646: 687b ldr r3, [r7, #4]
|
|
8006648: 3304 adds r3, #4
|
|
800664a: 2100 movs r1, #0
|
|
800664c: 4618 mov r0, r3
|
|
800664e: f000 facb bl 8006be8 <RCCEx_PLLSAI1_Config>
|
|
8006652: 4603 mov r3, r0
|
|
8006654: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8006656: e00c b.n 8006672 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
8006658: 687b ldr r3, [r7, #4]
|
|
800665a: 3320 adds r3, #32
|
|
800665c: 2100 movs r1, #0
|
|
800665e: 4618 mov r0, r3
|
|
8006660: f000 fbb6 bl 8006dd0 <RCCEx_PLLSAI2_Config>
|
|
8006664: 4603 mov r3, r0
|
|
8006666: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8006668: e003 b.n 8006672 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
800666a: 2301 movs r3, #1
|
|
800666c: 74fb strb r3, [r7, #19]
|
|
break;
|
|
800666e: e000 b.n 8006672 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
break;
|
|
8006670: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8006672: 7cfb ldrb r3, [r7, #19]
|
|
8006674: 2b00 cmp r3, #0
|
|
8006676: d10b bne.n 8006690 <HAL_RCCEx_PeriphCLKConfig+0x9c>
|
|
{
|
|
/* Set the source of SAI1 clock*/
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8006678: 4b76 ldr r3, [pc, #472] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800667a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800667e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
8006682: 687b ldr r3, [r7, #4]
|
|
8006684: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8006686: 4973 ldr r1, [pc, #460] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8006688: 4313 orrs r3, r2
|
|
800668a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
800668e: e001 b.n 8006694 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8006690: 7cfb ldrb r3, [r7, #19]
|
|
8006692: 74bb strb r3, [r7, #18]
|
|
#endif /* SAI1 */
|
|
|
|
#if defined(SAI2)
|
|
|
|
/*-------------------------- SAI2 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
|
|
8006694: 687b ldr r3, [r7, #4]
|
|
8006696: 681b ldr r3, [r3, #0]
|
|
8006698: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
800669c: 2b00 cmp r3, #0
|
|
800669e: d041 beq.n 8006724 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai2ClockSelection)
|
|
80066a0: 687b ldr r3, [r7, #4]
|
|
80066a2: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
80066a4: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
|
|
80066a8: d02a beq.n 8006700 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
80066aa: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
|
|
80066ae: d824 bhi.n 80066fa <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
80066b0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
80066b4: d008 beq.n 80066c8 <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
|
80066b6: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
80066ba: d81e bhi.n 80066fa <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
80066bc: 2b00 cmp r3, #0
|
|
80066be: d00a beq.n 80066d6 <HAL_RCCEx_PeriphCLKConfig+0xe2>
|
|
80066c0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80066c4: d010 beq.n 80066e8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
80066c6: e018 b.n 80066fa <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
{
|
|
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
80066c8: 4b62 ldr r3, [pc, #392] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80066ca: 68db ldr r3, [r3, #12]
|
|
80066cc: 4a61 ldr r2, [pc, #388] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80066ce: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80066d2: 60d3 str r3, [r2, #12]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
80066d4: e015 b.n 8006702 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
80066d6: 687b ldr r3, [r7, #4]
|
|
80066d8: 3304 adds r3, #4
|
|
80066da: 2100 movs r1, #0
|
|
80066dc: 4618 mov r0, r3
|
|
80066de: f000 fa83 bl 8006be8 <RCCEx_PLLSAI1_Config>
|
|
80066e2: 4603 mov r3, r0
|
|
80066e4: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
80066e6: e00c b.n 8006702 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
80066e8: 687b ldr r3, [r7, #4]
|
|
80066ea: 3320 adds r3, #32
|
|
80066ec: 2100 movs r1, #0
|
|
80066ee: 4618 mov r0, r3
|
|
80066f0: f000 fb6e bl 8006dd0 <RCCEx_PLLSAI2_Config>
|
|
80066f4: 4603 mov r3, r0
|
|
80066f6: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
80066f8: e003 b.n 8006702 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
80066fa: 2301 movs r3, #1
|
|
80066fc: 74fb strb r3, [r7, #19]
|
|
break;
|
|
80066fe: e000 b.n 8006702 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
break;
|
|
8006700: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8006702: 7cfb ldrb r3, [r7, #19]
|
|
8006704: 2b00 cmp r3, #0
|
|
8006706: d10b bne.n 8006720 <HAL_RCCEx_PeriphCLKConfig+0x12c>
|
|
{
|
|
/* Set the source of SAI2 clock*/
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
8006708: 4b52 ldr r3, [pc, #328] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800670a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800670e: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
|
|
8006712: 687b ldr r3, [r7, #4]
|
|
8006714: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8006716: 494f ldr r1, [pc, #316] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8006718: 4313 orrs r3, r2
|
|
800671a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
800671e: e001 b.n 8006724 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8006720: 7cfb ldrb r3, [r7, #19]
|
|
8006722: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
#endif /* SAI2 */
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
8006724: 687b ldr r3, [r7, #4]
|
|
8006726: 681b ldr r3, [r3, #0]
|
|
8006728: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800672c: 2b00 cmp r3, #0
|
|
800672e: f000 80a0 beq.w 8006872 <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8006732: 2300 movs r3, #0
|
|
8006734: 747b strb r3, [r7, #17]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
8006736: 4b47 ldr r3, [pc, #284] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8006738: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800673a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800673e: 2b00 cmp r3, #0
|
|
8006740: d101 bne.n 8006746 <HAL_RCCEx_PeriphCLKConfig+0x152>
|
|
8006742: 2301 movs r3, #1
|
|
8006744: e000 b.n 8006748 <HAL_RCCEx_PeriphCLKConfig+0x154>
|
|
8006746: 2300 movs r3, #0
|
|
8006748: 2b00 cmp r3, #0
|
|
800674a: d00d beq.n 8006768 <HAL_RCCEx_PeriphCLKConfig+0x174>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800674c: 4b41 ldr r3, [pc, #260] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800674e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006750: 4a40 ldr r2, [pc, #256] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8006752: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006756: 6593 str r3, [r2, #88] @ 0x58
|
|
8006758: 4b3e ldr r3, [pc, #248] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800675a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800675c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8006760: 60bb str r3, [r7, #8]
|
|
8006762: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8006764: 2301 movs r3, #1
|
|
8006766: 747b strb r3, [r7, #17]
|
|
}
|
|
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8006768: 4b3b ldr r3, [pc, #236] @ (8006858 <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
800676a: 681b ldr r3, [r3, #0]
|
|
800676c: 4a3a ldr r2, [pc, #232] @ (8006858 <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
800676e: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8006772: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8006774: f7fd fac4 bl 8003d00 <HAL_GetTick>
|
|
8006778: 60f8 str r0, [r7, #12]
|
|
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
800677a: e009 b.n 8006790 <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800677c: f7fd fac0 bl 8003d00 <HAL_GetTick>
|
|
8006780: 4602 mov r2, r0
|
|
8006782: 68fb ldr r3, [r7, #12]
|
|
8006784: 1ad3 subs r3, r2, r3
|
|
8006786: 2b02 cmp r3, #2
|
|
8006788: d902 bls.n 8006790 <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
800678a: 2303 movs r3, #3
|
|
800678c: 74fb strb r3, [r7, #19]
|
|
break;
|
|
800678e: e005 b.n 800679c <HAL_RCCEx_PeriphCLKConfig+0x1a8>
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
8006790: 4b31 ldr r3, [pc, #196] @ (8006858 <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
8006792: 681b ldr r3, [r3, #0]
|
|
8006794: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8006798: 2b00 cmp r3, #0
|
|
800679a: d0ef beq.n 800677c <HAL_RCCEx_PeriphCLKConfig+0x188>
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
800679c: 7cfb ldrb r3, [r7, #19]
|
|
800679e: 2b00 cmp r3, #0
|
|
80067a0: d15c bne.n 800685c <HAL_RCCEx_PeriphCLKConfig+0x268>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
80067a2: 4b2c ldr r3, [pc, #176] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80067a4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80067a8: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80067ac: 617b str r3, [r7, #20]
|
|
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
80067ae: 697b ldr r3, [r7, #20]
|
|
80067b0: 2b00 cmp r3, #0
|
|
80067b2: d01f beq.n 80067f4 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
|
80067b4: 687b ldr r3, [r7, #4]
|
|
80067b6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80067ba: 697a ldr r2, [r7, #20]
|
|
80067bc: 429a cmp r2, r3
|
|
80067be: d019 beq.n 80067f4 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
80067c0: 4b24 ldr r3, [pc, #144] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80067c2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80067c6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80067ca: 617b str r3, [r7, #20]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
80067cc: 4b21 ldr r3, [pc, #132] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80067ce: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80067d2: 4a20 ldr r2, [pc, #128] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80067d4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80067d8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
80067dc: 4b1d ldr r3, [pc, #116] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80067de: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80067e2: 4a1c ldr r2, [pc, #112] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80067e4: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80067e8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
80067ec: 4a19 ldr r2, [pc, #100] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80067ee: 697b ldr r3, [r7, #20]
|
|
80067f0: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
80067f4: 697b ldr r3, [r7, #20]
|
|
80067f6: f003 0301 and.w r3, r3, #1
|
|
80067fa: 2b00 cmp r3, #0
|
|
80067fc: d016 beq.n 800682c <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80067fe: f7fd fa7f bl 8003d00 <HAL_GetTick>
|
|
8006802: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8006804: e00b b.n 800681e <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8006806: f7fd fa7b bl 8003d00 <HAL_GetTick>
|
|
800680a: 4602 mov r2, r0
|
|
800680c: 68fb ldr r3, [r7, #12]
|
|
800680e: 1ad3 subs r3, r2, r3
|
|
8006810: f241 3288 movw r2, #5000 @ 0x1388
|
|
8006814: 4293 cmp r3, r2
|
|
8006816: d902 bls.n 800681e <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8006818: 2303 movs r3, #3
|
|
800681a: 74fb strb r3, [r7, #19]
|
|
break;
|
|
800681c: e006 b.n 800682c <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
800681e: 4b0d ldr r3, [pc, #52] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8006820: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006824: f003 0302 and.w r3, r3, #2
|
|
8006828: 2b00 cmp r3, #0
|
|
800682a: d0ec beq.n 8006806 <HAL_RCCEx_PeriphCLKConfig+0x212>
|
|
}
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
800682c: 7cfb ldrb r3, [r7, #19]
|
|
800682e: 2b00 cmp r3, #0
|
|
8006830: d10c bne.n 800684c <HAL_RCCEx_PeriphCLKConfig+0x258>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8006832: 4b08 ldr r3, [pc, #32] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8006834: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006838: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
800683c: 687b ldr r3, [r7, #4]
|
|
800683e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8006842: 4904 ldr r1, [pc, #16] @ (8006854 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8006844: 4313 orrs r3, r2
|
|
8006846: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
800684a: e009 b.n 8006860 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800684c: 7cfb ldrb r3, [r7, #19]
|
|
800684e: 74bb strb r3, [r7, #18]
|
|
8006850: e006 b.n 8006860 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
8006852: bf00 nop
|
|
8006854: 40021000 .word 0x40021000
|
|
8006858: 40007000 .word 0x40007000
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800685c: 7cfb ldrb r3, [r7, #19]
|
|
800685e: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
8006860: 7c7b ldrb r3, [r7, #17]
|
|
8006862: 2b01 cmp r3, #1
|
|
8006864: d105 bne.n 8006872 <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8006866: 4b9e ldr r3, [pc, #632] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006868: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800686a: 4a9d ldr r2, [pc, #628] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800686c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8006870: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
8006872: 687b ldr r3, [r7, #4]
|
|
8006874: 681b ldr r3, [r3, #0]
|
|
8006876: f003 0301 and.w r3, r3, #1
|
|
800687a: 2b00 cmp r3, #0
|
|
800687c: d00a beq.n 8006894 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
800687e: 4b98 ldr r3, [pc, #608] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006880: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006884: f023 0203 bic.w r2, r3, #3
|
|
8006888: 687b ldr r3, [r7, #4]
|
|
800688a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800688c: 4994 ldr r1, [pc, #592] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800688e: 4313 orrs r3, r2
|
|
8006890: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
8006894: 687b ldr r3, [r7, #4]
|
|
8006896: 681b ldr r3, [r3, #0]
|
|
8006898: f003 0302 and.w r3, r3, #2
|
|
800689c: 2b00 cmp r3, #0
|
|
800689e: d00a beq.n 80068b6 <HAL_RCCEx_PeriphCLKConfig+0x2c2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
80068a0: 4b8f ldr r3, [pc, #572] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80068a2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80068a6: f023 020c bic.w r2, r3, #12
|
|
80068aa: 687b ldr r3, [r7, #4]
|
|
80068ac: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80068ae: 498c ldr r1, [pc, #560] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80068b0: 4313 orrs r3, r2
|
|
80068b2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(USART3)
|
|
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
80068b6: 687b ldr r3, [r7, #4]
|
|
80068b8: 681b ldr r3, [r3, #0]
|
|
80068ba: f003 0304 and.w r3, r3, #4
|
|
80068be: 2b00 cmp r3, #0
|
|
80068c0: d00a beq.n 80068d8 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
80068c2: 4b87 ldr r3, [pc, #540] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80068c4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80068c8: f023 0230 bic.w r2, r3, #48 @ 0x30
|
|
80068cc: 687b ldr r3, [r7, #4]
|
|
80068ce: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80068d0: 4983 ldr r1, [pc, #524] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80068d2: 4313 orrs r3, r2
|
|
80068d4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* USART3 */
|
|
|
|
#if defined(UART4)
|
|
|
|
/*-------------------------- UART4 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
80068d8: 687b ldr r3, [r7, #4]
|
|
80068da: 681b ldr r3, [r3, #0]
|
|
80068dc: f003 0308 and.w r3, r3, #8
|
|
80068e0: 2b00 cmp r3, #0
|
|
80068e2: d00a beq.n 80068fa <HAL_RCCEx_PeriphCLKConfig+0x306>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
80068e4: 4b7e ldr r3, [pc, #504] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80068e6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80068ea: f023 02c0 bic.w r2, r3, #192 @ 0xc0
|
|
80068ee: 687b ldr r3, [r7, #4]
|
|
80068f0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80068f2: 497b ldr r1, [pc, #492] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80068f4: 4313 orrs r3, r2
|
|
80068f6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* UART4 */
|
|
|
|
#if defined(UART5)
|
|
|
|
/*-------------------------- UART5 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
|
80068fa: 687b ldr r3, [r7, #4]
|
|
80068fc: 681b ldr r3, [r3, #0]
|
|
80068fe: f003 0310 and.w r3, r3, #16
|
|
8006902: 2b00 cmp r3, #0
|
|
8006904: d00a beq.n 800691c <HAL_RCCEx_PeriphCLKConfig+0x328>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
|
|
|
/* Configure the UART5 clock source */
|
|
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
|
8006906: 4b76 ldr r3, [pc, #472] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006908: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800690c: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8006910: 687b ldr r3, [r7, #4]
|
|
8006912: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006914: 4972 ldr r1, [pc, #456] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006916: 4313 orrs r3, r2
|
|
8006918: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* UART5 */
|
|
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
800691c: 687b ldr r3, [r7, #4]
|
|
800691e: 681b ldr r3, [r3, #0]
|
|
8006920: f003 0320 and.w r3, r3, #32
|
|
8006924: 2b00 cmp r3, #0
|
|
8006926: d00a beq.n 800693e <HAL_RCCEx_PeriphCLKConfig+0x34a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUART1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
8006928: 4b6d ldr r3, [pc, #436] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800692a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800692e: f423 6240 bic.w r2, r3, #3072 @ 0xc00
|
|
8006932: 687b ldr r3, [r7, #4]
|
|
8006934: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8006936: 496a ldr r1, [pc, #424] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006938: 4313 orrs r3, r2
|
|
800693a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
800693e: 687b ldr r3, [r7, #4]
|
|
8006940: 681b ldr r3, [r3, #0]
|
|
8006942: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8006946: 2b00 cmp r3, #0
|
|
8006948: d00a beq.n 8006960 <HAL_RCCEx_PeriphCLKConfig+0x36c>
|
|
{
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
800694a: 4b65 ldr r3, [pc, #404] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800694c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006950: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
|
|
8006954: 687b ldr r3, [r7, #4]
|
|
8006956: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8006958: 4961 ldr r1, [pc, #388] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800695a: 4313 orrs r3, r2
|
|
800695c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
8006960: 687b ldr r3, [r7, #4]
|
|
8006962: 681b ldr r3, [r3, #0]
|
|
8006964: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8006968: 2b00 cmp r3, #0
|
|
800696a: d00a beq.n 8006982 <HAL_RCCEx_PeriphCLKConfig+0x38e>
|
|
{
|
|
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
800696c: 4b5c ldr r3, [pc, #368] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800696e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006972: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8006976: 687b ldr r3, [r7, #4]
|
|
8006978: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800697a: 4959 ldr r1, [pc, #356] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800697c: 4313 orrs r3, r2
|
|
800697e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
8006982: 687b ldr r3, [r7, #4]
|
|
8006984: 681b ldr r3, [r3, #0]
|
|
8006986: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800698a: 2b00 cmp r3, #0
|
|
800698c: d00a beq.n 80069a4 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
800698e: 4b54 ldr r3, [pc, #336] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006990: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006994: f423 5240 bic.w r2, r3, #12288 @ 0x3000
|
|
8006998: 687b ldr r3, [r7, #4]
|
|
800699a: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800699c: 4950 ldr r1, [pc, #320] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800699e: 4313 orrs r3, r2
|
|
80069a0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(I2C2)
|
|
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
80069a4: 687b ldr r3, [r7, #4]
|
|
80069a6: 681b ldr r3, [r3, #0]
|
|
80069a8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80069ac: 2b00 cmp r3, #0
|
|
80069ae: d00a beq.n 80069c6 <HAL_RCCEx_PeriphCLKConfig+0x3d2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
80069b0: 4b4b ldr r3, [pc, #300] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80069b2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80069b6: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
80069ba: 687b ldr r3, [r7, #4]
|
|
80069bc: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80069be: 4948 ldr r1, [pc, #288] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80069c0: 4313 orrs r3, r2
|
|
80069c2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* I2C2 */
|
|
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
80069c6: 687b ldr r3, [r7, #4]
|
|
80069c8: 681b ldr r3, [r3, #0]
|
|
80069ca: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80069ce: 2b00 cmp r3, #0
|
|
80069d0: d00a beq.n 80069e8 <HAL_RCCEx_PeriphCLKConfig+0x3f4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
80069d2: 4b43 ldr r3, [pc, #268] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80069d4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80069d8: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
80069dc: 687b ldr r3, [r7, #4]
|
|
80069de: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80069e0: 493f ldr r1, [pc, #252] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80069e2: 4313 orrs r3, r2
|
|
80069e4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* I2C4 */
|
|
|
|
#if defined(USB_OTG_FS) || defined(USB)
|
|
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|
80069e8: 687b ldr r3, [r7, #4]
|
|
80069ea: 681b ldr r3, [r3, #0]
|
|
80069ec: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
80069f0: 2b00 cmp r3, #0
|
|
80069f2: d028 beq.n 8006a46 <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
80069f4: 4b3a ldr r3, [pc, #232] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80069f6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80069fa: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
80069fe: 687b ldr r3, [r7, #4]
|
|
8006a00: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8006a02: 4937 ldr r1, [pc, #220] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006a04: 4313 orrs r3, r2
|
|
8006a06: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
|
8006a0a: 687b ldr r3, [r7, #4]
|
|
8006a0c: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8006a0e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8006a12: d106 bne.n 8006a22 <HAL_RCCEx_PeriphCLKConfig+0x42e>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8006a14: 4b32 ldr r3, [pc, #200] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006a16: 68db ldr r3, [r3, #12]
|
|
8006a18: 4a31 ldr r2, [pc, #196] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006a1a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8006a1e: 60d3 str r3, [r2, #12]
|
|
8006a20: e011 b.n 8006a46 <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
}
|
|
else
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
|
|
8006a22: 687b ldr r3, [r7, #4]
|
|
8006a24: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8006a26: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8006a2a: d10c bne.n 8006a46 <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8006a2c: 687b ldr r3, [r7, #4]
|
|
8006a2e: 3304 adds r3, #4
|
|
8006a30: 2101 movs r1, #1
|
|
8006a32: 4618 mov r0, r3
|
|
8006a34: f000 f8d8 bl 8006be8 <RCCEx_PLLSAI1_Config>
|
|
8006a38: 4603 mov r3, r0
|
|
8006a3a: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8006a3c: 7cfb ldrb r3, [r7, #19]
|
|
8006a3e: 2b00 cmp r3, #0
|
|
8006a40: d001 beq.n 8006a46 <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8006a42: 7cfb ldrb r3, [r7, #19]
|
|
8006a44: 74bb strb r3, [r7, #18]
|
|
#endif /* USB_OTG_FS || USB */
|
|
|
|
#if defined(SDMMC1)
|
|
|
|
/*-------------------------- SDMMC1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
|
|
8006a46: 687b ldr r3, [r7, #4]
|
|
8006a48: 681b ldr r3, [r3, #0]
|
|
8006a4a: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8006a4e: 2b00 cmp r3, #0
|
|
8006a50: d028 beq.n 8006aa4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
|
|
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
|
|
8006a52: 4b23 ldr r3, [pc, #140] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006a54: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006a58: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8006a5c: 687b ldr r3, [r7, #4]
|
|
8006a5e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8006a60: 491f ldr r1, [pc, #124] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006a62: 4313 orrs r3, r2
|
|
8006a64: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
|
|
8006a68: 687b ldr r3, [r7, #4]
|
|
8006a6a: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8006a6c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8006a70: d106 bne.n 8006a80 <HAL_RCCEx_PeriphCLKConfig+0x48c>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8006a72: 4b1b ldr r3, [pc, #108] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006a74: 68db ldr r3, [r3, #12]
|
|
8006a76: 4a1a ldr r2, [pc, #104] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006a78: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8006a7c: 60d3 str r3, [r2, #12]
|
|
8006a7e: e011 b.n 8006aa4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* Enable PLLSAI3CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
}
|
|
#endif
|
|
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
|
|
8006a80: 687b ldr r3, [r7, #4]
|
|
8006a82: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8006a84: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8006a88: d10c bne.n 8006aa4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8006a8a: 687b ldr r3, [r7, #4]
|
|
8006a8c: 3304 adds r3, #4
|
|
8006a8e: 2101 movs r1, #1
|
|
8006a90: 4618 mov r0, r3
|
|
8006a92: f000 f8a9 bl 8006be8 <RCCEx_PLLSAI1_Config>
|
|
8006a96: 4603 mov r3, r0
|
|
8006a98: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8006a9a: 7cfb ldrb r3, [r7, #19]
|
|
8006a9c: 2b00 cmp r3, #0
|
|
8006a9e: d001 beq.n 8006aa4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8006aa0: 7cfb ldrb r3, [r7, #19]
|
|
8006aa2: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
#endif /* SDMMC1 */
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
8006aa4: 687b ldr r3, [r7, #4]
|
|
8006aa6: 681b ldr r3, [r3, #0]
|
|
8006aa8: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8006aac: 2b00 cmp r3, #0
|
|
8006aae: d02b beq.n 8006b08 <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
8006ab0: 4b0b ldr r3, [pc, #44] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006ab2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006ab6: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8006aba: 687b ldr r3, [r7, #4]
|
|
8006abc: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8006abe: 4908 ldr r1, [pc, #32] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006ac0: 4313 orrs r3, r2
|
|
8006ac2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
8006ac6: 687b ldr r3, [r7, #4]
|
|
8006ac8: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8006aca: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8006ace: d109 bne.n 8006ae4 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8006ad0: 4b03 ldr r3, [pc, #12] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006ad2: 68db ldr r3, [r3, #12]
|
|
8006ad4: 4a02 ldr r2, [pc, #8] @ (8006ae0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8006ad6: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8006ada: 60d3 str r3, [r2, #12]
|
|
8006adc: e014 b.n 8006b08 <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
8006ade: bf00 nop
|
|
8006ae0: 40021000 .word 0x40021000
|
|
}
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
|
|
8006ae4: 687b ldr r3, [r7, #4]
|
|
8006ae6: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8006ae8: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8006aec: d10c bne.n 8006b08 <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8006aee: 687b ldr r3, [r7, #4]
|
|
8006af0: 3304 adds r3, #4
|
|
8006af2: 2101 movs r1, #1
|
|
8006af4: 4618 mov r0, r3
|
|
8006af6: f000 f877 bl 8006be8 <RCCEx_PLLSAI1_Config>
|
|
8006afa: 4603 mov r3, r0
|
|
8006afc: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8006afe: 7cfb ldrb r3, [r7, #19]
|
|
8006b00: 2b00 cmp r3, #0
|
|
8006b02: d001 beq.n 8006b08 <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8006b04: 7cfb ldrb r3, [r7, #19]
|
|
8006b06: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
#if !defined(STM32L412xx) && !defined(STM32L422xx)
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8006b08: 687b ldr r3, [r7, #4]
|
|
8006b0a: 681b ldr r3, [r3, #0]
|
|
8006b0c: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8006b10: 2b00 cmp r3, #0
|
|
8006b12: d02f beq.n 8006b74 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
8006b14: 4b2b ldr r3, [pc, #172] @ (8006bc4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8006b16: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006b1a: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
|
|
8006b1e: 687b ldr r3, [r7, #4]
|
|
8006b20: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8006b22: 4928 ldr r1, [pc, #160] @ (8006bc4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8006b24: 4313 orrs r3, r2
|
|
8006b26: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
|
|
8006b2a: 687b ldr r3, [r7, #4]
|
|
8006b2c: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8006b2e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8006b32: d10d bne.n 8006b50 <HAL_RCCEx_PeriphCLKConfig+0x55c>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
|
|
8006b34: 687b ldr r3, [r7, #4]
|
|
8006b36: 3304 adds r3, #4
|
|
8006b38: 2102 movs r1, #2
|
|
8006b3a: 4618 mov r0, r3
|
|
8006b3c: f000 f854 bl 8006be8 <RCCEx_PLLSAI1_Config>
|
|
8006b40: 4603 mov r3, r0
|
|
8006b42: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8006b44: 7cfb ldrb r3, [r7, #19]
|
|
8006b46: 2b00 cmp r3, #0
|
|
8006b48: d014 beq.n 8006b74 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8006b4a: 7cfb ldrb r3, [r7, #19]
|
|
8006b4c: 74bb strb r3, [r7, #18]
|
|
8006b4e: e011 b.n 8006b74 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
}
|
|
#endif /* RCC_PLLSAI1_SUPPORT */
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
|
|
|
|
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
|
|
8006b50: 687b ldr r3, [r7, #4]
|
|
8006b52: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8006b54: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8006b58: d10c bne.n 8006b74 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
|
|
8006b5a: 687b ldr r3, [r7, #4]
|
|
8006b5c: 3320 adds r3, #32
|
|
8006b5e: 2102 movs r1, #2
|
|
8006b60: 4618 mov r0, r3
|
|
8006b62: f000 f935 bl 8006dd0 <RCCEx_PLLSAI2_Config>
|
|
8006b66: 4603 mov r3, r0
|
|
8006b68: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8006b6a: 7cfb ldrb r3, [r7, #19]
|
|
8006b6c: 2b00 cmp r3, #0
|
|
8006b6e: d001 beq.n 8006b74 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8006b70: 7cfb ldrb r3, [r7, #19]
|
|
8006b72: 74bb strb r3, [r7, #18]
|
|
#endif /* !STM32L412xx && !STM32L422xx */
|
|
|
|
#if defined(SWPMI1)
|
|
|
|
/*-------------------------- SWPMI1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
|
|
8006b74: 687b ldr r3, [r7, #4]
|
|
8006b76: 681b ldr r3, [r3, #0]
|
|
8006b78: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8006b7c: 2b00 cmp r3, #0
|
|
8006b7e: d00a beq.n 8006b96 <HAL_RCCEx_PeriphCLKConfig+0x5a2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
|
|
|
|
/* Configure the SWPMI1 clock source */
|
|
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
|
|
8006b80: 4b10 ldr r3, [pc, #64] @ (8006bc4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8006b82: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006b86: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000
|
|
8006b8a: 687b ldr r3, [r7, #4]
|
|
8006b8c: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8006b8e: 490d ldr r1, [pc, #52] @ (8006bc4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8006b90: 4313 orrs r3, r2
|
|
8006b92: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* SWPMI1 */
|
|
|
|
#if defined(DFSDM1_Filter0)
|
|
|
|
/*-------------------------- DFSDM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
|
|
8006b96: 687b ldr r3, [r7, #4]
|
|
8006b98: 681b ldr r3, [r3, #0]
|
|
8006b9a: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8006b9e: 2b00 cmp r3, #0
|
|
8006ba0: d00b beq.n 8006bba <HAL_RCCEx_PeriphCLKConfig+0x5c6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
|
|
|
|
/* Configure the DFSDM1 interface clock source */
|
|
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
|
|
8006ba2: 4b08 ldr r3, [pc, #32] @ (8006bc4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8006ba4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006ba8: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
|
|
8006bac: 687b ldr r3, [r7, #4]
|
|
8006bae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8006bb2: 4904 ldr r1, [pc, #16] @ (8006bc4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8006bb4: 4313 orrs r3, r2
|
|
8006bb6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
}
|
|
|
|
#endif /* OCTOSPI1 || OCTOSPI2 */
|
|
|
|
return status;
|
|
8006bba: 7cbb ldrb r3, [r7, #18]
|
|
}
|
|
8006bbc: 4618 mov r0, r3
|
|
8006bbe: 3718 adds r7, #24
|
|
8006bc0: 46bd mov sp, r7
|
|
8006bc2: bd80 pop {r7, pc}
|
|
8006bc4: 40021000 .word 0x40021000
|
|
|
|
08006bc8 <HAL_RCCEx_EnableMSIPLLMode>:
|
|
* @note Prior to enable the PLL-mode of the MSI for automatic hardware
|
|
* calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableMSIPLLMode(void)
|
|
{
|
|
8006bc8: b480 push {r7}
|
|
8006bca: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
|
|
8006bcc: 4b05 ldr r3, [pc, #20] @ (8006be4 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
|
|
8006bce: 681b ldr r3, [r3, #0]
|
|
8006bd0: 4a04 ldr r2, [pc, #16] @ (8006be4 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
|
|
8006bd2: f043 0304 orr.w r3, r3, #4
|
|
8006bd6: 6013 str r3, [r2, #0]
|
|
}
|
|
8006bd8: bf00 nop
|
|
8006bda: 46bd mov sp, r7
|
|
8006bdc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006be0: 4770 bx lr
|
|
8006be2: bf00 nop
|
|
8006be4: 40021000 .word 0x40021000
|
|
|
|
08006be8 <RCCEx_PLLSAI1_Config>:
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
|
|
{
|
|
8006be8: b580 push {r7, lr}
|
|
8006bea: b084 sub sp, #16
|
|
8006bec: af00 add r7, sp, #0
|
|
8006bee: 6078 str r0, [r7, #4]
|
|
8006bf0: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8006bf2: 2300 movs r3, #0
|
|
8006bf4: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
|
|
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
|
|
|
|
/* Check that PLLSAI1 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
8006bf6: 4b75 ldr r3, [pc, #468] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006bf8: 68db ldr r3, [r3, #12]
|
|
8006bfa: f003 0303 and.w r3, r3, #3
|
|
8006bfe: 2b00 cmp r3, #0
|
|
8006c00: d018 beq.n 8006c34 <RCCEx_PLLSAI1_Config+0x4c>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
|
|
8006c02: 4b72 ldr r3, [pc, #456] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006c04: 68db ldr r3, [r3, #12]
|
|
8006c06: f003 0203 and.w r2, r3, #3
|
|
8006c0a: 687b ldr r3, [r7, #4]
|
|
8006c0c: 681b ldr r3, [r3, #0]
|
|
8006c0e: 429a cmp r2, r3
|
|
8006c10: d10d bne.n 8006c2e <RCCEx_PLLSAI1_Config+0x46>
|
|
||
|
|
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
|
|
8006c12: 687b ldr r3, [r7, #4]
|
|
8006c14: 681b ldr r3, [r3, #0]
|
|
||
|
|
8006c16: 2b00 cmp r3, #0
|
|
8006c18: d009 beq.n 8006c2e <RCCEx_PLLSAI1_Config+0x46>
|
|
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
|
|
8006c1a: 4b6c ldr r3, [pc, #432] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006c1c: 68db ldr r3, [r3, #12]
|
|
8006c1e: 091b lsrs r3, r3, #4
|
|
8006c20: f003 0307 and.w r3, r3, #7
|
|
8006c24: 1c5a adds r2, r3, #1
|
|
8006c26: 687b ldr r3, [r7, #4]
|
|
8006c28: 685b ldr r3, [r3, #4]
|
|
||
|
|
8006c2a: 429a cmp r2, r3
|
|
8006c2c: d047 beq.n 8006cbe <RCCEx_PLLSAI1_Config+0xd6>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
8006c2e: 2301 movs r3, #1
|
|
8006c30: 73fb strb r3, [r7, #15]
|
|
8006c32: e044 b.n 8006cbe <RCCEx_PLLSAI1_Config+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI1 clock source availability */
|
|
switch(PllSai1->PLLSAI1Source)
|
|
8006c34: 687b ldr r3, [r7, #4]
|
|
8006c36: 681b ldr r3, [r3, #0]
|
|
8006c38: 2b03 cmp r3, #3
|
|
8006c3a: d018 beq.n 8006c6e <RCCEx_PLLSAI1_Config+0x86>
|
|
8006c3c: 2b03 cmp r3, #3
|
|
8006c3e: d825 bhi.n 8006c8c <RCCEx_PLLSAI1_Config+0xa4>
|
|
8006c40: 2b01 cmp r3, #1
|
|
8006c42: d002 beq.n 8006c4a <RCCEx_PLLSAI1_Config+0x62>
|
|
8006c44: 2b02 cmp r3, #2
|
|
8006c46: d009 beq.n 8006c5c <RCCEx_PLLSAI1_Config+0x74>
|
|
8006c48: e020 b.n 8006c8c <RCCEx_PLLSAI1_Config+0xa4>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
8006c4a: 4b60 ldr r3, [pc, #384] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006c4c: 681b ldr r3, [r3, #0]
|
|
8006c4e: f003 0302 and.w r3, r3, #2
|
|
8006c52: 2b00 cmp r3, #0
|
|
8006c54: d11d bne.n 8006c92 <RCCEx_PLLSAI1_Config+0xaa>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006c56: 2301 movs r3, #1
|
|
8006c58: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8006c5a: e01a b.n 8006c92 <RCCEx_PLLSAI1_Config+0xaa>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8006c5c: 4b5b ldr r3, [pc, #364] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006c5e: 681b ldr r3, [r3, #0]
|
|
8006c60: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8006c64: 2b00 cmp r3, #0
|
|
8006c66: d116 bne.n 8006c96 <RCCEx_PLLSAI1_Config+0xae>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006c68: 2301 movs r3, #1
|
|
8006c6a: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8006c6c: e013 b.n 8006c96 <RCCEx_PLLSAI1_Config+0xae>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8006c6e: 4b57 ldr r3, [pc, #348] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006c70: 681b ldr r3, [r3, #0]
|
|
8006c72: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8006c76: 2b00 cmp r3, #0
|
|
8006c78: d10f bne.n 8006c9a <RCCEx_PLLSAI1_Config+0xb2>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
8006c7a: 4b54 ldr r3, [pc, #336] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006c7c: 681b ldr r3, [r3, #0]
|
|
8006c7e: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8006c82: 2b00 cmp r3, #0
|
|
8006c84: d109 bne.n 8006c9a <RCCEx_PLLSAI1_Config+0xb2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006c86: 2301 movs r3, #1
|
|
8006c88: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8006c8a: e006 b.n 8006c9a <RCCEx_PLLSAI1_Config+0xb2>
|
|
default:
|
|
status = HAL_ERROR;
|
|
8006c8c: 2301 movs r3, #1
|
|
8006c8e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006c90: e004 b.n 8006c9c <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8006c92: bf00 nop
|
|
8006c94: e002 b.n 8006c9c <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8006c96: bf00 nop
|
|
8006c98: e000 b.n 8006c9c <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8006c9a: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006c9c: 7bfb ldrb r3, [r7, #15]
|
|
8006c9e: 2b00 cmp r3, #0
|
|
8006ca0: d10d bne.n 8006cbe <RCCEx_PLLSAI1_Config+0xd6>
|
|
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI1 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
|
|
#else
|
|
/* Set PLLSAI1 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
8006ca2: 4b4a ldr r3, [pc, #296] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006ca4: 68db ldr r3, [r3, #12]
|
|
8006ca6: f023 0273 bic.w r2, r3, #115 @ 0x73
|
|
8006caa: 687b ldr r3, [r7, #4]
|
|
8006cac: 6819 ldr r1, [r3, #0]
|
|
8006cae: 687b ldr r3, [r7, #4]
|
|
8006cb0: 685b ldr r3, [r3, #4]
|
|
8006cb2: 3b01 subs r3, #1
|
|
8006cb4: 011b lsls r3, r3, #4
|
|
8006cb6: 430b orrs r3, r1
|
|
8006cb8: 4944 ldr r1, [pc, #272] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006cba: 4313 orrs r3, r2
|
|
8006cbc: 60cb str r3, [r1, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006cbe: 7bfb ldrb r3, [r7, #15]
|
|
8006cc0: 2b00 cmp r3, #0
|
|
8006cc2: d17d bne.n 8006dc0 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
/* Disable the PLLSAI1 */
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
8006cc4: 4b41 ldr r3, [pc, #260] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006cc6: 681b ldr r3, [r3, #0]
|
|
8006cc8: 4a40 ldr r2, [pc, #256] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006cca: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8006cce: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8006cd0: f7fd f816 bl 8003d00 <HAL_GetTick>
|
|
8006cd4: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
8006cd6: e009 b.n 8006cec <RCCEx_PLLSAI1_Config+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
8006cd8: f7fd f812 bl 8003d00 <HAL_GetTick>
|
|
8006cdc: 4602 mov r2, r0
|
|
8006cde: 68bb ldr r3, [r7, #8]
|
|
8006ce0: 1ad3 subs r3, r2, r3
|
|
8006ce2: 2b02 cmp r3, #2
|
|
8006ce4: d902 bls.n 8006cec <RCCEx_PLLSAI1_Config+0x104>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8006ce6: 2303 movs r3, #3
|
|
8006ce8: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006cea: e005 b.n 8006cf8 <RCCEx_PLLSAI1_Config+0x110>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
8006cec: 4b37 ldr r3, [pc, #220] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006cee: 681b ldr r3, [r3, #0]
|
|
8006cf0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8006cf4: 2b00 cmp r3, #0
|
|
8006cf6: d1ef bne.n 8006cd8 <RCCEx_PLLSAI1_Config+0xf0>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006cf8: 7bfb ldrb r3, [r7, #15]
|
|
8006cfa: 2b00 cmp r3, #0
|
|
8006cfc: d160 bne.n 8006dc0 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
8006cfe: 683b ldr r3, [r7, #0]
|
|
8006d00: 2b00 cmp r3, #0
|
|
8006d02: d111 bne.n 8006d28 <RCCEx_PLLSAI1_Config+0x140>
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8006d04: 4b31 ldr r3, [pc, #196] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006d06: 691b ldr r3, [r3, #16]
|
|
8006d08: f423 331f bic.w r3, r3, #162816 @ 0x27c00
|
|
8006d0c: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8006d10: 687a ldr r2, [r7, #4]
|
|
8006d12: 6892 ldr r2, [r2, #8]
|
|
8006d14: 0211 lsls r1, r2, #8
|
|
8006d16: 687a ldr r2, [r7, #4]
|
|
8006d18: 68d2 ldr r2, [r2, #12]
|
|
8006d1a: 0912 lsrs r2, r2, #4
|
|
8006d1c: 0452 lsls r2, r2, #17
|
|
8006d1e: 430a orrs r2, r1
|
|
8006d20: 492a ldr r1, [pc, #168] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006d22: 4313 orrs r3, r2
|
|
8006d24: 610b str r3, [r1, #16]
|
|
8006d26: e027 b.n 8006d78 <RCCEx_PLLSAI1_Config+0x190>
|
|
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
|
|
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
else if(Divider == DIVIDER_Q_UPDATE)
|
|
8006d28: 683b ldr r3, [r7, #0]
|
|
8006d2a: 2b01 cmp r3, #1
|
|
8006d2c: d112 bne.n 8006d54 <RCCEx_PLLSAI1_Config+0x16c>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8006d2e: 4b27 ldr r3, [pc, #156] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006d30: 691b ldr r3, [r3, #16]
|
|
8006d32: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000
|
|
8006d36: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8006d3a: 687a ldr r2, [r7, #4]
|
|
8006d3c: 6892 ldr r2, [r2, #8]
|
|
8006d3e: 0211 lsls r1, r2, #8
|
|
8006d40: 687a ldr r2, [r7, #4]
|
|
8006d42: 6912 ldr r2, [r2, #16]
|
|
8006d44: 0852 lsrs r2, r2, #1
|
|
8006d46: 3a01 subs r2, #1
|
|
8006d48: 0552 lsls r2, r2, #21
|
|
8006d4a: 430a orrs r2, r1
|
|
8006d4c: 491f ldr r1, [pc, #124] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006d4e: 4313 orrs r3, r2
|
|
8006d50: 610b str r3, [r1, #16]
|
|
8006d52: e011 b.n 8006d78 <RCCEx_PLLSAI1_Config+0x190>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8006d54: 4b1d ldr r3, [pc, #116] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006d56: 691b ldr r3, [r3, #16]
|
|
8006d58: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
|
|
8006d5c: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8006d60: 687a ldr r2, [r7, #4]
|
|
8006d62: 6892 ldr r2, [r2, #8]
|
|
8006d64: 0211 lsls r1, r2, #8
|
|
8006d66: 687a ldr r2, [r7, #4]
|
|
8006d68: 6952 ldr r2, [r2, #20]
|
|
8006d6a: 0852 lsrs r2, r2, #1
|
|
8006d6c: 3a01 subs r2, #1
|
|
8006d6e: 0652 lsls r2, r2, #25
|
|
8006d70: 430a orrs r2, r1
|
|
8006d72: 4916 ldr r1, [pc, #88] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006d74: 4313 orrs r3, r2
|
|
8006d76: 610b str r3, [r1, #16]
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
8006d78: 4b14 ldr r3, [pc, #80] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006d7a: 681b ldr r3, [r3, #0]
|
|
8006d7c: 4a13 ldr r2, [pc, #76] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006d7e: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
8006d82: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8006d84: f7fc ffbc bl 8003d00 <HAL_GetTick>
|
|
8006d88: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
8006d8a: e009 b.n 8006da0 <RCCEx_PLLSAI1_Config+0x1b8>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
8006d8c: f7fc ffb8 bl 8003d00 <HAL_GetTick>
|
|
8006d90: 4602 mov r2, r0
|
|
8006d92: 68bb ldr r3, [r7, #8]
|
|
8006d94: 1ad3 subs r3, r2, r3
|
|
8006d96: 2b02 cmp r3, #2
|
|
8006d98: d902 bls.n 8006da0 <RCCEx_PLLSAI1_Config+0x1b8>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8006d9a: 2303 movs r3, #3
|
|
8006d9c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006d9e: e005 b.n 8006dac <RCCEx_PLLSAI1_Config+0x1c4>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
8006da0: 4b0a ldr r3, [pc, #40] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006da2: 681b ldr r3, [r3, #0]
|
|
8006da4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8006da8: 2b00 cmp r3, #0
|
|
8006daa: d0ef beq.n 8006d8c <RCCEx_PLLSAI1_Config+0x1a4>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006dac: 7bfb ldrb r3, [r7, #15]
|
|
8006dae: 2b00 cmp r3, #0
|
|
8006db0: d106 bne.n 8006dc0 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
|
|
8006db2: 4b06 ldr r3, [pc, #24] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006db4: 691a ldr r2, [r3, #16]
|
|
8006db6: 687b ldr r3, [r7, #4]
|
|
8006db8: 699b ldr r3, [r3, #24]
|
|
8006dba: 4904 ldr r1, [pc, #16] @ (8006dcc <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006dbc: 4313 orrs r3, r2
|
|
8006dbe: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8006dc0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006dc2: 4618 mov r0, r3
|
|
8006dc4: 3710 adds r7, #16
|
|
8006dc6: 46bd mov sp, r7
|
|
8006dc8: bd80 pop {r7, pc}
|
|
8006dca: bf00 nop
|
|
8006dcc: 40021000 .word 0x40021000
|
|
|
|
08006dd0 <RCCEx_PLLSAI2_Config>:
|
|
* @note PLLSAI2 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
|
|
{
|
|
8006dd0: b580 push {r7, lr}
|
|
8006dd2: b084 sub sp, #16
|
|
8006dd4: af00 add r7, sp, #0
|
|
8006dd6: 6078 str r0, [r7, #4]
|
|
8006dd8: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8006dda: 2300 movs r3, #0
|
|
8006ddc: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
|
|
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
|
|
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
|
|
|
|
/* Check that PLLSAI2 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
8006dde: 4b6a ldr r3, [pc, #424] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006de0: 68db ldr r3, [r3, #12]
|
|
8006de2: f003 0303 and.w r3, r3, #3
|
|
8006de6: 2b00 cmp r3, #0
|
|
8006de8: d018 beq.n 8006e1c <RCCEx_PLLSAI2_Config+0x4c>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
|
|
8006dea: 4b67 ldr r3, [pc, #412] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006dec: 68db ldr r3, [r3, #12]
|
|
8006dee: f003 0203 and.w r2, r3, #3
|
|
8006df2: 687b ldr r3, [r7, #4]
|
|
8006df4: 681b ldr r3, [r3, #0]
|
|
8006df6: 429a cmp r2, r3
|
|
8006df8: d10d bne.n 8006e16 <RCCEx_PLLSAI2_Config+0x46>
|
|
||
|
|
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
|
|
8006dfa: 687b ldr r3, [r7, #4]
|
|
8006dfc: 681b ldr r3, [r3, #0]
|
|
||
|
|
8006dfe: 2b00 cmp r3, #0
|
|
8006e00: d009 beq.n 8006e16 <RCCEx_PLLSAI2_Config+0x46>
|
|
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
|
|
8006e02: 4b61 ldr r3, [pc, #388] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006e04: 68db ldr r3, [r3, #12]
|
|
8006e06: 091b lsrs r3, r3, #4
|
|
8006e08: f003 0307 and.w r3, r3, #7
|
|
8006e0c: 1c5a adds r2, r3, #1
|
|
8006e0e: 687b ldr r3, [r7, #4]
|
|
8006e10: 685b ldr r3, [r3, #4]
|
|
||
|
|
8006e12: 429a cmp r2, r3
|
|
8006e14: d047 beq.n 8006ea6 <RCCEx_PLLSAI2_Config+0xd6>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
8006e16: 2301 movs r3, #1
|
|
8006e18: 73fb strb r3, [r7, #15]
|
|
8006e1a: e044 b.n 8006ea6 <RCCEx_PLLSAI2_Config+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI2 clock source availability */
|
|
switch(PllSai2->PLLSAI2Source)
|
|
8006e1c: 687b ldr r3, [r7, #4]
|
|
8006e1e: 681b ldr r3, [r3, #0]
|
|
8006e20: 2b03 cmp r3, #3
|
|
8006e22: d018 beq.n 8006e56 <RCCEx_PLLSAI2_Config+0x86>
|
|
8006e24: 2b03 cmp r3, #3
|
|
8006e26: d825 bhi.n 8006e74 <RCCEx_PLLSAI2_Config+0xa4>
|
|
8006e28: 2b01 cmp r3, #1
|
|
8006e2a: d002 beq.n 8006e32 <RCCEx_PLLSAI2_Config+0x62>
|
|
8006e2c: 2b02 cmp r3, #2
|
|
8006e2e: d009 beq.n 8006e44 <RCCEx_PLLSAI2_Config+0x74>
|
|
8006e30: e020 b.n 8006e74 <RCCEx_PLLSAI2_Config+0xa4>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
8006e32: 4b55 ldr r3, [pc, #340] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006e34: 681b ldr r3, [r3, #0]
|
|
8006e36: f003 0302 and.w r3, r3, #2
|
|
8006e3a: 2b00 cmp r3, #0
|
|
8006e3c: d11d bne.n 8006e7a <RCCEx_PLLSAI2_Config+0xaa>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006e3e: 2301 movs r3, #1
|
|
8006e40: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8006e42: e01a b.n 8006e7a <RCCEx_PLLSAI2_Config+0xaa>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8006e44: 4b50 ldr r3, [pc, #320] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006e46: 681b ldr r3, [r3, #0]
|
|
8006e48: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8006e4c: 2b00 cmp r3, #0
|
|
8006e4e: d116 bne.n 8006e7e <RCCEx_PLLSAI2_Config+0xae>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006e50: 2301 movs r3, #1
|
|
8006e52: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8006e54: e013 b.n 8006e7e <RCCEx_PLLSAI2_Config+0xae>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8006e56: 4b4c ldr r3, [pc, #304] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006e58: 681b ldr r3, [r3, #0]
|
|
8006e5a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8006e5e: 2b00 cmp r3, #0
|
|
8006e60: d10f bne.n 8006e82 <RCCEx_PLLSAI2_Config+0xb2>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
8006e62: 4b49 ldr r3, [pc, #292] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006e64: 681b ldr r3, [r3, #0]
|
|
8006e66: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8006e6a: 2b00 cmp r3, #0
|
|
8006e6c: d109 bne.n 8006e82 <RCCEx_PLLSAI2_Config+0xb2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006e6e: 2301 movs r3, #1
|
|
8006e70: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8006e72: e006 b.n 8006e82 <RCCEx_PLLSAI2_Config+0xb2>
|
|
default:
|
|
status = HAL_ERROR;
|
|
8006e74: 2301 movs r3, #1
|
|
8006e76: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006e78: e004 b.n 8006e84 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8006e7a: bf00 nop
|
|
8006e7c: e002 b.n 8006e84 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8006e7e: bf00 nop
|
|
8006e80: e000 b.n 8006e84 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8006e82: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006e84: 7bfb ldrb r3, [r7, #15]
|
|
8006e86: 2b00 cmp r3, #0
|
|
8006e88: d10d bne.n 8006ea6 <RCCEx_PLLSAI2_Config+0xd6>
|
|
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI2 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
|
|
#else
|
|
/* Set PLLSAI2 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
8006e8a: 4b3f ldr r3, [pc, #252] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006e8c: 68db ldr r3, [r3, #12]
|
|
8006e8e: f023 0273 bic.w r2, r3, #115 @ 0x73
|
|
8006e92: 687b ldr r3, [r7, #4]
|
|
8006e94: 6819 ldr r1, [r3, #0]
|
|
8006e96: 687b ldr r3, [r7, #4]
|
|
8006e98: 685b ldr r3, [r3, #4]
|
|
8006e9a: 3b01 subs r3, #1
|
|
8006e9c: 011b lsls r3, r3, #4
|
|
8006e9e: 430b orrs r3, r1
|
|
8006ea0: 4939 ldr r1, [pc, #228] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006ea2: 4313 orrs r3, r2
|
|
8006ea4: 60cb str r3, [r1, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006ea6: 7bfb ldrb r3, [r7, #15]
|
|
8006ea8: 2b00 cmp r3, #0
|
|
8006eaa: d167 bne.n 8006f7c <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
/* Disable the PLLSAI2 */
|
|
__HAL_RCC_PLLSAI2_DISABLE();
|
|
8006eac: 4b36 ldr r3, [pc, #216] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006eae: 681b ldr r3, [r3, #0]
|
|
8006eb0: 4a35 ldr r2, [pc, #212] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006eb2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8006eb6: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8006eb8: f7fc ff22 bl 8003d00 <HAL_GetTick>
|
|
8006ebc: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
8006ebe: e009 b.n 8006ed4 <RCCEx_PLLSAI2_Config+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
8006ec0: f7fc ff1e bl 8003d00 <HAL_GetTick>
|
|
8006ec4: 4602 mov r2, r0
|
|
8006ec6: 68bb ldr r3, [r7, #8]
|
|
8006ec8: 1ad3 subs r3, r2, r3
|
|
8006eca: 2b02 cmp r3, #2
|
|
8006ecc: d902 bls.n 8006ed4 <RCCEx_PLLSAI2_Config+0x104>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8006ece: 2303 movs r3, #3
|
|
8006ed0: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006ed2: e005 b.n 8006ee0 <RCCEx_PLLSAI2_Config+0x110>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
8006ed4: 4b2c ldr r3, [pc, #176] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006ed6: 681b ldr r3, [r3, #0]
|
|
8006ed8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8006edc: 2b00 cmp r3, #0
|
|
8006ede: d1ef bne.n 8006ec0 <RCCEx_PLLSAI2_Config+0xf0>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006ee0: 7bfb ldrb r3, [r7, #15]
|
|
8006ee2: 2b00 cmp r3, #0
|
|
8006ee4: d14a bne.n 8006f7c <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
8006ee6: 683b ldr r3, [r7, #0]
|
|
8006ee8: 2b00 cmp r3, #0
|
|
8006eea: d111 bne.n 8006f10 <RCCEx_PLLSAI2_Config+0x140>
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
8006eec: 4b26 ldr r3, [pc, #152] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006eee: 695b ldr r3, [r3, #20]
|
|
8006ef0: f423 331f bic.w r3, r3, #162816 @ 0x27c00
|
|
8006ef4: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8006ef8: 687a ldr r2, [r7, #4]
|
|
8006efa: 6892 ldr r2, [r2, #8]
|
|
8006efc: 0211 lsls r1, r2, #8
|
|
8006efe: 687a ldr r2, [r7, #4]
|
|
8006f00: 68d2 ldr r2, [r2, #12]
|
|
8006f02: 0912 lsrs r2, r2, #4
|
|
8006f04: 0452 lsls r2, r2, #17
|
|
8006f06: 430a orrs r2, r1
|
|
8006f08: 491f ldr r1, [pc, #124] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006f0a: 4313 orrs r3, r2
|
|
8006f0c: 614b str r3, [r1, #20]
|
|
8006f0e: e011 b.n 8006f34 <RCCEx_PLLSAI2_Config+0x164>
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
|
|
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
8006f10: 4b1d ldr r3, [pc, #116] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006f12: 695b ldr r3, [r3, #20]
|
|
8006f14: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
|
|
8006f18: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8006f1c: 687a ldr r2, [r7, #4]
|
|
8006f1e: 6892 ldr r2, [r2, #8]
|
|
8006f20: 0211 lsls r1, r2, #8
|
|
8006f22: 687a ldr r2, [r7, #4]
|
|
8006f24: 6912 ldr r2, [r2, #16]
|
|
8006f26: 0852 lsrs r2, r2, #1
|
|
8006f28: 3a01 subs r2, #1
|
|
8006f2a: 0652 lsls r2, r2, #25
|
|
8006f2c: 430a orrs r2, r1
|
|
8006f2e: 4916 ldr r1, [pc, #88] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006f30: 4313 orrs r3, r2
|
|
8006f32: 614b str r3, [r1, #20]
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
|
|
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
|
|
__HAL_RCC_PLLSAI2_ENABLE();
|
|
8006f34: 4b14 ldr r3, [pc, #80] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006f36: 681b ldr r3, [r3, #0]
|
|
8006f38: 4a13 ldr r2, [pc, #76] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006f3a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006f3e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8006f40: f7fc fede bl 8003d00 <HAL_GetTick>
|
|
8006f44: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
8006f46: e009 b.n 8006f5c <RCCEx_PLLSAI2_Config+0x18c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
8006f48: f7fc feda bl 8003d00 <HAL_GetTick>
|
|
8006f4c: 4602 mov r2, r0
|
|
8006f4e: 68bb ldr r3, [r7, #8]
|
|
8006f50: 1ad3 subs r3, r2, r3
|
|
8006f52: 2b02 cmp r3, #2
|
|
8006f54: d902 bls.n 8006f5c <RCCEx_PLLSAI2_Config+0x18c>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8006f56: 2303 movs r3, #3
|
|
8006f58: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006f5a: e005 b.n 8006f68 <RCCEx_PLLSAI2_Config+0x198>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
8006f5c: 4b0a ldr r3, [pc, #40] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006f5e: 681b ldr r3, [r3, #0]
|
|
8006f60: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8006f64: 2b00 cmp r3, #0
|
|
8006f66: d0ef beq.n 8006f48 <RCCEx_PLLSAI2_Config+0x178>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006f68: 7bfb ldrb r3, [r7, #15]
|
|
8006f6a: 2b00 cmp r3, #0
|
|
8006f6c: d106 bne.n 8006f7c <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
/* Configure the PLLSAI2 Clock output(s) */
|
|
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
|
|
8006f6e: 4b06 ldr r3, [pc, #24] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006f70: 695a ldr r2, [r3, #20]
|
|
8006f72: 687b ldr r3, [r7, #4]
|
|
8006f74: 695b ldr r3, [r3, #20]
|
|
8006f76: 4904 ldr r1, [pc, #16] @ (8006f88 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006f78: 4313 orrs r3, r2
|
|
8006f7a: 614b str r3, [r1, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8006f7c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006f7e: 4618 mov r0, r3
|
|
8006f80: 3710 adds r7, #16
|
|
8006f82: 46bd mov sp, r7
|
|
8006f84: bd80 pop {r7, pc}
|
|
8006f86: bf00 nop
|
|
8006f88: 40021000 .word 0x40021000
|
|
|
|
08006f8c <HAL_SPI_Init>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8006f8c: b580 push {r7, lr}
|
|
8006f8e: b084 sub sp, #16
|
|
8006f90: af00 add r7, sp, #0
|
|
8006f92: 6078 str r0, [r7, #4]
|
|
uint32_t frxth;
|
|
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
8006f94: 687b ldr r3, [r7, #4]
|
|
8006f96: 2b00 cmp r3, #0
|
|
8006f98: d101 bne.n 8006f9e <HAL_SPI_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8006f9a: 2301 movs r3, #1
|
|
8006f9c: e095 b.n 80070ca <HAL_SPI_Init+0x13e>
|
|
assert_param(IS_SPI_NSS(hspi->Init.NSS));
|
|
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
|
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
|
|
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
|
|
8006f9e: 687b ldr r3, [r7, #4]
|
|
8006fa0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006fa2: 2b00 cmp r3, #0
|
|
8006fa4: d108 bne.n 8006fb8 <HAL_SPI_Init+0x2c>
|
|
{
|
|
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
|
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
|
|
|
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
|
8006fa6: 687b ldr r3, [r7, #4]
|
|
8006fa8: 685b ldr r3, [r3, #4]
|
|
8006faa: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8006fae: d009 beq.n 8006fc4 <HAL_SPI_Init+0x38>
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
}
|
|
else
|
|
{
|
|
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
|
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
8006fb0: 687b ldr r3, [r7, #4]
|
|
8006fb2: 2200 movs r2, #0
|
|
8006fb4: 61da str r2, [r3, #28]
|
|
8006fb6: e005 b.n 8006fc4 <HAL_SPI_Init+0x38>
|
|
else
|
|
{
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
|
|
/* Force polarity and phase to TI protocaol requirements */
|
|
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
8006fb8: 687b ldr r3, [r7, #4]
|
|
8006fba: 2200 movs r2, #0
|
|
8006fbc: 611a str r2, [r3, #16]
|
|
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8006fbe: 687b ldr r3, [r7, #4]
|
|
8006fc0: 2200 movs r2, #0
|
|
8006fc2: 615a str r2, [r3, #20]
|
|
{
|
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
|
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
|
|
}
|
|
#else
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8006fc4: 687b ldr r3, [r7, #4]
|
|
8006fc6: 2200 movs r2, #0
|
|
8006fc8: 629a str r2, [r3, #40] @ 0x28
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->State == HAL_SPI_STATE_RESET)
|
|
8006fca: 687b ldr r3, [r7, #4]
|
|
8006fcc: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
8006fd0: b2db uxtb r3, r3
|
|
8006fd2: 2b00 cmp r3, #0
|
|
8006fd4: d106 bne.n 8006fe4 <HAL_SPI_Init+0x58>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hspi->Lock = HAL_UNLOCKED;
|
|
8006fd6: 687b ldr r3, [r7, #4]
|
|
8006fd8: 2200 movs r2, #0
|
|
8006fda: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hspi->MspInitCallback(hspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspInit(hspi);
|
|
8006fde: 6878 ldr r0, [r7, #4]
|
|
8006fe0: f7fc faf0 bl 80035c4 <HAL_SPI_MspInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
8006fe4: 687b ldr r3, [r7, #4]
|
|
8006fe6: 2202 movs r2, #2
|
|
8006fe8: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Disable the selected SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8006fec: 687b ldr r3, [r7, #4]
|
|
8006fee: 681b ldr r3, [r3, #0]
|
|
8006ff0: 681a ldr r2, [r3, #0]
|
|
8006ff2: 687b ldr r3, [r7, #4]
|
|
8006ff4: 681b ldr r3, [r3, #0]
|
|
8006ff6: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8006ffa: 601a str r2, [r3, #0]
|
|
|
|
/* Align by default the rs fifo threshold on the data size */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
8006ffc: 687b ldr r3, [r7, #4]
|
|
8006ffe: 68db ldr r3, [r3, #12]
|
|
8007000: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8007004: d902 bls.n 800700c <HAL_SPI_Init+0x80>
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_HF;
|
|
8007006: 2300 movs r3, #0
|
|
8007008: 60fb str r3, [r7, #12]
|
|
800700a: e002 b.n 8007012 <HAL_SPI_Init+0x86>
|
|
}
|
|
else
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_QF;
|
|
800700c: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8007010: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* CRC calculation is valid only for 16Bit and 8 Bit */
|
|
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
|
|
8007012: 687b ldr r3, [r7, #4]
|
|
8007014: 68db ldr r3, [r3, #12]
|
|
8007016: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
|
|
800701a: d007 beq.n 800702c <HAL_SPI_Init+0xa0>
|
|
800701c: 687b ldr r3, [r7, #4]
|
|
800701e: 68db ldr r3, [r3, #12]
|
|
8007020: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8007024: d002 beq.n 800702c <HAL_SPI_Init+0xa0>
|
|
{
|
|
/* CRC must be disabled */
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8007026: 687b ldr r3, [r7, #4]
|
|
8007028: 2200 movs r2, #0
|
|
800702a: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
|
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
|
|
Communication speed, First bit and CRC calculation state */
|
|
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
|
800702c: 687b ldr r3, [r7, #4]
|
|
800702e: 685b ldr r3, [r3, #4]
|
|
8007030: f403 7282 and.w r2, r3, #260 @ 0x104
|
|
8007034: 687b ldr r3, [r7, #4]
|
|
8007036: 689b ldr r3, [r3, #8]
|
|
8007038: f403 4304 and.w r3, r3, #33792 @ 0x8400
|
|
800703c: 431a orrs r2, r3
|
|
800703e: 687b ldr r3, [r7, #4]
|
|
8007040: 691b ldr r3, [r3, #16]
|
|
8007042: f003 0302 and.w r3, r3, #2
|
|
8007046: 431a orrs r2, r3
|
|
8007048: 687b ldr r3, [r7, #4]
|
|
800704a: 695b ldr r3, [r3, #20]
|
|
800704c: f003 0301 and.w r3, r3, #1
|
|
8007050: 431a orrs r2, r3
|
|
8007052: 687b ldr r3, [r7, #4]
|
|
8007054: 699b ldr r3, [r3, #24]
|
|
8007056: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800705a: 431a orrs r2, r3
|
|
800705c: 687b ldr r3, [r7, #4]
|
|
800705e: 69db ldr r3, [r3, #28]
|
|
8007060: f003 0338 and.w r3, r3, #56 @ 0x38
|
|
8007064: 431a orrs r2, r3
|
|
8007066: 687b ldr r3, [r7, #4]
|
|
8007068: 6a1b ldr r3, [r3, #32]
|
|
800706a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800706e: ea42 0103 orr.w r1, r2, r3
|
|
8007072: 687b ldr r3, [r7, #4]
|
|
8007074: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8007076: f403 5200 and.w r2, r3, #8192 @ 0x2000
|
|
800707a: 687b ldr r3, [r7, #4]
|
|
800707c: 681b ldr r3, [r3, #0]
|
|
800707e: 430a orrs r2, r1
|
|
8007080: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
|
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
|
|
8007082: 687b ldr r3, [r7, #4]
|
|
8007084: 699b ldr r3, [r3, #24]
|
|
8007086: 0c1b lsrs r3, r3, #16
|
|
8007088: f003 0204 and.w r2, r3, #4
|
|
800708c: 687b ldr r3, [r7, #4]
|
|
800708e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007090: f003 0310 and.w r3, r3, #16
|
|
8007094: 431a orrs r2, r3
|
|
8007096: 687b ldr r3, [r7, #4]
|
|
8007098: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800709a: f003 0308 and.w r3, r3, #8
|
|
800709e: 431a orrs r2, r3
|
|
80070a0: 687b ldr r3, [r7, #4]
|
|
80070a2: 68db ldr r3, [r3, #12]
|
|
80070a4: f403 6370 and.w r3, r3, #3840 @ 0xf00
|
|
80070a8: ea42 0103 orr.w r1, r2, r3
|
|
80070ac: 68fb ldr r3, [r7, #12]
|
|
80070ae: f403 5280 and.w r2, r3, #4096 @ 0x1000
|
|
80070b2: 687b ldr r3, [r7, #4]
|
|
80070b4: 681b ldr r3, [r3, #0]
|
|
80070b6: 430a orrs r2, r1
|
|
80070b8: 605a str r2, [r3, #4]
|
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
80070ba: 687b ldr r3, [r7, #4]
|
|
80070bc: 2200 movs r2, #0
|
|
80070be: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80070c0: 687b ldr r3, [r7, #4]
|
|
80070c2: 2201 movs r2, #1
|
|
80070c4: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
return HAL_OK;
|
|
80070c8: 2300 movs r3, #0
|
|
}
|
|
80070ca: 4618 mov r0, r3
|
|
80070cc: 3710 adds r7, #16
|
|
80070ce: 46bd mov sp, r7
|
|
80070d0: bd80 pop {r7, pc}
|
|
|
|
080070d2 <HAL_SPI_DeInit>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
|
|
{
|
|
80070d2: b580 push {r7, lr}
|
|
80070d4: b082 sub sp, #8
|
|
80070d6: af00 add r7, sp, #0
|
|
80070d8: 6078 str r0, [r7, #4]
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
80070da: 687b ldr r3, [r7, #4]
|
|
80070dc: 2b00 cmp r3, #0
|
|
80070de: d101 bne.n 80070e4 <HAL_SPI_DeInit+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80070e0: 2301 movs r3, #1
|
|
80070e2: e01a b.n 800711a <HAL_SPI_DeInit+0x48>
|
|
}
|
|
|
|
/* Check SPI Instance parameter */
|
|
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
80070e4: 687b ldr r3, [r7, #4]
|
|
80070e6: 2202 movs r2, #2
|
|
80070e8: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Disable the SPI Peripheral Clock */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
80070ec: 687b ldr r3, [r7, #4]
|
|
80070ee: 681b ldr r3, [r3, #0]
|
|
80070f0: 681a ldr r2, [r3, #0]
|
|
80070f2: 687b ldr r3, [r7, #4]
|
|
80070f4: 681b ldr r3, [r3, #0]
|
|
80070f6: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
80070fa: 601a str r2, [r3, #0]
|
|
|
|
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
|
|
hspi->MspDeInitCallback(hspi);
|
|
#else
|
|
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspDeInit(hspi);
|
|
80070fc: 6878 ldr r0, [r7, #4]
|
|
80070fe: f7fc faa5 bl 800364c <HAL_SPI_MspDeInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8007102: 687b ldr r3, [r7, #4]
|
|
8007104: 2200 movs r2, #0
|
|
8007106: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->State = HAL_SPI_STATE_RESET;
|
|
8007108: 687b ldr r3, [r7, #4]
|
|
800710a: 2200 movs r2, #0
|
|
800710c: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hspi);
|
|
8007110: 687b ldr r3, [r7, #4]
|
|
8007112: 2200 movs r2, #0
|
|
8007114: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
return HAL_OK;
|
|
8007118: 2300 movs r3, #0
|
|
}
|
|
800711a: 4618 mov r0, r3
|
|
800711c: 3708 adds r7, #8
|
|
800711e: 46bd mov sp, r7
|
|
8007120: bd80 pop {r7, pc}
|
|
|
|
08007122 <HAL_SPI_Receive>:
|
|
* @param Size amount of data to be received
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8007122: b580 push {r7, lr}
|
|
8007124: b088 sub sp, #32
|
|
8007126: af02 add r7, sp, #8
|
|
8007128: 60f8 str r0, [r7, #12]
|
|
800712a: 60b9 str r1, [r7, #8]
|
|
800712c: 603b str r3, [r7, #0]
|
|
800712e: 4613 mov r3, r2
|
|
8007130: 80fb strh r3, [r7, #6]
|
|
__IO uint8_t *ptmpreg8;
|
|
__IO uint8_t tmpreg8 = 0;
|
|
#endif /* USE_SPI_CRC */
|
|
uint32_t tickstart;
|
|
|
|
if (hspi->State != HAL_SPI_STATE_READY)
|
|
8007132: 68fb ldr r3, [r7, #12]
|
|
8007134: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
8007138: b2db uxtb r3, r3
|
|
800713a: 2b01 cmp r3, #1
|
|
800713c: d001 beq.n 8007142 <HAL_SPI_Receive+0x20>
|
|
{
|
|
return HAL_BUSY;
|
|
800713e: 2302 movs r3, #2
|
|
8007140: e123 b.n 800738a <HAL_SPI_Receive+0x268>
|
|
}
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
|
|
8007142: 68fb ldr r3, [r7, #12]
|
|
8007144: 685b ldr r3, [r3, #4]
|
|
8007146: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800714a: d112 bne.n 8007172 <HAL_SPI_Receive+0x50>
|
|
800714c: 68fb ldr r3, [r7, #12]
|
|
800714e: 689b ldr r3, [r3, #8]
|
|
8007150: 2b00 cmp r3, #0
|
|
8007152: d10e bne.n 8007172 <HAL_SPI_Receive+0x50>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_BUSY_RX;
|
|
8007154: 68fb ldr r3, [r7, #12]
|
|
8007156: 2204 movs r2, #4
|
|
8007158: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
|
|
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
|
|
800715c: 88fa ldrh r2, [r7, #6]
|
|
800715e: 683b ldr r3, [r7, #0]
|
|
8007160: 9300 str r3, [sp, #0]
|
|
8007162: 4613 mov r3, r2
|
|
8007164: 68ba ldr r2, [r7, #8]
|
|
8007166: 68b9 ldr r1, [r7, #8]
|
|
8007168: 68f8 ldr r0, [r7, #12]
|
|
800716a: f000 f912 bl 8007392 <HAL_SPI_TransmitReceive>
|
|
800716e: 4603 mov r3, r0
|
|
8007170: e10b b.n 800738a <HAL_SPI_Receive+0x268>
|
|
}
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8007172: f7fc fdc5 bl 8003d00 <HAL_GetTick>
|
|
8007176: 6178 str r0, [r7, #20]
|
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8007178: 68bb ldr r3, [r7, #8]
|
|
800717a: 2b00 cmp r3, #0
|
|
800717c: d002 beq.n 8007184 <HAL_SPI_Receive+0x62>
|
|
800717e: 88fb ldrh r3, [r7, #6]
|
|
8007180: 2b00 cmp r3, #0
|
|
8007182: d101 bne.n 8007188 <HAL_SPI_Receive+0x66>
|
|
{
|
|
return HAL_ERROR;
|
|
8007184: 2301 movs r3, #1
|
|
8007186: e100 b.n 800738a <HAL_SPI_Receive+0x268>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hspi);
|
|
8007188: 68fb ldr r3, [r7, #12]
|
|
800718a: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
800718e: 2b01 cmp r3, #1
|
|
8007190: d101 bne.n 8007196 <HAL_SPI_Receive+0x74>
|
|
8007192: 2302 movs r3, #2
|
|
8007194: e0f9 b.n 800738a <HAL_SPI_Receive+0x268>
|
|
8007196: 68fb ldr r3, [r7, #12]
|
|
8007198: 2201 movs r2, #1
|
|
800719a: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set the transaction information */
|
|
hspi->State = HAL_SPI_STATE_BUSY_RX;
|
|
800719e: 68fb ldr r3, [r7, #12]
|
|
80071a0: 2204 movs r2, #4
|
|
80071a2: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
80071a6: 68fb ldr r3, [r7, #12]
|
|
80071a8: 2200 movs r2, #0
|
|
80071aa: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pRxBuffPtr = (uint8_t *)pData;
|
|
80071ac: 68fb ldr r3, [r7, #12]
|
|
80071ae: 68ba ldr r2, [r7, #8]
|
|
80071b0: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferSize = Size;
|
|
80071b2: 68fb ldr r3, [r7, #12]
|
|
80071b4: 88fa ldrh r2, [r7, #6]
|
|
80071b6: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->RxXferCount = Size;
|
|
80071ba: 68fb ldr r3, [r7, #12]
|
|
80071bc: 88fa ldrh r2, [r7, #6]
|
|
80071be: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
|
|
/*Init field not used in handle to zero */
|
|
hspi->pTxBuffPtr = (uint8_t *)NULL;
|
|
80071c2: 68fb ldr r3, [r7, #12]
|
|
80071c4: 2200 movs r2, #0
|
|
80071c6: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferSize = 0U;
|
|
80071c8: 68fb ldr r3, [r7, #12]
|
|
80071ca: 2200 movs r2, #0
|
|
80071cc: 879a strh r2, [r3, #60] @ 0x3c
|
|
hspi->TxXferCount = 0U;
|
|
80071ce: 68fb ldr r3, [r7, #12]
|
|
80071d0: 2200 movs r2, #0
|
|
80071d2: 87da strh r2, [r3, #62] @ 0x3e
|
|
hspi->RxISR = NULL;
|
|
80071d4: 68fb ldr r3, [r7, #12]
|
|
80071d6: 2200 movs r2, #0
|
|
80071d8: 64da str r2, [r3, #76] @ 0x4c
|
|
hspi->TxISR = NULL;
|
|
80071da: 68fb ldr r3, [r7, #12]
|
|
80071dc: 2200 movs r2, #0
|
|
80071de: 651a str r2, [r3, #80] @ 0x50
|
|
hspi->RxXferCount--;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Set the Rx Fifo threshold */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
80071e0: 68fb ldr r3, [r7, #12]
|
|
80071e2: 68db ldr r3, [r3, #12]
|
|
80071e4: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
80071e8: d908 bls.n 80071fc <HAL_SPI_Receive+0xda>
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 16bit */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
80071ea: 68fb ldr r3, [r7, #12]
|
|
80071ec: 681b ldr r3, [r3, #0]
|
|
80071ee: 685a ldr r2, [r3, #4]
|
|
80071f0: 68fb ldr r3, [r7, #12]
|
|
80071f2: 681b ldr r3, [r3, #0]
|
|
80071f4: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
80071f8: 605a str r2, [r3, #4]
|
|
80071fa: e007 b.n 800720c <HAL_SPI_Receive+0xea>
|
|
}
|
|
else
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 8bit */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
80071fc: 68fb ldr r3, [r7, #12]
|
|
80071fe: 681b ldr r3, [r3, #0]
|
|
8007200: 685a ldr r2, [r3, #4]
|
|
8007202: 68fb ldr r3, [r7, #12]
|
|
8007204: 681b ldr r3, [r3, #0]
|
|
8007206: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
800720a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Configure communication direction: 1Line */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
800720c: 68fb ldr r3, [r7, #12]
|
|
800720e: 689b ldr r3, [r3, #8]
|
|
8007210: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8007214: d10f bne.n 8007236 <HAL_SPI_Receive+0x114>
|
|
{
|
|
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8007216: 68fb ldr r3, [r7, #12]
|
|
8007218: 681b ldr r3, [r3, #0]
|
|
800721a: 681a ldr r2, [r3, #0]
|
|
800721c: 68fb ldr r3, [r7, #12]
|
|
800721e: 681b ldr r3, [r3, #0]
|
|
8007220: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8007224: 601a str r2, [r3, #0]
|
|
SPI_1LINE_RX(hspi);
|
|
8007226: 68fb ldr r3, [r7, #12]
|
|
8007228: 681b ldr r3, [r3, #0]
|
|
800722a: 681a ldr r2, [r3, #0]
|
|
800722c: 68fb ldr r3, [r7, #12]
|
|
800722e: 681b ldr r3, [r3, #0]
|
|
8007230: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
8007234: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
8007236: 68fb ldr r3, [r7, #12]
|
|
8007238: 681b ldr r3, [r3, #0]
|
|
800723a: 681b ldr r3, [r3, #0]
|
|
800723c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8007240: 2b40 cmp r3, #64 @ 0x40
|
|
8007242: d007 beq.n 8007254 <HAL_SPI_Receive+0x132>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
8007244: 68fb ldr r3, [r7, #12]
|
|
8007246: 681b ldr r3, [r3, #0]
|
|
8007248: 681a ldr r2, [r3, #0]
|
|
800724a: 68fb ldr r3, [r7, #12]
|
|
800724c: 681b ldr r3, [r3, #0]
|
|
800724e: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
8007252: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Receive data in 8 Bit mode */
|
|
if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
|
|
8007254: 68fb ldr r3, [r7, #12]
|
|
8007256: 68db ldr r3, [r3, #12]
|
|
8007258: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
800725c: d875 bhi.n 800734a <HAL_SPI_Receive+0x228>
|
|
{
|
|
/* Transfer loop */
|
|
while (hspi->RxXferCount > 0U)
|
|
800725e: e037 b.n 80072d0 <HAL_SPI_Receive+0x1ae>
|
|
{
|
|
/* Check the RXNE flag */
|
|
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
|
|
8007260: 68fb ldr r3, [r7, #12]
|
|
8007262: 681b ldr r3, [r3, #0]
|
|
8007264: 689b ldr r3, [r3, #8]
|
|
8007266: f003 0301 and.w r3, r3, #1
|
|
800726a: 2b01 cmp r3, #1
|
|
800726c: d117 bne.n 800729e <HAL_SPI_Receive+0x17c>
|
|
{
|
|
/* read the received data */
|
|
(* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
|
|
800726e: 68fb ldr r3, [r7, #12]
|
|
8007270: 681b ldr r3, [r3, #0]
|
|
8007272: f103 020c add.w r2, r3, #12
|
|
8007276: 68fb ldr r3, [r7, #12]
|
|
8007278: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800727a: 7812 ldrb r2, [r2, #0]
|
|
800727c: b2d2 uxtb r2, r2
|
|
800727e: 701a strb r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint8_t);
|
|
8007280: 68fb ldr r3, [r7, #12]
|
|
8007282: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007284: 1c5a adds r2, r3, #1
|
|
8007286: 68fb ldr r3, [r7, #12]
|
|
8007288: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
800728a: 68fb ldr r3, [r7, #12]
|
|
800728c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007290: b29b uxth r3, r3
|
|
8007292: 3b01 subs r3, #1
|
|
8007294: b29a uxth r2, r3
|
|
8007296: 68fb ldr r3, [r7, #12]
|
|
8007298: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
800729c: e018 b.n 80072d0 <HAL_SPI_Receive+0x1ae>
|
|
}
|
|
else
|
|
{
|
|
/* Timeout management */
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
|
|
800729e: f7fc fd2f bl 8003d00 <HAL_GetTick>
|
|
80072a2: 4602 mov r2, r0
|
|
80072a4: 697b ldr r3, [r7, #20]
|
|
80072a6: 1ad3 subs r3, r2, r3
|
|
80072a8: 683a ldr r2, [r7, #0]
|
|
80072aa: 429a cmp r2, r3
|
|
80072ac: d803 bhi.n 80072b6 <HAL_SPI_Receive+0x194>
|
|
80072ae: 683b ldr r3, [r7, #0]
|
|
80072b0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
80072b4: d102 bne.n 80072bc <HAL_SPI_Receive+0x19a>
|
|
80072b6: 683b ldr r3, [r7, #0]
|
|
80072b8: 2b00 cmp r3, #0
|
|
80072ba: d109 bne.n 80072d0 <HAL_SPI_Receive+0x1ae>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80072bc: 68fb ldr r3, [r7, #12]
|
|
80072be: 2201 movs r2, #1
|
|
80072c0: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
80072c4: 68fb ldr r3, [r7, #12]
|
|
80072c6: 2200 movs r2, #0
|
|
80072c8: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
80072cc: 2303 movs r3, #3
|
|
80072ce: e05c b.n 800738a <HAL_SPI_Receive+0x268>
|
|
while (hspi->RxXferCount > 0U)
|
|
80072d0: 68fb ldr r3, [r7, #12]
|
|
80072d2: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
80072d6: b29b uxth r3, r3
|
|
80072d8: 2b00 cmp r3, #0
|
|
80072da: d1c1 bne.n 8007260 <HAL_SPI_Receive+0x13e>
|
|
80072dc: e03b b.n 8007356 <HAL_SPI_Receive+0x234>
|
|
{
|
|
/* Transfer loop */
|
|
while (hspi->RxXferCount > 0U)
|
|
{
|
|
/* Check the RXNE flag */
|
|
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
|
|
80072de: 68fb ldr r3, [r7, #12]
|
|
80072e0: 681b ldr r3, [r3, #0]
|
|
80072e2: 689b ldr r3, [r3, #8]
|
|
80072e4: f003 0301 and.w r3, r3, #1
|
|
80072e8: 2b01 cmp r3, #1
|
|
80072ea: d115 bne.n 8007318 <HAL_SPI_Receive+0x1f6>
|
|
{
|
|
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
|
|
80072ec: 68fb ldr r3, [r7, #12]
|
|
80072ee: 681b ldr r3, [r3, #0]
|
|
80072f0: 68da ldr r2, [r3, #12]
|
|
80072f2: 68fb ldr r3, [r7, #12]
|
|
80072f4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80072f6: b292 uxth r2, r2
|
|
80072f8: 801a strh r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint16_t);
|
|
80072fa: 68fb ldr r3, [r7, #12]
|
|
80072fc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80072fe: 1c9a adds r2, r3, #2
|
|
8007300: 68fb ldr r3, [r7, #12]
|
|
8007302: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
8007304: 68fb ldr r3, [r7, #12]
|
|
8007306: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800730a: b29b uxth r3, r3
|
|
800730c: 3b01 subs r3, #1
|
|
800730e: b29a uxth r2, r3
|
|
8007310: 68fb ldr r3, [r7, #12]
|
|
8007312: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
8007316: e018 b.n 800734a <HAL_SPI_Receive+0x228>
|
|
}
|
|
else
|
|
{
|
|
/* Timeout management */
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
|
|
8007318: f7fc fcf2 bl 8003d00 <HAL_GetTick>
|
|
800731c: 4602 mov r2, r0
|
|
800731e: 697b ldr r3, [r7, #20]
|
|
8007320: 1ad3 subs r3, r2, r3
|
|
8007322: 683a ldr r2, [r7, #0]
|
|
8007324: 429a cmp r2, r3
|
|
8007326: d803 bhi.n 8007330 <HAL_SPI_Receive+0x20e>
|
|
8007328: 683b ldr r3, [r7, #0]
|
|
800732a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800732e: d102 bne.n 8007336 <HAL_SPI_Receive+0x214>
|
|
8007330: 683b ldr r3, [r7, #0]
|
|
8007332: 2b00 cmp r3, #0
|
|
8007334: d109 bne.n 800734a <HAL_SPI_Receive+0x228>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8007336: 68fb ldr r3, [r7, #12]
|
|
8007338: 2201 movs r2, #1
|
|
800733a: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
800733e: 68fb ldr r3, [r7, #12]
|
|
8007340: 2200 movs r2, #0
|
|
8007342: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
8007346: 2303 movs r3, #3
|
|
8007348: e01f b.n 800738a <HAL_SPI_Receive+0x268>
|
|
while (hspi->RxXferCount > 0U)
|
|
800734a: 68fb ldr r3, [r7, #12]
|
|
800734c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007350: b29b uxth r3, r3
|
|
8007352: 2b00 cmp r3, #0
|
|
8007354: d1c3 bne.n 80072de <HAL_SPI_Receive+0x1bc>
|
|
}
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
|
|
8007356: 697a ldr r2, [r7, #20]
|
|
8007358: 6839 ldr r1, [r7, #0]
|
|
800735a: 68f8 ldr r0, [r7, #12]
|
|
800735c: f000 fffa bl 8008354 <SPI_EndRxTransaction>
|
|
8007360: 4603 mov r3, r0
|
|
8007362: 2b00 cmp r3, #0
|
|
8007364: d002 beq.n 800736c <HAL_SPI_Receive+0x24a>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
|
|
8007366: 68fb ldr r3, [r7, #12]
|
|
8007368: 2220 movs r2, #32
|
|
800736a: 661a str r2, [r3, #96] @ 0x60
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
|
|
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800736c: 68fb ldr r3, [r7, #12]
|
|
800736e: 2201 movs r2, #1
|
|
8007370: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Unlock the process */
|
|
__HAL_UNLOCK(hspi);
|
|
8007374: 68fb ldr r3, [r7, #12]
|
|
8007376: 2200 movs r2, #0
|
|
8007378: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
800737c: 68fb ldr r3, [r7, #12]
|
|
800737e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8007380: 2b00 cmp r3, #0
|
|
8007382: d001 beq.n 8007388 <HAL_SPI_Receive+0x266>
|
|
{
|
|
return HAL_ERROR;
|
|
8007384: 2301 movs r3, #1
|
|
8007386: e000 b.n 800738a <HAL_SPI_Receive+0x268>
|
|
}
|
|
else
|
|
{
|
|
return HAL_OK;
|
|
8007388: 2300 movs r3, #0
|
|
}
|
|
}
|
|
800738a: 4618 mov r0, r3
|
|
800738c: 3718 adds r7, #24
|
|
800738e: 46bd mov sp, r7
|
|
8007390: bd80 pop {r7, pc}
|
|
|
|
08007392 <HAL_SPI_TransmitReceive>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
|
uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8007392: b580 push {r7, lr}
|
|
8007394: b08a sub sp, #40 @ 0x28
|
|
8007396: af00 add r7, sp, #0
|
|
8007398: 60f8 str r0, [r7, #12]
|
|
800739a: 60b9 str r1, [r7, #8]
|
|
800739c: 607a str r2, [r7, #4]
|
|
800739e: 807b strh r3, [r7, #2]
|
|
__IO uint8_t *ptmpreg8;
|
|
__IO uint8_t tmpreg8 = 0;
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Variable used to alternate Rx and Tx during transfer */
|
|
uint32_t txallowed = 1U;
|
|
80073a0: 2301 movs r3, #1
|
|
80073a2: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Check Direction parameter */
|
|
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
80073a4: f7fc fcac bl 8003d00 <HAL_GetTick>
|
|
80073a8: 6238 str r0, [r7, #32]
|
|
|
|
/* Init temporary variables */
|
|
tmp_state = hspi->State;
|
|
80073aa: 68fb ldr r3, [r7, #12]
|
|
80073ac: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
80073b0: 77fb strb r3, [r7, #31]
|
|
tmp_mode = hspi->Init.Mode;
|
|
80073b2: 68fb ldr r3, [r7, #12]
|
|
80073b4: 685b ldr r3, [r3, #4]
|
|
80073b6: 61bb str r3, [r7, #24]
|
|
initial_TxXferCount = Size;
|
|
80073b8: 887b ldrh r3, [r7, #2]
|
|
80073ba: 82fb strh r3, [r7, #22]
|
|
initial_RxXferCount = Size;
|
|
80073bc: 887b ldrh r3, [r7, #2]
|
|
80073be: 82bb strh r3, [r7, #20]
|
|
#if (USE_SPI_CRC != 0U)
|
|
spi_cr1 = READ_REG(hspi->Instance->CR1);
|
|
spi_cr2 = READ_REG(hspi->Instance->CR2);
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (!((tmp_state == HAL_SPI_STATE_READY) || \
|
|
80073c0: 7ffb ldrb r3, [r7, #31]
|
|
80073c2: 2b01 cmp r3, #1
|
|
80073c4: d00c beq.n 80073e0 <HAL_SPI_TransmitReceive+0x4e>
|
|
80073c6: 69bb ldr r3, [r7, #24]
|
|
80073c8: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
80073cc: d106 bne.n 80073dc <HAL_SPI_TransmitReceive+0x4a>
|
|
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
|
|
80073ce: 68fb ldr r3, [r7, #12]
|
|
80073d0: 689b ldr r3, [r3, #8]
|
|
80073d2: 2b00 cmp r3, #0
|
|
80073d4: d102 bne.n 80073dc <HAL_SPI_TransmitReceive+0x4a>
|
|
80073d6: 7ffb ldrb r3, [r7, #31]
|
|
80073d8: 2b04 cmp r3, #4
|
|
80073da: d001 beq.n 80073e0 <HAL_SPI_TransmitReceive+0x4e>
|
|
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
|
|
{
|
|
return HAL_BUSY;
|
|
80073dc: 2302 movs r3, #2
|
|
80073de: e1f3 b.n 80077c8 <HAL_SPI_TransmitReceive+0x436>
|
|
}
|
|
|
|
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
|
|
80073e0: 68bb ldr r3, [r7, #8]
|
|
80073e2: 2b00 cmp r3, #0
|
|
80073e4: d005 beq.n 80073f2 <HAL_SPI_TransmitReceive+0x60>
|
|
80073e6: 687b ldr r3, [r7, #4]
|
|
80073e8: 2b00 cmp r3, #0
|
|
80073ea: d002 beq.n 80073f2 <HAL_SPI_TransmitReceive+0x60>
|
|
80073ec: 887b ldrh r3, [r7, #2]
|
|
80073ee: 2b00 cmp r3, #0
|
|
80073f0: d101 bne.n 80073f6 <HAL_SPI_TransmitReceive+0x64>
|
|
{
|
|
return HAL_ERROR;
|
|
80073f2: 2301 movs r3, #1
|
|
80073f4: e1e8 b.n 80077c8 <HAL_SPI_TransmitReceive+0x436>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hspi);
|
|
80073f6: 68fb ldr r3, [r7, #12]
|
|
80073f8: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
80073fc: 2b01 cmp r3, #1
|
|
80073fe: d101 bne.n 8007404 <HAL_SPI_TransmitReceive+0x72>
|
|
8007400: 2302 movs r3, #2
|
|
8007402: e1e1 b.n 80077c8 <HAL_SPI_TransmitReceive+0x436>
|
|
8007404: 68fb ldr r3, [r7, #12]
|
|
8007406: 2201 movs r2, #1
|
|
8007408: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
|
|
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
|
|
800740c: 68fb ldr r3, [r7, #12]
|
|
800740e: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
8007412: b2db uxtb r3, r3
|
|
8007414: 2b04 cmp r3, #4
|
|
8007416: d003 beq.n 8007420 <HAL_SPI_TransmitReceive+0x8e>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
|
|
8007418: 68fb ldr r3, [r7, #12]
|
|
800741a: 2205 movs r2, #5
|
|
800741c: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
}
|
|
|
|
/* Set the transaction information */
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8007420: 68fb ldr r3, [r7, #12]
|
|
8007422: 2200 movs r2, #0
|
|
8007424: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pRxBuffPtr = (uint8_t *)pRxData;
|
|
8007426: 68fb ldr r3, [r7, #12]
|
|
8007428: 687a ldr r2, [r7, #4]
|
|
800742a: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount = Size;
|
|
800742c: 68fb ldr r3, [r7, #12]
|
|
800742e: 887a ldrh r2, [r7, #2]
|
|
8007430: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->RxXferSize = Size;
|
|
8007434: 68fb ldr r3, [r7, #12]
|
|
8007436: 887a ldrh r2, [r7, #2]
|
|
8007438: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
|
|
800743c: 68fb ldr r3, [r7, #12]
|
|
800743e: 68ba ldr r2, [r7, #8]
|
|
8007440: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount = Size;
|
|
8007442: 68fb ldr r3, [r7, #12]
|
|
8007444: 887a ldrh r2, [r7, #2]
|
|
8007446: 87da strh r2, [r3, #62] @ 0x3e
|
|
hspi->TxXferSize = Size;
|
|
8007448: 68fb ldr r3, [r7, #12]
|
|
800744a: 887a ldrh r2, [r7, #2]
|
|
800744c: 879a strh r2, [r3, #60] @ 0x3c
|
|
|
|
/*Init field not used in handle to zero */
|
|
hspi->RxISR = NULL;
|
|
800744e: 68fb ldr r3, [r7, #12]
|
|
8007450: 2200 movs r2, #0
|
|
8007452: 64da str r2, [r3, #76] @ 0x4c
|
|
hspi->TxISR = NULL;
|
|
8007454: 68fb ldr r3, [r7, #12]
|
|
8007456: 2200 movs r2, #0
|
|
8007458: 651a str r2, [r3, #80] @ 0x50
|
|
SPI_RESET_CRC(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Set the Rx Fifo threshold */
|
|
if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
|
|
800745a: 68fb ldr r3, [r7, #12]
|
|
800745c: 68db ldr r3, [r3, #12]
|
|
800745e: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8007462: d802 bhi.n 800746a <HAL_SPI_TransmitReceive+0xd8>
|
|
8007464: 8abb ldrh r3, [r7, #20]
|
|
8007466: 2b01 cmp r3, #1
|
|
8007468: d908 bls.n 800747c <HAL_SPI_TransmitReceive+0xea>
|
|
{
|
|
/* Set fiforxthreshold according the reception data length: 16bit */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
800746a: 68fb ldr r3, [r7, #12]
|
|
800746c: 681b ldr r3, [r3, #0]
|
|
800746e: 685a ldr r2, [r3, #4]
|
|
8007470: 68fb ldr r3, [r7, #12]
|
|
8007472: 681b ldr r3, [r3, #0]
|
|
8007474: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
8007478: 605a str r2, [r3, #4]
|
|
800747a: e007 b.n 800748c <HAL_SPI_TransmitReceive+0xfa>
|
|
}
|
|
else
|
|
{
|
|
/* Set fiforxthreshold according the reception data length: 8bit */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
800747c: 68fb ldr r3, [r7, #12]
|
|
800747e: 681b ldr r3, [r3, #0]
|
|
8007480: 685a ldr r2, [r3, #4]
|
|
8007482: 68fb ldr r3, [r7, #12]
|
|
8007484: 681b ldr r3, [r3, #0]
|
|
8007486: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
800748a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
800748c: 68fb ldr r3, [r7, #12]
|
|
800748e: 681b ldr r3, [r3, #0]
|
|
8007490: 681b ldr r3, [r3, #0]
|
|
8007492: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8007496: 2b40 cmp r3, #64 @ 0x40
|
|
8007498: d007 beq.n 80074aa <HAL_SPI_TransmitReceive+0x118>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
800749a: 68fb ldr r3, [r7, #12]
|
|
800749c: 681b ldr r3, [r3, #0]
|
|
800749e: 681a ldr r2, [r3, #0]
|
|
80074a0: 68fb ldr r3, [r7, #12]
|
|
80074a2: 681b ldr r3, [r3, #0]
|
|
80074a4: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
80074a8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Transmit and Receive data in 16 Bit mode */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
80074aa: 68fb ldr r3, [r7, #12]
|
|
80074ac: 68db ldr r3, [r3, #12]
|
|
80074ae: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
80074b2: f240 8083 bls.w 80075bc <HAL_SPI_TransmitReceive+0x22a>
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
80074b6: 68fb ldr r3, [r7, #12]
|
|
80074b8: 685b ldr r3, [r3, #4]
|
|
80074ba: 2b00 cmp r3, #0
|
|
80074bc: d002 beq.n 80074c4 <HAL_SPI_TransmitReceive+0x132>
|
|
80074be: 8afb ldrh r3, [r7, #22]
|
|
80074c0: 2b01 cmp r3, #1
|
|
80074c2: d16f bne.n 80075a4 <HAL_SPI_TransmitReceive+0x212>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
80074c4: 68fb ldr r3, [r7, #12]
|
|
80074c6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80074c8: 881a ldrh r2, [r3, #0]
|
|
80074ca: 68fb ldr r3, [r7, #12]
|
|
80074cc: 681b ldr r3, [r3, #0]
|
|
80074ce: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
80074d0: 68fb ldr r3, [r7, #12]
|
|
80074d2: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80074d4: 1c9a adds r2, r3, #2
|
|
80074d6: 68fb ldr r3, [r7, #12]
|
|
80074d8: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
80074da: 68fb ldr r3, [r7, #12]
|
|
80074dc: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80074de: b29b uxth r3, r3
|
|
80074e0: 3b01 subs r3, #1
|
|
80074e2: b29a uxth r2, r3
|
|
80074e4: 68fb ldr r3, [r7, #12]
|
|
80074e6: 87da strh r2, [r3, #62] @ 0x3e
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
}
|
|
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
|
|
80074e8: e05c b.n 80075a4 <HAL_SPI_TransmitReceive+0x212>
|
|
{
|
|
/* Check TXE flag */
|
|
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
|
|
80074ea: 68fb ldr r3, [r7, #12]
|
|
80074ec: 681b ldr r3, [r3, #0]
|
|
80074ee: 689b ldr r3, [r3, #8]
|
|
80074f0: f003 0302 and.w r3, r3, #2
|
|
80074f4: 2b02 cmp r3, #2
|
|
80074f6: d11b bne.n 8007530 <HAL_SPI_TransmitReceive+0x19e>
|
|
80074f8: 68fb ldr r3, [r7, #12]
|
|
80074fa: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80074fc: b29b uxth r3, r3
|
|
80074fe: 2b00 cmp r3, #0
|
|
8007500: d016 beq.n 8007530 <HAL_SPI_TransmitReceive+0x19e>
|
|
8007502: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007504: 2b01 cmp r3, #1
|
|
8007506: d113 bne.n 8007530 <HAL_SPI_TransmitReceive+0x19e>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
8007508: 68fb ldr r3, [r7, #12]
|
|
800750a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800750c: 881a ldrh r2, [r3, #0]
|
|
800750e: 68fb ldr r3, [r7, #12]
|
|
8007510: 681b ldr r3, [r3, #0]
|
|
8007512: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
8007514: 68fb ldr r3, [r7, #12]
|
|
8007516: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007518: 1c9a adds r2, r3, #2
|
|
800751a: 68fb ldr r3, [r7, #12]
|
|
800751c: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800751e: 68fb ldr r3, [r7, #12]
|
|
8007520: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007522: b29b uxth r3, r3
|
|
8007524: 3b01 subs r3, #1
|
|
8007526: b29a uxth r2, r3
|
|
8007528: 68fb ldr r3, [r7, #12]
|
|
800752a: 87da strh r2, [r3, #62] @ 0x3e
|
|
/* Next Data is a reception (Rx). Tx not allowed */
|
|
txallowed = 0U;
|
|
800752c: 2300 movs r3, #0
|
|
800752e: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
}
|
|
|
|
/* Check RXNE flag */
|
|
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
|
|
8007530: 68fb ldr r3, [r7, #12]
|
|
8007532: 681b ldr r3, [r3, #0]
|
|
8007534: 689b ldr r3, [r3, #8]
|
|
8007536: f003 0301 and.w r3, r3, #1
|
|
800753a: 2b01 cmp r3, #1
|
|
800753c: d11c bne.n 8007578 <HAL_SPI_TransmitReceive+0x1e6>
|
|
800753e: 68fb ldr r3, [r7, #12]
|
|
8007540: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007544: b29b uxth r3, r3
|
|
8007546: 2b00 cmp r3, #0
|
|
8007548: d016 beq.n 8007578 <HAL_SPI_TransmitReceive+0x1e6>
|
|
{
|
|
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
|
|
800754a: 68fb ldr r3, [r7, #12]
|
|
800754c: 681b ldr r3, [r3, #0]
|
|
800754e: 68da ldr r2, [r3, #12]
|
|
8007550: 68fb ldr r3, [r7, #12]
|
|
8007552: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007554: b292 uxth r2, r2
|
|
8007556: 801a strh r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint16_t);
|
|
8007558: 68fb ldr r3, [r7, #12]
|
|
800755a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800755c: 1c9a adds r2, r3, #2
|
|
800755e: 68fb ldr r3, [r7, #12]
|
|
8007560: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
8007562: 68fb ldr r3, [r7, #12]
|
|
8007564: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007568: b29b uxth r3, r3
|
|
800756a: 3b01 subs r3, #1
|
|
800756c: b29a uxth r2, r3
|
|
800756e: 68fb ldr r3, [r7, #12]
|
|
8007570: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
/* Next Data is a Transmission (Tx). Tx is allowed */
|
|
txallowed = 1U;
|
|
8007574: 2301 movs r3, #1
|
|
8007576: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
|
|
8007578: f7fc fbc2 bl 8003d00 <HAL_GetTick>
|
|
800757c: 4602 mov r2, r0
|
|
800757e: 6a3b ldr r3, [r7, #32]
|
|
8007580: 1ad3 subs r3, r2, r3
|
|
8007582: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8007584: 429a cmp r2, r3
|
|
8007586: d80d bhi.n 80075a4 <HAL_SPI_TransmitReceive+0x212>
|
|
8007588: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800758a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800758e: d009 beq.n 80075a4 <HAL_SPI_TransmitReceive+0x212>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8007590: 68fb ldr r3, [r7, #12]
|
|
8007592: 2201 movs r2, #1
|
|
8007594: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
8007598: 68fb ldr r3, [r7, #12]
|
|
800759a: 2200 movs r2, #0
|
|
800759c: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
80075a0: 2303 movs r3, #3
|
|
80075a2: e111 b.n 80077c8 <HAL_SPI_TransmitReceive+0x436>
|
|
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
|
|
80075a4: 68fb ldr r3, [r7, #12]
|
|
80075a6: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80075a8: b29b uxth r3, r3
|
|
80075aa: 2b00 cmp r3, #0
|
|
80075ac: d19d bne.n 80074ea <HAL_SPI_TransmitReceive+0x158>
|
|
80075ae: 68fb ldr r3, [r7, #12]
|
|
80075b0: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
80075b4: b29b uxth r3, r3
|
|
80075b6: 2b00 cmp r3, #0
|
|
80075b8: d197 bne.n 80074ea <HAL_SPI_TransmitReceive+0x158>
|
|
80075ba: e0e5 b.n 8007788 <HAL_SPI_TransmitReceive+0x3f6>
|
|
}
|
|
}
|
|
/* Transmit and Receive data in 8 Bit mode */
|
|
else
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
80075bc: 68fb ldr r3, [r7, #12]
|
|
80075be: 685b ldr r3, [r3, #4]
|
|
80075c0: 2b00 cmp r3, #0
|
|
80075c2: d003 beq.n 80075cc <HAL_SPI_TransmitReceive+0x23a>
|
|
80075c4: 8afb ldrh r3, [r7, #22]
|
|
80075c6: 2b01 cmp r3, #1
|
|
80075c8: f040 80d1 bne.w 800776e <HAL_SPI_TransmitReceive+0x3dc>
|
|
{
|
|
if (hspi->TxXferCount > 1U)
|
|
80075cc: 68fb ldr r3, [r7, #12]
|
|
80075ce: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80075d0: b29b uxth r3, r3
|
|
80075d2: 2b01 cmp r3, #1
|
|
80075d4: d912 bls.n 80075fc <HAL_SPI_TransmitReceive+0x26a>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
80075d6: 68fb ldr r3, [r7, #12]
|
|
80075d8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80075da: 881a ldrh r2, [r3, #0]
|
|
80075dc: 68fb ldr r3, [r7, #12]
|
|
80075de: 681b ldr r3, [r3, #0]
|
|
80075e0: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
80075e2: 68fb ldr r3, [r7, #12]
|
|
80075e4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80075e6: 1c9a adds r2, r3, #2
|
|
80075e8: 68fb ldr r3, [r7, #12]
|
|
80075ea: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
80075ec: 68fb ldr r3, [r7, #12]
|
|
80075ee: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80075f0: b29b uxth r3, r3
|
|
80075f2: 3b02 subs r3, #2
|
|
80075f4: b29a uxth r2, r3
|
|
80075f6: 68fb ldr r3, [r7, #12]
|
|
80075f8: 87da strh r2, [r3, #62] @ 0x3e
|
|
80075fa: e0b8 b.n 800776e <HAL_SPI_TransmitReceive+0x3dc>
|
|
}
|
|
else
|
|
{
|
|
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
80075fc: 68fb ldr r3, [r7, #12]
|
|
80075fe: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8007600: 68fb ldr r3, [r7, #12]
|
|
8007602: 681b ldr r3, [r3, #0]
|
|
8007604: 330c adds r3, #12
|
|
8007606: 7812 ldrb r2, [r2, #0]
|
|
8007608: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr++;
|
|
800760a: 68fb ldr r3, [r7, #12]
|
|
800760c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800760e: 1c5a adds r2, r3, #1
|
|
8007610: 68fb ldr r3, [r7, #12]
|
|
8007612: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
8007614: 68fb ldr r3, [r7, #12]
|
|
8007616: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007618: b29b uxth r3, r3
|
|
800761a: 3b01 subs r3, #1
|
|
800761c: b29a uxth r2, r3
|
|
800761e: 68fb ldr r3, [r7, #12]
|
|
8007620: 87da strh r2, [r3, #62] @ 0x3e
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
}
|
|
}
|
|
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
|
|
8007622: e0a4 b.n 800776e <HAL_SPI_TransmitReceive+0x3dc>
|
|
{
|
|
/* Check TXE flag */
|
|
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
|
|
8007624: 68fb ldr r3, [r7, #12]
|
|
8007626: 681b ldr r3, [r3, #0]
|
|
8007628: 689b ldr r3, [r3, #8]
|
|
800762a: f003 0302 and.w r3, r3, #2
|
|
800762e: 2b02 cmp r3, #2
|
|
8007630: d134 bne.n 800769c <HAL_SPI_TransmitReceive+0x30a>
|
|
8007632: 68fb ldr r3, [r7, #12]
|
|
8007634: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007636: b29b uxth r3, r3
|
|
8007638: 2b00 cmp r3, #0
|
|
800763a: d02f beq.n 800769c <HAL_SPI_TransmitReceive+0x30a>
|
|
800763c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800763e: 2b01 cmp r3, #1
|
|
8007640: d12c bne.n 800769c <HAL_SPI_TransmitReceive+0x30a>
|
|
{
|
|
if (hspi->TxXferCount > 1U)
|
|
8007642: 68fb ldr r3, [r7, #12]
|
|
8007644: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007646: b29b uxth r3, r3
|
|
8007648: 2b01 cmp r3, #1
|
|
800764a: d912 bls.n 8007672 <HAL_SPI_TransmitReceive+0x2e0>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800764c: 68fb ldr r3, [r7, #12]
|
|
800764e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007650: 881a ldrh r2, [r3, #0]
|
|
8007652: 68fb ldr r3, [r7, #12]
|
|
8007654: 681b ldr r3, [r3, #0]
|
|
8007656: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
8007658: 68fb ldr r3, [r7, #12]
|
|
800765a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800765c: 1c9a adds r2, r3, #2
|
|
800765e: 68fb ldr r3, [r7, #12]
|
|
8007660: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
8007662: 68fb ldr r3, [r7, #12]
|
|
8007664: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007666: b29b uxth r3, r3
|
|
8007668: 3b02 subs r3, #2
|
|
800766a: b29a uxth r2, r3
|
|
800766c: 68fb ldr r3, [r7, #12]
|
|
800766e: 87da strh r2, [r3, #62] @ 0x3e
|
|
8007670: e012 b.n 8007698 <HAL_SPI_TransmitReceive+0x306>
|
|
}
|
|
else
|
|
{
|
|
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
8007672: 68fb ldr r3, [r7, #12]
|
|
8007674: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8007676: 68fb ldr r3, [r7, #12]
|
|
8007678: 681b ldr r3, [r3, #0]
|
|
800767a: 330c adds r3, #12
|
|
800767c: 7812 ldrb r2, [r2, #0]
|
|
800767e: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr++;
|
|
8007680: 68fb ldr r3, [r7, #12]
|
|
8007682: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007684: 1c5a adds r2, r3, #1
|
|
8007686: 68fb ldr r3, [r7, #12]
|
|
8007688: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800768a: 68fb ldr r3, [r7, #12]
|
|
800768c: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800768e: b29b uxth r3, r3
|
|
8007690: 3b01 subs r3, #1
|
|
8007692: b29a uxth r2, r3
|
|
8007694: 68fb ldr r3, [r7, #12]
|
|
8007696: 87da strh r2, [r3, #62] @ 0x3e
|
|
}
|
|
/* Next Data is a reception (Rx). Tx not allowed */
|
|
txallowed = 0U;
|
|
8007698: 2300 movs r3, #0
|
|
800769a: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
}
|
|
|
|
/* Wait until RXNE flag is reset */
|
|
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
|
|
800769c: 68fb ldr r3, [r7, #12]
|
|
800769e: 681b ldr r3, [r3, #0]
|
|
80076a0: 689b ldr r3, [r3, #8]
|
|
80076a2: f003 0301 and.w r3, r3, #1
|
|
80076a6: 2b01 cmp r3, #1
|
|
80076a8: d148 bne.n 800773c <HAL_SPI_TransmitReceive+0x3aa>
|
|
80076aa: 68fb ldr r3, [r7, #12]
|
|
80076ac: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
80076b0: b29b uxth r3, r3
|
|
80076b2: 2b00 cmp r3, #0
|
|
80076b4: d042 beq.n 800773c <HAL_SPI_TransmitReceive+0x3aa>
|
|
{
|
|
if (hspi->RxXferCount > 1U)
|
|
80076b6: 68fb ldr r3, [r7, #12]
|
|
80076b8: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
80076bc: b29b uxth r3, r3
|
|
80076be: 2b01 cmp r3, #1
|
|
80076c0: d923 bls.n 800770a <HAL_SPI_TransmitReceive+0x378>
|
|
{
|
|
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
|
|
80076c2: 68fb ldr r3, [r7, #12]
|
|
80076c4: 681b ldr r3, [r3, #0]
|
|
80076c6: 68da ldr r2, [r3, #12]
|
|
80076c8: 68fb ldr r3, [r7, #12]
|
|
80076ca: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80076cc: b292 uxth r2, r2
|
|
80076ce: 801a strh r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint16_t);
|
|
80076d0: 68fb ldr r3, [r7, #12]
|
|
80076d2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80076d4: 1c9a adds r2, r3, #2
|
|
80076d6: 68fb ldr r3, [r7, #12]
|
|
80076d8: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount -= 2U;
|
|
80076da: 68fb ldr r3, [r7, #12]
|
|
80076dc: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
80076e0: b29b uxth r3, r3
|
|
80076e2: 3b02 subs r3, #2
|
|
80076e4: b29a uxth r2, r3
|
|
80076e6: 68fb ldr r3, [r7, #12]
|
|
80076e8: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
if (hspi->RxXferCount <= 1U)
|
|
80076ec: 68fb ldr r3, [r7, #12]
|
|
80076ee: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
80076f2: b29b uxth r3, r3
|
|
80076f4: 2b01 cmp r3, #1
|
|
80076f6: d81f bhi.n 8007738 <HAL_SPI_TransmitReceive+0x3a6>
|
|
{
|
|
/* Set RX Fifo threshold before to switch on 8 bit data size */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
80076f8: 68fb ldr r3, [r7, #12]
|
|
80076fa: 681b ldr r3, [r3, #0]
|
|
80076fc: 685a ldr r2, [r3, #4]
|
|
80076fe: 68fb ldr r3, [r7, #12]
|
|
8007700: 681b ldr r3, [r3, #0]
|
|
8007702: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
8007706: 605a str r2, [r3, #4]
|
|
8007708: e016 b.n 8007738 <HAL_SPI_TransmitReceive+0x3a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
|
|
800770a: 68fb ldr r3, [r7, #12]
|
|
800770c: 681b ldr r3, [r3, #0]
|
|
800770e: f103 020c add.w r2, r3, #12
|
|
8007712: 68fb ldr r3, [r7, #12]
|
|
8007714: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007716: 7812 ldrb r2, [r2, #0]
|
|
8007718: b2d2 uxtb r2, r2
|
|
800771a: 701a strb r2, [r3, #0]
|
|
hspi->pRxBuffPtr++;
|
|
800771c: 68fb ldr r3, [r7, #12]
|
|
800771e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007720: 1c5a adds r2, r3, #1
|
|
8007722: 68fb ldr r3, [r7, #12]
|
|
8007724: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
8007726: 68fb ldr r3, [r7, #12]
|
|
8007728: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800772c: b29b uxth r3, r3
|
|
800772e: 3b01 subs r3, #1
|
|
8007730: b29a uxth r2, r3
|
|
8007732: 68fb ldr r3, [r7, #12]
|
|
8007734: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
}
|
|
/* Next Data is a Transmission (Tx). Tx is allowed */
|
|
txallowed = 1U;
|
|
8007738: 2301 movs r3, #1
|
|
800773a: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
|
|
800773c: f7fc fae0 bl 8003d00 <HAL_GetTick>
|
|
8007740: 4602 mov r2, r0
|
|
8007742: 6a3b ldr r3, [r7, #32]
|
|
8007744: 1ad3 subs r3, r2, r3
|
|
8007746: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8007748: 429a cmp r2, r3
|
|
800774a: d803 bhi.n 8007754 <HAL_SPI_TransmitReceive+0x3c2>
|
|
800774c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800774e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8007752: d102 bne.n 800775a <HAL_SPI_TransmitReceive+0x3c8>
|
|
8007754: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8007756: 2b00 cmp r3, #0
|
|
8007758: d109 bne.n 800776e <HAL_SPI_TransmitReceive+0x3dc>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800775a: 68fb ldr r3, [r7, #12]
|
|
800775c: 2201 movs r2, #1
|
|
800775e: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
8007762: 68fb ldr r3, [r7, #12]
|
|
8007764: 2200 movs r2, #0
|
|
8007766: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
800776a: 2303 movs r3, #3
|
|
800776c: e02c b.n 80077c8 <HAL_SPI_TransmitReceive+0x436>
|
|
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
|
|
800776e: 68fb ldr r3, [r7, #12]
|
|
8007770: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007772: b29b uxth r3, r3
|
|
8007774: 2b00 cmp r3, #0
|
|
8007776: f47f af55 bne.w 8007624 <HAL_SPI_TransmitReceive+0x292>
|
|
800777a: 68fb ldr r3, [r7, #12]
|
|
800777c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007780: b29b uxth r3, r3
|
|
8007782: 2b00 cmp r3, #0
|
|
8007784: f47f af4e bne.w 8007624 <HAL_SPI_TransmitReceive+0x292>
|
|
return HAL_ERROR;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
|
|
8007788: 6a3a ldr r2, [r7, #32]
|
|
800778a: 6b39 ldr r1, [r7, #48] @ 0x30
|
|
800778c: 68f8 ldr r0, [r7, #12]
|
|
800778e: f000 fe39 bl 8008404 <SPI_EndRxTxTransaction>
|
|
8007792: 4603 mov r3, r0
|
|
8007794: 2b00 cmp r3, #0
|
|
8007796: d008 beq.n 80077aa <HAL_SPI_TransmitReceive+0x418>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
|
|
8007798: 68fb ldr r3, [r7, #12]
|
|
800779a: 2220 movs r2, #32
|
|
800779c: 661a str r2, [r3, #96] @ 0x60
|
|
__HAL_UNLOCK(hspi);
|
|
800779e: 68fb ldr r3, [r7, #12]
|
|
80077a0: 2200 movs r2, #0
|
|
80077a2: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_ERROR;
|
|
80077a6: 2301 movs r3, #1
|
|
80077a8: e00e b.n 80077c8 <HAL_SPI_TransmitReceive+0x436>
|
|
}
|
|
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80077aa: 68fb ldr r3, [r7, #12]
|
|
80077ac: 2201 movs r2, #1
|
|
80077ae: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Unlock the process */
|
|
__HAL_UNLOCK(hspi);
|
|
80077b2: 68fb ldr r3, [r7, #12]
|
|
80077b4: 2200 movs r2, #0
|
|
80077b6: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
80077ba: 68fb ldr r3, [r7, #12]
|
|
80077bc: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80077be: 2b00 cmp r3, #0
|
|
80077c0: d001 beq.n 80077c6 <HAL_SPI_TransmitReceive+0x434>
|
|
{
|
|
return HAL_ERROR;
|
|
80077c2: 2301 movs r3, #1
|
|
80077c4: e000 b.n 80077c8 <HAL_SPI_TransmitReceive+0x436>
|
|
}
|
|
else
|
|
{
|
|
return HAL_OK;
|
|
80077c6: 2300 movs r3, #0
|
|
}
|
|
}
|
|
80077c8: 4618 mov r0, r3
|
|
80077ca: 3728 adds r7, #40 @ 0x28
|
|
80077cc: 46bd mov sp, r7
|
|
80077ce: bd80 pop {r7, pc}
|
|
|
|
080077d0 <HAL_SPI_Transmit_IT>:
|
|
* @param pData pointer to data buffer
|
|
* @param Size amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
|
|
{
|
|
80077d0: b480 push {r7}
|
|
80077d2: b085 sub sp, #20
|
|
80077d4: af00 add r7, sp, #0
|
|
80077d6: 60f8 str r0, [r7, #12]
|
|
80077d8: 60b9 str r1, [r7, #8]
|
|
80077da: 4613 mov r3, r2
|
|
80077dc: 80fb strh r3, [r7, #6]
|
|
|
|
/* Check Direction parameter */
|
|
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
|
|
|
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80077de: 68bb ldr r3, [r7, #8]
|
|
80077e0: 2b00 cmp r3, #0
|
|
80077e2: d002 beq.n 80077ea <HAL_SPI_Transmit_IT+0x1a>
|
|
80077e4: 88fb ldrh r3, [r7, #6]
|
|
80077e6: 2b00 cmp r3, #0
|
|
80077e8: d101 bne.n 80077ee <HAL_SPI_Transmit_IT+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
80077ea: 2301 movs r3, #1
|
|
80077ec: e06d b.n 80078ca <HAL_SPI_Transmit_IT+0xfa>
|
|
}
|
|
|
|
if (hspi->State != HAL_SPI_STATE_READY)
|
|
80077ee: 68fb ldr r3, [r7, #12]
|
|
80077f0: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
80077f4: b2db uxtb r3, r3
|
|
80077f6: 2b01 cmp r3, #1
|
|
80077f8: d001 beq.n 80077fe <HAL_SPI_Transmit_IT+0x2e>
|
|
{
|
|
return HAL_BUSY;
|
|
80077fa: 2302 movs r3, #2
|
|
80077fc: e065 b.n 80078ca <HAL_SPI_Transmit_IT+0xfa>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hspi);
|
|
80077fe: 68fb ldr r3, [r7, #12]
|
|
8007800: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
8007804: 2b01 cmp r3, #1
|
|
8007806: d101 bne.n 800780c <HAL_SPI_Transmit_IT+0x3c>
|
|
8007808: 2302 movs r3, #2
|
|
800780a: e05e b.n 80078ca <HAL_SPI_Transmit_IT+0xfa>
|
|
800780c: 68fb ldr r3, [r7, #12]
|
|
800780e: 2201 movs r2, #1
|
|
8007810: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set the transaction information */
|
|
hspi->State = HAL_SPI_STATE_BUSY_TX;
|
|
8007814: 68fb ldr r3, [r7, #12]
|
|
8007816: 2203 movs r2, #3
|
|
8007818: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
800781c: 68fb ldr r3, [r7, #12]
|
|
800781e: 2200 movs r2, #0
|
|
8007820: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pTxBuffPtr = (const uint8_t *)pData;
|
|
8007822: 68fb ldr r3, [r7, #12]
|
|
8007824: 68ba ldr r2, [r7, #8]
|
|
8007826: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferSize = Size;
|
|
8007828: 68fb ldr r3, [r7, #12]
|
|
800782a: 88fa ldrh r2, [r7, #6]
|
|
800782c: 879a strh r2, [r3, #60] @ 0x3c
|
|
hspi->TxXferCount = Size;
|
|
800782e: 68fb ldr r3, [r7, #12]
|
|
8007830: 88fa ldrh r2, [r7, #6]
|
|
8007832: 87da strh r2, [r3, #62] @ 0x3e
|
|
|
|
/* Init field not used in handle to zero */
|
|
hspi->pRxBuffPtr = (uint8_t *)NULL;
|
|
8007834: 68fb ldr r3, [r7, #12]
|
|
8007836: 2200 movs r2, #0
|
|
8007838: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferSize = 0U;
|
|
800783a: 68fb ldr r3, [r7, #12]
|
|
800783c: 2200 movs r2, #0
|
|
800783e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->RxXferCount = 0U;
|
|
8007842: 68fb ldr r3, [r7, #12]
|
|
8007844: 2200 movs r2, #0
|
|
8007846: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->RxISR = NULL;
|
|
800784a: 68fb ldr r3, [r7, #12]
|
|
800784c: 2200 movs r2, #0
|
|
800784e: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the function for IT treatment */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
8007850: 68fb ldr r3, [r7, #12]
|
|
8007852: 68db ldr r3, [r3, #12]
|
|
8007854: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8007858: d903 bls.n 8007862 <HAL_SPI_Transmit_IT+0x92>
|
|
{
|
|
hspi->TxISR = SPI_TxISR_16BIT;
|
|
800785a: 68fb ldr r3, [r7, #12]
|
|
800785c: 4a1e ldr r2, [pc, #120] @ (80078d8 <HAL_SPI_Transmit_IT+0x108>)
|
|
800785e: 651a str r2, [r3, #80] @ 0x50
|
|
8007860: e002 b.n 8007868 <HAL_SPI_Transmit_IT+0x98>
|
|
}
|
|
else
|
|
{
|
|
hspi->TxISR = SPI_TxISR_8BIT;
|
|
8007862: 68fb ldr r3, [r7, #12]
|
|
8007864: 4a1d ldr r2, [pc, #116] @ (80078dc <HAL_SPI_Transmit_IT+0x10c>)
|
|
8007866: 651a str r2, [r3, #80] @ 0x50
|
|
}
|
|
|
|
/* Configure communication direction : 1Line */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
8007868: 68fb ldr r3, [r7, #12]
|
|
800786a: 689b ldr r3, [r3, #8]
|
|
800786c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8007870: d10f bne.n 8007892 <HAL_SPI_Transmit_IT+0xc2>
|
|
{
|
|
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8007872: 68fb ldr r3, [r7, #12]
|
|
8007874: 681b ldr r3, [r3, #0]
|
|
8007876: 681a ldr r2, [r3, #0]
|
|
8007878: 68fb ldr r3, [r7, #12]
|
|
800787a: 681b ldr r3, [r3, #0]
|
|
800787c: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8007880: 601a str r2, [r3, #0]
|
|
SPI_1LINE_TX(hspi);
|
|
8007882: 68fb ldr r3, [r7, #12]
|
|
8007884: 681b ldr r3, [r3, #0]
|
|
8007886: 681a ldr r2, [r3, #0]
|
|
8007888: 68fb ldr r3, [r7, #12]
|
|
800788a: 681b ldr r3, [r3, #0]
|
|
800788c: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
8007890: 601a str r2, [r3, #0]
|
|
SPI_RESET_CRC(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
8007892: 68fb ldr r3, [r7, #12]
|
|
8007894: 681b ldr r3, [r3, #0]
|
|
8007896: 681b ldr r3, [r3, #0]
|
|
8007898: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800789c: 2b40 cmp r3, #64 @ 0x40
|
|
800789e: d007 beq.n 80078b0 <HAL_SPI_Transmit_IT+0xe0>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
80078a0: 68fb ldr r3, [r7, #12]
|
|
80078a2: 681b ldr r3, [r3, #0]
|
|
80078a4: 681a ldr r2, [r3, #0]
|
|
80078a6: 68fb ldr r3, [r7, #12]
|
|
80078a8: 681b ldr r3, [r3, #0]
|
|
80078aa: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
80078ae: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
80078b0: 68fb ldr r3, [r7, #12]
|
|
80078b2: 2200 movs r2, #0
|
|
80078b4: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
/* Enable TXE and ERR interrupt */
|
|
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
|
|
80078b8: 68fb ldr r3, [r7, #12]
|
|
80078ba: 681b ldr r3, [r3, #0]
|
|
80078bc: 685a ldr r2, [r3, #4]
|
|
80078be: 68fb ldr r3, [r7, #12]
|
|
80078c0: 681b ldr r3, [r3, #0]
|
|
80078c2: f042 02a0 orr.w r2, r2, #160 @ 0xa0
|
|
80078c6: 605a str r2, [r3, #4]
|
|
|
|
return HAL_OK;
|
|
80078c8: 2300 movs r3, #0
|
|
}
|
|
80078ca: 4618 mov r0, r3
|
|
80078cc: 3714 adds r7, #20
|
|
80078ce: 46bd mov sp, r7
|
|
80078d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80078d4: 4770 bx lr
|
|
80078d6: bf00 nop
|
|
80078d8: 080080d3 .word 0x080080d3
|
|
80078dc: 0800808d .word 0x0800808d
|
|
|
|
080078e0 <HAL_SPI_Receive_IT>:
|
|
* @param pData pointer to data buffer
|
|
* @param Size amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
|
|
{
|
|
80078e0: b580 push {r7, lr}
|
|
80078e2: b084 sub sp, #16
|
|
80078e4: af00 add r7, sp, #0
|
|
80078e6: 60f8 str r0, [r7, #12]
|
|
80078e8: 60b9 str r1, [r7, #8]
|
|
80078ea: 4613 mov r3, r2
|
|
80078ec: 80fb strh r3, [r7, #6]
|
|
|
|
if (hspi->State != HAL_SPI_STATE_READY)
|
|
80078ee: 68fb ldr r3, [r7, #12]
|
|
80078f0: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
80078f4: b2db uxtb r3, r3
|
|
80078f6: 2b01 cmp r3, #1
|
|
80078f8: d001 beq.n 80078fe <HAL_SPI_Receive_IT+0x1e>
|
|
{
|
|
return HAL_BUSY;
|
|
80078fa: 2302 movs r3, #2
|
|
80078fc: e092 b.n 8007a24 <HAL_SPI_Receive_IT+0x144>
|
|
}
|
|
|
|
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
|
|
80078fe: 68fb ldr r3, [r7, #12]
|
|
8007900: 689b ldr r3, [r3, #8]
|
|
8007902: 2b00 cmp r3, #0
|
|
8007904: d110 bne.n 8007928 <HAL_SPI_Receive_IT+0x48>
|
|
8007906: 68fb ldr r3, [r7, #12]
|
|
8007908: 685b ldr r3, [r3, #4]
|
|
800790a: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800790e: d10b bne.n 8007928 <HAL_SPI_Receive_IT+0x48>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_BUSY_RX;
|
|
8007910: 68fb ldr r3, [r7, #12]
|
|
8007912: 2204 movs r2, #4
|
|
8007914: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
|
|
return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
|
|
8007918: 88fb ldrh r3, [r7, #6]
|
|
800791a: 68ba ldr r2, [r7, #8]
|
|
800791c: 68b9 ldr r1, [r7, #8]
|
|
800791e: 68f8 ldr r0, [r7, #12]
|
|
8007920: f000 f888 bl 8007a34 <HAL_SPI_TransmitReceive_IT>
|
|
8007924: 4603 mov r3, r0
|
|
8007926: e07d b.n 8007a24 <HAL_SPI_Receive_IT+0x144>
|
|
}
|
|
|
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8007928: 68bb ldr r3, [r7, #8]
|
|
800792a: 2b00 cmp r3, #0
|
|
800792c: d002 beq.n 8007934 <HAL_SPI_Receive_IT+0x54>
|
|
800792e: 88fb ldrh r3, [r7, #6]
|
|
8007930: 2b00 cmp r3, #0
|
|
8007932: d101 bne.n 8007938 <HAL_SPI_Receive_IT+0x58>
|
|
{
|
|
return HAL_ERROR;
|
|
8007934: 2301 movs r3, #1
|
|
8007936: e075 b.n 8007a24 <HAL_SPI_Receive_IT+0x144>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hspi);
|
|
8007938: 68fb ldr r3, [r7, #12]
|
|
800793a: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
800793e: 2b01 cmp r3, #1
|
|
8007940: d101 bne.n 8007946 <HAL_SPI_Receive_IT+0x66>
|
|
8007942: 2302 movs r3, #2
|
|
8007944: e06e b.n 8007a24 <HAL_SPI_Receive_IT+0x144>
|
|
8007946: 68fb ldr r3, [r7, #12]
|
|
8007948: 2201 movs r2, #1
|
|
800794a: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set the transaction information */
|
|
hspi->State = HAL_SPI_STATE_BUSY_RX;
|
|
800794e: 68fb ldr r3, [r7, #12]
|
|
8007950: 2204 movs r2, #4
|
|
8007952: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8007956: 68fb ldr r3, [r7, #12]
|
|
8007958: 2200 movs r2, #0
|
|
800795a: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pRxBuffPtr = (uint8_t *)pData;
|
|
800795c: 68fb ldr r3, [r7, #12]
|
|
800795e: 68ba ldr r2, [r7, #8]
|
|
8007960: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferSize = Size;
|
|
8007962: 68fb ldr r3, [r7, #12]
|
|
8007964: 88fa ldrh r2, [r7, #6]
|
|
8007966: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->RxXferCount = Size;
|
|
800796a: 68fb ldr r3, [r7, #12]
|
|
800796c: 88fa ldrh r2, [r7, #6]
|
|
800796e: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Init field not used in handle to zero */
|
|
hspi->pTxBuffPtr = (uint8_t *)NULL;
|
|
8007972: 68fb ldr r3, [r7, #12]
|
|
8007974: 2200 movs r2, #0
|
|
8007976: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferSize = 0U;
|
|
8007978: 68fb ldr r3, [r7, #12]
|
|
800797a: 2200 movs r2, #0
|
|
800797c: 879a strh r2, [r3, #60] @ 0x3c
|
|
hspi->TxXferCount = 0U;
|
|
800797e: 68fb ldr r3, [r7, #12]
|
|
8007980: 2200 movs r2, #0
|
|
8007982: 87da strh r2, [r3, #62] @ 0x3e
|
|
hspi->TxISR = NULL;
|
|
8007984: 68fb ldr r3, [r7, #12]
|
|
8007986: 2200 movs r2, #0
|
|
8007988: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Check the data size to adapt Rx threshold and the set the function for IT treatment */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
800798a: 68fb ldr r3, [r7, #12]
|
|
800798c: 68db ldr r3, [r3, #12]
|
|
800798e: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8007992: d90b bls.n 80079ac <HAL_SPI_Receive_IT+0xcc>
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 16 bit */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
8007994: 68fb ldr r3, [r7, #12]
|
|
8007996: 681b ldr r3, [r3, #0]
|
|
8007998: 685a ldr r2, [r3, #4]
|
|
800799a: 68fb ldr r3, [r7, #12]
|
|
800799c: 681b ldr r3, [r3, #0]
|
|
800799e: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
80079a2: 605a str r2, [r3, #4]
|
|
hspi->RxISR = SPI_RxISR_16BIT;
|
|
80079a4: 68fb ldr r3, [r7, #12]
|
|
80079a6: 4a21 ldr r2, [pc, #132] @ (8007a2c <HAL_SPI_Receive_IT+0x14c>)
|
|
80079a8: 64da str r2, [r3, #76] @ 0x4c
|
|
80079aa: e00a b.n 80079c2 <HAL_SPI_Receive_IT+0xe2>
|
|
}
|
|
else
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 8 bit */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
80079ac: 68fb ldr r3, [r7, #12]
|
|
80079ae: 681b ldr r3, [r3, #0]
|
|
80079b0: 685a ldr r2, [r3, #4]
|
|
80079b2: 68fb ldr r3, [r7, #12]
|
|
80079b4: 681b ldr r3, [r3, #0]
|
|
80079b6: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
80079ba: 605a str r2, [r3, #4]
|
|
hspi->RxISR = SPI_RxISR_8BIT;
|
|
80079bc: 68fb ldr r3, [r7, #12]
|
|
80079be: 4a1c ldr r2, [pc, #112] @ (8007a30 <HAL_SPI_Receive_IT+0x150>)
|
|
80079c0: 64da str r2, [r3, #76] @ 0x4c
|
|
}
|
|
|
|
/* Configure communication direction : 1Line */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
80079c2: 68fb ldr r3, [r7, #12]
|
|
80079c4: 689b ldr r3, [r3, #8]
|
|
80079c6: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80079ca: d10f bne.n 80079ec <HAL_SPI_Receive_IT+0x10c>
|
|
{
|
|
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
80079cc: 68fb ldr r3, [r7, #12]
|
|
80079ce: 681b ldr r3, [r3, #0]
|
|
80079d0: 681a ldr r2, [r3, #0]
|
|
80079d2: 68fb ldr r3, [r7, #12]
|
|
80079d4: 681b ldr r3, [r3, #0]
|
|
80079d6: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
80079da: 601a str r2, [r3, #0]
|
|
SPI_1LINE_RX(hspi);
|
|
80079dc: 68fb ldr r3, [r7, #12]
|
|
80079de: 681b ldr r3, [r3, #0]
|
|
80079e0: 681a ldr r2, [r3, #0]
|
|
80079e2: 68fb ldr r3, [r7, #12]
|
|
80079e4: 681b ldr r3, [r3, #0]
|
|
80079e6: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
80079ea: 601a str r2, [r3, #0]
|
|
/* Note : The SPI must be enabled after unlocking current process
|
|
to avoid the risk of SPI interrupt handle execution before current
|
|
process unlock */
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
80079ec: 68fb ldr r3, [r7, #12]
|
|
80079ee: 681b ldr r3, [r3, #0]
|
|
80079f0: 681b ldr r3, [r3, #0]
|
|
80079f2: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80079f6: 2b40 cmp r3, #64 @ 0x40
|
|
80079f8: d007 beq.n 8007a0a <HAL_SPI_Receive_IT+0x12a>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
80079fa: 68fb ldr r3, [r7, #12]
|
|
80079fc: 681b ldr r3, [r3, #0]
|
|
80079fe: 681a ldr r2, [r3, #0]
|
|
8007a00: 68fb ldr r3, [r7, #12]
|
|
8007a02: 681b ldr r3, [r3, #0]
|
|
8007a04: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
8007a08: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
8007a0a: 68fb ldr r3, [r7, #12]
|
|
8007a0c: 2200 movs r2, #0
|
|
8007a0e: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
/* Enable RXNE and ERR interrupt */
|
|
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
|
|
8007a12: 68fb ldr r3, [r7, #12]
|
|
8007a14: 681b ldr r3, [r3, #0]
|
|
8007a16: 685a ldr r2, [r3, #4]
|
|
8007a18: 68fb ldr r3, [r7, #12]
|
|
8007a1a: 681b ldr r3, [r3, #0]
|
|
8007a1c: f042 0260 orr.w r2, r2, #96 @ 0x60
|
|
8007a20: 605a str r2, [r3, #4]
|
|
|
|
return HAL_OK;
|
|
8007a22: 2300 movs r3, #0
|
|
}
|
|
8007a24: 4618 mov r0, r3
|
|
8007a26: 3710 adds r7, #16
|
|
8007a28: 46bd mov sp, r7
|
|
8007a2a: bd80 pop {r7, pc}
|
|
8007a2c: 08008041 .word 0x08008041
|
|
8007a30: 08007ff1 .word 0x08007ff1
|
|
|
|
08007a34 <HAL_SPI_TransmitReceive_IT>:
|
|
* @param Size amount of data to be sent and received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
|
uint16_t Size)
|
|
{
|
|
8007a34: b480 push {r7}
|
|
8007a36: b087 sub sp, #28
|
|
8007a38: af00 add r7, sp, #0
|
|
8007a3a: 60f8 str r0, [r7, #12]
|
|
8007a3c: 60b9 str r1, [r7, #8]
|
|
8007a3e: 607a str r2, [r7, #4]
|
|
8007a40: 807b strh r3, [r7, #2]
|
|
|
|
/* Check Direction parameter */
|
|
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
|
|
|
|
/* Init temporary variables */
|
|
tmp_state = hspi->State;
|
|
8007a42: 68fb ldr r3, [r7, #12]
|
|
8007a44: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
8007a48: 75fb strb r3, [r7, #23]
|
|
tmp_mode = hspi->Init.Mode;
|
|
8007a4a: 68fb ldr r3, [r7, #12]
|
|
8007a4c: 685b ldr r3, [r3, #4]
|
|
8007a4e: 613b str r3, [r7, #16]
|
|
|
|
if (!((tmp_state == HAL_SPI_STATE_READY) || \
|
|
8007a50: 7dfb ldrb r3, [r7, #23]
|
|
8007a52: 2b01 cmp r3, #1
|
|
8007a54: d00c beq.n 8007a70 <HAL_SPI_TransmitReceive_IT+0x3c>
|
|
8007a56: 693b ldr r3, [r7, #16]
|
|
8007a58: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8007a5c: d106 bne.n 8007a6c <HAL_SPI_TransmitReceive_IT+0x38>
|
|
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
|
|
8007a5e: 68fb ldr r3, [r7, #12]
|
|
8007a60: 689b ldr r3, [r3, #8]
|
|
8007a62: 2b00 cmp r3, #0
|
|
8007a64: d102 bne.n 8007a6c <HAL_SPI_TransmitReceive_IT+0x38>
|
|
8007a66: 7dfb ldrb r3, [r7, #23]
|
|
8007a68: 2b04 cmp r3, #4
|
|
8007a6a: d001 beq.n 8007a70 <HAL_SPI_TransmitReceive_IT+0x3c>
|
|
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
|
|
{
|
|
return HAL_BUSY;
|
|
8007a6c: 2302 movs r3, #2
|
|
8007a6e: e07d b.n 8007b6c <HAL_SPI_TransmitReceive_IT+0x138>
|
|
}
|
|
|
|
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
|
|
8007a70: 68bb ldr r3, [r7, #8]
|
|
8007a72: 2b00 cmp r3, #0
|
|
8007a74: d005 beq.n 8007a82 <HAL_SPI_TransmitReceive_IT+0x4e>
|
|
8007a76: 687b ldr r3, [r7, #4]
|
|
8007a78: 2b00 cmp r3, #0
|
|
8007a7a: d002 beq.n 8007a82 <HAL_SPI_TransmitReceive_IT+0x4e>
|
|
8007a7c: 887b ldrh r3, [r7, #2]
|
|
8007a7e: 2b00 cmp r3, #0
|
|
8007a80: d101 bne.n 8007a86 <HAL_SPI_TransmitReceive_IT+0x52>
|
|
{
|
|
return HAL_ERROR;
|
|
8007a82: 2301 movs r3, #1
|
|
8007a84: e072 b.n 8007b6c <HAL_SPI_TransmitReceive_IT+0x138>
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hspi);
|
|
8007a86: 68fb ldr r3, [r7, #12]
|
|
8007a88: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
8007a8c: 2b01 cmp r3, #1
|
|
8007a8e: d101 bne.n 8007a94 <HAL_SPI_TransmitReceive_IT+0x60>
|
|
8007a90: 2302 movs r3, #2
|
|
8007a92: e06b b.n 8007b6c <HAL_SPI_TransmitReceive_IT+0x138>
|
|
8007a94: 68fb ldr r3, [r7, #12]
|
|
8007a96: 2201 movs r2, #1
|
|
8007a98: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
|
|
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
|
|
8007a9c: 68fb ldr r3, [r7, #12]
|
|
8007a9e: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
8007aa2: b2db uxtb r3, r3
|
|
8007aa4: 2b04 cmp r3, #4
|
|
8007aa6: d003 beq.n 8007ab0 <HAL_SPI_TransmitReceive_IT+0x7c>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
|
|
8007aa8: 68fb ldr r3, [r7, #12]
|
|
8007aaa: 2205 movs r2, #5
|
|
8007aac: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
}
|
|
|
|
/* Set the transaction information */
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8007ab0: 68fb ldr r3, [r7, #12]
|
|
8007ab2: 2200 movs r2, #0
|
|
8007ab4: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
|
|
8007ab6: 68fb ldr r3, [r7, #12]
|
|
8007ab8: 68ba ldr r2, [r7, #8]
|
|
8007aba: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferSize = Size;
|
|
8007abc: 68fb ldr r3, [r7, #12]
|
|
8007abe: 887a ldrh r2, [r7, #2]
|
|
8007ac0: 879a strh r2, [r3, #60] @ 0x3c
|
|
hspi->TxXferCount = Size;
|
|
8007ac2: 68fb ldr r3, [r7, #12]
|
|
8007ac4: 887a ldrh r2, [r7, #2]
|
|
8007ac6: 87da strh r2, [r3, #62] @ 0x3e
|
|
hspi->pRxBuffPtr = (uint8_t *)pRxData;
|
|
8007ac8: 68fb ldr r3, [r7, #12]
|
|
8007aca: 687a ldr r2, [r7, #4]
|
|
8007acc: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferSize = Size;
|
|
8007ace: 68fb ldr r3, [r7, #12]
|
|
8007ad0: 887a ldrh r2, [r7, #2]
|
|
8007ad2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->RxXferCount = Size;
|
|
8007ad6: 68fb ldr r3, [r7, #12]
|
|
8007ad8: 887a ldrh r2, [r7, #2]
|
|
8007ada: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Set the function for IT treatment */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
8007ade: 68fb ldr r3, [r7, #12]
|
|
8007ae0: 68db ldr r3, [r3, #12]
|
|
8007ae2: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8007ae6: d906 bls.n 8007af6 <HAL_SPI_TransmitReceive_IT+0xc2>
|
|
{
|
|
hspi->RxISR = SPI_2linesRxISR_16BIT;
|
|
8007ae8: 68fb ldr r3, [r7, #12]
|
|
8007aea: 4a23 ldr r2, [pc, #140] @ (8007b78 <HAL_SPI_TransmitReceive_IT+0x144>)
|
|
8007aec: 64da str r2, [r3, #76] @ 0x4c
|
|
hspi->TxISR = SPI_2linesTxISR_16BIT;
|
|
8007aee: 68fb ldr r3, [r7, #12]
|
|
8007af0: 4a22 ldr r2, [pc, #136] @ (8007b7c <HAL_SPI_TransmitReceive_IT+0x148>)
|
|
8007af2: 651a str r2, [r3, #80] @ 0x50
|
|
8007af4: e005 b.n 8007b02 <HAL_SPI_TransmitReceive_IT+0xce>
|
|
}
|
|
else
|
|
{
|
|
hspi->RxISR = SPI_2linesRxISR_8BIT;
|
|
8007af6: 68fb ldr r3, [r7, #12]
|
|
8007af8: 4a21 ldr r2, [pc, #132] @ (8007b80 <HAL_SPI_TransmitReceive_IT+0x14c>)
|
|
8007afa: 64da str r2, [r3, #76] @ 0x4c
|
|
hspi->TxISR = SPI_2linesTxISR_8BIT;
|
|
8007afc: 68fb ldr r3, [r7, #12]
|
|
8007afe: 4a21 ldr r2, [pc, #132] @ (8007b84 <HAL_SPI_TransmitReceive_IT+0x150>)
|
|
8007b00: 651a str r2, [r3, #80] @ 0x50
|
|
hspi->CRCSize = 0U;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check if packing mode is enabled and if there is more than 2 data to receive */
|
|
if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
|
|
8007b02: 68fb ldr r3, [r7, #12]
|
|
8007b04: 68db ldr r3, [r3, #12]
|
|
8007b06: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8007b0a: d802 bhi.n 8007b12 <HAL_SPI_TransmitReceive_IT+0xde>
|
|
8007b0c: 887b ldrh r3, [r7, #2]
|
|
8007b0e: 2b01 cmp r3, #1
|
|
8007b10: d908 bls.n 8007b24 <HAL_SPI_TransmitReceive_IT+0xf0>
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 16 bit */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
8007b12: 68fb ldr r3, [r7, #12]
|
|
8007b14: 681b ldr r3, [r3, #0]
|
|
8007b16: 685a ldr r2, [r3, #4]
|
|
8007b18: 68fb ldr r3, [r7, #12]
|
|
8007b1a: 681b ldr r3, [r3, #0]
|
|
8007b1c: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
8007b20: 605a str r2, [r3, #4]
|
|
8007b22: e007 b.n 8007b34 <HAL_SPI_TransmitReceive_IT+0x100>
|
|
}
|
|
else
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 8 bit */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
8007b24: 68fb ldr r3, [r7, #12]
|
|
8007b26: 681b ldr r3, [r3, #0]
|
|
8007b28: 685a ldr r2, [r3, #4]
|
|
8007b2a: 68fb ldr r3, [r7, #12]
|
|
8007b2c: 681b ldr r3, [r3, #0]
|
|
8007b2e: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
8007b32: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
8007b34: 68fb ldr r3, [r7, #12]
|
|
8007b36: 681b ldr r3, [r3, #0]
|
|
8007b38: 681b ldr r3, [r3, #0]
|
|
8007b3a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8007b3e: 2b40 cmp r3, #64 @ 0x40
|
|
8007b40: d007 beq.n 8007b52 <HAL_SPI_TransmitReceive_IT+0x11e>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
8007b42: 68fb ldr r3, [r7, #12]
|
|
8007b44: 681b ldr r3, [r3, #0]
|
|
8007b46: 681a ldr r2, [r3, #0]
|
|
8007b48: 68fb ldr r3, [r7, #12]
|
|
8007b4a: 681b ldr r3, [r3, #0]
|
|
8007b4c: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
8007b50: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
8007b52: 68fb ldr r3, [r7, #12]
|
|
8007b54: 2200 movs r2, #0
|
|
8007b56: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
/* Enable TXE, RXNE and ERR interrupt */
|
|
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
|
8007b5a: 68fb ldr r3, [r7, #12]
|
|
8007b5c: 681b ldr r3, [r3, #0]
|
|
8007b5e: 685a ldr r2, [r3, #4]
|
|
8007b60: 68fb ldr r3, [r7, #12]
|
|
8007b62: 681b ldr r3, [r3, #0]
|
|
8007b64: f042 02e0 orr.w r2, r2, #224 @ 0xe0
|
|
8007b68: 605a str r2, [r3, #4]
|
|
|
|
return HAL_OK;
|
|
8007b6a: 2300 movs r3, #0
|
|
}
|
|
8007b6c: 4618 mov r0, r3
|
|
8007b6e: 371c adds r7, #28
|
|
8007b70: 46bd mov sp, r7
|
|
8007b72: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007b76: 4770 bx lr
|
|
8007b78: 08007f2b .word 0x08007f2b
|
|
8007b7c: 08007f91 .word 0x08007f91
|
|
8007b80: 08007ddb .word 0x08007ddb
|
|
8007b84: 08007e99 .word 0x08007e99
|
|
|
|
08007b88 <HAL_SPI_IRQHandler>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for the specified SPI module.
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8007b88: b580 push {r7, lr}
|
|
8007b8a: b088 sub sp, #32
|
|
8007b8c: af00 add r7, sp, #0
|
|
8007b8e: 6078 str r0, [r7, #4]
|
|
uint32_t itsource = hspi->Instance->CR2;
|
|
8007b90: 687b ldr r3, [r7, #4]
|
|
8007b92: 681b ldr r3, [r3, #0]
|
|
8007b94: 685b ldr r3, [r3, #4]
|
|
8007b96: 61fb str r3, [r7, #28]
|
|
uint32_t itflag = hspi->Instance->SR;
|
|
8007b98: 687b ldr r3, [r7, #4]
|
|
8007b9a: 681b ldr r3, [r3, #0]
|
|
8007b9c: 689b ldr r3, [r3, #8]
|
|
8007b9e: 61bb str r3, [r7, #24]
|
|
|
|
/* SPI in mode Receiver ----------------------------------------------------*/
|
|
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
|
|
8007ba0: 69bb ldr r3, [r7, #24]
|
|
8007ba2: 099b lsrs r3, r3, #6
|
|
8007ba4: f003 0301 and.w r3, r3, #1
|
|
8007ba8: 2b00 cmp r3, #0
|
|
8007baa: d10f bne.n 8007bcc <HAL_SPI_IRQHandler+0x44>
|
|
(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
|
|
8007bac: 69bb ldr r3, [r7, #24]
|
|
8007bae: f003 0301 and.w r3, r3, #1
|
|
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
|
|
8007bb2: 2b00 cmp r3, #0
|
|
8007bb4: d00a beq.n 8007bcc <HAL_SPI_IRQHandler+0x44>
|
|
(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
|
|
8007bb6: 69fb ldr r3, [r7, #28]
|
|
8007bb8: 099b lsrs r3, r3, #6
|
|
8007bba: f003 0301 and.w r3, r3, #1
|
|
8007bbe: 2b00 cmp r3, #0
|
|
8007bc0: d004 beq.n 8007bcc <HAL_SPI_IRQHandler+0x44>
|
|
{
|
|
hspi->RxISR(hspi);
|
|
8007bc2: 687b ldr r3, [r7, #4]
|
|
8007bc4: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8007bc6: 6878 ldr r0, [r7, #4]
|
|
8007bc8: 4798 blx r3
|
|
return;
|
|
8007bca: e0d7 b.n 8007d7c <HAL_SPI_IRQHandler+0x1f4>
|
|
}
|
|
|
|
/* SPI in mode Transmitter -------------------------------------------------*/
|
|
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
|
|
8007bcc: 69bb ldr r3, [r7, #24]
|
|
8007bce: 085b lsrs r3, r3, #1
|
|
8007bd0: f003 0301 and.w r3, r3, #1
|
|
8007bd4: 2b00 cmp r3, #0
|
|
8007bd6: d00a beq.n 8007bee <HAL_SPI_IRQHandler+0x66>
|
|
8007bd8: 69fb ldr r3, [r7, #28]
|
|
8007bda: 09db lsrs r3, r3, #7
|
|
8007bdc: f003 0301 and.w r3, r3, #1
|
|
8007be0: 2b00 cmp r3, #0
|
|
8007be2: d004 beq.n 8007bee <HAL_SPI_IRQHandler+0x66>
|
|
{
|
|
hspi->TxISR(hspi);
|
|
8007be4: 687b ldr r3, [r7, #4]
|
|
8007be6: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8007be8: 6878 ldr r0, [r7, #4]
|
|
8007bea: 4798 blx r3
|
|
return;
|
|
8007bec: e0c6 b.n 8007d7c <HAL_SPI_IRQHandler+0x1f4>
|
|
}
|
|
|
|
/* SPI in Error Treatment --------------------------------------------------*/
|
|
if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
|
|
8007bee: 69bb ldr r3, [r7, #24]
|
|
8007bf0: 095b lsrs r3, r3, #5
|
|
8007bf2: f003 0301 and.w r3, r3, #1
|
|
8007bf6: 2b00 cmp r3, #0
|
|
8007bf8: d10c bne.n 8007c14 <HAL_SPI_IRQHandler+0x8c>
|
|
8007bfa: 69bb ldr r3, [r7, #24]
|
|
8007bfc: 099b lsrs r3, r3, #6
|
|
8007bfe: f003 0301 and.w r3, r3, #1
|
|
8007c02: 2b00 cmp r3, #0
|
|
8007c04: d106 bne.n 8007c14 <HAL_SPI_IRQHandler+0x8c>
|
|
|| (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
|
|
8007c06: 69bb ldr r3, [r7, #24]
|
|
8007c08: 0a1b lsrs r3, r3, #8
|
|
8007c0a: f003 0301 and.w r3, r3, #1
|
|
8007c0e: 2b00 cmp r3, #0
|
|
8007c10: f000 80b4 beq.w 8007d7c <HAL_SPI_IRQHandler+0x1f4>
|
|
8007c14: 69fb ldr r3, [r7, #28]
|
|
8007c16: 095b lsrs r3, r3, #5
|
|
8007c18: f003 0301 and.w r3, r3, #1
|
|
8007c1c: 2b00 cmp r3, #0
|
|
8007c1e: f000 80ad beq.w 8007d7c <HAL_SPI_IRQHandler+0x1f4>
|
|
{
|
|
/* SPI Overrun error interrupt occurred ----------------------------------*/
|
|
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
|
|
8007c22: 69bb ldr r3, [r7, #24]
|
|
8007c24: 099b lsrs r3, r3, #6
|
|
8007c26: f003 0301 and.w r3, r3, #1
|
|
8007c2a: 2b00 cmp r3, #0
|
|
8007c2c: d023 beq.n 8007c76 <HAL_SPI_IRQHandler+0xee>
|
|
{
|
|
if (hspi->State != HAL_SPI_STATE_BUSY_TX)
|
|
8007c2e: 687b ldr r3, [r7, #4]
|
|
8007c30: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
8007c34: b2db uxtb r3, r3
|
|
8007c36: 2b03 cmp r3, #3
|
|
8007c38: d011 beq.n 8007c5e <HAL_SPI_IRQHandler+0xd6>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
|
|
8007c3a: 687b ldr r3, [r7, #4]
|
|
8007c3c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8007c3e: f043 0204 orr.w r2, r3, #4
|
|
8007c42: 687b ldr r3, [r7, #4]
|
|
8007c44: 661a str r2, [r3, #96] @ 0x60
|
|
__HAL_SPI_CLEAR_OVRFLAG(hspi);
|
|
8007c46: 2300 movs r3, #0
|
|
8007c48: 617b str r3, [r7, #20]
|
|
8007c4a: 687b ldr r3, [r7, #4]
|
|
8007c4c: 681b ldr r3, [r3, #0]
|
|
8007c4e: 68db ldr r3, [r3, #12]
|
|
8007c50: 617b str r3, [r7, #20]
|
|
8007c52: 687b ldr r3, [r7, #4]
|
|
8007c54: 681b ldr r3, [r3, #0]
|
|
8007c56: 689b ldr r3, [r3, #8]
|
|
8007c58: 617b str r3, [r7, #20]
|
|
8007c5a: 697b ldr r3, [r7, #20]
|
|
8007c5c: e00b b.n 8007c76 <HAL_SPI_IRQHandler+0xee>
|
|
}
|
|
else
|
|
{
|
|
__HAL_SPI_CLEAR_OVRFLAG(hspi);
|
|
8007c5e: 2300 movs r3, #0
|
|
8007c60: 613b str r3, [r7, #16]
|
|
8007c62: 687b ldr r3, [r7, #4]
|
|
8007c64: 681b ldr r3, [r3, #0]
|
|
8007c66: 68db ldr r3, [r3, #12]
|
|
8007c68: 613b str r3, [r7, #16]
|
|
8007c6a: 687b ldr r3, [r7, #4]
|
|
8007c6c: 681b ldr r3, [r3, #0]
|
|
8007c6e: 689b ldr r3, [r3, #8]
|
|
8007c70: 613b str r3, [r7, #16]
|
|
8007c72: 693b ldr r3, [r7, #16]
|
|
return;
|
|
8007c74: e082 b.n 8007d7c <HAL_SPI_IRQHandler+0x1f4>
|
|
}
|
|
}
|
|
|
|
/* SPI Mode Fault error interrupt occurred -------------------------------*/
|
|
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
|
|
8007c76: 69bb ldr r3, [r7, #24]
|
|
8007c78: 095b lsrs r3, r3, #5
|
|
8007c7a: f003 0301 and.w r3, r3, #1
|
|
8007c7e: 2b00 cmp r3, #0
|
|
8007c80: d014 beq.n 8007cac <HAL_SPI_IRQHandler+0x124>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
|
|
8007c82: 687b ldr r3, [r7, #4]
|
|
8007c84: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8007c86: f043 0201 orr.w r2, r3, #1
|
|
8007c8a: 687b ldr r3, [r7, #4]
|
|
8007c8c: 661a str r2, [r3, #96] @ 0x60
|
|
__HAL_SPI_CLEAR_MODFFLAG(hspi);
|
|
8007c8e: 2300 movs r3, #0
|
|
8007c90: 60fb str r3, [r7, #12]
|
|
8007c92: 687b ldr r3, [r7, #4]
|
|
8007c94: 681b ldr r3, [r3, #0]
|
|
8007c96: 689b ldr r3, [r3, #8]
|
|
8007c98: 60fb str r3, [r7, #12]
|
|
8007c9a: 687b ldr r3, [r7, #4]
|
|
8007c9c: 681b ldr r3, [r3, #0]
|
|
8007c9e: 681a ldr r2, [r3, #0]
|
|
8007ca0: 687b ldr r3, [r7, #4]
|
|
8007ca2: 681b ldr r3, [r3, #0]
|
|
8007ca4: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8007ca8: 601a str r2, [r3, #0]
|
|
8007caa: 68fb ldr r3, [r7, #12]
|
|
}
|
|
|
|
/* SPI Frame error interrupt occurred ------------------------------------*/
|
|
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
|
|
8007cac: 69bb ldr r3, [r7, #24]
|
|
8007cae: 0a1b lsrs r3, r3, #8
|
|
8007cb0: f003 0301 and.w r3, r3, #1
|
|
8007cb4: 2b00 cmp r3, #0
|
|
8007cb6: d00c beq.n 8007cd2 <HAL_SPI_IRQHandler+0x14a>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
|
|
8007cb8: 687b ldr r3, [r7, #4]
|
|
8007cba: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8007cbc: f043 0208 orr.w r2, r3, #8
|
|
8007cc0: 687b ldr r3, [r7, #4]
|
|
8007cc2: 661a str r2, [r3, #96] @ 0x60
|
|
__HAL_SPI_CLEAR_FREFLAG(hspi);
|
|
8007cc4: 2300 movs r3, #0
|
|
8007cc6: 60bb str r3, [r7, #8]
|
|
8007cc8: 687b ldr r3, [r7, #4]
|
|
8007cca: 681b ldr r3, [r3, #0]
|
|
8007ccc: 689b ldr r3, [r3, #8]
|
|
8007cce: 60bb str r3, [r7, #8]
|
|
8007cd0: 68bb ldr r3, [r7, #8]
|
|
}
|
|
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
8007cd2: 687b ldr r3, [r7, #4]
|
|
8007cd4: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8007cd6: 2b00 cmp r3, #0
|
|
8007cd8: d04f beq.n 8007d7a <HAL_SPI_IRQHandler+0x1f2>
|
|
{
|
|
/* Disable all interrupts */
|
|
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
|
|
8007cda: 687b ldr r3, [r7, #4]
|
|
8007cdc: 681b ldr r3, [r3, #0]
|
|
8007cde: 685a ldr r2, [r3, #4]
|
|
8007ce0: 687b ldr r3, [r7, #4]
|
|
8007ce2: 681b ldr r3, [r3, #0]
|
|
8007ce4: f022 02e0 bic.w r2, r2, #224 @ 0xe0
|
|
8007ce8: 605a str r2, [r3, #4]
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8007cea: 687b ldr r3, [r7, #4]
|
|
8007cec: 2201 movs r2, #1
|
|
8007cee: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Disable the SPI DMA requests if enabled */
|
|
if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
|
|
8007cf2: 69fb ldr r3, [r7, #28]
|
|
8007cf4: f003 0302 and.w r3, r3, #2
|
|
8007cf8: 2b00 cmp r3, #0
|
|
8007cfa: d104 bne.n 8007d06 <HAL_SPI_IRQHandler+0x17e>
|
|
8007cfc: 69fb ldr r3, [r7, #28]
|
|
8007cfe: f003 0301 and.w r3, r3, #1
|
|
8007d02: 2b00 cmp r3, #0
|
|
8007d04: d034 beq.n 8007d70 <HAL_SPI_IRQHandler+0x1e8>
|
|
{
|
|
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
|
|
8007d06: 687b ldr r3, [r7, #4]
|
|
8007d08: 681b ldr r3, [r3, #0]
|
|
8007d0a: 685a ldr r2, [r3, #4]
|
|
8007d0c: 687b ldr r3, [r7, #4]
|
|
8007d0e: 681b ldr r3, [r3, #0]
|
|
8007d10: f022 0203 bic.w r2, r2, #3
|
|
8007d14: 605a str r2, [r3, #4]
|
|
|
|
/* Abort the SPI DMA Rx channel */
|
|
if (hspi->hdmarx != NULL)
|
|
8007d16: 687b ldr r3, [r7, #4]
|
|
8007d18: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8007d1a: 2b00 cmp r3, #0
|
|
8007d1c: d011 beq.n 8007d42 <HAL_SPI_IRQHandler+0x1ba>
|
|
{
|
|
/* Set the SPI DMA Abort callback :
|
|
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
|
|
hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
|
|
8007d1e: 687b ldr r3, [r7, #4]
|
|
8007d20: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8007d22: 4a18 ldr r2, [pc, #96] @ (8007d84 <HAL_SPI_IRQHandler+0x1fc>)
|
|
8007d24: 639a str r2, [r3, #56] @ 0x38
|
|
if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
|
|
8007d26: 687b ldr r3, [r7, #4]
|
|
8007d28: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8007d2a: 4618 mov r0, r3
|
|
8007d2c: f7fc fa44 bl 80041b8 <HAL_DMA_Abort_IT>
|
|
8007d30: 4603 mov r3, r0
|
|
8007d32: 2b00 cmp r3, #0
|
|
8007d34: d005 beq.n 8007d42 <HAL_SPI_IRQHandler+0x1ba>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
|
|
8007d36: 687b ldr r3, [r7, #4]
|
|
8007d38: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8007d3a: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8007d3e: 687b ldr r3, [r7, #4]
|
|
8007d40: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
}
|
|
/* Abort the SPI DMA Tx channel */
|
|
if (hspi->hdmatx != NULL)
|
|
8007d42: 687b ldr r3, [r7, #4]
|
|
8007d44: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8007d46: 2b00 cmp r3, #0
|
|
8007d48: d016 beq.n 8007d78 <HAL_SPI_IRQHandler+0x1f0>
|
|
{
|
|
/* Set the SPI DMA Abort callback :
|
|
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
|
|
hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
|
|
8007d4a: 687b ldr r3, [r7, #4]
|
|
8007d4c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8007d4e: 4a0d ldr r2, [pc, #52] @ (8007d84 <HAL_SPI_IRQHandler+0x1fc>)
|
|
8007d50: 639a str r2, [r3, #56] @ 0x38
|
|
if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
|
|
8007d52: 687b ldr r3, [r7, #4]
|
|
8007d54: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8007d56: 4618 mov r0, r3
|
|
8007d58: f7fc fa2e bl 80041b8 <HAL_DMA_Abort_IT>
|
|
8007d5c: 4603 mov r3, r0
|
|
8007d5e: 2b00 cmp r3, #0
|
|
8007d60: d00a beq.n 8007d78 <HAL_SPI_IRQHandler+0x1f0>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
|
|
8007d62: 687b ldr r3, [r7, #4]
|
|
8007d64: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8007d66: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8007d6a: 687b ldr r3, [r7, #4]
|
|
8007d6c: 661a str r2, [r3, #96] @ 0x60
|
|
if (hspi->hdmatx != NULL)
|
|
8007d6e: e003 b.n 8007d78 <HAL_SPI_IRQHandler+0x1f0>
|
|
{
|
|
/* Call user error callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->ErrorCallback(hspi);
|
|
#else
|
|
HAL_SPI_ErrorCallback(hspi);
|
|
8007d70: 6878 ldr r0, [r7, #4]
|
|
8007d72: f000 f813 bl 8007d9c <HAL_SPI_ErrorCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
return;
|
|
8007d76: e000 b.n 8007d7a <HAL_SPI_IRQHandler+0x1f2>
|
|
if (hspi->hdmatx != NULL)
|
|
8007d78: bf00 nop
|
|
return;
|
|
8007d7a: bf00 nop
|
|
}
|
|
}
|
|
8007d7c: 3720 adds r7, #32
|
|
8007d7e: 46bd mov sp, r7
|
|
8007d80: bd80 pop {r7, pc}
|
|
8007d82: bf00 nop
|
|
8007d84: 08007db1 .word 0x08007db1
|
|
|
|
08007d88 <HAL_SPI_TxRxCpltCallback>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8007d88: b480 push {r7}
|
|
8007d8a: b083 sub sp, #12
|
|
8007d8c: af00 add r7, sp, #0
|
|
8007d8e: 6078 str r0, [r7, #4]
|
|
UNUSED(hspi);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_SPI_TxRxCpltCallback should be implemented in the user file
|
|
*/
|
|
}
|
|
8007d90: bf00 nop
|
|
8007d92: 370c adds r7, #12
|
|
8007d94: 46bd mov sp, r7
|
|
8007d96: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d9a: 4770 bx lr
|
|
|
|
08007d9c <HAL_SPI_ErrorCallback>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8007d9c: b480 push {r7}
|
|
8007d9e: b083 sub sp, #12
|
|
8007da0: af00 add r7, sp, #0
|
|
8007da2: 6078 str r0, [r7, #4]
|
|
the HAL_SPI_ErrorCallback should be implemented in the user file
|
|
*/
|
|
/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
|
|
and user can use HAL_SPI_GetError() API to check the latest error occurred
|
|
*/
|
|
}
|
|
8007da4: bf00 nop
|
|
8007da6: 370c adds r7, #12
|
|
8007da8: 46bd mov sp, r7
|
|
8007daa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007dae: 4770 bx lr
|
|
|
|
08007db0 <SPI_DMAAbortOnError>:
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8007db0: b580 push {r7, lr}
|
|
8007db2: b084 sub sp, #16
|
|
8007db4: af00 add r7, sp, #0
|
|
8007db6: 6078 str r0, [r7, #4]
|
|
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
8007db8: 687b ldr r3, [r7, #4]
|
|
8007dba: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8007dbc: 60fb str r3, [r7, #12]
|
|
hspi->RxXferCount = 0U;
|
|
8007dbe: 68fb ldr r3, [r7, #12]
|
|
8007dc0: 2200 movs r2, #0
|
|
8007dc2: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->TxXferCount = 0U;
|
|
8007dc6: 68fb ldr r3, [r7, #12]
|
|
8007dc8: 2200 movs r2, #0
|
|
8007dca: 87da strh r2, [r3, #62] @ 0x3e
|
|
|
|
/* Call user error callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->ErrorCallback(hspi);
|
|
#else
|
|
HAL_SPI_ErrorCallback(hspi);
|
|
8007dcc: 68f8 ldr r0, [r7, #12]
|
|
8007dce: f7ff ffe5 bl 8007d9c <HAL_SPI_ErrorCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
8007dd2: bf00 nop
|
|
8007dd4: 3710 adds r7, #16
|
|
8007dd6: 46bd mov sp, r7
|
|
8007dd8: bd80 pop {r7, pc}
|
|
|
|
08007dda <SPI_2linesRxISR_8BIT>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|
{
|
|
8007dda: b580 push {r7, lr}
|
|
8007ddc: b082 sub sp, #8
|
|
8007dde: af00 add r7, sp, #0
|
|
8007de0: 6078 str r0, [r7, #4]
|
|
/* Receive data in packing mode */
|
|
if (hspi->RxXferCount > 1U)
|
|
8007de2: 687b ldr r3, [r7, #4]
|
|
8007de4: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007de8: b29b uxth r3, r3
|
|
8007dea: 2b01 cmp r3, #1
|
|
8007dec: d923 bls.n 8007e36 <SPI_2linesRxISR_8BIT+0x5c>
|
|
{
|
|
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
|
|
8007dee: 687b ldr r3, [r7, #4]
|
|
8007df0: 681b ldr r3, [r3, #0]
|
|
8007df2: 68da ldr r2, [r3, #12]
|
|
8007df4: 687b ldr r3, [r7, #4]
|
|
8007df6: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007df8: b292 uxth r2, r2
|
|
8007dfa: 801a strh r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint16_t);
|
|
8007dfc: 687b ldr r3, [r7, #4]
|
|
8007dfe: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007e00: 1c9a adds r2, r3, #2
|
|
8007e02: 687b ldr r3, [r7, #4]
|
|
8007e04: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount -= 2U;
|
|
8007e06: 687b ldr r3, [r7, #4]
|
|
8007e08: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007e0c: b29b uxth r3, r3
|
|
8007e0e: 3b02 subs r3, #2
|
|
8007e10: b29a uxth r2, r3
|
|
8007e12: 687b ldr r3, [r7, #4]
|
|
8007e14: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
if (hspi->RxXferCount == 1U)
|
|
8007e18: 687b ldr r3, [r7, #4]
|
|
8007e1a: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007e1e: b29b uxth r3, r3
|
|
8007e20: 2b01 cmp r3, #1
|
|
8007e22: d11f bne.n 8007e64 <SPI_2linesRxISR_8BIT+0x8a>
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 8bit */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
8007e24: 687b ldr r3, [r7, #4]
|
|
8007e26: 681b ldr r3, [r3, #0]
|
|
8007e28: 685a ldr r2, [r3, #4]
|
|
8007e2a: 687b ldr r3, [r7, #4]
|
|
8007e2c: 681b ldr r3, [r3, #0]
|
|
8007e2e: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
8007e32: 605a str r2, [r3, #4]
|
|
8007e34: e016 b.n 8007e64 <SPI_2linesRxISR_8BIT+0x8a>
|
|
}
|
|
}
|
|
/* Receive data in 8 Bit mode */
|
|
else
|
|
{
|
|
*hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
|
|
8007e36: 687b ldr r3, [r7, #4]
|
|
8007e38: 681b ldr r3, [r3, #0]
|
|
8007e3a: f103 020c add.w r2, r3, #12
|
|
8007e3e: 687b ldr r3, [r7, #4]
|
|
8007e40: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007e42: 7812 ldrb r2, [r2, #0]
|
|
8007e44: b2d2 uxtb r2, r2
|
|
8007e46: 701a strb r2, [r3, #0]
|
|
hspi->pRxBuffPtr++;
|
|
8007e48: 687b ldr r3, [r7, #4]
|
|
8007e4a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007e4c: 1c5a adds r2, r3, #1
|
|
8007e4e: 687b ldr r3, [r7, #4]
|
|
8007e50: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
8007e52: 687b ldr r3, [r7, #4]
|
|
8007e54: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007e58: b29b uxth r3, r3
|
|
8007e5a: 3b01 subs r3, #1
|
|
8007e5c: b29a uxth r2, r3
|
|
8007e5e: 687b ldr r3, [r7, #4]
|
|
8007e60: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
}
|
|
|
|
/* Check end of the reception */
|
|
if (hspi->RxXferCount == 0U)
|
|
8007e64: 687b ldr r3, [r7, #4]
|
|
8007e66: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007e6a: b29b uxth r3, r3
|
|
8007e6c: 2b00 cmp r3, #0
|
|
8007e6e: d10f bne.n 8007e90 <SPI_2linesRxISR_8BIT+0xb6>
|
|
return;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Disable RXNE and ERR interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
|
|
8007e70: 687b ldr r3, [r7, #4]
|
|
8007e72: 681b ldr r3, [r3, #0]
|
|
8007e74: 685a ldr r2, [r3, #4]
|
|
8007e76: 687b ldr r3, [r7, #4]
|
|
8007e78: 681b ldr r3, [r3, #0]
|
|
8007e7a: f022 0260 bic.w r2, r2, #96 @ 0x60
|
|
8007e7e: 605a str r2, [r3, #4]
|
|
|
|
if (hspi->TxXferCount == 0U)
|
|
8007e80: 687b ldr r3, [r7, #4]
|
|
8007e82: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007e84: b29b uxth r3, r3
|
|
8007e86: 2b00 cmp r3, #0
|
|
8007e88: d102 bne.n 8007e90 <SPI_2linesRxISR_8BIT+0xb6>
|
|
{
|
|
SPI_CloseRxTx_ISR(hspi);
|
|
8007e8a: 6878 ldr r0, [r7, #4]
|
|
8007e8c: f000 fb00 bl 8008490 <SPI_CloseRxTx_ISR>
|
|
}
|
|
}
|
|
}
|
|
8007e90: bf00 nop
|
|
8007e92: 3708 adds r7, #8
|
|
8007e94: 46bd mov sp, r7
|
|
8007e96: bd80 pop {r7, pc}
|
|
|
|
08007e98 <SPI_2linesTxISR_8BIT>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|
{
|
|
8007e98: b580 push {r7, lr}
|
|
8007e9a: b082 sub sp, #8
|
|
8007e9c: af00 add r7, sp, #0
|
|
8007e9e: 6078 str r0, [r7, #4]
|
|
/* Transmit data in packing Bit mode */
|
|
if (hspi->TxXferCount >= 2U)
|
|
8007ea0: 687b ldr r3, [r7, #4]
|
|
8007ea2: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007ea4: b29b uxth r3, r3
|
|
8007ea6: 2b01 cmp r3, #1
|
|
8007ea8: d912 bls.n 8007ed0 <SPI_2linesTxISR_8BIT+0x38>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
8007eaa: 687b ldr r3, [r7, #4]
|
|
8007eac: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007eae: 881a ldrh r2, [r3, #0]
|
|
8007eb0: 687b ldr r3, [r7, #4]
|
|
8007eb2: 681b ldr r3, [r3, #0]
|
|
8007eb4: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
8007eb6: 687b ldr r3, [r7, #4]
|
|
8007eb8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007eba: 1c9a adds r2, r3, #2
|
|
8007ebc: 687b ldr r3, [r7, #4]
|
|
8007ebe: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
8007ec0: 687b ldr r3, [r7, #4]
|
|
8007ec2: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007ec4: b29b uxth r3, r3
|
|
8007ec6: 3b02 subs r3, #2
|
|
8007ec8: b29a uxth r2, r3
|
|
8007eca: 687b ldr r3, [r7, #4]
|
|
8007ecc: 87da strh r2, [r3, #62] @ 0x3e
|
|
8007ece: e012 b.n 8007ef6 <SPI_2linesTxISR_8BIT+0x5e>
|
|
}
|
|
/* Transmit data in 8 Bit mode */
|
|
else
|
|
{
|
|
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
8007ed0: 687b ldr r3, [r7, #4]
|
|
8007ed2: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8007ed4: 687b ldr r3, [r7, #4]
|
|
8007ed6: 681b ldr r3, [r3, #0]
|
|
8007ed8: 330c adds r3, #12
|
|
8007eda: 7812 ldrb r2, [r2, #0]
|
|
8007edc: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr++;
|
|
8007ede: 687b ldr r3, [r7, #4]
|
|
8007ee0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007ee2: 1c5a adds r2, r3, #1
|
|
8007ee4: 687b ldr r3, [r7, #4]
|
|
8007ee6: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
8007ee8: 687b ldr r3, [r7, #4]
|
|
8007eea: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007eec: b29b uxth r3, r3
|
|
8007eee: 3b01 subs r3, #1
|
|
8007ef0: b29a uxth r2, r3
|
|
8007ef2: 687b ldr r3, [r7, #4]
|
|
8007ef4: 87da strh r2, [r3, #62] @ 0x3e
|
|
}
|
|
|
|
/* Check the end of the transmission */
|
|
if (hspi->TxXferCount == 0U)
|
|
8007ef6: 687b ldr r3, [r7, #4]
|
|
8007ef8: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007efa: b29b uxth r3, r3
|
|
8007efc: 2b00 cmp r3, #0
|
|
8007efe: d110 bne.n 8007f22 <SPI_2linesTxISR_8BIT+0x8a>
|
|
return;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Disable TXE interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
|
|
8007f00: 687b ldr r3, [r7, #4]
|
|
8007f02: 681b ldr r3, [r3, #0]
|
|
8007f04: 685a ldr r2, [r3, #4]
|
|
8007f06: 687b ldr r3, [r7, #4]
|
|
8007f08: 681b ldr r3, [r3, #0]
|
|
8007f0a: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8007f0e: 605a str r2, [r3, #4]
|
|
|
|
if (hspi->RxXferCount == 0U)
|
|
8007f10: 687b ldr r3, [r7, #4]
|
|
8007f12: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007f16: b29b uxth r3, r3
|
|
8007f18: 2b00 cmp r3, #0
|
|
8007f1a: d102 bne.n 8007f22 <SPI_2linesTxISR_8BIT+0x8a>
|
|
{
|
|
SPI_CloseRxTx_ISR(hspi);
|
|
8007f1c: 6878 ldr r0, [r7, #4]
|
|
8007f1e: f000 fab7 bl 8008490 <SPI_CloseRxTx_ISR>
|
|
}
|
|
}
|
|
}
|
|
8007f22: bf00 nop
|
|
8007f24: 3708 adds r7, #8
|
|
8007f26: 46bd mov sp, r7
|
|
8007f28: bd80 pop {r7, pc}
|
|
|
|
08007f2a <SPI_2linesRxISR_16BIT>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|
{
|
|
8007f2a: b580 push {r7, lr}
|
|
8007f2c: b082 sub sp, #8
|
|
8007f2e: af00 add r7, sp, #0
|
|
8007f30: 6078 str r0, [r7, #4]
|
|
/* Receive data in 16 Bit mode */
|
|
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
|
|
8007f32: 687b ldr r3, [r7, #4]
|
|
8007f34: 681b ldr r3, [r3, #0]
|
|
8007f36: 68da ldr r2, [r3, #12]
|
|
8007f38: 687b ldr r3, [r7, #4]
|
|
8007f3a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007f3c: b292 uxth r2, r2
|
|
8007f3e: 801a strh r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint16_t);
|
|
8007f40: 687b ldr r3, [r7, #4]
|
|
8007f42: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007f44: 1c9a adds r2, r3, #2
|
|
8007f46: 687b ldr r3, [r7, #4]
|
|
8007f48: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
8007f4a: 687b ldr r3, [r7, #4]
|
|
8007f4c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007f50: b29b uxth r3, r3
|
|
8007f52: 3b01 subs r3, #1
|
|
8007f54: b29a uxth r2, r3
|
|
8007f56: 687b ldr r3, [r7, #4]
|
|
8007f58: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
|
|
if (hspi->RxXferCount == 0U)
|
|
8007f5c: 687b ldr r3, [r7, #4]
|
|
8007f5e: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007f62: b29b uxth r3, r3
|
|
8007f64: 2b00 cmp r3, #0
|
|
8007f66: d10f bne.n 8007f88 <SPI_2linesRxISR_16BIT+0x5e>
|
|
return;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Disable RXNE interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
|
|
8007f68: 687b ldr r3, [r7, #4]
|
|
8007f6a: 681b ldr r3, [r3, #0]
|
|
8007f6c: 685a ldr r2, [r3, #4]
|
|
8007f6e: 687b ldr r3, [r7, #4]
|
|
8007f70: 681b ldr r3, [r3, #0]
|
|
8007f72: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8007f76: 605a str r2, [r3, #4]
|
|
|
|
if (hspi->TxXferCount == 0U)
|
|
8007f78: 687b ldr r3, [r7, #4]
|
|
8007f7a: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007f7c: b29b uxth r3, r3
|
|
8007f7e: 2b00 cmp r3, #0
|
|
8007f80: d102 bne.n 8007f88 <SPI_2linesRxISR_16BIT+0x5e>
|
|
{
|
|
SPI_CloseRxTx_ISR(hspi);
|
|
8007f82: 6878 ldr r0, [r7, #4]
|
|
8007f84: f000 fa84 bl 8008490 <SPI_CloseRxTx_ISR>
|
|
}
|
|
}
|
|
}
|
|
8007f88: bf00 nop
|
|
8007f8a: 3708 adds r7, #8
|
|
8007f8c: 46bd mov sp, r7
|
|
8007f8e: bd80 pop {r7, pc}
|
|
|
|
08007f90 <SPI_2linesTxISR_16BIT>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|
{
|
|
8007f90: b580 push {r7, lr}
|
|
8007f92: b082 sub sp, #8
|
|
8007f94: af00 add r7, sp, #0
|
|
8007f96: 6078 str r0, [r7, #4]
|
|
/* Transmit data in 16 Bit mode */
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
8007f98: 687b ldr r3, [r7, #4]
|
|
8007f9a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007f9c: 881a ldrh r2, [r3, #0]
|
|
8007f9e: 687b ldr r3, [r7, #4]
|
|
8007fa0: 681b ldr r3, [r3, #0]
|
|
8007fa2: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
8007fa4: 687b ldr r3, [r7, #4]
|
|
8007fa6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007fa8: 1c9a adds r2, r3, #2
|
|
8007faa: 687b ldr r3, [r7, #4]
|
|
8007fac: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
8007fae: 687b ldr r3, [r7, #4]
|
|
8007fb0: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007fb2: b29b uxth r3, r3
|
|
8007fb4: 3b01 subs r3, #1
|
|
8007fb6: b29a uxth r2, r3
|
|
8007fb8: 687b ldr r3, [r7, #4]
|
|
8007fba: 87da strh r2, [r3, #62] @ 0x3e
|
|
|
|
/* Enable CRC Transmission */
|
|
if (hspi->TxXferCount == 0U)
|
|
8007fbc: 687b ldr r3, [r7, #4]
|
|
8007fbe: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8007fc0: b29b uxth r3, r3
|
|
8007fc2: 2b00 cmp r3, #0
|
|
8007fc4: d110 bne.n 8007fe8 <SPI_2linesTxISR_16BIT+0x58>
|
|
return;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Disable TXE interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
|
|
8007fc6: 687b ldr r3, [r7, #4]
|
|
8007fc8: 681b ldr r3, [r3, #0]
|
|
8007fca: 685a ldr r2, [r3, #4]
|
|
8007fcc: 687b ldr r3, [r7, #4]
|
|
8007fce: 681b ldr r3, [r3, #0]
|
|
8007fd0: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8007fd4: 605a str r2, [r3, #4]
|
|
|
|
if (hspi->RxXferCount == 0U)
|
|
8007fd6: 687b ldr r3, [r7, #4]
|
|
8007fd8: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8007fdc: b29b uxth r3, r3
|
|
8007fde: 2b00 cmp r3, #0
|
|
8007fe0: d102 bne.n 8007fe8 <SPI_2linesTxISR_16BIT+0x58>
|
|
{
|
|
SPI_CloseRxTx_ISR(hspi);
|
|
8007fe2: 6878 ldr r0, [r7, #4]
|
|
8007fe4: f000 fa54 bl 8008490 <SPI_CloseRxTx_ISR>
|
|
}
|
|
}
|
|
}
|
|
8007fe8: bf00 nop
|
|
8007fea: 3708 adds r7, #8
|
|
8007fec: 46bd mov sp, r7
|
|
8007fee: bd80 pop {r7, pc}
|
|
|
|
08007ff0 <SPI_RxISR_8BIT>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|
{
|
|
8007ff0: b580 push {r7, lr}
|
|
8007ff2: b082 sub sp, #8
|
|
8007ff4: af00 add r7, sp, #0
|
|
8007ff6: 6078 str r0, [r7, #4]
|
|
*hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
|
|
8007ff8: 687b ldr r3, [r7, #4]
|
|
8007ffa: 681b ldr r3, [r3, #0]
|
|
8007ffc: f103 020c add.w r2, r3, #12
|
|
8008000: 687b ldr r3, [r7, #4]
|
|
8008002: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8008004: 7812 ldrb r2, [r2, #0]
|
|
8008006: b2d2 uxtb r2, r2
|
|
8008008: 701a strb r2, [r3, #0]
|
|
hspi->pRxBuffPtr++;
|
|
800800a: 687b ldr r3, [r7, #4]
|
|
800800c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800800e: 1c5a adds r2, r3, #1
|
|
8008010: 687b ldr r3, [r7, #4]
|
|
8008012: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
8008014: 687b ldr r3, [r7, #4]
|
|
8008016: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800801a: b29b uxth r3, r3
|
|
800801c: 3b01 subs r3, #1
|
|
800801e: b29a uxth r2, r3
|
|
8008020: 687b ldr r3, [r7, #4]
|
|
8008022: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
{
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->RxXferCount == 0U)
|
|
8008026: 687b ldr r3, [r7, #4]
|
|
8008028: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800802c: b29b uxth r3, r3
|
|
800802e: 2b00 cmp r3, #0
|
|
8008030: d102 bne.n 8008038 <SPI_RxISR_8BIT+0x48>
|
|
{
|
|
hspi->RxISR = SPI_RxISR_8BITCRC;
|
|
return;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
SPI_CloseRx_ISR(hspi);
|
|
8008032: 6878 ldr r0, [r7, #4]
|
|
8008034: f000 fa6e bl 8008514 <SPI_CloseRx_ISR>
|
|
}
|
|
}
|
|
8008038: bf00 nop
|
|
800803a: 3708 adds r7, #8
|
|
800803c: 46bd mov sp, r7
|
|
800803e: bd80 pop {r7, pc}
|
|
|
|
08008040 <SPI_RxISR_16BIT>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|
{
|
|
8008040: b580 push {r7, lr}
|
|
8008042: b082 sub sp, #8
|
|
8008044: af00 add r7, sp, #0
|
|
8008046: 6078 str r0, [r7, #4]
|
|
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
|
|
8008048: 687b ldr r3, [r7, #4]
|
|
800804a: 681b ldr r3, [r3, #0]
|
|
800804c: 68da ldr r2, [r3, #12]
|
|
800804e: 687b ldr r3, [r7, #4]
|
|
8008050: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8008052: b292 uxth r2, r2
|
|
8008054: 801a strh r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint16_t);
|
|
8008056: 687b ldr r3, [r7, #4]
|
|
8008058: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800805a: 1c9a adds r2, r3, #2
|
|
800805c: 687b ldr r3, [r7, #4]
|
|
800805e: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
8008060: 687b ldr r3, [r7, #4]
|
|
8008062: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8008066: b29b uxth r3, r3
|
|
8008068: 3b01 subs r3, #1
|
|
800806a: b29a uxth r2, r3
|
|
800806c: 687b ldr r3, [r7, #4]
|
|
800806e: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
{
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->RxXferCount == 0U)
|
|
8008072: 687b ldr r3, [r7, #4]
|
|
8008074: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
8008078: b29b uxth r3, r3
|
|
800807a: 2b00 cmp r3, #0
|
|
800807c: d102 bne.n 8008084 <SPI_RxISR_16BIT+0x44>
|
|
{
|
|
hspi->RxISR = SPI_RxISR_16BITCRC;
|
|
return;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
SPI_CloseRx_ISR(hspi);
|
|
800807e: 6878 ldr r0, [r7, #4]
|
|
8008080: f000 fa48 bl 8008514 <SPI_CloseRx_ISR>
|
|
}
|
|
}
|
|
8008084: bf00 nop
|
|
8008086: 3708 adds r7, #8
|
|
8008088: 46bd mov sp, r7
|
|
800808a: bd80 pop {r7, pc}
|
|
|
|
0800808c <SPI_TxISR_8BIT>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|
{
|
|
800808c: b580 push {r7, lr}
|
|
800808e: b082 sub sp, #8
|
|
8008090: af00 add r7, sp, #0
|
|
8008092: 6078 str r0, [r7, #4]
|
|
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
8008094: 687b ldr r3, [r7, #4]
|
|
8008096: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8008098: 687b ldr r3, [r7, #4]
|
|
800809a: 681b ldr r3, [r3, #0]
|
|
800809c: 330c adds r3, #12
|
|
800809e: 7812 ldrb r2, [r2, #0]
|
|
80080a0: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr++;
|
|
80080a2: 687b ldr r3, [r7, #4]
|
|
80080a4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80080a6: 1c5a adds r2, r3, #1
|
|
80080a8: 687b ldr r3, [r7, #4]
|
|
80080aa: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
80080ac: 687b ldr r3, [r7, #4]
|
|
80080ae: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80080b0: b29b uxth r3, r3
|
|
80080b2: 3b01 subs r3, #1
|
|
80080b4: b29a uxth r2, r3
|
|
80080b6: 687b ldr r3, [r7, #4]
|
|
80080b8: 87da strh r2, [r3, #62] @ 0x3e
|
|
|
|
if (hspi->TxXferCount == 0U)
|
|
80080ba: 687b ldr r3, [r7, #4]
|
|
80080bc: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80080be: b29b uxth r3, r3
|
|
80080c0: 2b00 cmp r3, #0
|
|
80080c2: d102 bne.n 80080ca <SPI_TxISR_8BIT+0x3e>
|
|
{
|
|
/* Enable CRC Transmission */
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
SPI_CloseTx_ISR(hspi);
|
|
80080c4: 6878 ldr r0, [r7, #4]
|
|
80080c6: f000 fa55 bl 8008574 <SPI_CloseTx_ISR>
|
|
}
|
|
}
|
|
80080ca: bf00 nop
|
|
80080cc: 3708 adds r7, #8
|
|
80080ce: 46bd mov sp, r7
|
|
80080d0: bd80 pop {r7, pc}
|
|
|
|
080080d2 <SPI_TxISR_16BIT>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|
{
|
|
80080d2: b580 push {r7, lr}
|
|
80080d4: b082 sub sp, #8
|
|
80080d6: af00 add r7, sp, #0
|
|
80080d8: 6078 str r0, [r7, #4]
|
|
/* Transmit data in 16 Bit mode */
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
80080da: 687b ldr r3, [r7, #4]
|
|
80080dc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80080de: 881a ldrh r2, [r3, #0]
|
|
80080e0: 687b ldr r3, [r7, #4]
|
|
80080e2: 681b ldr r3, [r3, #0]
|
|
80080e4: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
80080e6: 687b ldr r3, [r7, #4]
|
|
80080e8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80080ea: 1c9a adds r2, r3, #2
|
|
80080ec: 687b ldr r3, [r7, #4]
|
|
80080ee: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
80080f0: 687b ldr r3, [r7, #4]
|
|
80080f2: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80080f4: b29b uxth r3, r3
|
|
80080f6: 3b01 subs r3, #1
|
|
80080f8: b29a uxth r2, r3
|
|
80080fa: 687b ldr r3, [r7, #4]
|
|
80080fc: 87da strh r2, [r3, #62] @ 0x3e
|
|
|
|
if (hspi->TxXferCount == 0U)
|
|
80080fe: 687b ldr r3, [r7, #4]
|
|
8008100: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8008102: b29b uxth r3, r3
|
|
8008104: 2b00 cmp r3, #0
|
|
8008106: d102 bne.n 800810e <SPI_TxISR_16BIT+0x3c>
|
|
{
|
|
/* Enable CRC Transmission */
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
SPI_CloseTx_ISR(hspi);
|
|
8008108: 6878 ldr r0, [r7, #4]
|
|
800810a: f000 fa33 bl 8008574 <SPI_CloseTx_ISR>
|
|
}
|
|
}
|
|
800810e: bf00 nop
|
|
8008110: 3708 adds r7, #8
|
|
8008112: 46bd mov sp, r7
|
|
8008114: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008118 <SPI_WaitFlagStateUntilTimeout>:
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8008118: b580 push {r7, lr}
|
|
800811a: b088 sub sp, #32
|
|
800811c: af00 add r7, sp, #0
|
|
800811e: 60f8 str r0, [r7, #12]
|
|
8008120: 60b9 str r1, [r7, #8]
|
|
8008122: 603b str r3, [r7, #0]
|
|
8008124: 4613 mov r3, r2
|
|
8008126: 71fb strb r3, [r7, #7]
|
|
__IO uint32_t count;
|
|
uint32_t tmp_timeout;
|
|
uint32_t tmp_tickstart;
|
|
|
|
/* Adjust Timeout value in case of end of transfer */
|
|
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
|
8008128: f7fb fdea bl 8003d00 <HAL_GetTick>
|
|
800812c: 4602 mov r2, r0
|
|
800812e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8008130: 1a9b subs r3, r3, r2
|
|
8008132: 683a ldr r2, [r7, #0]
|
|
8008134: 4413 add r3, r2
|
|
8008136: 61fb str r3, [r7, #28]
|
|
tmp_tickstart = HAL_GetTick();
|
|
8008138: f7fb fde2 bl 8003d00 <HAL_GetTick>
|
|
800813c: 61b8 str r0, [r7, #24]
|
|
|
|
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
|
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
|
|
800813e: 4b39 ldr r3, [pc, #228] @ (8008224 <SPI_WaitFlagStateUntilTimeout+0x10c>)
|
|
8008140: 681b ldr r3, [r3, #0]
|
|
8008142: 015b lsls r3, r3, #5
|
|
8008144: 0d1b lsrs r3, r3, #20
|
|
8008146: 69fa ldr r2, [r7, #28]
|
|
8008148: fb02 f303 mul.w r3, r2, r3
|
|
800814c: 617b str r3, [r7, #20]
|
|
|
|
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
|
800814e: e054 b.n 80081fa <SPI_WaitFlagStateUntilTimeout+0xe2>
|
|
{
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8008150: 683b ldr r3, [r7, #0]
|
|
8008152: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8008156: d050 beq.n 80081fa <SPI_WaitFlagStateUntilTimeout+0xe2>
|
|
{
|
|
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
|
8008158: f7fb fdd2 bl 8003d00 <HAL_GetTick>
|
|
800815c: 4602 mov r2, r0
|
|
800815e: 69bb ldr r3, [r7, #24]
|
|
8008160: 1ad3 subs r3, r2, r3
|
|
8008162: 69fa ldr r2, [r7, #28]
|
|
8008164: 429a cmp r2, r3
|
|
8008166: d902 bls.n 800816e <SPI_WaitFlagStateUntilTimeout+0x56>
|
|
8008168: 69fb ldr r3, [r7, #28]
|
|
800816a: 2b00 cmp r3, #0
|
|
800816c: d13d bne.n 80081ea <SPI_WaitFlagStateUntilTimeout+0xd2>
|
|
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
|
on both master and slave sides in order to resynchronize the master
|
|
and slave for their respective CRC calculation */
|
|
|
|
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
|
800816e: 68fb ldr r3, [r7, #12]
|
|
8008170: 681b ldr r3, [r3, #0]
|
|
8008172: 685a ldr r2, [r3, #4]
|
|
8008174: 68fb ldr r3, [r7, #12]
|
|
8008176: 681b ldr r3, [r3, #0]
|
|
8008178: f022 02e0 bic.w r2, r2, #224 @ 0xe0
|
|
800817c: 605a str r2, [r3, #4]
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
800817e: 68fb ldr r3, [r7, #12]
|
|
8008180: 685b ldr r3, [r3, #4]
|
|
8008182: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8008186: d111 bne.n 80081ac <SPI_WaitFlagStateUntilTimeout+0x94>
|
|
8008188: 68fb ldr r3, [r7, #12]
|
|
800818a: 689b ldr r3, [r3, #8]
|
|
800818c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8008190: d004 beq.n 800819c <SPI_WaitFlagStateUntilTimeout+0x84>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
8008192: 68fb ldr r3, [r7, #12]
|
|
8008194: 689b ldr r3, [r3, #8]
|
|
8008196: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800819a: d107 bne.n 80081ac <SPI_WaitFlagStateUntilTimeout+0x94>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800819c: 68fb ldr r3, [r7, #12]
|
|
800819e: 681b ldr r3, [r3, #0]
|
|
80081a0: 681a ldr r2, [r3, #0]
|
|
80081a2: 68fb ldr r3, [r7, #12]
|
|
80081a4: 681b ldr r3, [r3, #0]
|
|
80081a6: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
80081aa: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Reset CRC Calculation */
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
80081ac: 68fb ldr r3, [r7, #12]
|
|
80081ae: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80081b0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
80081b4: d10f bne.n 80081d6 <SPI_WaitFlagStateUntilTimeout+0xbe>
|
|
{
|
|
SPI_RESET_CRC(hspi);
|
|
80081b6: 68fb ldr r3, [r7, #12]
|
|
80081b8: 681b ldr r3, [r3, #0]
|
|
80081ba: 681a ldr r2, [r3, #0]
|
|
80081bc: 68fb ldr r3, [r7, #12]
|
|
80081be: 681b ldr r3, [r3, #0]
|
|
80081c0: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
80081c4: 601a str r2, [r3, #0]
|
|
80081c6: 68fb ldr r3, [r7, #12]
|
|
80081c8: 681b ldr r3, [r3, #0]
|
|
80081ca: 681a ldr r2, [r3, #0]
|
|
80081cc: 68fb ldr r3, [r7, #12]
|
|
80081ce: 681b ldr r3, [r3, #0]
|
|
80081d0: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
80081d4: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80081d6: 68fb ldr r3, [r7, #12]
|
|
80081d8: 2201 movs r2, #1
|
|
80081da: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
80081de: 68fb ldr r3, [r7, #12]
|
|
80081e0: 2200 movs r2, #0
|
|
80081e2: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
return HAL_TIMEOUT;
|
|
80081e6: 2303 movs r3, #3
|
|
80081e8: e017 b.n 800821a <SPI_WaitFlagStateUntilTimeout+0x102>
|
|
}
|
|
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
|
if (count == 0U)
|
|
80081ea: 697b ldr r3, [r7, #20]
|
|
80081ec: 2b00 cmp r3, #0
|
|
80081ee: d101 bne.n 80081f4 <SPI_WaitFlagStateUntilTimeout+0xdc>
|
|
{
|
|
tmp_timeout = 0U;
|
|
80081f0: 2300 movs r3, #0
|
|
80081f2: 61fb str r3, [r7, #28]
|
|
}
|
|
count--;
|
|
80081f4: 697b ldr r3, [r7, #20]
|
|
80081f6: 3b01 subs r3, #1
|
|
80081f8: 617b str r3, [r7, #20]
|
|
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
|
80081fa: 68fb ldr r3, [r7, #12]
|
|
80081fc: 681b ldr r3, [r3, #0]
|
|
80081fe: 689a ldr r2, [r3, #8]
|
|
8008200: 68bb ldr r3, [r7, #8]
|
|
8008202: 4013 ands r3, r2
|
|
8008204: 68ba ldr r2, [r7, #8]
|
|
8008206: 429a cmp r2, r3
|
|
8008208: bf0c ite eq
|
|
800820a: 2301 moveq r3, #1
|
|
800820c: 2300 movne r3, #0
|
|
800820e: b2db uxtb r3, r3
|
|
8008210: 461a mov r2, r3
|
|
8008212: 79fb ldrb r3, [r7, #7]
|
|
8008214: 429a cmp r2, r3
|
|
8008216: d19b bne.n 8008150 <SPI_WaitFlagStateUntilTimeout+0x38>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8008218: 2300 movs r3, #0
|
|
}
|
|
800821a: 4618 mov r0, r3
|
|
800821c: 3720 adds r7, #32
|
|
800821e: 46bd mov sp, r7
|
|
8008220: bd80 pop {r7, pc}
|
|
8008222: bf00 nop
|
|
8008224: 200000c4 .word 0x200000c4
|
|
|
|
08008228 <SPI_WaitFifoStateUntilTimeout>:
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8008228: b580 push {r7, lr}
|
|
800822a: b08a sub sp, #40 @ 0x28
|
|
800822c: af00 add r7, sp, #0
|
|
800822e: 60f8 str r0, [r7, #12]
|
|
8008230: 60b9 str r1, [r7, #8]
|
|
8008232: 607a str r2, [r7, #4]
|
|
8008234: 603b str r3, [r7, #0]
|
|
__IO uint32_t count;
|
|
uint32_t tmp_timeout;
|
|
uint32_t tmp_tickstart;
|
|
__IO const uint8_t *ptmpreg8;
|
|
__IO uint8_t tmpreg8 = 0;
|
|
8008236: 2300 movs r3, #0
|
|
8008238: 75fb strb r3, [r7, #23]
|
|
|
|
/* Adjust Timeout value in case of end of transfer */
|
|
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
|
800823a: f7fb fd61 bl 8003d00 <HAL_GetTick>
|
|
800823e: 4602 mov r2, r0
|
|
8008240: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8008242: 1a9b subs r3, r3, r2
|
|
8008244: 683a ldr r2, [r7, #0]
|
|
8008246: 4413 add r3, r2
|
|
8008248: 627b str r3, [r7, #36] @ 0x24
|
|
tmp_tickstart = HAL_GetTick();
|
|
800824a: f7fb fd59 bl 8003d00 <HAL_GetTick>
|
|
800824e: 6238 str r0, [r7, #32]
|
|
|
|
/* Initialize the 8bit temporary pointer */
|
|
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
|
8008250: 68fb ldr r3, [r7, #12]
|
|
8008252: 681b ldr r3, [r3, #0]
|
|
8008254: 330c adds r3, #12
|
|
8008256: 61fb str r3, [r7, #28]
|
|
|
|
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
|
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
|
|
8008258: 4b3d ldr r3, [pc, #244] @ (8008350 <SPI_WaitFifoStateUntilTimeout+0x128>)
|
|
800825a: 681a ldr r2, [r3, #0]
|
|
800825c: 4613 mov r3, r2
|
|
800825e: 009b lsls r3, r3, #2
|
|
8008260: 4413 add r3, r2
|
|
8008262: 00da lsls r2, r3, #3
|
|
8008264: 1ad3 subs r3, r2, r3
|
|
8008266: 0d1b lsrs r3, r3, #20
|
|
8008268: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800826a: fb02 f303 mul.w r3, r2, r3
|
|
800826e: 61bb str r3, [r7, #24]
|
|
|
|
while ((hspi->Instance->SR & Fifo) != State)
|
|
8008270: e060 b.n 8008334 <SPI_WaitFifoStateUntilTimeout+0x10c>
|
|
{
|
|
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
|
|
8008272: 68bb ldr r3, [r7, #8]
|
|
8008274: f5b3 6fc0 cmp.w r3, #1536 @ 0x600
|
|
8008278: d107 bne.n 800828a <SPI_WaitFifoStateUntilTimeout+0x62>
|
|
800827a: 687b ldr r3, [r7, #4]
|
|
800827c: 2b00 cmp r3, #0
|
|
800827e: d104 bne.n 800828a <SPI_WaitFifoStateUntilTimeout+0x62>
|
|
{
|
|
/* Flush Data Register by a blank read */
|
|
tmpreg8 = *ptmpreg8;
|
|
8008280: 69fb ldr r3, [r7, #28]
|
|
8008282: 781b ldrb r3, [r3, #0]
|
|
8008284: b2db uxtb r3, r3
|
|
8008286: 75fb strb r3, [r7, #23]
|
|
/* To avoid GCC warning */
|
|
UNUSED(tmpreg8);
|
|
8008288: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800828a: 683b ldr r3, [r7, #0]
|
|
800828c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8008290: d050 beq.n 8008334 <SPI_WaitFifoStateUntilTimeout+0x10c>
|
|
{
|
|
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
|
8008292: f7fb fd35 bl 8003d00 <HAL_GetTick>
|
|
8008296: 4602 mov r2, r0
|
|
8008298: 6a3b ldr r3, [r7, #32]
|
|
800829a: 1ad3 subs r3, r2, r3
|
|
800829c: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800829e: 429a cmp r2, r3
|
|
80082a0: d902 bls.n 80082a8 <SPI_WaitFifoStateUntilTimeout+0x80>
|
|
80082a2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80082a4: 2b00 cmp r3, #0
|
|
80082a6: d13d bne.n 8008324 <SPI_WaitFifoStateUntilTimeout+0xfc>
|
|
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
|
on both master and slave sides in order to resynchronize the master
|
|
and slave for their respective CRC calculation */
|
|
|
|
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
|
80082a8: 68fb ldr r3, [r7, #12]
|
|
80082aa: 681b ldr r3, [r3, #0]
|
|
80082ac: 685a ldr r2, [r3, #4]
|
|
80082ae: 68fb ldr r3, [r7, #12]
|
|
80082b0: 681b ldr r3, [r3, #0]
|
|
80082b2: f022 02e0 bic.w r2, r2, #224 @ 0xe0
|
|
80082b6: 605a str r2, [r3, #4]
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
80082b8: 68fb ldr r3, [r7, #12]
|
|
80082ba: 685b ldr r3, [r3, #4]
|
|
80082bc: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
80082c0: d111 bne.n 80082e6 <SPI_WaitFifoStateUntilTimeout+0xbe>
|
|
80082c2: 68fb ldr r3, [r7, #12]
|
|
80082c4: 689b ldr r3, [r3, #8]
|
|
80082c6: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80082ca: d004 beq.n 80082d6 <SPI_WaitFifoStateUntilTimeout+0xae>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
80082cc: 68fb ldr r3, [r7, #12]
|
|
80082ce: 689b ldr r3, [r3, #8]
|
|
80082d0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80082d4: d107 bne.n 80082e6 <SPI_WaitFifoStateUntilTimeout+0xbe>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
80082d6: 68fb ldr r3, [r7, #12]
|
|
80082d8: 681b ldr r3, [r3, #0]
|
|
80082da: 681a ldr r2, [r3, #0]
|
|
80082dc: 68fb ldr r3, [r7, #12]
|
|
80082de: 681b ldr r3, [r3, #0]
|
|
80082e0: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
80082e4: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Reset CRC Calculation */
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
80082e6: 68fb ldr r3, [r7, #12]
|
|
80082e8: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80082ea: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
80082ee: d10f bne.n 8008310 <SPI_WaitFifoStateUntilTimeout+0xe8>
|
|
{
|
|
SPI_RESET_CRC(hspi);
|
|
80082f0: 68fb ldr r3, [r7, #12]
|
|
80082f2: 681b ldr r3, [r3, #0]
|
|
80082f4: 681a ldr r2, [r3, #0]
|
|
80082f6: 68fb ldr r3, [r7, #12]
|
|
80082f8: 681b ldr r3, [r3, #0]
|
|
80082fa: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
80082fe: 601a str r2, [r3, #0]
|
|
8008300: 68fb ldr r3, [r7, #12]
|
|
8008302: 681b ldr r3, [r3, #0]
|
|
8008304: 681a ldr r2, [r3, #0]
|
|
8008306: 68fb ldr r3, [r7, #12]
|
|
8008308: 681b ldr r3, [r3, #0]
|
|
800830a: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
800830e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8008310: 68fb ldr r3, [r7, #12]
|
|
8008312: 2201 movs r2, #1
|
|
8008314: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
8008318: 68fb ldr r3, [r7, #12]
|
|
800831a: 2200 movs r2, #0
|
|
800831c: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
return HAL_TIMEOUT;
|
|
8008320: 2303 movs r3, #3
|
|
8008322: e010 b.n 8008346 <SPI_WaitFifoStateUntilTimeout+0x11e>
|
|
}
|
|
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
|
if (count == 0U)
|
|
8008324: 69bb ldr r3, [r7, #24]
|
|
8008326: 2b00 cmp r3, #0
|
|
8008328: d101 bne.n 800832e <SPI_WaitFifoStateUntilTimeout+0x106>
|
|
{
|
|
tmp_timeout = 0U;
|
|
800832a: 2300 movs r3, #0
|
|
800832c: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
count--;
|
|
800832e: 69bb ldr r3, [r7, #24]
|
|
8008330: 3b01 subs r3, #1
|
|
8008332: 61bb str r3, [r7, #24]
|
|
while ((hspi->Instance->SR & Fifo) != State)
|
|
8008334: 68fb ldr r3, [r7, #12]
|
|
8008336: 681b ldr r3, [r3, #0]
|
|
8008338: 689a ldr r2, [r3, #8]
|
|
800833a: 68bb ldr r3, [r7, #8]
|
|
800833c: 4013 ands r3, r2
|
|
800833e: 687a ldr r2, [r7, #4]
|
|
8008340: 429a cmp r2, r3
|
|
8008342: d196 bne.n 8008272 <SPI_WaitFifoStateUntilTimeout+0x4a>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8008344: 2300 movs r3, #0
|
|
}
|
|
8008346: 4618 mov r0, r3
|
|
8008348: 3728 adds r7, #40 @ 0x28
|
|
800834a: 46bd mov sp, r7
|
|
800834c: bd80 pop {r7, pc}
|
|
800834e: bf00 nop
|
|
8008350: 200000c4 .word 0x200000c4
|
|
|
|
08008354 <SPI_EndRxTransaction>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8008354: b580 push {r7, lr}
|
|
8008356: b086 sub sp, #24
|
|
8008358: af02 add r7, sp, #8
|
|
800835a: 60f8 str r0, [r7, #12]
|
|
800835c: 60b9 str r1, [r7, #8]
|
|
800835e: 607a str r2, [r7, #4]
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
8008360: 68fb ldr r3, [r7, #12]
|
|
8008362: 685b ldr r3, [r3, #4]
|
|
8008364: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8008368: d111 bne.n 800838e <SPI_EndRxTransaction+0x3a>
|
|
800836a: 68fb ldr r3, [r7, #12]
|
|
800836c: 689b ldr r3, [r3, #8]
|
|
800836e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8008372: d004 beq.n 800837e <SPI_EndRxTransaction+0x2a>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
8008374: 68fb ldr r3, [r7, #12]
|
|
8008376: 689b ldr r3, [r3, #8]
|
|
8008378: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800837c: d107 bne.n 800838e <SPI_EndRxTransaction+0x3a>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800837e: 68fb ldr r3, [r7, #12]
|
|
8008380: 681b ldr r3, [r3, #0]
|
|
8008382: 681a ldr r2, [r3, #0]
|
|
8008384: 68fb ldr r3, [r7, #12]
|
|
8008386: 681b ldr r3, [r3, #0]
|
|
8008388: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800838c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
|
|
800838e: 687b ldr r3, [r7, #4]
|
|
8008390: 9300 str r3, [sp, #0]
|
|
8008392: 68bb ldr r3, [r7, #8]
|
|
8008394: 2200 movs r2, #0
|
|
8008396: 2180 movs r1, #128 @ 0x80
|
|
8008398: 68f8 ldr r0, [r7, #12]
|
|
800839a: f7ff febd bl 8008118 <SPI_WaitFlagStateUntilTimeout>
|
|
800839e: 4603 mov r3, r0
|
|
80083a0: 2b00 cmp r3, #0
|
|
80083a2: d007 beq.n 80083b4 <SPI_EndRxTransaction+0x60>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
80083a4: 68fb ldr r3, [r7, #12]
|
|
80083a6: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80083a8: f043 0220 orr.w r2, r3, #32
|
|
80083ac: 68fb ldr r3, [r7, #12]
|
|
80083ae: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
80083b0: 2303 movs r3, #3
|
|
80083b2: e023 b.n 80083fc <SPI_EndRxTransaction+0xa8>
|
|
}
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
80083b4: 68fb ldr r3, [r7, #12]
|
|
80083b6: 685b ldr r3, [r3, #4]
|
|
80083b8: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
80083bc: d11d bne.n 80083fa <SPI_EndRxTransaction+0xa6>
|
|
80083be: 68fb ldr r3, [r7, #12]
|
|
80083c0: 689b ldr r3, [r3, #8]
|
|
80083c2: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80083c6: d004 beq.n 80083d2 <SPI_EndRxTransaction+0x7e>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
80083c8: 68fb ldr r3, [r7, #12]
|
|
80083ca: 689b ldr r3, [r3, #8]
|
|
80083cc: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80083d0: d113 bne.n 80083fa <SPI_EndRxTransaction+0xa6>
|
|
{
|
|
/* Empty the FRLVL fifo */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
|
|
80083d2: 687b ldr r3, [r7, #4]
|
|
80083d4: 9300 str r3, [sp, #0]
|
|
80083d6: 68bb ldr r3, [r7, #8]
|
|
80083d8: 2200 movs r2, #0
|
|
80083da: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
80083de: 68f8 ldr r0, [r7, #12]
|
|
80083e0: f7ff ff22 bl 8008228 <SPI_WaitFifoStateUntilTimeout>
|
|
80083e4: 4603 mov r3, r0
|
|
80083e6: 2b00 cmp r3, #0
|
|
80083e8: d007 beq.n 80083fa <SPI_EndRxTransaction+0xa6>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
80083ea: 68fb ldr r3, [r7, #12]
|
|
80083ec: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80083ee: f043 0220 orr.w r2, r3, #32
|
|
80083f2: 68fb ldr r3, [r7, #12]
|
|
80083f4: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
80083f6: 2303 movs r3, #3
|
|
80083f8: e000 b.n 80083fc <SPI_EndRxTransaction+0xa8>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80083fa: 2300 movs r3, #0
|
|
}
|
|
80083fc: 4618 mov r0, r3
|
|
80083fe: 3710 adds r7, #16
|
|
8008400: 46bd mov sp, r7
|
|
8008402: bd80 pop {r7, pc}
|
|
|
|
08008404 <SPI_EndRxTxTransaction>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8008404: b580 push {r7, lr}
|
|
8008406: b086 sub sp, #24
|
|
8008408: af02 add r7, sp, #8
|
|
800840a: 60f8 str r0, [r7, #12]
|
|
800840c: 60b9 str r1, [r7, #8]
|
|
800840e: 607a str r2, [r7, #4]
|
|
/* Control if the TX fifo is empty */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
|
|
8008410: 687b ldr r3, [r7, #4]
|
|
8008412: 9300 str r3, [sp, #0]
|
|
8008414: 68bb ldr r3, [r7, #8]
|
|
8008416: 2200 movs r2, #0
|
|
8008418: f44f 51c0 mov.w r1, #6144 @ 0x1800
|
|
800841c: 68f8 ldr r0, [r7, #12]
|
|
800841e: f7ff ff03 bl 8008228 <SPI_WaitFifoStateUntilTimeout>
|
|
8008422: 4603 mov r3, r0
|
|
8008424: 2b00 cmp r3, #0
|
|
8008426: d007 beq.n 8008438 <SPI_EndRxTxTransaction+0x34>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
8008428: 68fb ldr r3, [r7, #12]
|
|
800842a: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800842c: f043 0220 orr.w r2, r3, #32
|
|
8008430: 68fb ldr r3, [r7, #12]
|
|
8008432: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
8008434: 2303 movs r3, #3
|
|
8008436: e027 b.n 8008488 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8008438: 687b ldr r3, [r7, #4]
|
|
800843a: 9300 str r3, [sp, #0]
|
|
800843c: 68bb ldr r3, [r7, #8]
|
|
800843e: 2200 movs r2, #0
|
|
8008440: 2180 movs r1, #128 @ 0x80
|
|
8008442: 68f8 ldr r0, [r7, #12]
|
|
8008444: f7ff fe68 bl 8008118 <SPI_WaitFlagStateUntilTimeout>
|
|
8008448: 4603 mov r3, r0
|
|
800844a: 2b00 cmp r3, #0
|
|
800844c: d007 beq.n 800845e <SPI_EndRxTxTransaction+0x5a>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
800844e: 68fb ldr r3, [r7, #12]
|
|
8008450: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8008452: f043 0220 orr.w r2, r3, #32
|
|
8008456: 68fb ldr r3, [r7, #12]
|
|
8008458: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
800845a: 2303 movs r3, #3
|
|
800845c: e014 b.n 8008488 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
/* Control if the RX fifo is empty */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
|
|
800845e: 687b ldr r3, [r7, #4]
|
|
8008460: 9300 str r3, [sp, #0]
|
|
8008462: 68bb ldr r3, [r7, #8]
|
|
8008464: 2200 movs r2, #0
|
|
8008466: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800846a: 68f8 ldr r0, [r7, #12]
|
|
800846c: f7ff fedc bl 8008228 <SPI_WaitFifoStateUntilTimeout>
|
|
8008470: 4603 mov r3, r0
|
|
8008472: 2b00 cmp r3, #0
|
|
8008474: d007 beq.n 8008486 <SPI_EndRxTxTransaction+0x82>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
8008476: 68fb ldr r3, [r7, #12]
|
|
8008478: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800847a: f043 0220 orr.w r2, r3, #32
|
|
800847e: 68fb ldr r3, [r7, #12]
|
|
8008480: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
8008482: 2303 movs r3, #3
|
|
8008484: e000 b.n 8008488 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8008486: 2300 movs r3, #0
|
|
}
|
|
8008488: 4618 mov r0, r3
|
|
800848a: 3710 adds r7, #16
|
|
800848c: 46bd mov sp, r7
|
|
800848e: bd80 pop {r7, pc}
|
|
|
|
08008490 <SPI_CloseRxTx_ISR>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8008490: b580 push {r7, lr}
|
|
8008492: b084 sub sp, #16
|
|
8008494: af00 add r7, sp, #0
|
|
8008496: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8008498: f7fb fc32 bl 8003d00 <HAL_GetTick>
|
|
800849c: 60f8 str r0, [r7, #12]
|
|
|
|
/* Disable ERR interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
|
|
800849e: 687b ldr r3, [r7, #4]
|
|
80084a0: 681b ldr r3, [r3, #0]
|
|
80084a2: 685a ldr r2, [r3, #4]
|
|
80084a4: 687b ldr r3, [r7, #4]
|
|
80084a6: 681b ldr r3, [r3, #0]
|
|
80084a8: f022 0220 bic.w r2, r2, #32
|
|
80084ac: 605a str r2, [r3, #4]
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
|
|
80084ae: 68fa ldr r2, [r7, #12]
|
|
80084b0: 2164 movs r1, #100 @ 0x64
|
|
80084b2: 6878 ldr r0, [r7, #4]
|
|
80084b4: f7ff ffa6 bl 8008404 <SPI_EndRxTxTransaction>
|
|
80084b8: 4603 mov r3, r0
|
|
80084ba: 2b00 cmp r3, #0
|
|
80084bc: d005 beq.n 80084ca <SPI_CloseRxTx_ISR+0x3a>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
80084be: 687b ldr r3, [r7, #4]
|
|
80084c0: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80084c2: f043 0220 orr.w r2, r3, #32
|
|
80084c6: 687b ldr r3, [r7, #4]
|
|
80084c8: 661a str r2, [r3, #96] @ 0x60
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
#endif /* USE_SPI_CRC */
|
|
if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
|
|
80084ca: 687b ldr r3, [r7, #4]
|
|
80084cc: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80084ce: 2b00 cmp r3, #0
|
|
80084d0: d115 bne.n 80084fe <SPI_CloseRxTx_ISR+0x6e>
|
|
{
|
|
if (hspi->State == HAL_SPI_STATE_BUSY_RX)
|
|
80084d2: 687b ldr r3, [r7, #4]
|
|
80084d4: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
80084d8: b2db uxtb r3, r3
|
|
80084da: 2b04 cmp r3, #4
|
|
80084dc: d107 bne.n 80084ee <SPI_CloseRxTx_ISR+0x5e>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80084de: 687b ldr r3, [r7, #4]
|
|
80084e0: 2201 movs r2, #1
|
|
80084e2: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Call user Rx complete callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->RxCpltCallback(hspi);
|
|
#else
|
|
HAL_SPI_RxCpltCallback(hspi);
|
|
80084e6: 6878 ldr r0, [r7, #4]
|
|
80084e8: f003 fcda bl 800bea0 <HAL_SPI_RxCpltCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
#if (USE_SPI_CRC != 0U)
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
}
|
|
80084ec: e00e b.n 800850c <SPI_CloseRxTx_ISR+0x7c>
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80084ee: 687b ldr r3, [r7, #4]
|
|
80084f0: 2201 movs r2, #1
|
|
80084f2: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
HAL_SPI_TxRxCpltCallback(hspi);
|
|
80084f6: 6878 ldr r0, [r7, #4]
|
|
80084f8: f7ff fc46 bl 8007d88 <HAL_SPI_TxRxCpltCallback>
|
|
}
|
|
80084fc: e006 b.n 800850c <SPI_CloseRxTx_ISR+0x7c>
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80084fe: 687b ldr r3, [r7, #4]
|
|
8008500: 2201 movs r2, #1
|
|
8008502: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
HAL_SPI_ErrorCallback(hspi);
|
|
8008506: 6878 ldr r0, [r7, #4]
|
|
8008508: f7ff fc48 bl 8007d9c <HAL_SPI_ErrorCallback>
|
|
}
|
|
800850c: bf00 nop
|
|
800850e: 3710 adds r7, #16
|
|
8008510: 46bd mov sp, r7
|
|
8008512: bd80 pop {r7, pc}
|
|
|
|
08008514 <SPI_CloseRx_ISR>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8008514: b580 push {r7, lr}
|
|
8008516: b082 sub sp, #8
|
|
8008518: af00 add r7, sp, #0
|
|
800851a: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE and ERR interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
|
|
800851c: 687b ldr r3, [r7, #4]
|
|
800851e: 681b ldr r3, [r3, #0]
|
|
8008520: 685a ldr r2, [r3, #4]
|
|
8008522: 687b ldr r3, [r7, #4]
|
|
8008524: 681b ldr r3, [r3, #0]
|
|
8008526: f022 0260 bic.w r2, r2, #96 @ 0x60
|
|
800852a: 605a str r2, [r3, #4]
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
|
|
800852c: f7fb fbe8 bl 8003d00 <HAL_GetTick>
|
|
8008530: 4603 mov r3, r0
|
|
8008532: 461a mov r2, r3
|
|
8008534: 2164 movs r1, #100 @ 0x64
|
|
8008536: 6878 ldr r0, [r7, #4]
|
|
8008538: f7ff ff0c bl 8008354 <SPI_EndRxTransaction>
|
|
800853c: 4603 mov r3, r0
|
|
800853e: 2b00 cmp r3, #0
|
|
8008540: d005 beq.n 800854e <SPI_CloseRx_ISR+0x3a>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
8008542: 687b ldr r3, [r7, #4]
|
|
8008544: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8008546: f043 0220 orr.w r2, r3, #32
|
|
800854a: 687b ldr r3, [r7, #4]
|
|
800854c: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800854e: 687b ldr r3, [r7, #4]
|
|
8008550: 2201 movs r2, #1
|
|
8008552: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
#endif /* USE_SPI_CRC */
|
|
if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
|
|
8008556: 687b ldr r3, [r7, #4]
|
|
8008558: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800855a: 2b00 cmp r3, #0
|
|
800855c: d103 bne.n 8008566 <SPI_CloseRx_ISR+0x52>
|
|
{
|
|
/* Call user Rx complete callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->RxCpltCallback(hspi);
|
|
#else
|
|
HAL_SPI_RxCpltCallback(hspi);
|
|
800855e: 6878 ldr r0, [r7, #4]
|
|
8008560: f003 fc9e bl 800bea0 <HAL_SPI_RxCpltCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
#if (USE_SPI_CRC != 0U)
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
}
|
|
8008564: e002 b.n 800856c <SPI_CloseRx_ISR+0x58>
|
|
HAL_SPI_ErrorCallback(hspi);
|
|
8008566: 6878 ldr r0, [r7, #4]
|
|
8008568: f7ff fc18 bl 8007d9c <HAL_SPI_ErrorCallback>
|
|
}
|
|
800856c: bf00 nop
|
|
800856e: 3708 adds r7, #8
|
|
8008570: 46bd mov sp, r7
|
|
8008572: bd80 pop {r7, pc}
|
|
|
|
08008574 <SPI_CloseTx_ISR>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8008574: b580 push {r7, lr}
|
|
8008576: b084 sub sp, #16
|
|
8008578: af00 add r7, sp, #0
|
|
800857a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
800857c: f7fb fbc0 bl 8003d00 <HAL_GetTick>
|
|
8008580: 60f8 str r0, [r7, #12]
|
|
|
|
/* Disable TXE and ERR interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
|
|
8008582: 687b ldr r3, [r7, #4]
|
|
8008584: 681b ldr r3, [r3, #0]
|
|
8008586: 685a ldr r2, [r3, #4]
|
|
8008588: 687b ldr r3, [r7, #4]
|
|
800858a: 681b ldr r3, [r3, #0]
|
|
800858c: f022 02a0 bic.w r2, r2, #160 @ 0xa0
|
|
8008590: 605a str r2, [r3, #4]
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
|
|
8008592: 68fa ldr r2, [r7, #12]
|
|
8008594: 2164 movs r1, #100 @ 0x64
|
|
8008596: 6878 ldr r0, [r7, #4]
|
|
8008598: f7ff ff34 bl 8008404 <SPI_EndRxTxTransaction>
|
|
800859c: 4603 mov r3, r0
|
|
800859e: 2b00 cmp r3, #0
|
|
80085a0: d005 beq.n 80085ae <SPI_CloseTx_ISR+0x3a>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
80085a2: 687b ldr r3, [r7, #4]
|
|
80085a4: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80085a6: f043 0220 orr.w r2, r3, #32
|
|
80085aa: 687b ldr r3, [r7, #4]
|
|
80085ac: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Clear overrun flag in 2 Lines communication mode because received is not read */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
|
|
80085ae: 687b ldr r3, [r7, #4]
|
|
80085b0: 689b ldr r3, [r3, #8]
|
|
80085b2: 2b00 cmp r3, #0
|
|
80085b4: d10a bne.n 80085cc <SPI_CloseTx_ISR+0x58>
|
|
{
|
|
__HAL_SPI_CLEAR_OVRFLAG(hspi);
|
|
80085b6: 2300 movs r3, #0
|
|
80085b8: 60bb str r3, [r7, #8]
|
|
80085ba: 687b ldr r3, [r7, #4]
|
|
80085bc: 681b ldr r3, [r3, #0]
|
|
80085be: 68db ldr r3, [r3, #12]
|
|
80085c0: 60bb str r3, [r7, #8]
|
|
80085c2: 687b ldr r3, [r7, #4]
|
|
80085c4: 681b ldr r3, [r3, #0]
|
|
80085c6: 689b ldr r3, [r3, #8]
|
|
80085c8: 60bb str r3, [r7, #8]
|
|
80085ca: 68bb ldr r3, [r7, #8]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80085cc: 687b ldr r3, [r7, #4]
|
|
80085ce: 2201 movs r2, #1
|
|
80085d0: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
80085d4: 687b ldr r3, [r7, #4]
|
|
80085d6: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80085d8: 2b00 cmp r3, #0
|
|
80085da: d003 beq.n 80085e4 <SPI_CloseTx_ISR+0x70>
|
|
{
|
|
/* Call user error callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->ErrorCallback(hspi);
|
|
#else
|
|
HAL_SPI_ErrorCallback(hspi);
|
|
80085dc: 6878 ldr r0, [r7, #4]
|
|
80085de: f7ff fbdd bl 8007d9c <HAL_SPI_ErrorCallback>
|
|
hspi->TxCpltCallback(hspi);
|
|
#else
|
|
HAL_SPI_TxCpltCallback(hspi);
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
80085e2: e002 b.n 80085ea <SPI_CloseTx_ISR+0x76>
|
|
HAL_SPI_TxCpltCallback(hspi);
|
|
80085e4: 6878 ldr r0, [r7, #4]
|
|
80085e6: f003 fc6f bl 800bec8 <HAL_SPI_TxCpltCallback>
|
|
}
|
|
80085ea: bf00 nop
|
|
80085ec: 3710 adds r7, #16
|
|
80085ee: 46bd mov sp, r7
|
|
80085f0: bd80 pop {r7, pc}
|
|
|
|
080085f2 <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80085f2: b580 push {r7, lr}
|
|
80085f4: b082 sub sp, #8
|
|
80085f6: af00 add r7, sp, #0
|
|
80085f8: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80085fa: 687b ldr r3, [r7, #4]
|
|
80085fc: 2b00 cmp r3, #0
|
|
80085fe: d101 bne.n 8008604 <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8008600: 2301 movs r3, #1
|
|
8008602: e049 b.n 8008698 <HAL_TIM_Base_Init+0xa6>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8008604: 687b ldr r3, [r7, #4]
|
|
8008606: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800860a: b2db uxtb r3, r3
|
|
800860c: 2b00 cmp r3, #0
|
|
800860e: d106 bne.n 800861e <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8008610: 687b ldr r3, [r7, #4]
|
|
8008612: 2200 movs r2, #0
|
|
8008614: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
8008618: 6878 ldr r0, [r7, #4]
|
|
800861a: f000 f841 bl 80086a0 <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800861e: 687b ldr r3, [r7, #4]
|
|
8008620: 2202 movs r2, #2
|
|
8008622: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8008626: 687b ldr r3, [r7, #4]
|
|
8008628: 681a ldr r2, [r3, #0]
|
|
800862a: 687b ldr r3, [r7, #4]
|
|
800862c: 3304 adds r3, #4
|
|
800862e: 4619 mov r1, r3
|
|
8008630: 4610 mov r0, r2
|
|
8008632: f000 f9df bl 80089f4 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8008636: 687b ldr r3, [r7, #4]
|
|
8008638: 2201 movs r2, #1
|
|
800863a: f883 2048 strb.w r2, [r3, #72] @ 0x48
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800863e: 687b ldr r3, [r7, #4]
|
|
8008640: 2201 movs r2, #1
|
|
8008642: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8008646: 687b ldr r3, [r7, #4]
|
|
8008648: 2201 movs r2, #1
|
|
800864a: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
800864e: 687b ldr r3, [r7, #4]
|
|
8008650: 2201 movs r2, #1
|
|
8008652: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8008656: 687b ldr r3, [r7, #4]
|
|
8008658: 2201 movs r2, #1
|
|
800865a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
800865e: 687b ldr r3, [r7, #4]
|
|
8008660: 2201 movs r2, #1
|
|
8008662: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
8008666: 687b ldr r3, [r7, #4]
|
|
8008668: 2201 movs r2, #1
|
|
800866a: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800866e: 687b ldr r3, [r7, #4]
|
|
8008670: 2201 movs r2, #1
|
|
8008672: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8008676: 687b ldr r3, [r7, #4]
|
|
8008678: 2201 movs r2, #1
|
|
800867a: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800867e: 687b ldr r3, [r7, #4]
|
|
8008680: 2201 movs r2, #1
|
|
8008682: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
8008686: 687b ldr r3, [r7, #4]
|
|
8008688: 2201 movs r2, #1
|
|
800868a: f883 2047 strb.w r2, [r3, #71] @ 0x47
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800868e: 687b ldr r3, [r7, #4]
|
|
8008690: 2201 movs r2, #1
|
|
8008692: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8008696: 2300 movs r3, #0
|
|
}
|
|
8008698: 4618 mov r0, r3
|
|
800869a: 3708 adds r7, #8
|
|
800869c: 46bd mov sp, r7
|
|
800869e: bd80 pop {r7, pc}
|
|
|
|
080086a0 <HAL_TIM_Base_MspInit>:
|
|
* @brief Initializes the TIM Base MSP.
|
|
* @param htim TIM Base handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
|
|
{
|
|
80086a0: b480 push {r7}
|
|
80086a2: b083 sub sp, #12
|
|
80086a4: af00 add r7, sp, #0
|
|
80086a6: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_Base_MspInit could be implemented in the user file
|
|
*/
|
|
}
|
|
80086a8: bf00 nop
|
|
80086aa: 370c adds r7, #12
|
|
80086ac: 46bd mov sp, r7
|
|
80086ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
80086b2: 4770 bx lr
|
|
|
|
080086b4 <HAL_TIM_Base_Start_IT>:
|
|
* @brief Starts the TIM Base generation in interrupt mode.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
|
|
{
|
|
80086b4: b480 push {r7}
|
|
80086b6: b085 sub sp, #20
|
|
80086b8: af00 add r7, sp, #0
|
|
80086ba: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Check the TIM state */
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
80086bc: 687b ldr r3, [r7, #4]
|
|
80086be: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80086c2: b2db uxtb r3, r3
|
|
80086c4: 2b01 cmp r3, #1
|
|
80086c6: d001 beq.n 80086cc <HAL_TIM_Base_Start_IT+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
80086c8: 2301 movs r3, #1
|
|
80086ca: e04f b.n 800876c <HAL_TIM_Base_Start_IT+0xb8>
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80086cc: 687b ldr r3, [r7, #4]
|
|
80086ce: 2202 movs r2, #2
|
|
80086d0: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Enable the TIM Update interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|
80086d4: 687b ldr r3, [r7, #4]
|
|
80086d6: 681b ldr r3, [r3, #0]
|
|
80086d8: 68da ldr r2, [r3, #12]
|
|
80086da: 687b ldr r3, [r7, #4]
|
|
80086dc: 681b ldr r3, [r3, #0]
|
|
80086de: f042 0201 orr.w r2, r2, #1
|
|
80086e2: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
80086e4: 687b ldr r3, [r7, #4]
|
|
80086e6: 681b ldr r3, [r3, #0]
|
|
80086e8: 4a23 ldr r2, [pc, #140] @ (8008778 <HAL_TIM_Base_Start_IT+0xc4>)
|
|
80086ea: 4293 cmp r3, r2
|
|
80086ec: d01d beq.n 800872a <HAL_TIM_Base_Start_IT+0x76>
|
|
80086ee: 687b ldr r3, [r7, #4]
|
|
80086f0: 681b ldr r3, [r3, #0]
|
|
80086f2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80086f6: d018 beq.n 800872a <HAL_TIM_Base_Start_IT+0x76>
|
|
80086f8: 687b ldr r3, [r7, #4]
|
|
80086fa: 681b ldr r3, [r3, #0]
|
|
80086fc: 4a1f ldr r2, [pc, #124] @ (800877c <HAL_TIM_Base_Start_IT+0xc8>)
|
|
80086fe: 4293 cmp r3, r2
|
|
8008700: d013 beq.n 800872a <HAL_TIM_Base_Start_IT+0x76>
|
|
8008702: 687b ldr r3, [r7, #4]
|
|
8008704: 681b ldr r3, [r3, #0]
|
|
8008706: 4a1e ldr r2, [pc, #120] @ (8008780 <HAL_TIM_Base_Start_IT+0xcc>)
|
|
8008708: 4293 cmp r3, r2
|
|
800870a: d00e beq.n 800872a <HAL_TIM_Base_Start_IT+0x76>
|
|
800870c: 687b ldr r3, [r7, #4]
|
|
800870e: 681b ldr r3, [r3, #0]
|
|
8008710: 4a1c ldr r2, [pc, #112] @ (8008784 <HAL_TIM_Base_Start_IT+0xd0>)
|
|
8008712: 4293 cmp r3, r2
|
|
8008714: d009 beq.n 800872a <HAL_TIM_Base_Start_IT+0x76>
|
|
8008716: 687b ldr r3, [r7, #4]
|
|
8008718: 681b ldr r3, [r3, #0]
|
|
800871a: 4a1b ldr r2, [pc, #108] @ (8008788 <HAL_TIM_Base_Start_IT+0xd4>)
|
|
800871c: 4293 cmp r3, r2
|
|
800871e: d004 beq.n 800872a <HAL_TIM_Base_Start_IT+0x76>
|
|
8008720: 687b ldr r3, [r7, #4]
|
|
8008722: 681b ldr r3, [r3, #0]
|
|
8008724: 4a19 ldr r2, [pc, #100] @ (800878c <HAL_TIM_Base_Start_IT+0xd8>)
|
|
8008726: 4293 cmp r3, r2
|
|
8008728: d115 bne.n 8008756 <HAL_TIM_Base_Start_IT+0xa2>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
800872a: 687b ldr r3, [r7, #4]
|
|
800872c: 681b ldr r3, [r3, #0]
|
|
800872e: 689a ldr r2, [r3, #8]
|
|
8008730: 4b17 ldr r3, [pc, #92] @ (8008790 <HAL_TIM_Base_Start_IT+0xdc>)
|
|
8008732: 4013 ands r3, r2
|
|
8008734: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8008736: 68fb ldr r3, [r7, #12]
|
|
8008738: 2b06 cmp r3, #6
|
|
800873a: d015 beq.n 8008768 <HAL_TIM_Base_Start_IT+0xb4>
|
|
800873c: 68fb ldr r3, [r7, #12]
|
|
800873e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8008742: d011 beq.n 8008768 <HAL_TIM_Base_Start_IT+0xb4>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8008744: 687b ldr r3, [r7, #4]
|
|
8008746: 681b ldr r3, [r3, #0]
|
|
8008748: 681a ldr r2, [r3, #0]
|
|
800874a: 687b ldr r3, [r7, #4]
|
|
800874c: 681b ldr r3, [r3, #0]
|
|
800874e: f042 0201 orr.w r2, r2, #1
|
|
8008752: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8008754: e008 b.n 8008768 <HAL_TIM_Base_Start_IT+0xb4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8008756: 687b ldr r3, [r7, #4]
|
|
8008758: 681b ldr r3, [r3, #0]
|
|
800875a: 681a ldr r2, [r3, #0]
|
|
800875c: 687b ldr r3, [r7, #4]
|
|
800875e: 681b ldr r3, [r3, #0]
|
|
8008760: f042 0201 orr.w r2, r2, #1
|
|
8008764: 601a str r2, [r3, #0]
|
|
8008766: e000 b.n 800876a <HAL_TIM_Base_Start_IT+0xb6>
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8008768: bf00 nop
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800876a: 2300 movs r3, #0
|
|
}
|
|
800876c: 4618 mov r0, r3
|
|
800876e: 3714 adds r7, #20
|
|
8008770: 46bd mov sp, r7
|
|
8008772: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008776: 4770 bx lr
|
|
8008778: 40012c00 .word 0x40012c00
|
|
800877c: 40000400 .word 0x40000400
|
|
8008780: 40000800 .word 0x40000800
|
|
8008784: 40000c00 .word 0x40000c00
|
|
8008788: 40013400 .word 0x40013400
|
|
800878c: 40014000 .word 0x40014000
|
|
8008790: 00010007 .word 0x00010007
|
|
|
|
08008794 <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
8008794: b580 push {r7, lr}
|
|
8008796: b084 sub sp, #16
|
|
8008798: af00 add r7, sp, #0
|
|
800879a: 6078 str r0, [r7, #4]
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
800879c: 687b ldr r3, [r7, #4]
|
|
800879e: 681b ldr r3, [r3, #0]
|
|
80087a0: 68db ldr r3, [r3, #12]
|
|
80087a2: 60fb str r3, [r7, #12]
|
|
uint32_t itflag = htim->Instance->SR;
|
|
80087a4: 687b ldr r3, [r7, #4]
|
|
80087a6: 681b ldr r3, [r3, #0]
|
|
80087a8: 691b ldr r3, [r3, #16]
|
|
80087aa: 60bb str r3, [r7, #8]
|
|
|
|
/* Capture compare 1 event */
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
80087ac: 68bb ldr r3, [r7, #8]
|
|
80087ae: f003 0302 and.w r3, r3, #2
|
|
80087b2: 2b00 cmp r3, #0
|
|
80087b4: d020 beq.n 80087f8 <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
|
80087b6: 68fb ldr r3, [r7, #12]
|
|
80087b8: f003 0302 and.w r3, r3, #2
|
|
80087bc: 2b00 cmp r3, #0
|
|
80087be: d01b beq.n 80087f8 <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
|
80087c0: 687b ldr r3, [r7, #4]
|
|
80087c2: 681b ldr r3, [r3, #0]
|
|
80087c4: f06f 0202 mvn.w r2, #2
|
|
80087c8: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
80087ca: 687b ldr r3, [r7, #4]
|
|
80087cc: 2201 movs r2, #1
|
|
80087ce: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
80087d0: 687b ldr r3, [r7, #4]
|
|
80087d2: 681b ldr r3, [r3, #0]
|
|
80087d4: 699b ldr r3, [r3, #24]
|
|
80087d6: f003 0303 and.w r3, r3, #3
|
|
80087da: 2b00 cmp r3, #0
|
|
80087dc: d003 beq.n 80087e6 <HAL_TIM_IRQHandler+0x52>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80087de: 6878 ldr r0, [r7, #4]
|
|
80087e0: f000 f8e9 bl 80089b6 <HAL_TIM_IC_CaptureCallback>
|
|
80087e4: e005 b.n 80087f2 <HAL_TIM_IRQHandler+0x5e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80087e6: 6878 ldr r0, [r7, #4]
|
|
80087e8: f000 f8db bl 80089a2 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
80087ec: 6878 ldr r0, [r7, #4]
|
|
80087ee: f000 f8ec bl 80089ca <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
80087f2: 687b ldr r3, [r7, #4]
|
|
80087f4: 2200 movs r2, #0
|
|
80087f6: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
|
80087f8: 68bb ldr r3, [r7, #8]
|
|
80087fa: f003 0304 and.w r3, r3, #4
|
|
80087fe: 2b00 cmp r3, #0
|
|
8008800: d020 beq.n 8008844 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
|
8008802: 68fb ldr r3, [r7, #12]
|
|
8008804: f003 0304 and.w r3, r3, #4
|
|
8008808: 2b00 cmp r3, #0
|
|
800880a: d01b beq.n 8008844 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
|
800880c: 687b ldr r3, [r7, #4]
|
|
800880e: 681b ldr r3, [r3, #0]
|
|
8008810: f06f 0204 mvn.w r2, #4
|
|
8008814: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
8008816: 687b ldr r3, [r7, #4]
|
|
8008818: 2202 movs r2, #2
|
|
800881a: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
800881c: 687b ldr r3, [r7, #4]
|
|
800881e: 681b ldr r3, [r3, #0]
|
|
8008820: 699b ldr r3, [r3, #24]
|
|
8008822: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8008826: 2b00 cmp r3, #0
|
|
8008828: d003 beq.n 8008832 <HAL_TIM_IRQHandler+0x9e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800882a: 6878 ldr r0, [r7, #4]
|
|
800882c: f000 f8c3 bl 80089b6 <HAL_TIM_IC_CaptureCallback>
|
|
8008830: e005 b.n 800883e <HAL_TIM_IRQHandler+0xaa>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8008832: 6878 ldr r0, [r7, #4]
|
|
8008834: f000 f8b5 bl 80089a2 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8008838: 6878 ldr r0, [r7, #4]
|
|
800883a: f000 f8c6 bl 80089ca <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800883e: 687b ldr r3, [r7, #4]
|
|
8008840: 2200 movs r2, #0
|
|
8008842: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
|
8008844: 68bb ldr r3, [r7, #8]
|
|
8008846: f003 0308 and.w r3, r3, #8
|
|
800884a: 2b00 cmp r3, #0
|
|
800884c: d020 beq.n 8008890 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
|
800884e: 68fb ldr r3, [r7, #12]
|
|
8008850: f003 0308 and.w r3, r3, #8
|
|
8008854: 2b00 cmp r3, #0
|
|
8008856: d01b beq.n 8008890 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
|
8008858: 687b ldr r3, [r7, #4]
|
|
800885a: 681b ldr r3, [r3, #0]
|
|
800885c: f06f 0208 mvn.w r2, #8
|
|
8008860: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
8008862: 687b ldr r3, [r7, #4]
|
|
8008864: 2204 movs r2, #4
|
|
8008866: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
8008868: 687b ldr r3, [r7, #4]
|
|
800886a: 681b ldr r3, [r3, #0]
|
|
800886c: 69db ldr r3, [r3, #28]
|
|
800886e: f003 0303 and.w r3, r3, #3
|
|
8008872: 2b00 cmp r3, #0
|
|
8008874: d003 beq.n 800887e <HAL_TIM_IRQHandler+0xea>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8008876: 6878 ldr r0, [r7, #4]
|
|
8008878: f000 f89d bl 80089b6 <HAL_TIM_IC_CaptureCallback>
|
|
800887c: e005 b.n 800888a <HAL_TIM_IRQHandler+0xf6>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800887e: 6878 ldr r0, [r7, #4]
|
|
8008880: f000 f88f bl 80089a2 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8008884: 6878 ldr r0, [r7, #4]
|
|
8008886: f000 f8a0 bl 80089ca <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800888a: 687b ldr r3, [r7, #4]
|
|
800888c: 2200 movs r2, #0
|
|
800888e: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
|
8008890: 68bb ldr r3, [r7, #8]
|
|
8008892: f003 0310 and.w r3, r3, #16
|
|
8008896: 2b00 cmp r3, #0
|
|
8008898: d020 beq.n 80088dc <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
|
800889a: 68fb ldr r3, [r7, #12]
|
|
800889c: f003 0310 and.w r3, r3, #16
|
|
80088a0: 2b00 cmp r3, #0
|
|
80088a2: d01b beq.n 80088dc <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
|
80088a4: 687b ldr r3, [r7, #4]
|
|
80088a6: 681b ldr r3, [r3, #0]
|
|
80088a8: f06f 0210 mvn.w r2, #16
|
|
80088ac: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
80088ae: 687b ldr r3, [r7, #4]
|
|
80088b0: 2208 movs r2, #8
|
|
80088b2: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
80088b4: 687b ldr r3, [r7, #4]
|
|
80088b6: 681b ldr r3, [r3, #0]
|
|
80088b8: 69db ldr r3, [r3, #28]
|
|
80088ba: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80088be: 2b00 cmp r3, #0
|
|
80088c0: d003 beq.n 80088ca <HAL_TIM_IRQHandler+0x136>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80088c2: 6878 ldr r0, [r7, #4]
|
|
80088c4: f000 f877 bl 80089b6 <HAL_TIM_IC_CaptureCallback>
|
|
80088c8: e005 b.n 80088d6 <HAL_TIM_IRQHandler+0x142>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80088ca: 6878 ldr r0, [r7, #4]
|
|
80088cc: f000 f869 bl 80089a2 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
80088d0: 6878 ldr r0, [r7, #4]
|
|
80088d2: f000 f87a bl 80089ca <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
80088d6: 687b ldr r3, [r7, #4]
|
|
80088d8: 2200 movs r2, #0
|
|
80088da: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
|
80088dc: 68bb ldr r3, [r7, #8]
|
|
80088de: f003 0301 and.w r3, r3, #1
|
|
80088e2: 2b00 cmp r3, #0
|
|
80088e4: d00c beq.n 8008900 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
|
80088e6: 68fb ldr r3, [r7, #12]
|
|
80088e8: f003 0301 and.w r3, r3, #1
|
|
80088ec: 2b00 cmp r3, #0
|
|
80088ee: d007 beq.n 8008900 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
80088f0: 687b ldr r3, [r7, #4]
|
|
80088f2: 681b ldr r3, [r3, #0]
|
|
80088f4: f06f 0201 mvn.w r2, #1
|
|
80088f8: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
80088fa: 6878 ldr r0, [r7, #4]
|
|
80088fc: f7fa fca6 bl 800324c <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
|
8008900: 68bb ldr r3, [r7, #8]
|
|
8008902: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8008906: 2b00 cmp r3, #0
|
|
8008908: d104 bne.n 8008914 <HAL_TIM_IRQHandler+0x180>
|
|
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
|
|
800890a: 68bb ldr r3, [r7, #8]
|
|
800890c: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
|
8008910: 2b00 cmp r3, #0
|
|
8008912: d00c beq.n 800892e <HAL_TIM_IRQHandler+0x19a>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8008914: 68fb ldr r3, [r7, #12]
|
|
8008916: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800891a: 2b00 cmp r3, #0
|
|
800891c: d007 beq.n 800892e <HAL_TIM_IRQHandler+0x19a>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
|
|
800891e: 687b ldr r3, [r7, #4]
|
|
8008920: 681b ldr r3, [r3, #0]
|
|
8008922: f46f 5202 mvn.w r2, #8320 @ 0x2080
|
|
8008926: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8008928: 6878 ldr r0, [r7, #4]
|
|
800892a: f000 f913 bl 8008b54 <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break2 input event */
|
|
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
|
|
800892e: 68bb ldr r3, [r7, #8]
|
|
8008930: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8008934: 2b00 cmp r3, #0
|
|
8008936: d00c beq.n 8008952 <HAL_TIM_IRQHandler+0x1be>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8008938: 68fb ldr r3, [r7, #12]
|
|
800893a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800893e: 2b00 cmp r3, #0
|
|
8008940: d007 beq.n 8008952 <HAL_TIM_IRQHandler+0x1be>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
|
8008942: 687b ldr r3, [r7, #4]
|
|
8008944: 681b ldr r3, [r3, #0]
|
|
8008946: f46f 7280 mvn.w r2, #256 @ 0x100
|
|
800894a: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->Break2Callback(htim);
|
|
#else
|
|
HAL_TIMEx_Break2Callback(htim);
|
|
800894c: 6878 ldr r0, [r7, #4]
|
|
800894e: f000 f90b bl 8008b68 <HAL_TIMEx_Break2Callback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Trigger detection event */
|
|
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
|
8008952: 68bb ldr r3, [r7, #8]
|
|
8008954: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8008958: 2b00 cmp r3, #0
|
|
800895a: d00c beq.n 8008976 <HAL_TIM_IRQHandler+0x1e2>
|
|
{
|
|
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
|
800895c: 68fb ldr r3, [r7, #12]
|
|
800895e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8008962: 2b00 cmp r3, #0
|
|
8008964: d007 beq.n 8008976 <HAL_TIM_IRQHandler+0x1e2>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
8008966: 687b ldr r3, [r7, #4]
|
|
8008968: 681b ldr r3, [r3, #0]
|
|
800896a: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
800896e: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
8008970: 6878 ldr r0, [r7, #4]
|
|
8008972: f000 f834 bl 80089de <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
|
8008976: 68bb ldr r3, [r7, #8]
|
|
8008978: f003 0320 and.w r3, r3, #32
|
|
800897c: 2b00 cmp r3, #0
|
|
800897e: d00c beq.n 800899a <HAL_TIM_IRQHandler+0x206>
|
|
{
|
|
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
|
8008980: 68fb ldr r3, [r7, #12]
|
|
8008982: f003 0320 and.w r3, r3, #32
|
|
8008986: 2b00 cmp r3, #0
|
|
8008988: d007 beq.n 800899a <HAL_TIM_IRQHandler+0x206>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
800898a: 687b ldr r3, [r7, #4]
|
|
800898c: 681b ldr r3, [r3, #0]
|
|
800898e: f06f 0220 mvn.w r2, #32
|
|
8008992: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
8008994: 6878 ldr r0, [r7, #4]
|
|
8008996: f000 f8d3 bl 8008b40 <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
800899a: bf00 nop
|
|
800899c: 3710 adds r7, #16
|
|
800899e: 46bd mov sp, r7
|
|
80089a0: bd80 pop {r7, pc}
|
|
|
|
080089a2 <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80089a2: b480 push {r7}
|
|
80089a4: b083 sub sp, #12
|
|
80089a6: af00 add r7, sp, #0
|
|
80089a8: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80089aa: bf00 nop
|
|
80089ac: 370c adds r7, #12
|
|
80089ae: 46bd mov sp, r7
|
|
80089b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80089b4: 4770 bx lr
|
|
|
|
080089b6 <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80089b6: b480 push {r7}
|
|
80089b8: b083 sub sp, #12
|
|
80089ba: af00 add r7, sp, #0
|
|
80089bc: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80089be: bf00 nop
|
|
80089c0: 370c adds r7, #12
|
|
80089c2: 46bd mov sp, r7
|
|
80089c4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80089c8: 4770 bx lr
|
|
|
|
080089ca <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80089ca: b480 push {r7}
|
|
80089cc: b083 sub sp, #12
|
|
80089ce: af00 add r7, sp, #0
|
|
80089d0: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80089d2: bf00 nop
|
|
80089d4: 370c adds r7, #12
|
|
80089d6: 46bd mov sp, r7
|
|
80089d8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80089dc: 4770 bx lr
|
|
|
|
080089de <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80089de: b480 push {r7}
|
|
80089e0: b083 sub sp, #12
|
|
80089e2: af00 add r7, sp, #0
|
|
80089e4: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80089e6: bf00 nop
|
|
80089e8: 370c adds r7, #12
|
|
80089ea: 46bd mov sp, r7
|
|
80089ec: f85d 7b04 ldr.w r7, [sp], #4
|
|
80089f0: 4770 bx lr
|
|
...
|
|
|
|
080089f4 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
80089f4: b480 push {r7}
|
|
80089f6: b085 sub sp, #20
|
|
80089f8: af00 add r7, sp, #0
|
|
80089fa: 6078 str r0, [r7, #4]
|
|
80089fc: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
80089fe: 687b ldr r3, [r7, #4]
|
|
8008a00: 681b ldr r3, [r3, #0]
|
|
8008a02: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8008a04: 687b ldr r3, [r7, #4]
|
|
8008a06: 4a46 ldr r2, [pc, #280] @ (8008b20 <TIM_Base_SetConfig+0x12c>)
|
|
8008a08: 4293 cmp r3, r2
|
|
8008a0a: d013 beq.n 8008a34 <TIM_Base_SetConfig+0x40>
|
|
8008a0c: 687b ldr r3, [r7, #4]
|
|
8008a0e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8008a12: d00f beq.n 8008a34 <TIM_Base_SetConfig+0x40>
|
|
8008a14: 687b ldr r3, [r7, #4]
|
|
8008a16: 4a43 ldr r2, [pc, #268] @ (8008b24 <TIM_Base_SetConfig+0x130>)
|
|
8008a18: 4293 cmp r3, r2
|
|
8008a1a: d00b beq.n 8008a34 <TIM_Base_SetConfig+0x40>
|
|
8008a1c: 687b ldr r3, [r7, #4]
|
|
8008a1e: 4a42 ldr r2, [pc, #264] @ (8008b28 <TIM_Base_SetConfig+0x134>)
|
|
8008a20: 4293 cmp r3, r2
|
|
8008a22: d007 beq.n 8008a34 <TIM_Base_SetConfig+0x40>
|
|
8008a24: 687b ldr r3, [r7, #4]
|
|
8008a26: 4a41 ldr r2, [pc, #260] @ (8008b2c <TIM_Base_SetConfig+0x138>)
|
|
8008a28: 4293 cmp r3, r2
|
|
8008a2a: d003 beq.n 8008a34 <TIM_Base_SetConfig+0x40>
|
|
8008a2c: 687b ldr r3, [r7, #4]
|
|
8008a2e: 4a40 ldr r2, [pc, #256] @ (8008b30 <TIM_Base_SetConfig+0x13c>)
|
|
8008a30: 4293 cmp r3, r2
|
|
8008a32: d108 bne.n 8008a46 <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
8008a34: 68fb ldr r3, [r7, #12]
|
|
8008a36: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8008a3a: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
8008a3c: 683b ldr r3, [r7, #0]
|
|
8008a3e: 685b ldr r3, [r3, #4]
|
|
8008a40: 68fa ldr r2, [r7, #12]
|
|
8008a42: 4313 orrs r3, r2
|
|
8008a44: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
8008a46: 687b ldr r3, [r7, #4]
|
|
8008a48: 4a35 ldr r2, [pc, #212] @ (8008b20 <TIM_Base_SetConfig+0x12c>)
|
|
8008a4a: 4293 cmp r3, r2
|
|
8008a4c: d01f beq.n 8008a8e <TIM_Base_SetConfig+0x9a>
|
|
8008a4e: 687b ldr r3, [r7, #4]
|
|
8008a50: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8008a54: d01b beq.n 8008a8e <TIM_Base_SetConfig+0x9a>
|
|
8008a56: 687b ldr r3, [r7, #4]
|
|
8008a58: 4a32 ldr r2, [pc, #200] @ (8008b24 <TIM_Base_SetConfig+0x130>)
|
|
8008a5a: 4293 cmp r3, r2
|
|
8008a5c: d017 beq.n 8008a8e <TIM_Base_SetConfig+0x9a>
|
|
8008a5e: 687b ldr r3, [r7, #4]
|
|
8008a60: 4a31 ldr r2, [pc, #196] @ (8008b28 <TIM_Base_SetConfig+0x134>)
|
|
8008a62: 4293 cmp r3, r2
|
|
8008a64: d013 beq.n 8008a8e <TIM_Base_SetConfig+0x9a>
|
|
8008a66: 687b ldr r3, [r7, #4]
|
|
8008a68: 4a30 ldr r2, [pc, #192] @ (8008b2c <TIM_Base_SetConfig+0x138>)
|
|
8008a6a: 4293 cmp r3, r2
|
|
8008a6c: d00f beq.n 8008a8e <TIM_Base_SetConfig+0x9a>
|
|
8008a6e: 687b ldr r3, [r7, #4]
|
|
8008a70: 4a2f ldr r2, [pc, #188] @ (8008b30 <TIM_Base_SetConfig+0x13c>)
|
|
8008a72: 4293 cmp r3, r2
|
|
8008a74: d00b beq.n 8008a8e <TIM_Base_SetConfig+0x9a>
|
|
8008a76: 687b ldr r3, [r7, #4]
|
|
8008a78: 4a2e ldr r2, [pc, #184] @ (8008b34 <TIM_Base_SetConfig+0x140>)
|
|
8008a7a: 4293 cmp r3, r2
|
|
8008a7c: d007 beq.n 8008a8e <TIM_Base_SetConfig+0x9a>
|
|
8008a7e: 687b ldr r3, [r7, #4]
|
|
8008a80: 4a2d ldr r2, [pc, #180] @ (8008b38 <TIM_Base_SetConfig+0x144>)
|
|
8008a82: 4293 cmp r3, r2
|
|
8008a84: d003 beq.n 8008a8e <TIM_Base_SetConfig+0x9a>
|
|
8008a86: 687b ldr r3, [r7, #4]
|
|
8008a88: 4a2c ldr r2, [pc, #176] @ (8008b3c <TIM_Base_SetConfig+0x148>)
|
|
8008a8a: 4293 cmp r3, r2
|
|
8008a8c: d108 bne.n 8008aa0 <TIM_Base_SetConfig+0xac>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
8008a8e: 68fb ldr r3, [r7, #12]
|
|
8008a90: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8008a94: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
8008a96: 683b ldr r3, [r7, #0]
|
|
8008a98: 68db ldr r3, [r3, #12]
|
|
8008a9a: 68fa ldr r2, [r7, #12]
|
|
8008a9c: 4313 orrs r3, r2
|
|
8008a9e: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8008aa0: 68fb ldr r3, [r7, #12]
|
|
8008aa2: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
8008aa6: 683b ldr r3, [r7, #0]
|
|
8008aa8: 695b ldr r3, [r3, #20]
|
|
8008aaa: 4313 orrs r3, r2
|
|
8008aac: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8008aae: 687b ldr r3, [r7, #4]
|
|
8008ab0: 68fa ldr r2, [r7, #12]
|
|
8008ab2: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
8008ab4: 683b ldr r3, [r7, #0]
|
|
8008ab6: 689a ldr r2, [r3, #8]
|
|
8008ab8: 687b ldr r3, [r7, #4]
|
|
8008aba: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8008abc: 683b ldr r3, [r7, #0]
|
|
8008abe: 681a ldr r2, [r3, #0]
|
|
8008ac0: 687b ldr r3, [r7, #4]
|
|
8008ac2: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
8008ac4: 687b ldr r3, [r7, #4]
|
|
8008ac6: 4a16 ldr r2, [pc, #88] @ (8008b20 <TIM_Base_SetConfig+0x12c>)
|
|
8008ac8: 4293 cmp r3, r2
|
|
8008aca: d00f beq.n 8008aec <TIM_Base_SetConfig+0xf8>
|
|
8008acc: 687b ldr r3, [r7, #4]
|
|
8008ace: 4a18 ldr r2, [pc, #96] @ (8008b30 <TIM_Base_SetConfig+0x13c>)
|
|
8008ad0: 4293 cmp r3, r2
|
|
8008ad2: d00b beq.n 8008aec <TIM_Base_SetConfig+0xf8>
|
|
8008ad4: 687b ldr r3, [r7, #4]
|
|
8008ad6: 4a17 ldr r2, [pc, #92] @ (8008b34 <TIM_Base_SetConfig+0x140>)
|
|
8008ad8: 4293 cmp r3, r2
|
|
8008ada: d007 beq.n 8008aec <TIM_Base_SetConfig+0xf8>
|
|
8008adc: 687b ldr r3, [r7, #4]
|
|
8008ade: 4a16 ldr r2, [pc, #88] @ (8008b38 <TIM_Base_SetConfig+0x144>)
|
|
8008ae0: 4293 cmp r3, r2
|
|
8008ae2: d003 beq.n 8008aec <TIM_Base_SetConfig+0xf8>
|
|
8008ae4: 687b ldr r3, [r7, #4]
|
|
8008ae6: 4a15 ldr r2, [pc, #84] @ (8008b3c <TIM_Base_SetConfig+0x148>)
|
|
8008ae8: 4293 cmp r3, r2
|
|
8008aea: d103 bne.n 8008af4 <TIM_Base_SetConfig+0x100>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8008aec: 683b ldr r3, [r7, #0]
|
|
8008aee: 691a ldr r2, [r3, #16]
|
|
8008af0: 687b ldr r3, [r7, #4]
|
|
8008af2: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8008af4: 687b ldr r3, [r7, #4]
|
|
8008af6: 2201 movs r2, #1
|
|
8008af8: 615a str r2, [r3, #20]
|
|
|
|
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
|
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
|
8008afa: 687b ldr r3, [r7, #4]
|
|
8008afc: 691b ldr r3, [r3, #16]
|
|
8008afe: f003 0301 and.w r3, r3, #1
|
|
8008b02: 2b01 cmp r3, #1
|
|
8008b04: d105 bne.n 8008b12 <TIM_Base_SetConfig+0x11e>
|
|
{
|
|
/* Clear the update flag */
|
|
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
|
8008b06: 687b ldr r3, [r7, #4]
|
|
8008b08: 691b ldr r3, [r3, #16]
|
|
8008b0a: f023 0201 bic.w r2, r3, #1
|
|
8008b0e: 687b ldr r3, [r7, #4]
|
|
8008b10: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
8008b12: bf00 nop
|
|
8008b14: 3714 adds r7, #20
|
|
8008b16: 46bd mov sp, r7
|
|
8008b18: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008b1c: 4770 bx lr
|
|
8008b1e: bf00 nop
|
|
8008b20: 40012c00 .word 0x40012c00
|
|
8008b24: 40000400 .word 0x40000400
|
|
8008b28: 40000800 .word 0x40000800
|
|
8008b2c: 40000c00 .word 0x40000c00
|
|
8008b30: 40013400 .word 0x40013400
|
|
8008b34: 40014000 .word 0x40014000
|
|
8008b38: 40014400 .word 0x40014400
|
|
8008b3c: 40014800 .word 0x40014800
|
|
|
|
08008b40 <HAL_TIMEx_CommutCallback>:
|
|
* @brief Commutation callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8008b40: b480 push {r7}
|
|
8008b42: b083 sub sp, #12
|
|
8008b44: af00 add r7, sp, #0
|
|
8008b46: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8008b48: bf00 nop
|
|
8008b4a: 370c adds r7, #12
|
|
8008b4c: 46bd mov sp, r7
|
|
8008b4e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008b52: 4770 bx lr
|
|
|
|
08008b54 <HAL_TIMEx_BreakCallback>:
|
|
* @brief Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8008b54: b480 push {r7}
|
|
8008b56: b083 sub sp, #12
|
|
8008b58: af00 add r7, sp, #0
|
|
8008b5a: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8008b5c: bf00 nop
|
|
8008b5e: 370c adds r7, #12
|
|
8008b60: 46bd mov sp, r7
|
|
8008b62: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008b66: 4770 bx lr
|
|
|
|
08008b68 <HAL_TIMEx_Break2Callback>:
|
|
* @brief Break2 detection callback in non blocking mode
|
|
* @param htim: TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8008b68: b480 push {r7}
|
|
8008b6a: b083 sub sp, #12
|
|
8008b6c: af00 add r7, sp, #0
|
|
8008b6e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_Break2Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
8008b70: bf00 nop
|
|
8008b72: 370c adds r7, #12
|
|
8008b74: 46bd mov sp, r7
|
|
8008b76: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008b7a: 4770 bx lr
|
|
|
|
08008b7c <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8008b7c: b580 push {r7, lr}
|
|
8008b7e: b082 sub sp, #8
|
|
8008b80: af00 add r7, sp, #0
|
|
8008b82: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8008b84: 687b ldr r3, [r7, #4]
|
|
8008b86: 2b00 cmp r3, #0
|
|
8008b88: d101 bne.n 8008b8e <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8008b8a: 2301 movs r3, #1
|
|
8008b8c: e040 b.n 8008c10 <HAL_UART_Init+0x94>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8008b8e: 687b ldr r3, [r7, #4]
|
|
8008b90: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8008b92: 2b00 cmp r3, #0
|
|
8008b94: d106 bne.n 8008ba4 <HAL_UART_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8008b96: 687b ldr r3, [r7, #4]
|
|
8008b98: 2200 movs r2, #0
|
|
8008b9a: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8008b9e: 6878 ldr r0, [r7, #4]
|
|
8008ba0: f7fa fd72 bl 8003688 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8008ba4: 687b ldr r3, [r7, #4]
|
|
8008ba6: 2224 movs r2, #36 @ 0x24
|
|
8008ba8: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
8008baa: 687b ldr r3, [r7, #4]
|
|
8008bac: 681b ldr r3, [r3, #0]
|
|
8008bae: 681a ldr r2, [r3, #0]
|
|
8008bb0: 687b ldr r3, [r7, #4]
|
|
8008bb2: 681b ldr r3, [r3, #0]
|
|
8008bb4: f022 0201 bic.w r2, r2, #1
|
|
8008bb8: 601a str r2, [r3, #0]
|
|
|
|
/* Perform advanced settings configuration */
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
8008bba: 687b ldr r3, [r7, #4]
|
|
8008bbc: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008bbe: 2b00 cmp r3, #0
|
|
8008bc0: d002 beq.n 8008bc8 <HAL_UART_Init+0x4c>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
8008bc2: 6878 ldr r0, [r7, #4]
|
|
8008bc4: f000 ff24 bl 8009a10 <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
8008bc8: 6878 ldr r0, [r7, #4]
|
|
8008bca: f000 fc69 bl 80094a0 <UART_SetConfig>
|
|
8008bce: 4603 mov r3, r0
|
|
8008bd0: 2b01 cmp r3, #1
|
|
8008bd2: d101 bne.n 8008bd8 <HAL_UART_Init+0x5c>
|
|
{
|
|
return HAL_ERROR;
|
|
8008bd4: 2301 movs r3, #1
|
|
8008bd6: e01b b.n 8008c10 <HAL_UART_Init+0x94>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8008bd8: 687b ldr r3, [r7, #4]
|
|
8008bda: 681b ldr r3, [r3, #0]
|
|
8008bdc: 685a ldr r2, [r3, #4]
|
|
8008bde: 687b ldr r3, [r7, #4]
|
|
8008be0: 681b ldr r3, [r3, #0]
|
|
8008be2: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8008be6: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8008be8: 687b ldr r3, [r7, #4]
|
|
8008bea: 681b ldr r3, [r3, #0]
|
|
8008bec: 689a ldr r2, [r3, #8]
|
|
8008bee: 687b ldr r3, [r7, #4]
|
|
8008bf0: 681b ldr r3, [r3, #0]
|
|
8008bf2: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8008bf6: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
8008bf8: 687b ldr r3, [r7, #4]
|
|
8008bfa: 681b ldr r3, [r3, #0]
|
|
8008bfc: 681a ldr r2, [r3, #0]
|
|
8008bfe: 687b ldr r3, [r7, #4]
|
|
8008c00: 681b ldr r3, [r3, #0]
|
|
8008c02: f042 0201 orr.w r2, r2, #1
|
|
8008c06: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
8008c08: 6878 ldr r0, [r7, #4]
|
|
8008c0a: f000 ffa3 bl 8009b54 <UART_CheckIdleState>
|
|
8008c0e: 4603 mov r3, r0
|
|
}
|
|
8008c10: 4618 mov r0, r3
|
|
8008c12: 3708 adds r7, #8
|
|
8008c14: 46bd mov sp, r7
|
|
8008c16: bd80 pop {r7, pc}
|
|
|
|
08008c18 <HAL_UART_Receive>:
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @param Timeout Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8008c18: b580 push {r7, lr}
|
|
8008c1a: b08a sub sp, #40 @ 0x28
|
|
8008c1c: af02 add r7, sp, #8
|
|
8008c1e: 60f8 str r0, [r7, #12]
|
|
8008c20: 60b9 str r1, [r7, #8]
|
|
8008c22: 603b str r3, [r7, #0]
|
|
8008c24: 4613 mov r3, r2
|
|
8008c26: 80fb strh r3, [r7, #6]
|
|
uint16_t *pdata16bits;
|
|
uint16_t uhMask;
|
|
uint32_t tickstart;
|
|
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
8008c28: 68fb ldr r3, [r7, #12]
|
|
8008c2a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8008c2e: 2b20 cmp r3, #32
|
|
8008c30: f040 80b6 bne.w 8008da0 <HAL_UART_Receive+0x188>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8008c34: 68bb ldr r3, [r7, #8]
|
|
8008c36: 2b00 cmp r3, #0
|
|
8008c38: d002 beq.n 8008c40 <HAL_UART_Receive+0x28>
|
|
8008c3a: 88fb ldrh r3, [r7, #6]
|
|
8008c3c: 2b00 cmp r3, #0
|
|
8008c3e: d101 bne.n 8008c44 <HAL_UART_Receive+0x2c>
|
|
{
|
|
return HAL_ERROR;
|
|
8008c40: 2301 movs r3, #1
|
|
8008c42: e0ae b.n 8008da2 <HAL_UART_Receive+0x18a>
|
|
}
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8008c44: 68fb ldr r3, [r7, #12]
|
|
8008c46: 2200 movs r2, #0
|
|
8008c48: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8008c4c: 68fb ldr r3, [r7, #12]
|
|
8008c4e: 2222 movs r2, #34 @ 0x22
|
|
8008c50: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8008c54: 68fb ldr r3, [r7, #12]
|
|
8008c56: 2200 movs r2, #0
|
|
8008c58: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8008c5a: f7fb f851 bl 8003d00 <HAL_GetTick>
|
|
8008c5e: 6178 str r0, [r7, #20]
|
|
|
|
huart->RxXferSize = Size;
|
|
8008c60: 68fb ldr r3, [r7, #12]
|
|
8008c62: 88fa ldrh r2, [r7, #6]
|
|
8008c64: f8a3 2058 strh.w r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount = Size;
|
|
8008c68: 68fb ldr r3, [r7, #12]
|
|
8008c6a: 88fa ldrh r2, [r7, #6]
|
|
8008c6c: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
|
|
/* Computation of UART mask to apply to RDR register */
|
|
UART_MASK_COMPUTATION(huart);
|
|
8008c70: 68fb ldr r3, [r7, #12]
|
|
8008c72: 689b ldr r3, [r3, #8]
|
|
8008c74: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8008c78: d10e bne.n 8008c98 <HAL_UART_Receive+0x80>
|
|
8008c7a: 68fb ldr r3, [r7, #12]
|
|
8008c7c: 691b ldr r3, [r3, #16]
|
|
8008c7e: 2b00 cmp r3, #0
|
|
8008c80: d105 bne.n 8008c8e <HAL_UART_Receive+0x76>
|
|
8008c82: 68fb ldr r3, [r7, #12]
|
|
8008c84: f240 12ff movw r2, #511 @ 0x1ff
|
|
8008c88: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8008c8c: e02d b.n 8008cea <HAL_UART_Receive+0xd2>
|
|
8008c8e: 68fb ldr r3, [r7, #12]
|
|
8008c90: 22ff movs r2, #255 @ 0xff
|
|
8008c92: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8008c96: e028 b.n 8008cea <HAL_UART_Receive+0xd2>
|
|
8008c98: 68fb ldr r3, [r7, #12]
|
|
8008c9a: 689b ldr r3, [r3, #8]
|
|
8008c9c: 2b00 cmp r3, #0
|
|
8008c9e: d10d bne.n 8008cbc <HAL_UART_Receive+0xa4>
|
|
8008ca0: 68fb ldr r3, [r7, #12]
|
|
8008ca2: 691b ldr r3, [r3, #16]
|
|
8008ca4: 2b00 cmp r3, #0
|
|
8008ca6: d104 bne.n 8008cb2 <HAL_UART_Receive+0x9a>
|
|
8008ca8: 68fb ldr r3, [r7, #12]
|
|
8008caa: 22ff movs r2, #255 @ 0xff
|
|
8008cac: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8008cb0: e01b b.n 8008cea <HAL_UART_Receive+0xd2>
|
|
8008cb2: 68fb ldr r3, [r7, #12]
|
|
8008cb4: 227f movs r2, #127 @ 0x7f
|
|
8008cb6: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8008cba: e016 b.n 8008cea <HAL_UART_Receive+0xd2>
|
|
8008cbc: 68fb ldr r3, [r7, #12]
|
|
8008cbe: 689b ldr r3, [r3, #8]
|
|
8008cc0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8008cc4: d10d bne.n 8008ce2 <HAL_UART_Receive+0xca>
|
|
8008cc6: 68fb ldr r3, [r7, #12]
|
|
8008cc8: 691b ldr r3, [r3, #16]
|
|
8008cca: 2b00 cmp r3, #0
|
|
8008ccc: d104 bne.n 8008cd8 <HAL_UART_Receive+0xc0>
|
|
8008cce: 68fb ldr r3, [r7, #12]
|
|
8008cd0: 227f movs r2, #127 @ 0x7f
|
|
8008cd2: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8008cd6: e008 b.n 8008cea <HAL_UART_Receive+0xd2>
|
|
8008cd8: 68fb ldr r3, [r7, #12]
|
|
8008cda: 223f movs r2, #63 @ 0x3f
|
|
8008cdc: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8008ce0: e003 b.n 8008cea <HAL_UART_Receive+0xd2>
|
|
8008ce2: 68fb ldr r3, [r7, #12]
|
|
8008ce4: 2200 movs r2, #0
|
|
8008ce6: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
uhMask = huart->Mask;
|
|
8008cea: 68fb ldr r3, [r7, #12]
|
|
8008cec: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8008cf0: 827b strh r3, [r7, #18]
|
|
|
|
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8008cf2: 68fb ldr r3, [r7, #12]
|
|
8008cf4: 689b ldr r3, [r3, #8]
|
|
8008cf6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8008cfa: d108 bne.n 8008d0e <HAL_UART_Receive+0xf6>
|
|
8008cfc: 68fb ldr r3, [r7, #12]
|
|
8008cfe: 691b ldr r3, [r3, #16]
|
|
8008d00: 2b00 cmp r3, #0
|
|
8008d02: d104 bne.n 8008d0e <HAL_UART_Receive+0xf6>
|
|
{
|
|
pdata8bits = NULL;
|
|
8008d04: 2300 movs r3, #0
|
|
8008d06: 61fb str r3, [r7, #28]
|
|
pdata16bits = (uint16_t *) pData;
|
|
8008d08: 68bb ldr r3, [r7, #8]
|
|
8008d0a: 61bb str r3, [r7, #24]
|
|
8008d0c: e003 b.n 8008d16 <HAL_UART_Receive+0xfe>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
8008d0e: 68bb ldr r3, [r7, #8]
|
|
8008d10: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
8008d12: 2300 movs r3, #0
|
|
8008d14: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
/* as long as data have to be received */
|
|
while (huart->RxXferCount > 0U)
|
|
8008d16: e037 b.n 8008d88 <HAL_UART_Receive+0x170>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
|
|
8008d18: 683b ldr r3, [r7, #0]
|
|
8008d1a: 9300 str r3, [sp, #0]
|
|
8008d1c: 697b ldr r3, [r7, #20]
|
|
8008d1e: 2200 movs r2, #0
|
|
8008d20: 2120 movs r1, #32
|
|
8008d22: 68f8 ldr r0, [r7, #12]
|
|
8008d24: f000 ffbe bl 8009ca4 <UART_WaitOnFlagUntilTimeout>
|
|
8008d28: 4603 mov r3, r0
|
|
8008d2a: 2b00 cmp r3, #0
|
|
8008d2c: d005 beq.n 8008d3a <HAL_UART_Receive+0x122>
|
|
{
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8008d2e: 68fb ldr r3, [r7, #12]
|
|
8008d30: 2220 movs r2, #32
|
|
8008d32: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
return HAL_TIMEOUT;
|
|
8008d36: 2303 movs r3, #3
|
|
8008d38: e033 b.n 8008da2 <HAL_UART_Receive+0x18a>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
8008d3a: 69fb ldr r3, [r7, #28]
|
|
8008d3c: 2b00 cmp r3, #0
|
|
8008d3e: d10c bne.n 8008d5a <HAL_UART_Receive+0x142>
|
|
{
|
|
*pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
|
|
8008d40: 68fb ldr r3, [r7, #12]
|
|
8008d42: 681b ldr r3, [r3, #0]
|
|
8008d44: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8008d46: b29a uxth r2, r3
|
|
8008d48: 8a7b ldrh r3, [r7, #18]
|
|
8008d4a: 4013 ands r3, r2
|
|
8008d4c: b29a uxth r2, r3
|
|
8008d4e: 69bb ldr r3, [r7, #24]
|
|
8008d50: 801a strh r2, [r3, #0]
|
|
pdata16bits++;
|
|
8008d52: 69bb ldr r3, [r7, #24]
|
|
8008d54: 3302 adds r3, #2
|
|
8008d56: 61bb str r3, [r7, #24]
|
|
8008d58: e00d b.n 8008d76 <HAL_UART_Receive+0x15e>
|
|
}
|
|
else
|
|
{
|
|
*pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
|
|
8008d5a: 68fb ldr r3, [r7, #12]
|
|
8008d5c: 681b ldr r3, [r3, #0]
|
|
8008d5e: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8008d60: b29b uxth r3, r3
|
|
8008d62: b2da uxtb r2, r3
|
|
8008d64: 8a7b ldrh r3, [r7, #18]
|
|
8008d66: b2db uxtb r3, r3
|
|
8008d68: 4013 ands r3, r2
|
|
8008d6a: b2da uxtb r2, r3
|
|
8008d6c: 69fb ldr r3, [r7, #28]
|
|
8008d6e: 701a strb r2, [r3, #0]
|
|
pdata8bits++;
|
|
8008d70: 69fb ldr r3, [r7, #28]
|
|
8008d72: 3301 adds r3, #1
|
|
8008d74: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->RxXferCount--;
|
|
8008d76: 68fb ldr r3, [r7, #12]
|
|
8008d78: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
8008d7c: b29b uxth r3, r3
|
|
8008d7e: 3b01 subs r3, #1
|
|
8008d80: b29a uxth r2, r3
|
|
8008d82: 68fb ldr r3, [r7, #12]
|
|
8008d84: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
while (huart->RxXferCount > 0U)
|
|
8008d88: 68fb ldr r3, [r7, #12]
|
|
8008d8a: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
8008d8e: b29b uxth r3, r3
|
|
8008d90: 2b00 cmp r3, #0
|
|
8008d92: d1c1 bne.n 8008d18 <HAL_UART_Receive+0x100>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8008d94: 68fb ldr r3, [r7, #12]
|
|
8008d96: 2220 movs r2, #32
|
|
8008d98: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
return HAL_OK;
|
|
8008d9c: 2300 movs r3, #0
|
|
8008d9e: e000 b.n 8008da2 <HAL_UART_Receive+0x18a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8008da0: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8008da2: 4618 mov r0, r3
|
|
8008da4: 3720 adds r7, #32
|
|
8008da6: 46bd mov sp, r7
|
|
8008da8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008dac <HAL_UART_Transmit_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
|
|
{
|
|
8008dac: b480 push {r7}
|
|
8008dae: b08b sub sp, #44 @ 0x2c
|
|
8008db0: af00 add r7, sp, #0
|
|
8008db2: 60f8 str r0, [r7, #12]
|
|
8008db4: 60b9 str r1, [r7, #8]
|
|
8008db6: 4613 mov r3, r2
|
|
8008db8: 80fb strh r3, [r7, #6]
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8008dba: 68fb ldr r3, [r7, #12]
|
|
8008dbc: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8008dbe: 2b20 cmp r3, #32
|
|
8008dc0: d147 bne.n 8008e52 <HAL_UART_Transmit_IT+0xa6>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8008dc2: 68bb ldr r3, [r7, #8]
|
|
8008dc4: 2b00 cmp r3, #0
|
|
8008dc6: d002 beq.n 8008dce <HAL_UART_Transmit_IT+0x22>
|
|
8008dc8: 88fb ldrh r3, [r7, #6]
|
|
8008dca: 2b00 cmp r3, #0
|
|
8008dcc: d101 bne.n 8008dd2 <HAL_UART_Transmit_IT+0x26>
|
|
{
|
|
return HAL_ERROR;
|
|
8008dce: 2301 movs r3, #1
|
|
8008dd0: e040 b.n 8008e54 <HAL_UART_Transmit_IT+0xa8>
|
|
}
|
|
|
|
huart->pTxBuffPtr = pData;
|
|
8008dd2: 68fb ldr r3, [r7, #12]
|
|
8008dd4: 68ba ldr r2, [r7, #8]
|
|
8008dd6: 64da str r2, [r3, #76] @ 0x4c
|
|
huart->TxXferSize = Size;
|
|
8008dd8: 68fb ldr r3, [r7, #12]
|
|
8008dda: 88fa ldrh r2, [r7, #6]
|
|
8008ddc: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
|
|
huart->TxXferCount = Size;
|
|
8008de0: 68fb ldr r3, [r7, #12]
|
|
8008de2: 88fa ldrh r2, [r7, #6]
|
|
8008de4: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
huart->TxISR = NULL;
|
|
8008de8: 68fb ldr r3, [r7, #12]
|
|
8008dea: 2200 movs r2, #0
|
|
8008dec: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8008dee: 68fb ldr r3, [r7, #12]
|
|
8008df0: 2200 movs r2, #0
|
|
8008df2: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8008df6: 68fb ldr r3, [r7, #12]
|
|
8008df8: 2221 movs r2, #33 @ 0x21
|
|
8008dfa: 67da str r2, [r3, #124] @ 0x7c
|
|
/* Enable the Transmit Data Register Empty interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
|
}
|
|
#else
|
|
/* Set the Tx ISR function pointer according to the data word length */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8008dfc: 68fb ldr r3, [r7, #12]
|
|
8008dfe: 689b ldr r3, [r3, #8]
|
|
8008e00: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8008e04: d107 bne.n 8008e16 <HAL_UART_Transmit_IT+0x6a>
|
|
8008e06: 68fb ldr r3, [r7, #12]
|
|
8008e08: 691b ldr r3, [r3, #16]
|
|
8008e0a: 2b00 cmp r3, #0
|
|
8008e0c: d103 bne.n 8008e16 <HAL_UART_Transmit_IT+0x6a>
|
|
{
|
|
huart->TxISR = UART_TxISR_16BIT;
|
|
8008e0e: 68fb ldr r3, [r7, #12]
|
|
8008e10: 4a13 ldr r2, [pc, #76] @ (8008e60 <HAL_UART_Transmit_IT+0xb4>)
|
|
8008e12: 66da str r2, [r3, #108] @ 0x6c
|
|
8008e14: e002 b.n 8008e1c <HAL_UART_Transmit_IT+0x70>
|
|
}
|
|
else
|
|
{
|
|
huart->TxISR = UART_TxISR_8BIT;
|
|
8008e16: 68fb ldr r3, [r7, #12]
|
|
8008e18: 4a12 ldr r2, [pc, #72] @ (8008e64 <HAL_UART_Transmit_IT+0xb8>)
|
|
8008e1a: 66da str r2, [r3, #108] @ 0x6c
|
|
}
|
|
|
|
/* Enable the Transmit Data Register Empty interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|
8008e1c: 68fb ldr r3, [r7, #12]
|
|
8008e1e: 681b ldr r3, [r3, #0]
|
|
8008e20: 617b str r3, [r7, #20]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8008e22: 697b ldr r3, [r7, #20]
|
|
8008e24: e853 3f00 ldrex r3, [r3]
|
|
8008e28: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8008e2a: 693b ldr r3, [r7, #16]
|
|
8008e2c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8008e30: 627b str r3, [r7, #36] @ 0x24
|
|
8008e32: 68fb ldr r3, [r7, #12]
|
|
8008e34: 681b ldr r3, [r3, #0]
|
|
8008e36: 461a mov r2, r3
|
|
8008e38: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8008e3a: 623b str r3, [r7, #32]
|
|
8008e3c: 61fa str r2, [r7, #28]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8008e3e: 69f9 ldr r1, [r7, #28]
|
|
8008e40: 6a3a ldr r2, [r7, #32]
|
|
8008e42: e841 2300 strex r3, r2, [r1]
|
|
8008e46: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
8008e48: 69bb ldr r3, [r7, #24]
|
|
8008e4a: 2b00 cmp r3, #0
|
|
8008e4c: d1e6 bne.n 8008e1c <HAL_UART_Transmit_IT+0x70>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
return HAL_OK;
|
|
8008e4e: 2300 movs r3, #0
|
|
8008e50: e000 b.n 8008e54 <HAL_UART_Transmit_IT+0xa8>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8008e52: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8008e54: 4618 mov r0, r3
|
|
8008e56: 372c adds r7, #44 @ 0x2c
|
|
8008e58: 46bd mov sp, r7
|
|
8008e5a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008e5e: 4770 bx lr
|
|
8008e60: 08009f29 .word 0x08009f29
|
|
8008e64: 08009e73 .word 0x08009e73
|
|
|
|
08008e68 <HAL_UART_IRQHandler>:
|
|
* @brief Handle UART interrupt request.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
8008e68: b580 push {r7, lr}
|
|
8008e6a: b0ba sub sp, #232 @ 0xe8
|
|
8008e6c: af00 add r7, sp, #0
|
|
8008e6e: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8008e70: 687b ldr r3, [r7, #4]
|
|
8008e72: 681b ldr r3, [r3, #0]
|
|
8008e74: 69db ldr r3, [r3, #28]
|
|
8008e76: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8008e7a: 687b ldr r3, [r7, #4]
|
|
8008e7c: 681b ldr r3, [r3, #0]
|
|
8008e7e: 681b ldr r3, [r3, #0]
|
|
8008e80: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8008e84: 687b ldr r3, [r7, #4]
|
|
8008e86: 681b ldr r3, [r3, #0]
|
|
8008e88: 689b ldr r3, [r3, #8]
|
|
8008e8a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
|
|
uint32_t errorflags;
|
|
uint32_t errorcode;
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|
8008e8e: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4
|
|
8008e92: f640 030f movw r3, #2063 @ 0x80f
|
|
8008e96: 4013 ands r3, r2
|
|
8008e98: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
if (errorflags == 0U)
|
|
8008e9c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8008ea0: 2b00 cmp r3, #0
|
|
8008ea2: d115 bne.n 8008ed0 <HAL_UART_IRQHandler+0x68>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|
8008ea4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8008ea8: f003 0320 and.w r3, r3, #32
|
|
8008eac: 2b00 cmp r3, #0
|
|
8008eae: d00f beq.n 8008ed0 <HAL_UART_IRQHandler+0x68>
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|
8008eb0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8008eb4: f003 0320 and.w r3, r3, #32
|
|
8008eb8: 2b00 cmp r3, #0
|
|
8008eba: d009 beq.n 8008ed0 <HAL_UART_IRQHandler+0x68>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
8008ebc: 687b ldr r3, [r7, #4]
|
|
8008ebe: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8008ec0: 2b00 cmp r3, #0
|
|
8008ec2: f000 82ca beq.w 800945a <HAL_UART_IRQHandler+0x5f2>
|
|
{
|
|
huart->RxISR(huart);
|
|
8008ec6: 687b ldr r3, [r7, #4]
|
|
8008ec8: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8008eca: 6878 ldr r0, [r7, #4]
|
|
8008ecc: 4798 blx r3
|
|
}
|
|
return;
|
|
8008ece: e2c4 b.n 800945a <HAL_UART_IRQHandler+0x5f2>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if ((errorflags != 0U)
|
|
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|
|
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
|
|
#else
|
|
if ((errorflags != 0U)
|
|
8008ed0: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8008ed4: 2b00 cmp r3, #0
|
|
8008ed6: f000 8117 beq.w 8009108 <HAL_UART_IRQHandler+0x2a0>
|
|
&& (((cr3its & USART_CR3_EIE) != 0U)
|
|
8008eda: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8008ede: f003 0301 and.w r3, r3, #1
|
|
8008ee2: 2b00 cmp r3, #0
|
|
8008ee4: d106 bne.n 8008ef4 <HAL_UART_IRQHandler+0x8c>
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
|
|
8008ee6: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0
|
|
8008eea: 4b85 ldr r3, [pc, #532] @ (8009100 <HAL_UART_IRQHandler+0x298>)
|
|
8008eec: 4013 ands r3, r2
|
|
8008eee: 2b00 cmp r3, #0
|
|
8008ef0: f000 810a beq.w 8009108 <HAL_UART_IRQHandler+0x2a0>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
8008ef4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8008ef8: f003 0301 and.w r3, r3, #1
|
|
8008efc: 2b00 cmp r3, #0
|
|
8008efe: d011 beq.n 8008f24 <HAL_UART_IRQHandler+0xbc>
|
|
8008f00: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8008f04: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8008f08: 2b00 cmp r3, #0
|
|
8008f0a: d00b beq.n 8008f24 <HAL_UART_IRQHandler+0xbc>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8008f0c: 687b ldr r3, [r7, #4]
|
|
8008f0e: 681b ldr r3, [r3, #0]
|
|
8008f10: 2201 movs r2, #1
|
|
8008f12: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8008f14: 687b ldr r3, [r7, #4]
|
|
8008f16: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8008f1a: f043 0201 orr.w r2, r3, #1
|
|
8008f1e: 687b ldr r3, [r7, #4]
|
|
8008f20: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8008f24: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8008f28: f003 0302 and.w r3, r3, #2
|
|
8008f2c: 2b00 cmp r3, #0
|
|
8008f2e: d011 beq.n 8008f54 <HAL_UART_IRQHandler+0xec>
|
|
8008f30: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8008f34: f003 0301 and.w r3, r3, #1
|
|
8008f38: 2b00 cmp r3, #0
|
|
8008f3a: d00b beq.n 8008f54 <HAL_UART_IRQHandler+0xec>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8008f3c: 687b ldr r3, [r7, #4]
|
|
8008f3e: 681b ldr r3, [r3, #0]
|
|
8008f40: 2202 movs r2, #2
|
|
8008f42: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8008f44: 687b ldr r3, [r7, #4]
|
|
8008f46: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8008f4a: f043 0204 orr.w r2, r3, #4
|
|
8008f4e: 687b ldr r3, [r7, #4]
|
|
8008f50: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8008f54: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8008f58: f003 0304 and.w r3, r3, #4
|
|
8008f5c: 2b00 cmp r3, #0
|
|
8008f5e: d011 beq.n 8008f84 <HAL_UART_IRQHandler+0x11c>
|
|
8008f60: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8008f64: f003 0301 and.w r3, r3, #1
|
|
8008f68: 2b00 cmp r3, #0
|
|
8008f6a: d00b beq.n 8008f84 <HAL_UART_IRQHandler+0x11c>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8008f6c: 687b ldr r3, [r7, #4]
|
|
8008f6e: 681b ldr r3, [r3, #0]
|
|
8008f70: 2204 movs r2, #4
|
|
8008f72: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8008f74: 687b ldr r3, [r7, #4]
|
|
8008f76: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8008f7a: f043 0202 orr.w r2, r3, #2
|
|
8008f7e: 687b ldr r3, [r7, #4]
|
|
8008f80: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
8008f84: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8008f88: f003 0308 and.w r3, r3, #8
|
|
8008f8c: 2b00 cmp r3, #0
|
|
8008f8e: d017 beq.n 8008fc0 <HAL_UART_IRQHandler+0x158>
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|
8008f90: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8008f94: f003 0320 and.w r3, r3, #32
|
|
8008f98: 2b00 cmp r3, #0
|
|
8008f9a: d105 bne.n 8008fa8 <HAL_UART_IRQHandler+0x140>
|
|
((cr3its & USART_CR3_EIE) != 0U)))
|
|
8008f9c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8008fa0: f003 0301 and.w r3, r3, #1
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|
8008fa4: 2b00 cmp r3, #0
|
|
8008fa6: d00b beq.n 8008fc0 <HAL_UART_IRQHandler+0x158>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8008fa8: 687b ldr r3, [r7, #4]
|
|
8008faa: 681b ldr r3, [r3, #0]
|
|
8008fac: 2208 movs r2, #8
|
|
8008fae: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
8008fb0: 687b ldr r3, [r7, #4]
|
|
8008fb2: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8008fb6: f043 0208 orr.w r2, r3, #8
|
|
8008fba: 687b ldr r3, [r7, #4]
|
|
8008fbc: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|
8008fc0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8008fc4: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8008fc8: 2b00 cmp r3, #0
|
|
8008fca: d012 beq.n 8008ff2 <HAL_UART_IRQHandler+0x18a>
|
|
8008fcc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8008fd0: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8008fd4: 2b00 cmp r3, #0
|
|
8008fd6: d00c beq.n 8008ff2 <HAL_UART_IRQHandler+0x18a>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8008fd8: 687b ldr r3, [r7, #4]
|
|
8008fda: 681b ldr r3, [r3, #0]
|
|
8008fdc: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8008fe0: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|
8008fe2: 687b ldr r3, [r7, #4]
|
|
8008fe4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8008fe8: f043 0220 orr.w r2, r3, #32
|
|
8008fec: 687b ldr r3, [r7, #4]
|
|
8008fee: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
8008ff2: 687b ldr r3, [r7, #4]
|
|
8008ff4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8008ff8: 2b00 cmp r3, #0
|
|
8008ffa: f000 8230 beq.w 800945e <HAL_UART_IRQHandler+0x5f6>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|
8008ffe: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8009002: f003 0320 and.w r3, r3, #32
|
|
8009006: 2b00 cmp r3, #0
|
|
8009008: d00d beq.n 8009026 <HAL_UART_IRQHandler+0x1be>
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|
800900a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800900e: f003 0320 and.w r3, r3, #32
|
|
8009012: 2b00 cmp r3, #0
|
|
8009014: d007 beq.n 8009026 <HAL_UART_IRQHandler+0x1be>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
8009016: 687b ldr r3, [r7, #4]
|
|
8009018: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
800901a: 2b00 cmp r3, #0
|
|
800901c: d003 beq.n 8009026 <HAL_UART_IRQHandler+0x1be>
|
|
{
|
|
huart->RxISR(huart);
|
|
800901e: 687b ldr r3, [r7, #4]
|
|
8009020: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8009022: 6878 ldr r0, [r7, #4]
|
|
8009024: 4798 blx r3
|
|
/* If Error is to be considered as blocking :
|
|
- Receiver Timeout error in Reception
|
|
- Overrun error in Reception
|
|
- any error occurs in DMA mode reception
|
|
*/
|
|
errorcode = huart->ErrorCode;
|
|
8009026: 687b ldr r3, [r7, #4]
|
|
8009028: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800902c: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
8009030: 687b ldr r3, [r7, #4]
|
|
8009032: 681b ldr r3, [r3, #0]
|
|
8009034: 689b ldr r3, [r3, #8]
|
|
8009036: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800903a: 2b40 cmp r3, #64 @ 0x40
|
|
800903c: d005 beq.n 800904a <HAL_UART_IRQHandler+0x1e2>
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
800903e: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
8009042: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
8009046: 2b00 cmp r3, #0
|
|
8009048: d04f beq.n 80090ea <HAL_UART_IRQHandler+0x282>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
800904a: 6878 ldr r0, [r7, #4]
|
|
800904c: f000 fe97 bl 8009d7e <UART_EndRxTransfer>
|
|
|
|
/* Abort the UART DMA Rx channel if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8009050: 687b ldr r3, [r7, #4]
|
|
8009052: 681b ldr r3, [r3, #0]
|
|
8009054: 689b ldr r3, [r3, #8]
|
|
8009056: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800905a: 2b40 cmp r3, #64 @ 0x40
|
|
800905c: d141 bne.n 80090e2 <HAL_UART_IRQHandler+0x27a>
|
|
{
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
800905e: 687b ldr r3, [r7, #4]
|
|
8009060: 681b ldr r3, [r3, #0]
|
|
8009062: 3308 adds r3, #8
|
|
8009064: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009068: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
800906c: e853 3f00 ldrex r3, [r3]
|
|
8009070: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
return(result);
|
|
8009074: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8009078: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800907c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
8009080: 687b ldr r3, [r7, #4]
|
|
8009082: 681b ldr r3, [r3, #0]
|
|
8009084: 3308 adds r3, #8
|
|
8009086: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
|
|
800908a: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
|
|
800908e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009092: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
|
|
8009096: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
|
|
800909a: e841 2300 strex r3, r2, [r1]
|
|
800909e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return(result);
|
|
80090a2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
80090a6: 2b00 cmp r3, #0
|
|
80090a8: d1d9 bne.n 800905e <HAL_UART_IRQHandler+0x1f6>
|
|
|
|
/* Abort the UART DMA Rx channel */
|
|
if (huart->hdmarx != NULL)
|
|
80090aa: 687b ldr r3, [r7, #4]
|
|
80090ac: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80090ae: 2b00 cmp r3, #0
|
|
80090b0: d013 beq.n 80090da <HAL_UART_IRQHandler+0x272>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
80090b2: 687b ldr r3, [r7, #4]
|
|
80090b4: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80090b6: 4a13 ldr r2, [pc, #76] @ (8009104 <HAL_UART_IRQHandler+0x29c>)
|
|
80090b8: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Abort DMA RX */
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
80090ba: 687b ldr r3, [r7, #4]
|
|
80090bc: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80090be: 4618 mov r0, r3
|
|
80090c0: f7fb f87a bl 80041b8 <HAL_DMA_Abort_IT>
|
|
80090c4: 4603 mov r3, r0
|
|
80090c6: 2b00 cmp r3, #0
|
|
80090c8: d017 beq.n 80090fa <HAL_UART_IRQHandler+0x292>
|
|
{
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
80090ca: 687b ldr r3, [r7, #4]
|
|
80090cc: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80090ce: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80090d0: 687a ldr r2, [r7, #4]
|
|
80090d2: 6f52 ldr r2, [r2, #116] @ 0x74
|
|
80090d4: 4610 mov r0, r2
|
|
80090d6: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80090d8: e00f b.n 80090fa <HAL_UART_IRQHandler+0x292>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80090da: 6878 ldr r0, [r7, #4]
|
|
80090dc: f000 f9ca bl 8009474 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80090e0: e00b b.n 80090fa <HAL_UART_IRQHandler+0x292>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80090e2: 6878 ldr r0, [r7, #4]
|
|
80090e4: f000 f9c6 bl 8009474 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80090e8: e007 b.n 80090fa <HAL_UART_IRQHandler+0x292>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80090ea: 6878 ldr r0, [r7, #4]
|
|
80090ec: f000 f9c2 bl 8009474 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80090f0: 687b ldr r3, [r7, #4]
|
|
80090f2: 2200 movs r2, #0
|
|
80090f4: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
}
|
|
return;
|
|
80090f8: e1b1 b.n 800945e <HAL_UART_IRQHandler+0x5f6>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80090fa: bf00 nop
|
|
return;
|
|
80090fc: e1af b.n 800945e <HAL_UART_IRQHandler+0x5f6>
|
|
80090fe: bf00 nop
|
|
8009100: 04000120 .word 0x04000120
|
|
8009104: 08009e47 .word 0x08009e47
|
|
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8009108: 687b ldr r3, [r7, #4]
|
|
800910a: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800910c: 2b01 cmp r3, #1
|
|
800910e: f040 816a bne.w 80093e6 <HAL_UART_IRQHandler+0x57e>
|
|
&& ((isrflags & USART_ISR_IDLE) != 0U)
|
|
8009112: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8009116: f003 0310 and.w r3, r3, #16
|
|
800911a: 2b00 cmp r3, #0
|
|
800911c: f000 8163 beq.w 80093e6 <HAL_UART_IRQHandler+0x57e>
|
|
&& ((cr1its & USART_ISR_IDLE) != 0U))
|
|
8009120: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8009124: f003 0310 and.w r3, r3, #16
|
|
8009128: 2b00 cmp r3, #0
|
|
800912a: f000 815c beq.w 80093e6 <HAL_UART_IRQHandler+0x57e>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
800912e: 687b ldr r3, [r7, #4]
|
|
8009130: 681b ldr r3, [r3, #0]
|
|
8009132: 2210 movs r2, #16
|
|
8009134: 621a str r2, [r3, #32]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8009136: 687b ldr r3, [r7, #4]
|
|
8009138: 681b ldr r3, [r3, #0]
|
|
800913a: 689b ldr r3, [r3, #8]
|
|
800913c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8009140: 2b40 cmp r3, #64 @ 0x40
|
|
8009142: f040 80d4 bne.w 80092ee <HAL_UART_IRQHandler+0x486>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
8009146: 687b ldr r3, [r7, #4]
|
|
8009148: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800914a: 681b ldr r3, [r3, #0]
|
|
800914c: 685b ldr r3, [r3, #4]
|
|
800914e: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
|
|
if ((nb_remaining_rx_data > 0U)
|
|
8009152: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
|
|
8009156: 2b00 cmp r3, #0
|
|
8009158: f000 80ad beq.w 80092b6 <HAL_UART_IRQHandler+0x44e>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
800915c: 687b ldr r3, [r7, #4]
|
|
800915e: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
8009162: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8009166: 429a cmp r2, r3
|
|
8009168: f080 80a5 bcs.w 80092b6 <HAL_UART_IRQHandler+0x44e>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
800916c: 687b ldr r3, [r7, #4]
|
|
800916e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8009172: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
8009176: 687b ldr r3, [r7, #4]
|
|
8009178: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800917a: 681b ldr r3, [r3, #0]
|
|
800917c: 681b ldr r3, [r3, #0]
|
|
800917e: f003 0320 and.w r3, r3, #32
|
|
8009182: 2b00 cmp r3, #0
|
|
8009184: f040 8086 bne.w 8009294 <HAL_UART_IRQHandler+0x42c>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8009188: 687b ldr r3, [r7, #4]
|
|
800918a: 681b ldr r3, [r3, #0]
|
|
800918c: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009190: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
8009194: e853 3f00 ldrex r3, [r3]
|
|
8009198: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
return(result);
|
|
800919c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
80091a0: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80091a4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
80091a8: 687b ldr r3, [r7, #4]
|
|
80091aa: 681b ldr r3, [r3, #0]
|
|
80091ac: 461a mov r2, r3
|
|
80091ae: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
80091b2: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
80091b6: f8c7 2090 str.w r2, [r7, #144] @ 0x90
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80091ba: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
|
|
80091be: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
80091c2: e841 2300 strex r3, r2, [r1]
|
|
80091c6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
return(result);
|
|
80091ca: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80091ce: 2b00 cmp r3, #0
|
|
80091d0: d1da bne.n 8009188 <HAL_UART_IRQHandler+0x320>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80091d2: 687b ldr r3, [r7, #4]
|
|
80091d4: 681b ldr r3, [r3, #0]
|
|
80091d6: 3308 adds r3, #8
|
|
80091d8: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80091da: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80091dc: e853 3f00 ldrex r3, [r3]
|
|
80091e0: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
80091e2: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
80091e4: f023 0301 bic.w r3, r3, #1
|
|
80091e8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
80091ec: 687b ldr r3, [r7, #4]
|
|
80091ee: 681b ldr r3, [r3, #0]
|
|
80091f0: 3308 adds r3, #8
|
|
80091f2: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
80091f6: f8c7 2080 str.w r2, [r7, #128] @ 0x80
|
|
80091fa: 67fb str r3, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80091fc: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
80091fe: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
8009202: e841 2300 strex r3, r2, [r1]
|
|
8009206: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8009208: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800920a: 2b00 cmp r3, #0
|
|
800920c: d1e1 bne.n 80091d2 <HAL_UART_IRQHandler+0x36a>
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
800920e: 687b ldr r3, [r7, #4]
|
|
8009210: 681b ldr r3, [r3, #0]
|
|
8009212: 3308 adds r3, #8
|
|
8009214: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009216: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8009218: e853 3f00 ldrex r3, [r3]
|
|
800921c: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
800921e: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8009220: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8009224: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8009228: 687b ldr r3, [r7, #4]
|
|
800922a: 681b ldr r3, [r3, #0]
|
|
800922c: 3308 adds r3, #8
|
|
800922e: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
|
|
8009232: 66fa str r2, [r7, #108] @ 0x6c
|
|
8009234: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009236: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
8009238: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
800923a: e841 2300 strex r3, r2, [r1]
|
|
800923e: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
8009240: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8009242: 2b00 cmp r3, #0
|
|
8009244: d1e3 bne.n 800920e <HAL_UART_IRQHandler+0x3a6>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8009246: 687b ldr r3, [r7, #4]
|
|
8009248: 2220 movs r2, #32
|
|
800924a: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800924e: 687b ldr r3, [r7, #4]
|
|
8009250: 2200 movs r2, #0
|
|
8009252: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8009254: 687b ldr r3, [r7, #4]
|
|
8009256: 681b ldr r3, [r3, #0]
|
|
8009258: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800925a: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800925c: e853 3f00 ldrex r3, [r3]
|
|
8009260: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
8009262: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009264: f023 0310 bic.w r3, r3, #16
|
|
8009268: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
800926c: 687b ldr r3, [r7, #4]
|
|
800926e: 681b ldr r3, [r3, #0]
|
|
8009270: 461a mov r2, r3
|
|
8009272: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8009276: 65bb str r3, [r7, #88] @ 0x58
|
|
8009278: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800927a: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
800927c: 6dba ldr r2, [r7, #88] @ 0x58
|
|
800927e: e841 2300 strex r3, r2, [r1]
|
|
8009282: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8009284: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8009286: 2b00 cmp r3, #0
|
|
8009288: d1e4 bne.n 8009254 <HAL_UART_IRQHandler+0x3ec>
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
800928a: 687b ldr r3, [r7, #4]
|
|
800928c: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800928e: 4618 mov r0, r3
|
|
8009290: f7fa ff54 bl 800413c <HAL_DMA_Abort>
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8009294: 687b ldr r3, [r7, #4]
|
|
8009296: 2202 movs r2, #2
|
|
8009298: 665a str r2, [r3, #100] @ 0x64
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
800929a: 687b ldr r3, [r7, #4]
|
|
800929c: f8b3 2058 ldrh.w r2, [r3, #88] @ 0x58
|
|
80092a0: 687b ldr r3, [r7, #4]
|
|
80092a2: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
80092a6: b29b uxth r3, r3
|
|
80092a8: 1ad3 subs r3, r2, r3
|
|
80092aa: b29b uxth r3, r3
|
|
80092ac: 4619 mov r1, r3
|
|
80092ae: 6878 ldr r0, [r7, #4]
|
|
80092b0: f000 f8ea bl 8009488 <HAL_UARTEx_RxEventCallback>
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
80092b4: e0d5 b.n 8009462 <HAL_UART_IRQHandler+0x5fa>
|
|
if (nb_remaining_rx_data == huart->RxXferSize)
|
|
80092b6: 687b ldr r3, [r7, #4]
|
|
80092b8: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
80092bc: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
80092c0: 429a cmp r2, r3
|
|
80092c2: f040 80ce bne.w 8009462 <HAL_UART_IRQHandler+0x5fa>
|
|
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
80092c6: 687b ldr r3, [r7, #4]
|
|
80092c8: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80092ca: 681b ldr r3, [r3, #0]
|
|
80092cc: 681b ldr r3, [r3, #0]
|
|
80092ce: f003 0320 and.w r3, r3, #32
|
|
80092d2: 2b20 cmp r3, #32
|
|
80092d4: f040 80c5 bne.w 8009462 <HAL_UART_IRQHandler+0x5fa>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
80092d8: 687b ldr r3, [r7, #4]
|
|
80092da: 2202 movs r2, #2
|
|
80092dc: 665a str r2, [r3, #100] @ 0x64
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
80092de: 687b ldr r3, [r7, #4]
|
|
80092e0: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
80092e4: 4619 mov r1, r3
|
|
80092e6: 6878 ldr r0, [r7, #4]
|
|
80092e8: f000 f8ce bl 8009488 <HAL_UARTEx_RxEventCallback>
|
|
return;
|
|
80092ec: e0b9 b.n 8009462 <HAL_UART_IRQHandler+0x5fa>
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
80092ee: 687b ldr r3, [r7, #4]
|
|
80092f0: f8b3 2058 ldrh.w r2, [r3, #88] @ 0x58
|
|
80092f4: 687b ldr r3, [r7, #4]
|
|
80092f6: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
80092fa: b29b uxth r3, r3
|
|
80092fc: 1ad3 subs r3, r2, r3
|
|
80092fe: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
|
|
if ((huart->RxXferCount > 0U)
|
|
8009302: 687b ldr r3, [r7, #4]
|
|
8009304: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
8009308: b29b uxth r3, r3
|
|
800930a: 2b00 cmp r3, #0
|
|
800930c: f000 80ab beq.w 8009466 <HAL_UART_IRQHandler+0x5fe>
|
|
&& (nb_rx_data > 0U))
|
|
8009310: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8009314: 2b00 cmp r3, #0
|
|
8009316: f000 80a6 beq.w 8009466 <HAL_UART_IRQHandler+0x5fe>
|
|
|
|
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
#else
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
800931a: 687b ldr r3, [r7, #4]
|
|
800931c: 681b ldr r3, [r3, #0]
|
|
800931e: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009320: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8009322: e853 3f00 ldrex r3, [r3]
|
|
8009326: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8009328: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800932a: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
800932e: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8009332: 687b ldr r3, [r7, #4]
|
|
8009334: 681b ldr r3, [r3, #0]
|
|
8009336: 461a mov r2, r3
|
|
8009338: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
800933c: 647b str r3, [r7, #68] @ 0x44
|
|
800933e: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009340: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8009342: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8009344: e841 2300 strex r3, r2, [r1]
|
|
8009348: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
800934a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800934c: 2b00 cmp r3, #0
|
|
800934e: d1e4 bne.n 800931a <HAL_UART_IRQHandler+0x4b2>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8009350: 687b ldr r3, [r7, #4]
|
|
8009352: 681b ldr r3, [r3, #0]
|
|
8009354: 3308 adds r3, #8
|
|
8009356: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009358: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800935a: e853 3f00 ldrex r3, [r3]
|
|
800935e: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8009360: 6a3b ldr r3, [r7, #32]
|
|
8009362: f023 0301 bic.w r3, r3, #1
|
|
8009366: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
800936a: 687b ldr r3, [r7, #4]
|
|
800936c: 681b ldr r3, [r3, #0]
|
|
800936e: 3308 adds r3, #8
|
|
8009370: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
|
|
8009374: 633a str r2, [r7, #48] @ 0x30
|
|
8009376: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009378: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800937a: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800937c: e841 2300 strex r3, r2, [r1]
|
|
8009380: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8009382: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009384: 2b00 cmp r3, #0
|
|
8009386: d1e3 bne.n 8009350 <HAL_UART_IRQHandler+0x4e8>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8009388: 687b ldr r3, [r7, #4]
|
|
800938a: 2220 movs r2, #32
|
|
800938c: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8009390: 687b ldr r3, [r7, #4]
|
|
8009392: 2200 movs r2, #0
|
|
8009394: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8009396: 687b ldr r3, [r7, #4]
|
|
8009398: 2200 movs r2, #0
|
|
800939a: 669a str r2, [r3, #104] @ 0x68
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800939c: 687b ldr r3, [r7, #4]
|
|
800939e: 681b ldr r3, [r3, #0]
|
|
80093a0: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80093a2: 693b ldr r3, [r7, #16]
|
|
80093a4: e853 3f00 ldrex r3, [r3]
|
|
80093a8: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80093aa: 68fb ldr r3, [r7, #12]
|
|
80093ac: f023 0310 bic.w r3, r3, #16
|
|
80093b0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
80093b4: 687b ldr r3, [r7, #4]
|
|
80093b6: 681b ldr r3, [r3, #0]
|
|
80093b8: 461a mov r2, r3
|
|
80093ba: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
|
|
80093be: 61fb str r3, [r7, #28]
|
|
80093c0: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80093c2: 69b9 ldr r1, [r7, #24]
|
|
80093c4: 69fa ldr r2, [r7, #28]
|
|
80093c6: e841 2300 strex r3, r2, [r1]
|
|
80093ca: 617b str r3, [r7, #20]
|
|
return(result);
|
|
80093cc: 697b ldr r3, [r7, #20]
|
|
80093ce: 2b00 cmp r3, #0
|
|
80093d0: d1e4 bne.n 800939c <HAL_UART_IRQHandler+0x534>
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
80093d2: 687b ldr r3, [r7, #4]
|
|
80093d4: 2202 movs r2, #2
|
|
80093d6: 665a str r2, [r3, #100] @ 0x64
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
80093d8: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
80093dc: 4619 mov r1, r3
|
|
80093de: 6878 ldr r0, [r7, #4]
|
|
80093e0: f000 f852 bl 8009488 <HAL_UARTEx_RxEventCallback>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
return;
|
|
80093e4: e03f b.n 8009466 <HAL_UART_IRQHandler+0x5fe>
|
|
}
|
|
}
|
|
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|
80093e6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80093ea: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80093ee: 2b00 cmp r3, #0
|
|
80093f0: d00e beq.n 8009410 <HAL_UART_IRQHandler+0x5a8>
|
|
80093f2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80093f6: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80093fa: 2b00 cmp r3, #0
|
|
80093fc: d008 beq.n 8009410 <HAL_UART_IRQHandler+0x5a8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|
80093fe: 687b ldr r3, [r7, #4]
|
|
8009400: 681b ldr r3, [r3, #0]
|
|
8009402: f44f 1280 mov.w r2, #1048576 @ 0x100000
|
|
8009406: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Wakeup Callback */
|
|
huart->WakeupCallback(huart);
|
|
#else
|
|
/* Call legacy weak Wakeup Callback */
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
8009408: 6878 ldr r0, [r7, #4]
|
|
800940a: f000 fe17 bl 800a03c <HAL_UARTEx_WakeupCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
800940e: e02d b.n 800946c <HAL_UART_IRQHandler+0x604>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
|
|
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_TXE) != 0U)
|
|
8009410: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8009414: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8009418: 2b00 cmp r3, #0
|
|
800941a: d00e beq.n 800943a <HAL_UART_IRQHandler+0x5d2>
|
|
&& ((cr1its & USART_CR1_TXEIE) != 0U))
|
|
800941c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8009420: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8009424: 2b00 cmp r3, #0
|
|
8009426: d008 beq.n 800943a <HAL_UART_IRQHandler+0x5d2>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->TxISR != NULL)
|
|
8009428: 687b ldr r3, [r7, #4]
|
|
800942a: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
800942c: 2b00 cmp r3, #0
|
|
800942e: d01c beq.n 800946a <HAL_UART_IRQHandler+0x602>
|
|
{
|
|
huart->TxISR(huart);
|
|
8009430: 687b ldr r3, [r7, #4]
|
|
8009432: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8009434: 6878 ldr r0, [r7, #4]
|
|
8009436: 4798 blx r3
|
|
}
|
|
return;
|
|
8009438: e017 b.n 800946a <HAL_UART_IRQHandler+0x602>
|
|
}
|
|
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|
800943a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800943e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8009442: 2b00 cmp r3, #0
|
|
8009444: d012 beq.n 800946c <HAL_UART_IRQHandler+0x604>
|
|
8009446: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800944a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800944e: 2b00 cmp r3, #0
|
|
8009450: d00c beq.n 800946c <HAL_UART_IRQHandler+0x604>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
8009452: 6878 ldr r0, [r7, #4]
|
|
8009454: f000 fdc8 bl 8009fe8 <UART_EndTransmit_IT>
|
|
return;
|
|
8009458: e008 b.n 800946c <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
800945a: bf00 nop
|
|
800945c: e006 b.n 800946c <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
800945e: bf00 nop
|
|
8009460: e004 b.n 800946c <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
8009462: bf00 nop
|
|
8009464: e002 b.n 800946c <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
8009466: bf00 nop
|
|
8009468: e000 b.n 800946c <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
800946a: bf00 nop
|
|
HAL_UARTEx_RxFifoFullCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
}
|
|
#endif /* USART_CR1_FIFOEN */
|
|
}
|
|
800946c: 37e8 adds r7, #232 @ 0xe8
|
|
800946e: 46bd mov sp, r7
|
|
8009470: bd80 pop {r7, pc}
|
|
8009472: bf00 nop
|
|
|
|
08009474 <HAL_UART_ErrorCallback>:
|
|
* @brief UART error callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8009474: b480 push {r7}
|
|
8009476: b083 sub sp, #12
|
|
8009478: af00 add r7, sp, #0
|
|
800947a: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800947c: bf00 nop
|
|
800947e: 370c adds r7, #12
|
|
8009480: 46bd mov sp, r7
|
|
8009482: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009486: 4770 bx lr
|
|
|
|
08009488 <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
8009488: b480 push {r7}
|
|
800948a: b083 sub sp, #12
|
|
800948c: af00 add r7, sp, #0
|
|
800948e: 6078 str r0, [r7, #4]
|
|
8009490: 460b mov r3, r1
|
|
8009492: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8009494: bf00 nop
|
|
8009496: 370c adds r7, #12
|
|
8009498: 46bd mov sp, r7
|
|
800949a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800949e: 4770 bx lr
|
|
|
|
080094a0 <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
80094a0: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
80094a4: b08a sub sp, #40 @ 0x28
|
|
80094a6: af00 add r7, sp, #0
|
|
80094a8: 60f8 str r0, [r7, #12]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
80094aa: 2300 movs r3, #0
|
|
80094ac: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
80094b0: 68fb ldr r3, [r7, #12]
|
|
80094b2: 689a ldr r2, [r3, #8]
|
|
80094b4: 68fb ldr r3, [r7, #12]
|
|
80094b6: 691b ldr r3, [r3, #16]
|
|
80094b8: 431a orrs r2, r3
|
|
80094ba: 68fb ldr r3, [r7, #12]
|
|
80094bc: 695b ldr r3, [r3, #20]
|
|
80094be: 431a orrs r2, r3
|
|
80094c0: 68fb ldr r3, [r7, #12]
|
|
80094c2: 69db ldr r3, [r3, #28]
|
|
80094c4: 4313 orrs r3, r2
|
|
80094c6: 627b str r3, [r7, #36] @ 0x24
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
80094c8: 68fb ldr r3, [r7, #12]
|
|
80094ca: 681b ldr r3, [r3, #0]
|
|
80094cc: 681a ldr r2, [r3, #0]
|
|
80094ce: 4ba4 ldr r3, [pc, #656] @ (8009760 <UART_SetConfig+0x2c0>)
|
|
80094d0: 4013 ands r3, r2
|
|
80094d2: 68fa ldr r2, [r7, #12]
|
|
80094d4: 6812 ldr r2, [r2, #0]
|
|
80094d6: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80094d8: 430b orrs r3, r1
|
|
80094da: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
80094dc: 68fb ldr r3, [r7, #12]
|
|
80094de: 681b ldr r3, [r3, #0]
|
|
80094e0: 685b ldr r3, [r3, #4]
|
|
80094e2: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
80094e6: 68fb ldr r3, [r7, #12]
|
|
80094e8: 68da ldr r2, [r3, #12]
|
|
80094ea: 68fb ldr r3, [r7, #12]
|
|
80094ec: 681b ldr r3, [r3, #0]
|
|
80094ee: 430a orrs r2, r1
|
|
80094f0: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
80094f2: 68fb ldr r3, [r7, #12]
|
|
80094f4: 699b ldr r3, [r3, #24]
|
|
80094f6: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
80094f8: 68fb ldr r3, [r7, #12]
|
|
80094fa: 681b ldr r3, [r3, #0]
|
|
80094fc: 4a99 ldr r2, [pc, #612] @ (8009764 <UART_SetConfig+0x2c4>)
|
|
80094fe: 4293 cmp r3, r2
|
|
8009500: d004 beq.n 800950c <UART_SetConfig+0x6c>
|
|
{
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
8009502: 68fb ldr r3, [r7, #12]
|
|
8009504: 6a1b ldr r3, [r3, #32]
|
|
8009506: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8009508: 4313 orrs r3, r2
|
|
800950a: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
800950c: 68fb ldr r3, [r7, #12]
|
|
800950e: 681b ldr r3, [r3, #0]
|
|
8009510: 689b ldr r3, [r3, #8]
|
|
8009512: f423 6130 bic.w r1, r3, #2816 @ 0xb00
|
|
8009516: 68fb ldr r3, [r7, #12]
|
|
8009518: 681b ldr r3, [r3, #0]
|
|
800951a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800951c: 430a orrs r2, r1
|
|
800951e: 609a str r2, [r3, #8]
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
8009520: 68fb ldr r3, [r7, #12]
|
|
8009522: 681b ldr r3, [r3, #0]
|
|
8009524: 4a90 ldr r2, [pc, #576] @ (8009768 <UART_SetConfig+0x2c8>)
|
|
8009526: 4293 cmp r3, r2
|
|
8009528: d126 bne.n 8009578 <UART_SetConfig+0xd8>
|
|
800952a: 4b90 ldr r3, [pc, #576] @ (800976c <UART_SetConfig+0x2cc>)
|
|
800952c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8009530: f003 0303 and.w r3, r3, #3
|
|
8009534: 2b03 cmp r3, #3
|
|
8009536: d81b bhi.n 8009570 <UART_SetConfig+0xd0>
|
|
8009538: a201 add r2, pc, #4 @ (adr r2, 8009540 <UART_SetConfig+0xa0>)
|
|
800953a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800953e: bf00 nop
|
|
8009540: 08009551 .word 0x08009551
|
|
8009544: 08009561 .word 0x08009561
|
|
8009548: 08009559 .word 0x08009559
|
|
800954c: 08009569 .word 0x08009569
|
|
8009550: 2301 movs r3, #1
|
|
8009552: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009556: e116 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009558: 2302 movs r3, #2
|
|
800955a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800955e: e112 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009560: 2304 movs r3, #4
|
|
8009562: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009566: e10e b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009568: 2308 movs r3, #8
|
|
800956a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800956e: e10a b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009570: 2310 movs r3, #16
|
|
8009572: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009576: e106 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009578: 68fb ldr r3, [r7, #12]
|
|
800957a: 681b ldr r3, [r3, #0]
|
|
800957c: 4a7c ldr r2, [pc, #496] @ (8009770 <UART_SetConfig+0x2d0>)
|
|
800957e: 4293 cmp r3, r2
|
|
8009580: d138 bne.n 80095f4 <UART_SetConfig+0x154>
|
|
8009582: 4b7a ldr r3, [pc, #488] @ (800976c <UART_SetConfig+0x2cc>)
|
|
8009584: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8009588: f003 030c and.w r3, r3, #12
|
|
800958c: 2b0c cmp r3, #12
|
|
800958e: d82d bhi.n 80095ec <UART_SetConfig+0x14c>
|
|
8009590: a201 add r2, pc, #4 @ (adr r2, 8009598 <UART_SetConfig+0xf8>)
|
|
8009592: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009596: bf00 nop
|
|
8009598: 080095cd .word 0x080095cd
|
|
800959c: 080095ed .word 0x080095ed
|
|
80095a0: 080095ed .word 0x080095ed
|
|
80095a4: 080095ed .word 0x080095ed
|
|
80095a8: 080095dd .word 0x080095dd
|
|
80095ac: 080095ed .word 0x080095ed
|
|
80095b0: 080095ed .word 0x080095ed
|
|
80095b4: 080095ed .word 0x080095ed
|
|
80095b8: 080095d5 .word 0x080095d5
|
|
80095bc: 080095ed .word 0x080095ed
|
|
80095c0: 080095ed .word 0x080095ed
|
|
80095c4: 080095ed .word 0x080095ed
|
|
80095c8: 080095e5 .word 0x080095e5
|
|
80095cc: 2300 movs r3, #0
|
|
80095ce: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80095d2: e0d8 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80095d4: 2302 movs r3, #2
|
|
80095d6: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80095da: e0d4 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80095dc: 2304 movs r3, #4
|
|
80095de: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80095e2: e0d0 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80095e4: 2308 movs r3, #8
|
|
80095e6: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80095ea: e0cc b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80095ec: 2310 movs r3, #16
|
|
80095ee: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80095f2: e0c8 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80095f4: 68fb ldr r3, [r7, #12]
|
|
80095f6: 681b ldr r3, [r3, #0]
|
|
80095f8: 4a5e ldr r2, [pc, #376] @ (8009774 <UART_SetConfig+0x2d4>)
|
|
80095fa: 4293 cmp r3, r2
|
|
80095fc: d125 bne.n 800964a <UART_SetConfig+0x1aa>
|
|
80095fe: 4b5b ldr r3, [pc, #364] @ (800976c <UART_SetConfig+0x2cc>)
|
|
8009600: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8009604: f003 0330 and.w r3, r3, #48 @ 0x30
|
|
8009608: 2b30 cmp r3, #48 @ 0x30
|
|
800960a: d016 beq.n 800963a <UART_SetConfig+0x19a>
|
|
800960c: 2b30 cmp r3, #48 @ 0x30
|
|
800960e: d818 bhi.n 8009642 <UART_SetConfig+0x1a2>
|
|
8009610: 2b20 cmp r3, #32
|
|
8009612: d00a beq.n 800962a <UART_SetConfig+0x18a>
|
|
8009614: 2b20 cmp r3, #32
|
|
8009616: d814 bhi.n 8009642 <UART_SetConfig+0x1a2>
|
|
8009618: 2b00 cmp r3, #0
|
|
800961a: d002 beq.n 8009622 <UART_SetConfig+0x182>
|
|
800961c: 2b10 cmp r3, #16
|
|
800961e: d008 beq.n 8009632 <UART_SetConfig+0x192>
|
|
8009620: e00f b.n 8009642 <UART_SetConfig+0x1a2>
|
|
8009622: 2300 movs r3, #0
|
|
8009624: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009628: e0ad b.n 8009786 <UART_SetConfig+0x2e6>
|
|
800962a: 2302 movs r3, #2
|
|
800962c: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009630: e0a9 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009632: 2304 movs r3, #4
|
|
8009634: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009638: e0a5 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
800963a: 2308 movs r3, #8
|
|
800963c: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009640: e0a1 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009642: 2310 movs r3, #16
|
|
8009644: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009648: e09d b.n 8009786 <UART_SetConfig+0x2e6>
|
|
800964a: 68fb ldr r3, [r7, #12]
|
|
800964c: 681b ldr r3, [r3, #0]
|
|
800964e: 4a4a ldr r2, [pc, #296] @ (8009778 <UART_SetConfig+0x2d8>)
|
|
8009650: 4293 cmp r3, r2
|
|
8009652: d125 bne.n 80096a0 <UART_SetConfig+0x200>
|
|
8009654: 4b45 ldr r3, [pc, #276] @ (800976c <UART_SetConfig+0x2cc>)
|
|
8009656: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800965a: f003 03c0 and.w r3, r3, #192 @ 0xc0
|
|
800965e: 2bc0 cmp r3, #192 @ 0xc0
|
|
8009660: d016 beq.n 8009690 <UART_SetConfig+0x1f0>
|
|
8009662: 2bc0 cmp r3, #192 @ 0xc0
|
|
8009664: d818 bhi.n 8009698 <UART_SetConfig+0x1f8>
|
|
8009666: 2b80 cmp r3, #128 @ 0x80
|
|
8009668: d00a beq.n 8009680 <UART_SetConfig+0x1e0>
|
|
800966a: 2b80 cmp r3, #128 @ 0x80
|
|
800966c: d814 bhi.n 8009698 <UART_SetConfig+0x1f8>
|
|
800966e: 2b00 cmp r3, #0
|
|
8009670: d002 beq.n 8009678 <UART_SetConfig+0x1d8>
|
|
8009672: 2b40 cmp r3, #64 @ 0x40
|
|
8009674: d008 beq.n 8009688 <UART_SetConfig+0x1e8>
|
|
8009676: e00f b.n 8009698 <UART_SetConfig+0x1f8>
|
|
8009678: 2300 movs r3, #0
|
|
800967a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800967e: e082 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009680: 2302 movs r3, #2
|
|
8009682: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009686: e07e b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009688: 2304 movs r3, #4
|
|
800968a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800968e: e07a b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009690: 2308 movs r3, #8
|
|
8009692: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009696: e076 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009698: 2310 movs r3, #16
|
|
800969a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800969e: e072 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80096a0: 68fb ldr r3, [r7, #12]
|
|
80096a2: 681b ldr r3, [r3, #0]
|
|
80096a4: 4a35 ldr r2, [pc, #212] @ (800977c <UART_SetConfig+0x2dc>)
|
|
80096a6: 4293 cmp r3, r2
|
|
80096a8: d12a bne.n 8009700 <UART_SetConfig+0x260>
|
|
80096aa: 4b30 ldr r3, [pc, #192] @ (800976c <UART_SetConfig+0x2cc>)
|
|
80096ac: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80096b0: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80096b4: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80096b8: d01a beq.n 80096f0 <UART_SetConfig+0x250>
|
|
80096ba: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80096be: d81b bhi.n 80096f8 <UART_SetConfig+0x258>
|
|
80096c0: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80096c4: d00c beq.n 80096e0 <UART_SetConfig+0x240>
|
|
80096c6: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80096ca: d815 bhi.n 80096f8 <UART_SetConfig+0x258>
|
|
80096cc: 2b00 cmp r3, #0
|
|
80096ce: d003 beq.n 80096d8 <UART_SetConfig+0x238>
|
|
80096d0: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80096d4: d008 beq.n 80096e8 <UART_SetConfig+0x248>
|
|
80096d6: e00f b.n 80096f8 <UART_SetConfig+0x258>
|
|
80096d8: 2300 movs r3, #0
|
|
80096da: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80096de: e052 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80096e0: 2302 movs r3, #2
|
|
80096e2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80096e6: e04e b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80096e8: 2304 movs r3, #4
|
|
80096ea: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80096ee: e04a b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80096f0: 2308 movs r3, #8
|
|
80096f2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80096f6: e046 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
80096f8: 2310 movs r3, #16
|
|
80096fa: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80096fe: e042 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009700: 68fb ldr r3, [r7, #12]
|
|
8009702: 681b ldr r3, [r3, #0]
|
|
8009704: 4a17 ldr r2, [pc, #92] @ (8009764 <UART_SetConfig+0x2c4>)
|
|
8009706: 4293 cmp r3, r2
|
|
8009708: d13a bne.n 8009780 <UART_SetConfig+0x2e0>
|
|
800970a: 4b18 ldr r3, [pc, #96] @ (800976c <UART_SetConfig+0x2cc>)
|
|
800970c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8009710: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
8009714: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
8009718: d01a beq.n 8009750 <UART_SetConfig+0x2b0>
|
|
800971a: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
800971e: d81b bhi.n 8009758 <UART_SetConfig+0x2b8>
|
|
8009720: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8009724: d00c beq.n 8009740 <UART_SetConfig+0x2a0>
|
|
8009726: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
800972a: d815 bhi.n 8009758 <UART_SetConfig+0x2b8>
|
|
800972c: 2b00 cmp r3, #0
|
|
800972e: d003 beq.n 8009738 <UART_SetConfig+0x298>
|
|
8009730: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8009734: d008 beq.n 8009748 <UART_SetConfig+0x2a8>
|
|
8009736: e00f b.n 8009758 <UART_SetConfig+0x2b8>
|
|
8009738: 2300 movs r3, #0
|
|
800973a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800973e: e022 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009740: 2302 movs r3, #2
|
|
8009742: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009746: e01e b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009748: 2304 movs r3, #4
|
|
800974a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800974e: e01a b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009750: 2308 movs r3, #8
|
|
8009752: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8009756: e016 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009758: 2310 movs r3, #16
|
|
800975a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800975e: e012 b.n 8009786 <UART_SetConfig+0x2e6>
|
|
8009760: efff69f3 .word 0xefff69f3
|
|
8009764: 40008000 .word 0x40008000
|
|
8009768: 40013800 .word 0x40013800
|
|
800976c: 40021000 .word 0x40021000
|
|
8009770: 40004400 .word 0x40004400
|
|
8009774: 40004800 .word 0x40004800
|
|
8009778: 40004c00 .word 0x40004c00
|
|
800977c: 40005000 .word 0x40005000
|
|
8009780: 2310 movs r3, #16
|
|
8009782: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
|
|
/* Check LPUART instance */
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
8009786: 68fb ldr r3, [r7, #12]
|
|
8009788: 681b ldr r3, [r3, #0]
|
|
800978a: 4a9f ldr r2, [pc, #636] @ (8009a08 <UART_SetConfig+0x568>)
|
|
800978c: 4293 cmp r3, r2
|
|
800978e: d17a bne.n 8009886 <UART_SetConfig+0x3e6>
|
|
{
|
|
/* Retrieve frequency clock */
|
|
switch (clocksource)
|
|
8009790: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8009794: 2b08 cmp r3, #8
|
|
8009796: d824 bhi.n 80097e2 <UART_SetConfig+0x342>
|
|
8009798: a201 add r2, pc, #4 @ (adr r2, 80097a0 <UART_SetConfig+0x300>)
|
|
800979a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800979e: bf00 nop
|
|
80097a0: 080097c5 .word 0x080097c5
|
|
80097a4: 080097e3 .word 0x080097e3
|
|
80097a8: 080097cd .word 0x080097cd
|
|
80097ac: 080097e3 .word 0x080097e3
|
|
80097b0: 080097d3 .word 0x080097d3
|
|
80097b4: 080097e3 .word 0x080097e3
|
|
80097b8: 080097e3 .word 0x080097e3
|
|
80097bc: 080097e3 .word 0x080097e3
|
|
80097c0: 080097db .word 0x080097db
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
80097c4: f7fc fe58 bl 8006478 <HAL_RCC_GetPCLK1Freq>
|
|
80097c8: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80097ca: e010 b.n 80097ee <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
80097cc: 4b8f ldr r3, [pc, #572] @ (8009a0c <UART_SetConfig+0x56c>)
|
|
80097ce: 61fb str r3, [r7, #28]
|
|
break;
|
|
80097d0: e00d b.n 80097ee <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
80097d2: f7fc fdb9 bl 8006348 <HAL_RCC_GetSysClockFreq>
|
|
80097d6: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80097d8: e009 b.n 80097ee <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
80097da: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80097de: 61fb str r3, [r7, #28]
|
|
break;
|
|
80097e0: e005 b.n 80097ee <UART_SetConfig+0x34e>
|
|
default:
|
|
pclk = 0U;
|
|
80097e2: 2300 movs r3, #0
|
|
80097e4: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
80097e6: 2301 movs r3, #1
|
|
80097e8: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
80097ec: bf00 nop
|
|
}
|
|
|
|
/* If proper clock source reported */
|
|
if (pclk != 0U)
|
|
80097ee: 69fb ldr r3, [r7, #28]
|
|
80097f0: 2b00 cmp r3, #0
|
|
80097f2: f000 80fb beq.w 80099ec <UART_SetConfig+0x54c>
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
#else
|
|
/* No Prescaler applicable */
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
80097f6: 68fb ldr r3, [r7, #12]
|
|
80097f8: 685a ldr r2, [r3, #4]
|
|
80097fa: 4613 mov r3, r2
|
|
80097fc: 005b lsls r3, r3, #1
|
|
80097fe: 4413 add r3, r2
|
|
8009800: 69fa ldr r2, [r7, #28]
|
|
8009802: 429a cmp r2, r3
|
|
8009804: d305 bcc.n 8009812 <UART_SetConfig+0x372>
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
|
8009806: 68fb ldr r3, [r7, #12]
|
|
8009808: 685b ldr r3, [r3, #4]
|
|
800980a: 031b lsls r3, r3, #12
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
800980c: 69fa ldr r2, [r7, #28]
|
|
800980e: 429a cmp r2, r3
|
|
8009810: d903 bls.n 800981a <UART_SetConfig+0x37a>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8009812: 2301 movs r3, #1
|
|
8009814: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
8009818: e0e8 b.n 80099ec <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
|
800981a: 69fb ldr r3, [r7, #28]
|
|
800981c: 2200 movs r2, #0
|
|
800981e: 461c mov r4, r3
|
|
8009820: 4615 mov r5, r2
|
|
8009822: f04f 0200 mov.w r2, #0
|
|
8009826: f04f 0300 mov.w r3, #0
|
|
800982a: 022b lsls r3, r5, #8
|
|
800982c: ea43 6314 orr.w r3, r3, r4, lsr #24
|
|
8009830: 0222 lsls r2, r4, #8
|
|
8009832: 68f9 ldr r1, [r7, #12]
|
|
8009834: 6849 ldr r1, [r1, #4]
|
|
8009836: 0849 lsrs r1, r1, #1
|
|
8009838: 2000 movs r0, #0
|
|
800983a: 4688 mov r8, r1
|
|
800983c: 4681 mov r9, r0
|
|
800983e: eb12 0a08 adds.w sl, r2, r8
|
|
8009842: eb43 0b09 adc.w fp, r3, r9
|
|
8009846: 68fb ldr r3, [r7, #12]
|
|
8009848: 685b ldr r3, [r3, #4]
|
|
800984a: 2200 movs r2, #0
|
|
800984c: 603b str r3, [r7, #0]
|
|
800984e: 607a str r2, [r7, #4]
|
|
8009850: e9d7 2300 ldrd r2, r3, [r7]
|
|
8009854: 4650 mov r0, sl
|
|
8009856: 4659 mov r1, fp
|
|
8009858: f7f7 fa16 bl 8000c88 <__aeabi_uldivmod>
|
|
800985c: 4602 mov r2, r0
|
|
800985e: 460b mov r3, r1
|
|
8009860: 4613 mov r3, r2
|
|
8009862: 61bb str r3, [r7, #24]
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
8009864: 69bb ldr r3, [r7, #24]
|
|
8009866: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
800986a: d308 bcc.n 800987e <UART_SetConfig+0x3de>
|
|
800986c: 69bb ldr r3, [r7, #24]
|
|
800986e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8009872: d204 bcs.n 800987e <UART_SetConfig+0x3de>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
8009874: 68fb ldr r3, [r7, #12]
|
|
8009876: 681b ldr r3, [r3, #0]
|
|
8009878: 69ba ldr r2, [r7, #24]
|
|
800987a: 60da str r2, [r3, #12]
|
|
800987c: e0b6 b.n 80099ec <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800987e: 2301 movs r3, #1
|
|
8009880: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
8009884: e0b2 b.n 80099ec <UART_SetConfig+0x54c>
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
} /* if (pclk != 0) */
|
|
}
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8009886: 68fb ldr r3, [r7, #12]
|
|
8009888: 69db ldr r3, [r3, #28]
|
|
800988a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800988e: d15e bne.n 800994e <UART_SetConfig+0x4ae>
|
|
{
|
|
switch (clocksource)
|
|
8009890: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8009894: 2b08 cmp r3, #8
|
|
8009896: d828 bhi.n 80098ea <UART_SetConfig+0x44a>
|
|
8009898: a201 add r2, pc, #4 @ (adr r2, 80098a0 <UART_SetConfig+0x400>)
|
|
800989a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800989e: bf00 nop
|
|
80098a0: 080098c5 .word 0x080098c5
|
|
80098a4: 080098cd .word 0x080098cd
|
|
80098a8: 080098d5 .word 0x080098d5
|
|
80098ac: 080098eb .word 0x080098eb
|
|
80098b0: 080098db .word 0x080098db
|
|
80098b4: 080098eb .word 0x080098eb
|
|
80098b8: 080098eb .word 0x080098eb
|
|
80098bc: 080098eb .word 0x080098eb
|
|
80098c0: 080098e3 .word 0x080098e3
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
80098c4: f7fc fdd8 bl 8006478 <HAL_RCC_GetPCLK1Freq>
|
|
80098c8: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80098ca: e014 b.n 80098f6 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
80098cc: f7fc fdea bl 80064a4 <HAL_RCC_GetPCLK2Freq>
|
|
80098d0: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80098d2: e010 b.n 80098f6 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
80098d4: 4b4d ldr r3, [pc, #308] @ (8009a0c <UART_SetConfig+0x56c>)
|
|
80098d6: 61fb str r3, [r7, #28]
|
|
break;
|
|
80098d8: e00d b.n 80098f6 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
80098da: f7fc fd35 bl 8006348 <HAL_RCC_GetSysClockFreq>
|
|
80098de: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80098e0: e009 b.n 80098f6 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
80098e2: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80098e6: 61fb str r3, [r7, #28]
|
|
break;
|
|
80098e8: e005 b.n 80098f6 <UART_SetConfig+0x456>
|
|
default:
|
|
pclk = 0U;
|
|
80098ea: 2300 movs r3, #0
|
|
80098ec: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
80098ee: 2301 movs r3, #1
|
|
80098f0: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
80098f4: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
80098f6: 69fb ldr r3, [r7, #28]
|
|
80098f8: 2b00 cmp r3, #0
|
|
80098fa: d077 beq.n 80099ec <UART_SetConfig+0x54c>
|
|
{
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
80098fc: 69fb ldr r3, [r7, #28]
|
|
80098fe: 005a lsls r2, r3, #1
|
|
8009900: 68fb ldr r3, [r7, #12]
|
|
8009902: 685b ldr r3, [r3, #4]
|
|
8009904: 085b lsrs r3, r3, #1
|
|
8009906: 441a add r2, r3
|
|
8009908: 68fb ldr r3, [r7, #12]
|
|
800990a: 685b ldr r3, [r3, #4]
|
|
800990c: fbb2 f3f3 udiv r3, r2, r3
|
|
8009910: 61bb str r3, [r7, #24]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8009912: 69bb ldr r3, [r7, #24]
|
|
8009914: 2b0f cmp r3, #15
|
|
8009916: d916 bls.n 8009946 <UART_SetConfig+0x4a6>
|
|
8009918: 69bb ldr r3, [r7, #24]
|
|
800991a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800991e: d212 bcs.n 8009946 <UART_SetConfig+0x4a6>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8009920: 69bb ldr r3, [r7, #24]
|
|
8009922: b29b uxth r3, r3
|
|
8009924: f023 030f bic.w r3, r3, #15
|
|
8009928: 82fb strh r3, [r7, #22]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
800992a: 69bb ldr r3, [r7, #24]
|
|
800992c: 085b lsrs r3, r3, #1
|
|
800992e: b29b uxth r3, r3
|
|
8009930: f003 0307 and.w r3, r3, #7
|
|
8009934: b29a uxth r2, r3
|
|
8009936: 8afb ldrh r3, [r7, #22]
|
|
8009938: 4313 orrs r3, r2
|
|
800993a: 82fb strh r3, [r7, #22]
|
|
huart->Instance->BRR = brrtemp;
|
|
800993c: 68fb ldr r3, [r7, #12]
|
|
800993e: 681b ldr r3, [r3, #0]
|
|
8009940: 8afa ldrh r2, [r7, #22]
|
|
8009942: 60da str r2, [r3, #12]
|
|
8009944: e052 b.n 80099ec <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8009946: 2301 movs r3, #1
|
|
8009948: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
800994c: e04e b.n 80099ec <UART_SetConfig+0x54c>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
800994e: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8009952: 2b08 cmp r3, #8
|
|
8009954: d827 bhi.n 80099a6 <UART_SetConfig+0x506>
|
|
8009956: a201 add r2, pc, #4 @ (adr r2, 800995c <UART_SetConfig+0x4bc>)
|
|
8009958: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800995c: 08009981 .word 0x08009981
|
|
8009960: 08009989 .word 0x08009989
|
|
8009964: 08009991 .word 0x08009991
|
|
8009968: 080099a7 .word 0x080099a7
|
|
800996c: 08009997 .word 0x08009997
|
|
8009970: 080099a7 .word 0x080099a7
|
|
8009974: 080099a7 .word 0x080099a7
|
|
8009978: 080099a7 .word 0x080099a7
|
|
800997c: 0800999f .word 0x0800999f
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8009980: f7fc fd7a bl 8006478 <HAL_RCC_GetPCLK1Freq>
|
|
8009984: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8009986: e014 b.n 80099b2 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8009988: f7fc fd8c bl 80064a4 <HAL_RCC_GetPCLK2Freq>
|
|
800998c: 61f8 str r0, [r7, #28]
|
|
break;
|
|
800998e: e010 b.n 80099b2 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8009990: 4b1e ldr r3, [pc, #120] @ (8009a0c <UART_SetConfig+0x56c>)
|
|
8009992: 61fb str r3, [r7, #28]
|
|
break;
|
|
8009994: e00d b.n 80099b2 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8009996: f7fc fcd7 bl 8006348 <HAL_RCC_GetSysClockFreq>
|
|
800999a: 61f8 str r0, [r7, #28]
|
|
break;
|
|
800999c: e009 b.n 80099b2 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
800999e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80099a2: 61fb str r3, [r7, #28]
|
|
break;
|
|
80099a4: e005 b.n 80099b2 <UART_SetConfig+0x512>
|
|
default:
|
|
pclk = 0U;
|
|
80099a6: 2300 movs r3, #0
|
|
80099a8: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
80099aa: 2301 movs r3, #1
|
|
80099ac: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
80099b0: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
80099b2: 69fb ldr r3, [r7, #28]
|
|
80099b4: 2b00 cmp r3, #0
|
|
80099b6: d019 beq.n 80099ec <UART_SetConfig+0x54c>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
80099b8: 68fb ldr r3, [r7, #12]
|
|
80099ba: 685b ldr r3, [r3, #4]
|
|
80099bc: 085a lsrs r2, r3, #1
|
|
80099be: 69fb ldr r3, [r7, #28]
|
|
80099c0: 441a add r2, r3
|
|
80099c2: 68fb ldr r3, [r7, #12]
|
|
80099c4: 685b ldr r3, [r3, #4]
|
|
80099c6: fbb2 f3f3 udiv r3, r2, r3
|
|
80099ca: 61bb str r3, [r7, #24]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
80099cc: 69bb ldr r3, [r7, #24]
|
|
80099ce: 2b0f cmp r3, #15
|
|
80099d0: d909 bls.n 80099e6 <UART_SetConfig+0x546>
|
|
80099d2: 69bb ldr r3, [r7, #24]
|
|
80099d4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
80099d8: d205 bcs.n 80099e6 <UART_SetConfig+0x546>
|
|
{
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
80099da: 69bb ldr r3, [r7, #24]
|
|
80099dc: b29a uxth r2, r3
|
|
80099de: 68fb ldr r3, [r7, #12]
|
|
80099e0: 681b ldr r3, [r3, #0]
|
|
80099e2: 60da str r2, [r3, #12]
|
|
80099e4: e002 b.n 80099ec <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
80099e6: 2301 movs r3, #1
|
|
80099e8: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
huart->NbTxDataToProcess = 1;
|
|
huart->NbRxDataToProcess = 1;
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
80099ec: 68fb ldr r3, [r7, #12]
|
|
80099ee: 2200 movs r2, #0
|
|
80099f0: 669a str r2, [r3, #104] @ 0x68
|
|
huart->TxISR = NULL;
|
|
80099f2: 68fb ldr r3, [r7, #12]
|
|
80099f4: 2200 movs r2, #0
|
|
80099f6: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
return ret;
|
|
80099f8: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
|
|
}
|
|
80099fc: 4618 mov r0, r3
|
|
80099fe: 3728 adds r7, #40 @ 0x28
|
|
8009a00: 46bd mov sp, r7
|
|
8009a02: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8009a06: bf00 nop
|
|
8009a08: 40008000 .word 0x40008000
|
|
8009a0c: 00f42400 .word 0x00f42400
|
|
|
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08009a10 <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8009a10: b480 push {r7}
|
|
8009a12: b083 sub sp, #12
|
|
8009a14: af00 add r7, sp, #0
|
|
8009a16: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
8009a18: 687b ldr r3, [r7, #4]
|
|
8009a1a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8009a1c: f003 0308 and.w r3, r3, #8
|
|
8009a20: 2b00 cmp r3, #0
|
|
8009a22: d00a beq.n 8009a3a <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
8009a24: 687b ldr r3, [r7, #4]
|
|
8009a26: 681b ldr r3, [r3, #0]
|
|
8009a28: 685b ldr r3, [r3, #4]
|
|
8009a2a: f423 4100 bic.w r1, r3, #32768 @ 0x8000
|
|
8009a2e: 687b ldr r3, [r7, #4]
|
|
8009a30: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8009a32: 687b ldr r3, [r7, #4]
|
|
8009a34: 681b ldr r3, [r3, #0]
|
|
8009a36: 430a orrs r2, r1
|
|
8009a38: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
8009a3a: 687b ldr r3, [r7, #4]
|
|
8009a3c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8009a3e: f003 0301 and.w r3, r3, #1
|
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8009a42: 2b00 cmp r3, #0
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8009a44: d00a beq.n 8009a5c <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
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|
8009a46: 687b ldr r3, [r7, #4]
|
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8009a48: 681b ldr r3, [r3, #0]
|
|
8009a4a: 685b ldr r3, [r3, #4]
|
|
8009a4c: f423 3100 bic.w r1, r3, #131072 @ 0x20000
|
|
8009a50: 687b ldr r3, [r7, #4]
|
|
8009a52: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
8009a54: 687b ldr r3, [r7, #4]
|
|
8009a56: 681b ldr r3, [r3, #0]
|
|
8009a58: 430a orrs r2, r1
|
|
8009a5a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8009a5c: 687b ldr r3, [r7, #4]
|
|
8009a5e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8009a60: f003 0302 and.w r3, r3, #2
|
|
8009a64: 2b00 cmp r3, #0
|
|
8009a66: d00a beq.n 8009a7e <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
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8009a68: 687b ldr r3, [r7, #4]
|
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8009a6a: 681b ldr r3, [r3, #0]
|
|
8009a6c: 685b ldr r3, [r3, #4]
|
|
8009a6e: f423 3180 bic.w r1, r3, #65536 @ 0x10000
|
|
8009a72: 687b ldr r3, [r7, #4]
|
|
8009a74: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8009a76: 687b ldr r3, [r7, #4]
|
|
8009a78: 681b ldr r3, [r3, #0]
|
|
8009a7a: 430a orrs r2, r1
|
|
8009a7c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8009a7e: 687b ldr r3, [r7, #4]
|
|
8009a80: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8009a82: f003 0304 and.w r3, r3, #4
|
|
8009a86: 2b00 cmp r3, #0
|
|
8009a88: d00a beq.n 8009aa0 <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
8009a8a: 687b ldr r3, [r7, #4]
|
|
8009a8c: 681b ldr r3, [r3, #0]
|
|
8009a8e: 685b ldr r3, [r3, #4]
|
|
8009a90: f423 2180 bic.w r1, r3, #262144 @ 0x40000
|
|
8009a94: 687b ldr r3, [r7, #4]
|
|
8009a96: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8009a98: 687b ldr r3, [r7, #4]
|
|
8009a9a: 681b ldr r3, [r3, #0]
|
|
8009a9c: 430a orrs r2, r1
|
|
8009a9e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8009aa0: 687b ldr r3, [r7, #4]
|
|
8009aa2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8009aa4: f003 0310 and.w r3, r3, #16
|
|
8009aa8: 2b00 cmp r3, #0
|
|
8009aaa: d00a beq.n 8009ac2 <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
8009aac: 687b ldr r3, [r7, #4]
|
|
8009aae: 681b ldr r3, [r3, #0]
|
|
8009ab0: 689b ldr r3, [r3, #8]
|
|
8009ab2: f423 5180 bic.w r1, r3, #4096 @ 0x1000
|
|
8009ab6: 687b ldr r3, [r7, #4]
|
|
8009ab8: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8009aba: 687b ldr r3, [r7, #4]
|
|
8009abc: 681b ldr r3, [r3, #0]
|
|
8009abe: 430a orrs r2, r1
|
|
8009ac0: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8009ac2: 687b ldr r3, [r7, #4]
|
|
8009ac4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8009ac6: f003 0320 and.w r3, r3, #32
|
|
8009aca: 2b00 cmp r3, #0
|
|
8009acc: d00a beq.n 8009ae4 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
8009ace: 687b ldr r3, [r7, #4]
|
|
8009ad0: 681b ldr r3, [r3, #0]
|
|
8009ad2: 689b ldr r3, [r3, #8]
|
|
8009ad4: f423 5100 bic.w r1, r3, #8192 @ 0x2000
|
|
8009ad8: 687b ldr r3, [r7, #4]
|
|
8009ada: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8009adc: 687b ldr r3, [r7, #4]
|
|
8009ade: 681b ldr r3, [r3, #0]
|
|
8009ae0: 430a orrs r2, r1
|
|
8009ae2: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
8009ae4: 687b ldr r3, [r7, #4]
|
|
8009ae6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8009ae8: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8009aec: 2b00 cmp r3, #0
|
|
8009aee: d01a beq.n 8009b26 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
8009af0: 687b ldr r3, [r7, #4]
|
|
8009af2: 681b ldr r3, [r3, #0]
|
|
8009af4: 685b ldr r3, [r3, #4]
|
|
8009af6: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
|
|
8009afa: 687b ldr r3, [r7, #4]
|
|
8009afc: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8009afe: 687b ldr r3, [r7, #4]
|
|
8009b00: 681b ldr r3, [r3, #0]
|
|
8009b02: 430a orrs r2, r1
|
|
8009b04: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
8009b06: 687b ldr r3, [r7, #4]
|
|
8009b08: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8009b0a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8009b0e: d10a bne.n 8009b26 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
8009b10: 687b ldr r3, [r7, #4]
|
|
8009b12: 681b ldr r3, [r3, #0]
|
|
8009b14: 685b ldr r3, [r3, #4]
|
|
8009b16: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
|
|
8009b1a: 687b ldr r3, [r7, #4]
|
|
8009b1c: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8009b1e: 687b ldr r3, [r7, #4]
|
|
8009b20: 681b ldr r3, [r3, #0]
|
|
8009b22: 430a orrs r2, r1
|
|
8009b24: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
8009b26: 687b ldr r3, [r7, #4]
|
|
8009b28: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8009b2a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8009b2e: 2b00 cmp r3, #0
|
|
8009b30: d00a beq.n 8009b48 <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
8009b32: 687b ldr r3, [r7, #4]
|
|
8009b34: 681b ldr r3, [r3, #0]
|
|
8009b36: 685b ldr r3, [r3, #4]
|
|
8009b38: f423 2100 bic.w r1, r3, #524288 @ 0x80000
|
|
8009b3c: 687b ldr r3, [r7, #4]
|
|
8009b3e: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
8009b40: 687b ldr r3, [r7, #4]
|
|
8009b42: 681b ldr r3, [r3, #0]
|
|
8009b44: 430a orrs r2, r1
|
|
8009b46: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
8009b48: bf00 nop
|
|
8009b4a: 370c adds r7, #12
|
|
8009b4c: 46bd mov sp, r7
|
|
8009b4e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009b52: 4770 bx lr
|
|
|
|
08009b54 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8009b54: b580 push {r7, lr}
|
|
8009b56: b098 sub sp, #96 @ 0x60
|
|
8009b58: af02 add r7, sp, #8
|
|
8009b5a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8009b5c: 687b ldr r3, [r7, #4]
|
|
8009b5e: 2200 movs r2, #0
|
|
8009b60: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8009b64: f7fa f8cc bl 8003d00 <HAL_GetTick>
|
|
8009b68: 6578 str r0, [r7, #84] @ 0x54
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
8009b6a: 687b ldr r3, [r7, #4]
|
|
8009b6c: 681b ldr r3, [r3, #0]
|
|
8009b6e: 681b ldr r3, [r3, #0]
|
|
8009b70: f003 0308 and.w r3, r3, #8
|
|
8009b74: 2b08 cmp r3, #8
|
|
8009b76: d12e bne.n 8009bd6 <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8009b78: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8009b7c: 9300 str r3, [sp, #0]
|
|
8009b7e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8009b80: 2200 movs r2, #0
|
|
8009b82: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
8009b86: 6878 ldr r0, [r7, #4]
|
|
8009b88: f000 f88c bl 8009ca4 <UART_WaitOnFlagUntilTimeout>
|
|
8009b8c: 4603 mov r3, r0
|
|
8009b8e: 2b00 cmp r3, #0
|
|
8009b90: d021 beq.n 8009bd6 <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
|
|
8009b92: 687b ldr r3, [r7, #4]
|
|
8009b94: 681b ldr r3, [r3, #0]
|
|
8009b96: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009b98: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8009b9a: e853 3f00 ldrex r3, [r3]
|
|
8009b9e: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8009ba0: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8009ba2: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8009ba6: 653b str r3, [r7, #80] @ 0x50
|
|
8009ba8: 687b ldr r3, [r7, #4]
|
|
8009baa: 681b ldr r3, [r3, #0]
|
|
8009bac: 461a mov r2, r3
|
|
8009bae: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8009bb0: 647b str r3, [r7, #68] @ 0x44
|
|
8009bb2: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009bb4: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8009bb6: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8009bb8: e841 2300 strex r3, r2, [r1]
|
|
8009bbc: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8009bbe: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8009bc0: 2b00 cmp r3, #0
|
|
8009bc2: d1e6 bne.n 8009b92 <UART_CheckIdleState+0x3e>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8009bc4: 687b ldr r3, [r7, #4]
|
|
8009bc6: 2220 movs r2, #32
|
|
8009bc8: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8009bca: 687b ldr r3, [r7, #4]
|
|
8009bcc: 2200 movs r2, #0
|
|
8009bce: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8009bd2: 2303 movs r3, #3
|
|
8009bd4: e062 b.n 8009c9c <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
8009bd6: 687b ldr r3, [r7, #4]
|
|
8009bd8: 681b ldr r3, [r3, #0]
|
|
8009bda: 681b ldr r3, [r3, #0]
|
|
8009bdc: f003 0304 and.w r3, r3, #4
|
|
8009be0: 2b04 cmp r3, #4
|
|
8009be2: d149 bne.n 8009c78 <UART_CheckIdleState+0x124>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8009be4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8009be8: 9300 str r3, [sp, #0]
|
|
8009bea: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8009bec: 2200 movs r2, #0
|
|
8009bee: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
8009bf2: 6878 ldr r0, [r7, #4]
|
|
8009bf4: f000 f856 bl 8009ca4 <UART_WaitOnFlagUntilTimeout>
|
|
8009bf8: 4603 mov r3, r0
|
|
8009bfa: 2b00 cmp r3, #0
|
|
8009bfc: d03c beq.n 8009c78 <UART_CheckIdleState+0x124>
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8009bfe: 687b ldr r3, [r7, #4]
|
|
8009c00: 681b ldr r3, [r3, #0]
|
|
8009c02: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009c04: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8009c06: e853 3f00 ldrex r3, [r3]
|
|
8009c0a: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8009c0c: 6a3b ldr r3, [r7, #32]
|
|
8009c0e: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8009c12: 64fb str r3, [r7, #76] @ 0x4c
|
|
8009c14: 687b ldr r3, [r7, #4]
|
|
8009c16: 681b ldr r3, [r3, #0]
|
|
8009c18: 461a mov r2, r3
|
|
8009c1a: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8009c1c: 633b str r3, [r7, #48] @ 0x30
|
|
8009c1e: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009c20: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8009c22: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8009c24: e841 2300 strex r3, r2, [r1]
|
|
8009c28: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8009c2a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009c2c: 2b00 cmp r3, #0
|
|
8009c2e: d1e6 bne.n 8009bfe <UART_CheckIdleState+0xaa>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8009c30: 687b ldr r3, [r7, #4]
|
|
8009c32: 681b ldr r3, [r3, #0]
|
|
8009c34: 3308 adds r3, #8
|
|
8009c36: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009c38: 693b ldr r3, [r7, #16]
|
|
8009c3a: e853 3f00 ldrex r3, [r3]
|
|
8009c3e: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8009c40: 68fb ldr r3, [r7, #12]
|
|
8009c42: f023 0301 bic.w r3, r3, #1
|
|
8009c46: 64bb str r3, [r7, #72] @ 0x48
|
|
8009c48: 687b ldr r3, [r7, #4]
|
|
8009c4a: 681b ldr r3, [r3, #0]
|
|
8009c4c: 3308 adds r3, #8
|
|
8009c4e: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8009c50: 61fa str r2, [r7, #28]
|
|
8009c52: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009c54: 69b9 ldr r1, [r7, #24]
|
|
8009c56: 69fa ldr r2, [r7, #28]
|
|
8009c58: e841 2300 strex r3, r2, [r1]
|
|
8009c5c: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8009c5e: 697b ldr r3, [r7, #20]
|
|
8009c60: 2b00 cmp r3, #0
|
|
8009c62: d1e5 bne.n 8009c30 <UART_CheckIdleState+0xdc>
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8009c64: 687b ldr r3, [r7, #4]
|
|
8009c66: 2220 movs r2, #32
|
|
8009c68: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8009c6c: 687b ldr r3, [r7, #4]
|
|
8009c6e: 2200 movs r2, #0
|
|
8009c70: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8009c74: 2303 movs r3, #3
|
|
8009c76: e011 b.n 8009c9c <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8009c78: 687b ldr r3, [r7, #4]
|
|
8009c7a: 2220 movs r2, #32
|
|
8009c7c: 67da str r2, [r3, #124] @ 0x7c
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8009c7e: 687b ldr r3, [r7, #4]
|
|
8009c80: 2220 movs r2, #32
|
|
8009c82: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8009c86: 687b ldr r3, [r7, #4]
|
|
8009c88: 2200 movs r2, #0
|
|
8009c8a: 661a str r2, [r3, #96] @ 0x60
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8009c8c: 687b ldr r3, [r7, #4]
|
|
8009c8e: 2200 movs r2, #0
|
|
8009c90: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8009c92: 687b ldr r3, [r7, #4]
|
|
8009c94: 2200 movs r2, #0
|
|
8009c96: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_OK;
|
|
8009c9a: 2300 movs r3, #0
|
|
}
|
|
8009c9c: 4618 mov r0, r3
|
|
8009c9e: 3758 adds r7, #88 @ 0x58
|
|
8009ca0: 46bd mov sp, r7
|
|
8009ca2: bd80 pop {r7, pc}
|
|
|
|
08009ca4 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8009ca4: b580 push {r7, lr}
|
|
8009ca6: b084 sub sp, #16
|
|
8009ca8: af00 add r7, sp, #0
|
|
8009caa: 60f8 str r0, [r7, #12]
|
|
8009cac: 60b9 str r1, [r7, #8]
|
|
8009cae: 603b str r3, [r7, #0]
|
|
8009cb0: 4613 mov r3, r2
|
|
8009cb2: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8009cb4: e04f b.n 8009d56 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8009cb6: 69bb ldr r3, [r7, #24]
|
|
8009cb8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8009cbc: d04b beq.n 8009d56 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8009cbe: f7fa f81f bl 8003d00 <HAL_GetTick>
|
|
8009cc2: 4602 mov r2, r0
|
|
8009cc4: 683b ldr r3, [r7, #0]
|
|
8009cc6: 1ad3 subs r3, r2, r3
|
|
8009cc8: 69ba ldr r2, [r7, #24]
|
|
8009cca: 429a cmp r2, r3
|
|
8009ccc: d302 bcc.n 8009cd4 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
8009cce: 69bb ldr r3, [r7, #24]
|
|
8009cd0: 2b00 cmp r3, #0
|
|
8009cd2: d101 bne.n 8009cd8 <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
8009cd4: 2303 movs r3, #3
|
|
8009cd6: e04e b.n 8009d76 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
8009cd8: 68fb ldr r3, [r7, #12]
|
|
8009cda: 681b ldr r3, [r3, #0]
|
|
8009cdc: 681b ldr r3, [r3, #0]
|
|
8009cde: f003 0304 and.w r3, r3, #4
|
|
8009ce2: 2b00 cmp r3, #0
|
|
8009ce4: d037 beq.n 8009d56 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8009ce6: 68bb ldr r3, [r7, #8]
|
|
8009ce8: 2b80 cmp r3, #128 @ 0x80
|
|
8009cea: d034 beq.n 8009d56 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8009cec: 68bb ldr r3, [r7, #8]
|
|
8009cee: 2b40 cmp r3, #64 @ 0x40
|
|
8009cf0: d031 beq.n 8009d56 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
8009cf2: 68fb ldr r3, [r7, #12]
|
|
8009cf4: 681b ldr r3, [r3, #0]
|
|
8009cf6: 69db ldr r3, [r3, #28]
|
|
8009cf8: f003 0308 and.w r3, r3, #8
|
|
8009cfc: 2b08 cmp r3, #8
|
|
8009cfe: d110 bne.n 8009d22 <UART_WaitOnFlagUntilTimeout+0x7e>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8009d00: 68fb ldr r3, [r7, #12]
|
|
8009d02: 681b ldr r3, [r3, #0]
|
|
8009d04: 2208 movs r2, #8
|
|
8009d06: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8009d08: 68f8 ldr r0, [r7, #12]
|
|
8009d0a: f000 f838 bl 8009d7e <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
8009d0e: 68fb ldr r3, [r7, #12]
|
|
8009d10: 2208 movs r2, #8
|
|
8009d12: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8009d16: 68fb ldr r3, [r7, #12]
|
|
8009d18: 2200 movs r2, #0
|
|
8009d1a: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_ERROR;
|
|
8009d1e: 2301 movs r3, #1
|
|
8009d20: e029 b.n 8009d76 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
8009d22: 68fb ldr r3, [r7, #12]
|
|
8009d24: 681b ldr r3, [r3, #0]
|
|
8009d26: 69db ldr r3, [r3, #28]
|
|
8009d28: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8009d2c: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8009d30: d111 bne.n 8009d56 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8009d32: 68fb ldr r3, [r7, #12]
|
|
8009d34: 681b ldr r3, [r3, #0]
|
|
8009d36: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8009d3a: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8009d3c: 68f8 ldr r0, [r7, #12]
|
|
8009d3e: f000 f81e bl 8009d7e <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
8009d42: 68fb ldr r3, [r7, #12]
|
|
8009d44: 2220 movs r2, #32
|
|
8009d46: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8009d4a: 68fb ldr r3, [r7, #12]
|
|
8009d4c: 2200 movs r2, #0
|
|
8009d4e: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_TIMEOUT;
|
|
8009d52: 2303 movs r3, #3
|
|
8009d54: e00f b.n 8009d76 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8009d56: 68fb ldr r3, [r7, #12]
|
|
8009d58: 681b ldr r3, [r3, #0]
|
|
8009d5a: 69da ldr r2, [r3, #28]
|
|
8009d5c: 68bb ldr r3, [r7, #8]
|
|
8009d5e: 4013 ands r3, r2
|
|
8009d60: 68ba ldr r2, [r7, #8]
|
|
8009d62: 429a cmp r2, r3
|
|
8009d64: bf0c ite eq
|
|
8009d66: 2301 moveq r3, #1
|
|
8009d68: 2300 movne r3, #0
|
|
8009d6a: b2db uxtb r3, r3
|
|
8009d6c: 461a mov r2, r3
|
|
8009d6e: 79fb ldrb r3, [r7, #7]
|
|
8009d70: 429a cmp r2, r3
|
|
8009d72: d0a0 beq.n 8009cb6 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8009d74: 2300 movs r3, #0
|
|
}
|
|
8009d76: 4618 mov r0, r3
|
|
8009d78: 3710 adds r7, #16
|
|
8009d7a: 46bd mov sp, r7
|
|
8009d7c: bd80 pop {r7, pc}
|
|
|
|
08009d7e <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
8009d7e: b480 push {r7}
|
|
8009d80: b095 sub sp, #84 @ 0x54
|
|
8009d82: af00 add r7, sp, #0
|
|
8009d84: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8009d86: 687b ldr r3, [r7, #4]
|
|
8009d88: 681b ldr r3, [r3, #0]
|
|
8009d8a: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009d8c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8009d8e: e853 3f00 ldrex r3, [r3]
|
|
8009d92: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8009d94: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8009d96: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8009d9a: 64fb str r3, [r7, #76] @ 0x4c
|
|
8009d9c: 687b ldr r3, [r7, #4]
|
|
8009d9e: 681b ldr r3, [r3, #0]
|
|
8009da0: 461a mov r2, r3
|
|
8009da2: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8009da4: 643b str r3, [r7, #64] @ 0x40
|
|
8009da6: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009da8: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8009daa: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8009dac: e841 2300 strex r3, r2, [r1]
|
|
8009db0: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8009db2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8009db4: 2b00 cmp r3, #0
|
|
8009db6: d1e6 bne.n 8009d86 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8009db8: 687b ldr r3, [r7, #4]
|
|
8009dba: 681b ldr r3, [r3, #0]
|
|
8009dbc: 3308 adds r3, #8
|
|
8009dbe: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009dc0: 6a3b ldr r3, [r7, #32]
|
|
8009dc2: e853 3f00 ldrex r3, [r3]
|
|
8009dc6: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8009dc8: 69fb ldr r3, [r7, #28]
|
|
8009dca: f023 0301 bic.w r3, r3, #1
|
|
8009dce: 64bb str r3, [r7, #72] @ 0x48
|
|
8009dd0: 687b ldr r3, [r7, #4]
|
|
8009dd2: 681b ldr r3, [r3, #0]
|
|
8009dd4: 3308 adds r3, #8
|
|
8009dd6: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8009dd8: 62fa str r2, [r7, #44] @ 0x2c
|
|
8009dda: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009ddc: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8009dde: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8009de0: e841 2300 strex r3, r2, [r1]
|
|
8009de4: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8009de6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8009de8: 2b00 cmp r3, #0
|
|
8009dea: d1e5 bne.n 8009db8 <UART_EndRxTransfer+0x3a>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8009dec: 687b ldr r3, [r7, #4]
|
|
8009dee: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8009df0: 2b01 cmp r3, #1
|
|
8009df2: d118 bne.n 8009e26 <UART_EndRxTransfer+0xa8>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8009df4: 687b ldr r3, [r7, #4]
|
|
8009df6: 681b ldr r3, [r3, #0]
|
|
8009df8: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009dfa: 68fb ldr r3, [r7, #12]
|
|
8009dfc: e853 3f00 ldrex r3, [r3]
|
|
8009e00: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8009e02: 68bb ldr r3, [r7, #8]
|
|
8009e04: f023 0310 bic.w r3, r3, #16
|
|
8009e08: 647b str r3, [r7, #68] @ 0x44
|
|
8009e0a: 687b ldr r3, [r7, #4]
|
|
8009e0c: 681b ldr r3, [r3, #0]
|
|
8009e0e: 461a mov r2, r3
|
|
8009e10: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8009e12: 61bb str r3, [r7, #24]
|
|
8009e14: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009e16: 6979 ldr r1, [r7, #20]
|
|
8009e18: 69ba ldr r2, [r7, #24]
|
|
8009e1a: e841 2300 strex r3, r2, [r1]
|
|
8009e1e: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8009e20: 693b ldr r3, [r7, #16]
|
|
8009e22: 2b00 cmp r3, #0
|
|
8009e24: d1e6 bne.n 8009df4 <UART_EndRxTransfer+0x76>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8009e26: 687b ldr r3, [r7, #4]
|
|
8009e28: 2220 movs r2, #32
|
|
8009e2a: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8009e2e: 687b ldr r3, [r7, #4]
|
|
8009e30: 2200 movs r2, #0
|
|
8009e32: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
8009e34: 687b ldr r3, [r7, #4]
|
|
8009e36: 2200 movs r2, #0
|
|
8009e38: 669a str r2, [r3, #104] @ 0x68
|
|
}
|
|
8009e3a: bf00 nop
|
|
8009e3c: 3754 adds r7, #84 @ 0x54
|
|
8009e3e: 46bd mov sp, r7
|
|
8009e40: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009e44: 4770 bx lr
|
|
|
|
08009e46 <UART_DMAAbortOnError>:
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8009e46: b580 push {r7, lr}
|
|
8009e48: b084 sub sp, #16
|
|
8009e4a: af00 add r7, sp, #0
|
|
8009e4c: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
8009e4e: 687b ldr r3, [r7, #4]
|
|
8009e50: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8009e52: 60fb str r3, [r7, #12]
|
|
huart->RxXferCount = 0U;
|
|
8009e54: 68fb ldr r3, [r7, #12]
|
|
8009e56: 2200 movs r2, #0
|
|
8009e58: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
huart->TxXferCount = 0U;
|
|
8009e5c: 68fb ldr r3, [r7, #12]
|
|
8009e5e: 2200 movs r2, #0
|
|
8009e60: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8009e64: 68f8 ldr r0, [r7, #12]
|
|
8009e66: f7ff fb05 bl 8009474 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8009e6a: bf00 nop
|
|
8009e6c: 3710 adds r7, #16
|
|
8009e6e: 46bd mov sp, r7
|
|
8009e70: bd80 pop {r7, pc}
|
|
|
|
08009e72 <UART_TxISR_8BIT>:
|
|
* interruptions have been enabled by HAL_UART_Transmit_IT().
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
8009e72: b480 push {r7}
|
|
8009e74: b08f sub sp, #60 @ 0x3c
|
|
8009e76: af00 add r7, sp, #0
|
|
8009e78: 6078 str r0, [r7, #4]
|
|
/* Check that a Tx process is ongoing */
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|
8009e7a: 687b ldr r3, [r7, #4]
|
|
8009e7c: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8009e7e: 2b21 cmp r3, #33 @ 0x21
|
|
8009e80: d14c bne.n 8009f1c <UART_TxISR_8BIT+0xaa>
|
|
{
|
|
if (huart->TxXferCount == 0U)
|
|
8009e82: 687b ldr r3, [r7, #4]
|
|
8009e84: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8009e88: b29b uxth r3, r3
|
|
8009e8a: 2b00 cmp r3, #0
|
|
8009e8c: d132 bne.n 8009ef4 <UART_TxISR_8BIT+0x82>
|
|
{
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|
8009e8e: 687b ldr r3, [r7, #4]
|
|
8009e90: 681b ldr r3, [r3, #0]
|
|
8009e92: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009e94: 6a3b ldr r3, [r7, #32]
|
|
8009e96: e853 3f00 ldrex r3, [r3]
|
|
8009e9a: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8009e9c: 69fb ldr r3, [r7, #28]
|
|
8009e9e: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8009ea2: 637b str r3, [r7, #52] @ 0x34
|
|
8009ea4: 687b ldr r3, [r7, #4]
|
|
8009ea6: 681b ldr r3, [r3, #0]
|
|
8009ea8: 461a mov r2, r3
|
|
8009eaa: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8009eac: 62fb str r3, [r7, #44] @ 0x2c
|
|
8009eae: 62ba str r2, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009eb0: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8009eb2: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8009eb4: e841 2300 strex r3, r2, [r1]
|
|
8009eb8: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8009eba: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8009ebc: 2b00 cmp r3, #0
|
|
8009ebe: d1e6 bne.n 8009e8e <UART_TxISR_8BIT+0x1c>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
8009ec0: 687b ldr r3, [r7, #4]
|
|
8009ec2: 681b ldr r3, [r3, #0]
|
|
8009ec4: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009ec6: 68fb ldr r3, [r7, #12]
|
|
8009ec8: e853 3f00 ldrex r3, [r3]
|
|
8009ecc: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8009ece: 68bb ldr r3, [r7, #8]
|
|
8009ed0: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8009ed4: 633b str r3, [r7, #48] @ 0x30
|
|
8009ed6: 687b ldr r3, [r7, #4]
|
|
8009ed8: 681b ldr r3, [r3, #0]
|
|
8009eda: 461a mov r2, r3
|
|
8009edc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8009ede: 61bb str r3, [r7, #24]
|
|
8009ee0: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009ee2: 6979 ldr r1, [r7, #20]
|
|
8009ee4: 69ba ldr r2, [r7, #24]
|
|
8009ee6: e841 2300 strex r3, r2, [r1]
|
|
8009eea: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8009eec: 693b ldr r3, [r7, #16]
|
|
8009eee: 2b00 cmp r3, #0
|
|
8009ef0: d1e6 bne.n 8009ec0 <UART_TxISR_8BIT+0x4e>
|
|
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
|
|
huart->pTxBuffPtr++;
|
|
huart->TxXferCount--;
|
|
}
|
|
}
|
|
}
|
|
8009ef2: e013 b.n 8009f1c <UART_TxISR_8BIT+0xaa>
|
|
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
|
|
8009ef4: 687b ldr r3, [r7, #4]
|
|
8009ef6: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8009ef8: 781a ldrb r2, [r3, #0]
|
|
8009efa: 687b ldr r3, [r7, #4]
|
|
8009efc: 681b ldr r3, [r3, #0]
|
|
8009efe: 851a strh r2, [r3, #40] @ 0x28
|
|
huart->pTxBuffPtr++;
|
|
8009f00: 687b ldr r3, [r7, #4]
|
|
8009f02: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8009f04: 1c5a adds r2, r3, #1
|
|
8009f06: 687b ldr r3, [r7, #4]
|
|
8009f08: 64da str r2, [r3, #76] @ 0x4c
|
|
huart->TxXferCount--;
|
|
8009f0a: 687b ldr r3, [r7, #4]
|
|
8009f0c: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8009f10: b29b uxth r3, r3
|
|
8009f12: 3b01 subs r3, #1
|
|
8009f14: b29a uxth r2, r3
|
|
8009f16: 687b ldr r3, [r7, #4]
|
|
8009f18: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
}
|
|
8009f1c: bf00 nop
|
|
8009f1e: 373c adds r7, #60 @ 0x3c
|
|
8009f20: 46bd mov sp, r7
|
|
8009f22: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009f26: 4770 bx lr
|
|
|
|
08009f28 <UART_TxISR_16BIT>:
|
|
* interruptions have been enabled by HAL_UART_Transmit_IT().
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
8009f28: b480 push {r7}
|
|
8009f2a: b091 sub sp, #68 @ 0x44
|
|
8009f2c: af00 add r7, sp, #0
|
|
8009f2e: 6078 str r0, [r7, #4]
|
|
const uint16_t *tmp;
|
|
|
|
/* Check that a Tx process is ongoing */
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|
8009f30: 687b ldr r3, [r7, #4]
|
|
8009f32: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8009f34: 2b21 cmp r3, #33 @ 0x21
|
|
8009f36: d151 bne.n 8009fdc <UART_TxISR_16BIT+0xb4>
|
|
{
|
|
if (huart->TxXferCount == 0U)
|
|
8009f38: 687b ldr r3, [r7, #4]
|
|
8009f3a: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8009f3e: b29b uxth r3, r3
|
|
8009f40: 2b00 cmp r3, #0
|
|
8009f42: d132 bne.n 8009faa <UART_TxISR_16BIT+0x82>
|
|
{
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
|
|
8009f44: 687b ldr r3, [r7, #4]
|
|
8009f46: 681b ldr r3, [r3, #0]
|
|
8009f48: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009f4a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8009f4c: e853 3f00 ldrex r3, [r3]
|
|
8009f50: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8009f52: 6a3b ldr r3, [r7, #32]
|
|
8009f54: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8009f58: 63bb str r3, [r7, #56] @ 0x38
|
|
8009f5a: 687b ldr r3, [r7, #4]
|
|
8009f5c: 681b ldr r3, [r3, #0]
|
|
8009f5e: 461a mov r2, r3
|
|
8009f60: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8009f62: 633b str r3, [r7, #48] @ 0x30
|
|
8009f64: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009f66: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8009f68: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8009f6a: e841 2300 strex r3, r2, [r1]
|
|
8009f6e: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8009f70: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009f72: 2b00 cmp r3, #0
|
|
8009f74: d1e6 bne.n 8009f44 <UART_TxISR_16BIT+0x1c>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
8009f76: 687b ldr r3, [r7, #4]
|
|
8009f78: 681b ldr r3, [r3, #0]
|
|
8009f7a: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009f7c: 693b ldr r3, [r7, #16]
|
|
8009f7e: e853 3f00 ldrex r3, [r3]
|
|
8009f82: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8009f84: 68fb ldr r3, [r7, #12]
|
|
8009f86: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8009f8a: 637b str r3, [r7, #52] @ 0x34
|
|
8009f8c: 687b ldr r3, [r7, #4]
|
|
8009f8e: 681b ldr r3, [r3, #0]
|
|
8009f90: 461a mov r2, r3
|
|
8009f92: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8009f94: 61fb str r3, [r7, #28]
|
|
8009f96: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8009f98: 69b9 ldr r1, [r7, #24]
|
|
8009f9a: 69fa ldr r2, [r7, #28]
|
|
8009f9c: e841 2300 strex r3, r2, [r1]
|
|
8009fa0: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8009fa2: 697b ldr r3, [r7, #20]
|
|
8009fa4: 2b00 cmp r3, #0
|
|
8009fa6: d1e6 bne.n 8009f76 <UART_TxISR_16BIT+0x4e>
|
|
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
|
|
huart->pTxBuffPtr += 2U;
|
|
huart->TxXferCount--;
|
|
}
|
|
}
|
|
}
|
|
8009fa8: e018 b.n 8009fdc <UART_TxISR_16BIT+0xb4>
|
|
tmp = (const uint16_t *) huart->pTxBuffPtr;
|
|
8009faa: 687b ldr r3, [r7, #4]
|
|
8009fac: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8009fae: 63fb str r3, [r7, #60] @ 0x3c
|
|
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
|
|
8009fb0: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8009fb2: 881a ldrh r2, [r3, #0]
|
|
8009fb4: 687b ldr r3, [r7, #4]
|
|
8009fb6: 681b ldr r3, [r3, #0]
|
|
8009fb8: f3c2 0208 ubfx r2, r2, #0, #9
|
|
8009fbc: b292 uxth r2, r2
|
|
8009fbe: 851a strh r2, [r3, #40] @ 0x28
|
|
huart->pTxBuffPtr += 2U;
|
|
8009fc0: 687b ldr r3, [r7, #4]
|
|
8009fc2: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8009fc4: 1c9a adds r2, r3, #2
|
|
8009fc6: 687b ldr r3, [r7, #4]
|
|
8009fc8: 64da str r2, [r3, #76] @ 0x4c
|
|
huart->TxXferCount--;
|
|
8009fca: 687b ldr r3, [r7, #4]
|
|
8009fcc: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8009fd0: b29b uxth r3, r3
|
|
8009fd2: 3b01 subs r3, #1
|
|
8009fd4: b29a uxth r2, r3
|
|
8009fd6: 687b ldr r3, [r7, #4]
|
|
8009fd8: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
}
|
|
8009fdc: bf00 nop
|
|
8009fde: 3744 adds r7, #68 @ 0x44
|
|
8009fe0: 46bd mov sp, r7
|
|
8009fe2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009fe6: 4770 bx lr
|
|
|
|
08009fe8 <UART_EndTransmit_IT>:
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8009fe8: b580 push {r7, lr}
|
|
8009fea: b088 sub sp, #32
|
|
8009fec: af00 add r7, sp, #0
|
|
8009fee: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
8009ff0: 687b ldr r3, [r7, #4]
|
|
8009ff2: 681b ldr r3, [r3, #0]
|
|
8009ff4: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8009ff6: 68fb ldr r3, [r7, #12]
|
|
8009ff8: e853 3f00 ldrex r3, [r3]
|
|
8009ffc: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8009ffe: 68bb ldr r3, [r7, #8]
|
|
800a000: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800a004: 61fb str r3, [r7, #28]
|
|
800a006: 687b ldr r3, [r7, #4]
|
|
800a008: 681b ldr r3, [r3, #0]
|
|
800a00a: 461a mov r2, r3
|
|
800a00c: 69fb ldr r3, [r7, #28]
|
|
800a00e: 61bb str r3, [r7, #24]
|
|
800a010: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800a012: 6979 ldr r1, [r7, #20]
|
|
800a014: 69ba ldr r2, [r7, #24]
|
|
800a016: e841 2300 strex r3, r2, [r1]
|
|
800a01a: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800a01c: 693b ldr r3, [r7, #16]
|
|
800a01e: 2b00 cmp r3, #0
|
|
800a020: d1e6 bne.n 8009ff0 <UART_EndTransmit_IT+0x8>
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800a022: 687b ldr r3, [r7, #4]
|
|
800a024: 2220 movs r2, #32
|
|
800a026: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
/* Cleat TxISR function pointer */
|
|
huart->TxISR = NULL;
|
|
800a028: 687b ldr r3, [r7, #4]
|
|
800a02a: 2200 movs r2, #0
|
|
800a02c: 66da str r2, [r3, #108] @ 0x6c
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
800a02e: 6878 ldr r0, [r7, #4]
|
|
800a030: f7f9 f926 bl 8003280 <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800a034: bf00 nop
|
|
800a036: 3720 adds r7, #32
|
|
800a038: 46bd mov sp, r7
|
|
800a03a: bd80 pop {r7, pc}
|
|
|
|
0800a03c <HAL_UARTEx_WakeupCallback>:
|
|
* @brief UART wakeup from Stop mode callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800a03c: b480 push {r7}
|
|
800a03e: b083 sub sp, #12
|
|
800a040: af00 add r7, sp, #0
|
|
800a042: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800a044: bf00 nop
|
|
800a046: 370c adds r7, #12
|
|
800a048: 46bd mov sp, r7
|
|
800a04a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a04e: 4770 bx lr
|
|
|
|
0800a050 <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
800a050: b084 sub sp, #16
|
|
800a052: b580 push {r7, lr}
|
|
800a054: b084 sub sp, #16
|
|
800a056: af00 add r7, sp, #0
|
|
800a058: 6078 str r0, [r7, #4]
|
|
800a05a: f107 001c add.w r0, r7, #28
|
|
800a05e: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret;
|
|
|
|
/* Select FS Embedded PHY */
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
|
800a062: 687b ldr r3, [r7, #4]
|
|
800a064: 68db ldr r3, [r3, #12]
|
|
800a066: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
800a06a: 687b ldr r3, [r7, #4]
|
|
800a06c: 60da str r2, [r3, #12]
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
800a06e: 6878 ldr r0, [r7, #4]
|
|
800a070: f000 fa68 bl 800a544 <USB_CoreReset>
|
|
800a074: 4603 mov r3, r0
|
|
800a076: 73fb strb r3, [r7, #15]
|
|
|
|
if (cfg.battery_charging_enable == 0U)
|
|
800a078: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
800a07c: 2b00 cmp r3, #0
|
|
800a07e: d106 bne.n 800a08e <USB_CoreInit+0x3e>
|
|
{
|
|
/* Activate the USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
800a080: 687b ldr r3, [r7, #4]
|
|
800a082: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800a084: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
800a088: 687b ldr r3, [r7, #4]
|
|
800a08a: 639a str r2, [r3, #56] @ 0x38
|
|
800a08c: e005 b.n 800a09a <USB_CoreInit+0x4a>
|
|
}
|
|
else
|
|
{
|
|
/* Deactivate the USB Transceiver */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
800a08e: 687b ldr r3, [r7, #4]
|
|
800a090: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800a092: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
800a096: 687b ldr r3, [r7, #4]
|
|
800a098: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
return ret;
|
|
800a09a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800a09c: 4618 mov r0, r3
|
|
800a09e: 3710 adds r7, #16
|
|
800a0a0: 46bd mov sp, r7
|
|
800a0a2: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
800a0a6: b004 add sp, #16
|
|
800a0a8: 4770 bx lr
|
|
|
|
0800a0aa <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800a0aa: b480 push {r7}
|
|
800a0ac: b083 sub sp, #12
|
|
800a0ae: af00 add r7, sp, #0
|
|
800a0b0: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
800a0b2: 687b ldr r3, [r7, #4]
|
|
800a0b4: 689b ldr r3, [r3, #8]
|
|
800a0b6: f023 0201 bic.w r2, r3, #1
|
|
800a0ba: 687b ldr r3, [r7, #4]
|
|
800a0bc: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
800a0be: 2300 movs r3, #0
|
|
}
|
|
800a0c0: 4618 mov r0, r3
|
|
800a0c2: 370c adds r7, #12
|
|
800a0c4: 46bd mov sp, r7
|
|
800a0c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a0ca: 4770 bx lr
|
|
|
|
0800a0cc <USB_SetCurrentMode>:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @arg USB_HOST_MODE Host mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
|
|
{
|
|
800a0cc: b580 push {r7, lr}
|
|
800a0ce: b084 sub sp, #16
|
|
800a0d0: af00 add r7, sp, #0
|
|
800a0d2: 6078 str r0, [r7, #4]
|
|
800a0d4: 460b mov r3, r1
|
|
800a0d6: 70fb strb r3, [r7, #3]
|
|
uint32_t ms = 0U;
|
|
800a0d8: 2300 movs r3, #0
|
|
800a0da: 60fb str r3, [r7, #12]
|
|
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
|
800a0dc: 687b ldr r3, [r7, #4]
|
|
800a0de: 68db ldr r3, [r3, #12]
|
|
800a0e0: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
|
|
800a0e4: 687b ldr r3, [r7, #4]
|
|
800a0e6: 60da str r2, [r3, #12]
|
|
|
|
if (mode == USB_HOST_MODE)
|
|
800a0e8: 78fb ldrb r3, [r7, #3]
|
|
800a0ea: 2b01 cmp r3, #1
|
|
800a0ec: d115 bne.n 800a11a <USB_SetCurrentMode+0x4e>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
|
|
800a0ee: 687b ldr r3, [r7, #4]
|
|
800a0f0: 68db ldr r3, [r3, #12]
|
|
800a0f2: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
|
|
800a0f6: 687b ldr r3, [r7, #4]
|
|
800a0f8: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
800a0fa: 200a movs r0, #10
|
|
800a0fc: f7f9 fe0c bl 8003d18 <HAL_Delay>
|
|
ms += 10U;
|
|
800a100: 68fb ldr r3, [r7, #12]
|
|
800a102: 330a adds r3, #10
|
|
800a104: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
800a106: 6878 ldr r0, [r7, #4]
|
|
800a108: f000 fa0e bl 800a528 <USB_GetMode>
|
|
800a10c: 4603 mov r3, r0
|
|
800a10e: 2b01 cmp r3, #1
|
|
800a110: d01e beq.n 800a150 <USB_SetCurrentMode+0x84>
|
|
800a112: 68fb ldr r3, [r7, #12]
|
|
800a114: 2bc7 cmp r3, #199 @ 0xc7
|
|
800a116: d9f0 bls.n 800a0fa <USB_SetCurrentMode+0x2e>
|
|
800a118: e01a b.n 800a150 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else if (mode == USB_DEVICE_MODE)
|
|
800a11a: 78fb ldrb r3, [r7, #3]
|
|
800a11c: 2b00 cmp r3, #0
|
|
800a11e: d115 bne.n 800a14c <USB_SetCurrentMode+0x80>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
|
800a120: 687b ldr r3, [r7, #4]
|
|
800a122: 68db ldr r3, [r3, #12]
|
|
800a124: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
|
|
800a128: 687b ldr r3, [r7, #4]
|
|
800a12a: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
800a12c: 200a movs r0, #10
|
|
800a12e: f7f9 fdf3 bl 8003d18 <HAL_Delay>
|
|
ms += 10U;
|
|
800a132: 68fb ldr r3, [r7, #12]
|
|
800a134: 330a adds r3, #10
|
|
800a136: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
800a138: 6878 ldr r0, [r7, #4]
|
|
800a13a: f000 f9f5 bl 800a528 <USB_GetMode>
|
|
800a13e: 4603 mov r3, r0
|
|
800a140: 2b00 cmp r3, #0
|
|
800a142: d005 beq.n 800a150 <USB_SetCurrentMode+0x84>
|
|
800a144: 68fb ldr r3, [r7, #12]
|
|
800a146: 2bc7 cmp r3, #199 @ 0xc7
|
|
800a148: d9f0 bls.n 800a12c <USB_SetCurrentMode+0x60>
|
|
800a14a: e001 b.n 800a150 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
800a14c: 2301 movs r3, #1
|
|
800a14e: e005 b.n 800a15c <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
|
|
800a150: 68fb ldr r3, [r7, #12]
|
|
800a152: 2bc8 cmp r3, #200 @ 0xc8
|
|
800a154: d101 bne.n 800a15a <USB_SetCurrentMode+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
800a156: 2301 movs r3, #1
|
|
800a158: e000 b.n 800a15c <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800a15a: 2300 movs r3, #0
|
|
}
|
|
800a15c: 4618 mov r0, r3
|
|
800a15e: 3710 adds r7, #16
|
|
800a160: 46bd mov sp, r7
|
|
800a162: bd80 pop {r7, pc}
|
|
|
|
0800a164 <USB_DevInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
800a164: b084 sub sp, #16
|
|
800a166: b580 push {r7, lr}
|
|
800a168: b086 sub sp, #24
|
|
800a16a: af00 add r7, sp, #0
|
|
800a16c: 6078 str r0, [r7, #4]
|
|
800a16e: f107 0024 add.w r0, r7, #36 @ 0x24
|
|
800a172: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800a176: 2300 movs r3, #0
|
|
800a178: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800a17a: 687b ldr r3, [r7, #4]
|
|
800a17c: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
|
|
for (i = 0U; i < 15U; i++)
|
|
800a17e: 2300 movs r3, #0
|
|
800a180: 613b str r3, [r7, #16]
|
|
800a182: e009 b.n 800a198 <USB_DevInit+0x34>
|
|
{
|
|
USBx->DIEPTXF[i] = 0U;
|
|
800a184: 687a ldr r2, [r7, #4]
|
|
800a186: 693b ldr r3, [r7, #16]
|
|
800a188: 3340 adds r3, #64 @ 0x40
|
|
800a18a: 009b lsls r3, r3, #2
|
|
800a18c: 4413 add r3, r2
|
|
800a18e: 2200 movs r2, #0
|
|
800a190: 605a str r2, [r3, #4]
|
|
for (i = 0U; i < 15U; i++)
|
|
800a192: 693b ldr r3, [r7, #16]
|
|
800a194: 3301 adds r3, #1
|
|
800a196: 613b str r3, [r7, #16]
|
|
800a198: 693b ldr r3, [r7, #16]
|
|
800a19a: 2b0e cmp r3, #14
|
|
800a19c: d9f2 bls.n 800a184 <USB_DevInit+0x20>
|
|
}
|
|
|
|
/* VBUS Sensing setup */
|
|
if (cfg.vbus_sensing_enable == 0U)
|
|
800a19e: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
800a1a2: 2b00 cmp r3, #0
|
|
800a1a4: d11c bne.n 800a1e0 <USB_DevInit+0x7c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
800a1a6: 68fb ldr r3, [r7, #12]
|
|
800a1a8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800a1ac: 685b ldr r3, [r3, #4]
|
|
800a1ae: 68fa ldr r2, [r7, #12]
|
|
800a1b0: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800a1b4: f043 0302 orr.w r3, r3, #2
|
|
800a1b8: 6053 str r3, [r2, #4]
|
|
|
|
/* Deactivate VBUS Sensing B */
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
|
800a1ba: 687b ldr r3, [r7, #4]
|
|
800a1bc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800a1be: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
|
|
800a1c2: 687b ldr r3, [r7, #4]
|
|
800a1c4: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* B-peripheral session valid override enable */
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
|
800a1c6: 687b ldr r3, [r7, #4]
|
|
800a1c8: 681b ldr r3, [r3, #0]
|
|
800a1ca: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
800a1ce: 687b ldr r3, [r7, #4]
|
|
800a1d0: 601a str r2, [r3, #0]
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
|
800a1d2: 687b ldr r3, [r7, #4]
|
|
800a1d4: 681b ldr r3, [r3, #0]
|
|
800a1d6: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
800a1da: 687b ldr r3, [r7, #4]
|
|
800a1dc: 601a str r2, [r3, #0]
|
|
800a1de: e005 b.n 800a1ec <USB_DevInit+0x88>
|
|
}
|
|
else
|
|
{
|
|
/* Enable HW VBUS sensing */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
|
800a1e0: 687b ldr r3, [r7, #4]
|
|
800a1e2: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800a1e4: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
800a1e8: 687b ldr r3, [r7, #4]
|
|
800a1ea: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
/* Restart the Phy Clock */
|
|
USBx_PCGCCTL = 0U;
|
|
800a1ec: 68fb ldr r3, [r7, #12]
|
|
800a1ee: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800a1f2: 461a mov r2, r3
|
|
800a1f4: 2300 movs r3, #0
|
|
800a1f6: 6013 str r3, [r2, #0]
|
|
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
|
|
800a1f8: 2103 movs r1, #3
|
|
800a1fa: 6878 ldr r0, [r7, #4]
|
|
800a1fc: f000 f95a bl 800a4b4 <USB_SetDevSpeed>
|
|
|
|
/* Flush the FIFOs */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
800a200: 2110 movs r1, #16
|
|
800a202: 6878 ldr r0, [r7, #4]
|
|
800a204: f000 f8f6 bl 800a3f4 <USB_FlushTxFifo>
|
|
800a208: 4603 mov r3, r0
|
|
800a20a: 2b00 cmp r3, #0
|
|
800a20c: d001 beq.n 800a212 <USB_DevInit+0xae>
|
|
{
|
|
ret = HAL_ERROR;
|
|
800a20e: 2301 movs r3, #1
|
|
800a210: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
800a212: 6878 ldr r0, [r7, #4]
|
|
800a214: f000 f920 bl 800a458 <USB_FlushRxFifo>
|
|
800a218: 4603 mov r3, r0
|
|
800a21a: 2b00 cmp r3, #0
|
|
800a21c: d001 beq.n 800a222 <USB_DevInit+0xbe>
|
|
{
|
|
ret = HAL_ERROR;
|
|
800a21e: 2301 movs r3, #1
|
|
800a220: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Clear all pending Device Interrupts */
|
|
USBx_DEVICE->DIEPMSK = 0U;
|
|
800a222: 68fb ldr r3, [r7, #12]
|
|
800a224: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800a228: 461a mov r2, r3
|
|
800a22a: 2300 movs r3, #0
|
|
800a22c: 6113 str r3, [r2, #16]
|
|
USBx_DEVICE->DOEPMSK = 0U;
|
|
800a22e: 68fb ldr r3, [r7, #12]
|
|
800a230: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800a234: 461a mov r2, r3
|
|
800a236: 2300 movs r3, #0
|
|
800a238: 6153 str r3, [r2, #20]
|
|
USBx_DEVICE->DAINTMSK = 0U;
|
|
800a23a: 68fb ldr r3, [r7, #12]
|
|
800a23c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800a240: 461a mov r2, r3
|
|
800a242: 2300 movs r3, #0
|
|
800a244: 61d3 str r3, [r2, #28]
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
800a246: 2300 movs r3, #0
|
|
800a248: 613b str r3, [r7, #16]
|
|
800a24a: e043 b.n 800a2d4 <USB_DevInit+0x170>
|
|
{
|
|
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
800a24c: 693b ldr r3, [r7, #16]
|
|
800a24e: 015a lsls r2, r3, #5
|
|
800a250: 68fb ldr r3, [r7, #12]
|
|
800a252: 4413 add r3, r2
|
|
800a254: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800a258: 681b ldr r3, [r3, #0]
|
|
800a25a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800a25e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800a262: d118 bne.n 800a296 <USB_DevInit+0x132>
|
|
{
|
|
if (i == 0U)
|
|
800a264: 693b ldr r3, [r7, #16]
|
|
800a266: 2b00 cmp r3, #0
|
|
800a268: d10a bne.n 800a280 <USB_DevInit+0x11c>
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
|
|
800a26a: 693b ldr r3, [r7, #16]
|
|
800a26c: 015a lsls r2, r3, #5
|
|
800a26e: 68fb ldr r3, [r7, #12]
|
|
800a270: 4413 add r3, r2
|
|
800a272: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800a276: 461a mov r2, r3
|
|
800a278: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
800a27c: 6013 str r3, [r2, #0]
|
|
800a27e: e013 b.n 800a2a8 <USB_DevInit+0x144>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
|
|
800a280: 693b ldr r3, [r7, #16]
|
|
800a282: 015a lsls r2, r3, #5
|
|
800a284: 68fb ldr r3, [r7, #12]
|
|
800a286: 4413 add r3, r2
|
|
800a288: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800a28c: 461a mov r2, r3
|
|
800a28e: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
800a292: 6013 str r3, [r2, #0]
|
|
800a294: e008 b.n 800a2a8 <USB_DevInit+0x144>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = 0U;
|
|
800a296: 693b ldr r3, [r7, #16]
|
|
800a298: 015a lsls r2, r3, #5
|
|
800a29a: 68fb ldr r3, [r7, #12]
|
|
800a29c: 4413 add r3, r2
|
|
800a29e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800a2a2: 461a mov r2, r3
|
|
800a2a4: 2300 movs r3, #0
|
|
800a2a6: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_INEP(i)->DIEPTSIZ = 0U;
|
|
800a2a8: 693b ldr r3, [r7, #16]
|
|
800a2aa: 015a lsls r2, r3, #5
|
|
800a2ac: 68fb ldr r3, [r7, #12]
|
|
800a2ae: 4413 add r3, r2
|
|
800a2b0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800a2b4: 461a mov r2, r3
|
|
800a2b6: 2300 movs r3, #0
|
|
800a2b8: 6113 str r3, [r2, #16]
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
800a2ba: 693b ldr r3, [r7, #16]
|
|
800a2bc: 015a lsls r2, r3, #5
|
|
800a2be: 68fb ldr r3, [r7, #12]
|
|
800a2c0: 4413 add r3, r2
|
|
800a2c2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800a2c6: 461a mov r2, r3
|
|
800a2c8: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
800a2cc: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
800a2ce: 693b ldr r3, [r7, #16]
|
|
800a2d0: 3301 adds r3, #1
|
|
800a2d2: 613b str r3, [r7, #16]
|
|
800a2d4: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
800a2d8: 461a mov r2, r3
|
|
800a2da: 693b ldr r3, [r7, #16]
|
|
800a2dc: 4293 cmp r3, r2
|
|
800a2de: d3b5 bcc.n 800a24c <USB_DevInit+0xe8>
|
|
}
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
800a2e0: 2300 movs r3, #0
|
|
800a2e2: 613b str r3, [r7, #16]
|
|
800a2e4: e043 b.n 800a36e <USB_DevInit+0x20a>
|
|
{
|
|
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
800a2e6: 693b ldr r3, [r7, #16]
|
|
800a2e8: 015a lsls r2, r3, #5
|
|
800a2ea: 68fb ldr r3, [r7, #12]
|
|
800a2ec: 4413 add r3, r2
|
|
800a2ee: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800a2f2: 681b ldr r3, [r3, #0]
|
|
800a2f4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800a2f8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800a2fc: d118 bne.n 800a330 <USB_DevInit+0x1cc>
|
|
{
|
|
if (i == 0U)
|
|
800a2fe: 693b ldr r3, [r7, #16]
|
|
800a300: 2b00 cmp r3, #0
|
|
800a302: d10a bne.n 800a31a <USB_DevInit+0x1b6>
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
|
|
800a304: 693b ldr r3, [r7, #16]
|
|
800a306: 015a lsls r2, r3, #5
|
|
800a308: 68fb ldr r3, [r7, #12]
|
|
800a30a: 4413 add r3, r2
|
|
800a30c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800a310: 461a mov r2, r3
|
|
800a312: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
800a316: 6013 str r3, [r2, #0]
|
|
800a318: e013 b.n 800a342 <USB_DevInit+0x1de>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
|
|
800a31a: 693b ldr r3, [r7, #16]
|
|
800a31c: 015a lsls r2, r3, #5
|
|
800a31e: 68fb ldr r3, [r7, #12]
|
|
800a320: 4413 add r3, r2
|
|
800a322: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800a326: 461a mov r2, r3
|
|
800a328: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
800a32c: 6013 str r3, [r2, #0]
|
|
800a32e: e008 b.n 800a342 <USB_DevInit+0x1de>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = 0U;
|
|
800a330: 693b ldr r3, [r7, #16]
|
|
800a332: 015a lsls r2, r3, #5
|
|
800a334: 68fb ldr r3, [r7, #12]
|
|
800a336: 4413 add r3, r2
|
|
800a338: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800a33c: 461a mov r2, r3
|
|
800a33e: 2300 movs r3, #0
|
|
800a340: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_OUTEP(i)->DOEPTSIZ = 0U;
|
|
800a342: 693b ldr r3, [r7, #16]
|
|
800a344: 015a lsls r2, r3, #5
|
|
800a346: 68fb ldr r3, [r7, #12]
|
|
800a348: 4413 add r3, r2
|
|
800a34a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800a34e: 461a mov r2, r3
|
|
800a350: 2300 movs r3, #0
|
|
800a352: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
800a354: 693b ldr r3, [r7, #16]
|
|
800a356: 015a lsls r2, r3, #5
|
|
800a358: 68fb ldr r3, [r7, #12]
|
|
800a35a: 4413 add r3, r2
|
|
800a35c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800a360: 461a mov r2, r3
|
|
800a362: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
800a366: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
800a368: 693b ldr r3, [r7, #16]
|
|
800a36a: 3301 adds r3, #1
|
|
800a36c: 613b str r3, [r7, #16]
|
|
800a36e: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
800a372: 461a mov r2, r3
|
|
800a374: 693b ldr r3, [r7, #16]
|
|
800a376: 4293 cmp r3, r2
|
|
800a378: d3b5 bcc.n 800a2e6 <USB_DevInit+0x182>
|
|
}
|
|
|
|
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
|
|
800a37a: 68fb ldr r3, [r7, #12]
|
|
800a37c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800a380: 691b ldr r3, [r3, #16]
|
|
800a382: 68fa ldr r2, [r7, #12]
|
|
800a384: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800a388: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800a38c: 6113 str r3, [r2, #16]
|
|
|
|
/* Disable all interrupts. */
|
|
USBx->GINTMSK = 0U;
|
|
800a38e: 687b ldr r3, [r7, #4]
|
|
800a390: 2200 movs r2, #0
|
|
800a392: 619a str r2, [r3, #24]
|
|
|
|
/* Clear any pending interrupts */
|
|
USBx->GINTSTS = 0xBFFFFFFFU;
|
|
800a394: 687b ldr r3, [r7, #4]
|
|
800a396: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
|
|
800a39a: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the common interrupts */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
|
800a39c: 687b ldr r3, [r7, #4]
|
|
800a39e: 699b ldr r3, [r3, #24]
|
|
800a3a0: f043 0210 orr.w r2, r3, #16
|
|
800a3a4: 687b ldr r3, [r7, #4]
|
|
800a3a6: 619a str r2, [r3, #24]
|
|
|
|
/* Enable interrupts matching to the Device mode ONLY */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
|
|
800a3a8: 687b ldr r3, [r7, #4]
|
|
800a3aa: 699a ldr r2, [r3, #24]
|
|
800a3ac: 4b10 ldr r3, [pc, #64] @ (800a3f0 <USB_DevInit+0x28c>)
|
|
800a3ae: 4313 orrs r3, r2
|
|
800a3b0: 687a ldr r2, [r7, #4]
|
|
800a3b2: 6193 str r3, [r2, #24]
|
|
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
|
|
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
|
|
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
|
|
|
|
if (cfg.Sof_enable != 0U)
|
|
800a3b4: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
800a3b8: 2b00 cmp r3, #0
|
|
800a3ba: d005 beq.n 800a3c8 <USB_DevInit+0x264>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
|
|
800a3bc: 687b ldr r3, [r7, #4]
|
|
800a3be: 699b ldr r3, [r3, #24]
|
|
800a3c0: f043 0208 orr.w r2, r3, #8
|
|
800a3c4: 687b ldr r3, [r7, #4]
|
|
800a3c6: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (cfg.vbus_sensing_enable == 1U)
|
|
800a3c8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
800a3cc: 2b01 cmp r3, #1
|
|
800a3ce: d107 bne.n 800a3e0 <USB_DevInit+0x27c>
|
|
{
|
|
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
|
|
800a3d0: 687b ldr r3, [r7, #4]
|
|
800a3d2: 699b ldr r3, [r3, #24]
|
|
800a3d4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
800a3d8: f043 0304 orr.w r3, r3, #4
|
|
800a3dc: 687a ldr r2, [r7, #4]
|
|
800a3de: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
return ret;
|
|
800a3e0: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800a3e2: 4618 mov r0, r3
|
|
800a3e4: 3718 adds r7, #24
|
|
800a3e6: 46bd mov sp, r7
|
|
800a3e8: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
800a3ec: b004 add sp, #16
|
|
800a3ee: 4770 bx lr
|
|
800a3f0: 803c3800 .word 0x803c3800
|
|
|
|
0800a3f4 <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
800a3f4: b480 push {r7}
|
|
800a3f6: b085 sub sp, #20
|
|
800a3f8: af00 add r7, sp, #0
|
|
800a3fa: 6078 str r0, [r7, #4]
|
|
800a3fc: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
800a3fe: 2300 movs r3, #0
|
|
800a400: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800a402: 68fb ldr r3, [r7, #12]
|
|
800a404: 3301 adds r3, #1
|
|
800a406: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800a408: 68fb ldr r3, [r7, #12]
|
|
800a40a: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800a40e: d901 bls.n 800a414 <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800a410: 2303 movs r3, #3
|
|
800a412: e01b b.n 800a44c <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
800a414: 687b ldr r3, [r7, #4]
|
|
800a416: 691b ldr r3, [r3, #16]
|
|
800a418: 2b00 cmp r3, #0
|
|
800a41a: daf2 bge.n 800a402 <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
800a41c: 2300 movs r3, #0
|
|
800a41e: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
800a420: 683b ldr r3, [r7, #0]
|
|
800a422: 019b lsls r3, r3, #6
|
|
800a424: f043 0220 orr.w r2, r3, #32
|
|
800a428: 687b ldr r3, [r7, #4]
|
|
800a42a: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
800a42c: 68fb ldr r3, [r7, #12]
|
|
800a42e: 3301 adds r3, #1
|
|
800a430: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800a432: 68fb ldr r3, [r7, #12]
|
|
800a434: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800a438: d901 bls.n 800a43e <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800a43a: 2303 movs r3, #3
|
|
800a43c: e006 b.n 800a44c <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
800a43e: 687b ldr r3, [r7, #4]
|
|
800a440: 691b ldr r3, [r3, #16]
|
|
800a442: f003 0320 and.w r3, r3, #32
|
|
800a446: 2b20 cmp r3, #32
|
|
800a448: d0f0 beq.n 800a42c <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
800a44a: 2300 movs r3, #0
|
|
}
|
|
800a44c: 4618 mov r0, r3
|
|
800a44e: 3714 adds r7, #20
|
|
800a450: 46bd mov sp, r7
|
|
800a452: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a456: 4770 bx lr
|
|
|
|
0800a458 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800a458: b480 push {r7}
|
|
800a45a: b085 sub sp, #20
|
|
800a45c: af00 add r7, sp, #0
|
|
800a45e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
800a460: 2300 movs r3, #0
|
|
800a462: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800a464: 68fb ldr r3, [r7, #12]
|
|
800a466: 3301 adds r3, #1
|
|
800a468: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800a46a: 68fb ldr r3, [r7, #12]
|
|
800a46c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800a470: d901 bls.n 800a476 <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800a472: 2303 movs r3, #3
|
|
800a474: e018 b.n 800a4a8 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
800a476: 687b ldr r3, [r7, #4]
|
|
800a478: 691b ldr r3, [r3, #16]
|
|
800a47a: 2b00 cmp r3, #0
|
|
800a47c: daf2 bge.n 800a464 <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
800a47e: 2300 movs r3, #0
|
|
800a480: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
800a482: 687b ldr r3, [r7, #4]
|
|
800a484: 2210 movs r2, #16
|
|
800a486: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
800a488: 68fb ldr r3, [r7, #12]
|
|
800a48a: 3301 adds r3, #1
|
|
800a48c: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800a48e: 68fb ldr r3, [r7, #12]
|
|
800a490: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800a494: d901 bls.n 800a49a <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800a496: 2303 movs r3, #3
|
|
800a498: e006 b.n 800a4a8 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
800a49a: 687b ldr r3, [r7, #4]
|
|
800a49c: 691b ldr r3, [r3, #16]
|
|
800a49e: f003 0310 and.w r3, r3, #16
|
|
800a4a2: 2b10 cmp r3, #16
|
|
800a4a4: d0f0 beq.n 800a488 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
800a4a6: 2300 movs r3, #0
|
|
}
|
|
800a4a8: 4618 mov r0, r3
|
|
800a4aa: 3714 adds r7, #20
|
|
800a4ac: 46bd mov sp, r7
|
|
800a4ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a4b2: 4770 bx lr
|
|
|
|
0800a4b4 <USB_SetDevSpeed>:
|
|
* This parameter can be one of these values:
|
|
* @arg USB_OTG_SPEED_FULL: Full speed mode
|
|
* @retval Hal status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
|
|
{
|
|
800a4b4: b480 push {r7}
|
|
800a4b6: b085 sub sp, #20
|
|
800a4b8: af00 add r7, sp, #0
|
|
800a4ba: 6078 str r0, [r7, #4]
|
|
800a4bc: 460b mov r3, r1
|
|
800a4be: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800a4c0: 687b ldr r3, [r7, #4]
|
|
800a4c2: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG |= speed;
|
|
800a4c4: 68fb ldr r3, [r7, #12]
|
|
800a4c6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800a4ca: 681a ldr r2, [r3, #0]
|
|
800a4cc: 78fb ldrb r3, [r7, #3]
|
|
800a4ce: 68f9 ldr r1, [r7, #12]
|
|
800a4d0: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
800a4d4: 4313 orrs r3, r2
|
|
800a4d6: 600b str r3, [r1, #0]
|
|
return HAL_OK;
|
|
800a4d8: 2300 movs r3, #0
|
|
}
|
|
800a4da: 4618 mov r0, r3
|
|
800a4dc: 3714 adds r7, #20
|
|
800a4de: 46bd mov sp, r7
|
|
800a4e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a4e4: 4770 bx lr
|
|
|
|
0800a4e6 <USB_DevDisconnect>:
|
|
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800a4e6: b480 push {r7}
|
|
800a4e8: b085 sub sp, #20
|
|
800a4ea: af00 add r7, sp, #0
|
|
800a4ec: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800a4ee: 687b ldr r3, [r7, #4]
|
|
800a4f0: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
800a4f2: 68fb ldr r3, [r7, #12]
|
|
800a4f4: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800a4f8: 681b ldr r3, [r3, #0]
|
|
800a4fa: 68fa ldr r2, [r7, #12]
|
|
800a4fc: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800a500: f023 0303 bic.w r3, r3, #3
|
|
800a504: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
800a506: 68fb ldr r3, [r7, #12]
|
|
800a508: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800a50c: 685b ldr r3, [r3, #4]
|
|
800a50e: 68fa ldr r2, [r7, #12]
|
|
800a510: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800a514: f043 0302 orr.w r3, r3, #2
|
|
800a518: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
800a51a: 2300 movs r3, #0
|
|
}
|
|
800a51c: 4618 mov r0, r3
|
|
800a51e: 3714 adds r7, #20
|
|
800a520: 46bd mov sp, r7
|
|
800a522: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a526: 4770 bx lr
|
|
|
|
0800a528 <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 0 : Host
|
|
* 1 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800a528: b480 push {r7}
|
|
800a52a: b083 sub sp, #12
|
|
800a52c: af00 add r7, sp, #0
|
|
800a52e: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
800a530: 687b ldr r3, [r7, #4]
|
|
800a532: 695b ldr r3, [r3, #20]
|
|
800a534: f003 0301 and.w r3, r3, #1
|
|
}
|
|
800a538: 4618 mov r0, r3
|
|
800a53a: 370c adds r7, #12
|
|
800a53c: 46bd mov sp, r7
|
|
800a53e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a542: 4770 bx lr
|
|
|
|
0800a544 <USB_CoreReset>:
|
|
* @brief Reset the USB Core (needed after USB clock settings change)
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800a544: b480 push {r7}
|
|
800a546: b085 sub sp, #20
|
|
800a548: af00 add r7, sp, #0
|
|
800a54a: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
800a54c: 2300 movs r3, #0
|
|
800a54e: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800a550: 68fb ldr r3, [r7, #12]
|
|
800a552: 3301 adds r3, #1
|
|
800a554: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800a556: 68fb ldr r3, [r7, #12]
|
|
800a558: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800a55c: d901 bls.n 800a562 <USB_CoreReset+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800a55e: 2303 movs r3, #3
|
|
800a560: e01b b.n 800a59a <USB_CoreReset+0x56>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
800a562: 687b ldr r3, [r7, #4]
|
|
800a564: 691b ldr r3, [r3, #16]
|
|
800a566: 2b00 cmp r3, #0
|
|
800a568: daf2 bge.n 800a550 <USB_CoreReset+0xc>
|
|
|
|
/* Core Soft Reset */
|
|
count = 0U;
|
|
800a56a: 2300 movs r3, #0
|
|
800a56c: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
|
800a56e: 687b ldr r3, [r7, #4]
|
|
800a570: 691b ldr r3, [r3, #16]
|
|
800a572: f043 0201 orr.w r2, r3, #1
|
|
800a576: 687b ldr r3, [r7, #4]
|
|
800a578: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
800a57a: 68fb ldr r3, [r7, #12]
|
|
800a57c: 3301 adds r3, #1
|
|
800a57e: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800a580: 68fb ldr r3, [r7, #12]
|
|
800a582: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800a586: d901 bls.n 800a58c <USB_CoreReset+0x48>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800a588: 2303 movs r3, #3
|
|
800a58a: e006 b.n 800a59a <USB_CoreReset+0x56>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
|
800a58c: 687b ldr r3, [r7, #4]
|
|
800a58e: 691b ldr r3, [r3, #16]
|
|
800a590: f003 0301 and.w r3, r3, #1
|
|
800a594: 2b01 cmp r3, #1
|
|
800a596: d0f0 beq.n 800a57a <USB_CoreReset+0x36>
|
|
|
|
return HAL_OK;
|
|
800a598: 2300 movs r3, #0
|
|
}
|
|
800a59a: 4618 mov r0, r3
|
|
800a59c: 3714 adds r7, #20
|
|
800a59e: 46bd mov sp, r7
|
|
800a5a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a5a4: 4770 bx lr
|
|
|
|
0800a5a6 <Hex2Num>:
|
|
* @param a: character to convert
|
|
* @retval integer value.
|
|
*/
|
|
|
|
static uint8_t Hex2Num(char a)
|
|
{
|
|
800a5a6: b480 push {r7}
|
|
800a5a8: b083 sub sp, #12
|
|
800a5aa: af00 add r7, sp, #0
|
|
800a5ac: 4603 mov r3, r0
|
|
800a5ae: 71fb strb r3, [r7, #7]
|
|
if (a >= '0' && a <= '9') { /* Char is num */
|
|
800a5b0: 79fb ldrb r3, [r7, #7]
|
|
800a5b2: 2b2f cmp r3, #47 @ 0x2f
|
|
800a5b4: d906 bls.n 800a5c4 <Hex2Num+0x1e>
|
|
800a5b6: 79fb ldrb r3, [r7, #7]
|
|
800a5b8: 2b39 cmp r3, #57 @ 0x39
|
|
800a5ba: d803 bhi.n 800a5c4 <Hex2Num+0x1e>
|
|
return a - '0';
|
|
800a5bc: 79fb ldrb r3, [r7, #7]
|
|
800a5be: 3b30 subs r3, #48 @ 0x30
|
|
800a5c0: b2db uxtb r3, r3
|
|
800a5c2: e014 b.n 800a5ee <Hex2Num+0x48>
|
|
} else if (a >= 'a' && a <= 'f') { /* Char is lowercase character A - Z (hex) */
|
|
800a5c4: 79fb ldrb r3, [r7, #7]
|
|
800a5c6: 2b60 cmp r3, #96 @ 0x60
|
|
800a5c8: d906 bls.n 800a5d8 <Hex2Num+0x32>
|
|
800a5ca: 79fb ldrb r3, [r7, #7]
|
|
800a5cc: 2b66 cmp r3, #102 @ 0x66
|
|
800a5ce: d803 bhi.n 800a5d8 <Hex2Num+0x32>
|
|
return (a - 'a') + 10;
|
|
800a5d0: 79fb ldrb r3, [r7, #7]
|
|
800a5d2: 3b57 subs r3, #87 @ 0x57
|
|
800a5d4: b2db uxtb r3, r3
|
|
800a5d6: e00a b.n 800a5ee <Hex2Num+0x48>
|
|
} else if (a >= 'A' && a <= 'F') { /* Char is uppercase character A - Z (hex) */
|
|
800a5d8: 79fb ldrb r3, [r7, #7]
|
|
800a5da: 2b40 cmp r3, #64 @ 0x40
|
|
800a5dc: d906 bls.n 800a5ec <Hex2Num+0x46>
|
|
800a5de: 79fb ldrb r3, [r7, #7]
|
|
800a5e0: 2b46 cmp r3, #70 @ 0x46
|
|
800a5e2: d803 bhi.n 800a5ec <Hex2Num+0x46>
|
|
return (a - 'A') + 10;
|
|
800a5e4: 79fb ldrb r3, [r7, #7]
|
|
800a5e6: 3b37 subs r3, #55 @ 0x37
|
|
800a5e8: b2db uxtb r3, r3
|
|
800a5ea: e000 b.n 800a5ee <Hex2Num+0x48>
|
|
}
|
|
|
|
return 0;
|
|
800a5ec: 2300 movs r3, #0
|
|
}
|
|
800a5ee: 4618 mov r0, r3
|
|
800a5f0: 370c adds r7, #12
|
|
800a5f2: 46bd mov sp, r7
|
|
800a5f4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a5f8: 4770 bx lr
|
|
|
|
0800a5fa <ParseHexNumber>:
|
|
* @param ptr: pointer to string
|
|
* @param cnt: pointer to the number of parsed digit
|
|
* @retval Hex value.
|
|
*/
|
|
static uint32_t ParseHexNumber(char* ptr, uint8_t* cnt)
|
|
{
|
|
800a5fa: b580 push {r7, lr}
|
|
800a5fc: b084 sub sp, #16
|
|
800a5fe: af00 add r7, sp, #0
|
|
800a600: 6078 str r0, [r7, #4]
|
|
800a602: 6039 str r1, [r7, #0]
|
|
uint32_t sum = 0;
|
|
800a604: 2300 movs r3, #0
|
|
800a606: 60fb str r3, [r7, #12]
|
|
uint8_t i = 0;
|
|
800a608: 2300 movs r3, #0
|
|
800a60a: 72fb strb r3, [r7, #11]
|
|
|
|
while (CHARISHEXNUM(*ptr)) { /* Parse number */
|
|
800a60c: e012 b.n 800a634 <ParseHexNumber+0x3a>
|
|
sum <<= 4;
|
|
800a60e: 68fb ldr r3, [r7, #12]
|
|
800a610: 011b lsls r3, r3, #4
|
|
800a612: 60fb str r3, [r7, #12]
|
|
sum += Hex2Num(*ptr);
|
|
800a614: 687b ldr r3, [r7, #4]
|
|
800a616: 781b ldrb r3, [r3, #0]
|
|
800a618: 4618 mov r0, r3
|
|
800a61a: f7ff ffc4 bl 800a5a6 <Hex2Num>
|
|
800a61e: 4603 mov r3, r0
|
|
800a620: 461a mov r2, r3
|
|
800a622: 68fb ldr r3, [r7, #12]
|
|
800a624: 4413 add r3, r2
|
|
800a626: 60fb str r3, [r7, #12]
|
|
ptr++;
|
|
800a628: 687b ldr r3, [r7, #4]
|
|
800a62a: 3301 adds r3, #1
|
|
800a62c: 607b str r3, [r7, #4]
|
|
i++;
|
|
800a62e: 7afb ldrb r3, [r7, #11]
|
|
800a630: 3301 adds r3, #1
|
|
800a632: 72fb strb r3, [r7, #11]
|
|
while (CHARISHEXNUM(*ptr)) { /* Parse number */
|
|
800a634: 687b ldr r3, [r7, #4]
|
|
800a636: 781b ldrb r3, [r3, #0]
|
|
800a638: 2b2f cmp r3, #47 @ 0x2f
|
|
800a63a: d903 bls.n 800a644 <ParseHexNumber+0x4a>
|
|
800a63c: 687b ldr r3, [r7, #4]
|
|
800a63e: 781b ldrb r3, [r3, #0]
|
|
800a640: 2b39 cmp r3, #57 @ 0x39
|
|
800a642: d9e4 bls.n 800a60e <ParseHexNumber+0x14>
|
|
800a644: 687b ldr r3, [r7, #4]
|
|
800a646: 781b ldrb r3, [r3, #0]
|
|
800a648: 2b60 cmp r3, #96 @ 0x60
|
|
800a64a: d903 bls.n 800a654 <ParseHexNumber+0x5a>
|
|
800a64c: 687b ldr r3, [r7, #4]
|
|
800a64e: 781b ldrb r3, [r3, #0]
|
|
800a650: 2b66 cmp r3, #102 @ 0x66
|
|
800a652: d9dc bls.n 800a60e <ParseHexNumber+0x14>
|
|
800a654: 687b ldr r3, [r7, #4]
|
|
800a656: 781b ldrb r3, [r3, #0]
|
|
800a658: 2b40 cmp r3, #64 @ 0x40
|
|
800a65a: d903 bls.n 800a664 <ParseHexNumber+0x6a>
|
|
800a65c: 687b ldr r3, [r7, #4]
|
|
800a65e: 781b ldrb r3, [r3, #0]
|
|
800a660: 2b46 cmp r3, #70 @ 0x46
|
|
800a662: d9d4 bls.n 800a60e <ParseHexNumber+0x14>
|
|
}
|
|
|
|
if (cnt != NULL) { /* Save number of characters used for number */
|
|
800a664: 683b ldr r3, [r7, #0]
|
|
800a666: 2b00 cmp r3, #0
|
|
800a668: d002 beq.n 800a670 <ParseHexNumber+0x76>
|
|
*cnt = i;
|
|
800a66a: 683b ldr r3, [r7, #0]
|
|
800a66c: 7afa ldrb r2, [r7, #11]
|
|
800a66e: 701a strb r2, [r3, #0]
|
|
}
|
|
return sum; /* Return number */
|
|
800a670: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800a672: 4618 mov r0, r3
|
|
800a674: 3710 adds r7, #16
|
|
800a676: 46bd mov sp, r7
|
|
800a678: bd80 pop {r7, pc}
|
|
|
|
0800a67a <ParseNumber>:
|
|
* @param ptr: pointer to string
|
|
* @param cnt: pointer to the number of parsed digit
|
|
* @retval integer value.
|
|
*/
|
|
static int32_t ParseNumber(char* ptr, uint8_t* cnt)
|
|
{
|
|
800a67a: b480 push {r7}
|
|
800a67c: b085 sub sp, #20
|
|
800a67e: af00 add r7, sp, #0
|
|
800a680: 6078 str r0, [r7, #4]
|
|
800a682: 6039 str r1, [r7, #0]
|
|
uint8_t minus = 0, i = 0;
|
|
800a684: 2300 movs r3, #0
|
|
800a686: 73fb strb r3, [r7, #15]
|
|
800a688: 2300 movs r3, #0
|
|
800a68a: 73bb strb r3, [r7, #14]
|
|
int32_t sum = 0;
|
|
800a68c: 2300 movs r3, #0
|
|
800a68e: 60bb str r3, [r7, #8]
|
|
|
|
if (*ptr == '-') { /* Check for minus character */
|
|
800a690: 687b ldr r3, [r7, #4]
|
|
800a692: 781b ldrb r3, [r3, #0]
|
|
800a694: 2b2d cmp r3, #45 @ 0x2d
|
|
800a696: d119 bne.n 800a6cc <ParseNumber+0x52>
|
|
minus = 1;
|
|
800a698: 2301 movs r3, #1
|
|
800a69a: 73fb strb r3, [r7, #15]
|
|
ptr++;
|
|
800a69c: 687b ldr r3, [r7, #4]
|
|
800a69e: 3301 adds r3, #1
|
|
800a6a0: 607b str r3, [r7, #4]
|
|
i++;
|
|
800a6a2: 7bbb ldrb r3, [r7, #14]
|
|
800a6a4: 3301 adds r3, #1
|
|
800a6a6: 73bb strb r3, [r7, #14]
|
|
}
|
|
while (CHARISNUM(*ptr)) { /* Parse number */
|
|
800a6a8: e010 b.n 800a6cc <ParseNumber+0x52>
|
|
sum = 10 * sum + CHAR2NUM(*ptr);
|
|
800a6aa: 68ba ldr r2, [r7, #8]
|
|
800a6ac: 4613 mov r3, r2
|
|
800a6ae: 009b lsls r3, r3, #2
|
|
800a6b0: 4413 add r3, r2
|
|
800a6b2: 005b lsls r3, r3, #1
|
|
800a6b4: 461a mov r2, r3
|
|
800a6b6: 687b ldr r3, [r7, #4]
|
|
800a6b8: 781b ldrb r3, [r3, #0]
|
|
800a6ba: 3b30 subs r3, #48 @ 0x30
|
|
800a6bc: 4413 add r3, r2
|
|
800a6be: 60bb str r3, [r7, #8]
|
|
ptr++;
|
|
800a6c0: 687b ldr r3, [r7, #4]
|
|
800a6c2: 3301 adds r3, #1
|
|
800a6c4: 607b str r3, [r7, #4]
|
|
i++;
|
|
800a6c6: 7bbb ldrb r3, [r7, #14]
|
|
800a6c8: 3301 adds r3, #1
|
|
800a6ca: 73bb strb r3, [r7, #14]
|
|
while (CHARISNUM(*ptr)) { /* Parse number */
|
|
800a6cc: 687b ldr r3, [r7, #4]
|
|
800a6ce: 781b ldrb r3, [r3, #0]
|
|
800a6d0: 2b2f cmp r3, #47 @ 0x2f
|
|
800a6d2: d903 bls.n 800a6dc <ParseNumber+0x62>
|
|
800a6d4: 687b ldr r3, [r7, #4]
|
|
800a6d6: 781b ldrb r3, [r3, #0]
|
|
800a6d8: 2b39 cmp r3, #57 @ 0x39
|
|
800a6da: d9e6 bls.n 800a6aa <ParseNumber+0x30>
|
|
}
|
|
if (cnt != NULL) { /* Save number of characters used for number */
|
|
800a6dc: 683b ldr r3, [r7, #0]
|
|
800a6de: 2b00 cmp r3, #0
|
|
800a6e0: d002 beq.n 800a6e8 <ParseNumber+0x6e>
|
|
*cnt = i;
|
|
800a6e2: 683b ldr r3, [r7, #0]
|
|
800a6e4: 7bba ldrb r2, [r7, #14]
|
|
800a6e6: 701a strb r2, [r3, #0]
|
|
}
|
|
if (minus) { /* Minus detected */
|
|
800a6e8: 7bfb ldrb r3, [r7, #15]
|
|
800a6ea: 2b00 cmp r3, #0
|
|
800a6ec: d002 beq.n 800a6f4 <ParseNumber+0x7a>
|
|
return 0 - sum;
|
|
800a6ee: 68bb ldr r3, [r7, #8]
|
|
800a6f0: 425b negs r3, r3
|
|
800a6f2: e000 b.n 800a6f6 <ParseNumber+0x7c>
|
|
}
|
|
return sum; /* Return number */
|
|
800a6f4: 68bb ldr r3, [r7, #8]
|
|
}
|
|
800a6f6: 4618 mov r0, r3
|
|
800a6f8: 3714 adds r7, #20
|
|
800a6fa: 46bd mov sp, r7
|
|
800a6fc: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a700: 4770 bx lr
|
|
|
|
0800a702 <ParseMAC>:
|
|
* @param ptr: pointer to string
|
|
* @param arr: pointer to MAC array
|
|
* @retval None.
|
|
*/
|
|
static void ParseMAC(char* ptr, uint8_t* arr)
|
|
{
|
|
800a702: b580 push {r7, lr}
|
|
800a704: b084 sub sp, #16
|
|
800a706: af00 add r7, sp, #0
|
|
800a708: 6078 str r0, [r7, #4]
|
|
800a70a: 6039 str r1, [r7, #0]
|
|
uint8_t hexnum = 0, hexcnt;
|
|
800a70c: 2300 movs r3, #0
|
|
800a70e: 73fb strb r3, [r7, #15]
|
|
|
|
while(* ptr) {
|
|
800a710: e019 b.n 800a746 <ParseMAC+0x44>
|
|
hexcnt = 1;
|
|
800a712: 2301 movs r3, #1
|
|
800a714: 73bb strb r3, [r7, #14]
|
|
if(*ptr != ':')
|
|
800a716: 687b ldr r3, [r7, #4]
|
|
800a718: 781b ldrb r3, [r3, #0]
|
|
800a71a: 2b3a cmp r3, #58 @ 0x3a
|
|
800a71c: d00e beq.n 800a73c <ParseMAC+0x3a>
|
|
{
|
|
arr[hexnum++] = ParseHexNumber(ptr, &hexcnt);
|
|
800a71e: f107 030e add.w r3, r7, #14
|
|
800a722: 4619 mov r1, r3
|
|
800a724: 6878 ldr r0, [r7, #4]
|
|
800a726: f7ff ff68 bl 800a5fa <ParseHexNumber>
|
|
800a72a: 4601 mov r1, r0
|
|
800a72c: 7bfb ldrb r3, [r7, #15]
|
|
800a72e: 1c5a adds r2, r3, #1
|
|
800a730: 73fa strb r2, [r7, #15]
|
|
800a732: 461a mov r2, r3
|
|
800a734: 683b ldr r3, [r7, #0]
|
|
800a736: 4413 add r3, r2
|
|
800a738: b2ca uxtb r2, r1
|
|
800a73a: 701a strb r2, [r3, #0]
|
|
}
|
|
ptr = ptr + hexcnt;
|
|
800a73c: 7bbb ldrb r3, [r7, #14]
|
|
800a73e: 461a mov r2, r3
|
|
800a740: 687b ldr r3, [r7, #4]
|
|
800a742: 4413 add r3, r2
|
|
800a744: 607b str r3, [r7, #4]
|
|
while(* ptr) {
|
|
800a746: 687b ldr r3, [r7, #4]
|
|
800a748: 781b ldrb r3, [r3, #0]
|
|
800a74a: 2b00 cmp r3, #0
|
|
800a74c: d1e1 bne.n 800a712 <ParseMAC+0x10>
|
|
}
|
|
}
|
|
800a74e: bf00 nop
|
|
800a750: bf00 nop
|
|
800a752: 3710 adds r7, #16
|
|
800a754: 46bd mov sp, r7
|
|
800a756: bd80 pop {r7, pc}
|
|
|
|
0800a758 <ParseIP>:
|
|
* @param ptr: pointer to string
|
|
* @param arr: pointer to IP array
|
|
* @retval None.
|
|
*/
|
|
static void ParseIP(char* ptr, uint8_t* arr)
|
|
{
|
|
800a758: b580 push {r7, lr}
|
|
800a75a: b084 sub sp, #16
|
|
800a75c: af00 add r7, sp, #0
|
|
800a75e: 6078 str r0, [r7, #4]
|
|
800a760: 6039 str r1, [r7, #0]
|
|
uint8_t hexnum = 0, hexcnt;
|
|
800a762: 2300 movs r3, #0
|
|
800a764: 73fb strb r3, [r7, #15]
|
|
|
|
while(* ptr) {
|
|
800a766: e019 b.n 800a79c <ParseIP+0x44>
|
|
hexcnt = 1;
|
|
800a768: 2301 movs r3, #1
|
|
800a76a: 73bb strb r3, [r7, #14]
|
|
if(*ptr != '.')
|
|
800a76c: 687b ldr r3, [r7, #4]
|
|
800a76e: 781b ldrb r3, [r3, #0]
|
|
800a770: 2b2e cmp r3, #46 @ 0x2e
|
|
800a772: d00e beq.n 800a792 <ParseIP+0x3a>
|
|
{
|
|
arr[hexnum++] = ParseNumber(ptr, &hexcnt);
|
|
800a774: f107 030e add.w r3, r7, #14
|
|
800a778: 4619 mov r1, r3
|
|
800a77a: 6878 ldr r0, [r7, #4]
|
|
800a77c: f7ff ff7d bl 800a67a <ParseNumber>
|
|
800a780: 4601 mov r1, r0
|
|
800a782: 7bfb ldrb r3, [r7, #15]
|
|
800a784: 1c5a adds r2, r3, #1
|
|
800a786: 73fa strb r2, [r7, #15]
|
|
800a788: 461a mov r2, r3
|
|
800a78a: 683b ldr r3, [r7, #0]
|
|
800a78c: 4413 add r3, r2
|
|
800a78e: b2ca uxtb r2, r1
|
|
800a790: 701a strb r2, [r3, #0]
|
|
}
|
|
ptr = ptr + hexcnt;
|
|
800a792: 7bbb ldrb r3, [r7, #14]
|
|
800a794: 461a mov r2, r3
|
|
800a796: 687b ldr r3, [r7, #4]
|
|
800a798: 4413 add r3, r2
|
|
800a79a: 607b str r3, [r7, #4]
|
|
while(* ptr) {
|
|
800a79c: 687b ldr r3, [r7, #4]
|
|
800a79e: 781b ldrb r3, [r3, #0]
|
|
800a7a0: 2b00 cmp r3, #0
|
|
800a7a2: d1e1 bne.n 800a768 <ParseIP+0x10>
|
|
}
|
|
}
|
|
800a7a4: bf00 nop
|
|
800a7a6: bf00 nop
|
|
800a7a8: 3710 adds r7, #16
|
|
800a7aa: 46bd mov sp, r7
|
|
800a7ac: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800a7b0 <AT_ParseInfo>:
|
|
* @param Obj: pointer to module handle
|
|
* @param ptr: pointer to string
|
|
* @retval None.
|
|
*/
|
|
static void AT_ParseInfo(ES_WIFIObject_t *Obj,uint8_t *pdata)
|
|
{
|
|
800a7b0: b580 push {r7, lr}
|
|
800a7b2: b084 sub sp, #16
|
|
800a7b4: af00 add r7, sp, #0
|
|
800a7b6: 6078 str r0, [r7, #4]
|
|
800a7b8: 6039 str r1, [r7, #0]
|
|
char *ptr;
|
|
uint8_t num = 0;
|
|
800a7ba: 2300 movs r3, #0
|
|
800a7bc: 72fb strb r3, [r7, #11]
|
|
|
|
ptr = strtok((char *)pdata + 2, ",");
|
|
800a7be: 683b ldr r3, [r7, #0]
|
|
800a7c0: 3302 adds r3, #2
|
|
800a7c2: 4934 ldr r1, [pc, #208] @ (800a894 <AT_ParseInfo+0xe4>)
|
|
800a7c4: 4618 mov r0, r3
|
|
800a7c6: f005 febb bl 8010540 <strtok>
|
|
800a7ca: 60f8 str r0, [r7, #12]
|
|
|
|
while (ptr != NULL){
|
|
800a7cc: e05a b.n 800a884 <AT_ParseInfo+0xd4>
|
|
switch (num++) {
|
|
800a7ce: 7afb ldrb r3, [r7, #11]
|
|
800a7d0: 1c5a adds r2, r3, #1
|
|
800a7d2: 72fa strb r2, [r7, #11]
|
|
800a7d4: 2b06 cmp r3, #6
|
|
800a7d6: d84f bhi.n 800a878 <AT_ParseInfo+0xc8>
|
|
800a7d8: a201 add r2, pc, #4 @ (adr r2, 800a7e0 <AT_ParseInfo+0x30>)
|
|
800a7da: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a7de: bf00 nop
|
|
800a7e0: 0800a7fd .word 0x0800a7fd
|
|
800a7e4: 0800a80b .word 0x0800a80b
|
|
800a7e8: 0800a81b .word 0x0800a81b
|
|
800a7ec: 0800a82b .word 0x0800a82b
|
|
800a7f0: 0800a83b .word 0x0800a83b
|
|
800a7f4: 0800a84b .word 0x0800a84b
|
|
800a7f8: 0800a85f .word 0x0800a85f
|
|
case 0:
|
|
strncpy((char *)Obj->Product_ID, ptr, ES_WIFI_PRODUCT_ID_SIZE);
|
|
800a7fc: 687b ldr r3, [r7, #4]
|
|
800a7fe: 2220 movs r2, #32
|
|
800a800: 68f9 ldr r1, [r7, #12]
|
|
800a802: 4618 mov r0, r3
|
|
800a804: f005 fe89 bl 801051a <strncpy>
|
|
break;
|
|
800a808: e037 b.n 800a87a <AT_ParseInfo+0xca>
|
|
|
|
case 1:
|
|
strncpy((char *)Obj->FW_Rev, ptr, ES_WIFI_FW_REV_SIZE );
|
|
800a80a: 687b ldr r3, [r7, #4]
|
|
800a80c: 3320 adds r3, #32
|
|
800a80e: 2218 movs r2, #24
|
|
800a810: 68f9 ldr r1, [r7, #12]
|
|
800a812: 4618 mov r0, r3
|
|
800a814: f005 fe81 bl 801051a <strncpy>
|
|
break;
|
|
800a818: e02f b.n 800a87a <AT_ParseInfo+0xca>
|
|
|
|
case 2:
|
|
strncpy((char *)Obj->API_Rev, ptr, ES_WIFI_API_REV_SIZE);
|
|
800a81a: 687b ldr r3, [r7, #4]
|
|
800a81c: 3338 adds r3, #56 @ 0x38
|
|
800a81e: 2210 movs r2, #16
|
|
800a820: 68f9 ldr r1, [r7, #12]
|
|
800a822: 4618 mov r0, r3
|
|
800a824: f005 fe79 bl 801051a <strncpy>
|
|
break;
|
|
800a828: e027 b.n 800a87a <AT_ParseInfo+0xca>
|
|
|
|
case 3:
|
|
strncpy((char *)Obj->Stack_Rev, ptr, ES_WIFI_STACK_REV_SIZE);
|
|
800a82a: 687b ldr r3, [r7, #4]
|
|
800a82c: 3348 adds r3, #72 @ 0x48
|
|
800a82e: 2210 movs r2, #16
|
|
800a830: 68f9 ldr r1, [r7, #12]
|
|
800a832: 4618 mov r0, r3
|
|
800a834: f005 fe71 bl 801051a <strncpy>
|
|
break;
|
|
800a838: e01f b.n 800a87a <AT_ParseInfo+0xca>
|
|
|
|
case 4:
|
|
strncpy((char *)Obj->RTOS_Rev, ptr, ES_WIFI_RTOS_REV_SIZE);
|
|
800a83a: 687b ldr r3, [r7, #4]
|
|
800a83c: 3358 adds r3, #88 @ 0x58
|
|
800a83e: 2210 movs r2, #16
|
|
800a840: 68f9 ldr r1, [r7, #12]
|
|
800a842: 4618 mov r0, r3
|
|
800a844: f005 fe69 bl 801051a <strncpy>
|
|
break;
|
|
800a848: e017 b.n 800a87a <AT_ParseInfo+0xca>
|
|
|
|
case 5:
|
|
Obj->CPU_Clock = ParseNumber(ptr, NULL);
|
|
800a84a: 2100 movs r1, #0
|
|
800a84c: 68f8 ldr r0, [r7, #12]
|
|
800a84e: f7ff ff14 bl 800a67a <ParseNumber>
|
|
800a852: 4603 mov r3, r0
|
|
800a854: 461a mov r2, r3
|
|
800a856: 687b ldr r3, [r7, #4]
|
|
800a858: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
break;
|
|
800a85c: e00d b.n 800a87a <AT_ParseInfo+0xca>
|
|
|
|
case 6:
|
|
ptr = strtok(ptr, "\r");
|
|
800a85e: 490e ldr r1, [pc, #56] @ (800a898 <AT_ParseInfo+0xe8>)
|
|
800a860: 68f8 ldr r0, [r7, #12]
|
|
800a862: f005 fe6d bl 8010540 <strtok>
|
|
800a866: 60f8 str r0, [r7, #12]
|
|
strncpy((char *)Obj->Product_Name, ptr, ES_WIFI_PRODUCT_NAME_SIZE);
|
|
800a868: 687b ldr r3, [r7, #4]
|
|
800a86a: 3368 adds r3, #104 @ 0x68
|
|
800a86c: 2220 movs r2, #32
|
|
800a86e: 68f9 ldr r1, [r7, #12]
|
|
800a870: 4618 mov r0, r3
|
|
800a872: f005 fe52 bl 801051a <strncpy>
|
|
break;
|
|
800a876: e000 b.n 800a87a <AT_ParseInfo+0xca>
|
|
|
|
default: break;
|
|
800a878: bf00 nop
|
|
}
|
|
ptr = strtok(NULL, ",");
|
|
800a87a: 4906 ldr r1, [pc, #24] @ (800a894 <AT_ParseInfo+0xe4>)
|
|
800a87c: 2000 movs r0, #0
|
|
800a87e: f005 fe5f bl 8010540 <strtok>
|
|
800a882: 60f8 str r0, [r7, #12]
|
|
while (ptr != NULL){
|
|
800a884: 68fb ldr r3, [r7, #12]
|
|
800a886: 2b00 cmp r3, #0
|
|
800a888: d1a1 bne.n 800a7ce <AT_ParseInfo+0x1e>
|
|
}
|
|
}
|
|
800a88a: bf00 nop
|
|
800a88c: bf00 nop
|
|
800a88e: 3710 adds r7, #16
|
|
800a890: 46bd mov sp, r7
|
|
800a892: bd80 pop {r7, pc}
|
|
800a894: 08014298 .word 0x08014298
|
|
800a898: 0801429c .word 0x0801429c
|
|
|
|
0800a89c <AT_ParseConnSettings>:
|
|
* @param NetSettings: settings
|
|
* @param pdata: pointer to data
|
|
* @retval None.
|
|
*/
|
|
static void AT_ParseConnSettings(char *pdata, ES_WIFI_Network_t *NetSettings)
|
|
{
|
|
800a89c: b580 push {r7, lr}
|
|
800a89e: b084 sub sp, #16
|
|
800a8a0: af00 add r7, sp, #0
|
|
800a8a2: 6078 str r0, [r7, #4]
|
|
800a8a4: 6039 str r1, [r7, #0]
|
|
uint8_t num = 0;
|
|
800a8a6: 2300 movs r3, #0
|
|
800a8a8: 73fb strb r3, [r7, #15]
|
|
char *ptr;
|
|
|
|
ptr = strtok(pdata + 2, ",");
|
|
800a8aa: 687b ldr r3, [r7, #4]
|
|
800a8ac: 3302 adds r3, #2
|
|
800a8ae: 4952 ldr r1, [pc, #328] @ (800a9f8 <AT_ParseConnSettings+0x15c>)
|
|
800a8b0: 4618 mov r0, r3
|
|
800a8b2: f005 fe45 bl 8010540 <strtok>
|
|
800a8b6: 60b8 str r0, [r7, #8]
|
|
|
|
while (ptr != NULL) {
|
|
800a8b8: e095 b.n 800a9e6 <AT_ParseConnSettings+0x14a>
|
|
switch (num++) {
|
|
800a8ba: 7bfb ldrb r3, [r7, #15]
|
|
800a8bc: 1c5a adds r2, r3, #1
|
|
800a8be: 73fa strb r2, [r7, #15]
|
|
800a8c0: 2b0b cmp r3, #11
|
|
800a8c2: d87f bhi.n 800a9c4 <AT_ParseConnSettings+0x128>
|
|
800a8c4: a201 add r2, pc, #4 @ (adr r2, 800a8cc <AT_ParseConnSettings+0x30>)
|
|
800a8c6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a8ca: bf00 nop
|
|
800a8cc: 0800a8fd .word 0x0800a8fd
|
|
800a8d0: 0800a90b .word 0x0800a90b
|
|
800a8d4: 0800a91b .word 0x0800a91b
|
|
800a8d8: 0800a92f .word 0x0800a92f
|
|
800a8dc: 0800a943 .word 0x0800a943
|
|
800a8e0: 0800a957 .word 0x0800a957
|
|
800a8e4: 0800a965 .word 0x0800a965
|
|
800a8e8: 0800a973 .word 0x0800a973
|
|
800a8ec: 0800a981 .word 0x0800a981
|
|
800a8f0: 0800a98f .word 0x0800a98f
|
|
800a8f4: 0800a99d .word 0x0800a99d
|
|
800a8f8: 0800a9b1 .word 0x0800a9b1
|
|
case 0:
|
|
strncpy((char *)NetSettings->SSID, ptr, ES_WIFI_MAX_SSID_NAME_SIZE + 1);
|
|
800a8fc: 683b ldr r3, [r7, #0]
|
|
800a8fe: 2221 movs r2, #33 @ 0x21
|
|
800a900: 68b9 ldr r1, [r7, #8]
|
|
800a902: 4618 mov r0, r3
|
|
800a904: f005 fe09 bl 801051a <strncpy>
|
|
break;
|
|
800a908: e05d b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 1:
|
|
strncpy((char *)NetSettings->pswd, ptr, ES_WIFI_MAX_PSWD_NAME_SIZE + 1);
|
|
800a90a: 683b ldr r3, [r7, #0]
|
|
800a90c: 3321 adds r3, #33 @ 0x21
|
|
800a90e: 2221 movs r2, #33 @ 0x21
|
|
800a910: 68b9 ldr r1, [r7, #8]
|
|
800a912: 4618 mov r0, r3
|
|
800a914: f005 fe01 bl 801051a <strncpy>
|
|
break;
|
|
800a918: e055 b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 2:
|
|
NetSettings->Security = (ES_WIFI_SecurityType_t)ParseNumber(ptr, NULL);
|
|
800a91a: 2100 movs r1, #0
|
|
800a91c: 68b8 ldr r0, [r7, #8]
|
|
800a91e: f7ff feac bl 800a67a <ParseNumber>
|
|
800a922: 4603 mov r3, r0
|
|
800a924: b2da uxtb r2, r3
|
|
800a926: 683b ldr r3, [r7, #0]
|
|
800a928: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
break;
|
|
800a92c: e04b b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 3:
|
|
NetSettings->DHCP_IsEnabled = ParseNumber(ptr, NULL);
|
|
800a92e: 2100 movs r1, #0
|
|
800a930: 68b8 ldr r0, [r7, #8]
|
|
800a932: f7ff fea2 bl 800a67a <ParseNumber>
|
|
800a936: 4603 mov r3, r0
|
|
800a938: b2da uxtb r2, r3
|
|
800a93a: 683b ldr r3, [r7, #0]
|
|
800a93c: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
break;
|
|
800a940: e041 b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 4:
|
|
NetSettings->IP_Ver = (ES_WIFI_IPVer_t)ParseNumber(ptr, NULL);
|
|
800a942: 2100 movs r1, #0
|
|
800a944: 68b8 ldr r0, [r7, #8]
|
|
800a946: f7ff fe98 bl 800a67a <ParseNumber>
|
|
800a94a: 4603 mov r3, r0
|
|
800a94c: b2da uxtb r2, r3
|
|
800a94e: 683b ldr r3, [r7, #0]
|
|
800a950: f883 2047 strb.w r2, [r3, #71] @ 0x47
|
|
break;
|
|
800a954: e037 b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 5:
|
|
ParseIP(ptr, NetSettings->IP_Addr);
|
|
800a956: 683b ldr r3, [r7, #0]
|
|
800a958: 3348 adds r3, #72 @ 0x48
|
|
800a95a: 4619 mov r1, r3
|
|
800a95c: 68b8 ldr r0, [r7, #8]
|
|
800a95e: f7ff fefb bl 800a758 <ParseIP>
|
|
break;
|
|
800a962: e030 b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 6:
|
|
ParseIP(ptr, NetSettings->IP_Mask);
|
|
800a964: 683b ldr r3, [r7, #0]
|
|
800a966: 334c adds r3, #76 @ 0x4c
|
|
800a968: 4619 mov r1, r3
|
|
800a96a: 68b8 ldr r0, [r7, #8]
|
|
800a96c: f7ff fef4 bl 800a758 <ParseIP>
|
|
break;
|
|
800a970: e029 b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 7:
|
|
ParseIP(ptr, NetSettings->Gateway_Addr);
|
|
800a972: 683b ldr r3, [r7, #0]
|
|
800a974: 3350 adds r3, #80 @ 0x50
|
|
800a976: 4619 mov r1, r3
|
|
800a978: 68b8 ldr r0, [r7, #8]
|
|
800a97a: f7ff feed bl 800a758 <ParseIP>
|
|
break;
|
|
800a97e: e022 b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 8:
|
|
ParseIP(ptr, NetSettings->DNS1);
|
|
800a980: 683b ldr r3, [r7, #0]
|
|
800a982: 3354 adds r3, #84 @ 0x54
|
|
800a984: 4619 mov r1, r3
|
|
800a986: 68b8 ldr r0, [r7, #8]
|
|
800a988: f7ff fee6 bl 800a758 <ParseIP>
|
|
break;
|
|
800a98c: e01b b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 9:
|
|
ParseIP(ptr, NetSettings->DNS2);
|
|
800a98e: 683b ldr r3, [r7, #0]
|
|
800a990: 3358 adds r3, #88 @ 0x58
|
|
800a992: 4619 mov r1, r3
|
|
800a994: 68b8 ldr r0, [r7, #8]
|
|
800a996: f7ff fedf bl 800a758 <ParseIP>
|
|
break;
|
|
800a99a: e014 b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 10:
|
|
NetSettings->JoinRetries = ParseNumber(ptr, NULL);
|
|
800a99c: 2100 movs r1, #0
|
|
800a99e: 68b8 ldr r0, [r7, #8]
|
|
800a9a0: f7ff fe6b bl 800a67a <ParseNumber>
|
|
800a9a4: 4603 mov r3, r0
|
|
800a9a6: b2da uxtb r2, r3
|
|
800a9a8: 683b ldr r3, [r7, #0]
|
|
800a9aa: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
break;
|
|
800a9ae: e00a b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
case 11:
|
|
NetSettings->AutoConnect = ParseNumber(ptr, NULL);
|
|
800a9b0: 2100 movs r1, #0
|
|
800a9b2: 68b8 ldr r0, [r7, #8]
|
|
800a9b4: f7ff fe61 bl 800a67a <ParseNumber>
|
|
800a9b8: 4603 mov r3, r0
|
|
800a9ba: b2da uxtb r2, r3
|
|
800a9bc: 683b ldr r3, [r7, #0]
|
|
800a9be: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
break;
|
|
800a9c2: e000 b.n 800a9c6 <AT_ParseConnSettings+0x12a>
|
|
|
|
default:
|
|
break;
|
|
800a9c4: bf00 nop
|
|
}
|
|
ptr = strtok(NULL, ",");
|
|
800a9c6: 490c ldr r1, [pc, #48] @ (800a9f8 <AT_ParseConnSettings+0x15c>)
|
|
800a9c8: 2000 movs r0, #0
|
|
800a9ca: f005 fdb9 bl 8010540 <strtok>
|
|
800a9ce: 60b8 str r0, [r7, #8]
|
|
if ((ptr != NULL) && (ptr[-1] == ','))
|
|
800a9d0: 68bb ldr r3, [r7, #8]
|
|
800a9d2: 2b00 cmp r3, #0
|
|
800a9d4: d007 beq.n 800a9e6 <AT_ParseConnSettings+0x14a>
|
|
800a9d6: 68bb ldr r3, [r7, #8]
|
|
800a9d8: 3b01 subs r3, #1
|
|
800a9da: 781b ldrb r3, [r3, #0]
|
|
800a9dc: 2b2c cmp r3, #44 @ 0x2c
|
|
800a9de: d102 bne.n 800a9e6 <AT_ParseConnSettings+0x14a>
|
|
{ /* Ignore empty fields */
|
|
num++;
|
|
800a9e0: 7bfb ldrb r3, [r7, #15]
|
|
800a9e2: 3301 adds r3, #1
|
|
800a9e4: 73fb strb r3, [r7, #15]
|
|
while (ptr != NULL) {
|
|
800a9e6: 68bb ldr r3, [r7, #8]
|
|
800a9e8: 2b00 cmp r3, #0
|
|
800a9ea: f47f af66 bne.w 800a8ba <AT_ParseConnSettings+0x1e>
|
|
}
|
|
}
|
|
}
|
|
800a9ee: bf00 nop
|
|
800a9f0: bf00 nop
|
|
800a9f2: 3710 adds r7, #16
|
|
800a9f4: 46bd mov sp, r7
|
|
800a9f6: bd80 pop {r7, pc}
|
|
800a9f8: 08014298 .word 0x08014298
|
|
|
|
0800a9fc <AT_ParseIsConnected>:
|
|
* @param pdata: pointer to data
|
|
* @param isConnected: pointer to result
|
|
* @retval None.
|
|
*/
|
|
static void AT_ParseIsConnected(char *pdata, uint8_t *isConnected)
|
|
{
|
|
800a9fc: b480 push {r7}
|
|
800a9fe: b083 sub sp, #12
|
|
800aa00: af00 add r7, sp, #0
|
|
800aa02: 6078 str r0, [r7, #4]
|
|
800aa04: 6039 str r1, [r7, #0]
|
|
*isConnected = (pdata[2] == '1') ? 1 : 0;
|
|
800aa06: 687b ldr r3, [r7, #4]
|
|
800aa08: 3302 adds r3, #2
|
|
800aa0a: 781b ldrb r3, [r3, #0]
|
|
800aa0c: 2b31 cmp r3, #49 @ 0x31
|
|
800aa0e: bf0c ite eq
|
|
800aa10: 2301 moveq r3, #1
|
|
800aa12: 2300 movne r3, #0
|
|
800aa14: b2db uxtb r3, r3
|
|
800aa16: 461a mov r2, r3
|
|
800aa18: 683b ldr r3, [r7, #0]
|
|
800aa1a: 701a strb r2, [r3, #0]
|
|
}
|
|
800aa1c: bf00 nop
|
|
800aa1e: 370c adds r7, #12
|
|
800aa20: 46bd mov sp, r7
|
|
800aa22: f85d 7b04 ldr.w r7, [sp], #4
|
|
800aa26: 4770 bx lr
|
|
|
|
0800aa28 <AT_ExecuteCommand>:
|
|
* @param cmd: pointer to command string
|
|
* @param pdata: pointer to returned data
|
|
* @retval Operation Status.
|
|
*/
|
|
static ES_WIFI_Status_t AT_ExecuteCommand(ES_WIFIObject_t *Obj, uint8_t* cmd, uint8_t *pdata)
|
|
{
|
|
800aa28: b590 push {r4, r7, lr}
|
|
800aa2a: b087 sub sp, #28
|
|
800aa2c: af00 add r7, sp, #0
|
|
800aa2e: 60f8 str r0, [r7, #12]
|
|
800aa30: 60b9 str r1, [r7, #8]
|
|
800aa32: 607a str r2, [r7, #4]
|
|
int ret = 0;
|
|
800aa34: 2300 movs r3, #0
|
|
800aa36: 613b str r3, [r7, #16]
|
|
int16_t recv_len = 0;
|
|
800aa38: 2300 movs r3, #0
|
|
800aa3a: 82fb strh r3, [r7, #22]
|
|
LOCK_WIFI();
|
|
|
|
ret = Obj->fops.IO_Send(cmd, strlen((char*)cmd), Obj->Timeout);
|
|
800aa3c: 68fb ldr r3, [r7, #12]
|
|
800aa3e: f8d3 4120 ldr.w r4, [r3, #288] @ 0x120
|
|
800aa42: 68b8 ldr r0, [r7, #8]
|
|
800aa44: f7f5 fc14 bl 8000270 <strlen>
|
|
800aa48: 4603 mov r3, r0
|
|
800aa4a: b299 uxth r1, r3
|
|
800aa4c: 68fb ldr r3, [r7, #12]
|
|
800aa4e: f8d3 38f8 ldr.w r3, [r3, #2296] @ 0x8f8
|
|
800aa52: 461a mov r2, r3
|
|
800aa54: 68b8 ldr r0, [r7, #8]
|
|
800aa56: 47a0 blx r4
|
|
800aa58: 4603 mov r3, r0
|
|
800aa5a: 613b str r3, [r7, #16]
|
|
|
|
if( ret > 0)
|
|
800aa5c: 693b ldr r3, [r7, #16]
|
|
800aa5e: 2b00 cmp r3, #0
|
|
800aa60: dd3e ble.n 800aae0 <AT_ExecuteCommand+0xb8>
|
|
{
|
|
recv_len = Obj->fops.IO_Receive(pdata, ES_WIFI_DATA_SIZE, Obj->Timeout);
|
|
800aa62: 68fb ldr r3, [r7, #12]
|
|
800aa64: f8d3 3124 ldr.w r3, [r3, #292] @ 0x124
|
|
800aa68: 68fa ldr r2, [r7, #12]
|
|
800aa6a: f8d2 28f8 ldr.w r2, [r2, #2296] @ 0x8f8
|
|
800aa6e: f44f 61fa mov.w r1, #2000 @ 0x7d0
|
|
800aa72: 6878 ldr r0, [r7, #4]
|
|
800aa74: 4798 blx r3
|
|
800aa76: 4603 mov r3, r0
|
|
800aa78: 82fb strh r3, [r7, #22]
|
|
if((recv_len > 0) && (recv_len <= ES_WIFI_DATA_SIZE))
|
|
800aa7a: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800aa7e: 2b00 cmp r3, #0
|
|
800aa80: dd27 ble.n 800aad2 <AT_ExecuteCommand+0xaa>
|
|
800aa82: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800aa86: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0
|
|
800aa8a: dc22 bgt.n 800aad2 <AT_ExecuteCommand+0xaa>
|
|
{
|
|
if (recv_len == ES_WIFI_DATA_SIZE)
|
|
800aa8c: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800aa90: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0
|
|
800aa94: d105 bne.n 800aaa2 <AT_ExecuteCommand+0x7a>
|
|
{
|
|
// ES_WIFI_DATA_SIZE maybe too small !!
|
|
recv_len--;
|
|
800aa96: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800aa9a: b29b uxth r3, r3
|
|
800aa9c: 3b01 subs r3, #1
|
|
800aa9e: b29b uxth r3, r3
|
|
800aaa0: 82fb strh r3, [r7, #22]
|
|
}
|
|
*(pdata + recv_len) = 0;
|
|
800aaa2: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800aaa6: 687a ldr r2, [r7, #4]
|
|
800aaa8: 4413 add r3, r2
|
|
800aaaa: 2200 movs r2, #0
|
|
800aaac: 701a strb r2, [r3, #0]
|
|
if(strstr((char *)pdata, AT_OK_STRING))
|
|
800aaae: 490f ldr r1, [pc, #60] @ (800aaec <AT_ExecuteCommand+0xc4>)
|
|
800aab0: 6878 ldr r0, [r7, #4]
|
|
800aab2: f005 fda1 bl 80105f8 <strstr>
|
|
800aab6: 4603 mov r3, r0
|
|
800aab8: 2b00 cmp r3, #0
|
|
800aaba: d001 beq.n 800aac0 <AT_ExecuteCommand+0x98>
|
|
{
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_OK;
|
|
800aabc: 2300 movs r3, #0
|
|
800aabe: e010 b.n 800aae2 <AT_ExecuteCommand+0xba>
|
|
}
|
|
else if(strstr((char *)pdata, AT_ERROR_STRING))
|
|
800aac0: 490b ldr r1, [pc, #44] @ (800aaf0 <AT_ExecuteCommand+0xc8>)
|
|
800aac2: 6878 ldr r0, [r7, #4]
|
|
800aac4: f005 fd98 bl 80105f8 <strstr>
|
|
800aac8: 4603 mov r3, r0
|
|
800aaca: 2b00 cmp r3, #0
|
|
800aacc: d001 beq.n 800aad2 <AT_ExecuteCommand+0xaa>
|
|
{
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_UNEXPECTED_CLOSED_SOCKET;
|
|
800aace: 2305 movs r3, #5
|
|
800aad0: e007 b.n 800aae2 <AT_ExecuteCommand+0xba>
|
|
}
|
|
}
|
|
if (recv_len == ES_WIFI_ERROR_STUFFING_FOREVER )
|
|
800aad2: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800aad6: f113 0f04 cmn.w r3, #4
|
|
800aada: d101 bne.n 800aae0 <AT_ExecuteCommand+0xb8>
|
|
{
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_MODULE_CRASH;
|
|
800aadc: 2306 movs r3, #6
|
|
800aade: e000 b.n 800aae2 <AT_ExecuteCommand+0xba>
|
|
}
|
|
}
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_IO_ERROR;
|
|
800aae0: 2304 movs r3, #4
|
|
}
|
|
800aae2: 4618 mov r0, r3
|
|
800aae4: 371c adds r7, #28
|
|
800aae6: 46bd mov sp, r7
|
|
800aae8: bd90 pop {r4, r7, pc}
|
|
800aaea: bf00 nop
|
|
800aaec: 080142ac .word 0x080142ac
|
|
800aaf0: 080142b8 .word 0x080142b8
|
|
|
|
0800aaf4 <AT_RequestSendData>:
|
|
* @param pdata: pointer to returned data
|
|
* @retval Operation Status.
|
|
*/
|
|
|
|
static ES_WIFI_Status_t AT_RequestSendData(ES_WIFIObject_t *Obj, uint8_t* cmd, uint8_t *pcmd_data, uint16_t len, uint8_t *pdata)
|
|
{
|
|
800aaf4: b580 push {r7, lr}
|
|
800aaf6: b086 sub sp, #24
|
|
800aaf8: af00 add r7, sp, #0
|
|
800aafa: 60f8 str r0, [r7, #12]
|
|
800aafc: 60b9 str r1, [r7, #8]
|
|
800aafe: 607a str r2, [r7, #4]
|
|
800ab00: 807b strh r3, [r7, #2]
|
|
int16_t send_len = 0;
|
|
800ab02: 2300 movs r3, #0
|
|
800ab04: 82fb strh r3, [r7, #22]
|
|
int16_t recv_len = 0;
|
|
800ab06: 2300 movs r3, #0
|
|
800ab08: 82bb strh r3, [r7, #20]
|
|
uint16_t cmd_len = 0;
|
|
800ab0a: 2300 movs r3, #0
|
|
800ab0c: 827b strh r3, [r7, #18]
|
|
uint16_t n ;
|
|
|
|
LOCK_WIFI();
|
|
cmd_len = strlen((char*)cmd);
|
|
800ab0e: 68b8 ldr r0, [r7, #8]
|
|
800ab10: f7f5 fbae bl 8000270 <strlen>
|
|
800ab14: 4603 mov r3, r0
|
|
800ab16: 827b strh r3, [r7, #18]
|
|
|
|
/* can send only even number of byte on first send */
|
|
if (cmd_len & 1) return ES_WIFI_STATUS_ERROR;
|
|
800ab18: 8a7b ldrh r3, [r7, #18]
|
|
800ab1a: f003 0301 and.w r3, r3, #1
|
|
800ab1e: 2b00 cmp r3, #0
|
|
800ab20: d001 beq.n 800ab26 <AT_RequestSendData+0x32>
|
|
800ab22: 2302 movs r3, #2
|
|
800ab24: e053 b.n 800abce <AT_RequestSendData+0xda>
|
|
n=Obj->fops.IO_Send(cmd, cmd_len, Obj->Timeout);
|
|
800ab26: 68fb ldr r3, [r7, #12]
|
|
800ab28: f8d3 3120 ldr.w r3, [r3, #288] @ 0x120
|
|
800ab2c: 68fa ldr r2, [r7, #12]
|
|
800ab2e: f8d2 28f8 ldr.w r2, [r2, #2296] @ 0x8f8
|
|
800ab32: 8a79 ldrh r1, [r7, #18]
|
|
800ab34: 68b8 ldr r0, [r7, #8]
|
|
800ab36: 4798 blx r3
|
|
800ab38: 4603 mov r3, r0
|
|
800ab3a: 823b strh r3, [r7, #16]
|
|
if (n == cmd_len)
|
|
800ab3c: 8a3a ldrh r2, [r7, #16]
|
|
800ab3e: 8a7b ldrh r3, [r7, #18]
|
|
800ab40: 429a cmp r2, r3
|
|
800ab42: d143 bne.n 800abcc <AT_RequestSendData+0xd8>
|
|
{
|
|
send_len = Obj->fops.IO_Send(pcmd_data, len, Obj->Timeout);
|
|
800ab44: 68fb ldr r3, [r7, #12]
|
|
800ab46: f8d3 3120 ldr.w r3, [r3, #288] @ 0x120
|
|
800ab4a: 68fa ldr r2, [r7, #12]
|
|
800ab4c: f8d2 28f8 ldr.w r2, [r2, #2296] @ 0x8f8
|
|
800ab50: 8879 ldrh r1, [r7, #2]
|
|
800ab52: 6878 ldr r0, [r7, #4]
|
|
800ab54: 4798 blx r3
|
|
800ab56: 4603 mov r3, r0
|
|
800ab58: 82fb strh r3, [r7, #22]
|
|
if (send_len == len)
|
|
800ab5a: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
800ab5e: 887b ldrh r3, [r7, #2]
|
|
800ab60: 429a cmp r2, r3
|
|
800ab62: d131 bne.n 800abc8 <AT_RequestSendData+0xd4>
|
|
{
|
|
recv_len = Obj->fops.IO_Receive(pdata, 0, Obj->Timeout);
|
|
800ab64: 68fb ldr r3, [r7, #12]
|
|
800ab66: f8d3 3124 ldr.w r3, [r3, #292] @ 0x124
|
|
800ab6a: 68fa ldr r2, [r7, #12]
|
|
800ab6c: f8d2 28f8 ldr.w r2, [r2, #2296] @ 0x8f8
|
|
800ab70: 2100 movs r1, #0
|
|
800ab72: 6a38 ldr r0, [r7, #32]
|
|
800ab74: 4798 blx r3
|
|
800ab76: 4603 mov r3, r0
|
|
800ab78: 82bb strh r3, [r7, #20]
|
|
if (recv_len > 0)
|
|
800ab7a: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
800ab7e: 2b00 cmp r3, #0
|
|
800ab80: dd19 ble.n 800abb6 <AT_RequestSendData+0xc2>
|
|
{
|
|
*(pdata+recv_len) = 0;
|
|
800ab82: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
800ab86: 6a3a ldr r2, [r7, #32]
|
|
800ab88: 4413 add r3, r2
|
|
800ab8a: 2200 movs r2, #0
|
|
800ab8c: 701a strb r2, [r3, #0]
|
|
if(strstr((char *)pdata, AT_OK_STRING))
|
|
800ab8e: 4912 ldr r1, [pc, #72] @ (800abd8 <AT_RequestSendData+0xe4>)
|
|
800ab90: 6a38 ldr r0, [r7, #32]
|
|
800ab92: f005 fd31 bl 80105f8 <strstr>
|
|
800ab96: 4603 mov r3, r0
|
|
800ab98: 2b00 cmp r3, #0
|
|
800ab9a: d001 beq.n 800aba0 <AT_RequestSendData+0xac>
|
|
{
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_OK;
|
|
800ab9c: 2300 movs r3, #0
|
|
800ab9e: e016 b.n 800abce <AT_RequestSendData+0xda>
|
|
}
|
|
else if(strstr((char *)pdata, AT_ERROR_STRING))
|
|
800aba0: 490e ldr r1, [pc, #56] @ (800abdc <AT_RequestSendData+0xe8>)
|
|
800aba2: 6a38 ldr r0, [r7, #32]
|
|
800aba4: f005 fd28 bl 80105f8 <strstr>
|
|
800aba8: 4603 mov r3, r0
|
|
800abaa: 2b00 cmp r3, #0
|
|
800abac: d001 beq.n 800abb2 <AT_RequestSendData+0xbe>
|
|
{
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_UNEXPECTED_CLOSED_SOCKET;
|
|
800abae: 2305 movs r3, #5
|
|
800abb0: e00d b.n 800abce <AT_RequestSendData+0xda>
|
|
}
|
|
else
|
|
{
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_ERROR;
|
|
800abb2: 2302 movs r3, #2
|
|
800abb4: e00b b.n 800abce <AT_RequestSendData+0xda>
|
|
}
|
|
}
|
|
UNLOCK_WIFI();
|
|
if (recv_len == ES_WIFI_ERROR_STUFFING_FOREVER )
|
|
800abb6: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
800abba: f113 0f04 cmn.w r3, #4
|
|
800abbe: d101 bne.n 800abc4 <AT_RequestSendData+0xd0>
|
|
{
|
|
return ES_WIFI_STATUS_MODULE_CRASH;
|
|
800abc0: 2306 movs r3, #6
|
|
800abc2: e004 b.n 800abce <AT_RequestSendData+0xda>
|
|
}
|
|
return ES_WIFI_STATUS_ERROR;
|
|
800abc4: 2302 movs r3, #2
|
|
800abc6: e002 b.n 800abce <AT_RequestSendData+0xda>
|
|
}
|
|
else
|
|
{
|
|
return ES_WIFI_STATUS_ERROR;
|
|
800abc8: 2302 movs r3, #2
|
|
800abca: e000 b.n 800abce <AT_RequestSendData+0xda>
|
|
}
|
|
}
|
|
return ES_WIFI_STATUS_IO_ERROR;
|
|
800abcc: 2304 movs r3, #4
|
|
}
|
|
800abce: 4618 mov r0, r3
|
|
800abd0: 3718 adds r7, #24
|
|
800abd2: 46bd mov sp, r7
|
|
800abd4: bd80 pop {r7, pc}
|
|
800abd6: bf00 nop
|
|
800abd8: 080142ac .word 0x080142ac
|
|
800abdc: 080142b8 .word 0x080142b8
|
|
|
|
0800abe0 <AT_RequestReceiveData>:
|
|
* @param Reqlen : requested Data length.
|
|
* @param ReadData : pointer to received data length.
|
|
* @retval Operation Status.
|
|
*/
|
|
static ES_WIFI_Status_t AT_RequestReceiveData(ES_WIFIObject_t *Obj, uint8_t* cmd, char *pdata, uint16_t Reqlen, uint16_t *ReadData)
|
|
{
|
|
800abe0: b590 push {r4, r7, lr}
|
|
800abe2: b087 sub sp, #28
|
|
800abe4: af00 add r7, sp, #0
|
|
800abe6: 60f8 str r0, [r7, #12]
|
|
800abe8: 60b9 str r1, [r7, #8]
|
|
800abea: 607a str r2, [r7, #4]
|
|
800abec: 807b strh r3, [r7, #2]
|
|
int len;
|
|
uint8_t *p=Obj->CmdData;
|
|
800abee: 68fb ldr r3, [r7, #12]
|
|
800abf0: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800abf4: 613b str r3, [r7, #16]
|
|
|
|
LOCK_WIFI();
|
|
if(Obj->fops.IO_Send(cmd, strlen((char*)cmd), Obj->Timeout) > 0)
|
|
800abf6: 68fb ldr r3, [r7, #12]
|
|
800abf8: f8d3 4120 ldr.w r4, [r3, #288] @ 0x120
|
|
800abfc: 68b8 ldr r0, [r7, #8]
|
|
800abfe: f7f5 fb37 bl 8000270 <strlen>
|
|
800ac02: 4603 mov r3, r0
|
|
800ac04: b299 uxth r1, r3
|
|
800ac06: 68fb ldr r3, [r7, #12]
|
|
800ac08: f8d3 38f8 ldr.w r3, [r3, #2296] @ 0x8f8
|
|
800ac0c: 461a mov r2, r3
|
|
800ac0e: 68b8 ldr r0, [r7, #8]
|
|
800ac10: 47a0 blx r4
|
|
800ac12: 4603 mov r3, r0
|
|
800ac14: 2b00 cmp r3, #0
|
|
800ac16: dd6f ble.n 800acf8 <AT_RequestReceiveData+0x118>
|
|
{
|
|
len = Obj->fops.IO_Receive(p, 0 , Obj->Timeout);
|
|
800ac18: 68fb ldr r3, [r7, #12]
|
|
800ac1a: f8d3 3124 ldr.w r3, [r3, #292] @ 0x124
|
|
800ac1e: 68fa ldr r2, [r7, #12]
|
|
800ac20: f8d2 28f8 ldr.w r2, [r2, #2296] @ 0x8f8
|
|
800ac24: 2100 movs r1, #0
|
|
800ac26: 6938 ldr r0, [r7, #16]
|
|
800ac28: 4798 blx r3
|
|
800ac2a: 4603 mov r3, r0
|
|
800ac2c: 617b str r3, [r7, #20]
|
|
if ((p[0]!='\r') || (p[1]!='\n'))
|
|
800ac2e: 693b ldr r3, [r7, #16]
|
|
800ac30: 781b ldrb r3, [r3, #0]
|
|
800ac32: 2b0d cmp r3, #13
|
|
800ac34: d104 bne.n 800ac40 <AT_RequestReceiveData+0x60>
|
|
800ac36: 693b ldr r3, [r7, #16]
|
|
800ac38: 3301 adds r3, #1
|
|
800ac3a: 781b ldrb r3, [r3, #0]
|
|
800ac3c: 2b0a cmp r3, #10
|
|
800ac3e: d001 beq.n 800ac44 <AT_RequestReceiveData+0x64>
|
|
{
|
|
return ES_WIFI_STATUS_IO_ERROR;
|
|
800ac40: 2304 movs r3, #4
|
|
800ac42: e05a b.n 800acfa <AT_RequestReceiveData+0x11a>
|
|
}
|
|
len-=2;
|
|
800ac44: 697b ldr r3, [r7, #20]
|
|
800ac46: 3b02 subs r3, #2
|
|
800ac48: 617b str r3, [r7, #20]
|
|
p+=2;
|
|
800ac4a: 693b ldr r3, [r7, #16]
|
|
800ac4c: 3302 adds r3, #2
|
|
800ac4e: 613b str r3, [r7, #16]
|
|
if (len >= AT_OK_STRING_LEN)
|
|
800ac50: 697b ldr r3, [r7, #20]
|
|
800ac52: 2b07 cmp r3, #7
|
|
800ac54: d94a bls.n 800acec <AT_RequestReceiveData+0x10c>
|
|
{
|
|
while(len && (p[len-1]==0x15)) len--;
|
|
800ac56: e002 b.n 800ac5e <AT_RequestReceiveData+0x7e>
|
|
800ac58: 697b ldr r3, [r7, #20]
|
|
800ac5a: 3b01 subs r3, #1
|
|
800ac5c: 617b str r3, [r7, #20]
|
|
800ac5e: 697b ldr r3, [r7, #20]
|
|
800ac60: 2b00 cmp r3, #0
|
|
800ac62: d006 beq.n 800ac72 <AT_RequestReceiveData+0x92>
|
|
800ac64: 697b ldr r3, [r7, #20]
|
|
800ac66: 3b01 subs r3, #1
|
|
800ac68: 693a ldr r2, [r7, #16]
|
|
800ac6a: 4413 add r3, r2
|
|
800ac6c: 781b ldrb r3, [r3, #0]
|
|
800ac6e: 2b15 cmp r3, #21
|
|
800ac70: d0f2 beq.n 800ac58 <AT_RequestReceiveData+0x78>
|
|
p[len] = '\0';
|
|
800ac72: 697b ldr r3, [r7, #20]
|
|
800ac74: 693a ldr r2, [r7, #16]
|
|
800ac76: 4413 add r3, r2
|
|
800ac78: 2200 movs r2, #0
|
|
800ac7a: 701a strb r2, [r3, #0]
|
|
if(strstr( (char*) p + len - AT_OK_STRING_LEN, AT_OK_STRING))
|
|
800ac7c: 697b ldr r3, [r7, #20]
|
|
800ac7e: 3b08 subs r3, #8
|
|
800ac80: 693a ldr r2, [r7, #16]
|
|
800ac82: 4413 add r3, r2
|
|
800ac84: 491f ldr r1, [pc, #124] @ (800ad04 <AT_RequestReceiveData+0x124>)
|
|
800ac86: 4618 mov r0, r3
|
|
800ac88: f005 fcb6 bl 80105f8 <strstr>
|
|
800ac8c: 4603 mov r3, r0
|
|
800ac8e: 2b00 cmp r3, #0
|
|
800ac90: d016 beq.n 800acc0 <AT_RequestReceiveData+0xe0>
|
|
{
|
|
*ReadData = len - AT_OK_STRING_LEN;
|
|
800ac92: 697b ldr r3, [r7, #20]
|
|
800ac94: b29b uxth r3, r3
|
|
800ac96: 3b08 subs r3, #8
|
|
800ac98: b29a uxth r2, r3
|
|
800ac9a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ac9c: 801a strh r2, [r3, #0]
|
|
if (*ReadData > Reqlen)
|
|
800ac9e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800aca0: 881b ldrh r3, [r3, #0]
|
|
800aca2: 887a ldrh r2, [r7, #2]
|
|
800aca4: 429a cmp r2, r3
|
|
800aca6: d202 bcs.n 800acae <AT_RequestReceiveData+0xce>
|
|
{
|
|
*ReadData = Reqlen;
|
|
800aca8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800acaa: 887a ldrh r2, [r7, #2]
|
|
800acac: 801a strh r2, [r3, #0]
|
|
}
|
|
memcpy(pdata, p, *ReadData);
|
|
800acae: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800acb0: 881b ldrh r3, [r3, #0]
|
|
800acb2: 461a mov r2, r3
|
|
800acb4: 6939 ldr r1, [r7, #16]
|
|
800acb6: 6878 ldr r0, [r7, #4]
|
|
800acb8: f005 fd2b bl 8010712 <memcpy>
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_OK;
|
|
800acbc: 2300 movs r3, #0
|
|
800acbe: e01c b.n 800acfa <AT_RequestReceiveData+0x11a>
|
|
}
|
|
else if(memcmp((char *)p + len - AT_DELIMETER_LEN , AT_DELIMETER_STRING, AT_DELIMETER_LEN) == 0)
|
|
800acc0: 697b ldr r3, [r7, #20]
|
|
800acc2: 3b04 subs r3, #4
|
|
800acc4: 693a ldr r2, [r7, #16]
|
|
800acc6: 4413 add r3, r2
|
|
800acc8: 2204 movs r2, #4
|
|
800acca: 490f ldr r1, [pc, #60] @ (800ad08 <AT_RequestReceiveData+0x128>)
|
|
800accc: 4618 mov r0, r3
|
|
800acce: f005 fbeb bl 80104a8 <memcmp>
|
|
800acd2: 4603 mov r3, r0
|
|
800acd4: 2b00 cmp r3, #0
|
|
800acd6: d104 bne.n 800ace2 <AT_RequestReceiveData+0x102>
|
|
{
|
|
*ReadData = 0;
|
|
800acd8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800acda: 2200 movs r2, #0
|
|
800acdc: 801a strh r2, [r3, #0]
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_UNEXPECTED_CLOSED_SOCKET;
|
|
800acde: 2305 movs r3, #5
|
|
800ace0: e00b b.n 800acfa <AT_RequestReceiveData+0x11a>
|
|
}
|
|
|
|
UNLOCK_WIFI();
|
|
*ReadData = 0;
|
|
800ace2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ace4: 2200 movs r2, #0
|
|
800ace6: 801a strh r2, [r3, #0]
|
|
return ES_WIFI_STATUS_UNEXPECTED_CLOSED_SOCKET;
|
|
800ace8: 2305 movs r3, #5
|
|
800acea: e006 b.n 800acfa <AT_RequestReceiveData+0x11a>
|
|
}
|
|
if (len == ES_WIFI_ERROR_STUFFING_FOREVER )
|
|
800acec: 697b ldr r3, [r7, #20]
|
|
800acee: f113 0f04 cmn.w r3, #4
|
|
800acf2: d101 bne.n 800acf8 <AT_RequestReceiveData+0x118>
|
|
{
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_MODULE_CRASH;
|
|
800acf4: 2306 movs r3, #6
|
|
800acf6: e000 b.n 800acfa <AT_RequestReceiveData+0x11a>
|
|
}
|
|
}
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_IO_ERROR;
|
|
800acf8: 2304 movs r3, #4
|
|
}
|
|
800acfa: 4618 mov r0, r3
|
|
800acfc: 371c adds r7, #28
|
|
800acfe: 46bd mov sp, r7
|
|
800ad00: bd90 pop {r4, r7, pc}
|
|
800ad02: bf00 nop
|
|
800ad04: 080142ac .word 0x080142ac
|
|
800ad08: 080142c0 .word 0x080142c0
|
|
|
|
0800ad0c <ES_WIFI_Init>:
|
|
* @brief Initialize WIFI module.
|
|
* @param Obj: pointer to module handle
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_Init(ES_WIFIObject_t *Obj)
|
|
{
|
|
800ad0c: b580 push {r7, lr}
|
|
800ad0e: b084 sub sp, #16
|
|
800ad10: af00 add r7, sp, #0
|
|
800ad12: 6078 str r0, [r7, #4]
|
|
ES_WIFI_Status_t ret = ES_WIFI_STATUS_ERROR;
|
|
800ad14: 2302 movs r3, #2
|
|
800ad16: 73fb strb r3, [r7, #15]
|
|
|
|
LOCK_WIFI();
|
|
|
|
Obj->Timeout = ES_WIFI_TIMEOUT;
|
|
800ad18: 687b ldr r3, [r7, #4]
|
|
800ad1a: f247 5230 movw r2, #30000 @ 0x7530
|
|
800ad1e: f8c3 28f8 str.w r2, [r3, #2296] @ 0x8f8
|
|
|
|
if (Obj->fops.IO_Init(ES_WIFI_INIT) == 0)
|
|
800ad22: 687b ldr r3, [r7, #4]
|
|
800ad24: f8d3 3114 ldr.w r3, [r3, #276] @ 0x114
|
|
800ad28: 2000 movs r0, #0
|
|
800ad2a: 4798 blx r3
|
|
800ad2c: 4603 mov r3, r0
|
|
800ad2e: 2b00 cmp r3, #0
|
|
800ad30: d113 bne.n 800ad5a <ES_WIFI_Init+0x4e>
|
|
{
|
|
ret = AT_ExecuteCommand(Obj,(uint8_t*)"I?\r\n", Obj->CmdData);
|
|
800ad32: 687b ldr r3, [r7, #4]
|
|
800ad34: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ad38: 461a mov r2, r3
|
|
800ad3a: 490a ldr r1, [pc, #40] @ (800ad64 <ES_WIFI_Init+0x58>)
|
|
800ad3c: 6878 ldr r0, [r7, #4]
|
|
800ad3e: f7ff fe73 bl 800aa28 <AT_ExecuteCommand>
|
|
800ad42: 4603 mov r3, r0
|
|
800ad44: 73fb strb r3, [r7, #15]
|
|
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800ad46: 7bfb ldrb r3, [r7, #15]
|
|
800ad48: 2b00 cmp r3, #0
|
|
800ad4a: d106 bne.n 800ad5a <ES_WIFI_Init+0x4e>
|
|
{
|
|
AT_ParseInfo (Obj, Obj->CmdData);
|
|
800ad4c: 687b ldr r3, [r7, #4]
|
|
800ad4e: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ad52: 4619 mov r1, r3
|
|
800ad54: 6878 ldr r0, [r7, #4]
|
|
800ad56: f7ff fd2b bl 800a7b0 <AT_ParseInfo>
|
|
}
|
|
}
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800ad5a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800ad5c: 4618 mov r0, r3
|
|
800ad5e: 3710 adds r7, #16
|
|
800ad60: 46bd mov sp, r7
|
|
800ad62: bd80 pop {r7, pc}
|
|
800ad64: 080142c8 .word 0x080142c8
|
|
|
|
0800ad68 <ES_WIFI_RegisterBusIO>:
|
|
ES_WIFI_Status_t ES_WIFI_RegisterBusIO(ES_WIFIObject_t *Obj, IO_Init_Func IO_Init,
|
|
IO_DeInit_Func IO_DeInit,
|
|
IO_Delay_Func IO_Delay,
|
|
IO_Send_Func IO_Send,
|
|
IO_Receive_Func IO_Receive)
|
|
{
|
|
800ad68: b480 push {r7}
|
|
800ad6a: b085 sub sp, #20
|
|
800ad6c: af00 add r7, sp, #0
|
|
800ad6e: 60f8 str r0, [r7, #12]
|
|
800ad70: 60b9 str r1, [r7, #8]
|
|
800ad72: 607a str r2, [r7, #4]
|
|
800ad74: 603b str r3, [r7, #0]
|
|
if(!Obj || !IO_Init || !IO_DeInit || !IO_Send || !IO_Receive)
|
|
800ad76: 68fb ldr r3, [r7, #12]
|
|
800ad78: 2b00 cmp r3, #0
|
|
800ad7a: d00b beq.n 800ad94 <ES_WIFI_RegisterBusIO+0x2c>
|
|
800ad7c: 68bb ldr r3, [r7, #8]
|
|
800ad7e: 2b00 cmp r3, #0
|
|
800ad80: d008 beq.n 800ad94 <ES_WIFI_RegisterBusIO+0x2c>
|
|
800ad82: 687b ldr r3, [r7, #4]
|
|
800ad84: 2b00 cmp r3, #0
|
|
800ad86: d005 beq.n 800ad94 <ES_WIFI_RegisterBusIO+0x2c>
|
|
800ad88: 69bb ldr r3, [r7, #24]
|
|
800ad8a: 2b00 cmp r3, #0
|
|
800ad8c: d002 beq.n 800ad94 <ES_WIFI_RegisterBusIO+0x2c>
|
|
800ad8e: 69fb ldr r3, [r7, #28]
|
|
800ad90: 2b00 cmp r3, #0
|
|
800ad92: d101 bne.n 800ad98 <ES_WIFI_RegisterBusIO+0x30>
|
|
{
|
|
return ES_WIFI_STATUS_ERROR;
|
|
800ad94: 2302 movs r3, #2
|
|
800ad96: e014 b.n 800adc2 <ES_WIFI_RegisterBusIO+0x5a>
|
|
}
|
|
|
|
Obj->fops.IO_Init = IO_Init;
|
|
800ad98: 68fb ldr r3, [r7, #12]
|
|
800ad9a: 68ba ldr r2, [r7, #8]
|
|
800ad9c: f8c3 2114 str.w r2, [r3, #276] @ 0x114
|
|
Obj->fops.IO_DeInit = IO_DeInit;
|
|
800ada0: 68fb ldr r3, [r7, #12]
|
|
800ada2: 687a ldr r2, [r7, #4]
|
|
800ada4: f8c3 2118 str.w r2, [r3, #280] @ 0x118
|
|
Obj->fops.IO_Send = IO_Send;
|
|
800ada8: 68fb ldr r3, [r7, #12]
|
|
800adaa: 69ba ldr r2, [r7, #24]
|
|
800adac: f8c3 2120 str.w r2, [r3, #288] @ 0x120
|
|
Obj->fops.IO_Receive = IO_Receive;
|
|
800adb0: 68fb ldr r3, [r7, #12]
|
|
800adb2: 69fa ldr r2, [r7, #28]
|
|
800adb4: f8c3 2124 str.w r2, [r3, #292] @ 0x124
|
|
Obj->fops.IO_Delay = IO_Delay;
|
|
800adb8: 68fb ldr r3, [r7, #12]
|
|
800adba: 683a ldr r2, [r7, #0]
|
|
800adbc: f8c3 211c str.w r2, [r3, #284] @ 0x11c
|
|
|
|
return ES_WIFI_STATUS_OK;
|
|
800adc0: 2300 movs r3, #0
|
|
}
|
|
800adc2: 4618 mov r0, r3
|
|
800adc4: 3714 adds r7, #20
|
|
800adc6: 46bd mov sp, r7
|
|
800adc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800adcc: 4770 bx lr
|
|
...
|
|
|
|
0800add0 <ES_WIFI_Connect>:
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_Connect(ES_WIFIObject_t *Obj, const char* SSID,
|
|
const char* Password,
|
|
ES_WIFI_SecurityType_t SecType)
|
|
{
|
|
800add0: b580 push {r7, lr}
|
|
800add2: b086 sub sp, #24
|
|
800add4: af00 add r7, sp, #0
|
|
800add6: 60f8 str r0, [r7, #12]
|
|
800add8: 60b9 str r1, [r7, #8]
|
|
800adda: 607a str r2, [r7, #4]
|
|
800addc: 70fb strb r3, [r7, #3]
|
|
ES_WIFI_Status_t ret;
|
|
LOCK_WIFI();
|
|
|
|
sprintf((char*)Obj->CmdData,"C1=%s\r", SSID);
|
|
800adde: 68fb ldr r3, [r7, #12]
|
|
800ade0: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ade4: 68ba ldr r2, [r7, #8]
|
|
800ade6: 4932 ldr r1, [pc, #200] @ (800aeb0 <ES_WIFI_Connect+0xe0>)
|
|
800ade8: 4618 mov r0, r3
|
|
800adea: f005 fa63 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800adee: 68fb ldr r3, [r7, #12]
|
|
800adf0: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800adf4: 68fb ldr r3, [r7, #12]
|
|
800adf6: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800adfa: 461a mov r2, r3
|
|
800adfc: 68f8 ldr r0, [r7, #12]
|
|
800adfe: f7ff fe13 bl 800aa28 <AT_ExecuteCommand>
|
|
800ae02: 4603 mov r3, r0
|
|
800ae04: 75fb strb r3, [r7, #23]
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800ae06: 7dfb ldrb r3, [r7, #23]
|
|
800ae08: 2b00 cmp r3, #0
|
|
800ae0a: d14b bne.n 800aea4 <ES_WIFI_Connect+0xd4>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"C2=%s\r", Password);
|
|
800ae0c: 68fb ldr r3, [r7, #12]
|
|
800ae0e: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ae12: 687a ldr r2, [r7, #4]
|
|
800ae14: 4927 ldr r1, [pc, #156] @ (800aeb4 <ES_WIFI_Connect+0xe4>)
|
|
800ae16: 4618 mov r0, r3
|
|
800ae18: f005 fa4c bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800ae1c: 68fb ldr r3, [r7, #12]
|
|
800ae1e: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800ae22: 68fb ldr r3, [r7, #12]
|
|
800ae24: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ae28: 461a mov r2, r3
|
|
800ae2a: 68f8 ldr r0, [r7, #12]
|
|
800ae2c: f7ff fdfc bl 800aa28 <AT_ExecuteCommand>
|
|
800ae30: 4603 mov r3, r0
|
|
800ae32: 75fb strb r3, [r7, #23]
|
|
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800ae34: 7dfb ldrb r3, [r7, #23]
|
|
800ae36: 2b00 cmp r3, #0
|
|
800ae38: d134 bne.n 800aea4 <ES_WIFI_Connect+0xd4>
|
|
{
|
|
Obj->Security = SecType;
|
|
800ae3a: 68fb ldr r3, [r7, #12]
|
|
800ae3c: 78fa ldrb r2, [r7, #3]
|
|
800ae3e: f883 208c strb.w r2, [r3, #140] @ 0x8c
|
|
sprintf((char*)Obj->CmdData,"C3=%d\r", (uint8_t)SecType);
|
|
800ae42: 68fb ldr r3, [r7, #12]
|
|
800ae44: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ae48: 78fa ldrb r2, [r7, #3]
|
|
800ae4a: 491b ldr r1, [pc, #108] @ (800aeb8 <ES_WIFI_Connect+0xe8>)
|
|
800ae4c: 4618 mov r0, r3
|
|
800ae4e: f005 fa31 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800ae52: 68fb ldr r3, [r7, #12]
|
|
800ae54: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800ae58: 68fb ldr r3, [r7, #12]
|
|
800ae5a: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ae5e: 461a mov r2, r3
|
|
800ae60: 68f8 ldr r0, [r7, #12]
|
|
800ae62: f7ff fde1 bl 800aa28 <AT_ExecuteCommand>
|
|
800ae66: 4603 mov r3, r0
|
|
800ae68: 75fb strb r3, [r7, #23]
|
|
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800ae6a: 7dfb ldrb r3, [r7, #23]
|
|
800ae6c: 2b00 cmp r3, #0
|
|
800ae6e: d119 bne.n 800aea4 <ES_WIFI_Connect+0xd4>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"C0\r");
|
|
800ae70: 68fb ldr r3, [r7, #12]
|
|
800ae72: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ae76: 4911 ldr r1, [pc, #68] @ (800aebc <ES_WIFI_Connect+0xec>)
|
|
800ae78: 4618 mov r0, r3
|
|
800ae7a: f005 fa1b bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800ae7e: 68fb ldr r3, [r7, #12]
|
|
800ae80: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800ae84: 68fb ldr r3, [r7, #12]
|
|
800ae86: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800ae8a: 461a mov r2, r3
|
|
800ae8c: 68f8 ldr r0, [r7, #12]
|
|
800ae8e: f7ff fdcb bl 800aa28 <AT_ExecuteCommand>
|
|
800ae92: 4603 mov r3, r0
|
|
800ae94: 75fb strb r3, [r7, #23]
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800ae96: 7dfb ldrb r3, [r7, #23]
|
|
800ae98: 2b00 cmp r3, #0
|
|
800ae9a: d103 bne.n 800aea4 <ES_WIFI_Connect+0xd4>
|
|
{
|
|
Obj->NetSettings.IsConnected = 1;
|
|
800ae9c: 68fb ldr r3, [r7, #12]
|
|
800ae9e: 2201 movs r2, #1
|
|
800aea0: f883 20d2 strb.w r2, [r3, #210] @ 0xd2
|
|
}
|
|
}
|
|
}
|
|
}
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800aea4: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800aea6: 4618 mov r0, r3
|
|
800aea8: 3718 adds r7, #24
|
|
800aeaa: 46bd mov sp, r7
|
|
800aeac: bd80 pop {r7, pc}
|
|
800aeae: bf00 nop
|
|
800aeb0: 080142e0 .word 0x080142e0
|
|
800aeb4: 080142e8 .word 0x080142e8
|
|
800aeb8: 080142f0 .word 0x080142f0
|
|
800aebc: 080142f8 .word 0x080142f8
|
|
|
|
0800aec0 <ES_WIFI_IsConnected>:
|
|
/**
|
|
* @brief Check whether the module is connected to an access point.
|
|
* @retval Operation Status.
|
|
*/
|
|
uint8_t ES_WIFI_IsConnected(ES_WIFIObject_t *Obj)
|
|
{
|
|
800aec0: b580 push {r7, lr}
|
|
800aec2: b084 sub sp, #16
|
|
800aec4: af00 add r7, sp, #0
|
|
800aec6: 6078 str r0, [r7, #4]
|
|
ES_WIFI_Status_t ret ;
|
|
LOCK_WIFI();
|
|
|
|
sprintf((char*)Obj->CmdData,"CS\r");
|
|
800aec8: 687b ldr r3, [r7, #4]
|
|
800aeca: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800aece: 4911 ldr r1, [pc, #68] @ (800af14 <ES_WIFI_IsConnected+0x54>)
|
|
800aed0: 4618 mov r0, r3
|
|
800aed2: f005 f9ef bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800aed6: 687b ldr r3, [r7, #4]
|
|
800aed8: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800aedc: 687b ldr r3, [r7, #4]
|
|
800aede: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800aee2: 461a mov r2, r3
|
|
800aee4: 6878 ldr r0, [r7, #4]
|
|
800aee6: f7ff fd9f bl 800aa28 <AT_ExecuteCommand>
|
|
800aeea: 4603 mov r3, r0
|
|
800aeec: 73fb strb r3, [r7, #15]
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800aeee: 7bfb ldrb r3, [r7, #15]
|
|
800aef0: 2b00 cmp r3, #0
|
|
800aef2: d108 bne.n 800af06 <ES_WIFI_IsConnected+0x46>
|
|
{
|
|
AT_ParseIsConnected((char *)Obj->CmdData, &(Obj->NetSettings.IsConnected));
|
|
800aef4: 687b ldr r3, [r7, #4]
|
|
800aef6: f503 7294 add.w r2, r3, #296 @ 0x128
|
|
800aefa: 687b ldr r3, [r7, #4]
|
|
800aefc: 33d2 adds r3, #210 @ 0xd2
|
|
800aefe: 4619 mov r1, r3
|
|
800af00: 4610 mov r0, r2
|
|
800af02: f7ff fd7b bl 800a9fc <AT_ParseIsConnected>
|
|
}
|
|
UNLOCK_WIFI();
|
|
return Obj->NetSettings.IsConnected;
|
|
800af06: 687b ldr r3, [r7, #4]
|
|
800af08: f893 30d2 ldrb.w r3, [r3, #210] @ 0xd2
|
|
}
|
|
800af0c: 4618 mov r0, r3
|
|
800af0e: 3710 adds r7, #16
|
|
800af10: 46bd mov sp, r7
|
|
800af12: bd80 pop {r7, pc}
|
|
800af14: 080142fc .word 0x080142fc
|
|
|
|
0800af18 <ES_WIFI_GetNetworkSettings>:
|
|
* @param Obj: pointer to module handle
|
|
* @param Pointer to network setting structure.
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_GetNetworkSettings(ES_WIFIObject_t *Obj)
|
|
{
|
|
800af18: b580 push {r7, lr}
|
|
800af1a: b084 sub sp, #16
|
|
800af1c: af00 add r7, sp, #0
|
|
800af1e: 6078 str r0, [r7, #4]
|
|
ES_WIFI_Status_t ret;
|
|
LOCK_WIFI();
|
|
|
|
sprintf((char*)Obj->CmdData,"C?\r");
|
|
800af20: 687b ldr r3, [r7, #4]
|
|
800af22: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800af26: 4910 ldr r1, [pc, #64] @ (800af68 <ES_WIFI_GetNetworkSettings+0x50>)
|
|
800af28: 4618 mov r0, r3
|
|
800af2a: f005 f9c3 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800af2e: 687b ldr r3, [r7, #4]
|
|
800af30: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800af34: 687b ldr r3, [r7, #4]
|
|
800af36: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800af3a: 461a mov r2, r3
|
|
800af3c: 6878 ldr r0, [r7, #4]
|
|
800af3e: f7ff fd73 bl 800aa28 <AT_ExecuteCommand>
|
|
800af42: 4603 mov r3, r0
|
|
800af44: 73fb strb r3, [r7, #15]
|
|
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800af46: 7bfb ldrb r3, [r7, #15]
|
|
800af48: 2b00 cmp r3, #0
|
|
800af4a: d108 bne.n 800af5e <ES_WIFI_GetNetworkSettings+0x46>
|
|
{
|
|
AT_ParseConnSettings((char *)Obj->CmdData, &Obj->NetSettings);
|
|
800af4c: 687b ldr r3, [r7, #4]
|
|
800af4e: f503 7294 add.w r2, r3, #296 @ 0x128
|
|
800af52: 687b ldr r3, [r7, #4]
|
|
800af54: 338d adds r3, #141 @ 0x8d
|
|
800af56: 4619 mov r1, r3
|
|
800af58: 4610 mov r0, r2
|
|
800af5a: f7ff fc9f bl 800a89c <AT_ParseConnSettings>
|
|
}
|
|
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800af5e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800af60: 4618 mov r0, r3
|
|
800af62: 3710 adds r7, #16
|
|
800af64: 46bd mov sp, r7
|
|
800af66: bd80 pop {r7, pc}
|
|
800af68: 08014304 .word 0x08014304
|
|
|
|
0800af6c <ES_WIFI_GetMACAddress>:
|
|
* @param Obj: pointer to module handle
|
|
* @param mac: pointer to the MAC address array.
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_GetMACAddress(ES_WIFIObject_t *Obj, uint8_t *mac)
|
|
{
|
|
800af6c: b580 push {r7, lr}
|
|
800af6e: b084 sub sp, #16
|
|
800af70: af00 add r7, sp, #0
|
|
800af72: 6078 str r0, [r7, #4]
|
|
800af74: 6039 str r1, [r7, #0]
|
|
ES_WIFI_Status_t ret ;
|
|
char *ptr;
|
|
LOCK_WIFI();
|
|
|
|
sprintf((char*)Obj->CmdData,"Z5\r");
|
|
800af76: 687b ldr r3, [r7, #4]
|
|
800af78: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800af7c: 4912 ldr r1, [pc, #72] @ (800afc8 <ES_WIFI_GetMACAddress+0x5c>)
|
|
800af7e: 4618 mov r0, r3
|
|
800af80: f005 f998 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800af84: 687b ldr r3, [r7, #4]
|
|
800af86: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800af8a: 687b ldr r3, [r7, #4]
|
|
800af8c: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800af90: 461a mov r2, r3
|
|
800af92: 6878 ldr r0, [r7, #4]
|
|
800af94: f7ff fd48 bl 800aa28 <AT_ExecuteCommand>
|
|
800af98: 4603 mov r3, r0
|
|
800af9a: 73fb strb r3, [r7, #15]
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800af9c: 7bfb ldrb r3, [r7, #15]
|
|
800af9e: 2b00 cmp r3, #0
|
|
800afa0: d10c bne.n 800afbc <ES_WIFI_GetMACAddress+0x50>
|
|
{
|
|
ptr = strtok((char *)(Obj->CmdData + 2), "\r\n");
|
|
800afa2: 687b ldr r3, [r7, #4]
|
|
800afa4: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800afa8: 3302 adds r3, #2
|
|
800afaa: 4908 ldr r1, [pc, #32] @ (800afcc <ES_WIFI_GetMACAddress+0x60>)
|
|
800afac: 4618 mov r0, r3
|
|
800afae: f005 fac7 bl 8010540 <strtok>
|
|
800afb2: 60b8 str r0, [r7, #8]
|
|
ParseMAC(ptr, mac) ;
|
|
800afb4: 6839 ldr r1, [r7, #0]
|
|
800afb6: 68b8 ldr r0, [r7, #8]
|
|
800afb8: f7ff fba3 bl 800a702 <ParseMAC>
|
|
}
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800afbc: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800afbe: 4618 mov r0, r3
|
|
800afc0: 3710 adds r7, #16
|
|
800afc2: 46bd mov sp, r7
|
|
800afc4: bd80 pop {r7, pc}
|
|
800afc6: bf00 nop
|
|
800afc8: 08014360 .word 0x08014360
|
|
800afcc: 08014364 .word 0x08014364
|
|
|
|
0800afd0 <ES_WIFI_StartServerSingleConn>:
|
|
* @param Obj: pointer to module handle
|
|
* @param conn: pointer to the connection structure
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_StartServerSingleConn(ES_WIFIObject_t *Obj, ES_WIFI_Conn_t *conn)
|
|
{
|
|
800afd0: b580 push {r7, lr}
|
|
800afd2: b084 sub sp, #16
|
|
800afd4: af00 add r7, sp, #0
|
|
800afd6: 6078 str r0, [r7, #4]
|
|
800afd8: 6039 str r1, [r7, #0]
|
|
ES_WIFI_Status_t ret = ES_WIFI_STATUS_OK;
|
|
800afda: 2300 movs r3, #0
|
|
800afdc: 73fb strb r3, [r7, #15]
|
|
LOCK_WIFI();
|
|
|
|
sprintf((char*)Obj->CmdData,"P0=%d\r", conn->Number);
|
|
800afde: 687b ldr r3, [r7, #4]
|
|
800afe0: f503 7094 add.w r0, r3, #296 @ 0x128
|
|
800afe4: 683b ldr r3, [r7, #0]
|
|
800afe6: 785b ldrb r3, [r3, #1]
|
|
800afe8: 461a mov r2, r3
|
|
800afea: 4949 ldr r1, [pc, #292] @ (800b110 <ES_WIFI_StartServerSingleConn+0x140>)
|
|
800afec: f005 f962 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800aff0: 687b ldr r3, [r7, #4]
|
|
800aff2: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800aff6: 687b ldr r3, [r7, #4]
|
|
800aff8: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800affc: 461a mov r2, r3
|
|
800affe: 6878 ldr r0, [r7, #4]
|
|
800b000: f7ff fd12 bl 800aa28 <AT_ExecuteCommand>
|
|
800b004: 4603 mov r3, r0
|
|
800b006: 73fb strb r3, [r7, #15]
|
|
if(ret != ES_WIFI_STATUS_OK)
|
|
800b008: 7bfb ldrb r3, [r7, #15]
|
|
800b00a: 2b00 cmp r3, #0
|
|
800b00c: d001 beq.n 800b012 <ES_WIFI_StartServerSingleConn+0x42>
|
|
{
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b00e: 7bfb ldrb r3, [r7, #15]
|
|
800b010: e079 b.n 800b106 <ES_WIFI_StartServerSingleConn+0x136>
|
|
}
|
|
|
|
if ((conn->Type != ES_WIFI_UDP_CONNECTION) && (conn->Type != ES_WIFI_UDP_LITE_CONNECTION))
|
|
800b012: 683b ldr r3, [r7, #0]
|
|
800b014: 781b ldrb r3, [r3, #0]
|
|
800b016: 2b01 cmp r3, #1
|
|
800b018: d016 beq.n 800b048 <ES_WIFI_StartServerSingleConn+0x78>
|
|
800b01a: 683b ldr r3, [r7, #0]
|
|
800b01c: 781b ldrb r3, [r3, #0]
|
|
800b01e: 2b02 cmp r3, #2
|
|
800b020: d012 beq.n 800b048 <ES_WIFI_StartServerSingleConn+0x78>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"PK=1,3000\r");
|
|
800b022: 687b ldr r3, [r7, #4]
|
|
800b024: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b028: 493a ldr r1, [pc, #232] @ (800b114 <ES_WIFI_StartServerSingleConn+0x144>)
|
|
800b02a: 4618 mov r0, r3
|
|
800b02c: f005 f942 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b030: 687b ldr r3, [r7, #4]
|
|
800b032: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b036: 687b ldr r3, [r7, #4]
|
|
800b038: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b03c: 461a mov r2, r3
|
|
800b03e: 6878 ldr r0, [r7, #4]
|
|
800b040: f7ff fcf2 bl 800aa28 <AT_ExecuteCommand>
|
|
800b044: 4603 mov r3, r0
|
|
800b046: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b048: 7bfb ldrb r3, [r7, #15]
|
|
800b04a: 2b00 cmp r3, #0
|
|
800b04c: d15a bne.n 800b104 <ES_WIFI_StartServerSingleConn+0x134>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"P1=%d\r", conn->Type);
|
|
800b04e: 687b ldr r3, [r7, #4]
|
|
800b050: f503 7094 add.w r0, r3, #296 @ 0x128
|
|
800b054: 683b ldr r3, [r7, #0]
|
|
800b056: 781b ldrb r3, [r3, #0]
|
|
800b058: 461a mov r2, r3
|
|
800b05a: 492f ldr r1, [pc, #188] @ (800b118 <ES_WIFI_StartServerSingleConn+0x148>)
|
|
800b05c: f005 f92a bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b060: 687b ldr r3, [r7, #4]
|
|
800b062: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b066: 687b ldr r3, [r7, #4]
|
|
800b068: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b06c: 461a mov r2, r3
|
|
800b06e: 6878 ldr r0, [r7, #4]
|
|
800b070: f7ff fcda bl 800aa28 <AT_ExecuteCommand>
|
|
800b074: 4603 mov r3, r0
|
|
800b076: 73fb strb r3, [r7, #15]
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b078: 7bfb ldrb r3, [r7, #15]
|
|
800b07a: 2b00 cmp r3, #0
|
|
800b07c: d142 bne.n 800b104 <ES_WIFI_StartServerSingleConn+0x134>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"P8=%d\r", conn->Backlog);
|
|
800b07e: 687b ldr r3, [r7, #4]
|
|
800b080: f503 7094 add.w r0, r3, #296 @ 0x128
|
|
800b084: 683b ldr r3, [r7, #0]
|
|
800b086: 7c1b ldrb r3, [r3, #16]
|
|
800b088: 461a mov r2, r3
|
|
800b08a: 4924 ldr r1, [pc, #144] @ (800b11c <ES_WIFI_StartServerSingleConn+0x14c>)
|
|
800b08c: f005 f912 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b090: 687b ldr r3, [r7, #4]
|
|
800b092: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b096: 687b ldr r3, [r7, #4]
|
|
800b098: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b09c: 461a mov r2, r3
|
|
800b09e: 6878 ldr r0, [r7, #4]
|
|
800b0a0: f7ff fcc2 bl 800aa28 <AT_ExecuteCommand>
|
|
800b0a4: 4603 mov r3, r0
|
|
800b0a6: 73fb strb r3, [r7, #15]
|
|
if (ret == ES_WIFI_STATUS_OK)
|
|
800b0a8: 7bfb ldrb r3, [r7, #15]
|
|
800b0aa: 2b00 cmp r3, #0
|
|
800b0ac: d12a bne.n 800b104 <ES_WIFI_StartServerSingleConn+0x134>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"P2=%d\r", conn->LocalPort);
|
|
800b0ae: 687b ldr r3, [r7, #4]
|
|
800b0b0: f503 7094 add.w r0, r3, #296 @ 0x128
|
|
800b0b4: 683b ldr r3, [r7, #0]
|
|
800b0b6: 889b ldrh r3, [r3, #4]
|
|
800b0b8: 461a mov r2, r3
|
|
800b0ba: 4919 ldr r1, [pc, #100] @ (800b120 <ES_WIFI_StartServerSingleConn+0x150>)
|
|
800b0bc: f005 f8fa bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b0c0: 687b ldr r3, [r7, #4]
|
|
800b0c2: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b0c6: 687b ldr r3, [r7, #4]
|
|
800b0c8: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b0cc: 461a mov r2, r3
|
|
800b0ce: 6878 ldr r0, [r7, #4]
|
|
800b0d0: f7ff fcaa bl 800aa28 <AT_ExecuteCommand>
|
|
800b0d4: 4603 mov r3, r0
|
|
800b0d6: 73fb strb r3, [r7, #15]
|
|
if (ret == ES_WIFI_STATUS_OK)
|
|
800b0d8: 7bfb ldrb r3, [r7, #15]
|
|
800b0da: 2b00 cmp r3, #0
|
|
800b0dc: d112 bne.n 800b104 <ES_WIFI_StartServerSingleConn+0x134>
|
|
{
|
|
// multi accept mode
|
|
sprintf((char*)Obj->CmdData,"P5=11\r");
|
|
800b0de: 687b ldr r3, [r7, #4]
|
|
800b0e0: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b0e4: 490f ldr r1, [pc, #60] @ (800b124 <ES_WIFI_StartServerSingleConn+0x154>)
|
|
800b0e6: 4618 mov r0, r3
|
|
800b0e8: f005 f8e4 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b0ec: 687b ldr r3, [r7, #4]
|
|
800b0ee: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b0f2: 687b ldr r3, [r7, #4]
|
|
800b0f4: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b0f8: 461a mov r2, r3
|
|
800b0fa: 6878 ldr r0, [r7, #4]
|
|
800b0fc: f7ff fc94 bl 800aa28 <AT_ExecuteCommand>
|
|
800b100: 4603 mov r3, r0
|
|
800b102: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b104: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800b106: 4618 mov r0, r3
|
|
800b108: 3710 adds r7, #16
|
|
800b10a: 46bd mov sp, r7
|
|
800b10c: bd80 pop {r7, pc}
|
|
800b10e: bf00 nop
|
|
800b110: 080143c8 .word 0x080143c8
|
|
800b114: 08014410 .word 0x08014410
|
|
800b118: 080143d0 .word 0x080143d0
|
|
800b11c: 0801441c .word 0x0801441c
|
|
800b120: 080143d8 .word 0x080143d8
|
|
800b124: 08014424 .word 0x08014424
|
|
|
|
0800b128 <ES_WIFI_WaitServerConnection>:
|
|
* @param Obj: pointer to module handle
|
|
* @param conn: pointer to the connection structure
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_WaitServerConnection(ES_WIFIObject_t *Obj,uint32_t timeout,ES_WIFI_Conn_t *conn)
|
|
{
|
|
800b128: b580 push {r7, lr}
|
|
800b12a: b08a sub sp, #40 @ 0x28
|
|
800b12c: af00 add r7, sp, #0
|
|
800b12e: 60f8 str r0, [r7, #12]
|
|
800b130: 60b9 str r1, [r7, #8]
|
|
800b132: 607a str r2, [r7, #4]
|
|
ES_WIFI_Status_t ret = ES_WIFI_STATUS_OK;
|
|
800b134: 2300 movs r3, #0
|
|
800b136: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
uint32_t t;
|
|
uint32_t tlast;
|
|
uint32_t tstart;
|
|
char *ptr;
|
|
|
|
tstart=HAL_GetTick();
|
|
800b13a: f7f8 fde1 bl 8003d00 <HAL_GetTick>
|
|
800b13e: 6278 str r0, [r7, #36] @ 0x24
|
|
tlast=tstart+timeout;
|
|
800b140: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800b142: 68bb ldr r3, [r7, #8]
|
|
800b144: 4413 add r3, r2
|
|
800b146: 61fb str r3, [r7, #28]
|
|
if (tlast < tstart )
|
|
800b148: 69fa ldr r2, [r7, #28]
|
|
800b14a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b14c: 429a cmp r2, r3
|
|
800b14e: d201 bcs.n 800b154 <ES_WIFI_WaitServerConnection+0x2c>
|
|
{
|
|
tstart=0;
|
|
800b150: 2300 movs r3, #0
|
|
800b152: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
do
|
|
{
|
|
#if (ES_WIFI_USE_UART == 0)
|
|
// mandatory to flush MR async messages
|
|
memset(Obj->CmdData,0,sizeof(Obj->CmdData));
|
|
800b154: 68fb ldr r3, [r7, #12]
|
|
800b156: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b15a: f44f 62fa mov.w r2, #2000 @ 0x7d0
|
|
800b15e: 2100 movs r1, #0
|
|
800b160: 4618 mov r0, r3
|
|
800b162: f005 f9b1 bl 80104c8 <memset>
|
|
sprintf((char*)Obj->CmdData,"MR\r");
|
|
800b166: 68fb ldr r3, [r7, #12]
|
|
800b168: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b16c: 4972 ldr r1, [pc, #456] @ (800b338 <ES_WIFI_WaitServerConnection+0x210>)
|
|
800b16e: 4618 mov r0, r3
|
|
800b170: f005 f8a0 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b174: 68fb ldr r3, [r7, #12]
|
|
800b176: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b17a: 68fb ldr r3, [r7, #12]
|
|
800b17c: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b180: 461a mov r2, r3
|
|
800b182: 68f8 ldr r0, [r7, #12]
|
|
800b184: f7ff fc50 bl 800aa28 <AT_ExecuteCommand>
|
|
800b188: 4603 mov r3, r0
|
|
800b18a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b18e: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
800b192: 2b00 cmp r3, #0
|
|
800b194: d136 bne.n 800b204 <ES_WIFI_WaitServerConnection+0xdc>
|
|
{
|
|
if((strstr((char *)Obj->CmdData, "[SOMA]")) && (strstr((char *)Obj->CmdData, "[EOMA]")))
|
|
800b196: 68fb ldr r3, [r7, #12]
|
|
800b198: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b19c: 4967 ldr r1, [pc, #412] @ (800b33c <ES_WIFI_WaitServerConnection+0x214>)
|
|
800b19e: 4618 mov r0, r3
|
|
800b1a0: f005 fa2a bl 80105f8 <strstr>
|
|
800b1a4: 4603 mov r3, r0
|
|
800b1a6: 2b00 cmp r3, #0
|
|
800b1a8: d03b beq.n 800b222 <ES_WIFI_WaitServerConnection+0xfa>
|
|
800b1aa: 68fb ldr r3, [r7, #12]
|
|
800b1ac: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b1b0: 4963 ldr r1, [pc, #396] @ (800b340 <ES_WIFI_WaitServerConnection+0x218>)
|
|
800b1b2: 4618 mov r0, r3
|
|
800b1b4: f005 fa20 bl 80105f8 <strstr>
|
|
800b1b8: 4603 mov r3, r0
|
|
800b1ba: 2b00 cmp r3, #0
|
|
800b1bc: d031 beq.n 800b222 <ES_WIFI_WaitServerConnection+0xfa>
|
|
{
|
|
if(strstr((char *)Obj->CmdData, "Accepted"))
|
|
800b1be: 68fb ldr r3, [r7, #12]
|
|
800b1c0: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b1c4: 495f ldr r1, [pc, #380] @ (800b344 <ES_WIFI_WaitServerConnection+0x21c>)
|
|
800b1c6: 4618 mov r0, r3
|
|
800b1c8: f005 fa16 bl 80105f8 <strstr>
|
|
800b1cc: 4603 mov r3, r0
|
|
800b1ce: 2b00 cmp r3, #0
|
|
800b1d0: d127 bne.n 800b222 <ES_WIFI_WaitServerConnection+0xfa>
|
|
{
|
|
//printf("SOMA Accepted\n");
|
|
}
|
|
else if(!strstr((char *)Obj->CmdData,"[SOMA][EOMA]"))
|
|
800b1d2: 68fb ldr r3, [r7, #12]
|
|
800b1d4: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b1d8: 495b ldr r1, [pc, #364] @ (800b348 <ES_WIFI_WaitServerConnection+0x220>)
|
|
800b1da: 4618 mov r0, r3
|
|
800b1dc: f005 fa0c bl 80105f8 <strstr>
|
|
800b1e0: 4603 mov r3, r0
|
|
800b1e2: 2b00 cmp r3, #0
|
|
800b1e4: d11d bne.n 800b222 <ES_WIFI_WaitServerConnection+0xfa>
|
|
{
|
|
DEBUG("Bad MR stntax msg %s\n", Obj->CmdData);
|
|
800b1e6: f240 7241 movw r2, #1857 @ 0x741
|
|
800b1ea: 4958 ldr r1, [pc, #352] @ (800b34c <ES_WIFI_WaitServerConnection+0x224>)
|
|
800b1ec: 4858 ldr r0, [pc, #352] @ (800b350 <ES_WIFI_WaitServerConnection+0x228>)
|
|
800b1ee: f004 fff1 bl 80101d4 <iprintf>
|
|
800b1f2: 68fb ldr r3, [r7, #12]
|
|
800b1f4: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b1f8: 4619 mov r1, r3
|
|
800b1fa: 4856 ldr r0, [pc, #344] @ (800b354 <ES_WIFI_WaitServerConnection+0x22c>)
|
|
800b1fc: f004 ffea bl 80101d4 <iprintf>
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_ERROR;
|
|
800b200: 2302 movs r3, #2
|
|
800b202: e095 b.n 800b330 <ES_WIFI_WaitServerConnection+0x208>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DEBUG("MR command failed %s\n", Obj->CmdData);
|
|
800b204: f240 7249 movw r2, #1865 @ 0x749
|
|
800b208: 4950 ldr r1, [pc, #320] @ (800b34c <ES_WIFI_WaitServerConnection+0x224>)
|
|
800b20a: 4851 ldr r0, [pc, #324] @ (800b350 <ES_WIFI_WaitServerConnection+0x228>)
|
|
800b20c: f004 ffe2 bl 80101d4 <iprintf>
|
|
800b210: 68fb ldr r3, [r7, #12]
|
|
800b212: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b216: 4619 mov r1, r3
|
|
800b218: 484f ldr r0, [pc, #316] @ (800b358 <ES_WIFI_WaitServerConnection+0x230>)
|
|
800b21a: f004 ffdb bl 80101d4 <iprintf>
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_ERROR;
|
|
800b21e: 2302 movs r3, #2
|
|
800b220: e086 b.n 800b330 <ES_WIFI_WaitServerConnection+0x208>
|
|
}
|
|
#endif
|
|
|
|
memset(Obj->CmdData,0,sizeof(Obj->CmdData));
|
|
800b222: 68fb ldr r3, [r7, #12]
|
|
800b224: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b228: f44f 62fa mov.w r2, #2000 @ 0x7d0
|
|
800b22c: 2100 movs r1, #0
|
|
800b22e: 4618 mov r0, r3
|
|
800b230: f005 f94a bl 80104c8 <memset>
|
|
sprintf((char*)Obj->CmdData,"P?\r");
|
|
800b234: 68fb ldr r3, [r7, #12]
|
|
800b236: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b23a: 4948 ldr r1, [pc, #288] @ (800b35c <ES_WIFI_WaitServerConnection+0x234>)
|
|
800b23c: 4618 mov r0, r3
|
|
800b23e: f005 f839 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b242: 68fb ldr r3, [r7, #12]
|
|
800b244: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b248: 68fb ldr r3, [r7, #12]
|
|
800b24a: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b24e: 461a mov r2, r3
|
|
800b250: 68f8 ldr r0, [r7, #12]
|
|
800b252: f7ff fbe9 bl 800aa28 <AT_ExecuteCommand>
|
|
800b256: 4603 mov r3, r0
|
|
800b258: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b25c: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
800b260: 2b00 cmp r3, #0
|
|
800b262: d13f bne.n 800b2e4 <ES_WIFI_WaitServerConnection+0x1bc>
|
|
{
|
|
if (strncmp((char *)Obj->CmdData, "\r\n0,0.0.0.0,",12)!=0)
|
|
800b264: 68fb ldr r3, [r7, #12]
|
|
800b266: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b26a: 220c movs r2, #12
|
|
800b26c: 493c ldr r1, [pc, #240] @ (800b360 <ES_WIFI_WaitServerConnection+0x238>)
|
|
800b26e: 4618 mov r0, r3
|
|
800b270: f005 f941 bl 80104f6 <strncmp>
|
|
800b274: 4603 mov r3, r0
|
|
800b276: 2b00 cmp r3, #0
|
|
800b278: d043 beq.n 800b302 <ES_WIFI_WaitServerConnection+0x1da>
|
|
{
|
|
ptr = strtok((char *)Obj->CmdData + 2, ",");
|
|
800b27a: 68fb ldr r3, [r7, #12]
|
|
800b27c: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b280: 3302 adds r3, #2
|
|
800b282: 4938 ldr r1, [pc, #224] @ (800b364 <ES_WIFI_WaitServerConnection+0x23c>)
|
|
800b284: 4618 mov r0, r3
|
|
800b286: f005 f95b bl 8010540 <strtok>
|
|
800b28a: 6178 str r0, [r7, #20]
|
|
ptr = strtok(0, ","); //port
|
|
800b28c: 4935 ldr r1, [pc, #212] @ (800b364 <ES_WIFI_WaitServerConnection+0x23c>)
|
|
800b28e: 2000 movs r0, #0
|
|
800b290: f005 f956 bl 8010540 <strtok>
|
|
800b294: 6178 str r0, [r7, #20]
|
|
ParseIP((char *)ptr, conn->RemoteIP);
|
|
800b296: 687b ldr r3, [r7, #4]
|
|
800b298: 3306 adds r3, #6
|
|
800b29a: 4619 mov r1, r3
|
|
800b29c: 6978 ldr r0, [r7, #20]
|
|
800b29e: f7ff fa5b bl 800a758 <ParseIP>
|
|
ptr = strtok(0, ","); //port
|
|
800b2a2: 4930 ldr r1, [pc, #192] @ (800b364 <ES_WIFI_WaitServerConnection+0x23c>)
|
|
800b2a4: 2000 movs r0, #0
|
|
800b2a6: f005 f94b bl 8010540 <strtok>
|
|
800b2aa: 6178 str r0, [r7, #20]
|
|
conn->LocalPort=ParseNumber(ptr,0);
|
|
800b2ac: 2100 movs r1, #0
|
|
800b2ae: 6978 ldr r0, [r7, #20]
|
|
800b2b0: f7ff f9e3 bl 800a67a <ParseNumber>
|
|
800b2b4: 4603 mov r3, r0
|
|
800b2b6: b29a uxth r2, r3
|
|
800b2b8: 687b ldr r3, [r7, #4]
|
|
800b2ba: 809a strh r2, [r3, #4]
|
|
ptr = strtok(0, ","); //ip
|
|
800b2bc: 4929 ldr r1, [pc, #164] @ (800b364 <ES_WIFI_WaitServerConnection+0x23c>)
|
|
800b2be: 2000 movs r0, #0
|
|
800b2c0: f005 f93e bl 8010540 <strtok>
|
|
800b2c4: 6178 str r0, [r7, #20]
|
|
ptr = strtok(0, ","); //remote port
|
|
800b2c6: 4927 ldr r1, [pc, #156] @ (800b364 <ES_WIFI_WaitServerConnection+0x23c>)
|
|
800b2c8: 2000 movs r0, #0
|
|
800b2ca: f005 f939 bl 8010540 <strtok>
|
|
800b2ce: 6178 str r0, [r7, #20]
|
|
conn->RemotePort=ParseNumber(ptr,0);
|
|
800b2d0: 2100 movs r1, #0
|
|
800b2d2: 6978 ldr r0, [r7, #20]
|
|
800b2d4: f7ff f9d1 bl 800a67a <ParseNumber>
|
|
800b2d8: 4603 mov r3, r0
|
|
800b2da: b29a uxth r2, r3
|
|
800b2dc: 687b ldr r3, [r7, #4]
|
|
800b2de: 805a strh r2, [r3, #2]
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_OK;
|
|
800b2e0: 2300 movs r3, #0
|
|
800b2e2: e025 b.n 800b330 <ES_WIFI_WaitServerConnection+0x208>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DEBUG("P? command failed %s\n", Obj->CmdData);
|
|
800b2e4: f240 7264 movw r2, #1892 @ 0x764
|
|
800b2e8: 4918 ldr r1, [pc, #96] @ (800b34c <ES_WIFI_WaitServerConnection+0x224>)
|
|
800b2ea: 4819 ldr r0, [pc, #100] @ (800b350 <ES_WIFI_WaitServerConnection+0x228>)
|
|
800b2ec: f004 ff72 bl 80101d4 <iprintf>
|
|
800b2f0: 68fb ldr r3, [r7, #12]
|
|
800b2f2: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b2f6: 4619 mov r1, r3
|
|
800b2f8: 481b ldr r0, [pc, #108] @ (800b368 <ES_WIFI_WaitServerConnection+0x240>)
|
|
800b2fa: f004 ff6b bl 80101d4 <iprintf>
|
|
UNLOCK_WIFI();
|
|
return ES_WIFI_STATUS_ERROR;
|
|
800b2fe: 2302 movs r3, #2
|
|
800b300: e016 b.n 800b330 <ES_WIFI_WaitServerConnection+0x208>
|
|
}
|
|
|
|
UNLOCK_WIFI();
|
|
Obj->fops.IO_Delay(100);
|
|
800b302: 68fb ldr r3, [r7, #12]
|
|
800b304: f8d3 311c ldr.w r3, [r3, #284] @ 0x11c
|
|
800b308: 2064 movs r0, #100 @ 0x64
|
|
800b30a: 4798 blx r3
|
|
LOCK_WIFI();
|
|
t = HAL_GetTick();
|
|
800b30c: f7f8 fcf8 bl 8003d00 <HAL_GetTick>
|
|
800b310: 61b8 str r0, [r7, #24]
|
|
}
|
|
while ((timeout==0) ||((t < tlast) || (t < tstart)));
|
|
800b312: 68bb ldr r3, [r7, #8]
|
|
800b314: 2b00 cmp r3, #0
|
|
800b316: f43f af1d beq.w 800b154 <ES_WIFI_WaitServerConnection+0x2c>
|
|
800b31a: 69ba ldr r2, [r7, #24]
|
|
800b31c: 69fb ldr r3, [r7, #28]
|
|
800b31e: 429a cmp r2, r3
|
|
800b320: f4ff af18 bcc.w 800b154 <ES_WIFI_WaitServerConnection+0x2c>
|
|
800b324: 69ba ldr r2, [r7, #24]
|
|
800b326: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b328: 429a cmp r2, r3
|
|
800b32a: f4ff af13 bcc.w 800b154 <ES_WIFI_WaitServerConnection+0x2c>
|
|
return ES_WIFI_STATUS_TIMEOUT;
|
|
800b32e: 2303 movs r3, #3
|
|
}
|
|
800b330: 4618 mov r0, r3
|
|
800b332: 3728 adds r7, #40 @ 0x28
|
|
800b334: 46bd mov sp, r7
|
|
800b336: bd80 pop {r7, pc}
|
|
800b338: 080142d8 .word 0x080142d8
|
|
800b33c: 0801442c .word 0x0801442c
|
|
800b340: 08014434 .word 0x08014434
|
|
800b344: 0801443c .word 0x0801443c
|
|
800b348: 08014448 .word 0x08014448
|
|
800b34c: 08014458 .word 0x08014458
|
|
800b350: 08014474 .word 0x08014474
|
|
800b354: 0801447c .word 0x0801447c
|
|
800b358: 08014494 .word 0x08014494
|
|
800b35c: 080144ac .word 0x080144ac
|
|
800b360: 080144b0 .word 0x080144b0
|
|
800b364: 08014298 .word 0x08014298
|
|
800b368: 080144c0 .word 0x080144c0
|
|
|
|
0800b36c <ES_WIFI_CloseServerConnection>:
|
|
* @param Obj: pointer to module handle
|
|
* @param socket: server socket
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_CloseServerConnection(ES_WIFIObject_t *Obj, int socket)
|
|
{
|
|
800b36c: b580 push {r7, lr}
|
|
800b36e: b084 sub sp, #16
|
|
800b370: af00 add r7, sp, #0
|
|
800b372: 6078 str r0, [r7, #4]
|
|
800b374: 6039 str r1, [r7, #0]
|
|
ES_WIFI_Status_t ret;
|
|
LOCK_WIFI();
|
|
sprintf((char*)Obj->CmdData,"P0=%d\r", socket);
|
|
800b376: 687b ldr r3, [r7, #4]
|
|
800b378: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b37c: 683a ldr r2, [r7, #0]
|
|
800b37e: 4925 ldr r1, [pc, #148] @ (800b414 <ES_WIFI_CloseServerConnection+0xa8>)
|
|
800b380: 4618 mov r0, r3
|
|
800b382: f004 ff97 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b386: 687b ldr r3, [r7, #4]
|
|
800b388: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b38c: 687b ldr r3, [r7, #4]
|
|
800b38e: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b392: 461a mov r2, r3
|
|
800b394: 6878 ldr r0, [r7, #4]
|
|
800b396: f7ff fb47 bl 800aa28 <AT_ExecuteCommand>
|
|
800b39a: 4603 mov r3, r0
|
|
800b39c: 73fb strb r3, [r7, #15]
|
|
if(ret != ES_WIFI_STATUS_OK)
|
|
800b39e: 7bfb ldrb r3, [r7, #15]
|
|
800b3a0: 2b00 cmp r3, #0
|
|
800b3a2: d00e beq.n 800b3c2 <ES_WIFI_CloseServerConnection+0x56>
|
|
{
|
|
DEBUG(" Can not select socket %s\n", Obj->CmdData);
|
|
800b3a4: f44f 62f0 mov.w r2, #1920 @ 0x780
|
|
800b3a8: 491b ldr r1, [pc, #108] @ (800b418 <ES_WIFI_CloseServerConnection+0xac>)
|
|
800b3aa: 481c ldr r0, [pc, #112] @ (800b41c <ES_WIFI_CloseServerConnection+0xb0>)
|
|
800b3ac: f004 ff12 bl 80101d4 <iprintf>
|
|
800b3b0: 687b ldr r3, [r7, #4]
|
|
800b3b2: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b3b6: 4619 mov r1, r3
|
|
800b3b8: 4819 ldr r0, [pc, #100] @ (800b420 <ES_WIFI_CloseServerConnection+0xb4>)
|
|
800b3ba: f004 ff0b bl 80101d4 <iprintf>
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b3be: 7bfb ldrb r3, [r7, #15]
|
|
800b3c0: e023 b.n 800b40a <ES_WIFI_CloseServerConnection+0x9e>
|
|
}
|
|
|
|
sprintf((char*)Obj->CmdData,"P5=10\r");
|
|
800b3c2: 687b ldr r3, [r7, #4]
|
|
800b3c4: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b3c8: 4916 ldr r1, [pc, #88] @ (800b424 <ES_WIFI_CloseServerConnection+0xb8>)
|
|
800b3ca: 4618 mov r0, r3
|
|
800b3cc: f004 ff72 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b3d0: 687b ldr r3, [r7, #4]
|
|
800b3d2: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b3d6: 687b ldr r3, [r7, #4]
|
|
800b3d8: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b3dc: 461a mov r2, r3
|
|
800b3de: 6878 ldr r0, [r7, #4]
|
|
800b3e0: f7ff fb22 bl 800aa28 <AT_ExecuteCommand>
|
|
800b3e4: 4603 mov r3, r0
|
|
800b3e6: 73fb strb r3, [r7, #15]
|
|
if(ret != ES_WIFI_STATUS_OK)
|
|
800b3e8: 7bfb ldrb r3, [r7, #15]
|
|
800b3ea: 2b00 cmp r3, #0
|
|
800b3ec: d00c beq.n 800b408 <ES_WIFI_CloseServerConnection+0x9c>
|
|
{
|
|
DEBUG(" Open next failed %s\n", Obj->CmdData);
|
|
800b3ee: f240 7289 movw r2, #1929 @ 0x789
|
|
800b3f2: 4909 ldr r1, [pc, #36] @ (800b418 <ES_WIFI_CloseServerConnection+0xac>)
|
|
800b3f4: 4809 ldr r0, [pc, #36] @ (800b41c <ES_WIFI_CloseServerConnection+0xb0>)
|
|
800b3f6: f004 feed bl 80101d4 <iprintf>
|
|
800b3fa: 687b ldr r3, [r7, #4]
|
|
800b3fc: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b400: 4619 mov r1, r3
|
|
800b402: 4809 ldr r0, [pc, #36] @ (800b428 <ES_WIFI_CloseServerConnection+0xbc>)
|
|
800b404: f004 fee6 bl 80101d4 <iprintf>
|
|
}
|
|
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b408: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800b40a: 4618 mov r0, r3
|
|
800b40c: 3710 adds r7, #16
|
|
800b40e: 46bd mov sp, r7
|
|
800b410: bd80 pop {r7, pc}
|
|
800b412: bf00 nop
|
|
800b414: 080143c8 .word 0x080143c8
|
|
800b418: 08014458 .word 0x08014458
|
|
800b41c: 08014474 .word 0x08014474
|
|
800b420: 080144d8 .word 0x080144d8
|
|
800b424: 080144f4 .word 0x080144f4
|
|
800b428: 080144fc .word 0x080144fc
|
|
|
|
0800b42c <ES_WIFI_StopServerSingleConn>:
|
|
* @brief Stop a Server.
|
|
* @param Obj: pointer to module handle
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_StopServerSingleConn(ES_WIFIObject_t *Obj, int socket)
|
|
{
|
|
800b42c: b580 push {r7, lr}
|
|
800b42e: b084 sub sp, #16
|
|
800b430: af00 add r7, sp, #0
|
|
800b432: 6078 str r0, [r7, #4]
|
|
800b434: 6039 str r1, [r7, #0]
|
|
ES_WIFI_Status_t ret;
|
|
LOCK_WIFI();
|
|
sprintf((char*)Obj->CmdData,"P0=%d\r", socket);
|
|
800b436: 687b ldr r3, [r7, #4]
|
|
800b438: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b43c: 683a ldr r2, [r7, #0]
|
|
800b43e: 4926 ldr r1, [pc, #152] @ (800b4d8 <ES_WIFI_StopServerSingleConn+0xac>)
|
|
800b440: 4618 mov r0, r3
|
|
800b442: f004 ff37 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b446: 687b ldr r3, [r7, #4]
|
|
800b448: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b44c: 687b ldr r3, [r7, #4]
|
|
800b44e: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b452: 461a mov r2, r3
|
|
800b454: 6878 ldr r0, [r7, #4]
|
|
800b456: f7ff fae7 bl 800aa28 <AT_ExecuteCommand>
|
|
800b45a: 4603 mov r3, r0
|
|
800b45c: 73fb strb r3, [r7, #15]
|
|
if(ret != ES_WIFI_STATUS_OK)
|
|
800b45e: 7bfb ldrb r3, [r7, #15]
|
|
800b460: 2b00 cmp r3, #0
|
|
800b462: d00e beq.n 800b482 <ES_WIFI_StopServerSingleConn+0x56>
|
|
{
|
|
DEBUG("Selecting socket failed: %s\n", Obj->CmdData);
|
|
800b464: f240 729f movw r2, #1951 @ 0x79f
|
|
800b468: 491c ldr r1, [pc, #112] @ (800b4dc <ES_WIFI_StopServerSingleConn+0xb0>)
|
|
800b46a: 481d ldr r0, [pc, #116] @ (800b4e0 <ES_WIFI_StopServerSingleConn+0xb4>)
|
|
800b46c: f004 feb2 bl 80101d4 <iprintf>
|
|
800b470: 687b ldr r3, [r7, #4]
|
|
800b472: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b476: 4619 mov r1, r3
|
|
800b478: 481a ldr r0, [pc, #104] @ (800b4e4 <ES_WIFI_StopServerSingleConn+0xb8>)
|
|
800b47a: f004 feab bl 80101d4 <iprintf>
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b47e: 7bfb ldrb r3, [r7, #15]
|
|
800b480: e025 b.n 800b4ce <ES_WIFI_StopServerSingleConn+0xa2>
|
|
}
|
|
|
|
sprintf((char*)Obj->CmdData,"P5=0\r");
|
|
800b482: 687b ldr r3, [r7, #4]
|
|
800b484: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b488: 4917 ldr r1, [pc, #92] @ (800b4e8 <ES_WIFI_StopServerSingleConn+0xbc>)
|
|
800b48a: 4618 mov r0, r3
|
|
800b48c: f004 ff12 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b490: 687b ldr r3, [r7, #4]
|
|
800b492: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b496: 687b ldr r3, [r7, #4]
|
|
800b498: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b49c: 461a mov r2, r3
|
|
800b49e: 6878 ldr r0, [r7, #4]
|
|
800b4a0: f7ff fac2 bl 800aa28 <AT_ExecuteCommand>
|
|
800b4a4: 4603 mov r3, r0
|
|
800b4a6: 73fb strb r3, [r7, #15]
|
|
if(ret != ES_WIFI_STATUS_OK)
|
|
800b4a8: 7bfb ldrb r3, [r7, #15]
|
|
800b4aa: 2b00 cmp r3, #0
|
|
800b4ac: d00e beq.n 800b4cc <ES_WIFI_StopServerSingleConn+0xa0>
|
|
{
|
|
DEBUG("Stopping server failed %s\n", Obj->CmdData);
|
|
800b4ae: f44f 62f5 mov.w r2, #1960 @ 0x7a8
|
|
800b4b2: 490a ldr r1, [pc, #40] @ (800b4dc <ES_WIFI_StopServerSingleConn+0xb0>)
|
|
800b4b4: 480a ldr r0, [pc, #40] @ (800b4e0 <ES_WIFI_StopServerSingleConn+0xb4>)
|
|
800b4b6: f004 fe8d bl 80101d4 <iprintf>
|
|
800b4ba: 687b ldr r3, [r7, #4]
|
|
800b4bc: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b4c0: 4619 mov r1, r3
|
|
800b4c2: 480a ldr r0, [pc, #40] @ (800b4ec <ES_WIFI_StopServerSingleConn+0xc0>)
|
|
800b4c4: f004 fe86 bl 80101d4 <iprintf>
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b4c8: 7bfb ldrb r3, [r7, #15]
|
|
800b4ca: e000 b.n 800b4ce <ES_WIFI_StopServerSingleConn+0xa2>
|
|
}
|
|
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b4cc: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800b4ce: 4618 mov r0, r3
|
|
800b4d0: 3710 adds r7, #16
|
|
800b4d2: 46bd mov sp, r7
|
|
800b4d4: bd80 pop {r7, pc}
|
|
800b4d6: bf00 nop
|
|
800b4d8: 080143c8 .word 0x080143c8
|
|
800b4dc: 08014458 .word 0x08014458
|
|
800b4e0: 08014474 .word 0x08014474
|
|
800b4e4: 08014514 .word 0x08014514
|
|
800b4e8: 08014534 .word 0x08014534
|
|
800b4ec: 0801453c .word 0x0801453c
|
|
|
|
0800b4f0 <ES_WIFI_SendData>:
|
|
* @param pdata: pointer to data
|
|
* @param len : length of the data to be sent
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_SendData(ES_WIFIObject_t *Obj, uint8_t Socket, uint8_t *pdata, uint16_t Reqlen , uint16_t *SentLen , uint32_t Timeout)
|
|
{
|
|
800b4f0: b580 push {r7, lr}
|
|
800b4f2: b088 sub sp, #32
|
|
800b4f4: af02 add r7, sp, #8
|
|
800b4f6: 60f8 str r0, [r7, #12]
|
|
800b4f8: 607a str r2, [r7, #4]
|
|
800b4fa: 461a mov r2, r3
|
|
800b4fc: 460b mov r3, r1
|
|
800b4fe: 72fb strb r3, [r7, #11]
|
|
800b500: 4613 mov r3, r2
|
|
800b502: 813b strh r3, [r7, #8]
|
|
uint32_t wkgTimeOut;
|
|
|
|
ES_WIFI_Status_t ret = ES_WIFI_STATUS_ERROR;
|
|
800b504: 2302 movs r3, #2
|
|
800b506: 74fb strb r3, [r7, #19]
|
|
|
|
if (Timeout == 0)
|
|
800b508: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b50a: 2b00 cmp r3, #0
|
|
800b50c: d102 bne.n 800b514 <ES_WIFI_SendData+0x24>
|
|
{
|
|
wkgTimeOut = NET_DEFAULT_NOBLOCKING_WRITE_TIMEOUT;
|
|
800b50e: 2301 movs r3, #1
|
|
800b510: 617b str r3, [r7, #20]
|
|
800b512: e001 b.n 800b518 <ES_WIFI_SendData+0x28>
|
|
}
|
|
else
|
|
{
|
|
wkgTimeOut = Timeout;
|
|
800b514: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b516: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
LOCK_WIFI();
|
|
if(Reqlen >= ES_WIFI_PAYLOAD_SIZE ) Reqlen= ES_WIFI_PAYLOAD_SIZE;
|
|
800b518: 893b ldrh r3, [r7, #8]
|
|
800b51a: f5b3 6f96 cmp.w r3, #1200 @ 0x4b0
|
|
800b51e: d302 bcc.n 800b526 <ES_WIFI_SendData+0x36>
|
|
800b520: f44f 6396 mov.w r3, #1200 @ 0x4b0
|
|
800b524: 813b strh r3, [r7, #8]
|
|
|
|
*SentLen = Reqlen;
|
|
800b526: 6a3b ldr r3, [r7, #32]
|
|
800b528: 893a ldrh r2, [r7, #8]
|
|
800b52a: 801a strh r2, [r3, #0]
|
|
sprintf((char*)Obj->CmdData,"P0=%d\r", Socket);
|
|
800b52c: 68fb ldr r3, [r7, #12]
|
|
800b52e: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b532: 7afa ldrb r2, [r7, #11]
|
|
800b534: 4942 ldr r1, [pc, #264] @ (800b640 <ES_WIFI_SendData+0x150>)
|
|
800b536: 4618 mov r0, r3
|
|
800b538: f004 febc bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b53c: 68fb ldr r3, [r7, #12]
|
|
800b53e: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b542: 68fb ldr r3, [r7, #12]
|
|
800b544: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b548: 461a mov r2, r3
|
|
800b54a: 68f8 ldr r0, [r7, #12]
|
|
800b54c: f7ff fa6c bl 800aa28 <AT_ExecuteCommand>
|
|
800b550: 4603 mov r3, r0
|
|
800b552: 74fb strb r3, [r7, #19]
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b554: 7cfb ldrb r3, [r7, #19]
|
|
800b556: 2b00 cmp r3, #0
|
|
800b558: d15e bne.n 800b618 <ES_WIFI_SendData+0x128>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"S2=%lu\r",wkgTimeOut);
|
|
800b55a: 68fb ldr r3, [r7, #12]
|
|
800b55c: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b560: 697a ldr r2, [r7, #20]
|
|
800b562: 4938 ldr r1, [pc, #224] @ (800b644 <ES_WIFI_SendData+0x154>)
|
|
800b564: 4618 mov r0, r3
|
|
800b566: f004 fea5 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b56a: 68fb ldr r3, [r7, #12]
|
|
800b56c: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b570: 68fb ldr r3, [r7, #12]
|
|
800b572: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b576: 461a mov r2, r3
|
|
800b578: 68f8 ldr r0, [r7, #12]
|
|
800b57a: f7ff fa55 bl 800aa28 <AT_ExecuteCommand>
|
|
800b57e: 4603 mov r3, r0
|
|
800b580: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b582: 7cfb ldrb r3, [r7, #19]
|
|
800b584: 2b00 cmp r3, #0
|
|
800b586: d13d bne.n 800b604 <ES_WIFI_SendData+0x114>
|
|
{
|
|
sprintf((char *)Obj->CmdData,"S3=%04d\r",Reqlen);
|
|
800b588: 68fb ldr r3, [r7, #12]
|
|
800b58a: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b58e: 893a ldrh r2, [r7, #8]
|
|
800b590: 492d ldr r1, [pc, #180] @ (800b648 <ES_WIFI_SendData+0x158>)
|
|
800b592: 4618 mov r0, r3
|
|
800b594: f004 fe8e bl 80102b4 <siprintf>
|
|
ret = AT_RequestSendData(Obj, Obj->CmdData, pdata, Reqlen, Obj->CmdData);
|
|
800b598: 68fb ldr r3, [r7, #12]
|
|
800b59a: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b59e: 68fb ldr r3, [r7, #12]
|
|
800b5a0: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b5a4: 893a ldrh r2, [r7, #8]
|
|
800b5a6: 9300 str r3, [sp, #0]
|
|
800b5a8: 4613 mov r3, r2
|
|
800b5aa: 687a ldr r2, [r7, #4]
|
|
800b5ac: 68f8 ldr r0, [r7, #12]
|
|
800b5ae: f7ff faa1 bl 800aaf4 <AT_RequestSendData>
|
|
800b5b2: 4603 mov r3, r0
|
|
800b5b4: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b5b6: 7cfb ldrb r3, [r7, #19]
|
|
800b5b8: 2b00 cmp r3, #0
|
|
800b5ba: d119 bne.n 800b5f0 <ES_WIFI_SendData+0x100>
|
|
{
|
|
if(strstr((char *)Obj->CmdData,"-1\r\n"))
|
|
800b5bc: 68fb ldr r3, [r7, #12]
|
|
800b5be: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b5c2: 4922 ldr r1, [pc, #136] @ (800b64c <ES_WIFI_SendData+0x15c>)
|
|
800b5c4: 4618 mov r0, r3
|
|
800b5c6: f005 f817 bl 80105f8 <strstr>
|
|
800b5ca: 4603 mov r3, r0
|
|
800b5cc: 2b00 cmp r3, #0
|
|
800b5ce: d02c beq.n 800b62a <ES_WIFI_SendData+0x13a>
|
|
{
|
|
DEBUG("Send Data detect error %s\n", (char *)Obj->CmdData);
|
|
800b5d0: f640 025c movw r2, #2140 @ 0x85c
|
|
800b5d4: 491e ldr r1, [pc, #120] @ (800b650 <ES_WIFI_SendData+0x160>)
|
|
800b5d6: 481f ldr r0, [pc, #124] @ (800b654 <ES_WIFI_SendData+0x164>)
|
|
800b5d8: f004 fdfc bl 80101d4 <iprintf>
|
|
800b5dc: 68fb ldr r3, [r7, #12]
|
|
800b5de: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b5e2: 4619 mov r1, r3
|
|
800b5e4: 481c ldr r0, [pc, #112] @ (800b658 <ES_WIFI_SendData+0x168>)
|
|
800b5e6: f004 fdf5 bl 80101d4 <iprintf>
|
|
ret = ES_WIFI_STATUS_ERROR;
|
|
800b5ea: 2302 movs r3, #2
|
|
800b5ec: 74fb strb r3, [r7, #19]
|
|
800b5ee: e01c b.n 800b62a <ES_WIFI_SendData+0x13a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DEBUG("Send Data command failed\n");
|
|
800b5f0: f640 0262 movw r2, #2146 @ 0x862
|
|
800b5f4: 4916 ldr r1, [pc, #88] @ (800b650 <ES_WIFI_SendData+0x160>)
|
|
800b5f6: 4817 ldr r0, [pc, #92] @ (800b654 <ES_WIFI_SendData+0x164>)
|
|
800b5f8: f004 fdec bl 80101d4 <iprintf>
|
|
800b5fc: 4817 ldr r0, [pc, #92] @ (800b65c <ES_WIFI_SendData+0x16c>)
|
|
800b5fe: f004 fe51 bl 80102a4 <puts>
|
|
800b602: e012 b.n 800b62a <ES_WIFI_SendData+0x13a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DEBUG("S2 command failed\n");
|
|
800b604: f640 0267 movw r2, #2151 @ 0x867
|
|
800b608: 4911 ldr r1, [pc, #68] @ (800b650 <ES_WIFI_SendData+0x160>)
|
|
800b60a: 4812 ldr r0, [pc, #72] @ (800b654 <ES_WIFI_SendData+0x164>)
|
|
800b60c: f004 fde2 bl 80101d4 <iprintf>
|
|
800b610: 4813 ldr r0, [pc, #76] @ (800b660 <ES_WIFI_SendData+0x170>)
|
|
800b612: f004 fe47 bl 80102a4 <puts>
|
|
800b616: e008 b.n 800b62a <ES_WIFI_SendData+0x13a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DEBUG("P0 command failed\n");
|
|
800b618: f640 026c movw r2, #2156 @ 0x86c
|
|
800b61c: 490c ldr r1, [pc, #48] @ (800b650 <ES_WIFI_SendData+0x160>)
|
|
800b61e: 480d ldr r0, [pc, #52] @ (800b654 <ES_WIFI_SendData+0x164>)
|
|
800b620: f004 fdd8 bl 80101d4 <iprintf>
|
|
800b624: 480f ldr r0, [pc, #60] @ (800b664 <ES_WIFI_SendData+0x174>)
|
|
800b626: f004 fe3d bl 80102a4 <puts>
|
|
}
|
|
|
|
if (ret == ES_WIFI_STATUS_ERROR)
|
|
800b62a: 7cfb ldrb r3, [r7, #19]
|
|
800b62c: 2b02 cmp r3, #2
|
|
800b62e: d102 bne.n 800b636 <ES_WIFI_SendData+0x146>
|
|
{
|
|
*SentLen = 0;
|
|
800b630: 6a3b ldr r3, [r7, #32]
|
|
800b632: 2200 movs r2, #0
|
|
800b634: 801a strh r2, [r3, #0]
|
|
}
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b636: 7cfb ldrb r3, [r7, #19]
|
|
}
|
|
800b638: 4618 mov r0, r3
|
|
800b63a: 3718 adds r7, #24
|
|
800b63c: 46bd mov sp, r7
|
|
800b63e: bd80 pop {r7, pc}
|
|
800b640: 080143c8 .word 0x080143c8
|
|
800b644: 08014580 .word 0x08014580
|
|
800b648: 08014588 .word 0x08014588
|
|
800b64c: 08014594 .word 0x08014594
|
|
800b650: 08014458 .word 0x08014458
|
|
800b654: 08014474 .word 0x08014474
|
|
800b658: 0801459c .word 0x0801459c
|
|
800b65c: 080145b8 .word 0x080145b8
|
|
800b660: 080145d4 .word 0x080145d4
|
|
800b664: 080145e8 .word 0x080145e8
|
|
|
|
0800b668 <ES_WIFI_ReceiveData>:
|
|
* @param pdata: pointer to data
|
|
* @param len : pointer to the length of the data to be received
|
|
* @retval Operation Status.
|
|
*/
|
|
ES_WIFI_Status_t ES_WIFI_ReceiveData(ES_WIFIObject_t *Obj, uint8_t Socket, uint8_t *pdata, uint16_t Reqlen, uint16_t *Receivedlen, uint32_t Timeout)
|
|
{
|
|
800b668: b580 push {r7, lr}
|
|
800b66a: b088 sub sp, #32
|
|
800b66c: af02 add r7, sp, #8
|
|
800b66e: 60f8 str r0, [r7, #12]
|
|
800b670: 607a str r2, [r7, #4]
|
|
800b672: 461a mov r2, r3
|
|
800b674: 460b mov r3, r1
|
|
800b676: 72fb strb r3, [r7, #11]
|
|
800b678: 4613 mov r3, r2
|
|
800b67a: 813b strh r3, [r7, #8]
|
|
uint32_t wkgTimeOut;
|
|
|
|
ES_WIFI_Status_t ret = ES_WIFI_STATUS_ERROR;
|
|
800b67c: 2302 movs r3, #2
|
|
800b67e: 74fb strb r3, [r7, #19]
|
|
|
|
if (Timeout == 0)
|
|
800b680: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b682: 2b00 cmp r3, #0
|
|
800b684: d102 bne.n 800b68c <ES_WIFI_ReceiveData+0x24>
|
|
{
|
|
wkgTimeOut = NET_DEFAULT_NOBLOCKING_READ_TIMEOUT;
|
|
800b686: 2301 movs r3, #1
|
|
800b688: 617b str r3, [r7, #20]
|
|
800b68a: e001 b.n 800b690 <ES_WIFI_ReceiveData+0x28>
|
|
}
|
|
else
|
|
{
|
|
wkgTimeOut = Timeout;
|
|
800b68c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b68e: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
LOCK_WIFI();
|
|
|
|
if(Reqlen <= ES_WIFI_PAYLOAD_SIZE )
|
|
800b690: 893b ldrh r3, [r7, #8]
|
|
800b692: f5b3 6f96 cmp.w r3, #1200 @ 0x4b0
|
|
800b696: f200 808b bhi.w 800b7b0 <ES_WIFI_ReceiveData+0x148>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"P0=%d\r", Socket);
|
|
800b69a: 68fb ldr r3, [r7, #12]
|
|
800b69c: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b6a0: 7afa ldrb r2, [r7, #11]
|
|
800b6a2: 4946 ldr r1, [pc, #280] @ (800b7bc <ES_WIFI_ReceiveData+0x154>)
|
|
800b6a4: 4618 mov r0, r3
|
|
800b6a6: f004 fe05 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b6aa: 68fb ldr r3, [r7, #12]
|
|
800b6ac: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b6b0: 68fb ldr r3, [r7, #12]
|
|
800b6b2: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b6b6: 461a mov r2, r3
|
|
800b6b8: 68f8 ldr r0, [r7, #12]
|
|
800b6ba: f7ff f9b5 bl 800aa28 <AT_ExecuteCommand>
|
|
800b6be: 4603 mov r3, r0
|
|
800b6c0: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b6c2: 7cfb ldrb r3, [r7, #19]
|
|
800b6c4: 2b00 cmp r3, #0
|
|
800b6c6: d165 bne.n 800b794 <ES_WIFI_ReceiveData+0x12c>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"R1=%d\r", Reqlen);
|
|
800b6c8: 68fb ldr r3, [r7, #12]
|
|
800b6ca: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b6ce: 893a ldrh r2, [r7, #8]
|
|
800b6d0: 493b ldr r1, [pc, #236] @ (800b7c0 <ES_WIFI_ReceiveData+0x158>)
|
|
800b6d2: 4618 mov r0, r3
|
|
800b6d4: f004 fdee bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b6d8: 68fb ldr r3, [r7, #12]
|
|
800b6da: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b6de: 68fb ldr r3, [r7, #12]
|
|
800b6e0: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b6e4: 461a mov r2, r3
|
|
800b6e6: 68f8 ldr r0, [r7, #12]
|
|
800b6e8: f7ff f99e bl 800aa28 <AT_ExecuteCommand>
|
|
800b6ec: 4603 mov r3, r0
|
|
800b6ee: 74fb strb r3, [r7, #19]
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b6f0: 7cfb ldrb r3, [r7, #19]
|
|
800b6f2: 2b00 cmp r3, #0
|
|
800b6f4: d141 bne.n 800b77a <ES_WIFI_ReceiveData+0x112>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"R2=%lu\r", wkgTimeOut);
|
|
800b6f6: 68fb ldr r3, [r7, #12]
|
|
800b6f8: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b6fc: 697a ldr r2, [r7, #20]
|
|
800b6fe: 4931 ldr r1, [pc, #196] @ (800b7c4 <ES_WIFI_ReceiveData+0x15c>)
|
|
800b700: 4618 mov r0, r3
|
|
800b702: f004 fdd7 bl 80102b4 <siprintf>
|
|
ret = AT_ExecuteCommand(Obj, Obj->CmdData, Obj->CmdData);
|
|
800b706: 68fb ldr r3, [r7, #12]
|
|
800b708: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b70c: 68fb ldr r3, [r7, #12]
|
|
800b70e: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b712: 461a mov r2, r3
|
|
800b714: 68f8 ldr r0, [r7, #12]
|
|
800b716: f7ff f987 bl 800aa28 <AT_ExecuteCommand>
|
|
800b71a: 4603 mov r3, r0
|
|
800b71c: 74fb strb r3, [r7, #19]
|
|
if(ret == ES_WIFI_STATUS_OK)
|
|
800b71e: 7cfb ldrb r3, [r7, #19]
|
|
800b720: 2b00 cmp r3, #0
|
|
800b722: d120 bne.n 800b766 <ES_WIFI_ReceiveData+0xfe>
|
|
{
|
|
sprintf((char*)Obj->CmdData,"R0\r");
|
|
800b724: 68fb ldr r3, [r7, #12]
|
|
800b726: f503 7394 add.w r3, r3, #296 @ 0x128
|
|
800b72a: 4927 ldr r1, [pc, #156] @ (800b7c8 <ES_WIFI_ReceiveData+0x160>)
|
|
800b72c: 4618 mov r0, r3
|
|
800b72e: f004 fdc1 bl 80102b4 <siprintf>
|
|
ret = AT_RequestReceiveData(Obj, Obj->CmdData, (char *)pdata, Reqlen, Receivedlen);
|
|
800b732: 68fb ldr r3, [r7, #12]
|
|
800b734: f503 7194 add.w r1, r3, #296 @ 0x128
|
|
800b738: 893a ldrh r2, [r7, #8]
|
|
800b73a: 6a3b ldr r3, [r7, #32]
|
|
800b73c: 9300 str r3, [sp, #0]
|
|
800b73e: 4613 mov r3, r2
|
|
800b740: 687a ldr r2, [r7, #4]
|
|
800b742: 68f8 ldr r0, [r7, #12]
|
|
800b744: f7ff fa4c bl 800abe0 <AT_RequestReceiveData>
|
|
800b748: 4603 mov r3, r0
|
|
800b74a: 74fb strb r3, [r7, #19]
|
|
if (ret != ES_WIFI_STATUS_OK)
|
|
800b74c: 7cfb ldrb r3, [r7, #19]
|
|
800b74e: 2b00 cmp r3, #0
|
|
800b750: d02e beq.n 800b7b0 <ES_WIFI_ReceiveData+0x148>
|
|
{
|
|
DEBUG("AT_RequestReceiveData failed\n");
|
|
800b752: f640 02fd movw r2, #2301 @ 0x8fd
|
|
800b756: 491d ldr r1, [pc, #116] @ (800b7cc <ES_WIFI_ReceiveData+0x164>)
|
|
800b758: 481d ldr r0, [pc, #116] @ (800b7d0 <ES_WIFI_ReceiveData+0x168>)
|
|
800b75a: f004 fd3b bl 80101d4 <iprintf>
|
|
800b75e: 481d ldr r0, [pc, #116] @ (800b7d4 <ES_WIFI_ReceiveData+0x16c>)
|
|
800b760: f004 fda0 bl 80102a4 <puts>
|
|
800b764: e024 b.n 800b7b0 <ES_WIFI_ReceiveData+0x148>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DEBUG("setting timeout failed\n");
|
|
800b766: f640 1202 movw r2, #2306 @ 0x902
|
|
800b76a: 4918 ldr r1, [pc, #96] @ (800b7cc <ES_WIFI_ReceiveData+0x164>)
|
|
800b76c: 4818 ldr r0, [pc, #96] @ (800b7d0 <ES_WIFI_ReceiveData+0x168>)
|
|
800b76e: f004 fd31 bl 80101d4 <iprintf>
|
|
800b772: 4819 ldr r0, [pc, #100] @ (800b7d8 <ES_WIFI_ReceiveData+0x170>)
|
|
800b774: f004 fd96 bl 80102a4 <puts>
|
|
800b778: e01a b.n 800b7b0 <ES_WIFI_ReceiveData+0x148>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DEBUG("setting requested len failed\n");
|
|
800b77a: f640 1207 movw r2, #2311 @ 0x907
|
|
800b77e: 4913 ldr r1, [pc, #76] @ (800b7cc <ES_WIFI_ReceiveData+0x164>)
|
|
800b780: 4813 ldr r0, [pc, #76] @ (800b7d0 <ES_WIFI_ReceiveData+0x168>)
|
|
800b782: f004 fd27 bl 80101d4 <iprintf>
|
|
800b786: 4815 ldr r0, [pc, #84] @ (800b7dc <ES_WIFI_ReceiveData+0x174>)
|
|
800b788: f004 fd8c bl 80102a4 <puts>
|
|
*Receivedlen = 0;
|
|
800b78c: 6a3b ldr r3, [r7, #32]
|
|
800b78e: 2200 movs r2, #0
|
|
800b790: 801a strh r2, [r3, #0]
|
|
800b792: e00d b.n 800b7b0 <ES_WIFI_ReceiveData+0x148>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DEBUG("setting socket for read failed\n");
|
|
800b794: f640 120d movw r2, #2317 @ 0x90d
|
|
800b798: 490c ldr r1, [pc, #48] @ (800b7cc <ES_WIFI_ReceiveData+0x164>)
|
|
800b79a: 480d ldr r0, [pc, #52] @ (800b7d0 <ES_WIFI_ReceiveData+0x168>)
|
|
800b79c: f004 fd1a bl 80101d4 <iprintf>
|
|
800b7a0: 480f ldr r0, [pc, #60] @ (800b7e0 <ES_WIFI_ReceiveData+0x178>)
|
|
800b7a2: f004 fd7f bl 80102a4 <puts>
|
|
issue15++;
|
|
800b7a6: 4b0f ldr r3, [pc, #60] @ (800b7e4 <ES_WIFI_ReceiveData+0x17c>)
|
|
800b7a8: 681b ldr r3, [r3, #0]
|
|
800b7aa: 3301 adds r3, #1
|
|
800b7ac: 4a0d ldr r2, [pc, #52] @ (800b7e4 <ES_WIFI_ReceiveData+0x17c>)
|
|
800b7ae: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
UNLOCK_WIFI();
|
|
return ret;
|
|
800b7b0: 7cfb ldrb r3, [r7, #19]
|
|
}
|
|
800b7b2: 4618 mov r0, r3
|
|
800b7b4: 3718 adds r7, #24
|
|
800b7b6: 46bd mov sp, r7
|
|
800b7b8: bd80 pop {r7, pc}
|
|
800b7ba: bf00 nop
|
|
800b7bc: 080143c8 .word 0x080143c8
|
|
800b7c0: 0801460c .word 0x0801460c
|
|
800b7c4: 08014614 .word 0x08014614
|
|
800b7c8: 0801461c .word 0x0801461c
|
|
800b7cc: 08014458 .word 0x08014458
|
|
800b7d0: 08014474 .word 0x08014474
|
|
800b7d4: 08014620 .word 0x08014620
|
|
800b7d8: 08014640 .word 0x08014640
|
|
800b7dc: 08014658 .word 0x08014658
|
|
800b7e0: 08014678 .word 0x08014678
|
|
800b7e4: 2000130c .word 0x2000130c
|
|
|
|
0800b7e8 <SPI_WIFI_MspInit>:
|
|
* @brief Initialize SPI MSP
|
|
* @param hspi: SPI handle
|
|
* @retval None
|
|
*/
|
|
void SPI_WIFI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
800b7e8: b580 push {r7, lr}
|
|
800b7ea: b08c sub sp, #48 @ 0x30
|
|
800b7ec: af00 add r7, sp, #0
|
|
800b7ee: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_Init;
|
|
|
|
__HAL_RCC_SPI3_CLK_ENABLE();
|
|
800b7f0: 4b57 ldr r3, [pc, #348] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b7f2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800b7f4: 4a56 ldr r2, [pc, #344] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b7f6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800b7fa: 6593 str r3, [r2, #88] @ 0x58
|
|
800b7fc: 4b54 ldr r3, [pc, #336] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b7fe: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800b800: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
800b804: 61bb str r3, [r7, #24]
|
|
800b806: 69bb ldr r3, [r7, #24]
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800b808: 4b51 ldr r3, [pc, #324] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b80a: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800b80c: 4a50 ldr r2, [pc, #320] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b80e: f043 0302 orr.w r3, r3, #2
|
|
800b812: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800b814: 4b4e ldr r3, [pc, #312] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b816: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800b818: f003 0302 and.w r3, r3, #2
|
|
800b81c: 617b str r3, [r7, #20]
|
|
800b81e: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800b820: 4b4b ldr r3, [pc, #300] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b822: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800b824: 4a4a ldr r2, [pc, #296] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b826: f043 0304 orr.w r3, r3, #4
|
|
800b82a: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800b82c: 4b48 ldr r3, [pc, #288] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b82e: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800b830: f003 0304 and.w r3, r3, #4
|
|
800b834: 613b str r3, [r7, #16]
|
|
800b836: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
800b838: 4b45 ldr r3, [pc, #276] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b83a: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800b83c: 4a44 ldr r2, [pc, #272] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b83e: f043 0310 orr.w r3, r3, #16
|
|
800b842: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800b844: 4b42 ldr r3, [pc, #264] @ (800b950 <SPI_WIFI_MspInit+0x168>)
|
|
800b846: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800b848: f003 0310 and.w r3, r3, #16
|
|
800b84c: 60fb str r3, [r7, #12]
|
|
800b84e: 68fb ldr r3, [r7, #12]
|
|
|
|
/* configure Wake up pin */
|
|
HAL_GPIO_WritePin(GPIOB,GPIO_PIN_13, GPIO_PIN_RESET );
|
|
800b850: 2200 movs r2, #0
|
|
800b852: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
800b856: 483f ldr r0, [pc, #252] @ (800b954 <SPI_WIFI_MspInit+0x16c>)
|
|
800b858: f7f8 ffa6 bl 80047a8 <HAL_GPIO_WritePin>
|
|
GPIO_Init.Pin = GPIO_PIN_13;
|
|
800b85c: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
800b860: 61fb str r3, [r7, #28]
|
|
GPIO_Init.Mode = GPIO_MODE_OUTPUT_PP;
|
|
800b862: 2301 movs r3, #1
|
|
800b864: 623b str r3, [r7, #32]
|
|
GPIO_Init.Pull = GPIO_NOPULL;
|
|
800b866: 2300 movs r3, #0
|
|
800b868: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_Init.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800b86a: 2300 movs r3, #0
|
|
800b86c: 62bb str r3, [r7, #40] @ 0x28
|
|
HAL_GPIO_Init(GPIOB, &GPIO_Init );
|
|
800b86e: f107 031c add.w r3, r7, #28
|
|
800b872: 4619 mov r1, r3
|
|
800b874: 4837 ldr r0, [pc, #220] @ (800b954 <SPI_WIFI_MspInit+0x16c>)
|
|
800b876: f7f8 fce1 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* configure Data ready pin */
|
|
GPIO_Init.Pin = GPIO_PIN_1;
|
|
800b87a: 2302 movs r3, #2
|
|
800b87c: 61fb str r3, [r7, #28]
|
|
GPIO_Init.Mode = GPIO_MODE_IT_RISING;
|
|
800b87e: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
800b882: 623b str r3, [r7, #32]
|
|
GPIO_Init.Pull = GPIO_NOPULL;
|
|
800b884: 2300 movs r3, #0
|
|
800b886: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_Init.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800b888: 2300 movs r3, #0
|
|
800b88a: 62bb str r3, [r7, #40] @ 0x28
|
|
HAL_GPIO_Init(GPIOE, &GPIO_Init );
|
|
800b88c: f107 031c add.w r3, r7, #28
|
|
800b890: 4619 mov r1, r3
|
|
800b892: 4831 ldr r0, [pc, #196] @ (800b958 <SPI_WIFI_MspInit+0x170>)
|
|
800b894: f7f8 fcd2 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* configure Reset pin */
|
|
GPIO_Init.Pin = GPIO_PIN_8;
|
|
800b898: f44f 7380 mov.w r3, #256 @ 0x100
|
|
800b89c: 61fb str r3, [r7, #28]
|
|
GPIO_Init.Mode = GPIO_MODE_OUTPUT_PP;
|
|
800b89e: 2301 movs r3, #1
|
|
800b8a0: 623b str r3, [r7, #32]
|
|
GPIO_Init.Pull = GPIO_NOPULL;
|
|
800b8a2: 2300 movs r3, #0
|
|
800b8a4: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_Init.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800b8a6: 2300 movs r3, #0
|
|
800b8a8: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_Init.Alternate = 0;
|
|
800b8aa: 2300 movs r3, #0
|
|
800b8ac: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(GPIOE, &GPIO_Init );
|
|
800b8ae: f107 031c add.w r3, r7, #28
|
|
800b8b2: 4619 mov r1, r3
|
|
800b8b4: 4828 ldr r0, [pc, #160] @ (800b958 <SPI_WIFI_MspInit+0x170>)
|
|
800b8b6: f7f8 fcc1 bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* configure SPI NSS pin pin */
|
|
HAL_GPIO_WritePin( GPIOE , GPIO_PIN_0, GPIO_PIN_SET );
|
|
800b8ba: 2201 movs r2, #1
|
|
800b8bc: 2101 movs r1, #1
|
|
800b8be: 4826 ldr r0, [pc, #152] @ (800b958 <SPI_WIFI_MspInit+0x170>)
|
|
800b8c0: f7f8 ff72 bl 80047a8 <HAL_GPIO_WritePin>
|
|
GPIO_Init.Pin = GPIO_PIN_0;
|
|
800b8c4: 2301 movs r3, #1
|
|
800b8c6: 61fb str r3, [r7, #28]
|
|
GPIO_Init.Mode = GPIO_MODE_OUTPUT_PP;
|
|
800b8c8: 2301 movs r3, #1
|
|
800b8ca: 623b str r3, [r7, #32]
|
|
GPIO_Init.Pull = GPIO_NOPULL;
|
|
800b8cc: 2300 movs r3, #0
|
|
800b8ce: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_Init.Speed = GPIO_SPEED_FREQ_MEDIUM;
|
|
800b8d0: 2301 movs r3, #1
|
|
800b8d2: 62bb str r3, [r7, #40] @ 0x28
|
|
HAL_GPIO_Init( GPIOE, &GPIO_Init );
|
|
800b8d4: f107 031c add.w r3, r7, #28
|
|
800b8d8: 4619 mov r1, r3
|
|
800b8da: 481f ldr r0, [pc, #124] @ (800b958 <SPI_WIFI_MspInit+0x170>)
|
|
800b8dc: f7f8 fcae bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* configure SPI CLK pin */
|
|
GPIO_Init.Pin = GPIO_PIN_10;
|
|
800b8e0: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
800b8e4: 61fb str r3, [r7, #28]
|
|
GPIO_Init.Mode = GPIO_MODE_AF_PP;
|
|
800b8e6: 2302 movs r3, #2
|
|
800b8e8: 623b str r3, [r7, #32]
|
|
GPIO_Init.Pull = GPIO_NOPULL;
|
|
800b8ea: 2300 movs r3, #0
|
|
800b8ec: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_Init.Speed = GPIO_SPEED_FREQ_MEDIUM;
|
|
800b8ee: 2301 movs r3, #1
|
|
800b8f0: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_Init.Alternate = GPIO_AF6_SPI3;
|
|
800b8f2: 2306 movs r3, #6
|
|
800b8f4: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(GPIOC, &GPIO_Init );
|
|
800b8f6: f107 031c add.w r3, r7, #28
|
|
800b8fa: 4619 mov r1, r3
|
|
800b8fc: 4817 ldr r0, [pc, #92] @ (800b95c <SPI_WIFI_MspInit+0x174>)
|
|
800b8fe: f7f8 fc9d bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* configure SPI MOSI pin */
|
|
GPIO_Init.Pin = GPIO_PIN_12;
|
|
800b902: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
800b906: 61fb str r3, [r7, #28]
|
|
GPIO_Init.Mode = GPIO_MODE_AF_PP;
|
|
800b908: 2302 movs r3, #2
|
|
800b90a: 623b str r3, [r7, #32]
|
|
GPIO_Init.Pull = GPIO_NOPULL;
|
|
800b90c: 2300 movs r3, #0
|
|
800b90e: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_Init.Speed = GPIO_SPEED_FREQ_MEDIUM;
|
|
800b910: 2301 movs r3, #1
|
|
800b912: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_Init.Alternate = GPIO_AF6_SPI3;
|
|
800b914: 2306 movs r3, #6
|
|
800b916: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init( GPIOC, &GPIO_Init );
|
|
800b918: f107 031c add.w r3, r7, #28
|
|
800b91c: 4619 mov r1, r3
|
|
800b91e: 480f ldr r0, [pc, #60] @ (800b95c <SPI_WIFI_MspInit+0x174>)
|
|
800b920: f7f8 fc8c bl 800423c <HAL_GPIO_Init>
|
|
|
|
/* configure SPI MISO pin */
|
|
GPIO_Init.Pin = GPIO_PIN_11;
|
|
800b924: f44f 6300 mov.w r3, #2048 @ 0x800
|
|
800b928: 61fb str r3, [r7, #28]
|
|
GPIO_Init.Mode = GPIO_MODE_AF_PP;
|
|
800b92a: 2302 movs r3, #2
|
|
800b92c: 623b str r3, [r7, #32]
|
|
GPIO_Init.Pull = GPIO_PULLUP;
|
|
800b92e: 2301 movs r3, #1
|
|
800b930: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_Init.Speed = GPIO_SPEED_FREQ_MEDIUM;
|
|
800b932: 2301 movs r3, #1
|
|
800b934: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_Init.Alternate = GPIO_AF6_SPI3;
|
|
800b936: 2306 movs r3, #6
|
|
800b938: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init( GPIOC,&GPIO_Init );
|
|
800b93a: f107 031c add.w r3, r7, #28
|
|
800b93e: 4619 mov r1, r3
|
|
800b940: 4806 ldr r0, [pc, #24] @ (800b95c <SPI_WIFI_MspInit+0x174>)
|
|
800b942: f7f8 fc7b bl 800423c <HAL_GPIO_Init>
|
|
}
|
|
800b946: bf00 nop
|
|
800b948: 3730 adds r7, #48 @ 0x30
|
|
800b94a: 46bd mov sp, r7
|
|
800b94c: bd80 pop {r7, pc}
|
|
800b94e: bf00 nop
|
|
800b950: 40021000 .word 0x40021000
|
|
800b954: 48000400 .word 0x48000400
|
|
800b958: 48001000 .word 0x48001000
|
|
800b95c: 48000800 .word 0x48000800
|
|
|
|
0800b960 <SPI_WIFI_Init>:
|
|
* @brief Initialize the SPI3
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
int8_t SPI_WIFI_Init(uint16_t mode)
|
|
{
|
|
800b960: b580 push {r7, lr}
|
|
800b962: b084 sub sp, #16
|
|
800b964: af00 add r7, sp, #0
|
|
800b966: 4603 mov r3, r0
|
|
800b968: 80fb strh r3, [r7, #6]
|
|
int8_t rc=0;
|
|
800b96a: 2300 movs r3, #0
|
|
800b96c: 73fb strb r3, [r7, #15]
|
|
|
|
if (mode == ES_WIFI_INIT)
|
|
800b96e: 88fb ldrh r3, [r7, #6]
|
|
800b970: 2b00 cmp r3, #0
|
|
800b972: d145 bne.n 800ba00 <SPI_WIFI_Init+0xa0>
|
|
{
|
|
hspi.Instance = SPI3;
|
|
800b974: 4b27 ldr r3, [pc, #156] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b976: 4a28 ldr r2, [pc, #160] @ (800ba18 <SPI_WIFI_Init+0xb8>)
|
|
800b978: 601a str r2, [r3, #0]
|
|
SPI_WIFI_MspInit(&hspi);
|
|
800b97a: 4826 ldr r0, [pc, #152] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b97c: f7ff ff34 bl 800b7e8 <SPI_WIFI_MspInit>
|
|
|
|
hspi.Init.Mode = SPI_MODE_MASTER;
|
|
800b980: 4b24 ldr r3, [pc, #144] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b982: f44f 7282 mov.w r2, #260 @ 0x104
|
|
800b986: 605a str r2, [r3, #4]
|
|
hspi.Init.Direction = SPI_DIRECTION_2LINES;
|
|
800b988: 4b22 ldr r3, [pc, #136] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b98a: 2200 movs r2, #0
|
|
800b98c: 609a str r2, [r3, #8]
|
|
hspi.Init.DataSize = SPI_DATASIZE_16BIT;
|
|
800b98e: 4b21 ldr r3, [pc, #132] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b990: f44f 6270 mov.w r2, #3840 @ 0xf00
|
|
800b994: 60da str r2, [r3, #12]
|
|
hspi.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
800b996: 4b1f ldr r3, [pc, #124] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b998: 2200 movs r2, #0
|
|
800b99a: 611a str r2, [r3, #16]
|
|
hspi.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
800b99c: 4b1d ldr r3, [pc, #116] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b99e: 2200 movs r2, #0
|
|
800b9a0: 615a str r2, [r3, #20]
|
|
hspi.Init.NSS = SPI_NSS_SOFT;
|
|
800b9a2: 4b1c ldr r3, [pc, #112] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b9a4: f44f 7200 mov.w r2, #512 @ 0x200
|
|
800b9a8: 619a str r2, [r3, #24]
|
|
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; /* 80/8= 10MHz (Inventek WIFI module supports up to 20MHz)*/
|
|
800b9aa: 4b1a ldr r3, [pc, #104] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b9ac: 2210 movs r2, #16
|
|
800b9ae: 61da str r2, [r3, #28]
|
|
hspi.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
800b9b0: 4b18 ldr r3, [pc, #96] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b9b2: 2200 movs r2, #0
|
|
800b9b4: 621a str r2, [r3, #32]
|
|
hspi.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
800b9b6: 4b17 ldr r3, [pc, #92] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b9b8: 2200 movs r2, #0
|
|
800b9ba: 625a str r2, [r3, #36] @ 0x24
|
|
hspi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
800b9bc: 4b15 ldr r3, [pc, #84] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b9be: 2200 movs r2, #0
|
|
800b9c0: 629a str r2, [r3, #40] @ 0x28
|
|
hspi.Init.CRCPolynomial = 0;
|
|
800b9c2: 4b14 ldr r3, [pc, #80] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b9c4: 2200 movs r2, #0
|
|
800b9c6: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
if(HAL_SPI_Init( &hspi ) != HAL_OK)
|
|
800b9c8: 4812 ldr r0, [pc, #72] @ (800ba14 <SPI_WIFI_Init+0xb4>)
|
|
800b9ca: f7fb fadf bl 8006f8c <HAL_SPI_Init>
|
|
800b9ce: 4603 mov r3, r0
|
|
800b9d0: 2b00 cmp r3, #0
|
|
800b9d2: d002 beq.n 800b9da <SPI_WIFI_Init+0x7a>
|
|
{
|
|
return -1;
|
|
800b9d4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800b9d8: e018 b.n 800ba0c <SPI_WIFI_Init+0xac>
|
|
}
|
|
|
|
/* Enable Interrupt for Data Ready pin , GPIO_PIN1 */
|
|
HAL_NVIC_SetPriority((IRQn_Type)EXTI1_IRQn, SPI_INTERFACE_PRIO, 0x00);
|
|
800b9da: 2200 movs r2, #0
|
|
800b9dc: 2100 movs r1, #0
|
|
800b9de: 2007 movs r0, #7
|
|
800b9e0: f7f8 fa76 bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ((IRQn_Type)EXTI1_IRQn);
|
|
800b9e4: 2007 movs r0, #7
|
|
800b9e6: f7f8 fa8f bl 8003f08 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* Enable Interrupt for SPI tx and rx */
|
|
HAL_NVIC_SetPriority((IRQn_Type)SPI3_IRQn, SPI_INTERFACE_PRIO, 0);
|
|
800b9ea: 2200 movs r2, #0
|
|
800b9ec: 2100 movs r1, #0
|
|
800b9ee: 2033 movs r0, #51 @ 0x33
|
|
800b9f0: f7f8 fa6e bl 8003ed0 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ((IRQn_Type)SPI3_IRQn);
|
|
800b9f4: 2033 movs r0, #51 @ 0x33
|
|
800b9f6: f7f8 fa87 bl 8003f08 <HAL_NVIC_EnableIRQ>
|
|
SEM_WAIT(spi_rx_sem, 1);
|
|
SEM_WAIT(spi_tx_sem, 1);
|
|
|
|
#endif
|
|
/* first call used for calibration */
|
|
SPI_WIFI_DelayUs(10);
|
|
800b9fa: 200a movs r0, #10
|
|
800b9fc: f000 f9fe bl 800bdfc <SPI_WIFI_DelayUs>
|
|
}
|
|
|
|
rc= SPI_WIFI_ResetModule();
|
|
800ba00: f000 f80c bl 800ba1c <SPI_WIFI_ResetModule>
|
|
800ba04: 4603 mov r3, r0
|
|
800ba06: 73fb strb r3, [r7, #15]
|
|
|
|
return rc;
|
|
800ba08: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
800ba0c: 4618 mov r0, r3
|
|
800ba0e: 3710 adds r7, #16
|
|
800ba10: 46bd mov sp, r7
|
|
800ba12: bd80 pop {r7, pc}
|
|
800ba14: 20001310 .word 0x20001310
|
|
800ba18: 40003c00 .word 0x40003c00
|
|
|
|
0800ba1c <SPI_WIFI_ResetModule>:
|
|
|
|
|
|
int8_t SPI_WIFI_ResetModule(void)
|
|
{
|
|
800ba1c: b580 push {r7, lr}
|
|
800ba1e: b084 sub sp, #16
|
|
800ba20: af00 add r7, sp, #0
|
|
uint32_t tickstart = HAL_GetTick();
|
|
800ba22: f7f8 f96d bl 8003d00 <HAL_GetTick>
|
|
800ba26: 60b8 str r0, [r7, #8]
|
|
uint8_t Prompt[6];
|
|
uint8_t count = 0;
|
|
800ba28: 2300 movs r3, #0
|
|
800ba2a: 73fb strb r3, [r7, #15]
|
|
HAL_StatusTypeDef Status;
|
|
|
|
WIFI_RESET_MODULE();
|
|
800ba2c: 2200 movs r2, #0
|
|
800ba2e: f44f 7180 mov.w r1, #256 @ 0x100
|
|
800ba32: 4830 ldr r0, [pc, #192] @ (800baf4 <SPI_WIFI_ResetModule+0xd8>)
|
|
800ba34: f7f8 feb8 bl 80047a8 <HAL_GPIO_WritePin>
|
|
800ba38: 200a movs r0, #10
|
|
800ba3a: f7f8 f96d bl 8003d18 <HAL_Delay>
|
|
800ba3e: 2201 movs r2, #1
|
|
800ba40: f44f 7180 mov.w r1, #256 @ 0x100
|
|
800ba44: 482b ldr r0, [pc, #172] @ (800baf4 <SPI_WIFI_ResetModule+0xd8>)
|
|
800ba46: f7f8 feaf bl 80047a8 <HAL_GPIO_WritePin>
|
|
800ba4a: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
800ba4e: f7f8 f963 bl 8003d18 <HAL_Delay>
|
|
WIFI_ENABLE_NSS();
|
|
800ba52: 2200 movs r2, #0
|
|
800ba54: 2101 movs r1, #1
|
|
800ba56: 4827 ldr r0, [pc, #156] @ (800baf4 <SPI_WIFI_ResetModule+0xd8>)
|
|
800ba58: f7f8 fea6 bl 80047a8 <HAL_GPIO_WritePin>
|
|
SPI_WIFI_DelayUs(15);
|
|
800ba5c: 200f movs r0, #15
|
|
800ba5e: f000 f9cd bl 800bdfc <SPI_WIFI_DelayUs>
|
|
|
|
while (WIFI_IS_CMDDATA_READY())
|
|
800ba62: e020 b.n 800baa6 <SPI_WIFI_ResetModule+0x8a>
|
|
{
|
|
Status = HAL_SPI_Receive(&hspi , &Prompt[count], 1, 0xFFFF);
|
|
800ba64: 7bfb ldrb r3, [r7, #15]
|
|
800ba66: 463a mov r2, r7
|
|
800ba68: 18d1 adds r1, r2, r3
|
|
800ba6a: f64f 73ff movw r3, #65535 @ 0xffff
|
|
800ba6e: 2201 movs r2, #1
|
|
800ba70: 4821 ldr r0, [pc, #132] @ (800baf8 <SPI_WIFI_ResetModule+0xdc>)
|
|
800ba72: f7fb fb56 bl 8007122 <HAL_SPI_Receive>
|
|
800ba76: 4603 mov r3, r0
|
|
800ba78: 71fb strb r3, [r7, #7]
|
|
count += 2;
|
|
800ba7a: 7bfb ldrb r3, [r7, #15]
|
|
800ba7c: 3302 adds r3, #2
|
|
800ba7e: 73fb strb r3, [r7, #15]
|
|
if(((HAL_GetTick() - tickstart ) > 0xFFFF) || (Status != HAL_OK))
|
|
800ba80: f7f8 f93e bl 8003d00 <HAL_GetTick>
|
|
800ba84: 4602 mov r2, r0
|
|
800ba86: 68bb ldr r3, [r7, #8]
|
|
800ba88: 1ad3 subs r3, r2, r3
|
|
800ba8a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800ba8e: d202 bcs.n 800ba96 <SPI_WIFI_ResetModule+0x7a>
|
|
800ba90: 79fb ldrb r3, [r7, #7]
|
|
800ba92: 2b00 cmp r3, #0
|
|
800ba94: d007 beq.n 800baa6 <SPI_WIFI_ResetModule+0x8a>
|
|
{
|
|
WIFI_DISABLE_NSS();
|
|
800ba96: 2201 movs r2, #1
|
|
800ba98: 2101 movs r1, #1
|
|
800ba9a: 4816 ldr r0, [pc, #88] @ (800baf4 <SPI_WIFI_ResetModule+0xd8>)
|
|
800ba9c: f7f8 fe84 bl 80047a8 <HAL_GPIO_WritePin>
|
|
return -1;
|
|
800baa0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800baa4: e021 b.n 800baea <SPI_WIFI_ResetModule+0xce>
|
|
while (WIFI_IS_CMDDATA_READY())
|
|
800baa6: 2102 movs r1, #2
|
|
800baa8: 4812 ldr r0, [pc, #72] @ (800baf4 <SPI_WIFI_ResetModule+0xd8>)
|
|
800baaa: f7f8 fe65 bl 8004778 <HAL_GPIO_ReadPin>
|
|
800baae: 4603 mov r3, r0
|
|
800bab0: 2b01 cmp r3, #1
|
|
800bab2: d0d7 beq.n 800ba64 <SPI_WIFI_ResetModule+0x48>
|
|
}
|
|
}
|
|
|
|
WIFI_DISABLE_NSS();
|
|
800bab4: 2201 movs r2, #1
|
|
800bab6: 2101 movs r1, #1
|
|
800bab8: 480e ldr r0, [pc, #56] @ (800baf4 <SPI_WIFI_ResetModule+0xd8>)
|
|
800baba: f7f8 fe75 bl 80047a8 <HAL_GPIO_WritePin>
|
|
if((Prompt[0] != 0x15) ||(Prompt[1] != 0x15) ||(Prompt[2] != '\r')||
|
|
800babe: 783b ldrb r3, [r7, #0]
|
|
800bac0: 2b15 cmp r3, #21
|
|
800bac2: d10e bne.n 800bae2 <SPI_WIFI_ResetModule+0xc6>
|
|
800bac4: 787b ldrb r3, [r7, #1]
|
|
800bac6: 2b15 cmp r3, #21
|
|
800bac8: d10b bne.n 800bae2 <SPI_WIFI_ResetModule+0xc6>
|
|
800baca: 78bb ldrb r3, [r7, #2]
|
|
800bacc: 2b0d cmp r3, #13
|
|
800bace: d108 bne.n 800bae2 <SPI_WIFI_ResetModule+0xc6>
|
|
(Prompt[3] != '\n') ||(Prompt[4] != '>') ||(Prompt[5] != ' '))
|
|
800bad0: 78fb ldrb r3, [r7, #3]
|
|
if((Prompt[0] != 0x15) ||(Prompt[1] != 0x15) ||(Prompt[2] != '\r')||
|
|
800bad2: 2b0a cmp r3, #10
|
|
800bad4: d105 bne.n 800bae2 <SPI_WIFI_ResetModule+0xc6>
|
|
(Prompt[3] != '\n') ||(Prompt[4] != '>') ||(Prompt[5] != ' '))
|
|
800bad6: 793b ldrb r3, [r7, #4]
|
|
800bad8: 2b3e cmp r3, #62 @ 0x3e
|
|
800bada: d102 bne.n 800bae2 <SPI_WIFI_ResetModule+0xc6>
|
|
800badc: 797b ldrb r3, [r7, #5]
|
|
800bade: 2b20 cmp r3, #32
|
|
800bae0: d002 beq.n 800bae8 <SPI_WIFI_ResetModule+0xcc>
|
|
{
|
|
return -1;
|
|
800bae2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bae6: e000 b.n 800baea <SPI_WIFI_ResetModule+0xce>
|
|
}
|
|
return 0;
|
|
800bae8: 2300 movs r3, #0
|
|
}
|
|
800baea: 4618 mov r0, r3
|
|
800baec: 3710 adds r7, #16
|
|
800baee: 46bd mov sp, r7
|
|
800baf0: bd80 pop {r7, pc}
|
|
800baf2: bf00 nop
|
|
800baf4: 48001000 .word 0x48001000
|
|
800baf8: 20001310 .word 0x20001310
|
|
|
|
0800bafc <SPI_WIFI_DeInit>:
|
|
* @brief DeInitialize the SPI
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
int8_t SPI_WIFI_DeInit(void)
|
|
{
|
|
800bafc: b580 push {r7, lr}
|
|
800bafe: af00 add r7, sp, #0
|
|
HAL_SPI_DeInit( &hspi );
|
|
800bb00: 4802 ldr r0, [pc, #8] @ (800bb0c <SPI_WIFI_DeInit+0x10>)
|
|
800bb02: f7fb fae6 bl 80070d2 <HAL_SPI_DeInit>
|
|
osMutexDelete(es_wifi_mutex);
|
|
osSemaphoreDelete(spi_tx_sem);
|
|
osSemaphoreDelete(spi_rx_sem);
|
|
osSemaphoreDelete(cmddata_rdy_rising_sem);
|
|
#endif
|
|
return 0;
|
|
800bb06: 2300 movs r3, #0
|
|
}
|
|
800bb08: 4618 mov r0, r3
|
|
800bb0a: bd80 pop {r7, pc}
|
|
800bb0c: 20001310 .word 0x20001310
|
|
|
|
0800bb10 <wait_cmddata_rdy_high>:
|
|
* @param timeout : send timeout in mS
|
|
* @retval Length of received data (payload)
|
|
*/
|
|
|
|
int wait_cmddata_rdy_high(int timeout)
|
|
{
|
|
800bb10: b580 push {r7, lr}
|
|
800bb12: b084 sub sp, #16
|
|
800bb14: af00 add r7, sp, #0
|
|
800bb16: 6078 str r0, [r7, #4]
|
|
int tickstart = HAL_GetTick();
|
|
800bb18: f7f8 f8f2 bl 8003d00 <HAL_GetTick>
|
|
800bb1c: 4603 mov r3, r0
|
|
800bb1e: 60fb str r3, [r7, #12]
|
|
while (WIFI_IS_CMDDATA_READY()==0)
|
|
800bb20: e00a b.n 800bb38 <wait_cmddata_rdy_high+0x28>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > timeout)
|
|
800bb22: f7f8 f8ed bl 8003d00 <HAL_GetTick>
|
|
800bb26: 4602 mov r2, r0
|
|
800bb28: 68fb ldr r3, [r7, #12]
|
|
800bb2a: 1ad2 subs r2, r2, r3
|
|
800bb2c: 687b ldr r3, [r7, #4]
|
|
800bb2e: 429a cmp r2, r3
|
|
800bb30: d902 bls.n 800bb38 <wait_cmddata_rdy_high+0x28>
|
|
{
|
|
return -1;
|
|
800bb32: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bb36: e007 b.n 800bb48 <wait_cmddata_rdy_high+0x38>
|
|
while (WIFI_IS_CMDDATA_READY()==0)
|
|
800bb38: 2102 movs r1, #2
|
|
800bb3a: 4805 ldr r0, [pc, #20] @ (800bb50 <wait_cmddata_rdy_high+0x40>)
|
|
800bb3c: f7f8 fe1c bl 8004778 <HAL_GPIO_ReadPin>
|
|
800bb40: 4603 mov r3, r0
|
|
800bb42: 2b01 cmp r3, #1
|
|
800bb44: d1ed bne.n 800bb22 <wait_cmddata_rdy_high+0x12>
|
|
}
|
|
}
|
|
return 0;
|
|
800bb46: 2300 movs r3, #0
|
|
}
|
|
800bb48: 4618 mov r0, r3
|
|
800bb4a: 3710 adds r7, #16
|
|
800bb4c: 46bd mov sp, r7
|
|
800bb4e: bd80 pop {r7, pc}
|
|
800bb50: 48001000 .word 0x48001000
|
|
|
|
0800bb54 <wait_cmddata_rdy_rising_event>:
|
|
|
|
|
|
|
|
int wait_cmddata_rdy_rising_event(int timeout)
|
|
{
|
|
800bb54: b580 push {r7, lr}
|
|
800bb56: b084 sub sp, #16
|
|
800bb58: af00 add r7, sp, #0
|
|
800bb5a: 6078 str r0, [r7, #4]
|
|
#ifdef SEM_WAIT
|
|
return SEM_WAIT(cmddata_rdy_rising_sem, timeout);
|
|
#else
|
|
int tickstart = HAL_GetTick();
|
|
800bb5c: f7f8 f8d0 bl 8003d00 <HAL_GetTick>
|
|
800bb60: 4603 mov r3, r0
|
|
800bb62: 60fb str r3, [r7, #12]
|
|
while (cmddata_rdy_rising_event==1)
|
|
800bb64: e00a b.n 800bb7c <wait_cmddata_rdy_rising_event+0x28>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > timeout)
|
|
800bb66: f7f8 f8cb bl 8003d00 <HAL_GetTick>
|
|
800bb6a: 4602 mov r2, r0
|
|
800bb6c: 68fb ldr r3, [r7, #12]
|
|
800bb6e: 1ad2 subs r2, r2, r3
|
|
800bb70: 687b ldr r3, [r7, #4]
|
|
800bb72: 429a cmp r2, r3
|
|
800bb74: d902 bls.n 800bb7c <wait_cmddata_rdy_rising_event+0x28>
|
|
{
|
|
return -1;
|
|
800bb76: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bb7a: e004 b.n 800bb86 <wait_cmddata_rdy_rising_event+0x32>
|
|
while (cmddata_rdy_rising_event==1)
|
|
800bb7c: 4b04 ldr r3, [pc, #16] @ (800bb90 <wait_cmddata_rdy_rising_event+0x3c>)
|
|
800bb7e: 681b ldr r3, [r3, #0]
|
|
800bb80: 2b01 cmp r3, #1
|
|
800bb82: d0f0 beq.n 800bb66 <wait_cmddata_rdy_rising_event+0x12>
|
|
}
|
|
}
|
|
return 0;
|
|
800bb84: 2300 movs r3, #0
|
|
#endif
|
|
}
|
|
800bb86: 4618 mov r0, r3
|
|
800bb88: 3710 adds r7, #16
|
|
800bb8a: 46bd mov sp, r7
|
|
800bb8c: bd80 pop {r7, pc}
|
|
800bb8e: bf00 nop
|
|
800bb90: 2000137c .word 0x2000137c
|
|
|
|
0800bb94 <wait_spi_rx_event>:
|
|
|
|
int wait_spi_rx_event(int timeout)
|
|
{
|
|
800bb94: b580 push {r7, lr}
|
|
800bb96: b084 sub sp, #16
|
|
800bb98: af00 add r7, sp, #0
|
|
800bb9a: 6078 str r0, [r7, #4]
|
|
#ifdef SEM_WAIT
|
|
return SEM_WAIT(spi_rx_sem, timeout);
|
|
#else
|
|
int tickstart = HAL_GetTick();
|
|
800bb9c: f7f8 f8b0 bl 8003d00 <HAL_GetTick>
|
|
800bba0: 4603 mov r3, r0
|
|
800bba2: 60fb str r3, [r7, #12]
|
|
while (spi_rx_event==1)
|
|
800bba4: e00a b.n 800bbbc <wait_spi_rx_event+0x28>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > timeout)
|
|
800bba6: f7f8 f8ab bl 8003d00 <HAL_GetTick>
|
|
800bbaa: 4602 mov r2, r0
|
|
800bbac: 68fb ldr r3, [r7, #12]
|
|
800bbae: 1ad2 subs r2, r2, r3
|
|
800bbb0: 687b ldr r3, [r7, #4]
|
|
800bbb2: 429a cmp r2, r3
|
|
800bbb4: d902 bls.n 800bbbc <wait_spi_rx_event+0x28>
|
|
{
|
|
return -1;
|
|
800bbb6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bbba: e004 b.n 800bbc6 <wait_spi_rx_event+0x32>
|
|
while (spi_rx_event==1)
|
|
800bbbc: 4b04 ldr r3, [pc, #16] @ (800bbd0 <wait_spi_rx_event+0x3c>)
|
|
800bbbe: 681b ldr r3, [r3, #0]
|
|
800bbc0: 2b01 cmp r3, #1
|
|
800bbc2: d0f0 beq.n 800bba6 <wait_spi_rx_event+0x12>
|
|
}
|
|
}
|
|
return 0;
|
|
800bbc4: 2300 movs r3, #0
|
|
#endif
|
|
}
|
|
800bbc6: 4618 mov r0, r3
|
|
800bbc8: 3710 adds r7, #16
|
|
800bbca: 46bd mov sp, r7
|
|
800bbcc: bd80 pop {r7, pc}
|
|
800bbce: bf00 nop
|
|
800bbd0: 20001374 .word 0x20001374
|
|
|
|
0800bbd4 <wait_spi_tx_event>:
|
|
|
|
int wait_spi_tx_event(int timeout)
|
|
{
|
|
800bbd4: b580 push {r7, lr}
|
|
800bbd6: b084 sub sp, #16
|
|
800bbd8: af00 add r7, sp, #0
|
|
800bbda: 6078 str r0, [r7, #4]
|
|
#ifdef SEM_WAIT
|
|
return SEM_WAIT(spi_tx_sem, timeout);
|
|
#else
|
|
int tickstart = HAL_GetTick();
|
|
800bbdc: f7f8 f890 bl 8003d00 <HAL_GetTick>
|
|
800bbe0: 4603 mov r3, r0
|
|
800bbe2: 60fb str r3, [r7, #12]
|
|
while (spi_tx_event==1)
|
|
800bbe4: e00a b.n 800bbfc <wait_spi_tx_event+0x28>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > timeout)
|
|
800bbe6: f7f8 f88b bl 8003d00 <HAL_GetTick>
|
|
800bbea: 4602 mov r2, r0
|
|
800bbec: 68fb ldr r3, [r7, #12]
|
|
800bbee: 1ad2 subs r2, r2, r3
|
|
800bbf0: 687b ldr r3, [r7, #4]
|
|
800bbf2: 429a cmp r2, r3
|
|
800bbf4: d902 bls.n 800bbfc <wait_spi_tx_event+0x28>
|
|
{
|
|
return -1;
|
|
800bbf6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bbfa: e004 b.n 800bc06 <wait_spi_tx_event+0x32>
|
|
while (spi_tx_event==1)
|
|
800bbfc: 4b04 ldr r3, [pc, #16] @ (800bc10 <wait_spi_tx_event+0x3c>)
|
|
800bbfe: 681b ldr r3, [r3, #0]
|
|
800bc00: 2b01 cmp r3, #1
|
|
800bc02: d0f0 beq.n 800bbe6 <wait_spi_tx_event+0x12>
|
|
}
|
|
}
|
|
return 0;
|
|
800bc04: 2300 movs r3, #0
|
|
#endif
|
|
}
|
|
800bc06: 4618 mov r0, r3
|
|
800bc08: 3710 adds r7, #16
|
|
800bc0a: 46bd mov sp, r7
|
|
800bc0c: bd80 pop {r7, pc}
|
|
800bc0e: bf00 nop
|
|
800bc10: 20001378 .word 0x20001378
|
|
|
|
0800bc14 <SPI_WIFI_ReceiveData>:
|
|
|
|
|
|
|
|
int16_t SPI_WIFI_ReceiveData(uint8_t *pData, uint16_t len, uint32_t timeout)
|
|
{
|
|
800bc14: b580 push {r7, lr}
|
|
800bc16: b086 sub sp, #24
|
|
800bc18: af00 add r7, sp, #0
|
|
800bc1a: 60f8 str r0, [r7, #12]
|
|
800bc1c: 460b mov r3, r1
|
|
800bc1e: 607a str r2, [r7, #4]
|
|
800bc20: 817b strh r3, [r7, #10]
|
|
int16_t length = 0;
|
|
800bc22: 2300 movs r3, #0
|
|
800bc24: 82fb strh r3, [r7, #22]
|
|
uint8_t tmp[2];
|
|
|
|
WIFI_DISABLE_NSS();
|
|
800bc26: 2201 movs r2, #1
|
|
800bc28: 2101 movs r1, #1
|
|
800bc2a: 4834 ldr r0, [pc, #208] @ (800bcfc <SPI_WIFI_ReceiveData+0xe8>)
|
|
800bc2c: f7f8 fdbc bl 80047a8 <HAL_GPIO_WritePin>
|
|
UNLOCK_SPI();
|
|
SPI_WIFI_DelayUs(3);
|
|
800bc30: 2003 movs r0, #3
|
|
800bc32: f000 f8e3 bl 800bdfc <SPI_WIFI_DelayUs>
|
|
|
|
|
|
if (wait_cmddata_rdy_rising_event(timeout)<0)
|
|
800bc36: 687b ldr r3, [r7, #4]
|
|
800bc38: 4618 mov r0, r3
|
|
800bc3a: f7ff ff8b bl 800bb54 <wait_cmddata_rdy_rising_event>
|
|
800bc3e: 4603 mov r3, r0
|
|
800bc40: 2b00 cmp r3, #0
|
|
800bc42: da02 bge.n 800bc4a <SPI_WIFI_ReceiveData+0x36>
|
|
{
|
|
return ES_WIFI_ERROR_WAITING_DRDY_FALLING;
|
|
800bc44: f06f 0302 mvn.w r3, #2
|
|
800bc48: e054 b.n 800bcf4 <SPI_WIFI_ReceiveData+0xe0>
|
|
}
|
|
|
|
LOCK_SPI();
|
|
WIFI_ENABLE_NSS();
|
|
800bc4a: 2200 movs r2, #0
|
|
800bc4c: 2101 movs r1, #1
|
|
800bc4e: 482b ldr r0, [pc, #172] @ (800bcfc <SPI_WIFI_ReceiveData+0xe8>)
|
|
800bc50: f7f8 fdaa bl 80047a8 <HAL_GPIO_WritePin>
|
|
SPI_WIFI_DelayUs(15);
|
|
800bc54: 200f movs r0, #15
|
|
800bc56: f000 f8d1 bl 800bdfc <SPI_WIFI_DelayUs>
|
|
while (WIFI_IS_CMDDATA_READY())
|
|
800bc5a: e03d b.n 800bcd8 <SPI_WIFI_ReceiveData+0xc4>
|
|
{
|
|
if((length < len) || (!len))
|
|
800bc5c: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
800bc60: 897b ldrh r3, [r7, #10]
|
|
800bc62: 429a cmp r2, r3
|
|
800bc64: db02 blt.n 800bc6c <SPI_WIFI_ReceiveData+0x58>
|
|
800bc66: 897b ldrh r3, [r7, #10]
|
|
800bc68: 2b00 cmp r3, #0
|
|
800bc6a: d13c bne.n 800bce6 <SPI_WIFI_ReceiveData+0xd2>
|
|
{
|
|
spi_rx_event=1;
|
|
800bc6c: 4b24 ldr r3, [pc, #144] @ (800bd00 <SPI_WIFI_ReceiveData+0xec>)
|
|
800bc6e: 2201 movs r2, #1
|
|
800bc70: 601a str r2, [r3, #0]
|
|
if (HAL_SPI_Receive_IT(&hspi, tmp, 1) != HAL_OK) {
|
|
800bc72: f107 0314 add.w r3, r7, #20
|
|
800bc76: 2201 movs r2, #1
|
|
800bc78: 4619 mov r1, r3
|
|
800bc7a: 4822 ldr r0, [pc, #136] @ (800bd04 <SPI_WIFI_ReceiveData+0xf0>)
|
|
800bc7c: f7fb fe30 bl 80078e0 <HAL_SPI_Receive_IT>
|
|
800bc80: 4603 mov r3, r0
|
|
800bc82: 2b00 cmp r3, #0
|
|
800bc84: d007 beq.n 800bc96 <SPI_WIFI_ReceiveData+0x82>
|
|
WIFI_DISABLE_NSS();
|
|
800bc86: 2201 movs r2, #1
|
|
800bc88: 2101 movs r1, #1
|
|
800bc8a: 481c ldr r0, [pc, #112] @ (800bcfc <SPI_WIFI_ReceiveData+0xe8>)
|
|
800bc8c: f7f8 fd8c bl 80047a8 <HAL_GPIO_WritePin>
|
|
UNLOCK_SPI();
|
|
return ES_WIFI_ERROR_SPI_FAILED;
|
|
800bc90: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bc94: e02e b.n 800bcf4 <SPI_WIFI_ReceiveData+0xe0>
|
|
}
|
|
|
|
wait_spi_rx_event(timeout);
|
|
800bc96: 687b ldr r3, [r7, #4]
|
|
800bc98: 4618 mov r0, r3
|
|
800bc9a: f7ff ff7b bl 800bb94 <wait_spi_rx_event>
|
|
|
|
pData[0] = tmp[0];
|
|
800bc9e: 7d3a ldrb r2, [r7, #20]
|
|
800bca0: 68fb ldr r3, [r7, #12]
|
|
800bca2: 701a strb r2, [r3, #0]
|
|
pData[1] = tmp[1];
|
|
800bca4: 68fb ldr r3, [r7, #12]
|
|
800bca6: 3301 adds r3, #1
|
|
800bca8: 7d7a ldrb r2, [r7, #21]
|
|
800bcaa: 701a strb r2, [r3, #0]
|
|
length += 2;
|
|
800bcac: 8afb ldrh r3, [r7, #22]
|
|
800bcae: 3302 adds r3, #2
|
|
800bcb0: b29b uxth r3, r3
|
|
800bcb2: 82fb strh r3, [r7, #22]
|
|
pData += 2;
|
|
800bcb4: 68fb ldr r3, [r7, #12]
|
|
800bcb6: 3302 adds r3, #2
|
|
800bcb8: 60fb str r3, [r7, #12]
|
|
|
|
if (length >= ES_WIFI_DATA_SIZE) {
|
|
800bcba: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
800bcbe: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0
|
|
800bcc2: db09 blt.n 800bcd8 <SPI_WIFI_ReceiveData+0xc4>
|
|
WIFI_DISABLE_NSS();
|
|
800bcc4: 2201 movs r2, #1
|
|
800bcc6: 2101 movs r1, #1
|
|
800bcc8: 480c ldr r0, [pc, #48] @ (800bcfc <SPI_WIFI_ReceiveData+0xe8>)
|
|
800bcca: f7f8 fd6d bl 80047a8 <HAL_GPIO_WritePin>
|
|
SPI_WIFI_ResetModule();
|
|
800bcce: f7ff fea5 bl 800ba1c <SPI_WIFI_ResetModule>
|
|
UNLOCK_SPI();
|
|
return ES_WIFI_ERROR_STUFFING_FOREVER;
|
|
800bcd2: f06f 0303 mvn.w r3, #3
|
|
800bcd6: e00d b.n 800bcf4 <SPI_WIFI_ReceiveData+0xe0>
|
|
while (WIFI_IS_CMDDATA_READY())
|
|
800bcd8: 2102 movs r1, #2
|
|
800bcda: 4808 ldr r0, [pc, #32] @ (800bcfc <SPI_WIFI_ReceiveData+0xe8>)
|
|
800bcdc: f7f8 fd4c bl 8004778 <HAL_GPIO_ReadPin>
|
|
800bce0: 4603 mov r3, r0
|
|
800bce2: 2b01 cmp r3, #1
|
|
800bce4: d0ba beq.n 800bc5c <SPI_WIFI_ReceiveData+0x48>
|
|
else
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
WIFI_DISABLE_NSS();
|
|
800bce6: 2201 movs r2, #1
|
|
800bce8: 2101 movs r1, #1
|
|
800bcea: 4804 ldr r0, [pc, #16] @ (800bcfc <SPI_WIFI_ReceiveData+0xe8>)
|
|
800bcec: f7f8 fd5c bl 80047a8 <HAL_GPIO_WritePin>
|
|
UNLOCK_SPI();
|
|
return length;
|
|
800bcf0: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
}
|
|
800bcf4: 4618 mov r0, r3
|
|
800bcf6: 3718 adds r7, #24
|
|
800bcf8: 46bd mov sp, r7
|
|
800bcfa: bd80 pop {r7, pc}
|
|
800bcfc: 48001000 .word 0x48001000
|
|
800bd00: 20001374 .word 0x20001374
|
|
800bd04: 20001310 .word 0x20001310
|
|
|
|
0800bd08 <SPI_WIFI_SendData>:
|
|
* @param len : Data length
|
|
* @param timeout : send timeout in mS
|
|
* @retval Length of sent data
|
|
*/
|
|
int16_t SPI_WIFI_SendData( uint8_t *pdata, uint16_t len, uint32_t timeout)
|
|
{
|
|
800bd08: b580 push {r7, lr}
|
|
800bd0a: b086 sub sp, #24
|
|
800bd0c: af00 add r7, sp, #0
|
|
800bd0e: 60f8 str r0, [r7, #12]
|
|
800bd10: 460b mov r3, r1
|
|
800bd12: 607a str r2, [r7, #4]
|
|
800bd14: 817b strh r3, [r7, #10]
|
|
uint8_t Padding[2];
|
|
|
|
if (wait_cmddata_rdy_high(timeout)<0)
|
|
800bd16: 687b ldr r3, [r7, #4]
|
|
800bd18: 4618 mov r0, r3
|
|
800bd1a: f7ff fef9 bl 800bb10 <wait_cmddata_rdy_high>
|
|
800bd1e: 4603 mov r3, r0
|
|
800bd20: 2b00 cmp r3, #0
|
|
800bd22: da02 bge.n 800bd2a <SPI_WIFI_SendData+0x22>
|
|
{
|
|
return ES_WIFI_ERROR_SPI_FAILED;
|
|
800bd24: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bd28: e04f b.n 800bdca <SPI_WIFI_SendData+0xc2>
|
|
}
|
|
|
|
/* arm to detect rising event */
|
|
cmddata_rdy_rising_event=1;
|
|
800bd2a: 4b2a ldr r3, [pc, #168] @ (800bdd4 <SPI_WIFI_SendData+0xcc>)
|
|
800bd2c: 2201 movs r2, #1
|
|
800bd2e: 601a str r2, [r3, #0]
|
|
LOCK_SPI();
|
|
WIFI_ENABLE_NSS();
|
|
800bd30: 2200 movs r2, #0
|
|
800bd32: 2101 movs r1, #1
|
|
800bd34: 4828 ldr r0, [pc, #160] @ (800bdd8 <SPI_WIFI_SendData+0xd0>)
|
|
800bd36: f7f8 fd37 bl 80047a8 <HAL_GPIO_WritePin>
|
|
SPI_WIFI_DelayUs(15);
|
|
800bd3a: 200f movs r0, #15
|
|
800bd3c: f000 f85e bl 800bdfc <SPI_WIFI_DelayUs>
|
|
if (len > 1)
|
|
800bd40: 897b ldrh r3, [r7, #10]
|
|
800bd42: 2b01 cmp r3, #1
|
|
800bd44: d919 bls.n 800bd7a <SPI_WIFI_SendData+0x72>
|
|
{
|
|
spi_tx_event=1;
|
|
800bd46: 4b25 ldr r3, [pc, #148] @ (800bddc <SPI_WIFI_SendData+0xd4>)
|
|
800bd48: 2201 movs r2, #1
|
|
800bd4a: 601a str r2, [r3, #0]
|
|
if( HAL_SPI_Transmit_IT(&hspi, (uint8_t *)pdata , len/2) != HAL_OK)
|
|
800bd4c: 897b ldrh r3, [r7, #10]
|
|
800bd4e: 085b lsrs r3, r3, #1
|
|
800bd50: b29b uxth r3, r3
|
|
800bd52: 461a mov r2, r3
|
|
800bd54: 68f9 ldr r1, [r7, #12]
|
|
800bd56: 4822 ldr r0, [pc, #136] @ (800bde0 <SPI_WIFI_SendData+0xd8>)
|
|
800bd58: f7fb fd3a bl 80077d0 <HAL_SPI_Transmit_IT>
|
|
800bd5c: 4603 mov r3, r0
|
|
800bd5e: 2b00 cmp r3, #0
|
|
800bd60: d007 beq.n 800bd72 <SPI_WIFI_SendData+0x6a>
|
|
{
|
|
WIFI_DISABLE_NSS();
|
|
800bd62: 2201 movs r2, #1
|
|
800bd64: 2101 movs r1, #1
|
|
800bd66: 481c ldr r0, [pc, #112] @ (800bdd8 <SPI_WIFI_SendData+0xd0>)
|
|
800bd68: f7f8 fd1e bl 80047a8 <HAL_GPIO_WritePin>
|
|
UNLOCK_SPI();
|
|
return ES_WIFI_ERROR_SPI_FAILED;
|
|
800bd6c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bd70: e02b b.n 800bdca <SPI_WIFI_SendData+0xc2>
|
|
}
|
|
wait_spi_tx_event(timeout);
|
|
800bd72: 687b ldr r3, [r7, #4]
|
|
800bd74: 4618 mov r0, r3
|
|
800bd76: f7ff ff2d bl 800bbd4 <wait_spi_tx_event>
|
|
}
|
|
|
|
if ( len & 1)
|
|
800bd7a: 897b ldrh r3, [r7, #10]
|
|
800bd7c: f003 0301 and.w r3, r3, #1
|
|
800bd80: 2b00 cmp r3, #0
|
|
800bd82: d020 beq.n 800bdc6 <SPI_WIFI_SendData+0xbe>
|
|
{
|
|
Padding[0] = pdata[len-1];
|
|
800bd84: 897b ldrh r3, [r7, #10]
|
|
800bd86: 3b01 subs r3, #1
|
|
800bd88: 68fa ldr r2, [r7, #12]
|
|
800bd8a: 4413 add r3, r2
|
|
800bd8c: 781b ldrb r3, [r3, #0]
|
|
800bd8e: 753b strb r3, [r7, #20]
|
|
Padding[1] = '\n';
|
|
800bd90: 230a movs r3, #10
|
|
800bd92: 757b strb r3, [r7, #21]
|
|
|
|
spi_tx_event=1;
|
|
800bd94: 4b11 ldr r3, [pc, #68] @ (800bddc <SPI_WIFI_SendData+0xd4>)
|
|
800bd96: 2201 movs r2, #1
|
|
800bd98: 601a str r2, [r3, #0]
|
|
if( HAL_SPI_Transmit_IT(&hspi, Padding, 1) != HAL_OK)
|
|
800bd9a: f107 0314 add.w r3, r7, #20
|
|
800bd9e: 2201 movs r2, #1
|
|
800bda0: 4619 mov r1, r3
|
|
800bda2: 480f ldr r0, [pc, #60] @ (800bde0 <SPI_WIFI_SendData+0xd8>)
|
|
800bda4: f7fb fd14 bl 80077d0 <HAL_SPI_Transmit_IT>
|
|
800bda8: 4603 mov r3, r0
|
|
800bdaa: 2b00 cmp r3, #0
|
|
800bdac: d007 beq.n 800bdbe <SPI_WIFI_SendData+0xb6>
|
|
{
|
|
WIFI_DISABLE_NSS();
|
|
800bdae: 2201 movs r2, #1
|
|
800bdb0: 2101 movs r1, #1
|
|
800bdb2: 4809 ldr r0, [pc, #36] @ (800bdd8 <SPI_WIFI_SendData+0xd0>)
|
|
800bdb4: f7f8 fcf8 bl 80047a8 <HAL_GPIO_WritePin>
|
|
UNLOCK_SPI();
|
|
return ES_WIFI_ERROR_SPI_FAILED;
|
|
800bdb8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800bdbc: e005 b.n 800bdca <SPI_WIFI_SendData+0xc2>
|
|
}
|
|
wait_spi_tx_event(timeout);
|
|
800bdbe: 687b ldr r3, [r7, #4]
|
|
800bdc0: 4618 mov r0, r3
|
|
800bdc2: f7ff ff07 bl 800bbd4 <wait_spi_tx_event>
|
|
|
|
}
|
|
return len;
|
|
800bdc6: f9b7 300a ldrsh.w r3, [r7, #10]
|
|
}
|
|
800bdca: 4618 mov r0, r3
|
|
800bdcc: 3718 adds r7, #24
|
|
800bdce: 46bd mov sp, r7
|
|
800bdd0: bd80 pop {r7, pc}
|
|
800bdd2: bf00 nop
|
|
800bdd4: 2000137c .word 0x2000137c
|
|
800bdd8: 48001000 .word 0x48001000
|
|
800bddc: 20001378 .word 0x20001378
|
|
800bde0: 20001310 .word 0x20001310
|
|
|
|
0800bde4 <SPI_WIFI_Delay>:
|
|
* @brief Delay
|
|
* @param Delay in ms
|
|
* @retval None
|
|
*/
|
|
void SPI_WIFI_Delay(uint32_t Delay)
|
|
{
|
|
800bde4: b580 push {r7, lr}
|
|
800bde6: b082 sub sp, #8
|
|
800bde8: af00 add r7, sp, #0
|
|
800bdea: 6078 str r0, [r7, #4]
|
|
HAL_Delay(Delay);
|
|
800bdec: 6878 ldr r0, [r7, #4]
|
|
800bdee: f7f7 ff93 bl 8003d18 <HAL_Delay>
|
|
}
|
|
800bdf2: bf00 nop
|
|
800bdf4: 3708 adds r7, #8
|
|
800bdf6: 46bd mov sp, r7
|
|
800bdf8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800bdfc <SPI_WIFI_DelayUs>:
|
|
* @brief Delay
|
|
* @param Delay in us
|
|
* @retval None
|
|
*/
|
|
void SPI_WIFI_DelayUs(uint32_t n)
|
|
{
|
|
800bdfc: b580 push {r7, lr}
|
|
800bdfe: b086 sub sp, #24
|
|
800be00: af00 add r7, sp, #0
|
|
800be02: 6078 str r0, [r7, #4]
|
|
volatile uint32_t ct = 0;
|
|
800be04: 2300 movs r3, #0
|
|
800be06: 60bb str r3, [r7, #8]
|
|
uint32_t loop_per_us = 0;
|
|
800be08: 2300 movs r3, #0
|
|
800be0a: 617b str r3, [r7, #20]
|
|
static uint32_t cycle_per_loop = 0;
|
|
|
|
/* calibration happen on first call for a duration of 1 ms * nbcycle per loop */
|
|
/* 10 cycle for STM32L4 */
|
|
if (cycle_per_loop == 0 )
|
|
800be0c: 4b20 ldr r3, [pc, #128] @ (800be90 <SPI_WIFI_DelayUs+0x94>)
|
|
800be0e: 681b ldr r3, [r3, #0]
|
|
800be10: 2b00 cmp r3, #0
|
|
800be12: d122 bne.n 800be5a <SPI_WIFI_DelayUs+0x5e>
|
|
{
|
|
uint32_t cycle_per_ms = (SystemCoreClock/1000UL);
|
|
800be14: 4b1f ldr r3, [pc, #124] @ (800be94 <SPI_WIFI_DelayUs+0x98>)
|
|
800be16: 681b ldr r3, [r3, #0]
|
|
800be18: 4a1f ldr r2, [pc, #124] @ (800be98 <SPI_WIFI_DelayUs+0x9c>)
|
|
800be1a: fba2 2303 umull r2, r3, r2, r3
|
|
800be1e: 099b lsrs r3, r3, #6
|
|
800be20: 613b str r3, [r7, #16]
|
|
uint32_t t = 0;
|
|
800be22: 2300 movs r3, #0
|
|
800be24: 60fb str r3, [r7, #12]
|
|
ct = cycle_per_ms;
|
|
800be26: 693b ldr r3, [r7, #16]
|
|
800be28: 60bb str r3, [r7, #8]
|
|
t = HAL_GetTick();
|
|
800be2a: f7f7 ff69 bl 8003d00 <HAL_GetTick>
|
|
800be2e: 60f8 str r0, [r7, #12]
|
|
while(ct) ct--;
|
|
800be30: e002 b.n 800be38 <SPI_WIFI_DelayUs+0x3c>
|
|
800be32: 68bb ldr r3, [r7, #8]
|
|
800be34: 3b01 subs r3, #1
|
|
800be36: 60bb str r3, [r7, #8]
|
|
800be38: 68bb ldr r3, [r7, #8]
|
|
800be3a: 2b00 cmp r3, #0
|
|
800be3c: d1f9 bne.n 800be32 <SPI_WIFI_DelayUs+0x36>
|
|
cycle_per_loop = HAL_GetTick()-t;
|
|
800be3e: f7f7 ff5f bl 8003d00 <HAL_GetTick>
|
|
800be42: 4602 mov r2, r0
|
|
800be44: 68fb ldr r3, [r7, #12]
|
|
800be46: 1ad3 subs r3, r2, r3
|
|
800be48: 4a11 ldr r2, [pc, #68] @ (800be90 <SPI_WIFI_DelayUs+0x94>)
|
|
800be4a: 6013 str r3, [r2, #0]
|
|
if (cycle_per_loop == 0) cycle_per_loop = 1;
|
|
800be4c: 4b10 ldr r3, [pc, #64] @ (800be90 <SPI_WIFI_DelayUs+0x94>)
|
|
800be4e: 681b ldr r3, [r3, #0]
|
|
800be50: 2b00 cmp r3, #0
|
|
800be52: d102 bne.n 800be5a <SPI_WIFI_DelayUs+0x5e>
|
|
800be54: 4b0e ldr r3, [pc, #56] @ (800be90 <SPI_WIFI_DelayUs+0x94>)
|
|
800be56: 2201 movs r2, #1
|
|
800be58: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
loop_per_us = SystemCoreClock/1000000UL/cycle_per_loop;
|
|
800be5a: 4b0e ldr r3, [pc, #56] @ (800be94 <SPI_WIFI_DelayUs+0x98>)
|
|
800be5c: 681b ldr r3, [r3, #0]
|
|
800be5e: 4a0f ldr r2, [pc, #60] @ (800be9c <SPI_WIFI_DelayUs+0xa0>)
|
|
800be60: fba2 2303 umull r2, r3, r2, r3
|
|
800be64: 0c9a lsrs r2, r3, #18
|
|
800be66: 4b0a ldr r3, [pc, #40] @ (800be90 <SPI_WIFI_DelayUs+0x94>)
|
|
800be68: 681b ldr r3, [r3, #0]
|
|
800be6a: fbb2 f3f3 udiv r3, r2, r3
|
|
800be6e: 617b str r3, [r7, #20]
|
|
ct = n * loop_per_us;
|
|
800be70: 687b ldr r3, [r7, #4]
|
|
800be72: 697a ldr r2, [r7, #20]
|
|
800be74: fb02 f303 mul.w r3, r2, r3
|
|
800be78: 60bb str r3, [r7, #8]
|
|
while(ct) ct--;
|
|
800be7a: e002 b.n 800be82 <SPI_WIFI_DelayUs+0x86>
|
|
800be7c: 68bb ldr r3, [r7, #8]
|
|
800be7e: 3b01 subs r3, #1
|
|
800be80: 60bb str r3, [r7, #8]
|
|
800be82: 68bb ldr r3, [r7, #8]
|
|
800be84: 2b00 cmp r3, #0
|
|
800be86: d1f9 bne.n 800be7c <SPI_WIFI_DelayUs+0x80>
|
|
return;
|
|
800be88: bf00 nop
|
|
}
|
|
800be8a: 3718 adds r7, #24
|
|
800be8c: 46bd mov sp, r7
|
|
800be8e: bd80 pop {r7, pc}
|
|
800be90: 20001380 .word 0x20001380
|
|
800be94: 200000c4 .word 0x200000c4
|
|
800be98: 10624dd3 .word 0x10624dd3
|
|
800be9c: 431bde83 .word 0x431bde83
|
|
|
|
0800bea0 <HAL_SPI_RxCpltCallback>:
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
|
|
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800bea0: b480 push {r7}
|
|
800bea2: b083 sub sp, #12
|
|
800bea4: af00 add r7, sp, #0
|
|
800bea6: 6078 str r0, [r7, #4]
|
|
if (spi_rx_event)
|
|
800bea8: 4b06 ldr r3, [pc, #24] @ (800bec4 <HAL_SPI_RxCpltCallback+0x24>)
|
|
800beaa: 681b ldr r3, [r3, #0]
|
|
800beac: 2b00 cmp r3, #0
|
|
800beae: d002 beq.n 800beb6 <HAL_SPI_RxCpltCallback+0x16>
|
|
{
|
|
SEM_SIGNAL(spi_rx_sem);
|
|
spi_rx_event = 0;
|
|
800beb0: 4b04 ldr r3, [pc, #16] @ (800bec4 <HAL_SPI_RxCpltCallback+0x24>)
|
|
800beb2: 2200 movs r2, #0
|
|
800beb4: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
800beb6: bf00 nop
|
|
800beb8: 370c adds r7, #12
|
|
800beba: 46bd mov sp, r7
|
|
800bebc: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bec0: 4770 bx lr
|
|
800bec2: bf00 nop
|
|
800bec4: 20001374 .word 0x20001374
|
|
|
|
0800bec8 <HAL_SPI_TxCpltCallback>:
|
|
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800bec8: b480 push {r7}
|
|
800beca: b083 sub sp, #12
|
|
800becc: af00 add r7, sp, #0
|
|
800bece: 6078 str r0, [r7, #4]
|
|
if (spi_tx_event)
|
|
800bed0: 4b06 ldr r3, [pc, #24] @ (800beec <HAL_SPI_TxCpltCallback+0x24>)
|
|
800bed2: 681b ldr r3, [r3, #0]
|
|
800bed4: 2b00 cmp r3, #0
|
|
800bed6: d002 beq.n 800bede <HAL_SPI_TxCpltCallback+0x16>
|
|
{
|
|
SEM_SIGNAL(spi_tx_sem);
|
|
spi_tx_event = 0;
|
|
800bed8: 4b04 ldr r3, [pc, #16] @ (800beec <HAL_SPI_TxCpltCallback+0x24>)
|
|
800beda: 2200 movs r2, #0
|
|
800bedc: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
800bede: bf00 nop
|
|
800bee0: 370c adds r7, #12
|
|
800bee2: 46bd mov sp, r7
|
|
800bee4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bee8: 4770 bx lr
|
|
800beea: bf00 nop
|
|
800beec: 20001378 .word 0x20001378
|
|
|
|
0800bef0 <SPI_WIFI_ISR>:
|
|
* @brief Interrupt handler for Data RDY signal
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI_WIFI_ISR(void)
|
|
{
|
|
800bef0: b480 push {r7}
|
|
800bef2: af00 add r7, sp, #0
|
|
if (cmddata_rdy_rising_event==1)
|
|
800bef4: 4b05 ldr r3, [pc, #20] @ (800bf0c <SPI_WIFI_ISR+0x1c>)
|
|
800bef6: 681b ldr r3, [r3, #0]
|
|
800bef8: 2b01 cmp r3, #1
|
|
800befa: d102 bne.n 800bf02 <SPI_WIFI_ISR+0x12>
|
|
{
|
|
SEM_SIGNAL(cmddata_rdy_rising_sem);
|
|
cmddata_rdy_rising_event = 0;
|
|
800befc: 4b03 ldr r3, [pc, #12] @ (800bf0c <SPI_WIFI_ISR+0x1c>)
|
|
800befe: 2200 movs r2, #0
|
|
800bf00: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
800bf02: bf00 nop
|
|
800bf04: 46bd mov sp, r7
|
|
800bf06: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bf0a: 4770 bx lr
|
|
800bf0c: 2000137c .word 0x2000137c
|
|
|
|
0800bf10 <WIFI_Init>:
|
|
* @brief Initialize the WIFI core
|
|
* @param None
|
|
* @retval Operation status
|
|
*/
|
|
WIFI_Status_t WIFI_Init(void)
|
|
{
|
|
800bf10: b580 push {r7, lr}
|
|
800bf12: b084 sub sp, #16
|
|
800bf14: af02 add r7, sp, #8
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800bf16: 2301 movs r3, #1
|
|
800bf18: 71fb strb r3, [r7, #7]
|
|
|
|
if(ES_WIFI_RegisterBusIO(&EsWifiObj,
|
|
800bf1a: 4b0d ldr r3, [pc, #52] @ (800bf50 <WIFI_Init+0x40>)
|
|
800bf1c: 9301 str r3, [sp, #4]
|
|
800bf1e: 4b0d ldr r3, [pc, #52] @ (800bf54 <WIFI_Init+0x44>)
|
|
800bf20: 9300 str r3, [sp, #0]
|
|
800bf22: 4b0d ldr r3, [pc, #52] @ (800bf58 <WIFI_Init+0x48>)
|
|
800bf24: 4a0d ldr r2, [pc, #52] @ (800bf5c <WIFI_Init+0x4c>)
|
|
800bf26: 490e ldr r1, [pc, #56] @ (800bf60 <WIFI_Init+0x50>)
|
|
800bf28: 480e ldr r0, [pc, #56] @ (800bf64 <WIFI_Init+0x54>)
|
|
800bf2a: f7fe ff1d bl 800ad68 <ES_WIFI_RegisterBusIO>
|
|
800bf2e: 4603 mov r3, r0
|
|
800bf30: 2b00 cmp r3, #0
|
|
800bf32: d107 bne.n 800bf44 <WIFI_Init+0x34>
|
|
SPI_WIFI_DeInit,
|
|
SPI_WIFI_Delay,
|
|
SPI_WIFI_SendData,
|
|
SPI_WIFI_ReceiveData) == ES_WIFI_STATUS_OK)
|
|
{
|
|
if(ES_WIFI_Init(&EsWifiObj) == ES_WIFI_STATUS_OK)
|
|
800bf34: 480b ldr r0, [pc, #44] @ (800bf64 <WIFI_Init+0x54>)
|
|
800bf36: f7fe fee9 bl 800ad0c <ES_WIFI_Init>
|
|
800bf3a: 4603 mov r3, r0
|
|
800bf3c: 2b00 cmp r3, #0
|
|
800bf3e: d101 bne.n 800bf44 <WIFI_Init+0x34>
|
|
{
|
|
ret = WIFI_STATUS_OK;
|
|
800bf40: 2300 movs r3, #0
|
|
800bf42: 71fb strb r3, [r7, #7]
|
|
}
|
|
}
|
|
return ret;
|
|
800bf44: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
800bf46: 4618 mov r0, r3
|
|
800bf48: 3708 adds r7, #8
|
|
800bf4a: 46bd mov sp, r7
|
|
800bf4c: bd80 pop {r7, pc}
|
|
800bf4e: bf00 nop
|
|
800bf50: 0800bc15 .word 0x0800bc15
|
|
800bf54: 0800bd09 .word 0x0800bd09
|
|
800bf58: 0800bde5 .word 0x0800bde5
|
|
800bf5c: 0800bafd .word 0x0800bafd
|
|
800bf60: 0800b961 .word 0x0800b961
|
|
800bf64: 20001384 .word 0x20001384
|
|
|
|
0800bf68 <WIFI_Connect>:
|
|
*/
|
|
WIFI_Status_t WIFI_Connect(
|
|
const char* SSID,
|
|
const char* Password,
|
|
WIFI_Ecn_t ecn)
|
|
{
|
|
800bf68: b580 push {r7, lr}
|
|
800bf6a: b086 sub sp, #24
|
|
800bf6c: af00 add r7, sp, #0
|
|
800bf6e: 60f8 str r0, [r7, #12]
|
|
800bf70: 60b9 str r1, [r7, #8]
|
|
800bf72: 4613 mov r3, r2
|
|
800bf74: 71fb strb r3, [r7, #7]
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800bf76: 2301 movs r3, #1
|
|
800bf78: 75fb strb r3, [r7, #23]
|
|
|
|
if(ES_WIFI_Connect(&EsWifiObj, SSID, Password, (ES_WIFI_SecurityType_t) ecn) == ES_WIFI_STATUS_OK)
|
|
800bf7a: 79fb ldrb r3, [r7, #7]
|
|
800bf7c: 68ba ldr r2, [r7, #8]
|
|
800bf7e: 68f9 ldr r1, [r7, #12]
|
|
800bf80: 4809 ldr r0, [pc, #36] @ (800bfa8 <WIFI_Connect+0x40>)
|
|
800bf82: f7fe ff25 bl 800add0 <ES_WIFI_Connect>
|
|
800bf86: 4603 mov r3, r0
|
|
800bf88: 2b00 cmp r3, #0
|
|
800bf8a: d107 bne.n 800bf9c <WIFI_Connect+0x34>
|
|
{
|
|
if(ES_WIFI_GetNetworkSettings(&EsWifiObj) == ES_WIFI_STATUS_OK)
|
|
800bf8c: 4806 ldr r0, [pc, #24] @ (800bfa8 <WIFI_Connect+0x40>)
|
|
800bf8e: f7fe ffc3 bl 800af18 <ES_WIFI_GetNetworkSettings>
|
|
800bf92: 4603 mov r3, r0
|
|
800bf94: 2b00 cmp r3, #0
|
|
800bf96: d101 bne.n 800bf9c <WIFI_Connect+0x34>
|
|
{
|
|
ret = WIFI_STATUS_OK;
|
|
800bf98: 2300 movs r3, #0
|
|
800bf9a: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
return ret;
|
|
800bf9c: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800bf9e: 4618 mov r0, r3
|
|
800bfa0: 3718 adds r7, #24
|
|
800bfa2: 46bd mov sp, r7
|
|
800bfa4: bd80 pop {r7, pc}
|
|
800bfa6: bf00 nop
|
|
800bfa8: 20001384 .word 0x20001384
|
|
|
|
0800bfac <WIFI_GetMAC_Address>:
|
|
/**
|
|
* @brief This function retrieves the WiFi interface's MAC address.
|
|
* @retval Operation Status.
|
|
*/
|
|
WIFI_Status_t WIFI_GetMAC_Address(uint8_t *mac)
|
|
{
|
|
800bfac: b580 push {r7, lr}
|
|
800bfae: b084 sub sp, #16
|
|
800bfb0: af00 add r7, sp, #0
|
|
800bfb2: 6078 str r0, [r7, #4]
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800bfb4: 2301 movs r3, #1
|
|
800bfb6: 73fb strb r3, [r7, #15]
|
|
|
|
if(ES_WIFI_GetMACAddress(&EsWifiObj, mac) == ES_WIFI_STATUS_OK)
|
|
800bfb8: 6879 ldr r1, [r7, #4]
|
|
800bfba: 4806 ldr r0, [pc, #24] @ (800bfd4 <WIFI_GetMAC_Address+0x28>)
|
|
800bfbc: f7fe ffd6 bl 800af6c <ES_WIFI_GetMACAddress>
|
|
800bfc0: 4603 mov r3, r0
|
|
800bfc2: 2b00 cmp r3, #0
|
|
800bfc4: d101 bne.n 800bfca <WIFI_GetMAC_Address+0x1e>
|
|
{
|
|
ret = WIFI_STATUS_OK;
|
|
800bfc6: 2300 movs r3, #0
|
|
800bfc8: 73fb strb r3, [r7, #15]
|
|
}
|
|
return ret;
|
|
800bfca: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800bfcc: 4618 mov r0, r3
|
|
800bfce: 3710 adds r7, #16
|
|
800bfd0: 46bd mov sp, r7
|
|
800bfd2: bd80 pop {r7, pc}
|
|
800bfd4: 20001384 .word 0x20001384
|
|
|
|
0800bfd8 <WIFI_GetIP_Address>:
|
|
/**
|
|
* @brief This function retrieves the WiFi interface's IP address.
|
|
* @retval Operation Status.
|
|
*/
|
|
WIFI_Status_t WIFI_GetIP_Address (uint8_t *ipaddr)
|
|
{
|
|
800bfd8: b580 push {r7, lr}
|
|
800bfda: b084 sub sp, #16
|
|
800bfdc: af00 add r7, sp, #0
|
|
800bfde: 6078 str r0, [r7, #4]
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800bfe0: 2301 movs r3, #1
|
|
800bfe2: 73fb strb r3, [r7, #15]
|
|
|
|
if (ES_WIFI_IsConnected(&EsWifiObj) == 1)
|
|
800bfe4: 4809 ldr r0, [pc, #36] @ (800c00c <WIFI_GetIP_Address+0x34>)
|
|
800bfe6: f7fe ff6b bl 800aec0 <ES_WIFI_IsConnected>
|
|
800bfea: 4603 mov r3, r0
|
|
800bfec: 2b01 cmp r3, #1
|
|
800bfee: d107 bne.n 800c000 <WIFI_GetIP_Address+0x28>
|
|
{
|
|
memcpy(ipaddr, EsWifiObj.NetSettings.IP_Addr, 4);
|
|
800bff0: 4b06 ldr r3, [pc, #24] @ (800c00c <WIFI_GetIP_Address+0x34>)
|
|
800bff2: f8d3 30d5 ldr.w r3, [r3, #213] @ 0xd5
|
|
800bff6: 461a mov r2, r3
|
|
800bff8: 687b ldr r3, [r7, #4]
|
|
800bffa: 601a str r2, [r3, #0]
|
|
ret = WIFI_STATUS_OK;
|
|
800bffc: 2300 movs r3, #0
|
|
800bffe: 73fb strb r3, [r7, #15]
|
|
}
|
|
return ret;
|
|
800c000: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800c002: 4618 mov r0, r3
|
|
800c004: 3710 adds r7, #16
|
|
800c006: 46bd mov sp, r7
|
|
800c008: bd80 pop {r7, pc}
|
|
800c00a: bf00 nop
|
|
800c00c: 20001384 .word 0x20001384
|
|
|
|
0800c010 <WIFI_StartServer>:
|
|
* @param name : name of the connection
|
|
* @param port : Remote port
|
|
* @retval Operation status
|
|
*/
|
|
WIFI_Status_t WIFI_StartServer(uint32_t socket, WIFI_Protocol_t protocol, uint16_t backlog ,const char *name, uint16_t port)
|
|
{
|
|
800c010: b580 push {r7, lr}
|
|
800c012: b08a sub sp, #40 @ 0x28
|
|
800c014: af00 add r7, sp, #0
|
|
800c016: 60f8 str r0, [r7, #12]
|
|
800c018: 607b str r3, [r7, #4]
|
|
800c01a: 460b mov r3, r1
|
|
800c01c: 72fb strb r3, [r7, #11]
|
|
800c01e: 4613 mov r3, r2
|
|
800c020: 813b strh r3, [r7, #8]
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800c022: 2301 movs r3, #1
|
|
800c024: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
ES_WIFI_Conn_t conn;
|
|
conn.Number = socket;
|
|
800c028: 68fb ldr r3, [r7, #12]
|
|
800c02a: b2db uxtb r3, r3
|
|
800c02c: 747b strb r3, [r7, #17]
|
|
conn.LocalPort = port;
|
|
800c02e: 8e3b ldrh r3, [r7, #48] @ 0x30
|
|
800c030: 82bb strh r3, [r7, #20]
|
|
conn.Type = (protocol == WIFI_TCP_PROTOCOL)? ES_WIFI_TCP_CONNECTION : ES_WIFI_UDP_CONNECTION;
|
|
800c032: 7afb ldrb r3, [r7, #11]
|
|
800c034: 2b00 cmp r3, #0
|
|
800c036: bf14 ite ne
|
|
800c038: 2301 movne r3, #1
|
|
800c03a: 2300 moveq r3, #0
|
|
800c03c: b2db uxtb r3, r3
|
|
800c03e: 743b strb r3, [r7, #16]
|
|
conn.Backlog = backlog;
|
|
800c040: 893b ldrh r3, [r7, #8]
|
|
800c042: b2db uxtb r3, r3
|
|
800c044: f887 3020 strb.w r3, [r7, #32]
|
|
if(ES_WIFI_StartServerSingleConn(&EsWifiObj, &conn)== ES_WIFI_STATUS_OK)
|
|
800c048: f107 0310 add.w r3, r7, #16
|
|
800c04c: 4619 mov r1, r3
|
|
800c04e: 4807 ldr r0, [pc, #28] @ (800c06c <WIFI_StartServer+0x5c>)
|
|
800c050: f7fe ffbe bl 800afd0 <ES_WIFI_StartServerSingleConn>
|
|
800c054: 4603 mov r3, r0
|
|
800c056: 2b00 cmp r3, #0
|
|
800c058: d102 bne.n 800c060 <WIFI_StartServer+0x50>
|
|
{
|
|
ret = WIFI_STATUS_OK;
|
|
800c05a: 2300 movs r3, #0
|
|
800c05c: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
return ret;
|
|
800c060: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
800c064: 4618 mov r0, r3
|
|
800c066: 3728 adds r7, #40 @ 0x28
|
|
800c068: 46bd mov sp, r7
|
|
800c06a: bd80 pop {r7, pc}
|
|
800c06c: 20001384 .word 0x20001384
|
|
|
|
0800c070 <WIFI_WaitServerConnection>:
|
|
* @brief Wait for a client connection to the server
|
|
* @param socket : socket
|
|
* @retval Operation status
|
|
*/
|
|
WIFI_Status_t WIFI_WaitServerConnection(int socket,uint32_t Timeout,uint8_t *RemoteIp,uint16_t *RemotePort)
|
|
{
|
|
800c070: b580 push {r7, lr}
|
|
800c072: b08a sub sp, #40 @ 0x28
|
|
800c074: af00 add r7, sp, #0
|
|
800c076: 60f8 str r0, [r7, #12]
|
|
800c078: 60b9 str r1, [r7, #8]
|
|
800c07a: 607a str r2, [r7, #4]
|
|
800c07c: 603b str r3, [r7, #0]
|
|
ES_WIFI_Conn_t conn;
|
|
ES_WIFI_Status_t ret;
|
|
|
|
conn.Number = socket;
|
|
800c07e: 68fb ldr r3, [r7, #12]
|
|
800c080: b2db uxtb r3, r3
|
|
800c082: 747b strb r3, [r7, #17]
|
|
|
|
ret = ES_WIFI_WaitServerConnection(&EsWifiObj,Timeout,&conn);
|
|
800c084: f107 0310 add.w r3, r7, #16
|
|
800c088: 461a mov r2, r3
|
|
800c08a: 68b9 ldr r1, [r7, #8]
|
|
800c08c: 4819 ldr r0, [pc, #100] @ (800c0f4 <WIFI_WaitServerConnection+0x84>)
|
|
800c08e: f7ff f84b bl 800b128 <ES_WIFI_WaitServerConnection>
|
|
800c092: 4603 mov r3, r0
|
|
800c094: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
|
|
if (ES_WIFI_STATUS_OK == ret)
|
|
800c098: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800c09c: 2b00 cmp r3, #0
|
|
800c09e: d10f bne.n 800c0c0 <WIFI_WaitServerConnection+0x50>
|
|
{
|
|
if (RemotePort) *RemotePort=conn.RemotePort;
|
|
800c0a0: 683b ldr r3, [r7, #0]
|
|
800c0a2: 2b00 cmp r3, #0
|
|
800c0a4: d002 beq.n 800c0ac <WIFI_WaitServerConnection+0x3c>
|
|
800c0a6: 8a7a ldrh r2, [r7, #18]
|
|
800c0a8: 683b ldr r3, [r7, #0]
|
|
800c0aa: 801a strh r2, [r3, #0]
|
|
if (RemoteIp)
|
|
800c0ac: 687b ldr r3, [r7, #4]
|
|
800c0ae: 2b00 cmp r3, #0
|
|
800c0b0: d004 beq.n 800c0bc <WIFI_WaitServerConnection+0x4c>
|
|
{
|
|
memcpy(RemoteIp,conn.RemoteIP,sizeof(conn.RemoteIP));
|
|
800c0b2: f8d7 3016 ldr.w r3, [r7, #22]
|
|
800c0b6: 461a mov r2, r3
|
|
800c0b8: 687b ldr r3, [r7, #4]
|
|
800c0ba: 601a str r2, [r3, #0]
|
|
}
|
|
return WIFI_STATUS_OK;
|
|
800c0bc: 2300 movs r3, #0
|
|
800c0be: e014 b.n 800c0ea <WIFI_WaitServerConnection+0x7a>
|
|
}
|
|
|
|
if (ES_WIFI_STATUS_TIMEOUT ==ret)
|
|
800c0c0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800c0c4: 2b03 cmp r3, #3
|
|
800c0c6: d10f bne.n 800c0e8 <WIFI_WaitServerConnection+0x78>
|
|
{
|
|
if (RemotePort) *RemotePort=0;
|
|
800c0c8: 683b ldr r3, [r7, #0]
|
|
800c0ca: 2b00 cmp r3, #0
|
|
800c0cc: d002 beq.n 800c0d4 <WIFI_WaitServerConnection+0x64>
|
|
800c0ce: 683b ldr r3, [r7, #0]
|
|
800c0d0: 2200 movs r2, #0
|
|
800c0d2: 801a strh r2, [r3, #0]
|
|
if (RemoteIp)
|
|
800c0d4: 687b ldr r3, [r7, #4]
|
|
800c0d6: 2b00 cmp r3, #0
|
|
800c0d8: d004 beq.n 800c0e4 <WIFI_WaitServerConnection+0x74>
|
|
{
|
|
memset(RemoteIp,0,sizeof(conn.RemoteIP));
|
|
800c0da: 2204 movs r2, #4
|
|
800c0dc: 2100 movs r1, #0
|
|
800c0de: 6878 ldr r0, [r7, #4]
|
|
800c0e0: f004 f9f2 bl 80104c8 <memset>
|
|
}
|
|
return WIFI_STATUS_TIMEOUT;
|
|
800c0e4: 2305 movs r3, #5
|
|
800c0e6: e000 b.n 800c0ea <WIFI_WaitServerConnection+0x7a>
|
|
}
|
|
|
|
return WIFI_STATUS_ERROR;
|
|
800c0e8: 2301 movs r3, #1
|
|
}
|
|
800c0ea: 4618 mov r0, r3
|
|
800c0ec: 3728 adds r7, #40 @ 0x28
|
|
800c0ee: 46bd mov sp, r7
|
|
800c0f0: bd80 pop {r7, pc}
|
|
800c0f2: bf00 nop
|
|
800c0f4: 20001384 .word 0x20001384
|
|
|
|
0800c0f8 <WIFI_CloseServerConnection>:
|
|
/**
|
|
* @brief Close current connection from a client to the server
|
|
* @retval Operation status
|
|
*/
|
|
WIFI_Status_t WIFI_CloseServerConnection(int socket)
|
|
{
|
|
800c0f8: b580 push {r7, lr}
|
|
800c0fa: b084 sub sp, #16
|
|
800c0fc: af00 add r7, sp, #0
|
|
800c0fe: 6078 str r0, [r7, #4]
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800c100: 2301 movs r3, #1
|
|
800c102: 73fb strb r3, [r7, #15]
|
|
if (ES_WIFI_STATUS_OK == ES_WIFI_CloseServerConnection(&EsWifiObj,socket))
|
|
800c104: 6879 ldr r1, [r7, #4]
|
|
800c106: 4806 ldr r0, [pc, #24] @ (800c120 <WIFI_CloseServerConnection+0x28>)
|
|
800c108: f7ff f930 bl 800b36c <ES_WIFI_CloseServerConnection>
|
|
800c10c: 4603 mov r3, r0
|
|
800c10e: 2b00 cmp r3, #0
|
|
800c110: d101 bne.n 800c116 <WIFI_CloseServerConnection+0x1e>
|
|
{
|
|
ret = WIFI_STATUS_OK;
|
|
800c112: 2300 movs r3, #0
|
|
800c114: 73fb strb r3, [r7, #15]
|
|
}
|
|
return ret;
|
|
800c116: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800c118: 4618 mov r0, r3
|
|
800c11a: 3710 adds r7, #16
|
|
800c11c: 46bd mov sp, r7
|
|
800c11e: bd80 pop {r7, pc}
|
|
800c120: 20001384 .word 0x20001384
|
|
|
|
0800c124 <WIFI_StopServer>:
|
|
* @brief Stop a server
|
|
* @param socket : socket
|
|
* @retval Operation status
|
|
*/
|
|
WIFI_Status_t WIFI_StopServer(uint32_t socket)
|
|
{
|
|
800c124: b580 push {r7, lr}
|
|
800c126: b084 sub sp, #16
|
|
800c128: af00 add r7, sp, #0
|
|
800c12a: 6078 str r0, [r7, #4]
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800c12c: 2301 movs r3, #1
|
|
800c12e: 73fb strb r3, [r7, #15]
|
|
|
|
if(ES_WIFI_StopServerSingleConn(&EsWifiObj,socket)== ES_WIFI_STATUS_OK)
|
|
800c130: 687b ldr r3, [r7, #4]
|
|
800c132: 4619 mov r1, r3
|
|
800c134: 4806 ldr r0, [pc, #24] @ (800c150 <WIFI_StopServer+0x2c>)
|
|
800c136: f7ff f979 bl 800b42c <ES_WIFI_StopServerSingleConn>
|
|
800c13a: 4603 mov r3, r0
|
|
800c13c: 2b00 cmp r3, #0
|
|
800c13e: d101 bne.n 800c144 <WIFI_StopServer+0x20>
|
|
{
|
|
ret = WIFI_STATUS_OK;
|
|
800c140: 2300 movs r3, #0
|
|
800c142: 73fb strb r3, [r7, #15]
|
|
}
|
|
return ret;
|
|
800c144: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800c146: 4618 mov r0, r3
|
|
800c148: 3710 adds r7, #16
|
|
800c14a: 46bd mov sp, r7
|
|
800c14c: bd80 pop {r7, pc}
|
|
800c14e: bf00 nop
|
|
800c150: 20001384 .word 0x20001384
|
|
|
|
0800c154 <WIFI_SendData>:
|
|
* @param SentDatalen : (OUT) length actually sent
|
|
* @param Timeout : Socket write timeout (ms)
|
|
* @retval Operation status
|
|
*/
|
|
WIFI_Status_t WIFI_SendData(uint8_t socket, uint8_t *pdata, uint16_t Reqlen, uint16_t *SentDatalen, uint32_t Timeout)
|
|
{
|
|
800c154: b580 push {r7, lr}
|
|
800c156: b088 sub sp, #32
|
|
800c158: af02 add r7, sp, #8
|
|
800c15a: 60b9 str r1, [r7, #8]
|
|
800c15c: 607b str r3, [r7, #4]
|
|
800c15e: 4603 mov r3, r0
|
|
800c160: 73fb strb r3, [r7, #15]
|
|
800c162: 4613 mov r3, r2
|
|
800c164: 81bb strh r3, [r7, #12]
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800c166: 2301 movs r3, #1
|
|
800c168: 75fb strb r3, [r7, #23]
|
|
|
|
if(ES_WIFI_SendData(&EsWifiObj, socket, pdata, Reqlen, SentDatalen, Timeout) == ES_WIFI_STATUS_OK)
|
|
800c16a: 89ba ldrh r2, [r7, #12]
|
|
800c16c: 7bf9 ldrb r1, [r7, #15]
|
|
800c16e: 6a3b ldr r3, [r7, #32]
|
|
800c170: 9301 str r3, [sp, #4]
|
|
800c172: 687b ldr r3, [r7, #4]
|
|
800c174: 9300 str r3, [sp, #0]
|
|
800c176: 4613 mov r3, r2
|
|
800c178: 68ba ldr r2, [r7, #8]
|
|
800c17a: 4806 ldr r0, [pc, #24] @ (800c194 <WIFI_SendData+0x40>)
|
|
800c17c: f7ff f9b8 bl 800b4f0 <ES_WIFI_SendData>
|
|
800c180: 4603 mov r3, r0
|
|
800c182: 2b00 cmp r3, #0
|
|
800c184: d101 bne.n 800c18a <WIFI_SendData+0x36>
|
|
{
|
|
ret = WIFI_STATUS_OK;
|
|
800c186: 2300 movs r3, #0
|
|
800c188: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return ret;
|
|
800c18a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800c18c: 4618 mov r0, r3
|
|
800c18e: 3718 adds r7, #24
|
|
800c190: 46bd mov sp, r7
|
|
800c192: bd80 pop {r7, pc}
|
|
800c194: 20001384 .word 0x20001384
|
|
|
|
0800c198 <WIFI_ReceiveData>:
|
|
* @param RcvDatalen : (OUT) length of the data actually received
|
|
* @param Timeout : Socket read timeout (ms)
|
|
* @retval Operation status
|
|
*/
|
|
WIFI_Status_t WIFI_ReceiveData(uint8_t socket, uint8_t *pdata, uint16_t Reqlen, uint16_t *RcvDatalen, uint32_t Timeout)
|
|
{
|
|
800c198: b580 push {r7, lr}
|
|
800c19a: b088 sub sp, #32
|
|
800c19c: af02 add r7, sp, #8
|
|
800c19e: 60b9 str r1, [r7, #8]
|
|
800c1a0: 607b str r3, [r7, #4]
|
|
800c1a2: 4603 mov r3, r0
|
|
800c1a4: 73fb strb r3, [r7, #15]
|
|
800c1a6: 4613 mov r3, r2
|
|
800c1a8: 81bb strh r3, [r7, #12]
|
|
WIFI_Status_t ret = WIFI_STATUS_ERROR;
|
|
800c1aa: 2301 movs r3, #1
|
|
800c1ac: 75fb strb r3, [r7, #23]
|
|
|
|
if(ES_WIFI_ReceiveData(&EsWifiObj, socket, pdata, Reqlen, RcvDatalen, Timeout) == ES_WIFI_STATUS_OK)
|
|
800c1ae: 89ba ldrh r2, [r7, #12]
|
|
800c1b0: 7bf9 ldrb r1, [r7, #15]
|
|
800c1b2: 6a3b ldr r3, [r7, #32]
|
|
800c1b4: 9301 str r3, [sp, #4]
|
|
800c1b6: 687b ldr r3, [r7, #4]
|
|
800c1b8: 9300 str r3, [sp, #0]
|
|
800c1ba: 4613 mov r3, r2
|
|
800c1bc: 68ba ldr r2, [r7, #8]
|
|
800c1be: 4806 ldr r0, [pc, #24] @ (800c1d8 <WIFI_ReceiveData+0x40>)
|
|
800c1c0: f7ff fa52 bl 800b668 <ES_WIFI_ReceiveData>
|
|
800c1c4: 4603 mov r3, r0
|
|
800c1c6: 2b00 cmp r3, #0
|
|
800c1c8: d101 bne.n 800c1ce <WIFI_ReceiveData+0x36>
|
|
{
|
|
ret = WIFI_STATUS_OK;
|
|
800c1ca: 2300 movs r3, #0
|
|
800c1cc: 75fb strb r3, [r7, #23]
|
|
}
|
|
return ret;
|
|
800c1ce: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800c1d0: 4618 mov r0, r3
|
|
800c1d2: 3718 adds r7, #24
|
|
800c1d4: 46bd mov sp, r7
|
|
800c1d6: bd80 pop {r7, pc}
|
|
800c1d8: 20001384 .word 0x20001384
|
|
|
|
0800c1dc <__NVIC_SetPriority>:
|
|
{
|
|
800c1dc: b480 push {r7}
|
|
800c1de: b083 sub sp, #12
|
|
800c1e0: af00 add r7, sp, #0
|
|
800c1e2: 4603 mov r3, r0
|
|
800c1e4: 6039 str r1, [r7, #0]
|
|
800c1e6: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800c1e8: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800c1ec: 2b00 cmp r3, #0
|
|
800c1ee: db0a blt.n 800c206 <__NVIC_SetPriority+0x2a>
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800c1f0: 683b ldr r3, [r7, #0]
|
|
800c1f2: b2da uxtb r2, r3
|
|
800c1f4: 490c ldr r1, [pc, #48] @ (800c228 <__NVIC_SetPriority+0x4c>)
|
|
800c1f6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800c1fa: 0112 lsls r2, r2, #4
|
|
800c1fc: b2d2 uxtb r2, r2
|
|
800c1fe: 440b add r3, r1
|
|
800c200: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
800c204: e00a b.n 800c21c <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800c206: 683b ldr r3, [r7, #0]
|
|
800c208: b2da uxtb r2, r3
|
|
800c20a: 4908 ldr r1, [pc, #32] @ (800c22c <__NVIC_SetPriority+0x50>)
|
|
800c20c: 79fb ldrb r3, [r7, #7]
|
|
800c20e: f003 030f and.w r3, r3, #15
|
|
800c212: 3b04 subs r3, #4
|
|
800c214: 0112 lsls r2, r2, #4
|
|
800c216: b2d2 uxtb r2, r2
|
|
800c218: 440b add r3, r1
|
|
800c21a: 761a strb r2, [r3, #24]
|
|
}
|
|
800c21c: bf00 nop
|
|
800c21e: 370c adds r7, #12
|
|
800c220: 46bd mov sp, r7
|
|
800c222: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c226: 4770 bx lr
|
|
800c228: e000e100 .word 0xe000e100
|
|
800c22c: e000ed00 .word 0xe000ed00
|
|
|
|
0800c230 <SysTick_Handler>:
|
|
|
|
/*
|
|
SysTick handler implementation that also clears overflow flag.
|
|
*/
|
|
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
|
|
void SysTick_Handler (void) {
|
|
800c230: b580 push {r7, lr}
|
|
800c232: af00 add r7, sp, #0
|
|
/* Clear overflow flag */
|
|
SysTick->CTRL;
|
|
800c234: 4b05 ldr r3, [pc, #20] @ (800c24c <SysTick_Handler+0x1c>)
|
|
800c236: 681b ldr r3, [r3, #0]
|
|
|
|
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
|
|
800c238: f001 fe28 bl 800de8c <xTaskGetSchedulerState>
|
|
800c23c: 4603 mov r3, r0
|
|
800c23e: 2b01 cmp r3, #1
|
|
800c240: d001 beq.n 800c246 <SysTick_Handler+0x16>
|
|
/* Call tick handler */
|
|
xPortSysTickHandler();
|
|
800c242: f002 fe21 bl 800ee88 <xPortSysTickHandler>
|
|
}
|
|
}
|
|
800c246: bf00 nop
|
|
800c248: bd80 pop {r7, pc}
|
|
800c24a: bf00 nop
|
|
800c24c: e000e010 .word 0xe000e010
|
|
|
|
0800c250 <SVC_Setup>:
|
|
#endif /* SysTick */
|
|
|
|
/*
|
|
Setup SVC to reset value.
|
|
*/
|
|
__STATIC_INLINE void SVC_Setup (void) {
|
|
800c250: b580 push {r7, lr}
|
|
800c252: af00 add r7, sp, #0
|
|
#if (__ARM_ARCH_7A__ == 0U)
|
|
/* Service Call interrupt might be configured before kernel start */
|
|
/* and when its priority is lower or equal to BASEPRI, svc intruction */
|
|
/* causes a Hard Fault. */
|
|
NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
|
|
800c254: 2100 movs r1, #0
|
|
800c256: f06f 0004 mvn.w r0, #4
|
|
800c25a: f7ff ffbf bl 800c1dc <__NVIC_SetPriority>
|
|
#endif
|
|
}
|
|
800c25e: bf00 nop
|
|
800c260: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800c264 <osKernelInitialize>:
|
|
static uint32_t OS_Tick_GetOverflow (void);
|
|
/* Get OS Tick interval */
|
|
static uint32_t OS_Tick_GetInterval (void);
|
|
/*---------------------------------------------------------------------------*/
|
|
|
|
osStatus_t osKernelInitialize (void) {
|
|
800c264: b480 push {r7}
|
|
800c266: b083 sub sp, #12
|
|
800c268: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
|
800c26a: f3ef 8305 mrs r3, IPSR
|
|
800c26e: 603b str r3, [r7, #0]
|
|
return(result);
|
|
800c270: 683b ldr r3, [r7, #0]
|
|
osStatus_t stat;
|
|
|
|
if (IS_IRQ()) {
|
|
800c272: 2b00 cmp r3, #0
|
|
800c274: d003 beq.n 800c27e <osKernelInitialize+0x1a>
|
|
stat = osErrorISR;
|
|
800c276: f06f 0305 mvn.w r3, #5
|
|
800c27a: 607b str r3, [r7, #4]
|
|
800c27c: e00c b.n 800c298 <osKernelInitialize+0x34>
|
|
}
|
|
else {
|
|
if (KernelState == osKernelInactive) {
|
|
800c27e: 4b0a ldr r3, [pc, #40] @ (800c2a8 <osKernelInitialize+0x44>)
|
|
800c280: 681b ldr r3, [r3, #0]
|
|
800c282: 2b00 cmp r3, #0
|
|
800c284: d105 bne.n 800c292 <osKernelInitialize+0x2e>
|
|
EvrFreeRTOSSetup(0U);
|
|
#endif
|
|
#if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
|
|
vPortDefineHeapRegions (configHEAP_5_REGIONS);
|
|
#endif
|
|
KernelState = osKernelReady;
|
|
800c286: 4b08 ldr r3, [pc, #32] @ (800c2a8 <osKernelInitialize+0x44>)
|
|
800c288: 2201 movs r2, #1
|
|
800c28a: 601a str r2, [r3, #0]
|
|
stat = osOK;
|
|
800c28c: 2300 movs r3, #0
|
|
800c28e: 607b str r3, [r7, #4]
|
|
800c290: e002 b.n 800c298 <osKernelInitialize+0x34>
|
|
} else {
|
|
stat = osError;
|
|
800c292: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800c296: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
return (stat);
|
|
800c298: 687b ldr r3, [r7, #4]
|
|
}
|
|
800c29a: 4618 mov r0, r3
|
|
800c29c: 370c adds r7, #12
|
|
800c29e: 46bd mov sp, r7
|
|
800c2a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c2a4: 4770 bx lr
|
|
800c2a6: bf00 nop
|
|
800c2a8: 20001c84 .word 0x20001c84
|
|
|
|
0800c2ac <osKernelStart>:
|
|
}
|
|
|
|
return (state);
|
|
}
|
|
|
|
osStatus_t osKernelStart (void) {
|
|
800c2ac: b580 push {r7, lr}
|
|
800c2ae: b082 sub sp, #8
|
|
800c2b0: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
|
800c2b2: f3ef 8305 mrs r3, IPSR
|
|
800c2b6: 603b str r3, [r7, #0]
|
|
return(result);
|
|
800c2b8: 683b ldr r3, [r7, #0]
|
|
osStatus_t stat;
|
|
|
|
if (IS_IRQ()) {
|
|
800c2ba: 2b00 cmp r3, #0
|
|
800c2bc: d003 beq.n 800c2c6 <osKernelStart+0x1a>
|
|
stat = osErrorISR;
|
|
800c2be: f06f 0305 mvn.w r3, #5
|
|
800c2c2: 607b str r3, [r7, #4]
|
|
800c2c4: e010 b.n 800c2e8 <osKernelStart+0x3c>
|
|
}
|
|
else {
|
|
if (KernelState == osKernelReady) {
|
|
800c2c6: 4b0b ldr r3, [pc, #44] @ (800c2f4 <osKernelStart+0x48>)
|
|
800c2c8: 681b ldr r3, [r3, #0]
|
|
800c2ca: 2b01 cmp r3, #1
|
|
800c2cc: d109 bne.n 800c2e2 <osKernelStart+0x36>
|
|
/* Ensure SVC priority is at the reset value */
|
|
SVC_Setup();
|
|
800c2ce: f7ff ffbf bl 800c250 <SVC_Setup>
|
|
/* Change state to enable IRQ masking check */
|
|
KernelState = osKernelRunning;
|
|
800c2d2: 4b08 ldr r3, [pc, #32] @ (800c2f4 <osKernelStart+0x48>)
|
|
800c2d4: 2202 movs r2, #2
|
|
800c2d6: 601a str r2, [r3, #0]
|
|
/* Start the kernel scheduler */
|
|
vTaskStartScheduler();
|
|
800c2d8: f001 f98a bl 800d5f0 <vTaskStartScheduler>
|
|
stat = osOK;
|
|
800c2dc: 2300 movs r3, #0
|
|
800c2de: 607b str r3, [r7, #4]
|
|
800c2e0: e002 b.n 800c2e8 <osKernelStart+0x3c>
|
|
} else {
|
|
stat = osError;
|
|
800c2e2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800c2e6: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
return (stat);
|
|
800c2e8: 687b ldr r3, [r7, #4]
|
|
}
|
|
800c2ea: 4618 mov r0, r3
|
|
800c2ec: 3708 adds r7, #8
|
|
800c2ee: 46bd mov sp, r7
|
|
800c2f0: bd80 pop {r7, pc}
|
|
800c2f2: bf00 nop
|
|
800c2f4: 20001c84 .word 0x20001c84
|
|
|
|
0800c2f8 <vApplicationGetIdleTaskMemory>:
|
|
|
|
/*
|
|
vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
|
|
equals to 1 and is required for static memory allocation support.
|
|
*/
|
|
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
|
|
800c2f8: b480 push {r7}
|
|
800c2fa: b085 sub sp, #20
|
|
800c2fc: af00 add r7, sp, #0
|
|
800c2fe: 60f8 str r0, [r7, #12]
|
|
800c300: 60b9 str r1, [r7, #8]
|
|
800c302: 607a str r2, [r7, #4]
|
|
/* Idle task control block and stack */
|
|
static StaticTask_t Idle_TCB;
|
|
static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
|
|
|
|
*ppxIdleTaskTCBBuffer = &Idle_TCB;
|
|
800c304: 68fb ldr r3, [r7, #12]
|
|
800c306: 4a07 ldr r2, [pc, #28] @ (800c324 <vApplicationGetIdleTaskMemory+0x2c>)
|
|
800c308: 601a str r2, [r3, #0]
|
|
*ppxIdleTaskStackBuffer = &Idle_Stack[0];
|
|
800c30a: 68bb ldr r3, [r7, #8]
|
|
800c30c: 4a06 ldr r2, [pc, #24] @ (800c328 <vApplicationGetIdleTaskMemory+0x30>)
|
|
800c30e: 601a str r2, [r3, #0]
|
|
*pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
|
|
800c310: 687b ldr r3, [r7, #4]
|
|
800c312: 2280 movs r2, #128 @ 0x80
|
|
800c314: 601a str r2, [r3, #0]
|
|
}
|
|
800c316: bf00 nop
|
|
800c318: 3714 adds r7, #20
|
|
800c31a: 46bd mov sp, r7
|
|
800c31c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c320: 4770 bx lr
|
|
800c322: bf00 nop
|
|
800c324: 20001c88 .word 0x20001c88
|
|
800c328: 20001ce4 .word 0x20001ce4
|
|
|
|
0800c32c <vApplicationGetTimerTaskMemory>:
|
|
|
|
/*
|
|
vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
|
|
equals to 1 and is required for static memory allocation support.
|
|
*/
|
|
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
|
|
800c32c: b480 push {r7}
|
|
800c32e: b085 sub sp, #20
|
|
800c330: af00 add r7, sp, #0
|
|
800c332: 60f8 str r0, [r7, #12]
|
|
800c334: 60b9 str r1, [r7, #8]
|
|
800c336: 607a str r2, [r7, #4]
|
|
/* Timer task control block and stack */
|
|
static StaticTask_t Timer_TCB;
|
|
static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
|
|
|
|
*ppxTimerTaskTCBBuffer = &Timer_TCB;
|
|
800c338: 68fb ldr r3, [r7, #12]
|
|
800c33a: 4a07 ldr r2, [pc, #28] @ (800c358 <vApplicationGetTimerTaskMemory+0x2c>)
|
|
800c33c: 601a str r2, [r3, #0]
|
|
*ppxTimerTaskStackBuffer = &Timer_Stack[0];
|
|
800c33e: 68bb ldr r3, [r7, #8]
|
|
800c340: 4a06 ldr r2, [pc, #24] @ (800c35c <vApplicationGetTimerTaskMemory+0x30>)
|
|
800c342: 601a str r2, [r3, #0]
|
|
*pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
|
|
800c344: 687b ldr r3, [r7, #4]
|
|
800c346: f44f 7280 mov.w r2, #256 @ 0x100
|
|
800c34a: 601a str r2, [r3, #0]
|
|
}
|
|
800c34c: bf00 nop
|
|
800c34e: 3714 adds r7, #20
|
|
800c350: 46bd mov sp, r7
|
|
800c352: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c356: 4770 bx lr
|
|
800c358: 20001ee4 .word 0x20001ee4
|
|
800c35c: 20001f40 .word 0x20001f40
|
|
|
|
0800c360 <vListInitialise>:
|
|
/*-----------------------------------------------------------
|
|
* PUBLIC LIST API documented in list.h
|
|
*----------------------------------------------------------*/
|
|
|
|
void vListInitialise( List_t * const pxList )
|
|
{
|
|
800c360: b480 push {r7}
|
|
800c362: b083 sub sp, #12
|
|
800c364: af00 add r7, sp, #0
|
|
800c366: 6078 str r0, [r7, #4]
|
|
/* The list structure contains a list item which is used to mark the
|
|
end of the list. To initialise the list the list end is inserted
|
|
as the only list entry. */
|
|
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800c368: 687b ldr r3, [r7, #4]
|
|
800c36a: f103 0208 add.w r2, r3, #8
|
|
800c36e: 687b ldr r3, [r7, #4]
|
|
800c370: 605a str r2, [r3, #4]
|
|
|
|
/* The list end value is the highest possible value in the list to
|
|
ensure it remains at the end of the list. */
|
|
pxList->xListEnd.xItemValue = portMAX_DELAY;
|
|
800c372: 687b ldr r3, [r7, #4]
|
|
800c374: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800c378: 609a str r2, [r3, #8]
|
|
|
|
/* The list end next and previous pointers point to itself so we know
|
|
when the list is empty. */
|
|
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800c37a: 687b ldr r3, [r7, #4]
|
|
800c37c: f103 0208 add.w r2, r3, #8
|
|
800c380: 687b ldr r3, [r7, #4]
|
|
800c382: 60da str r2, [r3, #12]
|
|
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800c384: 687b ldr r3, [r7, #4]
|
|
800c386: f103 0208 add.w r2, r3, #8
|
|
800c38a: 687b ldr r3, [r7, #4]
|
|
800c38c: 611a str r2, [r3, #16]
|
|
|
|
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
|
|
800c38e: 687b ldr r3, [r7, #4]
|
|
800c390: 2200 movs r2, #0
|
|
800c392: 601a str r2, [r3, #0]
|
|
|
|
/* Write known values into the list if
|
|
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
|
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
|
|
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
|
|
}
|
|
800c394: bf00 nop
|
|
800c396: 370c adds r7, #12
|
|
800c398: 46bd mov sp, r7
|
|
800c39a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c39e: 4770 bx lr
|
|
|
|
0800c3a0 <vListInitialiseItem>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInitialiseItem( ListItem_t * const pxItem )
|
|
{
|
|
800c3a0: b480 push {r7}
|
|
800c3a2: b083 sub sp, #12
|
|
800c3a4: af00 add r7, sp, #0
|
|
800c3a6: 6078 str r0, [r7, #4]
|
|
/* Make sure the list item is not recorded as being on a list. */
|
|
pxItem->pxContainer = NULL;
|
|
800c3a8: 687b ldr r3, [r7, #4]
|
|
800c3aa: 2200 movs r2, #0
|
|
800c3ac: 611a str r2, [r3, #16]
|
|
|
|
/* Write known values into the list item if
|
|
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
|
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
}
|
|
800c3ae: bf00 nop
|
|
800c3b0: 370c adds r7, #12
|
|
800c3b2: 46bd mov sp, r7
|
|
800c3b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c3b8: 4770 bx lr
|
|
|
|
0800c3ba <vListInsertEnd>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
|
|
{
|
|
800c3ba: b480 push {r7}
|
|
800c3bc: b085 sub sp, #20
|
|
800c3be: af00 add r7, sp, #0
|
|
800c3c0: 6078 str r0, [r7, #4]
|
|
800c3c2: 6039 str r1, [r7, #0]
|
|
ListItem_t * const pxIndex = pxList->pxIndex;
|
|
800c3c4: 687b ldr r3, [r7, #4]
|
|
800c3c6: 685b ldr r3, [r3, #4]
|
|
800c3c8: 60fb str r3, [r7, #12]
|
|
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
|
|
|
/* Insert a new list item into pxList, but rather than sort the list,
|
|
makes the new list item the last item to be removed by a call to
|
|
listGET_OWNER_OF_NEXT_ENTRY(). */
|
|
pxNewListItem->pxNext = pxIndex;
|
|
800c3ca: 683b ldr r3, [r7, #0]
|
|
800c3cc: 68fa ldr r2, [r7, #12]
|
|
800c3ce: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
|
|
800c3d0: 68fb ldr r3, [r7, #12]
|
|
800c3d2: 689a ldr r2, [r3, #8]
|
|
800c3d4: 683b ldr r3, [r7, #0]
|
|
800c3d6: 609a str r2, [r3, #8]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
pxIndex->pxPrevious->pxNext = pxNewListItem;
|
|
800c3d8: 68fb ldr r3, [r7, #12]
|
|
800c3da: 689b ldr r3, [r3, #8]
|
|
800c3dc: 683a ldr r2, [r7, #0]
|
|
800c3de: 605a str r2, [r3, #4]
|
|
pxIndex->pxPrevious = pxNewListItem;
|
|
800c3e0: 68fb ldr r3, [r7, #12]
|
|
800c3e2: 683a ldr r2, [r7, #0]
|
|
800c3e4: 609a str r2, [r3, #8]
|
|
|
|
/* Remember which list the item is in. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
800c3e6: 683b ldr r3, [r7, #0]
|
|
800c3e8: 687a ldr r2, [r7, #4]
|
|
800c3ea: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
800c3ec: 687b ldr r3, [r7, #4]
|
|
800c3ee: 681b ldr r3, [r3, #0]
|
|
800c3f0: 1c5a adds r2, r3, #1
|
|
800c3f2: 687b ldr r3, [r7, #4]
|
|
800c3f4: 601a str r2, [r3, #0]
|
|
}
|
|
800c3f6: bf00 nop
|
|
800c3f8: 3714 adds r7, #20
|
|
800c3fa: 46bd mov sp, r7
|
|
800c3fc: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c400: 4770 bx lr
|
|
|
|
0800c402 <vListInsert>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
|
|
{
|
|
800c402: b480 push {r7}
|
|
800c404: b085 sub sp, #20
|
|
800c406: af00 add r7, sp, #0
|
|
800c408: 6078 str r0, [r7, #4]
|
|
800c40a: 6039 str r1, [r7, #0]
|
|
ListItem_t *pxIterator;
|
|
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
|
|
800c40c: 683b ldr r3, [r7, #0]
|
|
800c40e: 681b ldr r3, [r3, #0]
|
|
800c410: 60bb str r3, [r7, #8]
|
|
new list item should be placed after it. This ensures that TCBs which are
|
|
stored in ready lists (all of which have the same xItemValue value) get a
|
|
share of the CPU. However, if the xItemValue is the same as the back marker
|
|
the iteration loop below will not end. Therefore the value is checked
|
|
first, and the algorithm slightly modified if necessary. */
|
|
if( xValueOfInsertion == portMAX_DELAY )
|
|
800c412: 68bb ldr r3, [r7, #8]
|
|
800c414: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800c418: d103 bne.n 800c422 <vListInsert+0x20>
|
|
{
|
|
pxIterator = pxList->xListEnd.pxPrevious;
|
|
800c41a: 687b ldr r3, [r7, #4]
|
|
800c41c: 691b ldr r3, [r3, #16]
|
|
800c41e: 60fb str r3, [r7, #12]
|
|
800c420: e00c b.n 800c43c <vListInsert+0x3a>
|
|
4) Using a queue or semaphore before it has been initialised or
|
|
before the scheduler has been started (are interrupts firing
|
|
before vTaskStartScheduler() has been called?).
|
|
**********************************************************************/
|
|
|
|
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
|
|
800c422: 687b ldr r3, [r7, #4]
|
|
800c424: 3308 adds r3, #8
|
|
800c426: 60fb str r3, [r7, #12]
|
|
800c428: e002 b.n 800c430 <vListInsert+0x2e>
|
|
800c42a: 68fb ldr r3, [r7, #12]
|
|
800c42c: 685b ldr r3, [r3, #4]
|
|
800c42e: 60fb str r3, [r7, #12]
|
|
800c430: 68fb ldr r3, [r7, #12]
|
|
800c432: 685b ldr r3, [r3, #4]
|
|
800c434: 681b ldr r3, [r3, #0]
|
|
800c436: 68ba ldr r2, [r7, #8]
|
|
800c438: 429a cmp r2, r3
|
|
800c43a: d2f6 bcs.n 800c42a <vListInsert+0x28>
|
|
/* There is nothing to do here, just iterating to the wanted
|
|
insertion position. */
|
|
}
|
|
}
|
|
|
|
pxNewListItem->pxNext = pxIterator->pxNext;
|
|
800c43c: 68fb ldr r3, [r7, #12]
|
|
800c43e: 685a ldr r2, [r3, #4]
|
|
800c440: 683b ldr r3, [r7, #0]
|
|
800c442: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
|
|
800c444: 683b ldr r3, [r7, #0]
|
|
800c446: 685b ldr r3, [r3, #4]
|
|
800c448: 683a ldr r2, [r7, #0]
|
|
800c44a: 609a str r2, [r3, #8]
|
|
pxNewListItem->pxPrevious = pxIterator;
|
|
800c44c: 683b ldr r3, [r7, #0]
|
|
800c44e: 68fa ldr r2, [r7, #12]
|
|
800c450: 609a str r2, [r3, #8]
|
|
pxIterator->pxNext = pxNewListItem;
|
|
800c452: 68fb ldr r3, [r7, #12]
|
|
800c454: 683a ldr r2, [r7, #0]
|
|
800c456: 605a str r2, [r3, #4]
|
|
|
|
/* Remember which list the item is in. This allows fast removal of the
|
|
item later. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
800c458: 683b ldr r3, [r7, #0]
|
|
800c45a: 687a ldr r2, [r7, #4]
|
|
800c45c: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
800c45e: 687b ldr r3, [r7, #4]
|
|
800c460: 681b ldr r3, [r3, #0]
|
|
800c462: 1c5a adds r2, r3, #1
|
|
800c464: 687b ldr r3, [r7, #4]
|
|
800c466: 601a str r2, [r3, #0]
|
|
}
|
|
800c468: bf00 nop
|
|
800c46a: 3714 adds r7, #20
|
|
800c46c: 46bd mov sp, r7
|
|
800c46e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c472: 4770 bx lr
|
|
|
|
0800c474 <uxListRemove>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
|
|
{
|
|
800c474: b480 push {r7}
|
|
800c476: b085 sub sp, #20
|
|
800c478: af00 add r7, sp, #0
|
|
800c47a: 6078 str r0, [r7, #4]
|
|
/* The list item knows which list it is in. Obtain the list from the list
|
|
item. */
|
|
List_t * const pxList = pxItemToRemove->pxContainer;
|
|
800c47c: 687b ldr r3, [r7, #4]
|
|
800c47e: 691b ldr r3, [r3, #16]
|
|
800c480: 60fb str r3, [r7, #12]
|
|
|
|
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
|
|
800c482: 687b ldr r3, [r7, #4]
|
|
800c484: 685b ldr r3, [r3, #4]
|
|
800c486: 687a ldr r2, [r7, #4]
|
|
800c488: 6892 ldr r2, [r2, #8]
|
|
800c48a: 609a str r2, [r3, #8]
|
|
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
|
|
800c48c: 687b ldr r3, [r7, #4]
|
|
800c48e: 689b ldr r3, [r3, #8]
|
|
800c490: 687a ldr r2, [r7, #4]
|
|
800c492: 6852 ldr r2, [r2, #4]
|
|
800c494: 605a str r2, [r3, #4]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
/* Make sure the index is left pointing to a valid item. */
|
|
if( pxList->pxIndex == pxItemToRemove )
|
|
800c496: 68fb ldr r3, [r7, #12]
|
|
800c498: 685b ldr r3, [r3, #4]
|
|
800c49a: 687a ldr r2, [r7, #4]
|
|
800c49c: 429a cmp r2, r3
|
|
800c49e: d103 bne.n 800c4a8 <uxListRemove+0x34>
|
|
{
|
|
pxList->pxIndex = pxItemToRemove->pxPrevious;
|
|
800c4a0: 687b ldr r3, [r7, #4]
|
|
800c4a2: 689a ldr r2, [r3, #8]
|
|
800c4a4: 68fb ldr r3, [r7, #12]
|
|
800c4a6: 605a str r2, [r3, #4]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxItemToRemove->pxContainer = NULL;
|
|
800c4a8: 687b ldr r3, [r7, #4]
|
|
800c4aa: 2200 movs r2, #0
|
|
800c4ac: 611a str r2, [r3, #16]
|
|
( pxList->uxNumberOfItems )--;
|
|
800c4ae: 68fb ldr r3, [r7, #12]
|
|
800c4b0: 681b ldr r3, [r3, #0]
|
|
800c4b2: 1e5a subs r2, r3, #1
|
|
800c4b4: 68fb ldr r3, [r7, #12]
|
|
800c4b6: 601a str r2, [r3, #0]
|
|
|
|
return pxList->uxNumberOfItems;
|
|
800c4b8: 68fb ldr r3, [r7, #12]
|
|
800c4ba: 681b ldr r3, [r3, #0]
|
|
}
|
|
800c4bc: 4618 mov r0, r3
|
|
800c4be: 3714 adds r7, #20
|
|
800c4c0: 46bd mov sp, r7
|
|
800c4c2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c4c6: 4770 bx lr
|
|
|
|
0800c4c8 <xQueueGenericReset>:
|
|
} \
|
|
taskEXIT_CRITICAL()
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
|
|
{
|
|
800c4c8: b580 push {r7, lr}
|
|
800c4ca: b084 sub sp, #16
|
|
800c4cc: af00 add r7, sp, #0
|
|
800c4ce: 6078 str r0, [r7, #4]
|
|
800c4d0: 6039 str r1, [r7, #0]
|
|
Queue_t * const pxQueue = xQueue;
|
|
800c4d2: 687b ldr r3, [r7, #4]
|
|
800c4d4: 60fb str r3, [r7, #12]
|
|
|
|
configASSERT( pxQueue );
|
|
800c4d6: 68fb ldr r3, [r7, #12]
|
|
800c4d8: 2b00 cmp r3, #0
|
|
800c4da: d10b bne.n 800c4f4 <xQueueGenericReset+0x2c>
|
|
|
|
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
800c4dc: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c4e0: f383 8811 msr BASEPRI, r3
|
|
800c4e4: f3bf 8f6f isb sy
|
|
800c4e8: f3bf 8f4f dsb sy
|
|
800c4ec: 60bb str r3, [r7, #8]
|
|
" msr basepri, %0 \n" \
|
|
" isb \n" \
|
|
" dsb \n" \
|
|
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
}
|
|
800c4ee: bf00 nop
|
|
800c4f0: bf00 nop
|
|
800c4f2: e7fd b.n 800c4f0 <xQueueGenericReset+0x28>
|
|
|
|
taskENTER_CRITICAL();
|
|
800c4f4: f002 fc38 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800c4f8: 68fb ldr r3, [r7, #12]
|
|
800c4fa: 681a ldr r2, [r3, #0]
|
|
800c4fc: 68fb ldr r3, [r7, #12]
|
|
800c4fe: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800c500: 68f9 ldr r1, [r7, #12]
|
|
800c502: 6c09 ldr r1, [r1, #64] @ 0x40
|
|
800c504: fb01 f303 mul.w r3, r1, r3
|
|
800c508: 441a add r2, r3
|
|
800c50a: 68fb ldr r3, [r7, #12]
|
|
800c50c: 609a str r2, [r3, #8]
|
|
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
|
|
800c50e: 68fb ldr r3, [r7, #12]
|
|
800c510: 2200 movs r2, #0
|
|
800c512: 639a str r2, [r3, #56] @ 0x38
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
800c514: 68fb ldr r3, [r7, #12]
|
|
800c516: 681a ldr r2, [r3, #0]
|
|
800c518: 68fb ldr r3, [r7, #12]
|
|
800c51a: 605a str r2, [r3, #4]
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800c51c: 68fb ldr r3, [r7, #12]
|
|
800c51e: 681a ldr r2, [r3, #0]
|
|
800c520: 68fb ldr r3, [r7, #12]
|
|
800c522: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800c524: 3b01 subs r3, #1
|
|
800c526: 68f9 ldr r1, [r7, #12]
|
|
800c528: 6c09 ldr r1, [r1, #64] @ 0x40
|
|
800c52a: fb01 f303 mul.w r3, r1, r3
|
|
800c52e: 441a add r2, r3
|
|
800c530: 68fb ldr r3, [r7, #12]
|
|
800c532: 60da str r2, [r3, #12]
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
800c534: 68fb ldr r3, [r7, #12]
|
|
800c536: 22ff movs r2, #255 @ 0xff
|
|
800c538: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
800c53c: 68fb ldr r3, [r7, #12]
|
|
800c53e: 22ff movs r2, #255 @ 0xff
|
|
800c540: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
if( xNewQueue == pdFALSE )
|
|
800c544: 683b ldr r3, [r7, #0]
|
|
800c546: 2b00 cmp r3, #0
|
|
800c548: d114 bne.n 800c574 <xQueueGenericReset+0xac>
|
|
/* If there are tasks blocked waiting to read from the queue, then
|
|
the tasks will remain blocked as after this function exits the queue
|
|
will still be empty. If there are tasks blocked waiting to write to
|
|
the queue, then one should be unblocked as after this function exits
|
|
it will be possible to write to it. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800c54a: 68fb ldr r3, [r7, #12]
|
|
800c54c: 691b ldr r3, [r3, #16]
|
|
800c54e: 2b00 cmp r3, #0
|
|
800c550: d01a beq.n 800c588 <xQueueGenericReset+0xc0>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800c552: 68fb ldr r3, [r7, #12]
|
|
800c554: 3310 adds r3, #16
|
|
800c556: 4618 mov r0, r3
|
|
800c558: f001 fad8 bl 800db0c <xTaskRemoveFromEventList>
|
|
800c55c: 4603 mov r3, r0
|
|
800c55e: 2b00 cmp r3, #0
|
|
800c560: d012 beq.n 800c588 <xQueueGenericReset+0xc0>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800c562: 4b0d ldr r3, [pc, #52] @ (800c598 <xQueueGenericReset+0xd0>)
|
|
800c564: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800c568: 601a str r2, [r3, #0]
|
|
800c56a: f3bf 8f4f dsb sy
|
|
800c56e: f3bf 8f6f isb sy
|
|
800c572: e009 b.n 800c588 <xQueueGenericReset+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Ensure the event queues start in the correct state. */
|
|
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
|
|
800c574: 68fb ldr r3, [r7, #12]
|
|
800c576: 3310 adds r3, #16
|
|
800c578: 4618 mov r0, r3
|
|
800c57a: f7ff fef1 bl 800c360 <vListInitialise>
|
|
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
|
|
800c57e: 68fb ldr r3, [r7, #12]
|
|
800c580: 3324 adds r3, #36 @ 0x24
|
|
800c582: 4618 mov r0, r3
|
|
800c584: f7ff feec bl 800c360 <vListInitialise>
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800c588: f002 fc20 bl 800edcc <vPortExitCritical>
|
|
|
|
/* A value is returned for calling semantic consistency with previous
|
|
versions. */
|
|
return pdPASS;
|
|
800c58c: 2301 movs r3, #1
|
|
}
|
|
800c58e: 4618 mov r0, r3
|
|
800c590: 3710 adds r7, #16
|
|
800c592: 46bd mov sp, r7
|
|
800c594: bd80 pop {r7, pc}
|
|
800c596: bf00 nop
|
|
800c598: e000ed04 .word 0xe000ed04
|
|
|
|
0800c59c <xQueueGenericCreateStatic>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
|
|
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
|
|
{
|
|
800c59c: b580 push {r7, lr}
|
|
800c59e: b08e sub sp, #56 @ 0x38
|
|
800c5a0: af02 add r7, sp, #8
|
|
800c5a2: 60f8 str r0, [r7, #12]
|
|
800c5a4: 60b9 str r1, [r7, #8]
|
|
800c5a6: 607a str r2, [r7, #4]
|
|
800c5a8: 603b str r3, [r7, #0]
|
|
Queue_t *pxNewQueue;
|
|
|
|
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
|
|
800c5aa: 68fb ldr r3, [r7, #12]
|
|
800c5ac: 2b00 cmp r3, #0
|
|
800c5ae: d10b bne.n 800c5c8 <xQueueGenericCreateStatic+0x2c>
|
|
__asm volatile
|
|
800c5b0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c5b4: f383 8811 msr BASEPRI, r3
|
|
800c5b8: f3bf 8f6f isb sy
|
|
800c5bc: f3bf 8f4f dsb sy
|
|
800c5c0: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
800c5c2: bf00 nop
|
|
800c5c4: bf00 nop
|
|
800c5c6: e7fd b.n 800c5c4 <xQueueGenericCreateStatic+0x28>
|
|
|
|
/* The StaticQueue_t structure and the queue storage area must be
|
|
supplied. */
|
|
configASSERT( pxStaticQueue != NULL );
|
|
800c5c8: 683b ldr r3, [r7, #0]
|
|
800c5ca: 2b00 cmp r3, #0
|
|
800c5cc: d10b bne.n 800c5e6 <xQueueGenericCreateStatic+0x4a>
|
|
__asm volatile
|
|
800c5ce: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c5d2: f383 8811 msr BASEPRI, r3
|
|
800c5d6: f3bf 8f6f isb sy
|
|
800c5da: f3bf 8f4f dsb sy
|
|
800c5de: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
800c5e0: bf00 nop
|
|
800c5e2: bf00 nop
|
|
800c5e4: e7fd b.n 800c5e2 <xQueueGenericCreateStatic+0x46>
|
|
|
|
/* A queue storage area should be provided if the item size is not 0, and
|
|
should not be provided if the item size is 0. */
|
|
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
|
|
800c5e6: 687b ldr r3, [r7, #4]
|
|
800c5e8: 2b00 cmp r3, #0
|
|
800c5ea: d002 beq.n 800c5f2 <xQueueGenericCreateStatic+0x56>
|
|
800c5ec: 68bb ldr r3, [r7, #8]
|
|
800c5ee: 2b00 cmp r3, #0
|
|
800c5f0: d001 beq.n 800c5f6 <xQueueGenericCreateStatic+0x5a>
|
|
800c5f2: 2301 movs r3, #1
|
|
800c5f4: e000 b.n 800c5f8 <xQueueGenericCreateStatic+0x5c>
|
|
800c5f6: 2300 movs r3, #0
|
|
800c5f8: 2b00 cmp r3, #0
|
|
800c5fa: d10b bne.n 800c614 <xQueueGenericCreateStatic+0x78>
|
|
__asm volatile
|
|
800c5fc: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c600: f383 8811 msr BASEPRI, r3
|
|
800c604: f3bf 8f6f isb sy
|
|
800c608: f3bf 8f4f dsb sy
|
|
800c60c: 623b str r3, [r7, #32]
|
|
}
|
|
800c60e: bf00 nop
|
|
800c610: bf00 nop
|
|
800c612: e7fd b.n 800c610 <xQueueGenericCreateStatic+0x74>
|
|
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
|
|
800c614: 687b ldr r3, [r7, #4]
|
|
800c616: 2b00 cmp r3, #0
|
|
800c618: d102 bne.n 800c620 <xQueueGenericCreateStatic+0x84>
|
|
800c61a: 68bb ldr r3, [r7, #8]
|
|
800c61c: 2b00 cmp r3, #0
|
|
800c61e: d101 bne.n 800c624 <xQueueGenericCreateStatic+0x88>
|
|
800c620: 2301 movs r3, #1
|
|
800c622: e000 b.n 800c626 <xQueueGenericCreateStatic+0x8a>
|
|
800c624: 2300 movs r3, #0
|
|
800c626: 2b00 cmp r3, #0
|
|
800c628: d10b bne.n 800c642 <xQueueGenericCreateStatic+0xa6>
|
|
__asm volatile
|
|
800c62a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c62e: f383 8811 msr BASEPRI, r3
|
|
800c632: f3bf 8f6f isb sy
|
|
800c636: f3bf 8f4f dsb sy
|
|
800c63a: 61fb str r3, [r7, #28]
|
|
}
|
|
800c63c: bf00 nop
|
|
800c63e: bf00 nop
|
|
800c640: e7fd b.n 800c63e <xQueueGenericCreateStatic+0xa2>
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
/* Sanity check that the size of the structure used to declare a
|
|
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
|
|
the real queue and semaphore structures. */
|
|
volatile size_t xSize = sizeof( StaticQueue_t );
|
|
800c642: 2350 movs r3, #80 @ 0x50
|
|
800c644: 617b str r3, [r7, #20]
|
|
configASSERT( xSize == sizeof( Queue_t ) );
|
|
800c646: 697b ldr r3, [r7, #20]
|
|
800c648: 2b50 cmp r3, #80 @ 0x50
|
|
800c64a: d00b beq.n 800c664 <xQueueGenericCreateStatic+0xc8>
|
|
__asm volatile
|
|
800c64c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c650: f383 8811 msr BASEPRI, r3
|
|
800c654: f3bf 8f6f isb sy
|
|
800c658: f3bf 8f4f dsb sy
|
|
800c65c: 61bb str r3, [r7, #24]
|
|
}
|
|
800c65e: bf00 nop
|
|
800c660: bf00 nop
|
|
800c662: e7fd b.n 800c660 <xQueueGenericCreateStatic+0xc4>
|
|
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
|
|
800c664: 697b ldr r3, [r7, #20]
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/* The address of a statically allocated queue was passed in, use it.
|
|
The address of a statically allocated storage area was also passed in
|
|
but is already set. */
|
|
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
|
800c666: 683b ldr r3, [r7, #0]
|
|
800c668: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
if( pxNewQueue != NULL )
|
|
800c66a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c66c: 2b00 cmp r3, #0
|
|
800c66e: d00d beq.n 800c68c <xQueueGenericCreateStatic+0xf0>
|
|
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
{
|
|
/* Queues can be allocated wither statically or dynamically, so
|
|
note this queue was allocated statically in case the queue is
|
|
later deleted. */
|
|
pxNewQueue->ucStaticallyAllocated = pdTRUE;
|
|
800c670: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c672: 2201 movs r2, #1
|
|
800c674: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
|
800c678: f897 2038 ldrb.w r2, [r7, #56] @ 0x38
|
|
800c67c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c67e: 9300 str r3, [sp, #0]
|
|
800c680: 4613 mov r3, r2
|
|
800c682: 687a ldr r2, [r7, #4]
|
|
800c684: 68b9 ldr r1, [r7, #8]
|
|
800c686: 68f8 ldr r0, [r7, #12]
|
|
800c688: f000 f840 bl 800c70c <prvInitialiseNewQueue>
|
|
{
|
|
traceQUEUE_CREATE_FAILED( ucQueueType );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return pxNewQueue;
|
|
800c68c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
}
|
|
800c68e: 4618 mov r0, r3
|
|
800c690: 3730 adds r7, #48 @ 0x30
|
|
800c692: 46bd mov sp, r7
|
|
800c694: bd80 pop {r7, pc}
|
|
|
|
0800c696 <xQueueGenericCreate>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
|
|
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
|
|
{
|
|
800c696: b580 push {r7, lr}
|
|
800c698: b08a sub sp, #40 @ 0x28
|
|
800c69a: af02 add r7, sp, #8
|
|
800c69c: 60f8 str r0, [r7, #12]
|
|
800c69e: 60b9 str r1, [r7, #8]
|
|
800c6a0: 4613 mov r3, r2
|
|
800c6a2: 71fb strb r3, [r7, #7]
|
|
Queue_t *pxNewQueue;
|
|
size_t xQueueSizeInBytes;
|
|
uint8_t *pucQueueStorage;
|
|
|
|
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
|
|
800c6a4: 68fb ldr r3, [r7, #12]
|
|
800c6a6: 2b00 cmp r3, #0
|
|
800c6a8: d10b bne.n 800c6c2 <xQueueGenericCreate+0x2c>
|
|
__asm volatile
|
|
800c6aa: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c6ae: f383 8811 msr BASEPRI, r3
|
|
800c6b2: f3bf 8f6f isb sy
|
|
800c6b6: f3bf 8f4f dsb sy
|
|
800c6ba: 613b str r3, [r7, #16]
|
|
}
|
|
800c6bc: bf00 nop
|
|
800c6be: bf00 nop
|
|
800c6c0: e7fd b.n 800c6be <xQueueGenericCreate+0x28>
|
|
|
|
/* Allocate enough space to hold the maximum number of items that
|
|
can be in the queue at any time. It is valid for uxItemSize to be
|
|
zero in the case the queue is used as a semaphore. */
|
|
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800c6c2: 68fb ldr r3, [r7, #12]
|
|
800c6c4: 68ba ldr r2, [r7, #8]
|
|
800c6c6: fb02 f303 mul.w r3, r2, r3
|
|
800c6ca: 61fb str r3, [r7, #28]
|
|
alignment requirements of the Queue_t structure - which in this case
|
|
is an int8_t *. Therefore, whenever the stack alignment requirements
|
|
are greater than or equal to the pointer to char requirements the cast
|
|
is safe. In other cases alignment requirements are not strict (one or
|
|
two bytes). */
|
|
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
|
|
800c6cc: 69fb ldr r3, [r7, #28]
|
|
800c6ce: 3350 adds r3, #80 @ 0x50
|
|
800c6d0: 4618 mov r0, r3
|
|
800c6d2: f002 fc6b bl 800efac <pvPortMalloc>
|
|
800c6d6: 61b8 str r0, [r7, #24]
|
|
|
|
if( pxNewQueue != NULL )
|
|
800c6d8: 69bb ldr r3, [r7, #24]
|
|
800c6da: 2b00 cmp r3, #0
|
|
800c6dc: d011 beq.n 800c702 <xQueueGenericCreate+0x6c>
|
|
{
|
|
/* Jump past the queue structure to find the location of the queue
|
|
storage area. */
|
|
pucQueueStorage = ( uint8_t * ) pxNewQueue;
|
|
800c6de: 69bb ldr r3, [r7, #24]
|
|
800c6e0: 617b str r3, [r7, #20]
|
|
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800c6e2: 697b ldr r3, [r7, #20]
|
|
800c6e4: 3350 adds r3, #80 @ 0x50
|
|
800c6e6: 617b str r3, [r7, #20]
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
/* Queues can be created either statically or dynamically, so
|
|
note this task was created dynamically in case it is later
|
|
deleted. */
|
|
pxNewQueue->ucStaticallyAllocated = pdFALSE;
|
|
800c6e8: 69bb ldr r3, [r7, #24]
|
|
800c6ea: 2200 movs r2, #0
|
|
800c6ec: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
}
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
|
800c6f0: 79fa ldrb r2, [r7, #7]
|
|
800c6f2: 69bb ldr r3, [r7, #24]
|
|
800c6f4: 9300 str r3, [sp, #0]
|
|
800c6f6: 4613 mov r3, r2
|
|
800c6f8: 697a ldr r2, [r7, #20]
|
|
800c6fa: 68b9 ldr r1, [r7, #8]
|
|
800c6fc: 68f8 ldr r0, [r7, #12]
|
|
800c6fe: f000 f805 bl 800c70c <prvInitialiseNewQueue>
|
|
{
|
|
traceQUEUE_CREATE_FAILED( ucQueueType );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return pxNewQueue;
|
|
800c702: 69bb ldr r3, [r7, #24]
|
|
}
|
|
800c704: 4618 mov r0, r3
|
|
800c706: 3720 adds r7, #32
|
|
800c708: 46bd mov sp, r7
|
|
800c70a: bd80 pop {r7, pc}
|
|
|
|
0800c70c <prvInitialiseNewQueue>:
|
|
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
|
|
{
|
|
800c70c: b580 push {r7, lr}
|
|
800c70e: b084 sub sp, #16
|
|
800c710: af00 add r7, sp, #0
|
|
800c712: 60f8 str r0, [r7, #12]
|
|
800c714: 60b9 str r1, [r7, #8]
|
|
800c716: 607a str r2, [r7, #4]
|
|
800c718: 70fb strb r3, [r7, #3]
|
|
/* Remove compiler warnings about unused parameters should
|
|
configUSE_TRACE_FACILITY not be set to 1. */
|
|
( void ) ucQueueType;
|
|
|
|
if( uxItemSize == ( UBaseType_t ) 0 )
|
|
800c71a: 68bb ldr r3, [r7, #8]
|
|
800c71c: 2b00 cmp r3, #0
|
|
800c71e: d103 bne.n 800c728 <prvInitialiseNewQueue+0x1c>
|
|
{
|
|
/* No RAM was allocated for the queue storage area, but PC head cannot
|
|
be set to NULL because NULL is used as a key to say the queue is used as
|
|
a mutex. Therefore just set pcHead to point to the queue as a benign
|
|
value that is known to be within the memory map. */
|
|
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
|
|
800c720: 69bb ldr r3, [r7, #24]
|
|
800c722: 69ba ldr r2, [r7, #24]
|
|
800c724: 601a str r2, [r3, #0]
|
|
800c726: e002 b.n 800c72e <prvInitialiseNewQueue+0x22>
|
|
}
|
|
else
|
|
{
|
|
/* Set the head to the start of the queue storage area. */
|
|
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
|
|
800c728: 69bb ldr r3, [r7, #24]
|
|
800c72a: 687a ldr r2, [r7, #4]
|
|
800c72c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Initialise the queue members as described where the queue type is
|
|
defined. */
|
|
pxNewQueue->uxLength = uxQueueLength;
|
|
800c72e: 69bb ldr r3, [r7, #24]
|
|
800c730: 68fa ldr r2, [r7, #12]
|
|
800c732: 63da str r2, [r3, #60] @ 0x3c
|
|
pxNewQueue->uxItemSize = uxItemSize;
|
|
800c734: 69bb ldr r3, [r7, #24]
|
|
800c736: 68ba ldr r2, [r7, #8]
|
|
800c738: 641a str r2, [r3, #64] @ 0x40
|
|
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
|
|
800c73a: 2101 movs r1, #1
|
|
800c73c: 69b8 ldr r0, [r7, #24]
|
|
800c73e: f7ff fec3 bl 800c4c8 <xQueueGenericReset>
|
|
|
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
|
{
|
|
pxNewQueue->ucQueueType = ucQueueType;
|
|
800c742: 69bb ldr r3, [r7, #24]
|
|
800c744: 78fa ldrb r2, [r7, #3]
|
|
800c746: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
pxNewQueue->pxQueueSetContainer = NULL;
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
traceQUEUE_CREATE( pxNewQueue );
|
|
}
|
|
800c74a: bf00 nop
|
|
800c74c: 3710 adds r7, #16
|
|
800c74e: 46bd mov sp, r7
|
|
800c750: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800c754 <xQueueGenericSend>:
|
|
|
|
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
|
|
{
|
|
800c754: b580 push {r7, lr}
|
|
800c756: b08e sub sp, #56 @ 0x38
|
|
800c758: af00 add r7, sp, #0
|
|
800c75a: 60f8 str r0, [r7, #12]
|
|
800c75c: 60b9 str r1, [r7, #8]
|
|
800c75e: 607a str r2, [r7, #4]
|
|
800c760: 603b str r3, [r7, #0]
|
|
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
|
|
800c762: 2300 movs r3, #0
|
|
800c764: 637b str r3, [r7, #52] @ 0x34
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800c766: 68fb ldr r3, [r7, #12]
|
|
800c768: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
configASSERT( pxQueue );
|
|
800c76a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c76c: 2b00 cmp r3, #0
|
|
800c76e: d10b bne.n 800c788 <xQueueGenericSend+0x34>
|
|
__asm volatile
|
|
800c770: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c774: f383 8811 msr BASEPRI, r3
|
|
800c778: f3bf 8f6f isb sy
|
|
800c77c: f3bf 8f4f dsb sy
|
|
800c780: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
800c782: bf00 nop
|
|
800c784: bf00 nop
|
|
800c786: e7fd b.n 800c784 <xQueueGenericSend+0x30>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800c788: 68bb ldr r3, [r7, #8]
|
|
800c78a: 2b00 cmp r3, #0
|
|
800c78c: d103 bne.n 800c796 <xQueueGenericSend+0x42>
|
|
800c78e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c790: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800c792: 2b00 cmp r3, #0
|
|
800c794: d101 bne.n 800c79a <xQueueGenericSend+0x46>
|
|
800c796: 2301 movs r3, #1
|
|
800c798: e000 b.n 800c79c <xQueueGenericSend+0x48>
|
|
800c79a: 2300 movs r3, #0
|
|
800c79c: 2b00 cmp r3, #0
|
|
800c79e: d10b bne.n 800c7b8 <xQueueGenericSend+0x64>
|
|
__asm volatile
|
|
800c7a0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c7a4: f383 8811 msr BASEPRI, r3
|
|
800c7a8: f3bf 8f6f isb sy
|
|
800c7ac: f3bf 8f4f dsb sy
|
|
800c7b0: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
800c7b2: bf00 nop
|
|
800c7b4: bf00 nop
|
|
800c7b6: e7fd b.n 800c7b4 <xQueueGenericSend+0x60>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
800c7b8: 683b ldr r3, [r7, #0]
|
|
800c7ba: 2b02 cmp r3, #2
|
|
800c7bc: d103 bne.n 800c7c6 <xQueueGenericSend+0x72>
|
|
800c7be: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c7c0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800c7c2: 2b01 cmp r3, #1
|
|
800c7c4: d101 bne.n 800c7ca <xQueueGenericSend+0x76>
|
|
800c7c6: 2301 movs r3, #1
|
|
800c7c8: e000 b.n 800c7cc <xQueueGenericSend+0x78>
|
|
800c7ca: 2300 movs r3, #0
|
|
800c7cc: 2b00 cmp r3, #0
|
|
800c7ce: d10b bne.n 800c7e8 <xQueueGenericSend+0x94>
|
|
__asm volatile
|
|
800c7d0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c7d4: f383 8811 msr BASEPRI, r3
|
|
800c7d8: f3bf 8f6f isb sy
|
|
800c7dc: f3bf 8f4f dsb sy
|
|
800c7e0: 623b str r3, [r7, #32]
|
|
}
|
|
800c7e2: bf00 nop
|
|
800c7e4: bf00 nop
|
|
800c7e6: e7fd b.n 800c7e4 <xQueueGenericSend+0x90>
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
800c7e8: f001 fb50 bl 800de8c <xTaskGetSchedulerState>
|
|
800c7ec: 4603 mov r3, r0
|
|
800c7ee: 2b00 cmp r3, #0
|
|
800c7f0: d102 bne.n 800c7f8 <xQueueGenericSend+0xa4>
|
|
800c7f2: 687b ldr r3, [r7, #4]
|
|
800c7f4: 2b00 cmp r3, #0
|
|
800c7f6: d101 bne.n 800c7fc <xQueueGenericSend+0xa8>
|
|
800c7f8: 2301 movs r3, #1
|
|
800c7fa: e000 b.n 800c7fe <xQueueGenericSend+0xaa>
|
|
800c7fc: 2300 movs r3, #0
|
|
800c7fe: 2b00 cmp r3, #0
|
|
800c800: d10b bne.n 800c81a <xQueueGenericSend+0xc6>
|
|
__asm volatile
|
|
800c802: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c806: f383 8811 msr BASEPRI, r3
|
|
800c80a: f3bf 8f6f isb sy
|
|
800c80e: f3bf 8f4f dsb sy
|
|
800c812: 61fb str r3, [r7, #28]
|
|
}
|
|
800c814: bf00 nop
|
|
800c816: bf00 nop
|
|
800c818: e7fd b.n 800c816 <xQueueGenericSend+0xc2>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
allow return statements within the function itself. This is done in the
|
|
interest of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800c81a: f002 faa5 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
/* Is there room on the queue now? The running task must be the
|
|
highest priority task wanting to access the queue. If the head item
|
|
in the queue is to be overwritten then it does not matter if the
|
|
queue is full. */
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
800c81e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c820: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800c822: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c824: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800c826: 429a cmp r2, r3
|
|
800c828: d302 bcc.n 800c830 <xQueueGenericSend+0xdc>
|
|
800c82a: 683b ldr r3, [r7, #0]
|
|
800c82c: 2b02 cmp r3, #2
|
|
800c82e: d129 bne.n 800c884 <xQueueGenericSend+0x130>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
800c830: 683a ldr r2, [r7, #0]
|
|
800c832: 68b9 ldr r1, [r7, #8]
|
|
800c834: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800c836: f000 fbc7 bl 800cfc8 <prvCopyDataToQueue>
|
|
800c83a: 62f8 str r0, [r7, #44] @ 0x2c
|
|
|
|
/* If there was a task waiting for data to arrive on the
|
|
queue then unblock it now. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800c83c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c83e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800c840: 2b00 cmp r3, #0
|
|
800c842: d010 beq.n 800c866 <xQueueGenericSend+0x112>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800c844: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c846: 3324 adds r3, #36 @ 0x24
|
|
800c848: 4618 mov r0, r3
|
|
800c84a: f001 f95f bl 800db0c <xTaskRemoveFromEventList>
|
|
800c84e: 4603 mov r3, r0
|
|
800c850: 2b00 cmp r3, #0
|
|
800c852: d013 beq.n 800c87c <xQueueGenericSend+0x128>
|
|
{
|
|
/* The unblocked task has a priority higher than
|
|
our own so yield immediately. Yes it is ok to do
|
|
this from within the critical section - the kernel
|
|
takes care of that. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800c854: 4b3f ldr r3, [pc, #252] @ (800c954 <xQueueGenericSend+0x200>)
|
|
800c856: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800c85a: 601a str r2, [r3, #0]
|
|
800c85c: f3bf 8f4f dsb sy
|
|
800c860: f3bf 8f6f isb sy
|
|
800c864: e00a b.n 800c87c <xQueueGenericSend+0x128>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else if( xYieldRequired != pdFALSE )
|
|
800c866: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800c868: 2b00 cmp r3, #0
|
|
800c86a: d007 beq.n 800c87c <xQueueGenericSend+0x128>
|
|
{
|
|
/* This path is a special case that will only get
|
|
executed if the task was holding multiple mutexes and
|
|
the mutexes were given back in an order that is
|
|
different to that in which they were taken. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800c86c: 4b39 ldr r3, [pc, #228] @ (800c954 <xQueueGenericSend+0x200>)
|
|
800c86e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800c872: 601a str r2, [r3, #0]
|
|
800c874: f3bf 8f4f dsb sy
|
|
800c878: f3bf 8f6f isb sy
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
taskEXIT_CRITICAL();
|
|
800c87c: f002 faa6 bl 800edcc <vPortExitCritical>
|
|
return pdPASS;
|
|
800c880: 2301 movs r3, #1
|
|
800c882: e063 b.n 800c94c <xQueueGenericSend+0x1f8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
800c884: 687b ldr r3, [r7, #4]
|
|
800c886: 2b00 cmp r3, #0
|
|
800c888: d103 bne.n 800c892 <xQueueGenericSend+0x13e>
|
|
{
|
|
/* The queue was full and no block time is specified (or
|
|
the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
800c88a: f002 fa9f bl 800edcc <vPortExitCritical>
|
|
|
|
/* Return to the original privilege level before exiting
|
|
the function. */
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
800c88e: 2300 movs r3, #0
|
|
800c890: e05c b.n 800c94c <xQueueGenericSend+0x1f8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
800c892: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800c894: 2b00 cmp r3, #0
|
|
800c896: d106 bne.n 800c8a6 <xQueueGenericSend+0x152>
|
|
{
|
|
/* The queue was full and a block time was specified so
|
|
configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
800c898: f107 0314 add.w r3, r7, #20
|
|
800c89c: 4618 mov r0, r3
|
|
800c89e: f001 f999 bl 800dbd4 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
800c8a2: 2301 movs r3, #1
|
|
800c8a4: 637b str r3, [r7, #52] @ 0x34
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800c8a6: f002 fa91 bl 800edcc <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
800c8aa: f000 ff09 bl 800d6c0 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
800c8ae: f002 fa5b bl 800ed68 <vPortEnterCritical>
|
|
800c8b2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c8b4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800c8b8: b25b sxtb r3, r3
|
|
800c8ba: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800c8be: d103 bne.n 800c8c8 <xQueueGenericSend+0x174>
|
|
800c8c0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c8c2: 2200 movs r2, #0
|
|
800c8c4: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800c8c8: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c8ca: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800c8ce: b25b sxtb r3, r3
|
|
800c8d0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800c8d4: d103 bne.n 800c8de <xQueueGenericSend+0x18a>
|
|
800c8d6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c8d8: 2200 movs r2, #0
|
|
800c8da: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800c8de: f002 fa75 bl 800edcc <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
800c8e2: 1d3a adds r2, r7, #4
|
|
800c8e4: f107 0314 add.w r3, r7, #20
|
|
800c8e8: 4611 mov r1, r2
|
|
800c8ea: 4618 mov r0, r3
|
|
800c8ec: f001 f988 bl 800dc00 <xTaskCheckForTimeOut>
|
|
800c8f0: 4603 mov r3, r0
|
|
800c8f2: 2b00 cmp r3, #0
|
|
800c8f4: d124 bne.n 800c940 <xQueueGenericSend+0x1ec>
|
|
{
|
|
if( prvIsQueueFull( pxQueue ) != pdFALSE )
|
|
800c8f6: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800c8f8: f000 fc5e bl 800d1b8 <prvIsQueueFull>
|
|
800c8fc: 4603 mov r3, r0
|
|
800c8fe: 2b00 cmp r3, #0
|
|
800c900: d018 beq.n 800c934 <xQueueGenericSend+0x1e0>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
|
|
800c902: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800c904: 3310 adds r3, #16
|
|
800c906: 687a ldr r2, [r7, #4]
|
|
800c908: 4611 mov r1, r2
|
|
800c90a: 4618 mov r0, r3
|
|
800c90c: f001 f8ac bl 800da68 <vTaskPlaceOnEventList>
|
|
/* Unlocking the queue means queue events can effect the
|
|
event list. It is possible that interrupts occurring now
|
|
remove this task from the event list again - but as the
|
|
scheduler is suspended the task will go onto the pending
|
|
ready last instead of the actual ready list. */
|
|
prvUnlockQueue( pxQueue );
|
|
800c910: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800c912: f000 fbe9 bl 800d0e8 <prvUnlockQueue>
|
|
/* Resuming the scheduler will move tasks from the pending
|
|
ready list into the ready list - so it is feasible that this
|
|
task is already in a ready list before it yields - in which
|
|
case the yield will not cause a context switch unless there
|
|
is also a higher priority task in the pending ready list. */
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800c916: f000 fee1 bl 800d6dc <xTaskResumeAll>
|
|
800c91a: 4603 mov r3, r0
|
|
800c91c: 2b00 cmp r3, #0
|
|
800c91e: f47f af7c bne.w 800c81a <xQueueGenericSend+0xc6>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800c922: 4b0c ldr r3, [pc, #48] @ (800c954 <xQueueGenericSend+0x200>)
|
|
800c924: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800c928: 601a str r2, [r3, #0]
|
|
800c92a: f3bf 8f4f dsb sy
|
|
800c92e: f3bf 8f6f isb sy
|
|
800c932: e772 b.n 800c81a <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Try again. */
|
|
prvUnlockQueue( pxQueue );
|
|
800c934: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800c936: f000 fbd7 bl 800d0e8 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800c93a: f000 fecf bl 800d6dc <xTaskResumeAll>
|
|
800c93e: e76c b.n 800c81a <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* The timeout has expired. */
|
|
prvUnlockQueue( pxQueue );
|
|
800c940: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800c942: f000 fbd1 bl 800d0e8 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800c946: f000 fec9 bl 800d6dc <xTaskResumeAll>
|
|
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
800c94a: 2300 movs r3, #0
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
800c94c: 4618 mov r0, r3
|
|
800c94e: 3738 adds r7, #56 @ 0x38
|
|
800c950: 46bd mov sp, r7
|
|
800c952: bd80 pop {r7, pc}
|
|
800c954: e000ed04 .word 0xe000ed04
|
|
|
|
0800c958 <xQueueGenericSendFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
|
|
{
|
|
800c958: b580 push {r7, lr}
|
|
800c95a: b090 sub sp, #64 @ 0x40
|
|
800c95c: af00 add r7, sp, #0
|
|
800c95e: 60f8 str r0, [r7, #12]
|
|
800c960: 60b9 str r1, [r7, #8]
|
|
800c962: 607a str r2, [r7, #4]
|
|
800c964: 603b str r3, [r7, #0]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800c966: 68fb ldr r3, [r7, #12]
|
|
800c968: 63bb str r3, [r7, #56] @ 0x38
|
|
|
|
configASSERT( pxQueue );
|
|
800c96a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800c96c: 2b00 cmp r3, #0
|
|
800c96e: d10b bne.n 800c988 <xQueueGenericSendFromISR+0x30>
|
|
__asm volatile
|
|
800c970: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c974: f383 8811 msr BASEPRI, r3
|
|
800c978: f3bf 8f6f isb sy
|
|
800c97c: f3bf 8f4f dsb sy
|
|
800c980: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
800c982: bf00 nop
|
|
800c984: bf00 nop
|
|
800c986: e7fd b.n 800c984 <xQueueGenericSendFromISR+0x2c>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800c988: 68bb ldr r3, [r7, #8]
|
|
800c98a: 2b00 cmp r3, #0
|
|
800c98c: d103 bne.n 800c996 <xQueueGenericSendFromISR+0x3e>
|
|
800c98e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800c990: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800c992: 2b00 cmp r3, #0
|
|
800c994: d101 bne.n 800c99a <xQueueGenericSendFromISR+0x42>
|
|
800c996: 2301 movs r3, #1
|
|
800c998: e000 b.n 800c99c <xQueueGenericSendFromISR+0x44>
|
|
800c99a: 2300 movs r3, #0
|
|
800c99c: 2b00 cmp r3, #0
|
|
800c99e: d10b bne.n 800c9b8 <xQueueGenericSendFromISR+0x60>
|
|
__asm volatile
|
|
800c9a0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c9a4: f383 8811 msr BASEPRI, r3
|
|
800c9a8: f3bf 8f6f isb sy
|
|
800c9ac: f3bf 8f4f dsb sy
|
|
800c9b0: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
800c9b2: bf00 nop
|
|
800c9b4: bf00 nop
|
|
800c9b6: e7fd b.n 800c9b4 <xQueueGenericSendFromISR+0x5c>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
800c9b8: 683b ldr r3, [r7, #0]
|
|
800c9ba: 2b02 cmp r3, #2
|
|
800c9bc: d103 bne.n 800c9c6 <xQueueGenericSendFromISR+0x6e>
|
|
800c9be: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800c9c0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800c9c2: 2b01 cmp r3, #1
|
|
800c9c4: d101 bne.n 800c9ca <xQueueGenericSendFromISR+0x72>
|
|
800c9c6: 2301 movs r3, #1
|
|
800c9c8: e000 b.n 800c9cc <xQueueGenericSendFromISR+0x74>
|
|
800c9ca: 2300 movs r3, #0
|
|
800c9cc: 2b00 cmp r3, #0
|
|
800c9ce: d10b bne.n 800c9e8 <xQueueGenericSendFromISR+0x90>
|
|
__asm volatile
|
|
800c9d0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c9d4: f383 8811 msr BASEPRI, r3
|
|
800c9d8: f3bf 8f6f isb sy
|
|
800c9dc: f3bf 8f4f dsb sy
|
|
800c9e0: 623b str r3, [r7, #32]
|
|
}
|
|
800c9e2: bf00 nop
|
|
800c9e4: bf00 nop
|
|
800c9e6: e7fd b.n 800c9e4 <xQueueGenericSendFromISR+0x8c>
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
800c9e8: f002 fa9e bl 800ef28 <vPortValidateInterruptPriority>
|
|
|
|
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
800c9ec: f3ef 8211 mrs r2, BASEPRI
|
|
800c9f0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c9f4: f383 8811 msr BASEPRI, r3
|
|
800c9f8: f3bf 8f6f isb sy
|
|
800c9fc: f3bf 8f4f dsb sy
|
|
800ca00: 61fa str r2, [r7, #28]
|
|
800ca02: 61bb str r3, [r7, #24]
|
|
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
|
|
/* This return will not be reached but is necessary to prevent compiler
|
|
warnings. */
|
|
return ulOriginalBASEPRI;
|
|
800ca04: 69fb ldr r3, [r7, #28]
|
|
/* Similar to xQueueGenericSend, except without blocking if there is no room
|
|
in the queue. Also don't directly wake a task that was blocked on a queue
|
|
read, instead return a flag to say whether a context switch is required or
|
|
not (i.e. has a task with a higher priority than us been woken by this
|
|
post). */
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
800ca06: 637b str r3, [r7, #52] @ 0x34
|
|
{
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
800ca08: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ca0a: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800ca0c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ca0e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800ca10: 429a cmp r2, r3
|
|
800ca12: d302 bcc.n 800ca1a <xQueueGenericSendFromISR+0xc2>
|
|
800ca14: 683b ldr r3, [r7, #0]
|
|
800ca16: 2b02 cmp r3, #2
|
|
800ca18: d12f bne.n 800ca7a <xQueueGenericSendFromISR+0x122>
|
|
{
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
|
800ca1a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ca1c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800ca20: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800ca24: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ca26: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800ca28: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
|
|
semaphore or mutex. That means prvCopyDataToQueue() cannot result
|
|
in a task disinheriting a priority and prvCopyDataToQueue() can be
|
|
called here even though the disinherit function does not check if
|
|
the scheduler is suspended before accessing the ready lists. */
|
|
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
800ca2a: 683a ldr r2, [r7, #0]
|
|
800ca2c: 68b9 ldr r1, [r7, #8]
|
|
800ca2e: 6bb8 ldr r0, [r7, #56] @ 0x38
|
|
800ca30: f000 faca bl 800cfc8 <prvCopyDataToQueue>
|
|
|
|
/* The event list is not altered if the queue is locked. This will
|
|
be done when the queue is unlocked later. */
|
|
if( cTxLock == queueUNLOCKED )
|
|
800ca34: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33
|
|
800ca38: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800ca3c: d112 bne.n 800ca64 <xQueueGenericSendFromISR+0x10c>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800ca3e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ca40: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800ca42: 2b00 cmp r3, #0
|
|
800ca44: d016 beq.n 800ca74 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800ca46: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ca48: 3324 adds r3, #36 @ 0x24
|
|
800ca4a: 4618 mov r0, r3
|
|
800ca4c: f001 f85e bl 800db0c <xTaskRemoveFromEventList>
|
|
800ca50: 4603 mov r3, r0
|
|
800ca52: 2b00 cmp r3, #0
|
|
800ca54: d00e beq.n 800ca74 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
/* The task waiting has a higher priority so record that a
|
|
context switch is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
800ca56: 687b ldr r3, [r7, #4]
|
|
800ca58: 2b00 cmp r3, #0
|
|
800ca5a: d00b beq.n 800ca74 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
800ca5c: 687b ldr r3, [r7, #4]
|
|
800ca5e: 2201 movs r2, #1
|
|
800ca60: 601a str r2, [r3, #0]
|
|
800ca62: e007 b.n 800ca74 <xQueueGenericSendFromISR+0x11c>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
knows that data was posted while it was locked. */
|
|
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
|
|
800ca64: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
800ca68: 3301 adds r3, #1
|
|
800ca6a: b2db uxtb r3, r3
|
|
800ca6c: b25a sxtb r2, r3
|
|
800ca6e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ca70: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
800ca74: 2301 movs r3, #1
|
|
800ca76: 63fb str r3, [r7, #60] @ 0x3c
|
|
{
|
|
800ca78: e001 b.n 800ca7e <xQueueGenericSendFromISR+0x126>
|
|
}
|
|
else
|
|
{
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
|
xReturn = errQUEUE_FULL;
|
|
800ca7a: 2300 movs r3, #0
|
|
800ca7c: 63fb str r3, [r7, #60] @ 0x3c
|
|
800ca7e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800ca80: 617b str r3, [r7, #20]
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
|
{
|
|
__asm volatile
|
|
800ca82: 697b ldr r3, [r7, #20]
|
|
800ca84: f383 8811 msr BASEPRI, r3
|
|
(
|
|
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
|
|
);
|
|
}
|
|
800ca88: bf00 nop
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800ca8a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
}
|
|
800ca8c: 4618 mov r0, r3
|
|
800ca8e: 3740 adds r7, #64 @ 0x40
|
|
800ca90: 46bd mov sp, r7
|
|
800ca92: bd80 pop {r7, pc}
|
|
|
|
0800ca94 <xQueueGiveFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
|
|
{
|
|
800ca94: b580 push {r7, lr}
|
|
800ca96: b08e sub sp, #56 @ 0x38
|
|
800ca98: af00 add r7, sp, #0
|
|
800ca9a: 6078 str r0, [r7, #4]
|
|
800ca9c: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800ca9e: 687b ldr r3, [r7, #4]
|
|
800caa0: 633b str r3, [r7, #48] @ 0x30
|
|
item size is 0. Don't directly wake a task that was blocked on a queue
|
|
read, instead return a flag to say whether a context switch is required or
|
|
not (i.e. has a task with a higher priority than us been woken by this
|
|
post). */
|
|
|
|
configASSERT( pxQueue );
|
|
800caa2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800caa4: 2b00 cmp r3, #0
|
|
800caa6: d10b bne.n 800cac0 <xQueueGiveFromISR+0x2c>
|
|
__asm volatile
|
|
800caa8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800caac: f383 8811 msr BASEPRI, r3
|
|
800cab0: f3bf 8f6f isb sy
|
|
800cab4: f3bf 8f4f dsb sy
|
|
800cab8: 623b str r3, [r7, #32]
|
|
}
|
|
800caba: bf00 nop
|
|
800cabc: bf00 nop
|
|
800cabe: e7fd b.n 800cabc <xQueueGiveFromISR+0x28>
|
|
|
|
/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
|
|
if the item size is not 0. */
|
|
configASSERT( pxQueue->uxItemSize == 0 );
|
|
800cac0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cac2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800cac4: 2b00 cmp r3, #0
|
|
800cac6: d00b beq.n 800cae0 <xQueueGiveFromISR+0x4c>
|
|
__asm volatile
|
|
800cac8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cacc: f383 8811 msr BASEPRI, r3
|
|
800cad0: f3bf 8f6f isb sy
|
|
800cad4: f3bf 8f4f dsb sy
|
|
800cad8: 61fb str r3, [r7, #28]
|
|
}
|
|
800cada: bf00 nop
|
|
800cadc: bf00 nop
|
|
800cade: e7fd b.n 800cadc <xQueueGiveFromISR+0x48>
|
|
|
|
/* Normally a mutex would not be given from an interrupt, especially if
|
|
there is a mutex holder, as priority inheritance makes no sense for an
|
|
interrupts, only tasks. */
|
|
configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
|
|
800cae0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cae2: 681b ldr r3, [r3, #0]
|
|
800cae4: 2b00 cmp r3, #0
|
|
800cae6: d103 bne.n 800caf0 <xQueueGiveFromISR+0x5c>
|
|
800cae8: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800caea: 689b ldr r3, [r3, #8]
|
|
800caec: 2b00 cmp r3, #0
|
|
800caee: d101 bne.n 800caf4 <xQueueGiveFromISR+0x60>
|
|
800caf0: 2301 movs r3, #1
|
|
800caf2: e000 b.n 800caf6 <xQueueGiveFromISR+0x62>
|
|
800caf4: 2300 movs r3, #0
|
|
800caf6: 2b00 cmp r3, #0
|
|
800caf8: d10b bne.n 800cb12 <xQueueGiveFromISR+0x7e>
|
|
__asm volatile
|
|
800cafa: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cafe: f383 8811 msr BASEPRI, r3
|
|
800cb02: f3bf 8f6f isb sy
|
|
800cb06: f3bf 8f4f dsb sy
|
|
800cb0a: 61bb str r3, [r7, #24]
|
|
}
|
|
800cb0c: bf00 nop
|
|
800cb0e: bf00 nop
|
|
800cb10: e7fd b.n 800cb0e <xQueueGiveFromISR+0x7a>
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
800cb12: f002 fa09 bl 800ef28 <vPortValidateInterruptPriority>
|
|
__asm volatile
|
|
800cb16: f3ef 8211 mrs r2, BASEPRI
|
|
800cb1a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cb1e: f383 8811 msr BASEPRI, r3
|
|
800cb22: f3bf 8f6f isb sy
|
|
800cb26: f3bf 8f4f dsb sy
|
|
800cb2a: 617a str r2, [r7, #20]
|
|
800cb2c: 613b str r3, [r7, #16]
|
|
return ulOriginalBASEPRI;
|
|
800cb2e: 697b ldr r3, [r7, #20]
|
|
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
800cb30: 62fb str r3, [r7, #44] @ 0x2c
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800cb32: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cb34: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800cb36: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* When the queue is used to implement a semaphore no data is ever
|
|
moved through the queue but it is still valid to see if the queue 'has
|
|
space'. */
|
|
if( uxMessagesWaiting < pxQueue->uxLength )
|
|
800cb38: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cb3a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800cb3c: 6aba ldr r2, [r7, #40] @ 0x28
|
|
800cb3e: 429a cmp r2, r3
|
|
800cb40: d22b bcs.n 800cb9a <xQueueGiveFromISR+0x106>
|
|
{
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
|
800cb42: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cb44: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800cb48: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
holder - and if there is a mutex holder then the mutex cannot be
|
|
given from an ISR. As this is the ISR version of the function it
|
|
can be assumed there is no mutex holder and no need to determine if
|
|
priority disinheritance is needed. Simply increase the count of
|
|
messages (semaphores) available. */
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
|
800cb4c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cb4e: 1c5a adds r2, r3, #1
|
|
800cb50: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cb52: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* The event list is not altered if the queue is locked. This will
|
|
be done when the queue is unlocked later. */
|
|
if( cTxLock == queueUNLOCKED )
|
|
800cb54: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27
|
|
800cb58: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800cb5c: d112 bne.n 800cb84 <xQueueGiveFromISR+0xf0>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800cb5e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cb60: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800cb62: 2b00 cmp r3, #0
|
|
800cb64: d016 beq.n 800cb94 <xQueueGiveFromISR+0x100>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800cb66: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cb68: 3324 adds r3, #36 @ 0x24
|
|
800cb6a: 4618 mov r0, r3
|
|
800cb6c: f000 ffce bl 800db0c <xTaskRemoveFromEventList>
|
|
800cb70: 4603 mov r3, r0
|
|
800cb72: 2b00 cmp r3, #0
|
|
800cb74: d00e beq.n 800cb94 <xQueueGiveFromISR+0x100>
|
|
{
|
|
/* The task waiting has a higher priority so record that a
|
|
context switch is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
800cb76: 683b ldr r3, [r7, #0]
|
|
800cb78: 2b00 cmp r3, #0
|
|
800cb7a: d00b beq.n 800cb94 <xQueueGiveFromISR+0x100>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
800cb7c: 683b ldr r3, [r7, #0]
|
|
800cb7e: 2201 movs r2, #1
|
|
800cb80: 601a str r2, [r3, #0]
|
|
800cb82: e007 b.n 800cb94 <xQueueGiveFromISR+0x100>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
knows that data was posted while it was locked. */
|
|
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
|
|
800cb84: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800cb88: 3301 adds r3, #1
|
|
800cb8a: b2db uxtb r3, r3
|
|
800cb8c: b25a sxtb r2, r3
|
|
800cb8e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cb90: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
800cb94: 2301 movs r3, #1
|
|
800cb96: 637b str r3, [r7, #52] @ 0x34
|
|
800cb98: e001 b.n 800cb9e <xQueueGiveFromISR+0x10a>
|
|
}
|
|
else
|
|
{
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
|
xReturn = errQUEUE_FULL;
|
|
800cb9a: 2300 movs r3, #0
|
|
800cb9c: 637b str r3, [r7, #52] @ 0x34
|
|
800cb9e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cba0: 60fb str r3, [r7, #12]
|
|
__asm volatile
|
|
800cba2: 68fb ldr r3, [r7, #12]
|
|
800cba4: f383 8811 msr BASEPRI, r3
|
|
}
|
|
800cba8: bf00 nop
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800cbaa: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
}
|
|
800cbac: 4618 mov r0, r3
|
|
800cbae: 3738 adds r7, #56 @ 0x38
|
|
800cbb0: 46bd mov sp, r7
|
|
800cbb2: bd80 pop {r7, pc}
|
|
|
|
0800cbb4 <xQueueReceive>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
|
|
{
|
|
800cbb4: b580 push {r7, lr}
|
|
800cbb6: b08c sub sp, #48 @ 0x30
|
|
800cbb8: af00 add r7, sp, #0
|
|
800cbba: 60f8 str r0, [r7, #12]
|
|
800cbbc: 60b9 str r1, [r7, #8]
|
|
800cbbe: 607a str r2, [r7, #4]
|
|
BaseType_t xEntryTimeSet = pdFALSE;
|
|
800cbc0: 2300 movs r3, #0
|
|
800cbc2: 62fb str r3, [r7, #44] @ 0x2c
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800cbc4: 68fb ldr r3, [r7, #12]
|
|
800cbc6: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check the pointer is not NULL. */
|
|
configASSERT( ( pxQueue ) );
|
|
800cbc8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cbca: 2b00 cmp r3, #0
|
|
800cbcc: d10b bne.n 800cbe6 <xQueueReceive+0x32>
|
|
__asm volatile
|
|
800cbce: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cbd2: f383 8811 msr BASEPRI, r3
|
|
800cbd6: f3bf 8f6f isb sy
|
|
800cbda: f3bf 8f4f dsb sy
|
|
800cbde: 623b str r3, [r7, #32]
|
|
}
|
|
800cbe0: bf00 nop
|
|
800cbe2: bf00 nop
|
|
800cbe4: e7fd b.n 800cbe2 <xQueueReceive+0x2e>
|
|
|
|
/* The buffer into which data is received can only be NULL if the data size
|
|
is zero (so no data is copied into the buffer. */
|
|
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800cbe6: 68bb ldr r3, [r7, #8]
|
|
800cbe8: 2b00 cmp r3, #0
|
|
800cbea: d103 bne.n 800cbf4 <xQueueReceive+0x40>
|
|
800cbec: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cbee: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800cbf0: 2b00 cmp r3, #0
|
|
800cbf2: d101 bne.n 800cbf8 <xQueueReceive+0x44>
|
|
800cbf4: 2301 movs r3, #1
|
|
800cbf6: e000 b.n 800cbfa <xQueueReceive+0x46>
|
|
800cbf8: 2300 movs r3, #0
|
|
800cbfa: 2b00 cmp r3, #0
|
|
800cbfc: d10b bne.n 800cc16 <xQueueReceive+0x62>
|
|
__asm volatile
|
|
800cbfe: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cc02: f383 8811 msr BASEPRI, r3
|
|
800cc06: f3bf 8f6f isb sy
|
|
800cc0a: f3bf 8f4f dsb sy
|
|
800cc0e: 61fb str r3, [r7, #28]
|
|
}
|
|
800cc10: bf00 nop
|
|
800cc12: bf00 nop
|
|
800cc14: e7fd b.n 800cc12 <xQueueReceive+0x5e>
|
|
|
|
/* Cannot block if the scheduler is suspended. */
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
800cc16: f001 f939 bl 800de8c <xTaskGetSchedulerState>
|
|
800cc1a: 4603 mov r3, r0
|
|
800cc1c: 2b00 cmp r3, #0
|
|
800cc1e: d102 bne.n 800cc26 <xQueueReceive+0x72>
|
|
800cc20: 687b ldr r3, [r7, #4]
|
|
800cc22: 2b00 cmp r3, #0
|
|
800cc24: d101 bne.n 800cc2a <xQueueReceive+0x76>
|
|
800cc26: 2301 movs r3, #1
|
|
800cc28: e000 b.n 800cc2c <xQueueReceive+0x78>
|
|
800cc2a: 2300 movs r3, #0
|
|
800cc2c: 2b00 cmp r3, #0
|
|
800cc2e: d10b bne.n 800cc48 <xQueueReceive+0x94>
|
|
__asm volatile
|
|
800cc30: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cc34: f383 8811 msr BASEPRI, r3
|
|
800cc38: f3bf 8f6f isb sy
|
|
800cc3c: f3bf 8f4f dsb sy
|
|
800cc40: 61bb str r3, [r7, #24]
|
|
}
|
|
800cc42: bf00 nop
|
|
800cc44: bf00 nop
|
|
800cc46: e7fd b.n 800cc44 <xQueueReceive+0x90>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
allow return statements within the function itself. This is done in the
|
|
interest of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800cc48: f002 f88e bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800cc4c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cc4e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800cc50: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Is there data in the queue now? To be running the calling task
|
|
must be the highest priority task wanting to access the queue. */
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
800cc52: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800cc54: 2b00 cmp r3, #0
|
|
800cc56: d01f beq.n 800cc98 <xQueueReceive+0xe4>
|
|
{
|
|
/* Data available, remove one item. */
|
|
prvCopyDataFromQueue( pxQueue, pvBuffer );
|
|
800cc58: 68b9 ldr r1, [r7, #8]
|
|
800cc5a: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800cc5c: f000 fa1e bl 800d09c <prvCopyDataFromQueue>
|
|
traceQUEUE_RECEIVE( pxQueue );
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
|
|
800cc60: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800cc62: 1e5a subs r2, r3, #1
|
|
800cc64: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cc66: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* There is now space in the queue, were any tasks waiting to
|
|
post to the queue? If so, unblock the highest priority waiting
|
|
task. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800cc68: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cc6a: 691b ldr r3, [r3, #16]
|
|
800cc6c: 2b00 cmp r3, #0
|
|
800cc6e: d00f beq.n 800cc90 <xQueueReceive+0xdc>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800cc70: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cc72: 3310 adds r3, #16
|
|
800cc74: 4618 mov r0, r3
|
|
800cc76: f000 ff49 bl 800db0c <xTaskRemoveFromEventList>
|
|
800cc7a: 4603 mov r3, r0
|
|
800cc7c: 2b00 cmp r3, #0
|
|
800cc7e: d007 beq.n 800cc90 <xQueueReceive+0xdc>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800cc80: 4b3c ldr r3, [pc, #240] @ (800cd74 <xQueueReceive+0x1c0>)
|
|
800cc82: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800cc86: 601a str r2, [r3, #0]
|
|
800cc88: f3bf 8f4f dsb sy
|
|
800cc8c: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
taskEXIT_CRITICAL();
|
|
800cc90: f002 f89c bl 800edcc <vPortExitCritical>
|
|
return pdPASS;
|
|
800cc94: 2301 movs r3, #1
|
|
800cc96: e069 b.n 800cd6c <xQueueReceive+0x1b8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
800cc98: 687b ldr r3, [r7, #4]
|
|
800cc9a: 2b00 cmp r3, #0
|
|
800cc9c: d103 bne.n 800cca6 <xQueueReceive+0xf2>
|
|
{
|
|
/* The queue was empty and no block time is specified (or
|
|
the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
800cc9e: f002 f895 bl 800edcc <vPortExitCritical>
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800cca2: 2300 movs r3, #0
|
|
800cca4: e062 b.n 800cd6c <xQueueReceive+0x1b8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
800cca6: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cca8: 2b00 cmp r3, #0
|
|
800ccaa: d106 bne.n 800ccba <xQueueReceive+0x106>
|
|
{
|
|
/* The queue was empty and a block time was specified so
|
|
configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
800ccac: f107 0310 add.w r3, r7, #16
|
|
800ccb0: 4618 mov r0, r3
|
|
800ccb2: f000 ff8f bl 800dbd4 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
800ccb6: 2301 movs r3, #1
|
|
800ccb8: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ccba: f002 f887 bl 800edcc <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
800ccbe: f000 fcff bl 800d6c0 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
800ccc2: f002 f851 bl 800ed68 <vPortEnterCritical>
|
|
800ccc6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ccc8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800cccc: b25b sxtb r3, r3
|
|
800ccce: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800ccd2: d103 bne.n 800ccdc <xQueueReceive+0x128>
|
|
800ccd4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ccd6: 2200 movs r2, #0
|
|
800ccd8: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800ccdc: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ccde: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800cce2: b25b sxtb r3, r3
|
|
800cce4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800cce8: d103 bne.n 800ccf2 <xQueueReceive+0x13e>
|
|
800ccea: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ccec: 2200 movs r2, #0
|
|
800ccee: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800ccf2: f002 f86b bl 800edcc <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
800ccf6: 1d3a adds r2, r7, #4
|
|
800ccf8: f107 0310 add.w r3, r7, #16
|
|
800ccfc: 4611 mov r1, r2
|
|
800ccfe: 4618 mov r0, r3
|
|
800cd00: f000 ff7e bl 800dc00 <xTaskCheckForTimeOut>
|
|
800cd04: 4603 mov r3, r0
|
|
800cd06: 2b00 cmp r3, #0
|
|
800cd08: d123 bne.n 800cd52 <xQueueReceive+0x19e>
|
|
{
|
|
/* The timeout has not expired. If the queue is still empty place
|
|
the task on the list of tasks waiting to receive from the queue. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800cd0a: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800cd0c: f000 fa3e bl 800d18c <prvIsQueueEmpty>
|
|
800cd10: 4603 mov r3, r0
|
|
800cd12: 2b00 cmp r3, #0
|
|
800cd14: d017 beq.n 800cd46 <xQueueReceive+0x192>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
|
|
800cd16: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800cd18: 3324 adds r3, #36 @ 0x24
|
|
800cd1a: 687a ldr r2, [r7, #4]
|
|
800cd1c: 4611 mov r1, r2
|
|
800cd1e: 4618 mov r0, r3
|
|
800cd20: f000 fea2 bl 800da68 <vTaskPlaceOnEventList>
|
|
prvUnlockQueue( pxQueue );
|
|
800cd24: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800cd26: f000 f9df bl 800d0e8 <prvUnlockQueue>
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800cd2a: f000 fcd7 bl 800d6dc <xTaskResumeAll>
|
|
800cd2e: 4603 mov r3, r0
|
|
800cd30: 2b00 cmp r3, #0
|
|
800cd32: d189 bne.n 800cc48 <xQueueReceive+0x94>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800cd34: 4b0f ldr r3, [pc, #60] @ (800cd74 <xQueueReceive+0x1c0>)
|
|
800cd36: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800cd3a: 601a str r2, [r3, #0]
|
|
800cd3c: f3bf 8f4f dsb sy
|
|
800cd40: f3bf 8f6f isb sy
|
|
800cd44: e780 b.n 800cc48 <xQueueReceive+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* The queue contains data again. Loop back to try and read the
|
|
data. */
|
|
prvUnlockQueue( pxQueue );
|
|
800cd46: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800cd48: f000 f9ce bl 800d0e8 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800cd4c: f000 fcc6 bl 800d6dc <xTaskResumeAll>
|
|
800cd50: e77a b.n 800cc48 <xQueueReceive+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* Timed out. If there is no data in the queue exit, otherwise loop
|
|
back and attempt to read the data. */
|
|
prvUnlockQueue( pxQueue );
|
|
800cd52: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800cd54: f000 f9c8 bl 800d0e8 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800cd58: f000 fcc0 bl 800d6dc <xTaskResumeAll>
|
|
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800cd5c: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800cd5e: f000 fa15 bl 800d18c <prvIsQueueEmpty>
|
|
800cd62: 4603 mov r3, r0
|
|
800cd64: 2b00 cmp r3, #0
|
|
800cd66: f43f af6f beq.w 800cc48 <xQueueReceive+0x94>
|
|
{
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800cd6a: 2300 movs r3, #0
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
800cd6c: 4618 mov r0, r3
|
|
800cd6e: 3730 adds r7, #48 @ 0x30
|
|
800cd70: 46bd mov sp, r7
|
|
800cd72: bd80 pop {r7, pc}
|
|
800cd74: e000ed04 .word 0xe000ed04
|
|
|
|
0800cd78 <xQueueSemaphoreTake>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
|
|
{
|
|
800cd78: b580 push {r7, lr}
|
|
800cd7a: b08e sub sp, #56 @ 0x38
|
|
800cd7c: af00 add r7, sp, #0
|
|
800cd7e: 6078 str r0, [r7, #4]
|
|
800cd80: 6039 str r1, [r7, #0]
|
|
BaseType_t xEntryTimeSet = pdFALSE;
|
|
800cd82: 2300 movs r3, #0
|
|
800cd84: 637b str r3, [r7, #52] @ 0x34
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800cd86: 687b ldr r3, [r7, #4]
|
|
800cd88: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
#if( configUSE_MUTEXES == 1 )
|
|
BaseType_t xInheritanceOccurred = pdFALSE;
|
|
800cd8a: 2300 movs r3, #0
|
|
800cd8c: 633b str r3, [r7, #48] @ 0x30
|
|
#endif
|
|
|
|
/* Check the queue pointer is not NULL. */
|
|
configASSERT( ( pxQueue ) );
|
|
800cd8e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cd90: 2b00 cmp r3, #0
|
|
800cd92: d10b bne.n 800cdac <xQueueSemaphoreTake+0x34>
|
|
__asm volatile
|
|
800cd94: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cd98: f383 8811 msr BASEPRI, r3
|
|
800cd9c: f3bf 8f6f isb sy
|
|
800cda0: f3bf 8f4f dsb sy
|
|
800cda4: 623b str r3, [r7, #32]
|
|
}
|
|
800cda6: bf00 nop
|
|
800cda8: bf00 nop
|
|
800cdaa: e7fd b.n 800cda8 <xQueueSemaphoreTake+0x30>
|
|
|
|
/* Check this really is a semaphore, in which case the item size will be
|
|
0. */
|
|
configASSERT( pxQueue->uxItemSize == 0 );
|
|
800cdac: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cdae: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800cdb0: 2b00 cmp r3, #0
|
|
800cdb2: d00b beq.n 800cdcc <xQueueSemaphoreTake+0x54>
|
|
__asm volatile
|
|
800cdb4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cdb8: f383 8811 msr BASEPRI, r3
|
|
800cdbc: f3bf 8f6f isb sy
|
|
800cdc0: f3bf 8f4f dsb sy
|
|
800cdc4: 61fb str r3, [r7, #28]
|
|
}
|
|
800cdc6: bf00 nop
|
|
800cdc8: bf00 nop
|
|
800cdca: e7fd b.n 800cdc8 <xQueueSemaphoreTake+0x50>
|
|
|
|
/* Cannot block if the scheduler is suspended. */
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
800cdcc: f001 f85e bl 800de8c <xTaskGetSchedulerState>
|
|
800cdd0: 4603 mov r3, r0
|
|
800cdd2: 2b00 cmp r3, #0
|
|
800cdd4: d102 bne.n 800cddc <xQueueSemaphoreTake+0x64>
|
|
800cdd6: 683b ldr r3, [r7, #0]
|
|
800cdd8: 2b00 cmp r3, #0
|
|
800cdda: d101 bne.n 800cde0 <xQueueSemaphoreTake+0x68>
|
|
800cddc: 2301 movs r3, #1
|
|
800cdde: e000 b.n 800cde2 <xQueueSemaphoreTake+0x6a>
|
|
800cde0: 2300 movs r3, #0
|
|
800cde2: 2b00 cmp r3, #0
|
|
800cde4: d10b bne.n 800cdfe <xQueueSemaphoreTake+0x86>
|
|
__asm volatile
|
|
800cde6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800cdea: f383 8811 msr BASEPRI, r3
|
|
800cdee: f3bf 8f6f isb sy
|
|
800cdf2: f3bf 8f4f dsb sy
|
|
800cdf6: 61bb str r3, [r7, #24]
|
|
}
|
|
800cdf8: bf00 nop
|
|
800cdfa: bf00 nop
|
|
800cdfc: e7fd b.n 800cdfa <xQueueSemaphoreTake+0x82>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
|
|
statements within the function itself. This is done in the interest
|
|
of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800cdfe: f001 ffb3 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
/* Semaphores are queues with an item size of 0, and where the
|
|
number of messages in the queue is the semaphore's count value. */
|
|
const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
|
|
800ce02: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ce04: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800ce06: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Is there data in the queue now? To be running the calling task
|
|
must be the highest priority task wanting to access the queue. */
|
|
if( uxSemaphoreCount > ( UBaseType_t ) 0 )
|
|
800ce08: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ce0a: 2b00 cmp r3, #0
|
|
800ce0c: d024 beq.n 800ce58 <xQueueSemaphoreTake+0xe0>
|
|
{
|
|
traceQUEUE_RECEIVE( pxQueue );
|
|
|
|
/* Semaphores are queues with a data size of zero and where the
|
|
messages waiting is the semaphore's count. Reduce the count. */
|
|
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
|
|
800ce0e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ce10: 1e5a subs r2, r3, #1
|
|
800ce12: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ce14: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
800ce16: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ce18: 681b ldr r3, [r3, #0]
|
|
800ce1a: 2b00 cmp r3, #0
|
|
800ce1c: d104 bne.n 800ce28 <xQueueSemaphoreTake+0xb0>
|
|
{
|
|
/* Record the information required to implement
|
|
priority inheritance should it become necessary. */
|
|
pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
|
|
800ce1e: f001 f9af bl 800e180 <pvTaskIncrementMutexHeldCount>
|
|
800ce22: 4602 mov r2, r0
|
|
800ce24: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ce26: 609a str r2, [r3, #8]
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
/* Check to see if other tasks are blocked waiting to give the
|
|
semaphore, and if so, unblock the highest priority such task. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800ce28: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ce2a: 691b ldr r3, [r3, #16]
|
|
800ce2c: 2b00 cmp r3, #0
|
|
800ce2e: d00f beq.n 800ce50 <xQueueSemaphoreTake+0xd8>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800ce30: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ce32: 3310 adds r3, #16
|
|
800ce34: 4618 mov r0, r3
|
|
800ce36: f000 fe69 bl 800db0c <xTaskRemoveFromEventList>
|
|
800ce3a: 4603 mov r3, r0
|
|
800ce3c: 2b00 cmp r3, #0
|
|
800ce3e: d007 beq.n 800ce50 <xQueueSemaphoreTake+0xd8>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800ce40: 4b54 ldr r3, [pc, #336] @ (800cf94 <xQueueSemaphoreTake+0x21c>)
|
|
800ce42: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800ce46: 601a str r2, [r3, #0]
|
|
800ce48: f3bf 8f4f dsb sy
|
|
800ce4c: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
taskEXIT_CRITICAL();
|
|
800ce50: f001 ffbc bl 800edcc <vPortExitCritical>
|
|
return pdPASS;
|
|
800ce54: 2301 movs r3, #1
|
|
800ce56: e098 b.n 800cf8a <xQueueSemaphoreTake+0x212>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
800ce58: 683b ldr r3, [r7, #0]
|
|
800ce5a: 2b00 cmp r3, #0
|
|
800ce5c: d112 bne.n 800ce84 <xQueueSemaphoreTake+0x10c>
|
|
/* For inheritance to have occurred there must have been an
|
|
initial timeout, and an adjusted timeout cannot become 0, as
|
|
if it were 0 the function would have exited. */
|
|
#if( configUSE_MUTEXES == 1 )
|
|
{
|
|
configASSERT( xInheritanceOccurred == pdFALSE );
|
|
800ce5e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800ce60: 2b00 cmp r3, #0
|
|
800ce62: d00b beq.n 800ce7c <xQueueSemaphoreTake+0x104>
|
|
__asm volatile
|
|
800ce64: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ce68: f383 8811 msr BASEPRI, r3
|
|
800ce6c: f3bf 8f6f isb sy
|
|
800ce70: f3bf 8f4f dsb sy
|
|
800ce74: 617b str r3, [r7, #20]
|
|
}
|
|
800ce76: bf00 nop
|
|
800ce78: bf00 nop
|
|
800ce7a: e7fd b.n 800ce78 <xQueueSemaphoreTake+0x100>
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
/* The semaphore count was 0 and no block time is specified
|
|
(or the block time has expired) so exit now. */
|
|
taskEXIT_CRITICAL();
|
|
800ce7c: f001 ffa6 bl 800edcc <vPortExitCritical>
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800ce80: 2300 movs r3, #0
|
|
800ce82: e082 b.n 800cf8a <xQueueSemaphoreTake+0x212>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
800ce84: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800ce86: 2b00 cmp r3, #0
|
|
800ce88: d106 bne.n 800ce98 <xQueueSemaphoreTake+0x120>
|
|
{
|
|
/* The semaphore count was 0 and a block time was specified
|
|
so configure the timeout structure ready to block. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
800ce8a: f107 030c add.w r3, r7, #12
|
|
800ce8e: 4618 mov r0, r3
|
|
800ce90: f000 fea0 bl 800dbd4 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
800ce94: 2301 movs r3, #1
|
|
800ce96: 637b str r3, [r7, #52] @ 0x34
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ce98: f001 ff98 bl 800edcc <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can give to and take from the semaphore
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
800ce9c: f000 fc10 bl 800d6c0 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
800cea0: f001 ff62 bl 800ed68 <vPortEnterCritical>
|
|
800cea4: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cea6: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800ceaa: b25b sxtb r3, r3
|
|
800ceac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800ceb0: d103 bne.n 800ceba <xQueueSemaphoreTake+0x142>
|
|
800ceb2: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ceb4: 2200 movs r2, #0
|
|
800ceb6: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800ceba: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cebc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800cec0: b25b sxtb r3, r3
|
|
800cec2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800cec6: d103 bne.n 800ced0 <xQueueSemaphoreTake+0x158>
|
|
800cec8: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ceca: 2200 movs r2, #0
|
|
800cecc: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800ced0: f001 ff7c bl 800edcc <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
800ced4: 463a mov r2, r7
|
|
800ced6: f107 030c add.w r3, r7, #12
|
|
800ceda: 4611 mov r1, r2
|
|
800cedc: 4618 mov r0, r3
|
|
800cede: f000 fe8f bl 800dc00 <xTaskCheckForTimeOut>
|
|
800cee2: 4603 mov r3, r0
|
|
800cee4: 2b00 cmp r3, #0
|
|
800cee6: d132 bne.n 800cf4e <xQueueSemaphoreTake+0x1d6>
|
|
{
|
|
/* A block time is specified and not expired. If the semaphore
|
|
count is 0 then enter the Blocked state to wait for a semaphore to
|
|
become available. As semaphores are implemented with queues the
|
|
queue being empty is equivalent to the semaphore count being 0. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800cee8: 6af8 ldr r0, [r7, #44] @ 0x2c
|
|
800ceea: f000 f94f bl 800d18c <prvIsQueueEmpty>
|
|
800ceee: 4603 mov r3, r0
|
|
800cef0: 2b00 cmp r3, #0
|
|
800cef2: d026 beq.n 800cf42 <xQueueSemaphoreTake+0x1ca>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
800cef4: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cef6: 681b ldr r3, [r3, #0]
|
|
800cef8: 2b00 cmp r3, #0
|
|
800cefa: d109 bne.n 800cf10 <xQueueSemaphoreTake+0x198>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800cefc: f001 ff34 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
|
|
800cf00: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cf02: 689b ldr r3, [r3, #8]
|
|
800cf04: 4618 mov r0, r3
|
|
800cf06: f000 ffdf bl 800dec8 <xTaskPriorityInherit>
|
|
800cf0a: 6338 str r0, [r7, #48] @ 0x30
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800cf0c: f001 ff5e bl 800edcc <vPortExitCritical>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
|
|
800cf10: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cf12: 3324 adds r3, #36 @ 0x24
|
|
800cf14: 683a ldr r2, [r7, #0]
|
|
800cf16: 4611 mov r1, r2
|
|
800cf18: 4618 mov r0, r3
|
|
800cf1a: f000 fda5 bl 800da68 <vTaskPlaceOnEventList>
|
|
prvUnlockQueue( pxQueue );
|
|
800cf1e: 6af8 ldr r0, [r7, #44] @ 0x2c
|
|
800cf20: f000 f8e2 bl 800d0e8 <prvUnlockQueue>
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800cf24: f000 fbda bl 800d6dc <xTaskResumeAll>
|
|
800cf28: 4603 mov r3, r0
|
|
800cf2a: 2b00 cmp r3, #0
|
|
800cf2c: f47f af67 bne.w 800cdfe <xQueueSemaphoreTake+0x86>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800cf30: 4b18 ldr r3, [pc, #96] @ (800cf94 <xQueueSemaphoreTake+0x21c>)
|
|
800cf32: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800cf36: 601a str r2, [r3, #0]
|
|
800cf38: f3bf 8f4f dsb sy
|
|
800cf3c: f3bf 8f6f isb sy
|
|
800cf40: e75d b.n 800cdfe <xQueueSemaphoreTake+0x86>
|
|
}
|
|
else
|
|
{
|
|
/* There was no timeout and the semaphore count was not 0, so
|
|
attempt to take the semaphore again. */
|
|
prvUnlockQueue( pxQueue );
|
|
800cf42: 6af8 ldr r0, [r7, #44] @ 0x2c
|
|
800cf44: f000 f8d0 bl 800d0e8 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800cf48: f000 fbc8 bl 800d6dc <xTaskResumeAll>
|
|
800cf4c: e757 b.n 800cdfe <xQueueSemaphoreTake+0x86>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Timed out. */
|
|
prvUnlockQueue( pxQueue );
|
|
800cf4e: 6af8 ldr r0, [r7, #44] @ 0x2c
|
|
800cf50: f000 f8ca bl 800d0e8 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800cf54: f000 fbc2 bl 800d6dc <xTaskResumeAll>
|
|
|
|
/* If the semaphore count is 0 exit now as the timeout has
|
|
expired. Otherwise return to attempt to take the semaphore that is
|
|
known to be available. As semaphores are implemented by queues the
|
|
queue being empty is equivalent to the semaphore count being 0. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800cf58: 6af8 ldr r0, [r7, #44] @ 0x2c
|
|
800cf5a: f000 f917 bl 800d18c <prvIsQueueEmpty>
|
|
800cf5e: 4603 mov r3, r0
|
|
800cf60: 2b00 cmp r3, #0
|
|
800cf62: f43f af4c beq.w 800cdfe <xQueueSemaphoreTake+0x86>
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
/* xInheritanceOccurred could only have be set if
|
|
pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
|
|
test the mutex type again to check it is actually a mutex. */
|
|
if( xInheritanceOccurred != pdFALSE )
|
|
800cf66: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800cf68: 2b00 cmp r3, #0
|
|
800cf6a: d00d beq.n 800cf88 <xQueueSemaphoreTake+0x210>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800cf6c: f001 fefc bl 800ed68 <vPortEnterCritical>
|
|
/* This task blocking on the mutex caused another
|
|
task to inherit this task's priority. Now this task
|
|
has timed out the priority should be disinherited
|
|
again, but only as low as the next highest priority
|
|
task that is waiting for the same mutex. */
|
|
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
|
|
800cf70: 6af8 ldr r0, [r7, #44] @ 0x2c
|
|
800cf72: f000 f811 bl 800cf98 <prvGetDisinheritPriorityAfterTimeout>
|
|
800cf76: 6278 str r0, [r7, #36] @ 0x24
|
|
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
|
|
800cf78: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800cf7a: 689b ldr r3, [r3, #8]
|
|
800cf7c: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
800cf7e: 4618 mov r0, r3
|
|
800cf80: f001 f87a bl 800e078 <vTaskPriorityDisinheritAfterTimeout>
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800cf84: f001 ff22 bl 800edcc <vPortExitCritical>
|
|
}
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800cf88: 2300 movs r3, #0
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
800cf8a: 4618 mov r0, r3
|
|
800cf8c: 3738 adds r7, #56 @ 0x38
|
|
800cf8e: 46bd mov sp, r7
|
|
800cf90: bd80 pop {r7, pc}
|
|
800cf92: bf00 nop
|
|
800cf94: e000ed04 .word 0xe000ed04
|
|
|
|
0800cf98 <prvGetDisinheritPriorityAfterTimeout>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configUSE_MUTEXES == 1 )
|
|
|
|
static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
|
|
{
|
|
800cf98: b480 push {r7}
|
|
800cf9a: b085 sub sp, #20
|
|
800cf9c: af00 add r7, sp, #0
|
|
800cf9e: 6078 str r0, [r7, #4]
|
|
priority, but the waiting task times out, then the holder should
|
|
disinherit the priority - but only down to the highest priority of any
|
|
other tasks that are waiting for the same mutex. For this purpose,
|
|
return the priority of the highest priority task that is waiting for the
|
|
mutex. */
|
|
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
|
|
800cfa0: 687b ldr r3, [r7, #4]
|
|
800cfa2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800cfa4: 2b00 cmp r3, #0
|
|
800cfa6: d006 beq.n 800cfb6 <prvGetDisinheritPriorityAfterTimeout+0x1e>
|
|
{
|
|
uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
|
|
800cfa8: 687b ldr r3, [r7, #4]
|
|
800cfaa: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800cfac: 681b ldr r3, [r3, #0]
|
|
800cfae: f1c3 0338 rsb r3, r3, #56 @ 0x38
|
|
800cfb2: 60fb str r3, [r7, #12]
|
|
800cfb4: e001 b.n 800cfba <prvGetDisinheritPriorityAfterTimeout+0x22>
|
|
}
|
|
else
|
|
{
|
|
uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
|
|
800cfb6: 2300 movs r3, #0
|
|
800cfb8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return uxHighestPriorityOfWaitingTasks;
|
|
800cfba: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800cfbc: 4618 mov r0, r3
|
|
800cfbe: 3714 adds r7, #20
|
|
800cfc0: 46bd mov sp, r7
|
|
800cfc2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800cfc6: 4770 bx lr
|
|
|
|
0800cfc8 <prvCopyDataToQueue>:
|
|
|
|
#endif /* configUSE_MUTEXES */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
|
|
{
|
|
800cfc8: b580 push {r7, lr}
|
|
800cfca: b086 sub sp, #24
|
|
800cfcc: af00 add r7, sp, #0
|
|
800cfce: 60f8 str r0, [r7, #12]
|
|
800cfd0: 60b9 str r1, [r7, #8]
|
|
800cfd2: 607a str r2, [r7, #4]
|
|
BaseType_t xReturn = pdFALSE;
|
|
800cfd4: 2300 movs r3, #0
|
|
800cfd6: 617b str r3, [r7, #20]
|
|
UBaseType_t uxMessagesWaiting;
|
|
|
|
/* This function is called from a critical section. */
|
|
|
|
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800cfd8: 68fb ldr r3, [r7, #12]
|
|
800cfda: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800cfdc: 613b str r3, [r7, #16]
|
|
|
|
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
|
|
800cfde: 68fb ldr r3, [r7, #12]
|
|
800cfe0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800cfe2: 2b00 cmp r3, #0
|
|
800cfe4: d10d bne.n 800d002 <prvCopyDataToQueue+0x3a>
|
|
{
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
800cfe6: 68fb ldr r3, [r7, #12]
|
|
800cfe8: 681b ldr r3, [r3, #0]
|
|
800cfea: 2b00 cmp r3, #0
|
|
800cfec: d14d bne.n 800d08a <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* The mutex is no longer being held. */
|
|
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
|
|
800cfee: 68fb ldr r3, [r7, #12]
|
|
800cff0: 689b ldr r3, [r3, #8]
|
|
800cff2: 4618 mov r0, r3
|
|
800cff4: f000 ffd0 bl 800df98 <xTaskPriorityDisinherit>
|
|
800cff8: 6178 str r0, [r7, #20]
|
|
pxQueue->u.xSemaphore.xMutexHolder = NULL;
|
|
800cffa: 68fb ldr r3, [r7, #12]
|
|
800cffc: 2200 movs r2, #0
|
|
800cffe: 609a str r2, [r3, #8]
|
|
800d000: e043 b.n 800d08a <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
}
|
|
else if( xPosition == queueSEND_TO_BACK )
|
|
800d002: 687b ldr r3, [r7, #4]
|
|
800d004: 2b00 cmp r3, #0
|
|
800d006: d119 bne.n 800d03c <prvCopyDataToQueue+0x74>
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
800d008: 68fb ldr r3, [r7, #12]
|
|
800d00a: 6858 ldr r0, [r3, #4]
|
|
800d00c: 68fb ldr r3, [r7, #12]
|
|
800d00e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d010: 461a mov r2, r3
|
|
800d012: 68b9 ldr r1, [r7, #8]
|
|
800d014: f003 fb7d bl 8010712 <memcpy>
|
|
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
800d018: 68fb ldr r3, [r7, #12]
|
|
800d01a: 685a ldr r2, [r3, #4]
|
|
800d01c: 68fb ldr r3, [r7, #12]
|
|
800d01e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d020: 441a add r2, r3
|
|
800d022: 68fb ldr r3, [r7, #12]
|
|
800d024: 605a str r2, [r3, #4]
|
|
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
800d026: 68fb ldr r3, [r7, #12]
|
|
800d028: 685a ldr r2, [r3, #4]
|
|
800d02a: 68fb ldr r3, [r7, #12]
|
|
800d02c: 689b ldr r3, [r3, #8]
|
|
800d02e: 429a cmp r2, r3
|
|
800d030: d32b bcc.n 800d08a <prvCopyDataToQueue+0xc2>
|
|
{
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
800d032: 68fb ldr r3, [r7, #12]
|
|
800d034: 681a ldr r2, [r3, #0]
|
|
800d036: 68fb ldr r3, [r7, #12]
|
|
800d038: 605a str r2, [r3, #4]
|
|
800d03a: e026 b.n 800d08a <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
|
|
800d03c: 68fb ldr r3, [r7, #12]
|
|
800d03e: 68d8 ldr r0, [r3, #12]
|
|
800d040: 68fb ldr r3, [r7, #12]
|
|
800d042: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d044: 461a mov r2, r3
|
|
800d046: 68b9 ldr r1, [r7, #8]
|
|
800d048: f003 fb63 bl 8010712 <memcpy>
|
|
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
|
|
800d04c: 68fb ldr r3, [r7, #12]
|
|
800d04e: 68da ldr r2, [r3, #12]
|
|
800d050: 68fb ldr r3, [r7, #12]
|
|
800d052: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d054: 425b negs r3, r3
|
|
800d056: 441a add r2, r3
|
|
800d058: 68fb ldr r3, [r7, #12]
|
|
800d05a: 60da str r2, [r3, #12]
|
|
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
800d05c: 68fb ldr r3, [r7, #12]
|
|
800d05e: 68da ldr r2, [r3, #12]
|
|
800d060: 68fb ldr r3, [r7, #12]
|
|
800d062: 681b ldr r3, [r3, #0]
|
|
800d064: 429a cmp r2, r3
|
|
800d066: d207 bcs.n 800d078 <prvCopyDataToQueue+0xb0>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
|
|
800d068: 68fb ldr r3, [r7, #12]
|
|
800d06a: 689a ldr r2, [r3, #8]
|
|
800d06c: 68fb ldr r3, [r7, #12]
|
|
800d06e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d070: 425b negs r3, r3
|
|
800d072: 441a add r2, r3
|
|
800d074: 68fb ldr r3, [r7, #12]
|
|
800d076: 60da str r2, [r3, #12]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( xPosition == queueOVERWRITE )
|
|
800d078: 687b ldr r3, [r7, #4]
|
|
800d07a: 2b02 cmp r3, #2
|
|
800d07c: d105 bne.n 800d08a <prvCopyDataToQueue+0xc2>
|
|
{
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
800d07e: 693b ldr r3, [r7, #16]
|
|
800d080: 2b00 cmp r3, #0
|
|
800d082: d002 beq.n 800d08a <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* An item is not being added but overwritten, so subtract
|
|
one from the recorded number of items in the queue so when
|
|
one is added again below the number of recorded items remains
|
|
correct. */
|
|
--uxMessagesWaiting;
|
|
800d084: 693b ldr r3, [r7, #16]
|
|
800d086: 3b01 subs r3, #1
|
|
800d088: 613b str r3, [r7, #16]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
|
800d08a: 693b ldr r3, [r7, #16]
|
|
800d08c: 1c5a adds r2, r3, #1
|
|
800d08e: 68fb ldr r3, [r7, #12]
|
|
800d090: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
return xReturn;
|
|
800d092: 697b ldr r3, [r7, #20]
|
|
}
|
|
800d094: 4618 mov r0, r3
|
|
800d096: 3718 adds r7, #24
|
|
800d098: 46bd mov sp, r7
|
|
800d09a: bd80 pop {r7, pc}
|
|
|
|
0800d09c <prvCopyDataFromQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
|
|
{
|
|
800d09c: b580 push {r7, lr}
|
|
800d09e: b082 sub sp, #8
|
|
800d0a0: af00 add r7, sp, #0
|
|
800d0a2: 6078 str r0, [r7, #4]
|
|
800d0a4: 6039 str r1, [r7, #0]
|
|
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
|
|
800d0a6: 687b ldr r3, [r7, #4]
|
|
800d0a8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d0aa: 2b00 cmp r3, #0
|
|
800d0ac: d018 beq.n 800d0e0 <prvCopyDataFromQueue+0x44>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
800d0ae: 687b ldr r3, [r7, #4]
|
|
800d0b0: 68da ldr r2, [r3, #12]
|
|
800d0b2: 687b ldr r3, [r7, #4]
|
|
800d0b4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d0b6: 441a add r2, r3
|
|
800d0b8: 687b ldr r3, [r7, #4]
|
|
800d0ba: 60da str r2, [r3, #12]
|
|
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
|
|
800d0bc: 687b ldr r3, [r7, #4]
|
|
800d0be: 68da ldr r2, [r3, #12]
|
|
800d0c0: 687b ldr r3, [r7, #4]
|
|
800d0c2: 689b ldr r3, [r3, #8]
|
|
800d0c4: 429a cmp r2, r3
|
|
800d0c6: d303 bcc.n 800d0d0 <prvCopyDataFromQueue+0x34>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
|
|
800d0c8: 687b ldr r3, [r7, #4]
|
|
800d0ca: 681a ldr r2, [r3, #0]
|
|
800d0cc: 687b ldr r3, [r7, #4]
|
|
800d0ce: 60da str r2, [r3, #12]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
800d0d0: 687b ldr r3, [r7, #4]
|
|
800d0d2: 68d9 ldr r1, [r3, #12]
|
|
800d0d4: 687b ldr r3, [r7, #4]
|
|
800d0d6: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d0d8: 461a mov r2, r3
|
|
800d0da: 6838 ldr r0, [r7, #0]
|
|
800d0dc: f003 fb19 bl 8010712 <memcpy>
|
|
}
|
|
}
|
|
800d0e0: bf00 nop
|
|
800d0e2: 3708 adds r7, #8
|
|
800d0e4: 46bd mov sp, r7
|
|
800d0e6: bd80 pop {r7, pc}
|
|
|
|
0800d0e8 <prvUnlockQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvUnlockQueue( Queue_t * const pxQueue )
|
|
{
|
|
800d0e8: b580 push {r7, lr}
|
|
800d0ea: b084 sub sp, #16
|
|
800d0ec: af00 add r7, sp, #0
|
|
800d0ee: 6078 str r0, [r7, #4]
|
|
|
|
/* The lock counts contains the number of extra data items placed or
|
|
removed from the queue while the queue was locked. When a queue is
|
|
locked items can be added or removed, but the event lists cannot be
|
|
updated. */
|
|
taskENTER_CRITICAL();
|
|
800d0f0: f001 fe3a bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
int8_t cTxLock = pxQueue->cTxLock;
|
|
800d0f4: 687b ldr r3, [r7, #4]
|
|
800d0f6: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800d0fa: 73fb strb r3, [r7, #15]
|
|
|
|
/* See if data was added to the queue while it was locked. */
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
800d0fc: e011 b.n 800d122 <prvUnlockQueue+0x3a>
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
/* Tasks that are removed from the event list will get added to
|
|
the pending ready list as the scheduler is still suspended. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800d0fe: 687b ldr r3, [r7, #4]
|
|
800d100: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800d102: 2b00 cmp r3, #0
|
|
800d104: d012 beq.n 800d12c <prvUnlockQueue+0x44>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800d106: 687b ldr r3, [r7, #4]
|
|
800d108: 3324 adds r3, #36 @ 0x24
|
|
800d10a: 4618 mov r0, r3
|
|
800d10c: f000 fcfe bl 800db0c <xTaskRemoveFromEventList>
|
|
800d110: 4603 mov r3, r0
|
|
800d112: 2b00 cmp r3, #0
|
|
800d114: d001 beq.n 800d11a <prvUnlockQueue+0x32>
|
|
{
|
|
/* The task waiting has a higher priority so record that
|
|
a context switch is required. */
|
|
vTaskMissedYield();
|
|
800d116: f000 fdd7 bl 800dcc8 <vTaskMissedYield>
|
|
break;
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
--cTxLock;
|
|
800d11a: 7bfb ldrb r3, [r7, #15]
|
|
800d11c: 3b01 subs r3, #1
|
|
800d11e: b2db uxtb r3, r3
|
|
800d120: 73fb strb r3, [r7, #15]
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
800d122: f997 300f ldrsb.w r3, [r7, #15]
|
|
800d126: 2b00 cmp r3, #0
|
|
800d128: dce9 bgt.n 800d0fe <prvUnlockQueue+0x16>
|
|
800d12a: e000 b.n 800d12e <prvUnlockQueue+0x46>
|
|
break;
|
|
800d12c: bf00 nop
|
|
}
|
|
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
800d12e: 687b ldr r3, [r7, #4]
|
|
800d130: 22ff movs r2, #255 @ 0xff
|
|
800d132: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800d136: f001 fe49 bl 800edcc <vPortExitCritical>
|
|
|
|
/* Do the same for the Rx lock. */
|
|
taskENTER_CRITICAL();
|
|
800d13a: f001 fe15 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
int8_t cRxLock = pxQueue->cRxLock;
|
|
800d13e: 687b ldr r3, [r7, #4]
|
|
800d140: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800d144: 73bb strb r3, [r7, #14]
|
|
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
800d146: e011 b.n 800d16c <prvUnlockQueue+0x84>
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800d148: 687b ldr r3, [r7, #4]
|
|
800d14a: 691b ldr r3, [r3, #16]
|
|
800d14c: 2b00 cmp r3, #0
|
|
800d14e: d012 beq.n 800d176 <prvUnlockQueue+0x8e>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800d150: 687b ldr r3, [r7, #4]
|
|
800d152: 3310 adds r3, #16
|
|
800d154: 4618 mov r0, r3
|
|
800d156: f000 fcd9 bl 800db0c <xTaskRemoveFromEventList>
|
|
800d15a: 4603 mov r3, r0
|
|
800d15c: 2b00 cmp r3, #0
|
|
800d15e: d001 beq.n 800d164 <prvUnlockQueue+0x7c>
|
|
{
|
|
vTaskMissedYield();
|
|
800d160: f000 fdb2 bl 800dcc8 <vTaskMissedYield>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
--cRxLock;
|
|
800d164: 7bbb ldrb r3, [r7, #14]
|
|
800d166: 3b01 subs r3, #1
|
|
800d168: b2db uxtb r3, r3
|
|
800d16a: 73bb strb r3, [r7, #14]
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
800d16c: f997 300e ldrsb.w r3, [r7, #14]
|
|
800d170: 2b00 cmp r3, #0
|
|
800d172: dce9 bgt.n 800d148 <prvUnlockQueue+0x60>
|
|
800d174: e000 b.n 800d178 <prvUnlockQueue+0x90>
|
|
}
|
|
else
|
|
{
|
|
break;
|
|
800d176: bf00 nop
|
|
}
|
|
}
|
|
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
800d178: 687b ldr r3, [r7, #4]
|
|
800d17a: 22ff movs r2, #255 @ 0xff
|
|
800d17c: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800d180: f001 fe24 bl 800edcc <vPortExitCritical>
|
|
}
|
|
800d184: bf00 nop
|
|
800d186: 3710 adds r7, #16
|
|
800d188: 46bd mov sp, r7
|
|
800d18a: bd80 pop {r7, pc}
|
|
|
|
0800d18c <prvIsQueueEmpty>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
|
|
{
|
|
800d18c: b580 push {r7, lr}
|
|
800d18e: b084 sub sp, #16
|
|
800d190: af00 add r7, sp, #0
|
|
800d192: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
800d194: f001 fde8 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
|
|
800d198: 687b ldr r3, [r7, #4]
|
|
800d19a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d19c: 2b00 cmp r3, #0
|
|
800d19e: d102 bne.n 800d1a6 <prvIsQueueEmpty+0x1a>
|
|
{
|
|
xReturn = pdTRUE;
|
|
800d1a0: 2301 movs r3, #1
|
|
800d1a2: 60fb str r3, [r7, #12]
|
|
800d1a4: e001 b.n 800d1aa <prvIsQueueEmpty+0x1e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800d1a6: 2300 movs r3, #0
|
|
800d1a8: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800d1aa: f001 fe0f bl 800edcc <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800d1ae: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800d1b0: 4618 mov r0, r3
|
|
800d1b2: 3710 adds r7, #16
|
|
800d1b4: 46bd mov sp, r7
|
|
800d1b6: bd80 pop {r7, pc}
|
|
|
|
0800d1b8 <prvIsQueueFull>:
|
|
return xReturn;
|
|
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
|
|
{
|
|
800d1b8: b580 push {r7, lr}
|
|
800d1ba: b084 sub sp, #16
|
|
800d1bc: af00 add r7, sp, #0
|
|
800d1be: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
800d1c0: f001 fdd2 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
|
|
800d1c4: 687b ldr r3, [r7, #4]
|
|
800d1c6: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800d1c8: 687b ldr r3, [r7, #4]
|
|
800d1ca: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800d1cc: 429a cmp r2, r3
|
|
800d1ce: d102 bne.n 800d1d6 <prvIsQueueFull+0x1e>
|
|
{
|
|
xReturn = pdTRUE;
|
|
800d1d0: 2301 movs r3, #1
|
|
800d1d2: 60fb str r3, [r7, #12]
|
|
800d1d4: e001 b.n 800d1da <prvIsQueueFull+0x22>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800d1d6: 2300 movs r3, #0
|
|
800d1d8: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800d1da: f001 fdf7 bl 800edcc <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800d1de: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800d1e0: 4618 mov r0, r3
|
|
800d1e2: 3710 adds r7, #16
|
|
800d1e4: 46bd mov sp, r7
|
|
800d1e6: bd80 pop {r7, pc}
|
|
|
|
0800d1e8 <vQueueAddToRegistry>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
|
|
|
void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
|
|
{
|
|
800d1e8: b480 push {r7}
|
|
800d1ea: b085 sub sp, #20
|
|
800d1ec: af00 add r7, sp, #0
|
|
800d1ee: 6078 str r0, [r7, #4]
|
|
800d1f0: 6039 str r1, [r7, #0]
|
|
UBaseType_t ux;
|
|
|
|
/* See if there is an empty space in the registry. A NULL name denotes
|
|
a free slot. */
|
|
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
|
|
800d1f2: 2300 movs r3, #0
|
|
800d1f4: 60fb str r3, [r7, #12]
|
|
800d1f6: e014 b.n 800d222 <vQueueAddToRegistry+0x3a>
|
|
{
|
|
if( xQueueRegistry[ ux ].pcQueueName == NULL )
|
|
800d1f8: 4a0f ldr r2, [pc, #60] @ (800d238 <vQueueAddToRegistry+0x50>)
|
|
800d1fa: 68fb ldr r3, [r7, #12]
|
|
800d1fc: f852 3033 ldr.w r3, [r2, r3, lsl #3]
|
|
800d200: 2b00 cmp r3, #0
|
|
800d202: d10b bne.n 800d21c <vQueueAddToRegistry+0x34>
|
|
{
|
|
/* Store the information on this queue. */
|
|
xQueueRegistry[ ux ].pcQueueName = pcQueueName;
|
|
800d204: 490c ldr r1, [pc, #48] @ (800d238 <vQueueAddToRegistry+0x50>)
|
|
800d206: 68fb ldr r3, [r7, #12]
|
|
800d208: 683a ldr r2, [r7, #0]
|
|
800d20a: f841 2033 str.w r2, [r1, r3, lsl #3]
|
|
xQueueRegistry[ ux ].xHandle = xQueue;
|
|
800d20e: 4a0a ldr r2, [pc, #40] @ (800d238 <vQueueAddToRegistry+0x50>)
|
|
800d210: 68fb ldr r3, [r7, #12]
|
|
800d212: 00db lsls r3, r3, #3
|
|
800d214: 4413 add r3, r2
|
|
800d216: 687a ldr r2, [r7, #4]
|
|
800d218: 605a str r2, [r3, #4]
|
|
|
|
traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
|
|
break;
|
|
800d21a: e006 b.n 800d22a <vQueueAddToRegistry+0x42>
|
|
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
|
|
800d21c: 68fb ldr r3, [r7, #12]
|
|
800d21e: 3301 adds r3, #1
|
|
800d220: 60fb str r3, [r7, #12]
|
|
800d222: 68fb ldr r3, [r7, #12]
|
|
800d224: 2b07 cmp r3, #7
|
|
800d226: d9e7 bls.n 800d1f8 <vQueueAddToRegistry+0x10>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
800d228: bf00 nop
|
|
800d22a: bf00 nop
|
|
800d22c: 3714 adds r7, #20
|
|
800d22e: 46bd mov sp, r7
|
|
800d230: f85d 7b04 ldr.w r7, [sp], #4
|
|
800d234: 4770 bx lr
|
|
800d236: bf00 nop
|
|
800d238: 20002340 .word 0x20002340
|
|
|
|
0800d23c <vQueueWaitForMessageRestricted>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_TIMERS == 1 )
|
|
|
|
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
|
|
{
|
|
800d23c: b580 push {r7, lr}
|
|
800d23e: b086 sub sp, #24
|
|
800d240: af00 add r7, sp, #0
|
|
800d242: 60f8 str r0, [r7, #12]
|
|
800d244: 60b9 str r1, [r7, #8]
|
|
800d246: 607a str r2, [r7, #4]
|
|
Queue_t * const pxQueue = xQueue;
|
|
800d248: 68fb ldr r3, [r7, #12]
|
|
800d24a: 617b str r3, [r7, #20]
|
|
will not actually cause the task to block, just place it on a blocked
|
|
list. It will not block until the scheduler is unlocked - at which
|
|
time a yield will be performed. If an item is added to the queue while
|
|
the queue is locked, and the calling task blocks on the queue, then the
|
|
calling task will be immediately unblocked when the queue is unlocked. */
|
|
prvLockQueue( pxQueue );
|
|
800d24c: f001 fd8c bl 800ed68 <vPortEnterCritical>
|
|
800d250: 697b ldr r3, [r7, #20]
|
|
800d252: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800d256: b25b sxtb r3, r3
|
|
800d258: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800d25c: d103 bne.n 800d266 <vQueueWaitForMessageRestricted+0x2a>
|
|
800d25e: 697b ldr r3, [r7, #20]
|
|
800d260: 2200 movs r2, #0
|
|
800d262: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800d266: 697b ldr r3, [r7, #20]
|
|
800d268: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800d26c: b25b sxtb r3, r3
|
|
800d26e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800d272: d103 bne.n 800d27c <vQueueWaitForMessageRestricted+0x40>
|
|
800d274: 697b ldr r3, [r7, #20]
|
|
800d276: 2200 movs r2, #0
|
|
800d278: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800d27c: f001 fda6 bl 800edcc <vPortExitCritical>
|
|
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
|
|
800d280: 697b ldr r3, [r7, #20]
|
|
800d282: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d284: 2b00 cmp r3, #0
|
|
800d286: d106 bne.n 800d296 <vQueueWaitForMessageRestricted+0x5a>
|
|
{
|
|
/* There is nothing in the queue, block for the specified period. */
|
|
vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
|
|
800d288: 697b ldr r3, [r7, #20]
|
|
800d28a: 3324 adds r3, #36 @ 0x24
|
|
800d28c: 687a ldr r2, [r7, #4]
|
|
800d28e: 68b9 ldr r1, [r7, #8]
|
|
800d290: 4618 mov r0, r3
|
|
800d292: f000 fc0f bl 800dab4 <vTaskPlaceOnEventListRestricted>
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
prvUnlockQueue( pxQueue );
|
|
800d296: 6978 ldr r0, [r7, #20]
|
|
800d298: f7ff ff26 bl 800d0e8 <prvUnlockQueue>
|
|
}
|
|
800d29c: bf00 nop
|
|
800d29e: 3718 adds r7, #24
|
|
800d2a0: 46bd mov sp, r7
|
|
800d2a2: bd80 pop {r7, pc}
|
|
|
|
0800d2a4 <xTaskCreateStatic>:
|
|
const uint32_t ulStackDepth,
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
StackType_t * const puxStackBuffer,
|
|
StaticTask_t * const pxTaskBuffer )
|
|
{
|
|
800d2a4: b580 push {r7, lr}
|
|
800d2a6: b08e sub sp, #56 @ 0x38
|
|
800d2a8: af04 add r7, sp, #16
|
|
800d2aa: 60f8 str r0, [r7, #12]
|
|
800d2ac: 60b9 str r1, [r7, #8]
|
|
800d2ae: 607a str r2, [r7, #4]
|
|
800d2b0: 603b str r3, [r7, #0]
|
|
TCB_t *pxNewTCB;
|
|
TaskHandle_t xReturn;
|
|
|
|
configASSERT( puxStackBuffer != NULL );
|
|
800d2b2: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800d2b4: 2b00 cmp r3, #0
|
|
800d2b6: d10b bne.n 800d2d0 <xTaskCreateStatic+0x2c>
|
|
__asm volatile
|
|
800d2b8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d2bc: f383 8811 msr BASEPRI, r3
|
|
800d2c0: f3bf 8f6f isb sy
|
|
800d2c4: f3bf 8f4f dsb sy
|
|
800d2c8: 623b str r3, [r7, #32]
|
|
}
|
|
800d2ca: bf00 nop
|
|
800d2cc: bf00 nop
|
|
800d2ce: e7fd b.n 800d2cc <xTaskCreateStatic+0x28>
|
|
configASSERT( pxTaskBuffer != NULL );
|
|
800d2d0: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800d2d2: 2b00 cmp r3, #0
|
|
800d2d4: d10b bne.n 800d2ee <xTaskCreateStatic+0x4a>
|
|
__asm volatile
|
|
800d2d6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d2da: f383 8811 msr BASEPRI, r3
|
|
800d2de: f3bf 8f6f isb sy
|
|
800d2e2: f3bf 8f4f dsb sy
|
|
800d2e6: 61fb str r3, [r7, #28]
|
|
}
|
|
800d2e8: bf00 nop
|
|
800d2ea: bf00 nop
|
|
800d2ec: e7fd b.n 800d2ea <xTaskCreateStatic+0x46>
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
/* Sanity check that the size of the structure used to declare a
|
|
variable of type StaticTask_t equals the size of the real task
|
|
structure. */
|
|
volatile size_t xSize = sizeof( StaticTask_t );
|
|
800d2ee: 235c movs r3, #92 @ 0x5c
|
|
800d2f0: 613b str r3, [r7, #16]
|
|
configASSERT( xSize == sizeof( TCB_t ) );
|
|
800d2f2: 693b ldr r3, [r7, #16]
|
|
800d2f4: 2b5c cmp r3, #92 @ 0x5c
|
|
800d2f6: d00b beq.n 800d310 <xTaskCreateStatic+0x6c>
|
|
__asm volatile
|
|
800d2f8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d2fc: f383 8811 msr BASEPRI, r3
|
|
800d300: f3bf 8f6f isb sy
|
|
800d304: f3bf 8f4f dsb sy
|
|
800d308: 61bb str r3, [r7, #24]
|
|
}
|
|
800d30a: bf00 nop
|
|
800d30c: bf00 nop
|
|
800d30e: e7fd b.n 800d30c <xTaskCreateStatic+0x68>
|
|
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
|
|
800d310: 693b ldr r3, [r7, #16]
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
|
|
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
|
|
800d312: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800d314: 2b00 cmp r3, #0
|
|
800d316: d01e beq.n 800d356 <xTaskCreateStatic+0xb2>
|
|
800d318: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800d31a: 2b00 cmp r3, #0
|
|
800d31c: d01b beq.n 800d356 <xTaskCreateStatic+0xb2>
|
|
{
|
|
/* The memory used for the task's TCB and stack are passed into this
|
|
function - use them. */
|
|
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
|
800d31e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800d320: 627b str r3, [r7, #36] @ 0x24
|
|
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
|
|
800d322: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800d324: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
800d326: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* Tasks can be created statically or dynamically, so note this
|
|
task was created statically in case the task is later deleted. */
|
|
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
|
|
800d328: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800d32a: 2202 movs r2, #2
|
|
800d32c: f883 2059 strb.w r2, [r3, #89] @ 0x59
|
|
}
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
|
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
|
|
800d330: 2300 movs r3, #0
|
|
800d332: 9303 str r3, [sp, #12]
|
|
800d334: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800d336: 9302 str r3, [sp, #8]
|
|
800d338: f107 0314 add.w r3, r7, #20
|
|
800d33c: 9301 str r3, [sp, #4]
|
|
800d33e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d340: 9300 str r3, [sp, #0]
|
|
800d342: 683b ldr r3, [r7, #0]
|
|
800d344: 687a ldr r2, [r7, #4]
|
|
800d346: 68b9 ldr r1, [r7, #8]
|
|
800d348: 68f8 ldr r0, [r7, #12]
|
|
800d34a: f000 f850 bl 800d3ee <prvInitialiseNewTask>
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
|
800d34e: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
800d350: f000 f8de bl 800d510 <prvAddNewTaskToReadyList>
|
|
800d354: e001 b.n 800d35a <xTaskCreateStatic+0xb6>
|
|
}
|
|
else
|
|
{
|
|
xReturn = NULL;
|
|
800d356: 2300 movs r3, #0
|
|
800d358: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
return xReturn;
|
|
800d35a: 697b ldr r3, [r7, #20]
|
|
}
|
|
800d35c: 4618 mov r0, r3
|
|
800d35e: 3728 adds r7, #40 @ 0x28
|
|
800d360: 46bd mov sp, r7
|
|
800d362: bd80 pop {r7, pc}
|
|
|
|
0800d364 <xTaskCreate>:
|
|
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
|
|
const configSTACK_DEPTH_TYPE usStackDepth,
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
TaskHandle_t * const pxCreatedTask )
|
|
{
|
|
800d364: b580 push {r7, lr}
|
|
800d366: b08c sub sp, #48 @ 0x30
|
|
800d368: af04 add r7, sp, #16
|
|
800d36a: 60f8 str r0, [r7, #12]
|
|
800d36c: 60b9 str r1, [r7, #8]
|
|
800d36e: 603b str r3, [r7, #0]
|
|
800d370: 4613 mov r3, r2
|
|
800d372: 80fb strh r3, [r7, #6]
|
|
#else /* portSTACK_GROWTH */
|
|
{
|
|
StackType_t *pxStack;
|
|
|
|
/* Allocate space for the stack used by the task being created. */
|
|
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
|
|
800d374: 88fb ldrh r3, [r7, #6]
|
|
800d376: 009b lsls r3, r3, #2
|
|
800d378: 4618 mov r0, r3
|
|
800d37a: f001 fe17 bl 800efac <pvPortMalloc>
|
|
800d37e: 6178 str r0, [r7, #20]
|
|
|
|
if( pxStack != NULL )
|
|
800d380: 697b ldr r3, [r7, #20]
|
|
800d382: 2b00 cmp r3, #0
|
|
800d384: d00e beq.n 800d3a4 <xTaskCreate+0x40>
|
|
{
|
|
/* Allocate space for the TCB. */
|
|
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
|
|
800d386: 205c movs r0, #92 @ 0x5c
|
|
800d388: f001 fe10 bl 800efac <pvPortMalloc>
|
|
800d38c: 61f8 str r0, [r7, #28]
|
|
|
|
if( pxNewTCB != NULL )
|
|
800d38e: 69fb ldr r3, [r7, #28]
|
|
800d390: 2b00 cmp r3, #0
|
|
800d392: d003 beq.n 800d39c <xTaskCreate+0x38>
|
|
{
|
|
/* Store the stack location in the TCB. */
|
|
pxNewTCB->pxStack = pxStack;
|
|
800d394: 69fb ldr r3, [r7, #28]
|
|
800d396: 697a ldr r2, [r7, #20]
|
|
800d398: 631a str r2, [r3, #48] @ 0x30
|
|
800d39a: e005 b.n 800d3a8 <xTaskCreate+0x44>
|
|
}
|
|
else
|
|
{
|
|
/* The stack cannot be used as the TCB was not created. Free
|
|
it again. */
|
|
vPortFree( pxStack );
|
|
800d39c: 6978 ldr r0, [r7, #20]
|
|
800d39e: f001 fed3 bl 800f148 <vPortFree>
|
|
800d3a2: e001 b.n 800d3a8 <xTaskCreate+0x44>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxNewTCB = NULL;
|
|
800d3a4: 2300 movs r3, #0
|
|
800d3a6: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
|
|
if( pxNewTCB != NULL )
|
|
800d3a8: 69fb ldr r3, [r7, #28]
|
|
800d3aa: 2b00 cmp r3, #0
|
|
800d3ac: d017 beq.n 800d3de <xTaskCreate+0x7a>
|
|
{
|
|
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* Tasks can be created statically or dynamically, so note this
|
|
task was created dynamically in case it is later deleted. */
|
|
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
|
|
800d3ae: 69fb ldr r3, [r7, #28]
|
|
800d3b0: 2200 movs r2, #0
|
|
800d3b2: f883 2059 strb.w r2, [r3, #89] @ 0x59
|
|
}
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
|
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
|
|
800d3b6: 88fa ldrh r2, [r7, #6]
|
|
800d3b8: 2300 movs r3, #0
|
|
800d3ba: 9303 str r3, [sp, #12]
|
|
800d3bc: 69fb ldr r3, [r7, #28]
|
|
800d3be: 9302 str r3, [sp, #8]
|
|
800d3c0: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800d3c2: 9301 str r3, [sp, #4]
|
|
800d3c4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800d3c6: 9300 str r3, [sp, #0]
|
|
800d3c8: 683b ldr r3, [r7, #0]
|
|
800d3ca: 68b9 ldr r1, [r7, #8]
|
|
800d3cc: 68f8 ldr r0, [r7, #12]
|
|
800d3ce: f000 f80e bl 800d3ee <prvInitialiseNewTask>
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
|
800d3d2: 69f8 ldr r0, [r7, #28]
|
|
800d3d4: f000 f89c bl 800d510 <prvAddNewTaskToReadyList>
|
|
xReturn = pdPASS;
|
|
800d3d8: 2301 movs r3, #1
|
|
800d3da: 61bb str r3, [r7, #24]
|
|
800d3dc: e002 b.n 800d3e4 <xTaskCreate+0x80>
|
|
}
|
|
else
|
|
{
|
|
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
|
|
800d3de: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800d3e2: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return xReturn;
|
|
800d3e4: 69bb ldr r3, [r7, #24]
|
|
}
|
|
800d3e6: 4618 mov r0, r3
|
|
800d3e8: 3720 adds r7, #32
|
|
800d3ea: 46bd mov sp, r7
|
|
800d3ec: bd80 pop {r7, pc}
|
|
|
|
0800d3ee <prvInitialiseNewTask>:
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
TaskHandle_t * const pxCreatedTask,
|
|
TCB_t *pxNewTCB,
|
|
const MemoryRegion_t * const xRegions )
|
|
{
|
|
800d3ee: b580 push {r7, lr}
|
|
800d3f0: b088 sub sp, #32
|
|
800d3f2: af00 add r7, sp, #0
|
|
800d3f4: 60f8 str r0, [r7, #12]
|
|
800d3f6: 60b9 str r1, [r7, #8]
|
|
800d3f8: 607a str r2, [r7, #4]
|
|
800d3fa: 603b str r3, [r7, #0]
|
|
|
|
/* Avoid dependency on memset() if it is not required. */
|
|
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
|
|
{
|
|
/* Fill the stack with a known value to assist debugging. */
|
|
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
|
|
800d3fc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d3fe: 6b18 ldr r0, [r3, #48] @ 0x30
|
|
800d400: 687b ldr r3, [r7, #4]
|
|
800d402: 009b lsls r3, r3, #2
|
|
800d404: 461a mov r2, r3
|
|
800d406: 21a5 movs r1, #165 @ 0xa5
|
|
800d408: f003 f85e bl 80104c8 <memset>
|
|
grows from high memory to low (as per the 80x86) or vice versa.
|
|
portSTACK_GROWTH is used to make the result positive or negative as required
|
|
by the port. */
|
|
#if( portSTACK_GROWTH < 0 )
|
|
{
|
|
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
|
|
800d40c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d40e: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
800d410: 687b ldr r3, [r7, #4]
|
|
800d412: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000
|
|
800d416: 3b01 subs r3, #1
|
|
800d418: 009b lsls r3, r3, #2
|
|
800d41a: 4413 add r3, r2
|
|
800d41c: 61bb str r3, [r7, #24]
|
|
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
|
|
800d41e: 69bb ldr r3, [r7, #24]
|
|
800d420: f023 0307 bic.w r3, r3, #7
|
|
800d424: 61bb str r3, [r7, #24]
|
|
|
|
/* Check the alignment of the calculated top of stack is correct. */
|
|
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
|
|
800d426: 69bb ldr r3, [r7, #24]
|
|
800d428: f003 0307 and.w r3, r3, #7
|
|
800d42c: 2b00 cmp r3, #0
|
|
800d42e: d00b beq.n 800d448 <prvInitialiseNewTask+0x5a>
|
|
__asm volatile
|
|
800d430: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d434: f383 8811 msr BASEPRI, r3
|
|
800d438: f3bf 8f6f isb sy
|
|
800d43c: f3bf 8f4f dsb sy
|
|
800d440: 617b str r3, [r7, #20]
|
|
}
|
|
800d442: bf00 nop
|
|
800d444: bf00 nop
|
|
800d446: e7fd b.n 800d444 <prvInitialiseNewTask+0x56>
|
|
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
|
|
/* Store the task name in the TCB. */
|
|
if( pcName != NULL )
|
|
800d448: 68bb ldr r3, [r7, #8]
|
|
800d44a: 2b00 cmp r3, #0
|
|
800d44c: d01f beq.n 800d48e <prvInitialiseNewTask+0xa0>
|
|
{
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
|
800d44e: 2300 movs r3, #0
|
|
800d450: 61fb str r3, [r7, #28]
|
|
800d452: e012 b.n 800d47a <prvInitialiseNewTask+0x8c>
|
|
{
|
|
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
|
|
800d454: 68ba ldr r2, [r7, #8]
|
|
800d456: 69fb ldr r3, [r7, #28]
|
|
800d458: 4413 add r3, r2
|
|
800d45a: 7819 ldrb r1, [r3, #0]
|
|
800d45c: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800d45e: 69fb ldr r3, [r7, #28]
|
|
800d460: 4413 add r3, r2
|
|
800d462: 3334 adds r3, #52 @ 0x34
|
|
800d464: 460a mov r2, r1
|
|
800d466: 701a strb r2, [r3, #0]
|
|
|
|
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
|
|
configMAX_TASK_NAME_LEN characters just in case the memory after the
|
|
string is not accessible (extremely unlikely). */
|
|
if( pcName[ x ] == ( char ) 0x00 )
|
|
800d468: 68ba ldr r2, [r7, #8]
|
|
800d46a: 69fb ldr r3, [r7, #28]
|
|
800d46c: 4413 add r3, r2
|
|
800d46e: 781b ldrb r3, [r3, #0]
|
|
800d470: 2b00 cmp r3, #0
|
|
800d472: d006 beq.n 800d482 <prvInitialiseNewTask+0x94>
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
|
800d474: 69fb ldr r3, [r7, #28]
|
|
800d476: 3301 adds r3, #1
|
|
800d478: 61fb str r3, [r7, #28]
|
|
800d47a: 69fb ldr r3, [r7, #28]
|
|
800d47c: 2b0f cmp r3, #15
|
|
800d47e: d9e9 bls.n 800d454 <prvInitialiseNewTask+0x66>
|
|
800d480: e000 b.n 800d484 <prvInitialiseNewTask+0x96>
|
|
{
|
|
break;
|
|
800d482: bf00 nop
|
|
}
|
|
}
|
|
|
|
/* Ensure the name string is terminated in the case that the string length
|
|
was greater or equal to configMAX_TASK_NAME_LEN. */
|
|
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
|
|
800d484: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d486: 2200 movs r2, #0
|
|
800d488: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
800d48c: e003 b.n 800d496 <prvInitialiseNewTask+0xa8>
|
|
}
|
|
else
|
|
{
|
|
/* The task has not been given a name, so just ensure there is a NULL
|
|
terminator when it is read out. */
|
|
pxNewTCB->pcTaskName[ 0 ] = 0x00;
|
|
800d48e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d490: 2200 movs r2, #0
|
|
800d492: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
/* This is used as an array index so must ensure it's not too large. First
|
|
remove the privilege bit if one is present. */
|
|
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
|
|
800d496: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800d498: 2b37 cmp r3, #55 @ 0x37
|
|
800d49a: d901 bls.n 800d4a0 <prvInitialiseNewTask+0xb2>
|
|
{
|
|
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
|
|
800d49c: 2337 movs r3, #55 @ 0x37
|
|
800d49e: 62bb str r3, [r7, #40] @ 0x28
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxNewTCB->uxPriority = uxPriority;
|
|
800d4a0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4a2: 6aba ldr r2, [r7, #40] @ 0x28
|
|
800d4a4: 62da str r2, [r3, #44] @ 0x2c
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
pxNewTCB->uxBasePriority = uxPriority;
|
|
800d4a6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4a8: 6aba ldr r2, [r7, #40] @ 0x28
|
|
800d4aa: 64da str r2, [r3, #76] @ 0x4c
|
|
pxNewTCB->uxMutexesHeld = 0;
|
|
800d4ac: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4ae: 2200 movs r2, #0
|
|
800d4b0: 651a str r2, [r3, #80] @ 0x50
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
|
|
800d4b2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4b4: 3304 adds r3, #4
|
|
800d4b6: 4618 mov r0, r3
|
|
800d4b8: f7fe ff72 bl 800c3a0 <vListInitialiseItem>
|
|
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
|
|
800d4bc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4be: 3318 adds r3, #24
|
|
800d4c0: 4618 mov r0, r3
|
|
800d4c2: f7fe ff6d bl 800c3a0 <vListInitialiseItem>
|
|
|
|
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
|
|
back to the containing TCB from a generic item in a list. */
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
|
|
800d4c6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4c8: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800d4ca: 611a str r2, [r3, #16]
|
|
|
|
/* Event lists are always in priority order. */
|
|
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800d4cc: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800d4ce: f1c3 0238 rsb r2, r3, #56 @ 0x38
|
|
800d4d2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4d4: 619a str r2, [r3, #24]
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
|
|
800d4d6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4d8: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800d4da: 625a str r2, [r3, #36] @ 0x24
|
|
}
|
|
#endif
|
|
|
|
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
|
|
{
|
|
pxNewTCB->ulNotifiedValue = 0;
|
|
800d4dc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4de: 2200 movs r2, #0
|
|
800d4e0: 655a str r2, [r3, #84] @ 0x54
|
|
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
|
|
800d4e2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4e4: 2200 movs r2, #0
|
|
800d4e6: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
}
|
|
#else /* portHAS_STACK_OVERFLOW_CHECKING */
|
|
{
|
|
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
|
|
800d4ea: 683a ldr r2, [r7, #0]
|
|
800d4ec: 68f9 ldr r1, [r7, #12]
|
|
800d4ee: 69b8 ldr r0, [r7, #24]
|
|
800d4f0: f001 fb0a bl 800eb08 <pxPortInitialiseStack>
|
|
800d4f4: 4602 mov r2, r0
|
|
800d4f6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d4f8: 601a str r2, [r3, #0]
|
|
}
|
|
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
|
|
}
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
|
|
|
if( pxCreatedTask != NULL )
|
|
800d4fa: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800d4fc: 2b00 cmp r3, #0
|
|
800d4fe: d002 beq.n 800d506 <prvInitialiseNewTask+0x118>
|
|
{
|
|
/* Pass the handle out in an anonymous way. The handle can be used to
|
|
change the created task's priority, delete the created task, etc.*/
|
|
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
|
|
800d500: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800d502: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800d504: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800d506: bf00 nop
|
|
800d508: 3720 adds r7, #32
|
|
800d50a: 46bd mov sp, r7
|
|
800d50c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800d510 <prvAddNewTaskToReadyList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
|
|
{
|
|
800d510: b580 push {r7, lr}
|
|
800d512: b082 sub sp, #8
|
|
800d514: af00 add r7, sp, #0
|
|
800d516: 6078 str r0, [r7, #4]
|
|
/* Ensure interrupts don't access the task lists while the lists are being
|
|
updated. */
|
|
taskENTER_CRITICAL();
|
|
800d518: f001 fc26 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
uxCurrentNumberOfTasks++;
|
|
800d51c: 4b2d ldr r3, [pc, #180] @ (800d5d4 <prvAddNewTaskToReadyList+0xc4>)
|
|
800d51e: 681b ldr r3, [r3, #0]
|
|
800d520: 3301 adds r3, #1
|
|
800d522: 4a2c ldr r2, [pc, #176] @ (800d5d4 <prvAddNewTaskToReadyList+0xc4>)
|
|
800d524: 6013 str r3, [r2, #0]
|
|
if( pxCurrentTCB == NULL )
|
|
800d526: 4b2c ldr r3, [pc, #176] @ (800d5d8 <prvAddNewTaskToReadyList+0xc8>)
|
|
800d528: 681b ldr r3, [r3, #0]
|
|
800d52a: 2b00 cmp r3, #0
|
|
800d52c: d109 bne.n 800d542 <prvAddNewTaskToReadyList+0x32>
|
|
{
|
|
/* There are no other tasks, or all the other tasks are in
|
|
the suspended state - make this the current task. */
|
|
pxCurrentTCB = pxNewTCB;
|
|
800d52e: 4a2a ldr r2, [pc, #168] @ (800d5d8 <prvAddNewTaskToReadyList+0xc8>)
|
|
800d530: 687b ldr r3, [r7, #4]
|
|
800d532: 6013 str r3, [r2, #0]
|
|
|
|
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
|
|
800d534: 4b27 ldr r3, [pc, #156] @ (800d5d4 <prvAddNewTaskToReadyList+0xc4>)
|
|
800d536: 681b ldr r3, [r3, #0]
|
|
800d538: 2b01 cmp r3, #1
|
|
800d53a: d110 bne.n 800d55e <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
/* This is the first task to be created so do the preliminary
|
|
initialisation required. We will not recover if this call
|
|
fails, but we will report the failure. */
|
|
prvInitialiseTaskLists();
|
|
800d53c: f000 fbe8 bl 800dd10 <prvInitialiseTaskLists>
|
|
800d540: e00d b.n 800d55e <prvAddNewTaskToReadyList+0x4e>
|
|
else
|
|
{
|
|
/* If the scheduler is not already running, make this task the
|
|
current task if it is the highest priority task to be created
|
|
so far. */
|
|
if( xSchedulerRunning == pdFALSE )
|
|
800d542: 4b26 ldr r3, [pc, #152] @ (800d5dc <prvAddNewTaskToReadyList+0xcc>)
|
|
800d544: 681b ldr r3, [r3, #0]
|
|
800d546: 2b00 cmp r3, #0
|
|
800d548: d109 bne.n 800d55e <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
|
|
800d54a: 4b23 ldr r3, [pc, #140] @ (800d5d8 <prvAddNewTaskToReadyList+0xc8>)
|
|
800d54c: 681b ldr r3, [r3, #0]
|
|
800d54e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d550: 687b ldr r3, [r7, #4]
|
|
800d552: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800d554: 429a cmp r2, r3
|
|
800d556: d802 bhi.n 800d55e <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
pxCurrentTCB = pxNewTCB;
|
|
800d558: 4a1f ldr r2, [pc, #124] @ (800d5d8 <prvAddNewTaskToReadyList+0xc8>)
|
|
800d55a: 687b ldr r3, [r7, #4]
|
|
800d55c: 6013 str r3, [r2, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
uxTaskNumber++;
|
|
800d55e: 4b20 ldr r3, [pc, #128] @ (800d5e0 <prvAddNewTaskToReadyList+0xd0>)
|
|
800d560: 681b ldr r3, [r3, #0]
|
|
800d562: 3301 adds r3, #1
|
|
800d564: 4a1e ldr r2, [pc, #120] @ (800d5e0 <prvAddNewTaskToReadyList+0xd0>)
|
|
800d566: 6013 str r3, [r2, #0]
|
|
|
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
|
{
|
|
/* Add a counter into the TCB for tracing only. */
|
|
pxNewTCB->uxTCBNumber = uxTaskNumber;
|
|
800d568: 4b1d ldr r3, [pc, #116] @ (800d5e0 <prvAddNewTaskToReadyList+0xd0>)
|
|
800d56a: 681a ldr r2, [r3, #0]
|
|
800d56c: 687b ldr r3, [r7, #4]
|
|
800d56e: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
#endif /* configUSE_TRACE_FACILITY */
|
|
traceTASK_CREATE( pxNewTCB );
|
|
|
|
prvAddTaskToReadyList( pxNewTCB );
|
|
800d570: 687b ldr r3, [r7, #4]
|
|
800d572: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d574: 4b1b ldr r3, [pc, #108] @ (800d5e4 <prvAddNewTaskToReadyList+0xd4>)
|
|
800d576: 681b ldr r3, [r3, #0]
|
|
800d578: 429a cmp r2, r3
|
|
800d57a: d903 bls.n 800d584 <prvAddNewTaskToReadyList+0x74>
|
|
800d57c: 687b ldr r3, [r7, #4]
|
|
800d57e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800d580: 4a18 ldr r2, [pc, #96] @ (800d5e4 <prvAddNewTaskToReadyList+0xd4>)
|
|
800d582: 6013 str r3, [r2, #0]
|
|
800d584: 687b ldr r3, [r7, #4]
|
|
800d586: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d588: 4613 mov r3, r2
|
|
800d58a: 009b lsls r3, r3, #2
|
|
800d58c: 4413 add r3, r2
|
|
800d58e: 009b lsls r3, r3, #2
|
|
800d590: 4a15 ldr r2, [pc, #84] @ (800d5e8 <prvAddNewTaskToReadyList+0xd8>)
|
|
800d592: 441a add r2, r3
|
|
800d594: 687b ldr r3, [r7, #4]
|
|
800d596: 3304 adds r3, #4
|
|
800d598: 4619 mov r1, r3
|
|
800d59a: 4610 mov r0, r2
|
|
800d59c: f7fe ff0d bl 800c3ba <vListInsertEnd>
|
|
|
|
portSETUP_TCB( pxNewTCB );
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800d5a0: f001 fc14 bl 800edcc <vPortExitCritical>
|
|
|
|
if( xSchedulerRunning != pdFALSE )
|
|
800d5a4: 4b0d ldr r3, [pc, #52] @ (800d5dc <prvAddNewTaskToReadyList+0xcc>)
|
|
800d5a6: 681b ldr r3, [r3, #0]
|
|
800d5a8: 2b00 cmp r3, #0
|
|
800d5aa: d00e beq.n 800d5ca <prvAddNewTaskToReadyList+0xba>
|
|
{
|
|
/* If the created task is of a higher priority than the current task
|
|
then it should run now. */
|
|
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
|
|
800d5ac: 4b0a ldr r3, [pc, #40] @ (800d5d8 <prvAddNewTaskToReadyList+0xc8>)
|
|
800d5ae: 681b ldr r3, [r3, #0]
|
|
800d5b0: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d5b2: 687b ldr r3, [r7, #4]
|
|
800d5b4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800d5b6: 429a cmp r2, r3
|
|
800d5b8: d207 bcs.n 800d5ca <prvAddNewTaskToReadyList+0xba>
|
|
{
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
800d5ba: 4b0c ldr r3, [pc, #48] @ (800d5ec <prvAddNewTaskToReadyList+0xdc>)
|
|
800d5bc: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800d5c0: 601a str r2, [r3, #0]
|
|
800d5c2: f3bf 8f4f dsb sy
|
|
800d5c6: f3bf 8f6f isb sy
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800d5ca: bf00 nop
|
|
800d5cc: 3708 adds r7, #8
|
|
800d5ce: 46bd mov sp, r7
|
|
800d5d0: bd80 pop {r7, pc}
|
|
800d5d2: bf00 nop
|
|
800d5d4: 20002854 .word 0x20002854
|
|
800d5d8: 20002380 .word 0x20002380
|
|
800d5dc: 20002860 .word 0x20002860
|
|
800d5e0: 20002870 .word 0x20002870
|
|
800d5e4: 2000285c .word 0x2000285c
|
|
800d5e8: 20002384 .word 0x20002384
|
|
800d5ec: e000ed04 .word 0xe000ed04
|
|
|
|
0800d5f0 <vTaskStartScheduler>:
|
|
|
|
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskStartScheduler( void )
|
|
{
|
|
800d5f0: b580 push {r7, lr}
|
|
800d5f2: b08a sub sp, #40 @ 0x28
|
|
800d5f4: af04 add r7, sp, #16
|
|
BaseType_t xReturn;
|
|
|
|
/* Add the idle task at the lowest priority. */
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
|
|
800d5f6: 2300 movs r3, #0
|
|
800d5f8: 60bb str r3, [r7, #8]
|
|
StackType_t *pxIdleTaskStackBuffer = NULL;
|
|
800d5fa: 2300 movs r3, #0
|
|
800d5fc: 607b str r3, [r7, #4]
|
|
uint32_t ulIdleTaskStackSize;
|
|
|
|
/* The Idle task is created using user provided RAM - obtain the
|
|
address of the RAM then create the idle task. */
|
|
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
|
|
800d5fe: 463a mov r2, r7
|
|
800d600: 1d39 adds r1, r7, #4
|
|
800d602: f107 0308 add.w r3, r7, #8
|
|
800d606: 4618 mov r0, r3
|
|
800d608: f7fe fe76 bl 800c2f8 <vApplicationGetIdleTaskMemory>
|
|
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
|
|
800d60c: 6839 ldr r1, [r7, #0]
|
|
800d60e: 687b ldr r3, [r7, #4]
|
|
800d610: 68ba ldr r2, [r7, #8]
|
|
800d612: 9202 str r2, [sp, #8]
|
|
800d614: 9301 str r3, [sp, #4]
|
|
800d616: 2300 movs r3, #0
|
|
800d618: 9300 str r3, [sp, #0]
|
|
800d61a: 2300 movs r3, #0
|
|
800d61c: 460a mov r2, r1
|
|
800d61e: 4922 ldr r1, [pc, #136] @ (800d6a8 <vTaskStartScheduler+0xb8>)
|
|
800d620: 4822 ldr r0, [pc, #136] @ (800d6ac <vTaskStartScheduler+0xbc>)
|
|
800d622: f7ff fe3f bl 800d2a4 <xTaskCreateStatic>
|
|
800d626: 4603 mov r3, r0
|
|
800d628: 4a21 ldr r2, [pc, #132] @ (800d6b0 <vTaskStartScheduler+0xc0>)
|
|
800d62a: 6013 str r3, [r2, #0]
|
|
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
|
|
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
|
|
pxIdleTaskStackBuffer,
|
|
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
|
|
|
|
if( xIdleTaskHandle != NULL )
|
|
800d62c: 4b20 ldr r3, [pc, #128] @ (800d6b0 <vTaskStartScheduler+0xc0>)
|
|
800d62e: 681b ldr r3, [r3, #0]
|
|
800d630: 2b00 cmp r3, #0
|
|
800d632: d002 beq.n 800d63a <vTaskStartScheduler+0x4a>
|
|
{
|
|
xReturn = pdPASS;
|
|
800d634: 2301 movs r3, #1
|
|
800d636: 617b str r3, [r7, #20]
|
|
800d638: e001 b.n 800d63e <vTaskStartScheduler+0x4e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFAIL;
|
|
800d63a: 2300 movs r3, #0
|
|
800d63c: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
|
|
#if ( configUSE_TIMERS == 1 )
|
|
{
|
|
if( xReturn == pdPASS )
|
|
800d63e: 697b ldr r3, [r7, #20]
|
|
800d640: 2b01 cmp r3, #1
|
|
800d642: d102 bne.n 800d64a <vTaskStartScheduler+0x5a>
|
|
{
|
|
xReturn = xTimerCreateTimerTask();
|
|
800d644: f000 ff06 bl 800e454 <xTimerCreateTimerTask>
|
|
800d648: 6178 str r0, [r7, #20]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_TIMERS */
|
|
|
|
if( xReturn == pdPASS )
|
|
800d64a: 697b ldr r3, [r7, #20]
|
|
800d64c: 2b01 cmp r3, #1
|
|
800d64e: d116 bne.n 800d67e <vTaskStartScheduler+0x8e>
|
|
__asm volatile
|
|
800d650: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d654: f383 8811 msr BASEPRI, r3
|
|
800d658: f3bf 8f6f isb sy
|
|
800d65c: f3bf 8f4f dsb sy
|
|
800d660: 613b str r3, [r7, #16]
|
|
}
|
|
800d662: bf00 nop
|
|
for additional information. */
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
|
}
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
|
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
800d664: 4b13 ldr r3, [pc, #76] @ (800d6b4 <vTaskStartScheduler+0xc4>)
|
|
800d666: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800d66a: 601a str r2, [r3, #0]
|
|
xSchedulerRunning = pdTRUE;
|
|
800d66c: 4b12 ldr r3, [pc, #72] @ (800d6b8 <vTaskStartScheduler+0xc8>)
|
|
800d66e: 2201 movs r2, #1
|
|
800d670: 601a str r2, [r3, #0]
|
|
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
|
|
800d672: 4b12 ldr r3, [pc, #72] @ (800d6bc <vTaskStartScheduler+0xcc>)
|
|
800d674: 2200 movs r2, #0
|
|
800d676: 601a str r2, [r3, #0]
|
|
|
|
traceTASK_SWITCHED_IN();
|
|
|
|
/* Setting up the timer tick is hardware specific and thus in the
|
|
portable interface. */
|
|
if( xPortStartScheduler() != pdFALSE )
|
|
800d678: f001 fad2 bl 800ec20 <xPortStartScheduler>
|
|
}
|
|
|
|
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
|
|
meaning xIdleTaskHandle is not used anywhere else. */
|
|
( void ) xIdleTaskHandle;
|
|
}
|
|
800d67c: e00f b.n 800d69e <vTaskStartScheduler+0xae>
|
|
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
|
|
800d67e: 697b ldr r3, [r7, #20]
|
|
800d680: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800d684: d10b bne.n 800d69e <vTaskStartScheduler+0xae>
|
|
__asm volatile
|
|
800d686: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d68a: f383 8811 msr BASEPRI, r3
|
|
800d68e: f3bf 8f6f isb sy
|
|
800d692: f3bf 8f4f dsb sy
|
|
800d696: 60fb str r3, [r7, #12]
|
|
}
|
|
800d698: bf00 nop
|
|
800d69a: bf00 nop
|
|
800d69c: e7fd b.n 800d69a <vTaskStartScheduler+0xaa>
|
|
}
|
|
800d69e: bf00 nop
|
|
800d6a0: 3718 adds r7, #24
|
|
800d6a2: 46bd mov sp, r7
|
|
800d6a4: bd80 pop {r7, pc}
|
|
800d6a6: bf00 nop
|
|
800d6a8: 0801472c .word 0x0801472c
|
|
800d6ac: 0800dce1 .word 0x0800dce1
|
|
800d6b0: 20002878 .word 0x20002878
|
|
800d6b4: 20002874 .word 0x20002874
|
|
800d6b8: 20002860 .word 0x20002860
|
|
800d6bc: 20002858 .word 0x20002858
|
|
|
|
0800d6c0 <vTaskSuspendAll>:
|
|
vPortEndScheduler();
|
|
}
|
|
/*----------------------------------------------------------*/
|
|
|
|
void vTaskSuspendAll( void )
|
|
{
|
|
800d6c0: b480 push {r7}
|
|
800d6c2: af00 add r7, sp, #0
|
|
do not otherwise exhibit real time behaviour. */
|
|
portSOFTWARE_BARRIER();
|
|
|
|
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
|
|
is used to allow calls to vTaskSuspendAll() to nest. */
|
|
++uxSchedulerSuspended;
|
|
800d6c4: 4b04 ldr r3, [pc, #16] @ (800d6d8 <vTaskSuspendAll+0x18>)
|
|
800d6c6: 681b ldr r3, [r3, #0]
|
|
800d6c8: 3301 adds r3, #1
|
|
800d6ca: 4a03 ldr r2, [pc, #12] @ (800d6d8 <vTaskSuspendAll+0x18>)
|
|
800d6cc: 6013 str r3, [r2, #0]
|
|
|
|
/* Enforces ordering for ports and optimised compilers that may otherwise place
|
|
the above increment elsewhere. */
|
|
portMEMORY_BARRIER();
|
|
}
|
|
800d6ce: bf00 nop
|
|
800d6d0: 46bd mov sp, r7
|
|
800d6d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800d6d6: 4770 bx lr
|
|
800d6d8: 2000287c .word 0x2000287c
|
|
|
|
0800d6dc <xTaskResumeAll>:
|
|
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskResumeAll( void )
|
|
{
|
|
800d6dc: b580 push {r7, lr}
|
|
800d6de: b084 sub sp, #16
|
|
800d6e0: af00 add r7, sp, #0
|
|
TCB_t *pxTCB = NULL;
|
|
800d6e2: 2300 movs r3, #0
|
|
800d6e4: 60fb str r3, [r7, #12]
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
|
800d6e6: 2300 movs r3, #0
|
|
800d6e8: 60bb str r3, [r7, #8]
|
|
|
|
/* If uxSchedulerSuspended is zero then this function does not match a
|
|
previous call to vTaskSuspendAll(). */
|
|
configASSERT( uxSchedulerSuspended );
|
|
800d6ea: 4b42 ldr r3, [pc, #264] @ (800d7f4 <xTaskResumeAll+0x118>)
|
|
800d6ec: 681b ldr r3, [r3, #0]
|
|
800d6ee: 2b00 cmp r3, #0
|
|
800d6f0: d10b bne.n 800d70a <xTaskResumeAll+0x2e>
|
|
__asm volatile
|
|
800d6f2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d6f6: f383 8811 msr BASEPRI, r3
|
|
800d6fa: f3bf 8f6f isb sy
|
|
800d6fe: f3bf 8f4f dsb sy
|
|
800d702: 603b str r3, [r7, #0]
|
|
}
|
|
800d704: bf00 nop
|
|
800d706: bf00 nop
|
|
800d708: e7fd b.n 800d706 <xTaskResumeAll+0x2a>
|
|
/* It is possible that an ISR caused a task to be removed from an event
|
|
list while the scheduler was suspended. If this was the case then the
|
|
removed task will have been added to the xPendingReadyList. Once the
|
|
scheduler has been resumed it is safe to move all the pending ready
|
|
tasks from this list into their appropriate ready list. */
|
|
taskENTER_CRITICAL();
|
|
800d70a: f001 fb2d bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
--uxSchedulerSuspended;
|
|
800d70e: 4b39 ldr r3, [pc, #228] @ (800d7f4 <xTaskResumeAll+0x118>)
|
|
800d710: 681b ldr r3, [r3, #0]
|
|
800d712: 3b01 subs r3, #1
|
|
800d714: 4a37 ldr r2, [pc, #220] @ (800d7f4 <xTaskResumeAll+0x118>)
|
|
800d716: 6013 str r3, [r2, #0]
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800d718: 4b36 ldr r3, [pc, #216] @ (800d7f4 <xTaskResumeAll+0x118>)
|
|
800d71a: 681b ldr r3, [r3, #0]
|
|
800d71c: 2b00 cmp r3, #0
|
|
800d71e: d162 bne.n 800d7e6 <xTaskResumeAll+0x10a>
|
|
{
|
|
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
|
|
800d720: 4b35 ldr r3, [pc, #212] @ (800d7f8 <xTaskResumeAll+0x11c>)
|
|
800d722: 681b ldr r3, [r3, #0]
|
|
800d724: 2b00 cmp r3, #0
|
|
800d726: d05e beq.n 800d7e6 <xTaskResumeAll+0x10a>
|
|
{
|
|
/* Move any readied tasks from the pending list into the
|
|
appropriate ready list. */
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
800d728: e02f b.n 800d78a <xTaskResumeAll+0xae>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800d72a: 4b34 ldr r3, [pc, #208] @ (800d7fc <xTaskResumeAll+0x120>)
|
|
800d72c: 68db ldr r3, [r3, #12]
|
|
800d72e: 68db ldr r3, [r3, #12]
|
|
800d730: 60fb str r3, [r7, #12]
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
800d732: 68fb ldr r3, [r7, #12]
|
|
800d734: 3318 adds r3, #24
|
|
800d736: 4618 mov r0, r3
|
|
800d738: f7fe fe9c bl 800c474 <uxListRemove>
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800d73c: 68fb ldr r3, [r7, #12]
|
|
800d73e: 3304 adds r3, #4
|
|
800d740: 4618 mov r0, r3
|
|
800d742: f7fe fe97 bl 800c474 <uxListRemove>
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800d746: 68fb ldr r3, [r7, #12]
|
|
800d748: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d74a: 4b2d ldr r3, [pc, #180] @ (800d800 <xTaskResumeAll+0x124>)
|
|
800d74c: 681b ldr r3, [r3, #0]
|
|
800d74e: 429a cmp r2, r3
|
|
800d750: d903 bls.n 800d75a <xTaskResumeAll+0x7e>
|
|
800d752: 68fb ldr r3, [r7, #12]
|
|
800d754: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800d756: 4a2a ldr r2, [pc, #168] @ (800d800 <xTaskResumeAll+0x124>)
|
|
800d758: 6013 str r3, [r2, #0]
|
|
800d75a: 68fb ldr r3, [r7, #12]
|
|
800d75c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d75e: 4613 mov r3, r2
|
|
800d760: 009b lsls r3, r3, #2
|
|
800d762: 4413 add r3, r2
|
|
800d764: 009b lsls r3, r3, #2
|
|
800d766: 4a27 ldr r2, [pc, #156] @ (800d804 <xTaskResumeAll+0x128>)
|
|
800d768: 441a add r2, r3
|
|
800d76a: 68fb ldr r3, [r7, #12]
|
|
800d76c: 3304 adds r3, #4
|
|
800d76e: 4619 mov r1, r3
|
|
800d770: 4610 mov r0, r2
|
|
800d772: f7fe fe22 bl 800c3ba <vListInsertEnd>
|
|
|
|
/* If the moved task has a priority higher than the current
|
|
task then a yield must be performed. */
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
|
800d776: 68fb ldr r3, [r7, #12]
|
|
800d778: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d77a: 4b23 ldr r3, [pc, #140] @ (800d808 <xTaskResumeAll+0x12c>)
|
|
800d77c: 681b ldr r3, [r3, #0]
|
|
800d77e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800d780: 429a cmp r2, r3
|
|
800d782: d302 bcc.n 800d78a <xTaskResumeAll+0xae>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
800d784: 4b21 ldr r3, [pc, #132] @ (800d80c <xTaskResumeAll+0x130>)
|
|
800d786: 2201 movs r2, #1
|
|
800d788: 601a str r2, [r3, #0]
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
800d78a: 4b1c ldr r3, [pc, #112] @ (800d7fc <xTaskResumeAll+0x120>)
|
|
800d78c: 681b ldr r3, [r3, #0]
|
|
800d78e: 2b00 cmp r3, #0
|
|
800d790: d1cb bne.n 800d72a <xTaskResumeAll+0x4e>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( pxTCB != NULL )
|
|
800d792: 68fb ldr r3, [r7, #12]
|
|
800d794: 2b00 cmp r3, #0
|
|
800d796: d001 beq.n 800d79c <xTaskResumeAll+0xc0>
|
|
which may have prevented the next unblock time from being
|
|
re-calculated, in which case re-calculate it now. Mainly
|
|
important for low power tickless implementations, where
|
|
this can prevent an unnecessary exit from low power
|
|
state. */
|
|
prvResetNextTaskUnblockTime();
|
|
800d798: f000 fb58 bl 800de4c <prvResetNextTaskUnblockTime>
|
|
/* If any ticks occurred while the scheduler was suspended then
|
|
they should be processed now. This ensures the tick count does
|
|
not slip, and that any delayed tasks are resumed at the correct
|
|
time. */
|
|
{
|
|
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
|
|
800d79c: 4b1c ldr r3, [pc, #112] @ (800d810 <xTaskResumeAll+0x134>)
|
|
800d79e: 681b ldr r3, [r3, #0]
|
|
800d7a0: 607b str r3, [r7, #4]
|
|
|
|
if( xPendedCounts > ( TickType_t ) 0U )
|
|
800d7a2: 687b ldr r3, [r7, #4]
|
|
800d7a4: 2b00 cmp r3, #0
|
|
800d7a6: d010 beq.n 800d7ca <xTaskResumeAll+0xee>
|
|
{
|
|
do
|
|
{
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
800d7a8: f000 f846 bl 800d838 <xTaskIncrementTick>
|
|
800d7ac: 4603 mov r3, r0
|
|
800d7ae: 2b00 cmp r3, #0
|
|
800d7b0: d002 beq.n 800d7b8 <xTaskResumeAll+0xdc>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
800d7b2: 4b16 ldr r3, [pc, #88] @ (800d80c <xTaskResumeAll+0x130>)
|
|
800d7b4: 2201 movs r2, #1
|
|
800d7b6: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
--xPendedCounts;
|
|
800d7b8: 687b ldr r3, [r7, #4]
|
|
800d7ba: 3b01 subs r3, #1
|
|
800d7bc: 607b str r3, [r7, #4]
|
|
} while( xPendedCounts > ( TickType_t ) 0U );
|
|
800d7be: 687b ldr r3, [r7, #4]
|
|
800d7c0: 2b00 cmp r3, #0
|
|
800d7c2: d1f1 bne.n 800d7a8 <xTaskResumeAll+0xcc>
|
|
|
|
xPendedTicks = 0;
|
|
800d7c4: 4b12 ldr r3, [pc, #72] @ (800d810 <xTaskResumeAll+0x134>)
|
|
800d7c6: 2200 movs r2, #0
|
|
800d7c8: 601a str r2, [r3, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( xYieldPending != pdFALSE )
|
|
800d7ca: 4b10 ldr r3, [pc, #64] @ (800d80c <xTaskResumeAll+0x130>)
|
|
800d7cc: 681b ldr r3, [r3, #0]
|
|
800d7ce: 2b00 cmp r3, #0
|
|
800d7d0: d009 beq.n 800d7e6 <xTaskResumeAll+0x10a>
|
|
{
|
|
#if( configUSE_PREEMPTION != 0 )
|
|
{
|
|
xAlreadyYielded = pdTRUE;
|
|
800d7d2: 2301 movs r3, #1
|
|
800d7d4: 60bb str r3, [r7, #8]
|
|
}
|
|
#endif
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
800d7d6: 4b0f ldr r3, [pc, #60] @ (800d814 <xTaskResumeAll+0x138>)
|
|
800d7d8: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800d7dc: 601a str r2, [r3, #0]
|
|
800d7de: f3bf 8f4f dsb sy
|
|
800d7e2: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800d7e6: f001 faf1 bl 800edcc <vPortExitCritical>
|
|
|
|
return xAlreadyYielded;
|
|
800d7ea: 68bb ldr r3, [r7, #8]
|
|
}
|
|
800d7ec: 4618 mov r0, r3
|
|
800d7ee: 3710 adds r7, #16
|
|
800d7f0: 46bd mov sp, r7
|
|
800d7f2: bd80 pop {r7, pc}
|
|
800d7f4: 2000287c .word 0x2000287c
|
|
800d7f8: 20002854 .word 0x20002854
|
|
800d7fc: 20002814 .word 0x20002814
|
|
800d800: 2000285c .word 0x2000285c
|
|
800d804: 20002384 .word 0x20002384
|
|
800d808: 20002380 .word 0x20002380
|
|
800d80c: 20002868 .word 0x20002868
|
|
800d810: 20002864 .word 0x20002864
|
|
800d814: e000ed04 .word 0xe000ed04
|
|
|
|
0800d818 <xTaskGetTickCount>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
TickType_t xTaskGetTickCount( void )
|
|
{
|
|
800d818: b480 push {r7}
|
|
800d81a: b083 sub sp, #12
|
|
800d81c: af00 add r7, sp, #0
|
|
TickType_t xTicks;
|
|
|
|
/* Critical section required if running on a 16 bit processor. */
|
|
portTICK_TYPE_ENTER_CRITICAL();
|
|
{
|
|
xTicks = xTickCount;
|
|
800d81e: 4b05 ldr r3, [pc, #20] @ (800d834 <xTaskGetTickCount+0x1c>)
|
|
800d820: 681b ldr r3, [r3, #0]
|
|
800d822: 607b str r3, [r7, #4]
|
|
}
|
|
portTICK_TYPE_EXIT_CRITICAL();
|
|
|
|
return xTicks;
|
|
800d824: 687b ldr r3, [r7, #4]
|
|
}
|
|
800d826: 4618 mov r0, r3
|
|
800d828: 370c adds r7, #12
|
|
800d82a: 46bd mov sp, r7
|
|
800d82c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800d830: 4770 bx lr
|
|
800d832: bf00 nop
|
|
800d834: 20002858 .word 0x20002858
|
|
|
|
0800d838 <xTaskIncrementTick>:
|
|
|
|
#endif /* INCLUDE_xTaskAbortDelay */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskIncrementTick( void )
|
|
{
|
|
800d838: b580 push {r7, lr}
|
|
800d83a: b086 sub sp, #24
|
|
800d83c: af00 add r7, sp, #0
|
|
TCB_t * pxTCB;
|
|
TickType_t xItemValue;
|
|
BaseType_t xSwitchRequired = pdFALSE;
|
|
800d83e: 2300 movs r3, #0
|
|
800d840: 617b str r3, [r7, #20]
|
|
|
|
/* Called by the portable layer each time a tick interrupt occurs.
|
|
Increments the tick then checks to see if the new tick value will cause any
|
|
tasks to be unblocked. */
|
|
traceTASK_INCREMENT_TICK( xTickCount );
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800d842: 4b4f ldr r3, [pc, #316] @ (800d980 <xTaskIncrementTick+0x148>)
|
|
800d844: 681b ldr r3, [r3, #0]
|
|
800d846: 2b00 cmp r3, #0
|
|
800d848: f040 8090 bne.w 800d96c <xTaskIncrementTick+0x134>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this
|
|
block. */
|
|
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
|
|
800d84c: 4b4d ldr r3, [pc, #308] @ (800d984 <xTaskIncrementTick+0x14c>)
|
|
800d84e: 681b ldr r3, [r3, #0]
|
|
800d850: 3301 adds r3, #1
|
|
800d852: 613b str r3, [r7, #16]
|
|
|
|
/* Increment the RTOS tick, switching the delayed and overflowed
|
|
delayed lists if it wraps to 0. */
|
|
xTickCount = xConstTickCount;
|
|
800d854: 4a4b ldr r2, [pc, #300] @ (800d984 <xTaskIncrementTick+0x14c>)
|
|
800d856: 693b ldr r3, [r7, #16]
|
|
800d858: 6013 str r3, [r2, #0]
|
|
|
|
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
|
|
800d85a: 693b ldr r3, [r7, #16]
|
|
800d85c: 2b00 cmp r3, #0
|
|
800d85e: d121 bne.n 800d8a4 <xTaskIncrementTick+0x6c>
|
|
{
|
|
taskSWITCH_DELAYED_LISTS();
|
|
800d860: 4b49 ldr r3, [pc, #292] @ (800d988 <xTaskIncrementTick+0x150>)
|
|
800d862: 681b ldr r3, [r3, #0]
|
|
800d864: 681b ldr r3, [r3, #0]
|
|
800d866: 2b00 cmp r3, #0
|
|
800d868: d00b beq.n 800d882 <xTaskIncrementTick+0x4a>
|
|
__asm volatile
|
|
800d86a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d86e: f383 8811 msr BASEPRI, r3
|
|
800d872: f3bf 8f6f isb sy
|
|
800d876: f3bf 8f4f dsb sy
|
|
800d87a: 603b str r3, [r7, #0]
|
|
}
|
|
800d87c: bf00 nop
|
|
800d87e: bf00 nop
|
|
800d880: e7fd b.n 800d87e <xTaskIncrementTick+0x46>
|
|
800d882: 4b41 ldr r3, [pc, #260] @ (800d988 <xTaskIncrementTick+0x150>)
|
|
800d884: 681b ldr r3, [r3, #0]
|
|
800d886: 60fb str r3, [r7, #12]
|
|
800d888: 4b40 ldr r3, [pc, #256] @ (800d98c <xTaskIncrementTick+0x154>)
|
|
800d88a: 681b ldr r3, [r3, #0]
|
|
800d88c: 4a3e ldr r2, [pc, #248] @ (800d988 <xTaskIncrementTick+0x150>)
|
|
800d88e: 6013 str r3, [r2, #0]
|
|
800d890: 4a3e ldr r2, [pc, #248] @ (800d98c <xTaskIncrementTick+0x154>)
|
|
800d892: 68fb ldr r3, [r7, #12]
|
|
800d894: 6013 str r3, [r2, #0]
|
|
800d896: 4b3e ldr r3, [pc, #248] @ (800d990 <xTaskIncrementTick+0x158>)
|
|
800d898: 681b ldr r3, [r3, #0]
|
|
800d89a: 3301 adds r3, #1
|
|
800d89c: 4a3c ldr r2, [pc, #240] @ (800d990 <xTaskIncrementTick+0x158>)
|
|
800d89e: 6013 str r3, [r2, #0]
|
|
800d8a0: f000 fad4 bl 800de4c <prvResetNextTaskUnblockTime>
|
|
|
|
/* See if this tick has made a timeout expire. Tasks are stored in
|
|
the queue in the order of their wake time - meaning once one task
|
|
has been found whose block time has not expired there is no need to
|
|
look any further down the list. */
|
|
if( xConstTickCount >= xNextTaskUnblockTime )
|
|
800d8a4: 4b3b ldr r3, [pc, #236] @ (800d994 <xTaskIncrementTick+0x15c>)
|
|
800d8a6: 681b ldr r3, [r3, #0]
|
|
800d8a8: 693a ldr r2, [r7, #16]
|
|
800d8aa: 429a cmp r2, r3
|
|
800d8ac: d349 bcc.n 800d942 <xTaskIncrementTick+0x10a>
|
|
{
|
|
for( ;; )
|
|
{
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800d8ae: 4b36 ldr r3, [pc, #216] @ (800d988 <xTaskIncrementTick+0x150>)
|
|
800d8b0: 681b ldr r3, [r3, #0]
|
|
800d8b2: 681b ldr r3, [r3, #0]
|
|
800d8b4: 2b00 cmp r3, #0
|
|
800d8b6: d104 bne.n 800d8c2 <xTaskIncrementTick+0x8a>
|
|
/* The delayed list is empty. Set xNextTaskUnblockTime
|
|
to the maximum possible value so it is extremely
|
|
unlikely that the
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass
|
|
next time through. */
|
|
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800d8b8: 4b36 ldr r3, [pc, #216] @ (800d994 <xTaskIncrementTick+0x15c>)
|
|
800d8ba: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800d8be: 601a str r2, [r3, #0]
|
|
break;
|
|
800d8c0: e03f b.n 800d942 <xTaskIncrementTick+0x10a>
|
|
{
|
|
/* The delayed list is not empty, get the value of the
|
|
item at the head of the delayed list. This is the time
|
|
at which the task at the head of the delayed list must
|
|
be removed from the Blocked state. */
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800d8c2: 4b31 ldr r3, [pc, #196] @ (800d988 <xTaskIncrementTick+0x150>)
|
|
800d8c4: 681b ldr r3, [r3, #0]
|
|
800d8c6: 68db ldr r3, [r3, #12]
|
|
800d8c8: 68db ldr r3, [r3, #12]
|
|
800d8ca: 60bb str r3, [r7, #8]
|
|
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
|
|
800d8cc: 68bb ldr r3, [r7, #8]
|
|
800d8ce: 685b ldr r3, [r3, #4]
|
|
800d8d0: 607b str r3, [r7, #4]
|
|
|
|
if( xConstTickCount < xItemValue )
|
|
800d8d2: 693a ldr r2, [r7, #16]
|
|
800d8d4: 687b ldr r3, [r7, #4]
|
|
800d8d6: 429a cmp r2, r3
|
|
800d8d8: d203 bcs.n 800d8e2 <xTaskIncrementTick+0xaa>
|
|
/* It is not time to unblock this item yet, but the
|
|
item value is the time at which the task at the head
|
|
of the blocked list must be removed from the Blocked
|
|
state - so record the item value in
|
|
xNextTaskUnblockTime. */
|
|
xNextTaskUnblockTime = xItemValue;
|
|
800d8da: 4a2e ldr r2, [pc, #184] @ (800d994 <xTaskIncrementTick+0x15c>)
|
|
800d8dc: 687b ldr r3, [r7, #4]
|
|
800d8de: 6013 str r3, [r2, #0]
|
|
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
|
|
800d8e0: e02f b.n 800d942 <xTaskIncrementTick+0x10a>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* It is time to remove the item from the Blocked state. */
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800d8e2: 68bb ldr r3, [r7, #8]
|
|
800d8e4: 3304 adds r3, #4
|
|
800d8e6: 4618 mov r0, r3
|
|
800d8e8: f7fe fdc4 bl 800c474 <uxListRemove>
|
|
|
|
/* Is the task waiting on an event also? If so remove
|
|
it from the event list. */
|
|
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
|
|
800d8ec: 68bb ldr r3, [r7, #8]
|
|
800d8ee: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800d8f0: 2b00 cmp r3, #0
|
|
800d8f2: d004 beq.n 800d8fe <xTaskIncrementTick+0xc6>
|
|
{
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
800d8f4: 68bb ldr r3, [r7, #8]
|
|
800d8f6: 3318 adds r3, #24
|
|
800d8f8: 4618 mov r0, r3
|
|
800d8fa: f7fe fdbb bl 800c474 <uxListRemove>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Place the unblocked task into the appropriate ready
|
|
list. */
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800d8fe: 68bb ldr r3, [r7, #8]
|
|
800d900: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d902: 4b25 ldr r3, [pc, #148] @ (800d998 <xTaskIncrementTick+0x160>)
|
|
800d904: 681b ldr r3, [r3, #0]
|
|
800d906: 429a cmp r2, r3
|
|
800d908: d903 bls.n 800d912 <xTaskIncrementTick+0xda>
|
|
800d90a: 68bb ldr r3, [r7, #8]
|
|
800d90c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800d90e: 4a22 ldr r2, [pc, #136] @ (800d998 <xTaskIncrementTick+0x160>)
|
|
800d910: 6013 str r3, [r2, #0]
|
|
800d912: 68bb ldr r3, [r7, #8]
|
|
800d914: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d916: 4613 mov r3, r2
|
|
800d918: 009b lsls r3, r3, #2
|
|
800d91a: 4413 add r3, r2
|
|
800d91c: 009b lsls r3, r3, #2
|
|
800d91e: 4a1f ldr r2, [pc, #124] @ (800d99c <xTaskIncrementTick+0x164>)
|
|
800d920: 441a add r2, r3
|
|
800d922: 68bb ldr r3, [r7, #8]
|
|
800d924: 3304 adds r3, #4
|
|
800d926: 4619 mov r1, r3
|
|
800d928: 4610 mov r0, r2
|
|
800d92a: f7fe fd46 bl 800c3ba <vListInsertEnd>
|
|
{
|
|
/* Preemption is on, but a context switch should
|
|
only be performed if the unblocked task has a
|
|
priority that is equal to or higher than the
|
|
currently executing task. */
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
|
800d92e: 68bb ldr r3, [r7, #8]
|
|
800d930: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d932: 4b1b ldr r3, [pc, #108] @ (800d9a0 <xTaskIncrementTick+0x168>)
|
|
800d934: 681b ldr r3, [r3, #0]
|
|
800d936: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800d938: 429a cmp r2, r3
|
|
800d93a: d3b8 bcc.n 800d8ae <xTaskIncrementTick+0x76>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800d93c: 2301 movs r3, #1
|
|
800d93e: 617b str r3, [r7, #20]
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800d940: e7b5 b.n 800d8ae <xTaskIncrementTick+0x76>
|
|
/* Tasks of equal priority to the currently running task will share
|
|
processing time (time slice) if preemption is on, and the application
|
|
writer has not explicitly turned time slicing off. */
|
|
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
|
|
{
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
|
|
800d942: 4b17 ldr r3, [pc, #92] @ (800d9a0 <xTaskIncrementTick+0x168>)
|
|
800d944: 681b ldr r3, [r3, #0]
|
|
800d946: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800d948: 4914 ldr r1, [pc, #80] @ (800d99c <xTaskIncrementTick+0x164>)
|
|
800d94a: 4613 mov r3, r2
|
|
800d94c: 009b lsls r3, r3, #2
|
|
800d94e: 4413 add r3, r2
|
|
800d950: 009b lsls r3, r3, #2
|
|
800d952: 440b add r3, r1
|
|
800d954: 681b ldr r3, [r3, #0]
|
|
800d956: 2b01 cmp r3, #1
|
|
800d958: d901 bls.n 800d95e <xTaskIncrementTick+0x126>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800d95a: 2301 movs r3, #1
|
|
800d95c: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* configUSE_TICK_HOOK */
|
|
|
|
#if ( configUSE_PREEMPTION == 1 )
|
|
{
|
|
if( xYieldPending != pdFALSE )
|
|
800d95e: 4b11 ldr r3, [pc, #68] @ (800d9a4 <xTaskIncrementTick+0x16c>)
|
|
800d960: 681b ldr r3, [r3, #0]
|
|
800d962: 2b00 cmp r3, #0
|
|
800d964: d007 beq.n 800d976 <xTaskIncrementTick+0x13e>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800d966: 2301 movs r3, #1
|
|
800d968: 617b str r3, [r7, #20]
|
|
800d96a: e004 b.n 800d976 <xTaskIncrementTick+0x13e>
|
|
}
|
|
#endif /* configUSE_PREEMPTION */
|
|
}
|
|
else
|
|
{
|
|
++xPendedTicks;
|
|
800d96c: 4b0e ldr r3, [pc, #56] @ (800d9a8 <xTaskIncrementTick+0x170>)
|
|
800d96e: 681b ldr r3, [r3, #0]
|
|
800d970: 3301 adds r3, #1
|
|
800d972: 4a0d ldr r2, [pc, #52] @ (800d9a8 <xTaskIncrementTick+0x170>)
|
|
800d974: 6013 str r3, [r2, #0]
|
|
vApplicationTickHook();
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return xSwitchRequired;
|
|
800d976: 697b ldr r3, [r7, #20]
|
|
}
|
|
800d978: 4618 mov r0, r3
|
|
800d97a: 3718 adds r7, #24
|
|
800d97c: 46bd mov sp, r7
|
|
800d97e: bd80 pop {r7, pc}
|
|
800d980: 2000287c .word 0x2000287c
|
|
800d984: 20002858 .word 0x20002858
|
|
800d988: 2000280c .word 0x2000280c
|
|
800d98c: 20002810 .word 0x20002810
|
|
800d990: 2000286c .word 0x2000286c
|
|
800d994: 20002874 .word 0x20002874
|
|
800d998: 2000285c .word 0x2000285c
|
|
800d99c: 20002384 .word 0x20002384
|
|
800d9a0: 20002380 .word 0x20002380
|
|
800d9a4: 20002868 .word 0x20002868
|
|
800d9a8: 20002864 .word 0x20002864
|
|
|
|
0800d9ac <vTaskSwitchContext>:
|
|
|
|
#endif /* configUSE_APPLICATION_TASK_TAG */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskSwitchContext( void )
|
|
{
|
|
800d9ac: b480 push {r7}
|
|
800d9ae: b085 sub sp, #20
|
|
800d9b0: af00 add r7, sp, #0
|
|
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
|
|
800d9b2: 4b28 ldr r3, [pc, #160] @ (800da54 <vTaskSwitchContext+0xa8>)
|
|
800d9b4: 681b ldr r3, [r3, #0]
|
|
800d9b6: 2b00 cmp r3, #0
|
|
800d9b8: d003 beq.n 800d9c2 <vTaskSwitchContext+0x16>
|
|
{
|
|
/* The scheduler is currently suspended - do not allow a context
|
|
switch. */
|
|
xYieldPending = pdTRUE;
|
|
800d9ba: 4b27 ldr r3, [pc, #156] @ (800da58 <vTaskSwitchContext+0xac>)
|
|
800d9bc: 2201 movs r2, #1
|
|
800d9be: 601a str r2, [r3, #0]
|
|
for additional information. */
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
|
}
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
|
}
|
|
}
|
|
800d9c0: e042 b.n 800da48 <vTaskSwitchContext+0x9c>
|
|
xYieldPending = pdFALSE;
|
|
800d9c2: 4b25 ldr r3, [pc, #148] @ (800da58 <vTaskSwitchContext+0xac>)
|
|
800d9c4: 2200 movs r2, #0
|
|
800d9c6: 601a str r2, [r3, #0]
|
|
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800d9c8: 4b24 ldr r3, [pc, #144] @ (800da5c <vTaskSwitchContext+0xb0>)
|
|
800d9ca: 681b ldr r3, [r3, #0]
|
|
800d9cc: 60fb str r3, [r7, #12]
|
|
800d9ce: e011 b.n 800d9f4 <vTaskSwitchContext+0x48>
|
|
800d9d0: 68fb ldr r3, [r7, #12]
|
|
800d9d2: 2b00 cmp r3, #0
|
|
800d9d4: d10b bne.n 800d9ee <vTaskSwitchContext+0x42>
|
|
__asm volatile
|
|
800d9d6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800d9da: f383 8811 msr BASEPRI, r3
|
|
800d9de: f3bf 8f6f isb sy
|
|
800d9e2: f3bf 8f4f dsb sy
|
|
800d9e6: 607b str r3, [r7, #4]
|
|
}
|
|
800d9e8: bf00 nop
|
|
800d9ea: bf00 nop
|
|
800d9ec: e7fd b.n 800d9ea <vTaskSwitchContext+0x3e>
|
|
800d9ee: 68fb ldr r3, [r7, #12]
|
|
800d9f0: 3b01 subs r3, #1
|
|
800d9f2: 60fb str r3, [r7, #12]
|
|
800d9f4: 491a ldr r1, [pc, #104] @ (800da60 <vTaskSwitchContext+0xb4>)
|
|
800d9f6: 68fa ldr r2, [r7, #12]
|
|
800d9f8: 4613 mov r3, r2
|
|
800d9fa: 009b lsls r3, r3, #2
|
|
800d9fc: 4413 add r3, r2
|
|
800d9fe: 009b lsls r3, r3, #2
|
|
800da00: 440b add r3, r1
|
|
800da02: 681b ldr r3, [r3, #0]
|
|
800da04: 2b00 cmp r3, #0
|
|
800da06: d0e3 beq.n 800d9d0 <vTaskSwitchContext+0x24>
|
|
800da08: 68fa ldr r2, [r7, #12]
|
|
800da0a: 4613 mov r3, r2
|
|
800da0c: 009b lsls r3, r3, #2
|
|
800da0e: 4413 add r3, r2
|
|
800da10: 009b lsls r3, r3, #2
|
|
800da12: 4a13 ldr r2, [pc, #76] @ (800da60 <vTaskSwitchContext+0xb4>)
|
|
800da14: 4413 add r3, r2
|
|
800da16: 60bb str r3, [r7, #8]
|
|
800da18: 68bb ldr r3, [r7, #8]
|
|
800da1a: 685b ldr r3, [r3, #4]
|
|
800da1c: 685a ldr r2, [r3, #4]
|
|
800da1e: 68bb ldr r3, [r7, #8]
|
|
800da20: 605a str r2, [r3, #4]
|
|
800da22: 68bb ldr r3, [r7, #8]
|
|
800da24: 685a ldr r2, [r3, #4]
|
|
800da26: 68bb ldr r3, [r7, #8]
|
|
800da28: 3308 adds r3, #8
|
|
800da2a: 429a cmp r2, r3
|
|
800da2c: d104 bne.n 800da38 <vTaskSwitchContext+0x8c>
|
|
800da2e: 68bb ldr r3, [r7, #8]
|
|
800da30: 685b ldr r3, [r3, #4]
|
|
800da32: 685a ldr r2, [r3, #4]
|
|
800da34: 68bb ldr r3, [r7, #8]
|
|
800da36: 605a str r2, [r3, #4]
|
|
800da38: 68bb ldr r3, [r7, #8]
|
|
800da3a: 685b ldr r3, [r3, #4]
|
|
800da3c: 68db ldr r3, [r3, #12]
|
|
800da3e: 4a09 ldr r2, [pc, #36] @ (800da64 <vTaskSwitchContext+0xb8>)
|
|
800da40: 6013 str r3, [r2, #0]
|
|
800da42: 4a06 ldr r2, [pc, #24] @ (800da5c <vTaskSwitchContext+0xb0>)
|
|
800da44: 68fb ldr r3, [r7, #12]
|
|
800da46: 6013 str r3, [r2, #0]
|
|
}
|
|
800da48: bf00 nop
|
|
800da4a: 3714 adds r7, #20
|
|
800da4c: 46bd mov sp, r7
|
|
800da4e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800da52: 4770 bx lr
|
|
800da54: 2000287c .word 0x2000287c
|
|
800da58: 20002868 .word 0x20002868
|
|
800da5c: 2000285c .word 0x2000285c
|
|
800da60: 20002384 .word 0x20002384
|
|
800da64: 20002380 .word 0x20002380
|
|
|
|
0800da68 <vTaskPlaceOnEventList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
|
|
{
|
|
800da68: b580 push {r7, lr}
|
|
800da6a: b084 sub sp, #16
|
|
800da6c: af00 add r7, sp, #0
|
|
800da6e: 6078 str r0, [r7, #4]
|
|
800da70: 6039 str r1, [r7, #0]
|
|
configASSERT( pxEventList );
|
|
800da72: 687b ldr r3, [r7, #4]
|
|
800da74: 2b00 cmp r3, #0
|
|
800da76: d10b bne.n 800da90 <vTaskPlaceOnEventList+0x28>
|
|
__asm volatile
|
|
800da78: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800da7c: f383 8811 msr BASEPRI, r3
|
|
800da80: f3bf 8f6f isb sy
|
|
800da84: f3bf 8f4f dsb sy
|
|
800da88: 60fb str r3, [r7, #12]
|
|
}
|
|
800da8a: bf00 nop
|
|
800da8c: bf00 nop
|
|
800da8e: e7fd b.n 800da8c <vTaskPlaceOnEventList+0x24>
|
|
|
|
/* Place the event list item of the TCB in the appropriate event list.
|
|
This is placed in the list in priority order so the highest priority task
|
|
is the first to be woken by the event. The queue that contains the event
|
|
list is locked, preventing simultaneous access from interrupts. */
|
|
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
|
800da90: 4b07 ldr r3, [pc, #28] @ (800dab0 <vTaskPlaceOnEventList+0x48>)
|
|
800da92: 681b ldr r3, [r3, #0]
|
|
800da94: 3318 adds r3, #24
|
|
800da96: 4619 mov r1, r3
|
|
800da98: 6878 ldr r0, [r7, #4]
|
|
800da9a: f7fe fcb2 bl 800c402 <vListInsert>
|
|
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
|
800da9e: 2101 movs r1, #1
|
|
800daa0: 6838 ldr r0, [r7, #0]
|
|
800daa2: f000 fc83 bl 800e3ac <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
800daa6: bf00 nop
|
|
800daa8: 3710 adds r7, #16
|
|
800daaa: 46bd mov sp, r7
|
|
800daac: bd80 pop {r7, pc}
|
|
800daae: bf00 nop
|
|
800dab0: 20002380 .word 0x20002380
|
|
|
|
0800dab4 <vTaskPlaceOnEventListRestricted>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configUSE_TIMERS == 1 )
|
|
|
|
void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
|
|
{
|
|
800dab4: b580 push {r7, lr}
|
|
800dab6: b086 sub sp, #24
|
|
800dab8: af00 add r7, sp, #0
|
|
800daba: 60f8 str r0, [r7, #12]
|
|
800dabc: 60b9 str r1, [r7, #8]
|
|
800dabe: 607a str r2, [r7, #4]
|
|
configASSERT( pxEventList );
|
|
800dac0: 68fb ldr r3, [r7, #12]
|
|
800dac2: 2b00 cmp r3, #0
|
|
800dac4: d10b bne.n 800dade <vTaskPlaceOnEventListRestricted+0x2a>
|
|
__asm volatile
|
|
800dac6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800daca: f383 8811 msr BASEPRI, r3
|
|
800dace: f3bf 8f6f isb sy
|
|
800dad2: f3bf 8f4f dsb sy
|
|
800dad6: 617b str r3, [r7, #20]
|
|
}
|
|
800dad8: bf00 nop
|
|
800dada: bf00 nop
|
|
800dadc: e7fd b.n 800dada <vTaskPlaceOnEventListRestricted+0x26>
|
|
|
|
/* Place the event list item of the TCB in the appropriate event list.
|
|
In this case it is assume that this is the only task that is going to
|
|
be waiting on this event list, so the faster vListInsertEnd() function
|
|
can be used in place of vListInsert. */
|
|
vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
|
800dade: 4b0a ldr r3, [pc, #40] @ (800db08 <vTaskPlaceOnEventListRestricted+0x54>)
|
|
800dae0: 681b ldr r3, [r3, #0]
|
|
800dae2: 3318 adds r3, #24
|
|
800dae4: 4619 mov r1, r3
|
|
800dae6: 68f8 ldr r0, [r7, #12]
|
|
800dae8: f7fe fc67 bl 800c3ba <vListInsertEnd>
|
|
|
|
/* If the task should block indefinitely then set the block time to a
|
|
value that will be recognised as an indefinite delay inside the
|
|
prvAddCurrentTaskToDelayedList() function. */
|
|
if( xWaitIndefinitely != pdFALSE )
|
|
800daec: 687b ldr r3, [r7, #4]
|
|
800daee: 2b00 cmp r3, #0
|
|
800daf0: d002 beq.n 800daf8 <vTaskPlaceOnEventListRestricted+0x44>
|
|
{
|
|
xTicksToWait = portMAX_DELAY;
|
|
800daf2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800daf6: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
|
|
800daf8: 6879 ldr r1, [r7, #4]
|
|
800dafa: 68b8 ldr r0, [r7, #8]
|
|
800dafc: f000 fc56 bl 800e3ac <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
800db00: bf00 nop
|
|
800db02: 3718 adds r7, #24
|
|
800db04: 46bd mov sp, r7
|
|
800db06: bd80 pop {r7, pc}
|
|
800db08: 20002380 .word 0x20002380
|
|
|
|
0800db0c <xTaskRemoveFromEventList>:
|
|
|
|
#endif /* configUSE_TIMERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
|
|
{
|
|
800db0c: b580 push {r7, lr}
|
|
800db0e: b086 sub sp, #24
|
|
800db10: af00 add r7, sp, #0
|
|
800db12: 6078 str r0, [r7, #4]
|
|
get called - the lock count on the queue will get modified instead. This
|
|
means exclusive access to the event list is guaranteed here.
|
|
|
|
This function assumes that a check has already been made to ensure that
|
|
pxEventList is not empty. */
|
|
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800db14: 687b ldr r3, [r7, #4]
|
|
800db16: 68db ldr r3, [r3, #12]
|
|
800db18: 68db ldr r3, [r3, #12]
|
|
800db1a: 613b str r3, [r7, #16]
|
|
configASSERT( pxUnblockedTCB );
|
|
800db1c: 693b ldr r3, [r7, #16]
|
|
800db1e: 2b00 cmp r3, #0
|
|
800db20: d10b bne.n 800db3a <xTaskRemoveFromEventList+0x2e>
|
|
__asm volatile
|
|
800db22: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800db26: f383 8811 msr BASEPRI, r3
|
|
800db2a: f3bf 8f6f isb sy
|
|
800db2e: f3bf 8f4f dsb sy
|
|
800db32: 60fb str r3, [r7, #12]
|
|
}
|
|
800db34: bf00 nop
|
|
800db36: bf00 nop
|
|
800db38: e7fd b.n 800db36 <xTaskRemoveFromEventList+0x2a>
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
|
|
800db3a: 693b ldr r3, [r7, #16]
|
|
800db3c: 3318 adds r3, #24
|
|
800db3e: 4618 mov r0, r3
|
|
800db40: f7fe fc98 bl 800c474 <uxListRemove>
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800db44: 4b1d ldr r3, [pc, #116] @ (800dbbc <xTaskRemoveFromEventList+0xb0>)
|
|
800db46: 681b ldr r3, [r3, #0]
|
|
800db48: 2b00 cmp r3, #0
|
|
800db4a: d11d bne.n 800db88 <xTaskRemoveFromEventList+0x7c>
|
|
{
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
|
|
800db4c: 693b ldr r3, [r7, #16]
|
|
800db4e: 3304 adds r3, #4
|
|
800db50: 4618 mov r0, r3
|
|
800db52: f7fe fc8f bl 800c474 <uxListRemove>
|
|
prvAddTaskToReadyList( pxUnblockedTCB );
|
|
800db56: 693b ldr r3, [r7, #16]
|
|
800db58: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800db5a: 4b19 ldr r3, [pc, #100] @ (800dbc0 <xTaskRemoveFromEventList+0xb4>)
|
|
800db5c: 681b ldr r3, [r3, #0]
|
|
800db5e: 429a cmp r2, r3
|
|
800db60: d903 bls.n 800db6a <xTaskRemoveFromEventList+0x5e>
|
|
800db62: 693b ldr r3, [r7, #16]
|
|
800db64: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800db66: 4a16 ldr r2, [pc, #88] @ (800dbc0 <xTaskRemoveFromEventList+0xb4>)
|
|
800db68: 6013 str r3, [r2, #0]
|
|
800db6a: 693b ldr r3, [r7, #16]
|
|
800db6c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800db6e: 4613 mov r3, r2
|
|
800db70: 009b lsls r3, r3, #2
|
|
800db72: 4413 add r3, r2
|
|
800db74: 009b lsls r3, r3, #2
|
|
800db76: 4a13 ldr r2, [pc, #76] @ (800dbc4 <xTaskRemoveFromEventList+0xb8>)
|
|
800db78: 441a add r2, r3
|
|
800db7a: 693b ldr r3, [r7, #16]
|
|
800db7c: 3304 adds r3, #4
|
|
800db7e: 4619 mov r1, r3
|
|
800db80: 4610 mov r0, r2
|
|
800db82: f7fe fc1a bl 800c3ba <vListInsertEnd>
|
|
800db86: e005 b.n 800db94 <xTaskRemoveFromEventList+0x88>
|
|
}
|
|
else
|
|
{
|
|
/* The delayed and ready lists cannot be accessed, so hold this task
|
|
pending until the scheduler is resumed. */
|
|
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
|
|
800db88: 693b ldr r3, [r7, #16]
|
|
800db8a: 3318 adds r3, #24
|
|
800db8c: 4619 mov r1, r3
|
|
800db8e: 480e ldr r0, [pc, #56] @ (800dbc8 <xTaskRemoveFromEventList+0xbc>)
|
|
800db90: f7fe fc13 bl 800c3ba <vListInsertEnd>
|
|
}
|
|
|
|
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
800db94: 693b ldr r3, [r7, #16]
|
|
800db96: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800db98: 4b0c ldr r3, [pc, #48] @ (800dbcc <xTaskRemoveFromEventList+0xc0>)
|
|
800db9a: 681b ldr r3, [r3, #0]
|
|
800db9c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800db9e: 429a cmp r2, r3
|
|
800dba0: d905 bls.n 800dbae <xTaskRemoveFromEventList+0xa2>
|
|
{
|
|
/* Return true if the task removed from the event list has a higher
|
|
priority than the calling task. This allows the calling task to know if
|
|
it should force a context switch now. */
|
|
xReturn = pdTRUE;
|
|
800dba2: 2301 movs r3, #1
|
|
800dba4: 617b str r3, [r7, #20]
|
|
|
|
/* Mark that a yield is pending in case the user is not using the
|
|
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
|
|
xYieldPending = pdTRUE;
|
|
800dba6: 4b0a ldr r3, [pc, #40] @ (800dbd0 <xTaskRemoveFromEventList+0xc4>)
|
|
800dba8: 2201 movs r2, #1
|
|
800dbaa: 601a str r2, [r3, #0]
|
|
800dbac: e001 b.n 800dbb2 <xTaskRemoveFromEventList+0xa6>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800dbae: 2300 movs r3, #0
|
|
800dbb0: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
return xReturn;
|
|
800dbb2: 697b ldr r3, [r7, #20]
|
|
}
|
|
800dbb4: 4618 mov r0, r3
|
|
800dbb6: 3718 adds r7, #24
|
|
800dbb8: 46bd mov sp, r7
|
|
800dbba: bd80 pop {r7, pc}
|
|
800dbbc: 2000287c .word 0x2000287c
|
|
800dbc0: 2000285c .word 0x2000285c
|
|
800dbc4: 20002384 .word 0x20002384
|
|
800dbc8: 20002814 .word 0x20002814
|
|
800dbcc: 20002380 .word 0x20002380
|
|
800dbd0: 20002868 .word 0x20002868
|
|
|
|
0800dbd4 <vTaskInternalSetTimeOutState>:
|
|
taskEXIT_CRITICAL();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
|
|
{
|
|
800dbd4: b480 push {r7}
|
|
800dbd6: b083 sub sp, #12
|
|
800dbd8: af00 add r7, sp, #0
|
|
800dbda: 6078 str r0, [r7, #4]
|
|
/* For internal use only as it does not use a critical section. */
|
|
pxTimeOut->xOverflowCount = xNumOfOverflows;
|
|
800dbdc: 4b06 ldr r3, [pc, #24] @ (800dbf8 <vTaskInternalSetTimeOutState+0x24>)
|
|
800dbde: 681a ldr r2, [r3, #0]
|
|
800dbe0: 687b ldr r3, [r7, #4]
|
|
800dbe2: 601a str r2, [r3, #0]
|
|
pxTimeOut->xTimeOnEntering = xTickCount;
|
|
800dbe4: 4b05 ldr r3, [pc, #20] @ (800dbfc <vTaskInternalSetTimeOutState+0x28>)
|
|
800dbe6: 681a ldr r2, [r3, #0]
|
|
800dbe8: 687b ldr r3, [r7, #4]
|
|
800dbea: 605a str r2, [r3, #4]
|
|
}
|
|
800dbec: bf00 nop
|
|
800dbee: 370c adds r7, #12
|
|
800dbf0: 46bd mov sp, r7
|
|
800dbf2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dbf6: 4770 bx lr
|
|
800dbf8: 2000286c .word 0x2000286c
|
|
800dbfc: 20002858 .word 0x20002858
|
|
|
|
0800dc00 <xTaskCheckForTimeOut>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
|
|
{
|
|
800dc00: b580 push {r7, lr}
|
|
800dc02: b088 sub sp, #32
|
|
800dc04: af00 add r7, sp, #0
|
|
800dc06: 6078 str r0, [r7, #4]
|
|
800dc08: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
|
|
configASSERT( pxTimeOut );
|
|
800dc0a: 687b ldr r3, [r7, #4]
|
|
800dc0c: 2b00 cmp r3, #0
|
|
800dc0e: d10b bne.n 800dc28 <xTaskCheckForTimeOut+0x28>
|
|
__asm volatile
|
|
800dc10: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800dc14: f383 8811 msr BASEPRI, r3
|
|
800dc18: f3bf 8f6f isb sy
|
|
800dc1c: f3bf 8f4f dsb sy
|
|
800dc20: 613b str r3, [r7, #16]
|
|
}
|
|
800dc22: bf00 nop
|
|
800dc24: bf00 nop
|
|
800dc26: e7fd b.n 800dc24 <xTaskCheckForTimeOut+0x24>
|
|
configASSERT( pxTicksToWait );
|
|
800dc28: 683b ldr r3, [r7, #0]
|
|
800dc2a: 2b00 cmp r3, #0
|
|
800dc2c: d10b bne.n 800dc46 <xTaskCheckForTimeOut+0x46>
|
|
__asm volatile
|
|
800dc2e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800dc32: f383 8811 msr BASEPRI, r3
|
|
800dc36: f3bf 8f6f isb sy
|
|
800dc3a: f3bf 8f4f dsb sy
|
|
800dc3e: 60fb str r3, [r7, #12]
|
|
}
|
|
800dc40: bf00 nop
|
|
800dc42: bf00 nop
|
|
800dc44: e7fd b.n 800dc42 <xTaskCheckForTimeOut+0x42>
|
|
|
|
taskENTER_CRITICAL();
|
|
800dc46: f001 f88f bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this block. */
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
800dc4a: 4b1d ldr r3, [pc, #116] @ (800dcc0 <xTaskCheckForTimeOut+0xc0>)
|
|
800dc4c: 681b ldr r3, [r3, #0]
|
|
800dc4e: 61bb str r3, [r7, #24]
|
|
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
|
|
800dc50: 687b ldr r3, [r7, #4]
|
|
800dc52: 685b ldr r3, [r3, #4]
|
|
800dc54: 69ba ldr r2, [r7, #24]
|
|
800dc56: 1ad3 subs r3, r2, r3
|
|
800dc58: 617b str r3, [r7, #20]
|
|
}
|
|
else
|
|
#endif
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
if( *pxTicksToWait == portMAX_DELAY )
|
|
800dc5a: 683b ldr r3, [r7, #0]
|
|
800dc5c: 681b ldr r3, [r3, #0]
|
|
800dc5e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800dc62: d102 bne.n 800dc6a <xTaskCheckForTimeOut+0x6a>
|
|
{
|
|
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
|
|
specified is the maximum block time then the task should block
|
|
indefinitely, and therefore never time out. */
|
|
xReturn = pdFALSE;
|
|
800dc64: 2300 movs r3, #0
|
|
800dc66: 61fb str r3, [r7, #28]
|
|
800dc68: e023 b.n 800dcb2 <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else
|
|
#endif
|
|
|
|
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
|
|
800dc6a: 687b ldr r3, [r7, #4]
|
|
800dc6c: 681a ldr r2, [r3, #0]
|
|
800dc6e: 4b15 ldr r3, [pc, #84] @ (800dcc4 <xTaskCheckForTimeOut+0xc4>)
|
|
800dc70: 681b ldr r3, [r3, #0]
|
|
800dc72: 429a cmp r2, r3
|
|
800dc74: d007 beq.n 800dc86 <xTaskCheckForTimeOut+0x86>
|
|
800dc76: 687b ldr r3, [r7, #4]
|
|
800dc78: 685b ldr r3, [r3, #4]
|
|
800dc7a: 69ba ldr r2, [r7, #24]
|
|
800dc7c: 429a cmp r2, r3
|
|
800dc7e: d302 bcc.n 800dc86 <xTaskCheckForTimeOut+0x86>
|
|
/* The tick count is greater than the time at which
|
|
vTaskSetTimeout() was called, but has also overflowed since
|
|
vTaskSetTimeOut() was called. It must have wrapped all the way
|
|
around and gone past again. This passed since vTaskSetTimeout()
|
|
was called. */
|
|
xReturn = pdTRUE;
|
|
800dc80: 2301 movs r3, #1
|
|
800dc82: 61fb str r3, [r7, #28]
|
|
800dc84: e015 b.n 800dcb2 <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
|
|
800dc86: 683b ldr r3, [r7, #0]
|
|
800dc88: 681b ldr r3, [r3, #0]
|
|
800dc8a: 697a ldr r2, [r7, #20]
|
|
800dc8c: 429a cmp r2, r3
|
|
800dc8e: d20b bcs.n 800dca8 <xTaskCheckForTimeOut+0xa8>
|
|
{
|
|
/* Not a genuine timeout. Adjust parameters for time remaining. */
|
|
*pxTicksToWait -= xElapsedTime;
|
|
800dc90: 683b ldr r3, [r7, #0]
|
|
800dc92: 681a ldr r2, [r3, #0]
|
|
800dc94: 697b ldr r3, [r7, #20]
|
|
800dc96: 1ad2 subs r2, r2, r3
|
|
800dc98: 683b ldr r3, [r7, #0]
|
|
800dc9a: 601a str r2, [r3, #0]
|
|
vTaskInternalSetTimeOutState( pxTimeOut );
|
|
800dc9c: 6878 ldr r0, [r7, #4]
|
|
800dc9e: f7ff ff99 bl 800dbd4 <vTaskInternalSetTimeOutState>
|
|
xReturn = pdFALSE;
|
|
800dca2: 2300 movs r3, #0
|
|
800dca4: 61fb str r3, [r7, #28]
|
|
800dca6: e004 b.n 800dcb2 <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else
|
|
{
|
|
*pxTicksToWait = 0;
|
|
800dca8: 683b ldr r3, [r7, #0]
|
|
800dcaa: 2200 movs r2, #0
|
|
800dcac: 601a str r2, [r3, #0]
|
|
xReturn = pdTRUE;
|
|
800dcae: 2301 movs r3, #1
|
|
800dcb0: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800dcb2: f001 f88b bl 800edcc <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800dcb6: 69fb ldr r3, [r7, #28]
|
|
}
|
|
800dcb8: 4618 mov r0, r3
|
|
800dcba: 3720 adds r7, #32
|
|
800dcbc: 46bd mov sp, r7
|
|
800dcbe: bd80 pop {r7, pc}
|
|
800dcc0: 20002858 .word 0x20002858
|
|
800dcc4: 2000286c .word 0x2000286c
|
|
|
|
0800dcc8 <vTaskMissedYield>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskMissedYield( void )
|
|
{
|
|
800dcc8: b480 push {r7}
|
|
800dcca: af00 add r7, sp, #0
|
|
xYieldPending = pdTRUE;
|
|
800dccc: 4b03 ldr r3, [pc, #12] @ (800dcdc <vTaskMissedYield+0x14>)
|
|
800dcce: 2201 movs r2, #1
|
|
800dcd0: 601a str r2, [r3, #0]
|
|
}
|
|
800dcd2: bf00 nop
|
|
800dcd4: 46bd mov sp, r7
|
|
800dcd6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dcda: 4770 bx lr
|
|
800dcdc: 20002868 .word 0x20002868
|
|
|
|
0800dce0 <prvIdleTask>:
|
|
*
|
|
* void prvIdleTask( void *pvParameters );
|
|
*
|
|
*/
|
|
static portTASK_FUNCTION( prvIdleTask, pvParameters )
|
|
{
|
|
800dce0: b580 push {r7, lr}
|
|
800dce2: b082 sub sp, #8
|
|
800dce4: af00 add r7, sp, #0
|
|
800dce6: 6078 str r0, [r7, #4]
|
|
|
|
for( ;; )
|
|
{
|
|
/* See if any tasks have deleted themselves - if so then the idle task
|
|
is responsible for freeing the deleted task's TCB and stack. */
|
|
prvCheckTasksWaitingTermination();
|
|
800dce8: f000 f852 bl 800dd90 <prvCheckTasksWaitingTermination>
|
|
|
|
A critical region is not required here as we are just reading from
|
|
the list, and an occasional incorrect value will not matter. If
|
|
the ready list at the idle priority contains more than one task
|
|
then a task other than the idle task is ready to execute. */
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
|
|
800dcec: 4b06 ldr r3, [pc, #24] @ (800dd08 <prvIdleTask+0x28>)
|
|
800dcee: 681b ldr r3, [r3, #0]
|
|
800dcf0: 2b01 cmp r3, #1
|
|
800dcf2: d9f9 bls.n 800dce8 <prvIdleTask+0x8>
|
|
{
|
|
taskYIELD();
|
|
800dcf4: 4b05 ldr r3, [pc, #20] @ (800dd0c <prvIdleTask+0x2c>)
|
|
800dcf6: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800dcfa: 601a str r2, [r3, #0]
|
|
800dcfc: f3bf 8f4f dsb sy
|
|
800dd00: f3bf 8f6f isb sy
|
|
prvCheckTasksWaitingTermination();
|
|
800dd04: e7f0 b.n 800dce8 <prvIdleTask+0x8>
|
|
800dd06: bf00 nop
|
|
800dd08: 20002384 .word 0x20002384
|
|
800dd0c: e000ed04 .word 0xe000ed04
|
|
|
|
0800dd10 <prvInitialiseTaskLists>:
|
|
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInitialiseTaskLists( void )
|
|
{
|
|
800dd10: b580 push {r7, lr}
|
|
800dd12: b082 sub sp, #8
|
|
800dd14: af00 add r7, sp, #0
|
|
UBaseType_t uxPriority;
|
|
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
|
800dd16: 2300 movs r3, #0
|
|
800dd18: 607b str r3, [r7, #4]
|
|
800dd1a: e00c b.n 800dd36 <prvInitialiseTaskLists+0x26>
|
|
{
|
|
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
|
|
800dd1c: 687a ldr r2, [r7, #4]
|
|
800dd1e: 4613 mov r3, r2
|
|
800dd20: 009b lsls r3, r3, #2
|
|
800dd22: 4413 add r3, r2
|
|
800dd24: 009b lsls r3, r3, #2
|
|
800dd26: 4a12 ldr r2, [pc, #72] @ (800dd70 <prvInitialiseTaskLists+0x60>)
|
|
800dd28: 4413 add r3, r2
|
|
800dd2a: 4618 mov r0, r3
|
|
800dd2c: f7fe fb18 bl 800c360 <vListInitialise>
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
|
800dd30: 687b ldr r3, [r7, #4]
|
|
800dd32: 3301 adds r3, #1
|
|
800dd34: 607b str r3, [r7, #4]
|
|
800dd36: 687b ldr r3, [r7, #4]
|
|
800dd38: 2b37 cmp r3, #55 @ 0x37
|
|
800dd3a: d9ef bls.n 800dd1c <prvInitialiseTaskLists+0xc>
|
|
}
|
|
|
|
vListInitialise( &xDelayedTaskList1 );
|
|
800dd3c: 480d ldr r0, [pc, #52] @ (800dd74 <prvInitialiseTaskLists+0x64>)
|
|
800dd3e: f7fe fb0f bl 800c360 <vListInitialise>
|
|
vListInitialise( &xDelayedTaskList2 );
|
|
800dd42: 480d ldr r0, [pc, #52] @ (800dd78 <prvInitialiseTaskLists+0x68>)
|
|
800dd44: f7fe fb0c bl 800c360 <vListInitialise>
|
|
vListInitialise( &xPendingReadyList );
|
|
800dd48: 480c ldr r0, [pc, #48] @ (800dd7c <prvInitialiseTaskLists+0x6c>)
|
|
800dd4a: f7fe fb09 bl 800c360 <vListInitialise>
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
{
|
|
vListInitialise( &xTasksWaitingTermination );
|
|
800dd4e: 480c ldr r0, [pc, #48] @ (800dd80 <prvInitialiseTaskLists+0x70>)
|
|
800dd50: f7fe fb06 bl 800c360 <vListInitialise>
|
|
}
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
vListInitialise( &xSuspendedTaskList );
|
|
800dd54: 480b ldr r0, [pc, #44] @ (800dd84 <prvInitialiseTaskLists+0x74>)
|
|
800dd56: f7fe fb03 bl 800c360 <vListInitialise>
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
|
|
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
|
|
using list2. */
|
|
pxDelayedTaskList = &xDelayedTaskList1;
|
|
800dd5a: 4b0b ldr r3, [pc, #44] @ (800dd88 <prvInitialiseTaskLists+0x78>)
|
|
800dd5c: 4a05 ldr r2, [pc, #20] @ (800dd74 <prvInitialiseTaskLists+0x64>)
|
|
800dd5e: 601a str r2, [r3, #0]
|
|
pxOverflowDelayedTaskList = &xDelayedTaskList2;
|
|
800dd60: 4b0a ldr r3, [pc, #40] @ (800dd8c <prvInitialiseTaskLists+0x7c>)
|
|
800dd62: 4a05 ldr r2, [pc, #20] @ (800dd78 <prvInitialiseTaskLists+0x68>)
|
|
800dd64: 601a str r2, [r3, #0]
|
|
}
|
|
800dd66: bf00 nop
|
|
800dd68: 3708 adds r7, #8
|
|
800dd6a: 46bd mov sp, r7
|
|
800dd6c: bd80 pop {r7, pc}
|
|
800dd6e: bf00 nop
|
|
800dd70: 20002384 .word 0x20002384
|
|
800dd74: 200027e4 .word 0x200027e4
|
|
800dd78: 200027f8 .word 0x200027f8
|
|
800dd7c: 20002814 .word 0x20002814
|
|
800dd80: 20002828 .word 0x20002828
|
|
800dd84: 20002840 .word 0x20002840
|
|
800dd88: 2000280c .word 0x2000280c
|
|
800dd8c: 20002810 .word 0x20002810
|
|
|
|
0800dd90 <prvCheckTasksWaitingTermination>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCheckTasksWaitingTermination( void )
|
|
{
|
|
800dd90: b580 push {r7, lr}
|
|
800dd92: b082 sub sp, #8
|
|
800dd94: af00 add r7, sp, #0
|
|
{
|
|
TCB_t *pxTCB;
|
|
|
|
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
|
|
being called too often in the idle task. */
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
|
800dd96: e019 b.n 800ddcc <prvCheckTasksWaitingTermination+0x3c>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800dd98: f000 ffe6 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800dd9c: 4b10 ldr r3, [pc, #64] @ (800dde0 <prvCheckTasksWaitingTermination+0x50>)
|
|
800dd9e: 68db ldr r3, [r3, #12]
|
|
800dda0: 68db ldr r3, [r3, #12]
|
|
800dda2: 607b str r3, [r7, #4]
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800dda4: 687b ldr r3, [r7, #4]
|
|
800dda6: 3304 adds r3, #4
|
|
800dda8: 4618 mov r0, r3
|
|
800ddaa: f7fe fb63 bl 800c474 <uxListRemove>
|
|
--uxCurrentNumberOfTasks;
|
|
800ddae: 4b0d ldr r3, [pc, #52] @ (800dde4 <prvCheckTasksWaitingTermination+0x54>)
|
|
800ddb0: 681b ldr r3, [r3, #0]
|
|
800ddb2: 3b01 subs r3, #1
|
|
800ddb4: 4a0b ldr r2, [pc, #44] @ (800dde4 <prvCheckTasksWaitingTermination+0x54>)
|
|
800ddb6: 6013 str r3, [r2, #0]
|
|
--uxDeletedTasksWaitingCleanUp;
|
|
800ddb8: 4b0b ldr r3, [pc, #44] @ (800dde8 <prvCheckTasksWaitingTermination+0x58>)
|
|
800ddba: 681b ldr r3, [r3, #0]
|
|
800ddbc: 3b01 subs r3, #1
|
|
800ddbe: 4a0a ldr r2, [pc, #40] @ (800dde8 <prvCheckTasksWaitingTermination+0x58>)
|
|
800ddc0: 6013 str r3, [r2, #0]
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ddc2: f001 f803 bl 800edcc <vPortExitCritical>
|
|
|
|
prvDeleteTCB( pxTCB );
|
|
800ddc6: 6878 ldr r0, [r7, #4]
|
|
800ddc8: f000 f810 bl 800ddec <prvDeleteTCB>
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
|
800ddcc: 4b06 ldr r3, [pc, #24] @ (800dde8 <prvCheckTasksWaitingTermination+0x58>)
|
|
800ddce: 681b ldr r3, [r3, #0]
|
|
800ddd0: 2b00 cmp r3, #0
|
|
800ddd2: d1e1 bne.n 800dd98 <prvCheckTasksWaitingTermination+0x8>
|
|
}
|
|
}
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
}
|
|
800ddd4: bf00 nop
|
|
800ddd6: bf00 nop
|
|
800ddd8: 3708 adds r7, #8
|
|
800ddda: 46bd mov sp, r7
|
|
800dddc: bd80 pop {r7, pc}
|
|
800ddde: bf00 nop
|
|
800dde0: 20002828 .word 0x20002828
|
|
800dde4: 20002854 .word 0x20002854
|
|
800dde8: 2000283c .word 0x2000283c
|
|
|
|
0800ddec <prvDeleteTCB>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
|
|
static void prvDeleteTCB( TCB_t *pxTCB )
|
|
{
|
|
800ddec: b580 push {r7, lr}
|
|
800ddee: b084 sub sp, #16
|
|
800ddf0: af00 add r7, sp, #0
|
|
800ddf2: 6078 str r0, [r7, #4]
|
|
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* The task could have been allocated statically or dynamically, so
|
|
check what was statically allocated before trying to free the
|
|
memory. */
|
|
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
|
|
800ddf4: 687b ldr r3, [r7, #4]
|
|
800ddf6: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
|
|
800ddfa: 2b00 cmp r3, #0
|
|
800ddfc: d108 bne.n 800de10 <prvDeleteTCB+0x24>
|
|
{
|
|
/* Both the stack and TCB were allocated dynamically, so both
|
|
must be freed. */
|
|
vPortFree( pxTCB->pxStack );
|
|
800ddfe: 687b ldr r3, [r7, #4]
|
|
800de00: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800de02: 4618 mov r0, r3
|
|
800de04: f001 f9a0 bl 800f148 <vPortFree>
|
|
vPortFree( pxTCB );
|
|
800de08: 6878 ldr r0, [r7, #4]
|
|
800de0a: f001 f99d bl 800f148 <vPortFree>
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
}
|
|
800de0e: e019 b.n 800de44 <prvDeleteTCB+0x58>
|
|
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
|
|
800de10: 687b ldr r3, [r7, #4]
|
|
800de12: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
|
|
800de16: 2b01 cmp r3, #1
|
|
800de18: d103 bne.n 800de22 <prvDeleteTCB+0x36>
|
|
vPortFree( pxTCB );
|
|
800de1a: 6878 ldr r0, [r7, #4]
|
|
800de1c: f001 f994 bl 800f148 <vPortFree>
|
|
}
|
|
800de20: e010 b.n 800de44 <prvDeleteTCB+0x58>
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
|
800de22: 687b ldr r3, [r7, #4]
|
|
800de24: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
|
|
800de28: 2b02 cmp r3, #2
|
|
800de2a: d00b beq.n 800de44 <prvDeleteTCB+0x58>
|
|
__asm volatile
|
|
800de2c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800de30: f383 8811 msr BASEPRI, r3
|
|
800de34: f3bf 8f6f isb sy
|
|
800de38: f3bf 8f4f dsb sy
|
|
800de3c: 60fb str r3, [r7, #12]
|
|
}
|
|
800de3e: bf00 nop
|
|
800de40: bf00 nop
|
|
800de42: e7fd b.n 800de40 <prvDeleteTCB+0x54>
|
|
}
|
|
800de44: bf00 nop
|
|
800de46: 3710 adds r7, #16
|
|
800de48: 46bd mov sp, r7
|
|
800de4a: bd80 pop {r7, pc}
|
|
|
|
0800de4c <prvResetNextTaskUnblockTime>:
|
|
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvResetNextTaskUnblockTime( void )
|
|
{
|
|
800de4c: b480 push {r7}
|
|
800de4e: b083 sub sp, #12
|
|
800de50: af00 add r7, sp, #0
|
|
TCB_t *pxTCB;
|
|
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800de52: 4b0c ldr r3, [pc, #48] @ (800de84 <prvResetNextTaskUnblockTime+0x38>)
|
|
800de54: 681b ldr r3, [r3, #0]
|
|
800de56: 681b ldr r3, [r3, #0]
|
|
800de58: 2b00 cmp r3, #0
|
|
800de5a: d104 bne.n 800de66 <prvResetNextTaskUnblockTime+0x1a>
|
|
{
|
|
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
|
|
the maximum possible value so it is extremely unlikely that the
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
|
|
there is an item in the delayed list. */
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
800de5c: 4b0a ldr r3, [pc, #40] @ (800de88 <prvResetNextTaskUnblockTime+0x3c>)
|
|
800de5e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800de62: 601a str r2, [r3, #0]
|
|
which the task at the head of the delayed list should be removed
|
|
from the Blocked state. */
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
|
}
|
|
}
|
|
800de64: e008 b.n 800de78 <prvResetNextTaskUnblockTime+0x2c>
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800de66: 4b07 ldr r3, [pc, #28] @ (800de84 <prvResetNextTaskUnblockTime+0x38>)
|
|
800de68: 681b ldr r3, [r3, #0]
|
|
800de6a: 68db ldr r3, [r3, #12]
|
|
800de6c: 68db ldr r3, [r3, #12]
|
|
800de6e: 607b str r3, [r7, #4]
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
|
800de70: 687b ldr r3, [r7, #4]
|
|
800de72: 685b ldr r3, [r3, #4]
|
|
800de74: 4a04 ldr r2, [pc, #16] @ (800de88 <prvResetNextTaskUnblockTime+0x3c>)
|
|
800de76: 6013 str r3, [r2, #0]
|
|
}
|
|
800de78: bf00 nop
|
|
800de7a: 370c adds r7, #12
|
|
800de7c: 46bd mov sp, r7
|
|
800de7e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800de82: 4770 bx lr
|
|
800de84: 2000280c .word 0x2000280c
|
|
800de88: 20002874 .word 0x20002874
|
|
|
|
0800de8c <xTaskGetSchedulerState>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
|
|
BaseType_t xTaskGetSchedulerState( void )
|
|
{
|
|
800de8c: b480 push {r7}
|
|
800de8e: b083 sub sp, #12
|
|
800de90: af00 add r7, sp, #0
|
|
BaseType_t xReturn;
|
|
|
|
if( xSchedulerRunning == pdFALSE )
|
|
800de92: 4b0b ldr r3, [pc, #44] @ (800dec0 <xTaskGetSchedulerState+0x34>)
|
|
800de94: 681b ldr r3, [r3, #0]
|
|
800de96: 2b00 cmp r3, #0
|
|
800de98: d102 bne.n 800dea0 <xTaskGetSchedulerState+0x14>
|
|
{
|
|
xReturn = taskSCHEDULER_NOT_STARTED;
|
|
800de9a: 2301 movs r3, #1
|
|
800de9c: 607b str r3, [r7, #4]
|
|
800de9e: e008 b.n 800deb2 <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800dea0: 4b08 ldr r3, [pc, #32] @ (800dec4 <xTaskGetSchedulerState+0x38>)
|
|
800dea2: 681b ldr r3, [r3, #0]
|
|
800dea4: 2b00 cmp r3, #0
|
|
800dea6: d102 bne.n 800deae <xTaskGetSchedulerState+0x22>
|
|
{
|
|
xReturn = taskSCHEDULER_RUNNING;
|
|
800dea8: 2302 movs r3, #2
|
|
800deaa: 607b str r3, [r7, #4]
|
|
800deac: e001 b.n 800deb2 <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
xReturn = taskSCHEDULER_SUSPENDED;
|
|
800deae: 2300 movs r3, #0
|
|
800deb0: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
return xReturn;
|
|
800deb2: 687b ldr r3, [r7, #4]
|
|
}
|
|
800deb4: 4618 mov r0, r3
|
|
800deb6: 370c adds r7, #12
|
|
800deb8: 46bd mov sp, r7
|
|
800deba: f85d 7b04 ldr.w r7, [sp], #4
|
|
800debe: 4770 bx lr
|
|
800dec0: 20002860 .word 0x20002860
|
|
800dec4: 2000287c .word 0x2000287c
|
|
|
|
0800dec8 <xTaskPriorityInherit>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
|
|
{
|
|
800dec8: b580 push {r7, lr}
|
|
800deca: b084 sub sp, #16
|
|
800decc: af00 add r7, sp, #0
|
|
800dece: 6078 str r0, [r7, #4]
|
|
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
|
|
800ded0: 687b ldr r3, [r7, #4]
|
|
800ded2: 60bb str r3, [r7, #8]
|
|
BaseType_t xReturn = pdFALSE;
|
|
800ded4: 2300 movs r3, #0
|
|
800ded6: 60fb str r3, [r7, #12]
|
|
|
|
/* If the mutex was given back by an interrupt while the queue was
|
|
locked then the mutex holder might now be NULL. _RB_ Is this still
|
|
needed as interrupts can no longer use mutexes? */
|
|
if( pxMutexHolder != NULL )
|
|
800ded8: 687b ldr r3, [r7, #4]
|
|
800deda: 2b00 cmp r3, #0
|
|
800dedc: d051 beq.n 800df82 <xTaskPriorityInherit+0xba>
|
|
{
|
|
/* If the holder of the mutex has a priority below the priority of
|
|
the task attempting to obtain the mutex then it will temporarily
|
|
inherit the priority of the task attempting to obtain the mutex. */
|
|
if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
|
|
800dede: 68bb ldr r3, [r7, #8]
|
|
800dee0: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800dee2: 4b2a ldr r3, [pc, #168] @ (800df8c <xTaskPriorityInherit+0xc4>)
|
|
800dee4: 681b ldr r3, [r3, #0]
|
|
800dee6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800dee8: 429a cmp r2, r3
|
|
800deea: d241 bcs.n 800df70 <xTaskPriorityInherit+0xa8>
|
|
{
|
|
/* Adjust the mutex holder state to account for its new
|
|
priority. Only reset the event list item value if the value is
|
|
not being used for anything else. */
|
|
if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
|
|
800deec: 68bb ldr r3, [r7, #8]
|
|
800deee: 699b ldr r3, [r3, #24]
|
|
800def0: 2b00 cmp r3, #0
|
|
800def2: db06 blt.n 800df02 <xTaskPriorityInherit+0x3a>
|
|
{
|
|
listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800def4: 4b25 ldr r3, [pc, #148] @ (800df8c <xTaskPriorityInherit+0xc4>)
|
|
800def6: 681b ldr r3, [r3, #0]
|
|
800def8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800defa: f1c3 0238 rsb r2, r3, #56 @ 0x38
|
|
800defe: 68bb ldr r3, [r7, #8]
|
|
800df00: 619a str r2, [r3, #24]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* If the task being modified is in the ready state it will need
|
|
to be moved into a new list. */
|
|
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
|
|
800df02: 68bb ldr r3, [r7, #8]
|
|
800df04: 6959 ldr r1, [r3, #20]
|
|
800df06: 68bb ldr r3, [r7, #8]
|
|
800df08: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800df0a: 4613 mov r3, r2
|
|
800df0c: 009b lsls r3, r3, #2
|
|
800df0e: 4413 add r3, r2
|
|
800df10: 009b lsls r3, r3, #2
|
|
800df12: 4a1f ldr r2, [pc, #124] @ (800df90 <xTaskPriorityInherit+0xc8>)
|
|
800df14: 4413 add r3, r2
|
|
800df16: 4299 cmp r1, r3
|
|
800df18: d122 bne.n 800df60 <xTaskPriorityInherit+0x98>
|
|
{
|
|
if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800df1a: 68bb ldr r3, [r7, #8]
|
|
800df1c: 3304 adds r3, #4
|
|
800df1e: 4618 mov r0, r3
|
|
800df20: f7fe faa8 bl 800c474 <uxListRemove>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Inherit the priority before being moved into the new list. */
|
|
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
|
|
800df24: 4b19 ldr r3, [pc, #100] @ (800df8c <xTaskPriorityInherit+0xc4>)
|
|
800df26: 681b ldr r3, [r3, #0]
|
|
800df28: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800df2a: 68bb ldr r3, [r7, #8]
|
|
800df2c: 62da str r2, [r3, #44] @ 0x2c
|
|
prvAddTaskToReadyList( pxMutexHolderTCB );
|
|
800df2e: 68bb ldr r3, [r7, #8]
|
|
800df30: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800df32: 4b18 ldr r3, [pc, #96] @ (800df94 <xTaskPriorityInherit+0xcc>)
|
|
800df34: 681b ldr r3, [r3, #0]
|
|
800df36: 429a cmp r2, r3
|
|
800df38: d903 bls.n 800df42 <xTaskPriorityInherit+0x7a>
|
|
800df3a: 68bb ldr r3, [r7, #8]
|
|
800df3c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800df3e: 4a15 ldr r2, [pc, #84] @ (800df94 <xTaskPriorityInherit+0xcc>)
|
|
800df40: 6013 str r3, [r2, #0]
|
|
800df42: 68bb ldr r3, [r7, #8]
|
|
800df44: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800df46: 4613 mov r3, r2
|
|
800df48: 009b lsls r3, r3, #2
|
|
800df4a: 4413 add r3, r2
|
|
800df4c: 009b lsls r3, r3, #2
|
|
800df4e: 4a10 ldr r2, [pc, #64] @ (800df90 <xTaskPriorityInherit+0xc8>)
|
|
800df50: 441a add r2, r3
|
|
800df52: 68bb ldr r3, [r7, #8]
|
|
800df54: 3304 adds r3, #4
|
|
800df56: 4619 mov r1, r3
|
|
800df58: 4610 mov r0, r2
|
|
800df5a: f7fe fa2e bl 800c3ba <vListInsertEnd>
|
|
800df5e: e004 b.n 800df6a <xTaskPriorityInherit+0xa2>
|
|
}
|
|
else
|
|
{
|
|
/* Just inherit the priority. */
|
|
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
|
|
800df60: 4b0a ldr r3, [pc, #40] @ (800df8c <xTaskPriorityInherit+0xc4>)
|
|
800df62: 681b ldr r3, [r3, #0]
|
|
800df64: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800df66: 68bb ldr r3, [r7, #8]
|
|
800df68: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
|
|
|
|
/* Inheritance occurred. */
|
|
xReturn = pdTRUE;
|
|
800df6a: 2301 movs r3, #1
|
|
800df6c: 60fb str r3, [r7, #12]
|
|
800df6e: e008 b.n 800df82 <xTaskPriorityInherit+0xba>
|
|
}
|
|
else
|
|
{
|
|
if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
|
|
800df70: 68bb ldr r3, [r7, #8]
|
|
800df72: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
800df74: 4b05 ldr r3, [pc, #20] @ (800df8c <xTaskPriorityInherit+0xc4>)
|
|
800df76: 681b ldr r3, [r3, #0]
|
|
800df78: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800df7a: 429a cmp r2, r3
|
|
800df7c: d201 bcs.n 800df82 <xTaskPriorityInherit+0xba>
|
|
current priority of the mutex holder is not lower than the
|
|
priority of the task attempting to take the mutex.
|
|
Therefore the mutex holder must have already inherited a
|
|
priority, but inheritance would have occurred if that had
|
|
not been the case. */
|
|
xReturn = pdTRUE;
|
|
800df7e: 2301 movs r3, #1
|
|
800df80: 60fb str r3, [r7, #12]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
800df82: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800df84: 4618 mov r0, r3
|
|
800df86: 3710 adds r7, #16
|
|
800df88: 46bd mov sp, r7
|
|
800df8a: bd80 pop {r7, pc}
|
|
800df8c: 20002380 .word 0x20002380
|
|
800df90: 20002384 .word 0x20002384
|
|
800df94: 2000285c .word 0x2000285c
|
|
|
|
0800df98 <xTaskPriorityDisinherit>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
|
|
{
|
|
800df98: b580 push {r7, lr}
|
|
800df9a: b086 sub sp, #24
|
|
800df9c: af00 add r7, sp, #0
|
|
800df9e: 6078 str r0, [r7, #4]
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
|
800dfa0: 687b ldr r3, [r7, #4]
|
|
800dfa2: 613b str r3, [r7, #16]
|
|
BaseType_t xReturn = pdFALSE;
|
|
800dfa4: 2300 movs r3, #0
|
|
800dfa6: 617b str r3, [r7, #20]
|
|
|
|
if( pxMutexHolder != NULL )
|
|
800dfa8: 687b ldr r3, [r7, #4]
|
|
800dfaa: 2b00 cmp r3, #0
|
|
800dfac: d058 beq.n 800e060 <xTaskPriorityDisinherit+0xc8>
|
|
{
|
|
/* A task can only have an inherited priority if it holds the mutex.
|
|
If the mutex is held by a task then it cannot be given from an
|
|
interrupt, and if a mutex is given by the holding task then it must
|
|
be the running state task. */
|
|
configASSERT( pxTCB == pxCurrentTCB );
|
|
800dfae: 4b2f ldr r3, [pc, #188] @ (800e06c <xTaskPriorityDisinherit+0xd4>)
|
|
800dfb0: 681b ldr r3, [r3, #0]
|
|
800dfb2: 693a ldr r2, [r7, #16]
|
|
800dfb4: 429a cmp r2, r3
|
|
800dfb6: d00b beq.n 800dfd0 <xTaskPriorityDisinherit+0x38>
|
|
__asm volatile
|
|
800dfb8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800dfbc: f383 8811 msr BASEPRI, r3
|
|
800dfc0: f3bf 8f6f isb sy
|
|
800dfc4: f3bf 8f4f dsb sy
|
|
800dfc8: 60fb str r3, [r7, #12]
|
|
}
|
|
800dfca: bf00 nop
|
|
800dfcc: bf00 nop
|
|
800dfce: e7fd b.n 800dfcc <xTaskPriorityDisinherit+0x34>
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
|
800dfd0: 693b ldr r3, [r7, #16]
|
|
800dfd2: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800dfd4: 2b00 cmp r3, #0
|
|
800dfd6: d10b bne.n 800dff0 <xTaskPriorityDisinherit+0x58>
|
|
__asm volatile
|
|
800dfd8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800dfdc: f383 8811 msr BASEPRI, r3
|
|
800dfe0: f3bf 8f6f isb sy
|
|
800dfe4: f3bf 8f4f dsb sy
|
|
800dfe8: 60bb str r3, [r7, #8]
|
|
}
|
|
800dfea: bf00 nop
|
|
800dfec: bf00 nop
|
|
800dfee: e7fd b.n 800dfec <xTaskPriorityDisinherit+0x54>
|
|
( pxTCB->uxMutexesHeld )--;
|
|
800dff0: 693b ldr r3, [r7, #16]
|
|
800dff2: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800dff4: 1e5a subs r2, r3, #1
|
|
800dff6: 693b ldr r3, [r7, #16]
|
|
800dff8: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Has the holder of the mutex inherited the priority of another
|
|
task? */
|
|
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
|
|
800dffa: 693b ldr r3, [r7, #16]
|
|
800dffc: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800dffe: 693b ldr r3, [r7, #16]
|
|
800e000: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800e002: 429a cmp r2, r3
|
|
800e004: d02c beq.n 800e060 <xTaskPriorityDisinherit+0xc8>
|
|
{
|
|
/* Only disinherit if no other mutexes are held. */
|
|
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
|
|
800e006: 693b ldr r3, [r7, #16]
|
|
800e008: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800e00a: 2b00 cmp r3, #0
|
|
800e00c: d128 bne.n 800e060 <xTaskPriorityDisinherit+0xc8>
|
|
/* A task can only have an inherited priority if it holds
|
|
the mutex. If the mutex is held by a task then it cannot be
|
|
given from an interrupt, and if a mutex is given by the
|
|
holding task then it must be the running state task. Remove
|
|
the holding task from the ready/delayed list. */
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800e00e: 693b ldr r3, [r7, #16]
|
|
800e010: 3304 adds r3, #4
|
|
800e012: 4618 mov r0, r3
|
|
800e014: f7fe fa2e bl 800c474 <uxListRemove>
|
|
}
|
|
|
|
/* Disinherit the priority before adding the task into the
|
|
new ready list. */
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
|
|
pxTCB->uxPriority = pxTCB->uxBasePriority;
|
|
800e018: 693b ldr r3, [r7, #16]
|
|
800e01a: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
800e01c: 693b ldr r3, [r7, #16]
|
|
800e01e: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Reset the event list item value. It cannot be in use for
|
|
any other purpose if this task is running, and it must be
|
|
running to give back the mutex. */
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800e020: 693b ldr r3, [r7, #16]
|
|
800e022: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800e024: f1c3 0238 rsb r2, r3, #56 @ 0x38
|
|
800e028: 693b ldr r3, [r7, #16]
|
|
800e02a: 619a str r2, [r3, #24]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800e02c: 693b ldr r3, [r7, #16]
|
|
800e02e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800e030: 4b0f ldr r3, [pc, #60] @ (800e070 <xTaskPriorityDisinherit+0xd8>)
|
|
800e032: 681b ldr r3, [r3, #0]
|
|
800e034: 429a cmp r2, r3
|
|
800e036: d903 bls.n 800e040 <xTaskPriorityDisinherit+0xa8>
|
|
800e038: 693b ldr r3, [r7, #16]
|
|
800e03a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800e03c: 4a0c ldr r2, [pc, #48] @ (800e070 <xTaskPriorityDisinherit+0xd8>)
|
|
800e03e: 6013 str r3, [r2, #0]
|
|
800e040: 693b ldr r3, [r7, #16]
|
|
800e042: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800e044: 4613 mov r3, r2
|
|
800e046: 009b lsls r3, r3, #2
|
|
800e048: 4413 add r3, r2
|
|
800e04a: 009b lsls r3, r3, #2
|
|
800e04c: 4a09 ldr r2, [pc, #36] @ (800e074 <xTaskPriorityDisinherit+0xdc>)
|
|
800e04e: 441a add r2, r3
|
|
800e050: 693b ldr r3, [r7, #16]
|
|
800e052: 3304 adds r3, #4
|
|
800e054: 4619 mov r1, r3
|
|
800e056: 4610 mov r0, r2
|
|
800e058: f7fe f9af bl 800c3ba <vListInsertEnd>
|
|
in an order different to that in which they were taken.
|
|
If a context switch did not occur when the first mutex was
|
|
returned, even if a task was waiting on it, then a context
|
|
switch should occur when the last mutex is returned whether
|
|
a task is waiting on it or not. */
|
|
xReturn = pdTRUE;
|
|
800e05c: 2301 movs r3, #1
|
|
800e05e: 617b str r3, [r7, #20]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
800e060: 697b ldr r3, [r7, #20]
|
|
}
|
|
800e062: 4618 mov r0, r3
|
|
800e064: 3718 adds r7, #24
|
|
800e066: 46bd mov sp, r7
|
|
800e068: bd80 pop {r7, pc}
|
|
800e06a: bf00 nop
|
|
800e06c: 20002380 .word 0x20002380
|
|
800e070: 2000285c .word 0x2000285c
|
|
800e074: 20002384 .word 0x20002384
|
|
|
|
0800e078 <vTaskPriorityDisinheritAfterTimeout>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
|
|
{
|
|
800e078: b580 push {r7, lr}
|
|
800e07a: b088 sub sp, #32
|
|
800e07c: af00 add r7, sp, #0
|
|
800e07e: 6078 str r0, [r7, #4]
|
|
800e080: 6039 str r1, [r7, #0]
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
|
800e082: 687b ldr r3, [r7, #4]
|
|
800e084: 61bb str r3, [r7, #24]
|
|
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
|
|
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
|
|
800e086: 2301 movs r3, #1
|
|
800e088: 617b str r3, [r7, #20]
|
|
|
|
if( pxMutexHolder != NULL )
|
|
800e08a: 687b ldr r3, [r7, #4]
|
|
800e08c: 2b00 cmp r3, #0
|
|
800e08e: d06c beq.n 800e16a <vTaskPriorityDisinheritAfterTimeout+0xf2>
|
|
{
|
|
/* If pxMutexHolder is not NULL then the holder must hold at least
|
|
one mutex. */
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
|
800e090: 69bb ldr r3, [r7, #24]
|
|
800e092: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800e094: 2b00 cmp r3, #0
|
|
800e096: d10b bne.n 800e0b0 <vTaskPriorityDisinheritAfterTimeout+0x38>
|
|
__asm volatile
|
|
800e098: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e09c: f383 8811 msr BASEPRI, r3
|
|
800e0a0: f3bf 8f6f isb sy
|
|
800e0a4: f3bf 8f4f dsb sy
|
|
800e0a8: 60fb str r3, [r7, #12]
|
|
}
|
|
800e0aa: bf00 nop
|
|
800e0ac: bf00 nop
|
|
800e0ae: e7fd b.n 800e0ac <vTaskPriorityDisinheritAfterTimeout+0x34>
|
|
|
|
/* Determine the priority to which the priority of the task that
|
|
holds the mutex should be set. This will be the greater of the
|
|
holding task's base priority and the priority of the highest
|
|
priority task that is waiting to obtain the mutex. */
|
|
if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
|
|
800e0b0: 69bb ldr r3, [r7, #24]
|
|
800e0b2: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800e0b4: 683a ldr r2, [r7, #0]
|
|
800e0b6: 429a cmp r2, r3
|
|
800e0b8: d902 bls.n 800e0c0 <vTaskPriorityDisinheritAfterTimeout+0x48>
|
|
{
|
|
uxPriorityToUse = uxHighestPriorityWaitingTask;
|
|
800e0ba: 683b ldr r3, [r7, #0]
|
|
800e0bc: 61fb str r3, [r7, #28]
|
|
800e0be: e002 b.n 800e0c6 <vTaskPriorityDisinheritAfterTimeout+0x4e>
|
|
}
|
|
else
|
|
{
|
|
uxPriorityToUse = pxTCB->uxBasePriority;
|
|
800e0c0: 69bb ldr r3, [r7, #24]
|
|
800e0c2: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800e0c4: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
/* Does the priority need to change? */
|
|
if( pxTCB->uxPriority != uxPriorityToUse )
|
|
800e0c6: 69bb ldr r3, [r7, #24]
|
|
800e0c8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800e0ca: 69fa ldr r2, [r7, #28]
|
|
800e0cc: 429a cmp r2, r3
|
|
800e0ce: d04c beq.n 800e16a <vTaskPriorityDisinheritAfterTimeout+0xf2>
|
|
{
|
|
/* Only disinherit if no other mutexes are held. This is a
|
|
simplification in the priority inheritance implementation. If
|
|
the task that holds the mutex is also holding other mutexes then
|
|
the other mutexes may have caused the priority inheritance. */
|
|
if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
|
|
800e0d0: 69bb ldr r3, [r7, #24]
|
|
800e0d2: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800e0d4: 697a ldr r2, [r7, #20]
|
|
800e0d6: 429a cmp r2, r3
|
|
800e0d8: d147 bne.n 800e16a <vTaskPriorityDisinheritAfterTimeout+0xf2>
|
|
{
|
|
/* If a task has timed out because it already holds the
|
|
mutex it was trying to obtain then it cannot of inherited
|
|
its own priority. */
|
|
configASSERT( pxTCB != pxCurrentTCB );
|
|
800e0da: 4b26 ldr r3, [pc, #152] @ (800e174 <vTaskPriorityDisinheritAfterTimeout+0xfc>)
|
|
800e0dc: 681b ldr r3, [r3, #0]
|
|
800e0de: 69ba ldr r2, [r7, #24]
|
|
800e0e0: 429a cmp r2, r3
|
|
800e0e2: d10b bne.n 800e0fc <vTaskPriorityDisinheritAfterTimeout+0x84>
|
|
__asm volatile
|
|
800e0e4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e0e8: f383 8811 msr BASEPRI, r3
|
|
800e0ec: f3bf 8f6f isb sy
|
|
800e0f0: f3bf 8f4f dsb sy
|
|
800e0f4: 60bb str r3, [r7, #8]
|
|
}
|
|
800e0f6: bf00 nop
|
|
800e0f8: bf00 nop
|
|
800e0fa: e7fd b.n 800e0f8 <vTaskPriorityDisinheritAfterTimeout+0x80>
|
|
|
|
/* Disinherit the priority, remembering the previous
|
|
priority to facilitate determining the subject task's
|
|
state. */
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
|
|
uxPriorityUsedOnEntry = pxTCB->uxPriority;
|
|
800e0fc: 69bb ldr r3, [r7, #24]
|
|
800e0fe: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800e100: 613b str r3, [r7, #16]
|
|
pxTCB->uxPriority = uxPriorityToUse;
|
|
800e102: 69bb ldr r3, [r7, #24]
|
|
800e104: 69fa ldr r2, [r7, #28]
|
|
800e106: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Only reset the event list item value if the value is not
|
|
being used for anything else. */
|
|
if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
|
|
800e108: 69bb ldr r3, [r7, #24]
|
|
800e10a: 699b ldr r3, [r3, #24]
|
|
800e10c: 2b00 cmp r3, #0
|
|
800e10e: db04 blt.n 800e11a <vTaskPriorityDisinheritAfterTimeout+0xa2>
|
|
{
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800e110: 69fb ldr r3, [r7, #28]
|
|
800e112: f1c3 0238 rsb r2, r3, #56 @ 0x38
|
|
800e116: 69bb ldr r3, [r7, #24]
|
|
800e118: 619a str r2, [r3, #24]
|
|
then the task that holds the mutex could be in either the
|
|
Ready, Blocked or Suspended states. Only remove the task
|
|
from its current state list if it is in the Ready state as
|
|
the task's priority is going to change and there is one
|
|
Ready list per priority. */
|
|
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
|
|
800e11a: 69bb ldr r3, [r7, #24]
|
|
800e11c: 6959 ldr r1, [r3, #20]
|
|
800e11e: 693a ldr r2, [r7, #16]
|
|
800e120: 4613 mov r3, r2
|
|
800e122: 009b lsls r3, r3, #2
|
|
800e124: 4413 add r3, r2
|
|
800e126: 009b lsls r3, r3, #2
|
|
800e128: 4a13 ldr r2, [pc, #76] @ (800e178 <vTaskPriorityDisinheritAfterTimeout+0x100>)
|
|
800e12a: 4413 add r3, r2
|
|
800e12c: 4299 cmp r1, r3
|
|
800e12e: d11c bne.n 800e16a <vTaskPriorityDisinheritAfterTimeout+0xf2>
|
|
{
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800e130: 69bb ldr r3, [r7, #24]
|
|
800e132: 3304 adds r3, #4
|
|
800e134: 4618 mov r0, r3
|
|
800e136: f7fe f99d bl 800c474 <uxListRemove>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800e13a: 69bb ldr r3, [r7, #24]
|
|
800e13c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800e13e: 4b0f ldr r3, [pc, #60] @ (800e17c <vTaskPriorityDisinheritAfterTimeout+0x104>)
|
|
800e140: 681b ldr r3, [r3, #0]
|
|
800e142: 429a cmp r2, r3
|
|
800e144: d903 bls.n 800e14e <vTaskPriorityDisinheritAfterTimeout+0xd6>
|
|
800e146: 69bb ldr r3, [r7, #24]
|
|
800e148: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800e14a: 4a0c ldr r2, [pc, #48] @ (800e17c <vTaskPriorityDisinheritAfterTimeout+0x104>)
|
|
800e14c: 6013 str r3, [r2, #0]
|
|
800e14e: 69bb ldr r3, [r7, #24]
|
|
800e150: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800e152: 4613 mov r3, r2
|
|
800e154: 009b lsls r3, r3, #2
|
|
800e156: 4413 add r3, r2
|
|
800e158: 009b lsls r3, r3, #2
|
|
800e15a: 4a07 ldr r2, [pc, #28] @ (800e178 <vTaskPriorityDisinheritAfterTimeout+0x100>)
|
|
800e15c: 441a add r2, r3
|
|
800e15e: 69bb ldr r3, [r7, #24]
|
|
800e160: 3304 adds r3, #4
|
|
800e162: 4619 mov r1, r3
|
|
800e164: 4610 mov r0, r2
|
|
800e166: f7fe f928 bl 800c3ba <vListInsertEnd>
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800e16a: bf00 nop
|
|
800e16c: 3720 adds r7, #32
|
|
800e16e: 46bd mov sp, r7
|
|
800e170: bd80 pop {r7, pc}
|
|
800e172: bf00 nop
|
|
800e174: 20002380 .word 0x20002380
|
|
800e178: 20002384 .word 0x20002384
|
|
800e17c: 2000285c .word 0x2000285c
|
|
|
|
0800e180 <pvTaskIncrementMutexHeldCount>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
|
|
{
|
|
800e180: b480 push {r7}
|
|
800e182: af00 add r7, sp, #0
|
|
/* If xSemaphoreCreateMutex() is called before any tasks have been created
|
|
then pxCurrentTCB will be NULL. */
|
|
if( pxCurrentTCB != NULL )
|
|
800e184: 4b07 ldr r3, [pc, #28] @ (800e1a4 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
800e186: 681b ldr r3, [r3, #0]
|
|
800e188: 2b00 cmp r3, #0
|
|
800e18a: d004 beq.n 800e196 <pvTaskIncrementMutexHeldCount+0x16>
|
|
{
|
|
( pxCurrentTCB->uxMutexesHeld )++;
|
|
800e18c: 4b05 ldr r3, [pc, #20] @ (800e1a4 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
800e18e: 681b ldr r3, [r3, #0]
|
|
800e190: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
800e192: 3201 adds r2, #1
|
|
800e194: 651a str r2, [r3, #80] @ 0x50
|
|
}
|
|
|
|
return pxCurrentTCB;
|
|
800e196: 4b03 ldr r3, [pc, #12] @ (800e1a4 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
800e198: 681b ldr r3, [r3, #0]
|
|
}
|
|
800e19a: 4618 mov r0, r3
|
|
800e19c: 46bd mov sp, r7
|
|
800e19e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800e1a2: 4770 bx lr
|
|
800e1a4: 20002380 .word 0x20002380
|
|
|
|
0800e1a8 <ulTaskNotifyTake>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configUSE_TASK_NOTIFICATIONS == 1 )
|
|
|
|
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
|
|
{
|
|
800e1a8: b580 push {r7, lr}
|
|
800e1aa: b084 sub sp, #16
|
|
800e1ac: af00 add r7, sp, #0
|
|
800e1ae: 6078 str r0, [r7, #4]
|
|
800e1b0: 6039 str r1, [r7, #0]
|
|
uint32_t ulReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
800e1b2: f000 fdd9 bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
/* Only block if the notification count is not already non-zero. */
|
|
if( pxCurrentTCB->ulNotifiedValue == 0UL )
|
|
800e1b6: 4b1e ldr r3, [pc, #120] @ (800e230 <ulTaskNotifyTake+0x88>)
|
|
800e1b8: 681b ldr r3, [r3, #0]
|
|
800e1ba: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800e1bc: 2b00 cmp r3, #0
|
|
800e1be: d113 bne.n 800e1e8 <ulTaskNotifyTake+0x40>
|
|
{
|
|
/* Mark this task as waiting for a notification. */
|
|
pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
|
|
800e1c0: 4b1b ldr r3, [pc, #108] @ (800e230 <ulTaskNotifyTake+0x88>)
|
|
800e1c2: 681b ldr r3, [r3, #0]
|
|
800e1c4: 2201 movs r2, #1
|
|
800e1c6: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
if( xTicksToWait > ( TickType_t ) 0 )
|
|
800e1ca: 683b ldr r3, [r7, #0]
|
|
800e1cc: 2b00 cmp r3, #0
|
|
800e1ce: d00b beq.n 800e1e8 <ulTaskNotifyTake+0x40>
|
|
{
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
|
800e1d0: 2101 movs r1, #1
|
|
800e1d2: 6838 ldr r0, [r7, #0]
|
|
800e1d4: f000 f8ea bl 800e3ac <prvAddCurrentTaskToDelayedList>
|
|
|
|
/* All ports are written to allow a yield in a critical
|
|
section (some will yield immediately, others wait until the
|
|
critical section exits) - but it is not something that
|
|
application code should ever do. */
|
|
portYIELD_WITHIN_API();
|
|
800e1d8: 4b16 ldr r3, [pc, #88] @ (800e234 <ulTaskNotifyTake+0x8c>)
|
|
800e1da: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800e1de: 601a str r2, [r3, #0]
|
|
800e1e0: f3bf 8f4f dsb sy
|
|
800e1e4: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800e1e8: f000 fdf0 bl 800edcc <vPortExitCritical>
|
|
|
|
taskENTER_CRITICAL();
|
|
800e1ec: f000 fdbc bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
traceTASK_NOTIFY_TAKE();
|
|
ulReturn = pxCurrentTCB->ulNotifiedValue;
|
|
800e1f0: 4b0f ldr r3, [pc, #60] @ (800e230 <ulTaskNotifyTake+0x88>)
|
|
800e1f2: 681b ldr r3, [r3, #0]
|
|
800e1f4: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800e1f6: 60fb str r3, [r7, #12]
|
|
|
|
if( ulReturn != 0UL )
|
|
800e1f8: 68fb ldr r3, [r7, #12]
|
|
800e1fa: 2b00 cmp r3, #0
|
|
800e1fc: d00c beq.n 800e218 <ulTaskNotifyTake+0x70>
|
|
{
|
|
if( xClearCountOnExit != pdFALSE )
|
|
800e1fe: 687b ldr r3, [r7, #4]
|
|
800e200: 2b00 cmp r3, #0
|
|
800e202: d004 beq.n 800e20e <ulTaskNotifyTake+0x66>
|
|
{
|
|
pxCurrentTCB->ulNotifiedValue = 0UL;
|
|
800e204: 4b0a ldr r3, [pc, #40] @ (800e230 <ulTaskNotifyTake+0x88>)
|
|
800e206: 681b ldr r3, [r3, #0]
|
|
800e208: 2200 movs r2, #0
|
|
800e20a: 655a str r2, [r3, #84] @ 0x54
|
|
800e20c: e004 b.n 800e218 <ulTaskNotifyTake+0x70>
|
|
}
|
|
else
|
|
{
|
|
pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
|
|
800e20e: 4b08 ldr r3, [pc, #32] @ (800e230 <ulTaskNotifyTake+0x88>)
|
|
800e210: 681b ldr r3, [r3, #0]
|
|
800e212: 68fa ldr r2, [r7, #12]
|
|
800e214: 3a01 subs r2, #1
|
|
800e216: 655a str r2, [r3, #84] @ 0x54
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
|
|
800e218: 4b05 ldr r3, [pc, #20] @ (800e230 <ulTaskNotifyTake+0x88>)
|
|
800e21a: 681b ldr r3, [r3, #0]
|
|
800e21c: 2200 movs r2, #0
|
|
800e21e: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800e222: f000 fdd3 bl 800edcc <vPortExitCritical>
|
|
|
|
return ulReturn;
|
|
800e226: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800e228: 4618 mov r0, r3
|
|
800e22a: 3710 adds r7, #16
|
|
800e22c: 46bd mov sp, r7
|
|
800e22e: bd80 pop {r7, pc}
|
|
800e230: 20002380 .word 0x20002380
|
|
800e234: e000ed04 .word 0xe000ed04
|
|
|
|
0800e238 <xTaskGenericNotify>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configUSE_TASK_NOTIFICATIONS == 1 )
|
|
|
|
BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
|
|
{
|
|
800e238: b580 push {r7, lr}
|
|
800e23a: b08a sub sp, #40 @ 0x28
|
|
800e23c: af00 add r7, sp, #0
|
|
800e23e: 60f8 str r0, [r7, #12]
|
|
800e240: 60b9 str r1, [r7, #8]
|
|
800e242: 603b str r3, [r7, #0]
|
|
800e244: 4613 mov r3, r2
|
|
800e246: 71fb strb r3, [r7, #7]
|
|
TCB_t * pxTCB;
|
|
BaseType_t xReturn = pdPASS;
|
|
800e248: 2301 movs r3, #1
|
|
800e24a: 627b str r3, [r7, #36] @ 0x24
|
|
uint8_t ucOriginalNotifyState;
|
|
|
|
configASSERT( xTaskToNotify );
|
|
800e24c: 68fb ldr r3, [r7, #12]
|
|
800e24e: 2b00 cmp r3, #0
|
|
800e250: d10b bne.n 800e26a <xTaskGenericNotify+0x32>
|
|
__asm volatile
|
|
800e252: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e256: f383 8811 msr BASEPRI, r3
|
|
800e25a: f3bf 8f6f isb sy
|
|
800e25e: f3bf 8f4f dsb sy
|
|
800e262: 61bb str r3, [r7, #24]
|
|
}
|
|
800e264: bf00 nop
|
|
800e266: bf00 nop
|
|
800e268: e7fd b.n 800e266 <xTaskGenericNotify+0x2e>
|
|
pxTCB = xTaskToNotify;
|
|
800e26a: 68fb ldr r3, [r7, #12]
|
|
800e26c: 623b str r3, [r7, #32]
|
|
|
|
taskENTER_CRITICAL();
|
|
800e26e: f000 fd7b bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
if( pulPreviousNotificationValue != NULL )
|
|
800e272: 683b ldr r3, [r7, #0]
|
|
800e274: 2b00 cmp r3, #0
|
|
800e276: d003 beq.n 800e280 <xTaskGenericNotify+0x48>
|
|
{
|
|
*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
|
|
800e278: 6a3b ldr r3, [r7, #32]
|
|
800e27a: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
800e27c: 683b ldr r3, [r7, #0]
|
|
800e27e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
ucOriginalNotifyState = pxTCB->ucNotifyState;
|
|
800e280: 6a3b ldr r3, [r7, #32]
|
|
800e282: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
|
|
800e286: 77fb strb r3, [r7, #31]
|
|
|
|
pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
|
|
800e288: 6a3b ldr r3, [r7, #32]
|
|
800e28a: 2202 movs r2, #2
|
|
800e28c: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
switch( eAction )
|
|
800e290: 79fb ldrb r3, [r7, #7]
|
|
800e292: 2b04 cmp r3, #4
|
|
800e294: d827 bhi.n 800e2e6 <xTaskGenericNotify+0xae>
|
|
800e296: a201 add r2, pc, #4 @ (adr r2, 800e29c <xTaskGenericNotify+0x64>)
|
|
800e298: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800e29c: 0800e309 .word 0x0800e309
|
|
800e2a0: 0800e2b1 .word 0x0800e2b1
|
|
800e2a4: 0800e2bf .word 0x0800e2bf
|
|
800e2a8: 0800e2cb .word 0x0800e2cb
|
|
800e2ac: 0800e2d3 .word 0x0800e2d3
|
|
{
|
|
case eSetBits :
|
|
pxTCB->ulNotifiedValue |= ulValue;
|
|
800e2b0: 6a3b ldr r3, [r7, #32]
|
|
800e2b2: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
800e2b4: 68bb ldr r3, [r7, #8]
|
|
800e2b6: 431a orrs r2, r3
|
|
800e2b8: 6a3b ldr r3, [r7, #32]
|
|
800e2ba: 655a str r2, [r3, #84] @ 0x54
|
|
break;
|
|
800e2bc: e027 b.n 800e30e <xTaskGenericNotify+0xd6>
|
|
|
|
case eIncrement :
|
|
( pxTCB->ulNotifiedValue )++;
|
|
800e2be: 6a3b ldr r3, [r7, #32]
|
|
800e2c0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800e2c2: 1c5a adds r2, r3, #1
|
|
800e2c4: 6a3b ldr r3, [r7, #32]
|
|
800e2c6: 655a str r2, [r3, #84] @ 0x54
|
|
break;
|
|
800e2c8: e021 b.n 800e30e <xTaskGenericNotify+0xd6>
|
|
|
|
case eSetValueWithOverwrite :
|
|
pxTCB->ulNotifiedValue = ulValue;
|
|
800e2ca: 6a3b ldr r3, [r7, #32]
|
|
800e2cc: 68ba ldr r2, [r7, #8]
|
|
800e2ce: 655a str r2, [r3, #84] @ 0x54
|
|
break;
|
|
800e2d0: e01d b.n 800e30e <xTaskGenericNotify+0xd6>
|
|
|
|
case eSetValueWithoutOverwrite :
|
|
if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
|
|
800e2d2: 7ffb ldrb r3, [r7, #31]
|
|
800e2d4: 2b02 cmp r3, #2
|
|
800e2d6: d003 beq.n 800e2e0 <xTaskGenericNotify+0xa8>
|
|
{
|
|
pxTCB->ulNotifiedValue = ulValue;
|
|
800e2d8: 6a3b ldr r3, [r7, #32]
|
|
800e2da: 68ba ldr r2, [r7, #8]
|
|
800e2dc: 655a str r2, [r3, #84] @ 0x54
|
|
else
|
|
{
|
|
/* The value could not be written to the task. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
break;
|
|
800e2de: e016 b.n 800e30e <xTaskGenericNotify+0xd6>
|
|
xReturn = pdFAIL;
|
|
800e2e0: 2300 movs r3, #0
|
|
800e2e2: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
800e2e4: e013 b.n 800e30e <xTaskGenericNotify+0xd6>
|
|
|
|
default:
|
|
/* Should not get here if all enums are handled.
|
|
Artificially force an assert by testing a value the
|
|
compiler can't assume is const. */
|
|
configASSERT( pxTCB->ulNotifiedValue == ~0UL );
|
|
800e2e6: 6a3b ldr r3, [r7, #32]
|
|
800e2e8: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800e2ea: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800e2ee: d00d beq.n 800e30c <xTaskGenericNotify+0xd4>
|
|
__asm volatile
|
|
800e2f0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e2f4: f383 8811 msr BASEPRI, r3
|
|
800e2f8: f3bf 8f6f isb sy
|
|
800e2fc: f3bf 8f4f dsb sy
|
|
800e300: 617b str r3, [r7, #20]
|
|
}
|
|
800e302: bf00 nop
|
|
800e304: bf00 nop
|
|
800e306: e7fd b.n 800e304 <xTaskGenericNotify+0xcc>
|
|
break;
|
|
800e308: bf00 nop
|
|
800e30a: e000 b.n 800e30e <xTaskGenericNotify+0xd6>
|
|
|
|
break;
|
|
800e30c: bf00 nop
|
|
|
|
traceTASK_NOTIFY();
|
|
|
|
/* If the task is in the blocked state specifically to wait for a
|
|
notification then unblock it now. */
|
|
if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
|
|
800e30e: 7ffb ldrb r3, [r7, #31]
|
|
800e310: 2b01 cmp r3, #1
|
|
800e312: d13b bne.n 800e38c <xTaskGenericNotify+0x154>
|
|
{
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800e314: 6a3b ldr r3, [r7, #32]
|
|
800e316: 3304 adds r3, #4
|
|
800e318: 4618 mov r0, r3
|
|
800e31a: f7fe f8ab bl 800c474 <uxListRemove>
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800e31e: 6a3b ldr r3, [r7, #32]
|
|
800e320: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800e322: 4b1e ldr r3, [pc, #120] @ (800e39c <xTaskGenericNotify+0x164>)
|
|
800e324: 681b ldr r3, [r3, #0]
|
|
800e326: 429a cmp r2, r3
|
|
800e328: d903 bls.n 800e332 <xTaskGenericNotify+0xfa>
|
|
800e32a: 6a3b ldr r3, [r7, #32]
|
|
800e32c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800e32e: 4a1b ldr r2, [pc, #108] @ (800e39c <xTaskGenericNotify+0x164>)
|
|
800e330: 6013 str r3, [r2, #0]
|
|
800e332: 6a3b ldr r3, [r7, #32]
|
|
800e334: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800e336: 4613 mov r3, r2
|
|
800e338: 009b lsls r3, r3, #2
|
|
800e33a: 4413 add r3, r2
|
|
800e33c: 009b lsls r3, r3, #2
|
|
800e33e: 4a18 ldr r2, [pc, #96] @ (800e3a0 <xTaskGenericNotify+0x168>)
|
|
800e340: 441a add r2, r3
|
|
800e342: 6a3b ldr r3, [r7, #32]
|
|
800e344: 3304 adds r3, #4
|
|
800e346: 4619 mov r1, r3
|
|
800e348: 4610 mov r0, r2
|
|
800e34a: f7fe f836 bl 800c3ba <vListInsertEnd>
|
|
|
|
/* The task should not have been on an event list. */
|
|
configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
|
|
800e34e: 6a3b ldr r3, [r7, #32]
|
|
800e350: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800e352: 2b00 cmp r3, #0
|
|
800e354: d00b beq.n 800e36e <xTaskGenericNotify+0x136>
|
|
__asm volatile
|
|
800e356: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e35a: f383 8811 msr BASEPRI, r3
|
|
800e35e: f3bf 8f6f isb sy
|
|
800e362: f3bf 8f4f dsb sy
|
|
800e366: 613b str r3, [r7, #16]
|
|
}
|
|
800e368: bf00 nop
|
|
800e36a: bf00 nop
|
|
800e36c: e7fd b.n 800e36a <xTaskGenericNotify+0x132>
|
|
earliest possible time. */
|
|
prvResetNextTaskUnblockTime();
|
|
}
|
|
#endif
|
|
|
|
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
800e36e: 6a3b ldr r3, [r7, #32]
|
|
800e370: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800e372: 4b0c ldr r3, [pc, #48] @ (800e3a4 <xTaskGenericNotify+0x16c>)
|
|
800e374: 681b ldr r3, [r3, #0]
|
|
800e376: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800e378: 429a cmp r2, r3
|
|
800e37a: d907 bls.n 800e38c <xTaskGenericNotify+0x154>
|
|
{
|
|
/* The notified task has a priority above the currently
|
|
executing task so a yield is required. */
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
800e37c: 4b0a ldr r3, [pc, #40] @ (800e3a8 <xTaskGenericNotify+0x170>)
|
|
800e37e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800e382: 601a str r2, [r3, #0]
|
|
800e384: f3bf 8f4f dsb sy
|
|
800e388: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800e38c: f000 fd1e bl 800edcc <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800e390: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
800e392: 4618 mov r0, r3
|
|
800e394: 3728 adds r7, #40 @ 0x28
|
|
800e396: 46bd mov sp, r7
|
|
800e398: bd80 pop {r7, pc}
|
|
800e39a: bf00 nop
|
|
800e39c: 2000285c .word 0x2000285c
|
|
800e3a0: 20002384 .word 0x20002384
|
|
800e3a4: 20002380 .word 0x20002380
|
|
800e3a8: e000ed04 .word 0xe000ed04
|
|
|
|
0800e3ac <prvAddCurrentTaskToDelayedList>:
|
|
|
|
#endif
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
|
|
{
|
|
800e3ac: b580 push {r7, lr}
|
|
800e3ae: b084 sub sp, #16
|
|
800e3b0: af00 add r7, sp, #0
|
|
800e3b2: 6078 str r0, [r7, #4]
|
|
800e3b4: 6039 str r1, [r7, #0]
|
|
TickType_t xTimeToWake;
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
800e3b6: 4b21 ldr r3, [pc, #132] @ (800e43c <prvAddCurrentTaskToDelayedList+0x90>)
|
|
800e3b8: 681b ldr r3, [r3, #0]
|
|
800e3ba: 60fb str r3, [r7, #12]
|
|
}
|
|
#endif
|
|
|
|
/* Remove the task from the ready list before adding it to the blocked list
|
|
as the same list item is used for both lists. */
|
|
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800e3bc: 4b20 ldr r3, [pc, #128] @ (800e440 <prvAddCurrentTaskToDelayedList+0x94>)
|
|
800e3be: 681b ldr r3, [r3, #0]
|
|
800e3c0: 3304 adds r3, #4
|
|
800e3c2: 4618 mov r0, r3
|
|
800e3c4: f7fe f856 bl 800c474 <uxListRemove>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
|
|
800e3c8: 687b ldr r3, [r7, #4]
|
|
800e3ca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800e3ce: d10a bne.n 800e3e6 <prvAddCurrentTaskToDelayedList+0x3a>
|
|
800e3d0: 683b ldr r3, [r7, #0]
|
|
800e3d2: 2b00 cmp r3, #0
|
|
800e3d4: d007 beq.n 800e3e6 <prvAddCurrentTaskToDelayedList+0x3a>
|
|
{
|
|
/* Add the task to the suspended task list instead of a delayed task
|
|
list to ensure it is not woken by a timing event. It will block
|
|
indefinitely. */
|
|
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800e3d6: 4b1a ldr r3, [pc, #104] @ (800e440 <prvAddCurrentTaskToDelayedList+0x94>)
|
|
800e3d8: 681b ldr r3, [r3, #0]
|
|
800e3da: 3304 adds r3, #4
|
|
800e3dc: 4619 mov r1, r3
|
|
800e3de: 4819 ldr r0, [pc, #100] @ (800e444 <prvAddCurrentTaskToDelayedList+0x98>)
|
|
800e3e0: f7fd ffeb bl 800c3ba <vListInsertEnd>
|
|
|
|
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
|
|
( void ) xCanBlockIndefinitely;
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
}
|
|
800e3e4: e026 b.n 800e434 <prvAddCurrentTaskToDelayedList+0x88>
|
|
xTimeToWake = xConstTickCount + xTicksToWait;
|
|
800e3e6: 68fa ldr r2, [r7, #12]
|
|
800e3e8: 687b ldr r3, [r7, #4]
|
|
800e3ea: 4413 add r3, r2
|
|
800e3ec: 60bb str r3, [r7, #8]
|
|
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
|
|
800e3ee: 4b14 ldr r3, [pc, #80] @ (800e440 <prvAddCurrentTaskToDelayedList+0x94>)
|
|
800e3f0: 681b ldr r3, [r3, #0]
|
|
800e3f2: 68ba ldr r2, [r7, #8]
|
|
800e3f4: 605a str r2, [r3, #4]
|
|
if( xTimeToWake < xConstTickCount )
|
|
800e3f6: 68ba ldr r2, [r7, #8]
|
|
800e3f8: 68fb ldr r3, [r7, #12]
|
|
800e3fa: 429a cmp r2, r3
|
|
800e3fc: d209 bcs.n 800e412 <prvAddCurrentTaskToDelayedList+0x66>
|
|
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800e3fe: 4b12 ldr r3, [pc, #72] @ (800e448 <prvAddCurrentTaskToDelayedList+0x9c>)
|
|
800e400: 681a ldr r2, [r3, #0]
|
|
800e402: 4b0f ldr r3, [pc, #60] @ (800e440 <prvAddCurrentTaskToDelayedList+0x94>)
|
|
800e404: 681b ldr r3, [r3, #0]
|
|
800e406: 3304 adds r3, #4
|
|
800e408: 4619 mov r1, r3
|
|
800e40a: 4610 mov r0, r2
|
|
800e40c: f7fd fff9 bl 800c402 <vListInsert>
|
|
}
|
|
800e410: e010 b.n 800e434 <prvAddCurrentTaskToDelayedList+0x88>
|
|
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800e412: 4b0e ldr r3, [pc, #56] @ (800e44c <prvAddCurrentTaskToDelayedList+0xa0>)
|
|
800e414: 681a ldr r2, [r3, #0]
|
|
800e416: 4b0a ldr r3, [pc, #40] @ (800e440 <prvAddCurrentTaskToDelayedList+0x94>)
|
|
800e418: 681b ldr r3, [r3, #0]
|
|
800e41a: 3304 adds r3, #4
|
|
800e41c: 4619 mov r1, r3
|
|
800e41e: 4610 mov r0, r2
|
|
800e420: f7fd ffef bl 800c402 <vListInsert>
|
|
if( xTimeToWake < xNextTaskUnblockTime )
|
|
800e424: 4b0a ldr r3, [pc, #40] @ (800e450 <prvAddCurrentTaskToDelayedList+0xa4>)
|
|
800e426: 681b ldr r3, [r3, #0]
|
|
800e428: 68ba ldr r2, [r7, #8]
|
|
800e42a: 429a cmp r2, r3
|
|
800e42c: d202 bcs.n 800e434 <prvAddCurrentTaskToDelayedList+0x88>
|
|
xNextTaskUnblockTime = xTimeToWake;
|
|
800e42e: 4a08 ldr r2, [pc, #32] @ (800e450 <prvAddCurrentTaskToDelayedList+0xa4>)
|
|
800e430: 68bb ldr r3, [r7, #8]
|
|
800e432: 6013 str r3, [r2, #0]
|
|
}
|
|
800e434: bf00 nop
|
|
800e436: 3710 adds r7, #16
|
|
800e438: 46bd mov sp, r7
|
|
800e43a: bd80 pop {r7, pc}
|
|
800e43c: 20002858 .word 0x20002858
|
|
800e440: 20002380 .word 0x20002380
|
|
800e444: 20002840 .word 0x20002840
|
|
800e448: 20002810 .word 0x20002810
|
|
800e44c: 2000280c .word 0x2000280c
|
|
800e450: 20002874 .word 0x20002874
|
|
|
|
0800e454 <xTimerCreateTimerTask>:
|
|
TimerCallbackFunction_t pxCallbackFunction,
|
|
Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTimerCreateTimerTask( void )
|
|
{
|
|
800e454: b580 push {r7, lr}
|
|
800e456: b08a sub sp, #40 @ 0x28
|
|
800e458: af04 add r7, sp, #16
|
|
BaseType_t xReturn = pdFAIL;
|
|
800e45a: 2300 movs r3, #0
|
|
800e45c: 617b str r3, [r7, #20]
|
|
|
|
/* This function is called when the scheduler is started if
|
|
configUSE_TIMERS is set to 1. Check that the infrastructure used by the
|
|
timer service task has been created/initialised. If timers have already
|
|
been created then the initialisation will already have been performed. */
|
|
prvCheckForValidListAndQueue();
|
|
800e45e: f000 fb13 bl 800ea88 <prvCheckForValidListAndQueue>
|
|
|
|
if( xTimerQueue != NULL )
|
|
800e462: 4b1d ldr r3, [pc, #116] @ (800e4d8 <xTimerCreateTimerTask+0x84>)
|
|
800e464: 681b ldr r3, [r3, #0]
|
|
800e466: 2b00 cmp r3, #0
|
|
800e468: d021 beq.n 800e4ae <xTimerCreateTimerTask+0x5a>
|
|
{
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
StaticTask_t *pxTimerTaskTCBBuffer = NULL;
|
|
800e46a: 2300 movs r3, #0
|
|
800e46c: 60fb str r3, [r7, #12]
|
|
StackType_t *pxTimerTaskStackBuffer = NULL;
|
|
800e46e: 2300 movs r3, #0
|
|
800e470: 60bb str r3, [r7, #8]
|
|
uint32_t ulTimerTaskStackSize;
|
|
|
|
vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
|
|
800e472: 1d3a adds r2, r7, #4
|
|
800e474: f107 0108 add.w r1, r7, #8
|
|
800e478: f107 030c add.w r3, r7, #12
|
|
800e47c: 4618 mov r0, r3
|
|
800e47e: f7fd ff55 bl 800c32c <vApplicationGetTimerTaskMemory>
|
|
xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
|
|
800e482: 6879 ldr r1, [r7, #4]
|
|
800e484: 68bb ldr r3, [r7, #8]
|
|
800e486: 68fa ldr r2, [r7, #12]
|
|
800e488: 9202 str r2, [sp, #8]
|
|
800e48a: 9301 str r3, [sp, #4]
|
|
800e48c: 2302 movs r3, #2
|
|
800e48e: 9300 str r3, [sp, #0]
|
|
800e490: 2300 movs r3, #0
|
|
800e492: 460a mov r2, r1
|
|
800e494: 4911 ldr r1, [pc, #68] @ (800e4dc <xTimerCreateTimerTask+0x88>)
|
|
800e496: 4812 ldr r0, [pc, #72] @ (800e4e0 <xTimerCreateTimerTask+0x8c>)
|
|
800e498: f7fe ff04 bl 800d2a4 <xTaskCreateStatic>
|
|
800e49c: 4603 mov r3, r0
|
|
800e49e: 4a11 ldr r2, [pc, #68] @ (800e4e4 <xTimerCreateTimerTask+0x90>)
|
|
800e4a0: 6013 str r3, [r2, #0]
|
|
NULL,
|
|
( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
|
|
pxTimerTaskStackBuffer,
|
|
pxTimerTaskTCBBuffer );
|
|
|
|
if( xTimerTaskHandle != NULL )
|
|
800e4a2: 4b10 ldr r3, [pc, #64] @ (800e4e4 <xTimerCreateTimerTask+0x90>)
|
|
800e4a4: 681b ldr r3, [r3, #0]
|
|
800e4a6: 2b00 cmp r3, #0
|
|
800e4a8: d001 beq.n 800e4ae <xTimerCreateTimerTask+0x5a>
|
|
{
|
|
xReturn = pdPASS;
|
|
800e4aa: 2301 movs r3, #1
|
|
800e4ac: 617b str r3, [r7, #20]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
configASSERT( xReturn );
|
|
800e4ae: 697b ldr r3, [r7, #20]
|
|
800e4b0: 2b00 cmp r3, #0
|
|
800e4b2: d10b bne.n 800e4cc <xTimerCreateTimerTask+0x78>
|
|
__asm volatile
|
|
800e4b4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e4b8: f383 8811 msr BASEPRI, r3
|
|
800e4bc: f3bf 8f6f isb sy
|
|
800e4c0: f3bf 8f4f dsb sy
|
|
800e4c4: 613b str r3, [r7, #16]
|
|
}
|
|
800e4c6: bf00 nop
|
|
800e4c8: bf00 nop
|
|
800e4ca: e7fd b.n 800e4c8 <xTimerCreateTimerTask+0x74>
|
|
return xReturn;
|
|
800e4cc: 697b ldr r3, [r7, #20]
|
|
}
|
|
800e4ce: 4618 mov r0, r3
|
|
800e4d0: 3718 adds r7, #24
|
|
800e4d2: 46bd mov sp, r7
|
|
800e4d4: bd80 pop {r7, pc}
|
|
800e4d6: bf00 nop
|
|
800e4d8: 200028b0 .word 0x200028b0
|
|
800e4dc: 08014734 .word 0x08014734
|
|
800e4e0: 0800e621 .word 0x0800e621
|
|
800e4e4: 200028b4 .word 0x200028b4
|
|
|
|
0800e4e8 <xTimerGenericCommand>:
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
|
|
{
|
|
800e4e8: b580 push {r7, lr}
|
|
800e4ea: b08a sub sp, #40 @ 0x28
|
|
800e4ec: af00 add r7, sp, #0
|
|
800e4ee: 60f8 str r0, [r7, #12]
|
|
800e4f0: 60b9 str r1, [r7, #8]
|
|
800e4f2: 607a str r2, [r7, #4]
|
|
800e4f4: 603b str r3, [r7, #0]
|
|
BaseType_t xReturn = pdFAIL;
|
|
800e4f6: 2300 movs r3, #0
|
|
800e4f8: 627b str r3, [r7, #36] @ 0x24
|
|
DaemonTaskMessage_t xMessage;
|
|
|
|
configASSERT( xTimer );
|
|
800e4fa: 68fb ldr r3, [r7, #12]
|
|
800e4fc: 2b00 cmp r3, #0
|
|
800e4fe: d10b bne.n 800e518 <xTimerGenericCommand+0x30>
|
|
__asm volatile
|
|
800e500: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e504: f383 8811 msr BASEPRI, r3
|
|
800e508: f3bf 8f6f isb sy
|
|
800e50c: f3bf 8f4f dsb sy
|
|
800e510: 623b str r3, [r7, #32]
|
|
}
|
|
800e512: bf00 nop
|
|
800e514: bf00 nop
|
|
800e516: e7fd b.n 800e514 <xTimerGenericCommand+0x2c>
|
|
|
|
/* Send a message to the timer service task to perform a particular action
|
|
on a particular timer definition. */
|
|
if( xTimerQueue != NULL )
|
|
800e518: 4b19 ldr r3, [pc, #100] @ (800e580 <xTimerGenericCommand+0x98>)
|
|
800e51a: 681b ldr r3, [r3, #0]
|
|
800e51c: 2b00 cmp r3, #0
|
|
800e51e: d02a beq.n 800e576 <xTimerGenericCommand+0x8e>
|
|
{
|
|
/* Send a command to the timer service task to start the xTimer timer. */
|
|
xMessage.xMessageID = xCommandID;
|
|
800e520: 68bb ldr r3, [r7, #8]
|
|
800e522: 613b str r3, [r7, #16]
|
|
xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
|
|
800e524: 687b ldr r3, [r7, #4]
|
|
800e526: 617b str r3, [r7, #20]
|
|
xMessage.u.xTimerParameters.pxTimer = xTimer;
|
|
800e528: 68fb ldr r3, [r7, #12]
|
|
800e52a: 61bb str r3, [r7, #24]
|
|
|
|
if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
|
|
800e52c: 68bb ldr r3, [r7, #8]
|
|
800e52e: 2b05 cmp r3, #5
|
|
800e530: dc18 bgt.n 800e564 <xTimerGenericCommand+0x7c>
|
|
{
|
|
if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
|
|
800e532: f7ff fcab bl 800de8c <xTaskGetSchedulerState>
|
|
800e536: 4603 mov r3, r0
|
|
800e538: 2b02 cmp r3, #2
|
|
800e53a: d109 bne.n 800e550 <xTimerGenericCommand+0x68>
|
|
{
|
|
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
|
|
800e53c: 4b10 ldr r3, [pc, #64] @ (800e580 <xTimerGenericCommand+0x98>)
|
|
800e53e: 6818 ldr r0, [r3, #0]
|
|
800e540: f107 0110 add.w r1, r7, #16
|
|
800e544: 2300 movs r3, #0
|
|
800e546: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800e548: f7fe f904 bl 800c754 <xQueueGenericSend>
|
|
800e54c: 6278 str r0, [r7, #36] @ 0x24
|
|
800e54e: e012 b.n 800e576 <xTimerGenericCommand+0x8e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
|
|
800e550: 4b0b ldr r3, [pc, #44] @ (800e580 <xTimerGenericCommand+0x98>)
|
|
800e552: 6818 ldr r0, [r3, #0]
|
|
800e554: f107 0110 add.w r1, r7, #16
|
|
800e558: 2300 movs r3, #0
|
|
800e55a: 2200 movs r2, #0
|
|
800e55c: f7fe f8fa bl 800c754 <xQueueGenericSend>
|
|
800e560: 6278 str r0, [r7, #36] @ 0x24
|
|
800e562: e008 b.n 800e576 <xTimerGenericCommand+0x8e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
|
|
800e564: 4b06 ldr r3, [pc, #24] @ (800e580 <xTimerGenericCommand+0x98>)
|
|
800e566: 6818 ldr r0, [r3, #0]
|
|
800e568: f107 0110 add.w r1, r7, #16
|
|
800e56c: 2300 movs r3, #0
|
|
800e56e: 683a ldr r2, [r7, #0]
|
|
800e570: f7fe f9f2 bl 800c958 <xQueueGenericSendFromISR>
|
|
800e574: 6278 str r0, [r7, #36] @ 0x24
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
800e576: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
800e578: 4618 mov r0, r3
|
|
800e57a: 3728 adds r7, #40 @ 0x28
|
|
800e57c: 46bd mov sp, r7
|
|
800e57e: bd80 pop {r7, pc}
|
|
800e580: 200028b0 .word 0x200028b0
|
|
|
|
0800e584 <prvProcessExpiredTimer>:
|
|
return pxTimer->pcTimerName;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
|
|
{
|
|
800e584: b580 push {r7, lr}
|
|
800e586: b088 sub sp, #32
|
|
800e588: af02 add r7, sp, #8
|
|
800e58a: 6078 str r0, [r7, #4]
|
|
800e58c: 6039 str r1, [r7, #0]
|
|
BaseType_t xResult;
|
|
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800e58e: 4b23 ldr r3, [pc, #140] @ (800e61c <prvProcessExpiredTimer+0x98>)
|
|
800e590: 681b ldr r3, [r3, #0]
|
|
800e592: 68db ldr r3, [r3, #12]
|
|
800e594: 68db ldr r3, [r3, #12]
|
|
800e596: 617b str r3, [r7, #20]
|
|
|
|
/* Remove the timer from the list of active timers. A check has already
|
|
been performed to ensure the list is not empty. */
|
|
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
|
|
800e598: 697b ldr r3, [r7, #20]
|
|
800e59a: 3304 adds r3, #4
|
|
800e59c: 4618 mov r0, r3
|
|
800e59e: f7fd ff69 bl 800c474 <uxListRemove>
|
|
traceTIMER_EXPIRED( pxTimer );
|
|
|
|
/* If the timer is an auto-reload timer then calculate the next
|
|
expiry time and re-insert the timer in the list of active timers. */
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
|
|
800e5a2: 697b ldr r3, [r7, #20]
|
|
800e5a4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e5a8: f003 0304 and.w r3, r3, #4
|
|
800e5ac: 2b00 cmp r3, #0
|
|
800e5ae: d023 beq.n 800e5f8 <prvProcessExpiredTimer+0x74>
|
|
{
|
|
/* The timer is inserted into a list using a time relative to anything
|
|
other than the current time. It will therefore be inserted into the
|
|
correct list relative to the time this task thinks it is now. */
|
|
if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
|
|
800e5b0: 697b ldr r3, [r7, #20]
|
|
800e5b2: 699a ldr r2, [r3, #24]
|
|
800e5b4: 687b ldr r3, [r7, #4]
|
|
800e5b6: 18d1 adds r1, r2, r3
|
|
800e5b8: 687b ldr r3, [r7, #4]
|
|
800e5ba: 683a ldr r2, [r7, #0]
|
|
800e5bc: 6978 ldr r0, [r7, #20]
|
|
800e5be: f000 f8d5 bl 800e76c <prvInsertTimerInActiveList>
|
|
800e5c2: 4603 mov r3, r0
|
|
800e5c4: 2b00 cmp r3, #0
|
|
800e5c6: d020 beq.n 800e60a <prvProcessExpiredTimer+0x86>
|
|
{
|
|
/* The timer expired before it was added to the active timer
|
|
list. Reload it now. */
|
|
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
|
|
800e5c8: 2300 movs r3, #0
|
|
800e5ca: 9300 str r3, [sp, #0]
|
|
800e5cc: 2300 movs r3, #0
|
|
800e5ce: 687a ldr r2, [r7, #4]
|
|
800e5d0: 2100 movs r1, #0
|
|
800e5d2: 6978 ldr r0, [r7, #20]
|
|
800e5d4: f7ff ff88 bl 800e4e8 <xTimerGenericCommand>
|
|
800e5d8: 6138 str r0, [r7, #16]
|
|
configASSERT( xResult );
|
|
800e5da: 693b ldr r3, [r7, #16]
|
|
800e5dc: 2b00 cmp r3, #0
|
|
800e5de: d114 bne.n 800e60a <prvProcessExpiredTimer+0x86>
|
|
__asm volatile
|
|
800e5e0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e5e4: f383 8811 msr BASEPRI, r3
|
|
800e5e8: f3bf 8f6f isb sy
|
|
800e5ec: f3bf 8f4f dsb sy
|
|
800e5f0: 60fb str r3, [r7, #12]
|
|
}
|
|
800e5f2: bf00 nop
|
|
800e5f4: bf00 nop
|
|
800e5f6: e7fd b.n 800e5f4 <prvProcessExpiredTimer+0x70>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
|
|
800e5f8: 697b ldr r3, [r7, #20]
|
|
800e5fa: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e5fe: f023 0301 bic.w r3, r3, #1
|
|
800e602: b2da uxtb r2, r3
|
|
800e604: 697b ldr r3, [r7, #20]
|
|
800e606: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Call the timer callback. */
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
|
800e60a: 697b ldr r3, [r7, #20]
|
|
800e60c: 6a1b ldr r3, [r3, #32]
|
|
800e60e: 6978 ldr r0, [r7, #20]
|
|
800e610: 4798 blx r3
|
|
}
|
|
800e612: bf00 nop
|
|
800e614: 3718 adds r7, #24
|
|
800e616: 46bd mov sp, r7
|
|
800e618: bd80 pop {r7, pc}
|
|
800e61a: bf00 nop
|
|
800e61c: 200028a8 .word 0x200028a8
|
|
|
|
0800e620 <prvTimerTask>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static portTASK_FUNCTION( prvTimerTask, pvParameters )
|
|
{
|
|
800e620: b580 push {r7, lr}
|
|
800e622: b084 sub sp, #16
|
|
800e624: af00 add r7, sp, #0
|
|
800e626: 6078 str r0, [r7, #4]
|
|
|
|
for( ;; )
|
|
{
|
|
/* Query the timers list to see if it contains any timers, and if so,
|
|
obtain the time at which the next timer will expire. */
|
|
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
|
|
800e628: f107 0308 add.w r3, r7, #8
|
|
800e62c: 4618 mov r0, r3
|
|
800e62e: f000 f859 bl 800e6e4 <prvGetNextExpireTime>
|
|
800e632: 60f8 str r0, [r7, #12]
|
|
|
|
/* If a timer has expired, process it. Otherwise, block this task
|
|
until either a timer does expire, or a command is received. */
|
|
prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
|
|
800e634: 68bb ldr r3, [r7, #8]
|
|
800e636: 4619 mov r1, r3
|
|
800e638: 68f8 ldr r0, [r7, #12]
|
|
800e63a: f000 f805 bl 800e648 <prvProcessTimerOrBlockTask>
|
|
|
|
/* Empty the command queue. */
|
|
prvProcessReceivedCommands();
|
|
800e63e: f000 f8d7 bl 800e7f0 <prvProcessReceivedCommands>
|
|
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
|
|
800e642: bf00 nop
|
|
800e644: e7f0 b.n 800e628 <prvTimerTask+0x8>
|
|
...
|
|
|
|
0800e648 <prvProcessTimerOrBlockTask>:
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
|
|
{
|
|
800e648: b580 push {r7, lr}
|
|
800e64a: b084 sub sp, #16
|
|
800e64c: af00 add r7, sp, #0
|
|
800e64e: 6078 str r0, [r7, #4]
|
|
800e650: 6039 str r1, [r7, #0]
|
|
TickType_t xTimeNow;
|
|
BaseType_t xTimerListsWereSwitched;
|
|
|
|
vTaskSuspendAll();
|
|
800e652: f7ff f835 bl 800d6c0 <vTaskSuspendAll>
|
|
/* Obtain the time now to make an assessment as to whether the timer
|
|
has expired or not. If obtaining the time causes the lists to switch
|
|
then don't process this timer as any timers that remained in the list
|
|
when the lists were switched will have been processed within the
|
|
prvSampleTimeNow() function. */
|
|
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
|
|
800e656: f107 0308 add.w r3, r7, #8
|
|
800e65a: 4618 mov r0, r3
|
|
800e65c: f000 f866 bl 800e72c <prvSampleTimeNow>
|
|
800e660: 60f8 str r0, [r7, #12]
|
|
if( xTimerListsWereSwitched == pdFALSE )
|
|
800e662: 68bb ldr r3, [r7, #8]
|
|
800e664: 2b00 cmp r3, #0
|
|
800e666: d130 bne.n 800e6ca <prvProcessTimerOrBlockTask+0x82>
|
|
{
|
|
/* The tick count has not overflowed, has the timer expired? */
|
|
if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
|
|
800e668: 683b ldr r3, [r7, #0]
|
|
800e66a: 2b00 cmp r3, #0
|
|
800e66c: d10a bne.n 800e684 <prvProcessTimerOrBlockTask+0x3c>
|
|
800e66e: 687a ldr r2, [r7, #4]
|
|
800e670: 68fb ldr r3, [r7, #12]
|
|
800e672: 429a cmp r2, r3
|
|
800e674: d806 bhi.n 800e684 <prvProcessTimerOrBlockTask+0x3c>
|
|
{
|
|
( void ) xTaskResumeAll();
|
|
800e676: f7ff f831 bl 800d6dc <xTaskResumeAll>
|
|
prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
|
|
800e67a: 68f9 ldr r1, [r7, #12]
|
|
800e67c: 6878 ldr r0, [r7, #4]
|
|
800e67e: f7ff ff81 bl 800e584 <prvProcessExpiredTimer>
|
|
else
|
|
{
|
|
( void ) xTaskResumeAll();
|
|
}
|
|
}
|
|
}
|
|
800e682: e024 b.n 800e6ce <prvProcessTimerOrBlockTask+0x86>
|
|
if( xListWasEmpty != pdFALSE )
|
|
800e684: 683b ldr r3, [r7, #0]
|
|
800e686: 2b00 cmp r3, #0
|
|
800e688: d008 beq.n 800e69c <prvProcessTimerOrBlockTask+0x54>
|
|
xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
|
|
800e68a: 4b13 ldr r3, [pc, #76] @ (800e6d8 <prvProcessTimerOrBlockTask+0x90>)
|
|
800e68c: 681b ldr r3, [r3, #0]
|
|
800e68e: 681b ldr r3, [r3, #0]
|
|
800e690: 2b00 cmp r3, #0
|
|
800e692: d101 bne.n 800e698 <prvProcessTimerOrBlockTask+0x50>
|
|
800e694: 2301 movs r3, #1
|
|
800e696: e000 b.n 800e69a <prvProcessTimerOrBlockTask+0x52>
|
|
800e698: 2300 movs r3, #0
|
|
800e69a: 603b str r3, [r7, #0]
|
|
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
|
|
800e69c: 4b0f ldr r3, [pc, #60] @ (800e6dc <prvProcessTimerOrBlockTask+0x94>)
|
|
800e69e: 6818 ldr r0, [r3, #0]
|
|
800e6a0: 687a ldr r2, [r7, #4]
|
|
800e6a2: 68fb ldr r3, [r7, #12]
|
|
800e6a4: 1ad3 subs r3, r2, r3
|
|
800e6a6: 683a ldr r2, [r7, #0]
|
|
800e6a8: 4619 mov r1, r3
|
|
800e6aa: f7fe fdc7 bl 800d23c <vQueueWaitForMessageRestricted>
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800e6ae: f7ff f815 bl 800d6dc <xTaskResumeAll>
|
|
800e6b2: 4603 mov r3, r0
|
|
800e6b4: 2b00 cmp r3, #0
|
|
800e6b6: d10a bne.n 800e6ce <prvProcessTimerOrBlockTask+0x86>
|
|
portYIELD_WITHIN_API();
|
|
800e6b8: 4b09 ldr r3, [pc, #36] @ (800e6e0 <prvProcessTimerOrBlockTask+0x98>)
|
|
800e6ba: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800e6be: 601a str r2, [r3, #0]
|
|
800e6c0: f3bf 8f4f dsb sy
|
|
800e6c4: f3bf 8f6f isb sy
|
|
}
|
|
800e6c8: e001 b.n 800e6ce <prvProcessTimerOrBlockTask+0x86>
|
|
( void ) xTaskResumeAll();
|
|
800e6ca: f7ff f807 bl 800d6dc <xTaskResumeAll>
|
|
}
|
|
800e6ce: bf00 nop
|
|
800e6d0: 3710 adds r7, #16
|
|
800e6d2: 46bd mov sp, r7
|
|
800e6d4: bd80 pop {r7, pc}
|
|
800e6d6: bf00 nop
|
|
800e6d8: 200028ac .word 0x200028ac
|
|
800e6dc: 200028b0 .word 0x200028b0
|
|
800e6e0: e000ed04 .word 0xe000ed04
|
|
|
|
0800e6e4 <prvGetNextExpireTime>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
|
|
{
|
|
800e6e4: b480 push {r7}
|
|
800e6e6: b085 sub sp, #20
|
|
800e6e8: af00 add r7, sp, #0
|
|
800e6ea: 6078 str r0, [r7, #4]
|
|
the timer with the nearest expiry time will expire. If there are no
|
|
active timers then just set the next expire time to 0. That will cause
|
|
this task to unblock when the tick count overflows, at which point the
|
|
timer lists will be switched and the next expiry time can be
|
|
re-assessed. */
|
|
*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
|
|
800e6ec: 4b0e ldr r3, [pc, #56] @ (800e728 <prvGetNextExpireTime+0x44>)
|
|
800e6ee: 681b ldr r3, [r3, #0]
|
|
800e6f0: 681b ldr r3, [r3, #0]
|
|
800e6f2: 2b00 cmp r3, #0
|
|
800e6f4: d101 bne.n 800e6fa <prvGetNextExpireTime+0x16>
|
|
800e6f6: 2201 movs r2, #1
|
|
800e6f8: e000 b.n 800e6fc <prvGetNextExpireTime+0x18>
|
|
800e6fa: 2200 movs r2, #0
|
|
800e6fc: 687b ldr r3, [r7, #4]
|
|
800e6fe: 601a str r2, [r3, #0]
|
|
if( *pxListWasEmpty == pdFALSE )
|
|
800e700: 687b ldr r3, [r7, #4]
|
|
800e702: 681b ldr r3, [r3, #0]
|
|
800e704: 2b00 cmp r3, #0
|
|
800e706: d105 bne.n 800e714 <prvGetNextExpireTime+0x30>
|
|
{
|
|
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
|
|
800e708: 4b07 ldr r3, [pc, #28] @ (800e728 <prvGetNextExpireTime+0x44>)
|
|
800e70a: 681b ldr r3, [r3, #0]
|
|
800e70c: 68db ldr r3, [r3, #12]
|
|
800e70e: 681b ldr r3, [r3, #0]
|
|
800e710: 60fb str r3, [r7, #12]
|
|
800e712: e001 b.n 800e718 <prvGetNextExpireTime+0x34>
|
|
}
|
|
else
|
|
{
|
|
/* Ensure the task unblocks when the tick count rolls over. */
|
|
xNextExpireTime = ( TickType_t ) 0U;
|
|
800e714: 2300 movs r3, #0
|
|
800e716: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return xNextExpireTime;
|
|
800e718: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800e71a: 4618 mov r0, r3
|
|
800e71c: 3714 adds r7, #20
|
|
800e71e: 46bd mov sp, r7
|
|
800e720: f85d 7b04 ldr.w r7, [sp], #4
|
|
800e724: 4770 bx lr
|
|
800e726: bf00 nop
|
|
800e728: 200028a8 .word 0x200028a8
|
|
|
|
0800e72c <prvSampleTimeNow>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
|
|
{
|
|
800e72c: b580 push {r7, lr}
|
|
800e72e: b084 sub sp, #16
|
|
800e730: af00 add r7, sp, #0
|
|
800e732: 6078 str r0, [r7, #4]
|
|
TickType_t xTimeNow;
|
|
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
|
|
|
|
xTimeNow = xTaskGetTickCount();
|
|
800e734: f7ff f870 bl 800d818 <xTaskGetTickCount>
|
|
800e738: 60f8 str r0, [r7, #12]
|
|
|
|
if( xTimeNow < xLastTime )
|
|
800e73a: 4b0b ldr r3, [pc, #44] @ (800e768 <prvSampleTimeNow+0x3c>)
|
|
800e73c: 681b ldr r3, [r3, #0]
|
|
800e73e: 68fa ldr r2, [r7, #12]
|
|
800e740: 429a cmp r2, r3
|
|
800e742: d205 bcs.n 800e750 <prvSampleTimeNow+0x24>
|
|
{
|
|
prvSwitchTimerLists();
|
|
800e744: f000 f93a bl 800e9bc <prvSwitchTimerLists>
|
|
*pxTimerListsWereSwitched = pdTRUE;
|
|
800e748: 687b ldr r3, [r7, #4]
|
|
800e74a: 2201 movs r2, #1
|
|
800e74c: 601a str r2, [r3, #0]
|
|
800e74e: e002 b.n 800e756 <prvSampleTimeNow+0x2a>
|
|
}
|
|
else
|
|
{
|
|
*pxTimerListsWereSwitched = pdFALSE;
|
|
800e750: 687b ldr r3, [r7, #4]
|
|
800e752: 2200 movs r2, #0
|
|
800e754: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
xLastTime = xTimeNow;
|
|
800e756: 4a04 ldr r2, [pc, #16] @ (800e768 <prvSampleTimeNow+0x3c>)
|
|
800e758: 68fb ldr r3, [r7, #12]
|
|
800e75a: 6013 str r3, [r2, #0]
|
|
|
|
return xTimeNow;
|
|
800e75c: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800e75e: 4618 mov r0, r3
|
|
800e760: 3710 adds r7, #16
|
|
800e762: 46bd mov sp, r7
|
|
800e764: bd80 pop {r7, pc}
|
|
800e766: bf00 nop
|
|
800e768: 200028b8 .word 0x200028b8
|
|
|
|
0800e76c <prvInsertTimerInActiveList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
|
|
{
|
|
800e76c: b580 push {r7, lr}
|
|
800e76e: b086 sub sp, #24
|
|
800e770: af00 add r7, sp, #0
|
|
800e772: 60f8 str r0, [r7, #12]
|
|
800e774: 60b9 str r1, [r7, #8]
|
|
800e776: 607a str r2, [r7, #4]
|
|
800e778: 603b str r3, [r7, #0]
|
|
BaseType_t xProcessTimerNow = pdFALSE;
|
|
800e77a: 2300 movs r3, #0
|
|
800e77c: 617b str r3, [r7, #20]
|
|
|
|
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
|
|
800e77e: 68fb ldr r3, [r7, #12]
|
|
800e780: 68ba ldr r2, [r7, #8]
|
|
800e782: 605a str r2, [r3, #4]
|
|
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
|
|
800e784: 68fb ldr r3, [r7, #12]
|
|
800e786: 68fa ldr r2, [r7, #12]
|
|
800e788: 611a str r2, [r3, #16]
|
|
|
|
if( xNextExpiryTime <= xTimeNow )
|
|
800e78a: 68ba ldr r2, [r7, #8]
|
|
800e78c: 687b ldr r3, [r7, #4]
|
|
800e78e: 429a cmp r2, r3
|
|
800e790: d812 bhi.n 800e7b8 <prvInsertTimerInActiveList+0x4c>
|
|
{
|
|
/* Has the expiry time elapsed between the command to start/reset a
|
|
timer was issued, and the time the command was processed? */
|
|
if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800e792: 687a ldr r2, [r7, #4]
|
|
800e794: 683b ldr r3, [r7, #0]
|
|
800e796: 1ad2 subs r2, r2, r3
|
|
800e798: 68fb ldr r3, [r7, #12]
|
|
800e79a: 699b ldr r3, [r3, #24]
|
|
800e79c: 429a cmp r2, r3
|
|
800e79e: d302 bcc.n 800e7a6 <prvInsertTimerInActiveList+0x3a>
|
|
{
|
|
/* The time between a command being issued and the command being
|
|
processed actually exceeds the timers period. */
|
|
xProcessTimerNow = pdTRUE;
|
|
800e7a0: 2301 movs r3, #1
|
|
800e7a2: 617b str r3, [r7, #20]
|
|
800e7a4: e01b b.n 800e7de <prvInsertTimerInActiveList+0x72>
|
|
}
|
|
else
|
|
{
|
|
vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
|
|
800e7a6: 4b10 ldr r3, [pc, #64] @ (800e7e8 <prvInsertTimerInActiveList+0x7c>)
|
|
800e7a8: 681a ldr r2, [r3, #0]
|
|
800e7aa: 68fb ldr r3, [r7, #12]
|
|
800e7ac: 3304 adds r3, #4
|
|
800e7ae: 4619 mov r1, r3
|
|
800e7b0: 4610 mov r0, r2
|
|
800e7b2: f7fd fe26 bl 800c402 <vListInsert>
|
|
800e7b6: e012 b.n 800e7de <prvInsertTimerInActiveList+0x72>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
|
|
800e7b8: 687a ldr r2, [r7, #4]
|
|
800e7ba: 683b ldr r3, [r7, #0]
|
|
800e7bc: 429a cmp r2, r3
|
|
800e7be: d206 bcs.n 800e7ce <prvInsertTimerInActiveList+0x62>
|
|
800e7c0: 68ba ldr r2, [r7, #8]
|
|
800e7c2: 683b ldr r3, [r7, #0]
|
|
800e7c4: 429a cmp r2, r3
|
|
800e7c6: d302 bcc.n 800e7ce <prvInsertTimerInActiveList+0x62>
|
|
{
|
|
/* If, since the command was issued, the tick count has overflowed
|
|
but the expiry time has not, then the timer must have already passed
|
|
its expiry time and should be processed immediately. */
|
|
xProcessTimerNow = pdTRUE;
|
|
800e7c8: 2301 movs r3, #1
|
|
800e7ca: 617b str r3, [r7, #20]
|
|
800e7cc: e007 b.n 800e7de <prvInsertTimerInActiveList+0x72>
|
|
}
|
|
else
|
|
{
|
|
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
|
|
800e7ce: 4b07 ldr r3, [pc, #28] @ (800e7ec <prvInsertTimerInActiveList+0x80>)
|
|
800e7d0: 681a ldr r2, [r3, #0]
|
|
800e7d2: 68fb ldr r3, [r7, #12]
|
|
800e7d4: 3304 adds r3, #4
|
|
800e7d6: 4619 mov r1, r3
|
|
800e7d8: 4610 mov r0, r2
|
|
800e7da: f7fd fe12 bl 800c402 <vListInsert>
|
|
}
|
|
}
|
|
|
|
return xProcessTimerNow;
|
|
800e7de: 697b ldr r3, [r7, #20]
|
|
}
|
|
800e7e0: 4618 mov r0, r3
|
|
800e7e2: 3718 adds r7, #24
|
|
800e7e4: 46bd mov sp, r7
|
|
800e7e6: bd80 pop {r7, pc}
|
|
800e7e8: 200028ac .word 0x200028ac
|
|
800e7ec: 200028a8 .word 0x200028a8
|
|
|
|
0800e7f0 <prvProcessReceivedCommands>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvProcessReceivedCommands( void )
|
|
{
|
|
800e7f0: b580 push {r7, lr}
|
|
800e7f2: b08e sub sp, #56 @ 0x38
|
|
800e7f4: af02 add r7, sp, #8
|
|
DaemonTaskMessage_t xMessage;
|
|
Timer_t *pxTimer;
|
|
BaseType_t xTimerListsWereSwitched, xResult;
|
|
TickType_t xTimeNow;
|
|
|
|
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
|
|
800e7f6: e0ce b.n 800e996 <prvProcessReceivedCommands+0x1a6>
|
|
{
|
|
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
|
|
{
|
|
/* Negative commands are pended function calls rather than timer
|
|
commands. */
|
|
if( xMessage.xMessageID < ( BaseType_t ) 0 )
|
|
800e7f8: 687b ldr r3, [r7, #4]
|
|
800e7fa: 2b00 cmp r3, #0
|
|
800e7fc: da19 bge.n 800e832 <prvProcessReceivedCommands+0x42>
|
|
{
|
|
const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
|
|
800e7fe: 1d3b adds r3, r7, #4
|
|
800e800: 3304 adds r3, #4
|
|
800e802: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
/* The timer uses the xCallbackParameters member to request a
|
|
callback be executed. Check the callback is not NULL. */
|
|
configASSERT( pxCallback );
|
|
800e804: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800e806: 2b00 cmp r3, #0
|
|
800e808: d10b bne.n 800e822 <prvProcessReceivedCommands+0x32>
|
|
__asm volatile
|
|
800e80a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e80e: f383 8811 msr BASEPRI, r3
|
|
800e812: f3bf 8f6f isb sy
|
|
800e816: f3bf 8f4f dsb sy
|
|
800e81a: 61fb str r3, [r7, #28]
|
|
}
|
|
800e81c: bf00 nop
|
|
800e81e: bf00 nop
|
|
800e820: e7fd b.n 800e81e <prvProcessReceivedCommands+0x2e>
|
|
|
|
/* Call the function. */
|
|
pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
|
|
800e822: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800e824: 681b ldr r3, [r3, #0]
|
|
800e826: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800e828: 6850 ldr r0, [r2, #4]
|
|
800e82a: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800e82c: 6892 ldr r2, [r2, #8]
|
|
800e82e: 4611 mov r1, r2
|
|
800e830: 4798 blx r3
|
|
}
|
|
#endif /* INCLUDE_xTimerPendFunctionCall */
|
|
|
|
/* Commands that are positive are timer commands rather than pended
|
|
function calls. */
|
|
if( xMessage.xMessageID >= ( BaseType_t ) 0 )
|
|
800e832: 687b ldr r3, [r7, #4]
|
|
800e834: 2b00 cmp r3, #0
|
|
800e836: f2c0 80ae blt.w 800e996 <prvProcessReceivedCommands+0x1a6>
|
|
{
|
|
/* The messages uses the xTimerParameters member to work on a
|
|
software timer. */
|
|
pxTimer = xMessage.u.xTimerParameters.pxTimer;
|
|
800e83a: 68fb ldr r3, [r7, #12]
|
|
800e83c: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
|
|
800e83e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e840: 695b ldr r3, [r3, #20]
|
|
800e842: 2b00 cmp r3, #0
|
|
800e844: d004 beq.n 800e850 <prvProcessReceivedCommands+0x60>
|
|
{
|
|
/* The timer is in a list, remove it. */
|
|
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
|
|
800e846: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e848: 3304 adds r3, #4
|
|
800e84a: 4618 mov r0, r3
|
|
800e84c: f7fd fe12 bl 800c474 <uxListRemove>
|
|
it must be present in the function call. prvSampleTimeNow() must be
|
|
called after the message is received from xTimerQueue so there is no
|
|
possibility of a higher priority task adding a message to the message
|
|
queue with a time that is ahead of the timer daemon task (because it
|
|
pre-empted the timer daemon task after the xTimeNow value was set). */
|
|
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
|
|
800e850: 463b mov r3, r7
|
|
800e852: 4618 mov r0, r3
|
|
800e854: f7ff ff6a bl 800e72c <prvSampleTimeNow>
|
|
800e858: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
switch( xMessage.xMessageID )
|
|
800e85a: 687b ldr r3, [r7, #4]
|
|
800e85c: 2b09 cmp r3, #9
|
|
800e85e: f200 8097 bhi.w 800e990 <prvProcessReceivedCommands+0x1a0>
|
|
800e862: a201 add r2, pc, #4 @ (adr r2, 800e868 <prvProcessReceivedCommands+0x78>)
|
|
800e864: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800e868: 0800e891 .word 0x0800e891
|
|
800e86c: 0800e891 .word 0x0800e891
|
|
800e870: 0800e891 .word 0x0800e891
|
|
800e874: 0800e907 .word 0x0800e907
|
|
800e878: 0800e91b .word 0x0800e91b
|
|
800e87c: 0800e967 .word 0x0800e967
|
|
800e880: 0800e891 .word 0x0800e891
|
|
800e884: 0800e891 .word 0x0800e891
|
|
800e888: 0800e907 .word 0x0800e907
|
|
800e88c: 0800e91b .word 0x0800e91b
|
|
case tmrCOMMAND_START_FROM_ISR :
|
|
case tmrCOMMAND_RESET :
|
|
case tmrCOMMAND_RESET_FROM_ISR :
|
|
case tmrCOMMAND_START_DONT_TRACE :
|
|
/* Start or restart a timer. */
|
|
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
|
|
800e890: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e892: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e896: f043 0301 orr.w r3, r3, #1
|
|
800e89a: b2da uxtb r2, r3
|
|
800e89c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e89e: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
|
|
800e8a2: 68ba ldr r2, [r7, #8]
|
|
800e8a4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e8a6: 699b ldr r3, [r3, #24]
|
|
800e8a8: 18d1 adds r1, r2, r3
|
|
800e8aa: 68bb ldr r3, [r7, #8]
|
|
800e8ac: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800e8ae: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800e8b0: f7ff ff5c bl 800e76c <prvInsertTimerInActiveList>
|
|
800e8b4: 4603 mov r3, r0
|
|
800e8b6: 2b00 cmp r3, #0
|
|
800e8b8: d06c beq.n 800e994 <prvProcessReceivedCommands+0x1a4>
|
|
{
|
|
/* The timer expired before it was added to the active
|
|
timer list. Process it now. */
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
|
800e8ba: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e8bc: 6a1b ldr r3, [r3, #32]
|
|
800e8be: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800e8c0: 4798 blx r3
|
|
traceTIMER_EXPIRED( pxTimer );
|
|
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
|
|
800e8c2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e8c4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e8c8: f003 0304 and.w r3, r3, #4
|
|
800e8cc: 2b00 cmp r3, #0
|
|
800e8ce: d061 beq.n 800e994 <prvProcessReceivedCommands+0x1a4>
|
|
{
|
|
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
|
|
800e8d0: 68ba ldr r2, [r7, #8]
|
|
800e8d2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e8d4: 699b ldr r3, [r3, #24]
|
|
800e8d6: 441a add r2, r3
|
|
800e8d8: 2300 movs r3, #0
|
|
800e8da: 9300 str r3, [sp, #0]
|
|
800e8dc: 2300 movs r3, #0
|
|
800e8de: 2100 movs r1, #0
|
|
800e8e0: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800e8e2: f7ff fe01 bl 800e4e8 <xTimerGenericCommand>
|
|
800e8e6: 6238 str r0, [r7, #32]
|
|
configASSERT( xResult );
|
|
800e8e8: 6a3b ldr r3, [r7, #32]
|
|
800e8ea: 2b00 cmp r3, #0
|
|
800e8ec: d152 bne.n 800e994 <prvProcessReceivedCommands+0x1a4>
|
|
__asm volatile
|
|
800e8ee: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e8f2: f383 8811 msr BASEPRI, r3
|
|
800e8f6: f3bf 8f6f isb sy
|
|
800e8fa: f3bf 8f4f dsb sy
|
|
800e8fe: 61bb str r3, [r7, #24]
|
|
}
|
|
800e900: bf00 nop
|
|
800e902: bf00 nop
|
|
800e904: e7fd b.n 800e902 <prvProcessReceivedCommands+0x112>
|
|
break;
|
|
|
|
case tmrCOMMAND_STOP :
|
|
case tmrCOMMAND_STOP_FROM_ISR :
|
|
/* The timer has already been removed from the active list. */
|
|
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
|
|
800e906: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e908: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e90c: f023 0301 bic.w r3, r3, #1
|
|
800e910: b2da uxtb r2, r3
|
|
800e912: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e914: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
break;
|
|
800e918: e03d b.n 800e996 <prvProcessReceivedCommands+0x1a6>
|
|
|
|
case tmrCOMMAND_CHANGE_PERIOD :
|
|
case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
|
|
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
|
|
800e91a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e91c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e920: f043 0301 orr.w r3, r3, #1
|
|
800e924: b2da uxtb r2, r3
|
|
800e926: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e928: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
|
|
800e92c: 68ba ldr r2, [r7, #8]
|
|
800e92e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e930: 619a str r2, [r3, #24]
|
|
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
|
|
800e932: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e934: 699b ldr r3, [r3, #24]
|
|
800e936: 2b00 cmp r3, #0
|
|
800e938: d10b bne.n 800e952 <prvProcessReceivedCommands+0x162>
|
|
__asm volatile
|
|
800e93a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800e93e: f383 8811 msr BASEPRI, r3
|
|
800e942: f3bf 8f6f isb sy
|
|
800e946: f3bf 8f4f dsb sy
|
|
800e94a: 617b str r3, [r7, #20]
|
|
}
|
|
800e94c: bf00 nop
|
|
800e94e: bf00 nop
|
|
800e950: e7fd b.n 800e94e <prvProcessReceivedCommands+0x15e>
|
|
be longer or shorter than the old one. The command time is
|
|
therefore set to the current time, and as the period cannot
|
|
be zero the next expiry time can only be in the future,
|
|
meaning (unlike for the xTimerStart() case above) there is
|
|
no fail case that needs to be handled here. */
|
|
( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
|
|
800e952: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e954: 699a ldr r2, [r3, #24]
|
|
800e956: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800e958: 18d1 adds r1, r2, r3
|
|
800e95a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800e95c: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800e95e: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800e960: f7ff ff04 bl 800e76c <prvInsertTimerInActiveList>
|
|
break;
|
|
800e964: e017 b.n 800e996 <prvProcessReceivedCommands+0x1a6>
|
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
{
|
|
/* The timer has already been removed from the active list,
|
|
just free up the memory if the memory was dynamically
|
|
allocated. */
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
|
|
800e966: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e968: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e96c: f003 0302 and.w r3, r3, #2
|
|
800e970: 2b00 cmp r3, #0
|
|
800e972: d103 bne.n 800e97c <prvProcessReceivedCommands+0x18c>
|
|
{
|
|
vPortFree( pxTimer );
|
|
800e974: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800e976: f000 fbe7 bl 800f148 <vPortFree>
|
|
no need to free the memory - just mark the timer as
|
|
"not active". */
|
|
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
break;
|
|
800e97a: e00c b.n 800e996 <prvProcessReceivedCommands+0x1a6>
|
|
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
|
|
800e97c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e97e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e982: f023 0301 bic.w r3, r3, #1
|
|
800e986: b2da uxtb r2, r3
|
|
800e988: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800e98a: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
break;
|
|
800e98e: e002 b.n 800e996 <prvProcessReceivedCommands+0x1a6>
|
|
|
|
default :
|
|
/* Don't expect to get here. */
|
|
break;
|
|
800e990: bf00 nop
|
|
800e992: e000 b.n 800e996 <prvProcessReceivedCommands+0x1a6>
|
|
break;
|
|
800e994: bf00 nop
|
|
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
|
|
800e996: 4b08 ldr r3, [pc, #32] @ (800e9b8 <prvProcessReceivedCommands+0x1c8>)
|
|
800e998: 681b ldr r3, [r3, #0]
|
|
800e99a: 1d39 adds r1, r7, #4
|
|
800e99c: 2200 movs r2, #0
|
|
800e99e: 4618 mov r0, r3
|
|
800e9a0: f7fe f908 bl 800cbb4 <xQueueReceive>
|
|
800e9a4: 4603 mov r3, r0
|
|
800e9a6: 2b00 cmp r3, #0
|
|
800e9a8: f47f af26 bne.w 800e7f8 <prvProcessReceivedCommands+0x8>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
800e9ac: bf00 nop
|
|
800e9ae: bf00 nop
|
|
800e9b0: 3730 adds r7, #48 @ 0x30
|
|
800e9b2: 46bd mov sp, r7
|
|
800e9b4: bd80 pop {r7, pc}
|
|
800e9b6: bf00 nop
|
|
800e9b8: 200028b0 .word 0x200028b0
|
|
|
|
0800e9bc <prvSwitchTimerLists>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvSwitchTimerLists( void )
|
|
{
|
|
800e9bc: b580 push {r7, lr}
|
|
800e9be: b088 sub sp, #32
|
|
800e9c0: af02 add r7, sp, #8
|
|
|
|
/* The tick count has overflowed. The timer lists must be switched.
|
|
If there are any timers still referenced from the current timer list
|
|
then they must have expired and should be processed before the lists
|
|
are switched. */
|
|
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
|
|
800e9c2: e049 b.n 800ea58 <prvSwitchTimerLists+0x9c>
|
|
{
|
|
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
|
|
800e9c4: 4b2e ldr r3, [pc, #184] @ (800ea80 <prvSwitchTimerLists+0xc4>)
|
|
800e9c6: 681b ldr r3, [r3, #0]
|
|
800e9c8: 68db ldr r3, [r3, #12]
|
|
800e9ca: 681b ldr r3, [r3, #0]
|
|
800e9cc: 613b str r3, [r7, #16]
|
|
|
|
/* Remove the timer from the list. */
|
|
pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800e9ce: 4b2c ldr r3, [pc, #176] @ (800ea80 <prvSwitchTimerLists+0xc4>)
|
|
800e9d0: 681b ldr r3, [r3, #0]
|
|
800e9d2: 68db ldr r3, [r3, #12]
|
|
800e9d4: 68db ldr r3, [r3, #12]
|
|
800e9d6: 60fb str r3, [r7, #12]
|
|
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
|
|
800e9d8: 68fb ldr r3, [r7, #12]
|
|
800e9da: 3304 adds r3, #4
|
|
800e9dc: 4618 mov r0, r3
|
|
800e9de: f7fd fd49 bl 800c474 <uxListRemove>
|
|
traceTIMER_EXPIRED( pxTimer );
|
|
|
|
/* Execute its callback, then send a command to restart the timer if
|
|
it is an auto-reload timer. It cannot be restarted here as the lists
|
|
have not yet been switched. */
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
|
800e9e2: 68fb ldr r3, [r7, #12]
|
|
800e9e4: 6a1b ldr r3, [r3, #32]
|
|
800e9e6: 68f8 ldr r0, [r7, #12]
|
|
800e9e8: 4798 blx r3
|
|
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
|
|
800e9ea: 68fb ldr r3, [r7, #12]
|
|
800e9ec: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
800e9f0: f003 0304 and.w r3, r3, #4
|
|
800e9f4: 2b00 cmp r3, #0
|
|
800e9f6: d02f beq.n 800ea58 <prvSwitchTimerLists+0x9c>
|
|
the timer going into the same timer list then it has already expired
|
|
and the timer should be re-inserted into the current list so it is
|
|
processed again within this loop. Otherwise a command should be sent
|
|
to restart the timer to ensure it is only inserted into a list after
|
|
the lists have been swapped. */
|
|
xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
|
|
800e9f8: 68fb ldr r3, [r7, #12]
|
|
800e9fa: 699b ldr r3, [r3, #24]
|
|
800e9fc: 693a ldr r2, [r7, #16]
|
|
800e9fe: 4413 add r3, r2
|
|
800ea00: 60bb str r3, [r7, #8]
|
|
if( xReloadTime > xNextExpireTime )
|
|
800ea02: 68ba ldr r2, [r7, #8]
|
|
800ea04: 693b ldr r3, [r7, #16]
|
|
800ea06: 429a cmp r2, r3
|
|
800ea08: d90e bls.n 800ea28 <prvSwitchTimerLists+0x6c>
|
|
{
|
|
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
|
|
800ea0a: 68fb ldr r3, [r7, #12]
|
|
800ea0c: 68ba ldr r2, [r7, #8]
|
|
800ea0e: 605a str r2, [r3, #4]
|
|
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
|
|
800ea10: 68fb ldr r3, [r7, #12]
|
|
800ea12: 68fa ldr r2, [r7, #12]
|
|
800ea14: 611a str r2, [r3, #16]
|
|
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
|
|
800ea16: 4b1a ldr r3, [pc, #104] @ (800ea80 <prvSwitchTimerLists+0xc4>)
|
|
800ea18: 681a ldr r2, [r3, #0]
|
|
800ea1a: 68fb ldr r3, [r7, #12]
|
|
800ea1c: 3304 adds r3, #4
|
|
800ea1e: 4619 mov r1, r3
|
|
800ea20: 4610 mov r0, r2
|
|
800ea22: f7fd fcee bl 800c402 <vListInsert>
|
|
800ea26: e017 b.n 800ea58 <prvSwitchTimerLists+0x9c>
|
|
}
|
|
else
|
|
{
|
|
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
|
|
800ea28: 2300 movs r3, #0
|
|
800ea2a: 9300 str r3, [sp, #0]
|
|
800ea2c: 2300 movs r3, #0
|
|
800ea2e: 693a ldr r2, [r7, #16]
|
|
800ea30: 2100 movs r1, #0
|
|
800ea32: 68f8 ldr r0, [r7, #12]
|
|
800ea34: f7ff fd58 bl 800e4e8 <xTimerGenericCommand>
|
|
800ea38: 6078 str r0, [r7, #4]
|
|
configASSERT( xResult );
|
|
800ea3a: 687b ldr r3, [r7, #4]
|
|
800ea3c: 2b00 cmp r3, #0
|
|
800ea3e: d10b bne.n 800ea58 <prvSwitchTimerLists+0x9c>
|
|
__asm volatile
|
|
800ea40: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ea44: f383 8811 msr BASEPRI, r3
|
|
800ea48: f3bf 8f6f isb sy
|
|
800ea4c: f3bf 8f4f dsb sy
|
|
800ea50: 603b str r3, [r7, #0]
|
|
}
|
|
800ea52: bf00 nop
|
|
800ea54: bf00 nop
|
|
800ea56: e7fd b.n 800ea54 <prvSwitchTimerLists+0x98>
|
|
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
|
|
800ea58: 4b09 ldr r3, [pc, #36] @ (800ea80 <prvSwitchTimerLists+0xc4>)
|
|
800ea5a: 681b ldr r3, [r3, #0]
|
|
800ea5c: 681b ldr r3, [r3, #0]
|
|
800ea5e: 2b00 cmp r3, #0
|
|
800ea60: d1b0 bne.n 800e9c4 <prvSwitchTimerLists+0x8>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
pxTemp = pxCurrentTimerList;
|
|
800ea62: 4b07 ldr r3, [pc, #28] @ (800ea80 <prvSwitchTimerLists+0xc4>)
|
|
800ea64: 681b ldr r3, [r3, #0]
|
|
800ea66: 617b str r3, [r7, #20]
|
|
pxCurrentTimerList = pxOverflowTimerList;
|
|
800ea68: 4b06 ldr r3, [pc, #24] @ (800ea84 <prvSwitchTimerLists+0xc8>)
|
|
800ea6a: 681b ldr r3, [r3, #0]
|
|
800ea6c: 4a04 ldr r2, [pc, #16] @ (800ea80 <prvSwitchTimerLists+0xc4>)
|
|
800ea6e: 6013 str r3, [r2, #0]
|
|
pxOverflowTimerList = pxTemp;
|
|
800ea70: 4a04 ldr r2, [pc, #16] @ (800ea84 <prvSwitchTimerLists+0xc8>)
|
|
800ea72: 697b ldr r3, [r7, #20]
|
|
800ea74: 6013 str r3, [r2, #0]
|
|
}
|
|
800ea76: bf00 nop
|
|
800ea78: 3718 adds r7, #24
|
|
800ea7a: 46bd mov sp, r7
|
|
800ea7c: bd80 pop {r7, pc}
|
|
800ea7e: bf00 nop
|
|
800ea80: 200028a8 .word 0x200028a8
|
|
800ea84: 200028ac .word 0x200028ac
|
|
|
|
0800ea88 <prvCheckForValidListAndQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCheckForValidListAndQueue( void )
|
|
{
|
|
800ea88: b580 push {r7, lr}
|
|
800ea8a: b082 sub sp, #8
|
|
800ea8c: af02 add r7, sp, #8
|
|
/* Check that the list from which active timers are referenced, and the
|
|
queue used to communicate with the timer service, have been
|
|
initialised. */
|
|
taskENTER_CRITICAL();
|
|
800ea8e: f000 f96b bl 800ed68 <vPortEnterCritical>
|
|
{
|
|
if( xTimerQueue == NULL )
|
|
800ea92: 4b15 ldr r3, [pc, #84] @ (800eae8 <prvCheckForValidListAndQueue+0x60>)
|
|
800ea94: 681b ldr r3, [r3, #0]
|
|
800ea96: 2b00 cmp r3, #0
|
|
800ea98: d120 bne.n 800eadc <prvCheckForValidListAndQueue+0x54>
|
|
{
|
|
vListInitialise( &xActiveTimerList1 );
|
|
800ea9a: 4814 ldr r0, [pc, #80] @ (800eaec <prvCheckForValidListAndQueue+0x64>)
|
|
800ea9c: f7fd fc60 bl 800c360 <vListInitialise>
|
|
vListInitialise( &xActiveTimerList2 );
|
|
800eaa0: 4813 ldr r0, [pc, #76] @ (800eaf0 <prvCheckForValidListAndQueue+0x68>)
|
|
800eaa2: f7fd fc5d bl 800c360 <vListInitialise>
|
|
pxCurrentTimerList = &xActiveTimerList1;
|
|
800eaa6: 4b13 ldr r3, [pc, #76] @ (800eaf4 <prvCheckForValidListAndQueue+0x6c>)
|
|
800eaa8: 4a10 ldr r2, [pc, #64] @ (800eaec <prvCheckForValidListAndQueue+0x64>)
|
|
800eaaa: 601a str r2, [r3, #0]
|
|
pxOverflowTimerList = &xActiveTimerList2;
|
|
800eaac: 4b12 ldr r3, [pc, #72] @ (800eaf8 <prvCheckForValidListAndQueue+0x70>)
|
|
800eaae: 4a10 ldr r2, [pc, #64] @ (800eaf0 <prvCheckForValidListAndQueue+0x68>)
|
|
800eab0: 601a str r2, [r3, #0]
|
|
/* The timer queue is allocated statically in case
|
|
configSUPPORT_DYNAMIC_ALLOCATION is 0. */
|
|
static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
|
|
static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
|
|
|
|
xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
|
|
800eab2: 2300 movs r3, #0
|
|
800eab4: 9300 str r3, [sp, #0]
|
|
800eab6: 4b11 ldr r3, [pc, #68] @ (800eafc <prvCheckForValidListAndQueue+0x74>)
|
|
800eab8: 4a11 ldr r2, [pc, #68] @ (800eb00 <prvCheckForValidListAndQueue+0x78>)
|
|
800eaba: 2110 movs r1, #16
|
|
800eabc: 200a movs r0, #10
|
|
800eabe: f7fd fd6d bl 800c59c <xQueueGenericCreateStatic>
|
|
800eac2: 4603 mov r3, r0
|
|
800eac4: 4a08 ldr r2, [pc, #32] @ (800eae8 <prvCheckForValidListAndQueue+0x60>)
|
|
800eac6: 6013 str r3, [r2, #0]
|
|
}
|
|
#endif
|
|
|
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
|
{
|
|
if( xTimerQueue != NULL )
|
|
800eac8: 4b07 ldr r3, [pc, #28] @ (800eae8 <prvCheckForValidListAndQueue+0x60>)
|
|
800eaca: 681b ldr r3, [r3, #0]
|
|
800eacc: 2b00 cmp r3, #0
|
|
800eace: d005 beq.n 800eadc <prvCheckForValidListAndQueue+0x54>
|
|
{
|
|
vQueueAddToRegistry( xTimerQueue, "TmrQ" );
|
|
800ead0: 4b05 ldr r3, [pc, #20] @ (800eae8 <prvCheckForValidListAndQueue+0x60>)
|
|
800ead2: 681b ldr r3, [r3, #0]
|
|
800ead4: 490b ldr r1, [pc, #44] @ (800eb04 <prvCheckForValidListAndQueue+0x7c>)
|
|
800ead6: 4618 mov r0, r3
|
|
800ead8: f7fe fb86 bl 800d1e8 <vQueueAddToRegistry>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800eadc: f000 f976 bl 800edcc <vPortExitCritical>
|
|
}
|
|
800eae0: bf00 nop
|
|
800eae2: 46bd mov sp, r7
|
|
800eae4: bd80 pop {r7, pc}
|
|
800eae6: bf00 nop
|
|
800eae8: 200028b0 .word 0x200028b0
|
|
800eaec: 20002880 .word 0x20002880
|
|
800eaf0: 20002894 .word 0x20002894
|
|
800eaf4: 200028a8 .word 0x200028a8
|
|
800eaf8: 200028ac .word 0x200028ac
|
|
800eafc: 2000295c .word 0x2000295c
|
|
800eb00: 200028bc .word 0x200028bc
|
|
800eb04: 0801473c .word 0x0801473c
|
|
|
|
0800eb08 <pxPortInitialiseStack>:
|
|
|
|
/*
|
|
* See header file for description.
|
|
*/
|
|
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
|
{
|
|
800eb08: b480 push {r7}
|
|
800eb0a: b085 sub sp, #20
|
|
800eb0c: af00 add r7, sp, #0
|
|
800eb0e: 60f8 str r0, [r7, #12]
|
|
800eb10: 60b9 str r1, [r7, #8]
|
|
800eb12: 607a str r2, [r7, #4]
|
|
/* Simulate the stack frame as it would be created by a context switch
|
|
interrupt. */
|
|
|
|
/* Offset added to account for the way the MCU uses the stack on entry/exit
|
|
of interrupts, and to ensure alignment. */
|
|
pxTopOfStack--;
|
|
800eb14: 68fb ldr r3, [r7, #12]
|
|
800eb16: 3b04 subs r3, #4
|
|
800eb18: 60fb str r3, [r7, #12]
|
|
|
|
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
|
|
800eb1a: 68fb ldr r3, [r7, #12]
|
|
800eb1c: f04f 7280 mov.w r2, #16777216 @ 0x1000000
|
|
800eb20: 601a str r2, [r3, #0]
|
|
pxTopOfStack--;
|
|
800eb22: 68fb ldr r3, [r7, #12]
|
|
800eb24: 3b04 subs r3, #4
|
|
800eb26: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
|
|
800eb28: 68bb ldr r3, [r7, #8]
|
|
800eb2a: f023 0201 bic.w r2, r3, #1
|
|
800eb2e: 68fb ldr r3, [r7, #12]
|
|
800eb30: 601a str r2, [r3, #0]
|
|
pxTopOfStack--;
|
|
800eb32: 68fb ldr r3, [r7, #12]
|
|
800eb34: 3b04 subs r3, #4
|
|
800eb36: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
|
|
800eb38: 4a0c ldr r2, [pc, #48] @ (800eb6c <pxPortInitialiseStack+0x64>)
|
|
800eb3a: 68fb ldr r3, [r7, #12]
|
|
800eb3c: 601a str r2, [r3, #0]
|
|
|
|
/* Save code space by skipping register initialisation. */
|
|
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
|
|
800eb3e: 68fb ldr r3, [r7, #12]
|
|
800eb40: 3b14 subs r3, #20
|
|
800eb42: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
|
|
800eb44: 687a ldr r2, [r7, #4]
|
|
800eb46: 68fb ldr r3, [r7, #12]
|
|
800eb48: 601a str r2, [r3, #0]
|
|
|
|
/* A save method is being used that requires each task to maintain its
|
|
own exec return value. */
|
|
pxTopOfStack--;
|
|
800eb4a: 68fb ldr r3, [r7, #12]
|
|
800eb4c: 3b04 subs r3, #4
|
|
800eb4e: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = portINITIAL_EXC_RETURN;
|
|
800eb50: 68fb ldr r3, [r7, #12]
|
|
800eb52: f06f 0202 mvn.w r2, #2
|
|
800eb56: 601a str r2, [r3, #0]
|
|
|
|
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
|
|
800eb58: 68fb ldr r3, [r7, #12]
|
|
800eb5a: 3b20 subs r3, #32
|
|
800eb5c: 60fb str r3, [r7, #12]
|
|
|
|
return pxTopOfStack;
|
|
800eb5e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800eb60: 4618 mov r0, r3
|
|
800eb62: 3714 adds r7, #20
|
|
800eb64: 46bd mov sp, r7
|
|
800eb66: f85d 7b04 ldr.w r7, [sp], #4
|
|
800eb6a: 4770 bx lr
|
|
800eb6c: 0800eb71 .word 0x0800eb71
|
|
|
|
0800eb70 <prvTaskExitError>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvTaskExitError( void )
|
|
{
|
|
800eb70: b480 push {r7}
|
|
800eb72: b085 sub sp, #20
|
|
800eb74: af00 add r7, sp, #0
|
|
volatile uint32_t ulDummy = 0;
|
|
800eb76: 2300 movs r3, #0
|
|
800eb78: 607b str r3, [r7, #4]
|
|
its caller as there is nothing to return to. If a task wants to exit it
|
|
should instead call vTaskDelete( NULL ).
|
|
|
|
Artificially force an assert() to be triggered if configASSERT() is
|
|
defined, then stop here so application writers can catch the error. */
|
|
configASSERT( uxCriticalNesting == ~0UL );
|
|
800eb7a: 4b13 ldr r3, [pc, #76] @ (800ebc8 <prvTaskExitError+0x58>)
|
|
800eb7c: 681b ldr r3, [r3, #0]
|
|
800eb7e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800eb82: d00b beq.n 800eb9c <prvTaskExitError+0x2c>
|
|
__asm volatile
|
|
800eb84: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800eb88: f383 8811 msr BASEPRI, r3
|
|
800eb8c: f3bf 8f6f isb sy
|
|
800eb90: f3bf 8f4f dsb sy
|
|
800eb94: 60fb str r3, [r7, #12]
|
|
}
|
|
800eb96: bf00 nop
|
|
800eb98: bf00 nop
|
|
800eb9a: e7fd b.n 800eb98 <prvTaskExitError+0x28>
|
|
__asm volatile
|
|
800eb9c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800eba0: f383 8811 msr BASEPRI, r3
|
|
800eba4: f3bf 8f6f isb sy
|
|
800eba8: f3bf 8f4f dsb sy
|
|
800ebac: 60bb str r3, [r7, #8]
|
|
}
|
|
800ebae: bf00 nop
|
|
portDISABLE_INTERRUPTS();
|
|
while( ulDummy == 0 )
|
|
800ebb0: bf00 nop
|
|
800ebb2: 687b ldr r3, [r7, #4]
|
|
800ebb4: 2b00 cmp r3, #0
|
|
800ebb6: d0fc beq.n 800ebb2 <prvTaskExitError+0x42>
|
|
about code appearing after this function is called - making ulDummy
|
|
volatile makes the compiler think the function could return and
|
|
therefore not output an 'unreachable code' warning for code that appears
|
|
after it. */
|
|
}
|
|
}
|
|
800ebb8: bf00 nop
|
|
800ebba: bf00 nop
|
|
800ebbc: 3714 adds r7, #20
|
|
800ebbe: 46bd mov sp, r7
|
|
800ebc0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ebc4: 4770 bx lr
|
|
800ebc6: bf00 nop
|
|
800ebc8: 200000d0 .word 0x200000d0
|
|
800ebcc: 00000000 .word 0x00000000
|
|
|
|
0800ebd0 <SVC_Handler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortSVCHandler( void )
|
|
{
|
|
__asm volatile (
|
|
800ebd0: 4b07 ldr r3, [pc, #28] @ (800ebf0 <pxCurrentTCBConst2>)
|
|
800ebd2: 6819 ldr r1, [r3, #0]
|
|
800ebd4: 6808 ldr r0, [r1, #0]
|
|
800ebd6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800ebda: f380 8809 msr PSP, r0
|
|
800ebde: f3bf 8f6f isb sy
|
|
800ebe2: f04f 0000 mov.w r0, #0
|
|
800ebe6: f380 8811 msr BASEPRI, r0
|
|
800ebea: 4770 bx lr
|
|
800ebec: f3af 8000 nop.w
|
|
|
|
0800ebf0 <pxCurrentTCBConst2>:
|
|
800ebf0: 20002380 .word 0x20002380
|
|
" bx r14 \n"
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
|
|
);
|
|
}
|
|
800ebf4: bf00 nop
|
|
800ebf6: bf00 nop
|
|
|
|
0800ebf8 <prvPortStartFirstTask>:
|
|
{
|
|
/* Start the first task. This also clears the bit that indicates the FPU is
|
|
in use in case the FPU was used before the scheduler was started - which
|
|
would otherwise result in the unnecessary leaving of space in the SVC stack
|
|
for lazy saving of FPU registers. */
|
|
__asm volatile(
|
|
800ebf8: 4808 ldr r0, [pc, #32] @ (800ec1c <prvPortStartFirstTask+0x24>)
|
|
800ebfa: 6800 ldr r0, [r0, #0]
|
|
800ebfc: 6800 ldr r0, [r0, #0]
|
|
800ebfe: f380 8808 msr MSP, r0
|
|
800ec02: f04f 0000 mov.w r0, #0
|
|
800ec06: f380 8814 msr CONTROL, r0
|
|
800ec0a: b662 cpsie i
|
|
800ec0c: b661 cpsie f
|
|
800ec0e: f3bf 8f4f dsb sy
|
|
800ec12: f3bf 8f6f isb sy
|
|
800ec16: df00 svc 0
|
|
800ec18: bf00 nop
|
|
" dsb \n"
|
|
" isb \n"
|
|
" svc 0 \n" /* System call to start first task. */
|
|
" nop \n"
|
|
);
|
|
}
|
|
800ec1a: bf00 nop
|
|
800ec1c: e000ed08 .word 0xe000ed08
|
|
|
|
0800ec20 <xPortStartScheduler>:
|
|
|
|
/*
|
|
* See header file for description.
|
|
*/
|
|
BaseType_t xPortStartScheduler( void )
|
|
{
|
|
800ec20: b580 push {r7, lr}
|
|
800ec22: b086 sub sp, #24
|
|
800ec24: af00 add r7, sp, #0
|
|
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
|
|
|
|
/* This port can be used on all revisions of the Cortex-M7 core other than
|
|
the r0p1 parts. r0p1 parts should use the port from the
|
|
/source/portable/GCC/ARM_CM7/r0p1 directory. */
|
|
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
|
|
800ec26: 4b47 ldr r3, [pc, #284] @ (800ed44 <xPortStartScheduler+0x124>)
|
|
800ec28: 681b ldr r3, [r3, #0]
|
|
800ec2a: 4a47 ldr r2, [pc, #284] @ (800ed48 <xPortStartScheduler+0x128>)
|
|
800ec2c: 4293 cmp r3, r2
|
|
800ec2e: d10b bne.n 800ec48 <xPortStartScheduler+0x28>
|
|
__asm volatile
|
|
800ec30: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ec34: f383 8811 msr BASEPRI, r3
|
|
800ec38: f3bf 8f6f isb sy
|
|
800ec3c: f3bf 8f4f dsb sy
|
|
800ec40: 60fb str r3, [r7, #12]
|
|
}
|
|
800ec42: bf00 nop
|
|
800ec44: bf00 nop
|
|
800ec46: e7fd b.n 800ec44 <xPortStartScheduler+0x24>
|
|
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
|
|
800ec48: 4b3e ldr r3, [pc, #248] @ (800ed44 <xPortStartScheduler+0x124>)
|
|
800ec4a: 681b ldr r3, [r3, #0]
|
|
800ec4c: 4a3f ldr r2, [pc, #252] @ (800ed4c <xPortStartScheduler+0x12c>)
|
|
800ec4e: 4293 cmp r3, r2
|
|
800ec50: d10b bne.n 800ec6a <xPortStartScheduler+0x4a>
|
|
__asm volatile
|
|
800ec52: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ec56: f383 8811 msr BASEPRI, r3
|
|
800ec5a: f3bf 8f6f isb sy
|
|
800ec5e: f3bf 8f4f dsb sy
|
|
800ec62: 613b str r3, [r7, #16]
|
|
}
|
|
800ec64: bf00 nop
|
|
800ec66: bf00 nop
|
|
800ec68: e7fd b.n 800ec66 <xPortStartScheduler+0x46>
|
|
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
volatile uint32_t ulOriginalPriority;
|
|
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
|
|
800ec6a: 4b39 ldr r3, [pc, #228] @ (800ed50 <xPortStartScheduler+0x130>)
|
|
800ec6c: 617b str r3, [r7, #20]
|
|
functions can be called. ISR safe functions are those that end in
|
|
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
|
|
ensure interrupt entry is as fast and simple as possible.
|
|
|
|
Save the interrupt priority value that is about to be clobbered. */
|
|
ulOriginalPriority = *pucFirstUserPriorityRegister;
|
|
800ec6e: 697b ldr r3, [r7, #20]
|
|
800ec70: 781b ldrb r3, [r3, #0]
|
|
800ec72: b2db uxtb r3, r3
|
|
800ec74: 607b str r3, [r7, #4]
|
|
|
|
/* Determine the number of priority bits available. First write to all
|
|
possible bits. */
|
|
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
|
|
800ec76: 697b ldr r3, [r7, #20]
|
|
800ec78: 22ff movs r2, #255 @ 0xff
|
|
800ec7a: 701a strb r2, [r3, #0]
|
|
|
|
/* Read the value back to see how many bits stuck. */
|
|
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
|
800ec7c: 697b ldr r3, [r7, #20]
|
|
800ec7e: 781b ldrb r3, [r3, #0]
|
|
800ec80: b2db uxtb r3, r3
|
|
800ec82: 70fb strb r3, [r7, #3]
|
|
|
|
/* Use the same mask on the maximum system call priority. */
|
|
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
|
800ec84: 78fb ldrb r3, [r7, #3]
|
|
800ec86: b2db uxtb r3, r3
|
|
800ec88: f003 0350 and.w r3, r3, #80 @ 0x50
|
|
800ec8c: b2da uxtb r2, r3
|
|
800ec8e: 4b31 ldr r3, [pc, #196] @ (800ed54 <xPortStartScheduler+0x134>)
|
|
800ec90: 701a strb r2, [r3, #0]
|
|
|
|
/* Calculate the maximum acceptable priority group value for the number
|
|
of bits read back. */
|
|
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
|
800ec92: 4b31 ldr r3, [pc, #196] @ (800ed58 <xPortStartScheduler+0x138>)
|
|
800ec94: 2207 movs r2, #7
|
|
800ec96: 601a str r2, [r3, #0]
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
800ec98: e009 b.n 800ecae <xPortStartScheduler+0x8e>
|
|
{
|
|
ulMaxPRIGROUPValue--;
|
|
800ec9a: 4b2f ldr r3, [pc, #188] @ (800ed58 <xPortStartScheduler+0x138>)
|
|
800ec9c: 681b ldr r3, [r3, #0]
|
|
800ec9e: 3b01 subs r3, #1
|
|
800eca0: 4a2d ldr r2, [pc, #180] @ (800ed58 <xPortStartScheduler+0x138>)
|
|
800eca2: 6013 str r3, [r2, #0]
|
|
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
|
|
800eca4: 78fb ldrb r3, [r7, #3]
|
|
800eca6: b2db uxtb r3, r3
|
|
800eca8: 005b lsls r3, r3, #1
|
|
800ecaa: b2db uxtb r3, r3
|
|
800ecac: 70fb strb r3, [r7, #3]
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
800ecae: 78fb ldrb r3, [r7, #3]
|
|
800ecb0: b2db uxtb r3, r3
|
|
800ecb2: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800ecb6: 2b80 cmp r3, #128 @ 0x80
|
|
800ecb8: d0ef beq.n 800ec9a <xPortStartScheduler+0x7a>
|
|
#ifdef configPRIO_BITS
|
|
{
|
|
/* Check the FreeRTOS configuration that defines the number of
|
|
priority bits matches the number of priority bits actually queried
|
|
from the hardware. */
|
|
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
|
|
800ecba: 4b27 ldr r3, [pc, #156] @ (800ed58 <xPortStartScheduler+0x138>)
|
|
800ecbc: 681b ldr r3, [r3, #0]
|
|
800ecbe: f1c3 0307 rsb r3, r3, #7
|
|
800ecc2: 2b04 cmp r3, #4
|
|
800ecc4: d00b beq.n 800ecde <xPortStartScheduler+0xbe>
|
|
__asm volatile
|
|
800ecc6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ecca: f383 8811 msr BASEPRI, r3
|
|
800ecce: f3bf 8f6f isb sy
|
|
800ecd2: f3bf 8f4f dsb sy
|
|
800ecd6: 60bb str r3, [r7, #8]
|
|
}
|
|
800ecd8: bf00 nop
|
|
800ecda: bf00 nop
|
|
800ecdc: e7fd b.n 800ecda <xPortStartScheduler+0xba>
|
|
}
|
|
#endif
|
|
|
|
/* Shift the priority group value back to its position within the AIRCR
|
|
register. */
|
|
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
|
|
800ecde: 4b1e ldr r3, [pc, #120] @ (800ed58 <xPortStartScheduler+0x138>)
|
|
800ece0: 681b ldr r3, [r3, #0]
|
|
800ece2: 021b lsls r3, r3, #8
|
|
800ece4: 4a1c ldr r2, [pc, #112] @ (800ed58 <xPortStartScheduler+0x138>)
|
|
800ece6: 6013 str r3, [r2, #0]
|
|
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
|
|
800ece8: 4b1b ldr r3, [pc, #108] @ (800ed58 <xPortStartScheduler+0x138>)
|
|
800ecea: 681b ldr r3, [r3, #0]
|
|
800ecec: f403 63e0 and.w r3, r3, #1792 @ 0x700
|
|
800ecf0: 4a19 ldr r2, [pc, #100] @ (800ed58 <xPortStartScheduler+0x138>)
|
|
800ecf2: 6013 str r3, [r2, #0]
|
|
|
|
/* Restore the clobbered interrupt priority register to its original
|
|
value. */
|
|
*pucFirstUserPriorityRegister = ulOriginalPriority;
|
|
800ecf4: 687b ldr r3, [r7, #4]
|
|
800ecf6: b2da uxtb r2, r3
|
|
800ecf8: 697b ldr r3, [r7, #20]
|
|
800ecfa: 701a strb r2, [r3, #0]
|
|
}
|
|
#endif /* conifgASSERT_DEFINED */
|
|
|
|
/* Make PendSV and SysTick the lowest priority interrupts. */
|
|
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
|
|
800ecfc: 4b17 ldr r3, [pc, #92] @ (800ed5c <xPortStartScheduler+0x13c>)
|
|
800ecfe: 681b ldr r3, [r3, #0]
|
|
800ed00: 4a16 ldr r2, [pc, #88] @ (800ed5c <xPortStartScheduler+0x13c>)
|
|
800ed02: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
800ed06: 6013 str r3, [r2, #0]
|
|
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
|
|
800ed08: 4b14 ldr r3, [pc, #80] @ (800ed5c <xPortStartScheduler+0x13c>)
|
|
800ed0a: 681b ldr r3, [r3, #0]
|
|
800ed0c: 4a13 ldr r2, [pc, #76] @ (800ed5c <xPortStartScheduler+0x13c>)
|
|
800ed0e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000
|
|
800ed12: 6013 str r3, [r2, #0]
|
|
|
|
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
|
here already. */
|
|
vPortSetupTimerInterrupt();
|
|
800ed14: f000 f8da bl 800eecc <vPortSetupTimerInterrupt>
|
|
|
|
/* Initialise the critical nesting count ready for the first task. */
|
|
uxCriticalNesting = 0;
|
|
800ed18: 4b11 ldr r3, [pc, #68] @ (800ed60 <xPortStartScheduler+0x140>)
|
|
800ed1a: 2200 movs r2, #0
|
|
800ed1c: 601a str r2, [r3, #0]
|
|
|
|
/* Ensure the VFP is enabled - it should be anyway. */
|
|
vPortEnableVFP();
|
|
800ed1e: f000 f8f9 bl 800ef14 <vPortEnableVFP>
|
|
|
|
/* Lazy save always. */
|
|
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
|
|
800ed22: 4b10 ldr r3, [pc, #64] @ (800ed64 <xPortStartScheduler+0x144>)
|
|
800ed24: 681b ldr r3, [r3, #0]
|
|
800ed26: 4a0f ldr r2, [pc, #60] @ (800ed64 <xPortStartScheduler+0x144>)
|
|
800ed28: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000
|
|
800ed2c: 6013 str r3, [r2, #0]
|
|
|
|
/* Start the first task. */
|
|
prvPortStartFirstTask();
|
|
800ed2e: f7ff ff63 bl 800ebf8 <prvPortStartFirstTask>
|
|
exit error function to prevent compiler warnings about a static function
|
|
not being called in the case that the application writer overrides this
|
|
functionality by defining configTASK_RETURN_ADDRESS. Call
|
|
vTaskSwitchContext() so link time optimisation does not remove the
|
|
symbol. */
|
|
vTaskSwitchContext();
|
|
800ed32: f7fe fe3b bl 800d9ac <vTaskSwitchContext>
|
|
prvTaskExitError();
|
|
800ed36: f7ff ff1b bl 800eb70 <prvTaskExitError>
|
|
|
|
/* Should not get here! */
|
|
return 0;
|
|
800ed3a: 2300 movs r3, #0
|
|
}
|
|
800ed3c: 4618 mov r0, r3
|
|
800ed3e: 3718 adds r7, #24
|
|
800ed40: 46bd mov sp, r7
|
|
800ed42: bd80 pop {r7, pc}
|
|
800ed44: e000ed00 .word 0xe000ed00
|
|
800ed48: 410fc271 .word 0x410fc271
|
|
800ed4c: 410fc270 .word 0x410fc270
|
|
800ed50: e000e400 .word 0xe000e400
|
|
800ed54: 200029ac .word 0x200029ac
|
|
800ed58: 200029b0 .word 0x200029b0
|
|
800ed5c: e000ed20 .word 0xe000ed20
|
|
800ed60: 200000d0 .word 0x200000d0
|
|
800ed64: e000ef34 .word 0xe000ef34
|
|
|
|
0800ed68 <vPortEnterCritical>:
|
|
configASSERT( uxCriticalNesting == 1000UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
800ed68: b480 push {r7}
|
|
800ed6a: b083 sub sp, #12
|
|
800ed6c: af00 add r7, sp, #0
|
|
__asm volatile
|
|
800ed6e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ed72: f383 8811 msr BASEPRI, r3
|
|
800ed76: f3bf 8f6f isb sy
|
|
800ed7a: f3bf 8f4f dsb sy
|
|
800ed7e: 607b str r3, [r7, #4]
|
|
}
|
|
800ed80: bf00 nop
|
|
portDISABLE_INTERRUPTS();
|
|
uxCriticalNesting++;
|
|
800ed82: 4b10 ldr r3, [pc, #64] @ (800edc4 <vPortEnterCritical+0x5c>)
|
|
800ed84: 681b ldr r3, [r3, #0]
|
|
800ed86: 3301 adds r3, #1
|
|
800ed88: 4a0e ldr r2, [pc, #56] @ (800edc4 <vPortEnterCritical+0x5c>)
|
|
800ed8a: 6013 str r3, [r2, #0]
|
|
/* This is not the interrupt safe version of the enter critical function so
|
|
assert() if it is being called from an interrupt context. Only API
|
|
functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
the critical nesting count is 1 to protect against recursive calls if the
|
|
assert function also uses a critical section. */
|
|
if( uxCriticalNesting == 1 )
|
|
800ed8c: 4b0d ldr r3, [pc, #52] @ (800edc4 <vPortEnterCritical+0x5c>)
|
|
800ed8e: 681b ldr r3, [r3, #0]
|
|
800ed90: 2b01 cmp r3, #1
|
|
800ed92: d110 bne.n 800edb6 <vPortEnterCritical+0x4e>
|
|
{
|
|
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
|
|
800ed94: 4b0c ldr r3, [pc, #48] @ (800edc8 <vPortEnterCritical+0x60>)
|
|
800ed96: 681b ldr r3, [r3, #0]
|
|
800ed98: b2db uxtb r3, r3
|
|
800ed9a: 2b00 cmp r3, #0
|
|
800ed9c: d00b beq.n 800edb6 <vPortEnterCritical+0x4e>
|
|
__asm volatile
|
|
800ed9e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800eda2: f383 8811 msr BASEPRI, r3
|
|
800eda6: f3bf 8f6f isb sy
|
|
800edaa: f3bf 8f4f dsb sy
|
|
800edae: 603b str r3, [r7, #0]
|
|
}
|
|
800edb0: bf00 nop
|
|
800edb2: bf00 nop
|
|
800edb4: e7fd b.n 800edb2 <vPortEnterCritical+0x4a>
|
|
}
|
|
}
|
|
800edb6: bf00 nop
|
|
800edb8: 370c adds r7, #12
|
|
800edba: 46bd mov sp, r7
|
|
800edbc: f85d 7b04 ldr.w r7, [sp], #4
|
|
800edc0: 4770 bx lr
|
|
800edc2: bf00 nop
|
|
800edc4: 200000d0 .word 0x200000d0
|
|
800edc8: e000ed04 .word 0xe000ed04
|
|
|
|
0800edcc <vPortExitCritical>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
800edcc: b480 push {r7}
|
|
800edce: b083 sub sp, #12
|
|
800edd0: af00 add r7, sp, #0
|
|
configASSERT( uxCriticalNesting );
|
|
800edd2: 4b12 ldr r3, [pc, #72] @ (800ee1c <vPortExitCritical+0x50>)
|
|
800edd4: 681b ldr r3, [r3, #0]
|
|
800edd6: 2b00 cmp r3, #0
|
|
800edd8: d10b bne.n 800edf2 <vPortExitCritical+0x26>
|
|
__asm volatile
|
|
800edda: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800edde: f383 8811 msr BASEPRI, r3
|
|
800ede2: f3bf 8f6f isb sy
|
|
800ede6: f3bf 8f4f dsb sy
|
|
800edea: 607b str r3, [r7, #4]
|
|
}
|
|
800edec: bf00 nop
|
|
800edee: bf00 nop
|
|
800edf0: e7fd b.n 800edee <vPortExitCritical+0x22>
|
|
uxCriticalNesting--;
|
|
800edf2: 4b0a ldr r3, [pc, #40] @ (800ee1c <vPortExitCritical+0x50>)
|
|
800edf4: 681b ldr r3, [r3, #0]
|
|
800edf6: 3b01 subs r3, #1
|
|
800edf8: 4a08 ldr r2, [pc, #32] @ (800ee1c <vPortExitCritical+0x50>)
|
|
800edfa: 6013 str r3, [r2, #0]
|
|
if( uxCriticalNesting == 0 )
|
|
800edfc: 4b07 ldr r3, [pc, #28] @ (800ee1c <vPortExitCritical+0x50>)
|
|
800edfe: 681b ldr r3, [r3, #0]
|
|
800ee00: 2b00 cmp r3, #0
|
|
800ee02: d105 bne.n 800ee10 <vPortExitCritical+0x44>
|
|
800ee04: 2300 movs r3, #0
|
|
800ee06: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
800ee08: 683b ldr r3, [r7, #0]
|
|
800ee0a: f383 8811 msr BASEPRI, r3
|
|
}
|
|
800ee0e: bf00 nop
|
|
{
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
}
|
|
800ee10: bf00 nop
|
|
800ee12: 370c adds r7, #12
|
|
800ee14: 46bd mov sp, r7
|
|
800ee16: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ee1a: 4770 bx lr
|
|
800ee1c: 200000d0 .word 0x200000d0
|
|
|
|
0800ee20 <PendSV_Handler>:
|
|
|
|
void xPortPendSVHandler( void )
|
|
{
|
|
/* This is a naked function. */
|
|
|
|
__asm volatile
|
|
800ee20: f3ef 8009 mrs r0, PSP
|
|
800ee24: f3bf 8f6f isb sy
|
|
800ee28: 4b15 ldr r3, [pc, #84] @ (800ee80 <pxCurrentTCBConst>)
|
|
800ee2a: 681a ldr r2, [r3, #0]
|
|
800ee2c: f01e 0f10 tst.w lr, #16
|
|
800ee30: bf08 it eq
|
|
800ee32: ed20 8a10 vstmdbeq r0!, {s16-s31}
|
|
800ee36: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800ee3a: 6010 str r0, [r2, #0]
|
|
800ee3c: e92d 0009 stmdb sp!, {r0, r3}
|
|
800ee40: f04f 0050 mov.w r0, #80 @ 0x50
|
|
800ee44: f380 8811 msr BASEPRI, r0
|
|
800ee48: f3bf 8f4f dsb sy
|
|
800ee4c: f3bf 8f6f isb sy
|
|
800ee50: f7fe fdac bl 800d9ac <vTaskSwitchContext>
|
|
800ee54: f04f 0000 mov.w r0, #0
|
|
800ee58: f380 8811 msr BASEPRI, r0
|
|
800ee5c: bc09 pop {r0, r3}
|
|
800ee5e: 6819 ldr r1, [r3, #0]
|
|
800ee60: 6808 ldr r0, [r1, #0]
|
|
800ee62: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800ee66: f01e 0f10 tst.w lr, #16
|
|
800ee6a: bf08 it eq
|
|
800ee6c: ecb0 8a10 vldmiaeq r0!, {s16-s31}
|
|
800ee70: f380 8809 msr PSP, r0
|
|
800ee74: f3bf 8f6f isb sy
|
|
800ee78: 4770 bx lr
|
|
800ee7a: bf00 nop
|
|
800ee7c: f3af 8000 nop.w
|
|
|
|
0800ee80 <pxCurrentTCBConst>:
|
|
800ee80: 20002380 .word 0x20002380
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
|
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
|
|
);
|
|
}
|
|
800ee84: bf00 nop
|
|
800ee86: bf00 nop
|
|
|
|
0800ee88 <xPortSysTickHandler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void xPortSysTickHandler( void )
|
|
{
|
|
800ee88: b580 push {r7, lr}
|
|
800ee8a: b082 sub sp, #8
|
|
800ee8c: af00 add r7, sp, #0
|
|
__asm volatile
|
|
800ee8e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ee92: f383 8811 msr BASEPRI, r3
|
|
800ee96: f3bf 8f6f isb sy
|
|
800ee9a: f3bf 8f4f dsb sy
|
|
800ee9e: 607b str r3, [r7, #4]
|
|
}
|
|
800eea0: bf00 nop
|
|
save and then restore the interrupt mask value as its value is already
|
|
known. */
|
|
portDISABLE_INTERRUPTS();
|
|
{
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
800eea2: f7fe fcc9 bl 800d838 <xTaskIncrementTick>
|
|
800eea6: 4603 mov r3, r0
|
|
800eea8: 2b00 cmp r3, #0
|
|
800eeaa: d003 beq.n 800eeb4 <xPortSysTickHandler+0x2c>
|
|
{
|
|
/* A context switch is required. Context switching is performed in
|
|
the PendSV interrupt. Pend the PendSV interrupt. */
|
|
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
|
800eeac: 4b06 ldr r3, [pc, #24] @ (800eec8 <xPortSysTickHandler+0x40>)
|
|
800eeae: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800eeb2: 601a str r2, [r3, #0]
|
|
800eeb4: 2300 movs r3, #0
|
|
800eeb6: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
800eeb8: 683b ldr r3, [r7, #0]
|
|
800eeba: f383 8811 msr BASEPRI, r3
|
|
}
|
|
800eebe: bf00 nop
|
|
}
|
|
}
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
800eec0: bf00 nop
|
|
800eec2: 3708 adds r7, #8
|
|
800eec4: 46bd mov sp, r7
|
|
800eec6: bd80 pop {r7, pc}
|
|
800eec8: e000ed04 .word 0xe000ed04
|
|
|
|
0800eecc <vPortSetupTimerInterrupt>:
|
|
/*
|
|
* Setup the systick timer to generate the tick interrupts at the required
|
|
* frequency.
|
|
*/
|
|
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
|
|
{
|
|
800eecc: b480 push {r7}
|
|
800eece: af00 add r7, sp, #0
|
|
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
|
|
}
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
|
|
/* Stop and clear the SysTick. */
|
|
portNVIC_SYSTICK_CTRL_REG = 0UL;
|
|
800eed0: 4b0b ldr r3, [pc, #44] @ (800ef00 <vPortSetupTimerInterrupt+0x34>)
|
|
800eed2: 2200 movs r2, #0
|
|
800eed4: 601a str r2, [r3, #0]
|
|
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
800eed6: 4b0b ldr r3, [pc, #44] @ (800ef04 <vPortSetupTimerInterrupt+0x38>)
|
|
800eed8: 2200 movs r2, #0
|
|
800eeda: 601a str r2, [r3, #0]
|
|
|
|
/* Configure SysTick to interrupt at the requested rate. */
|
|
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
|
800eedc: 4b0a ldr r3, [pc, #40] @ (800ef08 <vPortSetupTimerInterrupt+0x3c>)
|
|
800eede: 681b ldr r3, [r3, #0]
|
|
800eee0: 4a0a ldr r2, [pc, #40] @ (800ef0c <vPortSetupTimerInterrupt+0x40>)
|
|
800eee2: fba2 2303 umull r2, r3, r2, r3
|
|
800eee6: 099b lsrs r3, r3, #6
|
|
800eee8: 4a09 ldr r2, [pc, #36] @ (800ef10 <vPortSetupTimerInterrupt+0x44>)
|
|
800eeea: 3b01 subs r3, #1
|
|
800eeec: 6013 str r3, [r2, #0]
|
|
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
|
|
800eeee: 4b04 ldr r3, [pc, #16] @ (800ef00 <vPortSetupTimerInterrupt+0x34>)
|
|
800eef0: 2207 movs r2, #7
|
|
800eef2: 601a str r2, [r3, #0]
|
|
}
|
|
800eef4: bf00 nop
|
|
800eef6: 46bd mov sp, r7
|
|
800eef8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800eefc: 4770 bx lr
|
|
800eefe: bf00 nop
|
|
800ef00: e000e010 .word 0xe000e010
|
|
800ef04: e000e018 .word 0xe000e018
|
|
800ef08: 200000c4 .word 0x200000c4
|
|
800ef0c: 10624dd3 .word 0x10624dd3
|
|
800ef10: e000e014 .word 0xe000e014
|
|
|
|
0800ef14 <vPortEnableVFP>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/* This is a naked function. */
|
|
static void vPortEnableVFP( void )
|
|
{
|
|
__asm volatile
|
|
800ef14: f8df 000c ldr.w r0, [pc, #12] @ 800ef24 <vPortEnableVFP+0x10>
|
|
800ef18: 6801 ldr r1, [r0, #0]
|
|
800ef1a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
800ef1e: 6001 str r1, [r0, #0]
|
|
800ef20: 4770 bx lr
|
|
" \n"
|
|
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
|
|
" str r1, [r0] \n"
|
|
" bx r14 "
|
|
);
|
|
}
|
|
800ef22: bf00 nop
|
|
800ef24: e000ed88 .word 0xe000ed88
|
|
|
|
0800ef28 <vPortValidateInterruptPriority>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
800ef28: b480 push {r7}
|
|
800ef2a: b085 sub sp, #20
|
|
800ef2c: af00 add r7, sp, #0
|
|
uint32_t ulCurrentInterrupt;
|
|
uint8_t ucCurrentPriority;
|
|
|
|
/* Obtain the number of the currently executing interrupt. */
|
|
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
|
|
800ef2e: f3ef 8305 mrs r3, IPSR
|
|
800ef32: 60fb str r3, [r7, #12]
|
|
|
|
/* Is the interrupt number a user defined interrupt? */
|
|
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
|
|
800ef34: 68fb ldr r3, [r7, #12]
|
|
800ef36: 2b0f cmp r3, #15
|
|
800ef38: d915 bls.n 800ef66 <vPortValidateInterruptPriority+0x3e>
|
|
{
|
|
/* Look up the interrupt's priority. */
|
|
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
|
800ef3a: 4a18 ldr r2, [pc, #96] @ (800ef9c <vPortValidateInterruptPriority+0x74>)
|
|
800ef3c: 68fb ldr r3, [r7, #12]
|
|
800ef3e: 4413 add r3, r2
|
|
800ef40: 781b ldrb r3, [r3, #0]
|
|
800ef42: 72fb strb r3, [r7, #11]
|
|
interrupt entry is as fast and simple as possible.
|
|
|
|
The following links provide detailed information:
|
|
http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
|
http://www.freertos.org/FAQHelp.html */
|
|
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
|
800ef44: 4b16 ldr r3, [pc, #88] @ (800efa0 <vPortValidateInterruptPriority+0x78>)
|
|
800ef46: 781b ldrb r3, [r3, #0]
|
|
800ef48: 7afa ldrb r2, [r7, #11]
|
|
800ef4a: 429a cmp r2, r3
|
|
800ef4c: d20b bcs.n 800ef66 <vPortValidateInterruptPriority+0x3e>
|
|
__asm volatile
|
|
800ef4e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ef52: f383 8811 msr BASEPRI, r3
|
|
800ef56: f3bf 8f6f isb sy
|
|
800ef5a: f3bf 8f4f dsb sy
|
|
800ef5e: 607b str r3, [r7, #4]
|
|
}
|
|
800ef60: bf00 nop
|
|
800ef62: bf00 nop
|
|
800ef64: e7fd b.n 800ef62 <vPortValidateInterruptPriority+0x3a>
|
|
configuration then the correct setting can be achieved on all Cortex-M
|
|
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
|
scheduler. Note however that some vendor specific peripheral libraries
|
|
assume a non-zero priority group setting, in which cases using a value
|
|
of zero will result in unpredictable behaviour. */
|
|
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
|
800ef66: 4b0f ldr r3, [pc, #60] @ (800efa4 <vPortValidateInterruptPriority+0x7c>)
|
|
800ef68: 681b ldr r3, [r3, #0]
|
|
800ef6a: f403 62e0 and.w r2, r3, #1792 @ 0x700
|
|
800ef6e: 4b0e ldr r3, [pc, #56] @ (800efa8 <vPortValidateInterruptPriority+0x80>)
|
|
800ef70: 681b ldr r3, [r3, #0]
|
|
800ef72: 429a cmp r2, r3
|
|
800ef74: d90b bls.n 800ef8e <vPortValidateInterruptPriority+0x66>
|
|
__asm volatile
|
|
800ef76: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ef7a: f383 8811 msr BASEPRI, r3
|
|
800ef7e: f3bf 8f6f isb sy
|
|
800ef82: f3bf 8f4f dsb sy
|
|
800ef86: 603b str r3, [r7, #0]
|
|
}
|
|
800ef88: bf00 nop
|
|
800ef8a: bf00 nop
|
|
800ef8c: e7fd b.n 800ef8a <vPortValidateInterruptPriority+0x62>
|
|
}
|
|
800ef8e: bf00 nop
|
|
800ef90: 3714 adds r7, #20
|
|
800ef92: 46bd mov sp, r7
|
|
800ef94: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ef98: 4770 bx lr
|
|
800ef9a: bf00 nop
|
|
800ef9c: e000e3f0 .word 0xe000e3f0
|
|
800efa0: 200029ac .word 0x200029ac
|
|
800efa4: e000ed0c .word 0xe000ed0c
|
|
800efa8: 200029b0 .word 0x200029b0
|
|
|
|
0800efac <pvPortMalloc>:
|
|
static size_t xBlockAllocatedBit = 0;
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void *pvPortMalloc( size_t xWantedSize )
|
|
{
|
|
800efac: b580 push {r7, lr}
|
|
800efae: b08a sub sp, #40 @ 0x28
|
|
800efb0: af00 add r7, sp, #0
|
|
800efb2: 6078 str r0, [r7, #4]
|
|
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
|
|
void *pvReturn = NULL;
|
|
800efb4: 2300 movs r3, #0
|
|
800efb6: 61fb str r3, [r7, #28]
|
|
|
|
vTaskSuspendAll();
|
|
800efb8: f7fe fb82 bl 800d6c0 <vTaskSuspendAll>
|
|
{
|
|
/* If this is the first call to malloc then the heap will require
|
|
initialisation to setup the list of free blocks. */
|
|
if( pxEnd == NULL )
|
|
800efbc: 4b5c ldr r3, [pc, #368] @ (800f130 <pvPortMalloc+0x184>)
|
|
800efbe: 681b ldr r3, [r3, #0]
|
|
800efc0: 2b00 cmp r3, #0
|
|
800efc2: d101 bne.n 800efc8 <pvPortMalloc+0x1c>
|
|
{
|
|
prvHeapInit();
|
|
800efc4: f000 f924 bl 800f210 <prvHeapInit>
|
|
|
|
/* Check the requested block size is not so large that the top bit is
|
|
set. The top bit of the block size member of the BlockLink_t structure
|
|
is used to determine who owns the block - the application or the
|
|
kernel, so it must be free. */
|
|
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
|
|
800efc8: 4b5a ldr r3, [pc, #360] @ (800f134 <pvPortMalloc+0x188>)
|
|
800efca: 681a ldr r2, [r3, #0]
|
|
800efcc: 687b ldr r3, [r7, #4]
|
|
800efce: 4013 ands r3, r2
|
|
800efd0: 2b00 cmp r3, #0
|
|
800efd2: f040 8095 bne.w 800f100 <pvPortMalloc+0x154>
|
|
{
|
|
/* The wanted size is increased so it can contain a BlockLink_t
|
|
structure in addition to the requested amount of bytes. */
|
|
if( xWantedSize > 0 )
|
|
800efd6: 687b ldr r3, [r7, #4]
|
|
800efd8: 2b00 cmp r3, #0
|
|
800efda: d01e beq.n 800f01a <pvPortMalloc+0x6e>
|
|
{
|
|
xWantedSize += xHeapStructSize;
|
|
800efdc: 2208 movs r2, #8
|
|
800efde: 687b ldr r3, [r7, #4]
|
|
800efe0: 4413 add r3, r2
|
|
800efe2: 607b str r3, [r7, #4]
|
|
|
|
/* Ensure that blocks are always aligned to the required number
|
|
of bytes. */
|
|
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
|
|
800efe4: 687b ldr r3, [r7, #4]
|
|
800efe6: f003 0307 and.w r3, r3, #7
|
|
800efea: 2b00 cmp r3, #0
|
|
800efec: d015 beq.n 800f01a <pvPortMalloc+0x6e>
|
|
{
|
|
/* Byte alignment required. */
|
|
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
|
|
800efee: 687b ldr r3, [r7, #4]
|
|
800eff0: f023 0307 bic.w r3, r3, #7
|
|
800eff4: 3308 adds r3, #8
|
|
800eff6: 607b str r3, [r7, #4]
|
|
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
800eff8: 687b ldr r3, [r7, #4]
|
|
800effa: f003 0307 and.w r3, r3, #7
|
|
800effe: 2b00 cmp r3, #0
|
|
800f000: d00b beq.n 800f01a <pvPortMalloc+0x6e>
|
|
__asm volatile
|
|
800f002: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800f006: f383 8811 msr BASEPRI, r3
|
|
800f00a: f3bf 8f6f isb sy
|
|
800f00e: f3bf 8f4f dsb sy
|
|
800f012: 617b str r3, [r7, #20]
|
|
}
|
|
800f014: bf00 nop
|
|
800f016: bf00 nop
|
|
800f018: e7fd b.n 800f016 <pvPortMalloc+0x6a>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
|
|
800f01a: 687b ldr r3, [r7, #4]
|
|
800f01c: 2b00 cmp r3, #0
|
|
800f01e: d06f beq.n 800f100 <pvPortMalloc+0x154>
|
|
800f020: 4b45 ldr r3, [pc, #276] @ (800f138 <pvPortMalloc+0x18c>)
|
|
800f022: 681b ldr r3, [r3, #0]
|
|
800f024: 687a ldr r2, [r7, #4]
|
|
800f026: 429a cmp r2, r3
|
|
800f028: d86a bhi.n 800f100 <pvPortMalloc+0x154>
|
|
{
|
|
/* Traverse the list from the start (lowest address) block until
|
|
one of adequate size is found. */
|
|
pxPreviousBlock = &xStart;
|
|
800f02a: 4b44 ldr r3, [pc, #272] @ (800f13c <pvPortMalloc+0x190>)
|
|
800f02c: 623b str r3, [r7, #32]
|
|
pxBlock = xStart.pxNextFreeBlock;
|
|
800f02e: 4b43 ldr r3, [pc, #268] @ (800f13c <pvPortMalloc+0x190>)
|
|
800f030: 681b ldr r3, [r3, #0]
|
|
800f032: 627b str r3, [r7, #36] @ 0x24
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
|
800f034: e004 b.n 800f040 <pvPortMalloc+0x94>
|
|
{
|
|
pxPreviousBlock = pxBlock;
|
|
800f036: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f038: 623b str r3, [r7, #32]
|
|
pxBlock = pxBlock->pxNextFreeBlock;
|
|
800f03a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f03c: 681b ldr r3, [r3, #0]
|
|
800f03e: 627b str r3, [r7, #36] @ 0x24
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
|
800f040: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f042: 685b ldr r3, [r3, #4]
|
|
800f044: 687a ldr r2, [r7, #4]
|
|
800f046: 429a cmp r2, r3
|
|
800f048: d903 bls.n 800f052 <pvPortMalloc+0xa6>
|
|
800f04a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f04c: 681b ldr r3, [r3, #0]
|
|
800f04e: 2b00 cmp r3, #0
|
|
800f050: d1f1 bne.n 800f036 <pvPortMalloc+0x8a>
|
|
}
|
|
|
|
/* If the end marker was reached then a block of adequate size
|
|
was not found. */
|
|
if( pxBlock != pxEnd )
|
|
800f052: 4b37 ldr r3, [pc, #220] @ (800f130 <pvPortMalloc+0x184>)
|
|
800f054: 681b ldr r3, [r3, #0]
|
|
800f056: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800f058: 429a cmp r2, r3
|
|
800f05a: d051 beq.n 800f100 <pvPortMalloc+0x154>
|
|
{
|
|
/* Return the memory space pointed to - jumping over the
|
|
BlockLink_t structure at its start. */
|
|
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
|
|
800f05c: 6a3b ldr r3, [r7, #32]
|
|
800f05e: 681b ldr r3, [r3, #0]
|
|
800f060: 2208 movs r2, #8
|
|
800f062: 4413 add r3, r2
|
|
800f064: 61fb str r3, [r7, #28]
|
|
|
|
/* This block is being returned for use so must be taken out
|
|
of the list of free blocks. */
|
|
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
|
|
800f066: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f068: 681a ldr r2, [r3, #0]
|
|
800f06a: 6a3b ldr r3, [r7, #32]
|
|
800f06c: 601a str r2, [r3, #0]
|
|
|
|
/* If the block is larger than required it can be split into
|
|
two. */
|
|
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
|
|
800f06e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f070: 685a ldr r2, [r3, #4]
|
|
800f072: 687b ldr r3, [r7, #4]
|
|
800f074: 1ad2 subs r2, r2, r3
|
|
800f076: 2308 movs r3, #8
|
|
800f078: 005b lsls r3, r3, #1
|
|
800f07a: 429a cmp r2, r3
|
|
800f07c: d920 bls.n 800f0c0 <pvPortMalloc+0x114>
|
|
{
|
|
/* This block is to be split into two. Create a new
|
|
block following the number of bytes requested. The void
|
|
cast is used to prevent byte alignment warnings from the
|
|
compiler. */
|
|
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
|
|
800f07e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800f080: 687b ldr r3, [r7, #4]
|
|
800f082: 4413 add r3, r2
|
|
800f084: 61bb str r3, [r7, #24]
|
|
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
800f086: 69bb ldr r3, [r7, #24]
|
|
800f088: f003 0307 and.w r3, r3, #7
|
|
800f08c: 2b00 cmp r3, #0
|
|
800f08e: d00b beq.n 800f0a8 <pvPortMalloc+0xfc>
|
|
__asm volatile
|
|
800f090: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800f094: f383 8811 msr BASEPRI, r3
|
|
800f098: f3bf 8f6f isb sy
|
|
800f09c: f3bf 8f4f dsb sy
|
|
800f0a0: 613b str r3, [r7, #16]
|
|
}
|
|
800f0a2: bf00 nop
|
|
800f0a4: bf00 nop
|
|
800f0a6: e7fd b.n 800f0a4 <pvPortMalloc+0xf8>
|
|
|
|
/* Calculate the sizes of two blocks split from the
|
|
single block. */
|
|
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
|
|
800f0a8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f0aa: 685a ldr r2, [r3, #4]
|
|
800f0ac: 687b ldr r3, [r7, #4]
|
|
800f0ae: 1ad2 subs r2, r2, r3
|
|
800f0b0: 69bb ldr r3, [r7, #24]
|
|
800f0b2: 605a str r2, [r3, #4]
|
|
pxBlock->xBlockSize = xWantedSize;
|
|
800f0b4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f0b6: 687a ldr r2, [r7, #4]
|
|
800f0b8: 605a str r2, [r3, #4]
|
|
|
|
/* Insert the new block into the list of free blocks. */
|
|
prvInsertBlockIntoFreeList( pxNewBlockLink );
|
|
800f0ba: 69b8 ldr r0, [r7, #24]
|
|
800f0bc: f000 f90a bl 800f2d4 <prvInsertBlockIntoFreeList>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
xFreeBytesRemaining -= pxBlock->xBlockSize;
|
|
800f0c0: 4b1d ldr r3, [pc, #116] @ (800f138 <pvPortMalloc+0x18c>)
|
|
800f0c2: 681a ldr r2, [r3, #0]
|
|
800f0c4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f0c6: 685b ldr r3, [r3, #4]
|
|
800f0c8: 1ad3 subs r3, r2, r3
|
|
800f0ca: 4a1b ldr r2, [pc, #108] @ (800f138 <pvPortMalloc+0x18c>)
|
|
800f0cc: 6013 str r3, [r2, #0]
|
|
|
|
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
|
|
800f0ce: 4b1a ldr r3, [pc, #104] @ (800f138 <pvPortMalloc+0x18c>)
|
|
800f0d0: 681a ldr r2, [r3, #0]
|
|
800f0d2: 4b1b ldr r3, [pc, #108] @ (800f140 <pvPortMalloc+0x194>)
|
|
800f0d4: 681b ldr r3, [r3, #0]
|
|
800f0d6: 429a cmp r2, r3
|
|
800f0d8: d203 bcs.n 800f0e2 <pvPortMalloc+0x136>
|
|
{
|
|
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
|
|
800f0da: 4b17 ldr r3, [pc, #92] @ (800f138 <pvPortMalloc+0x18c>)
|
|
800f0dc: 681b ldr r3, [r3, #0]
|
|
800f0de: 4a18 ldr r2, [pc, #96] @ (800f140 <pvPortMalloc+0x194>)
|
|
800f0e0: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* The block is being returned - it is allocated and owned
|
|
by the application and has no "next" block. */
|
|
pxBlock->xBlockSize |= xBlockAllocatedBit;
|
|
800f0e2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f0e4: 685a ldr r2, [r3, #4]
|
|
800f0e6: 4b13 ldr r3, [pc, #76] @ (800f134 <pvPortMalloc+0x188>)
|
|
800f0e8: 681b ldr r3, [r3, #0]
|
|
800f0ea: 431a orrs r2, r3
|
|
800f0ec: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f0ee: 605a str r2, [r3, #4]
|
|
pxBlock->pxNextFreeBlock = NULL;
|
|
800f0f0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f0f2: 2200 movs r2, #0
|
|
800f0f4: 601a str r2, [r3, #0]
|
|
xNumberOfSuccessfulAllocations++;
|
|
800f0f6: 4b13 ldr r3, [pc, #76] @ (800f144 <pvPortMalloc+0x198>)
|
|
800f0f8: 681b ldr r3, [r3, #0]
|
|
800f0fa: 3301 adds r3, #1
|
|
800f0fc: 4a11 ldr r2, [pc, #68] @ (800f144 <pvPortMalloc+0x198>)
|
|
800f0fe: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
traceMALLOC( pvReturn, xWantedSize );
|
|
}
|
|
( void ) xTaskResumeAll();
|
|
800f100: f7fe faec bl 800d6dc <xTaskResumeAll>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
800f104: 69fb ldr r3, [r7, #28]
|
|
800f106: f003 0307 and.w r3, r3, #7
|
|
800f10a: 2b00 cmp r3, #0
|
|
800f10c: d00b beq.n 800f126 <pvPortMalloc+0x17a>
|
|
__asm volatile
|
|
800f10e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800f112: f383 8811 msr BASEPRI, r3
|
|
800f116: f3bf 8f6f isb sy
|
|
800f11a: f3bf 8f4f dsb sy
|
|
800f11e: 60fb str r3, [r7, #12]
|
|
}
|
|
800f120: bf00 nop
|
|
800f122: bf00 nop
|
|
800f124: e7fd b.n 800f122 <pvPortMalloc+0x176>
|
|
return pvReturn;
|
|
800f126: 69fb ldr r3, [r7, #28]
|
|
}
|
|
800f128: 4618 mov r0, r3
|
|
800f12a: 3728 adds r7, #40 @ 0x28
|
|
800f12c: 46bd mov sp, r7
|
|
800f12e: bd80 pop {r7, pc}
|
|
800f130: 20003574 .word 0x20003574
|
|
800f134: 20003588 .word 0x20003588
|
|
800f138: 20003578 .word 0x20003578
|
|
800f13c: 2000356c .word 0x2000356c
|
|
800f140: 2000357c .word 0x2000357c
|
|
800f144: 20003580 .word 0x20003580
|
|
|
|
0800f148 <vPortFree>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortFree( void *pv )
|
|
{
|
|
800f148: b580 push {r7, lr}
|
|
800f14a: b086 sub sp, #24
|
|
800f14c: af00 add r7, sp, #0
|
|
800f14e: 6078 str r0, [r7, #4]
|
|
uint8_t *puc = ( uint8_t * ) pv;
|
|
800f150: 687b ldr r3, [r7, #4]
|
|
800f152: 617b str r3, [r7, #20]
|
|
BlockLink_t *pxLink;
|
|
|
|
if( pv != NULL )
|
|
800f154: 687b ldr r3, [r7, #4]
|
|
800f156: 2b00 cmp r3, #0
|
|
800f158: d04f beq.n 800f1fa <vPortFree+0xb2>
|
|
{
|
|
/* The memory being freed will have an BlockLink_t structure immediately
|
|
before it. */
|
|
puc -= xHeapStructSize;
|
|
800f15a: 2308 movs r3, #8
|
|
800f15c: 425b negs r3, r3
|
|
800f15e: 697a ldr r2, [r7, #20]
|
|
800f160: 4413 add r3, r2
|
|
800f162: 617b str r3, [r7, #20]
|
|
|
|
/* This casting is to keep the compiler from issuing warnings. */
|
|
pxLink = ( void * ) puc;
|
|
800f164: 697b ldr r3, [r7, #20]
|
|
800f166: 613b str r3, [r7, #16]
|
|
|
|
/* Check the block is actually allocated. */
|
|
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
|
|
800f168: 693b ldr r3, [r7, #16]
|
|
800f16a: 685a ldr r2, [r3, #4]
|
|
800f16c: 4b25 ldr r3, [pc, #148] @ (800f204 <vPortFree+0xbc>)
|
|
800f16e: 681b ldr r3, [r3, #0]
|
|
800f170: 4013 ands r3, r2
|
|
800f172: 2b00 cmp r3, #0
|
|
800f174: d10b bne.n 800f18e <vPortFree+0x46>
|
|
__asm volatile
|
|
800f176: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800f17a: f383 8811 msr BASEPRI, r3
|
|
800f17e: f3bf 8f6f isb sy
|
|
800f182: f3bf 8f4f dsb sy
|
|
800f186: 60fb str r3, [r7, #12]
|
|
}
|
|
800f188: bf00 nop
|
|
800f18a: bf00 nop
|
|
800f18c: e7fd b.n 800f18a <vPortFree+0x42>
|
|
configASSERT( pxLink->pxNextFreeBlock == NULL );
|
|
800f18e: 693b ldr r3, [r7, #16]
|
|
800f190: 681b ldr r3, [r3, #0]
|
|
800f192: 2b00 cmp r3, #0
|
|
800f194: d00b beq.n 800f1ae <vPortFree+0x66>
|
|
__asm volatile
|
|
800f196: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800f19a: f383 8811 msr BASEPRI, r3
|
|
800f19e: f3bf 8f6f isb sy
|
|
800f1a2: f3bf 8f4f dsb sy
|
|
800f1a6: 60bb str r3, [r7, #8]
|
|
}
|
|
800f1a8: bf00 nop
|
|
800f1aa: bf00 nop
|
|
800f1ac: e7fd b.n 800f1aa <vPortFree+0x62>
|
|
|
|
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
|
|
800f1ae: 693b ldr r3, [r7, #16]
|
|
800f1b0: 685a ldr r2, [r3, #4]
|
|
800f1b2: 4b14 ldr r3, [pc, #80] @ (800f204 <vPortFree+0xbc>)
|
|
800f1b4: 681b ldr r3, [r3, #0]
|
|
800f1b6: 4013 ands r3, r2
|
|
800f1b8: 2b00 cmp r3, #0
|
|
800f1ba: d01e beq.n 800f1fa <vPortFree+0xb2>
|
|
{
|
|
if( pxLink->pxNextFreeBlock == NULL )
|
|
800f1bc: 693b ldr r3, [r7, #16]
|
|
800f1be: 681b ldr r3, [r3, #0]
|
|
800f1c0: 2b00 cmp r3, #0
|
|
800f1c2: d11a bne.n 800f1fa <vPortFree+0xb2>
|
|
{
|
|
/* The block is being returned to the heap - it is no longer
|
|
allocated. */
|
|
pxLink->xBlockSize &= ~xBlockAllocatedBit;
|
|
800f1c4: 693b ldr r3, [r7, #16]
|
|
800f1c6: 685a ldr r2, [r3, #4]
|
|
800f1c8: 4b0e ldr r3, [pc, #56] @ (800f204 <vPortFree+0xbc>)
|
|
800f1ca: 681b ldr r3, [r3, #0]
|
|
800f1cc: 43db mvns r3, r3
|
|
800f1ce: 401a ands r2, r3
|
|
800f1d0: 693b ldr r3, [r7, #16]
|
|
800f1d2: 605a str r2, [r3, #4]
|
|
|
|
vTaskSuspendAll();
|
|
800f1d4: f7fe fa74 bl 800d6c0 <vTaskSuspendAll>
|
|
{
|
|
/* Add this block to the list of free blocks. */
|
|
xFreeBytesRemaining += pxLink->xBlockSize;
|
|
800f1d8: 693b ldr r3, [r7, #16]
|
|
800f1da: 685a ldr r2, [r3, #4]
|
|
800f1dc: 4b0a ldr r3, [pc, #40] @ (800f208 <vPortFree+0xc0>)
|
|
800f1de: 681b ldr r3, [r3, #0]
|
|
800f1e0: 4413 add r3, r2
|
|
800f1e2: 4a09 ldr r2, [pc, #36] @ (800f208 <vPortFree+0xc0>)
|
|
800f1e4: 6013 str r3, [r2, #0]
|
|
traceFREE( pv, pxLink->xBlockSize );
|
|
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
|
|
800f1e6: 6938 ldr r0, [r7, #16]
|
|
800f1e8: f000 f874 bl 800f2d4 <prvInsertBlockIntoFreeList>
|
|
xNumberOfSuccessfulFrees++;
|
|
800f1ec: 4b07 ldr r3, [pc, #28] @ (800f20c <vPortFree+0xc4>)
|
|
800f1ee: 681b ldr r3, [r3, #0]
|
|
800f1f0: 3301 adds r3, #1
|
|
800f1f2: 4a06 ldr r2, [pc, #24] @ (800f20c <vPortFree+0xc4>)
|
|
800f1f4: 6013 str r3, [r2, #0]
|
|
}
|
|
( void ) xTaskResumeAll();
|
|
800f1f6: f7fe fa71 bl 800d6dc <xTaskResumeAll>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
800f1fa: bf00 nop
|
|
800f1fc: 3718 adds r7, #24
|
|
800f1fe: 46bd mov sp, r7
|
|
800f200: bd80 pop {r7, pc}
|
|
800f202: bf00 nop
|
|
800f204: 20003588 .word 0x20003588
|
|
800f208: 20003578 .word 0x20003578
|
|
800f20c: 20003584 .word 0x20003584
|
|
|
|
0800f210 <prvHeapInit>:
|
|
/* This just exists to keep the linker quiet. */
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvHeapInit( void )
|
|
{
|
|
800f210: b480 push {r7}
|
|
800f212: b085 sub sp, #20
|
|
800f214: af00 add r7, sp, #0
|
|
BlockLink_t *pxFirstFreeBlock;
|
|
uint8_t *pucAlignedHeap;
|
|
size_t uxAddress;
|
|
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
|
|
800f216: f640 33b8 movw r3, #3000 @ 0xbb8
|
|
800f21a: 60bb str r3, [r7, #8]
|
|
|
|
/* Ensure the heap starts on a correctly aligned boundary. */
|
|
uxAddress = ( size_t ) ucHeap;
|
|
800f21c: 4b27 ldr r3, [pc, #156] @ (800f2bc <prvHeapInit+0xac>)
|
|
800f21e: 60fb str r3, [r7, #12]
|
|
|
|
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
|
|
800f220: 68fb ldr r3, [r7, #12]
|
|
800f222: f003 0307 and.w r3, r3, #7
|
|
800f226: 2b00 cmp r3, #0
|
|
800f228: d00c beq.n 800f244 <prvHeapInit+0x34>
|
|
{
|
|
uxAddress += ( portBYTE_ALIGNMENT - 1 );
|
|
800f22a: 68fb ldr r3, [r7, #12]
|
|
800f22c: 3307 adds r3, #7
|
|
800f22e: 60fb str r3, [r7, #12]
|
|
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
|
800f230: 68fb ldr r3, [r7, #12]
|
|
800f232: f023 0307 bic.w r3, r3, #7
|
|
800f236: 60fb str r3, [r7, #12]
|
|
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
|
|
800f238: 68ba ldr r2, [r7, #8]
|
|
800f23a: 68fb ldr r3, [r7, #12]
|
|
800f23c: 1ad3 subs r3, r2, r3
|
|
800f23e: 4a1f ldr r2, [pc, #124] @ (800f2bc <prvHeapInit+0xac>)
|
|
800f240: 4413 add r3, r2
|
|
800f242: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
pucAlignedHeap = ( uint8_t * ) uxAddress;
|
|
800f244: 68fb ldr r3, [r7, #12]
|
|
800f246: 607b str r3, [r7, #4]
|
|
|
|
/* xStart is used to hold a pointer to the first item in the list of free
|
|
blocks. The void cast is used to prevent compiler warnings. */
|
|
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
|
|
800f248: 4a1d ldr r2, [pc, #116] @ (800f2c0 <prvHeapInit+0xb0>)
|
|
800f24a: 687b ldr r3, [r7, #4]
|
|
800f24c: 6013 str r3, [r2, #0]
|
|
xStart.xBlockSize = ( size_t ) 0;
|
|
800f24e: 4b1c ldr r3, [pc, #112] @ (800f2c0 <prvHeapInit+0xb0>)
|
|
800f250: 2200 movs r2, #0
|
|
800f252: 605a str r2, [r3, #4]
|
|
|
|
/* pxEnd is used to mark the end of the list of free blocks and is inserted
|
|
at the end of the heap space. */
|
|
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
|
|
800f254: 687b ldr r3, [r7, #4]
|
|
800f256: 68ba ldr r2, [r7, #8]
|
|
800f258: 4413 add r3, r2
|
|
800f25a: 60fb str r3, [r7, #12]
|
|
uxAddress -= xHeapStructSize;
|
|
800f25c: 2208 movs r2, #8
|
|
800f25e: 68fb ldr r3, [r7, #12]
|
|
800f260: 1a9b subs r3, r3, r2
|
|
800f262: 60fb str r3, [r7, #12]
|
|
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
|
800f264: 68fb ldr r3, [r7, #12]
|
|
800f266: f023 0307 bic.w r3, r3, #7
|
|
800f26a: 60fb str r3, [r7, #12]
|
|
pxEnd = ( void * ) uxAddress;
|
|
800f26c: 68fb ldr r3, [r7, #12]
|
|
800f26e: 4a15 ldr r2, [pc, #84] @ (800f2c4 <prvHeapInit+0xb4>)
|
|
800f270: 6013 str r3, [r2, #0]
|
|
pxEnd->xBlockSize = 0;
|
|
800f272: 4b14 ldr r3, [pc, #80] @ (800f2c4 <prvHeapInit+0xb4>)
|
|
800f274: 681b ldr r3, [r3, #0]
|
|
800f276: 2200 movs r2, #0
|
|
800f278: 605a str r2, [r3, #4]
|
|
pxEnd->pxNextFreeBlock = NULL;
|
|
800f27a: 4b12 ldr r3, [pc, #72] @ (800f2c4 <prvHeapInit+0xb4>)
|
|
800f27c: 681b ldr r3, [r3, #0]
|
|
800f27e: 2200 movs r2, #0
|
|
800f280: 601a str r2, [r3, #0]
|
|
|
|
/* To start with there is a single free block that is sized to take up the
|
|
entire heap space, minus the space taken by pxEnd. */
|
|
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
|
|
800f282: 687b ldr r3, [r7, #4]
|
|
800f284: 603b str r3, [r7, #0]
|
|
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
|
|
800f286: 683b ldr r3, [r7, #0]
|
|
800f288: 68fa ldr r2, [r7, #12]
|
|
800f28a: 1ad2 subs r2, r2, r3
|
|
800f28c: 683b ldr r3, [r7, #0]
|
|
800f28e: 605a str r2, [r3, #4]
|
|
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
|
|
800f290: 4b0c ldr r3, [pc, #48] @ (800f2c4 <prvHeapInit+0xb4>)
|
|
800f292: 681a ldr r2, [r3, #0]
|
|
800f294: 683b ldr r3, [r7, #0]
|
|
800f296: 601a str r2, [r3, #0]
|
|
|
|
/* Only one block exists - and it covers the entire usable heap space. */
|
|
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
|
800f298: 683b ldr r3, [r7, #0]
|
|
800f29a: 685b ldr r3, [r3, #4]
|
|
800f29c: 4a0a ldr r2, [pc, #40] @ (800f2c8 <prvHeapInit+0xb8>)
|
|
800f29e: 6013 str r3, [r2, #0]
|
|
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
|
800f2a0: 683b ldr r3, [r7, #0]
|
|
800f2a2: 685b ldr r3, [r3, #4]
|
|
800f2a4: 4a09 ldr r2, [pc, #36] @ (800f2cc <prvHeapInit+0xbc>)
|
|
800f2a6: 6013 str r3, [r2, #0]
|
|
|
|
/* Work out the position of the top bit in a size_t variable. */
|
|
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
|
|
800f2a8: 4b09 ldr r3, [pc, #36] @ (800f2d0 <prvHeapInit+0xc0>)
|
|
800f2aa: f04f 4200 mov.w r2, #2147483648 @ 0x80000000
|
|
800f2ae: 601a str r2, [r3, #0]
|
|
}
|
|
800f2b0: bf00 nop
|
|
800f2b2: 3714 adds r7, #20
|
|
800f2b4: 46bd mov sp, r7
|
|
800f2b6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f2ba: 4770 bx lr
|
|
800f2bc: 200029b4 .word 0x200029b4
|
|
800f2c0: 2000356c .word 0x2000356c
|
|
800f2c4: 20003574 .word 0x20003574
|
|
800f2c8: 2000357c .word 0x2000357c
|
|
800f2cc: 20003578 .word 0x20003578
|
|
800f2d0: 20003588 .word 0x20003588
|
|
|
|
0800f2d4 <prvInsertBlockIntoFreeList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
|
|
{
|
|
800f2d4: b480 push {r7}
|
|
800f2d6: b085 sub sp, #20
|
|
800f2d8: af00 add r7, sp, #0
|
|
800f2da: 6078 str r0, [r7, #4]
|
|
BlockLink_t *pxIterator;
|
|
uint8_t *puc;
|
|
|
|
/* Iterate through the list until a block is found that has a higher address
|
|
than the block being inserted. */
|
|
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
|
|
800f2dc: 4b28 ldr r3, [pc, #160] @ (800f380 <prvInsertBlockIntoFreeList+0xac>)
|
|
800f2de: 60fb str r3, [r7, #12]
|
|
800f2e0: e002 b.n 800f2e8 <prvInsertBlockIntoFreeList+0x14>
|
|
800f2e2: 68fb ldr r3, [r7, #12]
|
|
800f2e4: 681b ldr r3, [r3, #0]
|
|
800f2e6: 60fb str r3, [r7, #12]
|
|
800f2e8: 68fb ldr r3, [r7, #12]
|
|
800f2ea: 681b ldr r3, [r3, #0]
|
|
800f2ec: 687a ldr r2, [r7, #4]
|
|
800f2ee: 429a cmp r2, r3
|
|
800f2f0: d8f7 bhi.n 800f2e2 <prvInsertBlockIntoFreeList+0xe>
|
|
/* Nothing to do here, just iterate to the right position. */
|
|
}
|
|
|
|
/* Do the block being inserted, and the block it is being inserted after
|
|
make a contiguous block of memory? */
|
|
puc = ( uint8_t * ) pxIterator;
|
|
800f2f2: 68fb ldr r3, [r7, #12]
|
|
800f2f4: 60bb str r3, [r7, #8]
|
|
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
|
|
800f2f6: 68fb ldr r3, [r7, #12]
|
|
800f2f8: 685b ldr r3, [r3, #4]
|
|
800f2fa: 68ba ldr r2, [r7, #8]
|
|
800f2fc: 4413 add r3, r2
|
|
800f2fe: 687a ldr r2, [r7, #4]
|
|
800f300: 429a cmp r2, r3
|
|
800f302: d108 bne.n 800f316 <prvInsertBlockIntoFreeList+0x42>
|
|
{
|
|
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
|
|
800f304: 68fb ldr r3, [r7, #12]
|
|
800f306: 685a ldr r2, [r3, #4]
|
|
800f308: 687b ldr r3, [r7, #4]
|
|
800f30a: 685b ldr r3, [r3, #4]
|
|
800f30c: 441a add r2, r3
|
|
800f30e: 68fb ldr r3, [r7, #12]
|
|
800f310: 605a str r2, [r3, #4]
|
|
pxBlockToInsert = pxIterator;
|
|
800f312: 68fb ldr r3, [r7, #12]
|
|
800f314: 607b str r3, [r7, #4]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Do the block being inserted, and the block it is being inserted before
|
|
make a contiguous block of memory? */
|
|
puc = ( uint8_t * ) pxBlockToInsert;
|
|
800f316: 687b ldr r3, [r7, #4]
|
|
800f318: 60bb str r3, [r7, #8]
|
|
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
|
|
800f31a: 687b ldr r3, [r7, #4]
|
|
800f31c: 685b ldr r3, [r3, #4]
|
|
800f31e: 68ba ldr r2, [r7, #8]
|
|
800f320: 441a add r2, r3
|
|
800f322: 68fb ldr r3, [r7, #12]
|
|
800f324: 681b ldr r3, [r3, #0]
|
|
800f326: 429a cmp r2, r3
|
|
800f328: d118 bne.n 800f35c <prvInsertBlockIntoFreeList+0x88>
|
|
{
|
|
if( pxIterator->pxNextFreeBlock != pxEnd )
|
|
800f32a: 68fb ldr r3, [r7, #12]
|
|
800f32c: 681a ldr r2, [r3, #0]
|
|
800f32e: 4b15 ldr r3, [pc, #84] @ (800f384 <prvInsertBlockIntoFreeList+0xb0>)
|
|
800f330: 681b ldr r3, [r3, #0]
|
|
800f332: 429a cmp r2, r3
|
|
800f334: d00d beq.n 800f352 <prvInsertBlockIntoFreeList+0x7e>
|
|
{
|
|
/* Form one big block from the two blocks. */
|
|
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
|
|
800f336: 687b ldr r3, [r7, #4]
|
|
800f338: 685a ldr r2, [r3, #4]
|
|
800f33a: 68fb ldr r3, [r7, #12]
|
|
800f33c: 681b ldr r3, [r3, #0]
|
|
800f33e: 685b ldr r3, [r3, #4]
|
|
800f340: 441a add r2, r3
|
|
800f342: 687b ldr r3, [r7, #4]
|
|
800f344: 605a str r2, [r3, #4]
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
|
|
800f346: 68fb ldr r3, [r7, #12]
|
|
800f348: 681b ldr r3, [r3, #0]
|
|
800f34a: 681a ldr r2, [r3, #0]
|
|
800f34c: 687b ldr r3, [r7, #4]
|
|
800f34e: 601a str r2, [r3, #0]
|
|
800f350: e008 b.n 800f364 <prvInsertBlockIntoFreeList+0x90>
|
|
}
|
|
else
|
|
{
|
|
pxBlockToInsert->pxNextFreeBlock = pxEnd;
|
|
800f352: 4b0c ldr r3, [pc, #48] @ (800f384 <prvInsertBlockIntoFreeList+0xb0>)
|
|
800f354: 681a ldr r2, [r3, #0]
|
|
800f356: 687b ldr r3, [r7, #4]
|
|
800f358: 601a str r2, [r3, #0]
|
|
800f35a: e003 b.n 800f364 <prvInsertBlockIntoFreeList+0x90>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
|
|
800f35c: 68fb ldr r3, [r7, #12]
|
|
800f35e: 681a ldr r2, [r3, #0]
|
|
800f360: 687b ldr r3, [r7, #4]
|
|
800f362: 601a str r2, [r3, #0]
|
|
|
|
/* If the block being inserted plugged a gab, so was merged with the block
|
|
before and the block after, then it's pxNextFreeBlock pointer will have
|
|
already been set, and should not be set here as that would make it point
|
|
to itself. */
|
|
if( pxIterator != pxBlockToInsert )
|
|
800f364: 68fa ldr r2, [r7, #12]
|
|
800f366: 687b ldr r3, [r7, #4]
|
|
800f368: 429a cmp r2, r3
|
|
800f36a: d002 beq.n 800f372 <prvInsertBlockIntoFreeList+0x9e>
|
|
{
|
|
pxIterator->pxNextFreeBlock = pxBlockToInsert;
|
|
800f36c: 68fb ldr r3, [r7, #12]
|
|
800f36e: 687a ldr r2, [r7, #4]
|
|
800f370: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800f372: bf00 nop
|
|
800f374: 3714 adds r7, #20
|
|
800f376: 46bd mov sp, r7
|
|
800f378: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f37c: 4770 bx lr
|
|
800f37e: bf00 nop
|
|
800f380: 2000356c .word 0x2000356c
|
|
800f384: 20003574 .word 0x20003574
|
|
|
|
0800f388 <__cvt>:
|
|
800f388: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800f38c: ec57 6b10 vmov r6, r7, d0
|
|
800f390: 2f00 cmp r7, #0
|
|
800f392: 460c mov r4, r1
|
|
800f394: 4619 mov r1, r3
|
|
800f396: 463b mov r3, r7
|
|
800f398: bfbb ittet lt
|
|
800f39a: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000
|
|
800f39e: 461f movlt r7, r3
|
|
800f3a0: 2300 movge r3, #0
|
|
800f3a2: 232d movlt r3, #45 @ 0x2d
|
|
800f3a4: 700b strb r3, [r1, #0]
|
|
800f3a6: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
800f3a8: f8dd a030 ldr.w sl, [sp, #48] @ 0x30
|
|
800f3ac: 4691 mov r9, r2
|
|
800f3ae: f023 0820 bic.w r8, r3, #32
|
|
800f3b2: bfbc itt lt
|
|
800f3b4: 4632 movlt r2, r6
|
|
800f3b6: 4616 movlt r6, r2
|
|
800f3b8: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
800f3bc: d005 beq.n 800f3ca <__cvt+0x42>
|
|
800f3be: f1b8 0f45 cmp.w r8, #69 @ 0x45
|
|
800f3c2: d100 bne.n 800f3c6 <__cvt+0x3e>
|
|
800f3c4: 3401 adds r4, #1
|
|
800f3c6: 2102 movs r1, #2
|
|
800f3c8: e000 b.n 800f3cc <__cvt+0x44>
|
|
800f3ca: 2103 movs r1, #3
|
|
800f3cc: ab03 add r3, sp, #12
|
|
800f3ce: 9301 str r3, [sp, #4]
|
|
800f3d0: ab02 add r3, sp, #8
|
|
800f3d2: 9300 str r3, [sp, #0]
|
|
800f3d4: ec47 6b10 vmov d0, r6, r7
|
|
800f3d8: 4653 mov r3, sl
|
|
800f3da: 4622 mov r2, r4
|
|
800f3dc: f001 fa54 bl 8010888 <_dtoa_r>
|
|
800f3e0: f1b8 0f47 cmp.w r8, #71 @ 0x47
|
|
800f3e4: 4605 mov r5, r0
|
|
800f3e6: d119 bne.n 800f41c <__cvt+0x94>
|
|
800f3e8: f019 0f01 tst.w r9, #1
|
|
800f3ec: d00e beq.n 800f40c <__cvt+0x84>
|
|
800f3ee: eb00 0904 add.w r9, r0, r4
|
|
800f3f2: 2200 movs r2, #0
|
|
800f3f4: 2300 movs r3, #0
|
|
800f3f6: 4630 mov r0, r6
|
|
800f3f8: 4639 mov r1, r7
|
|
800f3fa: f7f1 fb65 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800f3fe: b108 cbz r0, 800f404 <__cvt+0x7c>
|
|
800f400: f8cd 900c str.w r9, [sp, #12]
|
|
800f404: 2230 movs r2, #48 @ 0x30
|
|
800f406: 9b03 ldr r3, [sp, #12]
|
|
800f408: 454b cmp r3, r9
|
|
800f40a: d31e bcc.n 800f44a <__cvt+0xc2>
|
|
800f40c: 9b03 ldr r3, [sp, #12]
|
|
800f40e: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
800f410: 1b5b subs r3, r3, r5
|
|
800f412: 4628 mov r0, r5
|
|
800f414: 6013 str r3, [r2, #0]
|
|
800f416: b004 add sp, #16
|
|
800f418: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800f41c: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
800f420: eb00 0904 add.w r9, r0, r4
|
|
800f424: d1e5 bne.n 800f3f2 <__cvt+0x6a>
|
|
800f426: 7803 ldrb r3, [r0, #0]
|
|
800f428: 2b30 cmp r3, #48 @ 0x30
|
|
800f42a: d10a bne.n 800f442 <__cvt+0xba>
|
|
800f42c: 2200 movs r2, #0
|
|
800f42e: 2300 movs r3, #0
|
|
800f430: 4630 mov r0, r6
|
|
800f432: 4639 mov r1, r7
|
|
800f434: f7f1 fb48 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800f438: b918 cbnz r0, 800f442 <__cvt+0xba>
|
|
800f43a: f1c4 0401 rsb r4, r4, #1
|
|
800f43e: f8ca 4000 str.w r4, [sl]
|
|
800f442: f8da 3000 ldr.w r3, [sl]
|
|
800f446: 4499 add r9, r3
|
|
800f448: e7d3 b.n 800f3f2 <__cvt+0x6a>
|
|
800f44a: 1c59 adds r1, r3, #1
|
|
800f44c: 9103 str r1, [sp, #12]
|
|
800f44e: 701a strb r2, [r3, #0]
|
|
800f450: e7d9 b.n 800f406 <__cvt+0x7e>
|
|
|
|
0800f452 <__exponent>:
|
|
800f452: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
800f454: 2900 cmp r1, #0
|
|
800f456: bfba itte lt
|
|
800f458: 4249 neglt r1, r1
|
|
800f45a: 232d movlt r3, #45 @ 0x2d
|
|
800f45c: 232b movge r3, #43 @ 0x2b
|
|
800f45e: 2909 cmp r1, #9
|
|
800f460: 7002 strb r2, [r0, #0]
|
|
800f462: 7043 strb r3, [r0, #1]
|
|
800f464: dd29 ble.n 800f4ba <__exponent+0x68>
|
|
800f466: f10d 0307 add.w r3, sp, #7
|
|
800f46a: 461d mov r5, r3
|
|
800f46c: 270a movs r7, #10
|
|
800f46e: 461a mov r2, r3
|
|
800f470: fbb1 f6f7 udiv r6, r1, r7
|
|
800f474: fb07 1416 mls r4, r7, r6, r1
|
|
800f478: 3430 adds r4, #48 @ 0x30
|
|
800f47a: f802 4c01 strb.w r4, [r2, #-1]
|
|
800f47e: 460c mov r4, r1
|
|
800f480: 2c63 cmp r4, #99 @ 0x63
|
|
800f482: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff
|
|
800f486: 4631 mov r1, r6
|
|
800f488: dcf1 bgt.n 800f46e <__exponent+0x1c>
|
|
800f48a: 3130 adds r1, #48 @ 0x30
|
|
800f48c: 1e94 subs r4, r2, #2
|
|
800f48e: f803 1c01 strb.w r1, [r3, #-1]
|
|
800f492: 1c41 adds r1, r0, #1
|
|
800f494: 4623 mov r3, r4
|
|
800f496: 42ab cmp r3, r5
|
|
800f498: d30a bcc.n 800f4b0 <__exponent+0x5e>
|
|
800f49a: f10d 0309 add.w r3, sp, #9
|
|
800f49e: 1a9b subs r3, r3, r2
|
|
800f4a0: 42ac cmp r4, r5
|
|
800f4a2: bf88 it hi
|
|
800f4a4: 2300 movhi r3, #0
|
|
800f4a6: 3302 adds r3, #2
|
|
800f4a8: 4403 add r3, r0
|
|
800f4aa: 1a18 subs r0, r3, r0
|
|
800f4ac: b003 add sp, #12
|
|
800f4ae: bdf0 pop {r4, r5, r6, r7, pc}
|
|
800f4b0: f813 6b01 ldrb.w r6, [r3], #1
|
|
800f4b4: f801 6f01 strb.w r6, [r1, #1]!
|
|
800f4b8: e7ed b.n 800f496 <__exponent+0x44>
|
|
800f4ba: 2330 movs r3, #48 @ 0x30
|
|
800f4bc: 3130 adds r1, #48 @ 0x30
|
|
800f4be: 7083 strb r3, [r0, #2]
|
|
800f4c0: 70c1 strb r1, [r0, #3]
|
|
800f4c2: 1d03 adds r3, r0, #4
|
|
800f4c4: e7f1 b.n 800f4aa <__exponent+0x58>
|
|
...
|
|
|
|
0800f4c8 <_printf_float>:
|
|
800f4c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800f4cc: b08d sub sp, #52 @ 0x34
|
|
800f4ce: 460c mov r4, r1
|
|
800f4d0: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
|
|
800f4d4: 4616 mov r6, r2
|
|
800f4d6: 461f mov r7, r3
|
|
800f4d8: 4605 mov r5, r0
|
|
800f4da: f001 f8a3 bl 8010624 <_localeconv_r>
|
|
800f4de: 6803 ldr r3, [r0, #0]
|
|
800f4e0: 9304 str r3, [sp, #16]
|
|
800f4e2: 4618 mov r0, r3
|
|
800f4e4: f7f0 fec4 bl 8000270 <strlen>
|
|
800f4e8: 2300 movs r3, #0
|
|
800f4ea: 930a str r3, [sp, #40] @ 0x28
|
|
800f4ec: f8d8 3000 ldr.w r3, [r8]
|
|
800f4f0: 9005 str r0, [sp, #20]
|
|
800f4f2: 3307 adds r3, #7
|
|
800f4f4: f023 0307 bic.w r3, r3, #7
|
|
800f4f8: f103 0208 add.w r2, r3, #8
|
|
800f4fc: f894 a018 ldrb.w sl, [r4, #24]
|
|
800f500: f8d4 b000 ldr.w fp, [r4]
|
|
800f504: f8c8 2000 str.w r2, [r8]
|
|
800f508: e9d3 8900 ldrd r8, r9, [r3]
|
|
800f50c: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
|
|
800f510: 9307 str r3, [sp, #28]
|
|
800f512: f8cd 8018 str.w r8, [sp, #24]
|
|
800f516: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48
|
|
800f51a: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
800f51e: 4b9c ldr r3, [pc, #624] @ (800f790 <_printf_float+0x2c8>)
|
|
800f520: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800f524: f7f1 fb02 bl 8000b2c <__aeabi_dcmpun>
|
|
800f528: bb70 cbnz r0, 800f588 <_printf_float+0xc0>
|
|
800f52a: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
800f52e: 4b98 ldr r3, [pc, #608] @ (800f790 <_printf_float+0x2c8>)
|
|
800f530: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800f534: f7f1 fadc bl 8000af0 <__aeabi_dcmple>
|
|
800f538: bb30 cbnz r0, 800f588 <_printf_float+0xc0>
|
|
800f53a: 2200 movs r2, #0
|
|
800f53c: 2300 movs r3, #0
|
|
800f53e: 4640 mov r0, r8
|
|
800f540: 4649 mov r1, r9
|
|
800f542: f7f1 facb bl 8000adc <__aeabi_dcmplt>
|
|
800f546: b110 cbz r0, 800f54e <_printf_float+0x86>
|
|
800f548: 232d movs r3, #45 @ 0x2d
|
|
800f54a: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
800f54e: 4a91 ldr r2, [pc, #580] @ (800f794 <_printf_float+0x2cc>)
|
|
800f550: 4b91 ldr r3, [pc, #580] @ (800f798 <_printf_float+0x2d0>)
|
|
800f552: f1ba 0f47 cmp.w sl, #71 @ 0x47
|
|
800f556: bf8c ite hi
|
|
800f558: 4690 movhi r8, r2
|
|
800f55a: 4698 movls r8, r3
|
|
800f55c: 2303 movs r3, #3
|
|
800f55e: 6123 str r3, [r4, #16]
|
|
800f560: f02b 0304 bic.w r3, fp, #4
|
|
800f564: 6023 str r3, [r4, #0]
|
|
800f566: f04f 0900 mov.w r9, #0
|
|
800f56a: 9700 str r7, [sp, #0]
|
|
800f56c: 4633 mov r3, r6
|
|
800f56e: aa0b add r2, sp, #44 @ 0x2c
|
|
800f570: 4621 mov r1, r4
|
|
800f572: 4628 mov r0, r5
|
|
800f574: f000 f9d2 bl 800f91c <_printf_common>
|
|
800f578: 3001 adds r0, #1
|
|
800f57a: f040 808d bne.w 800f698 <_printf_float+0x1d0>
|
|
800f57e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800f582: b00d add sp, #52 @ 0x34
|
|
800f584: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800f588: 4642 mov r2, r8
|
|
800f58a: 464b mov r3, r9
|
|
800f58c: 4640 mov r0, r8
|
|
800f58e: 4649 mov r1, r9
|
|
800f590: f7f1 facc bl 8000b2c <__aeabi_dcmpun>
|
|
800f594: b140 cbz r0, 800f5a8 <_printf_float+0xe0>
|
|
800f596: 464b mov r3, r9
|
|
800f598: 2b00 cmp r3, #0
|
|
800f59a: bfbc itt lt
|
|
800f59c: 232d movlt r3, #45 @ 0x2d
|
|
800f59e: f884 3043 strblt.w r3, [r4, #67] @ 0x43
|
|
800f5a2: 4a7e ldr r2, [pc, #504] @ (800f79c <_printf_float+0x2d4>)
|
|
800f5a4: 4b7e ldr r3, [pc, #504] @ (800f7a0 <_printf_float+0x2d8>)
|
|
800f5a6: e7d4 b.n 800f552 <_printf_float+0x8a>
|
|
800f5a8: 6863 ldr r3, [r4, #4]
|
|
800f5aa: f00a 02df and.w r2, sl, #223 @ 0xdf
|
|
800f5ae: 9206 str r2, [sp, #24]
|
|
800f5b0: 1c5a adds r2, r3, #1
|
|
800f5b2: d13b bne.n 800f62c <_printf_float+0x164>
|
|
800f5b4: 2306 movs r3, #6
|
|
800f5b6: 6063 str r3, [r4, #4]
|
|
800f5b8: f44b 6280 orr.w r2, fp, #1024 @ 0x400
|
|
800f5bc: 2300 movs r3, #0
|
|
800f5be: 6022 str r2, [r4, #0]
|
|
800f5c0: 9303 str r3, [sp, #12]
|
|
800f5c2: ab0a add r3, sp, #40 @ 0x28
|
|
800f5c4: e9cd a301 strd sl, r3, [sp, #4]
|
|
800f5c8: ab09 add r3, sp, #36 @ 0x24
|
|
800f5ca: 9300 str r3, [sp, #0]
|
|
800f5cc: 6861 ldr r1, [r4, #4]
|
|
800f5ce: ec49 8b10 vmov d0, r8, r9
|
|
800f5d2: f10d 0323 add.w r3, sp, #35 @ 0x23
|
|
800f5d6: 4628 mov r0, r5
|
|
800f5d8: f7ff fed6 bl 800f388 <__cvt>
|
|
800f5dc: 9b06 ldr r3, [sp, #24]
|
|
800f5de: 9909 ldr r1, [sp, #36] @ 0x24
|
|
800f5e0: 2b47 cmp r3, #71 @ 0x47
|
|
800f5e2: 4680 mov r8, r0
|
|
800f5e4: d129 bne.n 800f63a <_printf_float+0x172>
|
|
800f5e6: 1cc8 adds r0, r1, #3
|
|
800f5e8: db02 blt.n 800f5f0 <_printf_float+0x128>
|
|
800f5ea: 6863 ldr r3, [r4, #4]
|
|
800f5ec: 4299 cmp r1, r3
|
|
800f5ee: dd41 ble.n 800f674 <_printf_float+0x1ac>
|
|
800f5f0: f1aa 0a02 sub.w sl, sl, #2
|
|
800f5f4: fa5f fa8a uxtb.w sl, sl
|
|
800f5f8: 3901 subs r1, #1
|
|
800f5fa: 4652 mov r2, sl
|
|
800f5fc: f104 0050 add.w r0, r4, #80 @ 0x50
|
|
800f600: 9109 str r1, [sp, #36] @ 0x24
|
|
800f602: f7ff ff26 bl 800f452 <__exponent>
|
|
800f606: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
800f608: 1813 adds r3, r2, r0
|
|
800f60a: 2a01 cmp r2, #1
|
|
800f60c: 4681 mov r9, r0
|
|
800f60e: 6123 str r3, [r4, #16]
|
|
800f610: dc02 bgt.n 800f618 <_printf_float+0x150>
|
|
800f612: 6822 ldr r2, [r4, #0]
|
|
800f614: 07d2 lsls r2, r2, #31
|
|
800f616: d501 bpl.n 800f61c <_printf_float+0x154>
|
|
800f618: 3301 adds r3, #1
|
|
800f61a: 6123 str r3, [r4, #16]
|
|
800f61c: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
|
|
800f620: 2b00 cmp r3, #0
|
|
800f622: d0a2 beq.n 800f56a <_printf_float+0xa2>
|
|
800f624: 232d movs r3, #45 @ 0x2d
|
|
800f626: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
800f62a: e79e b.n 800f56a <_printf_float+0xa2>
|
|
800f62c: 9a06 ldr r2, [sp, #24]
|
|
800f62e: 2a47 cmp r2, #71 @ 0x47
|
|
800f630: d1c2 bne.n 800f5b8 <_printf_float+0xf0>
|
|
800f632: 2b00 cmp r3, #0
|
|
800f634: d1c0 bne.n 800f5b8 <_printf_float+0xf0>
|
|
800f636: 2301 movs r3, #1
|
|
800f638: e7bd b.n 800f5b6 <_printf_float+0xee>
|
|
800f63a: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
800f63e: d9db bls.n 800f5f8 <_printf_float+0x130>
|
|
800f640: f1ba 0f66 cmp.w sl, #102 @ 0x66
|
|
800f644: d118 bne.n 800f678 <_printf_float+0x1b0>
|
|
800f646: 2900 cmp r1, #0
|
|
800f648: 6863 ldr r3, [r4, #4]
|
|
800f64a: dd0b ble.n 800f664 <_printf_float+0x19c>
|
|
800f64c: 6121 str r1, [r4, #16]
|
|
800f64e: b913 cbnz r3, 800f656 <_printf_float+0x18e>
|
|
800f650: 6822 ldr r2, [r4, #0]
|
|
800f652: 07d0 lsls r0, r2, #31
|
|
800f654: d502 bpl.n 800f65c <_printf_float+0x194>
|
|
800f656: 3301 adds r3, #1
|
|
800f658: 440b add r3, r1
|
|
800f65a: 6123 str r3, [r4, #16]
|
|
800f65c: 65a1 str r1, [r4, #88] @ 0x58
|
|
800f65e: f04f 0900 mov.w r9, #0
|
|
800f662: e7db b.n 800f61c <_printf_float+0x154>
|
|
800f664: b913 cbnz r3, 800f66c <_printf_float+0x1a4>
|
|
800f666: 6822 ldr r2, [r4, #0]
|
|
800f668: 07d2 lsls r2, r2, #31
|
|
800f66a: d501 bpl.n 800f670 <_printf_float+0x1a8>
|
|
800f66c: 3302 adds r3, #2
|
|
800f66e: e7f4 b.n 800f65a <_printf_float+0x192>
|
|
800f670: 2301 movs r3, #1
|
|
800f672: e7f2 b.n 800f65a <_printf_float+0x192>
|
|
800f674: f04f 0a67 mov.w sl, #103 @ 0x67
|
|
800f678: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
800f67a: 4299 cmp r1, r3
|
|
800f67c: db05 blt.n 800f68a <_printf_float+0x1c2>
|
|
800f67e: 6823 ldr r3, [r4, #0]
|
|
800f680: 6121 str r1, [r4, #16]
|
|
800f682: 07d8 lsls r0, r3, #31
|
|
800f684: d5ea bpl.n 800f65c <_printf_float+0x194>
|
|
800f686: 1c4b adds r3, r1, #1
|
|
800f688: e7e7 b.n 800f65a <_printf_float+0x192>
|
|
800f68a: 2900 cmp r1, #0
|
|
800f68c: bfd4 ite le
|
|
800f68e: f1c1 0202 rsble r2, r1, #2
|
|
800f692: 2201 movgt r2, #1
|
|
800f694: 4413 add r3, r2
|
|
800f696: e7e0 b.n 800f65a <_printf_float+0x192>
|
|
800f698: 6823 ldr r3, [r4, #0]
|
|
800f69a: 055a lsls r2, r3, #21
|
|
800f69c: d407 bmi.n 800f6ae <_printf_float+0x1e6>
|
|
800f69e: 6923 ldr r3, [r4, #16]
|
|
800f6a0: 4642 mov r2, r8
|
|
800f6a2: 4631 mov r1, r6
|
|
800f6a4: 4628 mov r0, r5
|
|
800f6a6: 47b8 blx r7
|
|
800f6a8: 3001 adds r0, #1
|
|
800f6aa: d12b bne.n 800f704 <_printf_float+0x23c>
|
|
800f6ac: e767 b.n 800f57e <_printf_float+0xb6>
|
|
800f6ae: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
800f6b2: f240 80dd bls.w 800f870 <_printf_float+0x3a8>
|
|
800f6b6: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
800f6ba: 2200 movs r2, #0
|
|
800f6bc: 2300 movs r3, #0
|
|
800f6be: f7f1 fa03 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800f6c2: 2800 cmp r0, #0
|
|
800f6c4: d033 beq.n 800f72e <_printf_float+0x266>
|
|
800f6c6: 4a37 ldr r2, [pc, #220] @ (800f7a4 <_printf_float+0x2dc>)
|
|
800f6c8: 2301 movs r3, #1
|
|
800f6ca: 4631 mov r1, r6
|
|
800f6cc: 4628 mov r0, r5
|
|
800f6ce: 47b8 blx r7
|
|
800f6d0: 3001 adds r0, #1
|
|
800f6d2: f43f af54 beq.w 800f57e <_printf_float+0xb6>
|
|
800f6d6: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
|
|
800f6da: 4543 cmp r3, r8
|
|
800f6dc: db02 blt.n 800f6e4 <_printf_float+0x21c>
|
|
800f6de: 6823 ldr r3, [r4, #0]
|
|
800f6e0: 07d8 lsls r0, r3, #31
|
|
800f6e2: d50f bpl.n 800f704 <_printf_float+0x23c>
|
|
800f6e4: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
800f6e8: 4631 mov r1, r6
|
|
800f6ea: 4628 mov r0, r5
|
|
800f6ec: 47b8 blx r7
|
|
800f6ee: 3001 adds r0, #1
|
|
800f6f0: f43f af45 beq.w 800f57e <_printf_float+0xb6>
|
|
800f6f4: f04f 0900 mov.w r9, #0
|
|
800f6f8: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
|
|
800f6fc: f104 0a1a add.w sl, r4, #26
|
|
800f700: 45c8 cmp r8, r9
|
|
800f702: dc09 bgt.n 800f718 <_printf_float+0x250>
|
|
800f704: 6823 ldr r3, [r4, #0]
|
|
800f706: 079b lsls r3, r3, #30
|
|
800f708: f100 8103 bmi.w 800f912 <_printf_float+0x44a>
|
|
800f70c: 68e0 ldr r0, [r4, #12]
|
|
800f70e: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
800f710: 4298 cmp r0, r3
|
|
800f712: bfb8 it lt
|
|
800f714: 4618 movlt r0, r3
|
|
800f716: e734 b.n 800f582 <_printf_float+0xba>
|
|
800f718: 2301 movs r3, #1
|
|
800f71a: 4652 mov r2, sl
|
|
800f71c: 4631 mov r1, r6
|
|
800f71e: 4628 mov r0, r5
|
|
800f720: 47b8 blx r7
|
|
800f722: 3001 adds r0, #1
|
|
800f724: f43f af2b beq.w 800f57e <_printf_float+0xb6>
|
|
800f728: f109 0901 add.w r9, r9, #1
|
|
800f72c: e7e8 b.n 800f700 <_printf_float+0x238>
|
|
800f72e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
800f730: 2b00 cmp r3, #0
|
|
800f732: dc39 bgt.n 800f7a8 <_printf_float+0x2e0>
|
|
800f734: 4a1b ldr r2, [pc, #108] @ (800f7a4 <_printf_float+0x2dc>)
|
|
800f736: 2301 movs r3, #1
|
|
800f738: 4631 mov r1, r6
|
|
800f73a: 4628 mov r0, r5
|
|
800f73c: 47b8 blx r7
|
|
800f73e: 3001 adds r0, #1
|
|
800f740: f43f af1d beq.w 800f57e <_printf_float+0xb6>
|
|
800f744: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
|
|
800f748: ea59 0303 orrs.w r3, r9, r3
|
|
800f74c: d102 bne.n 800f754 <_printf_float+0x28c>
|
|
800f74e: 6823 ldr r3, [r4, #0]
|
|
800f750: 07d9 lsls r1, r3, #31
|
|
800f752: d5d7 bpl.n 800f704 <_printf_float+0x23c>
|
|
800f754: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
800f758: 4631 mov r1, r6
|
|
800f75a: 4628 mov r0, r5
|
|
800f75c: 47b8 blx r7
|
|
800f75e: 3001 adds r0, #1
|
|
800f760: f43f af0d beq.w 800f57e <_printf_float+0xb6>
|
|
800f764: f04f 0a00 mov.w sl, #0
|
|
800f768: f104 0b1a add.w fp, r4, #26
|
|
800f76c: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
800f76e: 425b negs r3, r3
|
|
800f770: 4553 cmp r3, sl
|
|
800f772: dc01 bgt.n 800f778 <_printf_float+0x2b0>
|
|
800f774: 464b mov r3, r9
|
|
800f776: e793 b.n 800f6a0 <_printf_float+0x1d8>
|
|
800f778: 2301 movs r3, #1
|
|
800f77a: 465a mov r2, fp
|
|
800f77c: 4631 mov r1, r6
|
|
800f77e: 4628 mov r0, r5
|
|
800f780: 47b8 blx r7
|
|
800f782: 3001 adds r0, #1
|
|
800f784: f43f aefb beq.w 800f57e <_printf_float+0xb6>
|
|
800f788: f10a 0a01 add.w sl, sl, #1
|
|
800f78c: e7ee b.n 800f76c <_printf_float+0x2a4>
|
|
800f78e: bf00 nop
|
|
800f790: 7fefffff .word 0x7fefffff
|
|
800f794: 08014790 .word 0x08014790
|
|
800f798: 0801478c .word 0x0801478c
|
|
800f79c: 08014798 .word 0x08014798
|
|
800f7a0: 08014794 .word 0x08014794
|
|
800f7a4: 0801479c .word 0x0801479c
|
|
800f7a8: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
800f7aa: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
800f7ae: 4553 cmp r3, sl
|
|
800f7b0: bfa8 it ge
|
|
800f7b2: 4653 movge r3, sl
|
|
800f7b4: 2b00 cmp r3, #0
|
|
800f7b6: 4699 mov r9, r3
|
|
800f7b8: dc36 bgt.n 800f828 <_printf_float+0x360>
|
|
800f7ba: f04f 0b00 mov.w fp, #0
|
|
800f7be: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
800f7c2: f104 021a add.w r2, r4, #26
|
|
800f7c6: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
800f7c8: 9306 str r3, [sp, #24]
|
|
800f7ca: eba3 0309 sub.w r3, r3, r9
|
|
800f7ce: 455b cmp r3, fp
|
|
800f7d0: dc31 bgt.n 800f836 <_printf_float+0x36e>
|
|
800f7d2: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
800f7d4: 459a cmp sl, r3
|
|
800f7d6: dc3a bgt.n 800f84e <_printf_float+0x386>
|
|
800f7d8: 6823 ldr r3, [r4, #0]
|
|
800f7da: 07da lsls r2, r3, #31
|
|
800f7dc: d437 bmi.n 800f84e <_printf_float+0x386>
|
|
800f7de: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
800f7e0: ebaa 0903 sub.w r9, sl, r3
|
|
800f7e4: 9b06 ldr r3, [sp, #24]
|
|
800f7e6: ebaa 0303 sub.w r3, sl, r3
|
|
800f7ea: 4599 cmp r9, r3
|
|
800f7ec: bfa8 it ge
|
|
800f7ee: 4699 movge r9, r3
|
|
800f7f0: f1b9 0f00 cmp.w r9, #0
|
|
800f7f4: dc33 bgt.n 800f85e <_printf_float+0x396>
|
|
800f7f6: f04f 0800 mov.w r8, #0
|
|
800f7fa: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
800f7fe: f104 0b1a add.w fp, r4, #26
|
|
800f802: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
800f804: ebaa 0303 sub.w r3, sl, r3
|
|
800f808: eba3 0309 sub.w r3, r3, r9
|
|
800f80c: 4543 cmp r3, r8
|
|
800f80e: f77f af79 ble.w 800f704 <_printf_float+0x23c>
|
|
800f812: 2301 movs r3, #1
|
|
800f814: 465a mov r2, fp
|
|
800f816: 4631 mov r1, r6
|
|
800f818: 4628 mov r0, r5
|
|
800f81a: 47b8 blx r7
|
|
800f81c: 3001 adds r0, #1
|
|
800f81e: f43f aeae beq.w 800f57e <_printf_float+0xb6>
|
|
800f822: f108 0801 add.w r8, r8, #1
|
|
800f826: e7ec b.n 800f802 <_printf_float+0x33a>
|
|
800f828: 4642 mov r2, r8
|
|
800f82a: 4631 mov r1, r6
|
|
800f82c: 4628 mov r0, r5
|
|
800f82e: 47b8 blx r7
|
|
800f830: 3001 adds r0, #1
|
|
800f832: d1c2 bne.n 800f7ba <_printf_float+0x2f2>
|
|
800f834: e6a3 b.n 800f57e <_printf_float+0xb6>
|
|
800f836: 2301 movs r3, #1
|
|
800f838: 4631 mov r1, r6
|
|
800f83a: 4628 mov r0, r5
|
|
800f83c: 9206 str r2, [sp, #24]
|
|
800f83e: 47b8 blx r7
|
|
800f840: 3001 adds r0, #1
|
|
800f842: f43f ae9c beq.w 800f57e <_printf_float+0xb6>
|
|
800f846: 9a06 ldr r2, [sp, #24]
|
|
800f848: f10b 0b01 add.w fp, fp, #1
|
|
800f84c: e7bb b.n 800f7c6 <_printf_float+0x2fe>
|
|
800f84e: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
800f852: 4631 mov r1, r6
|
|
800f854: 4628 mov r0, r5
|
|
800f856: 47b8 blx r7
|
|
800f858: 3001 adds r0, #1
|
|
800f85a: d1c0 bne.n 800f7de <_printf_float+0x316>
|
|
800f85c: e68f b.n 800f57e <_printf_float+0xb6>
|
|
800f85e: 9a06 ldr r2, [sp, #24]
|
|
800f860: 464b mov r3, r9
|
|
800f862: 4442 add r2, r8
|
|
800f864: 4631 mov r1, r6
|
|
800f866: 4628 mov r0, r5
|
|
800f868: 47b8 blx r7
|
|
800f86a: 3001 adds r0, #1
|
|
800f86c: d1c3 bne.n 800f7f6 <_printf_float+0x32e>
|
|
800f86e: e686 b.n 800f57e <_printf_float+0xb6>
|
|
800f870: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
800f874: f1ba 0f01 cmp.w sl, #1
|
|
800f878: dc01 bgt.n 800f87e <_printf_float+0x3b6>
|
|
800f87a: 07db lsls r3, r3, #31
|
|
800f87c: d536 bpl.n 800f8ec <_printf_float+0x424>
|
|
800f87e: 2301 movs r3, #1
|
|
800f880: 4642 mov r2, r8
|
|
800f882: 4631 mov r1, r6
|
|
800f884: 4628 mov r0, r5
|
|
800f886: 47b8 blx r7
|
|
800f888: 3001 adds r0, #1
|
|
800f88a: f43f ae78 beq.w 800f57e <_printf_float+0xb6>
|
|
800f88e: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
800f892: 4631 mov r1, r6
|
|
800f894: 4628 mov r0, r5
|
|
800f896: 47b8 blx r7
|
|
800f898: 3001 adds r0, #1
|
|
800f89a: f43f ae70 beq.w 800f57e <_printf_float+0xb6>
|
|
800f89e: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
800f8a2: 2200 movs r2, #0
|
|
800f8a4: 2300 movs r3, #0
|
|
800f8a6: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
800f8aa: f7f1 f90d bl 8000ac8 <__aeabi_dcmpeq>
|
|
800f8ae: b9c0 cbnz r0, 800f8e2 <_printf_float+0x41a>
|
|
800f8b0: 4653 mov r3, sl
|
|
800f8b2: f108 0201 add.w r2, r8, #1
|
|
800f8b6: 4631 mov r1, r6
|
|
800f8b8: 4628 mov r0, r5
|
|
800f8ba: 47b8 blx r7
|
|
800f8bc: 3001 adds r0, #1
|
|
800f8be: d10c bne.n 800f8da <_printf_float+0x412>
|
|
800f8c0: e65d b.n 800f57e <_printf_float+0xb6>
|
|
800f8c2: 2301 movs r3, #1
|
|
800f8c4: 465a mov r2, fp
|
|
800f8c6: 4631 mov r1, r6
|
|
800f8c8: 4628 mov r0, r5
|
|
800f8ca: 47b8 blx r7
|
|
800f8cc: 3001 adds r0, #1
|
|
800f8ce: f43f ae56 beq.w 800f57e <_printf_float+0xb6>
|
|
800f8d2: f108 0801 add.w r8, r8, #1
|
|
800f8d6: 45d0 cmp r8, sl
|
|
800f8d8: dbf3 blt.n 800f8c2 <_printf_float+0x3fa>
|
|
800f8da: 464b mov r3, r9
|
|
800f8dc: f104 0250 add.w r2, r4, #80 @ 0x50
|
|
800f8e0: e6df b.n 800f6a2 <_printf_float+0x1da>
|
|
800f8e2: f04f 0800 mov.w r8, #0
|
|
800f8e6: f104 0b1a add.w fp, r4, #26
|
|
800f8ea: e7f4 b.n 800f8d6 <_printf_float+0x40e>
|
|
800f8ec: 2301 movs r3, #1
|
|
800f8ee: 4642 mov r2, r8
|
|
800f8f0: e7e1 b.n 800f8b6 <_printf_float+0x3ee>
|
|
800f8f2: 2301 movs r3, #1
|
|
800f8f4: 464a mov r2, r9
|
|
800f8f6: 4631 mov r1, r6
|
|
800f8f8: 4628 mov r0, r5
|
|
800f8fa: 47b8 blx r7
|
|
800f8fc: 3001 adds r0, #1
|
|
800f8fe: f43f ae3e beq.w 800f57e <_printf_float+0xb6>
|
|
800f902: f108 0801 add.w r8, r8, #1
|
|
800f906: 68e3 ldr r3, [r4, #12]
|
|
800f908: 990b ldr r1, [sp, #44] @ 0x2c
|
|
800f90a: 1a5b subs r3, r3, r1
|
|
800f90c: 4543 cmp r3, r8
|
|
800f90e: dcf0 bgt.n 800f8f2 <_printf_float+0x42a>
|
|
800f910: e6fc b.n 800f70c <_printf_float+0x244>
|
|
800f912: f04f 0800 mov.w r8, #0
|
|
800f916: f104 0919 add.w r9, r4, #25
|
|
800f91a: e7f4 b.n 800f906 <_printf_float+0x43e>
|
|
|
|
0800f91c <_printf_common>:
|
|
800f91c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800f920: 4616 mov r6, r2
|
|
800f922: 4698 mov r8, r3
|
|
800f924: 688a ldr r2, [r1, #8]
|
|
800f926: 690b ldr r3, [r1, #16]
|
|
800f928: f8dd 9020 ldr.w r9, [sp, #32]
|
|
800f92c: 4293 cmp r3, r2
|
|
800f92e: bfb8 it lt
|
|
800f930: 4613 movlt r3, r2
|
|
800f932: 6033 str r3, [r6, #0]
|
|
800f934: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
|
|
800f938: 4607 mov r7, r0
|
|
800f93a: 460c mov r4, r1
|
|
800f93c: b10a cbz r2, 800f942 <_printf_common+0x26>
|
|
800f93e: 3301 adds r3, #1
|
|
800f940: 6033 str r3, [r6, #0]
|
|
800f942: 6823 ldr r3, [r4, #0]
|
|
800f944: 0699 lsls r1, r3, #26
|
|
800f946: bf42 ittt mi
|
|
800f948: 6833 ldrmi r3, [r6, #0]
|
|
800f94a: 3302 addmi r3, #2
|
|
800f94c: 6033 strmi r3, [r6, #0]
|
|
800f94e: 6825 ldr r5, [r4, #0]
|
|
800f950: f015 0506 ands.w r5, r5, #6
|
|
800f954: d106 bne.n 800f964 <_printf_common+0x48>
|
|
800f956: f104 0a19 add.w sl, r4, #25
|
|
800f95a: 68e3 ldr r3, [r4, #12]
|
|
800f95c: 6832 ldr r2, [r6, #0]
|
|
800f95e: 1a9b subs r3, r3, r2
|
|
800f960: 42ab cmp r3, r5
|
|
800f962: dc26 bgt.n 800f9b2 <_printf_common+0x96>
|
|
800f964: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
|
|
800f968: 6822 ldr r2, [r4, #0]
|
|
800f96a: 3b00 subs r3, #0
|
|
800f96c: bf18 it ne
|
|
800f96e: 2301 movne r3, #1
|
|
800f970: 0692 lsls r2, r2, #26
|
|
800f972: d42b bmi.n 800f9cc <_printf_common+0xb0>
|
|
800f974: f104 0243 add.w r2, r4, #67 @ 0x43
|
|
800f978: 4641 mov r1, r8
|
|
800f97a: 4638 mov r0, r7
|
|
800f97c: 47c8 blx r9
|
|
800f97e: 3001 adds r0, #1
|
|
800f980: d01e beq.n 800f9c0 <_printf_common+0xa4>
|
|
800f982: 6823 ldr r3, [r4, #0]
|
|
800f984: 6922 ldr r2, [r4, #16]
|
|
800f986: f003 0306 and.w r3, r3, #6
|
|
800f98a: 2b04 cmp r3, #4
|
|
800f98c: bf02 ittt eq
|
|
800f98e: 68e5 ldreq r5, [r4, #12]
|
|
800f990: 6833 ldreq r3, [r6, #0]
|
|
800f992: 1aed subeq r5, r5, r3
|
|
800f994: 68a3 ldr r3, [r4, #8]
|
|
800f996: bf0c ite eq
|
|
800f998: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
800f99c: 2500 movne r5, #0
|
|
800f99e: 4293 cmp r3, r2
|
|
800f9a0: bfc4 itt gt
|
|
800f9a2: 1a9b subgt r3, r3, r2
|
|
800f9a4: 18ed addgt r5, r5, r3
|
|
800f9a6: 2600 movs r6, #0
|
|
800f9a8: 341a adds r4, #26
|
|
800f9aa: 42b5 cmp r5, r6
|
|
800f9ac: d11a bne.n 800f9e4 <_printf_common+0xc8>
|
|
800f9ae: 2000 movs r0, #0
|
|
800f9b0: e008 b.n 800f9c4 <_printf_common+0xa8>
|
|
800f9b2: 2301 movs r3, #1
|
|
800f9b4: 4652 mov r2, sl
|
|
800f9b6: 4641 mov r1, r8
|
|
800f9b8: 4638 mov r0, r7
|
|
800f9ba: 47c8 blx r9
|
|
800f9bc: 3001 adds r0, #1
|
|
800f9be: d103 bne.n 800f9c8 <_printf_common+0xac>
|
|
800f9c0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800f9c4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800f9c8: 3501 adds r5, #1
|
|
800f9ca: e7c6 b.n 800f95a <_printf_common+0x3e>
|
|
800f9cc: 18e1 adds r1, r4, r3
|
|
800f9ce: 1c5a adds r2, r3, #1
|
|
800f9d0: 2030 movs r0, #48 @ 0x30
|
|
800f9d2: f881 0043 strb.w r0, [r1, #67] @ 0x43
|
|
800f9d6: 4422 add r2, r4
|
|
800f9d8: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
|
|
800f9dc: f882 1043 strb.w r1, [r2, #67] @ 0x43
|
|
800f9e0: 3302 adds r3, #2
|
|
800f9e2: e7c7 b.n 800f974 <_printf_common+0x58>
|
|
800f9e4: 2301 movs r3, #1
|
|
800f9e6: 4622 mov r2, r4
|
|
800f9e8: 4641 mov r1, r8
|
|
800f9ea: 4638 mov r0, r7
|
|
800f9ec: 47c8 blx r9
|
|
800f9ee: 3001 adds r0, #1
|
|
800f9f0: d0e6 beq.n 800f9c0 <_printf_common+0xa4>
|
|
800f9f2: 3601 adds r6, #1
|
|
800f9f4: e7d9 b.n 800f9aa <_printf_common+0x8e>
|
|
...
|
|
|
|
0800f9f8 <_printf_i>:
|
|
800f9f8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800f9fc: 7e0f ldrb r7, [r1, #24]
|
|
800f9fe: 9e0c ldr r6, [sp, #48] @ 0x30
|
|
800fa00: 2f78 cmp r7, #120 @ 0x78
|
|
800fa02: 4691 mov r9, r2
|
|
800fa04: 4680 mov r8, r0
|
|
800fa06: 460c mov r4, r1
|
|
800fa08: 469a mov sl, r3
|
|
800fa0a: f101 0243 add.w r2, r1, #67 @ 0x43
|
|
800fa0e: d807 bhi.n 800fa20 <_printf_i+0x28>
|
|
800fa10: 2f62 cmp r7, #98 @ 0x62
|
|
800fa12: d80a bhi.n 800fa2a <_printf_i+0x32>
|
|
800fa14: 2f00 cmp r7, #0
|
|
800fa16: f000 80d1 beq.w 800fbbc <_printf_i+0x1c4>
|
|
800fa1a: 2f58 cmp r7, #88 @ 0x58
|
|
800fa1c: f000 80b8 beq.w 800fb90 <_printf_i+0x198>
|
|
800fa20: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
800fa24: f884 7042 strb.w r7, [r4, #66] @ 0x42
|
|
800fa28: e03a b.n 800faa0 <_printf_i+0xa8>
|
|
800fa2a: f1a7 0363 sub.w r3, r7, #99 @ 0x63
|
|
800fa2e: 2b15 cmp r3, #21
|
|
800fa30: d8f6 bhi.n 800fa20 <_printf_i+0x28>
|
|
800fa32: a101 add r1, pc, #4 @ (adr r1, 800fa38 <_printf_i+0x40>)
|
|
800fa34: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
800fa38: 0800fa91 .word 0x0800fa91
|
|
800fa3c: 0800faa5 .word 0x0800faa5
|
|
800fa40: 0800fa21 .word 0x0800fa21
|
|
800fa44: 0800fa21 .word 0x0800fa21
|
|
800fa48: 0800fa21 .word 0x0800fa21
|
|
800fa4c: 0800fa21 .word 0x0800fa21
|
|
800fa50: 0800faa5 .word 0x0800faa5
|
|
800fa54: 0800fa21 .word 0x0800fa21
|
|
800fa58: 0800fa21 .word 0x0800fa21
|
|
800fa5c: 0800fa21 .word 0x0800fa21
|
|
800fa60: 0800fa21 .word 0x0800fa21
|
|
800fa64: 0800fba3 .word 0x0800fba3
|
|
800fa68: 0800facf .word 0x0800facf
|
|
800fa6c: 0800fb5d .word 0x0800fb5d
|
|
800fa70: 0800fa21 .word 0x0800fa21
|
|
800fa74: 0800fa21 .word 0x0800fa21
|
|
800fa78: 0800fbc5 .word 0x0800fbc5
|
|
800fa7c: 0800fa21 .word 0x0800fa21
|
|
800fa80: 0800facf .word 0x0800facf
|
|
800fa84: 0800fa21 .word 0x0800fa21
|
|
800fa88: 0800fa21 .word 0x0800fa21
|
|
800fa8c: 0800fb65 .word 0x0800fb65
|
|
800fa90: 6833 ldr r3, [r6, #0]
|
|
800fa92: 1d1a adds r2, r3, #4
|
|
800fa94: 681b ldr r3, [r3, #0]
|
|
800fa96: 6032 str r2, [r6, #0]
|
|
800fa98: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
800fa9c: f884 3042 strb.w r3, [r4, #66] @ 0x42
|
|
800faa0: 2301 movs r3, #1
|
|
800faa2: e09c b.n 800fbde <_printf_i+0x1e6>
|
|
800faa4: 6833 ldr r3, [r6, #0]
|
|
800faa6: 6820 ldr r0, [r4, #0]
|
|
800faa8: 1d19 adds r1, r3, #4
|
|
800faaa: 6031 str r1, [r6, #0]
|
|
800faac: 0606 lsls r6, r0, #24
|
|
800faae: d501 bpl.n 800fab4 <_printf_i+0xbc>
|
|
800fab0: 681d ldr r5, [r3, #0]
|
|
800fab2: e003 b.n 800fabc <_printf_i+0xc4>
|
|
800fab4: 0645 lsls r5, r0, #25
|
|
800fab6: d5fb bpl.n 800fab0 <_printf_i+0xb8>
|
|
800fab8: f9b3 5000 ldrsh.w r5, [r3]
|
|
800fabc: 2d00 cmp r5, #0
|
|
800fabe: da03 bge.n 800fac8 <_printf_i+0xd0>
|
|
800fac0: 232d movs r3, #45 @ 0x2d
|
|
800fac2: 426d negs r5, r5
|
|
800fac4: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
800fac8: 4858 ldr r0, [pc, #352] @ (800fc2c <_printf_i+0x234>)
|
|
800faca: 230a movs r3, #10
|
|
800facc: e011 b.n 800faf2 <_printf_i+0xfa>
|
|
800face: 6821 ldr r1, [r4, #0]
|
|
800fad0: 6833 ldr r3, [r6, #0]
|
|
800fad2: 0608 lsls r0, r1, #24
|
|
800fad4: f853 5b04 ldr.w r5, [r3], #4
|
|
800fad8: d402 bmi.n 800fae0 <_printf_i+0xe8>
|
|
800fada: 0649 lsls r1, r1, #25
|
|
800fadc: bf48 it mi
|
|
800fade: b2ad uxthmi r5, r5
|
|
800fae0: 2f6f cmp r7, #111 @ 0x6f
|
|
800fae2: 4852 ldr r0, [pc, #328] @ (800fc2c <_printf_i+0x234>)
|
|
800fae4: 6033 str r3, [r6, #0]
|
|
800fae6: bf14 ite ne
|
|
800fae8: 230a movne r3, #10
|
|
800faea: 2308 moveq r3, #8
|
|
800faec: 2100 movs r1, #0
|
|
800faee: f884 1043 strb.w r1, [r4, #67] @ 0x43
|
|
800faf2: 6866 ldr r6, [r4, #4]
|
|
800faf4: 60a6 str r6, [r4, #8]
|
|
800faf6: 2e00 cmp r6, #0
|
|
800faf8: db05 blt.n 800fb06 <_printf_i+0x10e>
|
|
800fafa: 6821 ldr r1, [r4, #0]
|
|
800fafc: 432e orrs r6, r5
|
|
800fafe: f021 0104 bic.w r1, r1, #4
|
|
800fb02: 6021 str r1, [r4, #0]
|
|
800fb04: d04b beq.n 800fb9e <_printf_i+0x1a6>
|
|
800fb06: 4616 mov r6, r2
|
|
800fb08: fbb5 f1f3 udiv r1, r5, r3
|
|
800fb0c: fb03 5711 mls r7, r3, r1, r5
|
|
800fb10: 5dc7 ldrb r7, [r0, r7]
|
|
800fb12: f806 7d01 strb.w r7, [r6, #-1]!
|
|
800fb16: 462f mov r7, r5
|
|
800fb18: 42bb cmp r3, r7
|
|
800fb1a: 460d mov r5, r1
|
|
800fb1c: d9f4 bls.n 800fb08 <_printf_i+0x110>
|
|
800fb1e: 2b08 cmp r3, #8
|
|
800fb20: d10b bne.n 800fb3a <_printf_i+0x142>
|
|
800fb22: 6823 ldr r3, [r4, #0]
|
|
800fb24: 07df lsls r7, r3, #31
|
|
800fb26: d508 bpl.n 800fb3a <_printf_i+0x142>
|
|
800fb28: 6923 ldr r3, [r4, #16]
|
|
800fb2a: 6861 ldr r1, [r4, #4]
|
|
800fb2c: 4299 cmp r1, r3
|
|
800fb2e: bfde ittt le
|
|
800fb30: 2330 movle r3, #48 @ 0x30
|
|
800fb32: f806 3c01 strble.w r3, [r6, #-1]
|
|
800fb36: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
|
|
800fb3a: 1b92 subs r2, r2, r6
|
|
800fb3c: 6122 str r2, [r4, #16]
|
|
800fb3e: f8cd a000 str.w sl, [sp]
|
|
800fb42: 464b mov r3, r9
|
|
800fb44: aa03 add r2, sp, #12
|
|
800fb46: 4621 mov r1, r4
|
|
800fb48: 4640 mov r0, r8
|
|
800fb4a: f7ff fee7 bl 800f91c <_printf_common>
|
|
800fb4e: 3001 adds r0, #1
|
|
800fb50: d14a bne.n 800fbe8 <_printf_i+0x1f0>
|
|
800fb52: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800fb56: b004 add sp, #16
|
|
800fb58: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800fb5c: 6823 ldr r3, [r4, #0]
|
|
800fb5e: f043 0320 orr.w r3, r3, #32
|
|
800fb62: 6023 str r3, [r4, #0]
|
|
800fb64: 4832 ldr r0, [pc, #200] @ (800fc30 <_printf_i+0x238>)
|
|
800fb66: 2778 movs r7, #120 @ 0x78
|
|
800fb68: f884 7045 strb.w r7, [r4, #69] @ 0x45
|
|
800fb6c: 6823 ldr r3, [r4, #0]
|
|
800fb6e: 6831 ldr r1, [r6, #0]
|
|
800fb70: 061f lsls r7, r3, #24
|
|
800fb72: f851 5b04 ldr.w r5, [r1], #4
|
|
800fb76: d402 bmi.n 800fb7e <_printf_i+0x186>
|
|
800fb78: 065f lsls r7, r3, #25
|
|
800fb7a: bf48 it mi
|
|
800fb7c: b2ad uxthmi r5, r5
|
|
800fb7e: 6031 str r1, [r6, #0]
|
|
800fb80: 07d9 lsls r1, r3, #31
|
|
800fb82: bf44 itt mi
|
|
800fb84: f043 0320 orrmi.w r3, r3, #32
|
|
800fb88: 6023 strmi r3, [r4, #0]
|
|
800fb8a: b11d cbz r5, 800fb94 <_printf_i+0x19c>
|
|
800fb8c: 2310 movs r3, #16
|
|
800fb8e: e7ad b.n 800faec <_printf_i+0xf4>
|
|
800fb90: 4826 ldr r0, [pc, #152] @ (800fc2c <_printf_i+0x234>)
|
|
800fb92: e7e9 b.n 800fb68 <_printf_i+0x170>
|
|
800fb94: 6823 ldr r3, [r4, #0]
|
|
800fb96: f023 0320 bic.w r3, r3, #32
|
|
800fb9a: 6023 str r3, [r4, #0]
|
|
800fb9c: e7f6 b.n 800fb8c <_printf_i+0x194>
|
|
800fb9e: 4616 mov r6, r2
|
|
800fba0: e7bd b.n 800fb1e <_printf_i+0x126>
|
|
800fba2: 6833 ldr r3, [r6, #0]
|
|
800fba4: 6825 ldr r5, [r4, #0]
|
|
800fba6: 6961 ldr r1, [r4, #20]
|
|
800fba8: 1d18 adds r0, r3, #4
|
|
800fbaa: 6030 str r0, [r6, #0]
|
|
800fbac: 062e lsls r6, r5, #24
|
|
800fbae: 681b ldr r3, [r3, #0]
|
|
800fbb0: d501 bpl.n 800fbb6 <_printf_i+0x1be>
|
|
800fbb2: 6019 str r1, [r3, #0]
|
|
800fbb4: e002 b.n 800fbbc <_printf_i+0x1c4>
|
|
800fbb6: 0668 lsls r0, r5, #25
|
|
800fbb8: d5fb bpl.n 800fbb2 <_printf_i+0x1ba>
|
|
800fbba: 8019 strh r1, [r3, #0]
|
|
800fbbc: 2300 movs r3, #0
|
|
800fbbe: 6123 str r3, [r4, #16]
|
|
800fbc0: 4616 mov r6, r2
|
|
800fbc2: e7bc b.n 800fb3e <_printf_i+0x146>
|
|
800fbc4: 6833 ldr r3, [r6, #0]
|
|
800fbc6: 1d1a adds r2, r3, #4
|
|
800fbc8: 6032 str r2, [r6, #0]
|
|
800fbca: 681e ldr r6, [r3, #0]
|
|
800fbcc: 6862 ldr r2, [r4, #4]
|
|
800fbce: 2100 movs r1, #0
|
|
800fbd0: 4630 mov r0, r6
|
|
800fbd2: f7f0 fafd bl 80001d0 <memchr>
|
|
800fbd6: b108 cbz r0, 800fbdc <_printf_i+0x1e4>
|
|
800fbd8: 1b80 subs r0, r0, r6
|
|
800fbda: 6060 str r0, [r4, #4]
|
|
800fbdc: 6863 ldr r3, [r4, #4]
|
|
800fbde: 6123 str r3, [r4, #16]
|
|
800fbe0: 2300 movs r3, #0
|
|
800fbe2: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
800fbe6: e7aa b.n 800fb3e <_printf_i+0x146>
|
|
800fbe8: 6923 ldr r3, [r4, #16]
|
|
800fbea: 4632 mov r2, r6
|
|
800fbec: 4649 mov r1, r9
|
|
800fbee: 4640 mov r0, r8
|
|
800fbf0: 47d0 blx sl
|
|
800fbf2: 3001 adds r0, #1
|
|
800fbf4: d0ad beq.n 800fb52 <_printf_i+0x15a>
|
|
800fbf6: 6823 ldr r3, [r4, #0]
|
|
800fbf8: 079b lsls r3, r3, #30
|
|
800fbfa: d413 bmi.n 800fc24 <_printf_i+0x22c>
|
|
800fbfc: 68e0 ldr r0, [r4, #12]
|
|
800fbfe: 9b03 ldr r3, [sp, #12]
|
|
800fc00: 4298 cmp r0, r3
|
|
800fc02: bfb8 it lt
|
|
800fc04: 4618 movlt r0, r3
|
|
800fc06: e7a6 b.n 800fb56 <_printf_i+0x15e>
|
|
800fc08: 2301 movs r3, #1
|
|
800fc0a: 4632 mov r2, r6
|
|
800fc0c: 4649 mov r1, r9
|
|
800fc0e: 4640 mov r0, r8
|
|
800fc10: 47d0 blx sl
|
|
800fc12: 3001 adds r0, #1
|
|
800fc14: d09d beq.n 800fb52 <_printf_i+0x15a>
|
|
800fc16: 3501 adds r5, #1
|
|
800fc18: 68e3 ldr r3, [r4, #12]
|
|
800fc1a: 9903 ldr r1, [sp, #12]
|
|
800fc1c: 1a5b subs r3, r3, r1
|
|
800fc1e: 42ab cmp r3, r5
|
|
800fc20: dcf2 bgt.n 800fc08 <_printf_i+0x210>
|
|
800fc22: e7eb b.n 800fbfc <_printf_i+0x204>
|
|
800fc24: 2500 movs r5, #0
|
|
800fc26: f104 0619 add.w r6, r4, #25
|
|
800fc2a: e7f5 b.n 800fc18 <_printf_i+0x220>
|
|
800fc2c: 0801479e .word 0x0801479e
|
|
800fc30: 080147af .word 0x080147af
|
|
|
|
0800fc34 <_scanf_float>:
|
|
800fc34: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800fc38: b087 sub sp, #28
|
|
800fc3a: 4691 mov r9, r2
|
|
800fc3c: 9303 str r3, [sp, #12]
|
|
800fc3e: 688b ldr r3, [r1, #8]
|
|
800fc40: 1e5a subs r2, r3, #1
|
|
800fc42: f5b2 7fae cmp.w r2, #348 @ 0x15c
|
|
800fc46: bf81 itttt hi
|
|
800fc48: f46f 75ae mvnhi.w r5, #348 @ 0x15c
|
|
800fc4c: eb03 0b05 addhi.w fp, r3, r5
|
|
800fc50: f240 135d movwhi r3, #349 @ 0x15d
|
|
800fc54: 608b strhi r3, [r1, #8]
|
|
800fc56: 680b ldr r3, [r1, #0]
|
|
800fc58: 460a mov r2, r1
|
|
800fc5a: f04f 0500 mov.w r5, #0
|
|
800fc5e: f443 63f0 orr.w r3, r3, #1920 @ 0x780
|
|
800fc62: f842 3b1c str.w r3, [r2], #28
|
|
800fc66: e9cd 5504 strd r5, r5, [sp, #16]
|
|
800fc6a: 4680 mov r8, r0
|
|
800fc6c: 460c mov r4, r1
|
|
800fc6e: bf98 it ls
|
|
800fc70: f04f 0b00 movls.w fp, #0
|
|
800fc74: 9201 str r2, [sp, #4]
|
|
800fc76: 4616 mov r6, r2
|
|
800fc78: 46aa mov sl, r5
|
|
800fc7a: 462f mov r7, r5
|
|
800fc7c: 9502 str r5, [sp, #8]
|
|
800fc7e: 68a2 ldr r2, [r4, #8]
|
|
800fc80: b15a cbz r2, 800fc9a <_scanf_float+0x66>
|
|
800fc82: f8d9 3000 ldr.w r3, [r9]
|
|
800fc86: 781b ldrb r3, [r3, #0]
|
|
800fc88: 2b4e cmp r3, #78 @ 0x4e
|
|
800fc8a: d863 bhi.n 800fd54 <_scanf_float+0x120>
|
|
800fc8c: 2b40 cmp r3, #64 @ 0x40
|
|
800fc8e: d83b bhi.n 800fd08 <_scanf_float+0xd4>
|
|
800fc90: f1a3 012b sub.w r1, r3, #43 @ 0x2b
|
|
800fc94: b2c8 uxtb r0, r1
|
|
800fc96: 280e cmp r0, #14
|
|
800fc98: d939 bls.n 800fd0e <_scanf_float+0xda>
|
|
800fc9a: b11f cbz r7, 800fca4 <_scanf_float+0x70>
|
|
800fc9c: 6823 ldr r3, [r4, #0]
|
|
800fc9e: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800fca2: 6023 str r3, [r4, #0]
|
|
800fca4: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
800fca8: f1ba 0f01 cmp.w sl, #1
|
|
800fcac: f200 8114 bhi.w 800fed8 <_scanf_float+0x2a4>
|
|
800fcb0: 9b01 ldr r3, [sp, #4]
|
|
800fcb2: 429e cmp r6, r3
|
|
800fcb4: f200 8105 bhi.w 800fec2 <_scanf_float+0x28e>
|
|
800fcb8: 2001 movs r0, #1
|
|
800fcba: b007 add sp, #28
|
|
800fcbc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800fcc0: f1a3 0261 sub.w r2, r3, #97 @ 0x61
|
|
800fcc4: 2a0d cmp r2, #13
|
|
800fcc6: d8e8 bhi.n 800fc9a <_scanf_float+0x66>
|
|
800fcc8: a101 add r1, pc, #4 @ (adr r1, 800fcd0 <_scanf_float+0x9c>)
|
|
800fcca: f851 f022 ldr.w pc, [r1, r2, lsl #2]
|
|
800fcce: bf00 nop
|
|
800fcd0: 0800fe19 .word 0x0800fe19
|
|
800fcd4: 0800fc9b .word 0x0800fc9b
|
|
800fcd8: 0800fc9b .word 0x0800fc9b
|
|
800fcdc: 0800fc9b .word 0x0800fc9b
|
|
800fce0: 0800fe75 .word 0x0800fe75
|
|
800fce4: 0800fe4f .word 0x0800fe4f
|
|
800fce8: 0800fc9b .word 0x0800fc9b
|
|
800fcec: 0800fc9b .word 0x0800fc9b
|
|
800fcf0: 0800fe27 .word 0x0800fe27
|
|
800fcf4: 0800fc9b .word 0x0800fc9b
|
|
800fcf8: 0800fc9b .word 0x0800fc9b
|
|
800fcfc: 0800fc9b .word 0x0800fc9b
|
|
800fd00: 0800fc9b .word 0x0800fc9b
|
|
800fd04: 0800fde3 .word 0x0800fde3
|
|
800fd08: f1a3 0241 sub.w r2, r3, #65 @ 0x41
|
|
800fd0c: e7da b.n 800fcc4 <_scanf_float+0x90>
|
|
800fd0e: 290e cmp r1, #14
|
|
800fd10: d8c3 bhi.n 800fc9a <_scanf_float+0x66>
|
|
800fd12: a001 add r0, pc, #4 @ (adr r0, 800fd18 <_scanf_float+0xe4>)
|
|
800fd14: f850 f021 ldr.w pc, [r0, r1, lsl #2]
|
|
800fd18: 0800fdd3 .word 0x0800fdd3
|
|
800fd1c: 0800fc9b .word 0x0800fc9b
|
|
800fd20: 0800fdd3 .word 0x0800fdd3
|
|
800fd24: 0800fe63 .word 0x0800fe63
|
|
800fd28: 0800fc9b .word 0x0800fc9b
|
|
800fd2c: 0800fd75 .word 0x0800fd75
|
|
800fd30: 0800fdb9 .word 0x0800fdb9
|
|
800fd34: 0800fdb9 .word 0x0800fdb9
|
|
800fd38: 0800fdb9 .word 0x0800fdb9
|
|
800fd3c: 0800fdb9 .word 0x0800fdb9
|
|
800fd40: 0800fdb9 .word 0x0800fdb9
|
|
800fd44: 0800fdb9 .word 0x0800fdb9
|
|
800fd48: 0800fdb9 .word 0x0800fdb9
|
|
800fd4c: 0800fdb9 .word 0x0800fdb9
|
|
800fd50: 0800fdb9 .word 0x0800fdb9
|
|
800fd54: 2b6e cmp r3, #110 @ 0x6e
|
|
800fd56: d809 bhi.n 800fd6c <_scanf_float+0x138>
|
|
800fd58: 2b60 cmp r3, #96 @ 0x60
|
|
800fd5a: d8b1 bhi.n 800fcc0 <_scanf_float+0x8c>
|
|
800fd5c: 2b54 cmp r3, #84 @ 0x54
|
|
800fd5e: d07b beq.n 800fe58 <_scanf_float+0x224>
|
|
800fd60: 2b59 cmp r3, #89 @ 0x59
|
|
800fd62: d19a bne.n 800fc9a <_scanf_float+0x66>
|
|
800fd64: 2d07 cmp r5, #7
|
|
800fd66: d198 bne.n 800fc9a <_scanf_float+0x66>
|
|
800fd68: 2508 movs r5, #8
|
|
800fd6a: e02f b.n 800fdcc <_scanf_float+0x198>
|
|
800fd6c: 2b74 cmp r3, #116 @ 0x74
|
|
800fd6e: d073 beq.n 800fe58 <_scanf_float+0x224>
|
|
800fd70: 2b79 cmp r3, #121 @ 0x79
|
|
800fd72: e7f6 b.n 800fd62 <_scanf_float+0x12e>
|
|
800fd74: 6821 ldr r1, [r4, #0]
|
|
800fd76: 05c8 lsls r0, r1, #23
|
|
800fd78: d51e bpl.n 800fdb8 <_scanf_float+0x184>
|
|
800fd7a: f021 0180 bic.w r1, r1, #128 @ 0x80
|
|
800fd7e: 6021 str r1, [r4, #0]
|
|
800fd80: 3701 adds r7, #1
|
|
800fd82: f1bb 0f00 cmp.w fp, #0
|
|
800fd86: d003 beq.n 800fd90 <_scanf_float+0x15c>
|
|
800fd88: 3201 adds r2, #1
|
|
800fd8a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff
|
|
800fd8e: 60a2 str r2, [r4, #8]
|
|
800fd90: 68a3 ldr r3, [r4, #8]
|
|
800fd92: 3b01 subs r3, #1
|
|
800fd94: 60a3 str r3, [r4, #8]
|
|
800fd96: 6923 ldr r3, [r4, #16]
|
|
800fd98: 3301 adds r3, #1
|
|
800fd9a: 6123 str r3, [r4, #16]
|
|
800fd9c: f8d9 3004 ldr.w r3, [r9, #4]
|
|
800fda0: 3b01 subs r3, #1
|
|
800fda2: 2b00 cmp r3, #0
|
|
800fda4: f8c9 3004 str.w r3, [r9, #4]
|
|
800fda8: f340 8082 ble.w 800feb0 <_scanf_float+0x27c>
|
|
800fdac: f8d9 3000 ldr.w r3, [r9]
|
|
800fdb0: 3301 adds r3, #1
|
|
800fdb2: f8c9 3000 str.w r3, [r9]
|
|
800fdb6: e762 b.n 800fc7e <_scanf_float+0x4a>
|
|
800fdb8: eb1a 0105 adds.w r1, sl, r5
|
|
800fdbc: f47f af6d bne.w 800fc9a <_scanf_float+0x66>
|
|
800fdc0: 6822 ldr r2, [r4, #0]
|
|
800fdc2: f422 72c0 bic.w r2, r2, #384 @ 0x180
|
|
800fdc6: 6022 str r2, [r4, #0]
|
|
800fdc8: 460d mov r5, r1
|
|
800fdca: 468a mov sl, r1
|
|
800fdcc: f806 3b01 strb.w r3, [r6], #1
|
|
800fdd0: e7de b.n 800fd90 <_scanf_float+0x15c>
|
|
800fdd2: 6822 ldr r2, [r4, #0]
|
|
800fdd4: 0610 lsls r0, r2, #24
|
|
800fdd6: f57f af60 bpl.w 800fc9a <_scanf_float+0x66>
|
|
800fdda: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
800fdde: 6022 str r2, [r4, #0]
|
|
800fde0: e7f4 b.n 800fdcc <_scanf_float+0x198>
|
|
800fde2: f1ba 0f00 cmp.w sl, #0
|
|
800fde6: d10c bne.n 800fe02 <_scanf_float+0x1ce>
|
|
800fde8: b977 cbnz r7, 800fe08 <_scanf_float+0x1d4>
|
|
800fdea: 6822 ldr r2, [r4, #0]
|
|
800fdec: f402 61e0 and.w r1, r2, #1792 @ 0x700
|
|
800fdf0: f5b1 6fe0 cmp.w r1, #1792 @ 0x700
|
|
800fdf4: d108 bne.n 800fe08 <_scanf_float+0x1d4>
|
|
800fdf6: f422 62f0 bic.w r2, r2, #1920 @ 0x780
|
|
800fdfa: 6022 str r2, [r4, #0]
|
|
800fdfc: f04f 0a01 mov.w sl, #1
|
|
800fe00: e7e4 b.n 800fdcc <_scanf_float+0x198>
|
|
800fe02: f1ba 0f02 cmp.w sl, #2
|
|
800fe06: d050 beq.n 800feaa <_scanf_float+0x276>
|
|
800fe08: 2d01 cmp r5, #1
|
|
800fe0a: d002 beq.n 800fe12 <_scanf_float+0x1de>
|
|
800fe0c: 2d04 cmp r5, #4
|
|
800fe0e: f47f af44 bne.w 800fc9a <_scanf_float+0x66>
|
|
800fe12: 3501 adds r5, #1
|
|
800fe14: b2ed uxtb r5, r5
|
|
800fe16: e7d9 b.n 800fdcc <_scanf_float+0x198>
|
|
800fe18: f1ba 0f01 cmp.w sl, #1
|
|
800fe1c: f47f af3d bne.w 800fc9a <_scanf_float+0x66>
|
|
800fe20: f04f 0a02 mov.w sl, #2
|
|
800fe24: e7d2 b.n 800fdcc <_scanf_float+0x198>
|
|
800fe26: b975 cbnz r5, 800fe46 <_scanf_float+0x212>
|
|
800fe28: 2f00 cmp r7, #0
|
|
800fe2a: f47f af37 bne.w 800fc9c <_scanf_float+0x68>
|
|
800fe2e: 6822 ldr r2, [r4, #0]
|
|
800fe30: f402 61e0 and.w r1, r2, #1792 @ 0x700
|
|
800fe34: f5b1 6fe0 cmp.w r1, #1792 @ 0x700
|
|
800fe38: f040 8103 bne.w 8010042 <_scanf_float+0x40e>
|
|
800fe3c: f422 62f0 bic.w r2, r2, #1920 @ 0x780
|
|
800fe40: 6022 str r2, [r4, #0]
|
|
800fe42: 2501 movs r5, #1
|
|
800fe44: e7c2 b.n 800fdcc <_scanf_float+0x198>
|
|
800fe46: 2d03 cmp r5, #3
|
|
800fe48: d0e3 beq.n 800fe12 <_scanf_float+0x1de>
|
|
800fe4a: 2d05 cmp r5, #5
|
|
800fe4c: e7df b.n 800fe0e <_scanf_float+0x1da>
|
|
800fe4e: 2d02 cmp r5, #2
|
|
800fe50: f47f af23 bne.w 800fc9a <_scanf_float+0x66>
|
|
800fe54: 2503 movs r5, #3
|
|
800fe56: e7b9 b.n 800fdcc <_scanf_float+0x198>
|
|
800fe58: 2d06 cmp r5, #6
|
|
800fe5a: f47f af1e bne.w 800fc9a <_scanf_float+0x66>
|
|
800fe5e: 2507 movs r5, #7
|
|
800fe60: e7b4 b.n 800fdcc <_scanf_float+0x198>
|
|
800fe62: 6822 ldr r2, [r4, #0]
|
|
800fe64: 0591 lsls r1, r2, #22
|
|
800fe66: f57f af18 bpl.w 800fc9a <_scanf_float+0x66>
|
|
800fe6a: f422 7220 bic.w r2, r2, #640 @ 0x280
|
|
800fe6e: 6022 str r2, [r4, #0]
|
|
800fe70: 9702 str r7, [sp, #8]
|
|
800fe72: e7ab b.n 800fdcc <_scanf_float+0x198>
|
|
800fe74: 6822 ldr r2, [r4, #0]
|
|
800fe76: f402 61a0 and.w r1, r2, #1280 @ 0x500
|
|
800fe7a: f5b1 6f80 cmp.w r1, #1024 @ 0x400
|
|
800fe7e: d005 beq.n 800fe8c <_scanf_float+0x258>
|
|
800fe80: 0550 lsls r0, r2, #21
|
|
800fe82: f57f af0a bpl.w 800fc9a <_scanf_float+0x66>
|
|
800fe86: 2f00 cmp r7, #0
|
|
800fe88: f000 80db beq.w 8010042 <_scanf_float+0x40e>
|
|
800fe8c: 0591 lsls r1, r2, #22
|
|
800fe8e: bf58 it pl
|
|
800fe90: 9902 ldrpl r1, [sp, #8]
|
|
800fe92: f422 62f0 bic.w r2, r2, #1920 @ 0x780
|
|
800fe96: bf58 it pl
|
|
800fe98: 1a79 subpl r1, r7, r1
|
|
800fe9a: f442 72c0 orr.w r2, r2, #384 @ 0x180
|
|
800fe9e: bf58 it pl
|
|
800fea0: e9cd 1604 strdpl r1, r6, [sp, #16]
|
|
800fea4: 6022 str r2, [r4, #0]
|
|
800fea6: 2700 movs r7, #0
|
|
800fea8: e790 b.n 800fdcc <_scanf_float+0x198>
|
|
800feaa: f04f 0a03 mov.w sl, #3
|
|
800feae: e78d b.n 800fdcc <_scanf_float+0x198>
|
|
800feb0: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180
|
|
800feb4: 4649 mov r1, r9
|
|
800feb6: 4640 mov r0, r8
|
|
800feb8: 4798 blx r3
|
|
800feba: 2800 cmp r0, #0
|
|
800febc: f43f aedf beq.w 800fc7e <_scanf_float+0x4a>
|
|
800fec0: e6eb b.n 800fc9a <_scanf_float+0x66>
|
|
800fec2: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
800fec6: f816 1d01 ldrb.w r1, [r6, #-1]!
|
|
800feca: 464a mov r2, r9
|
|
800fecc: 4640 mov r0, r8
|
|
800fece: 4798 blx r3
|
|
800fed0: 6923 ldr r3, [r4, #16]
|
|
800fed2: 3b01 subs r3, #1
|
|
800fed4: 6123 str r3, [r4, #16]
|
|
800fed6: e6eb b.n 800fcb0 <_scanf_float+0x7c>
|
|
800fed8: 1e6b subs r3, r5, #1
|
|
800feda: 2b06 cmp r3, #6
|
|
800fedc: d824 bhi.n 800ff28 <_scanf_float+0x2f4>
|
|
800fede: 2d02 cmp r5, #2
|
|
800fee0: d836 bhi.n 800ff50 <_scanf_float+0x31c>
|
|
800fee2: 9b01 ldr r3, [sp, #4]
|
|
800fee4: 429e cmp r6, r3
|
|
800fee6: f67f aee7 bls.w 800fcb8 <_scanf_float+0x84>
|
|
800feea: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
800feee: f816 1d01 ldrb.w r1, [r6, #-1]!
|
|
800fef2: 464a mov r2, r9
|
|
800fef4: 4640 mov r0, r8
|
|
800fef6: 4798 blx r3
|
|
800fef8: 6923 ldr r3, [r4, #16]
|
|
800fefa: 3b01 subs r3, #1
|
|
800fefc: 6123 str r3, [r4, #16]
|
|
800fefe: e7f0 b.n 800fee2 <_scanf_float+0x2ae>
|
|
800ff00: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
800ff04: f81b 1d01 ldrb.w r1, [fp, #-1]!
|
|
800ff08: 464a mov r2, r9
|
|
800ff0a: 4640 mov r0, r8
|
|
800ff0c: 4798 blx r3
|
|
800ff0e: 6923 ldr r3, [r4, #16]
|
|
800ff10: 3b01 subs r3, #1
|
|
800ff12: 6123 str r3, [r4, #16]
|
|
800ff14: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
800ff18: fa5f fa8a uxtb.w sl, sl
|
|
800ff1c: f1ba 0f02 cmp.w sl, #2
|
|
800ff20: d1ee bne.n 800ff00 <_scanf_float+0x2cc>
|
|
800ff22: 3d03 subs r5, #3
|
|
800ff24: b2ed uxtb r5, r5
|
|
800ff26: 1b76 subs r6, r6, r5
|
|
800ff28: 6823 ldr r3, [r4, #0]
|
|
800ff2a: 05da lsls r2, r3, #23
|
|
800ff2c: d530 bpl.n 800ff90 <_scanf_float+0x35c>
|
|
800ff2e: 055b lsls r3, r3, #21
|
|
800ff30: d511 bpl.n 800ff56 <_scanf_float+0x322>
|
|
800ff32: 9b01 ldr r3, [sp, #4]
|
|
800ff34: 429e cmp r6, r3
|
|
800ff36: f67f aebf bls.w 800fcb8 <_scanf_float+0x84>
|
|
800ff3a: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
800ff3e: f816 1d01 ldrb.w r1, [r6, #-1]!
|
|
800ff42: 464a mov r2, r9
|
|
800ff44: 4640 mov r0, r8
|
|
800ff46: 4798 blx r3
|
|
800ff48: 6923 ldr r3, [r4, #16]
|
|
800ff4a: 3b01 subs r3, #1
|
|
800ff4c: 6123 str r3, [r4, #16]
|
|
800ff4e: e7f0 b.n 800ff32 <_scanf_float+0x2fe>
|
|
800ff50: 46aa mov sl, r5
|
|
800ff52: 46b3 mov fp, r6
|
|
800ff54: e7de b.n 800ff14 <_scanf_float+0x2e0>
|
|
800ff56: f816 1c01 ldrb.w r1, [r6, #-1]
|
|
800ff5a: 6923 ldr r3, [r4, #16]
|
|
800ff5c: 2965 cmp r1, #101 @ 0x65
|
|
800ff5e: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff
|
|
800ff62: f106 35ff add.w r5, r6, #4294967295 @ 0xffffffff
|
|
800ff66: 6123 str r3, [r4, #16]
|
|
800ff68: d00c beq.n 800ff84 <_scanf_float+0x350>
|
|
800ff6a: 2945 cmp r1, #69 @ 0x45
|
|
800ff6c: d00a beq.n 800ff84 <_scanf_float+0x350>
|
|
800ff6e: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
800ff72: 464a mov r2, r9
|
|
800ff74: 4640 mov r0, r8
|
|
800ff76: 4798 blx r3
|
|
800ff78: 6923 ldr r3, [r4, #16]
|
|
800ff7a: f816 1c02 ldrb.w r1, [r6, #-2]
|
|
800ff7e: 3b01 subs r3, #1
|
|
800ff80: 1eb5 subs r5, r6, #2
|
|
800ff82: 6123 str r3, [r4, #16]
|
|
800ff84: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
800ff88: 464a mov r2, r9
|
|
800ff8a: 4640 mov r0, r8
|
|
800ff8c: 4798 blx r3
|
|
800ff8e: 462e mov r6, r5
|
|
800ff90: 6822 ldr r2, [r4, #0]
|
|
800ff92: f012 0210 ands.w r2, r2, #16
|
|
800ff96: d001 beq.n 800ff9c <_scanf_float+0x368>
|
|
800ff98: 2000 movs r0, #0
|
|
800ff9a: e68e b.n 800fcba <_scanf_float+0x86>
|
|
800ff9c: 7032 strb r2, [r6, #0]
|
|
800ff9e: 6823 ldr r3, [r4, #0]
|
|
800ffa0: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
800ffa4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800ffa8: d125 bne.n 800fff6 <_scanf_float+0x3c2>
|
|
800ffaa: 9b02 ldr r3, [sp, #8]
|
|
800ffac: 429f cmp r7, r3
|
|
800ffae: d00a beq.n 800ffc6 <_scanf_float+0x392>
|
|
800ffb0: 1bda subs r2, r3, r7
|
|
800ffb2: f204 136f addw r3, r4, #367 @ 0x16f
|
|
800ffb6: 429e cmp r6, r3
|
|
800ffb8: bf28 it cs
|
|
800ffba: f504 76b7 addcs.w r6, r4, #366 @ 0x16e
|
|
800ffbe: 4922 ldr r1, [pc, #136] @ (8010048 <_scanf_float+0x414>)
|
|
800ffc0: 4630 mov r0, r6
|
|
800ffc2: f000 f977 bl 80102b4 <siprintf>
|
|
800ffc6: 9901 ldr r1, [sp, #4]
|
|
800ffc8: 2200 movs r2, #0
|
|
800ffca: 4640 mov r0, r8
|
|
800ffcc: f002 fdd8 bl 8012b80 <_strtod_r>
|
|
800ffd0: 9b03 ldr r3, [sp, #12]
|
|
800ffd2: 6821 ldr r1, [r4, #0]
|
|
800ffd4: 681b ldr r3, [r3, #0]
|
|
800ffd6: f011 0f02 tst.w r1, #2
|
|
800ffda: ec57 6b10 vmov r6, r7, d0
|
|
800ffde: f103 0204 add.w r2, r3, #4
|
|
800ffe2: d015 beq.n 8010010 <_scanf_float+0x3dc>
|
|
800ffe4: 9903 ldr r1, [sp, #12]
|
|
800ffe6: 600a str r2, [r1, #0]
|
|
800ffe8: 681b ldr r3, [r3, #0]
|
|
800ffea: e9c3 6700 strd r6, r7, [r3]
|
|
800ffee: 68e3 ldr r3, [r4, #12]
|
|
800fff0: 3301 adds r3, #1
|
|
800fff2: 60e3 str r3, [r4, #12]
|
|
800fff4: e7d0 b.n 800ff98 <_scanf_float+0x364>
|
|
800fff6: 9b04 ldr r3, [sp, #16]
|
|
800fff8: 2b00 cmp r3, #0
|
|
800fffa: d0e4 beq.n 800ffc6 <_scanf_float+0x392>
|
|
800fffc: 9905 ldr r1, [sp, #20]
|
|
800fffe: 230a movs r3, #10
|
|
8010000: 3101 adds r1, #1
|
|
8010002: 4640 mov r0, r8
|
|
8010004: f002 fe3c bl 8012c80 <_strtol_r>
|
|
8010008: 9b04 ldr r3, [sp, #16]
|
|
801000a: 9e05 ldr r6, [sp, #20]
|
|
801000c: 1ac2 subs r2, r0, r3
|
|
801000e: e7d0 b.n 800ffb2 <_scanf_float+0x37e>
|
|
8010010: f011 0f04 tst.w r1, #4
|
|
8010014: 9903 ldr r1, [sp, #12]
|
|
8010016: 600a str r2, [r1, #0]
|
|
8010018: d1e6 bne.n 800ffe8 <_scanf_float+0x3b4>
|
|
801001a: 681d ldr r5, [r3, #0]
|
|
801001c: 4632 mov r2, r6
|
|
801001e: 463b mov r3, r7
|
|
8010020: 4630 mov r0, r6
|
|
8010022: 4639 mov r1, r7
|
|
8010024: f7f0 fd82 bl 8000b2c <__aeabi_dcmpun>
|
|
8010028: b128 cbz r0, 8010036 <_scanf_float+0x402>
|
|
801002a: 4808 ldr r0, [pc, #32] @ (801004c <_scanf_float+0x418>)
|
|
801002c: f000 fb80 bl 8010730 <nanf>
|
|
8010030: ed85 0a00 vstr s0, [r5]
|
|
8010034: e7db b.n 800ffee <_scanf_float+0x3ba>
|
|
8010036: 4630 mov r0, r6
|
|
8010038: 4639 mov r1, r7
|
|
801003a: f7f0 fdd5 bl 8000be8 <__aeabi_d2f>
|
|
801003e: 6028 str r0, [r5, #0]
|
|
8010040: e7d5 b.n 800ffee <_scanf_float+0x3ba>
|
|
8010042: 2700 movs r7, #0
|
|
8010044: e62e b.n 800fca4 <_scanf_float+0x70>
|
|
8010046: bf00 nop
|
|
8010048: 080147c0 .word 0x080147c0
|
|
801004c: 08014871 .word 0x08014871
|
|
|
|
08010050 <std>:
|
|
8010050: 2300 movs r3, #0
|
|
8010052: b510 push {r4, lr}
|
|
8010054: 4604 mov r4, r0
|
|
8010056: e9c0 3300 strd r3, r3, [r0]
|
|
801005a: e9c0 3304 strd r3, r3, [r0, #16]
|
|
801005e: 6083 str r3, [r0, #8]
|
|
8010060: 8181 strh r1, [r0, #12]
|
|
8010062: 6643 str r3, [r0, #100] @ 0x64
|
|
8010064: 81c2 strh r2, [r0, #14]
|
|
8010066: 6183 str r3, [r0, #24]
|
|
8010068: 4619 mov r1, r3
|
|
801006a: 2208 movs r2, #8
|
|
801006c: 305c adds r0, #92 @ 0x5c
|
|
801006e: f000 fa2b bl 80104c8 <memset>
|
|
8010072: 4b0d ldr r3, [pc, #52] @ (80100a8 <std+0x58>)
|
|
8010074: 6263 str r3, [r4, #36] @ 0x24
|
|
8010076: 4b0d ldr r3, [pc, #52] @ (80100ac <std+0x5c>)
|
|
8010078: 62a3 str r3, [r4, #40] @ 0x28
|
|
801007a: 4b0d ldr r3, [pc, #52] @ (80100b0 <std+0x60>)
|
|
801007c: 62e3 str r3, [r4, #44] @ 0x2c
|
|
801007e: 4b0d ldr r3, [pc, #52] @ (80100b4 <std+0x64>)
|
|
8010080: 6323 str r3, [r4, #48] @ 0x30
|
|
8010082: 4b0d ldr r3, [pc, #52] @ (80100b8 <std+0x68>)
|
|
8010084: 6224 str r4, [r4, #32]
|
|
8010086: 429c cmp r4, r3
|
|
8010088: d006 beq.n 8010098 <std+0x48>
|
|
801008a: f103 0268 add.w r2, r3, #104 @ 0x68
|
|
801008e: 4294 cmp r4, r2
|
|
8010090: d002 beq.n 8010098 <std+0x48>
|
|
8010092: 33d0 adds r3, #208 @ 0xd0
|
|
8010094: 429c cmp r4, r3
|
|
8010096: d105 bne.n 80100a4 <std+0x54>
|
|
8010098: f104 0058 add.w r0, r4, #88 @ 0x58
|
|
801009c: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
80100a0: f000 bb34 b.w 801070c <__retarget_lock_init_recursive>
|
|
80100a4: bd10 pop {r4, pc}
|
|
80100a6: bf00 nop
|
|
80100a8: 080102f9 .word 0x080102f9
|
|
80100ac: 0801031b .word 0x0801031b
|
|
80100b0: 08010353 .word 0x08010353
|
|
80100b4: 08010377 .word 0x08010377
|
|
80100b8: 2000358c .word 0x2000358c
|
|
|
|
080100bc <stdio_exit_handler>:
|
|
80100bc: 4a02 ldr r2, [pc, #8] @ (80100c8 <stdio_exit_handler+0xc>)
|
|
80100be: 4903 ldr r1, [pc, #12] @ (80100cc <stdio_exit_handler+0x10>)
|
|
80100c0: 4803 ldr r0, [pc, #12] @ (80100d0 <stdio_exit_handler+0x14>)
|
|
80100c2: f000 b869 b.w 8010198 <_fwalk_sglue>
|
|
80100c6: bf00 nop
|
|
80100c8: 200000d4 .word 0x200000d4
|
|
80100cc: 080132c1 .word 0x080132c1
|
|
80100d0: 200000e4 .word 0x200000e4
|
|
|
|
080100d4 <cleanup_stdio>:
|
|
80100d4: 6841 ldr r1, [r0, #4]
|
|
80100d6: 4b0c ldr r3, [pc, #48] @ (8010108 <cleanup_stdio+0x34>)
|
|
80100d8: 4299 cmp r1, r3
|
|
80100da: b510 push {r4, lr}
|
|
80100dc: 4604 mov r4, r0
|
|
80100de: d001 beq.n 80100e4 <cleanup_stdio+0x10>
|
|
80100e0: f003 f8ee bl 80132c0 <_fflush_r>
|
|
80100e4: 68a1 ldr r1, [r4, #8]
|
|
80100e6: 4b09 ldr r3, [pc, #36] @ (801010c <cleanup_stdio+0x38>)
|
|
80100e8: 4299 cmp r1, r3
|
|
80100ea: d002 beq.n 80100f2 <cleanup_stdio+0x1e>
|
|
80100ec: 4620 mov r0, r4
|
|
80100ee: f003 f8e7 bl 80132c0 <_fflush_r>
|
|
80100f2: 68e1 ldr r1, [r4, #12]
|
|
80100f4: 4b06 ldr r3, [pc, #24] @ (8010110 <cleanup_stdio+0x3c>)
|
|
80100f6: 4299 cmp r1, r3
|
|
80100f8: d004 beq.n 8010104 <cleanup_stdio+0x30>
|
|
80100fa: 4620 mov r0, r4
|
|
80100fc: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8010100: f003 b8de b.w 80132c0 <_fflush_r>
|
|
8010104: bd10 pop {r4, pc}
|
|
8010106: bf00 nop
|
|
8010108: 2000358c .word 0x2000358c
|
|
801010c: 200035f4 .word 0x200035f4
|
|
8010110: 2000365c .word 0x2000365c
|
|
|
|
08010114 <global_stdio_init.part.0>:
|
|
8010114: b510 push {r4, lr}
|
|
8010116: 4b0b ldr r3, [pc, #44] @ (8010144 <global_stdio_init.part.0+0x30>)
|
|
8010118: 4c0b ldr r4, [pc, #44] @ (8010148 <global_stdio_init.part.0+0x34>)
|
|
801011a: 4a0c ldr r2, [pc, #48] @ (801014c <global_stdio_init.part.0+0x38>)
|
|
801011c: 601a str r2, [r3, #0]
|
|
801011e: 4620 mov r0, r4
|
|
8010120: 2200 movs r2, #0
|
|
8010122: 2104 movs r1, #4
|
|
8010124: f7ff ff94 bl 8010050 <std>
|
|
8010128: f104 0068 add.w r0, r4, #104 @ 0x68
|
|
801012c: 2201 movs r2, #1
|
|
801012e: 2109 movs r1, #9
|
|
8010130: f7ff ff8e bl 8010050 <std>
|
|
8010134: f104 00d0 add.w r0, r4, #208 @ 0xd0
|
|
8010138: 2202 movs r2, #2
|
|
801013a: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
801013e: 2112 movs r1, #18
|
|
8010140: f7ff bf86 b.w 8010050 <std>
|
|
8010144: 200036c4 .word 0x200036c4
|
|
8010148: 2000358c .word 0x2000358c
|
|
801014c: 080100bd .word 0x080100bd
|
|
|
|
08010150 <__sfp_lock_acquire>:
|
|
8010150: 4801 ldr r0, [pc, #4] @ (8010158 <__sfp_lock_acquire+0x8>)
|
|
8010152: f000 badc b.w 801070e <__retarget_lock_acquire_recursive>
|
|
8010156: bf00 nop
|
|
8010158: 200036cd .word 0x200036cd
|
|
|
|
0801015c <__sfp_lock_release>:
|
|
801015c: 4801 ldr r0, [pc, #4] @ (8010164 <__sfp_lock_release+0x8>)
|
|
801015e: f000 bad7 b.w 8010710 <__retarget_lock_release_recursive>
|
|
8010162: bf00 nop
|
|
8010164: 200036cd .word 0x200036cd
|
|
|
|
08010168 <__sinit>:
|
|
8010168: b510 push {r4, lr}
|
|
801016a: 4604 mov r4, r0
|
|
801016c: f7ff fff0 bl 8010150 <__sfp_lock_acquire>
|
|
8010170: 6a23 ldr r3, [r4, #32]
|
|
8010172: b11b cbz r3, 801017c <__sinit+0x14>
|
|
8010174: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8010178: f7ff bff0 b.w 801015c <__sfp_lock_release>
|
|
801017c: 4b04 ldr r3, [pc, #16] @ (8010190 <__sinit+0x28>)
|
|
801017e: 6223 str r3, [r4, #32]
|
|
8010180: 4b04 ldr r3, [pc, #16] @ (8010194 <__sinit+0x2c>)
|
|
8010182: 681b ldr r3, [r3, #0]
|
|
8010184: 2b00 cmp r3, #0
|
|
8010186: d1f5 bne.n 8010174 <__sinit+0xc>
|
|
8010188: f7ff ffc4 bl 8010114 <global_stdio_init.part.0>
|
|
801018c: e7f2 b.n 8010174 <__sinit+0xc>
|
|
801018e: bf00 nop
|
|
8010190: 080100d5 .word 0x080100d5
|
|
8010194: 200036c4 .word 0x200036c4
|
|
|
|
08010198 <_fwalk_sglue>:
|
|
8010198: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
801019c: 4607 mov r7, r0
|
|
801019e: 4688 mov r8, r1
|
|
80101a0: 4614 mov r4, r2
|
|
80101a2: 2600 movs r6, #0
|
|
80101a4: e9d4 9501 ldrd r9, r5, [r4, #4]
|
|
80101a8: f1b9 0901 subs.w r9, r9, #1
|
|
80101ac: d505 bpl.n 80101ba <_fwalk_sglue+0x22>
|
|
80101ae: 6824 ldr r4, [r4, #0]
|
|
80101b0: 2c00 cmp r4, #0
|
|
80101b2: d1f7 bne.n 80101a4 <_fwalk_sglue+0xc>
|
|
80101b4: 4630 mov r0, r6
|
|
80101b6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
80101ba: 89ab ldrh r3, [r5, #12]
|
|
80101bc: 2b01 cmp r3, #1
|
|
80101be: d907 bls.n 80101d0 <_fwalk_sglue+0x38>
|
|
80101c0: f9b5 300e ldrsh.w r3, [r5, #14]
|
|
80101c4: 3301 adds r3, #1
|
|
80101c6: d003 beq.n 80101d0 <_fwalk_sglue+0x38>
|
|
80101c8: 4629 mov r1, r5
|
|
80101ca: 4638 mov r0, r7
|
|
80101cc: 47c0 blx r8
|
|
80101ce: 4306 orrs r6, r0
|
|
80101d0: 3568 adds r5, #104 @ 0x68
|
|
80101d2: e7e9 b.n 80101a8 <_fwalk_sglue+0x10>
|
|
|
|
080101d4 <iprintf>:
|
|
80101d4: b40f push {r0, r1, r2, r3}
|
|
80101d6: b507 push {r0, r1, r2, lr}
|
|
80101d8: 4906 ldr r1, [pc, #24] @ (80101f4 <iprintf+0x20>)
|
|
80101da: ab04 add r3, sp, #16
|
|
80101dc: 6808 ldr r0, [r1, #0]
|
|
80101de: f853 2b04 ldr.w r2, [r3], #4
|
|
80101e2: 6881 ldr r1, [r0, #8]
|
|
80101e4: 9301 str r3, [sp, #4]
|
|
80101e6: f002 fecf bl 8012f88 <_vfiprintf_r>
|
|
80101ea: b003 add sp, #12
|
|
80101ec: f85d eb04 ldr.w lr, [sp], #4
|
|
80101f0: b004 add sp, #16
|
|
80101f2: 4770 bx lr
|
|
80101f4: 200000e0 .word 0x200000e0
|
|
|
|
080101f8 <_puts_r>:
|
|
80101f8: 6a03 ldr r3, [r0, #32]
|
|
80101fa: b570 push {r4, r5, r6, lr}
|
|
80101fc: 6884 ldr r4, [r0, #8]
|
|
80101fe: 4605 mov r5, r0
|
|
8010200: 460e mov r6, r1
|
|
8010202: b90b cbnz r3, 8010208 <_puts_r+0x10>
|
|
8010204: f7ff ffb0 bl 8010168 <__sinit>
|
|
8010208: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
801020a: 07db lsls r3, r3, #31
|
|
801020c: d405 bmi.n 801021a <_puts_r+0x22>
|
|
801020e: 89a3 ldrh r3, [r4, #12]
|
|
8010210: 0598 lsls r0, r3, #22
|
|
8010212: d402 bmi.n 801021a <_puts_r+0x22>
|
|
8010214: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8010216: f000 fa7a bl 801070e <__retarget_lock_acquire_recursive>
|
|
801021a: 89a3 ldrh r3, [r4, #12]
|
|
801021c: 0719 lsls r1, r3, #28
|
|
801021e: d502 bpl.n 8010226 <_puts_r+0x2e>
|
|
8010220: 6923 ldr r3, [r4, #16]
|
|
8010222: 2b00 cmp r3, #0
|
|
8010224: d135 bne.n 8010292 <_puts_r+0x9a>
|
|
8010226: 4621 mov r1, r4
|
|
8010228: 4628 mov r0, r5
|
|
801022a: f000 f8e7 bl 80103fc <__swsetup_r>
|
|
801022e: b380 cbz r0, 8010292 <_puts_r+0x9a>
|
|
8010230: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff
|
|
8010234: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
8010236: 07da lsls r2, r3, #31
|
|
8010238: d405 bmi.n 8010246 <_puts_r+0x4e>
|
|
801023a: 89a3 ldrh r3, [r4, #12]
|
|
801023c: 059b lsls r3, r3, #22
|
|
801023e: d402 bmi.n 8010246 <_puts_r+0x4e>
|
|
8010240: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8010242: f000 fa65 bl 8010710 <__retarget_lock_release_recursive>
|
|
8010246: 4628 mov r0, r5
|
|
8010248: bd70 pop {r4, r5, r6, pc}
|
|
801024a: 2b00 cmp r3, #0
|
|
801024c: da04 bge.n 8010258 <_puts_r+0x60>
|
|
801024e: 69a2 ldr r2, [r4, #24]
|
|
8010250: 429a cmp r2, r3
|
|
8010252: dc17 bgt.n 8010284 <_puts_r+0x8c>
|
|
8010254: 290a cmp r1, #10
|
|
8010256: d015 beq.n 8010284 <_puts_r+0x8c>
|
|
8010258: 6823 ldr r3, [r4, #0]
|
|
801025a: 1c5a adds r2, r3, #1
|
|
801025c: 6022 str r2, [r4, #0]
|
|
801025e: 7019 strb r1, [r3, #0]
|
|
8010260: 68a3 ldr r3, [r4, #8]
|
|
8010262: f816 1f01 ldrb.w r1, [r6, #1]!
|
|
8010266: 3b01 subs r3, #1
|
|
8010268: 60a3 str r3, [r4, #8]
|
|
801026a: 2900 cmp r1, #0
|
|
801026c: d1ed bne.n 801024a <_puts_r+0x52>
|
|
801026e: 2b00 cmp r3, #0
|
|
8010270: da11 bge.n 8010296 <_puts_r+0x9e>
|
|
8010272: 4622 mov r2, r4
|
|
8010274: 210a movs r1, #10
|
|
8010276: 4628 mov r0, r5
|
|
8010278: f000 f881 bl 801037e <__swbuf_r>
|
|
801027c: 3001 adds r0, #1
|
|
801027e: d0d7 beq.n 8010230 <_puts_r+0x38>
|
|
8010280: 250a movs r5, #10
|
|
8010282: e7d7 b.n 8010234 <_puts_r+0x3c>
|
|
8010284: 4622 mov r2, r4
|
|
8010286: 4628 mov r0, r5
|
|
8010288: f000 f879 bl 801037e <__swbuf_r>
|
|
801028c: 3001 adds r0, #1
|
|
801028e: d1e7 bne.n 8010260 <_puts_r+0x68>
|
|
8010290: e7ce b.n 8010230 <_puts_r+0x38>
|
|
8010292: 3e01 subs r6, #1
|
|
8010294: e7e4 b.n 8010260 <_puts_r+0x68>
|
|
8010296: 6823 ldr r3, [r4, #0]
|
|
8010298: 1c5a adds r2, r3, #1
|
|
801029a: 6022 str r2, [r4, #0]
|
|
801029c: 220a movs r2, #10
|
|
801029e: 701a strb r2, [r3, #0]
|
|
80102a0: e7ee b.n 8010280 <_puts_r+0x88>
|
|
...
|
|
|
|
080102a4 <puts>:
|
|
80102a4: 4b02 ldr r3, [pc, #8] @ (80102b0 <puts+0xc>)
|
|
80102a6: 4601 mov r1, r0
|
|
80102a8: 6818 ldr r0, [r3, #0]
|
|
80102aa: f7ff bfa5 b.w 80101f8 <_puts_r>
|
|
80102ae: bf00 nop
|
|
80102b0: 200000e0 .word 0x200000e0
|
|
|
|
080102b4 <siprintf>:
|
|
80102b4: b40e push {r1, r2, r3}
|
|
80102b6: b510 push {r4, lr}
|
|
80102b8: b09d sub sp, #116 @ 0x74
|
|
80102ba: ab1f add r3, sp, #124 @ 0x7c
|
|
80102bc: 9002 str r0, [sp, #8]
|
|
80102be: 9006 str r0, [sp, #24]
|
|
80102c0: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
|
|
80102c4: 480a ldr r0, [pc, #40] @ (80102f0 <siprintf+0x3c>)
|
|
80102c6: 9107 str r1, [sp, #28]
|
|
80102c8: 9104 str r1, [sp, #16]
|
|
80102ca: 490a ldr r1, [pc, #40] @ (80102f4 <siprintf+0x40>)
|
|
80102cc: f853 2b04 ldr.w r2, [r3], #4
|
|
80102d0: 9105 str r1, [sp, #20]
|
|
80102d2: 2400 movs r4, #0
|
|
80102d4: a902 add r1, sp, #8
|
|
80102d6: 6800 ldr r0, [r0, #0]
|
|
80102d8: 9301 str r3, [sp, #4]
|
|
80102da: 941b str r4, [sp, #108] @ 0x6c
|
|
80102dc: f002 fd2e bl 8012d3c <_svfiprintf_r>
|
|
80102e0: 9b02 ldr r3, [sp, #8]
|
|
80102e2: 701c strb r4, [r3, #0]
|
|
80102e4: b01d add sp, #116 @ 0x74
|
|
80102e6: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
80102ea: b003 add sp, #12
|
|
80102ec: 4770 bx lr
|
|
80102ee: bf00 nop
|
|
80102f0: 200000e0 .word 0x200000e0
|
|
80102f4: ffff0208 .word 0xffff0208
|
|
|
|
080102f8 <__sread>:
|
|
80102f8: b510 push {r4, lr}
|
|
80102fa: 460c mov r4, r1
|
|
80102fc: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
8010300: f000 f9b6 bl 8010670 <_read_r>
|
|
8010304: 2800 cmp r0, #0
|
|
8010306: bfab itete ge
|
|
8010308: 6d63 ldrge r3, [r4, #84] @ 0x54
|
|
801030a: 89a3 ldrhlt r3, [r4, #12]
|
|
801030c: 181b addge r3, r3, r0
|
|
801030e: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
|
|
8010312: bfac ite ge
|
|
8010314: 6563 strge r3, [r4, #84] @ 0x54
|
|
8010316: 81a3 strhlt r3, [r4, #12]
|
|
8010318: bd10 pop {r4, pc}
|
|
|
|
0801031a <__swrite>:
|
|
801031a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
801031e: 461f mov r7, r3
|
|
8010320: 898b ldrh r3, [r1, #12]
|
|
8010322: 05db lsls r3, r3, #23
|
|
8010324: 4605 mov r5, r0
|
|
8010326: 460c mov r4, r1
|
|
8010328: 4616 mov r6, r2
|
|
801032a: d505 bpl.n 8010338 <__swrite+0x1e>
|
|
801032c: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
8010330: 2302 movs r3, #2
|
|
8010332: 2200 movs r2, #0
|
|
8010334: f000 f98a bl 801064c <_lseek_r>
|
|
8010338: 89a3 ldrh r3, [r4, #12]
|
|
801033a: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
801033e: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
8010342: 81a3 strh r3, [r4, #12]
|
|
8010344: 4632 mov r2, r6
|
|
8010346: 463b mov r3, r7
|
|
8010348: 4628 mov r0, r5
|
|
801034a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
801034e: f000 b9a1 b.w 8010694 <_write_r>
|
|
|
|
08010352 <__sseek>:
|
|
8010352: b510 push {r4, lr}
|
|
8010354: 460c mov r4, r1
|
|
8010356: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801035a: f000 f977 bl 801064c <_lseek_r>
|
|
801035e: 1c43 adds r3, r0, #1
|
|
8010360: 89a3 ldrh r3, [r4, #12]
|
|
8010362: bf15 itete ne
|
|
8010364: 6560 strne r0, [r4, #84] @ 0x54
|
|
8010366: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
|
|
801036a: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
|
|
801036e: 81a3 strheq r3, [r4, #12]
|
|
8010370: bf18 it ne
|
|
8010372: 81a3 strhne r3, [r4, #12]
|
|
8010374: bd10 pop {r4, pc}
|
|
|
|
08010376 <__sclose>:
|
|
8010376: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801037a: f000 b957 b.w 801062c <_close_r>
|
|
|
|
0801037e <__swbuf_r>:
|
|
801037e: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8010380: 460e mov r6, r1
|
|
8010382: 4614 mov r4, r2
|
|
8010384: 4605 mov r5, r0
|
|
8010386: b118 cbz r0, 8010390 <__swbuf_r+0x12>
|
|
8010388: 6a03 ldr r3, [r0, #32]
|
|
801038a: b90b cbnz r3, 8010390 <__swbuf_r+0x12>
|
|
801038c: f7ff feec bl 8010168 <__sinit>
|
|
8010390: 69a3 ldr r3, [r4, #24]
|
|
8010392: 60a3 str r3, [r4, #8]
|
|
8010394: 89a3 ldrh r3, [r4, #12]
|
|
8010396: 071a lsls r2, r3, #28
|
|
8010398: d501 bpl.n 801039e <__swbuf_r+0x20>
|
|
801039a: 6923 ldr r3, [r4, #16]
|
|
801039c: b943 cbnz r3, 80103b0 <__swbuf_r+0x32>
|
|
801039e: 4621 mov r1, r4
|
|
80103a0: 4628 mov r0, r5
|
|
80103a2: f000 f82b bl 80103fc <__swsetup_r>
|
|
80103a6: b118 cbz r0, 80103b0 <__swbuf_r+0x32>
|
|
80103a8: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
|
|
80103ac: 4638 mov r0, r7
|
|
80103ae: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
80103b0: 6823 ldr r3, [r4, #0]
|
|
80103b2: 6922 ldr r2, [r4, #16]
|
|
80103b4: 1a98 subs r0, r3, r2
|
|
80103b6: 6963 ldr r3, [r4, #20]
|
|
80103b8: b2f6 uxtb r6, r6
|
|
80103ba: 4283 cmp r3, r0
|
|
80103bc: 4637 mov r7, r6
|
|
80103be: dc05 bgt.n 80103cc <__swbuf_r+0x4e>
|
|
80103c0: 4621 mov r1, r4
|
|
80103c2: 4628 mov r0, r5
|
|
80103c4: f002 ff7c bl 80132c0 <_fflush_r>
|
|
80103c8: 2800 cmp r0, #0
|
|
80103ca: d1ed bne.n 80103a8 <__swbuf_r+0x2a>
|
|
80103cc: 68a3 ldr r3, [r4, #8]
|
|
80103ce: 3b01 subs r3, #1
|
|
80103d0: 60a3 str r3, [r4, #8]
|
|
80103d2: 6823 ldr r3, [r4, #0]
|
|
80103d4: 1c5a adds r2, r3, #1
|
|
80103d6: 6022 str r2, [r4, #0]
|
|
80103d8: 701e strb r6, [r3, #0]
|
|
80103da: 6962 ldr r2, [r4, #20]
|
|
80103dc: 1c43 adds r3, r0, #1
|
|
80103de: 429a cmp r2, r3
|
|
80103e0: d004 beq.n 80103ec <__swbuf_r+0x6e>
|
|
80103e2: 89a3 ldrh r3, [r4, #12]
|
|
80103e4: 07db lsls r3, r3, #31
|
|
80103e6: d5e1 bpl.n 80103ac <__swbuf_r+0x2e>
|
|
80103e8: 2e0a cmp r6, #10
|
|
80103ea: d1df bne.n 80103ac <__swbuf_r+0x2e>
|
|
80103ec: 4621 mov r1, r4
|
|
80103ee: 4628 mov r0, r5
|
|
80103f0: f002 ff66 bl 80132c0 <_fflush_r>
|
|
80103f4: 2800 cmp r0, #0
|
|
80103f6: d0d9 beq.n 80103ac <__swbuf_r+0x2e>
|
|
80103f8: e7d6 b.n 80103a8 <__swbuf_r+0x2a>
|
|
...
|
|
|
|
080103fc <__swsetup_r>:
|
|
80103fc: b538 push {r3, r4, r5, lr}
|
|
80103fe: 4b29 ldr r3, [pc, #164] @ (80104a4 <__swsetup_r+0xa8>)
|
|
8010400: 4605 mov r5, r0
|
|
8010402: 6818 ldr r0, [r3, #0]
|
|
8010404: 460c mov r4, r1
|
|
8010406: b118 cbz r0, 8010410 <__swsetup_r+0x14>
|
|
8010408: 6a03 ldr r3, [r0, #32]
|
|
801040a: b90b cbnz r3, 8010410 <__swsetup_r+0x14>
|
|
801040c: f7ff feac bl 8010168 <__sinit>
|
|
8010410: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8010414: 0719 lsls r1, r3, #28
|
|
8010416: d422 bmi.n 801045e <__swsetup_r+0x62>
|
|
8010418: 06da lsls r2, r3, #27
|
|
801041a: d407 bmi.n 801042c <__swsetup_r+0x30>
|
|
801041c: 2209 movs r2, #9
|
|
801041e: 602a str r2, [r5, #0]
|
|
8010420: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8010424: 81a3 strh r3, [r4, #12]
|
|
8010426: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801042a: e033 b.n 8010494 <__swsetup_r+0x98>
|
|
801042c: 0758 lsls r0, r3, #29
|
|
801042e: d512 bpl.n 8010456 <__swsetup_r+0x5a>
|
|
8010430: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
8010432: b141 cbz r1, 8010446 <__swsetup_r+0x4a>
|
|
8010434: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
8010438: 4299 cmp r1, r3
|
|
801043a: d002 beq.n 8010442 <__swsetup_r+0x46>
|
|
801043c: 4628 mov r0, r5
|
|
801043e: f000 fff3 bl 8011428 <_free_r>
|
|
8010442: 2300 movs r3, #0
|
|
8010444: 6363 str r3, [r4, #52] @ 0x34
|
|
8010446: 89a3 ldrh r3, [r4, #12]
|
|
8010448: f023 0324 bic.w r3, r3, #36 @ 0x24
|
|
801044c: 81a3 strh r3, [r4, #12]
|
|
801044e: 2300 movs r3, #0
|
|
8010450: 6063 str r3, [r4, #4]
|
|
8010452: 6923 ldr r3, [r4, #16]
|
|
8010454: 6023 str r3, [r4, #0]
|
|
8010456: 89a3 ldrh r3, [r4, #12]
|
|
8010458: f043 0308 orr.w r3, r3, #8
|
|
801045c: 81a3 strh r3, [r4, #12]
|
|
801045e: 6923 ldr r3, [r4, #16]
|
|
8010460: b94b cbnz r3, 8010476 <__swsetup_r+0x7a>
|
|
8010462: 89a3 ldrh r3, [r4, #12]
|
|
8010464: f403 7320 and.w r3, r3, #640 @ 0x280
|
|
8010468: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
801046c: d003 beq.n 8010476 <__swsetup_r+0x7a>
|
|
801046e: 4621 mov r1, r4
|
|
8010470: 4628 mov r0, r5
|
|
8010472: f002 ff85 bl 8013380 <__smakebuf_r>
|
|
8010476: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801047a: f013 0201 ands.w r2, r3, #1
|
|
801047e: d00a beq.n 8010496 <__swsetup_r+0x9a>
|
|
8010480: 2200 movs r2, #0
|
|
8010482: 60a2 str r2, [r4, #8]
|
|
8010484: 6962 ldr r2, [r4, #20]
|
|
8010486: 4252 negs r2, r2
|
|
8010488: 61a2 str r2, [r4, #24]
|
|
801048a: 6922 ldr r2, [r4, #16]
|
|
801048c: b942 cbnz r2, 80104a0 <__swsetup_r+0xa4>
|
|
801048e: f013 0080 ands.w r0, r3, #128 @ 0x80
|
|
8010492: d1c5 bne.n 8010420 <__swsetup_r+0x24>
|
|
8010494: bd38 pop {r3, r4, r5, pc}
|
|
8010496: 0799 lsls r1, r3, #30
|
|
8010498: bf58 it pl
|
|
801049a: 6962 ldrpl r2, [r4, #20]
|
|
801049c: 60a2 str r2, [r4, #8]
|
|
801049e: e7f4 b.n 801048a <__swsetup_r+0x8e>
|
|
80104a0: 2000 movs r0, #0
|
|
80104a2: e7f7 b.n 8010494 <__swsetup_r+0x98>
|
|
80104a4: 200000e0 .word 0x200000e0
|
|
|
|
080104a8 <memcmp>:
|
|
80104a8: b510 push {r4, lr}
|
|
80104aa: 3901 subs r1, #1
|
|
80104ac: 4402 add r2, r0
|
|
80104ae: 4290 cmp r0, r2
|
|
80104b0: d101 bne.n 80104b6 <memcmp+0xe>
|
|
80104b2: 2000 movs r0, #0
|
|
80104b4: e005 b.n 80104c2 <memcmp+0x1a>
|
|
80104b6: 7803 ldrb r3, [r0, #0]
|
|
80104b8: f811 4f01 ldrb.w r4, [r1, #1]!
|
|
80104bc: 42a3 cmp r3, r4
|
|
80104be: d001 beq.n 80104c4 <memcmp+0x1c>
|
|
80104c0: 1b18 subs r0, r3, r4
|
|
80104c2: bd10 pop {r4, pc}
|
|
80104c4: 3001 adds r0, #1
|
|
80104c6: e7f2 b.n 80104ae <memcmp+0x6>
|
|
|
|
080104c8 <memset>:
|
|
80104c8: 4402 add r2, r0
|
|
80104ca: 4603 mov r3, r0
|
|
80104cc: 4293 cmp r3, r2
|
|
80104ce: d100 bne.n 80104d2 <memset+0xa>
|
|
80104d0: 4770 bx lr
|
|
80104d2: f803 1b01 strb.w r1, [r3], #1
|
|
80104d6: e7f9 b.n 80104cc <memset+0x4>
|
|
|
|
080104d8 <strcat>:
|
|
80104d8: b510 push {r4, lr}
|
|
80104da: 4602 mov r2, r0
|
|
80104dc: 7814 ldrb r4, [r2, #0]
|
|
80104de: 4613 mov r3, r2
|
|
80104e0: 3201 adds r2, #1
|
|
80104e2: 2c00 cmp r4, #0
|
|
80104e4: d1fa bne.n 80104dc <strcat+0x4>
|
|
80104e6: 3b01 subs r3, #1
|
|
80104e8: f811 2b01 ldrb.w r2, [r1], #1
|
|
80104ec: f803 2f01 strb.w r2, [r3, #1]!
|
|
80104f0: 2a00 cmp r2, #0
|
|
80104f2: d1f9 bne.n 80104e8 <strcat+0x10>
|
|
80104f4: bd10 pop {r4, pc}
|
|
|
|
080104f6 <strncmp>:
|
|
80104f6: b510 push {r4, lr}
|
|
80104f8: b16a cbz r2, 8010516 <strncmp+0x20>
|
|
80104fa: 3901 subs r1, #1
|
|
80104fc: 1884 adds r4, r0, r2
|
|
80104fe: f810 2b01 ldrb.w r2, [r0], #1
|
|
8010502: f811 3f01 ldrb.w r3, [r1, #1]!
|
|
8010506: 429a cmp r2, r3
|
|
8010508: d103 bne.n 8010512 <strncmp+0x1c>
|
|
801050a: 42a0 cmp r0, r4
|
|
801050c: d001 beq.n 8010512 <strncmp+0x1c>
|
|
801050e: 2a00 cmp r2, #0
|
|
8010510: d1f5 bne.n 80104fe <strncmp+0x8>
|
|
8010512: 1ad0 subs r0, r2, r3
|
|
8010514: bd10 pop {r4, pc}
|
|
8010516: 4610 mov r0, r2
|
|
8010518: e7fc b.n 8010514 <strncmp+0x1e>
|
|
|
|
0801051a <strncpy>:
|
|
801051a: b510 push {r4, lr}
|
|
801051c: 3901 subs r1, #1
|
|
801051e: 4603 mov r3, r0
|
|
8010520: b132 cbz r2, 8010530 <strncpy+0x16>
|
|
8010522: f811 4f01 ldrb.w r4, [r1, #1]!
|
|
8010526: f803 4b01 strb.w r4, [r3], #1
|
|
801052a: 3a01 subs r2, #1
|
|
801052c: 2c00 cmp r4, #0
|
|
801052e: d1f7 bne.n 8010520 <strncpy+0x6>
|
|
8010530: 441a add r2, r3
|
|
8010532: 2100 movs r1, #0
|
|
8010534: 4293 cmp r3, r2
|
|
8010536: d100 bne.n 801053a <strncpy+0x20>
|
|
8010538: bd10 pop {r4, pc}
|
|
801053a: f803 1b01 strb.w r1, [r3], #1
|
|
801053e: e7f9 b.n 8010534 <strncpy+0x1a>
|
|
|
|
08010540 <strtok>:
|
|
8010540: 4b16 ldr r3, [pc, #88] @ (801059c <strtok+0x5c>)
|
|
8010542: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8010546: 681f ldr r7, [r3, #0]
|
|
8010548: 6c7c ldr r4, [r7, #68] @ 0x44
|
|
801054a: 4605 mov r5, r0
|
|
801054c: 460e mov r6, r1
|
|
801054e: b9ec cbnz r4, 801058c <strtok+0x4c>
|
|
8010550: 2050 movs r0, #80 @ 0x50
|
|
8010552: f000 ffb3 bl 80114bc <malloc>
|
|
8010556: 4602 mov r2, r0
|
|
8010558: 6478 str r0, [r7, #68] @ 0x44
|
|
801055a: b920 cbnz r0, 8010566 <strtok+0x26>
|
|
801055c: 4b10 ldr r3, [pc, #64] @ (80105a0 <strtok+0x60>)
|
|
801055e: 4811 ldr r0, [pc, #68] @ (80105a4 <strtok+0x64>)
|
|
8010560: 215b movs r1, #91 @ 0x5b
|
|
8010562: f000 f8eb bl 801073c <__assert_func>
|
|
8010566: e9c0 4400 strd r4, r4, [r0]
|
|
801056a: e9c0 4402 strd r4, r4, [r0, #8]
|
|
801056e: e9c0 4404 strd r4, r4, [r0, #16]
|
|
8010572: e9c0 440a strd r4, r4, [r0, #40] @ 0x28
|
|
8010576: e9c0 440c strd r4, r4, [r0, #48] @ 0x30
|
|
801057a: e9c0 440e strd r4, r4, [r0, #56] @ 0x38
|
|
801057e: e9c0 4410 strd r4, r4, [r0, #64] @ 0x40
|
|
8010582: e9c0 4412 strd r4, r4, [r0, #72] @ 0x48
|
|
8010586: 6184 str r4, [r0, #24]
|
|
8010588: 7704 strb r4, [r0, #28]
|
|
801058a: 6244 str r4, [r0, #36] @ 0x24
|
|
801058c: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
801058e: 4631 mov r1, r6
|
|
8010590: 4628 mov r0, r5
|
|
8010592: 2301 movs r3, #1
|
|
8010594: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
8010598: f000 b806 b.w 80105a8 <__strtok_r>
|
|
801059c: 200000e0 .word 0x200000e0
|
|
80105a0: 080147c5 .word 0x080147c5
|
|
80105a4: 080147dc .word 0x080147dc
|
|
|
|
080105a8 <__strtok_r>:
|
|
80105a8: b5f0 push {r4, r5, r6, r7, lr}
|
|
80105aa: 4604 mov r4, r0
|
|
80105ac: b908 cbnz r0, 80105b2 <__strtok_r+0xa>
|
|
80105ae: 6814 ldr r4, [r2, #0]
|
|
80105b0: b144 cbz r4, 80105c4 <__strtok_r+0x1c>
|
|
80105b2: 4620 mov r0, r4
|
|
80105b4: f814 5b01 ldrb.w r5, [r4], #1
|
|
80105b8: 460f mov r7, r1
|
|
80105ba: f817 6b01 ldrb.w r6, [r7], #1
|
|
80105be: b91e cbnz r6, 80105c8 <__strtok_r+0x20>
|
|
80105c0: b965 cbnz r5, 80105dc <__strtok_r+0x34>
|
|
80105c2: 6015 str r5, [r2, #0]
|
|
80105c4: 2000 movs r0, #0
|
|
80105c6: e005 b.n 80105d4 <__strtok_r+0x2c>
|
|
80105c8: 42b5 cmp r5, r6
|
|
80105ca: d1f6 bne.n 80105ba <__strtok_r+0x12>
|
|
80105cc: 2b00 cmp r3, #0
|
|
80105ce: d1f0 bne.n 80105b2 <__strtok_r+0xa>
|
|
80105d0: 6014 str r4, [r2, #0]
|
|
80105d2: 7003 strb r3, [r0, #0]
|
|
80105d4: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80105d6: 461c mov r4, r3
|
|
80105d8: e00c b.n 80105f4 <__strtok_r+0x4c>
|
|
80105da: b91d cbnz r5, 80105e4 <__strtok_r+0x3c>
|
|
80105dc: 4627 mov r7, r4
|
|
80105de: f814 3b01 ldrb.w r3, [r4], #1
|
|
80105e2: 460e mov r6, r1
|
|
80105e4: f816 5b01 ldrb.w r5, [r6], #1
|
|
80105e8: 42ab cmp r3, r5
|
|
80105ea: d1f6 bne.n 80105da <__strtok_r+0x32>
|
|
80105ec: 2b00 cmp r3, #0
|
|
80105ee: d0f2 beq.n 80105d6 <__strtok_r+0x2e>
|
|
80105f0: 2300 movs r3, #0
|
|
80105f2: 703b strb r3, [r7, #0]
|
|
80105f4: 6014 str r4, [r2, #0]
|
|
80105f6: e7ed b.n 80105d4 <__strtok_r+0x2c>
|
|
|
|
080105f8 <strstr>:
|
|
80105f8: 780a ldrb r2, [r1, #0]
|
|
80105fa: b570 push {r4, r5, r6, lr}
|
|
80105fc: b96a cbnz r2, 801061a <strstr+0x22>
|
|
80105fe: bd70 pop {r4, r5, r6, pc}
|
|
8010600: 429a cmp r2, r3
|
|
8010602: d109 bne.n 8010618 <strstr+0x20>
|
|
8010604: 460c mov r4, r1
|
|
8010606: 4605 mov r5, r0
|
|
8010608: f814 3f01 ldrb.w r3, [r4, #1]!
|
|
801060c: 2b00 cmp r3, #0
|
|
801060e: d0f6 beq.n 80105fe <strstr+0x6>
|
|
8010610: f815 6f01 ldrb.w r6, [r5, #1]!
|
|
8010614: 429e cmp r6, r3
|
|
8010616: d0f7 beq.n 8010608 <strstr+0x10>
|
|
8010618: 3001 adds r0, #1
|
|
801061a: 7803 ldrb r3, [r0, #0]
|
|
801061c: 2b00 cmp r3, #0
|
|
801061e: d1ef bne.n 8010600 <strstr+0x8>
|
|
8010620: 4618 mov r0, r3
|
|
8010622: e7ec b.n 80105fe <strstr+0x6>
|
|
|
|
08010624 <_localeconv_r>:
|
|
8010624: 4800 ldr r0, [pc, #0] @ (8010628 <_localeconv_r+0x4>)
|
|
8010626: 4770 bx lr
|
|
8010628: 20000220 .word 0x20000220
|
|
|
|
0801062c <_close_r>:
|
|
801062c: b538 push {r3, r4, r5, lr}
|
|
801062e: 4d06 ldr r5, [pc, #24] @ (8010648 <_close_r+0x1c>)
|
|
8010630: 2300 movs r3, #0
|
|
8010632: 4604 mov r4, r0
|
|
8010634: 4608 mov r0, r1
|
|
8010636: 602b str r3, [r5, #0]
|
|
8010638: f7f3 fa90 bl 8003b5c <_close>
|
|
801063c: 1c43 adds r3, r0, #1
|
|
801063e: d102 bne.n 8010646 <_close_r+0x1a>
|
|
8010640: 682b ldr r3, [r5, #0]
|
|
8010642: b103 cbz r3, 8010646 <_close_r+0x1a>
|
|
8010644: 6023 str r3, [r4, #0]
|
|
8010646: bd38 pop {r3, r4, r5, pc}
|
|
8010648: 200036c8 .word 0x200036c8
|
|
|
|
0801064c <_lseek_r>:
|
|
801064c: b538 push {r3, r4, r5, lr}
|
|
801064e: 4d07 ldr r5, [pc, #28] @ (801066c <_lseek_r+0x20>)
|
|
8010650: 4604 mov r4, r0
|
|
8010652: 4608 mov r0, r1
|
|
8010654: 4611 mov r1, r2
|
|
8010656: 2200 movs r2, #0
|
|
8010658: 602a str r2, [r5, #0]
|
|
801065a: 461a mov r2, r3
|
|
801065c: f7f3 faa5 bl 8003baa <_lseek>
|
|
8010660: 1c43 adds r3, r0, #1
|
|
8010662: d102 bne.n 801066a <_lseek_r+0x1e>
|
|
8010664: 682b ldr r3, [r5, #0]
|
|
8010666: b103 cbz r3, 801066a <_lseek_r+0x1e>
|
|
8010668: 6023 str r3, [r4, #0]
|
|
801066a: bd38 pop {r3, r4, r5, pc}
|
|
801066c: 200036c8 .word 0x200036c8
|
|
|
|
08010670 <_read_r>:
|
|
8010670: b538 push {r3, r4, r5, lr}
|
|
8010672: 4d07 ldr r5, [pc, #28] @ (8010690 <_read_r+0x20>)
|
|
8010674: 4604 mov r4, r0
|
|
8010676: 4608 mov r0, r1
|
|
8010678: 4611 mov r1, r2
|
|
801067a: 2200 movs r2, #0
|
|
801067c: 602a str r2, [r5, #0]
|
|
801067e: 461a mov r2, r3
|
|
8010680: f7f3 fa33 bl 8003aea <_read>
|
|
8010684: 1c43 adds r3, r0, #1
|
|
8010686: d102 bne.n 801068e <_read_r+0x1e>
|
|
8010688: 682b ldr r3, [r5, #0]
|
|
801068a: b103 cbz r3, 801068e <_read_r+0x1e>
|
|
801068c: 6023 str r3, [r4, #0]
|
|
801068e: bd38 pop {r3, r4, r5, pc}
|
|
8010690: 200036c8 .word 0x200036c8
|
|
|
|
08010694 <_write_r>:
|
|
8010694: b538 push {r3, r4, r5, lr}
|
|
8010696: 4d07 ldr r5, [pc, #28] @ (80106b4 <_write_r+0x20>)
|
|
8010698: 4604 mov r4, r0
|
|
801069a: 4608 mov r0, r1
|
|
801069c: 4611 mov r1, r2
|
|
801069e: 2200 movs r2, #0
|
|
80106a0: 602a str r2, [r5, #0]
|
|
80106a2: 461a mov r2, r3
|
|
80106a4: f7f3 fa3e bl 8003b24 <_write>
|
|
80106a8: 1c43 adds r3, r0, #1
|
|
80106aa: d102 bne.n 80106b2 <_write_r+0x1e>
|
|
80106ac: 682b ldr r3, [r5, #0]
|
|
80106ae: b103 cbz r3, 80106b2 <_write_r+0x1e>
|
|
80106b0: 6023 str r3, [r4, #0]
|
|
80106b2: bd38 pop {r3, r4, r5, pc}
|
|
80106b4: 200036c8 .word 0x200036c8
|
|
|
|
080106b8 <__errno>:
|
|
80106b8: 4b01 ldr r3, [pc, #4] @ (80106c0 <__errno+0x8>)
|
|
80106ba: 6818 ldr r0, [r3, #0]
|
|
80106bc: 4770 bx lr
|
|
80106be: bf00 nop
|
|
80106c0: 200000e0 .word 0x200000e0
|
|
|
|
080106c4 <__libc_init_array>:
|
|
80106c4: b570 push {r4, r5, r6, lr}
|
|
80106c6: 4d0d ldr r5, [pc, #52] @ (80106fc <__libc_init_array+0x38>)
|
|
80106c8: 4c0d ldr r4, [pc, #52] @ (8010700 <__libc_init_array+0x3c>)
|
|
80106ca: 1b64 subs r4, r4, r5
|
|
80106cc: 10a4 asrs r4, r4, #2
|
|
80106ce: 2600 movs r6, #0
|
|
80106d0: 42a6 cmp r6, r4
|
|
80106d2: d109 bne.n 80106e8 <__libc_init_array+0x24>
|
|
80106d4: 4d0b ldr r5, [pc, #44] @ (8010704 <__libc_init_array+0x40>)
|
|
80106d6: 4c0c ldr r4, [pc, #48] @ (8010708 <__libc_init_array+0x44>)
|
|
80106d8: f003 face bl 8013c78 <_init>
|
|
80106dc: 1b64 subs r4, r4, r5
|
|
80106de: 10a4 asrs r4, r4, #2
|
|
80106e0: 2600 movs r6, #0
|
|
80106e2: 42a6 cmp r6, r4
|
|
80106e4: d105 bne.n 80106f2 <__libc_init_array+0x2e>
|
|
80106e6: bd70 pop {r4, r5, r6, pc}
|
|
80106e8: f855 3b04 ldr.w r3, [r5], #4
|
|
80106ec: 4798 blx r3
|
|
80106ee: 3601 adds r6, #1
|
|
80106f0: e7ee b.n 80106d0 <__libc_init_array+0xc>
|
|
80106f2: f855 3b04 ldr.w r3, [r5], #4
|
|
80106f6: 4798 blx r3
|
|
80106f8: 3601 adds r6, #1
|
|
80106fa: e7f2 b.n 80106e2 <__libc_init_array+0x1e>
|
|
80106fc: 08014c14 .word 0x08014c14
|
|
8010700: 08014c14 .word 0x08014c14
|
|
8010704: 08014c14 .word 0x08014c14
|
|
8010708: 08014c18 .word 0x08014c18
|
|
|
|
0801070c <__retarget_lock_init_recursive>:
|
|
801070c: 4770 bx lr
|
|
|
|
0801070e <__retarget_lock_acquire_recursive>:
|
|
801070e: 4770 bx lr
|
|
|
|
08010710 <__retarget_lock_release_recursive>:
|
|
8010710: 4770 bx lr
|
|
|
|
08010712 <memcpy>:
|
|
8010712: 440a add r2, r1
|
|
8010714: 4291 cmp r1, r2
|
|
8010716: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
801071a: d100 bne.n 801071e <memcpy+0xc>
|
|
801071c: 4770 bx lr
|
|
801071e: b510 push {r4, lr}
|
|
8010720: f811 4b01 ldrb.w r4, [r1], #1
|
|
8010724: f803 4f01 strb.w r4, [r3, #1]!
|
|
8010728: 4291 cmp r1, r2
|
|
801072a: d1f9 bne.n 8010720 <memcpy+0xe>
|
|
801072c: bd10 pop {r4, pc}
|
|
...
|
|
|
|
08010730 <nanf>:
|
|
8010730: ed9f 0a01 vldr s0, [pc, #4] @ 8010738 <nanf+0x8>
|
|
8010734: 4770 bx lr
|
|
8010736: bf00 nop
|
|
8010738: 7fc00000 .word 0x7fc00000
|
|
|
|
0801073c <__assert_func>:
|
|
801073c: b51f push {r0, r1, r2, r3, r4, lr}
|
|
801073e: 4614 mov r4, r2
|
|
8010740: 461a mov r2, r3
|
|
8010742: 4b09 ldr r3, [pc, #36] @ (8010768 <__assert_func+0x2c>)
|
|
8010744: 681b ldr r3, [r3, #0]
|
|
8010746: 4605 mov r5, r0
|
|
8010748: 68d8 ldr r0, [r3, #12]
|
|
801074a: b14c cbz r4, 8010760 <__assert_func+0x24>
|
|
801074c: 4b07 ldr r3, [pc, #28] @ (801076c <__assert_func+0x30>)
|
|
801074e: 9100 str r1, [sp, #0]
|
|
8010750: e9cd 3401 strd r3, r4, [sp, #4]
|
|
8010754: 4906 ldr r1, [pc, #24] @ (8010770 <__assert_func+0x34>)
|
|
8010756: 462b mov r3, r5
|
|
8010758: f002 fdda bl 8013310 <fiprintf>
|
|
801075c: f002 fea0 bl 80134a0 <abort>
|
|
8010760: 4b04 ldr r3, [pc, #16] @ (8010774 <__assert_func+0x38>)
|
|
8010762: 461c mov r4, r3
|
|
8010764: e7f3 b.n 801074e <__assert_func+0x12>
|
|
8010766: bf00 nop
|
|
8010768: 200000e0 .word 0x200000e0
|
|
801076c: 08014836 .word 0x08014836
|
|
8010770: 08014843 .word 0x08014843
|
|
8010774: 08014871 .word 0x08014871
|
|
|
|
08010778 <quorem>:
|
|
8010778: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801077c: 6903 ldr r3, [r0, #16]
|
|
801077e: 690c ldr r4, [r1, #16]
|
|
8010780: 42a3 cmp r3, r4
|
|
8010782: 4607 mov r7, r0
|
|
8010784: db7e blt.n 8010884 <quorem+0x10c>
|
|
8010786: 3c01 subs r4, #1
|
|
8010788: f101 0814 add.w r8, r1, #20
|
|
801078c: 00a3 lsls r3, r4, #2
|
|
801078e: f100 0514 add.w r5, r0, #20
|
|
8010792: 9300 str r3, [sp, #0]
|
|
8010794: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
8010798: 9301 str r3, [sp, #4]
|
|
801079a: f858 3024 ldr.w r3, [r8, r4, lsl #2]
|
|
801079e: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
80107a2: 3301 adds r3, #1
|
|
80107a4: 429a cmp r2, r3
|
|
80107a6: eb08 0984 add.w r9, r8, r4, lsl #2
|
|
80107aa: fbb2 f6f3 udiv r6, r2, r3
|
|
80107ae: d32e bcc.n 801080e <quorem+0x96>
|
|
80107b0: f04f 0a00 mov.w sl, #0
|
|
80107b4: 46c4 mov ip, r8
|
|
80107b6: 46ae mov lr, r5
|
|
80107b8: 46d3 mov fp, sl
|
|
80107ba: f85c 3b04 ldr.w r3, [ip], #4
|
|
80107be: b298 uxth r0, r3
|
|
80107c0: fb06 a000 mla r0, r6, r0, sl
|
|
80107c4: 0c02 lsrs r2, r0, #16
|
|
80107c6: 0c1b lsrs r3, r3, #16
|
|
80107c8: fb06 2303 mla r3, r6, r3, r2
|
|
80107cc: f8de 2000 ldr.w r2, [lr]
|
|
80107d0: b280 uxth r0, r0
|
|
80107d2: b292 uxth r2, r2
|
|
80107d4: 1a12 subs r2, r2, r0
|
|
80107d6: 445a add r2, fp
|
|
80107d8: f8de 0000 ldr.w r0, [lr]
|
|
80107dc: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
80107e0: b29b uxth r3, r3
|
|
80107e2: ebc3 4322 rsb r3, r3, r2, asr #16
|
|
80107e6: eb03 4310 add.w r3, r3, r0, lsr #16
|
|
80107ea: b292 uxth r2, r2
|
|
80107ec: ea42 4203 orr.w r2, r2, r3, lsl #16
|
|
80107f0: 45e1 cmp r9, ip
|
|
80107f2: f84e 2b04 str.w r2, [lr], #4
|
|
80107f6: ea4f 4b23 mov.w fp, r3, asr #16
|
|
80107fa: d2de bcs.n 80107ba <quorem+0x42>
|
|
80107fc: 9b00 ldr r3, [sp, #0]
|
|
80107fe: 58eb ldr r3, [r5, r3]
|
|
8010800: b92b cbnz r3, 801080e <quorem+0x96>
|
|
8010802: 9b01 ldr r3, [sp, #4]
|
|
8010804: 3b04 subs r3, #4
|
|
8010806: 429d cmp r5, r3
|
|
8010808: 461a mov r2, r3
|
|
801080a: d32f bcc.n 801086c <quorem+0xf4>
|
|
801080c: 613c str r4, [r7, #16]
|
|
801080e: 4638 mov r0, r7
|
|
8010810: f001 f9c6 bl 8011ba0 <__mcmp>
|
|
8010814: 2800 cmp r0, #0
|
|
8010816: db25 blt.n 8010864 <quorem+0xec>
|
|
8010818: 4629 mov r1, r5
|
|
801081a: 2000 movs r0, #0
|
|
801081c: f858 2b04 ldr.w r2, [r8], #4
|
|
8010820: f8d1 c000 ldr.w ip, [r1]
|
|
8010824: fa1f fe82 uxth.w lr, r2
|
|
8010828: fa1f f38c uxth.w r3, ip
|
|
801082c: eba3 030e sub.w r3, r3, lr
|
|
8010830: 4403 add r3, r0
|
|
8010832: 0c12 lsrs r2, r2, #16
|
|
8010834: ebc2 4223 rsb r2, r2, r3, asr #16
|
|
8010838: eb02 421c add.w r2, r2, ip, lsr #16
|
|
801083c: b29b uxth r3, r3
|
|
801083e: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8010842: 45c1 cmp r9, r8
|
|
8010844: f841 3b04 str.w r3, [r1], #4
|
|
8010848: ea4f 4022 mov.w r0, r2, asr #16
|
|
801084c: d2e6 bcs.n 801081c <quorem+0xa4>
|
|
801084e: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
8010852: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
8010856: b922 cbnz r2, 8010862 <quorem+0xea>
|
|
8010858: 3b04 subs r3, #4
|
|
801085a: 429d cmp r5, r3
|
|
801085c: 461a mov r2, r3
|
|
801085e: d30b bcc.n 8010878 <quorem+0x100>
|
|
8010860: 613c str r4, [r7, #16]
|
|
8010862: 3601 adds r6, #1
|
|
8010864: 4630 mov r0, r6
|
|
8010866: b003 add sp, #12
|
|
8010868: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801086c: 6812 ldr r2, [r2, #0]
|
|
801086e: 3b04 subs r3, #4
|
|
8010870: 2a00 cmp r2, #0
|
|
8010872: d1cb bne.n 801080c <quorem+0x94>
|
|
8010874: 3c01 subs r4, #1
|
|
8010876: e7c6 b.n 8010806 <quorem+0x8e>
|
|
8010878: 6812 ldr r2, [r2, #0]
|
|
801087a: 3b04 subs r3, #4
|
|
801087c: 2a00 cmp r2, #0
|
|
801087e: d1ef bne.n 8010860 <quorem+0xe8>
|
|
8010880: 3c01 subs r4, #1
|
|
8010882: e7ea b.n 801085a <quorem+0xe2>
|
|
8010884: 2000 movs r0, #0
|
|
8010886: e7ee b.n 8010866 <quorem+0xee>
|
|
|
|
08010888 <_dtoa_r>:
|
|
8010888: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801088c: 69c7 ldr r7, [r0, #28]
|
|
801088e: b097 sub sp, #92 @ 0x5c
|
|
8010890: ed8d 0b04 vstr d0, [sp, #16]
|
|
8010894: ec55 4b10 vmov r4, r5, d0
|
|
8010898: 9e20 ldr r6, [sp, #128] @ 0x80
|
|
801089a: 9107 str r1, [sp, #28]
|
|
801089c: 4681 mov r9, r0
|
|
801089e: 920c str r2, [sp, #48] @ 0x30
|
|
80108a0: 9311 str r3, [sp, #68] @ 0x44
|
|
80108a2: b97f cbnz r7, 80108c4 <_dtoa_r+0x3c>
|
|
80108a4: 2010 movs r0, #16
|
|
80108a6: f000 fe09 bl 80114bc <malloc>
|
|
80108aa: 4602 mov r2, r0
|
|
80108ac: f8c9 001c str.w r0, [r9, #28]
|
|
80108b0: b920 cbnz r0, 80108bc <_dtoa_r+0x34>
|
|
80108b2: 4ba9 ldr r3, [pc, #676] @ (8010b58 <_dtoa_r+0x2d0>)
|
|
80108b4: 21ef movs r1, #239 @ 0xef
|
|
80108b6: 48a9 ldr r0, [pc, #676] @ (8010b5c <_dtoa_r+0x2d4>)
|
|
80108b8: f7ff ff40 bl 801073c <__assert_func>
|
|
80108bc: e9c0 7701 strd r7, r7, [r0, #4]
|
|
80108c0: 6007 str r7, [r0, #0]
|
|
80108c2: 60c7 str r7, [r0, #12]
|
|
80108c4: f8d9 301c ldr.w r3, [r9, #28]
|
|
80108c8: 6819 ldr r1, [r3, #0]
|
|
80108ca: b159 cbz r1, 80108e4 <_dtoa_r+0x5c>
|
|
80108cc: 685a ldr r2, [r3, #4]
|
|
80108ce: 604a str r2, [r1, #4]
|
|
80108d0: 2301 movs r3, #1
|
|
80108d2: 4093 lsls r3, r2
|
|
80108d4: 608b str r3, [r1, #8]
|
|
80108d6: 4648 mov r0, r9
|
|
80108d8: f000 fee6 bl 80116a8 <_Bfree>
|
|
80108dc: f8d9 301c ldr.w r3, [r9, #28]
|
|
80108e0: 2200 movs r2, #0
|
|
80108e2: 601a str r2, [r3, #0]
|
|
80108e4: 1e2b subs r3, r5, #0
|
|
80108e6: bfb9 ittee lt
|
|
80108e8: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000
|
|
80108ec: 9305 strlt r3, [sp, #20]
|
|
80108ee: 2300 movge r3, #0
|
|
80108f0: 6033 strge r3, [r6, #0]
|
|
80108f2: 9f05 ldr r7, [sp, #20]
|
|
80108f4: 4b9a ldr r3, [pc, #616] @ (8010b60 <_dtoa_r+0x2d8>)
|
|
80108f6: bfbc itt lt
|
|
80108f8: 2201 movlt r2, #1
|
|
80108fa: 6032 strlt r2, [r6, #0]
|
|
80108fc: 43bb bics r3, r7
|
|
80108fe: d112 bne.n 8010926 <_dtoa_r+0x9e>
|
|
8010900: 9a11 ldr r2, [sp, #68] @ 0x44
|
|
8010902: f242 730f movw r3, #9999 @ 0x270f
|
|
8010906: 6013 str r3, [r2, #0]
|
|
8010908: f3c7 0313 ubfx r3, r7, #0, #20
|
|
801090c: 4323 orrs r3, r4
|
|
801090e: f000 855a beq.w 80113c6 <_dtoa_r+0xb3e>
|
|
8010912: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8010914: f8df a25c ldr.w sl, [pc, #604] @ 8010b74 <_dtoa_r+0x2ec>
|
|
8010918: 2b00 cmp r3, #0
|
|
801091a: f000 855c beq.w 80113d6 <_dtoa_r+0xb4e>
|
|
801091e: f10a 0303 add.w r3, sl, #3
|
|
8010922: f000 bd56 b.w 80113d2 <_dtoa_r+0xb4a>
|
|
8010926: ed9d 7b04 vldr d7, [sp, #16]
|
|
801092a: 2200 movs r2, #0
|
|
801092c: ec51 0b17 vmov r0, r1, d7
|
|
8010930: 2300 movs r3, #0
|
|
8010932: ed8d 7b0a vstr d7, [sp, #40] @ 0x28
|
|
8010936: f7f0 f8c7 bl 8000ac8 <__aeabi_dcmpeq>
|
|
801093a: 4680 mov r8, r0
|
|
801093c: b158 cbz r0, 8010956 <_dtoa_r+0xce>
|
|
801093e: 9a11 ldr r2, [sp, #68] @ 0x44
|
|
8010940: 2301 movs r3, #1
|
|
8010942: 6013 str r3, [r2, #0]
|
|
8010944: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8010946: b113 cbz r3, 801094e <_dtoa_r+0xc6>
|
|
8010948: 9a21 ldr r2, [sp, #132] @ 0x84
|
|
801094a: 4b86 ldr r3, [pc, #536] @ (8010b64 <_dtoa_r+0x2dc>)
|
|
801094c: 6013 str r3, [r2, #0]
|
|
801094e: f8df a228 ldr.w sl, [pc, #552] @ 8010b78 <_dtoa_r+0x2f0>
|
|
8010952: f000 bd40 b.w 80113d6 <_dtoa_r+0xb4e>
|
|
8010956: ed9d 0b0a vldr d0, [sp, #40] @ 0x28
|
|
801095a: aa14 add r2, sp, #80 @ 0x50
|
|
801095c: a915 add r1, sp, #84 @ 0x54
|
|
801095e: 4648 mov r0, r9
|
|
8010960: f001 fa3e bl 8011de0 <__d2b>
|
|
8010964: f3c7 560a ubfx r6, r7, #20, #11
|
|
8010968: 9002 str r0, [sp, #8]
|
|
801096a: 2e00 cmp r6, #0
|
|
801096c: d078 beq.n 8010a60 <_dtoa_r+0x1d8>
|
|
801096e: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8010970: f8cd 8048 str.w r8, [sp, #72] @ 0x48
|
|
8010974: f3c3 0313 ubfx r3, r3, #0, #20
|
|
8010978: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
801097c: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000
|
|
8010980: f443 1340 orr.w r3, r3, #3145728 @ 0x300000
|
|
8010984: f2a6 36ff subw r6, r6, #1023 @ 0x3ff
|
|
8010988: 4619 mov r1, r3
|
|
801098a: 2200 movs r2, #0
|
|
801098c: 4b76 ldr r3, [pc, #472] @ (8010b68 <_dtoa_r+0x2e0>)
|
|
801098e: f7ef fc7b bl 8000288 <__aeabi_dsub>
|
|
8010992: a36b add r3, pc, #428 @ (adr r3, 8010b40 <_dtoa_r+0x2b8>)
|
|
8010994: e9d3 2300 ldrd r2, r3, [r3]
|
|
8010998: f7ef fe2e bl 80005f8 <__aeabi_dmul>
|
|
801099c: a36a add r3, pc, #424 @ (adr r3, 8010b48 <_dtoa_r+0x2c0>)
|
|
801099e: e9d3 2300 ldrd r2, r3, [r3]
|
|
80109a2: f7ef fc73 bl 800028c <__adddf3>
|
|
80109a6: 4604 mov r4, r0
|
|
80109a8: 4630 mov r0, r6
|
|
80109aa: 460d mov r5, r1
|
|
80109ac: f7ef fdba bl 8000524 <__aeabi_i2d>
|
|
80109b0: a367 add r3, pc, #412 @ (adr r3, 8010b50 <_dtoa_r+0x2c8>)
|
|
80109b2: e9d3 2300 ldrd r2, r3, [r3]
|
|
80109b6: f7ef fe1f bl 80005f8 <__aeabi_dmul>
|
|
80109ba: 4602 mov r2, r0
|
|
80109bc: 460b mov r3, r1
|
|
80109be: 4620 mov r0, r4
|
|
80109c0: 4629 mov r1, r5
|
|
80109c2: f7ef fc63 bl 800028c <__adddf3>
|
|
80109c6: 4604 mov r4, r0
|
|
80109c8: 460d mov r5, r1
|
|
80109ca: f7f0 f8c5 bl 8000b58 <__aeabi_d2iz>
|
|
80109ce: 2200 movs r2, #0
|
|
80109d0: 4607 mov r7, r0
|
|
80109d2: 2300 movs r3, #0
|
|
80109d4: 4620 mov r0, r4
|
|
80109d6: 4629 mov r1, r5
|
|
80109d8: f7f0 f880 bl 8000adc <__aeabi_dcmplt>
|
|
80109dc: b140 cbz r0, 80109f0 <_dtoa_r+0x168>
|
|
80109de: 4638 mov r0, r7
|
|
80109e0: f7ef fda0 bl 8000524 <__aeabi_i2d>
|
|
80109e4: 4622 mov r2, r4
|
|
80109e6: 462b mov r3, r5
|
|
80109e8: f7f0 f86e bl 8000ac8 <__aeabi_dcmpeq>
|
|
80109ec: b900 cbnz r0, 80109f0 <_dtoa_r+0x168>
|
|
80109ee: 3f01 subs r7, #1
|
|
80109f0: 2f16 cmp r7, #22
|
|
80109f2: d852 bhi.n 8010a9a <_dtoa_r+0x212>
|
|
80109f4: 4b5d ldr r3, [pc, #372] @ (8010b6c <_dtoa_r+0x2e4>)
|
|
80109f6: eb03 03c7 add.w r3, r3, r7, lsl #3
|
|
80109fa: e9d3 2300 ldrd r2, r3, [r3]
|
|
80109fe: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
8010a02: f7f0 f86b bl 8000adc <__aeabi_dcmplt>
|
|
8010a06: 2800 cmp r0, #0
|
|
8010a08: d049 beq.n 8010a9e <_dtoa_r+0x216>
|
|
8010a0a: 3f01 subs r7, #1
|
|
8010a0c: 2300 movs r3, #0
|
|
8010a0e: 9310 str r3, [sp, #64] @ 0x40
|
|
8010a10: 9b14 ldr r3, [sp, #80] @ 0x50
|
|
8010a12: 1b9b subs r3, r3, r6
|
|
8010a14: 1e5a subs r2, r3, #1
|
|
8010a16: bf45 ittet mi
|
|
8010a18: f1c3 0301 rsbmi r3, r3, #1
|
|
8010a1c: 9300 strmi r3, [sp, #0]
|
|
8010a1e: 2300 movpl r3, #0
|
|
8010a20: 2300 movmi r3, #0
|
|
8010a22: 9206 str r2, [sp, #24]
|
|
8010a24: bf54 ite pl
|
|
8010a26: 9300 strpl r3, [sp, #0]
|
|
8010a28: 9306 strmi r3, [sp, #24]
|
|
8010a2a: 2f00 cmp r7, #0
|
|
8010a2c: db39 blt.n 8010aa2 <_dtoa_r+0x21a>
|
|
8010a2e: 9b06 ldr r3, [sp, #24]
|
|
8010a30: 970d str r7, [sp, #52] @ 0x34
|
|
8010a32: 443b add r3, r7
|
|
8010a34: 9306 str r3, [sp, #24]
|
|
8010a36: 2300 movs r3, #0
|
|
8010a38: 9308 str r3, [sp, #32]
|
|
8010a3a: 9b07 ldr r3, [sp, #28]
|
|
8010a3c: 2b09 cmp r3, #9
|
|
8010a3e: d863 bhi.n 8010b08 <_dtoa_r+0x280>
|
|
8010a40: 2b05 cmp r3, #5
|
|
8010a42: bfc4 itt gt
|
|
8010a44: 3b04 subgt r3, #4
|
|
8010a46: 9307 strgt r3, [sp, #28]
|
|
8010a48: 9b07 ldr r3, [sp, #28]
|
|
8010a4a: f1a3 0302 sub.w r3, r3, #2
|
|
8010a4e: bfcc ite gt
|
|
8010a50: 2400 movgt r4, #0
|
|
8010a52: 2401 movle r4, #1
|
|
8010a54: 2b03 cmp r3, #3
|
|
8010a56: d863 bhi.n 8010b20 <_dtoa_r+0x298>
|
|
8010a58: e8df f003 tbb [pc, r3]
|
|
8010a5c: 2b375452 .word 0x2b375452
|
|
8010a60: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50
|
|
8010a64: 441e add r6, r3
|
|
8010a66: f206 4332 addw r3, r6, #1074 @ 0x432
|
|
8010a6a: 2b20 cmp r3, #32
|
|
8010a6c: bfc1 itttt gt
|
|
8010a6e: f1c3 0340 rsbgt r3, r3, #64 @ 0x40
|
|
8010a72: 409f lslgt r7, r3
|
|
8010a74: f206 4312 addwgt r3, r6, #1042 @ 0x412
|
|
8010a78: fa24 f303 lsrgt.w r3, r4, r3
|
|
8010a7c: bfd6 itet le
|
|
8010a7e: f1c3 0320 rsble r3, r3, #32
|
|
8010a82: ea47 0003 orrgt.w r0, r7, r3
|
|
8010a86: fa04 f003 lslle.w r0, r4, r3
|
|
8010a8a: f7ef fd3b bl 8000504 <__aeabi_ui2d>
|
|
8010a8e: 2201 movs r2, #1
|
|
8010a90: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000
|
|
8010a94: 3e01 subs r6, #1
|
|
8010a96: 9212 str r2, [sp, #72] @ 0x48
|
|
8010a98: e776 b.n 8010988 <_dtoa_r+0x100>
|
|
8010a9a: 2301 movs r3, #1
|
|
8010a9c: e7b7 b.n 8010a0e <_dtoa_r+0x186>
|
|
8010a9e: 9010 str r0, [sp, #64] @ 0x40
|
|
8010aa0: e7b6 b.n 8010a10 <_dtoa_r+0x188>
|
|
8010aa2: 9b00 ldr r3, [sp, #0]
|
|
8010aa4: 1bdb subs r3, r3, r7
|
|
8010aa6: 9300 str r3, [sp, #0]
|
|
8010aa8: 427b negs r3, r7
|
|
8010aaa: 9308 str r3, [sp, #32]
|
|
8010aac: 2300 movs r3, #0
|
|
8010aae: 930d str r3, [sp, #52] @ 0x34
|
|
8010ab0: e7c3 b.n 8010a3a <_dtoa_r+0x1b2>
|
|
8010ab2: 2301 movs r3, #1
|
|
8010ab4: 9309 str r3, [sp, #36] @ 0x24
|
|
8010ab6: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8010ab8: eb07 0b03 add.w fp, r7, r3
|
|
8010abc: f10b 0301 add.w r3, fp, #1
|
|
8010ac0: 2b01 cmp r3, #1
|
|
8010ac2: 9303 str r3, [sp, #12]
|
|
8010ac4: bfb8 it lt
|
|
8010ac6: 2301 movlt r3, #1
|
|
8010ac8: e006 b.n 8010ad8 <_dtoa_r+0x250>
|
|
8010aca: 2301 movs r3, #1
|
|
8010acc: 9309 str r3, [sp, #36] @ 0x24
|
|
8010ace: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8010ad0: 2b00 cmp r3, #0
|
|
8010ad2: dd28 ble.n 8010b26 <_dtoa_r+0x29e>
|
|
8010ad4: 469b mov fp, r3
|
|
8010ad6: 9303 str r3, [sp, #12]
|
|
8010ad8: f8d9 001c ldr.w r0, [r9, #28]
|
|
8010adc: 2100 movs r1, #0
|
|
8010ade: 2204 movs r2, #4
|
|
8010ae0: f102 0514 add.w r5, r2, #20
|
|
8010ae4: 429d cmp r5, r3
|
|
8010ae6: d926 bls.n 8010b36 <_dtoa_r+0x2ae>
|
|
8010ae8: 6041 str r1, [r0, #4]
|
|
8010aea: 4648 mov r0, r9
|
|
8010aec: f000 fd9c bl 8011628 <_Balloc>
|
|
8010af0: 4682 mov sl, r0
|
|
8010af2: 2800 cmp r0, #0
|
|
8010af4: d142 bne.n 8010b7c <_dtoa_r+0x2f4>
|
|
8010af6: 4b1e ldr r3, [pc, #120] @ (8010b70 <_dtoa_r+0x2e8>)
|
|
8010af8: 4602 mov r2, r0
|
|
8010afa: f240 11af movw r1, #431 @ 0x1af
|
|
8010afe: e6da b.n 80108b6 <_dtoa_r+0x2e>
|
|
8010b00: 2300 movs r3, #0
|
|
8010b02: e7e3 b.n 8010acc <_dtoa_r+0x244>
|
|
8010b04: 2300 movs r3, #0
|
|
8010b06: e7d5 b.n 8010ab4 <_dtoa_r+0x22c>
|
|
8010b08: 2401 movs r4, #1
|
|
8010b0a: 2300 movs r3, #0
|
|
8010b0c: 9307 str r3, [sp, #28]
|
|
8010b0e: 9409 str r4, [sp, #36] @ 0x24
|
|
8010b10: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff
|
|
8010b14: 2200 movs r2, #0
|
|
8010b16: f8cd b00c str.w fp, [sp, #12]
|
|
8010b1a: 2312 movs r3, #18
|
|
8010b1c: 920c str r2, [sp, #48] @ 0x30
|
|
8010b1e: e7db b.n 8010ad8 <_dtoa_r+0x250>
|
|
8010b20: 2301 movs r3, #1
|
|
8010b22: 9309 str r3, [sp, #36] @ 0x24
|
|
8010b24: e7f4 b.n 8010b10 <_dtoa_r+0x288>
|
|
8010b26: f04f 0b01 mov.w fp, #1
|
|
8010b2a: f8cd b00c str.w fp, [sp, #12]
|
|
8010b2e: 465b mov r3, fp
|
|
8010b30: f8cd b030 str.w fp, [sp, #48] @ 0x30
|
|
8010b34: e7d0 b.n 8010ad8 <_dtoa_r+0x250>
|
|
8010b36: 3101 adds r1, #1
|
|
8010b38: 0052 lsls r2, r2, #1
|
|
8010b3a: e7d1 b.n 8010ae0 <_dtoa_r+0x258>
|
|
8010b3c: f3af 8000 nop.w
|
|
8010b40: 636f4361 .word 0x636f4361
|
|
8010b44: 3fd287a7 .word 0x3fd287a7
|
|
8010b48: 8b60c8b3 .word 0x8b60c8b3
|
|
8010b4c: 3fc68a28 .word 0x3fc68a28
|
|
8010b50: 509f79fb .word 0x509f79fb
|
|
8010b54: 3fd34413 .word 0x3fd34413
|
|
8010b58: 080147c5 .word 0x080147c5
|
|
8010b5c: 0801487f .word 0x0801487f
|
|
8010b60: 7ff00000 .word 0x7ff00000
|
|
8010b64: 0801479d .word 0x0801479d
|
|
8010b68: 3ff80000 .word 0x3ff80000
|
|
8010b6c: 080149f0 .word 0x080149f0
|
|
8010b70: 080148d7 .word 0x080148d7
|
|
8010b74: 0801487b .word 0x0801487b
|
|
8010b78: 0801479c .word 0x0801479c
|
|
8010b7c: f8d9 301c ldr.w r3, [r9, #28]
|
|
8010b80: 6018 str r0, [r3, #0]
|
|
8010b82: 9b03 ldr r3, [sp, #12]
|
|
8010b84: 2b0e cmp r3, #14
|
|
8010b86: f200 80a1 bhi.w 8010ccc <_dtoa_r+0x444>
|
|
8010b8a: 2c00 cmp r4, #0
|
|
8010b8c: f000 809e beq.w 8010ccc <_dtoa_r+0x444>
|
|
8010b90: 2f00 cmp r7, #0
|
|
8010b92: dd33 ble.n 8010bfc <_dtoa_r+0x374>
|
|
8010b94: 4b9c ldr r3, [pc, #624] @ (8010e08 <_dtoa_r+0x580>)
|
|
8010b96: f007 020f and.w r2, r7, #15
|
|
8010b9a: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
8010b9e: ed93 7b00 vldr d7, [r3]
|
|
8010ba2: 05f8 lsls r0, r7, #23
|
|
8010ba4: ed8d 7b0e vstr d7, [sp, #56] @ 0x38
|
|
8010ba8: ea4f 1427 mov.w r4, r7, asr #4
|
|
8010bac: d516 bpl.n 8010bdc <_dtoa_r+0x354>
|
|
8010bae: 4b97 ldr r3, [pc, #604] @ (8010e0c <_dtoa_r+0x584>)
|
|
8010bb0: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
8010bb4: e9d3 2308 ldrd r2, r3, [r3, #32]
|
|
8010bb8: f7ef fe48 bl 800084c <__aeabi_ddiv>
|
|
8010bbc: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8010bc0: f004 040f and.w r4, r4, #15
|
|
8010bc4: 2603 movs r6, #3
|
|
8010bc6: 4d91 ldr r5, [pc, #580] @ (8010e0c <_dtoa_r+0x584>)
|
|
8010bc8: b954 cbnz r4, 8010be0 <_dtoa_r+0x358>
|
|
8010bca: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8010bce: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010bd2: f7ef fe3b bl 800084c <__aeabi_ddiv>
|
|
8010bd6: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8010bda: e028 b.n 8010c2e <_dtoa_r+0x3a6>
|
|
8010bdc: 2602 movs r6, #2
|
|
8010bde: e7f2 b.n 8010bc6 <_dtoa_r+0x33e>
|
|
8010be0: 07e1 lsls r1, r4, #31
|
|
8010be2: d508 bpl.n 8010bf6 <_dtoa_r+0x36e>
|
|
8010be4: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8010be8: e9d5 2300 ldrd r2, r3, [r5]
|
|
8010bec: f7ef fd04 bl 80005f8 <__aeabi_dmul>
|
|
8010bf0: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8010bf4: 3601 adds r6, #1
|
|
8010bf6: 1064 asrs r4, r4, #1
|
|
8010bf8: 3508 adds r5, #8
|
|
8010bfa: e7e5 b.n 8010bc8 <_dtoa_r+0x340>
|
|
8010bfc: f000 80af beq.w 8010d5e <_dtoa_r+0x4d6>
|
|
8010c00: 427c negs r4, r7
|
|
8010c02: 4b81 ldr r3, [pc, #516] @ (8010e08 <_dtoa_r+0x580>)
|
|
8010c04: 4d81 ldr r5, [pc, #516] @ (8010e0c <_dtoa_r+0x584>)
|
|
8010c06: f004 020f and.w r2, r4, #15
|
|
8010c0a: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
8010c0e: e9d3 2300 ldrd r2, r3, [r3]
|
|
8010c12: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
8010c16: f7ef fcef bl 80005f8 <__aeabi_dmul>
|
|
8010c1a: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8010c1e: 1124 asrs r4, r4, #4
|
|
8010c20: 2300 movs r3, #0
|
|
8010c22: 2602 movs r6, #2
|
|
8010c24: 2c00 cmp r4, #0
|
|
8010c26: f040 808f bne.w 8010d48 <_dtoa_r+0x4c0>
|
|
8010c2a: 2b00 cmp r3, #0
|
|
8010c2c: d1d3 bne.n 8010bd6 <_dtoa_r+0x34e>
|
|
8010c2e: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
8010c30: e9dd 4504 ldrd r4, r5, [sp, #16]
|
|
8010c34: 2b00 cmp r3, #0
|
|
8010c36: f000 8094 beq.w 8010d62 <_dtoa_r+0x4da>
|
|
8010c3a: 4b75 ldr r3, [pc, #468] @ (8010e10 <_dtoa_r+0x588>)
|
|
8010c3c: 2200 movs r2, #0
|
|
8010c3e: 4620 mov r0, r4
|
|
8010c40: 4629 mov r1, r5
|
|
8010c42: f7ef ff4b bl 8000adc <__aeabi_dcmplt>
|
|
8010c46: 2800 cmp r0, #0
|
|
8010c48: f000 808b beq.w 8010d62 <_dtoa_r+0x4da>
|
|
8010c4c: 9b03 ldr r3, [sp, #12]
|
|
8010c4e: 2b00 cmp r3, #0
|
|
8010c50: f000 8087 beq.w 8010d62 <_dtoa_r+0x4da>
|
|
8010c54: f1bb 0f00 cmp.w fp, #0
|
|
8010c58: dd34 ble.n 8010cc4 <_dtoa_r+0x43c>
|
|
8010c5a: 4620 mov r0, r4
|
|
8010c5c: 4b6d ldr r3, [pc, #436] @ (8010e14 <_dtoa_r+0x58c>)
|
|
8010c5e: 2200 movs r2, #0
|
|
8010c60: 4629 mov r1, r5
|
|
8010c62: f7ef fcc9 bl 80005f8 <__aeabi_dmul>
|
|
8010c66: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8010c6a: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
|
|
8010c6e: 3601 adds r6, #1
|
|
8010c70: 465c mov r4, fp
|
|
8010c72: 4630 mov r0, r6
|
|
8010c74: f7ef fc56 bl 8000524 <__aeabi_i2d>
|
|
8010c78: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8010c7c: f7ef fcbc bl 80005f8 <__aeabi_dmul>
|
|
8010c80: 4b65 ldr r3, [pc, #404] @ (8010e18 <_dtoa_r+0x590>)
|
|
8010c82: 2200 movs r2, #0
|
|
8010c84: f7ef fb02 bl 800028c <__adddf3>
|
|
8010c88: 4605 mov r5, r0
|
|
8010c8a: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000
|
|
8010c8e: 2c00 cmp r4, #0
|
|
8010c90: d16a bne.n 8010d68 <_dtoa_r+0x4e0>
|
|
8010c92: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010c96: 4b61 ldr r3, [pc, #388] @ (8010e1c <_dtoa_r+0x594>)
|
|
8010c98: 2200 movs r2, #0
|
|
8010c9a: f7ef faf5 bl 8000288 <__aeabi_dsub>
|
|
8010c9e: 4602 mov r2, r0
|
|
8010ca0: 460b mov r3, r1
|
|
8010ca2: e9cd 2304 strd r2, r3, [sp, #16]
|
|
8010ca6: 462a mov r2, r5
|
|
8010ca8: 4633 mov r3, r6
|
|
8010caa: f7ef ff35 bl 8000b18 <__aeabi_dcmpgt>
|
|
8010cae: 2800 cmp r0, #0
|
|
8010cb0: f040 8298 bne.w 80111e4 <_dtoa_r+0x95c>
|
|
8010cb4: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010cb8: 462a mov r2, r5
|
|
8010cba: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000
|
|
8010cbe: f7ef ff0d bl 8000adc <__aeabi_dcmplt>
|
|
8010cc2: bb38 cbnz r0, 8010d14 <_dtoa_r+0x48c>
|
|
8010cc4: e9dd 340a ldrd r3, r4, [sp, #40] @ 0x28
|
|
8010cc8: e9cd 3404 strd r3, r4, [sp, #16]
|
|
8010ccc: 9b15 ldr r3, [sp, #84] @ 0x54
|
|
8010cce: 2b00 cmp r3, #0
|
|
8010cd0: f2c0 8157 blt.w 8010f82 <_dtoa_r+0x6fa>
|
|
8010cd4: 2f0e cmp r7, #14
|
|
8010cd6: f300 8154 bgt.w 8010f82 <_dtoa_r+0x6fa>
|
|
8010cda: 4b4b ldr r3, [pc, #300] @ (8010e08 <_dtoa_r+0x580>)
|
|
8010cdc: eb03 03c7 add.w r3, r3, r7, lsl #3
|
|
8010ce0: ed93 7b00 vldr d7, [r3]
|
|
8010ce4: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8010ce6: 2b00 cmp r3, #0
|
|
8010ce8: ed8d 7b00 vstr d7, [sp]
|
|
8010cec: f280 80e5 bge.w 8010eba <_dtoa_r+0x632>
|
|
8010cf0: 9b03 ldr r3, [sp, #12]
|
|
8010cf2: 2b00 cmp r3, #0
|
|
8010cf4: f300 80e1 bgt.w 8010eba <_dtoa_r+0x632>
|
|
8010cf8: d10c bne.n 8010d14 <_dtoa_r+0x48c>
|
|
8010cfa: 4b48 ldr r3, [pc, #288] @ (8010e1c <_dtoa_r+0x594>)
|
|
8010cfc: 2200 movs r2, #0
|
|
8010cfe: ec51 0b17 vmov r0, r1, d7
|
|
8010d02: f7ef fc79 bl 80005f8 <__aeabi_dmul>
|
|
8010d06: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8010d0a: f7ef fefb bl 8000b04 <__aeabi_dcmpge>
|
|
8010d0e: 2800 cmp r0, #0
|
|
8010d10: f000 8266 beq.w 80111e0 <_dtoa_r+0x958>
|
|
8010d14: 2400 movs r4, #0
|
|
8010d16: 4625 mov r5, r4
|
|
8010d18: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8010d1a: 4656 mov r6, sl
|
|
8010d1c: ea6f 0803 mvn.w r8, r3
|
|
8010d20: 2700 movs r7, #0
|
|
8010d22: 4621 mov r1, r4
|
|
8010d24: 4648 mov r0, r9
|
|
8010d26: f000 fcbf bl 80116a8 <_Bfree>
|
|
8010d2a: 2d00 cmp r5, #0
|
|
8010d2c: f000 80bd beq.w 8010eaa <_dtoa_r+0x622>
|
|
8010d30: b12f cbz r7, 8010d3e <_dtoa_r+0x4b6>
|
|
8010d32: 42af cmp r7, r5
|
|
8010d34: d003 beq.n 8010d3e <_dtoa_r+0x4b6>
|
|
8010d36: 4639 mov r1, r7
|
|
8010d38: 4648 mov r0, r9
|
|
8010d3a: f000 fcb5 bl 80116a8 <_Bfree>
|
|
8010d3e: 4629 mov r1, r5
|
|
8010d40: 4648 mov r0, r9
|
|
8010d42: f000 fcb1 bl 80116a8 <_Bfree>
|
|
8010d46: e0b0 b.n 8010eaa <_dtoa_r+0x622>
|
|
8010d48: 07e2 lsls r2, r4, #31
|
|
8010d4a: d505 bpl.n 8010d58 <_dtoa_r+0x4d0>
|
|
8010d4c: e9d5 2300 ldrd r2, r3, [r5]
|
|
8010d50: f7ef fc52 bl 80005f8 <__aeabi_dmul>
|
|
8010d54: 3601 adds r6, #1
|
|
8010d56: 2301 movs r3, #1
|
|
8010d58: 1064 asrs r4, r4, #1
|
|
8010d5a: 3508 adds r5, #8
|
|
8010d5c: e762 b.n 8010c24 <_dtoa_r+0x39c>
|
|
8010d5e: 2602 movs r6, #2
|
|
8010d60: e765 b.n 8010c2e <_dtoa_r+0x3a6>
|
|
8010d62: 9c03 ldr r4, [sp, #12]
|
|
8010d64: 46b8 mov r8, r7
|
|
8010d66: e784 b.n 8010c72 <_dtoa_r+0x3ea>
|
|
8010d68: 4b27 ldr r3, [pc, #156] @ (8010e08 <_dtoa_r+0x580>)
|
|
8010d6a: 9909 ldr r1, [sp, #36] @ 0x24
|
|
8010d6c: eb03 03c4 add.w r3, r3, r4, lsl #3
|
|
8010d70: e953 2302 ldrd r2, r3, [r3, #-8]
|
|
8010d74: 4454 add r4, sl
|
|
8010d76: 2900 cmp r1, #0
|
|
8010d78: d054 beq.n 8010e24 <_dtoa_r+0x59c>
|
|
8010d7a: 4929 ldr r1, [pc, #164] @ (8010e20 <_dtoa_r+0x598>)
|
|
8010d7c: 2000 movs r0, #0
|
|
8010d7e: f7ef fd65 bl 800084c <__aeabi_ddiv>
|
|
8010d82: 4633 mov r3, r6
|
|
8010d84: 462a mov r2, r5
|
|
8010d86: f7ef fa7f bl 8000288 <__aeabi_dsub>
|
|
8010d8a: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8010d8e: 4656 mov r6, sl
|
|
8010d90: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010d94: f7ef fee0 bl 8000b58 <__aeabi_d2iz>
|
|
8010d98: 4605 mov r5, r0
|
|
8010d9a: f7ef fbc3 bl 8000524 <__aeabi_i2d>
|
|
8010d9e: 4602 mov r2, r0
|
|
8010da0: 460b mov r3, r1
|
|
8010da2: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010da6: f7ef fa6f bl 8000288 <__aeabi_dsub>
|
|
8010daa: 3530 adds r5, #48 @ 0x30
|
|
8010dac: 4602 mov r2, r0
|
|
8010dae: 460b mov r3, r1
|
|
8010db0: e9cd 2304 strd r2, r3, [sp, #16]
|
|
8010db4: f806 5b01 strb.w r5, [r6], #1
|
|
8010db8: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8010dbc: f7ef fe8e bl 8000adc <__aeabi_dcmplt>
|
|
8010dc0: 2800 cmp r0, #0
|
|
8010dc2: d172 bne.n 8010eaa <_dtoa_r+0x622>
|
|
8010dc4: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8010dc8: 4911 ldr r1, [pc, #68] @ (8010e10 <_dtoa_r+0x588>)
|
|
8010dca: 2000 movs r0, #0
|
|
8010dcc: f7ef fa5c bl 8000288 <__aeabi_dsub>
|
|
8010dd0: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8010dd4: f7ef fe82 bl 8000adc <__aeabi_dcmplt>
|
|
8010dd8: 2800 cmp r0, #0
|
|
8010dda: f040 80b4 bne.w 8010f46 <_dtoa_r+0x6be>
|
|
8010dde: 42a6 cmp r6, r4
|
|
8010de0: f43f af70 beq.w 8010cc4 <_dtoa_r+0x43c>
|
|
8010de4: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8010de8: 4b0a ldr r3, [pc, #40] @ (8010e14 <_dtoa_r+0x58c>)
|
|
8010dea: 2200 movs r2, #0
|
|
8010dec: f7ef fc04 bl 80005f8 <__aeabi_dmul>
|
|
8010df0: 4b08 ldr r3, [pc, #32] @ (8010e14 <_dtoa_r+0x58c>)
|
|
8010df2: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8010df6: 2200 movs r2, #0
|
|
8010df8: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010dfc: f7ef fbfc bl 80005f8 <__aeabi_dmul>
|
|
8010e00: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8010e04: e7c4 b.n 8010d90 <_dtoa_r+0x508>
|
|
8010e06: bf00 nop
|
|
8010e08: 080149f0 .word 0x080149f0
|
|
8010e0c: 080149c8 .word 0x080149c8
|
|
8010e10: 3ff00000 .word 0x3ff00000
|
|
8010e14: 40240000 .word 0x40240000
|
|
8010e18: 401c0000 .word 0x401c0000
|
|
8010e1c: 40140000 .word 0x40140000
|
|
8010e20: 3fe00000 .word 0x3fe00000
|
|
8010e24: 4631 mov r1, r6
|
|
8010e26: 4628 mov r0, r5
|
|
8010e28: f7ef fbe6 bl 80005f8 <__aeabi_dmul>
|
|
8010e2c: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8010e30: 9413 str r4, [sp, #76] @ 0x4c
|
|
8010e32: 4656 mov r6, sl
|
|
8010e34: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010e38: f7ef fe8e bl 8000b58 <__aeabi_d2iz>
|
|
8010e3c: 4605 mov r5, r0
|
|
8010e3e: f7ef fb71 bl 8000524 <__aeabi_i2d>
|
|
8010e42: 4602 mov r2, r0
|
|
8010e44: 460b mov r3, r1
|
|
8010e46: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010e4a: f7ef fa1d bl 8000288 <__aeabi_dsub>
|
|
8010e4e: 3530 adds r5, #48 @ 0x30
|
|
8010e50: f806 5b01 strb.w r5, [r6], #1
|
|
8010e54: 4602 mov r2, r0
|
|
8010e56: 460b mov r3, r1
|
|
8010e58: 42a6 cmp r6, r4
|
|
8010e5a: e9cd 2304 strd r2, r3, [sp, #16]
|
|
8010e5e: f04f 0200 mov.w r2, #0
|
|
8010e62: d124 bne.n 8010eae <_dtoa_r+0x626>
|
|
8010e64: 4baf ldr r3, [pc, #700] @ (8011124 <_dtoa_r+0x89c>)
|
|
8010e66: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8010e6a: f7ef fa0f bl 800028c <__adddf3>
|
|
8010e6e: 4602 mov r2, r0
|
|
8010e70: 460b mov r3, r1
|
|
8010e72: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010e76: f7ef fe4f bl 8000b18 <__aeabi_dcmpgt>
|
|
8010e7a: 2800 cmp r0, #0
|
|
8010e7c: d163 bne.n 8010f46 <_dtoa_r+0x6be>
|
|
8010e7e: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8010e82: 49a8 ldr r1, [pc, #672] @ (8011124 <_dtoa_r+0x89c>)
|
|
8010e84: 2000 movs r0, #0
|
|
8010e86: f7ef f9ff bl 8000288 <__aeabi_dsub>
|
|
8010e8a: 4602 mov r2, r0
|
|
8010e8c: 460b mov r3, r1
|
|
8010e8e: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8010e92: f7ef fe23 bl 8000adc <__aeabi_dcmplt>
|
|
8010e96: 2800 cmp r0, #0
|
|
8010e98: f43f af14 beq.w 8010cc4 <_dtoa_r+0x43c>
|
|
8010e9c: 9e13 ldr r6, [sp, #76] @ 0x4c
|
|
8010e9e: 1e73 subs r3, r6, #1
|
|
8010ea0: 9313 str r3, [sp, #76] @ 0x4c
|
|
8010ea2: f816 3c01 ldrb.w r3, [r6, #-1]
|
|
8010ea6: 2b30 cmp r3, #48 @ 0x30
|
|
8010ea8: d0f8 beq.n 8010e9c <_dtoa_r+0x614>
|
|
8010eaa: 4647 mov r7, r8
|
|
8010eac: e03b b.n 8010f26 <_dtoa_r+0x69e>
|
|
8010eae: 4b9e ldr r3, [pc, #632] @ (8011128 <_dtoa_r+0x8a0>)
|
|
8010eb0: f7ef fba2 bl 80005f8 <__aeabi_dmul>
|
|
8010eb4: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8010eb8: e7bc b.n 8010e34 <_dtoa_r+0x5ac>
|
|
8010eba: e9dd 4504 ldrd r4, r5, [sp, #16]
|
|
8010ebe: 4656 mov r6, sl
|
|
8010ec0: e9dd 2300 ldrd r2, r3, [sp]
|
|
8010ec4: 4620 mov r0, r4
|
|
8010ec6: 4629 mov r1, r5
|
|
8010ec8: f7ef fcc0 bl 800084c <__aeabi_ddiv>
|
|
8010ecc: f7ef fe44 bl 8000b58 <__aeabi_d2iz>
|
|
8010ed0: 4680 mov r8, r0
|
|
8010ed2: f7ef fb27 bl 8000524 <__aeabi_i2d>
|
|
8010ed6: e9dd 2300 ldrd r2, r3, [sp]
|
|
8010eda: f7ef fb8d bl 80005f8 <__aeabi_dmul>
|
|
8010ede: 4602 mov r2, r0
|
|
8010ee0: 460b mov r3, r1
|
|
8010ee2: 4620 mov r0, r4
|
|
8010ee4: 4629 mov r1, r5
|
|
8010ee6: f108 0430 add.w r4, r8, #48 @ 0x30
|
|
8010eea: f7ef f9cd bl 8000288 <__aeabi_dsub>
|
|
8010eee: f806 4b01 strb.w r4, [r6], #1
|
|
8010ef2: 9d03 ldr r5, [sp, #12]
|
|
8010ef4: eba6 040a sub.w r4, r6, sl
|
|
8010ef8: 42a5 cmp r5, r4
|
|
8010efa: 4602 mov r2, r0
|
|
8010efc: 460b mov r3, r1
|
|
8010efe: d133 bne.n 8010f68 <_dtoa_r+0x6e0>
|
|
8010f00: f7ef f9c4 bl 800028c <__adddf3>
|
|
8010f04: e9dd 2300 ldrd r2, r3, [sp]
|
|
8010f08: 4604 mov r4, r0
|
|
8010f0a: 460d mov r5, r1
|
|
8010f0c: f7ef fe04 bl 8000b18 <__aeabi_dcmpgt>
|
|
8010f10: b9c0 cbnz r0, 8010f44 <_dtoa_r+0x6bc>
|
|
8010f12: e9dd 2300 ldrd r2, r3, [sp]
|
|
8010f16: 4620 mov r0, r4
|
|
8010f18: 4629 mov r1, r5
|
|
8010f1a: f7ef fdd5 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8010f1e: b110 cbz r0, 8010f26 <_dtoa_r+0x69e>
|
|
8010f20: f018 0f01 tst.w r8, #1
|
|
8010f24: d10e bne.n 8010f44 <_dtoa_r+0x6bc>
|
|
8010f26: 9902 ldr r1, [sp, #8]
|
|
8010f28: 4648 mov r0, r9
|
|
8010f2a: f000 fbbd bl 80116a8 <_Bfree>
|
|
8010f2e: 2300 movs r3, #0
|
|
8010f30: 7033 strb r3, [r6, #0]
|
|
8010f32: 9b11 ldr r3, [sp, #68] @ 0x44
|
|
8010f34: 3701 adds r7, #1
|
|
8010f36: 601f str r7, [r3, #0]
|
|
8010f38: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8010f3a: 2b00 cmp r3, #0
|
|
8010f3c: f000 824b beq.w 80113d6 <_dtoa_r+0xb4e>
|
|
8010f40: 601e str r6, [r3, #0]
|
|
8010f42: e248 b.n 80113d6 <_dtoa_r+0xb4e>
|
|
8010f44: 46b8 mov r8, r7
|
|
8010f46: 4633 mov r3, r6
|
|
8010f48: 461e mov r6, r3
|
|
8010f4a: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
8010f4e: 2a39 cmp r2, #57 @ 0x39
|
|
8010f50: d106 bne.n 8010f60 <_dtoa_r+0x6d8>
|
|
8010f52: 459a cmp sl, r3
|
|
8010f54: d1f8 bne.n 8010f48 <_dtoa_r+0x6c0>
|
|
8010f56: 2230 movs r2, #48 @ 0x30
|
|
8010f58: f108 0801 add.w r8, r8, #1
|
|
8010f5c: f88a 2000 strb.w r2, [sl]
|
|
8010f60: 781a ldrb r2, [r3, #0]
|
|
8010f62: 3201 adds r2, #1
|
|
8010f64: 701a strb r2, [r3, #0]
|
|
8010f66: e7a0 b.n 8010eaa <_dtoa_r+0x622>
|
|
8010f68: 4b6f ldr r3, [pc, #444] @ (8011128 <_dtoa_r+0x8a0>)
|
|
8010f6a: 2200 movs r2, #0
|
|
8010f6c: f7ef fb44 bl 80005f8 <__aeabi_dmul>
|
|
8010f70: 2200 movs r2, #0
|
|
8010f72: 2300 movs r3, #0
|
|
8010f74: 4604 mov r4, r0
|
|
8010f76: 460d mov r5, r1
|
|
8010f78: f7ef fda6 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8010f7c: 2800 cmp r0, #0
|
|
8010f7e: d09f beq.n 8010ec0 <_dtoa_r+0x638>
|
|
8010f80: e7d1 b.n 8010f26 <_dtoa_r+0x69e>
|
|
8010f82: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8010f84: 2a00 cmp r2, #0
|
|
8010f86: f000 80ea beq.w 801115e <_dtoa_r+0x8d6>
|
|
8010f8a: 9a07 ldr r2, [sp, #28]
|
|
8010f8c: 2a01 cmp r2, #1
|
|
8010f8e: f300 80cd bgt.w 801112c <_dtoa_r+0x8a4>
|
|
8010f92: 9a12 ldr r2, [sp, #72] @ 0x48
|
|
8010f94: 2a00 cmp r2, #0
|
|
8010f96: f000 80c1 beq.w 801111c <_dtoa_r+0x894>
|
|
8010f9a: f203 4333 addw r3, r3, #1075 @ 0x433
|
|
8010f9e: 9c08 ldr r4, [sp, #32]
|
|
8010fa0: 9e00 ldr r6, [sp, #0]
|
|
8010fa2: 9a00 ldr r2, [sp, #0]
|
|
8010fa4: 441a add r2, r3
|
|
8010fa6: 9200 str r2, [sp, #0]
|
|
8010fa8: 9a06 ldr r2, [sp, #24]
|
|
8010faa: 2101 movs r1, #1
|
|
8010fac: 441a add r2, r3
|
|
8010fae: 4648 mov r0, r9
|
|
8010fb0: 9206 str r2, [sp, #24]
|
|
8010fb2: f000 fc77 bl 80118a4 <__i2b>
|
|
8010fb6: 4605 mov r5, r0
|
|
8010fb8: b166 cbz r6, 8010fd4 <_dtoa_r+0x74c>
|
|
8010fba: 9b06 ldr r3, [sp, #24]
|
|
8010fbc: 2b00 cmp r3, #0
|
|
8010fbe: dd09 ble.n 8010fd4 <_dtoa_r+0x74c>
|
|
8010fc0: 42b3 cmp r3, r6
|
|
8010fc2: 9a00 ldr r2, [sp, #0]
|
|
8010fc4: bfa8 it ge
|
|
8010fc6: 4633 movge r3, r6
|
|
8010fc8: 1ad2 subs r2, r2, r3
|
|
8010fca: 9200 str r2, [sp, #0]
|
|
8010fcc: 9a06 ldr r2, [sp, #24]
|
|
8010fce: 1af6 subs r6, r6, r3
|
|
8010fd0: 1ad3 subs r3, r2, r3
|
|
8010fd2: 9306 str r3, [sp, #24]
|
|
8010fd4: 9b08 ldr r3, [sp, #32]
|
|
8010fd6: b30b cbz r3, 801101c <_dtoa_r+0x794>
|
|
8010fd8: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8010fda: 2b00 cmp r3, #0
|
|
8010fdc: f000 80c6 beq.w 801116c <_dtoa_r+0x8e4>
|
|
8010fe0: 2c00 cmp r4, #0
|
|
8010fe2: f000 80c0 beq.w 8011166 <_dtoa_r+0x8de>
|
|
8010fe6: 4629 mov r1, r5
|
|
8010fe8: 4622 mov r2, r4
|
|
8010fea: 4648 mov r0, r9
|
|
8010fec: f000 fd12 bl 8011a14 <__pow5mult>
|
|
8010ff0: 9a02 ldr r2, [sp, #8]
|
|
8010ff2: 4601 mov r1, r0
|
|
8010ff4: 4605 mov r5, r0
|
|
8010ff6: 4648 mov r0, r9
|
|
8010ff8: f000 fc6a bl 80118d0 <__multiply>
|
|
8010ffc: 9902 ldr r1, [sp, #8]
|
|
8010ffe: 4680 mov r8, r0
|
|
8011000: 4648 mov r0, r9
|
|
8011002: f000 fb51 bl 80116a8 <_Bfree>
|
|
8011006: 9b08 ldr r3, [sp, #32]
|
|
8011008: 1b1b subs r3, r3, r4
|
|
801100a: 9308 str r3, [sp, #32]
|
|
801100c: f000 80b1 beq.w 8011172 <_dtoa_r+0x8ea>
|
|
8011010: 9a08 ldr r2, [sp, #32]
|
|
8011012: 4641 mov r1, r8
|
|
8011014: 4648 mov r0, r9
|
|
8011016: f000 fcfd bl 8011a14 <__pow5mult>
|
|
801101a: 9002 str r0, [sp, #8]
|
|
801101c: 2101 movs r1, #1
|
|
801101e: 4648 mov r0, r9
|
|
8011020: f000 fc40 bl 80118a4 <__i2b>
|
|
8011024: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8011026: 4604 mov r4, r0
|
|
8011028: 2b00 cmp r3, #0
|
|
801102a: f000 81d8 beq.w 80113de <_dtoa_r+0xb56>
|
|
801102e: 461a mov r2, r3
|
|
8011030: 4601 mov r1, r0
|
|
8011032: 4648 mov r0, r9
|
|
8011034: f000 fcee bl 8011a14 <__pow5mult>
|
|
8011038: 9b07 ldr r3, [sp, #28]
|
|
801103a: 2b01 cmp r3, #1
|
|
801103c: 4604 mov r4, r0
|
|
801103e: f300 809f bgt.w 8011180 <_dtoa_r+0x8f8>
|
|
8011042: 9b04 ldr r3, [sp, #16]
|
|
8011044: 2b00 cmp r3, #0
|
|
8011046: f040 8097 bne.w 8011178 <_dtoa_r+0x8f0>
|
|
801104a: 9b05 ldr r3, [sp, #20]
|
|
801104c: f3c3 0313 ubfx r3, r3, #0, #20
|
|
8011050: 2b00 cmp r3, #0
|
|
8011052: f040 8093 bne.w 801117c <_dtoa_r+0x8f4>
|
|
8011056: 9b05 ldr r3, [sp, #20]
|
|
8011058: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
801105c: 0d1b lsrs r3, r3, #20
|
|
801105e: 051b lsls r3, r3, #20
|
|
8011060: b133 cbz r3, 8011070 <_dtoa_r+0x7e8>
|
|
8011062: 9b00 ldr r3, [sp, #0]
|
|
8011064: 3301 adds r3, #1
|
|
8011066: 9300 str r3, [sp, #0]
|
|
8011068: 9b06 ldr r3, [sp, #24]
|
|
801106a: 3301 adds r3, #1
|
|
801106c: 9306 str r3, [sp, #24]
|
|
801106e: 2301 movs r3, #1
|
|
8011070: 9308 str r3, [sp, #32]
|
|
8011072: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8011074: 2b00 cmp r3, #0
|
|
8011076: f000 81b8 beq.w 80113ea <_dtoa_r+0xb62>
|
|
801107a: 6923 ldr r3, [r4, #16]
|
|
801107c: eb04 0383 add.w r3, r4, r3, lsl #2
|
|
8011080: 6918 ldr r0, [r3, #16]
|
|
8011082: f000 fbc3 bl 801180c <__hi0bits>
|
|
8011086: f1c0 0020 rsb r0, r0, #32
|
|
801108a: 9b06 ldr r3, [sp, #24]
|
|
801108c: 4418 add r0, r3
|
|
801108e: f010 001f ands.w r0, r0, #31
|
|
8011092: f000 8082 beq.w 801119a <_dtoa_r+0x912>
|
|
8011096: f1c0 0320 rsb r3, r0, #32
|
|
801109a: 2b04 cmp r3, #4
|
|
801109c: dd73 ble.n 8011186 <_dtoa_r+0x8fe>
|
|
801109e: 9b00 ldr r3, [sp, #0]
|
|
80110a0: f1c0 001c rsb r0, r0, #28
|
|
80110a4: 4403 add r3, r0
|
|
80110a6: 9300 str r3, [sp, #0]
|
|
80110a8: 9b06 ldr r3, [sp, #24]
|
|
80110aa: 4403 add r3, r0
|
|
80110ac: 4406 add r6, r0
|
|
80110ae: 9306 str r3, [sp, #24]
|
|
80110b0: 9b00 ldr r3, [sp, #0]
|
|
80110b2: 2b00 cmp r3, #0
|
|
80110b4: dd05 ble.n 80110c2 <_dtoa_r+0x83a>
|
|
80110b6: 9902 ldr r1, [sp, #8]
|
|
80110b8: 461a mov r2, r3
|
|
80110ba: 4648 mov r0, r9
|
|
80110bc: f000 fd04 bl 8011ac8 <__lshift>
|
|
80110c0: 9002 str r0, [sp, #8]
|
|
80110c2: 9b06 ldr r3, [sp, #24]
|
|
80110c4: 2b00 cmp r3, #0
|
|
80110c6: dd05 ble.n 80110d4 <_dtoa_r+0x84c>
|
|
80110c8: 4621 mov r1, r4
|
|
80110ca: 461a mov r2, r3
|
|
80110cc: 4648 mov r0, r9
|
|
80110ce: f000 fcfb bl 8011ac8 <__lshift>
|
|
80110d2: 4604 mov r4, r0
|
|
80110d4: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
80110d6: 2b00 cmp r3, #0
|
|
80110d8: d061 beq.n 801119e <_dtoa_r+0x916>
|
|
80110da: 9802 ldr r0, [sp, #8]
|
|
80110dc: 4621 mov r1, r4
|
|
80110de: f000 fd5f bl 8011ba0 <__mcmp>
|
|
80110e2: 2800 cmp r0, #0
|
|
80110e4: da5b bge.n 801119e <_dtoa_r+0x916>
|
|
80110e6: 2300 movs r3, #0
|
|
80110e8: 9902 ldr r1, [sp, #8]
|
|
80110ea: 220a movs r2, #10
|
|
80110ec: 4648 mov r0, r9
|
|
80110ee: f000 fafd bl 80116ec <__multadd>
|
|
80110f2: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80110f4: 9002 str r0, [sp, #8]
|
|
80110f6: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
|
|
80110fa: 2b00 cmp r3, #0
|
|
80110fc: f000 8177 beq.w 80113ee <_dtoa_r+0xb66>
|
|
8011100: 4629 mov r1, r5
|
|
8011102: 2300 movs r3, #0
|
|
8011104: 220a movs r2, #10
|
|
8011106: 4648 mov r0, r9
|
|
8011108: f000 faf0 bl 80116ec <__multadd>
|
|
801110c: f1bb 0f00 cmp.w fp, #0
|
|
8011110: 4605 mov r5, r0
|
|
8011112: dc6f bgt.n 80111f4 <_dtoa_r+0x96c>
|
|
8011114: 9b07 ldr r3, [sp, #28]
|
|
8011116: 2b02 cmp r3, #2
|
|
8011118: dc49 bgt.n 80111ae <_dtoa_r+0x926>
|
|
801111a: e06b b.n 80111f4 <_dtoa_r+0x96c>
|
|
801111c: 9b14 ldr r3, [sp, #80] @ 0x50
|
|
801111e: f1c3 0336 rsb r3, r3, #54 @ 0x36
|
|
8011122: e73c b.n 8010f9e <_dtoa_r+0x716>
|
|
8011124: 3fe00000 .word 0x3fe00000
|
|
8011128: 40240000 .word 0x40240000
|
|
801112c: 9b03 ldr r3, [sp, #12]
|
|
801112e: 1e5c subs r4, r3, #1
|
|
8011130: 9b08 ldr r3, [sp, #32]
|
|
8011132: 42a3 cmp r3, r4
|
|
8011134: db09 blt.n 801114a <_dtoa_r+0x8c2>
|
|
8011136: 1b1c subs r4, r3, r4
|
|
8011138: 9b03 ldr r3, [sp, #12]
|
|
801113a: 2b00 cmp r3, #0
|
|
801113c: f6bf af30 bge.w 8010fa0 <_dtoa_r+0x718>
|
|
8011140: 9b00 ldr r3, [sp, #0]
|
|
8011142: 9a03 ldr r2, [sp, #12]
|
|
8011144: 1a9e subs r6, r3, r2
|
|
8011146: 2300 movs r3, #0
|
|
8011148: e72b b.n 8010fa2 <_dtoa_r+0x71a>
|
|
801114a: 9b08 ldr r3, [sp, #32]
|
|
801114c: 9a0d ldr r2, [sp, #52] @ 0x34
|
|
801114e: 9408 str r4, [sp, #32]
|
|
8011150: 1ae3 subs r3, r4, r3
|
|
8011152: 441a add r2, r3
|
|
8011154: 9e00 ldr r6, [sp, #0]
|
|
8011156: 9b03 ldr r3, [sp, #12]
|
|
8011158: 920d str r2, [sp, #52] @ 0x34
|
|
801115a: 2400 movs r4, #0
|
|
801115c: e721 b.n 8010fa2 <_dtoa_r+0x71a>
|
|
801115e: 9c08 ldr r4, [sp, #32]
|
|
8011160: 9e00 ldr r6, [sp, #0]
|
|
8011162: 9d09 ldr r5, [sp, #36] @ 0x24
|
|
8011164: e728 b.n 8010fb8 <_dtoa_r+0x730>
|
|
8011166: f8dd 8008 ldr.w r8, [sp, #8]
|
|
801116a: e751 b.n 8011010 <_dtoa_r+0x788>
|
|
801116c: 9a08 ldr r2, [sp, #32]
|
|
801116e: 9902 ldr r1, [sp, #8]
|
|
8011170: e750 b.n 8011014 <_dtoa_r+0x78c>
|
|
8011172: f8cd 8008 str.w r8, [sp, #8]
|
|
8011176: e751 b.n 801101c <_dtoa_r+0x794>
|
|
8011178: 2300 movs r3, #0
|
|
801117a: e779 b.n 8011070 <_dtoa_r+0x7e8>
|
|
801117c: 9b04 ldr r3, [sp, #16]
|
|
801117e: e777 b.n 8011070 <_dtoa_r+0x7e8>
|
|
8011180: 2300 movs r3, #0
|
|
8011182: 9308 str r3, [sp, #32]
|
|
8011184: e779 b.n 801107a <_dtoa_r+0x7f2>
|
|
8011186: d093 beq.n 80110b0 <_dtoa_r+0x828>
|
|
8011188: 9a00 ldr r2, [sp, #0]
|
|
801118a: 331c adds r3, #28
|
|
801118c: 441a add r2, r3
|
|
801118e: 9200 str r2, [sp, #0]
|
|
8011190: 9a06 ldr r2, [sp, #24]
|
|
8011192: 441a add r2, r3
|
|
8011194: 441e add r6, r3
|
|
8011196: 9206 str r2, [sp, #24]
|
|
8011198: e78a b.n 80110b0 <_dtoa_r+0x828>
|
|
801119a: 4603 mov r3, r0
|
|
801119c: e7f4 b.n 8011188 <_dtoa_r+0x900>
|
|
801119e: 9b03 ldr r3, [sp, #12]
|
|
80111a0: 2b00 cmp r3, #0
|
|
80111a2: 46b8 mov r8, r7
|
|
80111a4: dc20 bgt.n 80111e8 <_dtoa_r+0x960>
|
|
80111a6: 469b mov fp, r3
|
|
80111a8: 9b07 ldr r3, [sp, #28]
|
|
80111aa: 2b02 cmp r3, #2
|
|
80111ac: dd1e ble.n 80111ec <_dtoa_r+0x964>
|
|
80111ae: f1bb 0f00 cmp.w fp, #0
|
|
80111b2: f47f adb1 bne.w 8010d18 <_dtoa_r+0x490>
|
|
80111b6: 4621 mov r1, r4
|
|
80111b8: 465b mov r3, fp
|
|
80111ba: 2205 movs r2, #5
|
|
80111bc: 4648 mov r0, r9
|
|
80111be: f000 fa95 bl 80116ec <__multadd>
|
|
80111c2: 4601 mov r1, r0
|
|
80111c4: 4604 mov r4, r0
|
|
80111c6: 9802 ldr r0, [sp, #8]
|
|
80111c8: f000 fcea bl 8011ba0 <__mcmp>
|
|
80111cc: 2800 cmp r0, #0
|
|
80111ce: f77f ada3 ble.w 8010d18 <_dtoa_r+0x490>
|
|
80111d2: 4656 mov r6, sl
|
|
80111d4: 2331 movs r3, #49 @ 0x31
|
|
80111d6: f806 3b01 strb.w r3, [r6], #1
|
|
80111da: f108 0801 add.w r8, r8, #1
|
|
80111de: e59f b.n 8010d20 <_dtoa_r+0x498>
|
|
80111e0: 9c03 ldr r4, [sp, #12]
|
|
80111e2: 46b8 mov r8, r7
|
|
80111e4: 4625 mov r5, r4
|
|
80111e6: e7f4 b.n 80111d2 <_dtoa_r+0x94a>
|
|
80111e8: f8dd b00c ldr.w fp, [sp, #12]
|
|
80111ec: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80111ee: 2b00 cmp r3, #0
|
|
80111f0: f000 8101 beq.w 80113f6 <_dtoa_r+0xb6e>
|
|
80111f4: 2e00 cmp r6, #0
|
|
80111f6: dd05 ble.n 8011204 <_dtoa_r+0x97c>
|
|
80111f8: 4629 mov r1, r5
|
|
80111fa: 4632 mov r2, r6
|
|
80111fc: 4648 mov r0, r9
|
|
80111fe: f000 fc63 bl 8011ac8 <__lshift>
|
|
8011202: 4605 mov r5, r0
|
|
8011204: 9b08 ldr r3, [sp, #32]
|
|
8011206: 2b00 cmp r3, #0
|
|
8011208: d05c beq.n 80112c4 <_dtoa_r+0xa3c>
|
|
801120a: 6869 ldr r1, [r5, #4]
|
|
801120c: 4648 mov r0, r9
|
|
801120e: f000 fa0b bl 8011628 <_Balloc>
|
|
8011212: 4606 mov r6, r0
|
|
8011214: b928 cbnz r0, 8011222 <_dtoa_r+0x99a>
|
|
8011216: 4b82 ldr r3, [pc, #520] @ (8011420 <_dtoa_r+0xb98>)
|
|
8011218: 4602 mov r2, r0
|
|
801121a: f240 21ef movw r1, #751 @ 0x2ef
|
|
801121e: f7ff bb4a b.w 80108b6 <_dtoa_r+0x2e>
|
|
8011222: 692a ldr r2, [r5, #16]
|
|
8011224: 3202 adds r2, #2
|
|
8011226: 0092 lsls r2, r2, #2
|
|
8011228: f105 010c add.w r1, r5, #12
|
|
801122c: 300c adds r0, #12
|
|
801122e: f7ff fa70 bl 8010712 <memcpy>
|
|
8011232: 2201 movs r2, #1
|
|
8011234: 4631 mov r1, r6
|
|
8011236: 4648 mov r0, r9
|
|
8011238: f000 fc46 bl 8011ac8 <__lshift>
|
|
801123c: f10a 0301 add.w r3, sl, #1
|
|
8011240: 9300 str r3, [sp, #0]
|
|
8011242: eb0a 030b add.w r3, sl, fp
|
|
8011246: 9308 str r3, [sp, #32]
|
|
8011248: 9b04 ldr r3, [sp, #16]
|
|
801124a: f003 0301 and.w r3, r3, #1
|
|
801124e: 462f mov r7, r5
|
|
8011250: 9306 str r3, [sp, #24]
|
|
8011252: 4605 mov r5, r0
|
|
8011254: 9b00 ldr r3, [sp, #0]
|
|
8011256: 9802 ldr r0, [sp, #8]
|
|
8011258: 4621 mov r1, r4
|
|
801125a: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff
|
|
801125e: f7ff fa8b bl 8010778 <quorem>
|
|
8011262: 4603 mov r3, r0
|
|
8011264: 3330 adds r3, #48 @ 0x30
|
|
8011266: 9003 str r0, [sp, #12]
|
|
8011268: 4639 mov r1, r7
|
|
801126a: 9802 ldr r0, [sp, #8]
|
|
801126c: 9309 str r3, [sp, #36] @ 0x24
|
|
801126e: f000 fc97 bl 8011ba0 <__mcmp>
|
|
8011272: 462a mov r2, r5
|
|
8011274: 9004 str r0, [sp, #16]
|
|
8011276: 4621 mov r1, r4
|
|
8011278: 4648 mov r0, r9
|
|
801127a: f000 fcad bl 8011bd8 <__mdiff>
|
|
801127e: 68c2 ldr r2, [r0, #12]
|
|
8011280: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8011282: 4606 mov r6, r0
|
|
8011284: bb02 cbnz r2, 80112c8 <_dtoa_r+0xa40>
|
|
8011286: 4601 mov r1, r0
|
|
8011288: 9802 ldr r0, [sp, #8]
|
|
801128a: f000 fc89 bl 8011ba0 <__mcmp>
|
|
801128e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8011290: 4602 mov r2, r0
|
|
8011292: 4631 mov r1, r6
|
|
8011294: 4648 mov r0, r9
|
|
8011296: 920c str r2, [sp, #48] @ 0x30
|
|
8011298: 9309 str r3, [sp, #36] @ 0x24
|
|
801129a: f000 fa05 bl 80116a8 <_Bfree>
|
|
801129e: 9b07 ldr r3, [sp, #28]
|
|
80112a0: 9a0c ldr r2, [sp, #48] @ 0x30
|
|
80112a2: 9e00 ldr r6, [sp, #0]
|
|
80112a4: ea42 0103 orr.w r1, r2, r3
|
|
80112a8: 9b06 ldr r3, [sp, #24]
|
|
80112aa: 4319 orrs r1, r3
|
|
80112ac: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80112ae: d10d bne.n 80112cc <_dtoa_r+0xa44>
|
|
80112b0: 2b39 cmp r3, #57 @ 0x39
|
|
80112b2: d027 beq.n 8011304 <_dtoa_r+0xa7c>
|
|
80112b4: 9a04 ldr r2, [sp, #16]
|
|
80112b6: 2a00 cmp r2, #0
|
|
80112b8: dd01 ble.n 80112be <_dtoa_r+0xa36>
|
|
80112ba: 9b03 ldr r3, [sp, #12]
|
|
80112bc: 3331 adds r3, #49 @ 0x31
|
|
80112be: f88b 3000 strb.w r3, [fp]
|
|
80112c2: e52e b.n 8010d22 <_dtoa_r+0x49a>
|
|
80112c4: 4628 mov r0, r5
|
|
80112c6: e7b9 b.n 801123c <_dtoa_r+0x9b4>
|
|
80112c8: 2201 movs r2, #1
|
|
80112ca: e7e2 b.n 8011292 <_dtoa_r+0xa0a>
|
|
80112cc: 9904 ldr r1, [sp, #16]
|
|
80112ce: 2900 cmp r1, #0
|
|
80112d0: db04 blt.n 80112dc <_dtoa_r+0xa54>
|
|
80112d2: 9807 ldr r0, [sp, #28]
|
|
80112d4: 4301 orrs r1, r0
|
|
80112d6: 9806 ldr r0, [sp, #24]
|
|
80112d8: 4301 orrs r1, r0
|
|
80112da: d120 bne.n 801131e <_dtoa_r+0xa96>
|
|
80112dc: 2a00 cmp r2, #0
|
|
80112de: ddee ble.n 80112be <_dtoa_r+0xa36>
|
|
80112e0: 9902 ldr r1, [sp, #8]
|
|
80112e2: 9300 str r3, [sp, #0]
|
|
80112e4: 2201 movs r2, #1
|
|
80112e6: 4648 mov r0, r9
|
|
80112e8: f000 fbee bl 8011ac8 <__lshift>
|
|
80112ec: 4621 mov r1, r4
|
|
80112ee: 9002 str r0, [sp, #8]
|
|
80112f0: f000 fc56 bl 8011ba0 <__mcmp>
|
|
80112f4: 2800 cmp r0, #0
|
|
80112f6: 9b00 ldr r3, [sp, #0]
|
|
80112f8: dc02 bgt.n 8011300 <_dtoa_r+0xa78>
|
|
80112fa: d1e0 bne.n 80112be <_dtoa_r+0xa36>
|
|
80112fc: 07da lsls r2, r3, #31
|
|
80112fe: d5de bpl.n 80112be <_dtoa_r+0xa36>
|
|
8011300: 2b39 cmp r3, #57 @ 0x39
|
|
8011302: d1da bne.n 80112ba <_dtoa_r+0xa32>
|
|
8011304: 2339 movs r3, #57 @ 0x39
|
|
8011306: f88b 3000 strb.w r3, [fp]
|
|
801130a: 4633 mov r3, r6
|
|
801130c: 461e mov r6, r3
|
|
801130e: 3b01 subs r3, #1
|
|
8011310: f816 2c01 ldrb.w r2, [r6, #-1]
|
|
8011314: 2a39 cmp r2, #57 @ 0x39
|
|
8011316: d04e beq.n 80113b6 <_dtoa_r+0xb2e>
|
|
8011318: 3201 adds r2, #1
|
|
801131a: 701a strb r2, [r3, #0]
|
|
801131c: e501 b.n 8010d22 <_dtoa_r+0x49a>
|
|
801131e: 2a00 cmp r2, #0
|
|
8011320: dd03 ble.n 801132a <_dtoa_r+0xaa2>
|
|
8011322: 2b39 cmp r3, #57 @ 0x39
|
|
8011324: d0ee beq.n 8011304 <_dtoa_r+0xa7c>
|
|
8011326: 3301 adds r3, #1
|
|
8011328: e7c9 b.n 80112be <_dtoa_r+0xa36>
|
|
801132a: 9a00 ldr r2, [sp, #0]
|
|
801132c: 9908 ldr r1, [sp, #32]
|
|
801132e: f802 3c01 strb.w r3, [r2, #-1]
|
|
8011332: 428a cmp r2, r1
|
|
8011334: d028 beq.n 8011388 <_dtoa_r+0xb00>
|
|
8011336: 9902 ldr r1, [sp, #8]
|
|
8011338: 2300 movs r3, #0
|
|
801133a: 220a movs r2, #10
|
|
801133c: 4648 mov r0, r9
|
|
801133e: f000 f9d5 bl 80116ec <__multadd>
|
|
8011342: 42af cmp r7, r5
|
|
8011344: 9002 str r0, [sp, #8]
|
|
8011346: f04f 0300 mov.w r3, #0
|
|
801134a: f04f 020a mov.w r2, #10
|
|
801134e: 4639 mov r1, r7
|
|
8011350: 4648 mov r0, r9
|
|
8011352: d107 bne.n 8011364 <_dtoa_r+0xadc>
|
|
8011354: f000 f9ca bl 80116ec <__multadd>
|
|
8011358: 4607 mov r7, r0
|
|
801135a: 4605 mov r5, r0
|
|
801135c: 9b00 ldr r3, [sp, #0]
|
|
801135e: 3301 adds r3, #1
|
|
8011360: 9300 str r3, [sp, #0]
|
|
8011362: e777 b.n 8011254 <_dtoa_r+0x9cc>
|
|
8011364: f000 f9c2 bl 80116ec <__multadd>
|
|
8011368: 4629 mov r1, r5
|
|
801136a: 4607 mov r7, r0
|
|
801136c: 2300 movs r3, #0
|
|
801136e: 220a movs r2, #10
|
|
8011370: 4648 mov r0, r9
|
|
8011372: f000 f9bb bl 80116ec <__multadd>
|
|
8011376: 4605 mov r5, r0
|
|
8011378: e7f0 b.n 801135c <_dtoa_r+0xad4>
|
|
801137a: f1bb 0f00 cmp.w fp, #0
|
|
801137e: bfcc ite gt
|
|
8011380: 465e movgt r6, fp
|
|
8011382: 2601 movle r6, #1
|
|
8011384: 4456 add r6, sl
|
|
8011386: 2700 movs r7, #0
|
|
8011388: 9902 ldr r1, [sp, #8]
|
|
801138a: 9300 str r3, [sp, #0]
|
|
801138c: 2201 movs r2, #1
|
|
801138e: 4648 mov r0, r9
|
|
8011390: f000 fb9a bl 8011ac8 <__lshift>
|
|
8011394: 4621 mov r1, r4
|
|
8011396: 9002 str r0, [sp, #8]
|
|
8011398: f000 fc02 bl 8011ba0 <__mcmp>
|
|
801139c: 2800 cmp r0, #0
|
|
801139e: dcb4 bgt.n 801130a <_dtoa_r+0xa82>
|
|
80113a0: d102 bne.n 80113a8 <_dtoa_r+0xb20>
|
|
80113a2: 9b00 ldr r3, [sp, #0]
|
|
80113a4: 07db lsls r3, r3, #31
|
|
80113a6: d4b0 bmi.n 801130a <_dtoa_r+0xa82>
|
|
80113a8: 4633 mov r3, r6
|
|
80113aa: 461e mov r6, r3
|
|
80113ac: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
80113b0: 2a30 cmp r2, #48 @ 0x30
|
|
80113b2: d0fa beq.n 80113aa <_dtoa_r+0xb22>
|
|
80113b4: e4b5 b.n 8010d22 <_dtoa_r+0x49a>
|
|
80113b6: 459a cmp sl, r3
|
|
80113b8: d1a8 bne.n 801130c <_dtoa_r+0xa84>
|
|
80113ba: 2331 movs r3, #49 @ 0x31
|
|
80113bc: f108 0801 add.w r8, r8, #1
|
|
80113c0: f88a 3000 strb.w r3, [sl]
|
|
80113c4: e4ad b.n 8010d22 <_dtoa_r+0x49a>
|
|
80113c6: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
80113c8: f8df a058 ldr.w sl, [pc, #88] @ 8011424 <_dtoa_r+0xb9c>
|
|
80113cc: b11b cbz r3, 80113d6 <_dtoa_r+0xb4e>
|
|
80113ce: f10a 0308 add.w r3, sl, #8
|
|
80113d2: 9a21 ldr r2, [sp, #132] @ 0x84
|
|
80113d4: 6013 str r3, [r2, #0]
|
|
80113d6: 4650 mov r0, sl
|
|
80113d8: b017 add sp, #92 @ 0x5c
|
|
80113da: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80113de: 9b07 ldr r3, [sp, #28]
|
|
80113e0: 2b01 cmp r3, #1
|
|
80113e2: f77f ae2e ble.w 8011042 <_dtoa_r+0x7ba>
|
|
80113e6: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
80113e8: 9308 str r3, [sp, #32]
|
|
80113ea: 2001 movs r0, #1
|
|
80113ec: e64d b.n 801108a <_dtoa_r+0x802>
|
|
80113ee: f1bb 0f00 cmp.w fp, #0
|
|
80113f2: f77f aed9 ble.w 80111a8 <_dtoa_r+0x920>
|
|
80113f6: 4656 mov r6, sl
|
|
80113f8: 9802 ldr r0, [sp, #8]
|
|
80113fa: 4621 mov r1, r4
|
|
80113fc: f7ff f9bc bl 8010778 <quorem>
|
|
8011400: f100 0330 add.w r3, r0, #48 @ 0x30
|
|
8011404: f806 3b01 strb.w r3, [r6], #1
|
|
8011408: eba6 020a sub.w r2, r6, sl
|
|
801140c: 4593 cmp fp, r2
|
|
801140e: ddb4 ble.n 801137a <_dtoa_r+0xaf2>
|
|
8011410: 9902 ldr r1, [sp, #8]
|
|
8011412: 2300 movs r3, #0
|
|
8011414: 220a movs r2, #10
|
|
8011416: 4648 mov r0, r9
|
|
8011418: f000 f968 bl 80116ec <__multadd>
|
|
801141c: 9002 str r0, [sp, #8]
|
|
801141e: e7eb b.n 80113f8 <_dtoa_r+0xb70>
|
|
8011420: 080148d7 .word 0x080148d7
|
|
8011424: 08014872 .word 0x08014872
|
|
|
|
08011428 <_free_r>:
|
|
8011428: b538 push {r3, r4, r5, lr}
|
|
801142a: 4605 mov r5, r0
|
|
801142c: 2900 cmp r1, #0
|
|
801142e: d041 beq.n 80114b4 <_free_r+0x8c>
|
|
8011430: f851 3c04 ldr.w r3, [r1, #-4]
|
|
8011434: 1f0c subs r4, r1, #4
|
|
8011436: 2b00 cmp r3, #0
|
|
8011438: bfb8 it lt
|
|
801143a: 18e4 addlt r4, r4, r3
|
|
801143c: f000 f8e8 bl 8011610 <__malloc_lock>
|
|
8011440: 4a1d ldr r2, [pc, #116] @ (80114b8 <_free_r+0x90>)
|
|
8011442: 6813 ldr r3, [r2, #0]
|
|
8011444: b933 cbnz r3, 8011454 <_free_r+0x2c>
|
|
8011446: 6063 str r3, [r4, #4]
|
|
8011448: 6014 str r4, [r2, #0]
|
|
801144a: 4628 mov r0, r5
|
|
801144c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8011450: f000 b8e4 b.w 801161c <__malloc_unlock>
|
|
8011454: 42a3 cmp r3, r4
|
|
8011456: d908 bls.n 801146a <_free_r+0x42>
|
|
8011458: 6820 ldr r0, [r4, #0]
|
|
801145a: 1821 adds r1, r4, r0
|
|
801145c: 428b cmp r3, r1
|
|
801145e: bf01 itttt eq
|
|
8011460: 6819 ldreq r1, [r3, #0]
|
|
8011462: 685b ldreq r3, [r3, #4]
|
|
8011464: 1809 addeq r1, r1, r0
|
|
8011466: 6021 streq r1, [r4, #0]
|
|
8011468: e7ed b.n 8011446 <_free_r+0x1e>
|
|
801146a: 461a mov r2, r3
|
|
801146c: 685b ldr r3, [r3, #4]
|
|
801146e: b10b cbz r3, 8011474 <_free_r+0x4c>
|
|
8011470: 42a3 cmp r3, r4
|
|
8011472: d9fa bls.n 801146a <_free_r+0x42>
|
|
8011474: 6811 ldr r1, [r2, #0]
|
|
8011476: 1850 adds r0, r2, r1
|
|
8011478: 42a0 cmp r0, r4
|
|
801147a: d10b bne.n 8011494 <_free_r+0x6c>
|
|
801147c: 6820 ldr r0, [r4, #0]
|
|
801147e: 4401 add r1, r0
|
|
8011480: 1850 adds r0, r2, r1
|
|
8011482: 4283 cmp r3, r0
|
|
8011484: 6011 str r1, [r2, #0]
|
|
8011486: d1e0 bne.n 801144a <_free_r+0x22>
|
|
8011488: 6818 ldr r0, [r3, #0]
|
|
801148a: 685b ldr r3, [r3, #4]
|
|
801148c: 6053 str r3, [r2, #4]
|
|
801148e: 4408 add r0, r1
|
|
8011490: 6010 str r0, [r2, #0]
|
|
8011492: e7da b.n 801144a <_free_r+0x22>
|
|
8011494: d902 bls.n 801149c <_free_r+0x74>
|
|
8011496: 230c movs r3, #12
|
|
8011498: 602b str r3, [r5, #0]
|
|
801149a: e7d6 b.n 801144a <_free_r+0x22>
|
|
801149c: 6820 ldr r0, [r4, #0]
|
|
801149e: 1821 adds r1, r4, r0
|
|
80114a0: 428b cmp r3, r1
|
|
80114a2: bf04 itt eq
|
|
80114a4: 6819 ldreq r1, [r3, #0]
|
|
80114a6: 685b ldreq r3, [r3, #4]
|
|
80114a8: 6063 str r3, [r4, #4]
|
|
80114aa: bf04 itt eq
|
|
80114ac: 1809 addeq r1, r1, r0
|
|
80114ae: 6021 streq r1, [r4, #0]
|
|
80114b0: 6054 str r4, [r2, #4]
|
|
80114b2: e7ca b.n 801144a <_free_r+0x22>
|
|
80114b4: bd38 pop {r3, r4, r5, pc}
|
|
80114b6: bf00 nop
|
|
80114b8: 200036d4 .word 0x200036d4
|
|
|
|
080114bc <malloc>:
|
|
80114bc: 4b02 ldr r3, [pc, #8] @ (80114c8 <malloc+0xc>)
|
|
80114be: 4601 mov r1, r0
|
|
80114c0: 6818 ldr r0, [r3, #0]
|
|
80114c2: f000 b825 b.w 8011510 <_malloc_r>
|
|
80114c6: bf00 nop
|
|
80114c8: 200000e0 .word 0x200000e0
|
|
|
|
080114cc <sbrk_aligned>:
|
|
80114cc: b570 push {r4, r5, r6, lr}
|
|
80114ce: 4e0f ldr r6, [pc, #60] @ (801150c <sbrk_aligned+0x40>)
|
|
80114d0: 460c mov r4, r1
|
|
80114d2: 6831 ldr r1, [r6, #0]
|
|
80114d4: 4605 mov r5, r0
|
|
80114d6: b911 cbnz r1, 80114de <sbrk_aligned+0x12>
|
|
80114d8: f001 ffca bl 8013470 <_sbrk_r>
|
|
80114dc: 6030 str r0, [r6, #0]
|
|
80114de: 4621 mov r1, r4
|
|
80114e0: 4628 mov r0, r5
|
|
80114e2: f001 ffc5 bl 8013470 <_sbrk_r>
|
|
80114e6: 1c43 adds r3, r0, #1
|
|
80114e8: d103 bne.n 80114f2 <sbrk_aligned+0x26>
|
|
80114ea: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
|
|
80114ee: 4620 mov r0, r4
|
|
80114f0: bd70 pop {r4, r5, r6, pc}
|
|
80114f2: 1cc4 adds r4, r0, #3
|
|
80114f4: f024 0403 bic.w r4, r4, #3
|
|
80114f8: 42a0 cmp r0, r4
|
|
80114fa: d0f8 beq.n 80114ee <sbrk_aligned+0x22>
|
|
80114fc: 1a21 subs r1, r4, r0
|
|
80114fe: 4628 mov r0, r5
|
|
8011500: f001 ffb6 bl 8013470 <_sbrk_r>
|
|
8011504: 3001 adds r0, #1
|
|
8011506: d1f2 bne.n 80114ee <sbrk_aligned+0x22>
|
|
8011508: e7ef b.n 80114ea <sbrk_aligned+0x1e>
|
|
801150a: bf00 nop
|
|
801150c: 200036d0 .word 0x200036d0
|
|
|
|
08011510 <_malloc_r>:
|
|
8011510: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
8011514: 1ccd adds r5, r1, #3
|
|
8011516: f025 0503 bic.w r5, r5, #3
|
|
801151a: 3508 adds r5, #8
|
|
801151c: 2d0c cmp r5, #12
|
|
801151e: bf38 it cc
|
|
8011520: 250c movcc r5, #12
|
|
8011522: 2d00 cmp r5, #0
|
|
8011524: 4606 mov r6, r0
|
|
8011526: db01 blt.n 801152c <_malloc_r+0x1c>
|
|
8011528: 42a9 cmp r1, r5
|
|
801152a: d904 bls.n 8011536 <_malloc_r+0x26>
|
|
801152c: 230c movs r3, #12
|
|
801152e: 6033 str r3, [r6, #0]
|
|
8011530: 2000 movs r0, #0
|
|
8011532: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
8011536: f8df 80d4 ldr.w r8, [pc, #212] @ 801160c <_malloc_r+0xfc>
|
|
801153a: f000 f869 bl 8011610 <__malloc_lock>
|
|
801153e: f8d8 3000 ldr.w r3, [r8]
|
|
8011542: 461c mov r4, r3
|
|
8011544: bb44 cbnz r4, 8011598 <_malloc_r+0x88>
|
|
8011546: 4629 mov r1, r5
|
|
8011548: 4630 mov r0, r6
|
|
801154a: f7ff ffbf bl 80114cc <sbrk_aligned>
|
|
801154e: 1c43 adds r3, r0, #1
|
|
8011550: 4604 mov r4, r0
|
|
8011552: d158 bne.n 8011606 <_malloc_r+0xf6>
|
|
8011554: f8d8 4000 ldr.w r4, [r8]
|
|
8011558: 4627 mov r7, r4
|
|
801155a: 2f00 cmp r7, #0
|
|
801155c: d143 bne.n 80115e6 <_malloc_r+0xd6>
|
|
801155e: 2c00 cmp r4, #0
|
|
8011560: d04b beq.n 80115fa <_malloc_r+0xea>
|
|
8011562: 6823 ldr r3, [r4, #0]
|
|
8011564: 4639 mov r1, r7
|
|
8011566: 4630 mov r0, r6
|
|
8011568: eb04 0903 add.w r9, r4, r3
|
|
801156c: f001 ff80 bl 8013470 <_sbrk_r>
|
|
8011570: 4581 cmp r9, r0
|
|
8011572: d142 bne.n 80115fa <_malloc_r+0xea>
|
|
8011574: 6821 ldr r1, [r4, #0]
|
|
8011576: 1a6d subs r5, r5, r1
|
|
8011578: 4629 mov r1, r5
|
|
801157a: 4630 mov r0, r6
|
|
801157c: f7ff ffa6 bl 80114cc <sbrk_aligned>
|
|
8011580: 3001 adds r0, #1
|
|
8011582: d03a beq.n 80115fa <_malloc_r+0xea>
|
|
8011584: 6823 ldr r3, [r4, #0]
|
|
8011586: 442b add r3, r5
|
|
8011588: 6023 str r3, [r4, #0]
|
|
801158a: f8d8 3000 ldr.w r3, [r8]
|
|
801158e: 685a ldr r2, [r3, #4]
|
|
8011590: bb62 cbnz r2, 80115ec <_malloc_r+0xdc>
|
|
8011592: f8c8 7000 str.w r7, [r8]
|
|
8011596: e00f b.n 80115b8 <_malloc_r+0xa8>
|
|
8011598: 6822 ldr r2, [r4, #0]
|
|
801159a: 1b52 subs r2, r2, r5
|
|
801159c: d420 bmi.n 80115e0 <_malloc_r+0xd0>
|
|
801159e: 2a0b cmp r2, #11
|
|
80115a0: d917 bls.n 80115d2 <_malloc_r+0xc2>
|
|
80115a2: 1961 adds r1, r4, r5
|
|
80115a4: 42a3 cmp r3, r4
|
|
80115a6: 6025 str r5, [r4, #0]
|
|
80115a8: bf18 it ne
|
|
80115aa: 6059 strne r1, [r3, #4]
|
|
80115ac: 6863 ldr r3, [r4, #4]
|
|
80115ae: bf08 it eq
|
|
80115b0: f8c8 1000 streq.w r1, [r8]
|
|
80115b4: 5162 str r2, [r4, r5]
|
|
80115b6: 604b str r3, [r1, #4]
|
|
80115b8: 4630 mov r0, r6
|
|
80115ba: f000 f82f bl 801161c <__malloc_unlock>
|
|
80115be: f104 000b add.w r0, r4, #11
|
|
80115c2: 1d23 adds r3, r4, #4
|
|
80115c4: f020 0007 bic.w r0, r0, #7
|
|
80115c8: 1ac2 subs r2, r0, r3
|
|
80115ca: bf1c itt ne
|
|
80115cc: 1a1b subne r3, r3, r0
|
|
80115ce: 50a3 strne r3, [r4, r2]
|
|
80115d0: e7af b.n 8011532 <_malloc_r+0x22>
|
|
80115d2: 6862 ldr r2, [r4, #4]
|
|
80115d4: 42a3 cmp r3, r4
|
|
80115d6: bf0c ite eq
|
|
80115d8: f8c8 2000 streq.w r2, [r8]
|
|
80115dc: 605a strne r2, [r3, #4]
|
|
80115de: e7eb b.n 80115b8 <_malloc_r+0xa8>
|
|
80115e0: 4623 mov r3, r4
|
|
80115e2: 6864 ldr r4, [r4, #4]
|
|
80115e4: e7ae b.n 8011544 <_malloc_r+0x34>
|
|
80115e6: 463c mov r4, r7
|
|
80115e8: 687f ldr r7, [r7, #4]
|
|
80115ea: e7b6 b.n 801155a <_malloc_r+0x4a>
|
|
80115ec: 461a mov r2, r3
|
|
80115ee: 685b ldr r3, [r3, #4]
|
|
80115f0: 42a3 cmp r3, r4
|
|
80115f2: d1fb bne.n 80115ec <_malloc_r+0xdc>
|
|
80115f4: 2300 movs r3, #0
|
|
80115f6: 6053 str r3, [r2, #4]
|
|
80115f8: e7de b.n 80115b8 <_malloc_r+0xa8>
|
|
80115fa: 230c movs r3, #12
|
|
80115fc: 6033 str r3, [r6, #0]
|
|
80115fe: 4630 mov r0, r6
|
|
8011600: f000 f80c bl 801161c <__malloc_unlock>
|
|
8011604: e794 b.n 8011530 <_malloc_r+0x20>
|
|
8011606: 6005 str r5, [r0, #0]
|
|
8011608: e7d6 b.n 80115b8 <_malloc_r+0xa8>
|
|
801160a: bf00 nop
|
|
801160c: 200036d4 .word 0x200036d4
|
|
|
|
08011610 <__malloc_lock>:
|
|
8011610: 4801 ldr r0, [pc, #4] @ (8011618 <__malloc_lock+0x8>)
|
|
8011612: f7ff b87c b.w 801070e <__retarget_lock_acquire_recursive>
|
|
8011616: bf00 nop
|
|
8011618: 200036cc .word 0x200036cc
|
|
|
|
0801161c <__malloc_unlock>:
|
|
801161c: 4801 ldr r0, [pc, #4] @ (8011624 <__malloc_unlock+0x8>)
|
|
801161e: f7ff b877 b.w 8010710 <__retarget_lock_release_recursive>
|
|
8011622: bf00 nop
|
|
8011624: 200036cc .word 0x200036cc
|
|
|
|
08011628 <_Balloc>:
|
|
8011628: b570 push {r4, r5, r6, lr}
|
|
801162a: 69c6 ldr r6, [r0, #28]
|
|
801162c: 4604 mov r4, r0
|
|
801162e: 460d mov r5, r1
|
|
8011630: b976 cbnz r6, 8011650 <_Balloc+0x28>
|
|
8011632: 2010 movs r0, #16
|
|
8011634: f7ff ff42 bl 80114bc <malloc>
|
|
8011638: 4602 mov r2, r0
|
|
801163a: 61e0 str r0, [r4, #28]
|
|
801163c: b920 cbnz r0, 8011648 <_Balloc+0x20>
|
|
801163e: 4b18 ldr r3, [pc, #96] @ (80116a0 <_Balloc+0x78>)
|
|
8011640: 4818 ldr r0, [pc, #96] @ (80116a4 <_Balloc+0x7c>)
|
|
8011642: 216b movs r1, #107 @ 0x6b
|
|
8011644: f7ff f87a bl 801073c <__assert_func>
|
|
8011648: e9c0 6601 strd r6, r6, [r0, #4]
|
|
801164c: 6006 str r6, [r0, #0]
|
|
801164e: 60c6 str r6, [r0, #12]
|
|
8011650: 69e6 ldr r6, [r4, #28]
|
|
8011652: 68f3 ldr r3, [r6, #12]
|
|
8011654: b183 cbz r3, 8011678 <_Balloc+0x50>
|
|
8011656: 69e3 ldr r3, [r4, #28]
|
|
8011658: 68db ldr r3, [r3, #12]
|
|
801165a: f853 0025 ldr.w r0, [r3, r5, lsl #2]
|
|
801165e: b9b8 cbnz r0, 8011690 <_Balloc+0x68>
|
|
8011660: 2101 movs r1, #1
|
|
8011662: fa01 f605 lsl.w r6, r1, r5
|
|
8011666: 1d72 adds r2, r6, #5
|
|
8011668: 0092 lsls r2, r2, #2
|
|
801166a: 4620 mov r0, r4
|
|
801166c: f001 ff1f bl 80134ae <_calloc_r>
|
|
8011670: b160 cbz r0, 801168c <_Balloc+0x64>
|
|
8011672: e9c0 5601 strd r5, r6, [r0, #4]
|
|
8011676: e00e b.n 8011696 <_Balloc+0x6e>
|
|
8011678: 2221 movs r2, #33 @ 0x21
|
|
801167a: 2104 movs r1, #4
|
|
801167c: 4620 mov r0, r4
|
|
801167e: f001 ff16 bl 80134ae <_calloc_r>
|
|
8011682: 69e3 ldr r3, [r4, #28]
|
|
8011684: 60f0 str r0, [r6, #12]
|
|
8011686: 68db ldr r3, [r3, #12]
|
|
8011688: 2b00 cmp r3, #0
|
|
801168a: d1e4 bne.n 8011656 <_Balloc+0x2e>
|
|
801168c: 2000 movs r0, #0
|
|
801168e: bd70 pop {r4, r5, r6, pc}
|
|
8011690: 6802 ldr r2, [r0, #0]
|
|
8011692: f843 2025 str.w r2, [r3, r5, lsl #2]
|
|
8011696: 2300 movs r3, #0
|
|
8011698: e9c0 3303 strd r3, r3, [r0, #12]
|
|
801169c: e7f7 b.n 801168e <_Balloc+0x66>
|
|
801169e: bf00 nop
|
|
80116a0: 080147c5 .word 0x080147c5
|
|
80116a4: 080148e8 .word 0x080148e8
|
|
|
|
080116a8 <_Bfree>:
|
|
80116a8: b570 push {r4, r5, r6, lr}
|
|
80116aa: 69c6 ldr r6, [r0, #28]
|
|
80116ac: 4605 mov r5, r0
|
|
80116ae: 460c mov r4, r1
|
|
80116b0: b976 cbnz r6, 80116d0 <_Bfree+0x28>
|
|
80116b2: 2010 movs r0, #16
|
|
80116b4: f7ff ff02 bl 80114bc <malloc>
|
|
80116b8: 4602 mov r2, r0
|
|
80116ba: 61e8 str r0, [r5, #28]
|
|
80116bc: b920 cbnz r0, 80116c8 <_Bfree+0x20>
|
|
80116be: 4b09 ldr r3, [pc, #36] @ (80116e4 <_Bfree+0x3c>)
|
|
80116c0: 4809 ldr r0, [pc, #36] @ (80116e8 <_Bfree+0x40>)
|
|
80116c2: 218f movs r1, #143 @ 0x8f
|
|
80116c4: f7ff f83a bl 801073c <__assert_func>
|
|
80116c8: e9c0 6601 strd r6, r6, [r0, #4]
|
|
80116cc: 6006 str r6, [r0, #0]
|
|
80116ce: 60c6 str r6, [r0, #12]
|
|
80116d0: b13c cbz r4, 80116e2 <_Bfree+0x3a>
|
|
80116d2: 69eb ldr r3, [r5, #28]
|
|
80116d4: 6862 ldr r2, [r4, #4]
|
|
80116d6: 68db ldr r3, [r3, #12]
|
|
80116d8: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
80116dc: 6021 str r1, [r4, #0]
|
|
80116de: f843 4022 str.w r4, [r3, r2, lsl #2]
|
|
80116e2: bd70 pop {r4, r5, r6, pc}
|
|
80116e4: 080147c5 .word 0x080147c5
|
|
80116e8: 080148e8 .word 0x080148e8
|
|
|
|
080116ec <__multadd>:
|
|
80116ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
80116f0: 690d ldr r5, [r1, #16]
|
|
80116f2: 4607 mov r7, r0
|
|
80116f4: 460c mov r4, r1
|
|
80116f6: 461e mov r6, r3
|
|
80116f8: f101 0c14 add.w ip, r1, #20
|
|
80116fc: 2000 movs r0, #0
|
|
80116fe: f8dc 3000 ldr.w r3, [ip]
|
|
8011702: b299 uxth r1, r3
|
|
8011704: fb02 6101 mla r1, r2, r1, r6
|
|
8011708: 0c1e lsrs r6, r3, #16
|
|
801170a: 0c0b lsrs r3, r1, #16
|
|
801170c: fb02 3306 mla r3, r2, r6, r3
|
|
8011710: b289 uxth r1, r1
|
|
8011712: 3001 adds r0, #1
|
|
8011714: eb01 4103 add.w r1, r1, r3, lsl #16
|
|
8011718: 4285 cmp r5, r0
|
|
801171a: f84c 1b04 str.w r1, [ip], #4
|
|
801171e: ea4f 4613 mov.w r6, r3, lsr #16
|
|
8011722: dcec bgt.n 80116fe <__multadd+0x12>
|
|
8011724: b30e cbz r6, 801176a <__multadd+0x7e>
|
|
8011726: 68a3 ldr r3, [r4, #8]
|
|
8011728: 42ab cmp r3, r5
|
|
801172a: dc19 bgt.n 8011760 <__multadd+0x74>
|
|
801172c: 6861 ldr r1, [r4, #4]
|
|
801172e: 4638 mov r0, r7
|
|
8011730: 3101 adds r1, #1
|
|
8011732: f7ff ff79 bl 8011628 <_Balloc>
|
|
8011736: 4680 mov r8, r0
|
|
8011738: b928 cbnz r0, 8011746 <__multadd+0x5a>
|
|
801173a: 4602 mov r2, r0
|
|
801173c: 4b0c ldr r3, [pc, #48] @ (8011770 <__multadd+0x84>)
|
|
801173e: 480d ldr r0, [pc, #52] @ (8011774 <__multadd+0x88>)
|
|
8011740: 21ba movs r1, #186 @ 0xba
|
|
8011742: f7fe fffb bl 801073c <__assert_func>
|
|
8011746: 6922 ldr r2, [r4, #16]
|
|
8011748: 3202 adds r2, #2
|
|
801174a: f104 010c add.w r1, r4, #12
|
|
801174e: 0092 lsls r2, r2, #2
|
|
8011750: 300c adds r0, #12
|
|
8011752: f7fe ffde bl 8010712 <memcpy>
|
|
8011756: 4621 mov r1, r4
|
|
8011758: 4638 mov r0, r7
|
|
801175a: f7ff ffa5 bl 80116a8 <_Bfree>
|
|
801175e: 4644 mov r4, r8
|
|
8011760: eb04 0385 add.w r3, r4, r5, lsl #2
|
|
8011764: 3501 adds r5, #1
|
|
8011766: 615e str r6, [r3, #20]
|
|
8011768: 6125 str r5, [r4, #16]
|
|
801176a: 4620 mov r0, r4
|
|
801176c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
8011770: 080148d7 .word 0x080148d7
|
|
8011774: 080148e8 .word 0x080148e8
|
|
|
|
08011778 <__s2b>:
|
|
8011778: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
801177c: 460c mov r4, r1
|
|
801177e: 4615 mov r5, r2
|
|
8011780: 461f mov r7, r3
|
|
8011782: 2209 movs r2, #9
|
|
8011784: 3308 adds r3, #8
|
|
8011786: 4606 mov r6, r0
|
|
8011788: fb93 f3f2 sdiv r3, r3, r2
|
|
801178c: 2100 movs r1, #0
|
|
801178e: 2201 movs r2, #1
|
|
8011790: 429a cmp r2, r3
|
|
8011792: db09 blt.n 80117a8 <__s2b+0x30>
|
|
8011794: 4630 mov r0, r6
|
|
8011796: f7ff ff47 bl 8011628 <_Balloc>
|
|
801179a: b940 cbnz r0, 80117ae <__s2b+0x36>
|
|
801179c: 4602 mov r2, r0
|
|
801179e: 4b19 ldr r3, [pc, #100] @ (8011804 <__s2b+0x8c>)
|
|
80117a0: 4819 ldr r0, [pc, #100] @ (8011808 <__s2b+0x90>)
|
|
80117a2: 21d3 movs r1, #211 @ 0xd3
|
|
80117a4: f7fe ffca bl 801073c <__assert_func>
|
|
80117a8: 0052 lsls r2, r2, #1
|
|
80117aa: 3101 adds r1, #1
|
|
80117ac: e7f0 b.n 8011790 <__s2b+0x18>
|
|
80117ae: 9b08 ldr r3, [sp, #32]
|
|
80117b0: 6143 str r3, [r0, #20]
|
|
80117b2: 2d09 cmp r5, #9
|
|
80117b4: f04f 0301 mov.w r3, #1
|
|
80117b8: 6103 str r3, [r0, #16]
|
|
80117ba: dd16 ble.n 80117ea <__s2b+0x72>
|
|
80117bc: f104 0909 add.w r9, r4, #9
|
|
80117c0: 46c8 mov r8, r9
|
|
80117c2: 442c add r4, r5
|
|
80117c4: f818 3b01 ldrb.w r3, [r8], #1
|
|
80117c8: 4601 mov r1, r0
|
|
80117ca: 3b30 subs r3, #48 @ 0x30
|
|
80117cc: 220a movs r2, #10
|
|
80117ce: 4630 mov r0, r6
|
|
80117d0: f7ff ff8c bl 80116ec <__multadd>
|
|
80117d4: 45a0 cmp r8, r4
|
|
80117d6: d1f5 bne.n 80117c4 <__s2b+0x4c>
|
|
80117d8: f1a5 0408 sub.w r4, r5, #8
|
|
80117dc: 444c add r4, r9
|
|
80117de: 1b2d subs r5, r5, r4
|
|
80117e0: 1963 adds r3, r4, r5
|
|
80117e2: 42bb cmp r3, r7
|
|
80117e4: db04 blt.n 80117f0 <__s2b+0x78>
|
|
80117e6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
80117ea: 340a adds r4, #10
|
|
80117ec: 2509 movs r5, #9
|
|
80117ee: e7f6 b.n 80117de <__s2b+0x66>
|
|
80117f0: f814 3b01 ldrb.w r3, [r4], #1
|
|
80117f4: 4601 mov r1, r0
|
|
80117f6: 3b30 subs r3, #48 @ 0x30
|
|
80117f8: 220a movs r2, #10
|
|
80117fa: 4630 mov r0, r6
|
|
80117fc: f7ff ff76 bl 80116ec <__multadd>
|
|
8011800: e7ee b.n 80117e0 <__s2b+0x68>
|
|
8011802: bf00 nop
|
|
8011804: 080148d7 .word 0x080148d7
|
|
8011808: 080148e8 .word 0x080148e8
|
|
|
|
0801180c <__hi0bits>:
|
|
801180c: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
|
|
8011810: 4603 mov r3, r0
|
|
8011812: bf36 itet cc
|
|
8011814: 0403 lslcc r3, r0, #16
|
|
8011816: 2000 movcs r0, #0
|
|
8011818: 2010 movcc r0, #16
|
|
801181a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
801181e: bf3c itt cc
|
|
8011820: 021b lslcc r3, r3, #8
|
|
8011822: 3008 addcc r0, #8
|
|
8011824: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8011828: bf3c itt cc
|
|
801182a: 011b lslcc r3, r3, #4
|
|
801182c: 3004 addcc r0, #4
|
|
801182e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8011832: bf3c itt cc
|
|
8011834: 009b lslcc r3, r3, #2
|
|
8011836: 3002 addcc r0, #2
|
|
8011838: 2b00 cmp r3, #0
|
|
801183a: db05 blt.n 8011848 <__hi0bits+0x3c>
|
|
801183c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
|
|
8011840: f100 0001 add.w r0, r0, #1
|
|
8011844: bf08 it eq
|
|
8011846: 2020 moveq r0, #32
|
|
8011848: 4770 bx lr
|
|
|
|
0801184a <__lo0bits>:
|
|
801184a: 6803 ldr r3, [r0, #0]
|
|
801184c: 4602 mov r2, r0
|
|
801184e: f013 0007 ands.w r0, r3, #7
|
|
8011852: d00b beq.n 801186c <__lo0bits+0x22>
|
|
8011854: 07d9 lsls r1, r3, #31
|
|
8011856: d421 bmi.n 801189c <__lo0bits+0x52>
|
|
8011858: 0798 lsls r0, r3, #30
|
|
801185a: bf49 itett mi
|
|
801185c: 085b lsrmi r3, r3, #1
|
|
801185e: 089b lsrpl r3, r3, #2
|
|
8011860: 2001 movmi r0, #1
|
|
8011862: 6013 strmi r3, [r2, #0]
|
|
8011864: bf5c itt pl
|
|
8011866: 6013 strpl r3, [r2, #0]
|
|
8011868: 2002 movpl r0, #2
|
|
801186a: 4770 bx lr
|
|
801186c: b299 uxth r1, r3
|
|
801186e: b909 cbnz r1, 8011874 <__lo0bits+0x2a>
|
|
8011870: 0c1b lsrs r3, r3, #16
|
|
8011872: 2010 movs r0, #16
|
|
8011874: b2d9 uxtb r1, r3
|
|
8011876: b909 cbnz r1, 801187c <__lo0bits+0x32>
|
|
8011878: 3008 adds r0, #8
|
|
801187a: 0a1b lsrs r3, r3, #8
|
|
801187c: 0719 lsls r1, r3, #28
|
|
801187e: bf04 itt eq
|
|
8011880: 091b lsreq r3, r3, #4
|
|
8011882: 3004 addeq r0, #4
|
|
8011884: 0799 lsls r1, r3, #30
|
|
8011886: bf04 itt eq
|
|
8011888: 089b lsreq r3, r3, #2
|
|
801188a: 3002 addeq r0, #2
|
|
801188c: 07d9 lsls r1, r3, #31
|
|
801188e: d403 bmi.n 8011898 <__lo0bits+0x4e>
|
|
8011890: 085b lsrs r3, r3, #1
|
|
8011892: f100 0001 add.w r0, r0, #1
|
|
8011896: d003 beq.n 80118a0 <__lo0bits+0x56>
|
|
8011898: 6013 str r3, [r2, #0]
|
|
801189a: 4770 bx lr
|
|
801189c: 2000 movs r0, #0
|
|
801189e: 4770 bx lr
|
|
80118a0: 2020 movs r0, #32
|
|
80118a2: 4770 bx lr
|
|
|
|
080118a4 <__i2b>:
|
|
80118a4: b510 push {r4, lr}
|
|
80118a6: 460c mov r4, r1
|
|
80118a8: 2101 movs r1, #1
|
|
80118aa: f7ff febd bl 8011628 <_Balloc>
|
|
80118ae: 4602 mov r2, r0
|
|
80118b0: b928 cbnz r0, 80118be <__i2b+0x1a>
|
|
80118b2: 4b05 ldr r3, [pc, #20] @ (80118c8 <__i2b+0x24>)
|
|
80118b4: 4805 ldr r0, [pc, #20] @ (80118cc <__i2b+0x28>)
|
|
80118b6: f240 1145 movw r1, #325 @ 0x145
|
|
80118ba: f7fe ff3f bl 801073c <__assert_func>
|
|
80118be: 2301 movs r3, #1
|
|
80118c0: 6144 str r4, [r0, #20]
|
|
80118c2: 6103 str r3, [r0, #16]
|
|
80118c4: bd10 pop {r4, pc}
|
|
80118c6: bf00 nop
|
|
80118c8: 080148d7 .word 0x080148d7
|
|
80118cc: 080148e8 .word 0x080148e8
|
|
|
|
080118d0 <__multiply>:
|
|
80118d0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80118d4: 4617 mov r7, r2
|
|
80118d6: 690a ldr r2, [r1, #16]
|
|
80118d8: 693b ldr r3, [r7, #16]
|
|
80118da: 429a cmp r2, r3
|
|
80118dc: bfa8 it ge
|
|
80118de: 463b movge r3, r7
|
|
80118e0: 4689 mov r9, r1
|
|
80118e2: bfa4 itt ge
|
|
80118e4: 460f movge r7, r1
|
|
80118e6: 4699 movge r9, r3
|
|
80118e8: 693d ldr r5, [r7, #16]
|
|
80118ea: f8d9 a010 ldr.w sl, [r9, #16]
|
|
80118ee: 68bb ldr r3, [r7, #8]
|
|
80118f0: 6879 ldr r1, [r7, #4]
|
|
80118f2: eb05 060a add.w r6, r5, sl
|
|
80118f6: 42b3 cmp r3, r6
|
|
80118f8: b085 sub sp, #20
|
|
80118fa: bfb8 it lt
|
|
80118fc: 3101 addlt r1, #1
|
|
80118fe: f7ff fe93 bl 8011628 <_Balloc>
|
|
8011902: b930 cbnz r0, 8011912 <__multiply+0x42>
|
|
8011904: 4602 mov r2, r0
|
|
8011906: 4b41 ldr r3, [pc, #260] @ (8011a0c <__multiply+0x13c>)
|
|
8011908: 4841 ldr r0, [pc, #260] @ (8011a10 <__multiply+0x140>)
|
|
801190a: f44f 71b1 mov.w r1, #354 @ 0x162
|
|
801190e: f7fe ff15 bl 801073c <__assert_func>
|
|
8011912: f100 0414 add.w r4, r0, #20
|
|
8011916: eb04 0e86 add.w lr, r4, r6, lsl #2
|
|
801191a: 4623 mov r3, r4
|
|
801191c: 2200 movs r2, #0
|
|
801191e: 4573 cmp r3, lr
|
|
8011920: d320 bcc.n 8011964 <__multiply+0x94>
|
|
8011922: f107 0814 add.w r8, r7, #20
|
|
8011926: f109 0114 add.w r1, r9, #20
|
|
801192a: eb08 0585 add.w r5, r8, r5, lsl #2
|
|
801192e: eb01 038a add.w r3, r1, sl, lsl #2
|
|
8011932: 9302 str r3, [sp, #8]
|
|
8011934: 1beb subs r3, r5, r7
|
|
8011936: 3b15 subs r3, #21
|
|
8011938: f023 0303 bic.w r3, r3, #3
|
|
801193c: 3304 adds r3, #4
|
|
801193e: 3715 adds r7, #21
|
|
8011940: 42bd cmp r5, r7
|
|
8011942: bf38 it cc
|
|
8011944: 2304 movcc r3, #4
|
|
8011946: 9301 str r3, [sp, #4]
|
|
8011948: 9b02 ldr r3, [sp, #8]
|
|
801194a: 9103 str r1, [sp, #12]
|
|
801194c: 428b cmp r3, r1
|
|
801194e: d80c bhi.n 801196a <__multiply+0x9a>
|
|
8011950: 2e00 cmp r6, #0
|
|
8011952: dd03 ble.n 801195c <__multiply+0x8c>
|
|
8011954: f85e 3d04 ldr.w r3, [lr, #-4]!
|
|
8011958: 2b00 cmp r3, #0
|
|
801195a: d055 beq.n 8011a08 <__multiply+0x138>
|
|
801195c: 6106 str r6, [r0, #16]
|
|
801195e: b005 add sp, #20
|
|
8011960: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8011964: f843 2b04 str.w r2, [r3], #4
|
|
8011968: e7d9 b.n 801191e <__multiply+0x4e>
|
|
801196a: f8b1 a000 ldrh.w sl, [r1]
|
|
801196e: f1ba 0f00 cmp.w sl, #0
|
|
8011972: d01f beq.n 80119b4 <__multiply+0xe4>
|
|
8011974: 46c4 mov ip, r8
|
|
8011976: 46a1 mov r9, r4
|
|
8011978: 2700 movs r7, #0
|
|
801197a: f85c 2b04 ldr.w r2, [ip], #4
|
|
801197e: f8d9 3000 ldr.w r3, [r9]
|
|
8011982: fa1f fb82 uxth.w fp, r2
|
|
8011986: b29b uxth r3, r3
|
|
8011988: fb0a 330b mla r3, sl, fp, r3
|
|
801198c: 443b add r3, r7
|
|
801198e: f8d9 7000 ldr.w r7, [r9]
|
|
8011992: 0c12 lsrs r2, r2, #16
|
|
8011994: 0c3f lsrs r7, r7, #16
|
|
8011996: fb0a 7202 mla r2, sl, r2, r7
|
|
801199a: eb02 4213 add.w r2, r2, r3, lsr #16
|
|
801199e: b29b uxth r3, r3
|
|
80119a0: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
80119a4: 4565 cmp r5, ip
|
|
80119a6: f849 3b04 str.w r3, [r9], #4
|
|
80119aa: ea4f 4712 mov.w r7, r2, lsr #16
|
|
80119ae: d8e4 bhi.n 801197a <__multiply+0xaa>
|
|
80119b0: 9b01 ldr r3, [sp, #4]
|
|
80119b2: 50e7 str r7, [r4, r3]
|
|
80119b4: 9b03 ldr r3, [sp, #12]
|
|
80119b6: f8b3 9002 ldrh.w r9, [r3, #2]
|
|
80119ba: 3104 adds r1, #4
|
|
80119bc: f1b9 0f00 cmp.w r9, #0
|
|
80119c0: d020 beq.n 8011a04 <__multiply+0x134>
|
|
80119c2: 6823 ldr r3, [r4, #0]
|
|
80119c4: 4647 mov r7, r8
|
|
80119c6: 46a4 mov ip, r4
|
|
80119c8: f04f 0a00 mov.w sl, #0
|
|
80119cc: f8b7 b000 ldrh.w fp, [r7]
|
|
80119d0: f8bc 2002 ldrh.w r2, [ip, #2]
|
|
80119d4: fb09 220b mla r2, r9, fp, r2
|
|
80119d8: 4452 add r2, sl
|
|
80119da: b29b uxth r3, r3
|
|
80119dc: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
80119e0: f84c 3b04 str.w r3, [ip], #4
|
|
80119e4: f857 3b04 ldr.w r3, [r7], #4
|
|
80119e8: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
80119ec: f8bc 3000 ldrh.w r3, [ip]
|
|
80119f0: fb09 330a mla r3, r9, sl, r3
|
|
80119f4: eb03 4312 add.w r3, r3, r2, lsr #16
|
|
80119f8: 42bd cmp r5, r7
|
|
80119fa: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
80119fe: d8e5 bhi.n 80119cc <__multiply+0xfc>
|
|
8011a00: 9a01 ldr r2, [sp, #4]
|
|
8011a02: 50a3 str r3, [r4, r2]
|
|
8011a04: 3404 adds r4, #4
|
|
8011a06: e79f b.n 8011948 <__multiply+0x78>
|
|
8011a08: 3e01 subs r6, #1
|
|
8011a0a: e7a1 b.n 8011950 <__multiply+0x80>
|
|
8011a0c: 080148d7 .word 0x080148d7
|
|
8011a10: 080148e8 .word 0x080148e8
|
|
|
|
08011a14 <__pow5mult>:
|
|
8011a14: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
8011a18: 4615 mov r5, r2
|
|
8011a1a: f012 0203 ands.w r2, r2, #3
|
|
8011a1e: 4607 mov r7, r0
|
|
8011a20: 460e mov r6, r1
|
|
8011a22: d007 beq.n 8011a34 <__pow5mult+0x20>
|
|
8011a24: 4c25 ldr r4, [pc, #148] @ (8011abc <__pow5mult+0xa8>)
|
|
8011a26: 3a01 subs r2, #1
|
|
8011a28: 2300 movs r3, #0
|
|
8011a2a: f854 2022 ldr.w r2, [r4, r2, lsl #2]
|
|
8011a2e: f7ff fe5d bl 80116ec <__multadd>
|
|
8011a32: 4606 mov r6, r0
|
|
8011a34: 10ad asrs r5, r5, #2
|
|
8011a36: d03d beq.n 8011ab4 <__pow5mult+0xa0>
|
|
8011a38: 69fc ldr r4, [r7, #28]
|
|
8011a3a: b97c cbnz r4, 8011a5c <__pow5mult+0x48>
|
|
8011a3c: 2010 movs r0, #16
|
|
8011a3e: f7ff fd3d bl 80114bc <malloc>
|
|
8011a42: 4602 mov r2, r0
|
|
8011a44: 61f8 str r0, [r7, #28]
|
|
8011a46: b928 cbnz r0, 8011a54 <__pow5mult+0x40>
|
|
8011a48: 4b1d ldr r3, [pc, #116] @ (8011ac0 <__pow5mult+0xac>)
|
|
8011a4a: 481e ldr r0, [pc, #120] @ (8011ac4 <__pow5mult+0xb0>)
|
|
8011a4c: f240 11b3 movw r1, #435 @ 0x1b3
|
|
8011a50: f7fe fe74 bl 801073c <__assert_func>
|
|
8011a54: e9c0 4401 strd r4, r4, [r0, #4]
|
|
8011a58: 6004 str r4, [r0, #0]
|
|
8011a5a: 60c4 str r4, [r0, #12]
|
|
8011a5c: f8d7 801c ldr.w r8, [r7, #28]
|
|
8011a60: f8d8 4008 ldr.w r4, [r8, #8]
|
|
8011a64: b94c cbnz r4, 8011a7a <__pow5mult+0x66>
|
|
8011a66: f240 2171 movw r1, #625 @ 0x271
|
|
8011a6a: 4638 mov r0, r7
|
|
8011a6c: f7ff ff1a bl 80118a4 <__i2b>
|
|
8011a70: 2300 movs r3, #0
|
|
8011a72: f8c8 0008 str.w r0, [r8, #8]
|
|
8011a76: 4604 mov r4, r0
|
|
8011a78: 6003 str r3, [r0, #0]
|
|
8011a7a: f04f 0900 mov.w r9, #0
|
|
8011a7e: 07eb lsls r3, r5, #31
|
|
8011a80: d50a bpl.n 8011a98 <__pow5mult+0x84>
|
|
8011a82: 4631 mov r1, r6
|
|
8011a84: 4622 mov r2, r4
|
|
8011a86: 4638 mov r0, r7
|
|
8011a88: f7ff ff22 bl 80118d0 <__multiply>
|
|
8011a8c: 4631 mov r1, r6
|
|
8011a8e: 4680 mov r8, r0
|
|
8011a90: 4638 mov r0, r7
|
|
8011a92: f7ff fe09 bl 80116a8 <_Bfree>
|
|
8011a96: 4646 mov r6, r8
|
|
8011a98: 106d asrs r5, r5, #1
|
|
8011a9a: d00b beq.n 8011ab4 <__pow5mult+0xa0>
|
|
8011a9c: 6820 ldr r0, [r4, #0]
|
|
8011a9e: b938 cbnz r0, 8011ab0 <__pow5mult+0x9c>
|
|
8011aa0: 4622 mov r2, r4
|
|
8011aa2: 4621 mov r1, r4
|
|
8011aa4: 4638 mov r0, r7
|
|
8011aa6: f7ff ff13 bl 80118d0 <__multiply>
|
|
8011aaa: 6020 str r0, [r4, #0]
|
|
8011aac: f8c0 9000 str.w r9, [r0]
|
|
8011ab0: 4604 mov r4, r0
|
|
8011ab2: e7e4 b.n 8011a7e <__pow5mult+0x6a>
|
|
8011ab4: 4630 mov r0, r6
|
|
8011ab6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
8011aba: bf00 nop
|
|
8011abc: 080149bc .word 0x080149bc
|
|
8011ac0: 080147c5 .word 0x080147c5
|
|
8011ac4: 080148e8 .word 0x080148e8
|
|
|
|
08011ac8 <__lshift>:
|
|
8011ac8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8011acc: 460c mov r4, r1
|
|
8011ace: 6849 ldr r1, [r1, #4]
|
|
8011ad0: 6923 ldr r3, [r4, #16]
|
|
8011ad2: eb03 1862 add.w r8, r3, r2, asr #5
|
|
8011ad6: 68a3 ldr r3, [r4, #8]
|
|
8011ad8: 4607 mov r7, r0
|
|
8011ada: 4691 mov r9, r2
|
|
8011adc: ea4f 1a62 mov.w sl, r2, asr #5
|
|
8011ae0: f108 0601 add.w r6, r8, #1
|
|
8011ae4: 42b3 cmp r3, r6
|
|
8011ae6: db0b blt.n 8011b00 <__lshift+0x38>
|
|
8011ae8: 4638 mov r0, r7
|
|
8011aea: f7ff fd9d bl 8011628 <_Balloc>
|
|
8011aee: 4605 mov r5, r0
|
|
8011af0: b948 cbnz r0, 8011b06 <__lshift+0x3e>
|
|
8011af2: 4602 mov r2, r0
|
|
8011af4: 4b28 ldr r3, [pc, #160] @ (8011b98 <__lshift+0xd0>)
|
|
8011af6: 4829 ldr r0, [pc, #164] @ (8011b9c <__lshift+0xd4>)
|
|
8011af8: f44f 71ef mov.w r1, #478 @ 0x1de
|
|
8011afc: f7fe fe1e bl 801073c <__assert_func>
|
|
8011b00: 3101 adds r1, #1
|
|
8011b02: 005b lsls r3, r3, #1
|
|
8011b04: e7ee b.n 8011ae4 <__lshift+0x1c>
|
|
8011b06: 2300 movs r3, #0
|
|
8011b08: f100 0114 add.w r1, r0, #20
|
|
8011b0c: f100 0210 add.w r2, r0, #16
|
|
8011b10: 4618 mov r0, r3
|
|
8011b12: 4553 cmp r3, sl
|
|
8011b14: db33 blt.n 8011b7e <__lshift+0xb6>
|
|
8011b16: 6920 ldr r0, [r4, #16]
|
|
8011b18: ea2a 7aea bic.w sl, sl, sl, asr #31
|
|
8011b1c: f104 0314 add.w r3, r4, #20
|
|
8011b20: f019 091f ands.w r9, r9, #31
|
|
8011b24: eb01 018a add.w r1, r1, sl, lsl #2
|
|
8011b28: eb03 0c80 add.w ip, r3, r0, lsl #2
|
|
8011b2c: d02b beq.n 8011b86 <__lshift+0xbe>
|
|
8011b2e: f1c9 0e20 rsb lr, r9, #32
|
|
8011b32: 468a mov sl, r1
|
|
8011b34: 2200 movs r2, #0
|
|
8011b36: 6818 ldr r0, [r3, #0]
|
|
8011b38: fa00 f009 lsl.w r0, r0, r9
|
|
8011b3c: 4310 orrs r0, r2
|
|
8011b3e: f84a 0b04 str.w r0, [sl], #4
|
|
8011b42: f853 2b04 ldr.w r2, [r3], #4
|
|
8011b46: 459c cmp ip, r3
|
|
8011b48: fa22 f20e lsr.w r2, r2, lr
|
|
8011b4c: d8f3 bhi.n 8011b36 <__lshift+0x6e>
|
|
8011b4e: ebac 0304 sub.w r3, ip, r4
|
|
8011b52: 3b15 subs r3, #21
|
|
8011b54: f023 0303 bic.w r3, r3, #3
|
|
8011b58: 3304 adds r3, #4
|
|
8011b5a: f104 0015 add.w r0, r4, #21
|
|
8011b5e: 4560 cmp r0, ip
|
|
8011b60: bf88 it hi
|
|
8011b62: 2304 movhi r3, #4
|
|
8011b64: 50ca str r2, [r1, r3]
|
|
8011b66: b10a cbz r2, 8011b6c <__lshift+0xa4>
|
|
8011b68: f108 0602 add.w r6, r8, #2
|
|
8011b6c: 3e01 subs r6, #1
|
|
8011b6e: 4638 mov r0, r7
|
|
8011b70: 612e str r6, [r5, #16]
|
|
8011b72: 4621 mov r1, r4
|
|
8011b74: f7ff fd98 bl 80116a8 <_Bfree>
|
|
8011b78: 4628 mov r0, r5
|
|
8011b7a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8011b7e: f842 0f04 str.w r0, [r2, #4]!
|
|
8011b82: 3301 adds r3, #1
|
|
8011b84: e7c5 b.n 8011b12 <__lshift+0x4a>
|
|
8011b86: 3904 subs r1, #4
|
|
8011b88: f853 2b04 ldr.w r2, [r3], #4
|
|
8011b8c: f841 2f04 str.w r2, [r1, #4]!
|
|
8011b90: 459c cmp ip, r3
|
|
8011b92: d8f9 bhi.n 8011b88 <__lshift+0xc0>
|
|
8011b94: e7ea b.n 8011b6c <__lshift+0xa4>
|
|
8011b96: bf00 nop
|
|
8011b98: 080148d7 .word 0x080148d7
|
|
8011b9c: 080148e8 .word 0x080148e8
|
|
|
|
08011ba0 <__mcmp>:
|
|
8011ba0: 690a ldr r2, [r1, #16]
|
|
8011ba2: 4603 mov r3, r0
|
|
8011ba4: 6900 ldr r0, [r0, #16]
|
|
8011ba6: 1a80 subs r0, r0, r2
|
|
8011ba8: b530 push {r4, r5, lr}
|
|
8011baa: d10e bne.n 8011bca <__mcmp+0x2a>
|
|
8011bac: 3314 adds r3, #20
|
|
8011bae: 3114 adds r1, #20
|
|
8011bb0: eb03 0482 add.w r4, r3, r2, lsl #2
|
|
8011bb4: eb01 0182 add.w r1, r1, r2, lsl #2
|
|
8011bb8: f854 5d04 ldr.w r5, [r4, #-4]!
|
|
8011bbc: f851 2d04 ldr.w r2, [r1, #-4]!
|
|
8011bc0: 4295 cmp r5, r2
|
|
8011bc2: d003 beq.n 8011bcc <__mcmp+0x2c>
|
|
8011bc4: d205 bcs.n 8011bd2 <__mcmp+0x32>
|
|
8011bc6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8011bca: bd30 pop {r4, r5, pc}
|
|
8011bcc: 42a3 cmp r3, r4
|
|
8011bce: d3f3 bcc.n 8011bb8 <__mcmp+0x18>
|
|
8011bd0: e7fb b.n 8011bca <__mcmp+0x2a>
|
|
8011bd2: 2001 movs r0, #1
|
|
8011bd4: e7f9 b.n 8011bca <__mcmp+0x2a>
|
|
...
|
|
|
|
08011bd8 <__mdiff>:
|
|
8011bd8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8011bdc: 4689 mov r9, r1
|
|
8011bde: 4606 mov r6, r0
|
|
8011be0: 4611 mov r1, r2
|
|
8011be2: 4648 mov r0, r9
|
|
8011be4: 4614 mov r4, r2
|
|
8011be6: f7ff ffdb bl 8011ba0 <__mcmp>
|
|
8011bea: 1e05 subs r5, r0, #0
|
|
8011bec: d112 bne.n 8011c14 <__mdiff+0x3c>
|
|
8011bee: 4629 mov r1, r5
|
|
8011bf0: 4630 mov r0, r6
|
|
8011bf2: f7ff fd19 bl 8011628 <_Balloc>
|
|
8011bf6: 4602 mov r2, r0
|
|
8011bf8: b928 cbnz r0, 8011c06 <__mdiff+0x2e>
|
|
8011bfa: 4b3f ldr r3, [pc, #252] @ (8011cf8 <__mdiff+0x120>)
|
|
8011bfc: f240 2137 movw r1, #567 @ 0x237
|
|
8011c00: 483e ldr r0, [pc, #248] @ (8011cfc <__mdiff+0x124>)
|
|
8011c02: f7fe fd9b bl 801073c <__assert_func>
|
|
8011c06: 2301 movs r3, #1
|
|
8011c08: e9c0 3504 strd r3, r5, [r0, #16]
|
|
8011c0c: 4610 mov r0, r2
|
|
8011c0e: b003 add sp, #12
|
|
8011c10: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8011c14: bfbc itt lt
|
|
8011c16: 464b movlt r3, r9
|
|
8011c18: 46a1 movlt r9, r4
|
|
8011c1a: 4630 mov r0, r6
|
|
8011c1c: f8d9 1004 ldr.w r1, [r9, #4]
|
|
8011c20: bfba itte lt
|
|
8011c22: 461c movlt r4, r3
|
|
8011c24: 2501 movlt r5, #1
|
|
8011c26: 2500 movge r5, #0
|
|
8011c28: f7ff fcfe bl 8011628 <_Balloc>
|
|
8011c2c: 4602 mov r2, r0
|
|
8011c2e: b918 cbnz r0, 8011c38 <__mdiff+0x60>
|
|
8011c30: 4b31 ldr r3, [pc, #196] @ (8011cf8 <__mdiff+0x120>)
|
|
8011c32: f240 2145 movw r1, #581 @ 0x245
|
|
8011c36: e7e3 b.n 8011c00 <__mdiff+0x28>
|
|
8011c38: f8d9 7010 ldr.w r7, [r9, #16]
|
|
8011c3c: 6926 ldr r6, [r4, #16]
|
|
8011c3e: 60c5 str r5, [r0, #12]
|
|
8011c40: f109 0310 add.w r3, r9, #16
|
|
8011c44: f109 0514 add.w r5, r9, #20
|
|
8011c48: f104 0e14 add.w lr, r4, #20
|
|
8011c4c: f100 0b14 add.w fp, r0, #20
|
|
8011c50: eb05 0887 add.w r8, r5, r7, lsl #2
|
|
8011c54: eb0e 0686 add.w r6, lr, r6, lsl #2
|
|
8011c58: 9301 str r3, [sp, #4]
|
|
8011c5a: 46d9 mov r9, fp
|
|
8011c5c: f04f 0c00 mov.w ip, #0
|
|
8011c60: 9b01 ldr r3, [sp, #4]
|
|
8011c62: f85e 0b04 ldr.w r0, [lr], #4
|
|
8011c66: f853 af04 ldr.w sl, [r3, #4]!
|
|
8011c6a: 9301 str r3, [sp, #4]
|
|
8011c6c: fa1f f38a uxth.w r3, sl
|
|
8011c70: 4619 mov r1, r3
|
|
8011c72: b283 uxth r3, r0
|
|
8011c74: 1acb subs r3, r1, r3
|
|
8011c76: 0c00 lsrs r0, r0, #16
|
|
8011c78: 4463 add r3, ip
|
|
8011c7a: ebc0 401a rsb r0, r0, sl, lsr #16
|
|
8011c7e: eb00 4023 add.w r0, r0, r3, asr #16
|
|
8011c82: b29b uxth r3, r3
|
|
8011c84: ea43 4300 orr.w r3, r3, r0, lsl #16
|
|
8011c88: 4576 cmp r6, lr
|
|
8011c8a: f849 3b04 str.w r3, [r9], #4
|
|
8011c8e: ea4f 4c20 mov.w ip, r0, asr #16
|
|
8011c92: d8e5 bhi.n 8011c60 <__mdiff+0x88>
|
|
8011c94: 1b33 subs r3, r6, r4
|
|
8011c96: 3b15 subs r3, #21
|
|
8011c98: f023 0303 bic.w r3, r3, #3
|
|
8011c9c: 3415 adds r4, #21
|
|
8011c9e: 3304 adds r3, #4
|
|
8011ca0: 42a6 cmp r6, r4
|
|
8011ca2: bf38 it cc
|
|
8011ca4: 2304 movcc r3, #4
|
|
8011ca6: 441d add r5, r3
|
|
8011ca8: 445b add r3, fp
|
|
8011caa: 461e mov r6, r3
|
|
8011cac: 462c mov r4, r5
|
|
8011cae: 4544 cmp r4, r8
|
|
8011cb0: d30e bcc.n 8011cd0 <__mdiff+0xf8>
|
|
8011cb2: f108 0103 add.w r1, r8, #3
|
|
8011cb6: 1b49 subs r1, r1, r5
|
|
8011cb8: f021 0103 bic.w r1, r1, #3
|
|
8011cbc: 3d03 subs r5, #3
|
|
8011cbe: 45a8 cmp r8, r5
|
|
8011cc0: bf38 it cc
|
|
8011cc2: 2100 movcc r1, #0
|
|
8011cc4: 440b add r3, r1
|
|
8011cc6: f853 1d04 ldr.w r1, [r3, #-4]!
|
|
8011cca: b191 cbz r1, 8011cf2 <__mdiff+0x11a>
|
|
8011ccc: 6117 str r7, [r2, #16]
|
|
8011cce: e79d b.n 8011c0c <__mdiff+0x34>
|
|
8011cd0: f854 1b04 ldr.w r1, [r4], #4
|
|
8011cd4: 46e6 mov lr, ip
|
|
8011cd6: 0c08 lsrs r0, r1, #16
|
|
8011cd8: fa1c fc81 uxtah ip, ip, r1
|
|
8011cdc: 4471 add r1, lr
|
|
8011cde: eb00 402c add.w r0, r0, ip, asr #16
|
|
8011ce2: b289 uxth r1, r1
|
|
8011ce4: ea41 4100 orr.w r1, r1, r0, lsl #16
|
|
8011ce8: f846 1b04 str.w r1, [r6], #4
|
|
8011cec: ea4f 4c20 mov.w ip, r0, asr #16
|
|
8011cf0: e7dd b.n 8011cae <__mdiff+0xd6>
|
|
8011cf2: 3f01 subs r7, #1
|
|
8011cf4: e7e7 b.n 8011cc6 <__mdiff+0xee>
|
|
8011cf6: bf00 nop
|
|
8011cf8: 080148d7 .word 0x080148d7
|
|
8011cfc: 080148e8 .word 0x080148e8
|
|
|
|
08011d00 <__ulp>:
|
|
8011d00: b082 sub sp, #8
|
|
8011d02: ed8d 0b00 vstr d0, [sp]
|
|
8011d06: 9a01 ldr r2, [sp, #4]
|
|
8011d08: 4b0f ldr r3, [pc, #60] @ (8011d48 <__ulp+0x48>)
|
|
8011d0a: 4013 ands r3, r2
|
|
8011d0c: f1a3 7350 sub.w r3, r3, #54525952 @ 0x3400000
|
|
8011d10: 2b00 cmp r3, #0
|
|
8011d12: dc08 bgt.n 8011d26 <__ulp+0x26>
|
|
8011d14: 425b negs r3, r3
|
|
8011d16: f1b3 7fa0 cmp.w r3, #20971520 @ 0x1400000
|
|
8011d1a: ea4f 5223 mov.w r2, r3, asr #20
|
|
8011d1e: da04 bge.n 8011d2a <__ulp+0x2a>
|
|
8011d20: f44f 2300 mov.w r3, #524288 @ 0x80000
|
|
8011d24: 4113 asrs r3, r2
|
|
8011d26: 2200 movs r2, #0
|
|
8011d28: e008 b.n 8011d3c <__ulp+0x3c>
|
|
8011d2a: f1a2 0314 sub.w r3, r2, #20
|
|
8011d2e: 2b1e cmp r3, #30
|
|
8011d30: bfda itte le
|
|
8011d32: f04f 4200 movle.w r2, #2147483648 @ 0x80000000
|
|
8011d36: 40da lsrle r2, r3
|
|
8011d38: 2201 movgt r2, #1
|
|
8011d3a: 2300 movs r3, #0
|
|
8011d3c: 4619 mov r1, r3
|
|
8011d3e: 4610 mov r0, r2
|
|
8011d40: ec41 0b10 vmov d0, r0, r1
|
|
8011d44: b002 add sp, #8
|
|
8011d46: 4770 bx lr
|
|
8011d48: 7ff00000 .word 0x7ff00000
|
|
|
|
08011d4c <__b2d>:
|
|
8011d4c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8011d50: 6906 ldr r6, [r0, #16]
|
|
8011d52: f100 0814 add.w r8, r0, #20
|
|
8011d56: eb08 0686 add.w r6, r8, r6, lsl #2
|
|
8011d5a: 1f37 subs r7, r6, #4
|
|
8011d5c: f856 2c04 ldr.w r2, [r6, #-4]
|
|
8011d60: 4610 mov r0, r2
|
|
8011d62: f7ff fd53 bl 801180c <__hi0bits>
|
|
8011d66: f1c0 0320 rsb r3, r0, #32
|
|
8011d6a: 280a cmp r0, #10
|
|
8011d6c: 600b str r3, [r1, #0]
|
|
8011d6e: 491b ldr r1, [pc, #108] @ (8011ddc <__b2d+0x90>)
|
|
8011d70: dc15 bgt.n 8011d9e <__b2d+0x52>
|
|
8011d72: f1c0 0c0b rsb ip, r0, #11
|
|
8011d76: fa22 f30c lsr.w r3, r2, ip
|
|
8011d7a: 45b8 cmp r8, r7
|
|
8011d7c: ea43 0501 orr.w r5, r3, r1
|
|
8011d80: bf34 ite cc
|
|
8011d82: f856 3c08 ldrcc.w r3, [r6, #-8]
|
|
8011d86: 2300 movcs r3, #0
|
|
8011d88: 3015 adds r0, #21
|
|
8011d8a: fa02 f000 lsl.w r0, r2, r0
|
|
8011d8e: fa23 f30c lsr.w r3, r3, ip
|
|
8011d92: 4303 orrs r3, r0
|
|
8011d94: 461c mov r4, r3
|
|
8011d96: ec45 4b10 vmov d0, r4, r5
|
|
8011d9a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
8011d9e: 45b8 cmp r8, r7
|
|
8011da0: bf3a itte cc
|
|
8011da2: f856 3c08 ldrcc.w r3, [r6, #-8]
|
|
8011da6: f1a6 0708 subcc.w r7, r6, #8
|
|
8011daa: 2300 movcs r3, #0
|
|
8011dac: 380b subs r0, #11
|
|
8011dae: d012 beq.n 8011dd6 <__b2d+0x8a>
|
|
8011db0: f1c0 0120 rsb r1, r0, #32
|
|
8011db4: fa23 f401 lsr.w r4, r3, r1
|
|
8011db8: 4082 lsls r2, r0
|
|
8011dba: 4322 orrs r2, r4
|
|
8011dbc: 4547 cmp r7, r8
|
|
8011dbe: f042 557f orr.w r5, r2, #1069547520 @ 0x3fc00000
|
|
8011dc2: bf8c ite hi
|
|
8011dc4: f857 2c04 ldrhi.w r2, [r7, #-4]
|
|
8011dc8: 2200 movls r2, #0
|
|
8011dca: 4083 lsls r3, r0
|
|
8011dcc: 40ca lsrs r2, r1
|
|
8011dce: f445 1540 orr.w r5, r5, #3145728 @ 0x300000
|
|
8011dd2: 4313 orrs r3, r2
|
|
8011dd4: e7de b.n 8011d94 <__b2d+0x48>
|
|
8011dd6: ea42 0501 orr.w r5, r2, r1
|
|
8011dda: e7db b.n 8011d94 <__b2d+0x48>
|
|
8011ddc: 3ff00000 .word 0x3ff00000
|
|
|
|
08011de0 <__d2b>:
|
|
8011de0: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
|
|
8011de4: 460f mov r7, r1
|
|
8011de6: 2101 movs r1, #1
|
|
8011de8: ec59 8b10 vmov r8, r9, d0
|
|
8011dec: 4616 mov r6, r2
|
|
8011dee: f7ff fc1b bl 8011628 <_Balloc>
|
|
8011df2: 4604 mov r4, r0
|
|
8011df4: b930 cbnz r0, 8011e04 <__d2b+0x24>
|
|
8011df6: 4602 mov r2, r0
|
|
8011df8: 4b23 ldr r3, [pc, #140] @ (8011e88 <__d2b+0xa8>)
|
|
8011dfa: 4824 ldr r0, [pc, #144] @ (8011e8c <__d2b+0xac>)
|
|
8011dfc: f240 310f movw r1, #783 @ 0x30f
|
|
8011e00: f7fe fc9c bl 801073c <__assert_func>
|
|
8011e04: f3c9 550a ubfx r5, r9, #20, #11
|
|
8011e08: f3c9 0313 ubfx r3, r9, #0, #20
|
|
8011e0c: b10d cbz r5, 8011e12 <__d2b+0x32>
|
|
8011e0e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8011e12: 9301 str r3, [sp, #4]
|
|
8011e14: f1b8 0300 subs.w r3, r8, #0
|
|
8011e18: d023 beq.n 8011e62 <__d2b+0x82>
|
|
8011e1a: 4668 mov r0, sp
|
|
8011e1c: 9300 str r3, [sp, #0]
|
|
8011e1e: f7ff fd14 bl 801184a <__lo0bits>
|
|
8011e22: e9dd 1200 ldrd r1, r2, [sp]
|
|
8011e26: b1d0 cbz r0, 8011e5e <__d2b+0x7e>
|
|
8011e28: f1c0 0320 rsb r3, r0, #32
|
|
8011e2c: fa02 f303 lsl.w r3, r2, r3
|
|
8011e30: 430b orrs r3, r1
|
|
8011e32: 40c2 lsrs r2, r0
|
|
8011e34: 6163 str r3, [r4, #20]
|
|
8011e36: 9201 str r2, [sp, #4]
|
|
8011e38: 9b01 ldr r3, [sp, #4]
|
|
8011e3a: 61a3 str r3, [r4, #24]
|
|
8011e3c: 2b00 cmp r3, #0
|
|
8011e3e: bf0c ite eq
|
|
8011e40: 2201 moveq r2, #1
|
|
8011e42: 2202 movne r2, #2
|
|
8011e44: 6122 str r2, [r4, #16]
|
|
8011e46: b1a5 cbz r5, 8011e72 <__d2b+0x92>
|
|
8011e48: f2a5 4533 subw r5, r5, #1075 @ 0x433
|
|
8011e4c: 4405 add r5, r0
|
|
8011e4e: 603d str r5, [r7, #0]
|
|
8011e50: f1c0 0035 rsb r0, r0, #53 @ 0x35
|
|
8011e54: 6030 str r0, [r6, #0]
|
|
8011e56: 4620 mov r0, r4
|
|
8011e58: b003 add sp, #12
|
|
8011e5a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
8011e5e: 6161 str r1, [r4, #20]
|
|
8011e60: e7ea b.n 8011e38 <__d2b+0x58>
|
|
8011e62: a801 add r0, sp, #4
|
|
8011e64: f7ff fcf1 bl 801184a <__lo0bits>
|
|
8011e68: 9b01 ldr r3, [sp, #4]
|
|
8011e6a: 6163 str r3, [r4, #20]
|
|
8011e6c: 3020 adds r0, #32
|
|
8011e6e: 2201 movs r2, #1
|
|
8011e70: e7e8 b.n 8011e44 <__d2b+0x64>
|
|
8011e72: eb04 0382 add.w r3, r4, r2, lsl #2
|
|
8011e76: f2a0 4032 subw r0, r0, #1074 @ 0x432
|
|
8011e7a: 6038 str r0, [r7, #0]
|
|
8011e7c: 6918 ldr r0, [r3, #16]
|
|
8011e7e: f7ff fcc5 bl 801180c <__hi0bits>
|
|
8011e82: ebc0 1042 rsb r0, r0, r2, lsl #5
|
|
8011e86: e7e5 b.n 8011e54 <__d2b+0x74>
|
|
8011e88: 080148d7 .word 0x080148d7
|
|
8011e8c: 080148e8 .word 0x080148e8
|
|
|
|
08011e90 <__ratio>:
|
|
8011e90: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8011e94: b085 sub sp, #20
|
|
8011e96: e9cd 1000 strd r1, r0, [sp]
|
|
8011e9a: a902 add r1, sp, #8
|
|
8011e9c: f7ff ff56 bl 8011d4c <__b2d>
|
|
8011ea0: 9800 ldr r0, [sp, #0]
|
|
8011ea2: a903 add r1, sp, #12
|
|
8011ea4: ec55 4b10 vmov r4, r5, d0
|
|
8011ea8: f7ff ff50 bl 8011d4c <__b2d>
|
|
8011eac: 9b01 ldr r3, [sp, #4]
|
|
8011eae: 6919 ldr r1, [r3, #16]
|
|
8011eb0: 9b00 ldr r3, [sp, #0]
|
|
8011eb2: 691b ldr r3, [r3, #16]
|
|
8011eb4: 1ac9 subs r1, r1, r3
|
|
8011eb6: e9dd 3202 ldrd r3, r2, [sp, #8]
|
|
8011eba: 1a9b subs r3, r3, r2
|
|
8011ebc: ec5b ab10 vmov sl, fp, d0
|
|
8011ec0: eb03 1341 add.w r3, r3, r1, lsl #5
|
|
8011ec4: 2b00 cmp r3, #0
|
|
8011ec6: bfce itee gt
|
|
8011ec8: 462a movgt r2, r5
|
|
8011eca: ebc3 3303 rsble r3, r3, r3, lsl #12
|
|
8011ece: 465a movle r2, fp
|
|
8011ed0: 462f mov r7, r5
|
|
8011ed2: 46d9 mov r9, fp
|
|
8011ed4: bfcc ite gt
|
|
8011ed6: eb02 5703 addgt.w r7, r2, r3, lsl #20
|
|
8011eda: eb02 5903 addle.w r9, r2, r3, lsl #20
|
|
8011ede: 464b mov r3, r9
|
|
8011ee0: 4652 mov r2, sl
|
|
8011ee2: 4620 mov r0, r4
|
|
8011ee4: 4639 mov r1, r7
|
|
8011ee6: f7ee fcb1 bl 800084c <__aeabi_ddiv>
|
|
8011eea: ec41 0b10 vmov d0, r0, r1
|
|
8011eee: b005 add sp, #20
|
|
8011ef0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
|
08011ef4 <__copybits>:
|
|
8011ef4: 3901 subs r1, #1
|
|
8011ef6: b570 push {r4, r5, r6, lr}
|
|
8011ef8: 1149 asrs r1, r1, #5
|
|
8011efa: 6914 ldr r4, [r2, #16]
|
|
8011efc: 3101 adds r1, #1
|
|
8011efe: f102 0314 add.w r3, r2, #20
|
|
8011f02: eb00 0181 add.w r1, r0, r1, lsl #2
|
|
8011f06: eb03 0484 add.w r4, r3, r4, lsl #2
|
|
8011f0a: 1f05 subs r5, r0, #4
|
|
8011f0c: 42a3 cmp r3, r4
|
|
8011f0e: d30c bcc.n 8011f2a <__copybits+0x36>
|
|
8011f10: 1aa3 subs r3, r4, r2
|
|
8011f12: 3b11 subs r3, #17
|
|
8011f14: f023 0303 bic.w r3, r3, #3
|
|
8011f18: 3211 adds r2, #17
|
|
8011f1a: 42a2 cmp r2, r4
|
|
8011f1c: bf88 it hi
|
|
8011f1e: 2300 movhi r3, #0
|
|
8011f20: 4418 add r0, r3
|
|
8011f22: 2300 movs r3, #0
|
|
8011f24: 4288 cmp r0, r1
|
|
8011f26: d305 bcc.n 8011f34 <__copybits+0x40>
|
|
8011f28: bd70 pop {r4, r5, r6, pc}
|
|
8011f2a: f853 6b04 ldr.w r6, [r3], #4
|
|
8011f2e: f845 6f04 str.w r6, [r5, #4]!
|
|
8011f32: e7eb b.n 8011f0c <__copybits+0x18>
|
|
8011f34: f840 3b04 str.w r3, [r0], #4
|
|
8011f38: e7f4 b.n 8011f24 <__copybits+0x30>
|
|
|
|
08011f3a <__any_on>:
|
|
8011f3a: f100 0214 add.w r2, r0, #20
|
|
8011f3e: 6900 ldr r0, [r0, #16]
|
|
8011f40: 114b asrs r3, r1, #5
|
|
8011f42: 4298 cmp r0, r3
|
|
8011f44: b510 push {r4, lr}
|
|
8011f46: db11 blt.n 8011f6c <__any_on+0x32>
|
|
8011f48: dd0a ble.n 8011f60 <__any_on+0x26>
|
|
8011f4a: f011 011f ands.w r1, r1, #31
|
|
8011f4e: d007 beq.n 8011f60 <__any_on+0x26>
|
|
8011f50: f852 4023 ldr.w r4, [r2, r3, lsl #2]
|
|
8011f54: fa24 f001 lsr.w r0, r4, r1
|
|
8011f58: fa00 f101 lsl.w r1, r0, r1
|
|
8011f5c: 428c cmp r4, r1
|
|
8011f5e: d10b bne.n 8011f78 <__any_on+0x3e>
|
|
8011f60: eb02 0383 add.w r3, r2, r3, lsl #2
|
|
8011f64: 4293 cmp r3, r2
|
|
8011f66: d803 bhi.n 8011f70 <__any_on+0x36>
|
|
8011f68: 2000 movs r0, #0
|
|
8011f6a: bd10 pop {r4, pc}
|
|
8011f6c: 4603 mov r3, r0
|
|
8011f6e: e7f7 b.n 8011f60 <__any_on+0x26>
|
|
8011f70: f853 1d04 ldr.w r1, [r3, #-4]!
|
|
8011f74: 2900 cmp r1, #0
|
|
8011f76: d0f5 beq.n 8011f64 <__any_on+0x2a>
|
|
8011f78: 2001 movs r0, #1
|
|
8011f7a: e7f6 b.n 8011f6a <__any_on+0x30>
|
|
|
|
08011f7c <sulp>:
|
|
8011f7c: b570 push {r4, r5, r6, lr}
|
|
8011f7e: 4604 mov r4, r0
|
|
8011f80: 460d mov r5, r1
|
|
8011f82: ec45 4b10 vmov d0, r4, r5
|
|
8011f86: 4616 mov r6, r2
|
|
8011f88: f7ff feba bl 8011d00 <__ulp>
|
|
8011f8c: ec51 0b10 vmov r0, r1, d0
|
|
8011f90: b17e cbz r6, 8011fb2 <sulp+0x36>
|
|
8011f92: f3c5 530a ubfx r3, r5, #20, #11
|
|
8011f96: f1c3 036b rsb r3, r3, #107 @ 0x6b
|
|
8011f9a: 2b00 cmp r3, #0
|
|
8011f9c: dd09 ble.n 8011fb2 <sulp+0x36>
|
|
8011f9e: 051b lsls r3, r3, #20
|
|
8011fa0: f103 557f add.w r5, r3, #1069547520 @ 0x3fc00000
|
|
8011fa4: 2400 movs r4, #0
|
|
8011fa6: f505 1540 add.w r5, r5, #3145728 @ 0x300000
|
|
8011faa: 4622 mov r2, r4
|
|
8011fac: 462b mov r3, r5
|
|
8011fae: f7ee fb23 bl 80005f8 <__aeabi_dmul>
|
|
8011fb2: ec41 0b10 vmov d0, r0, r1
|
|
8011fb6: bd70 pop {r4, r5, r6, pc}
|
|
|
|
08011fb8 <_strtod_l>:
|
|
8011fb8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8011fbc: b09f sub sp, #124 @ 0x7c
|
|
8011fbe: 460c mov r4, r1
|
|
8011fc0: 9217 str r2, [sp, #92] @ 0x5c
|
|
8011fc2: 2200 movs r2, #0
|
|
8011fc4: 921a str r2, [sp, #104] @ 0x68
|
|
8011fc6: 9005 str r0, [sp, #20]
|
|
8011fc8: f04f 0a00 mov.w sl, #0
|
|
8011fcc: f04f 0b00 mov.w fp, #0
|
|
8011fd0: 460a mov r2, r1
|
|
8011fd2: 9219 str r2, [sp, #100] @ 0x64
|
|
8011fd4: 7811 ldrb r1, [r2, #0]
|
|
8011fd6: 292b cmp r1, #43 @ 0x2b
|
|
8011fd8: d04a beq.n 8012070 <_strtod_l+0xb8>
|
|
8011fda: d838 bhi.n 801204e <_strtod_l+0x96>
|
|
8011fdc: 290d cmp r1, #13
|
|
8011fde: d832 bhi.n 8012046 <_strtod_l+0x8e>
|
|
8011fe0: 2908 cmp r1, #8
|
|
8011fe2: d832 bhi.n 801204a <_strtod_l+0x92>
|
|
8011fe4: 2900 cmp r1, #0
|
|
8011fe6: d03b beq.n 8012060 <_strtod_l+0xa8>
|
|
8011fe8: 2200 movs r2, #0
|
|
8011fea: 920e str r2, [sp, #56] @ 0x38
|
|
8011fec: 9d19 ldr r5, [sp, #100] @ 0x64
|
|
8011fee: 782a ldrb r2, [r5, #0]
|
|
8011ff0: 2a30 cmp r2, #48 @ 0x30
|
|
8011ff2: f040 80b2 bne.w 801215a <_strtod_l+0x1a2>
|
|
8011ff6: 786a ldrb r2, [r5, #1]
|
|
8011ff8: f002 02df and.w r2, r2, #223 @ 0xdf
|
|
8011ffc: 2a58 cmp r2, #88 @ 0x58
|
|
8011ffe: d16e bne.n 80120de <_strtod_l+0x126>
|
|
8012000: 9302 str r3, [sp, #8]
|
|
8012002: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
8012004: 9301 str r3, [sp, #4]
|
|
8012006: ab1a add r3, sp, #104 @ 0x68
|
|
8012008: 9300 str r3, [sp, #0]
|
|
801200a: 4a8f ldr r2, [pc, #572] @ (8012248 <_strtod_l+0x290>)
|
|
801200c: 9805 ldr r0, [sp, #20]
|
|
801200e: ab1b add r3, sp, #108 @ 0x6c
|
|
8012010: a919 add r1, sp, #100 @ 0x64
|
|
8012012: f001 fac7 bl 80135a4 <__gethex>
|
|
8012016: f010 060f ands.w r6, r0, #15
|
|
801201a: 4604 mov r4, r0
|
|
801201c: d005 beq.n 801202a <_strtod_l+0x72>
|
|
801201e: 2e06 cmp r6, #6
|
|
8012020: d128 bne.n 8012074 <_strtod_l+0xbc>
|
|
8012022: 3501 adds r5, #1
|
|
8012024: 2300 movs r3, #0
|
|
8012026: 9519 str r5, [sp, #100] @ 0x64
|
|
8012028: 930e str r3, [sp, #56] @ 0x38
|
|
801202a: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801202c: 2b00 cmp r3, #0
|
|
801202e: f040 858e bne.w 8012b4e <_strtod_l+0xb96>
|
|
8012032: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
8012034: b1cb cbz r3, 801206a <_strtod_l+0xb2>
|
|
8012036: 4652 mov r2, sl
|
|
8012038: f10b 4300 add.w r3, fp, #2147483648 @ 0x80000000
|
|
801203c: ec43 2b10 vmov d0, r2, r3
|
|
8012040: b01f add sp, #124 @ 0x7c
|
|
8012042: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8012046: 2920 cmp r1, #32
|
|
8012048: d1ce bne.n 8011fe8 <_strtod_l+0x30>
|
|
801204a: 3201 adds r2, #1
|
|
801204c: e7c1 b.n 8011fd2 <_strtod_l+0x1a>
|
|
801204e: 292d cmp r1, #45 @ 0x2d
|
|
8012050: d1ca bne.n 8011fe8 <_strtod_l+0x30>
|
|
8012052: 2101 movs r1, #1
|
|
8012054: 910e str r1, [sp, #56] @ 0x38
|
|
8012056: 1c51 adds r1, r2, #1
|
|
8012058: 9119 str r1, [sp, #100] @ 0x64
|
|
801205a: 7852 ldrb r2, [r2, #1]
|
|
801205c: 2a00 cmp r2, #0
|
|
801205e: d1c5 bne.n 8011fec <_strtod_l+0x34>
|
|
8012060: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
8012062: 9419 str r4, [sp, #100] @ 0x64
|
|
8012064: 2b00 cmp r3, #0
|
|
8012066: f040 8570 bne.w 8012b4a <_strtod_l+0xb92>
|
|
801206a: 4652 mov r2, sl
|
|
801206c: 465b mov r3, fp
|
|
801206e: e7e5 b.n 801203c <_strtod_l+0x84>
|
|
8012070: 2100 movs r1, #0
|
|
8012072: e7ef b.n 8012054 <_strtod_l+0x9c>
|
|
8012074: 9a1a ldr r2, [sp, #104] @ 0x68
|
|
8012076: b13a cbz r2, 8012088 <_strtod_l+0xd0>
|
|
8012078: 2135 movs r1, #53 @ 0x35
|
|
801207a: a81c add r0, sp, #112 @ 0x70
|
|
801207c: f7ff ff3a bl 8011ef4 <__copybits>
|
|
8012080: 991a ldr r1, [sp, #104] @ 0x68
|
|
8012082: 9805 ldr r0, [sp, #20]
|
|
8012084: f7ff fb10 bl 80116a8 <_Bfree>
|
|
8012088: 3e01 subs r6, #1
|
|
801208a: 9a1b ldr r2, [sp, #108] @ 0x6c
|
|
801208c: 2e04 cmp r6, #4
|
|
801208e: d806 bhi.n 801209e <_strtod_l+0xe6>
|
|
8012090: e8df f006 tbb [pc, r6]
|
|
8012094: 201d0314 .word 0x201d0314
|
|
8012098: 14 .byte 0x14
|
|
8012099: 00 .byte 0x00
|
|
801209a: e9dd ab1c ldrd sl, fp, [sp, #112] @ 0x70
|
|
801209e: 05e1 lsls r1, r4, #23
|
|
80120a0: bf48 it mi
|
|
80120a2: f04b 4b00 orrmi.w fp, fp, #2147483648 @ 0x80000000
|
|
80120a6: f02b 4300 bic.w r3, fp, #2147483648 @ 0x80000000
|
|
80120aa: 0d1b lsrs r3, r3, #20
|
|
80120ac: 051b lsls r3, r3, #20
|
|
80120ae: 2b00 cmp r3, #0
|
|
80120b0: d1bb bne.n 801202a <_strtod_l+0x72>
|
|
80120b2: f7fe fb01 bl 80106b8 <__errno>
|
|
80120b6: 2322 movs r3, #34 @ 0x22
|
|
80120b8: 6003 str r3, [r0, #0]
|
|
80120ba: e7b6 b.n 801202a <_strtod_l+0x72>
|
|
80120bc: e9dd a31c ldrd sl, r3, [sp, #112] @ 0x70
|
|
80120c0: f202 4233 addw r2, r2, #1075 @ 0x433
|
|
80120c4: f423 1380 bic.w r3, r3, #1048576 @ 0x100000
|
|
80120c8: ea43 5b02 orr.w fp, r3, r2, lsl #20
|
|
80120cc: e7e7 b.n 801209e <_strtod_l+0xe6>
|
|
80120ce: f8df b180 ldr.w fp, [pc, #384] @ 8012250 <_strtod_l+0x298>
|
|
80120d2: e7e4 b.n 801209e <_strtod_l+0xe6>
|
|
80120d4: f06f 4b00 mvn.w fp, #2147483648 @ 0x80000000
|
|
80120d8: f04f 3aff mov.w sl, #4294967295 @ 0xffffffff
|
|
80120dc: e7df b.n 801209e <_strtod_l+0xe6>
|
|
80120de: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
80120e0: 1c5a adds r2, r3, #1
|
|
80120e2: 9219 str r2, [sp, #100] @ 0x64
|
|
80120e4: 785b ldrb r3, [r3, #1]
|
|
80120e6: 2b30 cmp r3, #48 @ 0x30
|
|
80120e8: d0f9 beq.n 80120de <_strtod_l+0x126>
|
|
80120ea: 2b00 cmp r3, #0
|
|
80120ec: d09d beq.n 801202a <_strtod_l+0x72>
|
|
80120ee: 2301 movs r3, #1
|
|
80120f0: 2700 movs r7, #0
|
|
80120f2: 9308 str r3, [sp, #32]
|
|
80120f4: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
80120f6: 930c str r3, [sp, #48] @ 0x30
|
|
80120f8: 970b str r7, [sp, #44] @ 0x2c
|
|
80120fa: 46b9 mov r9, r7
|
|
80120fc: 220a movs r2, #10
|
|
80120fe: 9819 ldr r0, [sp, #100] @ 0x64
|
|
8012100: 7805 ldrb r5, [r0, #0]
|
|
8012102: f1a5 0330 sub.w r3, r5, #48 @ 0x30
|
|
8012106: b2d9 uxtb r1, r3
|
|
8012108: 2909 cmp r1, #9
|
|
801210a: d928 bls.n 801215e <_strtod_l+0x1a6>
|
|
801210c: 494f ldr r1, [pc, #316] @ (801224c <_strtod_l+0x294>)
|
|
801210e: 2201 movs r2, #1
|
|
8012110: f7fe f9f1 bl 80104f6 <strncmp>
|
|
8012114: 2800 cmp r0, #0
|
|
8012116: d032 beq.n 801217e <_strtod_l+0x1c6>
|
|
8012118: 2000 movs r0, #0
|
|
801211a: 462a mov r2, r5
|
|
801211c: 900a str r0, [sp, #40] @ 0x28
|
|
801211e: 464d mov r5, r9
|
|
8012120: 4603 mov r3, r0
|
|
8012122: 2a65 cmp r2, #101 @ 0x65
|
|
8012124: d001 beq.n 801212a <_strtod_l+0x172>
|
|
8012126: 2a45 cmp r2, #69 @ 0x45
|
|
8012128: d114 bne.n 8012154 <_strtod_l+0x19c>
|
|
801212a: b91d cbnz r5, 8012134 <_strtod_l+0x17c>
|
|
801212c: 9a08 ldr r2, [sp, #32]
|
|
801212e: 4302 orrs r2, r0
|
|
8012130: d096 beq.n 8012060 <_strtod_l+0xa8>
|
|
8012132: 2500 movs r5, #0
|
|
8012134: 9c19 ldr r4, [sp, #100] @ 0x64
|
|
8012136: 1c62 adds r2, r4, #1
|
|
8012138: 9219 str r2, [sp, #100] @ 0x64
|
|
801213a: 7862 ldrb r2, [r4, #1]
|
|
801213c: 2a2b cmp r2, #43 @ 0x2b
|
|
801213e: d07a beq.n 8012236 <_strtod_l+0x27e>
|
|
8012140: 2a2d cmp r2, #45 @ 0x2d
|
|
8012142: d07e beq.n 8012242 <_strtod_l+0x28a>
|
|
8012144: f04f 0c00 mov.w ip, #0
|
|
8012148: f1a2 0130 sub.w r1, r2, #48 @ 0x30
|
|
801214c: 2909 cmp r1, #9
|
|
801214e: f240 8085 bls.w 801225c <_strtod_l+0x2a4>
|
|
8012152: 9419 str r4, [sp, #100] @ 0x64
|
|
8012154: f04f 0800 mov.w r8, #0
|
|
8012158: e0a5 b.n 80122a6 <_strtod_l+0x2ee>
|
|
801215a: 2300 movs r3, #0
|
|
801215c: e7c8 b.n 80120f0 <_strtod_l+0x138>
|
|
801215e: f1b9 0f08 cmp.w r9, #8
|
|
8012162: bfd8 it le
|
|
8012164: 990b ldrle r1, [sp, #44] @ 0x2c
|
|
8012166: f100 0001 add.w r0, r0, #1
|
|
801216a: bfda itte le
|
|
801216c: fb02 3301 mlale r3, r2, r1, r3
|
|
8012170: 930b strle r3, [sp, #44] @ 0x2c
|
|
8012172: fb02 3707 mlagt r7, r2, r7, r3
|
|
8012176: f109 0901 add.w r9, r9, #1
|
|
801217a: 9019 str r0, [sp, #100] @ 0x64
|
|
801217c: e7bf b.n 80120fe <_strtod_l+0x146>
|
|
801217e: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
8012180: 1c5a adds r2, r3, #1
|
|
8012182: 9219 str r2, [sp, #100] @ 0x64
|
|
8012184: 785a ldrb r2, [r3, #1]
|
|
8012186: f1b9 0f00 cmp.w r9, #0
|
|
801218a: d03b beq.n 8012204 <_strtod_l+0x24c>
|
|
801218c: 900a str r0, [sp, #40] @ 0x28
|
|
801218e: 464d mov r5, r9
|
|
8012190: f1a2 0330 sub.w r3, r2, #48 @ 0x30
|
|
8012194: 2b09 cmp r3, #9
|
|
8012196: d912 bls.n 80121be <_strtod_l+0x206>
|
|
8012198: 2301 movs r3, #1
|
|
801219a: e7c2 b.n 8012122 <_strtod_l+0x16a>
|
|
801219c: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
801219e: 1c5a adds r2, r3, #1
|
|
80121a0: 9219 str r2, [sp, #100] @ 0x64
|
|
80121a2: 785a ldrb r2, [r3, #1]
|
|
80121a4: 3001 adds r0, #1
|
|
80121a6: 2a30 cmp r2, #48 @ 0x30
|
|
80121a8: d0f8 beq.n 801219c <_strtod_l+0x1e4>
|
|
80121aa: f1a2 0331 sub.w r3, r2, #49 @ 0x31
|
|
80121ae: 2b08 cmp r3, #8
|
|
80121b0: f200 84d2 bhi.w 8012b58 <_strtod_l+0xba0>
|
|
80121b4: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
80121b6: 900a str r0, [sp, #40] @ 0x28
|
|
80121b8: 2000 movs r0, #0
|
|
80121ba: 930c str r3, [sp, #48] @ 0x30
|
|
80121bc: 4605 mov r5, r0
|
|
80121be: 3a30 subs r2, #48 @ 0x30
|
|
80121c0: f100 0301 add.w r3, r0, #1
|
|
80121c4: d018 beq.n 80121f8 <_strtod_l+0x240>
|
|
80121c6: 990a ldr r1, [sp, #40] @ 0x28
|
|
80121c8: 4419 add r1, r3
|
|
80121ca: 910a str r1, [sp, #40] @ 0x28
|
|
80121cc: 462e mov r6, r5
|
|
80121ce: f04f 0e0a mov.w lr, #10
|
|
80121d2: 1c71 adds r1, r6, #1
|
|
80121d4: eba1 0c05 sub.w ip, r1, r5
|
|
80121d8: 4563 cmp r3, ip
|
|
80121da: dc15 bgt.n 8012208 <_strtod_l+0x250>
|
|
80121dc: ea20 70e0 bic.w r0, r0, r0, asr #31
|
|
80121e0: 182b adds r3, r5, r0
|
|
80121e2: 2b08 cmp r3, #8
|
|
80121e4: f105 0501 add.w r5, r5, #1
|
|
80121e8: 4405 add r5, r0
|
|
80121ea: dc1a bgt.n 8012222 <_strtod_l+0x26a>
|
|
80121ec: 990b ldr r1, [sp, #44] @ 0x2c
|
|
80121ee: 230a movs r3, #10
|
|
80121f0: fb03 2301 mla r3, r3, r1, r2
|
|
80121f4: 930b str r3, [sp, #44] @ 0x2c
|
|
80121f6: 2300 movs r3, #0
|
|
80121f8: 9a19 ldr r2, [sp, #100] @ 0x64
|
|
80121fa: 1c51 adds r1, r2, #1
|
|
80121fc: 9119 str r1, [sp, #100] @ 0x64
|
|
80121fe: 7852 ldrb r2, [r2, #1]
|
|
8012200: 4618 mov r0, r3
|
|
8012202: e7c5 b.n 8012190 <_strtod_l+0x1d8>
|
|
8012204: 4648 mov r0, r9
|
|
8012206: e7ce b.n 80121a6 <_strtod_l+0x1ee>
|
|
8012208: 2e08 cmp r6, #8
|
|
801220a: dc05 bgt.n 8012218 <_strtod_l+0x260>
|
|
801220c: 9e0b ldr r6, [sp, #44] @ 0x2c
|
|
801220e: fb0e f606 mul.w r6, lr, r6
|
|
8012212: 960b str r6, [sp, #44] @ 0x2c
|
|
8012214: 460e mov r6, r1
|
|
8012216: e7dc b.n 80121d2 <_strtod_l+0x21a>
|
|
8012218: 2910 cmp r1, #16
|
|
801221a: bfd8 it le
|
|
801221c: fb0e f707 mulle.w r7, lr, r7
|
|
8012220: e7f8 b.n 8012214 <_strtod_l+0x25c>
|
|
8012222: 2b0f cmp r3, #15
|
|
8012224: bfdc itt le
|
|
8012226: 230a movle r3, #10
|
|
8012228: fb03 2707 mlale r7, r3, r7, r2
|
|
801222c: e7e3 b.n 80121f6 <_strtod_l+0x23e>
|
|
801222e: 2300 movs r3, #0
|
|
8012230: 930a str r3, [sp, #40] @ 0x28
|
|
8012232: 2301 movs r3, #1
|
|
8012234: e77a b.n 801212c <_strtod_l+0x174>
|
|
8012236: f04f 0c00 mov.w ip, #0
|
|
801223a: 1ca2 adds r2, r4, #2
|
|
801223c: 9219 str r2, [sp, #100] @ 0x64
|
|
801223e: 78a2 ldrb r2, [r4, #2]
|
|
8012240: e782 b.n 8012148 <_strtod_l+0x190>
|
|
8012242: f04f 0c01 mov.w ip, #1
|
|
8012246: e7f8 b.n 801223a <_strtod_l+0x282>
|
|
8012248: 08014acc .word 0x08014acc
|
|
801224c: 08014941 .word 0x08014941
|
|
8012250: 7ff00000 .word 0x7ff00000
|
|
8012254: 9a19 ldr r2, [sp, #100] @ 0x64
|
|
8012256: 1c51 adds r1, r2, #1
|
|
8012258: 9119 str r1, [sp, #100] @ 0x64
|
|
801225a: 7852 ldrb r2, [r2, #1]
|
|
801225c: 2a30 cmp r2, #48 @ 0x30
|
|
801225e: d0f9 beq.n 8012254 <_strtod_l+0x29c>
|
|
8012260: f1a2 0131 sub.w r1, r2, #49 @ 0x31
|
|
8012264: 2908 cmp r1, #8
|
|
8012266: f63f af75 bhi.w 8012154 <_strtod_l+0x19c>
|
|
801226a: 3a30 subs r2, #48 @ 0x30
|
|
801226c: 9209 str r2, [sp, #36] @ 0x24
|
|
801226e: 9a19 ldr r2, [sp, #100] @ 0x64
|
|
8012270: 920f str r2, [sp, #60] @ 0x3c
|
|
8012272: f04f 080a mov.w r8, #10
|
|
8012276: 9a19 ldr r2, [sp, #100] @ 0x64
|
|
8012278: 1c56 adds r6, r2, #1
|
|
801227a: 9619 str r6, [sp, #100] @ 0x64
|
|
801227c: 7852 ldrb r2, [r2, #1]
|
|
801227e: f1a2 0e30 sub.w lr, r2, #48 @ 0x30
|
|
8012282: f1be 0f09 cmp.w lr, #9
|
|
8012286: d939 bls.n 80122fc <_strtod_l+0x344>
|
|
8012288: 990f ldr r1, [sp, #60] @ 0x3c
|
|
801228a: 1a76 subs r6, r6, r1
|
|
801228c: 2e08 cmp r6, #8
|
|
801228e: f644 681f movw r8, #19999 @ 0x4e1f
|
|
8012292: dc03 bgt.n 801229c <_strtod_l+0x2e4>
|
|
8012294: 9909 ldr r1, [sp, #36] @ 0x24
|
|
8012296: 4588 cmp r8, r1
|
|
8012298: bfa8 it ge
|
|
801229a: 4688 movge r8, r1
|
|
801229c: f1bc 0f00 cmp.w ip, #0
|
|
80122a0: d001 beq.n 80122a6 <_strtod_l+0x2ee>
|
|
80122a2: f1c8 0800 rsb r8, r8, #0
|
|
80122a6: 2d00 cmp r5, #0
|
|
80122a8: d14e bne.n 8012348 <_strtod_l+0x390>
|
|
80122aa: 9908 ldr r1, [sp, #32]
|
|
80122ac: 4308 orrs r0, r1
|
|
80122ae: f47f aebc bne.w 801202a <_strtod_l+0x72>
|
|
80122b2: 2b00 cmp r3, #0
|
|
80122b4: f47f aed4 bne.w 8012060 <_strtod_l+0xa8>
|
|
80122b8: 2a69 cmp r2, #105 @ 0x69
|
|
80122ba: d028 beq.n 801230e <_strtod_l+0x356>
|
|
80122bc: dc25 bgt.n 801230a <_strtod_l+0x352>
|
|
80122be: 2a49 cmp r2, #73 @ 0x49
|
|
80122c0: d025 beq.n 801230e <_strtod_l+0x356>
|
|
80122c2: 2a4e cmp r2, #78 @ 0x4e
|
|
80122c4: f47f aecc bne.w 8012060 <_strtod_l+0xa8>
|
|
80122c8: 499a ldr r1, [pc, #616] @ (8012534 <_strtod_l+0x57c>)
|
|
80122ca: a819 add r0, sp, #100 @ 0x64
|
|
80122cc: f001 fb8c bl 80139e8 <__match>
|
|
80122d0: 2800 cmp r0, #0
|
|
80122d2: f43f aec5 beq.w 8012060 <_strtod_l+0xa8>
|
|
80122d6: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
80122d8: 781b ldrb r3, [r3, #0]
|
|
80122da: 2b28 cmp r3, #40 @ 0x28
|
|
80122dc: d12e bne.n 801233c <_strtod_l+0x384>
|
|
80122de: 4996 ldr r1, [pc, #600] @ (8012538 <_strtod_l+0x580>)
|
|
80122e0: aa1c add r2, sp, #112 @ 0x70
|
|
80122e2: a819 add r0, sp, #100 @ 0x64
|
|
80122e4: f001 fb94 bl 8013a10 <__hexnan>
|
|
80122e8: 2805 cmp r0, #5
|
|
80122ea: d127 bne.n 801233c <_strtod_l+0x384>
|
|
80122ec: 9b1d ldr r3, [sp, #116] @ 0x74
|
|
80122ee: f8dd a070 ldr.w sl, [sp, #112] @ 0x70
|
|
80122f2: f043 4bff orr.w fp, r3, #2139095040 @ 0x7f800000
|
|
80122f6: f44b 0be0 orr.w fp, fp, #7340032 @ 0x700000
|
|
80122fa: e696 b.n 801202a <_strtod_l+0x72>
|
|
80122fc: 9909 ldr r1, [sp, #36] @ 0x24
|
|
80122fe: fb08 2101 mla r1, r8, r1, r2
|
|
8012302: f1a1 0230 sub.w r2, r1, #48 @ 0x30
|
|
8012306: 9209 str r2, [sp, #36] @ 0x24
|
|
8012308: e7b5 b.n 8012276 <_strtod_l+0x2be>
|
|
801230a: 2a6e cmp r2, #110 @ 0x6e
|
|
801230c: e7da b.n 80122c4 <_strtod_l+0x30c>
|
|
801230e: 498b ldr r1, [pc, #556] @ (801253c <_strtod_l+0x584>)
|
|
8012310: a819 add r0, sp, #100 @ 0x64
|
|
8012312: f001 fb69 bl 80139e8 <__match>
|
|
8012316: 2800 cmp r0, #0
|
|
8012318: f43f aea2 beq.w 8012060 <_strtod_l+0xa8>
|
|
801231c: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
801231e: 4988 ldr r1, [pc, #544] @ (8012540 <_strtod_l+0x588>)
|
|
8012320: 3b01 subs r3, #1
|
|
8012322: a819 add r0, sp, #100 @ 0x64
|
|
8012324: 9319 str r3, [sp, #100] @ 0x64
|
|
8012326: f001 fb5f bl 80139e8 <__match>
|
|
801232a: b910 cbnz r0, 8012332 <_strtod_l+0x37a>
|
|
801232c: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
801232e: 3301 adds r3, #1
|
|
8012330: 9319 str r3, [sp, #100] @ 0x64
|
|
8012332: f8df b21c ldr.w fp, [pc, #540] @ 8012550 <_strtod_l+0x598>
|
|
8012336: f04f 0a00 mov.w sl, #0
|
|
801233a: e676 b.n 801202a <_strtod_l+0x72>
|
|
801233c: 4881 ldr r0, [pc, #516] @ (8012544 <_strtod_l+0x58c>)
|
|
801233e: f001 f8a7 bl 8013490 <nan>
|
|
8012342: ec5b ab10 vmov sl, fp, d0
|
|
8012346: e670 b.n 801202a <_strtod_l+0x72>
|
|
8012348: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801234a: 980b ldr r0, [sp, #44] @ 0x2c
|
|
801234c: eba8 0303 sub.w r3, r8, r3
|
|
8012350: f1b9 0f00 cmp.w r9, #0
|
|
8012354: bf08 it eq
|
|
8012356: 46a9 moveq r9, r5
|
|
8012358: 2d10 cmp r5, #16
|
|
801235a: 9309 str r3, [sp, #36] @ 0x24
|
|
801235c: 462c mov r4, r5
|
|
801235e: bfa8 it ge
|
|
8012360: 2410 movge r4, #16
|
|
8012362: f7ee f8cf bl 8000504 <__aeabi_ui2d>
|
|
8012366: 2d09 cmp r5, #9
|
|
8012368: 4682 mov sl, r0
|
|
801236a: 468b mov fp, r1
|
|
801236c: dc13 bgt.n 8012396 <_strtod_l+0x3de>
|
|
801236e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8012370: 2b00 cmp r3, #0
|
|
8012372: f43f ae5a beq.w 801202a <_strtod_l+0x72>
|
|
8012376: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8012378: dd78 ble.n 801246c <_strtod_l+0x4b4>
|
|
801237a: 2b16 cmp r3, #22
|
|
801237c: dc5f bgt.n 801243e <_strtod_l+0x486>
|
|
801237e: 4972 ldr r1, [pc, #456] @ (8012548 <_strtod_l+0x590>)
|
|
8012380: eb01 01c3 add.w r1, r1, r3, lsl #3
|
|
8012384: e9d1 0100 ldrd r0, r1, [r1]
|
|
8012388: 4652 mov r2, sl
|
|
801238a: 465b mov r3, fp
|
|
801238c: f7ee f934 bl 80005f8 <__aeabi_dmul>
|
|
8012390: 4682 mov sl, r0
|
|
8012392: 468b mov fp, r1
|
|
8012394: e649 b.n 801202a <_strtod_l+0x72>
|
|
8012396: 4b6c ldr r3, [pc, #432] @ (8012548 <_strtod_l+0x590>)
|
|
8012398: eb03 03c4 add.w r3, r3, r4, lsl #3
|
|
801239c: e953 2312 ldrd r2, r3, [r3, #-72] @ 0x48
|
|
80123a0: f7ee f92a bl 80005f8 <__aeabi_dmul>
|
|
80123a4: 4682 mov sl, r0
|
|
80123a6: 4638 mov r0, r7
|
|
80123a8: 468b mov fp, r1
|
|
80123aa: f7ee f8ab bl 8000504 <__aeabi_ui2d>
|
|
80123ae: 4602 mov r2, r0
|
|
80123b0: 460b mov r3, r1
|
|
80123b2: 4650 mov r0, sl
|
|
80123b4: 4659 mov r1, fp
|
|
80123b6: f7ed ff69 bl 800028c <__adddf3>
|
|
80123ba: 2d0f cmp r5, #15
|
|
80123bc: 4682 mov sl, r0
|
|
80123be: 468b mov fp, r1
|
|
80123c0: ddd5 ble.n 801236e <_strtod_l+0x3b6>
|
|
80123c2: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80123c4: 1b2c subs r4, r5, r4
|
|
80123c6: 441c add r4, r3
|
|
80123c8: 2c00 cmp r4, #0
|
|
80123ca: f340 8093 ble.w 80124f4 <_strtod_l+0x53c>
|
|
80123ce: f014 030f ands.w r3, r4, #15
|
|
80123d2: d00a beq.n 80123ea <_strtod_l+0x432>
|
|
80123d4: 495c ldr r1, [pc, #368] @ (8012548 <_strtod_l+0x590>)
|
|
80123d6: eb01 01c3 add.w r1, r1, r3, lsl #3
|
|
80123da: 4652 mov r2, sl
|
|
80123dc: 465b mov r3, fp
|
|
80123de: e9d1 0100 ldrd r0, r1, [r1]
|
|
80123e2: f7ee f909 bl 80005f8 <__aeabi_dmul>
|
|
80123e6: 4682 mov sl, r0
|
|
80123e8: 468b mov fp, r1
|
|
80123ea: f034 040f bics.w r4, r4, #15
|
|
80123ee: d073 beq.n 80124d8 <_strtod_l+0x520>
|
|
80123f0: f5b4 7f9a cmp.w r4, #308 @ 0x134
|
|
80123f4: dd49 ble.n 801248a <_strtod_l+0x4d2>
|
|
80123f6: 2400 movs r4, #0
|
|
80123f8: 46a0 mov r8, r4
|
|
80123fa: 940b str r4, [sp, #44] @ 0x2c
|
|
80123fc: 46a1 mov r9, r4
|
|
80123fe: 9a05 ldr r2, [sp, #20]
|
|
8012400: f8df b14c ldr.w fp, [pc, #332] @ 8012550 <_strtod_l+0x598>
|
|
8012404: 2322 movs r3, #34 @ 0x22
|
|
8012406: 6013 str r3, [r2, #0]
|
|
8012408: f04f 0a00 mov.w sl, #0
|
|
801240c: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
801240e: 2b00 cmp r3, #0
|
|
8012410: f43f ae0b beq.w 801202a <_strtod_l+0x72>
|
|
8012414: 991a ldr r1, [sp, #104] @ 0x68
|
|
8012416: 9805 ldr r0, [sp, #20]
|
|
8012418: f7ff f946 bl 80116a8 <_Bfree>
|
|
801241c: 9805 ldr r0, [sp, #20]
|
|
801241e: 4649 mov r1, r9
|
|
8012420: f7ff f942 bl 80116a8 <_Bfree>
|
|
8012424: 9805 ldr r0, [sp, #20]
|
|
8012426: 4641 mov r1, r8
|
|
8012428: f7ff f93e bl 80116a8 <_Bfree>
|
|
801242c: 990b ldr r1, [sp, #44] @ 0x2c
|
|
801242e: 9805 ldr r0, [sp, #20]
|
|
8012430: f7ff f93a bl 80116a8 <_Bfree>
|
|
8012434: 9805 ldr r0, [sp, #20]
|
|
8012436: 4621 mov r1, r4
|
|
8012438: f7ff f936 bl 80116a8 <_Bfree>
|
|
801243c: e5f5 b.n 801202a <_strtod_l+0x72>
|
|
801243e: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8012440: f1c5 0325 rsb r3, r5, #37 @ 0x25
|
|
8012444: 4293 cmp r3, r2
|
|
8012446: dbbc blt.n 80123c2 <_strtod_l+0x40a>
|
|
8012448: 4c3f ldr r4, [pc, #252] @ (8012548 <_strtod_l+0x590>)
|
|
801244a: f1c5 050f rsb r5, r5, #15
|
|
801244e: eb04 01c5 add.w r1, r4, r5, lsl #3
|
|
8012452: 4652 mov r2, sl
|
|
8012454: 465b mov r3, fp
|
|
8012456: e9d1 0100 ldrd r0, r1, [r1]
|
|
801245a: f7ee f8cd bl 80005f8 <__aeabi_dmul>
|
|
801245e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8012460: 1b5d subs r5, r3, r5
|
|
8012462: eb04 04c5 add.w r4, r4, r5, lsl #3
|
|
8012466: e9d4 2300 ldrd r2, r3, [r4]
|
|
801246a: e78f b.n 801238c <_strtod_l+0x3d4>
|
|
801246c: 3316 adds r3, #22
|
|
801246e: dba8 blt.n 80123c2 <_strtod_l+0x40a>
|
|
8012470: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
8012472: eba3 0808 sub.w r8, r3, r8
|
|
8012476: 4b34 ldr r3, [pc, #208] @ (8012548 <_strtod_l+0x590>)
|
|
8012478: eb03 08c8 add.w r8, r3, r8, lsl #3
|
|
801247c: e9d8 2300 ldrd r2, r3, [r8]
|
|
8012480: 4650 mov r0, sl
|
|
8012482: 4659 mov r1, fp
|
|
8012484: f7ee f9e2 bl 800084c <__aeabi_ddiv>
|
|
8012488: e782 b.n 8012390 <_strtod_l+0x3d8>
|
|
801248a: 2300 movs r3, #0
|
|
801248c: 4f2f ldr r7, [pc, #188] @ (801254c <_strtod_l+0x594>)
|
|
801248e: 1124 asrs r4, r4, #4
|
|
8012490: 4650 mov r0, sl
|
|
8012492: 4659 mov r1, fp
|
|
8012494: 461e mov r6, r3
|
|
8012496: 2c01 cmp r4, #1
|
|
8012498: dc21 bgt.n 80124de <_strtod_l+0x526>
|
|
801249a: b10b cbz r3, 80124a0 <_strtod_l+0x4e8>
|
|
801249c: 4682 mov sl, r0
|
|
801249e: 468b mov fp, r1
|
|
80124a0: 492a ldr r1, [pc, #168] @ (801254c <_strtod_l+0x594>)
|
|
80124a2: f1ab 7b54 sub.w fp, fp, #55574528 @ 0x3500000
|
|
80124a6: eb01 01c6 add.w r1, r1, r6, lsl #3
|
|
80124aa: 4652 mov r2, sl
|
|
80124ac: 465b mov r3, fp
|
|
80124ae: e9d1 0100 ldrd r0, r1, [r1]
|
|
80124b2: f7ee f8a1 bl 80005f8 <__aeabi_dmul>
|
|
80124b6: 4b26 ldr r3, [pc, #152] @ (8012550 <_strtod_l+0x598>)
|
|
80124b8: 460a mov r2, r1
|
|
80124ba: 400b ands r3, r1
|
|
80124bc: 4925 ldr r1, [pc, #148] @ (8012554 <_strtod_l+0x59c>)
|
|
80124be: 428b cmp r3, r1
|
|
80124c0: 4682 mov sl, r0
|
|
80124c2: d898 bhi.n 80123f6 <_strtod_l+0x43e>
|
|
80124c4: f5a1 1180 sub.w r1, r1, #1048576 @ 0x100000
|
|
80124c8: 428b cmp r3, r1
|
|
80124ca: bf86 itte hi
|
|
80124cc: f8df b088 ldrhi.w fp, [pc, #136] @ 8012558 <_strtod_l+0x5a0>
|
|
80124d0: f04f 3aff movhi.w sl, #4294967295 @ 0xffffffff
|
|
80124d4: f102 7b54 addls.w fp, r2, #55574528 @ 0x3500000
|
|
80124d8: 2300 movs r3, #0
|
|
80124da: 9308 str r3, [sp, #32]
|
|
80124dc: e076 b.n 80125cc <_strtod_l+0x614>
|
|
80124de: 07e2 lsls r2, r4, #31
|
|
80124e0: d504 bpl.n 80124ec <_strtod_l+0x534>
|
|
80124e2: e9d7 2300 ldrd r2, r3, [r7]
|
|
80124e6: f7ee f887 bl 80005f8 <__aeabi_dmul>
|
|
80124ea: 2301 movs r3, #1
|
|
80124ec: 3601 adds r6, #1
|
|
80124ee: 1064 asrs r4, r4, #1
|
|
80124f0: 3708 adds r7, #8
|
|
80124f2: e7d0 b.n 8012496 <_strtod_l+0x4de>
|
|
80124f4: d0f0 beq.n 80124d8 <_strtod_l+0x520>
|
|
80124f6: 4264 negs r4, r4
|
|
80124f8: f014 020f ands.w r2, r4, #15
|
|
80124fc: d00a beq.n 8012514 <_strtod_l+0x55c>
|
|
80124fe: 4b12 ldr r3, [pc, #72] @ (8012548 <_strtod_l+0x590>)
|
|
8012500: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
8012504: 4650 mov r0, sl
|
|
8012506: 4659 mov r1, fp
|
|
8012508: e9d3 2300 ldrd r2, r3, [r3]
|
|
801250c: f7ee f99e bl 800084c <__aeabi_ddiv>
|
|
8012510: 4682 mov sl, r0
|
|
8012512: 468b mov fp, r1
|
|
8012514: 1124 asrs r4, r4, #4
|
|
8012516: d0df beq.n 80124d8 <_strtod_l+0x520>
|
|
8012518: 2c1f cmp r4, #31
|
|
801251a: dd1f ble.n 801255c <_strtod_l+0x5a4>
|
|
801251c: 2400 movs r4, #0
|
|
801251e: 46a0 mov r8, r4
|
|
8012520: 940b str r4, [sp, #44] @ 0x2c
|
|
8012522: 46a1 mov r9, r4
|
|
8012524: 9a05 ldr r2, [sp, #20]
|
|
8012526: 2322 movs r3, #34 @ 0x22
|
|
8012528: f04f 0a00 mov.w sl, #0
|
|
801252c: f04f 0b00 mov.w fp, #0
|
|
8012530: 6013 str r3, [r2, #0]
|
|
8012532: e76b b.n 801240c <_strtod_l+0x454>
|
|
8012534: 08014799 .word 0x08014799
|
|
8012538: 08014ab8 .word 0x08014ab8
|
|
801253c: 08014791 .word 0x08014791
|
|
8012540: 08014875 .word 0x08014875
|
|
8012544: 08014871 .word 0x08014871
|
|
8012548: 080149f0 .word 0x080149f0
|
|
801254c: 080149c8 .word 0x080149c8
|
|
8012550: 7ff00000 .word 0x7ff00000
|
|
8012554: 7ca00000 .word 0x7ca00000
|
|
8012558: 7fefffff .word 0x7fefffff
|
|
801255c: f014 0310 ands.w r3, r4, #16
|
|
8012560: bf18 it ne
|
|
8012562: 236a movne r3, #106 @ 0x6a
|
|
8012564: 4ea9 ldr r6, [pc, #676] @ (801280c <_strtod_l+0x854>)
|
|
8012566: 9308 str r3, [sp, #32]
|
|
8012568: 4650 mov r0, sl
|
|
801256a: 4659 mov r1, fp
|
|
801256c: 2300 movs r3, #0
|
|
801256e: 07e7 lsls r7, r4, #31
|
|
8012570: d504 bpl.n 801257c <_strtod_l+0x5c4>
|
|
8012572: e9d6 2300 ldrd r2, r3, [r6]
|
|
8012576: f7ee f83f bl 80005f8 <__aeabi_dmul>
|
|
801257a: 2301 movs r3, #1
|
|
801257c: 1064 asrs r4, r4, #1
|
|
801257e: f106 0608 add.w r6, r6, #8
|
|
8012582: d1f4 bne.n 801256e <_strtod_l+0x5b6>
|
|
8012584: b10b cbz r3, 801258a <_strtod_l+0x5d2>
|
|
8012586: 4682 mov sl, r0
|
|
8012588: 468b mov fp, r1
|
|
801258a: 9b08 ldr r3, [sp, #32]
|
|
801258c: b1b3 cbz r3, 80125bc <_strtod_l+0x604>
|
|
801258e: f3cb 520a ubfx r2, fp, #20, #11
|
|
8012592: f1c2 036b rsb r3, r2, #107 @ 0x6b
|
|
8012596: 2b00 cmp r3, #0
|
|
8012598: 4659 mov r1, fp
|
|
801259a: dd0f ble.n 80125bc <_strtod_l+0x604>
|
|
801259c: 2b1f cmp r3, #31
|
|
801259e: dd56 ble.n 801264e <_strtod_l+0x696>
|
|
80125a0: 2b34 cmp r3, #52 @ 0x34
|
|
80125a2: bfde ittt le
|
|
80125a4: f04f 33ff movle.w r3, #4294967295 @ 0xffffffff
|
|
80125a8: f1c2 024b rsble r2, r2, #75 @ 0x4b
|
|
80125ac: 4093 lslle r3, r2
|
|
80125ae: f04f 0a00 mov.w sl, #0
|
|
80125b2: bfcc ite gt
|
|
80125b4: f04f 7b5c movgt.w fp, #57671680 @ 0x3700000
|
|
80125b8: ea03 0b01 andle.w fp, r3, r1
|
|
80125bc: 2200 movs r2, #0
|
|
80125be: 2300 movs r3, #0
|
|
80125c0: 4650 mov r0, sl
|
|
80125c2: 4659 mov r1, fp
|
|
80125c4: f7ee fa80 bl 8000ac8 <__aeabi_dcmpeq>
|
|
80125c8: 2800 cmp r0, #0
|
|
80125ca: d1a7 bne.n 801251c <_strtod_l+0x564>
|
|
80125cc: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
80125ce: 9300 str r3, [sp, #0]
|
|
80125d0: 990c ldr r1, [sp, #48] @ 0x30
|
|
80125d2: 9805 ldr r0, [sp, #20]
|
|
80125d4: 462b mov r3, r5
|
|
80125d6: 464a mov r2, r9
|
|
80125d8: f7ff f8ce bl 8011778 <__s2b>
|
|
80125dc: 900b str r0, [sp, #44] @ 0x2c
|
|
80125de: 2800 cmp r0, #0
|
|
80125e0: f43f af09 beq.w 80123f6 <_strtod_l+0x43e>
|
|
80125e4: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
80125e6: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
80125e8: 2a00 cmp r2, #0
|
|
80125ea: eba3 0308 sub.w r3, r3, r8
|
|
80125ee: bfa8 it ge
|
|
80125f0: 2300 movge r3, #0
|
|
80125f2: 9312 str r3, [sp, #72] @ 0x48
|
|
80125f4: 2400 movs r4, #0
|
|
80125f6: ea22 73e2 bic.w r3, r2, r2, asr #31
|
|
80125fa: 9316 str r3, [sp, #88] @ 0x58
|
|
80125fc: 46a0 mov r8, r4
|
|
80125fe: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8012600: 9805 ldr r0, [sp, #20]
|
|
8012602: 6859 ldr r1, [r3, #4]
|
|
8012604: f7ff f810 bl 8011628 <_Balloc>
|
|
8012608: 4681 mov r9, r0
|
|
801260a: 2800 cmp r0, #0
|
|
801260c: f43f aef7 beq.w 80123fe <_strtod_l+0x446>
|
|
8012610: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8012612: 691a ldr r2, [r3, #16]
|
|
8012614: 3202 adds r2, #2
|
|
8012616: f103 010c add.w r1, r3, #12
|
|
801261a: 0092 lsls r2, r2, #2
|
|
801261c: 300c adds r0, #12
|
|
801261e: f7fe f878 bl 8010712 <memcpy>
|
|
8012622: ec4b ab10 vmov d0, sl, fp
|
|
8012626: 9805 ldr r0, [sp, #20]
|
|
8012628: aa1c add r2, sp, #112 @ 0x70
|
|
801262a: a91b add r1, sp, #108 @ 0x6c
|
|
801262c: e9cd ab0c strd sl, fp, [sp, #48] @ 0x30
|
|
8012630: f7ff fbd6 bl 8011de0 <__d2b>
|
|
8012634: 901a str r0, [sp, #104] @ 0x68
|
|
8012636: 2800 cmp r0, #0
|
|
8012638: f43f aee1 beq.w 80123fe <_strtod_l+0x446>
|
|
801263c: 9805 ldr r0, [sp, #20]
|
|
801263e: 2101 movs r1, #1
|
|
8012640: f7ff f930 bl 80118a4 <__i2b>
|
|
8012644: 4680 mov r8, r0
|
|
8012646: b948 cbnz r0, 801265c <_strtod_l+0x6a4>
|
|
8012648: f04f 0800 mov.w r8, #0
|
|
801264c: e6d7 b.n 80123fe <_strtod_l+0x446>
|
|
801264e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8012652: fa02 f303 lsl.w r3, r2, r3
|
|
8012656: ea03 0a0a and.w sl, r3, sl
|
|
801265a: e7af b.n 80125bc <_strtod_l+0x604>
|
|
801265c: 9d1b ldr r5, [sp, #108] @ 0x6c
|
|
801265e: 9a1c ldr r2, [sp, #112] @ 0x70
|
|
8012660: 2d00 cmp r5, #0
|
|
8012662: bfab itete ge
|
|
8012664: 9b12 ldrge r3, [sp, #72] @ 0x48
|
|
8012666: 9b16 ldrlt r3, [sp, #88] @ 0x58
|
|
8012668: 9e16 ldrge r6, [sp, #88] @ 0x58
|
|
801266a: 9f12 ldrlt r7, [sp, #72] @ 0x48
|
|
801266c: bfac ite ge
|
|
801266e: 18ef addge r7, r5, r3
|
|
8012670: 1b5e sublt r6, r3, r5
|
|
8012672: 9b08 ldr r3, [sp, #32]
|
|
8012674: 1aed subs r5, r5, r3
|
|
8012676: 4415 add r5, r2
|
|
8012678: 4b65 ldr r3, [pc, #404] @ (8012810 <_strtod_l+0x858>)
|
|
801267a: 3d01 subs r5, #1
|
|
801267c: 429d cmp r5, r3
|
|
801267e: f1c2 0236 rsb r2, r2, #54 @ 0x36
|
|
8012682: da50 bge.n 8012726 <_strtod_l+0x76e>
|
|
8012684: 1b5b subs r3, r3, r5
|
|
8012686: 2b1f cmp r3, #31
|
|
8012688: eba2 0203 sub.w r2, r2, r3
|
|
801268c: f04f 0101 mov.w r1, #1
|
|
8012690: dc3d bgt.n 801270e <_strtod_l+0x756>
|
|
8012692: fa01 f303 lsl.w r3, r1, r3
|
|
8012696: 9313 str r3, [sp, #76] @ 0x4c
|
|
8012698: 2300 movs r3, #0
|
|
801269a: 9310 str r3, [sp, #64] @ 0x40
|
|
801269c: 18bd adds r5, r7, r2
|
|
801269e: 9b08 ldr r3, [sp, #32]
|
|
80126a0: 42af cmp r7, r5
|
|
80126a2: 4416 add r6, r2
|
|
80126a4: 441e add r6, r3
|
|
80126a6: 463b mov r3, r7
|
|
80126a8: bfa8 it ge
|
|
80126aa: 462b movge r3, r5
|
|
80126ac: 42b3 cmp r3, r6
|
|
80126ae: bfa8 it ge
|
|
80126b0: 4633 movge r3, r6
|
|
80126b2: 2b00 cmp r3, #0
|
|
80126b4: bfc2 ittt gt
|
|
80126b6: 1aed subgt r5, r5, r3
|
|
80126b8: 1af6 subgt r6, r6, r3
|
|
80126ba: 1aff subgt r7, r7, r3
|
|
80126bc: 9b12 ldr r3, [sp, #72] @ 0x48
|
|
80126be: 2b00 cmp r3, #0
|
|
80126c0: dd16 ble.n 80126f0 <_strtod_l+0x738>
|
|
80126c2: 4641 mov r1, r8
|
|
80126c4: 9805 ldr r0, [sp, #20]
|
|
80126c6: 461a mov r2, r3
|
|
80126c8: f7ff f9a4 bl 8011a14 <__pow5mult>
|
|
80126cc: 4680 mov r8, r0
|
|
80126ce: 2800 cmp r0, #0
|
|
80126d0: d0ba beq.n 8012648 <_strtod_l+0x690>
|
|
80126d2: 4601 mov r1, r0
|
|
80126d4: 9a1a ldr r2, [sp, #104] @ 0x68
|
|
80126d6: 9805 ldr r0, [sp, #20]
|
|
80126d8: f7ff f8fa bl 80118d0 <__multiply>
|
|
80126dc: 900a str r0, [sp, #40] @ 0x28
|
|
80126de: 2800 cmp r0, #0
|
|
80126e0: f43f ae8d beq.w 80123fe <_strtod_l+0x446>
|
|
80126e4: 991a ldr r1, [sp, #104] @ 0x68
|
|
80126e6: 9805 ldr r0, [sp, #20]
|
|
80126e8: f7fe ffde bl 80116a8 <_Bfree>
|
|
80126ec: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
80126ee: 931a str r3, [sp, #104] @ 0x68
|
|
80126f0: 2d00 cmp r5, #0
|
|
80126f2: dc1d bgt.n 8012730 <_strtod_l+0x778>
|
|
80126f4: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80126f6: 2b00 cmp r3, #0
|
|
80126f8: dd23 ble.n 8012742 <_strtod_l+0x78a>
|
|
80126fa: 4649 mov r1, r9
|
|
80126fc: 9a16 ldr r2, [sp, #88] @ 0x58
|
|
80126fe: 9805 ldr r0, [sp, #20]
|
|
8012700: f7ff f988 bl 8011a14 <__pow5mult>
|
|
8012704: 4681 mov r9, r0
|
|
8012706: b9e0 cbnz r0, 8012742 <_strtod_l+0x78a>
|
|
8012708: f04f 0900 mov.w r9, #0
|
|
801270c: e677 b.n 80123fe <_strtod_l+0x446>
|
|
801270e: f1c5 457f rsb r5, r5, #4278190080 @ 0xff000000
|
|
8012712: f505 057f add.w r5, r5, #16711680 @ 0xff0000
|
|
8012716: f505 457b add.w r5, r5, #64256 @ 0xfb00
|
|
801271a: 35e2 adds r5, #226 @ 0xe2
|
|
801271c: fa01 f305 lsl.w r3, r1, r5
|
|
8012720: 9310 str r3, [sp, #64] @ 0x40
|
|
8012722: 9113 str r1, [sp, #76] @ 0x4c
|
|
8012724: e7ba b.n 801269c <_strtod_l+0x6e4>
|
|
8012726: 2300 movs r3, #0
|
|
8012728: 9310 str r3, [sp, #64] @ 0x40
|
|
801272a: 2301 movs r3, #1
|
|
801272c: 9313 str r3, [sp, #76] @ 0x4c
|
|
801272e: e7b5 b.n 801269c <_strtod_l+0x6e4>
|
|
8012730: 991a ldr r1, [sp, #104] @ 0x68
|
|
8012732: 9805 ldr r0, [sp, #20]
|
|
8012734: 462a mov r2, r5
|
|
8012736: f7ff f9c7 bl 8011ac8 <__lshift>
|
|
801273a: 901a str r0, [sp, #104] @ 0x68
|
|
801273c: 2800 cmp r0, #0
|
|
801273e: d1d9 bne.n 80126f4 <_strtod_l+0x73c>
|
|
8012740: e65d b.n 80123fe <_strtod_l+0x446>
|
|
8012742: 2e00 cmp r6, #0
|
|
8012744: dd07 ble.n 8012756 <_strtod_l+0x79e>
|
|
8012746: 4649 mov r1, r9
|
|
8012748: 9805 ldr r0, [sp, #20]
|
|
801274a: 4632 mov r2, r6
|
|
801274c: f7ff f9bc bl 8011ac8 <__lshift>
|
|
8012750: 4681 mov r9, r0
|
|
8012752: 2800 cmp r0, #0
|
|
8012754: d0d8 beq.n 8012708 <_strtod_l+0x750>
|
|
8012756: 2f00 cmp r7, #0
|
|
8012758: dd08 ble.n 801276c <_strtod_l+0x7b4>
|
|
801275a: 4641 mov r1, r8
|
|
801275c: 9805 ldr r0, [sp, #20]
|
|
801275e: 463a mov r2, r7
|
|
8012760: f7ff f9b2 bl 8011ac8 <__lshift>
|
|
8012764: 4680 mov r8, r0
|
|
8012766: 2800 cmp r0, #0
|
|
8012768: f43f ae49 beq.w 80123fe <_strtod_l+0x446>
|
|
801276c: 991a ldr r1, [sp, #104] @ 0x68
|
|
801276e: 9805 ldr r0, [sp, #20]
|
|
8012770: 464a mov r2, r9
|
|
8012772: f7ff fa31 bl 8011bd8 <__mdiff>
|
|
8012776: 4604 mov r4, r0
|
|
8012778: 2800 cmp r0, #0
|
|
801277a: f43f ae40 beq.w 80123fe <_strtod_l+0x446>
|
|
801277e: 68c3 ldr r3, [r0, #12]
|
|
8012780: 930f str r3, [sp, #60] @ 0x3c
|
|
8012782: 2300 movs r3, #0
|
|
8012784: 60c3 str r3, [r0, #12]
|
|
8012786: 4641 mov r1, r8
|
|
8012788: f7ff fa0a bl 8011ba0 <__mcmp>
|
|
801278c: 2800 cmp r0, #0
|
|
801278e: da45 bge.n 801281c <_strtod_l+0x864>
|
|
8012790: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
8012792: ea53 030a orrs.w r3, r3, sl
|
|
8012796: d16b bne.n 8012870 <_strtod_l+0x8b8>
|
|
8012798: f3cb 0313 ubfx r3, fp, #0, #20
|
|
801279c: 2b00 cmp r3, #0
|
|
801279e: d167 bne.n 8012870 <_strtod_l+0x8b8>
|
|
80127a0: f02b 4300 bic.w r3, fp, #2147483648 @ 0x80000000
|
|
80127a4: 0d1b lsrs r3, r3, #20
|
|
80127a6: 051b lsls r3, r3, #20
|
|
80127a8: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000
|
|
80127ac: d960 bls.n 8012870 <_strtod_l+0x8b8>
|
|
80127ae: 6963 ldr r3, [r4, #20]
|
|
80127b0: b913 cbnz r3, 80127b8 <_strtod_l+0x800>
|
|
80127b2: 6923 ldr r3, [r4, #16]
|
|
80127b4: 2b01 cmp r3, #1
|
|
80127b6: dd5b ble.n 8012870 <_strtod_l+0x8b8>
|
|
80127b8: 4621 mov r1, r4
|
|
80127ba: 2201 movs r2, #1
|
|
80127bc: 9805 ldr r0, [sp, #20]
|
|
80127be: f7ff f983 bl 8011ac8 <__lshift>
|
|
80127c2: 4641 mov r1, r8
|
|
80127c4: 4604 mov r4, r0
|
|
80127c6: f7ff f9eb bl 8011ba0 <__mcmp>
|
|
80127ca: 2800 cmp r0, #0
|
|
80127cc: dd50 ble.n 8012870 <_strtod_l+0x8b8>
|
|
80127ce: f02b 4300 bic.w r3, fp, #2147483648 @ 0x80000000
|
|
80127d2: 9a08 ldr r2, [sp, #32]
|
|
80127d4: 0d1b lsrs r3, r3, #20
|
|
80127d6: 051b lsls r3, r3, #20
|
|
80127d8: 2a00 cmp r2, #0
|
|
80127da: d06a beq.n 80128b2 <_strtod_l+0x8fa>
|
|
80127dc: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000
|
|
80127e0: d867 bhi.n 80128b2 <_strtod_l+0x8fa>
|
|
80127e2: f1b3 7f5c cmp.w r3, #57671680 @ 0x3700000
|
|
80127e6: f67f ae9d bls.w 8012524 <_strtod_l+0x56c>
|
|
80127ea: 4b0a ldr r3, [pc, #40] @ (8012814 <_strtod_l+0x85c>)
|
|
80127ec: 4650 mov r0, sl
|
|
80127ee: 4659 mov r1, fp
|
|
80127f0: 2200 movs r2, #0
|
|
80127f2: f7ed ff01 bl 80005f8 <__aeabi_dmul>
|
|
80127f6: 4b08 ldr r3, [pc, #32] @ (8012818 <_strtod_l+0x860>)
|
|
80127f8: 400b ands r3, r1
|
|
80127fa: 4682 mov sl, r0
|
|
80127fc: 468b mov fp, r1
|
|
80127fe: 2b00 cmp r3, #0
|
|
8012800: f47f ae08 bne.w 8012414 <_strtod_l+0x45c>
|
|
8012804: 9a05 ldr r2, [sp, #20]
|
|
8012806: 2322 movs r3, #34 @ 0x22
|
|
8012808: 6013 str r3, [r2, #0]
|
|
801280a: e603 b.n 8012414 <_strtod_l+0x45c>
|
|
801280c: 08014ae0 .word 0x08014ae0
|
|
8012810: fffffc02 .word 0xfffffc02
|
|
8012814: 39500000 .word 0x39500000
|
|
8012818: 7ff00000 .word 0x7ff00000
|
|
801281c: f8cd b028 str.w fp, [sp, #40] @ 0x28
|
|
8012820: d165 bne.n 80128ee <_strtod_l+0x936>
|
|
8012822: 9a0f ldr r2, [sp, #60] @ 0x3c
|
|
8012824: f3cb 0313 ubfx r3, fp, #0, #20
|
|
8012828: b35a cbz r2, 8012882 <_strtod_l+0x8ca>
|
|
801282a: 4a9f ldr r2, [pc, #636] @ (8012aa8 <_strtod_l+0xaf0>)
|
|
801282c: 4293 cmp r3, r2
|
|
801282e: d12b bne.n 8012888 <_strtod_l+0x8d0>
|
|
8012830: 9b08 ldr r3, [sp, #32]
|
|
8012832: 4651 mov r1, sl
|
|
8012834: b303 cbz r3, 8012878 <_strtod_l+0x8c0>
|
|
8012836: 4b9d ldr r3, [pc, #628] @ (8012aac <_strtod_l+0xaf4>)
|
|
8012838: 465a mov r2, fp
|
|
801283a: 4013 ands r3, r2
|
|
801283c: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000
|
|
8012840: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8012844: d81b bhi.n 801287e <_strtod_l+0x8c6>
|
|
8012846: 0d1b lsrs r3, r3, #20
|
|
8012848: f1c3 036b rsb r3, r3, #107 @ 0x6b
|
|
801284c: fa02 f303 lsl.w r3, r2, r3
|
|
8012850: 4299 cmp r1, r3
|
|
8012852: d119 bne.n 8012888 <_strtod_l+0x8d0>
|
|
8012854: 4b96 ldr r3, [pc, #600] @ (8012ab0 <_strtod_l+0xaf8>)
|
|
8012856: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
8012858: 429a cmp r2, r3
|
|
801285a: d102 bne.n 8012862 <_strtod_l+0x8aa>
|
|
801285c: 3101 adds r1, #1
|
|
801285e: f43f adce beq.w 80123fe <_strtod_l+0x446>
|
|
8012862: 4b92 ldr r3, [pc, #584] @ (8012aac <_strtod_l+0xaf4>)
|
|
8012864: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
8012866: 401a ands r2, r3
|
|
8012868: f502 1b80 add.w fp, r2, #1048576 @ 0x100000
|
|
801286c: f04f 0a00 mov.w sl, #0
|
|
8012870: 9b08 ldr r3, [sp, #32]
|
|
8012872: 2b00 cmp r3, #0
|
|
8012874: d1b9 bne.n 80127ea <_strtod_l+0x832>
|
|
8012876: e5cd b.n 8012414 <_strtod_l+0x45c>
|
|
8012878: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
801287c: e7e8 b.n 8012850 <_strtod_l+0x898>
|
|
801287e: 4613 mov r3, r2
|
|
8012880: e7e6 b.n 8012850 <_strtod_l+0x898>
|
|
8012882: ea53 030a orrs.w r3, r3, sl
|
|
8012886: d0a2 beq.n 80127ce <_strtod_l+0x816>
|
|
8012888: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
801288a: b1db cbz r3, 80128c4 <_strtod_l+0x90c>
|
|
801288c: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
801288e: 4213 tst r3, r2
|
|
8012890: d0ee beq.n 8012870 <_strtod_l+0x8b8>
|
|
8012892: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
8012894: 9a08 ldr r2, [sp, #32]
|
|
8012896: 4650 mov r0, sl
|
|
8012898: 4659 mov r1, fp
|
|
801289a: b1bb cbz r3, 80128cc <_strtod_l+0x914>
|
|
801289c: f7ff fb6e bl 8011f7c <sulp>
|
|
80128a0: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30
|
|
80128a4: ec53 2b10 vmov r2, r3, d0
|
|
80128a8: f7ed fcf0 bl 800028c <__adddf3>
|
|
80128ac: 4682 mov sl, r0
|
|
80128ae: 468b mov fp, r1
|
|
80128b0: e7de b.n 8012870 <_strtod_l+0x8b8>
|
|
80128b2: f5a3 1380 sub.w r3, r3, #1048576 @ 0x100000
|
|
80128b6: ea6f 5b13 mvn.w fp, r3, lsr #20
|
|
80128ba: ea6f 5b0b mvn.w fp, fp, lsl #20
|
|
80128be: f04f 3aff mov.w sl, #4294967295 @ 0xffffffff
|
|
80128c2: e7d5 b.n 8012870 <_strtod_l+0x8b8>
|
|
80128c4: 9b13 ldr r3, [sp, #76] @ 0x4c
|
|
80128c6: ea13 0f0a tst.w r3, sl
|
|
80128ca: e7e1 b.n 8012890 <_strtod_l+0x8d8>
|
|
80128cc: f7ff fb56 bl 8011f7c <sulp>
|
|
80128d0: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30
|
|
80128d4: ec53 2b10 vmov r2, r3, d0
|
|
80128d8: f7ed fcd6 bl 8000288 <__aeabi_dsub>
|
|
80128dc: 2200 movs r2, #0
|
|
80128de: 2300 movs r3, #0
|
|
80128e0: 4682 mov sl, r0
|
|
80128e2: 468b mov fp, r1
|
|
80128e4: f7ee f8f0 bl 8000ac8 <__aeabi_dcmpeq>
|
|
80128e8: 2800 cmp r0, #0
|
|
80128ea: d0c1 beq.n 8012870 <_strtod_l+0x8b8>
|
|
80128ec: e61a b.n 8012524 <_strtod_l+0x56c>
|
|
80128ee: 4641 mov r1, r8
|
|
80128f0: 4620 mov r0, r4
|
|
80128f2: f7ff facd bl 8011e90 <__ratio>
|
|
80128f6: ec57 6b10 vmov r6, r7, d0
|
|
80128fa: 2200 movs r2, #0
|
|
80128fc: f04f 4380 mov.w r3, #1073741824 @ 0x40000000
|
|
8012900: 4630 mov r0, r6
|
|
8012902: 4639 mov r1, r7
|
|
8012904: f7ee f8f4 bl 8000af0 <__aeabi_dcmple>
|
|
8012908: 2800 cmp r0, #0
|
|
801290a: d06f beq.n 80129ec <_strtod_l+0xa34>
|
|
801290c: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801290e: 2b00 cmp r3, #0
|
|
8012910: d17a bne.n 8012a08 <_strtod_l+0xa50>
|
|
8012912: f1ba 0f00 cmp.w sl, #0
|
|
8012916: d158 bne.n 80129ca <_strtod_l+0xa12>
|
|
8012918: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801291a: f3c3 0313 ubfx r3, r3, #0, #20
|
|
801291e: 2b00 cmp r3, #0
|
|
8012920: d15a bne.n 80129d8 <_strtod_l+0xa20>
|
|
8012922: 4b64 ldr r3, [pc, #400] @ (8012ab4 <_strtod_l+0xafc>)
|
|
8012924: 2200 movs r2, #0
|
|
8012926: 4630 mov r0, r6
|
|
8012928: 4639 mov r1, r7
|
|
801292a: f7ee f8d7 bl 8000adc <__aeabi_dcmplt>
|
|
801292e: 2800 cmp r0, #0
|
|
8012930: d159 bne.n 80129e6 <_strtod_l+0xa2e>
|
|
8012932: 4630 mov r0, r6
|
|
8012934: 4639 mov r1, r7
|
|
8012936: 4b60 ldr r3, [pc, #384] @ (8012ab8 <_strtod_l+0xb00>)
|
|
8012938: 2200 movs r2, #0
|
|
801293a: f7ed fe5d bl 80005f8 <__aeabi_dmul>
|
|
801293e: 4606 mov r6, r0
|
|
8012940: 460f mov r7, r1
|
|
8012942: f107 4300 add.w r3, r7, #2147483648 @ 0x80000000
|
|
8012946: 9606 str r6, [sp, #24]
|
|
8012948: 9307 str r3, [sp, #28]
|
|
801294a: e9dd 2306 ldrd r2, r3, [sp, #24]
|
|
801294e: 4d57 ldr r5, [pc, #348] @ (8012aac <_strtod_l+0xaf4>)
|
|
8012950: e9cd 2310 strd r2, r3, [sp, #64] @ 0x40
|
|
8012954: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
8012956: 401d ands r5, r3
|
|
8012958: 4b58 ldr r3, [pc, #352] @ (8012abc <_strtod_l+0xb04>)
|
|
801295a: 429d cmp r5, r3
|
|
801295c: f040 80b2 bne.w 8012ac4 <_strtod_l+0xb0c>
|
|
8012960: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
8012962: f1a3 7b54 sub.w fp, r3, #55574528 @ 0x3500000
|
|
8012966: ec4b ab10 vmov d0, sl, fp
|
|
801296a: f7ff f9c9 bl 8011d00 <__ulp>
|
|
801296e: e9dd 2306 ldrd r2, r3, [sp, #24]
|
|
8012972: ec51 0b10 vmov r0, r1, d0
|
|
8012976: f7ed fe3f bl 80005f8 <__aeabi_dmul>
|
|
801297a: 4652 mov r2, sl
|
|
801297c: 465b mov r3, fp
|
|
801297e: f7ed fc85 bl 800028c <__adddf3>
|
|
8012982: 460b mov r3, r1
|
|
8012984: 4949 ldr r1, [pc, #292] @ (8012aac <_strtod_l+0xaf4>)
|
|
8012986: 4a4e ldr r2, [pc, #312] @ (8012ac0 <_strtod_l+0xb08>)
|
|
8012988: 4019 ands r1, r3
|
|
801298a: 4291 cmp r1, r2
|
|
801298c: 4682 mov sl, r0
|
|
801298e: d942 bls.n 8012a16 <_strtod_l+0xa5e>
|
|
8012990: 9a0d ldr r2, [sp, #52] @ 0x34
|
|
8012992: 4b47 ldr r3, [pc, #284] @ (8012ab0 <_strtod_l+0xaf8>)
|
|
8012994: 429a cmp r2, r3
|
|
8012996: d103 bne.n 80129a0 <_strtod_l+0x9e8>
|
|
8012998: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
801299a: 3301 adds r3, #1
|
|
801299c: f43f ad2f beq.w 80123fe <_strtod_l+0x446>
|
|
80129a0: f8df b10c ldr.w fp, [pc, #268] @ 8012ab0 <_strtod_l+0xaf8>
|
|
80129a4: f04f 3aff mov.w sl, #4294967295 @ 0xffffffff
|
|
80129a8: 991a ldr r1, [sp, #104] @ 0x68
|
|
80129aa: 9805 ldr r0, [sp, #20]
|
|
80129ac: f7fe fe7c bl 80116a8 <_Bfree>
|
|
80129b0: 9805 ldr r0, [sp, #20]
|
|
80129b2: 4649 mov r1, r9
|
|
80129b4: f7fe fe78 bl 80116a8 <_Bfree>
|
|
80129b8: 9805 ldr r0, [sp, #20]
|
|
80129ba: 4641 mov r1, r8
|
|
80129bc: f7fe fe74 bl 80116a8 <_Bfree>
|
|
80129c0: 9805 ldr r0, [sp, #20]
|
|
80129c2: 4621 mov r1, r4
|
|
80129c4: f7fe fe70 bl 80116a8 <_Bfree>
|
|
80129c8: e619 b.n 80125fe <_strtod_l+0x646>
|
|
80129ca: f1ba 0f01 cmp.w sl, #1
|
|
80129ce: d103 bne.n 80129d8 <_strtod_l+0xa20>
|
|
80129d0: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
80129d2: 2b00 cmp r3, #0
|
|
80129d4: f43f ada6 beq.w 8012524 <_strtod_l+0x56c>
|
|
80129d8: ed9f 7b2b vldr d7, [pc, #172] @ 8012a88 <_strtod_l+0xad0>
|
|
80129dc: 4f35 ldr r7, [pc, #212] @ (8012ab4 <_strtod_l+0xafc>)
|
|
80129de: ed8d 7b06 vstr d7, [sp, #24]
|
|
80129e2: 2600 movs r6, #0
|
|
80129e4: e7b1 b.n 801294a <_strtod_l+0x992>
|
|
80129e6: 4f34 ldr r7, [pc, #208] @ (8012ab8 <_strtod_l+0xb00>)
|
|
80129e8: 2600 movs r6, #0
|
|
80129ea: e7aa b.n 8012942 <_strtod_l+0x98a>
|
|
80129ec: 4b32 ldr r3, [pc, #200] @ (8012ab8 <_strtod_l+0xb00>)
|
|
80129ee: 4630 mov r0, r6
|
|
80129f0: 4639 mov r1, r7
|
|
80129f2: 2200 movs r2, #0
|
|
80129f4: f7ed fe00 bl 80005f8 <__aeabi_dmul>
|
|
80129f8: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
80129fa: 4606 mov r6, r0
|
|
80129fc: 460f mov r7, r1
|
|
80129fe: 2b00 cmp r3, #0
|
|
8012a00: d09f beq.n 8012942 <_strtod_l+0x98a>
|
|
8012a02: e9cd 6706 strd r6, r7, [sp, #24]
|
|
8012a06: e7a0 b.n 801294a <_strtod_l+0x992>
|
|
8012a08: ed9f 7b21 vldr d7, [pc, #132] @ 8012a90 <_strtod_l+0xad8>
|
|
8012a0c: ed8d 7b06 vstr d7, [sp, #24]
|
|
8012a10: ec57 6b17 vmov r6, r7, d7
|
|
8012a14: e799 b.n 801294a <_strtod_l+0x992>
|
|
8012a16: f103 7b54 add.w fp, r3, #55574528 @ 0x3500000
|
|
8012a1a: 9b08 ldr r3, [sp, #32]
|
|
8012a1c: f8cd b028 str.w fp, [sp, #40] @ 0x28
|
|
8012a20: 2b00 cmp r3, #0
|
|
8012a22: d1c1 bne.n 80129a8 <_strtod_l+0x9f0>
|
|
8012a24: f02b 4300 bic.w r3, fp, #2147483648 @ 0x80000000
|
|
8012a28: 0d1b lsrs r3, r3, #20
|
|
8012a2a: 051b lsls r3, r3, #20
|
|
8012a2c: 429d cmp r5, r3
|
|
8012a2e: d1bb bne.n 80129a8 <_strtod_l+0x9f0>
|
|
8012a30: 4630 mov r0, r6
|
|
8012a32: 4639 mov r1, r7
|
|
8012a34: f7ee f940 bl 8000cb8 <__aeabi_d2lz>
|
|
8012a38: f7ed fdb0 bl 800059c <__aeabi_l2d>
|
|
8012a3c: 4602 mov r2, r0
|
|
8012a3e: 460b mov r3, r1
|
|
8012a40: 4630 mov r0, r6
|
|
8012a42: 4639 mov r1, r7
|
|
8012a44: f7ed fc20 bl 8000288 <__aeabi_dsub>
|
|
8012a48: 460b mov r3, r1
|
|
8012a4a: 4602 mov r2, r0
|
|
8012a4c: e9cd 230c strd r2, r3, [sp, #48] @ 0x30
|
|
8012a50: f3cb 0613 ubfx r6, fp, #0, #20
|
|
8012a54: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
8012a56: ea46 060a orr.w r6, r6, sl
|
|
8012a5a: 431e orrs r6, r3
|
|
8012a5c: d06f beq.n 8012b3e <_strtod_l+0xb86>
|
|
8012a5e: a30e add r3, pc, #56 @ (adr r3, 8012a98 <_strtod_l+0xae0>)
|
|
8012a60: e9d3 2300 ldrd r2, r3, [r3]
|
|
8012a64: f7ee f83a bl 8000adc <__aeabi_dcmplt>
|
|
8012a68: 2800 cmp r0, #0
|
|
8012a6a: f47f acd3 bne.w 8012414 <_strtod_l+0x45c>
|
|
8012a6e: a30c add r3, pc, #48 @ (adr r3, 8012aa0 <_strtod_l+0xae8>)
|
|
8012a70: e9d3 2300 ldrd r2, r3, [r3]
|
|
8012a74: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30
|
|
8012a78: f7ee f84e bl 8000b18 <__aeabi_dcmpgt>
|
|
8012a7c: 2800 cmp r0, #0
|
|
8012a7e: d093 beq.n 80129a8 <_strtod_l+0x9f0>
|
|
8012a80: e4c8 b.n 8012414 <_strtod_l+0x45c>
|
|
8012a82: bf00 nop
|
|
8012a84: f3af 8000 nop.w
|
|
8012a88: 00000000 .word 0x00000000
|
|
8012a8c: bff00000 .word 0xbff00000
|
|
8012a90: 00000000 .word 0x00000000
|
|
8012a94: 3ff00000 .word 0x3ff00000
|
|
8012a98: 94a03595 .word 0x94a03595
|
|
8012a9c: 3fdfffff .word 0x3fdfffff
|
|
8012aa0: 35afe535 .word 0x35afe535
|
|
8012aa4: 3fe00000 .word 0x3fe00000
|
|
8012aa8: 000fffff .word 0x000fffff
|
|
8012aac: 7ff00000 .word 0x7ff00000
|
|
8012ab0: 7fefffff .word 0x7fefffff
|
|
8012ab4: 3ff00000 .word 0x3ff00000
|
|
8012ab8: 3fe00000 .word 0x3fe00000
|
|
8012abc: 7fe00000 .word 0x7fe00000
|
|
8012ac0: 7c9fffff .word 0x7c9fffff
|
|
8012ac4: 9b08 ldr r3, [sp, #32]
|
|
8012ac6: b323 cbz r3, 8012b12 <_strtod_l+0xb5a>
|
|
8012ac8: f1b5 6fd4 cmp.w r5, #111149056 @ 0x6a00000
|
|
8012acc: d821 bhi.n 8012b12 <_strtod_l+0xb5a>
|
|
8012ace: a328 add r3, pc, #160 @ (adr r3, 8012b70 <_strtod_l+0xbb8>)
|
|
8012ad0: e9d3 2300 ldrd r2, r3, [r3]
|
|
8012ad4: 4630 mov r0, r6
|
|
8012ad6: 4639 mov r1, r7
|
|
8012ad8: f7ee f80a bl 8000af0 <__aeabi_dcmple>
|
|
8012adc: b1a0 cbz r0, 8012b08 <_strtod_l+0xb50>
|
|
8012ade: 4639 mov r1, r7
|
|
8012ae0: 4630 mov r0, r6
|
|
8012ae2: f7ee f861 bl 8000ba8 <__aeabi_d2uiz>
|
|
8012ae6: 2801 cmp r0, #1
|
|
8012ae8: bf38 it cc
|
|
8012aea: 2001 movcc r0, #1
|
|
8012aec: f7ed fd0a bl 8000504 <__aeabi_ui2d>
|
|
8012af0: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
8012af2: 4606 mov r6, r0
|
|
8012af4: 460f mov r7, r1
|
|
8012af6: b9fb cbnz r3, 8012b38 <_strtod_l+0xb80>
|
|
8012af8: f101 4300 add.w r3, r1, #2147483648 @ 0x80000000
|
|
8012afc: 9014 str r0, [sp, #80] @ 0x50
|
|
8012afe: 9315 str r3, [sp, #84] @ 0x54
|
|
8012b00: e9dd 2314 ldrd r2, r3, [sp, #80] @ 0x50
|
|
8012b04: e9cd 2310 strd r2, r3, [sp, #64] @ 0x40
|
|
8012b08: 9b11 ldr r3, [sp, #68] @ 0x44
|
|
8012b0a: f103 63d6 add.w r3, r3, #112197632 @ 0x6b00000
|
|
8012b0e: 1b5b subs r3, r3, r5
|
|
8012b10: 9311 str r3, [sp, #68] @ 0x44
|
|
8012b12: ed9d 0b0c vldr d0, [sp, #48] @ 0x30
|
|
8012b16: e9dd ab10 ldrd sl, fp, [sp, #64] @ 0x40
|
|
8012b1a: f7ff f8f1 bl 8011d00 <__ulp>
|
|
8012b1e: 4650 mov r0, sl
|
|
8012b20: ec53 2b10 vmov r2, r3, d0
|
|
8012b24: 4659 mov r1, fp
|
|
8012b26: f7ed fd67 bl 80005f8 <__aeabi_dmul>
|
|
8012b2a: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30
|
|
8012b2e: f7ed fbad bl 800028c <__adddf3>
|
|
8012b32: 4682 mov sl, r0
|
|
8012b34: 468b mov fp, r1
|
|
8012b36: e770 b.n 8012a1a <_strtod_l+0xa62>
|
|
8012b38: e9cd 6714 strd r6, r7, [sp, #80] @ 0x50
|
|
8012b3c: e7e0 b.n 8012b00 <_strtod_l+0xb48>
|
|
8012b3e: a30e add r3, pc, #56 @ (adr r3, 8012b78 <_strtod_l+0xbc0>)
|
|
8012b40: e9d3 2300 ldrd r2, r3, [r3]
|
|
8012b44: f7ed ffca bl 8000adc <__aeabi_dcmplt>
|
|
8012b48: e798 b.n 8012a7c <_strtod_l+0xac4>
|
|
8012b4a: 2300 movs r3, #0
|
|
8012b4c: 930e str r3, [sp, #56] @ 0x38
|
|
8012b4e: 9a17 ldr r2, [sp, #92] @ 0x5c
|
|
8012b50: 9b19 ldr r3, [sp, #100] @ 0x64
|
|
8012b52: 6013 str r3, [r2, #0]
|
|
8012b54: f7ff ba6d b.w 8012032 <_strtod_l+0x7a>
|
|
8012b58: 2a65 cmp r2, #101 @ 0x65
|
|
8012b5a: f43f ab68 beq.w 801222e <_strtod_l+0x276>
|
|
8012b5e: 2a45 cmp r2, #69 @ 0x45
|
|
8012b60: f43f ab65 beq.w 801222e <_strtod_l+0x276>
|
|
8012b64: 2301 movs r3, #1
|
|
8012b66: f7ff bba0 b.w 80122aa <_strtod_l+0x2f2>
|
|
8012b6a: bf00 nop
|
|
8012b6c: f3af 8000 nop.w
|
|
8012b70: ffc00000 .word 0xffc00000
|
|
8012b74: 41dfffff .word 0x41dfffff
|
|
8012b78: 94a03595 .word 0x94a03595
|
|
8012b7c: 3fcfffff .word 0x3fcfffff
|
|
|
|
08012b80 <_strtod_r>:
|
|
8012b80: 4b01 ldr r3, [pc, #4] @ (8012b88 <_strtod_r+0x8>)
|
|
8012b82: f7ff ba19 b.w 8011fb8 <_strtod_l>
|
|
8012b86: bf00 nop
|
|
8012b88: 20000130 .word 0x20000130
|
|
|
|
08012b8c <_strtol_l.isra.0>:
|
|
8012b8c: 2b24 cmp r3, #36 @ 0x24
|
|
8012b8e: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8012b92: 4686 mov lr, r0
|
|
8012b94: 4690 mov r8, r2
|
|
8012b96: d801 bhi.n 8012b9c <_strtol_l.isra.0+0x10>
|
|
8012b98: 2b01 cmp r3, #1
|
|
8012b9a: d106 bne.n 8012baa <_strtol_l.isra.0+0x1e>
|
|
8012b9c: f7fd fd8c bl 80106b8 <__errno>
|
|
8012ba0: 2316 movs r3, #22
|
|
8012ba2: 6003 str r3, [r0, #0]
|
|
8012ba4: 2000 movs r0, #0
|
|
8012ba6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8012baa: 4834 ldr r0, [pc, #208] @ (8012c7c <_strtol_l.isra.0+0xf0>)
|
|
8012bac: 460d mov r5, r1
|
|
8012bae: 462a mov r2, r5
|
|
8012bb0: f815 4b01 ldrb.w r4, [r5], #1
|
|
8012bb4: 5d06 ldrb r6, [r0, r4]
|
|
8012bb6: f016 0608 ands.w r6, r6, #8
|
|
8012bba: d1f8 bne.n 8012bae <_strtol_l.isra.0+0x22>
|
|
8012bbc: 2c2d cmp r4, #45 @ 0x2d
|
|
8012bbe: d110 bne.n 8012be2 <_strtol_l.isra.0+0x56>
|
|
8012bc0: 782c ldrb r4, [r5, #0]
|
|
8012bc2: 2601 movs r6, #1
|
|
8012bc4: 1c95 adds r5, r2, #2
|
|
8012bc6: f033 0210 bics.w r2, r3, #16
|
|
8012bca: d115 bne.n 8012bf8 <_strtol_l.isra.0+0x6c>
|
|
8012bcc: 2c30 cmp r4, #48 @ 0x30
|
|
8012bce: d10d bne.n 8012bec <_strtol_l.isra.0+0x60>
|
|
8012bd0: 782a ldrb r2, [r5, #0]
|
|
8012bd2: f002 02df and.w r2, r2, #223 @ 0xdf
|
|
8012bd6: 2a58 cmp r2, #88 @ 0x58
|
|
8012bd8: d108 bne.n 8012bec <_strtol_l.isra.0+0x60>
|
|
8012bda: 786c ldrb r4, [r5, #1]
|
|
8012bdc: 3502 adds r5, #2
|
|
8012bde: 2310 movs r3, #16
|
|
8012be0: e00a b.n 8012bf8 <_strtol_l.isra.0+0x6c>
|
|
8012be2: 2c2b cmp r4, #43 @ 0x2b
|
|
8012be4: bf04 itt eq
|
|
8012be6: 782c ldrbeq r4, [r5, #0]
|
|
8012be8: 1c95 addeq r5, r2, #2
|
|
8012bea: e7ec b.n 8012bc6 <_strtol_l.isra.0+0x3a>
|
|
8012bec: 2b00 cmp r3, #0
|
|
8012bee: d1f6 bne.n 8012bde <_strtol_l.isra.0+0x52>
|
|
8012bf0: 2c30 cmp r4, #48 @ 0x30
|
|
8012bf2: bf14 ite ne
|
|
8012bf4: 230a movne r3, #10
|
|
8012bf6: 2308 moveq r3, #8
|
|
8012bf8: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000
|
|
8012bfc: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff
|
|
8012c00: 2200 movs r2, #0
|
|
8012c02: fbbc f9f3 udiv r9, ip, r3
|
|
8012c06: 4610 mov r0, r2
|
|
8012c08: fb03 ca19 mls sl, r3, r9, ip
|
|
8012c0c: f1a4 0730 sub.w r7, r4, #48 @ 0x30
|
|
8012c10: 2f09 cmp r7, #9
|
|
8012c12: d80f bhi.n 8012c34 <_strtol_l.isra.0+0xa8>
|
|
8012c14: 463c mov r4, r7
|
|
8012c16: 42a3 cmp r3, r4
|
|
8012c18: dd1b ble.n 8012c52 <_strtol_l.isra.0+0xc6>
|
|
8012c1a: 1c57 adds r7, r2, #1
|
|
8012c1c: d007 beq.n 8012c2e <_strtol_l.isra.0+0xa2>
|
|
8012c1e: 4581 cmp r9, r0
|
|
8012c20: d314 bcc.n 8012c4c <_strtol_l.isra.0+0xc0>
|
|
8012c22: d101 bne.n 8012c28 <_strtol_l.isra.0+0x9c>
|
|
8012c24: 45a2 cmp sl, r4
|
|
8012c26: db11 blt.n 8012c4c <_strtol_l.isra.0+0xc0>
|
|
8012c28: fb00 4003 mla r0, r0, r3, r4
|
|
8012c2c: 2201 movs r2, #1
|
|
8012c2e: f815 4b01 ldrb.w r4, [r5], #1
|
|
8012c32: e7eb b.n 8012c0c <_strtol_l.isra.0+0x80>
|
|
8012c34: f1a4 0741 sub.w r7, r4, #65 @ 0x41
|
|
8012c38: 2f19 cmp r7, #25
|
|
8012c3a: d801 bhi.n 8012c40 <_strtol_l.isra.0+0xb4>
|
|
8012c3c: 3c37 subs r4, #55 @ 0x37
|
|
8012c3e: e7ea b.n 8012c16 <_strtol_l.isra.0+0x8a>
|
|
8012c40: f1a4 0761 sub.w r7, r4, #97 @ 0x61
|
|
8012c44: 2f19 cmp r7, #25
|
|
8012c46: d804 bhi.n 8012c52 <_strtol_l.isra.0+0xc6>
|
|
8012c48: 3c57 subs r4, #87 @ 0x57
|
|
8012c4a: e7e4 b.n 8012c16 <_strtol_l.isra.0+0x8a>
|
|
8012c4c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8012c50: e7ed b.n 8012c2e <_strtol_l.isra.0+0xa2>
|
|
8012c52: 1c53 adds r3, r2, #1
|
|
8012c54: d108 bne.n 8012c68 <_strtol_l.isra.0+0xdc>
|
|
8012c56: 2322 movs r3, #34 @ 0x22
|
|
8012c58: f8ce 3000 str.w r3, [lr]
|
|
8012c5c: 4660 mov r0, ip
|
|
8012c5e: f1b8 0f00 cmp.w r8, #0
|
|
8012c62: d0a0 beq.n 8012ba6 <_strtol_l.isra.0+0x1a>
|
|
8012c64: 1e69 subs r1, r5, #1
|
|
8012c66: e006 b.n 8012c76 <_strtol_l.isra.0+0xea>
|
|
8012c68: b106 cbz r6, 8012c6c <_strtol_l.isra.0+0xe0>
|
|
8012c6a: 4240 negs r0, r0
|
|
8012c6c: f1b8 0f00 cmp.w r8, #0
|
|
8012c70: d099 beq.n 8012ba6 <_strtol_l.isra.0+0x1a>
|
|
8012c72: 2a00 cmp r2, #0
|
|
8012c74: d1f6 bne.n 8012c64 <_strtol_l.isra.0+0xd8>
|
|
8012c76: f8c8 1000 str.w r1, [r8]
|
|
8012c7a: e794 b.n 8012ba6 <_strtol_l.isra.0+0x1a>
|
|
8012c7c: 08014b09 .word 0x08014b09
|
|
|
|
08012c80 <_strtol_r>:
|
|
8012c80: f7ff bf84 b.w 8012b8c <_strtol_l.isra.0>
|
|
|
|
08012c84 <__ssputs_r>:
|
|
8012c84: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8012c88: 688e ldr r6, [r1, #8]
|
|
8012c8a: 461f mov r7, r3
|
|
8012c8c: 42be cmp r6, r7
|
|
8012c8e: 680b ldr r3, [r1, #0]
|
|
8012c90: 4682 mov sl, r0
|
|
8012c92: 460c mov r4, r1
|
|
8012c94: 4690 mov r8, r2
|
|
8012c96: d82d bhi.n 8012cf4 <__ssputs_r+0x70>
|
|
8012c98: f9b1 200c ldrsh.w r2, [r1, #12]
|
|
8012c9c: f412 6f90 tst.w r2, #1152 @ 0x480
|
|
8012ca0: d026 beq.n 8012cf0 <__ssputs_r+0x6c>
|
|
8012ca2: 6965 ldr r5, [r4, #20]
|
|
8012ca4: 6909 ldr r1, [r1, #16]
|
|
8012ca6: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
8012caa: eba3 0901 sub.w r9, r3, r1
|
|
8012cae: eb05 75d5 add.w r5, r5, r5, lsr #31
|
|
8012cb2: 1c7b adds r3, r7, #1
|
|
8012cb4: 444b add r3, r9
|
|
8012cb6: 106d asrs r5, r5, #1
|
|
8012cb8: 429d cmp r5, r3
|
|
8012cba: bf38 it cc
|
|
8012cbc: 461d movcc r5, r3
|
|
8012cbe: 0553 lsls r3, r2, #21
|
|
8012cc0: d527 bpl.n 8012d12 <__ssputs_r+0x8e>
|
|
8012cc2: 4629 mov r1, r5
|
|
8012cc4: f7fe fc24 bl 8011510 <_malloc_r>
|
|
8012cc8: 4606 mov r6, r0
|
|
8012cca: b360 cbz r0, 8012d26 <__ssputs_r+0xa2>
|
|
8012ccc: 6921 ldr r1, [r4, #16]
|
|
8012cce: 464a mov r2, r9
|
|
8012cd0: f7fd fd1f bl 8010712 <memcpy>
|
|
8012cd4: 89a3 ldrh r3, [r4, #12]
|
|
8012cd6: f423 6390 bic.w r3, r3, #1152 @ 0x480
|
|
8012cda: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8012cde: 81a3 strh r3, [r4, #12]
|
|
8012ce0: 6126 str r6, [r4, #16]
|
|
8012ce2: 6165 str r5, [r4, #20]
|
|
8012ce4: 444e add r6, r9
|
|
8012ce6: eba5 0509 sub.w r5, r5, r9
|
|
8012cea: 6026 str r6, [r4, #0]
|
|
8012cec: 60a5 str r5, [r4, #8]
|
|
8012cee: 463e mov r6, r7
|
|
8012cf0: 42be cmp r6, r7
|
|
8012cf2: d900 bls.n 8012cf6 <__ssputs_r+0x72>
|
|
8012cf4: 463e mov r6, r7
|
|
8012cf6: 6820 ldr r0, [r4, #0]
|
|
8012cf8: 4632 mov r2, r6
|
|
8012cfa: 4641 mov r1, r8
|
|
8012cfc: f000 fb7c bl 80133f8 <memmove>
|
|
8012d00: 68a3 ldr r3, [r4, #8]
|
|
8012d02: 1b9b subs r3, r3, r6
|
|
8012d04: 60a3 str r3, [r4, #8]
|
|
8012d06: 6823 ldr r3, [r4, #0]
|
|
8012d08: 4433 add r3, r6
|
|
8012d0a: 6023 str r3, [r4, #0]
|
|
8012d0c: 2000 movs r0, #0
|
|
8012d0e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8012d12: 462a mov r2, r5
|
|
8012d14: f000 ff29 bl 8013b6a <_realloc_r>
|
|
8012d18: 4606 mov r6, r0
|
|
8012d1a: 2800 cmp r0, #0
|
|
8012d1c: d1e0 bne.n 8012ce0 <__ssputs_r+0x5c>
|
|
8012d1e: 6921 ldr r1, [r4, #16]
|
|
8012d20: 4650 mov r0, sl
|
|
8012d22: f7fe fb81 bl 8011428 <_free_r>
|
|
8012d26: 230c movs r3, #12
|
|
8012d28: f8ca 3000 str.w r3, [sl]
|
|
8012d2c: 89a3 ldrh r3, [r4, #12]
|
|
8012d2e: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8012d32: 81a3 strh r3, [r4, #12]
|
|
8012d34: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8012d38: e7e9 b.n 8012d0e <__ssputs_r+0x8a>
|
|
...
|
|
|
|
08012d3c <_svfiprintf_r>:
|
|
8012d3c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8012d40: 4698 mov r8, r3
|
|
8012d42: 898b ldrh r3, [r1, #12]
|
|
8012d44: 061b lsls r3, r3, #24
|
|
8012d46: b09d sub sp, #116 @ 0x74
|
|
8012d48: 4607 mov r7, r0
|
|
8012d4a: 460d mov r5, r1
|
|
8012d4c: 4614 mov r4, r2
|
|
8012d4e: d510 bpl.n 8012d72 <_svfiprintf_r+0x36>
|
|
8012d50: 690b ldr r3, [r1, #16]
|
|
8012d52: b973 cbnz r3, 8012d72 <_svfiprintf_r+0x36>
|
|
8012d54: 2140 movs r1, #64 @ 0x40
|
|
8012d56: f7fe fbdb bl 8011510 <_malloc_r>
|
|
8012d5a: 6028 str r0, [r5, #0]
|
|
8012d5c: 6128 str r0, [r5, #16]
|
|
8012d5e: b930 cbnz r0, 8012d6e <_svfiprintf_r+0x32>
|
|
8012d60: 230c movs r3, #12
|
|
8012d62: 603b str r3, [r7, #0]
|
|
8012d64: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8012d68: b01d add sp, #116 @ 0x74
|
|
8012d6a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8012d6e: 2340 movs r3, #64 @ 0x40
|
|
8012d70: 616b str r3, [r5, #20]
|
|
8012d72: 2300 movs r3, #0
|
|
8012d74: 9309 str r3, [sp, #36] @ 0x24
|
|
8012d76: 2320 movs r3, #32
|
|
8012d78: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
8012d7c: f8cd 800c str.w r8, [sp, #12]
|
|
8012d80: 2330 movs r3, #48 @ 0x30
|
|
8012d82: f8df 819c ldr.w r8, [pc, #412] @ 8012f20 <_svfiprintf_r+0x1e4>
|
|
8012d86: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
8012d8a: f04f 0901 mov.w r9, #1
|
|
8012d8e: 4623 mov r3, r4
|
|
8012d90: 469a mov sl, r3
|
|
8012d92: f813 2b01 ldrb.w r2, [r3], #1
|
|
8012d96: b10a cbz r2, 8012d9c <_svfiprintf_r+0x60>
|
|
8012d98: 2a25 cmp r2, #37 @ 0x25
|
|
8012d9a: d1f9 bne.n 8012d90 <_svfiprintf_r+0x54>
|
|
8012d9c: ebba 0b04 subs.w fp, sl, r4
|
|
8012da0: d00b beq.n 8012dba <_svfiprintf_r+0x7e>
|
|
8012da2: 465b mov r3, fp
|
|
8012da4: 4622 mov r2, r4
|
|
8012da6: 4629 mov r1, r5
|
|
8012da8: 4638 mov r0, r7
|
|
8012daa: f7ff ff6b bl 8012c84 <__ssputs_r>
|
|
8012dae: 3001 adds r0, #1
|
|
8012db0: f000 80a7 beq.w 8012f02 <_svfiprintf_r+0x1c6>
|
|
8012db4: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8012db6: 445a add r2, fp
|
|
8012db8: 9209 str r2, [sp, #36] @ 0x24
|
|
8012dba: f89a 3000 ldrb.w r3, [sl]
|
|
8012dbe: 2b00 cmp r3, #0
|
|
8012dc0: f000 809f beq.w 8012f02 <_svfiprintf_r+0x1c6>
|
|
8012dc4: 2300 movs r3, #0
|
|
8012dc6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8012dca: e9cd 2305 strd r2, r3, [sp, #20]
|
|
8012dce: f10a 0a01 add.w sl, sl, #1
|
|
8012dd2: 9304 str r3, [sp, #16]
|
|
8012dd4: 9307 str r3, [sp, #28]
|
|
8012dd6: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
8012dda: 931a str r3, [sp, #104] @ 0x68
|
|
8012ddc: 4654 mov r4, sl
|
|
8012dde: 2205 movs r2, #5
|
|
8012de0: f814 1b01 ldrb.w r1, [r4], #1
|
|
8012de4: 484e ldr r0, [pc, #312] @ (8012f20 <_svfiprintf_r+0x1e4>)
|
|
8012de6: f7ed f9f3 bl 80001d0 <memchr>
|
|
8012dea: 9a04 ldr r2, [sp, #16]
|
|
8012dec: b9d8 cbnz r0, 8012e26 <_svfiprintf_r+0xea>
|
|
8012dee: 06d0 lsls r0, r2, #27
|
|
8012df0: bf44 itt mi
|
|
8012df2: 2320 movmi r3, #32
|
|
8012df4: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8012df8: 0711 lsls r1, r2, #28
|
|
8012dfa: bf44 itt mi
|
|
8012dfc: 232b movmi r3, #43 @ 0x2b
|
|
8012dfe: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8012e02: f89a 3000 ldrb.w r3, [sl]
|
|
8012e06: 2b2a cmp r3, #42 @ 0x2a
|
|
8012e08: d015 beq.n 8012e36 <_svfiprintf_r+0xfa>
|
|
8012e0a: 9a07 ldr r2, [sp, #28]
|
|
8012e0c: 4654 mov r4, sl
|
|
8012e0e: 2000 movs r0, #0
|
|
8012e10: f04f 0c0a mov.w ip, #10
|
|
8012e14: 4621 mov r1, r4
|
|
8012e16: f811 3b01 ldrb.w r3, [r1], #1
|
|
8012e1a: 3b30 subs r3, #48 @ 0x30
|
|
8012e1c: 2b09 cmp r3, #9
|
|
8012e1e: d94b bls.n 8012eb8 <_svfiprintf_r+0x17c>
|
|
8012e20: b1b0 cbz r0, 8012e50 <_svfiprintf_r+0x114>
|
|
8012e22: 9207 str r2, [sp, #28]
|
|
8012e24: e014 b.n 8012e50 <_svfiprintf_r+0x114>
|
|
8012e26: eba0 0308 sub.w r3, r0, r8
|
|
8012e2a: fa09 f303 lsl.w r3, r9, r3
|
|
8012e2e: 4313 orrs r3, r2
|
|
8012e30: 9304 str r3, [sp, #16]
|
|
8012e32: 46a2 mov sl, r4
|
|
8012e34: e7d2 b.n 8012ddc <_svfiprintf_r+0xa0>
|
|
8012e36: 9b03 ldr r3, [sp, #12]
|
|
8012e38: 1d19 adds r1, r3, #4
|
|
8012e3a: 681b ldr r3, [r3, #0]
|
|
8012e3c: 9103 str r1, [sp, #12]
|
|
8012e3e: 2b00 cmp r3, #0
|
|
8012e40: bfbb ittet lt
|
|
8012e42: 425b neglt r3, r3
|
|
8012e44: f042 0202 orrlt.w r2, r2, #2
|
|
8012e48: 9307 strge r3, [sp, #28]
|
|
8012e4a: 9307 strlt r3, [sp, #28]
|
|
8012e4c: bfb8 it lt
|
|
8012e4e: 9204 strlt r2, [sp, #16]
|
|
8012e50: 7823 ldrb r3, [r4, #0]
|
|
8012e52: 2b2e cmp r3, #46 @ 0x2e
|
|
8012e54: d10a bne.n 8012e6c <_svfiprintf_r+0x130>
|
|
8012e56: 7863 ldrb r3, [r4, #1]
|
|
8012e58: 2b2a cmp r3, #42 @ 0x2a
|
|
8012e5a: d132 bne.n 8012ec2 <_svfiprintf_r+0x186>
|
|
8012e5c: 9b03 ldr r3, [sp, #12]
|
|
8012e5e: 1d1a adds r2, r3, #4
|
|
8012e60: 681b ldr r3, [r3, #0]
|
|
8012e62: 9203 str r2, [sp, #12]
|
|
8012e64: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
8012e68: 3402 adds r4, #2
|
|
8012e6a: 9305 str r3, [sp, #20]
|
|
8012e6c: f8df a0c0 ldr.w sl, [pc, #192] @ 8012f30 <_svfiprintf_r+0x1f4>
|
|
8012e70: 7821 ldrb r1, [r4, #0]
|
|
8012e72: 2203 movs r2, #3
|
|
8012e74: 4650 mov r0, sl
|
|
8012e76: f7ed f9ab bl 80001d0 <memchr>
|
|
8012e7a: b138 cbz r0, 8012e8c <_svfiprintf_r+0x150>
|
|
8012e7c: 9b04 ldr r3, [sp, #16]
|
|
8012e7e: eba0 000a sub.w r0, r0, sl
|
|
8012e82: 2240 movs r2, #64 @ 0x40
|
|
8012e84: 4082 lsls r2, r0
|
|
8012e86: 4313 orrs r3, r2
|
|
8012e88: 3401 adds r4, #1
|
|
8012e8a: 9304 str r3, [sp, #16]
|
|
8012e8c: f814 1b01 ldrb.w r1, [r4], #1
|
|
8012e90: 4824 ldr r0, [pc, #144] @ (8012f24 <_svfiprintf_r+0x1e8>)
|
|
8012e92: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
8012e96: 2206 movs r2, #6
|
|
8012e98: f7ed f99a bl 80001d0 <memchr>
|
|
8012e9c: 2800 cmp r0, #0
|
|
8012e9e: d036 beq.n 8012f0e <_svfiprintf_r+0x1d2>
|
|
8012ea0: 4b21 ldr r3, [pc, #132] @ (8012f28 <_svfiprintf_r+0x1ec>)
|
|
8012ea2: bb1b cbnz r3, 8012eec <_svfiprintf_r+0x1b0>
|
|
8012ea4: 9b03 ldr r3, [sp, #12]
|
|
8012ea6: 3307 adds r3, #7
|
|
8012ea8: f023 0307 bic.w r3, r3, #7
|
|
8012eac: 3308 adds r3, #8
|
|
8012eae: 9303 str r3, [sp, #12]
|
|
8012eb0: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8012eb2: 4433 add r3, r6
|
|
8012eb4: 9309 str r3, [sp, #36] @ 0x24
|
|
8012eb6: e76a b.n 8012d8e <_svfiprintf_r+0x52>
|
|
8012eb8: fb0c 3202 mla r2, ip, r2, r3
|
|
8012ebc: 460c mov r4, r1
|
|
8012ebe: 2001 movs r0, #1
|
|
8012ec0: e7a8 b.n 8012e14 <_svfiprintf_r+0xd8>
|
|
8012ec2: 2300 movs r3, #0
|
|
8012ec4: 3401 adds r4, #1
|
|
8012ec6: 9305 str r3, [sp, #20]
|
|
8012ec8: 4619 mov r1, r3
|
|
8012eca: f04f 0c0a mov.w ip, #10
|
|
8012ece: 4620 mov r0, r4
|
|
8012ed0: f810 2b01 ldrb.w r2, [r0], #1
|
|
8012ed4: 3a30 subs r2, #48 @ 0x30
|
|
8012ed6: 2a09 cmp r2, #9
|
|
8012ed8: d903 bls.n 8012ee2 <_svfiprintf_r+0x1a6>
|
|
8012eda: 2b00 cmp r3, #0
|
|
8012edc: d0c6 beq.n 8012e6c <_svfiprintf_r+0x130>
|
|
8012ede: 9105 str r1, [sp, #20]
|
|
8012ee0: e7c4 b.n 8012e6c <_svfiprintf_r+0x130>
|
|
8012ee2: fb0c 2101 mla r1, ip, r1, r2
|
|
8012ee6: 4604 mov r4, r0
|
|
8012ee8: 2301 movs r3, #1
|
|
8012eea: e7f0 b.n 8012ece <_svfiprintf_r+0x192>
|
|
8012eec: ab03 add r3, sp, #12
|
|
8012eee: 9300 str r3, [sp, #0]
|
|
8012ef0: 462a mov r2, r5
|
|
8012ef2: 4b0e ldr r3, [pc, #56] @ (8012f2c <_svfiprintf_r+0x1f0>)
|
|
8012ef4: a904 add r1, sp, #16
|
|
8012ef6: 4638 mov r0, r7
|
|
8012ef8: f7fc fae6 bl 800f4c8 <_printf_float>
|
|
8012efc: 1c42 adds r2, r0, #1
|
|
8012efe: 4606 mov r6, r0
|
|
8012f00: d1d6 bne.n 8012eb0 <_svfiprintf_r+0x174>
|
|
8012f02: 89ab ldrh r3, [r5, #12]
|
|
8012f04: 065b lsls r3, r3, #25
|
|
8012f06: f53f af2d bmi.w 8012d64 <_svfiprintf_r+0x28>
|
|
8012f0a: 9809 ldr r0, [sp, #36] @ 0x24
|
|
8012f0c: e72c b.n 8012d68 <_svfiprintf_r+0x2c>
|
|
8012f0e: ab03 add r3, sp, #12
|
|
8012f10: 9300 str r3, [sp, #0]
|
|
8012f12: 462a mov r2, r5
|
|
8012f14: 4b05 ldr r3, [pc, #20] @ (8012f2c <_svfiprintf_r+0x1f0>)
|
|
8012f16: a904 add r1, sp, #16
|
|
8012f18: 4638 mov r0, r7
|
|
8012f1a: f7fc fd6d bl 800f9f8 <_printf_i>
|
|
8012f1e: e7ed b.n 8012efc <_svfiprintf_r+0x1c0>
|
|
8012f20: 08014943 .word 0x08014943
|
|
8012f24: 0801494d .word 0x0801494d
|
|
8012f28: 0800f4c9 .word 0x0800f4c9
|
|
8012f2c: 08012c85 .word 0x08012c85
|
|
8012f30: 08014949 .word 0x08014949
|
|
|
|
08012f34 <__sfputc_r>:
|
|
8012f34: 6893 ldr r3, [r2, #8]
|
|
8012f36: 3b01 subs r3, #1
|
|
8012f38: 2b00 cmp r3, #0
|
|
8012f3a: b410 push {r4}
|
|
8012f3c: 6093 str r3, [r2, #8]
|
|
8012f3e: da08 bge.n 8012f52 <__sfputc_r+0x1e>
|
|
8012f40: 6994 ldr r4, [r2, #24]
|
|
8012f42: 42a3 cmp r3, r4
|
|
8012f44: db01 blt.n 8012f4a <__sfputc_r+0x16>
|
|
8012f46: 290a cmp r1, #10
|
|
8012f48: d103 bne.n 8012f52 <__sfputc_r+0x1e>
|
|
8012f4a: f85d 4b04 ldr.w r4, [sp], #4
|
|
8012f4e: f7fd ba16 b.w 801037e <__swbuf_r>
|
|
8012f52: 6813 ldr r3, [r2, #0]
|
|
8012f54: 1c58 adds r0, r3, #1
|
|
8012f56: 6010 str r0, [r2, #0]
|
|
8012f58: 7019 strb r1, [r3, #0]
|
|
8012f5a: 4608 mov r0, r1
|
|
8012f5c: f85d 4b04 ldr.w r4, [sp], #4
|
|
8012f60: 4770 bx lr
|
|
|
|
08012f62 <__sfputs_r>:
|
|
8012f62: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8012f64: 4606 mov r6, r0
|
|
8012f66: 460f mov r7, r1
|
|
8012f68: 4614 mov r4, r2
|
|
8012f6a: 18d5 adds r5, r2, r3
|
|
8012f6c: 42ac cmp r4, r5
|
|
8012f6e: d101 bne.n 8012f74 <__sfputs_r+0x12>
|
|
8012f70: 2000 movs r0, #0
|
|
8012f72: e007 b.n 8012f84 <__sfputs_r+0x22>
|
|
8012f74: f814 1b01 ldrb.w r1, [r4], #1
|
|
8012f78: 463a mov r2, r7
|
|
8012f7a: 4630 mov r0, r6
|
|
8012f7c: f7ff ffda bl 8012f34 <__sfputc_r>
|
|
8012f80: 1c43 adds r3, r0, #1
|
|
8012f82: d1f3 bne.n 8012f6c <__sfputs_r+0xa>
|
|
8012f84: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
...
|
|
|
|
08012f88 <_vfiprintf_r>:
|
|
8012f88: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8012f8c: 460d mov r5, r1
|
|
8012f8e: b09d sub sp, #116 @ 0x74
|
|
8012f90: 4614 mov r4, r2
|
|
8012f92: 4698 mov r8, r3
|
|
8012f94: 4606 mov r6, r0
|
|
8012f96: b118 cbz r0, 8012fa0 <_vfiprintf_r+0x18>
|
|
8012f98: 6a03 ldr r3, [r0, #32]
|
|
8012f9a: b90b cbnz r3, 8012fa0 <_vfiprintf_r+0x18>
|
|
8012f9c: f7fd f8e4 bl 8010168 <__sinit>
|
|
8012fa0: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8012fa2: 07d9 lsls r1, r3, #31
|
|
8012fa4: d405 bmi.n 8012fb2 <_vfiprintf_r+0x2a>
|
|
8012fa6: 89ab ldrh r3, [r5, #12]
|
|
8012fa8: 059a lsls r2, r3, #22
|
|
8012faa: d402 bmi.n 8012fb2 <_vfiprintf_r+0x2a>
|
|
8012fac: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8012fae: f7fd fbae bl 801070e <__retarget_lock_acquire_recursive>
|
|
8012fb2: 89ab ldrh r3, [r5, #12]
|
|
8012fb4: 071b lsls r3, r3, #28
|
|
8012fb6: d501 bpl.n 8012fbc <_vfiprintf_r+0x34>
|
|
8012fb8: 692b ldr r3, [r5, #16]
|
|
8012fba: b99b cbnz r3, 8012fe4 <_vfiprintf_r+0x5c>
|
|
8012fbc: 4629 mov r1, r5
|
|
8012fbe: 4630 mov r0, r6
|
|
8012fc0: f7fd fa1c bl 80103fc <__swsetup_r>
|
|
8012fc4: b170 cbz r0, 8012fe4 <_vfiprintf_r+0x5c>
|
|
8012fc6: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8012fc8: 07dc lsls r4, r3, #31
|
|
8012fca: d504 bpl.n 8012fd6 <_vfiprintf_r+0x4e>
|
|
8012fcc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8012fd0: b01d add sp, #116 @ 0x74
|
|
8012fd2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8012fd6: 89ab ldrh r3, [r5, #12]
|
|
8012fd8: 0598 lsls r0, r3, #22
|
|
8012fda: d4f7 bmi.n 8012fcc <_vfiprintf_r+0x44>
|
|
8012fdc: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8012fde: f7fd fb97 bl 8010710 <__retarget_lock_release_recursive>
|
|
8012fe2: e7f3 b.n 8012fcc <_vfiprintf_r+0x44>
|
|
8012fe4: 2300 movs r3, #0
|
|
8012fe6: 9309 str r3, [sp, #36] @ 0x24
|
|
8012fe8: 2320 movs r3, #32
|
|
8012fea: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
8012fee: f8cd 800c str.w r8, [sp, #12]
|
|
8012ff2: 2330 movs r3, #48 @ 0x30
|
|
8012ff4: f8df 81ac ldr.w r8, [pc, #428] @ 80131a4 <_vfiprintf_r+0x21c>
|
|
8012ff8: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
8012ffc: f04f 0901 mov.w r9, #1
|
|
8013000: 4623 mov r3, r4
|
|
8013002: 469a mov sl, r3
|
|
8013004: f813 2b01 ldrb.w r2, [r3], #1
|
|
8013008: b10a cbz r2, 801300e <_vfiprintf_r+0x86>
|
|
801300a: 2a25 cmp r2, #37 @ 0x25
|
|
801300c: d1f9 bne.n 8013002 <_vfiprintf_r+0x7a>
|
|
801300e: ebba 0b04 subs.w fp, sl, r4
|
|
8013012: d00b beq.n 801302c <_vfiprintf_r+0xa4>
|
|
8013014: 465b mov r3, fp
|
|
8013016: 4622 mov r2, r4
|
|
8013018: 4629 mov r1, r5
|
|
801301a: 4630 mov r0, r6
|
|
801301c: f7ff ffa1 bl 8012f62 <__sfputs_r>
|
|
8013020: 3001 adds r0, #1
|
|
8013022: f000 80a7 beq.w 8013174 <_vfiprintf_r+0x1ec>
|
|
8013026: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8013028: 445a add r2, fp
|
|
801302a: 9209 str r2, [sp, #36] @ 0x24
|
|
801302c: f89a 3000 ldrb.w r3, [sl]
|
|
8013030: 2b00 cmp r3, #0
|
|
8013032: f000 809f beq.w 8013174 <_vfiprintf_r+0x1ec>
|
|
8013036: 2300 movs r3, #0
|
|
8013038: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
801303c: e9cd 2305 strd r2, r3, [sp, #20]
|
|
8013040: f10a 0a01 add.w sl, sl, #1
|
|
8013044: 9304 str r3, [sp, #16]
|
|
8013046: 9307 str r3, [sp, #28]
|
|
8013048: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
801304c: 931a str r3, [sp, #104] @ 0x68
|
|
801304e: 4654 mov r4, sl
|
|
8013050: 2205 movs r2, #5
|
|
8013052: f814 1b01 ldrb.w r1, [r4], #1
|
|
8013056: 4853 ldr r0, [pc, #332] @ (80131a4 <_vfiprintf_r+0x21c>)
|
|
8013058: f7ed f8ba bl 80001d0 <memchr>
|
|
801305c: 9a04 ldr r2, [sp, #16]
|
|
801305e: b9d8 cbnz r0, 8013098 <_vfiprintf_r+0x110>
|
|
8013060: 06d1 lsls r1, r2, #27
|
|
8013062: bf44 itt mi
|
|
8013064: 2320 movmi r3, #32
|
|
8013066: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
801306a: 0713 lsls r3, r2, #28
|
|
801306c: bf44 itt mi
|
|
801306e: 232b movmi r3, #43 @ 0x2b
|
|
8013070: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8013074: f89a 3000 ldrb.w r3, [sl]
|
|
8013078: 2b2a cmp r3, #42 @ 0x2a
|
|
801307a: d015 beq.n 80130a8 <_vfiprintf_r+0x120>
|
|
801307c: 9a07 ldr r2, [sp, #28]
|
|
801307e: 4654 mov r4, sl
|
|
8013080: 2000 movs r0, #0
|
|
8013082: f04f 0c0a mov.w ip, #10
|
|
8013086: 4621 mov r1, r4
|
|
8013088: f811 3b01 ldrb.w r3, [r1], #1
|
|
801308c: 3b30 subs r3, #48 @ 0x30
|
|
801308e: 2b09 cmp r3, #9
|
|
8013090: d94b bls.n 801312a <_vfiprintf_r+0x1a2>
|
|
8013092: b1b0 cbz r0, 80130c2 <_vfiprintf_r+0x13a>
|
|
8013094: 9207 str r2, [sp, #28]
|
|
8013096: e014 b.n 80130c2 <_vfiprintf_r+0x13a>
|
|
8013098: eba0 0308 sub.w r3, r0, r8
|
|
801309c: fa09 f303 lsl.w r3, r9, r3
|
|
80130a0: 4313 orrs r3, r2
|
|
80130a2: 9304 str r3, [sp, #16]
|
|
80130a4: 46a2 mov sl, r4
|
|
80130a6: e7d2 b.n 801304e <_vfiprintf_r+0xc6>
|
|
80130a8: 9b03 ldr r3, [sp, #12]
|
|
80130aa: 1d19 adds r1, r3, #4
|
|
80130ac: 681b ldr r3, [r3, #0]
|
|
80130ae: 9103 str r1, [sp, #12]
|
|
80130b0: 2b00 cmp r3, #0
|
|
80130b2: bfbb ittet lt
|
|
80130b4: 425b neglt r3, r3
|
|
80130b6: f042 0202 orrlt.w r2, r2, #2
|
|
80130ba: 9307 strge r3, [sp, #28]
|
|
80130bc: 9307 strlt r3, [sp, #28]
|
|
80130be: bfb8 it lt
|
|
80130c0: 9204 strlt r2, [sp, #16]
|
|
80130c2: 7823 ldrb r3, [r4, #0]
|
|
80130c4: 2b2e cmp r3, #46 @ 0x2e
|
|
80130c6: d10a bne.n 80130de <_vfiprintf_r+0x156>
|
|
80130c8: 7863 ldrb r3, [r4, #1]
|
|
80130ca: 2b2a cmp r3, #42 @ 0x2a
|
|
80130cc: d132 bne.n 8013134 <_vfiprintf_r+0x1ac>
|
|
80130ce: 9b03 ldr r3, [sp, #12]
|
|
80130d0: 1d1a adds r2, r3, #4
|
|
80130d2: 681b ldr r3, [r3, #0]
|
|
80130d4: 9203 str r2, [sp, #12]
|
|
80130d6: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
80130da: 3402 adds r4, #2
|
|
80130dc: 9305 str r3, [sp, #20]
|
|
80130de: f8df a0d4 ldr.w sl, [pc, #212] @ 80131b4 <_vfiprintf_r+0x22c>
|
|
80130e2: 7821 ldrb r1, [r4, #0]
|
|
80130e4: 2203 movs r2, #3
|
|
80130e6: 4650 mov r0, sl
|
|
80130e8: f7ed f872 bl 80001d0 <memchr>
|
|
80130ec: b138 cbz r0, 80130fe <_vfiprintf_r+0x176>
|
|
80130ee: 9b04 ldr r3, [sp, #16]
|
|
80130f0: eba0 000a sub.w r0, r0, sl
|
|
80130f4: 2240 movs r2, #64 @ 0x40
|
|
80130f6: 4082 lsls r2, r0
|
|
80130f8: 4313 orrs r3, r2
|
|
80130fa: 3401 adds r4, #1
|
|
80130fc: 9304 str r3, [sp, #16]
|
|
80130fe: f814 1b01 ldrb.w r1, [r4], #1
|
|
8013102: 4829 ldr r0, [pc, #164] @ (80131a8 <_vfiprintf_r+0x220>)
|
|
8013104: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
8013108: 2206 movs r2, #6
|
|
801310a: f7ed f861 bl 80001d0 <memchr>
|
|
801310e: 2800 cmp r0, #0
|
|
8013110: d03f beq.n 8013192 <_vfiprintf_r+0x20a>
|
|
8013112: 4b26 ldr r3, [pc, #152] @ (80131ac <_vfiprintf_r+0x224>)
|
|
8013114: bb1b cbnz r3, 801315e <_vfiprintf_r+0x1d6>
|
|
8013116: 9b03 ldr r3, [sp, #12]
|
|
8013118: 3307 adds r3, #7
|
|
801311a: f023 0307 bic.w r3, r3, #7
|
|
801311e: 3308 adds r3, #8
|
|
8013120: 9303 str r3, [sp, #12]
|
|
8013122: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8013124: 443b add r3, r7
|
|
8013126: 9309 str r3, [sp, #36] @ 0x24
|
|
8013128: e76a b.n 8013000 <_vfiprintf_r+0x78>
|
|
801312a: fb0c 3202 mla r2, ip, r2, r3
|
|
801312e: 460c mov r4, r1
|
|
8013130: 2001 movs r0, #1
|
|
8013132: e7a8 b.n 8013086 <_vfiprintf_r+0xfe>
|
|
8013134: 2300 movs r3, #0
|
|
8013136: 3401 adds r4, #1
|
|
8013138: 9305 str r3, [sp, #20]
|
|
801313a: 4619 mov r1, r3
|
|
801313c: f04f 0c0a mov.w ip, #10
|
|
8013140: 4620 mov r0, r4
|
|
8013142: f810 2b01 ldrb.w r2, [r0], #1
|
|
8013146: 3a30 subs r2, #48 @ 0x30
|
|
8013148: 2a09 cmp r2, #9
|
|
801314a: d903 bls.n 8013154 <_vfiprintf_r+0x1cc>
|
|
801314c: 2b00 cmp r3, #0
|
|
801314e: d0c6 beq.n 80130de <_vfiprintf_r+0x156>
|
|
8013150: 9105 str r1, [sp, #20]
|
|
8013152: e7c4 b.n 80130de <_vfiprintf_r+0x156>
|
|
8013154: fb0c 2101 mla r1, ip, r1, r2
|
|
8013158: 4604 mov r4, r0
|
|
801315a: 2301 movs r3, #1
|
|
801315c: e7f0 b.n 8013140 <_vfiprintf_r+0x1b8>
|
|
801315e: ab03 add r3, sp, #12
|
|
8013160: 9300 str r3, [sp, #0]
|
|
8013162: 462a mov r2, r5
|
|
8013164: 4b12 ldr r3, [pc, #72] @ (80131b0 <_vfiprintf_r+0x228>)
|
|
8013166: a904 add r1, sp, #16
|
|
8013168: 4630 mov r0, r6
|
|
801316a: f7fc f9ad bl 800f4c8 <_printf_float>
|
|
801316e: 4607 mov r7, r0
|
|
8013170: 1c78 adds r0, r7, #1
|
|
8013172: d1d6 bne.n 8013122 <_vfiprintf_r+0x19a>
|
|
8013174: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8013176: 07d9 lsls r1, r3, #31
|
|
8013178: d405 bmi.n 8013186 <_vfiprintf_r+0x1fe>
|
|
801317a: 89ab ldrh r3, [r5, #12]
|
|
801317c: 059a lsls r2, r3, #22
|
|
801317e: d402 bmi.n 8013186 <_vfiprintf_r+0x1fe>
|
|
8013180: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8013182: f7fd fac5 bl 8010710 <__retarget_lock_release_recursive>
|
|
8013186: 89ab ldrh r3, [r5, #12]
|
|
8013188: 065b lsls r3, r3, #25
|
|
801318a: f53f af1f bmi.w 8012fcc <_vfiprintf_r+0x44>
|
|
801318e: 9809 ldr r0, [sp, #36] @ 0x24
|
|
8013190: e71e b.n 8012fd0 <_vfiprintf_r+0x48>
|
|
8013192: ab03 add r3, sp, #12
|
|
8013194: 9300 str r3, [sp, #0]
|
|
8013196: 462a mov r2, r5
|
|
8013198: 4b05 ldr r3, [pc, #20] @ (80131b0 <_vfiprintf_r+0x228>)
|
|
801319a: a904 add r1, sp, #16
|
|
801319c: 4630 mov r0, r6
|
|
801319e: f7fc fc2b bl 800f9f8 <_printf_i>
|
|
80131a2: e7e4 b.n 801316e <_vfiprintf_r+0x1e6>
|
|
80131a4: 08014943 .word 0x08014943
|
|
80131a8: 0801494d .word 0x0801494d
|
|
80131ac: 0800f4c9 .word 0x0800f4c9
|
|
80131b0: 08012f63 .word 0x08012f63
|
|
80131b4: 08014949 .word 0x08014949
|
|
|
|
080131b8 <__sflush_r>:
|
|
80131b8: f9b1 200c ldrsh.w r2, [r1, #12]
|
|
80131bc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
80131c0: 0716 lsls r6, r2, #28
|
|
80131c2: 4605 mov r5, r0
|
|
80131c4: 460c mov r4, r1
|
|
80131c6: d454 bmi.n 8013272 <__sflush_r+0xba>
|
|
80131c8: 684b ldr r3, [r1, #4]
|
|
80131ca: 2b00 cmp r3, #0
|
|
80131cc: dc02 bgt.n 80131d4 <__sflush_r+0x1c>
|
|
80131ce: 6c0b ldr r3, [r1, #64] @ 0x40
|
|
80131d0: 2b00 cmp r3, #0
|
|
80131d2: dd48 ble.n 8013266 <__sflush_r+0xae>
|
|
80131d4: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
80131d6: 2e00 cmp r6, #0
|
|
80131d8: d045 beq.n 8013266 <__sflush_r+0xae>
|
|
80131da: 2300 movs r3, #0
|
|
80131dc: f412 5280 ands.w r2, r2, #4096 @ 0x1000
|
|
80131e0: 682f ldr r7, [r5, #0]
|
|
80131e2: 6a21 ldr r1, [r4, #32]
|
|
80131e4: 602b str r3, [r5, #0]
|
|
80131e6: d030 beq.n 801324a <__sflush_r+0x92>
|
|
80131e8: 6d62 ldr r2, [r4, #84] @ 0x54
|
|
80131ea: 89a3 ldrh r3, [r4, #12]
|
|
80131ec: 0759 lsls r1, r3, #29
|
|
80131ee: d505 bpl.n 80131fc <__sflush_r+0x44>
|
|
80131f0: 6863 ldr r3, [r4, #4]
|
|
80131f2: 1ad2 subs r2, r2, r3
|
|
80131f4: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
80131f6: b10b cbz r3, 80131fc <__sflush_r+0x44>
|
|
80131f8: 6c23 ldr r3, [r4, #64] @ 0x40
|
|
80131fa: 1ad2 subs r2, r2, r3
|
|
80131fc: 2300 movs r3, #0
|
|
80131fe: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
8013200: 6a21 ldr r1, [r4, #32]
|
|
8013202: 4628 mov r0, r5
|
|
8013204: 47b0 blx r6
|
|
8013206: 1c43 adds r3, r0, #1
|
|
8013208: 89a3 ldrh r3, [r4, #12]
|
|
801320a: d106 bne.n 801321a <__sflush_r+0x62>
|
|
801320c: 6829 ldr r1, [r5, #0]
|
|
801320e: 291d cmp r1, #29
|
|
8013210: d82b bhi.n 801326a <__sflush_r+0xb2>
|
|
8013212: 4a2a ldr r2, [pc, #168] @ (80132bc <__sflush_r+0x104>)
|
|
8013214: 40ca lsrs r2, r1
|
|
8013216: 07d6 lsls r6, r2, #31
|
|
8013218: d527 bpl.n 801326a <__sflush_r+0xb2>
|
|
801321a: 2200 movs r2, #0
|
|
801321c: 6062 str r2, [r4, #4]
|
|
801321e: 04d9 lsls r1, r3, #19
|
|
8013220: 6922 ldr r2, [r4, #16]
|
|
8013222: 6022 str r2, [r4, #0]
|
|
8013224: d504 bpl.n 8013230 <__sflush_r+0x78>
|
|
8013226: 1c42 adds r2, r0, #1
|
|
8013228: d101 bne.n 801322e <__sflush_r+0x76>
|
|
801322a: 682b ldr r3, [r5, #0]
|
|
801322c: b903 cbnz r3, 8013230 <__sflush_r+0x78>
|
|
801322e: 6560 str r0, [r4, #84] @ 0x54
|
|
8013230: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
8013232: 602f str r7, [r5, #0]
|
|
8013234: b1b9 cbz r1, 8013266 <__sflush_r+0xae>
|
|
8013236: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
801323a: 4299 cmp r1, r3
|
|
801323c: d002 beq.n 8013244 <__sflush_r+0x8c>
|
|
801323e: 4628 mov r0, r5
|
|
8013240: f7fe f8f2 bl 8011428 <_free_r>
|
|
8013244: 2300 movs r3, #0
|
|
8013246: 6363 str r3, [r4, #52] @ 0x34
|
|
8013248: e00d b.n 8013266 <__sflush_r+0xae>
|
|
801324a: 2301 movs r3, #1
|
|
801324c: 4628 mov r0, r5
|
|
801324e: 47b0 blx r6
|
|
8013250: 4602 mov r2, r0
|
|
8013252: 1c50 adds r0, r2, #1
|
|
8013254: d1c9 bne.n 80131ea <__sflush_r+0x32>
|
|
8013256: 682b ldr r3, [r5, #0]
|
|
8013258: 2b00 cmp r3, #0
|
|
801325a: d0c6 beq.n 80131ea <__sflush_r+0x32>
|
|
801325c: 2b1d cmp r3, #29
|
|
801325e: d001 beq.n 8013264 <__sflush_r+0xac>
|
|
8013260: 2b16 cmp r3, #22
|
|
8013262: d11e bne.n 80132a2 <__sflush_r+0xea>
|
|
8013264: 602f str r7, [r5, #0]
|
|
8013266: 2000 movs r0, #0
|
|
8013268: e022 b.n 80132b0 <__sflush_r+0xf8>
|
|
801326a: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
801326e: b21b sxth r3, r3
|
|
8013270: e01b b.n 80132aa <__sflush_r+0xf2>
|
|
8013272: 690f ldr r7, [r1, #16]
|
|
8013274: 2f00 cmp r7, #0
|
|
8013276: d0f6 beq.n 8013266 <__sflush_r+0xae>
|
|
8013278: 0793 lsls r3, r2, #30
|
|
801327a: 680e ldr r6, [r1, #0]
|
|
801327c: bf08 it eq
|
|
801327e: 694b ldreq r3, [r1, #20]
|
|
8013280: 600f str r7, [r1, #0]
|
|
8013282: bf18 it ne
|
|
8013284: 2300 movne r3, #0
|
|
8013286: eba6 0807 sub.w r8, r6, r7
|
|
801328a: 608b str r3, [r1, #8]
|
|
801328c: f1b8 0f00 cmp.w r8, #0
|
|
8013290: dde9 ble.n 8013266 <__sflush_r+0xae>
|
|
8013292: 6a21 ldr r1, [r4, #32]
|
|
8013294: 6aa6 ldr r6, [r4, #40] @ 0x28
|
|
8013296: 4643 mov r3, r8
|
|
8013298: 463a mov r2, r7
|
|
801329a: 4628 mov r0, r5
|
|
801329c: 47b0 blx r6
|
|
801329e: 2800 cmp r0, #0
|
|
80132a0: dc08 bgt.n 80132b4 <__sflush_r+0xfc>
|
|
80132a2: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
80132a6: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
80132aa: 81a3 strh r3, [r4, #12]
|
|
80132ac: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80132b0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
80132b4: 4407 add r7, r0
|
|
80132b6: eba8 0800 sub.w r8, r8, r0
|
|
80132ba: e7e7 b.n 801328c <__sflush_r+0xd4>
|
|
80132bc: 20400001 .word 0x20400001
|
|
|
|
080132c0 <_fflush_r>:
|
|
80132c0: b538 push {r3, r4, r5, lr}
|
|
80132c2: 690b ldr r3, [r1, #16]
|
|
80132c4: 4605 mov r5, r0
|
|
80132c6: 460c mov r4, r1
|
|
80132c8: b913 cbnz r3, 80132d0 <_fflush_r+0x10>
|
|
80132ca: 2500 movs r5, #0
|
|
80132cc: 4628 mov r0, r5
|
|
80132ce: bd38 pop {r3, r4, r5, pc}
|
|
80132d0: b118 cbz r0, 80132da <_fflush_r+0x1a>
|
|
80132d2: 6a03 ldr r3, [r0, #32]
|
|
80132d4: b90b cbnz r3, 80132da <_fflush_r+0x1a>
|
|
80132d6: f7fc ff47 bl 8010168 <__sinit>
|
|
80132da: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
80132de: 2b00 cmp r3, #0
|
|
80132e0: d0f3 beq.n 80132ca <_fflush_r+0xa>
|
|
80132e2: 6e62 ldr r2, [r4, #100] @ 0x64
|
|
80132e4: 07d0 lsls r0, r2, #31
|
|
80132e6: d404 bmi.n 80132f2 <_fflush_r+0x32>
|
|
80132e8: 0599 lsls r1, r3, #22
|
|
80132ea: d402 bmi.n 80132f2 <_fflush_r+0x32>
|
|
80132ec: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
80132ee: f7fd fa0e bl 801070e <__retarget_lock_acquire_recursive>
|
|
80132f2: 4628 mov r0, r5
|
|
80132f4: 4621 mov r1, r4
|
|
80132f6: f7ff ff5f bl 80131b8 <__sflush_r>
|
|
80132fa: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
80132fc: 07da lsls r2, r3, #31
|
|
80132fe: 4605 mov r5, r0
|
|
8013300: d4e4 bmi.n 80132cc <_fflush_r+0xc>
|
|
8013302: 89a3 ldrh r3, [r4, #12]
|
|
8013304: 059b lsls r3, r3, #22
|
|
8013306: d4e1 bmi.n 80132cc <_fflush_r+0xc>
|
|
8013308: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
801330a: f7fd fa01 bl 8010710 <__retarget_lock_release_recursive>
|
|
801330e: e7dd b.n 80132cc <_fflush_r+0xc>
|
|
|
|
08013310 <fiprintf>:
|
|
8013310: b40e push {r1, r2, r3}
|
|
8013312: b503 push {r0, r1, lr}
|
|
8013314: 4601 mov r1, r0
|
|
8013316: ab03 add r3, sp, #12
|
|
8013318: 4805 ldr r0, [pc, #20] @ (8013330 <fiprintf+0x20>)
|
|
801331a: f853 2b04 ldr.w r2, [r3], #4
|
|
801331e: 6800 ldr r0, [r0, #0]
|
|
8013320: 9301 str r3, [sp, #4]
|
|
8013322: f7ff fe31 bl 8012f88 <_vfiprintf_r>
|
|
8013326: b002 add sp, #8
|
|
8013328: f85d eb04 ldr.w lr, [sp], #4
|
|
801332c: b003 add sp, #12
|
|
801332e: 4770 bx lr
|
|
8013330: 200000e0 .word 0x200000e0
|
|
|
|
08013334 <__swhatbuf_r>:
|
|
8013334: b570 push {r4, r5, r6, lr}
|
|
8013336: 460c mov r4, r1
|
|
8013338: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801333c: 2900 cmp r1, #0
|
|
801333e: b096 sub sp, #88 @ 0x58
|
|
8013340: 4615 mov r5, r2
|
|
8013342: 461e mov r6, r3
|
|
8013344: da0d bge.n 8013362 <__swhatbuf_r+0x2e>
|
|
8013346: 89a3 ldrh r3, [r4, #12]
|
|
8013348: f013 0f80 tst.w r3, #128 @ 0x80
|
|
801334c: f04f 0100 mov.w r1, #0
|
|
8013350: bf14 ite ne
|
|
8013352: 2340 movne r3, #64 @ 0x40
|
|
8013354: f44f 6380 moveq.w r3, #1024 @ 0x400
|
|
8013358: 2000 movs r0, #0
|
|
801335a: 6031 str r1, [r6, #0]
|
|
801335c: 602b str r3, [r5, #0]
|
|
801335e: b016 add sp, #88 @ 0x58
|
|
8013360: bd70 pop {r4, r5, r6, pc}
|
|
8013362: 466a mov r2, sp
|
|
8013364: f000 f862 bl 801342c <_fstat_r>
|
|
8013368: 2800 cmp r0, #0
|
|
801336a: dbec blt.n 8013346 <__swhatbuf_r+0x12>
|
|
801336c: 9901 ldr r1, [sp, #4]
|
|
801336e: f401 4170 and.w r1, r1, #61440 @ 0xf000
|
|
8013372: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
|
|
8013376: 4259 negs r1, r3
|
|
8013378: 4159 adcs r1, r3
|
|
801337a: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
801337e: e7eb b.n 8013358 <__swhatbuf_r+0x24>
|
|
|
|
08013380 <__smakebuf_r>:
|
|
8013380: 898b ldrh r3, [r1, #12]
|
|
8013382: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
8013384: 079d lsls r5, r3, #30
|
|
8013386: 4606 mov r6, r0
|
|
8013388: 460c mov r4, r1
|
|
801338a: d507 bpl.n 801339c <__smakebuf_r+0x1c>
|
|
801338c: f104 0347 add.w r3, r4, #71 @ 0x47
|
|
8013390: 6023 str r3, [r4, #0]
|
|
8013392: 6123 str r3, [r4, #16]
|
|
8013394: 2301 movs r3, #1
|
|
8013396: 6163 str r3, [r4, #20]
|
|
8013398: b003 add sp, #12
|
|
801339a: bdf0 pop {r4, r5, r6, r7, pc}
|
|
801339c: ab01 add r3, sp, #4
|
|
801339e: 466a mov r2, sp
|
|
80133a0: f7ff ffc8 bl 8013334 <__swhatbuf_r>
|
|
80133a4: 9f00 ldr r7, [sp, #0]
|
|
80133a6: 4605 mov r5, r0
|
|
80133a8: 4639 mov r1, r7
|
|
80133aa: 4630 mov r0, r6
|
|
80133ac: f7fe f8b0 bl 8011510 <_malloc_r>
|
|
80133b0: b948 cbnz r0, 80133c6 <__smakebuf_r+0x46>
|
|
80133b2: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
80133b6: 059a lsls r2, r3, #22
|
|
80133b8: d4ee bmi.n 8013398 <__smakebuf_r+0x18>
|
|
80133ba: f023 0303 bic.w r3, r3, #3
|
|
80133be: f043 0302 orr.w r3, r3, #2
|
|
80133c2: 81a3 strh r3, [r4, #12]
|
|
80133c4: e7e2 b.n 801338c <__smakebuf_r+0xc>
|
|
80133c6: 89a3 ldrh r3, [r4, #12]
|
|
80133c8: 6020 str r0, [r4, #0]
|
|
80133ca: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80133ce: 81a3 strh r3, [r4, #12]
|
|
80133d0: 9b01 ldr r3, [sp, #4]
|
|
80133d2: e9c4 0704 strd r0, r7, [r4, #16]
|
|
80133d6: b15b cbz r3, 80133f0 <__smakebuf_r+0x70>
|
|
80133d8: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
80133dc: 4630 mov r0, r6
|
|
80133de: f000 f837 bl 8013450 <_isatty_r>
|
|
80133e2: b128 cbz r0, 80133f0 <__smakebuf_r+0x70>
|
|
80133e4: 89a3 ldrh r3, [r4, #12]
|
|
80133e6: f023 0303 bic.w r3, r3, #3
|
|
80133ea: f043 0301 orr.w r3, r3, #1
|
|
80133ee: 81a3 strh r3, [r4, #12]
|
|
80133f0: 89a3 ldrh r3, [r4, #12]
|
|
80133f2: 431d orrs r5, r3
|
|
80133f4: 81a5 strh r5, [r4, #12]
|
|
80133f6: e7cf b.n 8013398 <__smakebuf_r+0x18>
|
|
|
|
080133f8 <memmove>:
|
|
80133f8: 4288 cmp r0, r1
|
|
80133fa: b510 push {r4, lr}
|
|
80133fc: eb01 0402 add.w r4, r1, r2
|
|
8013400: d902 bls.n 8013408 <memmove+0x10>
|
|
8013402: 4284 cmp r4, r0
|
|
8013404: 4623 mov r3, r4
|
|
8013406: d807 bhi.n 8013418 <memmove+0x20>
|
|
8013408: 1e43 subs r3, r0, #1
|
|
801340a: 42a1 cmp r1, r4
|
|
801340c: d008 beq.n 8013420 <memmove+0x28>
|
|
801340e: f811 2b01 ldrb.w r2, [r1], #1
|
|
8013412: f803 2f01 strb.w r2, [r3, #1]!
|
|
8013416: e7f8 b.n 801340a <memmove+0x12>
|
|
8013418: 4402 add r2, r0
|
|
801341a: 4601 mov r1, r0
|
|
801341c: 428a cmp r2, r1
|
|
801341e: d100 bne.n 8013422 <memmove+0x2a>
|
|
8013420: bd10 pop {r4, pc}
|
|
8013422: f813 4d01 ldrb.w r4, [r3, #-1]!
|
|
8013426: f802 4d01 strb.w r4, [r2, #-1]!
|
|
801342a: e7f7 b.n 801341c <memmove+0x24>
|
|
|
|
0801342c <_fstat_r>:
|
|
801342c: b538 push {r3, r4, r5, lr}
|
|
801342e: 4d07 ldr r5, [pc, #28] @ (801344c <_fstat_r+0x20>)
|
|
8013430: 2300 movs r3, #0
|
|
8013432: 4604 mov r4, r0
|
|
8013434: 4608 mov r0, r1
|
|
8013436: 4611 mov r1, r2
|
|
8013438: 602b str r3, [r5, #0]
|
|
801343a: f7f0 fb9b bl 8003b74 <_fstat>
|
|
801343e: 1c43 adds r3, r0, #1
|
|
8013440: d102 bne.n 8013448 <_fstat_r+0x1c>
|
|
8013442: 682b ldr r3, [r5, #0]
|
|
8013444: b103 cbz r3, 8013448 <_fstat_r+0x1c>
|
|
8013446: 6023 str r3, [r4, #0]
|
|
8013448: bd38 pop {r3, r4, r5, pc}
|
|
801344a: bf00 nop
|
|
801344c: 200036c8 .word 0x200036c8
|
|
|
|
08013450 <_isatty_r>:
|
|
8013450: b538 push {r3, r4, r5, lr}
|
|
8013452: 4d06 ldr r5, [pc, #24] @ (801346c <_isatty_r+0x1c>)
|
|
8013454: 2300 movs r3, #0
|
|
8013456: 4604 mov r4, r0
|
|
8013458: 4608 mov r0, r1
|
|
801345a: 602b str r3, [r5, #0]
|
|
801345c: f7f0 fb9a bl 8003b94 <_isatty>
|
|
8013460: 1c43 adds r3, r0, #1
|
|
8013462: d102 bne.n 801346a <_isatty_r+0x1a>
|
|
8013464: 682b ldr r3, [r5, #0]
|
|
8013466: b103 cbz r3, 801346a <_isatty_r+0x1a>
|
|
8013468: 6023 str r3, [r4, #0]
|
|
801346a: bd38 pop {r3, r4, r5, pc}
|
|
801346c: 200036c8 .word 0x200036c8
|
|
|
|
08013470 <_sbrk_r>:
|
|
8013470: b538 push {r3, r4, r5, lr}
|
|
8013472: 4d06 ldr r5, [pc, #24] @ (801348c <_sbrk_r+0x1c>)
|
|
8013474: 2300 movs r3, #0
|
|
8013476: 4604 mov r4, r0
|
|
8013478: 4608 mov r0, r1
|
|
801347a: 602b str r3, [r5, #0]
|
|
801347c: f7f0 fba2 bl 8003bc4 <_sbrk>
|
|
8013480: 1c43 adds r3, r0, #1
|
|
8013482: d102 bne.n 801348a <_sbrk_r+0x1a>
|
|
8013484: 682b ldr r3, [r5, #0]
|
|
8013486: b103 cbz r3, 801348a <_sbrk_r+0x1a>
|
|
8013488: 6023 str r3, [r4, #0]
|
|
801348a: bd38 pop {r3, r4, r5, pc}
|
|
801348c: 200036c8 .word 0x200036c8
|
|
|
|
08013490 <nan>:
|
|
8013490: ed9f 0b01 vldr d0, [pc, #4] @ 8013498 <nan+0x8>
|
|
8013494: 4770 bx lr
|
|
8013496: bf00 nop
|
|
8013498: 00000000 .word 0x00000000
|
|
801349c: 7ff80000 .word 0x7ff80000
|
|
|
|
080134a0 <abort>:
|
|
80134a0: b508 push {r3, lr}
|
|
80134a2: 2006 movs r0, #6
|
|
80134a4: f000 fbc4 bl 8013c30 <raise>
|
|
80134a8: 2001 movs r0, #1
|
|
80134aa: f7f0 fb13 bl 8003ad4 <_exit>
|
|
|
|
080134ae <_calloc_r>:
|
|
80134ae: b570 push {r4, r5, r6, lr}
|
|
80134b0: fba1 5402 umull r5, r4, r1, r2
|
|
80134b4: b934 cbnz r4, 80134c4 <_calloc_r+0x16>
|
|
80134b6: 4629 mov r1, r5
|
|
80134b8: f7fe f82a bl 8011510 <_malloc_r>
|
|
80134bc: 4606 mov r6, r0
|
|
80134be: b928 cbnz r0, 80134cc <_calloc_r+0x1e>
|
|
80134c0: 4630 mov r0, r6
|
|
80134c2: bd70 pop {r4, r5, r6, pc}
|
|
80134c4: 220c movs r2, #12
|
|
80134c6: 6002 str r2, [r0, #0]
|
|
80134c8: 2600 movs r6, #0
|
|
80134ca: e7f9 b.n 80134c0 <_calloc_r+0x12>
|
|
80134cc: 462a mov r2, r5
|
|
80134ce: 4621 mov r1, r4
|
|
80134d0: f7fc fffa bl 80104c8 <memset>
|
|
80134d4: e7f4 b.n 80134c0 <_calloc_r+0x12>
|
|
|
|
080134d6 <rshift>:
|
|
80134d6: 6903 ldr r3, [r0, #16]
|
|
80134d8: ebb3 1f61 cmp.w r3, r1, asr #5
|
|
80134dc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
|
|
80134e0: ea4f 1261 mov.w r2, r1, asr #5
|
|
80134e4: f100 0414 add.w r4, r0, #20
|
|
80134e8: dd45 ble.n 8013576 <rshift+0xa0>
|
|
80134ea: f011 011f ands.w r1, r1, #31
|
|
80134ee: eb04 0683 add.w r6, r4, r3, lsl #2
|
|
80134f2: eb04 0582 add.w r5, r4, r2, lsl #2
|
|
80134f6: d10c bne.n 8013512 <rshift+0x3c>
|
|
80134f8: f100 0710 add.w r7, r0, #16
|
|
80134fc: 4629 mov r1, r5
|
|
80134fe: 42b1 cmp r1, r6
|
|
8013500: d334 bcc.n 801356c <rshift+0x96>
|
|
8013502: 1a9b subs r3, r3, r2
|
|
8013504: 009b lsls r3, r3, #2
|
|
8013506: 1eea subs r2, r5, #3
|
|
8013508: 4296 cmp r6, r2
|
|
801350a: bf38 it cc
|
|
801350c: 2300 movcc r3, #0
|
|
801350e: 4423 add r3, r4
|
|
8013510: e015 b.n 801353e <rshift+0x68>
|
|
8013512: f854 7022 ldr.w r7, [r4, r2, lsl #2]
|
|
8013516: f1c1 0820 rsb r8, r1, #32
|
|
801351a: 40cf lsrs r7, r1
|
|
801351c: f105 0e04 add.w lr, r5, #4
|
|
8013520: 46a1 mov r9, r4
|
|
8013522: 4576 cmp r6, lr
|
|
8013524: 46f4 mov ip, lr
|
|
8013526: d815 bhi.n 8013554 <rshift+0x7e>
|
|
8013528: 1a9a subs r2, r3, r2
|
|
801352a: 0092 lsls r2, r2, #2
|
|
801352c: 3a04 subs r2, #4
|
|
801352e: 3501 adds r5, #1
|
|
8013530: 42ae cmp r6, r5
|
|
8013532: bf38 it cc
|
|
8013534: 2200 movcc r2, #0
|
|
8013536: 18a3 adds r3, r4, r2
|
|
8013538: 50a7 str r7, [r4, r2]
|
|
801353a: b107 cbz r7, 801353e <rshift+0x68>
|
|
801353c: 3304 adds r3, #4
|
|
801353e: 1b1a subs r2, r3, r4
|
|
8013540: 42a3 cmp r3, r4
|
|
8013542: ea4f 02a2 mov.w r2, r2, asr #2
|
|
8013546: bf08 it eq
|
|
8013548: 2300 moveq r3, #0
|
|
801354a: 6102 str r2, [r0, #16]
|
|
801354c: bf08 it eq
|
|
801354e: 6143 streq r3, [r0, #20]
|
|
8013550: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
8013554: f8dc c000 ldr.w ip, [ip]
|
|
8013558: fa0c fc08 lsl.w ip, ip, r8
|
|
801355c: ea4c 0707 orr.w r7, ip, r7
|
|
8013560: f849 7b04 str.w r7, [r9], #4
|
|
8013564: f85e 7b04 ldr.w r7, [lr], #4
|
|
8013568: 40cf lsrs r7, r1
|
|
801356a: e7da b.n 8013522 <rshift+0x4c>
|
|
801356c: f851 cb04 ldr.w ip, [r1], #4
|
|
8013570: f847 cf04 str.w ip, [r7, #4]!
|
|
8013574: e7c3 b.n 80134fe <rshift+0x28>
|
|
8013576: 4623 mov r3, r4
|
|
8013578: e7e1 b.n 801353e <rshift+0x68>
|
|
|
|
0801357a <__hexdig_fun>:
|
|
801357a: f1a0 0330 sub.w r3, r0, #48 @ 0x30
|
|
801357e: 2b09 cmp r3, #9
|
|
8013580: d802 bhi.n 8013588 <__hexdig_fun+0xe>
|
|
8013582: 3820 subs r0, #32
|
|
8013584: b2c0 uxtb r0, r0
|
|
8013586: 4770 bx lr
|
|
8013588: f1a0 0361 sub.w r3, r0, #97 @ 0x61
|
|
801358c: 2b05 cmp r3, #5
|
|
801358e: d801 bhi.n 8013594 <__hexdig_fun+0x1a>
|
|
8013590: 3847 subs r0, #71 @ 0x47
|
|
8013592: e7f7 b.n 8013584 <__hexdig_fun+0xa>
|
|
8013594: f1a0 0341 sub.w r3, r0, #65 @ 0x41
|
|
8013598: 2b05 cmp r3, #5
|
|
801359a: d801 bhi.n 80135a0 <__hexdig_fun+0x26>
|
|
801359c: 3827 subs r0, #39 @ 0x27
|
|
801359e: e7f1 b.n 8013584 <__hexdig_fun+0xa>
|
|
80135a0: 2000 movs r0, #0
|
|
80135a2: 4770 bx lr
|
|
|
|
080135a4 <__gethex>:
|
|
80135a4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80135a8: b085 sub sp, #20
|
|
80135aa: 468a mov sl, r1
|
|
80135ac: 9302 str r3, [sp, #8]
|
|
80135ae: 680b ldr r3, [r1, #0]
|
|
80135b0: 9001 str r0, [sp, #4]
|
|
80135b2: 4690 mov r8, r2
|
|
80135b4: 1c9c adds r4, r3, #2
|
|
80135b6: 46a1 mov r9, r4
|
|
80135b8: f814 0b01 ldrb.w r0, [r4], #1
|
|
80135bc: 2830 cmp r0, #48 @ 0x30
|
|
80135be: d0fa beq.n 80135b6 <__gethex+0x12>
|
|
80135c0: eba9 0303 sub.w r3, r9, r3
|
|
80135c4: f1a3 0b02 sub.w fp, r3, #2
|
|
80135c8: f7ff ffd7 bl 801357a <__hexdig_fun>
|
|
80135cc: 4605 mov r5, r0
|
|
80135ce: 2800 cmp r0, #0
|
|
80135d0: d168 bne.n 80136a4 <__gethex+0x100>
|
|
80135d2: 49a0 ldr r1, [pc, #640] @ (8013854 <__gethex+0x2b0>)
|
|
80135d4: 2201 movs r2, #1
|
|
80135d6: 4648 mov r0, r9
|
|
80135d8: f7fc ff8d bl 80104f6 <strncmp>
|
|
80135dc: 4607 mov r7, r0
|
|
80135de: 2800 cmp r0, #0
|
|
80135e0: d167 bne.n 80136b2 <__gethex+0x10e>
|
|
80135e2: f899 0001 ldrb.w r0, [r9, #1]
|
|
80135e6: 4626 mov r6, r4
|
|
80135e8: f7ff ffc7 bl 801357a <__hexdig_fun>
|
|
80135ec: 2800 cmp r0, #0
|
|
80135ee: d062 beq.n 80136b6 <__gethex+0x112>
|
|
80135f0: 4623 mov r3, r4
|
|
80135f2: 7818 ldrb r0, [r3, #0]
|
|
80135f4: 2830 cmp r0, #48 @ 0x30
|
|
80135f6: 4699 mov r9, r3
|
|
80135f8: f103 0301 add.w r3, r3, #1
|
|
80135fc: d0f9 beq.n 80135f2 <__gethex+0x4e>
|
|
80135fe: f7ff ffbc bl 801357a <__hexdig_fun>
|
|
8013602: fab0 f580 clz r5, r0
|
|
8013606: 096d lsrs r5, r5, #5
|
|
8013608: f04f 0b01 mov.w fp, #1
|
|
801360c: 464a mov r2, r9
|
|
801360e: 4616 mov r6, r2
|
|
8013610: 3201 adds r2, #1
|
|
8013612: 7830 ldrb r0, [r6, #0]
|
|
8013614: f7ff ffb1 bl 801357a <__hexdig_fun>
|
|
8013618: 2800 cmp r0, #0
|
|
801361a: d1f8 bne.n 801360e <__gethex+0x6a>
|
|
801361c: 498d ldr r1, [pc, #564] @ (8013854 <__gethex+0x2b0>)
|
|
801361e: 2201 movs r2, #1
|
|
8013620: 4630 mov r0, r6
|
|
8013622: f7fc ff68 bl 80104f6 <strncmp>
|
|
8013626: 2800 cmp r0, #0
|
|
8013628: d13f bne.n 80136aa <__gethex+0x106>
|
|
801362a: b944 cbnz r4, 801363e <__gethex+0x9a>
|
|
801362c: 1c74 adds r4, r6, #1
|
|
801362e: 4622 mov r2, r4
|
|
8013630: 4616 mov r6, r2
|
|
8013632: 3201 adds r2, #1
|
|
8013634: 7830 ldrb r0, [r6, #0]
|
|
8013636: f7ff ffa0 bl 801357a <__hexdig_fun>
|
|
801363a: 2800 cmp r0, #0
|
|
801363c: d1f8 bne.n 8013630 <__gethex+0x8c>
|
|
801363e: 1ba4 subs r4, r4, r6
|
|
8013640: 00a7 lsls r7, r4, #2
|
|
8013642: 7833 ldrb r3, [r6, #0]
|
|
8013644: f003 03df and.w r3, r3, #223 @ 0xdf
|
|
8013648: 2b50 cmp r3, #80 @ 0x50
|
|
801364a: d13e bne.n 80136ca <__gethex+0x126>
|
|
801364c: 7873 ldrb r3, [r6, #1]
|
|
801364e: 2b2b cmp r3, #43 @ 0x2b
|
|
8013650: d033 beq.n 80136ba <__gethex+0x116>
|
|
8013652: 2b2d cmp r3, #45 @ 0x2d
|
|
8013654: d034 beq.n 80136c0 <__gethex+0x11c>
|
|
8013656: 1c71 adds r1, r6, #1
|
|
8013658: 2400 movs r4, #0
|
|
801365a: 7808 ldrb r0, [r1, #0]
|
|
801365c: f7ff ff8d bl 801357a <__hexdig_fun>
|
|
8013660: 1e43 subs r3, r0, #1
|
|
8013662: b2db uxtb r3, r3
|
|
8013664: 2b18 cmp r3, #24
|
|
8013666: d830 bhi.n 80136ca <__gethex+0x126>
|
|
8013668: f1a0 0210 sub.w r2, r0, #16
|
|
801366c: f811 0f01 ldrb.w r0, [r1, #1]!
|
|
8013670: f7ff ff83 bl 801357a <__hexdig_fun>
|
|
8013674: f100 3cff add.w ip, r0, #4294967295 @ 0xffffffff
|
|
8013678: fa5f fc8c uxtb.w ip, ip
|
|
801367c: f1bc 0f18 cmp.w ip, #24
|
|
8013680: f04f 030a mov.w r3, #10
|
|
8013684: d91e bls.n 80136c4 <__gethex+0x120>
|
|
8013686: b104 cbz r4, 801368a <__gethex+0xe6>
|
|
8013688: 4252 negs r2, r2
|
|
801368a: 4417 add r7, r2
|
|
801368c: f8ca 1000 str.w r1, [sl]
|
|
8013690: b1ed cbz r5, 80136ce <__gethex+0x12a>
|
|
8013692: f1bb 0f00 cmp.w fp, #0
|
|
8013696: bf0c ite eq
|
|
8013698: 2506 moveq r5, #6
|
|
801369a: 2500 movne r5, #0
|
|
801369c: 4628 mov r0, r5
|
|
801369e: b005 add sp, #20
|
|
80136a0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80136a4: 2500 movs r5, #0
|
|
80136a6: 462c mov r4, r5
|
|
80136a8: e7b0 b.n 801360c <__gethex+0x68>
|
|
80136aa: 2c00 cmp r4, #0
|
|
80136ac: d1c7 bne.n 801363e <__gethex+0x9a>
|
|
80136ae: 4627 mov r7, r4
|
|
80136b0: e7c7 b.n 8013642 <__gethex+0x9e>
|
|
80136b2: 464e mov r6, r9
|
|
80136b4: 462f mov r7, r5
|
|
80136b6: 2501 movs r5, #1
|
|
80136b8: e7c3 b.n 8013642 <__gethex+0x9e>
|
|
80136ba: 2400 movs r4, #0
|
|
80136bc: 1cb1 adds r1, r6, #2
|
|
80136be: e7cc b.n 801365a <__gethex+0xb6>
|
|
80136c0: 2401 movs r4, #1
|
|
80136c2: e7fb b.n 80136bc <__gethex+0x118>
|
|
80136c4: fb03 0002 mla r0, r3, r2, r0
|
|
80136c8: e7ce b.n 8013668 <__gethex+0xc4>
|
|
80136ca: 4631 mov r1, r6
|
|
80136cc: e7de b.n 801368c <__gethex+0xe8>
|
|
80136ce: eba6 0309 sub.w r3, r6, r9
|
|
80136d2: 3b01 subs r3, #1
|
|
80136d4: 4629 mov r1, r5
|
|
80136d6: 2b07 cmp r3, #7
|
|
80136d8: dc0a bgt.n 80136f0 <__gethex+0x14c>
|
|
80136da: 9801 ldr r0, [sp, #4]
|
|
80136dc: f7fd ffa4 bl 8011628 <_Balloc>
|
|
80136e0: 4604 mov r4, r0
|
|
80136e2: b940 cbnz r0, 80136f6 <__gethex+0x152>
|
|
80136e4: 4b5c ldr r3, [pc, #368] @ (8013858 <__gethex+0x2b4>)
|
|
80136e6: 4602 mov r2, r0
|
|
80136e8: 21e4 movs r1, #228 @ 0xe4
|
|
80136ea: 485c ldr r0, [pc, #368] @ (801385c <__gethex+0x2b8>)
|
|
80136ec: f7fd f826 bl 801073c <__assert_func>
|
|
80136f0: 3101 adds r1, #1
|
|
80136f2: 105b asrs r3, r3, #1
|
|
80136f4: e7ef b.n 80136d6 <__gethex+0x132>
|
|
80136f6: f100 0a14 add.w sl, r0, #20
|
|
80136fa: 2300 movs r3, #0
|
|
80136fc: 4655 mov r5, sl
|
|
80136fe: 469b mov fp, r3
|
|
8013700: 45b1 cmp r9, r6
|
|
8013702: d337 bcc.n 8013774 <__gethex+0x1d0>
|
|
8013704: f845 bb04 str.w fp, [r5], #4
|
|
8013708: eba5 050a sub.w r5, r5, sl
|
|
801370c: 10ad asrs r5, r5, #2
|
|
801370e: 6125 str r5, [r4, #16]
|
|
8013710: 4658 mov r0, fp
|
|
8013712: f7fe f87b bl 801180c <__hi0bits>
|
|
8013716: 016d lsls r5, r5, #5
|
|
8013718: f8d8 6000 ldr.w r6, [r8]
|
|
801371c: 1a2d subs r5, r5, r0
|
|
801371e: 42b5 cmp r5, r6
|
|
8013720: dd54 ble.n 80137cc <__gethex+0x228>
|
|
8013722: 1bad subs r5, r5, r6
|
|
8013724: 4629 mov r1, r5
|
|
8013726: 4620 mov r0, r4
|
|
8013728: f7fe fc07 bl 8011f3a <__any_on>
|
|
801372c: 4681 mov r9, r0
|
|
801372e: b178 cbz r0, 8013750 <__gethex+0x1ac>
|
|
8013730: 1e6b subs r3, r5, #1
|
|
8013732: 1159 asrs r1, r3, #5
|
|
8013734: f003 021f and.w r2, r3, #31
|
|
8013738: f85a 1021 ldr.w r1, [sl, r1, lsl #2]
|
|
801373c: f04f 0901 mov.w r9, #1
|
|
8013740: fa09 f202 lsl.w r2, r9, r2
|
|
8013744: 420a tst r2, r1
|
|
8013746: d003 beq.n 8013750 <__gethex+0x1ac>
|
|
8013748: 454b cmp r3, r9
|
|
801374a: dc36 bgt.n 80137ba <__gethex+0x216>
|
|
801374c: f04f 0902 mov.w r9, #2
|
|
8013750: 4629 mov r1, r5
|
|
8013752: 4620 mov r0, r4
|
|
8013754: f7ff febf bl 80134d6 <rshift>
|
|
8013758: 442f add r7, r5
|
|
801375a: f8d8 3008 ldr.w r3, [r8, #8]
|
|
801375e: 42bb cmp r3, r7
|
|
8013760: da42 bge.n 80137e8 <__gethex+0x244>
|
|
8013762: 9801 ldr r0, [sp, #4]
|
|
8013764: 4621 mov r1, r4
|
|
8013766: f7fd ff9f bl 80116a8 <_Bfree>
|
|
801376a: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
801376c: 2300 movs r3, #0
|
|
801376e: 6013 str r3, [r2, #0]
|
|
8013770: 25a3 movs r5, #163 @ 0xa3
|
|
8013772: e793 b.n 801369c <__gethex+0xf8>
|
|
8013774: f816 2d01 ldrb.w r2, [r6, #-1]!
|
|
8013778: 2a2e cmp r2, #46 @ 0x2e
|
|
801377a: d012 beq.n 80137a2 <__gethex+0x1fe>
|
|
801377c: 2b20 cmp r3, #32
|
|
801377e: d104 bne.n 801378a <__gethex+0x1e6>
|
|
8013780: f845 bb04 str.w fp, [r5], #4
|
|
8013784: f04f 0b00 mov.w fp, #0
|
|
8013788: 465b mov r3, fp
|
|
801378a: 7830 ldrb r0, [r6, #0]
|
|
801378c: 9303 str r3, [sp, #12]
|
|
801378e: f7ff fef4 bl 801357a <__hexdig_fun>
|
|
8013792: 9b03 ldr r3, [sp, #12]
|
|
8013794: f000 000f and.w r0, r0, #15
|
|
8013798: 4098 lsls r0, r3
|
|
801379a: ea4b 0b00 orr.w fp, fp, r0
|
|
801379e: 3304 adds r3, #4
|
|
80137a0: e7ae b.n 8013700 <__gethex+0x15c>
|
|
80137a2: 45b1 cmp r9, r6
|
|
80137a4: d8ea bhi.n 801377c <__gethex+0x1d8>
|
|
80137a6: 492b ldr r1, [pc, #172] @ (8013854 <__gethex+0x2b0>)
|
|
80137a8: 9303 str r3, [sp, #12]
|
|
80137aa: 2201 movs r2, #1
|
|
80137ac: 4630 mov r0, r6
|
|
80137ae: f7fc fea2 bl 80104f6 <strncmp>
|
|
80137b2: 9b03 ldr r3, [sp, #12]
|
|
80137b4: 2800 cmp r0, #0
|
|
80137b6: d1e1 bne.n 801377c <__gethex+0x1d8>
|
|
80137b8: e7a2 b.n 8013700 <__gethex+0x15c>
|
|
80137ba: 1ea9 subs r1, r5, #2
|
|
80137bc: 4620 mov r0, r4
|
|
80137be: f7fe fbbc bl 8011f3a <__any_on>
|
|
80137c2: 2800 cmp r0, #0
|
|
80137c4: d0c2 beq.n 801374c <__gethex+0x1a8>
|
|
80137c6: f04f 0903 mov.w r9, #3
|
|
80137ca: e7c1 b.n 8013750 <__gethex+0x1ac>
|
|
80137cc: da09 bge.n 80137e2 <__gethex+0x23e>
|
|
80137ce: 1b75 subs r5, r6, r5
|
|
80137d0: 4621 mov r1, r4
|
|
80137d2: 9801 ldr r0, [sp, #4]
|
|
80137d4: 462a mov r2, r5
|
|
80137d6: f7fe f977 bl 8011ac8 <__lshift>
|
|
80137da: 1b7f subs r7, r7, r5
|
|
80137dc: 4604 mov r4, r0
|
|
80137de: f100 0a14 add.w sl, r0, #20
|
|
80137e2: f04f 0900 mov.w r9, #0
|
|
80137e6: e7b8 b.n 801375a <__gethex+0x1b6>
|
|
80137e8: f8d8 5004 ldr.w r5, [r8, #4]
|
|
80137ec: 42bd cmp r5, r7
|
|
80137ee: dd6f ble.n 80138d0 <__gethex+0x32c>
|
|
80137f0: 1bed subs r5, r5, r7
|
|
80137f2: 42ae cmp r6, r5
|
|
80137f4: dc34 bgt.n 8013860 <__gethex+0x2bc>
|
|
80137f6: f8d8 300c ldr.w r3, [r8, #12]
|
|
80137fa: 2b02 cmp r3, #2
|
|
80137fc: d022 beq.n 8013844 <__gethex+0x2a0>
|
|
80137fe: 2b03 cmp r3, #3
|
|
8013800: d024 beq.n 801384c <__gethex+0x2a8>
|
|
8013802: 2b01 cmp r3, #1
|
|
8013804: d115 bne.n 8013832 <__gethex+0x28e>
|
|
8013806: 42ae cmp r6, r5
|
|
8013808: d113 bne.n 8013832 <__gethex+0x28e>
|
|
801380a: 2e01 cmp r6, #1
|
|
801380c: d10b bne.n 8013826 <__gethex+0x282>
|
|
801380e: 9a02 ldr r2, [sp, #8]
|
|
8013810: f8d8 3004 ldr.w r3, [r8, #4]
|
|
8013814: 6013 str r3, [r2, #0]
|
|
8013816: 2301 movs r3, #1
|
|
8013818: 6123 str r3, [r4, #16]
|
|
801381a: f8ca 3000 str.w r3, [sl]
|
|
801381e: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
8013820: 2562 movs r5, #98 @ 0x62
|
|
8013822: 601c str r4, [r3, #0]
|
|
8013824: e73a b.n 801369c <__gethex+0xf8>
|
|
8013826: 1e71 subs r1, r6, #1
|
|
8013828: 4620 mov r0, r4
|
|
801382a: f7fe fb86 bl 8011f3a <__any_on>
|
|
801382e: 2800 cmp r0, #0
|
|
8013830: d1ed bne.n 801380e <__gethex+0x26a>
|
|
8013832: 9801 ldr r0, [sp, #4]
|
|
8013834: 4621 mov r1, r4
|
|
8013836: f7fd ff37 bl 80116a8 <_Bfree>
|
|
801383a: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
801383c: 2300 movs r3, #0
|
|
801383e: 6013 str r3, [r2, #0]
|
|
8013840: 2550 movs r5, #80 @ 0x50
|
|
8013842: e72b b.n 801369c <__gethex+0xf8>
|
|
8013844: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
8013846: 2b00 cmp r3, #0
|
|
8013848: d1f3 bne.n 8013832 <__gethex+0x28e>
|
|
801384a: e7e0 b.n 801380e <__gethex+0x26a>
|
|
801384c: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801384e: 2b00 cmp r3, #0
|
|
8013850: d1dd bne.n 801380e <__gethex+0x26a>
|
|
8013852: e7ee b.n 8013832 <__gethex+0x28e>
|
|
8013854: 08014941 .word 0x08014941
|
|
8013858: 080148d7 .word 0x080148d7
|
|
801385c: 0801495c .word 0x0801495c
|
|
8013860: 1e6f subs r7, r5, #1
|
|
8013862: f1b9 0f00 cmp.w r9, #0
|
|
8013866: d130 bne.n 80138ca <__gethex+0x326>
|
|
8013868: b127 cbz r7, 8013874 <__gethex+0x2d0>
|
|
801386a: 4639 mov r1, r7
|
|
801386c: 4620 mov r0, r4
|
|
801386e: f7fe fb64 bl 8011f3a <__any_on>
|
|
8013872: 4681 mov r9, r0
|
|
8013874: 117a asrs r2, r7, #5
|
|
8013876: 2301 movs r3, #1
|
|
8013878: f85a 2022 ldr.w r2, [sl, r2, lsl #2]
|
|
801387c: f007 071f and.w r7, r7, #31
|
|
8013880: 40bb lsls r3, r7
|
|
8013882: 4213 tst r3, r2
|
|
8013884: 4629 mov r1, r5
|
|
8013886: 4620 mov r0, r4
|
|
8013888: bf18 it ne
|
|
801388a: f049 0902 orrne.w r9, r9, #2
|
|
801388e: f7ff fe22 bl 80134d6 <rshift>
|
|
8013892: f8d8 7004 ldr.w r7, [r8, #4]
|
|
8013896: 1b76 subs r6, r6, r5
|
|
8013898: 2502 movs r5, #2
|
|
801389a: f1b9 0f00 cmp.w r9, #0
|
|
801389e: d047 beq.n 8013930 <__gethex+0x38c>
|
|
80138a0: f8d8 300c ldr.w r3, [r8, #12]
|
|
80138a4: 2b02 cmp r3, #2
|
|
80138a6: d015 beq.n 80138d4 <__gethex+0x330>
|
|
80138a8: 2b03 cmp r3, #3
|
|
80138aa: d017 beq.n 80138dc <__gethex+0x338>
|
|
80138ac: 2b01 cmp r3, #1
|
|
80138ae: d109 bne.n 80138c4 <__gethex+0x320>
|
|
80138b0: f019 0f02 tst.w r9, #2
|
|
80138b4: d006 beq.n 80138c4 <__gethex+0x320>
|
|
80138b6: f8da 3000 ldr.w r3, [sl]
|
|
80138ba: ea49 0903 orr.w r9, r9, r3
|
|
80138be: f019 0f01 tst.w r9, #1
|
|
80138c2: d10e bne.n 80138e2 <__gethex+0x33e>
|
|
80138c4: f045 0510 orr.w r5, r5, #16
|
|
80138c8: e032 b.n 8013930 <__gethex+0x38c>
|
|
80138ca: f04f 0901 mov.w r9, #1
|
|
80138ce: e7d1 b.n 8013874 <__gethex+0x2d0>
|
|
80138d0: 2501 movs r5, #1
|
|
80138d2: e7e2 b.n 801389a <__gethex+0x2f6>
|
|
80138d4: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
80138d6: f1c3 0301 rsb r3, r3, #1
|
|
80138da: 930f str r3, [sp, #60] @ 0x3c
|
|
80138dc: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
80138de: 2b00 cmp r3, #0
|
|
80138e0: d0f0 beq.n 80138c4 <__gethex+0x320>
|
|
80138e2: f8d4 b010 ldr.w fp, [r4, #16]
|
|
80138e6: f104 0314 add.w r3, r4, #20
|
|
80138ea: ea4f 0a8b mov.w sl, fp, lsl #2
|
|
80138ee: eb03 018b add.w r1, r3, fp, lsl #2
|
|
80138f2: f04f 0c00 mov.w ip, #0
|
|
80138f6: 4618 mov r0, r3
|
|
80138f8: f853 2b04 ldr.w r2, [r3], #4
|
|
80138fc: f1b2 3fff cmp.w r2, #4294967295 @ 0xffffffff
|
|
8013900: d01b beq.n 801393a <__gethex+0x396>
|
|
8013902: 3201 adds r2, #1
|
|
8013904: 6002 str r2, [r0, #0]
|
|
8013906: 2d02 cmp r5, #2
|
|
8013908: f104 0314 add.w r3, r4, #20
|
|
801390c: d13c bne.n 8013988 <__gethex+0x3e4>
|
|
801390e: f8d8 2000 ldr.w r2, [r8]
|
|
8013912: 3a01 subs r2, #1
|
|
8013914: 42b2 cmp r2, r6
|
|
8013916: d109 bne.n 801392c <__gethex+0x388>
|
|
8013918: 1171 asrs r1, r6, #5
|
|
801391a: 2201 movs r2, #1
|
|
801391c: f853 3021 ldr.w r3, [r3, r1, lsl #2]
|
|
8013920: f006 061f and.w r6, r6, #31
|
|
8013924: fa02 f606 lsl.w r6, r2, r6
|
|
8013928: 421e tst r6, r3
|
|
801392a: d13a bne.n 80139a2 <__gethex+0x3fe>
|
|
801392c: f045 0520 orr.w r5, r5, #32
|
|
8013930: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
8013932: 601c str r4, [r3, #0]
|
|
8013934: 9b02 ldr r3, [sp, #8]
|
|
8013936: 601f str r7, [r3, #0]
|
|
8013938: e6b0 b.n 801369c <__gethex+0xf8>
|
|
801393a: 4299 cmp r1, r3
|
|
801393c: f843 cc04 str.w ip, [r3, #-4]
|
|
8013940: d8d9 bhi.n 80138f6 <__gethex+0x352>
|
|
8013942: 68a3 ldr r3, [r4, #8]
|
|
8013944: 459b cmp fp, r3
|
|
8013946: db17 blt.n 8013978 <__gethex+0x3d4>
|
|
8013948: 6861 ldr r1, [r4, #4]
|
|
801394a: 9801 ldr r0, [sp, #4]
|
|
801394c: 3101 adds r1, #1
|
|
801394e: f7fd fe6b bl 8011628 <_Balloc>
|
|
8013952: 4681 mov r9, r0
|
|
8013954: b918 cbnz r0, 801395e <__gethex+0x3ba>
|
|
8013956: 4b1a ldr r3, [pc, #104] @ (80139c0 <__gethex+0x41c>)
|
|
8013958: 4602 mov r2, r0
|
|
801395a: 2184 movs r1, #132 @ 0x84
|
|
801395c: e6c5 b.n 80136ea <__gethex+0x146>
|
|
801395e: 6922 ldr r2, [r4, #16]
|
|
8013960: 3202 adds r2, #2
|
|
8013962: f104 010c add.w r1, r4, #12
|
|
8013966: 0092 lsls r2, r2, #2
|
|
8013968: 300c adds r0, #12
|
|
801396a: f7fc fed2 bl 8010712 <memcpy>
|
|
801396e: 4621 mov r1, r4
|
|
8013970: 9801 ldr r0, [sp, #4]
|
|
8013972: f7fd fe99 bl 80116a8 <_Bfree>
|
|
8013976: 464c mov r4, r9
|
|
8013978: 6923 ldr r3, [r4, #16]
|
|
801397a: 1c5a adds r2, r3, #1
|
|
801397c: eb04 0383 add.w r3, r4, r3, lsl #2
|
|
8013980: 6122 str r2, [r4, #16]
|
|
8013982: 2201 movs r2, #1
|
|
8013984: 615a str r2, [r3, #20]
|
|
8013986: e7be b.n 8013906 <__gethex+0x362>
|
|
8013988: 6922 ldr r2, [r4, #16]
|
|
801398a: 455a cmp r2, fp
|
|
801398c: dd0b ble.n 80139a6 <__gethex+0x402>
|
|
801398e: 2101 movs r1, #1
|
|
8013990: 4620 mov r0, r4
|
|
8013992: f7ff fda0 bl 80134d6 <rshift>
|
|
8013996: f8d8 3008 ldr.w r3, [r8, #8]
|
|
801399a: 3701 adds r7, #1
|
|
801399c: 42bb cmp r3, r7
|
|
801399e: f6ff aee0 blt.w 8013762 <__gethex+0x1be>
|
|
80139a2: 2501 movs r5, #1
|
|
80139a4: e7c2 b.n 801392c <__gethex+0x388>
|
|
80139a6: f016 061f ands.w r6, r6, #31
|
|
80139aa: d0fa beq.n 80139a2 <__gethex+0x3fe>
|
|
80139ac: 4453 add r3, sl
|
|
80139ae: f1c6 0620 rsb r6, r6, #32
|
|
80139b2: f853 0c04 ldr.w r0, [r3, #-4]
|
|
80139b6: f7fd ff29 bl 801180c <__hi0bits>
|
|
80139ba: 42b0 cmp r0, r6
|
|
80139bc: dbe7 blt.n 801398e <__gethex+0x3ea>
|
|
80139be: e7f0 b.n 80139a2 <__gethex+0x3fe>
|
|
80139c0: 080148d7 .word 0x080148d7
|
|
|
|
080139c4 <L_shift>:
|
|
80139c4: f1c2 0208 rsb r2, r2, #8
|
|
80139c8: 0092 lsls r2, r2, #2
|
|
80139ca: b570 push {r4, r5, r6, lr}
|
|
80139cc: f1c2 0620 rsb r6, r2, #32
|
|
80139d0: 6843 ldr r3, [r0, #4]
|
|
80139d2: 6804 ldr r4, [r0, #0]
|
|
80139d4: fa03 f506 lsl.w r5, r3, r6
|
|
80139d8: 432c orrs r4, r5
|
|
80139da: 40d3 lsrs r3, r2
|
|
80139dc: 6004 str r4, [r0, #0]
|
|
80139de: f840 3f04 str.w r3, [r0, #4]!
|
|
80139e2: 4288 cmp r0, r1
|
|
80139e4: d3f4 bcc.n 80139d0 <L_shift+0xc>
|
|
80139e6: bd70 pop {r4, r5, r6, pc}
|
|
|
|
080139e8 <__match>:
|
|
80139e8: b530 push {r4, r5, lr}
|
|
80139ea: 6803 ldr r3, [r0, #0]
|
|
80139ec: 3301 adds r3, #1
|
|
80139ee: f811 4b01 ldrb.w r4, [r1], #1
|
|
80139f2: b914 cbnz r4, 80139fa <__match+0x12>
|
|
80139f4: 6003 str r3, [r0, #0]
|
|
80139f6: 2001 movs r0, #1
|
|
80139f8: bd30 pop {r4, r5, pc}
|
|
80139fa: f813 2b01 ldrb.w r2, [r3], #1
|
|
80139fe: f1a2 0541 sub.w r5, r2, #65 @ 0x41
|
|
8013a02: 2d19 cmp r5, #25
|
|
8013a04: bf98 it ls
|
|
8013a06: 3220 addls r2, #32
|
|
8013a08: 42a2 cmp r2, r4
|
|
8013a0a: d0f0 beq.n 80139ee <__match+0x6>
|
|
8013a0c: 2000 movs r0, #0
|
|
8013a0e: e7f3 b.n 80139f8 <__match+0x10>
|
|
|
|
08013a10 <__hexnan>:
|
|
8013a10: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8013a14: 680b ldr r3, [r1, #0]
|
|
8013a16: 6801 ldr r1, [r0, #0]
|
|
8013a18: 115e asrs r6, r3, #5
|
|
8013a1a: eb02 0686 add.w r6, r2, r6, lsl #2
|
|
8013a1e: f013 031f ands.w r3, r3, #31
|
|
8013a22: b087 sub sp, #28
|
|
8013a24: bf18 it ne
|
|
8013a26: 3604 addne r6, #4
|
|
8013a28: 2500 movs r5, #0
|
|
8013a2a: 1f37 subs r7, r6, #4
|
|
8013a2c: 4682 mov sl, r0
|
|
8013a2e: 4690 mov r8, r2
|
|
8013a30: 9301 str r3, [sp, #4]
|
|
8013a32: f846 5c04 str.w r5, [r6, #-4]
|
|
8013a36: 46b9 mov r9, r7
|
|
8013a38: 463c mov r4, r7
|
|
8013a3a: 9502 str r5, [sp, #8]
|
|
8013a3c: 46ab mov fp, r5
|
|
8013a3e: 784a ldrb r2, [r1, #1]
|
|
8013a40: 1c4b adds r3, r1, #1
|
|
8013a42: 9303 str r3, [sp, #12]
|
|
8013a44: b342 cbz r2, 8013a98 <__hexnan+0x88>
|
|
8013a46: 4610 mov r0, r2
|
|
8013a48: 9105 str r1, [sp, #20]
|
|
8013a4a: 9204 str r2, [sp, #16]
|
|
8013a4c: f7ff fd95 bl 801357a <__hexdig_fun>
|
|
8013a50: 2800 cmp r0, #0
|
|
8013a52: d151 bne.n 8013af8 <__hexnan+0xe8>
|
|
8013a54: 9a04 ldr r2, [sp, #16]
|
|
8013a56: 9905 ldr r1, [sp, #20]
|
|
8013a58: 2a20 cmp r2, #32
|
|
8013a5a: d818 bhi.n 8013a8e <__hexnan+0x7e>
|
|
8013a5c: 9b02 ldr r3, [sp, #8]
|
|
8013a5e: 459b cmp fp, r3
|
|
8013a60: dd13 ble.n 8013a8a <__hexnan+0x7a>
|
|
8013a62: 454c cmp r4, r9
|
|
8013a64: d206 bcs.n 8013a74 <__hexnan+0x64>
|
|
8013a66: 2d07 cmp r5, #7
|
|
8013a68: dc04 bgt.n 8013a74 <__hexnan+0x64>
|
|
8013a6a: 462a mov r2, r5
|
|
8013a6c: 4649 mov r1, r9
|
|
8013a6e: 4620 mov r0, r4
|
|
8013a70: f7ff ffa8 bl 80139c4 <L_shift>
|
|
8013a74: 4544 cmp r4, r8
|
|
8013a76: d952 bls.n 8013b1e <__hexnan+0x10e>
|
|
8013a78: 2300 movs r3, #0
|
|
8013a7a: f1a4 0904 sub.w r9, r4, #4
|
|
8013a7e: f844 3c04 str.w r3, [r4, #-4]
|
|
8013a82: f8cd b008 str.w fp, [sp, #8]
|
|
8013a86: 464c mov r4, r9
|
|
8013a88: 461d mov r5, r3
|
|
8013a8a: 9903 ldr r1, [sp, #12]
|
|
8013a8c: e7d7 b.n 8013a3e <__hexnan+0x2e>
|
|
8013a8e: 2a29 cmp r2, #41 @ 0x29
|
|
8013a90: d157 bne.n 8013b42 <__hexnan+0x132>
|
|
8013a92: 3102 adds r1, #2
|
|
8013a94: f8ca 1000 str.w r1, [sl]
|
|
8013a98: f1bb 0f00 cmp.w fp, #0
|
|
8013a9c: d051 beq.n 8013b42 <__hexnan+0x132>
|
|
8013a9e: 454c cmp r4, r9
|
|
8013aa0: d206 bcs.n 8013ab0 <__hexnan+0xa0>
|
|
8013aa2: 2d07 cmp r5, #7
|
|
8013aa4: dc04 bgt.n 8013ab0 <__hexnan+0xa0>
|
|
8013aa6: 462a mov r2, r5
|
|
8013aa8: 4649 mov r1, r9
|
|
8013aaa: 4620 mov r0, r4
|
|
8013aac: f7ff ff8a bl 80139c4 <L_shift>
|
|
8013ab0: 4544 cmp r4, r8
|
|
8013ab2: d936 bls.n 8013b22 <__hexnan+0x112>
|
|
8013ab4: f1a8 0204 sub.w r2, r8, #4
|
|
8013ab8: 4623 mov r3, r4
|
|
8013aba: f853 1b04 ldr.w r1, [r3], #4
|
|
8013abe: f842 1f04 str.w r1, [r2, #4]!
|
|
8013ac2: 429f cmp r7, r3
|
|
8013ac4: d2f9 bcs.n 8013aba <__hexnan+0xaa>
|
|
8013ac6: 1b3b subs r3, r7, r4
|
|
8013ac8: f023 0303 bic.w r3, r3, #3
|
|
8013acc: 3304 adds r3, #4
|
|
8013ace: 3401 adds r4, #1
|
|
8013ad0: 3e03 subs r6, #3
|
|
8013ad2: 42b4 cmp r4, r6
|
|
8013ad4: bf88 it hi
|
|
8013ad6: 2304 movhi r3, #4
|
|
8013ad8: 4443 add r3, r8
|
|
8013ada: 2200 movs r2, #0
|
|
8013adc: f843 2b04 str.w r2, [r3], #4
|
|
8013ae0: 429f cmp r7, r3
|
|
8013ae2: d2fb bcs.n 8013adc <__hexnan+0xcc>
|
|
8013ae4: 683b ldr r3, [r7, #0]
|
|
8013ae6: b91b cbnz r3, 8013af0 <__hexnan+0xe0>
|
|
8013ae8: 4547 cmp r7, r8
|
|
8013aea: d128 bne.n 8013b3e <__hexnan+0x12e>
|
|
8013aec: 2301 movs r3, #1
|
|
8013aee: 603b str r3, [r7, #0]
|
|
8013af0: 2005 movs r0, #5
|
|
8013af2: b007 add sp, #28
|
|
8013af4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8013af8: 3501 adds r5, #1
|
|
8013afa: 2d08 cmp r5, #8
|
|
8013afc: f10b 0b01 add.w fp, fp, #1
|
|
8013b00: dd06 ble.n 8013b10 <__hexnan+0x100>
|
|
8013b02: 4544 cmp r4, r8
|
|
8013b04: d9c1 bls.n 8013a8a <__hexnan+0x7a>
|
|
8013b06: 2300 movs r3, #0
|
|
8013b08: f844 3c04 str.w r3, [r4, #-4]
|
|
8013b0c: 2501 movs r5, #1
|
|
8013b0e: 3c04 subs r4, #4
|
|
8013b10: 6822 ldr r2, [r4, #0]
|
|
8013b12: f000 000f and.w r0, r0, #15
|
|
8013b16: ea40 1002 orr.w r0, r0, r2, lsl #4
|
|
8013b1a: 6020 str r0, [r4, #0]
|
|
8013b1c: e7b5 b.n 8013a8a <__hexnan+0x7a>
|
|
8013b1e: 2508 movs r5, #8
|
|
8013b20: e7b3 b.n 8013a8a <__hexnan+0x7a>
|
|
8013b22: 9b01 ldr r3, [sp, #4]
|
|
8013b24: 2b00 cmp r3, #0
|
|
8013b26: d0dd beq.n 8013ae4 <__hexnan+0xd4>
|
|
8013b28: f1c3 0320 rsb r3, r3, #32
|
|
8013b2c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8013b30: 40da lsrs r2, r3
|
|
8013b32: f856 3c04 ldr.w r3, [r6, #-4]
|
|
8013b36: 4013 ands r3, r2
|
|
8013b38: f846 3c04 str.w r3, [r6, #-4]
|
|
8013b3c: e7d2 b.n 8013ae4 <__hexnan+0xd4>
|
|
8013b3e: 3f04 subs r7, #4
|
|
8013b40: e7d0 b.n 8013ae4 <__hexnan+0xd4>
|
|
8013b42: 2004 movs r0, #4
|
|
8013b44: e7d5 b.n 8013af2 <__hexnan+0xe2>
|
|
|
|
08013b46 <__ascii_mbtowc>:
|
|
8013b46: b082 sub sp, #8
|
|
8013b48: b901 cbnz r1, 8013b4c <__ascii_mbtowc+0x6>
|
|
8013b4a: a901 add r1, sp, #4
|
|
8013b4c: b142 cbz r2, 8013b60 <__ascii_mbtowc+0x1a>
|
|
8013b4e: b14b cbz r3, 8013b64 <__ascii_mbtowc+0x1e>
|
|
8013b50: 7813 ldrb r3, [r2, #0]
|
|
8013b52: 600b str r3, [r1, #0]
|
|
8013b54: 7812 ldrb r2, [r2, #0]
|
|
8013b56: 1e10 subs r0, r2, #0
|
|
8013b58: bf18 it ne
|
|
8013b5a: 2001 movne r0, #1
|
|
8013b5c: b002 add sp, #8
|
|
8013b5e: 4770 bx lr
|
|
8013b60: 4610 mov r0, r2
|
|
8013b62: e7fb b.n 8013b5c <__ascii_mbtowc+0x16>
|
|
8013b64: f06f 0001 mvn.w r0, #1
|
|
8013b68: e7f8 b.n 8013b5c <__ascii_mbtowc+0x16>
|
|
|
|
08013b6a <_realloc_r>:
|
|
8013b6a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8013b6e: 4607 mov r7, r0
|
|
8013b70: 4614 mov r4, r2
|
|
8013b72: 460d mov r5, r1
|
|
8013b74: b921 cbnz r1, 8013b80 <_realloc_r+0x16>
|
|
8013b76: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
8013b7a: 4611 mov r1, r2
|
|
8013b7c: f7fd bcc8 b.w 8011510 <_malloc_r>
|
|
8013b80: b92a cbnz r2, 8013b8e <_realloc_r+0x24>
|
|
8013b82: f7fd fc51 bl 8011428 <_free_r>
|
|
8013b86: 4625 mov r5, r4
|
|
8013b88: 4628 mov r0, r5
|
|
8013b8a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
8013b8e: f000 f86b bl 8013c68 <_malloc_usable_size_r>
|
|
8013b92: 4284 cmp r4, r0
|
|
8013b94: 4606 mov r6, r0
|
|
8013b96: d802 bhi.n 8013b9e <_realloc_r+0x34>
|
|
8013b98: ebb4 0f50 cmp.w r4, r0, lsr #1
|
|
8013b9c: d8f4 bhi.n 8013b88 <_realloc_r+0x1e>
|
|
8013b9e: 4621 mov r1, r4
|
|
8013ba0: 4638 mov r0, r7
|
|
8013ba2: f7fd fcb5 bl 8011510 <_malloc_r>
|
|
8013ba6: 4680 mov r8, r0
|
|
8013ba8: b908 cbnz r0, 8013bae <_realloc_r+0x44>
|
|
8013baa: 4645 mov r5, r8
|
|
8013bac: e7ec b.n 8013b88 <_realloc_r+0x1e>
|
|
8013bae: 42b4 cmp r4, r6
|
|
8013bb0: 4622 mov r2, r4
|
|
8013bb2: 4629 mov r1, r5
|
|
8013bb4: bf28 it cs
|
|
8013bb6: 4632 movcs r2, r6
|
|
8013bb8: f7fc fdab bl 8010712 <memcpy>
|
|
8013bbc: 4629 mov r1, r5
|
|
8013bbe: 4638 mov r0, r7
|
|
8013bc0: f7fd fc32 bl 8011428 <_free_r>
|
|
8013bc4: e7f1 b.n 8013baa <_realloc_r+0x40>
|
|
|
|
08013bc6 <__ascii_wctomb>:
|
|
8013bc6: 4603 mov r3, r0
|
|
8013bc8: 4608 mov r0, r1
|
|
8013bca: b141 cbz r1, 8013bde <__ascii_wctomb+0x18>
|
|
8013bcc: 2aff cmp r2, #255 @ 0xff
|
|
8013bce: d904 bls.n 8013bda <__ascii_wctomb+0x14>
|
|
8013bd0: 228a movs r2, #138 @ 0x8a
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8013bd2: 601a str r2, [r3, #0]
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|
8013bd4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8013bd8: 4770 bx lr
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|
8013bda: 700a strb r2, [r1, #0]
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|
8013bdc: 2001 movs r0, #1
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|
8013bde: 4770 bx lr
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|
|
|
08013be0 <_raise_r>:
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|
8013be0: 291f cmp r1, #31
|
|
8013be2: b538 push {r3, r4, r5, lr}
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|
8013be4: 4605 mov r5, r0
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|
8013be6: 460c mov r4, r1
|
|
8013be8: d904 bls.n 8013bf4 <_raise_r+0x14>
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|
8013bea: 2316 movs r3, #22
|
|
8013bec: 6003 str r3, [r0, #0]
|
|
8013bee: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8013bf2: bd38 pop {r3, r4, r5, pc}
|
|
8013bf4: 6bc2 ldr r2, [r0, #60] @ 0x3c
|
|
8013bf6: b112 cbz r2, 8013bfe <_raise_r+0x1e>
|
|
8013bf8: f852 3021 ldr.w r3, [r2, r1, lsl #2]
|
|
8013bfc: b94b cbnz r3, 8013c12 <_raise_r+0x32>
|
|
8013bfe: 4628 mov r0, r5
|
|
8013c00: f000 f830 bl 8013c64 <_getpid_r>
|
|
8013c04: 4622 mov r2, r4
|
|
8013c06: 4601 mov r1, r0
|
|
8013c08: 4628 mov r0, r5
|
|
8013c0a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8013c0e: f000 b817 b.w 8013c40 <_kill_r>
|
|
8013c12: 2b01 cmp r3, #1
|
|
8013c14: d00a beq.n 8013c2c <_raise_r+0x4c>
|
|
8013c16: 1c59 adds r1, r3, #1
|
|
8013c18: d103 bne.n 8013c22 <_raise_r+0x42>
|
|
8013c1a: 2316 movs r3, #22
|
|
8013c1c: 6003 str r3, [r0, #0]
|
|
8013c1e: 2001 movs r0, #1
|
|
8013c20: e7e7 b.n 8013bf2 <_raise_r+0x12>
|
|
8013c22: 2100 movs r1, #0
|
|
8013c24: f842 1024 str.w r1, [r2, r4, lsl #2]
|
|
8013c28: 4620 mov r0, r4
|
|
8013c2a: 4798 blx r3
|
|
8013c2c: 2000 movs r0, #0
|
|
8013c2e: e7e0 b.n 8013bf2 <_raise_r+0x12>
|
|
|
|
08013c30 <raise>:
|
|
8013c30: 4b02 ldr r3, [pc, #8] @ (8013c3c <raise+0xc>)
|
|
8013c32: 4601 mov r1, r0
|
|
8013c34: 6818 ldr r0, [r3, #0]
|
|
8013c36: f7ff bfd3 b.w 8013be0 <_raise_r>
|
|
8013c3a: bf00 nop
|
|
8013c3c: 200000e0 .word 0x200000e0
|
|
|
|
08013c40 <_kill_r>:
|
|
8013c40: b538 push {r3, r4, r5, lr}
|
|
8013c42: 4d07 ldr r5, [pc, #28] @ (8013c60 <_kill_r+0x20>)
|
|
8013c44: 2300 movs r3, #0
|
|
8013c46: 4604 mov r4, r0
|
|
8013c48: 4608 mov r0, r1
|
|
8013c4a: 4611 mov r1, r2
|
|
8013c4c: 602b str r3, [r5, #0]
|
|
8013c4e: f7ef ff31 bl 8003ab4 <_kill>
|
|
8013c52: 1c43 adds r3, r0, #1
|
|
8013c54: d102 bne.n 8013c5c <_kill_r+0x1c>
|
|
8013c56: 682b ldr r3, [r5, #0]
|
|
8013c58: b103 cbz r3, 8013c5c <_kill_r+0x1c>
|
|
8013c5a: 6023 str r3, [r4, #0]
|
|
8013c5c: bd38 pop {r3, r4, r5, pc}
|
|
8013c5e: bf00 nop
|
|
8013c60: 200036c8 .word 0x200036c8
|
|
|
|
08013c64 <_getpid_r>:
|
|
8013c64: f7ef bf1e b.w 8003aa4 <_getpid>
|
|
|
|
08013c68 <_malloc_usable_size_r>:
|
|
8013c68: f851 3c04 ldr.w r3, [r1, #-4]
|
|
8013c6c: 1f18 subs r0, r3, #4
|
|
8013c6e: 2b00 cmp r3, #0
|
|
8013c70: bfbc itt lt
|
|
8013c72: 580b ldrlt r3, [r1, r0]
|
|
8013c74: 18c0 addlt r0, r0, r3
|
|
8013c76: 4770 bx lr
|
|
|
|
08013c78 <_init>:
|
|
8013c78: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8013c7a: bf00 nop
|
|
8013c7c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8013c7e: bc08 pop {r3}
|
|
8013c80: 469e mov lr, r3
|
|
8013c82: 4770 bx lr
|
|
|
|
08013c84 <_fini>:
|
|
8013c84: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8013c86: bf00 nop
|
|
8013c88: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8013c8a: bc08 pop {r3}
|
|
8013c8c: 469e mov lr, r3
|
|
8013c8e: 4770 bx lr
|