23899 lines
890 KiB
Plaintext
23899 lines
890 KiB
Plaintext
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P3_SETR2.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00009e10 08000190 08000190 00001190 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 000004f4 08009fa0 08009fa0 0000afa0 2**3
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800a494 0800a494 0000c298 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 0800a494 0800a494 0000b494 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 0800a49c 0800a49c 0000c298 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 0800a49c 0800a49c 0000b49c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 0800a4a0 0800a4a0 0000b4a0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000298 20000000 0800a4a4 0000c000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 0000092c 20000298 0800a73c 0000c298 2**2
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ALLOC
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10 ._user_heap_stack 00000604 20000bc4 0800a73c 0000cbc4 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0000c298 2**0
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CONTENTS, READONLY
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12 .debug_info 0001bd49 00000000 00000000 0000c2c8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 0000459b 00000000 00000000 00028011 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00001a80 00000000 00000000 0002c5b0 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 00001421 00000000 00000000 0002e030 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_line 00015bdc 00000000 00000000 0002f451 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_str 00007b9a 00000000 00000000 0004502d 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .comment 00000043 00000000 00000000 0004cbc7 2**0
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CONTENTS, READONLY
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19 .debug_frame 00007c44 00000000 00000000 0004cc0c 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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20 .debug_line_str 00000052 00000000 00000000 00054850 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000190 <__do_global_dtors_aux>:
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8000190: b510 push {r4, lr}
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8000192: 4c05 ldr r4, [pc, #20] @ (80001a8 <__do_global_dtors_aux+0x18>)
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8000194: 7823 ldrb r3, [r4, #0]
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8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16>
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8000198: 4b04 ldr r3, [pc, #16] @ (80001ac <__do_global_dtors_aux+0x1c>)
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800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12>
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800019c: 4804 ldr r0, [pc, #16] @ (80001b0 <__do_global_dtors_aux+0x20>)
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800019e: f3af 8000 nop.w
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80001a2: 2301 movs r3, #1
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80001a4: 7023 strb r3, [r4, #0]
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80001a6: bd10 pop {r4, pc}
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80001a8: 20000298 .word 0x20000298
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80001ac: 00000000 .word 0x00000000
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80001b0: 08009f88 .word 0x08009f88
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080001b4 <frame_dummy>:
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80001b4: b508 push {r3, lr}
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80001b6: 4b03 ldr r3, [pc, #12] @ (80001c4 <frame_dummy+0x10>)
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80001b8: b11b cbz r3, 80001c2 <frame_dummy+0xe>
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80001ba: 4903 ldr r1, [pc, #12] @ (80001c8 <frame_dummy+0x14>)
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80001bc: 4803 ldr r0, [pc, #12] @ (80001cc <frame_dummy+0x18>)
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80001be: f3af 8000 nop.w
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80001c2: bd08 pop {r3, pc}
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80001c4: 00000000 .word 0x00000000
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80001c8: 2000029c .word 0x2000029c
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80001cc: 08009f88 .word 0x08009f88
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080001d0 <memchr>:
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80001d0: f001 01ff and.w r1, r1, #255 @ 0xff
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80001d4: 2a10 cmp r2, #16
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80001d6: db2b blt.n 8000230 <memchr+0x60>
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80001d8: f010 0f07 tst.w r0, #7
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80001dc: d008 beq.n 80001f0 <memchr+0x20>
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80001de: f810 3b01 ldrb.w r3, [r0], #1
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80001e2: 3a01 subs r2, #1
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80001e4: 428b cmp r3, r1
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80001e6: d02d beq.n 8000244 <memchr+0x74>
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80001e8: f010 0f07 tst.w r0, #7
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80001ec: b342 cbz r2, 8000240 <memchr+0x70>
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80001ee: d1f6 bne.n 80001de <memchr+0xe>
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80001f0: b4f0 push {r4, r5, r6, r7}
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80001f2: ea41 2101 orr.w r1, r1, r1, lsl #8
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80001f6: ea41 4101 orr.w r1, r1, r1, lsl #16
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80001fa: f022 0407 bic.w r4, r2, #7
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80001fe: f07f 0700 mvns.w r7, #0
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8000202: 2300 movs r3, #0
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8000204: e8f0 5602 ldrd r5, r6, [r0], #8
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8000208: 3c08 subs r4, #8
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800020a: ea85 0501 eor.w r5, r5, r1
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800020e: ea86 0601 eor.w r6, r6, r1
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8000212: fa85 f547 uadd8 r5, r5, r7
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8000216: faa3 f587 sel r5, r3, r7
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800021a: fa86 f647 uadd8 r6, r6, r7
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800021e: faa5 f687 sel r6, r5, r7
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8000222: b98e cbnz r6, 8000248 <memchr+0x78>
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8000224: d1ee bne.n 8000204 <memchr+0x34>
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8000226: bcf0 pop {r4, r5, r6, r7}
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8000228: f001 01ff and.w r1, r1, #255 @ 0xff
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800022c: f002 0207 and.w r2, r2, #7
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8000230: b132 cbz r2, 8000240 <memchr+0x70>
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8000232: f810 3b01 ldrb.w r3, [r0], #1
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8000236: 3a01 subs r2, #1
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8000238: ea83 0301 eor.w r3, r3, r1
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800023c: b113 cbz r3, 8000244 <memchr+0x74>
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800023e: d1f8 bne.n 8000232 <memchr+0x62>
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8000240: 2000 movs r0, #0
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8000242: 4770 bx lr
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8000244: 3801 subs r0, #1
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8000246: 4770 bx lr
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8000248: 2d00 cmp r5, #0
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800024a: bf06 itte eq
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800024c: 4635 moveq r5, r6
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800024e: 3803 subeq r0, #3
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8000250: 3807 subne r0, #7
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8000252: f015 0f01 tst.w r5, #1
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8000256: d107 bne.n 8000268 <memchr+0x98>
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8000258: 3001 adds r0, #1
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800025a: f415 7f80 tst.w r5, #256 @ 0x100
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800025e: bf02 ittt eq
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8000260: 3001 addeq r0, #1
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8000262: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
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8000266: 3001 addeq r0, #1
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8000268: bcf0 pop {r4, r5, r6, r7}
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800026a: 3801 subs r0, #1
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800026c: 4770 bx lr
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800026e: bf00 nop
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08000270 <strlen>:
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8000270: 4603 mov r3, r0
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8000272: f813 2b01 ldrb.w r2, [r3], #1
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8000276: 2a00 cmp r2, #0
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8000278: d1fb bne.n 8000272 <strlen+0x2>
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800027a: 1a18 subs r0, r3, r0
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800027c: 3801 subs r0, #1
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800027e: 4770 bx lr
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08000280 <__aeabi_drsub>:
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8000280: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
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8000284: e002 b.n 800028c <__adddf3>
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8000286: bf00 nop
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08000288 <__aeabi_dsub>:
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8000288: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
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0800028c <__adddf3>:
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800028c: b530 push {r4, r5, lr}
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800028e: ea4f 0441 mov.w r4, r1, lsl #1
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8000292: ea4f 0543 mov.w r5, r3, lsl #1
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8000296: ea94 0f05 teq r4, r5
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800029a: bf08 it eq
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800029c: ea90 0f02 teqeq r0, r2
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80002a0: bf1f itttt ne
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80002a2: ea54 0c00 orrsne.w ip, r4, r0
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80002a6: ea55 0c02 orrsne.w ip, r5, r2
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80002aa: ea7f 5c64 mvnsne.w ip, r4, asr #21
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80002ae: ea7f 5c65 mvnsne.w ip, r5, asr #21
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80002b2: f000 80e2 beq.w 800047a <__adddf3+0x1ee>
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80002b6: ea4f 5454 mov.w r4, r4, lsr #21
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80002ba: ebd4 5555 rsbs r5, r4, r5, lsr #21
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80002be: bfb8 it lt
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80002c0: 426d neglt r5, r5
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80002c2: dd0c ble.n 80002de <__adddf3+0x52>
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80002c4: 442c add r4, r5
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80002c6: ea80 0202 eor.w r2, r0, r2
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80002ca: ea81 0303 eor.w r3, r1, r3
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80002ce: ea82 0000 eor.w r0, r2, r0
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80002d2: ea83 0101 eor.w r1, r3, r1
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80002d6: ea80 0202 eor.w r2, r0, r2
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80002da: ea81 0303 eor.w r3, r1, r3
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80002de: 2d36 cmp r5, #54 @ 0x36
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80002e0: bf88 it hi
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80002e2: bd30 pophi {r4, r5, pc}
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80002e4: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
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80002e8: ea4f 3101 mov.w r1, r1, lsl #12
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80002ec: f44f 1c80 mov.w ip, #1048576 @ 0x100000
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80002f0: ea4c 3111 orr.w r1, ip, r1, lsr #12
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80002f4: d002 beq.n 80002fc <__adddf3+0x70>
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80002f6: 4240 negs r0, r0
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80002f8: eb61 0141 sbc.w r1, r1, r1, lsl #1
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80002fc: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
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8000300: ea4f 3303 mov.w r3, r3, lsl #12
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8000304: ea4c 3313 orr.w r3, ip, r3, lsr #12
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8000308: d002 beq.n 8000310 <__adddf3+0x84>
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800030a: 4252 negs r2, r2
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800030c: eb63 0343 sbc.w r3, r3, r3, lsl #1
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8000310: ea94 0f05 teq r4, r5
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8000314: f000 80a7 beq.w 8000466 <__adddf3+0x1da>
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8000318: f1a4 0401 sub.w r4, r4, #1
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800031c: f1d5 0e20 rsbs lr, r5, #32
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8000320: db0d blt.n 800033e <__adddf3+0xb2>
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8000322: fa02 fc0e lsl.w ip, r2, lr
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8000326: fa22 f205 lsr.w r2, r2, r5
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800032a: 1880 adds r0, r0, r2
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800032c: f141 0100 adc.w r1, r1, #0
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8000330: fa03 f20e lsl.w r2, r3, lr
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8000334: 1880 adds r0, r0, r2
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8000336: fa43 f305 asr.w r3, r3, r5
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800033a: 4159 adcs r1, r3
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800033c: e00e b.n 800035c <__adddf3+0xd0>
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800033e: f1a5 0520 sub.w r5, r5, #32
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8000342: f10e 0e20 add.w lr, lr, #32
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8000346: 2a01 cmp r2, #1
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8000348: fa03 fc0e lsl.w ip, r3, lr
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800034c: bf28 it cs
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800034e: f04c 0c02 orrcs.w ip, ip, #2
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8000352: fa43 f305 asr.w r3, r3, r5
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8000356: 18c0 adds r0, r0, r3
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8000358: eb51 71e3 adcs.w r1, r1, r3, asr #31
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800035c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
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8000360: d507 bpl.n 8000372 <__adddf3+0xe6>
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8000362: f04f 0e00 mov.w lr, #0
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8000366: f1dc 0c00 rsbs ip, ip, #0
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800036a: eb7e 0000 sbcs.w r0, lr, r0
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800036e: eb6e 0101 sbc.w r1, lr, r1
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8000372: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
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8000376: d31b bcc.n 80003b0 <__adddf3+0x124>
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8000378: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
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800037c: d30c bcc.n 8000398 <__adddf3+0x10c>
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800037e: 0849 lsrs r1, r1, #1
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8000380: ea5f 0030 movs.w r0, r0, rrx
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8000384: ea4f 0c3c mov.w ip, ip, rrx
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8000388: f104 0401 add.w r4, r4, #1
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800038c: ea4f 5244 mov.w r2, r4, lsl #21
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8000390: f512 0f80 cmn.w r2, #4194304 @ 0x400000
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8000394: f080 809a bcs.w 80004cc <__adddf3+0x240>
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8000398: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
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800039c: bf08 it eq
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800039e: ea5f 0c50 movseq.w ip, r0, lsr #1
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80003a2: f150 0000 adcs.w r0, r0, #0
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80003a6: eb41 5104 adc.w r1, r1, r4, lsl #20
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80003aa: ea41 0105 orr.w r1, r1, r5
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80003ae: bd30 pop {r4, r5, pc}
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80003b0: ea5f 0c4c movs.w ip, ip, lsl #1
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80003b4: 4140 adcs r0, r0
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80003b6: eb41 0101 adc.w r1, r1, r1
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80003ba: 3c01 subs r4, #1
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80003bc: bf28 it cs
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80003be: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
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80003c2: d2e9 bcs.n 8000398 <__adddf3+0x10c>
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80003c4: f091 0f00 teq r1, #0
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80003c8: bf04 itt eq
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80003ca: 4601 moveq r1, r0
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80003cc: 2000 moveq r0, #0
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80003ce: fab1 f381 clz r3, r1
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80003d2: bf08 it eq
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80003d4: 3320 addeq r3, #32
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80003d6: f1a3 030b sub.w r3, r3, #11
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80003da: f1b3 0220 subs.w r2, r3, #32
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80003de: da0c bge.n 80003fa <__adddf3+0x16e>
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80003e0: 320c adds r2, #12
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80003e2: dd08 ble.n 80003f6 <__adddf3+0x16a>
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80003e4: f102 0c14 add.w ip, r2, #20
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80003e8: f1c2 020c rsb r2, r2, #12
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80003ec: fa01 f00c lsl.w r0, r1, ip
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80003f0: fa21 f102 lsr.w r1, r1, r2
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80003f4: e00c b.n 8000410 <__adddf3+0x184>
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80003f6: f102 0214 add.w r2, r2, #20
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80003fa: bfd8 it le
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80003fc: f1c2 0c20 rsble ip, r2, #32
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8000400: fa01 f102 lsl.w r1, r1, r2
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8000404: fa20 fc0c lsr.w ip, r0, ip
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8000408: bfdc itt le
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800040a: ea41 010c orrle.w r1, r1, ip
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800040e: 4090 lslle r0, r2
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8000410: 1ae4 subs r4, r4, r3
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8000412: bfa2 ittt ge
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8000414: eb01 5104 addge.w r1, r1, r4, lsl #20
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8000418: 4329 orrge r1, r5
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800041a: bd30 popge {r4, r5, pc}
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800041c: ea6f 0404 mvn.w r4, r4
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8000420: 3c1f subs r4, #31
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8000422: da1c bge.n 800045e <__adddf3+0x1d2>
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8000424: 340c adds r4, #12
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8000426: dc0e bgt.n 8000446 <__adddf3+0x1ba>
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8000428: f104 0414 add.w r4, r4, #20
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800042c: f1c4 0220 rsb r2, r4, #32
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8000430: fa20 f004 lsr.w r0, r0, r4
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8000434: fa01 f302 lsl.w r3, r1, r2
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8000438: ea40 0003 orr.w r0, r0, r3
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800043c: fa21 f304 lsr.w r3, r1, r4
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8000440: ea45 0103 orr.w r1, r5, r3
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8000444: bd30 pop {r4, r5, pc}
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8000446: f1c4 040c rsb r4, r4, #12
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800044a: f1c4 0220 rsb r2, r4, #32
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800044e: fa20 f002 lsr.w r0, r0, r2
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8000452: fa01 f304 lsl.w r3, r1, r4
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8000456: ea40 0003 orr.w r0, r0, r3
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800045a: 4629 mov r1, r5
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800045c: bd30 pop {r4, r5, pc}
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800045e: fa21 f004 lsr.w r0, r1, r4
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8000462: 4629 mov r1, r5
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8000464: bd30 pop {r4, r5, pc}
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8000466: f094 0f00 teq r4, #0
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800046a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
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800046e: bf06 itte eq
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8000470: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
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8000474: 3401 addeq r4, #1
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8000476: 3d01 subne r5, #1
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8000478: e74e b.n 8000318 <__adddf3+0x8c>
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800047a: ea7f 5c64 mvns.w ip, r4, asr #21
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800047e: bf18 it ne
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8000480: ea7f 5c65 mvnsne.w ip, r5, asr #21
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8000484: d029 beq.n 80004da <__adddf3+0x24e>
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8000486: ea94 0f05 teq r4, r5
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800048a: bf08 it eq
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800048c: ea90 0f02 teqeq r0, r2
|
|
8000490: d005 beq.n 800049e <__adddf3+0x212>
|
|
8000492: ea54 0c00 orrs.w ip, r4, r0
|
|
8000496: bf04 itt eq
|
|
8000498: 4619 moveq r1, r3
|
|
800049a: 4610 moveq r0, r2
|
|
800049c: bd30 pop {r4, r5, pc}
|
|
800049e: ea91 0f03 teq r1, r3
|
|
80004a2: bf1e ittt ne
|
|
80004a4: 2100 movne r1, #0
|
|
80004a6: 2000 movne r0, #0
|
|
80004a8: bd30 popne {r4, r5, pc}
|
|
80004aa: ea5f 5c54 movs.w ip, r4, lsr #21
|
|
80004ae: d105 bne.n 80004bc <__adddf3+0x230>
|
|
80004b0: 0040 lsls r0, r0, #1
|
|
80004b2: 4149 adcs r1, r1
|
|
80004b4: bf28 it cs
|
|
80004b6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
|
|
80004ba: bd30 pop {r4, r5, pc}
|
|
80004bc: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
|
|
80004c0: bf3c itt cc
|
|
80004c2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
|
|
80004c6: bd30 popcc {r4, r5, pc}
|
|
80004c8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
80004cc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
|
|
80004d0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
80004d4: f04f 0000 mov.w r0, #0
|
|
80004d8: bd30 pop {r4, r5, pc}
|
|
80004da: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
80004de: bf1a itte ne
|
|
80004e0: 4619 movne r1, r3
|
|
80004e2: 4610 movne r0, r2
|
|
80004e4: ea7f 5c65 mvnseq.w ip, r5, asr #21
|
|
80004e8: bf1c itt ne
|
|
80004ea: 460b movne r3, r1
|
|
80004ec: 4602 movne r2, r0
|
|
80004ee: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80004f2: bf06 itte eq
|
|
80004f4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
|
|
80004f8: ea91 0f03 teqeq r1, r3
|
|
80004fc: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
|
|
8000500: bd30 pop {r4, r5, pc}
|
|
8000502: bf00 nop
|
|
|
|
08000504 <__aeabi_ui2d>:
|
|
8000504: f090 0f00 teq r0, #0
|
|
8000508: bf04 itt eq
|
|
800050a: 2100 moveq r1, #0
|
|
800050c: 4770 bxeq lr
|
|
800050e: b530 push {r4, r5, lr}
|
|
8000510: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000514: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000518: f04f 0500 mov.w r5, #0
|
|
800051c: f04f 0100 mov.w r1, #0
|
|
8000520: e750 b.n 80003c4 <__adddf3+0x138>
|
|
8000522: bf00 nop
|
|
|
|
08000524 <__aeabi_i2d>:
|
|
8000524: f090 0f00 teq r0, #0
|
|
8000528: bf04 itt eq
|
|
800052a: 2100 moveq r1, #0
|
|
800052c: 4770 bxeq lr
|
|
800052e: b530 push {r4, r5, lr}
|
|
8000530: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000534: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000538: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
|
|
800053c: bf48 it mi
|
|
800053e: 4240 negmi r0, r0
|
|
8000540: f04f 0100 mov.w r1, #0
|
|
8000544: e73e b.n 80003c4 <__adddf3+0x138>
|
|
8000546: bf00 nop
|
|
|
|
08000548 <__aeabi_f2d>:
|
|
8000548: 0042 lsls r2, r0, #1
|
|
800054a: ea4f 01e2 mov.w r1, r2, asr #3
|
|
800054e: ea4f 0131 mov.w r1, r1, rrx
|
|
8000552: ea4f 7002 mov.w r0, r2, lsl #28
|
|
8000556: bf1f itttt ne
|
|
8000558: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
|
|
800055c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
|
|
8000560: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
|
|
8000564: 4770 bxne lr
|
|
8000566: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
|
|
800056a: bf08 it eq
|
|
800056c: 4770 bxeq lr
|
|
800056e: f093 4f7f teq r3, #4278190080 @ 0xff000000
|
|
8000572: bf04 itt eq
|
|
8000574: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
|
|
8000578: 4770 bxeq lr
|
|
800057a: b530 push {r4, r5, lr}
|
|
800057c: f44f 7460 mov.w r4, #896 @ 0x380
|
|
8000580: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
8000584: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000588: e71c b.n 80003c4 <__adddf3+0x138>
|
|
800058a: bf00 nop
|
|
|
|
0800058c <__aeabi_ul2d>:
|
|
800058c: ea50 0201 orrs.w r2, r0, r1
|
|
8000590: bf08 it eq
|
|
8000592: 4770 bxeq lr
|
|
8000594: b530 push {r4, r5, lr}
|
|
8000596: f04f 0500 mov.w r5, #0
|
|
800059a: e00a b.n 80005b2 <__aeabi_l2d+0x16>
|
|
|
|
0800059c <__aeabi_l2d>:
|
|
800059c: ea50 0201 orrs.w r2, r0, r1
|
|
80005a0: bf08 it eq
|
|
80005a2: 4770 bxeq lr
|
|
80005a4: b530 push {r4, r5, lr}
|
|
80005a6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
|
|
80005aa: d502 bpl.n 80005b2 <__aeabi_l2d+0x16>
|
|
80005ac: 4240 negs r0, r0
|
|
80005ae: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
80005b2: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80005b6: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80005ba: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
80005be: f43f aed8 beq.w 8000372 <__adddf3+0xe6>
|
|
80005c2: f04f 0203 mov.w r2, #3
|
|
80005c6: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005ca: bf18 it ne
|
|
80005cc: 3203 addne r2, #3
|
|
80005ce: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005d2: bf18 it ne
|
|
80005d4: 3203 addne r2, #3
|
|
80005d6: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
80005da: f1c2 0320 rsb r3, r2, #32
|
|
80005de: fa00 fc03 lsl.w ip, r0, r3
|
|
80005e2: fa20 f002 lsr.w r0, r0, r2
|
|
80005e6: fa01 fe03 lsl.w lr, r1, r3
|
|
80005ea: ea40 000e orr.w r0, r0, lr
|
|
80005ee: fa21 f102 lsr.w r1, r1, r2
|
|
80005f2: 4414 add r4, r2
|
|
80005f4: e6bd b.n 8000372 <__adddf3+0xe6>
|
|
80005f6: bf00 nop
|
|
|
|
080005f8 <__aeabi_dmul>:
|
|
80005f8: b570 push {r4, r5, r6, lr}
|
|
80005fa: f04f 0cff mov.w ip, #255 @ 0xff
|
|
80005fe: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000602: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
8000606: bf1d ittte ne
|
|
8000608: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
800060c: ea94 0f0c teqne r4, ip
|
|
8000610: ea95 0f0c teqne r5, ip
|
|
8000614: f000 f8de bleq 80007d4 <__aeabi_dmul+0x1dc>
|
|
8000618: 442c add r4, r5
|
|
800061a: ea81 0603 eor.w r6, r1, r3
|
|
800061e: ea21 514c bic.w r1, r1, ip, lsl #21
|
|
8000622: ea23 534c bic.w r3, r3, ip, lsl #21
|
|
8000626: ea50 3501 orrs.w r5, r0, r1, lsl #12
|
|
800062a: bf18 it ne
|
|
800062c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
|
|
8000630: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
8000634: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8000638: d038 beq.n 80006ac <__aeabi_dmul+0xb4>
|
|
800063a: fba0 ce02 umull ip, lr, r0, r2
|
|
800063e: f04f 0500 mov.w r5, #0
|
|
8000642: fbe1 e502 umlal lr, r5, r1, r2
|
|
8000646: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
|
|
800064a: fbe0 e503 umlal lr, r5, r0, r3
|
|
800064e: f04f 0600 mov.w r6, #0
|
|
8000652: fbe1 5603 umlal r5, r6, r1, r3
|
|
8000656: f09c 0f00 teq ip, #0
|
|
800065a: bf18 it ne
|
|
800065c: f04e 0e01 orrne.w lr, lr, #1
|
|
8000660: f1a4 04ff sub.w r4, r4, #255 @ 0xff
|
|
8000664: f5b6 7f00 cmp.w r6, #512 @ 0x200
|
|
8000668: f564 7440 sbc.w r4, r4, #768 @ 0x300
|
|
800066c: d204 bcs.n 8000678 <__aeabi_dmul+0x80>
|
|
800066e: ea5f 0e4e movs.w lr, lr, lsl #1
|
|
8000672: 416d adcs r5, r5
|
|
8000674: eb46 0606 adc.w r6, r6, r6
|
|
8000678: ea42 21c6 orr.w r1, r2, r6, lsl #11
|
|
800067c: ea41 5155 orr.w r1, r1, r5, lsr #21
|
|
8000680: ea4f 20c5 mov.w r0, r5, lsl #11
|
|
8000684: ea40 505e orr.w r0, r0, lr, lsr #21
|
|
8000688: ea4f 2ece mov.w lr, lr, lsl #11
|
|
800068c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
8000690: bf88 it hi
|
|
8000692: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000696: d81e bhi.n 80006d6 <__aeabi_dmul+0xde>
|
|
8000698: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
|
|
800069c: bf08 it eq
|
|
800069e: ea5f 0e50 movseq.w lr, r0, lsr #1
|
|
80006a2: f150 0000 adcs.w r0, r0, #0
|
|
80006a6: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
80006aa: bd70 pop {r4, r5, r6, pc}
|
|
80006ac: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
|
|
80006b0: ea46 0101 orr.w r1, r6, r1
|
|
80006b4: ea40 0002 orr.w r0, r0, r2
|
|
80006b8: ea81 0103 eor.w r1, r1, r3
|
|
80006bc: ebb4 045c subs.w r4, r4, ip, lsr #1
|
|
80006c0: bfc2 ittt gt
|
|
80006c2: ebd4 050c rsbsgt r5, r4, ip
|
|
80006c6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80006ca: bd70 popgt {r4, r5, r6, pc}
|
|
80006cc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80006d0: f04f 0e00 mov.w lr, #0
|
|
80006d4: 3c01 subs r4, #1
|
|
80006d6: f300 80ab bgt.w 8000830 <__aeabi_dmul+0x238>
|
|
80006da: f114 0f36 cmn.w r4, #54 @ 0x36
|
|
80006de: bfde ittt le
|
|
80006e0: 2000 movle r0, #0
|
|
80006e2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
|
|
80006e6: bd70 pople {r4, r5, r6, pc}
|
|
80006e8: f1c4 0400 rsb r4, r4, #0
|
|
80006ec: 3c20 subs r4, #32
|
|
80006ee: da35 bge.n 800075c <__aeabi_dmul+0x164>
|
|
80006f0: 340c adds r4, #12
|
|
80006f2: dc1b bgt.n 800072c <__aeabi_dmul+0x134>
|
|
80006f4: f104 0414 add.w r4, r4, #20
|
|
80006f8: f1c4 0520 rsb r5, r4, #32
|
|
80006fc: fa00 f305 lsl.w r3, r0, r5
|
|
8000700: fa20 f004 lsr.w r0, r0, r4
|
|
8000704: fa01 f205 lsl.w r2, r1, r5
|
|
8000708: ea40 0002 orr.w r0, r0, r2
|
|
800070c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
|
|
8000710: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
8000718: fa21 f604 lsr.w r6, r1, r4
|
|
800071c: eb42 0106 adc.w r1, r2, r6
|
|
8000720: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000724: bf08 it eq
|
|
8000726: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800072a: bd70 pop {r4, r5, r6, pc}
|
|
800072c: f1c4 040c rsb r4, r4, #12
|
|
8000730: f1c4 0520 rsb r5, r4, #32
|
|
8000734: fa00 f304 lsl.w r3, r0, r4
|
|
8000738: fa20 f005 lsr.w r0, r0, r5
|
|
800073c: fa01 f204 lsl.w r2, r1, r4
|
|
8000740: ea40 0002 orr.w r0, r0, r2
|
|
8000744: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
8000748: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
800074c: f141 0100 adc.w r1, r1, #0
|
|
8000750: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000754: bf08 it eq
|
|
8000756: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800075a: bd70 pop {r4, r5, r6, pc}
|
|
800075c: f1c4 0520 rsb r5, r4, #32
|
|
8000760: fa00 f205 lsl.w r2, r0, r5
|
|
8000764: ea4e 0e02 orr.w lr, lr, r2
|
|
8000768: fa20 f304 lsr.w r3, r0, r4
|
|
800076c: fa01 f205 lsl.w r2, r1, r5
|
|
8000770: ea43 0302 orr.w r3, r3, r2
|
|
8000774: fa21 f004 lsr.w r0, r1, r4
|
|
8000778: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
800077c: fa21 f204 lsr.w r2, r1, r4
|
|
8000780: ea20 0002 bic.w r0, r0, r2
|
|
8000784: eb00 70d3 add.w r0, r0, r3, lsr #31
|
|
8000788: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
800078c: bf08 it eq
|
|
800078e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
8000792: bd70 pop {r4, r5, r6, pc}
|
|
8000794: f094 0f00 teq r4, #0
|
|
8000798: d10f bne.n 80007ba <__aeabi_dmul+0x1c2>
|
|
800079a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
|
|
800079e: 0040 lsls r0, r0, #1
|
|
80007a0: eb41 0101 adc.w r1, r1, r1
|
|
80007a4: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
80007a8: bf08 it eq
|
|
80007aa: 3c01 subeq r4, #1
|
|
80007ac: d0f7 beq.n 800079e <__aeabi_dmul+0x1a6>
|
|
80007ae: ea41 0106 orr.w r1, r1, r6
|
|
80007b2: f095 0f00 teq r5, #0
|
|
80007b6: bf18 it ne
|
|
80007b8: 4770 bxne lr
|
|
80007ba: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
|
|
80007be: 0052 lsls r2, r2, #1
|
|
80007c0: eb43 0303 adc.w r3, r3, r3
|
|
80007c4: f413 1f80 tst.w r3, #1048576 @ 0x100000
|
|
80007c8: bf08 it eq
|
|
80007ca: 3d01 subeq r5, #1
|
|
80007cc: d0f7 beq.n 80007be <__aeabi_dmul+0x1c6>
|
|
80007ce: ea43 0306 orr.w r3, r3, r6
|
|
80007d2: 4770 bx lr
|
|
80007d4: ea94 0f0c teq r4, ip
|
|
80007d8: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80007dc: bf18 it ne
|
|
80007de: ea95 0f0c teqne r5, ip
|
|
80007e2: d00c beq.n 80007fe <__aeabi_dmul+0x206>
|
|
80007e4: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
80007e8: bf18 it ne
|
|
80007ea: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
80007ee: d1d1 bne.n 8000794 <__aeabi_dmul+0x19c>
|
|
80007f0: ea81 0103 eor.w r1, r1, r3
|
|
80007f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
80007f8: f04f 0000 mov.w r0, #0
|
|
80007fc: bd70 pop {r4, r5, r6, pc}
|
|
80007fe: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000802: bf06 itte eq
|
|
8000804: 4610 moveq r0, r2
|
|
8000806: 4619 moveq r1, r3
|
|
8000808: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
800080c: d019 beq.n 8000842 <__aeabi_dmul+0x24a>
|
|
800080e: ea94 0f0c teq r4, ip
|
|
8000812: d102 bne.n 800081a <__aeabi_dmul+0x222>
|
|
8000814: ea50 3601 orrs.w r6, r0, r1, lsl #12
|
|
8000818: d113 bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800081a: ea95 0f0c teq r5, ip
|
|
800081e: d105 bne.n 800082c <__aeabi_dmul+0x234>
|
|
8000820: ea52 3603 orrs.w r6, r2, r3, lsl #12
|
|
8000824: bf1c itt ne
|
|
8000826: 4610 movne r0, r2
|
|
8000828: 4619 movne r1, r3
|
|
800082a: d10a bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800082c: ea81 0103 eor.w r1, r1, r3
|
|
8000830: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
8000834: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
8000838: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
800083c: f04f 0000 mov.w r0, #0
|
|
8000840: bd70 pop {r4, r5, r6, pc}
|
|
8000842: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
8000846: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
|
|
800084a: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0800084c <__aeabi_ddiv>:
|
|
800084c: b570 push {r4, r5, r6, lr}
|
|
800084e: f04f 0cff mov.w ip, #255 @ 0xff
|
|
8000852: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000856: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
800085a: bf1d ittte ne
|
|
800085c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
8000860: ea94 0f0c teqne r4, ip
|
|
8000864: ea95 0f0c teqne r5, ip
|
|
8000868: f000 f8a7 bleq 80009ba <__aeabi_ddiv+0x16e>
|
|
800086c: eba4 0405 sub.w r4, r4, r5
|
|
8000870: ea81 0e03 eor.w lr, r1, r3
|
|
8000874: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
8000878: ea4f 3101 mov.w r1, r1, lsl #12
|
|
800087c: f000 8088 beq.w 8000990 <__aeabi_ddiv+0x144>
|
|
8000880: ea4f 3303 mov.w r3, r3, lsl #12
|
|
8000884: f04f 5580 mov.w r5, #268435456 @ 0x10000000
|
|
8000888: ea45 1313 orr.w r3, r5, r3, lsr #4
|
|
800088c: ea43 6312 orr.w r3, r3, r2, lsr #24
|
|
8000890: ea4f 2202 mov.w r2, r2, lsl #8
|
|
8000894: ea45 1511 orr.w r5, r5, r1, lsr #4
|
|
8000898: ea45 6510 orr.w r5, r5, r0, lsr #24
|
|
800089c: ea4f 2600 mov.w r6, r0, lsl #8
|
|
80008a0: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
|
|
80008a4: 429d cmp r5, r3
|
|
80008a6: bf08 it eq
|
|
80008a8: 4296 cmpeq r6, r2
|
|
80008aa: f144 04fd adc.w r4, r4, #253 @ 0xfd
|
|
80008ae: f504 7440 add.w r4, r4, #768 @ 0x300
|
|
80008b2: d202 bcs.n 80008ba <__aeabi_ddiv+0x6e>
|
|
80008b4: 085b lsrs r3, r3, #1
|
|
80008b6: ea4f 0232 mov.w r2, r2, rrx
|
|
80008ba: 1ab6 subs r6, r6, r2
|
|
80008bc: eb65 0503 sbc.w r5, r5, r3
|
|
80008c0: 085b lsrs r3, r3, #1
|
|
80008c2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008c6: f44f 1080 mov.w r0, #1048576 @ 0x100000
|
|
80008ca: f44f 2c00 mov.w ip, #524288 @ 0x80000
|
|
80008ce: ebb6 0e02 subs.w lr, r6, r2
|
|
80008d2: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008d6: bf22 ittt cs
|
|
80008d8: 1ab6 subcs r6, r6, r2
|
|
80008da: 4675 movcs r5, lr
|
|
80008dc: ea40 000c orrcs.w r0, r0, ip
|
|
80008e0: 085b lsrs r3, r3, #1
|
|
80008e2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008e6: ebb6 0e02 subs.w lr, r6, r2
|
|
80008ea: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008ee: bf22 ittt cs
|
|
80008f0: 1ab6 subcs r6, r6, r2
|
|
80008f2: 4675 movcs r5, lr
|
|
80008f4: ea40 005c orrcs.w r0, r0, ip, lsr #1
|
|
80008f8: 085b lsrs r3, r3, #1
|
|
80008fa: ea4f 0232 mov.w r2, r2, rrx
|
|
80008fe: ebb6 0e02 subs.w lr, r6, r2
|
|
8000902: eb75 0e03 sbcs.w lr, r5, r3
|
|
8000906: bf22 ittt cs
|
|
8000908: 1ab6 subcs r6, r6, r2
|
|
800090a: 4675 movcs r5, lr
|
|
800090c: ea40 009c orrcs.w r0, r0, ip, lsr #2
|
|
8000910: 085b lsrs r3, r3, #1
|
|
8000912: ea4f 0232 mov.w r2, r2, rrx
|
|
8000916: ebb6 0e02 subs.w lr, r6, r2
|
|
800091a: eb75 0e03 sbcs.w lr, r5, r3
|
|
800091e: bf22 ittt cs
|
|
8000920: 1ab6 subcs r6, r6, r2
|
|
8000922: 4675 movcs r5, lr
|
|
8000924: ea40 00dc orrcs.w r0, r0, ip, lsr #3
|
|
8000928: ea55 0e06 orrs.w lr, r5, r6
|
|
800092c: d018 beq.n 8000960 <__aeabi_ddiv+0x114>
|
|
800092e: ea4f 1505 mov.w r5, r5, lsl #4
|
|
8000932: ea45 7516 orr.w r5, r5, r6, lsr #28
|
|
8000936: ea4f 1606 mov.w r6, r6, lsl #4
|
|
800093a: ea4f 03c3 mov.w r3, r3, lsl #3
|
|
800093e: ea43 7352 orr.w r3, r3, r2, lsr #29
|
|
8000942: ea4f 02c2 mov.w r2, r2, lsl #3
|
|
8000946: ea5f 1c1c movs.w ip, ip, lsr #4
|
|
800094a: d1c0 bne.n 80008ce <__aeabi_ddiv+0x82>
|
|
800094c: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000950: d10b bne.n 800096a <__aeabi_ddiv+0x11e>
|
|
8000952: ea41 0100 orr.w r1, r1, r0
|
|
8000956: f04f 0000 mov.w r0, #0
|
|
800095a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
|
|
800095e: e7b6 b.n 80008ce <__aeabi_ddiv+0x82>
|
|
8000960: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000964: bf04 itt eq
|
|
8000966: 4301 orreq r1, r0
|
|
8000968: 2000 moveq r0, #0
|
|
800096a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
800096e: bf88 it hi
|
|
8000970: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000974: f63f aeaf bhi.w 80006d6 <__aeabi_dmul+0xde>
|
|
8000978: ebb5 0c03 subs.w ip, r5, r3
|
|
800097c: bf04 itt eq
|
|
800097e: ebb6 0c02 subseq.w ip, r6, r2
|
|
8000982: ea5f 0c50 movseq.w ip, r0, lsr #1
|
|
8000986: f150 0000 adcs.w r0, r0, #0
|
|
800098a: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
800098e: bd70 pop {r4, r5, r6, pc}
|
|
8000990: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
|
|
8000994: ea4e 3111 orr.w r1, lr, r1, lsr #12
|
|
8000998: eb14 045c adds.w r4, r4, ip, lsr #1
|
|
800099c: bfc2 ittt gt
|
|
800099e: ebd4 050c rsbsgt r5, r4, ip
|
|
80009a2: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80009a6: bd70 popgt {r4, r5, r6, pc}
|
|
80009a8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80009ac: f04f 0e00 mov.w lr, #0
|
|
80009b0: 3c01 subs r4, #1
|
|
80009b2: e690 b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009b4: ea45 0e06 orr.w lr, r5, r6
|
|
80009b8: e68d b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009ba: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80009be: ea94 0f0c teq r4, ip
|
|
80009c2: bf08 it eq
|
|
80009c4: ea95 0f0c teqeq r5, ip
|
|
80009c8: f43f af3b beq.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009cc: ea94 0f0c teq r4, ip
|
|
80009d0: d10a bne.n 80009e8 <__aeabi_ddiv+0x19c>
|
|
80009d2: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80009d6: f47f af34 bne.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009da: ea95 0f0c teq r5, ip
|
|
80009de: f47f af25 bne.w 800082c <__aeabi_dmul+0x234>
|
|
80009e2: 4610 mov r0, r2
|
|
80009e4: 4619 mov r1, r3
|
|
80009e6: e72c b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009e8: ea95 0f0c teq r5, ip
|
|
80009ec: d106 bne.n 80009fc <__aeabi_ddiv+0x1b0>
|
|
80009ee: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
80009f2: f43f aefd beq.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
80009f6: 4610 mov r0, r2
|
|
80009f8: 4619 mov r1, r3
|
|
80009fa: e722 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009fc: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000a00: bf18 it ne
|
|
8000a02: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
8000a06: f47f aec5 bne.w 8000794 <__aeabi_dmul+0x19c>
|
|
8000a0a: ea50 0441 orrs.w r4, r0, r1, lsl #1
|
|
8000a0e: f47f af0d bne.w 800082c <__aeabi_dmul+0x234>
|
|
8000a12: ea52 0543 orrs.w r5, r2, r3, lsl #1
|
|
8000a16: f47f aeeb bne.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
8000a1a: e712 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
|
|
08000a1c <__gedf2>:
|
|
8000a1c: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff
|
|
8000a20: e006 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a22: bf00 nop
|
|
|
|
08000a24 <__ledf2>:
|
|
8000a24: f04f 0c01 mov.w ip, #1
|
|
8000a28: e002 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a2a: bf00 nop
|
|
|
|
08000a2c <__cmpdf2>:
|
|
8000a2c: f04f 0c01 mov.w ip, #1
|
|
8000a30: f84d cd04 str.w ip, [sp, #-4]!
|
|
8000a34: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a38: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a40: bf18 it ne
|
|
8000a42: ea7f 5c6c mvnsne.w ip, ip, asr #21
|
|
8000a46: d01b beq.n 8000a80 <__cmpdf2+0x54>
|
|
8000a48: b001 add sp, #4
|
|
8000a4a: ea50 0c41 orrs.w ip, r0, r1, lsl #1
|
|
8000a4e: bf0c ite eq
|
|
8000a50: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
|
|
8000a54: ea91 0f03 teqne r1, r3
|
|
8000a58: bf02 ittt eq
|
|
8000a5a: ea90 0f02 teqeq r0, r2
|
|
8000a5e: 2000 moveq r0, #0
|
|
8000a60: 4770 bxeq lr
|
|
8000a62: f110 0f00 cmn.w r0, #0
|
|
8000a66: ea91 0f03 teq r1, r3
|
|
8000a6a: bf58 it pl
|
|
8000a6c: 4299 cmppl r1, r3
|
|
8000a6e: bf08 it eq
|
|
8000a70: 4290 cmpeq r0, r2
|
|
8000a72: bf2c ite cs
|
|
8000a74: 17d8 asrcs r0, r3, #31
|
|
8000a76: ea6f 70e3 mvncc.w r0, r3, asr #31
|
|
8000a7a: f040 0001 orr.w r0, r0, #1
|
|
8000a7e: 4770 bx lr
|
|
8000a80: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a84: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a88: d102 bne.n 8000a90 <__cmpdf2+0x64>
|
|
8000a8a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000a8e: d107 bne.n 8000aa0 <__cmpdf2+0x74>
|
|
8000a90: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a94: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a98: d1d6 bne.n 8000a48 <__cmpdf2+0x1c>
|
|
8000a9a: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000a9e: d0d3 beq.n 8000a48 <__cmpdf2+0x1c>
|
|
8000aa0: f85d 0b04 ldr.w r0, [sp], #4
|
|
8000aa4: 4770 bx lr
|
|
8000aa6: bf00 nop
|
|
|
|
08000aa8 <__aeabi_cdrcmple>:
|
|
8000aa8: 4684 mov ip, r0
|
|
8000aaa: 4610 mov r0, r2
|
|
8000aac: 4662 mov r2, ip
|
|
8000aae: 468c mov ip, r1
|
|
8000ab0: 4619 mov r1, r3
|
|
8000ab2: 4663 mov r3, ip
|
|
8000ab4: e000 b.n 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ab6: bf00 nop
|
|
|
|
08000ab8 <__aeabi_cdcmpeq>:
|
|
8000ab8: b501 push {r0, lr}
|
|
8000aba: f7ff ffb7 bl 8000a2c <__cmpdf2>
|
|
8000abe: 2800 cmp r0, #0
|
|
8000ac0: bf48 it mi
|
|
8000ac2: f110 0f00 cmnmi.w r0, #0
|
|
8000ac6: bd01 pop {r0, pc}
|
|
|
|
08000ac8 <__aeabi_dcmpeq>:
|
|
8000ac8: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000acc: f7ff fff4 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ad0: bf0c ite eq
|
|
8000ad2: 2001 moveq r0, #1
|
|
8000ad4: 2000 movne r0, #0
|
|
8000ad6: f85d fb08 ldr.w pc, [sp], #8
|
|
8000ada: bf00 nop
|
|
|
|
08000adc <__aeabi_dcmplt>:
|
|
8000adc: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000ae0: f7ff ffea bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ae4: bf34 ite cc
|
|
8000ae6: 2001 movcc r0, #1
|
|
8000ae8: 2000 movcs r0, #0
|
|
8000aea: f85d fb08 ldr.w pc, [sp], #8
|
|
8000aee: bf00 nop
|
|
|
|
08000af0 <__aeabi_dcmple>:
|
|
8000af0: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000af4: f7ff ffe0 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000af8: bf94 ite ls
|
|
8000afa: 2001 movls r0, #1
|
|
8000afc: 2000 movhi r0, #0
|
|
8000afe: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b02: bf00 nop
|
|
|
|
08000b04 <__aeabi_dcmpge>:
|
|
8000b04: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b08: f7ff ffce bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b0c: bf94 ite ls
|
|
8000b0e: 2001 movls r0, #1
|
|
8000b10: 2000 movhi r0, #0
|
|
8000b12: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b16: bf00 nop
|
|
|
|
08000b18 <__aeabi_dcmpgt>:
|
|
8000b18: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b1c: f7ff ffc4 bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b20: bf34 ite cc
|
|
8000b22: 2001 movcc r0, #1
|
|
8000b24: 2000 movcs r0, #0
|
|
8000b26: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b2a: bf00 nop
|
|
|
|
08000b2c <__aeabi_dcmpun>:
|
|
8000b2c: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000b30: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b34: d102 bne.n 8000b3c <__aeabi_dcmpun+0x10>
|
|
8000b36: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000b3a: d10a bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000b40: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x20>
|
|
8000b46: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000b4a: d102 bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b4c: f04f 0000 mov.w r0, #0
|
|
8000b50: 4770 bx lr
|
|
8000b52: f04f 0001 mov.w r0, #1
|
|
8000b56: 4770 bx lr
|
|
|
|
08000b58 <__aeabi_d2iz>:
|
|
8000b58: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
8000b60: d215 bcs.n 8000b8e <__aeabi_d2iz+0x36>
|
|
8000b62: d511 bpl.n 8000b88 <__aeabi_d2iz+0x30>
|
|
8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
8000b6c: d912 bls.n 8000b94 <__aeabi_d2iz+0x3c>
|
|
8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
8000b7a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
|
|
8000b7e: fa23 f002 lsr.w r0, r3, r2
|
|
8000b82: bf18 it ne
|
|
8000b84: 4240 negne r0, r0
|
|
8000b86: 4770 bx lr
|
|
8000b88: f04f 0000 mov.w r0, #0
|
|
8000b8c: 4770 bx lr
|
|
8000b8e: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000b92: d105 bne.n 8000ba0 <__aeabi_d2iz+0x48>
|
|
8000b94: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
|
|
8000b98: bf08 it eq
|
|
8000b9a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
|
|
8000b9e: 4770 bx lr
|
|
8000ba0: f04f 0000 mov.w r0, #0
|
|
8000ba4: 4770 bx lr
|
|
8000ba6: bf00 nop
|
|
|
|
08000ba8 <__aeabi_uldivmod>:
|
|
8000ba8: b953 cbnz r3, 8000bc0 <__aeabi_uldivmod+0x18>
|
|
8000baa: b94a cbnz r2, 8000bc0 <__aeabi_uldivmod+0x18>
|
|
8000bac: 2900 cmp r1, #0
|
|
8000bae: bf08 it eq
|
|
8000bb0: 2800 cmpeq r0, #0
|
|
8000bb2: bf1c itt ne
|
|
8000bb4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
|
|
8000bb8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
|
|
8000bbc: f000 b988 b.w 8000ed0 <__aeabi_idiv0>
|
|
8000bc0: f1ad 0c08 sub.w ip, sp, #8
|
|
8000bc4: e96d ce04 strd ip, lr, [sp, #-16]!
|
|
8000bc8: f000 f806 bl 8000bd8 <__udivmoddi4>
|
|
8000bcc: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000bd0: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000bd4: b004 add sp, #16
|
|
8000bd6: 4770 bx lr
|
|
|
|
08000bd8 <__udivmoddi4>:
|
|
8000bd8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8000bdc: 9d08 ldr r5, [sp, #32]
|
|
8000bde: 468e mov lr, r1
|
|
8000be0: 4604 mov r4, r0
|
|
8000be2: 4688 mov r8, r1
|
|
8000be4: 2b00 cmp r3, #0
|
|
8000be6: d14a bne.n 8000c7e <__udivmoddi4+0xa6>
|
|
8000be8: 428a cmp r2, r1
|
|
8000bea: 4617 mov r7, r2
|
|
8000bec: d962 bls.n 8000cb4 <__udivmoddi4+0xdc>
|
|
8000bee: fab2 f682 clz r6, r2
|
|
8000bf2: b14e cbz r6, 8000c08 <__udivmoddi4+0x30>
|
|
8000bf4: f1c6 0320 rsb r3, r6, #32
|
|
8000bf8: fa01 f806 lsl.w r8, r1, r6
|
|
8000bfc: fa20 f303 lsr.w r3, r0, r3
|
|
8000c00: 40b7 lsls r7, r6
|
|
8000c02: ea43 0808 orr.w r8, r3, r8
|
|
8000c06: 40b4 lsls r4, r6
|
|
8000c08: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000c0c: fa1f fc87 uxth.w ip, r7
|
|
8000c10: fbb8 f1fe udiv r1, r8, lr
|
|
8000c14: 0c23 lsrs r3, r4, #16
|
|
8000c16: fb0e 8811 mls r8, lr, r1, r8
|
|
8000c1a: ea43 4308 orr.w r3, r3, r8, lsl #16
|
|
8000c1e: fb01 f20c mul.w r2, r1, ip
|
|
8000c22: 429a cmp r2, r3
|
|
8000c24: d909 bls.n 8000c3a <__udivmoddi4+0x62>
|
|
8000c26: 18fb adds r3, r7, r3
|
|
8000c28: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
|
|
8000c2c: f080 80ea bcs.w 8000e04 <__udivmoddi4+0x22c>
|
|
8000c30: 429a cmp r2, r3
|
|
8000c32: f240 80e7 bls.w 8000e04 <__udivmoddi4+0x22c>
|
|
8000c36: 3902 subs r1, #2
|
|
8000c38: 443b add r3, r7
|
|
8000c3a: 1a9a subs r2, r3, r2
|
|
8000c3c: b2a3 uxth r3, r4
|
|
8000c3e: fbb2 f0fe udiv r0, r2, lr
|
|
8000c42: fb0e 2210 mls r2, lr, r0, r2
|
|
8000c46: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8000c4a: fb00 fc0c mul.w ip, r0, ip
|
|
8000c4e: 459c cmp ip, r3
|
|
8000c50: d909 bls.n 8000c66 <__udivmoddi4+0x8e>
|
|
8000c52: 18fb adds r3, r7, r3
|
|
8000c54: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
|
|
8000c58: f080 80d6 bcs.w 8000e08 <__udivmoddi4+0x230>
|
|
8000c5c: 459c cmp ip, r3
|
|
8000c5e: f240 80d3 bls.w 8000e08 <__udivmoddi4+0x230>
|
|
8000c62: 443b add r3, r7
|
|
8000c64: 3802 subs r0, #2
|
|
8000c66: ea40 4001 orr.w r0, r0, r1, lsl #16
|
|
8000c6a: eba3 030c sub.w r3, r3, ip
|
|
8000c6e: 2100 movs r1, #0
|
|
8000c70: b11d cbz r5, 8000c7a <__udivmoddi4+0xa2>
|
|
8000c72: 40f3 lsrs r3, r6
|
|
8000c74: 2200 movs r2, #0
|
|
8000c76: e9c5 3200 strd r3, r2, [r5]
|
|
8000c7a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8000c7e: 428b cmp r3, r1
|
|
8000c80: d905 bls.n 8000c8e <__udivmoddi4+0xb6>
|
|
8000c82: b10d cbz r5, 8000c88 <__udivmoddi4+0xb0>
|
|
8000c84: e9c5 0100 strd r0, r1, [r5]
|
|
8000c88: 2100 movs r1, #0
|
|
8000c8a: 4608 mov r0, r1
|
|
8000c8c: e7f5 b.n 8000c7a <__udivmoddi4+0xa2>
|
|
8000c8e: fab3 f183 clz r1, r3
|
|
8000c92: 2900 cmp r1, #0
|
|
8000c94: d146 bne.n 8000d24 <__udivmoddi4+0x14c>
|
|
8000c96: 4573 cmp r3, lr
|
|
8000c98: d302 bcc.n 8000ca0 <__udivmoddi4+0xc8>
|
|
8000c9a: 4282 cmp r2, r0
|
|
8000c9c: f200 8105 bhi.w 8000eaa <__udivmoddi4+0x2d2>
|
|
8000ca0: 1a84 subs r4, r0, r2
|
|
8000ca2: eb6e 0203 sbc.w r2, lr, r3
|
|
8000ca6: 2001 movs r0, #1
|
|
8000ca8: 4690 mov r8, r2
|
|
8000caa: 2d00 cmp r5, #0
|
|
8000cac: d0e5 beq.n 8000c7a <__udivmoddi4+0xa2>
|
|
8000cae: e9c5 4800 strd r4, r8, [r5]
|
|
8000cb2: e7e2 b.n 8000c7a <__udivmoddi4+0xa2>
|
|
8000cb4: 2a00 cmp r2, #0
|
|
8000cb6: f000 8090 beq.w 8000dda <__udivmoddi4+0x202>
|
|
8000cba: fab2 f682 clz r6, r2
|
|
8000cbe: 2e00 cmp r6, #0
|
|
8000cc0: f040 80a4 bne.w 8000e0c <__udivmoddi4+0x234>
|
|
8000cc4: 1a8a subs r2, r1, r2
|
|
8000cc6: 0c03 lsrs r3, r0, #16
|
|
8000cc8: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000ccc: b280 uxth r0, r0
|
|
8000cce: b2bc uxth r4, r7
|
|
8000cd0: 2101 movs r1, #1
|
|
8000cd2: fbb2 fcfe udiv ip, r2, lr
|
|
8000cd6: fb0e 221c mls r2, lr, ip, r2
|
|
8000cda: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8000cde: fb04 f20c mul.w r2, r4, ip
|
|
8000ce2: 429a cmp r2, r3
|
|
8000ce4: d907 bls.n 8000cf6 <__udivmoddi4+0x11e>
|
|
8000ce6: 18fb adds r3, r7, r3
|
|
8000ce8: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
|
|
8000cec: d202 bcs.n 8000cf4 <__udivmoddi4+0x11c>
|
|
8000cee: 429a cmp r2, r3
|
|
8000cf0: f200 80e0 bhi.w 8000eb4 <__udivmoddi4+0x2dc>
|
|
8000cf4: 46c4 mov ip, r8
|
|
8000cf6: 1a9b subs r3, r3, r2
|
|
8000cf8: fbb3 f2fe udiv r2, r3, lr
|
|
8000cfc: fb0e 3312 mls r3, lr, r2, r3
|
|
8000d00: ea40 4303 orr.w r3, r0, r3, lsl #16
|
|
8000d04: fb02 f404 mul.w r4, r2, r4
|
|
8000d08: 429c cmp r4, r3
|
|
8000d0a: d907 bls.n 8000d1c <__udivmoddi4+0x144>
|
|
8000d0c: 18fb adds r3, r7, r3
|
|
8000d0e: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
|
|
8000d12: d202 bcs.n 8000d1a <__udivmoddi4+0x142>
|
|
8000d14: 429c cmp r4, r3
|
|
8000d16: f200 80ca bhi.w 8000eae <__udivmoddi4+0x2d6>
|
|
8000d1a: 4602 mov r2, r0
|
|
8000d1c: 1b1b subs r3, r3, r4
|
|
8000d1e: ea42 400c orr.w r0, r2, ip, lsl #16
|
|
8000d22: e7a5 b.n 8000c70 <__udivmoddi4+0x98>
|
|
8000d24: f1c1 0620 rsb r6, r1, #32
|
|
8000d28: 408b lsls r3, r1
|
|
8000d2a: fa22 f706 lsr.w r7, r2, r6
|
|
8000d2e: 431f orrs r7, r3
|
|
8000d30: fa0e f401 lsl.w r4, lr, r1
|
|
8000d34: fa20 f306 lsr.w r3, r0, r6
|
|
8000d38: fa2e fe06 lsr.w lr, lr, r6
|
|
8000d3c: ea4f 4917 mov.w r9, r7, lsr #16
|
|
8000d40: 4323 orrs r3, r4
|
|
8000d42: fa00 f801 lsl.w r8, r0, r1
|
|
8000d46: fa1f fc87 uxth.w ip, r7
|
|
8000d4a: fbbe f0f9 udiv r0, lr, r9
|
|
8000d4e: 0c1c lsrs r4, r3, #16
|
|
8000d50: fb09 ee10 mls lr, r9, r0, lr
|
|
8000d54: ea44 440e orr.w r4, r4, lr, lsl #16
|
|
8000d58: fb00 fe0c mul.w lr, r0, ip
|
|
8000d5c: 45a6 cmp lr, r4
|
|
8000d5e: fa02 f201 lsl.w r2, r2, r1
|
|
8000d62: d909 bls.n 8000d78 <__udivmoddi4+0x1a0>
|
|
8000d64: 193c adds r4, r7, r4
|
|
8000d66: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
|
|
8000d6a: f080 809c bcs.w 8000ea6 <__udivmoddi4+0x2ce>
|
|
8000d6e: 45a6 cmp lr, r4
|
|
8000d70: f240 8099 bls.w 8000ea6 <__udivmoddi4+0x2ce>
|
|
8000d74: 3802 subs r0, #2
|
|
8000d76: 443c add r4, r7
|
|
8000d78: eba4 040e sub.w r4, r4, lr
|
|
8000d7c: fa1f fe83 uxth.w lr, r3
|
|
8000d80: fbb4 f3f9 udiv r3, r4, r9
|
|
8000d84: fb09 4413 mls r4, r9, r3, r4
|
|
8000d88: ea4e 4404 orr.w r4, lr, r4, lsl #16
|
|
8000d8c: fb03 fc0c mul.w ip, r3, ip
|
|
8000d90: 45a4 cmp ip, r4
|
|
8000d92: d908 bls.n 8000da6 <__udivmoddi4+0x1ce>
|
|
8000d94: 193c adds r4, r7, r4
|
|
8000d96: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
|
|
8000d9a: f080 8082 bcs.w 8000ea2 <__udivmoddi4+0x2ca>
|
|
8000d9e: 45a4 cmp ip, r4
|
|
8000da0: d97f bls.n 8000ea2 <__udivmoddi4+0x2ca>
|
|
8000da2: 3b02 subs r3, #2
|
|
8000da4: 443c add r4, r7
|
|
8000da6: ea43 4000 orr.w r0, r3, r0, lsl #16
|
|
8000daa: eba4 040c sub.w r4, r4, ip
|
|
8000dae: fba0 ec02 umull lr, ip, r0, r2
|
|
8000db2: 4564 cmp r4, ip
|
|
8000db4: 4673 mov r3, lr
|
|
8000db6: 46e1 mov r9, ip
|
|
8000db8: d362 bcc.n 8000e80 <__udivmoddi4+0x2a8>
|
|
8000dba: d05f beq.n 8000e7c <__udivmoddi4+0x2a4>
|
|
8000dbc: b15d cbz r5, 8000dd6 <__udivmoddi4+0x1fe>
|
|
8000dbe: ebb8 0203 subs.w r2, r8, r3
|
|
8000dc2: eb64 0409 sbc.w r4, r4, r9
|
|
8000dc6: fa04 f606 lsl.w r6, r4, r6
|
|
8000dca: fa22 f301 lsr.w r3, r2, r1
|
|
8000dce: 431e orrs r6, r3
|
|
8000dd0: 40cc lsrs r4, r1
|
|
8000dd2: e9c5 6400 strd r6, r4, [r5]
|
|
8000dd6: 2100 movs r1, #0
|
|
8000dd8: e74f b.n 8000c7a <__udivmoddi4+0xa2>
|
|
8000dda: fbb1 fcf2 udiv ip, r1, r2
|
|
8000dde: 0c01 lsrs r1, r0, #16
|
|
8000de0: ea41 410e orr.w r1, r1, lr, lsl #16
|
|
8000de4: b280 uxth r0, r0
|
|
8000de6: ea40 4201 orr.w r2, r0, r1, lsl #16
|
|
8000dea: 463b mov r3, r7
|
|
8000dec: 4638 mov r0, r7
|
|
8000dee: 463c mov r4, r7
|
|
8000df0: 46b8 mov r8, r7
|
|
8000df2: 46be mov lr, r7
|
|
8000df4: 2620 movs r6, #32
|
|
8000df6: fbb1 f1f7 udiv r1, r1, r7
|
|
8000dfa: eba2 0208 sub.w r2, r2, r8
|
|
8000dfe: ea41 410c orr.w r1, r1, ip, lsl #16
|
|
8000e02: e766 b.n 8000cd2 <__udivmoddi4+0xfa>
|
|
8000e04: 4601 mov r1, r0
|
|
8000e06: e718 b.n 8000c3a <__udivmoddi4+0x62>
|
|
8000e08: 4610 mov r0, r2
|
|
8000e0a: e72c b.n 8000c66 <__udivmoddi4+0x8e>
|
|
8000e0c: f1c6 0220 rsb r2, r6, #32
|
|
8000e10: fa2e f302 lsr.w r3, lr, r2
|
|
8000e14: 40b7 lsls r7, r6
|
|
8000e16: 40b1 lsls r1, r6
|
|
8000e18: fa20 f202 lsr.w r2, r0, r2
|
|
8000e1c: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000e20: 430a orrs r2, r1
|
|
8000e22: fbb3 f8fe udiv r8, r3, lr
|
|
8000e26: b2bc uxth r4, r7
|
|
8000e28: fb0e 3318 mls r3, lr, r8, r3
|
|
8000e2c: 0c11 lsrs r1, r2, #16
|
|
8000e2e: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
8000e32: fb08 f904 mul.w r9, r8, r4
|
|
8000e36: 40b0 lsls r0, r6
|
|
8000e38: 4589 cmp r9, r1
|
|
8000e3a: ea4f 4310 mov.w r3, r0, lsr #16
|
|
8000e3e: b280 uxth r0, r0
|
|
8000e40: d93e bls.n 8000ec0 <__udivmoddi4+0x2e8>
|
|
8000e42: 1879 adds r1, r7, r1
|
|
8000e44: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
8000e48: d201 bcs.n 8000e4e <__udivmoddi4+0x276>
|
|
8000e4a: 4589 cmp r9, r1
|
|
8000e4c: d81f bhi.n 8000e8e <__udivmoddi4+0x2b6>
|
|
8000e4e: eba1 0109 sub.w r1, r1, r9
|
|
8000e52: fbb1 f9fe udiv r9, r1, lr
|
|
8000e56: fb09 f804 mul.w r8, r9, r4
|
|
8000e5a: fb0e 1119 mls r1, lr, r9, r1
|
|
8000e5e: b292 uxth r2, r2
|
|
8000e60: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
8000e64: 4542 cmp r2, r8
|
|
8000e66: d229 bcs.n 8000ebc <__udivmoddi4+0x2e4>
|
|
8000e68: 18ba adds r2, r7, r2
|
|
8000e6a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
8000e6e: d2c4 bcs.n 8000dfa <__udivmoddi4+0x222>
|
|
8000e70: 4542 cmp r2, r8
|
|
8000e72: d2c2 bcs.n 8000dfa <__udivmoddi4+0x222>
|
|
8000e74: f1a9 0102 sub.w r1, r9, #2
|
|
8000e78: 443a add r2, r7
|
|
8000e7a: e7be b.n 8000dfa <__udivmoddi4+0x222>
|
|
8000e7c: 45f0 cmp r8, lr
|
|
8000e7e: d29d bcs.n 8000dbc <__udivmoddi4+0x1e4>
|
|
8000e80: ebbe 0302 subs.w r3, lr, r2
|
|
8000e84: eb6c 0c07 sbc.w ip, ip, r7
|
|
8000e88: 3801 subs r0, #1
|
|
8000e8a: 46e1 mov r9, ip
|
|
8000e8c: e796 b.n 8000dbc <__udivmoddi4+0x1e4>
|
|
8000e8e: eba7 0909 sub.w r9, r7, r9
|
|
8000e92: 4449 add r1, r9
|
|
8000e94: f1a8 0c02 sub.w ip, r8, #2
|
|
8000e98: fbb1 f9fe udiv r9, r1, lr
|
|
8000e9c: fb09 f804 mul.w r8, r9, r4
|
|
8000ea0: e7db b.n 8000e5a <__udivmoddi4+0x282>
|
|
8000ea2: 4673 mov r3, lr
|
|
8000ea4: e77f b.n 8000da6 <__udivmoddi4+0x1ce>
|
|
8000ea6: 4650 mov r0, sl
|
|
8000ea8: e766 b.n 8000d78 <__udivmoddi4+0x1a0>
|
|
8000eaa: 4608 mov r0, r1
|
|
8000eac: e6fd b.n 8000caa <__udivmoddi4+0xd2>
|
|
8000eae: 443b add r3, r7
|
|
8000eb0: 3a02 subs r2, #2
|
|
8000eb2: e733 b.n 8000d1c <__udivmoddi4+0x144>
|
|
8000eb4: f1ac 0c02 sub.w ip, ip, #2
|
|
8000eb8: 443b add r3, r7
|
|
8000eba: e71c b.n 8000cf6 <__udivmoddi4+0x11e>
|
|
8000ebc: 4649 mov r1, r9
|
|
8000ebe: e79c b.n 8000dfa <__udivmoddi4+0x222>
|
|
8000ec0: eba1 0109 sub.w r1, r1, r9
|
|
8000ec4: 46c4 mov ip, r8
|
|
8000ec6: fbb1 f9fe udiv r9, r1, lr
|
|
8000eca: fb09 f804 mul.w r8, r9, r4
|
|
8000ece: e7c4 b.n 8000e5a <__udivmoddi4+0x282>
|
|
|
|
08000ed0 <__aeabi_idiv0>:
|
|
8000ed0: 4770 bx lr
|
|
8000ed2: bf00 nop
|
|
|
|
08000ed4 <I2Cx_MspInit>:
|
|
* @brief Initializes I2C MSP.
|
|
* @param i2c_handler I2C handler
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler)
|
|
{
|
|
8000ed4: b580 push {r7, lr}
|
|
8000ed6: b08a sub sp, #40 @ 0x28
|
|
8000ed8: af00 add r7, sp, #0
|
|
8000eda: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef gpio_init_structure;
|
|
|
|
/*** Configure the GPIOs ***/
|
|
/* Enable GPIO clock */
|
|
DISCOVERY_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
|
|
8000edc: 4b27 ldr r3, [pc, #156] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000ede: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8000ee0: 4a26 ldr r2, [pc, #152] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000ee2: f043 0302 orr.w r3, r3, #2
|
|
8000ee6: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8000ee8: 4b24 ldr r3, [pc, #144] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000eea: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8000eec: f003 0302 and.w r3, r3, #2
|
|
8000ef0: 613b str r3, [r7, #16]
|
|
8000ef2: 693b ldr r3, [r7, #16]
|
|
|
|
/* Configure I2C Tx, Rx as alternate function */
|
|
gpio_init_structure.Pin = DISCOVERY_I2Cx_SCL_PIN | DISCOVERY_I2Cx_SDA_PIN;
|
|
8000ef4: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
8000ef8: 617b str r3, [r7, #20]
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
|
|
8000efa: 2312 movs r3, #18
|
|
8000efc: 61bb str r3, [r7, #24]
|
|
gpio_init_structure.Pull = GPIO_PULLUP;
|
|
8000efe: 2301 movs r3, #1
|
|
8000f00: 61fb str r3, [r7, #28]
|
|
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000f02: 2303 movs r3, #3
|
|
8000f04: 623b str r3, [r7, #32]
|
|
gpio_init_structure.Alternate = DISCOVERY_I2Cx_SCL_SDA_AF;
|
|
8000f06: 2304 movs r3, #4
|
|
8000f08: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
|
8000f0a: f107 0314 add.w r3, r7, #20
|
|
8000f0e: 4619 mov r1, r3
|
|
8000f10: 481b ldr r0, [pc, #108] @ (8000f80 <I2Cx_MspInit+0xac>)
|
|
8000f12: f002 fbe3 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
HAL_GPIO_Init(DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
|
8000f16: f107 0314 add.w r3, r7, #20
|
|
8000f1a: 4619 mov r1, r3
|
|
8000f1c: 4818 ldr r0, [pc, #96] @ (8000f80 <I2Cx_MspInit+0xac>)
|
|
8000f1e: f002 fbdd bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*** Configure the I2C peripheral ***/
|
|
/* Enable I2C clock */
|
|
DISCOVERY_I2Cx_CLK_ENABLE();
|
|
8000f22: 4b16 ldr r3, [pc, #88] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000f24: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8000f26: 4a15 ldr r2, [pc, #84] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000f28: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8000f2c: 6593 str r3, [r2, #88] @ 0x58
|
|
8000f2e: 4b13 ldr r3, [pc, #76] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000f30: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8000f32: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8000f36: 60fb str r3, [r7, #12]
|
|
8000f38: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Force the I2C peripheral clock reset */
|
|
DISCOVERY_I2Cx_FORCE_RESET();
|
|
8000f3a: 4b10 ldr r3, [pc, #64] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000f3c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8000f3e: 4a0f ldr r2, [pc, #60] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000f40: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8000f44: 6393 str r3, [r2, #56] @ 0x38
|
|
|
|
/* Release the I2C peripheral clock reset */
|
|
DISCOVERY_I2Cx_RELEASE_RESET();
|
|
8000f46: 4b0d ldr r3, [pc, #52] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000f48: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8000f4a: 4a0c ldr r2, [pc, #48] @ (8000f7c <I2Cx_MspInit+0xa8>)
|
|
8000f4c: f423 0380 bic.w r3, r3, #4194304 @ 0x400000
|
|
8000f50: 6393 str r3, [r2, #56] @ 0x38
|
|
|
|
/* Enable and set I2Cx Interrupt to a lower priority */
|
|
HAL_NVIC_SetPriority(DISCOVERY_I2Cx_EV_IRQn, 0x0F, 0);
|
|
8000f52: 2200 movs r2, #0
|
|
8000f54: 210f movs r1, #15
|
|
8000f56: 2021 movs r0, #33 @ 0x21
|
|
8000f58: f002 fa7d bl 8003456 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_EV_IRQn);
|
|
8000f5c: 2021 movs r0, #33 @ 0x21
|
|
8000f5e: f002 fa96 bl 800348e <HAL_NVIC_EnableIRQ>
|
|
|
|
/* Enable and set I2Cx Interrupt to a lower priority */
|
|
HAL_NVIC_SetPriority(DISCOVERY_I2Cx_ER_IRQn, 0x0F, 0);
|
|
8000f62: 2200 movs r2, #0
|
|
8000f64: 210f movs r1, #15
|
|
8000f66: 2022 movs r0, #34 @ 0x22
|
|
8000f68: f002 fa75 bl 8003456 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_ER_IRQn);
|
|
8000f6c: 2022 movs r0, #34 @ 0x22
|
|
8000f6e: f002 fa8e bl 800348e <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8000f72: bf00 nop
|
|
8000f74: 3728 adds r7, #40 @ 0x28
|
|
8000f76: 46bd mov sp, r7
|
|
8000f78: bd80 pop {r7, pc}
|
|
8000f7a: bf00 nop
|
|
8000f7c: 40021000 .word 0x40021000
|
|
8000f80: 48000400 .word 0x48000400
|
|
|
|
08000f84 <I2Cx_Init>:
|
|
* @brief Initializes I2C HAL.
|
|
* @param i2c_handler I2C handler
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler)
|
|
{
|
|
8000f84: b580 push {r7, lr}
|
|
8000f86: b082 sub sp, #8
|
|
8000f88: af00 add r7, sp, #0
|
|
8000f8a: 6078 str r0, [r7, #4]
|
|
/* I2C configuration */
|
|
i2c_handler->Instance = DISCOVERY_I2Cx;
|
|
8000f8c: 687b ldr r3, [r7, #4]
|
|
8000f8e: 4a12 ldr r2, [pc, #72] @ (8000fd8 <I2Cx_Init+0x54>)
|
|
8000f90: 601a str r2, [r3, #0]
|
|
i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING;
|
|
8000f92: 687b ldr r3, [r7, #4]
|
|
8000f94: 4a11 ldr r2, [pc, #68] @ (8000fdc <I2Cx_Init+0x58>)
|
|
8000f96: 605a str r2, [r3, #4]
|
|
i2c_handler->Init.OwnAddress1 = 0;
|
|
8000f98: 687b ldr r3, [r7, #4]
|
|
8000f9a: 2200 movs r2, #0
|
|
8000f9c: 609a str r2, [r3, #8]
|
|
i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8000f9e: 687b ldr r3, [r7, #4]
|
|
8000fa0: 2201 movs r2, #1
|
|
8000fa2: 60da str r2, [r3, #12]
|
|
i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8000fa4: 687b ldr r3, [r7, #4]
|
|
8000fa6: 2200 movs r2, #0
|
|
8000fa8: 611a str r2, [r3, #16]
|
|
i2c_handler->Init.OwnAddress2 = 0;
|
|
8000faa: 687b ldr r3, [r7, #4]
|
|
8000fac: 2200 movs r2, #0
|
|
8000fae: 615a str r2, [r3, #20]
|
|
i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8000fb0: 687b ldr r3, [r7, #4]
|
|
8000fb2: 2200 movs r2, #0
|
|
8000fb4: 61da str r2, [r3, #28]
|
|
i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8000fb6: 687b ldr r3, [r7, #4]
|
|
8000fb8: 2200 movs r2, #0
|
|
8000fba: 621a str r2, [r3, #32]
|
|
|
|
/* Init the I2C */
|
|
I2Cx_MspInit(i2c_handler);
|
|
8000fbc: 6878 ldr r0, [r7, #4]
|
|
8000fbe: f7ff ff89 bl 8000ed4 <I2Cx_MspInit>
|
|
HAL_I2C_Init(i2c_handler);
|
|
8000fc2: 6878 ldr r0, [r7, #4]
|
|
8000fc4: f002 fe63 bl 8003c8e <HAL_I2C_Init>
|
|
|
|
/**Configure Analogue filter */
|
|
HAL_I2CEx_ConfigAnalogFilter(i2c_handler, I2C_ANALOGFILTER_ENABLE);
|
|
8000fc8: 2100 movs r1, #0
|
|
8000fca: 6878 ldr r0, [r7, #4]
|
|
8000fcc: f003 fc1a bl 8004804 <HAL_I2CEx_ConfigAnalogFilter>
|
|
}
|
|
8000fd0: bf00 nop
|
|
8000fd2: 3708 adds r7, #8
|
|
8000fd4: 46bd mov sp, r7
|
|
8000fd6: bd80 pop {r7, pc}
|
|
8000fd8: 40005800 .word 0x40005800
|
|
8000fdc: 00702681 .word 0x00702681
|
|
|
|
08000fe0 <I2Cx_ReadMultiple>:
|
|
* @param Buffer Pointer to data buffer
|
|
* @param Length Length of the data
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2Cx_ReadMultiple(I2C_HandleTypeDef *i2c_handler, uint8_t Addr, uint16_t Reg, uint16_t MemAddress, uint8_t *Buffer, uint16_t Length)
|
|
{
|
|
8000fe0: b580 push {r7, lr}
|
|
8000fe2: b08a sub sp, #40 @ 0x28
|
|
8000fe4: af04 add r7, sp, #16
|
|
8000fe6: 60f8 str r0, [r7, #12]
|
|
8000fe8: 4608 mov r0, r1
|
|
8000fea: 4611 mov r1, r2
|
|
8000fec: 461a mov r2, r3
|
|
8000fee: 4603 mov r3, r0
|
|
8000ff0: 72fb strb r3, [r7, #11]
|
|
8000ff2: 460b mov r3, r1
|
|
8000ff4: 813b strh r3, [r7, #8]
|
|
8000ff6: 4613 mov r3, r2
|
|
8000ff8: 80fb strh r3, [r7, #6]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8000ffa: 2300 movs r3, #0
|
|
8000ffc: 75fb strb r3, [r7, #23]
|
|
|
|
status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
|
|
8000ffe: 7afb ldrb r3, [r7, #11]
|
|
8001000: b299 uxth r1, r3
|
|
8001002: 88f8 ldrh r0, [r7, #6]
|
|
8001004: 893a ldrh r2, [r7, #8]
|
|
8001006: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
800100a: 9302 str r3, [sp, #8]
|
|
800100c: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
800100e: 9301 str r3, [sp, #4]
|
|
8001010: 6a3b ldr r3, [r7, #32]
|
|
8001012: 9300 str r3, [sp, #0]
|
|
8001014: 4603 mov r3, r0
|
|
8001016: 68f8 ldr r0, [r7, #12]
|
|
8001018: f003 f818 bl 800404c <HAL_I2C_Mem_Read>
|
|
800101c: 4603 mov r3, r0
|
|
800101e: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the communication status */
|
|
if(status != HAL_OK)
|
|
8001020: 7dfb ldrb r3, [r7, #23]
|
|
8001022: 2b00 cmp r3, #0
|
|
8001024: d004 beq.n 8001030 <I2Cx_ReadMultiple+0x50>
|
|
{
|
|
/* I2C error occured */
|
|
I2Cx_Error(i2c_handler, Addr);
|
|
8001026: 7afb ldrb r3, [r7, #11]
|
|
8001028: 4619 mov r1, r3
|
|
800102a: 68f8 ldr r0, [r7, #12]
|
|
800102c: f000 f832 bl 8001094 <I2Cx_Error>
|
|
}
|
|
return status;
|
|
8001030: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8001032: 4618 mov r0, r3
|
|
8001034: 3718 adds r7, #24
|
|
8001036: 46bd mov sp, r7
|
|
8001038: bd80 pop {r7, pc}
|
|
|
|
0800103a <I2Cx_WriteMultiple>:
|
|
* @param Buffer The target register value to be written
|
|
* @param Length buffer size to be written
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2Cx_WriteMultiple(I2C_HandleTypeDef *i2c_handler, uint8_t Addr, uint16_t Reg, uint16_t MemAddress, uint8_t *Buffer, uint16_t Length)
|
|
{
|
|
800103a: b580 push {r7, lr}
|
|
800103c: b08a sub sp, #40 @ 0x28
|
|
800103e: af04 add r7, sp, #16
|
|
8001040: 60f8 str r0, [r7, #12]
|
|
8001042: 4608 mov r0, r1
|
|
8001044: 4611 mov r1, r2
|
|
8001046: 461a mov r2, r3
|
|
8001048: 4603 mov r3, r0
|
|
800104a: 72fb strb r3, [r7, #11]
|
|
800104c: 460b mov r3, r1
|
|
800104e: 813b strh r3, [r7, #8]
|
|
8001050: 4613 mov r3, r2
|
|
8001052: 80fb strh r3, [r7, #6]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001054: 2300 movs r3, #0
|
|
8001056: 75fb strb r3, [r7, #23]
|
|
|
|
status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
|
|
8001058: 7afb ldrb r3, [r7, #11]
|
|
800105a: b299 uxth r1, r3
|
|
800105c: 88f8 ldrh r0, [r7, #6]
|
|
800105e: 893a ldrh r2, [r7, #8]
|
|
8001060: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001064: 9302 str r3, [sp, #8]
|
|
8001066: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
8001068: 9301 str r3, [sp, #4]
|
|
800106a: 6a3b ldr r3, [r7, #32]
|
|
800106c: 9300 str r3, [sp, #0]
|
|
800106e: 4603 mov r3, r0
|
|
8001070: 68f8 ldr r0, [r7, #12]
|
|
8001072: f002 fed7 bl 8003e24 <HAL_I2C_Mem_Write>
|
|
8001076: 4603 mov r3, r0
|
|
8001078: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the communication status */
|
|
if(status != HAL_OK)
|
|
800107a: 7dfb ldrb r3, [r7, #23]
|
|
800107c: 2b00 cmp r3, #0
|
|
800107e: d004 beq.n 800108a <I2Cx_WriteMultiple+0x50>
|
|
{
|
|
/* Re-Initiaize the I2C Bus */
|
|
I2Cx_Error(i2c_handler, Addr);
|
|
8001080: 7afb ldrb r3, [r7, #11]
|
|
8001082: 4619 mov r1, r3
|
|
8001084: 68f8 ldr r0, [r7, #12]
|
|
8001086: f000 f805 bl 8001094 <I2Cx_Error>
|
|
}
|
|
return status;
|
|
800108a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800108c: 4618 mov r0, r3
|
|
800108e: 3718 adds r7, #24
|
|
8001090: 46bd mov sp, r7
|
|
8001092: bd80 pop {r7, pc}
|
|
|
|
08001094 <I2Cx_Error>:
|
|
* @param i2c_handler I2C handler
|
|
* @param Addr I2C Address
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr)
|
|
{
|
|
8001094: b580 push {r7, lr}
|
|
8001096: b082 sub sp, #8
|
|
8001098: af00 add r7, sp, #0
|
|
800109a: 6078 str r0, [r7, #4]
|
|
800109c: 460b mov r3, r1
|
|
800109e: 70fb strb r3, [r7, #3]
|
|
/* De-initialize the I2C communication bus */
|
|
HAL_I2C_DeInit(i2c_handler);
|
|
80010a0: 6878 ldr r0, [r7, #4]
|
|
80010a2: f002 fe8f bl 8003dc4 <HAL_I2C_DeInit>
|
|
|
|
/* Re-Initialize the I2C communication bus */
|
|
I2Cx_Init(i2c_handler);
|
|
80010a6: 6878 ldr r0, [r7, #4]
|
|
80010a8: f7ff ff6c bl 8000f84 <I2Cx_Init>
|
|
}
|
|
80010ac: bf00 nop
|
|
80010ae: 3708 adds r7, #8
|
|
80010b0: 46bd mov sp, r7
|
|
80010b2: bd80 pop {r7, pc}
|
|
|
|
080010b4 <SENSOR_IO_Init>:
|
|
/**
|
|
* @brief Initializes Sensors low level.
|
|
* @retval None
|
|
*/
|
|
void SENSOR_IO_Init(void)
|
|
{
|
|
80010b4: b580 push {r7, lr}
|
|
80010b6: af00 add r7, sp, #0
|
|
I2Cx_Init(&hI2cHandler);
|
|
80010b8: 4802 ldr r0, [pc, #8] @ (80010c4 <SENSOR_IO_Init+0x10>)
|
|
80010ba: f7ff ff63 bl 8000f84 <I2Cx_Init>
|
|
}
|
|
80010be: bf00 nop
|
|
80010c0: bd80 pop {r7, pc}
|
|
80010c2: bf00 nop
|
|
80010c4: 200002b4 .word 0x200002b4
|
|
|
|
080010c8 <SENSOR_IO_Write>:
|
|
* @param Reg Reg address
|
|
* @param Value Data to be written
|
|
* @retval None
|
|
*/
|
|
void SENSOR_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
|
|
{
|
|
80010c8: b580 push {r7, lr}
|
|
80010ca: b084 sub sp, #16
|
|
80010cc: af02 add r7, sp, #8
|
|
80010ce: 4603 mov r3, r0
|
|
80010d0: 71fb strb r3, [r7, #7]
|
|
80010d2: 460b mov r3, r1
|
|
80010d4: 71bb strb r3, [r7, #6]
|
|
80010d6: 4613 mov r3, r2
|
|
80010d8: 717b strb r3, [r7, #5]
|
|
I2Cx_WriteMultiple(&hI2cHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1);
|
|
80010da: 79bb ldrb r3, [r7, #6]
|
|
80010dc: b29a uxth r2, r3
|
|
80010de: 79f9 ldrb r1, [r7, #7]
|
|
80010e0: 2301 movs r3, #1
|
|
80010e2: 9301 str r3, [sp, #4]
|
|
80010e4: 1d7b adds r3, r7, #5
|
|
80010e6: 9300 str r3, [sp, #0]
|
|
80010e8: 2301 movs r3, #1
|
|
80010ea: 4803 ldr r0, [pc, #12] @ (80010f8 <SENSOR_IO_Write+0x30>)
|
|
80010ec: f7ff ffa5 bl 800103a <I2Cx_WriteMultiple>
|
|
}
|
|
80010f0: bf00 nop
|
|
80010f2: 3708 adds r7, #8
|
|
80010f4: 46bd mov sp, r7
|
|
80010f6: bd80 pop {r7, pc}
|
|
80010f8: 200002b4 .word 0x200002b4
|
|
|
|
080010fc <SENSOR_IO_Read>:
|
|
* @param Addr I2C address
|
|
* @param Reg Reg address
|
|
* @retval Data to be read
|
|
*/
|
|
uint8_t SENSOR_IO_Read(uint8_t Addr, uint8_t Reg)
|
|
{
|
|
80010fc: b580 push {r7, lr}
|
|
80010fe: b086 sub sp, #24
|
|
8001100: af02 add r7, sp, #8
|
|
8001102: 4603 mov r3, r0
|
|
8001104: 460a mov r2, r1
|
|
8001106: 71fb strb r3, [r7, #7]
|
|
8001108: 4613 mov r3, r2
|
|
800110a: 71bb strb r3, [r7, #6]
|
|
uint8_t read_value = 0;
|
|
800110c: 2300 movs r3, #0
|
|
800110e: 73fb strb r3, [r7, #15]
|
|
|
|
I2Cx_ReadMultiple(&hI2cHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1);
|
|
8001110: 79bb ldrb r3, [r7, #6]
|
|
8001112: b29a uxth r2, r3
|
|
8001114: 79f9 ldrb r1, [r7, #7]
|
|
8001116: 2301 movs r3, #1
|
|
8001118: 9301 str r3, [sp, #4]
|
|
800111a: f107 030f add.w r3, r7, #15
|
|
800111e: 9300 str r3, [sp, #0]
|
|
8001120: 2301 movs r3, #1
|
|
8001122: 4804 ldr r0, [pc, #16] @ (8001134 <SENSOR_IO_Read+0x38>)
|
|
8001124: f7ff ff5c bl 8000fe0 <I2Cx_ReadMultiple>
|
|
|
|
return read_value;
|
|
8001128: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800112a: 4618 mov r0, r3
|
|
800112c: 3710 adds r7, #16
|
|
800112e: 46bd mov sp, r7
|
|
8001130: bd80 pop {r7, pc}
|
|
8001132: bf00 nop
|
|
8001134: 200002b4 .word 0x200002b4
|
|
|
|
08001138 <SENSOR_IO_ReadMultiple>:
|
|
* @param Buffer Pointer to data buffer
|
|
* @param Length Length of the data
|
|
* @retval HAL status
|
|
*/
|
|
uint16_t SENSOR_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length)
|
|
{
|
|
8001138: b580 push {r7, lr}
|
|
800113a: b084 sub sp, #16
|
|
800113c: af02 add r7, sp, #8
|
|
800113e: 603a str r2, [r7, #0]
|
|
8001140: 461a mov r2, r3
|
|
8001142: 4603 mov r3, r0
|
|
8001144: 71fb strb r3, [r7, #7]
|
|
8001146: 460b mov r3, r1
|
|
8001148: 71bb strb r3, [r7, #6]
|
|
800114a: 4613 mov r3, r2
|
|
800114c: 80bb strh r3, [r7, #4]
|
|
return I2Cx_ReadMultiple(&hI2cHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, Buffer, Length);
|
|
800114e: 79bb ldrb r3, [r7, #6]
|
|
8001150: b29a uxth r2, r3
|
|
8001152: 79f9 ldrb r1, [r7, #7]
|
|
8001154: 88bb ldrh r3, [r7, #4]
|
|
8001156: 9301 str r3, [sp, #4]
|
|
8001158: 683b ldr r3, [r7, #0]
|
|
800115a: 9300 str r3, [sp, #0]
|
|
800115c: 2301 movs r3, #1
|
|
800115e: 4804 ldr r0, [pc, #16] @ (8001170 <SENSOR_IO_ReadMultiple+0x38>)
|
|
8001160: f7ff ff3e bl 8000fe0 <I2Cx_ReadMultiple>
|
|
8001164: 4603 mov r3, r0
|
|
}
|
|
8001166: 4618 mov r0, r3
|
|
8001168: 3708 adds r7, #8
|
|
800116a: 46bd mov sp, r7
|
|
800116c: bd80 pop {r7, pc}
|
|
800116e: bf00 nop
|
|
8001170: 200002b4 .word 0x200002b4
|
|
|
|
08001174 <BSP_ACCELERO_Init>:
|
|
/**
|
|
* @brief Initialize the ACCELERO.
|
|
* @retval ACCELERO_OK or ACCELERO_ERROR
|
|
*/
|
|
ACCELERO_StatusTypeDef BSP_ACCELERO_Init(void)
|
|
{
|
|
8001174: b580 push {r7, lr}
|
|
8001176: b084 sub sp, #16
|
|
8001178: af00 add r7, sp, #0
|
|
ACCELERO_StatusTypeDef ret = ACCELERO_OK;
|
|
800117a: 2300 movs r3, #0
|
|
800117c: 73fb strb r3, [r7, #15]
|
|
uint16_t ctrl = 0x0000;
|
|
800117e: 2300 movs r3, #0
|
|
8001180: 81bb strh r3, [r7, #12]
|
|
ACCELERO_InitTypeDef LSM6DSL_InitStructure;
|
|
|
|
if(Lsm6dslAccDrv.ReadID() != LSM6DSL_ACC_GYRO_WHO_AM_I)
|
|
8001182: 4b1a ldr r3, [pc, #104] @ (80011ec <BSP_ACCELERO_Init+0x78>)
|
|
8001184: 689b ldr r3, [r3, #8]
|
|
8001186: 4798 blx r3
|
|
8001188: 4603 mov r3, r0
|
|
800118a: 2b6a cmp r3, #106 @ 0x6a
|
|
800118c: d002 beq.n 8001194 <BSP_ACCELERO_Init+0x20>
|
|
{
|
|
ret = ACCELERO_ERROR;
|
|
800118e: 2301 movs r3, #1
|
|
8001190: 73fb strb r3, [r7, #15]
|
|
8001192: e025 b.n 80011e0 <BSP_ACCELERO_Init+0x6c>
|
|
}
|
|
else
|
|
{
|
|
/* Initialize the ACCELERO accelerometer driver structure */
|
|
AccelerometerDrv = &Lsm6dslAccDrv;
|
|
8001194: 4b16 ldr r3, [pc, #88] @ (80011f0 <BSP_ACCELERO_Init+0x7c>)
|
|
8001196: 4a15 ldr r2, [pc, #84] @ (80011ec <BSP_ACCELERO_Init+0x78>)
|
|
8001198: 601a str r2, [r3, #0]
|
|
|
|
/* MEMS configuration ------------------------------------------------------*/
|
|
/* Fill the ACCELERO accelerometer structure */
|
|
LSM6DSL_InitStructure.AccOutput_DataRate = LSM6DSL_ODR_52Hz;
|
|
800119a: 2330 movs r3, #48 @ 0x30
|
|
800119c: 717b strb r3, [r7, #5]
|
|
LSM6DSL_InitStructure.Axes_Enable = 0;
|
|
800119e: 2300 movs r3, #0
|
|
80011a0: 71bb strb r3, [r7, #6]
|
|
LSM6DSL_InitStructure.AccFull_Scale = LSM6DSL_ACC_FULLSCALE_2G;
|
|
80011a2: 2300 movs r3, #0
|
|
80011a4: 72bb strb r3, [r7, #10]
|
|
LSM6DSL_InitStructure.BlockData_Update = LSM6DSL_BDU_BLOCK_UPDATE;
|
|
80011a6: 2340 movs r3, #64 @ 0x40
|
|
80011a8: 723b strb r3, [r7, #8]
|
|
LSM6DSL_InitStructure.High_Resolution = 0;
|
|
80011aa: 2300 movs r3, #0
|
|
80011ac: 71fb strb r3, [r7, #7]
|
|
LSM6DSL_InitStructure.Communication_Mode = 0;
|
|
80011ae: 2300 movs r3, #0
|
|
80011b0: 72fb strb r3, [r7, #11]
|
|
|
|
/* Configure MEMS: data rate, full scale */
|
|
ctrl = (LSM6DSL_InitStructure.AccOutput_DataRate | LSM6DSL_InitStructure.AccFull_Scale);
|
|
80011b2: 797a ldrb r2, [r7, #5]
|
|
80011b4: 7abb ldrb r3, [r7, #10]
|
|
80011b6: 4313 orrs r3, r2
|
|
80011b8: b2db uxtb r3, r3
|
|
80011ba: 81bb strh r3, [r7, #12]
|
|
|
|
/* Configure MEMS: BDU and Auto-increment for multi read/write */
|
|
ctrl |= ((LSM6DSL_InitStructure.BlockData_Update | LSM6DSL_ACC_GYRO_IF_INC_ENABLED) << 8);
|
|
80011bc: 7a3b ldrb r3, [r7, #8]
|
|
80011be: f043 0304 orr.w r3, r3, #4
|
|
80011c2: b2db uxtb r3, r3
|
|
80011c4: b21b sxth r3, r3
|
|
80011c6: 021b lsls r3, r3, #8
|
|
80011c8: b21a sxth r2, r3
|
|
80011ca: f9b7 300c ldrsh.w r3, [r7, #12]
|
|
80011ce: 4313 orrs r3, r2
|
|
80011d0: b21b sxth r3, r3
|
|
80011d2: 81bb strh r3, [r7, #12]
|
|
|
|
/* Configure the ACCELERO accelerometer main parameters */
|
|
AccelerometerDrv->Init(ctrl);
|
|
80011d4: 4b06 ldr r3, [pc, #24] @ (80011f0 <BSP_ACCELERO_Init+0x7c>)
|
|
80011d6: 681b ldr r3, [r3, #0]
|
|
80011d8: 681b ldr r3, [r3, #0]
|
|
80011da: 89ba ldrh r2, [r7, #12]
|
|
80011dc: 4610 mov r0, r2
|
|
80011de: 4798 blx r3
|
|
}
|
|
|
|
return ret;
|
|
80011e0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80011e2: 4618 mov r0, r3
|
|
80011e4: 3710 adds r7, #16
|
|
80011e6: 46bd mov sp, r7
|
|
80011e8: bd80 pop {r7, pc}
|
|
80011ea: bf00 nop
|
|
80011ec: 2000005c .word 0x2000005c
|
|
80011f0: 20000308 .word 0x20000308
|
|
|
|
080011f4 <BSP_ACCELERO_DeInit>:
|
|
/**
|
|
* @brief DeInitialize the ACCELERO.
|
|
* @retval None.
|
|
*/
|
|
void BSP_ACCELERO_DeInit(void)
|
|
{
|
|
80011f4: b580 push {r7, lr}
|
|
80011f6: af00 add r7, sp, #0
|
|
/* DeInitialize the accelerometer IO interfaces */
|
|
if(AccelerometerDrv != NULL)
|
|
80011f8: 4b07 ldr r3, [pc, #28] @ (8001218 <BSP_ACCELERO_DeInit+0x24>)
|
|
80011fa: 681b ldr r3, [r3, #0]
|
|
80011fc: 2b00 cmp r3, #0
|
|
80011fe: d008 beq.n 8001212 <BSP_ACCELERO_DeInit+0x1e>
|
|
{
|
|
if(AccelerometerDrv->DeInit != NULL)
|
|
8001200: 4b05 ldr r3, [pc, #20] @ (8001218 <BSP_ACCELERO_DeInit+0x24>)
|
|
8001202: 681b ldr r3, [r3, #0]
|
|
8001204: 685b ldr r3, [r3, #4]
|
|
8001206: 2b00 cmp r3, #0
|
|
8001208: d003 beq.n 8001212 <BSP_ACCELERO_DeInit+0x1e>
|
|
{
|
|
AccelerometerDrv->DeInit();
|
|
800120a: 4b03 ldr r3, [pc, #12] @ (8001218 <BSP_ACCELERO_DeInit+0x24>)
|
|
800120c: 681b ldr r3, [r3, #0]
|
|
800120e: 685b ldr r3, [r3, #4]
|
|
8001210: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
8001212: bf00 nop
|
|
8001214: bd80 pop {r7, pc}
|
|
8001216: bf00 nop
|
|
8001218: 20000308 .word 0x20000308
|
|
|
|
0800121c <BSP_ACCELERO_AccGetXYZ>:
|
|
* @param pDataXYZ Pointer on 3 angular accelerations table with
|
|
* pDataXYZ[0] = X axis, pDataXYZ[1] = Y axis, pDataXYZ[2] = Z axis
|
|
* @retval None
|
|
*/
|
|
void BSP_ACCELERO_AccGetXYZ(int16_t *pDataXYZ)
|
|
{
|
|
800121c: b580 push {r7, lr}
|
|
800121e: b082 sub sp, #8
|
|
8001220: af00 add r7, sp, #0
|
|
8001222: 6078 str r0, [r7, #4]
|
|
if(AccelerometerDrv != NULL)
|
|
8001224: 4b08 ldr r3, [pc, #32] @ (8001248 <BSP_ACCELERO_AccGetXYZ+0x2c>)
|
|
8001226: 681b ldr r3, [r3, #0]
|
|
8001228: 2b00 cmp r3, #0
|
|
800122a: d009 beq.n 8001240 <BSP_ACCELERO_AccGetXYZ+0x24>
|
|
{
|
|
if(AccelerometerDrv->GetXYZ != NULL)
|
|
800122c: 4b06 ldr r3, [pc, #24] @ (8001248 <BSP_ACCELERO_AccGetXYZ+0x2c>)
|
|
800122e: 681b ldr r3, [r3, #0]
|
|
8001230: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001232: 2b00 cmp r3, #0
|
|
8001234: d004 beq.n 8001240 <BSP_ACCELERO_AccGetXYZ+0x24>
|
|
{
|
|
AccelerometerDrv->GetXYZ(pDataXYZ);
|
|
8001236: 4b04 ldr r3, [pc, #16] @ (8001248 <BSP_ACCELERO_AccGetXYZ+0x2c>)
|
|
8001238: 681b ldr r3, [r3, #0]
|
|
800123a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800123c: 6878 ldr r0, [r7, #4]
|
|
800123e: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
8001240: bf00 nop
|
|
8001242: 3708 adds r7, #8
|
|
8001244: 46bd mov sp, r7
|
|
8001246: bd80 pop {r7, pc}
|
|
8001248: 20000308 .word 0x20000308
|
|
|
|
0800124c <BSP_GYRO_Init>:
|
|
/**
|
|
* @brief Initialize Gyroscope.
|
|
* @retval GYRO_OK or GYRO_ERROR
|
|
*/
|
|
uint8_t BSP_GYRO_Init(void)
|
|
{
|
|
800124c: b580 push {r7, lr}
|
|
800124e: b084 sub sp, #16
|
|
8001250: af00 add r7, sp, #0
|
|
uint8_t ret = GYRO_ERROR;
|
|
8001252: 2301 movs r3, #1
|
|
8001254: 73fb strb r3, [r7, #15]
|
|
uint16_t ctrl = 0x0000;
|
|
8001256: 2300 movs r3, #0
|
|
8001258: 81bb strh r3, [r7, #12]
|
|
GYRO_InitTypeDef LSM6DSL_InitStructure;
|
|
|
|
if(Lsm6dslGyroDrv.ReadID() != LSM6DSL_ACC_GYRO_WHO_AM_I)
|
|
800125a: 4b1c ldr r3, [pc, #112] @ (80012cc <BSP_GYRO_Init+0x80>)
|
|
800125c: 689b ldr r3, [r3, #8]
|
|
800125e: 4798 blx r3
|
|
8001260: 4603 mov r3, r0
|
|
8001262: 2b6a cmp r3, #106 @ 0x6a
|
|
8001264: d002 beq.n 800126c <BSP_GYRO_Init+0x20>
|
|
{
|
|
ret = GYRO_ERROR;
|
|
8001266: 2301 movs r3, #1
|
|
8001268: 73fb strb r3, [r7, #15]
|
|
800126a: e029 b.n 80012c0 <BSP_GYRO_Init+0x74>
|
|
}
|
|
else
|
|
{
|
|
/* Initialize the gyroscope driver structure */
|
|
GyroscopeDrv = &Lsm6dslGyroDrv;
|
|
800126c: 4b18 ldr r3, [pc, #96] @ (80012d0 <BSP_GYRO_Init+0x84>)
|
|
800126e: 4a17 ldr r2, [pc, #92] @ (80012cc <BSP_GYRO_Init+0x80>)
|
|
8001270: 601a str r2, [r3, #0]
|
|
|
|
/* Configure Mems : data rate, power mode, full scale and axes */
|
|
LSM6DSL_InitStructure.Power_Mode = 0;
|
|
8001272: 2300 movs r3, #0
|
|
8001274: 713b strb r3, [r7, #4]
|
|
LSM6DSL_InitStructure.Output_DataRate = LSM6DSL_ODR_52Hz;
|
|
8001276: 2330 movs r3, #48 @ 0x30
|
|
8001278: 717b strb r3, [r7, #5]
|
|
LSM6DSL_InitStructure.Axes_Enable = 0;
|
|
800127a: 2300 movs r3, #0
|
|
800127c: 71bb strb r3, [r7, #6]
|
|
LSM6DSL_InitStructure.Band_Width = 0;
|
|
800127e: 2300 movs r3, #0
|
|
8001280: 71fb strb r3, [r7, #7]
|
|
LSM6DSL_InitStructure.BlockData_Update = LSM6DSL_BDU_BLOCK_UPDATE;
|
|
8001282: 2340 movs r3, #64 @ 0x40
|
|
8001284: 723b strb r3, [r7, #8]
|
|
LSM6DSL_InitStructure.Endianness = 0;
|
|
8001286: 2300 movs r3, #0
|
|
8001288: 727b strb r3, [r7, #9]
|
|
LSM6DSL_InitStructure.Full_Scale = LSM6DSL_GYRO_FS_2000;
|
|
800128a: 230c movs r3, #12
|
|
800128c: 72bb strb r3, [r7, #10]
|
|
|
|
/* Configure MEMS: data rate, full scale */
|
|
ctrl = (LSM6DSL_InitStructure.Full_Scale | LSM6DSL_InitStructure.Output_DataRate);
|
|
800128e: 7aba ldrb r2, [r7, #10]
|
|
8001290: 797b ldrb r3, [r7, #5]
|
|
8001292: 4313 orrs r3, r2
|
|
8001294: b2db uxtb r3, r3
|
|
8001296: 81bb strh r3, [r7, #12]
|
|
|
|
/* Configure MEMS: BDU and Auto-increment for multi read/write */
|
|
ctrl |= ((LSM6DSL_InitStructure.BlockData_Update | LSM6DSL_ACC_GYRO_IF_INC_ENABLED) << 8);
|
|
8001298: 7a3b ldrb r3, [r7, #8]
|
|
800129a: f043 0304 orr.w r3, r3, #4
|
|
800129e: b2db uxtb r3, r3
|
|
80012a0: b21b sxth r3, r3
|
|
80012a2: 021b lsls r3, r3, #8
|
|
80012a4: b21a sxth r2, r3
|
|
80012a6: f9b7 300c ldrsh.w r3, [r7, #12]
|
|
80012aa: 4313 orrs r3, r2
|
|
80012ac: b21b sxth r3, r3
|
|
80012ae: 81bb strh r3, [r7, #12]
|
|
|
|
/* Initialize component */
|
|
GyroscopeDrv->Init(ctrl);
|
|
80012b0: 4b07 ldr r3, [pc, #28] @ (80012d0 <BSP_GYRO_Init+0x84>)
|
|
80012b2: 681b ldr r3, [r3, #0]
|
|
80012b4: 681b ldr r3, [r3, #0]
|
|
80012b6: 89ba ldrh r2, [r7, #12]
|
|
80012b8: 4610 mov r0, r2
|
|
80012ba: 4798 blx r3
|
|
|
|
ret = GYRO_OK;
|
|
80012bc: 2300 movs r3, #0
|
|
80012be: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return ret;
|
|
80012c0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80012c2: 4618 mov r0, r3
|
|
80012c4: 3710 adds r7, #16
|
|
80012c6: 46bd mov sp, r7
|
|
80012c8: bd80 pop {r7, pc}
|
|
80012ca: bf00 nop
|
|
80012cc: 20000090 .word 0x20000090
|
|
80012d0: 2000030c .word 0x2000030c
|
|
|
|
080012d4 <BSP_GYRO_DeInit>:
|
|
|
|
/**
|
|
* @brief DeInitialize Gyroscope.
|
|
*/
|
|
void BSP_GYRO_DeInit(void)
|
|
{
|
|
80012d4: b580 push {r7, lr}
|
|
80012d6: af00 add r7, sp, #0
|
|
/* DeInitialize the Gyroscope IO interfaces */
|
|
if(GyroscopeDrv != NULL)
|
|
80012d8: 4b07 ldr r3, [pc, #28] @ (80012f8 <BSP_GYRO_DeInit+0x24>)
|
|
80012da: 681b ldr r3, [r3, #0]
|
|
80012dc: 2b00 cmp r3, #0
|
|
80012de: d008 beq.n 80012f2 <BSP_GYRO_DeInit+0x1e>
|
|
{
|
|
if(GyroscopeDrv->DeInit!= NULL)
|
|
80012e0: 4b05 ldr r3, [pc, #20] @ (80012f8 <BSP_GYRO_DeInit+0x24>)
|
|
80012e2: 681b ldr r3, [r3, #0]
|
|
80012e4: 685b ldr r3, [r3, #4]
|
|
80012e6: 2b00 cmp r3, #0
|
|
80012e8: d003 beq.n 80012f2 <BSP_GYRO_DeInit+0x1e>
|
|
{
|
|
GyroscopeDrv->DeInit();
|
|
80012ea: 4b03 ldr r3, [pc, #12] @ (80012f8 <BSP_GYRO_DeInit+0x24>)
|
|
80012ec: 681b ldr r3, [r3, #0]
|
|
80012ee: 685b ldr r3, [r3, #4]
|
|
80012f0: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
80012f2: bf00 nop
|
|
80012f4: bd80 pop {r7, pc}
|
|
80012f6: bf00 nop
|
|
80012f8: 2000030c .word 0x2000030c
|
|
|
|
080012fc <BSP_GYRO_GetXYZ>:
|
|
/**
|
|
* @brief Get XYZ angular acceleration from the Gyroscope.
|
|
* @param pfData: pointer on floating array
|
|
*/
|
|
void BSP_GYRO_GetXYZ(float* pfData)
|
|
{
|
|
80012fc: b580 push {r7, lr}
|
|
80012fe: b082 sub sp, #8
|
|
8001300: af00 add r7, sp, #0
|
|
8001302: 6078 str r0, [r7, #4]
|
|
if(GyroscopeDrv != NULL)
|
|
8001304: 4b08 ldr r3, [pc, #32] @ (8001328 <BSP_GYRO_GetXYZ+0x2c>)
|
|
8001306: 681b ldr r3, [r3, #0]
|
|
8001308: 2b00 cmp r3, #0
|
|
800130a: d009 beq.n 8001320 <BSP_GYRO_GetXYZ+0x24>
|
|
{
|
|
if(GyroscopeDrv->GetXYZ!= NULL)
|
|
800130c: 4b06 ldr r3, [pc, #24] @ (8001328 <BSP_GYRO_GetXYZ+0x2c>)
|
|
800130e: 681b ldr r3, [r3, #0]
|
|
8001310: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001312: 2b00 cmp r3, #0
|
|
8001314: d004 beq.n 8001320 <BSP_GYRO_GetXYZ+0x24>
|
|
{
|
|
GyroscopeDrv->GetXYZ(pfData);
|
|
8001316: 4b04 ldr r3, [pc, #16] @ (8001328 <BSP_GYRO_GetXYZ+0x2c>)
|
|
8001318: 681b ldr r3, [r3, #0]
|
|
800131a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800131c: 6878 ldr r0, [r7, #4]
|
|
800131e: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
8001320: bf00 nop
|
|
8001322: 3708 adds r7, #8
|
|
8001324: 46bd mov sp, r7
|
|
8001326: bd80 pop {r7, pc}
|
|
8001328: 2000030c .word 0x2000030c
|
|
|
|
0800132c <BSP_HSENSOR_Init>:
|
|
/**
|
|
* @brief Initializes peripherals used by the I2C Humidity Sensor driver.
|
|
* @retval HSENSOR status
|
|
*/
|
|
uint32_t BSP_HSENSOR_Init(void)
|
|
{
|
|
800132c: b580 push {r7, lr}
|
|
800132e: b082 sub sp, #8
|
|
8001330: af00 add r7, sp, #0
|
|
uint32_t ret;
|
|
|
|
if(HTS221_H_Drv.ReadID(HTS221_I2C_ADDRESS) != HTS221_WHO_AM_I_VAL)
|
|
8001332: 4b0c ldr r3, [pc, #48] @ (8001364 <BSP_HSENSOR_Init+0x38>)
|
|
8001334: 685b ldr r3, [r3, #4]
|
|
8001336: 20be movs r0, #190 @ 0xbe
|
|
8001338: 4798 blx r3
|
|
800133a: 4603 mov r3, r0
|
|
800133c: 2bbc cmp r3, #188 @ 0xbc
|
|
800133e: d002 beq.n 8001346 <BSP_HSENSOR_Init+0x1a>
|
|
{
|
|
ret = HSENSOR_ERROR;
|
|
8001340: 2301 movs r3, #1
|
|
8001342: 607b str r3, [r7, #4]
|
|
8001344: e009 b.n 800135a <BSP_HSENSOR_Init+0x2e>
|
|
}
|
|
else
|
|
{
|
|
Hsensor_drv = &HTS221_H_Drv;
|
|
8001346: 4b08 ldr r3, [pc, #32] @ (8001368 <BSP_HSENSOR_Init+0x3c>)
|
|
8001348: 4a06 ldr r2, [pc, #24] @ (8001364 <BSP_HSENSOR_Init+0x38>)
|
|
800134a: 601a str r2, [r3, #0]
|
|
/* HSENSOR Init */
|
|
Hsensor_drv->Init(HTS221_I2C_ADDRESS);
|
|
800134c: 4b06 ldr r3, [pc, #24] @ (8001368 <BSP_HSENSOR_Init+0x3c>)
|
|
800134e: 681b ldr r3, [r3, #0]
|
|
8001350: 681b ldr r3, [r3, #0]
|
|
8001352: 20be movs r0, #190 @ 0xbe
|
|
8001354: 4798 blx r3
|
|
ret = HSENSOR_OK;
|
|
8001356: 2300 movs r3, #0
|
|
8001358: 607b str r3, [r7, #4]
|
|
}
|
|
|
|
return ret;
|
|
800135a: 687b ldr r3, [r7, #4]
|
|
}
|
|
800135c: 4618 mov r0, r3
|
|
800135e: 3708 adds r7, #8
|
|
8001360: 46bd mov sp, r7
|
|
8001362: bd80 pop {r7, pc}
|
|
8001364: 20000000 .word 0x20000000
|
|
8001368: 20000310 .word 0x20000310
|
|
|
|
0800136c <BSP_HSENSOR_ReadHumidity>:
|
|
/**
|
|
* @brief Read Humidity register of HTS221.
|
|
* @retval HTS221 measured humidity value.
|
|
*/
|
|
float BSP_HSENSOR_ReadHumidity(void)
|
|
{
|
|
800136c: b580 push {r7, lr}
|
|
800136e: af00 add r7, sp, #0
|
|
return Hsensor_drv->ReadHumidity(HTS221_I2C_ADDRESS);
|
|
8001370: 4b04 ldr r3, [pc, #16] @ (8001384 <BSP_HSENSOR_ReadHumidity+0x18>)
|
|
8001372: 681b ldr r3, [r3, #0]
|
|
8001374: 689b ldr r3, [r3, #8]
|
|
8001376: 20be movs r0, #190 @ 0xbe
|
|
8001378: 4798 blx r3
|
|
800137a: eef0 7a40 vmov.f32 s15, s0
|
|
}
|
|
800137e: eeb0 0a67 vmov.f32 s0, s15
|
|
8001382: bd80 pop {r7, pc}
|
|
8001384: 20000310 .word 0x20000310
|
|
|
|
08001388 <BSP_MAGNETO_Init>:
|
|
/**
|
|
* @brief Initialize a magnetometer sensor
|
|
* @retval COMPONENT_ERROR in case of failure
|
|
*/
|
|
MAGNETO_StatusTypeDef BSP_MAGNETO_Init(void)
|
|
{
|
|
8001388: b580 push {r7, lr}
|
|
800138a: b082 sub sp, #8
|
|
800138c: af00 add r7, sp, #0
|
|
MAGNETO_StatusTypeDef ret = MAGNETO_OK;
|
|
800138e: 2300 movs r3, #0
|
|
8001390: 71fb strb r3, [r7, #7]
|
|
MAGNETO_InitTypeDef LIS3MDL_InitStructureMag;
|
|
|
|
if(Lis3mdlMagDrv.ReadID() != I_AM_LIS3MDL)
|
|
8001392: 4b11 ldr r3, [pc, #68] @ (80013d8 <BSP_MAGNETO_Init+0x50>)
|
|
8001394: 689b ldr r3, [r3, #8]
|
|
8001396: 4798 blx r3
|
|
8001398: 4603 mov r3, r0
|
|
800139a: 2b3d cmp r3, #61 @ 0x3d
|
|
800139c: d002 beq.n 80013a4 <BSP_MAGNETO_Init+0x1c>
|
|
{
|
|
ret = MAGNETO_ERROR;
|
|
800139e: 2301 movs r3, #1
|
|
80013a0: 71fb strb r3, [r7, #7]
|
|
80013a2: e013 b.n 80013cc <BSP_MAGNETO_Init+0x44>
|
|
}
|
|
else
|
|
{
|
|
/* Initialize the MAGNETO magnetometer driver structure */
|
|
MagnetoDrv = &Lis3mdlMagDrv;
|
|
80013a4: 4b0d ldr r3, [pc, #52] @ (80013dc <BSP_MAGNETO_Init+0x54>)
|
|
80013a6: 4a0c ldr r2, [pc, #48] @ (80013d8 <BSP_MAGNETO_Init+0x50>)
|
|
80013a8: 601a str r2, [r3, #0]
|
|
|
|
/* MEMS configuration ------------------------------------------------------*/
|
|
/* Fill the MAGNETO magnetometer structure */
|
|
LIS3MDL_InitStructureMag.Register1 = LIS3MDL_MAG_TEMPSENSOR_DISABLE | LIS3MDL_MAG_OM_XY_HIGH | LIS3MDL_MAG_ODR_40_HZ;
|
|
80013aa: 2358 movs r3, #88 @ 0x58
|
|
80013ac: 703b strb r3, [r7, #0]
|
|
LIS3MDL_InitStructureMag.Register2 = LIS3MDL_MAG_FS_4_GA | LIS3MDL_MAG_REBOOT_DEFAULT | LIS3MDL_MAG_SOFT_RESET_DEFAULT;
|
|
80013ae: 2300 movs r3, #0
|
|
80013b0: 707b strb r3, [r7, #1]
|
|
LIS3MDL_InitStructureMag.Register3 = LIS3MDL_MAG_CONFIG_NORMAL_MODE | LIS3MDL_MAG_CONTINUOUS_MODE;
|
|
80013b2: 2300 movs r3, #0
|
|
80013b4: 70bb strb r3, [r7, #2]
|
|
LIS3MDL_InitStructureMag.Register4 = LIS3MDL_MAG_OM_Z_HIGH | LIS3MDL_MAG_BLE_LSB;
|
|
80013b6: 2308 movs r3, #8
|
|
80013b8: 70fb strb r3, [r7, #3]
|
|
LIS3MDL_InitStructureMag.Register5 = LIS3MDL_MAG_BDU_MSBLSB;
|
|
80013ba: 2340 movs r3, #64 @ 0x40
|
|
80013bc: 713b strb r3, [r7, #4]
|
|
/* Configure the MAGNETO magnetometer main parameters */
|
|
MagnetoDrv->Init(LIS3MDL_InitStructureMag);
|
|
80013be: 4b07 ldr r3, [pc, #28] @ (80013dc <BSP_MAGNETO_Init+0x54>)
|
|
80013c0: 681b ldr r3, [r3, #0]
|
|
80013c2: 681b ldr r3, [r3, #0]
|
|
80013c4: 463a mov r2, r7
|
|
80013c6: e892 0003 ldmia.w r2, {r0, r1}
|
|
80013ca: 4798 blx r3
|
|
}
|
|
|
|
return ret;
|
|
80013cc: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
80013ce: 4618 mov r0, r3
|
|
80013d0: 3708 adds r7, #8
|
|
80013d2: 46bd mov sp, r7
|
|
80013d4: bd80 pop {r7, pc}
|
|
80013d6: bf00 nop
|
|
80013d8: 2000001c .word 0x2000001c
|
|
80013dc: 20000314 .word 0x20000314
|
|
|
|
080013e0 <BSP_MAGNETO_DeInit>:
|
|
|
|
/**
|
|
* @brief DeInitialize the MAGNETO.
|
|
*/
|
|
void BSP_MAGNETO_DeInit(void)
|
|
{
|
|
80013e0: b580 push {r7, lr}
|
|
80013e2: af00 add r7, sp, #0
|
|
/* DeInitialize the magnetometer IO interfaces */
|
|
if(MagnetoDrv != NULL)
|
|
80013e4: 4b07 ldr r3, [pc, #28] @ (8001404 <BSP_MAGNETO_DeInit+0x24>)
|
|
80013e6: 681b ldr r3, [r3, #0]
|
|
80013e8: 2b00 cmp r3, #0
|
|
80013ea: d008 beq.n 80013fe <BSP_MAGNETO_DeInit+0x1e>
|
|
{
|
|
if(MagnetoDrv->DeInit != NULL)
|
|
80013ec: 4b05 ldr r3, [pc, #20] @ (8001404 <BSP_MAGNETO_DeInit+0x24>)
|
|
80013ee: 681b ldr r3, [r3, #0]
|
|
80013f0: 685b ldr r3, [r3, #4]
|
|
80013f2: 2b00 cmp r3, #0
|
|
80013f4: d003 beq.n 80013fe <BSP_MAGNETO_DeInit+0x1e>
|
|
{
|
|
MagnetoDrv->DeInit();
|
|
80013f6: 4b03 ldr r3, [pc, #12] @ (8001404 <BSP_MAGNETO_DeInit+0x24>)
|
|
80013f8: 681b ldr r3, [r3, #0]
|
|
80013fa: 685b ldr r3, [r3, #4]
|
|
80013fc: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
80013fe: bf00 nop
|
|
8001400: bd80 pop {r7, pc}
|
|
8001402: bf00 nop
|
|
8001404: 20000314 .word 0x20000314
|
|
|
|
08001408 <BSP_MAGNETO_GetXYZ>:
|
|
* @brief Get XYZ magnetometer values.
|
|
* @param pDataXYZ Pointer on 3 magnetometer values table with
|
|
* pDataXYZ[0] = X axis, pDataXYZ[1] = Y axis, pDataXYZ[2] = Z axis
|
|
*/
|
|
void BSP_MAGNETO_GetXYZ(int16_t *pDataXYZ)
|
|
{
|
|
8001408: b580 push {r7, lr}
|
|
800140a: b082 sub sp, #8
|
|
800140c: af00 add r7, sp, #0
|
|
800140e: 6078 str r0, [r7, #4]
|
|
if(MagnetoDrv != NULL)
|
|
8001410: 4b08 ldr r3, [pc, #32] @ (8001434 <BSP_MAGNETO_GetXYZ+0x2c>)
|
|
8001412: 681b ldr r3, [r3, #0]
|
|
8001414: 2b00 cmp r3, #0
|
|
8001416: d009 beq.n 800142c <BSP_MAGNETO_GetXYZ+0x24>
|
|
{
|
|
if(MagnetoDrv->GetXYZ != NULL)
|
|
8001418: 4b06 ldr r3, [pc, #24] @ (8001434 <BSP_MAGNETO_GetXYZ+0x2c>)
|
|
800141a: 681b ldr r3, [r3, #0]
|
|
800141c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800141e: 2b00 cmp r3, #0
|
|
8001420: d004 beq.n 800142c <BSP_MAGNETO_GetXYZ+0x24>
|
|
{
|
|
MagnetoDrv->GetXYZ(pDataXYZ);
|
|
8001422: 4b04 ldr r3, [pc, #16] @ (8001434 <BSP_MAGNETO_GetXYZ+0x2c>)
|
|
8001424: 681b ldr r3, [r3, #0]
|
|
8001426: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001428: 6878 ldr r0, [r7, #4]
|
|
800142a: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
800142c: bf00 nop
|
|
800142e: 3708 adds r7, #8
|
|
8001430: 46bd mov sp, r7
|
|
8001432: bd80 pop {r7, pc}
|
|
8001434: 20000314 .word 0x20000314
|
|
|
|
08001438 <BSP_PSENSOR_Init>:
|
|
/**
|
|
* @brief Initializes peripherals used by the I2C Pressure Sensor driver.
|
|
* @retval PSENSOR status
|
|
*/
|
|
uint32_t BSP_PSENSOR_Init(void)
|
|
{
|
|
8001438: b580 push {r7, lr}
|
|
800143a: b082 sub sp, #8
|
|
800143c: af00 add r7, sp, #0
|
|
uint32_t ret;
|
|
|
|
if(LPS22HB_P_Drv.ReadID(LPS22HB_I2C_ADDRESS) != LPS22HB_WHO_AM_I_VAL)
|
|
800143e: 4b0c ldr r3, [pc, #48] @ (8001470 <BSP_PSENSOR_Init+0x38>)
|
|
8001440: 685b ldr r3, [r3, #4]
|
|
8001442: 20ba movs r0, #186 @ 0xba
|
|
8001444: 4798 blx r3
|
|
8001446: 4603 mov r3, r0
|
|
8001448: 2bb1 cmp r3, #177 @ 0xb1
|
|
800144a: d002 beq.n 8001452 <BSP_PSENSOR_Init+0x1a>
|
|
{
|
|
ret = PSENSOR_ERROR;
|
|
800144c: 2301 movs r3, #1
|
|
800144e: 607b str r3, [r7, #4]
|
|
8001450: e009 b.n 8001466 <BSP_PSENSOR_Init+0x2e>
|
|
}
|
|
else
|
|
{
|
|
Psensor_drv = &LPS22HB_P_Drv;
|
|
8001452: 4b08 ldr r3, [pc, #32] @ (8001474 <BSP_PSENSOR_Init+0x3c>)
|
|
8001454: 4a06 ldr r2, [pc, #24] @ (8001470 <BSP_PSENSOR_Init+0x38>)
|
|
8001456: 601a str r2, [r3, #0]
|
|
|
|
/* PSENSOR Init */
|
|
Psensor_drv->Init(LPS22HB_I2C_ADDRESS);
|
|
8001458: 4b06 ldr r3, [pc, #24] @ (8001474 <BSP_PSENSOR_Init+0x3c>)
|
|
800145a: 681b ldr r3, [r3, #0]
|
|
800145c: 681b ldr r3, [r3, #0]
|
|
800145e: 20ba movs r0, #186 @ 0xba
|
|
8001460: 4798 blx r3
|
|
ret = PSENSOR_OK;
|
|
8001462: 2300 movs r3, #0
|
|
8001464: 607b str r3, [r7, #4]
|
|
}
|
|
|
|
return ret;
|
|
8001466: 687b ldr r3, [r7, #4]
|
|
}
|
|
8001468: 4618 mov r0, r3
|
|
800146a: 3708 adds r7, #8
|
|
800146c: 46bd mov sp, r7
|
|
800146e: bd80 pop {r7, pc}
|
|
8001470: 20000050 .word 0x20000050
|
|
8001474: 20000318 .word 0x20000318
|
|
|
|
08001478 <BSP_PSENSOR_ReadPressure>:
|
|
/**
|
|
* @brief Read Pressure register of LPS22HB.
|
|
* @retval LPS22HB measured pressure value.
|
|
*/
|
|
float BSP_PSENSOR_ReadPressure(void)
|
|
{
|
|
8001478: b580 push {r7, lr}
|
|
800147a: af00 add r7, sp, #0
|
|
return Psensor_drv->ReadPressure(LPS22HB_I2C_ADDRESS);
|
|
800147c: 4b04 ldr r3, [pc, #16] @ (8001490 <BSP_PSENSOR_ReadPressure+0x18>)
|
|
800147e: 681b ldr r3, [r3, #0]
|
|
8001480: 689b ldr r3, [r3, #8]
|
|
8001482: 20ba movs r0, #186 @ 0xba
|
|
8001484: 4798 blx r3
|
|
8001486: eef0 7a40 vmov.f32 s15, s0
|
|
}
|
|
800148a: eeb0 0a67 vmov.f32 s0, s15
|
|
800148e: bd80 pop {r7, pc}
|
|
8001490: 20000318 .word 0x20000318
|
|
|
|
08001494 <BSP_TSENSOR_Init>:
|
|
/**
|
|
* @brief Initializes peripherals used by the I2C Temperature Sensor driver.
|
|
* @retval TSENSOR status
|
|
*/
|
|
uint32_t BSP_TSENSOR_Init(void)
|
|
{
|
|
8001494: b580 push {r7, lr}
|
|
8001496: b082 sub sp, #8
|
|
8001498: af00 add r7, sp, #0
|
|
uint8_t ret = TSENSOR_ERROR;
|
|
800149a: 2301 movs r3, #1
|
|
800149c: 71fb strb r3, [r7, #7]
|
|
|
|
#ifdef USE_LPS22HB_TEMP
|
|
tsensor_drv = &LPS22HB_T_Drv;
|
|
#else /* USE_HTS221_TEMP */
|
|
tsensor_drv = &HTS221_T_Drv;
|
|
800149e: 4b09 ldr r3, [pc, #36] @ (80014c4 <BSP_TSENSOR_Init+0x30>)
|
|
80014a0: 4a09 ldr r2, [pc, #36] @ (80014c8 <BSP_TSENSOR_Init+0x34>)
|
|
80014a2: 601a str r2, [r3, #0]
|
|
#endif
|
|
|
|
/* Low level init */
|
|
SENSOR_IO_Init();
|
|
80014a4: f7ff fe06 bl 80010b4 <SENSOR_IO_Init>
|
|
|
|
/* TSENSOR Init */
|
|
tsensor_drv->Init(TSENSOR_I2C_ADDRESS, NULL);
|
|
80014a8: 4b06 ldr r3, [pc, #24] @ (80014c4 <BSP_TSENSOR_Init+0x30>)
|
|
80014aa: 681b ldr r3, [r3, #0]
|
|
80014ac: 681b ldr r3, [r3, #0]
|
|
80014ae: 2100 movs r1, #0
|
|
80014b0: 20be movs r0, #190 @ 0xbe
|
|
80014b2: 4798 blx r3
|
|
|
|
ret = TSENSOR_OK;
|
|
80014b4: 2300 movs r3, #0
|
|
80014b6: 71fb strb r3, [r7, #7]
|
|
|
|
return ret;
|
|
80014b8: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
80014ba: 4618 mov r0, r3
|
|
80014bc: 3708 adds r7, #8
|
|
80014be: 46bd mov sp, r7
|
|
80014c0: bd80 pop {r7, pc}
|
|
80014c2: bf00 nop
|
|
80014c4: 2000031c .word 0x2000031c
|
|
80014c8: 2000000c .word 0x2000000c
|
|
|
|
080014cc <BSP_TSENSOR_ReadTemp>:
|
|
/**
|
|
* @brief Read Temperature register of TS751.
|
|
* @retval STTS751 measured temperature value.
|
|
*/
|
|
float BSP_TSENSOR_ReadTemp(void)
|
|
{
|
|
80014cc: b580 push {r7, lr}
|
|
80014ce: af00 add r7, sp, #0
|
|
return tsensor_drv->ReadTemp(TSENSOR_I2C_ADDRESS);
|
|
80014d0: 4b04 ldr r3, [pc, #16] @ (80014e4 <BSP_TSENSOR_ReadTemp+0x18>)
|
|
80014d2: 681b ldr r3, [r3, #0]
|
|
80014d4: 68db ldr r3, [r3, #12]
|
|
80014d6: 20be movs r0, #190 @ 0xbe
|
|
80014d8: 4798 blx r3
|
|
80014da: eef0 7a40 vmov.f32 s15, s0
|
|
}
|
|
80014de: eeb0 0a67 vmov.f32 s0, s15
|
|
80014e2: bd80 pop {r7, pc}
|
|
80014e4: 2000031c .word 0x2000031c
|
|
|
|
080014e8 <HTS221_H_Init>:
|
|
*/
|
|
/**
|
|
* @brief Set HTS221 humidity sensor Initialization.
|
|
*/
|
|
void HTS221_H_Init(uint16_t DeviceAddr)
|
|
{
|
|
80014e8: b580 push {r7, lr}
|
|
80014ea: b084 sub sp, #16
|
|
80014ec: af00 add r7, sp, #0
|
|
80014ee: 4603 mov r3, r0
|
|
80014f0: 80fb strh r3, [r7, #6]
|
|
uint8_t tmp;
|
|
|
|
/* Read CTRL_REG1 */
|
|
tmp = SENSOR_IO_Read(DeviceAddr, HTS221_CTRL_REG1);
|
|
80014f2: 88fb ldrh r3, [r7, #6]
|
|
80014f4: b2db uxtb r3, r3
|
|
80014f6: 2120 movs r1, #32
|
|
80014f8: 4618 mov r0, r3
|
|
80014fa: f7ff fdff bl 80010fc <SENSOR_IO_Read>
|
|
80014fe: 4603 mov r3, r0
|
|
8001500: 73fb strb r3, [r7, #15]
|
|
|
|
/* Enable BDU */
|
|
tmp &= ~HTS221_BDU_MASK;
|
|
8001502: 7bfb ldrb r3, [r7, #15]
|
|
8001504: f023 0304 bic.w r3, r3, #4
|
|
8001508: 73fb strb r3, [r7, #15]
|
|
tmp |= (1 << HTS221_BDU_BIT);
|
|
800150a: 7bfb ldrb r3, [r7, #15]
|
|
800150c: f043 0304 orr.w r3, r3, #4
|
|
8001510: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set default ODR */
|
|
tmp &= ~HTS221_ODR_MASK;
|
|
8001512: 7bfb ldrb r3, [r7, #15]
|
|
8001514: f023 0303 bic.w r3, r3, #3
|
|
8001518: 73fb strb r3, [r7, #15]
|
|
tmp |= (uint8_t)0x01; /* Set ODR to 1Hz */
|
|
800151a: 7bfb ldrb r3, [r7, #15]
|
|
800151c: f043 0301 orr.w r3, r3, #1
|
|
8001520: 73fb strb r3, [r7, #15]
|
|
|
|
/* Activate the device */
|
|
tmp |= HTS221_PD_MASK;
|
|
8001522: 7bfb ldrb r3, [r7, #15]
|
|
8001524: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8001528: 73fb strb r3, [r7, #15]
|
|
|
|
/* Apply settings to CTRL_REG1 */
|
|
SENSOR_IO_Write(DeviceAddr, HTS221_CTRL_REG1, tmp);
|
|
800152a: 88fb ldrh r3, [r7, #6]
|
|
800152c: b2db uxtb r3, r3
|
|
800152e: 7bfa ldrb r2, [r7, #15]
|
|
8001530: 2120 movs r1, #32
|
|
8001532: 4618 mov r0, r3
|
|
8001534: f7ff fdc8 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001538: bf00 nop
|
|
800153a: 3710 adds r7, #16
|
|
800153c: 46bd mov sp, r7
|
|
800153e: bd80 pop {r7, pc}
|
|
|
|
08001540 <HTS221_H_ReadID>:
|
|
/**
|
|
* @brief Read HTS221 ID.
|
|
* @retval ID
|
|
*/
|
|
uint8_t HTS221_H_ReadID(uint16_t DeviceAddr)
|
|
{
|
|
8001540: b580 push {r7, lr}
|
|
8001542: b084 sub sp, #16
|
|
8001544: af00 add r7, sp, #0
|
|
8001546: 4603 mov r3, r0
|
|
8001548: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
800154a: 2300 movs r3, #0
|
|
800154c: 73fb strb r3, [r7, #15]
|
|
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
800154e: f7ff fdb1 bl 80010b4 <SENSOR_IO_Init>
|
|
|
|
/* Read value at Who am I register address */
|
|
ctrl = SENSOR_IO_Read(DeviceAddr, HTS221_WHO_AM_I_REG);
|
|
8001552: 88fb ldrh r3, [r7, #6]
|
|
8001554: b2db uxtb r3, r3
|
|
8001556: 210f movs r1, #15
|
|
8001558: 4618 mov r0, r3
|
|
800155a: f7ff fdcf bl 80010fc <SENSOR_IO_Read>
|
|
800155e: 4603 mov r3, r0
|
|
8001560: 73fb strb r3, [r7, #15]
|
|
|
|
return ctrl;
|
|
8001562: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001564: 4618 mov r0, r3
|
|
8001566: 3710 adds r7, #16
|
|
8001568: 46bd mov sp, r7
|
|
800156a: bd80 pop {r7, pc}
|
|
|
|
0800156c <HTS221_H_ReadHumidity>:
|
|
/**
|
|
* @brief Read humidity value of HTS221
|
|
* @retval humidity value;
|
|
*/
|
|
float HTS221_H_ReadHumidity(uint16_t DeviceAddr)
|
|
{
|
|
800156c: b580 push {r7, lr}
|
|
800156e: b088 sub sp, #32
|
|
8001570: af00 add r7, sp, #0
|
|
8001572: 4603 mov r3, r0
|
|
8001574: 80fb strh r3, [r7, #6]
|
|
int16_t H0_T0_out, H1_T0_out, H_T_out;
|
|
int16_t H0_rh, H1_rh;
|
|
uint8_t buffer[2];
|
|
float tmp_f;
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_H0_RH_X2 | 0x80), buffer, 2);
|
|
8001576: 88fb ldrh r3, [r7, #6]
|
|
8001578: b2d8 uxtb r0, r3
|
|
800157a: f107 020c add.w r2, r7, #12
|
|
800157e: 2302 movs r3, #2
|
|
8001580: 21b0 movs r1, #176 @ 0xb0
|
|
8001582: f7ff fdd9 bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
H0_rh = buffer[0] >> 1;
|
|
8001586: 7b3b ldrb r3, [r7, #12]
|
|
8001588: 085b lsrs r3, r3, #1
|
|
800158a: b2db uxtb r3, r3
|
|
800158c: 83fb strh r3, [r7, #30]
|
|
H1_rh = buffer[1] >> 1;
|
|
800158e: 7b7b ldrb r3, [r7, #13]
|
|
8001590: 085b lsrs r3, r3, #1
|
|
8001592: b2db uxtb r3, r3
|
|
8001594: 83bb strh r3, [r7, #28]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_H0_T0_OUT_L | 0x80), buffer, 2);
|
|
8001596: 88fb ldrh r3, [r7, #6]
|
|
8001598: b2d8 uxtb r0, r3
|
|
800159a: f107 020c add.w r2, r7, #12
|
|
800159e: 2302 movs r3, #2
|
|
80015a0: 21b6 movs r1, #182 @ 0xb6
|
|
80015a2: f7ff fdc9 bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
H0_T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
80015a6: 7b7b ldrb r3, [r7, #13]
|
|
80015a8: b21b sxth r3, r3
|
|
80015aa: 021b lsls r3, r3, #8
|
|
80015ac: b21a sxth r2, r3
|
|
80015ae: 7b3b ldrb r3, [r7, #12]
|
|
80015b0: b21b sxth r3, r3
|
|
80015b2: 4313 orrs r3, r2
|
|
80015b4: 837b strh r3, [r7, #26]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_H1_T0_OUT_L | 0x80), buffer, 2);
|
|
80015b6: 88fb ldrh r3, [r7, #6]
|
|
80015b8: b2d8 uxtb r0, r3
|
|
80015ba: f107 020c add.w r2, r7, #12
|
|
80015be: 2302 movs r3, #2
|
|
80015c0: 21ba movs r1, #186 @ 0xba
|
|
80015c2: f7ff fdb9 bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
H1_T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
80015c6: 7b7b ldrb r3, [r7, #13]
|
|
80015c8: b21b sxth r3, r3
|
|
80015ca: 021b lsls r3, r3, #8
|
|
80015cc: b21a sxth r2, r3
|
|
80015ce: 7b3b ldrb r3, [r7, #12]
|
|
80015d0: b21b sxth r3, r3
|
|
80015d2: 4313 orrs r3, r2
|
|
80015d4: 833b strh r3, [r7, #24]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_HR_OUT_L_REG | 0x80), buffer, 2);
|
|
80015d6: 88fb ldrh r3, [r7, #6]
|
|
80015d8: b2d8 uxtb r0, r3
|
|
80015da: f107 020c add.w r2, r7, #12
|
|
80015de: 2302 movs r3, #2
|
|
80015e0: 21a8 movs r1, #168 @ 0xa8
|
|
80015e2: f7ff fda9 bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
H_T_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
80015e6: 7b7b ldrb r3, [r7, #13]
|
|
80015e8: b21b sxth r3, r3
|
|
80015ea: 021b lsls r3, r3, #8
|
|
80015ec: b21a sxth r2, r3
|
|
80015ee: 7b3b ldrb r3, [r7, #12]
|
|
80015f0: b21b sxth r3, r3
|
|
80015f2: 4313 orrs r3, r2
|
|
80015f4: 82fb strh r3, [r7, #22]
|
|
|
|
tmp_f = (float)(H_T_out - H0_T0_out) * (float)(H1_rh - H0_rh) / (float)(H1_T0_out - H0_T0_out) + H0_rh;
|
|
80015f6: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80015fa: f9b7 301a ldrsh.w r3, [r7, #26]
|
|
80015fe: 1ad3 subs r3, r2, r3
|
|
8001600: ee07 3a90 vmov s15, r3
|
|
8001604: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8001608: f9b7 201c ldrsh.w r2, [r7, #28]
|
|
800160c: f9b7 301e ldrsh.w r3, [r7, #30]
|
|
8001610: 1ad3 subs r3, r2, r3
|
|
8001612: ee07 3a90 vmov s15, r3
|
|
8001616: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
800161a: ee67 6a27 vmul.f32 s13, s14, s15
|
|
800161e: f9b7 2018 ldrsh.w r2, [r7, #24]
|
|
8001622: f9b7 301a ldrsh.w r3, [r7, #26]
|
|
8001626: 1ad3 subs r3, r2, r3
|
|
8001628: ee07 3a90 vmov s15, r3
|
|
800162c: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001630: ee86 7aa7 vdiv.f32 s14, s13, s15
|
|
8001634: f9b7 301e ldrsh.w r3, [r7, #30]
|
|
8001638: ee07 3a90 vmov s15, r3
|
|
800163c: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001640: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001644: edc7 7a04 vstr s15, [r7, #16]
|
|
tmp_f *= 10.0f;
|
|
8001648: edd7 7a04 vldr s15, [r7, #16]
|
|
800164c: eeb2 7a04 vmov.f32 s14, #36 @ 0x41200000 10.0
|
|
8001650: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001654: edc7 7a04 vstr s15, [r7, #16]
|
|
|
|
tmp_f = ( tmp_f > 1000.0f ) ? 1000.0f
|
|
: ( tmp_f < 0.0f ) ? 0.0f
|
|
8001658: edd7 7a04 vldr s15, [r7, #16]
|
|
800165c: ed9f 7a10 vldr s14, [pc, #64] @ 80016a0 <HTS221_H_ReadHumidity+0x134>
|
|
8001660: eef4 7ac7 vcmpe.f32 s15, s14
|
|
8001664: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8001668: dd01 ble.n 800166e <HTS221_H_ReadHumidity+0x102>
|
|
800166a: 4b0e ldr r3, [pc, #56] @ (80016a4 <HTS221_H_ReadHumidity+0x138>)
|
|
800166c: e00a b.n 8001684 <HTS221_H_ReadHumidity+0x118>
|
|
: tmp_f;
|
|
800166e: edd7 7a04 vldr s15, [r7, #16]
|
|
8001672: eef5 7ac0 vcmpe.f32 s15, #0.0
|
|
8001676: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
800167a: d502 bpl.n 8001682 <HTS221_H_ReadHumidity+0x116>
|
|
800167c: f04f 0300 mov.w r3, #0
|
|
8001680: e000 b.n 8001684 <HTS221_H_ReadHumidity+0x118>
|
|
8001682: 693b ldr r3, [r7, #16]
|
|
tmp_f = ( tmp_f > 1000.0f ) ? 1000.0f
|
|
8001684: 613b str r3, [r7, #16]
|
|
|
|
return (tmp_f / 10.0f);
|
|
8001686: edd7 7a04 vldr s15, [r7, #16]
|
|
800168a: eeb2 7a04 vmov.f32 s14, #36 @ 0x41200000 10.0
|
|
800168e: eec7 6a87 vdiv.f32 s13, s15, s14
|
|
8001692: eef0 7a66 vmov.f32 s15, s13
|
|
}
|
|
8001696: eeb0 0a67 vmov.f32 s0, s15
|
|
800169a: 3720 adds r7, #32
|
|
800169c: 46bd mov sp, r7
|
|
800169e: bd80 pop {r7, pc}
|
|
80016a0: 447a0000 .word 0x447a0000
|
|
80016a4: 447a0000 .word 0x447a0000
|
|
|
|
080016a8 <HTS221_T_Init>:
|
|
* @param DeviceAddr: I2C device address
|
|
* @param InitStruct: pointer to a TSENSOR_InitTypeDef structure
|
|
* that contains the configuration setting for the HTS221.
|
|
*/
|
|
void HTS221_T_Init(uint16_t DeviceAddr, TSENSOR_InitTypeDef *pInitStruct)
|
|
{
|
|
80016a8: b580 push {r7, lr}
|
|
80016aa: b084 sub sp, #16
|
|
80016ac: af00 add r7, sp, #0
|
|
80016ae: 4603 mov r3, r0
|
|
80016b0: 6039 str r1, [r7, #0]
|
|
80016b2: 80fb strh r3, [r7, #6]
|
|
uint8_t tmp;
|
|
|
|
/* Read CTRL_REG1 */
|
|
tmp = SENSOR_IO_Read(DeviceAddr, HTS221_CTRL_REG1);
|
|
80016b4: 88fb ldrh r3, [r7, #6]
|
|
80016b6: b2db uxtb r3, r3
|
|
80016b8: 2120 movs r1, #32
|
|
80016ba: 4618 mov r0, r3
|
|
80016bc: f7ff fd1e bl 80010fc <SENSOR_IO_Read>
|
|
80016c0: 4603 mov r3, r0
|
|
80016c2: 73fb strb r3, [r7, #15]
|
|
|
|
/* Enable BDU */
|
|
tmp &= ~HTS221_BDU_MASK;
|
|
80016c4: 7bfb ldrb r3, [r7, #15]
|
|
80016c6: f023 0304 bic.w r3, r3, #4
|
|
80016ca: 73fb strb r3, [r7, #15]
|
|
tmp |= (1 << HTS221_BDU_BIT);
|
|
80016cc: 7bfb ldrb r3, [r7, #15]
|
|
80016ce: f043 0304 orr.w r3, r3, #4
|
|
80016d2: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set default ODR */
|
|
tmp &= ~HTS221_ODR_MASK;
|
|
80016d4: 7bfb ldrb r3, [r7, #15]
|
|
80016d6: f023 0303 bic.w r3, r3, #3
|
|
80016da: 73fb strb r3, [r7, #15]
|
|
tmp |= (uint8_t)0x01; /* Set ODR to 1Hz */
|
|
80016dc: 7bfb ldrb r3, [r7, #15]
|
|
80016de: f043 0301 orr.w r3, r3, #1
|
|
80016e2: 73fb strb r3, [r7, #15]
|
|
|
|
/* Activate the device */
|
|
tmp |= HTS221_PD_MASK;
|
|
80016e4: 7bfb ldrb r3, [r7, #15]
|
|
80016e6: f063 037f orn r3, r3, #127 @ 0x7f
|
|
80016ea: 73fb strb r3, [r7, #15]
|
|
|
|
/* Apply settings to CTRL_REG1 */
|
|
SENSOR_IO_Write(DeviceAddr, HTS221_CTRL_REG1, tmp);
|
|
80016ec: 88fb ldrh r3, [r7, #6]
|
|
80016ee: b2db uxtb r3, r3
|
|
80016f0: 7bfa ldrb r2, [r7, #15]
|
|
80016f2: 2120 movs r1, #32
|
|
80016f4: 4618 mov r0, r3
|
|
80016f6: f7ff fce7 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
80016fa: bf00 nop
|
|
80016fc: 3710 adds r7, #16
|
|
80016fe: 46bd mov sp, r7
|
|
8001700: bd80 pop {r7, pc}
|
|
|
|
08001702 <HTS221_T_ReadTemp>:
|
|
* @brief Read temperature value of HTS221
|
|
* @param DeviceAddr: I2C device address
|
|
* @retval temperature value
|
|
*/
|
|
float HTS221_T_ReadTemp(uint16_t DeviceAddr)
|
|
{
|
|
8001702: b580 push {r7, lr}
|
|
8001704: b088 sub sp, #32
|
|
8001706: af00 add r7, sp, #0
|
|
8001708: 4603 mov r3, r0
|
|
800170a: 80fb strh r3, [r7, #6]
|
|
int16_t T0_out, T1_out, T_out, T0_degC_x8_u16, T1_degC_x8_u16;
|
|
int16_t T0_degC, T1_degC;
|
|
uint8_t buffer[4], tmp;
|
|
float tmp_f;
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_T0_DEGC_X8 | 0x80), buffer, 2);
|
|
800170c: 88fb ldrh r3, [r7, #6]
|
|
800170e: b2d8 uxtb r0, r3
|
|
8001710: f107 0208 add.w r2, r7, #8
|
|
8001714: 2302 movs r3, #2
|
|
8001716: 21b2 movs r1, #178 @ 0xb2
|
|
8001718: f7ff fd0e bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
tmp = SENSOR_IO_Read(DeviceAddr, HTS221_T0_T1_DEGC_H2);
|
|
800171c: 88fb ldrh r3, [r7, #6]
|
|
800171e: b2db uxtb r3, r3
|
|
8001720: 2135 movs r1, #53 @ 0x35
|
|
8001722: 4618 mov r0, r3
|
|
8001724: f7ff fcea bl 80010fc <SENSOR_IO_Read>
|
|
8001728: 4603 mov r3, r0
|
|
800172a: 77fb strb r3, [r7, #31]
|
|
|
|
T0_degC_x8_u16 = (((uint16_t)(tmp & 0x03)) << 8) | ((uint16_t)buffer[0]);
|
|
800172c: 7ffb ldrb r3, [r7, #31]
|
|
800172e: b21b sxth r3, r3
|
|
8001730: 021b lsls r3, r3, #8
|
|
8001732: b21b sxth r3, r3
|
|
8001734: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8001738: b21a sxth r2, r3
|
|
800173a: 7a3b ldrb r3, [r7, #8]
|
|
800173c: b21b sxth r3, r3
|
|
800173e: 4313 orrs r3, r2
|
|
8001740: 83bb strh r3, [r7, #28]
|
|
T1_degC_x8_u16 = (((uint16_t)(tmp & 0x0C)) << 6) | ((uint16_t)buffer[1]);
|
|
8001742: 7ffb ldrb r3, [r7, #31]
|
|
8001744: b21b sxth r3, r3
|
|
8001746: 019b lsls r3, r3, #6
|
|
8001748: b21b sxth r3, r3
|
|
800174a: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800174e: b21a sxth r2, r3
|
|
8001750: 7a7b ldrb r3, [r7, #9]
|
|
8001752: b21b sxth r3, r3
|
|
8001754: 4313 orrs r3, r2
|
|
8001756: 837b strh r3, [r7, #26]
|
|
T0_degC = T0_degC_x8_u16 >> 3;
|
|
8001758: f9b7 301c ldrsh.w r3, [r7, #28]
|
|
800175c: 10db asrs r3, r3, #3
|
|
800175e: 833b strh r3, [r7, #24]
|
|
T1_degC = T1_degC_x8_u16 >> 3;
|
|
8001760: f9b7 301a ldrsh.w r3, [r7, #26]
|
|
8001764: 10db asrs r3, r3, #3
|
|
8001766: 82fb strh r3, [r7, #22]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_T0_OUT_L | 0x80), buffer, 4);
|
|
8001768: 88fb ldrh r3, [r7, #6]
|
|
800176a: b2d8 uxtb r0, r3
|
|
800176c: f107 0208 add.w r2, r7, #8
|
|
8001770: 2304 movs r3, #4
|
|
8001772: 21bc movs r1, #188 @ 0xbc
|
|
8001774: f7ff fce0 bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
8001778: 7a7b ldrb r3, [r7, #9]
|
|
800177a: b21b sxth r3, r3
|
|
800177c: 021b lsls r3, r3, #8
|
|
800177e: b21a sxth r2, r3
|
|
8001780: 7a3b ldrb r3, [r7, #8]
|
|
8001782: b21b sxth r3, r3
|
|
8001784: 4313 orrs r3, r2
|
|
8001786: 82bb strh r3, [r7, #20]
|
|
T1_out = (((uint16_t)buffer[3]) << 8) | (uint16_t)buffer[2];
|
|
8001788: 7afb ldrb r3, [r7, #11]
|
|
800178a: b21b sxth r3, r3
|
|
800178c: 021b lsls r3, r3, #8
|
|
800178e: b21a sxth r2, r3
|
|
8001790: 7abb ldrb r3, [r7, #10]
|
|
8001792: b21b sxth r3, r3
|
|
8001794: 4313 orrs r3, r2
|
|
8001796: 827b strh r3, [r7, #18]
|
|
|
|
SENSOR_IO_ReadMultiple(DeviceAddr, (HTS221_TEMP_OUT_L_REG | 0x80), buffer, 2);
|
|
8001798: 88fb ldrh r3, [r7, #6]
|
|
800179a: b2d8 uxtb r0, r3
|
|
800179c: f107 0208 add.w r2, r7, #8
|
|
80017a0: 2302 movs r3, #2
|
|
80017a2: 21aa movs r1, #170 @ 0xaa
|
|
80017a4: f7ff fcc8 bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
T_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0];
|
|
80017a8: 7a7b ldrb r3, [r7, #9]
|
|
80017aa: b21b sxth r3, r3
|
|
80017ac: 021b lsls r3, r3, #8
|
|
80017ae: b21a sxth r2, r3
|
|
80017b0: 7a3b ldrb r3, [r7, #8]
|
|
80017b2: b21b sxth r3, r3
|
|
80017b4: 4313 orrs r3, r2
|
|
80017b6: 823b strh r3, [r7, #16]
|
|
|
|
tmp_f = (float)(T_out - T0_out) * (float)(T1_degC - T0_degC) / (float)(T1_out - T0_out) + T0_degC;
|
|
80017b8: f9b7 2010 ldrsh.w r2, [r7, #16]
|
|
80017bc: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
80017c0: 1ad3 subs r3, r2, r3
|
|
80017c2: ee07 3a90 vmov s15, r3
|
|
80017c6: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80017ca: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
80017ce: f9b7 3018 ldrsh.w r3, [r7, #24]
|
|
80017d2: 1ad3 subs r3, r2, r3
|
|
80017d4: ee07 3a90 vmov s15, r3
|
|
80017d8: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80017dc: ee67 6a27 vmul.f32 s13, s14, s15
|
|
80017e0: f9b7 2012 ldrsh.w r2, [r7, #18]
|
|
80017e4: f9b7 3014 ldrsh.w r3, [r7, #20]
|
|
80017e8: 1ad3 subs r3, r2, r3
|
|
80017ea: ee07 3a90 vmov s15, r3
|
|
80017ee: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80017f2: ee86 7aa7 vdiv.f32 s14, s13, s15
|
|
80017f6: f9b7 3018 ldrsh.w r3, [r7, #24]
|
|
80017fa: ee07 3a90 vmov s15, r3
|
|
80017fe: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001802: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001806: edc7 7a03 vstr s15, [r7, #12]
|
|
|
|
return tmp_f;
|
|
800180a: 68fb ldr r3, [r7, #12]
|
|
800180c: ee07 3a90 vmov s15, r3
|
|
}
|
|
8001810: eeb0 0a67 vmov.f32 s0, s15
|
|
8001814: 3720 adds r7, #32
|
|
8001816: 46bd mov sp, r7
|
|
8001818: bd80 pop {r7, pc}
|
|
|
|
0800181a <LIS3MDL_MagInit>:
|
|
* @brief Set LIS3MDL Magnetometer Initialization.
|
|
* @param LIS3MDL_InitStruct: pointer to a LIS3MDL_MagInitTypeDef structure
|
|
* that contains the configuration setting for the LIS3MDL.
|
|
*/
|
|
void LIS3MDL_MagInit(MAGNETO_InitTypeDef LIS3MDL_InitStruct)
|
|
{
|
|
800181a: b580 push {r7, lr}
|
|
800181c: b082 sub sp, #8
|
|
800181e: af00 add r7, sp, #0
|
|
8001820: 463b mov r3, r7
|
|
8001822: e883 0003 stmia.w r3, {r0, r1}
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG1, LIS3MDL_InitStruct.Register1);
|
|
8001826: 783b ldrb r3, [r7, #0]
|
|
8001828: 461a mov r2, r3
|
|
800182a: 2120 movs r1, #32
|
|
800182c: 203c movs r0, #60 @ 0x3c
|
|
800182e: f7ff fc4b bl 80010c8 <SENSOR_IO_Write>
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG2, LIS3MDL_InitStruct.Register2);
|
|
8001832: 787b ldrb r3, [r7, #1]
|
|
8001834: 461a mov r2, r3
|
|
8001836: 2121 movs r1, #33 @ 0x21
|
|
8001838: 203c movs r0, #60 @ 0x3c
|
|
800183a: f7ff fc45 bl 80010c8 <SENSOR_IO_Write>
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3, LIS3MDL_InitStruct.Register3);
|
|
800183e: 78bb ldrb r3, [r7, #2]
|
|
8001840: 461a mov r2, r3
|
|
8001842: 2122 movs r1, #34 @ 0x22
|
|
8001844: 203c movs r0, #60 @ 0x3c
|
|
8001846: f7ff fc3f bl 80010c8 <SENSOR_IO_Write>
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG4, LIS3MDL_InitStruct.Register4);
|
|
800184a: 78fb ldrb r3, [r7, #3]
|
|
800184c: 461a mov r2, r3
|
|
800184e: 2123 movs r1, #35 @ 0x23
|
|
8001850: 203c movs r0, #60 @ 0x3c
|
|
8001852: f7ff fc39 bl 80010c8 <SENSOR_IO_Write>
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG5, LIS3MDL_InitStruct.Register5);
|
|
8001856: 793b ldrb r3, [r7, #4]
|
|
8001858: 461a mov r2, r3
|
|
800185a: 2124 movs r1, #36 @ 0x24
|
|
800185c: 203c movs r0, #60 @ 0x3c
|
|
800185e: f7ff fc33 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001862: bf00 nop
|
|
8001864: 3708 adds r7, #8
|
|
8001866: 46bd mov sp, r7
|
|
8001868: bd80 pop {r7, pc}
|
|
|
|
0800186a <LIS3MDL_MagDeInit>:
|
|
|
|
/**
|
|
* @brief LIS3MDL Magnetometer De-initialization.
|
|
*/
|
|
void LIS3MDL_MagDeInit(void)
|
|
{
|
|
800186a: b580 push {r7, lr}
|
|
800186c: b082 sub sp, #8
|
|
800186e: af00 add r7, sp, #0
|
|
uint8_t ctrl = 0x00;
|
|
8001870: 2300 movs r3, #0
|
|
8001872: 71fb strb r3, [r7, #7]
|
|
|
|
/* Read control register 1 value */
|
|
ctrl = SENSOR_IO_Read(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3);
|
|
8001874: 2122 movs r1, #34 @ 0x22
|
|
8001876: 203c movs r0, #60 @ 0x3c
|
|
8001878: f7ff fc40 bl 80010fc <SENSOR_IO_Read>
|
|
800187c: 4603 mov r3, r0
|
|
800187e: 71fb strb r3, [r7, #7]
|
|
|
|
/* Clear Selection Mode bits */
|
|
ctrl &= ~(LIS3MDL_MAG_SELECTION_MODE);
|
|
8001880: 79fb ldrb r3, [r7, #7]
|
|
8001882: f023 0303 bic.w r3, r3, #3
|
|
8001886: 71fb strb r3, [r7, #7]
|
|
|
|
/* Set Power down */
|
|
ctrl |= LIS3MDL_MAG_POWERDOWN2_MODE;
|
|
8001888: 79fb ldrb r3, [r7, #7]
|
|
800188a: f043 0303 orr.w r3, r3, #3
|
|
800188e: 71fb strb r3, [r7, #7]
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3, ctrl);
|
|
8001890: 79fb ldrb r3, [r7, #7]
|
|
8001892: 461a mov r2, r3
|
|
8001894: 2122 movs r1, #34 @ 0x22
|
|
8001896: 203c movs r0, #60 @ 0x3c
|
|
8001898: f7ff fc16 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
800189c: bf00 nop
|
|
800189e: 3708 adds r7, #8
|
|
80018a0: 46bd mov sp, r7
|
|
80018a2: bd80 pop {r7, pc}
|
|
|
|
080018a4 <LIS3MDL_MagReadID>:
|
|
/**
|
|
* @brief Read LIS3MDL ID.
|
|
* @retval ID
|
|
*/
|
|
uint8_t LIS3MDL_MagReadID(void)
|
|
{
|
|
80018a4: b580 push {r7, lr}
|
|
80018a6: af00 add r7, sp, #0
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
80018a8: f7ff fc04 bl 80010b4 <SENSOR_IO_Init>
|
|
/* Read value at Who am I register address */
|
|
return (SENSOR_IO_Read(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_WHO_AM_I_REG));
|
|
80018ac: 210f movs r1, #15
|
|
80018ae: 203c movs r0, #60 @ 0x3c
|
|
80018b0: f7ff fc24 bl 80010fc <SENSOR_IO_Read>
|
|
80018b4: 4603 mov r3, r0
|
|
}
|
|
80018b6: 4618 mov r0, r3
|
|
80018b8: bd80 pop {r7, pc}
|
|
|
|
080018ba <LIS3MDL_MagLowPower>:
|
|
/**
|
|
* @brief Set/Unset Magnetometer in low power mode.
|
|
* @param status 0 means disable Low Power Mode, otherwise Low Power Mode is enabled
|
|
*/
|
|
void LIS3MDL_MagLowPower(uint16_t status)
|
|
{
|
|
80018ba: b580 push {r7, lr}
|
|
80018bc: b084 sub sp, #16
|
|
80018be: af00 add r7, sp, #0
|
|
80018c0: 4603 mov r3, r0
|
|
80018c2: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0;
|
|
80018c4: 2300 movs r3, #0
|
|
80018c6: 73fb strb r3, [r7, #15]
|
|
|
|
/* Read control register 1 value */
|
|
ctrl = SENSOR_IO_Read(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3);
|
|
80018c8: 2122 movs r1, #34 @ 0x22
|
|
80018ca: 203c movs r0, #60 @ 0x3c
|
|
80018cc: f7ff fc16 bl 80010fc <SENSOR_IO_Read>
|
|
80018d0: 4603 mov r3, r0
|
|
80018d2: 73fb strb r3, [r7, #15]
|
|
|
|
/* Clear Low Power Mode bit */
|
|
ctrl &= ~(0x20);
|
|
80018d4: 7bfb ldrb r3, [r7, #15]
|
|
80018d6: f023 0320 bic.w r3, r3, #32
|
|
80018da: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set Low Power Mode */
|
|
if(status)
|
|
80018dc: 88fb ldrh r3, [r7, #6]
|
|
80018de: 2b00 cmp r3, #0
|
|
80018e0: d003 beq.n 80018ea <LIS3MDL_MagLowPower+0x30>
|
|
{
|
|
ctrl |= LIS3MDL_MAG_CONFIG_LOWPOWER_MODE;
|
|
80018e2: 7bfb ldrb r3, [r7, #15]
|
|
80018e4: f043 0320 orr.w r3, r3, #32
|
|
80018e8: 73fb strb r3, [r7, #15]
|
|
{
|
|
ctrl |= LIS3MDL_MAG_CONFIG_NORMAL_MODE;
|
|
}
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG3, ctrl);
|
|
80018ea: 7bfb ldrb r3, [r7, #15]
|
|
80018ec: 461a mov r2, r3
|
|
80018ee: 2122 movs r1, #34 @ 0x22
|
|
80018f0: 203c movs r0, #60 @ 0x3c
|
|
80018f2: f7ff fbe9 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
80018f6: bf00 nop
|
|
80018f8: 3710 adds r7, #16
|
|
80018fa: 46bd mov sp, r7
|
|
80018fc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001900 <LIS3MDL_MagReadXYZ>:
|
|
/**
|
|
* @brief Read X, Y & Z Magnetometer values
|
|
* @param pData: Data out pointer
|
|
*/
|
|
void LIS3MDL_MagReadXYZ(int16_t* pData)
|
|
{
|
|
8001900: b580 push {r7, lr}
|
|
8001902: b088 sub sp, #32
|
|
8001904: af00 add r7, sp, #0
|
|
8001906: 6078 str r0, [r7, #4]
|
|
int16_t pnRawData[3];
|
|
uint8_t ctrlm= 0;
|
|
8001908: 2300 movs r3, #0
|
|
800190a: 75fb strb r3, [r7, #23]
|
|
uint8_t buffer[6];
|
|
uint8_t i = 0;
|
|
800190c: 2300 movs r3, #0
|
|
800190e: 77fb strb r3, [r7, #31]
|
|
float sensitivity = 0;
|
|
8001910: f04f 0300 mov.w r3, #0
|
|
8001914: 61bb str r3, [r7, #24]
|
|
|
|
/* Read the magnetometer control register content */
|
|
ctrlm = SENSOR_IO_Read(LIS3MDL_MAG_I2C_ADDRESS_HIGH, LIS3MDL_MAG_CTRL_REG2);
|
|
8001916: 2121 movs r1, #33 @ 0x21
|
|
8001918: 203c movs r0, #60 @ 0x3c
|
|
800191a: f7ff fbef bl 80010fc <SENSOR_IO_Read>
|
|
800191e: 4603 mov r3, r0
|
|
8001920: 75fb strb r3, [r7, #23]
|
|
|
|
/* Read output register X, Y & Z acceleration */
|
|
SENSOR_IO_ReadMultiple(LIS3MDL_MAG_I2C_ADDRESS_HIGH, (LIS3MDL_MAG_OUTX_L | 0x80), buffer, 6);
|
|
8001922: f107 0208 add.w r2, r7, #8
|
|
8001926: 2306 movs r3, #6
|
|
8001928: 21a8 movs r1, #168 @ 0xa8
|
|
800192a: 203c movs r0, #60 @ 0x3c
|
|
800192c: f7ff fc04 bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
for(i=0; i<3; i++)
|
|
8001930: 2300 movs r3, #0
|
|
8001932: 77fb strb r3, [r7, #31]
|
|
8001934: e01a b.n 800196c <LIS3MDL_MagReadXYZ+0x6c>
|
|
{
|
|
pnRawData[i]=((((uint16_t)buffer[2*i+1]) << 8) + (uint16_t)buffer[2*i]);
|
|
8001936: 7ffb ldrb r3, [r7, #31]
|
|
8001938: 005b lsls r3, r3, #1
|
|
800193a: 3301 adds r3, #1
|
|
800193c: 3320 adds r3, #32
|
|
800193e: 443b add r3, r7
|
|
8001940: f813 3c18 ldrb.w r3, [r3, #-24]
|
|
8001944: 021b lsls r3, r3, #8
|
|
8001946: b29b uxth r3, r3
|
|
8001948: 7ffa ldrb r2, [r7, #31]
|
|
800194a: 0052 lsls r2, r2, #1
|
|
800194c: 3220 adds r2, #32
|
|
800194e: 443a add r2, r7
|
|
8001950: f812 2c18 ldrb.w r2, [r2, #-24]
|
|
8001954: 4413 add r3, r2
|
|
8001956: b29a uxth r2, r3
|
|
8001958: 7ffb ldrb r3, [r7, #31]
|
|
800195a: b212 sxth r2, r2
|
|
800195c: 005b lsls r3, r3, #1
|
|
800195e: 3320 adds r3, #32
|
|
8001960: 443b add r3, r7
|
|
8001962: f823 2c10 strh.w r2, [r3, #-16]
|
|
for(i=0; i<3; i++)
|
|
8001966: 7ffb ldrb r3, [r7, #31]
|
|
8001968: 3301 adds r3, #1
|
|
800196a: 77fb strb r3, [r7, #31]
|
|
800196c: 7ffb ldrb r3, [r7, #31]
|
|
800196e: 2b02 cmp r3, #2
|
|
8001970: d9e1 bls.n 8001936 <LIS3MDL_MagReadXYZ+0x36>
|
|
}
|
|
|
|
/* Normal mode */
|
|
/* Switch the sensitivity value set in the CRTL_REG2 */
|
|
switch(ctrlm & 0x60)
|
|
8001972: 7dfb ldrb r3, [r7, #23]
|
|
8001974: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8001978: 2b60 cmp r3, #96 @ 0x60
|
|
800197a: d013 beq.n 80019a4 <LIS3MDL_MagReadXYZ+0xa4>
|
|
800197c: 2b60 cmp r3, #96 @ 0x60
|
|
800197e: dc14 bgt.n 80019aa <LIS3MDL_MagReadXYZ+0xaa>
|
|
8001980: 2b40 cmp r3, #64 @ 0x40
|
|
8001982: d00c beq.n 800199e <LIS3MDL_MagReadXYZ+0x9e>
|
|
8001984: 2b40 cmp r3, #64 @ 0x40
|
|
8001986: dc10 bgt.n 80019aa <LIS3MDL_MagReadXYZ+0xaa>
|
|
8001988: 2b00 cmp r3, #0
|
|
800198a: d002 beq.n 8001992 <LIS3MDL_MagReadXYZ+0x92>
|
|
800198c: 2b20 cmp r3, #32
|
|
800198e: d003 beq.n 8001998 <LIS3MDL_MagReadXYZ+0x98>
|
|
8001990: e00b b.n 80019aa <LIS3MDL_MagReadXYZ+0xaa>
|
|
{
|
|
case LIS3MDL_MAG_FS_4_GA:
|
|
sensitivity = LIS3MDL_MAG_SENSITIVITY_FOR_FS_4GA;
|
|
8001992: 4b19 ldr r3, [pc, #100] @ (80019f8 <LIS3MDL_MagReadXYZ+0xf8>)
|
|
8001994: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001996: e008 b.n 80019aa <LIS3MDL_MagReadXYZ+0xaa>
|
|
case LIS3MDL_MAG_FS_8_GA:
|
|
sensitivity = LIS3MDL_MAG_SENSITIVITY_FOR_FS_8GA;
|
|
8001998: 4b18 ldr r3, [pc, #96] @ (80019fc <LIS3MDL_MagReadXYZ+0xfc>)
|
|
800199a: 61bb str r3, [r7, #24]
|
|
break;
|
|
800199c: e005 b.n 80019aa <LIS3MDL_MagReadXYZ+0xaa>
|
|
case LIS3MDL_MAG_FS_12_GA:
|
|
sensitivity = LIS3MDL_MAG_SENSITIVITY_FOR_FS_12GA;
|
|
800199e: 4b18 ldr r3, [pc, #96] @ (8001a00 <LIS3MDL_MagReadXYZ+0x100>)
|
|
80019a0: 61bb str r3, [r7, #24]
|
|
break;
|
|
80019a2: e002 b.n 80019aa <LIS3MDL_MagReadXYZ+0xaa>
|
|
case LIS3MDL_MAG_FS_16_GA:
|
|
sensitivity = LIS3MDL_MAG_SENSITIVITY_FOR_FS_16GA;
|
|
80019a4: 4b17 ldr r3, [pc, #92] @ (8001a04 <LIS3MDL_MagReadXYZ+0x104>)
|
|
80019a6: 61bb str r3, [r7, #24]
|
|
break;
|
|
80019a8: bf00 nop
|
|
}
|
|
|
|
/* Obtain the mGauss value for the three axis */
|
|
for(i=0; i<3; i++)
|
|
80019aa: 2300 movs r3, #0
|
|
80019ac: 77fb strb r3, [r7, #31]
|
|
80019ae: e01a b.n 80019e6 <LIS3MDL_MagReadXYZ+0xe6>
|
|
{
|
|
pData[i]=( int16_t )(pnRawData[i] * sensitivity);
|
|
80019b0: 7ffb ldrb r3, [r7, #31]
|
|
80019b2: 005b lsls r3, r3, #1
|
|
80019b4: 3320 adds r3, #32
|
|
80019b6: 443b add r3, r7
|
|
80019b8: f933 3c10 ldrsh.w r3, [r3, #-16]
|
|
80019bc: ee07 3a90 vmov s15, r3
|
|
80019c0: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80019c4: edd7 7a06 vldr s15, [r7, #24]
|
|
80019c8: ee67 7a27 vmul.f32 s15, s14, s15
|
|
80019cc: 7ffb ldrb r3, [r7, #31]
|
|
80019ce: 005b lsls r3, r3, #1
|
|
80019d0: 687a ldr r2, [r7, #4]
|
|
80019d2: 4413 add r3, r2
|
|
80019d4: eefd 7ae7 vcvt.s32.f32 s15, s15
|
|
80019d8: ee17 2a90 vmov r2, s15
|
|
80019dc: b212 sxth r2, r2
|
|
80019de: 801a strh r2, [r3, #0]
|
|
for(i=0; i<3; i++)
|
|
80019e0: 7ffb ldrb r3, [r7, #31]
|
|
80019e2: 3301 adds r3, #1
|
|
80019e4: 77fb strb r3, [r7, #31]
|
|
80019e6: 7ffb ldrb r3, [r7, #31]
|
|
80019e8: 2b02 cmp r3, #2
|
|
80019ea: d9e1 bls.n 80019b0 <LIS3MDL_MagReadXYZ+0xb0>
|
|
}
|
|
}
|
|
80019ec: bf00 nop
|
|
80019ee: bf00 nop
|
|
80019f0: 3720 adds r7, #32
|
|
80019f2: 46bd mov sp, r7
|
|
80019f4: bd80 pop {r7, pc}
|
|
80019f6: bf00 nop
|
|
80019f8: 3e0f5c29 .word 0x3e0f5c29
|
|
80019fc: 3e947ae1 .word 0x3e947ae1
|
|
8001a00: 3edc28f6 .word 0x3edc28f6
|
|
8001a04: 3f147ae1 .word 0x3f147ae1
|
|
|
|
08001a08 <LPS22HB_P_Init>:
|
|
*/
|
|
/**
|
|
* @brief Set LPS22HB pressure sensor Initialization.
|
|
*/
|
|
void LPS22HB_P_Init(uint16_t DeviceAddr)
|
|
{
|
|
8001a08: b580 push {r7, lr}
|
|
8001a0a: b082 sub sp, #8
|
|
8001a0c: af00 add r7, sp, #0
|
|
8001a0e: 4603 mov r3, r0
|
|
8001a10: 80fb strh r3, [r7, #6]
|
|
LPS22HB_Init(DeviceAddr);
|
|
8001a12: 88fb ldrh r3, [r7, #6]
|
|
8001a14: 4618 mov r0, r3
|
|
8001a16: f000 f879 bl 8001b0c <LPS22HB_Init>
|
|
}
|
|
8001a1a: bf00 nop
|
|
8001a1c: 3708 adds r7, #8
|
|
8001a1e: 46bd mov sp, r7
|
|
8001a20: bd80 pop {r7, pc}
|
|
|
|
08001a22 <LPS22HB_P_ReadID>:
|
|
/**
|
|
* @brief Read LPS22HB ID.
|
|
* @retval ID
|
|
*/
|
|
uint8_t LPS22HB_P_ReadID(uint16_t DeviceAddr)
|
|
{
|
|
8001a22: b580 push {r7, lr}
|
|
8001a24: b084 sub sp, #16
|
|
8001a26: af00 add r7, sp, #0
|
|
8001a28: 4603 mov r3, r0
|
|
8001a2a: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001a2c: 2300 movs r3, #0
|
|
8001a2e: 73fb strb r3, [r7, #15]
|
|
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
8001a30: f7ff fb40 bl 80010b4 <SENSOR_IO_Init>
|
|
|
|
/* Read value at Who am I register address */
|
|
ctrl = SENSOR_IO_Read(DeviceAddr, LPS22HB_WHO_AM_I_REG);
|
|
8001a34: 88fb ldrh r3, [r7, #6]
|
|
8001a36: b2db uxtb r3, r3
|
|
8001a38: 210f movs r1, #15
|
|
8001a3a: 4618 mov r0, r3
|
|
8001a3c: f7ff fb5e bl 80010fc <SENSOR_IO_Read>
|
|
8001a40: 4603 mov r3, r0
|
|
8001a42: 73fb strb r3, [r7, #15]
|
|
|
|
return ctrl;
|
|
8001a44: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001a46: 4618 mov r0, r3
|
|
8001a48: 3710 adds r7, #16
|
|
8001a4a: 46bd mov sp, r7
|
|
8001a4c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001a50 <LPS22HB_P_ReadPressure>:
|
|
/**
|
|
* @brief Read pressure value of LPS22HB
|
|
* @retval pressure value
|
|
*/
|
|
float LPS22HB_P_ReadPressure(uint16_t DeviceAddr)
|
|
{
|
|
8001a50: b590 push {r4, r7, lr}
|
|
8001a52: b087 sub sp, #28
|
|
8001a54: af00 add r7, sp, #0
|
|
8001a56: 4603 mov r3, r0
|
|
8001a58: 80fb strh r3, [r7, #6]
|
|
int32_t raw_press;
|
|
uint8_t buffer[3];
|
|
uint32_t tmp = 0;
|
|
8001a5a: 2300 movs r3, #0
|
|
8001a5c: 617b str r3, [r7, #20]
|
|
uint8_t i;
|
|
|
|
for(i = 0; i < 3; i++)
|
|
8001a5e: 2300 movs r3, #0
|
|
8001a60: 74fb strb r3, [r7, #19]
|
|
8001a62: e013 b.n 8001a8c <LPS22HB_P_ReadPressure+0x3c>
|
|
{
|
|
buffer[i] = SENSOR_IO_Read(DeviceAddr, (LPS22HB_PRESS_OUT_XL_REG + i));
|
|
8001a64: 88fb ldrh r3, [r7, #6]
|
|
8001a66: b2da uxtb r2, r3
|
|
8001a68: 7cfb ldrb r3, [r7, #19]
|
|
8001a6a: 3328 adds r3, #40 @ 0x28
|
|
8001a6c: b2db uxtb r3, r3
|
|
8001a6e: 7cfc ldrb r4, [r7, #19]
|
|
8001a70: 4619 mov r1, r3
|
|
8001a72: 4610 mov r0, r2
|
|
8001a74: f7ff fb42 bl 80010fc <SENSOR_IO_Read>
|
|
8001a78: 4603 mov r3, r0
|
|
8001a7a: 461a mov r2, r3
|
|
8001a7c: f104 0318 add.w r3, r4, #24
|
|
8001a80: 443b add r3, r7
|
|
8001a82: f803 2c10 strb.w r2, [r3, #-16]
|
|
for(i = 0; i < 3; i++)
|
|
8001a86: 7cfb ldrb r3, [r7, #19]
|
|
8001a88: 3301 adds r3, #1
|
|
8001a8a: 74fb strb r3, [r7, #19]
|
|
8001a8c: 7cfb ldrb r3, [r7, #19]
|
|
8001a8e: 2b02 cmp r3, #2
|
|
8001a90: d9e8 bls.n 8001a64 <LPS22HB_P_ReadPressure+0x14>
|
|
}
|
|
|
|
/* Build the raw data */
|
|
for(i = 0; i < 3; i++)
|
|
8001a92: 2300 movs r3, #0
|
|
8001a94: 74fb strb r3, [r7, #19]
|
|
8001a96: e00f b.n 8001ab8 <LPS22HB_P_ReadPressure+0x68>
|
|
tmp |= (((uint32_t)buffer[i]) << (8 * i));
|
|
8001a98: 7cfb ldrb r3, [r7, #19]
|
|
8001a9a: 3318 adds r3, #24
|
|
8001a9c: 443b add r3, r7
|
|
8001a9e: f813 3c10 ldrb.w r3, [r3, #-16]
|
|
8001aa2: 461a mov r2, r3
|
|
8001aa4: 7cfb ldrb r3, [r7, #19]
|
|
8001aa6: 00db lsls r3, r3, #3
|
|
8001aa8: fa02 f303 lsl.w r3, r2, r3
|
|
8001aac: 697a ldr r2, [r7, #20]
|
|
8001aae: 4313 orrs r3, r2
|
|
8001ab0: 617b str r3, [r7, #20]
|
|
for(i = 0; i < 3; i++)
|
|
8001ab2: 7cfb ldrb r3, [r7, #19]
|
|
8001ab4: 3301 adds r3, #1
|
|
8001ab6: 74fb strb r3, [r7, #19]
|
|
8001ab8: 7cfb ldrb r3, [r7, #19]
|
|
8001aba: 2b02 cmp r3, #2
|
|
8001abc: d9ec bls.n 8001a98 <LPS22HB_P_ReadPressure+0x48>
|
|
|
|
/* convert the 2's complement 24 bit to 2's complement 32 bit */
|
|
if(tmp & 0x00800000)
|
|
8001abe: 697b ldr r3, [r7, #20]
|
|
8001ac0: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8001ac4: 2b00 cmp r3, #0
|
|
8001ac6: d003 beq.n 8001ad0 <LPS22HB_P_ReadPressure+0x80>
|
|
tmp |= 0xFF000000;
|
|
8001ac8: 697b ldr r3, [r7, #20]
|
|
8001aca: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8001ace: 617b str r3, [r7, #20]
|
|
|
|
raw_press = ((int32_t)tmp);
|
|
8001ad0: 697b ldr r3, [r7, #20]
|
|
8001ad2: 60fb str r3, [r7, #12]
|
|
|
|
raw_press = (raw_press * 100) / 4096;
|
|
8001ad4: 68fb ldr r3, [r7, #12]
|
|
8001ad6: 2264 movs r2, #100 @ 0x64
|
|
8001ad8: fb02 f303 mul.w r3, r2, r3
|
|
8001adc: 2b00 cmp r3, #0
|
|
8001ade: da01 bge.n 8001ae4 <LPS22HB_P_ReadPressure+0x94>
|
|
8001ae0: f603 73ff addw r3, r3, #4095 @ 0xfff
|
|
8001ae4: 131b asrs r3, r3, #12
|
|
8001ae6: 60fb str r3, [r7, #12]
|
|
|
|
return (float)((float)raw_press / 100.0f);
|
|
8001ae8: 68fb ldr r3, [r7, #12]
|
|
8001aea: ee07 3a90 vmov s15, r3
|
|
8001aee: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001af2: ed9f 7a05 vldr s14, [pc, #20] @ 8001b08 <LPS22HB_P_ReadPressure+0xb8>
|
|
8001af6: eec7 6a87 vdiv.f32 s13, s15, s14
|
|
8001afa: eef0 7a66 vmov.f32 s15, s13
|
|
}
|
|
8001afe: eeb0 0a67 vmov.f32 s0, s15
|
|
8001b02: 371c adds r7, #28
|
|
8001b04: 46bd mov sp, r7
|
|
8001b06: bd90 pop {r4, r7, pc}
|
|
8001b08: 42c80000 .word 0x42c80000
|
|
|
|
08001b0c <LPS22HB_Init>:
|
|
* @brief Set LPS22HB Initialization.
|
|
* @param DeviceAddr: I2C device address
|
|
* @retval None
|
|
*/
|
|
static void LPS22HB_Init(uint16_t DeviceAddr)
|
|
{
|
|
8001b0c: b580 push {r7, lr}
|
|
8001b0e: b084 sub sp, #16
|
|
8001b10: af00 add r7, sp, #0
|
|
8001b12: 4603 mov r3, r0
|
|
8001b14: 80fb strh r3, [r7, #6]
|
|
uint8_t tmp;
|
|
|
|
/* Set Power mode */
|
|
tmp = SENSOR_IO_Read(DeviceAddr, LPS22HB_RES_CONF_REG);
|
|
8001b16: 88fb ldrh r3, [r7, #6]
|
|
8001b18: b2db uxtb r3, r3
|
|
8001b1a: 211a movs r1, #26
|
|
8001b1c: 4618 mov r0, r3
|
|
8001b1e: f7ff faed bl 80010fc <SENSOR_IO_Read>
|
|
8001b22: 4603 mov r3, r0
|
|
8001b24: 73fb strb r3, [r7, #15]
|
|
|
|
tmp &= ~LPS22HB_LCEN_MASK;
|
|
8001b26: 7bfb ldrb r3, [r7, #15]
|
|
8001b28: f023 0301 bic.w r3, r3, #1
|
|
8001b2c: 73fb strb r3, [r7, #15]
|
|
tmp |= (uint8_t)0x01; /* Set low current mode */
|
|
8001b2e: 7bfb ldrb r3, [r7, #15]
|
|
8001b30: f043 0301 orr.w r3, r3, #1
|
|
8001b34: 73fb strb r3, [r7, #15]
|
|
|
|
SENSOR_IO_Write(DeviceAddr, LPS22HB_RES_CONF_REG, tmp);
|
|
8001b36: 88fb ldrh r3, [r7, #6]
|
|
8001b38: b2db uxtb r3, r3
|
|
8001b3a: 7bfa ldrb r2, [r7, #15]
|
|
8001b3c: 211a movs r1, #26
|
|
8001b3e: 4618 mov r0, r3
|
|
8001b40: f7ff fac2 bl 80010c8 <SENSOR_IO_Write>
|
|
|
|
/* Read CTRL_REG1 */
|
|
tmp = SENSOR_IO_Read(DeviceAddr, LPS22HB_CTRL_REG1);
|
|
8001b44: 88fb ldrh r3, [r7, #6]
|
|
8001b46: b2db uxtb r3, r3
|
|
8001b48: 2110 movs r1, #16
|
|
8001b4a: 4618 mov r0, r3
|
|
8001b4c: f7ff fad6 bl 80010fc <SENSOR_IO_Read>
|
|
8001b50: 4603 mov r3, r0
|
|
8001b52: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set default ODR */
|
|
tmp &= ~LPS22HB_ODR_MASK;
|
|
8001b54: 7bfb ldrb r3, [r7, #15]
|
|
8001b56: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8001b5a: 73fb strb r3, [r7, #15]
|
|
tmp |= (uint8_t)0x30; /* Set ODR to 25Hz */
|
|
8001b5c: 7bfb ldrb r3, [r7, #15]
|
|
8001b5e: f043 0330 orr.w r3, r3, #48 @ 0x30
|
|
8001b62: 73fb strb r3, [r7, #15]
|
|
|
|
/* Enable BDU */
|
|
tmp &= ~LPS22HB_BDU_MASK;
|
|
8001b64: 7bfb ldrb r3, [r7, #15]
|
|
8001b66: f023 0302 bic.w r3, r3, #2
|
|
8001b6a: 73fb strb r3, [r7, #15]
|
|
tmp |= ((uint8_t)0x02);
|
|
8001b6c: 7bfb ldrb r3, [r7, #15]
|
|
8001b6e: f043 0302 orr.w r3, r3, #2
|
|
8001b72: 73fb strb r3, [r7, #15]
|
|
|
|
/* Apply settings to CTRL_REG1 */
|
|
SENSOR_IO_Write(DeviceAddr, LPS22HB_CTRL_REG1, tmp);
|
|
8001b74: 88fb ldrh r3, [r7, #6]
|
|
8001b76: b2db uxtb r3, r3
|
|
8001b78: 7bfa ldrb r2, [r7, #15]
|
|
8001b7a: 2110 movs r1, #16
|
|
8001b7c: 4618 mov r0, r3
|
|
8001b7e: f7ff faa3 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001b82: bf00 nop
|
|
8001b84: 3710 adds r7, #16
|
|
8001b86: 46bd mov sp, r7
|
|
8001b88: bd80 pop {r7, pc}
|
|
|
|
08001b8a <LSM6DSL_AccInit>:
|
|
/**
|
|
* @brief Set LSM6DSL Accelerometer Initialization.
|
|
* @param InitStruct: Init parameters
|
|
*/
|
|
void LSM6DSL_AccInit(uint16_t InitStruct)
|
|
{
|
|
8001b8a: b580 push {r7, lr}
|
|
8001b8c: b084 sub sp, #16
|
|
8001b8e: af00 add r7, sp, #0
|
|
8001b90: 4603 mov r3, r0
|
|
8001b92: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001b94: 2300 movs r3, #0
|
|
8001b96: 73fb strb r3, [r7, #15]
|
|
uint8_t tmp;
|
|
|
|
/* Read CTRL1_XL */
|
|
tmp = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL);
|
|
8001b98: 2110 movs r1, #16
|
|
8001b9a: 20d4 movs r0, #212 @ 0xd4
|
|
8001b9c: f7ff faae bl 80010fc <SENSOR_IO_Read>
|
|
8001ba0: 4603 mov r3, r0
|
|
8001ba2: 73bb strb r3, [r7, #14]
|
|
|
|
/* Write value to ACC MEMS CTRL1_XL register: FS and Data Rate */
|
|
ctrl = (uint8_t) InitStruct;
|
|
8001ba4: 88fb ldrh r3, [r7, #6]
|
|
8001ba6: 73fb strb r3, [r7, #15]
|
|
tmp &= ~(0xFC);
|
|
8001ba8: 7bbb ldrb r3, [r7, #14]
|
|
8001baa: f003 0303 and.w r3, r3, #3
|
|
8001bae: 73bb strb r3, [r7, #14]
|
|
tmp |= ctrl;
|
|
8001bb0: 7bba ldrb r2, [r7, #14]
|
|
8001bb2: 7bfb ldrb r3, [r7, #15]
|
|
8001bb4: 4313 orrs r3, r2
|
|
8001bb6: 73bb strb r3, [r7, #14]
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL, tmp);
|
|
8001bb8: 7bbb ldrb r3, [r7, #14]
|
|
8001bba: 461a mov r2, r3
|
|
8001bbc: 2110 movs r1, #16
|
|
8001bbe: 20d4 movs r0, #212 @ 0xd4
|
|
8001bc0: f7ff fa82 bl 80010c8 <SENSOR_IO_Write>
|
|
|
|
/* Read CTRL3_C */
|
|
tmp = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL3_C);
|
|
8001bc4: 2112 movs r1, #18
|
|
8001bc6: 20d4 movs r0, #212 @ 0xd4
|
|
8001bc8: f7ff fa98 bl 80010fc <SENSOR_IO_Read>
|
|
8001bcc: 4603 mov r3, r0
|
|
8001bce: 73bb strb r3, [r7, #14]
|
|
|
|
/* Write value to ACC MEMS CTRL3_C register: BDU and Auto-increment */
|
|
ctrl = ((uint8_t) (InitStruct >> 8));
|
|
8001bd0: 88fb ldrh r3, [r7, #6]
|
|
8001bd2: 0a1b lsrs r3, r3, #8
|
|
8001bd4: b29b uxth r3, r3
|
|
8001bd6: 73fb strb r3, [r7, #15]
|
|
tmp &= ~(0x44);
|
|
8001bd8: 7bbb ldrb r3, [r7, #14]
|
|
8001bda: f023 0344 bic.w r3, r3, #68 @ 0x44
|
|
8001bde: 73bb strb r3, [r7, #14]
|
|
tmp |= ctrl;
|
|
8001be0: 7bba ldrb r2, [r7, #14]
|
|
8001be2: 7bfb ldrb r3, [r7, #15]
|
|
8001be4: 4313 orrs r3, r2
|
|
8001be6: 73bb strb r3, [r7, #14]
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL3_C, tmp);
|
|
8001be8: 7bbb ldrb r3, [r7, #14]
|
|
8001bea: 461a mov r2, r3
|
|
8001bec: 2112 movs r1, #18
|
|
8001bee: 20d4 movs r0, #212 @ 0xd4
|
|
8001bf0: f7ff fa6a bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001bf4: bf00 nop
|
|
8001bf6: 3710 adds r7, #16
|
|
8001bf8: 46bd mov sp, r7
|
|
8001bfa: bd80 pop {r7, pc}
|
|
|
|
08001bfc <LSM6DSL_AccDeInit>:
|
|
|
|
/**
|
|
* @brief LSM6DSL Accelerometer De-initialization.
|
|
*/
|
|
void LSM6DSL_AccDeInit(void)
|
|
{
|
|
8001bfc: b580 push {r7, lr}
|
|
8001bfe: b082 sub sp, #8
|
|
8001c00: af00 add r7, sp, #0
|
|
uint8_t ctrl = 0x00;
|
|
8001c02: 2300 movs r3, #0
|
|
8001c04: 71fb strb r3, [r7, #7]
|
|
|
|
/* Read control register 1 value */
|
|
ctrl = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL);
|
|
8001c06: 2110 movs r1, #16
|
|
8001c08: 20d4 movs r0, #212 @ 0xd4
|
|
8001c0a: f7ff fa77 bl 80010fc <SENSOR_IO_Read>
|
|
8001c0e: 4603 mov r3, r0
|
|
8001c10: 71fb strb r3, [r7, #7]
|
|
|
|
/* Clear ODR bits */
|
|
ctrl &= ~(LSM6DSL_ODR_BITPOSITION);
|
|
8001c12: 79fb ldrb r3, [r7, #7]
|
|
8001c14: f003 030f and.w r3, r3, #15
|
|
8001c18: 71fb strb r3, [r7, #7]
|
|
|
|
/* Set Power down */
|
|
ctrl |= LSM6DSL_ODR_POWER_DOWN;
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL, ctrl);
|
|
8001c1a: 79fb ldrb r3, [r7, #7]
|
|
8001c1c: 461a mov r2, r3
|
|
8001c1e: 2110 movs r1, #16
|
|
8001c20: 20d4 movs r0, #212 @ 0xd4
|
|
8001c22: f7ff fa51 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001c26: bf00 nop
|
|
8001c28: 3708 adds r7, #8
|
|
8001c2a: 46bd mov sp, r7
|
|
8001c2c: bd80 pop {r7, pc}
|
|
|
|
08001c2e <LSM6DSL_AccReadID>:
|
|
/**
|
|
* @brief Read LSM6DSL ID.
|
|
* @retval ID
|
|
*/
|
|
uint8_t LSM6DSL_AccReadID(void)
|
|
{
|
|
8001c2e: b580 push {r7, lr}
|
|
8001c30: af00 add r7, sp, #0
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
8001c32: f7ff fa3f bl 80010b4 <SENSOR_IO_Init>
|
|
/* Read value at Who am I register address */
|
|
return (SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_WHO_AM_I_REG));
|
|
8001c36: 210f movs r1, #15
|
|
8001c38: 20d4 movs r0, #212 @ 0xd4
|
|
8001c3a: f7ff fa5f bl 80010fc <SENSOR_IO_Read>
|
|
8001c3e: 4603 mov r3, r0
|
|
}
|
|
8001c40: 4618 mov r0, r3
|
|
8001c42: bd80 pop {r7, pc}
|
|
|
|
08001c44 <LSM6DSL_AccLowPower>:
|
|
/**
|
|
* @brief Set/Unset Accelerometer in low power mode.
|
|
* @param status 0 means disable Low Power Mode, otherwise Low Power Mode is enabled
|
|
*/
|
|
void LSM6DSL_AccLowPower(uint16_t status)
|
|
{
|
|
8001c44: b580 push {r7, lr}
|
|
8001c46: b084 sub sp, #16
|
|
8001c48: af00 add r7, sp, #0
|
|
8001c4a: 4603 mov r3, r0
|
|
8001c4c: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001c4e: 2300 movs r3, #0
|
|
8001c50: 73fb strb r3, [r7, #15]
|
|
|
|
/* Read CTRL6_C value */
|
|
ctrl = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL6_C);
|
|
8001c52: 2115 movs r1, #21
|
|
8001c54: 20d4 movs r0, #212 @ 0xd4
|
|
8001c56: f7ff fa51 bl 80010fc <SENSOR_IO_Read>
|
|
8001c5a: 4603 mov r3, r0
|
|
8001c5c: 73fb strb r3, [r7, #15]
|
|
|
|
/* Clear Low Power Mode bit */
|
|
ctrl &= ~(0x10);
|
|
8001c5e: 7bfb ldrb r3, [r7, #15]
|
|
8001c60: f023 0310 bic.w r3, r3, #16
|
|
8001c64: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set Low Power Mode */
|
|
if(status)
|
|
8001c66: 88fb ldrh r3, [r7, #6]
|
|
8001c68: 2b00 cmp r3, #0
|
|
8001c6a: d003 beq.n 8001c74 <LSM6DSL_AccLowPower+0x30>
|
|
{
|
|
ctrl |= LSM6DSL_ACC_GYRO_LP_XL_ENABLED;
|
|
8001c6c: 7bfb ldrb r3, [r7, #15]
|
|
8001c6e: f043 0310 orr.w r3, r3, #16
|
|
8001c72: 73fb strb r3, [r7, #15]
|
|
{
|
|
ctrl |= LSM6DSL_ACC_GYRO_LP_XL_DISABLED;
|
|
}
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL6_C, ctrl);
|
|
8001c74: 7bfb ldrb r3, [r7, #15]
|
|
8001c76: 461a mov r2, r3
|
|
8001c78: 2115 movs r1, #21
|
|
8001c7a: 20d4 movs r0, #212 @ 0xd4
|
|
8001c7c: f7ff fa24 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001c80: bf00 nop
|
|
8001c82: 3710 adds r7, #16
|
|
8001c84: 46bd mov sp, r7
|
|
8001c86: bd80 pop {r7, pc}
|
|
|
|
08001c88 <LSM6DSL_AccReadXYZ>:
|
|
/**
|
|
* @brief Read X, Y & Z Acceleration values
|
|
* @param pData: Data out pointer
|
|
*/
|
|
void LSM6DSL_AccReadXYZ(int16_t* pData)
|
|
{
|
|
8001c88: b580 push {r7, lr}
|
|
8001c8a: b088 sub sp, #32
|
|
8001c8c: af00 add r7, sp, #0
|
|
8001c8e: 6078 str r0, [r7, #4]
|
|
int16_t pnRawData[3];
|
|
uint8_t ctrlx= 0;
|
|
8001c90: 2300 movs r3, #0
|
|
8001c92: 75fb strb r3, [r7, #23]
|
|
uint8_t buffer[6];
|
|
uint8_t i = 0;
|
|
8001c94: 2300 movs r3, #0
|
|
8001c96: 77fb strb r3, [r7, #31]
|
|
float sensitivity = 0;
|
|
8001c98: f04f 0300 mov.w r3, #0
|
|
8001c9c: 61bb str r3, [r7, #24]
|
|
|
|
/* Read the acceleration control register content */
|
|
ctrlx = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL1_XL);
|
|
8001c9e: 2110 movs r1, #16
|
|
8001ca0: 20d4 movs r0, #212 @ 0xd4
|
|
8001ca2: f7ff fa2b bl 80010fc <SENSOR_IO_Read>
|
|
8001ca6: 4603 mov r3, r0
|
|
8001ca8: 75fb strb r3, [r7, #23]
|
|
|
|
/* Read output register X, Y & Z acceleration */
|
|
SENSOR_IO_ReadMultiple(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_OUTX_L_XL, buffer, 6);
|
|
8001caa: f107 0208 add.w r2, r7, #8
|
|
8001cae: 2306 movs r3, #6
|
|
8001cb0: 2128 movs r1, #40 @ 0x28
|
|
8001cb2: 20d4 movs r0, #212 @ 0xd4
|
|
8001cb4: f7ff fa40 bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
for(i=0; i<3; i++)
|
|
8001cb8: 2300 movs r3, #0
|
|
8001cba: 77fb strb r3, [r7, #31]
|
|
8001cbc: e01a b.n 8001cf4 <LSM6DSL_AccReadXYZ+0x6c>
|
|
{
|
|
pnRawData[i]=((((uint16_t)buffer[2*i+1]) << 8) + (uint16_t)buffer[2*i]);
|
|
8001cbe: 7ffb ldrb r3, [r7, #31]
|
|
8001cc0: 005b lsls r3, r3, #1
|
|
8001cc2: 3301 adds r3, #1
|
|
8001cc4: 3320 adds r3, #32
|
|
8001cc6: 443b add r3, r7
|
|
8001cc8: f813 3c18 ldrb.w r3, [r3, #-24]
|
|
8001ccc: 021b lsls r3, r3, #8
|
|
8001cce: b29b uxth r3, r3
|
|
8001cd0: 7ffa ldrb r2, [r7, #31]
|
|
8001cd2: 0052 lsls r2, r2, #1
|
|
8001cd4: 3220 adds r2, #32
|
|
8001cd6: 443a add r2, r7
|
|
8001cd8: f812 2c18 ldrb.w r2, [r2, #-24]
|
|
8001cdc: 4413 add r3, r2
|
|
8001cde: b29a uxth r2, r3
|
|
8001ce0: 7ffb ldrb r3, [r7, #31]
|
|
8001ce2: b212 sxth r2, r2
|
|
8001ce4: 005b lsls r3, r3, #1
|
|
8001ce6: 3320 adds r3, #32
|
|
8001ce8: 443b add r3, r7
|
|
8001cea: f823 2c10 strh.w r2, [r3, #-16]
|
|
for(i=0; i<3; i++)
|
|
8001cee: 7ffb ldrb r3, [r7, #31]
|
|
8001cf0: 3301 adds r3, #1
|
|
8001cf2: 77fb strb r3, [r7, #31]
|
|
8001cf4: 7ffb ldrb r3, [r7, #31]
|
|
8001cf6: 2b02 cmp r3, #2
|
|
8001cf8: d9e1 bls.n 8001cbe <LSM6DSL_AccReadXYZ+0x36>
|
|
}
|
|
|
|
/* Normal mode */
|
|
/* Switch the sensitivity value set in the CRTL1_XL */
|
|
switch(ctrlx & 0x0C)
|
|
8001cfa: 7dfb ldrb r3, [r7, #23]
|
|
8001cfc: f003 030c and.w r3, r3, #12
|
|
8001d00: 2b0c cmp r3, #12
|
|
8001d02: d829 bhi.n 8001d58 <LSM6DSL_AccReadXYZ+0xd0>
|
|
8001d04: a201 add r2, pc, #4 @ (adr r2, 8001d0c <LSM6DSL_AccReadXYZ+0x84>)
|
|
8001d06: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8001d0a: bf00 nop
|
|
8001d0c: 08001d41 .word 0x08001d41
|
|
8001d10: 08001d59 .word 0x08001d59
|
|
8001d14: 08001d59 .word 0x08001d59
|
|
8001d18: 08001d59 .word 0x08001d59
|
|
8001d1c: 08001d53 .word 0x08001d53
|
|
8001d20: 08001d59 .word 0x08001d59
|
|
8001d24: 08001d59 .word 0x08001d59
|
|
8001d28: 08001d59 .word 0x08001d59
|
|
8001d2c: 08001d47 .word 0x08001d47
|
|
8001d30: 08001d59 .word 0x08001d59
|
|
8001d34: 08001d59 .word 0x08001d59
|
|
8001d38: 08001d59 .word 0x08001d59
|
|
8001d3c: 08001d4d .word 0x08001d4d
|
|
{
|
|
case LSM6DSL_ACC_FULLSCALE_2G:
|
|
sensitivity = LSM6DSL_ACC_SENSITIVITY_2G;
|
|
8001d40: 4b18 ldr r3, [pc, #96] @ (8001da4 <LSM6DSL_AccReadXYZ+0x11c>)
|
|
8001d42: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001d44: e008 b.n 8001d58 <LSM6DSL_AccReadXYZ+0xd0>
|
|
case LSM6DSL_ACC_FULLSCALE_4G:
|
|
sensitivity = LSM6DSL_ACC_SENSITIVITY_4G;
|
|
8001d46: 4b18 ldr r3, [pc, #96] @ (8001da8 <LSM6DSL_AccReadXYZ+0x120>)
|
|
8001d48: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001d4a: e005 b.n 8001d58 <LSM6DSL_AccReadXYZ+0xd0>
|
|
case LSM6DSL_ACC_FULLSCALE_8G:
|
|
sensitivity = LSM6DSL_ACC_SENSITIVITY_8G;
|
|
8001d4c: 4b17 ldr r3, [pc, #92] @ (8001dac <LSM6DSL_AccReadXYZ+0x124>)
|
|
8001d4e: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001d50: e002 b.n 8001d58 <LSM6DSL_AccReadXYZ+0xd0>
|
|
case LSM6DSL_ACC_FULLSCALE_16G:
|
|
sensitivity = LSM6DSL_ACC_SENSITIVITY_16G;
|
|
8001d52: 4b17 ldr r3, [pc, #92] @ (8001db0 <LSM6DSL_AccReadXYZ+0x128>)
|
|
8001d54: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001d56: bf00 nop
|
|
}
|
|
|
|
/* Obtain the mg value for the three axis */
|
|
for(i=0; i<3; i++)
|
|
8001d58: 2300 movs r3, #0
|
|
8001d5a: 77fb strb r3, [r7, #31]
|
|
8001d5c: e01a b.n 8001d94 <LSM6DSL_AccReadXYZ+0x10c>
|
|
{
|
|
pData[i]=( int16_t )(pnRawData[i] * sensitivity);
|
|
8001d5e: 7ffb ldrb r3, [r7, #31]
|
|
8001d60: 005b lsls r3, r3, #1
|
|
8001d62: 3320 adds r3, #32
|
|
8001d64: 443b add r3, r7
|
|
8001d66: f933 3c10 ldrsh.w r3, [r3, #-16]
|
|
8001d6a: ee07 3a90 vmov s15, r3
|
|
8001d6e: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8001d72: edd7 7a06 vldr s15, [r7, #24]
|
|
8001d76: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001d7a: 7ffb ldrb r3, [r7, #31]
|
|
8001d7c: 005b lsls r3, r3, #1
|
|
8001d7e: 687a ldr r2, [r7, #4]
|
|
8001d80: 4413 add r3, r2
|
|
8001d82: eefd 7ae7 vcvt.s32.f32 s15, s15
|
|
8001d86: ee17 2a90 vmov r2, s15
|
|
8001d8a: b212 sxth r2, r2
|
|
8001d8c: 801a strh r2, [r3, #0]
|
|
for(i=0; i<3; i++)
|
|
8001d8e: 7ffb ldrb r3, [r7, #31]
|
|
8001d90: 3301 adds r3, #1
|
|
8001d92: 77fb strb r3, [r7, #31]
|
|
8001d94: 7ffb ldrb r3, [r7, #31]
|
|
8001d96: 2b02 cmp r3, #2
|
|
8001d98: d9e1 bls.n 8001d5e <LSM6DSL_AccReadXYZ+0xd6>
|
|
}
|
|
}
|
|
8001d9a: bf00 nop
|
|
8001d9c: bf00 nop
|
|
8001d9e: 3720 adds r7, #32
|
|
8001da0: 46bd mov sp, r7
|
|
8001da2: bd80 pop {r7, pc}
|
|
8001da4: 3d79db23 .word 0x3d79db23
|
|
8001da8: 3df9db23 .word 0x3df9db23
|
|
8001dac: 3e79db23 .word 0x3e79db23
|
|
8001db0: 3ef9db23 .word 0x3ef9db23
|
|
|
|
08001db4 <LSM6DSL_GyroInit>:
|
|
* @brief Set LSM6DSL Gyroscope Initialization.
|
|
* @param InitStruct: pointer to a LSM6DSL_InitTypeDef structure
|
|
* that contains the configuration setting for the LSM6DSL.
|
|
*/
|
|
void LSM6DSL_GyroInit(uint16_t InitStruct)
|
|
{
|
|
8001db4: b580 push {r7, lr}
|
|
8001db6: b084 sub sp, #16
|
|
8001db8: af00 add r7, sp, #0
|
|
8001dba: 4603 mov r3, r0
|
|
8001dbc: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001dbe: 2300 movs r3, #0
|
|
8001dc0: 73fb strb r3, [r7, #15]
|
|
uint8_t tmp;
|
|
|
|
/* Read CTRL2_G */
|
|
tmp = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G);
|
|
8001dc2: 2111 movs r1, #17
|
|
8001dc4: 20d4 movs r0, #212 @ 0xd4
|
|
8001dc6: f7ff f999 bl 80010fc <SENSOR_IO_Read>
|
|
8001dca: 4603 mov r3, r0
|
|
8001dcc: 73bb strb r3, [r7, #14]
|
|
|
|
/* Write value to GYRO MEMS CTRL2_G register: FS and Data Rate */
|
|
ctrl = (uint8_t) InitStruct;
|
|
8001dce: 88fb ldrh r3, [r7, #6]
|
|
8001dd0: 73fb strb r3, [r7, #15]
|
|
tmp &= ~(0xFC);
|
|
8001dd2: 7bbb ldrb r3, [r7, #14]
|
|
8001dd4: f003 0303 and.w r3, r3, #3
|
|
8001dd8: 73bb strb r3, [r7, #14]
|
|
tmp |= ctrl;
|
|
8001dda: 7bba ldrb r2, [r7, #14]
|
|
8001ddc: 7bfb ldrb r3, [r7, #15]
|
|
8001dde: 4313 orrs r3, r2
|
|
8001de0: 73bb strb r3, [r7, #14]
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G, tmp);
|
|
8001de2: 7bbb ldrb r3, [r7, #14]
|
|
8001de4: 461a mov r2, r3
|
|
8001de6: 2111 movs r1, #17
|
|
8001de8: 20d4 movs r0, #212 @ 0xd4
|
|
8001dea: f7ff f96d bl 80010c8 <SENSOR_IO_Write>
|
|
|
|
/* Read CTRL3_C */
|
|
tmp = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL3_C);
|
|
8001dee: 2112 movs r1, #18
|
|
8001df0: 20d4 movs r0, #212 @ 0xd4
|
|
8001df2: f7ff f983 bl 80010fc <SENSOR_IO_Read>
|
|
8001df6: 4603 mov r3, r0
|
|
8001df8: 73bb strb r3, [r7, #14]
|
|
|
|
/* Write value to GYRO MEMS CTRL3_C register: BDU and Auto-increment */
|
|
ctrl = ((uint8_t) (InitStruct >> 8));
|
|
8001dfa: 88fb ldrh r3, [r7, #6]
|
|
8001dfc: 0a1b lsrs r3, r3, #8
|
|
8001dfe: b29b uxth r3, r3
|
|
8001e00: 73fb strb r3, [r7, #15]
|
|
tmp &= ~(0x44);
|
|
8001e02: 7bbb ldrb r3, [r7, #14]
|
|
8001e04: f023 0344 bic.w r3, r3, #68 @ 0x44
|
|
8001e08: 73bb strb r3, [r7, #14]
|
|
tmp |= ctrl;
|
|
8001e0a: 7bba ldrb r2, [r7, #14]
|
|
8001e0c: 7bfb ldrb r3, [r7, #15]
|
|
8001e0e: 4313 orrs r3, r2
|
|
8001e10: 73bb strb r3, [r7, #14]
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL3_C, tmp);
|
|
8001e12: 7bbb ldrb r3, [r7, #14]
|
|
8001e14: 461a mov r2, r3
|
|
8001e16: 2112 movs r1, #18
|
|
8001e18: 20d4 movs r0, #212 @ 0xd4
|
|
8001e1a: f7ff f955 bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001e1e: bf00 nop
|
|
8001e20: 3710 adds r7, #16
|
|
8001e22: 46bd mov sp, r7
|
|
8001e24: bd80 pop {r7, pc}
|
|
|
|
08001e26 <LSM6DSL_GyroDeInit>:
|
|
|
|
/**
|
|
* @brief LSM6DSL Gyroscope De-initialization
|
|
*/
|
|
void LSM6DSL_GyroDeInit(void)
|
|
{
|
|
8001e26: b580 push {r7, lr}
|
|
8001e28: b082 sub sp, #8
|
|
8001e2a: af00 add r7, sp, #0
|
|
uint8_t ctrl = 0x00;
|
|
8001e2c: 2300 movs r3, #0
|
|
8001e2e: 71fb strb r3, [r7, #7]
|
|
|
|
/* Read control register 1 value */
|
|
ctrl = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G);
|
|
8001e30: 2111 movs r1, #17
|
|
8001e32: 20d4 movs r0, #212 @ 0xd4
|
|
8001e34: f7ff f962 bl 80010fc <SENSOR_IO_Read>
|
|
8001e38: 4603 mov r3, r0
|
|
8001e3a: 71fb strb r3, [r7, #7]
|
|
|
|
/* Clear ODR bits */
|
|
ctrl &= ~(LSM6DSL_ODR_BITPOSITION);
|
|
8001e3c: 79fb ldrb r3, [r7, #7]
|
|
8001e3e: f003 030f and.w r3, r3, #15
|
|
8001e42: 71fb strb r3, [r7, #7]
|
|
|
|
/* Set Power down */
|
|
ctrl |= LSM6DSL_ODR_POWER_DOWN;
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G, ctrl);
|
|
8001e44: 79fb ldrb r3, [r7, #7]
|
|
8001e46: 461a mov r2, r3
|
|
8001e48: 2111 movs r1, #17
|
|
8001e4a: 20d4 movs r0, #212 @ 0xd4
|
|
8001e4c: f7ff f93c bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001e50: bf00 nop
|
|
8001e52: 3708 adds r7, #8
|
|
8001e54: 46bd mov sp, r7
|
|
8001e56: bd80 pop {r7, pc}
|
|
|
|
08001e58 <LSM6DSL_GyroReadID>:
|
|
/**
|
|
* @brief Read ID address of LSM6DSL
|
|
* @retval ID
|
|
*/
|
|
uint8_t LSM6DSL_GyroReadID(void)
|
|
{
|
|
8001e58: b580 push {r7, lr}
|
|
8001e5a: af00 add r7, sp, #0
|
|
/* IO interface initialization */
|
|
SENSOR_IO_Init();
|
|
8001e5c: f7ff f92a bl 80010b4 <SENSOR_IO_Init>
|
|
/* Read value at Who am I register address */
|
|
return SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_WHO_AM_I_REG);
|
|
8001e60: 210f movs r1, #15
|
|
8001e62: 20d4 movs r0, #212 @ 0xd4
|
|
8001e64: f7ff f94a bl 80010fc <SENSOR_IO_Read>
|
|
8001e68: 4603 mov r3, r0
|
|
}
|
|
8001e6a: 4618 mov r0, r3
|
|
8001e6c: bd80 pop {r7, pc}
|
|
|
|
08001e6e <LSM6DSL_GyroLowPower>:
|
|
/**
|
|
* @brief Set/Unset LSM6DSL Gyroscope in low power mode
|
|
* @param status 0 means disable Low Power Mode, otherwise Low Power Mode is enabled
|
|
*/
|
|
void LSM6DSL_GyroLowPower(uint16_t status)
|
|
{
|
|
8001e6e: b580 push {r7, lr}
|
|
8001e70: b084 sub sp, #16
|
|
8001e72: af00 add r7, sp, #0
|
|
8001e74: 4603 mov r3, r0
|
|
8001e76: 80fb strh r3, [r7, #6]
|
|
uint8_t ctrl = 0x00;
|
|
8001e78: 2300 movs r3, #0
|
|
8001e7a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Read CTRL7_G value */
|
|
ctrl = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL7_G);
|
|
8001e7c: 2116 movs r1, #22
|
|
8001e7e: 20d4 movs r0, #212 @ 0xd4
|
|
8001e80: f7ff f93c bl 80010fc <SENSOR_IO_Read>
|
|
8001e84: 4603 mov r3, r0
|
|
8001e86: 73fb strb r3, [r7, #15]
|
|
|
|
/* Clear Low Power Mode bit */
|
|
ctrl &= ~(0x80);
|
|
8001e88: 7bfb ldrb r3, [r7, #15]
|
|
8001e8a: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8001e8e: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set Low Power Mode */
|
|
if(status)
|
|
8001e90: 88fb ldrh r3, [r7, #6]
|
|
8001e92: 2b00 cmp r3, #0
|
|
8001e94: d003 beq.n 8001e9e <LSM6DSL_GyroLowPower+0x30>
|
|
{
|
|
ctrl |= LSM6DSL_ACC_GYRO_LP_G_ENABLED;
|
|
8001e96: 7bfb ldrb r3, [r7, #15]
|
|
8001e98: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8001e9c: 73fb strb r3, [r7, #15]
|
|
{
|
|
ctrl |= LSM6DSL_ACC_GYRO_LP_G_DISABLED;
|
|
}
|
|
|
|
/* write back control register */
|
|
SENSOR_IO_Write(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL7_G, ctrl);
|
|
8001e9e: 7bfb ldrb r3, [r7, #15]
|
|
8001ea0: 461a mov r2, r3
|
|
8001ea2: 2116 movs r1, #22
|
|
8001ea4: 20d4 movs r0, #212 @ 0xd4
|
|
8001ea6: f7ff f90f bl 80010c8 <SENSOR_IO_Write>
|
|
}
|
|
8001eaa: bf00 nop
|
|
8001eac: 3710 adds r7, #16
|
|
8001eae: 46bd mov sp, r7
|
|
8001eb0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001eb4 <LSM6DSL_GyroReadXYZAngRate>:
|
|
/**
|
|
* @brief Calculate the LSM6DSL angular data.
|
|
* @param pfData: Data out pointer
|
|
*/
|
|
void LSM6DSL_GyroReadXYZAngRate(float *pfData)
|
|
{
|
|
8001eb4: b580 push {r7, lr}
|
|
8001eb6: b088 sub sp, #32
|
|
8001eb8: af00 add r7, sp, #0
|
|
8001eba: 6078 str r0, [r7, #4]
|
|
int16_t pnRawData[3];
|
|
uint8_t ctrlg= 0;
|
|
8001ebc: 2300 movs r3, #0
|
|
8001ebe: 75fb strb r3, [r7, #23]
|
|
uint8_t buffer[6];
|
|
uint8_t i = 0;
|
|
8001ec0: 2300 movs r3, #0
|
|
8001ec2: 77fb strb r3, [r7, #31]
|
|
float sensitivity = 0;
|
|
8001ec4: f04f 0300 mov.w r3, #0
|
|
8001ec8: 61bb str r3, [r7, #24]
|
|
|
|
/* Read the gyro control register content */
|
|
ctrlg = SENSOR_IO_Read(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_CTRL2_G);
|
|
8001eca: 2111 movs r1, #17
|
|
8001ecc: 20d4 movs r0, #212 @ 0xd4
|
|
8001ece: f7ff f915 bl 80010fc <SENSOR_IO_Read>
|
|
8001ed2: 4603 mov r3, r0
|
|
8001ed4: 75fb strb r3, [r7, #23]
|
|
|
|
/* Read output register X, Y & Z acceleration */
|
|
SENSOR_IO_ReadMultiple(LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW, LSM6DSL_ACC_GYRO_OUTX_L_G, buffer, 6);
|
|
8001ed6: f107 0208 add.w r2, r7, #8
|
|
8001eda: 2306 movs r3, #6
|
|
8001edc: 2122 movs r1, #34 @ 0x22
|
|
8001ede: 20d4 movs r0, #212 @ 0xd4
|
|
8001ee0: f7ff f92a bl 8001138 <SENSOR_IO_ReadMultiple>
|
|
|
|
for(i=0; i<3; i++)
|
|
8001ee4: 2300 movs r3, #0
|
|
8001ee6: 77fb strb r3, [r7, #31]
|
|
8001ee8: e01a b.n 8001f20 <LSM6DSL_GyroReadXYZAngRate+0x6c>
|
|
{
|
|
pnRawData[i]=((((uint16_t)buffer[2*i+1]) << 8) + (uint16_t)buffer[2*i]);
|
|
8001eea: 7ffb ldrb r3, [r7, #31]
|
|
8001eec: 005b lsls r3, r3, #1
|
|
8001eee: 3301 adds r3, #1
|
|
8001ef0: 3320 adds r3, #32
|
|
8001ef2: 443b add r3, r7
|
|
8001ef4: f813 3c18 ldrb.w r3, [r3, #-24]
|
|
8001ef8: 021b lsls r3, r3, #8
|
|
8001efa: b29b uxth r3, r3
|
|
8001efc: 7ffa ldrb r2, [r7, #31]
|
|
8001efe: 0052 lsls r2, r2, #1
|
|
8001f00: 3220 adds r2, #32
|
|
8001f02: 443a add r2, r7
|
|
8001f04: f812 2c18 ldrb.w r2, [r2, #-24]
|
|
8001f08: 4413 add r3, r2
|
|
8001f0a: b29a uxth r2, r3
|
|
8001f0c: 7ffb ldrb r3, [r7, #31]
|
|
8001f0e: b212 sxth r2, r2
|
|
8001f10: 005b lsls r3, r3, #1
|
|
8001f12: 3320 adds r3, #32
|
|
8001f14: 443b add r3, r7
|
|
8001f16: f823 2c10 strh.w r2, [r3, #-16]
|
|
for(i=0; i<3; i++)
|
|
8001f1a: 7ffb ldrb r3, [r7, #31]
|
|
8001f1c: 3301 adds r3, #1
|
|
8001f1e: 77fb strb r3, [r7, #31]
|
|
8001f20: 7ffb ldrb r3, [r7, #31]
|
|
8001f22: 2b02 cmp r3, #2
|
|
8001f24: d9e1 bls.n 8001eea <LSM6DSL_GyroReadXYZAngRate+0x36>
|
|
}
|
|
|
|
/* Normal mode */
|
|
/* Switch the sensitivity value set in the CRTL2_G */
|
|
switch(ctrlg & 0x0C)
|
|
8001f26: 7dfb ldrb r3, [r7, #23]
|
|
8001f28: f003 030c and.w r3, r3, #12
|
|
8001f2c: 2b0c cmp r3, #12
|
|
8001f2e: d829 bhi.n 8001f84 <LSM6DSL_GyroReadXYZAngRate+0xd0>
|
|
8001f30: a201 add r2, pc, #4 @ (adr r2, 8001f38 <LSM6DSL_GyroReadXYZAngRate+0x84>)
|
|
8001f32: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8001f36: bf00 nop
|
|
8001f38: 08001f6d .word 0x08001f6d
|
|
8001f3c: 08001f85 .word 0x08001f85
|
|
8001f40: 08001f85 .word 0x08001f85
|
|
8001f44: 08001f85 .word 0x08001f85
|
|
8001f48: 08001f73 .word 0x08001f73
|
|
8001f4c: 08001f85 .word 0x08001f85
|
|
8001f50: 08001f85 .word 0x08001f85
|
|
8001f54: 08001f85 .word 0x08001f85
|
|
8001f58: 08001f79 .word 0x08001f79
|
|
8001f5c: 08001f85 .word 0x08001f85
|
|
8001f60: 08001f85 .word 0x08001f85
|
|
8001f64: 08001f85 .word 0x08001f85
|
|
8001f68: 08001f7f .word 0x08001f7f
|
|
{
|
|
case LSM6DSL_GYRO_FS_245:
|
|
sensitivity = LSM6DSL_GYRO_SENSITIVITY_245DPS;
|
|
8001f6c: 4b16 ldr r3, [pc, #88] @ (8001fc8 <LSM6DSL_GyroReadXYZAngRate+0x114>)
|
|
8001f6e: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001f70: e008 b.n 8001f84 <LSM6DSL_GyroReadXYZAngRate+0xd0>
|
|
case LSM6DSL_GYRO_FS_500:
|
|
sensitivity = LSM6DSL_GYRO_SENSITIVITY_500DPS;
|
|
8001f72: 4b16 ldr r3, [pc, #88] @ (8001fcc <LSM6DSL_GyroReadXYZAngRate+0x118>)
|
|
8001f74: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001f76: e005 b.n 8001f84 <LSM6DSL_GyroReadXYZAngRate+0xd0>
|
|
case LSM6DSL_GYRO_FS_1000:
|
|
sensitivity = LSM6DSL_GYRO_SENSITIVITY_1000DPS;
|
|
8001f78: 4b15 ldr r3, [pc, #84] @ (8001fd0 <LSM6DSL_GyroReadXYZAngRate+0x11c>)
|
|
8001f7a: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001f7c: e002 b.n 8001f84 <LSM6DSL_GyroReadXYZAngRate+0xd0>
|
|
case LSM6DSL_GYRO_FS_2000:
|
|
sensitivity = LSM6DSL_GYRO_SENSITIVITY_2000DPS;
|
|
8001f7e: 4b15 ldr r3, [pc, #84] @ (8001fd4 <LSM6DSL_GyroReadXYZAngRate+0x120>)
|
|
8001f80: 61bb str r3, [r7, #24]
|
|
break;
|
|
8001f82: bf00 nop
|
|
}
|
|
|
|
/* Obtain the mg value for the three axis */
|
|
for(i=0; i<3; i++)
|
|
8001f84: 2300 movs r3, #0
|
|
8001f86: 77fb strb r3, [r7, #31]
|
|
8001f88: e016 b.n 8001fb8 <LSM6DSL_GyroReadXYZAngRate+0x104>
|
|
{
|
|
pfData[i]=( float )(pnRawData[i] * sensitivity);
|
|
8001f8a: 7ffb ldrb r3, [r7, #31]
|
|
8001f8c: 005b lsls r3, r3, #1
|
|
8001f8e: 3320 adds r3, #32
|
|
8001f90: 443b add r3, r7
|
|
8001f92: f933 3c10 ldrsh.w r3, [r3, #-16]
|
|
8001f96: ee07 3a90 vmov s15, r3
|
|
8001f9a: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8001f9e: 7ffb ldrb r3, [r7, #31]
|
|
8001fa0: 009b lsls r3, r3, #2
|
|
8001fa2: 687a ldr r2, [r7, #4]
|
|
8001fa4: 4413 add r3, r2
|
|
8001fa6: edd7 7a06 vldr s15, [r7, #24]
|
|
8001faa: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001fae: edc3 7a00 vstr s15, [r3]
|
|
for(i=0; i<3; i++)
|
|
8001fb2: 7ffb ldrb r3, [r7, #31]
|
|
8001fb4: 3301 adds r3, #1
|
|
8001fb6: 77fb strb r3, [r7, #31]
|
|
8001fb8: 7ffb ldrb r3, [r7, #31]
|
|
8001fba: 2b02 cmp r3, #2
|
|
8001fbc: d9e5 bls.n 8001f8a <LSM6DSL_GyroReadXYZAngRate+0xd6>
|
|
}
|
|
}
|
|
8001fbe: bf00 nop
|
|
8001fc0: bf00 nop
|
|
8001fc2: 3720 adds r7, #32
|
|
8001fc4: 46bd mov sp, r7
|
|
8001fc6: bd80 pop {r7, pc}
|
|
8001fc8: 410c0000 .word 0x410c0000
|
|
8001fcc: 418c0000 .word 0x418c0000
|
|
8001fd0: 420c0000 .word 0x420c0000
|
|
8001fd4: 428c0000 .word 0x428c0000
|
|
|
|
08001fd8 <Accelero_Test>:
|
|
*/
|
|
|
|
#include "accelerometer.h"
|
|
|
|
void Accelero_Test(void)
|
|
{
|
|
8001fd8: b580 push {r7, lr}
|
|
8001fda: b082 sub sp, #8
|
|
8001fdc: af00 add r7, sp, #0
|
|
int16_t pDataXYZ[3] = {0};
|
|
8001fde: 463b mov r3, r7
|
|
8001fe0: 2200 movs r2, #0
|
|
8001fe2: 601a str r2, [r3, #0]
|
|
8001fe4: 809a strh r2, [r3, #4]
|
|
BSP_ACCELERO_Init();
|
|
8001fe6: f7ff f8c5 bl 8001174 <BSP_ACCELERO_Init>
|
|
BSP_ACCELERO_AccGetXYZ(pDataXYZ);
|
|
8001fea: 463b mov r3, r7
|
|
8001fec: 4618 mov r0, r3
|
|
8001fee: f7ff f915 bl 800121c <BSP_ACCELERO_AccGetXYZ>
|
|
printf("X= %d, Y = %d, Z = %d \n\r", pDataXYZ[0],
|
|
8001ff2: f9b7 3000 ldrsh.w r3, [r7]
|
|
8001ff6: 4619 mov r1, r3
|
|
pDataXYZ[1], pDataXYZ[2]);
|
|
8001ff8: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
printf("X= %d, Y = %d, Z = %d \n\r", pDataXYZ[0],
|
|
8001ffc: 461a mov r2, r3
|
|
pDataXYZ[1], pDataXYZ[2]);
|
|
8001ffe: f9b7 3004 ldrsh.w r3, [r7, #4]
|
|
printf("X= %d, Y = %d, Z = %d \n\r", pDataXYZ[0],
|
|
8002002: 4806 ldr r0, [pc, #24] @ (800201c <Accelero_Test+0x44>)
|
|
8002004: f005 ffe4 bl 8007fd0 <iprintf>
|
|
|
|
BSP_ACCELERO_DeInit();
|
|
8002008: f7ff f8f4 bl 80011f4 <BSP_ACCELERO_DeInit>
|
|
printf("\n*** End of Accelerometer Test ***\n\n");
|
|
800200c: 4804 ldr r0, [pc, #16] @ (8002020 <Accelero_Test+0x48>)
|
|
800200e: f006 f847 bl 80080a0 <puts>
|
|
return;
|
|
8002012: bf00 nop
|
|
}
|
|
8002014: 3708 adds r7, #8
|
|
8002016: 46bd mov sp, r7
|
|
8002018: bd80 pop {r7, pc}
|
|
800201a: bf00 nop
|
|
800201c: 08009fa0 .word 0x08009fa0
|
|
8002020: 08009fbc .word 0x08009fbc
|
|
|
|
08002024 <Gyro_Test>:
|
|
*/
|
|
|
|
#include "gyroscope.h"
|
|
|
|
void Gyro_Test(void)
|
|
{
|
|
8002024: b580 push {r7, lr}
|
|
8002026: b084 sub sp, #16
|
|
8002028: af00 add r7, sp, #0
|
|
float pGyroDataXYZ[3] = {0};
|
|
800202a: 1d3b adds r3, r7, #4
|
|
800202c: 2200 movs r2, #0
|
|
800202e: 601a str r2, [r3, #0]
|
|
8002030: 605a str r2, [r3, #4]
|
|
8002032: 609a str r2, [r3, #8]
|
|
BSP_GYRO_Init();
|
|
8002034: f7ff f90a bl 800124c <BSP_GYRO_Init>
|
|
|
|
BSP_GYRO_GetXYZ(pGyroDataXYZ);
|
|
8002038: 1d3b adds r3, r7, #4
|
|
800203a: 4618 mov r0, r3
|
|
800203c: f7ff f95e bl 80012fc <BSP_GYRO_GetXYZ>
|
|
printf("GYRO_X = %.2f \n", pGyroDataXYZ[0]);
|
|
8002040: 687b ldr r3, [r7, #4]
|
|
8002042: 4618 mov r0, r3
|
|
8002044: f7fe fa80 bl 8000548 <__aeabi_f2d>
|
|
8002048: 4602 mov r2, r0
|
|
800204a: 460b mov r3, r1
|
|
800204c: 480e ldr r0, [pc, #56] @ (8002088 <Gyro_Test+0x64>)
|
|
800204e: f005 ffbf bl 8007fd0 <iprintf>
|
|
printf("GYRO_Y = %.2f \n", pGyroDataXYZ[1]);
|
|
8002052: 68bb ldr r3, [r7, #8]
|
|
8002054: 4618 mov r0, r3
|
|
8002056: f7fe fa77 bl 8000548 <__aeabi_f2d>
|
|
800205a: 4602 mov r2, r0
|
|
800205c: 460b mov r3, r1
|
|
800205e: 480b ldr r0, [pc, #44] @ (800208c <Gyro_Test+0x68>)
|
|
8002060: f005 ffb6 bl 8007fd0 <iprintf>
|
|
printf("GYRO_Z = %.2f \n", pGyroDataXYZ[2]);
|
|
8002064: 68fb ldr r3, [r7, #12]
|
|
8002066: 4618 mov r0, r3
|
|
8002068: f7fe fa6e bl 8000548 <__aeabi_f2d>
|
|
800206c: 4602 mov r2, r0
|
|
800206e: 460b mov r3, r1
|
|
8002070: 4807 ldr r0, [pc, #28] @ (8002090 <Gyro_Test+0x6c>)
|
|
8002072: f005 ffad bl 8007fd0 <iprintf>
|
|
|
|
BSP_GYRO_DeInit();
|
|
8002076: f7ff f92d bl 80012d4 <BSP_GYRO_DeInit>
|
|
printf("\n*** End of Gyro Test ***\n\n");
|
|
800207a: 4806 ldr r0, [pc, #24] @ (8002094 <Gyro_Test+0x70>)
|
|
800207c: f006 f810 bl 80080a0 <puts>
|
|
return;
|
|
8002080: bf00 nop
|
|
}
|
|
8002082: 3710 adds r7, #16
|
|
8002084: 46bd mov sp, r7
|
|
8002086: bd80 pop {r7, pc}
|
|
8002088: 08009fe0 .word 0x08009fe0
|
|
800208c: 08009ff0 .word 0x08009ff0
|
|
8002090: 0800a000 .word 0x0800a000
|
|
8002094: 0800a010 .word 0x0800a010
|
|
|
|
08002098 <Humidity_Test>:
|
|
*/
|
|
|
|
#include "humidity.h"
|
|
|
|
void Humidity_Test(void)
|
|
{
|
|
8002098: b580 push {r7, lr}
|
|
800209a: b082 sub sp, #8
|
|
800209c: af00 add r7, sp, #0
|
|
float humidity_value;
|
|
BSP_HSENSOR_Init();
|
|
800209e: f7ff f945 bl 800132c <BSP_HSENSOR_Init>
|
|
humidity_value = BSP_HSENSOR_ReadHumidity();
|
|
80020a2: f7ff f963 bl 800136c <BSP_HSENSOR_ReadHumidity>
|
|
80020a6: ed87 0a01 vstr s0, [r7, #4]
|
|
printf("HUMIDITY is = %.2f %%\n", humidity_value);
|
|
80020aa: 6878 ldr r0, [r7, #4]
|
|
80020ac: f7fe fa4c bl 8000548 <__aeabi_f2d>
|
|
80020b0: 4602 mov r2, r0
|
|
80020b2: 460b mov r3, r1
|
|
80020b4: 4803 ldr r0, [pc, #12] @ (80020c4 <Humidity_Test+0x2c>)
|
|
80020b6: f005 ff8b bl 8007fd0 <iprintf>
|
|
}
|
|
80020ba: bf00 nop
|
|
80020bc: 3708 adds r7, #8
|
|
80020be: 46bd mov sp, r7
|
|
80020c0: bd80 pop {r7, pc}
|
|
80020c2: bf00 nop
|
|
80020c4: 0800a02c .word 0x0800a02c
|
|
|
|
080020c8 <Magneto_Test>:
|
|
*/
|
|
|
|
#include "magnetic.h"
|
|
|
|
void Magneto_Test(void)
|
|
{
|
|
80020c8: b580 push {r7, lr}
|
|
80020ca: b082 sub sp, #8
|
|
80020cc: af00 add r7, sp, #0
|
|
int16_t pDataXYZ[3] = {0};
|
|
80020ce: 463b mov r3, r7
|
|
80020d0: 2200 movs r2, #0
|
|
80020d2: 601a str r2, [r3, #0]
|
|
80020d4: 809a strh r2, [r3, #4]
|
|
BSP_MAGNETO_Init();
|
|
80020d6: f7ff f957 bl 8001388 <BSP_MAGNETO_Init>
|
|
|
|
BSP_MAGNETO_GetXYZ(pDataXYZ);
|
|
80020da: 463b mov r3, r7
|
|
80020dc: 4618 mov r0, r3
|
|
80020de: f7ff f993 bl 8001408 <BSP_MAGNETO_GetXYZ>
|
|
printf("MAGNETO_X = %d \n", pDataXYZ[0]);
|
|
80020e2: f9b7 3000 ldrsh.w r3, [r7]
|
|
80020e6: 4619 mov r1, r3
|
|
80020e8: 480b ldr r0, [pc, #44] @ (8002118 <Magneto_Test+0x50>)
|
|
80020ea: f005 ff71 bl 8007fd0 <iprintf>
|
|
printf("MAGNETO_Y = %d \n", pDataXYZ[1]);
|
|
80020ee: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
80020f2: 4619 mov r1, r3
|
|
80020f4: 4809 ldr r0, [pc, #36] @ (800211c <Magneto_Test+0x54>)
|
|
80020f6: f005 ff6b bl 8007fd0 <iprintf>
|
|
printf("MAGNETO_Z = %d \n", pDataXYZ[2]);
|
|
80020fa: f9b7 3004 ldrsh.w r3, [r7, #4]
|
|
80020fe: 4619 mov r1, r3
|
|
8002100: 4807 ldr r0, [pc, #28] @ (8002120 <Magneto_Test+0x58>)
|
|
8002102: f005 ff65 bl 8007fd0 <iprintf>
|
|
|
|
BSP_MAGNETO_DeInit();
|
|
8002106: f7ff f96b bl 80013e0 <BSP_MAGNETO_DeInit>
|
|
printf("\n*** End of Magneto Test ***\n\n");
|
|
800210a: 4806 ldr r0, [pc, #24] @ (8002124 <Magneto_Test+0x5c>)
|
|
800210c: f005 ffc8 bl 80080a0 <puts>
|
|
return;
|
|
8002110: bf00 nop
|
|
}
|
|
8002112: 3708 adds r7, #8
|
|
8002114: 46bd mov sp, r7
|
|
8002116: bd80 pop {r7, pc}
|
|
8002118: 0800a044 .word 0x0800a044
|
|
800211c: 0800a058 .word 0x0800a058
|
|
8002120: 0800a06c .word 0x0800a06c
|
|
8002124: 0800a080 .word 0x0800a080
|
|
|
|
08002128 <__io_putchar>:
|
|
/* USER CODE END PFP */
|
|
|
|
/* Private user code ---------------------------------------------------------*/
|
|
/* USER CODE BEGIN 0 */
|
|
int __io_putchar(int ch)
|
|
{
|
|
8002128: b580 push {r7, lr}
|
|
800212a: b082 sub sp, #8
|
|
800212c: af00 add r7, sp, #0
|
|
800212e: 6078 str r0, [r7, #4]
|
|
while(HAL_OK != HAL_UART_Transmit(&huart1, (uint8_t*)&ch, 1, 3000));
|
|
8002130: bf00 nop
|
|
8002132: 1d39 adds r1, r7, #4
|
|
8002134: f640 33b8 movw r3, #3000 @ 0xbb8
|
|
8002138: 2201 movs r2, #1
|
|
800213a: 4805 ldr r0, [pc, #20] @ (8002150 <__io_putchar+0x28>)
|
|
800213c: f004 fa29 bl 8006592 <HAL_UART_Transmit>
|
|
8002140: 4603 mov r3, r0
|
|
8002142: 2b00 cmp r3, #0
|
|
8002144: d1f5 bne.n 8002132 <__io_putchar+0xa>
|
|
return ch;
|
|
8002146: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002148: 4618 mov r0, r3
|
|
800214a: 3708 adds r7, #8
|
|
800214c: 46bd mov sp, r7
|
|
800214e: bd80 pop {r7, pc}
|
|
8002150: 20000454 .word 0x20000454
|
|
|
|
08002154 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8002154: b580 push {r7, lr}
|
|
8002156: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8002158: f001 f809 bl 800316e <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
800215c: f000 f822 bl 80021a4 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8002160: f000 f9ea bl 8002538 <MX_GPIO_Init>
|
|
MX_DFSDM1_Init();
|
|
8002164: f000 f880 bl 8002268 <MX_DFSDM1_Init>
|
|
MX_I2C2_Init();
|
|
8002168: f000 f8b6 bl 80022d8 <MX_I2C2_Init>
|
|
MX_QUADSPI_Init();
|
|
800216c: f000 f8f2 bl 8002354 <MX_QUADSPI_Init>
|
|
MX_SPI3_Init();
|
|
8002170: f000 f916 bl 80023a0 <MX_SPI3_Init>
|
|
MX_USART1_UART_Init();
|
|
8002174: f000 f952 bl 800241c <MX_USART1_UART_Init>
|
|
MX_USART3_UART_Init();
|
|
8002178: f000 f980 bl 800247c <MX_USART3_UART_Init>
|
|
MX_USB_OTG_FS_PCD_Init();
|
|
800217c: f000 f9ae bl 80024dc <MX_USB_OTG_FS_PCD_Init>
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
/* USER CODE END WHILE */
|
|
Temperature_Test();
|
|
8002180: f000 ffb2 bl 80030e8 <Temperature_Test>
|
|
Humidity_Test();
|
|
8002184: f7ff ff88 bl 8002098 <Humidity_Test>
|
|
Pressure_Test();
|
|
8002188: f000 fb8e bl 80028a8 <Pressure_Test>
|
|
Magneto_Test();
|
|
800218c: f7ff ff9c bl 80020c8 <Magneto_Test>
|
|
Gyro_Test();
|
|
8002190: f7ff ff48 bl 8002024 <Gyro_Test>
|
|
Accelero_Test();
|
|
8002194: f7ff ff20 bl 8001fd8 <Accelero_Test>
|
|
HAL_Delay(5000);
|
|
8002198: f241 3088 movw r0, #5000 @ 0x1388
|
|
800219c: f001 f85c bl 8003258 <HAL_Delay>
|
|
{
|
|
80021a0: bf00 nop
|
|
80021a2: e7ed b.n 8002180 <main+0x2c>
|
|
|
|
080021a4 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
80021a4: b580 push {r7, lr}
|
|
80021a6: b096 sub sp, #88 @ 0x58
|
|
80021a8: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
80021aa: f107 0314 add.w r3, r7, #20
|
|
80021ae: 2244 movs r2, #68 @ 0x44
|
|
80021b0: 2100 movs r1, #0
|
|
80021b2: 4618 mov r0, r3
|
|
80021b4: f006 f854 bl 8008260 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
80021b8: 463b mov r3, r7
|
|
80021ba: 2200 movs r2, #0
|
|
80021bc: 601a str r2, [r3, #0]
|
|
80021be: 605a str r2, [r3, #4]
|
|
80021c0: 609a str r2, [r3, #8]
|
|
80021c2: 60da str r2, [r3, #12]
|
|
80021c4: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
|
|
80021c6: f44f 7000 mov.w r0, #512 @ 0x200
|
|
80021ca: f002 fd03 bl 8004bd4 <HAL_PWREx_ControlVoltageScaling>
|
|
80021ce: 4603 mov r3, r0
|
|
80021d0: 2b00 cmp r3, #0
|
|
80021d2: d001 beq.n 80021d8 <SystemClock_Config+0x34>
|
|
{
|
|
Error_Handler();
|
|
80021d4: f000 fb62 bl 800289c <Error_Handler>
|
|
}
|
|
|
|
/** Configure LSE Drive Capability
|
|
*/
|
|
HAL_PWR_EnableBkUpAccess();
|
|
80021d8: f002 fcde bl 8004b98 <HAL_PWR_EnableBkUpAccess>
|
|
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
|
|
80021dc: 4b21 ldr r3, [pc, #132] @ (8002264 <SystemClock_Config+0xc0>)
|
|
80021de: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80021e2: 4a20 ldr r2, [pc, #128] @ (8002264 <SystemClock_Config+0xc0>)
|
|
80021e4: f023 0318 bic.w r3, r3, #24
|
|
80021e8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
|
|
80021ec: 2314 movs r3, #20
|
|
80021ee: 617b str r3, [r7, #20]
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
|
80021f0: 2301 movs r3, #1
|
|
80021f2: 61fb str r3, [r7, #28]
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
|
80021f4: 2301 movs r3, #1
|
|
80021f6: 62fb str r3, [r7, #44] @ 0x2c
|
|
RCC_OscInitStruct.MSICalibrationValue = 0;
|
|
80021f8: 2300 movs r3, #0
|
|
80021fa: 633b str r3, [r7, #48] @ 0x30
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
|
80021fc: 2360 movs r3, #96 @ 0x60
|
|
80021fe: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8002200: 2302 movs r3, #2
|
|
8002202: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
|
8002204: 2301 movs r3, #1
|
|
8002206: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLM = 1;
|
|
8002208: 2301 movs r3, #1
|
|
800220a: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLN = 40;
|
|
800220c: 2328 movs r3, #40 @ 0x28
|
|
800220e: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
|
8002210: 2307 movs r3, #7
|
|
8002212: 64fb str r3, [r7, #76] @ 0x4c
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
8002214: 2302 movs r3, #2
|
|
8002216: 653b str r3, [r7, #80] @ 0x50
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
8002218: 2302 movs r3, #2
|
|
800221a: 657b str r3, [r7, #84] @ 0x54
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
800221c: f107 0314 add.w r3, r7, #20
|
|
8002220: 4618 mov r0, r3
|
|
8002222: f002 fdf9 bl 8004e18 <HAL_RCC_OscConfig>
|
|
8002226: 4603 mov r3, r0
|
|
8002228: 2b00 cmp r3, #0
|
|
800222a: d001 beq.n 8002230 <SystemClock_Config+0x8c>
|
|
{
|
|
Error_Handler();
|
|
800222c: f000 fb36 bl 800289c <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8002230: 230f movs r3, #15
|
|
8002232: 603b str r3, [r7, #0]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8002234: 2303 movs r3, #3
|
|
8002236: 607b str r3, [r7, #4]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8002238: 2300 movs r3, #0
|
|
800223a: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
800223c: 2300 movs r3, #0
|
|
800223e: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8002240: 2300 movs r3, #0
|
|
8002242: 613b str r3, [r7, #16]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
|
8002244: 463b mov r3, r7
|
|
8002246: 2104 movs r1, #4
|
|
8002248: 4618 mov r0, r3
|
|
800224a: f003 f9c1 bl 80055d0 <HAL_RCC_ClockConfig>
|
|
800224e: 4603 mov r3, r0
|
|
8002250: 2b00 cmp r3, #0
|
|
8002252: d001 beq.n 8002258 <SystemClock_Config+0xb4>
|
|
{
|
|
Error_Handler();
|
|
8002254: f000 fb22 bl 800289c <Error_Handler>
|
|
}
|
|
|
|
/** Enable MSI Auto calibration
|
|
*/
|
|
HAL_RCCEx_EnableMSIPLLMode();
|
|
8002258: f003 fec8 bl 8005fec <HAL_RCCEx_EnableMSIPLLMode>
|
|
}
|
|
800225c: bf00 nop
|
|
800225e: 3758 adds r7, #88 @ 0x58
|
|
8002260: 46bd mov sp, r7
|
|
8002262: bd80 pop {r7, pc}
|
|
8002264: 40021000 .word 0x40021000
|
|
|
|
08002268 <MX_DFSDM1_Init>:
|
|
* @brief DFSDM1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_DFSDM1_Init(void)
|
|
{
|
|
8002268: b580 push {r7, lr}
|
|
800226a: af00 add r7, sp, #0
|
|
/* USER CODE END DFSDM1_Init 0 */
|
|
|
|
/* USER CODE BEGIN DFSDM1_Init 1 */
|
|
|
|
/* USER CODE END DFSDM1_Init 1 */
|
|
hdfsdm1_channel1.Instance = DFSDM1_Channel1;
|
|
800226c: 4b18 ldr r3, [pc, #96] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
800226e: 4a19 ldr r2, [pc, #100] @ (80022d4 <MX_DFSDM1_Init+0x6c>)
|
|
8002270: 601a str r2, [r3, #0]
|
|
hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;
|
|
8002272: 4b17 ldr r3, [pc, #92] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
8002274: 2201 movs r2, #1
|
|
8002276: 711a strb r2, [r3, #4]
|
|
hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;
|
|
8002278: 4b15 ldr r3, [pc, #84] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
800227a: 2200 movs r2, #0
|
|
800227c: 609a str r2, [r3, #8]
|
|
hdfsdm1_channel1.Init.OutputClock.Divider = 2;
|
|
800227e: 4b14 ldr r3, [pc, #80] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
8002280: 2202 movs r2, #2
|
|
8002282: 60da str r2, [r3, #12]
|
|
hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
|
|
8002284: 4b12 ldr r3, [pc, #72] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
8002286: 2200 movs r2, #0
|
|
8002288: 611a str r2, [r3, #16]
|
|
hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
|
|
800228a: 4b11 ldr r3, [pc, #68] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
800228c: 2200 movs r2, #0
|
|
800228e: 615a str r2, [r3, #20]
|
|
hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;
|
|
8002290: 4b0f ldr r3, [pc, #60] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
8002292: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8002296: 619a str r2, [r3, #24]
|
|
hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
|
|
8002298: 4b0d ldr r3, [pc, #52] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
800229a: 2200 movs r2, #0
|
|
800229c: 61da str r2, [r3, #28]
|
|
hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
|
|
800229e: 4b0c ldr r3, [pc, #48] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
80022a0: 2204 movs r2, #4
|
|
80022a2: 621a str r2, [r3, #32]
|
|
hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
|
|
80022a4: 4b0a ldr r3, [pc, #40] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
80022a6: 2200 movs r2, #0
|
|
80022a8: 625a str r2, [r3, #36] @ 0x24
|
|
hdfsdm1_channel1.Init.Awd.Oversampling = 1;
|
|
80022aa: 4b09 ldr r3, [pc, #36] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
80022ac: 2201 movs r2, #1
|
|
80022ae: 629a str r2, [r3, #40] @ 0x28
|
|
hdfsdm1_channel1.Init.Offset = 0;
|
|
80022b0: 4b07 ldr r3, [pc, #28] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
80022b2: 2200 movs r2, #0
|
|
80022b4: 62da str r2, [r3, #44] @ 0x2c
|
|
hdfsdm1_channel1.Init.RightBitShift = 0x00;
|
|
80022b6: 4b06 ldr r3, [pc, #24] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
80022b8: 2200 movs r2, #0
|
|
80022ba: 631a str r2, [r3, #48] @ 0x30
|
|
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)
|
|
80022bc: 4804 ldr r0, [pc, #16] @ (80022d0 <MX_DFSDM1_Init+0x68>)
|
|
80022be: f001 f901 bl 80034c4 <HAL_DFSDM_ChannelInit>
|
|
80022c2: 4603 mov r3, r0
|
|
80022c4: 2b00 cmp r3, #0
|
|
80022c6: d001 beq.n 80022cc <MX_DFSDM1_Init+0x64>
|
|
{
|
|
Error_Handler();
|
|
80022c8: f000 fae8 bl 800289c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN DFSDM1_Init 2 */
|
|
|
|
/* USER CODE END DFSDM1_Init 2 */
|
|
|
|
}
|
|
80022cc: bf00 nop
|
|
80022ce: bd80 pop {r7, pc}
|
|
80022d0: 20000320 .word 0x20000320
|
|
80022d4: 40016020 .word 0x40016020
|
|
|
|
080022d8 <MX_I2C2_Init>:
|
|
* @brief I2C2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C2_Init(void)
|
|
{
|
|
80022d8: b580 push {r7, lr}
|
|
80022da: af00 add r7, sp, #0
|
|
/* USER CODE END I2C2_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C2_Init 1 */
|
|
|
|
/* USER CODE END I2C2_Init 1 */
|
|
hi2c2.Instance = I2C2;
|
|
80022dc: 4b1b ldr r3, [pc, #108] @ (800234c <MX_I2C2_Init+0x74>)
|
|
80022de: 4a1c ldr r2, [pc, #112] @ (8002350 <MX_I2C2_Init+0x78>)
|
|
80022e0: 601a str r2, [r3, #0]
|
|
hi2c2.Init.Timing = 0x00000E14;
|
|
80022e2: 4b1a ldr r3, [pc, #104] @ (800234c <MX_I2C2_Init+0x74>)
|
|
80022e4: f640 6214 movw r2, #3604 @ 0xe14
|
|
80022e8: 605a str r2, [r3, #4]
|
|
hi2c2.Init.OwnAddress1 = 0;
|
|
80022ea: 4b18 ldr r3, [pc, #96] @ (800234c <MX_I2C2_Init+0x74>)
|
|
80022ec: 2200 movs r2, #0
|
|
80022ee: 609a str r2, [r3, #8]
|
|
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
80022f0: 4b16 ldr r3, [pc, #88] @ (800234c <MX_I2C2_Init+0x74>)
|
|
80022f2: 2201 movs r2, #1
|
|
80022f4: 60da str r2, [r3, #12]
|
|
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
80022f6: 4b15 ldr r3, [pc, #84] @ (800234c <MX_I2C2_Init+0x74>)
|
|
80022f8: 2200 movs r2, #0
|
|
80022fa: 611a str r2, [r3, #16]
|
|
hi2c2.Init.OwnAddress2 = 0;
|
|
80022fc: 4b13 ldr r3, [pc, #76] @ (800234c <MX_I2C2_Init+0x74>)
|
|
80022fe: 2200 movs r2, #0
|
|
8002300: 615a str r2, [r3, #20]
|
|
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
8002302: 4b12 ldr r3, [pc, #72] @ (800234c <MX_I2C2_Init+0x74>)
|
|
8002304: 2200 movs r2, #0
|
|
8002306: 619a str r2, [r3, #24]
|
|
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8002308: 4b10 ldr r3, [pc, #64] @ (800234c <MX_I2C2_Init+0x74>)
|
|
800230a: 2200 movs r2, #0
|
|
800230c: 61da str r2, [r3, #28]
|
|
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
800230e: 4b0f ldr r3, [pc, #60] @ (800234c <MX_I2C2_Init+0x74>)
|
|
8002310: 2200 movs r2, #0
|
|
8002312: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
|
|
8002314: 480d ldr r0, [pc, #52] @ (800234c <MX_I2C2_Init+0x74>)
|
|
8002316: f001 fcba bl 8003c8e <HAL_I2C_Init>
|
|
800231a: 4603 mov r3, r0
|
|
800231c: 2b00 cmp r3, #0
|
|
800231e: d001 beq.n 8002324 <MX_I2C2_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8002320: f000 fabc bl 800289c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
8002324: 2100 movs r1, #0
|
|
8002326: 4809 ldr r0, [pc, #36] @ (800234c <MX_I2C2_Init+0x74>)
|
|
8002328: f002 fa6c bl 8004804 <HAL_I2CEx_ConfigAnalogFilter>
|
|
800232c: 4603 mov r3, r0
|
|
800232e: 2b00 cmp r3, #0
|
|
8002330: d001 beq.n 8002336 <MX_I2C2_Init+0x5e>
|
|
{
|
|
Error_Handler();
|
|
8002332: f000 fab3 bl 800289c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
|
|
8002336: 2100 movs r1, #0
|
|
8002338: 4804 ldr r0, [pc, #16] @ (800234c <MX_I2C2_Init+0x74>)
|
|
800233a: f002 faae bl 800489a <HAL_I2CEx_ConfigDigitalFilter>
|
|
800233e: 4603 mov r3, r0
|
|
8002340: 2b00 cmp r3, #0
|
|
8002342: d001 beq.n 8002348 <MX_I2C2_Init+0x70>
|
|
{
|
|
Error_Handler();
|
|
8002344: f000 faaa bl 800289c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C2_Init 2 */
|
|
|
|
/* USER CODE END I2C2_Init 2 */
|
|
|
|
}
|
|
8002348: bf00 nop
|
|
800234a: bd80 pop {r7, pc}
|
|
800234c: 20000358 .word 0x20000358
|
|
8002350: 40005800 .word 0x40005800
|
|
|
|
08002354 <MX_QUADSPI_Init>:
|
|
* @brief QUADSPI Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_QUADSPI_Init(void)
|
|
{
|
|
8002354: b580 push {r7, lr}
|
|
8002356: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN QUADSPI_Init 1 */
|
|
|
|
/* USER CODE END QUADSPI_Init 1 */
|
|
/* QUADSPI parameter configuration*/
|
|
hqspi.Instance = QUADSPI;
|
|
8002358: 4b0f ldr r3, [pc, #60] @ (8002398 <MX_QUADSPI_Init+0x44>)
|
|
800235a: 4a10 ldr r2, [pc, #64] @ (800239c <MX_QUADSPI_Init+0x48>)
|
|
800235c: 601a str r2, [r3, #0]
|
|
hqspi.Init.ClockPrescaler = 2;
|
|
800235e: 4b0e ldr r3, [pc, #56] @ (8002398 <MX_QUADSPI_Init+0x44>)
|
|
8002360: 2202 movs r2, #2
|
|
8002362: 605a str r2, [r3, #4]
|
|
hqspi.Init.FifoThreshold = 4;
|
|
8002364: 4b0c ldr r3, [pc, #48] @ (8002398 <MX_QUADSPI_Init+0x44>)
|
|
8002366: 2204 movs r2, #4
|
|
8002368: 609a str r2, [r3, #8]
|
|
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
|
|
800236a: 4b0b ldr r3, [pc, #44] @ (8002398 <MX_QUADSPI_Init+0x44>)
|
|
800236c: 2210 movs r2, #16
|
|
800236e: 60da str r2, [r3, #12]
|
|
hqspi.Init.FlashSize = 23;
|
|
8002370: 4b09 ldr r3, [pc, #36] @ (8002398 <MX_QUADSPI_Init+0x44>)
|
|
8002372: 2217 movs r2, #23
|
|
8002374: 611a str r2, [r3, #16]
|
|
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
|
|
8002376: 4b08 ldr r3, [pc, #32] @ (8002398 <MX_QUADSPI_Init+0x44>)
|
|
8002378: 2200 movs r2, #0
|
|
800237a: 615a str r2, [r3, #20]
|
|
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
|
|
800237c: 4b06 ldr r3, [pc, #24] @ (8002398 <MX_QUADSPI_Init+0x44>)
|
|
800237e: 2200 movs r2, #0
|
|
8002380: 619a str r2, [r3, #24]
|
|
if (HAL_QSPI_Init(&hqspi) != HAL_OK)
|
|
8002382: 4805 ldr r0, [pc, #20] @ (8002398 <MX_QUADSPI_Init+0x44>)
|
|
8002384: f002 fc8c bl 8004ca0 <HAL_QSPI_Init>
|
|
8002388: 4603 mov r3, r0
|
|
800238a: 2b00 cmp r3, #0
|
|
800238c: d001 beq.n 8002392 <MX_QUADSPI_Init+0x3e>
|
|
{
|
|
Error_Handler();
|
|
800238e: f000 fa85 bl 800289c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN QUADSPI_Init 2 */
|
|
|
|
/* USER CODE END QUADSPI_Init 2 */
|
|
|
|
}
|
|
8002392: bf00 nop
|
|
8002394: bd80 pop {r7, pc}
|
|
8002396: bf00 nop
|
|
8002398: 200003ac .word 0x200003ac
|
|
800239c: a0001000 .word 0xa0001000
|
|
|
|
080023a0 <MX_SPI3_Init>:
|
|
* @brief SPI3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_SPI3_Init(void)
|
|
{
|
|
80023a0: b580 push {r7, lr}
|
|
80023a2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN SPI3_Init 1 */
|
|
|
|
/* USER CODE END SPI3_Init 1 */
|
|
/* SPI3 parameter configuration*/
|
|
hspi3.Instance = SPI3;
|
|
80023a4: 4b1b ldr r3, [pc, #108] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023a6: 4a1c ldr r2, [pc, #112] @ (8002418 <MX_SPI3_Init+0x78>)
|
|
80023a8: 601a str r2, [r3, #0]
|
|
hspi3.Init.Mode = SPI_MODE_MASTER;
|
|
80023aa: 4b1a ldr r3, [pc, #104] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023ac: f44f 7282 mov.w r2, #260 @ 0x104
|
|
80023b0: 605a str r2, [r3, #4]
|
|
hspi3.Init.Direction = SPI_DIRECTION_2LINES;
|
|
80023b2: 4b18 ldr r3, [pc, #96] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023b4: 2200 movs r2, #0
|
|
80023b6: 609a str r2, [r3, #8]
|
|
hspi3.Init.DataSize = SPI_DATASIZE_4BIT;
|
|
80023b8: 4b16 ldr r3, [pc, #88] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023ba: f44f 7240 mov.w r2, #768 @ 0x300
|
|
80023be: 60da str r2, [r3, #12]
|
|
hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
80023c0: 4b14 ldr r3, [pc, #80] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023c2: 2200 movs r2, #0
|
|
80023c4: 611a str r2, [r3, #16]
|
|
hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
80023c6: 4b13 ldr r3, [pc, #76] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023c8: 2200 movs r2, #0
|
|
80023ca: 615a str r2, [r3, #20]
|
|
hspi3.Init.NSS = SPI_NSS_SOFT;
|
|
80023cc: 4b11 ldr r3, [pc, #68] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023ce: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80023d2: 619a str r2, [r3, #24]
|
|
hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
80023d4: 4b0f ldr r3, [pc, #60] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023d6: 2200 movs r2, #0
|
|
80023d8: 61da str r2, [r3, #28]
|
|
hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
80023da: 4b0e ldr r3, [pc, #56] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023dc: 2200 movs r2, #0
|
|
80023de: 621a str r2, [r3, #32]
|
|
hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
80023e0: 4b0c ldr r3, [pc, #48] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023e2: 2200 movs r2, #0
|
|
80023e4: 625a str r2, [r3, #36] @ 0x24
|
|
hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
80023e6: 4b0b ldr r3, [pc, #44] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023e8: 2200 movs r2, #0
|
|
80023ea: 629a str r2, [r3, #40] @ 0x28
|
|
hspi3.Init.CRCPolynomial = 7;
|
|
80023ec: 4b09 ldr r3, [pc, #36] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023ee: 2207 movs r2, #7
|
|
80023f0: 62da str r2, [r3, #44] @ 0x2c
|
|
hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
|
|
80023f2: 4b08 ldr r3, [pc, #32] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023f4: 2200 movs r2, #0
|
|
80023f6: 631a str r2, [r3, #48] @ 0x30
|
|
hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
|
80023f8: 4b06 ldr r3, [pc, #24] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
80023fa: 2208 movs r2, #8
|
|
80023fc: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_SPI_Init(&hspi3) != HAL_OK)
|
|
80023fe: 4805 ldr r0, [pc, #20] @ (8002414 <MX_SPI3_Init+0x74>)
|
|
8002400: f003 ffd6 bl 80063b0 <HAL_SPI_Init>
|
|
8002404: 4603 mov r3, r0
|
|
8002406: 2b00 cmp r3, #0
|
|
8002408: d001 beq.n 800240e <MX_SPI3_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
800240a: f000 fa47 bl 800289c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SPI3_Init 2 */
|
|
|
|
/* USER CODE END SPI3_Init 2 */
|
|
|
|
}
|
|
800240e: bf00 nop
|
|
8002410: bd80 pop {r7, pc}
|
|
8002412: bf00 nop
|
|
8002414: 200003f0 .word 0x200003f0
|
|
8002418: 40003c00 .word 0x40003c00
|
|
|
|
0800241c <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
800241c: b580 push {r7, lr}
|
|
800241e: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8002420: 4b14 ldr r3, [pc, #80] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
8002422: 4a15 ldr r2, [pc, #84] @ (8002478 <MX_USART1_UART_Init+0x5c>)
|
|
8002424: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8002426: 4b13 ldr r3, [pc, #76] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
8002428: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
800242c: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800242e: 4b11 ldr r3, [pc, #68] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
8002430: 2200 movs r2, #0
|
|
8002432: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8002434: 4b0f ldr r3, [pc, #60] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
8002436: 2200 movs r2, #0
|
|
8002438: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
800243a: 4b0e ldr r3, [pc, #56] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
800243c: 2200 movs r2, #0
|
|
800243e: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8002440: 4b0c ldr r3, [pc, #48] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
8002442: 220c movs r2, #12
|
|
8002444: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8002446: 4b0b ldr r3, [pc, #44] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
8002448: 2200 movs r2, #0
|
|
800244a: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
800244c: 4b09 ldr r3, [pc, #36] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
800244e: 2200 movs r2, #0
|
|
8002450: 61da str r2, [r3, #28]
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8002452: 4b08 ldr r3, [pc, #32] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
8002454: 2200 movs r2, #0
|
|
8002456: 621a str r2, [r3, #32]
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8002458: 4b06 ldr r3, [pc, #24] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
800245a: 2200 movs r2, #0
|
|
800245c: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
800245e: 4805 ldr r0, [pc, #20] @ (8002474 <MX_USART1_UART_Init+0x58>)
|
|
8002460: f004 f849 bl 80064f6 <HAL_UART_Init>
|
|
8002464: 4603 mov r3, r0
|
|
8002466: 2b00 cmp r3, #0
|
|
8002468: d001 beq.n 800246e <MX_USART1_UART_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
800246a: f000 fa17 bl 800289c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
800246e: bf00 nop
|
|
8002470: bd80 pop {r7, pc}
|
|
8002472: bf00 nop
|
|
8002474: 20000454 .word 0x20000454
|
|
8002478: 40013800 .word 0x40013800
|
|
|
|
0800247c <MX_USART3_UART_Init>:
|
|
* @brief USART3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART3_UART_Init(void)
|
|
{
|
|
800247c: b580 push {r7, lr}
|
|
800247e: af00 add r7, sp, #0
|
|
/* USER CODE END USART3_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART3_Init 1 */
|
|
|
|
/* USER CODE END USART3_Init 1 */
|
|
huart3.Instance = USART3;
|
|
8002480: 4b14 ldr r3, [pc, #80] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
8002482: 4a15 ldr r2, [pc, #84] @ (80024d8 <MX_USART3_UART_Init+0x5c>)
|
|
8002484: 601a str r2, [r3, #0]
|
|
huart3.Init.BaudRate = 115200;
|
|
8002486: 4b13 ldr r3, [pc, #76] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
8002488: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
800248c: 605a str r2, [r3, #4]
|
|
huart3.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800248e: 4b11 ldr r3, [pc, #68] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
8002490: 2200 movs r2, #0
|
|
8002492: 609a str r2, [r3, #8]
|
|
huart3.Init.StopBits = UART_STOPBITS_1;
|
|
8002494: 4b0f ldr r3, [pc, #60] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
8002496: 2200 movs r2, #0
|
|
8002498: 60da str r2, [r3, #12]
|
|
huart3.Init.Parity = UART_PARITY_NONE;
|
|
800249a: 4b0e ldr r3, [pc, #56] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
800249c: 2200 movs r2, #0
|
|
800249e: 611a str r2, [r3, #16]
|
|
huart3.Init.Mode = UART_MODE_TX_RX;
|
|
80024a0: 4b0c ldr r3, [pc, #48] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
80024a2: 220c movs r2, #12
|
|
80024a4: 615a str r2, [r3, #20]
|
|
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80024a6: 4b0b ldr r3, [pc, #44] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
80024a8: 2200 movs r2, #0
|
|
80024aa: 619a str r2, [r3, #24]
|
|
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80024ac: 4b09 ldr r3, [pc, #36] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
80024ae: 2200 movs r2, #0
|
|
80024b0: 61da str r2, [r3, #28]
|
|
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
80024b2: 4b08 ldr r3, [pc, #32] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
80024b4: 2200 movs r2, #0
|
|
80024b6: 621a str r2, [r3, #32]
|
|
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
80024b8: 4b06 ldr r3, [pc, #24] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
80024ba: 2200 movs r2, #0
|
|
80024bc: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_UART_Init(&huart3) != HAL_OK)
|
|
80024be: 4805 ldr r0, [pc, #20] @ (80024d4 <MX_USART3_UART_Init+0x58>)
|
|
80024c0: f004 f819 bl 80064f6 <HAL_UART_Init>
|
|
80024c4: 4603 mov r3, r0
|
|
80024c6: 2b00 cmp r3, #0
|
|
80024c8: d001 beq.n 80024ce <MX_USART3_UART_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
80024ca: f000 f9e7 bl 800289c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART3_Init 2 */
|
|
|
|
/* USER CODE END USART3_Init 2 */
|
|
|
|
}
|
|
80024ce: bf00 nop
|
|
80024d0: bd80 pop {r7, pc}
|
|
80024d2: bf00 nop
|
|
80024d4: 200004dc .word 0x200004dc
|
|
80024d8: 40004800 .word 0x40004800
|
|
|
|
080024dc <MX_USB_OTG_FS_PCD_Init>:
|
|
* @brief USB_OTG_FS Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USB_OTG_FS_PCD_Init(void)
|
|
{
|
|
80024dc: b580 push {r7, lr}
|
|
80024de: af00 add r7, sp, #0
|
|
/* USER CODE END USB_OTG_FS_Init 0 */
|
|
|
|
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
|
|
|
|
/* USER CODE END USB_OTG_FS_Init 1 */
|
|
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
|
80024e0: 4b14 ldr r3, [pc, #80] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
80024e2: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
80024e6: 601a str r2, [r3, #0]
|
|
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
|
|
80024e8: 4b12 ldr r3, [pc, #72] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
80024ea: 2206 movs r2, #6
|
|
80024ec: 711a strb r2, [r3, #4]
|
|
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
|
|
80024ee: 4b11 ldr r3, [pc, #68] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
80024f0: 2202 movs r2, #2
|
|
80024f2: 71da strb r2, [r3, #7]
|
|
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
|
80024f4: 4b0f ldr r3, [pc, #60] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
80024f6: 2202 movs r2, #2
|
|
80024f8: 725a strb r2, [r3, #9]
|
|
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
|
|
80024fa: 4b0e ldr r3, [pc, #56] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
80024fc: 2200 movs r2, #0
|
|
80024fe: 729a strb r2, [r3, #10]
|
|
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
|
8002500: 4b0c ldr r3, [pc, #48] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002502: 2200 movs r2, #0
|
|
8002504: 72da strb r2, [r3, #11]
|
|
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
|
8002506: 4b0b ldr r3, [pc, #44] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002508: 2200 movs r2, #0
|
|
800250a: 731a strb r2, [r3, #12]
|
|
hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
|
|
800250c: 4b09 ldr r3, [pc, #36] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
800250e: 2200 movs r2, #0
|
|
8002510: 735a strb r2, [r3, #13]
|
|
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
|
8002512: 4b08 ldr r3, [pc, #32] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002514: 2200 movs r2, #0
|
|
8002516: 73da strb r2, [r3, #15]
|
|
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
|
8002518: 4b06 ldr r3, [pc, #24] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
800251a: 2200 movs r2, #0
|
|
800251c: 739a strb r2, [r3, #14]
|
|
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
|
|
800251e: 4805 ldr r0, [pc, #20] @ (8002534 <MX_USB_OTG_FS_PCD_Init+0x58>)
|
|
8002520: f002 fa07 bl 8004932 <HAL_PCD_Init>
|
|
8002524: 4603 mov r3, r0
|
|
8002526: 2b00 cmp r3, #0
|
|
8002528: d001 beq.n 800252e <MX_USB_OTG_FS_PCD_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
800252a: f000 f9b7 bl 800289c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
|
|
|
|
/* USER CODE END USB_OTG_FS_Init 2 */
|
|
|
|
}
|
|
800252e: bf00 nop
|
|
8002530: bd80 pop {r7, pc}
|
|
8002532: bf00 nop
|
|
8002534: 20000564 .word 0x20000564
|
|
|
|
08002538 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8002538: b580 push {r7, lr}
|
|
800253a: b08a sub sp, #40 @ 0x28
|
|
800253c: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800253e: f107 0314 add.w r3, r7, #20
|
|
8002542: 2200 movs r2, #0
|
|
8002544: 601a str r2, [r3, #0]
|
|
8002546: 605a str r2, [r3, #4]
|
|
8002548: 609a str r2, [r3, #8]
|
|
800254a: 60da str r2, [r3, #12]
|
|
800254c: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
800254e: 4bbd ldr r3, [pc, #756] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
8002550: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002552: 4abc ldr r2, [pc, #752] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
8002554: f043 0310 orr.w r3, r3, #16
|
|
8002558: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800255a: 4bba ldr r3, [pc, #744] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
800255c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800255e: f003 0310 and.w r3, r3, #16
|
|
8002562: 613b str r3, [r7, #16]
|
|
8002564: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8002566: 4bb7 ldr r3, [pc, #732] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
8002568: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800256a: 4ab6 ldr r2, [pc, #728] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
800256c: f043 0304 orr.w r3, r3, #4
|
|
8002570: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002572: 4bb4 ldr r3, [pc, #720] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
8002574: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002576: f003 0304 and.w r3, r3, #4
|
|
800257a: 60fb str r3, [r7, #12]
|
|
800257c: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800257e: 4bb1 ldr r3, [pc, #708] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
8002580: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002582: 4ab0 ldr r2, [pc, #704] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
8002584: f043 0301 orr.w r3, r3, #1
|
|
8002588: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800258a: 4bae ldr r3, [pc, #696] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
800258c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800258e: f003 0301 and.w r3, r3, #1
|
|
8002592: 60bb str r3, [r7, #8]
|
|
8002594: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8002596: 4bab ldr r3, [pc, #684] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
8002598: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800259a: 4aaa ldr r2, [pc, #680] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
800259c: f043 0302 orr.w r3, r3, #2
|
|
80025a0: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80025a2: 4ba8 ldr r3, [pc, #672] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
80025a4: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80025a6: f003 0302 and.w r3, r3, #2
|
|
80025aa: 607b str r3, [r7, #4]
|
|
80025ac: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
80025ae: 4ba5 ldr r3, [pc, #660] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
80025b0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80025b2: 4aa4 ldr r2, [pc, #656] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
80025b4: f043 0308 orr.w r3, r3, #8
|
|
80025b8: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80025ba: 4ba2 ldr r3, [pc, #648] @ (8002844 <MX_GPIO_Init+0x30c>)
|
|
80025bc: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80025be: f003 0308 and.w r3, r3, #8
|
|
80025c2: 603b str r3, [r7, #0]
|
|
80025c4: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET);
|
|
80025c6: 2200 movs r2, #0
|
|
80025c8: f44f 718a mov.w r1, #276 @ 0x114
|
|
80025cc: 489e ldr r0, [pc, #632] @ (8002848 <MX_GPIO_Init+0x310>)
|
|
80025ce: f001 fb23 bl 8003c18 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET);
|
|
80025d2: 2200 movs r2, #0
|
|
80025d4: f248 1104 movw r1, #33028 @ 0x8104
|
|
80025d8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80025dc: f001 fb1c bl 8003c18 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
|
|
80025e0: 2200 movs r2, #0
|
|
80025e2: f24f 0114 movw r1, #61460 @ 0xf014
|
|
80025e6: 4899 ldr r0, [pc, #612] @ (800284c <MX_GPIO_Init+0x314>)
|
|
80025e8: f001 fb16 bl 8003c18 <HAL_GPIO_WritePin>
|
|
|SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET);
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET);
|
|
80025ec: 2200 movs r2, #0
|
|
80025ee: f241 0181 movw r1, #4225 @ 0x1081
|
|
80025f2: 4897 ldr r0, [pc, #604] @ (8002850 <MX_GPIO_Init+0x318>)
|
|
80025f4: f001 fb10 bl 8003c18 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET);
|
|
80025f8: 2201 movs r2, #1
|
|
80025fa: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
80025fe: 4894 ldr r0, [pc, #592] @ (8002850 <MX_GPIO_Init+0x318>)
|
|
8002600: f001 fb0a bl 8003c18 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET);
|
|
8002604: 2200 movs r2, #0
|
|
8002606: f44f 7110 mov.w r1, #576 @ 0x240
|
|
800260a: 4892 ldr r0, [pc, #584] @ (8002854 <MX_GPIO_Init+0x31c>)
|
|
800260c: f001 fb04 bl 8003c18 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET);
|
|
8002610: 2201 movs r2, #1
|
|
8002612: 2120 movs r1, #32
|
|
8002614: 488d ldr r0, [pc, #564] @ (800284c <MX_GPIO_Init+0x314>)
|
|
8002616: f001 faff bl 8003c18 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET);
|
|
800261a: 2201 movs r2, #1
|
|
800261c: 2101 movs r1, #1
|
|
800261e: 488a ldr r0, [pc, #552] @ (8002848 <MX_GPIO_Init+0x310>)
|
|
8002620: f001 fafa bl 8003c18 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */
|
|
GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin;
|
|
8002624: f240 1315 movw r3, #277 @ 0x115
|
|
8002628: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
800262a: 2301 movs r3, #1
|
|
800262c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800262e: 2300 movs r3, #0
|
|
8002630: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8002632: 2300 movs r3, #0
|
|
8002634: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8002636: f107 0314 add.w r3, r7, #20
|
|
800263a: 4619 mov r1, r3
|
|
800263c: 4882 ldr r0, [pc, #520] @ (8002848 <MX_GPIO_Init+0x310>)
|
|
800263e: f001 f84d bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */
|
|
GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin;
|
|
8002642: 236a movs r3, #106 @ 0x6a
|
|
8002644: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
8002646: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
800264a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800264c: 2300 movs r3, #0
|
|
800264e: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8002650: f107 0314 add.w r3, r7, #20
|
|
8002654: 4619 mov r1, r3
|
|
8002656: 487c ldr r0, [pc, #496] @ (8002848 <MX_GPIO_Init+0x310>)
|
|
8002658: f001 f840 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : BUTTON_EXTI13_Pin */
|
|
GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin;
|
|
800265c: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8002660: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
8002662: f44f 1304 mov.w r3, #2162688 @ 0x210000
|
|
8002666: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002668: 2300 movs r3, #0
|
|
800266a: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct);
|
|
800266c: f107 0314 add.w r3, r7, #20
|
|
8002670: 4619 mov r1, r3
|
|
8002672: 4878 ldr r0, [pc, #480] @ (8002854 <MX_GPIO_Init+0x31c>)
|
|
8002674: f001 f832 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin
|
|
ARD_A1_Pin ARD_A0_Pin */
|
|
GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin
|
|
8002678: 233f movs r3, #63 @ 0x3f
|
|
800267a: 617b str r3, [r7, #20]
|
|
|ARD_A1_Pin|ARD_A0_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
|
|
800267c: 230b movs r3, #11
|
|
800267e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002680: 2300 movs r3, #0
|
|
8002682: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8002684: f107 0314 add.w r3, r7, #20
|
|
8002688: 4619 mov r1, r3
|
|
800268a: 4872 ldr r0, [pc, #456] @ (8002854 <MX_GPIO_Init+0x31c>)
|
|
800268c: f001 f826 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin;
|
|
8002690: 2303 movs r3, #3
|
|
8002692: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002694: 2302 movs r3, #2
|
|
8002696: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002698: 2300 movs r3, #0
|
|
800269a: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800269c: 2303 movs r3, #3
|
|
800269e: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
|
|
80026a0: 2308 movs r3, #8
|
|
80026a2: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80026a4: f107 0314 add.w r3, r7, #20
|
|
80026a8: 4619 mov r1, r3
|
|
80026aa: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80026ae: f001 f815 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D10_Pin SPBTLE_RF_RST_Pin ARD_D9_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin;
|
|
80026b2: f248 1304 movw r3, #33028 @ 0x8104
|
|
80026b6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80026b8: 2301 movs r3, #1
|
|
80026ba: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80026bc: 2300 movs r3, #0
|
|
80026be: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80026c0: 2300 movs r3, #0
|
|
80026c2: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80026c4: f107 0314 add.w r3, r7, #20
|
|
80026c8: 4619 mov r1, r3
|
|
80026ca: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80026ce: f001 f805 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ARD_D4_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D4_Pin;
|
|
80026d2: 2308 movs r3, #8
|
|
80026d4: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80026d6: 2302 movs r3, #2
|
|
80026d8: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80026da: 2300 movs r3, #0
|
|
80026dc: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80026de: 2300 movs r3, #0
|
|
80026e0: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
80026e2: 2301 movs r3, #1
|
|
80026e4: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct);
|
|
80026e6: f107 0314 add.w r3, r7, #20
|
|
80026ea: 4619 mov r1, r3
|
|
80026ec: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80026f0: f000 fff4 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ARD_D7_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D7_Pin;
|
|
80026f4: 2310 movs r3, #16
|
|
80026f6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
|
|
80026f8: 230b movs r3, #11
|
|
80026fa: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80026fc: 2300 movs r3, #0
|
|
80026fe: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct);
|
|
8002700: f107 0314 add.w r3, r7, #20
|
|
8002704: 4619 mov r1, r3
|
|
8002706: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800270a: f000 ffe7 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D13_Pin ARD_D12_Pin ARD_D11_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D13_Pin|ARD_D12_Pin|ARD_D11_Pin;
|
|
800270e: 23e0 movs r3, #224 @ 0xe0
|
|
8002710: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002712: 2302 movs r3, #2
|
|
8002714: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002716: 2300 movs r3, #0
|
|
8002718: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800271a: 2303 movs r3, #3
|
|
800271c: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
|
|
800271e: 2305 movs r3, #5
|
|
8002720: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002722: f107 0314 add.w r3, r7, #20
|
|
8002726: 4619 mov r1, r3
|
|
8002728: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800272c: f000 ffd6 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ARD_D3_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D3_Pin;
|
|
8002730: 2301 movs r3, #1
|
|
8002732: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
8002734: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
8002738: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800273a: 2300 movs r3, #0
|
|
800273c: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct);
|
|
800273e: f107 0314 add.w r3, r7, #20
|
|
8002742: 4619 mov r1, r3
|
|
8002744: 4841 ldr r0, [pc, #260] @ (800284c <MX_GPIO_Init+0x314>)
|
|
8002746: f000 ffc9 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ARD_D6_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D6_Pin;
|
|
800274a: 2302 movs r3, #2
|
|
800274c: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
|
|
800274e: 230b movs r3, #11
|
|
8002750: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002752: 2300 movs r3, #0
|
|
8002754: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct);
|
|
8002756: f107 0314 add.w r3, r7, #20
|
|
800275a: 4619 mov r1, r3
|
|
800275c: 483b ldr r0, [pc, #236] @ (800284c <MX_GPIO_Init+0x314>)
|
|
800275e: f000 ffbd bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin
|
|
SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
|
|
8002762: f24f 0334 movw r3, #61492 @ 0xf034
|
|
8002766: 617b str r3, [r7, #20]
|
|
|SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8002768: 2301 movs r3, #1
|
|
800276a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800276c: 2300 movs r3, #0
|
|
800276e: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8002770: 2300 movs r3, #0
|
|
8002772: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8002774: f107 0314 add.w r3, r7, #20
|
|
8002778: 4619 mov r1, r3
|
|
800277a: 4834 ldr r0, [pc, #208] @ (800284c <MX_GPIO_Init+0x314>)
|
|
800277c: f000 ffae bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin
|
|
PMOD_IRQ_EXTI12_Pin */
|
|
GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin
|
|
8002780: f64c 4304 movw r3, #52228 @ 0xcc04
|
|
8002784: 617b str r3, [r7, #20]
|
|
|PMOD_IRQ_EXTI12_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
8002786: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
800278a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800278c: 2300 movs r3, #0
|
|
800278e: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8002790: f107 0314 add.w r3, r7, #20
|
|
8002794: 4619 mov r1, r3
|
|
8002796: 482e ldr r0, [pc, #184] @ (8002850 <MX_GPIO_Init+0x318>)
|
|
8002798: f000 ffa0 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */
|
|
GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin;
|
|
800279c: f243 0381 movw r3, #12417 @ 0x3081
|
|
80027a0: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80027a2: 2301 movs r3, #1
|
|
80027a4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80027a6: 2300 movs r3, #0
|
|
80027a8: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80027aa: 2300 movs r3, #0
|
|
80027ac: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
80027ae: f107 0314 add.w r3, r7, #20
|
|
80027b2: 4619 mov r1, r3
|
|
80027b4: 4826 ldr r0, [pc, #152] @ (8002850 <MX_GPIO_Init+0x318>)
|
|
80027b6: f000 ff91 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */
|
|
GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin;
|
|
80027ba: f44f 7310 mov.w r3, #576 @ 0x240
|
|
80027be: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80027c0: 2301 movs r3, #1
|
|
80027c2: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80027c4: 2300 movs r3, #0
|
|
80027c6: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80027c8: 2300 movs r3, #0
|
|
80027ca: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80027cc: f107 0314 add.w r3, r7, #20
|
|
80027d0: 4619 mov r1, r3
|
|
80027d2: 4820 ldr r0, [pc, #128] @ (8002854 <MX_GPIO_Init+0x31c>)
|
|
80027d4: f000 ff82 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */
|
|
GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin;
|
|
80027d8: f44f 73c0 mov.w r3, #384 @ 0x180
|
|
80027dc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
80027de: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
80027e2: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80027e4: 2300 movs r3, #0
|
|
80027e6: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80027e8: f107 0314 add.w r3, r7, #20
|
|
80027ec: 4619 mov r1, r3
|
|
80027ee: 4819 ldr r0, [pc, #100] @ (8002854 <MX_GPIO_Init+0x31c>)
|
|
80027f0: f000 ff74 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PMOD_SPI2_SCK_Pin */
|
|
GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin;
|
|
80027f4: 2302 movs r3, #2
|
|
80027f6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80027f8: 2302 movs r3, #2
|
|
80027fa: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80027fc: 2300 movs r3, #0
|
|
80027fe: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002800: 2303 movs r3, #3
|
|
8002802: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
8002804: 2305 movs r3, #5
|
|
8002806: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct);
|
|
8002808: f107 0314 add.w r3, r7, #20
|
|
800280c: 4619 mov r1, r3
|
|
800280e: 4810 ldr r0, [pc, #64] @ (8002850 <MX_GPIO_Init+0x318>)
|
|
8002810: f000 ff64 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */
|
|
GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin;
|
|
8002814: 2378 movs r3, #120 @ 0x78
|
|
8002816: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002818: 2302 movs r3, #2
|
|
800281a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800281c: 2300 movs r3, #0
|
|
800281e: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002820: 2303 movs r3, #3
|
|
8002822: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
8002824: 2307 movs r3, #7
|
|
8002826: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8002828: f107 0314 add.w r3, r7, #20
|
|
800282c: 4619 mov r1, r3
|
|
800282e: 4808 ldr r0, [pc, #32] @ (8002850 <MX_GPIO_Init+0x318>)
|
|
8002830: f000 ff54 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */
|
|
GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin;
|
|
8002834: f44f 7340 mov.w r3, #768 @ 0x300
|
|
8002838: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
800283a: 2312 movs r3, #18
|
|
800283c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800283e: 2300 movs r3, #0
|
|
8002840: e00a b.n 8002858 <MX_GPIO_Init+0x320>
|
|
8002842: bf00 nop
|
|
8002844: 40021000 .word 0x40021000
|
|
8002848: 48001000 .word 0x48001000
|
|
800284c: 48000400 .word 0x48000400
|
|
8002850: 48000c00 .word 0x48000c00
|
|
8002854: 48000800 .word 0x48000800
|
|
8002858: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800285a: 2303 movs r3, #3
|
|
800285c: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
800285e: 2304 movs r3, #4
|
|
8002860: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8002862: f107 0314 add.w r3, r7, #20
|
|
8002866: 4619 mov r1, r3
|
|
8002868: 480b ldr r0, [pc, #44] @ (8002898 <MX_GPIO_Init+0x360>)
|
|
800286a: f000 ff37 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/* EXTI interrupt init*/
|
|
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
|
|
800286e: 2200 movs r2, #0
|
|
8002870: 2100 movs r1, #0
|
|
8002872: 2017 movs r0, #23
|
|
8002874: f000 fdef bl 8003456 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
|
|
8002878: 2017 movs r0, #23
|
|
800287a: f000 fe08 bl 800348e <HAL_NVIC_EnableIRQ>
|
|
|
|
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
|
|
800287e: 2200 movs r2, #0
|
|
8002880: 2100 movs r1, #0
|
|
8002882: 2028 movs r0, #40 @ 0x28
|
|
8002884: f000 fde7 bl 8003456 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
|
|
8002888: 2028 movs r0, #40 @ 0x28
|
|
800288a: f000 fe00 bl 800348e <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
800288e: bf00 nop
|
|
8002890: 3728 adds r7, #40 @ 0x28
|
|
8002892: 46bd mov sp, r7
|
|
8002894: bd80 pop {r7, pc}
|
|
8002896: bf00 nop
|
|
8002898: 48000400 .word 0x48000400
|
|
|
|
0800289c <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
800289c: b480 push {r7}
|
|
800289e: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80028a0: b672 cpsid i
|
|
}
|
|
80028a2: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
80028a4: bf00 nop
|
|
80028a6: e7fd b.n 80028a4 <Error_Handler+0x8>
|
|
|
|
080028a8 <Pressure_Test>:
|
|
*/
|
|
|
|
#include "pressure.h"
|
|
|
|
void Pressure_Test(void)
|
|
{
|
|
80028a8: b580 push {r7, lr}
|
|
80028aa: b082 sub sp, #8
|
|
80028ac: af00 add r7, sp, #0
|
|
float press_value = 0;
|
|
80028ae: f04f 0300 mov.w r3, #0
|
|
80028b2: 607b str r3, [r7, #4]
|
|
BSP_PSENSOR_Init();
|
|
80028b4: f7fe fdc0 bl 8001438 <BSP_PSENSOR_Init>
|
|
press_value = BSP_PSENSOR_ReadPressure();
|
|
80028b8: f7fe fdde bl 8001478 <BSP_PSENSOR_ReadPressure>
|
|
80028bc: ee07 0a90 vmov s15, r0
|
|
80028c0: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80028c4: edc7 7a01 vstr s15, [r7, #4]
|
|
printf("PRESSURE is = %.2f mBar \n", press_value);
|
|
80028c8: 6878 ldr r0, [r7, #4]
|
|
80028ca: f7fd fe3d bl 8000548 <__aeabi_f2d>
|
|
80028ce: 4602 mov r2, r0
|
|
80028d0: 460b mov r3, r1
|
|
80028d2: 4803 ldr r0, [pc, #12] @ (80028e0 <Pressure_Test+0x38>)
|
|
80028d4: f005 fb7c bl 8007fd0 <iprintf>
|
|
}
|
|
80028d8: bf00 nop
|
|
80028da: 3708 adds r7, #8
|
|
80028dc: 46bd mov sp, r7
|
|
80028de: bd80 pop {r7, pc}
|
|
80028e0: 0800a0a0 .word 0x0800a0a0
|
|
|
|
080028e4 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
80028e4: b480 push {r7}
|
|
80028e6: b083 sub sp, #12
|
|
80028e8: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80028ea: 4b0f ldr r3, [pc, #60] @ (8002928 <HAL_MspInit+0x44>)
|
|
80028ec: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80028ee: 4a0e ldr r2, [pc, #56] @ (8002928 <HAL_MspInit+0x44>)
|
|
80028f0: f043 0301 orr.w r3, r3, #1
|
|
80028f4: 6613 str r3, [r2, #96] @ 0x60
|
|
80028f6: 4b0c ldr r3, [pc, #48] @ (8002928 <HAL_MspInit+0x44>)
|
|
80028f8: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80028fa: f003 0301 and.w r3, r3, #1
|
|
80028fe: 607b str r3, [r7, #4]
|
|
8002900: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8002902: 4b09 ldr r3, [pc, #36] @ (8002928 <HAL_MspInit+0x44>)
|
|
8002904: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002906: 4a08 ldr r2, [pc, #32] @ (8002928 <HAL_MspInit+0x44>)
|
|
8002908: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800290c: 6593 str r3, [r2, #88] @ 0x58
|
|
800290e: 4b06 ldr r3, [pc, #24] @ (8002928 <HAL_MspInit+0x44>)
|
|
8002910: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002912: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8002916: 603b str r3, [r7, #0]
|
|
8002918: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
800291a: bf00 nop
|
|
800291c: 370c adds r7, #12
|
|
800291e: 46bd mov sp, r7
|
|
8002920: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002924: 4770 bx lr
|
|
8002926: bf00 nop
|
|
8002928: 40021000 .word 0x40021000
|
|
|
|
0800292c <HAL_DFSDM_ChannelMspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hdfsdm_channel: DFSDM_Channel handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)
|
|
{
|
|
800292c: b580 push {r7, lr}
|
|
800292e: b0ac sub sp, #176 @ 0xb0
|
|
8002930: af00 add r7, sp, #0
|
|
8002932: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002934: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002938: 2200 movs r2, #0
|
|
800293a: 601a str r2, [r3, #0]
|
|
800293c: 605a str r2, [r3, #4]
|
|
800293e: 609a str r2, [r3, #8]
|
|
8002940: 60da str r2, [r3, #12]
|
|
8002942: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002944: f107 0314 add.w r3, r7, #20
|
|
8002948: 2288 movs r2, #136 @ 0x88
|
|
800294a: 2100 movs r1, #0
|
|
800294c: 4618 mov r0, r3
|
|
800294e: f005 fc87 bl 8008260 <memset>
|
|
if(DFSDM1_Init == 0)
|
|
8002952: 4b25 ldr r3, [pc, #148] @ (80029e8 <HAL_DFSDM_ChannelMspInit+0xbc>)
|
|
8002954: 681b ldr r3, [r3, #0]
|
|
8002956: 2b00 cmp r3, #0
|
|
8002958: d142 bne.n 80029e0 <HAL_DFSDM_ChannelMspInit+0xb4>
|
|
|
|
/* USER CODE END DFSDM1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1;
|
|
800295a: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
800295e: 617b str r3, [r7, #20]
|
|
PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
|
|
8002960: 2300 movs r3, #0
|
|
8002962: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002966: f107 0314 add.w r3, r7, #20
|
|
800296a: 4618 mov r0, r3
|
|
800296c: f003 f854 bl 8005a18 <HAL_RCCEx_PeriphCLKConfig>
|
|
8002970: 4603 mov r3, r0
|
|
8002972: 2b00 cmp r3, #0
|
|
8002974: d001 beq.n 800297a <HAL_DFSDM_ChannelMspInit+0x4e>
|
|
{
|
|
Error_Handler();
|
|
8002976: f7ff ff91 bl 800289c <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_DFSDM1_CLK_ENABLE();
|
|
800297a: 4b1c ldr r3, [pc, #112] @ (80029ec <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
800297c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800297e: 4a1b ldr r2, [pc, #108] @ (80029ec <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
8002980: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8002984: 6613 str r3, [r2, #96] @ 0x60
|
|
8002986: 4b19 ldr r3, [pc, #100] @ (80029ec <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
8002988: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800298a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
800298e: 613b str r3, [r7, #16]
|
|
8002990: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8002992: 4b16 ldr r3, [pc, #88] @ (80029ec <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
8002994: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002996: 4a15 ldr r2, [pc, #84] @ (80029ec <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
8002998: f043 0310 orr.w r3, r3, #16
|
|
800299c: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800299e: 4b13 ldr r3, [pc, #76] @ (80029ec <HAL_DFSDM_ChannelMspInit+0xc0>)
|
|
80029a0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80029a2: f003 0310 and.w r3, r3, #16
|
|
80029a6: 60fb str r3, [r7, #12]
|
|
80029a8: 68fb ldr r3, [r7, #12]
|
|
/**DFSDM1 GPIO Configuration
|
|
PE7 ------> DFSDM1_DATIN2
|
|
PE9 ------> DFSDM1_CKOUT
|
|
*/
|
|
GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin;
|
|
80029aa: f44f 7320 mov.w r3, #640 @ 0x280
|
|
80029ae: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80029b2: 2302 movs r3, #2
|
|
80029b4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80029b8: 2300 movs r3, #0
|
|
80029ba: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80029be: 2300 movs r3, #0
|
|
80029c0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1;
|
|
80029c4: 2306 movs r3, #6
|
|
80029c6: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
80029ca: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
80029ce: 4619 mov r1, r3
|
|
80029d0: 4807 ldr r0, [pc, #28] @ (80029f0 <HAL_DFSDM_ChannelMspInit+0xc4>)
|
|
80029d2: f000 fe83 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN DFSDM1_MspInit 1 */
|
|
|
|
/* USER CODE END DFSDM1_MspInit 1 */
|
|
|
|
DFSDM1_Init++;
|
|
80029d6: 4b04 ldr r3, [pc, #16] @ (80029e8 <HAL_DFSDM_ChannelMspInit+0xbc>)
|
|
80029d8: 681b ldr r3, [r3, #0]
|
|
80029da: 3301 adds r3, #1
|
|
80029dc: 4a02 ldr r2, [pc, #8] @ (80029e8 <HAL_DFSDM_ChannelMspInit+0xbc>)
|
|
80029de: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
}
|
|
80029e0: bf00 nop
|
|
80029e2: 37b0 adds r7, #176 @ 0xb0
|
|
80029e4: 46bd mov sp, r7
|
|
80029e6: bd80 pop {r7, pc}
|
|
80029e8: 20000a48 .word 0x20000a48
|
|
80029ec: 40021000 .word 0x40021000
|
|
80029f0: 48001000 .word 0x48001000
|
|
|
|
080029f4 <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
80029f4: b580 push {r7, lr}
|
|
80029f6: b0ac sub sp, #176 @ 0xb0
|
|
80029f8: af00 add r7, sp, #0
|
|
80029fa: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80029fc: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002a00: 2200 movs r2, #0
|
|
8002a02: 601a str r2, [r3, #0]
|
|
8002a04: 605a str r2, [r3, #4]
|
|
8002a06: 609a str r2, [r3, #8]
|
|
8002a08: 60da str r2, [r3, #12]
|
|
8002a0a: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002a0c: f107 0314 add.w r3, r7, #20
|
|
8002a10: 2288 movs r2, #136 @ 0x88
|
|
8002a12: 2100 movs r1, #0
|
|
8002a14: 4618 mov r0, r3
|
|
8002a16: f005 fc23 bl 8008260 <memset>
|
|
if(hi2c->Instance==I2C2)
|
|
8002a1a: 687b ldr r3, [r7, #4]
|
|
8002a1c: 681b ldr r3, [r3, #0]
|
|
8002a1e: 4a21 ldr r2, [pc, #132] @ (8002aa4 <HAL_I2C_MspInit+0xb0>)
|
|
8002a20: 4293 cmp r3, r2
|
|
8002a22: d13b bne.n 8002a9c <HAL_I2C_MspInit+0xa8>
|
|
|
|
/* USER CODE END I2C2_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
|
|
8002a24: 2380 movs r3, #128 @ 0x80
|
|
8002a26: 617b str r3, [r7, #20]
|
|
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
|
|
8002a28: 2300 movs r3, #0
|
|
8002a2a: 66bb str r3, [r7, #104] @ 0x68
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002a2c: f107 0314 add.w r3, r7, #20
|
|
8002a30: 4618 mov r0, r3
|
|
8002a32: f002 fff1 bl 8005a18 <HAL_RCCEx_PeriphCLKConfig>
|
|
8002a36: 4603 mov r3, r0
|
|
8002a38: 2b00 cmp r3, #0
|
|
8002a3a: d001 beq.n 8002a40 <HAL_I2C_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8002a3c: f7ff ff2e bl 800289c <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8002a40: 4b19 ldr r3, [pc, #100] @ (8002aa8 <HAL_I2C_MspInit+0xb4>)
|
|
8002a42: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002a44: 4a18 ldr r2, [pc, #96] @ (8002aa8 <HAL_I2C_MspInit+0xb4>)
|
|
8002a46: f043 0302 orr.w r3, r3, #2
|
|
8002a4a: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002a4c: 4b16 ldr r3, [pc, #88] @ (8002aa8 <HAL_I2C_MspInit+0xb4>)
|
|
8002a4e: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002a50: f003 0302 and.w r3, r3, #2
|
|
8002a54: 613b str r3, [r7, #16]
|
|
8002a56: 693b ldr r3, [r7, #16]
|
|
/**I2C2 GPIO Configuration
|
|
PB10 ------> I2C2_SCL
|
|
PB11 ------> I2C2_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin;
|
|
8002a58: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
8002a5c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8002a60: 2312 movs r3, #18
|
|
8002a62: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8002a66: 2301 movs r3, #1
|
|
8002a68: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002a6c: 2303 movs r3, #3
|
|
8002a6e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
|
|
8002a72: 2304 movs r3, #4
|
|
8002a74: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8002a78: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002a7c: 4619 mov r1, r3
|
|
8002a7e: 480b ldr r0, [pc, #44] @ (8002aac <HAL_I2C_MspInit+0xb8>)
|
|
8002a80: f000 fe2c bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C2_CLK_ENABLE();
|
|
8002a84: 4b08 ldr r3, [pc, #32] @ (8002aa8 <HAL_I2C_MspInit+0xb4>)
|
|
8002a86: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002a88: 4a07 ldr r2, [pc, #28] @ (8002aa8 <HAL_I2C_MspInit+0xb4>)
|
|
8002a8a: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8002a8e: 6593 str r3, [r2, #88] @ 0x58
|
|
8002a90: 4b05 ldr r3, [pc, #20] @ (8002aa8 <HAL_I2C_MspInit+0xb4>)
|
|
8002a92: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002a94: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8002a98: 60fb str r3, [r7, #12]
|
|
8002a9a: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END I2C2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8002a9c: bf00 nop
|
|
8002a9e: 37b0 adds r7, #176 @ 0xb0
|
|
8002aa0: 46bd mov sp, r7
|
|
8002aa2: bd80 pop {r7, pc}
|
|
8002aa4: 40005800 .word 0x40005800
|
|
8002aa8: 40021000 .word 0x40021000
|
|
8002aac: 48000400 .word 0x48000400
|
|
|
|
08002ab0 <HAL_I2C_MspDeInit>:
|
|
* This function freeze the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8002ab0: b580 push {r7, lr}
|
|
8002ab2: b082 sub sp, #8
|
|
8002ab4: af00 add r7, sp, #0
|
|
8002ab6: 6078 str r0, [r7, #4]
|
|
if(hi2c->Instance==I2C2)
|
|
8002ab8: 687b ldr r3, [r7, #4]
|
|
8002aba: 681b ldr r3, [r3, #0]
|
|
8002abc: 4a0b ldr r2, [pc, #44] @ (8002aec <HAL_I2C_MspDeInit+0x3c>)
|
|
8002abe: 4293 cmp r3, r2
|
|
8002ac0: d10f bne.n 8002ae2 <HAL_I2C_MspDeInit+0x32>
|
|
{
|
|
/* USER CODE BEGIN I2C2_MspDeInit 0 */
|
|
|
|
/* USER CODE END I2C2_MspDeInit 0 */
|
|
/* Peripheral clock disable */
|
|
__HAL_RCC_I2C2_CLK_DISABLE();
|
|
8002ac2: 4b0b ldr r3, [pc, #44] @ (8002af0 <HAL_I2C_MspDeInit+0x40>)
|
|
8002ac4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002ac6: 4a0a ldr r2, [pc, #40] @ (8002af0 <HAL_I2C_MspDeInit+0x40>)
|
|
8002ac8: f423 0380 bic.w r3, r3, #4194304 @ 0x400000
|
|
8002acc: 6593 str r3, [r2, #88] @ 0x58
|
|
|
|
/**I2C2 GPIO Configuration
|
|
PB10 ------> I2C2_SCL
|
|
PB11 ------> I2C2_SDA
|
|
*/
|
|
HAL_GPIO_DeInit(INTERNAL_I2C2_SCL_GPIO_Port, INTERNAL_I2C2_SCL_Pin);
|
|
8002ace: f44f 6180 mov.w r1, #1024 @ 0x400
|
|
8002ad2: 4808 ldr r0, [pc, #32] @ (8002af4 <HAL_I2C_MspDeInit+0x44>)
|
|
8002ad4: f000 ffac bl 8003a30 <HAL_GPIO_DeInit>
|
|
|
|
HAL_GPIO_DeInit(INTERNAL_I2C2_SDA_GPIO_Port, INTERNAL_I2C2_SDA_Pin);
|
|
8002ad8: f44f 6100 mov.w r1, #2048 @ 0x800
|
|
8002adc: 4805 ldr r0, [pc, #20] @ (8002af4 <HAL_I2C_MspDeInit+0x44>)
|
|
8002ade: f000 ffa7 bl 8003a30 <HAL_GPIO_DeInit>
|
|
/* USER CODE BEGIN I2C2_MspDeInit 1 */
|
|
|
|
/* USER CODE END I2C2_MspDeInit 1 */
|
|
}
|
|
|
|
}
|
|
8002ae2: bf00 nop
|
|
8002ae4: 3708 adds r7, #8
|
|
8002ae6: 46bd mov sp, r7
|
|
8002ae8: bd80 pop {r7, pc}
|
|
8002aea: bf00 nop
|
|
8002aec: 40005800 .word 0x40005800
|
|
8002af0: 40021000 .word 0x40021000
|
|
8002af4: 48000400 .word 0x48000400
|
|
|
|
08002af8 <HAL_QSPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hqspi: QSPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
|
|
{
|
|
8002af8: b580 push {r7, lr}
|
|
8002afa: b08a sub sp, #40 @ 0x28
|
|
8002afc: af00 add r7, sp, #0
|
|
8002afe: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002b00: f107 0314 add.w r3, r7, #20
|
|
8002b04: 2200 movs r2, #0
|
|
8002b06: 601a str r2, [r3, #0]
|
|
8002b08: 605a str r2, [r3, #4]
|
|
8002b0a: 609a str r2, [r3, #8]
|
|
8002b0c: 60da str r2, [r3, #12]
|
|
8002b0e: 611a str r2, [r3, #16]
|
|
if(hqspi->Instance==QUADSPI)
|
|
8002b10: 687b ldr r3, [r7, #4]
|
|
8002b12: 681b ldr r3, [r3, #0]
|
|
8002b14: 4a17 ldr r2, [pc, #92] @ (8002b74 <HAL_QSPI_MspInit+0x7c>)
|
|
8002b16: 4293 cmp r3, r2
|
|
8002b18: d128 bne.n 8002b6c <HAL_QSPI_MspInit+0x74>
|
|
{
|
|
/* USER CODE BEGIN QUADSPI_MspInit 0 */
|
|
|
|
/* USER CODE END QUADSPI_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_QSPI_CLK_ENABLE();
|
|
8002b1a: 4b17 ldr r3, [pc, #92] @ (8002b78 <HAL_QSPI_MspInit+0x80>)
|
|
8002b1c: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8002b1e: 4a16 ldr r2, [pc, #88] @ (8002b78 <HAL_QSPI_MspInit+0x80>)
|
|
8002b20: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8002b24: 6513 str r3, [r2, #80] @ 0x50
|
|
8002b26: 4b14 ldr r3, [pc, #80] @ (8002b78 <HAL_QSPI_MspInit+0x80>)
|
|
8002b28: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8002b2a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002b2e: 613b str r3, [r7, #16]
|
|
8002b30: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8002b32: 4b11 ldr r3, [pc, #68] @ (8002b78 <HAL_QSPI_MspInit+0x80>)
|
|
8002b34: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002b36: 4a10 ldr r2, [pc, #64] @ (8002b78 <HAL_QSPI_MspInit+0x80>)
|
|
8002b38: f043 0310 orr.w r3, r3, #16
|
|
8002b3c: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002b3e: 4b0e ldr r3, [pc, #56] @ (8002b78 <HAL_QSPI_MspInit+0x80>)
|
|
8002b40: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002b42: f003 0310 and.w r3, r3, #16
|
|
8002b46: 60fb str r3, [r7, #12]
|
|
8002b48: 68fb ldr r3, [r7, #12]
|
|
PE12 ------> QUADSPI_BK1_IO0
|
|
PE13 ------> QUADSPI_BK1_IO1
|
|
PE14 ------> QUADSPI_BK1_IO2
|
|
PE15 ------> QUADSPI_BK1_IO3
|
|
*/
|
|
GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin
|
|
8002b4a: f44f 437c mov.w r3, #64512 @ 0xfc00
|
|
8002b4e: 617b str r3, [r7, #20]
|
|
|QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002b50: 2302 movs r3, #2
|
|
8002b52: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002b54: 2300 movs r3, #0
|
|
8002b56: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002b58: 2303 movs r3, #3
|
|
8002b5a: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
|
|
8002b5c: 230a movs r3, #10
|
|
8002b5e: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8002b60: f107 0314 add.w r3, r7, #20
|
|
8002b64: 4619 mov r1, r3
|
|
8002b66: 4805 ldr r0, [pc, #20] @ (8002b7c <HAL_QSPI_MspInit+0x84>)
|
|
8002b68: f000 fdb8 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END QUADSPI_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8002b6c: bf00 nop
|
|
8002b6e: 3728 adds r7, #40 @ 0x28
|
|
8002b70: 46bd mov sp, r7
|
|
8002b72: bd80 pop {r7, pc}
|
|
8002b74: a0001000 .word 0xa0001000
|
|
8002b78: 40021000 .word 0x40021000
|
|
8002b7c: 48001000 .word 0x48001000
|
|
|
|
08002b80 <HAL_SPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
8002b80: b580 push {r7, lr}
|
|
8002b82: b08a sub sp, #40 @ 0x28
|
|
8002b84: af00 add r7, sp, #0
|
|
8002b86: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002b88: f107 0314 add.w r3, r7, #20
|
|
8002b8c: 2200 movs r2, #0
|
|
8002b8e: 601a str r2, [r3, #0]
|
|
8002b90: 605a str r2, [r3, #4]
|
|
8002b92: 609a str r2, [r3, #8]
|
|
8002b94: 60da str r2, [r3, #12]
|
|
8002b96: 611a str r2, [r3, #16]
|
|
if(hspi->Instance==SPI3)
|
|
8002b98: 687b ldr r3, [r7, #4]
|
|
8002b9a: 681b ldr r3, [r3, #0]
|
|
8002b9c: 4a17 ldr r2, [pc, #92] @ (8002bfc <HAL_SPI_MspInit+0x7c>)
|
|
8002b9e: 4293 cmp r3, r2
|
|
8002ba0: d128 bne.n 8002bf4 <HAL_SPI_MspInit+0x74>
|
|
{
|
|
/* USER CODE BEGIN SPI3_MspInit 0 */
|
|
|
|
/* USER CODE END SPI3_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_SPI3_CLK_ENABLE();
|
|
8002ba2: 4b17 ldr r3, [pc, #92] @ (8002c00 <HAL_SPI_MspInit+0x80>)
|
|
8002ba4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002ba6: 4a16 ldr r2, [pc, #88] @ (8002c00 <HAL_SPI_MspInit+0x80>)
|
|
8002ba8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8002bac: 6593 str r3, [r2, #88] @ 0x58
|
|
8002bae: 4b14 ldr r3, [pc, #80] @ (8002c00 <HAL_SPI_MspInit+0x80>)
|
|
8002bb0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002bb2: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8002bb6: 613b str r3, [r7, #16]
|
|
8002bb8: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8002bba: 4b11 ldr r3, [pc, #68] @ (8002c00 <HAL_SPI_MspInit+0x80>)
|
|
8002bbc: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002bbe: 4a10 ldr r2, [pc, #64] @ (8002c00 <HAL_SPI_MspInit+0x80>)
|
|
8002bc0: f043 0304 orr.w r3, r3, #4
|
|
8002bc4: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002bc6: 4b0e ldr r3, [pc, #56] @ (8002c00 <HAL_SPI_MspInit+0x80>)
|
|
8002bc8: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002bca: f003 0304 and.w r3, r3, #4
|
|
8002bce: 60fb str r3, [r7, #12]
|
|
8002bd0: 68fb ldr r3, [r7, #12]
|
|
/**SPI3 GPIO Configuration
|
|
PC10 ------> SPI3_SCK
|
|
PC11 ------> SPI3_MISO
|
|
PC12 ------> SPI3_MOSI
|
|
*/
|
|
GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin;
|
|
8002bd2: f44f 53e0 mov.w r3, #7168 @ 0x1c00
|
|
8002bd6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002bd8: 2302 movs r3, #2
|
|
8002bda: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002bdc: 2300 movs r3, #0
|
|
8002bde: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002be0: 2303 movs r3, #3
|
|
8002be2: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
|
|
8002be4: 2306 movs r3, #6
|
|
8002be6: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8002be8: f107 0314 add.w r3, r7, #20
|
|
8002bec: 4619 mov r1, r3
|
|
8002bee: 4805 ldr r0, [pc, #20] @ (8002c04 <HAL_SPI_MspInit+0x84>)
|
|
8002bf0: f000 fd74 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END SPI3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8002bf4: bf00 nop
|
|
8002bf6: 3728 adds r7, #40 @ 0x28
|
|
8002bf8: 46bd mov sp, r7
|
|
8002bfa: bd80 pop {r7, pc}
|
|
8002bfc: 40003c00 .word 0x40003c00
|
|
8002c00: 40021000 .word 0x40021000
|
|
8002c04: 48000800 .word 0x48000800
|
|
|
|
08002c08 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8002c08: b580 push {r7, lr}
|
|
8002c0a: b0ae sub sp, #184 @ 0xb8
|
|
8002c0c: af00 add r7, sp, #0
|
|
8002c0e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002c10: f107 03a4 add.w r3, r7, #164 @ 0xa4
|
|
8002c14: 2200 movs r2, #0
|
|
8002c16: 601a str r2, [r3, #0]
|
|
8002c18: 605a str r2, [r3, #4]
|
|
8002c1a: 609a str r2, [r3, #8]
|
|
8002c1c: 60da str r2, [r3, #12]
|
|
8002c1e: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002c20: f107 031c add.w r3, r7, #28
|
|
8002c24: 2288 movs r2, #136 @ 0x88
|
|
8002c26: 2100 movs r1, #0
|
|
8002c28: 4618 mov r0, r3
|
|
8002c2a: f005 fb19 bl 8008260 <memset>
|
|
if(huart->Instance==USART1)
|
|
8002c2e: 687b ldr r3, [r7, #4]
|
|
8002c30: 681b ldr r3, [r3, #0]
|
|
8002c32: 4a42 ldr r2, [pc, #264] @ (8002d3c <HAL_UART_MspInit+0x134>)
|
|
8002c34: 4293 cmp r3, r2
|
|
8002c36: d13b bne.n 8002cb0 <HAL_UART_MspInit+0xa8>
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|
8002c38: 2301 movs r3, #1
|
|
8002c3a: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|
8002c3c: 2300 movs r3, #0
|
|
8002c3e: 657b str r3, [r7, #84] @ 0x54
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002c40: f107 031c add.w r3, r7, #28
|
|
8002c44: 4618 mov r0, r3
|
|
8002c46: f002 fee7 bl 8005a18 <HAL_RCCEx_PeriphCLKConfig>
|
|
8002c4a: 4603 mov r3, r0
|
|
8002c4c: 2b00 cmp r3, #0
|
|
8002c4e: d001 beq.n 8002c54 <HAL_UART_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8002c50: f7ff fe24 bl 800289c <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8002c54: 4b3a ldr r3, [pc, #232] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002c56: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002c58: 4a39 ldr r2, [pc, #228] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002c5a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8002c5e: 6613 str r3, [r2, #96] @ 0x60
|
|
8002c60: 4b37 ldr r3, [pc, #220] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002c62: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002c64: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8002c68: 61bb str r3, [r7, #24]
|
|
8002c6a: 69bb ldr r3, [r7, #24]
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8002c6c: 4b34 ldr r3, [pc, #208] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002c6e: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002c70: 4a33 ldr r2, [pc, #204] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002c72: f043 0302 orr.w r3, r3, #2
|
|
8002c76: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002c78: 4b31 ldr r3, [pc, #196] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002c7a: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002c7c: f003 0302 and.w r3, r3, #2
|
|
8002c80: 617b str r3, [r7, #20]
|
|
8002c82: 697b ldr r3, [r7, #20]
|
|
/**USART1 GPIO Configuration
|
|
PB6 ------> USART1_TX
|
|
PB7 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin;
|
|
8002c84: 23c0 movs r3, #192 @ 0xc0
|
|
8002c86: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002c8a: 2302 movs r3, #2
|
|
8002c8c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002c90: 2300 movs r3, #0
|
|
8002c92: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002c96: 2303 movs r3, #3
|
|
8002c98: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
8002c9c: 2307 movs r3, #7
|
|
8002c9e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8002ca2: f107 03a4 add.w r3, r7, #164 @ 0xa4
|
|
8002ca6: 4619 mov r1, r3
|
|
8002ca8: 4826 ldr r0, [pc, #152] @ (8002d44 <HAL_UART_MspInit+0x13c>)
|
|
8002caa: f000 fd17 bl 80036dc <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN USART3_MspInit 1 */
|
|
|
|
/* USER CODE END USART3_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8002cae: e040 b.n 8002d32 <HAL_UART_MspInit+0x12a>
|
|
else if(huart->Instance==USART3)
|
|
8002cb0: 687b ldr r3, [r7, #4]
|
|
8002cb2: 681b ldr r3, [r3, #0]
|
|
8002cb4: 4a24 ldr r2, [pc, #144] @ (8002d48 <HAL_UART_MspInit+0x140>)
|
|
8002cb6: 4293 cmp r3, r2
|
|
8002cb8: d13b bne.n 8002d32 <HAL_UART_MspInit+0x12a>
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3;
|
|
8002cba: 2304 movs r3, #4
|
|
8002cbc: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
|
|
8002cbe: 2300 movs r3, #0
|
|
8002cc0: 65fb str r3, [r7, #92] @ 0x5c
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002cc2: f107 031c add.w r3, r7, #28
|
|
8002cc6: 4618 mov r0, r3
|
|
8002cc8: f002 fea6 bl 8005a18 <HAL_RCCEx_PeriphCLKConfig>
|
|
8002ccc: 4603 mov r3, r0
|
|
8002cce: 2b00 cmp r3, #0
|
|
8002cd0: d001 beq.n 8002cd6 <HAL_UART_MspInit+0xce>
|
|
Error_Handler();
|
|
8002cd2: f7ff fde3 bl 800289c <Error_Handler>
|
|
__HAL_RCC_USART3_CLK_ENABLE();
|
|
8002cd6: 4b1a ldr r3, [pc, #104] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002cd8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002cda: 4a19 ldr r2, [pc, #100] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002cdc: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8002ce0: 6593 str r3, [r2, #88] @ 0x58
|
|
8002ce2: 4b17 ldr r3, [pc, #92] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002ce4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002ce6: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8002cea: 613b str r3, [r7, #16]
|
|
8002cec: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8002cee: 4b14 ldr r3, [pc, #80] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002cf0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002cf2: 4a13 ldr r2, [pc, #76] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002cf4: f043 0308 orr.w r3, r3, #8
|
|
8002cf8: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002cfa: 4b11 ldr r3, [pc, #68] @ (8002d40 <HAL_UART_MspInit+0x138>)
|
|
8002cfc: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002cfe: f003 0308 and.w r3, r3, #8
|
|
8002d02: 60fb str r3, [r7, #12]
|
|
8002d04: 68fb ldr r3, [r7, #12]
|
|
GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin;
|
|
8002d06: f44f 7340 mov.w r3, #768 @ 0x300
|
|
8002d0a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002d0e: 2302 movs r3, #2
|
|
8002d10: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002d14: 2300 movs r3, #0
|
|
8002d16: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002d1a: 2303 movs r3, #3
|
|
8002d1c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
|
|
8002d20: 2307 movs r3, #7
|
|
8002d22: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8002d26: f107 03a4 add.w r3, r7, #164 @ 0xa4
|
|
8002d2a: 4619 mov r1, r3
|
|
8002d2c: 4807 ldr r0, [pc, #28] @ (8002d4c <HAL_UART_MspInit+0x144>)
|
|
8002d2e: f000 fcd5 bl 80036dc <HAL_GPIO_Init>
|
|
}
|
|
8002d32: bf00 nop
|
|
8002d34: 37b8 adds r7, #184 @ 0xb8
|
|
8002d36: 46bd mov sp, r7
|
|
8002d38: bd80 pop {r7, pc}
|
|
8002d3a: bf00 nop
|
|
8002d3c: 40013800 .word 0x40013800
|
|
8002d40: 40021000 .word 0x40021000
|
|
8002d44: 48000400 .word 0x48000400
|
|
8002d48: 40004800 .word 0x40004800
|
|
8002d4c: 48000c00 .word 0x48000c00
|
|
|
|
08002d50 <HAL_PCD_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hpcd: PCD handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
|
{
|
|
8002d50: b580 push {r7, lr}
|
|
8002d52: b0ac sub sp, #176 @ 0xb0
|
|
8002d54: af00 add r7, sp, #0
|
|
8002d56: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002d58: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002d5c: 2200 movs r2, #0
|
|
8002d5e: 601a str r2, [r3, #0]
|
|
8002d60: 605a str r2, [r3, #4]
|
|
8002d62: 609a str r2, [r3, #8]
|
|
8002d64: 60da str r2, [r3, #12]
|
|
8002d66: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002d68: f107 0314 add.w r3, r7, #20
|
|
8002d6c: 2288 movs r2, #136 @ 0x88
|
|
8002d6e: 2100 movs r1, #0
|
|
8002d70: 4618 mov r0, r3
|
|
8002d72: f005 fa75 bl 8008260 <memset>
|
|
if(hpcd->Instance==USB_OTG_FS)
|
|
8002d76: 687b ldr r3, [r7, #4]
|
|
8002d78: 681b ldr r3, [r3, #0]
|
|
8002d7a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8002d7e: d17c bne.n 8002e7a <HAL_PCD_MspInit+0x12a>
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
|
8002d80: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8002d84: 617b str r3, [r7, #20]
|
|
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
|
8002d86: f04f 6380 mov.w r3, #67108864 @ 0x4000000
|
|
8002d8a: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
|
|
8002d8e: 2301 movs r3, #1
|
|
8002d90: 61bb str r3, [r7, #24]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
|
8002d92: 2301 movs r3, #1
|
|
8002d94: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
|
|
8002d96: 2318 movs r3, #24
|
|
8002d98: 623b str r3, [r7, #32]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
|
8002d9a: 2307 movs r3, #7
|
|
8002d9c: 627b str r3, [r7, #36] @ 0x24
|
|
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
|
8002d9e: 2302 movs r3, #2
|
|
8002da0: 62bb str r3, [r7, #40] @ 0x28
|
|
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
|
8002da2: 2302 movs r3, #2
|
|
8002da4: 62fb str r3, [r7, #44] @ 0x2c
|
|
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
|
8002da6: f44f 1380 mov.w r3, #1048576 @ 0x100000
|
|
8002daa: 633b str r3, [r7, #48] @ 0x30
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002dac: f107 0314 add.w r3, r7, #20
|
|
8002db0: 4618 mov r0, r3
|
|
8002db2: f002 fe31 bl 8005a18 <HAL_RCCEx_PeriphCLKConfig>
|
|
8002db6: 4603 mov r3, r0
|
|
8002db8: 2b00 cmp r3, #0
|
|
8002dba: d001 beq.n 8002dc0 <HAL_PCD_MspInit+0x70>
|
|
{
|
|
Error_Handler();
|
|
8002dbc: f7ff fd6e bl 800289c <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002dc0: 4b30 ldr r3, [pc, #192] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002dc2: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002dc4: 4a2f ldr r2, [pc, #188] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002dc6: f043 0301 orr.w r3, r3, #1
|
|
8002dca: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002dcc: 4b2d ldr r3, [pc, #180] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002dce: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002dd0: f003 0301 and.w r3, r3, #1
|
|
8002dd4: 613b str r3, [r7, #16]
|
|
8002dd6: 693b ldr r3, [r7, #16]
|
|
PA9 ------> USB_OTG_FS_VBUS
|
|
PA10 ------> USB_OTG_FS_ID
|
|
PA11 ------> USB_OTG_FS_DM
|
|
PA12 ------> USB_OTG_FS_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin;
|
|
8002dd8: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8002ddc: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8002de0: 2300 movs r3, #0
|
|
8002de2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002de6: 2300 movs r3, #0
|
|
8002de8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
|
|
8002dec: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002df0: 4619 mov r1, r3
|
|
8002df2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8002df6: f000 fc71 bl 80036dc <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin;
|
|
8002dfa: f44f 53e0 mov.w r3, #7168 @ 0x1c00
|
|
8002dfe: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002e02: 2302 movs r3, #2
|
|
8002e04: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002e08: 2300 movs r3, #0
|
|
8002e0a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002e0e: 2303 movs r3, #3
|
|
8002e10: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
|
8002e14: 230a movs r3, #10
|
|
8002e16: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002e1a: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002e1e: 4619 mov r1, r3
|
|
8002e20: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8002e24: f000 fc5a bl 80036dc <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
|
8002e28: 4b16 ldr r3, [pc, #88] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e2a: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002e2c: 4a15 ldr r2, [pc, #84] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e2e: f443 5380 orr.w r3, r3, #4096 @ 0x1000
|
|
8002e32: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8002e34: 4b13 ldr r3, [pc, #76] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e36: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002e38: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8002e3c: 60fb str r3, [r7, #12]
|
|
8002e3e: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Enable VDDUSB */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8002e40: 4b10 ldr r3, [pc, #64] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e42: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002e44: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8002e48: 2b00 cmp r3, #0
|
|
8002e4a: d114 bne.n 8002e76 <HAL_PCD_MspInit+0x126>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8002e4c: 4b0d ldr r3, [pc, #52] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e4e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002e50: 4a0c ldr r2, [pc, #48] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e52: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8002e56: 6593 str r3, [r2, #88] @ 0x58
|
|
8002e58: 4b0a ldr r3, [pc, #40] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e5a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002e5c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8002e60: 60bb str r3, [r7, #8]
|
|
8002e62: 68bb ldr r3, [r7, #8]
|
|
HAL_PWREx_EnableVddUSB();
|
|
8002e64: f001 ff0c bl 8004c80 <HAL_PWREx_EnableVddUSB>
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8002e68: 4b06 ldr r3, [pc, #24] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e6a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002e6c: 4a05 ldr r2, [pc, #20] @ (8002e84 <HAL_PCD_MspInit+0x134>)
|
|
8002e6e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8002e72: 6593 str r3, [r2, #88] @ 0x58
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8002e74: e001 b.n 8002e7a <HAL_PCD_MspInit+0x12a>
|
|
HAL_PWREx_EnableVddUSB();
|
|
8002e76: f001 ff03 bl 8004c80 <HAL_PWREx_EnableVddUSB>
|
|
}
|
|
8002e7a: bf00 nop
|
|
8002e7c: 37b0 adds r7, #176 @ 0xb0
|
|
8002e7e: 46bd mov sp, r7
|
|
8002e80: bd80 pop {r7, pc}
|
|
8002e82: bf00 nop
|
|
8002e84: 40021000 .word 0x40021000
|
|
|
|
08002e88 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8002e88: b480 push {r7}
|
|
8002e8a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8002e8c: bf00 nop
|
|
8002e8e: e7fd b.n 8002e8c <NMI_Handler+0x4>
|
|
|
|
08002e90 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8002e90: b480 push {r7}
|
|
8002e92: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8002e94: bf00 nop
|
|
8002e96: e7fd b.n 8002e94 <HardFault_Handler+0x4>
|
|
|
|
08002e98 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8002e98: b480 push {r7}
|
|
8002e9a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8002e9c: bf00 nop
|
|
8002e9e: e7fd b.n 8002e9c <MemManage_Handler+0x4>
|
|
|
|
08002ea0 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8002ea0: b480 push {r7}
|
|
8002ea2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8002ea4: bf00 nop
|
|
8002ea6: e7fd b.n 8002ea4 <BusFault_Handler+0x4>
|
|
|
|
08002ea8 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8002ea8: b480 push {r7}
|
|
8002eaa: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8002eac: bf00 nop
|
|
8002eae: e7fd b.n 8002eac <UsageFault_Handler+0x4>
|
|
|
|
08002eb0 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8002eb0: b480 push {r7}
|
|
8002eb2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8002eb4: bf00 nop
|
|
8002eb6: 46bd mov sp, r7
|
|
8002eb8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002ebc: 4770 bx lr
|
|
|
|
08002ebe <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8002ebe: b480 push {r7}
|
|
8002ec0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8002ec2: bf00 nop
|
|
8002ec4: 46bd mov sp, r7
|
|
8002ec6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002eca: 4770 bx lr
|
|
|
|
08002ecc <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8002ecc: b480 push {r7}
|
|
8002ece: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8002ed0: bf00 nop
|
|
8002ed2: 46bd mov sp, r7
|
|
8002ed4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002ed8: 4770 bx lr
|
|
|
|
08002eda <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8002eda: b580 push {r7, lr}
|
|
8002edc: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8002ede: f000 f99b bl 8003218 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8002ee2: bf00 nop
|
|
8002ee4: bd80 pop {r7, pc}
|
|
|
|
08002ee6 <EXTI9_5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI line[9:5] interrupts.
|
|
*/
|
|
void EXTI9_5_IRQHandler(void)
|
|
{
|
|
8002ee6: b580 push {r7, lr}
|
|
8002ee8: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI9_5_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI9_5_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(SPSGRF_915_GPIO3_EXTI5_Pin);
|
|
8002eea: 2020 movs r0, #32
|
|
8002eec: f000 feac bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(SPBTLE_RF_IRQ_EXTI6_Pin);
|
|
8002ef0: 2040 movs r0, #64 @ 0x40
|
|
8002ef2: f000 fea9 bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(VL53L0X_GPIO1_EXTI7_Pin);
|
|
8002ef6: 2080 movs r0, #128 @ 0x80
|
|
8002ef8: f000 fea6 bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(LSM3MDL_DRDY_EXTI8_Pin);
|
|
8002efc: f44f 7080 mov.w r0, #256 @ 0x100
|
|
8002f00: f000 fea2 bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI9_5_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI9_5_IRQn 1 */
|
|
}
|
|
8002f04: bf00 nop
|
|
8002f06: bd80 pop {r7, pc}
|
|
|
|
08002f08 <EXTI15_10_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI line[15:10] interrupts.
|
|
*/
|
|
void EXTI15_10_IRQHandler(void)
|
|
{
|
|
8002f08: b580 push {r7, lr}
|
|
8002f0a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI15_10_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(LPS22HB_INT_DRDY_EXTI0_Pin);
|
|
8002f0c: f44f 6080 mov.w r0, #1024 @ 0x400
|
|
8002f10: f000 fe9a bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(LSM6DSL_INT1_EXTI11_Pin);
|
|
8002f14: f44f 6000 mov.w r0, #2048 @ 0x800
|
|
8002f18: f000 fe96 bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(BUTTON_EXTI13_Pin);
|
|
8002f1c: f44f 5000 mov.w r0, #8192 @ 0x2000
|
|
8002f20: f000 fe92 bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(ARD_D2_Pin);
|
|
8002f24: f44f 4080 mov.w r0, #16384 @ 0x4000
|
|
8002f28: f000 fe8e bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(HTS221_DRDY_EXTI15_Pin);
|
|
8002f2c: f44f 4000 mov.w r0, #32768 @ 0x8000
|
|
8002f30: f000 fe8a bl 8003c48 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI15_10_IRQn 1 */
|
|
}
|
|
8002f34: bf00 nop
|
|
8002f36: bd80 pop {r7, pc}
|
|
|
|
08002f38 <_getpid>:
|
|
void initialise_monitor_handles()
|
|
{
|
|
}
|
|
|
|
int _getpid(void)
|
|
{
|
|
8002f38: b480 push {r7}
|
|
8002f3a: af00 add r7, sp, #0
|
|
return 1;
|
|
8002f3c: 2301 movs r3, #1
|
|
}
|
|
8002f3e: 4618 mov r0, r3
|
|
8002f40: 46bd mov sp, r7
|
|
8002f42: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002f46: 4770 bx lr
|
|
|
|
08002f48 <_kill>:
|
|
|
|
int _kill(int pid, int sig)
|
|
{
|
|
8002f48: b580 push {r7, lr}
|
|
8002f4a: b082 sub sp, #8
|
|
8002f4c: af00 add r7, sp, #0
|
|
8002f4e: 6078 str r0, [r7, #4]
|
|
8002f50: 6039 str r1, [r7, #0]
|
|
(void)pid;
|
|
(void)sig;
|
|
errno = EINVAL;
|
|
8002f52: f005 f9d7 bl 8008304 <__errno>
|
|
8002f56: 4603 mov r3, r0
|
|
8002f58: 2216 movs r2, #22
|
|
8002f5a: 601a str r2, [r3, #0]
|
|
return -1;
|
|
8002f5c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
8002f60: 4618 mov r0, r3
|
|
8002f62: 3708 adds r7, #8
|
|
8002f64: 46bd mov sp, r7
|
|
8002f66: bd80 pop {r7, pc}
|
|
|
|
08002f68 <_exit>:
|
|
|
|
void _exit (int status)
|
|
{
|
|
8002f68: b580 push {r7, lr}
|
|
8002f6a: b082 sub sp, #8
|
|
8002f6c: af00 add r7, sp, #0
|
|
8002f6e: 6078 str r0, [r7, #4]
|
|
_kill(status, -1);
|
|
8002f70: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8002f74: 6878 ldr r0, [r7, #4]
|
|
8002f76: f7ff ffe7 bl 8002f48 <_kill>
|
|
while (1) {} /* Make sure we hang here */
|
|
8002f7a: bf00 nop
|
|
8002f7c: e7fd b.n 8002f7a <_exit+0x12>
|
|
|
|
08002f7e <_read>:
|
|
}
|
|
|
|
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
|
{
|
|
8002f7e: b580 push {r7, lr}
|
|
8002f80: b086 sub sp, #24
|
|
8002f82: af00 add r7, sp, #0
|
|
8002f84: 60f8 str r0, [r7, #12]
|
|
8002f86: 60b9 str r1, [r7, #8]
|
|
8002f88: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002f8a: 2300 movs r3, #0
|
|
8002f8c: 617b str r3, [r7, #20]
|
|
8002f8e: e00a b.n 8002fa6 <_read+0x28>
|
|
{
|
|
*ptr++ = __io_getchar();
|
|
8002f90: f3af 8000 nop.w
|
|
8002f94: 4601 mov r1, r0
|
|
8002f96: 68bb ldr r3, [r7, #8]
|
|
8002f98: 1c5a adds r2, r3, #1
|
|
8002f9a: 60ba str r2, [r7, #8]
|
|
8002f9c: b2ca uxtb r2, r1
|
|
8002f9e: 701a strb r2, [r3, #0]
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002fa0: 697b ldr r3, [r7, #20]
|
|
8002fa2: 3301 adds r3, #1
|
|
8002fa4: 617b str r3, [r7, #20]
|
|
8002fa6: 697a ldr r2, [r7, #20]
|
|
8002fa8: 687b ldr r3, [r7, #4]
|
|
8002faa: 429a cmp r2, r3
|
|
8002fac: dbf0 blt.n 8002f90 <_read+0x12>
|
|
}
|
|
|
|
return len;
|
|
8002fae: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002fb0: 4618 mov r0, r3
|
|
8002fb2: 3718 adds r7, #24
|
|
8002fb4: 46bd mov sp, r7
|
|
8002fb6: bd80 pop {r7, pc}
|
|
|
|
08002fb8 <_write>:
|
|
|
|
__attribute__((weak)) int _write(int file, char *ptr, int len)
|
|
{
|
|
8002fb8: b580 push {r7, lr}
|
|
8002fba: b086 sub sp, #24
|
|
8002fbc: af00 add r7, sp, #0
|
|
8002fbe: 60f8 str r0, [r7, #12]
|
|
8002fc0: 60b9 str r1, [r7, #8]
|
|
8002fc2: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002fc4: 2300 movs r3, #0
|
|
8002fc6: 617b str r3, [r7, #20]
|
|
8002fc8: e009 b.n 8002fde <_write+0x26>
|
|
{
|
|
__io_putchar(*ptr++);
|
|
8002fca: 68bb ldr r3, [r7, #8]
|
|
8002fcc: 1c5a adds r2, r3, #1
|
|
8002fce: 60ba str r2, [r7, #8]
|
|
8002fd0: 781b ldrb r3, [r3, #0]
|
|
8002fd2: 4618 mov r0, r3
|
|
8002fd4: f7ff f8a8 bl 8002128 <__io_putchar>
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002fd8: 697b ldr r3, [r7, #20]
|
|
8002fda: 3301 adds r3, #1
|
|
8002fdc: 617b str r3, [r7, #20]
|
|
8002fde: 697a ldr r2, [r7, #20]
|
|
8002fe0: 687b ldr r3, [r7, #4]
|
|
8002fe2: 429a cmp r2, r3
|
|
8002fe4: dbf1 blt.n 8002fca <_write+0x12>
|
|
}
|
|
return len;
|
|
8002fe6: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002fe8: 4618 mov r0, r3
|
|
8002fea: 3718 adds r7, #24
|
|
8002fec: 46bd mov sp, r7
|
|
8002fee: bd80 pop {r7, pc}
|
|
|
|
08002ff0 <_close>:
|
|
|
|
int _close(int file)
|
|
{
|
|
8002ff0: b480 push {r7}
|
|
8002ff2: b083 sub sp, #12
|
|
8002ff4: af00 add r7, sp, #0
|
|
8002ff6: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return -1;
|
|
8002ff8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
8002ffc: 4618 mov r0, r3
|
|
8002ffe: 370c adds r7, #12
|
|
8003000: 46bd mov sp, r7
|
|
8003002: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003006: 4770 bx lr
|
|
|
|
08003008 <_fstat>:
|
|
|
|
|
|
int _fstat(int file, struct stat *st)
|
|
{
|
|
8003008: b480 push {r7}
|
|
800300a: b083 sub sp, #12
|
|
800300c: af00 add r7, sp, #0
|
|
800300e: 6078 str r0, [r7, #4]
|
|
8003010: 6039 str r1, [r7, #0]
|
|
(void)file;
|
|
st->st_mode = S_IFCHR;
|
|
8003012: 683b ldr r3, [r7, #0]
|
|
8003014: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
8003018: 605a str r2, [r3, #4]
|
|
return 0;
|
|
800301a: 2300 movs r3, #0
|
|
}
|
|
800301c: 4618 mov r0, r3
|
|
800301e: 370c adds r7, #12
|
|
8003020: 46bd mov sp, r7
|
|
8003022: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003026: 4770 bx lr
|
|
|
|
08003028 <_isatty>:
|
|
|
|
int _isatty(int file)
|
|
{
|
|
8003028: b480 push {r7}
|
|
800302a: b083 sub sp, #12
|
|
800302c: af00 add r7, sp, #0
|
|
800302e: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return 1;
|
|
8003030: 2301 movs r3, #1
|
|
}
|
|
8003032: 4618 mov r0, r3
|
|
8003034: 370c adds r7, #12
|
|
8003036: 46bd mov sp, r7
|
|
8003038: f85d 7b04 ldr.w r7, [sp], #4
|
|
800303c: 4770 bx lr
|
|
|
|
0800303e <_lseek>:
|
|
|
|
int _lseek(int file, int ptr, int dir)
|
|
{
|
|
800303e: b480 push {r7}
|
|
8003040: b085 sub sp, #20
|
|
8003042: af00 add r7, sp, #0
|
|
8003044: 60f8 str r0, [r7, #12]
|
|
8003046: 60b9 str r1, [r7, #8]
|
|
8003048: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
(void)ptr;
|
|
(void)dir;
|
|
return 0;
|
|
800304a: 2300 movs r3, #0
|
|
}
|
|
800304c: 4618 mov r0, r3
|
|
800304e: 3714 adds r7, #20
|
|
8003050: 46bd mov sp, r7
|
|
8003052: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003056: 4770 bx lr
|
|
|
|
08003058 <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
8003058: b580 push {r7, lr}
|
|
800305a: b086 sub sp, #24
|
|
800305c: af00 add r7, sp, #0
|
|
800305e: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
8003060: 4a14 ldr r2, [pc, #80] @ (80030b4 <_sbrk+0x5c>)
|
|
8003062: 4b15 ldr r3, [pc, #84] @ (80030b8 <_sbrk+0x60>)
|
|
8003064: 1ad3 subs r3, r2, r3
|
|
8003066: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
8003068: 697b ldr r3, [r7, #20]
|
|
800306a: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
800306c: 4b13 ldr r3, [pc, #76] @ (80030bc <_sbrk+0x64>)
|
|
800306e: 681b ldr r3, [r3, #0]
|
|
8003070: 2b00 cmp r3, #0
|
|
8003072: d102 bne.n 800307a <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
8003074: 4b11 ldr r3, [pc, #68] @ (80030bc <_sbrk+0x64>)
|
|
8003076: 4a12 ldr r2, [pc, #72] @ (80030c0 <_sbrk+0x68>)
|
|
8003078: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
800307a: 4b10 ldr r3, [pc, #64] @ (80030bc <_sbrk+0x64>)
|
|
800307c: 681a ldr r2, [r3, #0]
|
|
800307e: 687b ldr r3, [r7, #4]
|
|
8003080: 4413 add r3, r2
|
|
8003082: 693a ldr r2, [r7, #16]
|
|
8003084: 429a cmp r2, r3
|
|
8003086: d207 bcs.n 8003098 <_sbrk+0x40>
|
|
{
|
|
errno = ENOMEM;
|
|
8003088: f005 f93c bl 8008304 <__errno>
|
|
800308c: 4603 mov r3, r0
|
|
800308e: 220c movs r2, #12
|
|
8003090: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
8003092: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8003096: e009 b.n 80030ac <_sbrk+0x54>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
8003098: 4b08 ldr r3, [pc, #32] @ (80030bc <_sbrk+0x64>)
|
|
800309a: 681b ldr r3, [r3, #0]
|
|
800309c: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
800309e: 4b07 ldr r3, [pc, #28] @ (80030bc <_sbrk+0x64>)
|
|
80030a0: 681a ldr r2, [r3, #0]
|
|
80030a2: 687b ldr r3, [r7, #4]
|
|
80030a4: 4413 add r3, r2
|
|
80030a6: 4a05 ldr r2, [pc, #20] @ (80030bc <_sbrk+0x64>)
|
|
80030a8: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
80030aa: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80030ac: 4618 mov r0, r3
|
|
80030ae: 3718 adds r7, #24
|
|
80030b0: 46bd mov sp, r7
|
|
80030b2: bd80 pop {r7, pc}
|
|
80030b4: 20018000 .word 0x20018000
|
|
80030b8: 00000400 .word 0x00000400
|
|
80030bc: 20000a4c .word 0x20000a4c
|
|
80030c0: 20000bc8 .word 0x20000bc8
|
|
|
|
080030c4 <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
80030c4: b480 push {r7}
|
|
80030c6: af00 add r7, sp, #0
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
|
#endif
|
|
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
|
80030c8: 4b06 ldr r3, [pc, #24] @ (80030e4 <SystemInit+0x20>)
|
|
80030ca: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80030ce: 4a05 ldr r2, [pc, #20] @ (80030e4 <SystemInit+0x20>)
|
|
80030d0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
80030d4: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
#endif
|
|
}
|
|
80030d8: bf00 nop
|
|
80030da: 46bd mov sp, r7
|
|
80030dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80030e0: 4770 bx lr
|
|
80030e2: bf00 nop
|
|
80030e4: e000ed00 .word 0xe000ed00
|
|
|
|
080030e8 <Temperature_Test>:
|
|
*/
|
|
|
|
#include "temperature.h"
|
|
|
|
void Temperature_Test(void)
|
|
{
|
|
80030e8: b580 push {r7, lr}
|
|
80030ea: b082 sub sp, #8
|
|
80030ec: af00 add r7, sp, #0
|
|
float temp_value = 0;
|
|
80030ee: f04f 0300 mov.w r3, #0
|
|
80030f2: 607b str r3, [r7, #4]
|
|
BSP_TSENSOR_Init();
|
|
80030f4: f7fe f9ce bl 8001494 <BSP_TSENSOR_Init>
|
|
temp_value = BSP_TSENSOR_ReadTemp();
|
|
80030f8: f7fe f9e8 bl 80014cc <BSP_TSENSOR_ReadTemp>
|
|
80030fc: ed87 0a01 vstr s0, [r7, #4]
|
|
printf("TEMPERATURE is = %.2f ºC\n", temp_value);
|
|
8003100: 6878 ldr r0, [r7, #4]
|
|
8003102: f7fd fa21 bl 8000548 <__aeabi_f2d>
|
|
8003106: 4602 mov r2, r0
|
|
8003108: 460b mov r3, r1
|
|
800310a: 4803 ldr r0, [pc, #12] @ (8003118 <Temperature_Test+0x30>)
|
|
800310c: f004 ff60 bl 8007fd0 <iprintf>
|
|
}
|
|
8003110: bf00 nop
|
|
8003112: 3708 adds r7, #8
|
|
8003114: 46bd mov sp, r7
|
|
8003116: bd80 pop {r7, pc}
|
|
8003118: 0800a0bc .word 0x0800a0bc
|
|
|
|
0800311c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
800311c: f8df d034 ldr.w sp, [pc, #52] @ 8003154 <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8003120: f7ff ffd0 bl 80030c4 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8003124: 480c ldr r0, [pc, #48] @ (8003158 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
8003126: 490d ldr r1, [pc, #52] @ (800315c <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8003128: 4a0d ldr r2, [pc, #52] @ (8003160 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
800312a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800312c: e002 b.n 8003134 <LoopCopyDataInit>
|
|
|
|
0800312e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800312e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8003130: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8003132: 3304 adds r3, #4
|
|
|
|
08003134 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8003134: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8003136: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8003138: d3f9 bcc.n 800312e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800313a: 4a0a ldr r2, [pc, #40] @ (8003164 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
800313c: 4c0a ldr r4, [pc, #40] @ (8003168 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
800313e: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8003140: e001 b.n 8003146 <LoopFillZerobss>
|
|
|
|
08003142 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8003142: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8003144: 3204 adds r2, #4
|
|
|
|
08003146 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8003146: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8003148: d3fb bcc.n 8003142 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800314a: f005 f8e1 bl 8008310 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800314e: f7ff f801 bl 8002154 <main>
|
|
|
|
08003152 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
8003152: e7fe b.n 8003152 <LoopForever>
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8003154: 20018000 .word 0x20018000
|
|
ldr r0, =_sdata
|
|
8003158: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
800315c: 20000298 .word 0x20000298
|
|
ldr r2, =_sidata
|
|
8003160: 0800a4a4 .word 0x0800a4a4
|
|
ldr r2, =_sbss
|
|
8003164: 20000298 .word 0x20000298
|
|
ldr r4, =_ebss
|
|
8003168: 20000bc4 .word 0x20000bc4
|
|
|
|
0800316c <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
800316c: e7fe b.n 800316c <ADC1_2_IRQHandler>
|
|
|
|
0800316e <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
800316e: b580 push {r7, lr}
|
|
8003170: b082 sub sp, #8
|
|
8003172: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003174: 2300 movs r3, #0
|
|
8003176: 71fb strb r3, [r7, #7]
|
|
#if (PREFETCH_ENABLE != 0)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8003178: 2003 movs r0, #3
|
|
800317a: f000 f961 bl 8003440 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
800317e: 2000 movs r0, #0
|
|
8003180: f000 f80e bl 80031a0 <HAL_InitTick>
|
|
8003184: 4603 mov r3, r0
|
|
8003186: 2b00 cmp r3, #0
|
|
8003188: d002 beq.n 8003190 <HAL_Init+0x22>
|
|
{
|
|
status = HAL_ERROR;
|
|
800318a: 2301 movs r3, #1
|
|
800318c: 71fb strb r3, [r7, #7]
|
|
800318e: e001 b.n 8003194 <HAL_Init+0x26>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8003190: f7ff fba8 bl 80028e4 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8003194: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8003196: 4618 mov r0, r3
|
|
8003198: 3708 adds r7, #8
|
|
800319a: 46bd mov sp, r7
|
|
800319c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080031a0 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
80031a0: b580 push {r7, lr}
|
|
80031a2: b084 sub sp, #16
|
|
80031a4: af00 add r7, sp, #0
|
|
80031a6: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80031a8: 2300 movs r3, #0
|
|
80031aa: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
80031ac: 4b17 ldr r3, [pc, #92] @ (800320c <HAL_InitTick+0x6c>)
|
|
80031ae: 781b ldrb r3, [r3, #0]
|
|
80031b0: 2b00 cmp r3, #0
|
|
80031b2: d023 beq.n 80031fc <HAL_InitTick+0x5c>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
|
|
80031b4: 4b16 ldr r3, [pc, #88] @ (8003210 <HAL_InitTick+0x70>)
|
|
80031b6: 681a ldr r2, [r3, #0]
|
|
80031b8: 4b14 ldr r3, [pc, #80] @ (800320c <HAL_InitTick+0x6c>)
|
|
80031ba: 781b ldrb r3, [r3, #0]
|
|
80031bc: 4619 mov r1, r3
|
|
80031be: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80031c2: fbb3 f3f1 udiv r3, r3, r1
|
|
80031c6: fbb2 f3f3 udiv r3, r2, r3
|
|
80031ca: 4618 mov r0, r3
|
|
80031cc: f000 f96d bl 80034aa <HAL_SYSTICK_Config>
|
|
80031d0: 4603 mov r3, r0
|
|
80031d2: 2b00 cmp r3, #0
|
|
80031d4: d10f bne.n 80031f6 <HAL_InitTick+0x56>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80031d6: 687b ldr r3, [r7, #4]
|
|
80031d8: 2b0f cmp r3, #15
|
|
80031da: d809 bhi.n 80031f0 <HAL_InitTick+0x50>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80031dc: 2200 movs r2, #0
|
|
80031de: 6879 ldr r1, [r7, #4]
|
|
80031e0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80031e4: f000 f937 bl 8003456 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80031e8: 4a0a ldr r2, [pc, #40] @ (8003214 <HAL_InitTick+0x74>)
|
|
80031ea: 687b ldr r3, [r7, #4]
|
|
80031ec: 6013 str r3, [r2, #0]
|
|
80031ee: e007 b.n 8003200 <HAL_InitTick+0x60>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
80031f0: 2301 movs r3, #1
|
|
80031f2: 73fb strb r3, [r7, #15]
|
|
80031f4: e004 b.n 8003200 <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
80031f6: 2301 movs r3, #1
|
|
80031f8: 73fb strb r3, [r7, #15]
|
|
80031fa: e001 b.n 8003200 <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
80031fc: 2301 movs r3, #1
|
|
80031fe: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8003200: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8003202: 4618 mov r0, r3
|
|
8003204: 3710 adds r7, #16
|
|
8003206: 46bd mov sp, r7
|
|
8003208: bd80 pop {r7, pc}
|
|
800320a: bf00 nop
|
|
800320c: 200000cc .word 0x200000cc
|
|
8003210: 200000c4 .word 0x200000c4
|
|
8003214: 200000c8 .word 0x200000c8
|
|
|
|
08003218 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8003218: b480 push {r7}
|
|
800321a: af00 add r7, sp, #0
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
800321c: 4b06 ldr r3, [pc, #24] @ (8003238 <HAL_IncTick+0x20>)
|
|
800321e: 781b ldrb r3, [r3, #0]
|
|
8003220: 461a mov r2, r3
|
|
8003222: 4b06 ldr r3, [pc, #24] @ (800323c <HAL_IncTick+0x24>)
|
|
8003224: 681b ldr r3, [r3, #0]
|
|
8003226: 4413 add r3, r2
|
|
8003228: 4a04 ldr r2, [pc, #16] @ (800323c <HAL_IncTick+0x24>)
|
|
800322a: 6013 str r3, [r2, #0]
|
|
}
|
|
800322c: bf00 nop
|
|
800322e: 46bd mov sp, r7
|
|
8003230: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003234: 4770 bx lr
|
|
8003236: bf00 nop
|
|
8003238: 200000cc .word 0x200000cc
|
|
800323c: 20000a50 .word 0x20000a50
|
|
|
|
08003240 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8003240: b480 push {r7}
|
|
8003242: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8003244: 4b03 ldr r3, [pc, #12] @ (8003254 <HAL_GetTick+0x14>)
|
|
8003246: 681b ldr r3, [r3, #0]
|
|
}
|
|
8003248: 4618 mov r0, r3
|
|
800324a: 46bd mov sp, r7
|
|
800324c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003250: 4770 bx lr
|
|
8003252: bf00 nop
|
|
8003254: 20000a50 .word 0x20000a50
|
|
|
|
08003258 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8003258: b580 push {r7, lr}
|
|
800325a: b084 sub sp, #16
|
|
800325c: af00 add r7, sp, #0
|
|
800325e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8003260: f7ff ffee bl 8003240 <HAL_GetTick>
|
|
8003264: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8003266: 687b ldr r3, [r7, #4]
|
|
8003268: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a period to guaranty minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
800326a: 68fb ldr r3, [r7, #12]
|
|
800326c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8003270: d005 beq.n 800327e <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)uwTickFreq;
|
|
8003272: 4b0a ldr r3, [pc, #40] @ (800329c <HAL_Delay+0x44>)
|
|
8003274: 781b ldrb r3, [r3, #0]
|
|
8003276: 461a mov r2, r3
|
|
8003278: 68fb ldr r3, [r7, #12]
|
|
800327a: 4413 add r3, r2
|
|
800327c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
800327e: bf00 nop
|
|
8003280: f7ff ffde bl 8003240 <HAL_GetTick>
|
|
8003284: 4602 mov r2, r0
|
|
8003286: 68bb ldr r3, [r7, #8]
|
|
8003288: 1ad3 subs r3, r2, r3
|
|
800328a: 68fa ldr r2, [r7, #12]
|
|
800328c: 429a cmp r2, r3
|
|
800328e: d8f7 bhi.n 8003280 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8003290: bf00 nop
|
|
8003292: bf00 nop
|
|
8003294: 3710 adds r7, #16
|
|
8003296: 46bd mov sp, r7
|
|
8003298: bd80 pop {r7, pc}
|
|
800329a: bf00 nop
|
|
800329c: 200000cc .word 0x200000cc
|
|
|
|
080032a0 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80032a0: b480 push {r7}
|
|
80032a2: b085 sub sp, #20
|
|
80032a4: af00 add r7, sp, #0
|
|
80032a6: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80032a8: 687b ldr r3, [r7, #4]
|
|
80032aa: f003 0307 and.w r3, r3, #7
|
|
80032ae: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80032b0: 4b0c ldr r3, [pc, #48] @ (80032e4 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80032b2: 68db ldr r3, [r3, #12]
|
|
80032b4: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80032b6: 68ba ldr r2, [r7, #8]
|
|
80032b8: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80032bc: 4013 ands r3, r2
|
|
80032be: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80032c0: 68fb ldr r3, [r7, #12]
|
|
80032c2: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80032c4: 68bb ldr r3, [r7, #8]
|
|
80032c6: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80032c8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80032cc: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80032d0: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80032d2: 4a04 ldr r2, [pc, #16] @ (80032e4 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80032d4: 68bb ldr r3, [r7, #8]
|
|
80032d6: 60d3 str r3, [r2, #12]
|
|
}
|
|
80032d8: bf00 nop
|
|
80032da: 3714 adds r7, #20
|
|
80032dc: 46bd mov sp, r7
|
|
80032de: f85d 7b04 ldr.w r7, [sp], #4
|
|
80032e2: 4770 bx lr
|
|
80032e4: e000ed00 .word 0xe000ed00
|
|
|
|
080032e8 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80032e8: b480 push {r7}
|
|
80032ea: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80032ec: 4b04 ldr r3, [pc, #16] @ (8003300 <__NVIC_GetPriorityGrouping+0x18>)
|
|
80032ee: 68db ldr r3, [r3, #12]
|
|
80032f0: 0a1b lsrs r3, r3, #8
|
|
80032f2: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80032f6: 4618 mov r0, r3
|
|
80032f8: 46bd mov sp, r7
|
|
80032fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80032fe: 4770 bx lr
|
|
8003300: e000ed00 .word 0xe000ed00
|
|
|
|
08003304 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8003304: b480 push {r7}
|
|
8003306: b083 sub sp, #12
|
|
8003308: af00 add r7, sp, #0
|
|
800330a: 4603 mov r3, r0
|
|
800330c: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800330e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003312: 2b00 cmp r3, #0
|
|
8003314: db0b blt.n 800332e <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8003316: 79fb ldrb r3, [r7, #7]
|
|
8003318: f003 021f and.w r2, r3, #31
|
|
800331c: 4907 ldr r1, [pc, #28] @ (800333c <__NVIC_EnableIRQ+0x38>)
|
|
800331e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003322: 095b lsrs r3, r3, #5
|
|
8003324: 2001 movs r0, #1
|
|
8003326: fa00 f202 lsl.w r2, r0, r2
|
|
800332a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
800332e: bf00 nop
|
|
8003330: 370c adds r7, #12
|
|
8003332: 46bd mov sp, r7
|
|
8003334: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003338: 4770 bx lr
|
|
800333a: bf00 nop
|
|
800333c: e000e100 .word 0xe000e100
|
|
|
|
08003340 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8003340: b480 push {r7}
|
|
8003342: b083 sub sp, #12
|
|
8003344: af00 add r7, sp, #0
|
|
8003346: 4603 mov r3, r0
|
|
8003348: 6039 str r1, [r7, #0]
|
|
800334a: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800334c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003350: 2b00 cmp r3, #0
|
|
8003352: db0a blt.n 800336a <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8003354: 683b ldr r3, [r7, #0]
|
|
8003356: b2da uxtb r2, r3
|
|
8003358: 490c ldr r1, [pc, #48] @ (800338c <__NVIC_SetPriority+0x4c>)
|
|
800335a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800335e: 0112 lsls r2, r2, #4
|
|
8003360: b2d2 uxtb r2, r2
|
|
8003362: 440b add r3, r1
|
|
8003364: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8003368: e00a b.n 8003380 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800336a: 683b ldr r3, [r7, #0]
|
|
800336c: b2da uxtb r2, r3
|
|
800336e: 4908 ldr r1, [pc, #32] @ (8003390 <__NVIC_SetPriority+0x50>)
|
|
8003370: 79fb ldrb r3, [r7, #7]
|
|
8003372: f003 030f and.w r3, r3, #15
|
|
8003376: 3b04 subs r3, #4
|
|
8003378: 0112 lsls r2, r2, #4
|
|
800337a: b2d2 uxtb r2, r2
|
|
800337c: 440b add r3, r1
|
|
800337e: 761a strb r2, [r3, #24]
|
|
}
|
|
8003380: bf00 nop
|
|
8003382: 370c adds r7, #12
|
|
8003384: 46bd mov sp, r7
|
|
8003386: f85d 7b04 ldr.w r7, [sp], #4
|
|
800338a: 4770 bx lr
|
|
800338c: e000e100 .word 0xe000e100
|
|
8003390: e000ed00 .word 0xe000ed00
|
|
|
|
08003394 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8003394: b480 push {r7}
|
|
8003396: b089 sub sp, #36 @ 0x24
|
|
8003398: af00 add r7, sp, #0
|
|
800339a: 60f8 str r0, [r7, #12]
|
|
800339c: 60b9 str r1, [r7, #8]
|
|
800339e: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80033a0: 68fb ldr r3, [r7, #12]
|
|
80033a2: f003 0307 and.w r3, r3, #7
|
|
80033a6: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
80033a8: 69fb ldr r3, [r7, #28]
|
|
80033aa: f1c3 0307 rsb r3, r3, #7
|
|
80033ae: 2b04 cmp r3, #4
|
|
80033b0: bf28 it cs
|
|
80033b2: 2304 movcs r3, #4
|
|
80033b4: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80033b6: 69fb ldr r3, [r7, #28]
|
|
80033b8: 3304 adds r3, #4
|
|
80033ba: 2b06 cmp r3, #6
|
|
80033bc: d902 bls.n 80033c4 <NVIC_EncodePriority+0x30>
|
|
80033be: 69fb ldr r3, [r7, #28]
|
|
80033c0: 3b03 subs r3, #3
|
|
80033c2: e000 b.n 80033c6 <NVIC_EncodePriority+0x32>
|
|
80033c4: 2300 movs r3, #0
|
|
80033c6: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80033c8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80033cc: 69bb ldr r3, [r7, #24]
|
|
80033ce: fa02 f303 lsl.w r3, r2, r3
|
|
80033d2: 43da mvns r2, r3
|
|
80033d4: 68bb ldr r3, [r7, #8]
|
|
80033d6: 401a ands r2, r3
|
|
80033d8: 697b ldr r3, [r7, #20]
|
|
80033da: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80033dc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80033e0: 697b ldr r3, [r7, #20]
|
|
80033e2: fa01 f303 lsl.w r3, r1, r3
|
|
80033e6: 43d9 mvns r1, r3
|
|
80033e8: 687b ldr r3, [r7, #4]
|
|
80033ea: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80033ec: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80033ee: 4618 mov r0, r3
|
|
80033f0: 3724 adds r7, #36 @ 0x24
|
|
80033f2: 46bd mov sp, r7
|
|
80033f4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80033f8: 4770 bx lr
|
|
...
|
|
|
|
080033fc <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80033fc: b580 push {r7, lr}
|
|
80033fe: b082 sub sp, #8
|
|
8003400: af00 add r7, sp, #0
|
|
8003402: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8003404: 687b ldr r3, [r7, #4]
|
|
8003406: 3b01 subs r3, #1
|
|
8003408: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
800340c: d301 bcc.n 8003412 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
800340e: 2301 movs r3, #1
|
|
8003410: e00f b.n 8003432 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8003412: 4a0a ldr r2, [pc, #40] @ (800343c <SysTick_Config+0x40>)
|
|
8003414: 687b ldr r3, [r7, #4]
|
|
8003416: 3b01 subs r3, #1
|
|
8003418: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
800341a: 210f movs r1, #15
|
|
800341c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8003420: f7ff ff8e bl 8003340 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8003424: 4b05 ldr r3, [pc, #20] @ (800343c <SysTick_Config+0x40>)
|
|
8003426: 2200 movs r2, #0
|
|
8003428: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
800342a: 4b04 ldr r3, [pc, #16] @ (800343c <SysTick_Config+0x40>)
|
|
800342c: 2207 movs r2, #7
|
|
800342e: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8003430: 2300 movs r3, #0
|
|
}
|
|
8003432: 4618 mov r0, r3
|
|
8003434: 3708 adds r7, #8
|
|
8003436: 46bd mov sp, r7
|
|
8003438: bd80 pop {r7, pc}
|
|
800343a: bf00 nop
|
|
800343c: e000e010 .word 0xe000e010
|
|
|
|
08003440 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8003440: b580 push {r7, lr}
|
|
8003442: b082 sub sp, #8
|
|
8003444: af00 add r7, sp, #0
|
|
8003446: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8003448: 6878 ldr r0, [r7, #4]
|
|
800344a: f7ff ff29 bl 80032a0 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
800344e: bf00 nop
|
|
8003450: 3708 adds r7, #8
|
|
8003452: 46bd mov sp, r7
|
|
8003454: bd80 pop {r7, pc}
|
|
|
|
08003456 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8003456: b580 push {r7, lr}
|
|
8003458: b086 sub sp, #24
|
|
800345a: af00 add r7, sp, #0
|
|
800345c: 4603 mov r3, r0
|
|
800345e: 60b9 str r1, [r7, #8]
|
|
8003460: 607a str r2, [r7, #4]
|
|
8003462: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8003464: 2300 movs r3, #0
|
|
8003466: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8003468: f7ff ff3e bl 80032e8 <__NVIC_GetPriorityGrouping>
|
|
800346c: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
800346e: 687a ldr r2, [r7, #4]
|
|
8003470: 68b9 ldr r1, [r7, #8]
|
|
8003472: 6978 ldr r0, [r7, #20]
|
|
8003474: f7ff ff8e bl 8003394 <NVIC_EncodePriority>
|
|
8003478: 4602 mov r2, r0
|
|
800347a: f997 300f ldrsb.w r3, [r7, #15]
|
|
800347e: 4611 mov r1, r2
|
|
8003480: 4618 mov r0, r3
|
|
8003482: f7ff ff5d bl 8003340 <__NVIC_SetPriority>
|
|
}
|
|
8003486: bf00 nop
|
|
8003488: 3718 adds r7, #24
|
|
800348a: 46bd mov sp, r7
|
|
800348c: bd80 pop {r7, pc}
|
|
|
|
0800348e <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
800348e: b580 push {r7, lr}
|
|
8003490: b082 sub sp, #8
|
|
8003492: af00 add r7, sp, #0
|
|
8003494: 4603 mov r3, r0
|
|
8003496: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8003498: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800349c: 4618 mov r0, r3
|
|
800349e: f7ff ff31 bl 8003304 <__NVIC_EnableIRQ>
|
|
}
|
|
80034a2: bf00 nop
|
|
80034a4: 3708 adds r7, #8
|
|
80034a6: 46bd mov sp, r7
|
|
80034a8: bd80 pop {r7, pc}
|
|
|
|
080034aa <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
80034aa: b580 push {r7, lr}
|
|
80034ac: b082 sub sp, #8
|
|
80034ae: af00 add r7, sp, #0
|
|
80034b0: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
80034b2: 6878 ldr r0, [r7, #4]
|
|
80034b4: f7ff ffa2 bl 80033fc <SysTick_Config>
|
|
80034b8: 4603 mov r3, r0
|
|
}
|
|
80034ba: 4618 mov r0, r3
|
|
80034bc: 3708 adds r7, #8
|
|
80034be: 46bd mov sp, r7
|
|
80034c0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080034c4 <HAL_DFSDM_ChannelInit>:
|
|
* in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
|
|
* @param hdfsdm_channel DFSDM channel handle.
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
|
|
{
|
|
80034c4: b580 push {r7, lr}
|
|
80034c6: b082 sub sp, #8
|
|
80034c8: af00 add r7, sp, #0
|
|
80034ca: 6078 str r0, [r7, #4]
|
|
/* Check DFSDM Channel handle */
|
|
if (hdfsdm_channel == NULL)
|
|
80034cc: 687b ldr r3, [r7, #4]
|
|
80034ce: 2b00 cmp r3, #0
|
|
80034d0: d101 bne.n 80034d6 <HAL_DFSDM_ChannelInit+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80034d2: 2301 movs r3, #1
|
|
80034d4: e0ac b.n 8003630 <HAL_DFSDM_ChannelInit+0x16c>
|
|
assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
|
|
assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
|
|
assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
|
|
|
|
/* Check that channel has not been already initialized */
|
|
if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
|
|
80034d6: 687b ldr r3, [r7, #4]
|
|
80034d8: 681b ldr r3, [r3, #0]
|
|
80034da: 4618 mov r0, r3
|
|
80034dc: f000 f8b2 bl 8003644 <DFSDM_GetChannelFromInstance>
|
|
80034e0: 4603 mov r3, r0
|
|
80034e2: 4a55 ldr r2, [pc, #340] @ (8003638 <HAL_DFSDM_ChannelInit+0x174>)
|
|
80034e4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80034e8: 2b00 cmp r3, #0
|
|
80034ea: d001 beq.n 80034f0 <HAL_DFSDM_ChannelInit+0x2c>
|
|
{
|
|
return HAL_ERROR;
|
|
80034ec: 2301 movs r3, #1
|
|
80034ee: e09f b.n 8003630 <HAL_DFSDM_ChannelInit+0x16c>
|
|
hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
|
|
}
|
|
hdfsdm_channel->MspInitCallback(hdfsdm_channel);
|
|
#else
|
|
/* Call MSP init function */
|
|
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
|
|
80034f0: 6878 ldr r0, [r7, #4]
|
|
80034f2: f7ff fa1b bl 800292c <HAL_DFSDM_ChannelMspInit>
|
|
#endif
|
|
|
|
/* Update the channel counter */
|
|
v_dfsdm1ChannelCounter++;
|
|
80034f6: 4b51 ldr r3, [pc, #324] @ (800363c <HAL_DFSDM_ChannelInit+0x178>)
|
|
80034f8: 681b ldr r3, [r3, #0]
|
|
80034fa: 3301 adds r3, #1
|
|
80034fc: 4a4f ldr r2, [pc, #316] @ (800363c <HAL_DFSDM_ChannelInit+0x178>)
|
|
80034fe: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure output serial clock and enable global DFSDM interface only for first channel */
|
|
if (v_dfsdm1ChannelCounter == 1U)
|
|
8003500: 4b4e ldr r3, [pc, #312] @ (800363c <HAL_DFSDM_ChannelInit+0x178>)
|
|
8003502: 681b ldr r3, [r3, #0]
|
|
8003504: 2b01 cmp r3, #1
|
|
8003506: d125 bne.n 8003554 <HAL_DFSDM_ChannelInit+0x90>
|
|
{
|
|
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
|
|
/* Set the output serial clock source */
|
|
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
|
|
8003508: 4b4d ldr r3, [pc, #308] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
800350a: 681b ldr r3, [r3, #0]
|
|
800350c: 4a4c ldr r2, [pc, #304] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
800350e: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8003512: 6013 str r3, [r2, #0]
|
|
DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
|
|
8003514: 4b4a ldr r3, [pc, #296] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003516: 681a ldr r2, [r3, #0]
|
|
8003518: 687b ldr r3, [r7, #4]
|
|
800351a: 689b ldr r3, [r3, #8]
|
|
800351c: 4948 ldr r1, [pc, #288] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
800351e: 4313 orrs r3, r2
|
|
8003520: 600b str r3, [r1, #0]
|
|
|
|
/* Reset clock divider */
|
|
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
|
|
8003522: 4b47 ldr r3, [pc, #284] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003524: 681b ldr r3, [r3, #0]
|
|
8003526: 4a46 ldr r2, [pc, #280] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003528: f423 037f bic.w r3, r3, #16711680 @ 0xff0000
|
|
800352c: 6013 str r3, [r2, #0]
|
|
if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
|
|
800352e: 687b ldr r3, [r7, #4]
|
|
8003530: 791b ldrb r3, [r3, #4]
|
|
8003532: 2b01 cmp r3, #1
|
|
8003534: d108 bne.n 8003548 <HAL_DFSDM_ChannelInit+0x84>
|
|
{
|
|
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
|
|
/* Set the output clock divider */
|
|
DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
|
|
8003536: 4b42 ldr r3, [pc, #264] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003538: 681a ldr r2, [r3, #0]
|
|
800353a: 687b ldr r3, [r7, #4]
|
|
800353c: 68db ldr r3, [r3, #12]
|
|
800353e: 3b01 subs r3, #1
|
|
8003540: 041b lsls r3, r3, #16
|
|
8003542: 493f ldr r1, [pc, #252] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
8003544: 4313 orrs r3, r2
|
|
8003546: 600b str r3, [r1, #0]
|
|
DFSDM_CHCFGR1_CKOUTDIV_Pos);
|
|
}
|
|
|
|
/* enable the DFSDM global interface */
|
|
DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
|
|
8003548: 4b3d ldr r3, [pc, #244] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
800354a: 681b ldr r3, [r3, #0]
|
|
800354c: 4a3c ldr r2, [pc, #240] @ (8003640 <HAL_DFSDM_ChannelInit+0x17c>)
|
|
800354e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8003552: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
/* Set channel input parameters */
|
|
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
|
|
8003554: 687b ldr r3, [r7, #4]
|
|
8003556: 681b ldr r3, [r3, #0]
|
|
8003558: 681a ldr r2, [r3, #0]
|
|
800355a: 687b ldr r3, [r7, #4]
|
|
800355c: 681b ldr r3, [r3, #0]
|
|
800355e: f422 4271 bic.w r2, r2, #61696 @ 0xf100
|
|
8003562: 601a str r2, [r3, #0]
|
|
DFSDM_CHCFGR1_CHINSEL);
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
|
|
8003564: 687b ldr r3, [r7, #4]
|
|
8003566: 681b ldr r3, [r3, #0]
|
|
8003568: 6819 ldr r1, [r3, #0]
|
|
800356a: 687b ldr r3, [r7, #4]
|
|
800356c: 691a ldr r2, [r3, #16]
|
|
hdfsdm_channel->Init.Input.DataPacking |
|
|
800356e: 687b ldr r3, [r7, #4]
|
|
8003570: 695b ldr r3, [r3, #20]
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
|
|
8003572: 431a orrs r2, r3
|
|
hdfsdm_channel->Init.Input.Pins);
|
|
8003574: 687b ldr r3, [r7, #4]
|
|
8003576: 699b ldr r3, [r3, #24]
|
|
hdfsdm_channel->Init.Input.DataPacking |
|
|
8003578: 431a orrs r2, r3
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
|
|
800357a: 687b ldr r3, [r7, #4]
|
|
800357c: 681b ldr r3, [r3, #0]
|
|
800357e: 430a orrs r2, r1
|
|
8003580: 601a str r2, [r3, #0]
|
|
|
|
/* Set serial interface parameters */
|
|
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
|
|
8003582: 687b ldr r3, [r7, #4]
|
|
8003584: 681b ldr r3, [r3, #0]
|
|
8003586: 681a ldr r2, [r3, #0]
|
|
8003588: 687b ldr r3, [r7, #4]
|
|
800358a: 681b ldr r3, [r3, #0]
|
|
800358c: f022 020f bic.w r2, r2, #15
|
|
8003590: 601a str r2, [r3, #0]
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
|
|
8003592: 687b ldr r3, [r7, #4]
|
|
8003594: 681b ldr r3, [r3, #0]
|
|
8003596: 6819 ldr r1, [r3, #0]
|
|
8003598: 687b ldr r3, [r7, #4]
|
|
800359a: 69da ldr r2, [r3, #28]
|
|
hdfsdm_channel->Init.SerialInterface.SpiClock);
|
|
800359c: 687b ldr r3, [r7, #4]
|
|
800359e: 6a1b ldr r3, [r3, #32]
|
|
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
|
|
80035a0: 431a orrs r2, r3
|
|
80035a2: 687b ldr r3, [r7, #4]
|
|
80035a4: 681b ldr r3, [r3, #0]
|
|
80035a6: 430a orrs r2, r1
|
|
80035a8: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog watchdog parameters */
|
|
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
|
|
80035aa: 687b ldr r3, [r7, #4]
|
|
80035ac: 681b ldr r3, [r3, #0]
|
|
80035ae: 689a ldr r2, [r3, #8]
|
|
80035b0: 687b ldr r3, [r7, #4]
|
|
80035b2: 681b ldr r3, [r3, #0]
|
|
80035b4: f422 025f bic.w r2, r2, #14614528 @ 0xdf0000
|
|
80035b8: 609a str r2, [r3, #8]
|
|
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
|
|
80035ba: 687b ldr r3, [r7, #4]
|
|
80035bc: 681b ldr r3, [r3, #0]
|
|
80035be: 6899 ldr r1, [r3, #8]
|
|
80035c0: 687b ldr r3, [r7, #4]
|
|
80035c2: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
|
|
80035c4: 687b ldr r3, [r7, #4]
|
|
80035c6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80035c8: 3b01 subs r3, #1
|
|
80035ca: 041b lsls r3, r3, #16
|
|
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
|
|
80035cc: 431a orrs r2, r3
|
|
80035ce: 687b ldr r3, [r7, #4]
|
|
80035d0: 681b ldr r3, [r3, #0]
|
|
80035d2: 430a orrs r2, r1
|
|
80035d4: 609a str r2, [r3, #8]
|
|
|
|
/* Set channel offset and right bit shift */
|
|
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
|
|
80035d6: 687b ldr r3, [r7, #4]
|
|
80035d8: 681b ldr r3, [r3, #0]
|
|
80035da: 685a ldr r2, [r3, #4]
|
|
80035dc: 687b ldr r3, [r7, #4]
|
|
80035de: 681b ldr r3, [r3, #0]
|
|
80035e0: f002 0207 and.w r2, r2, #7
|
|
80035e4: 605a str r2, [r3, #4]
|
|
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
|
|
80035e6: 687b ldr r3, [r7, #4]
|
|
80035e8: 681b ldr r3, [r3, #0]
|
|
80035ea: 6859 ldr r1, [r3, #4]
|
|
80035ec: 687b ldr r3, [r7, #4]
|
|
80035ee: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80035f0: 021a lsls r2, r3, #8
|
|
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
|
|
80035f2: 687b ldr r3, [r7, #4]
|
|
80035f4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80035f6: 00db lsls r3, r3, #3
|
|
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
|
|
80035f8: 431a orrs r2, r3
|
|
80035fa: 687b ldr r3, [r7, #4]
|
|
80035fc: 681b ldr r3, [r3, #0]
|
|
80035fe: 430a orrs r2, r1
|
|
8003600: 605a str r2, [r3, #4]
|
|
|
|
/* Enable DFSDM channel */
|
|
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
|
|
8003602: 687b ldr r3, [r7, #4]
|
|
8003604: 681b ldr r3, [r3, #0]
|
|
8003606: 681a ldr r2, [r3, #0]
|
|
8003608: 687b ldr r3, [r7, #4]
|
|
800360a: 681b ldr r3, [r3, #0]
|
|
800360c: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
8003610: 601a str r2, [r3, #0]
|
|
|
|
/* Set DFSDM Channel to ready state */
|
|
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
|
|
8003612: 687b ldr r3, [r7, #4]
|
|
8003614: 2201 movs r2, #1
|
|
8003616: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
/* Store channel handle in DFSDM channel handle table */
|
|
a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
|
|
800361a: 687b ldr r3, [r7, #4]
|
|
800361c: 681b ldr r3, [r3, #0]
|
|
800361e: 4618 mov r0, r3
|
|
8003620: f000 f810 bl 8003644 <DFSDM_GetChannelFromInstance>
|
|
8003624: 4602 mov r2, r0
|
|
8003626: 4904 ldr r1, [pc, #16] @ (8003638 <HAL_DFSDM_ChannelInit+0x174>)
|
|
8003628: 687b ldr r3, [r7, #4]
|
|
800362a: f841 3022 str.w r3, [r1, r2, lsl #2]
|
|
|
|
return HAL_OK;
|
|
800362e: 2300 movs r3, #0
|
|
}
|
|
8003630: 4618 mov r0, r3
|
|
8003632: 3708 adds r7, #8
|
|
8003634: 46bd mov sp, r7
|
|
8003636: bd80 pop {r7, pc}
|
|
8003638: 20000a58 .word 0x20000a58
|
|
800363c: 20000a54 .word 0x20000a54
|
|
8003640: 40016000 .word 0x40016000
|
|
|
|
08003644 <DFSDM_GetChannelFromInstance>:
|
|
* @brief This function allows to get the channel number from channel instance.
|
|
* @param Instance DFSDM channel instance.
|
|
* @retval Channel number.
|
|
*/
|
|
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
|
|
{
|
|
8003644: b480 push {r7}
|
|
8003646: b085 sub sp, #20
|
|
8003648: af00 add r7, sp, #0
|
|
800364a: 6078 str r0, [r7, #4]
|
|
uint32_t channel;
|
|
|
|
/* Get channel from instance */
|
|
if (Instance == DFSDM1_Channel0)
|
|
800364c: 687b ldr r3, [r7, #4]
|
|
800364e: 4a1c ldr r2, [pc, #112] @ (80036c0 <DFSDM_GetChannelFromInstance+0x7c>)
|
|
8003650: 4293 cmp r3, r2
|
|
8003652: d102 bne.n 800365a <DFSDM_GetChannelFromInstance+0x16>
|
|
{
|
|
channel = 0;
|
|
8003654: 2300 movs r3, #0
|
|
8003656: 60fb str r3, [r7, #12]
|
|
8003658: e02b b.n 80036b2 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel1)
|
|
800365a: 687b ldr r3, [r7, #4]
|
|
800365c: 4a19 ldr r2, [pc, #100] @ (80036c4 <DFSDM_GetChannelFromInstance+0x80>)
|
|
800365e: 4293 cmp r3, r2
|
|
8003660: d102 bne.n 8003668 <DFSDM_GetChannelFromInstance+0x24>
|
|
{
|
|
channel = 1;
|
|
8003662: 2301 movs r3, #1
|
|
8003664: 60fb str r3, [r7, #12]
|
|
8003666: e024 b.n 80036b2 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel2)
|
|
8003668: 687b ldr r3, [r7, #4]
|
|
800366a: 4a17 ldr r2, [pc, #92] @ (80036c8 <DFSDM_GetChannelFromInstance+0x84>)
|
|
800366c: 4293 cmp r3, r2
|
|
800366e: d102 bne.n 8003676 <DFSDM_GetChannelFromInstance+0x32>
|
|
{
|
|
channel = 2;
|
|
8003670: 2302 movs r3, #2
|
|
8003672: 60fb str r3, [r7, #12]
|
|
8003674: e01d b.n 80036b2 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
|
|
defined(STM32L496xx) || defined(STM32L4A6xx) || \
|
|
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
|
else if (Instance == DFSDM1_Channel4)
|
|
8003676: 687b ldr r3, [r7, #4]
|
|
8003678: 4a14 ldr r2, [pc, #80] @ (80036cc <DFSDM_GetChannelFromInstance+0x88>)
|
|
800367a: 4293 cmp r3, r2
|
|
800367c: d102 bne.n 8003684 <DFSDM_GetChannelFromInstance+0x40>
|
|
{
|
|
channel = 4;
|
|
800367e: 2304 movs r3, #4
|
|
8003680: 60fb str r3, [r7, #12]
|
|
8003682: e016 b.n 80036b2 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel5)
|
|
8003684: 687b ldr r3, [r7, #4]
|
|
8003686: 4a12 ldr r2, [pc, #72] @ (80036d0 <DFSDM_GetChannelFromInstance+0x8c>)
|
|
8003688: 4293 cmp r3, r2
|
|
800368a: d102 bne.n 8003692 <DFSDM_GetChannelFromInstance+0x4e>
|
|
{
|
|
channel = 5;
|
|
800368c: 2305 movs r3, #5
|
|
800368e: 60fb str r3, [r7, #12]
|
|
8003690: e00f b.n 80036b2 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel6)
|
|
8003692: 687b ldr r3, [r7, #4]
|
|
8003694: 4a0f ldr r2, [pc, #60] @ (80036d4 <DFSDM_GetChannelFromInstance+0x90>)
|
|
8003696: 4293 cmp r3, r2
|
|
8003698: d102 bne.n 80036a0 <DFSDM_GetChannelFromInstance+0x5c>
|
|
{
|
|
channel = 6;
|
|
800369a: 2306 movs r3, #6
|
|
800369c: 60fb str r3, [r7, #12]
|
|
800369e: e008 b.n 80036b2 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
else if (Instance == DFSDM1_Channel7)
|
|
80036a0: 687b ldr r3, [r7, #4]
|
|
80036a2: 4a0d ldr r2, [pc, #52] @ (80036d8 <DFSDM_GetChannelFromInstance+0x94>)
|
|
80036a4: 4293 cmp r3, r2
|
|
80036a6: d102 bne.n 80036ae <DFSDM_GetChannelFromInstance+0x6a>
|
|
{
|
|
channel = 7;
|
|
80036a8: 2307 movs r3, #7
|
|
80036aa: 60fb str r3, [r7, #12]
|
|
80036ac: e001 b.n 80036b2 <DFSDM_GetChannelFromInstance+0x6e>
|
|
}
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
else /* DFSDM1_Channel3 */
|
|
{
|
|
channel = 3;
|
|
80036ae: 2303 movs r3, #3
|
|
80036b0: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return channel;
|
|
80036b2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80036b4: 4618 mov r0, r3
|
|
80036b6: 3714 adds r7, #20
|
|
80036b8: 46bd mov sp, r7
|
|
80036ba: f85d 7b04 ldr.w r7, [sp], #4
|
|
80036be: 4770 bx lr
|
|
80036c0: 40016000 .word 0x40016000
|
|
80036c4: 40016020 .word 0x40016020
|
|
80036c8: 40016040 .word 0x40016040
|
|
80036cc: 40016080 .word 0x40016080
|
|
80036d0: 400160a0 .word 0x400160a0
|
|
80036d4: 400160c0 .word 0x400160c0
|
|
80036d8: 400160e0 .word 0x400160e0
|
|
|
|
080036dc <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80036dc: b480 push {r7}
|
|
80036de: b087 sub sp, #28
|
|
80036e0: af00 add r7, sp, #0
|
|
80036e2: 6078 str r0, [r7, #4]
|
|
80036e4: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
80036e6: 2300 movs r3, #0
|
|
80036e8: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80036ea: e17f b.n 80039ec <HAL_GPIO_Init+0x310>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
80036ec: 683b ldr r3, [r7, #0]
|
|
80036ee: 681a ldr r2, [r3, #0]
|
|
80036f0: 2101 movs r1, #1
|
|
80036f2: 697b ldr r3, [r7, #20]
|
|
80036f4: fa01 f303 lsl.w r3, r1, r3
|
|
80036f8: 4013 ands r3, r2
|
|
80036fa: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
80036fc: 68fb ldr r3, [r7, #12]
|
|
80036fe: 2b00 cmp r3, #0
|
|
8003700: f000 8171 beq.w 80039e6 <HAL_GPIO_Init+0x30a>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
8003704: 683b ldr r3, [r7, #0]
|
|
8003706: 685b ldr r3, [r3, #4]
|
|
8003708: f003 0303 and.w r3, r3, #3
|
|
800370c: 2b01 cmp r3, #1
|
|
800370e: d005 beq.n 800371c <HAL_GPIO_Init+0x40>
|
|
8003710: 683b ldr r3, [r7, #0]
|
|
8003712: 685b ldr r3, [r3, #4]
|
|
8003714: f003 0303 and.w r3, r3, #3
|
|
8003718: 2b02 cmp r3, #2
|
|
800371a: d130 bne.n 800377e <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
800371c: 687b ldr r3, [r7, #4]
|
|
800371e: 689b ldr r3, [r3, #8]
|
|
8003720: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
8003722: 697b ldr r3, [r7, #20]
|
|
8003724: 005b lsls r3, r3, #1
|
|
8003726: 2203 movs r2, #3
|
|
8003728: fa02 f303 lsl.w r3, r2, r3
|
|
800372c: 43db mvns r3, r3
|
|
800372e: 693a ldr r2, [r7, #16]
|
|
8003730: 4013 ands r3, r2
|
|
8003732: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
8003734: 683b ldr r3, [r7, #0]
|
|
8003736: 68da ldr r2, [r3, #12]
|
|
8003738: 697b ldr r3, [r7, #20]
|
|
800373a: 005b lsls r3, r3, #1
|
|
800373c: fa02 f303 lsl.w r3, r2, r3
|
|
8003740: 693a ldr r2, [r7, #16]
|
|
8003742: 4313 orrs r3, r2
|
|
8003744: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8003746: 687b ldr r3, [r7, #4]
|
|
8003748: 693a ldr r2, [r7, #16]
|
|
800374a: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
800374c: 687b ldr r3, [r7, #4]
|
|
800374e: 685b ldr r3, [r3, #4]
|
|
8003750: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8003752: 2201 movs r2, #1
|
|
8003754: 697b ldr r3, [r7, #20]
|
|
8003756: fa02 f303 lsl.w r3, r2, r3
|
|
800375a: 43db mvns r3, r3
|
|
800375c: 693a ldr r2, [r7, #16]
|
|
800375e: 4013 ands r3, r2
|
|
8003760: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8003762: 683b ldr r3, [r7, #0]
|
|
8003764: 685b ldr r3, [r3, #4]
|
|
8003766: 091b lsrs r3, r3, #4
|
|
8003768: f003 0201 and.w r2, r3, #1
|
|
800376c: 697b ldr r3, [r7, #20]
|
|
800376e: fa02 f303 lsl.w r3, r2, r3
|
|
8003772: 693a ldr r2, [r7, #16]
|
|
8003774: 4313 orrs r3, r2
|
|
8003776: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8003778: 687b ldr r3, [r7, #4]
|
|
800377a: 693a ldr r2, [r7, #16]
|
|
800377c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
|
/* In case of Analog mode, check if ADC control mode is selected */
|
|
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
|
|
800377e: 683b ldr r3, [r7, #0]
|
|
8003780: 685b ldr r3, [r3, #4]
|
|
8003782: f003 0303 and.w r3, r3, #3
|
|
8003786: 2b03 cmp r3, #3
|
|
8003788: d118 bne.n 80037bc <HAL_GPIO_Init+0xe0>
|
|
{
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->ASCR;
|
|
800378a: 687b ldr r3, [r7, #4]
|
|
800378c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800378e: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_ASCR_ASC0 << position) ;
|
|
8003790: 2201 movs r2, #1
|
|
8003792: 697b ldr r3, [r7, #20]
|
|
8003794: fa02 f303 lsl.w r3, r2, r3
|
|
8003798: 43db mvns r3, r3
|
|
800379a: 693a ldr r2, [r7, #16]
|
|
800379c: 4013 ands r3, r2
|
|
800379e: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
|
|
80037a0: 683b ldr r3, [r7, #0]
|
|
80037a2: 685b ldr r3, [r3, #4]
|
|
80037a4: 08db lsrs r3, r3, #3
|
|
80037a6: f003 0201 and.w r2, r3, #1
|
|
80037aa: 697b ldr r3, [r7, #20]
|
|
80037ac: fa02 f303 lsl.w r3, r2, r3
|
|
80037b0: 693a ldr r2, [r7, #16]
|
|
80037b2: 4313 orrs r3, r2
|
|
80037b4: 613b str r3, [r7, #16]
|
|
GPIOx->ASCR = temp;
|
|
80037b6: 687b ldr r3, [r7, #4]
|
|
80037b8: 693a ldr r2, [r7, #16]
|
|
80037ba: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
80037bc: 683b ldr r3, [r7, #0]
|
|
80037be: 685b ldr r3, [r3, #4]
|
|
80037c0: f003 0303 and.w r3, r3, #3
|
|
80037c4: 2b03 cmp r3, #3
|
|
80037c6: d017 beq.n 80037f8 <HAL_GPIO_Init+0x11c>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
temp = GPIOx->PUPDR;
|
|
80037c8: 687b ldr r3, [r7, #4]
|
|
80037ca: 68db ldr r3, [r3, #12]
|
|
80037cc: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
80037ce: 697b ldr r3, [r7, #20]
|
|
80037d0: 005b lsls r3, r3, #1
|
|
80037d2: 2203 movs r2, #3
|
|
80037d4: fa02 f303 lsl.w r3, r2, r3
|
|
80037d8: 43db mvns r3, r3
|
|
80037da: 693a ldr r2, [r7, #16]
|
|
80037dc: 4013 ands r3, r2
|
|
80037de: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
80037e0: 683b ldr r3, [r7, #0]
|
|
80037e2: 689a ldr r2, [r3, #8]
|
|
80037e4: 697b ldr r3, [r7, #20]
|
|
80037e6: 005b lsls r3, r3, #1
|
|
80037e8: fa02 f303 lsl.w r3, r2, r3
|
|
80037ec: 693a ldr r2, [r7, #16]
|
|
80037ee: 4313 orrs r3, r2
|
|
80037f0: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
80037f2: 687b ldr r3, [r7, #4]
|
|
80037f4: 693a ldr r2, [r7, #16]
|
|
80037f6: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80037f8: 683b ldr r3, [r7, #0]
|
|
80037fa: 685b ldr r3, [r3, #4]
|
|
80037fc: f003 0303 and.w r3, r3, #3
|
|
8003800: 2b02 cmp r3, #2
|
|
8003802: d123 bne.n 800384c <HAL_GPIO_Init+0x170>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
8003804: 697b ldr r3, [r7, #20]
|
|
8003806: 08da lsrs r2, r3, #3
|
|
8003808: 687b ldr r3, [r7, #4]
|
|
800380a: 3208 adds r2, #8
|
|
800380c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8003810: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8003812: 697b ldr r3, [r7, #20]
|
|
8003814: f003 0307 and.w r3, r3, #7
|
|
8003818: 009b lsls r3, r3, #2
|
|
800381a: 220f movs r2, #15
|
|
800381c: fa02 f303 lsl.w r3, r2, r3
|
|
8003820: 43db mvns r3, r3
|
|
8003822: 693a ldr r2, [r7, #16]
|
|
8003824: 4013 ands r3, r2
|
|
8003826: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
8003828: 683b ldr r3, [r7, #0]
|
|
800382a: 691a ldr r2, [r3, #16]
|
|
800382c: 697b ldr r3, [r7, #20]
|
|
800382e: f003 0307 and.w r3, r3, #7
|
|
8003832: 009b lsls r3, r3, #2
|
|
8003834: fa02 f303 lsl.w r3, r2, r3
|
|
8003838: 693a ldr r2, [r7, #16]
|
|
800383a: 4313 orrs r3, r2
|
|
800383c: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
800383e: 697b ldr r3, [r7, #20]
|
|
8003840: 08da lsrs r2, r3, #3
|
|
8003842: 687b ldr r3, [r7, #4]
|
|
8003844: 3208 adds r2, #8
|
|
8003846: 6939 ldr r1, [r7, #16]
|
|
8003848: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
800384c: 687b ldr r3, [r7, #4]
|
|
800384e: 681b ldr r3, [r3, #0]
|
|
8003850: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
8003852: 697b ldr r3, [r7, #20]
|
|
8003854: 005b lsls r3, r3, #1
|
|
8003856: 2203 movs r2, #3
|
|
8003858: fa02 f303 lsl.w r3, r2, r3
|
|
800385c: 43db mvns r3, r3
|
|
800385e: 693a ldr r2, [r7, #16]
|
|
8003860: 4013 ands r3, r2
|
|
8003862: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
8003864: 683b ldr r3, [r7, #0]
|
|
8003866: 685b ldr r3, [r3, #4]
|
|
8003868: f003 0203 and.w r2, r3, #3
|
|
800386c: 697b ldr r3, [r7, #20]
|
|
800386e: 005b lsls r3, r3, #1
|
|
8003870: fa02 f303 lsl.w r3, r2, r3
|
|
8003874: 693a ldr r2, [r7, #16]
|
|
8003876: 4313 orrs r3, r2
|
|
8003878: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
800387a: 687b ldr r3, [r7, #4]
|
|
800387c: 693a ldr r2, [r7, #16]
|
|
800387e: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
8003880: 683b ldr r3, [r7, #0]
|
|
8003882: 685b ldr r3, [r3, #4]
|
|
8003884: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8003888: 2b00 cmp r3, #0
|
|
800388a: f000 80ac beq.w 80039e6 <HAL_GPIO_Init+0x30a>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800388e: 4b5f ldr r3, [pc, #380] @ (8003a0c <HAL_GPIO_Init+0x330>)
|
|
8003890: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8003892: 4a5e ldr r2, [pc, #376] @ (8003a0c <HAL_GPIO_Init+0x330>)
|
|
8003894: f043 0301 orr.w r3, r3, #1
|
|
8003898: 6613 str r3, [r2, #96] @ 0x60
|
|
800389a: 4b5c ldr r3, [pc, #368] @ (8003a0c <HAL_GPIO_Init+0x330>)
|
|
800389c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800389e: f003 0301 and.w r3, r3, #1
|
|
80038a2: 60bb str r3, [r7, #8]
|
|
80038a4: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
80038a6: 4a5a ldr r2, [pc, #360] @ (8003a10 <HAL_GPIO_Init+0x334>)
|
|
80038a8: 697b ldr r3, [r7, #20]
|
|
80038aa: 089b lsrs r3, r3, #2
|
|
80038ac: 3302 adds r3, #2
|
|
80038ae: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80038b2: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
80038b4: 697b ldr r3, [r7, #20]
|
|
80038b6: f003 0303 and.w r3, r3, #3
|
|
80038ba: 009b lsls r3, r3, #2
|
|
80038bc: 220f movs r2, #15
|
|
80038be: fa02 f303 lsl.w r3, r2, r3
|
|
80038c2: 43db mvns r3, r3
|
|
80038c4: 693a ldr r2, [r7, #16]
|
|
80038c6: 4013 ands r3, r2
|
|
80038c8: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
80038ca: 687b ldr r3, [r7, #4]
|
|
80038cc: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
80038d0: d025 beq.n 800391e <HAL_GPIO_Init+0x242>
|
|
80038d2: 687b ldr r3, [r7, #4]
|
|
80038d4: 4a4f ldr r2, [pc, #316] @ (8003a14 <HAL_GPIO_Init+0x338>)
|
|
80038d6: 4293 cmp r3, r2
|
|
80038d8: d01f beq.n 800391a <HAL_GPIO_Init+0x23e>
|
|
80038da: 687b ldr r3, [r7, #4]
|
|
80038dc: 4a4e ldr r2, [pc, #312] @ (8003a18 <HAL_GPIO_Init+0x33c>)
|
|
80038de: 4293 cmp r3, r2
|
|
80038e0: d019 beq.n 8003916 <HAL_GPIO_Init+0x23a>
|
|
80038e2: 687b ldr r3, [r7, #4]
|
|
80038e4: 4a4d ldr r2, [pc, #308] @ (8003a1c <HAL_GPIO_Init+0x340>)
|
|
80038e6: 4293 cmp r3, r2
|
|
80038e8: d013 beq.n 8003912 <HAL_GPIO_Init+0x236>
|
|
80038ea: 687b ldr r3, [r7, #4]
|
|
80038ec: 4a4c ldr r2, [pc, #304] @ (8003a20 <HAL_GPIO_Init+0x344>)
|
|
80038ee: 4293 cmp r3, r2
|
|
80038f0: d00d beq.n 800390e <HAL_GPIO_Init+0x232>
|
|
80038f2: 687b ldr r3, [r7, #4]
|
|
80038f4: 4a4b ldr r2, [pc, #300] @ (8003a24 <HAL_GPIO_Init+0x348>)
|
|
80038f6: 4293 cmp r3, r2
|
|
80038f8: d007 beq.n 800390a <HAL_GPIO_Init+0x22e>
|
|
80038fa: 687b ldr r3, [r7, #4]
|
|
80038fc: 4a4a ldr r2, [pc, #296] @ (8003a28 <HAL_GPIO_Init+0x34c>)
|
|
80038fe: 4293 cmp r3, r2
|
|
8003900: d101 bne.n 8003906 <HAL_GPIO_Init+0x22a>
|
|
8003902: 2306 movs r3, #6
|
|
8003904: e00c b.n 8003920 <HAL_GPIO_Init+0x244>
|
|
8003906: 2307 movs r3, #7
|
|
8003908: e00a b.n 8003920 <HAL_GPIO_Init+0x244>
|
|
800390a: 2305 movs r3, #5
|
|
800390c: e008 b.n 8003920 <HAL_GPIO_Init+0x244>
|
|
800390e: 2304 movs r3, #4
|
|
8003910: e006 b.n 8003920 <HAL_GPIO_Init+0x244>
|
|
8003912: 2303 movs r3, #3
|
|
8003914: e004 b.n 8003920 <HAL_GPIO_Init+0x244>
|
|
8003916: 2302 movs r3, #2
|
|
8003918: e002 b.n 8003920 <HAL_GPIO_Init+0x244>
|
|
800391a: 2301 movs r3, #1
|
|
800391c: e000 b.n 8003920 <HAL_GPIO_Init+0x244>
|
|
800391e: 2300 movs r3, #0
|
|
8003920: 697a ldr r2, [r7, #20]
|
|
8003922: f002 0203 and.w r2, r2, #3
|
|
8003926: 0092 lsls r2, r2, #2
|
|
8003928: 4093 lsls r3, r2
|
|
800392a: 693a ldr r2, [r7, #16]
|
|
800392c: 4313 orrs r3, r2
|
|
800392e: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
8003930: 4937 ldr r1, [pc, #220] @ (8003a10 <HAL_GPIO_Init+0x334>)
|
|
8003932: 697b ldr r3, [r7, #20]
|
|
8003934: 089b lsrs r3, r3, #2
|
|
8003936: 3302 adds r3, #2
|
|
8003938: 693a ldr r2, [r7, #16]
|
|
800393a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
800393e: 4b3b ldr r3, [pc, #236] @ (8003a2c <HAL_GPIO_Init+0x350>)
|
|
8003940: 689b ldr r3, [r3, #8]
|
|
8003942: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8003944: 68fb ldr r3, [r7, #12]
|
|
8003946: 43db mvns r3, r3
|
|
8003948: 693a ldr r2, [r7, #16]
|
|
800394a: 4013 ands r3, r2
|
|
800394c: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
800394e: 683b ldr r3, [r7, #0]
|
|
8003950: 685b ldr r3, [r3, #4]
|
|
8003952: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8003956: 2b00 cmp r3, #0
|
|
8003958: d003 beq.n 8003962 <HAL_GPIO_Init+0x286>
|
|
{
|
|
temp |= iocurrent;
|
|
800395a: 693a ldr r2, [r7, #16]
|
|
800395c: 68fb ldr r3, [r7, #12]
|
|
800395e: 4313 orrs r3, r2
|
|
8003960: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
8003962: 4a32 ldr r2, [pc, #200] @ (8003a2c <HAL_GPIO_Init+0x350>)
|
|
8003964: 693b ldr r3, [r7, #16]
|
|
8003966: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR1;
|
|
8003968: 4b30 ldr r3, [pc, #192] @ (8003a2c <HAL_GPIO_Init+0x350>)
|
|
800396a: 68db ldr r3, [r3, #12]
|
|
800396c: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
800396e: 68fb ldr r3, [r7, #12]
|
|
8003970: 43db mvns r3, r3
|
|
8003972: 693a ldr r2, [r7, #16]
|
|
8003974: 4013 ands r3, r2
|
|
8003976: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
8003978: 683b ldr r3, [r7, #0]
|
|
800397a: 685b ldr r3, [r3, #4]
|
|
800397c: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8003980: 2b00 cmp r3, #0
|
|
8003982: d003 beq.n 800398c <HAL_GPIO_Init+0x2b0>
|
|
{
|
|
temp |= iocurrent;
|
|
8003984: 693a ldr r2, [r7, #16]
|
|
8003986: 68fb ldr r3, [r7, #12]
|
|
8003988: 4313 orrs r3, r2
|
|
800398a: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
800398c: 4a27 ldr r2, [pc, #156] @ (8003a2c <HAL_GPIO_Init+0x350>)
|
|
800398e: 693b ldr r3, [r7, #16]
|
|
8003990: 60d3 str r3, [r2, #12]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->EMR1;
|
|
8003992: 4b26 ldr r3, [pc, #152] @ (8003a2c <HAL_GPIO_Init+0x350>)
|
|
8003994: 685b ldr r3, [r3, #4]
|
|
8003996: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8003998: 68fb ldr r3, [r7, #12]
|
|
800399a: 43db mvns r3, r3
|
|
800399c: 693a ldr r2, [r7, #16]
|
|
800399e: 4013 ands r3, r2
|
|
80039a0: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
80039a2: 683b ldr r3, [r7, #0]
|
|
80039a4: 685b ldr r3, [r3, #4]
|
|
80039a6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80039aa: 2b00 cmp r3, #0
|
|
80039ac: d003 beq.n 80039b6 <HAL_GPIO_Init+0x2da>
|
|
{
|
|
temp |= iocurrent;
|
|
80039ae: 693a ldr r2, [r7, #16]
|
|
80039b0: 68fb ldr r3, [r7, #12]
|
|
80039b2: 4313 orrs r3, r2
|
|
80039b4: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
80039b6: 4a1d ldr r2, [pc, #116] @ (8003a2c <HAL_GPIO_Init+0x350>)
|
|
80039b8: 693b ldr r3, [r7, #16]
|
|
80039ba: 6053 str r3, [r2, #4]
|
|
|
|
temp = EXTI->IMR1;
|
|
80039bc: 4b1b ldr r3, [pc, #108] @ (8003a2c <HAL_GPIO_Init+0x350>)
|
|
80039be: 681b ldr r3, [r3, #0]
|
|
80039c0: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80039c2: 68fb ldr r3, [r7, #12]
|
|
80039c4: 43db mvns r3, r3
|
|
80039c6: 693a ldr r2, [r7, #16]
|
|
80039c8: 4013 ands r3, r2
|
|
80039ca: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
80039cc: 683b ldr r3, [r7, #0]
|
|
80039ce: 685b ldr r3, [r3, #4]
|
|
80039d0: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
80039d4: 2b00 cmp r3, #0
|
|
80039d6: d003 beq.n 80039e0 <HAL_GPIO_Init+0x304>
|
|
{
|
|
temp |= iocurrent;
|
|
80039d8: 693a ldr r2, [r7, #16]
|
|
80039da: 68fb ldr r3, [r7, #12]
|
|
80039dc: 4313 orrs r3, r2
|
|
80039de: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
80039e0: 4a12 ldr r2, [pc, #72] @ (8003a2c <HAL_GPIO_Init+0x350>)
|
|
80039e2: 693b ldr r3, [r7, #16]
|
|
80039e4: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
80039e6: 697b ldr r3, [r7, #20]
|
|
80039e8: 3301 adds r3, #1
|
|
80039ea: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80039ec: 683b ldr r3, [r7, #0]
|
|
80039ee: 681a ldr r2, [r3, #0]
|
|
80039f0: 697b ldr r3, [r7, #20]
|
|
80039f2: fa22 f303 lsr.w r3, r2, r3
|
|
80039f6: 2b00 cmp r3, #0
|
|
80039f8: f47f ae78 bne.w 80036ec <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
80039fc: bf00 nop
|
|
80039fe: bf00 nop
|
|
8003a00: 371c adds r7, #28
|
|
8003a02: 46bd mov sp, r7
|
|
8003a04: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003a08: 4770 bx lr
|
|
8003a0a: bf00 nop
|
|
8003a0c: 40021000 .word 0x40021000
|
|
8003a10: 40010000 .word 0x40010000
|
|
8003a14: 48000400 .word 0x48000400
|
|
8003a18: 48000800 .word 0x48000800
|
|
8003a1c: 48000c00 .word 0x48000c00
|
|
8003a20: 48001000 .word 0x48001000
|
|
8003a24: 48001400 .word 0x48001400
|
|
8003a28: 48001800 .word 0x48001800
|
|
8003a2c: 40010400 .word 0x40010400
|
|
|
|
08003a30 <HAL_GPIO_DeInit>:
|
|
* @param GPIO_Pin specifies the port bit to be written.
|
|
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|
{
|
|
8003a30: b480 push {r7}
|
|
8003a32: b087 sub sp, #28
|
|
8003a34: af00 add r7, sp, #0
|
|
8003a36: 6078 str r0, [r7, #4]
|
|
8003a38: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8003a3a: 2300 movs r3, #0
|
|
8003a3c: 617b str r3, [r7, #20]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* Configure the port pins */
|
|
while ((GPIO_Pin >> position) != 0x00u)
|
|
8003a3e: e0cd b.n 8003bdc <HAL_GPIO_DeInit+0x1ac>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Pin) & (1uL << position);
|
|
8003a40: 2201 movs r2, #1
|
|
8003a42: 697b ldr r3, [r7, #20]
|
|
8003a44: fa02 f303 lsl.w r3, r2, r3
|
|
8003a48: 683a ldr r2, [r7, #0]
|
|
8003a4a: 4013 ands r3, r2
|
|
8003a4c: 613b str r3, [r7, #16]
|
|
|
|
if (iocurrent != 0x00u)
|
|
8003a4e: 693b ldr r3, [r7, #16]
|
|
8003a50: 2b00 cmp r3, #0
|
|
8003a52: f000 80c0 beq.w 8003bd6 <HAL_GPIO_DeInit+0x1a6>
|
|
{
|
|
/*------------------------- EXTI Mode Configuration --------------------*/
|
|
/* Clear the External Interrupt or Event for the current IO */
|
|
|
|
tmp = SYSCFG->EXTICR[position >> 2u];
|
|
8003a56: 4a68 ldr r2, [pc, #416] @ (8003bf8 <HAL_GPIO_DeInit+0x1c8>)
|
|
8003a58: 697b ldr r3, [r7, #20]
|
|
8003a5a: 089b lsrs r3, r3, #2
|
|
8003a5c: 3302 adds r3, #2
|
|
8003a5e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8003a62: 60fb str r3, [r7, #12]
|
|
tmp &= (0x0FuL << (4u * (position & 0x03u)));
|
|
8003a64: 697b ldr r3, [r7, #20]
|
|
8003a66: f003 0303 and.w r3, r3, #3
|
|
8003a6a: 009b lsls r3, r3, #2
|
|
8003a6c: 220f movs r2, #15
|
|
8003a6e: fa02 f303 lsl.w r3, r2, r3
|
|
8003a72: 68fa ldr r2, [r7, #12]
|
|
8003a74: 4013 ands r3, r2
|
|
8003a76: 60fb str r3, [r7, #12]
|
|
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
|
|
8003a78: 687b ldr r3, [r7, #4]
|
|
8003a7a: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
8003a7e: d025 beq.n 8003acc <HAL_GPIO_DeInit+0x9c>
|
|
8003a80: 687b ldr r3, [r7, #4]
|
|
8003a82: 4a5e ldr r2, [pc, #376] @ (8003bfc <HAL_GPIO_DeInit+0x1cc>)
|
|
8003a84: 4293 cmp r3, r2
|
|
8003a86: d01f beq.n 8003ac8 <HAL_GPIO_DeInit+0x98>
|
|
8003a88: 687b ldr r3, [r7, #4]
|
|
8003a8a: 4a5d ldr r2, [pc, #372] @ (8003c00 <HAL_GPIO_DeInit+0x1d0>)
|
|
8003a8c: 4293 cmp r3, r2
|
|
8003a8e: d019 beq.n 8003ac4 <HAL_GPIO_DeInit+0x94>
|
|
8003a90: 687b ldr r3, [r7, #4]
|
|
8003a92: 4a5c ldr r2, [pc, #368] @ (8003c04 <HAL_GPIO_DeInit+0x1d4>)
|
|
8003a94: 4293 cmp r3, r2
|
|
8003a96: d013 beq.n 8003ac0 <HAL_GPIO_DeInit+0x90>
|
|
8003a98: 687b ldr r3, [r7, #4]
|
|
8003a9a: 4a5b ldr r2, [pc, #364] @ (8003c08 <HAL_GPIO_DeInit+0x1d8>)
|
|
8003a9c: 4293 cmp r3, r2
|
|
8003a9e: d00d beq.n 8003abc <HAL_GPIO_DeInit+0x8c>
|
|
8003aa0: 687b ldr r3, [r7, #4]
|
|
8003aa2: 4a5a ldr r2, [pc, #360] @ (8003c0c <HAL_GPIO_DeInit+0x1dc>)
|
|
8003aa4: 4293 cmp r3, r2
|
|
8003aa6: d007 beq.n 8003ab8 <HAL_GPIO_DeInit+0x88>
|
|
8003aa8: 687b ldr r3, [r7, #4]
|
|
8003aaa: 4a59 ldr r2, [pc, #356] @ (8003c10 <HAL_GPIO_DeInit+0x1e0>)
|
|
8003aac: 4293 cmp r3, r2
|
|
8003aae: d101 bne.n 8003ab4 <HAL_GPIO_DeInit+0x84>
|
|
8003ab0: 2306 movs r3, #6
|
|
8003ab2: e00c b.n 8003ace <HAL_GPIO_DeInit+0x9e>
|
|
8003ab4: 2307 movs r3, #7
|
|
8003ab6: e00a b.n 8003ace <HAL_GPIO_DeInit+0x9e>
|
|
8003ab8: 2305 movs r3, #5
|
|
8003aba: e008 b.n 8003ace <HAL_GPIO_DeInit+0x9e>
|
|
8003abc: 2304 movs r3, #4
|
|
8003abe: e006 b.n 8003ace <HAL_GPIO_DeInit+0x9e>
|
|
8003ac0: 2303 movs r3, #3
|
|
8003ac2: e004 b.n 8003ace <HAL_GPIO_DeInit+0x9e>
|
|
8003ac4: 2302 movs r3, #2
|
|
8003ac6: e002 b.n 8003ace <HAL_GPIO_DeInit+0x9e>
|
|
8003ac8: 2301 movs r3, #1
|
|
8003aca: e000 b.n 8003ace <HAL_GPIO_DeInit+0x9e>
|
|
8003acc: 2300 movs r3, #0
|
|
8003ace: 697a ldr r2, [r7, #20]
|
|
8003ad0: f002 0203 and.w r2, r2, #3
|
|
8003ad4: 0092 lsls r2, r2, #2
|
|
8003ad6: 4093 lsls r3, r2
|
|
8003ad8: 68fa ldr r2, [r7, #12]
|
|
8003ada: 429a cmp r2, r3
|
|
8003adc: d132 bne.n 8003b44 <HAL_GPIO_DeInit+0x114>
|
|
{
|
|
/* Clear EXTI line configuration */
|
|
EXTI->IMR1 &= ~(iocurrent);
|
|
8003ade: 4b4d ldr r3, [pc, #308] @ (8003c14 <HAL_GPIO_DeInit+0x1e4>)
|
|
8003ae0: 681a ldr r2, [r3, #0]
|
|
8003ae2: 693b ldr r3, [r7, #16]
|
|
8003ae4: 43db mvns r3, r3
|
|
8003ae6: 494b ldr r1, [pc, #300] @ (8003c14 <HAL_GPIO_DeInit+0x1e4>)
|
|
8003ae8: 4013 ands r3, r2
|
|
8003aea: 600b str r3, [r1, #0]
|
|
EXTI->EMR1 &= ~(iocurrent);
|
|
8003aec: 4b49 ldr r3, [pc, #292] @ (8003c14 <HAL_GPIO_DeInit+0x1e4>)
|
|
8003aee: 685a ldr r2, [r3, #4]
|
|
8003af0: 693b ldr r3, [r7, #16]
|
|
8003af2: 43db mvns r3, r3
|
|
8003af4: 4947 ldr r1, [pc, #284] @ (8003c14 <HAL_GPIO_DeInit+0x1e4>)
|
|
8003af6: 4013 ands r3, r2
|
|
8003af8: 604b str r3, [r1, #4]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
EXTI->FTSR1 &= ~(iocurrent);
|
|
8003afa: 4b46 ldr r3, [pc, #280] @ (8003c14 <HAL_GPIO_DeInit+0x1e4>)
|
|
8003afc: 68da ldr r2, [r3, #12]
|
|
8003afe: 693b ldr r3, [r7, #16]
|
|
8003b00: 43db mvns r3, r3
|
|
8003b02: 4944 ldr r1, [pc, #272] @ (8003c14 <HAL_GPIO_DeInit+0x1e4>)
|
|
8003b04: 4013 ands r3, r2
|
|
8003b06: 60cb str r3, [r1, #12]
|
|
EXTI->RTSR1 &= ~(iocurrent);
|
|
8003b08: 4b42 ldr r3, [pc, #264] @ (8003c14 <HAL_GPIO_DeInit+0x1e4>)
|
|
8003b0a: 689a ldr r2, [r3, #8]
|
|
8003b0c: 693b ldr r3, [r7, #16]
|
|
8003b0e: 43db mvns r3, r3
|
|
8003b10: 4940 ldr r1, [pc, #256] @ (8003c14 <HAL_GPIO_DeInit+0x1e4>)
|
|
8003b12: 4013 ands r3, r2
|
|
8003b14: 608b str r3, [r1, #8]
|
|
|
|
tmp = 0x0FuL << (4u * (position & 0x03u));
|
|
8003b16: 697b ldr r3, [r7, #20]
|
|
8003b18: f003 0303 and.w r3, r3, #3
|
|
8003b1c: 009b lsls r3, r3, #2
|
|
8003b1e: 220f movs r2, #15
|
|
8003b20: fa02 f303 lsl.w r3, r2, r3
|
|
8003b24: 60fb str r3, [r7, #12]
|
|
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
|
|
8003b26: 4a34 ldr r2, [pc, #208] @ (8003bf8 <HAL_GPIO_DeInit+0x1c8>)
|
|
8003b28: 697b ldr r3, [r7, #20]
|
|
8003b2a: 089b lsrs r3, r3, #2
|
|
8003b2c: 3302 adds r3, #2
|
|
8003b2e: f852 1023 ldr.w r1, [r2, r3, lsl #2]
|
|
8003b32: 68fb ldr r3, [r7, #12]
|
|
8003b34: 43da mvns r2, r3
|
|
8003b36: 4830 ldr r0, [pc, #192] @ (8003bf8 <HAL_GPIO_DeInit+0x1c8>)
|
|
8003b38: 697b ldr r3, [r7, #20]
|
|
8003b3a: 089b lsrs r3, r3, #2
|
|
8003b3c: 400a ands r2, r1
|
|
8003b3e: 3302 adds r3, #2
|
|
8003b40: f840 2023 str.w r2, [r0, r3, lsl #2]
|
|
}
|
|
|
|
/*------------------------- GPIO Mode Configuration --------------------*/
|
|
/* Configure IO in Analog Mode */
|
|
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
|
|
8003b44: 687b ldr r3, [r7, #4]
|
|
8003b46: 681a ldr r2, [r3, #0]
|
|
8003b48: 697b ldr r3, [r7, #20]
|
|
8003b4a: 005b lsls r3, r3, #1
|
|
8003b4c: 2103 movs r1, #3
|
|
8003b4e: fa01 f303 lsl.w r3, r1, r3
|
|
8003b52: 431a orrs r2, r3
|
|
8003b54: 687b ldr r3, [r7, #4]
|
|
8003b56: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the default Alternate Function in current IO */
|
|
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
|
|
8003b58: 697b ldr r3, [r7, #20]
|
|
8003b5a: 08da lsrs r2, r3, #3
|
|
8003b5c: 687b ldr r3, [r7, #4]
|
|
8003b5e: 3208 adds r2, #8
|
|
8003b60: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
8003b64: 697b ldr r3, [r7, #20]
|
|
8003b66: f003 0307 and.w r3, r3, #7
|
|
8003b6a: 009b lsls r3, r3, #2
|
|
8003b6c: 220f movs r2, #15
|
|
8003b6e: fa02 f303 lsl.w r3, r2, r3
|
|
8003b72: 43db mvns r3, r3
|
|
8003b74: 697a ldr r2, [r7, #20]
|
|
8003b76: 08d2 lsrs r2, r2, #3
|
|
8003b78: 4019 ands r1, r3
|
|
8003b7a: 687b ldr r3, [r7, #4]
|
|
8003b7c: 3208 adds r2, #8
|
|
8003b7e: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
|
|
/* Configure the default value for IO Speed */
|
|
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
8003b82: 687b ldr r3, [r7, #4]
|
|
8003b84: 689a ldr r2, [r3, #8]
|
|
8003b86: 697b ldr r3, [r7, #20]
|
|
8003b88: 005b lsls r3, r3, #1
|
|
8003b8a: 2103 movs r1, #3
|
|
8003b8c: fa01 f303 lsl.w r3, r1, r3
|
|
8003b90: 43db mvns r3, r3
|
|
8003b92: 401a ands r2, r3
|
|
8003b94: 687b ldr r3, [r7, #4]
|
|
8003b96: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the default value IO Output Type */
|
|
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8003b98: 687b ldr r3, [r7, #4]
|
|
8003b9a: 685a ldr r2, [r3, #4]
|
|
8003b9c: 2101 movs r1, #1
|
|
8003b9e: 697b ldr r3, [r7, #20]
|
|
8003ba0: fa01 f303 lsl.w r3, r1, r3
|
|
8003ba4: 43db mvns r3, r3
|
|
8003ba6: 401a ands r2, r3
|
|
8003ba8: 687b ldr r3, [r7, #4]
|
|
8003baa: 605a str r2, [r3, #4]
|
|
|
|
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
|
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
|
8003bac: 687b ldr r3, [r7, #4]
|
|
8003bae: 68da ldr r2, [r3, #12]
|
|
8003bb0: 697b ldr r3, [r7, #20]
|
|
8003bb2: 005b lsls r3, r3, #1
|
|
8003bb4: 2103 movs r1, #3
|
|
8003bb6: fa01 f303 lsl.w r3, r1, r3
|
|
8003bba: 43db mvns r3, r3
|
|
8003bbc: 401a ands r2, r3
|
|
8003bbe: 687b ldr r3, [r7, #4]
|
|
8003bc0: 60da str r2, [r3, #12]
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
/* Deactivate the Control bit of Analog mode for the current IO */
|
|
GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
|
|
8003bc2: 687b ldr r3, [r7, #4]
|
|
8003bc4: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8003bc6: 2101 movs r1, #1
|
|
8003bc8: 697b ldr r3, [r7, #20]
|
|
8003bca: fa01 f303 lsl.w r3, r1, r3
|
|
8003bce: 43db mvns r3, r3
|
|
8003bd0: 401a ands r2, r3
|
|
8003bd2: 687b ldr r3, [r7, #4]
|
|
8003bd4: 62da str r2, [r3, #44] @ 0x2c
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
}
|
|
|
|
position++;
|
|
8003bd6: 697b ldr r3, [r7, #20]
|
|
8003bd8: 3301 adds r3, #1
|
|
8003bda: 617b str r3, [r7, #20]
|
|
while ((GPIO_Pin >> position) != 0x00u)
|
|
8003bdc: 683a ldr r2, [r7, #0]
|
|
8003bde: 697b ldr r3, [r7, #20]
|
|
8003be0: fa22 f303 lsr.w r3, r2, r3
|
|
8003be4: 2b00 cmp r3, #0
|
|
8003be6: f47f af2b bne.w 8003a40 <HAL_GPIO_DeInit+0x10>
|
|
}
|
|
}
|
|
8003bea: bf00 nop
|
|
8003bec: bf00 nop
|
|
8003bee: 371c adds r7, #28
|
|
8003bf0: 46bd mov sp, r7
|
|
8003bf2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003bf6: 4770 bx lr
|
|
8003bf8: 40010000 .word 0x40010000
|
|
8003bfc: 48000400 .word 0x48000400
|
|
8003c00: 48000800 .word 0x48000800
|
|
8003c04: 48000c00 .word 0x48000c00
|
|
8003c08: 48001000 .word 0x48001000
|
|
8003c0c: 48001400 .word 0x48001400
|
|
8003c10: 48001800 .word 0x48001800
|
|
8003c14: 40010400 .word 0x40010400
|
|
|
|
08003c18 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8003c18: b480 push {r7}
|
|
8003c1a: b083 sub sp, #12
|
|
8003c1c: af00 add r7, sp, #0
|
|
8003c1e: 6078 str r0, [r7, #4]
|
|
8003c20: 460b mov r3, r1
|
|
8003c22: 807b strh r3, [r7, #2]
|
|
8003c24: 4613 mov r3, r2
|
|
8003c26: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8003c28: 787b ldrb r3, [r7, #1]
|
|
8003c2a: 2b00 cmp r3, #0
|
|
8003c2c: d003 beq.n 8003c36 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8003c2e: 887a ldrh r2, [r7, #2]
|
|
8003c30: 687b ldr r3, [r7, #4]
|
|
8003c32: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8003c34: e002 b.n 8003c3c <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8003c36: 887a ldrh r2, [r7, #2]
|
|
8003c38: 687b ldr r3, [r7, #4]
|
|
8003c3a: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
8003c3c: bf00 nop
|
|
8003c3e: 370c adds r7, #12
|
|
8003c40: 46bd mov sp, r7
|
|
8003c42: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003c46: 4770 bx lr
|
|
|
|
08003c48 <HAL_GPIO_EXTI_IRQHandler>:
|
|
* @brief Handle EXTI interrupt request.
|
|
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
|
{
|
|
8003c48: b580 push {r7, lr}
|
|
8003c4a: b082 sub sp, #8
|
|
8003c4c: af00 add r7, sp, #0
|
|
8003c4e: 4603 mov r3, r0
|
|
8003c50: 80fb strh r3, [r7, #6]
|
|
/* EXTI line interrupt detected */
|
|
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
|
8003c52: 4b08 ldr r3, [pc, #32] @ (8003c74 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
|
|
8003c54: 695a ldr r2, [r3, #20]
|
|
8003c56: 88fb ldrh r3, [r7, #6]
|
|
8003c58: 4013 ands r3, r2
|
|
8003c5a: 2b00 cmp r3, #0
|
|
8003c5c: d006 beq.n 8003c6c <HAL_GPIO_EXTI_IRQHandler+0x24>
|
|
{
|
|
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
|
8003c5e: 4a05 ldr r2, [pc, #20] @ (8003c74 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
|
|
8003c60: 88fb ldrh r3, [r7, #6]
|
|
8003c62: 6153 str r3, [r2, #20]
|
|
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
|
8003c64: 88fb ldrh r3, [r7, #6]
|
|
8003c66: 4618 mov r0, r3
|
|
8003c68: f000 f806 bl 8003c78 <HAL_GPIO_EXTI_Callback>
|
|
}
|
|
}
|
|
8003c6c: bf00 nop
|
|
8003c6e: 3708 adds r7, #8
|
|
8003c70: 46bd mov sp, r7
|
|
8003c72: bd80 pop {r7, pc}
|
|
8003c74: 40010400 .word 0x40010400
|
|
|
|
08003c78 <HAL_GPIO_EXTI_Callback>:
|
|
* @brief EXTI line detection callback.
|
|
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
|
{
|
|
8003c78: b480 push {r7}
|
|
8003c7a: b083 sub sp, #12
|
|
8003c7c: af00 add r7, sp, #0
|
|
8003c7e: 4603 mov r3, r0
|
|
8003c80: 80fb strh r3, [r7, #6]
|
|
UNUSED(GPIO_Pin);
|
|
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
8003c82: bf00 nop
|
|
8003c84: 370c adds r7, #12
|
|
8003c86: 46bd mov sp, r7
|
|
8003c88: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003c8c: 4770 bx lr
|
|
|
|
08003c8e <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8003c8e: b580 push {r7, lr}
|
|
8003c90: b082 sub sp, #8
|
|
8003c92: af00 add r7, sp, #0
|
|
8003c94: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8003c96: 687b ldr r3, [r7, #4]
|
|
8003c98: 2b00 cmp r3, #0
|
|
8003c9a: d101 bne.n 8003ca0 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003c9c: 2301 movs r3, #1
|
|
8003c9e: e08d b.n 8003dbc <HAL_I2C_Init+0x12e>
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8003ca0: 687b ldr r3, [r7, #4]
|
|
8003ca2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8003ca6: b2db uxtb r3, r3
|
|
8003ca8: 2b00 cmp r3, #0
|
|
8003caa: d106 bne.n 8003cba <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8003cac: 687b ldr r3, [r7, #4]
|
|
8003cae: 2200 movs r2, #0
|
|
8003cb0: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8003cb4: 6878 ldr r0, [r7, #4]
|
|
8003cb6: f7fe fe9d bl 80029f4 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8003cba: 687b ldr r3, [r7, #4]
|
|
8003cbc: 2224 movs r2, #36 @ 0x24
|
|
8003cbe: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8003cc2: 687b ldr r3, [r7, #4]
|
|
8003cc4: 681b ldr r3, [r3, #0]
|
|
8003cc6: 681a ldr r2, [r3, #0]
|
|
8003cc8: 687b ldr r3, [r7, #4]
|
|
8003cca: 681b ldr r3, [r3, #0]
|
|
8003ccc: f022 0201 bic.w r2, r2, #1
|
|
8003cd0: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
|
|
8003cd2: 687b ldr r3, [r7, #4]
|
|
8003cd4: 685a ldr r2, [r3, #4]
|
|
8003cd6: 687b ldr r3, [r7, #4]
|
|
8003cd8: 681b ldr r3, [r3, #0]
|
|
8003cda: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
|
|
8003cde: 611a str r2, [r3, #16]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Disable Own Address1 before set the Own Address1 configuration */
|
|
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
|
|
8003ce0: 687b ldr r3, [r7, #4]
|
|
8003ce2: 681b ldr r3, [r3, #0]
|
|
8003ce4: 689a ldr r2, [r3, #8]
|
|
8003ce6: 687b ldr r3, [r7, #4]
|
|
8003ce8: 681b ldr r3, [r3, #0]
|
|
8003cea: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8003cee: 609a str r2, [r3, #8]
|
|
|
|
/* Configure I2Cx: Own Address1 and ack own address1 mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
8003cf0: 687b ldr r3, [r7, #4]
|
|
8003cf2: 68db ldr r3, [r3, #12]
|
|
8003cf4: 2b01 cmp r3, #1
|
|
8003cf6: d107 bne.n 8003d08 <HAL_I2C_Init+0x7a>
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
|
|
8003cf8: 687b ldr r3, [r7, #4]
|
|
8003cfa: 689a ldr r2, [r3, #8]
|
|
8003cfc: 687b ldr r3, [r7, #4]
|
|
8003cfe: 681b ldr r3, [r3, #0]
|
|
8003d00: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8003d04: 609a str r2, [r3, #8]
|
|
8003d06: e006 b.n 8003d16 <HAL_I2C_Init+0x88>
|
|
}
|
|
else /* I2C_ADDRESSINGMODE_10BIT */
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
|
|
8003d08: 687b ldr r3, [r7, #4]
|
|
8003d0a: 689a ldr r2, [r3, #8]
|
|
8003d0c: 687b ldr r3, [r7, #4]
|
|
8003d0e: 681b ldr r3, [r3, #0]
|
|
8003d10: f442 4204 orr.w r2, r2, #33792 @ 0x8400
|
|
8003d14: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Addressing Master mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
8003d16: 687b ldr r3, [r7, #4]
|
|
8003d18: 68db ldr r3, [r3, #12]
|
|
8003d1a: 2b02 cmp r3, #2
|
|
8003d1c: d108 bne.n 8003d30 <HAL_I2C_Init+0xa2>
|
|
{
|
|
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
8003d1e: 687b ldr r3, [r7, #4]
|
|
8003d20: 681b ldr r3, [r3, #0]
|
|
8003d22: 685a ldr r2, [r3, #4]
|
|
8003d24: 687b ldr r3, [r7, #4]
|
|
8003d26: 681b ldr r3, [r3, #0]
|
|
8003d28: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8003d2c: 605a str r2, [r3, #4]
|
|
8003d2e: e007 b.n 8003d40 <HAL_I2C_Init+0xb2>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the I2C ADD10 bit */
|
|
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
8003d30: 687b ldr r3, [r7, #4]
|
|
8003d32: 681b ldr r3, [r3, #0]
|
|
8003d34: 685a ldr r2, [r3, #4]
|
|
8003d36: 687b ldr r3, [r7, #4]
|
|
8003d38: 681b ldr r3, [r3, #0]
|
|
8003d3a: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8003d3e: 605a str r2, [r3, #4]
|
|
}
|
|
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
|
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
|
8003d40: 687b ldr r3, [r7, #4]
|
|
8003d42: 681b ldr r3, [r3, #0]
|
|
8003d44: 685b ldr r3, [r3, #4]
|
|
8003d46: 687a ldr r2, [r7, #4]
|
|
8003d48: 6812 ldr r2, [r2, #0]
|
|
8003d4a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
8003d4e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8003d52: 6053 str r3, [r2, #4]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Disable Own Address2 before set the Own Address2 configuration */
|
|
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
|
|
8003d54: 687b ldr r3, [r7, #4]
|
|
8003d56: 681b ldr r3, [r3, #0]
|
|
8003d58: 68da ldr r2, [r3, #12]
|
|
8003d5a: 687b ldr r3, [r7, #4]
|
|
8003d5c: 681b ldr r3, [r3, #0]
|
|
8003d5e: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8003d62: 60da str r2, [r3, #12]
|
|
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8003d64: 687b ldr r3, [r7, #4]
|
|
8003d66: 691a ldr r2, [r3, #16]
|
|
8003d68: 687b ldr r3, [r7, #4]
|
|
8003d6a: 695b ldr r3, [r3, #20]
|
|
8003d6c: ea42 0103 orr.w r1, r2, r3
|
|
(hi2c->Init.OwnAddress2Masks << 8));
|
|
8003d70: 687b ldr r3, [r7, #4]
|
|
8003d72: 699b ldr r3, [r3, #24]
|
|
8003d74: 021a lsls r2, r3, #8
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8003d76: 687b ldr r3, [r7, #4]
|
|
8003d78: 681b ldr r3, [r3, #0]
|
|
8003d7a: 430a orrs r2, r1
|
|
8003d7c: 60da str r2, [r3, #12]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
|
|
8003d7e: 687b ldr r3, [r7, #4]
|
|
8003d80: 69d9 ldr r1, [r3, #28]
|
|
8003d82: 687b ldr r3, [r7, #4]
|
|
8003d84: 6a1a ldr r2, [r3, #32]
|
|
8003d86: 687b ldr r3, [r7, #4]
|
|
8003d88: 681b ldr r3, [r3, #0]
|
|
8003d8a: 430a orrs r2, r1
|
|
8003d8c: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003d8e: 687b ldr r3, [r7, #4]
|
|
8003d90: 681b ldr r3, [r3, #0]
|
|
8003d92: 681a ldr r2, [r3, #0]
|
|
8003d94: 687b ldr r3, [r7, #4]
|
|
8003d96: 681b ldr r3, [r3, #0]
|
|
8003d98: f042 0201 orr.w r2, r2, #1
|
|
8003d9c: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8003d9e: 687b ldr r3, [r7, #4]
|
|
8003da0: 2200 movs r2, #0
|
|
8003da2: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003da4: 687b ldr r3, [r7, #4]
|
|
8003da6: 2220 movs r2, #32
|
|
8003da8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8003dac: 687b ldr r3, [r7, #4]
|
|
8003dae: 2200 movs r2, #0
|
|
8003db0: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003db2: 687b ldr r3, [r7, #4]
|
|
8003db4: 2200 movs r2, #0
|
|
8003db6: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_OK;
|
|
8003dba: 2300 movs r3, #0
|
|
}
|
|
8003dbc: 4618 mov r0, r3
|
|
8003dbe: 3708 adds r7, #8
|
|
8003dc0: 46bd mov sp, r7
|
|
8003dc2: bd80 pop {r7, pc}
|
|
|
|
08003dc4 <HAL_I2C_DeInit>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8003dc4: b580 push {r7, lr}
|
|
8003dc6: b082 sub sp, #8
|
|
8003dc8: af00 add r7, sp, #0
|
|
8003dca: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8003dcc: 687b ldr r3, [r7, #4]
|
|
8003dce: 2b00 cmp r3, #0
|
|
8003dd0: d101 bne.n 8003dd6 <HAL_I2C_DeInit+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003dd2: 2301 movs r3, #1
|
|
8003dd4: e021 b.n 8003e1a <HAL_I2C_DeInit+0x56>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8003dd6: 687b ldr r3, [r7, #4]
|
|
8003dd8: 2224 movs r2, #36 @ 0x24
|
|
8003dda: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the I2C Peripheral Clock */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8003dde: 687b ldr r3, [r7, #4]
|
|
8003de0: 681b ldr r3, [r3, #0]
|
|
8003de2: 681a ldr r2, [r3, #0]
|
|
8003de4: 687b ldr r3, [r7, #4]
|
|
8003de6: 681b ldr r3, [r3, #0]
|
|
8003de8: f022 0201 bic.w r2, r2, #1
|
|
8003dec: 601a str r2, [r3, #0]
|
|
|
|
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
hi2c->MspDeInitCallback(hi2c);
|
|
#else
|
|
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspDeInit(hi2c);
|
|
8003dee: 6878 ldr r0, [r7, #4]
|
|
8003df0: f7fe fe5e bl 8002ab0 <HAL_I2C_MspDeInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8003df4: 687b ldr r3, [r7, #4]
|
|
8003df6: 2200 movs r2, #0
|
|
8003df8: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_RESET;
|
|
8003dfa: 687b ldr r3, [r7, #4]
|
|
8003dfc: 2200 movs r2, #0
|
|
8003dfe: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8003e02: 687b ldr r3, [r7, #4]
|
|
8003e04: 2200 movs r2, #0
|
|
8003e06: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003e08: 687b ldr r3, [r7, #4]
|
|
8003e0a: 2200 movs r2, #0
|
|
8003e0c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hi2c);
|
|
8003e10: 687b ldr r3, [r7, #4]
|
|
8003e12: 2200 movs r2, #0
|
|
8003e14: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8003e18: 2300 movs r3, #0
|
|
}
|
|
8003e1a: 4618 mov r0, r3
|
|
8003e1c: 3708 adds r7, #8
|
|
8003e1e: 46bd mov sp, r7
|
|
8003e20: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08003e24 <HAL_I2C_Mem_Write>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8003e24: b580 push {r7, lr}
|
|
8003e26: b088 sub sp, #32
|
|
8003e28: af02 add r7, sp, #8
|
|
8003e2a: 60f8 str r0, [r7, #12]
|
|
8003e2c: 4608 mov r0, r1
|
|
8003e2e: 4611 mov r1, r2
|
|
8003e30: 461a mov r2, r3
|
|
8003e32: 4603 mov r3, r0
|
|
8003e34: 817b strh r3, [r7, #10]
|
|
8003e36: 460b mov r3, r1
|
|
8003e38: 813b strh r3, [r7, #8]
|
|
8003e3a: 4613 mov r3, r2
|
|
8003e3c: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8003e3e: 68fb ldr r3, [r7, #12]
|
|
8003e40: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8003e44: b2db uxtb r3, r3
|
|
8003e46: 2b20 cmp r3, #32
|
|
8003e48: f040 80f9 bne.w 800403e <HAL_I2C_Mem_Write+0x21a>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8003e4c: 6a3b ldr r3, [r7, #32]
|
|
8003e4e: 2b00 cmp r3, #0
|
|
8003e50: d002 beq.n 8003e58 <HAL_I2C_Mem_Write+0x34>
|
|
8003e52: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
8003e54: 2b00 cmp r3, #0
|
|
8003e56: d105 bne.n 8003e64 <HAL_I2C_Mem_Write+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8003e58: 68fb ldr r3, [r7, #12]
|
|
8003e5a: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8003e5e: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
8003e60: 2301 movs r3, #1
|
|
8003e62: e0ed b.n 8004040 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8003e64: 68fb ldr r3, [r7, #12]
|
|
8003e66: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8003e6a: 2b01 cmp r3, #1
|
|
8003e6c: d101 bne.n 8003e72 <HAL_I2C_Mem_Write+0x4e>
|
|
8003e6e: 2302 movs r3, #2
|
|
8003e70: e0e6 b.n 8004040 <HAL_I2C_Mem_Write+0x21c>
|
|
8003e72: 68fb ldr r3, [r7, #12]
|
|
8003e74: 2201 movs r2, #1
|
|
8003e76: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8003e7a: f7ff f9e1 bl 8003240 <HAL_GetTick>
|
|
8003e7e: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8003e80: 697b ldr r3, [r7, #20]
|
|
8003e82: 9300 str r3, [sp, #0]
|
|
8003e84: 2319 movs r3, #25
|
|
8003e86: 2201 movs r2, #1
|
|
8003e88: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
8003e8c: 68f8 ldr r0, [r7, #12]
|
|
8003e8e: f000 fac3 bl 8004418 <I2C_WaitOnFlagUntilTimeout>
|
|
8003e92: 4603 mov r3, r0
|
|
8003e94: 2b00 cmp r3, #0
|
|
8003e96: d001 beq.n 8003e9c <HAL_I2C_Mem_Write+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e98: 2301 movs r3, #1
|
|
8003e9a: e0d1 b.n 8004040 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
8003e9c: 68fb ldr r3, [r7, #12]
|
|
8003e9e: 2221 movs r2, #33 @ 0x21
|
|
8003ea0: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8003ea4: 68fb ldr r3, [r7, #12]
|
|
8003ea6: 2240 movs r2, #64 @ 0x40
|
|
8003ea8: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8003eac: 68fb ldr r3, [r7, #12]
|
|
8003eae: 2200 movs r2, #0
|
|
8003eb0: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8003eb2: 68fb ldr r3, [r7, #12]
|
|
8003eb4: 6a3a ldr r2, [r7, #32]
|
|
8003eb6: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8003eb8: 68fb ldr r3, [r7, #12]
|
|
8003eba: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
8003ebc: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8003ebe: 68fb ldr r3, [r7, #12]
|
|
8003ec0: 2200 movs r2, #0
|
|
8003ec2: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8003ec4: 88f8 ldrh r0, [r7, #6]
|
|
8003ec6: 893a ldrh r2, [r7, #8]
|
|
8003ec8: 8979 ldrh r1, [r7, #10]
|
|
8003eca: 697b ldr r3, [r7, #20]
|
|
8003ecc: 9301 str r3, [sp, #4]
|
|
8003ece: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003ed0: 9300 str r3, [sp, #0]
|
|
8003ed2: 4603 mov r3, r0
|
|
8003ed4: 68f8 ldr r0, [r7, #12]
|
|
8003ed6: f000 f9d3 bl 8004280 <I2C_RequestMemoryWrite>
|
|
8003eda: 4603 mov r3, r0
|
|
8003edc: 2b00 cmp r3, #0
|
|
8003ede: d005 beq.n 8003eec <HAL_I2C_Mem_Write+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8003ee0: 68fb ldr r3, [r7, #12]
|
|
8003ee2: 2200 movs r2, #0
|
|
8003ee4: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8003ee8: 2301 movs r3, #1
|
|
8003eea: e0a9 b.n 8004040 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8003eec: 68fb ldr r3, [r7, #12]
|
|
8003eee: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003ef0: b29b uxth r3, r3
|
|
8003ef2: 2bff cmp r3, #255 @ 0xff
|
|
8003ef4: d90e bls.n 8003f14 <HAL_I2C_Mem_Write+0xf0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8003ef6: 68fb ldr r3, [r7, #12]
|
|
8003ef8: 22ff movs r2, #255 @ 0xff
|
|
8003efa: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
8003efc: 68fb ldr r3, [r7, #12]
|
|
8003efe: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003f00: b2da uxtb r2, r3
|
|
8003f02: 8979 ldrh r1, [r7, #10]
|
|
8003f04: 2300 movs r3, #0
|
|
8003f06: 9300 str r3, [sp, #0]
|
|
8003f08: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8003f0c: 68f8 ldr r0, [r7, #12]
|
|
8003f0e: f000 fc47 bl 80047a0 <I2C_TransferConfig>
|
|
8003f12: e00f b.n 8003f34 <HAL_I2C_Mem_Write+0x110>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8003f14: 68fb ldr r3, [r7, #12]
|
|
8003f16: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003f18: b29a uxth r2, r3
|
|
8003f1a: 68fb ldr r3, [r7, #12]
|
|
8003f1c: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
8003f1e: 68fb ldr r3, [r7, #12]
|
|
8003f20: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003f22: b2da uxtb r2, r3
|
|
8003f24: 8979 ldrh r1, [r7, #10]
|
|
8003f26: 2300 movs r3, #0
|
|
8003f28: 9300 str r3, [sp, #0]
|
|
8003f2a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8003f2e: 68f8 ldr r0, [r7, #12]
|
|
8003f30: f000 fc36 bl 80047a0 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8003f34: 697a ldr r2, [r7, #20]
|
|
8003f36: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8003f38: 68f8 ldr r0, [r7, #12]
|
|
8003f3a: f000 fac6 bl 80044ca <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8003f3e: 4603 mov r3, r0
|
|
8003f40: 2b00 cmp r3, #0
|
|
8003f42: d001 beq.n 8003f48 <HAL_I2C_Mem_Write+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
8003f44: 2301 movs r3, #1
|
|
8003f46: e07b b.n 8004040 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Write data to TXDR */
|
|
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
|
8003f48: 68fb ldr r3, [r7, #12]
|
|
8003f4a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003f4c: 781a ldrb r2, [r3, #0]
|
|
8003f4e: 68fb ldr r3, [r7, #12]
|
|
8003f50: 681b ldr r3, [r3, #0]
|
|
8003f52: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8003f54: 68fb ldr r3, [r7, #12]
|
|
8003f56: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003f58: 1c5a adds r2, r3, #1
|
|
8003f5a: 68fb ldr r3, [r7, #12]
|
|
8003f5c: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferCount--;
|
|
8003f5e: 68fb ldr r3, [r7, #12]
|
|
8003f60: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003f62: b29b uxth r3, r3
|
|
8003f64: 3b01 subs r3, #1
|
|
8003f66: b29a uxth r2, r3
|
|
8003f68: 68fb ldr r3, [r7, #12]
|
|
8003f6a: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize--;
|
|
8003f6c: 68fb ldr r3, [r7, #12]
|
|
8003f6e: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003f70: 3b01 subs r3, #1
|
|
8003f72: b29a uxth r2, r3
|
|
8003f74: 68fb ldr r3, [r7, #12]
|
|
8003f76: 851a strh r2, [r3, #40] @ 0x28
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8003f78: 68fb ldr r3, [r7, #12]
|
|
8003f7a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003f7c: b29b uxth r3, r3
|
|
8003f7e: 2b00 cmp r3, #0
|
|
8003f80: d034 beq.n 8003fec <HAL_I2C_Mem_Write+0x1c8>
|
|
8003f82: 68fb ldr r3, [r7, #12]
|
|
8003f84: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003f86: 2b00 cmp r3, #0
|
|
8003f88: d130 bne.n 8003fec <HAL_I2C_Mem_Write+0x1c8>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8003f8a: 697b ldr r3, [r7, #20]
|
|
8003f8c: 9300 str r3, [sp, #0]
|
|
8003f8e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003f90: 2200 movs r2, #0
|
|
8003f92: 2180 movs r1, #128 @ 0x80
|
|
8003f94: 68f8 ldr r0, [r7, #12]
|
|
8003f96: f000 fa3f bl 8004418 <I2C_WaitOnFlagUntilTimeout>
|
|
8003f9a: 4603 mov r3, r0
|
|
8003f9c: 2b00 cmp r3, #0
|
|
8003f9e: d001 beq.n 8003fa4 <HAL_I2C_Mem_Write+0x180>
|
|
{
|
|
return HAL_ERROR;
|
|
8003fa0: 2301 movs r3, #1
|
|
8003fa2: e04d b.n 8004040 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8003fa4: 68fb ldr r3, [r7, #12]
|
|
8003fa6: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003fa8: b29b uxth r3, r3
|
|
8003faa: 2bff cmp r3, #255 @ 0xff
|
|
8003fac: d90e bls.n 8003fcc <HAL_I2C_Mem_Write+0x1a8>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8003fae: 68fb ldr r3, [r7, #12]
|
|
8003fb0: 22ff movs r2, #255 @ 0xff
|
|
8003fb2: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8003fb4: 68fb ldr r3, [r7, #12]
|
|
8003fb6: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003fb8: b2da uxtb r2, r3
|
|
8003fba: 8979 ldrh r1, [r7, #10]
|
|
8003fbc: 2300 movs r3, #0
|
|
8003fbe: 9300 str r3, [sp, #0]
|
|
8003fc0: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8003fc4: 68f8 ldr r0, [r7, #12]
|
|
8003fc6: f000 fbeb bl 80047a0 <I2C_TransferConfig>
|
|
8003fca: e00f b.n 8003fec <HAL_I2C_Mem_Write+0x1c8>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8003fcc: 68fb ldr r3, [r7, #12]
|
|
8003fce: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003fd0: b29a uxth r2, r3
|
|
8003fd2: 68fb ldr r3, [r7, #12]
|
|
8003fd4: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8003fd6: 68fb ldr r3, [r7, #12]
|
|
8003fd8: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003fda: b2da uxtb r2, r3
|
|
8003fdc: 8979 ldrh r1, [r7, #10]
|
|
8003fde: 2300 movs r3, #0
|
|
8003fe0: 9300 str r3, [sp, #0]
|
|
8003fe2: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8003fe6: 68f8 ldr r0, [r7, #12]
|
|
8003fe8: f000 fbda bl 80047a0 <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
|
|
} while (hi2c->XferCount > 0U);
|
|
8003fec: 68fb ldr r3, [r7, #12]
|
|
8003fee: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003ff0: b29b uxth r3, r3
|
|
8003ff2: 2b00 cmp r3, #0
|
|
8003ff4: d19e bne.n 8003f34 <HAL_I2C_Mem_Write+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8003ff6: 697a ldr r2, [r7, #20]
|
|
8003ff8: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8003ffa: 68f8 ldr r0, [r7, #12]
|
|
8003ffc: f000 faac bl 8004558 <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8004000: 4603 mov r3, r0
|
|
8004002: 2b00 cmp r3, #0
|
|
8004004: d001 beq.n 800400a <HAL_I2C_Mem_Write+0x1e6>
|
|
{
|
|
return HAL_ERROR;
|
|
8004006: 2301 movs r3, #1
|
|
8004008: e01a b.n 8004040 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
800400a: 68fb ldr r3, [r7, #12]
|
|
800400c: 681b ldr r3, [r3, #0]
|
|
800400e: 2220 movs r2, #32
|
|
8004010: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8004012: 68fb ldr r3, [r7, #12]
|
|
8004014: 681b ldr r3, [r3, #0]
|
|
8004016: 6859 ldr r1, [r3, #4]
|
|
8004018: 68fb ldr r3, [r7, #12]
|
|
800401a: 681a ldr r2, [r3, #0]
|
|
800401c: 4b0a ldr r3, [pc, #40] @ (8004048 <HAL_I2C_Mem_Write+0x224>)
|
|
800401e: 400b ands r3, r1
|
|
8004020: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004022: 68fb ldr r3, [r7, #12]
|
|
8004024: 2220 movs r2, #32
|
|
8004026: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800402a: 68fb ldr r3, [r7, #12]
|
|
800402c: 2200 movs r2, #0
|
|
800402e: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004032: 68fb ldr r3, [r7, #12]
|
|
8004034: 2200 movs r2, #0
|
|
8004036: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
800403a: 2300 movs r3, #0
|
|
800403c: e000 b.n 8004040 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800403e: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004040: 4618 mov r0, r3
|
|
8004042: 3718 adds r7, #24
|
|
8004044: 46bd mov sp, r7
|
|
8004046: bd80 pop {r7, pc}
|
|
8004048: fe00e800 .word 0xfe00e800
|
|
|
|
0800404c <HAL_I2C_Mem_Read>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
800404c: b580 push {r7, lr}
|
|
800404e: b088 sub sp, #32
|
|
8004050: af02 add r7, sp, #8
|
|
8004052: 60f8 str r0, [r7, #12]
|
|
8004054: 4608 mov r0, r1
|
|
8004056: 4611 mov r1, r2
|
|
8004058: 461a mov r2, r3
|
|
800405a: 4603 mov r3, r0
|
|
800405c: 817b strh r3, [r7, #10]
|
|
800405e: 460b mov r3, r1
|
|
8004060: 813b strh r3, [r7, #8]
|
|
8004062: 4613 mov r3, r2
|
|
8004064: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8004066: 68fb ldr r3, [r7, #12]
|
|
8004068: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800406c: b2db uxtb r3, r3
|
|
800406e: 2b20 cmp r3, #32
|
|
8004070: f040 80fd bne.w 800426e <HAL_I2C_Mem_Read+0x222>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004074: 6a3b ldr r3, [r7, #32]
|
|
8004076: 2b00 cmp r3, #0
|
|
8004078: d002 beq.n 8004080 <HAL_I2C_Mem_Read+0x34>
|
|
800407a: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
800407c: 2b00 cmp r3, #0
|
|
800407e: d105 bne.n 800408c <HAL_I2C_Mem_Read+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8004080: 68fb ldr r3, [r7, #12]
|
|
8004082: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8004086: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
8004088: 2301 movs r3, #1
|
|
800408a: e0f1 b.n 8004270 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
800408c: 68fb ldr r3, [r7, #12]
|
|
800408e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8004092: 2b01 cmp r3, #1
|
|
8004094: d101 bne.n 800409a <HAL_I2C_Mem_Read+0x4e>
|
|
8004096: 2302 movs r3, #2
|
|
8004098: e0ea b.n 8004270 <HAL_I2C_Mem_Read+0x224>
|
|
800409a: 68fb ldr r3, [r7, #12]
|
|
800409c: 2201 movs r2, #1
|
|
800409e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
80040a2: f7ff f8cd bl 8003240 <HAL_GetTick>
|
|
80040a6: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
80040a8: 697b ldr r3, [r7, #20]
|
|
80040aa: 9300 str r3, [sp, #0]
|
|
80040ac: 2319 movs r3, #25
|
|
80040ae: 2201 movs r2, #1
|
|
80040b0: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
80040b4: 68f8 ldr r0, [r7, #12]
|
|
80040b6: f000 f9af bl 8004418 <I2C_WaitOnFlagUntilTimeout>
|
|
80040ba: 4603 mov r3, r0
|
|
80040bc: 2b00 cmp r3, #0
|
|
80040be: d001 beq.n 80040c4 <HAL_I2C_Mem_Read+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
80040c0: 2301 movs r3, #1
|
|
80040c2: e0d5 b.n 8004270 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
80040c4: 68fb ldr r3, [r7, #12]
|
|
80040c6: 2222 movs r2, #34 @ 0x22
|
|
80040c8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
80040cc: 68fb ldr r3, [r7, #12]
|
|
80040ce: 2240 movs r2, #64 @ 0x40
|
|
80040d0: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
80040d4: 68fb ldr r3, [r7, #12]
|
|
80040d6: 2200 movs r2, #0
|
|
80040d8: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
80040da: 68fb ldr r3, [r7, #12]
|
|
80040dc: 6a3a ldr r2, [r7, #32]
|
|
80040de: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
80040e0: 68fb ldr r3, [r7, #12]
|
|
80040e2: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
80040e4: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferISR = NULL;
|
|
80040e6: 68fb ldr r3, [r7, #12]
|
|
80040e8: 2200 movs r2, #0
|
|
80040ea: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
80040ec: 88f8 ldrh r0, [r7, #6]
|
|
80040ee: 893a ldrh r2, [r7, #8]
|
|
80040f0: 8979 ldrh r1, [r7, #10]
|
|
80040f2: 697b ldr r3, [r7, #20]
|
|
80040f4: 9301 str r3, [sp, #4]
|
|
80040f6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80040f8: 9300 str r3, [sp, #0]
|
|
80040fa: 4603 mov r3, r0
|
|
80040fc: 68f8 ldr r0, [r7, #12]
|
|
80040fe: f000 f913 bl 8004328 <I2C_RequestMemoryRead>
|
|
8004102: 4603 mov r3, r0
|
|
8004104: 2b00 cmp r3, #0
|
|
8004106: d005 beq.n 8004114 <HAL_I2C_Mem_Read+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004108: 68fb ldr r3, [r7, #12]
|
|
800410a: 2200 movs r2, #0
|
|
800410c: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8004110: 2301 movs r3, #1
|
|
8004112: e0ad b.n 8004270 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Send Slave Address */
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8004114: 68fb ldr r3, [r7, #12]
|
|
8004116: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004118: b29b uxth r3, r3
|
|
800411a: 2bff cmp r3, #255 @ 0xff
|
|
800411c: d90e bls.n 800413c <HAL_I2C_Mem_Read+0xf0>
|
|
{
|
|
hi2c->XferSize = 1U;
|
|
800411e: 68fb ldr r3, [r7, #12]
|
|
8004120: 2201 movs r2, #1
|
|
8004122: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8004124: 68fb ldr r3, [r7, #12]
|
|
8004126: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004128: b2da uxtb r2, r3
|
|
800412a: 8979 ldrh r1, [r7, #10]
|
|
800412c: 4b52 ldr r3, [pc, #328] @ (8004278 <HAL_I2C_Mem_Read+0x22c>)
|
|
800412e: 9300 str r3, [sp, #0]
|
|
8004130: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8004134: 68f8 ldr r0, [r7, #12]
|
|
8004136: f000 fb33 bl 80047a0 <I2C_TransferConfig>
|
|
800413a: e00f b.n 800415c <HAL_I2C_Mem_Read+0x110>
|
|
I2C_GENERATE_START_READ);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
800413c: 68fb ldr r3, [r7, #12]
|
|
800413e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004140: b29a uxth r2, r3
|
|
8004142: 68fb ldr r3, [r7, #12]
|
|
8004144: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8004146: 68fb ldr r3, [r7, #12]
|
|
8004148: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800414a: b2da uxtb r2, r3
|
|
800414c: 8979 ldrh r1, [r7, #10]
|
|
800414e: 4b4a ldr r3, [pc, #296] @ (8004278 <HAL_I2C_Mem_Read+0x22c>)
|
|
8004150: 9300 str r3, [sp, #0]
|
|
8004152: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8004156: 68f8 ldr r0, [r7, #12]
|
|
8004158: f000 fb22 bl 80047a0 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
|
|
800415c: 697b ldr r3, [r7, #20]
|
|
800415e: 9300 str r3, [sp, #0]
|
|
8004160: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004162: 2200 movs r2, #0
|
|
8004164: 2104 movs r1, #4
|
|
8004166: 68f8 ldr r0, [r7, #12]
|
|
8004168: f000 f956 bl 8004418 <I2C_WaitOnFlagUntilTimeout>
|
|
800416c: 4603 mov r3, r0
|
|
800416e: 2b00 cmp r3, #0
|
|
8004170: d001 beq.n 8004176 <HAL_I2C_Mem_Read+0x12a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004172: 2301 movs r3, #1
|
|
8004174: e07c b.n 8004270 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
8004176: 68fb ldr r3, [r7, #12]
|
|
8004178: 681b ldr r3, [r3, #0]
|
|
800417a: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
800417c: 68fb ldr r3, [r7, #12]
|
|
800417e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004180: b2d2 uxtb r2, r2
|
|
8004182: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8004184: 68fb ldr r3, [r7, #12]
|
|
8004186: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004188: 1c5a adds r2, r3, #1
|
|
800418a: 68fb ldr r3, [r7, #12]
|
|
800418c: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferSize--;
|
|
800418e: 68fb ldr r3, [r7, #12]
|
|
8004190: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8004192: 3b01 subs r3, #1
|
|
8004194: b29a uxth r2, r3
|
|
8004196: 68fb ldr r3, [r7, #12]
|
|
8004198: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
800419a: 68fb ldr r3, [r7, #12]
|
|
800419c: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800419e: b29b uxth r3, r3
|
|
80041a0: 3b01 subs r3, #1
|
|
80041a2: b29a uxth r2, r3
|
|
80041a4: 68fb ldr r3, [r7, #12]
|
|
80041a6: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
80041a8: 68fb ldr r3, [r7, #12]
|
|
80041aa: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80041ac: b29b uxth r3, r3
|
|
80041ae: 2b00 cmp r3, #0
|
|
80041b0: d034 beq.n 800421c <HAL_I2C_Mem_Read+0x1d0>
|
|
80041b2: 68fb ldr r3, [r7, #12]
|
|
80041b4: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80041b6: 2b00 cmp r3, #0
|
|
80041b8: d130 bne.n 800421c <HAL_I2C_Mem_Read+0x1d0>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
80041ba: 697b ldr r3, [r7, #20]
|
|
80041bc: 9300 str r3, [sp, #0]
|
|
80041be: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80041c0: 2200 movs r2, #0
|
|
80041c2: 2180 movs r1, #128 @ 0x80
|
|
80041c4: 68f8 ldr r0, [r7, #12]
|
|
80041c6: f000 f927 bl 8004418 <I2C_WaitOnFlagUntilTimeout>
|
|
80041ca: 4603 mov r3, r0
|
|
80041cc: 2b00 cmp r3, #0
|
|
80041ce: d001 beq.n 80041d4 <HAL_I2C_Mem_Read+0x188>
|
|
{
|
|
return HAL_ERROR;
|
|
80041d0: 2301 movs r3, #1
|
|
80041d2: e04d b.n 8004270 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
80041d4: 68fb ldr r3, [r7, #12]
|
|
80041d6: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80041d8: b29b uxth r3, r3
|
|
80041da: 2bff cmp r3, #255 @ 0xff
|
|
80041dc: d90e bls.n 80041fc <HAL_I2C_Mem_Read+0x1b0>
|
|
{
|
|
hi2c->XferSize = 1U;
|
|
80041de: 68fb ldr r3, [r7, #12]
|
|
80041e0: 2201 movs r2, #1
|
|
80041e2: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
|
|
80041e4: 68fb ldr r3, [r7, #12]
|
|
80041e6: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80041e8: b2da uxtb r2, r3
|
|
80041ea: 8979 ldrh r1, [r7, #10]
|
|
80041ec: 2300 movs r3, #0
|
|
80041ee: 9300 str r3, [sp, #0]
|
|
80041f0: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
80041f4: 68f8 ldr r0, [r7, #12]
|
|
80041f6: f000 fad3 bl 80047a0 <I2C_TransferConfig>
|
|
80041fa: e00f b.n 800421c <HAL_I2C_Mem_Read+0x1d0>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
80041fc: 68fb ldr r3, [r7, #12]
|
|
80041fe: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004200: b29a uxth r2, r3
|
|
8004202: 68fb ldr r3, [r7, #12]
|
|
8004204: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8004206: 68fb ldr r3, [r7, #12]
|
|
8004208: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800420a: b2da uxtb r2, r3
|
|
800420c: 8979 ldrh r1, [r7, #10]
|
|
800420e: 2300 movs r3, #0
|
|
8004210: 9300 str r3, [sp, #0]
|
|
8004212: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8004216: 68f8 ldr r0, [r7, #12]
|
|
8004218: f000 fac2 bl 80047a0 <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
} while (hi2c->XferCount > 0U);
|
|
800421c: 68fb ldr r3, [r7, #12]
|
|
800421e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8004220: b29b uxth r3, r3
|
|
8004222: 2b00 cmp r3, #0
|
|
8004224: d19a bne.n 800415c <HAL_I2C_Mem_Read+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8004226: 697a ldr r2, [r7, #20]
|
|
8004228: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
800422a: 68f8 ldr r0, [r7, #12]
|
|
800422c: f000 f994 bl 8004558 <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8004230: 4603 mov r3, r0
|
|
8004232: 2b00 cmp r3, #0
|
|
8004234: d001 beq.n 800423a <HAL_I2C_Mem_Read+0x1ee>
|
|
{
|
|
return HAL_ERROR;
|
|
8004236: 2301 movs r3, #1
|
|
8004238: e01a b.n 8004270 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
800423a: 68fb ldr r3, [r7, #12]
|
|
800423c: 681b ldr r3, [r3, #0]
|
|
800423e: 2220 movs r2, #32
|
|
8004240: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8004242: 68fb ldr r3, [r7, #12]
|
|
8004244: 681b ldr r3, [r3, #0]
|
|
8004246: 6859 ldr r1, [r3, #4]
|
|
8004248: 68fb ldr r3, [r7, #12]
|
|
800424a: 681a ldr r2, [r3, #0]
|
|
800424c: 4b0b ldr r3, [pc, #44] @ (800427c <HAL_I2C_Mem_Read+0x230>)
|
|
800424e: 400b ands r3, r1
|
|
8004250: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004252: 68fb ldr r3, [r7, #12]
|
|
8004254: 2220 movs r2, #32
|
|
8004256: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800425a: 68fb ldr r3, [r7, #12]
|
|
800425c: 2200 movs r2, #0
|
|
800425e: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004262: 68fb ldr r3, [r7, #12]
|
|
8004264: 2200 movs r2, #0
|
|
8004266: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
800426a: 2300 movs r3, #0
|
|
800426c: e000 b.n 8004270 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800426e: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004270: 4618 mov r0, r3
|
|
8004272: 3718 adds r7, #24
|
|
8004274: 46bd mov sp, r7
|
|
8004276: bd80 pop {r7, pc}
|
|
8004278: 80002400 .word 0x80002400
|
|
800427c: fe00e800 .word 0xfe00e800
|
|
|
|
08004280 <I2C_RequestMemoryWrite>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8004280: b580 push {r7, lr}
|
|
8004282: b086 sub sp, #24
|
|
8004284: af02 add r7, sp, #8
|
|
8004286: 60f8 str r0, [r7, #12]
|
|
8004288: 4608 mov r0, r1
|
|
800428a: 4611 mov r1, r2
|
|
800428c: 461a mov r2, r3
|
|
800428e: 4603 mov r3, r0
|
|
8004290: 817b strh r3, [r7, #10]
|
|
8004292: 460b mov r3, r1
|
|
8004294: 813b strh r3, [r7, #8]
|
|
8004296: 4613 mov r3, r2
|
|
8004298: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
|
800429a: 88fb ldrh r3, [r7, #6]
|
|
800429c: b2da uxtb r2, r3
|
|
800429e: 8979 ldrh r1, [r7, #10]
|
|
80042a0: 4b20 ldr r3, [pc, #128] @ (8004324 <I2C_RequestMemoryWrite+0xa4>)
|
|
80042a2: 9300 str r3, [sp, #0]
|
|
80042a4: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
80042a8: 68f8 ldr r0, [r7, #12]
|
|
80042aa: f000 fa79 bl 80047a0 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80042ae: 69fa ldr r2, [r7, #28]
|
|
80042b0: 69b9 ldr r1, [r7, #24]
|
|
80042b2: 68f8 ldr r0, [r7, #12]
|
|
80042b4: f000 f909 bl 80044ca <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80042b8: 4603 mov r3, r0
|
|
80042ba: 2b00 cmp r3, #0
|
|
80042bc: d001 beq.n 80042c2 <I2C_RequestMemoryWrite+0x42>
|
|
{
|
|
return HAL_ERROR;
|
|
80042be: 2301 movs r3, #1
|
|
80042c0: e02c b.n 800431c <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
80042c2: 88fb ldrh r3, [r7, #6]
|
|
80042c4: 2b01 cmp r3, #1
|
|
80042c6: d105 bne.n 80042d4 <I2C_RequestMemoryWrite+0x54>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80042c8: 893b ldrh r3, [r7, #8]
|
|
80042ca: b2da uxtb r2, r3
|
|
80042cc: 68fb ldr r3, [r7, #12]
|
|
80042ce: 681b ldr r3, [r3, #0]
|
|
80042d0: 629a str r2, [r3, #40] @ 0x28
|
|
80042d2: e015 b.n 8004300 <I2C_RequestMemoryWrite+0x80>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
80042d4: 893b ldrh r3, [r7, #8]
|
|
80042d6: 0a1b lsrs r3, r3, #8
|
|
80042d8: b29b uxth r3, r3
|
|
80042da: b2da uxtb r2, r3
|
|
80042dc: 68fb ldr r3, [r7, #12]
|
|
80042de: 681b ldr r3, [r3, #0]
|
|
80042e0: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80042e2: 69fa ldr r2, [r7, #28]
|
|
80042e4: 69b9 ldr r1, [r7, #24]
|
|
80042e6: 68f8 ldr r0, [r7, #12]
|
|
80042e8: f000 f8ef bl 80044ca <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80042ec: 4603 mov r3, r0
|
|
80042ee: 2b00 cmp r3, #0
|
|
80042f0: d001 beq.n 80042f6 <I2C_RequestMemoryWrite+0x76>
|
|
{
|
|
return HAL_ERROR;
|
|
80042f2: 2301 movs r3, #1
|
|
80042f4: e012 b.n 800431c <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80042f6: 893b ldrh r3, [r7, #8]
|
|
80042f8: b2da uxtb r2, r3
|
|
80042fa: 68fb ldr r3, [r7, #12]
|
|
80042fc: 681b ldr r3, [r3, #0]
|
|
80042fe: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8004300: 69fb ldr r3, [r7, #28]
|
|
8004302: 9300 str r3, [sp, #0]
|
|
8004304: 69bb ldr r3, [r7, #24]
|
|
8004306: 2200 movs r2, #0
|
|
8004308: 2180 movs r1, #128 @ 0x80
|
|
800430a: 68f8 ldr r0, [r7, #12]
|
|
800430c: f000 f884 bl 8004418 <I2C_WaitOnFlagUntilTimeout>
|
|
8004310: 4603 mov r3, r0
|
|
8004312: 2b00 cmp r3, #0
|
|
8004314: d001 beq.n 800431a <I2C_RequestMemoryWrite+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004316: 2301 movs r3, #1
|
|
8004318: e000 b.n 800431c <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800431a: 2300 movs r3, #0
|
|
}
|
|
800431c: 4618 mov r0, r3
|
|
800431e: 3710 adds r7, #16
|
|
8004320: 46bd mov sp, r7
|
|
8004322: bd80 pop {r7, pc}
|
|
8004324: 80002000 .word 0x80002000
|
|
|
|
08004328 <I2C_RequestMemoryRead>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8004328: b580 push {r7, lr}
|
|
800432a: b086 sub sp, #24
|
|
800432c: af02 add r7, sp, #8
|
|
800432e: 60f8 str r0, [r7, #12]
|
|
8004330: 4608 mov r0, r1
|
|
8004332: 4611 mov r1, r2
|
|
8004334: 461a mov r2, r3
|
|
8004336: 4603 mov r3, r0
|
|
8004338: 817b strh r3, [r7, #10]
|
|
800433a: 460b mov r3, r1
|
|
800433c: 813b strh r3, [r7, #8]
|
|
800433e: 4613 mov r3, r2
|
|
8004340: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
|
8004342: 88fb ldrh r3, [r7, #6]
|
|
8004344: b2da uxtb r2, r3
|
|
8004346: 8979 ldrh r1, [r7, #10]
|
|
8004348: 4b20 ldr r3, [pc, #128] @ (80043cc <I2C_RequestMemoryRead+0xa4>)
|
|
800434a: 9300 str r3, [sp, #0]
|
|
800434c: 2300 movs r3, #0
|
|
800434e: 68f8 ldr r0, [r7, #12]
|
|
8004350: f000 fa26 bl 80047a0 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8004354: 69fa ldr r2, [r7, #28]
|
|
8004356: 69b9 ldr r1, [r7, #24]
|
|
8004358: 68f8 ldr r0, [r7, #12]
|
|
800435a: f000 f8b6 bl 80044ca <I2C_WaitOnTXISFlagUntilTimeout>
|
|
800435e: 4603 mov r3, r0
|
|
8004360: 2b00 cmp r3, #0
|
|
8004362: d001 beq.n 8004368 <I2C_RequestMemoryRead+0x40>
|
|
{
|
|
return HAL_ERROR;
|
|
8004364: 2301 movs r3, #1
|
|
8004366: e02c b.n 80043c2 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
8004368: 88fb ldrh r3, [r7, #6]
|
|
800436a: 2b01 cmp r3, #1
|
|
800436c: d105 bne.n 800437a <I2C_RequestMemoryRead+0x52>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
800436e: 893b ldrh r3, [r7, #8]
|
|
8004370: b2da uxtb r2, r3
|
|
8004372: 68fb ldr r3, [r7, #12]
|
|
8004374: 681b ldr r3, [r3, #0]
|
|
8004376: 629a str r2, [r3, #40] @ 0x28
|
|
8004378: e015 b.n 80043a6 <I2C_RequestMemoryRead+0x7e>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
800437a: 893b ldrh r3, [r7, #8]
|
|
800437c: 0a1b lsrs r3, r3, #8
|
|
800437e: b29b uxth r3, r3
|
|
8004380: b2da uxtb r2, r3
|
|
8004382: 68fb ldr r3, [r7, #12]
|
|
8004384: 681b ldr r3, [r3, #0]
|
|
8004386: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8004388: 69fa ldr r2, [r7, #28]
|
|
800438a: 69b9 ldr r1, [r7, #24]
|
|
800438c: 68f8 ldr r0, [r7, #12]
|
|
800438e: f000 f89c bl 80044ca <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8004392: 4603 mov r3, r0
|
|
8004394: 2b00 cmp r3, #0
|
|
8004396: d001 beq.n 800439c <I2C_RequestMemoryRead+0x74>
|
|
{
|
|
return HAL_ERROR;
|
|
8004398: 2301 movs r3, #1
|
|
800439a: e012 b.n 80043c2 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
800439c: 893b ldrh r3, [r7, #8]
|
|
800439e: b2da uxtb r2, r3
|
|
80043a0: 68fb ldr r3, [r7, #12]
|
|
80043a2: 681b ldr r3, [r3, #0]
|
|
80043a4: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until TC flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
|
|
80043a6: 69fb ldr r3, [r7, #28]
|
|
80043a8: 9300 str r3, [sp, #0]
|
|
80043aa: 69bb ldr r3, [r7, #24]
|
|
80043ac: 2200 movs r2, #0
|
|
80043ae: 2140 movs r1, #64 @ 0x40
|
|
80043b0: 68f8 ldr r0, [r7, #12]
|
|
80043b2: f000 f831 bl 8004418 <I2C_WaitOnFlagUntilTimeout>
|
|
80043b6: 4603 mov r3, r0
|
|
80043b8: 2b00 cmp r3, #0
|
|
80043ba: d001 beq.n 80043c0 <I2C_RequestMemoryRead+0x98>
|
|
{
|
|
return HAL_ERROR;
|
|
80043bc: 2301 movs r3, #1
|
|
80043be: e000 b.n 80043c2 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80043c0: 2300 movs r3, #0
|
|
}
|
|
80043c2: 4618 mov r0, r3
|
|
80043c4: 3710 adds r7, #16
|
|
80043c6: 46bd mov sp, r7
|
|
80043c8: bd80 pop {r7, pc}
|
|
80043ca: bf00 nop
|
|
80043cc: 80002000 .word 0x80002000
|
|
|
|
080043d0 <I2C_Flush_TXDR>:
|
|
* @brief I2C Tx data register flush process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
80043d0: b480 push {r7}
|
|
80043d2: b083 sub sp, #12
|
|
80043d4: af00 add r7, sp, #0
|
|
80043d6: 6078 str r0, [r7, #4]
|
|
/* If a pending TXIS flag is set */
|
|
/* Write a dummy data in TXDR to clear it */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
|
|
80043d8: 687b ldr r3, [r7, #4]
|
|
80043da: 681b ldr r3, [r3, #0]
|
|
80043dc: 699b ldr r3, [r3, #24]
|
|
80043de: f003 0302 and.w r3, r3, #2
|
|
80043e2: 2b02 cmp r3, #2
|
|
80043e4: d103 bne.n 80043ee <I2C_Flush_TXDR+0x1e>
|
|
{
|
|
hi2c->Instance->TXDR = 0x00U;
|
|
80043e6: 687b ldr r3, [r7, #4]
|
|
80043e8: 681b ldr r3, [r3, #0]
|
|
80043ea: 2200 movs r2, #0
|
|
80043ec: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Flush TX register if not empty */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
80043ee: 687b ldr r3, [r7, #4]
|
|
80043f0: 681b ldr r3, [r3, #0]
|
|
80043f2: 699b ldr r3, [r3, #24]
|
|
80043f4: f003 0301 and.w r3, r3, #1
|
|
80043f8: 2b01 cmp r3, #1
|
|
80043fa: d007 beq.n 800440c <I2C_Flush_TXDR+0x3c>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
|
|
80043fc: 687b ldr r3, [r7, #4]
|
|
80043fe: 681b ldr r3, [r3, #0]
|
|
8004400: 699a ldr r2, [r3, #24]
|
|
8004402: 687b ldr r3, [r7, #4]
|
|
8004404: 681b ldr r3, [r3, #0]
|
|
8004406: f042 0201 orr.w r2, r2, #1
|
|
800440a: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
800440c: bf00 nop
|
|
800440e: 370c adds r7, #12
|
|
8004410: 46bd mov sp, r7
|
|
8004412: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004416: 4770 bx lr
|
|
|
|
08004418 <I2C_WaitOnFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8004418: b580 push {r7, lr}
|
|
800441a: b084 sub sp, #16
|
|
800441c: af00 add r7, sp, #0
|
|
800441e: 60f8 str r0, [r7, #12]
|
|
8004420: 60b9 str r1, [r7, #8]
|
|
8004422: 603b str r3, [r7, #0]
|
|
8004424: 4613 mov r3, r2
|
|
8004426: 71fb strb r3, [r7, #7]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
8004428: e03b b.n 80044a2 <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
800442a: 69ba ldr r2, [r7, #24]
|
|
800442c: 6839 ldr r1, [r7, #0]
|
|
800442e: 68f8 ldr r0, [r7, #12]
|
|
8004430: f000 f8d6 bl 80045e0 <I2C_IsErrorOccurred>
|
|
8004434: 4603 mov r3, r0
|
|
8004436: 2b00 cmp r3, #0
|
|
8004438: d001 beq.n 800443e <I2C_WaitOnFlagUntilTimeout+0x26>
|
|
{
|
|
return HAL_ERROR;
|
|
800443a: 2301 movs r3, #1
|
|
800443c: e041 b.n 80044c2 <I2C_WaitOnFlagUntilTimeout+0xaa>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800443e: 683b ldr r3, [r7, #0]
|
|
8004440: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8004444: d02d beq.n 80044a2 <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8004446: f7fe fefb bl 8003240 <HAL_GetTick>
|
|
800444a: 4602 mov r2, r0
|
|
800444c: 69bb ldr r3, [r7, #24]
|
|
800444e: 1ad3 subs r3, r2, r3
|
|
8004450: 683a ldr r2, [r7, #0]
|
|
8004452: 429a cmp r2, r3
|
|
8004454: d302 bcc.n 800445c <I2C_WaitOnFlagUntilTimeout+0x44>
|
|
8004456: 683b ldr r3, [r7, #0]
|
|
8004458: 2b00 cmp r3, #0
|
|
800445a: d122 bne.n 80044a2 <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
|
|
800445c: 68fb ldr r3, [r7, #12]
|
|
800445e: 681b ldr r3, [r3, #0]
|
|
8004460: 699a ldr r2, [r3, #24]
|
|
8004462: 68bb ldr r3, [r7, #8]
|
|
8004464: 4013 ands r3, r2
|
|
8004466: 68ba ldr r2, [r7, #8]
|
|
8004468: 429a cmp r2, r3
|
|
800446a: bf0c ite eq
|
|
800446c: 2301 moveq r3, #1
|
|
800446e: 2300 movne r3, #0
|
|
8004470: b2db uxtb r3, r3
|
|
8004472: 461a mov r2, r3
|
|
8004474: 79fb ldrb r3, [r7, #7]
|
|
8004476: 429a cmp r2, r3
|
|
8004478: d113 bne.n 80044a2 <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
800447a: 68fb ldr r3, [r7, #12]
|
|
800447c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800447e: f043 0220 orr.w r2, r3, #32
|
|
8004482: 68fb ldr r3, [r7, #12]
|
|
8004484: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004486: 68fb ldr r3, [r7, #12]
|
|
8004488: 2220 movs r2, #32
|
|
800448a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800448e: 68fb ldr r3, [r7, #12]
|
|
8004490: 2200 movs r2, #0
|
|
8004492: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004496: 68fb ldr r3, [r7, #12]
|
|
8004498: 2200 movs r2, #0
|
|
800449a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
800449e: 2301 movs r3, #1
|
|
80044a0: e00f b.n 80044c2 <I2C_WaitOnFlagUntilTimeout+0xaa>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
80044a2: 68fb ldr r3, [r7, #12]
|
|
80044a4: 681b ldr r3, [r3, #0]
|
|
80044a6: 699a ldr r2, [r3, #24]
|
|
80044a8: 68bb ldr r3, [r7, #8]
|
|
80044aa: 4013 ands r3, r2
|
|
80044ac: 68ba ldr r2, [r7, #8]
|
|
80044ae: 429a cmp r2, r3
|
|
80044b0: bf0c ite eq
|
|
80044b2: 2301 moveq r3, #1
|
|
80044b4: 2300 movne r3, #0
|
|
80044b6: b2db uxtb r3, r3
|
|
80044b8: 461a mov r2, r3
|
|
80044ba: 79fb ldrb r3, [r7, #7]
|
|
80044bc: 429a cmp r2, r3
|
|
80044be: d0b4 beq.n 800442a <I2C_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80044c0: 2300 movs r3, #0
|
|
}
|
|
80044c2: 4618 mov r0, r3
|
|
80044c4: 3710 adds r7, #16
|
|
80044c6: 46bd mov sp, r7
|
|
80044c8: bd80 pop {r7, pc}
|
|
|
|
080044ca <I2C_WaitOnTXISFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
80044ca: b580 push {r7, lr}
|
|
80044cc: b084 sub sp, #16
|
|
80044ce: af00 add r7, sp, #0
|
|
80044d0: 60f8 str r0, [r7, #12]
|
|
80044d2: 60b9 str r1, [r7, #8]
|
|
80044d4: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
80044d6: e033 b.n 8004540 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80044d8: 687a ldr r2, [r7, #4]
|
|
80044da: 68b9 ldr r1, [r7, #8]
|
|
80044dc: 68f8 ldr r0, [r7, #12]
|
|
80044de: f000 f87f bl 80045e0 <I2C_IsErrorOccurred>
|
|
80044e2: 4603 mov r3, r0
|
|
80044e4: 2b00 cmp r3, #0
|
|
80044e6: d001 beq.n 80044ec <I2C_WaitOnTXISFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
80044e8: 2301 movs r3, #1
|
|
80044ea: e031 b.n 8004550 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80044ec: 68bb ldr r3, [r7, #8]
|
|
80044ee: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
80044f2: d025 beq.n 8004540 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80044f4: f7fe fea4 bl 8003240 <HAL_GetTick>
|
|
80044f8: 4602 mov r2, r0
|
|
80044fa: 687b ldr r3, [r7, #4]
|
|
80044fc: 1ad3 subs r3, r2, r3
|
|
80044fe: 68ba ldr r2, [r7, #8]
|
|
8004500: 429a cmp r2, r3
|
|
8004502: d302 bcc.n 800450a <I2C_WaitOnTXISFlagUntilTimeout+0x40>
|
|
8004504: 68bb ldr r3, [r7, #8]
|
|
8004506: 2b00 cmp r3, #0
|
|
8004508: d11a bne.n 8004540 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
|
|
800450a: 68fb ldr r3, [r7, #12]
|
|
800450c: 681b ldr r3, [r3, #0]
|
|
800450e: 699b ldr r3, [r3, #24]
|
|
8004510: f003 0302 and.w r3, r3, #2
|
|
8004514: 2b02 cmp r3, #2
|
|
8004516: d013 beq.n 8004540 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8004518: 68fb ldr r3, [r7, #12]
|
|
800451a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800451c: f043 0220 orr.w r2, r3, #32
|
|
8004520: 68fb ldr r3, [r7, #12]
|
|
8004522: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004524: 68fb ldr r3, [r7, #12]
|
|
8004526: 2220 movs r2, #32
|
|
8004528: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800452c: 68fb ldr r3, [r7, #12]
|
|
800452e: 2200 movs r2, #0
|
|
8004530: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004534: 68fb ldr r3, [r7, #12]
|
|
8004536: 2200 movs r2, #0
|
|
8004538: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
800453c: 2301 movs r3, #1
|
|
800453e: e007 b.n 8004550 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
8004540: 68fb ldr r3, [r7, #12]
|
|
8004542: 681b ldr r3, [r3, #0]
|
|
8004544: 699b ldr r3, [r3, #24]
|
|
8004546: f003 0302 and.w r3, r3, #2
|
|
800454a: 2b02 cmp r3, #2
|
|
800454c: d1c4 bne.n 80044d8 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800454e: 2300 movs r3, #0
|
|
}
|
|
8004550: 4618 mov r0, r3
|
|
8004552: 3710 adds r7, #16
|
|
8004554: 46bd mov sp, r7
|
|
8004556: bd80 pop {r7, pc}
|
|
|
|
08004558 <I2C_WaitOnSTOPFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8004558: b580 push {r7, lr}
|
|
800455a: b084 sub sp, #16
|
|
800455c: af00 add r7, sp, #0
|
|
800455e: 60f8 str r0, [r7, #12]
|
|
8004560: 60b9 str r1, [r7, #8]
|
|
8004562: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8004564: e02f b.n 80045c6 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8004566: 687a ldr r2, [r7, #4]
|
|
8004568: 68b9 ldr r1, [r7, #8]
|
|
800456a: 68f8 ldr r0, [r7, #12]
|
|
800456c: f000 f838 bl 80045e0 <I2C_IsErrorOccurred>
|
|
8004570: 4603 mov r3, r0
|
|
8004572: 2b00 cmp r3, #0
|
|
8004574: d001 beq.n 800457a <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
8004576: 2301 movs r3, #1
|
|
8004578: e02d b.n 80045d6 <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
800457a: f7fe fe61 bl 8003240 <HAL_GetTick>
|
|
800457e: 4602 mov r2, r0
|
|
8004580: 687b ldr r3, [r7, #4]
|
|
8004582: 1ad3 subs r3, r2, r3
|
|
8004584: 68ba ldr r2, [r7, #8]
|
|
8004586: 429a cmp r2, r3
|
|
8004588: d302 bcc.n 8004590 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
|
|
800458a: 68bb ldr r3, [r7, #8]
|
|
800458c: 2b00 cmp r3, #0
|
|
800458e: d11a bne.n 80045c6 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
|
|
8004590: 68fb ldr r3, [r7, #12]
|
|
8004592: 681b ldr r3, [r3, #0]
|
|
8004594: 699b ldr r3, [r3, #24]
|
|
8004596: f003 0320 and.w r3, r3, #32
|
|
800459a: 2b20 cmp r3, #32
|
|
800459c: d013 beq.n 80045c6 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
800459e: 68fb ldr r3, [r7, #12]
|
|
80045a0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80045a2: f043 0220 orr.w r2, r3, #32
|
|
80045a6: 68fb ldr r3, [r7, #12]
|
|
80045a8: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80045aa: 68fb ldr r3, [r7, #12]
|
|
80045ac: 2220 movs r2, #32
|
|
80045ae: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80045b2: 68fb ldr r3, [r7, #12]
|
|
80045b4: 2200 movs r2, #0
|
|
80045b6: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80045ba: 68fb ldr r3, [r7, #12]
|
|
80045bc: 2200 movs r2, #0
|
|
80045be: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
80045c2: 2301 movs r3, #1
|
|
80045c4: e007 b.n 80045d6 <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80045c6: 68fb ldr r3, [r7, #12]
|
|
80045c8: 681b ldr r3, [r3, #0]
|
|
80045ca: 699b ldr r3, [r3, #24]
|
|
80045cc: f003 0320 and.w r3, r3, #32
|
|
80045d0: 2b20 cmp r3, #32
|
|
80045d2: d1c8 bne.n 8004566 <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80045d4: 2300 movs r3, #0
|
|
}
|
|
80045d6: 4618 mov r0, r3
|
|
80045d8: 3710 adds r7, #16
|
|
80045da: 46bd mov sp, r7
|
|
80045dc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080045e0 <I2C_IsErrorOccurred>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80045e0: b580 push {r7, lr}
|
|
80045e2: b08a sub sp, #40 @ 0x28
|
|
80045e4: af00 add r7, sp, #0
|
|
80045e6: 60f8 str r0, [r7, #12]
|
|
80045e8: 60b9 str r1, [r7, #8]
|
|
80045ea: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80045ec: 2300 movs r3, #0
|
|
80045ee: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
uint32_t itflag = hi2c->Instance->ISR;
|
|
80045f2: 68fb ldr r3, [r7, #12]
|
|
80045f4: 681b ldr r3, [r3, #0]
|
|
80045f6: 699b ldr r3, [r3, #24]
|
|
80045f8: 61bb str r3, [r7, #24]
|
|
uint32_t error_code = 0;
|
|
80045fa: 2300 movs r3, #0
|
|
80045fc: 623b str r3, [r7, #32]
|
|
uint32_t tickstart = Tickstart;
|
|
80045fe: 687b ldr r3, [r7, #4]
|
|
8004600: 61fb str r3, [r7, #28]
|
|
uint32_t tmp1;
|
|
HAL_I2C_ModeTypeDef tmp2;
|
|
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
|
|
8004602: 69bb ldr r3, [r7, #24]
|
|
8004604: f003 0310 and.w r3, r3, #16
|
|
8004608: 2b00 cmp r3, #0
|
|
800460a: d068 beq.n 80046de <I2C_IsErrorOccurred+0xfe>
|
|
{
|
|
/* Clear NACKF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
800460c: 68fb ldr r3, [r7, #12]
|
|
800460e: 681b ldr r3, [r3, #0]
|
|
8004610: 2210 movs r2, #16
|
|
8004612: 61da str r2, [r3, #28]
|
|
|
|
/* Wait until STOP Flag is set or timeout occurred */
|
|
/* AutoEnd should be initiate after AF */
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
8004614: e049 b.n 80046aa <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8004616: 68bb ldr r3, [r7, #8]
|
|
8004618: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800461c: d045 beq.n 80046aa <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
|
800461e: f7fe fe0f bl 8003240 <HAL_GetTick>
|
|
8004622: 4602 mov r2, r0
|
|
8004624: 69fb ldr r3, [r7, #28]
|
|
8004626: 1ad3 subs r3, r2, r3
|
|
8004628: 68ba ldr r2, [r7, #8]
|
|
800462a: 429a cmp r2, r3
|
|
800462c: d302 bcc.n 8004634 <I2C_IsErrorOccurred+0x54>
|
|
800462e: 68bb ldr r3, [r7, #8]
|
|
8004630: 2b00 cmp r3, #0
|
|
8004632: d13a bne.n 80046aa <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
|
|
8004634: 68fb ldr r3, [r7, #12]
|
|
8004636: 681b ldr r3, [r3, #0]
|
|
8004638: 685b ldr r3, [r3, #4]
|
|
800463a: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800463e: 617b str r3, [r7, #20]
|
|
tmp2 = hi2c->Mode;
|
|
8004640: 68fb ldr r3, [r7, #12]
|
|
8004642: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8004646: 74fb strb r3, [r7, #19]
|
|
|
|
/* In case of I2C still busy, try to regenerate a STOP manually */
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
|
|
8004648: 68fb ldr r3, [r7, #12]
|
|
800464a: 681b ldr r3, [r3, #0]
|
|
800464c: 699b ldr r3, [r3, #24]
|
|
800464e: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8004652: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8004656: d121 bne.n 800469c <I2C_IsErrorOccurred+0xbc>
|
|
8004658: 697b ldr r3, [r7, #20]
|
|
800465a: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
800465e: d01d beq.n 800469c <I2C_IsErrorOccurred+0xbc>
|
|
(tmp1 != I2C_CR2_STOP) && \
|
|
8004660: 7cfb ldrb r3, [r7, #19]
|
|
8004662: 2b20 cmp r3, #32
|
|
8004664: d01a beq.n 800469c <I2C_IsErrorOccurred+0xbc>
|
|
(tmp2 != HAL_I2C_MODE_SLAVE))
|
|
{
|
|
/* Generate Stop */
|
|
hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
|
8004666: 68fb ldr r3, [r7, #12]
|
|
8004668: 681b ldr r3, [r3, #0]
|
|
800466a: 685a ldr r2, [r3, #4]
|
|
800466c: 68fb ldr r3, [r7, #12]
|
|
800466e: 681b ldr r3, [r3, #0]
|
|
8004670: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
8004674: 605a str r2, [r3, #4]
|
|
|
|
/* Update Tick with new reference */
|
|
tickstart = HAL_GetTick();
|
|
8004676: f7fe fde3 bl 8003240 <HAL_GetTick>
|
|
800467a: 61f8 str r0, [r7, #28]
|
|
}
|
|
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
800467c: e00e b.n 800469c <I2C_IsErrorOccurred+0xbc>
|
|
{
|
|
/* Check for the Timeout */
|
|
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
|
|
800467e: f7fe fddf bl 8003240 <HAL_GetTick>
|
|
8004682: 4602 mov r2, r0
|
|
8004684: 69fb ldr r3, [r7, #28]
|
|
8004686: 1ad3 subs r3, r2, r3
|
|
8004688: 2b19 cmp r3, #25
|
|
800468a: d907 bls.n 800469c <I2C_IsErrorOccurred+0xbc>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_TIMEOUT;
|
|
800468c: 6a3b ldr r3, [r7, #32]
|
|
800468e: f043 0320 orr.w r3, r3, #32
|
|
8004692: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
8004694: 2301 movs r3, #1
|
|
8004696: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
|
|
break;
|
|
800469a: e006 b.n 80046aa <I2C_IsErrorOccurred+0xca>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
800469c: 68fb ldr r3, [r7, #12]
|
|
800469e: 681b ldr r3, [r3, #0]
|
|
80046a0: 699b ldr r3, [r3, #24]
|
|
80046a2: f003 0320 and.w r3, r3, #32
|
|
80046a6: 2b20 cmp r3, #32
|
|
80046a8: d1e9 bne.n 800467e <I2C_IsErrorOccurred+0x9e>
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
80046aa: 68fb ldr r3, [r7, #12]
|
|
80046ac: 681b ldr r3, [r3, #0]
|
|
80046ae: 699b ldr r3, [r3, #24]
|
|
80046b0: f003 0320 and.w r3, r3, #32
|
|
80046b4: 2b20 cmp r3, #32
|
|
80046b6: d003 beq.n 80046c0 <I2C_IsErrorOccurred+0xe0>
|
|
80046b8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80046bc: 2b00 cmp r3, #0
|
|
80046be: d0aa beq.n 8004616 <I2C_IsErrorOccurred+0x36>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* In case STOP Flag is detected, clear it */
|
|
if (status == HAL_OK)
|
|
80046c0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80046c4: 2b00 cmp r3, #0
|
|
80046c6: d103 bne.n 80046d0 <I2C_IsErrorOccurred+0xf0>
|
|
{
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
80046c8: 68fb ldr r3, [r7, #12]
|
|
80046ca: 681b ldr r3, [r3, #0]
|
|
80046cc: 2220 movs r2, #32
|
|
80046ce: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
error_code |= HAL_I2C_ERROR_AF;
|
|
80046d0: 6a3b ldr r3, [r7, #32]
|
|
80046d2: f043 0304 orr.w r3, r3, #4
|
|
80046d6: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
80046d8: 2301 movs r3, #1
|
|
80046da: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Refresh Content of Status register */
|
|
itflag = hi2c->Instance->ISR;
|
|
80046de: 68fb ldr r3, [r7, #12]
|
|
80046e0: 681b ldr r3, [r3, #0]
|
|
80046e2: 699b ldr r3, [r3, #24]
|
|
80046e4: 61bb str r3, [r7, #24]
|
|
|
|
/* Then verify if an additional errors occurs */
|
|
/* Check if a Bus error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
|
|
80046e6: 69bb ldr r3, [r7, #24]
|
|
80046e8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80046ec: 2b00 cmp r3, #0
|
|
80046ee: d00b beq.n 8004708 <I2C_IsErrorOccurred+0x128>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_BERR;
|
|
80046f0: 6a3b ldr r3, [r7, #32]
|
|
80046f2: f043 0301 orr.w r3, r3, #1
|
|
80046f6: 623b str r3, [r7, #32]
|
|
|
|
/* Clear BERR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
|
|
80046f8: 68fb ldr r3, [r7, #12]
|
|
80046fa: 681b ldr r3, [r3, #0]
|
|
80046fc: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8004700: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
8004702: 2301 movs r3, #1
|
|
8004704: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Check if an Over-Run/Under-Run error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
|
|
8004708: 69bb ldr r3, [r7, #24]
|
|
800470a: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800470e: 2b00 cmp r3, #0
|
|
8004710: d00b beq.n 800472a <I2C_IsErrorOccurred+0x14a>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_OVR;
|
|
8004712: 6a3b ldr r3, [r7, #32]
|
|
8004714: f043 0308 orr.w r3, r3, #8
|
|
8004718: 623b str r3, [r7, #32]
|
|
|
|
/* Clear OVR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
|
|
800471a: 68fb ldr r3, [r7, #12]
|
|
800471c: 681b ldr r3, [r3, #0]
|
|
800471e: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8004722: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
8004724: 2301 movs r3, #1
|
|
8004726: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Check if an Arbitration Loss error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
|
|
800472a: 69bb ldr r3, [r7, #24]
|
|
800472c: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8004730: 2b00 cmp r3, #0
|
|
8004732: d00b beq.n 800474c <I2C_IsErrorOccurred+0x16c>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_ARLO;
|
|
8004734: 6a3b ldr r3, [r7, #32]
|
|
8004736: f043 0302 orr.w r3, r3, #2
|
|
800473a: 623b str r3, [r7, #32]
|
|
|
|
/* Clear ARLO flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
|
|
800473c: 68fb ldr r3, [r7, #12]
|
|
800473e: 681b ldr r3, [r3, #0]
|
|
8004740: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8004744: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
8004746: 2301 movs r3, #1
|
|
8004748: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
if (status != HAL_OK)
|
|
800474c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8004750: 2b00 cmp r3, #0
|
|
8004752: d01c beq.n 800478e <I2C_IsErrorOccurred+0x1ae>
|
|
{
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8004754: 68f8 ldr r0, [r7, #12]
|
|
8004756: f7ff fe3b bl 80043d0 <I2C_Flush_TXDR>
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
800475a: 68fb ldr r3, [r7, #12]
|
|
800475c: 681b ldr r3, [r3, #0]
|
|
800475e: 6859 ldr r1, [r3, #4]
|
|
8004760: 68fb ldr r3, [r7, #12]
|
|
8004762: 681a ldr r2, [r3, #0]
|
|
8004764: 4b0d ldr r3, [pc, #52] @ (800479c <I2C_IsErrorOccurred+0x1bc>)
|
|
8004766: 400b ands r3, r1
|
|
8004768: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->ErrorCode |= error_code;
|
|
800476a: 68fb ldr r3, [r7, #12]
|
|
800476c: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
800476e: 6a3b ldr r3, [r7, #32]
|
|
8004770: 431a orrs r2, r3
|
|
8004772: 68fb ldr r3, [r7, #12]
|
|
8004774: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004776: 68fb ldr r3, [r7, #12]
|
|
8004778: 2220 movs r2, #32
|
|
800477a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800477e: 68fb ldr r3, [r7, #12]
|
|
8004780: 2200 movs r2, #0
|
|
8004782: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004786: 68fb ldr r3, [r7, #12]
|
|
8004788: 2200 movs r2, #0
|
|
800478a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
}
|
|
|
|
return status;
|
|
800478e: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
8004792: 4618 mov r0, r3
|
|
8004794: 3728 adds r7, #40 @ 0x28
|
|
8004796: 46bd mov sp, r7
|
|
8004798: bd80 pop {r7, pc}
|
|
800479a: bf00 nop
|
|
800479c: fe00e800 .word 0xfe00e800
|
|
|
|
080047a0 <I2C_TransferConfig>:
|
|
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
|
uint32_t Request)
|
|
{
|
|
80047a0: b480 push {r7}
|
|
80047a2: b087 sub sp, #28
|
|
80047a4: af00 add r7, sp, #0
|
|
80047a6: 60f8 str r0, [r7, #12]
|
|
80047a8: 607b str r3, [r7, #4]
|
|
80047aa: 460b mov r3, r1
|
|
80047ac: 817b strh r3, [r7, #10]
|
|
80047ae: 4613 mov r3, r2
|
|
80047b0: 727b strb r3, [r7, #9]
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_TRANSFER_MODE(Mode));
|
|
assert_param(IS_TRANSFER_REQUEST(Request));
|
|
|
|
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
80047b2: 897b ldrh r3, [r7, #10]
|
|
80047b4: f3c3 0209 ubfx r2, r3, #0, #10
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
80047b8: 7a7b ldrb r3, [r7, #9]
|
|
80047ba: 041b lsls r3, r3, #16
|
|
80047bc: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
80047c0: 431a orrs r2, r3
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
80047c2: 687b ldr r3, [r7, #4]
|
|
80047c4: 431a orrs r2, r3
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
80047c6: 6a3b ldr r3, [r7, #32]
|
|
80047c8: 4313 orrs r3, r2
|
|
80047ca: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
80047ce: 617b str r3, [r7, #20]
|
|
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
|
|
|
|
/* update CR2 register */
|
|
MODIFY_REG(hi2c->Instance->CR2, \
|
|
80047d0: 68fb ldr r3, [r7, #12]
|
|
80047d2: 681b ldr r3, [r3, #0]
|
|
80047d4: 685a ldr r2, [r3, #4]
|
|
80047d6: 6a3b ldr r3, [r7, #32]
|
|
80047d8: 0d5b lsrs r3, r3, #21
|
|
80047da: f403 6180 and.w r1, r3, #1024 @ 0x400
|
|
80047de: 4b08 ldr r3, [pc, #32] @ (8004800 <I2C_TransferConfig+0x60>)
|
|
80047e0: 430b orrs r3, r1
|
|
80047e2: 43db mvns r3, r3
|
|
80047e4: ea02 0103 and.w r1, r2, r3
|
|
80047e8: 68fb ldr r3, [r7, #12]
|
|
80047ea: 681b ldr r3, [r3, #0]
|
|
80047ec: 697a ldr r2, [r7, #20]
|
|
80047ee: 430a orrs r2, r1
|
|
80047f0: 605a str r2, [r3, #4]
|
|
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
|
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
|
|
I2C_CR2_START | I2C_CR2_STOP)), tmp);
|
|
}
|
|
80047f2: bf00 nop
|
|
80047f4: 371c adds r7, #28
|
|
80047f6: 46bd mov sp, r7
|
|
80047f8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80047fc: 4770 bx lr
|
|
80047fe: bf00 nop
|
|
8004800: 03ff63ff .word 0x03ff63ff
|
|
|
|
08004804 <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter New state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8004804: b480 push {r7}
|
|
8004806: b083 sub sp, #12
|
|
8004808: af00 add r7, sp, #0
|
|
800480a: 6078 str r0, [r7, #4]
|
|
800480c: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
800480e: 687b ldr r3, [r7, #4]
|
|
8004810: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004814: b2db uxtb r3, r3
|
|
8004816: 2b20 cmp r3, #32
|
|
8004818: d138 bne.n 800488c <HAL_I2CEx_ConfigAnalogFilter+0x88>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
800481a: 687b ldr r3, [r7, #4]
|
|
800481c: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8004820: 2b01 cmp r3, #1
|
|
8004822: d101 bne.n 8004828 <HAL_I2CEx_ConfigAnalogFilter+0x24>
|
|
8004824: 2302 movs r3, #2
|
|
8004826: e032 b.n 800488e <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
8004828: 687b ldr r3, [r7, #4]
|
|
800482a: 2201 movs r2, #1
|
|
800482c: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8004830: 687b ldr r3, [r7, #4]
|
|
8004832: 2224 movs r2, #36 @ 0x24
|
|
8004834: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8004838: 687b ldr r3, [r7, #4]
|
|
800483a: 681b ldr r3, [r3, #0]
|
|
800483c: 681a ldr r2, [r3, #0]
|
|
800483e: 687b ldr r3, [r7, #4]
|
|
8004840: 681b ldr r3, [r3, #0]
|
|
8004842: f022 0201 bic.w r2, r2, #1
|
|
8004846: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
|
8004848: 687b ldr r3, [r7, #4]
|
|
800484a: 681b ldr r3, [r3, #0]
|
|
800484c: 681a ldr r2, [r3, #0]
|
|
800484e: 687b ldr r3, [r7, #4]
|
|
8004850: 681b ldr r3, [r3, #0]
|
|
8004852: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
8004856: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog filter bit*/
|
|
hi2c->Instance->CR1 |= AnalogFilter;
|
|
8004858: 687b ldr r3, [r7, #4]
|
|
800485a: 681b ldr r3, [r3, #0]
|
|
800485c: 6819 ldr r1, [r3, #0]
|
|
800485e: 687b ldr r3, [r7, #4]
|
|
8004860: 681b ldr r3, [r3, #0]
|
|
8004862: 683a ldr r2, [r7, #0]
|
|
8004864: 430a orrs r2, r1
|
|
8004866: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8004868: 687b ldr r3, [r7, #4]
|
|
800486a: 681b ldr r3, [r3, #0]
|
|
800486c: 681a ldr r2, [r3, #0]
|
|
800486e: 687b ldr r3, [r7, #4]
|
|
8004870: 681b ldr r3, [r3, #0]
|
|
8004872: f042 0201 orr.w r2, r2, #1
|
|
8004876: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004878: 687b ldr r3, [r7, #4]
|
|
800487a: 2220 movs r2, #32
|
|
800487c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004880: 687b ldr r3, [r7, #4]
|
|
8004882: 2200 movs r2, #0
|
|
8004884: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8004888: 2300 movs r3, #0
|
|
800488a: e000 b.n 800488e <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800488c: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800488e: 4618 mov r0, r3
|
|
8004890: 370c adds r7, #12
|
|
8004892: 46bd mov sp, r7
|
|
8004894: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004898: 4770 bx lr
|
|
|
|
0800489a <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
800489a: b480 push {r7}
|
|
800489c: b085 sub sp, #20
|
|
800489e: af00 add r7, sp, #0
|
|
80048a0: 6078 str r0, [r7, #4]
|
|
80048a2: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
80048a4: 687b ldr r3, [r7, #4]
|
|
80048a6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80048aa: b2db uxtb r3, r3
|
|
80048ac: 2b20 cmp r3, #32
|
|
80048ae: d139 bne.n 8004924 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80048b0: 687b ldr r3, [r7, #4]
|
|
80048b2: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
80048b6: 2b01 cmp r3, #1
|
|
80048b8: d101 bne.n 80048be <HAL_I2CEx_ConfigDigitalFilter+0x24>
|
|
80048ba: 2302 movs r3, #2
|
|
80048bc: e033 b.n 8004926 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
80048be: 687b ldr r3, [r7, #4]
|
|
80048c0: 2201 movs r2, #1
|
|
80048c2: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80048c6: 687b ldr r3, [r7, #4]
|
|
80048c8: 2224 movs r2, #36 @ 0x24
|
|
80048ca: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80048ce: 687b ldr r3, [r7, #4]
|
|
80048d0: 681b ldr r3, [r3, #0]
|
|
80048d2: 681a ldr r2, [r3, #0]
|
|
80048d4: 687b ldr r3, [r7, #4]
|
|
80048d6: 681b ldr r3, [r3, #0]
|
|
80048d8: f022 0201 bic.w r2, r2, #1
|
|
80048dc: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->CR1;
|
|
80048de: 687b ldr r3, [r7, #4]
|
|
80048e0: 681b ldr r3, [r3, #0]
|
|
80048e2: 681b ldr r3, [r3, #0]
|
|
80048e4: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2Cx DNF bits [11:8] */
|
|
tmpreg &= ~(I2C_CR1_DNF);
|
|
80048e6: 68fb ldr r3, [r7, #12]
|
|
80048e8: f423 6370 bic.w r3, r3, #3840 @ 0xf00
|
|
80048ec: 60fb str r3, [r7, #12]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter << 8U;
|
|
80048ee: 683b ldr r3, [r7, #0]
|
|
80048f0: 021b lsls r3, r3, #8
|
|
80048f2: 68fa ldr r2, [r7, #12]
|
|
80048f4: 4313 orrs r3, r2
|
|
80048f6: 60fb str r3, [r7, #12]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->CR1 = tmpreg;
|
|
80048f8: 687b ldr r3, [r7, #4]
|
|
80048fa: 681b ldr r3, [r3, #0]
|
|
80048fc: 68fa ldr r2, [r7, #12]
|
|
80048fe: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8004900: 687b ldr r3, [r7, #4]
|
|
8004902: 681b ldr r3, [r3, #0]
|
|
8004904: 681a ldr r2, [r3, #0]
|
|
8004906: 687b ldr r3, [r7, #4]
|
|
8004908: 681b ldr r3, [r3, #0]
|
|
800490a: f042 0201 orr.w r2, r2, #1
|
|
800490e: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004910: 687b ldr r3, [r7, #4]
|
|
8004912: 2220 movs r2, #32
|
|
8004914: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8004918: 687b ldr r3, [r7, #4]
|
|
800491a: 2200 movs r2, #0
|
|
800491c: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8004920: 2300 movs r3, #0
|
|
8004922: e000 b.n 8004926 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004924: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004926: 4618 mov r0, r3
|
|
8004928: 3714 adds r7, #20
|
|
800492a: 46bd mov sp, r7
|
|
800492c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004930: 4770 bx lr
|
|
|
|
08004932 <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8004932: b580 push {r7, lr}
|
|
8004934: b086 sub sp, #24
|
|
8004936: af02 add r7, sp, #8
|
|
8004938: 6078 str r0, [r7, #4]
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
800493a: 687b ldr r3, [r7, #4]
|
|
800493c: 2b00 cmp r3, #0
|
|
800493e: d101 bne.n 8004944 <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004940: 2301 movs r3, #1
|
|
8004942: e101 b.n 8004b48 <HAL_PCD_Init+0x216>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
8004944: 687b ldr r3, [r7, #4]
|
|
8004946: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
|
|
800494a: b2db uxtb r3, r3
|
|
800494c: 2b00 cmp r3, #0
|
|
800494e: d106 bne.n 800495e <HAL_PCD_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
8004950: 687b ldr r3, [r7, #4]
|
|
8004952: 2200 movs r2, #0
|
|
8004954: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
8004958: 6878 ldr r0, [r7, #4]
|
|
800495a: f7fe f9f9 bl 8002d50 <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
800495e: 687b ldr r3, [r7, #4]
|
|
8004960: 2203 movs r2, #3
|
|
8004962: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
/* Disable DMA mode for FS instance */
|
|
hpcd->Init.dma_enable = 0U;
|
|
8004966: 687b ldr r3, [r7, #4]
|
|
8004968: 2200 movs r2, #0
|
|
800496a: 719a strb r2, [r3, #6]
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
800496c: 687b ldr r3, [r7, #4]
|
|
800496e: 681b ldr r3, [r3, #0]
|
|
8004970: 4618 mov r0, r3
|
|
8004972: f002 fb97 bl 80070a4 <USB_DisableGlobalInt>
|
|
|
|
/*Init the Core (common init.) */
|
|
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8004976: 687b ldr r3, [r7, #4]
|
|
8004978: 6818 ldr r0, [r3, #0]
|
|
800497a: 687b ldr r3, [r7, #4]
|
|
800497c: 7c1a ldrb r2, [r3, #16]
|
|
800497e: f88d 2000 strb.w r2, [sp]
|
|
8004982: 3304 adds r3, #4
|
|
8004984: cb0e ldmia r3, {r1, r2, r3}
|
|
8004986: f002 fb60 bl 800704a <USB_CoreInit>
|
|
800498a: 4603 mov r3, r0
|
|
800498c: 2b00 cmp r3, #0
|
|
800498e: d005 beq.n 800499c <HAL_PCD_Init+0x6a>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8004990: 687b ldr r3, [r7, #4]
|
|
8004992: 2202 movs r2, #2
|
|
8004994: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8004998: 2301 movs r3, #1
|
|
800499a: e0d5 b.n 8004b48 <HAL_PCD_Init+0x216>
|
|
}
|
|
|
|
/* Force Device Mode */
|
|
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
|
|
800499c: 687b ldr r3, [r7, #4]
|
|
800499e: 681b ldr r3, [r3, #0]
|
|
80049a0: 2100 movs r1, #0
|
|
80049a2: 4618 mov r0, r3
|
|
80049a4: f002 fb8f bl 80070c6 <USB_SetCurrentMode>
|
|
80049a8: 4603 mov r3, r0
|
|
80049aa: 2b00 cmp r3, #0
|
|
80049ac: d005 beq.n 80049ba <HAL_PCD_Init+0x88>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
80049ae: 687b ldr r3, [r7, #4]
|
|
80049b0: 2202 movs r2, #2
|
|
80049b2: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
80049b6: 2301 movs r3, #1
|
|
80049b8: e0c6 b.n 8004b48 <HAL_PCD_Init+0x216>
|
|
}
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80049ba: 2300 movs r3, #0
|
|
80049bc: 73fb strb r3, [r7, #15]
|
|
80049be: e04a b.n 8004a56 <HAL_PCD_Init+0x124>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
80049c0: 7bfa ldrb r2, [r7, #15]
|
|
80049c2: 6879 ldr r1, [r7, #4]
|
|
80049c4: 4613 mov r3, r2
|
|
80049c6: 00db lsls r3, r3, #3
|
|
80049c8: 4413 add r3, r2
|
|
80049ca: 009b lsls r3, r3, #2
|
|
80049cc: 440b add r3, r1
|
|
80049ce: 3315 adds r3, #21
|
|
80049d0: 2201 movs r2, #1
|
|
80049d2: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
80049d4: 7bfa ldrb r2, [r7, #15]
|
|
80049d6: 6879 ldr r1, [r7, #4]
|
|
80049d8: 4613 mov r3, r2
|
|
80049da: 00db lsls r3, r3, #3
|
|
80049dc: 4413 add r3, r2
|
|
80049de: 009b lsls r3, r3, #2
|
|
80049e0: 440b add r3, r1
|
|
80049e2: 3314 adds r3, #20
|
|
80049e4: 7bfa ldrb r2, [r7, #15]
|
|
80049e6: 701a strb r2, [r3, #0]
|
|
#if defined (USB_OTG_FS)
|
|
hpcd->IN_ep[i].tx_fifo_num = i;
|
|
80049e8: 7bfa ldrb r2, [r7, #15]
|
|
80049ea: 7bfb ldrb r3, [r7, #15]
|
|
80049ec: b298 uxth r0, r3
|
|
80049ee: 6879 ldr r1, [r7, #4]
|
|
80049f0: 4613 mov r3, r2
|
|
80049f2: 00db lsls r3, r3, #3
|
|
80049f4: 4413 add r3, r2
|
|
80049f6: 009b lsls r3, r3, #2
|
|
80049f8: 440b add r3, r1
|
|
80049fa: 332e adds r3, #46 @ 0x2e
|
|
80049fc: 4602 mov r2, r0
|
|
80049fe: 801a strh r2, [r3, #0]
|
|
#endif /* defined (USB_OTG_FS) */
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8004a00: 7bfa ldrb r2, [r7, #15]
|
|
8004a02: 6879 ldr r1, [r7, #4]
|
|
8004a04: 4613 mov r3, r2
|
|
8004a06: 00db lsls r3, r3, #3
|
|
8004a08: 4413 add r3, r2
|
|
8004a0a: 009b lsls r3, r3, #2
|
|
8004a0c: 440b add r3, r1
|
|
8004a0e: 3318 adds r3, #24
|
|
8004a10: 2200 movs r2, #0
|
|
8004a12: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
8004a14: 7bfa ldrb r2, [r7, #15]
|
|
8004a16: 6879 ldr r1, [r7, #4]
|
|
8004a18: 4613 mov r3, r2
|
|
8004a1a: 00db lsls r3, r3, #3
|
|
8004a1c: 4413 add r3, r2
|
|
8004a1e: 009b lsls r3, r3, #2
|
|
8004a20: 440b add r3, r1
|
|
8004a22: 331c adds r3, #28
|
|
8004a24: 2200 movs r2, #0
|
|
8004a26: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
8004a28: 7bfa ldrb r2, [r7, #15]
|
|
8004a2a: 6879 ldr r1, [r7, #4]
|
|
8004a2c: 4613 mov r3, r2
|
|
8004a2e: 00db lsls r3, r3, #3
|
|
8004a30: 4413 add r3, r2
|
|
8004a32: 009b lsls r3, r3, #2
|
|
8004a34: 440b add r3, r1
|
|
8004a36: 3320 adds r3, #32
|
|
8004a38: 2200 movs r2, #0
|
|
8004a3a: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
8004a3c: 7bfa ldrb r2, [r7, #15]
|
|
8004a3e: 6879 ldr r1, [r7, #4]
|
|
8004a40: 4613 mov r3, r2
|
|
8004a42: 00db lsls r3, r3, #3
|
|
8004a44: 4413 add r3, r2
|
|
8004a46: 009b lsls r3, r3, #2
|
|
8004a48: 440b add r3, r1
|
|
8004a4a: 3324 adds r3, #36 @ 0x24
|
|
8004a4c: 2200 movs r2, #0
|
|
8004a4e: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8004a50: 7bfb ldrb r3, [r7, #15]
|
|
8004a52: 3301 adds r3, #1
|
|
8004a54: 73fb strb r3, [r7, #15]
|
|
8004a56: 687b ldr r3, [r7, #4]
|
|
8004a58: 791b ldrb r3, [r3, #4]
|
|
8004a5a: 7bfa ldrb r2, [r7, #15]
|
|
8004a5c: 429a cmp r2, r3
|
|
8004a5e: d3af bcc.n 80049c0 <HAL_PCD_Init+0x8e>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8004a60: 2300 movs r3, #0
|
|
8004a62: 73fb strb r3, [r7, #15]
|
|
8004a64: e044 b.n 8004af0 <HAL_PCD_Init+0x1be>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
8004a66: 7bfa ldrb r2, [r7, #15]
|
|
8004a68: 6879 ldr r1, [r7, #4]
|
|
8004a6a: 4613 mov r3, r2
|
|
8004a6c: 00db lsls r3, r3, #3
|
|
8004a6e: 4413 add r3, r2
|
|
8004a70: 009b lsls r3, r3, #2
|
|
8004a72: 440b add r3, r1
|
|
8004a74: f203 2355 addw r3, r3, #597 @ 0x255
|
|
8004a78: 2200 movs r2, #0
|
|
8004a7a: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
8004a7c: 7bfa ldrb r2, [r7, #15]
|
|
8004a7e: 6879 ldr r1, [r7, #4]
|
|
8004a80: 4613 mov r3, r2
|
|
8004a82: 00db lsls r3, r3, #3
|
|
8004a84: 4413 add r3, r2
|
|
8004a86: 009b lsls r3, r3, #2
|
|
8004a88: 440b add r3, r1
|
|
8004a8a: f503 7315 add.w r3, r3, #596 @ 0x254
|
|
8004a8e: 7bfa ldrb r2, [r7, #15]
|
|
8004a90: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
8004a92: 7bfa ldrb r2, [r7, #15]
|
|
8004a94: 6879 ldr r1, [r7, #4]
|
|
8004a96: 4613 mov r3, r2
|
|
8004a98: 00db lsls r3, r3, #3
|
|
8004a9a: 4413 add r3, r2
|
|
8004a9c: 009b lsls r3, r3, #2
|
|
8004a9e: 440b add r3, r1
|
|
8004aa0: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
8004aa4: 2200 movs r2, #0
|
|
8004aa6: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
8004aa8: 7bfa ldrb r2, [r7, #15]
|
|
8004aaa: 6879 ldr r1, [r7, #4]
|
|
8004aac: 4613 mov r3, r2
|
|
8004aae: 00db lsls r3, r3, #3
|
|
8004ab0: 4413 add r3, r2
|
|
8004ab2: 009b lsls r3, r3, #2
|
|
8004ab4: 440b add r3, r1
|
|
8004ab6: f503 7317 add.w r3, r3, #604 @ 0x25c
|
|
8004aba: 2200 movs r2, #0
|
|
8004abc: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
8004abe: 7bfa ldrb r2, [r7, #15]
|
|
8004ac0: 6879 ldr r1, [r7, #4]
|
|
8004ac2: 4613 mov r3, r2
|
|
8004ac4: 00db lsls r3, r3, #3
|
|
8004ac6: 4413 add r3, r2
|
|
8004ac8: 009b lsls r3, r3, #2
|
|
8004aca: 440b add r3, r1
|
|
8004acc: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
8004ad0: 2200 movs r2, #0
|
|
8004ad2: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
8004ad4: 7bfa ldrb r2, [r7, #15]
|
|
8004ad6: 6879 ldr r1, [r7, #4]
|
|
8004ad8: 4613 mov r3, r2
|
|
8004ada: 00db lsls r3, r3, #3
|
|
8004adc: 4413 add r3, r2
|
|
8004ade: 009b lsls r3, r3, #2
|
|
8004ae0: 440b add r3, r1
|
|
8004ae2: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
8004ae6: 2200 movs r2, #0
|
|
8004ae8: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8004aea: 7bfb ldrb r3, [r7, #15]
|
|
8004aec: 3301 adds r3, #1
|
|
8004aee: 73fb strb r3, [r7, #15]
|
|
8004af0: 687b ldr r3, [r7, #4]
|
|
8004af2: 791b ldrb r3, [r3, #4]
|
|
8004af4: 7bfa ldrb r2, [r7, #15]
|
|
8004af6: 429a cmp r2, r3
|
|
8004af8: d3b5 bcc.n 8004a66 <HAL_PCD_Init+0x134>
|
|
}
|
|
|
|
/* Init Device */
|
|
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8004afa: 687b ldr r3, [r7, #4]
|
|
8004afc: 6818 ldr r0, [r3, #0]
|
|
8004afe: 687b ldr r3, [r7, #4]
|
|
8004b00: 7c1a ldrb r2, [r3, #16]
|
|
8004b02: f88d 2000 strb.w r2, [sp]
|
|
8004b06: 3304 adds r3, #4
|
|
8004b08: cb0e ldmia r3, {r1, r2, r3}
|
|
8004b0a: f002 fb29 bl 8007160 <USB_DevInit>
|
|
8004b0e: 4603 mov r3, r0
|
|
8004b10: 2b00 cmp r3, #0
|
|
8004b12: d005 beq.n 8004b20 <HAL_PCD_Init+0x1ee>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8004b14: 687b ldr r3, [r7, #4]
|
|
8004b16: 2202 movs r2, #2
|
|
8004b18: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8004b1c: 2301 movs r3, #1
|
|
8004b1e: e013 b.n 8004b48 <HAL_PCD_Init+0x216>
|
|
}
|
|
|
|
hpcd->USB_Address = 0U;
|
|
8004b20: 687b ldr r3, [r7, #4]
|
|
8004b22: 2200 movs r2, #0
|
|
8004b24: 745a strb r2, [r3, #17]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
8004b26: 687b ldr r3, [r7, #4]
|
|
8004b28: 2201 movs r2, #1
|
|
8004b2a: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
/* Activate LPM */
|
|
if (hpcd->Init.lpm_enable == 1U)
|
|
8004b2e: 687b ldr r3, [r7, #4]
|
|
8004b30: 7b1b ldrb r3, [r3, #12]
|
|
8004b32: 2b01 cmp r3, #1
|
|
8004b34: d102 bne.n 8004b3c <HAL_PCD_Init+0x20a>
|
|
{
|
|
(void)HAL_PCDEx_ActivateLPM(hpcd);
|
|
8004b36: 6878 ldr r0, [r7, #4]
|
|
8004b38: f000 f80a bl 8004b50 <HAL_PCDEx_ActivateLPM>
|
|
}
|
|
|
|
(void)USB_DevDisconnect(hpcd->Instance);
|
|
8004b3c: 687b ldr r3, [r7, #4]
|
|
8004b3e: 681b ldr r3, [r3, #0]
|
|
8004b40: 4618 mov r0, r3
|
|
8004b42: f002 fcce bl 80074e2 <USB_DevDisconnect>
|
|
|
|
return HAL_OK;
|
|
8004b46: 2300 movs r3, #0
|
|
}
|
|
8004b48: 4618 mov r0, r3
|
|
8004b4a: 3710 adds r7, #16
|
|
8004b4c: 46bd mov sp, r7
|
|
8004b4e: bd80 pop {r7, pc}
|
|
|
|
08004b50 <HAL_PCDEx_ActivateLPM>:
|
|
* @brief Activate LPM feature.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8004b50: b480 push {r7}
|
|
8004b52: b085 sub sp, #20
|
|
8004b54: af00 add r7, sp, #0
|
|
8004b56: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8004b58: 687b ldr r3, [r7, #4]
|
|
8004b5a: 681b ldr r3, [r3, #0]
|
|
8004b5c: 60fb str r3, [r7, #12]
|
|
|
|
hpcd->lpm_active = 1U;
|
|
8004b5e: 687b ldr r3, [r7, #4]
|
|
8004b60: 2201 movs r2, #1
|
|
8004b62: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
|
|
hpcd->LPM_State = LPM_L0;
|
|
8004b66: 687b ldr r3, [r7, #4]
|
|
8004b68: 2200 movs r2, #0
|
|
8004b6a: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
|
8004b6e: 68fb ldr r3, [r7, #12]
|
|
8004b70: 699b ldr r3, [r3, #24]
|
|
8004b72: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
|
|
8004b76: 68fb ldr r3, [r7, #12]
|
|
8004b78: 619a str r2, [r3, #24]
|
|
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
|
8004b7a: 68fb ldr r3, [r7, #12]
|
|
8004b7c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8004b7e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8004b82: f043 0303 orr.w r3, r3, #3
|
|
8004b86: 68fa ldr r2, [r7, #12]
|
|
8004b88: 6553 str r3, [r2, #84] @ 0x54
|
|
|
|
return HAL_OK;
|
|
8004b8a: 2300 movs r3, #0
|
|
}
|
|
8004b8c: 4618 mov r0, r3
|
|
8004b8e: 3714 adds r7, #20
|
|
8004b90: 46bd mov sp, r7
|
|
8004b92: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b96: 4770 bx lr
|
|
|
|
08004b98 <HAL_PWR_EnableBkUpAccess>:
|
|
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
|
|
* back-up domain.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_EnableBkUpAccess(void)
|
|
{
|
|
8004b98: b480 push {r7}
|
|
8004b9a: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8004b9c: 4b05 ldr r3, [pc, #20] @ (8004bb4 <HAL_PWR_EnableBkUpAccess+0x1c>)
|
|
8004b9e: 681b ldr r3, [r3, #0]
|
|
8004ba0: 4a04 ldr r2, [pc, #16] @ (8004bb4 <HAL_PWR_EnableBkUpAccess+0x1c>)
|
|
8004ba2: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004ba6: 6013 str r3, [r2, #0]
|
|
}
|
|
8004ba8: bf00 nop
|
|
8004baa: 46bd mov sp, r7
|
|
8004bac: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004bb0: 4770 bx lr
|
|
8004bb2: bf00 nop
|
|
8004bb4: 40007000 .word 0x40007000
|
|
|
|
08004bb8 <HAL_PWREx_GetVoltageRange>:
|
|
* @brief Return Voltage Scaling Range.
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
|
|
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
|
|
*/
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
|
{
|
|
8004bb8: b480 push {r7}
|
|
8004bba: af00 add r7, sp, #0
|
|
else
|
|
{
|
|
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
|
|
}
|
|
#else
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
|
8004bbc: 4b04 ldr r3, [pc, #16] @ (8004bd0 <HAL_PWREx_GetVoltageRange+0x18>)
|
|
8004bbe: 681b ldr r3, [r3, #0]
|
|
8004bc0: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
#endif
|
|
}
|
|
8004bc4: 4618 mov r0, r3
|
|
8004bc6: 46bd mov sp, r7
|
|
8004bc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004bcc: 4770 bx lr
|
|
8004bce: bf00 nop
|
|
8004bd0: 40007000 .word 0x40007000
|
|
|
|
08004bd4 <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
8004bd4: b480 push {r7}
|
|
8004bd6: b085 sub sp, #20
|
|
8004bd8: af00 add r7, sp, #0
|
|
8004bda: 6078 str r0, [r7, #4]
|
|
}
|
|
|
|
#else
|
|
|
|
/* If Set Range 1 */
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8004bdc: 687b ldr r3, [r7, #4]
|
|
8004bde: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8004be2: d130 bne.n 8004c46 <HAL_PWREx_ControlVoltageScaling+0x72>
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8004be4: 4b23 ldr r3, [pc, #140] @ (8004c74 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8004be6: 681b ldr r3, [r3, #0]
|
|
8004be8: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8004bec: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8004bf0: d038 beq.n 8004c64 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8004bf2: 4b20 ldr r3, [pc, #128] @ (8004c74 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8004bf4: 681b ldr r3, [r3, #0]
|
|
8004bf6: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8004bfa: 4a1e ldr r2, [pc, #120] @ (8004c74 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8004bfc: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8004c00: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
8004c02: 4b1d ldr r3, [pc, #116] @ (8004c78 <HAL_PWREx_ControlVoltageScaling+0xa4>)
|
|
8004c04: 681b ldr r3, [r3, #0]
|
|
8004c06: 2232 movs r2, #50 @ 0x32
|
|
8004c08: fb02 f303 mul.w r3, r2, r3
|
|
8004c0c: 4a1b ldr r2, [pc, #108] @ (8004c7c <HAL_PWREx_ControlVoltageScaling+0xa8>)
|
|
8004c0e: fba2 2303 umull r2, r3, r2, r3
|
|
8004c12: 0c9b lsrs r3, r3, #18
|
|
8004c14: 3301 adds r3, #1
|
|
8004c16: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8004c18: e002 b.n 8004c20 <HAL_PWREx_ControlVoltageScaling+0x4c>
|
|
{
|
|
wait_loop_index--;
|
|
8004c1a: 68fb ldr r3, [r7, #12]
|
|
8004c1c: 3b01 subs r3, #1
|
|
8004c1e: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8004c20: 4b14 ldr r3, [pc, #80] @ (8004c74 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8004c22: 695b ldr r3, [r3, #20]
|
|
8004c24: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8004c28: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8004c2c: d102 bne.n 8004c34 <HAL_PWREx_ControlVoltageScaling+0x60>
|
|
8004c2e: 68fb ldr r3, [r7, #12]
|
|
8004c30: 2b00 cmp r3, #0
|
|
8004c32: d1f2 bne.n 8004c1a <HAL_PWREx_ControlVoltageScaling+0x46>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
8004c34: 4b0f ldr r3, [pc, #60] @ (8004c74 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8004c36: 695b ldr r3, [r3, #20]
|
|
8004c38: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8004c3c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8004c40: d110 bne.n 8004c64 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004c42: 2303 movs r3, #3
|
|
8004c44: e00f b.n 8004c66 <HAL_PWREx_ControlVoltageScaling+0x92>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
8004c46: 4b0b ldr r3, [pc, #44] @ (8004c74 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8004c48: 681b ldr r3, [r3, #0]
|
|
8004c4a: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8004c4e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8004c52: d007 beq.n 8004c64 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
/* Set Range 2 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
|
8004c54: 4b07 ldr r3, [pc, #28] @ (8004c74 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8004c56: 681b ldr r3, [r3, #0]
|
|
8004c58: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8004c5c: 4a05 ldr r2, [pc, #20] @ (8004c74 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8004c5e: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8004c62: 6013 str r3, [r2, #0]
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return HAL_OK;
|
|
8004c64: 2300 movs r3, #0
|
|
}
|
|
8004c66: 4618 mov r0, r3
|
|
8004c68: 3714 adds r7, #20
|
|
8004c6a: 46bd mov sp, r7
|
|
8004c6c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004c70: 4770 bx lr
|
|
8004c72: bf00 nop
|
|
8004c74: 40007000 .word 0x40007000
|
|
8004c78: 200000c4 .word 0x200000c4
|
|
8004c7c: 431bde83 .word 0x431bde83
|
|
|
|
08004c80 <HAL_PWREx_EnableVddUSB>:
|
|
* @brief Enable VDDUSB supply.
|
|
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_EnableVddUSB(void)
|
|
{
|
|
8004c80: b480 push {r7}
|
|
8004c82: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR2, PWR_CR2_USV);
|
|
8004c84: 4b05 ldr r3, [pc, #20] @ (8004c9c <HAL_PWREx_EnableVddUSB+0x1c>)
|
|
8004c86: 685b ldr r3, [r3, #4]
|
|
8004c88: 4a04 ldr r2, [pc, #16] @ (8004c9c <HAL_PWREx_EnableVddUSB+0x1c>)
|
|
8004c8a: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8004c8e: 6053 str r3, [r2, #4]
|
|
}
|
|
8004c90: bf00 nop
|
|
8004c92: 46bd mov sp, r7
|
|
8004c94: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004c98: 4770 bx lr
|
|
8004c9a: bf00 nop
|
|
8004c9c: 40007000 .word 0x40007000
|
|
|
|
08004ca0 <HAL_QSPI_Init>:
|
|
* in the QSPI_InitTypeDef and initialize the associated handle.
|
|
* @param hqspi QSPI handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
|
|
{
|
|
8004ca0: b580 push {r7, lr}
|
|
8004ca2: b086 sub sp, #24
|
|
8004ca4: af02 add r7, sp, #8
|
|
8004ca6: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status;
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8004ca8: f7fe faca bl 8003240 <HAL_GetTick>
|
|
8004cac: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the QSPI handle allocation */
|
|
if(hqspi == NULL)
|
|
8004cae: 687b ldr r3, [r7, #4]
|
|
8004cb0: 2b00 cmp r3, #0
|
|
8004cb2: d101 bne.n 8004cb8 <HAL_QSPI_Init+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
8004cb4: 2301 movs r3, #1
|
|
8004cb6: e063 b.n 8004d80 <HAL_QSPI_Init+0xe0>
|
|
{
|
|
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
|
|
}
|
|
#endif
|
|
|
|
if(hqspi->State == HAL_QSPI_STATE_RESET)
|
|
8004cb8: 687b ldr r3, [r7, #4]
|
|
8004cba: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
|
|
8004cbe: b2db uxtb r3, r3
|
|
8004cc0: 2b00 cmp r3, #0
|
|
8004cc2: d10b bne.n 8004cdc <HAL_QSPI_Init+0x3c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hqspi->Lock = HAL_UNLOCKED;
|
|
8004cc4: 687b ldr r3, [r7, #4]
|
|
8004cc6: 2200 movs r2, #0
|
|
8004cc8: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
/* Init the low level hardware */
|
|
hqspi->MspInitCallback(hqspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_QSPI_MspInit(hqspi);
|
|
8004ccc: 6878 ldr r0, [r7, #4]
|
|
8004cce: f7fd ff13 bl 8002af8 <HAL_QSPI_MspInit>
|
|
#endif
|
|
|
|
/* Configure the default timeout for the QSPI memory access */
|
|
HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
|
|
8004cd2: f241 3188 movw r1, #5000 @ 0x1388
|
|
8004cd6: 6878 ldr r0, [r7, #4]
|
|
8004cd8: f000 f858 bl 8004d8c <HAL_QSPI_SetTimeout>
|
|
}
|
|
|
|
/* Configure QSPI FIFO Threshold */
|
|
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
|
|
8004cdc: 687b ldr r3, [r7, #4]
|
|
8004cde: 681b ldr r3, [r3, #0]
|
|
8004ce0: 681b ldr r3, [r3, #0]
|
|
8004ce2: f423 6170 bic.w r1, r3, #3840 @ 0xf00
|
|
8004ce6: 687b ldr r3, [r7, #4]
|
|
8004ce8: 689b ldr r3, [r3, #8]
|
|
8004cea: 3b01 subs r3, #1
|
|
8004cec: 021a lsls r2, r3, #8
|
|
8004cee: 687b ldr r3, [r7, #4]
|
|
8004cf0: 681b ldr r3, [r3, #0]
|
|
8004cf2: 430a orrs r2, r1
|
|
8004cf4: 601a str r2, [r3, #0]
|
|
((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
|
|
|
|
/* Wait till BUSY flag reset */
|
|
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
|
|
8004cf6: 687b ldr r3, [r7, #4]
|
|
8004cf8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004cfa: 9300 str r3, [sp, #0]
|
|
8004cfc: 68fb ldr r3, [r7, #12]
|
|
8004cfe: 2200 movs r2, #0
|
|
8004d00: 2120 movs r1, #32
|
|
8004d02: 6878 ldr r0, [r7, #4]
|
|
8004d04: f000 f850 bl 8004da8 <QSPI_WaitFlagStateUntilTimeout>
|
|
8004d08: 4603 mov r3, r0
|
|
8004d0a: 72fb strb r3, [r7, #11]
|
|
|
|
if(status == HAL_OK)
|
|
8004d0c: 7afb ldrb r3, [r7, #11]
|
|
8004d0e: 2b00 cmp r3, #0
|
|
8004d10: d131 bne.n 8004d76 <HAL_QSPI_Init+0xd6>
|
|
#if defined(QUADSPI_CR_DFM)
|
|
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
|
|
((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
|
|
hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
|
|
#else
|
|
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
|
|
8004d12: 687b ldr r3, [r7, #4]
|
|
8004d14: 681b ldr r3, [r3, #0]
|
|
8004d16: 681b ldr r3, [r3, #0]
|
|
8004d18: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000
|
|
8004d1c: f023 0310 bic.w r3, r3, #16
|
|
8004d20: 687a ldr r2, [r7, #4]
|
|
8004d22: 6852 ldr r2, [r2, #4]
|
|
8004d24: 0611 lsls r1, r2, #24
|
|
8004d26: 687a ldr r2, [r7, #4]
|
|
8004d28: 68d2 ldr r2, [r2, #12]
|
|
8004d2a: 4311 orrs r1, r2
|
|
8004d2c: 687a ldr r2, [r7, #4]
|
|
8004d2e: 6812 ldr r2, [r2, #0]
|
|
8004d30: 430b orrs r3, r1
|
|
8004d32: 6013 str r3, [r2, #0]
|
|
((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
|
|
hqspi->Init.SampleShifting));
|
|
#endif
|
|
|
|
/* Configure QSPI Flash Size, CS High Time and Clock Mode */
|
|
MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
|
|
8004d34: 687b ldr r3, [r7, #4]
|
|
8004d36: 681b ldr r3, [r3, #0]
|
|
8004d38: 685a ldr r2, [r3, #4]
|
|
8004d3a: 4b13 ldr r3, [pc, #76] @ (8004d88 <HAL_QSPI_Init+0xe8>)
|
|
8004d3c: 4013 ands r3, r2
|
|
8004d3e: 687a ldr r2, [r7, #4]
|
|
8004d40: 6912 ldr r2, [r2, #16]
|
|
8004d42: 0411 lsls r1, r2, #16
|
|
8004d44: 687a ldr r2, [r7, #4]
|
|
8004d46: 6952 ldr r2, [r2, #20]
|
|
8004d48: 4311 orrs r1, r2
|
|
8004d4a: 687a ldr r2, [r7, #4]
|
|
8004d4c: 6992 ldr r2, [r2, #24]
|
|
8004d4e: 4311 orrs r1, r2
|
|
8004d50: 687a ldr r2, [r7, #4]
|
|
8004d52: 6812 ldr r2, [r2, #0]
|
|
8004d54: 430b orrs r3, r1
|
|
8004d56: 6053 str r3, [r2, #4]
|
|
((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
|
|
hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
|
|
|
|
/* Enable the QSPI peripheral */
|
|
__HAL_QSPI_ENABLE(hqspi);
|
|
8004d58: 687b ldr r3, [r7, #4]
|
|
8004d5a: 681b ldr r3, [r3, #0]
|
|
8004d5c: 681a ldr r2, [r3, #0]
|
|
8004d5e: 687b ldr r3, [r7, #4]
|
|
8004d60: 681b ldr r3, [r3, #0]
|
|
8004d62: f042 0201 orr.w r2, r2, #1
|
|
8004d66: 601a str r2, [r3, #0]
|
|
|
|
/* Set QSPI error code to none */
|
|
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
|
|
8004d68: 687b ldr r3, [r7, #4]
|
|
8004d6a: 2200 movs r2, #0
|
|
8004d6c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Initialize the QSPI state */
|
|
hqspi->State = HAL_QSPI_STATE_READY;
|
|
8004d6e: 687b ldr r3, [r7, #4]
|
|
8004d70: 2201 movs r2, #1
|
|
8004d72: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hqspi);
|
|
8004d76: 687b ldr r3, [r7, #4]
|
|
8004d78: 2200 movs r2, #0
|
|
8004d7a: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8004d7e: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8004d80: 4618 mov r0, r3
|
|
8004d82: 3710 adds r7, #16
|
|
8004d84: 46bd mov sp, r7
|
|
8004d86: bd80 pop {r7, pc}
|
|
8004d88: ffe0f8fe .word 0xffe0f8fe
|
|
|
|
08004d8c <HAL_QSPI_SetTimeout>:
|
|
* @param hqspi QSPI handle.
|
|
* @param Timeout Timeout for the QSPI memory access.
|
|
* @retval None
|
|
*/
|
|
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
|
|
{
|
|
8004d8c: b480 push {r7}
|
|
8004d8e: b083 sub sp, #12
|
|
8004d90: af00 add r7, sp, #0
|
|
8004d92: 6078 str r0, [r7, #4]
|
|
8004d94: 6039 str r1, [r7, #0]
|
|
hqspi->Timeout = Timeout;
|
|
8004d96: 687b ldr r3, [r7, #4]
|
|
8004d98: 683a ldr r2, [r7, #0]
|
|
8004d9a: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
8004d9c: bf00 nop
|
|
8004d9e: 370c adds r7, #12
|
|
8004da0: 46bd mov sp, r7
|
|
8004da2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004da6: 4770 bx lr
|
|
|
|
08004da8 <QSPI_WaitFlagStateUntilTimeout>:
|
|
* @param Timeout Duration of the timeout
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
|
|
FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8004da8: b580 push {r7, lr}
|
|
8004daa: b084 sub sp, #16
|
|
8004dac: af00 add r7, sp, #0
|
|
8004dae: 60f8 str r0, [r7, #12]
|
|
8004db0: 60b9 str r1, [r7, #8]
|
|
8004db2: 603b str r3, [r7, #0]
|
|
8004db4: 4613 mov r3, r2
|
|
8004db6: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is in expected state */
|
|
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
|
|
8004db8: e01a b.n 8004df0 <QSPI_WaitFlagStateUntilTimeout+0x48>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8004dba: 69bb ldr r3, [r7, #24]
|
|
8004dbc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8004dc0: d016 beq.n 8004df0 <QSPI_WaitFlagStateUntilTimeout+0x48>
|
|
{
|
|
if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8004dc2: f7fe fa3d bl 8003240 <HAL_GetTick>
|
|
8004dc6: 4602 mov r2, r0
|
|
8004dc8: 683b ldr r3, [r7, #0]
|
|
8004dca: 1ad3 subs r3, r2, r3
|
|
8004dcc: 69ba ldr r2, [r7, #24]
|
|
8004dce: 429a cmp r2, r3
|
|
8004dd0: d302 bcc.n 8004dd8 <QSPI_WaitFlagStateUntilTimeout+0x30>
|
|
8004dd2: 69bb ldr r3, [r7, #24]
|
|
8004dd4: 2b00 cmp r3, #0
|
|
8004dd6: d10b bne.n 8004df0 <QSPI_WaitFlagStateUntilTimeout+0x48>
|
|
{
|
|
hqspi->State = HAL_QSPI_STATE_ERROR;
|
|
8004dd8: 68fb ldr r3, [r7, #12]
|
|
8004dda: 2204 movs r2, #4
|
|
8004ddc: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
|
|
8004de0: 68fb ldr r3, [r7, #12]
|
|
8004de2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004de4: f043 0201 orr.w r2, r3, #1
|
|
8004de8: 68fb ldr r3, [r7, #12]
|
|
8004dea: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_ERROR;
|
|
8004dec: 2301 movs r3, #1
|
|
8004dee: e00e b.n 8004e0e <QSPI_WaitFlagStateUntilTimeout+0x66>
|
|
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
|
|
8004df0: 68fb ldr r3, [r7, #12]
|
|
8004df2: 681b ldr r3, [r3, #0]
|
|
8004df4: 689a ldr r2, [r3, #8]
|
|
8004df6: 68bb ldr r3, [r7, #8]
|
|
8004df8: 4013 ands r3, r2
|
|
8004dfa: 2b00 cmp r3, #0
|
|
8004dfc: bf14 ite ne
|
|
8004dfe: 2301 movne r3, #1
|
|
8004e00: 2300 moveq r3, #0
|
|
8004e02: b2db uxtb r3, r3
|
|
8004e04: 461a mov r2, r3
|
|
8004e06: 79fb ldrb r3, [r7, #7]
|
|
8004e08: 429a cmp r2, r3
|
|
8004e0a: d1d6 bne.n 8004dba <QSPI_WaitFlagStateUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8004e0c: 2300 movs r3, #0
|
|
}
|
|
8004e0e: 4618 mov r0, r3
|
|
8004e10: 3710 adds r7, #16
|
|
8004e12: 46bd mov sp, r7
|
|
8004e14: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08004e18 <HAL_RCC_OscConfig>:
|
|
* @note If HSE failed to start, HSE should be disabled before recalling
|
|
HAL_RCC_OscConfig().
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8004e18: b580 push {r7, lr}
|
|
8004e1a: b088 sub sp, #32
|
|
8004e1c: af00 add r7, sp, #0
|
|
8004e1e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status;
|
|
uint32_t sysclk_source, pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8004e20: 687b ldr r3, [r7, #4]
|
|
8004e22: 2b00 cmp r3, #0
|
|
8004e24: d101 bne.n 8004e2a <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e26: 2301 movs r3, #1
|
|
8004e28: e3ca b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8004e2a: 4b97 ldr r3, [pc, #604] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004e2c: 689b ldr r3, [r3, #8]
|
|
8004e2e: f003 030c and.w r3, r3, #12
|
|
8004e32: 61bb str r3, [r7, #24]
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8004e34: 4b94 ldr r3, [pc, #592] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004e36: 68db ldr r3, [r3, #12]
|
|
8004e38: f003 0303 and.w r3, r3, #3
|
|
8004e3c: 617b str r3, [r7, #20]
|
|
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
8004e3e: 687b ldr r3, [r7, #4]
|
|
8004e40: 681b ldr r3, [r3, #0]
|
|
8004e42: f003 0310 and.w r3, r3, #16
|
|
8004e46: 2b00 cmp r3, #0
|
|
8004e48: f000 80e4 beq.w 8005014 <HAL_RCC_OscConfig+0x1fc>
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
8004e4c: 69bb ldr r3, [r7, #24]
|
|
8004e4e: 2b00 cmp r3, #0
|
|
8004e50: d007 beq.n 8004e62 <HAL_RCC_OscConfig+0x4a>
|
|
8004e52: 69bb ldr r3, [r7, #24]
|
|
8004e54: 2b0c cmp r3, #12
|
|
8004e56: f040 808b bne.w 8004f70 <HAL_RCC_OscConfig+0x158>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
|
|
8004e5a: 697b ldr r3, [r7, #20]
|
|
8004e5c: 2b01 cmp r3, #1
|
|
8004e5e: f040 8087 bne.w 8004f70 <HAL_RCC_OscConfig+0x158>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8004e62: 4b89 ldr r3, [pc, #548] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004e64: 681b ldr r3, [r3, #0]
|
|
8004e66: f003 0302 and.w r3, r3, #2
|
|
8004e6a: 2b00 cmp r3, #0
|
|
8004e6c: d005 beq.n 8004e7a <HAL_RCC_OscConfig+0x62>
|
|
8004e6e: 687b ldr r3, [r7, #4]
|
|
8004e70: 699b ldr r3, [r3, #24]
|
|
8004e72: 2b00 cmp r3, #0
|
|
8004e74: d101 bne.n 8004e7a <HAL_RCC_OscConfig+0x62>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e76: 2301 movs r3, #1
|
|
8004e78: e3a2 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
else
|
|
{
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
8004e7a: 687b ldr r3, [r7, #4]
|
|
8004e7c: 6a1a ldr r2, [r3, #32]
|
|
8004e7e: 4b82 ldr r3, [pc, #520] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004e80: 681b ldr r3, [r3, #0]
|
|
8004e82: f003 0308 and.w r3, r3, #8
|
|
8004e86: 2b00 cmp r3, #0
|
|
8004e88: d004 beq.n 8004e94 <HAL_RCC_OscConfig+0x7c>
|
|
8004e8a: 4b7f ldr r3, [pc, #508] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004e8c: 681b ldr r3, [r3, #0]
|
|
8004e8e: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8004e92: e005 b.n 8004ea0 <HAL_RCC_OscConfig+0x88>
|
|
8004e94: 4b7c ldr r3, [pc, #496] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004e96: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004e9a: 091b lsrs r3, r3, #4
|
|
8004e9c: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8004ea0: 4293 cmp r3, r2
|
|
8004ea2: d223 bcs.n 8004eec <HAL_RCC_OscConfig+0xd4>
|
|
{
|
|
/* First increase number of wait states update if necessary */
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8004ea4: 687b ldr r3, [r7, #4]
|
|
8004ea6: 6a1b ldr r3, [r3, #32]
|
|
8004ea8: 4618 mov r0, r3
|
|
8004eaa: f000 fd55 bl 8005958 <RCC_SetFlashLatencyFromMSIRange>
|
|
8004eae: 4603 mov r3, r0
|
|
8004eb0: 2b00 cmp r3, #0
|
|
8004eb2: d001 beq.n 8004eb8 <HAL_RCC_OscConfig+0xa0>
|
|
{
|
|
return HAL_ERROR;
|
|
8004eb4: 2301 movs r3, #1
|
|
8004eb6: e383 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8004eb8: 4b73 ldr r3, [pc, #460] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004eba: 681b ldr r3, [r3, #0]
|
|
8004ebc: 4a72 ldr r2, [pc, #456] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004ebe: f043 0308 orr.w r3, r3, #8
|
|
8004ec2: 6013 str r3, [r2, #0]
|
|
8004ec4: 4b70 ldr r3, [pc, #448] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004ec6: 681b ldr r3, [r3, #0]
|
|
8004ec8: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004ecc: 687b ldr r3, [r7, #4]
|
|
8004ece: 6a1b ldr r3, [r3, #32]
|
|
8004ed0: 496d ldr r1, [pc, #436] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004ed2: 4313 orrs r3, r2
|
|
8004ed4: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8004ed6: 4b6c ldr r3, [pc, #432] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004ed8: 685b ldr r3, [r3, #4]
|
|
8004eda: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8004ede: 687b ldr r3, [r7, #4]
|
|
8004ee0: 69db ldr r3, [r3, #28]
|
|
8004ee2: 021b lsls r3, r3, #8
|
|
8004ee4: 4968 ldr r1, [pc, #416] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004ee6: 4313 orrs r3, r2
|
|
8004ee8: 604b str r3, [r1, #4]
|
|
8004eea: e025 b.n 8004f38 <HAL_RCC_OscConfig+0x120>
|
|
}
|
|
else
|
|
{
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8004eec: 4b66 ldr r3, [pc, #408] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004eee: 681b ldr r3, [r3, #0]
|
|
8004ef0: 4a65 ldr r2, [pc, #404] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004ef2: f043 0308 orr.w r3, r3, #8
|
|
8004ef6: 6013 str r3, [r2, #0]
|
|
8004ef8: 4b63 ldr r3, [pc, #396] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004efa: 681b ldr r3, [r3, #0]
|
|
8004efc: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004f00: 687b ldr r3, [r7, #4]
|
|
8004f02: 6a1b ldr r3, [r3, #32]
|
|
8004f04: 4960 ldr r1, [pc, #384] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004f06: 4313 orrs r3, r2
|
|
8004f08: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8004f0a: 4b5f ldr r3, [pc, #380] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004f0c: 685b ldr r3, [r3, #4]
|
|
8004f0e: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8004f12: 687b ldr r3, [r7, #4]
|
|
8004f14: 69db ldr r3, [r3, #28]
|
|
8004f16: 021b lsls r3, r3, #8
|
|
8004f18: 495b ldr r1, [pc, #364] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004f1a: 4313 orrs r3, r2
|
|
8004f1c: 604b str r3, [r1, #4]
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
/* Only possible when MSI is the System clock source */
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8004f1e: 69bb ldr r3, [r7, #24]
|
|
8004f20: 2b00 cmp r3, #0
|
|
8004f22: d109 bne.n 8004f38 <HAL_RCC_OscConfig+0x120>
|
|
{
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8004f24: 687b ldr r3, [r7, #4]
|
|
8004f26: 6a1b ldr r3, [r3, #32]
|
|
8004f28: 4618 mov r0, r3
|
|
8004f2a: f000 fd15 bl 8005958 <RCC_SetFlashLatencyFromMSIRange>
|
|
8004f2e: 4603 mov r3, r0
|
|
8004f30: 2b00 cmp r3, #0
|
|
8004f32: d001 beq.n 8004f38 <HAL_RCC_OscConfig+0x120>
|
|
{
|
|
return HAL_ERROR;
|
|
8004f34: 2301 movs r3, #1
|
|
8004f36: e343 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8004f38: f000 fc4a bl 80057d0 <HAL_RCC_GetSysClockFreq>
|
|
8004f3c: 4602 mov r2, r0
|
|
8004f3e: 4b52 ldr r3, [pc, #328] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004f40: 689b ldr r3, [r3, #8]
|
|
8004f42: 091b lsrs r3, r3, #4
|
|
8004f44: f003 030f and.w r3, r3, #15
|
|
8004f48: 4950 ldr r1, [pc, #320] @ (800508c <HAL_RCC_OscConfig+0x274>)
|
|
8004f4a: 5ccb ldrb r3, [r1, r3]
|
|
8004f4c: f003 031f and.w r3, r3, #31
|
|
8004f50: fa22 f303 lsr.w r3, r2, r3
|
|
8004f54: 4a4e ldr r2, [pc, #312] @ (8005090 <HAL_RCC_OscConfig+0x278>)
|
|
8004f56: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
8004f58: 4b4e ldr r3, [pc, #312] @ (8005094 <HAL_RCC_OscConfig+0x27c>)
|
|
8004f5a: 681b ldr r3, [r3, #0]
|
|
8004f5c: 4618 mov r0, r3
|
|
8004f5e: f7fe f91f bl 80031a0 <HAL_InitTick>
|
|
8004f62: 4603 mov r3, r0
|
|
8004f64: 73fb strb r3, [r7, #15]
|
|
if(status != HAL_OK)
|
|
8004f66: 7bfb ldrb r3, [r7, #15]
|
|
8004f68: 2b00 cmp r3, #0
|
|
8004f6a: d052 beq.n 8005012 <HAL_RCC_OscConfig+0x1fa>
|
|
{
|
|
return status;
|
|
8004f6c: 7bfb ldrb r3, [r7, #15]
|
|
8004f6e: e327 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the MSI State */
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
8004f70: 687b ldr r3, [r7, #4]
|
|
8004f72: 699b ldr r3, [r3, #24]
|
|
8004f74: 2b00 cmp r3, #0
|
|
8004f76: d032 beq.n 8004fde <HAL_RCC_OscConfig+0x1c6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_ENABLE();
|
|
8004f78: 4b43 ldr r3, [pc, #268] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004f7a: 681b ldr r3, [r3, #0]
|
|
8004f7c: 4a42 ldr r2, [pc, #264] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004f7e: f043 0301 orr.w r3, r3, #1
|
|
8004f82: 6013 str r3, [r2, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8004f84: f7fe f95c bl 8003240 <HAL_GetTick>
|
|
8004f88: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8004f8a: e008 b.n 8004f9e <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8004f8c: f7fe f958 bl 8003240 <HAL_GetTick>
|
|
8004f90: 4602 mov r2, r0
|
|
8004f92: 693b ldr r3, [r7, #16]
|
|
8004f94: 1ad3 subs r3, r2, r3
|
|
8004f96: 2b02 cmp r3, #2
|
|
8004f98: d901 bls.n 8004f9e <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004f9a: 2303 movs r3, #3
|
|
8004f9c: e310 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8004f9e: 4b3a ldr r3, [pc, #232] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fa0: 681b ldr r3, [r3, #0]
|
|
8004fa2: f003 0302 and.w r3, r3, #2
|
|
8004fa6: 2b00 cmp r3, #0
|
|
8004fa8: d0f0 beq.n 8004f8c <HAL_RCC_OscConfig+0x174>
|
|
}
|
|
}
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8004faa: 4b37 ldr r3, [pc, #220] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fac: 681b ldr r3, [r3, #0]
|
|
8004fae: 4a36 ldr r2, [pc, #216] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fb0: f043 0308 orr.w r3, r3, #8
|
|
8004fb4: 6013 str r3, [r2, #0]
|
|
8004fb6: 4b34 ldr r3, [pc, #208] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fb8: 681b ldr r3, [r3, #0]
|
|
8004fba: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004fbe: 687b ldr r3, [r7, #4]
|
|
8004fc0: 6a1b ldr r3, [r3, #32]
|
|
8004fc2: 4931 ldr r1, [pc, #196] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fc4: 4313 orrs r3, r2
|
|
8004fc6: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8004fc8: 4b2f ldr r3, [pc, #188] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fca: 685b ldr r3, [r3, #4]
|
|
8004fcc: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8004fd0: 687b ldr r3, [r7, #4]
|
|
8004fd2: 69db ldr r3, [r3, #28]
|
|
8004fd4: 021b lsls r3, r3, #8
|
|
8004fd6: 492c ldr r1, [pc, #176] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fd8: 4313 orrs r3, r2
|
|
8004fda: 604b str r3, [r1, #4]
|
|
8004fdc: e01a b.n 8005014 <HAL_RCC_OscConfig+0x1fc>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_DISABLE();
|
|
8004fde: 4b2a ldr r3, [pc, #168] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fe0: 681b ldr r3, [r3, #0]
|
|
8004fe2: 4a29 ldr r2, [pc, #164] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8004fe4: f023 0301 bic.w r3, r3, #1
|
|
8004fe8: 6013 str r3, [r2, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8004fea: f7fe f929 bl 8003240 <HAL_GetTick>
|
|
8004fee: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
8004ff0: e008 b.n 8005004 <HAL_RCC_OscConfig+0x1ec>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8004ff2: f7fe f925 bl 8003240 <HAL_GetTick>
|
|
8004ff6: 4602 mov r2, r0
|
|
8004ff8: 693b ldr r3, [r7, #16]
|
|
8004ffa: 1ad3 subs r3, r2, r3
|
|
8004ffc: 2b02 cmp r3, #2
|
|
8004ffe: d901 bls.n 8005004 <HAL_RCC_OscConfig+0x1ec>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005000: 2303 movs r3, #3
|
|
8005002: e2dd b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
8005004: 4b20 ldr r3, [pc, #128] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8005006: 681b ldr r3, [r3, #0]
|
|
8005008: f003 0302 and.w r3, r3, #2
|
|
800500c: 2b00 cmp r3, #0
|
|
800500e: d1f0 bne.n 8004ff2 <HAL_RCC_OscConfig+0x1da>
|
|
8005010: e000 b.n 8005014 <HAL_RCC_OscConfig+0x1fc>
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8005012: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8005014: 687b ldr r3, [r7, #4]
|
|
8005016: 681b ldr r3, [r3, #0]
|
|
8005018: f003 0301 and.w r3, r3, #1
|
|
800501c: 2b00 cmp r3, #0
|
|
800501e: d074 beq.n 800510a <HAL_RCC_OscConfig+0x2f2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
|
|
8005020: 69bb ldr r3, [r7, #24]
|
|
8005022: 2b08 cmp r3, #8
|
|
8005024: d005 beq.n 8005032 <HAL_RCC_OscConfig+0x21a>
|
|
8005026: 69bb ldr r3, [r7, #24]
|
|
8005028: 2b0c cmp r3, #12
|
|
800502a: d10e bne.n 800504a <HAL_RCC_OscConfig+0x232>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
800502c: 697b ldr r3, [r7, #20]
|
|
800502e: 2b03 cmp r3, #3
|
|
8005030: d10b bne.n 800504a <HAL_RCC_OscConfig+0x232>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8005032: 4b15 ldr r3, [pc, #84] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8005034: 681b ldr r3, [r3, #0]
|
|
8005036: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800503a: 2b00 cmp r3, #0
|
|
800503c: d064 beq.n 8005108 <HAL_RCC_OscConfig+0x2f0>
|
|
800503e: 687b ldr r3, [r7, #4]
|
|
8005040: 685b ldr r3, [r3, #4]
|
|
8005042: 2b00 cmp r3, #0
|
|
8005044: d160 bne.n 8005108 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_ERROR;
|
|
8005046: 2301 movs r3, #1
|
|
8005048: e2ba b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
800504a: 687b ldr r3, [r7, #4]
|
|
800504c: 685b ldr r3, [r3, #4]
|
|
800504e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8005052: d106 bne.n 8005062 <HAL_RCC_OscConfig+0x24a>
|
|
8005054: 4b0c ldr r3, [pc, #48] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8005056: 681b ldr r3, [r3, #0]
|
|
8005058: 4a0b ldr r2, [pc, #44] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
800505a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800505e: 6013 str r3, [r2, #0]
|
|
8005060: e026 b.n 80050b0 <HAL_RCC_OscConfig+0x298>
|
|
8005062: 687b ldr r3, [r7, #4]
|
|
8005064: 685b ldr r3, [r3, #4]
|
|
8005066: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
800506a: d115 bne.n 8005098 <HAL_RCC_OscConfig+0x280>
|
|
800506c: 4b06 ldr r3, [pc, #24] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
800506e: 681b ldr r3, [r3, #0]
|
|
8005070: 4a05 ldr r2, [pc, #20] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
8005072: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8005076: 6013 str r3, [r2, #0]
|
|
8005078: 4b03 ldr r3, [pc, #12] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
800507a: 681b ldr r3, [r3, #0]
|
|
800507c: 4a02 ldr r2, [pc, #8] @ (8005088 <HAL_RCC_OscConfig+0x270>)
|
|
800507e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8005082: 6013 str r3, [r2, #0]
|
|
8005084: e014 b.n 80050b0 <HAL_RCC_OscConfig+0x298>
|
|
8005086: bf00 nop
|
|
8005088: 40021000 .word 0x40021000
|
|
800508c: 0800a0d8 .word 0x0800a0d8
|
|
8005090: 200000c4 .word 0x200000c4
|
|
8005094: 200000c8 .word 0x200000c8
|
|
8005098: 4ba0 ldr r3, [pc, #640] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
800509a: 681b ldr r3, [r3, #0]
|
|
800509c: 4a9f ldr r2, [pc, #636] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
800509e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80050a2: 6013 str r3, [r2, #0]
|
|
80050a4: 4b9d ldr r3, [pc, #628] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80050a6: 681b ldr r3, [r3, #0]
|
|
80050a8: 4a9c ldr r2, [pc, #624] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80050aa: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
80050ae: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
80050b0: 687b ldr r3, [r7, #4]
|
|
80050b2: 685b ldr r3, [r3, #4]
|
|
80050b4: 2b00 cmp r3, #0
|
|
80050b6: d013 beq.n 80050e0 <HAL_RCC_OscConfig+0x2c8>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80050b8: f7fe f8c2 bl 8003240 <HAL_GetTick>
|
|
80050bc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80050be: e008 b.n 80050d2 <HAL_RCC_OscConfig+0x2ba>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80050c0: f7fe f8be bl 8003240 <HAL_GetTick>
|
|
80050c4: 4602 mov r2, r0
|
|
80050c6: 693b ldr r3, [r7, #16]
|
|
80050c8: 1ad3 subs r3, r2, r3
|
|
80050ca: 2b64 cmp r3, #100 @ 0x64
|
|
80050cc: d901 bls.n 80050d2 <HAL_RCC_OscConfig+0x2ba>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80050ce: 2303 movs r3, #3
|
|
80050d0: e276 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80050d2: 4b92 ldr r3, [pc, #584] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80050d4: 681b ldr r3, [r3, #0]
|
|
80050d6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80050da: 2b00 cmp r3, #0
|
|
80050dc: d0f0 beq.n 80050c0 <HAL_RCC_OscConfig+0x2a8>
|
|
80050de: e014 b.n 800510a <HAL_RCC_OscConfig+0x2f2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80050e0: f7fe f8ae bl 8003240 <HAL_GetTick>
|
|
80050e4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
80050e6: e008 b.n 80050fa <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80050e8: f7fe f8aa bl 8003240 <HAL_GetTick>
|
|
80050ec: 4602 mov r2, r0
|
|
80050ee: 693b ldr r3, [r7, #16]
|
|
80050f0: 1ad3 subs r3, r2, r3
|
|
80050f2: 2b64 cmp r3, #100 @ 0x64
|
|
80050f4: d901 bls.n 80050fa <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80050f6: 2303 movs r3, #3
|
|
80050f8: e262 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
80050fa: 4b88 ldr r3, [pc, #544] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80050fc: 681b ldr r3, [r3, #0]
|
|
80050fe: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005102: 2b00 cmp r3, #0
|
|
8005104: d1f0 bne.n 80050e8 <HAL_RCC_OscConfig+0x2d0>
|
|
8005106: e000 b.n 800510a <HAL_RCC_OscConfig+0x2f2>
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8005108: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
800510a: 687b ldr r3, [r7, #4]
|
|
800510c: 681b ldr r3, [r3, #0]
|
|
800510e: f003 0302 and.w r3, r3, #2
|
|
8005112: 2b00 cmp r3, #0
|
|
8005114: d060 beq.n 80051d8 <HAL_RCC_OscConfig+0x3c0>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
|
|
8005116: 69bb ldr r3, [r7, #24]
|
|
8005118: 2b04 cmp r3, #4
|
|
800511a: d005 beq.n 8005128 <HAL_RCC_OscConfig+0x310>
|
|
800511c: 69bb ldr r3, [r7, #24]
|
|
800511e: 2b0c cmp r3, #12
|
|
8005120: d119 bne.n 8005156 <HAL_RCC_OscConfig+0x33e>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
8005122: 697b ldr r3, [r7, #20]
|
|
8005124: 2b02 cmp r3, #2
|
|
8005126: d116 bne.n 8005156 <HAL_RCC_OscConfig+0x33e>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8005128: 4b7c ldr r3, [pc, #496] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
800512a: 681b ldr r3, [r3, #0]
|
|
800512c: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8005130: 2b00 cmp r3, #0
|
|
8005132: d005 beq.n 8005140 <HAL_RCC_OscConfig+0x328>
|
|
8005134: 687b ldr r3, [r7, #4]
|
|
8005136: 68db ldr r3, [r3, #12]
|
|
8005138: 2b00 cmp r3, #0
|
|
800513a: d101 bne.n 8005140 <HAL_RCC_OscConfig+0x328>
|
|
{
|
|
return HAL_ERROR;
|
|
800513c: 2301 movs r3, #1
|
|
800513e: e23f b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8005140: 4b76 ldr r3, [pc, #472] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005142: 685b ldr r3, [r3, #4]
|
|
8005144: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
|
|
8005148: 687b ldr r3, [r7, #4]
|
|
800514a: 691b ldr r3, [r3, #16]
|
|
800514c: 061b lsls r3, r3, #24
|
|
800514e: 4973 ldr r1, [pc, #460] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005150: 4313 orrs r3, r2
|
|
8005152: 604b str r3, [r1, #4]
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8005154: e040 b.n 80051d8 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8005156: 687b ldr r3, [r7, #4]
|
|
8005158: 68db ldr r3, [r3, #12]
|
|
800515a: 2b00 cmp r3, #0
|
|
800515c: d023 beq.n 80051a6 <HAL_RCC_OscConfig+0x38e>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
800515e: 4b6f ldr r3, [pc, #444] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005160: 681b ldr r3, [r3, #0]
|
|
8005162: 4a6e ldr r2, [pc, #440] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005164: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8005168: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800516a: f7fe f869 bl 8003240 <HAL_GetTick>
|
|
800516e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8005170: e008 b.n 8005184 <HAL_RCC_OscConfig+0x36c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8005172: f7fe f865 bl 8003240 <HAL_GetTick>
|
|
8005176: 4602 mov r2, r0
|
|
8005178: 693b ldr r3, [r7, #16]
|
|
800517a: 1ad3 subs r3, r2, r3
|
|
800517c: 2b02 cmp r3, #2
|
|
800517e: d901 bls.n 8005184 <HAL_RCC_OscConfig+0x36c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005180: 2303 movs r3, #3
|
|
8005182: e21d b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8005184: 4b65 ldr r3, [pc, #404] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005186: 681b ldr r3, [r3, #0]
|
|
8005188: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800518c: 2b00 cmp r3, #0
|
|
800518e: d0f0 beq.n 8005172 <HAL_RCC_OscConfig+0x35a>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8005190: 4b62 ldr r3, [pc, #392] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005192: 685b ldr r3, [r3, #4]
|
|
8005194: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
|
|
8005198: 687b ldr r3, [r7, #4]
|
|
800519a: 691b ldr r3, [r3, #16]
|
|
800519c: 061b lsls r3, r3, #24
|
|
800519e: 495f ldr r1, [pc, #380] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80051a0: 4313 orrs r3, r2
|
|
80051a2: 604b str r3, [r1, #4]
|
|
80051a4: e018 b.n 80051d8 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
80051a6: 4b5d ldr r3, [pc, #372] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80051a8: 681b ldr r3, [r3, #0]
|
|
80051aa: 4a5c ldr r2, [pc, #368] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80051ac: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80051b0: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80051b2: f7fe f845 bl 8003240 <HAL_GetTick>
|
|
80051b6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
80051b8: e008 b.n 80051cc <HAL_RCC_OscConfig+0x3b4>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
80051ba: f7fe f841 bl 8003240 <HAL_GetTick>
|
|
80051be: 4602 mov r2, r0
|
|
80051c0: 693b ldr r3, [r7, #16]
|
|
80051c2: 1ad3 subs r3, r2, r3
|
|
80051c4: 2b02 cmp r3, #2
|
|
80051c6: d901 bls.n 80051cc <HAL_RCC_OscConfig+0x3b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80051c8: 2303 movs r3, #3
|
|
80051ca: e1f9 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
80051cc: 4b53 ldr r3, [pc, #332] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80051ce: 681b ldr r3, [r3, #0]
|
|
80051d0: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80051d4: 2b00 cmp r3, #0
|
|
80051d6: d1f0 bne.n 80051ba <HAL_RCC_OscConfig+0x3a2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
80051d8: 687b ldr r3, [r7, #4]
|
|
80051da: 681b ldr r3, [r3, #0]
|
|
80051dc: f003 0308 and.w r3, r3, #8
|
|
80051e0: 2b00 cmp r3, #0
|
|
80051e2: d03c beq.n 800525e <HAL_RCC_OscConfig+0x446>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
80051e4: 687b ldr r3, [r7, #4]
|
|
80051e6: 695b ldr r3, [r3, #20]
|
|
80051e8: 2b00 cmp r3, #0
|
|
80051ea: d01c beq.n 8005226 <HAL_RCC_OscConfig+0x40e>
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
|
|
}
|
|
#endif /* RCC_CSR_LSIPREDIV */
|
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
80051ec: 4b4b ldr r3, [pc, #300] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80051ee: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80051f2: 4a4a ldr r2, [pc, #296] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80051f4: f043 0301 orr.w r3, r3, #1
|
|
80051f8: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80051fc: f7fe f820 bl 8003240 <HAL_GetTick>
|
|
8005200: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8005202: e008 b.n 8005216 <HAL_RCC_OscConfig+0x3fe>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8005204: f7fe f81c bl 8003240 <HAL_GetTick>
|
|
8005208: 4602 mov r2, r0
|
|
800520a: 693b ldr r3, [r7, #16]
|
|
800520c: 1ad3 subs r3, r2, r3
|
|
800520e: 2b02 cmp r3, #2
|
|
8005210: d901 bls.n 8005216 <HAL_RCC_OscConfig+0x3fe>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005212: 2303 movs r3, #3
|
|
8005214: e1d4 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8005216: 4b41 ldr r3, [pc, #260] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005218: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800521c: f003 0302 and.w r3, r3, #2
|
|
8005220: 2b00 cmp r3, #0
|
|
8005222: d0ef beq.n 8005204 <HAL_RCC_OscConfig+0x3ec>
|
|
8005224: e01b b.n 800525e <HAL_RCC_OscConfig+0x446>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8005226: 4b3d ldr r3, [pc, #244] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005228: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800522c: 4a3b ldr r2, [pc, #236] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
800522e: f023 0301 bic.w r3, r3, #1
|
|
8005232: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005236: f7fe f803 bl 8003240 <HAL_GetTick>
|
|
800523a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
800523c: e008 b.n 8005250 <HAL_RCC_OscConfig+0x438>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
800523e: f7fd ffff bl 8003240 <HAL_GetTick>
|
|
8005242: 4602 mov r2, r0
|
|
8005244: 693b ldr r3, [r7, #16]
|
|
8005246: 1ad3 subs r3, r2, r3
|
|
8005248: 2b02 cmp r3, #2
|
|
800524a: d901 bls.n 8005250 <HAL_RCC_OscConfig+0x438>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800524c: 2303 movs r3, #3
|
|
800524e: e1b7 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8005250: 4b32 ldr r3, [pc, #200] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005252: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8005256: f003 0302 and.w r3, r3, #2
|
|
800525a: 2b00 cmp r3, #0
|
|
800525c: d1ef bne.n 800523e <HAL_RCC_OscConfig+0x426>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
800525e: 687b ldr r3, [r7, #4]
|
|
8005260: 681b ldr r3, [r3, #0]
|
|
8005262: f003 0304 and.w r3, r3, #4
|
|
8005266: 2b00 cmp r3, #0
|
|
8005268: f000 80a6 beq.w 80053b8 <HAL_RCC_OscConfig+0x5a0>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
800526c: 2300 movs r3, #0
|
|
800526e: 77fb strb r3, [r7, #31]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
|
|
8005270: 4b2a ldr r3, [pc, #168] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005272: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005274: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005278: 2b00 cmp r3, #0
|
|
800527a: d10d bne.n 8005298 <HAL_RCC_OscConfig+0x480>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800527c: 4b27 ldr r3, [pc, #156] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
800527e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005280: 4a26 ldr r2, [pc, #152] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005282: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005286: 6593 str r3, [r2, #88] @ 0x58
|
|
8005288: 4b24 ldr r3, [pc, #144] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
800528a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800528c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005290: 60bb str r3, [r7, #8]
|
|
8005292: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8005294: 2301 movs r3, #1
|
|
8005296: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8005298: 4b21 ldr r3, [pc, #132] @ (8005320 <HAL_RCC_OscConfig+0x508>)
|
|
800529a: 681b ldr r3, [r3, #0]
|
|
800529c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80052a0: 2b00 cmp r3, #0
|
|
80052a2: d118 bne.n 80052d6 <HAL_RCC_OscConfig+0x4be>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80052a4: 4b1e ldr r3, [pc, #120] @ (8005320 <HAL_RCC_OscConfig+0x508>)
|
|
80052a6: 681b ldr r3, [r3, #0]
|
|
80052a8: 4a1d ldr r2, [pc, #116] @ (8005320 <HAL_RCC_OscConfig+0x508>)
|
|
80052aa: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80052ae: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80052b0: f7fd ffc6 bl 8003240 <HAL_GetTick>
|
|
80052b4: 6138 str r0, [r7, #16]
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
80052b6: e008 b.n 80052ca <HAL_RCC_OscConfig+0x4b2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80052b8: f7fd ffc2 bl 8003240 <HAL_GetTick>
|
|
80052bc: 4602 mov r2, r0
|
|
80052be: 693b ldr r3, [r7, #16]
|
|
80052c0: 1ad3 subs r3, r2, r3
|
|
80052c2: 2b02 cmp r3, #2
|
|
80052c4: d901 bls.n 80052ca <HAL_RCC_OscConfig+0x4b2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80052c6: 2303 movs r3, #3
|
|
80052c8: e17a b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
80052ca: 4b15 ldr r3, [pc, #84] @ (8005320 <HAL_RCC_OscConfig+0x508>)
|
|
80052cc: 681b ldr r3, [r3, #0]
|
|
80052ce: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80052d2: 2b00 cmp r3, #0
|
|
80052d4: d0f0 beq.n 80052b8 <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
}
|
|
#else
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
80052d6: 687b ldr r3, [r7, #4]
|
|
80052d8: 689b ldr r3, [r3, #8]
|
|
80052da: 2b01 cmp r3, #1
|
|
80052dc: d108 bne.n 80052f0 <HAL_RCC_OscConfig+0x4d8>
|
|
80052de: 4b0f ldr r3, [pc, #60] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80052e0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80052e4: 4a0d ldr r2, [pc, #52] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80052e6: f043 0301 orr.w r3, r3, #1
|
|
80052ea: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
80052ee: e029 b.n 8005344 <HAL_RCC_OscConfig+0x52c>
|
|
80052f0: 687b ldr r3, [r7, #4]
|
|
80052f2: 689b ldr r3, [r3, #8]
|
|
80052f4: 2b05 cmp r3, #5
|
|
80052f6: d115 bne.n 8005324 <HAL_RCC_OscConfig+0x50c>
|
|
80052f8: 4b08 ldr r3, [pc, #32] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
80052fa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80052fe: 4a07 ldr r2, [pc, #28] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005300: f043 0304 orr.w r3, r3, #4
|
|
8005304: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8005308: 4b04 ldr r3, [pc, #16] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
800530a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800530e: 4a03 ldr r2, [pc, #12] @ (800531c <HAL_RCC_OscConfig+0x504>)
|
|
8005310: f043 0301 orr.w r3, r3, #1
|
|
8005314: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8005318: e014 b.n 8005344 <HAL_RCC_OscConfig+0x52c>
|
|
800531a: bf00 nop
|
|
800531c: 40021000 .word 0x40021000
|
|
8005320: 40007000 .word 0x40007000
|
|
8005324: 4b9c ldr r3, [pc, #624] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005326: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800532a: 4a9b ldr r2, [pc, #620] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800532c: f023 0301 bic.w r3, r3, #1
|
|
8005330: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8005334: 4b98 ldr r3, [pc, #608] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005336: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800533a: 4a97 ldr r2, [pc, #604] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800533c: f023 0304 bic.w r3, r3, #4
|
|
8005340: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8005344: 687b ldr r3, [r7, #4]
|
|
8005346: 689b ldr r3, [r3, #8]
|
|
8005348: 2b00 cmp r3, #0
|
|
800534a: d016 beq.n 800537a <HAL_RCC_OscConfig+0x562>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800534c: f7fd ff78 bl 8003240 <HAL_GetTick>
|
|
8005350: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8005352: e00a b.n 800536a <HAL_RCC_OscConfig+0x552>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005354: f7fd ff74 bl 8003240 <HAL_GetTick>
|
|
8005358: 4602 mov r2, r0
|
|
800535a: 693b ldr r3, [r7, #16]
|
|
800535c: 1ad3 subs r3, r2, r3
|
|
800535e: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005362: 4293 cmp r3, r2
|
|
8005364: d901 bls.n 800536a <HAL_RCC_OscConfig+0x552>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005366: 2303 movs r3, #3
|
|
8005368: e12a b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
800536a: 4b8b ldr r3, [pc, #556] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800536c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005370: f003 0302 and.w r3, r3, #2
|
|
8005374: 2b00 cmp r3, #0
|
|
8005376: d0ed beq.n 8005354 <HAL_RCC_OscConfig+0x53c>
|
|
8005378: e015 b.n 80053a6 <HAL_RCC_OscConfig+0x58e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800537a: f7fd ff61 bl 8003240 <HAL_GetTick>
|
|
800537e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8005380: e00a b.n 8005398 <HAL_RCC_OscConfig+0x580>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005382: f7fd ff5d bl 8003240 <HAL_GetTick>
|
|
8005386: 4602 mov r2, r0
|
|
8005388: 693b ldr r3, [r7, #16]
|
|
800538a: 1ad3 subs r3, r2, r3
|
|
800538c: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005390: 4293 cmp r3, r2
|
|
8005392: d901 bls.n 8005398 <HAL_RCC_OscConfig+0x580>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005394: 2303 movs r3, #3
|
|
8005396: e113 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8005398: 4b7f ldr r3, [pc, #508] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800539a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800539e: f003 0302 and.w r3, r3, #2
|
|
80053a2: 2b00 cmp r3, #0
|
|
80053a4: d1ed bne.n 8005382 <HAL_RCC_OscConfig+0x56a>
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
80053a6: 7ffb ldrb r3, [r7, #31]
|
|
80053a8: 2b01 cmp r3, #1
|
|
80053aa: d105 bne.n 80053b8 <HAL_RCC_OscConfig+0x5a0>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80053ac: 4b7a ldr r3, [pc, #488] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
80053ae: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80053b0: 4a79 ldr r2, [pc, #484] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
80053b2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80053b6: 6593 str r3, [r2, #88] @ 0x58
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
80053b8: 687b ldr r3, [r7, #4]
|
|
80053ba: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80053bc: 2b00 cmp r3, #0
|
|
80053be: f000 80fe beq.w 80055be <HAL_RCC_OscConfig+0x7a6>
|
|
{
|
|
/* PLL On ? */
|
|
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
80053c2: 687b ldr r3, [r7, #4]
|
|
80053c4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80053c6: 2b02 cmp r3, #2
|
|
80053c8: f040 80d0 bne.w 800556c <HAL_RCC_OscConfig+0x754>
|
|
#endif /* RCC_PLLP_SUPPORT */
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Do nothing if PLL configuration is the unchanged */
|
|
pll_config = RCC->PLLCFGR;
|
|
80053cc: 4b72 ldr r3, [pc, #456] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
80053ce: 68db ldr r3, [r3, #12]
|
|
80053d0: 617b str r3, [r7, #20]
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
80053d2: 697b ldr r3, [r7, #20]
|
|
80053d4: f003 0203 and.w r2, r3, #3
|
|
80053d8: 687b ldr r3, [r7, #4]
|
|
80053da: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80053dc: 429a cmp r2, r3
|
|
80053de: d130 bne.n 8005442 <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
80053e0: 697b ldr r3, [r7, #20]
|
|
80053e2: f003 0270 and.w r2, r3, #112 @ 0x70
|
|
80053e6: 687b ldr r3, [r7, #4]
|
|
80053e8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80053ea: 3b01 subs r3, #1
|
|
80053ec: 011b lsls r3, r3, #4
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
80053ee: 429a cmp r2, r3
|
|
80053f0: d127 bne.n 8005442 <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
80053f2: 697b ldr r3, [r7, #20]
|
|
80053f4: f403 42fe and.w r2, r3, #32512 @ 0x7f00
|
|
80053f8: 687b ldr r3, [r7, #4]
|
|
80053fa: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80053fc: 021b lsls r3, r3, #8
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
80053fe: 429a cmp r2, r3
|
|
8005400: d11f bne.n 8005442 <HAL_RCC_OscConfig+0x62a>
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
#else
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
8005402: 697b ldr r3, [r7, #20]
|
|
8005404: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005408: 687a ldr r2, [r7, #4]
|
|
800540a: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
800540c: 2a07 cmp r2, #7
|
|
800540e: bf14 ite ne
|
|
8005410: 2201 movne r2, #1
|
|
8005412: 2200 moveq r2, #0
|
|
8005414: b2d2 uxtb r2, r2
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8005416: 4293 cmp r3, r2
|
|
8005418: d113 bne.n 8005442 <HAL_RCC_OscConfig+0x62a>
|
|
#endif
|
|
#endif
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
800541a: 697b ldr r3, [r7, #20]
|
|
800541c: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
|
|
8005420: 687b ldr r3, [r7, #4]
|
|
8005422: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005424: 085b lsrs r3, r3, #1
|
|
8005426: 3b01 subs r3, #1
|
|
8005428: 055b lsls r3, r3, #21
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
800542a: 429a cmp r2, r3
|
|
800542c: d109 bne.n 8005442 <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
|
800542e: 697b ldr r3, [r7, #20]
|
|
8005430: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
|
|
8005434: 687b ldr r3, [r7, #4]
|
|
8005436: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005438: 085b lsrs r3, r3, #1
|
|
800543a: 3b01 subs r3, #1
|
|
800543c: 065b lsls r3, r3, #25
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
800543e: 429a cmp r2, r3
|
|
8005440: d06e beq.n 8005520 <HAL_RCC_OscConfig+0x708>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
8005442: 69bb ldr r3, [r7, #24]
|
|
8005444: 2b0c cmp r3, #12
|
|
8005446: d069 beq.n 800551c <HAL_RCC_OscConfig+0x704>
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
|
|
/* Check if main PLL can be updated */
|
|
/* Not possible if the source is shared by other enabled PLLSAIx */
|
|
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
|
|
8005448: 4b53 ldr r3, [pc, #332] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800544a: 681b ldr r3, [r3, #0]
|
|
800544c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8005450: 2b00 cmp r3, #0
|
|
8005452: d105 bne.n 8005460 <HAL_RCC_OscConfig+0x648>
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
|
|
8005454: 4b50 ldr r3, [pc, #320] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005456: 681b ldr r3, [r3, #0]
|
|
8005458: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800545c: 2b00 cmp r3, #0
|
|
800545e: d001 beq.n 8005464 <HAL_RCC_OscConfig+0x64c>
|
|
#endif
|
|
)
|
|
{
|
|
return HAL_ERROR;
|
|
8005460: 2301 movs r3, #1
|
|
8005462: e0ad b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
else
|
|
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8005464: 4b4c ldr r3, [pc, #304] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005466: 681b ldr r3, [r3, #0]
|
|
8005468: 4a4b ldr r2, [pc, #300] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800546a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800546e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005470: f7fd fee6 bl 8003240 <HAL_GetTick>
|
|
8005474: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8005476: e008 b.n 800548a <HAL_RCC_OscConfig+0x672>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8005478: f7fd fee2 bl 8003240 <HAL_GetTick>
|
|
800547c: 4602 mov r2, r0
|
|
800547e: 693b ldr r3, [r7, #16]
|
|
8005480: 1ad3 subs r3, r2, r3
|
|
8005482: 2b02 cmp r3, #2
|
|
8005484: d901 bls.n 800548a <HAL_RCC_OscConfig+0x672>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005486: 2303 movs r3, #3
|
|
8005488: e09a b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800548a: 4b43 ldr r3, [pc, #268] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800548c: 681b ldr r3, [r3, #0]
|
|
800548e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8005492: 2b00 cmp r3, #0
|
|
8005494: d1f0 bne.n 8005478 <HAL_RCC_OscConfig+0x660>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8005496: 4b40 ldr r3, [pc, #256] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005498: 68da ldr r2, [r3, #12]
|
|
800549a: 4b40 ldr r3, [pc, #256] @ (800559c <HAL_RCC_OscConfig+0x784>)
|
|
800549c: 4013 ands r3, r2
|
|
800549e: 687a ldr r2, [r7, #4]
|
|
80054a0: 6ad1 ldr r1, [r2, #44] @ 0x2c
|
|
80054a2: 687a ldr r2, [r7, #4]
|
|
80054a4: 6b12 ldr r2, [r2, #48] @ 0x30
|
|
80054a6: 3a01 subs r2, #1
|
|
80054a8: 0112 lsls r2, r2, #4
|
|
80054aa: 4311 orrs r1, r2
|
|
80054ac: 687a ldr r2, [r7, #4]
|
|
80054ae: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
80054b0: 0212 lsls r2, r2, #8
|
|
80054b2: 4311 orrs r1, r2
|
|
80054b4: 687a ldr r2, [r7, #4]
|
|
80054b6: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
80054b8: 0852 lsrs r2, r2, #1
|
|
80054ba: 3a01 subs r2, #1
|
|
80054bc: 0552 lsls r2, r2, #21
|
|
80054be: 4311 orrs r1, r2
|
|
80054c0: 687a ldr r2, [r7, #4]
|
|
80054c2: 6c12 ldr r2, [r2, #64] @ 0x40
|
|
80054c4: 0852 lsrs r2, r2, #1
|
|
80054c6: 3a01 subs r2, #1
|
|
80054c8: 0652 lsls r2, r2, #25
|
|
80054ca: 4311 orrs r1, r2
|
|
80054cc: 687a ldr r2, [r7, #4]
|
|
80054ce: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
80054d0: 0912 lsrs r2, r2, #4
|
|
80054d2: 0452 lsls r2, r2, #17
|
|
80054d4: 430a orrs r2, r1
|
|
80054d6: 4930 ldr r1, [pc, #192] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
80054d8: 4313 orrs r3, r2
|
|
80054da: 60cb str r3, [r1, #12]
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
#endif
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80054dc: 4b2e ldr r3, [pc, #184] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
80054de: 681b ldr r3, [r3, #0]
|
|
80054e0: 4a2d ldr r2, [pc, #180] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
80054e2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
80054e6: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
80054e8: 4b2b ldr r3, [pc, #172] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
80054ea: 68db ldr r3, [r3, #12]
|
|
80054ec: 4a2a ldr r2, [pc, #168] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
80054ee: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
80054f2: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80054f4: f7fd fea4 bl 8003240 <HAL_GetTick>
|
|
80054f8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80054fa: e008 b.n 800550e <HAL_RCC_OscConfig+0x6f6>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80054fc: f7fd fea0 bl 8003240 <HAL_GetTick>
|
|
8005500: 4602 mov r2, r0
|
|
8005502: 693b ldr r3, [r7, #16]
|
|
8005504: 1ad3 subs r3, r2, r3
|
|
8005506: 2b02 cmp r3, #2
|
|
8005508: d901 bls.n 800550e <HAL_RCC_OscConfig+0x6f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800550a: 2303 movs r3, #3
|
|
800550c: e058 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800550e: 4b22 ldr r3, [pc, #136] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005510: 681b ldr r3, [r3, #0]
|
|
8005512: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8005516: 2b00 cmp r3, #0
|
|
8005518: d0f0 beq.n 80054fc <HAL_RCC_OscConfig+0x6e4>
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
800551a: e050 b.n 80055be <HAL_RCC_OscConfig+0x7a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
800551c: 2301 movs r3, #1
|
|
800551e: e04f b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
else
|
|
{
|
|
/* PLL configuration is unchanged */
|
|
/* Re-enable PLL if it was disabled (ie. low power mode) */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8005520: 4b1d ldr r3, [pc, #116] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005522: 681b ldr r3, [r3, #0]
|
|
8005524: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8005528: 2b00 cmp r3, #0
|
|
800552a: d148 bne.n 80055be <HAL_RCC_OscConfig+0x7a6>
|
|
{
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
800552c: 4b1a ldr r3, [pc, #104] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800552e: 681b ldr r3, [r3, #0]
|
|
8005530: 4a19 ldr r2, [pc, #100] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005532: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8005536: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
8005538: 4b17 ldr r3, [pc, #92] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800553a: 68db ldr r3, [r3, #12]
|
|
800553c: 4a16 ldr r2, [pc, #88] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
800553e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8005542: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005544: f7fd fe7c bl 8003240 <HAL_GetTick>
|
|
8005548: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800554a: e008 b.n 800555e <HAL_RCC_OscConfig+0x746>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800554c: f7fd fe78 bl 8003240 <HAL_GetTick>
|
|
8005550: 4602 mov r2, r0
|
|
8005552: 693b ldr r3, [r7, #16]
|
|
8005554: 1ad3 subs r3, r2, r3
|
|
8005556: 2b02 cmp r3, #2
|
|
8005558: d901 bls.n 800555e <HAL_RCC_OscConfig+0x746>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800555a: 2303 movs r3, #3
|
|
800555c: e030 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800555e: 4b0e ldr r3, [pc, #56] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005560: 681b ldr r3, [r3, #0]
|
|
8005562: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8005566: 2b00 cmp r3, #0
|
|
8005568: d0f0 beq.n 800554c <HAL_RCC_OscConfig+0x734>
|
|
800556a: e028 b.n 80055be <HAL_RCC_OscConfig+0x7a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check that PLL is not used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
800556c: 69bb ldr r3, [r7, #24]
|
|
800556e: 2b0c cmp r3, #12
|
|
8005570: d023 beq.n 80055ba <HAL_RCC_OscConfig+0x7a2>
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8005572: 4b09 ldr r3, [pc, #36] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005574: 681b ldr r3, [r3, #0]
|
|
8005576: 4a08 ldr r2, [pc, #32] @ (8005598 <HAL_RCC_OscConfig+0x780>)
|
|
8005578: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800557c: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800557e: f7fd fe5f bl 8003240 <HAL_GetTick>
|
|
8005582: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8005584: e00c b.n 80055a0 <HAL_RCC_OscConfig+0x788>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8005586: f7fd fe5b bl 8003240 <HAL_GetTick>
|
|
800558a: 4602 mov r2, r0
|
|
800558c: 693b ldr r3, [r7, #16]
|
|
800558e: 1ad3 subs r3, r2, r3
|
|
8005590: 2b02 cmp r3, #2
|
|
8005592: d905 bls.n 80055a0 <HAL_RCC_OscConfig+0x788>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005594: 2303 movs r3, #3
|
|
8005596: e013 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
8005598: 40021000 .word 0x40021000
|
|
800559c: f99d808c .word 0xf99d808c
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
80055a0: 4b09 ldr r3, [pc, #36] @ (80055c8 <HAL_RCC_OscConfig+0x7b0>)
|
|
80055a2: 681b ldr r3, [r3, #0]
|
|
80055a4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80055a8: 2b00 cmp r3, #0
|
|
80055aa: d1ec bne.n 8005586 <HAL_RCC_OscConfig+0x76e>
|
|
}
|
|
}
|
|
/* Unselect main PLL clock source and disable main PLL outputs to save power */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
|
|
80055ac: 4b06 ldr r3, [pc, #24] @ (80055c8 <HAL_RCC_OscConfig+0x7b0>)
|
|
80055ae: 68da ldr r2, [r3, #12]
|
|
80055b0: 4905 ldr r1, [pc, #20] @ (80055c8 <HAL_RCC_OscConfig+0x7b0>)
|
|
80055b2: 4b06 ldr r3, [pc, #24] @ (80055cc <HAL_RCC_OscConfig+0x7b4>)
|
|
80055b4: 4013 ands r3, r2
|
|
80055b6: 60cb str r3, [r1, #12]
|
|
80055b8: e001 b.n 80055be <HAL_RCC_OscConfig+0x7a6>
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
80055ba: 2301 movs r3, #1
|
|
80055bc: e000 b.n 80055c0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80055be: 2300 movs r3, #0
|
|
}
|
|
80055c0: 4618 mov r0, r3
|
|
80055c2: 3720 adds r7, #32
|
|
80055c4: 46bd mov sp, r7
|
|
80055c6: bd80 pop {r7, pc}
|
|
80055c8: 40021000 .word 0x40021000
|
|
80055cc: feeefffc .word 0xfeeefffc
|
|
|
|
080055d0 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
80055d0: b580 push {r7, lr}
|
|
80055d2: b084 sub sp, #16
|
|
80055d4: af00 add r7, sp, #0
|
|
80055d6: 6078 str r0, [r7, #4]
|
|
80055d8: 6039 str r1, [r7, #0]
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
|
#endif
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
80055da: 687b ldr r3, [r7, #4]
|
|
80055dc: 2b00 cmp r3, #0
|
|
80055de: d101 bne.n 80055e4 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80055e0: 2301 movs r3, #1
|
|
80055e2: e0e7 b.n 80057b4 <HAL_RCC_ClockConfig+0x1e4>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80055e4: 4b75 ldr r3, [pc, #468] @ (80057bc <HAL_RCC_ClockConfig+0x1ec>)
|
|
80055e6: 681b ldr r3, [r3, #0]
|
|
80055e8: f003 0307 and.w r3, r3, #7
|
|
80055ec: 683a ldr r2, [r7, #0]
|
|
80055ee: 429a cmp r2, r3
|
|
80055f0: d910 bls.n 8005614 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80055f2: 4b72 ldr r3, [pc, #456] @ (80057bc <HAL_RCC_ClockConfig+0x1ec>)
|
|
80055f4: 681b ldr r3, [r3, #0]
|
|
80055f6: f023 0207 bic.w r2, r3, #7
|
|
80055fa: 4970 ldr r1, [pc, #448] @ (80057bc <HAL_RCC_ClockConfig+0x1ec>)
|
|
80055fc: 683b ldr r3, [r7, #0]
|
|
80055fe: 4313 orrs r3, r2
|
|
8005600: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8005602: 4b6e ldr r3, [pc, #440] @ (80057bc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8005604: 681b ldr r3, [r3, #0]
|
|
8005606: f003 0307 and.w r3, r3, #7
|
|
800560a: 683a ldr r2, [r7, #0]
|
|
800560c: 429a cmp r2, r3
|
|
800560e: d001 beq.n 8005614 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8005610: 2301 movs r3, #1
|
|
8005612: e0cf b.n 80057b4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
|
|
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
|
|
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8005614: 687b ldr r3, [r7, #4]
|
|
8005616: 681b ldr r3, [r3, #0]
|
|
8005618: f003 0302 and.w r3, r3, #2
|
|
800561c: 2b00 cmp r3, #0
|
|
800561e: d010 beq.n 8005642 <HAL_RCC_ClockConfig+0x72>
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
|
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
8005620: 687b ldr r3, [r7, #4]
|
|
8005622: 689a ldr r2, [r3, #8]
|
|
8005624: 4b66 ldr r3, [pc, #408] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005626: 689b ldr r3, [r3, #8]
|
|
8005628: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
800562c: 429a cmp r2, r3
|
|
800562e: d908 bls.n 8005642 <HAL_RCC_ClockConfig+0x72>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8005630: 4b63 ldr r3, [pc, #396] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005632: 689b ldr r3, [r3, #8]
|
|
8005634: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8005638: 687b ldr r3, [r7, #4]
|
|
800563a: 689b ldr r3, [r3, #8]
|
|
800563c: 4960 ldr r1, [pc, #384] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800563e: 4313 orrs r3, r2
|
|
8005640: 608b str r3, [r1, #8]
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8005642: 687b ldr r3, [r7, #4]
|
|
8005644: 681b ldr r3, [r3, #0]
|
|
8005646: f003 0301 and.w r3, r3, #1
|
|
800564a: 2b00 cmp r3, #0
|
|
800564c: d04c beq.n 80056e8 <HAL_RCC_ClockConfig+0x118>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
800564e: 687b ldr r3, [r7, #4]
|
|
8005650: 685b ldr r3, [r3, #4]
|
|
8005652: 2b03 cmp r3, #3
|
|
8005654: d107 bne.n 8005666 <HAL_RCC_ClockConfig+0x96>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8005656: 4b5a ldr r3, [pc, #360] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005658: 681b ldr r3, [r3, #0]
|
|
800565a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800565e: 2b00 cmp r3, #0
|
|
8005660: d121 bne.n 80056a6 <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
8005662: 2301 movs r3, #1
|
|
8005664: e0a6 b.n 80057b4 <HAL_RCC_ClockConfig+0x1e4>
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8005666: 687b ldr r3, [r7, #4]
|
|
8005668: 685b ldr r3, [r3, #4]
|
|
800566a: 2b02 cmp r3, #2
|
|
800566c: d107 bne.n 800567e <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
800566e: 4b54 ldr r3, [pc, #336] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005670: 681b ldr r3, [r3, #0]
|
|
8005672: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005676: 2b00 cmp r3, #0
|
|
8005678: d115 bne.n 80056a6 <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
800567a: 2301 movs r3, #1
|
|
800567c: e09a b.n 80057b4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
800567e: 687b ldr r3, [r7, #4]
|
|
8005680: 685b ldr r3, [r3, #4]
|
|
8005682: 2b00 cmp r3, #0
|
|
8005684: d107 bne.n 8005696 <HAL_RCC_ClockConfig+0xc6>
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8005686: 4b4e ldr r3, [pc, #312] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005688: 681b ldr r3, [r3, #0]
|
|
800568a: f003 0302 and.w r3, r3, #2
|
|
800568e: 2b00 cmp r3, #0
|
|
8005690: d109 bne.n 80056a6 <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
8005692: 2301 movs r3, #1
|
|
8005694: e08e b.n 80057b4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8005696: 4b4a ldr r3, [pc, #296] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005698: 681b ldr r3, [r3, #0]
|
|
800569a: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800569e: 2b00 cmp r3, #0
|
|
80056a0: d101 bne.n 80056a6 <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80056a2: 2301 movs r3, #1
|
|
80056a4: e086 b.n 80057b4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
80056a6: 4b46 ldr r3, [pc, #280] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80056a8: 689b ldr r3, [r3, #8]
|
|
80056aa: f023 0203 bic.w r2, r3, #3
|
|
80056ae: 687b ldr r3, [r7, #4]
|
|
80056b0: 685b ldr r3, [r3, #4]
|
|
80056b2: 4943 ldr r1, [pc, #268] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80056b4: 4313 orrs r3, r2
|
|
80056b6: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80056b8: f7fd fdc2 bl 8003240 <HAL_GetTick>
|
|
80056bc: 60f8 str r0, [r7, #12]
|
|
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80056be: e00a b.n 80056d6 <HAL_RCC_ClockConfig+0x106>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80056c0: f7fd fdbe bl 8003240 <HAL_GetTick>
|
|
80056c4: 4602 mov r2, r0
|
|
80056c6: 68fb ldr r3, [r7, #12]
|
|
80056c8: 1ad3 subs r3, r2, r3
|
|
80056ca: f241 3288 movw r2, #5000 @ 0x1388
|
|
80056ce: 4293 cmp r3, r2
|
|
80056d0: d901 bls.n 80056d6 <HAL_RCC_ClockConfig+0x106>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80056d2: 2303 movs r3, #3
|
|
80056d4: e06e b.n 80057b4 <HAL_RCC_ClockConfig+0x1e4>
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80056d6: 4b3a ldr r3, [pc, #232] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80056d8: 689b ldr r3, [r3, #8]
|
|
80056da: f003 020c and.w r2, r3, #12
|
|
80056de: 687b ldr r3, [r7, #4]
|
|
80056e0: 685b ldr r3, [r3, #4]
|
|
80056e2: 009b lsls r3, r3, #2
|
|
80056e4: 429a cmp r2, r3
|
|
80056e6: d1eb bne.n 80056c0 <HAL_RCC_ClockConfig+0xf0>
|
|
}
|
|
#endif
|
|
|
|
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
|
|
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
80056e8: 687b ldr r3, [r7, #4]
|
|
80056ea: 681b ldr r3, [r3, #0]
|
|
80056ec: f003 0302 and.w r3, r3, #2
|
|
80056f0: 2b00 cmp r3, #0
|
|
80056f2: d010 beq.n 8005716 <HAL_RCC_ClockConfig+0x146>
|
|
{
|
|
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
80056f4: 687b ldr r3, [r7, #4]
|
|
80056f6: 689a ldr r2, [r3, #8]
|
|
80056f8: 4b31 ldr r3, [pc, #196] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80056fa: 689b ldr r3, [r3, #8]
|
|
80056fc: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8005700: 429a cmp r2, r3
|
|
8005702: d208 bcs.n 8005716 <HAL_RCC_ClockConfig+0x146>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8005704: 4b2e ldr r3, [pc, #184] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005706: 689b ldr r3, [r3, #8]
|
|
8005708: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
800570c: 687b ldr r3, [r7, #4]
|
|
800570e: 689b ldr r3, [r3, #8]
|
|
8005710: 492b ldr r1, [pc, #172] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005712: 4313 orrs r3, r2
|
|
8005714: 608b str r3, [r1, #8]
|
|
}
|
|
}
|
|
|
|
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8005716: 4b29 ldr r3, [pc, #164] @ (80057bc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8005718: 681b ldr r3, [r3, #0]
|
|
800571a: f003 0307 and.w r3, r3, #7
|
|
800571e: 683a ldr r2, [r7, #0]
|
|
8005720: 429a cmp r2, r3
|
|
8005722: d210 bcs.n 8005746 <HAL_RCC_ClockConfig+0x176>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8005724: 4b25 ldr r3, [pc, #148] @ (80057bc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8005726: 681b ldr r3, [r3, #0]
|
|
8005728: f023 0207 bic.w r2, r3, #7
|
|
800572c: 4923 ldr r1, [pc, #140] @ (80057bc <HAL_RCC_ClockConfig+0x1ec>)
|
|
800572e: 683b ldr r3, [r7, #0]
|
|
8005730: 4313 orrs r3, r2
|
|
8005732: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8005734: 4b21 ldr r3, [pc, #132] @ (80057bc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8005736: 681b ldr r3, [r3, #0]
|
|
8005738: f003 0307 and.w r3, r3, #7
|
|
800573c: 683a ldr r2, [r7, #0]
|
|
800573e: 429a cmp r2, r3
|
|
8005740: d001 beq.n 8005746 <HAL_RCC_ClockConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
8005742: 2301 movs r3, #1
|
|
8005744: e036 b.n 80057b4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8005746: 687b ldr r3, [r7, #4]
|
|
8005748: 681b ldr r3, [r3, #0]
|
|
800574a: f003 0304 and.w r3, r3, #4
|
|
800574e: 2b00 cmp r3, #0
|
|
8005750: d008 beq.n 8005764 <HAL_RCC_ClockConfig+0x194>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8005752: 4b1b ldr r3, [pc, #108] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005754: 689b ldr r3, [r3, #8]
|
|
8005756: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
800575a: 687b ldr r3, [r7, #4]
|
|
800575c: 68db ldr r3, [r3, #12]
|
|
800575e: 4918 ldr r1, [pc, #96] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005760: 4313 orrs r3, r2
|
|
8005762: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8005764: 687b ldr r3, [r7, #4]
|
|
8005766: 681b ldr r3, [r3, #0]
|
|
8005768: f003 0308 and.w r3, r3, #8
|
|
800576c: 2b00 cmp r3, #0
|
|
800576e: d009 beq.n 8005784 <HAL_RCC_ClockConfig+0x1b4>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8005770: 4b13 ldr r3, [pc, #76] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005772: 689b ldr r3, [r3, #8]
|
|
8005774: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
8005778: 687b ldr r3, [r7, #4]
|
|
800577a: 691b ldr r3, [r3, #16]
|
|
800577c: 00db lsls r3, r3, #3
|
|
800577e: 4910 ldr r1, [pc, #64] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8005780: 4313 orrs r3, r2
|
|
8005782: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8005784: f000 f824 bl 80057d0 <HAL_RCC_GetSysClockFreq>
|
|
8005788: 4602 mov r2, r0
|
|
800578a: 4b0d ldr r3, [pc, #52] @ (80057c0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800578c: 689b ldr r3, [r3, #8]
|
|
800578e: 091b lsrs r3, r3, #4
|
|
8005790: f003 030f and.w r3, r3, #15
|
|
8005794: 490b ldr r1, [pc, #44] @ (80057c4 <HAL_RCC_ClockConfig+0x1f4>)
|
|
8005796: 5ccb ldrb r3, [r1, r3]
|
|
8005798: f003 031f and.w r3, r3, #31
|
|
800579c: fa22 f303 lsr.w r3, r2, r3
|
|
80057a0: 4a09 ldr r2, [pc, #36] @ (80057c8 <HAL_RCC_ClockConfig+0x1f8>)
|
|
80057a2: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
80057a4: 4b09 ldr r3, [pc, #36] @ (80057cc <HAL_RCC_ClockConfig+0x1fc>)
|
|
80057a6: 681b ldr r3, [r3, #0]
|
|
80057a8: 4618 mov r0, r3
|
|
80057aa: f7fd fcf9 bl 80031a0 <HAL_InitTick>
|
|
80057ae: 4603 mov r3, r0
|
|
80057b0: 72fb strb r3, [r7, #11]
|
|
|
|
return status;
|
|
80057b2: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
80057b4: 4618 mov r0, r3
|
|
80057b6: 3710 adds r7, #16
|
|
80057b8: 46bd mov sp, r7
|
|
80057ba: bd80 pop {r7, pc}
|
|
80057bc: 40022000 .word 0x40022000
|
|
80057c0: 40021000 .word 0x40021000
|
|
80057c4: 0800a0d8 .word 0x0800a0d8
|
|
80057c8: 200000c4 .word 0x200000c4
|
|
80057cc: 200000c8 .word 0x200000c8
|
|
|
|
080057d0 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80057d0: b480 push {r7}
|
|
80057d2: b089 sub sp, #36 @ 0x24
|
|
80057d4: af00 add r7, sp, #0
|
|
uint32_t msirange = 0U, sysclockfreq = 0U;
|
|
80057d6: 2300 movs r3, #0
|
|
80057d8: 61fb str r3, [r7, #28]
|
|
80057da: 2300 movs r3, #0
|
|
80057dc: 61bb str r3, [r7, #24]
|
|
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
|
|
uint32_t sysclk_source, pll_oscsource;
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
80057de: 4b3e ldr r3, [pc, #248] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80057e0: 689b ldr r3, [r3, #8]
|
|
80057e2: f003 030c and.w r3, r3, #12
|
|
80057e6: 613b str r3, [r7, #16]
|
|
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
80057e8: 4b3b ldr r3, [pc, #236] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80057ea: 68db ldr r3, [r3, #12]
|
|
80057ec: f003 0303 and.w r3, r3, #3
|
|
80057f0: 60fb str r3, [r7, #12]
|
|
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
80057f2: 693b ldr r3, [r7, #16]
|
|
80057f4: 2b00 cmp r3, #0
|
|
80057f6: d005 beq.n 8005804 <HAL_RCC_GetSysClockFreq+0x34>
|
|
80057f8: 693b ldr r3, [r7, #16]
|
|
80057fa: 2b0c cmp r3, #12
|
|
80057fc: d121 bne.n 8005842 <HAL_RCC_GetSysClockFreq+0x72>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
|
|
80057fe: 68fb ldr r3, [r7, #12]
|
|
8005800: 2b01 cmp r3, #1
|
|
8005802: d11e bne.n 8005842 <HAL_RCC_GetSysClockFreq+0x72>
|
|
{
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
|
|
/* Get SYSCLK source */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
|
|
8005804: 4b34 ldr r3, [pc, #208] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8005806: 681b ldr r3, [r3, #0]
|
|
8005808: f003 0308 and.w r3, r3, #8
|
|
800580c: 2b00 cmp r3, #0
|
|
800580e: d107 bne.n 8005820 <HAL_RCC_GetSysClockFreq+0x50>
|
|
{ /* MSISRANGE from RCC_CSR applies */
|
|
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
|
|
8005810: 4b31 ldr r3, [pc, #196] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8005812: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8005816: 0a1b lsrs r3, r3, #8
|
|
8005818: f003 030f and.w r3, r3, #15
|
|
800581c: 61fb str r3, [r7, #28]
|
|
800581e: e005 b.n 800582c <HAL_RCC_GetSysClockFreq+0x5c>
|
|
}
|
|
else
|
|
{ /* MSIRANGE from RCC_CR applies */
|
|
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
|
|
8005820: 4b2d ldr r3, [pc, #180] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8005822: 681b ldr r3, [r3, #0]
|
|
8005824: 091b lsrs r3, r3, #4
|
|
8005826: f003 030f and.w r3, r3, #15
|
|
800582a: 61fb str r3, [r7, #28]
|
|
}
|
|
/*MSI frequency range in HZ*/
|
|
msirange = MSIRangeTable[msirange];
|
|
800582c: 4a2b ldr r2, [pc, #172] @ (80058dc <HAL_RCC_GetSysClockFreq+0x10c>)
|
|
800582e: 69fb ldr r3, [r7, #28]
|
|
8005830: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8005834: 61fb str r3, [r7, #28]
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8005836: 693b ldr r3, [r7, #16]
|
|
8005838: 2b00 cmp r3, #0
|
|
800583a: d10d bne.n 8005858 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = msirange;
|
|
800583c: 69fb ldr r3, [r7, #28]
|
|
800583e: 61bb str r3, [r7, #24]
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8005840: e00a b.n 8005858 <HAL_RCC_GetSysClockFreq+0x88>
|
|
}
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSI)
|
|
8005842: 693b ldr r3, [r7, #16]
|
|
8005844: 2b04 cmp r3, #4
|
|
8005846: d102 bne.n 800584e <HAL_RCC_GetSysClockFreq+0x7e>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
8005848: 4b25 ldr r3, [pc, #148] @ (80058e0 <HAL_RCC_GetSysClockFreq+0x110>)
|
|
800584a: 61bb str r3, [r7, #24]
|
|
800584c: e004 b.n 8005858 <HAL_RCC_GetSysClockFreq+0x88>
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSE)
|
|
800584e: 693b ldr r3, [r7, #16]
|
|
8005850: 2b08 cmp r3, #8
|
|
8005852: d101 bne.n 8005858 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
8005854: 4b23 ldr r3, [pc, #140] @ (80058e4 <HAL_RCC_GetSysClockFreq+0x114>)
|
|
8005856: 61bb str r3, [r7, #24]
|
|
else
|
|
{
|
|
/* unexpected case: sysclockfreq at 0 */
|
|
}
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_PLL)
|
|
8005858: 693b ldr r3, [r7, #16]
|
|
800585a: 2b0c cmp r3, #12
|
|
800585c: d134 bne.n 80058c8 <HAL_RCC_GetSysClockFreq+0xf8>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
800585e: 4b1e ldr r3, [pc, #120] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8005860: 68db ldr r3, [r3, #12]
|
|
8005862: f003 0303 and.w r3, r3, #3
|
|
8005866: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
8005868: 68bb ldr r3, [r7, #8]
|
|
800586a: 2b02 cmp r3, #2
|
|
800586c: d003 beq.n 8005876 <HAL_RCC_GetSysClockFreq+0xa6>
|
|
800586e: 68bb ldr r3, [r7, #8]
|
|
8005870: 2b03 cmp r3, #3
|
|
8005872: d003 beq.n 800587c <HAL_RCC_GetSysClockFreq+0xac>
|
|
8005874: e005 b.n 8005882 <HAL_RCC_GetSysClockFreq+0xb2>
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllvco = HSI_VALUE;
|
|
8005876: 4b1a ldr r3, [pc, #104] @ (80058e0 <HAL_RCC_GetSysClockFreq+0x110>)
|
|
8005878: 617b str r3, [r7, #20]
|
|
break;
|
|
800587a: e005 b.n 8005888 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = HSE_VALUE;
|
|
800587c: 4b19 ldr r3, [pc, #100] @ (80058e4 <HAL_RCC_GetSysClockFreq+0x114>)
|
|
800587e: 617b str r3, [r7, #20]
|
|
break;
|
|
8005880: e002 b.n 8005888 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllvco = msirange;
|
|
8005882: 69fb ldr r3, [r7, #28]
|
|
8005884: 617b str r3, [r7, #20]
|
|
break;
|
|
8005886: bf00 nop
|
|
}
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8005888: 4b13 ldr r3, [pc, #76] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
800588a: 68db ldr r3, [r3, #12]
|
|
800588c: 091b lsrs r3, r3, #4
|
|
800588e: f003 0307 and.w r3, r3, #7
|
|
8005892: 3301 adds r3, #1
|
|
8005894: 607b str r3, [r7, #4]
|
|
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
|
|
8005896: 4b10 ldr r3, [pc, #64] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8005898: 68db ldr r3, [r3, #12]
|
|
800589a: 0a1b lsrs r3, r3, #8
|
|
800589c: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80058a0: 697a ldr r2, [r7, #20]
|
|
80058a2: fb03 f202 mul.w r2, r3, r2
|
|
80058a6: 687b ldr r3, [r7, #4]
|
|
80058a8: fbb2 f3f3 udiv r3, r2, r3
|
|
80058ac: 617b str r3, [r7, #20]
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
80058ae: 4b0a ldr r3, [pc, #40] @ (80058d8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80058b0: 68db ldr r3, [r3, #12]
|
|
80058b2: 0e5b lsrs r3, r3, #25
|
|
80058b4: f003 0303 and.w r3, r3, #3
|
|
80058b8: 3301 adds r3, #1
|
|
80058ba: 005b lsls r3, r3, #1
|
|
80058bc: 603b str r3, [r7, #0]
|
|
sysclockfreq = pllvco / pllr;
|
|
80058be: 697a ldr r2, [r7, #20]
|
|
80058c0: 683b ldr r3, [r7, #0]
|
|
80058c2: fbb2 f3f3 udiv r3, r2, r3
|
|
80058c6: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
80058c8: 69bb ldr r3, [r7, #24]
|
|
}
|
|
80058ca: 4618 mov r0, r3
|
|
80058cc: 3724 adds r7, #36 @ 0x24
|
|
80058ce: 46bd mov sp, r7
|
|
80058d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80058d4: 4770 bx lr
|
|
80058d6: bf00 nop
|
|
80058d8: 40021000 .word 0x40021000
|
|
80058dc: 0800a0f0 .word 0x0800a0f0
|
|
80058e0: 00f42400 .word 0x00f42400
|
|
80058e4: 007a1200 .word 0x007a1200
|
|
|
|
080058e8 <HAL_RCC_GetHCLKFreq>:
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
80058e8: b480 push {r7}
|
|
80058ea: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
80058ec: 4b03 ldr r3, [pc, #12] @ (80058fc <HAL_RCC_GetHCLKFreq+0x14>)
|
|
80058ee: 681b ldr r3, [r3, #0]
|
|
}
|
|
80058f0: 4618 mov r0, r3
|
|
80058f2: 46bd mov sp, r7
|
|
80058f4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80058f8: 4770 bx lr
|
|
80058fa: bf00 nop
|
|
80058fc: 200000c4 .word 0x200000c4
|
|
|
|
08005900 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8005900: b580 push {r7, lr}
|
|
8005902: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
|
8005904: f7ff fff0 bl 80058e8 <HAL_RCC_GetHCLKFreq>
|
|
8005908: 4602 mov r2, r0
|
|
800590a: 4b06 ldr r3, [pc, #24] @ (8005924 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
800590c: 689b ldr r3, [r3, #8]
|
|
800590e: 0a1b lsrs r3, r3, #8
|
|
8005910: f003 0307 and.w r3, r3, #7
|
|
8005914: 4904 ldr r1, [pc, #16] @ (8005928 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|
8005916: 5ccb ldrb r3, [r1, r3]
|
|
8005918: f003 031f and.w r3, r3, #31
|
|
800591c: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8005920: 4618 mov r0, r3
|
|
8005922: bd80 pop {r7, pc}
|
|
8005924: 40021000 .word 0x40021000
|
|
8005928: 0800a0e8 .word 0x0800a0e8
|
|
|
|
0800592c <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
800592c: b580 push {r7, lr}
|
|
800592e: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
|
8005930: f7ff ffda bl 80058e8 <HAL_RCC_GetHCLKFreq>
|
|
8005934: 4602 mov r2, r0
|
|
8005936: 4b06 ldr r3, [pc, #24] @ (8005950 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
8005938: 689b ldr r3, [r3, #8]
|
|
800593a: 0adb lsrs r3, r3, #11
|
|
800593c: f003 0307 and.w r3, r3, #7
|
|
8005940: 4904 ldr r1, [pc, #16] @ (8005954 <HAL_RCC_GetPCLK2Freq+0x28>)
|
|
8005942: 5ccb ldrb r3, [r1, r3]
|
|
8005944: f003 031f and.w r3, r3, #31
|
|
8005948: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
800594c: 4618 mov r0, r3
|
|
800594e: bd80 pop {r7, pc}
|
|
8005950: 40021000 .word 0x40021000
|
|
8005954: 0800a0e8 .word 0x0800a0e8
|
|
|
|
08005958 <RCC_SetFlashLatencyFromMSIRange>:
|
|
voltage range.
|
|
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
|
{
|
|
8005958: b580 push {r7, lr}
|
|
800595a: b086 sub sp, #24
|
|
800595c: af00 add r7, sp, #0
|
|
800595e: 6078 str r0, [r7, #4]
|
|
uint32_t vos;
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
8005960: 2300 movs r3, #0
|
|
8005962: 613b str r3, [r7, #16]
|
|
|
|
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
|
8005964: 4b2a ldr r3, [pc, #168] @ (8005a10 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8005966: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005968: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800596c: 2b00 cmp r3, #0
|
|
800596e: d003 beq.n 8005978 <RCC_SetFlashLatencyFromMSIRange+0x20>
|
|
{
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
8005970: f7ff f922 bl 8004bb8 <HAL_PWREx_GetVoltageRange>
|
|
8005974: 6178 str r0, [r7, #20]
|
|
8005976: e014 b.n 80059a2 <RCC_SetFlashLatencyFromMSIRange+0x4a>
|
|
}
|
|
else
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8005978: 4b25 ldr r3, [pc, #148] @ (8005a10 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
800597a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800597c: 4a24 ldr r2, [pc, #144] @ (8005a10 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
800597e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005982: 6593 str r3, [r2, #88] @ 0x58
|
|
8005984: 4b22 ldr r3, [pc, #136] @ (8005a10 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8005986: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005988: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800598c: 60fb str r3, [r7, #12]
|
|
800598e: 68fb ldr r3, [r7, #12]
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
8005990: f7ff f912 bl 8004bb8 <HAL_PWREx_GetVoltageRange>
|
|
8005994: 6178 str r0, [r7, #20]
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8005996: 4b1e ldr r3, [pc, #120] @ (8005a10 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8005998: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800599a: 4a1d ldr r2, [pc, #116] @ (8005a10 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
800599c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80059a0: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
|
|
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
80059a2: 697b ldr r3, [r7, #20]
|
|
80059a4: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80059a8: d10b bne.n 80059c2 <RCC_SetFlashLatencyFromMSIRange+0x6a>
|
|
{
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
80059aa: 687b ldr r3, [r7, #4]
|
|
80059ac: 2b80 cmp r3, #128 @ 0x80
|
|
80059ae: d919 bls.n 80059e4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
if(msirange > RCC_MSIRANGE_10)
|
|
80059b0: 687b ldr r3, [r7, #4]
|
|
80059b2: 2ba0 cmp r3, #160 @ 0xa0
|
|
80059b4: d902 bls.n 80059bc <RCC_SetFlashLatencyFromMSIRange+0x64>
|
|
{
|
|
/* MSI 48Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
80059b6: 2302 movs r3, #2
|
|
80059b8: 613b str r3, [r7, #16]
|
|
80059ba: e013 b.n 80059e4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else
|
|
{
|
|
/* MSI 24Mhz or 32Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
80059bc: 2301 movs r3, #1
|
|
80059be: 613b str r3, [r7, #16]
|
|
80059c0: e010 b.n 80059e4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
}
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
}
|
|
#else
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
80059c2: 687b ldr r3, [r7, #4]
|
|
80059c4: 2b80 cmp r3, #128 @ 0x80
|
|
80059c6: d902 bls.n 80059ce <RCC_SetFlashLatencyFromMSIRange+0x76>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
latency = FLASH_LATENCY_3; /* 3WS */
|
|
80059c8: 2303 movs r3, #3
|
|
80059ca: 613b str r3, [r7, #16]
|
|
80059cc: e00a b.n 80059e4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else
|
|
{
|
|
if(msirange == RCC_MSIRANGE_8)
|
|
80059ce: 687b ldr r3, [r7, #4]
|
|
80059d0: 2b80 cmp r3, #128 @ 0x80
|
|
80059d2: d102 bne.n 80059da <RCC_SetFlashLatencyFromMSIRange+0x82>
|
|
{
|
|
/* MSI 16Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
80059d4: 2302 movs r3, #2
|
|
80059d6: 613b str r3, [r7, #16]
|
|
80059d8: e004 b.n 80059e4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else if(msirange == RCC_MSIRANGE_7)
|
|
80059da: 687b ldr r3, [r7, #4]
|
|
80059dc: 2b70 cmp r3, #112 @ 0x70
|
|
80059de: d101 bne.n 80059e4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
{
|
|
/* MSI 8Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
80059e0: 2301 movs r3, #1
|
|
80059e2: 613b str r3, [r7, #16]
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
80059e4: 4b0b ldr r3, [pc, #44] @ (8005a14 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
80059e6: 681b ldr r3, [r3, #0]
|
|
80059e8: f023 0207 bic.w r2, r3, #7
|
|
80059ec: 4909 ldr r1, [pc, #36] @ (8005a14 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
80059ee: 693b ldr r3, [r7, #16]
|
|
80059f0: 4313 orrs r3, r2
|
|
80059f2: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != latency)
|
|
80059f4: 4b07 ldr r3, [pc, #28] @ (8005a14 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
80059f6: 681b ldr r3, [r3, #0]
|
|
80059f8: f003 0307 and.w r3, r3, #7
|
|
80059fc: 693a ldr r2, [r7, #16]
|
|
80059fe: 429a cmp r2, r3
|
|
8005a00: d001 beq.n 8005a06 <RCC_SetFlashLatencyFromMSIRange+0xae>
|
|
{
|
|
return HAL_ERROR;
|
|
8005a02: 2301 movs r3, #1
|
|
8005a04: e000 b.n 8005a08 <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8005a06: 2300 movs r3, #0
|
|
}
|
|
8005a08: 4618 mov r0, r3
|
|
8005a0a: 3718 adds r7, #24
|
|
8005a0c: 46bd mov sp, r7
|
|
8005a0e: bd80 pop {r7, pc}
|
|
8005a10: 40021000 .word 0x40021000
|
|
8005a14: 40022000 .word 0x40022000
|
|
|
|
08005a18 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8005a18: b580 push {r7, lr}
|
|
8005a1a: b086 sub sp, #24
|
|
8005a1c: af00 add r7, sp, #0
|
|
8005a1e: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister, tickstart; /* no init needed */
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
8005a20: 2300 movs r3, #0
|
|
8005a22: 74fb strb r3, [r7, #19]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
8005a24: 2300 movs r3, #0
|
|
8005a26: 74bb strb r3, [r7, #18]
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
#if defined(SAI1)
|
|
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
|
|
8005a28: 687b ldr r3, [r7, #4]
|
|
8005a2a: 681b ldr r3, [r3, #0]
|
|
8005a2c: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8005a30: 2b00 cmp r3, #0
|
|
8005a32: d041 beq.n 8005ab8 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai1ClockSelection)
|
|
8005a34: 687b ldr r3, [r7, #4]
|
|
8005a36: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8005a38: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
8005a3c: d02a beq.n 8005a94 <HAL_RCCEx_PeriphCLKConfig+0x7c>
|
|
8005a3e: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
8005a42: d824 bhi.n 8005a8e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
8005a44: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
8005a48: d008 beq.n 8005a5c <HAL_RCCEx_PeriphCLKConfig+0x44>
|
|
8005a4a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
8005a4e: d81e bhi.n 8005a8e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
8005a50: 2b00 cmp r3, #0
|
|
8005a52: d00a beq.n 8005a6a <HAL_RCCEx_PeriphCLKConfig+0x52>
|
|
8005a54: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8005a58: d010 beq.n 8005a7c <HAL_RCCEx_PeriphCLKConfig+0x64>
|
|
8005a5a: e018 b.n 8005a8e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
{
|
|
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
8005a5c: 4b86 ldr r3, [pc, #536] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005a5e: 68db ldr r3, [r3, #12]
|
|
8005a60: 4a85 ldr r2, [pc, #532] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005a62: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8005a66: 60d3 str r3, [r2, #12]
|
|
#else
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8005a68: e015 b.n 8005a96 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
8005a6a: 687b ldr r3, [r7, #4]
|
|
8005a6c: 3304 adds r3, #4
|
|
8005a6e: 2100 movs r1, #0
|
|
8005a70: 4618 mov r0, r3
|
|
8005a72: f000 facb bl 800600c <RCCEx_PLLSAI1_Config>
|
|
8005a76: 4603 mov r3, r0
|
|
8005a78: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8005a7a: e00c b.n 8005a96 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
8005a7c: 687b ldr r3, [r7, #4]
|
|
8005a7e: 3320 adds r3, #32
|
|
8005a80: 2100 movs r1, #0
|
|
8005a82: 4618 mov r0, r3
|
|
8005a84: f000 fbb6 bl 80061f4 <RCCEx_PLLSAI2_Config>
|
|
8005a88: 4603 mov r3, r0
|
|
8005a8a: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8005a8c: e003 b.n 8005a96 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
8005a8e: 2301 movs r3, #1
|
|
8005a90: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8005a92: e000 b.n 8005a96 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
break;
|
|
8005a94: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8005a96: 7cfb ldrb r3, [r7, #19]
|
|
8005a98: 2b00 cmp r3, #0
|
|
8005a9a: d10b bne.n 8005ab4 <HAL_RCCEx_PeriphCLKConfig+0x9c>
|
|
{
|
|
/* Set the source of SAI1 clock*/
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8005a9c: 4b76 ldr r3, [pc, #472] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005a9e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005aa2: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
8005aa6: 687b ldr r3, [r7, #4]
|
|
8005aa8: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8005aaa: 4973 ldr r1, [pc, #460] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005aac: 4313 orrs r3, r2
|
|
8005aae: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
8005ab2: e001 b.n 8005ab8 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005ab4: 7cfb ldrb r3, [r7, #19]
|
|
8005ab6: 74bb strb r3, [r7, #18]
|
|
#endif /* SAI1 */
|
|
|
|
#if defined(SAI2)
|
|
|
|
/*-------------------------- SAI2 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
|
|
8005ab8: 687b ldr r3, [r7, #4]
|
|
8005aba: 681b ldr r3, [r3, #0]
|
|
8005abc: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8005ac0: 2b00 cmp r3, #0
|
|
8005ac2: d041 beq.n 8005b48 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai2ClockSelection)
|
|
8005ac4: 687b ldr r3, [r7, #4]
|
|
8005ac6: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8005ac8: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
|
|
8005acc: d02a beq.n 8005b24 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
8005ace: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
|
|
8005ad2: d824 bhi.n 8005b1e <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
8005ad4: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
8005ad8: d008 beq.n 8005aec <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
|
8005ada: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
8005ade: d81e bhi.n 8005b1e <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
8005ae0: 2b00 cmp r3, #0
|
|
8005ae2: d00a beq.n 8005afa <HAL_RCCEx_PeriphCLKConfig+0xe2>
|
|
8005ae4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8005ae8: d010 beq.n 8005b0c <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
8005aea: e018 b.n 8005b1e <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
{
|
|
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
8005aec: 4b62 ldr r3, [pc, #392] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005aee: 68db ldr r3, [r3, #12]
|
|
8005af0: 4a61 ldr r2, [pc, #388] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005af2: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8005af6: 60d3 str r3, [r2, #12]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8005af8: e015 b.n 8005b26 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
8005afa: 687b ldr r3, [r7, #4]
|
|
8005afc: 3304 adds r3, #4
|
|
8005afe: 2100 movs r1, #0
|
|
8005b00: 4618 mov r0, r3
|
|
8005b02: f000 fa83 bl 800600c <RCCEx_PLLSAI1_Config>
|
|
8005b06: 4603 mov r3, r0
|
|
8005b08: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8005b0a: e00c b.n 8005b26 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
8005b0c: 687b ldr r3, [r7, #4]
|
|
8005b0e: 3320 adds r3, #32
|
|
8005b10: 2100 movs r1, #0
|
|
8005b12: 4618 mov r0, r3
|
|
8005b14: f000 fb6e bl 80061f4 <RCCEx_PLLSAI2_Config>
|
|
8005b18: 4603 mov r3, r0
|
|
8005b1a: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8005b1c: e003 b.n 8005b26 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
8005b1e: 2301 movs r3, #1
|
|
8005b20: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8005b22: e000 b.n 8005b26 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
break;
|
|
8005b24: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8005b26: 7cfb ldrb r3, [r7, #19]
|
|
8005b28: 2b00 cmp r3, #0
|
|
8005b2a: d10b bne.n 8005b44 <HAL_RCCEx_PeriphCLKConfig+0x12c>
|
|
{
|
|
/* Set the source of SAI2 clock*/
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
8005b2c: 4b52 ldr r3, [pc, #328] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005b2e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005b32: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
|
|
8005b36: 687b ldr r3, [r7, #4]
|
|
8005b38: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8005b3a: 494f ldr r1, [pc, #316] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005b3c: 4313 orrs r3, r2
|
|
8005b3e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
8005b42: e001 b.n 8005b48 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005b44: 7cfb ldrb r3, [r7, #19]
|
|
8005b46: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
#endif /* SAI2 */
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
8005b48: 687b ldr r3, [r7, #4]
|
|
8005b4a: 681b ldr r3, [r3, #0]
|
|
8005b4c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005b50: 2b00 cmp r3, #0
|
|
8005b52: f000 80a0 beq.w 8005c96 <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8005b56: 2300 movs r3, #0
|
|
8005b58: 747b strb r3, [r7, #17]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
8005b5a: 4b47 ldr r3, [pc, #284] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005b5c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005b5e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005b62: 2b00 cmp r3, #0
|
|
8005b64: d101 bne.n 8005b6a <HAL_RCCEx_PeriphCLKConfig+0x152>
|
|
8005b66: 2301 movs r3, #1
|
|
8005b68: e000 b.n 8005b6c <HAL_RCCEx_PeriphCLKConfig+0x154>
|
|
8005b6a: 2300 movs r3, #0
|
|
8005b6c: 2b00 cmp r3, #0
|
|
8005b6e: d00d beq.n 8005b8c <HAL_RCCEx_PeriphCLKConfig+0x174>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8005b70: 4b41 ldr r3, [pc, #260] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005b72: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005b74: 4a40 ldr r2, [pc, #256] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005b76: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005b7a: 6593 str r3, [r2, #88] @ 0x58
|
|
8005b7c: 4b3e ldr r3, [pc, #248] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005b7e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005b80: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005b84: 60bb str r3, [r7, #8]
|
|
8005b86: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8005b88: 2301 movs r3, #1
|
|
8005b8a: 747b strb r3, [r7, #17]
|
|
}
|
|
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8005b8c: 4b3b ldr r3, [pc, #236] @ (8005c7c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
8005b8e: 681b ldr r3, [r3, #0]
|
|
8005b90: 4a3a ldr r2, [pc, #232] @ (8005c7c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
8005b92: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8005b96: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8005b98: f7fd fb52 bl 8003240 <HAL_GetTick>
|
|
8005b9c: 60f8 str r0, [r7, #12]
|
|
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
8005b9e: e009 b.n 8005bb4 <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8005ba0: f7fd fb4e bl 8003240 <HAL_GetTick>
|
|
8005ba4: 4602 mov r2, r0
|
|
8005ba6: 68fb ldr r3, [r7, #12]
|
|
8005ba8: 1ad3 subs r3, r2, r3
|
|
8005baa: 2b02 cmp r3, #2
|
|
8005bac: d902 bls.n 8005bb4 <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8005bae: 2303 movs r3, #3
|
|
8005bb0: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8005bb2: e005 b.n 8005bc0 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
8005bb4: 4b31 ldr r3, [pc, #196] @ (8005c7c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
8005bb6: 681b ldr r3, [r3, #0]
|
|
8005bb8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005bbc: 2b00 cmp r3, #0
|
|
8005bbe: d0ef beq.n 8005ba0 <HAL_RCCEx_PeriphCLKConfig+0x188>
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8005bc0: 7cfb ldrb r3, [r7, #19]
|
|
8005bc2: 2b00 cmp r3, #0
|
|
8005bc4: d15c bne.n 8005c80 <HAL_RCCEx_PeriphCLKConfig+0x268>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
8005bc6: 4b2c ldr r3, [pc, #176] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005bc8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005bcc: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8005bd0: 617b str r3, [r7, #20]
|
|
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
8005bd2: 697b ldr r3, [r7, #20]
|
|
8005bd4: 2b00 cmp r3, #0
|
|
8005bd6: d01f beq.n 8005c18 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
|
8005bd8: 687b ldr r3, [r7, #4]
|
|
8005bda: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8005bde: 697a ldr r2, [r7, #20]
|
|
8005be0: 429a cmp r2, r3
|
|
8005be2: d019 beq.n 8005c18 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
8005be4: 4b24 ldr r3, [pc, #144] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005be6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005bea: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8005bee: 617b str r3, [r7, #20]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8005bf0: 4b21 ldr r3, [pc, #132] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005bf2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005bf6: 4a20 ldr r2, [pc, #128] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005bf8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8005bfc: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8005c00: 4b1d ldr r3, [pc, #116] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005c02: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005c06: 4a1c ldr r2, [pc, #112] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005c08: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8005c0c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
8005c10: 4a19 ldr r2, [pc, #100] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005c12: 697b ldr r3, [r7, #20]
|
|
8005c14: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
8005c18: 697b ldr r3, [r7, #20]
|
|
8005c1a: f003 0301 and.w r3, r3, #1
|
|
8005c1e: 2b00 cmp r3, #0
|
|
8005c20: d016 beq.n 8005c50 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005c22: f7fd fb0d bl 8003240 <HAL_GetTick>
|
|
8005c26: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8005c28: e00b b.n 8005c42 <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005c2a: f7fd fb09 bl 8003240 <HAL_GetTick>
|
|
8005c2e: 4602 mov r2, r0
|
|
8005c30: 68fb ldr r3, [r7, #12]
|
|
8005c32: 1ad3 subs r3, r2, r3
|
|
8005c34: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005c38: 4293 cmp r3, r2
|
|
8005c3a: d902 bls.n 8005c42 <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8005c3c: 2303 movs r3, #3
|
|
8005c3e: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8005c40: e006 b.n 8005c50 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8005c42: 4b0d ldr r3, [pc, #52] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005c44: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005c48: f003 0302 and.w r3, r3, #2
|
|
8005c4c: 2b00 cmp r3, #0
|
|
8005c4e: d0ec beq.n 8005c2a <HAL_RCCEx_PeriphCLKConfig+0x212>
|
|
}
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8005c50: 7cfb ldrb r3, [r7, #19]
|
|
8005c52: 2b00 cmp r3, #0
|
|
8005c54: d10c bne.n 8005c70 <HAL_RCCEx_PeriphCLKConfig+0x258>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8005c56: 4b08 ldr r3, [pc, #32] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005c58: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005c5c: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8005c60: 687b ldr r3, [r7, #4]
|
|
8005c62: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8005c66: 4904 ldr r1, [pc, #16] @ (8005c78 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8005c68: 4313 orrs r3, r2
|
|
8005c6a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
8005c6e: e009 b.n 8005c84 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005c70: 7cfb ldrb r3, [r7, #19]
|
|
8005c72: 74bb strb r3, [r7, #18]
|
|
8005c74: e006 b.n 8005c84 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
8005c76: bf00 nop
|
|
8005c78: 40021000 .word 0x40021000
|
|
8005c7c: 40007000 .word 0x40007000
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005c80: 7cfb ldrb r3, [r7, #19]
|
|
8005c82: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
8005c84: 7c7b ldrb r3, [r7, #17]
|
|
8005c86: 2b01 cmp r3, #1
|
|
8005c88: d105 bne.n 8005c96 <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8005c8a: 4b9e ldr r3, [pc, #632] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005c8c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005c8e: 4a9d ldr r2, [pc, #628] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005c90: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8005c94: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
8005c96: 687b ldr r3, [r7, #4]
|
|
8005c98: 681b ldr r3, [r3, #0]
|
|
8005c9a: f003 0301 and.w r3, r3, #1
|
|
8005c9e: 2b00 cmp r3, #0
|
|
8005ca0: d00a beq.n 8005cb8 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
8005ca2: 4b98 ldr r3, [pc, #608] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005ca4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005ca8: f023 0203 bic.w r2, r3, #3
|
|
8005cac: 687b ldr r3, [r7, #4]
|
|
8005cae: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005cb0: 4994 ldr r1, [pc, #592] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005cb2: 4313 orrs r3, r2
|
|
8005cb4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
8005cb8: 687b ldr r3, [r7, #4]
|
|
8005cba: 681b ldr r3, [r3, #0]
|
|
8005cbc: f003 0302 and.w r3, r3, #2
|
|
8005cc0: 2b00 cmp r3, #0
|
|
8005cc2: d00a beq.n 8005cda <HAL_RCCEx_PeriphCLKConfig+0x2c2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
8005cc4: 4b8f ldr r3, [pc, #572] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005cc6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005cca: f023 020c bic.w r2, r3, #12
|
|
8005cce: 687b ldr r3, [r7, #4]
|
|
8005cd0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005cd2: 498c ldr r1, [pc, #560] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005cd4: 4313 orrs r3, r2
|
|
8005cd6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(USART3)
|
|
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
8005cda: 687b ldr r3, [r7, #4]
|
|
8005cdc: 681b ldr r3, [r3, #0]
|
|
8005cde: f003 0304 and.w r3, r3, #4
|
|
8005ce2: 2b00 cmp r3, #0
|
|
8005ce4: d00a beq.n 8005cfc <HAL_RCCEx_PeriphCLKConfig+0x2e4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
8005ce6: 4b87 ldr r3, [pc, #540] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005ce8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005cec: f023 0230 bic.w r2, r3, #48 @ 0x30
|
|
8005cf0: 687b ldr r3, [r7, #4]
|
|
8005cf2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005cf4: 4983 ldr r1, [pc, #524] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005cf6: 4313 orrs r3, r2
|
|
8005cf8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* USART3 */
|
|
|
|
#if defined(UART4)
|
|
|
|
/*-------------------------- UART4 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
8005cfc: 687b ldr r3, [r7, #4]
|
|
8005cfe: 681b ldr r3, [r3, #0]
|
|
8005d00: f003 0308 and.w r3, r3, #8
|
|
8005d04: 2b00 cmp r3, #0
|
|
8005d06: d00a beq.n 8005d1e <HAL_RCCEx_PeriphCLKConfig+0x306>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
8005d08: 4b7e ldr r3, [pc, #504] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d0a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005d0e: f023 02c0 bic.w r2, r3, #192 @ 0xc0
|
|
8005d12: 687b ldr r3, [r7, #4]
|
|
8005d14: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005d16: 497b ldr r1, [pc, #492] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d18: 4313 orrs r3, r2
|
|
8005d1a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* UART4 */
|
|
|
|
#if defined(UART5)
|
|
|
|
/*-------------------------- UART5 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
|
8005d1e: 687b ldr r3, [r7, #4]
|
|
8005d20: 681b ldr r3, [r3, #0]
|
|
8005d22: f003 0310 and.w r3, r3, #16
|
|
8005d26: 2b00 cmp r3, #0
|
|
8005d28: d00a beq.n 8005d40 <HAL_RCCEx_PeriphCLKConfig+0x328>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
|
|
|
/* Configure the UART5 clock source */
|
|
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
|
8005d2a: 4b76 ldr r3, [pc, #472] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d2c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005d30: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8005d34: 687b ldr r3, [r7, #4]
|
|
8005d36: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8005d38: 4972 ldr r1, [pc, #456] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d3a: 4313 orrs r3, r2
|
|
8005d3c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* UART5 */
|
|
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
8005d40: 687b ldr r3, [r7, #4]
|
|
8005d42: 681b ldr r3, [r3, #0]
|
|
8005d44: f003 0320 and.w r3, r3, #32
|
|
8005d48: 2b00 cmp r3, #0
|
|
8005d4a: d00a beq.n 8005d62 <HAL_RCCEx_PeriphCLKConfig+0x34a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUART1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
8005d4c: 4b6d ldr r3, [pc, #436] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d4e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005d52: f423 6240 bic.w r2, r3, #3072 @ 0xc00
|
|
8005d56: 687b ldr r3, [r7, #4]
|
|
8005d58: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8005d5a: 496a ldr r1, [pc, #424] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d5c: 4313 orrs r3, r2
|
|
8005d5e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
8005d62: 687b ldr r3, [r7, #4]
|
|
8005d64: 681b ldr r3, [r3, #0]
|
|
8005d66: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8005d6a: 2b00 cmp r3, #0
|
|
8005d6c: d00a beq.n 8005d84 <HAL_RCCEx_PeriphCLKConfig+0x36c>
|
|
{
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
8005d6e: 4b65 ldr r3, [pc, #404] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d70: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005d74: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
|
|
8005d78: 687b ldr r3, [r7, #4]
|
|
8005d7a: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8005d7c: 4961 ldr r1, [pc, #388] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d7e: 4313 orrs r3, r2
|
|
8005d80: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
8005d84: 687b ldr r3, [r7, #4]
|
|
8005d86: 681b ldr r3, [r3, #0]
|
|
8005d88: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8005d8c: 2b00 cmp r3, #0
|
|
8005d8e: d00a beq.n 8005da6 <HAL_RCCEx_PeriphCLKConfig+0x38e>
|
|
{
|
|
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
8005d90: 4b5c ldr r3, [pc, #368] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005d92: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005d96: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8005d9a: 687b ldr r3, [r7, #4]
|
|
8005d9c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8005d9e: 4959 ldr r1, [pc, #356] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005da0: 4313 orrs r3, r2
|
|
8005da2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
8005da6: 687b ldr r3, [r7, #4]
|
|
8005da8: 681b ldr r3, [r3, #0]
|
|
8005daa: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005dae: 2b00 cmp r3, #0
|
|
8005db0: d00a beq.n 8005dc8 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
8005db2: 4b54 ldr r3, [pc, #336] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005db4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005db8: f423 5240 bic.w r2, r3, #12288 @ 0x3000
|
|
8005dbc: 687b ldr r3, [r7, #4]
|
|
8005dbe: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8005dc0: 4950 ldr r1, [pc, #320] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005dc2: 4313 orrs r3, r2
|
|
8005dc4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(I2C2)
|
|
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
8005dc8: 687b ldr r3, [r7, #4]
|
|
8005dca: 681b ldr r3, [r3, #0]
|
|
8005dcc: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005dd0: 2b00 cmp r3, #0
|
|
8005dd2: d00a beq.n 8005dea <HAL_RCCEx_PeriphCLKConfig+0x3d2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
8005dd4: 4b4b ldr r3, [pc, #300] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005dd6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005dda: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
8005dde: 687b ldr r3, [r7, #4]
|
|
8005de0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8005de2: 4948 ldr r1, [pc, #288] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005de4: 4313 orrs r3, r2
|
|
8005de6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* I2C2 */
|
|
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
8005dea: 687b ldr r3, [r7, #4]
|
|
8005dec: 681b ldr r3, [r3, #0]
|
|
8005dee: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005df2: 2b00 cmp r3, #0
|
|
8005df4: d00a beq.n 8005e0c <HAL_RCCEx_PeriphCLKConfig+0x3f4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
8005df6: 4b43 ldr r3, [pc, #268] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005df8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005dfc: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
8005e00: 687b ldr r3, [r7, #4]
|
|
8005e02: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005e04: 493f ldr r1, [pc, #252] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e06: 4313 orrs r3, r2
|
|
8005e08: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* I2C4 */
|
|
|
|
#if defined(USB_OTG_FS) || defined(USB)
|
|
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|
8005e0c: 687b ldr r3, [r7, #4]
|
|
8005e0e: 681b ldr r3, [r3, #0]
|
|
8005e10: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8005e14: 2b00 cmp r3, #0
|
|
8005e16: d028 beq.n 8005e6a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
8005e18: 4b3a ldr r3, [pc, #232] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e1a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005e1e: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8005e22: 687b ldr r3, [r7, #4]
|
|
8005e24: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8005e26: 4937 ldr r1, [pc, #220] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e28: 4313 orrs r3, r2
|
|
8005e2a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
|
8005e2e: 687b ldr r3, [r7, #4]
|
|
8005e30: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8005e32: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8005e36: d106 bne.n 8005e46 <HAL_RCCEx_PeriphCLKConfig+0x42e>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8005e38: 4b32 ldr r3, [pc, #200] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e3a: 68db ldr r3, [r3, #12]
|
|
8005e3c: 4a31 ldr r2, [pc, #196] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e3e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8005e42: 60d3 str r3, [r2, #12]
|
|
8005e44: e011 b.n 8005e6a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
}
|
|
else
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
|
|
8005e46: 687b ldr r3, [r7, #4]
|
|
8005e48: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8005e4a: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8005e4e: d10c bne.n 8005e6a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8005e50: 687b ldr r3, [r7, #4]
|
|
8005e52: 3304 adds r3, #4
|
|
8005e54: 2101 movs r1, #1
|
|
8005e56: 4618 mov r0, r3
|
|
8005e58: f000 f8d8 bl 800600c <RCCEx_PLLSAI1_Config>
|
|
8005e5c: 4603 mov r3, r0
|
|
8005e5e: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8005e60: 7cfb ldrb r3, [r7, #19]
|
|
8005e62: 2b00 cmp r3, #0
|
|
8005e64: d001 beq.n 8005e6a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005e66: 7cfb ldrb r3, [r7, #19]
|
|
8005e68: 74bb strb r3, [r7, #18]
|
|
#endif /* USB_OTG_FS || USB */
|
|
|
|
#if defined(SDMMC1)
|
|
|
|
/*-------------------------- SDMMC1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
|
|
8005e6a: 687b ldr r3, [r7, #4]
|
|
8005e6c: 681b ldr r3, [r3, #0]
|
|
8005e6e: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8005e72: 2b00 cmp r3, #0
|
|
8005e74: d028 beq.n 8005ec8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
|
|
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
|
|
8005e76: 4b23 ldr r3, [pc, #140] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e78: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005e7c: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8005e80: 687b ldr r3, [r7, #4]
|
|
8005e82: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005e84: 491f ldr r1, [pc, #124] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e86: 4313 orrs r3, r2
|
|
8005e88: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
|
|
8005e8c: 687b ldr r3, [r7, #4]
|
|
8005e8e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005e90: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8005e94: d106 bne.n 8005ea4 <HAL_RCCEx_PeriphCLKConfig+0x48c>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8005e96: 4b1b ldr r3, [pc, #108] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e98: 68db ldr r3, [r3, #12]
|
|
8005e9a: 4a1a ldr r2, [pc, #104] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005e9c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8005ea0: 60d3 str r3, [r2, #12]
|
|
8005ea2: e011 b.n 8005ec8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* Enable PLLSAI3CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
}
|
|
#endif
|
|
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
|
|
8005ea4: 687b ldr r3, [r7, #4]
|
|
8005ea6: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005ea8: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8005eac: d10c bne.n 8005ec8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8005eae: 687b ldr r3, [r7, #4]
|
|
8005eb0: 3304 adds r3, #4
|
|
8005eb2: 2101 movs r1, #1
|
|
8005eb4: 4618 mov r0, r3
|
|
8005eb6: f000 f8a9 bl 800600c <RCCEx_PLLSAI1_Config>
|
|
8005eba: 4603 mov r3, r0
|
|
8005ebc: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8005ebe: 7cfb ldrb r3, [r7, #19]
|
|
8005ec0: 2b00 cmp r3, #0
|
|
8005ec2: d001 beq.n 8005ec8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005ec4: 7cfb ldrb r3, [r7, #19]
|
|
8005ec6: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
#endif /* SDMMC1 */
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
8005ec8: 687b ldr r3, [r7, #4]
|
|
8005eca: 681b ldr r3, [r3, #0]
|
|
8005ecc: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8005ed0: 2b00 cmp r3, #0
|
|
8005ed2: d02b beq.n 8005f2c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
8005ed4: 4b0b ldr r3, [pc, #44] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005ed6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005eda: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8005ede: 687b ldr r3, [r7, #4]
|
|
8005ee0: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005ee2: 4908 ldr r1, [pc, #32] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005ee4: 4313 orrs r3, r2
|
|
8005ee6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
8005eea: 687b ldr r3, [r7, #4]
|
|
8005eec: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005eee: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8005ef2: d109 bne.n 8005f08 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8005ef4: 4b03 ldr r3, [pc, #12] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005ef6: 68db ldr r3, [r3, #12]
|
|
8005ef8: 4a02 ldr r2, [pc, #8] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8005efa: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8005efe: 60d3 str r3, [r2, #12]
|
|
8005f00: e014 b.n 8005f2c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
8005f02: bf00 nop
|
|
8005f04: 40021000 .word 0x40021000
|
|
}
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
|
|
8005f08: 687b ldr r3, [r7, #4]
|
|
8005f0a: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005f0c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8005f10: d10c bne.n 8005f2c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8005f12: 687b ldr r3, [r7, #4]
|
|
8005f14: 3304 adds r3, #4
|
|
8005f16: 2101 movs r1, #1
|
|
8005f18: 4618 mov r0, r3
|
|
8005f1a: f000 f877 bl 800600c <RCCEx_PLLSAI1_Config>
|
|
8005f1e: 4603 mov r3, r0
|
|
8005f20: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8005f22: 7cfb ldrb r3, [r7, #19]
|
|
8005f24: 2b00 cmp r3, #0
|
|
8005f26: d001 beq.n 8005f2c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005f28: 7cfb ldrb r3, [r7, #19]
|
|
8005f2a: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
#if !defined(STM32L412xx) && !defined(STM32L422xx)
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8005f2c: 687b ldr r3, [r7, #4]
|
|
8005f2e: 681b ldr r3, [r3, #0]
|
|
8005f30: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8005f34: 2b00 cmp r3, #0
|
|
8005f36: d02f beq.n 8005f98 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
8005f38: 4b2b ldr r3, [pc, #172] @ (8005fe8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8005f3a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005f3e: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
|
|
8005f42: 687b ldr r3, [r7, #4]
|
|
8005f44: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8005f46: 4928 ldr r1, [pc, #160] @ (8005fe8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8005f48: 4313 orrs r3, r2
|
|
8005f4a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
|
|
8005f4e: 687b ldr r3, [r7, #4]
|
|
8005f50: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8005f52: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8005f56: d10d bne.n 8005f74 <HAL_RCCEx_PeriphCLKConfig+0x55c>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
|
|
8005f58: 687b ldr r3, [r7, #4]
|
|
8005f5a: 3304 adds r3, #4
|
|
8005f5c: 2102 movs r1, #2
|
|
8005f5e: 4618 mov r0, r3
|
|
8005f60: f000 f854 bl 800600c <RCCEx_PLLSAI1_Config>
|
|
8005f64: 4603 mov r3, r0
|
|
8005f66: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8005f68: 7cfb ldrb r3, [r7, #19]
|
|
8005f6a: 2b00 cmp r3, #0
|
|
8005f6c: d014 beq.n 8005f98 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005f6e: 7cfb ldrb r3, [r7, #19]
|
|
8005f70: 74bb strb r3, [r7, #18]
|
|
8005f72: e011 b.n 8005f98 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
}
|
|
#endif /* RCC_PLLSAI1_SUPPORT */
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
|
|
|
|
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
|
|
8005f74: 687b ldr r3, [r7, #4]
|
|
8005f76: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8005f78: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8005f7c: d10c bne.n 8005f98 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
|
|
8005f7e: 687b ldr r3, [r7, #4]
|
|
8005f80: 3320 adds r3, #32
|
|
8005f82: 2102 movs r1, #2
|
|
8005f84: 4618 mov r0, r3
|
|
8005f86: f000 f935 bl 80061f4 <RCCEx_PLLSAI2_Config>
|
|
8005f8a: 4603 mov r3, r0
|
|
8005f8c: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8005f8e: 7cfb ldrb r3, [r7, #19]
|
|
8005f90: 2b00 cmp r3, #0
|
|
8005f92: d001 beq.n 8005f98 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8005f94: 7cfb ldrb r3, [r7, #19]
|
|
8005f96: 74bb strb r3, [r7, #18]
|
|
#endif /* !STM32L412xx && !STM32L422xx */
|
|
|
|
#if defined(SWPMI1)
|
|
|
|
/*-------------------------- SWPMI1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
|
|
8005f98: 687b ldr r3, [r7, #4]
|
|
8005f9a: 681b ldr r3, [r3, #0]
|
|
8005f9c: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8005fa0: 2b00 cmp r3, #0
|
|
8005fa2: d00a beq.n 8005fba <HAL_RCCEx_PeriphCLKConfig+0x5a2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
|
|
|
|
/* Configure the SWPMI1 clock source */
|
|
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
|
|
8005fa4: 4b10 ldr r3, [pc, #64] @ (8005fe8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8005fa6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005faa: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000
|
|
8005fae: 687b ldr r3, [r7, #4]
|
|
8005fb0: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8005fb2: 490d ldr r1, [pc, #52] @ (8005fe8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8005fb4: 4313 orrs r3, r2
|
|
8005fb6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* SWPMI1 */
|
|
|
|
#if defined(DFSDM1_Filter0)
|
|
|
|
/*-------------------------- DFSDM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
|
|
8005fba: 687b ldr r3, [r7, #4]
|
|
8005fbc: 681b ldr r3, [r3, #0]
|
|
8005fbe: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8005fc2: 2b00 cmp r3, #0
|
|
8005fc4: d00b beq.n 8005fde <HAL_RCCEx_PeriphCLKConfig+0x5c6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
|
|
|
|
/* Configure the DFSDM1 interface clock source */
|
|
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
|
|
8005fc6: 4b08 ldr r3, [pc, #32] @ (8005fe8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8005fc8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005fcc: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
|
|
8005fd0: 687b ldr r3, [r7, #4]
|
|
8005fd2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8005fd6: 4904 ldr r1, [pc, #16] @ (8005fe8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8005fd8: 4313 orrs r3, r2
|
|
8005fda: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
}
|
|
|
|
#endif /* OCTOSPI1 || OCTOSPI2 */
|
|
|
|
return status;
|
|
8005fde: 7cbb ldrb r3, [r7, #18]
|
|
}
|
|
8005fe0: 4618 mov r0, r3
|
|
8005fe2: 3718 adds r7, #24
|
|
8005fe4: 46bd mov sp, r7
|
|
8005fe6: bd80 pop {r7, pc}
|
|
8005fe8: 40021000 .word 0x40021000
|
|
|
|
08005fec <HAL_RCCEx_EnableMSIPLLMode>:
|
|
* @note Prior to enable the PLL-mode of the MSI for automatic hardware
|
|
* calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableMSIPLLMode(void)
|
|
{
|
|
8005fec: b480 push {r7}
|
|
8005fee: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
|
|
8005ff0: 4b05 ldr r3, [pc, #20] @ (8006008 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
|
|
8005ff2: 681b ldr r3, [r3, #0]
|
|
8005ff4: 4a04 ldr r2, [pc, #16] @ (8006008 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
|
|
8005ff6: f043 0304 orr.w r3, r3, #4
|
|
8005ffa: 6013 str r3, [r2, #0]
|
|
}
|
|
8005ffc: bf00 nop
|
|
8005ffe: 46bd mov sp, r7
|
|
8006000: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006004: 4770 bx lr
|
|
8006006: bf00 nop
|
|
8006008: 40021000 .word 0x40021000
|
|
|
|
0800600c <RCCEx_PLLSAI1_Config>:
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
|
|
{
|
|
800600c: b580 push {r7, lr}
|
|
800600e: b084 sub sp, #16
|
|
8006010: af00 add r7, sp, #0
|
|
8006012: 6078 str r0, [r7, #4]
|
|
8006014: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8006016: 2300 movs r3, #0
|
|
8006018: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
|
|
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
|
|
|
|
/* Check that PLLSAI1 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
800601a: 4b75 ldr r3, [pc, #468] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
800601c: 68db ldr r3, [r3, #12]
|
|
800601e: f003 0303 and.w r3, r3, #3
|
|
8006022: 2b00 cmp r3, #0
|
|
8006024: d018 beq.n 8006058 <RCCEx_PLLSAI1_Config+0x4c>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
|
|
8006026: 4b72 ldr r3, [pc, #456] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006028: 68db ldr r3, [r3, #12]
|
|
800602a: f003 0203 and.w r2, r3, #3
|
|
800602e: 687b ldr r3, [r7, #4]
|
|
8006030: 681b ldr r3, [r3, #0]
|
|
8006032: 429a cmp r2, r3
|
|
8006034: d10d bne.n 8006052 <RCCEx_PLLSAI1_Config+0x46>
|
|
||
|
|
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
|
|
8006036: 687b ldr r3, [r7, #4]
|
|
8006038: 681b ldr r3, [r3, #0]
|
|
||
|
|
800603a: 2b00 cmp r3, #0
|
|
800603c: d009 beq.n 8006052 <RCCEx_PLLSAI1_Config+0x46>
|
|
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
|
|
800603e: 4b6c ldr r3, [pc, #432] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006040: 68db ldr r3, [r3, #12]
|
|
8006042: 091b lsrs r3, r3, #4
|
|
8006044: f003 0307 and.w r3, r3, #7
|
|
8006048: 1c5a adds r2, r3, #1
|
|
800604a: 687b ldr r3, [r7, #4]
|
|
800604c: 685b ldr r3, [r3, #4]
|
|
||
|
|
800604e: 429a cmp r2, r3
|
|
8006050: d047 beq.n 80060e2 <RCCEx_PLLSAI1_Config+0xd6>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
8006052: 2301 movs r3, #1
|
|
8006054: 73fb strb r3, [r7, #15]
|
|
8006056: e044 b.n 80060e2 <RCCEx_PLLSAI1_Config+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI1 clock source availability */
|
|
switch(PllSai1->PLLSAI1Source)
|
|
8006058: 687b ldr r3, [r7, #4]
|
|
800605a: 681b ldr r3, [r3, #0]
|
|
800605c: 2b03 cmp r3, #3
|
|
800605e: d018 beq.n 8006092 <RCCEx_PLLSAI1_Config+0x86>
|
|
8006060: 2b03 cmp r3, #3
|
|
8006062: d825 bhi.n 80060b0 <RCCEx_PLLSAI1_Config+0xa4>
|
|
8006064: 2b01 cmp r3, #1
|
|
8006066: d002 beq.n 800606e <RCCEx_PLLSAI1_Config+0x62>
|
|
8006068: 2b02 cmp r3, #2
|
|
800606a: d009 beq.n 8006080 <RCCEx_PLLSAI1_Config+0x74>
|
|
800606c: e020 b.n 80060b0 <RCCEx_PLLSAI1_Config+0xa4>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
800606e: 4b60 ldr r3, [pc, #384] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006070: 681b ldr r3, [r3, #0]
|
|
8006072: f003 0302 and.w r3, r3, #2
|
|
8006076: 2b00 cmp r3, #0
|
|
8006078: d11d bne.n 80060b6 <RCCEx_PLLSAI1_Config+0xaa>
|
|
{
|
|
status = HAL_ERROR;
|
|
800607a: 2301 movs r3, #1
|
|
800607c: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
800607e: e01a b.n 80060b6 <RCCEx_PLLSAI1_Config+0xaa>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8006080: 4b5b ldr r3, [pc, #364] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006082: 681b ldr r3, [r3, #0]
|
|
8006084: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8006088: 2b00 cmp r3, #0
|
|
800608a: d116 bne.n 80060ba <RCCEx_PLLSAI1_Config+0xae>
|
|
{
|
|
status = HAL_ERROR;
|
|
800608c: 2301 movs r3, #1
|
|
800608e: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8006090: e013 b.n 80060ba <RCCEx_PLLSAI1_Config+0xae>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8006092: 4b57 ldr r3, [pc, #348] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006094: 681b ldr r3, [r3, #0]
|
|
8006096: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800609a: 2b00 cmp r3, #0
|
|
800609c: d10f bne.n 80060be <RCCEx_PLLSAI1_Config+0xb2>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
800609e: 4b54 ldr r3, [pc, #336] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80060a0: 681b ldr r3, [r3, #0]
|
|
80060a2: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
80060a6: 2b00 cmp r3, #0
|
|
80060a8: d109 bne.n 80060be <RCCEx_PLLSAI1_Config+0xb2>
|
|
{
|
|
status = HAL_ERROR;
|
|
80060aa: 2301 movs r3, #1
|
|
80060ac: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
80060ae: e006 b.n 80060be <RCCEx_PLLSAI1_Config+0xb2>
|
|
default:
|
|
status = HAL_ERROR;
|
|
80060b0: 2301 movs r3, #1
|
|
80060b2: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80060b4: e004 b.n 80060c0 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
80060b6: bf00 nop
|
|
80060b8: e002 b.n 80060c0 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
80060ba: bf00 nop
|
|
80060bc: e000 b.n 80060c0 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
80060be: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80060c0: 7bfb ldrb r3, [r7, #15]
|
|
80060c2: 2b00 cmp r3, #0
|
|
80060c4: d10d bne.n 80060e2 <RCCEx_PLLSAI1_Config+0xd6>
|
|
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI1 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
|
|
#else
|
|
/* Set PLLSAI1 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
80060c6: 4b4a ldr r3, [pc, #296] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80060c8: 68db ldr r3, [r3, #12]
|
|
80060ca: f023 0273 bic.w r2, r3, #115 @ 0x73
|
|
80060ce: 687b ldr r3, [r7, #4]
|
|
80060d0: 6819 ldr r1, [r3, #0]
|
|
80060d2: 687b ldr r3, [r7, #4]
|
|
80060d4: 685b ldr r3, [r3, #4]
|
|
80060d6: 3b01 subs r3, #1
|
|
80060d8: 011b lsls r3, r3, #4
|
|
80060da: 430b orrs r3, r1
|
|
80060dc: 4944 ldr r1, [pc, #272] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80060de: 4313 orrs r3, r2
|
|
80060e0: 60cb str r3, [r1, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80060e2: 7bfb ldrb r3, [r7, #15]
|
|
80060e4: 2b00 cmp r3, #0
|
|
80060e6: d17d bne.n 80061e4 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
/* Disable the PLLSAI1 */
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
80060e8: 4b41 ldr r3, [pc, #260] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80060ea: 681b ldr r3, [r3, #0]
|
|
80060ec: 4a40 ldr r2, [pc, #256] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80060ee: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
80060f2: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80060f4: f7fd f8a4 bl 8003240 <HAL_GetTick>
|
|
80060f8: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
80060fa: e009 b.n 8006110 <RCCEx_PLLSAI1_Config+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
80060fc: f7fd f8a0 bl 8003240 <HAL_GetTick>
|
|
8006100: 4602 mov r2, r0
|
|
8006102: 68bb ldr r3, [r7, #8]
|
|
8006104: 1ad3 subs r3, r2, r3
|
|
8006106: 2b02 cmp r3, #2
|
|
8006108: d902 bls.n 8006110 <RCCEx_PLLSAI1_Config+0x104>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
800610a: 2303 movs r3, #3
|
|
800610c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800610e: e005 b.n 800611c <RCCEx_PLLSAI1_Config+0x110>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
8006110: 4b37 ldr r3, [pc, #220] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006112: 681b ldr r3, [r3, #0]
|
|
8006114: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8006118: 2b00 cmp r3, #0
|
|
800611a: d1ef bne.n 80060fc <RCCEx_PLLSAI1_Config+0xf0>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
800611c: 7bfb ldrb r3, [r7, #15]
|
|
800611e: 2b00 cmp r3, #0
|
|
8006120: d160 bne.n 80061e4 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
8006122: 683b ldr r3, [r7, #0]
|
|
8006124: 2b00 cmp r3, #0
|
|
8006126: d111 bne.n 800614c <RCCEx_PLLSAI1_Config+0x140>
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8006128: 4b31 ldr r3, [pc, #196] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
800612a: 691b ldr r3, [r3, #16]
|
|
800612c: f423 331f bic.w r3, r3, #162816 @ 0x27c00
|
|
8006130: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8006134: 687a ldr r2, [r7, #4]
|
|
8006136: 6892 ldr r2, [r2, #8]
|
|
8006138: 0211 lsls r1, r2, #8
|
|
800613a: 687a ldr r2, [r7, #4]
|
|
800613c: 68d2 ldr r2, [r2, #12]
|
|
800613e: 0912 lsrs r2, r2, #4
|
|
8006140: 0452 lsls r2, r2, #17
|
|
8006142: 430a orrs r2, r1
|
|
8006144: 492a ldr r1, [pc, #168] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006146: 4313 orrs r3, r2
|
|
8006148: 610b str r3, [r1, #16]
|
|
800614a: e027 b.n 800619c <RCCEx_PLLSAI1_Config+0x190>
|
|
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
|
|
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
else if(Divider == DIVIDER_Q_UPDATE)
|
|
800614c: 683b ldr r3, [r7, #0]
|
|
800614e: 2b01 cmp r3, #1
|
|
8006150: d112 bne.n 8006178 <RCCEx_PLLSAI1_Config+0x16c>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8006152: 4b27 ldr r3, [pc, #156] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006154: 691b ldr r3, [r3, #16]
|
|
8006156: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000
|
|
800615a: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
800615e: 687a ldr r2, [r7, #4]
|
|
8006160: 6892 ldr r2, [r2, #8]
|
|
8006162: 0211 lsls r1, r2, #8
|
|
8006164: 687a ldr r2, [r7, #4]
|
|
8006166: 6912 ldr r2, [r2, #16]
|
|
8006168: 0852 lsrs r2, r2, #1
|
|
800616a: 3a01 subs r2, #1
|
|
800616c: 0552 lsls r2, r2, #21
|
|
800616e: 430a orrs r2, r1
|
|
8006170: 491f ldr r1, [pc, #124] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006172: 4313 orrs r3, r2
|
|
8006174: 610b str r3, [r1, #16]
|
|
8006176: e011 b.n 800619c <RCCEx_PLLSAI1_Config+0x190>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8006178: 4b1d ldr r3, [pc, #116] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
800617a: 691b ldr r3, [r3, #16]
|
|
800617c: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
|
|
8006180: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8006184: 687a ldr r2, [r7, #4]
|
|
8006186: 6892 ldr r2, [r2, #8]
|
|
8006188: 0211 lsls r1, r2, #8
|
|
800618a: 687a ldr r2, [r7, #4]
|
|
800618c: 6952 ldr r2, [r2, #20]
|
|
800618e: 0852 lsrs r2, r2, #1
|
|
8006190: 3a01 subs r2, #1
|
|
8006192: 0652 lsls r2, r2, #25
|
|
8006194: 430a orrs r2, r1
|
|
8006196: 4916 ldr r1, [pc, #88] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8006198: 4313 orrs r3, r2
|
|
800619a: 610b str r3, [r1, #16]
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
800619c: 4b14 ldr r3, [pc, #80] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
800619e: 681b ldr r3, [r3, #0]
|
|
80061a0: 4a13 ldr r2, [pc, #76] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80061a2: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
80061a6: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80061a8: f7fd f84a bl 8003240 <HAL_GetTick>
|
|
80061ac: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
80061ae: e009 b.n 80061c4 <RCCEx_PLLSAI1_Config+0x1b8>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
80061b0: f7fd f846 bl 8003240 <HAL_GetTick>
|
|
80061b4: 4602 mov r2, r0
|
|
80061b6: 68bb ldr r3, [r7, #8]
|
|
80061b8: 1ad3 subs r3, r2, r3
|
|
80061ba: 2b02 cmp r3, #2
|
|
80061bc: d902 bls.n 80061c4 <RCCEx_PLLSAI1_Config+0x1b8>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
80061be: 2303 movs r3, #3
|
|
80061c0: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80061c2: e005 b.n 80061d0 <RCCEx_PLLSAI1_Config+0x1c4>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
80061c4: 4b0a ldr r3, [pc, #40] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80061c6: 681b ldr r3, [r3, #0]
|
|
80061c8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
80061cc: 2b00 cmp r3, #0
|
|
80061ce: d0ef beq.n 80061b0 <RCCEx_PLLSAI1_Config+0x1a4>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80061d0: 7bfb ldrb r3, [r7, #15]
|
|
80061d2: 2b00 cmp r3, #0
|
|
80061d4: d106 bne.n 80061e4 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
|
|
80061d6: 4b06 ldr r3, [pc, #24] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80061d8: 691a ldr r2, [r3, #16]
|
|
80061da: 687b ldr r3, [r7, #4]
|
|
80061dc: 699b ldr r3, [r3, #24]
|
|
80061de: 4904 ldr r1, [pc, #16] @ (80061f0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
80061e0: 4313 orrs r3, r2
|
|
80061e2: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
80061e4: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80061e6: 4618 mov r0, r3
|
|
80061e8: 3710 adds r7, #16
|
|
80061ea: 46bd mov sp, r7
|
|
80061ec: bd80 pop {r7, pc}
|
|
80061ee: bf00 nop
|
|
80061f0: 40021000 .word 0x40021000
|
|
|
|
080061f4 <RCCEx_PLLSAI2_Config>:
|
|
* @note PLLSAI2 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
|
|
{
|
|
80061f4: b580 push {r7, lr}
|
|
80061f6: b084 sub sp, #16
|
|
80061f8: af00 add r7, sp, #0
|
|
80061fa: 6078 str r0, [r7, #4]
|
|
80061fc: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80061fe: 2300 movs r3, #0
|
|
8006200: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
|
|
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
|
|
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
|
|
|
|
/* Check that PLLSAI2 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
8006202: 4b6a ldr r3, [pc, #424] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006204: 68db ldr r3, [r3, #12]
|
|
8006206: f003 0303 and.w r3, r3, #3
|
|
800620a: 2b00 cmp r3, #0
|
|
800620c: d018 beq.n 8006240 <RCCEx_PLLSAI2_Config+0x4c>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
|
|
800620e: 4b67 ldr r3, [pc, #412] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006210: 68db ldr r3, [r3, #12]
|
|
8006212: f003 0203 and.w r2, r3, #3
|
|
8006216: 687b ldr r3, [r7, #4]
|
|
8006218: 681b ldr r3, [r3, #0]
|
|
800621a: 429a cmp r2, r3
|
|
800621c: d10d bne.n 800623a <RCCEx_PLLSAI2_Config+0x46>
|
|
||
|
|
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
|
|
800621e: 687b ldr r3, [r7, #4]
|
|
8006220: 681b ldr r3, [r3, #0]
|
|
||
|
|
8006222: 2b00 cmp r3, #0
|
|
8006224: d009 beq.n 800623a <RCCEx_PLLSAI2_Config+0x46>
|
|
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
|
|
8006226: 4b61 ldr r3, [pc, #388] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006228: 68db ldr r3, [r3, #12]
|
|
800622a: 091b lsrs r3, r3, #4
|
|
800622c: f003 0307 and.w r3, r3, #7
|
|
8006230: 1c5a adds r2, r3, #1
|
|
8006232: 687b ldr r3, [r7, #4]
|
|
8006234: 685b ldr r3, [r3, #4]
|
|
||
|
|
8006236: 429a cmp r2, r3
|
|
8006238: d047 beq.n 80062ca <RCCEx_PLLSAI2_Config+0xd6>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
800623a: 2301 movs r3, #1
|
|
800623c: 73fb strb r3, [r7, #15]
|
|
800623e: e044 b.n 80062ca <RCCEx_PLLSAI2_Config+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI2 clock source availability */
|
|
switch(PllSai2->PLLSAI2Source)
|
|
8006240: 687b ldr r3, [r7, #4]
|
|
8006242: 681b ldr r3, [r3, #0]
|
|
8006244: 2b03 cmp r3, #3
|
|
8006246: d018 beq.n 800627a <RCCEx_PLLSAI2_Config+0x86>
|
|
8006248: 2b03 cmp r3, #3
|
|
800624a: d825 bhi.n 8006298 <RCCEx_PLLSAI2_Config+0xa4>
|
|
800624c: 2b01 cmp r3, #1
|
|
800624e: d002 beq.n 8006256 <RCCEx_PLLSAI2_Config+0x62>
|
|
8006250: 2b02 cmp r3, #2
|
|
8006252: d009 beq.n 8006268 <RCCEx_PLLSAI2_Config+0x74>
|
|
8006254: e020 b.n 8006298 <RCCEx_PLLSAI2_Config+0xa4>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
8006256: 4b55 ldr r3, [pc, #340] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006258: 681b ldr r3, [r3, #0]
|
|
800625a: f003 0302 and.w r3, r3, #2
|
|
800625e: 2b00 cmp r3, #0
|
|
8006260: d11d bne.n 800629e <RCCEx_PLLSAI2_Config+0xaa>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006262: 2301 movs r3, #1
|
|
8006264: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8006266: e01a b.n 800629e <RCCEx_PLLSAI2_Config+0xaa>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8006268: 4b50 ldr r3, [pc, #320] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
800626a: 681b ldr r3, [r3, #0]
|
|
800626c: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8006270: 2b00 cmp r3, #0
|
|
8006272: d116 bne.n 80062a2 <RCCEx_PLLSAI2_Config+0xae>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006274: 2301 movs r3, #1
|
|
8006276: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8006278: e013 b.n 80062a2 <RCCEx_PLLSAI2_Config+0xae>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
800627a: 4b4c ldr r3, [pc, #304] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
800627c: 681b ldr r3, [r3, #0]
|
|
800627e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8006282: 2b00 cmp r3, #0
|
|
8006284: d10f bne.n 80062a6 <RCCEx_PLLSAI2_Config+0xb2>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
8006286: 4b49 ldr r3, [pc, #292] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006288: 681b ldr r3, [r3, #0]
|
|
800628a: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
800628e: 2b00 cmp r3, #0
|
|
8006290: d109 bne.n 80062a6 <RCCEx_PLLSAI2_Config+0xb2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8006292: 2301 movs r3, #1
|
|
8006294: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8006296: e006 b.n 80062a6 <RCCEx_PLLSAI2_Config+0xb2>
|
|
default:
|
|
status = HAL_ERROR;
|
|
8006298: 2301 movs r3, #1
|
|
800629a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800629c: e004 b.n 80062a8 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
800629e: bf00 nop
|
|
80062a0: e002 b.n 80062a8 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
80062a2: bf00 nop
|
|
80062a4: e000 b.n 80062a8 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
80062a6: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80062a8: 7bfb ldrb r3, [r7, #15]
|
|
80062aa: 2b00 cmp r3, #0
|
|
80062ac: d10d bne.n 80062ca <RCCEx_PLLSAI2_Config+0xd6>
|
|
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI2 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
|
|
#else
|
|
/* Set PLLSAI2 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
80062ae: 4b3f ldr r3, [pc, #252] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
80062b0: 68db ldr r3, [r3, #12]
|
|
80062b2: f023 0273 bic.w r2, r3, #115 @ 0x73
|
|
80062b6: 687b ldr r3, [r7, #4]
|
|
80062b8: 6819 ldr r1, [r3, #0]
|
|
80062ba: 687b ldr r3, [r7, #4]
|
|
80062bc: 685b ldr r3, [r3, #4]
|
|
80062be: 3b01 subs r3, #1
|
|
80062c0: 011b lsls r3, r3, #4
|
|
80062c2: 430b orrs r3, r1
|
|
80062c4: 4939 ldr r1, [pc, #228] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
80062c6: 4313 orrs r3, r2
|
|
80062c8: 60cb str r3, [r1, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80062ca: 7bfb ldrb r3, [r7, #15]
|
|
80062cc: 2b00 cmp r3, #0
|
|
80062ce: d167 bne.n 80063a0 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
/* Disable the PLLSAI2 */
|
|
__HAL_RCC_PLLSAI2_DISABLE();
|
|
80062d0: 4b36 ldr r3, [pc, #216] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
80062d2: 681b ldr r3, [r3, #0]
|
|
80062d4: 4a35 ldr r2, [pc, #212] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
80062d6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80062da: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80062dc: f7fc ffb0 bl 8003240 <HAL_GetTick>
|
|
80062e0: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
80062e2: e009 b.n 80062f8 <RCCEx_PLLSAI2_Config+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
80062e4: f7fc ffac bl 8003240 <HAL_GetTick>
|
|
80062e8: 4602 mov r2, r0
|
|
80062ea: 68bb ldr r3, [r7, #8]
|
|
80062ec: 1ad3 subs r3, r2, r3
|
|
80062ee: 2b02 cmp r3, #2
|
|
80062f0: d902 bls.n 80062f8 <RCCEx_PLLSAI2_Config+0x104>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
80062f2: 2303 movs r3, #3
|
|
80062f4: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80062f6: e005 b.n 8006304 <RCCEx_PLLSAI2_Config+0x110>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
80062f8: 4b2c ldr r3, [pc, #176] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
80062fa: 681b ldr r3, [r3, #0]
|
|
80062fc: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8006300: 2b00 cmp r3, #0
|
|
8006302: d1ef bne.n 80062e4 <RCCEx_PLLSAI2_Config+0xf0>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8006304: 7bfb ldrb r3, [r7, #15]
|
|
8006306: 2b00 cmp r3, #0
|
|
8006308: d14a bne.n 80063a0 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
800630a: 683b ldr r3, [r7, #0]
|
|
800630c: 2b00 cmp r3, #0
|
|
800630e: d111 bne.n 8006334 <RCCEx_PLLSAI2_Config+0x140>
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
8006310: 4b26 ldr r3, [pc, #152] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006312: 695b ldr r3, [r3, #20]
|
|
8006314: f423 331f bic.w r3, r3, #162816 @ 0x27c00
|
|
8006318: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800631c: 687a ldr r2, [r7, #4]
|
|
800631e: 6892 ldr r2, [r2, #8]
|
|
8006320: 0211 lsls r1, r2, #8
|
|
8006322: 687a ldr r2, [r7, #4]
|
|
8006324: 68d2 ldr r2, [r2, #12]
|
|
8006326: 0912 lsrs r2, r2, #4
|
|
8006328: 0452 lsls r2, r2, #17
|
|
800632a: 430a orrs r2, r1
|
|
800632c: 491f ldr r1, [pc, #124] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
800632e: 4313 orrs r3, r2
|
|
8006330: 614b str r3, [r1, #20]
|
|
8006332: e011 b.n 8006358 <RCCEx_PLLSAI2_Config+0x164>
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
|
|
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
8006334: 4b1d ldr r3, [pc, #116] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006336: 695b ldr r3, [r3, #20]
|
|
8006338: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
|
|
800633c: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8006340: 687a ldr r2, [r7, #4]
|
|
8006342: 6892 ldr r2, [r2, #8]
|
|
8006344: 0211 lsls r1, r2, #8
|
|
8006346: 687a ldr r2, [r7, #4]
|
|
8006348: 6912 ldr r2, [r2, #16]
|
|
800634a: 0852 lsrs r2, r2, #1
|
|
800634c: 3a01 subs r2, #1
|
|
800634e: 0652 lsls r2, r2, #25
|
|
8006350: 430a orrs r2, r1
|
|
8006352: 4916 ldr r1, [pc, #88] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006354: 4313 orrs r3, r2
|
|
8006356: 614b str r3, [r1, #20]
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
|
|
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
|
|
__HAL_RCC_PLLSAI2_ENABLE();
|
|
8006358: 4b14 ldr r3, [pc, #80] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
800635a: 681b ldr r3, [r3, #0]
|
|
800635c: 4a13 ldr r2, [pc, #76] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
800635e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006362: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8006364: f7fc ff6c bl 8003240 <HAL_GetTick>
|
|
8006368: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
800636a: e009 b.n 8006380 <RCCEx_PLLSAI2_Config+0x18c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
800636c: f7fc ff68 bl 8003240 <HAL_GetTick>
|
|
8006370: 4602 mov r2, r0
|
|
8006372: 68bb ldr r3, [r7, #8]
|
|
8006374: 1ad3 subs r3, r2, r3
|
|
8006376: 2b02 cmp r3, #2
|
|
8006378: d902 bls.n 8006380 <RCCEx_PLLSAI2_Config+0x18c>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
800637a: 2303 movs r3, #3
|
|
800637c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800637e: e005 b.n 800638c <RCCEx_PLLSAI2_Config+0x198>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
8006380: 4b0a ldr r3, [pc, #40] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006382: 681b ldr r3, [r3, #0]
|
|
8006384: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8006388: 2b00 cmp r3, #0
|
|
800638a: d0ef beq.n 800636c <RCCEx_PLLSAI2_Config+0x178>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
800638c: 7bfb ldrb r3, [r7, #15]
|
|
800638e: 2b00 cmp r3, #0
|
|
8006390: d106 bne.n 80063a0 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
/* Configure the PLLSAI2 Clock output(s) */
|
|
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
|
|
8006392: 4b06 ldr r3, [pc, #24] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8006394: 695a ldr r2, [r3, #20]
|
|
8006396: 687b ldr r3, [r7, #4]
|
|
8006398: 695b ldr r3, [r3, #20]
|
|
800639a: 4904 ldr r1, [pc, #16] @ (80063ac <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
800639c: 4313 orrs r3, r2
|
|
800639e: 614b str r3, [r1, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
80063a0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80063a2: 4618 mov r0, r3
|
|
80063a4: 3710 adds r7, #16
|
|
80063a6: 46bd mov sp, r7
|
|
80063a8: bd80 pop {r7, pc}
|
|
80063aa: bf00 nop
|
|
80063ac: 40021000 .word 0x40021000
|
|
|
|
080063b0 <HAL_SPI_Init>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|
{
|
|
80063b0: b580 push {r7, lr}
|
|
80063b2: b084 sub sp, #16
|
|
80063b4: af00 add r7, sp, #0
|
|
80063b6: 6078 str r0, [r7, #4]
|
|
uint32_t frxth;
|
|
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
80063b8: 687b ldr r3, [r7, #4]
|
|
80063ba: 2b00 cmp r3, #0
|
|
80063bc: d101 bne.n 80063c2 <HAL_SPI_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80063be: 2301 movs r3, #1
|
|
80063c0: e095 b.n 80064ee <HAL_SPI_Init+0x13e>
|
|
assert_param(IS_SPI_NSS(hspi->Init.NSS));
|
|
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
|
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
|
|
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
|
|
80063c2: 687b ldr r3, [r7, #4]
|
|
80063c4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80063c6: 2b00 cmp r3, #0
|
|
80063c8: d108 bne.n 80063dc <HAL_SPI_Init+0x2c>
|
|
{
|
|
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
|
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
|
|
|
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
|
80063ca: 687b ldr r3, [r7, #4]
|
|
80063cc: 685b ldr r3, [r3, #4]
|
|
80063ce: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
80063d2: d009 beq.n 80063e8 <HAL_SPI_Init+0x38>
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
}
|
|
else
|
|
{
|
|
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
|
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
80063d4: 687b ldr r3, [r7, #4]
|
|
80063d6: 2200 movs r2, #0
|
|
80063d8: 61da str r2, [r3, #28]
|
|
80063da: e005 b.n 80063e8 <HAL_SPI_Init+0x38>
|
|
else
|
|
{
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
|
|
/* Force polarity and phase to TI protocaol requirements */
|
|
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
80063dc: 687b ldr r3, [r7, #4]
|
|
80063de: 2200 movs r2, #0
|
|
80063e0: 611a str r2, [r3, #16]
|
|
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
80063e2: 687b ldr r3, [r7, #4]
|
|
80063e4: 2200 movs r2, #0
|
|
80063e6: 615a str r2, [r3, #20]
|
|
{
|
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
|
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
|
|
}
|
|
#else
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
80063e8: 687b ldr r3, [r7, #4]
|
|
80063ea: 2200 movs r2, #0
|
|
80063ec: 629a str r2, [r3, #40] @ 0x28
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->State == HAL_SPI_STATE_RESET)
|
|
80063ee: 687b ldr r3, [r7, #4]
|
|
80063f0: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
80063f4: b2db uxtb r3, r3
|
|
80063f6: 2b00 cmp r3, #0
|
|
80063f8: d106 bne.n 8006408 <HAL_SPI_Init+0x58>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hspi->Lock = HAL_UNLOCKED;
|
|
80063fa: 687b ldr r3, [r7, #4]
|
|
80063fc: 2200 movs r2, #0
|
|
80063fe: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hspi->MspInitCallback(hspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspInit(hspi);
|
|
8006402: 6878 ldr r0, [r7, #4]
|
|
8006404: f7fc fbbc bl 8002b80 <HAL_SPI_MspInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
8006408: 687b ldr r3, [r7, #4]
|
|
800640a: 2202 movs r2, #2
|
|
800640c: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Disable the selected SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8006410: 687b ldr r3, [r7, #4]
|
|
8006412: 681b ldr r3, [r3, #0]
|
|
8006414: 681a ldr r2, [r3, #0]
|
|
8006416: 687b ldr r3, [r7, #4]
|
|
8006418: 681b ldr r3, [r3, #0]
|
|
800641a: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800641e: 601a str r2, [r3, #0]
|
|
|
|
/* Align by default the rs fifo threshold on the data size */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
8006420: 687b ldr r3, [r7, #4]
|
|
8006422: 68db ldr r3, [r3, #12]
|
|
8006424: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8006428: d902 bls.n 8006430 <HAL_SPI_Init+0x80>
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_HF;
|
|
800642a: 2300 movs r3, #0
|
|
800642c: 60fb str r3, [r7, #12]
|
|
800642e: e002 b.n 8006436 <HAL_SPI_Init+0x86>
|
|
}
|
|
else
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_QF;
|
|
8006430: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8006434: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* CRC calculation is valid only for 16Bit and 8 Bit */
|
|
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
|
|
8006436: 687b ldr r3, [r7, #4]
|
|
8006438: 68db ldr r3, [r3, #12]
|
|
800643a: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
|
|
800643e: d007 beq.n 8006450 <HAL_SPI_Init+0xa0>
|
|
8006440: 687b ldr r3, [r7, #4]
|
|
8006442: 68db ldr r3, [r3, #12]
|
|
8006444: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8006448: d002 beq.n 8006450 <HAL_SPI_Init+0xa0>
|
|
{
|
|
/* CRC must be disabled */
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
800644a: 687b ldr r3, [r7, #4]
|
|
800644c: 2200 movs r2, #0
|
|
800644e: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
|
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
|
|
Communication speed, First bit and CRC calculation state */
|
|
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
|
8006450: 687b ldr r3, [r7, #4]
|
|
8006452: 685b ldr r3, [r3, #4]
|
|
8006454: f403 7282 and.w r2, r3, #260 @ 0x104
|
|
8006458: 687b ldr r3, [r7, #4]
|
|
800645a: 689b ldr r3, [r3, #8]
|
|
800645c: f403 4304 and.w r3, r3, #33792 @ 0x8400
|
|
8006460: 431a orrs r2, r3
|
|
8006462: 687b ldr r3, [r7, #4]
|
|
8006464: 691b ldr r3, [r3, #16]
|
|
8006466: f003 0302 and.w r3, r3, #2
|
|
800646a: 431a orrs r2, r3
|
|
800646c: 687b ldr r3, [r7, #4]
|
|
800646e: 695b ldr r3, [r3, #20]
|
|
8006470: f003 0301 and.w r3, r3, #1
|
|
8006474: 431a orrs r2, r3
|
|
8006476: 687b ldr r3, [r7, #4]
|
|
8006478: 699b ldr r3, [r3, #24]
|
|
800647a: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800647e: 431a orrs r2, r3
|
|
8006480: 687b ldr r3, [r7, #4]
|
|
8006482: 69db ldr r3, [r3, #28]
|
|
8006484: f003 0338 and.w r3, r3, #56 @ 0x38
|
|
8006488: 431a orrs r2, r3
|
|
800648a: 687b ldr r3, [r7, #4]
|
|
800648c: 6a1b ldr r3, [r3, #32]
|
|
800648e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006492: ea42 0103 orr.w r1, r2, r3
|
|
8006496: 687b ldr r3, [r7, #4]
|
|
8006498: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800649a: f403 5200 and.w r2, r3, #8192 @ 0x2000
|
|
800649e: 687b ldr r3, [r7, #4]
|
|
80064a0: 681b ldr r3, [r3, #0]
|
|
80064a2: 430a orrs r2, r1
|
|
80064a4: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
|
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
|
|
80064a6: 687b ldr r3, [r7, #4]
|
|
80064a8: 699b ldr r3, [r3, #24]
|
|
80064aa: 0c1b lsrs r3, r3, #16
|
|
80064ac: f003 0204 and.w r2, r3, #4
|
|
80064b0: 687b ldr r3, [r7, #4]
|
|
80064b2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80064b4: f003 0310 and.w r3, r3, #16
|
|
80064b8: 431a orrs r2, r3
|
|
80064ba: 687b ldr r3, [r7, #4]
|
|
80064bc: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80064be: f003 0308 and.w r3, r3, #8
|
|
80064c2: 431a orrs r2, r3
|
|
80064c4: 687b ldr r3, [r7, #4]
|
|
80064c6: 68db ldr r3, [r3, #12]
|
|
80064c8: f403 6370 and.w r3, r3, #3840 @ 0xf00
|
|
80064cc: ea42 0103 orr.w r1, r2, r3
|
|
80064d0: 68fb ldr r3, [r7, #12]
|
|
80064d2: f403 5280 and.w r2, r3, #4096 @ 0x1000
|
|
80064d6: 687b ldr r3, [r7, #4]
|
|
80064d8: 681b ldr r3, [r3, #0]
|
|
80064da: 430a orrs r2, r1
|
|
80064dc: 605a str r2, [r3, #4]
|
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
80064de: 687b ldr r3, [r7, #4]
|
|
80064e0: 2200 movs r2, #0
|
|
80064e2: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80064e4: 687b ldr r3, [r7, #4]
|
|
80064e6: 2201 movs r2, #1
|
|
80064e8: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
return HAL_OK;
|
|
80064ec: 2300 movs r3, #0
|
|
}
|
|
80064ee: 4618 mov r0, r3
|
|
80064f0: 3710 adds r7, #16
|
|
80064f2: 46bd mov sp, r7
|
|
80064f4: bd80 pop {r7, pc}
|
|
|
|
080064f6 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
80064f6: b580 push {r7, lr}
|
|
80064f8: b082 sub sp, #8
|
|
80064fa: af00 add r7, sp, #0
|
|
80064fc: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
80064fe: 687b ldr r3, [r7, #4]
|
|
8006500: 2b00 cmp r3, #0
|
|
8006502: d101 bne.n 8006508 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8006504: 2301 movs r3, #1
|
|
8006506: e040 b.n 800658a <HAL_UART_Init+0x94>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8006508: 687b ldr r3, [r7, #4]
|
|
800650a: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
800650c: 2b00 cmp r3, #0
|
|
800650e: d106 bne.n 800651e <HAL_UART_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8006510: 687b ldr r3, [r7, #4]
|
|
8006512: 2200 movs r2, #0
|
|
8006514: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8006518: 6878 ldr r0, [r7, #4]
|
|
800651a: f7fc fb75 bl 8002c08 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
800651e: 687b ldr r3, [r7, #4]
|
|
8006520: 2224 movs r2, #36 @ 0x24
|
|
8006522: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
8006524: 687b ldr r3, [r7, #4]
|
|
8006526: 681b ldr r3, [r3, #0]
|
|
8006528: 681a ldr r2, [r3, #0]
|
|
800652a: 687b ldr r3, [r7, #4]
|
|
800652c: 681b ldr r3, [r3, #0]
|
|
800652e: f022 0201 bic.w r2, r2, #1
|
|
8006532: 601a str r2, [r3, #0]
|
|
|
|
/* Perform advanced settings configuration */
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
8006534: 687b ldr r3, [r7, #4]
|
|
8006536: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006538: 2b00 cmp r3, #0
|
|
800653a: d002 beq.n 8006542 <HAL_UART_Init+0x4c>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
800653c: 6878 ldr r0, [r7, #4]
|
|
800653e: f000 fb69 bl 8006c14 <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
8006542: 6878 ldr r0, [r7, #4]
|
|
8006544: f000 f8ae bl 80066a4 <UART_SetConfig>
|
|
8006548: 4603 mov r3, r0
|
|
800654a: 2b01 cmp r3, #1
|
|
800654c: d101 bne.n 8006552 <HAL_UART_Init+0x5c>
|
|
{
|
|
return HAL_ERROR;
|
|
800654e: 2301 movs r3, #1
|
|
8006550: e01b b.n 800658a <HAL_UART_Init+0x94>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8006552: 687b ldr r3, [r7, #4]
|
|
8006554: 681b ldr r3, [r3, #0]
|
|
8006556: 685a ldr r2, [r3, #4]
|
|
8006558: 687b ldr r3, [r7, #4]
|
|
800655a: 681b ldr r3, [r3, #0]
|
|
800655c: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8006560: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8006562: 687b ldr r3, [r7, #4]
|
|
8006564: 681b ldr r3, [r3, #0]
|
|
8006566: 689a ldr r2, [r3, #8]
|
|
8006568: 687b ldr r3, [r7, #4]
|
|
800656a: 681b ldr r3, [r3, #0]
|
|
800656c: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8006570: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
8006572: 687b ldr r3, [r7, #4]
|
|
8006574: 681b ldr r3, [r3, #0]
|
|
8006576: 681a ldr r2, [r3, #0]
|
|
8006578: 687b ldr r3, [r7, #4]
|
|
800657a: 681b ldr r3, [r3, #0]
|
|
800657c: f042 0201 orr.w r2, r2, #1
|
|
8006580: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
8006582: 6878 ldr r0, [r7, #4]
|
|
8006584: f000 fbe8 bl 8006d58 <UART_CheckIdleState>
|
|
8006588: 4603 mov r3, r0
|
|
}
|
|
800658a: 4618 mov r0, r3
|
|
800658c: 3708 adds r7, #8
|
|
800658e: 46bd mov sp, r7
|
|
8006590: bd80 pop {r7, pc}
|
|
|
|
08006592 <HAL_UART_Transmit>:
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
* @param Timeout Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8006592: b580 push {r7, lr}
|
|
8006594: b08a sub sp, #40 @ 0x28
|
|
8006596: af02 add r7, sp, #8
|
|
8006598: 60f8 str r0, [r7, #12]
|
|
800659a: 60b9 str r1, [r7, #8]
|
|
800659c: 603b str r3, [r7, #0]
|
|
800659e: 4613 mov r3, r2
|
|
80065a0: 80fb strh r3, [r7, #6]
|
|
const uint8_t *pdata8bits;
|
|
const uint16_t *pdata16bits;
|
|
uint32_t tickstart;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
80065a2: 68fb ldr r3, [r7, #12]
|
|
80065a4: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
80065a6: 2b20 cmp r3, #32
|
|
80065a8: d177 bne.n 800669a <HAL_UART_Transmit+0x108>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80065aa: 68bb ldr r3, [r7, #8]
|
|
80065ac: 2b00 cmp r3, #0
|
|
80065ae: d002 beq.n 80065b6 <HAL_UART_Transmit+0x24>
|
|
80065b0: 88fb ldrh r3, [r7, #6]
|
|
80065b2: 2b00 cmp r3, #0
|
|
80065b4: d101 bne.n 80065ba <HAL_UART_Transmit+0x28>
|
|
{
|
|
return HAL_ERROR;
|
|
80065b6: 2301 movs r3, #1
|
|
80065b8: e070 b.n 800669c <HAL_UART_Transmit+0x10a>
|
|
}
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80065ba: 68fb ldr r3, [r7, #12]
|
|
80065bc: 2200 movs r2, #0
|
|
80065be: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
80065c2: 68fb ldr r3, [r7, #12]
|
|
80065c4: 2221 movs r2, #33 @ 0x21
|
|
80065c6: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
80065c8: f7fc fe3a bl 8003240 <HAL_GetTick>
|
|
80065cc: 6178 str r0, [r7, #20]
|
|
|
|
huart->TxXferSize = Size;
|
|
80065ce: 68fb ldr r3, [r7, #12]
|
|
80065d0: 88fa ldrh r2, [r7, #6]
|
|
80065d2: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
|
|
huart->TxXferCount = Size;
|
|
80065d6: 68fb ldr r3, [r7, #12]
|
|
80065d8: 88fa ldrh r2, [r7, #6]
|
|
80065da: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
80065de: 68fb ldr r3, [r7, #12]
|
|
80065e0: 689b ldr r3, [r3, #8]
|
|
80065e2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80065e6: d108 bne.n 80065fa <HAL_UART_Transmit+0x68>
|
|
80065e8: 68fb ldr r3, [r7, #12]
|
|
80065ea: 691b ldr r3, [r3, #16]
|
|
80065ec: 2b00 cmp r3, #0
|
|
80065ee: d104 bne.n 80065fa <HAL_UART_Transmit+0x68>
|
|
{
|
|
pdata8bits = NULL;
|
|
80065f0: 2300 movs r3, #0
|
|
80065f2: 61fb str r3, [r7, #28]
|
|
pdata16bits = (const uint16_t *) pData;
|
|
80065f4: 68bb ldr r3, [r7, #8]
|
|
80065f6: 61bb str r3, [r7, #24]
|
|
80065f8: e003 b.n 8006602 <HAL_UART_Transmit+0x70>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
80065fa: 68bb ldr r3, [r7, #8]
|
|
80065fc: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
80065fe: 2300 movs r3, #0
|
|
8006600: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
8006602: e02f b.n 8006664 <HAL_UART_Transmit+0xd2>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
8006604: 683b ldr r3, [r7, #0]
|
|
8006606: 9300 str r3, [sp, #0]
|
|
8006608: 697b ldr r3, [r7, #20]
|
|
800660a: 2200 movs r2, #0
|
|
800660c: 2180 movs r1, #128 @ 0x80
|
|
800660e: 68f8 ldr r0, [r7, #12]
|
|
8006610: f000 fc4a bl 8006ea8 <UART_WaitOnFlagUntilTimeout>
|
|
8006614: 4603 mov r3, r0
|
|
8006616: 2b00 cmp r3, #0
|
|
8006618: d004 beq.n 8006624 <HAL_UART_Transmit+0x92>
|
|
{
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800661a: 68fb ldr r3, [r7, #12]
|
|
800661c: 2220 movs r2, #32
|
|
800661e: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_TIMEOUT;
|
|
8006620: 2303 movs r3, #3
|
|
8006622: e03b b.n 800669c <HAL_UART_Transmit+0x10a>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
8006624: 69fb ldr r3, [r7, #28]
|
|
8006626: 2b00 cmp r3, #0
|
|
8006628: d10b bne.n 8006642 <HAL_UART_Transmit+0xb0>
|
|
{
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
800662a: 69bb ldr r3, [r7, #24]
|
|
800662c: 881a ldrh r2, [r3, #0]
|
|
800662e: 68fb ldr r3, [r7, #12]
|
|
8006630: 681b ldr r3, [r3, #0]
|
|
8006632: f3c2 0208 ubfx r2, r2, #0, #9
|
|
8006636: b292 uxth r2, r2
|
|
8006638: 851a strh r2, [r3, #40] @ 0x28
|
|
pdata16bits++;
|
|
800663a: 69bb ldr r3, [r7, #24]
|
|
800663c: 3302 adds r3, #2
|
|
800663e: 61bb str r3, [r7, #24]
|
|
8006640: e007 b.n 8006652 <HAL_UART_Transmit+0xc0>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
8006642: 69fb ldr r3, [r7, #28]
|
|
8006644: 781a ldrb r2, [r3, #0]
|
|
8006646: 68fb ldr r3, [r7, #12]
|
|
8006648: 681b ldr r3, [r3, #0]
|
|
800664a: 851a strh r2, [r3, #40] @ 0x28
|
|
pdata8bits++;
|
|
800664c: 69fb ldr r3, [r7, #28]
|
|
800664e: 3301 adds r3, #1
|
|
8006650: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->TxXferCount--;
|
|
8006652: 68fb ldr r3, [r7, #12]
|
|
8006654: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8006658: b29b uxth r3, r3
|
|
800665a: 3b01 subs r3, #1
|
|
800665c: b29a uxth r2, r3
|
|
800665e: 68fb ldr r3, [r7, #12]
|
|
8006660: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
while (huart->TxXferCount > 0U)
|
|
8006664: 68fb ldr r3, [r7, #12]
|
|
8006666: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
800666a: b29b uxth r3, r3
|
|
800666c: 2b00 cmp r3, #0
|
|
800666e: d1c9 bne.n 8006604 <HAL_UART_Transmit+0x72>
|
|
}
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
8006670: 683b ldr r3, [r7, #0]
|
|
8006672: 9300 str r3, [sp, #0]
|
|
8006674: 697b ldr r3, [r7, #20]
|
|
8006676: 2200 movs r2, #0
|
|
8006678: 2140 movs r1, #64 @ 0x40
|
|
800667a: 68f8 ldr r0, [r7, #12]
|
|
800667c: f000 fc14 bl 8006ea8 <UART_WaitOnFlagUntilTimeout>
|
|
8006680: 4603 mov r3, r0
|
|
8006682: 2b00 cmp r3, #0
|
|
8006684: d004 beq.n 8006690 <HAL_UART_Transmit+0xfe>
|
|
{
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006686: 68fb ldr r3, [r7, #12]
|
|
8006688: 2220 movs r2, #32
|
|
800668a: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_TIMEOUT;
|
|
800668c: 2303 movs r3, #3
|
|
800668e: e005 b.n 800669c <HAL_UART_Transmit+0x10a>
|
|
}
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006690: 68fb ldr r3, [r7, #12]
|
|
8006692: 2220 movs r2, #32
|
|
8006694: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_OK;
|
|
8006696: 2300 movs r3, #0
|
|
8006698: e000 b.n 800669c <HAL_UART_Transmit+0x10a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800669a: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800669c: 4618 mov r0, r3
|
|
800669e: 3720 adds r7, #32
|
|
80066a0: 46bd mov sp, r7
|
|
80066a2: bd80 pop {r7, pc}
|
|
|
|
080066a4 <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
80066a4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
80066a8: b08a sub sp, #40 @ 0x28
|
|
80066aa: af00 add r7, sp, #0
|
|
80066ac: 60f8 str r0, [r7, #12]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
80066ae: 2300 movs r3, #0
|
|
80066b0: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
80066b4: 68fb ldr r3, [r7, #12]
|
|
80066b6: 689a ldr r2, [r3, #8]
|
|
80066b8: 68fb ldr r3, [r7, #12]
|
|
80066ba: 691b ldr r3, [r3, #16]
|
|
80066bc: 431a orrs r2, r3
|
|
80066be: 68fb ldr r3, [r7, #12]
|
|
80066c0: 695b ldr r3, [r3, #20]
|
|
80066c2: 431a orrs r2, r3
|
|
80066c4: 68fb ldr r3, [r7, #12]
|
|
80066c6: 69db ldr r3, [r3, #28]
|
|
80066c8: 4313 orrs r3, r2
|
|
80066ca: 627b str r3, [r7, #36] @ 0x24
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
80066cc: 68fb ldr r3, [r7, #12]
|
|
80066ce: 681b ldr r3, [r3, #0]
|
|
80066d0: 681a ldr r2, [r3, #0]
|
|
80066d2: 4ba4 ldr r3, [pc, #656] @ (8006964 <UART_SetConfig+0x2c0>)
|
|
80066d4: 4013 ands r3, r2
|
|
80066d6: 68fa ldr r2, [r7, #12]
|
|
80066d8: 6812 ldr r2, [r2, #0]
|
|
80066da: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80066dc: 430b orrs r3, r1
|
|
80066de: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
80066e0: 68fb ldr r3, [r7, #12]
|
|
80066e2: 681b ldr r3, [r3, #0]
|
|
80066e4: 685b ldr r3, [r3, #4]
|
|
80066e6: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
80066ea: 68fb ldr r3, [r7, #12]
|
|
80066ec: 68da ldr r2, [r3, #12]
|
|
80066ee: 68fb ldr r3, [r7, #12]
|
|
80066f0: 681b ldr r3, [r3, #0]
|
|
80066f2: 430a orrs r2, r1
|
|
80066f4: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
80066f6: 68fb ldr r3, [r7, #12]
|
|
80066f8: 699b ldr r3, [r3, #24]
|
|
80066fa: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
80066fc: 68fb ldr r3, [r7, #12]
|
|
80066fe: 681b ldr r3, [r3, #0]
|
|
8006700: 4a99 ldr r2, [pc, #612] @ (8006968 <UART_SetConfig+0x2c4>)
|
|
8006702: 4293 cmp r3, r2
|
|
8006704: d004 beq.n 8006710 <UART_SetConfig+0x6c>
|
|
{
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
8006706: 68fb ldr r3, [r7, #12]
|
|
8006708: 6a1b ldr r3, [r3, #32]
|
|
800670a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800670c: 4313 orrs r3, r2
|
|
800670e: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
8006710: 68fb ldr r3, [r7, #12]
|
|
8006712: 681b ldr r3, [r3, #0]
|
|
8006714: 689b ldr r3, [r3, #8]
|
|
8006716: f423 6130 bic.w r1, r3, #2816 @ 0xb00
|
|
800671a: 68fb ldr r3, [r7, #12]
|
|
800671c: 681b ldr r3, [r3, #0]
|
|
800671e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8006720: 430a orrs r2, r1
|
|
8006722: 609a str r2, [r3, #8]
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
8006724: 68fb ldr r3, [r7, #12]
|
|
8006726: 681b ldr r3, [r3, #0]
|
|
8006728: 4a90 ldr r2, [pc, #576] @ (800696c <UART_SetConfig+0x2c8>)
|
|
800672a: 4293 cmp r3, r2
|
|
800672c: d126 bne.n 800677c <UART_SetConfig+0xd8>
|
|
800672e: 4b90 ldr r3, [pc, #576] @ (8006970 <UART_SetConfig+0x2cc>)
|
|
8006730: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006734: f003 0303 and.w r3, r3, #3
|
|
8006738: 2b03 cmp r3, #3
|
|
800673a: d81b bhi.n 8006774 <UART_SetConfig+0xd0>
|
|
800673c: a201 add r2, pc, #4 @ (adr r2, 8006744 <UART_SetConfig+0xa0>)
|
|
800673e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006742: bf00 nop
|
|
8006744: 08006755 .word 0x08006755
|
|
8006748: 08006765 .word 0x08006765
|
|
800674c: 0800675d .word 0x0800675d
|
|
8006750: 0800676d .word 0x0800676d
|
|
8006754: 2301 movs r3, #1
|
|
8006756: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800675a: e116 b.n 800698a <UART_SetConfig+0x2e6>
|
|
800675c: 2302 movs r3, #2
|
|
800675e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006762: e112 b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006764: 2304 movs r3, #4
|
|
8006766: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800676a: e10e b.n 800698a <UART_SetConfig+0x2e6>
|
|
800676c: 2308 movs r3, #8
|
|
800676e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006772: e10a b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006774: 2310 movs r3, #16
|
|
8006776: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800677a: e106 b.n 800698a <UART_SetConfig+0x2e6>
|
|
800677c: 68fb ldr r3, [r7, #12]
|
|
800677e: 681b ldr r3, [r3, #0]
|
|
8006780: 4a7c ldr r2, [pc, #496] @ (8006974 <UART_SetConfig+0x2d0>)
|
|
8006782: 4293 cmp r3, r2
|
|
8006784: d138 bne.n 80067f8 <UART_SetConfig+0x154>
|
|
8006786: 4b7a ldr r3, [pc, #488] @ (8006970 <UART_SetConfig+0x2cc>)
|
|
8006788: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800678c: f003 030c and.w r3, r3, #12
|
|
8006790: 2b0c cmp r3, #12
|
|
8006792: d82d bhi.n 80067f0 <UART_SetConfig+0x14c>
|
|
8006794: a201 add r2, pc, #4 @ (adr r2, 800679c <UART_SetConfig+0xf8>)
|
|
8006796: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800679a: bf00 nop
|
|
800679c: 080067d1 .word 0x080067d1
|
|
80067a0: 080067f1 .word 0x080067f1
|
|
80067a4: 080067f1 .word 0x080067f1
|
|
80067a8: 080067f1 .word 0x080067f1
|
|
80067ac: 080067e1 .word 0x080067e1
|
|
80067b0: 080067f1 .word 0x080067f1
|
|
80067b4: 080067f1 .word 0x080067f1
|
|
80067b8: 080067f1 .word 0x080067f1
|
|
80067bc: 080067d9 .word 0x080067d9
|
|
80067c0: 080067f1 .word 0x080067f1
|
|
80067c4: 080067f1 .word 0x080067f1
|
|
80067c8: 080067f1 .word 0x080067f1
|
|
80067cc: 080067e9 .word 0x080067e9
|
|
80067d0: 2300 movs r3, #0
|
|
80067d2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80067d6: e0d8 b.n 800698a <UART_SetConfig+0x2e6>
|
|
80067d8: 2302 movs r3, #2
|
|
80067da: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80067de: e0d4 b.n 800698a <UART_SetConfig+0x2e6>
|
|
80067e0: 2304 movs r3, #4
|
|
80067e2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80067e6: e0d0 b.n 800698a <UART_SetConfig+0x2e6>
|
|
80067e8: 2308 movs r3, #8
|
|
80067ea: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80067ee: e0cc b.n 800698a <UART_SetConfig+0x2e6>
|
|
80067f0: 2310 movs r3, #16
|
|
80067f2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80067f6: e0c8 b.n 800698a <UART_SetConfig+0x2e6>
|
|
80067f8: 68fb ldr r3, [r7, #12]
|
|
80067fa: 681b ldr r3, [r3, #0]
|
|
80067fc: 4a5e ldr r2, [pc, #376] @ (8006978 <UART_SetConfig+0x2d4>)
|
|
80067fe: 4293 cmp r3, r2
|
|
8006800: d125 bne.n 800684e <UART_SetConfig+0x1aa>
|
|
8006802: 4b5b ldr r3, [pc, #364] @ (8006970 <UART_SetConfig+0x2cc>)
|
|
8006804: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006808: f003 0330 and.w r3, r3, #48 @ 0x30
|
|
800680c: 2b30 cmp r3, #48 @ 0x30
|
|
800680e: d016 beq.n 800683e <UART_SetConfig+0x19a>
|
|
8006810: 2b30 cmp r3, #48 @ 0x30
|
|
8006812: d818 bhi.n 8006846 <UART_SetConfig+0x1a2>
|
|
8006814: 2b20 cmp r3, #32
|
|
8006816: d00a beq.n 800682e <UART_SetConfig+0x18a>
|
|
8006818: 2b20 cmp r3, #32
|
|
800681a: d814 bhi.n 8006846 <UART_SetConfig+0x1a2>
|
|
800681c: 2b00 cmp r3, #0
|
|
800681e: d002 beq.n 8006826 <UART_SetConfig+0x182>
|
|
8006820: 2b10 cmp r3, #16
|
|
8006822: d008 beq.n 8006836 <UART_SetConfig+0x192>
|
|
8006824: e00f b.n 8006846 <UART_SetConfig+0x1a2>
|
|
8006826: 2300 movs r3, #0
|
|
8006828: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800682c: e0ad b.n 800698a <UART_SetConfig+0x2e6>
|
|
800682e: 2302 movs r3, #2
|
|
8006830: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006834: e0a9 b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006836: 2304 movs r3, #4
|
|
8006838: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800683c: e0a5 b.n 800698a <UART_SetConfig+0x2e6>
|
|
800683e: 2308 movs r3, #8
|
|
8006840: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006844: e0a1 b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006846: 2310 movs r3, #16
|
|
8006848: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800684c: e09d b.n 800698a <UART_SetConfig+0x2e6>
|
|
800684e: 68fb ldr r3, [r7, #12]
|
|
8006850: 681b ldr r3, [r3, #0]
|
|
8006852: 4a4a ldr r2, [pc, #296] @ (800697c <UART_SetConfig+0x2d8>)
|
|
8006854: 4293 cmp r3, r2
|
|
8006856: d125 bne.n 80068a4 <UART_SetConfig+0x200>
|
|
8006858: 4b45 ldr r3, [pc, #276] @ (8006970 <UART_SetConfig+0x2cc>)
|
|
800685a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800685e: f003 03c0 and.w r3, r3, #192 @ 0xc0
|
|
8006862: 2bc0 cmp r3, #192 @ 0xc0
|
|
8006864: d016 beq.n 8006894 <UART_SetConfig+0x1f0>
|
|
8006866: 2bc0 cmp r3, #192 @ 0xc0
|
|
8006868: d818 bhi.n 800689c <UART_SetConfig+0x1f8>
|
|
800686a: 2b80 cmp r3, #128 @ 0x80
|
|
800686c: d00a beq.n 8006884 <UART_SetConfig+0x1e0>
|
|
800686e: 2b80 cmp r3, #128 @ 0x80
|
|
8006870: d814 bhi.n 800689c <UART_SetConfig+0x1f8>
|
|
8006872: 2b00 cmp r3, #0
|
|
8006874: d002 beq.n 800687c <UART_SetConfig+0x1d8>
|
|
8006876: 2b40 cmp r3, #64 @ 0x40
|
|
8006878: d008 beq.n 800688c <UART_SetConfig+0x1e8>
|
|
800687a: e00f b.n 800689c <UART_SetConfig+0x1f8>
|
|
800687c: 2300 movs r3, #0
|
|
800687e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006882: e082 b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006884: 2302 movs r3, #2
|
|
8006886: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800688a: e07e b.n 800698a <UART_SetConfig+0x2e6>
|
|
800688c: 2304 movs r3, #4
|
|
800688e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006892: e07a b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006894: 2308 movs r3, #8
|
|
8006896: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800689a: e076 b.n 800698a <UART_SetConfig+0x2e6>
|
|
800689c: 2310 movs r3, #16
|
|
800689e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80068a2: e072 b.n 800698a <UART_SetConfig+0x2e6>
|
|
80068a4: 68fb ldr r3, [r7, #12]
|
|
80068a6: 681b ldr r3, [r3, #0]
|
|
80068a8: 4a35 ldr r2, [pc, #212] @ (8006980 <UART_SetConfig+0x2dc>)
|
|
80068aa: 4293 cmp r3, r2
|
|
80068ac: d12a bne.n 8006904 <UART_SetConfig+0x260>
|
|
80068ae: 4b30 ldr r3, [pc, #192] @ (8006970 <UART_SetConfig+0x2cc>)
|
|
80068b0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80068b4: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80068b8: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80068bc: d01a beq.n 80068f4 <UART_SetConfig+0x250>
|
|
80068be: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80068c2: d81b bhi.n 80068fc <UART_SetConfig+0x258>
|
|
80068c4: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80068c8: d00c beq.n 80068e4 <UART_SetConfig+0x240>
|
|
80068ca: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80068ce: d815 bhi.n 80068fc <UART_SetConfig+0x258>
|
|
80068d0: 2b00 cmp r3, #0
|
|
80068d2: d003 beq.n 80068dc <UART_SetConfig+0x238>
|
|
80068d4: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80068d8: d008 beq.n 80068ec <UART_SetConfig+0x248>
|
|
80068da: e00f b.n 80068fc <UART_SetConfig+0x258>
|
|
80068dc: 2300 movs r3, #0
|
|
80068de: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80068e2: e052 b.n 800698a <UART_SetConfig+0x2e6>
|
|
80068e4: 2302 movs r3, #2
|
|
80068e6: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80068ea: e04e b.n 800698a <UART_SetConfig+0x2e6>
|
|
80068ec: 2304 movs r3, #4
|
|
80068ee: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80068f2: e04a b.n 800698a <UART_SetConfig+0x2e6>
|
|
80068f4: 2308 movs r3, #8
|
|
80068f6: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80068fa: e046 b.n 800698a <UART_SetConfig+0x2e6>
|
|
80068fc: 2310 movs r3, #16
|
|
80068fe: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006902: e042 b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006904: 68fb ldr r3, [r7, #12]
|
|
8006906: 681b ldr r3, [r3, #0]
|
|
8006908: 4a17 ldr r2, [pc, #92] @ (8006968 <UART_SetConfig+0x2c4>)
|
|
800690a: 4293 cmp r3, r2
|
|
800690c: d13a bne.n 8006984 <UART_SetConfig+0x2e0>
|
|
800690e: 4b18 ldr r3, [pc, #96] @ (8006970 <UART_SetConfig+0x2cc>)
|
|
8006910: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006914: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
8006918: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
800691c: d01a beq.n 8006954 <UART_SetConfig+0x2b0>
|
|
800691e: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
8006922: d81b bhi.n 800695c <UART_SetConfig+0x2b8>
|
|
8006924: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8006928: d00c beq.n 8006944 <UART_SetConfig+0x2a0>
|
|
800692a: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
800692e: d815 bhi.n 800695c <UART_SetConfig+0x2b8>
|
|
8006930: 2b00 cmp r3, #0
|
|
8006932: d003 beq.n 800693c <UART_SetConfig+0x298>
|
|
8006934: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8006938: d008 beq.n 800694c <UART_SetConfig+0x2a8>
|
|
800693a: e00f b.n 800695c <UART_SetConfig+0x2b8>
|
|
800693c: 2300 movs r3, #0
|
|
800693e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006942: e022 b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006944: 2302 movs r3, #2
|
|
8006946: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800694a: e01e b.n 800698a <UART_SetConfig+0x2e6>
|
|
800694c: 2304 movs r3, #4
|
|
800694e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006952: e01a b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006954: 2308 movs r3, #8
|
|
8006956: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800695a: e016 b.n 800698a <UART_SetConfig+0x2e6>
|
|
800695c: 2310 movs r3, #16
|
|
800695e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8006962: e012 b.n 800698a <UART_SetConfig+0x2e6>
|
|
8006964: efff69f3 .word 0xefff69f3
|
|
8006968: 40008000 .word 0x40008000
|
|
800696c: 40013800 .word 0x40013800
|
|
8006970: 40021000 .word 0x40021000
|
|
8006974: 40004400 .word 0x40004400
|
|
8006978: 40004800 .word 0x40004800
|
|
800697c: 40004c00 .word 0x40004c00
|
|
8006980: 40005000 .word 0x40005000
|
|
8006984: 2310 movs r3, #16
|
|
8006986: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
|
|
/* Check LPUART instance */
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
800698a: 68fb ldr r3, [r7, #12]
|
|
800698c: 681b ldr r3, [r3, #0]
|
|
800698e: 4a9f ldr r2, [pc, #636] @ (8006c0c <UART_SetConfig+0x568>)
|
|
8006990: 4293 cmp r3, r2
|
|
8006992: d17a bne.n 8006a8a <UART_SetConfig+0x3e6>
|
|
{
|
|
/* Retrieve frequency clock */
|
|
switch (clocksource)
|
|
8006994: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8006998: 2b08 cmp r3, #8
|
|
800699a: d824 bhi.n 80069e6 <UART_SetConfig+0x342>
|
|
800699c: a201 add r2, pc, #4 @ (adr r2, 80069a4 <UART_SetConfig+0x300>)
|
|
800699e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80069a2: bf00 nop
|
|
80069a4: 080069c9 .word 0x080069c9
|
|
80069a8: 080069e7 .word 0x080069e7
|
|
80069ac: 080069d1 .word 0x080069d1
|
|
80069b0: 080069e7 .word 0x080069e7
|
|
80069b4: 080069d7 .word 0x080069d7
|
|
80069b8: 080069e7 .word 0x080069e7
|
|
80069bc: 080069e7 .word 0x080069e7
|
|
80069c0: 080069e7 .word 0x080069e7
|
|
80069c4: 080069df .word 0x080069df
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
80069c8: f7fe ff9a bl 8005900 <HAL_RCC_GetPCLK1Freq>
|
|
80069cc: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80069ce: e010 b.n 80069f2 <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
80069d0: 4b8f ldr r3, [pc, #572] @ (8006c10 <UART_SetConfig+0x56c>)
|
|
80069d2: 61fb str r3, [r7, #28]
|
|
break;
|
|
80069d4: e00d b.n 80069f2 <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
80069d6: f7fe fefb bl 80057d0 <HAL_RCC_GetSysClockFreq>
|
|
80069da: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80069dc: e009 b.n 80069f2 <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
80069de: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80069e2: 61fb str r3, [r7, #28]
|
|
break;
|
|
80069e4: e005 b.n 80069f2 <UART_SetConfig+0x34e>
|
|
default:
|
|
pclk = 0U;
|
|
80069e6: 2300 movs r3, #0
|
|
80069e8: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
80069ea: 2301 movs r3, #1
|
|
80069ec: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
80069f0: bf00 nop
|
|
}
|
|
|
|
/* If proper clock source reported */
|
|
if (pclk != 0U)
|
|
80069f2: 69fb ldr r3, [r7, #28]
|
|
80069f4: 2b00 cmp r3, #0
|
|
80069f6: f000 80fb beq.w 8006bf0 <UART_SetConfig+0x54c>
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
#else
|
|
/* No Prescaler applicable */
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
80069fa: 68fb ldr r3, [r7, #12]
|
|
80069fc: 685a ldr r2, [r3, #4]
|
|
80069fe: 4613 mov r3, r2
|
|
8006a00: 005b lsls r3, r3, #1
|
|
8006a02: 4413 add r3, r2
|
|
8006a04: 69fa ldr r2, [r7, #28]
|
|
8006a06: 429a cmp r2, r3
|
|
8006a08: d305 bcc.n 8006a16 <UART_SetConfig+0x372>
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
|
8006a0a: 68fb ldr r3, [r7, #12]
|
|
8006a0c: 685b ldr r3, [r3, #4]
|
|
8006a0e: 031b lsls r3, r3, #12
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
8006a10: 69fa ldr r2, [r7, #28]
|
|
8006a12: 429a cmp r2, r3
|
|
8006a14: d903 bls.n 8006a1e <UART_SetConfig+0x37a>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006a16: 2301 movs r3, #1
|
|
8006a18: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
8006a1c: e0e8 b.n 8006bf0 <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
|
8006a1e: 69fb ldr r3, [r7, #28]
|
|
8006a20: 2200 movs r2, #0
|
|
8006a22: 461c mov r4, r3
|
|
8006a24: 4615 mov r5, r2
|
|
8006a26: f04f 0200 mov.w r2, #0
|
|
8006a2a: f04f 0300 mov.w r3, #0
|
|
8006a2e: 022b lsls r3, r5, #8
|
|
8006a30: ea43 6314 orr.w r3, r3, r4, lsr #24
|
|
8006a34: 0222 lsls r2, r4, #8
|
|
8006a36: 68f9 ldr r1, [r7, #12]
|
|
8006a38: 6849 ldr r1, [r1, #4]
|
|
8006a3a: 0849 lsrs r1, r1, #1
|
|
8006a3c: 2000 movs r0, #0
|
|
8006a3e: 4688 mov r8, r1
|
|
8006a40: 4681 mov r9, r0
|
|
8006a42: eb12 0a08 adds.w sl, r2, r8
|
|
8006a46: eb43 0b09 adc.w fp, r3, r9
|
|
8006a4a: 68fb ldr r3, [r7, #12]
|
|
8006a4c: 685b ldr r3, [r3, #4]
|
|
8006a4e: 2200 movs r2, #0
|
|
8006a50: 603b str r3, [r7, #0]
|
|
8006a52: 607a str r2, [r7, #4]
|
|
8006a54: e9d7 2300 ldrd r2, r3, [r7]
|
|
8006a58: 4650 mov r0, sl
|
|
8006a5a: 4659 mov r1, fp
|
|
8006a5c: f7fa f8a4 bl 8000ba8 <__aeabi_uldivmod>
|
|
8006a60: 4602 mov r2, r0
|
|
8006a62: 460b mov r3, r1
|
|
8006a64: 4613 mov r3, r2
|
|
8006a66: 61bb str r3, [r7, #24]
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
8006a68: 69bb ldr r3, [r7, #24]
|
|
8006a6a: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8006a6e: d308 bcc.n 8006a82 <UART_SetConfig+0x3de>
|
|
8006a70: 69bb ldr r3, [r7, #24]
|
|
8006a72: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8006a76: d204 bcs.n 8006a82 <UART_SetConfig+0x3de>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
8006a78: 68fb ldr r3, [r7, #12]
|
|
8006a7a: 681b ldr r3, [r3, #0]
|
|
8006a7c: 69ba ldr r2, [r7, #24]
|
|
8006a7e: 60da str r2, [r3, #12]
|
|
8006a80: e0b6 b.n 8006bf0 <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006a82: 2301 movs r3, #1
|
|
8006a84: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
8006a88: e0b2 b.n 8006bf0 <UART_SetConfig+0x54c>
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
} /* if (pclk != 0) */
|
|
}
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8006a8a: 68fb ldr r3, [r7, #12]
|
|
8006a8c: 69db ldr r3, [r3, #28]
|
|
8006a8e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8006a92: d15e bne.n 8006b52 <UART_SetConfig+0x4ae>
|
|
{
|
|
switch (clocksource)
|
|
8006a94: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8006a98: 2b08 cmp r3, #8
|
|
8006a9a: d828 bhi.n 8006aee <UART_SetConfig+0x44a>
|
|
8006a9c: a201 add r2, pc, #4 @ (adr r2, 8006aa4 <UART_SetConfig+0x400>)
|
|
8006a9e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006aa2: bf00 nop
|
|
8006aa4: 08006ac9 .word 0x08006ac9
|
|
8006aa8: 08006ad1 .word 0x08006ad1
|
|
8006aac: 08006ad9 .word 0x08006ad9
|
|
8006ab0: 08006aef .word 0x08006aef
|
|
8006ab4: 08006adf .word 0x08006adf
|
|
8006ab8: 08006aef .word 0x08006aef
|
|
8006abc: 08006aef .word 0x08006aef
|
|
8006ac0: 08006aef .word 0x08006aef
|
|
8006ac4: 08006ae7 .word 0x08006ae7
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006ac8: f7fe ff1a bl 8005900 <HAL_RCC_GetPCLK1Freq>
|
|
8006acc: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8006ace: e014 b.n 8006afa <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8006ad0: f7fe ff2c bl 800592c <HAL_RCC_GetPCLK2Freq>
|
|
8006ad4: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8006ad6: e010 b.n 8006afa <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8006ad8: 4b4d ldr r3, [pc, #308] @ (8006c10 <UART_SetConfig+0x56c>)
|
|
8006ada: 61fb str r3, [r7, #28]
|
|
break;
|
|
8006adc: e00d b.n 8006afa <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8006ade: f7fe fe77 bl 80057d0 <HAL_RCC_GetSysClockFreq>
|
|
8006ae2: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8006ae4: e009 b.n 8006afa <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8006ae6: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8006aea: 61fb str r3, [r7, #28]
|
|
break;
|
|
8006aec: e005 b.n 8006afa <UART_SetConfig+0x456>
|
|
default:
|
|
pclk = 0U;
|
|
8006aee: 2300 movs r3, #0
|
|
8006af0: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
8006af2: 2301 movs r3, #1
|
|
8006af4: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
8006af8: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
8006afa: 69fb ldr r3, [r7, #28]
|
|
8006afc: 2b00 cmp r3, #0
|
|
8006afe: d077 beq.n 8006bf0 <UART_SetConfig+0x54c>
|
|
{
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
8006b00: 69fb ldr r3, [r7, #28]
|
|
8006b02: 005a lsls r2, r3, #1
|
|
8006b04: 68fb ldr r3, [r7, #12]
|
|
8006b06: 685b ldr r3, [r3, #4]
|
|
8006b08: 085b lsrs r3, r3, #1
|
|
8006b0a: 441a add r2, r3
|
|
8006b0c: 68fb ldr r3, [r7, #12]
|
|
8006b0e: 685b ldr r3, [r3, #4]
|
|
8006b10: fbb2 f3f3 udiv r3, r2, r3
|
|
8006b14: 61bb str r3, [r7, #24]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8006b16: 69bb ldr r3, [r7, #24]
|
|
8006b18: 2b0f cmp r3, #15
|
|
8006b1a: d916 bls.n 8006b4a <UART_SetConfig+0x4a6>
|
|
8006b1c: 69bb ldr r3, [r7, #24]
|
|
8006b1e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8006b22: d212 bcs.n 8006b4a <UART_SetConfig+0x4a6>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8006b24: 69bb ldr r3, [r7, #24]
|
|
8006b26: b29b uxth r3, r3
|
|
8006b28: f023 030f bic.w r3, r3, #15
|
|
8006b2c: 82fb strh r3, [r7, #22]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
8006b2e: 69bb ldr r3, [r7, #24]
|
|
8006b30: 085b lsrs r3, r3, #1
|
|
8006b32: b29b uxth r3, r3
|
|
8006b34: f003 0307 and.w r3, r3, #7
|
|
8006b38: b29a uxth r2, r3
|
|
8006b3a: 8afb ldrh r3, [r7, #22]
|
|
8006b3c: 4313 orrs r3, r2
|
|
8006b3e: 82fb strh r3, [r7, #22]
|
|
huart->Instance->BRR = brrtemp;
|
|
8006b40: 68fb ldr r3, [r7, #12]
|
|
8006b42: 681b ldr r3, [r3, #0]
|
|
8006b44: 8afa ldrh r2, [r7, #22]
|
|
8006b46: 60da str r2, [r3, #12]
|
|
8006b48: e052 b.n 8006bf0 <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006b4a: 2301 movs r3, #1
|
|
8006b4c: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
8006b50: e04e b.n 8006bf0 <UART_SetConfig+0x54c>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
8006b52: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8006b56: 2b08 cmp r3, #8
|
|
8006b58: d827 bhi.n 8006baa <UART_SetConfig+0x506>
|
|
8006b5a: a201 add r2, pc, #4 @ (adr r2, 8006b60 <UART_SetConfig+0x4bc>)
|
|
8006b5c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006b60: 08006b85 .word 0x08006b85
|
|
8006b64: 08006b8d .word 0x08006b8d
|
|
8006b68: 08006b95 .word 0x08006b95
|
|
8006b6c: 08006bab .word 0x08006bab
|
|
8006b70: 08006b9b .word 0x08006b9b
|
|
8006b74: 08006bab .word 0x08006bab
|
|
8006b78: 08006bab .word 0x08006bab
|
|
8006b7c: 08006bab .word 0x08006bab
|
|
8006b80: 08006ba3 .word 0x08006ba3
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006b84: f7fe febc bl 8005900 <HAL_RCC_GetPCLK1Freq>
|
|
8006b88: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8006b8a: e014 b.n 8006bb6 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8006b8c: f7fe fece bl 800592c <HAL_RCC_GetPCLK2Freq>
|
|
8006b90: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8006b92: e010 b.n 8006bb6 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8006b94: 4b1e ldr r3, [pc, #120] @ (8006c10 <UART_SetConfig+0x56c>)
|
|
8006b96: 61fb str r3, [r7, #28]
|
|
break;
|
|
8006b98: e00d b.n 8006bb6 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8006b9a: f7fe fe19 bl 80057d0 <HAL_RCC_GetSysClockFreq>
|
|
8006b9e: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8006ba0: e009 b.n 8006bb6 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8006ba2: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8006ba6: 61fb str r3, [r7, #28]
|
|
break;
|
|
8006ba8: e005 b.n 8006bb6 <UART_SetConfig+0x512>
|
|
default:
|
|
pclk = 0U;
|
|
8006baa: 2300 movs r3, #0
|
|
8006bac: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
8006bae: 2301 movs r3, #1
|
|
8006bb0: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
8006bb4: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
8006bb6: 69fb ldr r3, [r7, #28]
|
|
8006bb8: 2b00 cmp r3, #0
|
|
8006bba: d019 beq.n 8006bf0 <UART_SetConfig+0x54c>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
8006bbc: 68fb ldr r3, [r7, #12]
|
|
8006bbe: 685b ldr r3, [r3, #4]
|
|
8006bc0: 085a lsrs r2, r3, #1
|
|
8006bc2: 69fb ldr r3, [r7, #28]
|
|
8006bc4: 441a add r2, r3
|
|
8006bc6: 68fb ldr r3, [r7, #12]
|
|
8006bc8: 685b ldr r3, [r3, #4]
|
|
8006bca: fbb2 f3f3 udiv r3, r2, r3
|
|
8006bce: 61bb str r3, [r7, #24]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8006bd0: 69bb ldr r3, [r7, #24]
|
|
8006bd2: 2b0f cmp r3, #15
|
|
8006bd4: d909 bls.n 8006bea <UART_SetConfig+0x546>
|
|
8006bd6: 69bb ldr r3, [r7, #24]
|
|
8006bd8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8006bdc: d205 bcs.n 8006bea <UART_SetConfig+0x546>
|
|
{
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
8006bde: 69bb ldr r3, [r7, #24]
|
|
8006be0: b29a uxth r2, r3
|
|
8006be2: 68fb ldr r3, [r7, #12]
|
|
8006be4: 681b ldr r3, [r3, #0]
|
|
8006be6: 60da str r2, [r3, #12]
|
|
8006be8: e002 b.n 8006bf0 <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006bea: 2301 movs r3, #1
|
|
8006bec: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
huart->NbTxDataToProcess = 1;
|
|
huart->NbRxDataToProcess = 1;
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
8006bf0: 68fb ldr r3, [r7, #12]
|
|
8006bf2: 2200 movs r2, #0
|
|
8006bf4: 669a str r2, [r3, #104] @ 0x68
|
|
huart->TxISR = NULL;
|
|
8006bf6: 68fb ldr r3, [r7, #12]
|
|
8006bf8: 2200 movs r2, #0
|
|
8006bfa: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
return ret;
|
|
8006bfc: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
|
|
}
|
|
8006c00: 4618 mov r0, r3
|
|
8006c02: 3728 adds r7, #40 @ 0x28
|
|
8006c04: 46bd mov sp, r7
|
|
8006c06: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8006c0a: bf00 nop
|
|
8006c0c: 40008000 .word 0x40008000
|
|
8006c10: 00f42400 .word 0x00f42400
|
|
|
|
08006c14 <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8006c14: b480 push {r7}
|
|
8006c16: b083 sub sp, #12
|
|
8006c18: af00 add r7, sp, #0
|
|
8006c1a: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
8006c1c: 687b ldr r3, [r7, #4]
|
|
8006c1e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006c20: f003 0308 and.w r3, r3, #8
|
|
8006c24: 2b00 cmp r3, #0
|
|
8006c26: d00a beq.n 8006c3e <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
8006c28: 687b ldr r3, [r7, #4]
|
|
8006c2a: 681b ldr r3, [r3, #0]
|
|
8006c2c: 685b ldr r3, [r3, #4]
|
|
8006c2e: f423 4100 bic.w r1, r3, #32768 @ 0x8000
|
|
8006c32: 687b ldr r3, [r7, #4]
|
|
8006c34: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8006c36: 687b ldr r3, [r7, #4]
|
|
8006c38: 681b ldr r3, [r3, #0]
|
|
8006c3a: 430a orrs r2, r1
|
|
8006c3c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
8006c3e: 687b ldr r3, [r7, #4]
|
|
8006c40: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006c42: f003 0301 and.w r3, r3, #1
|
|
8006c46: 2b00 cmp r3, #0
|
|
8006c48: d00a beq.n 8006c60 <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
8006c4a: 687b ldr r3, [r7, #4]
|
|
8006c4c: 681b ldr r3, [r3, #0]
|
|
8006c4e: 685b ldr r3, [r3, #4]
|
|
8006c50: f423 3100 bic.w r1, r3, #131072 @ 0x20000
|
|
8006c54: 687b ldr r3, [r7, #4]
|
|
8006c56: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
8006c58: 687b ldr r3, [r7, #4]
|
|
8006c5a: 681b ldr r3, [r3, #0]
|
|
8006c5c: 430a orrs r2, r1
|
|
8006c5e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8006c60: 687b ldr r3, [r7, #4]
|
|
8006c62: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006c64: f003 0302 and.w r3, r3, #2
|
|
8006c68: 2b00 cmp r3, #0
|
|
8006c6a: d00a beq.n 8006c82 <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
8006c6c: 687b ldr r3, [r7, #4]
|
|
8006c6e: 681b ldr r3, [r3, #0]
|
|
8006c70: 685b ldr r3, [r3, #4]
|
|
8006c72: f423 3180 bic.w r1, r3, #65536 @ 0x10000
|
|
8006c76: 687b ldr r3, [r7, #4]
|
|
8006c78: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8006c7a: 687b ldr r3, [r7, #4]
|
|
8006c7c: 681b ldr r3, [r3, #0]
|
|
8006c7e: 430a orrs r2, r1
|
|
8006c80: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8006c82: 687b ldr r3, [r7, #4]
|
|
8006c84: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006c86: f003 0304 and.w r3, r3, #4
|
|
8006c8a: 2b00 cmp r3, #0
|
|
8006c8c: d00a beq.n 8006ca4 <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
8006c8e: 687b ldr r3, [r7, #4]
|
|
8006c90: 681b ldr r3, [r3, #0]
|
|
8006c92: 685b ldr r3, [r3, #4]
|
|
8006c94: f423 2180 bic.w r1, r3, #262144 @ 0x40000
|
|
8006c98: 687b ldr r3, [r7, #4]
|
|
8006c9a: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8006c9c: 687b ldr r3, [r7, #4]
|
|
8006c9e: 681b ldr r3, [r3, #0]
|
|
8006ca0: 430a orrs r2, r1
|
|
8006ca2: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8006ca4: 687b ldr r3, [r7, #4]
|
|
8006ca6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006ca8: f003 0310 and.w r3, r3, #16
|
|
8006cac: 2b00 cmp r3, #0
|
|
8006cae: d00a beq.n 8006cc6 <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
8006cb0: 687b ldr r3, [r7, #4]
|
|
8006cb2: 681b ldr r3, [r3, #0]
|
|
8006cb4: 689b ldr r3, [r3, #8]
|
|
8006cb6: f423 5180 bic.w r1, r3, #4096 @ 0x1000
|
|
8006cba: 687b ldr r3, [r7, #4]
|
|
8006cbc: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8006cbe: 687b ldr r3, [r7, #4]
|
|
8006cc0: 681b ldr r3, [r3, #0]
|
|
8006cc2: 430a orrs r2, r1
|
|
8006cc4: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8006cc6: 687b ldr r3, [r7, #4]
|
|
8006cc8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006cca: f003 0320 and.w r3, r3, #32
|
|
8006cce: 2b00 cmp r3, #0
|
|
8006cd0: d00a beq.n 8006ce8 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
8006cd2: 687b ldr r3, [r7, #4]
|
|
8006cd4: 681b ldr r3, [r3, #0]
|
|
8006cd6: 689b ldr r3, [r3, #8]
|
|
8006cd8: f423 5100 bic.w r1, r3, #8192 @ 0x2000
|
|
8006cdc: 687b ldr r3, [r7, #4]
|
|
8006cde: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8006ce0: 687b ldr r3, [r7, #4]
|
|
8006ce2: 681b ldr r3, [r3, #0]
|
|
8006ce4: 430a orrs r2, r1
|
|
8006ce6: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
8006ce8: 687b ldr r3, [r7, #4]
|
|
8006cea: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006cec: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006cf0: 2b00 cmp r3, #0
|
|
8006cf2: d01a beq.n 8006d2a <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
8006cf4: 687b ldr r3, [r7, #4]
|
|
8006cf6: 681b ldr r3, [r3, #0]
|
|
8006cf8: 685b ldr r3, [r3, #4]
|
|
8006cfa: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
|
|
8006cfe: 687b ldr r3, [r7, #4]
|
|
8006d00: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8006d02: 687b ldr r3, [r7, #4]
|
|
8006d04: 681b ldr r3, [r3, #0]
|
|
8006d06: 430a orrs r2, r1
|
|
8006d08: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
8006d0a: 687b ldr r3, [r7, #4]
|
|
8006d0c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8006d0e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8006d12: d10a bne.n 8006d2a <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
8006d14: 687b ldr r3, [r7, #4]
|
|
8006d16: 681b ldr r3, [r3, #0]
|
|
8006d18: 685b ldr r3, [r3, #4]
|
|
8006d1a: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
|
|
8006d1e: 687b ldr r3, [r7, #4]
|
|
8006d20: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8006d22: 687b ldr r3, [r7, #4]
|
|
8006d24: 681b ldr r3, [r3, #0]
|
|
8006d26: 430a orrs r2, r1
|
|
8006d28: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
8006d2a: 687b ldr r3, [r7, #4]
|
|
8006d2c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006d2e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006d32: 2b00 cmp r3, #0
|
|
8006d34: d00a beq.n 8006d4c <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
8006d36: 687b ldr r3, [r7, #4]
|
|
8006d38: 681b ldr r3, [r3, #0]
|
|
8006d3a: 685b ldr r3, [r3, #4]
|
|
8006d3c: f423 2100 bic.w r1, r3, #524288 @ 0x80000
|
|
8006d40: 687b ldr r3, [r7, #4]
|
|
8006d42: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
8006d44: 687b ldr r3, [r7, #4]
|
|
8006d46: 681b ldr r3, [r3, #0]
|
|
8006d48: 430a orrs r2, r1
|
|
8006d4a: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
8006d4c: bf00 nop
|
|
8006d4e: 370c adds r7, #12
|
|
8006d50: 46bd mov sp, r7
|
|
8006d52: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d56: 4770 bx lr
|
|
|
|
08006d58 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8006d58: b580 push {r7, lr}
|
|
8006d5a: b098 sub sp, #96 @ 0x60
|
|
8006d5c: af02 add r7, sp, #8
|
|
8006d5e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006d60: 687b ldr r3, [r7, #4]
|
|
8006d62: 2200 movs r2, #0
|
|
8006d64: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8006d68: f7fc fa6a bl 8003240 <HAL_GetTick>
|
|
8006d6c: 6578 str r0, [r7, #84] @ 0x54
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
8006d6e: 687b ldr r3, [r7, #4]
|
|
8006d70: 681b ldr r3, [r3, #0]
|
|
8006d72: 681b ldr r3, [r3, #0]
|
|
8006d74: f003 0308 and.w r3, r3, #8
|
|
8006d78: 2b08 cmp r3, #8
|
|
8006d7a: d12e bne.n 8006dda <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8006d7c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8006d80: 9300 str r3, [sp, #0]
|
|
8006d82: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8006d84: 2200 movs r2, #0
|
|
8006d86: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
8006d8a: 6878 ldr r0, [r7, #4]
|
|
8006d8c: f000 f88c bl 8006ea8 <UART_WaitOnFlagUntilTimeout>
|
|
8006d90: 4603 mov r3, r0
|
|
8006d92: 2b00 cmp r3, #0
|
|
8006d94: d021 beq.n 8006dda <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
|
|
8006d96: 687b ldr r3, [r7, #4]
|
|
8006d98: 681b ldr r3, [r3, #0]
|
|
8006d9a: 63bb str r3, [r7, #56] @ 0x38
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006d9c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006d9e: e853 3f00 ldrex r3, [r3]
|
|
8006da2: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8006da4: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006da6: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8006daa: 653b str r3, [r7, #80] @ 0x50
|
|
8006dac: 687b ldr r3, [r7, #4]
|
|
8006dae: 681b ldr r3, [r3, #0]
|
|
8006db0: 461a mov r2, r3
|
|
8006db2: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8006db4: 647b str r3, [r7, #68] @ 0x44
|
|
8006db6: 643a str r2, [r7, #64] @ 0x40
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006db8: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8006dba: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8006dbc: e841 2300 strex r3, r2, [r1]
|
|
8006dc0: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8006dc2: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006dc4: 2b00 cmp r3, #0
|
|
8006dc6: d1e6 bne.n 8006d96 <UART_CheckIdleState+0x3e>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006dc8: 687b ldr r3, [r7, #4]
|
|
8006dca: 2220 movs r2, #32
|
|
8006dcc: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006dce: 687b ldr r3, [r7, #4]
|
|
8006dd0: 2200 movs r2, #0
|
|
8006dd2: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8006dd6: 2303 movs r3, #3
|
|
8006dd8: e062 b.n 8006ea0 <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
8006dda: 687b ldr r3, [r7, #4]
|
|
8006ddc: 681b ldr r3, [r3, #0]
|
|
8006dde: 681b ldr r3, [r3, #0]
|
|
8006de0: f003 0304 and.w r3, r3, #4
|
|
8006de4: 2b04 cmp r3, #4
|
|
8006de6: d149 bne.n 8006e7c <UART_CheckIdleState+0x124>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8006de8: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8006dec: 9300 str r3, [sp, #0]
|
|
8006dee: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8006df0: 2200 movs r2, #0
|
|
8006df2: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
8006df6: 6878 ldr r0, [r7, #4]
|
|
8006df8: f000 f856 bl 8006ea8 <UART_WaitOnFlagUntilTimeout>
|
|
8006dfc: 4603 mov r3, r0
|
|
8006dfe: 2b00 cmp r3, #0
|
|
8006e00: d03c beq.n 8006e7c <UART_CheckIdleState+0x124>
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8006e02: 687b ldr r3, [r7, #4]
|
|
8006e04: 681b ldr r3, [r3, #0]
|
|
8006e06: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006e08: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006e0a: e853 3f00 ldrex r3, [r3]
|
|
8006e0e: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006e10: 6a3b ldr r3, [r7, #32]
|
|
8006e12: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006e16: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006e18: 687b ldr r3, [r7, #4]
|
|
8006e1a: 681b ldr r3, [r3, #0]
|
|
8006e1c: 461a mov r2, r3
|
|
8006e1e: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006e20: 633b str r3, [r7, #48] @ 0x30
|
|
8006e22: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006e24: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8006e26: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8006e28: e841 2300 strex r3, r2, [r1]
|
|
8006e2c: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006e2e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006e30: 2b00 cmp r3, #0
|
|
8006e32: d1e6 bne.n 8006e02 <UART_CheckIdleState+0xaa>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006e34: 687b ldr r3, [r7, #4]
|
|
8006e36: 681b ldr r3, [r3, #0]
|
|
8006e38: 3308 adds r3, #8
|
|
8006e3a: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006e3c: 693b ldr r3, [r7, #16]
|
|
8006e3e: e853 3f00 ldrex r3, [r3]
|
|
8006e42: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006e44: 68fb ldr r3, [r7, #12]
|
|
8006e46: f023 0301 bic.w r3, r3, #1
|
|
8006e4a: 64bb str r3, [r7, #72] @ 0x48
|
|
8006e4c: 687b ldr r3, [r7, #4]
|
|
8006e4e: 681b ldr r3, [r3, #0]
|
|
8006e50: 3308 adds r3, #8
|
|
8006e52: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006e54: 61fa str r2, [r7, #28]
|
|
8006e56: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006e58: 69b9 ldr r1, [r7, #24]
|
|
8006e5a: 69fa ldr r2, [r7, #28]
|
|
8006e5c: e841 2300 strex r3, r2, [r1]
|
|
8006e60: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006e62: 697b ldr r3, [r7, #20]
|
|
8006e64: 2b00 cmp r3, #0
|
|
8006e66: d1e5 bne.n 8006e34 <UART_CheckIdleState+0xdc>
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006e68: 687b ldr r3, [r7, #4]
|
|
8006e6a: 2220 movs r2, #32
|
|
8006e6c: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006e70: 687b ldr r3, [r7, #4]
|
|
8006e72: 2200 movs r2, #0
|
|
8006e74: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8006e78: 2303 movs r3, #3
|
|
8006e7a: e011 b.n 8006ea0 <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006e7c: 687b ldr r3, [r7, #4]
|
|
8006e7e: 2220 movs r2, #32
|
|
8006e80: 67da str r2, [r3, #124] @ 0x7c
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006e82: 687b ldr r3, [r7, #4]
|
|
8006e84: 2220 movs r2, #32
|
|
8006e86: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006e8a: 687b ldr r3, [r7, #4]
|
|
8006e8c: 2200 movs r2, #0
|
|
8006e8e: 661a str r2, [r3, #96] @ 0x60
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8006e90: 687b ldr r3, [r7, #4]
|
|
8006e92: 2200 movs r2, #0
|
|
8006e94: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006e96: 687b ldr r3, [r7, #4]
|
|
8006e98: 2200 movs r2, #0
|
|
8006e9a: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_OK;
|
|
8006e9e: 2300 movs r3, #0
|
|
}
|
|
8006ea0: 4618 mov r0, r3
|
|
8006ea2: 3758 adds r7, #88 @ 0x58
|
|
8006ea4: 46bd mov sp, r7
|
|
8006ea6: bd80 pop {r7, pc}
|
|
|
|
08006ea8 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8006ea8: b580 push {r7, lr}
|
|
8006eaa: b084 sub sp, #16
|
|
8006eac: af00 add r7, sp, #0
|
|
8006eae: 60f8 str r0, [r7, #12]
|
|
8006eb0: 60b9 str r1, [r7, #8]
|
|
8006eb2: 603b str r3, [r7, #0]
|
|
8006eb4: 4613 mov r3, r2
|
|
8006eb6: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8006eb8: e04f b.n 8006f5a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8006eba: 69bb ldr r3, [r7, #24]
|
|
8006ebc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8006ec0: d04b beq.n 8006f5a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8006ec2: f7fc f9bd bl 8003240 <HAL_GetTick>
|
|
8006ec6: 4602 mov r2, r0
|
|
8006ec8: 683b ldr r3, [r7, #0]
|
|
8006eca: 1ad3 subs r3, r2, r3
|
|
8006ecc: 69ba ldr r2, [r7, #24]
|
|
8006ece: 429a cmp r2, r3
|
|
8006ed0: d302 bcc.n 8006ed8 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
8006ed2: 69bb ldr r3, [r7, #24]
|
|
8006ed4: 2b00 cmp r3, #0
|
|
8006ed6: d101 bne.n 8006edc <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
8006ed8: 2303 movs r3, #3
|
|
8006eda: e04e b.n 8006f7a <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
8006edc: 68fb ldr r3, [r7, #12]
|
|
8006ede: 681b ldr r3, [r3, #0]
|
|
8006ee0: 681b ldr r3, [r3, #0]
|
|
8006ee2: f003 0304 and.w r3, r3, #4
|
|
8006ee6: 2b00 cmp r3, #0
|
|
8006ee8: d037 beq.n 8006f5a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8006eea: 68bb ldr r3, [r7, #8]
|
|
8006eec: 2b80 cmp r3, #128 @ 0x80
|
|
8006eee: d034 beq.n 8006f5a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8006ef0: 68bb ldr r3, [r7, #8]
|
|
8006ef2: 2b40 cmp r3, #64 @ 0x40
|
|
8006ef4: d031 beq.n 8006f5a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
8006ef6: 68fb ldr r3, [r7, #12]
|
|
8006ef8: 681b ldr r3, [r3, #0]
|
|
8006efa: 69db ldr r3, [r3, #28]
|
|
8006efc: f003 0308 and.w r3, r3, #8
|
|
8006f00: 2b08 cmp r3, #8
|
|
8006f02: d110 bne.n 8006f26 <UART_WaitOnFlagUntilTimeout+0x7e>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8006f04: 68fb ldr r3, [r7, #12]
|
|
8006f06: 681b ldr r3, [r3, #0]
|
|
8006f08: 2208 movs r2, #8
|
|
8006f0a: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8006f0c: 68f8 ldr r0, [r7, #12]
|
|
8006f0e: f000 f838 bl 8006f82 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
8006f12: 68fb ldr r3, [r7, #12]
|
|
8006f14: 2208 movs r2, #8
|
|
8006f16: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8006f1a: 68fb ldr r3, [r7, #12]
|
|
8006f1c: 2200 movs r2, #0
|
|
8006f1e: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_ERROR;
|
|
8006f22: 2301 movs r3, #1
|
|
8006f24: e029 b.n 8006f7a <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
8006f26: 68fb ldr r3, [r7, #12]
|
|
8006f28: 681b ldr r3, [r3, #0]
|
|
8006f2a: 69db ldr r3, [r3, #28]
|
|
8006f2c: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8006f30: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8006f34: d111 bne.n 8006f5a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8006f36: 68fb ldr r3, [r7, #12]
|
|
8006f38: 681b ldr r3, [r3, #0]
|
|
8006f3a: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8006f3e: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8006f40: 68f8 ldr r0, [r7, #12]
|
|
8006f42: f000 f81e bl 8006f82 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
8006f46: 68fb ldr r3, [r7, #12]
|
|
8006f48: 2220 movs r2, #32
|
|
8006f4a: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8006f4e: 68fb ldr r3, [r7, #12]
|
|
8006f50: 2200 movs r2, #0
|
|
8006f52: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_TIMEOUT;
|
|
8006f56: 2303 movs r3, #3
|
|
8006f58: e00f b.n 8006f7a <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8006f5a: 68fb ldr r3, [r7, #12]
|
|
8006f5c: 681b ldr r3, [r3, #0]
|
|
8006f5e: 69da ldr r2, [r3, #28]
|
|
8006f60: 68bb ldr r3, [r7, #8]
|
|
8006f62: 4013 ands r3, r2
|
|
8006f64: 68ba ldr r2, [r7, #8]
|
|
8006f66: 429a cmp r2, r3
|
|
8006f68: bf0c ite eq
|
|
8006f6a: 2301 moveq r3, #1
|
|
8006f6c: 2300 movne r3, #0
|
|
8006f6e: b2db uxtb r3, r3
|
|
8006f70: 461a mov r2, r3
|
|
8006f72: 79fb ldrb r3, [r7, #7]
|
|
8006f74: 429a cmp r2, r3
|
|
8006f76: d0a0 beq.n 8006eba <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8006f78: 2300 movs r3, #0
|
|
}
|
|
8006f7a: 4618 mov r0, r3
|
|
8006f7c: 3710 adds r7, #16
|
|
8006f7e: 46bd mov sp, r7
|
|
8006f80: bd80 pop {r7, pc}
|
|
|
|
08006f82 <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
8006f82: b480 push {r7}
|
|
8006f84: b095 sub sp, #84 @ 0x54
|
|
8006f86: af00 add r7, sp, #0
|
|
8006f88: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8006f8a: 687b ldr r3, [r7, #4]
|
|
8006f8c: 681b ldr r3, [r3, #0]
|
|
8006f8e: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006f90: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006f92: e853 3f00 ldrex r3, [r3]
|
|
8006f96: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8006f98: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006f9a: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006f9e: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006fa0: 687b ldr r3, [r7, #4]
|
|
8006fa2: 681b ldr r3, [r3, #0]
|
|
8006fa4: 461a mov r2, r3
|
|
8006fa6: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006fa8: 643b str r3, [r7, #64] @ 0x40
|
|
8006faa: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006fac: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8006fae: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8006fb0: e841 2300 strex r3, r2, [r1]
|
|
8006fb4: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8006fb6: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006fb8: 2b00 cmp r3, #0
|
|
8006fba: d1e6 bne.n 8006f8a <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006fbc: 687b ldr r3, [r7, #4]
|
|
8006fbe: 681b ldr r3, [r3, #0]
|
|
8006fc0: 3308 adds r3, #8
|
|
8006fc2: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006fc4: 6a3b ldr r3, [r7, #32]
|
|
8006fc6: e853 3f00 ldrex r3, [r3]
|
|
8006fca: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8006fcc: 69fb ldr r3, [r7, #28]
|
|
8006fce: f023 0301 bic.w r3, r3, #1
|
|
8006fd2: 64bb str r3, [r7, #72] @ 0x48
|
|
8006fd4: 687b ldr r3, [r7, #4]
|
|
8006fd6: 681b ldr r3, [r3, #0]
|
|
8006fd8: 3308 adds r3, #8
|
|
8006fda: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006fdc: 62fa str r2, [r7, #44] @ 0x2c
|
|
8006fde: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006fe0: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8006fe2: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8006fe4: e841 2300 strex r3, r2, [r1]
|
|
8006fe8: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006fea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006fec: 2b00 cmp r3, #0
|
|
8006fee: d1e5 bne.n 8006fbc <UART_EndRxTransfer+0x3a>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006ff0: 687b ldr r3, [r7, #4]
|
|
8006ff2: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8006ff4: 2b01 cmp r3, #1
|
|
8006ff6: d118 bne.n 800702a <UART_EndRxTransfer+0xa8>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006ff8: 687b ldr r3, [r7, #4]
|
|
8006ffa: 681b ldr r3, [r3, #0]
|
|
8006ffc: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006ffe: 68fb ldr r3, [r7, #12]
|
|
8007000: e853 3f00 ldrex r3, [r3]
|
|
8007004: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8007006: 68bb ldr r3, [r7, #8]
|
|
8007008: f023 0310 bic.w r3, r3, #16
|
|
800700c: 647b str r3, [r7, #68] @ 0x44
|
|
800700e: 687b ldr r3, [r7, #4]
|
|
8007010: 681b ldr r3, [r3, #0]
|
|
8007012: 461a mov r2, r3
|
|
8007014: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8007016: 61bb str r3, [r7, #24]
|
|
8007018: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800701a: 6979 ldr r1, [r7, #20]
|
|
800701c: 69ba ldr r2, [r7, #24]
|
|
800701e: e841 2300 strex r3, r2, [r1]
|
|
8007022: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8007024: 693b ldr r3, [r7, #16]
|
|
8007026: 2b00 cmp r3, #0
|
|
8007028: d1e6 bne.n 8006ff8 <UART_EndRxTransfer+0x76>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800702a: 687b ldr r3, [r7, #4]
|
|
800702c: 2220 movs r2, #32
|
|
800702e: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8007032: 687b ldr r3, [r7, #4]
|
|
8007034: 2200 movs r2, #0
|
|
8007036: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
8007038: 687b ldr r3, [r7, #4]
|
|
800703a: 2200 movs r2, #0
|
|
800703c: 669a str r2, [r3, #104] @ 0x68
|
|
}
|
|
800703e: bf00 nop
|
|
8007040: 3754 adds r7, #84 @ 0x54
|
|
8007042: 46bd mov sp, r7
|
|
8007044: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007048: 4770 bx lr
|
|
|
|
0800704a <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
800704a: b084 sub sp, #16
|
|
800704c: b580 push {r7, lr}
|
|
800704e: b084 sub sp, #16
|
|
8007050: af00 add r7, sp, #0
|
|
8007052: 6078 str r0, [r7, #4]
|
|
8007054: f107 001c add.w r0, r7, #28
|
|
8007058: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret;
|
|
|
|
/* Select FS Embedded PHY */
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
|
800705c: 687b ldr r3, [r7, #4]
|
|
800705e: 68db ldr r3, [r3, #12]
|
|
8007060: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8007064: 687b ldr r3, [r7, #4]
|
|
8007066: 60da str r2, [r3, #12]
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8007068: 6878 ldr r0, [r7, #4]
|
|
800706a: f000 fa69 bl 8007540 <USB_CoreReset>
|
|
800706e: 4603 mov r3, r0
|
|
8007070: 73fb strb r3, [r7, #15]
|
|
|
|
if (cfg.battery_charging_enable == 0U)
|
|
8007072: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
8007076: 2b00 cmp r3, #0
|
|
8007078: d106 bne.n 8007088 <USB_CoreInit+0x3e>
|
|
{
|
|
/* Activate the USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
800707a: 687b ldr r3, [r7, #4]
|
|
800707c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800707e: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8007082: 687b ldr r3, [r7, #4]
|
|
8007084: 639a str r2, [r3, #56] @ 0x38
|
|
8007086: e005 b.n 8007094 <USB_CoreInit+0x4a>
|
|
}
|
|
else
|
|
{
|
|
/* Deactivate the USB Transceiver */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8007088: 687b ldr r3, [r7, #4]
|
|
800708a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800708c: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8007090: 687b ldr r3, [r7, #4]
|
|
8007092: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
return ret;
|
|
8007094: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007096: 4618 mov r0, r3
|
|
8007098: 3710 adds r7, #16
|
|
800709a: 46bd mov sp, r7
|
|
800709c: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
80070a0: b004 add sp, #16
|
|
80070a2: 4770 bx lr
|
|
|
|
080070a4 <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80070a4: b480 push {r7}
|
|
80070a6: b083 sub sp, #12
|
|
80070a8: af00 add r7, sp, #0
|
|
80070aa: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
80070ac: 687b ldr r3, [r7, #4]
|
|
80070ae: 689b ldr r3, [r3, #8]
|
|
80070b0: f023 0201 bic.w r2, r3, #1
|
|
80070b4: 687b ldr r3, [r7, #4]
|
|
80070b6: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
80070b8: 2300 movs r3, #0
|
|
}
|
|
80070ba: 4618 mov r0, r3
|
|
80070bc: 370c adds r7, #12
|
|
80070be: 46bd mov sp, r7
|
|
80070c0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80070c4: 4770 bx lr
|
|
|
|
080070c6 <USB_SetCurrentMode>:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @arg USB_HOST_MODE Host mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
|
|
{
|
|
80070c6: b580 push {r7, lr}
|
|
80070c8: b084 sub sp, #16
|
|
80070ca: af00 add r7, sp, #0
|
|
80070cc: 6078 str r0, [r7, #4]
|
|
80070ce: 460b mov r3, r1
|
|
80070d0: 70fb strb r3, [r7, #3]
|
|
uint32_t ms = 0U;
|
|
80070d2: 2300 movs r3, #0
|
|
80070d4: 60fb str r3, [r7, #12]
|
|
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
|
80070d6: 687b ldr r3, [r7, #4]
|
|
80070d8: 68db ldr r3, [r3, #12]
|
|
80070da: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
|
|
80070de: 687b ldr r3, [r7, #4]
|
|
80070e0: 60da str r2, [r3, #12]
|
|
|
|
if (mode == USB_HOST_MODE)
|
|
80070e2: 78fb ldrb r3, [r7, #3]
|
|
80070e4: 2b01 cmp r3, #1
|
|
80070e6: d115 bne.n 8007114 <USB_SetCurrentMode+0x4e>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
|
|
80070e8: 687b ldr r3, [r7, #4]
|
|
80070ea: 68db ldr r3, [r3, #12]
|
|
80070ec: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
|
|
80070f0: 687b ldr r3, [r7, #4]
|
|
80070f2: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
80070f4: 200a movs r0, #10
|
|
80070f6: f7fc f8af bl 8003258 <HAL_Delay>
|
|
ms += 10U;
|
|
80070fa: 68fb ldr r3, [r7, #12]
|
|
80070fc: 330a adds r3, #10
|
|
80070fe: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8007100: 6878 ldr r0, [r7, #4]
|
|
8007102: f000 fa0f bl 8007524 <USB_GetMode>
|
|
8007106: 4603 mov r3, r0
|
|
8007108: 2b01 cmp r3, #1
|
|
800710a: d01e beq.n 800714a <USB_SetCurrentMode+0x84>
|
|
800710c: 68fb ldr r3, [r7, #12]
|
|
800710e: 2bc7 cmp r3, #199 @ 0xc7
|
|
8007110: d9f0 bls.n 80070f4 <USB_SetCurrentMode+0x2e>
|
|
8007112: e01a b.n 800714a <USB_SetCurrentMode+0x84>
|
|
}
|
|
else if (mode == USB_DEVICE_MODE)
|
|
8007114: 78fb ldrb r3, [r7, #3]
|
|
8007116: 2b00 cmp r3, #0
|
|
8007118: d115 bne.n 8007146 <USB_SetCurrentMode+0x80>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
|
800711a: 687b ldr r3, [r7, #4]
|
|
800711c: 68db ldr r3, [r3, #12]
|
|
800711e: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
|
|
8007122: 687b ldr r3, [r7, #4]
|
|
8007124: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
8007126: 200a movs r0, #10
|
|
8007128: f7fc f896 bl 8003258 <HAL_Delay>
|
|
ms += 10U;
|
|
800712c: 68fb ldr r3, [r7, #12]
|
|
800712e: 330a adds r3, #10
|
|
8007130: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8007132: 6878 ldr r0, [r7, #4]
|
|
8007134: f000 f9f6 bl 8007524 <USB_GetMode>
|
|
8007138: 4603 mov r3, r0
|
|
800713a: 2b00 cmp r3, #0
|
|
800713c: d005 beq.n 800714a <USB_SetCurrentMode+0x84>
|
|
800713e: 68fb ldr r3, [r7, #12]
|
|
8007140: 2bc7 cmp r3, #199 @ 0xc7
|
|
8007142: d9f0 bls.n 8007126 <USB_SetCurrentMode+0x60>
|
|
8007144: e001 b.n 800714a <USB_SetCurrentMode+0x84>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
8007146: 2301 movs r3, #1
|
|
8007148: e005 b.n 8007156 <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
|
|
800714a: 68fb ldr r3, [r7, #12]
|
|
800714c: 2bc8 cmp r3, #200 @ 0xc8
|
|
800714e: d101 bne.n 8007154 <USB_SetCurrentMode+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
8007150: 2301 movs r3, #1
|
|
8007152: e000 b.n 8007156 <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007154: 2300 movs r3, #0
|
|
}
|
|
8007156: 4618 mov r0, r3
|
|
8007158: 3710 adds r7, #16
|
|
800715a: 46bd mov sp, r7
|
|
800715c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08007160 <USB_DevInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8007160: b084 sub sp, #16
|
|
8007162: b580 push {r7, lr}
|
|
8007164: b086 sub sp, #24
|
|
8007166: af00 add r7, sp, #0
|
|
8007168: 6078 str r0, [r7, #4]
|
|
800716a: f107 0024 add.w r0, r7, #36 @ 0x24
|
|
800716e: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8007172: 2300 movs r3, #0
|
|
8007174: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007176: 687b ldr r3, [r7, #4]
|
|
8007178: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
|
|
for (i = 0U; i < 15U; i++)
|
|
800717a: 2300 movs r3, #0
|
|
800717c: 613b str r3, [r7, #16]
|
|
800717e: e009 b.n 8007194 <USB_DevInit+0x34>
|
|
{
|
|
USBx->DIEPTXF[i] = 0U;
|
|
8007180: 687a ldr r2, [r7, #4]
|
|
8007182: 693b ldr r3, [r7, #16]
|
|
8007184: 3340 adds r3, #64 @ 0x40
|
|
8007186: 009b lsls r3, r3, #2
|
|
8007188: 4413 add r3, r2
|
|
800718a: 2200 movs r2, #0
|
|
800718c: 605a str r2, [r3, #4]
|
|
for (i = 0U; i < 15U; i++)
|
|
800718e: 693b ldr r3, [r7, #16]
|
|
8007190: 3301 adds r3, #1
|
|
8007192: 613b str r3, [r7, #16]
|
|
8007194: 693b ldr r3, [r7, #16]
|
|
8007196: 2b0e cmp r3, #14
|
|
8007198: d9f2 bls.n 8007180 <USB_DevInit+0x20>
|
|
}
|
|
|
|
/* VBUS Sensing setup */
|
|
if (cfg.vbus_sensing_enable == 0U)
|
|
800719a: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
800719e: 2b00 cmp r3, #0
|
|
80071a0: d11c bne.n 80071dc <USB_DevInit+0x7c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
80071a2: 68fb ldr r3, [r7, #12]
|
|
80071a4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80071a8: 685b ldr r3, [r3, #4]
|
|
80071aa: 68fa ldr r2, [r7, #12]
|
|
80071ac: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80071b0: f043 0302 orr.w r3, r3, #2
|
|
80071b4: 6053 str r3, [r2, #4]
|
|
|
|
/* Deactivate VBUS Sensing B */
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
|
80071b6: 687b ldr r3, [r7, #4]
|
|
80071b8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80071ba: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
|
|
80071be: 687b ldr r3, [r7, #4]
|
|
80071c0: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* B-peripheral session valid override enable */
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
|
80071c2: 687b ldr r3, [r7, #4]
|
|
80071c4: 681b ldr r3, [r3, #0]
|
|
80071c6: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
80071ca: 687b ldr r3, [r7, #4]
|
|
80071cc: 601a str r2, [r3, #0]
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
|
80071ce: 687b ldr r3, [r7, #4]
|
|
80071d0: 681b ldr r3, [r3, #0]
|
|
80071d2: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
80071d6: 687b ldr r3, [r7, #4]
|
|
80071d8: 601a str r2, [r3, #0]
|
|
80071da: e005 b.n 80071e8 <USB_DevInit+0x88>
|
|
}
|
|
else
|
|
{
|
|
/* Enable HW VBUS sensing */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
|
80071dc: 687b ldr r3, [r7, #4]
|
|
80071de: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80071e0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
80071e4: 687b ldr r3, [r7, #4]
|
|
80071e6: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
/* Restart the Phy Clock */
|
|
USBx_PCGCCTL = 0U;
|
|
80071e8: 68fb ldr r3, [r7, #12]
|
|
80071ea: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80071ee: 461a mov r2, r3
|
|
80071f0: 2300 movs r3, #0
|
|
80071f2: 6013 str r3, [r2, #0]
|
|
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
|
|
80071f4: 2103 movs r1, #3
|
|
80071f6: 6878 ldr r0, [r7, #4]
|
|
80071f8: f000 f95a bl 80074b0 <USB_SetDevSpeed>
|
|
|
|
/* Flush the FIFOs */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
80071fc: 2110 movs r1, #16
|
|
80071fe: 6878 ldr r0, [r7, #4]
|
|
8007200: f000 f8f6 bl 80073f0 <USB_FlushTxFifo>
|
|
8007204: 4603 mov r3, r0
|
|
8007206: 2b00 cmp r3, #0
|
|
8007208: d001 beq.n 800720e <USB_DevInit+0xae>
|
|
{
|
|
ret = HAL_ERROR;
|
|
800720a: 2301 movs r3, #1
|
|
800720c: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
800720e: 6878 ldr r0, [r7, #4]
|
|
8007210: f000 f920 bl 8007454 <USB_FlushRxFifo>
|
|
8007214: 4603 mov r3, r0
|
|
8007216: 2b00 cmp r3, #0
|
|
8007218: d001 beq.n 800721e <USB_DevInit+0xbe>
|
|
{
|
|
ret = HAL_ERROR;
|
|
800721a: 2301 movs r3, #1
|
|
800721c: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Clear all pending Device Interrupts */
|
|
USBx_DEVICE->DIEPMSK = 0U;
|
|
800721e: 68fb ldr r3, [r7, #12]
|
|
8007220: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007224: 461a mov r2, r3
|
|
8007226: 2300 movs r3, #0
|
|
8007228: 6113 str r3, [r2, #16]
|
|
USBx_DEVICE->DOEPMSK = 0U;
|
|
800722a: 68fb ldr r3, [r7, #12]
|
|
800722c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007230: 461a mov r2, r3
|
|
8007232: 2300 movs r3, #0
|
|
8007234: 6153 str r3, [r2, #20]
|
|
USBx_DEVICE->DAINTMSK = 0U;
|
|
8007236: 68fb ldr r3, [r7, #12]
|
|
8007238: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800723c: 461a mov r2, r3
|
|
800723e: 2300 movs r3, #0
|
|
8007240: 61d3 str r3, [r2, #28]
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8007242: 2300 movs r3, #0
|
|
8007244: 613b str r3, [r7, #16]
|
|
8007246: e043 b.n 80072d0 <USB_DevInit+0x170>
|
|
{
|
|
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8007248: 693b ldr r3, [r7, #16]
|
|
800724a: 015a lsls r2, r3, #5
|
|
800724c: 68fb ldr r3, [r7, #12]
|
|
800724e: 4413 add r3, r2
|
|
8007250: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007254: 681b ldr r3, [r3, #0]
|
|
8007256: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800725a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800725e: d118 bne.n 8007292 <USB_DevInit+0x132>
|
|
{
|
|
if (i == 0U)
|
|
8007260: 693b ldr r3, [r7, #16]
|
|
8007262: 2b00 cmp r3, #0
|
|
8007264: d10a bne.n 800727c <USB_DevInit+0x11c>
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
|
|
8007266: 693b ldr r3, [r7, #16]
|
|
8007268: 015a lsls r2, r3, #5
|
|
800726a: 68fb ldr r3, [r7, #12]
|
|
800726c: 4413 add r3, r2
|
|
800726e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007272: 461a mov r2, r3
|
|
8007274: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
8007278: 6013 str r3, [r2, #0]
|
|
800727a: e013 b.n 80072a4 <USB_DevInit+0x144>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
|
|
800727c: 693b ldr r3, [r7, #16]
|
|
800727e: 015a lsls r2, r3, #5
|
|
8007280: 68fb ldr r3, [r7, #12]
|
|
8007282: 4413 add r3, r2
|
|
8007284: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007288: 461a mov r2, r3
|
|
800728a: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
800728e: 6013 str r3, [r2, #0]
|
|
8007290: e008 b.n 80072a4 <USB_DevInit+0x144>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = 0U;
|
|
8007292: 693b ldr r3, [r7, #16]
|
|
8007294: 015a lsls r2, r3, #5
|
|
8007296: 68fb ldr r3, [r7, #12]
|
|
8007298: 4413 add r3, r2
|
|
800729a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800729e: 461a mov r2, r3
|
|
80072a0: 2300 movs r3, #0
|
|
80072a2: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_INEP(i)->DIEPTSIZ = 0U;
|
|
80072a4: 693b ldr r3, [r7, #16]
|
|
80072a6: 015a lsls r2, r3, #5
|
|
80072a8: 68fb ldr r3, [r7, #12]
|
|
80072aa: 4413 add r3, r2
|
|
80072ac: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80072b0: 461a mov r2, r3
|
|
80072b2: 2300 movs r3, #0
|
|
80072b4: 6113 str r3, [r2, #16]
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
80072b6: 693b ldr r3, [r7, #16]
|
|
80072b8: 015a lsls r2, r3, #5
|
|
80072ba: 68fb ldr r3, [r7, #12]
|
|
80072bc: 4413 add r3, r2
|
|
80072be: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80072c2: 461a mov r2, r3
|
|
80072c4: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
80072c8: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
80072ca: 693b ldr r3, [r7, #16]
|
|
80072cc: 3301 adds r3, #1
|
|
80072ce: 613b str r3, [r7, #16]
|
|
80072d0: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
80072d4: 461a mov r2, r3
|
|
80072d6: 693b ldr r3, [r7, #16]
|
|
80072d8: 4293 cmp r3, r2
|
|
80072da: d3b5 bcc.n 8007248 <USB_DevInit+0xe8>
|
|
}
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
80072dc: 2300 movs r3, #0
|
|
80072de: 613b str r3, [r7, #16]
|
|
80072e0: e043 b.n 800736a <USB_DevInit+0x20a>
|
|
{
|
|
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
80072e2: 693b ldr r3, [r7, #16]
|
|
80072e4: 015a lsls r2, r3, #5
|
|
80072e6: 68fb ldr r3, [r7, #12]
|
|
80072e8: 4413 add r3, r2
|
|
80072ea: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80072ee: 681b ldr r3, [r3, #0]
|
|
80072f0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80072f4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80072f8: d118 bne.n 800732c <USB_DevInit+0x1cc>
|
|
{
|
|
if (i == 0U)
|
|
80072fa: 693b ldr r3, [r7, #16]
|
|
80072fc: 2b00 cmp r3, #0
|
|
80072fe: d10a bne.n 8007316 <USB_DevInit+0x1b6>
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
|
|
8007300: 693b ldr r3, [r7, #16]
|
|
8007302: 015a lsls r2, r3, #5
|
|
8007304: 68fb ldr r3, [r7, #12]
|
|
8007306: 4413 add r3, r2
|
|
8007308: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800730c: 461a mov r2, r3
|
|
800730e: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
8007312: 6013 str r3, [r2, #0]
|
|
8007314: e013 b.n 800733e <USB_DevInit+0x1de>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
|
|
8007316: 693b ldr r3, [r7, #16]
|
|
8007318: 015a lsls r2, r3, #5
|
|
800731a: 68fb ldr r3, [r7, #12]
|
|
800731c: 4413 add r3, r2
|
|
800731e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007322: 461a mov r2, r3
|
|
8007324: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8007328: 6013 str r3, [r2, #0]
|
|
800732a: e008 b.n 800733e <USB_DevInit+0x1de>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = 0U;
|
|
800732c: 693b ldr r3, [r7, #16]
|
|
800732e: 015a lsls r2, r3, #5
|
|
8007330: 68fb ldr r3, [r7, #12]
|
|
8007332: 4413 add r3, r2
|
|
8007334: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007338: 461a mov r2, r3
|
|
800733a: 2300 movs r3, #0
|
|
800733c: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_OUTEP(i)->DOEPTSIZ = 0U;
|
|
800733e: 693b ldr r3, [r7, #16]
|
|
8007340: 015a lsls r2, r3, #5
|
|
8007342: 68fb ldr r3, [r7, #12]
|
|
8007344: 4413 add r3, r2
|
|
8007346: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800734a: 461a mov r2, r3
|
|
800734c: 2300 movs r3, #0
|
|
800734e: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8007350: 693b ldr r3, [r7, #16]
|
|
8007352: 015a lsls r2, r3, #5
|
|
8007354: 68fb ldr r3, [r7, #12]
|
|
8007356: 4413 add r3, r2
|
|
8007358: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800735c: 461a mov r2, r3
|
|
800735e: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8007362: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8007364: 693b ldr r3, [r7, #16]
|
|
8007366: 3301 adds r3, #1
|
|
8007368: 613b str r3, [r7, #16]
|
|
800736a: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
800736e: 461a mov r2, r3
|
|
8007370: 693b ldr r3, [r7, #16]
|
|
8007372: 4293 cmp r3, r2
|
|
8007374: d3b5 bcc.n 80072e2 <USB_DevInit+0x182>
|
|
}
|
|
|
|
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
|
|
8007376: 68fb ldr r3, [r7, #12]
|
|
8007378: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800737c: 691b ldr r3, [r3, #16]
|
|
800737e: 68fa ldr r2, [r7, #12]
|
|
8007380: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8007384: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8007388: 6113 str r3, [r2, #16]
|
|
|
|
/* Disable all interrupts. */
|
|
USBx->GINTMSK = 0U;
|
|
800738a: 687b ldr r3, [r7, #4]
|
|
800738c: 2200 movs r2, #0
|
|
800738e: 619a str r2, [r3, #24]
|
|
|
|
/* Clear any pending interrupts */
|
|
USBx->GINTSTS = 0xBFFFFFFFU;
|
|
8007390: 687b ldr r3, [r7, #4]
|
|
8007392: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
|
|
8007396: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the common interrupts */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
|
8007398: 687b ldr r3, [r7, #4]
|
|
800739a: 699b ldr r3, [r3, #24]
|
|
800739c: f043 0210 orr.w r2, r3, #16
|
|
80073a0: 687b ldr r3, [r7, #4]
|
|
80073a2: 619a str r2, [r3, #24]
|
|
|
|
/* Enable interrupts matching to the Device mode ONLY */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
|
|
80073a4: 687b ldr r3, [r7, #4]
|
|
80073a6: 699a ldr r2, [r3, #24]
|
|
80073a8: 4b10 ldr r3, [pc, #64] @ (80073ec <USB_DevInit+0x28c>)
|
|
80073aa: 4313 orrs r3, r2
|
|
80073ac: 687a ldr r2, [r7, #4]
|
|
80073ae: 6193 str r3, [r2, #24]
|
|
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
|
|
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
|
|
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
|
|
|
|
if (cfg.Sof_enable != 0U)
|
|
80073b0: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
80073b4: 2b00 cmp r3, #0
|
|
80073b6: d005 beq.n 80073c4 <USB_DevInit+0x264>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
|
|
80073b8: 687b ldr r3, [r7, #4]
|
|
80073ba: 699b ldr r3, [r3, #24]
|
|
80073bc: f043 0208 orr.w r2, r3, #8
|
|
80073c0: 687b ldr r3, [r7, #4]
|
|
80073c2: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (cfg.vbus_sensing_enable == 1U)
|
|
80073c4: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
80073c8: 2b01 cmp r3, #1
|
|
80073ca: d107 bne.n 80073dc <USB_DevInit+0x27c>
|
|
{
|
|
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
|
|
80073cc: 687b ldr r3, [r7, #4]
|
|
80073ce: 699b ldr r3, [r3, #24]
|
|
80073d0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80073d4: f043 0304 orr.w r3, r3, #4
|
|
80073d8: 687a ldr r2, [r7, #4]
|
|
80073da: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
return ret;
|
|
80073dc: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80073de: 4618 mov r0, r3
|
|
80073e0: 3718 adds r7, #24
|
|
80073e2: 46bd mov sp, r7
|
|
80073e4: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
80073e8: b004 add sp, #16
|
|
80073ea: 4770 bx lr
|
|
80073ec: 803c3800 .word 0x803c3800
|
|
|
|
080073f0 <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
80073f0: b480 push {r7}
|
|
80073f2: b085 sub sp, #20
|
|
80073f4: af00 add r7, sp, #0
|
|
80073f6: 6078 str r0, [r7, #4]
|
|
80073f8: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
80073fa: 2300 movs r3, #0
|
|
80073fc: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
80073fe: 68fb ldr r3, [r7, #12]
|
|
8007400: 3301 adds r3, #1
|
|
8007402: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8007404: 68fb ldr r3, [r7, #12]
|
|
8007406: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800740a: d901 bls.n 8007410 <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800740c: 2303 movs r3, #3
|
|
800740e: e01b b.n 8007448 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8007410: 687b ldr r3, [r7, #4]
|
|
8007412: 691b ldr r3, [r3, #16]
|
|
8007414: 2b00 cmp r3, #0
|
|
8007416: daf2 bge.n 80073fe <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
8007418: 2300 movs r3, #0
|
|
800741a: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
800741c: 683b ldr r3, [r7, #0]
|
|
800741e: 019b lsls r3, r3, #6
|
|
8007420: f043 0220 orr.w r2, r3, #32
|
|
8007424: 687b ldr r3, [r7, #4]
|
|
8007426: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007428: 68fb ldr r3, [r7, #12]
|
|
800742a: 3301 adds r3, #1
|
|
800742c: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800742e: 68fb ldr r3, [r7, #12]
|
|
8007430: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007434: d901 bls.n 800743a <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007436: 2303 movs r3, #3
|
|
8007438: e006 b.n 8007448 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
800743a: 687b ldr r3, [r7, #4]
|
|
800743c: 691b ldr r3, [r3, #16]
|
|
800743e: f003 0320 and.w r3, r3, #32
|
|
8007442: 2b20 cmp r3, #32
|
|
8007444: d0f0 beq.n 8007428 <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
8007446: 2300 movs r3, #0
|
|
}
|
|
8007448: 4618 mov r0, r3
|
|
800744a: 3714 adds r7, #20
|
|
800744c: 46bd mov sp, r7
|
|
800744e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007452: 4770 bx lr
|
|
|
|
08007454 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007454: b480 push {r7}
|
|
8007456: b085 sub sp, #20
|
|
8007458: af00 add r7, sp, #0
|
|
800745a: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
800745c: 2300 movs r3, #0
|
|
800745e: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8007460: 68fb ldr r3, [r7, #12]
|
|
8007462: 3301 adds r3, #1
|
|
8007464: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8007466: 68fb ldr r3, [r7, #12]
|
|
8007468: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800746c: d901 bls.n 8007472 <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800746e: 2303 movs r3, #3
|
|
8007470: e018 b.n 80074a4 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8007472: 687b ldr r3, [r7, #4]
|
|
8007474: 691b ldr r3, [r3, #16]
|
|
8007476: 2b00 cmp r3, #0
|
|
8007478: daf2 bge.n 8007460 <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
800747a: 2300 movs r3, #0
|
|
800747c: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
800747e: 687b ldr r3, [r7, #4]
|
|
8007480: 2210 movs r2, #16
|
|
8007482: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007484: 68fb ldr r3, [r7, #12]
|
|
8007486: 3301 adds r3, #1
|
|
8007488: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800748a: 68fb ldr r3, [r7, #12]
|
|
800748c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007490: d901 bls.n 8007496 <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007492: 2303 movs r3, #3
|
|
8007494: e006 b.n 80074a4 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
8007496: 687b ldr r3, [r7, #4]
|
|
8007498: 691b ldr r3, [r3, #16]
|
|
800749a: f003 0310 and.w r3, r3, #16
|
|
800749e: 2b10 cmp r3, #16
|
|
80074a0: d0f0 beq.n 8007484 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
80074a2: 2300 movs r3, #0
|
|
}
|
|
80074a4: 4618 mov r0, r3
|
|
80074a6: 3714 adds r7, #20
|
|
80074a8: 46bd mov sp, r7
|
|
80074aa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80074ae: 4770 bx lr
|
|
|
|
080074b0 <USB_SetDevSpeed>:
|
|
* This parameter can be one of these values:
|
|
* @arg USB_OTG_SPEED_FULL: Full speed mode
|
|
* @retval Hal status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
|
|
{
|
|
80074b0: b480 push {r7}
|
|
80074b2: b085 sub sp, #20
|
|
80074b4: af00 add r7, sp, #0
|
|
80074b6: 6078 str r0, [r7, #4]
|
|
80074b8: 460b mov r3, r1
|
|
80074ba: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80074bc: 687b ldr r3, [r7, #4]
|
|
80074be: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG |= speed;
|
|
80074c0: 68fb ldr r3, [r7, #12]
|
|
80074c2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80074c6: 681a ldr r2, [r3, #0]
|
|
80074c8: 78fb ldrb r3, [r7, #3]
|
|
80074ca: 68f9 ldr r1, [r7, #12]
|
|
80074cc: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80074d0: 4313 orrs r3, r2
|
|
80074d2: 600b str r3, [r1, #0]
|
|
return HAL_OK;
|
|
80074d4: 2300 movs r3, #0
|
|
}
|
|
80074d6: 4618 mov r0, r3
|
|
80074d8: 3714 adds r7, #20
|
|
80074da: 46bd mov sp, r7
|
|
80074dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80074e0: 4770 bx lr
|
|
|
|
080074e2 <USB_DevDisconnect>:
|
|
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80074e2: b480 push {r7}
|
|
80074e4: b085 sub sp, #20
|
|
80074e6: af00 add r7, sp, #0
|
|
80074e8: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80074ea: 687b ldr r3, [r7, #4]
|
|
80074ec: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
80074ee: 68fb ldr r3, [r7, #12]
|
|
80074f0: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80074f4: 681b ldr r3, [r3, #0]
|
|
80074f6: 68fa ldr r2, [r7, #12]
|
|
80074f8: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80074fc: f023 0303 bic.w r3, r3, #3
|
|
8007500: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
8007502: 68fb ldr r3, [r7, #12]
|
|
8007504: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007508: 685b ldr r3, [r3, #4]
|
|
800750a: 68fa ldr r2, [r7, #12]
|
|
800750c: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8007510: f043 0302 orr.w r3, r3, #2
|
|
8007514: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8007516: 2300 movs r3, #0
|
|
}
|
|
8007518: 4618 mov r0, r3
|
|
800751a: 3714 adds r7, #20
|
|
800751c: 46bd mov sp, r7
|
|
800751e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007522: 4770 bx lr
|
|
|
|
08007524 <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 0 : Host
|
|
* 1 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007524: b480 push {r7}
|
|
8007526: b083 sub sp, #12
|
|
8007528: af00 add r7, sp, #0
|
|
800752a: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
800752c: 687b ldr r3, [r7, #4]
|
|
800752e: 695b ldr r3, [r3, #20]
|
|
8007530: f003 0301 and.w r3, r3, #1
|
|
}
|
|
8007534: 4618 mov r0, r3
|
|
8007536: 370c adds r7, #12
|
|
8007538: 46bd mov sp, r7
|
|
800753a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800753e: 4770 bx lr
|
|
|
|
08007540 <USB_CoreReset>:
|
|
* @brief Reset the USB Core (needed after USB clock settings change)
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007540: b480 push {r7}
|
|
8007542: b085 sub sp, #20
|
|
8007544: af00 add r7, sp, #0
|
|
8007546: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
8007548: 2300 movs r3, #0
|
|
800754a: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800754c: 68fb ldr r3, [r7, #12]
|
|
800754e: 3301 adds r3, #1
|
|
8007550: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8007552: 68fb ldr r3, [r7, #12]
|
|
8007554: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007558: d901 bls.n 800755e <USB_CoreReset+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800755a: 2303 movs r3, #3
|
|
800755c: e01b b.n 8007596 <USB_CoreReset+0x56>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
800755e: 687b ldr r3, [r7, #4]
|
|
8007560: 691b ldr r3, [r3, #16]
|
|
8007562: 2b00 cmp r3, #0
|
|
8007564: daf2 bge.n 800754c <USB_CoreReset+0xc>
|
|
|
|
/* Core Soft Reset */
|
|
count = 0U;
|
|
8007566: 2300 movs r3, #0
|
|
8007568: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
|
800756a: 687b ldr r3, [r7, #4]
|
|
800756c: 691b ldr r3, [r3, #16]
|
|
800756e: f043 0201 orr.w r2, r3, #1
|
|
8007572: 687b ldr r3, [r7, #4]
|
|
8007574: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007576: 68fb ldr r3, [r7, #12]
|
|
8007578: 3301 adds r3, #1
|
|
800757a: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800757c: 68fb ldr r3, [r7, #12]
|
|
800757e: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007582: d901 bls.n 8007588 <USB_CoreReset+0x48>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007584: 2303 movs r3, #3
|
|
8007586: e006 b.n 8007596 <USB_CoreReset+0x56>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
|
8007588: 687b ldr r3, [r7, #4]
|
|
800758a: 691b ldr r3, [r3, #16]
|
|
800758c: f003 0301 and.w r3, r3, #1
|
|
8007590: 2b01 cmp r3, #1
|
|
8007592: d0f0 beq.n 8007576 <USB_CoreReset+0x36>
|
|
|
|
return HAL_OK;
|
|
8007594: 2300 movs r3, #0
|
|
}
|
|
8007596: 4618 mov r0, r3
|
|
8007598: 3714 adds r7, #20
|
|
800759a: 46bd mov sp, r7
|
|
800759c: f85d 7b04 ldr.w r7, [sp], #4
|
|
80075a0: 4770 bx lr
|
|
|
|
080075a2 <__cvt>:
|
|
80075a2: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
80075a6: ec57 6b10 vmov r6, r7, d0
|
|
80075aa: 2f00 cmp r7, #0
|
|
80075ac: 460c mov r4, r1
|
|
80075ae: 4619 mov r1, r3
|
|
80075b0: 463b mov r3, r7
|
|
80075b2: bfbb ittet lt
|
|
80075b4: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000
|
|
80075b8: 461f movlt r7, r3
|
|
80075ba: 2300 movge r3, #0
|
|
80075bc: 232d movlt r3, #45 @ 0x2d
|
|
80075be: 700b strb r3, [r1, #0]
|
|
80075c0: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
80075c2: f8dd a030 ldr.w sl, [sp, #48] @ 0x30
|
|
80075c6: 4691 mov r9, r2
|
|
80075c8: f023 0820 bic.w r8, r3, #32
|
|
80075cc: bfbc itt lt
|
|
80075ce: 4632 movlt r2, r6
|
|
80075d0: 4616 movlt r6, r2
|
|
80075d2: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
80075d6: d005 beq.n 80075e4 <__cvt+0x42>
|
|
80075d8: f1b8 0f45 cmp.w r8, #69 @ 0x45
|
|
80075dc: d100 bne.n 80075e0 <__cvt+0x3e>
|
|
80075de: 3401 adds r4, #1
|
|
80075e0: 2102 movs r1, #2
|
|
80075e2: e000 b.n 80075e6 <__cvt+0x44>
|
|
80075e4: 2103 movs r1, #3
|
|
80075e6: ab03 add r3, sp, #12
|
|
80075e8: 9301 str r3, [sp, #4]
|
|
80075ea: ab02 add r3, sp, #8
|
|
80075ec: 9300 str r3, [sp, #0]
|
|
80075ee: ec47 6b10 vmov d0, r6, r7
|
|
80075f2: 4653 mov r3, sl
|
|
80075f4: 4622 mov r2, r4
|
|
80075f6: f000 ff4b bl 8008490 <_dtoa_r>
|
|
80075fa: f1b8 0f47 cmp.w r8, #71 @ 0x47
|
|
80075fe: 4605 mov r5, r0
|
|
8007600: d119 bne.n 8007636 <__cvt+0x94>
|
|
8007602: f019 0f01 tst.w r9, #1
|
|
8007606: d00e beq.n 8007626 <__cvt+0x84>
|
|
8007608: eb00 0904 add.w r9, r0, r4
|
|
800760c: 2200 movs r2, #0
|
|
800760e: 2300 movs r3, #0
|
|
8007610: 4630 mov r0, r6
|
|
8007612: 4639 mov r1, r7
|
|
8007614: f7f9 fa58 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8007618: b108 cbz r0, 800761e <__cvt+0x7c>
|
|
800761a: f8cd 900c str.w r9, [sp, #12]
|
|
800761e: 2230 movs r2, #48 @ 0x30
|
|
8007620: 9b03 ldr r3, [sp, #12]
|
|
8007622: 454b cmp r3, r9
|
|
8007624: d31e bcc.n 8007664 <__cvt+0xc2>
|
|
8007626: 9b03 ldr r3, [sp, #12]
|
|
8007628: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
800762a: 1b5b subs r3, r3, r5
|
|
800762c: 4628 mov r0, r5
|
|
800762e: 6013 str r3, [r2, #0]
|
|
8007630: b004 add sp, #16
|
|
8007632: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8007636: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
800763a: eb00 0904 add.w r9, r0, r4
|
|
800763e: d1e5 bne.n 800760c <__cvt+0x6a>
|
|
8007640: 7803 ldrb r3, [r0, #0]
|
|
8007642: 2b30 cmp r3, #48 @ 0x30
|
|
8007644: d10a bne.n 800765c <__cvt+0xba>
|
|
8007646: 2200 movs r2, #0
|
|
8007648: 2300 movs r3, #0
|
|
800764a: 4630 mov r0, r6
|
|
800764c: 4639 mov r1, r7
|
|
800764e: f7f9 fa3b bl 8000ac8 <__aeabi_dcmpeq>
|
|
8007652: b918 cbnz r0, 800765c <__cvt+0xba>
|
|
8007654: f1c4 0401 rsb r4, r4, #1
|
|
8007658: f8ca 4000 str.w r4, [sl]
|
|
800765c: f8da 3000 ldr.w r3, [sl]
|
|
8007660: 4499 add r9, r3
|
|
8007662: e7d3 b.n 800760c <__cvt+0x6a>
|
|
8007664: 1c59 adds r1, r3, #1
|
|
8007666: 9103 str r1, [sp, #12]
|
|
8007668: 701a strb r2, [r3, #0]
|
|
800766a: e7d9 b.n 8007620 <__cvt+0x7e>
|
|
|
|
0800766c <__exponent>:
|
|
800766c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
800766e: 2900 cmp r1, #0
|
|
8007670: bfba itte lt
|
|
8007672: 4249 neglt r1, r1
|
|
8007674: 232d movlt r3, #45 @ 0x2d
|
|
8007676: 232b movge r3, #43 @ 0x2b
|
|
8007678: 2909 cmp r1, #9
|
|
800767a: 7002 strb r2, [r0, #0]
|
|
800767c: 7043 strb r3, [r0, #1]
|
|
800767e: dd29 ble.n 80076d4 <__exponent+0x68>
|
|
8007680: f10d 0307 add.w r3, sp, #7
|
|
8007684: 461d mov r5, r3
|
|
8007686: 270a movs r7, #10
|
|
8007688: 461a mov r2, r3
|
|
800768a: fbb1 f6f7 udiv r6, r1, r7
|
|
800768e: fb07 1416 mls r4, r7, r6, r1
|
|
8007692: 3430 adds r4, #48 @ 0x30
|
|
8007694: f802 4c01 strb.w r4, [r2, #-1]
|
|
8007698: 460c mov r4, r1
|
|
800769a: 2c63 cmp r4, #99 @ 0x63
|
|
800769c: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff
|
|
80076a0: 4631 mov r1, r6
|
|
80076a2: dcf1 bgt.n 8007688 <__exponent+0x1c>
|
|
80076a4: 3130 adds r1, #48 @ 0x30
|
|
80076a6: 1e94 subs r4, r2, #2
|
|
80076a8: f803 1c01 strb.w r1, [r3, #-1]
|
|
80076ac: 1c41 adds r1, r0, #1
|
|
80076ae: 4623 mov r3, r4
|
|
80076b0: 42ab cmp r3, r5
|
|
80076b2: d30a bcc.n 80076ca <__exponent+0x5e>
|
|
80076b4: f10d 0309 add.w r3, sp, #9
|
|
80076b8: 1a9b subs r3, r3, r2
|
|
80076ba: 42ac cmp r4, r5
|
|
80076bc: bf88 it hi
|
|
80076be: 2300 movhi r3, #0
|
|
80076c0: 3302 adds r3, #2
|
|
80076c2: 4403 add r3, r0
|
|
80076c4: 1a18 subs r0, r3, r0
|
|
80076c6: b003 add sp, #12
|
|
80076c8: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80076ca: f813 6b01 ldrb.w r6, [r3], #1
|
|
80076ce: f801 6f01 strb.w r6, [r1, #1]!
|
|
80076d2: e7ed b.n 80076b0 <__exponent+0x44>
|
|
80076d4: 2330 movs r3, #48 @ 0x30
|
|
80076d6: 3130 adds r1, #48 @ 0x30
|
|
80076d8: 7083 strb r3, [r0, #2]
|
|
80076da: 70c1 strb r1, [r0, #3]
|
|
80076dc: 1d03 adds r3, r0, #4
|
|
80076de: e7f1 b.n 80076c4 <__exponent+0x58>
|
|
|
|
080076e0 <_printf_float>:
|
|
80076e0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80076e4: b08d sub sp, #52 @ 0x34
|
|
80076e6: 460c mov r4, r1
|
|
80076e8: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
|
|
80076ec: 4616 mov r6, r2
|
|
80076ee: 461f mov r7, r3
|
|
80076f0: 4605 mov r5, r0
|
|
80076f2: f000 fdbd bl 8008270 <_localeconv_r>
|
|
80076f6: 6803 ldr r3, [r0, #0]
|
|
80076f8: 9304 str r3, [sp, #16]
|
|
80076fa: 4618 mov r0, r3
|
|
80076fc: f7f8 fdb8 bl 8000270 <strlen>
|
|
8007700: 2300 movs r3, #0
|
|
8007702: 930a str r3, [sp, #40] @ 0x28
|
|
8007704: f8d8 3000 ldr.w r3, [r8]
|
|
8007708: 9005 str r0, [sp, #20]
|
|
800770a: 3307 adds r3, #7
|
|
800770c: f023 0307 bic.w r3, r3, #7
|
|
8007710: f103 0208 add.w r2, r3, #8
|
|
8007714: f894 a018 ldrb.w sl, [r4, #24]
|
|
8007718: f8d4 b000 ldr.w fp, [r4]
|
|
800771c: f8c8 2000 str.w r2, [r8]
|
|
8007720: e9d3 8900 ldrd r8, r9, [r3]
|
|
8007724: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
|
|
8007728: 9307 str r3, [sp, #28]
|
|
800772a: f8cd 8018 str.w r8, [sp, #24]
|
|
800772e: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48
|
|
8007732: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
8007736: 4b9c ldr r3, [pc, #624] @ (80079a8 <_printf_float+0x2c8>)
|
|
8007738: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800773c: f7f9 f9f6 bl 8000b2c <__aeabi_dcmpun>
|
|
8007740: bb70 cbnz r0, 80077a0 <_printf_float+0xc0>
|
|
8007742: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
8007746: 4b98 ldr r3, [pc, #608] @ (80079a8 <_printf_float+0x2c8>)
|
|
8007748: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800774c: f7f9 f9d0 bl 8000af0 <__aeabi_dcmple>
|
|
8007750: bb30 cbnz r0, 80077a0 <_printf_float+0xc0>
|
|
8007752: 2200 movs r2, #0
|
|
8007754: 2300 movs r3, #0
|
|
8007756: 4640 mov r0, r8
|
|
8007758: 4649 mov r1, r9
|
|
800775a: f7f9 f9bf bl 8000adc <__aeabi_dcmplt>
|
|
800775e: b110 cbz r0, 8007766 <_printf_float+0x86>
|
|
8007760: 232d movs r3, #45 @ 0x2d
|
|
8007762: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8007766: 4a91 ldr r2, [pc, #580] @ (80079ac <_printf_float+0x2cc>)
|
|
8007768: 4b91 ldr r3, [pc, #580] @ (80079b0 <_printf_float+0x2d0>)
|
|
800776a: f1ba 0f47 cmp.w sl, #71 @ 0x47
|
|
800776e: bf8c ite hi
|
|
8007770: 4690 movhi r8, r2
|
|
8007772: 4698 movls r8, r3
|
|
8007774: 2303 movs r3, #3
|
|
8007776: 6123 str r3, [r4, #16]
|
|
8007778: f02b 0304 bic.w r3, fp, #4
|
|
800777c: 6023 str r3, [r4, #0]
|
|
800777e: f04f 0900 mov.w r9, #0
|
|
8007782: 9700 str r7, [sp, #0]
|
|
8007784: 4633 mov r3, r6
|
|
8007786: aa0b add r2, sp, #44 @ 0x2c
|
|
8007788: 4621 mov r1, r4
|
|
800778a: 4628 mov r0, r5
|
|
800778c: f000 f9d2 bl 8007b34 <_printf_common>
|
|
8007790: 3001 adds r0, #1
|
|
8007792: f040 808d bne.w 80078b0 <_printf_float+0x1d0>
|
|
8007796: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800779a: b00d add sp, #52 @ 0x34
|
|
800779c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80077a0: 4642 mov r2, r8
|
|
80077a2: 464b mov r3, r9
|
|
80077a4: 4640 mov r0, r8
|
|
80077a6: 4649 mov r1, r9
|
|
80077a8: f7f9 f9c0 bl 8000b2c <__aeabi_dcmpun>
|
|
80077ac: b140 cbz r0, 80077c0 <_printf_float+0xe0>
|
|
80077ae: 464b mov r3, r9
|
|
80077b0: 2b00 cmp r3, #0
|
|
80077b2: bfbc itt lt
|
|
80077b4: 232d movlt r3, #45 @ 0x2d
|
|
80077b6: f884 3043 strblt.w r3, [r4, #67] @ 0x43
|
|
80077ba: 4a7e ldr r2, [pc, #504] @ (80079b4 <_printf_float+0x2d4>)
|
|
80077bc: 4b7e ldr r3, [pc, #504] @ (80079b8 <_printf_float+0x2d8>)
|
|
80077be: e7d4 b.n 800776a <_printf_float+0x8a>
|
|
80077c0: 6863 ldr r3, [r4, #4]
|
|
80077c2: f00a 02df and.w r2, sl, #223 @ 0xdf
|
|
80077c6: 9206 str r2, [sp, #24]
|
|
80077c8: 1c5a adds r2, r3, #1
|
|
80077ca: d13b bne.n 8007844 <_printf_float+0x164>
|
|
80077cc: 2306 movs r3, #6
|
|
80077ce: 6063 str r3, [r4, #4]
|
|
80077d0: f44b 6280 orr.w r2, fp, #1024 @ 0x400
|
|
80077d4: 2300 movs r3, #0
|
|
80077d6: 6022 str r2, [r4, #0]
|
|
80077d8: 9303 str r3, [sp, #12]
|
|
80077da: ab0a add r3, sp, #40 @ 0x28
|
|
80077dc: e9cd a301 strd sl, r3, [sp, #4]
|
|
80077e0: ab09 add r3, sp, #36 @ 0x24
|
|
80077e2: 9300 str r3, [sp, #0]
|
|
80077e4: 6861 ldr r1, [r4, #4]
|
|
80077e6: ec49 8b10 vmov d0, r8, r9
|
|
80077ea: f10d 0323 add.w r3, sp, #35 @ 0x23
|
|
80077ee: 4628 mov r0, r5
|
|
80077f0: f7ff fed7 bl 80075a2 <__cvt>
|
|
80077f4: 9b06 ldr r3, [sp, #24]
|
|
80077f6: 9909 ldr r1, [sp, #36] @ 0x24
|
|
80077f8: 2b47 cmp r3, #71 @ 0x47
|
|
80077fa: 4680 mov r8, r0
|
|
80077fc: d129 bne.n 8007852 <_printf_float+0x172>
|
|
80077fe: 1cc8 adds r0, r1, #3
|
|
8007800: db02 blt.n 8007808 <_printf_float+0x128>
|
|
8007802: 6863 ldr r3, [r4, #4]
|
|
8007804: 4299 cmp r1, r3
|
|
8007806: dd41 ble.n 800788c <_printf_float+0x1ac>
|
|
8007808: f1aa 0a02 sub.w sl, sl, #2
|
|
800780c: fa5f fa8a uxtb.w sl, sl
|
|
8007810: 3901 subs r1, #1
|
|
8007812: 4652 mov r2, sl
|
|
8007814: f104 0050 add.w r0, r4, #80 @ 0x50
|
|
8007818: 9109 str r1, [sp, #36] @ 0x24
|
|
800781a: f7ff ff27 bl 800766c <__exponent>
|
|
800781e: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
8007820: 1813 adds r3, r2, r0
|
|
8007822: 2a01 cmp r2, #1
|
|
8007824: 4681 mov r9, r0
|
|
8007826: 6123 str r3, [r4, #16]
|
|
8007828: dc02 bgt.n 8007830 <_printf_float+0x150>
|
|
800782a: 6822 ldr r2, [r4, #0]
|
|
800782c: 07d2 lsls r2, r2, #31
|
|
800782e: d501 bpl.n 8007834 <_printf_float+0x154>
|
|
8007830: 3301 adds r3, #1
|
|
8007832: 6123 str r3, [r4, #16]
|
|
8007834: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
|
|
8007838: 2b00 cmp r3, #0
|
|
800783a: d0a2 beq.n 8007782 <_printf_float+0xa2>
|
|
800783c: 232d movs r3, #45 @ 0x2d
|
|
800783e: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8007842: e79e b.n 8007782 <_printf_float+0xa2>
|
|
8007844: 9a06 ldr r2, [sp, #24]
|
|
8007846: 2a47 cmp r2, #71 @ 0x47
|
|
8007848: d1c2 bne.n 80077d0 <_printf_float+0xf0>
|
|
800784a: 2b00 cmp r3, #0
|
|
800784c: d1c0 bne.n 80077d0 <_printf_float+0xf0>
|
|
800784e: 2301 movs r3, #1
|
|
8007850: e7bd b.n 80077ce <_printf_float+0xee>
|
|
8007852: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
8007856: d9db bls.n 8007810 <_printf_float+0x130>
|
|
8007858: f1ba 0f66 cmp.w sl, #102 @ 0x66
|
|
800785c: d118 bne.n 8007890 <_printf_float+0x1b0>
|
|
800785e: 2900 cmp r1, #0
|
|
8007860: 6863 ldr r3, [r4, #4]
|
|
8007862: dd0b ble.n 800787c <_printf_float+0x19c>
|
|
8007864: 6121 str r1, [r4, #16]
|
|
8007866: b913 cbnz r3, 800786e <_printf_float+0x18e>
|
|
8007868: 6822 ldr r2, [r4, #0]
|
|
800786a: 07d0 lsls r0, r2, #31
|
|
800786c: d502 bpl.n 8007874 <_printf_float+0x194>
|
|
800786e: 3301 adds r3, #1
|
|
8007870: 440b add r3, r1
|
|
8007872: 6123 str r3, [r4, #16]
|
|
8007874: 65a1 str r1, [r4, #88] @ 0x58
|
|
8007876: f04f 0900 mov.w r9, #0
|
|
800787a: e7db b.n 8007834 <_printf_float+0x154>
|
|
800787c: b913 cbnz r3, 8007884 <_printf_float+0x1a4>
|
|
800787e: 6822 ldr r2, [r4, #0]
|
|
8007880: 07d2 lsls r2, r2, #31
|
|
8007882: d501 bpl.n 8007888 <_printf_float+0x1a8>
|
|
8007884: 3302 adds r3, #2
|
|
8007886: e7f4 b.n 8007872 <_printf_float+0x192>
|
|
8007888: 2301 movs r3, #1
|
|
800788a: e7f2 b.n 8007872 <_printf_float+0x192>
|
|
800788c: f04f 0a67 mov.w sl, #103 @ 0x67
|
|
8007890: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
8007892: 4299 cmp r1, r3
|
|
8007894: db05 blt.n 80078a2 <_printf_float+0x1c2>
|
|
8007896: 6823 ldr r3, [r4, #0]
|
|
8007898: 6121 str r1, [r4, #16]
|
|
800789a: 07d8 lsls r0, r3, #31
|
|
800789c: d5ea bpl.n 8007874 <_printf_float+0x194>
|
|
800789e: 1c4b adds r3, r1, #1
|
|
80078a0: e7e7 b.n 8007872 <_printf_float+0x192>
|
|
80078a2: 2900 cmp r1, #0
|
|
80078a4: bfd4 ite le
|
|
80078a6: f1c1 0202 rsble r2, r1, #2
|
|
80078aa: 2201 movgt r2, #1
|
|
80078ac: 4413 add r3, r2
|
|
80078ae: e7e0 b.n 8007872 <_printf_float+0x192>
|
|
80078b0: 6823 ldr r3, [r4, #0]
|
|
80078b2: 055a lsls r2, r3, #21
|
|
80078b4: d407 bmi.n 80078c6 <_printf_float+0x1e6>
|
|
80078b6: 6923 ldr r3, [r4, #16]
|
|
80078b8: 4642 mov r2, r8
|
|
80078ba: 4631 mov r1, r6
|
|
80078bc: 4628 mov r0, r5
|
|
80078be: 47b8 blx r7
|
|
80078c0: 3001 adds r0, #1
|
|
80078c2: d12b bne.n 800791c <_printf_float+0x23c>
|
|
80078c4: e767 b.n 8007796 <_printf_float+0xb6>
|
|
80078c6: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
80078ca: f240 80dd bls.w 8007a88 <_printf_float+0x3a8>
|
|
80078ce: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
80078d2: 2200 movs r2, #0
|
|
80078d4: 2300 movs r3, #0
|
|
80078d6: f7f9 f8f7 bl 8000ac8 <__aeabi_dcmpeq>
|
|
80078da: 2800 cmp r0, #0
|
|
80078dc: d033 beq.n 8007946 <_printf_float+0x266>
|
|
80078de: 4a37 ldr r2, [pc, #220] @ (80079bc <_printf_float+0x2dc>)
|
|
80078e0: 2301 movs r3, #1
|
|
80078e2: 4631 mov r1, r6
|
|
80078e4: 4628 mov r0, r5
|
|
80078e6: 47b8 blx r7
|
|
80078e8: 3001 adds r0, #1
|
|
80078ea: f43f af54 beq.w 8007796 <_printf_float+0xb6>
|
|
80078ee: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
|
|
80078f2: 4543 cmp r3, r8
|
|
80078f4: db02 blt.n 80078fc <_printf_float+0x21c>
|
|
80078f6: 6823 ldr r3, [r4, #0]
|
|
80078f8: 07d8 lsls r0, r3, #31
|
|
80078fa: d50f bpl.n 800791c <_printf_float+0x23c>
|
|
80078fc: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8007900: 4631 mov r1, r6
|
|
8007902: 4628 mov r0, r5
|
|
8007904: 47b8 blx r7
|
|
8007906: 3001 adds r0, #1
|
|
8007908: f43f af45 beq.w 8007796 <_printf_float+0xb6>
|
|
800790c: f04f 0900 mov.w r9, #0
|
|
8007910: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
|
|
8007914: f104 0a1a add.w sl, r4, #26
|
|
8007918: 45c8 cmp r8, r9
|
|
800791a: dc09 bgt.n 8007930 <_printf_float+0x250>
|
|
800791c: 6823 ldr r3, [r4, #0]
|
|
800791e: 079b lsls r3, r3, #30
|
|
8007920: f100 8103 bmi.w 8007b2a <_printf_float+0x44a>
|
|
8007924: 68e0 ldr r0, [r4, #12]
|
|
8007926: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8007928: 4298 cmp r0, r3
|
|
800792a: bfb8 it lt
|
|
800792c: 4618 movlt r0, r3
|
|
800792e: e734 b.n 800779a <_printf_float+0xba>
|
|
8007930: 2301 movs r3, #1
|
|
8007932: 4652 mov r2, sl
|
|
8007934: 4631 mov r1, r6
|
|
8007936: 4628 mov r0, r5
|
|
8007938: 47b8 blx r7
|
|
800793a: 3001 adds r0, #1
|
|
800793c: f43f af2b beq.w 8007796 <_printf_float+0xb6>
|
|
8007940: f109 0901 add.w r9, r9, #1
|
|
8007944: e7e8 b.n 8007918 <_printf_float+0x238>
|
|
8007946: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007948: 2b00 cmp r3, #0
|
|
800794a: dc39 bgt.n 80079c0 <_printf_float+0x2e0>
|
|
800794c: 4a1b ldr r2, [pc, #108] @ (80079bc <_printf_float+0x2dc>)
|
|
800794e: 2301 movs r3, #1
|
|
8007950: 4631 mov r1, r6
|
|
8007952: 4628 mov r0, r5
|
|
8007954: 47b8 blx r7
|
|
8007956: 3001 adds r0, #1
|
|
8007958: f43f af1d beq.w 8007796 <_printf_float+0xb6>
|
|
800795c: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
|
|
8007960: ea59 0303 orrs.w r3, r9, r3
|
|
8007964: d102 bne.n 800796c <_printf_float+0x28c>
|
|
8007966: 6823 ldr r3, [r4, #0]
|
|
8007968: 07d9 lsls r1, r3, #31
|
|
800796a: d5d7 bpl.n 800791c <_printf_float+0x23c>
|
|
800796c: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8007970: 4631 mov r1, r6
|
|
8007972: 4628 mov r0, r5
|
|
8007974: 47b8 blx r7
|
|
8007976: 3001 adds r0, #1
|
|
8007978: f43f af0d beq.w 8007796 <_printf_float+0xb6>
|
|
800797c: f04f 0a00 mov.w sl, #0
|
|
8007980: f104 0b1a add.w fp, r4, #26
|
|
8007984: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007986: 425b negs r3, r3
|
|
8007988: 4553 cmp r3, sl
|
|
800798a: dc01 bgt.n 8007990 <_printf_float+0x2b0>
|
|
800798c: 464b mov r3, r9
|
|
800798e: e793 b.n 80078b8 <_printf_float+0x1d8>
|
|
8007990: 2301 movs r3, #1
|
|
8007992: 465a mov r2, fp
|
|
8007994: 4631 mov r1, r6
|
|
8007996: 4628 mov r0, r5
|
|
8007998: 47b8 blx r7
|
|
800799a: 3001 adds r0, #1
|
|
800799c: f43f aefb beq.w 8007796 <_printf_float+0xb6>
|
|
80079a0: f10a 0a01 add.w sl, sl, #1
|
|
80079a4: e7ee b.n 8007984 <_printf_float+0x2a4>
|
|
80079a6: bf00 nop
|
|
80079a8: 7fefffff .word 0x7fefffff
|
|
80079ac: 0800a124 .word 0x0800a124
|
|
80079b0: 0800a120 .word 0x0800a120
|
|
80079b4: 0800a12c .word 0x0800a12c
|
|
80079b8: 0800a128 .word 0x0800a128
|
|
80079bc: 0800a130 .word 0x0800a130
|
|
80079c0: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
80079c2: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
80079c6: 4553 cmp r3, sl
|
|
80079c8: bfa8 it ge
|
|
80079ca: 4653 movge r3, sl
|
|
80079cc: 2b00 cmp r3, #0
|
|
80079ce: 4699 mov r9, r3
|
|
80079d0: dc36 bgt.n 8007a40 <_printf_float+0x360>
|
|
80079d2: f04f 0b00 mov.w fp, #0
|
|
80079d6: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
80079da: f104 021a add.w r2, r4, #26
|
|
80079de: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
80079e0: 9306 str r3, [sp, #24]
|
|
80079e2: eba3 0309 sub.w r3, r3, r9
|
|
80079e6: 455b cmp r3, fp
|
|
80079e8: dc31 bgt.n 8007a4e <_printf_float+0x36e>
|
|
80079ea: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80079ec: 459a cmp sl, r3
|
|
80079ee: dc3a bgt.n 8007a66 <_printf_float+0x386>
|
|
80079f0: 6823 ldr r3, [r4, #0]
|
|
80079f2: 07da lsls r2, r3, #31
|
|
80079f4: d437 bmi.n 8007a66 <_printf_float+0x386>
|
|
80079f6: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80079f8: ebaa 0903 sub.w r9, sl, r3
|
|
80079fc: 9b06 ldr r3, [sp, #24]
|
|
80079fe: ebaa 0303 sub.w r3, sl, r3
|
|
8007a02: 4599 cmp r9, r3
|
|
8007a04: bfa8 it ge
|
|
8007a06: 4699 movge r9, r3
|
|
8007a08: f1b9 0f00 cmp.w r9, #0
|
|
8007a0c: dc33 bgt.n 8007a76 <_printf_float+0x396>
|
|
8007a0e: f04f 0800 mov.w r8, #0
|
|
8007a12: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
8007a16: f104 0b1a add.w fp, r4, #26
|
|
8007a1a: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007a1c: ebaa 0303 sub.w r3, sl, r3
|
|
8007a20: eba3 0309 sub.w r3, r3, r9
|
|
8007a24: 4543 cmp r3, r8
|
|
8007a26: f77f af79 ble.w 800791c <_printf_float+0x23c>
|
|
8007a2a: 2301 movs r3, #1
|
|
8007a2c: 465a mov r2, fp
|
|
8007a2e: 4631 mov r1, r6
|
|
8007a30: 4628 mov r0, r5
|
|
8007a32: 47b8 blx r7
|
|
8007a34: 3001 adds r0, #1
|
|
8007a36: f43f aeae beq.w 8007796 <_printf_float+0xb6>
|
|
8007a3a: f108 0801 add.w r8, r8, #1
|
|
8007a3e: e7ec b.n 8007a1a <_printf_float+0x33a>
|
|
8007a40: 4642 mov r2, r8
|
|
8007a42: 4631 mov r1, r6
|
|
8007a44: 4628 mov r0, r5
|
|
8007a46: 47b8 blx r7
|
|
8007a48: 3001 adds r0, #1
|
|
8007a4a: d1c2 bne.n 80079d2 <_printf_float+0x2f2>
|
|
8007a4c: e6a3 b.n 8007796 <_printf_float+0xb6>
|
|
8007a4e: 2301 movs r3, #1
|
|
8007a50: 4631 mov r1, r6
|
|
8007a52: 4628 mov r0, r5
|
|
8007a54: 9206 str r2, [sp, #24]
|
|
8007a56: 47b8 blx r7
|
|
8007a58: 3001 adds r0, #1
|
|
8007a5a: f43f ae9c beq.w 8007796 <_printf_float+0xb6>
|
|
8007a5e: 9a06 ldr r2, [sp, #24]
|
|
8007a60: f10b 0b01 add.w fp, fp, #1
|
|
8007a64: e7bb b.n 80079de <_printf_float+0x2fe>
|
|
8007a66: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8007a6a: 4631 mov r1, r6
|
|
8007a6c: 4628 mov r0, r5
|
|
8007a6e: 47b8 blx r7
|
|
8007a70: 3001 adds r0, #1
|
|
8007a72: d1c0 bne.n 80079f6 <_printf_float+0x316>
|
|
8007a74: e68f b.n 8007796 <_printf_float+0xb6>
|
|
8007a76: 9a06 ldr r2, [sp, #24]
|
|
8007a78: 464b mov r3, r9
|
|
8007a7a: 4442 add r2, r8
|
|
8007a7c: 4631 mov r1, r6
|
|
8007a7e: 4628 mov r0, r5
|
|
8007a80: 47b8 blx r7
|
|
8007a82: 3001 adds r0, #1
|
|
8007a84: d1c3 bne.n 8007a0e <_printf_float+0x32e>
|
|
8007a86: e686 b.n 8007796 <_printf_float+0xb6>
|
|
8007a88: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
8007a8c: f1ba 0f01 cmp.w sl, #1
|
|
8007a90: dc01 bgt.n 8007a96 <_printf_float+0x3b6>
|
|
8007a92: 07db lsls r3, r3, #31
|
|
8007a94: d536 bpl.n 8007b04 <_printf_float+0x424>
|
|
8007a96: 2301 movs r3, #1
|
|
8007a98: 4642 mov r2, r8
|
|
8007a9a: 4631 mov r1, r6
|
|
8007a9c: 4628 mov r0, r5
|
|
8007a9e: 47b8 blx r7
|
|
8007aa0: 3001 adds r0, #1
|
|
8007aa2: f43f ae78 beq.w 8007796 <_printf_float+0xb6>
|
|
8007aa6: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8007aaa: 4631 mov r1, r6
|
|
8007aac: 4628 mov r0, r5
|
|
8007aae: 47b8 blx r7
|
|
8007ab0: 3001 adds r0, #1
|
|
8007ab2: f43f ae70 beq.w 8007796 <_printf_float+0xb6>
|
|
8007ab6: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
8007aba: 2200 movs r2, #0
|
|
8007abc: 2300 movs r3, #0
|
|
8007abe: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
8007ac2: f7f9 f801 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8007ac6: b9c0 cbnz r0, 8007afa <_printf_float+0x41a>
|
|
8007ac8: 4653 mov r3, sl
|
|
8007aca: f108 0201 add.w r2, r8, #1
|
|
8007ace: 4631 mov r1, r6
|
|
8007ad0: 4628 mov r0, r5
|
|
8007ad2: 47b8 blx r7
|
|
8007ad4: 3001 adds r0, #1
|
|
8007ad6: d10c bne.n 8007af2 <_printf_float+0x412>
|
|
8007ad8: e65d b.n 8007796 <_printf_float+0xb6>
|
|
8007ada: 2301 movs r3, #1
|
|
8007adc: 465a mov r2, fp
|
|
8007ade: 4631 mov r1, r6
|
|
8007ae0: 4628 mov r0, r5
|
|
8007ae2: 47b8 blx r7
|
|
8007ae4: 3001 adds r0, #1
|
|
8007ae6: f43f ae56 beq.w 8007796 <_printf_float+0xb6>
|
|
8007aea: f108 0801 add.w r8, r8, #1
|
|
8007aee: 45d0 cmp r8, sl
|
|
8007af0: dbf3 blt.n 8007ada <_printf_float+0x3fa>
|
|
8007af2: 464b mov r3, r9
|
|
8007af4: f104 0250 add.w r2, r4, #80 @ 0x50
|
|
8007af8: e6df b.n 80078ba <_printf_float+0x1da>
|
|
8007afa: f04f 0800 mov.w r8, #0
|
|
8007afe: f104 0b1a add.w fp, r4, #26
|
|
8007b02: e7f4 b.n 8007aee <_printf_float+0x40e>
|
|
8007b04: 2301 movs r3, #1
|
|
8007b06: 4642 mov r2, r8
|
|
8007b08: e7e1 b.n 8007ace <_printf_float+0x3ee>
|
|
8007b0a: 2301 movs r3, #1
|
|
8007b0c: 464a mov r2, r9
|
|
8007b0e: 4631 mov r1, r6
|
|
8007b10: 4628 mov r0, r5
|
|
8007b12: 47b8 blx r7
|
|
8007b14: 3001 adds r0, #1
|
|
8007b16: f43f ae3e beq.w 8007796 <_printf_float+0xb6>
|
|
8007b1a: f108 0801 add.w r8, r8, #1
|
|
8007b1e: 68e3 ldr r3, [r4, #12]
|
|
8007b20: 990b ldr r1, [sp, #44] @ 0x2c
|
|
8007b22: 1a5b subs r3, r3, r1
|
|
8007b24: 4543 cmp r3, r8
|
|
8007b26: dcf0 bgt.n 8007b0a <_printf_float+0x42a>
|
|
8007b28: e6fc b.n 8007924 <_printf_float+0x244>
|
|
8007b2a: f04f 0800 mov.w r8, #0
|
|
8007b2e: f104 0919 add.w r9, r4, #25
|
|
8007b32: e7f4 b.n 8007b1e <_printf_float+0x43e>
|
|
|
|
08007b34 <_printf_common>:
|
|
8007b34: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8007b38: 4616 mov r6, r2
|
|
8007b3a: 4698 mov r8, r3
|
|
8007b3c: 688a ldr r2, [r1, #8]
|
|
8007b3e: 690b ldr r3, [r1, #16]
|
|
8007b40: f8dd 9020 ldr.w r9, [sp, #32]
|
|
8007b44: 4293 cmp r3, r2
|
|
8007b46: bfb8 it lt
|
|
8007b48: 4613 movlt r3, r2
|
|
8007b4a: 6033 str r3, [r6, #0]
|
|
8007b4c: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
|
|
8007b50: 4607 mov r7, r0
|
|
8007b52: 460c mov r4, r1
|
|
8007b54: b10a cbz r2, 8007b5a <_printf_common+0x26>
|
|
8007b56: 3301 adds r3, #1
|
|
8007b58: 6033 str r3, [r6, #0]
|
|
8007b5a: 6823 ldr r3, [r4, #0]
|
|
8007b5c: 0699 lsls r1, r3, #26
|
|
8007b5e: bf42 ittt mi
|
|
8007b60: 6833 ldrmi r3, [r6, #0]
|
|
8007b62: 3302 addmi r3, #2
|
|
8007b64: 6033 strmi r3, [r6, #0]
|
|
8007b66: 6825 ldr r5, [r4, #0]
|
|
8007b68: f015 0506 ands.w r5, r5, #6
|
|
8007b6c: d106 bne.n 8007b7c <_printf_common+0x48>
|
|
8007b6e: f104 0a19 add.w sl, r4, #25
|
|
8007b72: 68e3 ldr r3, [r4, #12]
|
|
8007b74: 6832 ldr r2, [r6, #0]
|
|
8007b76: 1a9b subs r3, r3, r2
|
|
8007b78: 42ab cmp r3, r5
|
|
8007b7a: dc26 bgt.n 8007bca <_printf_common+0x96>
|
|
8007b7c: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
|
|
8007b80: 6822 ldr r2, [r4, #0]
|
|
8007b82: 3b00 subs r3, #0
|
|
8007b84: bf18 it ne
|
|
8007b86: 2301 movne r3, #1
|
|
8007b88: 0692 lsls r2, r2, #26
|
|
8007b8a: d42b bmi.n 8007be4 <_printf_common+0xb0>
|
|
8007b8c: f104 0243 add.w r2, r4, #67 @ 0x43
|
|
8007b90: 4641 mov r1, r8
|
|
8007b92: 4638 mov r0, r7
|
|
8007b94: 47c8 blx r9
|
|
8007b96: 3001 adds r0, #1
|
|
8007b98: d01e beq.n 8007bd8 <_printf_common+0xa4>
|
|
8007b9a: 6823 ldr r3, [r4, #0]
|
|
8007b9c: 6922 ldr r2, [r4, #16]
|
|
8007b9e: f003 0306 and.w r3, r3, #6
|
|
8007ba2: 2b04 cmp r3, #4
|
|
8007ba4: bf02 ittt eq
|
|
8007ba6: 68e5 ldreq r5, [r4, #12]
|
|
8007ba8: 6833 ldreq r3, [r6, #0]
|
|
8007baa: 1aed subeq r5, r5, r3
|
|
8007bac: 68a3 ldr r3, [r4, #8]
|
|
8007bae: bf0c ite eq
|
|
8007bb0: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
8007bb4: 2500 movne r5, #0
|
|
8007bb6: 4293 cmp r3, r2
|
|
8007bb8: bfc4 itt gt
|
|
8007bba: 1a9b subgt r3, r3, r2
|
|
8007bbc: 18ed addgt r5, r5, r3
|
|
8007bbe: 2600 movs r6, #0
|
|
8007bc0: 341a adds r4, #26
|
|
8007bc2: 42b5 cmp r5, r6
|
|
8007bc4: d11a bne.n 8007bfc <_printf_common+0xc8>
|
|
8007bc6: 2000 movs r0, #0
|
|
8007bc8: e008 b.n 8007bdc <_printf_common+0xa8>
|
|
8007bca: 2301 movs r3, #1
|
|
8007bcc: 4652 mov r2, sl
|
|
8007bce: 4641 mov r1, r8
|
|
8007bd0: 4638 mov r0, r7
|
|
8007bd2: 47c8 blx r9
|
|
8007bd4: 3001 adds r0, #1
|
|
8007bd6: d103 bne.n 8007be0 <_printf_common+0xac>
|
|
8007bd8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8007bdc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8007be0: 3501 adds r5, #1
|
|
8007be2: e7c6 b.n 8007b72 <_printf_common+0x3e>
|
|
8007be4: 18e1 adds r1, r4, r3
|
|
8007be6: 1c5a adds r2, r3, #1
|
|
8007be8: 2030 movs r0, #48 @ 0x30
|
|
8007bea: f881 0043 strb.w r0, [r1, #67] @ 0x43
|
|
8007bee: 4422 add r2, r4
|
|
8007bf0: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
|
|
8007bf4: f882 1043 strb.w r1, [r2, #67] @ 0x43
|
|
8007bf8: 3302 adds r3, #2
|
|
8007bfa: e7c7 b.n 8007b8c <_printf_common+0x58>
|
|
8007bfc: 2301 movs r3, #1
|
|
8007bfe: 4622 mov r2, r4
|
|
8007c00: 4641 mov r1, r8
|
|
8007c02: 4638 mov r0, r7
|
|
8007c04: 47c8 blx r9
|
|
8007c06: 3001 adds r0, #1
|
|
8007c08: d0e6 beq.n 8007bd8 <_printf_common+0xa4>
|
|
8007c0a: 3601 adds r6, #1
|
|
8007c0c: e7d9 b.n 8007bc2 <_printf_common+0x8e>
|
|
...
|
|
|
|
08007c10 <_printf_i>:
|
|
8007c10: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8007c14: 7e0f ldrb r7, [r1, #24]
|
|
8007c16: 9e0c ldr r6, [sp, #48] @ 0x30
|
|
8007c18: 2f78 cmp r7, #120 @ 0x78
|
|
8007c1a: 4691 mov r9, r2
|
|
8007c1c: 4680 mov r8, r0
|
|
8007c1e: 460c mov r4, r1
|
|
8007c20: 469a mov sl, r3
|
|
8007c22: f101 0243 add.w r2, r1, #67 @ 0x43
|
|
8007c26: d807 bhi.n 8007c38 <_printf_i+0x28>
|
|
8007c28: 2f62 cmp r7, #98 @ 0x62
|
|
8007c2a: d80a bhi.n 8007c42 <_printf_i+0x32>
|
|
8007c2c: 2f00 cmp r7, #0
|
|
8007c2e: f000 80d1 beq.w 8007dd4 <_printf_i+0x1c4>
|
|
8007c32: 2f58 cmp r7, #88 @ 0x58
|
|
8007c34: f000 80b8 beq.w 8007da8 <_printf_i+0x198>
|
|
8007c38: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8007c3c: f884 7042 strb.w r7, [r4, #66] @ 0x42
|
|
8007c40: e03a b.n 8007cb8 <_printf_i+0xa8>
|
|
8007c42: f1a7 0363 sub.w r3, r7, #99 @ 0x63
|
|
8007c46: 2b15 cmp r3, #21
|
|
8007c48: d8f6 bhi.n 8007c38 <_printf_i+0x28>
|
|
8007c4a: a101 add r1, pc, #4 @ (adr r1, 8007c50 <_printf_i+0x40>)
|
|
8007c4c: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
8007c50: 08007ca9 .word 0x08007ca9
|
|
8007c54: 08007cbd .word 0x08007cbd
|
|
8007c58: 08007c39 .word 0x08007c39
|
|
8007c5c: 08007c39 .word 0x08007c39
|
|
8007c60: 08007c39 .word 0x08007c39
|
|
8007c64: 08007c39 .word 0x08007c39
|
|
8007c68: 08007cbd .word 0x08007cbd
|
|
8007c6c: 08007c39 .word 0x08007c39
|
|
8007c70: 08007c39 .word 0x08007c39
|
|
8007c74: 08007c39 .word 0x08007c39
|
|
8007c78: 08007c39 .word 0x08007c39
|
|
8007c7c: 08007dbb .word 0x08007dbb
|
|
8007c80: 08007ce7 .word 0x08007ce7
|
|
8007c84: 08007d75 .word 0x08007d75
|
|
8007c88: 08007c39 .word 0x08007c39
|
|
8007c8c: 08007c39 .word 0x08007c39
|
|
8007c90: 08007ddd .word 0x08007ddd
|
|
8007c94: 08007c39 .word 0x08007c39
|
|
8007c98: 08007ce7 .word 0x08007ce7
|
|
8007c9c: 08007c39 .word 0x08007c39
|
|
8007ca0: 08007c39 .word 0x08007c39
|
|
8007ca4: 08007d7d .word 0x08007d7d
|
|
8007ca8: 6833 ldr r3, [r6, #0]
|
|
8007caa: 1d1a adds r2, r3, #4
|
|
8007cac: 681b ldr r3, [r3, #0]
|
|
8007cae: 6032 str r2, [r6, #0]
|
|
8007cb0: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8007cb4: f884 3042 strb.w r3, [r4, #66] @ 0x42
|
|
8007cb8: 2301 movs r3, #1
|
|
8007cba: e09c b.n 8007df6 <_printf_i+0x1e6>
|
|
8007cbc: 6833 ldr r3, [r6, #0]
|
|
8007cbe: 6820 ldr r0, [r4, #0]
|
|
8007cc0: 1d19 adds r1, r3, #4
|
|
8007cc2: 6031 str r1, [r6, #0]
|
|
8007cc4: 0606 lsls r6, r0, #24
|
|
8007cc6: d501 bpl.n 8007ccc <_printf_i+0xbc>
|
|
8007cc8: 681d ldr r5, [r3, #0]
|
|
8007cca: e003 b.n 8007cd4 <_printf_i+0xc4>
|
|
8007ccc: 0645 lsls r5, r0, #25
|
|
8007cce: d5fb bpl.n 8007cc8 <_printf_i+0xb8>
|
|
8007cd0: f9b3 5000 ldrsh.w r5, [r3]
|
|
8007cd4: 2d00 cmp r5, #0
|
|
8007cd6: da03 bge.n 8007ce0 <_printf_i+0xd0>
|
|
8007cd8: 232d movs r3, #45 @ 0x2d
|
|
8007cda: 426d negs r5, r5
|
|
8007cdc: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8007ce0: 4858 ldr r0, [pc, #352] @ (8007e44 <_printf_i+0x234>)
|
|
8007ce2: 230a movs r3, #10
|
|
8007ce4: e011 b.n 8007d0a <_printf_i+0xfa>
|
|
8007ce6: 6821 ldr r1, [r4, #0]
|
|
8007ce8: 6833 ldr r3, [r6, #0]
|
|
8007cea: 0608 lsls r0, r1, #24
|
|
8007cec: f853 5b04 ldr.w r5, [r3], #4
|
|
8007cf0: d402 bmi.n 8007cf8 <_printf_i+0xe8>
|
|
8007cf2: 0649 lsls r1, r1, #25
|
|
8007cf4: bf48 it mi
|
|
8007cf6: b2ad uxthmi r5, r5
|
|
8007cf8: 2f6f cmp r7, #111 @ 0x6f
|
|
8007cfa: 4852 ldr r0, [pc, #328] @ (8007e44 <_printf_i+0x234>)
|
|
8007cfc: 6033 str r3, [r6, #0]
|
|
8007cfe: bf14 ite ne
|
|
8007d00: 230a movne r3, #10
|
|
8007d02: 2308 moveq r3, #8
|
|
8007d04: 2100 movs r1, #0
|
|
8007d06: f884 1043 strb.w r1, [r4, #67] @ 0x43
|
|
8007d0a: 6866 ldr r6, [r4, #4]
|
|
8007d0c: 60a6 str r6, [r4, #8]
|
|
8007d0e: 2e00 cmp r6, #0
|
|
8007d10: db05 blt.n 8007d1e <_printf_i+0x10e>
|
|
8007d12: 6821 ldr r1, [r4, #0]
|
|
8007d14: 432e orrs r6, r5
|
|
8007d16: f021 0104 bic.w r1, r1, #4
|
|
8007d1a: 6021 str r1, [r4, #0]
|
|
8007d1c: d04b beq.n 8007db6 <_printf_i+0x1a6>
|
|
8007d1e: 4616 mov r6, r2
|
|
8007d20: fbb5 f1f3 udiv r1, r5, r3
|
|
8007d24: fb03 5711 mls r7, r3, r1, r5
|
|
8007d28: 5dc7 ldrb r7, [r0, r7]
|
|
8007d2a: f806 7d01 strb.w r7, [r6, #-1]!
|
|
8007d2e: 462f mov r7, r5
|
|
8007d30: 42bb cmp r3, r7
|
|
8007d32: 460d mov r5, r1
|
|
8007d34: d9f4 bls.n 8007d20 <_printf_i+0x110>
|
|
8007d36: 2b08 cmp r3, #8
|
|
8007d38: d10b bne.n 8007d52 <_printf_i+0x142>
|
|
8007d3a: 6823 ldr r3, [r4, #0]
|
|
8007d3c: 07df lsls r7, r3, #31
|
|
8007d3e: d508 bpl.n 8007d52 <_printf_i+0x142>
|
|
8007d40: 6923 ldr r3, [r4, #16]
|
|
8007d42: 6861 ldr r1, [r4, #4]
|
|
8007d44: 4299 cmp r1, r3
|
|
8007d46: bfde ittt le
|
|
8007d48: 2330 movle r3, #48 @ 0x30
|
|
8007d4a: f806 3c01 strble.w r3, [r6, #-1]
|
|
8007d4e: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
|
|
8007d52: 1b92 subs r2, r2, r6
|
|
8007d54: 6122 str r2, [r4, #16]
|
|
8007d56: f8cd a000 str.w sl, [sp]
|
|
8007d5a: 464b mov r3, r9
|
|
8007d5c: aa03 add r2, sp, #12
|
|
8007d5e: 4621 mov r1, r4
|
|
8007d60: 4640 mov r0, r8
|
|
8007d62: f7ff fee7 bl 8007b34 <_printf_common>
|
|
8007d66: 3001 adds r0, #1
|
|
8007d68: d14a bne.n 8007e00 <_printf_i+0x1f0>
|
|
8007d6a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8007d6e: b004 add sp, #16
|
|
8007d70: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8007d74: 6823 ldr r3, [r4, #0]
|
|
8007d76: f043 0320 orr.w r3, r3, #32
|
|
8007d7a: 6023 str r3, [r4, #0]
|
|
8007d7c: 4832 ldr r0, [pc, #200] @ (8007e48 <_printf_i+0x238>)
|
|
8007d7e: 2778 movs r7, #120 @ 0x78
|
|
8007d80: f884 7045 strb.w r7, [r4, #69] @ 0x45
|
|
8007d84: 6823 ldr r3, [r4, #0]
|
|
8007d86: 6831 ldr r1, [r6, #0]
|
|
8007d88: 061f lsls r7, r3, #24
|
|
8007d8a: f851 5b04 ldr.w r5, [r1], #4
|
|
8007d8e: d402 bmi.n 8007d96 <_printf_i+0x186>
|
|
8007d90: 065f lsls r7, r3, #25
|
|
8007d92: bf48 it mi
|
|
8007d94: b2ad uxthmi r5, r5
|
|
8007d96: 6031 str r1, [r6, #0]
|
|
8007d98: 07d9 lsls r1, r3, #31
|
|
8007d9a: bf44 itt mi
|
|
8007d9c: f043 0320 orrmi.w r3, r3, #32
|
|
8007da0: 6023 strmi r3, [r4, #0]
|
|
8007da2: b11d cbz r5, 8007dac <_printf_i+0x19c>
|
|
8007da4: 2310 movs r3, #16
|
|
8007da6: e7ad b.n 8007d04 <_printf_i+0xf4>
|
|
8007da8: 4826 ldr r0, [pc, #152] @ (8007e44 <_printf_i+0x234>)
|
|
8007daa: e7e9 b.n 8007d80 <_printf_i+0x170>
|
|
8007dac: 6823 ldr r3, [r4, #0]
|
|
8007dae: f023 0320 bic.w r3, r3, #32
|
|
8007db2: 6023 str r3, [r4, #0]
|
|
8007db4: e7f6 b.n 8007da4 <_printf_i+0x194>
|
|
8007db6: 4616 mov r6, r2
|
|
8007db8: e7bd b.n 8007d36 <_printf_i+0x126>
|
|
8007dba: 6833 ldr r3, [r6, #0]
|
|
8007dbc: 6825 ldr r5, [r4, #0]
|
|
8007dbe: 6961 ldr r1, [r4, #20]
|
|
8007dc0: 1d18 adds r0, r3, #4
|
|
8007dc2: 6030 str r0, [r6, #0]
|
|
8007dc4: 062e lsls r6, r5, #24
|
|
8007dc6: 681b ldr r3, [r3, #0]
|
|
8007dc8: d501 bpl.n 8007dce <_printf_i+0x1be>
|
|
8007dca: 6019 str r1, [r3, #0]
|
|
8007dcc: e002 b.n 8007dd4 <_printf_i+0x1c4>
|
|
8007dce: 0668 lsls r0, r5, #25
|
|
8007dd0: d5fb bpl.n 8007dca <_printf_i+0x1ba>
|
|
8007dd2: 8019 strh r1, [r3, #0]
|
|
8007dd4: 2300 movs r3, #0
|
|
8007dd6: 6123 str r3, [r4, #16]
|
|
8007dd8: 4616 mov r6, r2
|
|
8007dda: e7bc b.n 8007d56 <_printf_i+0x146>
|
|
8007ddc: 6833 ldr r3, [r6, #0]
|
|
8007dde: 1d1a adds r2, r3, #4
|
|
8007de0: 6032 str r2, [r6, #0]
|
|
8007de2: 681e ldr r6, [r3, #0]
|
|
8007de4: 6862 ldr r2, [r4, #4]
|
|
8007de6: 2100 movs r1, #0
|
|
8007de8: 4630 mov r0, r6
|
|
8007dea: f7f8 f9f1 bl 80001d0 <memchr>
|
|
8007dee: b108 cbz r0, 8007df4 <_printf_i+0x1e4>
|
|
8007df0: 1b80 subs r0, r0, r6
|
|
8007df2: 6060 str r0, [r4, #4]
|
|
8007df4: 6863 ldr r3, [r4, #4]
|
|
8007df6: 6123 str r3, [r4, #16]
|
|
8007df8: 2300 movs r3, #0
|
|
8007dfa: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8007dfe: e7aa b.n 8007d56 <_printf_i+0x146>
|
|
8007e00: 6923 ldr r3, [r4, #16]
|
|
8007e02: 4632 mov r2, r6
|
|
8007e04: 4649 mov r1, r9
|
|
8007e06: 4640 mov r0, r8
|
|
8007e08: 47d0 blx sl
|
|
8007e0a: 3001 adds r0, #1
|
|
8007e0c: d0ad beq.n 8007d6a <_printf_i+0x15a>
|
|
8007e0e: 6823 ldr r3, [r4, #0]
|
|
8007e10: 079b lsls r3, r3, #30
|
|
8007e12: d413 bmi.n 8007e3c <_printf_i+0x22c>
|
|
8007e14: 68e0 ldr r0, [r4, #12]
|
|
8007e16: 9b03 ldr r3, [sp, #12]
|
|
8007e18: 4298 cmp r0, r3
|
|
8007e1a: bfb8 it lt
|
|
8007e1c: 4618 movlt r0, r3
|
|
8007e1e: e7a6 b.n 8007d6e <_printf_i+0x15e>
|
|
8007e20: 2301 movs r3, #1
|
|
8007e22: 4632 mov r2, r6
|
|
8007e24: 4649 mov r1, r9
|
|
8007e26: 4640 mov r0, r8
|
|
8007e28: 47d0 blx sl
|
|
8007e2a: 3001 adds r0, #1
|
|
8007e2c: d09d beq.n 8007d6a <_printf_i+0x15a>
|
|
8007e2e: 3501 adds r5, #1
|
|
8007e30: 68e3 ldr r3, [r4, #12]
|
|
8007e32: 9903 ldr r1, [sp, #12]
|
|
8007e34: 1a5b subs r3, r3, r1
|
|
8007e36: 42ab cmp r3, r5
|
|
8007e38: dcf2 bgt.n 8007e20 <_printf_i+0x210>
|
|
8007e3a: e7eb b.n 8007e14 <_printf_i+0x204>
|
|
8007e3c: 2500 movs r5, #0
|
|
8007e3e: f104 0619 add.w r6, r4, #25
|
|
8007e42: e7f5 b.n 8007e30 <_printf_i+0x220>
|
|
8007e44: 0800a132 .word 0x0800a132
|
|
8007e48: 0800a143 .word 0x0800a143
|
|
|
|
08007e4c <std>:
|
|
8007e4c: 2300 movs r3, #0
|
|
8007e4e: b510 push {r4, lr}
|
|
8007e50: 4604 mov r4, r0
|
|
8007e52: e9c0 3300 strd r3, r3, [r0]
|
|
8007e56: e9c0 3304 strd r3, r3, [r0, #16]
|
|
8007e5a: 6083 str r3, [r0, #8]
|
|
8007e5c: 8181 strh r1, [r0, #12]
|
|
8007e5e: 6643 str r3, [r0, #100] @ 0x64
|
|
8007e60: 81c2 strh r2, [r0, #14]
|
|
8007e62: 6183 str r3, [r0, #24]
|
|
8007e64: 4619 mov r1, r3
|
|
8007e66: 2208 movs r2, #8
|
|
8007e68: 305c adds r0, #92 @ 0x5c
|
|
8007e6a: f000 f9f9 bl 8008260 <memset>
|
|
8007e6e: 4b0d ldr r3, [pc, #52] @ (8007ea4 <std+0x58>)
|
|
8007e70: 6263 str r3, [r4, #36] @ 0x24
|
|
8007e72: 4b0d ldr r3, [pc, #52] @ (8007ea8 <std+0x5c>)
|
|
8007e74: 62a3 str r3, [r4, #40] @ 0x28
|
|
8007e76: 4b0d ldr r3, [pc, #52] @ (8007eac <std+0x60>)
|
|
8007e78: 62e3 str r3, [r4, #44] @ 0x2c
|
|
8007e7a: 4b0d ldr r3, [pc, #52] @ (8007eb0 <std+0x64>)
|
|
8007e7c: 6323 str r3, [r4, #48] @ 0x30
|
|
8007e7e: 4b0d ldr r3, [pc, #52] @ (8007eb4 <std+0x68>)
|
|
8007e80: 6224 str r4, [r4, #32]
|
|
8007e82: 429c cmp r4, r3
|
|
8007e84: d006 beq.n 8007e94 <std+0x48>
|
|
8007e86: f103 0268 add.w r2, r3, #104 @ 0x68
|
|
8007e8a: 4294 cmp r4, r2
|
|
8007e8c: d002 beq.n 8007e94 <std+0x48>
|
|
8007e8e: 33d0 adds r3, #208 @ 0xd0
|
|
8007e90: 429c cmp r4, r3
|
|
8007e92: d105 bne.n 8007ea0 <std+0x54>
|
|
8007e94: f104 0058 add.w r0, r4, #88 @ 0x58
|
|
8007e98: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8007e9c: f000 ba5c b.w 8008358 <__retarget_lock_init_recursive>
|
|
8007ea0: bd10 pop {r4, pc}
|
|
8007ea2: bf00 nop
|
|
8007ea4: 080080b1 .word 0x080080b1
|
|
8007ea8: 080080d3 .word 0x080080d3
|
|
8007eac: 0800810b .word 0x0800810b
|
|
8007eb0: 0800812f .word 0x0800812f
|
|
8007eb4: 20000a78 .word 0x20000a78
|
|
|
|
08007eb8 <stdio_exit_handler>:
|
|
8007eb8: 4a02 ldr r2, [pc, #8] @ (8007ec4 <stdio_exit_handler+0xc>)
|
|
8007eba: 4903 ldr r1, [pc, #12] @ (8007ec8 <stdio_exit_handler+0x10>)
|
|
8007ebc: 4803 ldr r0, [pc, #12] @ (8007ecc <stdio_exit_handler+0x14>)
|
|
8007ebe: f000 b869 b.w 8007f94 <_fwalk_sglue>
|
|
8007ec2: bf00 nop
|
|
8007ec4: 200000d0 .word 0x200000d0
|
|
8007ec8: 08009cb1 .word 0x08009cb1
|
|
8007ecc: 200000e0 .word 0x200000e0
|
|
|
|
08007ed0 <cleanup_stdio>:
|
|
8007ed0: 6841 ldr r1, [r0, #4]
|
|
8007ed2: 4b0c ldr r3, [pc, #48] @ (8007f04 <cleanup_stdio+0x34>)
|
|
8007ed4: 4299 cmp r1, r3
|
|
8007ed6: b510 push {r4, lr}
|
|
8007ed8: 4604 mov r4, r0
|
|
8007eda: d001 beq.n 8007ee0 <cleanup_stdio+0x10>
|
|
8007edc: f001 fee8 bl 8009cb0 <_fflush_r>
|
|
8007ee0: 68a1 ldr r1, [r4, #8]
|
|
8007ee2: 4b09 ldr r3, [pc, #36] @ (8007f08 <cleanup_stdio+0x38>)
|
|
8007ee4: 4299 cmp r1, r3
|
|
8007ee6: d002 beq.n 8007eee <cleanup_stdio+0x1e>
|
|
8007ee8: 4620 mov r0, r4
|
|
8007eea: f001 fee1 bl 8009cb0 <_fflush_r>
|
|
8007eee: 68e1 ldr r1, [r4, #12]
|
|
8007ef0: 4b06 ldr r3, [pc, #24] @ (8007f0c <cleanup_stdio+0x3c>)
|
|
8007ef2: 4299 cmp r1, r3
|
|
8007ef4: d004 beq.n 8007f00 <cleanup_stdio+0x30>
|
|
8007ef6: 4620 mov r0, r4
|
|
8007ef8: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8007efc: f001 bed8 b.w 8009cb0 <_fflush_r>
|
|
8007f00: bd10 pop {r4, pc}
|
|
8007f02: bf00 nop
|
|
8007f04: 20000a78 .word 0x20000a78
|
|
8007f08: 20000ae0 .word 0x20000ae0
|
|
8007f0c: 20000b48 .word 0x20000b48
|
|
|
|
08007f10 <global_stdio_init.part.0>:
|
|
8007f10: b510 push {r4, lr}
|
|
8007f12: 4b0b ldr r3, [pc, #44] @ (8007f40 <global_stdio_init.part.0+0x30>)
|
|
8007f14: 4c0b ldr r4, [pc, #44] @ (8007f44 <global_stdio_init.part.0+0x34>)
|
|
8007f16: 4a0c ldr r2, [pc, #48] @ (8007f48 <global_stdio_init.part.0+0x38>)
|
|
8007f18: 601a str r2, [r3, #0]
|
|
8007f1a: 4620 mov r0, r4
|
|
8007f1c: 2200 movs r2, #0
|
|
8007f1e: 2104 movs r1, #4
|
|
8007f20: f7ff ff94 bl 8007e4c <std>
|
|
8007f24: f104 0068 add.w r0, r4, #104 @ 0x68
|
|
8007f28: 2201 movs r2, #1
|
|
8007f2a: 2109 movs r1, #9
|
|
8007f2c: f7ff ff8e bl 8007e4c <std>
|
|
8007f30: f104 00d0 add.w r0, r4, #208 @ 0xd0
|
|
8007f34: 2202 movs r2, #2
|
|
8007f36: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8007f3a: 2112 movs r1, #18
|
|
8007f3c: f7ff bf86 b.w 8007e4c <std>
|
|
8007f40: 20000bb0 .word 0x20000bb0
|
|
8007f44: 20000a78 .word 0x20000a78
|
|
8007f48: 08007eb9 .word 0x08007eb9
|
|
|
|
08007f4c <__sfp_lock_acquire>:
|
|
8007f4c: 4801 ldr r0, [pc, #4] @ (8007f54 <__sfp_lock_acquire+0x8>)
|
|
8007f4e: f000 ba04 b.w 800835a <__retarget_lock_acquire_recursive>
|
|
8007f52: bf00 nop
|
|
8007f54: 20000bb9 .word 0x20000bb9
|
|
|
|
08007f58 <__sfp_lock_release>:
|
|
8007f58: 4801 ldr r0, [pc, #4] @ (8007f60 <__sfp_lock_release+0x8>)
|
|
8007f5a: f000 b9ff b.w 800835c <__retarget_lock_release_recursive>
|
|
8007f5e: bf00 nop
|
|
8007f60: 20000bb9 .word 0x20000bb9
|
|
|
|
08007f64 <__sinit>:
|
|
8007f64: b510 push {r4, lr}
|
|
8007f66: 4604 mov r4, r0
|
|
8007f68: f7ff fff0 bl 8007f4c <__sfp_lock_acquire>
|
|
8007f6c: 6a23 ldr r3, [r4, #32]
|
|
8007f6e: b11b cbz r3, 8007f78 <__sinit+0x14>
|
|
8007f70: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8007f74: f7ff bff0 b.w 8007f58 <__sfp_lock_release>
|
|
8007f78: 4b04 ldr r3, [pc, #16] @ (8007f8c <__sinit+0x28>)
|
|
8007f7a: 6223 str r3, [r4, #32]
|
|
8007f7c: 4b04 ldr r3, [pc, #16] @ (8007f90 <__sinit+0x2c>)
|
|
8007f7e: 681b ldr r3, [r3, #0]
|
|
8007f80: 2b00 cmp r3, #0
|
|
8007f82: d1f5 bne.n 8007f70 <__sinit+0xc>
|
|
8007f84: f7ff ffc4 bl 8007f10 <global_stdio_init.part.0>
|
|
8007f88: e7f2 b.n 8007f70 <__sinit+0xc>
|
|
8007f8a: bf00 nop
|
|
8007f8c: 08007ed1 .word 0x08007ed1
|
|
8007f90: 20000bb0 .word 0x20000bb0
|
|
|
|
08007f94 <_fwalk_sglue>:
|
|
8007f94: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
8007f98: 4607 mov r7, r0
|
|
8007f9a: 4688 mov r8, r1
|
|
8007f9c: 4614 mov r4, r2
|
|
8007f9e: 2600 movs r6, #0
|
|
8007fa0: e9d4 9501 ldrd r9, r5, [r4, #4]
|
|
8007fa4: f1b9 0901 subs.w r9, r9, #1
|
|
8007fa8: d505 bpl.n 8007fb6 <_fwalk_sglue+0x22>
|
|
8007faa: 6824 ldr r4, [r4, #0]
|
|
8007fac: 2c00 cmp r4, #0
|
|
8007fae: d1f7 bne.n 8007fa0 <_fwalk_sglue+0xc>
|
|
8007fb0: 4630 mov r0, r6
|
|
8007fb2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
8007fb6: 89ab ldrh r3, [r5, #12]
|
|
8007fb8: 2b01 cmp r3, #1
|
|
8007fba: d907 bls.n 8007fcc <_fwalk_sglue+0x38>
|
|
8007fbc: f9b5 300e ldrsh.w r3, [r5, #14]
|
|
8007fc0: 3301 adds r3, #1
|
|
8007fc2: d003 beq.n 8007fcc <_fwalk_sglue+0x38>
|
|
8007fc4: 4629 mov r1, r5
|
|
8007fc6: 4638 mov r0, r7
|
|
8007fc8: 47c0 blx r8
|
|
8007fca: 4306 orrs r6, r0
|
|
8007fcc: 3568 adds r5, #104 @ 0x68
|
|
8007fce: e7e9 b.n 8007fa4 <_fwalk_sglue+0x10>
|
|
|
|
08007fd0 <iprintf>:
|
|
8007fd0: b40f push {r0, r1, r2, r3}
|
|
8007fd2: b507 push {r0, r1, r2, lr}
|
|
8007fd4: 4906 ldr r1, [pc, #24] @ (8007ff0 <iprintf+0x20>)
|
|
8007fd6: ab04 add r3, sp, #16
|
|
8007fd8: 6808 ldr r0, [r1, #0]
|
|
8007fda: f853 2b04 ldr.w r2, [r3], #4
|
|
8007fde: 6881 ldr r1, [r0, #8]
|
|
8007fe0: 9301 str r3, [sp, #4]
|
|
8007fe2: f001 fcc9 bl 8009978 <_vfiprintf_r>
|
|
8007fe6: b003 add sp, #12
|
|
8007fe8: f85d eb04 ldr.w lr, [sp], #4
|
|
8007fec: b004 add sp, #16
|
|
8007fee: 4770 bx lr
|
|
8007ff0: 200000dc .word 0x200000dc
|
|
|
|
08007ff4 <_puts_r>:
|
|
8007ff4: 6a03 ldr r3, [r0, #32]
|
|
8007ff6: b570 push {r4, r5, r6, lr}
|
|
8007ff8: 6884 ldr r4, [r0, #8]
|
|
8007ffa: 4605 mov r5, r0
|
|
8007ffc: 460e mov r6, r1
|
|
8007ffe: b90b cbnz r3, 8008004 <_puts_r+0x10>
|
|
8008000: f7ff ffb0 bl 8007f64 <__sinit>
|
|
8008004: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
8008006: 07db lsls r3, r3, #31
|
|
8008008: d405 bmi.n 8008016 <_puts_r+0x22>
|
|
800800a: 89a3 ldrh r3, [r4, #12]
|
|
800800c: 0598 lsls r0, r3, #22
|
|
800800e: d402 bmi.n 8008016 <_puts_r+0x22>
|
|
8008010: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8008012: f000 f9a2 bl 800835a <__retarget_lock_acquire_recursive>
|
|
8008016: 89a3 ldrh r3, [r4, #12]
|
|
8008018: 0719 lsls r1, r3, #28
|
|
800801a: d502 bpl.n 8008022 <_puts_r+0x2e>
|
|
800801c: 6923 ldr r3, [r4, #16]
|
|
800801e: 2b00 cmp r3, #0
|
|
8008020: d135 bne.n 800808e <_puts_r+0x9a>
|
|
8008022: 4621 mov r1, r4
|
|
8008024: 4628 mov r0, r5
|
|
8008026: f000 f8c5 bl 80081b4 <__swsetup_r>
|
|
800802a: b380 cbz r0, 800808e <_puts_r+0x9a>
|
|
800802c: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff
|
|
8008030: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
8008032: 07da lsls r2, r3, #31
|
|
8008034: d405 bmi.n 8008042 <_puts_r+0x4e>
|
|
8008036: 89a3 ldrh r3, [r4, #12]
|
|
8008038: 059b lsls r3, r3, #22
|
|
800803a: d402 bmi.n 8008042 <_puts_r+0x4e>
|
|
800803c: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
800803e: f000 f98d bl 800835c <__retarget_lock_release_recursive>
|
|
8008042: 4628 mov r0, r5
|
|
8008044: bd70 pop {r4, r5, r6, pc}
|
|
8008046: 2b00 cmp r3, #0
|
|
8008048: da04 bge.n 8008054 <_puts_r+0x60>
|
|
800804a: 69a2 ldr r2, [r4, #24]
|
|
800804c: 429a cmp r2, r3
|
|
800804e: dc17 bgt.n 8008080 <_puts_r+0x8c>
|
|
8008050: 290a cmp r1, #10
|
|
8008052: d015 beq.n 8008080 <_puts_r+0x8c>
|
|
8008054: 6823 ldr r3, [r4, #0]
|
|
8008056: 1c5a adds r2, r3, #1
|
|
8008058: 6022 str r2, [r4, #0]
|
|
800805a: 7019 strb r1, [r3, #0]
|
|
800805c: 68a3 ldr r3, [r4, #8]
|
|
800805e: f816 1f01 ldrb.w r1, [r6, #1]!
|
|
8008062: 3b01 subs r3, #1
|
|
8008064: 60a3 str r3, [r4, #8]
|
|
8008066: 2900 cmp r1, #0
|
|
8008068: d1ed bne.n 8008046 <_puts_r+0x52>
|
|
800806a: 2b00 cmp r3, #0
|
|
800806c: da11 bge.n 8008092 <_puts_r+0x9e>
|
|
800806e: 4622 mov r2, r4
|
|
8008070: 210a movs r1, #10
|
|
8008072: 4628 mov r0, r5
|
|
8008074: f000 f85f bl 8008136 <__swbuf_r>
|
|
8008078: 3001 adds r0, #1
|
|
800807a: d0d7 beq.n 800802c <_puts_r+0x38>
|
|
800807c: 250a movs r5, #10
|
|
800807e: e7d7 b.n 8008030 <_puts_r+0x3c>
|
|
8008080: 4622 mov r2, r4
|
|
8008082: 4628 mov r0, r5
|
|
8008084: f000 f857 bl 8008136 <__swbuf_r>
|
|
8008088: 3001 adds r0, #1
|
|
800808a: d1e7 bne.n 800805c <_puts_r+0x68>
|
|
800808c: e7ce b.n 800802c <_puts_r+0x38>
|
|
800808e: 3e01 subs r6, #1
|
|
8008090: e7e4 b.n 800805c <_puts_r+0x68>
|
|
8008092: 6823 ldr r3, [r4, #0]
|
|
8008094: 1c5a adds r2, r3, #1
|
|
8008096: 6022 str r2, [r4, #0]
|
|
8008098: 220a movs r2, #10
|
|
800809a: 701a strb r2, [r3, #0]
|
|
800809c: e7ee b.n 800807c <_puts_r+0x88>
|
|
...
|
|
|
|
080080a0 <puts>:
|
|
80080a0: 4b02 ldr r3, [pc, #8] @ (80080ac <puts+0xc>)
|
|
80080a2: 4601 mov r1, r0
|
|
80080a4: 6818 ldr r0, [r3, #0]
|
|
80080a6: f7ff bfa5 b.w 8007ff4 <_puts_r>
|
|
80080aa: bf00 nop
|
|
80080ac: 200000dc .word 0x200000dc
|
|
|
|
080080b0 <__sread>:
|
|
80080b0: b510 push {r4, lr}
|
|
80080b2: 460c mov r4, r1
|
|
80080b4: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
80080b8: f000 f900 bl 80082bc <_read_r>
|
|
80080bc: 2800 cmp r0, #0
|
|
80080be: bfab itete ge
|
|
80080c0: 6d63 ldrge r3, [r4, #84] @ 0x54
|
|
80080c2: 89a3 ldrhlt r3, [r4, #12]
|
|
80080c4: 181b addge r3, r3, r0
|
|
80080c6: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
|
|
80080ca: bfac ite ge
|
|
80080cc: 6563 strge r3, [r4, #84] @ 0x54
|
|
80080ce: 81a3 strhlt r3, [r4, #12]
|
|
80080d0: bd10 pop {r4, pc}
|
|
|
|
080080d2 <__swrite>:
|
|
80080d2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
80080d6: 461f mov r7, r3
|
|
80080d8: 898b ldrh r3, [r1, #12]
|
|
80080da: 05db lsls r3, r3, #23
|
|
80080dc: 4605 mov r5, r0
|
|
80080de: 460c mov r4, r1
|
|
80080e0: 4616 mov r6, r2
|
|
80080e2: d505 bpl.n 80080f0 <__swrite+0x1e>
|
|
80080e4: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
80080e8: 2302 movs r3, #2
|
|
80080ea: 2200 movs r2, #0
|
|
80080ec: f000 f8d4 bl 8008298 <_lseek_r>
|
|
80080f0: 89a3 ldrh r3, [r4, #12]
|
|
80080f2: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
80080f6: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
80080fa: 81a3 strh r3, [r4, #12]
|
|
80080fc: 4632 mov r2, r6
|
|
80080fe: 463b mov r3, r7
|
|
8008100: 4628 mov r0, r5
|
|
8008102: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
8008106: f000 b8eb b.w 80082e0 <_write_r>
|
|
|
|
0800810a <__sseek>:
|
|
800810a: b510 push {r4, lr}
|
|
800810c: 460c mov r4, r1
|
|
800810e: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
8008112: f000 f8c1 bl 8008298 <_lseek_r>
|
|
8008116: 1c43 adds r3, r0, #1
|
|
8008118: 89a3 ldrh r3, [r4, #12]
|
|
800811a: bf15 itete ne
|
|
800811c: 6560 strne r0, [r4, #84] @ 0x54
|
|
800811e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
|
|
8008122: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
|
|
8008126: 81a3 strheq r3, [r4, #12]
|
|
8008128: bf18 it ne
|
|
800812a: 81a3 strhne r3, [r4, #12]
|
|
800812c: bd10 pop {r4, pc}
|
|
|
|
0800812e <__sclose>:
|
|
800812e: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
8008132: f000 b8a1 b.w 8008278 <_close_r>
|
|
|
|
08008136 <__swbuf_r>:
|
|
8008136: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8008138: 460e mov r6, r1
|
|
800813a: 4614 mov r4, r2
|
|
800813c: 4605 mov r5, r0
|
|
800813e: b118 cbz r0, 8008148 <__swbuf_r+0x12>
|
|
8008140: 6a03 ldr r3, [r0, #32]
|
|
8008142: b90b cbnz r3, 8008148 <__swbuf_r+0x12>
|
|
8008144: f7ff ff0e bl 8007f64 <__sinit>
|
|
8008148: 69a3 ldr r3, [r4, #24]
|
|
800814a: 60a3 str r3, [r4, #8]
|
|
800814c: 89a3 ldrh r3, [r4, #12]
|
|
800814e: 071a lsls r2, r3, #28
|
|
8008150: d501 bpl.n 8008156 <__swbuf_r+0x20>
|
|
8008152: 6923 ldr r3, [r4, #16]
|
|
8008154: b943 cbnz r3, 8008168 <__swbuf_r+0x32>
|
|
8008156: 4621 mov r1, r4
|
|
8008158: 4628 mov r0, r5
|
|
800815a: f000 f82b bl 80081b4 <__swsetup_r>
|
|
800815e: b118 cbz r0, 8008168 <__swbuf_r+0x32>
|
|
8008160: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
|
|
8008164: 4638 mov r0, r7
|
|
8008166: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
8008168: 6823 ldr r3, [r4, #0]
|
|
800816a: 6922 ldr r2, [r4, #16]
|
|
800816c: 1a98 subs r0, r3, r2
|
|
800816e: 6963 ldr r3, [r4, #20]
|
|
8008170: b2f6 uxtb r6, r6
|
|
8008172: 4283 cmp r3, r0
|
|
8008174: 4637 mov r7, r6
|
|
8008176: dc05 bgt.n 8008184 <__swbuf_r+0x4e>
|
|
8008178: 4621 mov r1, r4
|
|
800817a: 4628 mov r0, r5
|
|
800817c: f001 fd98 bl 8009cb0 <_fflush_r>
|
|
8008180: 2800 cmp r0, #0
|
|
8008182: d1ed bne.n 8008160 <__swbuf_r+0x2a>
|
|
8008184: 68a3 ldr r3, [r4, #8]
|
|
8008186: 3b01 subs r3, #1
|
|
8008188: 60a3 str r3, [r4, #8]
|
|
800818a: 6823 ldr r3, [r4, #0]
|
|
800818c: 1c5a adds r2, r3, #1
|
|
800818e: 6022 str r2, [r4, #0]
|
|
8008190: 701e strb r6, [r3, #0]
|
|
8008192: 6962 ldr r2, [r4, #20]
|
|
8008194: 1c43 adds r3, r0, #1
|
|
8008196: 429a cmp r2, r3
|
|
8008198: d004 beq.n 80081a4 <__swbuf_r+0x6e>
|
|
800819a: 89a3 ldrh r3, [r4, #12]
|
|
800819c: 07db lsls r3, r3, #31
|
|
800819e: d5e1 bpl.n 8008164 <__swbuf_r+0x2e>
|
|
80081a0: 2e0a cmp r6, #10
|
|
80081a2: d1df bne.n 8008164 <__swbuf_r+0x2e>
|
|
80081a4: 4621 mov r1, r4
|
|
80081a6: 4628 mov r0, r5
|
|
80081a8: f001 fd82 bl 8009cb0 <_fflush_r>
|
|
80081ac: 2800 cmp r0, #0
|
|
80081ae: d0d9 beq.n 8008164 <__swbuf_r+0x2e>
|
|
80081b0: e7d6 b.n 8008160 <__swbuf_r+0x2a>
|
|
...
|
|
|
|
080081b4 <__swsetup_r>:
|
|
80081b4: b538 push {r3, r4, r5, lr}
|
|
80081b6: 4b29 ldr r3, [pc, #164] @ (800825c <__swsetup_r+0xa8>)
|
|
80081b8: 4605 mov r5, r0
|
|
80081ba: 6818 ldr r0, [r3, #0]
|
|
80081bc: 460c mov r4, r1
|
|
80081be: b118 cbz r0, 80081c8 <__swsetup_r+0x14>
|
|
80081c0: 6a03 ldr r3, [r0, #32]
|
|
80081c2: b90b cbnz r3, 80081c8 <__swsetup_r+0x14>
|
|
80081c4: f7ff fece bl 8007f64 <__sinit>
|
|
80081c8: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
80081cc: 0719 lsls r1, r3, #28
|
|
80081ce: d422 bmi.n 8008216 <__swsetup_r+0x62>
|
|
80081d0: 06da lsls r2, r3, #27
|
|
80081d2: d407 bmi.n 80081e4 <__swsetup_r+0x30>
|
|
80081d4: 2209 movs r2, #9
|
|
80081d6: 602a str r2, [r5, #0]
|
|
80081d8: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
80081dc: 81a3 strh r3, [r4, #12]
|
|
80081de: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80081e2: e033 b.n 800824c <__swsetup_r+0x98>
|
|
80081e4: 0758 lsls r0, r3, #29
|
|
80081e6: d512 bpl.n 800820e <__swsetup_r+0x5a>
|
|
80081e8: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
80081ea: b141 cbz r1, 80081fe <__swsetup_r+0x4a>
|
|
80081ec: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
80081f0: 4299 cmp r1, r3
|
|
80081f2: d002 beq.n 80081fa <__swsetup_r+0x46>
|
|
80081f4: 4628 mov r0, r5
|
|
80081f6: f000 ff1b bl 8009030 <_free_r>
|
|
80081fa: 2300 movs r3, #0
|
|
80081fc: 6363 str r3, [r4, #52] @ 0x34
|
|
80081fe: 89a3 ldrh r3, [r4, #12]
|
|
8008200: f023 0324 bic.w r3, r3, #36 @ 0x24
|
|
8008204: 81a3 strh r3, [r4, #12]
|
|
8008206: 2300 movs r3, #0
|
|
8008208: 6063 str r3, [r4, #4]
|
|
800820a: 6923 ldr r3, [r4, #16]
|
|
800820c: 6023 str r3, [r4, #0]
|
|
800820e: 89a3 ldrh r3, [r4, #12]
|
|
8008210: f043 0308 orr.w r3, r3, #8
|
|
8008214: 81a3 strh r3, [r4, #12]
|
|
8008216: 6923 ldr r3, [r4, #16]
|
|
8008218: b94b cbnz r3, 800822e <__swsetup_r+0x7a>
|
|
800821a: 89a3 ldrh r3, [r4, #12]
|
|
800821c: f403 7320 and.w r3, r3, #640 @ 0x280
|
|
8008220: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8008224: d003 beq.n 800822e <__swsetup_r+0x7a>
|
|
8008226: 4621 mov r1, r4
|
|
8008228: 4628 mov r0, r5
|
|
800822a: f001 fd8f bl 8009d4c <__smakebuf_r>
|
|
800822e: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8008232: f013 0201 ands.w r2, r3, #1
|
|
8008236: d00a beq.n 800824e <__swsetup_r+0x9a>
|
|
8008238: 2200 movs r2, #0
|
|
800823a: 60a2 str r2, [r4, #8]
|
|
800823c: 6962 ldr r2, [r4, #20]
|
|
800823e: 4252 negs r2, r2
|
|
8008240: 61a2 str r2, [r4, #24]
|
|
8008242: 6922 ldr r2, [r4, #16]
|
|
8008244: b942 cbnz r2, 8008258 <__swsetup_r+0xa4>
|
|
8008246: f013 0080 ands.w r0, r3, #128 @ 0x80
|
|
800824a: d1c5 bne.n 80081d8 <__swsetup_r+0x24>
|
|
800824c: bd38 pop {r3, r4, r5, pc}
|
|
800824e: 0799 lsls r1, r3, #30
|
|
8008250: bf58 it pl
|
|
8008252: 6962 ldrpl r2, [r4, #20]
|
|
8008254: 60a2 str r2, [r4, #8]
|
|
8008256: e7f4 b.n 8008242 <__swsetup_r+0x8e>
|
|
8008258: 2000 movs r0, #0
|
|
800825a: e7f7 b.n 800824c <__swsetup_r+0x98>
|
|
800825c: 200000dc .word 0x200000dc
|
|
|
|
08008260 <memset>:
|
|
8008260: 4402 add r2, r0
|
|
8008262: 4603 mov r3, r0
|
|
8008264: 4293 cmp r3, r2
|
|
8008266: d100 bne.n 800826a <memset+0xa>
|
|
8008268: 4770 bx lr
|
|
800826a: f803 1b01 strb.w r1, [r3], #1
|
|
800826e: e7f9 b.n 8008264 <memset+0x4>
|
|
|
|
08008270 <_localeconv_r>:
|
|
8008270: 4800 ldr r0, [pc, #0] @ (8008274 <_localeconv_r+0x4>)
|
|
8008272: 4770 bx lr
|
|
8008274: 2000021c .word 0x2000021c
|
|
|
|
08008278 <_close_r>:
|
|
8008278: b538 push {r3, r4, r5, lr}
|
|
800827a: 4d06 ldr r5, [pc, #24] @ (8008294 <_close_r+0x1c>)
|
|
800827c: 2300 movs r3, #0
|
|
800827e: 4604 mov r4, r0
|
|
8008280: 4608 mov r0, r1
|
|
8008282: 602b str r3, [r5, #0]
|
|
8008284: f7fa feb4 bl 8002ff0 <_close>
|
|
8008288: 1c43 adds r3, r0, #1
|
|
800828a: d102 bne.n 8008292 <_close_r+0x1a>
|
|
800828c: 682b ldr r3, [r5, #0]
|
|
800828e: b103 cbz r3, 8008292 <_close_r+0x1a>
|
|
8008290: 6023 str r3, [r4, #0]
|
|
8008292: bd38 pop {r3, r4, r5, pc}
|
|
8008294: 20000bb4 .word 0x20000bb4
|
|
|
|
08008298 <_lseek_r>:
|
|
8008298: b538 push {r3, r4, r5, lr}
|
|
800829a: 4d07 ldr r5, [pc, #28] @ (80082b8 <_lseek_r+0x20>)
|
|
800829c: 4604 mov r4, r0
|
|
800829e: 4608 mov r0, r1
|
|
80082a0: 4611 mov r1, r2
|
|
80082a2: 2200 movs r2, #0
|
|
80082a4: 602a str r2, [r5, #0]
|
|
80082a6: 461a mov r2, r3
|
|
80082a8: f7fa fec9 bl 800303e <_lseek>
|
|
80082ac: 1c43 adds r3, r0, #1
|
|
80082ae: d102 bne.n 80082b6 <_lseek_r+0x1e>
|
|
80082b0: 682b ldr r3, [r5, #0]
|
|
80082b2: b103 cbz r3, 80082b6 <_lseek_r+0x1e>
|
|
80082b4: 6023 str r3, [r4, #0]
|
|
80082b6: bd38 pop {r3, r4, r5, pc}
|
|
80082b8: 20000bb4 .word 0x20000bb4
|
|
|
|
080082bc <_read_r>:
|
|
80082bc: b538 push {r3, r4, r5, lr}
|
|
80082be: 4d07 ldr r5, [pc, #28] @ (80082dc <_read_r+0x20>)
|
|
80082c0: 4604 mov r4, r0
|
|
80082c2: 4608 mov r0, r1
|
|
80082c4: 4611 mov r1, r2
|
|
80082c6: 2200 movs r2, #0
|
|
80082c8: 602a str r2, [r5, #0]
|
|
80082ca: 461a mov r2, r3
|
|
80082cc: f7fa fe57 bl 8002f7e <_read>
|
|
80082d0: 1c43 adds r3, r0, #1
|
|
80082d2: d102 bne.n 80082da <_read_r+0x1e>
|
|
80082d4: 682b ldr r3, [r5, #0]
|
|
80082d6: b103 cbz r3, 80082da <_read_r+0x1e>
|
|
80082d8: 6023 str r3, [r4, #0]
|
|
80082da: bd38 pop {r3, r4, r5, pc}
|
|
80082dc: 20000bb4 .word 0x20000bb4
|
|
|
|
080082e0 <_write_r>:
|
|
80082e0: b538 push {r3, r4, r5, lr}
|
|
80082e2: 4d07 ldr r5, [pc, #28] @ (8008300 <_write_r+0x20>)
|
|
80082e4: 4604 mov r4, r0
|
|
80082e6: 4608 mov r0, r1
|
|
80082e8: 4611 mov r1, r2
|
|
80082ea: 2200 movs r2, #0
|
|
80082ec: 602a str r2, [r5, #0]
|
|
80082ee: 461a mov r2, r3
|
|
80082f0: f7fa fe62 bl 8002fb8 <_write>
|
|
80082f4: 1c43 adds r3, r0, #1
|
|
80082f6: d102 bne.n 80082fe <_write_r+0x1e>
|
|
80082f8: 682b ldr r3, [r5, #0]
|
|
80082fa: b103 cbz r3, 80082fe <_write_r+0x1e>
|
|
80082fc: 6023 str r3, [r4, #0]
|
|
80082fe: bd38 pop {r3, r4, r5, pc}
|
|
8008300: 20000bb4 .word 0x20000bb4
|
|
|
|
08008304 <__errno>:
|
|
8008304: 4b01 ldr r3, [pc, #4] @ (800830c <__errno+0x8>)
|
|
8008306: 6818 ldr r0, [r3, #0]
|
|
8008308: 4770 bx lr
|
|
800830a: bf00 nop
|
|
800830c: 200000dc .word 0x200000dc
|
|
|
|
08008310 <__libc_init_array>:
|
|
8008310: b570 push {r4, r5, r6, lr}
|
|
8008312: 4d0d ldr r5, [pc, #52] @ (8008348 <__libc_init_array+0x38>)
|
|
8008314: 4c0d ldr r4, [pc, #52] @ (800834c <__libc_init_array+0x3c>)
|
|
8008316: 1b64 subs r4, r4, r5
|
|
8008318: 10a4 asrs r4, r4, #2
|
|
800831a: 2600 movs r6, #0
|
|
800831c: 42a6 cmp r6, r4
|
|
800831e: d109 bne.n 8008334 <__libc_init_array+0x24>
|
|
8008320: 4d0b ldr r5, [pc, #44] @ (8008350 <__libc_init_array+0x40>)
|
|
8008322: 4c0c ldr r4, [pc, #48] @ (8008354 <__libc_init_array+0x44>)
|
|
8008324: f001 fe30 bl 8009f88 <_init>
|
|
8008328: 1b64 subs r4, r4, r5
|
|
800832a: 10a4 asrs r4, r4, #2
|
|
800832c: 2600 movs r6, #0
|
|
800832e: 42a6 cmp r6, r4
|
|
8008330: d105 bne.n 800833e <__libc_init_array+0x2e>
|
|
8008332: bd70 pop {r4, r5, r6, pc}
|
|
8008334: f855 3b04 ldr.w r3, [r5], #4
|
|
8008338: 4798 blx r3
|
|
800833a: 3601 adds r6, #1
|
|
800833c: e7ee b.n 800831c <__libc_init_array+0xc>
|
|
800833e: f855 3b04 ldr.w r3, [r5], #4
|
|
8008342: 4798 blx r3
|
|
8008344: 3601 adds r6, #1
|
|
8008346: e7f2 b.n 800832e <__libc_init_array+0x1e>
|
|
8008348: 0800a49c .word 0x0800a49c
|
|
800834c: 0800a49c .word 0x0800a49c
|
|
8008350: 0800a49c .word 0x0800a49c
|
|
8008354: 0800a4a0 .word 0x0800a4a0
|
|
|
|
08008358 <__retarget_lock_init_recursive>:
|
|
8008358: 4770 bx lr
|
|
|
|
0800835a <__retarget_lock_acquire_recursive>:
|
|
800835a: 4770 bx lr
|
|
|
|
0800835c <__retarget_lock_release_recursive>:
|
|
800835c: 4770 bx lr
|
|
|
|
0800835e <memcpy>:
|
|
800835e: 440a add r2, r1
|
|
8008360: 4291 cmp r1, r2
|
|
8008362: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
8008366: d100 bne.n 800836a <memcpy+0xc>
|
|
8008368: 4770 bx lr
|
|
800836a: b510 push {r4, lr}
|
|
800836c: f811 4b01 ldrb.w r4, [r1], #1
|
|
8008370: f803 4f01 strb.w r4, [r3, #1]!
|
|
8008374: 4291 cmp r1, r2
|
|
8008376: d1f9 bne.n 800836c <memcpy+0xe>
|
|
8008378: bd10 pop {r4, pc}
|
|
|
|
0800837a <quorem>:
|
|
800837a: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800837e: 6903 ldr r3, [r0, #16]
|
|
8008380: 690c ldr r4, [r1, #16]
|
|
8008382: 42a3 cmp r3, r4
|
|
8008384: 4607 mov r7, r0
|
|
8008386: db7e blt.n 8008486 <quorem+0x10c>
|
|
8008388: 3c01 subs r4, #1
|
|
800838a: f101 0814 add.w r8, r1, #20
|
|
800838e: 00a3 lsls r3, r4, #2
|
|
8008390: f100 0514 add.w r5, r0, #20
|
|
8008394: 9300 str r3, [sp, #0]
|
|
8008396: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
800839a: 9301 str r3, [sp, #4]
|
|
800839c: f858 3024 ldr.w r3, [r8, r4, lsl #2]
|
|
80083a0: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
80083a4: 3301 adds r3, #1
|
|
80083a6: 429a cmp r2, r3
|
|
80083a8: eb08 0984 add.w r9, r8, r4, lsl #2
|
|
80083ac: fbb2 f6f3 udiv r6, r2, r3
|
|
80083b0: d32e bcc.n 8008410 <quorem+0x96>
|
|
80083b2: f04f 0a00 mov.w sl, #0
|
|
80083b6: 46c4 mov ip, r8
|
|
80083b8: 46ae mov lr, r5
|
|
80083ba: 46d3 mov fp, sl
|
|
80083bc: f85c 3b04 ldr.w r3, [ip], #4
|
|
80083c0: b298 uxth r0, r3
|
|
80083c2: fb06 a000 mla r0, r6, r0, sl
|
|
80083c6: 0c02 lsrs r2, r0, #16
|
|
80083c8: 0c1b lsrs r3, r3, #16
|
|
80083ca: fb06 2303 mla r3, r6, r3, r2
|
|
80083ce: f8de 2000 ldr.w r2, [lr]
|
|
80083d2: b280 uxth r0, r0
|
|
80083d4: b292 uxth r2, r2
|
|
80083d6: 1a12 subs r2, r2, r0
|
|
80083d8: 445a add r2, fp
|
|
80083da: f8de 0000 ldr.w r0, [lr]
|
|
80083de: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
80083e2: b29b uxth r3, r3
|
|
80083e4: ebc3 4322 rsb r3, r3, r2, asr #16
|
|
80083e8: eb03 4310 add.w r3, r3, r0, lsr #16
|
|
80083ec: b292 uxth r2, r2
|
|
80083ee: ea42 4203 orr.w r2, r2, r3, lsl #16
|
|
80083f2: 45e1 cmp r9, ip
|
|
80083f4: f84e 2b04 str.w r2, [lr], #4
|
|
80083f8: ea4f 4b23 mov.w fp, r3, asr #16
|
|
80083fc: d2de bcs.n 80083bc <quorem+0x42>
|
|
80083fe: 9b00 ldr r3, [sp, #0]
|
|
8008400: 58eb ldr r3, [r5, r3]
|
|
8008402: b92b cbnz r3, 8008410 <quorem+0x96>
|
|
8008404: 9b01 ldr r3, [sp, #4]
|
|
8008406: 3b04 subs r3, #4
|
|
8008408: 429d cmp r5, r3
|
|
800840a: 461a mov r2, r3
|
|
800840c: d32f bcc.n 800846e <quorem+0xf4>
|
|
800840e: 613c str r4, [r7, #16]
|
|
8008410: 4638 mov r0, r7
|
|
8008412: f001 f97f bl 8009714 <__mcmp>
|
|
8008416: 2800 cmp r0, #0
|
|
8008418: db25 blt.n 8008466 <quorem+0xec>
|
|
800841a: 4629 mov r1, r5
|
|
800841c: 2000 movs r0, #0
|
|
800841e: f858 2b04 ldr.w r2, [r8], #4
|
|
8008422: f8d1 c000 ldr.w ip, [r1]
|
|
8008426: fa1f fe82 uxth.w lr, r2
|
|
800842a: fa1f f38c uxth.w r3, ip
|
|
800842e: eba3 030e sub.w r3, r3, lr
|
|
8008432: 4403 add r3, r0
|
|
8008434: 0c12 lsrs r2, r2, #16
|
|
8008436: ebc2 4223 rsb r2, r2, r3, asr #16
|
|
800843a: eb02 421c add.w r2, r2, ip, lsr #16
|
|
800843e: b29b uxth r3, r3
|
|
8008440: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8008444: 45c1 cmp r9, r8
|
|
8008446: f841 3b04 str.w r3, [r1], #4
|
|
800844a: ea4f 4022 mov.w r0, r2, asr #16
|
|
800844e: d2e6 bcs.n 800841e <quorem+0xa4>
|
|
8008450: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
8008454: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
8008458: b922 cbnz r2, 8008464 <quorem+0xea>
|
|
800845a: 3b04 subs r3, #4
|
|
800845c: 429d cmp r5, r3
|
|
800845e: 461a mov r2, r3
|
|
8008460: d30b bcc.n 800847a <quorem+0x100>
|
|
8008462: 613c str r4, [r7, #16]
|
|
8008464: 3601 adds r6, #1
|
|
8008466: 4630 mov r0, r6
|
|
8008468: b003 add sp, #12
|
|
800846a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800846e: 6812 ldr r2, [r2, #0]
|
|
8008470: 3b04 subs r3, #4
|
|
8008472: 2a00 cmp r2, #0
|
|
8008474: d1cb bne.n 800840e <quorem+0x94>
|
|
8008476: 3c01 subs r4, #1
|
|
8008478: e7c6 b.n 8008408 <quorem+0x8e>
|
|
800847a: 6812 ldr r2, [r2, #0]
|
|
800847c: 3b04 subs r3, #4
|
|
800847e: 2a00 cmp r2, #0
|
|
8008480: d1ef bne.n 8008462 <quorem+0xe8>
|
|
8008482: 3c01 subs r4, #1
|
|
8008484: e7ea b.n 800845c <quorem+0xe2>
|
|
8008486: 2000 movs r0, #0
|
|
8008488: e7ee b.n 8008468 <quorem+0xee>
|
|
800848a: 0000 movs r0, r0
|
|
800848c: 0000 movs r0, r0
|
|
...
|
|
|
|
08008490 <_dtoa_r>:
|
|
8008490: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8008494: 69c7 ldr r7, [r0, #28]
|
|
8008496: b097 sub sp, #92 @ 0x5c
|
|
8008498: ed8d 0b04 vstr d0, [sp, #16]
|
|
800849c: ec55 4b10 vmov r4, r5, d0
|
|
80084a0: 9e20 ldr r6, [sp, #128] @ 0x80
|
|
80084a2: 9107 str r1, [sp, #28]
|
|
80084a4: 4681 mov r9, r0
|
|
80084a6: 920c str r2, [sp, #48] @ 0x30
|
|
80084a8: 9311 str r3, [sp, #68] @ 0x44
|
|
80084aa: b97f cbnz r7, 80084cc <_dtoa_r+0x3c>
|
|
80084ac: 2010 movs r0, #16
|
|
80084ae: f000 fe09 bl 80090c4 <malloc>
|
|
80084b2: 4602 mov r2, r0
|
|
80084b4: f8c9 001c str.w r0, [r9, #28]
|
|
80084b8: b920 cbnz r0, 80084c4 <_dtoa_r+0x34>
|
|
80084ba: 4ba9 ldr r3, [pc, #676] @ (8008760 <_dtoa_r+0x2d0>)
|
|
80084bc: 21ef movs r1, #239 @ 0xef
|
|
80084be: 48a9 ldr r0, [pc, #676] @ (8008764 <_dtoa_r+0x2d4>)
|
|
80084c0: f001 fcb2 bl 8009e28 <__assert_func>
|
|
80084c4: e9c0 7701 strd r7, r7, [r0, #4]
|
|
80084c8: 6007 str r7, [r0, #0]
|
|
80084ca: 60c7 str r7, [r0, #12]
|
|
80084cc: f8d9 301c ldr.w r3, [r9, #28]
|
|
80084d0: 6819 ldr r1, [r3, #0]
|
|
80084d2: b159 cbz r1, 80084ec <_dtoa_r+0x5c>
|
|
80084d4: 685a ldr r2, [r3, #4]
|
|
80084d6: 604a str r2, [r1, #4]
|
|
80084d8: 2301 movs r3, #1
|
|
80084da: 4093 lsls r3, r2
|
|
80084dc: 608b str r3, [r1, #8]
|
|
80084de: 4648 mov r0, r9
|
|
80084e0: f000 fee6 bl 80092b0 <_Bfree>
|
|
80084e4: f8d9 301c ldr.w r3, [r9, #28]
|
|
80084e8: 2200 movs r2, #0
|
|
80084ea: 601a str r2, [r3, #0]
|
|
80084ec: 1e2b subs r3, r5, #0
|
|
80084ee: bfb9 ittee lt
|
|
80084f0: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000
|
|
80084f4: 9305 strlt r3, [sp, #20]
|
|
80084f6: 2300 movge r3, #0
|
|
80084f8: 6033 strge r3, [r6, #0]
|
|
80084fa: 9f05 ldr r7, [sp, #20]
|
|
80084fc: 4b9a ldr r3, [pc, #616] @ (8008768 <_dtoa_r+0x2d8>)
|
|
80084fe: bfbc itt lt
|
|
8008500: 2201 movlt r2, #1
|
|
8008502: 6032 strlt r2, [r6, #0]
|
|
8008504: 43bb bics r3, r7
|
|
8008506: d112 bne.n 800852e <_dtoa_r+0x9e>
|
|
8008508: 9a11 ldr r2, [sp, #68] @ 0x44
|
|
800850a: f242 730f movw r3, #9999 @ 0x270f
|
|
800850e: 6013 str r3, [r2, #0]
|
|
8008510: f3c7 0313 ubfx r3, r7, #0, #20
|
|
8008514: 4323 orrs r3, r4
|
|
8008516: f000 855a beq.w 8008fce <_dtoa_r+0xb3e>
|
|
800851a: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
800851c: f8df a25c ldr.w sl, [pc, #604] @ 800877c <_dtoa_r+0x2ec>
|
|
8008520: 2b00 cmp r3, #0
|
|
8008522: f000 855c beq.w 8008fde <_dtoa_r+0xb4e>
|
|
8008526: f10a 0303 add.w r3, sl, #3
|
|
800852a: f000 bd56 b.w 8008fda <_dtoa_r+0xb4a>
|
|
800852e: ed9d 7b04 vldr d7, [sp, #16]
|
|
8008532: 2200 movs r2, #0
|
|
8008534: ec51 0b17 vmov r0, r1, d7
|
|
8008538: 2300 movs r3, #0
|
|
800853a: ed8d 7b0a vstr d7, [sp, #40] @ 0x28
|
|
800853e: f7f8 fac3 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8008542: 4680 mov r8, r0
|
|
8008544: b158 cbz r0, 800855e <_dtoa_r+0xce>
|
|
8008546: 9a11 ldr r2, [sp, #68] @ 0x44
|
|
8008548: 2301 movs r3, #1
|
|
800854a: 6013 str r3, [r2, #0]
|
|
800854c: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
800854e: b113 cbz r3, 8008556 <_dtoa_r+0xc6>
|
|
8008550: 9a21 ldr r2, [sp, #132] @ 0x84
|
|
8008552: 4b86 ldr r3, [pc, #536] @ (800876c <_dtoa_r+0x2dc>)
|
|
8008554: 6013 str r3, [r2, #0]
|
|
8008556: f8df a228 ldr.w sl, [pc, #552] @ 8008780 <_dtoa_r+0x2f0>
|
|
800855a: f000 bd40 b.w 8008fde <_dtoa_r+0xb4e>
|
|
800855e: ed9d 0b0a vldr d0, [sp, #40] @ 0x28
|
|
8008562: aa14 add r2, sp, #80 @ 0x50
|
|
8008564: a915 add r1, sp, #84 @ 0x54
|
|
8008566: 4648 mov r0, r9
|
|
8008568: f001 f984 bl 8009874 <__d2b>
|
|
800856c: f3c7 560a ubfx r6, r7, #20, #11
|
|
8008570: 9002 str r0, [sp, #8]
|
|
8008572: 2e00 cmp r6, #0
|
|
8008574: d078 beq.n 8008668 <_dtoa_r+0x1d8>
|
|
8008576: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8008578: f8cd 8048 str.w r8, [sp, #72] @ 0x48
|
|
800857c: f3c3 0313 ubfx r3, r3, #0, #20
|
|
8008580: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
8008584: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000
|
|
8008588: f443 1340 orr.w r3, r3, #3145728 @ 0x300000
|
|
800858c: f2a6 36ff subw r6, r6, #1023 @ 0x3ff
|
|
8008590: 4619 mov r1, r3
|
|
8008592: 2200 movs r2, #0
|
|
8008594: 4b76 ldr r3, [pc, #472] @ (8008770 <_dtoa_r+0x2e0>)
|
|
8008596: f7f7 fe77 bl 8000288 <__aeabi_dsub>
|
|
800859a: a36b add r3, pc, #428 @ (adr r3, 8008748 <_dtoa_r+0x2b8>)
|
|
800859c: e9d3 2300 ldrd r2, r3, [r3]
|
|
80085a0: f7f8 f82a bl 80005f8 <__aeabi_dmul>
|
|
80085a4: a36a add r3, pc, #424 @ (adr r3, 8008750 <_dtoa_r+0x2c0>)
|
|
80085a6: e9d3 2300 ldrd r2, r3, [r3]
|
|
80085aa: f7f7 fe6f bl 800028c <__adddf3>
|
|
80085ae: 4604 mov r4, r0
|
|
80085b0: 4630 mov r0, r6
|
|
80085b2: 460d mov r5, r1
|
|
80085b4: f7f7 ffb6 bl 8000524 <__aeabi_i2d>
|
|
80085b8: a367 add r3, pc, #412 @ (adr r3, 8008758 <_dtoa_r+0x2c8>)
|
|
80085ba: e9d3 2300 ldrd r2, r3, [r3]
|
|
80085be: f7f8 f81b bl 80005f8 <__aeabi_dmul>
|
|
80085c2: 4602 mov r2, r0
|
|
80085c4: 460b mov r3, r1
|
|
80085c6: 4620 mov r0, r4
|
|
80085c8: 4629 mov r1, r5
|
|
80085ca: f7f7 fe5f bl 800028c <__adddf3>
|
|
80085ce: 4604 mov r4, r0
|
|
80085d0: 460d mov r5, r1
|
|
80085d2: f7f8 fac1 bl 8000b58 <__aeabi_d2iz>
|
|
80085d6: 2200 movs r2, #0
|
|
80085d8: 4607 mov r7, r0
|
|
80085da: 2300 movs r3, #0
|
|
80085dc: 4620 mov r0, r4
|
|
80085de: 4629 mov r1, r5
|
|
80085e0: f7f8 fa7c bl 8000adc <__aeabi_dcmplt>
|
|
80085e4: b140 cbz r0, 80085f8 <_dtoa_r+0x168>
|
|
80085e6: 4638 mov r0, r7
|
|
80085e8: f7f7 ff9c bl 8000524 <__aeabi_i2d>
|
|
80085ec: 4622 mov r2, r4
|
|
80085ee: 462b mov r3, r5
|
|
80085f0: f7f8 fa6a bl 8000ac8 <__aeabi_dcmpeq>
|
|
80085f4: b900 cbnz r0, 80085f8 <_dtoa_r+0x168>
|
|
80085f6: 3f01 subs r7, #1
|
|
80085f8: 2f16 cmp r7, #22
|
|
80085fa: d852 bhi.n 80086a2 <_dtoa_r+0x212>
|
|
80085fc: 4b5d ldr r3, [pc, #372] @ (8008774 <_dtoa_r+0x2e4>)
|
|
80085fe: eb03 03c7 add.w r3, r3, r7, lsl #3
|
|
8008602: e9d3 2300 ldrd r2, r3, [r3]
|
|
8008606: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
800860a: f7f8 fa67 bl 8000adc <__aeabi_dcmplt>
|
|
800860e: 2800 cmp r0, #0
|
|
8008610: d049 beq.n 80086a6 <_dtoa_r+0x216>
|
|
8008612: 3f01 subs r7, #1
|
|
8008614: 2300 movs r3, #0
|
|
8008616: 9310 str r3, [sp, #64] @ 0x40
|
|
8008618: 9b14 ldr r3, [sp, #80] @ 0x50
|
|
800861a: 1b9b subs r3, r3, r6
|
|
800861c: 1e5a subs r2, r3, #1
|
|
800861e: bf45 ittet mi
|
|
8008620: f1c3 0301 rsbmi r3, r3, #1
|
|
8008624: 9300 strmi r3, [sp, #0]
|
|
8008626: 2300 movpl r3, #0
|
|
8008628: 2300 movmi r3, #0
|
|
800862a: 9206 str r2, [sp, #24]
|
|
800862c: bf54 ite pl
|
|
800862e: 9300 strpl r3, [sp, #0]
|
|
8008630: 9306 strmi r3, [sp, #24]
|
|
8008632: 2f00 cmp r7, #0
|
|
8008634: db39 blt.n 80086aa <_dtoa_r+0x21a>
|
|
8008636: 9b06 ldr r3, [sp, #24]
|
|
8008638: 970d str r7, [sp, #52] @ 0x34
|
|
800863a: 443b add r3, r7
|
|
800863c: 9306 str r3, [sp, #24]
|
|
800863e: 2300 movs r3, #0
|
|
8008640: 9308 str r3, [sp, #32]
|
|
8008642: 9b07 ldr r3, [sp, #28]
|
|
8008644: 2b09 cmp r3, #9
|
|
8008646: d863 bhi.n 8008710 <_dtoa_r+0x280>
|
|
8008648: 2b05 cmp r3, #5
|
|
800864a: bfc4 itt gt
|
|
800864c: 3b04 subgt r3, #4
|
|
800864e: 9307 strgt r3, [sp, #28]
|
|
8008650: 9b07 ldr r3, [sp, #28]
|
|
8008652: f1a3 0302 sub.w r3, r3, #2
|
|
8008656: bfcc ite gt
|
|
8008658: 2400 movgt r4, #0
|
|
800865a: 2401 movle r4, #1
|
|
800865c: 2b03 cmp r3, #3
|
|
800865e: d863 bhi.n 8008728 <_dtoa_r+0x298>
|
|
8008660: e8df f003 tbb [pc, r3]
|
|
8008664: 2b375452 .word 0x2b375452
|
|
8008668: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50
|
|
800866c: 441e add r6, r3
|
|
800866e: f206 4332 addw r3, r6, #1074 @ 0x432
|
|
8008672: 2b20 cmp r3, #32
|
|
8008674: bfc1 itttt gt
|
|
8008676: f1c3 0340 rsbgt r3, r3, #64 @ 0x40
|
|
800867a: 409f lslgt r7, r3
|
|
800867c: f206 4312 addwgt r3, r6, #1042 @ 0x412
|
|
8008680: fa24 f303 lsrgt.w r3, r4, r3
|
|
8008684: bfd6 itet le
|
|
8008686: f1c3 0320 rsble r3, r3, #32
|
|
800868a: ea47 0003 orrgt.w r0, r7, r3
|
|
800868e: fa04 f003 lslle.w r0, r4, r3
|
|
8008692: f7f7 ff37 bl 8000504 <__aeabi_ui2d>
|
|
8008696: 2201 movs r2, #1
|
|
8008698: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000
|
|
800869c: 3e01 subs r6, #1
|
|
800869e: 9212 str r2, [sp, #72] @ 0x48
|
|
80086a0: e776 b.n 8008590 <_dtoa_r+0x100>
|
|
80086a2: 2301 movs r3, #1
|
|
80086a4: e7b7 b.n 8008616 <_dtoa_r+0x186>
|
|
80086a6: 9010 str r0, [sp, #64] @ 0x40
|
|
80086a8: e7b6 b.n 8008618 <_dtoa_r+0x188>
|
|
80086aa: 9b00 ldr r3, [sp, #0]
|
|
80086ac: 1bdb subs r3, r3, r7
|
|
80086ae: 9300 str r3, [sp, #0]
|
|
80086b0: 427b negs r3, r7
|
|
80086b2: 9308 str r3, [sp, #32]
|
|
80086b4: 2300 movs r3, #0
|
|
80086b6: 930d str r3, [sp, #52] @ 0x34
|
|
80086b8: e7c3 b.n 8008642 <_dtoa_r+0x1b2>
|
|
80086ba: 2301 movs r3, #1
|
|
80086bc: 9309 str r3, [sp, #36] @ 0x24
|
|
80086be: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
80086c0: eb07 0b03 add.w fp, r7, r3
|
|
80086c4: f10b 0301 add.w r3, fp, #1
|
|
80086c8: 2b01 cmp r3, #1
|
|
80086ca: 9303 str r3, [sp, #12]
|
|
80086cc: bfb8 it lt
|
|
80086ce: 2301 movlt r3, #1
|
|
80086d0: e006 b.n 80086e0 <_dtoa_r+0x250>
|
|
80086d2: 2301 movs r3, #1
|
|
80086d4: 9309 str r3, [sp, #36] @ 0x24
|
|
80086d6: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
80086d8: 2b00 cmp r3, #0
|
|
80086da: dd28 ble.n 800872e <_dtoa_r+0x29e>
|
|
80086dc: 469b mov fp, r3
|
|
80086de: 9303 str r3, [sp, #12]
|
|
80086e0: f8d9 001c ldr.w r0, [r9, #28]
|
|
80086e4: 2100 movs r1, #0
|
|
80086e6: 2204 movs r2, #4
|
|
80086e8: f102 0514 add.w r5, r2, #20
|
|
80086ec: 429d cmp r5, r3
|
|
80086ee: d926 bls.n 800873e <_dtoa_r+0x2ae>
|
|
80086f0: 6041 str r1, [r0, #4]
|
|
80086f2: 4648 mov r0, r9
|
|
80086f4: f000 fd9c bl 8009230 <_Balloc>
|
|
80086f8: 4682 mov sl, r0
|
|
80086fa: 2800 cmp r0, #0
|
|
80086fc: d142 bne.n 8008784 <_dtoa_r+0x2f4>
|
|
80086fe: 4b1e ldr r3, [pc, #120] @ (8008778 <_dtoa_r+0x2e8>)
|
|
8008700: 4602 mov r2, r0
|
|
8008702: f240 11af movw r1, #431 @ 0x1af
|
|
8008706: e6da b.n 80084be <_dtoa_r+0x2e>
|
|
8008708: 2300 movs r3, #0
|
|
800870a: e7e3 b.n 80086d4 <_dtoa_r+0x244>
|
|
800870c: 2300 movs r3, #0
|
|
800870e: e7d5 b.n 80086bc <_dtoa_r+0x22c>
|
|
8008710: 2401 movs r4, #1
|
|
8008712: 2300 movs r3, #0
|
|
8008714: 9307 str r3, [sp, #28]
|
|
8008716: 9409 str r4, [sp, #36] @ 0x24
|
|
8008718: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff
|
|
800871c: 2200 movs r2, #0
|
|
800871e: f8cd b00c str.w fp, [sp, #12]
|
|
8008722: 2312 movs r3, #18
|
|
8008724: 920c str r2, [sp, #48] @ 0x30
|
|
8008726: e7db b.n 80086e0 <_dtoa_r+0x250>
|
|
8008728: 2301 movs r3, #1
|
|
800872a: 9309 str r3, [sp, #36] @ 0x24
|
|
800872c: e7f4 b.n 8008718 <_dtoa_r+0x288>
|
|
800872e: f04f 0b01 mov.w fp, #1
|
|
8008732: f8cd b00c str.w fp, [sp, #12]
|
|
8008736: 465b mov r3, fp
|
|
8008738: f8cd b030 str.w fp, [sp, #48] @ 0x30
|
|
800873c: e7d0 b.n 80086e0 <_dtoa_r+0x250>
|
|
800873e: 3101 adds r1, #1
|
|
8008740: 0052 lsls r2, r2, #1
|
|
8008742: e7d1 b.n 80086e8 <_dtoa_r+0x258>
|
|
8008744: f3af 8000 nop.w
|
|
8008748: 636f4361 .word 0x636f4361
|
|
800874c: 3fd287a7 .word 0x3fd287a7
|
|
8008750: 8b60c8b3 .word 0x8b60c8b3
|
|
8008754: 3fc68a28 .word 0x3fc68a28
|
|
8008758: 509f79fb .word 0x509f79fb
|
|
800875c: 3fd34413 .word 0x3fd34413
|
|
8008760: 0800a161 .word 0x0800a161
|
|
8008764: 0800a178 .word 0x0800a178
|
|
8008768: 7ff00000 .word 0x7ff00000
|
|
800876c: 0800a131 .word 0x0800a131
|
|
8008770: 3ff80000 .word 0x3ff80000
|
|
8008774: 0800a2c8 .word 0x0800a2c8
|
|
8008778: 0800a1d0 .word 0x0800a1d0
|
|
800877c: 0800a15d .word 0x0800a15d
|
|
8008780: 0800a130 .word 0x0800a130
|
|
8008784: f8d9 301c ldr.w r3, [r9, #28]
|
|
8008788: 6018 str r0, [r3, #0]
|
|
800878a: 9b03 ldr r3, [sp, #12]
|
|
800878c: 2b0e cmp r3, #14
|
|
800878e: f200 80a1 bhi.w 80088d4 <_dtoa_r+0x444>
|
|
8008792: 2c00 cmp r4, #0
|
|
8008794: f000 809e beq.w 80088d4 <_dtoa_r+0x444>
|
|
8008798: 2f00 cmp r7, #0
|
|
800879a: dd33 ble.n 8008804 <_dtoa_r+0x374>
|
|
800879c: 4b9c ldr r3, [pc, #624] @ (8008a10 <_dtoa_r+0x580>)
|
|
800879e: f007 020f and.w r2, r7, #15
|
|
80087a2: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
80087a6: ed93 7b00 vldr d7, [r3]
|
|
80087aa: 05f8 lsls r0, r7, #23
|
|
80087ac: ed8d 7b0e vstr d7, [sp, #56] @ 0x38
|
|
80087b0: ea4f 1427 mov.w r4, r7, asr #4
|
|
80087b4: d516 bpl.n 80087e4 <_dtoa_r+0x354>
|
|
80087b6: 4b97 ldr r3, [pc, #604] @ (8008a14 <_dtoa_r+0x584>)
|
|
80087b8: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
80087bc: e9d3 2308 ldrd r2, r3, [r3, #32]
|
|
80087c0: f7f8 f844 bl 800084c <__aeabi_ddiv>
|
|
80087c4: e9cd 0104 strd r0, r1, [sp, #16]
|
|
80087c8: f004 040f and.w r4, r4, #15
|
|
80087cc: 2603 movs r6, #3
|
|
80087ce: 4d91 ldr r5, [pc, #580] @ (8008a14 <_dtoa_r+0x584>)
|
|
80087d0: b954 cbnz r4, 80087e8 <_dtoa_r+0x358>
|
|
80087d2: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
80087d6: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80087da: f7f8 f837 bl 800084c <__aeabi_ddiv>
|
|
80087de: e9cd 0104 strd r0, r1, [sp, #16]
|
|
80087e2: e028 b.n 8008836 <_dtoa_r+0x3a6>
|
|
80087e4: 2602 movs r6, #2
|
|
80087e6: e7f2 b.n 80087ce <_dtoa_r+0x33e>
|
|
80087e8: 07e1 lsls r1, r4, #31
|
|
80087ea: d508 bpl.n 80087fe <_dtoa_r+0x36e>
|
|
80087ec: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
80087f0: e9d5 2300 ldrd r2, r3, [r5]
|
|
80087f4: f7f7 ff00 bl 80005f8 <__aeabi_dmul>
|
|
80087f8: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
80087fc: 3601 adds r6, #1
|
|
80087fe: 1064 asrs r4, r4, #1
|
|
8008800: 3508 adds r5, #8
|
|
8008802: e7e5 b.n 80087d0 <_dtoa_r+0x340>
|
|
8008804: f000 80af beq.w 8008966 <_dtoa_r+0x4d6>
|
|
8008808: 427c negs r4, r7
|
|
800880a: 4b81 ldr r3, [pc, #516] @ (8008a10 <_dtoa_r+0x580>)
|
|
800880c: 4d81 ldr r5, [pc, #516] @ (8008a14 <_dtoa_r+0x584>)
|
|
800880e: f004 020f and.w r2, r4, #15
|
|
8008812: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
8008816: e9d3 2300 ldrd r2, r3, [r3]
|
|
800881a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
800881e: f7f7 feeb bl 80005f8 <__aeabi_dmul>
|
|
8008822: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8008826: 1124 asrs r4, r4, #4
|
|
8008828: 2300 movs r3, #0
|
|
800882a: 2602 movs r6, #2
|
|
800882c: 2c00 cmp r4, #0
|
|
800882e: f040 808f bne.w 8008950 <_dtoa_r+0x4c0>
|
|
8008832: 2b00 cmp r3, #0
|
|
8008834: d1d3 bne.n 80087de <_dtoa_r+0x34e>
|
|
8008836: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
8008838: e9dd 4504 ldrd r4, r5, [sp, #16]
|
|
800883c: 2b00 cmp r3, #0
|
|
800883e: f000 8094 beq.w 800896a <_dtoa_r+0x4da>
|
|
8008842: 4b75 ldr r3, [pc, #468] @ (8008a18 <_dtoa_r+0x588>)
|
|
8008844: 2200 movs r2, #0
|
|
8008846: 4620 mov r0, r4
|
|
8008848: 4629 mov r1, r5
|
|
800884a: f7f8 f947 bl 8000adc <__aeabi_dcmplt>
|
|
800884e: 2800 cmp r0, #0
|
|
8008850: f000 808b beq.w 800896a <_dtoa_r+0x4da>
|
|
8008854: 9b03 ldr r3, [sp, #12]
|
|
8008856: 2b00 cmp r3, #0
|
|
8008858: f000 8087 beq.w 800896a <_dtoa_r+0x4da>
|
|
800885c: f1bb 0f00 cmp.w fp, #0
|
|
8008860: dd34 ble.n 80088cc <_dtoa_r+0x43c>
|
|
8008862: 4620 mov r0, r4
|
|
8008864: 4b6d ldr r3, [pc, #436] @ (8008a1c <_dtoa_r+0x58c>)
|
|
8008866: 2200 movs r2, #0
|
|
8008868: 4629 mov r1, r5
|
|
800886a: f7f7 fec5 bl 80005f8 <__aeabi_dmul>
|
|
800886e: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8008872: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
|
|
8008876: 3601 adds r6, #1
|
|
8008878: 465c mov r4, fp
|
|
800887a: 4630 mov r0, r6
|
|
800887c: f7f7 fe52 bl 8000524 <__aeabi_i2d>
|
|
8008880: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8008884: f7f7 feb8 bl 80005f8 <__aeabi_dmul>
|
|
8008888: 4b65 ldr r3, [pc, #404] @ (8008a20 <_dtoa_r+0x590>)
|
|
800888a: 2200 movs r2, #0
|
|
800888c: f7f7 fcfe bl 800028c <__adddf3>
|
|
8008890: 4605 mov r5, r0
|
|
8008892: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000
|
|
8008896: 2c00 cmp r4, #0
|
|
8008898: d16a bne.n 8008970 <_dtoa_r+0x4e0>
|
|
800889a: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
800889e: 4b61 ldr r3, [pc, #388] @ (8008a24 <_dtoa_r+0x594>)
|
|
80088a0: 2200 movs r2, #0
|
|
80088a2: f7f7 fcf1 bl 8000288 <__aeabi_dsub>
|
|
80088a6: 4602 mov r2, r0
|
|
80088a8: 460b mov r3, r1
|
|
80088aa: e9cd 2304 strd r2, r3, [sp, #16]
|
|
80088ae: 462a mov r2, r5
|
|
80088b0: 4633 mov r3, r6
|
|
80088b2: f7f8 f931 bl 8000b18 <__aeabi_dcmpgt>
|
|
80088b6: 2800 cmp r0, #0
|
|
80088b8: f040 8298 bne.w 8008dec <_dtoa_r+0x95c>
|
|
80088bc: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80088c0: 462a mov r2, r5
|
|
80088c2: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000
|
|
80088c6: f7f8 f909 bl 8000adc <__aeabi_dcmplt>
|
|
80088ca: bb38 cbnz r0, 800891c <_dtoa_r+0x48c>
|
|
80088cc: e9dd 340a ldrd r3, r4, [sp, #40] @ 0x28
|
|
80088d0: e9cd 3404 strd r3, r4, [sp, #16]
|
|
80088d4: 9b15 ldr r3, [sp, #84] @ 0x54
|
|
80088d6: 2b00 cmp r3, #0
|
|
80088d8: f2c0 8157 blt.w 8008b8a <_dtoa_r+0x6fa>
|
|
80088dc: 2f0e cmp r7, #14
|
|
80088de: f300 8154 bgt.w 8008b8a <_dtoa_r+0x6fa>
|
|
80088e2: 4b4b ldr r3, [pc, #300] @ (8008a10 <_dtoa_r+0x580>)
|
|
80088e4: eb03 03c7 add.w r3, r3, r7, lsl #3
|
|
80088e8: ed93 7b00 vldr d7, [r3]
|
|
80088ec: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
80088ee: 2b00 cmp r3, #0
|
|
80088f0: ed8d 7b00 vstr d7, [sp]
|
|
80088f4: f280 80e5 bge.w 8008ac2 <_dtoa_r+0x632>
|
|
80088f8: 9b03 ldr r3, [sp, #12]
|
|
80088fa: 2b00 cmp r3, #0
|
|
80088fc: f300 80e1 bgt.w 8008ac2 <_dtoa_r+0x632>
|
|
8008900: d10c bne.n 800891c <_dtoa_r+0x48c>
|
|
8008902: 4b48 ldr r3, [pc, #288] @ (8008a24 <_dtoa_r+0x594>)
|
|
8008904: 2200 movs r2, #0
|
|
8008906: ec51 0b17 vmov r0, r1, d7
|
|
800890a: f7f7 fe75 bl 80005f8 <__aeabi_dmul>
|
|
800890e: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8008912: f7f8 f8f7 bl 8000b04 <__aeabi_dcmpge>
|
|
8008916: 2800 cmp r0, #0
|
|
8008918: f000 8266 beq.w 8008de8 <_dtoa_r+0x958>
|
|
800891c: 2400 movs r4, #0
|
|
800891e: 4625 mov r5, r4
|
|
8008920: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8008922: 4656 mov r6, sl
|
|
8008924: ea6f 0803 mvn.w r8, r3
|
|
8008928: 2700 movs r7, #0
|
|
800892a: 4621 mov r1, r4
|
|
800892c: 4648 mov r0, r9
|
|
800892e: f000 fcbf bl 80092b0 <_Bfree>
|
|
8008932: 2d00 cmp r5, #0
|
|
8008934: f000 80bd beq.w 8008ab2 <_dtoa_r+0x622>
|
|
8008938: b12f cbz r7, 8008946 <_dtoa_r+0x4b6>
|
|
800893a: 42af cmp r7, r5
|
|
800893c: d003 beq.n 8008946 <_dtoa_r+0x4b6>
|
|
800893e: 4639 mov r1, r7
|
|
8008940: 4648 mov r0, r9
|
|
8008942: f000 fcb5 bl 80092b0 <_Bfree>
|
|
8008946: 4629 mov r1, r5
|
|
8008948: 4648 mov r0, r9
|
|
800894a: f000 fcb1 bl 80092b0 <_Bfree>
|
|
800894e: e0b0 b.n 8008ab2 <_dtoa_r+0x622>
|
|
8008950: 07e2 lsls r2, r4, #31
|
|
8008952: d505 bpl.n 8008960 <_dtoa_r+0x4d0>
|
|
8008954: e9d5 2300 ldrd r2, r3, [r5]
|
|
8008958: f7f7 fe4e bl 80005f8 <__aeabi_dmul>
|
|
800895c: 3601 adds r6, #1
|
|
800895e: 2301 movs r3, #1
|
|
8008960: 1064 asrs r4, r4, #1
|
|
8008962: 3508 adds r5, #8
|
|
8008964: e762 b.n 800882c <_dtoa_r+0x39c>
|
|
8008966: 2602 movs r6, #2
|
|
8008968: e765 b.n 8008836 <_dtoa_r+0x3a6>
|
|
800896a: 9c03 ldr r4, [sp, #12]
|
|
800896c: 46b8 mov r8, r7
|
|
800896e: e784 b.n 800887a <_dtoa_r+0x3ea>
|
|
8008970: 4b27 ldr r3, [pc, #156] @ (8008a10 <_dtoa_r+0x580>)
|
|
8008972: 9909 ldr r1, [sp, #36] @ 0x24
|
|
8008974: eb03 03c4 add.w r3, r3, r4, lsl #3
|
|
8008978: e953 2302 ldrd r2, r3, [r3, #-8]
|
|
800897c: 4454 add r4, sl
|
|
800897e: 2900 cmp r1, #0
|
|
8008980: d054 beq.n 8008a2c <_dtoa_r+0x59c>
|
|
8008982: 4929 ldr r1, [pc, #164] @ (8008a28 <_dtoa_r+0x598>)
|
|
8008984: 2000 movs r0, #0
|
|
8008986: f7f7 ff61 bl 800084c <__aeabi_ddiv>
|
|
800898a: 4633 mov r3, r6
|
|
800898c: 462a mov r2, r5
|
|
800898e: f7f7 fc7b bl 8000288 <__aeabi_dsub>
|
|
8008992: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8008996: 4656 mov r6, sl
|
|
8008998: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
800899c: f7f8 f8dc bl 8000b58 <__aeabi_d2iz>
|
|
80089a0: 4605 mov r5, r0
|
|
80089a2: f7f7 fdbf bl 8000524 <__aeabi_i2d>
|
|
80089a6: 4602 mov r2, r0
|
|
80089a8: 460b mov r3, r1
|
|
80089aa: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80089ae: f7f7 fc6b bl 8000288 <__aeabi_dsub>
|
|
80089b2: 3530 adds r5, #48 @ 0x30
|
|
80089b4: 4602 mov r2, r0
|
|
80089b6: 460b mov r3, r1
|
|
80089b8: e9cd 2304 strd r2, r3, [sp, #16]
|
|
80089bc: f806 5b01 strb.w r5, [r6], #1
|
|
80089c0: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
80089c4: f7f8 f88a bl 8000adc <__aeabi_dcmplt>
|
|
80089c8: 2800 cmp r0, #0
|
|
80089ca: d172 bne.n 8008ab2 <_dtoa_r+0x622>
|
|
80089cc: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
80089d0: 4911 ldr r1, [pc, #68] @ (8008a18 <_dtoa_r+0x588>)
|
|
80089d2: 2000 movs r0, #0
|
|
80089d4: f7f7 fc58 bl 8000288 <__aeabi_dsub>
|
|
80089d8: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
80089dc: f7f8 f87e bl 8000adc <__aeabi_dcmplt>
|
|
80089e0: 2800 cmp r0, #0
|
|
80089e2: f040 80b4 bne.w 8008b4e <_dtoa_r+0x6be>
|
|
80089e6: 42a6 cmp r6, r4
|
|
80089e8: f43f af70 beq.w 80088cc <_dtoa_r+0x43c>
|
|
80089ec: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
80089f0: 4b0a ldr r3, [pc, #40] @ (8008a1c <_dtoa_r+0x58c>)
|
|
80089f2: 2200 movs r2, #0
|
|
80089f4: f7f7 fe00 bl 80005f8 <__aeabi_dmul>
|
|
80089f8: 4b08 ldr r3, [pc, #32] @ (8008a1c <_dtoa_r+0x58c>)
|
|
80089fa: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
80089fe: 2200 movs r2, #0
|
|
8008a00: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8008a04: f7f7 fdf8 bl 80005f8 <__aeabi_dmul>
|
|
8008a08: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8008a0c: e7c4 b.n 8008998 <_dtoa_r+0x508>
|
|
8008a0e: bf00 nop
|
|
8008a10: 0800a2c8 .word 0x0800a2c8
|
|
8008a14: 0800a2a0 .word 0x0800a2a0
|
|
8008a18: 3ff00000 .word 0x3ff00000
|
|
8008a1c: 40240000 .word 0x40240000
|
|
8008a20: 401c0000 .word 0x401c0000
|
|
8008a24: 40140000 .word 0x40140000
|
|
8008a28: 3fe00000 .word 0x3fe00000
|
|
8008a2c: 4631 mov r1, r6
|
|
8008a2e: 4628 mov r0, r5
|
|
8008a30: f7f7 fde2 bl 80005f8 <__aeabi_dmul>
|
|
8008a34: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8008a38: 9413 str r4, [sp, #76] @ 0x4c
|
|
8008a3a: 4656 mov r6, sl
|
|
8008a3c: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8008a40: f7f8 f88a bl 8000b58 <__aeabi_d2iz>
|
|
8008a44: 4605 mov r5, r0
|
|
8008a46: f7f7 fd6d bl 8000524 <__aeabi_i2d>
|
|
8008a4a: 4602 mov r2, r0
|
|
8008a4c: 460b mov r3, r1
|
|
8008a4e: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8008a52: f7f7 fc19 bl 8000288 <__aeabi_dsub>
|
|
8008a56: 3530 adds r5, #48 @ 0x30
|
|
8008a58: f806 5b01 strb.w r5, [r6], #1
|
|
8008a5c: 4602 mov r2, r0
|
|
8008a5e: 460b mov r3, r1
|
|
8008a60: 42a6 cmp r6, r4
|
|
8008a62: e9cd 2304 strd r2, r3, [sp, #16]
|
|
8008a66: f04f 0200 mov.w r2, #0
|
|
8008a6a: d124 bne.n 8008ab6 <_dtoa_r+0x626>
|
|
8008a6c: 4baf ldr r3, [pc, #700] @ (8008d2c <_dtoa_r+0x89c>)
|
|
8008a6e: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8008a72: f7f7 fc0b bl 800028c <__adddf3>
|
|
8008a76: 4602 mov r2, r0
|
|
8008a78: 460b mov r3, r1
|
|
8008a7a: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8008a7e: f7f8 f84b bl 8000b18 <__aeabi_dcmpgt>
|
|
8008a82: 2800 cmp r0, #0
|
|
8008a84: d163 bne.n 8008b4e <_dtoa_r+0x6be>
|
|
8008a86: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8008a8a: 49a8 ldr r1, [pc, #672] @ (8008d2c <_dtoa_r+0x89c>)
|
|
8008a8c: 2000 movs r0, #0
|
|
8008a8e: f7f7 fbfb bl 8000288 <__aeabi_dsub>
|
|
8008a92: 4602 mov r2, r0
|
|
8008a94: 460b mov r3, r1
|
|
8008a96: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8008a9a: f7f8 f81f bl 8000adc <__aeabi_dcmplt>
|
|
8008a9e: 2800 cmp r0, #0
|
|
8008aa0: f43f af14 beq.w 80088cc <_dtoa_r+0x43c>
|
|
8008aa4: 9e13 ldr r6, [sp, #76] @ 0x4c
|
|
8008aa6: 1e73 subs r3, r6, #1
|
|
8008aa8: 9313 str r3, [sp, #76] @ 0x4c
|
|
8008aaa: f816 3c01 ldrb.w r3, [r6, #-1]
|
|
8008aae: 2b30 cmp r3, #48 @ 0x30
|
|
8008ab0: d0f8 beq.n 8008aa4 <_dtoa_r+0x614>
|
|
8008ab2: 4647 mov r7, r8
|
|
8008ab4: e03b b.n 8008b2e <_dtoa_r+0x69e>
|
|
8008ab6: 4b9e ldr r3, [pc, #632] @ (8008d30 <_dtoa_r+0x8a0>)
|
|
8008ab8: f7f7 fd9e bl 80005f8 <__aeabi_dmul>
|
|
8008abc: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8008ac0: e7bc b.n 8008a3c <_dtoa_r+0x5ac>
|
|
8008ac2: e9dd 4504 ldrd r4, r5, [sp, #16]
|
|
8008ac6: 4656 mov r6, sl
|
|
8008ac8: e9dd 2300 ldrd r2, r3, [sp]
|
|
8008acc: 4620 mov r0, r4
|
|
8008ace: 4629 mov r1, r5
|
|
8008ad0: f7f7 febc bl 800084c <__aeabi_ddiv>
|
|
8008ad4: f7f8 f840 bl 8000b58 <__aeabi_d2iz>
|
|
8008ad8: 4680 mov r8, r0
|
|
8008ada: f7f7 fd23 bl 8000524 <__aeabi_i2d>
|
|
8008ade: e9dd 2300 ldrd r2, r3, [sp]
|
|
8008ae2: f7f7 fd89 bl 80005f8 <__aeabi_dmul>
|
|
8008ae6: 4602 mov r2, r0
|
|
8008ae8: 460b mov r3, r1
|
|
8008aea: 4620 mov r0, r4
|
|
8008aec: 4629 mov r1, r5
|
|
8008aee: f108 0430 add.w r4, r8, #48 @ 0x30
|
|
8008af2: f7f7 fbc9 bl 8000288 <__aeabi_dsub>
|
|
8008af6: f806 4b01 strb.w r4, [r6], #1
|
|
8008afa: 9d03 ldr r5, [sp, #12]
|
|
8008afc: eba6 040a sub.w r4, r6, sl
|
|
8008b00: 42a5 cmp r5, r4
|
|
8008b02: 4602 mov r2, r0
|
|
8008b04: 460b mov r3, r1
|
|
8008b06: d133 bne.n 8008b70 <_dtoa_r+0x6e0>
|
|
8008b08: f7f7 fbc0 bl 800028c <__adddf3>
|
|
8008b0c: e9dd 2300 ldrd r2, r3, [sp]
|
|
8008b10: 4604 mov r4, r0
|
|
8008b12: 460d mov r5, r1
|
|
8008b14: f7f8 f800 bl 8000b18 <__aeabi_dcmpgt>
|
|
8008b18: b9c0 cbnz r0, 8008b4c <_dtoa_r+0x6bc>
|
|
8008b1a: e9dd 2300 ldrd r2, r3, [sp]
|
|
8008b1e: 4620 mov r0, r4
|
|
8008b20: 4629 mov r1, r5
|
|
8008b22: f7f7 ffd1 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8008b26: b110 cbz r0, 8008b2e <_dtoa_r+0x69e>
|
|
8008b28: f018 0f01 tst.w r8, #1
|
|
8008b2c: d10e bne.n 8008b4c <_dtoa_r+0x6bc>
|
|
8008b2e: 9902 ldr r1, [sp, #8]
|
|
8008b30: 4648 mov r0, r9
|
|
8008b32: f000 fbbd bl 80092b0 <_Bfree>
|
|
8008b36: 2300 movs r3, #0
|
|
8008b38: 7033 strb r3, [r6, #0]
|
|
8008b3a: 9b11 ldr r3, [sp, #68] @ 0x44
|
|
8008b3c: 3701 adds r7, #1
|
|
8008b3e: 601f str r7, [r3, #0]
|
|
8008b40: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8008b42: 2b00 cmp r3, #0
|
|
8008b44: f000 824b beq.w 8008fde <_dtoa_r+0xb4e>
|
|
8008b48: 601e str r6, [r3, #0]
|
|
8008b4a: e248 b.n 8008fde <_dtoa_r+0xb4e>
|
|
8008b4c: 46b8 mov r8, r7
|
|
8008b4e: 4633 mov r3, r6
|
|
8008b50: 461e mov r6, r3
|
|
8008b52: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
8008b56: 2a39 cmp r2, #57 @ 0x39
|
|
8008b58: d106 bne.n 8008b68 <_dtoa_r+0x6d8>
|
|
8008b5a: 459a cmp sl, r3
|
|
8008b5c: d1f8 bne.n 8008b50 <_dtoa_r+0x6c0>
|
|
8008b5e: 2230 movs r2, #48 @ 0x30
|
|
8008b60: f108 0801 add.w r8, r8, #1
|
|
8008b64: f88a 2000 strb.w r2, [sl]
|
|
8008b68: 781a ldrb r2, [r3, #0]
|
|
8008b6a: 3201 adds r2, #1
|
|
8008b6c: 701a strb r2, [r3, #0]
|
|
8008b6e: e7a0 b.n 8008ab2 <_dtoa_r+0x622>
|
|
8008b70: 4b6f ldr r3, [pc, #444] @ (8008d30 <_dtoa_r+0x8a0>)
|
|
8008b72: 2200 movs r2, #0
|
|
8008b74: f7f7 fd40 bl 80005f8 <__aeabi_dmul>
|
|
8008b78: 2200 movs r2, #0
|
|
8008b7a: 2300 movs r3, #0
|
|
8008b7c: 4604 mov r4, r0
|
|
8008b7e: 460d mov r5, r1
|
|
8008b80: f7f7 ffa2 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8008b84: 2800 cmp r0, #0
|
|
8008b86: d09f beq.n 8008ac8 <_dtoa_r+0x638>
|
|
8008b88: e7d1 b.n 8008b2e <_dtoa_r+0x69e>
|
|
8008b8a: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8008b8c: 2a00 cmp r2, #0
|
|
8008b8e: f000 80ea beq.w 8008d66 <_dtoa_r+0x8d6>
|
|
8008b92: 9a07 ldr r2, [sp, #28]
|
|
8008b94: 2a01 cmp r2, #1
|
|
8008b96: f300 80cd bgt.w 8008d34 <_dtoa_r+0x8a4>
|
|
8008b9a: 9a12 ldr r2, [sp, #72] @ 0x48
|
|
8008b9c: 2a00 cmp r2, #0
|
|
8008b9e: f000 80c1 beq.w 8008d24 <_dtoa_r+0x894>
|
|
8008ba2: f203 4333 addw r3, r3, #1075 @ 0x433
|
|
8008ba6: 9c08 ldr r4, [sp, #32]
|
|
8008ba8: 9e00 ldr r6, [sp, #0]
|
|
8008baa: 9a00 ldr r2, [sp, #0]
|
|
8008bac: 441a add r2, r3
|
|
8008bae: 9200 str r2, [sp, #0]
|
|
8008bb0: 9a06 ldr r2, [sp, #24]
|
|
8008bb2: 2101 movs r1, #1
|
|
8008bb4: 441a add r2, r3
|
|
8008bb6: 4648 mov r0, r9
|
|
8008bb8: 9206 str r2, [sp, #24]
|
|
8008bba: f000 fc2d bl 8009418 <__i2b>
|
|
8008bbe: 4605 mov r5, r0
|
|
8008bc0: b166 cbz r6, 8008bdc <_dtoa_r+0x74c>
|
|
8008bc2: 9b06 ldr r3, [sp, #24]
|
|
8008bc4: 2b00 cmp r3, #0
|
|
8008bc6: dd09 ble.n 8008bdc <_dtoa_r+0x74c>
|
|
8008bc8: 42b3 cmp r3, r6
|
|
8008bca: 9a00 ldr r2, [sp, #0]
|
|
8008bcc: bfa8 it ge
|
|
8008bce: 4633 movge r3, r6
|
|
8008bd0: 1ad2 subs r2, r2, r3
|
|
8008bd2: 9200 str r2, [sp, #0]
|
|
8008bd4: 9a06 ldr r2, [sp, #24]
|
|
8008bd6: 1af6 subs r6, r6, r3
|
|
8008bd8: 1ad3 subs r3, r2, r3
|
|
8008bda: 9306 str r3, [sp, #24]
|
|
8008bdc: 9b08 ldr r3, [sp, #32]
|
|
8008bde: b30b cbz r3, 8008c24 <_dtoa_r+0x794>
|
|
8008be0: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8008be2: 2b00 cmp r3, #0
|
|
8008be4: f000 80c6 beq.w 8008d74 <_dtoa_r+0x8e4>
|
|
8008be8: 2c00 cmp r4, #0
|
|
8008bea: f000 80c0 beq.w 8008d6e <_dtoa_r+0x8de>
|
|
8008bee: 4629 mov r1, r5
|
|
8008bf0: 4622 mov r2, r4
|
|
8008bf2: 4648 mov r0, r9
|
|
8008bf4: f000 fcc8 bl 8009588 <__pow5mult>
|
|
8008bf8: 9a02 ldr r2, [sp, #8]
|
|
8008bfa: 4601 mov r1, r0
|
|
8008bfc: 4605 mov r5, r0
|
|
8008bfe: 4648 mov r0, r9
|
|
8008c00: f000 fc20 bl 8009444 <__multiply>
|
|
8008c04: 9902 ldr r1, [sp, #8]
|
|
8008c06: 4680 mov r8, r0
|
|
8008c08: 4648 mov r0, r9
|
|
8008c0a: f000 fb51 bl 80092b0 <_Bfree>
|
|
8008c0e: 9b08 ldr r3, [sp, #32]
|
|
8008c10: 1b1b subs r3, r3, r4
|
|
8008c12: 9308 str r3, [sp, #32]
|
|
8008c14: f000 80b1 beq.w 8008d7a <_dtoa_r+0x8ea>
|
|
8008c18: 9a08 ldr r2, [sp, #32]
|
|
8008c1a: 4641 mov r1, r8
|
|
8008c1c: 4648 mov r0, r9
|
|
8008c1e: f000 fcb3 bl 8009588 <__pow5mult>
|
|
8008c22: 9002 str r0, [sp, #8]
|
|
8008c24: 2101 movs r1, #1
|
|
8008c26: 4648 mov r0, r9
|
|
8008c28: f000 fbf6 bl 8009418 <__i2b>
|
|
8008c2c: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8008c2e: 4604 mov r4, r0
|
|
8008c30: 2b00 cmp r3, #0
|
|
8008c32: f000 81d8 beq.w 8008fe6 <_dtoa_r+0xb56>
|
|
8008c36: 461a mov r2, r3
|
|
8008c38: 4601 mov r1, r0
|
|
8008c3a: 4648 mov r0, r9
|
|
8008c3c: f000 fca4 bl 8009588 <__pow5mult>
|
|
8008c40: 9b07 ldr r3, [sp, #28]
|
|
8008c42: 2b01 cmp r3, #1
|
|
8008c44: 4604 mov r4, r0
|
|
8008c46: f300 809f bgt.w 8008d88 <_dtoa_r+0x8f8>
|
|
8008c4a: 9b04 ldr r3, [sp, #16]
|
|
8008c4c: 2b00 cmp r3, #0
|
|
8008c4e: f040 8097 bne.w 8008d80 <_dtoa_r+0x8f0>
|
|
8008c52: 9b05 ldr r3, [sp, #20]
|
|
8008c54: f3c3 0313 ubfx r3, r3, #0, #20
|
|
8008c58: 2b00 cmp r3, #0
|
|
8008c5a: f040 8093 bne.w 8008d84 <_dtoa_r+0x8f4>
|
|
8008c5e: 9b05 ldr r3, [sp, #20]
|
|
8008c60: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8008c64: 0d1b lsrs r3, r3, #20
|
|
8008c66: 051b lsls r3, r3, #20
|
|
8008c68: b133 cbz r3, 8008c78 <_dtoa_r+0x7e8>
|
|
8008c6a: 9b00 ldr r3, [sp, #0]
|
|
8008c6c: 3301 adds r3, #1
|
|
8008c6e: 9300 str r3, [sp, #0]
|
|
8008c70: 9b06 ldr r3, [sp, #24]
|
|
8008c72: 3301 adds r3, #1
|
|
8008c74: 9306 str r3, [sp, #24]
|
|
8008c76: 2301 movs r3, #1
|
|
8008c78: 9308 str r3, [sp, #32]
|
|
8008c7a: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8008c7c: 2b00 cmp r3, #0
|
|
8008c7e: f000 81b8 beq.w 8008ff2 <_dtoa_r+0xb62>
|
|
8008c82: 6923 ldr r3, [r4, #16]
|
|
8008c84: eb04 0383 add.w r3, r4, r3, lsl #2
|
|
8008c88: 6918 ldr r0, [r3, #16]
|
|
8008c8a: f000 fb79 bl 8009380 <__hi0bits>
|
|
8008c8e: f1c0 0020 rsb r0, r0, #32
|
|
8008c92: 9b06 ldr r3, [sp, #24]
|
|
8008c94: 4418 add r0, r3
|
|
8008c96: f010 001f ands.w r0, r0, #31
|
|
8008c9a: f000 8082 beq.w 8008da2 <_dtoa_r+0x912>
|
|
8008c9e: f1c0 0320 rsb r3, r0, #32
|
|
8008ca2: 2b04 cmp r3, #4
|
|
8008ca4: dd73 ble.n 8008d8e <_dtoa_r+0x8fe>
|
|
8008ca6: 9b00 ldr r3, [sp, #0]
|
|
8008ca8: f1c0 001c rsb r0, r0, #28
|
|
8008cac: 4403 add r3, r0
|
|
8008cae: 9300 str r3, [sp, #0]
|
|
8008cb0: 9b06 ldr r3, [sp, #24]
|
|
8008cb2: 4403 add r3, r0
|
|
8008cb4: 4406 add r6, r0
|
|
8008cb6: 9306 str r3, [sp, #24]
|
|
8008cb8: 9b00 ldr r3, [sp, #0]
|
|
8008cba: 2b00 cmp r3, #0
|
|
8008cbc: dd05 ble.n 8008cca <_dtoa_r+0x83a>
|
|
8008cbe: 9902 ldr r1, [sp, #8]
|
|
8008cc0: 461a mov r2, r3
|
|
8008cc2: 4648 mov r0, r9
|
|
8008cc4: f000 fcba bl 800963c <__lshift>
|
|
8008cc8: 9002 str r0, [sp, #8]
|
|
8008cca: 9b06 ldr r3, [sp, #24]
|
|
8008ccc: 2b00 cmp r3, #0
|
|
8008cce: dd05 ble.n 8008cdc <_dtoa_r+0x84c>
|
|
8008cd0: 4621 mov r1, r4
|
|
8008cd2: 461a mov r2, r3
|
|
8008cd4: 4648 mov r0, r9
|
|
8008cd6: f000 fcb1 bl 800963c <__lshift>
|
|
8008cda: 4604 mov r4, r0
|
|
8008cdc: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
8008cde: 2b00 cmp r3, #0
|
|
8008ce0: d061 beq.n 8008da6 <_dtoa_r+0x916>
|
|
8008ce2: 9802 ldr r0, [sp, #8]
|
|
8008ce4: 4621 mov r1, r4
|
|
8008ce6: f000 fd15 bl 8009714 <__mcmp>
|
|
8008cea: 2800 cmp r0, #0
|
|
8008cec: da5b bge.n 8008da6 <_dtoa_r+0x916>
|
|
8008cee: 2300 movs r3, #0
|
|
8008cf0: 9902 ldr r1, [sp, #8]
|
|
8008cf2: 220a movs r2, #10
|
|
8008cf4: 4648 mov r0, r9
|
|
8008cf6: f000 fafd bl 80092f4 <__multadd>
|
|
8008cfa: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8008cfc: 9002 str r0, [sp, #8]
|
|
8008cfe: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
|
|
8008d02: 2b00 cmp r3, #0
|
|
8008d04: f000 8177 beq.w 8008ff6 <_dtoa_r+0xb66>
|
|
8008d08: 4629 mov r1, r5
|
|
8008d0a: 2300 movs r3, #0
|
|
8008d0c: 220a movs r2, #10
|
|
8008d0e: 4648 mov r0, r9
|
|
8008d10: f000 faf0 bl 80092f4 <__multadd>
|
|
8008d14: f1bb 0f00 cmp.w fp, #0
|
|
8008d18: 4605 mov r5, r0
|
|
8008d1a: dc6f bgt.n 8008dfc <_dtoa_r+0x96c>
|
|
8008d1c: 9b07 ldr r3, [sp, #28]
|
|
8008d1e: 2b02 cmp r3, #2
|
|
8008d20: dc49 bgt.n 8008db6 <_dtoa_r+0x926>
|
|
8008d22: e06b b.n 8008dfc <_dtoa_r+0x96c>
|
|
8008d24: 9b14 ldr r3, [sp, #80] @ 0x50
|
|
8008d26: f1c3 0336 rsb r3, r3, #54 @ 0x36
|
|
8008d2a: e73c b.n 8008ba6 <_dtoa_r+0x716>
|
|
8008d2c: 3fe00000 .word 0x3fe00000
|
|
8008d30: 40240000 .word 0x40240000
|
|
8008d34: 9b03 ldr r3, [sp, #12]
|
|
8008d36: 1e5c subs r4, r3, #1
|
|
8008d38: 9b08 ldr r3, [sp, #32]
|
|
8008d3a: 42a3 cmp r3, r4
|
|
8008d3c: db09 blt.n 8008d52 <_dtoa_r+0x8c2>
|
|
8008d3e: 1b1c subs r4, r3, r4
|
|
8008d40: 9b03 ldr r3, [sp, #12]
|
|
8008d42: 2b00 cmp r3, #0
|
|
8008d44: f6bf af30 bge.w 8008ba8 <_dtoa_r+0x718>
|
|
8008d48: 9b00 ldr r3, [sp, #0]
|
|
8008d4a: 9a03 ldr r2, [sp, #12]
|
|
8008d4c: 1a9e subs r6, r3, r2
|
|
8008d4e: 2300 movs r3, #0
|
|
8008d50: e72b b.n 8008baa <_dtoa_r+0x71a>
|
|
8008d52: 9b08 ldr r3, [sp, #32]
|
|
8008d54: 9a0d ldr r2, [sp, #52] @ 0x34
|
|
8008d56: 9408 str r4, [sp, #32]
|
|
8008d58: 1ae3 subs r3, r4, r3
|
|
8008d5a: 441a add r2, r3
|
|
8008d5c: 9e00 ldr r6, [sp, #0]
|
|
8008d5e: 9b03 ldr r3, [sp, #12]
|
|
8008d60: 920d str r2, [sp, #52] @ 0x34
|
|
8008d62: 2400 movs r4, #0
|
|
8008d64: e721 b.n 8008baa <_dtoa_r+0x71a>
|
|
8008d66: 9c08 ldr r4, [sp, #32]
|
|
8008d68: 9e00 ldr r6, [sp, #0]
|
|
8008d6a: 9d09 ldr r5, [sp, #36] @ 0x24
|
|
8008d6c: e728 b.n 8008bc0 <_dtoa_r+0x730>
|
|
8008d6e: f8dd 8008 ldr.w r8, [sp, #8]
|
|
8008d72: e751 b.n 8008c18 <_dtoa_r+0x788>
|
|
8008d74: 9a08 ldr r2, [sp, #32]
|
|
8008d76: 9902 ldr r1, [sp, #8]
|
|
8008d78: e750 b.n 8008c1c <_dtoa_r+0x78c>
|
|
8008d7a: f8cd 8008 str.w r8, [sp, #8]
|
|
8008d7e: e751 b.n 8008c24 <_dtoa_r+0x794>
|
|
8008d80: 2300 movs r3, #0
|
|
8008d82: e779 b.n 8008c78 <_dtoa_r+0x7e8>
|
|
8008d84: 9b04 ldr r3, [sp, #16]
|
|
8008d86: e777 b.n 8008c78 <_dtoa_r+0x7e8>
|
|
8008d88: 2300 movs r3, #0
|
|
8008d8a: 9308 str r3, [sp, #32]
|
|
8008d8c: e779 b.n 8008c82 <_dtoa_r+0x7f2>
|
|
8008d8e: d093 beq.n 8008cb8 <_dtoa_r+0x828>
|
|
8008d90: 9a00 ldr r2, [sp, #0]
|
|
8008d92: 331c adds r3, #28
|
|
8008d94: 441a add r2, r3
|
|
8008d96: 9200 str r2, [sp, #0]
|
|
8008d98: 9a06 ldr r2, [sp, #24]
|
|
8008d9a: 441a add r2, r3
|
|
8008d9c: 441e add r6, r3
|
|
8008d9e: 9206 str r2, [sp, #24]
|
|
8008da0: e78a b.n 8008cb8 <_dtoa_r+0x828>
|
|
8008da2: 4603 mov r3, r0
|
|
8008da4: e7f4 b.n 8008d90 <_dtoa_r+0x900>
|
|
8008da6: 9b03 ldr r3, [sp, #12]
|
|
8008da8: 2b00 cmp r3, #0
|
|
8008daa: 46b8 mov r8, r7
|
|
8008dac: dc20 bgt.n 8008df0 <_dtoa_r+0x960>
|
|
8008dae: 469b mov fp, r3
|
|
8008db0: 9b07 ldr r3, [sp, #28]
|
|
8008db2: 2b02 cmp r3, #2
|
|
8008db4: dd1e ble.n 8008df4 <_dtoa_r+0x964>
|
|
8008db6: f1bb 0f00 cmp.w fp, #0
|
|
8008dba: f47f adb1 bne.w 8008920 <_dtoa_r+0x490>
|
|
8008dbe: 4621 mov r1, r4
|
|
8008dc0: 465b mov r3, fp
|
|
8008dc2: 2205 movs r2, #5
|
|
8008dc4: 4648 mov r0, r9
|
|
8008dc6: f000 fa95 bl 80092f4 <__multadd>
|
|
8008dca: 4601 mov r1, r0
|
|
8008dcc: 4604 mov r4, r0
|
|
8008dce: 9802 ldr r0, [sp, #8]
|
|
8008dd0: f000 fca0 bl 8009714 <__mcmp>
|
|
8008dd4: 2800 cmp r0, #0
|
|
8008dd6: f77f ada3 ble.w 8008920 <_dtoa_r+0x490>
|
|
8008dda: 4656 mov r6, sl
|
|
8008ddc: 2331 movs r3, #49 @ 0x31
|
|
8008dde: f806 3b01 strb.w r3, [r6], #1
|
|
8008de2: f108 0801 add.w r8, r8, #1
|
|
8008de6: e59f b.n 8008928 <_dtoa_r+0x498>
|
|
8008de8: 9c03 ldr r4, [sp, #12]
|
|
8008dea: 46b8 mov r8, r7
|
|
8008dec: 4625 mov r5, r4
|
|
8008dee: e7f4 b.n 8008dda <_dtoa_r+0x94a>
|
|
8008df0: f8dd b00c ldr.w fp, [sp, #12]
|
|
8008df4: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8008df6: 2b00 cmp r3, #0
|
|
8008df8: f000 8101 beq.w 8008ffe <_dtoa_r+0xb6e>
|
|
8008dfc: 2e00 cmp r6, #0
|
|
8008dfe: dd05 ble.n 8008e0c <_dtoa_r+0x97c>
|
|
8008e00: 4629 mov r1, r5
|
|
8008e02: 4632 mov r2, r6
|
|
8008e04: 4648 mov r0, r9
|
|
8008e06: f000 fc19 bl 800963c <__lshift>
|
|
8008e0a: 4605 mov r5, r0
|
|
8008e0c: 9b08 ldr r3, [sp, #32]
|
|
8008e0e: 2b00 cmp r3, #0
|
|
8008e10: d05c beq.n 8008ecc <_dtoa_r+0xa3c>
|
|
8008e12: 6869 ldr r1, [r5, #4]
|
|
8008e14: 4648 mov r0, r9
|
|
8008e16: f000 fa0b bl 8009230 <_Balloc>
|
|
8008e1a: 4606 mov r6, r0
|
|
8008e1c: b928 cbnz r0, 8008e2a <_dtoa_r+0x99a>
|
|
8008e1e: 4b82 ldr r3, [pc, #520] @ (8009028 <_dtoa_r+0xb98>)
|
|
8008e20: 4602 mov r2, r0
|
|
8008e22: f240 21ef movw r1, #751 @ 0x2ef
|
|
8008e26: f7ff bb4a b.w 80084be <_dtoa_r+0x2e>
|
|
8008e2a: 692a ldr r2, [r5, #16]
|
|
8008e2c: 3202 adds r2, #2
|
|
8008e2e: 0092 lsls r2, r2, #2
|
|
8008e30: f105 010c add.w r1, r5, #12
|
|
8008e34: 300c adds r0, #12
|
|
8008e36: f7ff fa92 bl 800835e <memcpy>
|
|
8008e3a: 2201 movs r2, #1
|
|
8008e3c: 4631 mov r1, r6
|
|
8008e3e: 4648 mov r0, r9
|
|
8008e40: f000 fbfc bl 800963c <__lshift>
|
|
8008e44: f10a 0301 add.w r3, sl, #1
|
|
8008e48: 9300 str r3, [sp, #0]
|
|
8008e4a: eb0a 030b add.w r3, sl, fp
|
|
8008e4e: 9308 str r3, [sp, #32]
|
|
8008e50: 9b04 ldr r3, [sp, #16]
|
|
8008e52: f003 0301 and.w r3, r3, #1
|
|
8008e56: 462f mov r7, r5
|
|
8008e58: 9306 str r3, [sp, #24]
|
|
8008e5a: 4605 mov r5, r0
|
|
8008e5c: 9b00 ldr r3, [sp, #0]
|
|
8008e5e: 9802 ldr r0, [sp, #8]
|
|
8008e60: 4621 mov r1, r4
|
|
8008e62: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff
|
|
8008e66: f7ff fa88 bl 800837a <quorem>
|
|
8008e6a: 4603 mov r3, r0
|
|
8008e6c: 3330 adds r3, #48 @ 0x30
|
|
8008e6e: 9003 str r0, [sp, #12]
|
|
8008e70: 4639 mov r1, r7
|
|
8008e72: 9802 ldr r0, [sp, #8]
|
|
8008e74: 9309 str r3, [sp, #36] @ 0x24
|
|
8008e76: f000 fc4d bl 8009714 <__mcmp>
|
|
8008e7a: 462a mov r2, r5
|
|
8008e7c: 9004 str r0, [sp, #16]
|
|
8008e7e: 4621 mov r1, r4
|
|
8008e80: 4648 mov r0, r9
|
|
8008e82: f000 fc63 bl 800974c <__mdiff>
|
|
8008e86: 68c2 ldr r2, [r0, #12]
|
|
8008e88: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8008e8a: 4606 mov r6, r0
|
|
8008e8c: bb02 cbnz r2, 8008ed0 <_dtoa_r+0xa40>
|
|
8008e8e: 4601 mov r1, r0
|
|
8008e90: 9802 ldr r0, [sp, #8]
|
|
8008e92: f000 fc3f bl 8009714 <__mcmp>
|
|
8008e96: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8008e98: 4602 mov r2, r0
|
|
8008e9a: 4631 mov r1, r6
|
|
8008e9c: 4648 mov r0, r9
|
|
8008e9e: 920c str r2, [sp, #48] @ 0x30
|
|
8008ea0: 9309 str r3, [sp, #36] @ 0x24
|
|
8008ea2: f000 fa05 bl 80092b0 <_Bfree>
|
|
8008ea6: 9b07 ldr r3, [sp, #28]
|
|
8008ea8: 9a0c ldr r2, [sp, #48] @ 0x30
|
|
8008eaa: 9e00 ldr r6, [sp, #0]
|
|
8008eac: ea42 0103 orr.w r1, r2, r3
|
|
8008eb0: 9b06 ldr r3, [sp, #24]
|
|
8008eb2: 4319 orrs r1, r3
|
|
8008eb4: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8008eb6: d10d bne.n 8008ed4 <_dtoa_r+0xa44>
|
|
8008eb8: 2b39 cmp r3, #57 @ 0x39
|
|
8008eba: d027 beq.n 8008f0c <_dtoa_r+0xa7c>
|
|
8008ebc: 9a04 ldr r2, [sp, #16]
|
|
8008ebe: 2a00 cmp r2, #0
|
|
8008ec0: dd01 ble.n 8008ec6 <_dtoa_r+0xa36>
|
|
8008ec2: 9b03 ldr r3, [sp, #12]
|
|
8008ec4: 3331 adds r3, #49 @ 0x31
|
|
8008ec6: f88b 3000 strb.w r3, [fp]
|
|
8008eca: e52e b.n 800892a <_dtoa_r+0x49a>
|
|
8008ecc: 4628 mov r0, r5
|
|
8008ece: e7b9 b.n 8008e44 <_dtoa_r+0x9b4>
|
|
8008ed0: 2201 movs r2, #1
|
|
8008ed2: e7e2 b.n 8008e9a <_dtoa_r+0xa0a>
|
|
8008ed4: 9904 ldr r1, [sp, #16]
|
|
8008ed6: 2900 cmp r1, #0
|
|
8008ed8: db04 blt.n 8008ee4 <_dtoa_r+0xa54>
|
|
8008eda: 9807 ldr r0, [sp, #28]
|
|
8008edc: 4301 orrs r1, r0
|
|
8008ede: 9806 ldr r0, [sp, #24]
|
|
8008ee0: 4301 orrs r1, r0
|
|
8008ee2: d120 bne.n 8008f26 <_dtoa_r+0xa96>
|
|
8008ee4: 2a00 cmp r2, #0
|
|
8008ee6: ddee ble.n 8008ec6 <_dtoa_r+0xa36>
|
|
8008ee8: 9902 ldr r1, [sp, #8]
|
|
8008eea: 9300 str r3, [sp, #0]
|
|
8008eec: 2201 movs r2, #1
|
|
8008eee: 4648 mov r0, r9
|
|
8008ef0: f000 fba4 bl 800963c <__lshift>
|
|
8008ef4: 4621 mov r1, r4
|
|
8008ef6: 9002 str r0, [sp, #8]
|
|
8008ef8: f000 fc0c bl 8009714 <__mcmp>
|
|
8008efc: 2800 cmp r0, #0
|
|
8008efe: 9b00 ldr r3, [sp, #0]
|
|
8008f00: dc02 bgt.n 8008f08 <_dtoa_r+0xa78>
|
|
8008f02: d1e0 bne.n 8008ec6 <_dtoa_r+0xa36>
|
|
8008f04: 07da lsls r2, r3, #31
|
|
8008f06: d5de bpl.n 8008ec6 <_dtoa_r+0xa36>
|
|
8008f08: 2b39 cmp r3, #57 @ 0x39
|
|
8008f0a: d1da bne.n 8008ec2 <_dtoa_r+0xa32>
|
|
8008f0c: 2339 movs r3, #57 @ 0x39
|
|
8008f0e: f88b 3000 strb.w r3, [fp]
|
|
8008f12: 4633 mov r3, r6
|
|
8008f14: 461e mov r6, r3
|
|
8008f16: 3b01 subs r3, #1
|
|
8008f18: f816 2c01 ldrb.w r2, [r6, #-1]
|
|
8008f1c: 2a39 cmp r2, #57 @ 0x39
|
|
8008f1e: d04e beq.n 8008fbe <_dtoa_r+0xb2e>
|
|
8008f20: 3201 adds r2, #1
|
|
8008f22: 701a strb r2, [r3, #0]
|
|
8008f24: e501 b.n 800892a <_dtoa_r+0x49a>
|
|
8008f26: 2a00 cmp r2, #0
|
|
8008f28: dd03 ble.n 8008f32 <_dtoa_r+0xaa2>
|
|
8008f2a: 2b39 cmp r3, #57 @ 0x39
|
|
8008f2c: d0ee beq.n 8008f0c <_dtoa_r+0xa7c>
|
|
8008f2e: 3301 adds r3, #1
|
|
8008f30: e7c9 b.n 8008ec6 <_dtoa_r+0xa36>
|
|
8008f32: 9a00 ldr r2, [sp, #0]
|
|
8008f34: 9908 ldr r1, [sp, #32]
|
|
8008f36: f802 3c01 strb.w r3, [r2, #-1]
|
|
8008f3a: 428a cmp r2, r1
|
|
8008f3c: d028 beq.n 8008f90 <_dtoa_r+0xb00>
|
|
8008f3e: 9902 ldr r1, [sp, #8]
|
|
8008f40: 2300 movs r3, #0
|
|
8008f42: 220a movs r2, #10
|
|
8008f44: 4648 mov r0, r9
|
|
8008f46: f000 f9d5 bl 80092f4 <__multadd>
|
|
8008f4a: 42af cmp r7, r5
|
|
8008f4c: 9002 str r0, [sp, #8]
|
|
8008f4e: f04f 0300 mov.w r3, #0
|
|
8008f52: f04f 020a mov.w r2, #10
|
|
8008f56: 4639 mov r1, r7
|
|
8008f58: 4648 mov r0, r9
|
|
8008f5a: d107 bne.n 8008f6c <_dtoa_r+0xadc>
|
|
8008f5c: f000 f9ca bl 80092f4 <__multadd>
|
|
8008f60: 4607 mov r7, r0
|
|
8008f62: 4605 mov r5, r0
|
|
8008f64: 9b00 ldr r3, [sp, #0]
|
|
8008f66: 3301 adds r3, #1
|
|
8008f68: 9300 str r3, [sp, #0]
|
|
8008f6a: e777 b.n 8008e5c <_dtoa_r+0x9cc>
|
|
8008f6c: f000 f9c2 bl 80092f4 <__multadd>
|
|
8008f70: 4629 mov r1, r5
|
|
8008f72: 4607 mov r7, r0
|
|
8008f74: 2300 movs r3, #0
|
|
8008f76: 220a movs r2, #10
|
|
8008f78: 4648 mov r0, r9
|
|
8008f7a: f000 f9bb bl 80092f4 <__multadd>
|
|
8008f7e: 4605 mov r5, r0
|
|
8008f80: e7f0 b.n 8008f64 <_dtoa_r+0xad4>
|
|
8008f82: f1bb 0f00 cmp.w fp, #0
|
|
8008f86: bfcc ite gt
|
|
8008f88: 465e movgt r6, fp
|
|
8008f8a: 2601 movle r6, #1
|
|
8008f8c: 4456 add r6, sl
|
|
8008f8e: 2700 movs r7, #0
|
|
8008f90: 9902 ldr r1, [sp, #8]
|
|
8008f92: 9300 str r3, [sp, #0]
|
|
8008f94: 2201 movs r2, #1
|
|
8008f96: 4648 mov r0, r9
|
|
8008f98: f000 fb50 bl 800963c <__lshift>
|
|
8008f9c: 4621 mov r1, r4
|
|
8008f9e: 9002 str r0, [sp, #8]
|
|
8008fa0: f000 fbb8 bl 8009714 <__mcmp>
|
|
8008fa4: 2800 cmp r0, #0
|
|
8008fa6: dcb4 bgt.n 8008f12 <_dtoa_r+0xa82>
|
|
8008fa8: d102 bne.n 8008fb0 <_dtoa_r+0xb20>
|
|
8008faa: 9b00 ldr r3, [sp, #0]
|
|
8008fac: 07db lsls r3, r3, #31
|
|
8008fae: d4b0 bmi.n 8008f12 <_dtoa_r+0xa82>
|
|
8008fb0: 4633 mov r3, r6
|
|
8008fb2: 461e mov r6, r3
|
|
8008fb4: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
8008fb8: 2a30 cmp r2, #48 @ 0x30
|
|
8008fba: d0fa beq.n 8008fb2 <_dtoa_r+0xb22>
|
|
8008fbc: e4b5 b.n 800892a <_dtoa_r+0x49a>
|
|
8008fbe: 459a cmp sl, r3
|
|
8008fc0: d1a8 bne.n 8008f14 <_dtoa_r+0xa84>
|
|
8008fc2: 2331 movs r3, #49 @ 0x31
|
|
8008fc4: f108 0801 add.w r8, r8, #1
|
|
8008fc8: f88a 3000 strb.w r3, [sl]
|
|
8008fcc: e4ad b.n 800892a <_dtoa_r+0x49a>
|
|
8008fce: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8008fd0: f8df a058 ldr.w sl, [pc, #88] @ 800902c <_dtoa_r+0xb9c>
|
|
8008fd4: b11b cbz r3, 8008fde <_dtoa_r+0xb4e>
|
|
8008fd6: f10a 0308 add.w r3, sl, #8
|
|
8008fda: 9a21 ldr r2, [sp, #132] @ 0x84
|
|
8008fdc: 6013 str r3, [r2, #0]
|
|
8008fde: 4650 mov r0, sl
|
|
8008fe0: b017 add sp, #92 @ 0x5c
|
|
8008fe2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8008fe6: 9b07 ldr r3, [sp, #28]
|
|
8008fe8: 2b01 cmp r3, #1
|
|
8008fea: f77f ae2e ble.w 8008c4a <_dtoa_r+0x7ba>
|
|
8008fee: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8008ff0: 9308 str r3, [sp, #32]
|
|
8008ff2: 2001 movs r0, #1
|
|
8008ff4: e64d b.n 8008c92 <_dtoa_r+0x802>
|
|
8008ff6: f1bb 0f00 cmp.w fp, #0
|
|
8008ffa: f77f aed9 ble.w 8008db0 <_dtoa_r+0x920>
|
|
8008ffe: 4656 mov r6, sl
|
|
8009000: 9802 ldr r0, [sp, #8]
|
|
8009002: 4621 mov r1, r4
|
|
8009004: f7ff f9b9 bl 800837a <quorem>
|
|
8009008: f100 0330 add.w r3, r0, #48 @ 0x30
|
|
800900c: f806 3b01 strb.w r3, [r6], #1
|
|
8009010: eba6 020a sub.w r2, r6, sl
|
|
8009014: 4593 cmp fp, r2
|
|
8009016: ddb4 ble.n 8008f82 <_dtoa_r+0xaf2>
|
|
8009018: 9902 ldr r1, [sp, #8]
|
|
800901a: 2300 movs r3, #0
|
|
800901c: 220a movs r2, #10
|
|
800901e: 4648 mov r0, r9
|
|
8009020: f000 f968 bl 80092f4 <__multadd>
|
|
8009024: 9002 str r0, [sp, #8]
|
|
8009026: e7eb b.n 8009000 <_dtoa_r+0xb70>
|
|
8009028: 0800a1d0 .word 0x0800a1d0
|
|
800902c: 0800a154 .word 0x0800a154
|
|
|
|
08009030 <_free_r>:
|
|
8009030: b538 push {r3, r4, r5, lr}
|
|
8009032: 4605 mov r5, r0
|
|
8009034: 2900 cmp r1, #0
|
|
8009036: d041 beq.n 80090bc <_free_r+0x8c>
|
|
8009038: f851 3c04 ldr.w r3, [r1, #-4]
|
|
800903c: 1f0c subs r4, r1, #4
|
|
800903e: 2b00 cmp r3, #0
|
|
8009040: bfb8 it lt
|
|
8009042: 18e4 addlt r4, r4, r3
|
|
8009044: f000 f8e8 bl 8009218 <__malloc_lock>
|
|
8009048: 4a1d ldr r2, [pc, #116] @ (80090c0 <_free_r+0x90>)
|
|
800904a: 6813 ldr r3, [r2, #0]
|
|
800904c: b933 cbnz r3, 800905c <_free_r+0x2c>
|
|
800904e: 6063 str r3, [r4, #4]
|
|
8009050: 6014 str r4, [r2, #0]
|
|
8009052: 4628 mov r0, r5
|
|
8009054: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8009058: f000 b8e4 b.w 8009224 <__malloc_unlock>
|
|
800905c: 42a3 cmp r3, r4
|
|
800905e: d908 bls.n 8009072 <_free_r+0x42>
|
|
8009060: 6820 ldr r0, [r4, #0]
|
|
8009062: 1821 adds r1, r4, r0
|
|
8009064: 428b cmp r3, r1
|
|
8009066: bf01 itttt eq
|
|
8009068: 6819 ldreq r1, [r3, #0]
|
|
800906a: 685b ldreq r3, [r3, #4]
|
|
800906c: 1809 addeq r1, r1, r0
|
|
800906e: 6021 streq r1, [r4, #0]
|
|
8009070: e7ed b.n 800904e <_free_r+0x1e>
|
|
8009072: 461a mov r2, r3
|
|
8009074: 685b ldr r3, [r3, #4]
|
|
8009076: b10b cbz r3, 800907c <_free_r+0x4c>
|
|
8009078: 42a3 cmp r3, r4
|
|
800907a: d9fa bls.n 8009072 <_free_r+0x42>
|
|
800907c: 6811 ldr r1, [r2, #0]
|
|
800907e: 1850 adds r0, r2, r1
|
|
8009080: 42a0 cmp r0, r4
|
|
8009082: d10b bne.n 800909c <_free_r+0x6c>
|
|
8009084: 6820 ldr r0, [r4, #0]
|
|
8009086: 4401 add r1, r0
|
|
8009088: 1850 adds r0, r2, r1
|
|
800908a: 4283 cmp r3, r0
|
|
800908c: 6011 str r1, [r2, #0]
|
|
800908e: d1e0 bne.n 8009052 <_free_r+0x22>
|
|
8009090: 6818 ldr r0, [r3, #0]
|
|
8009092: 685b ldr r3, [r3, #4]
|
|
8009094: 6053 str r3, [r2, #4]
|
|
8009096: 4408 add r0, r1
|
|
8009098: 6010 str r0, [r2, #0]
|
|
800909a: e7da b.n 8009052 <_free_r+0x22>
|
|
800909c: d902 bls.n 80090a4 <_free_r+0x74>
|
|
800909e: 230c movs r3, #12
|
|
80090a0: 602b str r3, [r5, #0]
|
|
80090a2: e7d6 b.n 8009052 <_free_r+0x22>
|
|
80090a4: 6820 ldr r0, [r4, #0]
|
|
80090a6: 1821 adds r1, r4, r0
|
|
80090a8: 428b cmp r3, r1
|
|
80090aa: bf04 itt eq
|
|
80090ac: 6819 ldreq r1, [r3, #0]
|
|
80090ae: 685b ldreq r3, [r3, #4]
|
|
80090b0: 6063 str r3, [r4, #4]
|
|
80090b2: bf04 itt eq
|
|
80090b4: 1809 addeq r1, r1, r0
|
|
80090b6: 6021 streq r1, [r4, #0]
|
|
80090b8: 6054 str r4, [r2, #4]
|
|
80090ba: e7ca b.n 8009052 <_free_r+0x22>
|
|
80090bc: bd38 pop {r3, r4, r5, pc}
|
|
80090be: bf00 nop
|
|
80090c0: 20000bc0 .word 0x20000bc0
|
|
|
|
080090c4 <malloc>:
|
|
80090c4: 4b02 ldr r3, [pc, #8] @ (80090d0 <malloc+0xc>)
|
|
80090c6: 4601 mov r1, r0
|
|
80090c8: 6818 ldr r0, [r3, #0]
|
|
80090ca: f000 b825 b.w 8009118 <_malloc_r>
|
|
80090ce: bf00 nop
|
|
80090d0: 200000dc .word 0x200000dc
|
|
|
|
080090d4 <sbrk_aligned>:
|
|
80090d4: b570 push {r4, r5, r6, lr}
|
|
80090d6: 4e0f ldr r6, [pc, #60] @ (8009114 <sbrk_aligned+0x40>)
|
|
80090d8: 460c mov r4, r1
|
|
80090da: 6831 ldr r1, [r6, #0]
|
|
80090dc: 4605 mov r5, r0
|
|
80090de: b911 cbnz r1, 80090e6 <sbrk_aligned+0x12>
|
|
80090e0: f000 fe92 bl 8009e08 <_sbrk_r>
|
|
80090e4: 6030 str r0, [r6, #0]
|
|
80090e6: 4621 mov r1, r4
|
|
80090e8: 4628 mov r0, r5
|
|
80090ea: f000 fe8d bl 8009e08 <_sbrk_r>
|
|
80090ee: 1c43 adds r3, r0, #1
|
|
80090f0: d103 bne.n 80090fa <sbrk_aligned+0x26>
|
|
80090f2: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
|
|
80090f6: 4620 mov r0, r4
|
|
80090f8: bd70 pop {r4, r5, r6, pc}
|
|
80090fa: 1cc4 adds r4, r0, #3
|
|
80090fc: f024 0403 bic.w r4, r4, #3
|
|
8009100: 42a0 cmp r0, r4
|
|
8009102: d0f8 beq.n 80090f6 <sbrk_aligned+0x22>
|
|
8009104: 1a21 subs r1, r4, r0
|
|
8009106: 4628 mov r0, r5
|
|
8009108: f000 fe7e bl 8009e08 <_sbrk_r>
|
|
800910c: 3001 adds r0, #1
|
|
800910e: d1f2 bne.n 80090f6 <sbrk_aligned+0x22>
|
|
8009110: e7ef b.n 80090f2 <sbrk_aligned+0x1e>
|
|
8009112: bf00 nop
|
|
8009114: 20000bbc .word 0x20000bbc
|
|
|
|
08009118 <_malloc_r>:
|
|
8009118: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
800911c: 1ccd adds r5, r1, #3
|
|
800911e: f025 0503 bic.w r5, r5, #3
|
|
8009122: 3508 adds r5, #8
|
|
8009124: 2d0c cmp r5, #12
|
|
8009126: bf38 it cc
|
|
8009128: 250c movcc r5, #12
|
|
800912a: 2d00 cmp r5, #0
|
|
800912c: 4606 mov r6, r0
|
|
800912e: db01 blt.n 8009134 <_malloc_r+0x1c>
|
|
8009130: 42a9 cmp r1, r5
|
|
8009132: d904 bls.n 800913e <_malloc_r+0x26>
|
|
8009134: 230c movs r3, #12
|
|
8009136: 6033 str r3, [r6, #0]
|
|
8009138: 2000 movs r0, #0
|
|
800913a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
800913e: f8df 80d4 ldr.w r8, [pc, #212] @ 8009214 <_malloc_r+0xfc>
|
|
8009142: f000 f869 bl 8009218 <__malloc_lock>
|
|
8009146: f8d8 3000 ldr.w r3, [r8]
|
|
800914a: 461c mov r4, r3
|
|
800914c: bb44 cbnz r4, 80091a0 <_malloc_r+0x88>
|
|
800914e: 4629 mov r1, r5
|
|
8009150: 4630 mov r0, r6
|
|
8009152: f7ff ffbf bl 80090d4 <sbrk_aligned>
|
|
8009156: 1c43 adds r3, r0, #1
|
|
8009158: 4604 mov r4, r0
|
|
800915a: d158 bne.n 800920e <_malloc_r+0xf6>
|
|
800915c: f8d8 4000 ldr.w r4, [r8]
|
|
8009160: 4627 mov r7, r4
|
|
8009162: 2f00 cmp r7, #0
|
|
8009164: d143 bne.n 80091ee <_malloc_r+0xd6>
|
|
8009166: 2c00 cmp r4, #0
|
|
8009168: d04b beq.n 8009202 <_malloc_r+0xea>
|
|
800916a: 6823 ldr r3, [r4, #0]
|
|
800916c: 4639 mov r1, r7
|
|
800916e: 4630 mov r0, r6
|
|
8009170: eb04 0903 add.w r9, r4, r3
|
|
8009174: f000 fe48 bl 8009e08 <_sbrk_r>
|
|
8009178: 4581 cmp r9, r0
|
|
800917a: d142 bne.n 8009202 <_malloc_r+0xea>
|
|
800917c: 6821 ldr r1, [r4, #0]
|
|
800917e: 1a6d subs r5, r5, r1
|
|
8009180: 4629 mov r1, r5
|
|
8009182: 4630 mov r0, r6
|
|
8009184: f7ff ffa6 bl 80090d4 <sbrk_aligned>
|
|
8009188: 3001 adds r0, #1
|
|
800918a: d03a beq.n 8009202 <_malloc_r+0xea>
|
|
800918c: 6823 ldr r3, [r4, #0]
|
|
800918e: 442b add r3, r5
|
|
8009190: 6023 str r3, [r4, #0]
|
|
8009192: f8d8 3000 ldr.w r3, [r8]
|
|
8009196: 685a ldr r2, [r3, #4]
|
|
8009198: bb62 cbnz r2, 80091f4 <_malloc_r+0xdc>
|
|
800919a: f8c8 7000 str.w r7, [r8]
|
|
800919e: e00f b.n 80091c0 <_malloc_r+0xa8>
|
|
80091a0: 6822 ldr r2, [r4, #0]
|
|
80091a2: 1b52 subs r2, r2, r5
|
|
80091a4: d420 bmi.n 80091e8 <_malloc_r+0xd0>
|
|
80091a6: 2a0b cmp r2, #11
|
|
80091a8: d917 bls.n 80091da <_malloc_r+0xc2>
|
|
80091aa: 1961 adds r1, r4, r5
|
|
80091ac: 42a3 cmp r3, r4
|
|
80091ae: 6025 str r5, [r4, #0]
|
|
80091b0: bf18 it ne
|
|
80091b2: 6059 strne r1, [r3, #4]
|
|
80091b4: 6863 ldr r3, [r4, #4]
|
|
80091b6: bf08 it eq
|
|
80091b8: f8c8 1000 streq.w r1, [r8]
|
|
80091bc: 5162 str r2, [r4, r5]
|
|
80091be: 604b str r3, [r1, #4]
|
|
80091c0: 4630 mov r0, r6
|
|
80091c2: f000 f82f bl 8009224 <__malloc_unlock>
|
|
80091c6: f104 000b add.w r0, r4, #11
|
|
80091ca: 1d23 adds r3, r4, #4
|
|
80091cc: f020 0007 bic.w r0, r0, #7
|
|
80091d0: 1ac2 subs r2, r0, r3
|
|
80091d2: bf1c itt ne
|
|
80091d4: 1a1b subne r3, r3, r0
|
|
80091d6: 50a3 strne r3, [r4, r2]
|
|
80091d8: e7af b.n 800913a <_malloc_r+0x22>
|
|
80091da: 6862 ldr r2, [r4, #4]
|
|
80091dc: 42a3 cmp r3, r4
|
|
80091de: bf0c ite eq
|
|
80091e0: f8c8 2000 streq.w r2, [r8]
|
|
80091e4: 605a strne r2, [r3, #4]
|
|
80091e6: e7eb b.n 80091c0 <_malloc_r+0xa8>
|
|
80091e8: 4623 mov r3, r4
|
|
80091ea: 6864 ldr r4, [r4, #4]
|
|
80091ec: e7ae b.n 800914c <_malloc_r+0x34>
|
|
80091ee: 463c mov r4, r7
|
|
80091f0: 687f ldr r7, [r7, #4]
|
|
80091f2: e7b6 b.n 8009162 <_malloc_r+0x4a>
|
|
80091f4: 461a mov r2, r3
|
|
80091f6: 685b ldr r3, [r3, #4]
|
|
80091f8: 42a3 cmp r3, r4
|
|
80091fa: d1fb bne.n 80091f4 <_malloc_r+0xdc>
|
|
80091fc: 2300 movs r3, #0
|
|
80091fe: 6053 str r3, [r2, #4]
|
|
8009200: e7de b.n 80091c0 <_malloc_r+0xa8>
|
|
8009202: 230c movs r3, #12
|
|
8009204: 6033 str r3, [r6, #0]
|
|
8009206: 4630 mov r0, r6
|
|
8009208: f000 f80c bl 8009224 <__malloc_unlock>
|
|
800920c: e794 b.n 8009138 <_malloc_r+0x20>
|
|
800920e: 6005 str r5, [r0, #0]
|
|
8009210: e7d6 b.n 80091c0 <_malloc_r+0xa8>
|
|
8009212: bf00 nop
|
|
8009214: 20000bc0 .word 0x20000bc0
|
|
|
|
08009218 <__malloc_lock>:
|
|
8009218: 4801 ldr r0, [pc, #4] @ (8009220 <__malloc_lock+0x8>)
|
|
800921a: f7ff b89e b.w 800835a <__retarget_lock_acquire_recursive>
|
|
800921e: bf00 nop
|
|
8009220: 20000bb8 .word 0x20000bb8
|
|
|
|
08009224 <__malloc_unlock>:
|
|
8009224: 4801 ldr r0, [pc, #4] @ (800922c <__malloc_unlock+0x8>)
|
|
8009226: f7ff b899 b.w 800835c <__retarget_lock_release_recursive>
|
|
800922a: bf00 nop
|
|
800922c: 20000bb8 .word 0x20000bb8
|
|
|
|
08009230 <_Balloc>:
|
|
8009230: b570 push {r4, r5, r6, lr}
|
|
8009232: 69c6 ldr r6, [r0, #28]
|
|
8009234: 4604 mov r4, r0
|
|
8009236: 460d mov r5, r1
|
|
8009238: b976 cbnz r6, 8009258 <_Balloc+0x28>
|
|
800923a: 2010 movs r0, #16
|
|
800923c: f7ff ff42 bl 80090c4 <malloc>
|
|
8009240: 4602 mov r2, r0
|
|
8009242: 61e0 str r0, [r4, #28]
|
|
8009244: b920 cbnz r0, 8009250 <_Balloc+0x20>
|
|
8009246: 4b18 ldr r3, [pc, #96] @ (80092a8 <_Balloc+0x78>)
|
|
8009248: 4818 ldr r0, [pc, #96] @ (80092ac <_Balloc+0x7c>)
|
|
800924a: 216b movs r1, #107 @ 0x6b
|
|
800924c: f000 fdec bl 8009e28 <__assert_func>
|
|
8009250: e9c0 6601 strd r6, r6, [r0, #4]
|
|
8009254: 6006 str r6, [r0, #0]
|
|
8009256: 60c6 str r6, [r0, #12]
|
|
8009258: 69e6 ldr r6, [r4, #28]
|
|
800925a: 68f3 ldr r3, [r6, #12]
|
|
800925c: b183 cbz r3, 8009280 <_Balloc+0x50>
|
|
800925e: 69e3 ldr r3, [r4, #28]
|
|
8009260: 68db ldr r3, [r3, #12]
|
|
8009262: f853 0025 ldr.w r0, [r3, r5, lsl #2]
|
|
8009266: b9b8 cbnz r0, 8009298 <_Balloc+0x68>
|
|
8009268: 2101 movs r1, #1
|
|
800926a: fa01 f605 lsl.w r6, r1, r5
|
|
800926e: 1d72 adds r2, r6, #5
|
|
8009270: 0092 lsls r2, r2, #2
|
|
8009272: 4620 mov r0, r4
|
|
8009274: f000 fdf6 bl 8009e64 <_calloc_r>
|
|
8009278: b160 cbz r0, 8009294 <_Balloc+0x64>
|
|
800927a: e9c0 5601 strd r5, r6, [r0, #4]
|
|
800927e: e00e b.n 800929e <_Balloc+0x6e>
|
|
8009280: 2221 movs r2, #33 @ 0x21
|
|
8009282: 2104 movs r1, #4
|
|
8009284: 4620 mov r0, r4
|
|
8009286: f000 fded bl 8009e64 <_calloc_r>
|
|
800928a: 69e3 ldr r3, [r4, #28]
|
|
800928c: 60f0 str r0, [r6, #12]
|
|
800928e: 68db ldr r3, [r3, #12]
|
|
8009290: 2b00 cmp r3, #0
|
|
8009292: d1e4 bne.n 800925e <_Balloc+0x2e>
|
|
8009294: 2000 movs r0, #0
|
|
8009296: bd70 pop {r4, r5, r6, pc}
|
|
8009298: 6802 ldr r2, [r0, #0]
|
|
800929a: f843 2025 str.w r2, [r3, r5, lsl #2]
|
|
800929e: 2300 movs r3, #0
|
|
80092a0: e9c0 3303 strd r3, r3, [r0, #12]
|
|
80092a4: e7f7 b.n 8009296 <_Balloc+0x66>
|
|
80092a6: bf00 nop
|
|
80092a8: 0800a161 .word 0x0800a161
|
|
80092ac: 0800a1e1 .word 0x0800a1e1
|
|
|
|
080092b0 <_Bfree>:
|
|
80092b0: b570 push {r4, r5, r6, lr}
|
|
80092b2: 69c6 ldr r6, [r0, #28]
|
|
80092b4: 4605 mov r5, r0
|
|
80092b6: 460c mov r4, r1
|
|
80092b8: b976 cbnz r6, 80092d8 <_Bfree+0x28>
|
|
80092ba: 2010 movs r0, #16
|
|
80092bc: f7ff ff02 bl 80090c4 <malloc>
|
|
80092c0: 4602 mov r2, r0
|
|
80092c2: 61e8 str r0, [r5, #28]
|
|
80092c4: b920 cbnz r0, 80092d0 <_Bfree+0x20>
|
|
80092c6: 4b09 ldr r3, [pc, #36] @ (80092ec <_Bfree+0x3c>)
|
|
80092c8: 4809 ldr r0, [pc, #36] @ (80092f0 <_Bfree+0x40>)
|
|
80092ca: 218f movs r1, #143 @ 0x8f
|
|
80092cc: f000 fdac bl 8009e28 <__assert_func>
|
|
80092d0: e9c0 6601 strd r6, r6, [r0, #4]
|
|
80092d4: 6006 str r6, [r0, #0]
|
|
80092d6: 60c6 str r6, [r0, #12]
|
|
80092d8: b13c cbz r4, 80092ea <_Bfree+0x3a>
|
|
80092da: 69eb ldr r3, [r5, #28]
|
|
80092dc: 6862 ldr r2, [r4, #4]
|
|
80092de: 68db ldr r3, [r3, #12]
|
|
80092e0: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
80092e4: 6021 str r1, [r4, #0]
|
|
80092e6: f843 4022 str.w r4, [r3, r2, lsl #2]
|
|
80092ea: bd70 pop {r4, r5, r6, pc}
|
|
80092ec: 0800a161 .word 0x0800a161
|
|
80092f0: 0800a1e1 .word 0x0800a1e1
|
|
|
|
080092f4 <__multadd>:
|
|
80092f4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
80092f8: 690d ldr r5, [r1, #16]
|
|
80092fa: 4607 mov r7, r0
|
|
80092fc: 460c mov r4, r1
|
|
80092fe: 461e mov r6, r3
|
|
8009300: f101 0c14 add.w ip, r1, #20
|
|
8009304: 2000 movs r0, #0
|
|
8009306: f8dc 3000 ldr.w r3, [ip]
|
|
800930a: b299 uxth r1, r3
|
|
800930c: fb02 6101 mla r1, r2, r1, r6
|
|
8009310: 0c1e lsrs r6, r3, #16
|
|
8009312: 0c0b lsrs r3, r1, #16
|
|
8009314: fb02 3306 mla r3, r2, r6, r3
|
|
8009318: b289 uxth r1, r1
|
|
800931a: 3001 adds r0, #1
|
|
800931c: eb01 4103 add.w r1, r1, r3, lsl #16
|
|
8009320: 4285 cmp r5, r0
|
|
8009322: f84c 1b04 str.w r1, [ip], #4
|
|
8009326: ea4f 4613 mov.w r6, r3, lsr #16
|
|
800932a: dcec bgt.n 8009306 <__multadd+0x12>
|
|
800932c: b30e cbz r6, 8009372 <__multadd+0x7e>
|
|
800932e: 68a3 ldr r3, [r4, #8]
|
|
8009330: 42ab cmp r3, r5
|
|
8009332: dc19 bgt.n 8009368 <__multadd+0x74>
|
|
8009334: 6861 ldr r1, [r4, #4]
|
|
8009336: 4638 mov r0, r7
|
|
8009338: 3101 adds r1, #1
|
|
800933a: f7ff ff79 bl 8009230 <_Balloc>
|
|
800933e: 4680 mov r8, r0
|
|
8009340: b928 cbnz r0, 800934e <__multadd+0x5a>
|
|
8009342: 4602 mov r2, r0
|
|
8009344: 4b0c ldr r3, [pc, #48] @ (8009378 <__multadd+0x84>)
|
|
8009346: 480d ldr r0, [pc, #52] @ (800937c <__multadd+0x88>)
|
|
8009348: 21ba movs r1, #186 @ 0xba
|
|
800934a: f000 fd6d bl 8009e28 <__assert_func>
|
|
800934e: 6922 ldr r2, [r4, #16]
|
|
8009350: 3202 adds r2, #2
|
|
8009352: f104 010c add.w r1, r4, #12
|
|
8009356: 0092 lsls r2, r2, #2
|
|
8009358: 300c adds r0, #12
|
|
800935a: f7ff f800 bl 800835e <memcpy>
|
|
800935e: 4621 mov r1, r4
|
|
8009360: 4638 mov r0, r7
|
|
8009362: f7ff ffa5 bl 80092b0 <_Bfree>
|
|
8009366: 4644 mov r4, r8
|
|
8009368: eb04 0385 add.w r3, r4, r5, lsl #2
|
|
800936c: 3501 adds r5, #1
|
|
800936e: 615e str r6, [r3, #20]
|
|
8009370: 6125 str r5, [r4, #16]
|
|
8009372: 4620 mov r0, r4
|
|
8009374: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
8009378: 0800a1d0 .word 0x0800a1d0
|
|
800937c: 0800a1e1 .word 0x0800a1e1
|
|
|
|
08009380 <__hi0bits>:
|
|
8009380: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
|
|
8009384: 4603 mov r3, r0
|
|
8009386: bf36 itet cc
|
|
8009388: 0403 lslcc r3, r0, #16
|
|
800938a: 2000 movcs r0, #0
|
|
800938c: 2010 movcc r0, #16
|
|
800938e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8009392: bf3c itt cc
|
|
8009394: 021b lslcc r3, r3, #8
|
|
8009396: 3008 addcc r0, #8
|
|
8009398: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
800939c: bf3c itt cc
|
|
800939e: 011b lslcc r3, r3, #4
|
|
80093a0: 3004 addcc r0, #4
|
|
80093a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80093a6: bf3c itt cc
|
|
80093a8: 009b lslcc r3, r3, #2
|
|
80093aa: 3002 addcc r0, #2
|
|
80093ac: 2b00 cmp r3, #0
|
|
80093ae: db05 blt.n 80093bc <__hi0bits+0x3c>
|
|
80093b0: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
|
|
80093b4: f100 0001 add.w r0, r0, #1
|
|
80093b8: bf08 it eq
|
|
80093ba: 2020 moveq r0, #32
|
|
80093bc: 4770 bx lr
|
|
|
|
080093be <__lo0bits>:
|
|
80093be: 6803 ldr r3, [r0, #0]
|
|
80093c0: 4602 mov r2, r0
|
|
80093c2: f013 0007 ands.w r0, r3, #7
|
|
80093c6: d00b beq.n 80093e0 <__lo0bits+0x22>
|
|
80093c8: 07d9 lsls r1, r3, #31
|
|
80093ca: d421 bmi.n 8009410 <__lo0bits+0x52>
|
|
80093cc: 0798 lsls r0, r3, #30
|
|
80093ce: bf49 itett mi
|
|
80093d0: 085b lsrmi r3, r3, #1
|
|
80093d2: 089b lsrpl r3, r3, #2
|
|
80093d4: 2001 movmi r0, #1
|
|
80093d6: 6013 strmi r3, [r2, #0]
|
|
80093d8: bf5c itt pl
|
|
80093da: 6013 strpl r3, [r2, #0]
|
|
80093dc: 2002 movpl r0, #2
|
|
80093de: 4770 bx lr
|
|
80093e0: b299 uxth r1, r3
|
|
80093e2: b909 cbnz r1, 80093e8 <__lo0bits+0x2a>
|
|
80093e4: 0c1b lsrs r3, r3, #16
|
|
80093e6: 2010 movs r0, #16
|
|
80093e8: b2d9 uxtb r1, r3
|
|
80093ea: b909 cbnz r1, 80093f0 <__lo0bits+0x32>
|
|
80093ec: 3008 adds r0, #8
|
|
80093ee: 0a1b lsrs r3, r3, #8
|
|
80093f0: 0719 lsls r1, r3, #28
|
|
80093f2: bf04 itt eq
|
|
80093f4: 091b lsreq r3, r3, #4
|
|
80093f6: 3004 addeq r0, #4
|
|
80093f8: 0799 lsls r1, r3, #30
|
|
80093fa: bf04 itt eq
|
|
80093fc: 089b lsreq r3, r3, #2
|
|
80093fe: 3002 addeq r0, #2
|
|
8009400: 07d9 lsls r1, r3, #31
|
|
8009402: d403 bmi.n 800940c <__lo0bits+0x4e>
|
|
8009404: 085b lsrs r3, r3, #1
|
|
8009406: f100 0001 add.w r0, r0, #1
|
|
800940a: d003 beq.n 8009414 <__lo0bits+0x56>
|
|
800940c: 6013 str r3, [r2, #0]
|
|
800940e: 4770 bx lr
|
|
8009410: 2000 movs r0, #0
|
|
8009412: 4770 bx lr
|
|
8009414: 2020 movs r0, #32
|
|
8009416: 4770 bx lr
|
|
|
|
08009418 <__i2b>:
|
|
8009418: b510 push {r4, lr}
|
|
800941a: 460c mov r4, r1
|
|
800941c: 2101 movs r1, #1
|
|
800941e: f7ff ff07 bl 8009230 <_Balloc>
|
|
8009422: 4602 mov r2, r0
|
|
8009424: b928 cbnz r0, 8009432 <__i2b+0x1a>
|
|
8009426: 4b05 ldr r3, [pc, #20] @ (800943c <__i2b+0x24>)
|
|
8009428: 4805 ldr r0, [pc, #20] @ (8009440 <__i2b+0x28>)
|
|
800942a: f240 1145 movw r1, #325 @ 0x145
|
|
800942e: f000 fcfb bl 8009e28 <__assert_func>
|
|
8009432: 2301 movs r3, #1
|
|
8009434: 6144 str r4, [r0, #20]
|
|
8009436: 6103 str r3, [r0, #16]
|
|
8009438: bd10 pop {r4, pc}
|
|
800943a: bf00 nop
|
|
800943c: 0800a1d0 .word 0x0800a1d0
|
|
8009440: 0800a1e1 .word 0x0800a1e1
|
|
|
|
08009444 <__multiply>:
|
|
8009444: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8009448: 4617 mov r7, r2
|
|
800944a: 690a ldr r2, [r1, #16]
|
|
800944c: 693b ldr r3, [r7, #16]
|
|
800944e: 429a cmp r2, r3
|
|
8009450: bfa8 it ge
|
|
8009452: 463b movge r3, r7
|
|
8009454: 4689 mov r9, r1
|
|
8009456: bfa4 itt ge
|
|
8009458: 460f movge r7, r1
|
|
800945a: 4699 movge r9, r3
|
|
800945c: 693d ldr r5, [r7, #16]
|
|
800945e: f8d9 a010 ldr.w sl, [r9, #16]
|
|
8009462: 68bb ldr r3, [r7, #8]
|
|
8009464: 6879 ldr r1, [r7, #4]
|
|
8009466: eb05 060a add.w r6, r5, sl
|
|
800946a: 42b3 cmp r3, r6
|
|
800946c: b085 sub sp, #20
|
|
800946e: bfb8 it lt
|
|
8009470: 3101 addlt r1, #1
|
|
8009472: f7ff fedd bl 8009230 <_Balloc>
|
|
8009476: b930 cbnz r0, 8009486 <__multiply+0x42>
|
|
8009478: 4602 mov r2, r0
|
|
800947a: 4b41 ldr r3, [pc, #260] @ (8009580 <__multiply+0x13c>)
|
|
800947c: 4841 ldr r0, [pc, #260] @ (8009584 <__multiply+0x140>)
|
|
800947e: f44f 71b1 mov.w r1, #354 @ 0x162
|
|
8009482: f000 fcd1 bl 8009e28 <__assert_func>
|
|
8009486: f100 0414 add.w r4, r0, #20
|
|
800948a: eb04 0e86 add.w lr, r4, r6, lsl #2
|
|
800948e: 4623 mov r3, r4
|
|
8009490: 2200 movs r2, #0
|
|
8009492: 4573 cmp r3, lr
|
|
8009494: d320 bcc.n 80094d8 <__multiply+0x94>
|
|
8009496: f107 0814 add.w r8, r7, #20
|
|
800949a: f109 0114 add.w r1, r9, #20
|
|
800949e: eb08 0585 add.w r5, r8, r5, lsl #2
|
|
80094a2: eb01 038a add.w r3, r1, sl, lsl #2
|
|
80094a6: 9302 str r3, [sp, #8]
|
|
80094a8: 1beb subs r3, r5, r7
|
|
80094aa: 3b15 subs r3, #21
|
|
80094ac: f023 0303 bic.w r3, r3, #3
|
|
80094b0: 3304 adds r3, #4
|
|
80094b2: 3715 adds r7, #21
|
|
80094b4: 42bd cmp r5, r7
|
|
80094b6: bf38 it cc
|
|
80094b8: 2304 movcc r3, #4
|
|
80094ba: 9301 str r3, [sp, #4]
|
|
80094bc: 9b02 ldr r3, [sp, #8]
|
|
80094be: 9103 str r1, [sp, #12]
|
|
80094c0: 428b cmp r3, r1
|
|
80094c2: d80c bhi.n 80094de <__multiply+0x9a>
|
|
80094c4: 2e00 cmp r6, #0
|
|
80094c6: dd03 ble.n 80094d0 <__multiply+0x8c>
|
|
80094c8: f85e 3d04 ldr.w r3, [lr, #-4]!
|
|
80094cc: 2b00 cmp r3, #0
|
|
80094ce: d055 beq.n 800957c <__multiply+0x138>
|
|
80094d0: 6106 str r6, [r0, #16]
|
|
80094d2: b005 add sp, #20
|
|
80094d4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80094d8: f843 2b04 str.w r2, [r3], #4
|
|
80094dc: e7d9 b.n 8009492 <__multiply+0x4e>
|
|
80094de: f8b1 a000 ldrh.w sl, [r1]
|
|
80094e2: f1ba 0f00 cmp.w sl, #0
|
|
80094e6: d01f beq.n 8009528 <__multiply+0xe4>
|
|
80094e8: 46c4 mov ip, r8
|
|
80094ea: 46a1 mov r9, r4
|
|
80094ec: 2700 movs r7, #0
|
|
80094ee: f85c 2b04 ldr.w r2, [ip], #4
|
|
80094f2: f8d9 3000 ldr.w r3, [r9]
|
|
80094f6: fa1f fb82 uxth.w fp, r2
|
|
80094fa: b29b uxth r3, r3
|
|
80094fc: fb0a 330b mla r3, sl, fp, r3
|
|
8009500: 443b add r3, r7
|
|
8009502: f8d9 7000 ldr.w r7, [r9]
|
|
8009506: 0c12 lsrs r2, r2, #16
|
|
8009508: 0c3f lsrs r7, r7, #16
|
|
800950a: fb0a 7202 mla r2, sl, r2, r7
|
|
800950e: eb02 4213 add.w r2, r2, r3, lsr #16
|
|
8009512: b29b uxth r3, r3
|
|
8009514: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8009518: 4565 cmp r5, ip
|
|
800951a: f849 3b04 str.w r3, [r9], #4
|
|
800951e: ea4f 4712 mov.w r7, r2, lsr #16
|
|
8009522: d8e4 bhi.n 80094ee <__multiply+0xaa>
|
|
8009524: 9b01 ldr r3, [sp, #4]
|
|
8009526: 50e7 str r7, [r4, r3]
|
|
8009528: 9b03 ldr r3, [sp, #12]
|
|
800952a: f8b3 9002 ldrh.w r9, [r3, #2]
|
|
800952e: 3104 adds r1, #4
|
|
8009530: f1b9 0f00 cmp.w r9, #0
|
|
8009534: d020 beq.n 8009578 <__multiply+0x134>
|
|
8009536: 6823 ldr r3, [r4, #0]
|
|
8009538: 4647 mov r7, r8
|
|
800953a: 46a4 mov ip, r4
|
|
800953c: f04f 0a00 mov.w sl, #0
|
|
8009540: f8b7 b000 ldrh.w fp, [r7]
|
|
8009544: f8bc 2002 ldrh.w r2, [ip, #2]
|
|
8009548: fb09 220b mla r2, r9, fp, r2
|
|
800954c: 4452 add r2, sl
|
|
800954e: b29b uxth r3, r3
|
|
8009550: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8009554: f84c 3b04 str.w r3, [ip], #4
|
|
8009558: f857 3b04 ldr.w r3, [r7], #4
|
|
800955c: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
8009560: f8bc 3000 ldrh.w r3, [ip]
|
|
8009564: fb09 330a mla r3, r9, sl, r3
|
|
8009568: eb03 4312 add.w r3, r3, r2, lsr #16
|
|
800956c: 42bd cmp r5, r7
|
|
800956e: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
8009572: d8e5 bhi.n 8009540 <__multiply+0xfc>
|
|
8009574: 9a01 ldr r2, [sp, #4]
|
|
8009576: 50a3 str r3, [r4, r2]
|
|
8009578: 3404 adds r4, #4
|
|
800957a: e79f b.n 80094bc <__multiply+0x78>
|
|
800957c: 3e01 subs r6, #1
|
|
800957e: e7a1 b.n 80094c4 <__multiply+0x80>
|
|
8009580: 0800a1d0 .word 0x0800a1d0
|
|
8009584: 0800a1e1 .word 0x0800a1e1
|
|
|
|
08009588 <__pow5mult>:
|
|
8009588: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
800958c: 4615 mov r5, r2
|
|
800958e: f012 0203 ands.w r2, r2, #3
|
|
8009592: 4607 mov r7, r0
|
|
8009594: 460e mov r6, r1
|
|
8009596: d007 beq.n 80095a8 <__pow5mult+0x20>
|
|
8009598: 4c25 ldr r4, [pc, #148] @ (8009630 <__pow5mult+0xa8>)
|
|
800959a: 3a01 subs r2, #1
|
|
800959c: 2300 movs r3, #0
|
|
800959e: f854 2022 ldr.w r2, [r4, r2, lsl #2]
|
|
80095a2: f7ff fea7 bl 80092f4 <__multadd>
|
|
80095a6: 4606 mov r6, r0
|
|
80095a8: 10ad asrs r5, r5, #2
|
|
80095aa: d03d beq.n 8009628 <__pow5mult+0xa0>
|
|
80095ac: 69fc ldr r4, [r7, #28]
|
|
80095ae: b97c cbnz r4, 80095d0 <__pow5mult+0x48>
|
|
80095b0: 2010 movs r0, #16
|
|
80095b2: f7ff fd87 bl 80090c4 <malloc>
|
|
80095b6: 4602 mov r2, r0
|
|
80095b8: 61f8 str r0, [r7, #28]
|
|
80095ba: b928 cbnz r0, 80095c8 <__pow5mult+0x40>
|
|
80095bc: 4b1d ldr r3, [pc, #116] @ (8009634 <__pow5mult+0xac>)
|
|
80095be: 481e ldr r0, [pc, #120] @ (8009638 <__pow5mult+0xb0>)
|
|
80095c0: f240 11b3 movw r1, #435 @ 0x1b3
|
|
80095c4: f000 fc30 bl 8009e28 <__assert_func>
|
|
80095c8: e9c0 4401 strd r4, r4, [r0, #4]
|
|
80095cc: 6004 str r4, [r0, #0]
|
|
80095ce: 60c4 str r4, [r0, #12]
|
|
80095d0: f8d7 801c ldr.w r8, [r7, #28]
|
|
80095d4: f8d8 4008 ldr.w r4, [r8, #8]
|
|
80095d8: b94c cbnz r4, 80095ee <__pow5mult+0x66>
|
|
80095da: f240 2171 movw r1, #625 @ 0x271
|
|
80095de: 4638 mov r0, r7
|
|
80095e0: f7ff ff1a bl 8009418 <__i2b>
|
|
80095e4: 2300 movs r3, #0
|
|
80095e6: f8c8 0008 str.w r0, [r8, #8]
|
|
80095ea: 4604 mov r4, r0
|
|
80095ec: 6003 str r3, [r0, #0]
|
|
80095ee: f04f 0900 mov.w r9, #0
|
|
80095f2: 07eb lsls r3, r5, #31
|
|
80095f4: d50a bpl.n 800960c <__pow5mult+0x84>
|
|
80095f6: 4631 mov r1, r6
|
|
80095f8: 4622 mov r2, r4
|
|
80095fa: 4638 mov r0, r7
|
|
80095fc: f7ff ff22 bl 8009444 <__multiply>
|
|
8009600: 4631 mov r1, r6
|
|
8009602: 4680 mov r8, r0
|
|
8009604: 4638 mov r0, r7
|
|
8009606: f7ff fe53 bl 80092b0 <_Bfree>
|
|
800960a: 4646 mov r6, r8
|
|
800960c: 106d asrs r5, r5, #1
|
|
800960e: d00b beq.n 8009628 <__pow5mult+0xa0>
|
|
8009610: 6820 ldr r0, [r4, #0]
|
|
8009612: b938 cbnz r0, 8009624 <__pow5mult+0x9c>
|
|
8009614: 4622 mov r2, r4
|
|
8009616: 4621 mov r1, r4
|
|
8009618: 4638 mov r0, r7
|
|
800961a: f7ff ff13 bl 8009444 <__multiply>
|
|
800961e: 6020 str r0, [r4, #0]
|
|
8009620: f8c0 9000 str.w r9, [r0]
|
|
8009624: 4604 mov r4, r0
|
|
8009626: e7e4 b.n 80095f2 <__pow5mult+0x6a>
|
|
8009628: 4630 mov r0, r6
|
|
800962a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
800962e: bf00 nop
|
|
8009630: 0800a294 .word 0x0800a294
|
|
8009634: 0800a161 .word 0x0800a161
|
|
8009638: 0800a1e1 .word 0x0800a1e1
|
|
|
|
0800963c <__lshift>:
|
|
800963c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8009640: 460c mov r4, r1
|
|
8009642: 6849 ldr r1, [r1, #4]
|
|
8009644: 6923 ldr r3, [r4, #16]
|
|
8009646: eb03 1862 add.w r8, r3, r2, asr #5
|
|
800964a: 68a3 ldr r3, [r4, #8]
|
|
800964c: 4607 mov r7, r0
|
|
800964e: 4691 mov r9, r2
|
|
8009650: ea4f 1a62 mov.w sl, r2, asr #5
|
|
8009654: f108 0601 add.w r6, r8, #1
|
|
8009658: 42b3 cmp r3, r6
|
|
800965a: db0b blt.n 8009674 <__lshift+0x38>
|
|
800965c: 4638 mov r0, r7
|
|
800965e: f7ff fde7 bl 8009230 <_Balloc>
|
|
8009662: 4605 mov r5, r0
|
|
8009664: b948 cbnz r0, 800967a <__lshift+0x3e>
|
|
8009666: 4602 mov r2, r0
|
|
8009668: 4b28 ldr r3, [pc, #160] @ (800970c <__lshift+0xd0>)
|
|
800966a: 4829 ldr r0, [pc, #164] @ (8009710 <__lshift+0xd4>)
|
|
800966c: f44f 71ef mov.w r1, #478 @ 0x1de
|
|
8009670: f000 fbda bl 8009e28 <__assert_func>
|
|
8009674: 3101 adds r1, #1
|
|
8009676: 005b lsls r3, r3, #1
|
|
8009678: e7ee b.n 8009658 <__lshift+0x1c>
|
|
800967a: 2300 movs r3, #0
|
|
800967c: f100 0114 add.w r1, r0, #20
|
|
8009680: f100 0210 add.w r2, r0, #16
|
|
8009684: 4618 mov r0, r3
|
|
8009686: 4553 cmp r3, sl
|
|
8009688: db33 blt.n 80096f2 <__lshift+0xb6>
|
|
800968a: 6920 ldr r0, [r4, #16]
|
|
800968c: ea2a 7aea bic.w sl, sl, sl, asr #31
|
|
8009690: f104 0314 add.w r3, r4, #20
|
|
8009694: f019 091f ands.w r9, r9, #31
|
|
8009698: eb01 018a add.w r1, r1, sl, lsl #2
|
|
800969c: eb03 0c80 add.w ip, r3, r0, lsl #2
|
|
80096a0: d02b beq.n 80096fa <__lshift+0xbe>
|
|
80096a2: f1c9 0e20 rsb lr, r9, #32
|
|
80096a6: 468a mov sl, r1
|
|
80096a8: 2200 movs r2, #0
|
|
80096aa: 6818 ldr r0, [r3, #0]
|
|
80096ac: fa00 f009 lsl.w r0, r0, r9
|
|
80096b0: 4310 orrs r0, r2
|
|
80096b2: f84a 0b04 str.w r0, [sl], #4
|
|
80096b6: f853 2b04 ldr.w r2, [r3], #4
|
|
80096ba: 459c cmp ip, r3
|
|
80096bc: fa22 f20e lsr.w r2, r2, lr
|
|
80096c0: d8f3 bhi.n 80096aa <__lshift+0x6e>
|
|
80096c2: ebac 0304 sub.w r3, ip, r4
|
|
80096c6: 3b15 subs r3, #21
|
|
80096c8: f023 0303 bic.w r3, r3, #3
|
|
80096cc: 3304 adds r3, #4
|
|
80096ce: f104 0015 add.w r0, r4, #21
|
|
80096d2: 4560 cmp r0, ip
|
|
80096d4: bf88 it hi
|
|
80096d6: 2304 movhi r3, #4
|
|
80096d8: 50ca str r2, [r1, r3]
|
|
80096da: b10a cbz r2, 80096e0 <__lshift+0xa4>
|
|
80096dc: f108 0602 add.w r6, r8, #2
|
|
80096e0: 3e01 subs r6, #1
|
|
80096e2: 4638 mov r0, r7
|
|
80096e4: 612e str r6, [r5, #16]
|
|
80096e6: 4621 mov r1, r4
|
|
80096e8: f7ff fde2 bl 80092b0 <_Bfree>
|
|
80096ec: 4628 mov r0, r5
|
|
80096ee: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
80096f2: f842 0f04 str.w r0, [r2, #4]!
|
|
80096f6: 3301 adds r3, #1
|
|
80096f8: e7c5 b.n 8009686 <__lshift+0x4a>
|
|
80096fa: 3904 subs r1, #4
|
|
80096fc: f853 2b04 ldr.w r2, [r3], #4
|
|
8009700: f841 2f04 str.w r2, [r1, #4]!
|
|
8009704: 459c cmp ip, r3
|
|
8009706: d8f9 bhi.n 80096fc <__lshift+0xc0>
|
|
8009708: e7ea b.n 80096e0 <__lshift+0xa4>
|
|
800970a: bf00 nop
|
|
800970c: 0800a1d0 .word 0x0800a1d0
|
|
8009710: 0800a1e1 .word 0x0800a1e1
|
|
|
|
08009714 <__mcmp>:
|
|
8009714: 690a ldr r2, [r1, #16]
|
|
8009716: 4603 mov r3, r0
|
|
8009718: 6900 ldr r0, [r0, #16]
|
|
800971a: 1a80 subs r0, r0, r2
|
|
800971c: b530 push {r4, r5, lr}
|
|
800971e: d10e bne.n 800973e <__mcmp+0x2a>
|
|
8009720: 3314 adds r3, #20
|
|
8009722: 3114 adds r1, #20
|
|
8009724: eb03 0482 add.w r4, r3, r2, lsl #2
|
|
8009728: eb01 0182 add.w r1, r1, r2, lsl #2
|
|
800972c: f854 5d04 ldr.w r5, [r4, #-4]!
|
|
8009730: f851 2d04 ldr.w r2, [r1, #-4]!
|
|
8009734: 4295 cmp r5, r2
|
|
8009736: d003 beq.n 8009740 <__mcmp+0x2c>
|
|
8009738: d205 bcs.n 8009746 <__mcmp+0x32>
|
|
800973a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800973e: bd30 pop {r4, r5, pc}
|
|
8009740: 42a3 cmp r3, r4
|
|
8009742: d3f3 bcc.n 800972c <__mcmp+0x18>
|
|
8009744: e7fb b.n 800973e <__mcmp+0x2a>
|
|
8009746: 2001 movs r0, #1
|
|
8009748: e7f9 b.n 800973e <__mcmp+0x2a>
|
|
...
|
|
|
|
0800974c <__mdiff>:
|
|
800974c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8009750: 4689 mov r9, r1
|
|
8009752: 4606 mov r6, r0
|
|
8009754: 4611 mov r1, r2
|
|
8009756: 4648 mov r0, r9
|
|
8009758: 4614 mov r4, r2
|
|
800975a: f7ff ffdb bl 8009714 <__mcmp>
|
|
800975e: 1e05 subs r5, r0, #0
|
|
8009760: d112 bne.n 8009788 <__mdiff+0x3c>
|
|
8009762: 4629 mov r1, r5
|
|
8009764: 4630 mov r0, r6
|
|
8009766: f7ff fd63 bl 8009230 <_Balloc>
|
|
800976a: 4602 mov r2, r0
|
|
800976c: b928 cbnz r0, 800977a <__mdiff+0x2e>
|
|
800976e: 4b3f ldr r3, [pc, #252] @ (800986c <__mdiff+0x120>)
|
|
8009770: f240 2137 movw r1, #567 @ 0x237
|
|
8009774: 483e ldr r0, [pc, #248] @ (8009870 <__mdiff+0x124>)
|
|
8009776: f000 fb57 bl 8009e28 <__assert_func>
|
|
800977a: 2301 movs r3, #1
|
|
800977c: e9c0 3504 strd r3, r5, [r0, #16]
|
|
8009780: 4610 mov r0, r2
|
|
8009782: b003 add sp, #12
|
|
8009784: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8009788: bfbc itt lt
|
|
800978a: 464b movlt r3, r9
|
|
800978c: 46a1 movlt r9, r4
|
|
800978e: 4630 mov r0, r6
|
|
8009790: f8d9 1004 ldr.w r1, [r9, #4]
|
|
8009794: bfba itte lt
|
|
8009796: 461c movlt r4, r3
|
|
8009798: 2501 movlt r5, #1
|
|
800979a: 2500 movge r5, #0
|
|
800979c: f7ff fd48 bl 8009230 <_Balloc>
|
|
80097a0: 4602 mov r2, r0
|
|
80097a2: b918 cbnz r0, 80097ac <__mdiff+0x60>
|
|
80097a4: 4b31 ldr r3, [pc, #196] @ (800986c <__mdiff+0x120>)
|
|
80097a6: f240 2145 movw r1, #581 @ 0x245
|
|
80097aa: e7e3 b.n 8009774 <__mdiff+0x28>
|
|
80097ac: f8d9 7010 ldr.w r7, [r9, #16]
|
|
80097b0: 6926 ldr r6, [r4, #16]
|
|
80097b2: 60c5 str r5, [r0, #12]
|
|
80097b4: f109 0310 add.w r3, r9, #16
|
|
80097b8: f109 0514 add.w r5, r9, #20
|
|
80097bc: f104 0e14 add.w lr, r4, #20
|
|
80097c0: f100 0b14 add.w fp, r0, #20
|
|
80097c4: eb05 0887 add.w r8, r5, r7, lsl #2
|
|
80097c8: eb0e 0686 add.w r6, lr, r6, lsl #2
|
|
80097cc: 9301 str r3, [sp, #4]
|
|
80097ce: 46d9 mov r9, fp
|
|
80097d0: f04f 0c00 mov.w ip, #0
|
|
80097d4: 9b01 ldr r3, [sp, #4]
|
|
80097d6: f85e 0b04 ldr.w r0, [lr], #4
|
|
80097da: f853 af04 ldr.w sl, [r3, #4]!
|
|
80097de: 9301 str r3, [sp, #4]
|
|
80097e0: fa1f f38a uxth.w r3, sl
|
|
80097e4: 4619 mov r1, r3
|
|
80097e6: b283 uxth r3, r0
|
|
80097e8: 1acb subs r3, r1, r3
|
|
80097ea: 0c00 lsrs r0, r0, #16
|
|
80097ec: 4463 add r3, ip
|
|
80097ee: ebc0 401a rsb r0, r0, sl, lsr #16
|
|
80097f2: eb00 4023 add.w r0, r0, r3, asr #16
|
|
80097f6: b29b uxth r3, r3
|
|
80097f8: ea43 4300 orr.w r3, r3, r0, lsl #16
|
|
80097fc: 4576 cmp r6, lr
|
|
80097fe: f849 3b04 str.w r3, [r9], #4
|
|
8009802: ea4f 4c20 mov.w ip, r0, asr #16
|
|
8009806: d8e5 bhi.n 80097d4 <__mdiff+0x88>
|
|
8009808: 1b33 subs r3, r6, r4
|
|
800980a: 3b15 subs r3, #21
|
|
800980c: f023 0303 bic.w r3, r3, #3
|
|
8009810: 3415 adds r4, #21
|
|
8009812: 3304 adds r3, #4
|
|
8009814: 42a6 cmp r6, r4
|
|
8009816: bf38 it cc
|
|
8009818: 2304 movcc r3, #4
|
|
800981a: 441d add r5, r3
|
|
800981c: 445b add r3, fp
|
|
800981e: 461e mov r6, r3
|
|
8009820: 462c mov r4, r5
|
|
8009822: 4544 cmp r4, r8
|
|
8009824: d30e bcc.n 8009844 <__mdiff+0xf8>
|
|
8009826: f108 0103 add.w r1, r8, #3
|
|
800982a: 1b49 subs r1, r1, r5
|
|
800982c: f021 0103 bic.w r1, r1, #3
|
|
8009830: 3d03 subs r5, #3
|
|
8009832: 45a8 cmp r8, r5
|
|
8009834: bf38 it cc
|
|
8009836: 2100 movcc r1, #0
|
|
8009838: 440b add r3, r1
|
|
800983a: f853 1d04 ldr.w r1, [r3, #-4]!
|
|
800983e: b191 cbz r1, 8009866 <__mdiff+0x11a>
|
|
8009840: 6117 str r7, [r2, #16]
|
|
8009842: e79d b.n 8009780 <__mdiff+0x34>
|
|
8009844: f854 1b04 ldr.w r1, [r4], #4
|
|
8009848: 46e6 mov lr, ip
|
|
800984a: 0c08 lsrs r0, r1, #16
|
|
800984c: fa1c fc81 uxtah ip, ip, r1
|
|
8009850: 4471 add r1, lr
|
|
8009852: eb00 402c add.w r0, r0, ip, asr #16
|
|
8009856: b289 uxth r1, r1
|
|
8009858: ea41 4100 orr.w r1, r1, r0, lsl #16
|
|
800985c: f846 1b04 str.w r1, [r6], #4
|
|
8009860: ea4f 4c20 mov.w ip, r0, asr #16
|
|
8009864: e7dd b.n 8009822 <__mdiff+0xd6>
|
|
8009866: 3f01 subs r7, #1
|
|
8009868: e7e7 b.n 800983a <__mdiff+0xee>
|
|
800986a: bf00 nop
|
|
800986c: 0800a1d0 .word 0x0800a1d0
|
|
8009870: 0800a1e1 .word 0x0800a1e1
|
|
|
|
08009874 <__d2b>:
|
|
8009874: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
|
|
8009878: 460f mov r7, r1
|
|
800987a: 2101 movs r1, #1
|
|
800987c: ec59 8b10 vmov r8, r9, d0
|
|
8009880: 4616 mov r6, r2
|
|
8009882: f7ff fcd5 bl 8009230 <_Balloc>
|
|
8009886: 4604 mov r4, r0
|
|
8009888: b930 cbnz r0, 8009898 <__d2b+0x24>
|
|
800988a: 4602 mov r2, r0
|
|
800988c: 4b23 ldr r3, [pc, #140] @ (800991c <__d2b+0xa8>)
|
|
800988e: 4824 ldr r0, [pc, #144] @ (8009920 <__d2b+0xac>)
|
|
8009890: f240 310f movw r1, #783 @ 0x30f
|
|
8009894: f000 fac8 bl 8009e28 <__assert_func>
|
|
8009898: f3c9 550a ubfx r5, r9, #20, #11
|
|
800989c: f3c9 0313 ubfx r3, r9, #0, #20
|
|
80098a0: b10d cbz r5, 80098a6 <__d2b+0x32>
|
|
80098a2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
80098a6: 9301 str r3, [sp, #4]
|
|
80098a8: f1b8 0300 subs.w r3, r8, #0
|
|
80098ac: d023 beq.n 80098f6 <__d2b+0x82>
|
|
80098ae: 4668 mov r0, sp
|
|
80098b0: 9300 str r3, [sp, #0]
|
|
80098b2: f7ff fd84 bl 80093be <__lo0bits>
|
|
80098b6: e9dd 1200 ldrd r1, r2, [sp]
|
|
80098ba: b1d0 cbz r0, 80098f2 <__d2b+0x7e>
|
|
80098bc: f1c0 0320 rsb r3, r0, #32
|
|
80098c0: fa02 f303 lsl.w r3, r2, r3
|
|
80098c4: 430b orrs r3, r1
|
|
80098c6: 40c2 lsrs r2, r0
|
|
80098c8: 6163 str r3, [r4, #20]
|
|
80098ca: 9201 str r2, [sp, #4]
|
|
80098cc: 9b01 ldr r3, [sp, #4]
|
|
80098ce: 61a3 str r3, [r4, #24]
|
|
80098d0: 2b00 cmp r3, #0
|
|
80098d2: bf0c ite eq
|
|
80098d4: 2201 moveq r2, #1
|
|
80098d6: 2202 movne r2, #2
|
|
80098d8: 6122 str r2, [r4, #16]
|
|
80098da: b1a5 cbz r5, 8009906 <__d2b+0x92>
|
|
80098dc: f2a5 4533 subw r5, r5, #1075 @ 0x433
|
|
80098e0: 4405 add r5, r0
|
|
80098e2: 603d str r5, [r7, #0]
|
|
80098e4: f1c0 0035 rsb r0, r0, #53 @ 0x35
|
|
80098e8: 6030 str r0, [r6, #0]
|
|
80098ea: 4620 mov r0, r4
|
|
80098ec: b003 add sp, #12
|
|
80098ee: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
80098f2: 6161 str r1, [r4, #20]
|
|
80098f4: e7ea b.n 80098cc <__d2b+0x58>
|
|
80098f6: a801 add r0, sp, #4
|
|
80098f8: f7ff fd61 bl 80093be <__lo0bits>
|
|
80098fc: 9b01 ldr r3, [sp, #4]
|
|
80098fe: 6163 str r3, [r4, #20]
|
|
8009900: 3020 adds r0, #32
|
|
8009902: 2201 movs r2, #1
|
|
8009904: e7e8 b.n 80098d8 <__d2b+0x64>
|
|
8009906: eb04 0382 add.w r3, r4, r2, lsl #2
|
|
800990a: f2a0 4032 subw r0, r0, #1074 @ 0x432
|
|
800990e: 6038 str r0, [r7, #0]
|
|
8009910: 6918 ldr r0, [r3, #16]
|
|
8009912: f7ff fd35 bl 8009380 <__hi0bits>
|
|
8009916: ebc0 1042 rsb r0, r0, r2, lsl #5
|
|
800991a: e7e5 b.n 80098e8 <__d2b+0x74>
|
|
800991c: 0800a1d0 .word 0x0800a1d0
|
|
8009920: 0800a1e1 .word 0x0800a1e1
|
|
|
|
08009924 <__sfputc_r>:
|
|
8009924: 6893 ldr r3, [r2, #8]
|
|
8009926: 3b01 subs r3, #1
|
|
8009928: 2b00 cmp r3, #0
|
|
800992a: b410 push {r4}
|
|
800992c: 6093 str r3, [r2, #8]
|
|
800992e: da08 bge.n 8009942 <__sfputc_r+0x1e>
|
|
8009930: 6994 ldr r4, [r2, #24]
|
|
8009932: 42a3 cmp r3, r4
|
|
8009934: db01 blt.n 800993a <__sfputc_r+0x16>
|
|
8009936: 290a cmp r1, #10
|
|
8009938: d103 bne.n 8009942 <__sfputc_r+0x1e>
|
|
800993a: f85d 4b04 ldr.w r4, [sp], #4
|
|
800993e: f7fe bbfa b.w 8008136 <__swbuf_r>
|
|
8009942: 6813 ldr r3, [r2, #0]
|
|
8009944: 1c58 adds r0, r3, #1
|
|
8009946: 6010 str r0, [r2, #0]
|
|
8009948: 7019 strb r1, [r3, #0]
|
|
800994a: 4608 mov r0, r1
|
|
800994c: f85d 4b04 ldr.w r4, [sp], #4
|
|
8009950: 4770 bx lr
|
|
|
|
08009952 <__sfputs_r>:
|
|
8009952: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8009954: 4606 mov r6, r0
|
|
8009956: 460f mov r7, r1
|
|
8009958: 4614 mov r4, r2
|
|
800995a: 18d5 adds r5, r2, r3
|
|
800995c: 42ac cmp r4, r5
|
|
800995e: d101 bne.n 8009964 <__sfputs_r+0x12>
|
|
8009960: 2000 movs r0, #0
|
|
8009962: e007 b.n 8009974 <__sfputs_r+0x22>
|
|
8009964: f814 1b01 ldrb.w r1, [r4], #1
|
|
8009968: 463a mov r2, r7
|
|
800996a: 4630 mov r0, r6
|
|
800996c: f7ff ffda bl 8009924 <__sfputc_r>
|
|
8009970: 1c43 adds r3, r0, #1
|
|
8009972: d1f3 bne.n 800995c <__sfputs_r+0xa>
|
|
8009974: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
...
|
|
|
|
08009978 <_vfiprintf_r>:
|
|
8009978: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800997c: 460d mov r5, r1
|
|
800997e: b09d sub sp, #116 @ 0x74
|
|
8009980: 4614 mov r4, r2
|
|
8009982: 4698 mov r8, r3
|
|
8009984: 4606 mov r6, r0
|
|
8009986: b118 cbz r0, 8009990 <_vfiprintf_r+0x18>
|
|
8009988: 6a03 ldr r3, [r0, #32]
|
|
800998a: b90b cbnz r3, 8009990 <_vfiprintf_r+0x18>
|
|
800998c: f7fe faea bl 8007f64 <__sinit>
|
|
8009990: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8009992: 07d9 lsls r1, r3, #31
|
|
8009994: d405 bmi.n 80099a2 <_vfiprintf_r+0x2a>
|
|
8009996: 89ab ldrh r3, [r5, #12]
|
|
8009998: 059a lsls r2, r3, #22
|
|
800999a: d402 bmi.n 80099a2 <_vfiprintf_r+0x2a>
|
|
800999c: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
800999e: f7fe fcdc bl 800835a <__retarget_lock_acquire_recursive>
|
|
80099a2: 89ab ldrh r3, [r5, #12]
|
|
80099a4: 071b lsls r3, r3, #28
|
|
80099a6: d501 bpl.n 80099ac <_vfiprintf_r+0x34>
|
|
80099a8: 692b ldr r3, [r5, #16]
|
|
80099aa: b99b cbnz r3, 80099d4 <_vfiprintf_r+0x5c>
|
|
80099ac: 4629 mov r1, r5
|
|
80099ae: 4630 mov r0, r6
|
|
80099b0: f7fe fc00 bl 80081b4 <__swsetup_r>
|
|
80099b4: b170 cbz r0, 80099d4 <_vfiprintf_r+0x5c>
|
|
80099b6: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
80099b8: 07dc lsls r4, r3, #31
|
|
80099ba: d504 bpl.n 80099c6 <_vfiprintf_r+0x4e>
|
|
80099bc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80099c0: b01d add sp, #116 @ 0x74
|
|
80099c2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80099c6: 89ab ldrh r3, [r5, #12]
|
|
80099c8: 0598 lsls r0, r3, #22
|
|
80099ca: d4f7 bmi.n 80099bc <_vfiprintf_r+0x44>
|
|
80099cc: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
80099ce: f7fe fcc5 bl 800835c <__retarget_lock_release_recursive>
|
|
80099d2: e7f3 b.n 80099bc <_vfiprintf_r+0x44>
|
|
80099d4: 2300 movs r3, #0
|
|
80099d6: 9309 str r3, [sp, #36] @ 0x24
|
|
80099d8: 2320 movs r3, #32
|
|
80099da: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
80099de: f8cd 800c str.w r8, [sp, #12]
|
|
80099e2: 2330 movs r3, #48 @ 0x30
|
|
80099e4: f8df 81ac ldr.w r8, [pc, #428] @ 8009b94 <_vfiprintf_r+0x21c>
|
|
80099e8: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
80099ec: f04f 0901 mov.w r9, #1
|
|
80099f0: 4623 mov r3, r4
|
|
80099f2: 469a mov sl, r3
|
|
80099f4: f813 2b01 ldrb.w r2, [r3], #1
|
|
80099f8: b10a cbz r2, 80099fe <_vfiprintf_r+0x86>
|
|
80099fa: 2a25 cmp r2, #37 @ 0x25
|
|
80099fc: d1f9 bne.n 80099f2 <_vfiprintf_r+0x7a>
|
|
80099fe: ebba 0b04 subs.w fp, sl, r4
|
|
8009a02: d00b beq.n 8009a1c <_vfiprintf_r+0xa4>
|
|
8009a04: 465b mov r3, fp
|
|
8009a06: 4622 mov r2, r4
|
|
8009a08: 4629 mov r1, r5
|
|
8009a0a: 4630 mov r0, r6
|
|
8009a0c: f7ff ffa1 bl 8009952 <__sfputs_r>
|
|
8009a10: 3001 adds r0, #1
|
|
8009a12: f000 80a7 beq.w 8009b64 <_vfiprintf_r+0x1ec>
|
|
8009a16: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8009a18: 445a add r2, fp
|
|
8009a1a: 9209 str r2, [sp, #36] @ 0x24
|
|
8009a1c: f89a 3000 ldrb.w r3, [sl]
|
|
8009a20: 2b00 cmp r3, #0
|
|
8009a22: f000 809f beq.w 8009b64 <_vfiprintf_r+0x1ec>
|
|
8009a26: 2300 movs r3, #0
|
|
8009a28: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8009a2c: e9cd 2305 strd r2, r3, [sp, #20]
|
|
8009a30: f10a 0a01 add.w sl, sl, #1
|
|
8009a34: 9304 str r3, [sp, #16]
|
|
8009a36: 9307 str r3, [sp, #28]
|
|
8009a38: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
8009a3c: 931a str r3, [sp, #104] @ 0x68
|
|
8009a3e: 4654 mov r4, sl
|
|
8009a40: 2205 movs r2, #5
|
|
8009a42: f814 1b01 ldrb.w r1, [r4], #1
|
|
8009a46: 4853 ldr r0, [pc, #332] @ (8009b94 <_vfiprintf_r+0x21c>)
|
|
8009a48: f7f6 fbc2 bl 80001d0 <memchr>
|
|
8009a4c: 9a04 ldr r2, [sp, #16]
|
|
8009a4e: b9d8 cbnz r0, 8009a88 <_vfiprintf_r+0x110>
|
|
8009a50: 06d1 lsls r1, r2, #27
|
|
8009a52: bf44 itt mi
|
|
8009a54: 2320 movmi r3, #32
|
|
8009a56: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8009a5a: 0713 lsls r3, r2, #28
|
|
8009a5c: bf44 itt mi
|
|
8009a5e: 232b movmi r3, #43 @ 0x2b
|
|
8009a60: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8009a64: f89a 3000 ldrb.w r3, [sl]
|
|
8009a68: 2b2a cmp r3, #42 @ 0x2a
|
|
8009a6a: d015 beq.n 8009a98 <_vfiprintf_r+0x120>
|
|
8009a6c: 9a07 ldr r2, [sp, #28]
|
|
8009a6e: 4654 mov r4, sl
|
|
8009a70: 2000 movs r0, #0
|
|
8009a72: f04f 0c0a mov.w ip, #10
|
|
8009a76: 4621 mov r1, r4
|
|
8009a78: f811 3b01 ldrb.w r3, [r1], #1
|
|
8009a7c: 3b30 subs r3, #48 @ 0x30
|
|
8009a7e: 2b09 cmp r3, #9
|
|
8009a80: d94b bls.n 8009b1a <_vfiprintf_r+0x1a2>
|
|
8009a82: b1b0 cbz r0, 8009ab2 <_vfiprintf_r+0x13a>
|
|
8009a84: 9207 str r2, [sp, #28]
|
|
8009a86: e014 b.n 8009ab2 <_vfiprintf_r+0x13a>
|
|
8009a88: eba0 0308 sub.w r3, r0, r8
|
|
8009a8c: fa09 f303 lsl.w r3, r9, r3
|
|
8009a90: 4313 orrs r3, r2
|
|
8009a92: 9304 str r3, [sp, #16]
|
|
8009a94: 46a2 mov sl, r4
|
|
8009a96: e7d2 b.n 8009a3e <_vfiprintf_r+0xc6>
|
|
8009a98: 9b03 ldr r3, [sp, #12]
|
|
8009a9a: 1d19 adds r1, r3, #4
|
|
8009a9c: 681b ldr r3, [r3, #0]
|
|
8009a9e: 9103 str r1, [sp, #12]
|
|
8009aa0: 2b00 cmp r3, #0
|
|
8009aa2: bfbb ittet lt
|
|
8009aa4: 425b neglt r3, r3
|
|
8009aa6: f042 0202 orrlt.w r2, r2, #2
|
|
8009aaa: 9307 strge r3, [sp, #28]
|
|
8009aac: 9307 strlt r3, [sp, #28]
|
|
8009aae: bfb8 it lt
|
|
8009ab0: 9204 strlt r2, [sp, #16]
|
|
8009ab2: 7823 ldrb r3, [r4, #0]
|
|
8009ab4: 2b2e cmp r3, #46 @ 0x2e
|
|
8009ab6: d10a bne.n 8009ace <_vfiprintf_r+0x156>
|
|
8009ab8: 7863 ldrb r3, [r4, #1]
|
|
8009aba: 2b2a cmp r3, #42 @ 0x2a
|
|
8009abc: d132 bne.n 8009b24 <_vfiprintf_r+0x1ac>
|
|
8009abe: 9b03 ldr r3, [sp, #12]
|
|
8009ac0: 1d1a adds r2, r3, #4
|
|
8009ac2: 681b ldr r3, [r3, #0]
|
|
8009ac4: 9203 str r2, [sp, #12]
|
|
8009ac6: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
8009aca: 3402 adds r4, #2
|
|
8009acc: 9305 str r3, [sp, #20]
|
|
8009ace: f8df a0d4 ldr.w sl, [pc, #212] @ 8009ba4 <_vfiprintf_r+0x22c>
|
|
8009ad2: 7821 ldrb r1, [r4, #0]
|
|
8009ad4: 2203 movs r2, #3
|
|
8009ad6: 4650 mov r0, sl
|
|
8009ad8: f7f6 fb7a bl 80001d0 <memchr>
|
|
8009adc: b138 cbz r0, 8009aee <_vfiprintf_r+0x176>
|
|
8009ade: 9b04 ldr r3, [sp, #16]
|
|
8009ae0: eba0 000a sub.w r0, r0, sl
|
|
8009ae4: 2240 movs r2, #64 @ 0x40
|
|
8009ae6: 4082 lsls r2, r0
|
|
8009ae8: 4313 orrs r3, r2
|
|
8009aea: 3401 adds r4, #1
|
|
8009aec: 9304 str r3, [sp, #16]
|
|
8009aee: f814 1b01 ldrb.w r1, [r4], #1
|
|
8009af2: 4829 ldr r0, [pc, #164] @ (8009b98 <_vfiprintf_r+0x220>)
|
|
8009af4: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
8009af8: 2206 movs r2, #6
|
|
8009afa: f7f6 fb69 bl 80001d0 <memchr>
|
|
8009afe: 2800 cmp r0, #0
|
|
8009b00: d03f beq.n 8009b82 <_vfiprintf_r+0x20a>
|
|
8009b02: 4b26 ldr r3, [pc, #152] @ (8009b9c <_vfiprintf_r+0x224>)
|
|
8009b04: bb1b cbnz r3, 8009b4e <_vfiprintf_r+0x1d6>
|
|
8009b06: 9b03 ldr r3, [sp, #12]
|
|
8009b08: 3307 adds r3, #7
|
|
8009b0a: f023 0307 bic.w r3, r3, #7
|
|
8009b0e: 3308 adds r3, #8
|
|
8009b10: 9303 str r3, [sp, #12]
|
|
8009b12: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8009b14: 443b add r3, r7
|
|
8009b16: 9309 str r3, [sp, #36] @ 0x24
|
|
8009b18: e76a b.n 80099f0 <_vfiprintf_r+0x78>
|
|
8009b1a: fb0c 3202 mla r2, ip, r2, r3
|
|
8009b1e: 460c mov r4, r1
|
|
8009b20: 2001 movs r0, #1
|
|
8009b22: e7a8 b.n 8009a76 <_vfiprintf_r+0xfe>
|
|
8009b24: 2300 movs r3, #0
|
|
8009b26: 3401 adds r4, #1
|
|
8009b28: 9305 str r3, [sp, #20]
|
|
8009b2a: 4619 mov r1, r3
|
|
8009b2c: f04f 0c0a mov.w ip, #10
|
|
8009b30: 4620 mov r0, r4
|
|
8009b32: f810 2b01 ldrb.w r2, [r0], #1
|
|
8009b36: 3a30 subs r2, #48 @ 0x30
|
|
8009b38: 2a09 cmp r2, #9
|
|
8009b3a: d903 bls.n 8009b44 <_vfiprintf_r+0x1cc>
|
|
8009b3c: 2b00 cmp r3, #0
|
|
8009b3e: d0c6 beq.n 8009ace <_vfiprintf_r+0x156>
|
|
8009b40: 9105 str r1, [sp, #20]
|
|
8009b42: e7c4 b.n 8009ace <_vfiprintf_r+0x156>
|
|
8009b44: fb0c 2101 mla r1, ip, r1, r2
|
|
8009b48: 4604 mov r4, r0
|
|
8009b4a: 2301 movs r3, #1
|
|
8009b4c: e7f0 b.n 8009b30 <_vfiprintf_r+0x1b8>
|
|
8009b4e: ab03 add r3, sp, #12
|
|
8009b50: 9300 str r3, [sp, #0]
|
|
8009b52: 462a mov r2, r5
|
|
8009b54: 4b12 ldr r3, [pc, #72] @ (8009ba0 <_vfiprintf_r+0x228>)
|
|
8009b56: a904 add r1, sp, #16
|
|
8009b58: 4630 mov r0, r6
|
|
8009b5a: f7fd fdc1 bl 80076e0 <_printf_float>
|
|
8009b5e: 4607 mov r7, r0
|
|
8009b60: 1c78 adds r0, r7, #1
|
|
8009b62: d1d6 bne.n 8009b12 <_vfiprintf_r+0x19a>
|
|
8009b64: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8009b66: 07d9 lsls r1, r3, #31
|
|
8009b68: d405 bmi.n 8009b76 <_vfiprintf_r+0x1fe>
|
|
8009b6a: 89ab ldrh r3, [r5, #12]
|
|
8009b6c: 059a lsls r2, r3, #22
|
|
8009b6e: d402 bmi.n 8009b76 <_vfiprintf_r+0x1fe>
|
|
8009b70: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8009b72: f7fe fbf3 bl 800835c <__retarget_lock_release_recursive>
|
|
8009b76: 89ab ldrh r3, [r5, #12]
|
|
8009b78: 065b lsls r3, r3, #25
|
|
8009b7a: f53f af1f bmi.w 80099bc <_vfiprintf_r+0x44>
|
|
8009b7e: 9809 ldr r0, [sp, #36] @ 0x24
|
|
8009b80: e71e b.n 80099c0 <_vfiprintf_r+0x48>
|
|
8009b82: ab03 add r3, sp, #12
|
|
8009b84: 9300 str r3, [sp, #0]
|
|
8009b86: 462a mov r2, r5
|
|
8009b88: 4b05 ldr r3, [pc, #20] @ (8009ba0 <_vfiprintf_r+0x228>)
|
|
8009b8a: a904 add r1, sp, #16
|
|
8009b8c: 4630 mov r0, r6
|
|
8009b8e: f7fe f83f bl 8007c10 <_printf_i>
|
|
8009b92: e7e4 b.n 8009b5e <_vfiprintf_r+0x1e6>
|
|
8009b94: 0800a23a .word 0x0800a23a
|
|
8009b98: 0800a244 .word 0x0800a244
|
|
8009b9c: 080076e1 .word 0x080076e1
|
|
8009ba0: 08009953 .word 0x08009953
|
|
8009ba4: 0800a240 .word 0x0800a240
|
|
|
|
08009ba8 <__sflush_r>:
|
|
8009ba8: f9b1 200c ldrsh.w r2, [r1, #12]
|
|
8009bac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8009bb0: 0716 lsls r6, r2, #28
|
|
8009bb2: 4605 mov r5, r0
|
|
8009bb4: 460c mov r4, r1
|
|
8009bb6: d454 bmi.n 8009c62 <__sflush_r+0xba>
|
|
8009bb8: 684b ldr r3, [r1, #4]
|
|
8009bba: 2b00 cmp r3, #0
|
|
8009bbc: dc02 bgt.n 8009bc4 <__sflush_r+0x1c>
|
|
8009bbe: 6c0b ldr r3, [r1, #64] @ 0x40
|
|
8009bc0: 2b00 cmp r3, #0
|
|
8009bc2: dd48 ble.n 8009c56 <__sflush_r+0xae>
|
|
8009bc4: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
8009bc6: 2e00 cmp r6, #0
|
|
8009bc8: d045 beq.n 8009c56 <__sflush_r+0xae>
|
|
8009bca: 2300 movs r3, #0
|
|
8009bcc: f412 5280 ands.w r2, r2, #4096 @ 0x1000
|
|
8009bd0: 682f ldr r7, [r5, #0]
|
|
8009bd2: 6a21 ldr r1, [r4, #32]
|
|
8009bd4: 602b str r3, [r5, #0]
|
|
8009bd6: d030 beq.n 8009c3a <__sflush_r+0x92>
|
|
8009bd8: 6d62 ldr r2, [r4, #84] @ 0x54
|
|
8009bda: 89a3 ldrh r3, [r4, #12]
|
|
8009bdc: 0759 lsls r1, r3, #29
|
|
8009bde: d505 bpl.n 8009bec <__sflush_r+0x44>
|
|
8009be0: 6863 ldr r3, [r4, #4]
|
|
8009be2: 1ad2 subs r2, r2, r3
|
|
8009be4: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
8009be6: b10b cbz r3, 8009bec <__sflush_r+0x44>
|
|
8009be8: 6c23 ldr r3, [r4, #64] @ 0x40
|
|
8009bea: 1ad2 subs r2, r2, r3
|
|
8009bec: 2300 movs r3, #0
|
|
8009bee: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
8009bf0: 6a21 ldr r1, [r4, #32]
|
|
8009bf2: 4628 mov r0, r5
|
|
8009bf4: 47b0 blx r6
|
|
8009bf6: 1c43 adds r3, r0, #1
|
|
8009bf8: 89a3 ldrh r3, [r4, #12]
|
|
8009bfa: d106 bne.n 8009c0a <__sflush_r+0x62>
|
|
8009bfc: 6829 ldr r1, [r5, #0]
|
|
8009bfe: 291d cmp r1, #29
|
|
8009c00: d82b bhi.n 8009c5a <__sflush_r+0xb2>
|
|
8009c02: 4a2a ldr r2, [pc, #168] @ (8009cac <__sflush_r+0x104>)
|
|
8009c04: 40ca lsrs r2, r1
|
|
8009c06: 07d6 lsls r6, r2, #31
|
|
8009c08: d527 bpl.n 8009c5a <__sflush_r+0xb2>
|
|
8009c0a: 2200 movs r2, #0
|
|
8009c0c: 6062 str r2, [r4, #4]
|
|
8009c0e: 04d9 lsls r1, r3, #19
|
|
8009c10: 6922 ldr r2, [r4, #16]
|
|
8009c12: 6022 str r2, [r4, #0]
|
|
8009c14: d504 bpl.n 8009c20 <__sflush_r+0x78>
|
|
8009c16: 1c42 adds r2, r0, #1
|
|
8009c18: d101 bne.n 8009c1e <__sflush_r+0x76>
|
|
8009c1a: 682b ldr r3, [r5, #0]
|
|
8009c1c: b903 cbnz r3, 8009c20 <__sflush_r+0x78>
|
|
8009c1e: 6560 str r0, [r4, #84] @ 0x54
|
|
8009c20: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
8009c22: 602f str r7, [r5, #0]
|
|
8009c24: b1b9 cbz r1, 8009c56 <__sflush_r+0xae>
|
|
8009c26: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
8009c2a: 4299 cmp r1, r3
|
|
8009c2c: d002 beq.n 8009c34 <__sflush_r+0x8c>
|
|
8009c2e: 4628 mov r0, r5
|
|
8009c30: f7ff f9fe bl 8009030 <_free_r>
|
|
8009c34: 2300 movs r3, #0
|
|
8009c36: 6363 str r3, [r4, #52] @ 0x34
|
|
8009c38: e00d b.n 8009c56 <__sflush_r+0xae>
|
|
8009c3a: 2301 movs r3, #1
|
|
8009c3c: 4628 mov r0, r5
|
|
8009c3e: 47b0 blx r6
|
|
8009c40: 4602 mov r2, r0
|
|
8009c42: 1c50 adds r0, r2, #1
|
|
8009c44: d1c9 bne.n 8009bda <__sflush_r+0x32>
|
|
8009c46: 682b ldr r3, [r5, #0]
|
|
8009c48: 2b00 cmp r3, #0
|
|
8009c4a: d0c6 beq.n 8009bda <__sflush_r+0x32>
|
|
8009c4c: 2b1d cmp r3, #29
|
|
8009c4e: d001 beq.n 8009c54 <__sflush_r+0xac>
|
|
8009c50: 2b16 cmp r3, #22
|
|
8009c52: d11e bne.n 8009c92 <__sflush_r+0xea>
|
|
8009c54: 602f str r7, [r5, #0]
|
|
8009c56: 2000 movs r0, #0
|
|
8009c58: e022 b.n 8009ca0 <__sflush_r+0xf8>
|
|
8009c5a: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8009c5e: b21b sxth r3, r3
|
|
8009c60: e01b b.n 8009c9a <__sflush_r+0xf2>
|
|
8009c62: 690f ldr r7, [r1, #16]
|
|
8009c64: 2f00 cmp r7, #0
|
|
8009c66: d0f6 beq.n 8009c56 <__sflush_r+0xae>
|
|
8009c68: 0793 lsls r3, r2, #30
|
|
8009c6a: 680e ldr r6, [r1, #0]
|
|
8009c6c: bf08 it eq
|
|
8009c6e: 694b ldreq r3, [r1, #20]
|
|
8009c70: 600f str r7, [r1, #0]
|
|
8009c72: bf18 it ne
|
|
8009c74: 2300 movne r3, #0
|
|
8009c76: eba6 0807 sub.w r8, r6, r7
|
|
8009c7a: 608b str r3, [r1, #8]
|
|
8009c7c: f1b8 0f00 cmp.w r8, #0
|
|
8009c80: dde9 ble.n 8009c56 <__sflush_r+0xae>
|
|
8009c82: 6a21 ldr r1, [r4, #32]
|
|
8009c84: 6aa6 ldr r6, [r4, #40] @ 0x28
|
|
8009c86: 4643 mov r3, r8
|
|
8009c88: 463a mov r2, r7
|
|
8009c8a: 4628 mov r0, r5
|
|
8009c8c: 47b0 blx r6
|
|
8009c8e: 2800 cmp r0, #0
|
|
8009c90: dc08 bgt.n 8009ca4 <__sflush_r+0xfc>
|
|
8009c92: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8009c96: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8009c9a: 81a3 strh r3, [r4, #12]
|
|
8009c9c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8009ca0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
8009ca4: 4407 add r7, r0
|
|
8009ca6: eba8 0800 sub.w r8, r8, r0
|
|
8009caa: e7e7 b.n 8009c7c <__sflush_r+0xd4>
|
|
8009cac: 20400001 .word 0x20400001
|
|
|
|
08009cb0 <_fflush_r>:
|
|
8009cb0: b538 push {r3, r4, r5, lr}
|
|
8009cb2: 690b ldr r3, [r1, #16]
|
|
8009cb4: 4605 mov r5, r0
|
|
8009cb6: 460c mov r4, r1
|
|
8009cb8: b913 cbnz r3, 8009cc0 <_fflush_r+0x10>
|
|
8009cba: 2500 movs r5, #0
|
|
8009cbc: 4628 mov r0, r5
|
|
8009cbe: bd38 pop {r3, r4, r5, pc}
|
|
8009cc0: b118 cbz r0, 8009cca <_fflush_r+0x1a>
|
|
8009cc2: 6a03 ldr r3, [r0, #32]
|
|
8009cc4: b90b cbnz r3, 8009cca <_fflush_r+0x1a>
|
|
8009cc6: f7fe f94d bl 8007f64 <__sinit>
|
|
8009cca: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8009cce: 2b00 cmp r3, #0
|
|
8009cd0: d0f3 beq.n 8009cba <_fflush_r+0xa>
|
|
8009cd2: 6e62 ldr r2, [r4, #100] @ 0x64
|
|
8009cd4: 07d0 lsls r0, r2, #31
|
|
8009cd6: d404 bmi.n 8009ce2 <_fflush_r+0x32>
|
|
8009cd8: 0599 lsls r1, r3, #22
|
|
8009cda: d402 bmi.n 8009ce2 <_fflush_r+0x32>
|
|
8009cdc: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8009cde: f7fe fb3c bl 800835a <__retarget_lock_acquire_recursive>
|
|
8009ce2: 4628 mov r0, r5
|
|
8009ce4: 4621 mov r1, r4
|
|
8009ce6: f7ff ff5f bl 8009ba8 <__sflush_r>
|
|
8009cea: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
8009cec: 07da lsls r2, r3, #31
|
|
8009cee: 4605 mov r5, r0
|
|
8009cf0: d4e4 bmi.n 8009cbc <_fflush_r+0xc>
|
|
8009cf2: 89a3 ldrh r3, [r4, #12]
|
|
8009cf4: 059b lsls r3, r3, #22
|
|
8009cf6: d4e1 bmi.n 8009cbc <_fflush_r+0xc>
|
|
8009cf8: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8009cfa: f7fe fb2f bl 800835c <__retarget_lock_release_recursive>
|
|
8009cfe: e7dd b.n 8009cbc <_fflush_r+0xc>
|
|
|
|
08009d00 <__swhatbuf_r>:
|
|
8009d00: b570 push {r4, r5, r6, lr}
|
|
8009d02: 460c mov r4, r1
|
|
8009d04: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
8009d08: 2900 cmp r1, #0
|
|
8009d0a: b096 sub sp, #88 @ 0x58
|
|
8009d0c: 4615 mov r5, r2
|
|
8009d0e: 461e mov r6, r3
|
|
8009d10: da0d bge.n 8009d2e <__swhatbuf_r+0x2e>
|
|
8009d12: 89a3 ldrh r3, [r4, #12]
|
|
8009d14: f013 0f80 tst.w r3, #128 @ 0x80
|
|
8009d18: f04f 0100 mov.w r1, #0
|
|
8009d1c: bf14 ite ne
|
|
8009d1e: 2340 movne r3, #64 @ 0x40
|
|
8009d20: f44f 6380 moveq.w r3, #1024 @ 0x400
|
|
8009d24: 2000 movs r0, #0
|
|
8009d26: 6031 str r1, [r6, #0]
|
|
8009d28: 602b str r3, [r5, #0]
|
|
8009d2a: b016 add sp, #88 @ 0x58
|
|
8009d2c: bd70 pop {r4, r5, r6, pc}
|
|
8009d2e: 466a mov r2, sp
|
|
8009d30: f000 f848 bl 8009dc4 <_fstat_r>
|
|
8009d34: 2800 cmp r0, #0
|
|
8009d36: dbec blt.n 8009d12 <__swhatbuf_r+0x12>
|
|
8009d38: 9901 ldr r1, [sp, #4]
|
|
8009d3a: f401 4170 and.w r1, r1, #61440 @ 0xf000
|
|
8009d3e: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
|
|
8009d42: 4259 negs r1, r3
|
|
8009d44: 4159 adcs r1, r3
|
|
8009d46: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8009d4a: e7eb b.n 8009d24 <__swhatbuf_r+0x24>
|
|
|
|
08009d4c <__smakebuf_r>:
|
|
8009d4c: 898b ldrh r3, [r1, #12]
|
|
8009d4e: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
8009d50: 079d lsls r5, r3, #30
|
|
8009d52: 4606 mov r6, r0
|
|
8009d54: 460c mov r4, r1
|
|
8009d56: d507 bpl.n 8009d68 <__smakebuf_r+0x1c>
|
|
8009d58: f104 0347 add.w r3, r4, #71 @ 0x47
|
|
8009d5c: 6023 str r3, [r4, #0]
|
|
8009d5e: 6123 str r3, [r4, #16]
|
|
8009d60: 2301 movs r3, #1
|
|
8009d62: 6163 str r3, [r4, #20]
|
|
8009d64: b003 add sp, #12
|
|
8009d66: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8009d68: ab01 add r3, sp, #4
|
|
8009d6a: 466a mov r2, sp
|
|
8009d6c: f7ff ffc8 bl 8009d00 <__swhatbuf_r>
|
|
8009d70: 9f00 ldr r7, [sp, #0]
|
|
8009d72: 4605 mov r5, r0
|
|
8009d74: 4639 mov r1, r7
|
|
8009d76: 4630 mov r0, r6
|
|
8009d78: f7ff f9ce bl 8009118 <_malloc_r>
|
|
8009d7c: b948 cbnz r0, 8009d92 <__smakebuf_r+0x46>
|
|
8009d7e: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8009d82: 059a lsls r2, r3, #22
|
|
8009d84: d4ee bmi.n 8009d64 <__smakebuf_r+0x18>
|
|
8009d86: f023 0303 bic.w r3, r3, #3
|
|
8009d8a: f043 0302 orr.w r3, r3, #2
|
|
8009d8e: 81a3 strh r3, [r4, #12]
|
|
8009d90: e7e2 b.n 8009d58 <__smakebuf_r+0xc>
|
|
8009d92: 89a3 ldrh r3, [r4, #12]
|
|
8009d94: 6020 str r0, [r4, #0]
|
|
8009d96: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8009d9a: 81a3 strh r3, [r4, #12]
|
|
8009d9c: 9b01 ldr r3, [sp, #4]
|
|
8009d9e: e9c4 0704 strd r0, r7, [r4, #16]
|
|
8009da2: b15b cbz r3, 8009dbc <__smakebuf_r+0x70>
|
|
8009da4: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
8009da8: 4630 mov r0, r6
|
|
8009daa: f000 f81d bl 8009de8 <_isatty_r>
|
|
8009dae: b128 cbz r0, 8009dbc <__smakebuf_r+0x70>
|
|
8009db0: 89a3 ldrh r3, [r4, #12]
|
|
8009db2: f023 0303 bic.w r3, r3, #3
|
|
8009db6: f043 0301 orr.w r3, r3, #1
|
|
8009dba: 81a3 strh r3, [r4, #12]
|
|
8009dbc: 89a3 ldrh r3, [r4, #12]
|
|
8009dbe: 431d orrs r5, r3
|
|
8009dc0: 81a5 strh r5, [r4, #12]
|
|
8009dc2: e7cf b.n 8009d64 <__smakebuf_r+0x18>
|
|
|
|
08009dc4 <_fstat_r>:
|
|
8009dc4: b538 push {r3, r4, r5, lr}
|
|
8009dc6: 4d07 ldr r5, [pc, #28] @ (8009de4 <_fstat_r+0x20>)
|
|
8009dc8: 2300 movs r3, #0
|
|
8009dca: 4604 mov r4, r0
|
|
8009dcc: 4608 mov r0, r1
|
|
8009dce: 4611 mov r1, r2
|
|
8009dd0: 602b str r3, [r5, #0]
|
|
8009dd2: f7f9 f919 bl 8003008 <_fstat>
|
|
8009dd6: 1c43 adds r3, r0, #1
|
|
8009dd8: d102 bne.n 8009de0 <_fstat_r+0x1c>
|
|
8009dda: 682b ldr r3, [r5, #0]
|
|
8009ddc: b103 cbz r3, 8009de0 <_fstat_r+0x1c>
|
|
8009dde: 6023 str r3, [r4, #0]
|
|
8009de0: bd38 pop {r3, r4, r5, pc}
|
|
8009de2: bf00 nop
|
|
8009de4: 20000bb4 .word 0x20000bb4
|
|
|
|
08009de8 <_isatty_r>:
|
|
8009de8: b538 push {r3, r4, r5, lr}
|
|
8009dea: 4d06 ldr r5, [pc, #24] @ (8009e04 <_isatty_r+0x1c>)
|
|
8009dec: 2300 movs r3, #0
|
|
8009dee: 4604 mov r4, r0
|
|
8009df0: 4608 mov r0, r1
|
|
8009df2: 602b str r3, [r5, #0]
|
|
8009df4: f7f9 f918 bl 8003028 <_isatty>
|
|
8009df8: 1c43 adds r3, r0, #1
|
|
8009dfa: d102 bne.n 8009e02 <_isatty_r+0x1a>
|
|
8009dfc: 682b ldr r3, [r5, #0]
|
|
8009dfe: b103 cbz r3, 8009e02 <_isatty_r+0x1a>
|
|
8009e00: 6023 str r3, [r4, #0]
|
|
8009e02: bd38 pop {r3, r4, r5, pc}
|
|
8009e04: 20000bb4 .word 0x20000bb4
|
|
|
|
08009e08 <_sbrk_r>:
|
|
8009e08: b538 push {r3, r4, r5, lr}
|
|
8009e0a: 4d06 ldr r5, [pc, #24] @ (8009e24 <_sbrk_r+0x1c>)
|
|
8009e0c: 2300 movs r3, #0
|
|
8009e0e: 4604 mov r4, r0
|
|
8009e10: 4608 mov r0, r1
|
|
8009e12: 602b str r3, [r5, #0]
|
|
8009e14: f7f9 f920 bl 8003058 <_sbrk>
|
|
8009e18: 1c43 adds r3, r0, #1
|
|
8009e1a: d102 bne.n 8009e22 <_sbrk_r+0x1a>
|
|
8009e1c: 682b ldr r3, [r5, #0]
|
|
8009e1e: b103 cbz r3, 8009e22 <_sbrk_r+0x1a>
|
|
8009e20: 6023 str r3, [r4, #0]
|
|
8009e22: bd38 pop {r3, r4, r5, pc}
|
|
8009e24: 20000bb4 .word 0x20000bb4
|
|
|
|
08009e28 <__assert_func>:
|
|
8009e28: b51f push {r0, r1, r2, r3, r4, lr}
|
|
8009e2a: 4614 mov r4, r2
|
|
8009e2c: 461a mov r2, r3
|
|
8009e2e: 4b09 ldr r3, [pc, #36] @ (8009e54 <__assert_func+0x2c>)
|
|
8009e30: 681b ldr r3, [r3, #0]
|
|
8009e32: 4605 mov r5, r0
|
|
8009e34: 68d8 ldr r0, [r3, #12]
|
|
8009e36: b14c cbz r4, 8009e4c <__assert_func+0x24>
|
|
8009e38: 4b07 ldr r3, [pc, #28] @ (8009e58 <__assert_func+0x30>)
|
|
8009e3a: 9100 str r1, [sp, #0]
|
|
8009e3c: e9cd 3401 strd r3, r4, [sp, #4]
|
|
8009e40: 4906 ldr r1, [pc, #24] @ (8009e5c <__assert_func+0x34>)
|
|
8009e42: 462b mov r3, r5
|
|
8009e44: f000 f842 bl 8009ecc <fiprintf>
|
|
8009e48: f000 f852 bl 8009ef0 <abort>
|
|
8009e4c: 4b04 ldr r3, [pc, #16] @ (8009e60 <__assert_func+0x38>)
|
|
8009e4e: 461c mov r4, r3
|
|
8009e50: e7f3 b.n 8009e3a <__assert_func+0x12>
|
|
8009e52: bf00 nop
|
|
8009e54: 200000dc .word 0x200000dc
|
|
8009e58: 0800a255 .word 0x0800a255
|
|
8009e5c: 0800a262 .word 0x0800a262
|
|
8009e60: 0800a290 .word 0x0800a290
|
|
|
|
08009e64 <_calloc_r>:
|
|
8009e64: b570 push {r4, r5, r6, lr}
|
|
8009e66: fba1 5402 umull r5, r4, r1, r2
|
|
8009e6a: b934 cbnz r4, 8009e7a <_calloc_r+0x16>
|
|
8009e6c: 4629 mov r1, r5
|
|
8009e6e: f7ff f953 bl 8009118 <_malloc_r>
|
|
8009e72: 4606 mov r6, r0
|
|
8009e74: b928 cbnz r0, 8009e82 <_calloc_r+0x1e>
|
|
8009e76: 4630 mov r0, r6
|
|
8009e78: bd70 pop {r4, r5, r6, pc}
|
|
8009e7a: 220c movs r2, #12
|
|
8009e7c: 6002 str r2, [r0, #0]
|
|
8009e7e: 2600 movs r6, #0
|
|
8009e80: e7f9 b.n 8009e76 <_calloc_r+0x12>
|
|
8009e82: 462a mov r2, r5
|
|
8009e84: 4621 mov r1, r4
|
|
8009e86: f7fe f9eb bl 8008260 <memset>
|
|
8009e8a: e7f4 b.n 8009e76 <_calloc_r+0x12>
|
|
|
|
08009e8c <__ascii_mbtowc>:
|
|
8009e8c: b082 sub sp, #8
|
|
8009e8e: b901 cbnz r1, 8009e92 <__ascii_mbtowc+0x6>
|
|
8009e90: a901 add r1, sp, #4
|
|
8009e92: b142 cbz r2, 8009ea6 <__ascii_mbtowc+0x1a>
|
|
8009e94: b14b cbz r3, 8009eaa <__ascii_mbtowc+0x1e>
|
|
8009e96: 7813 ldrb r3, [r2, #0]
|
|
8009e98: 600b str r3, [r1, #0]
|
|
8009e9a: 7812 ldrb r2, [r2, #0]
|
|
8009e9c: 1e10 subs r0, r2, #0
|
|
8009e9e: bf18 it ne
|
|
8009ea0: 2001 movne r0, #1
|
|
8009ea2: b002 add sp, #8
|
|
8009ea4: 4770 bx lr
|
|
8009ea6: 4610 mov r0, r2
|
|
8009ea8: e7fb b.n 8009ea2 <__ascii_mbtowc+0x16>
|
|
8009eaa: f06f 0001 mvn.w r0, #1
|
|
8009eae: e7f8 b.n 8009ea2 <__ascii_mbtowc+0x16>
|
|
|
|
08009eb0 <__ascii_wctomb>:
|
|
8009eb0: 4603 mov r3, r0
|
|
8009eb2: 4608 mov r0, r1
|
|
8009eb4: b141 cbz r1, 8009ec8 <__ascii_wctomb+0x18>
|
|
8009eb6: 2aff cmp r2, #255 @ 0xff
|
|
8009eb8: d904 bls.n 8009ec4 <__ascii_wctomb+0x14>
|
|
8009eba: 228a movs r2, #138 @ 0x8a
|
|
8009ebc: 601a str r2, [r3, #0]
|
|
8009ebe: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8009ec2: 4770 bx lr
|
|
8009ec4: 700a strb r2, [r1, #0]
|
|
8009ec6: 2001 movs r0, #1
|
|
8009ec8: 4770 bx lr
|
|
...
|
|
|
|
08009ecc <fiprintf>:
|
|
8009ecc: b40e push {r1, r2, r3}
|
|
8009ece: b503 push {r0, r1, lr}
|
|
8009ed0: 4601 mov r1, r0
|
|
8009ed2: ab03 add r3, sp, #12
|
|
8009ed4: 4805 ldr r0, [pc, #20] @ (8009eec <fiprintf+0x20>)
|
|
8009ed6: f853 2b04 ldr.w r2, [r3], #4
|
|
8009eda: 6800 ldr r0, [r0, #0]
|
|
8009edc: 9301 str r3, [sp, #4]
|
|
8009ede: f7ff fd4b bl 8009978 <_vfiprintf_r>
|
|
8009ee2: b002 add sp, #8
|
|
8009ee4: f85d eb04 ldr.w lr, [sp], #4
|
|
8009ee8: b003 add sp, #12
|
|
8009eea: 4770 bx lr
|
|
8009eec: 200000dc .word 0x200000dc
|
|
|
|
08009ef0 <abort>:
|
|
8009ef0: b508 push {r3, lr}
|
|
8009ef2: 2006 movs r0, #6
|
|
8009ef4: f000 f82c bl 8009f50 <raise>
|
|
8009ef8: 2001 movs r0, #1
|
|
8009efa: f7f9 f835 bl 8002f68 <_exit>
|
|
|
|
08009efe <_raise_r>:
|
|
8009efe: 291f cmp r1, #31
|
|
8009f00: b538 push {r3, r4, r5, lr}
|
|
8009f02: 4605 mov r5, r0
|
|
8009f04: 460c mov r4, r1
|
|
8009f06: d904 bls.n 8009f12 <_raise_r+0x14>
|
|
8009f08: 2316 movs r3, #22
|
|
8009f0a: 6003 str r3, [r0, #0]
|
|
8009f0c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8009f10: bd38 pop {r3, r4, r5, pc}
|
|
8009f12: 6bc2 ldr r2, [r0, #60] @ 0x3c
|
|
8009f14: b112 cbz r2, 8009f1c <_raise_r+0x1e>
|
|
8009f16: f852 3021 ldr.w r3, [r2, r1, lsl #2]
|
|
8009f1a: b94b cbnz r3, 8009f30 <_raise_r+0x32>
|
|
8009f1c: 4628 mov r0, r5
|
|
8009f1e: f000 f831 bl 8009f84 <_getpid_r>
|
|
8009f22: 4622 mov r2, r4
|
|
8009f24: 4601 mov r1, r0
|
|
8009f26: 4628 mov r0, r5
|
|
8009f28: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8009f2c: f000 b818 b.w 8009f60 <_kill_r>
|
|
8009f30: 2b01 cmp r3, #1
|
|
8009f32: d00a beq.n 8009f4a <_raise_r+0x4c>
|
|
8009f34: 1c59 adds r1, r3, #1
|
|
8009f36: d103 bne.n 8009f40 <_raise_r+0x42>
|
|
8009f38: 2316 movs r3, #22
|
|
8009f3a: 6003 str r3, [r0, #0]
|
|
8009f3c: 2001 movs r0, #1
|
|
8009f3e: e7e7 b.n 8009f10 <_raise_r+0x12>
|
|
8009f40: 2100 movs r1, #0
|
|
8009f42: f842 1024 str.w r1, [r2, r4, lsl #2]
|
|
8009f46: 4620 mov r0, r4
|
|
8009f48: 4798 blx r3
|
|
8009f4a: 2000 movs r0, #0
|
|
8009f4c: e7e0 b.n 8009f10 <_raise_r+0x12>
|
|
...
|
|
|
|
08009f50 <raise>:
|
|
8009f50: 4b02 ldr r3, [pc, #8] @ (8009f5c <raise+0xc>)
|
|
8009f52: 4601 mov r1, r0
|
|
8009f54: 6818 ldr r0, [r3, #0]
|
|
8009f56: f7ff bfd2 b.w 8009efe <_raise_r>
|
|
8009f5a: bf00 nop
|
|
8009f5c: 200000dc .word 0x200000dc
|
|
|
|
08009f60 <_kill_r>:
|
|
8009f60: b538 push {r3, r4, r5, lr}
|
|
8009f62: 4d07 ldr r5, [pc, #28] @ (8009f80 <_kill_r+0x20>)
|
|
8009f64: 2300 movs r3, #0
|
|
8009f66: 4604 mov r4, r0
|
|
8009f68: 4608 mov r0, r1
|
|
8009f6a: 4611 mov r1, r2
|
|
8009f6c: 602b str r3, [r5, #0]
|
|
8009f6e: f7f8 ffeb bl 8002f48 <_kill>
|
|
8009f72: 1c43 adds r3, r0, #1
|
|
8009f74: d102 bne.n 8009f7c <_kill_r+0x1c>
|
|
8009f76: 682b ldr r3, [r5, #0]
|
|
8009f78: b103 cbz r3, 8009f7c <_kill_r+0x1c>
|
|
8009f7a: 6023 str r3, [r4, #0]
|
|
8009f7c: bd38 pop {r3, r4, r5, pc}
|
|
8009f7e: bf00 nop
|
|
8009f80: 20000bb4 .word 0x20000bb4
|
|
|
|
08009f84 <_getpid_r>:
|
|
8009f84: f7f8 bfd8 b.w 8002f38 <_getpid>
|
|
|
|
08009f88 <_init>:
|
|
8009f88: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8009f8a: bf00 nop
|
|
8009f8c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8009f8e: bc08 pop {r3}
|
|
8009f90: 469e mov lr, r3
|
|
8009f92: 4770 bx lr
|
|
|
|
08009f94 <_fini>:
|
|
8009f94: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8009f96: bf00 nop
|
|
8009f98: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8009f9a: bc08 pop {r3}
|
|
8009f9c: 469e mov lr, r3
|
|
8009f9e: 4770 bx lr
|