Gallardo7761/setr2-monorepo
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b9c332427df3991ef2b30e18dbcae29973c1aedb
setr2-monorepo/P1_SETR2/Debug/P1_SETR2.list
Jose 580d746aeb Add: P1 SETR2
2025-10-09 19:35:22 +02:00

13126 lines
497 KiB
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P1_SETR2.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00004b40 08000188 08000188 00001188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000048 08004cc8 08004cc8 00005cc8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08004d10 08004d10 00006010 2**0
CONTENTS, READONLY
4 .ARM 00000008 08004d10 08004d10 00005d10 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08004d18 08004d18 00006010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08004d18 08004d18 00005d18 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08004d1c 08004d1c 00005d1c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000010 20000000 08004d20 00006000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000774 20000010 08004d30 00006010 2**2
ALLOC
10 ._user_heap_stack 00000604 20000784 08004d30 00006784 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00006010 2**0
CONTENTS, READONLY
12 .debug_info 000175dc 00000000 00000000 00006040 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003018 00000000 00000000 0001d61c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000015c8 00000000 00000000 00020638 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000010df 00000000 00000000 00021c00 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0002771e 00000000 00000000 00022cdf 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00018b7c 00000000 00000000 0004a3fd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000efc51 00000000 00000000 00062f79 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 00152bca 2**0
CONTENTS, READONLY
20 .debug_frame 00005cf0 00000000 00000000 00152c10 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000061 00000000 00000000 00158900 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 20000010 .word 0x20000010
80001a4: 00000000 .word 0x00000000
80001a8: 08004cb0 .word 0x08004cb0
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000014 .word 0x20000014
80001c4: 08004cb0 .word 0x08004cb0
080001c8 <__aeabi_uldivmod>:
80001c8: b953 cbnz r3, 80001e0 <__aeabi_uldivmod+0x18>
80001ca: b94a cbnz r2, 80001e0 <__aeabi_uldivmod+0x18>
80001cc: 2900 cmp r1, #0
80001ce: bf08 it eq
80001d0: 2800 cmpeq r0, #0
80001d2: bf1c itt ne
80001d4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
80001d8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
80001dc: f000 b988 b.w 80004f0 <__aeabi_idiv0>
80001e0: f1ad 0c08 sub.w ip, sp, #8
80001e4: e96d ce04 strd ip, lr, [sp, #-16]!
80001e8: f000 f806 bl 80001f8 <__udivmoddi4>
80001ec: f8dd e004 ldr.w lr, [sp, #4]
80001f0: e9dd 2302 ldrd r2, r3, [sp, #8]
80001f4: b004 add sp, #16
80001f6: 4770 bx lr
080001f8 <__udivmoddi4>:
80001f8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80001fc: 9d08 ldr r5, [sp, #32]
80001fe: 468e mov lr, r1
8000200: 4604 mov r4, r0
8000202: 4688 mov r8, r1
8000204: 2b00 cmp r3, #0
8000206: d14a bne.n 800029e <__udivmoddi4+0xa6>
8000208: 428a cmp r2, r1
800020a: 4617 mov r7, r2
800020c: d962 bls.n 80002d4 <__udivmoddi4+0xdc>
800020e: fab2 f682 clz r6, r2
8000212: b14e cbz r6, 8000228 <__udivmoddi4+0x30>
8000214: f1c6 0320 rsb r3, r6, #32
8000218: fa01 f806 lsl.w r8, r1, r6
800021c: fa20 f303 lsr.w r3, r0, r3
8000220: 40b7 lsls r7, r6
8000222: ea43 0808 orr.w r8, r3, r8
8000226: 40b4 lsls r4, r6
8000228: ea4f 4e17 mov.w lr, r7, lsr #16
800022c: fa1f fc87 uxth.w ip, r7
8000230: fbb8 f1fe udiv r1, r8, lr
8000234: 0c23 lsrs r3, r4, #16
8000236: fb0e 8811 mls r8, lr, r1, r8
800023a: ea43 4308 orr.w r3, r3, r8, lsl #16
800023e: fb01 f20c mul.w r2, r1, ip
8000242: 429a cmp r2, r3
8000244: d909 bls.n 800025a <__udivmoddi4+0x62>
8000246: 18fb adds r3, r7, r3
8000248: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
800024c: f080 80ea bcs.w 8000424 <__udivmoddi4+0x22c>
8000250: 429a cmp r2, r3
8000252: f240 80e7 bls.w 8000424 <__udivmoddi4+0x22c>
8000256: 3902 subs r1, #2
8000258: 443b add r3, r7
800025a: 1a9a subs r2, r3, r2
800025c: b2a3 uxth r3, r4
800025e: fbb2 f0fe udiv r0, r2, lr
8000262: fb0e 2210 mls r2, lr, r0, r2
8000266: ea43 4302 orr.w r3, r3, r2, lsl #16
800026a: fb00 fc0c mul.w ip, r0, ip
800026e: 459c cmp ip, r3
8000270: d909 bls.n 8000286 <__udivmoddi4+0x8e>
8000272: 18fb adds r3, r7, r3
8000274: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
8000278: f080 80d6 bcs.w 8000428 <__udivmoddi4+0x230>
800027c: 459c cmp ip, r3
800027e: f240 80d3 bls.w 8000428 <__udivmoddi4+0x230>
8000282: 443b add r3, r7
8000284: 3802 subs r0, #2
8000286: ea40 4001 orr.w r0, r0, r1, lsl #16
800028a: eba3 030c sub.w r3, r3, ip
800028e: 2100 movs r1, #0
8000290: b11d cbz r5, 800029a <__udivmoddi4+0xa2>
8000292: 40f3 lsrs r3, r6
8000294: 2200 movs r2, #0
8000296: e9c5 3200 strd r3, r2, [r5]
800029a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800029e: 428b cmp r3, r1
80002a0: d905 bls.n 80002ae <__udivmoddi4+0xb6>
80002a2: b10d cbz r5, 80002a8 <__udivmoddi4+0xb0>
80002a4: e9c5 0100 strd r0, r1, [r5]
80002a8: 2100 movs r1, #0
80002aa: 4608 mov r0, r1
80002ac: e7f5 b.n 800029a <__udivmoddi4+0xa2>
80002ae: fab3 f183 clz r1, r3
80002b2: 2900 cmp r1, #0
80002b4: d146 bne.n 8000344 <__udivmoddi4+0x14c>
80002b6: 4573 cmp r3, lr
80002b8: d302 bcc.n 80002c0 <__udivmoddi4+0xc8>
80002ba: 4282 cmp r2, r0
80002bc: f200 8105 bhi.w 80004ca <__udivmoddi4+0x2d2>
80002c0: 1a84 subs r4, r0, r2
80002c2: eb6e 0203 sbc.w r2, lr, r3
80002c6: 2001 movs r0, #1
80002c8: 4690 mov r8, r2
80002ca: 2d00 cmp r5, #0
80002cc: d0e5 beq.n 800029a <__udivmoddi4+0xa2>
80002ce: e9c5 4800 strd r4, r8, [r5]
80002d2: e7e2 b.n 800029a <__udivmoddi4+0xa2>
80002d4: 2a00 cmp r2, #0
80002d6: f000 8090 beq.w 80003fa <__udivmoddi4+0x202>
80002da: fab2 f682 clz r6, r2
80002de: 2e00 cmp r6, #0
80002e0: f040 80a4 bne.w 800042c <__udivmoddi4+0x234>
80002e4: 1a8a subs r2, r1, r2
80002e6: 0c03 lsrs r3, r0, #16
80002e8: ea4f 4e17 mov.w lr, r7, lsr #16
80002ec: b280 uxth r0, r0
80002ee: b2bc uxth r4, r7
80002f0: 2101 movs r1, #1
80002f2: fbb2 fcfe udiv ip, r2, lr
80002f6: fb0e 221c mls r2, lr, ip, r2
80002fa: ea43 4302 orr.w r3, r3, r2, lsl #16
80002fe: fb04 f20c mul.w r2, r4, ip
8000302: 429a cmp r2, r3
8000304: d907 bls.n 8000316 <__udivmoddi4+0x11e>
8000306: 18fb adds r3, r7, r3
8000308: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
800030c: d202 bcs.n 8000314 <__udivmoddi4+0x11c>
800030e: 429a cmp r2, r3
8000310: f200 80e0 bhi.w 80004d4 <__udivmoddi4+0x2dc>
8000314: 46c4 mov ip, r8
8000316: 1a9b subs r3, r3, r2
8000318: fbb3 f2fe udiv r2, r3, lr
800031c: fb0e 3312 mls r3, lr, r2, r3
8000320: ea40 4303 orr.w r3, r0, r3, lsl #16
8000324: fb02 f404 mul.w r4, r2, r4
8000328: 429c cmp r4, r3
800032a: d907 bls.n 800033c <__udivmoddi4+0x144>
800032c: 18fb adds r3, r7, r3
800032e: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
8000332: d202 bcs.n 800033a <__udivmoddi4+0x142>
8000334: 429c cmp r4, r3
8000336: f200 80ca bhi.w 80004ce <__udivmoddi4+0x2d6>
800033a: 4602 mov r2, r0
800033c: 1b1b subs r3, r3, r4
800033e: ea42 400c orr.w r0, r2, ip, lsl #16
8000342: e7a5 b.n 8000290 <__udivmoddi4+0x98>
8000344: f1c1 0620 rsb r6, r1, #32
8000348: 408b lsls r3, r1
800034a: fa22 f706 lsr.w r7, r2, r6
800034e: 431f orrs r7, r3
8000350: fa0e f401 lsl.w r4, lr, r1
8000354: fa20 f306 lsr.w r3, r0, r6
8000358: fa2e fe06 lsr.w lr, lr, r6
800035c: ea4f 4917 mov.w r9, r7, lsr #16
8000360: 4323 orrs r3, r4
8000362: fa00 f801 lsl.w r8, r0, r1
8000366: fa1f fc87 uxth.w ip, r7
800036a: fbbe f0f9 udiv r0, lr, r9
800036e: 0c1c lsrs r4, r3, #16
8000370: fb09 ee10 mls lr, r9, r0, lr
8000374: ea44 440e orr.w r4, r4, lr, lsl #16
8000378: fb00 fe0c mul.w lr, r0, ip
800037c: 45a6 cmp lr, r4
800037e: fa02 f201 lsl.w r2, r2, r1
8000382: d909 bls.n 8000398 <__udivmoddi4+0x1a0>
8000384: 193c adds r4, r7, r4
8000386: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
800038a: f080 809c bcs.w 80004c6 <__udivmoddi4+0x2ce>
800038e: 45a6 cmp lr, r4
8000390: f240 8099 bls.w 80004c6 <__udivmoddi4+0x2ce>
8000394: 3802 subs r0, #2
8000396: 443c add r4, r7
8000398: eba4 040e sub.w r4, r4, lr
800039c: fa1f fe83 uxth.w lr, r3
80003a0: fbb4 f3f9 udiv r3, r4, r9
80003a4: fb09 4413 mls r4, r9, r3, r4
80003a8: ea4e 4404 orr.w r4, lr, r4, lsl #16
80003ac: fb03 fc0c mul.w ip, r3, ip
80003b0: 45a4 cmp ip, r4
80003b2: d908 bls.n 80003c6 <__udivmoddi4+0x1ce>
80003b4: 193c adds r4, r7, r4
80003b6: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
80003ba: f080 8082 bcs.w 80004c2 <__udivmoddi4+0x2ca>
80003be: 45a4 cmp ip, r4
80003c0: d97f bls.n 80004c2 <__udivmoddi4+0x2ca>
80003c2: 3b02 subs r3, #2
80003c4: 443c add r4, r7
80003c6: ea43 4000 orr.w r0, r3, r0, lsl #16
80003ca: eba4 040c sub.w r4, r4, ip
80003ce: fba0 ec02 umull lr, ip, r0, r2
80003d2: 4564 cmp r4, ip
80003d4: 4673 mov r3, lr
80003d6: 46e1 mov r9, ip
80003d8: d362 bcc.n 80004a0 <__udivmoddi4+0x2a8>
80003da: d05f beq.n 800049c <__udivmoddi4+0x2a4>
80003dc: b15d cbz r5, 80003f6 <__udivmoddi4+0x1fe>
80003de: ebb8 0203 subs.w r2, r8, r3
80003e2: eb64 0409 sbc.w r4, r4, r9
80003e6: fa04 f606 lsl.w r6, r4, r6
80003ea: fa22 f301 lsr.w r3, r2, r1
80003ee: 431e orrs r6, r3
80003f0: 40cc lsrs r4, r1
80003f2: e9c5 6400 strd r6, r4, [r5]
80003f6: 2100 movs r1, #0
80003f8: e74f b.n 800029a <__udivmoddi4+0xa2>
80003fa: fbb1 fcf2 udiv ip, r1, r2
80003fe: 0c01 lsrs r1, r0, #16
8000400: ea41 410e orr.w r1, r1, lr, lsl #16
8000404: b280 uxth r0, r0
8000406: ea40 4201 orr.w r2, r0, r1, lsl #16
800040a: 463b mov r3, r7
800040c: 4638 mov r0, r7
800040e: 463c mov r4, r7
8000410: 46b8 mov r8, r7
8000412: 46be mov lr, r7
8000414: 2620 movs r6, #32
8000416: fbb1 f1f7 udiv r1, r1, r7
800041a: eba2 0208 sub.w r2, r2, r8
800041e: ea41 410c orr.w r1, r1, ip, lsl #16
8000422: e766 b.n 80002f2 <__udivmoddi4+0xfa>
8000424: 4601 mov r1, r0
8000426: e718 b.n 800025a <__udivmoddi4+0x62>
8000428: 4610 mov r0, r2
800042a: e72c b.n 8000286 <__udivmoddi4+0x8e>
800042c: f1c6 0220 rsb r2, r6, #32
8000430: fa2e f302 lsr.w r3, lr, r2
8000434: 40b7 lsls r7, r6
8000436: 40b1 lsls r1, r6
8000438: fa20 f202 lsr.w r2, r0, r2
800043c: ea4f 4e17 mov.w lr, r7, lsr #16
8000440: 430a orrs r2, r1
8000442: fbb3 f8fe udiv r8, r3, lr
8000446: b2bc uxth r4, r7
8000448: fb0e 3318 mls r3, lr, r8, r3
800044c: 0c11 lsrs r1, r2, #16
800044e: ea41 4103 orr.w r1, r1, r3, lsl #16
8000452: fb08 f904 mul.w r9, r8, r4
8000456: 40b0 lsls r0, r6
8000458: 4589 cmp r9, r1
800045a: ea4f 4310 mov.w r3, r0, lsr #16
800045e: b280 uxth r0, r0
8000460: d93e bls.n 80004e0 <__udivmoddi4+0x2e8>
8000462: 1879 adds r1, r7, r1
8000464: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000468: d201 bcs.n 800046e <__udivmoddi4+0x276>
800046a: 4589 cmp r9, r1
800046c: d81f bhi.n 80004ae <__udivmoddi4+0x2b6>
800046e: eba1 0109 sub.w r1, r1, r9
8000472: fbb1 f9fe udiv r9, r1, lr
8000476: fb09 f804 mul.w r8, r9, r4
800047a: fb0e 1119 mls r1, lr, r9, r1
800047e: b292 uxth r2, r2
8000480: ea42 4201 orr.w r2, r2, r1, lsl #16
8000484: 4542 cmp r2, r8
8000486: d229 bcs.n 80004dc <__udivmoddi4+0x2e4>
8000488: 18ba adds r2, r7, r2
800048a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
800048e: d2c4 bcs.n 800041a <__udivmoddi4+0x222>
8000490: 4542 cmp r2, r8
8000492: d2c2 bcs.n 800041a <__udivmoddi4+0x222>
8000494: f1a9 0102 sub.w r1, r9, #2
8000498: 443a add r2, r7
800049a: e7be b.n 800041a <__udivmoddi4+0x222>
800049c: 45f0 cmp r8, lr
800049e: d29d bcs.n 80003dc <__udivmoddi4+0x1e4>
80004a0: ebbe 0302 subs.w r3, lr, r2
80004a4: eb6c 0c07 sbc.w ip, ip, r7
80004a8: 3801 subs r0, #1
80004aa: 46e1 mov r9, ip
80004ac: e796 b.n 80003dc <__udivmoddi4+0x1e4>
80004ae: eba7 0909 sub.w r9, r7, r9
80004b2: 4449 add r1, r9
80004b4: f1a8 0c02 sub.w ip, r8, #2
80004b8: fbb1 f9fe udiv r9, r1, lr
80004bc: fb09 f804 mul.w r8, r9, r4
80004c0: e7db b.n 800047a <__udivmoddi4+0x282>
80004c2: 4673 mov r3, lr
80004c4: e77f b.n 80003c6 <__udivmoddi4+0x1ce>
80004c6: 4650 mov r0, sl
80004c8: e766 b.n 8000398 <__udivmoddi4+0x1a0>
80004ca: 4608 mov r0, r1
80004cc: e6fd b.n 80002ca <__udivmoddi4+0xd2>
80004ce: 443b add r3, r7
80004d0: 3a02 subs r2, #2
80004d2: e733 b.n 800033c <__udivmoddi4+0x144>
80004d4: f1ac 0c02 sub.w ip, ip, #2
80004d8: 443b add r3, r7
80004da: e71c b.n 8000316 <__udivmoddi4+0x11e>
80004dc: 4649 mov r1, r9
80004de: e79c b.n 800041a <__udivmoddi4+0x222>
80004e0: eba1 0109 sub.w r1, r1, r9
80004e4: 46c4 mov ip, r8
80004e6: fbb1 f9fe udiv r9, r1, lr
80004ea: fb09 f804 mul.w r8, r9, r4
80004ee: e7c4 b.n 800047a <__udivmoddi4+0x282>
080004f0 <__aeabi_idiv0>:
80004f0: 4770 bx lr
80004f2: bf00 nop
080004f4 <ReadJoy>:
static uint8_t previous_state = GPIO_PIN_SET;
static uint8_t virtual_button = 0;
uint8_t ReadJoy(void)
{
80004f4: b580 push {r7, lr}
80004f6: b082 sub sp, #8
80004f8: af00 add r7, sp, #0
GPIO_PinState current_state = HAL_GPIO_ReadPin(GPIOC, GPIO_PIN_13);
80004fa: f44f 5100 mov.w r1, #8192 @ 0x2000
80004fe: 4813 ldr r0, [pc, #76] @ (800054c <ReadJoy+0x58>)
8000500: f001 fc74 bl 8001dec <HAL_GPIO_ReadPin>
8000504: 4603 mov r3, r0
8000506: 71fb strb r3, [r7, #7]
if (previous_state == GPIO_PIN_SET && current_state == GPIO_PIN_RESET)
8000508: 4b11 ldr r3, [pc, #68] @ (8000550 <ReadJoy+0x5c>)
800050a: 781b ldrb r3, [r3, #0]
800050c: 2b01 cmp r3, #1
800050e: d10f bne.n 8000530 <ReadJoy+0x3c>
8000510: 79fb ldrb r3, [r7, #7]
8000512: 2b00 cmp r3, #0
8000514: d10c bne.n 8000530 <ReadJoy+0x3c>
{
virtual_button++;
8000516: 4b0f ldr r3, [pc, #60] @ (8000554 <ReadJoy+0x60>)
8000518: 781b ldrb r3, [r3, #0]
800051a: 3301 adds r3, #1
800051c: b2da uxtb r2, r3
800051e: 4b0d ldr r3, [pc, #52] @ (8000554 <ReadJoy+0x60>)
8000520: 701a strb r2, [r3, #0]
if (virtual_button > 4) virtual_button = 1;
8000522: 4b0c ldr r3, [pc, #48] @ (8000554 <ReadJoy+0x60>)
8000524: 781b ldrb r3, [r3, #0]
8000526: 2b04 cmp r3, #4
8000528: d902 bls.n 8000530 <ReadJoy+0x3c>
800052a: 4b0a ldr r3, [pc, #40] @ (8000554 <ReadJoy+0x60>)
800052c: 2201 movs r2, #1
800052e: 701a strb r2, [r3, #0]
}
previous_state = current_state;
8000530: 4a07 ldr r2, [pc, #28] @ (8000550 <ReadJoy+0x5c>)
8000532: 79fb ldrb r3, [r7, #7]
8000534: 7013 strb r3, [r2, #0]
if (current_state == GPIO_PIN_RESET) return virtual_button;
8000536: 79fb ldrb r3, [r7, #7]
8000538: 2b00 cmp r3, #0
800053a: d102 bne.n 8000542 <ReadJoy+0x4e>
800053c: 4b05 ldr r3, [pc, #20] @ (8000554 <ReadJoy+0x60>)
800053e: 781b ldrb r3, [r3, #0]
8000540: e000 b.n 8000544 <ReadJoy+0x50>
else return 0;
8000542: 2300 movs r3, #0
}
8000544: 4618 mov r0, r3
8000546: 3708 adds r7, #8
8000548: 46bd mov sp, r7
800054a: bd80 pop {r7, pc}
800054c: 48000800 .word 0x48000800
8000550: 20000000 .word 0x20000000
8000554: 2000002c .word 0x2000002c
08000558 <LED_On>:
*/
#include "led_driver.h"
void LED_On(uint8_t led)
{
8000558: b580 push {r7, lr}
800055a: b082 sub sp, #8
800055c: af00 add r7, sp, #0
800055e: 4603 mov r3, r0
8000560: 71fb strb r3, [r7, #7]
switch(led)
8000562: 79fb ldrb r3, [r7, #7]
8000564: 2b02 cmp r3, #2
8000566: d014 beq.n 8000592 <LED_On+0x3a>
8000568: 2b02 cmp r3, #2
800056a: dc19 bgt.n 80005a0 <LED_On+0x48>
800056c: 2b00 cmp r3, #0
800056e: d002 beq.n 8000576 <LED_On+0x1e>
8000570: 2b01 cmp r3, #1
8000572: d007 beq.n 8000584 <LED_On+0x2c>
break;
case 2:
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET);
break;
}
}
8000574: e014 b.n 80005a0 <LED_On+0x48>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
8000576: 2201 movs r2, #1
8000578: 2120 movs r1, #32
800057a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800057e: f001 fc4d bl 8001e1c <HAL_GPIO_WritePin>
break;
8000582: e00d b.n 80005a0 <LED_On+0x48>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET);
8000584: 2201 movs r2, #1
8000586: f44f 4180 mov.w r1, #16384 @ 0x4000
800058a: 4807 ldr r0, [pc, #28] @ (80005a8 <LED_On+0x50>)
800058c: f001 fc46 bl 8001e1c <HAL_GPIO_WritePin>
break;
8000590: e006 b.n 80005a0 <LED_On+0x48>
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET);
8000592: 2201 movs r2, #1
8000594: f44f 7100 mov.w r1, #512 @ 0x200
8000598: 4804 ldr r0, [pc, #16] @ (80005ac <LED_On+0x54>)
800059a: f001 fc3f bl 8001e1c <HAL_GPIO_WritePin>
break;
800059e: bf00 nop
}
80005a0: bf00 nop
80005a2: 3708 adds r7, #8
80005a4: 46bd mov sp, r7
80005a6: bd80 pop {r7, pc}
80005a8: 48000400 .word 0x48000400
80005ac: 48000800 .word 0x48000800
080005b0 <LED_Off>:
void LED_Off(uint8_t led)
{
80005b0: b580 push {r7, lr}
80005b2: b082 sub sp, #8
80005b4: af00 add r7, sp, #0
80005b6: 4603 mov r3, r0
80005b8: 71fb strb r3, [r7, #7]
switch(led)
80005ba: 79fb ldrb r3, [r7, #7]
80005bc: 2b02 cmp r3, #2
80005be: d014 beq.n 80005ea <LED_Off+0x3a>
80005c0: 2b02 cmp r3, #2
80005c2: dc19 bgt.n 80005f8 <LED_Off+0x48>
80005c4: 2b00 cmp r3, #0
80005c6: d002 beq.n 80005ce <LED_Off+0x1e>
80005c8: 2b01 cmp r3, #1
80005ca: d007 beq.n 80005dc <LED_Off+0x2c>
break;
case 2:
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_RESET);
break;
}
}
80005cc: e014 b.n 80005f8 <LED_Off+0x48>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
80005ce: 2200 movs r2, #0
80005d0: 2120 movs r1, #32
80005d2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80005d6: f001 fc21 bl 8001e1c <HAL_GPIO_WritePin>
break;
80005da: e00d b.n 80005f8 <LED_Off+0x48>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET);
80005dc: 2200 movs r2, #0
80005de: f44f 4180 mov.w r1, #16384 @ 0x4000
80005e2: 4807 ldr r0, [pc, #28] @ (8000600 <LED_Off+0x50>)
80005e4: f001 fc1a bl 8001e1c <HAL_GPIO_WritePin>
break;
80005e8: e006 b.n 80005f8 <LED_Off+0x48>
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_RESET);
80005ea: 2200 movs r2, #0
80005ec: f44f 7100 mov.w r1, #512 @ 0x200
80005f0: 4804 ldr r0, [pc, #16] @ (8000604 <LED_Off+0x54>)
80005f2: f001 fc13 bl 8001e1c <HAL_GPIO_WritePin>
break;
80005f6: bf00 nop
}
80005f8: bf00 nop
80005fa: 3708 adds r7, #8
80005fc: 46bd mov sp, r7
80005fe: bd80 pop {r7, pc}
8000600: 48000400 .word 0x48000400
8000604: 48000800 .word 0x48000800
08000608 <animation1>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void animation1(void){
8000608: b580 push {r7, lr}
800060a: b082 sub sp, #8
800060c: af00 add r7, sp, #0
int i;
for(i = 0; i < 3; i++){
800060e: 2300 movs r3, #0
8000610: 607b str r3, [r7, #4]
8000612: e00f b.n 8000634 <animation1+0x2c>
LED_On(i);
8000614: 687b ldr r3, [r7, #4]
8000616: b2db uxtb r3, r3
8000618: 4618 mov r0, r3
800061a: f7ff ff9d bl 8000558 <LED_On>
HAL_Delay(150);
800061e: 2096 movs r0, #150 @ 0x96
8000620: f000 fff8 bl 8001614 <HAL_Delay>
LED_Off(i);
8000624: 687b ldr r3, [r7, #4]
8000626: b2db uxtb r3, r3
8000628: 4618 mov r0, r3
800062a: f7ff ffc1 bl 80005b0 <LED_Off>
for(i = 0; i < 3; i++){
800062e: 687b ldr r3, [r7, #4]
8000630: 3301 adds r3, #1
8000632: 607b str r3, [r7, #4]
8000634: 687b ldr r3, [r7, #4]
8000636: 2b02 cmp r3, #2
8000638: ddec ble.n 8000614 <animation1+0xc>
}
for(i = 1; i > 0; i--){
800063a: 2301 movs r3, #1
800063c: 607b str r3, [r7, #4]
800063e: e00f b.n 8000660 <animation1+0x58>
LED_On(i);
8000640: 687b ldr r3, [r7, #4]
8000642: b2db uxtb r3, r3
8000644: 4618 mov r0, r3
8000646: f7ff ff87 bl 8000558 <LED_On>
HAL_Delay(150);
800064a: 2096 movs r0, #150 @ 0x96
800064c: f000 ffe2 bl 8001614 <HAL_Delay>
LED_Off(i);
8000650: 687b ldr r3, [r7, #4]
8000652: b2db uxtb r3, r3
8000654: 4618 mov r0, r3
8000656: f7ff ffab bl 80005b0 <LED_Off>
for(i = 1; i > 0; i--){
800065a: 687b ldr r3, [r7, #4]
800065c: 3b01 subs r3, #1
800065e: 607b str r3, [r7, #4]
8000660: 687b ldr r3, [r7, #4]
8000662: 2b00 cmp r3, #0
8000664: dcec bgt.n 8000640 <animation1+0x38>
}
}
8000666: bf00 nop
8000668: bf00 nop
800066a: 3708 adds r7, #8
800066c: 46bd mov sp, r7
800066e: bd80 pop {r7, pc}
08000670 <animation2>:
void animation2(void){
8000670: b580 push {r7, lr}
8000672: b082 sub sp, #8
8000674: af00 add r7, sp, #0
int i, j;
for(j = 0; j < 5; j++){
8000676: 2300 movs r3, #0
8000678: 603b str r3, [r7, #0]
800067a: e024 b.n 80006c6 <animation2+0x56>
for(i = 0; i < 3; i++)
800067c: 2300 movs r3, #0
800067e: 607b str r3, [r7, #4]
8000680: e007 b.n 8000692 <animation2+0x22>
LED_On(i);
8000682: 687b ldr r3, [r7, #4]
8000684: b2db uxtb r3, r3
8000686: 4618 mov r0, r3
8000688: f7ff ff66 bl 8000558 <LED_On>
for(i = 0; i < 3; i++)
800068c: 687b ldr r3, [r7, #4]
800068e: 3301 adds r3, #1
8000690: 607b str r3, [r7, #4]
8000692: 687b ldr r3, [r7, #4]
8000694: 2b02 cmp r3, #2
8000696: ddf4 ble.n 8000682 <animation2+0x12>
HAL_Delay(100);
8000698: 2064 movs r0, #100 @ 0x64
800069a: f000 ffbb bl 8001614 <HAL_Delay>
for(i = 0; i < 3; i++)
800069e: 2300 movs r3, #0
80006a0: 607b str r3, [r7, #4]
80006a2: e007 b.n 80006b4 <animation2+0x44>
LED_Off(i);
80006a4: 687b ldr r3, [r7, #4]
80006a6: b2db uxtb r3, r3
80006a8: 4618 mov r0, r3
80006aa: f7ff ff81 bl 80005b0 <LED_Off>
for(i = 0; i < 3; i++)
80006ae: 687b ldr r3, [r7, #4]
80006b0: 3301 adds r3, #1
80006b2: 607b str r3, [r7, #4]
80006b4: 687b ldr r3, [r7, #4]
80006b6: 2b02 cmp r3, #2
80006b8: ddf4 ble.n 80006a4 <animation2+0x34>
HAL_Delay(100);
80006ba: 2064 movs r0, #100 @ 0x64
80006bc: f000 ffaa bl 8001614 <HAL_Delay>
for(j = 0; j < 5; j++){
80006c0: 683b ldr r3, [r7, #0]
80006c2: 3301 adds r3, #1
80006c4: 603b str r3, [r7, #0]
80006c6: 683b ldr r3, [r7, #0]
80006c8: 2b04 cmp r3, #4
80006ca: ddd7 ble.n 800067c <animation2+0xc>
}
}
80006cc: bf00 nop
80006ce: bf00 nop
80006d0: 3708 adds r7, #8
80006d2: 46bd mov sp, r7
80006d4: bd80 pop {r7, pc}
080006d6 <animation3>:
void animation3(void){
80006d6: b580 push {r7, lr}
80006d8: b082 sub sp, #8
80006da: af00 add r7, sp, #0
int i;
for(i = 0; i < 3; i++){
80006dc: 2300 movs r3, #0
80006de: 607b str r3, [r7, #4]
80006e0: e00a b.n 80006f8 <animation3+0x22>
LED_On(i);
80006e2: 687b ldr r3, [r7, #4]
80006e4: b2db uxtb r3, r3
80006e6: 4618 mov r0, r3
80006e8: f7ff ff36 bl 8000558 <LED_On>
HAL_Delay(150);
80006ec: 2096 movs r0, #150 @ 0x96
80006ee: f000 ff91 bl 8001614 <HAL_Delay>
for(i = 0; i < 3; i++){
80006f2: 687b ldr r3, [r7, #4]
80006f4: 3301 adds r3, #1
80006f6: 607b str r3, [r7, #4]
80006f8: 687b ldr r3, [r7, #4]
80006fa: 2b02 cmp r3, #2
80006fc: ddf1 ble.n 80006e2 <animation3+0xc>
}
for(i = 2; i >= 0; i--){
80006fe: 2302 movs r3, #2
8000700: 607b str r3, [r7, #4]
8000702: e00a b.n 800071a <animation3+0x44>
LED_Off(i);
8000704: 687b ldr r3, [r7, #4]
8000706: b2db uxtb r3, r3
8000708: 4618 mov r0, r3
800070a: f7ff ff51 bl 80005b0 <LED_Off>
HAL_Delay(150);
800070e: 2096 movs r0, #150 @ 0x96
8000710: f000 ff80 bl 8001614 <HAL_Delay>
for(i = 2; i >= 0; i--){
8000714: 687b ldr r3, [r7, #4]
8000716: 3b01 subs r3, #1
8000718: 607b str r3, [r7, #4]
800071a: 687b ldr r3, [r7, #4]
800071c: 2b00 cmp r3, #0
800071e: daf1 bge.n 8000704 <animation3+0x2e>
}
}
8000720: bf00 nop
8000722: bf00 nop
8000724: 3708 adds r7, #8
8000726: 46bd mov sp, r7
8000728: bd80 pop {r7, pc}
...
0800072c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800072c: b580 push {r7, lr}
800072e: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000730: f000 fefb bl 800152a <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000734: f000 f836 bl 80007a4 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000738: f000 f9fe bl 8000b38 <MX_GPIO_Init>
MX_DFSDM1_Init();
800073c: f000 f894 bl 8000868 <MX_DFSDM1_Init>
MX_I2C2_Init();
8000740: f000 f8ca bl 80008d8 <MX_I2C2_Init>
MX_QUADSPI_Init();
8000744: f000 f906 bl 8000954 <MX_QUADSPI_Init>
MX_SPI3_Init();
8000748: f000 f92a bl 80009a0 <MX_SPI3_Init>
MX_USART1_UART_Init();
800074c: f000 f966 bl 8000a1c <MX_USART1_UART_Init>
MX_USART3_UART_Init();
8000750: f000 f994 bl 8000a7c <MX_USART3_UART_Init>
MX_USB_OTG_FS_PCD_Init();
8000754: f000 f9c2 bl 8000adc <MX_USB_OTG_FS_PCD_Init>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
switch(ReadJoy())
8000758: f7ff fecc bl 80004f4 <ReadJoy>
800075c: 4603 mov r3, r0
800075e: 2b03 cmp r3, #3
8000760: d8fa bhi.n 8000758 <main+0x2c>
8000762: a201 add r2, pc, #4 @ (adr r2, 8000768 <main+0x3c>)
8000764: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8000768: 08000779 .word 0x08000779
800076c: 0800078d .word 0x0800078d
8000770: 08000793 .word 0x08000793
8000774: 08000799 .word 0x08000799
{
case 0:
LED_Off(0);
8000778: 2000 movs r0, #0
800077a: f7ff ff19 bl 80005b0 <LED_Off>
LED_Off(1);
800077e: 2001 movs r0, #1
8000780: f7ff ff16 bl 80005b0 <LED_Off>
LED_Off(2);
8000784: 2002 movs r0, #2
8000786: f7ff ff13 bl 80005b0 <LED_Off>
break;
800078a: e009 b.n 80007a0 <main+0x74>
case 1:
animation1();
800078c: f7ff ff3c bl 8000608 <animation1>
break;
8000790: e006 b.n 80007a0 <main+0x74>
case 2:
animation2();
8000792: f7ff ff6d bl 8000670 <animation2>
break;
8000796: e003 b.n 80007a0 <main+0x74>
case 3:
animation3();
8000798: f7ff ff9d bl 80006d6 <animation3>
break;
800079c: bf00 nop
800079e: e7db b.n 8000758 <main+0x2c>
switch(ReadJoy())
80007a0: e7da b.n 8000758 <main+0x2c>
80007a2: bf00 nop
080007a4 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80007a4: b580 push {r7, lr}
80007a6: b096 sub sp, #88 @ 0x58
80007a8: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80007aa: f107 0314 add.w r3, r7, #20
80007ae: 2244 movs r2, #68 @ 0x44
80007b0: 2100 movs r1, #0
80007b2: 4618 mov r0, r3
80007b4: f004 fa4f bl 8004c56 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80007b8: 463b mov r3, r7
80007ba: 2200 movs r2, #0
80007bc: 601a str r2, [r3, #0]
80007be: 605a str r2, [r3, #4]
80007c0: 609a str r2, [r3, #8]
80007c2: 60da str r2, [r3, #12]
80007c4: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
80007c6: f44f 7000 mov.w r0, #512 @ 0x200
80007ca: f001 fde5 bl 8002398 <HAL_PWREx_ControlVoltageScaling>
80007ce: 4603 mov r3, r0
80007d0: 2b00 cmp r3, #0
80007d2: d001 beq.n 80007d8 <SystemClock_Config+0x34>
{
Error_Handler();
80007d4: f000 fb62 bl 8000e9c <Error_Handler>
}
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
80007d8: f001 fdc0 bl 800235c <HAL_PWR_EnableBkUpAccess>
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
80007dc: 4b21 ldr r3, [pc, #132] @ (8000864 <SystemClock_Config+0xc0>)
80007de: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80007e2: 4a20 ldr r2, [pc, #128] @ (8000864 <SystemClock_Config+0xc0>)
80007e4: f023 0318 bic.w r3, r3, #24
80007e8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
80007ec: 2314 movs r3, #20
80007ee: 617b str r3, [r7, #20]
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
80007f0: 2301 movs r3, #1
80007f2: 61fb str r3, [r7, #28]
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
80007f4: 2301 movs r3, #1
80007f6: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.MSICalibrationValue = 0;
80007f8: 2300 movs r3, #0
80007fa: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
80007fc: 2360 movs r3, #96 @ 0x60
80007fe: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000800: 2302 movs r3, #2
8000802: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
8000804: 2301 movs r3, #1
8000806: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLM = 1;
8000808: 2301 movs r3, #1
800080a: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLN = 40;
800080c: 2328 movs r3, #40 @ 0x28
800080e: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
8000810: 2307 movs r3, #7
8000812: 64fb str r3, [r7, #76] @ 0x4c
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
8000814: 2302 movs r3, #2
8000816: 653b str r3, [r7, #80] @ 0x50
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
8000818: 2302 movs r3, #2
800081a: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800081c: f107 0314 add.w r3, r7, #20
8000820: 4618 mov r0, r3
8000822: f001 fedb bl 80025dc <HAL_RCC_OscConfig>
8000826: 4603 mov r3, r0
8000828: 2b00 cmp r3, #0
800082a: d001 beq.n 8000830 <SystemClock_Config+0x8c>
{
Error_Handler();
800082c: f000 fb36 bl 8000e9c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000830: 230f movs r3, #15
8000832: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000834: 2303 movs r3, #3
8000836: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000838: 2300 movs r3, #0
800083a: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800083c: 2300 movs r3, #0
800083e: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000840: 2300 movs r3, #0
8000842: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
8000844: 463b mov r3, r7
8000846: 2104 movs r1, #4
8000848: 4618 mov r0, r3
800084a: f002 faa3 bl 8002d94 <HAL_RCC_ClockConfig>
800084e: 4603 mov r3, r0
8000850: 2b00 cmp r3, #0
8000852: d001 beq.n 8000858 <SystemClock_Config+0xb4>
{
Error_Handler();
8000854: f000 fb22 bl 8000e9c <Error_Handler>
}
/** Enable MSI Auto calibration
*/
HAL_RCCEx_EnableMSIPLLMode();
8000858: f002 ffaa bl 80037b0 <HAL_RCCEx_EnableMSIPLLMode>
}
800085c: bf00 nop
800085e: 3758 adds r7, #88 @ 0x58
8000860: 46bd mov sp, r7
8000862: bd80 pop {r7, pc}
8000864: 40021000 .word 0x40021000
08000868 <MX_DFSDM1_Init>:
* @brief DFSDM1 Initialization Function
* @param None
* @retval None
*/
static void MX_DFSDM1_Init(void)
{
8000868: b580 push {r7, lr}
800086a: af00 add r7, sp, #0
/* USER CODE END DFSDM1_Init 0 */
/* USER CODE BEGIN DFSDM1_Init 1 */
/* USER CODE END DFSDM1_Init 1 */
hdfsdm1_channel1.Instance = DFSDM1_Channel1;
800086c: 4b18 ldr r3, [pc, #96] @ (80008d0 <MX_DFSDM1_Init+0x68>)
800086e: 4a19 ldr r2, [pc, #100] @ (80008d4 <MX_DFSDM1_Init+0x6c>)
8000870: 601a str r2, [r3, #0]
hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;
8000872: 4b17 ldr r3, [pc, #92] @ (80008d0 <MX_DFSDM1_Init+0x68>)
8000874: 2201 movs r2, #1
8000876: 711a strb r2, [r3, #4]
hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;
8000878: 4b15 ldr r3, [pc, #84] @ (80008d0 <MX_DFSDM1_Init+0x68>)
800087a: 2200 movs r2, #0
800087c: 609a str r2, [r3, #8]
hdfsdm1_channel1.Init.OutputClock.Divider = 2;
800087e: 4b14 ldr r3, [pc, #80] @ (80008d0 <MX_DFSDM1_Init+0x68>)
8000880: 2202 movs r2, #2
8000882: 60da str r2, [r3, #12]
hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
8000884: 4b12 ldr r3, [pc, #72] @ (80008d0 <MX_DFSDM1_Init+0x68>)
8000886: 2200 movs r2, #0
8000888: 611a str r2, [r3, #16]
hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
800088a: 4b11 ldr r3, [pc, #68] @ (80008d0 <MX_DFSDM1_Init+0x68>)
800088c: 2200 movs r2, #0
800088e: 615a str r2, [r3, #20]
hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;
8000890: 4b0f ldr r3, [pc, #60] @ (80008d0 <MX_DFSDM1_Init+0x68>)
8000892: f44f 7280 mov.w r2, #256 @ 0x100
8000896: 619a str r2, [r3, #24]
hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
8000898: 4b0d ldr r3, [pc, #52] @ (80008d0 <MX_DFSDM1_Init+0x68>)
800089a: 2200 movs r2, #0
800089c: 61da str r2, [r3, #28]
hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
800089e: 4b0c ldr r3, [pc, #48] @ (80008d0 <MX_DFSDM1_Init+0x68>)
80008a0: 2204 movs r2, #4
80008a2: 621a str r2, [r3, #32]
hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
80008a4: 4b0a ldr r3, [pc, #40] @ (80008d0 <MX_DFSDM1_Init+0x68>)
80008a6: 2200 movs r2, #0
80008a8: 625a str r2, [r3, #36] @ 0x24
hdfsdm1_channel1.Init.Awd.Oversampling = 1;
80008aa: 4b09 ldr r3, [pc, #36] @ (80008d0 <MX_DFSDM1_Init+0x68>)
80008ac: 2201 movs r2, #1
80008ae: 629a str r2, [r3, #40] @ 0x28
hdfsdm1_channel1.Init.Offset = 0;
80008b0: 4b07 ldr r3, [pc, #28] @ (80008d0 <MX_DFSDM1_Init+0x68>)
80008b2: 2200 movs r2, #0
80008b4: 62da str r2, [r3, #44] @ 0x2c
hdfsdm1_channel1.Init.RightBitShift = 0x00;
80008b6: 4b06 ldr r3, [pc, #24] @ (80008d0 <MX_DFSDM1_Init+0x68>)
80008b8: 2200 movs r2, #0
80008ba: 631a str r2, [r3, #48] @ 0x30
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)
80008bc: 4804 ldr r0, [pc, #16] @ (80008d0 <MX_DFSDM1_Init+0x68>)
80008be: f000 ffdf bl 8001880 <HAL_DFSDM_ChannelInit>
80008c2: 4603 mov r3, r0
80008c4: 2b00 cmp r3, #0
80008c6: d001 beq.n 80008cc <MX_DFSDM1_Init+0x64>
{
Error_Handler();
80008c8: f000 fae8 bl 8000e9c <Error_Handler>
}
/* USER CODE BEGIN DFSDM1_Init 2 */
/* USER CODE END DFSDM1_Init 2 */
}
80008cc: bf00 nop
80008ce: bd80 pop {r7, pc}
80008d0: 20000030 .word 0x20000030
80008d4: 40016020 .word 0x40016020
080008d8 <MX_I2C2_Init>:
* @brief I2C2 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C2_Init(void)
{
80008d8: b580 push {r7, lr}
80008da: af00 add r7, sp, #0
/* USER CODE END I2C2_Init 0 */
/* USER CODE BEGIN I2C2_Init 1 */
/* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2;
80008dc: 4b1b ldr r3, [pc, #108] @ (800094c <MX_I2C2_Init+0x74>)
80008de: 4a1c ldr r2, [pc, #112] @ (8000950 <MX_I2C2_Init+0x78>)
80008e0: 601a str r2, [r3, #0]
hi2c2.Init.Timing = 0x00000E14;
80008e2: 4b1a ldr r3, [pc, #104] @ (800094c <MX_I2C2_Init+0x74>)
80008e4: f640 6214 movw r2, #3604 @ 0xe14
80008e8: 605a str r2, [r3, #4]
hi2c2.Init.OwnAddress1 = 0;
80008ea: 4b18 ldr r3, [pc, #96] @ (800094c <MX_I2C2_Init+0x74>)
80008ec: 2200 movs r2, #0
80008ee: 609a str r2, [r3, #8]
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
80008f0: 4b16 ldr r3, [pc, #88] @ (800094c <MX_I2C2_Init+0x74>)
80008f2: 2201 movs r2, #1
80008f4: 60da str r2, [r3, #12]
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80008f6: 4b15 ldr r3, [pc, #84] @ (800094c <MX_I2C2_Init+0x74>)
80008f8: 2200 movs r2, #0
80008fa: 611a str r2, [r3, #16]
hi2c2.Init.OwnAddress2 = 0;
80008fc: 4b13 ldr r3, [pc, #76] @ (800094c <MX_I2C2_Init+0x74>)
80008fe: 2200 movs r2, #0
8000900: 615a str r2, [r3, #20]
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
8000902: 4b12 ldr r3, [pc, #72] @ (800094c <MX_I2C2_Init+0x74>)
8000904: 2200 movs r2, #0
8000906: 619a str r2, [r3, #24]
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8000908: 4b10 ldr r3, [pc, #64] @ (800094c <MX_I2C2_Init+0x74>)
800090a: 2200 movs r2, #0
800090c: 61da str r2, [r3, #28]
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
800090e: 4b0f ldr r3, [pc, #60] @ (800094c <MX_I2C2_Init+0x74>)
8000910: 2200 movs r2, #0
8000912: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
8000914: 480d ldr r0, [pc, #52] @ (800094c <MX_I2C2_Init+0x74>)
8000916: f001 fabc bl 8001e92 <HAL_I2C_Init>
800091a: 4603 mov r3, r0
800091c: 2b00 cmp r3, #0
800091e: d001 beq.n 8000924 <MX_I2C2_Init+0x4c>
{
Error_Handler();
8000920: f000 fabc bl 8000e9c <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
8000924: 2100 movs r1, #0
8000926: 4809 ldr r0, [pc, #36] @ (800094c <MX_I2C2_Init+0x74>)
8000928: f001 fb4e bl 8001fc8 <HAL_I2CEx_ConfigAnalogFilter>
800092c: 4603 mov r3, r0
800092e: 2b00 cmp r3, #0
8000930: d001 beq.n 8000936 <MX_I2C2_Init+0x5e>
{
Error_Handler();
8000932: f000 fab3 bl 8000e9c <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
8000936: 2100 movs r1, #0
8000938: 4804 ldr r0, [pc, #16] @ (800094c <MX_I2C2_Init+0x74>)
800093a: f001 fb90 bl 800205e <HAL_I2CEx_ConfigDigitalFilter>
800093e: 4603 mov r3, r0
8000940: 2b00 cmp r3, #0
8000942: d001 beq.n 8000948 <MX_I2C2_Init+0x70>
{
Error_Handler();
8000944: f000 faaa bl 8000e9c <Error_Handler>
}
/* USER CODE BEGIN I2C2_Init 2 */
/* USER CODE END I2C2_Init 2 */
}
8000948: bf00 nop
800094a: bd80 pop {r7, pc}
800094c: 20000068 .word 0x20000068
8000950: 40005800 .word 0x40005800
08000954 <MX_QUADSPI_Init>:
* @brief QUADSPI Initialization Function
* @param None
* @retval None
*/
static void MX_QUADSPI_Init(void)
{
8000954: b580 push {r7, lr}
8000956: af00 add r7, sp, #0
/* USER CODE BEGIN QUADSPI_Init 1 */
/* USER CODE END QUADSPI_Init 1 */
/* QUADSPI parameter configuration*/
hqspi.Instance = QUADSPI;
8000958: 4b0f ldr r3, [pc, #60] @ (8000998 <MX_QUADSPI_Init+0x44>)
800095a: 4a10 ldr r2, [pc, #64] @ (800099c <MX_QUADSPI_Init+0x48>)
800095c: 601a str r2, [r3, #0]
hqspi.Init.ClockPrescaler = 2;
800095e: 4b0e ldr r3, [pc, #56] @ (8000998 <MX_QUADSPI_Init+0x44>)
8000960: 2202 movs r2, #2
8000962: 605a str r2, [r3, #4]
hqspi.Init.FifoThreshold = 4;
8000964: 4b0c ldr r3, [pc, #48] @ (8000998 <MX_QUADSPI_Init+0x44>)
8000966: 2204 movs r2, #4
8000968: 609a str r2, [r3, #8]
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
800096a: 4b0b ldr r3, [pc, #44] @ (8000998 <MX_QUADSPI_Init+0x44>)
800096c: 2210 movs r2, #16
800096e: 60da str r2, [r3, #12]
hqspi.Init.FlashSize = 23;
8000970: 4b09 ldr r3, [pc, #36] @ (8000998 <MX_QUADSPI_Init+0x44>)
8000972: 2217 movs r2, #23
8000974: 611a str r2, [r3, #16]
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
8000976: 4b08 ldr r3, [pc, #32] @ (8000998 <MX_QUADSPI_Init+0x44>)
8000978: 2200 movs r2, #0
800097a: 615a str r2, [r3, #20]
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
800097c: 4b06 ldr r3, [pc, #24] @ (8000998 <MX_QUADSPI_Init+0x44>)
800097e: 2200 movs r2, #0
8000980: 619a str r2, [r3, #24]
if (HAL_QSPI_Init(&hqspi) != HAL_OK)
8000982: 4805 ldr r0, [pc, #20] @ (8000998 <MX_QUADSPI_Init+0x44>)
8000984: f001 fd6e bl 8002464 <HAL_QSPI_Init>
8000988: 4603 mov r3, r0
800098a: 2b00 cmp r3, #0
800098c: d001 beq.n 8000992 <MX_QUADSPI_Init+0x3e>
{
Error_Handler();
800098e: f000 fa85 bl 8000e9c <Error_Handler>
}
/* USER CODE BEGIN QUADSPI_Init 2 */
/* USER CODE END QUADSPI_Init 2 */
}
8000992: bf00 nop
8000994: bd80 pop {r7, pc}
8000996: bf00 nop
8000998: 200000bc .word 0x200000bc
800099c: a0001000 .word 0xa0001000
080009a0 <MX_SPI3_Init>:
* @brief SPI3 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI3_Init(void)
{
80009a0: b580 push {r7, lr}
80009a2: af00 add r7, sp, #0
/* USER CODE BEGIN SPI3_Init 1 */
/* USER CODE END SPI3_Init 1 */
/* SPI3 parameter configuration*/
hspi3.Instance = SPI3;
80009a4: 4b1b ldr r3, [pc, #108] @ (8000a14 <MX_SPI3_Init+0x74>)
80009a6: 4a1c ldr r2, [pc, #112] @ (8000a18 <MX_SPI3_Init+0x78>)
80009a8: 601a str r2, [r3, #0]
hspi3.Init.Mode = SPI_MODE_MASTER;
80009aa: 4b1a ldr r3, [pc, #104] @ (8000a14 <MX_SPI3_Init+0x74>)
80009ac: f44f 7282 mov.w r2, #260 @ 0x104
80009b0: 605a str r2, [r3, #4]
hspi3.Init.Direction = SPI_DIRECTION_2LINES;
80009b2: 4b18 ldr r3, [pc, #96] @ (8000a14 <MX_SPI3_Init+0x74>)
80009b4: 2200 movs r2, #0
80009b6: 609a str r2, [r3, #8]
hspi3.Init.DataSize = SPI_DATASIZE_4BIT;
80009b8: 4b16 ldr r3, [pc, #88] @ (8000a14 <MX_SPI3_Init+0x74>)
80009ba: f44f 7240 mov.w r2, #768 @ 0x300
80009be: 60da str r2, [r3, #12]
hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
80009c0: 4b14 ldr r3, [pc, #80] @ (8000a14 <MX_SPI3_Init+0x74>)
80009c2: 2200 movs r2, #0
80009c4: 611a str r2, [r3, #16]
hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
80009c6: 4b13 ldr r3, [pc, #76] @ (8000a14 <MX_SPI3_Init+0x74>)
80009c8: 2200 movs r2, #0
80009ca: 615a str r2, [r3, #20]
hspi3.Init.NSS = SPI_NSS_SOFT;
80009cc: 4b11 ldr r3, [pc, #68] @ (8000a14 <MX_SPI3_Init+0x74>)
80009ce: f44f 7200 mov.w r2, #512 @ 0x200
80009d2: 619a str r2, [r3, #24]
hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80009d4: 4b0f ldr r3, [pc, #60] @ (8000a14 <MX_SPI3_Init+0x74>)
80009d6: 2200 movs r2, #0
80009d8: 61da str r2, [r3, #28]
hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
80009da: 4b0e ldr r3, [pc, #56] @ (8000a14 <MX_SPI3_Init+0x74>)
80009dc: 2200 movs r2, #0
80009de: 621a str r2, [r3, #32]
hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
80009e0: 4b0c ldr r3, [pc, #48] @ (8000a14 <MX_SPI3_Init+0x74>)
80009e2: 2200 movs r2, #0
80009e4: 625a str r2, [r3, #36] @ 0x24
hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80009e6: 4b0b ldr r3, [pc, #44] @ (8000a14 <MX_SPI3_Init+0x74>)
80009e8: 2200 movs r2, #0
80009ea: 629a str r2, [r3, #40] @ 0x28
hspi3.Init.CRCPolynomial = 7;
80009ec: 4b09 ldr r3, [pc, #36] @ (8000a14 <MX_SPI3_Init+0x74>)
80009ee: 2207 movs r2, #7
80009f0: 62da str r2, [r3, #44] @ 0x2c
hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
80009f2: 4b08 ldr r3, [pc, #32] @ (8000a14 <MX_SPI3_Init+0x74>)
80009f4: 2200 movs r2, #0
80009f6: 631a str r2, [r3, #48] @ 0x30
hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
80009f8: 4b06 ldr r3, [pc, #24] @ (8000a14 <MX_SPI3_Init+0x74>)
80009fa: 2208 movs r2, #8
80009fc: 635a str r2, [r3, #52] @ 0x34
if (HAL_SPI_Init(&hspi3) != HAL_OK)
80009fe: 4805 ldr r0, [pc, #20] @ (8000a14 <MX_SPI3_Init+0x74>)
8000a00: f003 f8b8 bl 8003b74 <HAL_SPI_Init>
8000a04: 4603 mov r3, r0
8000a06: 2b00 cmp r3, #0
8000a08: d001 beq.n 8000a0e <MX_SPI3_Init+0x6e>
{
Error_Handler();
8000a0a: f000 fa47 bl 8000e9c <Error_Handler>
}
/* USER CODE BEGIN SPI3_Init 2 */
/* USER CODE END SPI3_Init 2 */
}
8000a0e: bf00 nop
8000a10: bd80 pop {r7, pc}
8000a12: bf00 nop
8000a14: 20000100 .word 0x20000100
8000a18: 40003c00 .word 0x40003c00
08000a1c <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8000a1c: b580 push {r7, lr}
8000a1e: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8000a20: 4b14 ldr r3, [pc, #80] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a22: 4a15 ldr r2, [pc, #84] @ (8000a78 <MX_USART1_UART_Init+0x5c>)
8000a24: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8000a26: 4b13 ldr r3, [pc, #76] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a28: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000a2c: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8000a2e: 4b11 ldr r3, [pc, #68] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a30: 2200 movs r2, #0
8000a32: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8000a34: 4b0f ldr r3, [pc, #60] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a36: 2200 movs r2, #0
8000a38: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8000a3a: 4b0e ldr r3, [pc, #56] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a3c: 2200 movs r2, #0
8000a3e: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8000a40: 4b0c ldr r3, [pc, #48] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a42: 220c movs r2, #12
8000a44: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000a46: 4b0b ldr r3, [pc, #44] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a48: 2200 movs r2, #0
8000a4a: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8000a4c: 4b09 ldr r3, [pc, #36] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a4e: 2200 movs r2, #0
8000a50: 61da str r2, [r3, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000a52: 4b08 ldr r3, [pc, #32] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a54: 2200 movs r2, #0
8000a56: 621a str r2, [r3, #32]
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000a58: 4b06 ldr r3, [pc, #24] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a5a: 2200 movs r2, #0
8000a5c: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart1) != HAL_OK)
8000a5e: 4805 ldr r0, [pc, #20] @ (8000a74 <MX_USART1_UART_Init+0x58>)
8000a60: f003 f92b bl 8003cba <HAL_UART_Init>
8000a64: 4603 mov r3, r0
8000a66: 2b00 cmp r3, #0
8000a68: d001 beq.n 8000a6e <MX_USART1_UART_Init+0x52>
{
Error_Handler();
8000a6a: f000 fa17 bl 8000e9c <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8000a6e: bf00 nop
8000a70: bd80 pop {r7, pc}
8000a72: bf00 nop
8000a74: 20000164 .word 0x20000164
8000a78: 40013800 .word 0x40013800
08000a7c <MX_USART3_UART_Init>:
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static void MX_USART3_UART_Init(void)
{
8000a7c: b580 push {r7, lr}
8000a7e: af00 add r7, sp, #0
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
8000a80: 4b14 ldr r3, [pc, #80] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000a82: 4a15 ldr r2, [pc, #84] @ (8000ad8 <MX_USART3_UART_Init+0x5c>)
8000a84: 601a str r2, [r3, #0]
huart3.Init.BaudRate = 115200;
8000a86: 4b13 ldr r3, [pc, #76] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000a88: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000a8c: 605a str r2, [r3, #4]
huart3.Init.WordLength = UART_WORDLENGTH_8B;
8000a8e: 4b11 ldr r3, [pc, #68] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000a90: 2200 movs r2, #0
8000a92: 609a str r2, [r3, #8]
huart3.Init.StopBits = UART_STOPBITS_1;
8000a94: 4b0f ldr r3, [pc, #60] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000a96: 2200 movs r2, #0
8000a98: 60da str r2, [r3, #12]
huart3.Init.Parity = UART_PARITY_NONE;
8000a9a: 4b0e ldr r3, [pc, #56] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000a9c: 2200 movs r2, #0
8000a9e: 611a str r2, [r3, #16]
huart3.Init.Mode = UART_MODE_TX_RX;
8000aa0: 4b0c ldr r3, [pc, #48] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000aa2: 220c movs r2, #12
8000aa4: 615a str r2, [r3, #20]
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000aa6: 4b0b ldr r3, [pc, #44] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000aa8: 2200 movs r2, #0
8000aaa: 619a str r2, [r3, #24]
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
8000aac: 4b09 ldr r3, [pc, #36] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000aae: 2200 movs r2, #0
8000ab0: 61da str r2, [r3, #28]
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000ab2: 4b08 ldr r3, [pc, #32] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000ab4: 2200 movs r2, #0
8000ab6: 621a str r2, [r3, #32]
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000ab8: 4b06 ldr r3, [pc, #24] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000aba: 2200 movs r2, #0
8000abc: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart3) != HAL_OK)
8000abe: 4805 ldr r0, [pc, #20] @ (8000ad4 <MX_USART3_UART_Init+0x58>)
8000ac0: f003 f8fb bl 8003cba <HAL_UART_Init>
8000ac4: 4603 mov r3, r0
8000ac6: 2b00 cmp r3, #0
8000ac8: d001 beq.n 8000ace <MX_USART3_UART_Init+0x52>
{
Error_Handler();
8000aca: f000 f9e7 bl 8000e9c <Error_Handler>
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
8000ace: bf00 nop
8000ad0: bd80 pop {r7, pc}
8000ad2: bf00 nop
8000ad4: 200001ec .word 0x200001ec
8000ad8: 40004800 .word 0x40004800
08000adc <MX_USB_OTG_FS_PCD_Init>:
* @brief USB_OTG_FS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_FS_PCD_Init(void)
{
8000adc: b580 push {r7, lr}
8000ade: af00 add r7, sp, #0
/* USER CODE END USB_OTG_FS_Init 0 */
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
/* USER CODE END USB_OTG_FS_Init 1 */
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
8000ae0: 4b14 ldr r3, [pc, #80] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000ae2: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
8000ae6: 601a str r2, [r3, #0]
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
8000ae8: 4b12 ldr r3, [pc, #72] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000aea: 2206 movs r2, #6
8000aec: 711a strb r2, [r3, #4]
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
8000aee: 4b11 ldr r3, [pc, #68] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000af0: 2202 movs r2, #2
8000af2: 71da strb r2, [r3, #7]
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
8000af4: 4b0f ldr r3, [pc, #60] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000af6: 2202 movs r2, #2
8000af8: 725a strb r2, [r3, #9]
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
8000afa: 4b0e ldr r3, [pc, #56] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000afc: 2200 movs r2, #0
8000afe: 729a strb r2, [r3, #10]
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
8000b00: 4b0c ldr r3, [pc, #48] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000b02: 2200 movs r2, #0
8000b04: 72da strb r2, [r3, #11]
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
8000b06: 4b0b ldr r3, [pc, #44] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000b08: 2200 movs r2, #0
8000b0a: 731a strb r2, [r3, #12]
hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
8000b0c: 4b09 ldr r3, [pc, #36] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000b0e: 2200 movs r2, #0
8000b10: 735a strb r2, [r3, #13]
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
8000b12: 4b08 ldr r3, [pc, #32] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000b14: 2200 movs r2, #0
8000b16: 73da strb r2, [r3, #15]
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
8000b18: 4b06 ldr r3, [pc, #24] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000b1a: 2200 movs r2, #0
8000b1c: 739a strb r2, [r3, #14]
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
8000b1e: 4805 ldr r0, [pc, #20] @ (8000b34 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000b20: f001 fae9 bl 80020f6 <HAL_PCD_Init>
8000b24: 4603 mov r3, r0
8000b26: 2b00 cmp r3, #0
8000b28: d001 beq.n 8000b2e <MX_USB_OTG_FS_PCD_Init+0x52>
{
Error_Handler();
8000b2a: f000 f9b7 bl 8000e9c <Error_Handler>
}
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
/* USER CODE END USB_OTG_FS_Init 2 */
}
8000b2e: bf00 nop
8000b30: bd80 pop {r7, pc}
8000b32: bf00 nop
8000b34: 20000274 .word 0x20000274
08000b38 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000b38: b580 push {r7, lr}
8000b3a: b08a sub sp, #40 @ 0x28
8000b3c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000b3e: f107 0314 add.w r3, r7, #20
8000b42: 2200 movs r2, #0
8000b44: 601a str r2, [r3, #0]
8000b46: 605a str r2, [r3, #4]
8000b48: 609a str r2, [r3, #8]
8000b4a: 60da str r2, [r3, #12]
8000b4c: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
8000b4e: 4bbd ldr r3, [pc, #756] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b50: 6cdb ldr r3, [r3, #76] @ 0x4c
8000b52: 4abc ldr r2, [pc, #752] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b54: f043 0310 orr.w r3, r3, #16
8000b58: 64d3 str r3, [r2, #76] @ 0x4c
8000b5a: 4bba ldr r3, [pc, #744] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b5c: 6cdb ldr r3, [r3, #76] @ 0x4c
8000b5e: f003 0310 and.w r3, r3, #16
8000b62: 613b str r3, [r7, #16]
8000b64: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000b66: 4bb7 ldr r3, [pc, #732] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b68: 6cdb ldr r3, [r3, #76] @ 0x4c
8000b6a: 4ab6 ldr r2, [pc, #728] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b6c: f043 0304 orr.w r3, r3, #4
8000b70: 64d3 str r3, [r2, #76] @ 0x4c
8000b72: 4bb4 ldr r3, [pc, #720] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b74: 6cdb ldr r3, [r3, #76] @ 0x4c
8000b76: f003 0304 and.w r3, r3, #4
8000b7a: 60fb str r3, [r7, #12]
8000b7c: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000b7e: 4bb1 ldr r3, [pc, #708] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b80: 6cdb ldr r3, [r3, #76] @ 0x4c
8000b82: 4ab0 ldr r2, [pc, #704] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b84: f043 0301 orr.w r3, r3, #1
8000b88: 64d3 str r3, [r2, #76] @ 0x4c
8000b8a: 4bae ldr r3, [pc, #696] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b8c: 6cdb ldr r3, [r3, #76] @ 0x4c
8000b8e: f003 0301 and.w r3, r3, #1
8000b92: 60bb str r3, [r7, #8]
8000b94: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000b96: 4bab ldr r3, [pc, #684] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b98: 6cdb ldr r3, [r3, #76] @ 0x4c
8000b9a: 4aaa ldr r2, [pc, #680] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000b9c: f043 0302 orr.w r3, r3, #2
8000ba0: 64d3 str r3, [r2, #76] @ 0x4c
8000ba2: 4ba8 ldr r3, [pc, #672] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000ba4: 6cdb ldr r3, [r3, #76] @ 0x4c
8000ba6: f003 0302 and.w r3, r3, #2
8000baa: 607b str r3, [r7, #4]
8000bac: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000bae: 4ba5 ldr r3, [pc, #660] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000bb0: 6cdb ldr r3, [r3, #76] @ 0x4c
8000bb2: 4aa4 ldr r2, [pc, #656] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000bb4: f043 0308 orr.w r3, r3, #8
8000bb8: 64d3 str r3, [r2, #76] @ 0x4c
8000bba: 4ba2 ldr r3, [pc, #648] @ (8000e44 <MX_GPIO_Init+0x30c>)
8000bbc: 6cdb ldr r3, [r3, #76] @ 0x4c
8000bbe: f003 0308 and.w r3, r3, #8
8000bc2: 603b str r3, [r7, #0]
8000bc4: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET);
8000bc6: 2200 movs r2, #0
8000bc8: f44f 718a mov.w r1, #276 @ 0x114
8000bcc: 489e ldr r0, [pc, #632] @ (8000e48 <MX_GPIO_Init+0x310>)
8000bce: f001 f925 bl 8001e1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET);
8000bd2: 2200 movs r2, #0
8000bd4: f248 1104 movw r1, #33028 @ 0x8104
8000bd8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000bdc: f001 f91e bl 8001e1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
8000be0: 2200 movs r2, #0
8000be2: f24f 0114 movw r1, #61460 @ 0xf014
8000be6: 4899 ldr r0, [pc, #612] @ (8000e4c <MX_GPIO_Init+0x314>)
8000be8: f001 f918 bl 8001e1c <HAL_GPIO_WritePin>
|SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET);
8000bec: 2200 movs r2, #0
8000bee: f241 0181 movw r1, #4225 @ 0x1081
8000bf2: 4897 ldr r0, [pc, #604] @ (8000e50 <MX_GPIO_Init+0x318>)
8000bf4: f001 f912 bl 8001e1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET);
8000bf8: 2201 movs r2, #1
8000bfa: f44f 5100 mov.w r1, #8192 @ 0x2000
8000bfe: 4894 ldr r0, [pc, #592] @ (8000e50 <MX_GPIO_Init+0x318>)
8000c00: f001 f90c bl 8001e1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET);
8000c04: 2200 movs r2, #0
8000c06: f44f 7110 mov.w r1, #576 @ 0x240
8000c0a: 4892 ldr r0, [pc, #584] @ (8000e54 <MX_GPIO_Init+0x31c>)
8000c0c: f001 f906 bl 8001e1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET);
8000c10: 2201 movs r2, #1
8000c12: 2120 movs r1, #32
8000c14: 488d ldr r0, [pc, #564] @ (8000e4c <MX_GPIO_Init+0x314>)
8000c16: f001 f901 bl 8001e1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET);
8000c1a: 2201 movs r2, #1
8000c1c: 2101 movs r1, #1
8000c1e: 488a ldr r0, [pc, #552] @ (8000e48 <MX_GPIO_Init+0x310>)
8000c20: f001 f8fc bl 8001e1c <HAL_GPIO_WritePin>
/*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */
GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin;
8000c24: f240 1315 movw r3, #277 @ 0x115
8000c28: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c2a: 2301 movs r3, #1
8000c2c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c2e: 2300 movs r3, #0
8000c30: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c32: 2300 movs r3, #0
8000c34: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000c36: f107 0314 add.w r3, r7, #20
8000c3a: 4619 mov r1, r3
8000c3c: 4882 ldr r0, [pc, #520] @ (8000e48 <MX_GPIO_Init+0x310>)
8000c3e: f000 ff2b bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */
GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin;
8000c42: 236a movs r3, #106 @ 0x6a
8000c44: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000c46: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000c4a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c4c: 2300 movs r3, #0
8000c4e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000c50: f107 0314 add.w r3, r7, #20
8000c54: 4619 mov r1, r3
8000c56: 487c ldr r0, [pc, #496] @ (8000e48 <MX_GPIO_Init+0x310>)
8000c58: f000 ff1e bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pin : BUTTON_EXTI13_Pin */
GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin;
8000c5c: f44f 5300 mov.w r3, #8192 @ 0x2000
8000c60: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
8000c62: f44f 1304 mov.w r3, #2162688 @ 0x210000
8000c66: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c68: 2300 movs r3, #0
8000c6a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct);
8000c6c: f107 0314 add.w r3, r7, #20
8000c70: 4619 mov r1, r3
8000c72: 4878 ldr r0, [pc, #480] @ (8000e54 <MX_GPIO_Init+0x31c>)
8000c74: f000 ff10 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin
ARD_A1_Pin ARD_A0_Pin */
GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin
8000c78: 233f movs r3, #63 @ 0x3f
8000c7a: 617b str r3, [r7, #20]
|ARD_A1_Pin|ARD_A0_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
8000c7c: 230b movs r3, #11
8000c7e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c80: 2300 movs r3, #0
8000c82: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000c84: f107 0314 add.w r3, r7, #20
8000c88: 4619 mov r1, r3
8000c8a: 4872 ldr r0, [pc, #456] @ (8000e54 <MX_GPIO_Init+0x31c>)
8000c8c: f000 ff04 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */
GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin;
8000c90: 2303 movs r3, #3
8000c92: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c94: 2302 movs r3, #2
8000c96: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c98: 2300 movs r3, #0
8000c9a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c9c: 2303 movs r3, #3
8000c9e: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
8000ca0: 2308 movs r3, #8
8000ca2: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000ca4: f107 0314 add.w r3, r7, #20
8000ca8: 4619 mov r1, r3
8000caa: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000cae: f000 fef3 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D10_Pin SPBTLE_RF_RST_Pin ARD_D9_Pin */
GPIO_InitStruct.Pin = ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin;
8000cb2: f248 1304 movw r3, #33028 @ 0x8104
8000cb6: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000cb8: 2301 movs r3, #1
8000cba: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cbc: 2300 movs r3, #0
8000cbe: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000cc0: 2300 movs r3, #0
8000cc2: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000cc4: f107 0314 add.w r3, r7, #20
8000cc8: 4619 mov r1, r3
8000cca: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000cce: f000 fee3 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D4_Pin */
GPIO_InitStruct.Pin = ARD_D4_Pin;
8000cd2: 2308 movs r3, #8
8000cd4: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cd6: 2302 movs r3, #2
8000cd8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cda: 2300 movs r3, #0
8000cdc: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000cde: 2300 movs r3, #0
8000ce0: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8000ce2: 2301 movs r3, #1
8000ce4: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct);
8000ce6: f107 0314 add.w r3, r7, #20
8000cea: 4619 mov r1, r3
8000cec: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000cf0: f000 fed2 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D7_Pin */
GPIO_InitStruct.Pin = ARD_D7_Pin;
8000cf4: 2310 movs r3, #16
8000cf6: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
8000cf8: 230b movs r3, #11
8000cfa: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cfc: 2300 movs r3, #0
8000cfe: 61fb str r3, [r7, #28]
HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct);
8000d00: f107 0314 add.w r3, r7, #20
8000d04: 4619 mov r1, r3
8000d06: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000d0a: f000 fec5 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D13_Pin ARD_D12_Pin ARD_D11_Pin */
GPIO_InitStruct.Pin = ARD_D13_Pin|ARD_D12_Pin|ARD_D11_Pin;
8000d0e: 23e0 movs r3, #224 @ 0xe0
8000d10: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d12: 2302 movs r3, #2
8000d14: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d16: 2300 movs r3, #0
8000d18: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d1a: 2303 movs r3, #3
8000d1c: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000d1e: 2305 movs r3, #5
8000d20: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000d22: f107 0314 add.w r3, r7, #20
8000d26: 4619 mov r1, r3
8000d28: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000d2c: f000 feb4 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D3_Pin */
GPIO_InitStruct.Pin = ARD_D3_Pin;
8000d30: 2301 movs r3, #1
8000d32: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000d34: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000d38: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d3a: 2300 movs r3, #0
8000d3c: 61fb str r3, [r7, #28]
HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct);
8000d3e: f107 0314 add.w r3, r7, #20
8000d42: 4619 mov r1, r3
8000d44: 4841 ldr r0, [pc, #260] @ (8000e4c <MX_GPIO_Init+0x314>)
8000d46: f000 fea7 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D6_Pin */
GPIO_InitStruct.Pin = ARD_D6_Pin;
8000d4a: 2302 movs r3, #2
8000d4c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
8000d4e: 230b movs r3, #11
8000d50: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d52: 2300 movs r3, #0
8000d54: 61fb str r3, [r7, #28]
HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct);
8000d56: f107 0314 add.w r3, r7, #20
8000d5a: 4619 mov r1, r3
8000d5c: 483b ldr r0, [pc, #236] @ (8000e4c <MX_GPIO_Init+0x314>)
8000d5e: f000 fe9b bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin
SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */
GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
8000d62: f24f 0334 movw r3, #61492 @ 0xf034
8000d66: 617b str r3, [r7, #20]
|SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d68: 2301 movs r3, #1
8000d6a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d6c: 2300 movs r3, #0
8000d6e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d70: 2300 movs r3, #0
8000d72: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000d74: f107 0314 add.w r3, r7, #20
8000d78: 4619 mov r1, r3
8000d7a: 4834 ldr r0, [pc, #208] @ (8000e4c <MX_GPIO_Init+0x314>)
8000d7c: f000 fe8c bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin
PMOD_IRQ_EXTI12_Pin */
GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin
8000d80: f64c 4304 movw r3, #52228 @ 0xcc04
8000d84: 617b str r3, [r7, #20]
|PMOD_IRQ_EXTI12_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000d86: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000d8a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d8c: 2300 movs r3, #0
8000d8e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000d90: f107 0314 add.w r3, r7, #20
8000d94: 4619 mov r1, r3
8000d96: 482e ldr r0, [pc, #184] @ (8000e50 <MX_GPIO_Init+0x318>)
8000d98: f000 fe7e bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */
GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin;
8000d9c: f243 0381 movw r3, #12417 @ 0x3081
8000da0: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000da2: 2301 movs r3, #1
8000da4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000da6: 2300 movs r3, #0
8000da8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000daa: 2300 movs r3, #0
8000dac: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000dae: f107 0314 add.w r3, r7, #20
8000db2: 4619 mov r1, r3
8000db4: 4826 ldr r0, [pc, #152] @ (8000e50 <MX_GPIO_Init+0x318>)
8000db6: f000 fe6f bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */
GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin;
8000dba: f44f 7310 mov.w r3, #576 @ 0x240
8000dbe: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000dc0: 2301 movs r3, #1
8000dc2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000dc4: 2300 movs r3, #0
8000dc6: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000dc8: 2300 movs r3, #0
8000dca: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000dcc: f107 0314 add.w r3, r7, #20
8000dd0: 4619 mov r1, r3
8000dd2: 4820 ldr r0, [pc, #128] @ (8000e54 <MX_GPIO_Init+0x31c>)
8000dd4: f000 fe60 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */
GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin;
8000dd8: f44f 73c0 mov.w r3, #384 @ 0x180
8000ddc: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000dde: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000de2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000de4: 2300 movs r3, #0
8000de6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000de8: f107 0314 add.w r3, r7, #20
8000dec: 4619 mov r1, r3
8000dee: 4819 ldr r0, [pc, #100] @ (8000e54 <MX_GPIO_Init+0x31c>)
8000df0: f000 fe52 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pin : PMOD_SPI2_SCK_Pin */
GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin;
8000df4: 2302 movs r3, #2
8000df6: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000df8: 2302 movs r3, #2
8000dfa: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000dfc: 2300 movs r3, #0
8000dfe: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000e00: 2303 movs r3, #3
8000e02: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8000e04: 2305 movs r3, #5
8000e06: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct);
8000e08: f107 0314 add.w r3, r7, #20
8000e0c: 4619 mov r1, r3
8000e0e: 4810 ldr r0, [pc, #64] @ (8000e50 <MX_GPIO_Init+0x318>)
8000e10: f000 fe42 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */
GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin;
8000e14: 2378 movs r3, #120 @ 0x78
8000e16: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000e18: 2302 movs r3, #2
8000e1a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e1c: 2300 movs r3, #0
8000e1e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000e20: 2303 movs r3, #3
8000e22: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000e24: 2307 movs r3, #7
8000e26: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000e28: f107 0314 add.w r3, r7, #20
8000e2c: 4619 mov r1, r3
8000e2e: 4808 ldr r0, [pc, #32] @ (8000e50 <MX_GPIO_Init+0x318>)
8000e30: f000 fe32 bl 8001a98 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */
GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin;
8000e34: f44f 7340 mov.w r3, #768 @ 0x300
8000e38: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000e3a: 2312 movs r3, #18
8000e3c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e3e: 2300 movs r3, #0
8000e40: e00a b.n 8000e58 <MX_GPIO_Init+0x320>
8000e42: bf00 nop
8000e44: 40021000 .word 0x40021000
8000e48: 48001000 .word 0x48001000
8000e4c: 48000400 .word 0x48000400
8000e50: 48000c00 .word 0x48000c00
8000e54: 48000800 .word 0x48000800
8000e58: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000e5a: 2303 movs r3, #3
8000e5c: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
8000e5e: 2304 movs r3, #4
8000e60: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000e62: f107 0314 add.w r3, r7, #20
8000e66: 4619 mov r1, r3
8000e68: 480b ldr r0, [pc, #44] @ (8000e98 <MX_GPIO_Init+0x360>)
8000e6a: f000 fe15 bl 8001a98 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
8000e6e: 2200 movs r2, #0
8000e70: 2100 movs r1, #0
8000e72: 2017 movs r0, #23
8000e74: f000 fccd bl 8001812 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
8000e78: 2017 movs r0, #23
8000e7a: f000 fce6 bl 800184a <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
8000e7e: 2200 movs r2, #0
8000e80: 2100 movs r1, #0
8000e82: 2028 movs r0, #40 @ 0x28
8000e84: f000 fcc5 bl 8001812 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
8000e88: 2028 movs r0, #40 @ 0x28
8000e8a: f000 fcde bl 800184a <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000e8e: bf00 nop
8000e90: 3728 adds r7, #40 @ 0x28
8000e92: 46bd mov sp, r7
8000e94: bd80 pop {r7, pc}
8000e96: bf00 nop
8000e98: 48000400 .word 0x48000400
08000e9c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000e9c: b480 push {r7}
8000e9e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000ea0: b672 cpsid i
}
8000ea2: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000ea4: bf00 nop
8000ea6: e7fd b.n 8000ea4 <Error_Handler+0x8>
08000ea8 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000ea8: b480 push {r7}
8000eaa: b083 sub sp, #12
8000eac: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000eae: 4b0f ldr r3, [pc, #60] @ (8000eec <HAL_MspInit+0x44>)
8000eb0: 6e1b ldr r3, [r3, #96] @ 0x60
8000eb2: 4a0e ldr r2, [pc, #56] @ (8000eec <HAL_MspInit+0x44>)
8000eb4: f043 0301 orr.w r3, r3, #1
8000eb8: 6613 str r3, [r2, #96] @ 0x60
8000eba: 4b0c ldr r3, [pc, #48] @ (8000eec <HAL_MspInit+0x44>)
8000ebc: 6e1b ldr r3, [r3, #96] @ 0x60
8000ebe: f003 0301 and.w r3, r3, #1
8000ec2: 607b str r3, [r7, #4]
8000ec4: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000ec6: 4b09 ldr r3, [pc, #36] @ (8000eec <HAL_MspInit+0x44>)
8000ec8: 6d9b ldr r3, [r3, #88] @ 0x58
8000eca: 4a08 ldr r2, [pc, #32] @ (8000eec <HAL_MspInit+0x44>)
8000ecc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000ed0: 6593 str r3, [r2, #88] @ 0x58
8000ed2: 4b06 ldr r3, [pc, #24] @ (8000eec <HAL_MspInit+0x44>)
8000ed4: 6d9b ldr r3, [r3, #88] @ 0x58
8000ed6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000eda: 603b str r3, [r7, #0]
8000edc: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000ede: bf00 nop
8000ee0: 370c adds r7, #12
8000ee2: 46bd mov sp, r7
8000ee4: f85d 7b04 ldr.w r7, [sp], #4
8000ee8: 4770 bx lr
8000eea: bf00 nop
8000eec: 40021000 .word 0x40021000
08000ef0 <HAL_DFSDM_ChannelMspInit>:
* This function configures the hardware resources used in this example
* @param hdfsdm_channel: DFSDM_Channel handle pointer
* @retval None
*/
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)
{
8000ef0: b580 push {r7, lr}
8000ef2: b0ac sub sp, #176 @ 0xb0
8000ef4: af00 add r7, sp, #0
8000ef6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000ef8: f107 039c add.w r3, r7, #156 @ 0x9c
8000efc: 2200 movs r2, #0
8000efe: 601a str r2, [r3, #0]
8000f00: 605a str r2, [r3, #4]
8000f02: 609a str r2, [r3, #8]
8000f04: 60da str r2, [r3, #12]
8000f06: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000f08: f107 0314 add.w r3, r7, #20
8000f0c: 2288 movs r2, #136 @ 0x88
8000f0e: 2100 movs r1, #0
8000f10: 4618 mov r0, r3
8000f12: f003 fea0 bl 8004c56 <memset>
if(DFSDM1_Init == 0)
8000f16: 4b25 ldr r3, [pc, #148] @ (8000fac <HAL_DFSDM_ChannelMspInit+0xbc>)
8000f18: 681b ldr r3, [r3, #0]
8000f1a: 2b00 cmp r3, #0
8000f1c: d142 bne.n 8000fa4 <HAL_DFSDM_ChannelMspInit+0xb4>
/* USER CODE END DFSDM1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1;
8000f1e: f44f 3380 mov.w r3, #65536 @ 0x10000
8000f22: 617b str r3, [r7, #20]
PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
8000f24: 2300 movs r3, #0
8000f26: f8c7 3094 str.w r3, [r7, #148] @ 0x94
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000f2a: f107 0314 add.w r3, r7, #20
8000f2e: 4618 mov r0, r3
8000f30: f002 f954 bl 80031dc <HAL_RCCEx_PeriphCLKConfig>
8000f34: 4603 mov r3, r0
8000f36: 2b00 cmp r3, #0
8000f38: d001 beq.n 8000f3e <HAL_DFSDM_ChannelMspInit+0x4e>
{
Error_Handler();
8000f3a: f7ff ffaf bl 8000e9c <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_DFSDM1_CLK_ENABLE();
8000f3e: 4b1c ldr r3, [pc, #112] @ (8000fb0 <HAL_DFSDM_ChannelMspInit+0xc0>)
8000f40: 6e1b ldr r3, [r3, #96] @ 0x60
8000f42: 4a1b ldr r2, [pc, #108] @ (8000fb0 <HAL_DFSDM_ChannelMspInit+0xc0>)
8000f44: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8000f48: 6613 str r3, [r2, #96] @ 0x60
8000f4a: 4b19 ldr r3, [pc, #100] @ (8000fb0 <HAL_DFSDM_ChannelMspInit+0xc0>)
8000f4c: 6e1b ldr r3, [r3, #96] @ 0x60
8000f4e: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8000f52: 613b str r3, [r7, #16]
8000f54: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOE_CLK_ENABLE();
8000f56: 4b16 ldr r3, [pc, #88] @ (8000fb0 <HAL_DFSDM_ChannelMspInit+0xc0>)
8000f58: 6cdb ldr r3, [r3, #76] @ 0x4c
8000f5a: 4a15 ldr r2, [pc, #84] @ (8000fb0 <HAL_DFSDM_ChannelMspInit+0xc0>)
8000f5c: f043 0310 orr.w r3, r3, #16
8000f60: 64d3 str r3, [r2, #76] @ 0x4c
8000f62: 4b13 ldr r3, [pc, #76] @ (8000fb0 <HAL_DFSDM_ChannelMspInit+0xc0>)
8000f64: 6cdb ldr r3, [r3, #76] @ 0x4c
8000f66: f003 0310 and.w r3, r3, #16
8000f6a: 60fb str r3, [r7, #12]
8000f6c: 68fb ldr r3, [r7, #12]
/**DFSDM1 GPIO Configuration
PE7 ------> DFSDM1_DATIN2
PE9 ------> DFSDM1_CKOUT
*/
GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin;
8000f6e: f44f 7320 mov.w r3, #640 @ 0x280
8000f72: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f76: 2302 movs r3, #2
8000f78: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f7c: 2300 movs r3, #0
8000f7e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000f82: 2300 movs r3, #0
8000f84: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1;
8000f88: 2306 movs r3, #6
8000f8a: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000f8e: f107 039c add.w r3, r7, #156 @ 0x9c
8000f92: 4619 mov r1, r3
8000f94: 4807 ldr r0, [pc, #28] @ (8000fb4 <HAL_DFSDM_ChannelMspInit+0xc4>)
8000f96: f000 fd7f bl 8001a98 <HAL_GPIO_Init>
/* USER CODE BEGIN DFSDM1_MspInit 1 */
/* USER CODE END DFSDM1_MspInit 1 */
DFSDM1_Init++;
8000f9a: 4b04 ldr r3, [pc, #16] @ (8000fac <HAL_DFSDM_ChannelMspInit+0xbc>)
8000f9c: 681b ldr r3, [r3, #0]
8000f9e: 3301 adds r3, #1
8000fa0: 4a02 ldr r2, [pc, #8] @ (8000fac <HAL_DFSDM_ChannelMspInit+0xbc>)
8000fa2: 6013 str r3, [r2, #0]
}
}
8000fa4: bf00 nop
8000fa6: 37b0 adds r7, #176 @ 0xb0
8000fa8: 46bd mov sp, r7
8000faa: bd80 pop {r7, pc}
8000fac: 20000758 .word 0x20000758
8000fb0: 40021000 .word 0x40021000
8000fb4: 48001000 .word 0x48001000
08000fb8 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8000fb8: b580 push {r7, lr}
8000fba: b0ac sub sp, #176 @ 0xb0
8000fbc: af00 add r7, sp, #0
8000fbe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000fc0: f107 039c add.w r3, r7, #156 @ 0x9c
8000fc4: 2200 movs r2, #0
8000fc6: 601a str r2, [r3, #0]
8000fc8: 605a str r2, [r3, #4]
8000fca: 609a str r2, [r3, #8]
8000fcc: 60da str r2, [r3, #12]
8000fce: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000fd0: f107 0314 add.w r3, r7, #20
8000fd4: 2288 movs r2, #136 @ 0x88
8000fd6: 2100 movs r1, #0
8000fd8: 4618 mov r0, r3
8000fda: f003 fe3c bl 8004c56 <memset>
if(hi2c->Instance==I2C2)
8000fde: 687b ldr r3, [r7, #4]
8000fe0: 681b ldr r3, [r3, #0]
8000fe2: 4a21 ldr r2, [pc, #132] @ (8001068 <HAL_I2C_MspInit+0xb0>)
8000fe4: 4293 cmp r3, r2
8000fe6: d13b bne.n 8001060 <HAL_I2C_MspInit+0xa8>
/* USER CODE END I2C2_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
8000fe8: 2380 movs r3, #128 @ 0x80
8000fea: 617b str r3, [r7, #20]
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
8000fec: 2300 movs r3, #0
8000fee: 66bb str r3, [r7, #104] @ 0x68
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000ff0: f107 0314 add.w r3, r7, #20
8000ff4: 4618 mov r0, r3
8000ff6: f002 f8f1 bl 80031dc <HAL_RCCEx_PeriphCLKConfig>
8000ffa: 4603 mov r3, r0
8000ffc: 2b00 cmp r3, #0
8000ffe: d001 beq.n 8001004 <HAL_I2C_MspInit+0x4c>
{
Error_Handler();
8001000: f7ff ff4c bl 8000e9c <Error_Handler>
}
__HAL_RCC_GPIOB_CLK_ENABLE();
8001004: 4b19 ldr r3, [pc, #100] @ (800106c <HAL_I2C_MspInit+0xb4>)
8001006: 6cdb ldr r3, [r3, #76] @ 0x4c
8001008: 4a18 ldr r2, [pc, #96] @ (800106c <HAL_I2C_MspInit+0xb4>)
800100a: f043 0302 orr.w r3, r3, #2
800100e: 64d3 str r3, [r2, #76] @ 0x4c
8001010: 4b16 ldr r3, [pc, #88] @ (800106c <HAL_I2C_MspInit+0xb4>)
8001012: 6cdb ldr r3, [r3, #76] @ 0x4c
8001014: f003 0302 and.w r3, r3, #2
8001018: 613b str r3, [r7, #16]
800101a: 693b ldr r3, [r7, #16]
/**I2C2 GPIO Configuration
PB10 ------> I2C2_SCL
PB11 ------> I2C2_SDA
*/
GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin;
800101c: f44f 6340 mov.w r3, #3072 @ 0xc00
8001020: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8001024: 2312 movs r3, #18
8001026: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_PULLUP;
800102a: 2301 movs r3, #1
800102c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001030: 2303 movs r3, #3
8001032: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
8001036: 2304 movs r3, #4
8001038: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800103c: f107 039c add.w r3, r7, #156 @ 0x9c
8001040: 4619 mov r1, r3
8001042: 480b ldr r0, [pc, #44] @ (8001070 <HAL_I2C_MspInit+0xb8>)
8001044: f000 fd28 bl 8001a98 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C2_CLK_ENABLE();
8001048: 4b08 ldr r3, [pc, #32] @ (800106c <HAL_I2C_MspInit+0xb4>)
800104a: 6d9b ldr r3, [r3, #88] @ 0x58
800104c: 4a07 ldr r2, [pc, #28] @ (800106c <HAL_I2C_MspInit+0xb4>)
800104e: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8001052: 6593 str r3, [r2, #88] @ 0x58
8001054: 4b05 ldr r3, [pc, #20] @ (800106c <HAL_I2C_MspInit+0xb4>)
8001056: 6d9b ldr r3, [r3, #88] @ 0x58
8001058: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800105c: 60fb str r3, [r7, #12]
800105e: 68fb ldr r3, [r7, #12]
/* USER CODE END I2C2_MspInit 1 */
}
}
8001060: bf00 nop
8001062: 37b0 adds r7, #176 @ 0xb0
8001064: 46bd mov sp, r7
8001066: bd80 pop {r7, pc}
8001068: 40005800 .word 0x40005800
800106c: 40021000 .word 0x40021000
8001070: 48000400 .word 0x48000400
08001074 <HAL_QSPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hqspi: QSPI handle pointer
* @retval None
*/
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
{
8001074: b580 push {r7, lr}
8001076: b08a sub sp, #40 @ 0x28
8001078: af00 add r7, sp, #0
800107a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800107c: f107 0314 add.w r3, r7, #20
8001080: 2200 movs r2, #0
8001082: 601a str r2, [r3, #0]
8001084: 605a str r2, [r3, #4]
8001086: 609a str r2, [r3, #8]
8001088: 60da str r2, [r3, #12]
800108a: 611a str r2, [r3, #16]
if(hqspi->Instance==QUADSPI)
800108c: 687b ldr r3, [r7, #4]
800108e: 681b ldr r3, [r3, #0]
8001090: 4a17 ldr r2, [pc, #92] @ (80010f0 <HAL_QSPI_MspInit+0x7c>)
8001092: 4293 cmp r3, r2
8001094: d128 bne.n 80010e8 <HAL_QSPI_MspInit+0x74>
{
/* USER CODE BEGIN QUADSPI_MspInit 0 */
/* USER CODE END QUADSPI_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_QSPI_CLK_ENABLE();
8001096: 4b17 ldr r3, [pc, #92] @ (80010f4 <HAL_QSPI_MspInit+0x80>)
8001098: 6d1b ldr r3, [r3, #80] @ 0x50
800109a: 4a16 ldr r2, [pc, #88] @ (80010f4 <HAL_QSPI_MspInit+0x80>)
800109c: f443 7380 orr.w r3, r3, #256 @ 0x100
80010a0: 6513 str r3, [r2, #80] @ 0x50
80010a2: 4b14 ldr r3, [pc, #80] @ (80010f4 <HAL_QSPI_MspInit+0x80>)
80010a4: 6d1b ldr r3, [r3, #80] @ 0x50
80010a6: f403 7380 and.w r3, r3, #256 @ 0x100
80010aa: 613b str r3, [r7, #16]
80010ac: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOE_CLK_ENABLE();
80010ae: 4b11 ldr r3, [pc, #68] @ (80010f4 <HAL_QSPI_MspInit+0x80>)
80010b0: 6cdb ldr r3, [r3, #76] @ 0x4c
80010b2: 4a10 ldr r2, [pc, #64] @ (80010f4 <HAL_QSPI_MspInit+0x80>)
80010b4: f043 0310 orr.w r3, r3, #16
80010b8: 64d3 str r3, [r2, #76] @ 0x4c
80010ba: 4b0e ldr r3, [pc, #56] @ (80010f4 <HAL_QSPI_MspInit+0x80>)
80010bc: 6cdb ldr r3, [r3, #76] @ 0x4c
80010be: f003 0310 and.w r3, r3, #16
80010c2: 60fb str r3, [r7, #12]
80010c4: 68fb ldr r3, [r7, #12]
PE12 ------> QUADSPI_BK1_IO0
PE13 ------> QUADSPI_BK1_IO1
PE14 ------> QUADSPI_BK1_IO2
PE15 ------> QUADSPI_BK1_IO3
*/
GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin
80010c6: f44f 437c mov.w r3, #64512 @ 0xfc00
80010ca: 617b str r3, [r7, #20]
|QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010cc: 2302 movs r3, #2
80010ce: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010d0: 2300 movs r3, #0
80010d2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80010d4: 2303 movs r3, #3
80010d6: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
80010d8: 230a movs r3, #10
80010da: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
80010dc: f107 0314 add.w r3, r7, #20
80010e0: 4619 mov r1, r3
80010e2: 4805 ldr r0, [pc, #20] @ (80010f8 <HAL_QSPI_MspInit+0x84>)
80010e4: f000 fcd8 bl 8001a98 <HAL_GPIO_Init>
/* USER CODE END QUADSPI_MspInit 1 */
}
}
80010e8: bf00 nop
80010ea: 3728 adds r7, #40 @ 0x28
80010ec: 46bd mov sp, r7
80010ee: bd80 pop {r7, pc}
80010f0: a0001000 .word 0xa0001000
80010f4: 40021000 .word 0x40021000
80010f8: 48001000 .word 0x48001000
080010fc <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80010fc: b580 push {r7, lr}
80010fe: b08a sub sp, #40 @ 0x28
8001100: af00 add r7, sp, #0
8001102: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001104: f107 0314 add.w r3, r7, #20
8001108: 2200 movs r2, #0
800110a: 601a str r2, [r3, #0]
800110c: 605a str r2, [r3, #4]
800110e: 609a str r2, [r3, #8]
8001110: 60da str r2, [r3, #12]
8001112: 611a str r2, [r3, #16]
if(hspi->Instance==SPI3)
8001114: 687b ldr r3, [r7, #4]
8001116: 681b ldr r3, [r3, #0]
8001118: 4a17 ldr r2, [pc, #92] @ (8001178 <HAL_SPI_MspInit+0x7c>)
800111a: 4293 cmp r3, r2
800111c: d128 bne.n 8001170 <HAL_SPI_MspInit+0x74>
{
/* USER CODE BEGIN SPI3_MspInit 0 */
/* USER CODE END SPI3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI3_CLK_ENABLE();
800111e: 4b17 ldr r3, [pc, #92] @ (800117c <HAL_SPI_MspInit+0x80>)
8001120: 6d9b ldr r3, [r3, #88] @ 0x58
8001122: 4a16 ldr r2, [pc, #88] @ (800117c <HAL_SPI_MspInit+0x80>)
8001124: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8001128: 6593 str r3, [r2, #88] @ 0x58
800112a: 4b14 ldr r3, [pc, #80] @ (800117c <HAL_SPI_MspInit+0x80>)
800112c: 6d9b ldr r3, [r3, #88] @ 0x58
800112e: f403 4300 and.w r3, r3, #32768 @ 0x8000
8001132: 613b str r3, [r7, #16]
8001134: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001136: 4b11 ldr r3, [pc, #68] @ (800117c <HAL_SPI_MspInit+0x80>)
8001138: 6cdb ldr r3, [r3, #76] @ 0x4c
800113a: 4a10 ldr r2, [pc, #64] @ (800117c <HAL_SPI_MspInit+0x80>)
800113c: f043 0304 orr.w r3, r3, #4
8001140: 64d3 str r3, [r2, #76] @ 0x4c
8001142: 4b0e ldr r3, [pc, #56] @ (800117c <HAL_SPI_MspInit+0x80>)
8001144: 6cdb ldr r3, [r3, #76] @ 0x4c
8001146: f003 0304 and.w r3, r3, #4
800114a: 60fb str r3, [r7, #12]
800114c: 68fb ldr r3, [r7, #12]
/**SPI3 GPIO Configuration
PC10 ------> SPI3_SCK
PC11 ------> SPI3_MISO
PC12 ------> SPI3_MOSI
*/
GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin;
800114e: f44f 53e0 mov.w r3, #7168 @ 0x1c00
8001152: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001154: 2302 movs r3, #2
8001156: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001158: 2300 movs r3, #0
800115a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800115c: 2303 movs r3, #3
800115e: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
8001160: 2306 movs r3, #6
8001162: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001164: f107 0314 add.w r3, r7, #20
8001168: 4619 mov r1, r3
800116a: 4805 ldr r0, [pc, #20] @ (8001180 <HAL_SPI_MspInit+0x84>)
800116c: f000 fc94 bl 8001a98 <HAL_GPIO_Init>
/* USER CODE END SPI3_MspInit 1 */
}
}
8001170: bf00 nop
8001172: 3728 adds r7, #40 @ 0x28
8001174: 46bd mov sp, r7
8001176: bd80 pop {r7, pc}
8001178: 40003c00 .word 0x40003c00
800117c: 40021000 .word 0x40021000
8001180: 48000800 .word 0x48000800
08001184 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001184: b580 push {r7, lr}
8001186: b0ae sub sp, #184 @ 0xb8
8001188: af00 add r7, sp, #0
800118a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800118c: f107 03a4 add.w r3, r7, #164 @ 0xa4
8001190: 2200 movs r2, #0
8001192: 601a str r2, [r3, #0]
8001194: 605a str r2, [r3, #4]
8001196: 609a str r2, [r3, #8]
8001198: 60da str r2, [r3, #12]
800119a: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
800119c: f107 031c add.w r3, r7, #28
80011a0: 2288 movs r2, #136 @ 0x88
80011a2: 2100 movs r1, #0
80011a4: 4618 mov r0, r3
80011a6: f003 fd56 bl 8004c56 <memset>
if(huart->Instance==USART1)
80011aa: 687b ldr r3, [r7, #4]
80011ac: 681b ldr r3, [r3, #0]
80011ae: 4a42 ldr r2, [pc, #264] @ (80012b8 <HAL_UART_MspInit+0x134>)
80011b0: 4293 cmp r3, r2
80011b2: d13b bne.n 800122c <HAL_UART_MspInit+0xa8>
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
80011b4: 2301 movs r3, #1
80011b6: 61fb str r3, [r7, #28]
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
80011b8: 2300 movs r3, #0
80011ba: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80011bc: f107 031c add.w r3, r7, #28
80011c0: 4618 mov r0, r3
80011c2: f002 f80b bl 80031dc <HAL_RCCEx_PeriphCLKConfig>
80011c6: 4603 mov r3, r0
80011c8: 2b00 cmp r3, #0
80011ca: d001 beq.n 80011d0 <HAL_UART_MspInit+0x4c>
{
Error_Handler();
80011cc: f7ff fe66 bl 8000e9c <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
80011d0: 4b3a ldr r3, [pc, #232] @ (80012bc <HAL_UART_MspInit+0x138>)
80011d2: 6e1b ldr r3, [r3, #96] @ 0x60
80011d4: 4a39 ldr r2, [pc, #228] @ (80012bc <HAL_UART_MspInit+0x138>)
80011d6: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80011da: 6613 str r3, [r2, #96] @ 0x60
80011dc: 4b37 ldr r3, [pc, #220] @ (80012bc <HAL_UART_MspInit+0x138>)
80011de: 6e1b ldr r3, [r3, #96] @ 0x60
80011e0: f403 4380 and.w r3, r3, #16384 @ 0x4000
80011e4: 61bb str r3, [r7, #24]
80011e6: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOB_CLK_ENABLE();
80011e8: 4b34 ldr r3, [pc, #208] @ (80012bc <HAL_UART_MspInit+0x138>)
80011ea: 6cdb ldr r3, [r3, #76] @ 0x4c
80011ec: 4a33 ldr r2, [pc, #204] @ (80012bc <HAL_UART_MspInit+0x138>)
80011ee: f043 0302 orr.w r3, r3, #2
80011f2: 64d3 str r3, [r2, #76] @ 0x4c
80011f4: 4b31 ldr r3, [pc, #196] @ (80012bc <HAL_UART_MspInit+0x138>)
80011f6: 6cdb ldr r3, [r3, #76] @ 0x4c
80011f8: f003 0302 and.w r3, r3, #2
80011fc: 617b str r3, [r7, #20]
80011fe: 697b ldr r3, [r7, #20]
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin;
8001200: 23c0 movs r3, #192 @ 0xc0
8001202: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001206: 2302 movs r3, #2
8001208: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Pull = GPIO_NOPULL;
800120c: 2300 movs r3, #0
800120e: f8c7 30ac str.w r3, [r7, #172] @ 0xac
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001212: 2303 movs r3, #3
8001214: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001218: 2307 movs r3, #7
800121a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800121e: f107 03a4 add.w r3, r7, #164 @ 0xa4
8001222: 4619 mov r1, r3
8001224: 4826 ldr r0, [pc, #152] @ (80012c0 <HAL_UART_MspInit+0x13c>)
8001226: f000 fc37 bl 8001a98 <HAL_GPIO_Init>
/* USER CODE BEGIN USART3_MspInit 1 */
/* USER CODE END USART3_MspInit 1 */
}
}
800122a: e040 b.n 80012ae <HAL_UART_MspInit+0x12a>
else if(huart->Instance==USART3)
800122c: 687b ldr r3, [r7, #4]
800122e: 681b ldr r3, [r3, #0]
8001230: 4a24 ldr r2, [pc, #144] @ (80012c4 <HAL_UART_MspInit+0x140>)
8001232: 4293 cmp r3, r2
8001234: d13b bne.n 80012ae <HAL_UART_MspInit+0x12a>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3;
8001236: 2304 movs r3, #4
8001238: 61fb str r3, [r7, #28]
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
800123a: 2300 movs r3, #0
800123c: 65fb str r3, [r7, #92] @ 0x5c
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
800123e: f107 031c add.w r3, r7, #28
8001242: 4618 mov r0, r3
8001244: f001 ffca bl 80031dc <HAL_RCCEx_PeriphCLKConfig>
8001248: 4603 mov r3, r0
800124a: 2b00 cmp r3, #0
800124c: d001 beq.n 8001252 <HAL_UART_MspInit+0xce>
Error_Handler();
800124e: f7ff fe25 bl 8000e9c <Error_Handler>
__HAL_RCC_USART3_CLK_ENABLE();
8001252: 4b1a ldr r3, [pc, #104] @ (80012bc <HAL_UART_MspInit+0x138>)
8001254: 6d9b ldr r3, [r3, #88] @ 0x58
8001256: 4a19 ldr r2, [pc, #100] @ (80012bc <HAL_UART_MspInit+0x138>)
8001258: f443 2380 orr.w r3, r3, #262144 @ 0x40000
800125c: 6593 str r3, [r2, #88] @ 0x58
800125e: 4b17 ldr r3, [pc, #92] @ (80012bc <HAL_UART_MspInit+0x138>)
8001260: 6d9b ldr r3, [r3, #88] @ 0x58
8001262: f403 2380 and.w r3, r3, #262144 @ 0x40000
8001266: 613b str r3, [r7, #16]
8001268: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOD_CLK_ENABLE();
800126a: 4b14 ldr r3, [pc, #80] @ (80012bc <HAL_UART_MspInit+0x138>)
800126c: 6cdb ldr r3, [r3, #76] @ 0x4c
800126e: 4a13 ldr r2, [pc, #76] @ (80012bc <HAL_UART_MspInit+0x138>)
8001270: f043 0308 orr.w r3, r3, #8
8001274: 64d3 str r3, [r2, #76] @ 0x4c
8001276: 4b11 ldr r3, [pc, #68] @ (80012bc <HAL_UART_MspInit+0x138>)
8001278: 6cdb ldr r3, [r3, #76] @ 0x4c
800127a: f003 0308 and.w r3, r3, #8
800127e: 60fb str r3, [r7, #12]
8001280: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin;
8001282: f44f 7340 mov.w r3, #768 @ 0x300
8001286: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800128a: 2302 movs r3, #2
800128c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001290: 2300 movs r3, #0
8001292: f8c7 30ac str.w r3, [r7, #172] @ 0xac
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001296: 2303 movs r3, #3
8001298: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
800129c: 2307 movs r3, #7
800129e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80012a2: f107 03a4 add.w r3, r7, #164 @ 0xa4
80012a6: 4619 mov r1, r3
80012a8: 4807 ldr r0, [pc, #28] @ (80012c8 <HAL_UART_MspInit+0x144>)
80012aa: f000 fbf5 bl 8001a98 <HAL_GPIO_Init>
}
80012ae: bf00 nop
80012b0: 37b8 adds r7, #184 @ 0xb8
80012b2: 46bd mov sp, r7
80012b4: bd80 pop {r7, pc}
80012b6: bf00 nop
80012b8: 40013800 .word 0x40013800
80012bc: 40021000 .word 0x40021000
80012c0: 48000400 .word 0x48000400
80012c4: 40004800 .word 0x40004800
80012c8: 48000c00 .word 0x48000c00
080012cc <HAL_PCD_MspInit>:
* This function configures the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
80012cc: b580 push {r7, lr}
80012ce: b0ac sub sp, #176 @ 0xb0
80012d0: af00 add r7, sp, #0
80012d2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80012d4: f107 039c add.w r3, r7, #156 @ 0x9c
80012d8: 2200 movs r2, #0
80012da: 601a str r2, [r3, #0]
80012dc: 605a str r2, [r3, #4]
80012de: 609a str r2, [r3, #8]
80012e0: 60da str r2, [r3, #12]
80012e2: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
80012e4: f107 0314 add.w r3, r7, #20
80012e8: 2288 movs r2, #136 @ 0x88
80012ea: 2100 movs r1, #0
80012ec: 4618 mov r0, r3
80012ee: f003 fcb2 bl 8004c56 <memset>
if(hpcd->Instance==USB_OTG_FS)
80012f2: 687b ldr r3, [r7, #4]
80012f4: 681b ldr r3, [r3, #0]
80012f6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80012fa: d17c bne.n 80013f6 <HAL_PCD_MspInit+0x12a>
/* USER CODE END USB_OTG_FS_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
80012fc: f44f 5300 mov.w r3, #8192 @ 0x2000
8001300: 617b str r3, [r7, #20]
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
8001302: f04f 6380 mov.w r3, #67108864 @ 0x4000000
8001306: f8c7 3080 str.w r3, [r7, #128] @ 0x80
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
800130a: 2301 movs r3, #1
800130c: 61bb str r3, [r7, #24]
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
800130e: 2301 movs r3, #1
8001310: 61fb str r3, [r7, #28]
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
8001312: 2318 movs r3, #24
8001314: 623b str r3, [r7, #32]
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
8001316: 2307 movs r3, #7
8001318: 627b str r3, [r7, #36] @ 0x24
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
800131a: 2302 movs r3, #2
800131c: 62bb str r3, [r7, #40] @ 0x28
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
800131e: 2302 movs r3, #2
8001320: 62fb str r3, [r7, #44] @ 0x2c
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
8001322: f44f 1380 mov.w r3, #1048576 @ 0x100000
8001326: 633b str r3, [r7, #48] @ 0x30
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001328: f107 0314 add.w r3, r7, #20
800132c: 4618 mov r0, r3
800132e: f001 ff55 bl 80031dc <HAL_RCCEx_PeriphCLKConfig>
8001332: 4603 mov r3, r0
8001334: 2b00 cmp r3, #0
8001336: d001 beq.n 800133c <HAL_PCD_MspInit+0x70>
{
Error_Handler();
8001338: f7ff fdb0 bl 8000e9c <Error_Handler>
}
__HAL_RCC_GPIOA_CLK_ENABLE();
800133c: 4b30 ldr r3, [pc, #192] @ (8001400 <HAL_PCD_MspInit+0x134>)
800133e: 6cdb ldr r3, [r3, #76] @ 0x4c
8001340: 4a2f ldr r2, [pc, #188] @ (8001400 <HAL_PCD_MspInit+0x134>)
8001342: f043 0301 orr.w r3, r3, #1
8001346: 64d3 str r3, [r2, #76] @ 0x4c
8001348: 4b2d ldr r3, [pc, #180] @ (8001400 <HAL_PCD_MspInit+0x134>)
800134a: 6cdb ldr r3, [r3, #76] @ 0x4c
800134c: f003 0301 and.w r3, r3, #1
8001350: 613b str r3, [r7, #16]
8001352: 693b ldr r3, [r7, #16]
PA9 ------> USB_OTG_FS_VBUS
PA10 ------> USB_OTG_FS_ID
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin;
8001354: f44f 7300 mov.w r3, #512 @ 0x200
8001358: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800135c: 2300 movs r3, #0
800135e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001362: 2300 movs r3, #0
8001364: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
8001368: f107 039c add.w r3, r7, #156 @ 0x9c
800136c: 4619 mov r1, r3
800136e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001372: f000 fb91 bl 8001a98 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin;
8001376: f44f 53e0 mov.w r3, #7168 @ 0x1c00
800137a: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800137e: 2302 movs r3, #2
8001380: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001384: 2300 movs r3, #0
8001386: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800138a: 2303 movs r3, #3
800138c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
8001390: 230a movs r3, #10
8001392: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001396: f107 039c add.w r3, r7, #156 @ 0x9c
800139a: 4619 mov r1, r3
800139c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80013a0: f000 fb7a bl 8001a98 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
80013a4: 4b16 ldr r3, [pc, #88] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013a6: 6cdb ldr r3, [r3, #76] @ 0x4c
80013a8: 4a15 ldr r2, [pc, #84] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013aa: f443 5380 orr.w r3, r3, #4096 @ 0x1000
80013ae: 64d3 str r3, [r2, #76] @ 0x4c
80013b0: 4b13 ldr r3, [pc, #76] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013b2: 6cdb ldr r3, [r3, #76] @ 0x4c
80013b4: f403 5380 and.w r3, r3, #4096 @ 0x1000
80013b8: 60fb str r3, [r7, #12]
80013ba: 68fb ldr r3, [r7, #12]
/* Enable VDDUSB */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80013bc: 4b10 ldr r3, [pc, #64] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013be: 6d9b ldr r3, [r3, #88] @ 0x58
80013c0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80013c4: 2b00 cmp r3, #0
80013c6: d114 bne.n 80013f2 <HAL_PCD_MspInit+0x126>
{
__HAL_RCC_PWR_CLK_ENABLE();
80013c8: 4b0d ldr r3, [pc, #52] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013ca: 6d9b ldr r3, [r3, #88] @ 0x58
80013cc: 4a0c ldr r2, [pc, #48] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013ce: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80013d2: 6593 str r3, [r2, #88] @ 0x58
80013d4: 4b0a ldr r3, [pc, #40] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013d6: 6d9b ldr r3, [r3, #88] @ 0x58
80013d8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80013dc: 60bb str r3, [r7, #8]
80013de: 68bb ldr r3, [r7, #8]
HAL_PWREx_EnableVddUSB();
80013e0: f001 f830 bl 8002444 <HAL_PWREx_EnableVddUSB>
__HAL_RCC_PWR_CLK_DISABLE();
80013e4: 4b06 ldr r3, [pc, #24] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013e6: 6d9b ldr r3, [r3, #88] @ 0x58
80013e8: 4a05 ldr r2, [pc, #20] @ (8001400 <HAL_PCD_MspInit+0x134>)
80013ea: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80013ee: 6593 str r3, [r2, #88] @ 0x58
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
80013f0: e001 b.n 80013f6 <HAL_PCD_MspInit+0x12a>
HAL_PWREx_EnableVddUSB();
80013f2: f001 f827 bl 8002444 <HAL_PWREx_EnableVddUSB>
}
80013f6: bf00 nop
80013f8: 37b0 adds r7, #176 @ 0xb0
80013fa: 46bd mov sp, r7
80013fc: bd80 pop {r7, pc}
80013fe: bf00 nop
8001400: 40021000 .word 0x40021000
08001404 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001404: b480 push {r7}
8001406: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001408: bf00 nop
800140a: e7fd b.n 8001408 <NMI_Handler+0x4>
0800140c <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800140c: b480 push {r7}
800140e: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001410: bf00 nop
8001412: e7fd b.n 8001410 <HardFault_Handler+0x4>
08001414 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001414: b480 push {r7}
8001416: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001418: bf00 nop
800141a: e7fd b.n 8001418 <MemManage_Handler+0x4>
0800141c <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800141c: b480 push {r7}
800141e: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001420: bf00 nop
8001422: e7fd b.n 8001420 <BusFault_Handler+0x4>
08001424 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001424: b480 push {r7}
8001426: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001428: bf00 nop
800142a: e7fd b.n 8001428 <UsageFault_Handler+0x4>
0800142c <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800142c: b480 push {r7}
800142e: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001430: bf00 nop
8001432: 46bd mov sp, r7
8001434: f85d 7b04 ldr.w r7, [sp], #4
8001438: 4770 bx lr
0800143a <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
800143a: b480 push {r7}
800143c: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800143e: bf00 nop
8001440: 46bd mov sp, r7
8001442: f85d 7b04 ldr.w r7, [sp], #4
8001446: 4770 bx lr
08001448 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001448: b480 push {r7}
800144a: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800144c: bf00 nop
800144e: 46bd mov sp, r7
8001450: f85d 7b04 ldr.w r7, [sp], #4
8001454: 4770 bx lr
08001456 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001456: b580 push {r7, lr}
8001458: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800145a: f000 f8bb bl 80015d4 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800145e: bf00 nop
8001460: bd80 pop {r7, pc}
08001462 <EXTI9_5_IRQHandler>:
/**
* @brief This function handles EXTI line[9:5] interrupts.
*/
void EXTI9_5_IRQHandler(void)
{
8001462: b580 push {r7, lr}
8001464: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI9_5_IRQn 0 */
/* USER CODE END EXTI9_5_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(SPSGRF_915_GPIO3_EXTI5_Pin);
8001466: 2020 movs r0, #32
8001468: f000 fcf0 bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(SPBTLE_RF_IRQ_EXTI6_Pin);
800146c: 2040 movs r0, #64 @ 0x40
800146e: f000 fced bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(VL53L0X_GPIO1_EXTI7_Pin);
8001472: 2080 movs r0, #128 @ 0x80
8001474: f000 fcea bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(LSM3MDL_DRDY_EXTI8_Pin);
8001478: f44f 7080 mov.w r0, #256 @ 0x100
800147c: f000 fce6 bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI9_5_IRQn 1 */
/* USER CODE END EXTI9_5_IRQn 1 */
}
8001480: bf00 nop
8001482: bd80 pop {r7, pc}
08001484 <EXTI15_10_IRQHandler>:
/**
* @brief This function handles EXTI line[15:10] interrupts.
*/
void EXTI15_10_IRQHandler(void)
{
8001484: b580 push {r7, lr}
8001486: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(LPS22HB_INT_DRDY_EXTI0_Pin);
8001488: f44f 6080 mov.w r0, #1024 @ 0x400
800148c: f000 fcde bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(LSM6DSL_INT1_EXTI11_Pin);
8001490: f44f 6000 mov.w r0, #2048 @ 0x800
8001494: f000 fcda bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(BUTTON_EXTI13_Pin);
8001498: f44f 5000 mov.w r0, #8192 @ 0x2000
800149c: f000 fcd6 bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(ARD_D2_Pin);
80014a0: f44f 4080 mov.w r0, #16384 @ 0x4000
80014a4: f000 fcd2 bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(HTS221_DRDY_EXTI15_Pin);
80014a8: f44f 4000 mov.w r0, #32768 @ 0x8000
80014ac: f000 fcce bl 8001e4c <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 1 */
}
80014b0: bf00 nop
80014b2: bd80 pop {r7, pc}
080014b4 <SystemInit>:
* @brief Setup the microcontroller system.
* @retval None
*/
void SystemInit(void)
{
80014b4: b480 push {r7}
80014b6: af00 add r7, sp, #0
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
80014b8: 4b06 ldr r3, [pc, #24] @ (80014d4 <SystemInit+0x20>)
80014ba: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80014be: 4a05 ldr r2, [pc, #20] @ (80014d4 <SystemInit+0x20>)
80014c0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80014c4: f8c2 3088 str.w r3, [r2, #136] @ 0x88
#endif
}
80014c8: bf00 nop
80014ca: 46bd mov sp, r7
80014cc: f85d 7b04 ldr.w r7, [sp], #4
80014d0: 4770 bx lr
80014d2: bf00 nop
80014d4: e000ed00 .word 0xe000ed00
080014d8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
80014d8: f8df d034 ldr.w sp, [pc, #52] @ 8001510 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
80014dc: f7ff ffea bl 80014b4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80014e0: 480c ldr r0, [pc, #48] @ (8001514 <LoopForever+0x6>)
ldr r1, =_edata
80014e2: 490d ldr r1, [pc, #52] @ (8001518 <LoopForever+0xa>)
ldr r2, =_sidata
80014e4: 4a0d ldr r2, [pc, #52] @ (800151c <LoopForever+0xe>)
movs r3, #0
80014e6: 2300 movs r3, #0
b LoopCopyDataInit
80014e8: e002 b.n 80014f0 <LoopCopyDataInit>
080014ea <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80014ea: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80014ec: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80014ee: 3304 adds r3, #4
080014f0 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80014f0: 18c4 adds r4, r0, r3
cmp r4, r1
80014f2: 428c cmp r4, r1
bcc CopyDataInit
80014f4: d3f9 bcc.n 80014ea <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80014f6: 4a0a ldr r2, [pc, #40] @ (8001520 <LoopForever+0x12>)
ldr r4, =_ebss
80014f8: 4c0a ldr r4, [pc, #40] @ (8001524 <LoopForever+0x16>)
movs r3, #0
80014fa: 2300 movs r3, #0
b LoopFillZerobss
80014fc: e001 b.n 8001502 <LoopFillZerobss>
080014fe <FillZerobss>:
FillZerobss:
str r3, [r2]
80014fe: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001500: 3204 adds r2, #4
08001502 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001502: 42a2 cmp r2, r4
bcc FillZerobss
8001504: d3fb bcc.n 80014fe <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001506: f003 fbaf bl 8004c68 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800150a: f7ff f90f bl 800072c <main>
0800150e <LoopForever>:
LoopForever:
b LoopForever
800150e: e7fe b.n 800150e <LoopForever>
ldr sp, =_estack /* Set stack pointer */
8001510: 20018000 .word 0x20018000
ldr r0, =_sdata
8001514: 20000000 .word 0x20000000
ldr r1, =_edata
8001518: 20000010 .word 0x20000010
ldr r2, =_sidata
800151c: 08004d20 .word 0x08004d20
ldr r2, =_sbss
8001520: 20000010 .word 0x20000010
ldr r4, =_ebss
8001524: 20000784 .word 0x20000784
08001528 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001528: e7fe b.n 8001528 <ADC1_2_IRQHandler>
0800152a <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800152a: b580 push {r7, lr}
800152c: b082 sub sp, #8
800152e: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001530: 2300 movs r3, #0
8001532: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001534: 2003 movs r0, #3
8001536: f000 f961 bl 80017fc <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
800153a: 2000 movs r0, #0
800153c: f000 f80e bl 800155c <HAL_InitTick>
8001540: 4603 mov r3, r0
8001542: 2b00 cmp r3, #0
8001544: d002 beq.n 800154c <HAL_Init+0x22>
{
status = HAL_ERROR;
8001546: 2301 movs r3, #1
8001548: 71fb strb r3, [r7, #7]
800154a: e001 b.n 8001550 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
800154c: f7ff fcac bl 8000ea8 <HAL_MspInit>
}
/* Return function status */
return status;
8001550: 79fb ldrb r3, [r7, #7]
}
8001552: 4618 mov r0, r3
8001554: 3708 adds r7, #8
8001556: 46bd mov sp, r7
8001558: bd80 pop {r7, pc}
...
0800155c <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
800155c: b580 push {r7, lr}
800155e: b084 sub sp, #16
8001560: af00 add r7, sp, #0
8001562: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001564: 2300 movs r3, #0
8001566: 73fb strb r3, [r7, #15]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8001568: 4b17 ldr r3, [pc, #92] @ (80015c8 <HAL_InitTick+0x6c>)
800156a: 781b ldrb r3, [r3, #0]
800156c: 2b00 cmp r3, #0
800156e: d023 beq.n 80015b8 <HAL_InitTick+0x5c>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
8001570: 4b16 ldr r3, [pc, #88] @ (80015cc <HAL_InitTick+0x70>)
8001572: 681a ldr r2, [r3, #0]
8001574: 4b14 ldr r3, [pc, #80] @ (80015c8 <HAL_InitTick+0x6c>)
8001576: 781b ldrb r3, [r3, #0]
8001578: 4619 mov r1, r3
800157a: f44f 737a mov.w r3, #1000 @ 0x3e8
800157e: fbb3 f3f1 udiv r3, r3, r1
8001582: fbb2 f3f3 udiv r3, r2, r3
8001586: 4618 mov r0, r3
8001588: f000 f96d bl 8001866 <HAL_SYSTICK_Config>
800158c: 4603 mov r3, r0
800158e: 2b00 cmp r3, #0
8001590: d10f bne.n 80015b2 <HAL_InitTick+0x56>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001592: 687b ldr r3, [r7, #4]
8001594: 2b0f cmp r3, #15
8001596: d809 bhi.n 80015ac <HAL_InitTick+0x50>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001598: 2200 movs r2, #0
800159a: 6879 ldr r1, [r7, #4]
800159c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80015a0: f000 f937 bl 8001812 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80015a4: 4a0a ldr r2, [pc, #40] @ (80015d0 <HAL_InitTick+0x74>)
80015a6: 687b ldr r3, [r7, #4]
80015a8: 6013 str r3, [r2, #0]
80015aa: e007 b.n 80015bc <HAL_InitTick+0x60>
}
else
{
status = HAL_ERROR;
80015ac: 2301 movs r3, #1
80015ae: 73fb strb r3, [r7, #15]
80015b0: e004 b.n 80015bc <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
80015b2: 2301 movs r3, #1
80015b4: 73fb strb r3, [r7, #15]
80015b6: e001 b.n 80015bc <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
80015b8: 2301 movs r3, #1
80015ba: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
80015bc: 7bfb ldrb r3, [r7, #15]
}
80015be: 4618 mov r0, r3
80015c0: 3710 adds r7, #16
80015c2: 46bd mov sp, r7
80015c4: bd80 pop {r7, pc}
80015c6: bf00 nop
80015c8: 2000000c .word 0x2000000c
80015cc: 20000004 .word 0x20000004
80015d0: 20000008 .word 0x20000008
080015d4 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80015d4: b480 push {r7}
80015d6: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
80015d8: 4b06 ldr r3, [pc, #24] @ (80015f4 <HAL_IncTick+0x20>)
80015da: 781b ldrb r3, [r3, #0]
80015dc: 461a mov r2, r3
80015de: 4b06 ldr r3, [pc, #24] @ (80015f8 <HAL_IncTick+0x24>)
80015e0: 681b ldr r3, [r3, #0]
80015e2: 4413 add r3, r2
80015e4: 4a04 ldr r2, [pc, #16] @ (80015f8 <HAL_IncTick+0x24>)
80015e6: 6013 str r3, [r2, #0]
}
80015e8: bf00 nop
80015ea: 46bd mov sp, r7
80015ec: f85d 7b04 ldr.w r7, [sp], #4
80015f0: 4770 bx lr
80015f2: bf00 nop
80015f4: 2000000c .word 0x2000000c
80015f8: 2000075c .word 0x2000075c
080015fc <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80015fc: b480 push {r7}
80015fe: af00 add r7, sp, #0
return uwTick;
8001600: 4b03 ldr r3, [pc, #12] @ (8001610 <HAL_GetTick+0x14>)
8001602: 681b ldr r3, [r3, #0]
}
8001604: 4618 mov r0, r3
8001606: 46bd mov sp, r7
8001608: f85d 7b04 ldr.w r7, [sp], #4
800160c: 4770 bx lr
800160e: bf00 nop
8001610: 2000075c .word 0x2000075c
08001614 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001614: b580 push {r7, lr}
8001616: b084 sub sp, #16
8001618: af00 add r7, sp, #0
800161a: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
800161c: f7ff ffee bl 80015fc <HAL_GetTick>
8001620: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001622: 687b ldr r3, [r7, #4]
8001624: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
8001626: 68fb ldr r3, [r7, #12]
8001628: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800162c: d005 beq.n 800163a <HAL_Delay+0x26>
{
wait += (uint32_t)uwTickFreq;
800162e: 4b0a ldr r3, [pc, #40] @ (8001658 <HAL_Delay+0x44>)
8001630: 781b ldrb r3, [r3, #0]
8001632: 461a mov r2, r3
8001634: 68fb ldr r3, [r7, #12]
8001636: 4413 add r3, r2
8001638: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
800163a: bf00 nop
800163c: f7ff ffde bl 80015fc <HAL_GetTick>
8001640: 4602 mov r2, r0
8001642: 68bb ldr r3, [r7, #8]
8001644: 1ad3 subs r3, r2, r3
8001646: 68fa ldr r2, [r7, #12]
8001648: 429a cmp r2, r3
800164a: d8f7 bhi.n 800163c <HAL_Delay+0x28>
{
}
}
800164c: bf00 nop
800164e: bf00 nop
8001650: 3710 adds r7, #16
8001652: 46bd mov sp, r7
8001654: bd80 pop {r7, pc}
8001656: bf00 nop
8001658: 2000000c .word 0x2000000c
0800165c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800165c: b480 push {r7}
800165e: b085 sub sp, #20
8001660: af00 add r7, sp, #0
8001662: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001664: 687b ldr r3, [r7, #4]
8001666: f003 0307 and.w r3, r3, #7
800166a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
800166c: 4b0c ldr r3, [pc, #48] @ (80016a0 <__NVIC_SetPriorityGrouping+0x44>)
800166e: 68db ldr r3, [r3, #12]
8001670: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8001672: 68ba ldr r2, [r7, #8]
8001674: f64f 03ff movw r3, #63743 @ 0xf8ff
8001678: 4013 ands r3, r2
800167a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800167c: 68fb ldr r3, [r7, #12]
800167e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001680: 68bb ldr r3, [r7, #8]
8001682: 4313 orrs r3, r2
reg_value = (reg_value |
8001684: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8001688: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800168c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800168e: 4a04 ldr r2, [pc, #16] @ (80016a0 <__NVIC_SetPriorityGrouping+0x44>)
8001690: 68bb ldr r3, [r7, #8]
8001692: 60d3 str r3, [r2, #12]
}
8001694: bf00 nop
8001696: 3714 adds r7, #20
8001698: 46bd mov sp, r7
800169a: f85d 7b04 ldr.w r7, [sp], #4
800169e: 4770 bx lr
80016a0: e000ed00 .word 0xe000ed00
080016a4 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80016a4: b480 push {r7}
80016a6: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80016a8: 4b04 ldr r3, [pc, #16] @ (80016bc <__NVIC_GetPriorityGrouping+0x18>)
80016aa: 68db ldr r3, [r3, #12]
80016ac: 0a1b lsrs r3, r3, #8
80016ae: f003 0307 and.w r3, r3, #7
}
80016b2: 4618 mov r0, r3
80016b4: 46bd mov sp, r7
80016b6: f85d 7b04 ldr.w r7, [sp], #4
80016ba: 4770 bx lr
80016bc: e000ed00 .word 0xe000ed00
080016c0 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80016c0: b480 push {r7}
80016c2: b083 sub sp, #12
80016c4: af00 add r7, sp, #0
80016c6: 4603 mov r3, r0
80016c8: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80016ca: f997 3007 ldrsb.w r3, [r7, #7]
80016ce: 2b00 cmp r3, #0
80016d0: db0b blt.n 80016ea <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80016d2: 79fb ldrb r3, [r7, #7]
80016d4: f003 021f and.w r2, r3, #31
80016d8: 4907 ldr r1, [pc, #28] @ (80016f8 <__NVIC_EnableIRQ+0x38>)
80016da: f997 3007 ldrsb.w r3, [r7, #7]
80016de: 095b lsrs r3, r3, #5
80016e0: 2001 movs r0, #1
80016e2: fa00 f202 lsl.w r2, r0, r2
80016e6: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
80016ea: bf00 nop
80016ec: 370c adds r7, #12
80016ee: 46bd mov sp, r7
80016f0: f85d 7b04 ldr.w r7, [sp], #4
80016f4: 4770 bx lr
80016f6: bf00 nop
80016f8: e000e100 .word 0xe000e100
080016fc <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80016fc: b480 push {r7}
80016fe: b083 sub sp, #12
8001700: af00 add r7, sp, #0
8001702: 4603 mov r3, r0
8001704: 6039 str r1, [r7, #0]
8001706: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001708: f997 3007 ldrsb.w r3, [r7, #7]
800170c: 2b00 cmp r3, #0
800170e: db0a blt.n 8001726 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001710: 683b ldr r3, [r7, #0]
8001712: b2da uxtb r2, r3
8001714: 490c ldr r1, [pc, #48] @ (8001748 <__NVIC_SetPriority+0x4c>)
8001716: f997 3007 ldrsb.w r3, [r7, #7]
800171a: 0112 lsls r2, r2, #4
800171c: b2d2 uxtb r2, r2
800171e: 440b add r3, r1
8001720: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001724: e00a b.n 800173c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001726: 683b ldr r3, [r7, #0]
8001728: b2da uxtb r2, r3
800172a: 4908 ldr r1, [pc, #32] @ (800174c <__NVIC_SetPriority+0x50>)
800172c: 79fb ldrb r3, [r7, #7]
800172e: f003 030f and.w r3, r3, #15
8001732: 3b04 subs r3, #4
8001734: 0112 lsls r2, r2, #4
8001736: b2d2 uxtb r2, r2
8001738: 440b add r3, r1
800173a: 761a strb r2, [r3, #24]
}
800173c: bf00 nop
800173e: 370c adds r7, #12
8001740: 46bd mov sp, r7
8001742: f85d 7b04 ldr.w r7, [sp], #4
8001746: 4770 bx lr
8001748: e000e100 .word 0xe000e100
800174c: e000ed00 .word 0xe000ed00
08001750 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001750: b480 push {r7}
8001752: b089 sub sp, #36 @ 0x24
8001754: af00 add r7, sp, #0
8001756: 60f8 str r0, [r7, #12]
8001758: 60b9 str r1, [r7, #8]
800175a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800175c: 68fb ldr r3, [r7, #12]
800175e: f003 0307 and.w r3, r3, #7
8001762: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001764: 69fb ldr r3, [r7, #28]
8001766: f1c3 0307 rsb r3, r3, #7
800176a: 2b04 cmp r3, #4
800176c: bf28 it cs
800176e: 2304 movcs r3, #4
8001770: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001772: 69fb ldr r3, [r7, #28]
8001774: 3304 adds r3, #4
8001776: 2b06 cmp r3, #6
8001778: d902 bls.n 8001780 <NVIC_EncodePriority+0x30>
800177a: 69fb ldr r3, [r7, #28]
800177c: 3b03 subs r3, #3
800177e: e000 b.n 8001782 <NVIC_EncodePriority+0x32>
8001780: 2300 movs r3, #0
8001782: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001784: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8001788: 69bb ldr r3, [r7, #24]
800178a: fa02 f303 lsl.w r3, r2, r3
800178e: 43da mvns r2, r3
8001790: 68bb ldr r3, [r7, #8]
8001792: 401a ands r2, r3
8001794: 697b ldr r3, [r7, #20]
8001796: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001798: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
800179c: 697b ldr r3, [r7, #20]
800179e: fa01 f303 lsl.w r3, r1, r3
80017a2: 43d9 mvns r1, r3
80017a4: 687b ldr r3, [r7, #4]
80017a6: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80017a8: 4313 orrs r3, r2
);
}
80017aa: 4618 mov r0, r3
80017ac: 3724 adds r7, #36 @ 0x24
80017ae: 46bd mov sp, r7
80017b0: f85d 7b04 ldr.w r7, [sp], #4
80017b4: 4770 bx lr
...
080017b8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80017b8: b580 push {r7, lr}
80017ba: b082 sub sp, #8
80017bc: af00 add r7, sp, #0
80017be: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80017c0: 687b ldr r3, [r7, #4]
80017c2: 3b01 subs r3, #1
80017c4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80017c8: d301 bcc.n 80017ce <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80017ca: 2301 movs r3, #1
80017cc: e00f b.n 80017ee <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80017ce: 4a0a ldr r2, [pc, #40] @ (80017f8 <SysTick_Config+0x40>)
80017d0: 687b ldr r3, [r7, #4]
80017d2: 3b01 subs r3, #1
80017d4: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80017d6: 210f movs r1, #15
80017d8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80017dc: f7ff ff8e bl 80016fc <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80017e0: 4b05 ldr r3, [pc, #20] @ (80017f8 <SysTick_Config+0x40>)
80017e2: 2200 movs r2, #0
80017e4: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80017e6: 4b04 ldr r3, [pc, #16] @ (80017f8 <SysTick_Config+0x40>)
80017e8: 2207 movs r2, #7
80017ea: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80017ec: 2300 movs r3, #0
}
80017ee: 4618 mov r0, r3
80017f0: 3708 adds r7, #8
80017f2: 46bd mov sp, r7
80017f4: bd80 pop {r7, pc}
80017f6: bf00 nop
80017f8: e000e010 .word 0xe000e010
080017fc <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80017fc: b580 push {r7, lr}
80017fe: b082 sub sp, #8
8001800: af00 add r7, sp, #0
8001802: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001804: 6878 ldr r0, [r7, #4]
8001806: f7ff ff29 bl 800165c <__NVIC_SetPriorityGrouping>
}
800180a: bf00 nop
800180c: 3708 adds r7, #8
800180e: 46bd mov sp, r7
8001810: bd80 pop {r7, pc}
08001812 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001812: b580 push {r7, lr}
8001814: b086 sub sp, #24
8001816: af00 add r7, sp, #0
8001818: 4603 mov r3, r0
800181a: 60b9 str r1, [r7, #8]
800181c: 607a str r2, [r7, #4]
800181e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8001820: 2300 movs r3, #0
8001822: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001824: f7ff ff3e bl 80016a4 <__NVIC_GetPriorityGrouping>
8001828: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800182a: 687a ldr r2, [r7, #4]
800182c: 68b9 ldr r1, [r7, #8]
800182e: 6978 ldr r0, [r7, #20]
8001830: f7ff ff8e bl 8001750 <NVIC_EncodePriority>
8001834: 4602 mov r2, r0
8001836: f997 300f ldrsb.w r3, [r7, #15]
800183a: 4611 mov r1, r2
800183c: 4618 mov r0, r3
800183e: f7ff ff5d bl 80016fc <__NVIC_SetPriority>
}
8001842: bf00 nop
8001844: 3718 adds r7, #24
8001846: 46bd mov sp, r7
8001848: bd80 pop {r7, pc}
0800184a <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800184a: b580 push {r7, lr}
800184c: b082 sub sp, #8
800184e: af00 add r7, sp, #0
8001850: 4603 mov r3, r0
8001852: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001854: f997 3007 ldrsb.w r3, [r7, #7]
8001858: 4618 mov r0, r3
800185a: f7ff ff31 bl 80016c0 <__NVIC_EnableIRQ>
}
800185e: bf00 nop
8001860: 3708 adds r7, #8
8001862: 46bd mov sp, r7
8001864: bd80 pop {r7, pc}
08001866 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8001866: b580 push {r7, lr}
8001868: b082 sub sp, #8
800186a: af00 add r7, sp, #0
800186c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
800186e: 6878 ldr r0, [r7, #4]
8001870: f7ff ffa2 bl 80017b8 <SysTick_Config>
8001874: 4603 mov r3, r0
}
8001876: 4618 mov r0, r3
8001878: 3708 adds r7, #8
800187a: 46bd mov sp, r7
800187c: bd80 pop {r7, pc}
...
08001880 <HAL_DFSDM_ChannelInit>:
* in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
8001880: b580 push {r7, lr}
8001882: b082 sub sp, #8
8001884: af00 add r7, sp, #0
8001886: 6078 str r0, [r7, #4]
/* Check DFSDM Channel handle */
if (hdfsdm_channel == NULL)
8001888: 687b ldr r3, [r7, #4]
800188a: 2b00 cmp r3, #0
800188c: d101 bne.n 8001892 <HAL_DFSDM_ChannelInit+0x12>
{
return HAL_ERROR;
800188e: 2301 movs r3, #1
8001890: e0ac b.n 80019ec <HAL_DFSDM_ChannelInit+0x16c>
assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
/* Check that channel has not been already initialized */
if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
8001892: 687b ldr r3, [r7, #4]
8001894: 681b ldr r3, [r3, #0]
8001896: 4618 mov r0, r3
8001898: f000 f8b2 bl 8001a00 <DFSDM_GetChannelFromInstance>
800189c: 4603 mov r3, r0
800189e: 4a55 ldr r2, [pc, #340] @ (80019f4 <HAL_DFSDM_ChannelInit+0x174>)
80018a0: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80018a4: 2b00 cmp r3, #0
80018a6: d001 beq.n 80018ac <HAL_DFSDM_ChannelInit+0x2c>
{
return HAL_ERROR;
80018a8: 2301 movs r3, #1
80018aa: e09f b.n 80019ec <HAL_DFSDM_ChannelInit+0x16c>
hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
}
hdfsdm_channel->MspInitCallback(hdfsdm_channel);
#else
/* Call MSP init function */
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
80018ac: 6878 ldr r0, [r7, #4]
80018ae: f7ff fb1f bl 8000ef0 <HAL_DFSDM_ChannelMspInit>
#endif
/* Update the channel counter */
v_dfsdm1ChannelCounter++;
80018b2: 4b51 ldr r3, [pc, #324] @ (80019f8 <HAL_DFSDM_ChannelInit+0x178>)
80018b4: 681b ldr r3, [r3, #0]
80018b6: 3301 adds r3, #1
80018b8: 4a4f ldr r2, [pc, #316] @ (80019f8 <HAL_DFSDM_ChannelInit+0x178>)
80018ba: 6013 str r3, [r2, #0]
/* Configure output serial clock and enable global DFSDM interface only for first channel */
if (v_dfsdm1ChannelCounter == 1U)
80018bc: 4b4e ldr r3, [pc, #312] @ (80019f8 <HAL_DFSDM_ChannelInit+0x178>)
80018be: 681b ldr r3, [r3, #0]
80018c0: 2b01 cmp r3, #1
80018c2: d125 bne.n 8001910 <HAL_DFSDM_ChannelInit+0x90>
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
/* Set the output serial clock source */
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
80018c4: 4b4d ldr r3, [pc, #308] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
80018c6: 681b ldr r3, [r3, #0]
80018c8: 4a4c ldr r2, [pc, #304] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
80018ca: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
80018ce: 6013 str r3, [r2, #0]
DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
80018d0: 4b4a ldr r3, [pc, #296] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
80018d2: 681a ldr r2, [r3, #0]
80018d4: 687b ldr r3, [r7, #4]
80018d6: 689b ldr r3, [r3, #8]
80018d8: 4948 ldr r1, [pc, #288] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
80018da: 4313 orrs r3, r2
80018dc: 600b str r3, [r1, #0]
/* Reset clock divider */
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
80018de: 4b47 ldr r3, [pc, #284] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
80018e0: 681b ldr r3, [r3, #0]
80018e2: 4a46 ldr r2, [pc, #280] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
80018e4: f423 037f bic.w r3, r3, #16711680 @ 0xff0000
80018e8: 6013 str r3, [r2, #0]
if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
80018ea: 687b ldr r3, [r7, #4]
80018ec: 791b ldrb r3, [r3, #4]
80018ee: 2b01 cmp r3, #1
80018f0: d108 bne.n 8001904 <HAL_DFSDM_ChannelInit+0x84>
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
/* Set the output clock divider */
DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
80018f2: 4b42 ldr r3, [pc, #264] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
80018f4: 681a ldr r2, [r3, #0]
80018f6: 687b ldr r3, [r7, #4]
80018f8: 68db ldr r3, [r3, #12]
80018fa: 3b01 subs r3, #1
80018fc: 041b lsls r3, r3, #16
80018fe: 493f ldr r1, [pc, #252] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
8001900: 4313 orrs r3, r2
8001902: 600b str r3, [r1, #0]
DFSDM_CHCFGR1_CKOUTDIV_Pos);
}
/* enable the DFSDM global interface */
DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
8001904: 4b3d ldr r3, [pc, #244] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
8001906: 681b ldr r3, [r3, #0]
8001908: 4a3c ldr r2, [pc, #240] @ (80019fc <HAL_DFSDM_ChannelInit+0x17c>)
800190a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
800190e: 6013 str r3, [r2, #0]
}
/* Set channel input parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
8001910: 687b ldr r3, [r7, #4]
8001912: 681b ldr r3, [r3, #0]
8001914: 681a ldr r2, [r3, #0]
8001916: 687b ldr r3, [r7, #4]
8001918: 681b ldr r3, [r3, #0]
800191a: f422 4271 bic.w r2, r2, #61696 @ 0xf100
800191e: 601a str r2, [r3, #0]
DFSDM_CHCFGR1_CHINSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
8001920: 687b ldr r3, [r7, #4]
8001922: 681b ldr r3, [r3, #0]
8001924: 6819 ldr r1, [r3, #0]
8001926: 687b ldr r3, [r7, #4]
8001928: 691a ldr r2, [r3, #16]
hdfsdm_channel->Init.Input.DataPacking |
800192a: 687b ldr r3, [r7, #4]
800192c: 695b ldr r3, [r3, #20]
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
800192e: 431a orrs r2, r3
hdfsdm_channel->Init.Input.Pins);
8001930: 687b ldr r3, [r7, #4]
8001932: 699b ldr r3, [r3, #24]
hdfsdm_channel->Init.Input.DataPacking |
8001934: 431a orrs r2, r3
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
8001936: 687b ldr r3, [r7, #4]
8001938: 681b ldr r3, [r3, #0]
800193a: 430a orrs r2, r1
800193c: 601a str r2, [r3, #0]
/* Set serial interface parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
800193e: 687b ldr r3, [r7, #4]
8001940: 681b ldr r3, [r3, #0]
8001942: 681a ldr r2, [r3, #0]
8001944: 687b ldr r3, [r7, #4]
8001946: 681b ldr r3, [r3, #0]
8001948: f022 020f bic.w r2, r2, #15
800194c: 601a str r2, [r3, #0]
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
800194e: 687b ldr r3, [r7, #4]
8001950: 681b ldr r3, [r3, #0]
8001952: 6819 ldr r1, [r3, #0]
8001954: 687b ldr r3, [r7, #4]
8001956: 69da ldr r2, [r3, #28]
hdfsdm_channel->Init.SerialInterface.SpiClock);
8001958: 687b ldr r3, [r7, #4]
800195a: 6a1b ldr r3, [r3, #32]
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
800195c: 431a orrs r2, r3
800195e: 687b ldr r3, [r7, #4]
8001960: 681b ldr r3, [r3, #0]
8001962: 430a orrs r2, r1
8001964: 601a str r2, [r3, #0]
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
8001966: 687b ldr r3, [r7, #4]
8001968: 681b ldr r3, [r3, #0]
800196a: 689a ldr r2, [r3, #8]
800196c: 687b ldr r3, [r7, #4]
800196e: 681b ldr r3, [r3, #0]
8001970: f422 025f bic.w r2, r2, #14614528 @ 0xdf0000
8001974: 609a str r2, [r3, #8]
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
8001976: 687b ldr r3, [r7, #4]
8001978: 681b ldr r3, [r3, #0]
800197a: 6899 ldr r1, [r3, #8]
800197c: 687b ldr r3, [r7, #4]
800197e: 6a5a ldr r2, [r3, #36] @ 0x24
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
8001980: 687b ldr r3, [r7, #4]
8001982: 6a9b ldr r3, [r3, #40] @ 0x28
8001984: 3b01 subs r3, #1
8001986: 041b lsls r3, r3, #16
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
8001988: 431a orrs r2, r3
800198a: 687b ldr r3, [r7, #4]
800198c: 681b ldr r3, [r3, #0]
800198e: 430a orrs r2, r1
8001990: 609a str r2, [r3, #8]
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
8001992: 687b ldr r3, [r7, #4]
8001994: 681b ldr r3, [r3, #0]
8001996: 685a ldr r2, [r3, #4]
8001998: 687b ldr r3, [r7, #4]
800199a: 681b ldr r3, [r3, #0]
800199c: f002 0207 and.w r2, r2, #7
80019a0: 605a str r2, [r3, #4]
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
80019a2: 687b ldr r3, [r7, #4]
80019a4: 681b ldr r3, [r3, #0]
80019a6: 6859 ldr r1, [r3, #4]
80019a8: 687b ldr r3, [r7, #4]
80019aa: 6adb ldr r3, [r3, #44] @ 0x2c
80019ac: 021a lsls r2, r3, #8
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
80019ae: 687b ldr r3, [r7, #4]
80019b0: 6b1b ldr r3, [r3, #48] @ 0x30
80019b2: 00db lsls r3, r3, #3
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
80019b4: 431a orrs r2, r3
80019b6: 687b ldr r3, [r7, #4]
80019b8: 681b ldr r3, [r3, #0]
80019ba: 430a orrs r2, r1
80019bc: 605a str r2, [r3, #4]
/* Enable DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
80019be: 687b ldr r3, [r7, #4]
80019c0: 681b ldr r3, [r3, #0]
80019c2: 681a ldr r2, [r3, #0]
80019c4: 687b ldr r3, [r7, #4]
80019c6: 681b ldr r3, [r3, #0]
80019c8: f042 0280 orr.w r2, r2, #128 @ 0x80
80019cc: 601a str r2, [r3, #0]
/* Set DFSDM Channel to ready state */
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
80019ce: 687b ldr r3, [r7, #4]
80019d0: 2201 movs r2, #1
80019d2: f883 2034 strb.w r2, [r3, #52] @ 0x34
/* Store channel handle in DFSDM channel handle table */
a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
80019d6: 687b ldr r3, [r7, #4]
80019d8: 681b ldr r3, [r3, #0]
80019da: 4618 mov r0, r3
80019dc: f000 f810 bl 8001a00 <DFSDM_GetChannelFromInstance>
80019e0: 4602 mov r2, r0
80019e2: 4904 ldr r1, [pc, #16] @ (80019f4 <HAL_DFSDM_ChannelInit+0x174>)
80019e4: 687b ldr r3, [r7, #4]
80019e6: f841 3022 str.w r3, [r1, r2, lsl #2]
return HAL_OK;
80019ea: 2300 movs r3, #0
}
80019ec: 4618 mov r0, r3
80019ee: 3708 adds r7, #8
80019f0: 46bd mov sp, r7
80019f2: bd80 pop {r7, pc}
80019f4: 20000764 .word 0x20000764
80019f8: 20000760 .word 0x20000760
80019fc: 40016000 .word 0x40016000
08001a00 <DFSDM_GetChannelFromInstance>:
* @brief This function allows to get the channel number from channel instance.
* @param Instance DFSDM channel instance.
* @retval Channel number.
*/
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
{
8001a00: b480 push {r7}
8001a02: b085 sub sp, #20
8001a04: af00 add r7, sp, #0
8001a06: 6078 str r0, [r7, #4]
uint32_t channel;
/* Get channel from instance */
if (Instance == DFSDM1_Channel0)
8001a08: 687b ldr r3, [r7, #4]
8001a0a: 4a1c ldr r2, [pc, #112] @ (8001a7c <DFSDM_GetChannelFromInstance+0x7c>)
8001a0c: 4293 cmp r3, r2
8001a0e: d102 bne.n 8001a16 <DFSDM_GetChannelFromInstance+0x16>
{
channel = 0;
8001a10: 2300 movs r3, #0
8001a12: 60fb str r3, [r7, #12]
8001a14: e02b b.n 8001a6e <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel1)
8001a16: 687b ldr r3, [r7, #4]
8001a18: 4a19 ldr r2, [pc, #100] @ (8001a80 <DFSDM_GetChannelFromInstance+0x80>)
8001a1a: 4293 cmp r3, r2
8001a1c: d102 bne.n 8001a24 <DFSDM_GetChannelFromInstance+0x24>
{
channel = 1;
8001a1e: 2301 movs r3, #1
8001a20: 60fb str r3, [r7, #12]
8001a22: e024 b.n 8001a6e <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel2)
8001a24: 687b ldr r3, [r7, #4]
8001a26: 4a17 ldr r2, [pc, #92] @ (8001a84 <DFSDM_GetChannelFromInstance+0x84>)
8001a28: 4293 cmp r3, r2
8001a2a: d102 bne.n 8001a32 <DFSDM_GetChannelFromInstance+0x32>
{
channel = 2;
8001a2c: 2302 movs r3, #2
8001a2e: 60fb str r3, [r7, #12]
8001a30: e01d b.n 8001a6e <DFSDM_GetChannelFromInstance+0x6e>
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
else if (Instance == DFSDM1_Channel4)
8001a32: 687b ldr r3, [r7, #4]
8001a34: 4a14 ldr r2, [pc, #80] @ (8001a88 <DFSDM_GetChannelFromInstance+0x88>)
8001a36: 4293 cmp r3, r2
8001a38: d102 bne.n 8001a40 <DFSDM_GetChannelFromInstance+0x40>
{
channel = 4;
8001a3a: 2304 movs r3, #4
8001a3c: 60fb str r3, [r7, #12]
8001a3e: e016 b.n 8001a6e <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel5)
8001a40: 687b ldr r3, [r7, #4]
8001a42: 4a12 ldr r2, [pc, #72] @ (8001a8c <DFSDM_GetChannelFromInstance+0x8c>)
8001a44: 4293 cmp r3, r2
8001a46: d102 bne.n 8001a4e <DFSDM_GetChannelFromInstance+0x4e>
{
channel = 5;
8001a48: 2305 movs r3, #5
8001a4a: 60fb str r3, [r7, #12]
8001a4c: e00f b.n 8001a6e <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel6)
8001a4e: 687b ldr r3, [r7, #4]
8001a50: 4a0f ldr r2, [pc, #60] @ (8001a90 <DFSDM_GetChannelFromInstance+0x90>)
8001a52: 4293 cmp r3, r2
8001a54: d102 bne.n 8001a5c <DFSDM_GetChannelFromInstance+0x5c>
{
channel = 6;
8001a56: 2306 movs r3, #6
8001a58: 60fb str r3, [r7, #12]
8001a5a: e008 b.n 8001a6e <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel7)
8001a5c: 687b ldr r3, [r7, #4]
8001a5e: 4a0d ldr r2, [pc, #52] @ (8001a94 <DFSDM_GetChannelFromInstance+0x94>)
8001a60: 4293 cmp r3, r2
8001a62: d102 bne.n 8001a6a <DFSDM_GetChannelFromInstance+0x6a>
{
channel = 7;
8001a64: 2307 movs r3, #7
8001a66: 60fb str r3, [r7, #12]
8001a68: e001 b.n 8001a6e <DFSDM_GetChannelFromInstance+0x6e>
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
else /* DFSDM1_Channel3 */
{
channel = 3;
8001a6a: 2303 movs r3, #3
8001a6c: 60fb str r3, [r7, #12]
}
return channel;
8001a6e: 68fb ldr r3, [r7, #12]
}
8001a70: 4618 mov r0, r3
8001a72: 3714 adds r7, #20
8001a74: 46bd mov sp, r7
8001a76: f85d 7b04 ldr.w r7, [sp], #4
8001a7a: 4770 bx lr
8001a7c: 40016000 .word 0x40016000
8001a80: 40016020 .word 0x40016020
8001a84: 40016040 .word 0x40016040
8001a88: 40016080 .word 0x40016080
8001a8c: 400160a0 .word 0x400160a0
8001a90: 400160c0 .word 0x400160c0
8001a94: 400160e0 .word 0x400160e0
08001a98 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001a98: b480 push {r7}
8001a9a: b087 sub sp, #28
8001a9c: af00 add r7, sp, #0
8001a9e: 6078 str r0, [r7, #4]
8001aa0: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8001aa2: 2300 movs r3, #0
8001aa4: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001aa6: e17f b.n 8001da8 <HAL_GPIO_Init+0x310>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8001aa8: 683b ldr r3, [r7, #0]
8001aaa: 681a ldr r2, [r3, #0]
8001aac: 2101 movs r1, #1
8001aae: 697b ldr r3, [r7, #20]
8001ab0: fa01 f303 lsl.w r3, r1, r3
8001ab4: 4013 ands r3, r2
8001ab6: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001ab8: 68fb ldr r3, [r7, #12]
8001aba: 2b00 cmp r3, #0
8001abc: f000 8171 beq.w 8001da2 <HAL_GPIO_Init+0x30a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001ac0: 683b ldr r3, [r7, #0]
8001ac2: 685b ldr r3, [r3, #4]
8001ac4: f003 0303 and.w r3, r3, #3
8001ac8: 2b01 cmp r3, #1
8001aca: d005 beq.n 8001ad8 <HAL_GPIO_Init+0x40>
8001acc: 683b ldr r3, [r7, #0]
8001ace: 685b ldr r3, [r3, #4]
8001ad0: f003 0303 and.w r3, r3, #3
8001ad4: 2b02 cmp r3, #2
8001ad6: d130 bne.n 8001b3a <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001ad8: 687b ldr r3, [r7, #4]
8001ada: 689b ldr r3, [r3, #8]
8001adc: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
8001ade: 697b ldr r3, [r7, #20]
8001ae0: 005b lsls r3, r3, #1
8001ae2: 2203 movs r2, #3
8001ae4: fa02 f303 lsl.w r3, r2, r3
8001ae8: 43db mvns r3, r3
8001aea: 693a ldr r2, [r7, #16]
8001aec: 4013 ands r3, r2
8001aee: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001af0: 683b ldr r3, [r7, #0]
8001af2: 68da ldr r2, [r3, #12]
8001af4: 697b ldr r3, [r7, #20]
8001af6: 005b lsls r3, r3, #1
8001af8: fa02 f303 lsl.w r3, r2, r3
8001afc: 693a ldr r2, [r7, #16]
8001afe: 4313 orrs r3, r2
8001b00: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8001b02: 687b ldr r3, [r7, #4]
8001b04: 693a ldr r2, [r7, #16]
8001b06: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001b08: 687b ldr r3, [r7, #4]
8001b0a: 685b ldr r3, [r3, #4]
8001b0c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8001b0e: 2201 movs r2, #1
8001b10: 697b ldr r3, [r7, #20]
8001b12: fa02 f303 lsl.w r3, r2, r3
8001b16: 43db mvns r3, r3
8001b18: 693a ldr r2, [r7, #16]
8001b1a: 4013 ands r3, r2
8001b1c: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001b1e: 683b ldr r3, [r7, #0]
8001b20: 685b ldr r3, [r3, #4]
8001b22: 091b lsrs r3, r3, #4
8001b24: f003 0201 and.w r2, r3, #1
8001b28: 697b ldr r3, [r7, #20]
8001b2a: fa02 f303 lsl.w r3, r2, r3
8001b2e: 693a ldr r2, [r7, #16]
8001b30: 4313 orrs r3, r2
8001b32: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001b34: 687b ldr r3, [r7, #4]
8001b36: 693a ldr r2, [r7, #16]
8001b38: 605a str r2, [r3, #4]
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* In case of Analog mode, check if ADC control mode is selected */
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
8001b3a: 683b ldr r3, [r7, #0]
8001b3c: 685b ldr r3, [r3, #4]
8001b3e: f003 0303 and.w r3, r3, #3
8001b42: 2b03 cmp r3, #3
8001b44: d118 bne.n 8001b78 <HAL_GPIO_Init+0xe0>
{
/* Configure the IO Output Type */
temp = GPIOx->ASCR;
8001b46: 687b ldr r3, [r7, #4]
8001b48: 6adb ldr r3, [r3, #44] @ 0x2c
8001b4a: 613b str r3, [r7, #16]
temp &= ~(GPIO_ASCR_ASC0 << position) ;
8001b4c: 2201 movs r2, #1
8001b4e: 697b ldr r3, [r7, #20]
8001b50: fa02 f303 lsl.w r3, r2, r3
8001b54: 43db mvns r3, r3
8001b56: 693a ldr r2, [r7, #16]
8001b58: 4013 ands r3, r2
8001b5a: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
8001b5c: 683b ldr r3, [r7, #0]
8001b5e: 685b ldr r3, [r3, #4]
8001b60: 08db lsrs r3, r3, #3
8001b62: f003 0201 and.w r2, r3, #1
8001b66: 697b ldr r3, [r7, #20]
8001b68: fa02 f303 lsl.w r3, r2, r3
8001b6c: 693a ldr r2, [r7, #16]
8001b6e: 4313 orrs r3, r2
8001b70: 613b str r3, [r7, #16]
GPIOx->ASCR = temp;
8001b72: 687b ldr r3, [r7, #4]
8001b74: 693a ldr r2, [r7, #16]
8001b76: 62da str r2, [r3, #44] @ 0x2c
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001b78: 683b ldr r3, [r7, #0]
8001b7a: 685b ldr r3, [r3, #4]
8001b7c: f003 0303 and.w r3, r3, #3
8001b80: 2b03 cmp r3, #3
8001b82: d017 beq.n 8001bb4 <HAL_GPIO_Init+0x11c>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
temp = GPIOx->PUPDR;
8001b84: 687b ldr r3, [r7, #4]
8001b86: 68db ldr r3, [r3, #12]
8001b88: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8001b8a: 697b ldr r3, [r7, #20]
8001b8c: 005b lsls r3, r3, #1
8001b8e: 2203 movs r2, #3
8001b90: fa02 f303 lsl.w r3, r2, r3
8001b94: 43db mvns r3, r3
8001b96: 693a ldr r2, [r7, #16]
8001b98: 4013 ands r3, r2
8001b9a: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8001b9c: 683b ldr r3, [r7, #0]
8001b9e: 689a ldr r2, [r3, #8]
8001ba0: 697b ldr r3, [r7, #20]
8001ba2: 005b lsls r3, r3, #1
8001ba4: fa02 f303 lsl.w r3, r2, r3
8001ba8: 693a ldr r2, [r7, #16]
8001baa: 4313 orrs r3, r2
8001bac: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8001bae: 687b ldr r3, [r7, #4]
8001bb0: 693a ldr r2, [r7, #16]
8001bb2: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001bb4: 683b ldr r3, [r7, #0]
8001bb6: 685b ldr r3, [r3, #4]
8001bb8: f003 0303 and.w r3, r3, #3
8001bbc: 2b02 cmp r3, #2
8001bbe: d123 bne.n 8001c08 <HAL_GPIO_Init+0x170>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8001bc0: 697b ldr r3, [r7, #20]
8001bc2: 08da lsrs r2, r3, #3
8001bc4: 687b ldr r3, [r7, #4]
8001bc6: 3208 adds r2, #8
8001bc8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001bcc: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8001bce: 697b ldr r3, [r7, #20]
8001bd0: f003 0307 and.w r3, r3, #7
8001bd4: 009b lsls r3, r3, #2
8001bd6: 220f movs r2, #15
8001bd8: fa02 f303 lsl.w r3, r2, r3
8001bdc: 43db mvns r3, r3
8001bde: 693a ldr r2, [r7, #16]
8001be0: 4013 ands r3, r2
8001be2: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8001be4: 683b ldr r3, [r7, #0]
8001be6: 691a ldr r2, [r3, #16]
8001be8: 697b ldr r3, [r7, #20]
8001bea: f003 0307 and.w r3, r3, #7
8001bee: 009b lsls r3, r3, #2
8001bf0: fa02 f303 lsl.w r3, r2, r3
8001bf4: 693a ldr r2, [r7, #16]
8001bf6: 4313 orrs r3, r2
8001bf8: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001bfa: 697b ldr r3, [r7, #20]
8001bfc: 08da lsrs r2, r3, #3
8001bfe: 687b ldr r3, [r7, #4]
8001c00: 3208 adds r2, #8
8001c02: 6939 ldr r1, [r7, #16]
8001c04: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001c08: 687b ldr r3, [r7, #4]
8001c0a: 681b ldr r3, [r3, #0]
8001c0c: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8001c0e: 697b ldr r3, [r7, #20]
8001c10: 005b lsls r3, r3, #1
8001c12: 2203 movs r2, #3
8001c14: fa02 f303 lsl.w r3, r2, r3
8001c18: 43db mvns r3, r3
8001c1a: 693a ldr r2, [r7, #16]
8001c1c: 4013 ands r3, r2
8001c1e: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001c20: 683b ldr r3, [r7, #0]
8001c22: 685b ldr r3, [r3, #4]
8001c24: f003 0203 and.w r2, r3, #3
8001c28: 697b ldr r3, [r7, #20]
8001c2a: 005b lsls r3, r3, #1
8001c2c: fa02 f303 lsl.w r3, r2, r3
8001c30: 693a ldr r2, [r7, #16]
8001c32: 4313 orrs r3, r2
8001c34: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001c36: 687b ldr r3, [r7, #4]
8001c38: 693a ldr r2, [r7, #16]
8001c3a: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001c3c: 683b ldr r3, [r7, #0]
8001c3e: 685b ldr r3, [r3, #4]
8001c40: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001c44: 2b00 cmp r3, #0
8001c46: f000 80ac beq.w 8001da2 <HAL_GPIO_Init+0x30a>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001c4a: 4b5f ldr r3, [pc, #380] @ (8001dc8 <HAL_GPIO_Init+0x330>)
8001c4c: 6e1b ldr r3, [r3, #96] @ 0x60
8001c4e: 4a5e ldr r2, [pc, #376] @ (8001dc8 <HAL_GPIO_Init+0x330>)
8001c50: f043 0301 orr.w r3, r3, #1
8001c54: 6613 str r3, [r2, #96] @ 0x60
8001c56: 4b5c ldr r3, [pc, #368] @ (8001dc8 <HAL_GPIO_Init+0x330>)
8001c58: 6e1b ldr r3, [r3, #96] @ 0x60
8001c5a: f003 0301 and.w r3, r3, #1
8001c5e: 60bb str r3, [r7, #8]
8001c60: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8001c62: 4a5a ldr r2, [pc, #360] @ (8001dcc <HAL_GPIO_Init+0x334>)
8001c64: 697b ldr r3, [r7, #20]
8001c66: 089b lsrs r3, r3, #2
8001c68: 3302 adds r3, #2
8001c6a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001c6e: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8001c70: 697b ldr r3, [r7, #20]
8001c72: f003 0303 and.w r3, r3, #3
8001c76: 009b lsls r3, r3, #2
8001c78: 220f movs r2, #15
8001c7a: fa02 f303 lsl.w r3, r2, r3
8001c7e: 43db mvns r3, r3
8001c80: 693a ldr r2, [r7, #16]
8001c82: 4013 ands r3, r2
8001c84: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8001c86: 687b ldr r3, [r7, #4]
8001c88: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8001c8c: d025 beq.n 8001cda <HAL_GPIO_Init+0x242>
8001c8e: 687b ldr r3, [r7, #4]
8001c90: 4a4f ldr r2, [pc, #316] @ (8001dd0 <HAL_GPIO_Init+0x338>)
8001c92: 4293 cmp r3, r2
8001c94: d01f beq.n 8001cd6 <HAL_GPIO_Init+0x23e>
8001c96: 687b ldr r3, [r7, #4]
8001c98: 4a4e ldr r2, [pc, #312] @ (8001dd4 <HAL_GPIO_Init+0x33c>)
8001c9a: 4293 cmp r3, r2
8001c9c: d019 beq.n 8001cd2 <HAL_GPIO_Init+0x23a>
8001c9e: 687b ldr r3, [r7, #4]
8001ca0: 4a4d ldr r2, [pc, #308] @ (8001dd8 <HAL_GPIO_Init+0x340>)
8001ca2: 4293 cmp r3, r2
8001ca4: d013 beq.n 8001cce <HAL_GPIO_Init+0x236>
8001ca6: 687b ldr r3, [r7, #4]
8001ca8: 4a4c ldr r2, [pc, #304] @ (8001ddc <HAL_GPIO_Init+0x344>)
8001caa: 4293 cmp r3, r2
8001cac: d00d beq.n 8001cca <HAL_GPIO_Init+0x232>
8001cae: 687b ldr r3, [r7, #4]
8001cb0: 4a4b ldr r2, [pc, #300] @ (8001de0 <HAL_GPIO_Init+0x348>)
8001cb2: 4293 cmp r3, r2
8001cb4: d007 beq.n 8001cc6 <HAL_GPIO_Init+0x22e>
8001cb6: 687b ldr r3, [r7, #4]
8001cb8: 4a4a ldr r2, [pc, #296] @ (8001de4 <HAL_GPIO_Init+0x34c>)
8001cba: 4293 cmp r3, r2
8001cbc: d101 bne.n 8001cc2 <HAL_GPIO_Init+0x22a>
8001cbe: 2306 movs r3, #6
8001cc0: e00c b.n 8001cdc <HAL_GPIO_Init+0x244>
8001cc2: 2307 movs r3, #7
8001cc4: e00a b.n 8001cdc <HAL_GPIO_Init+0x244>
8001cc6: 2305 movs r3, #5
8001cc8: e008 b.n 8001cdc <HAL_GPIO_Init+0x244>
8001cca: 2304 movs r3, #4
8001ccc: e006 b.n 8001cdc <HAL_GPIO_Init+0x244>
8001cce: 2303 movs r3, #3
8001cd0: e004 b.n 8001cdc <HAL_GPIO_Init+0x244>
8001cd2: 2302 movs r3, #2
8001cd4: e002 b.n 8001cdc <HAL_GPIO_Init+0x244>
8001cd6: 2301 movs r3, #1
8001cd8: e000 b.n 8001cdc <HAL_GPIO_Init+0x244>
8001cda: 2300 movs r3, #0
8001cdc: 697a ldr r2, [r7, #20]
8001cde: f002 0203 and.w r2, r2, #3
8001ce2: 0092 lsls r2, r2, #2
8001ce4: 4093 lsls r3, r2
8001ce6: 693a ldr r2, [r7, #16]
8001ce8: 4313 orrs r3, r2
8001cea: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8001cec: 4937 ldr r1, [pc, #220] @ (8001dcc <HAL_GPIO_Init+0x334>)
8001cee: 697b ldr r3, [r7, #20]
8001cf0: 089b lsrs r3, r3, #2
8001cf2: 3302 adds r3, #2
8001cf4: 693a ldr r2, [r7, #16]
8001cf6: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8001cfa: 4b3b ldr r3, [pc, #236] @ (8001de8 <HAL_GPIO_Init+0x350>)
8001cfc: 689b ldr r3, [r3, #8]
8001cfe: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001d00: 68fb ldr r3, [r7, #12]
8001d02: 43db mvns r3, r3
8001d04: 693a ldr r2, [r7, #16]
8001d06: 4013 ands r3, r2
8001d08: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001d0a: 683b ldr r3, [r7, #0]
8001d0c: 685b ldr r3, [r3, #4]
8001d0e: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001d12: 2b00 cmp r3, #0
8001d14: d003 beq.n 8001d1e <HAL_GPIO_Init+0x286>
{
temp |= iocurrent;
8001d16: 693a ldr r2, [r7, #16]
8001d18: 68fb ldr r3, [r7, #12]
8001d1a: 4313 orrs r3, r2
8001d1c: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8001d1e: 4a32 ldr r2, [pc, #200] @ (8001de8 <HAL_GPIO_Init+0x350>)
8001d20: 693b ldr r3, [r7, #16]
8001d22: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8001d24: 4b30 ldr r3, [pc, #192] @ (8001de8 <HAL_GPIO_Init+0x350>)
8001d26: 68db ldr r3, [r3, #12]
8001d28: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001d2a: 68fb ldr r3, [r7, #12]
8001d2c: 43db mvns r3, r3
8001d2e: 693a ldr r2, [r7, #16]
8001d30: 4013 ands r3, r2
8001d32: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8001d34: 683b ldr r3, [r7, #0]
8001d36: 685b ldr r3, [r3, #4]
8001d38: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001d3c: 2b00 cmp r3, #0
8001d3e: d003 beq.n 8001d48 <HAL_GPIO_Init+0x2b0>
{
temp |= iocurrent;
8001d40: 693a ldr r2, [r7, #16]
8001d42: 68fb ldr r3, [r7, #12]
8001d44: 4313 orrs r3, r2
8001d46: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8001d48: 4a27 ldr r2, [pc, #156] @ (8001de8 <HAL_GPIO_Init+0x350>)
8001d4a: 693b ldr r3, [r7, #16]
8001d4c: 60d3 str r3, [r2, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8001d4e: 4b26 ldr r3, [pc, #152] @ (8001de8 <HAL_GPIO_Init+0x350>)
8001d50: 685b ldr r3, [r3, #4]
8001d52: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001d54: 68fb ldr r3, [r7, #12]
8001d56: 43db mvns r3, r3
8001d58: 693a ldr r2, [r7, #16]
8001d5a: 4013 ands r3, r2
8001d5c: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001d5e: 683b ldr r3, [r7, #0]
8001d60: 685b ldr r3, [r3, #4]
8001d62: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001d66: 2b00 cmp r3, #0
8001d68: d003 beq.n 8001d72 <HAL_GPIO_Init+0x2da>
{
temp |= iocurrent;
8001d6a: 693a ldr r2, [r7, #16]
8001d6c: 68fb ldr r3, [r7, #12]
8001d6e: 4313 orrs r3, r2
8001d70: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8001d72: 4a1d ldr r2, [pc, #116] @ (8001de8 <HAL_GPIO_Init+0x350>)
8001d74: 693b ldr r3, [r7, #16]
8001d76: 6053 str r3, [r2, #4]
temp = EXTI->IMR1;
8001d78: 4b1b ldr r3, [pc, #108] @ (8001de8 <HAL_GPIO_Init+0x350>)
8001d7a: 681b ldr r3, [r3, #0]
8001d7c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001d7e: 68fb ldr r3, [r7, #12]
8001d80: 43db mvns r3, r3
8001d82: 693a ldr r2, [r7, #16]
8001d84: 4013 ands r3, r2
8001d86: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001d88: 683b ldr r3, [r7, #0]
8001d8a: 685b ldr r3, [r3, #4]
8001d8c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001d90: 2b00 cmp r3, #0
8001d92: d003 beq.n 8001d9c <HAL_GPIO_Init+0x304>
{
temp |= iocurrent;
8001d94: 693a ldr r2, [r7, #16]
8001d96: 68fb ldr r3, [r7, #12]
8001d98: 4313 orrs r3, r2
8001d9a: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8001d9c: 4a12 ldr r2, [pc, #72] @ (8001de8 <HAL_GPIO_Init+0x350>)
8001d9e: 693b ldr r3, [r7, #16]
8001da0: 6013 str r3, [r2, #0]
}
}
position++;
8001da2: 697b ldr r3, [r7, #20]
8001da4: 3301 adds r3, #1
8001da6: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001da8: 683b ldr r3, [r7, #0]
8001daa: 681a ldr r2, [r3, #0]
8001dac: 697b ldr r3, [r7, #20]
8001dae: fa22 f303 lsr.w r3, r2, r3
8001db2: 2b00 cmp r3, #0
8001db4: f47f ae78 bne.w 8001aa8 <HAL_GPIO_Init+0x10>
}
}
8001db8: bf00 nop
8001dba: bf00 nop
8001dbc: 371c adds r7, #28
8001dbe: 46bd mov sp, r7
8001dc0: f85d 7b04 ldr.w r7, [sp], #4
8001dc4: 4770 bx lr
8001dc6: bf00 nop
8001dc8: 40021000 .word 0x40021000
8001dcc: 40010000 .word 0x40010000
8001dd0: 48000400 .word 0x48000400
8001dd4: 48000800 .word 0x48000800
8001dd8: 48000c00 .word 0x48000c00
8001ddc: 48001000 .word 0x48001000
8001de0: 48001400 .word 0x48001400
8001de4: 48001800 .word 0x48001800
8001de8: 40010400 .word 0x40010400
08001dec <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001dec: b480 push {r7}
8001dee: b085 sub sp, #20
8001df0: af00 add r7, sp, #0
8001df2: 6078 str r0, [r7, #4]
8001df4: 460b mov r3, r1
8001df6: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
8001df8: 687b ldr r3, [r7, #4]
8001dfa: 691a ldr r2, [r3, #16]
8001dfc: 887b ldrh r3, [r7, #2]
8001dfe: 4013 ands r3, r2
8001e00: 2b00 cmp r3, #0
8001e02: d002 beq.n 8001e0a <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8001e04: 2301 movs r3, #1
8001e06: 73fb strb r3, [r7, #15]
8001e08: e001 b.n 8001e0e <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8001e0a: 2300 movs r3, #0
8001e0c: 73fb strb r3, [r7, #15]
}
return bitstatus;
8001e0e: 7bfb ldrb r3, [r7, #15]
}
8001e10: 4618 mov r0, r3
8001e12: 3714 adds r7, #20
8001e14: 46bd mov sp, r7
8001e16: f85d 7b04 ldr.w r7, [sp], #4
8001e1a: 4770 bx lr
08001e1c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001e1c: b480 push {r7}
8001e1e: b083 sub sp, #12
8001e20: af00 add r7, sp, #0
8001e22: 6078 str r0, [r7, #4]
8001e24: 460b mov r3, r1
8001e26: 807b strh r3, [r7, #2]
8001e28: 4613 mov r3, r2
8001e2a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001e2c: 787b ldrb r3, [r7, #1]
8001e2e: 2b00 cmp r3, #0
8001e30: d003 beq.n 8001e3a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001e32: 887a ldrh r2, [r7, #2]
8001e34: 687b ldr r3, [r7, #4]
8001e36: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8001e38: e002 b.n 8001e40 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8001e3a: 887a ldrh r2, [r7, #2]
8001e3c: 687b ldr r3, [r7, #4]
8001e3e: 629a str r2, [r3, #40] @ 0x28
}
8001e40: bf00 nop
8001e42: 370c adds r7, #12
8001e44: 46bd mov sp, r7
8001e46: f85d 7b04 ldr.w r7, [sp], #4
8001e4a: 4770 bx lr
08001e4c <HAL_GPIO_EXTI_IRQHandler>:
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
8001e4c: b580 push {r7, lr}
8001e4e: b082 sub sp, #8
8001e50: af00 add r7, sp, #0
8001e52: 4603 mov r3, r0
8001e54: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
8001e56: 4b08 ldr r3, [pc, #32] @ (8001e78 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8001e58: 695a ldr r2, [r3, #20]
8001e5a: 88fb ldrh r3, [r7, #6]
8001e5c: 4013 ands r3, r2
8001e5e: 2b00 cmp r3, #0
8001e60: d006 beq.n 8001e70 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8001e62: 4a05 ldr r2, [pc, #20] @ (8001e78 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8001e64: 88fb ldrh r3, [r7, #6]
8001e66: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
8001e68: 88fb ldrh r3, [r7, #6]
8001e6a: 4618 mov r0, r3
8001e6c: f000 f806 bl 8001e7c <HAL_GPIO_EXTI_Callback>
}
}
8001e70: bf00 nop
8001e72: 3708 adds r7, #8
8001e74: 46bd mov sp, r7
8001e76: bd80 pop {r7, pc}
8001e78: 40010400 .word 0x40010400
08001e7c <HAL_GPIO_EXTI_Callback>:
* @brief EXTI line detection callback.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8001e7c: b480 push {r7}
8001e7e: b083 sub sp, #12
8001e80: af00 add r7, sp, #0
8001e82: 4603 mov r3, r0
8001e84: 80fb strh r3, [r7, #6]
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
8001e86: bf00 nop
8001e88: 370c adds r7, #12
8001e8a: 46bd mov sp, r7
8001e8c: f85d 7b04 ldr.w r7, [sp], #4
8001e90: 4770 bx lr
08001e92 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8001e92: b580 push {r7, lr}
8001e94: b082 sub sp, #8
8001e96: af00 add r7, sp, #0
8001e98: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8001e9a: 687b ldr r3, [r7, #4]
8001e9c: 2b00 cmp r3, #0
8001e9e: d101 bne.n 8001ea4 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8001ea0: 2301 movs r3, #1
8001ea2: e08d b.n 8001fc0 <HAL_I2C_Init+0x12e>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8001ea4: 687b ldr r3, [r7, #4]
8001ea6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8001eaa: b2db uxtb r3, r3
8001eac: 2b00 cmp r3, #0
8001eae: d106 bne.n 8001ebe <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8001eb0: 687b ldr r3, [r7, #4]
8001eb2: 2200 movs r2, #0
8001eb4: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
8001eb8: 6878 ldr r0, [r7, #4]
8001eba: f7ff f87d bl 8000fb8 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8001ebe: 687b ldr r3, [r7, #4]
8001ec0: 2224 movs r2, #36 @ 0x24
8001ec2: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001ec6: 687b ldr r3, [r7, #4]
8001ec8: 681b ldr r3, [r3, #0]
8001eca: 681a ldr r2, [r3, #0]
8001ecc: 687b ldr r3, [r7, #4]
8001ece: 681b ldr r3, [r3, #0]
8001ed0: f022 0201 bic.w r2, r2, #1
8001ed4: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8001ed6: 687b ldr r3, [r7, #4]
8001ed8: 685a ldr r2, [r3, #4]
8001eda: 687b ldr r3, [r7, #4]
8001edc: 681b ldr r3, [r3, #0]
8001ede: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
8001ee2: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8001ee4: 687b ldr r3, [r7, #4]
8001ee6: 681b ldr r3, [r3, #0]
8001ee8: 689a ldr r2, [r3, #8]
8001eea: 687b ldr r3, [r7, #4]
8001eec: 681b ldr r3, [r3, #0]
8001eee: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8001ef2: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8001ef4: 687b ldr r3, [r7, #4]
8001ef6: 68db ldr r3, [r3, #12]
8001ef8: 2b01 cmp r3, #1
8001efa: d107 bne.n 8001f0c <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
8001efc: 687b ldr r3, [r7, #4]
8001efe: 689a ldr r2, [r3, #8]
8001f00: 687b ldr r3, [r7, #4]
8001f02: 681b ldr r3, [r3, #0]
8001f04: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8001f08: 609a str r2, [r3, #8]
8001f0a: e006 b.n 8001f1a <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
8001f0c: 687b ldr r3, [r7, #4]
8001f0e: 689a ldr r2, [r3, #8]
8001f10: 687b ldr r3, [r7, #4]
8001f12: 681b ldr r3, [r3, #0]
8001f14: f442 4204 orr.w r2, r2, #33792 @ 0x8400
8001f18: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 68db ldr r3, [r3, #12]
8001f1e: 2b02 cmp r3, #2
8001f20: d108 bne.n 8001f34 <HAL_I2C_Init+0xa2>
{
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8001f22: 687b ldr r3, [r7, #4]
8001f24: 681b ldr r3, [r3, #0]
8001f26: 685a ldr r2, [r3, #4]
8001f28: 687b ldr r3, [r7, #4]
8001f2a: 681b ldr r3, [r3, #0]
8001f2c: f442 6200 orr.w r2, r2, #2048 @ 0x800
8001f30: 605a str r2, [r3, #4]
8001f32: e007 b.n 8001f44 <HAL_I2C_Init+0xb2>
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8001f34: 687b ldr r3, [r7, #4]
8001f36: 681b ldr r3, [r3, #0]
8001f38: 685a ldr r2, [r3, #4]
8001f3a: 687b ldr r3, [r7, #4]
8001f3c: 681b ldr r3, [r3, #0]
8001f3e: f422 6200 bic.w r2, r2, #2048 @ 0x800
8001f42: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8001f44: 687b ldr r3, [r7, #4]
8001f46: 681b ldr r3, [r3, #0]
8001f48: 685b ldr r3, [r3, #4]
8001f4a: 687a ldr r2, [r7, #4]
8001f4c: 6812 ldr r2, [r2, #0]
8001f4e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8001f52: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8001f56: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8001f58: 687b ldr r3, [r7, #4]
8001f5a: 681b ldr r3, [r3, #0]
8001f5c: 68da ldr r2, [r3, #12]
8001f5e: 687b ldr r3, [r7, #4]
8001f60: 681b ldr r3, [r3, #0]
8001f62: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8001f66: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8001f68: 687b ldr r3, [r7, #4]
8001f6a: 691a ldr r2, [r3, #16]
8001f6c: 687b ldr r3, [r7, #4]
8001f6e: 695b ldr r3, [r3, #20]
8001f70: ea42 0103 orr.w r1, r2, r3
(hi2c->Init.OwnAddress2Masks << 8));
8001f74: 687b ldr r3, [r7, #4]
8001f76: 699b ldr r3, [r3, #24]
8001f78: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8001f7a: 687b ldr r3, [r7, #4]
8001f7c: 681b ldr r3, [r3, #0]
8001f7e: 430a orrs r2, r1
8001f80: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8001f82: 687b ldr r3, [r7, #4]
8001f84: 69d9 ldr r1, [r3, #28]
8001f86: 687b ldr r3, [r7, #4]
8001f88: 6a1a ldr r2, [r3, #32]
8001f8a: 687b ldr r3, [r7, #4]
8001f8c: 681b ldr r3, [r3, #0]
8001f8e: 430a orrs r2, r1
8001f90: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8001f92: 687b ldr r3, [r7, #4]
8001f94: 681b ldr r3, [r3, #0]
8001f96: 681a ldr r2, [r3, #0]
8001f98: 687b ldr r3, [r7, #4]
8001f9a: 681b ldr r3, [r3, #0]
8001f9c: f042 0201 orr.w r2, r2, #1
8001fa0: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001fa2: 687b ldr r3, [r7, #4]
8001fa4: 2200 movs r2, #0
8001fa6: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
8001fa8: 687b ldr r3, [r7, #4]
8001faa: 2220 movs r2, #32
8001fac: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8001fb0: 687b ldr r3, [r7, #4]
8001fb2: 2200 movs r2, #0
8001fb4: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8001fb6: 687b ldr r3, [r7, #4]
8001fb8: 2200 movs r2, #0
8001fba: f883 2042 strb.w r2, [r3, #66] @ 0x42
return HAL_OK;
8001fbe: 2300 movs r3, #0
}
8001fc0: 4618 mov r0, r3
8001fc2: 3708 adds r7, #8
8001fc4: 46bd mov sp, r7
8001fc6: bd80 pop {r7, pc}
08001fc8 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
8001fc8: b480 push {r7}
8001fca: b083 sub sp, #12
8001fcc: af00 add r7, sp, #0
8001fce: 6078 str r0, [r7, #4]
8001fd0: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8001fd2: 687b ldr r3, [r7, #4]
8001fd4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8001fd8: b2db uxtb r3, r3
8001fda: 2b20 cmp r3, #32
8001fdc: d138 bne.n 8002050 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8001fde: 687b ldr r3, [r7, #4]
8001fe0: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8001fe4: 2b01 cmp r3, #1
8001fe6: d101 bne.n 8001fec <HAL_I2CEx_ConfigAnalogFilter+0x24>
8001fe8: 2302 movs r3, #2
8001fea: e032 b.n 8002052 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
8001fec: 687b ldr r3, [r7, #4]
8001fee: 2201 movs r2, #1
8001ff0: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8001ff4: 687b ldr r3, [r7, #4]
8001ff6: 2224 movs r2, #36 @ 0x24
8001ff8: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001ffc: 687b ldr r3, [r7, #4]
8001ffe: 681b ldr r3, [r3, #0]
8002000: 681a ldr r2, [r3, #0]
8002002: 687b ldr r3, [r7, #4]
8002004: 681b ldr r3, [r3, #0]
8002006: f022 0201 bic.w r2, r2, #1
800200a: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
800200c: 687b ldr r3, [r7, #4]
800200e: 681b ldr r3, [r3, #0]
8002010: 681a ldr r2, [r3, #0]
8002012: 687b ldr r3, [r7, #4]
8002014: 681b ldr r3, [r3, #0]
8002016: f422 5280 bic.w r2, r2, #4096 @ 0x1000
800201a: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
800201c: 687b ldr r3, [r7, #4]
800201e: 681b ldr r3, [r3, #0]
8002020: 6819 ldr r1, [r3, #0]
8002022: 687b ldr r3, [r7, #4]
8002024: 681b ldr r3, [r3, #0]
8002026: 683a ldr r2, [r7, #0]
8002028: 430a orrs r2, r1
800202a: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
800202c: 687b ldr r3, [r7, #4]
800202e: 681b ldr r3, [r3, #0]
8002030: 681a ldr r2, [r3, #0]
8002032: 687b ldr r3, [r7, #4]
8002034: 681b ldr r3, [r3, #0]
8002036: f042 0201 orr.w r2, r2, #1
800203a: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
800203c: 687b ldr r3, [r7, #4]
800203e: 2220 movs r2, #32
8002040: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002044: 687b ldr r3, [r7, #4]
8002046: 2200 movs r2, #0
8002048: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
800204c: 2300 movs r3, #0
800204e: e000 b.n 8002052 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8002050: 2302 movs r3, #2
}
}
8002052: 4618 mov r0, r3
8002054: 370c adds r7, #12
8002056: 46bd mov sp, r7
8002058: f85d 7b04 ldr.w r7, [sp], #4
800205c: 4770 bx lr
0800205e <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
800205e: b480 push {r7}
8002060: b085 sub sp, #20
8002062: af00 add r7, sp, #0
8002064: 6078 str r0, [r7, #4]
8002066: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8002068: 687b ldr r3, [r7, #4]
800206a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800206e: b2db uxtb r3, r3
8002070: 2b20 cmp r3, #32
8002072: d139 bne.n 80020e8 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8002074: 687b ldr r3, [r7, #4]
8002076: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
800207a: 2b01 cmp r3, #1
800207c: d101 bne.n 8002082 <HAL_I2CEx_ConfigDigitalFilter+0x24>
800207e: 2302 movs r3, #2
8002080: e033 b.n 80020ea <HAL_I2CEx_ConfigDigitalFilter+0x8c>
8002082: 687b ldr r3, [r7, #4]
8002084: 2201 movs r2, #1
8002086: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
800208a: 687b ldr r3, [r7, #4]
800208c: 2224 movs r2, #36 @ 0x24
800208e: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8002092: 687b ldr r3, [r7, #4]
8002094: 681b ldr r3, [r3, #0]
8002096: 681a ldr r2, [r3, #0]
8002098: 687b ldr r3, [r7, #4]
800209a: 681b ldr r3, [r3, #0]
800209c: f022 0201 bic.w r2, r2, #1
80020a0: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
80020a2: 687b ldr r3, [r7, #4]
80020a4: 681b ldr r3, [r3, #0]
80020a6: 681b ldr r3, [r3, #0]
80020a8: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
80020aa: 68fb ldr r3, [r7, #12]
80020ac: f423 6370 bic.w r3, r3, #3840 @ 0xf00
80020b0: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
80020b2: 683b ldr r3, [r7, #0]
80020b4: 021b lsls r3, r3, #8
80020b6: 68fa ldr r2, [r7, #12]
80020b8: 4313 orrs r3, r2
80020ba: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
80020bc: 687b ldr r3, [r7, #4]
80020be: 681b ldr r3, [r3, #0]
80020c0: 68fa ldr r2, [r7, #12]
80020c2: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
80020c4: 687b ldr r3, [r7, #4]
80020c6: 681b ldr r3, [r3, #0]
80020c8: 681a ldr r2, [r3, #0]
80020ca: 687b ldr r3, [r7, #4]
80020cc: 681b ldr r3, [r3, #0]
80020ce: f042 0201 orr.w r2, r2, #1
80020d2: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80020d4: 687b ldr r3, [r7, #4]
80020d6: 2220 movs r2, #32
80020d8: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80020dc: 687b ldr r3, [r7, #4]
80020de: 2200 movs r2, #0
80020e0: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
80020e4: 2300 movs r3, #0
80020e6: e000 b.n 80020ea <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
80020e8: 2302 movs r3, #2
}
}
80020ea: 4618 mov r0, r3
80020ec: 3714 adds r7, #20
80020ee: 46bd mov sp, r7
80020f0: f85d 7b04 ldr.w r7, [sp], #4
80020f4: 4770 bx lr
080020f6 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
80020f6: b580 push {r7, lr}
80020f8: b086 sub sp, #24
80020fa: af02 add r7, sp, #8
80020fc: 6078 str r0, [r7, #4]
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
80020fe: 687b ldr r3, [r7, #4]
8002100: 2b00 cmp r3, #0
8002102: d101 bne.n 8002108 <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8002104: 2301 movs r3, #1
8002106: e101 b.n 800230c <HAL_PCD_Init+0x216>
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
8002108: 687b ldr r3, [r7, #4]
800210a: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
800210e: b2db uxtb r3, r3
8002110: 2b00 cmp r3, #0
8002112: d106 bne.n 8002122 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8002114: 687b ldr r3, [r7, #4]
8002116: 2200 movs r2, #0
8002118: f883 2494 strb.w r2, [r3, #1172] @ 0x494
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
800211c: 6878 ldr r0, [r7, #4]
800211e: f7ff f8d5 bl 80012cc <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8002122: 687b ldr r3, [r7, #4]
8002124: 2203 movs r2, #3
8002126: f883 2495 strb.w r2, [r3, #1173] @ 0x495
/* Disable DMA mode for FS instance */
hpcd->Init.dma_enable = 0U;
800212a: 687b ldr r3, [r7, #4]
800212c: 2200 movs r2, #0
800212e: 719a strb r2, [r3, #6]
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
8002130: 687b ldr r3, [r7, #4]
8002132: 681b ldr r3, [r3, #0]
8002134: 4618 mov r0, r3
8002136: f002 fb0f bl 8004758 <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
800213a: 687b ldr r3, [r7, #4]
800213c: 6818 ldr r0, [r3, #0]
800213e: 687b ldr r3, [r7, #4]
8002140: 7c1a ldrb r2, [r3, #16]
8002142: f88d 2000 strb.w r2, [sp]
8002146: 3304 adds r3, #4
8002148: cb0e ldmia r3, {r1, r2, r3}
800214a: f002 fad8 bl 80046fe <USB_CoreInit>
800214e: 4603 mov r3, r0
8002150: 2b00 cmp r3, #0
8002152: d005 beq.n 8002160 <HAL_PCD_Init+0x6a>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8002154: 687b ldr r3, [r7, #4]
8002156: 2202 movs r2, #2
8002158: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
800215c: 2301 movs r3, #1
800215e: e0d5 b.n 800230c <HAL_PCD_Init+0x216>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
8002160: 687b ldr r3, [r7, #4]
8002162: 681b ldr r3, [r3, #0]
8002164: 2100 movs r1, #0
8002166: 4618 mov r0, r3
8002168: f002 fb07 bl 800477a <USB_SetCurrentMode>
800216c: 4603 mov r3, r0
800216e: 2b00 cmp r3, #0
8002170: d005 beq.n 800217e <HAL_PCD_Init+0x88>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8002172: 687b ldr r3, [r7, #4]
8002174: 2202 movs r2, #2
8002176: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
800217a: 2301 movs r3, #1
800217c: e0c6 b.n 800230c <HAL_PCD_Init+0x216>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
800217e: 2300 movs r3, #0
8002180: 73fb strb r3, [r7, #15]
8002182: e04a b.n 800221a <HAL_PCD_Init+0x124>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
8002184: 7bfa ldrb r2, [r7, #15]
8002186: 6879 ldr r1, [r7, #4]
8002188: 4613 mov r3, r2
800218a: 00db lsls r3, r3, #3
800218c: 4413 add r3, r2
800218e: 009b lsls r3, r3, #2
8002190: 440b add r3, r1
8002192: 3315 adds r3, #21
8002194: 2201 movs r2, #1
8002196: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
8002198: 7bfa ldrb r2, [r7, #15]
800219a: 6879 ldr r1, [r7, #4]
800219c: 4613 mov r3, r2
800219e: 00db lsls r3, r3, #3
80021a0: 4413 add r3, r2
80021a2: 009b lsls r3, r3, #2
80021a4: 440b add r3, r1
80021a6: 3314 adds r3, #20
80021a8: 7bfa ldrb r2, [r7, #15]
80021aa: 701a strb r2, [r3, #0]
#if defined (USB_OTG_FS)
hpcd->IN_ep[i].tx_fifo_num = i;
80021ac: 7bfa ldrb r2, [r7, #15]
80021ae: 7bfb ldrb r3, [r7, #15]
80021b0: b298 uxth r0, r3
80021b2: 6879 ldr r1, [r7, #4]
80021b4: 4613 mov r3, r2
80021b6: 00db lsls r3, r3, #3
80021b8: 4413 add r3, r2
80021ba: 009b lsls r3, r3, #2
80021bc: 440b add r3, r1
80021be: 332e adds r3, #46 @ 0x2e
80021c0: 4602 mov r2, r0
80021c2: 801a strh r2, [r3, #0]
#endif /* defined (USB_OTG_FS) */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
80021c4: 7bfa ldrb r2, [r7, #15]
80021c6: 6879 ldr r1, [r7, #4]
80021c8: 4613 mov r3, r2
80021ca: 00db lsls r3, r3, #3
80021cc: 4413 add r3, r2
80021ce: 009b lsls r3, r3, #2
80021d0: 440b add r3, r1
80021d2: 3318 adds r3, #24
80021d4: 2200 movs r2, #0
80021d6: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
80021d8: 7bfa ldrb r2, [r7, #15]
80021da: 6879 ldr r1, [r7, #4]
80021dc: 4613 mov r3, r2
80021de: 00db lsls r3, r3, #3
80021e0: 4413 add r3, r2
80021e2: 009b lsls r3, r3, #2
80021e4: 440b add r3, r1
80021e6: 331c adds r3, #28
80021e8: 2200 movs r2, #0
80021ea: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
80021ec: 7bfa ldrb r2, [r7, #15]
80021ee: 6879 ldr r1, [r7, #4]
80021f0: 4613 mov r3, r2
80021f2: 00db lsls r3, r3, #3
80021f4: 4413 add r3, r2
80021f6: 009b lsls r3, r3, #2
80021f8: 440b add r3, r1
80021fa: 3320 adds r3, #32
80021fc: 2200 movs r2, #0
80021fe: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8002200: 7bfa ldrb r2, [r7, #15]
8002202: 6879 ldr r1, [r7, #4]
8002204: 4613 mov r3, r2
8002206: 00db lsls r3, r3, #3
8002208: 4413 add r3, r2
800220a: 009b lsls r3, r3, #2
800220c: 440b add r3, r1
800220e: 3324 adds r3, #36 @ 0x24
8002210: 2200 movs r2, #0
8002212: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8002214: 7bfb ldrb r3, [r7, #15]
8002216: 3301 adds r3, #1
8002218: 73fb strb r3, [r7, #15]
800221a: 687b ldr r3, [r7, #4]
800221c: 791b ldrb r3, [r3, #4]
800221e: 7bfa ldrb r2, [r7, #15]
8002220: 429a cmp r2, r3
8002222: d3af bcc.n 8002184 <HAL_PCD_Init+0x8e>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8002224: 2300 movs r3, #0
8002226: 73fb strb r3, [r7, #15]
8002228: e044 b.n 80022b4 <HAL_PCD_Init+0x1be>
{
hpcd->OUT_ep[i].is_in = 0U;
800222a: 7bfa ldrb r2, [r7, #15]
800222c: 6879 ldr r1, [r7, #4]
800222e: 4613 mov r3, r2
8002230: 00db lsls r3, r3, #3
8002232: 4413 add r3, r2
8002234: 009b lsls r3, r3, #2
8002236: 440b add r3, r1
8002238: f203 2355 addw r3, r3, #597 @ 0x255
800223c: 2200 movs r2, #0
800223e: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8002240: 7bfa ldrb r2, [r7, #15]
8002242: 6879 ldr r1, [r7, #4]
8002244: 4613 mov r3, r2
8002246: 00db lsls r3, r3, #3
8002248: 4413 add r3, r2
800224a: 009b lsls r3, r3, #2
800224c: 440b add r3, r1
800224e: f503 7315 add.w r3, r3, #596 @ 0x254
8002252: 7bfa ldrb r2, [r7, #15]
8002254: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8002256: 7bfa ldrb r2, [r7, #15]
8002258: 6879 ldr r1, [r7, #4]
800225a: 4613 mov r3, r2
800225c: 00db lsls r3, r3, #3
800225e: 4413 add r3, r2
8002260: 009b lsls r3, r3, #2
8002262: 440b add r3, r1
8002264: f503 7316 add.w r3, r3, #600 @ 0x258
8002268: 2200 movs r2, #0
800226a: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
800226c: 7bfa ldrb r2, [r7, #15]
800226e: 6879 ldr r1, [r7, #4]
8002270: 4613 mov r3, r2
8002272: 00db lsls r3, r3, #3
8002274: 4413 add r3, r2
8002276: 009b lsls r3, r3, #2
8002278: 440b add r3, r1
800227a: f503 7317 add.w r3, r3, #604 @ 0x25c
800227e: 2200 movs r2, #0
8002280: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8002282: 7bfa ldrb r2, [r7, #15]
8002284: 6879 ldr r1, [r7, #4]
8002286: 4613 mov r3, r2
8002288: 00db lsls r3, r3, #3
800228a: 4413 add r3, r2
800228c: 009b lsls r3, r3, #2
800228e: 440b add r3, r1
8002290: f503 7318 add.w r3, r3, #608 @ 0x260
8002294: 2200 movs r2, #0
8002296: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8002298: 7bfa ldrb r2, [r7, #15]
800229a: 6879 ldr r1, [r7, #4]
800229c: 4613 mov r3, r2
800229e: 00db lsls r3, r3, #3
80022a0: 4413 add r3, r2
80022a2: 009b lsls r3, r3, #2
80022a4: 440b add r3, r1
80022a6: f503 7319 add.w r3, r3, #612 @ 0x264
80022aa: 2200 movs r2, #0
80022ac: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80022ae: 7bfb ldrb r3, [r7, #15]
80022b0: 3301 adds r3, #1
80022b2: 73fb strb r3, [r7, #15]
80022b4: 687b ldr r3, [r7, #4]
80022b6: 791b ldrb r3, [r3, #4]
80022b8: 7bfa ldrb r2, [r7, #15]
80022ba: 429a cmp r2, r3
80022bc: d3b5 bcc.n 800222a <HAL_PCD_Init+0x134>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
80022be: 687b ldr r3, [r7, #4]
80022c0: 6818 ldr r0, [r3, #0]
80022c2: 687b ldr r3, [r7, #4]
80022c4: 7c1a ldrb r2, [r3, #16]
80022c6: f88d 2000 strb.w r2, [sp]
80022ca: 3304 adds r3, #4
80022cc: cb0e ldmia r3, {r1, r2, r3}
80022ce: f002 faa1 bl 8004814 <USB_DevInit>
80022d2: 4603 mov r3, r0
80022d4: 2b00 cmp r3, #0
80022d6: d005 beq.n 80022e4 <HAL_PCD_Init+0x1ee>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80022d8: 687b ldr r3, [r7, #4]
80022da: 2202 movs r2, #2
80022dc: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
80022e0: 2301 movs r3, #1
80022e2: e013 b.n 800230c <HAL_PCD_Init+0x216>
}
hpcd->USB_Address = 0U;
80022e4: 687b ldr r3, [r7, #4]
80022e6: 2200 movs r2, #0
80022e8: 745a strb r2, [r3, #17]
hpcd->State = HAL_PCD_STATE_READY;
80022ea: 687b ldr r3, [r7, #4]
80022ec: 2201 movs r2, #1
80022ee: f883 2495 strb.w r2, [r3, #1173] @ 0x495
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
80022f2: 687b ldr r3, [r7, #4]
80022f4: 7b1b ldrb r3, [r3, #12]
80022f6: 2b01 cmp r3, #1
80022f8: d102 bne.n 8002300 <HAL_PCD_Init+0x20a>
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
80022fa: 6878 ldr r0, [r7, #4]
80022fc: f000 f80a bl 8002314 <HAL_PCDEx_ActivateLPM>
}
(void)USB_DevDisconnect(hpcd->Instance);
8002300: 687b ldr r3, [r7, #4]
8002302: 681b ldr r3, [r3, #0]
8002304: 4618 mov r0, r3
8002306: f002 fc46 bl 8004b96 <USB_DevDisconnect>
return HAL_OK;
800230a: 2300 movs r3, #0
}
800230c: 4618 mov r0, r3
800230e: 3710 adds r7, #16
8002310: 46bd mov sp, r7
8002312: bd80 pop {r7, pc}
08002314 <HAL_PCDEx_ActivateLPM>:
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
8002314: b480 push {r7}
8002316: b085 sub sp, #20
8002318: af00 add r7, sp, #0
800231a: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
800231c: 687b ldr r3, [r7, #4]
800231e: 681b ldr r3, [r3, #0]
8002320: 60fb str r3, [r7, #12]
hpcd->lpm_active = 1U;
8002322: 687b ldr r3, [r7, #4]
8002324: 2201 movs r2, #1
8002326: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
hpcd->LPM_State = LPM_L0;
800232a: 687b ldr r3, [r7, #4]
800232c: 2200 movs r2, #0
800232e: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
8002332: 68fb ldr r3, [r7, #12]
8002334: 699b ldr r3, [r3, #24]
8002336: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
800233a: 68fb ldr r3, [r7, #12]
800233c: 619a str r2, [r3, #24]
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
800233e: 68fb ldr r3, [r7, #12]
8002340: 6d5b ldr r3, [r3, #84] @ 0x54
8002342: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002346: f043 0303 orr.w r3, r3, #3
800234a: 68fa ldr r2, [r7, #12]
800234c: 6553 str r3, [r2, #84] @ 0x54
return HAL_OK;
800234e: 2300 movs r3, #0
}
8002350: 4618 mov r0, r3
8002352: 3714 adds r7, #20
8002354: 46bd mov sp, r7
8002356: f85d 7b04 ldr.w r7, [sp], #4
800235a: 4770 bx lr
0800235c <HAL_PWR_EnableBkUpAccess>:
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
* back-up domain.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
800235c: b480 push {r7}
800235e: af00 add r7, sp, #0
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8002360: 4b05 ldr r3, [pc, #20] @ (8002378 <HAL_PWR_EnableBkUpAccess+0x1c>)
8002362: 681b ldr r3, [r3, #0]
8002364: 4a04 ldr r2, [pc, #16] @ (8002378 <HAL_PWR_EnableBkUpAccess+0x1c>)
8002366: f443 7380 orr.w r3, r3, #256 @ 0x100
800236a: 6013 str r3, [r2, #0]
}
800236c: bf00 nop
800236e: 46bd mov sp, r7
8002370: f85d 7b04 ldr.w r7, [sp], #4
8002374: 4770 bx lr
8002376: bf00 nop
8002378: 40007000 .word 0x40007000
0800237c <HAL_PWREx_GetVoltageRange>:
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
800237c: b480 push {r7}
800237e: af00 add r7, sp, #0
else
{
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
}
#else
return (PWR->CR1 & PWR_CR1_VOS);
8002380: 4b04 ldr r3, [pc, #16] @ (8002394 <HAL_PWREx_GetVoltageRange+0x18>)
8002382: 681b ldr r3, [r3, #0]
8002384: f403 63c0 and.w r3, r3, #1536 @ 0x600
#endif
}
8002388: 4618 mov r0, r3
800238a: 46bd mov sp, r7
800238c: f85d 7b04 ldr.w r7, [sp], #4
8002390: 4770 bx lr
8002392: bf00 nop
8002394: 40007000 .word 0x40007000
08002398 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8002398: b480 push {r7}
800239a: b085 sub sp, #20
800239c: af00 add r7, sp, #0
800239e: 6078 str r0, [r7, #4]
}
#else
/* If Set Range 1 */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
80023a0: 687b ldr r3, [r7, #4]
80023a2: f5b3 7f00 cmp.w r3, #512 @ 0x200
80023a6: d130 bne.n 800240a <HAL_PWREx_ControlVoltageScaling+0x72>
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
80023a8: 4b23 ldr r3, [pc, #140] @ (8002438 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80023aa: 681b ldr r3, [r3, #0]
80023ac: f403 63c0 and.w r3, r3, #1536 @ 0x600
80023b0: f5b3 7f00 cmp.w r3, #512 @ 0x200
80023b4: d038 beq.n 8002428 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
80023b6: 4b20 ldr r3, [pc, #128] @ (8002438 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80023b8: 681b ldr r3, [r3, #0]
80023ba: f423 63c0 bic.w r3, r3, #1536 @ 0x600
80023be: 4a1e ldr r2, [pc, #120] @ (8002438 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80023c0: f443 7300 orr.w r3, r3, #512 @ 0x200
80023c4: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
80023c6: 4b1d ldr r3, [pc, #116] @ (800243c <HAL_PWREx_ControlVoltageScaling+0xa4>)
80023c8: 681b ldr r3, [r3, #0]
80023ca: 2232 movs r2, #50 @ 0x32
80023cc: fb02 f303 mul.w r3, r2, r3
80023d0: 4a1b ldr r2, [pc, #108] @ (8002440 <HAL_PWREx_ControlVoltageScaling+0xa8>)
80023d2: fba2 2303 umull r2, r3, r2, r3
80023d6: 0c9b lsrs r3, r3, #18
80023d8: 3301 adds r3, #1
80023da: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80023dc: e002 b.n 80023e4 <HAL_PWREx_ControlVoltageScaling+0x4c>
{
wait_loop_index--;
80023de: 68fb ldr r3, [r7, #12]
80023e0: 3b01 subs r3, #1
80023e2: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80023e4: 4b14 ldr r3, [pc, #80] @ (8002438 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80023e6: 695b ldr r3, [r3, #20]
80023e8: f403 6380 and.w r3, r3, #1024 @ 0x400
80023ec: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80023f0: d102 bne.n 80023f8 <HAL_PWREx_ControlVoltageScaling+0x60>
80023f2: 68fb ldr r3, [r7, #12]
80023f4: 2b00 cmp r3, #0
80023f6: d1f2 bne.n 80023de <HAL_PWREx_ControlVoltageScaling+0x46>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
80023f8: 4b0f ldr r3, [pc, #60] @ (8002438 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80023fa: 695b ldr r3, [r3, #20]
80023fc: f403 6380 and.w r3, r3, #1024 @ 0x400
8002400: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002404: d110 bne.n 8002428 <HAL_PWREx_ControlVoltageScaling+0x90>
{
return HAL_TIMEOUT;
8002406: 2303 movs r3, #3
8002408: e00f b.n 800242a <HAL_PWREx_ControlVoltageScaling+0x92>
}
}
}
else
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
800240a: 4b0b ldr r3, [pc, #44] @ (8002438 <HAL_PWREx_ControlVoltageScaling+0xa0>)
800240c: 681b ldr r3, [r3, #0]
800240e: f403 63c0 and.w r3, r3, #1536 @ 0x600
8002412: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002416: d007 beq.n 8002428 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
8002418: 4b07 ldr r3, [pc, #28] @ (8002438 <HAL_PWREx_ControlVoltageScaling+0xa0>)
800241a: 681b ldr r3, [r3, #0]
800241c: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8002420: 4a05 ldr r2, [pc, #20] @ (8002438 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002422: f443 6380 orr.w r3, r3, #1024 @ 0x400
8002426: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
}
}
#endif
return HAL_OK;
8002428: 2300 movs r3, #0
}
800242a: 4618 mov r0, r3
800242c: 3714 adds r7, #20
800242e: 46bd mov sp, r7
8002430: f85d 7b04 ldr.w r7, [sp], #4
8002434: 4770 bx lr
8002436: bf00 nop
8002438: 40007000 .word 0x40007000
800243c: 20000004 .word 0x20000004
8002440: 431bde83 .word 0x431bde83
08002444 <HAL_PWREx_EnableVddUSB>:
* @brief Enable VDDUSB supply.
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
* @retval None
*/
void HAL_PWREx_EnableVddUSB(void)
{
8002444: b480 push {r7}
8002446: af00 add r7, sp, #0
SET_BIT(PWR->CR2, PWR_CR2_USV);
8002448: 4b05 ldr r3, [pc, #20] @ (8002460 <HAL_PWREx_EnableVddUSB+0x1c>)
800244a: 685b ldr r3, [r3, #4]
800244c: 4a04 ldr r2, [pc, #16] @ (8002460 <HAL_PWREx_EnableVddUSB+0x1c>)
800244e: f443 6380 orr.w r3, r3, #1024 @ 0x400
8002452: 6053 str r3, [r2, #4]
}
8002454: bf00 nop
8002456: 46bd mov sp, r7
8002458: f85d 7b04 ldr.w r7, [sp], #4
800245c: 4770 bx lr
800245e: bf00 nop
8002460: 40007000 .word 0x40007000
08002464 <HAL_QSPI_Init>:
* in the QSPI_InitTypeDef and initialize the associated handle.
* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
{
8002464: b580 push {r7, lr}
8002466: b086 sub sp, #24
8002468: af02 add r7, sp, #8
800246a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
800246c: f7ff f8c6 bl 80015fc <HAL_GetTick>
8002470: 60f8 str r0, [r7, #12]
/* Check the QSPI handle allocation */
if(hqspi == NULL)
8002472: 687b ldr r3, [r7, #4]
8002474: 2b00 cmp r3, #0
8002476: d101 bne.n 800247c <HAL_QSPI_Init+0x18>
{
return HAL_ERROR;
8002478: 2301 movs r3, #1
800247a: e063 b.n 8002544 <HAL_QSPI_Init+0xe0>
{
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
}
#endif
if(hqspi->State == HAL_QSPI_STATE_RESET)
800247c: 687b ldr r3, [r7, #4]
800247e: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8002482: b2db uxtb r3, r3
8002484: 2b00 cmp r3, #0
8002486: d10b bne.n 80024a0 <HAL_QSPI_Init+0x3c>
{
/* Allocate lock resource and initialize it */
hqspi->Lock = HAL_UNLOCKED;
8002488: 687b ldr r3, [r7, #4]
800248a: 2200 movs r2, #0
800248c: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* Init the low level hardware */
hqspi->MspInitCallback(hqspi);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_QSPI_MspInit(hqspi);
8002490: 6878 ldr r0, [r7, #4]
8002492: f7fe fdef bl 8001074 <HAL_QSPI_MspInit>
#endif
/* Configure the default timeout for the QSPI memory access */
HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
8002496: f241 3188 movw r1, #5000 @ 0x1388
800249a: 6878 ldr r0, [r7, #4]
800249c: f000 f858 bl 8002550 <HAL_QSPI_SetTimeout>
}
/* Configure QSPI FIFO Threshold */
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
80024a0: 687b ldr r3, [r7, #4]
80024a2: 681b ldr r3, [r3, #0]
80024a4: 681b ldr r3, [r3, #0]
80024a6: f423 6170 bic.w r1, r3, #3840 @ 0xf00
80024aa: 687b ldr r3, [r7, #4]
80024ac: 689b ldr r3, [r3, #8]
80024ae: 3b01 subs r3, #1
80024b0: 021a lsls r2, r3, #8
80024b2: 687b ldr r3, [r7, #4]
80024b4: 681b ldr r3, [r3, #0]
80024b6: 430a orrs r2, r1
80024b8: 601a str r2, [r3, #0]
((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
80024ba: 687b ldr r3, [r7, #4]
80024bc: 6c1b ldr r3, [r3, #64] @ 0x40
80024be: 9300 str r3, [sp, #0]
80024c0: 68fb ldr r3, [r7, #12]
80024c2: 2200 movs r2, #0
80024c4: 2120 movs r1, #32
80024c6: 6878 ldr r0, [r7, #4]
80024c8: f000 f850 bl 800256c <QSPI_WaitFlagStateUntilTimeout>
80024cc: 4603 mov r3, r0
80024ce: 72fb strb r3, [r7, #11]
if(status == HAL_OK)
80024d0: 7afb ldrb r3, [r7, #11]
80024d2: 2b00 cmp r3, #0
80024d4: d131 bne.n 800253a <HAL_QSPI_Init+0xd6>
#if defined(QUADSPI_CR_DFM)
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
#else
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
80024d6: 687b ldr r3, [r7, #4]
80024d8: 681b ldr r3, [r3, #0]
80024da: 681b ldr r3, [r3, #0]
80024dc: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000
80024e0: f023 0310 bic.w r3, r3, #16
80024e4: 687a ldr r2, [r7, #4]
80024e6: 6852 ldr r2, [r2, #4]
80024e8: 0611 lsls r1, r2, #24
80024ea: 687a ldr r2, [r7, #4]
80024ec: 68d2 ldr r2, [r2, #12]
80024ee: 4311 orrs r1, r2
80024f0: 687a ldr r2, [r7, #4]
80024f2: 6812 ldr r2, [r2, #0]
80024f4: 430b orrs r3, r1
80024f6: 6013 str r3, [r2, #0]
((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
hqspi->Init.SampleShifting));
#endif
/* Configure QSPI Flash Size, CS High Time and Clock Mode */
MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
80024f8: 687b ldr r3, [r7, #4]
80024fa: 681b ldr r3, [r3, #0]
80024fc: 685a ldr r2, [r3, #4]
80024fe: 4b13 ldr r3, [pc, #76] @ (800254c <HAL_QSPI_Init+0xe8>)
8002500: 4013 ands r3, r2
8002502: 687a ldr r2, [r7, #4]
8002504: 6912 ldr r2, [r2, #16]
8002506: 0411 lsls r1, r2, #16
8002508: 687a ldr r2, [r7, #4]
800250a: 6952 ldr r2, [r2, #20]
800250c: 4311 orrs r1, r2
800250e: 687a ldr r2, [r7, #4]
8002510: 6992 ldr r2, [r2, #24]
8002512: 4311 orrs r1, r2
8002514: 687a ldr r2, [r7, #4]
8002516: 6812 ldr r2, [r2, #0]
8002518: 430b orrs r3, r1
800251a: 6053 str r3, [r2, #4]
((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
/* Enable the QSPI peripheral */
__HAL_QSPI_ENABLE(hqspi);
800251c: 687b ldr r3, [r7, #4]
800251e: 681b ldr r3, [r3, #0]
8002520: 681a ldr r2, [r3, #0]
8002522: 687b ldr r3, [r7, #4]
8002524: 681b ldr r3, [r3, #0]
8002526: f042 0201 orr.w r2, r2, #1
800252a: 601a str r2, [r3, #0]
/* Set QSPI error code to none */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
800252c: 687b ldr r3, [r7, #4]
800252e: 2200 movs r2, #0
8002530: 63da str r2, [r3, #60] @ 0x3c
/* Initialize the QSPI state */
hqspi->State = HAL_QSPI_STATE_READY;
8002532: 687b ldr r3, [r7, #4]
8002534: 2201 movs r2, #1
8002536: f883 2039 strb.w r2, [r3, #57] @ 0x39
}
/* Release Lock */
__HAL_UNLOCK(hqspi);
800253a: 687b ldr r3, [r7, #4]
800253c: 2200 movs r2, #0
800253e: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* Return function status */
return status;
8002542: 7afb ldrb r3, [r7, #11]
}
8002544: 4618 mov r0, r3
8002546: 3710 adds r7, #16
8002548: 46bd mov sp, r7
800254a: bd80 pop {r7, pc}
800254c: ffe0f8fe .word 0xffe0f8fe
08002550 <HAL_QSPI_SetTimeout>:
* @param hqspi QSPI handle.
* @param Timeout Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
{
8002550: b480 push {r7}
8002552: b083 sub sp, #12
8002554: af00 add r7, sp, #0
8002556: 6078 str r0, [r7, #4]
8002558: 6039 str r1, [r7, #0]
hqspi->Timeout = Timeout;
800255a: 687b ldr r3, [r7, #4]
800255c: 683a ldr r2, [r7, #0]
800255e: 641a str r2, [r3, #64] @ 0x40
}
8002560: bf00 nop
8002562: 370c adds r7, #12
8002564: 46bd mov sp, r7
8002566: f85d 7b04 ldr.w r7, [sp], #4
800256a: 4770 bx lr
0800256c <QSPI_WaitFlagStateUntilTimeout>:
* @param Timeout Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
800256c: b580 push {r7, lr}
800256e: b084 sub sp, #16
8002570: af00 add r7, sp, #0
8002572: 60f8 str r0, [r7, #12]
8002574: 60b9 str r1, [r7, #8]
8002576: 603b str r3, [r7, #0]
8002578: 4613 mov r3, r2
800257a: 71fb strb r3, [r7, #7]
/* Wait until flag is in expected state */
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
800257c: e01a b.n 80025b4 <QSPI_WaitFlagStateUntilTimeout+0x48>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800257e: 69bb ldr r3, [r7, #24]
8002580: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8002584: d016 beq.n 80025b4 <QSPI_WaitFlagStateUntilTimeout+0x48>
{
if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8002586: f7ff f839 bl 80015fc <HAL_GetTick>
800258a: 4602 mov r2, r0
800258c: 683b ldr r3, [r7, #0]
800258e: 1ad3 subs r3, r2, r3
8002590: 69ba ldr r2, [r7, #24]
8002592: 429a cmp r2, r3
8002594: d302 bcc.n 800259c <QSPI_WaitFlagStateUntilTimeout+0x30>
8002596: 69bb ldr r3, [r7, #24]
8002598: 2b00 cmp r3, #0
800259a: d10b bne.n 80025b4 <QSPI_WaitFlagStateUntilTimeout+0x48>
{
hqspi->State = HAL_QSPI_STATE_ERROR;
800259c: 68fb ldr r3, [r7, #12]
800259e: 2204 movs r2, #4
80025a0: f883 2039 strb.w r2, [r3, #57] @ 0x39
hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
80025a4: 68fb ldr r3, [r7, #12]
80025a6: 6bdb ldr r3, [r3, #60] @ 0x3c
80025a8: f043 0201 orr.w r2, r3, #1
80025ac: 68fb ldr r3, [r7, #12]
80025ae: 63da str r2, [r3, #60] @ 0x3c
return HAL_ERROR;
80025b0: 2301 movs r3, #1
80025b2: e00e b.n 80025d2 <QSPI_WaitFlagStateUntilTimeout+0x66>
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
80025b4: 68fb ldr r3, [r7, #12]
80025b6: 681b ldr r3, [r3, #0]
80025b8: 689a ldr r2, [r3, #8]
80025ba: 68bb ldr r3, [r7, #8]
80025bc: 4013 ands r3, r2
80025be: 2b00 cmp r3, #0
80025c0: bf14 ite ne
80025c2: 2301 movne r3, #1
80025c4: 2300 moveq r3, #0
80025c6: b2db uxtb r3, r3
80025c8: 461a mov r2, r3
80025ca: 79fb ldrb r3, [r7, #7]
80025cc: 429a cmp r2, r3
80025ce: d1d6 bne.n 800257e <QSPI_WaitFlagStateUntilTimeout+0x12>
}
}
}
return HAL_OK;
80025d0: 2300 movs r3, #0
}
80025d2: 4618 mov r0, r3
80025d4: 3710 adds r7, #16
80025d6: 46bd mov sp, r7
80025d8: bd80 pop {r7, pc}
...
080025dc <HAL_RCC_OscConfig>:
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80025dc: b580 push {r7, lr}
80025de: b088 sub sp, #32
80025e0: af00 add r7, sp, #0
80025e2: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
80025e4: 687b ldr r3, [r7, #4]
80025e6: 2b00 cmp r3, #0
80025e8: d101 bne.n 80025ee <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80025ea: 2301 movs r3, #1
80025ec: e3ca b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
80025ee: 4b97 ldr r3, [pc, #604] @ (800284c <HAL_RCC_OscConfig+0x270>)
80025f0: 689b ldr r3, [r3, #8]
80025f2: f003 030c and.w r3, r3, #12
80025f6: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
80025f8: 4b94 ldr r3, [pc, #592] @ (800284c <HAL_RCC_OscConfig+0x270>)
80025fa: 68db ldr r3, [r3, #12]
80025fc: f003 0303 and.w r3, r3, #3
8002600: 617b str r3, [r7, #20]
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8002602: 687b ldr r3, [r7, #4]
8002604: 681b ldr r3, [r3, #0]
8002606: f003 0310 and.w r3, r3, #16
800260a: 2b00 cmp r3, #0
800260c: f000 80e4 beq.w 80027d8 <HAL_RCC_OscConfig+0x1fc>
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
8002610: 69bb ldr r3, [r7, #24]
8002612: 2b00 cmp r3, #0
8002614: d007 beq.n 8002626 <HAL_RCC_OscConfig+0x4a>
8002616: 69bb ldr r3, [r7, #24]
8002618: 2b0c cmp r3, #12
800261a: f040 808b bne.w 8002734 <HAL_RCC_OscConfig+0x158>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
800261e: 697b ldr r3, [r7, #20]
8002620: 2b01 cmp r3, #1
8002622: f040 8087 bne.w 8002734 <HAL_RCC_OscConfig+0x158>
{
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8002626: 4b89 ldr r3, [pc, #548] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002628: 681b ldr r3, [r3, #0]
800262a: f003 0302 and.w r3, r3, #2
800262e: 2b00 cmp r3, #0
8002630: d005 beq.n 800263e <HAL_RCC_OscConfig+0x62>
8002632: 687b ldr r3, [r7, #4]
8002634: 699b ldr r3, [r3, #24]
8002636: 2b00 cmp r3, #0
8002638: d101 bne.n 800263e <HAL_RCC_OscConfig+0x62>
{
return HAL_ERROR;
800263a: 2301 movs r3, #1
800263c: e3a2 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
else
{
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
800263e: 687b ldr r3, [r7, #4]
8002640: 6a1a ldr r2, [r3, #32]
8002642: 4b82 ldr r3, [pc, #520] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002644: 681b ldr r3, [r3, #0]
8002646: f003 0308 and.w r3, r3, #8
800264a: 2b00 cmp r3, #0
800264c: d004 beq.n 8002658 <HAL_RCC_OscConfig+0x7c>
800264e: 4b7f ldr r3, [pc, #508] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002650: 681b ldr r3, [r3, #0]
8002652: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002656: e005 b.n 8002664 <HAL_RCC_OscConfig+0x88>
8002658: 4b7c ldr r3, [pc, #496] @ (800284c <HAL_RCC_OscConfig+0x270>)
800265a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800265e: 091b lsrs r3, r3, #4
8002660: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002664: 4293 cmp r3, r2
8002666: d223 bcs.n 80026b0 <HAL_RCC_OscConfig+0xd4>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8002668: 687b ldr r3, [r7, #4]
800266a: 6a1b ldr r3, [r3, #32]
800266c: 4618 mov r0, r3
800266e: f000 fd55 bl 800311c <RCC_SetFlashLatencyFromMSIRange>
8002672: 4603 mov r3, r0
8002674: 2b00 cmp r3, #0
8002676: d001 beq.n 800267c <HAL_RCC_OscConfig+0xa0>
{
return HAL_ERROR;
8002678: 2301 movs r3, #1
800267a: e383 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
800267c: 4b73 ldr r3, [pc, #460] @ (800284c <HAL_RCC_OscConfig+0x270>)
800267e: 681b ldr r3, [r3, #0]
8002680: 4a72 ldr r2, [pc, #456] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002682: f043 0308 orr.w r3, r3, #8
8002686: 6013 str r3, [r2, #0]
8002688: 4b70 ldr r3, [pc, #448] @ (800284c <HAL_RCC_OscConfig+0x270>)
800268a: 681b ldr r3, [r3, #0]
800268c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002690: 687b ldr r3, [r7, #4]
8002692: 6a1b ldr r3, [r3, #32]
8002694: 496d ldr r1, [pc, #436] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002696: 4313 orrs r3, r2
8002698: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
800269a: 4b6c ldr r3, [pc, #432] @ (800284c <HAL_RCC_OscConfig+0x270>)
800269c: 685b ldr r3, [r3, #4]
800269e: f423 427f bic.w r2, r3, #65280 @ 0xff00
80026a2: 687b ldr r3, [r7, #4]
80026a4: 69db ldr r3, [r3, #28]
80026a6: 021b lsls r3, r3, #8
80026a8: 4968 ldr r1, [pc, #416] @ (800284c <HAL_RCC_OscConfig+0x270>)
80026aa: 4313 orrs r3, r2
80026ac: 604b str r3, [r1, #4]
80026ae: e025 b.n 80026fc <HAL_RCC_OscConfig+0x120>
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80026b0: 4b66 ldr r3, [pc, #408] @ (800284c <HAL_RCC_OscConfig+0x270>)
80026b2: 681b ldr r3, [r3, #0]
80026b4: 4a65 ldr r2, [pc, #404] @ (800284c <HAL_RCC_OscConfig+0x270>)
80026b6: f043 0308 orr.w r3, r3, #8
80026ba: 6013 str r3, [r2, #0]
80026bc: 4b63 ldr r3, [pc, #396] @ (800284c <HAL_RCC_OscConfig+0x270>)
80026be: 681b ldr r3, [r3, #0]
80026c0: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80026c4: 687b ldr r3, [r7, #4]
80026c6: 6a1b ldr r3, [r3, #32]
80026c8: 4960 ldr r1, [pc, #384] @ (800284c <HAL_RCC_OscConfig+0x270>)
80026ca: 4313 orrs r3, r2
80026cc: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80026ce: 4b5f ldr r3, [pc, #380] @ (800284c <HAL_RCC_OscConfig+0x270>)
80026d0: 685b ldr r3, [r3, #4]
80026d2: f423 427f bic.w r2, r3, #65280 @ 0xff00
80026d6: 687b ldr r3, [r7, #4]
80026d8: 69db ldr r3, [r3, #28]
80026da: 021b lsls r3, r3, #8
80026dc: 495b ldr r1, [pc, #364] @ (800284c <HAL_RCC_OscConfig+0x270>)
80026de: 4313 orrs r3, r2
80026e0: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
/* Only possible when MSI is the System clock source */
if(sysclk_source == RCC_CFGR_SWS_MSI)
80026e2: 69bb ldr r3, [r7, #24]
80026e4: 2b00 cmp r3, #0
80026e6: d109 bne.n 80026fc <HAL_RCC_OscConfig+0x120>
{
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
80026e8: 687b ldr r3, [r7, #4]
80026ea: 6a1b ldr r3, [r3, #32]
80026ec: 4618 mov r0, r3
80026ee: f000 fd15 bl 800311c <RCC_SetFlashLatencyFromMSIRange>
80026f2: 4603 mov r3, r0
80026f4: 2b00 cmp r3, #0
80026f6: d001 beq.n 80026fc <HAL_RCC_OscConfig+0x120>
{
return HAL_ERROR;
80026f8: 2301 movs r3, #1
80026fa: e343 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
80026fc: f000 fc4a bl 8002f94 <HAL_RCC_GetSysClockFreq>
8002700: 4602 mov r2, r0
8002702: 4b52 ldr r3, [pc, #328] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002704: 689b ldr r3, [r3, #8]
8002706: 091b lsrs r3, r3, #4
8002708: f003 030f and.w r3, r3, #15
800270c: 4950 ldr r1, [pc, #320] @ (8002850 <HAL_RCC_OscConfig+0x274>)
800270e: 5ccb ldrb r3, [r1, r3]
8002710: f003 031f and.w r3, r3, #31
8002714: fa22 f303 lsr.w r3, r2, r3
8002718: 4a4e ldr r2, [pc, #312] @ (8002854 <HAL_RCC_OscConfig+0x278>)
800271a: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
800271c: 4b4e ldr r3, [pc, #312] @ (8002858 <HAL_RCC_OscConfig+0x27c>)
800271e: 681b ldr r3, [r3, #0]
8002720: 4618 mov r0, r3
8002722: f7fe ff1b bl 800155c <HAL_InitTick>
8002726: 4603 mov r3, r0
8002728: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
800272a: 7bfb ldrb r3, [r7, #15]
800272c: 2b00 cmp r3, #0
800272e: d052 beq.n 80027d6 <HAL_RCC_OscConfig+0x1fa>
{
return status;
8002730: 7bfb ldrb r3, [r7, #15]
8002732: e327 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
}
else
{
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8002734: 687b ldr r3, [r7, #4]
8002736: 699b ldr r3, [r3, #24]
8002738: 2b00 cmp r3, #0
800273a: d032 beq.n 80027a2 <HAL_RCC_OscConfig+0x1c6>
{
/* Enable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
800273c: 4b43 ldr r3, [pc, #268] @ (800284c <HAL_RCC_OscConfig+0x270>)
800273e: 681b ldr r3, [r3, #0]
8002740: 4a42 ldr r2, [pc, #264] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002742: f043 0301 orr.w r3, r3, #1
8002746: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8002748: f7fe ff58 bl 80015fc <HAL_GetTick>
800274c: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
800274e: e008 b.n 8002762 <HAL_RCC_OscConfig+0x186>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8002750: f7fe ff54 bl 80015fc <HAL_GetTick>
8002754: 4602 mov r2, r0
8002756: 693b ldr r3, [r7, #16]
8002758: 1ad3 subs r3, r2, r3
800275a: 2b02 cmp r3, #2
800275c: d901 bls.n 8002762 <HAL_RCC_OscConfig+0x186>
{
return HAL_TIMEOUT;
800275e: 2303 movs r3, #3
8002760: e310 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8002762: 4b3a ldr r3, [pc, #232] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002764: 681b ldr r3, [r3, #0]
8002766: f003 0302 and.w r3, r3, #2
800276a: 2b00 cmp r3, #0
800276c: d0f0 beq.n 8002750 <HAL_RCC_OscConfig+0x174>
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
800276e: 4b37 ldr r3, [pc, #220] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002770: 681b ldr r3, [r3, #0]
8002772: 4a36 ldr r2, [pc, #216] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002774: f043 0308 orr.w r3, r3, #8
8002778: 6013 str r3, [r2, #0]
800277a: 4b34 ldr r3, [pc, #208] @ (800284c <HAL_RCC_OscConfig+0x270>)
800277c: 681b ldr r3, [r3, #0]
800277e: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002782: 687b ldr r3, [r7, #4]
8002784: 6a1b ldr r3, [r3, #32]
8002786: 4931 ldr r1, [pc, #196] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002788: 4313 orrs r3, r2
800278a: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
800278c: 4b2f ldr r3, [pc, #188] @ (800284c <HAL_RCC_OscConfig+0x270>)
800278e: 685b ldr r3, [r3, #4]
8002790: f423 427f bic.w r2, r3, #65280 @ 0xff00
8002794: 687b ldr r3, [r7, #4]
8002796: 69db ldr r3, [r3, #28]
8002798: 021b lsls r3, r3, #8
800279a: 492c ldr r1, [pc, #176] @ (800284c <HAL_RCC_OscConfig+0x270>)
800279c: 4313 orrs r3, r2
800279e: 604b str r3, [r1, #4]
80027a0: e01a b.n 80027d8 <HAL_RCC_OscConfig+0x1fc>
}
else
{
/* Disable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
80027a2: 4b2a ldr r3, [pc, #168] @ (800284c <HAL_RCC_OscConfig+0x270>)
80027a4: 681b ldr r3, [r3, #0]
80027a6: 4a29 ldr r2, [pc, #164] @ (800284c <HAL_RCC_OscConfig+0x270>)
80027a8: f023 0301 bic.w r3, r3, #1
80027ac: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
80027ae: f7fe ff25 bl 80015fc <HAL_GetTick>
80027b2: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
80027b4: e008 b.n 80027c8 <HAL_RCC_OscConfig+0x1ec>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
80027b6: f7fe ff21 bl 80015fc <HAL_GetTick>
80027ba: 4602 mov r2, r0
80027bc: 693b ldr r3, [r7, #16]
80027be: 1ad3 subs r3, r2, r3
80027c0: 2b02 cmp r3, #2
80027c2: d901 bls.n 80027c8 <HAL_RCC_OscConfig+0x1ec>
{
return HAL_TIMEOUT;
80027c4: 2303 movs r3, #3
80027c6: e2dd b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
80027c8: 4b20 ldr r3, [pc, #128] @ (800284c <HAL_RCC_OscConfig+0x270>)
80027ca: 681b ldr r3, [r3, #0]
80027cc: f003 0302 and.w r3, r3, #2
80027d0: 2b00 cmp r3, #0
80027d2: d1f0 bne.n 80027b6 <HAL_RCC_OscConfig+0x1da>
80027d4: e000 b.n 80027d8 <HAL_RCC_OscConfig+0x1fc>
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
80027d6: bf00 nop
}
}
}
}
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80027d8: 687b ldr r3, [r7, #4]
80027da: 681b ldr r3, [r3, #0]
80027dc: f003 0301 and.w r3, r3, #1
80027e0: 2b00 cmp r3, #0
80027e2: d074 beq.n 80028ce <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
80027e4: 69bb ldr r3, [r7, #24]
80027e6: 2b08 cmp r3, #8
80027e8: d005 beq.n 80027f6 <HAL_RCC_OscConfig+0x21a>
80027ea: 69bb ldr r3, [r7, #24]
80027ec: 2b0c cmp r3, #12
80027ee: d10e bne.n 800280e <HAL_RCC_OscConfig+0x232>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
80027f0: 697b ldr r3, [r7, #20]
80027f2: 2b03 cmp r3, #3
80027f4: d10b bne.n 800280e <HAL_RCC_OscConfig+0x232>
{
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80027f6: 4b15 ldr r3, [pc, #84] @ (800284c <HAL_RCC_OscConfig+0x270>)
80027f8: 681b ldr r3, [r3, #0]
80027fa: f403 3300 and.w r3, r3, #131072 @ 0x20000
80027fe: 2b00 cmp r3, #0
8002800: d064 beq.n 80028cc <HAL_RCC_OscConfig+0x2f0>
8002802: 687b ldr r3, [r7, #4]
8002804: 685b ldr r3, [r3, #4]
8002806: 2b00 cmp r3, #0
8002808: d160 bne.n 80028cc <HAL_RCC_OscConfig+0x2f0>
{
return HAL_ERROR;
800280a: 2301 movs r3, #1
800280c: e2ba b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800280e: 687b ldr r3, [r7, #4]
8002810: 685b ldr r3, [r3, #4]
8002812: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002816: d106 bne.n 8002826 <HAL_RCC_OscConfig+0x24a>
8002818: 4b0c ldr r3, [pc, #48] @ (800284c <HAL_RCC_OscConfig+0x270>)
800281a: 681b ldr r3, [r3, #0]
800281c: 4a0b ldr r2, [pc, #44] @ (800284c <HAL_RCC_OscConfig+0x270>)
800281e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002822: 6013 str r3, [r2, #0]
8002824: e026 b.n 8002874 <HAL_RCC_OscConfig+0x298>
8002826: 687b ldr r3, [r7, #4]
8002828: 685b ldr r3, [r3, #4]
800282a: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
800282e: d115 bne.n 800285c <HAL_RCC_OscConfig+0x280>
8002830: 4b06 ldr r3, [pc, #24] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002832: 681b ldr r3, [r3, #0]
8002834: 4a05 ldr r2, [pc, #20] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002836: f443 2380 orr.w r3, r3, #262144 @ 0x40000
800283a: 6013 str r3, [r2, #0]
800283c: 4b03 ldr r3, [pc, #12] @ (800284c <HAL_RCC_OscConfig+0x270>)
800283e: 681b ldr r3, [r3, #0]
8002840: 4a02 ldr r2, [pc, #8] @ (800284c <HAL_RCC_OscConfig+0x270>)
8002842: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002846: 6013 str r3, [r2, #0]
8002848: e014 b.n 8002874 <HAL_RCC_OscConfig+0x298>
800284a: bf00 nop
800284c: 40021000 .word 0x40021000
8002850: 08004cc8 .word 0x08004cc8
8002854: 20000004 .word 0x20000004
8002858: 20000008 .word 0x20000008
800285c: 4ba0 ldr r3, [pc, #640] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
800285e: 681b ldr r3, [r3, #0]
8002860: 4a9f ldr r2, [pc, #636] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002862: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002866: 6013 str r3, [r2, #0]
8002868: 4b9d ldr r3, [pc, #628] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
800286a: 681b ldr r3, [r3, #0]
800286c: 4a9c ldr r2, [pc, #624] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
800286e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8002872: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8002874: 687b ldr r3, [r7, #4]
8002876: 685b ldr r3, [r3, #4]
8002878: 2b00 cmp r3, #0
800287a: d013 beq.n 80028a4 <HAL_RCC_OscConfig+0x2c8>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800287c: f7fe febe bl 80015fc <HAL_GetTick>
8002880: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8002882: e008 b.n 8002896 <HAL_RCC_OscConfig+0x2ba>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002884: f7fe feba bl 80015fc <HAL_GetTick>
8002888: 4602 mov r2, r0
800288a: 693b ldr r3, [r7, #16]
800288c: 1ad3 subs r3, r2, r3
800288e: 2b64 cmp r3, #100 @ 0x64
8002890: d901 bls.n 8002896 <HAL_RCC_OscConfig+0x2ba>
{
return HAL_TIMEOUT;
8002892: 2303 movs r3, #3
8002894: e276 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8002896: 4b92 ldr r3, [pc, #584] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002898: 681b ldr r3, [r3, #0]
800289a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800289e: 2b00 cmp r3, #0
80028a0: d0f0 beq.n 8002884 <HAL_RCC_OscConfig+0x2a8>
80028a2: e014 b.n 80028ce <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80028a4: f7fe feaa bl 80015fc <HAL_GetTick>
80028a8: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80028aa: e008 b.n 80028be <HAL_RCC_OscConfig+0x2e2>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80028ac: f7fe fea6 bl 80015fc <HAL_GetTick>
80028b0: 4602 mov r2, r0
80028b2: 693b ldr r3, [r7, #16]
80028b4: 1ad3 subs r3, r2, r3
80028b6: 2b64 cmp r3, #100 @ 0x64
80028b8: d901 bls.n 80028be <HAL_RCC_OscConfig+0x2e2>
{
return HAL_TIMEOUT;
80028ba: 2303 movs r3, #3
80028bc: e262 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80028be: 4b88 ldr r3, [pc, #544] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
80028c0: 681b ldr r3, [r3, #0]
80028c2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80028c6: 2b00 cmp r3, #0
80028c8: d1f0 bne.n 80028ac <HAL_RCC_OscConfig+0x2d0>
80028ca: e000 b.n 80028ce <HAL_RCC_OscConfig+0x2f2>
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80028cc: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80028ce: 687b ldr r3, [r7, #4]
80028d0: 681b ldr r3, [r3, #0]
80028d2: f003 0302 and.w r3, r3, #2
80028d6: 2b00 cmp r3, #0
80028d8: d060 beq.n 800299c <HAL_RCC_OscConfig+0x3c0>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
80028da: 69bb ldr r3, [r7, #24]
80028dc: 2b04 cmp r3, #4
80028de: d005 beq.n 80028ec <HAL_RCC_OscConfig+0x310>
80028e0: 69bb ldr r3, [r7, #24]
80028e2: 2b0c cmp r3, #12
80028e4: d119 bne.n 800291a <HAL_RCC_OscConfig+0x33e>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
80028e6: 697b ldr r3, [r7, #20]
80028e8: 2b02 cmp r3, #2
80028ea: d116 bne.n 800291a <HAL_RCC_OscConfig+0x33e>
{
/* When HSI is used as system clock it will not be disabled */
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80028ec: 4b7c ldr r3, [pc, #496] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
80028ee: 681b ldr r3, [r3, #0]
80028f0: f403 6380 and.w r3, r3, #1024 @ 0x400
80028f4: 2b00 cmp r3, #0
80028f6: d005 beq.n 8002904 <HAL_RCC_OscConfig+0x328>
80028f8: 687b ldr r3, [r7, #4]
80028fa: 68db ldr r3, [r3, #12]
80028fc: 2b00 cmp r3, #0
80028fe: d101 bne.n 8002904 <HAL_RCC_OscConfig+0x328>
{
return HAL_ERROR;
8002900: 2301 movs r3, #1
8002902: e23f b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002904: 4b76 ldr r3, [pc, #472] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002906: 685b ldr r3, [r3, #4]
8002908: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
800290c: 687b ldr r3, [r7, #4]
800290e: 691b ldr r3, [r3, #16]
8002910: 061b lsls r3, r3, #24
8002912: 4973 ldr r1, [pc, #460] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002914: 4313 orrs r3, r2
8002916: 604b str r3, [r1, #4]
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8002918: e040 b.n 800299c <HAL_RCC_OscConfig+0x3c0>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800291a: 687b ldr r3, [r7, #4]
800291c: 68db ldr r3, [r3, #12]
800291e: 2b00 cmp r3, #0
8002920: d023 beq.n 800296a <HAL_RCC_OscConfig+0x38e>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002922: 4b6f ldr r3, [pc, #444] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002924: 681b ldr r3, [r3, #0]
8002926: 4a6e ldr r2, [pc, #440] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002928: f443 7380 orr.w r3, r3, #256 @ 0x100
800292c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800292e: f7fe fe65 bl 80015fc <HAL_GetTick>
8002932: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8002934: e008 b.n 8002948 <HAL_RCC_OscConfig+0x36c>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8002936: f7fe fe61 bl 80015fc <HAL_GetTick>
800293a: 4602 mov r2, r0
800293c: 693b ldr r3, [r7, #16]
800293e: 1ad3 subs r3, r2, r3
8002940: 2b02 cmp r3, #2
8002942: d901 bls.n 8002948 <HAL_RCC_OscConfig+0x36c>
{
return HAL_TIMEOUT;
8002944: 2303 movs r3, #3
8002946: e21d b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8002948: 4b65 ldr r3, [pc, #404] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
800294a: 681b ldr r3, [r3, #0]
800294c: f403 6380 and.w r3, r3, #1024 @ 0x400
8002950: 2b00 cmp r3, #0
8002952: d0f0 beq.n 8002936 <HAL_RCC_OscConfig+0x35a>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002954: 4b62 ldr r3, [pc, #392] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002956: 685b ldr r3, [r3, #4]
8002958: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
800295c: 687b ldr r3, [r7, #4]
800295e: 691b ldr r3, [r3, #16]
8002960: 061b lsls r3, r3, #24
8002962: 495f ldr r1, [pc, #380] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002964: 4313 orrs r3, r2
8002966: 604b str r3, [r1, #4]
8002968: e018 b.n 800299c <HAL_RCC_OscConfig+0x3c0>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800296a: 4b5d ldr r3, [pc, #372] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
800296c: 681b ldr r3, [r3, #0]
800296e: 4a5c ldr r2, [pc, #368] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002970: f423 7380 bic.w r3, r3, #256 @ 0x100
8002974: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002976: f7fe fe41 bl 80015fc <HAL_GetTick>
800297a: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
800297c: e008 b.n 8002990 <HAL_RCC_OscConfig+0x3b4>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800297e: f7fe fe3d bl 80015fc <HAL_GetTick>
8002982: 4602 mov r2, r0
8002984: 693b ldr r3, [r7, #16]
8002986: 1ad3 subs r3, r2, r3
8002988: 2b02 cmp r3, #2
800298a: d901 bls.n 8002990 <HAL_RCC_OscConfig+0x3b4>
{
return HAL_TIMEOUT;
800298c: 2303 movs r3, #3
800298e: e1f9 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8002990: 4b53 ldr r3, [pc, #332] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002992: 681b ldr r3, [r3, #0]
8002994: f403 6380 and.w r3, r3, #1024 @ 0x400
8002998: 2b00 cmp r3, #0
800299a: d1f0 bne.n 800297e <HAL_RCC_OscConfig+0x3a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800299c: 687b ldr r3, [r7, #4]
800299e: 681b ldr r3, [r3, #0]
80029a0: f003 0308 and.w r3, r3, #8
80029a4: 2b00 cmp r3, #0
80029a6: d03c beq.n 8002a22 <HAL_RCC_OscConfig+0x446>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80029a8: 687b ldr r3, [r7, #4]
80029aa: 695b ldr r3, [r3, #20]
80029ac: 2b00 cmp r3, #0
80029ae: d01c beq.n 80029ea <HAL_RCC_OscConfig+0x40e>
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
}
#endif /* RCC_CSR_LSIPREDIV */
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80029b0: 4b4b ldr r3, [pc, #300] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
80029b2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80029b6: 4a4a ldr r2, [pc, #296] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
80029b8: f043 0301 orr.w r3, r3, #1
80029bc: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
80029c0: f7fe fe1c bl 80015fc <HAL_GetTick>
80029c4: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80029c6: e008 b.n 80029da <HAL_RCC_OscConfig+0x3fe>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80029c8: f7fe fe18 bl 80015fc <HAL_GetTick>
80029cc: 4602 mov r2, r0
80029ce: 693b ldr r3, [r7, #16]
80029d0: 1ad3 subs r3, r2, r3
80029d2: 2b02 cmp r3, #2
80029d4: d901 bls.n 80029da <HAL_RCC_OscConfig+0x3fe>
{
return HAL_TIMEOUT;
80029d6: 2303 movs r3, #3
80029d8: e1d4 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80029da: 4b41 ldr r3, [pc, #260] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
80029dc: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80029e0: f003 0302 and.w r3, r3, #2
80029e4: 2b00 cmp r3, #0
80029e6: d0ef beq.n 80029c8 <HAL_RCC_OscConfig+0x3ec>
80029e8: e01b b.n 8002a22 <HAL_RCC_OscConfig+0x446>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80029ea: 4b3d ldr r3, [pc, #244] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
80029ec: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80029f0: 4a3b ldr r2, [pc, #236] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
80029f2: f023 0301 bic.w r3, r3, #1
80029f6: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
80029fa: f7fe fdff bl 80015fc <HAL_GetTick>
80029fe: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8002a00: e008 b.n 8002a14 <HAL_RCC_OscConfig+0x438>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002a02: f7fe fdfb bl 80015fc <HAL_GetTick>
8002a06: 4602 mov r2, r0
8002a08: 693b ldr r3, [r7, #16]
8002a0a: 1ad3 subs r3, r2, r3
8002a0c: 2b02 cmp r3, #2
8002a0e: d901 bls.n 8002a14 <HAL_RCC_OscConfig+0x438>
{
return HAL_TIMEOUT;
8002a10: 2303 movs r3, #3
8002a12: e1b7 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8002a14: 4b32 ldr r3, [pc, #200] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002a16: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8002a1a: f003 0302 and.w r3, r3, #2
8002a1e: 2b00 cmp r3, #0
8002a20: d1ef bne.n 8002a02 <HAL_RCC_OscConfig+0x426>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002a22: 687b ldr r3, [r7, #4]
8002a24: 681b ldr r3, [r3, #0]
8002a26: f003 0304 and.w r3, r3, #4
8002a2a: 2b00 cmp r3, #0
8002a2c: f000 80a6 beq.w 8002b7c <HAL_RCC_OscConfig+0x5a0>
{
FlagStatus pwrclkchanged = RESET;
8002a30: 2300 movs r3, #0
8002a32: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
8002a34: 4b2a ldr r3, [pc, #168] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002a36: 6d9b ldr r3, [r3, #88] @ 0x58
8002a38: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002a3c: 2b00 cmp r3, #0
8002a3e: d10d bne.n 8002a5c <HAL_RCC_OscConfig+0x480>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002a40: 4b27 ldr r3, [pc, #156] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002a42: 6d9b ldr r3, [r3, #88] @ 0x58
8002a44: 4a26 ldr r2, [pc, #152] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002a46: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002a4a: 6593 str r3, [r2, #88] @ 0x58
8002a4c: 4b24 ldr r3, [pc, #144] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002a4e: 6d9b ldr r3, [r3, #88] @ 0x58
8002a50: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002a54: 60bb str r3, [r7, #8]
8002a56: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002a58: 2301 movs r3, #1
8002a5a: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8002a5c: 4b21 ldr r3, [pc, #132] @ (8002ae4 <HAL_RCC_OscConfig+0x508>)
8002a5e: 681b ldr r3, [r3, #0]
8002a60: f403 7380 and.w r3, r3, #256 @ 0x100
8002a64: 2b00 cmp r3, #0
8002a66: d118 bne.n 8002a9a <HAL_RCC_OscConfig+0x4be>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8002a68: 4b1e ldr r3, [pc, #120] @ (8002ae4 <HAL_RCC_OscConfig+0x508>)
8002a6a: 681b ldr r3, [r3, #0]
8002a6c: 4a1d ldr r2, [pc, #116] @ (8002ae4 <HAL_RCC_OscConfig+0x508>)
8002a6e: f443 7380 orr.w r3, r3, #256 @ 0x100
8002a72: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002a74: f7fe fdc2 bl 80015fc <HAL_GetTick>
8002a78: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8002a7a: e008 b.n 8002a8e <HAL_RCC_OscConfig+0x4b2>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002a7c: f7fe fdbe bl 80015fc <HAL_GetTick>
8002a80: 4602 mov r2, r0
8002a82: 693b ldr r3, [r7, #16]
8002a84: 1ad3 subs r3, r2, r3
8002a86: 2b02 cmp r3, #2
8002a88: d901 bls.n 8002a8e <HAL_RCC_OscConfig+0x4b2>
{
return HAL_TIMEOUT;
8002a8a: 2303 movs r3, #3
8002a8c: e17a b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8002a8e: 4b15 ldr r3, [pc, #84] @ (8002ae4 <HAL_RCC_OscConfig+0x508>)
8002a90: 681b ldr r3, [r3, #0]
8002a92: f403 7380 and.w r3, r3, #256 @ 0x100
8002a96: 2b00 cmp r3, #0
8002a98: d0f0 beq.n 8002a7c <HAL_RCC_OscConfig+0x4a0>
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
#else
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002a9a: 687b ldr r3, [r7, #4]
8002a9c: 689b ldr r3, [r3, #8]
8002a9e: 2b01 cmp r3, #1
8002aa0: d108 bne.n 8002ab4 <HAL_RCC_OscConfig+0x4d8>
8002aa2: 4b0f ldr r3, [pc, #60] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002aa4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002aa8: 4a0d ldr r2, [pc, #52] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002aaa: f043 0301 orr.w r3, r3, #1
8002aae: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8002ab2: e029 b.n 8002b08 <HAL_RCC_OscConfig+0x52c>
8002ab4: 687b ldr r3, [r7, #4]
8002ab6: 689b ldr r3, [r3, #8]
8002ab8: 2b05 cmp r3, #5
8002aba: d115 bne.n 8002ae8 <HAL_RCC_OscConfig+0x50c>
8002abc: 4b08 ldr r3, [pc, #32] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002abe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002ac2: 4a07 ldr r2, [pc, #28] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002ac4: f043 0304 orr.w r3, r3, #4
8002ac8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8002acc: 4b04 ldr r3, [pc, #16] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002ace: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002ad2: 4a03 ldr r2, [pc, #12] @ (8002ae0 <HAL_RCC_OscConfig+0x504>)
8002ad4: f043 0301 orr.w r3, r3, #1
8002ad8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8002adc: e014 b.n 8002b08 <HAL_RCC_OscConfig+0x52c>
8002ade: bf00 nop
8002ae0: 40021000 .word 0x40021000
8002ae4: 40007000 .word 0x40007000
8002ae8: 4b9c ldr r3, [pc, #624] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002aea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002aee: 4a9b ldr r2, [pc, #620] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002af0: f023 0301 bic.w r3, r3, #1
8002af4: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8002af8: 4b98 ldr r3, [pc, #608] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002afa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002afe: 4a97 ldr r2, [pc, #604] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002b00: f023 0304 bic.w r3, r3, #4
8002b04: f8c2 3090 str.w r3, [r2, #144] @ 0x90
#endif /* RCC_BDCR_LSESYSDIS */
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8002b08: 687b ldr r3, [r7, #4]
8002b0a: 689b ldr r3, [r3, #8]
8002b0c: 2b00 cmp r3, #0
8002b0e: d016 beq.n 8002b3e <HAL_RCC_OscConfig+0x562>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002b10: f7fe fd74 bl 80015fc <HAL_GetTick>
8002b14: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8002b16: e00a b.n 8002b2e <HAL_RCC_OscConfig+0x552>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002b18: f7fe fd70 bl 80015fc <HAL_GetTick>
8002b1c: 4602 mov r2, r0
8002b1e: 693b ldr r3, [r7, #16]
8002b20: 1ad3 subs r3, r2, r3
8002b22: f241 3288 movw r2, #5000 @ 0x1388
8002b26: 4293 cmp r3, r2
8002b28: d901 bls.n 8002b2e <HAL_RCC_OscConfig+0x552>
{
return HAL_TIMEOUT;
8002b2a: 2303 movs r3, #3
8002b2c: e12a b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8002b2e: 4b8b ldr r3, [pc, #556] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002b30: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002b34: f003 0302 and.w r3, r3, #2
8002b38: 2b00 cmp r3, #0
8002b3a: d0ed beq.n 8002b18 <HAL_RCC_OscConfig+0x53c>
8002b3c: e015 b.n 8002b6a <HAL_RCC_OscConfig+0x58e>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002b3e: f7fe fd5d bl 80015fc <HAL_GetTick>
8002b42: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8002b44: e00a b.n 8002b5c <HAL_RCC_OscConfig+0x580>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002b46: f7fe fd59 bl 80015fc <HAL_GetTick>
8002b4a: 4602 mov r2, r0
8002b4c: 693b ldr r3, [r7, #16]
8002b4e: 1ad3 subs r3, r2, r3
8002b50: f241 3288 movw r2, #5000 @ 0x1388
8002b54: 4293 cmp r3, r2
8002b56: d901 bls.n 8002b5c <HAL_RCC_OscConfig+0x580>
{
return HAL_TIMEOUT;
8002b58: 2303 movs r3, #3
8002b5a: e113 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8002b5c: 4b7f ldr r3, [pc, #508] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002b5e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002b62: f003 0302 and.w r3, r3, #2
8002b66: 2b00 cmp r3, #0
8002b68: d1ed bne.n 8002b46 <HAL_RCC_OscConfig+0x56a>
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8002b6a: 7ffb ldrb r3, [r7, #31]
8002b6c: 2b01 cmp r3, #1
8002b6e: d105 bne.n 8002b7c <HAL_RCC_OscConfig+0x5a0>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002b70: 4b7a ldr r3, [pc, #488] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002b72: 6d9b ldr r3, [r3, #88] @ 0x58
8002b74: 4a79 ldr r2, [pc, #484] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002b76: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002b7a: 6593 str r3, [r2, #88] @ 0x58
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8002b7c: 687b ldr r3, [r7, #4]
8002b7e: 6a9b ldr r3, [r3, #40] @ 0x28
8002b80: 2b00 cmp r3, #0
8002b82: f000 80fe beq.w 8002d82 <HAL_RCC_OscConfig+0x7a6>
{
/* PLL On ? */
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
8002b86: 687b ldr r3, [r7, #4]
8002b88: 6a9b ldr r3, [r3, #40] @ 0x28
8002b8a: 2b02 cmp r3, #2
8002b8c: f040 80d0 bne.w 8002d30 <HAL_RCC_OscConfig+0x754>
#endif /* RCC_PLLP_SUPPORT */
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Do nothing if PLL configuration is the unchanged */
pll_config = RCC->PLLCFGR;
8002b90: 4b72 ldr r3, [pc, #456] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002b92: 68db ldr r3, [r3, #12]
8002b94: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002b96: 697b ldr r3, [r7, #20]
8002b98: f003 0203 and.w r2, r3, #3
8002b9c: 687b ldr r3, [r7, #4]
8002b9e: 6adb ldr r3, [r3, #44] @ 0x2c
8002ba0: 429a cmp r2, r3
8002ba2: d130 bne.n 8002c06 <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8002ba4: 697b ldr r3, [r7, #20]
8002ba6: f003 0270 and.w r2, r3, #112 @ 0x70
8002baa: 687b ldr r3, [r7, #4]
8002bac: 6b1b ldr r3, [r3, #48] @ 0x30
8002bae: 3b01 subs r3, #1
8002bb0: 011b lsls r3, r3, #4
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002bb2: 429a cmp r2, r3
8002bb4: d127 bne.n 8002c06 <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8002bb6: 697b ldr r3, [r7, #20]
8002bb8: f403 42fe and.w r2, r3, #32512 @ 0x7f00
8002bbc: 687b ldr r3, [r7, #4]
8002bbe: 6b5b ldr r3, [r3, #52] @ 0x34
8002bc0: 021b lsls r3, r3, #8
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8002bc2: 429a cmp r2, r3
8002bc4: d11f bne.n 8002c06 <HAL_RCC_OscConfig+0x62a>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
#else
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
8002bc6: 697b ldr r3, [r7, #20]
8002bc8: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002bcc: 687a ldr r2, [r7, #4]
8002bce: 6b92 ldr r2, [r2, #56] @ 0x38
8002bd0: 2a07 cmp r2, #7
8002bd2: bf14 ite ne
8002bd4: 2201 movne r2, #1
8002bd6: 2200 moveq r2, #0
8002bd8: b2d2 uxtb r2, r2
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8002bda: 4293 cmp r3, r2
8002bdc: d113 bne.n 8002c06 <HAL_RCC_OscConfig+0x62a>
#endif
#endif
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8002bde: 697b ldr r3, [r7, #20]
8002be0: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
8002be4: 687b ldr r3, [r7, #4]
8002be6: 6bdb ldr r3, [r3, #60] @ 0x3c
8002be8: 085b lsrs r3, r3, #1
8002bea: 3b01 subs r3, #1
8002bec: 055b lsls r3, r3, #21
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
8002bee: 429a cmp r2, r3
8002bf0: d109 bne.n 8002c06 <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
8002bf2: 697b ldr r3, [r7, #20]
8002bf4: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
8002bf8: 687b ldr r3, [r7, #4]
8002bfa: 6c1b ldr r3, [r3, #64] @ 0x40
8002bfc: 085b lsrs r3, r3, #1
8002bfe: 3b01 subs r3, #1
8002c00: 065b lsls r3, r3, #25
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8002c02: 429a cmp r2, r3
8002c04: d06e beq.n 8002ce4 <HAL_RCC_OscConfig+0x708>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
8002c06: 69bb ldr r3, [r7, #24]
8002c08: 2b0c cmp r3, #12
8002c0a: d069 beq.n 8002ce0 <HAL_RCC_OscConfig+0x704>
{
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
/* Check if main PLL can be updated */
/* Not possible if the source is shared by other enabled PLLSAIx */
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
8002c0c: 4b53 ldr r3, [pc, #332] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002c0e: 681b ldr r3, [r3, #0]
8002c10: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8002c14: 2b00 cmp r3, #0
8002c16: d105 bne.n 8002c24 <HAL_RCC_OscConfig+0x648>
#if defined(RCC_PLLSAI2_SUPPORT)
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
8002c18: 4b50 ldr r3, [pc, #320] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002c1a: 681b ldr r3, [r3, #0]
8002c1c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002c20: 2b00 cmp r3, #0
8002c22: d001 beq.n 8002c28 <HAL_RCC_OscConfig+0x64c>
#endif
)
{
return HAL_ERROR;
8002c24: 2301 movs r3, #1
8002c26: e0ad b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002c28: 4b4c ldr r3, [pc, #304] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002c2a: 681b ldr r3, [r3, #0]
8002c2c: 4a4b ldr r2, [pc, #300] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002c2e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8002c32: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002c34: f7fe fce2 bl 80015fc <HAL_GetTick>
8002c38: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002c3a: e008 b.n 8002c4e <HAL_RCC_OscConfig+0x672>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002c3c: f7fe fcde bl 80015fc <HAL_GetTick>
8002c40: 4602 mov r2, r0
8002c42: 693b ldr r3, [r7, #16]
8002c44: 1ad3 subs r3, r2, r3
8002c46: 2b02 cmp r3, #2
8002c48: d901 bls.n 8002c4e <HAL_RCC_OscConfig+0x672>
{
return HAL_TIMEOUT;
8002c4a: 2303 movs r3, #3
8002c4c: e09a b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002c4e: 4b43 ldr r3, [pc, #268] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002c50: 681b ldr r3, [r3, #0]
8002c52: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002c56: 2b00 cmp r3, #0
8002c58: d1f0 bne.n 8002c3c <HAL_RCC_OscConfig+0x660>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8002c5a: 4b40 ldr r3, [pc, #256] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002c5c: 68da ldr r2, [r3, #12]
8002c5e: 4b40 ldr r3, [pc, #256] @ (8002d60 <HAL_RCC_OscConfig+0x784>)
8002c60: 4013 ands r3, r2
8002c62: 687a ldr r2, [r7, #4]
8002c64: 6ad1 ldr r1, [r2, #44] @ 0x2c
8002c66: 687a ldr r2, [r7, #4]
8002c68: 6b12 ldr r2, [r2, #48] @ 0x30
8002c6a: 3a01 subs r2, #1
8002c6c: 0112 lsls r2, r2, #4
8002c6e: 4311 orrs r1, r2
8002c70: 687a ldr r2, [r7, #4]
8002c72: 6b52 ldr r2, [r2, #52] @ 0x34
8002c74: 0212 lsls r2, r2, #8
8002c76: 4311 orrs r1, r2
8002c78: 687a ldr r2, [r7, #4]
8002c7a: 6bd2 ldr r2, [r2, #60] @ 0x3c
8002c7c: 0852 lsrs r2, r2, #1
8002c7e: 3a01 subs r2, #1
8002c80: 0552 lsls r2, r2, #21
8002c82: 4311 orrs r1, r2
8002c84: 687a ldr r2, [r7, #4]
8002c86: 6c12 ldr r2, [r2, #64] @ 0x40
8002c88: 0852 lsrs r2, r2, #1
8002c8a: 3a01 subs r2, #1
8002c8c: 0652 lsls r2, r2, #25
8002c8e: 4311 orrs r1, r2
8002c90: 687a ldr r2, [r7, #4]
8002c92: 6b92 ldr r2, [r2, #56] @ 0x38
8002c94: 0912 lsrs r2, r2, #4
8002c96: 0452 lsls r2, r2, #17
8002c98: 430a orrs r2, r1
8002c9a: 4930 ldr r1, [pc, #192] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002c9c: 4313 orrs r3, r2
8002c9e: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002ca0: 4b2e ldr r3, [pc, #184] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002ca2: 681b ldr r3, [r3, #0]
8002ca4: 4a2d ldr r2, [pc, #180] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002ca6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002caa: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8002cac: 4b2b ldr r3, [pc, #172] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002cae: 68db ldr r3, [r3, #12]
8002cb0: 4a2a ldr r2, [pc, #168] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002cb2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002cb6: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002cb8: f7fe fca0 bl 80015fc <HAL_GetTick>
8002cbc: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002cbe: e008 b.n 8002cd2 <HAL_RCC_OscConfig+0x6f6>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002cc0: f7fe fc9c bl 80015fc <HAL_GetTick>
8002cc4: 4602 mov r2, r0
8002cc6: 693b ldr r3, [r7, #16]
8002cc8: 1ad3 subs r3, r2, r3
8002cca: 2b02 cmp r3, #2
8002ccc: d901 bls.n 8002cd2 <HAL_RCC_OscConfig+0x6f6>
{
return HAL_TIMEOUT;
8002cce: 2303 movs r3, #3
8002cd0: e058 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002cd2: 4b22 ldr r3, [pc, #136] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002cd4: 681b ldr r3, [r3, #0]
8002cd6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002cda: 2b00 cmp r3, #0
8002cdc: d0f0 beq.n 8002cc0 <HAL_RCC_OscConfig+0x6e4>
if(sysclk_source != RCC_CFGR_SWS_PLL)
8002cde: e050 b.n 8002d82 <HAL_RCC_OscConfig+0x7a6>
}
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
8002ce0: 2301 movs r3, #1
8002ce2: e04f b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
else
{
/* PLL configuration is unchanged */
/* Re-enable PLL if it was disabled (ie. low power mode) */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002ce4: 4b1d ldr r3, [pc, #116] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002ce6: 681b ldr r3, [r3, #0]
8002ce8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002cec: 2b00 cmp r3, #0
8002cee: d148 bne.n 8002d82 <HAL_RCC_OscConfig+0x7a6>
{
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002cf0: 4b1a ldr r3, [pc, #104] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002cf2: 681b ldr r3, [r3, #0]
8002cf4: 4a19 ldr r2, [pc, #100] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002cf6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002cfa: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8002cfc: 4b17 ldr r3, [pc, #92] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002cfe: 68db ldr r3, [r3, #12]
8002d00: 4a16 ldr r2, [pc, #88] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002d02: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002d06: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002d08: f7fe fc78 bl 80015fc <HAL_GetTick>
8002d0c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002d0e: e008 b.n 8002d22 <HAL_RCC_OscConfig+0x746>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002d10: f7fe fc74 bl 80015fc <HAL_GetTick>
8002d14: 4602 mov r2, r0
8002d16: 693b ldr r3, [r7, #16]
8002d18: 1ad3 subs r3, r2, r3
8002d1a: 2b02 cmp r3, #2
8002d1c: d901 bls.n 8002d22 <HAL_RCC_OscConfig+0x746>
{
return HAL_TIMEOUT;
8002d1e: 2303 movs r3, #3
8002d20: e030 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002d22: 4b0e ldr r3, [pc, #56] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002d24: 681b ldr r3, [r3, #0]
8002d26: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002d2a: 2b00 cmp r3, #0
8002d2c: d0f0 beq.n 8002d10 <HAL_RCC_OscConfig+0x734>
8002d2e: e028 b.n 8002d82 <HAL_RCC_OscConfig+0x7a6>
}
}
else
{
/* Check that PLL is not used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
8002d30: 69bb ldr r3, [r7, #24]
8002d32: 2b0c cmp r3, #12
8002d34: d023 beq.n 8002d7e <HAL_RCC_OscConfig+0x7a2>
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002d36: 4b09 ldr r3, [pc, #36] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002d38: 681b ldr r3, [r3, #0]
8002d3a: 4a08 ldr r2, [pc, #32] @ (8002d5c <HAL_RCC_OscConfig+0x780>)
8002d3c: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8002d40: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002d42: f7fe fc5b bl 80015fc <HAL_GetTick>
8002d46: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002d48: e00c b.n 8002d64 <HAL_RCC_OscConfig+0x788>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002d4a: f7fe fc57 bl 80015fc <HAL_GetTick>
8002d4e: 4602 mov r2, r0
8002d50: 693b ldr r3, [r7, #16]
8002d52: 1ad3 subs r3, r2, r3
8002d54: 2b02 cmp r3, #2
8002d56: d905 bls.n 8002d64 <HAL_RCC_OscConfig+0x788>
{
return HAL_TIMEOUT;
8002d58: 2303 movs r3, #3
8002d5a: e013 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
8002d5c: 40021000 .word 0x40021000
8002d60: f99d808c .word 0xf99d808c
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002d64: 4b09 ldr r3, [pc, #36] @ (8002d8c <HAL_RCC_OscConfig+0x7b0>)
8002d66: 681b ldr r3, [r3, #0]
8002d68: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002d6c: 2b00 cmp r3, #0
8002d6e: d1ec bne.n 8002d4a <HAL_RCC_OscConfig+0x76e>
}
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
8002d70: 4b06 ldr r3, [pc, #24] @ (8002d8c <HAL_RCC_OscConfig+0x7b0>)
8002d72: 68da ldr r2, [r3, #12]
8002d74: 4905 ldr r1, [pc, #20] @ (8002d8c <HAL_RCC_OscConfig+0x7b0>)
8002d76: 4b06 ldr r3, [pc, #24] @ (8002d90 <HAL_RCC_OscConfig+0x7b4>)
8002d78: 4013 ands r3, r2
8002d7a: 60cb str r3, [r1, #12]
8002d7c: e001 b.n 8002d82 <HAL_RCC_OscConfig+0x7a6>
#endif /* RCC_PLLSAI2_SUPPORT */
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
8002d7e: 2301 movs r3, #1
8002d80: e000 b.n 8002d84 <HAL_RCC_OscConfig+0x7a8>
}
}
}
return HAL_OK;
8002d82: 2300 movs r3, #0
}
8002d84: 4618 mov r0, r3
8002d86: 3720 adds r7, #32
8002d88: 46bd mov sp, r7
8002d8a: bd80 pop {r7, pc}
8002d8c: 40021000 .word 0x40021000
8002d90: feeefffc .word 0xfeeefffc
08002d94 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002d94: b580 push {r7, lr}
8002d96: b084 sub sp, #16
8002d98: af00 add r7, sp, #0
8002d9a: 6078 str r0, [r7, #4]
8002d9c: 6039 str r1, [r7, #0]
uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
HAL_StatusTypeDef status;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002d9e: 687b ldr r3, [r7, #4]
8002da0: 2b00 cmp r3, #0
8002da2: d101 bne.n 8002da8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8002da4: 2301 movs r3, #1
8002da6: e0e7 b.n 8002f78 <HAL_RCC_ClockConfig+0x1e4>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8002da8: 4b75 ldr r3, [pc, #468] @ (8002f80 <HAL_RCC_ClockConfig+0x1ec>)
8002daa: 681b ldr r3, [r3, #0]
8002dac: f003 0307 and.w r3, r3, #7
8002db0: 683a ldr r2, [r7, #0]
8002db2: 429a cmp r2, r3
8002db4: d910 bls.n 8002dd8 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002db6: 4b72 ldr r3, [pc, #456] @ (8002f80 <HAL_RCC_ClockConfig+0x1ec>)
8002db8: 681b ldr r3, [r3, #0]
8002dba: f023 0207 bic.w r2, r3, #7
8002dbe: 4970 ldr r1, [pc, #448] @ (8002f80 <HAL_RCC_ClockConfig+0x1ec>)
8002dc0: 683b ldr r3, [r7, #0]
8002dc2: 4313 orrs r3, r2
8002dc4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002dc6: 4b6e ldr r3, [pc, #440] @ (8002f80 <HAL_RCC_ClockConfig+0x1ec>)
8002dc8: 681b ldr r3, [r3, #0]
8002dca: f003 0307 and.w r3, r3, #7
8002dce: 683a ldr r2, [r7, #0]
8002dd0: 429a cmp r2, r3
8002dd2: d001 beq.n 8002dd8 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8002dd4: 2301 movs r3, #1
8002dd6: e0cf b.n 8002f78 <HAL_RCC_ClockConfig+0x1e4>
}
}
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002dd8: 687b ldr r3, [r7, #4]
8002dda: 681b ldr r3, [r3, #0]
8002ddc: f003 0302 and.w r3, r3, #2
8002de0: 2b00 cmp r3, #0
8002de2: d010 beq.n 8002e06 <HAL_RCC_ClockConfig+0x72>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
8002de4: 687b ldr r3, [r7, #4]
8002de6: 689a ldr r2, [r3, #8]
8002de8: 4b66 ldr r3, [pc, #408] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002dea: 689b ldr r3, [r3, #8]
8002dec: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002df0: 429a cmp r2, r3
8002df2: d908 bls.n 8002e06 <HAL_RCC_ClockConfig+0x72>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002df4: 4b63 ldr r3, [pc, #396] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002df6: 689b ldr r3, [r3, #8]
8002df8: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002dfc: 687b ldr r3, [r7, #4]
8002dfe: 689b ldr r3, [r3, #8]
8002e00: 4960 ldr r1, [pc, #384] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002e02: 4313 orrs r3, r2
8002e04: 608b str r3, [r1, #8]
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002e06: 687b ldr r3, [r7, #4]
8002e08: 681b ldr r3, [r3, #0]
8002e0a: f003 0301 and.w r3, r3, #1
8002e0e: 2b00 cmp r3, #0
8002e10: d04c beq.n 8002eac <HAL_RCC_ClockConfig+0x118>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8002e12: 687b ldr r3, [r7, #4]
8002e14: 685b ldr r3, [r3, #4]
8002e16: 2b03 cmp r3, #3
8002e18: d107 bne.n 8002e2a <HAL_RCC_ClockConfig+0x96>
{
/* Check the PLL ready flag */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002e1a: 4b5a ldr r3, [pc, #360] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002e1c: 681b ldr r3, [r3, #0]
8002e1e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002e22: 2b00 cmp r3, #0
8002e24: d121 bne.n 8002e6a <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
8002e26: 2301 movs r3, #1
8002e28: e0a6 b.n 8002f78 <HAL_RCC_ClockConfig+0x1e4>
#endif
}
else
{
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002e2a: 687b ldr r3, [r7, #4]
8002e2c: 685b ldr r3, [r3, #4]
8002e2e: 2b02 cmp r3, #2
8002e30: d107 bne.n 8002e42 <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8002e32: 4b54 ldr r3, [pc, #336] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002e34: 681b ldr r3, [r3, #0]
8002e36: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002e3a: 2b00 cmp r3, #0
8002e3c: d115 bne.n 8002e6a <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
8002e3e: 2301 movs r3, #1
8002e40: e09a b.n 8002f78 <HAL_RCC_ClockConfig+0x1e4>
}
}
/* MSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
8002e42: 687b ldr r3, [r7, #4]
8002e44: 685b ldr r3, [r3, #4]
8002e46: 2b00 cmp r3, #0
8002e48: d107 bne.n 8002e5a <HAL_RCC_ClockConfig+0xc6>
{
/* Check the MSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8002e4a: 4b4e ldr r3, [pc, #312] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002e4c: 681b ldr r3, [r3, #0]
8002e4e: f003 0302 and.w r3, r3, #2
8002e52: 2b00 cmp r3, #0
8002e54: d109 bne.n 8002e6a <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
8002e56: 2301 movs r3, #1
8002e58: e08e b.n 8002f78 <HAL_RCC_ClockConfig+0x1e4>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8002e5a: 4b4a ldr r3, [pc, #296] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002e5c: 681b ldr r3, [r3, #0]
8002e5e: f403 6380 and.w r3, r3, #1024 @ 0x400
8002e62: 2b00 cmp r3, #0
8002e64: d101 bne.n 8002e6a <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
8002e66: 2301 movs r3, #1
8002e68: e086 b.n 8002f78 <HAL_RCC_ClockConfig+0x1e4>
}
#endif
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8002e6a: 4b46 ldr r3, [pc, #280] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002e6c: 689b ldr r3, [r3, #8]
8002e6e: f023 0203 bic.w r2, r3, #3
8002e72: 687b ldr r3, [r7, #4]
8002e74: 685b ldr r3, [r3, #4]
8002e76: 4943 ldr r1, [pc, #268] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002e78: 4313 orrs r3, r2
8002e7a: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002e7c: f7fe fbbe bl 80015fc <HAL_GetTick>
8002e80: 60f8 str r0, [r7, #12]
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002e82: e00a b.n 8002e9a <HAL_RCC_ClockConfig+0x106>
{
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002e84: f7fe fbba bl 80015fc <HAL_GetTick>
8002e88: 4602 mov r2, r0
8002e8a: 68fb ldr r3, [r7, #12]
8002e8c: 1ad3 subs r3, r2, r3
8002e8e: f241 3288 movw r2, #5000 @ 0x1388
8002e92: 4293 cmp r3, r2
8002e94: d901 bls.n 8002e9a <HAL_RCC_ClockConfig+0x106>
{
return HAL_TIMEOUT;
8002e96: 2303 movs r3, #3
8002e98: e06e b.n 8002f78 <HAL_RCC_ClockConfig+0x1e4>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002e9a: 4b3a ldr r3, [pc, #232] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002e9c: 689b ldr r3, [r3, #8]
8002e9e: f003 020c and.w r2, r3, #12
8002ea2: 687b ldr r3, [r7, #4]
8002ea4: 685b ldr r3, [r3, #4]
8002ea6: 009b lsls r3, r3, #2
8002ea8: 429a cmp r2, r3
8002eaa: d1eb bne.n 8002e84 <HAL_RCC_ClockConfig+0xf0>
}
#endif
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002eac: 687b ldr r3, [r7, #4]
8002eae: 681b ldr r3, [r3, #0]
8002eb0: f003 0302 and.w r3, r3, #2
8002eb4: 2b00 cmp r3, #0
8002eb6: d010 beq.n 8002eda <HAL_RCC_ClockConfig+0x146>
{
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
8002eb8: 687b ldr r3, [r7, #4]
8002eba: 689a ldr r2, [r3, #8]
8002ebc: 4b31 ldr r3, [pc, #196] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002ebe: 689b ldr r3, [r3, #8]
8002ec0: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002ec4: 429a cmp r2, r3
8002ec6: d208 bcs.n 8002eda <HAL_RCC_ClockConfig+0x146>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002ec8: 4b2e ldr r3, [pc, #184] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002eca: 689b ldr r3, [r3, #8]
8002ecc: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002ed0: 687b ldr r3, [r7, #4]
8002ed2: 689b ldr r3, [r3, #8]
8002ed4: 492b ldr r1, [pc, #172] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002ed6: 4313 orrs r3, r2
8002ed8: 608b str r3, [r1, #8]
}
}
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8002eda: 4b29 ldr r3, [pc, #164] @ (8002f80 <HAL_RCC_ClockConfig+0x1ec>)
8002edc: 681b ldr r3, [r3, #0]
8002ede: f003 0307 and.w r3, r3, #7
8002ee2: 683a ldr r2, [r7, #0]
8002ee4: 429a cmp r2, r3
8002ee6: d210 bcs.n 8002f0a <HAL_RCC_ClockConfig+0x176>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002ee8: 4b25 ldr r3, [pc, #148] @ (8002f80 <HAL_RCC_ClockConfig+0x1ec>)
8002eea: 681b ldr r3, [r3, #0]
8002eec: f023 0207 bic.w r2, r3, #7
8002ef0: 4923 ldr r1, [pc, #140] @ (8002f80 <HAL_RCC_ClockConfig+0x1ec>)
8002ef2: 683b ldr r3, [r7, #0]
8002ef4: 4313 orrs r3, r2
8002ef6: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002ef8: 4b21 ldr r3, [pc, #132] @ (8002f80 <HAL_RCC_ClockConfig+0x1ec>)
8002efa: 681b ldr r3, [r3, #0]
8002efc: f003 0307 and.w r3, r3, #7
8002f00: 683a ldr r2, [r7, #0]
8002f02: 429a cmp r2, r3
8002f04: d001 beq.n 8002f0a <HAL_RCC_ClockConfig+0x176>
{
return HAL_ERROR;
8002f06: 2301 movs r3, #1
8002f08: e036 b.n 8002f78 <HAL_RCC_ClockConfig+0x1e4>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002f0a: 687b ldr r3, [r7, #4]
8002f0c: 681b ldr r3, [r3, #0]
8002f0e: f003 0304 and.w r3, r3, #4
8002f12: 2b00 cmp r3, #0
8002f14: d008 beq.n 8002f28 <HAL_RCC_ClockConfig+0x194>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8002f16: 4b1b ldr r3, [pc, #108] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002f18: 689b ldr r3, [r3, #8]
8002f1a: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8002f1e: 687b ldr r3, [r7, #4]
8002f20: 68db ldr r3, [r3, #12]
8002f22: 4918 ldr r1, [pc, #96] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002f24: 4313 orrs r3, r2
8002f26: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002f28: 687b ldr r3, [r7, #4]
8002f2a: 681b ldr r3, [r3, #0]
8002f2c: f003 0308 and.w r3, r3, #8
8002f30: 2b00 cmp r3, #0
8002f32: d009 beq.n 8002f48 <HAL_RCC_ClockConfig+0x1b4>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8002f34: 4b13 ldr r3, [pc, #76] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002f36: 689b ldr r3, [r3, #8]
8002f38: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8002f3c: 687b ldr r3, [r7, #4]
8002f3e: 691b ldr r3, [r3, #16]
8002f40: 00db lsls r3, r3, #3
8002f42: 4910 ldr r1, [pc, #64] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002f44: 4313 orrs r3, r2
8002f46: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8002f48: f000 f824 bl 8002f94 <HAL_RCC_GetSysClockFreq>
8002f4c: 4602 mov r2, r0
8002f4e: 4b0d ldr r3, [pc, #52] @ (8002f84 <HAL_RCC_ClockConfig+0x1f0>)
8002f50: 689b ldr r3, [r3, #8]
8002f52: 091b lsrs r3, r3, #4
8002f54: f003 030f and.w r3, r3, #15
8002f58: 490b ldr r1, [pc, #44] @ (8002f88 <HAL_RCC_ClockConfig+0x1f4>)
8002f5a: 5ccb ldrb r3, [r1, r3]
8002f5c: f003 031f and.w r3, r3, #31
8002f60: fa22 f303 lsr.w r3, r2, r3
8002f64: 4a09 ldr r2, [pc, #36] @ (8002f8c <HAL_RCC_ClockConfig+0x1f8>)
8002f66: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8002f68: 4b09 ldr r3, [pc, #36] @ (8002f90 <HAL_RCC_ClockConfig+0x1fc>)
8002f6a: 681b ldr r3, [r3, #0]
8002f6c: 4618 mov r0, r3
8002f6e: f7fe faf5 bl 800155c <HAL_InitTick>
8002f72: 4603 mov r3, r0
8002f74: 72fb strb r3, [r7, #11]
return status;
8002f76: 7afb ldrb r3, [r7, #11]
}
8002f78: 4618 mov r0, r3
8002f7a: 3710 adds r7, #16
8002f7c: 46bd mov sp, r7
8002f7e: bd80 pop {r7, pc}
8002f80: 40022000 .word 0x40022000
8002f84: 40021000 .word 0x40021000
8002f88: 08004cc8 .word 0x08004cc8
8002f8c: 20000004 .word 0x20000004
8002f90: 20000008 .word 0x20000008
08002f94 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002f94: b480 push {r7}
8002f96: b089 sub sp, #36 @ 0x24
8002f98: af00 add r7, sp, #0
uint32_t msirange = 0U, sysclockfreq = 0U;
8002f9a: 2300 movs r3, #0
8002f9c: 61fb str r3, [r7, #28]
8002f9e: 2300 movs r3, #0
8002fa0: 61bb str r3, [r7, #24]
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
uint32_t sysclk_source, pll_oscsource;
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8002fa2: 4b3e ldr r3, [pc, #248] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
8002fa4: 689b ldr r3, [r3, #8]
8002fa6: f003 030c and.w r3, r3, #12
8002faa: 613b str r3, [r7, #16]
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
8002fac: 4b3b ldr r3, [pc, #236] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
8002fae: 68db ldr r3, [r3, #12]
8002fb0: f003 0303 and.w r3, r3, #3
8002fb4: 60fb str r3, [r7, #12]
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
8002fb6: 693b ldr r3, [r7, #16]
8002fb8: 2b00 cmp r3, #0
8002fba: d005 beq.n 8002fc8 <HAL_RCC_GetSysClockFreq+0x34>
8002fbc: 693b ldr r3, [r7, #16]
8002fbe: 2b0c cmp r3, #12
8002fc0: d121 bne.n 8003006 <HAL_RCC_GetSysClockFreq+0x72>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
8002fc2: 68fb ldr r3, [r7, #12]
8002fc4: 2b01 cmp r3, #1
8002fc6: d11e bne.n 8003006 <HAL_RCC_GetSysClockFreq+0x72>
{
/* MSI or PLL with MSI source used as system clock source */
/* Get SYSCLK source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
8002fc8: 4b34 ldr r3, [pc, #208] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
8002fca: 681b ldr r3, [r3, #0]
8002fcc: f003 0308 and.w r3, r3, #8
8002fd0: 2b00 cmp r3, #0
8002fd2: d107 bne.n 8002fe4 <HAL_RCC_GetSysClockFreq+0x50>
{ /* MSISRANGE from RCC_CSR applies */
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
8002fd4: 4b31 ldr r3, [pc, #196] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
8002fd6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8002fda: 0a1b lsrs r3, r3, #8
8002fdc: f003 030f and.w r3, r3, #15
8002fe0: 61fb str r3, [r7, #28]
8002fe2: e005 b.n 8002ff0 <HAL_RCC_GetSysClockFreq+0x5c>
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
8002fe4: 4b2d ldr r3, [pc, #180] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
8002fe6: 681b ldr r3, [r3, #0]
8002fe8: 091b lsrs r3, r3, #4
8002fea: f003 030f and.w r3, r3, #15
8002fee: 61fb str r3, [r7, #28]
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
8002ff0: 4a2b ldr r2, [pc, #172] @ (80030a0 <HAL_RCC_GetSysClockFreq+0x10c>)
8002ff2: 69fb ldr r3, [r7, #28]
8002ff4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8002ff8: 61fb str r3, [r7, #28]
if(sysclk_source == RCC_CFGR_SWS_MSI)
8002ffa: 693b ldr r3, [r7, #16]
8002ffc: 2b00 cmp r3, #0
8002ffe: d10d bne.n 800301c <HAL_RCC_GetSysClockFreq+0x88>
{
/* MSI used as system clock source */
sysclockfreq = msirange;
8003000: 69fb ldr r3, [r7, #28]
8003002: 61bb str r3, [r7, #24]
if(sysclk_source == RCC_CFGR_SWS_MSI)
8003004: e00a b.n 800301c <HAL_RCC_GetSysClockFreq+0x88>
}
}
else if(sysclk_source == RCC_CFGR_SWS_HSI)
8003006: 693b ldr r3, [r7, #16]
8003008: 2b04 cmp r3, #4
800300a: d102 bne.n 8003012 <HAL_RCC_GetSysClockFreq+0x7e>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
800300c: 4b25 ldr r3, [pc, #148] @ (80030a4 <HAL_RCC_GetSysClockFreq+0x110>)
800300e: 61bb str r3, [r7, #24]
8003010: e004 b.n 800301c <HAL_RCC_GetSysClockFreq+0x88>
}
else if(sysclk_source == RCC_CFGR_SWS_HSE)
8003012: 693b ldr r3, [r7, #16]
8003014: 2b08 cmp r3, #8
8003016: d101 bne.n 800301c <HAL_RCC_GetSysClockFreq+0x88>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8003018: 4b23 ldr r3, [pc, #140] @ (80030a8 <HAL_RCC_GetSysClockFreq+0x114>)
800301a: 61bb str r3, [r7, #24]
else
{
/* unexpected case: sysclockfreq at 0 */
}
if(sysclk_source == RCC_CFGR_SWS_PLL)
800301c: 693b ldr r3, [r7, #16]
800301e: 2b0c cmp r3, #12
8003020: d134 bne.n 800308c <HAL_RCC_GetSysClockFreq+0xf8>
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8003022: 4b1e ldr r3, [pc, #120] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
8003024: 68db ldr r3, [r3, #12]
8003026: f003 0303 and.w r3, r3, #3
800302a: 60bb str r3, [r7, #8]
switch (pllsource)
800302c: 68bb ldr r3, [r7, #8]
800302e: 2b02 cmp r3, #2
8003030: d003 beq.n 800303a <HAL_RCC_GetSysClockFreq+0xa6>
8003032: 68bb ldr r3, [r7, #8]
8003034: 2b03 cmp r3, #3
8003036: d003 beq.n 8003040 <HAL_RCC_GetSysClockFreq+0xac>
8003038: e005 b.n 8003046 <HAL_RCC_GetSysClockFreq+0xb2>
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllvco = HSI_VALUE;
800303a: 4b1a ldr r3, [pc, #104] @ (80030a4 <HAL_RCC_GetSysClockFreq+0x110>)
800303c: 617b str r3, [r7, #20]
break;
800303e: e005 b.n 800304c <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = HSE_VALUE;
8003040: 4b19 ldr r3, [pc, #100] @ (80030a8 <HAL_RCC_GetSysClockFreq+0x114>)
8003042: 617b str r3, [r7, #20]
break;
8003044: e002 b.n 800304c <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default:
pllvco = msirange;
8003046: 69fb ldr r3, [r7, #28]
8003048: 617b str r3, [r7, #20]
break;
800304a: bf00 nop
}
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
800304c: 4b13 ldr r3, [pc, #76] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
800304e: 68db ldr r3, [r3, #12]
8003050: 091b lsrs r3, r3, #4
8003052: f003 0307 and.w r3, r3, #7
8003056: 3301 adds r3, #1
8003058: 607b str r3, [r7, #4]
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
800305a: 4b10 ldr r3, [pc, #64] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
800305c: 68db ldr r3, [r3, #12]
800305e: 0a1b lsrs r3, r3, #8
8003060: f003 037f and.w r3, r3, #127 @ 0x7f
8003064: 697a ldr r2, [r7, #20]
8003066: fb03 f202 mul.w r2, r3, r2
800306a: 687b ldr r3, [r7, #4]
800306c: fbb2 f3f3 udiv r3, r2, r3
8003070: 617b str r3, [r7, #20]
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8003072: 4b0a ldr r3, [pc, #40] @ (800309c <HAL_RCC_GetSysClockFreq+0x108>)
8003074: 68db ldr r3, [r3, #12]
8003076: 0e5b lsrs r3, r3, #25
8003078: f003 0303 and.w r3, r3, #3
800307c: 3301 adds r3, #1
800307e: 005b lsls r3, r3, #1
8003080: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllr;
8003082: 697a ldr r2, [r7, #20]
8003084: 683b ldr r3, [r7, #0]
8003086: fbb2 f3f3 udiv r3, r2, r3
800308a: 61bb str r3, [r7, #24]
}
return sysclockfreq;
800308c: 69bb ldr r3, [r7, #24]
}
800308e: 4618 mov r0, r3
8003090: 3724 adds r7, #36 @ 0x24
8003092: 46bd mov sp, r7
8003094: f85d 7b04 ldr.w r7, [sp], #4
8003098: 4770 bx lr
800309a: bf00 nop
800309c: 40021000 .word 0x40021000
80030a0: 08004ce0 .word 0x08004ce0
80030a4: 00f42400 .word 0x00f42400
80030a8: 007a1200 .word 0x007a1200
080030ac <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80030ac: b480 push {r7}
80030ae: af00 add r7, sp, #0
return SystemCoreClock;
80030b0: 4b03 ldr r3, [pc, #12] @ (80030c0 <HAL_RCC_GetHCLKFreq+0x14>)
80030b2: 681b ldr r3, [r3, #0]
}
80030b4: 4618 mov r0, r3
80030b6: 46bd mov sp, r7
80030b8: f85d 7b04 ldr.w r7, [sp], #4
80030bc: 4770 bx lr
80030be: bf00 nop
80030c0: 20000004 .word 0x20000004
080030c4 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
80030c4: b580 push {r7, lr}
80030c6: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
80030c8: f7ff fff0 bl 80030ac <HAL_RCC_GetHCLKFreq>
80030cc: 4602 mov r2, r0
80030ce: 4b06 ldr r3, [pc, #24] @ (80030e8 <HAL_RCC_GetPCLK1Freq+0x24>)
80030d0: 689b ldr r3, [r3, #8]
80030d2: 0a1b lsrs r3, r3, #8
80030d4: f003 0307 and.w r3, r3, #7
80030d8: 4904 ldr r1, [pc, #16] @ (80030ec <HAL_RCC_GetPCLK1Freq+0x28>)
80030da: 5ccb ldrb r3, [r1, r3]
80030dc: f003 031f and.w r3, r3, #31
80030e0: fa22 f303 lsr.w r3, r2, r3
}
80030e4: 4618 mov r0, r3
80030e6: bd80 pop {r7, pc}
80030e8: 40021000 .word 0x40021000
80030ec: 08004cd8 .word 0x08004cd8
080030f0 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
80030f0: b580 push {r7, lr}
80030f2: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
80030f4: f7ff ffda bl 80030ac <HAL_RCC_GetHCLKFreq>
80030f8: 4602 mov r2, r0
80030fa: 4b06 ldr r3, [pc, #24] @ (8003114 <HAL_RCC_GetPCLK2Freq+0x24>)
80030fc: 689b ldr r3, [r3, #8]
80030fe: 0adb lsrs r3, r3, #11
8003100: f003 0307 and.w r3, r3, #7
8003104: 4904 ldr r1, [pc, #16] @ (8003118 <HAL_RCC_GetPCLK2Freq+0x28>)
8003106: 5ccb ldrb r3, [r1, r3]
8003108: f003 031f and.w r3, r3, #31
800310c: fa22 f303 lsr.w r3, r2, r3
}
8003110: 4618 mov r0, r3
8003112: bd80 pop {r7, pc}
8003114: 40021000 .word 0x40021000
8003118: 08004cd8 .word 0x08004cd8
0800311c <RCC_SetFlashLatencyFromMSIRange>:
voltage range.
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
800311c: b580 push {r7, lr}
800311e: b086 sub sp, #24
8003120: af00 add r7, sp, #0
8003122: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
8003124: 2300 movs r3, #0
8003126: 613b str r3, [r7, #16]
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
8003128: 4b2a ldr r3, [pc, #168] @ (80031d4 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800312a: 6d9b ldr r3, [r3, #88] @ 0x58
800312c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003130: 2b00 cmp r3, #0
8003132: d003 beq.n 800313c <RCC_SetFlashLatencyFromMSIRange+0x20>
{
vos = HAL_PWREx_GetVoltageRange();
8003134: f7ff f922 bl 800237c <HAL_PWREx_GetVoltageRange>
8003138: 6178 str r0, [r7, #20]
800313a: e014 b.n 8003166 <RCC_SetFlashLatencyFromMSIRange+0x4a>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
800313c: 4b25 ldr r3, [pc, #148] @ (80031d4 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800313e: 6d9b ldr r3, [r3, #88] @ 0x58
8003140: 4a24 ldr r2, [pc, #144] @ (80031d4 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8003142: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003146: 6593 str r3, [r2, #88] @ 0x58
8003148: 4b22 ldr r3, [pc, #136] @ (80031d4 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800314a: 6d9b ldr r3, [r3, #88] @ 0x58
800314c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003150: 60fb str r3, [r7, #12]
8003152: 68fb ldr r3, [r7, #12]
vos = HAL_PWREx_GetVoltageRange();
8003154: f7ff f912 bl 800237c <HAL_PWREx_GetVoltageRange>
8003158: 6178 str r0, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
800315a: 4b1e ldr r3, [pc, #120] @ (80031d4 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800315c: 6d9b ldr r3, [r3, #88] @ 0x58
800315e: 4a1d ldr r2, [pc, #116] @ (80031d4 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8003160: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8003164: 6593 str r3, [r2, #88] @ 0x58
}
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
8003166: 697b ldr r3, [r7, #20]
8003168: f5b3 7f00 cmp.w r3, #512 @ 0x200
800316c: d10b bne.n 8003186 <RCC_SetFlashLatencyFromMSIRange+0x6a>
{
if(msirange > RCC_MSIRANGE_8)
800316e: 687b ldr r3, [r7, #4]
8003170: 2b80 cmp r3, #128 @ 0x80
8003172: d919 bls.n 80031a8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI > 16Mhz */
if(msirange > RCC_MSIRANGE_10)
8003174: 687b ldr r3, [r7, #4]
8003176: 2ba0 cmp r3, #160 @ 0xa0
8003178: d902 bls.n 8003180 <RCC_SetFlashLatencyFromMSIRange+0x64>
{
/* MSI 48Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
800317a: 2302 movs r3, #2
800317c: 613b str r3, [r7, #16]
800317e: e013 b.n 80031a8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
/* MSI 24Mhz or 32Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
8003180: 2301 movs r3, #1
8003182: 613b str r3, [r7, #16]
8003184: e010 b.n 80031a8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
latency = FLASH_LATENCY_1; /* 1WS */
}
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
}
#else
if(msirange > RCC_MSIRANGE_8)
8003186: 687b ldr r3, [r7, #4]
8003188: 2b80 cmp r3, #128 @ 0x80
800318a: d902 bls.n 8003192 <RCC_SetFlashLatencyFromMSIRange+0x76>
{
/* MSI > 16Mhz */
latency = FLASH_LATENCY_3; /* 3WS */
800318c: 2303 movs r3, #3
800318e: 613b str r3, [r7, #16]
8003190: e00a b.n 80031a8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
if(msirange == RCC_MSIRANGE_8)
8003192: 687b ldr r3, [r7, #4]
8003194: 2b80 cmp r3, #128 @ 0x80
8003196: d102 bne.n 800319e <RCC_SetFlashLatencyFromMSIRange+0x82>
{
/* MSI 16Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
8003198: 2302 movs r3, #2
800319a: 613b str r3, [r7, #16]
800319c: e004 b.n 80031a8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else if(msirange == RCC_MSIRANGE_7)
800319e: 687b ldr r3, [r7, #4]
80031a0: 2b70 cmp r3, #112 @ 0x70
80031a2: d101 bne.n 80031a8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
80031a4: 2301 movs r3, #1
80031a6: 613b str r3, [r7, #16]
}
}
#endif
}
__HAL_FLASH_SET_LATENCY(latency);
80031a8: 4b0b ldr r3, [pc, #44] @ (80031d8 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80031aa: 681b ldr r3, [r3, #0]
80031ac: f023 0207 bic.w r2, r3, #7
80031b0: 4909 ldr r1, [pc, #36] @ (80031d8 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80031b2: 693b ldr r3, [r7, #16]
80031b4: 4313 orrs r3, r2
80031b6: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
80031b8: 4b07 ldr r3, [pc, #28] @ (80031d8 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80031ba: 681b ldr r3, [r3, #0]
80031bc: f003 0307 and.w r3, r3, #7
80031c0: 693a ldr r2, [r7, #16]
80031c2: 429a cmp r2, r3
80031c4: d001 beq.n 80031ca <RCC_SetFlashLatencyFromMSIRange+0xae>
{
return HAL_ERROR;
80031c6: 2301 movs r3, #1
80031c8: e000 b.n 80031cc <RCC_SetFlashLatencyFromMSIRange+0xb0>
}
return HAL_OK;
80031ca: 2300 movs r3, #0
}
80031cc: 4618 mov r0, r3
80031ce: 3718 adds r7, #24
80031d0: 46bd mov sp, r7
80031d2: bd80 pop {r7, pc}
80031d4: 40021000 .word 0x40021000
80031d8: 40022000 .word 0x40022000
080031dc <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
80031dc: b580 push {r7, lr}
80031de: b086 sub sp, #24
80031e0: af00 add r7, sp, #0
80031e2: 6078 str r0, [r7, #4]
uint32_t tmpregister, tickstart; /* no init needed */
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
80031e4: 2300 movs r3, #0
80031e6: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
80031e8: 2300 movs r3, #0
80031ea: 74bb strb r3, [r7, #18]
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
80031ec: 687b ldr r3, [r7, #4]
80031ee: 681b ldr r3, [r3, #0]
80031f0: f403 6300 and.w r3, r3, #2048 @ 0x800
80031f4: 2b00 cmp r3, #0
80031f6: d041 beq.n 800327c <HAL_RCCEx_PeriphCLKConfig+0xa0>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
switch(PeriphClkInit->Sai1ClockSelection)
80031f8: 687b ldr r3, [r7, #4]
80031fa: 6e5b ldr r3, [r3, #100] @ 0x64
80031fc: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
8003200: d02a beq.n 8003258 <HAL_RCCEx_PeriphCLKConfig+0x7c>
8003202: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
8003206: d824 bhi.n 8003252 <HAL_RCCEx_PeriphCLKConfig+0x76>
8003208: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
800320c: d008 beq.n 8003220 <HAL_RCCEx_PeriphCLKConfig+0x44>
800320e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
8003212: d81e bhi.n 8003252 <HAL_RCCEx_PeriphCLKConfig+0x76>
8003214: 2b00 cmp r3, #0
8003216: d00a beq.n 800322e <HAL_RCCEx_PeriphCLKConfig+0x52>
8003218: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
800321c: d010 beq.n 8003240 <HAL_RCCEx_PeriphCLKConfig+0x64>
800321e: e018 b.n 8003252 <HAL_RCCEx_PeriphCLKConfig+0x76>
{
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
/* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
8003220: 4b86 ldr r3, [pc, #536] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003222: 68db ldr r3, [r3, #12]
8003224: 4a85 ldr r2, [pc, #532] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003226: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800322a: 60d3 str r3, [r2, #12]
#else
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
/* SAI1 clock source config set later after clock selection check */
break;
800322c: e015 b.n 800325a <HAL_RCCEx_PeriphCLKConfig+0x7e>
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
800322e: 687b ldr r3, [r7, #4]
8003230: 3304 adds r3, #4
8003232: 2100 movs r1, #0
8003234: 4618 mov r0, r3
8003236: f000 facb bl 80037d0 <RCCEx_PLLSAI1_Config>
800323a: 4603 mov r3, r0
800323c: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
800323e: e00c b.n 800325a <HAL_RCCEx_PeriphCLKConfig+0x7e>
#if defined(RCC_PLLSAI2_SUPPORT)
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
8003240: 687b ldr r3, [r7, #4]
8003242: 3320 adds r3, #32
8003244: 2100 movs r1, #0
8003246: 4618 mov r0, r3
8003248: f000 fbb6 bl 80039b8 <RCCEx_PLLSAI2_Config>
800324c: 4603 mov r3, r0
800324e: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
8003250: e003 b.n 800325a <HAL_RCCEx_PeriphCLKConfig+0x7e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI1 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
8003252: 2301 movs r3, #1
8003254: 74fb strb r3, [r7, #19]
break;
8003256: e000 b.n 800325a <HAL_RCCEx_PeriphCLKConfig+0x7e>
break;
8003258: bf00 nop
}
if(ret == HAL_OK)
800325a: 7cfb ldrb r3, [r7, #19]
800325c: 2b00 cmp r3, #0
800325e: d10b bne.n 8003278 <HAL_RCCEx_PeriphCLKConfig+0x9c>
{
/* Set the source of SAI1 clock*/
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8003260: 4b76 ldr r3, [pc, #472] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003262: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003266: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
800326a: 687b ldr r3, [r7, #4]
800326c: 6e5b ldr r3, [r3, #100] @ 0x64
800326e: 4973 ldr r1, [pc, #460] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003270: 4313 orrs r3, r2
8003272: f8c1 3088 str.w r3, [r1, #136] @ 0x88
8003276: e001 b.n 800327c <HAL_RCCEx_PeriphCLKConfig+0xa0>
}
else
{
/* set overall return value */
status = ret;
8003278: 7cfb ldrb r3, [r7, #19]
800327a: 74bb strb r3, [r7, #18]
#endif /* SAI1 */
#if defined(SAI2)
/*-------------------------- SAI2 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
800327c: 687b ldr r3, [r7, #4]
800327e: 681b ldr r3, [r3, #0]
8003280: f403 5380 and.w r3, r3, #4096 @ 0x1000
8003284: 2b00 cmp r3, #0
8003286: d041 beq.n 800330c <HAL_RCCEx_PeriphCLKConfig+0x130>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
switch(PeriphClkInit->Sai2ClockSelection)
8003288: 687b ldr r3, [r7, #4]
800328a: 6e9b ldr r3, [r3, #104] @ 0x68
800328c: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
8003290: d02a beq.n 80032e8 <HAL_RCCEx_PeriphCLKConfig+0x10c>
8003292: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
8003296: d824 bhi.n 80032e2 <HAL_RCCEx_PeriphCLKConfig+0x106>
8003298: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
800329c: d008 beq.n 80032b0 <HAL_RCCEx_PeriphCLKConfig+0xd4>
800329e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
80032a2: d81e bhi.n 80032e2 <HAL_RCCEx_PeriphCLKConfig+0x106>
80032a4: 2b00 cmp r3, #0
80032a6: d00a beq.n 80032be <HAL_RCCEx_PeriphCLKConfig+0xe2>
80032a8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80032ac: d010 beq.n 80032d0 <HAL_RCCEx_PeriphCLKConfig+0xf4>
80032ae: e018 b.n 80032e2 <HAL_RCCEx_PeriphCLKConfig+0x106>
{
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
/* Enable SAI Clock output generated from System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
80032b0: 4b62 ldr r3, [pc, #392] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80032b2: 68db ldr r3, [r3, #12]
80032b4: 4a61 ldr r2, [pc, #388] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80032b6: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80032ba: 60d3 str r3, [r2, #12]
/* SAI2 clock source config set later after clock selection check */
break;
80032bc: e015 b.n 80032ea <HAL_RCCEx_PeriphCLKConfig+0x10e>
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
80032be: 687b ldr r3, [r7, #4]
80032c0: 3304 adds r3, #4
80032c2: 2100 movs r1, #0
80032c4: 4618 mov r0, r3
80032c6: f000 fa83 bl 80037d0 <RCCEx_PLLSAI1_Config>
80032ca: 4603 mov r3, r0
80032cc: 74fb strb r3, [r7, #19]
/* SAI2 clock source config set later after clock selection check */
break;
80032ce: e00c b.n 80032ea <HAL_RCCEx_PeriphCLKConfig+0x10e>
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
80032d0: 687b ldr r3, [r7, #4]
80032d2: 3320 adds r3, #32
80032d4: 2100 movs r1, #0
80032d6: 4618 mov r0, r3
80032d8: f000 fb6e bl 80039b8 <RCCEx_PLLSAI2_Config>
80032dc: 4603 mov r3, r0
80032de: 74fb strb r3, [r7, #19]
/* SAI2 clock source config set later after clock selection check */
break;
80032e0: e003 b.n 80032ea <HAL_RCCEx_PeriphCLKConfig+0x10e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI2 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
80032e2: 2301 movs r3, #1
80032e4: 74fb strb r3, [r7, #19]
break;
80032e6: e000 b.n 80032ea <HAL_RCCEx_PeriphCLKConfig+0x10e>
break;
80032e8: bf00 nop
}
if(ret == HAL_OK)
80032ea: 7cfb ldrb r3, [r7, #19]
80032ec: 2b00 cmp r3, #0
80032ee: d10b bne.n 8003308 <HAL_RCCEx_PeriphCLKConfig+0x12c>
{
/* Set the source of SAI2 clock*/
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
80032f0: 4b52 ldr r3, [pc, #328] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80032f2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80032f6: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
80032fa: 687b ldr r3, [r7, #4]
80032fc: 6e9b ldr r3, [r3, #104] @ 0x68
80032fe: 494f ldr r1, [pc, #316] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003300: 4313 orrs r3, r2
8003302: f8c1 3088 str.w r3, [r1, #136] @ 0x88
8003306: e001 b.n 800330c <HAL_RCCEx_PeriphCLKConfig+0x130>
}
else
{
/* set overall return value */
status = ret;
8003308: 7cfb ldrb r3, [r7, #19]
800330a: 74bb strb r3, [r7, #18]
}
}
#endif /* SAI2 */
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
800330c: 687b ldr r3, [r7, #4]
800330e: 681b ldr r3, [r3, #0]
8003310: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003314: 2b00 cmp r3, #0
8003316: f000 80a0 beq.w 800345a <HAL_RCCEx_PeriphCLKConfig+0x27e>
{
FlagStatus pwrclkchanged = RESET;
800331a: 2300 movs r3, #0
800331c: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
800331e: 4b47 ldr r3, [pc, #284] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003320: 6d9b ldr r3, [r3, #88] @ 0x58
8003322: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003326: 2b00 cmp r3, #0
8003328: d101 bne.n 800332e <HAL_RCCEx_PeriphCLKConfig+0x152>
800332a: 2301 movs r3, #1
800332c: e000 b.n 8003330 <HAL_RCCEx_PeriphCLKConfig+0x154>
800332e: 2300 movs r3, #0
8003330: 2b00 cmp r3, #0
8003332: d00d beq.n 8003350 <HAL_RCCEx_PeriphCLKConfig+0x174>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003334: 4b41 ldr r3, [pc, #260] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003336: 6d9b ldr r3, [r3, #88] @ 0x58
8003338: 4a40 ldr r2, [pc, #256] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
800333a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800333e: 6593 str r3, [r2, #88] @ 0x58
8003340: 4b3e ldr r3, [pc, #248] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003342: 6d9b ldr r3, [r3, #88] @ 0x58
8003344: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003348: 60bb str r3, [r7, #8]
800334a: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800334c: 2301 movs r3, #1
800334e: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8003350: 4b3b ldr r3, [pc, #236] @ (8003440 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8003352: 681b ldr r3, [r3, #0]
8003354: 4a3a ldr r2, [pc, #232] @ (8003440 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8003356: f443 7380 orr.w r3, r3, #256 @ 0x100
800335a: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800335c: f7fe f94e bl 80015fc <HAL_GetTick>
8003360: 60f8 str r0, [r7, #12]
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8003362: e009 b.n 8003378 <HAL_RCCEx_PeriphCLKConfig+0x19c>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003364: f7fe f94a bl 80015fc <HAL_GetTick>
8003368: 4602 mov r2, r0
800336a: 68fb ldr r3, [r7, #12]
800336c: 1ad3 subs r3, r2, r3
800336e: 2b02 cmp r3, #2
8003370: d902 bls.n 8003378 <HAL_RCCEx_PeriphCLKConfig+0x19c>
{
ret = HAL_TIMEOUT;
8003372: 2303 movs r3, #3
8003374: 74fb strb r3, [r7, #19]
break;
8003376: e005 b.n 8003384 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8003378: 4b31 ldr r3, [pc, #196] @ (8003440 <HAL_RCCEx_PeriphCLKConfig+0x264>)
800337a: 681b ldr r3, [r3, #0]
800337c: f403 7380 and.w r3, r3, #256 @ 0x100
8003380: 2b00 cmp r3, #0
8003382: d0ef beq.n 8003364 <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
if(ret == HAL_OK)
8003384: 7cfb ldrb r3, [r7, #19]
8003386: 2b00 cmp r3, #0
8003388: d15c bne.n 8003444 <HAL_RCCEx_PeriphCLKConfig+0x268>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
800338a: 4b2c ldr r3, [pc, #176] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
800338c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003390: f403 7340 and.w r3, r3, #768 @ 0x300
8003394: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8003396: 697b ldr r3, [r7, #20]
8003398: 2b00 cmp r3, #0
800339a: d01f beq.n 80033dc <HAL_RCCEx_PeriphCLKConfig+0x200>
800339c: 687b ldr r3, [r7, #4]
800339e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
80033a2: 697a ldr r2, [r7, #20]
80033a4: 429a cmp r2, r3
80033a6: d019 beq.n 80033dc <HAL_RCCEx_PeriphCLKConfig+0x200>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
80033a8: 4b24 ldr r3, [pc, #144] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80033aa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80033ae: f423 7340 bic.w r3, r3, #768 @ 0x300
80033b2: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80033b4: 4b21 ldr r3, [pc, #132] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80033b6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80033ba: 4a20 ldr r2, [pc, #128] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80033bc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80033c0: f8c2 3090 str.w r3, [r2, #144] @ 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
80033c4: 4b1d ldr r3, [pc, #116] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80033c6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80033ca: 4a1c ldr r2, [pc, #112] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80033cc: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80033d0: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
80033d4: 4a19 ldr r2, [pc, #100] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
80033d6: 697b ldr r3, [r7, #20]
80033d8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
80033dc: 697b ldr r3, [r7, #20]
80033de: f003 0301 and.w r3, r3, #1
80033e2: 2b00 cmp r3, #0
80033e4: d016 beq.n 8003414 <HAL_RCCEx_PeriphCLKConfig+0x238>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80033e6: f7fe f909 bl 80015fc <HAL_GetTick>
80033ea: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80033ec: e00b b.n 8003406 <HAL_RCCEx_PeriphCLKConfig+0x22a>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80033ee: f7fe f905 bl 80015fc <HAL_GetTick>
80033f2: 4602 mov r2, r0
80033f4: 68fb ldr r3, [r7, #12]
80033f6: 1ad3 subs r3, r2, r3
80033f8: f241 3288 movw r2, #5000 @ 0x1388
80033fc: 4293 cmp r3, r2
80033fe: d902 bls.n 8003406 <HAL_RCCEx_PeriphCLKConfig+0x22a>
{
ret = HAL_TIMEOUT;
8003400: 2303 movs r3, #3
8003402: 74fb strb r3, [r7, #19]
break;
8003404: e006 b.n 8003414 <HAL_RCCEx_PeriphCLKConfig+0x238>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003406: 4b0d ldr r3, [pc, #52] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003408: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800340c: f003 0302 and.w r3, r3, #2
8003410: 2b00 cmp r3, #0
8003412: d0ec beq.n 80033ee <HAL_RCCEx_PeriphCLKConfig+0x212>
}
}
}
if(ret == HAL_OK)
8003414: 7cfb ldrb r3, [r7, #19]
8003416: 2b00 cmp r3, #0
8003418: d10c bne.n 8003434 <HAL_RCCEx_PeriphCLKConfig+0x258>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800341a: 4b08 ldr r3, [pc, #32] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
800341c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003420: f423 7240 bic.w r2, r3, #768 @ 0x300
8003424: 687b ldr r3, [r7, #4]
8003426: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
800342a: 4904 ldr r1, [pc, #16] @ (800343c <HAL_RCCEx_PeriphCLKConfig+0x260>)
800342c: 4313 orrs r3, r2
800342e: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8003432: e009 b.n 8003448 <HAL_RCCEx_PeriphCLKConfig+0x26c>
}
else
{
/* set overall return value */
status = ret;
8003434: 7cfb ldrb r3, [r7, #19]
8003436: 74bb strb r3, [r7, #18]
8003438: e006 b.n 8003448 <HAL_RCCEx_PeriphCLKConfig+0x26c>
800343a: bf00 nop
800343c: 40021000 .word 0x40021000
8003440: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8003444: 7cfb ldrb r3, [r7, #19]
8003446: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8003448: 7c7b ldrb r3, [r7, #17]
800344a: 2b01 cmp r3, #1
800344c: d105 bne.n 800345a <HAL_RCCEx_PeriphCLKConfig+0x27e>
{
__HAL_RCC_PWR_CLK_DISABLE();
800344e: 4b9e ldr r3, [pc, #632] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003450: 6d9b ldr r3, [r3, #88] @ 0x58
8003452: 4a9d ldr r2, [pc, #628] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003454: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8003458: 6593 str r3, [r2, #88] @ 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
800345a: 687b ldr r3, [r7, #4]
800345c: 681b ldr r3, [r3, #0]
800345e: f003 0301 and.w r3, r3, #1
8003462: 2b00 cmp r3, #0
8003464: d00a beq.n 800347c <HAL_RCCEx_PeriphCLKConfig+0x2a0>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8003466: 4b98 ldr r3, [pc, #608] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003468: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800346c: f023 0203 bic.w r2, r3, #3
8003470: 687b ldr r3, [r7, #4]
8003472: 6b9b ldr r3, [r3, #56] @ 0x38
8003474: 4994 ldr r1, [pc, #592] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003476: 4313 orrs r3, r2
8003478: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
800347c: 687b ldr r3, [r7, #4]
800347e: 681b ldr r3, [r3, #0]
8003480: f003 0302 and.w r3, r3, #2
8003484: 2b00 cmp r3, #0
8003486: d00a beq.n 800349e <HAL_RCCEx_PeriphCLKConfig+0x2c2>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8003488: 4b8f ldr r3, [pc, #572] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800348a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800348e: f023 020c bic.w r2, r3, #12
8003492: 687b ldr r3, [r7, #4]
8003494: 6bdb ldr r3, [r3, #60] @ 0x3c
8003496: 498c ldr r1, [pc, #560] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003498: 4313 orrs r3, r2
800349a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
800349e: 687b ldr r3, [r7, #4]
80034a0: 681b ldr r3, [r3, #0]
80034a2: f003 0304 and.w r3, r3, #4
80034a6: 2b00 cmp r3, #0
80034a8: d00a beq.n 80034c0 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
80034aa: 4b87 ldr r3, [pc, #540] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80034ac: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80034b0: f023 0230 bic.w r2, r3, #48 @ 0x30
80034b4: 687b ldr r3, [r7, #4]
80034b6: 6c1b ldr r3, [r3, #64] @ 0x40
80034b8: 4983 ldr r1, [pc, #524] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80034ba: 4313 orrs r3, r2
80034bc: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* USART3 */
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
80034c0: 687b ldr r3, [r7, #4]
80034c2: 681b ldr r3, [r3, #0]
80034c4: f003 0308 and.w r3, r3, #8
80034c8: 2b00 cmp r3, #0
80034ca: d00a beq.n 80034e2 <HAL_RCCEx_PeriphCLKConfig+0x306>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
80034cc: 4b7e ldr r3, [pc, #504] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80034ce: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80034d2: f023 02c0 bic.w r2, r3, #192 @ 0xc0
80034d6: 687b ldr r3, [r7, #4]
80034d8: 6c5b ldr r3, [r3, #68] @ 0x44
80034da: 497b ldr r1, [pc, #492] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80034dc: 4313 orrs r3, r2
80034de: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* UART4 */
#if defined(UART5)
/*-------------------------- UART5 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
80034e2: 687b ldr r3, [r7, #4]
80034e4: 681b ldr r3, [r3, #0]
80034e6: f003 0310 and.w r3, r3, #16
80034ea: 2b00 cmp r3, #0
80034ec: d00a beq.n 8003504 <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
80034ee: 4b76 ldr r3, [pc, #472] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80034f0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80034f4: f423 7240 bic.w r2, r3, #768 @ 0x300
80034f8: 687b ldr r3, [r7, #4]
80034fa: 6c9b ldr r3, [r3, #72] @ 0x48
80034fc: 4972 ldr r1, [pc, #456] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80034fe: 4313 orrs r3, r2
8003500: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8003504: 687b ldr r3, [r7, #4]
8003506: 681b ldr r3, [r3, #0]
8003508: f003 0320 and.w r3, r3, #32
800350c: 2b00 cmp r3, #0
800350e: d00a beq.n 8003526 <HAL_RCCEx_PeriphCLKConfig+0x34a>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUART1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8003510: 4b6d ldr r3, [pc, #436] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003512: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003516: f423 6240 bic.w r2, r3, #3072 @ 0xc00
800351a: 687b ldr r3, [r7, #4]
800351c: 6cdb ldr r3, [r3, #76] @ 0x4c
800351e: 496a ldr r1, [pc, #424] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003520: 4313 orrs r3, r2
8003522: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
8003526: 687b ldr r3, [r7, #4]
8003528: 681b ldr r3, [r3, #0]
800352a: f403 7300 and.w r3, r3, #512 @ 0x200
800352e: 2b00 cmp r3, #0
8003530: d00a beq.n 8003548 <HAL_RCCEx_PeriphCLKConfig+0x36c>
{
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8003532: 4b65 ldr r3, [pc, #404] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003534: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003538: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
800353c: 687b ldr r3, [r7, #4]
800353e: 6ddb ldr r3, [r3, #92] @ 0x5c
8003540: 4961 ldr r1, [pc, #388] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003542: 4313 orrs r3, r2
8003544: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
8003548: 687b ldr r3, [r7, #4]
800354a: 681b ldr r3, [r3, #0]
800354c: f403 6380 and.w r3, r3, #1024 @ 0x400
8003550: 2b00 cmp r3, #0
8003552: d00a beq.n 800356a <HAL_RCCEx_PeriphCLKConfig+0x38e>
{
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
8003554: 4b5c ldr r3, [pc, #368] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003556: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800355a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
800355e: 687b ldr r3, [r7, #4]
8003560: 6e1b ldr r3, [r3, #96] @ 0x60
8003562: 4959 ldr r1, [pc, #356] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003564: 4313 orrs r3, r2
8003566: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
800356a: 687b ldr r3, [r7, #4]
800356c: 681b ldr r3, [r3, #0]
800356e: f003 0340 and.w r3, r3, #64 @ 0x40
8003572: 2b00 cmp r3, #0
8003574: d00a beq.n 800358c <HAL_RCCEx_PeriphCLKConfig+0x3b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8003576: 4b54 ldr r3, [pc, #336] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003578: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800357c: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8003580: 687b ldr r3, [r7, #4]
8003582: 6d1b ldr r3, [r3, #80] @ 0x50
8003584: 4950 ldr r1, [pc, #320] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003586: 4313 orrs r3, r2
8003588: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(I2C2)
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
800358c: 687b ldr r3, [r7, #4]
800358e: 681b ldr r3, [r3, #0]
8003590: f003 0380 and.w r3, r3, #128 @ 0x80
8003594: 2b00 cmp r3, #0
8003596: d00a beq.n 80035ae <HAL_RCCEx_PeriphCLKConfig+0x3d2>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8003598: 4b4b ldr r3, [pc, #300] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800359a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800359e: f423 4240 bic.w r2, r3, #49152 @ 0xc000
80035a2: 687b ldr r3, [r7, #4]
80035a4: 6d5b ldr r3, [r3, #84] @ 0x54
80035a6: 4948 ldr r1, [pc, #288] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80035a8: 4313 orrs r3, r2
80035aa: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* I2C2 */
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
80035ae: 687b ldr r3, [r7, #4]
80035b0: 681b ldr r3, [r3, #0]
80035b2: f403 7380 and.w r3, r3, #256 @ 0x100
80035b6: 2b00 cmp r3, #0
80035b8: d00a beq.n 80035d0 <HAL_RCCEx_PeriphCLKConfig+0x3f4>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
80035ba: 4b43 ldr r3, [pc, #268] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80035bc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80035c0: f423 3240 bic.w r2, r3, #196608 @ 0x30000
80035c4: 687b ldr r3, [r7, #4]
80035c6: 6d9b ldr r3, [r3, #88] @ 0x58
80035c8: 493f ldr r1, [pc, #252] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80035ca: 4313 orrs r3, r2
80035cc: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* I2C4 */
#if defined(USB_OTG_FS) || defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
80035d0: 687b ldr r3, [r7, #4]
80035d2: 681b ldr r3, [r3, #0]
80035d4: f403 5300 and.w r3, r3, #8192 @ 0x2000
80035d8: 2b00 cmp r3, #0
80035da: d028 beq.n 800362e <HAL_RCCEx_PeriphCLKConfig+0x452>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
80035dc: 4b3a ldr r3, [pc, #232] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80035de: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80035e2: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
80035e6: 687b ldr r3, [r7, #4]
80035e8: 6edb ldr r3, [r3, #108] @ 0x6c
80035ea: 4937 ldr r1, [pc, #220] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80035ec: 4313 orrs r3, r2
80035ee: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
80035f2: 687b ldr r3, [r7, #4]
80035f4: 6edb ldr r3, [r3, #108] @ 0x6c
80035f6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80035fa: d106 bne.n 800360a <HAL_RCCEx_PeriphCLKConfig+0x42e>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80035fc: 4b32 ldr r3, [pc, #200] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80035fe: 68db ldr r3, [r3, #12]
8003600: 4a31 ldr r2, [pc, #196] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003602: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8003606: 60d3 str r3, [r2, #12]
8003608: e011 b.n 800362e <HAL_RCCEx_PeriphCLKConfig+0x452>
}
else
{
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
800360a: 687b ldr r3, [r7, #4]
800360c: 6edb ldr r3, [r3, #108] @ 0x6c
800360e: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
8003612: d10c bne.n 800362e <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
8003614: 687b ldr r3, [r7, #4]
8003616: 3304 adds r3, #4
8003618: 2101 movs r1, #1
800361a: 4618 mov r0, r3
800361c: f000 f8d8 bl 80037d0 <RCCEx_PLLSAI1_Config>
8003620: 4603 mov r3, r0
8003622: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003624: 7cfb ldrb r3, [r7, #19]
8003626: 2b00 cmp r3, #0
8003628: d001 beq.n 800362e <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* set overall return value */
status = ret;
800362a: 7cfb ldrb r3, [r7, #19]
800362c: 74bb strb r3, [r7, #18]
#endif /* USB_OTG_FS || USB */
#if defined(SDMMC1)
/*-------------------------- SDMMC1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
800362e: 687b ldr r3, [r7, #4]
8003630: 681b ldr r3, [r3, #0]
8003632: f403 2300 and.w r3, r3, #524288 @ 0x80000
8003636: 2b00 cmp r3, #0
8003638: d028 beq.n 800368c <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
800363a: 4b23 ldr r3, [pc, #140] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800363c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003640: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8003644: 687b ldr r3, [r7, #4]
8003646: 6f1b ldr r3, [r3, #112] @ 0x70
8003648: 491f ldr r1, [pc, #124] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800364a: 4313 orrs r3, r2
800364c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
8003650: 687b ldr r3, [r7, #4]
8003652: 6f1b ldr r3, [r3, #112] @ 0x70
8003654: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8003658: d106 bne.n 8003668 <HAL_RCCEx_PeriphCLKConfig+0x48c>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
800365a: 4b1b ldr r3, [pc, #108] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800365c: 68db ldr r3, [r3, #12]
800365e: 4a1a ldr r2, [pc, #104] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003660: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8003664: 60d3 str r3, [r2, #12]
8003666: e011 b.n 800368c <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* Enable PLLSAI3CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
}
#endif
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
8003668: 687b ldr r3, [r7, #4]
800366a: 6f1b ldr r3, [r3, #112] @ 0x70
800366c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
8003670: d10c bne.n 800368c <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
8003672: 687b ldr r3, [r7, #4]
8003674: 3304 adds r3, #4
8003676: 2101 movs r1, #1
8003678: 4618 mov r0, r3
800367a: f000 f8a9 bl 80037d0 <RCCEx_PLLSAI1_Config>
800367e: 4603 mov r3, r0
8003680: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003682: 7cfb ldrb r3, [r7, #19]
8003684: 2b00 cmp r3, #0
8003686: d001 beq.n 800368c <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* set overall return value */
status = ret;
8003688: 7cfb ldrb r3, [r7, #19]
800368a: 74bb strb r3, [r7, #18]
}
#endif /* SDMMC1 */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
800368c: 687b ldr r3, [r7, #4]
800368e: 681b ldr r3, [r3, #0]
8003690: f403 2380 and.w r3, r3, #262144 @ 0x40000
8003694: 2b00 cmp r3, #0
8003696: d02b beq.n 80036f0 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
8003698: 4b0b ldr r3, [pc, #44] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800369a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800369e: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
80036a2: 687b ldr r3, [r7, #4]
80036a4: 6f5b ldr r3, [r3, #116] @ 0x74
80036a6: 4908 ldr r1, [pc, #32] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80036a8: 4313 orrs r3, r2
80036aa: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
80036ae: 687b ldr r3, [r7, #4]
80036b0: 6f5b ldr r3, [r3, #116] @ 0x74
80036b2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80036b6: d109 bne.n 80036cc <HAL_RCCEx_PeriphCLKConfig+0x4f0>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80036b8: 4b03 ldr r3, [pc, #12] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80036ba: 68db ldr r3, [r3, #12]
80036bc: 4a02 ldr r2, [pc, #8] @ (80036c8 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80036be: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80036c2: 60d3 str r3, [r2, #12]
80036c4: e014 b.n 80036f0 <HAL_RCCEx_PeriphCLKConfig+0x514>
80036c6: bf00 nop
80036c8: 40021000 .word 0x40021000
}
#if defined(RCC_PLLSAI1_SUPPORT)
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
80036cc: 687b ldr r3, [r7, #4]
80036ce: 6f5b ldr r3, [r3, #116] @ 0x74
80036d0: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
80036d4: d10c bne.n 80036f0 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
80036d6: 687b ldr r3, [r7, #4]
80036d8: 3304 adds r3, #4
80036da: 2101 movs r1, #1
80036dc: 4618 mov r0, r3
80036de: f000 f877 bl 80037d0 <RCCEx_PLLSAI1_Config>
80036e2: 4603 mov r3, r0
80036e4: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
80036e6: 7cfb ldrb r3, [r7, #19]
80036e8: 2b00 cmp r3, #0
80036ea: d001 beq.n 80036f0 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* set overall return value */
status = ret;
80036ec: 7cfb ldrb r3, [r7, #19]
80036ee: 74bb strb r3, [r7, #18]
}
}
/*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
80036f0: 687b ldr r3, [r7, #4]
80036f2: 681b ldr r3, [r3, #0]
80036f4: f403 4380 and.w r3, r3, #16384 @ 0x4000
80036f8: 2b00 cmp r3, #0
80036fa: d02f beq.n 800375c <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
80036fc: 4b2b ldr r3, [pc, #172] @ (80037ac <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
80036fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003702: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
8003706: 687b ldr r3, [r7, #4]
8003708: 6f9b ldr r3, [r3, #120] @ 0x78
800370a: 4928 ldr r1, [pc, #160] @ (80037ac <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
800370c: 4313 orrs r3, r2
800370e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
8003712: 687b ldr r3, [r7, #4]
8003714: 6f9b ldr r3, [r3, #120] @ 0x78
8003716: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800371a: d10d bne.n 8003738 <HAL_RCCEx_PeriphCLKConfig+0x55c>
{
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
800371c: 687b ldr r3, [r7, #4]
800371e: 3304 adds r3, #4
8003720: 2102 movs r1, #2
8003722: 4618 mov r0, r3
8003724: f000 f854 bl 80037d0 <RCCEx_PLLSAI1_Config>
8003728: 4603 mov r3, r0
800372a: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
800372c: 7cfb ldrb r3, [r7, #19]
800372e: 2b00 cmp r3, #0
8003730: d014 beq.n 800375c <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* set overall return value */
status = ret;
8003732: 7cfb ldrb r3, [r7, #19]
8003734: 74bb strb r3, [r7, #18]
8003736: e011 b.n 800375c <HAL_RCCEx_PeriphCLKConfig+0x580>
}
#endif /* RCC_PLLSAI1_SUPPORT */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
8003738: 687b ldr r3, [r7, #4]
800373a: 6f9b ldr r3, [r3, #120] @ 0x78
800373c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8003740: d10c bne.n 800375c <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
8003742: 687b ldr r3, [r7, #4]
8003744: 3320 adds r3, #32
8003746: 2102 movs r1, #2
8003748: 4618 mov r0, r3
800374a: f000 f935 bl 80039b8 <RCCEx_PLLSAI2_Config>
800374e: 4603 mov r3, r0
8003750: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003752: 7cfb ldrb r3, [r7, #19]
8003754: 2b00 cmp r3, #0
8003756: d001 beq.n 800375c <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* set overall return value */
status = ret;
8003758: 7cfb ldrb r3, [r7, #19]
800375a: 74bb strb r3, [r7, #18]
#endif /* !STM32L412xx && !STM32L422xx */
#if defined(SWPMI1)
/*-------------------------- SWPMI1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
800375c: 687b ldr r3, [r7, #4]
800375e: 681b ldr r3, [r3, #0]
8003760: f403 4300 and.w r3, r3, #32768 @ 0x8000
8003764: 2b00 cmp r3, #0
8003766: d00a beq.n 800377e <HAL_RCCEx_PeriphCLKConfig+0x5a2>
{
/* Check the parameters */
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
/* Configure the SWPMI1 clock source */
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
8003768: 4b10 ldr r3, [pc, #64] @ (80037ac <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
800376a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800376e: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000
8003772: 687b ldr r3, [r7, #4]
8003774: 6fdb ldr r3, [r3, #124] @ 0x7c
8003776: 490d ldr r1, [pc, #52] @ (80037ac <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003778: 4313 orrs r3, r2
800377a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* SWPMI1 */
#if defined(DFSDM1_Filter0)
/*-------------------------- DFSDM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
800377e: 687b ldr r3, [r7, #4]
8003780: 681b ldr r3, [r3, #0]
8003782: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003786: 2b00 cmp r3, #0
8003788: d00b beq.n 80037a2 <HAL_RCCEx_PeriphCLKConfig+0x5c6>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
/* Configure the DFSDM1 interface clock source */
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
800378a: 4b08 ldr r3, [pc, #32] @ (80037ac <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
800378c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003790: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8003794: 687b ldr r3, [r7, #4]
8003796: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800379a: 4904 ldr r1, [pc, #16] @ (80037ac <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
800379c: 4313 orrs r3, r2
800379e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
}
#endif /* OCTOSPI1 || OCTOSPI2 */
return status;
80037a2: 7cbb ldrb r3, [r7, #18]
}
80037a4: 4618 mov r0, r3
80037a6: 3718 adds r7, #24
80037a8: 46bd mov sp, r7
80037aa: bd80 pop {r7, pc}
80037ac: 40021000 .word 0x40021000
080037b0 <HAL_RCCEx_EnableMSIPLLMode>:
* @note Prior to enable the PLL-mode of the MSI for automatic hardware
* calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
* @retval None
*/
void HAL_RCCEx_EnableMSIPLLMode(void)
{
80037b0: b480 push {r7}
80037b2: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
80037b4: 4b05 ldr r3, [pc, #20] @ (80037cc <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
80037b6: 681b ldr r3, [r3, #0]
80037b8: 4a04 ldr r2, [pc, #16] @ (80037cc <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
80037ba: f043 0304 orr.w r3, r3, #4
80037be: 6013 str r3, [r2, #0]
}
80037c0: bf00 nop
80037c2: 46bd mov sp, r7
80037c4: f85d 7b04 ldr.w r7, [sp], #4
80037c8: 4770 bx lr
80037ca: bf00 nop
80037cc: 40021000 .word 0x40021000
080037d0 <RCCEx_PLLSAI1_Config>:
* @note PLLSAI1 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
80037d0: b580 push {r7, lr}
80037d2: b084 sub sp, #16
80037d4: af00 add r7, sp, #0
80037d6: 6078 str r0, [r7, #4]
80037d8: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
80037da: 2300 movs r3, #0
80037dc: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
/* Check that PLLSAI1 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
80037de: 4b75 ldr r3, [pc, #468] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
80037e0: 68db ldr r3, [r3, #12]
80037e2: f003 0303 and.w r3, r3, #3
80037e6: 2b00 cmp r3, #0
80037e8: d018 beq.n 800381c <RCCEx_PLLSAI1_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
80037ea: 4b72 ldr r3, [pc, #456] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
80037ec: 68db ldr r3, [r3, #12]
80037ee: f003 0203 and.w r2, r3, #3
80037f2: 687b ldr r3, [r7, #4]
80037f4: 681b ldr r3, [r3, #0]
80037f6: 429a cmp r2, r3
80037f8: d10d bne.n 8003816 <RCCEx_PLLSAI1_Config+0x46>
||
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
80037fa: 687b ldr r3, [r7, #4]
80037fc: 681b ldr r3, [r3, #0]
||
80037fe: 2b00 cmp r3, #0
8003800: d009 beq.n 8003816 <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
8003802: 4b6c ldr r3, [pc, #432] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003804: 68db ldr r3, [r3, #12]
8003806: 091b lsrs r3, r3, #4
8003808: f003 0307 and.w r3, r3, #7
800380c: 1c5a adds r2, r3, #1
800380e: 687b ldr r3, [r7, #4]
8003810: 685b ldr r3, [r3, #4]
||
8003812: 429a cmp r2, r3
8003814: d047 beq.n 80038a6 <RCCEx_PLLSAI1_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
8003816: 2301 movs r3, #1
8003818: 73fb strb r3, [r7, #15]
800381a: e044 b.n 80038a6 <RCCEx_PLLSAI1_Config+0xd6>
}
}
else
{
/* Check PLLSAI1 clock source availability */
switch(PllSai1->PLLSAI1Source)
800381c: 687b ldr r3, [r7, #4]
800381e: 681b ldr r3, [r3, #0]
8003820: 2b03 cmp r3, #3
8003822: d018 beq.n 8003856 <RCCEx_PLLSAI1_Config+0x86>
8003824: 2b03 cmp r3, #3
8003826: d825 bhi.n 8003874 <RCCEx_PLLSAI1_Config+0xa4>
8003828: 2b01 cmp r3, #1
800382a: d002 beq.n 8003832 <RCCEx_PLLSAI1_Config+0x62>
800382c: 2b02 cmp r3, #2
800382e: d009 beq.n 8003844 <RCCEx_PLLSAI1_Config+0x74>
8003830: e020 b.n 8003874 <RCCEx_PLLSAI1_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
8003832: 4b60 ldr r3, [pc, #384] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003834: 681b ldr r3, [r3, #0]
8003836: f003 0302 and.w r3, r3, #2
800383a: 2b00 cmp r3, #0
800383c: d11d bne.n 800387a <RCCEx_PLLSAI1_Config+0xaa>
{
status = HAL_ERROR;
800383e: 2301 movs r3, #1
8003840: 73fb strb r3, [r7, #15]
}
break;
8003842: e01a b.n 800387a <RCCEx_PLLSAI1_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
8003844: 4b5b ldr r3, [pc, #364] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003846: 681b ldr r3, [r3, #0]
8003848: f403 6380 and.w r3, r3, #1024 @ 0x400
800384c: 2b00 cmp r3, #0
800384e: d116 bne.n 800387e <RCCEx_PLLSAI1_Config+0xae>
{
status = HAL_ERROR;
8003850: 2301 movs r3, #1
8003852: 73fb strb r3, [r7, #15]
}
break;
8003854: e013 b.n 800387e <RCCEx_PLLSAI1_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
8003856: 4b57 ldr r3, [pc, #348] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003858: 681b ldr r3, [r3, #0]
800385a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800385e: 2b00 cmp r3, #0
8003860: d10f bne.n 8003882 <RCCEx_PLLSAI1_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
8003862: 4b54 ldr r3, [pc, #336] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003864: 681b ldr r3, [r3, #0]
8003866: f403 2380 and.w r3, r3, #262144 @ 0x40000
800386a: 2b00 cmp r3, #0
800386c: d109 bne.n 8003882 <RCCEx_PLLSAI1_Config+0xb2>
{
status = HAL_ERROR;
800386e: 2301 movs r3, #1
8003870: 73fb strb r3, [r7, #15]
}
}
break;
8003872: e006 b.n 8003882 <RCCEx_PLLSAI1_Config+0xb2>
default:
status = HAL_ERROR;
8003874: 2301 movs r3, #1
8003876: 73fb strb r3, [r7, #15]
break;
8003878: e004 b.n 8003884 <RCCEx_PLLSAI1_Config+0xb4>
break;
800387a: bf00 nop
800387c: e002 b.n 8003884 <RCCEx_PLLSAI1_Config+0xb4>
break;
800387e: bf00 nop
8003880: e000 b.n 8003884 <RCCEx_PLLSAI1_Config+0xb4>
break;
8003882: bf00 nop
}
if(status == HAL_OK)
8003884: 7bfb ldrb r3, [r7, #15]
8003886: 2b00 cmp r3, #0
8003888: d10d bne.n 80038a6 <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
/* Set PLLSAI1 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
/* Set PLLSAI1 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
800388a: 4b4a ldr r3, [pc, #296] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
800388c: 68db ldr r3, [r3, #12]
800388e: f023 0273 bic.w r2, r3, #115 @ 0x73
8003892: 687b ldr r3, [r7, #4]
8003894: 6819 ldr r1, [r3, #0]
8003896: 687b ldr r3, [r7, #4]
8003898: 685b ldr r3, [r3, #4]
800389a: 3b01 subs r3, #1
800389c: 011b lsls r3, r3, #4
800389e: 430b orrs r3, r1
80038a0: 4944 ldr r1, [pc, #272] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
80038a2: 4313 orrs r3, r2
80038a4: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
80038a6: 7bfb ldrb r3, [r7, #15]
80038a8: 2b00 cmp r3, #0
80038aa: d17d bne.n 80039a8 <RCCEx_PLLSAI1_Config+0x1d8>
{
/* Disable the PLLSAI1 */
__HAL_RCC_PLLSAI1_DISABLE();
80038ac: 4b41 ldr r3, [pc, #260] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
80038ae: 681b ldr r3, [r3, #0]
80038b0: 4a40 ldr r2, [pc, #256] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
80038b2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
80038b6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80038b8: f7fd fea0 bl 80015fc <HAL_GetTick>
80038bc: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
80038be: e009 b.n 80038d4 <RCCEx_PLLSAI1_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
80038c0: f7fd fe9c bl 80015fc <HAL_GetTick>
80038c4: 4602 mov r2, r0
80038c6: 68bb ldr r3, [r7, #8]
80038c8: 1ad3 subs r3, r2, r3
80038ca: 2b02 cmp r3, #2
80038cc: d902 bls.n 80038d4 <RCCEx_PLLSAI1_Config+0x104>
{
status = HAL_TIMEOUT;
80038ce: 2303 movs r3, #3
80038d0: 73fb strb r3, [r7, #15]
break;
80038d2: e005 b.n 80038e0 <RCCEx_PLLSAI1_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
80038d4: 4b37 ldr r3, [pc, #220] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
80038d6: 681b ldr r3, [r3, #0]
80038d8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
80038dc: 2b00 cmp r3, #0
80038de: d1ef bne.n 80038c0 <RCCEx_PLLSAI1_Config+0xf0>
}
}
if(status == HAL_OK)
80038e0: 7bfb ldrb r3, [r7, #15]
80038e2: 2b00 cmp r3, #0
80038e4: d160 bne.n 80039a8 <RCCEx_PLLSAI1_Config+0x1d8>
{
if(Divider == DIVIDER_P_UPDATE)
80038e6: 683b ldr r3, [r7, #0]
80038e8: 2b00 cmp r3, #0
80038ea: d111 bne.n 8003910 <RCCEx_PLLSAI1_Config+0x140>
MODIFY_REG(RCC->PLLSAI1CFGR,
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI1CFGR,
80038ec: 4b31 ldr r3, [pc, #196] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
80038ee: 691b ldr r3, [r3, #16]
80038f0: f423 331f bic.w r3, r3, #162816 @ 0x27c00
80038f4: f423 7340 bic.w r3, r3, #768 @ 0x300
80038f8: 687a ldr r2, [r7, #4]
80038fa: 6892 ldr r2, [r2, #8]
80038fc: 0211 lsls r1, r2, #8
80038fe: 687a ldr r2, [r7, #4]
8003900: 68d2 ldr r2, [r2, #12]
8003902: 0912 lsrs r2, r2, #4
8003904: 0452 lsls r2, r2, #17
8003906: 430a orrs r2, r1
8003908: 492a ldr r1, [pc, #168] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
800390a: 4313 orrs r3, r2
800390c: 610b str r3, [r1, #16]
800390e: e027 b.n 8003960 <RCCEx_PLLSAI1_Config+0x190>
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
else if(Divider == DIVIDER_Q_UPDATE)
8003910: 683b ldr r3, [r7, #0]
8003912: 2b01 cmp r3, #1
8003914: d112 bne.n 800393c <RCCEx_PLLSAI1_Config+0x16c>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
8003916: 4b27 ldr r3, [pc, #156] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003918: 691b ldr r3, [r3, #16]
800391a: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000
800391e: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
8003922: 687a ldr r2, [r7, #4]
8003924: 6892 ldr r2, [r2, #8]
8003926: 0211 lsls r1, r2, #8
8003928: 687a ldr r2, [r7, #4]
800392a: 6912 ldr r2, [r2, #16]
800392c: 0852 lsrs r2, r2, #1
800392e: 3a01 subs r2, #1
8003930: 0552 lsls r2, r2, #21
8003932: 430a orrs r2, r1
8003934: 491f ldr r1, [pc, #124] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003936: 4313 orrs r3, r2
8003938: 610b str r3, [r1, #16]
800393a: e011 b.n 8003960 <RCCEx_PLLSAI1_Config+0x190>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
800393c: 4b1d ldr r3, [pc, #116] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
800393e: 691b ldr r3, [r3, #16]
8003940: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
8003944: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
8003948: 687a ldr r2, [r7, #4]
800394a: 6892 ldr r2, [r2, #8]
800394c: 0211 lsls r1, r2, #8
800394e: 687a ldr r2, [r7, #4]
8003950: 6952 ldr r2, [r2, #20]
8003952: 0852 lsrs r2, r2, #1
8003954: 3a01 subs r2, #1
8003956: 0652 lsls r2, r2, #25
8003958: 430a orrs r2, r1
800395a: 4916 ldr r1, [pc, #88] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
800395c: 4313 orrs r3, r2
800395e: 610b str r3, [r1, #16]
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
__HAL_RCC_PLLSAI1_ENABLE();
8003960: 4b14 ldr r3, [pc, #80] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003962: 681b ldr r3, [r3, #0]
8003964: 4a13 ldr r2, [pc, #76] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
8003966: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
800396a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800396c: f7fd fe46 bl 80015fc <HAL_GetTick>
8003970: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
8003972: e009 b.n 8003988 <RCCEx_PLLSAI1_Config+0x1b8>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
8003974: f7fd fe42 bl 80015fc <HAL_GetTick>
8003978: 4602 mov r2, r0
800397a: 68bb ldr r3, [r7, #8]
800397c: 1ad3 subs r3, r2, r3
800397e: 2b02 cmp r3, #2
8003980: d902 bls.n 8003988 <RCCEx_PLLSAI1_Config+0x1b8>
{
status = HAL_TIMEOUT;
8003982: 2303 movs r3, #3
8003984: 73fb strb r3, [r7, #15]
break;
8003986: e005 b.n 8003994 <RCCEx_PLLSAI1_Config+0x1c4>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
8003988: 4b0a ldr r3, [pc, #40] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
800398a: 681b ldr r3, [r3, #0]
800398c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8003990: 2b00 cmp r3, #0
8003992: d0ef beq.n 8003974 <RCCEx_PLLSAI1_Config+0x1a4>
}
}
if(status == HAL_OK)
8003994: 7bfb ldrb r3, [r7, #15]
8003996: 2b00 cmp r3, #0
8003998: d106 bne.n 80039a8 <RCCEx_PLLSAI1_Config+0x1d8>
{
/* Configure the PLLSAI1 Clock output(s) */
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
800399a: 4b06 ldr r3, [pc, #24] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
800399c: 691a ldr r2, [r3, #16]
800399e: 687b ldr r3, [r7, #4]
80039a0: 699b ldr r3, [r3, #24]
80039a2: 4904 ldr r1, [pc, #16] @ (80039b4 <RCCEx_PLLSAI1_Config+0x1e4>)
80039a4: 4313 orrs r3, r2
80039a6: 610b str r3, [r1, #16]
}
}
}
return status;
80039a8: 7bfb ldrb r3, [r7, #15]
}
80039aa: 4618 mov r0, r3
80039ac: 3710 adds r7, #16
80039ae: 46bd mov sp, r7
80039b0: bd80 pop {r7, pc}
80039b2: bf00 nop
80039b4: 40021000 .word 0x40021000
080039b8 <RCCEx_PLLSAI2_Config>:
* @note PLLSAI2 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
{
80039b8: b580 push {r7, lr}
80039ba: b084 sub sp, #16
80039bc: af00 add r7, sp, #0
80039be: 6078 str r0, [r7, #4]
80039c0: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
80039c2: 2300 movs r3, #0
80039c4: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
/* Check that PLLSAI2 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
80039c6: 4b6a ldr r3, [pc, #424] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
80039c8: 68db ldr r3, [r3, #12]
80039ca: f003 0303 and.w r3, r3, #3
80039ce: 2b00 cmp r3, #0
80039d0: d018 beq.n 8003a04 <RCCEx_PLLSAI2_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
80039d2: 4b67 ldr r3, [pc, #412] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
80039d4: 68db ldr r3, [r3, #12]
80039d6: f003 0203 and.w r2, r3, #3
80039da: 687b ldr r3, [r7, #4]
80039dc: 681b ldr r3, [r3, #0]
80039de: 429a cmp r2, r3
80039e0: d10d bne.n 80039fe <RCCEx_PLLSAI2_Config+0x46>
||
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
80039e2: 687b ldr r3, [r7, #4]
80039e4: 681b ldr r3, [r3, #0]
||
80039e6: 2b00 cmp r3, #0
80039e8: d009 beq.n 80039fe <RCCEx_PLLSAI2_Config+0x46>
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
80039ea: 4b61 ldr r3, [pc, #388] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
80039ec: 68db ldr r3, [r3, #12]
80039ee: 091b lsrs r3, r3, #4
80039f0: f003 0307 and.w r3, r3, #7
80039f4: 1c5a adds r2, r3, #1
80039f6: 687b ldr r3, [r7, #4]
80039f8: 685b ldr r3, [r3, #4]
||
80039fa: 429a cmp r2, r3
80039fc: d047 beq.n 8003a8e <RCCEx_PLLSAI2_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
80039fe: 2301 movs r3, #1
8003a00: 73fb strb r3, [r7, #15]
8003a02: e044 b.n 8003a8e <RCCEx_PLLSAI2_Config+0xd6>
}
}
else
{
/* Check PLLSAI2 clock source availability */
switch(PllSai2->PLLSAI2Source)
8003a04: 687b ldr r3, [r7, #4]
8003a06: 681b ldr r3, [r3, #0]
8003a08: 2b03 cmp r3, #3
8003a0a: d018 beq.n 8003a3e <RCCEx_PLLSAI2_Config+0x86>
8003a0c: 2b03 cmp r3, #3
8003a0e: d825 bhi.n 8003a5c <RCCEx_PLLSAI2_Config+0xa4>
8003a10: 2b01 cmp r3, #1
8003a12: d002 beq.n 8003a1a <RCCEx_PLLSAI2_Config+0x62>
8003a14: 2b02 cmp r3, #2
8003a16: d009 beq.n 8003a2c <RCCEx_PLLSAI2_Config+0x74>
8003a18: e020 b.n 8003a5c <RCCEx_PLLSAI2_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
8003a1a: 4b55 ldr r3, [pc, #340] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003a1c: 681b ldr r3, [r3, #0]
8003a1e: f003 0302 and.w r3, r3, #2
8003a22: 2b00 cmp r3, #0
8003a24: d11d bne.n 8003a62 <RCCEx_PLLSAI2_Config+0xaa>
{
status = HAL_ERROR;
8003a26: 2301 movs r3, #1
8003a28: 73fb strb r3, [r7, #15]
}
break;
8003a2a: e01a b.n 8003a62 <RCCEx_PLLSAI2_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
8003a2c: 4b50 ldr r3, [pc, #320] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003a2e: 681b ldr r3, [r3, #0]
8003a30: f403 6380 and.w r3, r3, #1024 @ 0x400
8003a34: 2b00 cmp r3, #0
8003a36: d116 bne.n 8003a66 <RCCEx_PLLSAI2_Config+0xae>
{
status = HAL_ERROR;
8003a38: 2301 movs r3, #1
8003a3a: 73fb strb r3, [r7, #15]
}
break;
8003a3c: e013 b.n 8003a66 <RCCEx_PLLSAI2_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
8003a3e: 4b4c ldr r3, [pc, #304] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003a40: 681b ldr r3, [r3, #0]
8003a42: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003a46: 2b00 cmp r3, #0
8003a48: d10f bne.n 8003a6a <RCCEx_PLLSAI2_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
8003a4a: 4b49 ldr r3, [pc, #292] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003a4c: 681b ldr r3, [r3, #0]
8003a4e: f403 2380 and.w r3, r3, #262144 @ 0x40000
8003a52: 2b00 cmp r3, #0
8003a54: d109 bne.n 8003a6a <RCCEx_PLLSAI2_Config+0xb2>
{
status = HAL_ERROR;
8003a56: 2301 movs r3, #1
8003a58: 73fb strb r3, [r7, #15]
}
}
break;
8003a5a: e006 b.n 8003a6a <RCCEx_PLLSAI2_Config+0xb2>
default:
status = HAL_ERROR;
8003a5c: 2301 movs r3, #1
8003a5e: 73fb strb r3, [r7, #15]
break;
8003a60: e004 b.n 8003a6c <RCCEx_PLLSAI2_Config+0xb4>
break;
8003a62: bf00 nop
8003a64: e002 b.n 8003a6c <RCCEx_PLLSAI2_Config+0xb4>
break;
8003a66: bf00 nop
8003a68: e000 b.n 8003a6c <RCCEx_PLLSAI2_Config+0xb4>
break;
8003a6a: bf00 nop
}
if(status == HAL_OK)
8003a6c: 7bfb ldrb r3, [r7, #15]
8003a6e: 2b00 cmp r3, #0
8003a70: d10d bne.n 8003a8e <RCCEx_PLLSAI2_Config+0xd6>
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
/* Set PLLSAI2 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
#else
/* Set PLLSAI2 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
8003a72: 4b3f ldr r3, [pc, #252] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003a74: 68db ldr r3, [r3, #12]
8003a76: f023 0273 bic.w r2, r3, #115 @ 0x73
8003a7a: 687b ldr r3, [r7, #4]
8003a7c: 6819 ldr r1, [r3, #0]
8003a7e: 687b ldr r3, [r7, #4]
8003a80: 685b ldr r3, [r3, #4]
8003a82: 3b01 subs r3, #1
8003a84: 011b lsls r3, r3, #4
8003a86: 430b orrs r3, r1
8003a88: 4939 ldr r1, [pc, #228] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003a8a: 4313 orrs r3, r2
8003a8c: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
8003a8e: 7bfb ldrb r3, [r7, #15]
8003a90: 2b00 cmp r3, #0
8003a92: d167 bne.n 8003b64 <RCCEx_PLLSAI2_Config+0x1ac>
{
/* Disable the PLLSAI2 */
__HAL_RCC_PLLSAI2_DISABLE();
8003a94: 4b36 ldr r3, [pc, #216] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003a96: 681b ldr r3, [r3, #0]
8003a98: 4a35 ldr r2, [pc, #212] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003a9a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8003a9e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003aa0: f7fd fdac bl 80015fc <HAL_GetTick>
8003aa4: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI2 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
8003aa6: e009 b.n 8003abc <RCCEx_PLLSAI2_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
8003aa8: f7fd fda8 bl 80015fc <HAL_GetTick>
8003aac: 4602 mov r2, r0
8003aae: 68bb ldr r3, [r7, #8]
8003ab0: 1ad3 subs r3, r2, r3
8003ab2: 2b02 cmp r3, #2
8003ab4: d902 bls.n 8003abc <RCCEx_PLLSAI2_Config+0x104>
{
status = HAL_TIMEOUT;
8003ab6: 2303 movs r3, #3
8003ab8: 73fb strb r3, [r7, #15]
break;
8003aba: e005 b.n 8003ac8 <RCCEx_PLLSAI2_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
8003abc: 4b2c ldr r3, [pc, #176] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003abe: 681b ldr r3, [r3, #0]
8003ac0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8003ac4: 2b00 cmp r3, #0
8003ac6: d1ef bne.n 8003aa8 <RCCEx_PLLSAI2_Config+0xf0>
}
}
if(status == HAL_OK)
8003ac8: 7bfb ldrb r3, [r7, #15]
8003aca: 2b00 cmp r3, #0
8003acc: d14a bne.n 8003b64 <RCCEx_PLLSAI2_Config+0x1ac>
{
if(Divider == DIVIDER_P_UPDATE)
8003ace: 683b ldr r3, [r7, #0]
8003ad0: 2b00 cmp r3, #0
8003ad2: d111 bne.n 8003af8 <RCCEx_PLLSAI2_Config+0x140>
MODIFY_REG(RCC->PLLSAI2CFGR,
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI2CFGR,
8003ad4: 4b26 ldr r3, [pc, #152] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003ad6: 695b ldr r3, [r3, #20]
8003ad8: f423 331f bic.w r3, r3, #162816 @ 0x27c00
8003adc: f423 7340 bic.w r3, r3, #768 @ 0x300
8003ae0: 687a ldr r2, [r7, #4]
8003ae2: 6892 ldr r2, [r2, #8]
8003ae4: 0211 lsls r1, r2, #8
8003ae6: 687a ldr r2, [r7, #4]
8003ae8: 68d2 ldr r2, [r2, #12]
8003aea: 0912 lsrs r2, r2, #4
8003aec: 0452 lsls r2, r2, #17
8003aee: 430a orrs r2, r1
8003af0: 491f ldr r1, [pc, #124] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003af2: 4313 orrs r3, r2
8003af4: 614b str r3, [r1, #20]
8003af6: e011 b.n 8003b1c <RCCEx_PLLSAI2_Config+0x164>
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
#else
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI2CFGR,
8003af8: 4b1d ldr r3, [pc, #116] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003afa: 695b ldr r3, [r3, #20]
8003afc: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
8003b00: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
8003b04: 687a ldr r2, [r7, #4]
8003b06: 6892 ldr r2, [r2, #8]
8003b08: 0211 lsls r1, r2, #8
8003b0a: 687a ldr r2, [r7, #4]
8003b0c: 6912 ldr r2, [r2, #16]
8003b0e: 0852 lsrs r2, r2, #1
8003b10: 3a01 subs r2, #1
8003b12: 0652 lsls r2, r2, #25
8003b14: 430a orrs r2, r1
8003b16: 4916 ldr r1, [pc, #88] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003b18: 4313 orrs r3, r2
8003b1a: 614b str r3, [r1, #20]
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
__HAL_RCC_PLLSAI2_ENABLE();
8003b1c: 4b14 ldr r3, [pc, #80] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003b1e: 681b ldr r3, [r3, #0]
8003b20: 4a13 ldr r2, [pc, #76] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003b22: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003b26: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003b28: f7fd fd68 bl 80015fc <HAL_GetTick>
8003b2c: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI2 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
8003b2e: e009 b.n 8003b44 <RCCEx_PLLSAI2_Config+0x18c>
{
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
8003b30: f7fd fd64 bl 80015fc <HAL_GetTick>
8003b34: 4602 mov r2, r0
8003b36: 68bb ldr r3, [r7, #8]
8003b38: 1ad3 subs r3, r2, r3
8003b3a: 2b02 cmp r3, #2
8003b3c: d902 bls.n 8003b44 <RCCEx_PLLSAI2_Config+0x18c>
{
status = HAL_TIMEOUT;
8003b3e: 2303 movs r3, #3
8003b40: 73fb strb r3, [r7, #15]
break;
8003b42: e005 b.n 8003b50 <RCCEx_PLLSAI2_Config+0x198>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
8003b44: 4b0a ldr r3, [pc, #40] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003b46: 681b ldr r3, [r3, #0]
8003b48: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8003b4c: 2b00 cmp r3, #0
8003b4e: d0ef beq.n 8003b30 <RCCEx_PLLSAI2_Config+0x178>
}
}
if(status == HAL_OK)
8003b50: 7bfb ldrb r3, [r7, #15]
8003b52: 2b00 cmp r3, #0
8003b54: d106 bne.n 8003b64 <RCCEx_PLLSAI2_Config+0x1ac>
{
/* Configure the PLLSAI2 Clock output(s) */
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
8003b56: 4b06 ldr r3, [pc, #24] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003b58: 695a ldr r2, [r3, #20]
8003b5a: 687b ldr r3, [r7, #4]
8003b5c: 695b ldr r3, [r3, #20]
8003b5e: 4904 ldr r1, [pc, #16] @ (8003b70 <RCCEx_PLLSAI2_Config+0x1b8>)
8003b60: 4313 orrs r3, r2
8003b62: 614b str r3, [r1, #20]
}
}
}
return status;
8003b64: 7bfb ldrb r3, [r7, #15]
}
8003b66: 4618 mov r0, r3
8003b68: 3710 adds r7, #16
8003b6a: 46bd mov sp, r7
8003b6c: bd80 pop {r7, pc}
8003b6e: bf00 nop
8003b70: 40021000 .word 0x40021000
08003b74 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8003b74: b580 push {r7, lr}
8003b76: b084 sub sp, #16
8003b78: af00 add r7, sp, #0
8003b7a: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
8003b7c: 687b ldr r3, [r7, #4]
8003b7e: 2b00 cmp r3, #0
8003b80: d101 bne.n 8003b86 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8003b82: 2301 movs r3, #1
8003b84: e095 b.n 8003cb2 <HAL_SPI_Init+0x13e>
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8003b86: 687b ldr r3, [r7, #4]
8003b88: 6a5b ldr r3, [r3, #36] @ 0x24
8003b8a: 2b00 cmp r3, #0
8003b8c: d108 bne.n 8003ba0 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8003b8e: 687b ldr r3, [r7, #4]
8003b90: 685b ldr r3, [r3, #4]
8003b92: f5b3 7f82 cmp.w r3, #260 @ 0x104
8003b96: d009 beq.n 8003bac <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8003b98: 687b ldr r3, [r7, #4]
8003b9a: 2200 movs r2, #0
8003b9c: 61da str r2, [r3, #28]
8003b9e: e005 b.n 8003bac <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8003ba0: 687b ldr r3, [r7, #4]
8003ba2: 2200 movs r2, #0
8003ba4: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8003ba6: 687b ldr r3, [r7, #4]
8003ba8: 2200 movs r2, #0
8003baa: 615a str r2, [r3, #20]
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003bac: 687b ldr r3, [r7, #4]
8003bae: 2200 movs r2, #0
8003bb0: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8003bb2: 687b ldr r3, [r7, #4]
8003bb4: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
8003bb8: b2db uxtb r3, r3
8003bba: 2b00 cmp r3, #0
8003bbc: d106 bne.n 8003bcc <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8003bbe: 687b ldr r3, [r7, #4]
8003bc0: 2200 movs r2, #0
8003bc2: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8003bc6: 6878 ldr r0, [r7, #4]
8003bc8: f7fd fa98 bl 80010fc <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8003bcc: 687b ldr r3, [r7, #4]
8003bce: 2202 movs r2, #2
8003bd0: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8003bd4: 687b ldr r3, [r7, #4]
8003bd6: 681b ldr r3, [r3, #0]
8003bd8: 681a ldr r2, [r3, #0]
8003bda: 687b ldr r3, [r7, #4]
8003bdc: 681b ldr r3, [r3, #0]
8003bde: f022 0240 bic.w r2, r2, #64 @ 0x40
8003be2: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8003be4: 687b ldr r3, [r7, #4]
8003be6: 68db ldr r3, [r3, #12]
8003be8: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
8003bec: d902 bls.n 8003bf4 <HAL_SPI_Init+0x80>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
8003bee: 2300 movs r3, #0
8003bf0: 60fb str r3, [r7, #12]
8003bf2: e002 b.n 8003bfa <HAL_SPI_Init+0x86>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
8003bf4: f44f 5380 mov.w r3, #4096 @ 0x1000
8003bf8: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
8003bfa: 687b ldr r3, [r7, #4]
8003bfc: 68db ldr r3, [r3, #12]
8003bfe: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
8003c02: d007 beq.n 8003c14 <HAL_SPI_Init+0xa0>
8003c04: 687b ldr r3, [r7, #4]
8003c06: 68db ldr r3, [r3, #12]
8003c08: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
8003c0c: d002 beq.n 8003c14 <HAL_SPI_Init+0xa0>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003c0e: 687b ldr r3, [r7, #4]
8003c10: 2200 movs r2, #0
8003c12: 629a str r2, [r3, #40] @ 0x28
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
8003c14: 687b ldr r3, [r7, #4]
8003c16: 685b ldr r3, [r3, #4]
8003c18: f403 7282 and.w r2, r3, #260 @ 0x104
8003c1c: 687b ldr r3, [r7, #4]
8003c1e: 689b ldr r3, [r3, #8]
8003c20: f403 4304 and.w r3, r3, #33792 @ 0x8400
8003c24: 431a orrs r2, r3
8003c26: 687b ldr r3, [r7, #4]
8003c28: 691b ldr r3, [r3, #16]
8003c2a: f003 0302 and.w r3, r3, #2
8003c2e: 431a orrs r2, r3
8003c30: 687b ldr r3, [r7, #4]
8003c32: 695b ldr r3, [r3, #20]
8003c34: f003 0301 and.w r3, r3, #1
8003c38: 431a orrs r2, r3
8003c3a: 687b ldr r3, [r7, #4]
8003c3c: 699b ldr r3, [r3, #24]
8003c3e: f403 7300 and.w r3, r3, #512 @ 0x200
8003c42: 431a orrs r2, r3
8003c44: 687b ldr r3, [r7, #4]
8003c46: 69db ldr r3, [r3, #28]
8003c48: f003 0338 and.w r3, r3, #56 @ 0x38
8003c4c: 431a orrs r2, r3
8003c4e: 687b ldr r3, [r7, #4]
8003c50: 6a1b ldr r3, [r3, #32]
8003c52: f003 0380 and.w r3, r3, #128 @ 0x80
8003c56: ea42 0103 orr.w r1, r2, r3
8003c5a: 687b ldr r3, [r7, #4]
8003c5c: 6a9b ldr r3, [r3, #40] @ 0x28
8003c5e: f403 5200 and.w r2, r3, #8192 @ 0x2000
8003c62: 687b ldr r3, [r7, #4]
8003c64: 681b ldr r3, [r3, #0]
8003c66: 430a orrs r2, r1
8003c68: 601a str r2, [r3, #0]
}
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
8003c6a: 687b ldr r3, [r7, #4]
8003c6c: 699b ldr r3, [r3, #24]
8003c6e: 0c1b lsrs r3, r3, #16
8003c70: f003 0204 and.w r2, r3, #4
8003c74: 687b ldr r3, [r7, #4]
8003c76: 6a5b ldr r3, [r3, #36] @ 0x24
8003c78: f003 0310 and.w r3, r3, #16
8003c7c: 431a orrs r2, r3
8003c7e: 687b ldr r3, [r7, #4]
8003c80: 6b5b ldr r3, [r3, #52] @ 0x34
8003c82: f003 0308 and.w r3, r3, #8
8003c86: 431a orrs r2, r3
8003c88: 687b ldr r3, [r7, #4]
8003c8a: 68db ldr r3, [r3, #12]
8003c8c: f403 6370 and.w r3, r3, #3840 @ 0xf00
8003c90: ea42 0103 orr.w r1, r2, r3
8003c94: 68fb ldr r3, [r7, #12]
8003c96: f403 5280 and.w r2, r3, #4096 @ 0x1000
8003c9a: 687b ldr r3, [r7, #4]
8003c9c: 681b ldr r3, [r3, #0]
8003c9e: 430a orrs r2, r1
8003ca0: 605a str r2, [r3, #4]
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8003ca2: 687b ldr r3, [r7, #4]
8003ca4: 2200 movs r2, #0
8003ca6: 661a str r2, [r3, #96] @ 0x60
hspi->State = HAL_SPI_STATE_READY;
8003ca8: 687b ldr r3, [r7, #4]
8003caa: 2201 movs r2, #1
8003cac: f883 205d strb.w r2, [r3, #93] @ 0x5d
return HAL_OK;
8003cb0: 2300 movs r3, #0
}
8003cb2: 4618 mov r0, r3
8003cb4: 3710 adds r7, #16
8003cb6: 46bd mov sp, r7
8003cb8: bd80 pop {r7, pc}
08003cba <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8003cba: b580 push {r7, lr}
8003cbc: b082 sub sp, #8
8003cbe: af00 add r7, sp, #0
8003cc0: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8003cc2: 687b ldr r3, [r7, #4]
8003cc4: 2b00 cmp r3, #0
8003cc6: d101 bne.n 8003ccc <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8003cc8: 2301 movs r3, #1
8003cca: e040 b.n 8003d4e <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
8003ccc: 687b ldr r3, [r7, #4]
8003cce: 6fdb ldr r3, [r3, #124] @ 0x7c
8003cd0: 2b00 cmp r3, #0
8003cd2: d106 bne.n 8003ce2 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8003cd4: 687b ldr r3, [r7, #4]
8003cd6: 2200 movs r2, #0
8003cd8: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8003cdc: 6878 ldr r0, [r7, #4]
8003cde: f7fd fa51 bl 8001184 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8003ce2: 687b ldr r3, [r7, #4]
8003ce4: 2224 movs r2, #36 @ 0x24
8003ce6: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
8003ce8: 687b ldr r3, [r7, #4]
8003cea: 681b ldr r3, [r3, #0]
8003cec: 681a ldr r2, [r3, #0]
8003cee: 687b ldr r3, [r7, #4]
8003cf0: 681b ldr r3, [r3, #0]
8003cf2: f022 0201 bic.w r2, r2, #1
8003cf6: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8003cf8: 687b ldr r3, [r7, #4]
8003cfa: 6a5b ldr r3, [r3, #36] @ 0x24
8003cfc: 2b00 cmp r3, #0
8003cfe: d002 beq.n 8003d06 <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
8003d00: 6878 ldr r0, [r7, #4]
8003d02: f000 fae1 bl 80042c8 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8003d06: 6878 ldr r0, [r7, #4]
8003d08: f000 f826 bl 8003d58 <UART_SetConfig>
8003d0c: 4603 mov r3, r0
8003d0e: 2b01 cmp r3, #1
8003d10: d101 bne.n 8003d16 <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
8003d12: 2301 movs r3, #1
8003d14: e01b b.n 8003d4e <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8003d16: 687b ldr r3, [r7, #4]
8003d18: 681b ldr r3, [r3, #0]
8003d1a: 685a ldr r2, [r3, #4]
8003d1c: 687b ldr r3, [r7, #4]
8003d1e: 681b ldr r3, [r3, #0]
8003d20: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8003d24: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8003d26: 687b ldr r3, [r7, #4]
8003d28: 681b ldr r3, [r3, #0]
8003d2a: 689a ldr r2, [r3, #8]
8003d2c: 687b ldr r3, [r7, #4]
8003d2e: 681b ldr r3, [r3, #0]
8003d30: f022 022a bic.w r2, r2, #42 @ 0x2a
8003d34: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8003d36: 687b ldr r3, [r7, #4]
8003d38: 681b ldr r3, [r3, #0]
8003d3a: 681a ldr r2, [r3, #0]
8003d3c: 687b ldr r3, [r7, #4]
8003d3e: 681b ldr r3, [r3, #0]
8003d40: f042 0201 orr.w r2, r2, #1
8003d44: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8003d46: 6878 ldr r0, [r7, #4]
8003d48: f000 fb60 bl 800440c <UART_CheckIdleState>
8003d4c: 4603 mov r3, r0
}
8003d4e: 4618 mov r0, r3
8003d50: 3708 adds r7, #8
8003d52: 46bd mov sp, r7
8003d54: bd80 pop {r7, pc}
...
08003d58 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8003d58: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8003d5c: b08a sub sp, #40 @ 0x28
8003d5e: af00 add r7, sp, #0
8003d60: 60f8 str r0, [r7, #12]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8003d62: 2300 movs r3, #0
8003d64: f887 3022 strb.w r3, [r7, #34] @ 0x22
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8003d68: 68fb ldr r3, [r7, #12]
8003d6a: 689a ldr r2, [r3, #8]
8003d6c: 68fb ldr r3, [r7, #12]
8003d6e: 691b ldr r3, [r3, #16]
8003d70: 431a orrs r2, r3
8003d72: 68fb ldr r3, [r7, #12]
8003d74: 695b ldr r3, [r3, #20]
8003d76: 431a orrs r2, r3
8003d78: 68fb ldr r3, [r7, #12]
8003d7a: 69db ldr r3, [r3, #28]
8003d7c: 4313 orrs r3, r2
8003d7e: 627b str r3, [r7, #36] @ 0x24
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8003d80: 68fb ldr r3, [r7, #12]
8003d82: 681b ldr r3, [r3, #0]
8003d84: 681a ldr r2, [r3, #0]
8003d86: 4ba4 ldr r3, [pc, #656] @ (8004018 <UART_SetConfig+0x2c0>)
8003d88: 4013 ands r3, r2
8003d8a: 68fa ldr r2, [r7, #12]
8003d8c: 6812 ldr r2, [r2, #0]
8003d8e: 6a79 ldr r1, [r7, #36] @ 0x24
8003d90: 430b orrs r3, r1
8003d92: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8003d94: 68fb ldr r3, [r7, #12]
8003d96: 681b ldr r3, [r3, #0]
8003d98: 685b ldr r3, [r3, #4]
8003d9a: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8003d9e: 68fb ldr r3, [r7, #12]
8003da0: 68da ldr r2, [r3, #12]
8003da2: 68fb ldr r3, [r7, #12]
8003da4: 681b ldr r3, [r3, #0]
8003da6: 430a orrs r2, r1
8003da8: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8003daa: 68fb ldr r3, [r7, #12]
8003dac: 699b ldr r3, [r3, #24]
8003dae: 627b str r3, [r7, #36] @ 0x24
if (!(UART_INSTANCE_LOWPOWER(huart)))
8003db0: 68fb ldr r3, [r7, #12]
8003db2: 681b ldr r3, [r3, #0]
8003db4: 4a99 ldr r2, [pc, #612] @ (800401c <UART_SetConfig+0x2c4>)
8003db6: 4293 cmp r3, r2
8003db8: d004 beq.n 8003dc4 <UART_SetConfig+0x6c>
{
tmpreg |= huart->Init.OneBitSampling;
8003dba: 68fb ldr r3, [r7, #12]
8003dbc: 6a1b ldr r3, [r3, #32]
8003dbe: 6a7a ldr r2, [r7, #36] @ 0x24
8003dc0: 4313 orrs r3, r2
8003dc2: 627b str r3, [r7, #36] @ 0x24
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8003dc4: 68fb ldr r3, [r7, #12]
8003dc6: 681b ldr r3, [r3, #0]
8003dc8: 689b ldr r3, [r3, #8]
8003dca: f423 6130 bic.w r1, r3, #2816 @ 0xb00
8003dce: 68fb ldr r3, [r7, #12]
8003dd0: 681b ldr r3, [r3, #0]
8003dd2: 6a7a ldr r2, [r7, #36] @ 0x24
8003dd4: 430a orrs r2, r1
8003dd6: 609a str r2, [r3, #8]
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
#endif /* USART_PRESC_PRESCALER */
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8003dd8: 68fb ldr r3, [r7, #12]
8003dda: 681b ldr r3, [r3, #0]
8003ddc: 4a90 ldr r2, [pc, #576] @ (8004020 <UART_SetConfig+0x2c8>)
8003dde: 4293 cmp r3, r2
8003de0: d126 bne.n 8003e30 <UART_SetConfig+0xd8>
8003de2: 4b90 ldr r3, [pc, #576] @ (8004024 <UART_SetConfig+0x2cc>)
8003de4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003de8: f003 0303 and.w r3, r3, #3
8003dec: 2b03 cmp r3, #3
8003dee: d81b bhi.n 8003e28 <UART_SetConfig+0xd0>
8003df0: a201 add r2, pc, #4 @ (adr r2, 8003df8 <UART_SetConfig+0xa0>)
8003df2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003df6: bf00 nop
8003df8: 08003e09 .word 0x08003e09
8003dfc: 08003e19 .word 0x08003e19
8003e00: 08003e11 .word 0x08003e11
8003e04: 08003e21 .word 0x08003e21
8003e08: 2301 movs r3, #1
8003e0a: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003e0e: e116 b.n 800403e <UART_SetConfig+0x2e6>
8003e10: 2302 movs r3, #2
8003e12: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003e16: e112 b.n 800403e <UART_SetConfig+0x2e6>
8003e18: 2304 movs r3, #4
8003e1a: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003e1e: e10e b.n 800403e <UART_SetConfig+0x2e6>
8003e20: 2308 movs r3, #8
8003e22: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003e26: e10a b.n 800403e <UART_SetConfig+0x2e6>
8003e28: 2310 movs r3, #16
8003e2a: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003e2e: e106 b.n 800403e <UART_SetConfig+0x2e6>
8003e30: 68fb ldr r3, [r7, #12]
8003e32: 681b ldr r3, [r3, #0]
8003e34: 4a7c ldr r2, [pc, #496] @ (8004028 <UART_SetConfig+0x2d0>)
8003e36: 4293 cmp r3, r2
8003e38: d138 bne.n 8003eac <UART_SetConfig+0x154>
8003e3a: 4b7a ldr r3, [pc, #488] @ (8004024 <UART_SetConfig+0x2cc>)
8003e3c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003e40: f003 030c and.w r3, r3, #12
8003e44: 2b0c cmp r3, #12
8003e46: d82d bhi.n 8003ea4 <UART_SetConfig+0x14c>
8003e48: a201 add r2, pc, #4 @ (adr r2, 8003e50 <UART_SetConfig+0xf8>)
8003e4a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003e4e: bf00 nop
8003e50: 08003e85 .word 0x08003e85
8003e54: 08003ea5 .word 0x08003ea5
8003e58: 08003ea5 .word 0x08003ea5
8003e5c: 08003ea5 .word 0x08003ea5
8003e60: 08003e95 .word 0x08003e95
8003e64: 08003ea5 .word 0x08003ea5
8003e68: 08003ea5 .word 0x08003ea5
8003e6c: 08003ea5 .word 0x08003ea5
8003e70: 08003e8d .word 0x08003e8d
8003e74: 08003ea5 .word 0x08003ea5
8003e78: 08003ea5 .word 0x08003ea5
8003e7c: 08003ea5 .word 0x08003ea5
8003e80: 08003e9d .word 0x08003e9d
8003e84: 2300 movs r3, #0
8003e86: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003e8a: e0d8 b.n 800403e <UART_SetConfig+0x2e6>
8003e8c: 2302 movs r3, #2
8003e8e: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003e92: e0d4 b.n 800403e <UART_SetConfig+0x2e6>
8003e94: 2304 movs r3, #4
8003e96: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003e9a: e0d0 b.n 800403e <UART_SetConfig+0x2e6>
8003e9c: 2308 movs r3, #8
8003e9e: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003ea2: e0cc b.n 800403e <UART_SetConfig+0x2e6>
8003ea4: 2310 movs r3, #16
8003ea6: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003eaa: e0c8 b.n 800403e <UART_SetConfig+0x2e6>
8003eac: 68fb ldr r3, [r7, #12]
8003eae: 681b ldr r3, [r3, #0]
8003eb0: 4a5e ldr r2, [pc, #376] @ (800402c <UART_SetConfig+0x2d4>)
8003eb2: 4293 cmp r3, r2
8003eb4: d125 bne.n 8003f02 <UART_SetConfig+0x1aa>
8003eb6: 4b5b ldr r3, [pc, #364] @ (8004024 <UART_SetConfig+0x2cc>)
8003eb8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003ebc: f003 0330 and.w r3, r3, #48 @ 0x30
8003ec0: 2b30 cmp r3, #48 @ 0x30
8003ec2: d016 beq.n 8003ef2 <UART_SetConfig+0x19a>
8003ec4: 2b30 cmp r3, #48 @ 0x30
8003ec6: d818 bhi.n 8003efa <UART_SetConfig+0x1a2>
8003ec8: 2b20 cmp r3, #32
8003eca: d00a beq.n 8003ee2 <UART_SetConfig+0x18a>
8003ecc: 2b20 cmp r3, #32
8003ece: d814 bhi.n 8003efa <UART_SetConfig+0x1a2>
8003ed0: 2b00 cmp r3, #0
8003ed2: d002 beq.n 8003eda <UART_SetConfig+0x182>
8003ed4: 2b10 cmp r3, #16
8003ed6: d008 beq.n 8003eea <UART_SetConfig+0x192>
8003ed8: e00f b.n 8003efa <UART_SetConfig+0x1a2>
8003eda: 2300 movs r3, #0
8003edc: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003ee0: e0ad b.n 800403e <UART_SetConfig+0x2e6>
8003ee2: 2302 movs r3, #2
8003ee4: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003ee8: e0a9 b.n 800403e <UART_SetConfig+0x2e6>
8003eea: 2304 movs r3, #4
8003eec: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003ef0: e0a5 b.n 800403e <UART_SetConfig+0x2e6>
8003ef2: 2308 movs r3, #8
8003ef4: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003ef8: e0a1 b.n 800403e <UART_SetConfig+0x2e6>
8003efa: 2310 movs r3, #16
8003efc: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003f00: e09d b.n 800403e <UART_SetConfig+0x2e6>
8003f02: 68fb ldr r3, [r7, #12]
8003f04: 681b ldr r3, [r3, #0]
8003f06: 4a4a ldr r2, [pc, #296] @ (8004030 <UART_SetConfig+0x2d8>)
8003f08: 4293 cmp r3, r2
8003f0a: d125 bne.n 8003f58 <UART_SetConfig+0x200>
8003f0c: 4b45 ldr r3, [pc, #276] @ (8004024 <UART_SetConfig+0x2cc>)
8003f0e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003f12: f003 03c0 and.w r3, r3, #192 @ 0xc0
8003f16: 2bc0 cmp r3, #192 @ 0xc0
8003f18: d016 beq.n 8003f48 <UART_SetConfig+0x1f0>
8003f1a: 2bc0 cmp r3, #192 @ 0xc0
8003f1c: d818 bhi.n 8003f50 <UART_SetConfig+0x1f8>
8003f1e: 2b80 cmp r3, #128 @ 0x80
8003f20: d00a beq.n 8003f38 <UART_SetConfig+0x1e0>
8003f22: 2b80 cmp r3, #128 @ 0x80
8003f24: d814 bhi.n 8003f50 <UART_SetConfig+0x1f8>
8003f26: 2b00 cmp r3, #0
8003f28: d002 beq.n 8003f30 <UART_SetConfig+0x1d8>
8003f2a: 2b40 cmp r3, #64 @ 0x40
8003f2c: d008 beq.n 8003f40 <UART_SetConfig+0x1e8>
8003f2e: e00f b.n 8003f50 <UART_SetConfig+0x1f8>
8003f30: 2300 movs r3, #0
8003f32: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003f36: e082 b.n 800403e <UART_SetConfig+0x2e6>
8003f38: 2302 movs r3, #2
8003f3a: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003f3e: e07e b.n 800403e <UART_SetConfig+0x2e6>
8003f40: 2304 movs r3, #4
8003f42: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003f46: e07a b.n 800403e <UART_SetConfig+0x2e6>
8003f48: 2308 movs r3, #8
8003f4a: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003f4e: e076 b.n 800403e <UART_SetConfig+0x2e6>
8003f50: 2310 movs r3, #16
8003f52: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003f56: e072 b.n 800403e <UART_SetConfig+0x2e6>
8003f58: 68fb ldr r3, [r7, #12]
8003f5a: 681b ldr r3, [r3, #0]
8003f5c: 4a35 ldr r2, [pc, #212] @ (8004034 <UART_SetConfig+0x2dc>)
8003f5e: 4293 cmp r3, r2
8003f60: d12a bne.n 8003fb8 <UART_SetConfig+0x260>
8003f62: 4b30 ldr r3, [pc, #192] @ (8004024 <UART_SetConfig+0x2cc>)
8003f64: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003f68: f403 7340 and.w r3, r3, #768 @ 0x300
8003f6c: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003f70: d01a beq.n 8003fa8 <UART_SetConfig+0x250>
8003f72: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003f76: d81b bhi.n 8003fb0 <UART_SetConfig+0x258>
8003f78: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003f7c: d00c beq.n 8003f98 <UART_SetConfig+0x240>
8003f7e: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003f82: d815 bhi.n 8003fb0 <UART_SetConfig+0x258>
8003f84: 2b00 cmp r3, #0
8003f86: d003 beq.n 8003f90 <UART_SetConfig+0x238>
8003f88: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003f8c: d008 beq.n 8003fa0 <UART_SetConfig+0x248>
8003f8e: e00f b.n 8003fb0 <UART_SetConfig+0x258>
8003f90: 2300 movs r3, #0
8003f92: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003f96: e052 b.n 800403e <UART_SetConfig+0x2e6>
8003f98: 2302 movs r3, #2
8003f9a: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003f9e: e04e b.n 800403e <UART_SetConfig+0x2e6>
8003fa0: 2304 movs r3, #4
8003fa2: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003fa6: e04a b.n 800403e <UART_SetConfig+0x2e6>
8003fa8: 2308 movs r3, #8
8003faa: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003fae: e046 b.n 800403e <UART_SetConfig+0x2e6>
8003fb0: 2310 movs r3, #16
8003fb2: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003fb6: e042 b.n 800403e <UART_SetConfig+0x2e6>
8003fb8: 68fb ldr r3, [r7, #12]
8003fba: 681b ldr r3, [r3, #0]
8003fbc: 4a17 ldr r2, [pc, #92] @ (800401c <UART_SetConfig+0x2c4>)
8003fbe: 4293 cmp r3, r2
8003fc0: d13a bne.n 8004038 <UART_SetConfig+0x2e0>
8003fc2: 4b18 ldr r3, [pc, #96] @ (8004024 <UART_SetConfig+0x2cc>)
8003fc4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003fc8: f403 6340 and.w r3, r3, #3072 @ 0xc00
8003fcc: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8003fd0: d01a beq.n 8004008 <UART_SetConfig+0x2b0>
8003fd2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8003fd6: d81b bhi.n 8004010 <UART_SetConfig+0x2b8>
8003fd8: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003fdc: d00c beq.n 8003ff8 <UART_SetConfig+0x2a0>
8003fde: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003fe2: d815 bhi.n 8004010 <UART_SetConfig+0x2b8>
8003fe4: 2b00 cmp r3, #0
8003fe6: d003 beq.n 8003ff0 <UART_SetConfig+0x298>
8003fe8: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003fec: d008 beq.n 8004000 <UART_SetConfig+0x2a8>
8003fee: e00f b.n 8004010 <UART_SetConfig+0x2b8>
8003ff0: 2300 movs r3, #0
8003ff2: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003ff6: e022 b.n 800403e <UART_SetConfig+0x2e6>
8003ff8: 2302 movs r3, #2
8003ffa: f887 3023 strb.w r3, [r7, #35] @ 0x23
8003ffe: e01e b.n 800403e <UART_SetConfig+0x2e6>
8004000: 2304 movs r3, #4
8004002: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004006: e01a b.n 800403e <UART_SetConfig+0x2e6>
8004008: 2308 movs r3, #8
800400a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800400e: e016 b.n 800403e <UART_SetConfig+0x2e6>
8004010: 2310 movs r3, #16
8004012: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004016: e012 b.n 800403e <UART_SetConfig+0x2e6>
8004018: efff69f3 .word 0xefff69f3
800401c: 40008000 .word 0x40008000
8004020: 40013800 .word 0x40013800
8004024: 40021000 .word 0x40021000
8004028: 40004400 .word 0x40004400
800402c: 40004800 .word 0x40004800
8004030: 40004c00 .word 0x40004c00
8004034: 40005000 .word 0x40005000
8004038: 2310 movs r3, #16
800403a: f887 3023 strb.w r3, [r7, #35] @ 0x23
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
800403e: 68fb ldr r3, [r7, #12]
8004040: 681b ldr r3, [r3, #0]
8004042: 4a9f ldr r2, [pc, #636] @ (80042c0 <UART_SetConfig+0x568>)
8004044: 4293 cmp r3, r2
8004046: d17a bne.n 800413e <UART_SetConfig+0x3e6>
{
/* Retrieve frequency clock */
switch (clocksource)
8004048: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
800404c: 2b08 cmp r3, #8
800404e: d824 bhi.n 800409a <UART_SetConfig+0x342>
8004050: a201 add r2, pc, #4 @ (adr r2, 8004058 <UART_SetConfig+0x300>)
8004052: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004056: bf00 nop
8004058: 0800407d .word 0x0800407d
800405c: 0800409b .word 0x0800409b
8004060: 08004085 .word 0x08004085
8004064: 0800409b .word 0x0800409b
8004068: 0800408b .word 0x0800408b
800406c: 0800409b .word 0x0800409b
8004070: 0800409b .word 0x0800409b
8004074: 0800409b .word 0x0800409b
8004078: 08004093 .word 0x08004093
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800407c: f7ff f822 bl 80030c4 <HAL_RCC_GetPCLK1Freq>
8004080: 61f8 str r0, [r7, #28]
break;
8004082: e010 b.n 80040a6 <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8004084: 4b8f ldr r3, [pc, #572] @ (80042c4 <UART_SetConfig+0x56c>)
8004086: 61fb str r3, [r7, #28]
break;
8004088: e00d b.n 80040a6 <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800408a: f7fe ff83 bl 8002f94 <HAL_RCC_GetSysClockFreq>
800408e: 61f8 str r0, [r7, #28]
break;
8004090: e009 b.n 80040a6 <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8004092: f44f 4300 mov.w r3, #32768 @ 0x8000
8004096: 61fb str r3, [r7, #28]
break;
8004098: e005 b.n 80040a6 <UART_SetConfig+0x34e>
default:
pclk = 0U;
800409a: 2300 movs r3, #0
800409c: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
800409e: 2301 movs r3, #1
80040a0: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
80040a4: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
80040a6: 69fb ldr r3, [r7, #28]
80040a8: 2b00 cmp r3, #0
80040aa: f000 80fb beq.w 80042a4 <UART_SetConfig+0x54c>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
#else
/* No Prescaler applicable */
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((pclk < (3U * huart->Init.BaudRate)) ||
80040ae: 68fb ldr r3, [r7, #12]
80040b0: 685a ldr r2, [r3, #4]
80040b2: 4613 mov r3, r2
80040b4: 005b lsls r3, r3, #1
80040b6: 4413 add r3, r2
80040b8: 69fa ldr r2, [r7, #28]
80040ba: 429a cmp r2, r3
80040bc: d305 bcc.n 80040ca <UART_SetConfig+0x372>
(pclk > (4096U * huart->Init.BaudRate)))
80040be: 68fb ldr r3, [r7, #12]
80040c0: 685b ldr r3, [r3, #4]
80040c2: 031b lsls r3, r3, #12
if ((pclk < (3U * huart->Init.BaudRate)) ||
80040c4: 69fa ldr r2, [r7, #28]
80040c6: 429a cmp r2, r3
80040c8: d903 bls.n 80040d2 <UART_SetConfig+0x37a>
{
ret = HAL_ERROR;
80040ca: 2301 movs r3, #1
80040cc: f887 3022 strb.w r3, [r7, #34] @ 0x22
80040d0: e0e8 b.n 80042a4 <UART_SetConfig+0x54c>
}
else
{
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
80040d2: 69fb ldr r3, [r7, #28]
80040d4: 2200 movs r2, #0
80040d6: 461c mov r4, r3
80040d8: 4615 mov r5, r2
80040da: f04f 0200 mov.w r2, #0
80040de: f04f 0300 mov.w r3, #0
80040e2: 022b lsls r3, r5, #8
80040e4: ea43 6314 orr.w r3, r3, r4, lsr #24
80040e8: 0222 lsls r2, r4, #8
80040ea: 68f9 ldr r1, [r7, #12]
80040ec: 6849 ldr r1, [r1, #4]
80040ee: 0849 lsrs r1, r1, #1
80040f0: 2000 movs r0, #0
80040f2: 4688 mov r8, r1
80040f4: 4681 mov r9, r0
80040f6: eb12 0a08 adds.w sl, r2, r8
80040fa: eb43 0b09 adc.w fp, r3, r9
80040fe: 68fb ldr r3, [r7, #12]
8004100: 685b ldr r3, [r3, #4]
8004102: 2200 movs r2, #0
8004104: 603b str r3, [r7, #0]
8004106: 607a str r2, [r7, #4]
8004108: e9d7 2300 ldrd r2, r3, [r7]
800410c: 4650 mov r0, sl
800410e: 4659 mov r1, fp
8004110: f7fc f85a bl 80001c8 <__aeabi_uldivmod>
8004114: 4602 mov r2, r0
8004116: 460b mov r3, r1
8004118: 4613 mov r3, r2
800411a: 61bb str r3, [r7, #24]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
800411c: 69bb ldr r3, [r7, #24]
800411e: f5b3 7f40 cmp.w r3, #768 @ 0x300
8004122: d308 bcc.n 8004136 <UART_SetConfig+0x3de>
8004124: 69bb ldr r3, [r7, #24]
8004126: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800412a: d204 bcs.n 8004136 <UART_SetConfig+0x3de>
{
huart->Instance->BRR = usartdiv;
800412c: 68fb ldr r3, [r7, #12]
800412e: 681b ldr r3, [r3, #0]
8004130: 69ba ldr r2, [r7, #24]
8004132: 60da str r2, [r3, #12]
8004134: e0b6 b.n 80042a4 <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
8004136: 2301 movs r3, #1
8004138: f887 3022 strb.w r3, [r7, #34] @ 0x22
800413c: e0b2 b.n 80042a4 <UART_SetConfig+0x54c>
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
#endif /* USART_PRESC_PRESCALER */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
800413e: 68fb ldr r3, [r7, #12]
8004140: 69db ldr r3, [r3, #28]
8004142: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8004146: d15e bne.n 8004206 <UART_SetConfig+0x4ae>
{
switch (clocksource)
8004148: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
800414c: 2b08 cmp r3, #8
800414e: d828 bhi.n 80041a2 <UART_SetConfig+0x44a>
8004150: a201 add r2, pc, #4 @ (adr r2, 8004158 <UART_SetConfig+0x400>)
8004152: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004156: bf00 nop
8004158: 0800417d .word 0x0800417d
800415c: 08004185 .word 0x08004185
8004160: 0800418d .word 0x0800418d
8004164: 080041a3 .word 0x080041a3
8004168: 08004193 .word 0x08004193
800416c: 080041a3 .word 0x080041a3
8004170: 080041a3 .word 0x080041a3
8004174: 080041a3 .word 0x080041a3
8004178: 0800419b .word 0x0800419b
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800417c: f7fe ffa2 bl 80030c4 <HAL_RCC_GetPCLK1Freq>
8004180: 61f8 str r0, [r7, #28]
break;
8004182: e014 b.n 80041ae <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8004184: f7fe ffb4 bl 80030f0 <HAL_RCC_GetPCLK2Freq>
8004188: 61f8 str r0, [r7, #28]
break;
800418a: e010 b.n 80041ae <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
800418c: 4b4d ldr r3, [pc, #308] @ (80042c4 <UART_SetConfig+0x56c>)
800418e: 61fb str r3, [r7, #28]
break;
8004190: e00d b.n 80041ae <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8004192: f7fe feff bl 8002f94 <HAL_RCC_GetSysClockFreq>
8004196: 61f8 str r0, [r7, #28]
break;
8004198: e009 b.n 80041ae <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
800419a: f44f 4300 mov.w r3, #32768 @ 0x8000
800419e: 61fb str r3, [r7, #28]
break;
80041a0: e005 b.n 80041ae <UART_SetConfig+0x456>
default:
pclk = 0U;
80041a2: 2300 movs r3, #0
80041a4: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
80041a6: 2301 movs r3, #1
80041a8: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
80041ac: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
80041ae: 69fb ldr r3, [r7, #28]
80041b0: 2b00 cmp r3, #0
80041b2: d077 beq.n 80042a4 <UART_SetConfig+0x54c>
{
#if defined(USART_PRESC_PRESCALER)
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
80041b4: 69fb ldr r3, [r7, #28]
80041b6: 005a lsls r2, r3, #1
80041b8: 68fb ldr r3, [r7, #12]
80041ba: 685b ldr r3, [r3, #4]
80041bc: 085b lsrs r3, r3, #1
80041be: 441a add r2, r3
80041c0: 68fb ldr r3, [r7, #12]
80041c2: 685b ldr r3, [r3, #4]
80041c4: fbb2 f3f3 udiv r3, r2, r3
80041c8: 61bb str r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80041ca: 69bb ldr r3, [r7, #24]
80041cc: 2b0f cmp r3, #15
80041ce: d916 bls.n 80041fe <UART_SetConfig+0x4a6>
80041d0: 69bb ldr r3, [r7, #24]
80041d2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80041d6: d212 bcs.n 80041fe <UART_SetConfig+0x4a6>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
80041d8: 69bb ldr r3, [r7, #24]
80041da: b29b uxth r3, r3
80041dc: f023 030f bic.w r3, r3, #15
80041e0: 82fb strh r3, [r7, #22]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
80041e2: 69bb ldr r3, [r7, #24]
80041e4: 085b lsrs r3, r3, #1
80041e6: b29b uxth r3, r3
80041e8: f003 0307 and.w r3, r3, #7
80041ec: b29a uxth r2, r3
80041ee: 8afb ldrh r3, [r7, #22]
80041f0: 4313 orrs r3, r2
80041f2: 82fb strh r3, [r7, #22]
huart->Instance->BRR = brrtemp;
80041f4: 68fb ldr r3, [r7, #12]
80041f6: 681b ldr r3, [r3, #0]
80041f8: 8afa ldrh r2, [r7, #22]
80041fa: 60da str r2, [r3, #12]
80041fc: e052 b.n 80042a4 <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
80041fe: 2301 movs r3, #1
8004200: f887 3022 strb.w r3, [r7, #34] @ 0x22
8004204: e04e b.n 80042a4 <UART_SetConfig+0x54c>
}
}
}
else
{
switch (clocksource)
8004206: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
800420a: 2b08 cmp r3, #8
800420c: d827 bhi.n 800425e <UART_SetConfig+0x506>
800420e: a201 add r2, pc, #4 @ (adr r2, 8004214 <UART_SetConfig+0x4bc>)
8004210: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004214: 08004239 .word 0x08004239
8004218: 08004241 .word 0x08004241
800421c: 08004249 .word 0x08004249
8004220: 0800425f .word 0x0800425f
8004224: 0800424f .word 0x0800424f
8004228: 0800425f .word 0x0800425f
800422c: 0800425f .word 0x0800425f
8004230: 0800425f .word 0x0800425f
8004234: 08004257 .word 0x08004257
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004238: f7fe ff44 bl 80030c4 <HAL_RCC_GetPCLK1Freq>
800423c: 61f8 str r0, [r7, #28]
break;
800423e: e014 b.n 800426a <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8004240: f7fe ff56 bl 80030f0 <HAL_RCC_GetPCLK2Freq>
8004244: 61f8 str r0, [r7, #28]
break;
8004246: e010 b.n 800426a <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8004248: 4b1e ldr r3, [pc, #120] @ (80042c4 <UART_SetConfig+0x56c>)
800424a: 61fb str r3, [r7, #28]
break;
800424c: e00d b.n 800426a <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800424e: f7fe fea1 bl 8002f94 <HAL_RCC_GetSysClockFreq>
8004252: 61f8 str r0, [r7, #28]
break;
8004254: e009 b.n 800426a <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8004256: f44f 4300 mov.w r3, #32768 @ 0x8000
800425a: 61fb str r3, [r7, #28]
break;
800425c: e005 b.n 800426a <UART_SetConfig+0x512>
default:
pclk = 0U;
800425e: 2300 movs r3, #0
8004260: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
8004262: 2301 movs r3, #1
8004264: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
8004268: bf00 nop
}
if (pclk != 0U)
800426a: 69fb ldr r3, [r7, #28]
800426c: 2b00 cmp r3, #0
800426e: d019 beq.n 80042a4 <UART_SetConfig+0x54c>
{
/* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
8004270: 68fb ldr r3, [r7, #12]
8004272: 685b ldr r3, [r3, #4]
8004274: 085a lsrs r2, r3, #1
8004276: 69fb ldr r3, [r7, #28]
8004278: 441a add r2, r3
800427a: 68fb ldr r3, [r7, #12]
800427c: 685b ldr r3, [r3, #4]
800427e: fbb2 f3f3 udiv r3, r2, r3
8004282: 61bb str r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004284: 69bb ldr r3, [r7, #24]
8004286: 2b0f cmp r3, #15
8004288: d909 bls.n 800429e <UART_SetConfig+0x546>
800428a: 69bb ldr r3, [r7, #24]
800428c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004290: d205 bcs.n 800429e <UART_SetConfig+0x546>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8004292: 69bb ldr r3, [r7, #24]
8004294: b29a uxth r2, r3
8004296: 68fb ldr r3, [r7, #12]
8004298: 681b ldr r3, [r3, #0]
800429a: 60da str r2, [r3, #12]
800429c: e002 b.n 80042a4 <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
800429e: 2301 movs r3, #1
80042a0: f887 3022 strb.w r3, [r7, #34] @ 0x22
huart->NbTxDataToProcess = 1;
huart->NbRxDataToProcess = 1;
#endif /* USART_CR1_FIFOEN */
/* Clear ISR function pointers */
huart->RxISR = NULL;
80042a4: 68fb ldr r3, [r7, #12]
80042a6: 2200 movs r2, #0
80042a8: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
80042aa: 68fb ldr r3, [r7, #12]
80042ac: 2200 movs r2, #0
80042ae: 66da str r2, [r3, #108] @ 0x6c
return ret;
80042b0: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
}
80042b4: 4618 mov r0, r3
80042b6: 3728 adds r7, #40 @ 0x28
80042b8: 46bd mov sp, r7
80042ba: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80042be: bf00 nop
80042c0: 40008000 .word 0x40008000
80042c4: 00f42400 .word 0x00f42400
080042c8 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
80042c8: b480 push {r7}
80042ca: b083 sub sp, #12
80042cc: af00 add r7, sp, #0
80042ce: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80042d0: 687b ldr r3, [r7, #4]
80042d2: 6a5b ldr r3, [r3, #36] @ 0x24
80042d4: f003 0308 and.w r3, r3, #8
80042d8: 2b00 cmp r3, #0
80042da: d00a beq.n 80042f2 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
80042dc: 687b ldr r3, [r7, #4]
80042de: 681b ldr r3, [r3, #0]
80042e0: 685b ldr r3, [r3, #4]
80042e2: f423 4100 bic.w r1, r3, #32768 @ 0x8000
80042e6: 687b ldr r3, [r7, #4]
80042e8: 6b5a ldr r2, [r3, #52] @ 0x34
80042ea: 687b ldr r3, [r7, #4]
80042ec: 681b ldr r3, [r3, #0]
80042ee: 430a orrs r2, r1
80042f0: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
80042f2: 687b ldr r3, [r7, #4]
80042f4: 6a5b ldr r3, [r3, #36] @ 0x24
80042f6: f003 0301 and.w r3, r3, #1
80042fa: 2b00 cmp r3, #0
80042fc: d00a beq.n 8004314 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
80042fe: 687b ldr r3, [r7, #4]
8004300: 681b ldr r3, [r3, #0]
8004302: 685b ldr r3, [r3, #4]
8004304: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8004308: 687b ldr r3, [r7, #4]
800430a: 6a9a ldr r2, [r3, #40] @ 0x28
800430c: 687b ldr r3, [r7, #4]
800430e: 681b ldr r3, [r3, #0]
8004310: 430a orrs r2, r1
8004312: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8004314: 687b ldr r3, [r7, #4]
8004316: 6a5b ldr r3, [r3, #36] @ 0x24
8004318: f003 0302 and.w r3, r3, #2
800431c: 2b00 cmp r3, #0
800431e: d00a beq.n 8004336 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8004320: 687b ldr r3, [r7, #4]
8004322: 681b ldr r3, [r3, #0]
8004324: 685b ldr r3, [r3, #4]
8004326: f423 3180 bic.w r1, r3, #65536 @ 0x10000
800432a: 687b ldr r3, [r7, #4]
800432c: 6ada ldr r2, [r3, #44] @ 0x2c
800432e: 687b ldr r3, [r7, #4]
8004330: 681b ldr r3, [r3, #0]
8004332: 430a orrs r2, r1
8004334: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8004336: 687b ldr r3, [r7, #4]
8004338: 6a5b ldr r3, [r3, #36] @ 0x24
800433a: f003 0304 and.w r3, r3, #4
800433e: 2b00 cmp r3, #0
8004340: d00a beq.n 8004358 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8004342: 687b ldr r3, [r7, #4]
8004344: 681b ldr r3, [r3, #0]
8004346: 685b ldr r3, [r3, #4]
8004348: f423 2180 bic.w r1, r3, #262144 @ 0x40000
800434c: 687b ldr r3, [r7, #4]
800434e: 6b1a ldr r2, [r3, #48] @ 0x30
8004350: 687b ldr r3, [r7, #4]
8004352: 681b ldr r3, [r3, #0]
8004354: 430a orrs r2, r1
8004356: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8004358: 687b ldr r3, [r7, #4]
800435a: 6a5b ldr r3, [r3, #36] @ 0x24
800435c: f003 0310 and.w r3, r3, #16
8004360: 2b00 cmp r3, #0
8004362: d00a beq.n 800437a <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8004364: 687b ldr r3, [r7, #4]
8004366: 681b ldr r3, [r3, #0]
8004368: 689b ldr r3, [r3, #8]
800436a: f423 5180 bic.w r1, r3, #4096 @ 0x1000
800436e: 687b ldr r3, [r7, #4]
8004370: 6b9a ldr r2, [r3, #56] @ 0x38
8004372: 687b ldr r3, [r7, #4]
8004374: 681b ldr r3, [r3, #0]
8004376: 430a orrs r2, r1
8004378: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
800437a: 687b ldr r3, [r7, #4]
800437c: 6a5b ldr r3, [r3, #36] @ 0x24
800437e: f003 0320 and.w r3, r3, #32
8004382: 2b00 cmp r3, #0
8004384: d00a beq.n 800439c <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8004386: 687b ldr r3, [r7, #4]
8004388: 681b ldr r3, [r3, #0]
800438a: 689b ldr r3, [r3, #8]
800438c: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8004390: 687b ldr r3, [r7, #4]
8004392: 6bda ldr r2, [r3, #60] @ 0x3c
8004394: 687b ldr r3, [r7, #4]
8004396: 681b ldr r3, [r3, #0]
8004398: 430a orrs r2, r1
800439a: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
800439c: 687b ldr r3, [r7, #4]
800439e: 6a5b ldr r3, [r3, #36] @ 0x24
80043a0: f003 0340 and.w r3, r3, #64 @ 0x40
80043a4: 2b00 cmp r3, #0
80043a6: d01a beq.n 80043de <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
80043a8: 687b ldr r3, [r7, #4]
80043aa: 681b ldr r3, [r3, #0]
80043ac: 685b ldr r3, [r3, #4]
80043ae: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
80043b2: 687b ldr r3, [r7, #4]
80043b4: 6c1a ldr r2, [r3, #64] @ 0x40
80043b6: 687b ldr r3, [r7, #4]
80043b8: 681b ldr r3, [r3, #0]
80043ba: 430a orrs r2, r1
80043bc: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
80043be: 687b ldr r3, [r7, #4]
80043c0: 6c1b ldr r3, [r3, #64] @ 0x40
80043c2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80043c6: d10a bne.n 80043de <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
80043c8: 687b ldr r3, [r7, #4]
80043ca: 681b ldr r3, [r3, #0]
80043cc: 685b ldr r3, [r3, #4]
80043ce: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
80043d2: 687b ldr r3, [r7, #4]
80043d4: 6c5a ldr r2, [r3, #68] @ 0x44
80043d6: 687b ldr r3, [r7, #4]
80043d8: 681b ldr r3, [r3, #0]
80043da: 430a orrs r2, r1
80043dc: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
80043de: 687b ldr r3, [r7, #4]
80043e0: 6a5b ldr r3, [r3, #36] @ 0x24
80043e2: f003 0380 and.w r3, r3, #128 @ 0x80
80043e6: 2b00 cmp r3, #0
80043e8: d00a beq.n 8004400 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
80043ea: 687b ldr r3, [r7, #4]
80043ec: 681b ldr r3, [r3, #0]
80043ee: 685b ldr r3, [r3, #4]
80043f0: f423 2100 bic.w r1, r3, #524288 @ 0x80000
80043f4: 687b ldr r3, [r7, #4]
80043f6: 6c9a ldr r2, [r3, #72] @ 0x48
80043f8: 687b ldr r3, [r7, #4]
80043fa: 681b ldr r3, [r3, #0]
80043fc: 430a orrs r2, r1
80043fe: 605a str r2, [r3, #4]
}
}
8004400: bf00 nop
8004402: 370c adds r7, #12
8004404: 46bd mov sp, r7
8004406: f85d 7b04 ldr.w r7, [sp], #4
800440a: 4770 bx lr
0800440c <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
800440c: b580 push {r7, lr}
800440e: b098 sub sp, #96 @ 0x60
8004410: af02 add r7, sp, #8
8004412: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004414: 687b ldr r3, [r7, #4]
8004416: 2200 movs r2, #0
8004418: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800441c: f7fd f8ee bl 80015fc <HAL_GetTick>
8004420: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8004422: 687b ldr r3, [r7, #4]
8004424: 681b ldr r3, [r3, #0]
8004426: 681b ldr r3, [r3, #0]
8004428: f003 0308 and.w r3, r3, #8
800442c: 2b08 cmp r3, #8
800442e: d12e bne.n 800448e <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8004430: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8004434: 9300 str r3, [sp, #0]
8004436: 6d7b ldr r3, [r7, #84] @ 0x54
8004438: 2200 movs r2, #0
800443a: f44f 1100 mov.w r1, #2097152 @ 0x200000
800443e: 6878 ldr r0, [r7, #4]
8004440: f000 f88c bl 800455c <UART_WaitOnFlagUntilTimeout>
8004444: 4603 mov r3, r0
8004446: 2b00 cmp r3, #0
8004448: d021 beq.n 800448e <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
800444a: 687b ldr r3, [r7, #4]
800444c: 681b ldr r3, [r3, #0]
800444e: 63bb str r3, [r7, #56] @ 0x38
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004450: 6bbb ldr r3, [r7, #56] @ 0x38
8004452: e853 3f00 ldrex r3, [r3]
8004456: 637b str r3, [r7, #52] @ 0x34
return(result);
8004458: 6b7b ldr r3, [r7, #52] @ 0x34
800445a: f023 0380 bic.w r3, r3, #128 @ 0x80
800445e: 653b str r3, [r7, #80] @ 0x50
8004460: 687b ldr r3, [r7, #4]
8004462: 681b ldr r3, [r3, #0]
8004464: 461a mov r2, r3
8004466: 6d3b ldr r3, [r7, #80] @ 0x50
8004468: 647b str r3, [r7, #68] @ 0x44
800446a: 643a str r2, [r7, #64] @ 0x40
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800446c: 6c39 ldr r1, [r7, #64] @ 0x40
800446e: 6c7a ldr r2, [r7, #68] @ 0x44
8004470: e841 2300 strex r3, r2, [r1]
8004474: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8004476: 6bfb ldr r3, [r7, #60] @ 0x3c
8004478: 2b00 cmp r3, #0
800447a: d1e6 bne.n 800444a <UART_CheckIdleState+0x3e>
#endif /* USART_CR1_FIFOEN */
huart->gState = HAL_UART_STATE_READY;
800447c: 687b ldr r3, [r7, #4]
800447e: 2220 movs r2, #32
8004480: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
8004482: 687b ldr r3, [r7, #4]
8004484: 2200 movs r2, #0
8004486: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
800448a: 2303 movs r3, #3
800448c: e062 b.n 8004554 <UART_CheckIdleState+0x148>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
800448e: 687b ldr r3, [r7, #4]
8004490: 681b ldr r3, [r3, #0]
8004492: 681b ldr r3, [r3, #0]
8004494: f003 0304 and.w r3, r3, #4
8004498: 2b04 cmp r3, #4
800449a: d149 bne.n 8004530 <UART_CheckIdleState+0x124>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
800449c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
80044a0: 9300 str r3, [sp, #0]
80044a2: 6d7b ldr r3, [r7, #84] @ 0x54
80044a4: 2200 movs r2, #0
80044a6: f44f 0180 mov.w r1, #4194304 @ 0x400000
80044aa: 6878 ldr r0, [r7, #4]
80044ac: f000 f856 bl 800455c <UART_WaitOnFlagUntilTimeout>
80044b0: 4603 mov r3, r0
80044b2: 2b00 cmp r3, #0
80044b4: d03c beq.n 8004530 <UART_CheckIdleState+0x124>
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80044b6: 687b ldr r3, [r7, #4]
80044b8: 681b ldr r3, [r3, #0]
80044ba: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80044bc: 6a7b ldr r3, [r7, #36] @ 0x24
80044be: e853 3f00 ldrex r3, [r3]
80044c2: 623b str r3, [r7, #32]
return(result);
80044c4: 6a3b ldr r3, [r7, #32]
80044c6: f423 7390 bic.w r3, r3, #288 @ 0x120
80044ca: 64fb str r3, [r7, #76] @ 0x4c
80044cc: 687b ldr r3, [r7, #4]
80044ce: 681b ldr r3, [r3, #0]
80044d0: 461a mov r2, r3
80044d2: 6cfb ldr r3, [r7, #76] @ 0x4c
80044d4: 633b str r3, [r7, #48] @ 0x30
80044d6: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80044d8: 6af9 ldr r1, [r7, #44] @ 0x2c
80044da: 6b3a ldr r2, [r7, #48] @ 0x30
80044dc: e841 2300 strex r3, r2, [r1]
80044e0: 62bb str r3, [r7, #40] @ 0x28
return(result);
80044e2: 6abb ldr r3, [r7, #40] @ 0x28
80044e4: 2b00 cmp r3, #0
80044e6: d1e6 bne.n 80044b6 <UART_CheckIdleState+0xaa>
#endif /* USART_CR1_FIFOEN */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80044e8: 687b ldr r3, [r7, #4]
80044ea: 681b ldr r3, [r3, #0]
80044ec: 3308 adds r3, #8
80044ee: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80044f0: 693b ldr r3, [r7, #16]
80044f2: e853 3f00 ldrex r3, [r3]
80044f6: 60fb str r3, [r7, #12]
return(result);
80044f8: 68fb ldr r3, [r7, #12]
80044fa: f023 0301 bic.w r3, r3, #1
80044fe: 64bb str r3, [r7, #72] @ 0x48
8004500: 687b ldr r3, [r7, #4]
8004502: 681b ldr r3, [r3, #0]
8004504: 3308 adds r3, #8
8004506: 6cba ldr r2, [r7, #72] @ 0x48
8004508: 61fa str r2, [r7, #28]
800450a: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800450c: 69b9 ldr r1, [r7, #24]
800450e: 69fa ldr r2, [r7, #28]
8004510: e841 2300 strex r3, r2, [r1]
8004514: 617b str r3, [r7, #20]
return(result);
8004516: 697b ldr r3, [r7, #20]
8004518: 2b00 cmp r3, #0
800451a: d1e5 bne.n 80044e8 <UART_CheckIdleState+0xdc>
huart->RxState = HAL_UART_STATE_READY;
800451c: 687b ldr r3, [r7, #4]
800451e: 2220 movs r2, #32
8004520: f8c3 2080 str.w r2, [r3, #128] @ 0x80
__HAL_UNLOCK(huart);
8004524: 687b ldr r3, [r7, #4]
8004526: 2200 movs r2, #0
8004528: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
800452c: 2303 movs r3, #3
800452e: e011 b.n 8004554 <UART_CheckIdleState+0x148>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8004530: 687b ldr r3, [r7, #4]
8004532: 2220 movs r2, #32
8004534: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
8004536: 687b ldr r3, [r7, #4]
8004538: 2220 movs r2, #32
800453a: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800453e: 687b ldr r3, [r7, #4]
8004540: 2200 movs r2, #0
8004542: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8004544: 687b ldr r3, [r7, #4]
8004546: 2200 movs r2, #0
8004548: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
800454a: 687b ldr r3, [r7, #4]
800454c: 2200 movs r2, #0
800454e: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
8004552: 2300 movs r3, #0
}
8004554: 4618 mov r0, r3
8004556: 3758 adds r7, #88 @ 0x58
8004558: 46bd mov sp, r7
800455a: bd80 pop {r7, pc}
0800455c <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
800455c: b580 push {r7, lr}
800455e: b084 sub sp, #16
8004560: af00 add r7, sp, #0
8004562: 60f8 str r0, [r7, #12]
8004564: 60b9 str r1, [r7, #8]
8004566: 603b str r3, [r7, #0]
8004568: 4613 mov r3, r2
800456a: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800456c: e04f b.n 800460e <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800456e: 69bb ldr r3, [r7, #24]
8004570: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8004574: d04b beq.n 800460e <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004576: f7fd f841 bl 80015fc <HAL_GetTick>
800457a: 4602 mov r2, r0
800457c: 683b ldr r3, [r7, #0]
800457e: 1ad3 subs r3, r2, r3
8004580: 69ba ldr r2, [r7, #24]
8004582: 429a cmp r2, r3
8004584: d302 bcc.n 800458c <UART_WaitOnFlagUntilTimeout+0x30>
8004586: 69bb ldr r3, [r7, #24]
8004588: 2b00 cmp r3, #0
800458a: d101 bne.n 8004590 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
800458c: 2303 movs r3, #3
800458e: e04e b.n 800462e <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8004590: 68fb ldr r3, [r7, #12]
8004592: 681b ldr r3, [r3, #0]
8004594: 681b ldr r3, [r3, #0]
8004596: f003 0304 and.w r3, r3, #4
800459a: 2b00 cmp r3, #0
800459c: d037 beq.n 800460e <UART_WaitOnFlagUntilTimeout+0xb2>
800459e: 68bb ldr r3, [r7, #8]
80045a0: 2b80 cmp r3, #128 @ 0x80
80045a2: d034 beq.n 800460e <UART_WaitOnFlagUntilTimeout+0xb2>
80045a4: 68bb ldr r3, [r7, #8]
80045a6: 2b40 cmp r3, #64 @ 0x40
80045a8: d031 beq.n 800460e <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
80045aa: 68fb ldr r3, [r7, #12]
80045ac: 681b ldr r3, [r3, #0]
80045ae: 69db ldr r3, [r3, #28]
80045b0: f003 0308 and.w r3, r3, #8
80045b4: 2b08 cmp r3, #8
80045b6: d110 bne.n 80045da <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
80045b8: 68fb ldr r3, [r7, #12]
80045ba: 681b ldr r3, [r3, #0]
80045bc: 2208 movs r2, #8
80045be: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
80045c0: 68f8 ldr r0, [r7, #12]
80045c2: f000 f838 bl 8004636 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
80045c6: 68fb ldr r3, [r7, #12]
80045c8: 2208 movs r2, #8
80045ca: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
80045ce: 68fb ldr r3, [r7, #12]
80045d0: 2200 movs r2, #0
80045d2: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
80045d6: 2301 movs r3, #1
80045d8: e029 b.n 800462e <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
80045da: 68fb ldr r3, [r7, #12]
80045dc: 681b ldr r3, [r3, #0]
80045de: 69db ldr r3, [r3, #28]
80045e0: f403 6300 and.w r3, r3, #2048 @ 0x800
80045e4: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80045e8: d111 bne.n 800460e <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80045ea: 68fb ldr r3, [r7, #12]
80045ec: 681b ldr r3, [r3, #0]
80045ee: f44f 6200 mov.w r2, #2048 @ 0x800
80045f2: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
80045f4: 68f8 ldr r0, [r7, #12]
80045f6: f000 f81e bl 8004636 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
80045fa: 68fb ldr r3, [r7, #12]
80045fc: 2220 movs r2, #32
80045fe: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004602: 68fb ldr r3, [r7, #12]
8004604: 2200 movs r2, #0
8004606: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
800460a: 2303 movs r3, #3
800460c: e00f b.n 800462e <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800460e: 68fb ldr r3, [r7, #12]
8004610: 681b ldr r3, [r3, #0]
8004612: 69da ldr r2, [r3, #28]
8004614: 68bb ldr r3, [r7, #8]
8004616: 4013 ands r3, r2
8004618: 68ba ldr r2, [r7, #8]
800461a: 429a cmp r2, r3
800461c: bf0c ite eq
800461e: 2301 moveq r3, #1
8004620: 2300 movne r3, #0
8004622: b2db uxtb r3, r3
8004624: 461a mov r2, r3
8004626: 79fb ldrb r3, [r7, #7]
8004628: 429a cmp r2, r3
800462a: d0a0 beq.n 800456e <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
800462c: 2300 movs r3, #0
}
800462e: 4618 mov r0, r3
8004630: 3710 adds r7, #16
8004632: 46bd mov sp, r7
8004634: bd80 pop {r7, pc}
08004636 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004636: b480 push {r7}
8004638: b095 sub sp, #84 @ 0x54
800463a: af00 add r7, sp, #0
800463c: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
800463e: 687b ldr r3, [r7, #4]
8004640: 681b ldr r3, [r3, #0]
8004642: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004644: 6b7b ldr r3, [r7, #52] @ 0x34
8004646: e853 3f00 ldrex r3, [r3]
800464a: 633b str r3, [r7, #48] @ 0x30
return(result);
800464c: 6b3b ldr r3, [r7, #48] @ 0x30
800464e: f423 7390 bic.w r3, r3, #288 @ 0x120
8004652: 64fb str r3, [r7, #76] @ 0x4c
8004654: 687b ldr r3, [r7, #4]
8004656: 681b ldr r3, [r3, #0]
8004658: 461a mov r2, r3
800465a: 6cfb ldr r3, [r7, #76] @ 0x4c
800465c: 643b str r3, [r7, #64] @ 0x40
800465e: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004660: 6bf9 ldr r1, [r7, #60] @ 0x3c
8004662: 6c3a ldr r2, [r7, #64] @ 0x40
8004664: e841 2300 strex r3, r2, [r1]
8004668: 63bb str r3, [r7, #56] @ 0x38
return(result);
800466a: 6bbb ldr r3, [r7, #56] @ 0x38
800466c: 2b00 cmp r3, #0
800466e: d1e6 bne.n 800463e <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004670: 687b ldr r3, [r7, #4]
8004672: 681b ldr r3, [r3, #0]
8004674: 3308 adds r3, #8
8004676: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004678: 6a3b ldr r3, [r7, #32]
800467a: e853 3f00 ldrex r3, [r3]
800467e: 61fb str r3, [r7, #28]
return(result);
8004680: 69fb ldr r3, [r7, #28]
8004682: f023 0301 bic.w r3, r3, #1
8004686: 64bb str r3, [r7, #72] @ 0x48
8004688: 687b ldr r3, [r7, #4]
800468a: 681b ldr r3, [r3, #0]
800468c: 3308 adds r3, #8
800468e: 6cba ldr r2, [r7, #72] @ 0x48
8004690: 62fa str r2, [r7, #44] @ 0x2c
8004692: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004694: 6ab9 ldr r1, [r7, #40] @ 0x28
8004696: 6afa ldr r2, [r7, #44] @ 0x2c
8004698: e841 2300 strex r3, r2, [r1]
800469c: 627b str r3, [r7, #36] @ 0x24
return(result);
800469e: 6a7b ldr r3, [r7, #36] @ 0x24
80046a0: 2b00 cmp r3, #0
80046a2: d1e5 bne.n 8004670 <UART_EndRxTransfer+0x3a>
#endif /* USART_CR1_FIFOEN */
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80046a4: 687b ldr r3, [r7, #4]
80046a6: 6e1b ldr r3, [r3, #96] @ 0x60
80046a8: 2b01 cmp r3, #1
80046aa: d118 bne.n 80046de <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80046ac: 687b ldr r3, [r7, #4]
80046ae: 681b ldr r3, [r3, #0]
80046b0: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80046b2: 68fb ldr r3, [r7, #12]
80046b4: e853 3f00 ldrex r3, [r3]
80046b8: 60bb str r3, [r7, #8]
return(result);
80046ba: 68bb ldr r3, [r7, #8]
80046bc: f023 0310 bic.w r3, r3, #16
80046c0: 647b str r3, [r7, #68] @ 0x44
80046c2: 687b ldr r3, [r7, #4]
80046c4: 681b ldr r3, [r3, #0]
80046c6: 461a mov r2, r3
80046c8: 6c7b ldr r3, [r7, #68] @ 0x44
80046ca: 61bb str r3, [r7, #24]
80046cc: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80046ce: 6979 ldr r1, [r7, #20]
80046d0: 69ba ldr r2, [r7, #24]
80046d2: e841 2300 strex r3, r2, [r1]
80046d6: 613b str r3, [r7, #16]
return(result);
80046d8: 693b ldr r3, [r7, #16]
80046da: 2b00 cmp r3, #0
80046dc: d1e6 bne.n 80046ac <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80046de: 687b ldr r3, [r7, #4]
80046e0: 2220 movs r2, #32
80046e2: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80046e6: 687b ldr r3, [r7, #4]
80046e8: 2200 movs r2, #0
80046ea: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
80046ec: 687b ldr r3, [r7, #4]
80046ee: 2200 movs r2, #0
80046f0: 669a str r2, [r3, #104] @ 0x68
}
80046f2: bf00 nop
80046f4: 3754 adds r7, #84 @ 0x54
80046f6: 46bd mov sp, r7
80046f8: f85d 7b04 ldr.w r7, [sp], #4
80046fc: 4770 bx lr
080046fe <USB_CoreInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
80046fe: b084 sub sp, #16
8004700: b580 push {r7, lr}
8004702: b084 sub sp, #16
8004704: af00 add r7, sp, #0
8004706: 6078 str r0, [r7, #4]
8004708: f107 001c add.w r0, r7, #28
800470c: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret;
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
8004710: 687b ldr r3, [r7, #4]
8004712: 68db ldr r3, [r3, #12]
8004714: f043 0240 orr.w r2, r3, #64 @ 0x40
8004718: 687b ldr r3, [r7, #4]
800471a: 60da str r2, [r3, #12]
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
800471c: 6878 ldr r0, [r7, #4]
800471e: f000 fa69 bl 8004bf4 <USB_CoreReset>
8004722: 4603 mov r3, r0
8004724: 73fb strb r3, [r7, #15]
if (cfg.battery_charging_enable == 0U)
8004726: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
800472a: 2b00 cmp r3, #0
800472c: d106 bne.n 800473c <USB_CoreInit+0x3e>
{
/* Activate the USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
800472e: 687b ldr r3, [r7, #4]
8004730: 6b9b ldr r3, [r3, #56] @ 0x38
8004732: f443 3280 orr.w r2, r3, #65536 @ 0x10000
8004736: 687b ldr r3, [r7, #4]
8004738: 639a str r2, [r3, #56] @ 0x38
800473a: e005 b.n 8004748 <USB_CoreInit+0x4a>
}
else
{
/* Deactivate the USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
800473c: 687b ldr r3, [r7, #4]
800473e: 6b9b ldr r3, [r3, #56] @ 0x38
8004740: f423 3280 bic.w r2, r3, #65536 @ 0x10000
8004744: 687b ldr r3, [r7, #4]
8004746: 639a str r2, [r3, #56] @ 0x38
}
return ret;
8004748: 7bfb ldrb r3, [r7, #15]
}
800474a: 4618 mov r0, r3
800474c: 3710 adds r7, #16
800474e: 46bd mov sp, r7
8004750: e8bd 4080 ldmia.w sp!, {r7, lr}
8004754: b004 add sp, #16
8004756: 4770 bx lr
08004758 <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
8004758: b480 push {r7}
800475a: b083 sub sp, #12
800475c: af00 add r7, sp, #0
800475e: 6078 str r0, [r7, #4]
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
8004760: 687b ldr r3, [r7, #4]
8004762: 689b ldr r3, [r3, #8]
8004764: f023 0201 bic.w r2, r3, #1
8004768: 687b ldr r3, [r7, #4]
800476a: 609a str r2, [r3, #8]
return HAL_OK;
800476c: 2300 movs r3, #0
}
800476e: 4618 mov r0, r3
8004770: 370c adds r7, #12
8004772: 46bd mov sp, r7
8004774: f85d 7b04 ldr.w r7, [sp], #4
8004778: 4770 bx lr
0800477a <USB_SetCurrentMode>:
* @arg USB_DEVICE_MODE Peripheral mode
* @arg USB_HOST_MODE Host mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
{
800477a: b580 push {r7, lr}
800477c: b084 sub sp, #16
800477e: af00 add r7, sp, #0
8004780: 6078 str r0, [r7, #4]
8004782: 460b mov r3, r1
8004784: 70fb strb r3, [r7, #3]
uint32_t ms = 0U;
8004786: 2300 movs r3, #0
8004788: 60fb str r3, [r7, #12]
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
800478a: 687b ldr r3, [r7, #4]
800478c: 68db ldr r3, [r3, #12]
800478e: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
8004792: 687b ldr r3, [r7, #4]
8004794: 60da str r2, [r3, #12]
if (mode == USB_HOST_MODE)
8004796: 78fb ldrb r3, [r7, #3]
8004798: 2b01 cmp r3, #1
800479a: d115 bne.n 80047c8 <USB_SetCurrentMode+0x4e>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
800479c: 687b ldr r3, [r7, #4]
800479e: 68db ldr r3, [r3, #12]
80047a0: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
80047a4: 687b ldr r3, [r7, #4]
80047a6: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
80047a8: 200a movs r0, #10
80047aa: f7fc ff33 bl 8001614 <HAL_Delay>
ms += 10U;
80047ae: 68fb ldr r3, [r7, #12]
80047b0: 330a adds r3, #10
80047b2: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
80047b4: 6878 ldr r0, [r7, #4]
80047b6: f000 fa0f bl 8004bd8 <USB_GetMode>
80047ba: 4603 mov r3, r0
80047bc: 2b01 cmp r3, #1
80047be: d01e beq.n 80047fe <USB_SetCurrentMode+0x84>
80047c0: 68fb ldr r3, [r7, #12]
80047c2: 2bc7 cmp r3, #199 @ 0xc7
80047c4: d9f0 bls.n 80047a8 <USB_SetCurrentMode+0x2e>
80047c6: e01a b.n 80047fe <USB_SetCurrentMode+0x84>
}
else if (mode == USB_DEVICE_MODE)
80047c8: 78fb ldrb r3, [r7, #3]
80047ca: 2b00 cmp r3, #0
80047cc: d115 bne.n 80047fa <USB_SetCurrentMode+0x80>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
80047ce: 687b ldr r3, [r7, #4]
80047d0: 68db ldr r3, [r3, #12]
80047d2: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
80047d6: 687b ldr r3, [r7, #4]
80047d8: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
80047da: 200a movs r0, #10
80047dc: f7fc ff1a bl 8001614 <HAL_Delay>
ms += 10U;
80047e0: 68fb ldr r3, [r7, #12]
80047e2: 330a adds r3, #10
80047e4: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
80047e6: 6878 ldr r0, [r7, #4]
80047e8: f000 f9f6 bl 8004bd8 <USB_GetMode>
80047ec: 4603 mov r3, r0
80047ee: 2b00 cmp r3, #0
80047f0: d005 beq.n 80047fe <USB_SetCurrentMode+0x84>
80047f2: 68fb ldr r3, [r7, #12]
80047f4: 2bc7 cmp r3, #199 @ 0xc7
80047f6: d9f0 bls.n 80047da <USB_SetCurrentMode+0x60>
80047f8: e001 b.n 80047fe <USB_SetCurrentMode+0x84>
}
else
{
return HAL_ERROR;
80047fa: 2301 movs r3, #1
80047fc: e005 b.n 800480a <USB_SetCurrentMode+0x90>
}
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
80047fe: 68fb ldr r3, [r7, #12]
8004800: 2bc8 cmp r3, #200 @ 0xc8
8004802: d101 bne.n 8004808 <USB_SetCurrentMode+0x8e>
{
return HAL_ERROR;
8004804: 2301 movs r3, #1
8004806: e000 b.n 800480a <USB_SetCurrentMode+0x90>
}
return HAL_OK;
8004808: 2300 movs r3, #0
}
800480a: 4618 mov r0, r3
800480c: 3710 adds r7, #16
800480e: 46bd mov sp, r7
8004810: bd80 pop {r7, pc}
...
08004814 <USB_DevInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
8004814: b084 sub sp, #16
8004816: b580 push {r7, lr}
8004818: b086 sub sp, #24
800481a: af00 add r7, sp, #0
800481c: 6078 str r0, [r7, #4]
800481e: f107 0024 add.w r0, r7, #36 @ 0x24
8004822: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret = HAL_OK;
8004826: 2300 movs r3, #0
8004828: 75fb strb r3, [r7, #23]
uint32_t USBx_BASE = (uint32_t)USBx;
800482a: 687b ldr r3, [r7, #4]
800482c: 60fb str r3, [r7, #12]
uint32_t i;
for (i = 0U; i < 15U; i++)
800482e: 2300 movs r3, #0
8004830: 613b str r3, [r7, #16]
8004832: e009 b.n 8004848 <USB_DevInit+0x34>
{
USBx->DIEPTXF[i] = 0U;
8004834: 687a ldr r2, [r7, #4]
8004836: 693b ldr r3, [r7, #16]
8004838: 3340 adds r3, #64 @ 0x40
800483a: 009b lsls r3, r3, #2
800483c: 4413 add r3, r2
800483e: 2200 movs r2, #0
8004840: 605a str r2, [r3, #4]
for (i = 0U; i < 15U; i++)
8004842: 693b ldr r3, [r7, #16]
8004844: 3301 adds r3, #1
8004846: 613b str r3, [r7, #16]
8004848: 693b ldr r3, [r7, #16]
800484a: 2b0e cmp r3, #14
800484c: d9f2 bls.n 8004834 <USB_DevInit+0x20>
}
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
800484e: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
8004852: 2b00 cmp r3, #0
8004854: d11c bne.n 8004890 <USB_DevInit+0x7c>
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
8004856: 68fb ldr r3, [r7, #12]
8004858: f503 6300 add.w r3, r3, #2048 @ 0x800
800485c: 685b ldr r3, [r3, #4]
800485e: 68fa ldr r2, [r7, #12]
8004860: f502 6200 add.w r2, r2, #2048 @ 0x800
8004864: f043 0302 orr.w r3, r3, #2
8004868: 6053 str r3, [r2, #4]
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
800486a: 687b ldr r3, [r7, #4]
800486c: 6b9b ldr r3, [r3, #56] @ 0x38
800486e: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
8004872: 687b ldr r3, [r7, #4]
8004874: 639a str r2, [r3, #56] @ 0x38
/* B-peripheral session valid override enable */
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
8004876: 687b ldr r3, [r7, #4]
8004878: 681b ldr r3, [r3, #0]
800487a: f043 0240 orr.w r2, r3, #64 @ 0x40
800487e: 687b ldr r3, [r7, #4]
8004880: 601a str r2, [r3, #0]
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
8004882: 687b ldr r3, [r7, #4]
8004884: 681b ldr r3, [r3, #0]
8004886: f043 0280 orr.w r2, r3, #128 @ 0x80
800488a: 687b ldr r3, [r7, #4]
800488c: 601a str r2, [r3, #0]
800488e: e005 b.n 800489c <USB_DevInit+0x88>
}
else
{
/* Enable HW VBUS sensing */
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
8004890: 687b ldr r3, [r7, #4]
8004892: 6b9b ldr r3, [r3, #56] @ 0x38
8004894: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
8004898: 687b ldr r3, [r7, #4]
800489a: 639a str r2, [r3, #56] @ 0x38
}
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
800489c: 68fb ldr r3, [r7, #12]
800489e: f503 6360 add.w r3, r3, #3584 @ 0xe00
80048a2: 461a mov r2, r3
80048a4: 2300 movs r3, #0
80048a6: 6013 str r3, [r2, #0]
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
80048a8: 2103 movs r1, #3
80048aa: 6878 ldr r0, [r7, #4]
80048ac: f000 f95a bl 8004b64 <USB_SetDevSpeed>
/* Flush the FIFOs */
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
80048b0: 2110 movs r1, #16
80048b2: 6878 ldr r0, [r7, #4]
80048b4: f000 f8f6 bl 8004aa4 <USB_FlushTxFifo>
80048b8: 4603 mov r3, r0
80048ba: 2b00 cmp r3, #0
80048bc: d001 beq.n 80048c2 <USB_DevInit+0xae>
{
ret = HAL_ERROR;
80048be: 2301 movs r3, #1
80048c0: 75fb strb r3, [r7, #23]
}
if (USB_FlushRxFifo(USBx) != HAL_OK)
80048c2: 6878 ldr r0, [r7, #4]
80048c4: f000 f920 bl 8004b08 <USB_FlushRxFifo>
80048c8: 4603 mov r3, r0
80048ca: 2b00 cmp r3, #0
80048cc: d001 beq.n 80048d2 <USB_DevInit+0xbe>
{
ret = HAL_ERROR;
80048ce: 2301 movs r3, #1
80048d0: 75fb strb r3, [r7, #23]
}
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0U;
80048d2: 68fb ldr r3, [r7, #12]
80048d4: f503 6300 add.w r3, r3, #2048 @ 0x800
80048d8: 461a mov r2, r3
80048da: 2300 movs r3, #0
80048dc: 6113 str r3, [r2, #16]
USBx_DEVICE->DOEPMSK = 0U;
80048de: 68fb ldr r3, [r7, #12]
80048e0: f503 6300 add.w r3, r3, #2048 @ 0x800
80048e4: 461a mov r2, r3
80048e6: 2300 movs r3, #0
80048e8: 6153 str r3, [r2, #20]
USBx_DEVICE->DAINTMSK = 0U;
80048ea: 68fb ldr r3, [r7, #12]
80048ec: f503 6300 add.w r3, r3, #2048 @ 0x800
80048f0: 461a mov r2, r3
80048f2: 2300 movs r3, #0
80048f4: 61d3 str r3, [r2, #28]
for (i = 0U; i < cfg.dev_endpoints; i++)
80048f6: 2300 movs r3, #0
80048f8: 613b str r3, [r7, #16]
80048fa: e043 b.n 8004984 <USB_DevInit+0x170>
{
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
80048fc: 693b ldr r3, [r7, #16]
80048fe: 015a lsls r2, r3, #5
8004900: 68fb ldr r3, [r7, #12]
8004902: 4413 add r3, r2
8004904: f503 6310 add.w r3, r3, #2304 @ 0x900
8004908: 681b ldr r3, [r3, #0]
800490a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800490e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8004912: d118 bne.n 8004946 <USB_DevInit+0x132>
{
if (i == 0U)
8004914: 693b ldr r3, [r7, #16]
8004916: 2b00 cmp r3, #0
8004918: d10a bne.n 8004930 <USB_DevInit+0x11c>
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
800491a: 693b ldr r3, [r7, #16]
800491c: 015a lsls r2, r3, #5
800491e: 68fb ldr r3, [r7, #12]
8004920: 4413 add r3, r2
8004922: f503 6310 add.w r3, r3, #2304 @ 0x900
8004926: 461a mov r2, r3
8004928: f04f 6300 mov.w r3, #134217728 @ 0x8000000
800492c: 6013 str r3, [r2, #0]
800492e: e013 b.n 8004958 <USB_DevInit+0x144>
}
else
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
8004930: 693b ldr r3, [r7, #16]
8004932: 015a lsls r2, r3, #5
8004934: 68fb ldr r3, [r7, #12]
8004936: 4413 add r3, r2
8004938: f503 6310 add.w r3, r3, #2304 @ 0x900
800493c: 461a mov r2, r3
800493e: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
8004942: 6013 str r3, [r2, #0]
8004944: e008 b.n 8004958 <USB_DevInit+0x144>
}
}
else
{
USBx_INEP(i)->DIEPCTL = 0U;
8004946: 693b ldr r3, [r7, #16]
8004948: 015a lsls r2, r3, #5
800494a: 68fb ldr r3, [r7, #12]
800494c: 4413 add r3, r2
800494e: f503 6310 add.w r3, r3, #2304 @ 0x900
8004952: 461a mov r2, r3
8004954: 2300 movs r3, #0
8004956: 6013 str r3, [r2, #0]
}
USBx_INEP(i)->DIEPTSIZ = 0U;
8004958: 693b ldr r3, [r7, #16]
800495a: 015a lsls r2, r3, #5
800495c: 68fb ldr r3, [r7, #12]
800495e: 4413 add r3, r2
8004960: f503 6310 add.w r3, r3, #2304 @ 0x900
8004964: 461a mov r2, r3
8004966: 2300 movs r3, #0
8004968: 6113 str r3, [r2, #16]
USBx_INEP(i)->DIEPINT = 0xFB7FU;
800496a: 693b ldr r3, [r7, #16]
800496c: 015a lsls r2, r3, #5
800496e: 68fb ldr r3, [r7, #12]
8004970: 4413 add r3, r2
8004972: f503 6310 add.w r3, r3, #2304 @ 0x900
8004976: 461a mov r2, r3
8004978: f64f 337f movw r3, #64383 @ 0xfb7f
800497c: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
800497e: 693b ldr r3, [r7, #16]
8004980: 3301 adds r3, #1
8004982: 613b str r3, [r7, #16]
8004984: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8004988: 461a mov r2, r3
800498a: 693b ldr r3, [r7, #16]
800498c: 4293 cmp r3, r2
800498e: d3b5 bcc.n 80048fc <USB_DevInit+0xe8>
}
for (i = 0U; i < cfg.dev_endpoints; i++)
8004990: 2300 movs r3, #0
8004992: 613b str r3, [r7, #16]
8004994: e043 b.n 8004a1e <USB_DevInit+0x20a>
{
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
8004996: 693b ldr r3, [r7, #16]
8004998: 015a lsls r2, r3, #5
800499a: 68fb ldr r3, [r7, #12]
800499c: 4413 add r3, r2
800499e: f503 6330 add.w r3, r3, #2816 @ 0xb00
80049a2: 681b ldr r3, [r3, #0]
80049a4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80049a8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80049ac: d118 bne.n 80049e0 <USB_DevInit+0x1cc>
{
if (i == 0U)
80049ae: 693b ldr r3, [r7, #16]
80049b0: 2b00 cmp r3, #0
80049b2: d10a bne.n 80049ca <USB_DevInit+0x1b6>
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
80049b4: 693b ldr r3, [r7, #16]
80049b6: 015a lsls r2, r3, #5
80049b8: 68fb ldr r3, [r7, #12]
80049ba: 4413 add r3, r2
80049bc: f503 6330 add.w r3, r3, #2816 @ 0xb00
80049c0: 461a mov r2, r3
80049c2: f04f 6300 mov.w r3, #134217728 @ 0x8000000
80049c6: 6013 str r3, [r2, #0]
80049c8: e013 b.n 80049f2 <USB_DevInit+0x1de>
}
else
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
80049ca: 693b ldr r3, [r7, #16]
80049cc: 015a lsls r2, r3, #5
80049ce: 68fb ldr r3, [r7, #12]
80049d0: 4413 add r3, r2
80049d2: f503 6330 add.w r3, r3, #2816 @ 0xb00
80049d6: 461a mov r2, r3
80049d8: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
80049dc: 6013 str r3, [r2, #0]
80049de: e008 b.n 80049f2 <USB_DevInit+0x1de>
}
}
else
{
USBx_OUTEP(i)->DOEPCTL = 0U;
80049e0: 693b ldr r3, [r7, #16]
80049e2: 015a lsls r2, r3, #5
80049e4: 68fb ldr r3, [r7, #12]
80049e6: 4413 add r3, r2
80049e8: f503 6330 add.w r3, r3, #2816 @ 0xb00
80049ec: 461a mov r2, r3
80049ee: 2300 movs r3, #0
80049f0: 6013 str r3, [r2, #0]
}
USBx_OUTEP(i)->DOEPTSIZ = 0U;
80049f2: 693b ldr r3, [r7, #16]
80049f4: 015a lsls r2, r3, #5
80049f6: 68fb ldr r3, [r7, #12]
80049f8: 4413 add r3, r2
80049fa: f503 6330 add.w r3, r3, #2816 @ 0xb00
80049fe: 461a mov r2, r3
8004a00: 2300 movs r3, #0
8004a02: 6113 str r3, [r2, #16]
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
8004a04: 693b ldr r3, [r7, #16]
8004a06: 015a lsls r2, r3, #5
8004a08: 68fb ldr r3, [r7, #12]
8004a0a: 4413 add r3, r2
8004a0c: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004a10: 461a mov r2, r3
8004a12: f64f 337f movw r3, #64383 @ 0xfb7f
8004a16: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
8004a18: 693b ldr r3, [r7, #16]
8004a1a: 3301 adds r3, #1
8004a1c: 613b str r3, [r7, #16]
8004a1e: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8004a22: 461a mov r2, r3
8004a24: 693b ldr r3, [r7, #16]
8004a26: 4293 cmp r3, r2
8004a28: d3b5 bcc.n 8004996 <USB_DevInit+0x182>
}
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
8004a2a: 68fb ldr r3, [r7, #12]
8004a2c: f503 6300 add.w r3, r3, #2048 @ 0x800
8004a30: 691b ldr r3, [r3, #16]
8004a32: 68fa ldr r2, [r7, #12]
8004a34: f502 6200 add.w r2, r2, #2048 @ 0x800
8004a38: f423 7380 bic.w r3, r3, #256 @ 0x100
8004a3c: 6113 str r3, [r2, #16]
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
8004a3e: 687b ldr r3, [r7, #4]
8004a40: 2200 movs r2, #0
8004a42: 619a str r2, [r3, #24]
/* Clear any pending interrupts */
USBx->GINTSTS = 0xBFFFFFFFU;
8004a44: 687b ldr r3, [r7, #4]
8004a46: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
8004a4a: 615a str r2, [r3, #20]
/* Enable the common interrupts */
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
8004a4c: 687b ldr r3, [r7, #4]
8004a4e: 699b ldr r3, [r3, #24]
8004a50: f043 0210 orr.w r2, r3, #16
8004a54: 687b ldr r3, [r7, #4]
8004a56: 619a str r2, [r3, #24]
/* Enable interrupts matching to the Device mode ONLY */
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
8004a58: 687b ldr r3, [r7, #4]
8004a5a: 699a ldr r2, [r3, #24]
8004a5c: 4b10 ldr r3, [pc, #64] @ (8004aa0 <USB_DevInit+0x28c>)
8004a5e: 4313 orrs r3, r2
8004a60: 687a ldr r2, [r7, #4]
8004a62: 6193 str r3, [r2, #24]
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
if (cfg.Sof_enable != 0U)
8004a64: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
8004a68: 2b00 cmp r3, #0
8004a6a: d005 beq.n 8004a78 <USB_DevInit+0x264>
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
8004a6c: 687b ldr r3, [r7, #4]
8004a6e: 699b ldr r3, [r3, #24]
8004a70: f043 0208 orr.w r2, r3, #8
8004a74: 687b ldr r3, [r7, #4]
8004a76: 619a str r2, [r3, #24]
}
if (cfg.vbus_sensing_enable == 1U)
8004a78: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
8004a7c: 2b01 cmp r3, #1
8004a7e: d107 bne.n 8004a90 <USB_DevInit+0x27c>
{
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
8004a80: 687b ldr r3, [r7, #4]
8004a82: 699b ldr r3, [r3, #24]
8004a84: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8004a88: f043 0304 orr.w r3, r3, #4
8004a8c: 687a ldr r2, [r7, #4]
8004a8e: 6193 str r3, [r2, #24]
}
return ret;
8004a90: 7dfb ldrb r3, [r7, #23]
}
8004a92: 4618 mov r0, r3
8004a94: 3718 adds r7, #24
8004a96: 46bd mov sp, r7
8004a98: e8bd 4080 ldmia.w sp!, {r7, lr}
8004a9c: b004 add sp, #16
8004a9e: 4770 bx lr
8004aa0: 803c3800 .word 0x803c3800
08004aa4 <USB_FlushTxFifo>:
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
8004aa4: b480 push {r7}
8004aa6: b085 sub sp, #20
8004aa8: af00 add r7, sp, #0
8004aaa: 6078 str r0, [r7, #4]
8004aac: 6039 str r1, [r7, #0]
__IO uint32_t count = 0U;
8004aae: 2300 movs r3, #0
8004ab0: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8004ab2: 68fb ldr r3, [r7, #12]
8004ab4: 3301 adds r3, #1
8004ab6: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8004ab8: 68fb ldr r3, [r7, #12]
8004aba: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8004abe: d901 bls.n 8004ac4 <USB_FlushTxFifo+0x20>
{
return HAL_TIMEOUT;
8004ac0: 2303 movs r3, #3
8004ac2: e01b b.n 8004afc <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8004ac4: 687b ldr r3, [r7, #4]
8004ac6: 691b ldr r3, [r3, #16]
8004ac8: 2b00 cmp r3, #0
8004aca: daf2 bge.n 8004ab2 <USB_FlushTxFifo+0xe>
/* Flush TX Fifo */
count = 0U;
8004acc: 2300 movs r3, #0
8004ace: 60fb str r3, [r7, #12]
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
8004ad0: 683b ldr r3, [r7, #0]
8004ad2: 019b lsls r3, r3, #6
8004ad4: f043 0220 orr.w r2, r3, #32
8004ad8: 687b ldr r3, [r7, #4]
8004ada: 611a str r2, [r3, #16]
do
{
count++;
8004adc: 68fb ldr r3, [r7, #12]
8004ade: 3301 adds r3, #1
8004ae0: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8004ae2: 68fb ldr r3, [r7, #12]
8004ae4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8004ae8: d901 bls.n 8004aee <USB_FlushTxFifo+0x4a>
{
return HAL_TIMEOUT;
8004aea: 2303 movs r3, #3
8004aec: e006 b.n 8004afc <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
8004aee: 687b ldr r3, [r7, #4]
8004af0: 691b ldr r3, [r3, #16]
8004af2: f003 0320 and.w r3, r3, #32
8004af6: 2b20 cmp r3, #32
8004af8: d0f0 beq.n 8004adc <USB_FlushTxFifo+0x38>
return HAL_OK;
8004afa: 2300 movs r3, #0
}
8004afc: 4618 mov r0, r3
8004afe: 3714 adds r7, #20
8004b00: 46bd mov sp, r7
8004b02: f85d 7b04 ldr.w r7, [sp], #4
8004b06: 4770 bx lr
08004b08 <USB_FlushRxFifo>:
* @brief USB_FlushRxFifo Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
8004b08: b480 push {r7}
8004b0a: b085 sub sp, #20
8004b0c: af00 add r7, sp, #0
8004b0e: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8004b10: 2300 movs r3, #0
8004b12: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8004b14: 68fb ldr r3, [r7, #12]
8004b16: 3301 adds r3, #1
8004b18: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8004b1a: 68fb ldr r3, [r7, #12]
8004b1c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8004b20: d901 bls.n 8004b26 <USB_FlushRxFifo+0x1e>
{
return HAL_TIMEOUT;
8004b22: 2303 movs r3, #3
8004b24: e018 b.n 8004b58 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8004b26: 687b ldr r3, [r7, #4]
8004b28: 691b ldr r3, [r3, #16]
8004b2a: 2b00 cmp r3, #0
8004b2c: daf2 bge.n 8004b14 <USB_FlushRxFifo+0xc>
/* Flush RX Fifo */
count = 0U;
8004b2e: 2300 movs r3, #0
8004b30: 60fb str r3, [r7, #12]
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
8004b32: 687b ldr r3, [r7, #4]
8004b34: 2210 movs r2, #16
8004b36: 611a str r2, [r3, #16]
do
{
count++;
8004b38: 68fb ldr r3, [r7, #12]
8004b3a: 3301 adds r3, #1
8004b3c: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8004b3e: 68fb ldr r3, [r7, #12]
8004b40: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8004b44: d901 bls.n 8004b4a <USB_FlushRxFifo+0x42>
{
return HAL_TIMEOUT;
8004b46: 2303 movs r3, #3
8004b48: e006 b.n 8004b58 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
8004b4a: 687b ldr r3, [r7, #4]
8004b4c: 691b ldr r3, [r3, #16]
8004b4e: f003 0310 and.w r3, r3, #16
8004b52: 2b10 cmp r3, #16
8004b54: d0f0 beq.n 8004b38 <USB_FlushRxFifo+0x30>
return HAL_OK;
8004b56: 2300 movs r3, #0
}
8004b58: 4618 mov r0, r3
8004b5a: 3714 adds r7, #20
8004b5c: 46bd mov sp, r7
8004b5e: f85d 7b04 ldr.w r7, [sp], #4
8004b62: 4770 bx lr
08004b64 <USB_SetDevSpeed>:
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
8004b64: b480 push {r7}
8004b66: b085 sub sp, #20
8004b68: af00 add r7, sp, #0
8004b6a: 6078 str r0, [r7, #4]
8004b6c: 460b mov r3, r1
8004b6e: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
8004b70: 687b ldr r3, [r7, #4]
8004b72: 60fb str r3, [r7, #12]
USBx_DEVICE->DCFG |= speed;
8004b74: 68fb ldr r3, [r7, #12]
8004b76: f503 6300 add.w r3, r3, #2048 @ 0x800
8004b7a: 681a ldr r2, [r3, #0]
8004b7c: 78fb ldrb r3, [r7, #3]
8004b7e: 68f9 ldr r1, [r7, #12]
8004b80: f501 6100 add.w r1, r1, #2048 @ 0x800
8004b84: 4313 orrs r3, r2
8004b86: 600b str r3, [r1, #0]
return HAL_OK;
8004b88: 2300 movs r3, #0
}
8004b8a: 4618 mov r0, r3
8004b8c: 3714 adds r7, #20
8004b8e: 46bd mov sp, r7
8004b90: f85d 7b04 ldr.w r7, [sp], #4
8004b94: 4770 bx lr
08004b96 <USB_DevDisconnect>:
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
8004b96: b480 push {r7}
8004b98: b085 sub sp, #20
8004b9a: af00 add r7, sp, #0
8004b9c: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
8004b9e: 687b ldr r3, [r7, #4]
8004ba0: 60fb str r3, [r7, #12]
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
8004ba2: 68fb ldr r3, [r7, #12]
8004ba4: f503 6360 add.w r3, r3, #3584 @ 0xe00
8004ba8: 681b ldr r3, [r3, #0]
8004baa: 68fa ldr r2, [r7, #12]
8004bac: f502 6260 add.w r2, r2, #3584 @ 0xe00
8004bb0: f023 0303 bic.w r3, r3, #3
8004bb4: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
8004bb6: 68fb ldr r3, [r7, #12]
8004bb8: f503 6300 add.w r3, r3, #2048 @ 0x800
8004bbc: 685b ldr r3, [r3, #4]
8004bbe: 68fa ldr r2, [r7, #12]
8004bc0: f502 6200 add.w r2, r2, #2048 @ 0x800
8004bc4: f043 0302 orr.w r3, r3, #2
8004bc8: 6053 str r3, [r2, #4]
return HAL_OK;
8004bca: 2300 movs r3, #0
}
8004bcc: 4618 mov r0, r3
8004bce: 3714 adds r7, #20
8004bd0: 46bd mov sp, r7
8004bd2: f85d 7b04 ldr.w r7, [sp], #4
8004bd6: 4770 bx lr
08004bd8 <USB_GetMode>:
* This parameter can be one of these values:
* 0 : Host
* 1 : Device
*/
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
8004bd8: b480 push {r7}
8004bda: b083 sub sp, #12
8004bdc: af00 add r7, sp, #0
8004bde: 6078 str r0, [r7, #4]
return ((USBx->GINTSTS) & 0x1U);
8004be0: 687b ldr r3, [r7, #4]
8004be2: 695b ldr r3, [r3, #20]
8004be4: f003 0301 and.w r3, r3, #1
}
8004be8: 4618 mov r0, r3
8004bea: 370c adds r7, #12
8004bec: 46bd mov sp, r7
8004bee: f85d 7b04 ldr.w r7, [sp], #4
8004bf2: 4770 bx lr
08004bf4 <USB_CoreReset>:
* @brief Reset the USB Core (needed after USB clock settings change)
* @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
8004bf4: b480 push {r7}
8004bf6: b085 sub sp, #20
8004bf8: af00 add r7, sp, #0
8004bfa: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8004bfc: 2300 movs r3, #0
8004bfe: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8004c00: 68fb ldr r3, [r7, #12]
8004c02: 3301 adds r3, #1
8004c04: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8004c06: 68fb ldr r3, [r7, #12]
8004c08: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8004c0c: d901 bls.n 8004c12 <USB_CoreReset+0x1e>
{
return HAL_TIMEOUT;
8004c0e: 2303 movs r3, #3
8004c10: e01b b.n 8004c4a <USB_CoreReset+0x56>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8004c12: 687b ldr r3, [r7, #4]
8004c14: 691b ldr r3, [r3, #16]
8004c16: 2b00 cmp r3, #0
8004c18: daf2 bge.n 8004c00 <USB_CoreReset+0xc>
/* Core Soft Reset */
count = 0U;
8004c1a: 2300 movs r3, #0
8004c1c: 60fb str r3, [r7, #12]
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
8004c1e: 687b ldr r3, [r7, #4]
8004c20: 691b ldr r3, [r3, #16]
8004c22: f043 0201 orr.w r2, r3, #1
8004c26: 687b ldr r3, [r7, #4]
8004c28: 611a str r2, [r3, #16]
do
{
count++;
8004c2a: 68fb ldr r3, [r7, #12]
8004c2c: 3301 adds r3, #1
8004c2e: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8004c30: 68fb ldr r3, [r7, #12]
8004c32: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8004c36: d901 bls.n 8004c3c <USB_CoreReset+0x48>
{
return HAL_TIMEOUT;
8004c38: 2303 movs r3, #3
8004c3a: e006 b.n 8004c4a <USB_CoreReset+0x56>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
8004c3c: 687b ldr r3, [r7, #4]
8004c3e: 691b ldr r3, [r3, #16]
8004c40: f003 0301 and.w r3, r3, #1
8004c44: 2b01 cmp r3, #1
8004c46: d0f0 beq.n 8004c2a <USB_CoreReset+0x36>
return HAL_OK;
8004c48: 2300 movs r3, #0
}
8004c4a: 4618 mov r0, r3
8004c4c: 3714 adds r7, #20
8004c4e: 46bd mov sp, r7
8004c50: f85d 7b04 ldr.w r7, [sp], #4
8004c54: 4770 bx lr
08004c56 <memset>:
8004c56: 4402 add r2, r0
8004c58: 4603 mov r3, r0
8004c5a: 4293 cmp r3, r2
8004c5c: d100 bne.n 8004c60 <memset+0xa>
8004c5e: 4770 bx lr
8004c60: f803 1b01 strb.w r1, [r3], #1
8004c64: e7f9 b.n 8004c5a <memset+0x4>
...
08004c68 <__libc_init_array>:
8004c68: b570 push {r4, r5, r6, lr}
8004c6a: 4d0d ldr r5, [pc, #52] @ (8004ca0 <__libc_init_array+0x38>)
8004c6c: 4c0d ldr r4, [pc, #52] @ (8004ca4 <__libc_init_array+0x3c>)
8004c6e: 1b64 subs r4, r4, r5
8004c70: 10a4 asrs r4, r4, #2
8004c72: 2600 movs r6, #0
8004c74: 42a6 cmp r6, r4
8004c76: d109 bne.n 8004c8c <__libc_init_array+0x24>
8004c78: 4d0b ldr r5, [pc, #44] @ (8004ca8 <__libc_init_array+0x40>)
8004c7a: 4c0c ldr r4, [pc, #48] @ (8004cac <__libc_init_array+0x44>)
8004c7c: f000 f818 bl 8004cb0 <_init>
8004c80: 1b64 subs r4, r4, r5
8004c82: 10a4 asrs r4, r4, #2
8004c84: 2600 movs r6, #0
8004c86: 42a6 cmp r6, r4
8004c88: d105 bne.n 8004c96 <__libc_init_array+0x2e>
8004c8a: bd70 pop {r4, r5, r6, pc}
8004c8c: f855 3b04 ldr.w r3, [r5], #4
8004c90: 4798 blx r3
8004c92: 3601 adds r6, #1
8004c94: e7ee b.n 8004c74 <__libc_init_array+0xc>
8004c96: f855 3b04 ldr.w r3, [r5], #4
8004c9a: 4798 blx r3
8004c9c: 3601 adds r6, #1
8004c9e: e7f2 b.n 8004c86 <__libc_init_array+0x1e>
8004ca0: 08004d18 .word 0x08004d18
8004ca4: 08004d18 .word 0x08004d18
8004ca8: 08004d18 .word 0x08004d18
8004cac: 08004d1c .word 0x08004d1c
08004cb0 <_init>:
8004cb0: b5f8 push {r3, r4, r5, r6, r7, lr}
8004cb2: bf00 nop
8004cb4: bcf8 pop {r3, r4, r5, r6, r7}
8004cb6: bc08 pop {r3}
8004cb8: 469e mov lr, r3
8004cba: 4770 bx lr
08004cbc <_fini>:
8004cbc: b5f8 push {r3, r4, r5, r6, r7, lr}
8004cbe: bf00 nop
8004cc0: bcf8 pop {r3, r4, r5, r6, r7}
8004cc2: bc08 pop {r3}
8004cc4: 469e mov lr, r3
8004cc6: 4770 bx lr
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