302 lines
12 KiB
C
302 lines
12 KiB
C
/**
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******************************************************************************
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* @file mx25lm51245g.h
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* @author MCD Application Team
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* @brief This file contains all the description of the MX25LM51245G Octal memory.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __MX25LM51245G_H
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#define __MX25LM51245G_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup MX25LM51245G
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* @{
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*/
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/** @defgroup MX25LM51245G_Exported_Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup MX25LM51245G_Exported_Constants
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* @{
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*/
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/**
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* @brief MX25LM51245G Configuration
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*/
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#define MX25LM51245G_FLASH_SIZE 0x4000000 /* 512 MBits => 64 MBytes */
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#define MX25LM51245G_BLOCK_SIZE 0x10000 /* 1024 blocks of 64 KBytes */
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#define MX25LM51245G_SECTOR_SIZE 0x1000 /* 16384 sectors of 4 kBytes */
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#define MX25LM51245G_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */
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#define MX25LM51245G_DUMMY_CYCLES_READ 8
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#define MX25LM51245G_DUMMY_CYCLES_READ_OCTAL_66M 6
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#define MX25LM51245G_DUMMY_CYCLES_READ_OCTAL_84M 8
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#define MX25LM51245G_DUMMY_CYCLES_READ_OCTAL_104M 10
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#define MX25LM51245G_DUMMY_CYCLES_READ_OCTAL_133M 14
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#define MX25LM51245G_CR2_DC_66M MX25LM51245G_CR2_DC_6_CYCLES
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#define MX25LM51245G_CR2_DC_84M MX25LM51245G_CR2_DC_8_CYCLES
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#define MX25LM51245G_CR2_DC_104M MX25LM51245G_CR2_DC_10_CYCLES
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#define MX25LM51245G_CR2_DC_133M MX25LM51245G_CR2_DC_14_CYCLES
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#define MX25LM51245G_CHIP_ERASE_MAX_TIME 300000
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#define MX25LM51245G_BLOCK_ERASE_MAX_TIME 2000
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#define MX25LM51245G_SECTOR_ERASE_MAX_TIME 400
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#define MX25LM51245G_WRITE_REG_MAX_TIME 40
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/**
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* @brief MX25LM51245G Commands
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*/
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/* Read Operations */
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#define READ_CMD 0x03
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#define READ_4_BYTE_ADDR_CMD 0x13
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#define FAST_READ_CMD 0x0B
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#define FAST_READ_4_BYTE_ADDR_CMD 0x0C
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#define OCTAL_IO_READ_CMD 0xEC13
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#define OCTAL_IO_DTR_READ_CMD 0xEE11
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/* Program Operations */
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#define PAGE_PROG_CMD 0x02
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#define PAGE_PROG_4_BYTE_ADDR_CMD 0x12
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#define OCTAL_PAGE_PROG_CMD 0x12ED
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/* Erase Operations */
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#define SECTOR_ERASE_CMD 0x20
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#define SECTOR_ERASE_4_BYTE_ADDR_CMD 0x21
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#define OCTAL_SECTOR_ERASE_CMD 0x21DE
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#define BLOCK_ERASE_CMD 0xD8
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#define BLOCK_ERASE_4_BYTE_ADDR_CMD 0xDC
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#define OCTAL_BLOCK_ERASE_CMD 0xDC23
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#define CHIP_ERASE_CMD 0x60
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#define CHIP_ERASE_CMD_2 0xC7
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#define OCTAL_CHIP_ERASE_CMD 0x609F
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#define OCTAL_CHIP_ERASE_CMD_2 0xC738
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#define PROG_ERASE_RESUME_CMD 0x30
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#define PROG_ERASE_SUSPEND_CMD 0xB0
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#define OCTAL_PROG_ERASE_RESUME_CMD 0x30CF
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#define OCTAL_PROG_ERASE_SUSPEND_CMD 0xB04F
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/* Identification Operations */
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#define READ_ID_CMD 0x9F
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#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A
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#define OCTAL_READ_ID_CMD 0x9F60
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#define OCTAL_READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5AA5
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/* Write Operations */
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#define WRITE_ENABLE_CMD 0x06
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#define WRITE_DISABLE_CMD 0x04
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#define OCTAL_WRITE_ENABLE_CMD 0x06F9
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#define OCTAL_WRITE_DISABLE_CMD 0x04FB
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/* Register Operations */
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#define READ_STATUS_REG_CMD 0x05
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#define READ_CFG_REG_CMD 0x15
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#define WRITE_STATUS_CFG_REG_CMD 0x01
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#define OCTAL_READ_STATUS_REG_CMD 0x05FA
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#define OCTAL_READ_CFG_REG_CMD 0x15EA
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#define OCTAL_WRITE_STATUS_CFG_REG_CMD 0x01FE
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#define READ_CFG_REG_2_CMD 0x71
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#define WRITE_CFG_REG_2_CMD 0x72
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#define OCTAL_READ_CFG_REG_2_CMD 0x718E
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#define OCTAL_WRITE_CFG_REG_2_CMD 0x728D
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#define READ_FAST_BOOT_REG_CMD 0x16
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#define WRITE_FAST_BOOT_REG 0x17
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#define ERASE_FAST_BOOT_REG 0x18
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#define OCTAL_READ_FAST_BOOT_REG_CMD 0x16E9
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#define OCTAL_WRITE_FAST_BOOT_REG 0x17E8
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#define OCTAL_ERASE_FAST_BOOT_REG 0x18E7
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#define READ_SEC_REG_CMD 0x2B
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#define WRITE_SEC_REG_CMD 0x2F
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#define OCTAL_READ_SECURITY_REG_CMD 0x2BD4
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#define OCTAL_WRITE_SECURITY_REG_CMD 0x2FD0
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#define READ_LOCK_REG_CMD 0x2D
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#define WRITE_LOCK_REG_CMD 0x2C
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#define OCTAL_READ_LOCK_REG_CMD 0x2DD2
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#define OCTAL_WRITE_LOCK_REG_CMD 0x2CD3
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#define READ_SPB_STATUS_CMD 0xE2
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#define PROG_SPB_BIT_CMD 0xE3
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#define ERASE_ALL_SPB_BIT_CMD 0xE4
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#define OCTAL_READ_SPB_STATUS_CMD 0xE21D
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#define OCTAL_PROG_SPB_BIT_CMD 0xE31C
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#define OCTAL_ERASE_ALL_SPB_BIT_CMD 0xE41B
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#define READ_DPB_REG_CMD 0xE0
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#define WRITE_DPB_REG_CMD 0xE1
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#define OCTAL_READ_DPB_REG_CMD 0xE01F
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#define OCTAL_WRITE_DPB_REG_CMD 0xE11E
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/* Power Down Operations */
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#define DEEP_POWER_DOWN_CMD 0xB9
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#define RELEASE_DEEP_POWER_DOWN_CMD 0xAB
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#define OCTAL_ENTER_DEEP_POWER_DOWN_CMD 0xB946
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/* Burst Operations */
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#define SET_BURST_LENGTH_CMD 0xC0
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#define OCTAL_SET_BURST_LENGTH_CMD 0xC03F
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/* One-Time Programmable Operations */
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#define ENTER_SECURED_OTP_CMD 0xB1
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#define EXIT_SECURED_OTP_CMD 0xC1
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#define OCTAL_ENTER_SECURED_OTP_CMD 0xB14E
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#define OCTAL_EXIT_SECURED_OTP_CMD 0xC13E
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/* No Operation */
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#define NO_OPERATION_CMD 0x00
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#define OCTAL_NO_OPERATION_CMD 0x00FF
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/* Reset Operations */
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#define RESET_ENABLE_CMD 0x66
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#define RESET_MEMORY_CMD 0x99
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#define OCTAL_RESET_ENABLE_CMD 0x6699
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#define OCTAL_RESET_MEMORY_CMD 0x9966
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/* Protection Operations */
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#define WRITE_PROTECT_SEL_CMD 0x68
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#define OCTAL_WRITE_PROTECT_SEL_CMD 0x6897
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#define GANG_BLOCK_LOCK_CMD 0x7E
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#define GANG_BLOCK_UNLOCK_CMD 0x98
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#define OCTAL_GANG_BLOCK_LOCK_CMD 0x7E81
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#define OCTAL_GANG_BLOCK_UNLOCK_CMD 0x9867
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/**
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* @brief MX25LM51245G Registers
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*/
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/* Status Register */
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#define MX25LM51245G_SR_WIP ((uint8_t)0x01) /*!< Write in progress */
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#define MX25LM51245G_SR_WEL ((uint8_t)0x02) /*!< Write enable latch */
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#define MX25LM51245G_SR_BP ((uint8_t)0x3C) /*!< Block protect */
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/* Configuration Register 1 */
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#define MX25LM51245G_CR1_ODS ((uint8_t)0x07) /*!< Output driver strength */
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#define MX25LM51245G_CR1_TB ((uint8_t)0x08) /*!< Top / bottom */
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/* Configuration Register 2 */
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/* Address : 0x00000000 */
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#define MX25LM51245G_CR2_REG1_ADDR ((uint32_t)0x00000000) /*!< CR2 register address 0x00000000 */
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#define MX25LM51245G_CR2_SOPI ((uint8_t)0x01) /*!< STR OPI Enable */
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#define MX25LM51245G_CR2_DOPI ((uint8_t)0x02) /*!< DTR OPI Enable */
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/* Address : 0x00000200 */
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#define MX25LM51245G_CR2_REG2_ADDR ((uint32_t)0x00000200) /*!< CR2 register address 0x00000200 */
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#define MX25LM51245G_CR2_DQSPRC ((uint8_t)0x01) /*!< DTR DQS pre-cycle */
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#define MX25LM51245G_CR2_DOS ((uint8_t)0x02) /*!< DQS on STR mode */
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/* Address : 0x00000300 */
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#define MX25LM51245G_CR2_REG3_ADDR ((uint32_t)0x00000300) /*!< CR2 register address 0x00000300 */
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#define MX25LM51245G_CR2_DC ((uint8_t)0x07) /*!< Dummy cycle */
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#define MX25LM51245G_CR2_DC_20_CYCLES ((uint8_t)0x00) /*!< 20 Dummy cycles */
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#define MX25LM51245G_CR2_DC_18_CYCLES ((uint8_t)0x01) /*!< 18 Dummy cycles */
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#define MX25LM51245G_CR2_DC_16_CYCLES ((uint8_t)0x02) /*!< 16 Dummy cycles */
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#define MX25LM51245G_CR2_DC_14_CYCLES ((uint8_t)0x03) /*!< 14 Dummy cycles */
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#define MX25LM51245G_CR2_DC_12_CYCLES ((uint8_t)0x04) /*!< 12 Dummy cycles */
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#define MX25LM51245G_CR2_DC_10_CYCLES ((uint8_t)0x05) /*!< 10 Dummy cycles */
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#define MX25LM51245G_CR2_DC_8_CYCLES ((uint8_t)0x06) /*!< 8 Dummy cycles */
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#define MX25LM51245G_CR2_DC_6_CYCLES ((uint8_t)0x07) /*!< 6 Dummy cycles */
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/* Address : 0x00000500 */
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#define MX25LM51245G_CR2_REG4_ADDR ((uint32_t)0x00000500) /*!< CR2 register address 0x00000500 */
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#define MX25LM51245G_CR2_PPTSEL ((uint8_t)0x01) /*!< Preamble pattern selection */
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/* Address : 0x40000000 */
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#define MX25LM51245G_CR2_REG5_ADDR ((uint32_t)0x40000000) /*!< CR2 register address 0x40000000 */
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#define MX25LM51245G_CR2_DEFSOPI ((uint8_t)0x01) /*!< Enable SOPI after power on reset */
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#define MX25LM51245G_CR2_DEFDOPI ((uint8_t)0x02) /*!< Enable DOPI after power on reset */
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/* Security Register */
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#define MX25LM51245G_SECR_SOI ((uint8_t)0x01) /*!< Secured OTP indicator */
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#define MX25LM51245G_SECR_LDSO ((uint8_t)0x02) /*!< Lock-down secured OTP */
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#define MX25LM51245G_SECR_PSB ((uint8_t)0x04) /*!< Program suspend bit */
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#define MX25LM51245G_SECR_ESB ((uint8_t)0x08) /*!< Erase suspend bit */
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#define MX25LM51245G_SECR_P_FAIL ((uint8_t)0x20) /*!< Program fail flag */
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#define MX25LM51245G_SECR_E_FAIL ((uint8_t)0x40) /*!< Erase fail flag */
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#define MX25LM51245G_SECR_WPSEL ((uint8_t)0x40) /*!< Write protection selection */
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/**
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* @}
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*/
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/** @defgroup MX25LM51245G_Exported_Functions
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* @{
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __MX25LM51245G_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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