134 lines
4.0 KiB
C
134 lines
4.0 KiB
C
/**
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******************************************************************************
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* @file iss66wvh8m8.h
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* @author MCD Application Team
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* @brief This file contains all the description of the ISS66WVH8M8 Octal memory.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __ISS66WVH8M8_H
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#define __ISS66WVH8M8_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup ISS66WVH8M8
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* @{
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*/
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/** @defgroup ISS66WVH8M8_Exported_Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup ISS66WVH8M8_Exported_Constants
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* @{
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*/
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/**
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* @brief ISS66WVH8M8 Configuration
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*/
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#define ISS66WVH8M8_RAM_SIZE 0x800000 /* 64 MBits => 8 MBytes */
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#define ISS66WVH8M8_LATENCY_83M 3
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#define ISS66WVH8M8_LATENCY_100M 4
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#define ISS66WVH8M8_LATENCY_133M 5
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#define ISS66WVH8M8_LATENCY_166M 6
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#define ISS66WVH8M8_CR0_LATENCY_83M ISS66WVH8M8_CR0_IL_3_CLOCK
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#define ISS66WVH8M8_CR0_LATENCY_100M ISS66WVH8M8_CR0_IL_4_CLOCK
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#define ISS66WVH8M8_CR0_LATENCY_133M ISS66WVH8M8_CR0_IL_5_CLOCK
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#define ISS66WVH8M8_CR0_LATENCY_166M ISS66WVH8M8_CR0_IL_6_CLOCK
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/**
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* @brief ISS66WVH8M8 Registers
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*/
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/* Device Identification Register 0 */
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#define ISS66WVH8M8_DIR0_ADDRESS ((uint32_t)0x00000000)
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#define ISS66WVH8M8_DIR0_MANUFACTURER ((uint16_t)0x000F) /*!< Manufacturer */
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#define ISS66WVH8M8_DIR0_CADC ((uint16_t)0x00F0) /*!< Column Address Bit Count */
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#define ISS66WVH8M8_DIR0_RABC ((uint16_t)0x1F00) /*!< Row Address Bit Count */
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#define ISS66WVH8M8_DIR0_DADDR ((uint16_t)0xC000) /*!< Die Address */
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/* Device Identification Register 1 */
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#define ISS66WVH8M8_DIR1_ADDRESS ((uint32_t)0x00000001)
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#define ISS66WVH8M8_DIR1_DTYPE ((uint16_t)0x000F) /*!< Device Type */
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/* Configuration Register 0 */
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#define ISS66WVH8M8_CR0_ADDRESS ((uint32_t)0x00000800)
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#define ISS66WVH8M8_CR0_BLENGTH ((uint16_t)0x0003) /*!< Burst length */
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#define ISS66WVH8M8_CR0_HBE ((uint16_t)0x0004) /*!< Hybrid burst enable */
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#define ISS66WVH8M8_CR0_FLE ((uint16_t)0x0008) /*!< Fixed latency enable */
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#define ISS66WVH8M8_CR0_IL ((uint16_t)0x00F0) /*!< Initial latency */
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#define ISS66WVH8M8_CR0_IL_5_CLOCK ((uint16_t)0x0000) /*!< 5 clock latency */
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#define ISS66WVH8M8_CR0_IL_6_CLOCK ((uint16_t)0x0010) /*!< 6 clock latency */
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#define ISS66WVH8M8_CR0_IL_3_CLOCK ((uint16_t)0x00E0) /*!< 3 clock latency */
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#define ISS66WVH8M8_CR0_IL_4_CLOCK ((uint16_t)0x00F0) /*!< 4 clock latency */
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#define ISS66WVH8M8_CR0_DS ((uint16_t)0x7000) /*!< Drive strength */
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#define ISS66WVH8M8_CR0_DPDE ((uint16_t)0x8000) /*!< Deep Power down enable */
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/* Configuration Register 1 */
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#define ISS66WVH8M8_CR1_ADDRESS ((uint32_t)0x00000801)
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#define ISS66WVH8M8_CR1_DRI ((uint16_t)0x0003) /*!< Distributed refresh interval */
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/**
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* @}
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*/
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/** @defgroup ISS66WVH8M8_Exported_Functions
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* @{
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ISS66WVH8M8_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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