P2_SETR2.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00007ce0 08000190 08000190 00001190 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000084 08007e70 08007e70 00008e70 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08007ef4 08007ef4 00009060 2**0 CONTENTS, READONLY 4 .ARM 00000008 08007ef4 08007ef4 00008ef4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08007efc 08007efc 00009060 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08007efc 08007efc 00008efc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08007f00 08007f00 00008f00 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000060 20000000 08007f04 00009000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00008c14 20000060 08007f64 00009060 2**2 ALLOC 10 ._user_heap_stack 00000604 20008c74 08007f64 00009c74 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 00009060 2**0 CONTENTS, READONLY 12 .debug_info 00027cd0 00000000 00000000 00009090 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004e38 00000000 00000000 00030d60 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00002360 00000000 00000000 00035b98 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001b91 00000000 00000000 00037ef8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000052ec 00000000 00000000 00039a89 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0002721c 00000000 00000000 0003ed75 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00108686 00000000 00000000 00065f91 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0016e617 2**0 CONTENTS, READONLY 20 .debug_frame 00009b5c 00000000 00000000 0016e65c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000061 00000000 00000000 001781b8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000190 <__do_global_dtors_aux>: 8000190: b510 push {r4, lr} 8000192: 4c05 ldr r4, [pc, #20] @ (80001a8 <__do_global_dtors_aux+0x18>) 8000194: 7823 ldrb r3, [r4, #0] 8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16> 8000198: 4b04 ldr r3, [pc, #16] @ (80001ac <__do_global_dtors_aux+0x1c>) 800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12> 800019c: 4804 ldr r0, [pc, #16] @ (80001b0 <__do_global_dtors_aux+0x20>) 800019e: f3af 8000 nop.w 80001a2: 2301 movs r3, #1 80001a4: 7023 strb r3, [r4, #0] 80001a6: bd10 pop {r4, pc} 80001a8: 20000060 .word 0x20000060 80001ac: 00000000 .word 0x00000000 80001b0: 08007e58 .word 0x08007e58 080001b4 : 80001b4: b508 push {r3, lr} 80001b6: 4b03 ldr r3, [pc, #12] @ (80001c4 ) 80001b8: b11b cbz r3, 80001c2 80001ba: 4903 ldr r1, [pc, #12] @ (80001c8 ) 80001bc: 4803 ldr r0, [pc, #12] @ (80001cc ) 80001be: f3af 8000 nop.w 80001c2: bd08 pop {r3, pc} 80001c4: 00000000 .word 0x00000000 80001c8: 20000064 .word 0x20000064 80001cc: 08007e58 .word 0x08007e58 080001d0 <__aeabi_uldivmod>: 80001d0: b953 cbnz r3, 80001e8 <__aeabi_uldivmod+0x18> 80001d2: b94a cbnz r2, 80001e8 <__aeabi_uldivmod+0x18> 80001d4: 2900 cmp r1, #0 80001d6: bf08 it eq 80001d8: 2800 cmpeq r0, #0 80001da: bf1c itt ne 80001dc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80001e0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80001e4: f000 b988 b.w 80004f8 <__aeabi_idiv0> 80001e8: f1ad 0c08 sub.w ip, sp, #8 80001ec: e96d ce04 strd ip, lr, [sp, #-16]! 80001f0: f000 f806 bl 8000200 <__udivmoddi4> 80001f4: f8dd e004 ldr.w lr, [sp, #4] 80001f8: e9dd 2302 ldrd r2, r3, [sp, #8] 80001fc: b004 add sp, #16 80001fe: 4770 bx lr 08000200 <__udivmoddi4>: 8000200: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000204: 9d08 ldr r5, [sp, #32] 8000206: 468e mov lr, r1 8000208: 4604 mov r4, r0 800020a: 4688 mov r8, r1 800020c: 2b00 cmp r3, #0 800020e: d14a bne.n 80002a6 <__udivmoddi4+0xa6> 8000210: 428a cmp r2, r1 8000212: 4617 mov r7, r2 8000214: d962 bls.n 80002dc <__udivmoddi4+0xdc> 8000216: fab2 f682 clz r6, r2 800021a: b14e cbz r6, 8000230 <__udivmoddi4+0x30> 800021c: f1c6 0320 rsb r3, r6, #32 8000220: fa01 f806 lsl.w r8, r1, r6 8000224: fa20 f303 lsr.w r3, r0, r3 8000228: 40b7 lsls r7, r6 800022a: ea43 0808 orr.w r8, r3, r8 800022e: 40b4 lsls r4, r6 8000230: ea4f 4e17 mov.w lr, r7, lsr #16 8000234: fa1f fc87 uxth.w ip, r7 8000238: fbb8 f1fe udiv r1, r8, lr 800023c: 0c23 lsrs r3, r4, #16 800023e: fb0e 8811 mls r8, lr, r1, r8 8000242: ea43 4308 orr.w r3, r3, r8, lsl #16 8000246: fb01 f20c mul.w r2, r1, ip 800024a: 429a cmp r2, r3 800024c: d909 bls.n 8000262 <__udivmoddi4+0x62> 800024e: 18fb adds r3, r7, r3 8000250: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000254: f080 80ea bcs.w 800042c <__udivmoddi4+0x22c> 8000258: 429a cmp r2, r3 800025a: f240 80e7 bls.w 800042c <__udivmoddi4+0x22c> 800025e: 3902 subs r1, #2 8000260: 443b add r3, r7 8000262: 1a9a subs r2, r3, r2 8000264: b2a3 uxth r3, r4 8000266: fbb2 f0fe udiv r0, r2, lr 800026a: fb0e 2210 mls r2, lr, r0, r2 800026e: ea43 4302 orr.w r3, r3, r2, lsl #16 8000272: fb00 fc0c mul.w ip, r0, ip 8000276: 459c cmp ip, r3 8000278: d909 bls.n 800028e <__udivmoddi4+0x8e> 800027a: 18fb adds r3, r7, r3 800027c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 8000280: f080 80d6 bcs.w 8000430 <__udivmoddi4+0x230> 8000284: 459c cmp ip, r3 8000286: f240 80d3 bls.w 8000430 <__udivmoddi4+0x230> 800028a: 443b add r3, r7 800028c: 3802 subs r0, #2 800028e: ea40 4001 orr.w r0, r0, r1, lsl #16 8000292: eba3 030c sub.w r3, r3, ip 8000296: 2100 movs r1, #0 8000298: b11d cbz r5, 80002a2 <__udivmoddi4+0xa2> 800029a: 40f3 lsrs r3, r6 800029c: 2200 movs r2, #0 800029e: e9c5 3200 strd r3, r2, [r5] 80002a2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002a6: 428b cmp r3, r1 80002a8: d905 bls.n 80002b6 <__udivmoddi4+0xb6> 80002aa: b10d cbz r5, 80002b0 <__udivmoddi4+0xb0> 80002ac: e9c5 0100 strd r0, r1, [r5] 80002b0: 2100 movs r1, #0 80002b2: 4608 mov r0, r1 80002b4: e7f5 b.n 80002a2 <__udivmoddi4+0xa2> 80002b6: fab3 f183 clz r1, r3 80002ba: 2900 cmp r1, #0 80002bc: d146 bne.n 800034c <__udivmoddi4+0x14c> 80002be: 4573 cmp r3, lr 80002c0: d302 bcc.n 80002c8 <__udivmoddi4+0xc8> 80002c2: 4282 cmp r2, r0 80002c4: f200 8105 bhi.w 80004d2 <__udivmoddi4+0x2d2> 80002c8: 1a84 subs r4, r0, r2 80002ca: eb6e 0203 sbc.w r2, lr, r3 80002ce: 2001 movs r0, #1 80002d0: 4690 mov r8, r2 80002d2: 2d00 cmp r5, #0 80002d4: d0e5 beq.n 80002a2 <__udivmoddi4+0xa2> 80002d6: e9c5 4800 strd r4, r8, [r5] 80002da: e7e2 b.n 80002a2 <__udivmoddi4+0xa2> 80002dc: 2a00 cmp r2, #0 80002de: f000 8090 beq.w 8000402 <__udivmoddi4+0x202> 80002e2: fab2 f682 clz r6, r2 80002e6: 2e00 cmp r6, #0 80002e8: f040 80a4 bne.w 8000434 <__udivmoddi4+0x234> 80002ec: 1a8a subs r2, r1, r2 80002ee: 0c03 lsrs r3, r0, #16 80002f0: ea4f 4e17 mov.w lr, r7, lsr #16 80002f4: b280 uxth r0, r0 80002f6: b2bc uxth r4, r7 80002f8: 2101 movs r1, #1 80002fa: fbb2 fcfe udiv ip, r2, lr 80002fe: fb0e 221c mls r2, lr, ip, r2 8000302: ea43 4302 orr.w r3, r3, r2, lsl #16 8000306: fb04 f20c mul.w r2, r4, ip 800030a: 429a cmp r2, r3 800030c: d907 bls.n 800031e <__udivmoddi4+0x11e> 800030e: 18fb adds r3, r7, r3 8000310: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000314: d202 bcs.n 800031c <__udivmoddi4+0x11c> 8000316: 429a cmp r2, r3 8000318: f200 80e0 bhi.w 80004dc <__udivmoddi4+0x2dc> 800031c: 46c4 mov ip, r8 800031e: 1a9b subs r3, r3, r2 8000320: fbb3 f2fe udiv r2, r3, lr 8000324: fb0e 3312 mls r3, lr, r2, r3 8000328: ea40 4303 orr.w r3, r0, r3, lsl #16 800032c: fb02 f404 mul.w r4, r2, r4 8000330: 429c cmp r4, r3 8000332: d907 bls.n 8000344 <__udivmoddi4+0x144> 8000334: 18fb adds r3, r7, r3 8000336: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800033a: d202 bcs.n 8000342 <__udivmoddi4+0x142> 800033c: 429c cmp r4, r3 800033e: f200 80ca bhi.w 80004d6 <__udivmoddi4+0x2d6> 8000342: 4602 mov r2, r0 8000344: 1b1b subs r3, r3, r4 8000346: ea42 400c orr.w r0, r2, ip, lsl #16 800034a: e7a5 b.n 8000298 <__udivmoddi4+0x98> 800034c: f1c1 0620 rsb r6, r1, #32 8000350: 408b lsls r3, r1 8000352: fa22 f706 lsr.w r7, r2, r6 8000356: 431f orrs r7, r3 8000358: fa0e f401 lsl.w r4, lr, r1 800035c: fa20 f306 lsr.w r3, r0, r6 8000360: fa2e fe06 lsr.w lr, lr, r6 8000364: ea4f 4917 mov.w r9, r7, lsr #16 8000368: 4323 orrs r3, r4 800036a: fa00 f801 lsl.w r8, r0, r1 800036e: fa1f fc87 uxth.w ip, r7 8000372: fbbe f0f9 udiv r0, lr, r9 8000376: 0c1c lsrs r4, r3, #16 8000378: fb09 ee10 mls lr, r9, r0, lr 800037c: ea44 440e orr.w r4, r4, lr, lsl #16 8000380: fb00 fe0c mul.w lr, r0, ip 8000384: 45a6 cmp lr, r4 8000386: fa02 f201 lsl.w r2, r2, r1 800038a: d909 bls.n 80003a0 <__udivmoddi4+0x1a0> 800038c: 193c adds r4, r7, r4 800038e: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 8000392: f080 809c bcs.w 80004ce <__udivmoddi4+0x2ce> 8000396: 45a6 cmp lr, r4 8000398: f240 8099 bls.w 80004ce <__udivmoddi4+0x2ce> 800039c: 3802 subs r0, #2 800039e: 443c add r4, r7 80003a0: eba4 040e sub.w r4, r4, lr 80003a4: fa1f fe83 uxth.w lr, r3 80003a8: fbb4 f3f9 udiv r3, r4, r9 80003ac: fb09 4413 mls r4, r9, r3, r4 80003b0: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003b4: fb03 fc0c mul.w ip, r3, ip 80003b8: 45a4 cmp ip, r4 80003ba: d908 bls.n 80003ce <__udivmoddi4+0x1ce> 80003bc: 193c adds r4, r7, r4 80003be: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003c2: f080 8082 bcs.w 80004ca <__udivmoddi4+0x2ca> 80003c6: 45a4 cmp ip, r4 80003c8: d97f bls.n 80004ca <__udivmoddi4+0x2ca> 80003ca: 3b02 subs r3, #2 80003cc: 443c add r4, r7 80003ce: ea43 4000 orr.w r0, r3, r0, lsl #16 80003d2: eba4 040c sub.w r4, r4, ip 80003d6: fba0 ec02 umull lr, ip, r0, r2 80003da: 4564 cmp r4, ip 80003dc: 4673 mov r3, lr 80003de: 46e1 mov r9, ip 80003e0: d362 bcc.n 80004a8 <__udivmoddi4+0x2a8> 80003e2: d05f beq.n 80004a4 <__udivmoddi4+0x2a4> 80003e4: b15d cbz r5, 80003fe <__udivmoddi4+0x1fe> 80003e6: ebb8 0203 subs.w r2, r8, r3 80003ea: eb64 0409 sbc.w r4, r4, r9 80003ee: fa04 f606 lsl.w r6, r4, r6 80003f2: fa22 f301 lsr.w r3, r2, r1 80003f6: 431e orrs r6, r3 80003f8: 40cc lsrs r4, r1 80003fa: e9c5 6400 strd r6, r4, [r5] 80003fe: 2100 movs r1, #0 8000400: e74f b.n 80002a2 <__udivmoddi4+0xa2> 8000402: fbb1 fcf2 udiv ip, r1, r2 8000406: 0c01 lsrs r1, r0, #16 8000408: ea41 410e orr.w r1, r1, lr, lsl #16 800040c: b280 uxth r0, r0 800040e: ea40 4201 orr.w r2, r0, r1, lsl #16 8000412: 463b mov r3, r7 8000414: 4638 mov r0, r7 8000416: 463c mov r4, r7 8000418: 46b8 mov r8, r7 800041a: 46be mov lr, r7 800041c: 2620 movs r6, #32 800041e: fbb1 f1f7 udiv r1, r1, r7 8000422: eba2 0208 sub.w r2, r2, r8 8000426: ea41 410c orr.w r1, r1, ip, lsl #16 800042a: e766 b.n 80002fa <__udivmoddi4+0xfa> 800042c: 4601 mov r1, r0 800042e: e718 b.n 8000262 <__udivmoddi4+0x62> 8000430: 4610 mov r0, r2 8000432: e72c b.n 800028e <__udivmoddi4+0x8e> 8000434: f1c6 0220 rsb r2, r6, #32 8000438: fa2e f302 lsr.w r3, lr, r2 800043c: 40b7 lsls r7, r6 800043e: 40b1 lsls r1, r6 8000440: fa20 f202 lsr.w r2, r0, r2 8000444: ea4f 4e17 mov.w lr, r7, lsr #16 8000448: 430a orrs r2, r1 800044a: fbb3 f8fe udiv r8, r3, lr 800044e: b2bc uxth r4, r7 8000450: fb0e 3318 mls r3, lr, r8, r3 8000454: 0c11 lsrs r1, r2, #16 8000456: ea41 4103 orr.w r1, r1, r3, lsl #16 800045a: fb08 f904 mul.w r9, r8, r4 800045e: 40b0 lsls r0, r6 8000460: 4589 cmp r9, r1 8000462: ea4f 4310 mov.w r3, r0, lsr #16 8000466: b280 uxth r0, r0 8000468: d93e bls.n 80004e8 <__udivmoddi4+0x2e8> 800046a: 1879 adds r1, r7, r1 800046c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 8000470: d201 bcs.n 8000476 <__udivmoddi4+0x276> 8000472: 4589 cmp r9, r1 8000474: d81f bhi.n 80004b6 <__udivmoddi4+0x2b6> 8000476: eba1 0109 sub.w r1, r1, r9 800047a: fbb1 f9fe udiv r9, r1, lr 800047e: fb09 f804 mul.w r8, r9, r4 8000482: fb0e 1119 mls r1, lr, r9, r1 8000486: b292 uxth r2, r2 8000488: ea42 4201 orr.w r2, r2, r1, lsl #16 800048c: 4542 cmp r2, r8 800048e: d229 bcs.n 80004e4 <__udivmoddi4+0x2e4> 8000490: 18ba adds r2, r7, r2 8000492: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 8000496: d2c4 bcs.n 8000422 <__udivmoddi4+0x222> 8000498: 4542 cmp r2, r8 800049a: d2c2 bcs.n 8000422 <__udivmoddi4+0x222> 800049c: f1a9 0102 sub.w r1, r9, #2 80004a0: 443a add r2, r7 80004a2: e7be b.n 8000422 <__udivmoddi4+0x222> 80004a4: 45f0 cmp r8, lr 80004a6: d29d bcs.n 80003e4 <__udivmoddi4+0x1e4> 80004a8: ebbe 0302 subs.w r3, lr, r2 80004ac: eb6c 0c07 sbc.w ip, ip, r7 80004b0: 3801 subs r0, #1 80004b2: 46e1 mov r9, ip 80004b4: e796 b.n 80003e4 <__udivmoddi4+0x1e4> 80004b6: eba7 0909 sub.w r9, r7, r9 80004ba: 4449 add r1, r9 80004bc: f1a8 0c02 sub.w ip, r8, #2 80004c0: fbb1 f9fe udiv r9, r1, lr 80004c4: fb09 f804 mul.w r8, r9, r4 80004c8: e7db b.n 8000482 <__udivmoddi4+0x282> 80004ca: 4673 mov r3, lr 80004cc: e77f b.n 80003ce <__udivmoddi4+0x1ce> 80004ce: 4650 mov r0, sl 80004d0: e766 b.n 80003a0 <__udivmoddi4+0x1a0> 80004d2: 4608 mov r0, r1 80004d4: e6fd b.n 80002d2 <__udivmoddi4+0xd2> 80004d6: 443b add r3, r7 80004d8: 3a02 subs r2, #2 80004da: e733 b.n 8000344 <__udivmoddi4+0x144> 80004dc: f1ac 0c02 sub.w ip, ip, #2 80004e0: 443b add r3, r7 80004e2: e71c b.n 800031e <__udivmoddi4+0x11e> 80004e4: 4649 mov r1, r9 80004e6: e79c b.n 8000422 <__udivmoddi4+0x222> 80004e8: eba1 0109 sub.w r1, r1, r9 80004ec: 46c4 mov ip, r8 80004ee: fbb1 f9fe udiv r9, r1, lr 80004f2: fb09 f804 mul.w r8, r9, r4 80004f6: e7c4 b.n 8000482 <__udivmoddi4+0x282> 080004f8 <__aeabi_idiv0>: 80004f8: 4770 bx lr 80004fa: bf00 nop 080004fc : break; } } void LED_Toggle(uint8_t led) { 80004fc: b580 push {r7, lr} 80004fe: b082 sub sp, #8 8000500: af00 add r7, sp, #0 8000502: 4603 mov r3, r0 8000504: 71fb strb r3, [r7, #7] switch(led) 8000506: 79fb ldrb r3, [r7, #7] 8000508: 2b02 cmp r3, #2 800050a: d012 beq.n 8000532 800050c: 2b02 cmp r3, #2 800050e: dc16 bgt.n 800053e 8000510: 2b00 cmp r3, #0 8000512: d002 beq.n 800051a 8000514: 2b01 cmp r3, #1 8000516: d006 beq.n 8000526 break; case 2: HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_9); break; } } 8000518: e011 b.n 800053e HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_5); 800051a: 2120 movs r1, #32 800051c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000520: f001 fbd8 bl 8001cd4 break; 8000524: e00b b.n 800053e HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_14); 8000526: f44f 4180 mov.w r1, #16384 @ 0x4000 800052a: 4807 ldr r0, [pc, #28] @ (8000548 ) 800052c: f001 fbd2 bl 8001cd4 break; 8000530: e005 b.n 800053e HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_9); 8000532: f44f 7100 mov.w r1, #512 @ 0x200 8000536: 4805 ldr r0, [pc, #20] @ (800054c ) 8000538: f001 fbcc bl 8001cd4 break; 800053c: bf00 nop } 800053e: bf00 nop 8000540: 3708 adds r7, #8 8000542: 46bd mov sp, r7 8000544: bd80 pop {r7, pc} 8000546: bf00 nop 8000548: 48000400 .word 0x48000400 800054c: 48000800 .word 0x48000800 08000550 : */ #include "led_task.h" void CreateLedTask() { 8000550: b580 push {r7, lr} 8000552: b084 sub sp, #16 8000554: af02 add r7, sp, #8 LED_Config* cfg = pvPortMalloc(sizeof(LED_Config)); 8000556: 2008 movs r0, #8 8000558: f007 f9a0 bl 800789c 800055c: 6078 str r0, [r7, #4] if (cfg != NULL) 800055e: 687b ldr r3, [r7, #4] 8000560: 2b00 cmp r3, #0 8000562: d005 beq.n 8000570 { cfg->led = 0; 8000564: 687b ldr r3, [r7, #4] 8000566: 2200 movs r2, #0 8000568: 701a strb r2, [r3, #0] cfg->delay = 200; 800056a: 687b ldr r3, [r7, #4] 800056c: 22c8 movs r2, #200 @ 0xc8 800056e: 605a str r2, [r3, #4] } xTaskCreate( 8000570: 2300 movs r3, #0 8000572: 9301 str r3, [sp, #4] 8000574: 2301 movs r3, #1 8000576: 9300 str r3, [sp, #0] 8000578: 687b ldr r3, [r7, #4] 800057a: 2280 movs r2, #128 @ 0x80 800057c: 4903 ldr r1, [pc, #12] @ (800058c ) 800057e: 4804 ldr r0, [pc, #16] @ (8000590 ) 8000580: f005 fc8e bl 8005ea0 128, (void*) cfg, 1, NULL ); } 8000584: bf00 nop 8000586: 3708 adds r7, #8 8000588: 46bd mov sp, r7 800058a: bd80 pop {r7, pc} 800058c: 08007e70 .word 0x08007e70 8000590: 08000595 .word 0x08000595 08000594 : void LedToggleTask(void* pArgs) { 8000594: b580 push {r7, lr} 8000596: b086 sub sp, #24 8000598: af02 add r7, sp, #8 800059a: 6078 str r0, [r7, #4] LED_Config* cfg = (LED_Config*) pArgs; 800059c: 687b ldr r3, [r7, #4] 800059e: 60bb str r3, [r7, #8] uint8_t counter = 5; 80005a0: 2305 movs r3, #5 80005a2: 73fb strb r3, [r7, #15] for(;;) { if(cfg->led > 2) 80005a4: 68bb ldr r3, [r7, #8] 80005a6: 781b ldrb r3, [r3, #0] 80005a8: 2b02 cmp r3, #2 80005aa: d910 bls.n 80005ce { cfg->led = 0; 80005ac: 68bb ldr r3, [r7, #8] 80005ae: 2200 movs r2, #0 80005b0: 701a strb r2, [r3, #0] } while (counter > 0) 80005b2: e00c b.n 80005ce { LED_Toggle(cfg->led); 80005b4: 68bb ldr r3, [r7, #8] 80005b6: 781b ldrb r3, [r3, #0] 80005b8: 4618 mov r0, r3 80005ba: f7ff ff9f bl 80004fc vTaskDelay(cfg->delay); 80005be: 68bb ldr r3, [r7, #8] 80005c0: 685b ldr r3, [r3, #4] 80005c2: 4618 mov r0, r3 80005c4: f005 fe3e bl 8006244 counter--; 80005c8: 7bfb ldrb r3, [r7, #15] 80005ca: 3b01 subs r3, #1 80005cc: 73fb strb r3, [r7, #15] while (counter > 0) 80005ce: 7bfb ldrb r3, [r7, #15] 80005d0: 2b00 cmp r3, #0 80005d2: d1ef bne.n 80005b4 } cfg->led++; 80005d4: 68bb ldr r3, [r7, #8] 80005d6: 781b ldrb r3, [r3, #0] 80005d8: 3301 adds r3, #1 80005da: b2da uxtb r2, r3 80005dc: 68bb ldr r3, [r7, #8] 80005de: 701a strb r2, [r3, #0] xTaskCreate( 80005e0: 2300 movs r3, #0 80005e2: 9301 str r3, [sp, #4] 80005e4: 2301 movs r3, #1 80005e6: 9300 str r3, [sp, #0] 80005e8: 68bb ldr r3, [r7, #8] 80005ea: 2280 movs r2, #128 @ 0x80 80005ec: 4903 ldr r1, [pc, #12] @ (80005fc ) 80005ee: 4804 ldr r0, [pc, #16] @ (8000600 ) 80005f0: f005 fc56 bl 8005ea0 (void*) cfg, 1, NULL ); vTaskDelete(NULL); 80005f4: 2000 movs r0, #0 80005f6: f005 fdb1 bl 800615c if(cfg->led > 2) 80005fa: e7d3 b.n 80005a4 80005fc: 08007e80 .word 0x08007e80 8000600: 08000595 .word 0x08000595 08000604
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000604: b580 push {r7, lr} 8000606: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000608: f000 ff57 bl 80014ba /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800060c: f000 f818 bl 8000640 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000610: f000 f9e0 bl 80009d4 MX_DFSDM1_Init(); 8000614: f000 f876 bl 8000704 MX_I2C2_Init(); 8000618: f000 f8ac bl 8000774 MX_QUADSPI_Init(); 800061c: f000 f8e8 bl 80007f0 MX_SPI3_Init(); 8000620: f000 f90c bl 800083c MX_USART1_UART_Init(); 8000624: f000 f948 bl 80008b8 MX_USART3_UART_Init(); 8000628: f000 f976 bl 8000918 MX_USB_OTG_FS_PCD_Init(); 800062c: f000 f9a4 bl 8000978 /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 8000630: f004 fdaa bl 8005188 /* Create the thread(s) */ /* creation of defaultTask */ //defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); /* USER CODE BEGIN RTOS_THREADS */ CreateLedTask(); 8000634: f7ff ff8c bl 8000550 /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 8000638: f004 fdca bl 80051d0 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 800063c: bf00 nop 800063e: e7fd b.n 800063c 08000640 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000640: b580 push {r7, lr} 8000642: b096 sub sp, #88 @ 0x58 8000644: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000646: f107 0314 add.w r3, r7, #20 800064a: 2244 movs r2, #68 @ 0x44 800064c: 2100 movs r1, #0 800064e: 4618 mov r0, r3 8000650: f007 fb12 bl 8007c78 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000654: 463b mov r3, r7 8000656: 2200 movs r2, #0 8000658: 601a str r2, [r3, #0] 800065a: 605a str r2, [r3, #4] 800065c: 609a str r2, [r3, #8] 800065e: 60da str r2, [r3, #12] 8000660: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) 8000662: f44f 7000 mov.w r0, #512 @ 0x200 8000666: f001 fdf5 bl 8002254 800066a: 4603 mov r3, r0 800066c: 2b00 cmp r3, #0 800066e: d001 beq.n 8000674 { Error_Handler(); 8000670: f000 fb74 bl 8000d5c } /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); 8000674: f001 fdd0 bl 8002218 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); 8000678: 4b21 ldr r3, [pc, #132] @ (8000700 ) 800067a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800067e: 4a20 ldr r2, [pc, #128] @ (8000700 ) 8000680: f023 0318 bic.w r3, r3, #24 8000684: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; 8000688: 2314 movs r3, #20 800068a: 617b str r3, [r7, #20] RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800068c: 2301 movs r3, #1 800068e: 61fb str r3, [r7, #28] RCC_OscInitStruct.MSIState = RCC_MSI_ON; 8000690: 2301 movs r3, #1 8000692: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.MSICalibrationValue = 0; 8000694: 2300 movs r3, #0 8000696: 633b str r3, [r7, #48] @ 0x30 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; 8000698: 2360 movs r3, #96 @ 0x60 800069a: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800069c: 2302 movs r3, #2 800069e: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; 80006a0: 2301 movs r3, #1 80006a2: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLM = 1; 80006a4: 2301 movs r3, #1 80006a6: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLN = 40; 80006a8: 2328 movs r3, #40 @ 0x28 80006aa: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; 80006ac: 2307 movs r3, #7 80006ae: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 80006b0: 2302 movs r3, #2 80006b2: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 80006b4: 2302 movs r3, #2 80006b6: 657b str r3, [r7, #84] @ 0x54 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80006b8: f107 0314 add.w r3, r7, #20 80006bc: 4618 mov r0, r3 80006be: f001 feeb bl 8002498 80006c2: 4603 mov r3, r0 80006c4: 2b00 cmp r3, #0 80006c6: d001 beq.n 80006cc { Error_Handler(); 80006c8: f000 fb48 bl 8000d5c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80006cc: 230f movs r3, #15 80006ce: 603b str r3, [r7, #0] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80006d0: 2303 movs r3, #3 80006d2: 607b str r3, [r7, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80006d4: 2300 movs r3, #0 80006d6: 60bb str r3, [r7, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80006d8: 2300 movs r3, #0 80006da: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80006dc: 2300 movs r3, #0 80006de: 613b str r3, [r7, #16] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 80006e0: 463b mov r3, r7 80006e2: 2104 movs r1, #4 80006e4: 4618 mov r0, r3 80006e6: f002 fab3 bl 8002c50 80006ea: 4603 mov r3, r0 80006ec: 2b00 cmp r3, #0 80006ee: d001 beq.n 80006f4 { Error_Handler(); 80006f0: f000 fb34 bl 8000d5c } /** Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); 80006f4: f002 ffec bl 80036d0 } 80006f8: bf00 nop 80006fa: 3758 adds r7, #88 @ 0x58 80006fc: 46bd mov sp, r7 80006fe: bd80 pop {r7, pc} 8000700: 40021000 .word 0x40021000 08000704 : * @brief DFSDM1 Initialization Function * @param None * @retval None */ static void MX_DFSDM1_Init(void) { 8000704: b580 push {r7, lr} 8000706: af00 add r7, sp, #0 /* USER CODE END DFSDM1_Init 0 */ /* USER CODE BEGIN DFSDM1_Init 1 */ /* USER CODE END DFSDM1_Init 1 */ hdfsdm1_channel1.Instance = DFSDM1_Channel1; 8000708: 4b18 ldr r3, [pc, #96] @ (800076c ) 800070a: 4a19 ldr r2, [pc, #100] @ (8000770 ) 800070c: 601a str r2, [r3, #0] hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE; 800070e: 4b17 ldr r3, [pc, #92] @ (800076c ) 8000710: 2201 movs r2, #1 8000712: 711a strb r2, [r3, #4] hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM; 8000714: 4b15 ldr r3, [pc, #84] @ (800076c ) 8000716: 2200 movs r2, #0 8000718: 609a str r2, [r3, #8] hdfsdm1_channel1.Init.OutputClock.Divider = 2; 800071a: 4b14 ldr r3, [pc, #80] @ (800076c ) 800071c: 2202 movs r2, #2 800071e: 60da str r2, [r3, #12] hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS; 8000720: 4b12 ldr r3, [pc, #72] @ (800076c ) 8000722: 2200 movs r2, #0 8000724: 611a str r2, [r3, #16] hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE; 8000726: 4b11 ldr r3, [pc, #68] @ (800076c ) 8000728: 2200 movs r2, #0 800072a: 615a str r2, [r3, #20] hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS; 800072c: 4b0f ldr r3, [pc, #60] @ (800076c ) 800072e: f44f 7280 mov.w r2, #256 @ 0x100 8000732: 619a str r2, [r3, #24] hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING; 8000734: 4b0d ldr r3, [pc, #52] @ (800076c ) 8000736: 2200 movs r2, #0 8000738: 61da str r2, [r3, #28] hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL; 800073a: 4b0c ldr r3, [pc, #48] @ (800076c ) 800073c: 2204 movs r2, #4 800073e: 621a str r2, [r3, #32] hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER; 8000740: 4b0a ldr r3, [pc, #40] @ (800076c ) 8000742: 2200 movs r2, #0 8000744: 625a str r2, [r3, #36] @ 0x24 hdfsdm1_channel1.Init.Awd.Oversampling = 1; 8000746: 4b09 ldr r3, [pc, #36] @ (800076c ) 8000748: 2201 movs r2, #1 800074a: 629a str r2, [r3, #40] @ 0x28 hdfsdm1_channel1.Init.Offset = 0; 800074c: 4b07 ldr r3, [pc, #28] @ (800076c ) 800074e: 2200 movs r2, #0 8000750: 62da str r2, [r3, #44] @ 0x2c hdfsdm1_channel1.Init.RightBitShift = 0x00; 8000752: 4b06 ldr r3, [pc, #24] @ (800076c ) 8000754: 2200 movs r2, #0 8000756: 631a str r2, [r3, #48] @ 0x30 if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK) 8000758: 4804 ldr r0, [pc, #16] @ (800076c ) 800075a: f000 ffed bl 8001738 800075e: 4603 mov r3, r0 8000760: 2b00 cmp r3, #0 8000762: d001 beq.n 8000768 { Error_Handler(); 8000764: f000 fafa bl 8000d5c } /* USER CODE BEGIN DFSDM1_Init 2 */ /* USER CODE END DFSDM1_Init 2 */ } 8000768: bf00 nop 800076a: bd80 pop {r7, pc} 800076c: 2000007c .word 0x2000007c 8000770: 40016020 .word 0x40016020 08000774 : * @brief I2C2 Initialization Function * @param None * @retval None */ static void MX_I2C2_Init(void) { 8000774: b580 push {r7, lr} 8000776: af00 add r7, sp, #0 /* USER CODE END I2C2_Init 0 */ /* USER CODE BEGIN I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */ hi2c2.Instance = I2C2; 8000778: 4b1b ldr r3, [pc, #108] @ (80007e8 ) 800077a: 4a1c ldr r2, [pc, #112] @ (80007ec ) 800077c: 601a str r2, [r3, #0] hi2c2.Init.Timing = 0x00000E14; 800077e: 4b1a ldr r3, [pc, #104] @ (80007e8 ) 8000780: f640 6214 movw r2, #3604 @ 0xe14 8000784: 605a str r2, [r3, #4] hi2c2.Init.OwnAddress1 = 0; 8000786: 4b18 ldr r3, [pc, #96] @ (80007e8 ) 8000788: 2200 movs r2, #0 800078a: 609a str r2, [r3, #8] hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 800078c: 4b16 ldr r3, [pc, #88] @ (80007e8 ) 800078e: 2201 movs r2, #1 8000790: 60da str r2, [r3, #12] hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000792: 4b15 ldr r3, [pc, #84] @ (80007e8 ) 8000794: 2200 movs r2, #0 8000796: 611a str r2, [r3, #16] hi2c2.Init.OwnAddress2 = 0; 8000798: 4b13 ldr r3, [pc, #76] @ (80007e8 ) 800079a: 2200 movs r2, #0 800079c: 615a str r2, [r3, #20] hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 800079e: 4b12 ldr r3, [pc, #72] @ (80007e8 ) 80007a0: 2200 movs r2, #0 80007a2: 619a str r2, [r3, #24] hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80007a4: 4b10 ldr r3, [pc, #64] @ (80007e8 ) 80007a6: 2200 movs r2, #0 80007a8: 61da str r2, [r3, #28] hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 80007aa: 4b0f ldr r3, [pc, #60] @ (80007e8 ) 80007ac: 2200 movs r2, #0 80007ae: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c2) != HAL_OK) 80007b0: 480d ldr r0, [pc, #52] @ (80007e8 ) 80007b2: f001 facc bl 8001d4e 80007b6: 4603 mov r3, r0 80007b8: 2b00 cmp r3, #0 80007ba: d001 beq.n 80007c0 { Error_Handler(); 80007bc: f000 face bl 8000d5c } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 80007c0: 2100 movs r1, #0 80007c2: 4809 ldr r0, [pc, #36] @ (80007e8 ) 80007c4: f001 fb5e bl 8001e84 80007c8: 4603 mov r3, r0 80007ca: 2b00 cmp r3, #0 80007cc: d001 beq.n 80007d2 { Error_Handler(); 80007ce: f000 fac5 bl 8000d5c } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) 80007d2: 2100 movs r1, #0 80007d4: 4804 ldr r0, [pc, #16] @ (80007e8 ) 80007d6: f001 fba0 bl 8001f1a 80007da: 4603 mov r3, r0 80007dc: 2b00 cmp r3, #0 80007de: d001 beq.n 80007e4 { Error_Handler(); 80007e0: f000 fabc bl 8000d5c } /* USER CODE BEGIN I2C2_Init 2 */ /* USER CODE END I2C2_Init 2 */ } 80007e4: bf00 nop 80007e6: bd80 pop {r7, pc} 80007e8: 200000b4 .word 0x200000b4 80007ec: 40005800 .word 0x40005800 080007f0 : * @brief QUADSPI Initialization Function * @param None * @retval None */ static void MX_QUADSPI_Init(void) { 80007f0: b580 push {r7, lr} 80007f2: af00 add r7, sp, #0 /* USER CODE BEGIN QUADSPI_Init 1 */ /* USER CODE END QUADSPI_Init 1 */ /* QUADSPI parameter configuration*/ hqspi.Instance = QUADSPI; 80007f4: 4b0f ldr r3, [pc, #60] @ (8000834 ) 80007f6: 4a10 ldr r2, [pc, #64] @ (8000838 ) 80007f8: 601a str r2, [r3, #0] hqspi.Init.ClockPrescaler = 2; 80007fa: 4b0e ldr r3, [pc, #56] @ (8000834 ) 80007fc: 2202 movs r2, #2 80007fe: 605a str r2, [r3, #4] hqspi.Init.FifoThreshold = 4; 8000800: 4b0c ldr r3, [pc, #48] @ (8000834 ) 8000802: 2204 movs r2, #4 8000804: 609a str r2, [r3, #8] hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; 8000806: 4b0b ldr r3, [pc, #44] @ (8000834 ) 8000808: 2210 movs r2, #16 800080a: 60da str r2, [r3, #12] hqspi.Init.FlashSize = 23; 800080c: 4b09 ldr r3, [pc, #36] @ (8000834 ) 800080e: 2217 movs r2, #23 8000810: 611a str r2, [r3, #16] hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE; 8000812: 4b08 ldr r3, [pc, #32] @ (8000834 ) 8000814: 2200 movs r2, #0 8000816: 615a str r2, [r3, #20] hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; 8000818: 4b06 ldr r3, [pc, #24] @ (8000834 ) 800081a: 2200 movs r2, #0 800081c: 619a str r2, [r3, #24] if (HAL_QSPI_Init(&hqspi) != HAL_OK) 800081e: 4805 ldr r0, [pc, #20] @ (8000834 ) 8000820: f001 fd7e bl 8002320 8000824: 4603 mov r3, r0 8000826: 2b00 cmp r3, #0 8000828: d001 beq.n 800082e { Error_Handler(); 800082a: f000 fa97 bl 8000d5c } /* USER CODE BEGIN QUADSPI_Init 2 */ /* USER CODE END QUADSPI_Init 2 */ } 800082e: bf00 nop 8000830: bd80 pop {r7, pc} 8000832: bf00 nop 8000834: 20000108 .word 0x20000108 8000838: a0001000 .word 0xa0001000 0800083c : * @brief SPI3 Initialization Function * @param None * @retval None */ static void MX_SPI3_Init(void) { 800083c: b580 push {r7, lr} 800083e: af00 add r7, sp, #0 /* USER CODE BEGIN SPI3_Init 1 */ /* USER CODE END SPI3_Init 1 */ /* SPI3 parameter configuration*/ hspi3.Instance = SPI3; 8000840: 4b1b ldr r3, [pc, #108] @ (80008b0 ) 8000842: 4a1c ldr r2, [pc, #112] @ (80008b4 ) 8000844: 601a str r2, [r3, #0] hspi3.Init.Mode = SPI_MODE_MASTER; 8000846: 4b1a ldr r3, [pc, #104] @ (80008b0 ) 8000848: f44f 7282 mov.w r2, #260 @ 0x104 800084c: 605a str r2, [r3, #4] hspi3.Init.Direction = SPI_DIRECTION_2LINES; 800084e: 4b18 ldr r3, [pc, #96] @ (80008b0 ) 8000850: 2200 movs r2, #0 8000852: 609a str r2, [r3, #8] hspi3.Init.DataSize = SPI_DATASIZE_4BIT; 8000854: 4b16 ldr r3, [pc, #88] @ (80008b0 ) 8000856: f44f 7240 mov.w r2, #768 @ 0x300 800085a: 60da str r2, [r3, #12] hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; 800085c: 4b14 ldr r3, [pc, #80] @ (80008b0 ) 800085e: 2200 movs r2, #0 8000860: 611a str r2, [r3, #16] hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; 8000862: 4b13 ldr r3, [pc, #76] @ (80008b0 ) 8000864: 2200 movs r2, #0 8000866: 615a str r2, [r3, #20] hspi3.Init.NSS = SPI_NSS_SOFT; 8000868: 4b11 ldr r3, [pc, #68] @ (80008b0 ) 800086a: f44f 7200 mov.w r2, #512 @ 0x200 800086e: 619a str r2, [r3, #24] hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8000870: 4b0f ldr r3, [pc, #60] @ (80008b0 ) 8000872: 2200 movs r2, #0 8000874: 61da str r2, [r3, #28] hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; 8000876: 4b0e ldr r3, [pc, #56] @ (80008b0 ) 8000878: 2200 movs r2, #0 800087a: 621a str r2, [r3, #32] hspi3.Init.TIMode = SPI_TIMODE_DISABLE; 800087c: 4b0c ldr r3, [pc, #48] @ (80008b0 ) 800087e: 2200 movs r2, #0 8000880: 625a str r2, [r3, #36] @ 0x24 hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8000882: 4b0b ldr r3, [pc, #44] @ (80008b0 ) 8000884: 2200 movs r2, #0 8000886: 629a str r2, [r3, #40] @ 0x28 hspi3.Init.CRCPolynomial = 7; 8000888: 4b09 ldr r3, [pc, #36] @ (80008b0 ) 800088a: 2207 movs r2, #7 800088c: 62da str r2, [r3, #44] @ 0x2c hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 800088e: 4b08 ldr r3, [pc, #32] @ (80008b0 ) 8000890: 2200 movs r2, #0 8000892: 631a str r2, [r3, #48] @ 0x30 hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 8000894: 4b06 ldr r3, [pc, #24] @ (80008b0 ) 8000896: 2208 movs r2, #8 8000898: 635a str r2, [r3, #52] @ 0x34 if (HAL_SPI_Init(&hspi3) != HAL_OK) 800089a: 4805 ldr r0, [pc, #20] @ (80008b0 ) 800089c: f003 f8fa bl 8003a94 80008a0: 4603 mov r3, r0 80008a2: 2b00 cmp r3, #0 80008a4: d001 beq.n 80008aa { Error_Handler(); 80008a6: f000 fa59 bl 8000d5c } /* USER CODE BEGIN SPI3_Init 2 */ /* USER CODE END SPI3_Init 2 */ } 80008aa: bf00 nop 80008ac: bd80 pop {r7, pc} 80008ae: bf00 nop 80008b0: 2000014c .word 0x2000014c 80008b4: 40003c00 .word 0x40003c00 080008b8 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 80008b8: b580 push {r7, lr} 80008ba: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80008bc: 4b14 ldr r3, [pc, #80] @ (8000910 ) 80008be: 4a15 ldr r2, [pc, #84] @ (8000914 ) 80008c0: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80008c2: 4b13 ldr r3, [pc, #76] @ (8000910 ) 80008c4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80008c8: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80008ca: 4b11 ldr r3, [pc, #68] @ (8000910 ) 80008cc: 2200 movs r2, #0 80008ce: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80008d0: 4b0f ldr r3, [pc, #60] @ (8000910 ) 80008d2: 2200 movs r2, #0 80008d4: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80008d6: 4b0e ldr r3, [pc, #56] @ (8000910 ) 80008d8: 2200 movs r2, #0 80008da: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80008dc: 4b0c ldr r3, [pc, #48] @ (8000910 ) 80008de: 220c movs r2, #12 80008e0: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80008e2: 4b0b ldr r3, [pc, #44] @ (8000910 ) 80008e4: 2200 movs r2, #0 80008e6: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80008e8: 4b09 ldr r3, [pc, #36] @ (8000910 ) 80008ea: 2200 movs r2, #0 80008ec: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80008ee: 4b08 ldr r3, [pc, #32] @ (8000910 ) 80008f0: 2200 movs r2, #0 80008f2: 621a str r2, [r3, #32] huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80008f4: 4b06 ldr r3, [pc, #24] @ (8000910 ) 80008f6: 2200 movs r2, #0 80008f8: 625a str r2, [r3, #36] @ 0x24 if (HAL_UART_Init(&huart1) != HAL_OK) 80008fa: 4805 ldr r0, [pc, #20] @ (8000910 ) 80008fc: f003 fc32 bl 8004164 8000900: 4603 mov r3, r0 8000902: 2b00 cmp r3, #0 8000904: d001 beq.n 800090a { Error_Handler(); 8000906: f000 fa29 bl 8000d5c } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800090a: bf00 nop 800090c: bd80 pop {r7, pc} 800090e: bf00 nop 8000910: 200001b0 .word 0x200001b0 8000914: 40013800 .word 0x40013800 08000918 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 8000918: b580 push {r7, lr} 800091a: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800091c: 4b14 ldr r3, [pc, #80] @ (8000970 ) 800091e: 4a15 ldr r2, [pc, #84] @ (8000974 ) 8000920: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 8000922: 4b13 ldr r3, [pc, #76] @ (8000970 ) 8000924: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8000928: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800092a: 4b11 ldr r3, [pc, #68] @ (8000970 ) 800092c: 2200 movs r2, #0 800092e: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 8000930: 4b0f ldr r3, [pc, #60] @ (8000970 ) 8000932: 2200 movs r2, #0 8000934: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 8000936: 4b0e ldr r3, [pc, #56] @ (8000970 ) 8000938: 2200 movs r2, #0 800093a: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800093c: 4b0c ldr r3, [pc, #48] @ (8000970 ) 800093e: 220c movs r2, #12 8000940: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000942: 4b0b ldr r3, [pc, #44] @ (8000970 ) 8000944: 2200 movs r2, #0 8000946: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 8000948: 4b09 ldr r3, [pc, #36] @ (8000970 ) 800094a: 2200 movs r2, #0 800094c: 61da str r2, [r3, #28] huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800094e: 4b08 ldr r3, [pc, #32] @ (8000970 ) 8000950: 2200 movs r2, #0 8000952: 621a str r2, [r3, #32] huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000954: 4b06 ldr r3, [pc, #24] @ (8000970 ) 8000956: 2200 movs r2, #0 8000958: 625a str r2, [r3, #36] @ 0x24 if (HAL_UART_Init(&huart3) != HAL_OK) 800095a: 4805 ldr r0, [pc, #20] @ (8000970 ) 800095c: f003 fc02 bl 8004164 8000960: 4603 mov r3, r0 8000962: 2b00 cmp r3, #0 8000964: d001 beq.n 800096a { Error_Handler(); 8000966: f000 f9f9 bl 8000d5c } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800096a: bf00 nop 800096c: bd80 pop {r7, pc} 800096e: bf00 nop 8000970: 20000238 .word 0x20000238 8000974: 40004800 .word 0x40004800 08000978 : * @brief USB_OTG_FS Initialization Function * @param None * @retval None */ static void MX_USB_OTG_FS_PCD_Init(void) { 8000978: b580 push {r7, lr} 800097a: af00 add r7, sp, #0 /* USER CODE END USB_OTG_FS_Init 0 */ /* USER CODE BEGIN USB_OTG_FS_Init 1 */ /* USER CODE END USB_OTG_FS_Init 1 */ hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800097c: 4b14 ldr r3, [pc, #80] @ (80009d0 ) 800097e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 8000982: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 8000984: 4b12 ldr r3, [pc, #72] @ (80009d0 ) 8000986: 2206 movs r2, #6 8000988: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800098a: 4b11 ldr r3, [pc, #68] @ (80009d0 ) 800098c: 2202 movs r2, #2 800098e: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 8000990: 4b0f ldr r3, [pc, #60] @ (80009d0 ) 8000992: 2202 movs r2, #2 8000994: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 8000996: 4b0e ldr r3, [pc, #56] @ (80009d0 ) 8000998: 2200 movs r2, #0 800099a: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800099c: 4b0c ldr r3, [pc, #48] @ (80009d0 ) 800099e: 2200 movs r2, #0 80009a0: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 80009a2: 4b0b ldr r3, [pc, #44] @ (80009d0 ) 80009a4: 2200 movs r2, #0 80009a6: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE; 80009a8: 4b09 ldr r3, [pc, #36] @ (80009d0 ) 80009aa: 2200 movs r2, #0 80009ac: 735a strb r2, [r3, #13] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 80009ae: 4b08 ldr r3, [pc, #32] @ (80009d0 ) 80009b0: 2200 movs r2, #0 80009b2: 73da strb r2, [r3, #15] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 80009b4: 4b06 ldr r3, [pc, #24] @ (80009d0 ) 80009b6: 2200 movs r2, #0 80009b8: 739a strb r2, [r3, #14] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 80009ba: 4805 ldr r0, [pc, #20] @ (80009d0 ) 80009bc: f001 faf9 bl 8001fb2 80009c0: 4603 mov r3, r0 80009c2: 2b00 cmp r3, #0 80009c4: d001 beq.n 80009ca { Error_Handler(); 80009c6: f000 f9c9 bl 8000d5c } /* USER CODE BEGIN USB_OTG_FS_Init 2 */ /* USER CODE END USB_OTG_FS_Init 2 */ } 80009ca: bf00 nop 80009cc: bd80 pop {r7, pc} 80009ce: bf00 nop 80009d0: 200002c0 .word 0x200002c0 080009d4 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80009d4: b580 push {r7, lr} 80009d6: b08a sub sp, #40 @ 0x28 80009d8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80009da: f107 0314 add.w r3, r7, #20 80009de: 2200 movs r2, #0 80009e0: 601a str r2, [r3, #0] 80009e2: 605a str r2, [r3, #4] 80009e4: 609a str r2, [r3, #8] 80009e6: 60da str r2, [r3, #12] 80009e8: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); 80009ea: 4bbd ldr r3, [pc, #756] @ (8000ce0 ) 80009ec: 6cdb ldr r3, [r3, #76] @ 0x4c 80009ee: 4abc ldr r2, [pc, #752] @ (8000ce0 ) 80009f0: f043 0310 orr.w r3, r3, #16 80009f4: 64d3 str r3, [r2, #76] @ 0x4c 80009f6: 4bba ldr r3, [pc, #744] @ (8000ce0 ) 80009f8: 6cdb ldr r3, [r3, #76] @ 0x4c 80009fa: f003 0310 and.w r3, r3, #16 80009fe: 613b str r3, [r7, #16] 8000a00: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000a02: 4bb7 ldr r3, [pc, #732] @ (8000ce0 ) 8000a04: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a06: 4ab6 ldr r2, [pc, #728] @ (8000ce0 ) 8000a08: f043 0304 orr.w r3, r3, #4 8000a0c: 64d3 str r3, [r2, #76] @ 0x4c 8000a0e: 4bb4 ldr r3, [pc, #720] @ (8000ce0 ) 8000a10: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a12: f003 0304 and.w r3, r3, #4 8000a16: 60fb str r3, [r7, #12] 8000a18: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000a1a: 4bb1 ldr r3, [pc, #708] @ (8000ce0 ) 8000a1c: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a1e: 4ab0 ldr r2, [pc, #704] @ (8000ce0 ) 8000a20: f043 0301 orr.w r3, r3, #1 8000a24: 64d3 str r3, [r2, #76] @ 0x4c 8000a26: 4bae ldr r3, [pc, #696] @ (8000ce0 ) 8000a28: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a2a: f003 0301 and.w r3, r3, #1 8000a2e: 60bb str r3, [r7, #8] 8000a30: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000a32: 4bab ldr r3, [pc, #684] @ (8000ce0 ) 8000a34: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a36: 4aaa ldr r2, [pc, #680] @ (8000ce0 ) 8000a38: f043 0302 orr.w r3, r3, #2 8000a3c: 64d3 str r3, [r2, #76] @ 0x4c 8000a3e: 4ba8 ldr r3, [pc, #672] @ (8000ce0 ) 8000a40: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a42: f003 0302 and.w r3, r3, #2 8000a46: 607b str r3, [r7, #4] 8000a48: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000a4a: 4ba5 ldr r3, [pc, #660] @ (8000ce0 ) 8000a4c: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a4e: 4aa4 ldr r2, [pc, #656] @ (8000ce0 ) 8000a50: f043 0308 orr.w r3, r3, #8 8000a54: 64d3 str r3, [r2, #76] @ 0x4c 8000a56: 4ba2 ldr r3, [pc, #648] @ (8000ce0 ) 8000a58: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a5a: f003 0308 and.w r3, r3, #8 8000a5e: 603b str r3, [r7, #0] 8000a60: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET); 8000a62: 2200 movs r2, #0 8000a64: f44f 718a mov.w r1, #276 @ 0x114 8000a68: 489e ldr r0, [pc, #632] @ (8000ce4 ) 8000a6a: f001 f91b bl 8001ca4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|GPIO_PIN_5|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET); 8000a6e: 2200 movs r2, #0 8000a70: f248 1124 movw r1, #33060 @ 0x8124 8000a74: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000a78: f001 f914 bl 8001ca4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin 8000a7c: 2200 movs r2, #0 8000a7e: f24f 0114 movw r1, #61460 @ 0xf014 8000a82: 4899 ldr r0, [pc, #612] @ (8000ce8 ) 8000a84: f001 f90e bl 8001ca4 |SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET); 8000a88: 2200 movs r2, #0 8000a8a: f241 0181 movw r1, #4225 @ 0x1081 8000a8e: 4897 ldr r0, [pc, #604] @ (8000cec ) 8000a90: f001 f908 bl 8001ca4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET); 8000a94: 2201 movs r2, #1 8000a96: f44f 5100 mov.w r1, #8192 @ 0x2000 8000a9a: 4894 ldr r0, [pc, #592] @ (8000cec ) 8000a9c: f001 f902 bl 8001ca4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET); 8000aa0: 2200 movs r2, #0 8000aa2: f44f 7110 mov.w r1, #576 @ 0x240 8000aa6: 4892 ldr r0, [pc, #584] @ (8000cf0 ) 8000aa8: f001 f8fc bl 8001ca4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET); 8000aac: 2201 movs r2, #1 8000aae: 2120 movs r1, #32 8000ab0: 488d ldr r0, [pc, #564] @ (8000ce8 ) 8000ab2: f001 f8f7 bl 8001ca4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET); 8000ab6: 2201 movs r2, #1 8000ab8: 2101 movs r1, #1 8000aba: 488a ldr r0, [pc, #552] @ (8000ce4 ) 8000abc: f001 f8f2 bl 8001ca4 /*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */ GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin; 8000ac0: f240 1315 movw r3, #277 @ 0x115 8000ac4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000ac6: 2301 movs r3, #1 8000ac8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000aca: 2300 movs r3, #0 8000acc: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000ace: 2300 movs r3, #0 8000ad0: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000ad2: f107 0314 add.w r3, r7, #20 8000ad6: 4619 mov r1, r3 8000ad8: 4882 ldr r0, [pc, #520] @ (8000ce4 ) 8000ada: f000 ff39 bl 8001950 /*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */ GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin; 8000ade: 236a movs r3, #106 @ 0x6a 8000ae0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000ae2: f44f 1388 mov.w r3, #1114112 @ 0x110000 8000ae6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000ae8: 2300 movs r3, #0 8000aea: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000aec: f107 0314 add.w r3, r7, #20 8000af0: 4619 mov r1, r3 8000af2: 487c ldr r0, [pc, #496] @ (8000ce4 ) 8000af4: f000 ff2c bl 8001950 /*Configure GPIO pin : BUTTON_EXTI13_Pin */ GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin; 8000af8: f44f 5300 mov.w r3, #8192 @ 0x2000 8000afc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 8000afe: f44f 1304 mov.w r3, #2162688 @ 0x210000 8000b02: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b04: 2300 movs r3, #0 8000b06: 61fb str r3, [r7, #28] HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct); 8000b08: f107 0314 add.w r3, r7, #20 8000b0c: 4619 mov r1, r3 8000b0e: 4878 ldr r0, [pc, #480] @ (8000cf0 ) 8000b10: f000 ff1e bl 8001950 /*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin ARD_A1_Pin ARD_A0_Pin */ GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin 8000b14: 233f movs r3, #63 @ 0x3f 8000b16: 617b str r3, [r7, #20] |ARD_A1_Pin|ARD_A0_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; 8000b18: 230b movs r3, #11 8000b1a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b1c: 2300 movs r3, #0 8000b1e: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000b20: f107 0314 add.w r3, r7, #20 8000b24: 4619 mov r1, r3 8000b26: 4872 ldr r0, [pc, #456] @ (8000cf0 ) 8000b28: f000 ff12 bl 8001950 /*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */ GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin; 8000b2c: 2303 movs r3, #3 8000b2e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000b30: 2302 movs r3, #2 8000b32: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b34: 2300 movs r3, #0 8000b36: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000b38: 2303 movs r3, #3 8000b3a: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8000b3c: 2308 movs r3, #8 8000b3e: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000b40: f107 0314 add.w r3, r7, #20 8000b44: 4619 mov r1, r3 8000b46: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000b4a: f000 ff01 bl 8001950 /*Configure GPIO pins : ARD_D10_Pin PA5 SPBTLE_RF_RST_Pin ARD_D9_Pin */ GPIO_InitStruct.Pin = ARD_D10_Pin|GPIO_PIN_5|SPBTLE_RF_RST_Pin|ARD_D9_Pin; 8000b4e: f248 1324 movw r3, #33060 @ 0x8124 8000b52: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000b54: 2301 movs r3, #1 8000b56: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b58: 2300 movs r3, #0 8000b5a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000b5c: 2300 movs r3, #0 8000b5e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000b60: f107 0314 add.w r3, r7, #20 8000b64: 4619 mov r1, r3 8000b66: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000b6a: f000 fef1 bl 8001950 /*Configure GPIO pin : ARD_D4_Pin */ GPIO_InitStruct.Pin = ARD_D4_Pin; 8000b6e: 2308 movs r3, #8 8000b70: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000b72: 2302 movs r3, #2 8000b74: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b76: 2300 movs r3, #0 8000b78: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000b7a: 2300 movs r3, #0 8000b7c: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8000b7e: 2301 movs r3, #1 8000b80: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct); 8000b82: f107 0314 add.w r3, r7, #20 8000b86: 4619 mov r1, r3 8000b88: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000b8c: f000 fee0 bl 8001950 /*Configure GPIO pin : ARD_D7_Pin */ GPIO_InitStruct.Pin = ARD_D7_Pin; 8000b90: 2310 movs r3, #16 8000b92: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; 8000b94: 230b movs r3, #11 8000b96: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b98: 2300 movs r3, #0 8000b9a: 61fb str r3, [r7, #28] HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct); 8000b9c: f107 0314 add.w r3, r7, #20 8000ba0: 4619 mov r1, r3 8000ba2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000ba6: f000 fed3 bl 8001950 /*Configure GPIO pins : ARD_D12_Pin ARD_D11_Pin */ GPIO_InitStruct.Pin = ARD_D12_Pin|ARD_D11_Pin; 8000baa: 23c0 movs r3, #192 @ 0xc0 8000bac: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000bae: 2302 movs r3, #2 8000bb0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bb2: 2300 movs r3, #0 8000bb4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000bb6: 2303 movs r3, #3 8000bb8: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; 8000bba: 2305 movs r3, #5 8000bbc: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000bbe: f107 0314 add.w r3, r7, #20 8000bc2: 4619 mov r1, r3 8000bc4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000bc8: f000 fec2 bl 8001950 /*Configure GPIO pin : ARD_D3_Pin */ GPIO_InitStruct.Pin = ARD_D3_Pin; 8000bcc: 2301 movs r3, #1 8000bce: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000bd0: f44f 1388 mov.w r3, #1114112 @ 0x110000 8000bd4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bd6: 2300 movs r3, #0 8000bd8: 61fb str r3, [r7, #28] HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct); 8000bda: f107 0314 add.w r3, r7, #20 8000bde: 4619 mov r1, r3 8000be0: 4841 ldr r0, [pc, #260] @ (8000ce8 ) 8000be2: f000 feb5 bl 8001950 /*Configure GPIO pin : ARD_D6_Pin */ GPIO_InitStruct.Pin = ARD_D6_Pin; 8000be6: 2302 movs r3, #2 8000be8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; 8000bea: 230b movs r3, #11 8000bec: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bee: 2300 movs r3, #0 8000bf0: 61fb str r3, [r7, #28] HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct); 8000bf2: f107 0314 add.w r3, r7, #20 8000bf6: 4619 mov r1, r3 8000bf8: 483b ldr r0, [pc, #236] @ (8000ce8 ) 8000bfa: f000 fea9 bl 8001950 /*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */ GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin 8000bfe: f24f 0334 movw r3, #61492 @ 0xf034 8000c02: 617b str r3, [r7, #20] |SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c04: 2301 movs r3, #1 8000c06: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c08: 2300 movs r3, #0 8000c0a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c0c: 2300 movs r3, #0 8000c0e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000c10: f107 0314 add.w r3, r7, #20 8000c14: 4619 mov r1, r3 8000c16: 4834 ldr r0, [pc, #208] @ (8000ce8 ) 8000c18: f000 fe9a bl 8001950 /*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin PMOD_IRQ_EXTI12_Pin */ GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin 8000c1c: f64c 4304 movw r3, #52228 @ 0xcc04 8000c20: 617b str r3, [r7, #20] |PMOD_IRQ_EXTI12_Pin; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000c22: f44f 1388 mov.w r3, #1114112 @ 0x110000 8000c26: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c28: 2300 movs r3, #0 8000c2a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000c2c: f107 0314 add.w r3, r7, #20 8000c30: 4619 mov r1, r3 8000c32: 482e ldr r0, [pc, #184] @ (8000cec ) 8000c34: f000 fe8c bl 8001950 /*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */ GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin; 8000c38: f243 0381 movw r3, #12417 @ 0x3081 8000c3c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c3e: 2301 movs r3, #1 8000c40: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c42: 2300 movs r3, #0 8000c44: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c46: 2300 movs r3, #0 8000c48: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000c4a: f107 0314 add.w r3, r7, #20 8000c4e: 4619 mov r1, r3 8000c50: 4826 ldr r0, [pc, #152] @ (8000cec ) 8000c52: f000 fe7d bl 8001950 /*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */ GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin; 8000c56: f44f 7310 mov.w r3, #576 @ 0x240 8000c5a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c5c: 2301 movs r3, #1 8000c5e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c60: 2300 movs r3, #0 8000c62: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c64: 2300 movs r3, #0 8000c66: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000c68: f107 0314 add.w r3, r7, #20 8000c6c: 4619 mov r1, r3 8000c6e: 4820 ldr r0, [pc, #128] @ (8000cf0 ) 8000c70: f000 fe6e bl 8001950 /*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */ GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin; 8000c74: f44f 73c0 mov.w r3, #384 @ 0x180 8000c78: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000c7a: f44f 1388 mov.w r3, #1114112 @ 0x110000 8000c7e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c80: 2300 movs r3, #0 8000c82: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000c84: f107 0314 add.w r3, r7, #20 8000c88: 4619 mov r1, r3 8000c8a: 4819 ldr r0, [pc, #100] @ (8000cf0 ) 8000c8c: f000 fe60 bl 8001950 /*Configure GPIO pin : PMOD_SPI2_SCK_Pin */ GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin; 8000c90: 2302 movs r3, #2 8000c92: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000c94: 2302 movs r3, #2 8000c96: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c98: 2300 movs r3, #0 8000c9a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000c9c: 2303 movs r3, #3 8000c9e: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 8000ca0: 2305 movs r3, #5 8000ca2: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct); 8000ca4: f107 0314 add.w r3, r7, #20 8000ca8: 4619 mov r1, r3 8000caa: 4810 ldr r0, [pc, #64] @ (8000cec ) 8000cac: f000 fe50 bl 8001950 /*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */ GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin; 8000cb0: 2378 movs r3, #120 @ 0x78 8000cb2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000cb4: 2302 movs r3, #2 8000cb6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cb8: 2300 movs r3, #0 8000cba: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000cbc: 2303 movs r3, #3 8000cbe: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8000cc0: 2307 movs r3, #7 8000cc2: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000cc4: f107 0314 add.w r3, r7, #20 8000cc8: 4619 mov r1, r3 8000cca: 4808 ldr r0, [pc, #32] @ (8000cec ) 8000ccc: f000 fe40 bl 8001950 /*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */ GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin; 8000cd0: f44f 7340 mov.w r3, #768 @ 0x300 8000cd4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000cd6: 2312 movs r3, #18 8000cd8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cda: 2300 movs r3, #0 8000cdc: e00a b.n 8000cf4 8000cde: bf00 nop 8000ce0: 40021000 .word 0x40021000 8000ce4: 48001000 .word 0x48001000 8000ce8: 48000400 .word 0x48000400 8000cec: 48000c00 .word 0x48000c00 8000cf0: 48000800 .word 0x48000800 8000cf4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000cf6: 2303 movs r3, #3 8000cf8: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 8000cfa: 2304 movs r3, #4 8000cfc: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000cfe: f107 0314 add.w r3, r7, #20 8000d02: 4619 mov r1, r3 8000d04: 480b ldr r0, [pc, #44] @ (8000d34 ) 8000d06: f000 fe23 bl 8001950 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); 8000d0a: 2200 movs r2, #0 8000d0c: 2105 movs r1, #5 8000d0e: 2017 movs r0, #23 8000d10: f000 fce8 bl 80016e4 HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 8000d14: 2017 movs r0, #23 8000d16: f000 fd01 bl 800171c HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 8000d1a: 2200 movs r2, #0 8000d1c: 2105 movs r1, #5 8000d1e: 2028 movs r0, #40 @ 0x28 8000d20: f000 fce0 bl 80016e4 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8000d24: 2028 movs r0, #40 @ 0x28 8000d26: f000 fcf9 bl 800171c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000d2a: bf00 nop 8000d2c: 3728 adds r7, #40 @ 0x28 8000d2e: 46bd mov sp, r7 8000d30: bd80 pop {r7, pc} 8000d32: bf00 nop 8000d34: 48000400 .word 0x48000400 08000d38 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8000d38: b580 push {r7, lr} 8000d3a: b082 sub sp, #8 8000d3c: af00 add r7, sp, #0 8000d3e: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM17) 8000d40: 687b ldr r3, [r7, #4] 8000d42: 681b ldr r3, [r3, #0] 8000d44: 4a04 ldr r2, [pc, #16] @ (8000d58 ) 8000d46: 4293 cmp r3, r2 8000d48: d101 bne.n 8000d4e { HAL_IncTick(); 8000d4a: f000 fbcf bl 80014ec } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } 8000d4e: bf00 nop 8000d50: 3708 adds r7, #8 8000d52: 46bd mov sp, r7 8000d54: bd80 pop {r7, pc} 8000d56: bf00 nop 8000d58: 40014800 .word 0x40014800 08000d5c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000d5c: b480 push {r7} 8000d5e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000d60: b672 cpsid i } 8000d62: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000d64: bf00 nop 8000d66: e7fd b.n 8000d64 08000d68 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000d68: b580 push {r7, lr} 8000d6a: b082 sub sp, #8 8000d6c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000d6e: 4b11 ldr r3, [pc, #68] @ (8000db4 ) 8000d70: 6e1b ldr r3, [r3, #96] @ 0x60 8000d72: 4a10 ldr r2, [pc, #64] @ (8000db4 ) 8000d74: f043 0301 orr.w r3, r3, #1 8000d78: 6613 str r3, [r2, #96] @ 0x60 8000d7a: 4b0e ldr r3, [pc, #56] @ (8000db4 ) 8000d7c: 6e1b ldr r3, [r3, #96] @ 0x60 8000d7e: f003 0301 and.w r3, r3, #1 8000d82: 607b str r3, [r7, #4] 8000d84: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000d86: 4b0b ldr r3, [pc, #44] @ (8000db4 ) 8000d88: 6d9b ldr r3, [r3, #88] @ 0x58 8000d8a: 4a0a ldr r2, [pc, #40] @ (8000db4 ) 8000d8c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000d90: 6593 str r3, [r2, #88] @ 0x58 8000d92: 4b08 ldr r3, [pc, #32] @ (8000db4 ) 8000d94: 6d9b ldr r3, [r3, #88] @ 0x58 8000d96: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000d9a: 603b str r3, [r7, #0] 8000d9c: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8000d9e: 2200 movs r2, #0 8000da0: 210f movs r1, #15 8000da2: f06f 0001 mvn.w r0, #1 8000da6: f000 fc9d bl 80016e4 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000daa: bf00 nop 8000dac: 3708 adds r7, #8 8000dae: 46bd mov sp, r7 8000db0: bd80 pop {r7, pc} 8000db2: bf00 nop 8000db4: 40021000 .word 0x40021000 08000db8 : * This function configures the hardware resources used in this example * @param hdfsdm_channel: DFSDM_Channel handle pointer * @retval None */ void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel) { 8000db8: b580 push {r7, lr} 8000dba: b0ac sub sp, #176 @ 0xb0 8000dbc: af00 add r7, sp, #0 8000dbe: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000dc0: f107 039c add.w r3, r7, #156 @ 0x9c 8000dc4: 2200 movs r2, #0 8000dc6: 601a str r2, [r3, #0] 8000dc8: 605a str r2, [r3, #4] 8000dca: 609a str r2, [r3, #8] 8000dcc: 60da str r2, [r3, #12] 8000dce: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000dd0: f107 0314 add.w r3, r7, #20 8000dd4: 2288 movs r2, #136 @ 0x88 8000dd6: 2100 movs r1, #0 8000dd8: 4618 mov r0, r3 8000dda: f006 ff4d bl 8007c78 if(DFSDM1_Init == 0) 8000dde: 4b25 ldr r3, [pc, #148] @ (8000e74 ) 8000de0: 681b ldr r3, [r3, #0] 8000de2: 2b00 cmp r3, #0 8000de4: d142 bne.n 8000e6c /* USER CODE END DFSDM1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1; 8000de6: f44f 3380 mov.w r3, #65536 @ 0x10000 8000dea: 617b str r3, [r7, #20] PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK; 8000dec: 2300 movs r3, #0 8000dee: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000df2: f107 0314 add.w r3, r7, #20 8000df6: 4618 mov r0, r3 8000df8: f002 f980 bl 80030fc 8000dfc: 4603 mov r3, r0 8000dfe: 2b00 cmp r3, #0 8000e00: d001 beq.n 8000e06 { Error_Handler(); 8000e02: f7ff ffab bl 8000d5c } /* Peripheral clock enable */ __HAL_RCC_DFSDM1_CLK_ENABLE(); 8000e06: 4b1c ldr r3, [pc, #112] @ (8000e78 ) 8000e08: 6e1b ldr r3, [r3, #96] @ 0x60 8000e0a: 4a1b ldr r2, [pc, #108] @ (8000e78 ) 8000e0c: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8000e10: 6613 str r3, [r2, #96] @ 0x60 8000e12: 4b19 ldr r3, [pc, #100] @ (8000e78 ) 8000e14: 6e1b ldr r3, [r3, #96] @ 0x60 8000e16: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8000e1a: 613b str r3, [r7, #16] 8000e1c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000e1e: 4b16 ldr r3, [pc, #88] @ (8000e78 ) 8000e20: 6cdb ldr r3, [r3, #76] @ 0x4c 8000e22: 4a15 ldr r2, [pc, #84] @ (8000e78 ) 8000e24: f043 0310 orr.w r3, r3, #16 8000e28: 64d3 str r3, [r2, #76] @ 0x4c 8000e2a: 4b13 ldr r3, [pc, #76] @ (8000e78 ) 8000e2c: 6cdb ldr r3, [r3, #76] @ 0x4c 8000e2e: f003 0310 and.w r3, r3, #16 8000e32: 60fb str r3, [r7, #12] 8000e34: 68fb ldr r3, [r7, #12] /**DFSDM1 GPIO Configuration PE7 ------> DFSDM1_DATIN2 PE9 ------> DFSDM1_CKOUT */ GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin; 8000e36: f44f 7320 mov.w r3, #640 @ 0x280 8000e3a: f8c7 309c str.w r3, [r7, #156] @ 0x9c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000e3e: 2302 movs r3, #2 8000e40: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e44: 2300 movs r3, #0 8000e46: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000e4a: 2300 movs r3, #0 8000e4c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1; 8000e50: 2306 movs r3, #6 8000e52: f8c7 30ac str.w r3, [r7, #172] @ 0xac HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000e56: f107 039c add.w r3, r7, #156 @ 0x9c 8000e5a: 4619 mov r1, r3 8000e5c: 4807 ldr r0, [pc, #28] @ (8000e7c ) 8000e5e: f000 fd77 bl 8001950 /* USER CODE BEGIN DFSDM1_MspInit 1 */ /* USER CODE END DFSDM1_MspInit 1 */ DFSDM1_Init++; 8000e62: 4b04 ldr r3, [pc, #16] @ (8000e74 ) 8000e64: 681b ldr r3, [r3, #0] 8000e66: 3301 adds r3, #1 8000e68: 4a02 ldr r2, [pc, #8] @ (8000e74 ) 8000e6a: 6013 str r3, [r2, #0] } } 8000e6c: bf00 nop 8000e6e: 37b0 adds r7, #176 @ 0xb0 8000e70: 46bd mov sp, r7 8000e72: bd80 pop {r7, pc} 8000e74: 200007a4 .word 0x200007a4 8000e78: 40021000 .word 0x40021000 8000e7c: 48001000 .word 0x48001000 08000e80 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8000e80: b580 push {r7, lr} 8000e82: b0ac sub sp, #176 @ 0xb0 8000e84: af00 add r7, sp, #0 8000e86: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e88: f107 039c add.w r3, r7, #156 @ 0x9c 8000e8c: 2200 movs r2, #0 8000e8e: 601a str r2, [r3, #0] 8000e90: 605a str r2, [r3, #4] 8000e92: 609a str r2, [r3, #8] 8000e94: 60da str r2, [r3, #12] 8000e96: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000e98: f107 0314 add.w r3, r7, #20 8000e9c: 2288 movs r2, #136 @ 0x88 8000e9e: 2100 movs r1, #0 8000ea0: 4618 mov r0, r3 8000ea2: f006 fee9 bl 8007c78 if(hi2c->Instance==I2C2) 8000ea6: 687b ldr r3, [r7, #4] 8000ea8: 681b ldr r3, [r3, #0] 8000eaa: 4a21 ldr r2, [pc, #132] @ (8000f30 ) 8000eac: 4293 cmp r3, r2 8000eae: d13b bne.n 8000f28 /* USER CODE END I2C2_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2; 8000eb0: 2380 movs r3, #128 @ 0x80 8000eb2: 617b str r3, [r7, #20] PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1; 8000eb4: 2300 movs r3, #0 8000eb6: 66bb str r3, [r7, #104] @ 0x68 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000eb8: f107 0314 add.w r3, r7, #20 8000ebc: 4618 mov r0, r3 8000ebe: f002 f91d bl 80030fc 8000ec2: 4603 mov r3, r0 8000ec4: 2b00 cmp r3, #0 8000ec6: d001 beq.n 8000ecc { Error_Handler(); 8000ec8: f7ff ff48 bl 8000d5c } __HAL_RCC_GPIOB_CLK_ENABLE(); 8000ecc: 4b19 ldr r3, [pc, #100] @ (8000f34 ) 8000ece: 6cdb ldr r3, [r3, #76] @ 0x4c 8000ed0: 4a18 ldr r2, [pc, #96] @ (8000f34 ) 8000ed2: f043 0302 orr.w r3, r3, #2 8000ed6: 64d3 str r3, [r2, #76] @ 0x4c 8000ed8: 4b16 ldr r3, [pc, #88] @ (8000f34 ) 8000eda: 6cdb ldr r3, [r3, #76] @ 0x4c 8000edc: f003 0302 and.w r3, r3, #2 8000ee0: 613b str r3, [r7, #16] 8000ee2: 693b ldr r3, [r7, #16] /**I2C2 GPIO Configuration PB10 ------> I2C2_SCL PB11 ------> I2C2_SDA */ GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin; 8000ee4: f44f 6340 mov.w r3, #3072 @ 0xc00 8000ee8: f8c7 309c str.w r3, [r7, #156] @ 0x9c GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000eec: 2312 movs r3, #18 8000eee: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 GPIO_InitStruct.Pull = GPIO_PULLUP; 8000ef2: 2301 movs r3, #1 8000ef4: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000ef8: 2303 movs r3, #3 8000efa: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; 8000efe: 2304 movs r3, #4 8000f00: f8c7 30ac str.w r3, [r7, #172] @ 0xac HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000f04: f107 039c add.w r3, r7, #156 @ 0x9c 8000f08: 4619 mov r1, r3 8000f0a: 480b ldr r0, [pc, #44] @ (8000f38 ) 8000f0c: f000 fd20 bl 8001950 /* Peripheral clock enable */ __HAL_RCC_I2C2_CLK_ENABLE(); 8000f10: 4b08 ldr r3, [pc, #32] @ (8000f34 ) 8000f12: 6d9b ldr r3, [r3, #88] @ 0x58 8000f14: 4a07 ldr r2, [pc, #28] @ (8000f34 ) 8000f16: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000f1a: 6593 str r3, [r2, #88] @ 0x58 8000f1c: 4b05 ldr r3, [pc, #20] @ (8000f34 ) 8000f1e: 6d9b ldr r3, [r3, #88] @ 0x58 8000f20: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8000f24: 60fb str r3, [r7, #12] 8000f26: 68fb ldr r3, [r7, #12] /* USER CODE END I2C2_MspInit 1 */ } } 8000f28: bf00 nop 8000f2a: 37b0 adds r7, #176 @ 0xb0 8000f2c: 46bd mov sp, r7 8000f2e: bd80 pop {r7, pc} 8000f30: 40005800 .word 0x40005800 8000f34: 40021000 .word 0x40021000 8000f38: 48000400 .word 0x48000400 08000f3c : * This function configures the hardware resources used in this example * @param hqspi: QSPI handle pointer * @retval None */ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) { 8000f3c: b580 push {r7, lr} 8000f3e: b08a sub sp, #40 @ 0x28 8000f40: af00 add r7, sp, #0 8000f42: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000f44: f107 0314 add.w r3, r7, #20 8000f48: 2200 movs r2, #0 8000f4a: 601a str r2, [r3, #0] 8000f4c: 605a str r2, [r3, #4] 8000f4e: 609a str r2, [r3, #8] 8000f50: 60da str r2, [r3, #12] 8000f52: 611a str r2, [r3, #16] if(hqspi->Instance==QUADSPI) 8000f54: 687b ldr r3, [r7, #4] 8000f56: 681b ldr r3, [r3, #0] 8000f58: 4a17 ldr r2, [pc, #92] @ (8000fb8 ) 8000f5a: 4293 cmp r3, r2 8000f5c: d128 bne.n 8000fb0 { /* USER CODE BEGIN QUADSPI_MspInit 0 */ /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); 8000f5e: 4b17 ldr r3, [pc, #92] @ (8000fbc ) 8000f60: 6d1b ldr r3, [r3, #80] @ 0x50 8000f62: 4a16 ldr r2, [pc, #88] @ (8000fbc ) 8000f64: f443 7380 orr.w r3, r3, #256 @ 0x100 8000f68: 6513 str r3, [r2, #80] @ 0x50 8000f6a: 4b14 ldr r3, [pc, #80] @ (8000fbc ) 8000f6c: 6d1b ldr r3, [r3, #80] @ 0x50 8000f6e: f403 7380 and.w r3, r3, #256 @ 0x100 8000f72: 613b str r3, [r7, #16] 8000f74: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000f76: 4b11 ldr r3, [pc, #68] @ (8000fbc ) 8000f78: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f7a: 4a10 ldr r2, [pc, #64] @ (8000fbc ) 8000f7c: f043 0310 orr.w r3, r3, #16 8000f80: 64d3 str r3, [r2, #76] @ 0x4c 8000f82: 4b0e ldr r3, [pc, #56] @ (8000fbc ) 8000f84: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f86: f003 0310 and.w r3, r3, #16 8000f8a: 60fb str r3, [r7, #12] 8000f8c: 68fb ldr r3, [r7, #12] PE12 ------> QUADSPI_BK1_IO0 PE13 ------> QUADSPI_BK1_IO1 PE14 ------> QUADSPI_BK1_IO2 PE15 ------> QUADSPI_BK1_IO3 */ GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin 8000f8e: f44f 437c mov.w r3, #64512 @ 0xfc00 8000f92: 617b str r3, [r7, #20] |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f94: 2302 movs r3, #2 8000f96: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f98: 2300 movs r3, #0 8000f9a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000f9c: 2303 movs r3, #3 8000f9e: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; 8000fa0: 230a movs r3, #10 8000fa2: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000fa4: f107 0314 add.w r3, r7, #20 8000fa8: 4619 mov r1, r3 8000faa: 4805 ldr r0, [pc, #20] @ (8000fc0 ) 8000fac: f000 fcd0 bl 8001950 /* USER CODE END QUADSPI_MspInit 1 */ } } 8000fb0: bf00 nop 8000fb2: 3728 adds r7, #40 @ 0x28 8000fb4: 46bd mov sp, r7 8000fb6: bd80 pop {r7, pc} 8000fb8: a0001000 .word 0xa0001000 8000fbc: 40021000 .word 0x40021000 8000fc0: 48001000 .word 0x48001000 08000fc4 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8000fc4: b580 push {r7, lr} 8000fc6: b08a sub sp, #40 @ 0x28 8000fc8: af00 add r7, sp, #0 8000fca: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000fcc: f107 0314 add.w r3, r7, #20 8000fd0: 2200 movs r2, #0 8000fd2: 601a str r2, [r3, #0] 8000fd4: 605a str r2, [r3, #4] 8000fd6: 609a str r2, [r3, #8] 8000fd8: 60da str r2, [r3, #12] 8000fda: 611a str r2, [r3, #16] if(hspi->Instance==SPI3) 8000fdc: 687b ldr r3, [r7, #4] 8000fde: 681b ldr r3, [r3, #0] 8000fe0: 4a17 ldr r2, [pc, #92] @ (8001040 ) 8000fe2: 4293 cmp r3, r2 8000fe4: d128 bne.n 8001038 { /* USER CODE BEGIN SPI3_MspInit 0 */ /* USER CODE END SPI3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI3_CLK_ENABLE(); 8000fe6: 4b17 ldr r3, [pc, #92] @ (8001044 ) 8000fe8: 6d9b ldr r3, [r3, #88] @ 0x58 8000fea: 4a16 ldr r2, [pc, #88] @ (8001044 ) 8000fec: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8000ff0: 6593 str r3, [r2, #88] @ 0x58 8000ff2: 4b14 ldr r3, [pc, #80] @ (8001044 ) 8000ff4: 6d9b ldr r3, [r3, #88] @ 0x58 8000ff6: f403 4300 and.w r3, r3, #32768 @ 0x8000 8000ffa: 613b str r3, [r7, #16] 8000ffc: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000ffe: 4b11 ldr r3, [pc, #68] @ (8001044 ) 8001000: 6cdb ldr r3, [r3, #76] @ 0x4c 8001002: 4a10 ldr r2, [pc, #64] @ (8001044 ) 8001004: f043 0304 orr.w r3, r3, #4 8001008: 64d3 str r3, [r2, #76] @ 0x4c 800100a: 4b0e ldr r3, [pc, #56] @ (8001044 ) 800100c: 6cdb ldr r3, [r3, #76] @ 0x4c 800100e: f003 0304 and.w r3, r3, #4 8001012: 60fb str r3, [r7, #12] 8001014: 68fb ldr r3, [r7, #12] /**SPI3 GPIO Configuration PC10 ------> SPI3_SCK PC11 ------> SPI3_MISO PC12 ------> SPI3_MOSI */ GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin; 8001016: f44f 53e0 mov.w r3, #7168 @ 0x1c00 800101a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800101c: 2302 movs r3, #2 800101e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001020: 2300 movs r3, #0 8001022: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001024: 2303 movs r3, #3 8001026: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; 8001028: 2306 movs r3, #6 800102a: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800102c: f107 0314 add.w r3, r7, #20 8001030: 4619 mov r1, r3 8001032: 4805 ldr r0, [pc, #20] @ (8001048 ) 8001034: f000 fc8c bl 8001950 /* USER CODE END SPI3_MspInit 1 */ } } 8001038: bf00 nop 800103a: 3728 adds r7, #40 @ 0x28 800103c: 46bd mov sp, r7 800103e: bd80 pop {r7, pc} 8001040: 40003c00 .word 0x40003c00 8001044: 40021000 .word 0x40021000 8001048: 48000800 .word 0x48000800 0800104c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 800104c: b580 push {r7, lr} 800104e: b0ae sub sp, #184 @ 0xb8 8001050: af00 add r7, sp, #0 8001052: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001054: f107 03a4 add.w r3, r7, #164 @ 0xa4 8001058: 2200 movs r2, #0 800105a: 601a str r2, [r3, #0] 800105c: 605a str r2, [r3, #4] 800105e: 609a str r2, [r3, #8] 8001060: 60da str r2, [r3, #12] 8001062: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001064: f107 031c add.w r3, r7, #28 8001068: 2288 movs r2, #136 @ 0x88 800106a: 2100 movs r1, #0 800106c: 4618 mov r0, r3 800106e: f006 fe03 bl 8007c78 if(huart->Instance==USART1) 8001072: 687b ldr r3, [r7, #4] 8001074: 681b ldr r3, [r3, #0] 8001076: 4a42 ldr r2, [pc, #264] @ (8001180 ) 8001078: 4293 cmp r3, r2 800107a: d13b bne.n 80010f4 /* USER CODE END USART1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; 800107c: 2301 movs r3, #1 800107e: 61fb str r3, [r7, #28] PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 8001080: 2300 movs r3, #0 8001082: 657b str r3, [r7, #84] @ 0x54 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001084: f107 031c add.w r3, r7, #28 8001088: 4618 mov r0, r3 800108a: f002 f837 bl 80030fc 800108e: 4603 mov r3, r0 8001090: 2b00 cmp r3, #0 8001092: d001 beq.n 8001098 { Error_Handler(); 8001094: f7ff fe62 bl 8000d5c } /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8001098: 4b3a ldr r3, [pc, #232] @ (8001184 ) 800109a: 6e1b ldr r3, [r3, #96] @ 0x60 800109c: 4a39 ldr r2, [pc, #228] @ (8001184 ) 800109e: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80010a2: 6613 str r3, [r2, #96] @ 0x60 80010a4: 4b37 ldr r3, [pc, #220] @ (8001184 ) 80010a6: 6e1b ldr r3, [r3, #96] @ 0x60 80010a8: f403 4380 and.w r3, r3, #16384 @ 0x4000 80010ac: 61bb str r3, [r7, #24] 80010ae: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 80010b0: 4b34 ldr r3, [pc, #208] @ (8001184 ) 80010b2: 6cdb ldr r3, [r3, #76] @ 0x4c 80010b4: 4a33 ldr r2, [pc, #204] @ (8001184 ) 80010b6: f043 0302 orr.w r3, r3, #2 80010ba: 64d3 str r3, [r2, #76] @ 0x4c 80010bc: 4b31 ldr r3, [pc, #196] @ (8001184 ) 80010be: 6cdb ldr r3, [r3, #76] @ 0x4c 80010c0: f003 0302 and.w r3, r3, #2 80010c4: 617b str r3, [r7, #20] 80010c6: 697b ldr r3, [r7, #20] /**USART1 GPIO Configuration PB6 ------> USART1_TX PB7 ------> USART1_RX */ GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin; 80010c8: 23c0 movs r3, #192 @ 0xc0 80010ca: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80010ce: 2302 movs r3, #2 80010d0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 GPIO_InitStruct.Pull = GPIO_NOPULL; 80010d4: 2300 movs r3, #0 80010d6: f8c7 30ac str.w r3, [r7, #172] @ 0xac GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80010da: 2303 movs r3, #3 80010dc: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 80010e0: 2307 movs r3, #7 80010e2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80010e6: f107 03a4 add.w r3, r7, #164 @ 0xa4 80010ea: 4619 mov r1, r3 80010ec: 4826 ldr r0, [pc, #152] @ (8001188 ) 80010ee: f000 fc2f bl 8001950 /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 80010f2: e040 b.n 8001176 else if(huart->Instance==USART3) 80010f4: 687b ldr r3, [r7, #4] 80010f6: 681b ldr r3, [r3, #0] 80010f8: 4a24 ldr r2, [pc, #144] @ (800118c ) 80010fa: 4293 cmp r3, r2 80010fc: d13b bne.n 8001176 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3; 80010fe: 2304 movs r3, #4 8001100: 61fb str r3, [r7, #28] PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; 8001102: 2300 movs r3, #0 8001104: 65fb str r3, [r7, #92] @ 0x5c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001106: f107 031c add.w r3, r7, #28 800110a: 4618 mov r0, r3 800110c: f001 fff6 bl 80030fc 8001110: 4603 mov r3, r0 8001112: 2b00 cmp r3, #0 8001114: d001 beq.n 800111a Error_Handler(); 8001116: f7ff fe21 bl 8000d5c __HAL_RCC_USART3_CLK_ENABLE(); 800111a: 4b1a ldr r3, [pc, #104] @ (8001184 ) 800111c: 6d9b ldr r3, [r3, #88] @ 0x58 800111e: 4a19 ldr r2, [pc, #100] @ (8001184 ) 8001120: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8001124: 6593 str r3, [r2, #88] @ 0x58 8001126: 4b17 ldr r3, [pc, #92] @ (8001184 ) 8001128: 6d9b ldr r3, [r3, #88] @ 0x58 800112a: f403 2380 and.w r3, r3, #262144 @ 0x40000 800112e: 613b str r3, [r7, #16] 8001130: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001132: 4b14 ldr r3, [pc, #80] @ (8001184 ) 8001134: 6cdb ldr r3, [r3, #76] @ 0x4c 8001136: 4a13 ldr r2, [pc, #76] @ (8001184 ) 8001138: f043 0308 orr.w r3, r3, #8 800113c: 64d3 str r3, [r2, #76] @ 0x4c 800113e: 4b11 ldr r3, [pc, #68] @ (8001184 ) 8001140: 6cdb ldr r3, [r3, #76] @ 0x4c 8001142: f003 0308 and.w r3, r3, #8 8001146: 60fb str r3, [r7, #12] 8001148: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin; 800114a: f44f 7340 mov.w r3, #768 @ 0x300 800114e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001152: 2302 movs r3, #2 8001154: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001158: 2300 movs r3, #0 800115a: f8c7 30ac str.w r3, [r7, #172] @ 0xac GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800115e: 2303 movs r3, #3 8001160: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 8001164: 2307 movs r3, #7 8001166: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800116a: f107 03a4 add.w r3, r7, #164 @ 0xa4 800116e: 4619 mov r1, r3 8001170: 4807 ldr r0, [pc, #28] @ (8001190 ) 8001172: f000 fbed bl 8001950 } 8001176: bf00 nop 8001178: 37b8 adds r7, #184 @ 0xb8 800117a: 46bd mov sp, r7 800117c: bd80 pop {r7, pc} 800117e: bf00 nop 8001180: 40013800 .word 0x40013800 8001184: 40021000 .word 0x40021000 8001188: 48000400 .word 0x48000400 800118c: 40004800 .word 0x40004800 8001190: 48000c00 .word 0x48000c00 08001194 : * This function configures the hardware resources used in this example * @param hpcd: PCD handle pointer * @retval None */ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) { 8001194: b580 push {r7, lr} 8001196: b0ac sub sp, #176 @ 0xb0 8001198: af00 add r7, sp, #0 800119a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800119c: f107 039c add.w r3, r7, #156 @ 0x9c 80011a0: 2200 movs r2, #0 80011a2: 601a str r2, [r3, #0] 80011a4: 605a str r2, [r3, #4] 80011a6: 609a str r2, [r3, #8] 80011a8: 60da str r2, [r3, #12] 80011aa: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 80011ac: f107 0314 add.w r3, r7, #20 80011b0: 2288 movs r2, #136 @ 0x88 80011b2: 2100 movs r1, #0 80011b4: 4618 mov r0, r3 80011b6: f006 fd5f bl 8007c78 if(hpcd->Instance==USB_OTG_FS) 80011ba: 687b ldr r3, [r7, #4] 80011bc: 681b ldr r3, [r3, #0] 80011be: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 80011c2: d17c bne.n 80012be /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; 80011c4: f44f 5300 mov.w r3, #8192 @ 0x2000 80011c8: 617b str r3, [r7, #20] PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; 80011ca: f04f 6380 mov.w r3, #67108864 @ 0x4000000 80011ce: f8c7 3080 str.w r3, [r7, #128] @ 0x80 PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; 80011d2: 2301 movs r3, #1 80011d4: 61bb str r3, [r7, #24] PeriphClkInit.PLLSAI1.PLLSAI1M = 1; 80011d6: 2301 movs r3, #1 80011d8: 61fb str r3, [r7, #28] PeriphClkInit.PLLSAI1.PLLSAI1N = 24; 80011da: 2318 movs r3, #24 80011dc: 623b str r3, [r7, #32] PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; 80011de: 2307 movs r3, #7 80011e0: 627b str r3, [r7, #36] @ 0x24 PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; 80011e2: 2302 movs r3, #2 80011e4: 62bb str r3, [r7, #40] @ 0x28 PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; 80011e6: 2302 movs r3, #2 80011e8: 62fb str r3, [r7, #44] @ 0x2c PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; 80011ea: f44f 1380 mov.w r3, #1048576 @ 0x100000 80011ee: 633b str r3, [r7, #48] @ 0x30 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80011f0: f107 0314 add.w r3, r7, #20 80011f4: 4618 mov r0, r3 80011f6: f001 ff81 bl 80030fc 80011fa: 4603 mov r3, r0 80011fc: 2b00 cmp r3, #0 80011fe: d001 beq.n 8001204 { Error_Handler(); 8001200: f7ff fdac bl 8000d5c } __HAL_RCC_GPIOA_CLK_ENABLE(); 8001204: 4b30 ldr r3, [pc, #192] @ (80012c8 ) 8001206: 6cdb ldr r3, [r3, #76] @ 0x4c 8001208: 4a2f ldr r2, [pc, #188] @ (80012c8 ) 800120a: f043 0301 orr.w r3, r3, #1 800120e: 64d3 str r3, [r2, #76] @ 0x4c 8001210: 4b2d ldr r3, [pc, #180] @ (80012c8 ) 8001212: 6cdb ldr r3, [r3, #76] @ 0x4c 8001214: f003 0301 and.w r3, r3, #1 8001218: 613b str r3, [r7, #16] 800121a: 693b ldr r3, [r7, #16] PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin; 800121c: f44f 7300 mov.w r3, #512 @ 0x200 8001220: f8c7 309c str.w r3, [r7, #156] @ 0x9c GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001224: 2300 movs r3, #0 8001226: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800122a: 2300 movs r3, #0 800122c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct); 8001230: f107 039c add.w r3, r7, #156 @ 0x9c 8001234: 4619 mov r1, r3 8001236: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 800123a: f000 fb89 bl 8001950 GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin; 800123e: f44f 53e0 mov.w r3, #7168 @ 0x1c00 8001242: f8c7 309c str.w r3, [r7, #156] @ 0x9c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001246: 2302 movs r3, #2 8001248: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800124c: 2300 movs r3, #0 800124e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001252: 2303 movs r3, #3 8001254: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 8001258: 230a movs r3, #10 800125a: f8c7 30ac str.w r3, [r7, #172] @ 0xac HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800125e: f107 039c add.w r3, r7, #156 @ 0x9c 8001262: 4619 mov r1, r3 8001264: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8001268: f000 fb72 bl 8001950 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800126c: 4b16 ldr r3, [pc, #88] @ (80012c8 ) 800126e: 6cdb ldr r3, [r3, #76] @ 0x4c 8001270: 4a15 ldr r2, [pc, #84] @ (80012c8 ) 8001272: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8001276: 64d3 str r3, [r2, #76] @ 0x4c 8001278: 4b13 ldr r3, [pc, #76] @ (80012c8 ) 800127a: 6cdb ldr r3, [r3, #76] @ 0x4c 800127c: f403 5380 and.w r3, r3, #4096 @ 0x1000 8001280: 60fb str r3, [r7, #12] 8001282: 68fb ldr r3, [r7, #12] /* Enable VDDUSB */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001284: 4b10 ldr r3, [pc, #64] @ (80012c8 ) 8001286: 6d9b ldr r3, [r3, #88] @ 0x58 8001288: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800128c: 2b00 cmp r3, #0 800128e: d114 bne.n 80012ba { __HAL_RCC_PWR_CLK_ENABLE(); 8001290: 4b0d ldr r3, [pc, #52] @ (80012c8 ) 8001292: 6d9b ldr r3, [r3, #88] @ 0x58 8001294: 4a0c ldr r2, [pc, #48] @ (80012c8 ) 8001296: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800129a: 6593 str r3, [r2, #88] @ 0x58 800129c: 4b0a ldr r3, [pc, #40] @ (80012c8 ) 800129e: 6d9b ldr r3, [r3, #88] @ 0x58 80012a0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80012a4: 60bb str r3, [r7, #8] 80012a6: 68bb ldr r3, [r7, #8] HAL_PWREx_EnableVddUSB(); 80012a8: f001 f82a bl 8002300 __HAL_RCC_PWR_CLK_DISABLE(); 80012ac: 4b06 ldr r3, [pc, #24] @ (80012c8 ) 80012ae: 6d9b ldr r3, [r3, #88] @ 0x58 80012b0: 4a05 ldr r2, [pc, #20] @ (80012c8 ) 80012b2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80012b6: 6593 str r3, [r2, #88] @ 0x58 /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 80012b8: e001 b.n 80012be HAL_PWREx_EnableVddUSB(); 80012ba: f001 f821 bl 8002300 } 80012be: bf00 nop 80012c0: 37b0 adds r7, #176 @ 0xb0 80012c2: 46bd mov sp, r7 80012c4: bd80 pop {r7, pc} 80012c6: bf00 nop 80012c8: 40021000 .word 0x40021000 080012cc : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80012cc: b580 push {r7, lr} 80012ce: b08c sub sp, #48 @ 0x30 80012d0: af00 add r7, sp, #0 80012d2: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock; uint32_t uwPrescalerValue; uint32_t pFLatency; HAL_StatusTypeDef status = HAL_OK; 80012d4: 2300 movs r3, #0 80012d6: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Enable TIM17 clock */ __HAL_RCC_TIM17_CLK_ENABLE(); 80012da: 4b2e ldr r3, [pc, #184] @ (8001394 ) 80012dc: 6e1b ldr r3, [r3, #96] @ 0x60 80012de: 4a2d ldr r2, [pc, #180] @ (8001394 ) 80012e0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80012e4: 6613 str r3, [r2, #96] @ 0x60 80012e6: 4b2b ldr r3, [pc, #172] @ (8001394 ) 80012e8: 6e1b ldr r3, [r3, #96] @ 0x60 80012ea: f403 2380 and.w r3, r3, #262144 @ 0x40000 80012ee: 60bb str r3, [r7, #8] 80012f0: 68bb ldr r3, [r7, #8] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 80012f2: f107 020c add.w r2, r7, #12 80012f6: f107 0310 add.w r3, r7, #16 80012fa: 4611 mov r1, r2 80012fc: 4618 mov r0, r3 80012fe: f001 fe6b bl 8002fd8 /* Compute TIM17 clock */ uwTimclock = HAL_RCC_GetPCLK2Freq(); 8001302: f001 fe53 bl 8002fac 8001306: 62b8 str r0, [r7, #40] @ 0x28 /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8001308: 6abb ldr r3, [r7, #40] @ 0x28 800130a: 4a23 ldr r2, [pc, #140] @ (8001398 ) 800130c: fba2 2303 umull r2, r3, r2, r3 8001310: 0c9b lsrs r3, r3, #18 8001312: 3b01 subs r3, #1 8001314: 627b str r3, [r7, #36] @ 0x24 /* Initialize TIM17 */ htim17.Instance = TIM17; 8001316: 4b21 ldr r3, [pc, #132] @ (800139c ) 8001318: 4a21 ldr r2, [pc, #132] @ (80013a0 ) 800131a: 601a str r2, [r3, #0] * Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base. * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. * ClockDivision = 0 * Counter direction = Up */ htim17.Init.Period = (1000000U / 1000U) - 1U; 800131c: 4b1f ldr r3, [pc, #124] @ (800139c ) 800131e: f240 32e7 movw r2, #999 @ 0x3e7 8001322: 60da str r2, [r3, #12] htim17.Init.Prescaler = uwPrescalerValue; 8001324: 4a1d ldr r2, [pc, #116] @ (800139c ) 8001326: 6a7b ldr r3, [r7, #36] @ 0x24 8001328: 6053 str r3, [r2, #4] htim17.Init.ClockDivision = 0; 800132a: 4b1c ldr r3, [pc, #112] @ (800139c ) 800132c: 2200 movs r2, #0 800132e: 611a str r2, [r3, #16] htim17.Init.CounterMode = TIM_COUNTERMODE_UP; 8001330: 4b1a ldr r3, [pc, #104] @ (800139c ) 8001332: 2200 movs r2, #0 8001334: 609a str r2, [r3, #8] htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001336: 4b19 ldr r3, [pc, #100] @ (800139c ) 8001338: 2200 movs r2, #0 800133a: 619a str r2, [r3, #24] status = HAL_TIM_Base_Init(&htim17); 800133c: 4817 ldr r0, [pc, #92] @ (800139c ) 800133e: f002 fc4c bl 8003bda 8001342: 4603 mov r3, r0 8001344: f887 302f strb.w r3, [r7, #47] @ 0x2f if (status == HAL_OK) 8001348: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 800134c: 2b00 cmp r3, #0 800134e: d11b bne.n 8001388 { /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&htim17); 8001350: 4812 ldr r0, [pc, #72] @ (800139c ) 8001352: f002 fca3 bl 8003c9c 8001356: 4603 mov r3, r0 8001358: f887 302f strb.w r3, [r7, #47] @ 0x2f if (status == HAL_OK) 800135c: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8001360: 2b00 cmp r3, #0 8001362: d111 bne.n 8001388 { /* Enable the TIM17 global Interrupt */ HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); 8001364: 201a movs r0, #26 8001366: f000 f9d9 bl 800171c /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800136a: 687b ldr r3, [r7, #4] 800136c: 2b0f cmp r3, #15 800136e: d808 bhi.n 8001382 { /* Configure the TIM IRQ priority */ HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority, 0U); 8001370: 2200 movs r2, #0 8001372: 6879 ldr r1, [r7, #4] 8001374: 201a movs r0, #26 8001376: f000 f9b5 bl 80016e4 uwTickPrio = TickPriority; 800137a: 4a0a ldr r2, [pc, #40] @ (80013a4 ) 800137c: 687b ldr r3, [r7, #4] 800137e: 6013 str r3, [r2, #0] 8001380: e002 b.n 8001388 } else { status = HAL_ERROR; 8001382: 2301 movs r3, #1 8001384: f887 302f strb.w r3, [r7, #47] @ 0x2f } } } /* Return function status */ return status; 8001388: f897 302f ldrb.w r3, [r7, #47] @ 0x2f } 800138c: 4618 mov r0, r3 800138e: 3730 adds r7, #48 @ 0x30 8001390: 46bd mov sp, r7 8001392: bd80 pop {r7, pc} 8001394: 40021000 .word 0x40021000 8001398: 431bde83 .word 0x431bde83 800139c: 200007a8 .word 0x200007a8 80013a0: 40014800 .word 0x40014800 80013a4: 20000004 .word 0x20000004 080013a8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80013a8: b480 push {r7} 80013aa: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80013ac: bf00 nop 80013ae: e7fd b.n 80013ac 080013b0 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80013b0: b480 push {r7} 80013b2: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80013b4: bf00 nop 80013b6: e7fd b.n 80013b4 080013b8 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80013b8: b480 push {r7} 80013ba: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80013bc: bf00 nop 80013be: e7fd b.n 80013bc 080013c0 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80013c0: b480 push {r7} 80013c2: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80013c4: bf00 nop 80013c6: e7fd b.n 80013c4 080013c8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80013c8: b480 push {r7} 80013ca: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80013cc: bf00 nop 80013ce: e7fd b.n 80013cc 080013d0 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80013d0: b480 push {r7} 80013d2: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80013d4: bf00 nop 80013d6: 46bd mov sp, r7 80013d8: f85d 7b04 ldr.w r7, [sp], #4 80013dc: 4770 bx lr 080013de : /** * @brief This function handles EXTI line[9:5] interrupts. */ void EXTI9_5_IRQHandler(void) { 80013de: b580 push {r7, lr} 80013e0: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ /* USER CODE END EXTI9_5_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(SPSGRF_915_GPIO3_EXTI5_Pin); 80013e2: 2020 movs r0, #32 80013e4: f000 fc90 bl 8001d08 HAL_GPIO_EXTI_IRQHandler(SPBTLE_RF_IRQ_EXTI6_Pin); 80013e8: 2040 movs r0, #64 @ 0x40 80013ea: f000 fc8d bl 8001d08 HAL_GPIO_EXTI_IRQHandler(VL53L0X_GPIO1_EXTI7_Pin); 80013ee: 2080 movs r0, #128 @ 0x80 80013f0: f000 fc8a bl 8001d08 HAL_GPIO_EXTI_IRQHandler(LSM3MDL_DRDY_EXTI8_Pin); 80013f4: f44f 7080 mov.w r0, #256 @ 0x100 80013f8: f000 fc86 bl 8001d08 /* USER CODE BEGIN EXTI9_5_IRQn 1 */ /* USER CODE END EXTI9_5_IRQn 1 */ } 80013fc: bf00 nop 80013fe: bd80 pop {r7, pc} 08001400 : /** * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt. */ void TIM1_TRG_COM_TIM17_IRQHandler(void) { 8001400: b580 push {r7, lr} 8001402: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */ /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */ HAL_TIM_IRQHandler(&htim17); 8001404: 4802 ldr r0, [pc, #8] @ (8001410 ) 8001406: f002 fcb9 bl 8003d7c /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */ /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */ } 800140a: bf00 nop 800140c: bd80 pop {r7, pc} 800140e: bf00 nop 8001410: 200007a8 .word 0x200007a8 08001414 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8001414: b580 push {r7, lr} 8001416: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(LPS22HB_INT_DRDY_EXTI0_Pin); 8001418: f44f 6080 mov.w r0, #1024 @ 0x400 800141c: f000 fc74 bl 8001d08 HAL_GPIO_EXTI_IRQHandler(LSM6DSL_INT1_EXTI11_Pin); 8001420: f44f 6000 mov.w r0, #2048 @ 0x800 8001424: f000 fc70 bl 8001d08 HAL_GPIO_EXTI_IRQHandler(BUTTON_EXTI13_Pin); 8001428: f44f 5000 mov.w r0, #8192 @ 0x2000 800142c: f000 fc6c bl 8001d08 HAL_GPIO_EXTI_IRQHandler(ARD_D2_Pin); 8001430: f44f 4080 mov.w r0, #16384 @ 0x4000 8001434: f000 fc68 bl 8001d08 HAL_GPIO_EXTI_IRQHandler(HTS221_DRDY_EXTI15_Pin); 8001438: f44f 4000 mov.w r0, #32768 @ 0x8000 800143c: f000 fc64 bl 8001d08 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 8001440: bf00 nop 8001442: bd80 pop {r7, pc} 08001444 : * @brief Setup the microcontroller system. * @retval None */ void SystemInit(void) { 8001444: b480 push {r7} 8001446: af00 add r7, sp, #0 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; #endif /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ 8001448: 4b06 ldr r3, [pc, #24] @ (8001464 ) 800144a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800144e: 4a05 ldr r2, [pc, #20] @ (8001464 ) 8001450: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8001454: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif } 8001458: bf00 nop 800145a: 46bd mov sp, r7 800145c: f85d 7b04 ldr.w r7, [sp], #4 8001460: 4770 bx lr 8001462: bf00 nop 8001464: e000ed00 .word 0xe000ed00 08001468 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Set stack pointer */ 8001468: f8df d034 ldr.w sp, [pc, #52] @ 80014a0 /* Call the clock system initialization function.*/ bl SystemInit 800146c: f7ff ffea bl 8001444 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001470: 480c ldr r0, [pc, #48] @ (80014a4 ) ldr r1, =_edata 8001472: 490d ldr r1, [pc, #52] @ (80014a8 ) ldr r2, =_sidata 8001474: 4a0d ldr r2, [pc, #52] @ (80014ac ) movs r3, #0 8001476: 2300 movs r3, #0 b LoopCopyDataInit 8001478: e002 b.n 8001480 0800147a : CopyDataInit: ldr r4, [r2, r3] 800147a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800147c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800147e: 3304 adds r3, #4 08001480 : LoopCopyDataInit: adds r4, r0, r3 8001480: 18c4 adds r4, r0, r3 cmp r4, r1 8001482: 428c cmp r4, r1 bcc CopyDataInit 8001484: d3f9 bcc.n 800147a /* Zero fill the bss segment. */ ldr r2, =_sbss 8001486: 4a0a ldr r2, [pc, #40] @ (80014b0 ) ldr r4, =_ebss 8001488: 4c0a ldr r4, [pc, #40] @ (80014b4 ) movs r3, #0 800148a: 2300 movs r3, #0 b LoopFillZerobss 800148c: e001 b.n 8001492 0800148e : FillZerobss: str r3, [r2] 800148e: 6013 str r3, [r2, #0] adds r2, r2, #4 8001490: 3204 adds r2, #4 08001492 : LoopFillZerobss: cmp r2, r4 8001492: 42a2 cmp r2, r4 bcc FillZerobss 8001494: d3fb bcc.n 800148e /* Call static constructors */ bl __libc_init_array 8001496: f006 fc55 bl 8007d44 <__libc_init_array> /* Call the application's entry point.*/ bl main 800149a: f7ff f8b3 bl 8000604
0800149e : LoopForever: b LoopForever 800149e: e7fe b.n 800149e ldr sp, =_estack /* Set stack pointer */ 80014a0: 20018000 .word 0x20018000 ldr r0, =_sdata 80014a4: 20000000 .word 0x20000000 ldr r1, =_edata 80014a8: 20000060 .word 0x20000060 ldr r2, =_sidata 80014ac: 08007f04 .word 0x08007f04 ldr r2, =_sbss 80014b0: 20000060 .word 0x20000060 ldr r4, =_ebss 80014b4: 20008c74 .word 0x20008c74 080014b8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80014b8: e7fe b.n 80014b8 080014ba : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80014ba: b580 push {r7, lr} 80014bc: b082 sub sp, #8 80014be: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 80014c0: 2300 movs r3, #0 80014c2: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80014c4: 2003 movs r0, #3 80014c6: f000 f902 bl 80016ce /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 80014ca: 200f movs r0, #15 80014cc: f7ff fefe bl 80012cc 80014d0: 4603 mov r3, r0 80014d2: 2b00 cmp r3, #0 80014d4: d002 beq.n 80014dc { status = HAL_ERROR; 80014d6: 2301 movs r3, #1 80014d8: 71fb strb r3, [r7, #7] 80014da: e001 b.n 80014e0 } else { /* Init the low level hardware */ HAL_MspInit(); 80014dc: f7ff fc44 bl 8000d68 } /* Return function status */ return status; 80014e0: 79fb ldrb r3, [r7, #7] } 80014e2: 4618 mov r0, r3 80014e4: 3708 adds r7, #8 80014e6: 46bd mov sp, r7 80014e8: bd80 pop {r7, pc} ... 080014ec : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80014ec: b480 push {r7} 80014ee: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 80014f0: 4b06 ldr r3, [pc, #24] @ (800150c ) 80014f2: 781b ldrb r3, [r3, #0] 80014f4: 461a mov r2, r3 80014f6: 4b06 ldr r3, [pc, #24] @ (8001510 ) 80014f8: 681b ldr r3, [r3, #0] 80014fa: 4413 add r3, r2 80014fc: 4a04 ldr r2, [pc, #16] @ (8001510 ) 80014fe: 6013 str r3, [r2, #0] } 8001500: bf00 nop 8001502: 46bd mov sp, r7 8001504: f85d 7b04 ldr.w r7, [sp], #4 8001508: 4770 bx lr 800150a: bf00 nop 800150c: 20000008 .word 0x20000008 8001510: 200007f4 .word 0x200007f4 08001514 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001514: b480 push {r7} 8001516: af00 add r7, sp, #0 return uwTick; 8001518: 4b03 ldr r3, [pc, #12] @ (8001528 ) 800151a: 681b ldr r3, [r3, #0] } 800151c: 4618 mov r0, r3 800151e: 46bd mov sp, r7 8001520: f85d 7b04 ldr.w r7, [sp], #4 8001524: 4770 bx lr 8001526: bf00 nop 8001528: 200007f4 .word 0x200007f4 0800152c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800152c: b580 push {r7, lr} 800152e: b084 sub sp, #16 8001530: af00 add r7, sp, #0 8001532: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001534: f7ff ffee bl 8001514 8001538: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800153a: 687b ldr r3, [r7, #4] 800153c: 60fb str r3, [r7, #12] /* Add a period to guaranty minimum wait */ if (wait < HAL_MAX_DELAY) 800153e: 68fb ldr r3, [r7, #12] 8001540: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001544: d005 beq.n 8001552 { wait += (uint32_t)uwTickFreq; 8001546: 4b0a ldr r3, [pc, #40] @ (8001570 ) 8001548: 781b ldrb r3, [r3, #0] 800154a: 461a mov r2, r3 800154c: 68fb ldr r3, [r7, #12] 800154e: 4413 add r3, r2 8001550: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8001552: bf00 nop 8001554: f7ff ffde bl 8001514 8001558: 4602 mov r2, r0 800155a: 68bb ldr r3, [r7, #8] 800155c: 1ad3 subs r3, r2, r3 800155e: 68fa ldr r2, [r7, #12] 8001560: 429a cmp r2, r3 8001562: d8f7 bhi.n 8001554 { } } 8001564: bf00 nop 8001566: bf00 nop 8001568: 3710 adds r7, #16 800156a: 46bd mov sp, r7 800156c: bd80 pop {r7, pc} 800156e: bf00 nop 8001570: 20000008 .word 0x20000008 08001574 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001574: b480 push {r7} 8001576: b085 sub sp, #20 8001578: af00 add r7, sp, #0 800157a: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800157c: 687b ldr r3, [r7, #4] 800157e: f003 0307 and.w r3, r3, #7 8001582: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001584: 4b0c ldr r3, [pc, #48] @ (80015b8 <__NVIC_SetPriorityGrouping+0x44>) 8001586: 68db ldr r3, [r3, #12] 8001588: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800158a: 68ba ldr r2, [r7, #8] 800158c: f64f 03ff movw r3, #63743 @ 0xf8ff 8001590: 4013 ands r3, r2 8001592: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001594: 68fb ldr r3, [r7, #12] 8001596: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001598: 68bb ldr r3, [r7, #8] 800159a: 4313 orrs r3, r2 reg_value = (reg_value | 800159c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80015a0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80015a4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80015a6: 4a04 ldr r2, [pc, #16] @ (80015b8 <__NVIC_SetPriorityGrouping+0x44>) 80015a8: 68bb ldr r3, [r7, #8] 80015aa: 60d3 str r3, [r2, #12] } 80015ac: bf00 nop 80015ae: 3714 adds r7, #20 80015b0: 46bd mov sp, r7 80015b2: f85d 7b04 ldr.w r7, [sp], #4 80015b6: 4770 bx lr 80015b8: e000ed00 .word 0xe000ed00 080015bc <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80015bc: b480 push {r7} 80015be: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80015c0: 4b04 ldr r3, [pc, #16] @ (80015d4 <__NVIC_GetPriorityGrouping+0x18>) 80015c2: 68db ldr r3, [r3, #12] 80015c4: 0a1b lsrs r3, r3, #8 80015c6: f003 0307 and.w r3, r3, #7 } 80015ca: 4618 mov r0, r3 80015cc: 46bd mov sp, r7 80015ce: f85d 7b04 ldr.w r7, [sp], #4 80015d2: 4770 bx lr 80015d4: e000ed00 .word 0xe000ed00 080015d8 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80015d8: b480 push {r7} 80015da: b083 sub sp, #12 80015dc: af00 add r7, sp, #0 80015de: 4603 mov r3, r0 80015e0: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80015e2: f997 3007 ldrsb.w r3, [r7, #7] 80015e6: 2b00 cmp r3, #0 80015e8: db0b blt.n 8001602 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80015ea: 79fb ldrb r3, [r7, #7] 80015ec: f003 021f and.w r2, r3, #31 80015f0: 4907 ldr r1, [pc, #28] @ (8001610 <__NVIC_EnableIRQ+0x38>) 80015f2: f997 3007 ldrsb.w r3, [r7, #7] 80015f6: 095b lsrs r3, r3, #5 80015f8: 2001 movs r0, #1 80015fa: fa00 f202 lsl.w r2, r0, r2 80015fe: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001602: bf00 nop 8001604: 370c adds r7, #12 8001606: 46bd mov sp, r7 8001608: f85d 7b04 ldr.w r7, [sp], #4 800160c: 4770 bx lr 800160e: bf00 nop 8001610: e000e100 .word 0xe000e100 08001614 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001614: b480 push {r7} 8001616: b083 sub sp, #12 8001618: af00 add r7, sp, #0 800161a: 4603 mov r3, r0 800161c: 6039 str r1, [r7, #0] 800161e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001620: f997 3007 ldrsb.w r3, [r7, #7] 8001624: 2b00 cmp r3, #0 8001626: db0a blt.n 800163e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001628: 683b ldr r3, [r7, #0] 800162a: b2da uxtb r2, r3 800162c: 490c ldr r1, [pc, #48] @ (8001660 <__NVIC_SetPriority+0x4c>) 800162e: f997 3007 ldrsb.w r3, [r7, #7] 8001632: 0112 lsls r2, r2, #4 8001634: b2d2 uxtb r2, r2 8001636: 440b add r3, r1 8001638: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 800163c: e00a b.n 8001654 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800163e: 683b ldr r3, [r7, #0] 8001640: b2da uxtb r2, r3 8001642: 4908 ldr r1, [pc, #32] @ (8001664 <__NVIC_SetPriority+0x50>) 8001644: 79fb ldrb r3, [r7, #7] 8001646: f003 030f and.w r3, r3, #15 800164a: 3b04 subs r3, #4 800164c: 0112 lsls r2, r2, #4 800164e: b2d2 uxtb r2, r2 8001650: 440b add r3, r1 8001652: 761a strb r2, [r3, #24] } 8001654: bf00 nop 8001656: 370c adds r7, #12 8001658: 46bd mov sp, r7 800165a: f85d 7b04 ldr.w r7, [sp], #4 800165e: 4770 bx lr 8001660: e000e100 .word 0xe000e100 8001664: e000ed00 .word 0xe000ed00 08001668 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001668: b480 push {r7} 800166a: b089 sub sp, #36 @ 0x24 800166c: af00 add r7, sp, #0 800166e: 60f8 str r0, [r7, #12] 8001670: 60b9 str r1, [r7, #8] 8001672: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001674: 68fb ldr r3, [r7, #12] 8001676: f003 0307 and.w r3, r3, #7 800167a: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800167c: 69fb ldr r3, [r7, #28] 800167e: f1c3 0307 rsb r3, r3, #7 8001682: 2b04 cmp r3, #4 8001684: bf28 it cs 8001686: 2304 movcs r3, #4 8001688: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800168a: 69fb ldr r3, [r7, #28] 800168c: 3304 adds r3, #4 800168e: 2b06 cmp r3, #6 8001690: d902 bls.n 8001698 8001692: 69fb ldr r3, [r7, #28] 8001694: 3b03 subs r3, #3 8001696: e000 b.n 800169a 8001698: 2300 movs r3, #0 800169a: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800169c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80016a0: 69bb ldr r3, [r7, #24] 80016a2: fa02 f303 lsl.w r3, r2, r3 80016a6: 43da mvns r2, r3 80016a8: 68bb ldr r3, [r7, #8] 80016aa: 401a ands r2, r3 80016ac: 697b ldr r3, [r7, #20] 80016ae: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80016b0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80016b4: 697b ldr r3, [r7, #20] 80016b6: fa01 f303 lsl.w r3, r1, r3 80016ba: 43d9 mvns r1, r3 80016bc: 687b ldr r3, [r7, #4] 80016be: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80016c0: 4313 orrs r3, r2 ); } 80016c2: 4618 mov r0, r3 80016c4: 3724 adds r7, #36 @ 0x24 80016c6: 46bd mov sp, r7 80016c8: f85d 7b04 ldr.w r7, [sp], #4 80016cc: 4770 bx lr 080016ce : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80016ce: b580 push {r7, lr} 80016d0: b082 sub sp, #8 80016d2: af00 add r7, sp, #0 80016d4: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80016d6: 6878 ldr r0, [r7, #4] 80016d8: f7ff ff4c bl 8001574 <__NVIC_SetPriorityGrouping> } 80016dc: bf00 nop 80016de: 3708 adds r7, #8 80016e0: 46bd mov sp, r7 80016e2: bd80 pop {r7, pc} 080016e4 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80016e4: b580 push {r7, lr} 80016e6: b086 sub sp, #24 80016e8: af00 add r7, sp, #0 80016ea: 4603 mov r3, r0 80016ec: 60b9 str r1, [r7, #8] 80016ee: 607a str r2, [r7, #4] 80016f0: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; 80016f2: 2300 movs r3, #0 80016f4: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80016f6: f7ff ff61 bl 80015bc <__NVIC_GetPriorityGrouping> 80016fa: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80016fc: 687a ldr r2, [r7, #4] 80016fe: 68b9 ldr r1, [r7, #8] 8001700: 6978 ldr r0, [r7, #20] 8001702: f7ff ffb1 bl 8001668 8001706: 4602 mov r2, r0 8001708: f997 300f ldrsb.w r3, [r7, #15] 800170c: 4611 mov r1, r2 800170e: 4618 mov r0, r3 8001710: f7ff ff80 bl 8001614 <__NVIC_SetPriority> } 8001714: bf00 nop 8001716: 3718 adds r7, #24 8001718: 46bd mov sp, r7 800171a: bd80 pop {r7, pc} 0800171c : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800171c: b580 push {r7, lr} 800171e: b082 sub sp, #8 8001720: af00 add r7, sp, #0 8001722: 4603 mov r3, r0 8001724: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001726: f997 3007 ldrsb.w r3, [r7, #7] 800172a: 4618 mov r0, r3 800172c: f7ff ff54 bl 80015d8 <__NVIC_EnableIRQ> } 8001730: bf00 nop 8001732: 3708 adds r7, #8 8001734: 46bd mov sp, r7 8001736: bd80 pop {r7, pc} 08001738 : * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { 8001738: b580 push {r7, lr} 800173a: b082 sub sp, #8 800173c: af00 add r7, sp, #0 800173e: 6078 str r0, [r7, #4] /* Check DFSDM Channel handle */ if (hdfsdm_channel == NULL) 8001740: 687b ldr r3, [r7, #4] 8001742: 2b00 cmp r3, #0 8001744: d101 bne.n 800174a { return HAL_ERROR; 8001746: 2301 movs r3, #1 8001748: e0ac b.n 80018a4 assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling)); assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset)); assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift)); /* Check that channel has not been already initialized */ if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) 800174a: 687b ldr r3, [r7, #4] 800174c: 681b ldr r3, [r3, #0] 800174e: 4618 mov r0, r3 8001750: f000 f8b2 bl 80018b8 8001754: 4603 mov r3, r0 8001756: 4a55 ldr r2, [pc, #340] @ (80018ac ) 8001758: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800175c: 2b00 cmp r3, #0 800175e: d001 beq.n 8001764 { return HAL_ERROR; 8001760: 2301 movs r3, #1 8001762: e09f b.n 80018a4 hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; } hdfsdm_channel->MspInitCallback(hdfsdm_channel); #else /* Call MSP init function */ HAL_DFSDM_ChannelMspInit(hdfsdm_channel); 8001764: 6878 ldr r0, [r7, #4] 8001766: f7ff fb27 bl 8000db8 #endif /* Update the channel counter */ v_dfsdm1ChannelCounter++; 800176a: 4b51 ldr r3, [pc, #324] @ (80018b0 ) 800176c: 681b ldr r3, [r3, #0] 800176e: 3301 adds r3, #1 8001770: 4a4f ldr r2, [pc, #316] @ (80018b0 ) 8001772: 6013 str r3, [r2, #0] /* Configure output serial clock and enable global DFSDM interface only for first channel */ if (v_dfsdm1ChannelCounter == 1U) 8001774: 4b4e ldr r3, [pc, #312] @ (80018b0 ) 8001776: 681b ldr r3, [r3, #0] 8001778: 2b01 cmp r3, #1 800177a: d125 bne.n 80017c8 { assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection)); /* Set the output serial clock source */ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); 800177c: 4b4d ldr r3, [pc, #308] @ (80018b4 ) 800177e: 681b ldr r3, [r3, #0] 8001780: 4a4c ldr r2, [pc, #304] @ (80018b4 ) 8001782: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8001786: 6013 str r3, [r2, #0] DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; 8001788: 4b4a ldr r3, [pc, #296] @ (80018b4 ) 800178a: 681a ldr r2, [r3, #0] 800178c: 687b ldr r3, [r7, #4] 800178e: 689b ldr r3, [r3, #8] 8001790: 4948 ldr r1, [pc, #288] @ (80018b4 ) 8001792: 4313 orrs r3, r2 8001794: 600b str r3, [r1, #0] /* Reset clock divider */ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); 8001796: 4b47 ldr r3, [pc, #284] @ (80018b4 ) 8001798: 681b ldr r3, [r3, #0] 800179a: 4a46 ldr r2, [pc, #280] @ (80018b4 ) 800179c: f423 037f bic.w r3, r3, #16711680 @ 0xff0000 80017a0: 6013 str r3, [r2, #0] if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE) 80017a2: 687b ldr r3, [r7, #4] 80017a4: 791b ldrb r3, [r3, #4] 80017a6: 2b01 cmp r3, #1 80017a8: d108 bne.n 80017bc { assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) << 80017aa: 4b42 ldr r3, [pc, #264] @ (80018b4 ) 80017ac: 681a ldr r2, [r3, #0] 80017ae: 687b ldr r3, [r7, #4] 80017b0: 68db ldr r3, [r3, #12] 80017b2: 3b01 subs r3, #1 80017b4: 041b lsls r3, r3, #16 80017b6: 493f ldr r1, [pc, #252] @ (80018b4 ) 80017b8: 4313 orrs r3, r2 80017ba: 600b str r3, [r1, #0] DFSDM_CHCFGR1_CKOUTDIV_Pos); } /* enable the DFSDM global interface */ DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; 80017bc: 4b3d ldr r3, [pc, #244] @ (80018b4 ) 80017be: 681b ldr r3, [r3, #0] 80017c0: 4a3c ldr r2, [pc, #240] @ (80018b4 ) 80017c2: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80017c6: 6013 str r3, [r2, #0] } /* Set channel input parameters */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | 80017c8: 687b ldr r3, [r7, #4] 80017ca: 681b ldr r3, [r3, #0] 80017cc: 681a ldr r2, [r3, #0] 80017ce: 687b ldr r3, [r7, #4] 80017d0: 681b ldr r3, [r3, #0] 80017d2: f422 4271 bic.w r2, r2, #61696 @ 0xf100 80017d6: 601a str r2, [r3, #0] DFSDM_CHCFGR1_CHINSEL); hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | 80017d8: 687b ldr r3, [r7, #4] 80017da: 681b ldr r3, [r3, #0] 80017dc: 6819 ldr r1, [r3, #0] 80017de: 687b ldr r3, [r7, #4] 80017e0: 691a ldr r2, [r3, #16] hdfsdm_channel->Init.Input.DataPacking | 80017e2: 687b ldr r3, [r7, #4] 80017e4: 695b ldr r3, [r3, #20] hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | 80017e6: 431a orrs r2, r3 hdfsdm_channel->Init.Input.Pins); 80017e8: 687b ldr r3, [r7, #4] 80017ea: 699b ldr r3, [r3, #24] hdfsdm_channel->Init.Input.DataPacking | 80017ec: 431a orrs r2, r3 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | 80017ee: 687b ldr r3, [r7, #4] 80017f0: 681b ldr r3, [r3, #0] 80017f2: 430a orrs r2, r1 80017f4: 601a str r2, [r3, #0] /* Set serial interface parameters */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); 80017f6: 687b ldr r3, [r7, #4] 80017f8: 681b ldr r3, [r3, #0] 80017fa: 681a ldr r2, [r3, #0] 80017fc: 687b ldr r3, [r7, #4] 80017fe: 681b ldr r3, [r3, #0] 8001800: f022 020f bic.w r2, r2, #15 8001804: 601a str r2, [r3, #0] hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | 8001806: 687b ldr r3, [r7, #4] 8001808: 681b ldr r3, [r3, #0] 800180a: 6819 ldr r1, [r3, #0] 800180c: 687b ldr r3, [r7, #4] 800180e: 69da ldr r2, [r3, #28] hdfsdm_channel->Init.SerialInterface.SpiClock); 8001810: 687b ldr r3, [r7, #4] 8001812: 6a1b ldr r3, [r3, #32] hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | 8001814: 431a orrs r2, r3 8001816: 687b ldr r3, [r7, #4] 8001818: 681b ldr r3, [r3, #0] 800181a: 430a orrs r2, r1 800181c: 601a str r2, [r3, #0] /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); 800181e: 687b ldr r3, [r7, #4] 8001820: 681b ldr r3, [r3, #0] 8001822: 689a ldr r2, [r3, #8] 8001824: 687b ldr r3, [r7, #4] 8001826: 681b ldr r3, [r3, #0] 8001828: f422 025f bic.w r2, r2, #14614528 @ 0xdf0000 800182c: 609a str r2, [r3, #8] hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | 800182e: 687b ldr r3, [r7, #4] 8001830: 681b ldr r3, [r3, #0] 8001832: 6899 ldr r1, [r3, #8] 8001834: 687b ldr r3, [r7, #4] 8001836: 6a5a ldr r2, [r3, #36] @ 0x24 ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); 8001838: 687b ldr r3, [r7, #4] 800183a: 6a9b ldr r3, [r3, #40] @ 0x28 800183c: 3b01 subs r3, #1 800183e: 041b lsls r3, r3, #16 hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | 8001840: 431a orrs r2, r3 8001842: 687b ldr r3, [r7, #4] 8001844: 681b ldr r3, [r3, #0] 8001846: 430a orrs r2, r1 8001848: 609a str r2, [r3, #8] /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); 800184a: 687b ldr r3, [r7, #4] 800184c: 681b ldr r3, [r3, #0] 800184e: 685a ldr r2, [r3, #4] 8001850: 687b ldr r3, [r7, #4] 8001852: 681b ldr r3, [r3, #0] 8001854: f002 0207 and.w r2, r2, #7 8001858: 605a str r2, [r3, #4] hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | 800185a: 687b ldr r3, [r7, #4] 800185c: 681b ldr r3, [r3, #0] 800185e: 6859 ldr r1, [r3, #4] 8001860: 687b ldr r3, [r7, #4] 8001862: 6adb ldr r3, [r3, #44] @ 0x2c 8001864: 021a lsls r2, r3, #8 (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); 8001866: 687b ldr r3, [r7, #4] 8001868: 6b1b ldr r3, [r3, #48] @ 0x30 800186a: 00db lsls r3, r3, #3 hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | 800186c: 431a orrs r2, r3 800186e: 687b ldr r3, [r7, #4] 8001870: 681b ldr r3, [r3, #0] 8001872: 430a orrs r2, r1 8001874: 605a str r2, [r3, #4] /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; 8001876: 687b ldr r3, [r7, #4] 8001878: 681b ldr r3, [r3, #0] 800187a: 681a ldr r2, [r3, #0] 800187c: 687b ldr r3, [r7, #4] 800187e: 681b ldr r3, [r3, #0] 8001880: f042 0280 orr.w r2, r2, #128 @ 0x80 8001884: 601a str r2, [r3, #0] /* Set DFSDM Channel to ready state */ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; 8001886: 687b ldr r3, [r7, #4] 8001888: 2201 movs r2, #1 800188a: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Store channel handle in DFSDM channel handle table */ a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; 800188e: 687b ldr r3, [r7, #4] 8001890: 681b ldr r3, [r3, #0] 8001892: 4618 mov r0, r3 8001894: f000 f810 bl 80018b8 8001898: 4602 mov r2, r0 800189a: 4904 ldr r1, [pc, #16] @ (80018ac ) 800189c: 687b ldr r3, [r7, #4] 800189e: f841 3022 str.w r3, [r1, r2, lsl #2] return HAL_OK; 80018a2: 2300 movs r3, #0 } 80018a4: 4618 mov r0, r3 80018a6: 3708 adds r7, #8 80018a8: 46bd mov sp, r7 80018aa: bd80 pop {r7, pc} 80018ac: 200007fc .word 0x200007fc 80018b0: 200007f8 .word 0x200007f8 80018b4: 40016000 .word 0x40016000 080018b8 : * @brief This function allows to get the channel number from channel instance. * @param Instance DFSDM channel instance. * @retval Channel number. */ static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance) { 80018b8: b480 push {r7} 80018ba: b085 sub sp, #20 80018bc: af00 add r7, sp, #0 80018be: 6078 str r0, [r7, #4] uint32_t channel; /* Get channel from instance */ if (Instance == DFSDM1_Channel0) 80018c0: 687b ldr r3, [r7, #4] 80018c2: 4a1c ldr r2, [pc, #112] @ (8001934 ) 80018c4: 4293 cmp r3, r2 80018c6: d102 bne.n 80018ce { channel = 0; 80018c8: 2300 movs r3, #0 80018ca: 60fb str r3, [r7, #12] 80018cc: e02b b.n 8001926 } else if (Instance == DFSDM1_Channel1) 80018ce: 687b ldr r3, [r7, #4] 80018d0: 4a19 ldr r2, [pc, #100] @ (8001938 ) 80018d2: 4293 cmp r3, r2 80018d4: d102 bne.n 80018dc { channel = 1; 80018d6: 2301 movs r3, #1 80018d8: 60fb str r3, [r7, #12] 80018da: e024 b.n 8001926 } else if (Instance == DFSDM1_Channel2) 80018dc: 687b ldr r3, [r7, #4] 80018de: 4a17 ldr r2, [pc, #92] @ (800193c ) 80018e0: 4293 cmp r3, r2 80018e2: d102 bne.n 80018ea { channel = 2; 80018e4: 2302 movs r3, #2 80018e6: 60fb str r3, [r7, #12] 80018e8: e01d b.n 8001926 } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) else if (Instance == DFSDM1_Channel4) 80018ea: 687b ldr r3, [r7, #4] 80018ec: 4a14 ldr r2, [pc, #80] @ (8001940 ) 80018ee: 4293 cmp r3, r2 80018f0: d102 bne.n 80018f8 { channel = 4; 80018f2: 2304 movs r3, #4 80018f4: 60fb str r3, [r7, #12] 80018f6: e016 b.n 8001926 } else if (Instance == DFSDM1_Channel5) 80018f8: 687b ldr r3, [r7, #4] 80018fa: 4a12 ldr r2, [pc, #72] @ (8001944 ) 80018fc: 4293 cmp r3, r2 80018fe: d102 bne.n 8001906 { channel = 5; 8001900: 2305 movs r3, #5 8001902: 60fb str r3, [r7, #12] 8001904: e00f b.n 8001926 } else if (Instance == DFSDM1_Channel6) 8001906: 687b ldr r3, [r7, #4] 8001908: 4a0f ldr r2, [pc, #60] @ (8001948 ) 800190a: 4293 cmp r3, r2 800190c: d102 bne.n 8001914 { channel = 6; 800190e: 2306 movs r3, #6 8001910: 60fb str r3, [r7, #12] 8001912: e008 b.n 8001926 } else if (Instance == DFSDM1_Channel7) 8001914: 687b ldr r3, [r7, #4] 8001916: 4a0d ldr r2, [pc, #52] @ (800194c ) 8001918: 4293 cmp r3, r2 800191a: d102 bne.n 8001922 { channel = 7; 800191c: 2307 movs r3, #7 800191e: 60fb str r3, [r7, #12] 8001920: e001 b.n 8001926 } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ else /* DFSDM1_Channel3 */ { channel = 3; 8001922: 2303 movs r3, #3 8001924: 60fb str r3, [r7, #12] } return channel; 8001926: 68fb ldr r3, [r7, #12] } 8001928: 4618 mov r0, r3 800192a: 3714 adds r7, #20 800192c: 46bd mov sp, r7 800192e: f85d 7b04 ldr.w r7, [sp], #4 8001932: 4770 bx lr 8001934: 40016000 .word 0x40016000 8001938: 40016020 .word 0x40016020 800193c: 40016040 .word 0x40016040 8001940: 40016080 .word 0x40016080 8001944: 400160a0 .word 0x400160a0 8001948: 400160c0 .word 0x400160c0 800194c: 400160e0 .word 0x400160e0 08001950 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001950: b480 push {r7} 8001952: b087 sub sp, #28 8001954: af00 add r7, sp, #0 8001956: 6078 str r0, [r7, #4] 8001958: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800195a: 2300 movs r3, #0 800195c: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800195e: e17f b.n 8001c60 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8001960: 683b ldr r3, [r7, #0] 8001962: 681a ldr r2, [r3, #0] 8001964: 2101 movs r1, #1 8001966: 697b ldr r3, [r7, #20] 8001968: fa01 f303 lsl.w r3, r1, r3 800196c: 4013 ands r3, r2 800196e: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8001970: 68fb ldr r3, [r7, #12] 8001972: 2b00 cmp r3, #0 8001974: f000 8171 beq.w 8001c5a { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8001978: 683b ldr r3, [r7, #0] 800197a: 685b ldr r3, [r3, #4] 800197c: f003 0303 and.w r3, r3, #3 8001980: 2b01 cmp r3, #1 8001982: d005 beq.n 8001990 8001984: 683b ldr r3, [r7, #0] 8001986: 685b ldr r3, [r3, #4] 8001988: f003 0303 and.w r3, r3, #3 800198c: 2b02 cmp r3, #2 800198e: d130 bne.n 80019f2 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001990: 687b ldr r3, [r7, #4] 8001992: 689b ldr r3, [r3, #8] 8001994: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); 8001996: 697b ldr r3, [r7, #20] 8001998: 005b lsls r3, r3, #1 800199a: 2203 movs r2, #3 800199c: fa02 f303 lsl.w r3, r2, r3 80019a0: 43db mvns r3, r3 80019a2: 693a ldr r2, [r7, #16] 80019a4: 4013 ands r3, r2 80019a6: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 80019a8: 683b ldr r3, [r7, #0] 80019aa: 68da ldr r2, [r3, #12] 80019ac: 697b ldr r3, [r7, #20] 80019ae: 005b lsls r3, r3, #1 80019b0: fa02 f303 lsl.w r3, r2, r3 80019b4: 693a ldr r2, [r7, #16] 80019b6: 4313 orrs r3, r2 80019b8: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 80019ba: 687b ldr r3, [r7, #4] 80019bc: 693a ldr r2, [r7, #16] 80019be: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80019c0: 687b ldr r3, [r7, #4] 80019c2: 685b ldr r3, [r3, #4] 80019c4: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 80019c6: 2201 movs r2, #1 80019c8: 697b ldr r3, [r7, #20] 80019ca: fa02 f303 lsl.w r3, r2, r3 80019ce: 43db mvns r3, r3 80019d0: 693a ldr r2, [r7, #16] 80019d2: 4013 ands r3, r2 80019d4: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80019d6: 683b ldr r3, [r7, #0] 80019d8: 685b ldr r3, [r3, #4] 80019da: 091b lsrs r3, r3, #4 80019dc: f003 0201 and.w r2, r3, #1 80019e0: 697b ldr r3, [r7, #20] 80019e2: fa02 f303 lsl.w r3, r2, r3 80019e6: 693a ldr r2, [r7, #16] 80019e8: 4313 orrs r3, r2 80019ea: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 80019ec: 687b ldr r3, [r7, #4] 80019ee: 693a ldr r2, [r7, #16] 80019f0: 605a str r2, [r3, #4] } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) /* In case of Analog mode, check if ADC control mode is selected */ if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG) 80019f2: 683b ldr r3, [r7, #0] 80019f4: 685b ldr r3, [r3, #4] 80019f6: f003 0303 and.w r3, r3, #3 80019fa: 2b03 cmp r3, #3 80019fc: d118 bne.n 8001a30 { /* Configure the IO Output Type */ temp = GPIOx->ASCR; 80019fe: 687b ldr r3, [r7, #4] 8001a00: 6adb ldr r3, [r3, #44] @ 0x2c 8001a02: 613b str r3, [r7, #16] temp &= ~(GPIO_ASCR_ASC0 << position) ; 8001a04: 2201 movs r2, #1 8001a06: 697b ldr r3, [r7, #20] 8001a08: fa02 f303 lsl.w r3, r2, r3 8001a0c: 43db mvns r3, r3 8001a0e: 693a ldr r2, [r7, #16] 8001a10: 4013 ands r3, r2 8001a12: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position); 8001a14: 683b ldr r3, [r7, #0] 8001a16: 685b ldr r3, [r3, #4] 8001a18: 08db lsrs r3, r3, #3 8001a1a: f003 0201 and.w r2, r3, #1 8001a1e: 697b ldr r3, [r7, #20] 8001a20: fa02 f303 lsl.w r3, r2, r3 8001a24: 693a ldr r2, [r7, #16] 8001a26: 4313 orrs r3, r2 8001a28: 613b str r3, [r7, #16] GPIOx->ASCR = temp; 8001a2a: 687b ldr r3, [r7, #4] 8001a2c: 693a ldr r2, [r7, #16] 8001a2e: 62da str r2, [r3, #44] @ 0x2c } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ /* Activate the Pull-up or Pull down resistor for the current IO */ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001a30: 683b ldr r3, [r7, #0] 8001a32: 685b ldr r3, [r3, #4] 8001a34: f003 0303 and.w r3, r3, #3 8001a38: 2b03 cmp r3, #3 8001a3a: d017 beq.n 8001a6c { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); temp = GPIOx->PUPDR; 8001a3c: 687b ldr r3, [r7, #4] 8001a3e: 68db ldr r3, [r3, #12] 8001a40: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8001a42: 697b ldr r3, [r7, #20] 8001a44: 005b lsls r3, r3, #1 8001a46: 2203 movs r2, #3 8001a48: fa02 f303 lsl.w r3, r2, r3 8001a4c: 43db mvns r3, r3 8001a4e: 693a ldr r2, [r7, #16] 8001a50: 4013 ands r3, r2 8001a52: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001a54: 683b ldr r3, [r7, #0] 8001a56: 689a ldr r2, [r3, #8] 8001a58: 697b ldr r3, [r7, #20] 8001a5a: 005b lsls r3, r3, #1 8001a5c: fa02 f303 lsl.w r3, r2, r3 8001a60: 693a ldr r2, [r7, #16] 8001a62: 4313 orrs r3, r2 8001a64: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8001a66: 687b ldr r3, [r7, #4] 8001a68: 693a ldr r2, [r7, #16] 8001a6a: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001a6c: 683b ldr r3, [r7, #0] 8001a6e: 685b ldr r3, [r3, #4] 8001a70: f003 0303 and.w r3, r3, #3 8001a74: 2b02 cmp r3, #2 8001a76: d123 bne.n 8001ac0 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8001a78: 697b ldr r3, [r7, #20] 8001a7a: 08da lsrs r2, r3, #3 8001a7c: 687b ldr r3, [r7, #4] 8001a7e: 3208 adds r2, #8 8001a80: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001a84: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8001a86: 697b ldr r3, [r7, #20] 8001a88: f003 0307 and.w r3, r3, #7 8001a8c: 009b lsls r3, r3, #2 8001a8e: 220f movs r2, #15 8001a90: fa02 f303 lsl.w r3, r2, r3 8001a94: 43db mvns r3, r3 8001a96: 693a ldr r2, [r7, #16] 8001a98: 4013 ands r3, r2 8001a9a: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8001a9c: 683b ldr r3, [r7, #0] 8001a9e: 691a ldr r2, [r3, #16] 8001aa0: 697b ldr r3, [r7, #20] 8001aa2: f003 0307 and.w r3, r3, #7 8001aa6: 009b lsls r3, r3, #2 8001aa8: fa02 f303 lsl.w r3, r2, r3 8001aac: 693a ldr r2, [r7, #16] 8001aae: 4313 orrs r3, r2 8001ab0: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8001ab2: 697b ldr r3, [r7, #20] 8001ab4: 08da lsrs r2, r3, #3 8001ab6: 687b ldr r3, [r7, #4] 8001ab8: 3208 adds r2, #8 8001aba: 6939 ldr r1, [r7, #16] 8001abc: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001ac0: 687b ldr r3, [r7, #4] 8001ac2: 681b ldr r3, [r3, #0] 8001ac4: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); 8001ac6: 697b ldr r3, [r7, #20] 8001ac8: 005b lsls r3, r3, #1 8001aca: 2203 movs r2, #3 8001acc: fa02 f303 lsl.w r3, r2, r3 8001ad0: 43db mvns r3, r3 8001ad2: 693a ldr r2, [r7, #16] 8001ad4: 4013 ands r3, r2 8001ad6: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8001ad8: 683b ldr r3, [r7, #0] 8001ada: 685b ldr r3, [r3, #4] 8001adc: f003 0203 and.w r2, r3, #3 8001ae0: 697b ldr r3, [r7, #20] 8001ae2: 005b lsls r3, r3, #1 8001ae4: fa02 f303 lsl.w r3, r2, r3 8001ae8: 693a ldr r2, [r7, #16] 8001aea: 4313 orrs r3, r2 8001aec: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8001aee: 687b ldr r3, [r7, #4] 8001af0: 693a ldr r2, [r7, #16] 8001af2: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8001af4: 683b ldr r3, [r7, #0] 8001af6: 685b ldr r3, [r3, #4] 8001af8: f403 3340 and.w r3, r3, #196608 @ 0x30000 8001afc: 2b00 cmp r3, #0 8001afe: f000 80ac beq.w 8001c5a { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001b02: 4b5f ldr r3, [pc, #380] @ (8001c80 ) 8001b04: 6e1b ldr r3, [r3, #96] @ 0x60 8001b06: 4a5e ldr r2, [pc, #376] @ (8001c80 ) 8001b08: f043 0301 orr.w r3, r3, #1 8001b0c: 6613 str r3, [r2, #96] @ 0x60 8001b0e: 4b5c ldr r3, [pc, #368] @ (8001c80 ) 8001b10: 6e1b ldr r3, [r3, #96] @ 0x60 8001b12: f003 0301 and.w r3, r3, #1 8001b16: 60bb str r3, [r7, #8] 8001b18: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 8001b1a: 4a5a ldr r2, [pc, #360] @ (8001c84 ) 8001b1c: 697b ldr r3, [r7, #20] 8001b1e: 089b lsrs r3, r3, #2 8001b20: 3302 adds r3, #2 8001b22: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001b26: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 8001b28: 697b ldr r3, [r7, #20] 8001b2a: f003 0303 and.w r3, r3, #3 8001b2e: 009b lsls r3, r3, #2 8001b30: 220f movs r2, #15 8001b32: fa02 f303 lsl.w r3, r2, r3 8001b36: 43db mvns r3, r3 8001b38: 693a ldr r2, [r7, #16] 8001b3a: 4013 ands r3, r2 8001b3c: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 8001b3e: 687b ldr r3, [r7, #4] 8001b40: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 8001b44: d025 beq.n 8001b92 8001b46: 687b ldr r3, [r7, #4] 8001b48: 4a4f ldr r2, [pc, #316] @ (8001c88 ) 8001b4a: 4293 cmp r3, r2 8001b4c: d01f beq.n 8001b8e 8001b4e: 687b ldr r3, [r7, #4] 8001b50: 4a4e ldr r2, [pc, #312] @ (8001c8c ) 8001b52: 4293 cmp r3, r2 8001b54: d019 beq.n 8001b8a 8001b56: 687b ldr r3, [r7, #4] 8001b58: 4a4d ldr r2, [pc, #308] @ (8001c90 ) 8001b5a: 4293 cmp r3, r2 8001b5c: d013 beq.n 8001b86 8001b5e: 687b ldr r3, [r7, #4] 8001b60: 4a4c ldr r2, [pc, #304] @ (8001c94 ) 8001b62: 4293 cmp r3, r2 8001b64: d00d beq.n 8001b82 8001b66: 687b ldr r3, [r7, #4] 8001b68: 4a4b ldr r2, [pc, #300] @ (8001c98 ) 8001b6a: 4293 cmp r3, r2 8001b6c: d007 beq.n 8001b7e 8001b6e: 687b ldr r3, [r7, #4] 8001b70: 4a4a ldr r2, [pc, #296] @ (8001c9c ) 8001b72: 4293 cmp r3, r2 8001b74: d101 bne.n 8001b7a 8001b76: 2306 movs r3, #6 8001b78: e00c b.n 8001b94 8001b7a: 2307 movs r3, #7 8001b7c: e00a b.n 8001b94 8001b7e: 2305 movs r3, #5 8001b80: e008 b.n 8001b94 8001b82: 2304 movs r3, #4 8001b84: e006 b.n 8001b94 8001b86: 2303 movs r3, #3 8001b88: e004 b.n 8001b94 8001b8a: 2302 movs r3, #2 8001b8c: e002 b.n 8001b94 8001b8e: 2301 movs r3, #1 8001b90: e000 b.n 8001b94 8001b92: 2300 movs r3, #0 8001b94: 697a ldr r2, [r7, #20] 8001b96: f002 0203 and.w r2, r2, #3 8001b9a: 0092 lsls r2, r2, #2 8001b9c: 4093 lsls r3, r2 8001b9e: 693a ldr r2, [r7, #16] 8001ba0: 4313 orrs r3, r2 8001ba2: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8001ba4: 4937 ldr r1, [pc, #220] @ (8001c84 ) 8001ba6: 697b ldr r3, [r7, #20] 8001ba8: 089b lsrs r3, r3, #2 8001baa: 3302 adds r3, #2 8001bac: 693a ldr r2, [r7, #16] 8001bae: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8001bb2: 4b3b ldr r3, [pc, #236] @ (8001ca0 ) 8001bb4: 689b ldr r3, [r3, #8] 8001bb6: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001bb8: 68fb ldr r3, [r7, #12] 8001bba: 43db mvns r3, r3 8001bbc: 693a ldr r2, [r7, #16] 8001bbe: 4013 ands r3, r2 8001bc0: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8001bc2: 683b ldr r3, [r7, #0] 8001bc4: 685b ldr r3, [r3, #4] 8001bc6: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001bca: 2b00 cmp r3, #0 8001bcc: d003 beq.n 8001bd6 { temp |= iocurrent; 8001bce: 693a ldr r2, [r7, #16] 8001bd0: 68fb ldr r3, [r7, #12] 8001bd2: 4313 orrs r3, r2 8001bd4: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8001bd6: 4a32 ldr r2, [pc, #200] @ (8001ca0 ) 8001bd8: 693b ldr r3, [r7, #16] 8001bda: 6093 str r3, [r2, #8] temp = EXTI->FTSR1; 8001bdc: 4b30 ldr r3, [pc, #192] @ (8001ca0 ) 8001bde: 68db ldr r3, [r3, #12] 8001be0: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001be2: 68fb ldr r3, [r7, #12] 8001be4: 43db mvns r3, r3 8001be6: 693a ldr r2, [r7, #16] 8001be8: 4013 ands r3, r2 8001bea: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8001bec: 683b ldr r3, [r7, #0] 8001bee: 685b ldr r3, [r3, #4] 8001bf0: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8001bf4: 2b00 cmp r3, #0 8001bf6: d003 beq.n 8001c00 { temp |= iocurrent; 8001bf8: 693a ldr r2, [r7, #16] 8001bfa: 68fb ldr r3, [r7, #12] 8001bfc: 4313 orrs r3, r2 8001bfe: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8001c00: 4a27 ldr r2, [pc, #156] @ (8001ca0 ) 8001c02: 693b ldr r3, [r7, #16] 8001c04: 60d3 str r3, [r2, #12] /* Clear EXTI line configuration */ temp = EXTI->EMR1; 8001c06: 4b26 ldr r3, [pc, #152] @ (8001ca0 ) 8001c08: 685b ldr r3, [r3, #4] 8001c0a: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001c0c: 68fb ldr r3, [r7, #12] 8001c0e: 43db mvns r3, r3 8001c10: 693a ldr r2, [r7, #16] 8001c12: 4013 ands r3, r2 8001c14: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8001c16: 683b ldr r3, [r7, #0] 8001c18: 685b ldr r3, [r3, #4] 8001c1a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001c1e: 2b00 cmp r3, #0 8001c20: d003 beq.n 8001c2a { temp |= iocurrent; 8001c22: 693a ldr r2, [r7, #16] 8001c24: 68fb ldr r3, [r7, #12] 8001c26: 4313 orrs r3, r2 8001c28: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8001c2a: 4a1d ldr r2, [pc, #116] @ (8001ca0 ) 8001c2c: 693b ldr r3, [r7, #16] 8001c2e: 6053 str r3, [r2, #4] temp = EXTI->IMR1; 8001c30: 4b1b ldr r3, [pc, #108] @ (8001ca0 ) 8001c32: 681b ldr r3, [r3, #0] 8001c34: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001c36: 68fb ldr r3, [r7, #12] 8001c38: 43db mvns r3, r3 8001c3a: 693a ldr r2, [r7, #16] 8001c3c: 4013 ands r3, r2 8001c3e: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8001c40: 683b ldr r3, [r7, #0] 8001c42: 685b ldr r3, [r3, #4] 8001c44: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001c48: 2b00 cmp r3, #0 8001c4a: d003 beq.n 8001c54 { temp |= iocurrent; 8001c4c: 693a ldr r2, [r7, #16] 8001c4e: 68fb ldr r3, [r7, #12] 8001c50: 4313 orrs r3, r2 8001c52: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 8001c54: 4a12 ldr r2, [pc, #72] @ (8001ca0 ) 8001c56: 693b ldr r3, [r7, #16] 8001c58: 6013 str r3, [r2, #0] } } position++; 8001c5a: 697b ldr r3, [r7, #20] 8001c5c: 3301 adds r3, #1 8001c5e: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8001c60: 683b ldr r3, [r7, #0] 8001c62: 681a ldr r2, [r3, #0] 8001c64: 697b ldr r3, [r7, #20] 8001c66: fa22 f303 lsr.w r3, r2, r3 8001c6a: 2b00 cmp r3, #0 8001c6c: f47f ae78 bne.w 8001960 } } 8001c70: bf00 nop 8001c72: bf00 nop 8001c74: 371c adds r7, #28 8001c76: 46bd mov sp, r7 8001c78: f85d 7b04 ldr.w r7, [sp], #4 8001c7c: 4770 bx lr 8001c7e: bf00 nop 8001c80: 40021000 .word 0x40021000 8001c84: 40010000 .word 0x40010000 8001c88: 48000400 .word 0x48000400 8001c8c: 48000800 .word 0x48000800 8001c90: 48000c00 .word 0x48000c00 8001c94: 48001000 .word 0x48001000 8001c98: 48001400 .word 0x48001400 8001c9c: 48001800 .word 0x48001800 8001ca0: 40010400 .word 0x40010400 08001ca4 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001ca4: b480 push {r7} 8001ca6: b083 sub sp, #12 8001ca8: af00 add r7, sp, #0 8001caa: 6078 str r0, [r7, #4] 8001cac: 460b mov r3, r1 8001cae: 807b strh r3, [r7, #2] 8001cb0: 4613 mov r3, r2 8001cb2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8001cb4: 787b ldrb r3, [r7, #1] 8001cb6: 2b00 cmp r3, #0 8001cb8: d003 beq.n 8001cc2 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8001cba: 887a ldrh r2, [r7, #2] 8001cbc: 687b ldr r3, [r7, #4] 8001cbe: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8001cc0: e002 b.n 8001cc8 GPIOx->BRR = (uint32_t)GPIO_Pin; 8001cc2: 887a ldrh r2, [r7, #2] 8001cc4: 687b ldr r3, [r7, #4] 8001cc6: 629a str r2, [r3, #40] @ 0x28 } 8001cc8: bf00 nop 8001cca: 370c adds r7, #12 8001ccc: 46bd mov sp, r7 8001cce: f85d 7b04 ldr.w r7, [sp], #4 8001cd2: 4770 bx lr 08001cd4 : * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin specifies the pin to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8001cd4: b480 push {r7} 8001cd6: b085 sub sp, #20 8001cd8: af00 add r7, sp, #0 8001cda: 6078 str r0, [r7, #4] 8001cdc: 460b mov r3, r1 8001cde: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 8001ce0: 687b ldr r3, [r7, #4] 8001ce2: 695b ldr r3, [r3, #20] 8001ce4: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 8001ce6: 887a ldrh r2, [r7, #2] 8001ce8: 68fb ldr r3, [r7, #12] 8001cea: 4013 ands r3, r2 8001cec: 041a lsls r2, r3, #16 8001cee: 68fb ldr r3, [r7, #12] 8001cf0: 43d9 mvns r1, r3 8001cf2: 887b ldrh r3, [r7, #2] 8001cf4: 400b ands r3, r1 8001cf6: 431a orrs r2, r3 8001cf8: 687b ldr r3, [r7, #4] 8001cfa: 619a str r2, [r3, #24] } 8001cfc: bf00 nop 8001cfe: 3714 adds r7, #20 8001d00: 46bd mov sp, r7 8001d02: f85d 7b04 ldr.w r7, [sp], #4 8001d06: 4770 bx lr 08001d08 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8001d08: b580 push {r7, lr} 8001d0a: b082 sub sp, #8 8001d0c: af00 add r7, sp, #0 8001d0e: 4603 mov r3, r0 8001d10: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 8001d12: 4b08 ldr r3, [pc, #32] @ (8001d34 ) 8001d14: 695a ldr r2, [r3, #20] 8001d16: 88fb ldrh r3, [r7, #6] 8001d18: 4013 ands r3, r2 8001d1a: 2b00 cmp r3, #0 8001d1c: d006 beq.n 8001d2c { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 8001d1e: 4a05 ldr r2, [pc, #20] @ (8001d34 ) 8001d20: 88fb ldrh r3, [r7, #6] 8001d22: 6153 str r3, [r2, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 8001d24: 88fb ldrh r3, [r7, #6] 8001d26: 4618 mov r0, r3 8001d28: f000 f806 bl 8001d38 } } 8001d2c: bf00 nop 8001d2e: 3708 adds r7, #8 8001d30: 46bd mov sp, r7 8001d32: bd80 pop {r7, pc} 8001d34: 40010400 .word 0x40010400 08001d38 : * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8001d38: b480 push {r7} 8001d3a: b083 sub sp, #12 8001d3c: af00 add r7, sp, #0 8001d3e: 4603 mov r3, r0 8001d40: 80fb strh r3, [r7, #6] UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ } 8001d42: bf00 nop 8001d44: 370c adds r7, #12 8001d46: 46bd mov sp, r7 8001d48: f85d 7b04 ldr.w r7, [sp], #4 8001d4c: 4770 bx lr 08001d4e : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8001d4e: b580 push {r7, lr} 8001d50: b082 sub sp, #8 8001d52: af00 add r7, sp, #0 8001d54: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 8001d56: 687b ldr r3, [r7, #4] 8001d58: 2b00 cmp r3, #0 8001d5a: d101 bne.n 8001d60 { return HAL_ERROR; 8001d5c: 2301 movs r3, #1 8001d5e: e08d b.n 8001e7c assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8001d60: 687b ldr r3, [r7, #4] 8001d62: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8001d66: b2db uxtb r3, r3 8001d68: 2b00 cmp r3, #0 8001d6a: d106 bne.n 8001d7a { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8001d6c: 687b ldr r3, [r7, #4] 8001d6e: 2200 movs r2, #0 8001d70: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 8001d74: 6878 ldr r0, [r7, #4] 8001d76: f7ff f883 bl 8000e80 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8001d7a: 687b ldr r3, [r7, #4] 8001d7c: 2224 movs r2, #36 @ 0x24 8001d7e: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001d82: 687b ldr r3, [r7, #4] 8001d84: 681b ldr r3, [r3, #0] 8001d86: 681a ldr r2, [r3, #0] 8001d88: 687b ldr r3, [r7, #4] 8001d8a: 681b ldr r3, [r3, #0] 8001d8c: f022 0201 bic.w r2, r2, #1 8001d90: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 8001d92: 687b ldr r3, [r7, #4] 8001d94: 685a ldr r2, [r3, #4] 8001d96: 687b ldr r3, [r7, #4] 8001d98: 681b ldr r3, [r3, #0] 8001d9a: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000 8001d9e: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 8001da0: 687b ldr r3, [r7, #4] 8001da2: 681b ldr r3, [r3, #0] 8001da4: 689a ldr r2, [r3, #8] 8001da6: 687b ldr r3, [r7, #4] 8001da8: 681b ldr r3, [r3, #0] 8001daa: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8001dae: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 8001db0: 687b ldr r3, [r7, #4] 8001db2: 68db ldr r3, [r3, #12] 8001db4: 2b01 cmp r3, #1 8001db6: d107 bne.n 8001dc8 { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 8001db8: 687b ldr r3, [r7, #4] 8001dba: 689a ldr r2, [r3, #8] 8001dbc: 687b ldr r3, [r7, #4] 8001dbe: 681b ldr r3, [r3, #0] 8001dc0: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8001dc4: 609a str r2, [r3, #8] 8001dc6: e006 b.n 8001dd6 } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 8001dc8: 687b ldr r3, [r7, #4] 8001dca: 689a ldr r2, [r3, #8] 8001dcc: 687b ldr r3, [r7, #4] 8001dce: 681b ldr r3, [r3, #0] 8001dd0: f442 4204 orr.w r2, r2, #33792 @ 0x8400 8001dd4: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8001dd6: 687b ldr r3, [r7, #4] 8001dd8: 68db ldr r3, [r3, #12] 8001dda: 2b02 cmp r3, #2 8001ddc: d108 bne.n 8001df0 { SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8001dde: 687b ldr r3, [r7, #4] 8001de0: 681b ldr r3, [r3, #0] 8001de2: 685a ldr r2, [r3, #4] 8001de4: 687b ldr r3, [r7, #4] 8001de6: 681b ldr r3, [r3, #0] 8001de8: f442 6200 orr.w r2, r2, #2048 @ 0x800 8001dec: 605a str r2, [r3, #4] 8001dee: e007 b.n 8001e00 } else { /* Clear the I2C ADD10 bit */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8001df0: 687b ldr r3, [r7, #4] 8001df2: 681b ldr r3, [r3, #0] 8001df4: 685a ldr r2, [r3, #4] 8001df6: 687b ldr r3, [r7, #4] 8001df8: 681b ldr r3, [r3, #0] 8001dfa: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001dfe: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 8001e00: 687b ldr r3, [r7, #4] 8001e02: 681b ldr r3, [r3, #0] 8001e04: 685b ldr r3, [r3, #4] 8001e06: 687a ldr r2, [r7, #4] 8001e08: 6812 ldr r2, [r2, #0] 8001e0a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8001e0e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8001e12: 6053 str r3, [r2, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8001e14: 687b ldr r3, [r7, #4] 8001e16: 681b ldr r3, [r3, #0] 8001e18: 68da ldr r2, [r3, #12] 8001e1a: 687b ldr r3, [r7, #4] 8001e1c: 681b ldr r3, [r3, #0] 8001e1e: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8001e22: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8001e24: 687b ldr r3, [r7, #4] 8001e26: 691a ldr r2, [r3, #16] 8001e28: 687b ldr r3, [r7, #4] 8001e2a: 695b ldr r3, [r3, #20] 8001e2c: ea42 0103 orr.w r1, r2, r3 (hi2c->Init.OwnAddress2Masks << 8)); 8001e30: 687b ldr r3, [r7, #4] 8001e32: 699b ldr r3, [r3, #24] 8001e34: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8001e36: 687b ldr r3, [r7, #4] 8001e38: 681b ldr r3, [r3, #0] 8001e3a: 430a orrs r2, r1 8001e3c: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 8001e3e: 687b ldr r3, [r7, #4] 8001e40: 69d9 ldr r1, [r3, #28] 8001e42: 687b ldr r3, [r7, #4] 8001e44: 6a1a ldr r2, [r3, #32] 8001e46: 687b ldr r3, [r7, #4] 8001e48: 681b ldr r3, [r3, #0] 8001e4a: 430a orrs r2, r1 8001e4c: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8001e4e: 687b ldr r3, [r7, #4] 8001e50: 681b ldr r3, [r3, #0] 8001e52: 681a ldr r2, [r3, #0] 8001e54: 687b ldr r3, [r7, #4] 8001e56: 681b ldr r3, [r3, #0] 8001e58: f042 0201 orr.w r2, r2, #1 8001e5c: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8001e5e: 687b ldr r3, [r7, #4] 8001e60: 2200 movs r2, #0 8001e62: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 8001e64: 687b ldr r3, [r7, #4] 8001e66: 2220 movs r2, #32 8001e68: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: 2200 movs r2, #0 8001e70: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8001e72: 687b ldr r3, [r7, #4] 8001e74: 2200 movs r2, #0 8001e76: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_OK; 8001e7a: 2300 movs r3, #0 } 8001e7c: 4618 mov r0, r3 8001e7e: 3708 adds r7, #8 8001e80: 46bd mov sp, r7 8001e82: bd80 pop {r7, pc} 08001e84 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8001e84: b480 push {r7} 8001e86: b083 sub sp, #12 8001e88: af00 add r7, sp, #0 8001e8a: 6078 str r0, [r7, #4] 8001e8c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8001e8e: 687b ldr r3, [r7, #4] 8001e90: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8001e94: b2db uxtb r3, r3 8001e96: 2b20 cmp r3, #32 8001e98: d138 bne.n 8001f0c { /* Process Locked */ __HAL_LOCK(hi2c); 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8001ea0: 2b01 cmp r3, #1 8001ea2: d101 bne.n 8001ea8 8001ea4: 2302 movs r3, #2 8001ea6: e032 b.n 8001f0e 8001ea8: 687b ldr r3, [r7, #4] 8001eaa: 2201 movs r2, #1 8001eac: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 8001eb0: 687b ldr r3, [r7, #4] 8001eb2: 2224 movs r2, #36 @ 0x24 8001eb4: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001eb8: 687b ldr r3, [r7, #4] 8001eba: 681b ldr r3, [r3, #0] 8001ebc: 681a ldr r2, [r3, #0] 8001ebe: 687b ldr r3, [r7, #4] 8001ec0: 681b ldr r3, [r3, #0] 8001ec2: f022 0201 bic.w r2, r2, #1 8001ec6: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 8001ec8: 687b ldr r3, [r7, #4] 8001eca: 681b ldr r3, [r3, #0] 8001ecc: 681a ldr r2, [r3, #0] 8001ece: 687b ldr r3, [r7, #4] 8001ed0: 681b ldr r3, [r3, #0] 8001ed2: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8001ed6: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 8001ed8: 687b ldr r3, [r7, #4] 8001eda: 681b ldr r3, [r3, #0] 8001edc: 6819 ldr r1, [r3, #0] 8001ede: 687b ldr r3, [r7, #4] 8001ee0: 681b ldr r3, [r3, #0] 8001ee2: 683a ldr r2, [r7, #0] 8001ee4: 430a orrs r2, r1 8001ee6: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8001ee8: 687b ldr r3, [r7, #4] 8001eea: 681b ldr r3, [r3, #0] 8001eec: 681a ldr r2, [r3, #0] 8001eee: 687b ldr r3, [r7, #4] 8001ef0: 681b ldr r3, [r3, #0] 8001ef2: f042 0201 orr.w r2, r2, #1 8001ef6: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8001ef8: 687b ldr r3, [r7, #4] 8001efa: 2220 movs r2, #32 8001efc: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8001f00: 687b ldr r3, [r7, #4] 8001f02: 2200 movs r2, #0 8001f04: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8001f08: 2300 movs r3, #0 8001f0a: e000 b.n 8001f0e } else { return HAL_BUSY; 8001f0c: 2302 movs r3, #2 } } 8001f0e: 4618 mov r0, r3 8001f10: 370c adds r7, #12 8001f12: 46bd mov sp, r7 8001f14: f85d 7b04 ldr.w r7, [sp], #4 8001f18: 4770 bx lr 08001f1a : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8001f1a: b480 push {r7} 8001f1c: b085 sub sp, #20 8001f1e: af00 add r7, sp, #0 8001f20: 6078 str r0, [r7, #4] 8001f22: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8001f24: 687b ldr r3, [r7, #4] 8001f26: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8001f2a: b2db uxtb r3, r3 8001f2c: 2b20 cmp r3, #32 8001f2e: d139 bne.n 8001fa4 { /* Process Locked */ __HAL_LOCK(hi2c); 8001f30: 687b ldr r3, [r7, #4] 8001f32: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8001f36: 2b01 cmp r3, #1 8001f38: d101 bne.n 8001f3e 8001f3a: 2302 movs r3, #2 8001f3c: e033 b.n 8001fa6 8001f3e: 687b ldr r3, [r7, #4] 8001f40: 2201 movs r2, #1 8001f42: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 8001f46: 687b ldr r3, [r7, #4] 8001f48: 2224 movs r2, #36 @ 0x24 8001f4a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001f4e: 687b ldr r3, [r7, #4] 8001f50: 681b ldr r3, [r3, #0] 8001f52: 681a ldr r2, [r3, #0] 8001f54: 687b ldr r3, [r7, #4] 8001f56: 681b ldr r3, [r3, #0] 8001f58: f022 0201 bic.w r2, r2, #1 8001f5c: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 8001f5e: 687b ldr r3, [r7, #4] 8001f60: 681b ldr r3, [r3, #0] 8001f62: 681b ldr r3, [r3, #0] 8001f64: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 8001f66: 68fb ldr r3, [r7, #12] 8001f68: f423 6370 bic.w r3, r3, #3840 @ 0xf00 8001f6c: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 8001f6e: 683b ldr r3, [r7, #0] 8001f70: 021b lsls r3, r3, #8 8001f72: 68fa ldr r2, [r7, #12] 8001f74: 4313 orrs r3, r2 8001f76: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 8001f78: 687b ldr r3, [r7, #4] 8001f7a: 681b ldr r3, [r3, #0] 8001f7c: 68fa ldr r2, [r7, #12] 8001f7e: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8001f80: 687b ldr r3, [r7, #4] 8001f82: 681b ldr r3, [r3, #0] 8001f84: 681a ldr r2, [r3, #0] 8001f86: 687b ldr r3, [r7, #4] 8001f88: 681b ldr r3, [r3, #0] 8001f8a: f042 0201 orr.w r2, r2, #1 8001f8e: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8001f90: 687b ldr r3, [r7, #4] 8001f92: 2220 movs r2, #32 8001f94: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8001f98: 687b ldr r3, [r7, #4] 8001f9a: 2200 movs r2, #0 8001f9c: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8001fa0: 2300 movs r3, #0 8001fa2: e000 b.n 8001fa6 } else { return HAL_BUSY; 8001fa4: 2302 movs r3, #2 } } 8001fa6: 4618 mov r0, r3 8001fa8: 3714 adds r7, #20 8001faa: 46bd mov sp, r7 8001fac: f85d 7b04 ldr.w r7, [sp], #4 8001fb0: 4770 bx lr 08001fb2 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8001fb2: b580 push {r7, lr} 8001fb4: b086 sub sp, #24 8001fb6: af02 add r7, sp, #8 8001fb8: 6078 str r0, [r7, #4] uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8001fba: 687b ldr r3, [r7, #4] 8001fbc: 2b00 cmp r3, #0 8001fbe: d101 bne.n 8001fc4 { return HAL_ERROR; 8001fc0: 2301 movs r3, #1 8001fc2: e101 b.n 80021c8 } /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); if (hpcd->State == HAL_PCD_STATE_RESET) 8001fc4: 687b ldr r3, [r7, #4] 8001fc6: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8001fca: b2db uxtb r3, r3 8001fcc: 2b00 cmp r3, #0 8001fce: d106 bne.n 8001fde { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8001fd0: 687b ldr r3, [r7, #4] 8001fd2: 2200 movs r2, #0 8001fd4: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8001fd8: 6878 ldr r0, [r7, #4] 8001fda: f7ff f8db bl 8001194 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8001fde: 687b ldr r3, [r7, #4] 8001fe0: 2203 movs r2, #3 8001fe2: f883 2495 strb.w r2, [r3, #1173] @ 0x495 /* Disable DMA mode for FS instance */ hpcd->Init.dma_enable = 0U; 8001fe6: 687b ldr r3, [r7, #4] 8001fe8: 2200 movs r2, #0 8001fea: 719a strb r2, [r3, #6] /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8001fec: 687b ldr r3, [r7, #4] 8001fee: 681b ldr r3, [r3, #0] 8001ff0: 4618 mov r0, r3 8001ff2: f002 fe05 bl 8004c00 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8001ff6: 687b ldr r3, [r7, #4] 8001ff8: 6818 ldr r0, [r3, #0] 8001ffa: 687b ldr r3, [r7, #4] 8001ffc: 7c1a ldrb r2, [r3, #16] 8001ffe: f88d 2000 strb.w r2, [sp] 8002002: 3304 adds r3, #4 8002004: cb0e ldmia r3, {r1, r2, r3} 8002006: f002 fdce bl 8004ba6 800200a: 4603 mov r3, r0 800200c: 2b00 cmp r3, #0 800200e: d005 beq.n 800201c { hpcd->State = HAL_PCD_STATE_ERROR; 8002010: 687b ldr r3, [r7, #4] 8002012: 2202 movs r2, #2 8002014: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002018: 2301 movs r3, #1 800201a: e0d5 b.n 80021c8 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 800201c: 687b ldr r3, [r7, #4] 800201e: 681b ldr r3, [r3, #0] 8002020: 2100 movs r1, #0 8002022: 4618 mov r0, r3 8002024: f002 fdfd bl 8004c22 8002028: 4603 mov r3, r0 800202a: 2b00 cmp r3, #0 800202c: d005 beq.n 800203a { hpcd->State = HAL_PCD_STATE_ERROR; 800202e: 687b ldr r3, [r7, #4] 8002030: 2202 movs r2, #2 8002032: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002036: 2301 movs r3, #1 8002038: e0c6 b.n 80021c8 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800203a: 2300 movs r3, #0 800203c: 73fb strb r3, [r7, #15] 800203e: e04a b.n 80020d6 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8002040: 7bfa ldrb r2, [r7, #15] 8002042: 6879 ldr r1, [r7, #4] 8002044: 4613 mov r3, r2 8002046: 00db lsls r3, r3, #3 8002048: 4413 add r3, r2 800204a: 009b lsls r3, r3, #2 800204c: 440b add r3, r1 800204e: 3315 adds r3, #21 8002050: 2201 movs r2, #1 8002052: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8002054: 7bfa ldrb r2, [r7, #15] 8002056: 6879 ldr r1, [r7, #4] 8002058: 4613 mov r3, r2 800205a: 00db lsls r3, r3, #3 800205c: 4413 add r3, r2 800205e: 009b lsls r3, r3, #2 8002060: 440b add r3, r1 8002062: 3314 adds r3, #20 8002064: 7bfa ldrb r2, [r7, #15] 8002066: 701a strb r2, [r3, #0] #if defined (USB_OTG_FS) hpcd->IN_ep[i].tx_fifo_num = i; 8002068: 7bfa ldrb r2, [r7, #15] 800206a: 7bfb ldrb r3, [r7, #15] 800206c: b298 uxth r0, r3 800206e: 6879 ldr r1, [r7, #4] 8002070: 4613 mov r3, r2 8002072: 00db lsls r3, r3, #3 8002074: 4413 add r3, r2 8002076: 009b lsls r3, r3, #2 8002078: 440b add r3, r1 800207a: 332e adds r3, #46 @ 0x2e 800207c: 4602 mov r2, r0 800207e: 801a strh r2, [r3, #0] #endif /* defined (USB_OTG_FS) */ /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8002080: 7bfa ldrb r2, [r7, #15] 8002082: 6879 ldr r1, [r7, #4] 8002084: 4613 mov r3, r2 8002086: 00db lsls r3, r3, #3 8002088: 4413 add r3, r2 800208a: 009b lsls r3, r3, #2 800208c: 440b add r3, r1 800208e: 3318 adds r3, #24 8002090: 2200 movs r2, #0 8002092: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8002094: 7bfa ldrb r2, [r7, #15] 8002096: 6879 ldr r1, [r7, #4] 8002098: 4613 mov r3, r2 800209a: 00db lsls r3, r3, #3 800209c: 4413 add r3, r2 800209e: 009b lsls r3, r3, #2 80020a0: 440b add r3, r1 80020a2: 331c adds r3, #28 80020a4: 2200 movs r2, #0 80020a6: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 80020a8: 7bfa ldrb r2, [r7, #15] 80020aa: 6879 ldr r1, [r7, #4] 80020ac: 4613 mov r3, r2 80020ae: 00db lsls r3, r3, #3 80020b0: 4413 add r3, r2 80020b2: 009b lsls r3, r3, #2 80020b4: 440b add r3, r1 80020b6: 3320 adds r3, #32 80020b8: 2200 movs r2, #0 80020ba: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 80020bc: 7bfa ldrb r2, [r7, #15] 80020be: 6879 ldr r1, [r7, #4] 80020c0: 4613 mov r3, r2 80020c2: 00db lsls r3, r3, #3 80020c4: 4413 add r3, r2 80020c6: 009b lsls r3, r3, #2 80020c8: 440b add r3, r1 80020ca: 3324 adds r3, #36 @ 0x24 80020cc: 2200 movs r2, #0 80020ce: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80020d0: 7bfb ldrb r3, [r7, #15] 80020d2: 3301 adds r3, #1 80020d4: 73fb strb r3, [r7, #15] 80020d6: 687b ldr r3, [r7, #4] 80020d8: 791b ldrb r3, [r3, #4] 80020da: 7bfa ldrb r2, [r7, #15] 80020dc: 429a cmp r2, r3 80020de: d3af bcc.n 8002040 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80020e0: 2300 movs r3, #0 80020e2: 73fb strb r3, [r7, #15] 80020e4: e044 b.n 8002170 { hpcd->OUT_ep[i].is_in = 0U; 80020e6: 7bfa ldrb r2, [r7, #15] 80020e8: 6879 ldr r1, [r7, #4] 80020ea: 4613 mov r3, r2 80020ec: 00db lsls r3, r3, #3 80020ee: 4413 add r3, r2 80020f0: 009b lsls r3, r3, #2 80020f2: 440b add r3, r1 80020f4: f203 2355 addw r3, r3, #597 @ 0x255 80020f8: 2200 movs r2, #0 80020fa: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 80020fc: 7bfa ldrb r2, [r7, #15] 80020fe: 6879 ldr r1, [r7, #4] 8002100: 4613 mov r3, r2 8002102: 00db lsls r3, r3, #3 8002104: 4413 add r3, r2 8002106: 009b lsls r3, r3, #2 8002108: 440b add r3, r1 800210a: f503 7315 add.w r3, r3, #596 @ 0x254 800210e: 7bfa ldrb r2, [r7, #15] 8002110: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8002112: 7bfa ldrb r2, [r7, #15] 8002114: 6879 ldr r1, [r7, #4] 8002116: 4613 mov r3, r2 8002118: 00db lsls r3, r3, #3 800211a: 4413 add r3, r2 800211c: 009b lsls r3, r3, #2 800211e: 440b add r3, r1 8002120: f503 7316 add.w r3, r3, #600 @ 0x258 8002124: 2200 movs r2, #0 8002126: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8002128: 7bfa ldrb r2, [r7, #15] 800212a: 6879 ldr r1, [r7, #4] 800212c: 4613 mov r3, r2 800212e: 00db lsls r3, r3, #3 8002130: 4413 add r3, r2 8002132: 009b lsls r3, r3, #2 8002134: 440b add r3, r1 8002136: f503 7317 add.w r3, r3, #604 @ 0x25c 800213a: 2200 movs r2, #0 800213c: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 800213e: 7bfa ldrb r2, [r7, #15] 8002140: 6879 ldr r1, [r7, #4] 8002142: 4613 mov r3, r2 8002144: 00db lsls r3, r3, #3 8002146: 4413 add r3, r2 8002148: 009b lsls r3, r3, #2 800214a: 440b add r3, r1 800214c: f503 7318 add.w r3, r3, #608 @ 0x260 8002150: 2200 movs r2, #0 8002152: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8002154: 7bfa ldrb r2, [r7, #15] 8002156: 6879 ldr r1, [r7, #4] 8002158: 4613 mov r3, r2 800215a: 00db lsls r3, r3, #3 800215c: 4413 add r3, r2 800215e: 009b lsls r3, r3, #2 8002160: 440b add r3, r1 8002162: f503 7319 add.w r3, r3, #612 @ 0x264 8002166: 2200 movs r2, #0 8002168: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800216a: 7bfb ldrb r3, [r7, #15] 800216c: 3301 adds r3, #1 800216e: 73fb strb r3, [r7, #15] 8002170: 687b ldr r3, [r7, #4] 8002172: 791b ldrb r3, [r3, #4] 8002174: 7bfa ldrb r2, [r7, #15] 8002176: 429a cmp r2, r3 8002178: d3b5 bcc.n 80020e6 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 800217a: 687b ldr r3, [r7, #4] 800217c: 6818 ldr r0, [r3, #0] 800217e: 687b ldr r3, [r7, #4] 8002180: 7c1a ldrb r2, [r3, #16] 8002182: f88d 2000 strb.w r2, [sp] 8002186: 3304 adds r3, #4 8002188: cb0e ldmia r3, {r1, r2, r3} 800218a: f002 fd97 bl 8004cbc 800218e: 4603 mov r3, r0 8002190: 2b00 cmp r3, #0 8002192: d005 beq.n 80021a0 { hpcd->State = HAL_PCD_STATE_ERROR; 8002194: 687b ldr r3, [r7, #4] 8002196: 2202 movs r2, #2 8002198: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 800219c: 2301 movs r3, #1 800219e: e013 b.n 80021c8 } hpcd->USB_Address = 0U; 80021a0: 687b ldr r3, [r7, #4] 80021a2: 2200 movs r2, #0 80021a4: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 80021a6: 687b ldr r3, [r7, #4] 80021a8: 2201 movs r2, #1 80021aa: f883 2495 strb.w r2, [r3, #1173] @ 0x495 /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 80021ae: 687b ldr r3, [r7, #4] 80021b0: 7b1b ldrb r3, [r3, #12] 80021b2: 2b01 cmp r3, #1 80021b4: d102 bne.n 80021bc { (void)HAL_PCDEx_ActivateLPM(hpcd); 80021b6: 6878 ldr r0, [r7, #4] 80021b8: f000 f80a bl 80021d0 } (void)USB_DevDisconnect(hpcd->Instance); 80021bc: 687b ldr r3, [r7, #4] 80021be: 681b ldr r3, [r3, #0] 80021c0: 4618 mov r0, r3 80021c2: f002 ff3c bl 800503e return HAL_OK; 80021c6: 2300 movs r3, #0 } 80021c8: 4618 mov r0, r3 80021ca: 3710 adds r7, #16 80021cc: 46bd mov sp, r7 80021ce: bd80 pop {r7, pc} 080021d0 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 80021d0: b480 push {r7} 80021d2: b085 sub sp, #20 80021d4: af00 add r7, sp, #0 80021d6: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80021d8: 687b ldr r3, [r7, #4] 80021da: 681b ldr r3, [r3, #0] 80021dc: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 80021de: 687b ldr r3, [r7, #4] 80021e0: 2201 movs r2, #1 80021e2: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 80021e6: 687b ldr r3, [r7, #4] 80021e8: 2200 movs r2, #0 80021ea: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 80021ee: 68fb ldr r3, [r7, #12] 80021f0: 699b ldr r3, [r3, #24] 80021f2: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 80021f6: 68fb ldr r3, [r7, #12] 80021f8: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 80021fa: 68fb ldr r3, [r7, #12] 80021fc: 6d5b ldr r3, [r3, #84] @ 0x54 80021fe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8002202: f043 0303 orr.w r3, r3, #3 8002206: 68fa ldr r2, [r7, #12] 8002208: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 800220a: 2300 movs r3, #0 } 800220c: 4618 mov r0, r3 800220e: 3714 adds r7, #20 8002210: 46bd mov sp, r7 8002212: f85d 7b04 ldr.w r7, [sp], #4 8002216: 4770 bx lr 08002218 : * @note LSEON bit that switches on and off the LSE crystal belongs as well to the * back-up domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8002218: b480 push {r7} 800221a: af00 add r7, sp, #0 SET_BIT(PWR->CR1, PWR_CR1_DBP); 800221c: 4b05 ldr r3, [pc, #20] @ (8002234 ) 800221e: 681b ldr r3, [r3, #0] 8002220: 4a04 ldr r2, [pc, #16] @ (8002234 ) 8002222: f443 7380 orr.w r3, r3, #256 @ 0x100 8002226: 6013 str r3, [r2, #0] } 8002228: bf00 nop 800222a: 46bd mov sp, r7 800222c: f85d 7b04 ldr.w r7, [sp], #4 8002230: 4770 bx lr 8002232: bf00 nop 8002234: 40007000 .word 0x40007000 08002238 : * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) */ uint32_t HAL_PWREx_GetVoltageRange(void) { 8002238: b480 push {r7} 800223a: af00 add r7, sp, #0 else { return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; } #else return (PWR->CR1 & PWR_CR1_VOS); 800223c: 4b04 ldr r3, [pc, #16] @ (8002250 ) 800223e: 681b ldr r3, [r3, #0] 8002240: f403 63c0 and.w r3, r3, #1536 @ 0x600 #endif } 8002244: 4618 mov r0, r3 8002246: 46bd mov sp, r7 8002248: f85d 7b04 ldr.w r7, [sp], #4 800224c: 4770 bx lr 800224e: bf00 nop 8002250: 40007000 .word 0x40007000 08002254 : * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 8002254: b480 push {r7} 8002256: b085 sub sp, #20 8002258: af00 add r7, sp, #0 800225a: 6078 str r0, [r7, #4] } #else /* If Set Range 1 */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 800225c: 687b ldr r3, [r7, #4] 800225e: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002262: d130 bne.n 80022c6 { if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) 8002264: 4b23 ldr r3, [pc, #140] @ (80022f4 ) 8002266: 681b ldr r3, [r3, #0] 8002268: f403 63c0 and.w r3, r3, #1536 @ 0x600 800226c: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002270: d038 beq.n 80022e4 { /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8002272: 4b20 ldr r3, [pc, #128] @ (80022f4 ) 8002274: 681b ldr r3, [r3, #0] 8002276: f423 63c0 bic.w r3, r3, #1536 @ 0x600 800227a: 4a1e ldr r2, [pc, #120] @ (80022f4 ) 800227c: f443 7300 orr.w r3, r3, #512 @ 0x200 8002280: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8002282: 4b1d ldr r3, [pc, #116] @ (80022f8 ) 8002284: 681b ldr r3, [r3, #0] 8002286: 2232 movs r2, #50 @ 0x32 8002288: fb02 f303 mul.w r3, r2, r3 800228c: 4a1b ldr r2, [pc, #108] @ (80022fc ) 800228e: fba2 2303 umull r2, r3, r2, r3 8002292: 0c9b lsrs r3, r3, #18 8002294: 3301 adds r3, #1 8002296: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8002298: e002 b.n 80022a0 { wait_loop_index--; 800229a: 68fb ldr r3, [r7, #12] 800229c: 3b01 subs r3, #1 800229e: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80022a0: 4b14 ldr r3, [pc, #80] @ (80022f4 ) 80022a2: 695b ldr r3, [r3, #20] 80022a4: f403 6380 and.w r3, r3, #1024 @ 0x400 80022a8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80022ac: d102 bne.n 80022b4 80022ae: 68fb ldr r3, [r7, #12] 80022b0: 2b00 cmp r3, #0 80022b2: d1f2 bne.n 800229a } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 80022b4: 4b0f ldr r3, [pc, #60] @ (80022f4 ) 80022b6: 695b ldr r3, [r3, #20] 80022b8: f403 6380 and.w r3, r3, #1024 @ 0x400 80022bc: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80022c0: d110 bne.n 80022e4 { return HAL_TIMEOUT; 80022c2: 2303 movs r3, #3 80022c4: e00f b.n 80022e6 } } } else { if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) 80022c6: 4b0b ldr r3, [pc, #44] @ (80022f4 ) 80022c8: 681b ldr r3, [r3, #0] 80022ca: f403 63c0 and.w r3, r3, #1536 @ 0x600 80022ce: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80022d2: d007 beq.n 80022e4 { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 80022d4: 4b07 ldr r3, [pc, #28] @ (80022f4 ) 80022d6: 681b ldr r3, [r3, #0] 80022d8: f423 63c0 bic.w r3, r3, #1536 @ 0x600 80022dc: 4a05 ldr r2, [pc, #20] @ (80022f4 ) 80022de: f443 6380 orr.w r3, r3, #1024 @ 0x400 80022e2: 6013 str r3, [r2, #0] /* No need to wait for VOSF to be cleared for this transition */ } } #endif return HAL_OK; 80022e4: 2300 movs r3, #0 } 80022e6: 4618 mov r0, r3 80022e8: 3714 adds r7, #20 80022ea: 46bd mov sp, r7 80022ec: f85d 7b04 ldr.w r7, [sp], #4 80022f0: 4770 bx lr 80022f2: bf00 nop 80022f4: 40007000 .word 0x40007000 80022f8: 20000000 .word 0x20000000 80022fc: 431bde83 .word 0x431bde83 08002300 : * @brief Enable VDDUSB supply. * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. * @retval None */ void HAL_PWREx_EnableVddUSB(void) { 8002300: b480 push {r7} 8002302: af00 add r7, sp, #0 SET_BIT(PWR->CR2, PWR_CR2_USV); 8002304: 4b05 ldr r3, [pc, #20] @ (800231c ) 8002306: 685b ldr r3, [r3, #4] 8002308: 4a04 ldr r2, [pc, #16] @ (800231c ) 800230a: f443 6380 orr.w r3, r3, #1024 @ 0x400 800230e: 6053 str r3, [r2, #4] } 8002310: bf00 nop 8002312: 46bd mov sp, r7 8002314: f85d 7b04 ldr.w r7, [sp], #4 8002318: 4770 bx lr 800231a: bf00 nop 800231c: 40007000 .word 0x40007000 08002320 : * in the QSPI_InitTypeDef and initialize the associated handle. * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) { 8002320: b580 push {r7, lr} 8002322: b086 sub sp, #24 8002324: af02 add r7, sp, #8 8002326: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); 8002328: f7ff f8f4 bl 8001514 800232c: 60f8 str r0, [r7, #12] /* Check the QSPI handle allocation */ if(hqspi == NULL) 800232e: 687b ldr r3, [r7, #4] 8002330: 2b00 cmp r3, #0 8002332: d101 bne.n 8002338 { return HAL_ERROR; 8002334: 2301 movs r3, #1 8002336: e063 b.n 8002400 { assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); } #endif if(hqspi->State == HAL_QSPI_STATE_RESET) 8002338: 687b ldr r3, [r7, #4] 800233a: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 800233e: b2db uxtb r3, r3 8002340: 2b00 cmp r3, #0 8002342: d10b bne.n 800235c { /* Allocate lock resource and initialize it */ hqspi->Lock = HAL_UNLOCKED; 8002344: 687b ldr r3, [r7, #4] 8002346: 2200 movs r2, #0 8002348: f883 2038 strb.w r2, [r3, #56] @ 0x38 /* Init the low level hardware */ hqspi->MspInitCallback(hqspi); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_QSPI_MspInit(hqspi); 800234c: 6878 ldr r0, [r7, #4] 800234e: f7fe fdf5 bl 8000f3c #endif /* Configure the default timeout for the QSPI memory access */ HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); 8002352: f241 3188 movw r1, #5000 @ 0x1388 8002356: 6878 ldr r0, [r7, #4] 8002358: f000 f858 bl 800240c } /* Configure QSPI FIFO Threshold */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, 800235c: 687b ldr r3, [r7, #4] 800235e: 681b ldr r3, [r3, #0] 8002360: 681b ldr r3, [r3, #0] 8002362: f423 6170 bic.w r1, r3, #3840 @ 0xf00 8002366: 687b ldr r3, [r7, #4] 8002368: 689b ldr r3, [r3, #8] 800236a: 3b01 subs r3, #1 800236c: 021a lsls r2, r3, #8 800236e: 687b ldr r3, [r7, #4] 8002370: 681b ldr r3, [r3, #0] 8002372: 430a orrs r2, r1 8002374: 601a str r2, [r3, #0] ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); 8002376: 687b ldr r3, [r7, #4] 8002378: 6c1b ldr r3, [r3, #64] @ 0x40 800237a: 9300 str r3, [sp, #0] 800237c: 68fb ldr r3, [r7, #12] 800237e: 2200 movs r2, #0 8002380: 2120 movs r1, #32 8002382: 6878 ldr r0, [r7, #4] 8002384: f000 f850 bl 8002428 8002388: 4603 mov r3, r0 800238a: 72fb strb r3, [r7, #11] if(status == HAL_OK) 800238c: 7afb ldrb r3, [r7, #11] 800238e: 2b00 cmp r3, #0 8002390: d131 bne.n 80023f6 #if defined(QUADSPI_CR_DFM) MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); #else MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), 8002392: 687b ldr r3, [r7, #4] 8002394: 681b ldr r3, [r3, #0] 8002396: 681b ldr r3, [r3, #0] 8002398: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000 800239c: f023 0310 bic.w r3, r3, #16 80023a0: 687a ldr r2, [r7, #4] 80023a2: 6852 ldr r2, [r2, #4] 80023a4: 0611 lsls r1, r2, #24 80023a6: 687a ldr r2, [r7, #4] 80023a8: 68d2 ldr r2, [r2, #12] 80023aa: 4311 orrs r1, r2 80023ac: 687a ldr r2, [r7, #4] 80023ae: 6812 ldr r2, [r2, #0] 80023b0: 430b orrs r3, r1 80023b2: 6013 str r3, [r2, #0] ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting)); #endif /* Configure QSPI Flash Size, CS High Time and Clock Mode */ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), 80023b4: 687b ldr r3, [r7, #4] 80023b6: 681b ldr r3, [r3, #0] 80023b8: 685a ldr r2, [r3, #4] 80023ba: 4b13 ldr r3, [pc, #76] @ (8002408 ) 80023bc: 4013 ands r3, r2 80023be: 687a ldr r2, [r7, #4] 80023c0: 6912 ldr r2, [r2, #16] 80023c2: 0411 lsls r1, r2, #16 80023c4: 687a ldr r2, [r7, #4] 80023c6: 6952 ldr r2, [r2, #20] 80023c8: 4311 orrs r1, r2 80023ca: 687a ldr r2, [r7, #4] 80023cc: 6992 ldr r2, [r2, #24] 80023ce: 4311 orrs r1, r2 80023d0: 687a ldr r2, [r7, #4] 80023d2: 6812 ldr r2, [r2, #0] 80023d4: 430b orrs r3, r1 80023d6: 6053 str r3, [r2, #4] ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); /* Enable the QSPI peripheral */ __HAL_QSPI_ENABLE(hqspi); 80023d8: 687b ldr r3, [r7, #4] 80023da: 681b ldr r3, [r3, #0] 80023dc: 681a ldr r2, [r3, #0] 80023de: 687b ldr r3, [r7, #4] 80023e0: 681b ldr r3, [r3, #0] 80023e2: f042 0201 orr.w r2, r2, #1 80023e6: 601a str r2, [r3, #0] /* Set QSPI error code to none */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; 80023e8: 687b ldr r3, [r7, #4] 80023ea: 2200 movs r2, #0 80023ec: 63da str r2, [r3, #60] @ 0x3c /* Initialize the QSPI state */ hqspi->State = HAL_QSPI_STATE_READY; 80023ee: 687b ldr r3, [r7, #4] 80023f0: 2201 movs r2, #1 80023f2: f883 2039 strb.w r2, [r3, #57] @ 0x39 } /* Release Lock */ __HAL_UNLOCK(hqspi); 80023f6: 687b ldr r3, [r7, #4] 80023f8: 2200 movs r2, #0 80023fa: f883 2038 strb.w r2, [r3, #56] @ 0x38 /* Return function status */ return status; 80023fe: 7afb ldrb r3, [r7, #11] } 8002400: 4618 mov r0, r3 8002402: 3710 adds r7, #16 8002404: 46bd mov sp, r7 8002406: bd80 pop {r7, pc} 8002408: ffe0f8fe .word 0xffe0f8fe 0800240c : * @param hqspi QSPI handle. * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) { 800240c: b480 push {r7} 800240e: b083 sub sp, #12 8002410: af00 add r7, sp, #0 8002412: 6078 str r0, [r7, #4] 8002414: 6039 str r1, [r7, #0] hqspi->Timeout = Timeout; 8002416: 687b ldr r3, [r7, #4] 8002418: 683a ldr r2, [r7, #0] 800241a: 641a str r2, [r3, #64] @ 0x40 } 800241c: bf00 nop 800241e: 370c adds r7, #12 8002420: 46bd mov sp, r7 8002422: f85d 7b04 ldr.w r7, [sp], #4 8002426: 4770 bx lr 08002428 : * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { 8002428: b580 push {r7, lr} 800242a: b084 sub sp, #16 800242c: af00 add r7, sp, #0 800242e: 60f8 str r0, [r7, #12] 8002430: 60b9 str r1, [r7, #8] 8002432: 603b str r3, [r7, #0] 8002434: 4613 mov r3, r2 8002436: 71fb strb r3, [r7, #7] /* Wait until flag is in expected state */ while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) 8002438: e01a b.n 8002470 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800243a: 69bb ldr r3, [r7, #24] 800243c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8002440: d016 beq.n 8002470 { if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8002442: f7ff f867 bl 8001514 8002446: 4602 mov r2, r0 8002448: 683b ldr r3, [r7, #0] 800244a: 1ad3 subs r3, r2, r3 800244c: 69ba ldr r2, [r7, #24] 800244e: 429a cmp r2, r3 8002450: d302 bcc.n 8002458 8002452: 69bb ldr r3, [r7, #24] 8002454: 2b00 cmp r3, #0 8002456: d10b bne.n 8002470 { hqspi->State = HAL_QSPI_STATE_ERROR; 8002458: 68fb ldr r3, [r7, #12] 800245a: 2204 movs r2, #4 800245c: f883 2039 strb.w r2, [r3, #57] @ 0x39 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; 8002460: 68fb ldr r3, [r7, #12] 8002462: 6bdb ldr r3, [r3, #60] @ 0x3c 8002464: f043 0201 orr.w r2, r3, #1 8002468: 68fb ldr r3, [r7, #12] 800246a: 63da str r2, [r3, #60] @ 0x3c return HAL_ERROR; 800246c: 2301 movs r3, #1 800246e: e00e b.n 800248e while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) 8002470: 68fb ldr r3, [r7, #12] 8002472: 681b ldr r3, [r3, #0] 8002474: 689a ldr r2, [r3, #8] 8002476: 68bb ldr r3, [r7, #8] 8002478: 4013 ands r3, r2 800247a: 2b00 cmp r3, #0 800247c: bf14 ite ne 800247e: 2301 movne r3, #1 8002480: 2300 moveq r3, #0 8002482: b2db uxtb r3, r3 8002484: 461a mov r2, r3 8002486: 79fb ldrb r3, [r7, #7] 8002488: 429a cmp r2, r3 800248a: d1d6 bne.n 800243a } } } return HAL_OK; 800248c: 2300 movs r3, #0 } 800248e: 4618 mov r0, r3 8002490: 3710 adds r7, #16 8002492: 46bd mov sp, r7 8002494: bd80 pop {r7, pc} ... 08002498 : * @note If HSE failed to start, HSE should be disabled before recalling HAL_RCC_OscConfig(). * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8002498: b580 push {r7, lr} 800249a: b088 sub sp, #32 800249c: af00 add r7, sp, #0 800249e: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status; uint32_t sysclk_source, pll_config; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 80024a0: 687b ldr r3, [r7, #4] 80024a2: 2b00 cmp r3, #0 80024a4: d101 bne.n 80024aa { return HAL_ERROR; 80024a6: 2301 movs r3, #1 80024a8: e3ca b.n 8002c40 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); 80024aa: 4b97 ldr r3, [pc, #604] @ (8002708 ) 80024ac: 689b ldr r3, [r3, #8] 80024ae: f003 030c and.w r3, r3, #12 80024b2: 61bb str r3, [r7, #24] pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); 80024b4: 4b94 ldr r3, [pc, #592] @ (8002708 ) 80024b6: 68db ldr r3, [r3, #12] 80024b8: f003 0303 and.w r3, r3, #3 80024bc: 617b str r3, [r7, #20] /*----------------------------- MSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) 80024be: 687b ldr r3, [r7, #4] 80024c0: 681b ldr r3, [r3, #0] 80024c2: f003 0310 and.w r3, r3, #16 80024c6: 2b00 cmp r3, #0 80024c8: f000 80e4 beq.w 8002694 assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */ if((sysclk_source == RCC_CFGR_SWS_MSI) || 80024cc: 69bb ldr r3, [r7, #24] 80024ce: 2b00 cmp r3, #0 80024d0: d007 beq.n 80024e2 80024d2: 69bb ldr r3, [r7, #24] 80024d4: 2b0c cmp r3, #12 80024d6: f040 808b bne.w 80025f0 ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI))) 80024da: 697b ldr r3, [r7, #20] 80024dc: 2b01 cmp r3, #1 80024de: f040 8087 bne.w 80025f0 { if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) 80024e2: 4b89 ldr r3, [pc, #548] @ (8002708 ) 80024e4: 681b ldr r3, [r3, #0] 80024e6: f003 0302 and.w r3, r3, #2 80024ea: 2b00 cmp r3, #0 80024ec: d005 beq.n 80024fa 80024ee: 687b ldr r3, [r7, #4] 80024f0: 699b ldr r3, [r3, #24] 80024f2: 2b00 cmp r3, #0 80024f4: d101 bne.n 80024fa { return HAL_ERROR; 80024f6: 2301 movs r3, #1 80024f8: e3a2 b.n 8002c40 else { /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) 80024fa: 687b ldr r3, [r7, #4] 80024fc: 6a1a ldr r2, [r3, #32] 80024fe: 4b82 ldr r3, [pc, #520] @ (8002708 ) 8002500: 681b ldr r3, [r3, #0] 8002502: f003 0308 and.w r3, r3, #8 8002506: 2b00 cmp r3, #0 8002508: d004 beq.n 8002514 800250a: 4b7f ldr r3, [pc, #508] @ (8002708 ) 800250c: 681b ldr r3, [r3, #0] 800250e: f003 03f0 and.w r3, r3, #240 @ 0xf0 8002512: e005 b.n 8002520 8002514: 4b7c ldr r3, [pc, #496] @ (8002708 ) 8002516: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800251a: 091b lsrs r3, r3, #4 800251c: f003 03f0 and.w r3, r3, #240 @ 0xf0 8002520: 4293 cmp r3, r2 8002522: d223 bcs.n 800256c { /* First increase number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 8002524: 687b ldr r3, [r7, #4] 8002526: 6a1b ldr r3, [r3, #32] 8002528: 4618 mov r0, r3 800252a: f000 fd87 bl 800303c 800252e: 4603 mov r3, r0 8002530: 2b00 cmp r3, #0 8002532: d001 beq.n 8002538 { return HAL_ERROR; 8002534: 2301 movs r3, #1 8002536: e383 b.n 8002c40 } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8002538: 4b73 ldr r3, [pc, #460] @ (8002708 ) 800253a: 681b ldr r3, [r3, #0] 800253c: 4a72 ldr r2, [pc, #456] @ (8002708 ) 800253e: f043 0308 orr.w r3, r3, #8 8002542: 6013 str r3, [r2, #0] 8002544: 4b70 ldr r3, [pc, #448] @ (8002708 ) 8002546: 681b ldr r3, [r3, #0] 8002548: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800254c: 687b ldr r3, [r7, #4] 800254e: 6a1b ldr r3, [r3, #32] 8002550: 496d ldr r1, [pc, #436] @ (8002708 ) 8002552: 4313 orrs r3, r2 8002554: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8002556: 4b6c ldr r3, [pc, #432] @ (8002708 ) 8002558: 685b ldr r3, [r3, #4] 800255a: f423 427f bic.w r2, r3, #65280 @ 0xff00 800255e: 687b ldr r3, [r7, #4] 8002560: 69db ldr r3, [r3, #28] 8002562: 021b lsls r3, r3, #8 8002564: 4968 ldr r1, [pc, #416] @ (8002708 ) 8002566: 4313 orrs r3, r2 8002568: 604b str r3, [r1, #4] 800256a: e025 b.n 80025b8 } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800256c: 4b66 ldr r3, [pc, #408] @ (8002708 ) 800256e: 681b ldr r3, [r3, #0] 8002570: 4a65 ldr r2, [pc, #404] @ (8002708 ) 8002572: f043 0308 orr.w r3, r3, #8 8002576: 6013 str r3, [r2, #0] 8002578: 4b63 ldr r3, [pc, #396] @ (8002708 ) 800257a: 681b ldr r3, [r3, #0] 800257c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8002580: 687b ldr r3, [r7, #4] 8002582: 6a1b ldr r3, [r3, #32] 8002584: 4960 ldr r1, [pc, #384] @ (8002708 ) 8002586: 4313 orrs r3, r2 8002588: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 800258a: 4b5f ldr r3, [pc, #380] @ (8002708 ) 800258c: 685b ldr r3, [r3, #4] 800258e: f423 427f bic.w r2, r3, #65280 @ 0xff00 8002592: 687b ldr r3, [r7, #4] 8002594: 69db ldr r3, [r3, #28] 8002596: 021b lsls r3, r3, #8 8002598: 495b ldr r1, [pc, #364] @ (8002708 ) 800259a: 4313 orrs r3, r2 800259c: 604b str r3, [r1, #4] /* Decrease number of wait states update if necessary */ /* Only possible when MSI is the System clock source */ if(sysclk_source == RCC_CFGR_SWS_MSI) 800259e: 69bb ldr r3, [r7, #24] 80025a0: 2b00 cmp r3, #0 80025a2: d109 bne.n 80025b8 { if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 80025a4: 687b ldr r3, [r7, #4] 80025a6: 6a1b ldr r3, [r3, #32] 80025a8: 4618 mov r0, r3 80025aa: f000 fd47 bl 800303c 80025ae: 4603 mov r3, r0 80025b0: 2b00 cmp r3, #0 80025b2: d001 beq.n 80025b8 { return HAL_ERROR; 80025b4: 2301 movs r3, #1 80025b6: e343 b.n 8002c40 } } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 80025b8: f000 fc4a bl 8002e50 80025bc: 4602 mov r2, r0 80025be: 4b52 ldr r3, [pc, #328] @ (8002708 ) 80025c0: 689b ldr r3, [r3, #8] 80025c2: 091b lsrs r3, r3, #4 80025c4: f003 030f and.w r3, r3, #15 80025c8: 4950 ldr r1, [pc, #320] @ (800270c ) 80025ca: 5ccb ldrb r3, [r1, r3] 80025cc: f003 031f and.w r3, r3, #31 80025d0: fa22 f303 lsr.w r3, r2, r3 80025d4: 4a4e ldr r2, [pc, #312] @ (8002710 ) 80025d6: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ status = HAL_InitTick(uwTickPrio); 80025d8: 4b4e ldr r3, [pc, #312] @ (8002714 ) 80025da: 681b ldr r3, [r3, #0] 80025dc: 4618 mov r0, r3 80025de: f7fe fe75 bl 80012cc 80025e2: 4603 mov r3, r0 80025e4: 73fb strb r3, [r7, #15] if(status != HAL_OK) 80025e6: 7bfb ldrb r3, [r7, #15] 80025e8: 2b00 cmp r3, #0 80025ea: d052 beq.n 8002692 { return status; 80025ec: 7bfb ldrb r3, [r7, #15] 80025ee: e327 b.n 8002c40 } } else { /* Check the MSI State */ if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) 80025f0: 687b ldr r3, [r7, #4] 80025f2: 699b ldr r3, [r3, #24] 80025f4: 2b00 cmp r3, #0 80025f6: d032 beq.n 800265e { /* Enable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); 80025f8: 4b43 ldr r3, [pc, #268] @ (8002708 ) 80025fa: 681b ldr r3, [r3, #0] 80025fc: 4a42 ldr r2, [pc, #264] @ (8002708 ) 80025fe: f043 0301 orr.w r3, r3, #1 8002602: 6013 str r3, [r2, #0] /* Get timeout */ tickstart = HAL_GetTick(); 8002604: f7fe ff86 bl 8001514 8002608: 6138 str r0, [r7, #16] /* Wait till MSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) 800260a: e008 b.n 800261e { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 800260c: f7fe ff82 bl 8001514 8002610: 4602 mov r2, r0 8002612: 693b ldr r3, [r7, #16] 8002614: 1ad3 subs r3, r2, r3 8002616: 2b02 cmp r3, #2 8002618: d901 bls.n 800261e { return HAL_TIMEOUT; 800261a: 2303 movs r3, #3 800261c: e310 b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) 800261e: 4b3a ldr r3, [pc, #232] @ (8002708 ) 8002620: 681b ldr r3, [r3, #0] 8002622: f003 0302 and.w r3, r3, #2 8002626: 2b00 cmp r3, #0 8002628: d0f0 beq.n 800260c } } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800262a: 4b37 ldr r3, [pc, #220] @ (8002708 ) 800262c: 681b ldr r3, [r3, #0] 800262e: 4a36 ldr r2, [pc, #216] @ (8002708 ) 8002630: f043 0308 orr.w r3, r3, #8 8002634: 6013 str r3, [r2, #0] 8002636: 4b34 ldr r3, [pc, #208] @ (8002708 ) 8002638: 681b ldr r3, [r3, #0] 800263a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800263e: 687b ldr r3, [r7, #4] 8002640: 6a1b ldr r3, [r3, #32] 8002642: 4931 ldr r1, [pc, #196] @ (8002708 ) 8002644: 4313 orrs r3, r2 8002646: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8002648: 4b2f ldr r3, [pc, #188] @ (8002708 ) 800264a: 685b ldr r3, [r3, #4] 800264c: f423 427f bic.w r2, r3, #65280 @ 0xff00 8002650: 687b ldr r3, [r7, #4] 8002652: 69db ldr r3, [r3, #28] 8002654: 021b lsls r3, r3, #8 8002656: 492c ldr r1, [pc, #176] @ (8002708 ) 8002658: 4313 orrs r3, r2 800265a: 604b str r3, [r1, #4] 800265c: e01a b.n 8002694 } else { /* Disable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); 800265e: 4b2a ldr r3, [pc, #168] @ (8002708 ) 8002660: 681b ldr r3, [r3, #0] 8002662: 4a29 ldr r2, [pc, #164] @ (8002708 ) 8002664: f023 0301 bic.w r3, r3, #1 8002668: 6013 str r3, [r2, #0] /* Get timeout */ tickstart = HAL_GetTick(); 800266a: f7fe ff53 bl 8001514 800266e: 6138 str r0, [r7, #16] /* Wait till MSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) 8002670: e008 b.n 8002684 { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 8002672: f7fe ff4f bl 8001514 8002676: 4602 mov r2, r0 8002678: 693b ldr r3, [r7, #16] 800267a: 1ad3 subs r3, r2, r3 800267c: 2b02 cmp r3, #2 800267e: d901 bls.n 8002684 { return HAL_TIMEOUT; 8002680: 2303 movs r3, #3 8002682: e2dd b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) 8002684: 4b20 ldr r3, [pc, #128] @ (8002708 ) 8002686: 681b ldr r3, [r3, #0] 8002688: f003 0302 and.w r3, r3, #2 800268c: 2b00 cmp r3, #0 800268e: d1f0 bne.n 8002672 8002690: e000 b.n 8002694 if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) 8002692: bf00 nop } } } } /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8002694: 687b ldr r3, [r7, #4] 8002696: 681b ldr r3, [r3, #0] 8002698: f003 0301 and.w r3, r3, #1 800269c: 2b00 cmp r3, #0 800269e: d074 beq.n 800278a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((sysclk_source == RCC_CFGR_SWS_HSE) || 80026a0: 69bb ldr r3, [r7, #24] 80026a2: 2b08 cmp r3, #8 80026a4: d005 beq.n 80026b2 80026a6: 69bb ldr r3, [r7, #24] 80026a8: 2b0c cmp r3, #12 80026aa: d10e bne.n 80026ca ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE))) 80026ac: 697b ldr r3, [r7, #20] 80026ae: 2b03 cmp r3, #3 80026b0: d10b bne.n 80026ca { if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80026b2: 4b15 ldr r3, [pc, #84] @ (8002708 ) 80026b4: 681b ldr r3, [r3, #0] 80026b6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80026ba: 2b00 cmp r3, #0 80026bc: d064 beq.n 8002788 80026be: 687b ldr r3, [r7, #4] 80026c0: 685b ldr r3, [r3, #4] 80026c2: 2b00 cmp r3, #0 80026c4: d160 bne.n 8002788 { return HAL_ERROR; 80026c6: 2301 movs r3, #1 80026c8: e2ba b.n 8002c40 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80026ca: 687b ldr r3, [r7, #4] 80026cc: 685b ldr r3, [r3, #4] 80026ce: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80026d2: d106 bne.n 80026e2 80026d4: 4b0c ldr r3, [pc, #48] @ (8002708 ) 80026d6: 681b ldr r3, [r3, #0] 80026d8: 4a0b ldr r2, [pc, #44] @ (8002708 ) 80026da: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80026de: 6013 str r3, [r2, #0] 80026e0: e026 b.n 8002730 80026e2: 687b ldr r3, [r7, #4] 80026e4: 685b ldr r3, [r3, #4] 80026e6: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80026ea: d115 bne.n 8002718 80026ec: 4b06 ldr r3, [pc, #24] @ (8002708 ) 80026ee: 681b ldr r3, [r3, #0] 80026f0: 4a05 ldr r2, [pc, #20] @ (8002708 ) 80026f2: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80026f6: 6013 str r3, [r2, #0] 80026f8: 4b03 ldr r3, [pc, #12] @ (8002708 ) 80026fa: 681b ldr r3, [r3, #0] 80026fc: 4a02 ldr r2, [pc, #8] @ (8002708 ) 80026fe: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8002702: 6013 str r3, [r2, #0] 8002704: e014 b.n 8002730 8002706: bf00 nop 8002708: 40021000 .word 0x40021000 800270c: 08007eac .word 0x08007eac 8002710: 20000000 .word 0x20000000 8002714: 20000004 .word 0x20000004 8002718: 4ba0 ldr r3, [pc, #640] @ (800299c ) 800271a: 681b ldr r3, [r3, #0] 800271c: 4a9f ldr r2, [pc, #636] @ (800299c ) 800271e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002722: 6013 str r3, [r2, #0] 8002724: 4b9d ldr r3, [pc, #628] @ (800299c ) 8002726: 681b ldr r3, [r3, #0] 8002728: 4a9c ldr r2, [pc, #624] @ (800299c ) 800272a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800272e: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8002730: 687b ldr r3, [r7, #4] 8002732: 685b ldr r3, [r3, #4] 8002734: 2b00 cmp r3, #0 8002736: d013 beq.n 8002760 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002738: f7fe feec bl 8001514 800273c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 800273e: e008 b.n 8002752 { if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002740: f7fe fee8 bl 8001514 8002744: 4602 mov r2, r0 8002746: 693b ldr r3, [r7, #16] 8002748: 1ad3 subs r3, r2, r3 800274a: 2b64 cmp r3, #100 @ 0x64 800274c: d901 bls.n 8002752 { return HAL_TIMEOUT; 800274e: 2303 movs r3, #3 8002750: e276 b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002752: 4b92 ldr r3, [pc, #584] @ (800299c ) 8002754: 681b ldr r3, [r3, #0] 8002756: f403 3300 and.w r3, r3, #131072 @ 0x20000 800275a: 2b00 cmp r3, #0 800275c: d0f0 beq.n 8002740 800275e: e014 b.n 800278a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002760: f7fe fed8 bl 8001514 8002764: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8002766: e008 b.n 800277a { if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002768: f7fe fed4 bl 8001514 800276c: 4602 mov r2, r0 800276e: 693b ldr r3, [r7, #16] 8002770: 1ad3 subs r3, r2, r3 8002772: 2b64 cmp r3, #100 @ 0x64 8002774: d901 bls.n 800277a { return HAL_TIMEOUT; 8002776: 2303 movs r3, #3 8002778: e262 b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 800277a: 4b88 ldr r3, [pc, #544] @ (800299c ) 800277c: 681b ldr r3, [r3, #0] 800277e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002782: 2b00 cmp r3, #0 8002784: d1f0 bne.n 8002768 8002786: e000 b.n 800278a if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8002788: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800278a: 687b ldr r3, [r7, #4] 800278c: 681b ldr r3, [r3, #0] 800278e: f003 0302 and.w r3, r3, #2 8002792: 2b00 cmp r3, #0 8002794: d060 beq.n 8002858 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((sysclk_source == RCC_CFGR_SWS_HSI) || 8002796: 69bb ldr r3, [r7, #24] 8002798: 2b04 cmp r3, #4 800279a: d005 beq.n 80027a8 800279c: 69bb ldr r3, [r7, #24] 800279e: 2b0c cmp r3, #12 80027a0: d119 bne.n 80027d6 ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI))) 80027a2: 697b ldr r3, [r7, #20] 80027a4: 2b02 cmp r3, #2 80027a6: d116 bne.n 80027d6 { /* When HSI is used as system clock it will not be disabled */ if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80027a8: 4b7c ldr r3, [pc, #496] @ (800299c ) 80027aa: 681b ldr r3, [r3, #0] 80027ac: f403 6380 and.w r3, r3, #1024 @ 0x400 80027b0: 2b00 cmp r3, #0 80027b2: d005 beq.n 80027c0 80027b4: 687b ldr r3, [r7, #4] 80027b6: 68db ldr r3, [r3, #12] 80027b8: 2b00 cmp r3, #0 80027ba: d101 bne.n 80027c0 { return HAL_ERROR; 80027bc: 2301 movs r3, #1 80027be: e23f b.n 8002c40 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80027c0: 4b76 ldr r3, [pc, #472] @ (800299c ) 80027c2: 685b ldr r3, [r3, #4] 80027c4: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000 80027c8: 687b ldr r3, [r7, #4] 80027ca: 691b ldr r3, [r3, #16] 80027cc: 061b lsls r3, r3, #24 80027ce: 4973 ldr r1, [pc, #460] @ (800299c ) 80027d0: 4313 orrs r3, r2 80027d2: 604b str r3, [r1, #4] if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80027d4: e040 b.n 8002858 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80027d6: 687b ldr r3, [r7, #4] 80027d8: 68db ldr r3, [r3, #12] 80027da: 2b00 cmp r3, #0 80027dc: d023 beq.n 8002826 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80027de: 4b6f ldr r3, [pc, #444] @ (800299c ) 80027e0: 681b ldr r3, [r3, #0] 80027e2: 4a6e ldr r2, [pc, #440] @ (800299c ) 80027e4: f443 7380 orr.w r3, r3, #256 @ 0x100 80027e8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80027ea: f7fe fe93 bl 8001514 80027ee: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 80027f0: e008 b.n 8002804 { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80027f2: f7fe fe8f bl 8001514 80027f6: 4602 mov r2, r0 80027f8: 693b ldr r3, [r7, #16] 80027fa: 1ad3 subs r3, r2, r3 80027fc: 2b02 cmp r3, #2 80027fe: d901 bls.n 8002804 { return HAL_TIMEOUT; 8002800: 2303 movs r3, #3 8002802: e21d b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002804: 4b65 ldr r3, [pc, #404] @ (800299c ) 8002806: 681b ldr r3, [r3, #0] 8002808: f403 6380 and.w r3, r3, #1024 @ 0x400 800280c: 2b00 cmp r3, #0 800280e: d0f0 beq.n 80027f2 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8002810: 4b62 ldr r3, [pc, #392] @ (800299c ) 8002812: 685b ldr r3, [r3, #4] 8002814: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000 8002818: 687b ldr r3, [r7, #4] 800281a: 691b ldr r3, [r3, #16] 800281c: 061b lsls r3, r3, #24 800281e: 495f ldr r1, [pc, #380] @ (800299c ) 8002820: 4313 orrs r3, r2 8002822: 604b str r3, [r1, #4] 8002824: e018 b.n 8002858 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8002826: 4b5d ldr r3, [pc, #372] @ (800299c ) 8002828: 681b ldr r3, [r3, #0] 800282a: 4a5c ldr r2, [pc, #368] @ (800299c ) 800282c: f423 7380 bic.w r3, r3, #256 @ 0x100 8002830: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002832: f7fe fe6f bl 8001514 8002836: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8002838: e008 b.n 800284c { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800283a: f7fe fe6b bl 8001514 800283e: 4602 mov r2, r0 8002840: 693b ldr r3, [r7, #16] 8002842: 1ad3 subs r3, r2, r3 8002844: 2b02 cmp r3, #2 8002846: d901 bls.n 800284c { return HAL_TIMEOUT; 8002848: 2303 movs r3, #3 800284a: e1f9 b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 800284c: 4b53 ldr r3, [pc, #332] @ (800299c ) 800284e: 681b ldr r3, [r3, #0] 8002850: f403 6380 and.w r3, r3, #1024 @ 0x400 8002854: 2b00 cmp r3, #0 8002856: d1f0 bne.n 800283a } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8002858: 687b ldr r3, [r7, #4] 800285a: 681b ldr r3, [r3, #0] 800285c: f003 0308 and.w r3, r3, #8 8002860: 2b00 cmp r3, #0 8002862: d03c beq.n 80028de { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8002864: 687b ldr r3, [r7, #4] 8002866: 695b ldr r3, [r3, #20] 8002868: 2b00 cmp r3, #0 800286a: d01c beq.n 80028a6 MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv); } #endif /* RCC_CSR_LSIPREDIV */ /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800286c: 4b4b ldr r3, [pc, #300] @ (800299c ) 800286e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8002872: 4a4a ldr r2, [pc, #296] @ (800299c ) 8002874: f043 0301 orr.w r3, r3, #1 8002878: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800287c: f7fe fe4a bl 8001514 8002880: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002882: e008 b.n 8002896 { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002884: f7fe fe46 bl 8001514 8002888: 4602 mov r2, r0 800288a: 693b ldr r3, [r7, #16] 800288c: 1ad3 subs r3, r2, r3 800288e: 2b02 cmp r3, #2 8002890: d901 bls.n 8002896 { return HAL_TIMEOUT; 8002892: 2303 movs r3, #3 8002894: e1d4 b.n 8002c40 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002896: 4b41 ldr r3, [pc, #260] @ (800299c ) 8002898: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800289c: f003 0302 and.w r3, r3, #2 80028a0: 2b00 cmp r3, #0 80028a2: d0ef beq.n 8002884 80028a4: e01b b.n 80028de } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80028a6: 4b3d ldr r3, [pc, #244] @ (800299c ) 80028a8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80028ac: 4a3b ldr r2, [pc, #236] @ (800299c ) 80028ae: f023 0301 bic.w r3, r3, #1 80028b2: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80028b6: f7fe fe2d bl 8001514 80028ba: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 80028bc: e008 b.n 80028d0 { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80028be: f7fe fe29 bl 8001514 80028c2: 4602 mov r2, r0 80028c4: 693b ldr r3, [r7, #16] 80028c6: 1ad3 subs r3, r2, r3 80028c8: 2b02 cmp r3, #2 80028ca: d901 bls.n 80028d0 { return HAL_TIMEOUT; 80028cc: 2303 movs r3, #3 80028ce: e1b7 b.n 8002c40 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 80028d0: 4b32 ldr r3, [pc, #200] @ (800299c ) 80028d2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80028d6: f003 0302 and.w r3, r3, #2 80028da: 2b00 cmp r3, #0 80028dc: d1ef bne.n 80028be } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80028de: 687b ldr r3, [r7, #4] 80028e0: 681b ldr r3, [r3, #0] 80028e2: f003 0304 and.w r3, r3, #4 80028e6: 2b00 cmp r3, #0 80028e8: f000 80a6 beq.w 8002a38 { FlagStatus pwrclkchanged = RESET; 80028ec: 2300 movs r3, #0 80028ee: 77fb strb r3, [r7, #31] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)) 80028f0: 4b2a ldr r3, [pc, #168] @ (800299c ) 80028f2: 6d9b ldr r3, [r3, #88] @ 0x58 80028f4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80028f8: 2b00 cmp r3, #0 80028fa: d10d bne.n 8002918 { __HAL_RCC_PWR_CLK_ENABLE(); 80028fc: 4b27 ldr r3, [pc, #156] @ (800299c ) 80028fe: 6d9b ldr r3, [r3, #88] @ 0x58 8002900: 4a26 ldr r2, [pc, #152] @ (800299c ) 8002902: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8002906: 6593 str r3, [r2, #88] @ 0x58 8002908: 4b24 ldr r3, [pc, #144] @ (800299c ) 800290a: 6d9b ldr r3, [r3, #88] @ 0x58 800290c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8002910: 60bb str r3, [r7, #8] 8002912: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8002914: 2301 movs r3, #1 8002916: 77fb strb r3, [r7, #31] } if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8002918: 4b21 ldr r3, [pc, #132] @ (80029a0 ) 800291a: 681b ldr r3, [r3, #0] 800291c: f403 7380 and.w r3, r3, #256 @ 0x100 8002920: 2b00 cmp r3, #0 8002922: d118 bne.n 8002956 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8002924: 4b1e ldr r3, [pc, #120] @ (80029a0 ) 8002926: 681b ldr r3, [r3, #0] 8002928: 4a1d ldr r2, [pc, #116] @ (80029a0 ) 800292a: f443 7380 orr.w r3, r3, #256 @ 0x100 800292e: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8002930: f7fe fdf0 bl 8001514 8002934: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8002936: e008 b.n 800294a { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8002938: f7fe fdec bl 8001514 800293c: 4602 mov r2, r0 800293e: 693b ldr r3, [r7, #16] 8002940: 1ad3 subs r3, r2, r3 8002942: 2b02 cmp r3, #2 8002944: d901 bls.n 800294a { return HAL_TIMEOUT; 8002946: 2303 movs r3, #3 8002948: e17a b.n 8002c40 while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800294a: 4b15 ldr r3, [pc, #84] @ (80029a0 ) 800294c: 681b ldr r3, [r3, #0] 800294e: f403 7380 and.w r3, r3, #256 @ 0x100 8002952: 2b00 cmp r3, #0 8002954: d0f0 beq.n 8002938 { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } #else __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8002956: 687b ldr r3, [r7, #4] 8002958: 689b ldr r3, [r3, #8] 800295a: 2b01 cmp r3, #1 800295c: d108 bne.n 8002970 800295e: 4b0f ldr r3, [pc, #60] @ (800299c ) 8002960: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002964: 4a0d ldr r2, [pc, #52] @ (800299c ) 8002966: f043 0301 orr.w r3, r3, #1 800296a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 800296e: e029 b.n 80029c4 8002970: 687b ldr r3, [r7, #4] 8002972: 689b ldr r3, [r3, #8] 8002974: 2b05 cmp r3, #5 8002976: d115 bne.n 80029a4 8002978: 4b08 ldr r3, [pc, #32] @ (800299c ) 800297a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800297e: 4a07 ldr r2, [pc, #28] @ (800299c ) 8002980: f043 0304 orr.w r3, r3, #4 8002984: f8c2 3090 str.w r3, [r2, #144] @ 0x90 8002988: 4b04 ldr r3, [pc, #16] @ (800299c ) 800298a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800298e: 4a03 ldr r2, [pc, #12] @ (800299c ) 8002990: f043 0301 orr.w r3, r3, #1 8002994: f8c2 3090 str.w r3, [r2, #144] @ 0x90 8002998: e014 b.n 80029c4 800299a: bf00 nop 800299c: 40021000 .word 0x40021000 80029a0: 40007000 .word 0x40007000 80029a4: 4b9c ldr r3, [pc, #624] @ (8002c18 ) 80029a6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80029aa: 4a9b ldr r2, [pc, #620] @ (8002c18 ) 80029ac: f023 0301 bic.w r3, r3, #1 80029b0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 80029b4: 4b98 ldr r3, [pc, #608] @ (8002c18 ) 80029b6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80029ba: 4a97 ldr r2, [pc, #604] @ (8002c18 ) 80029bc: f023 0304 bic.w r3, r3, #4 80029c0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 #endif /* RCC_BDCR_LSESYSDIS */ /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80029c4: 687b ldr r3, [r7, #4] 80029c6: 689b ldr r3, [r3, #8] 80029c8: 2b00 cmp r3, #0 80029ca: d016 beq.n 80029fa { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80029cc: f7fe fda2 bl 8001514 80029d0: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80029d2: e00a b.n 80029ea { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80029d4: f7fe fd9e bl 8001514 80029d8: 4602 mov r2, r0 80029da: 693b ldr r3, [r7, #16] 80029dc: 1ad3 subs r3, r2, r3 80029de: f241 3288 movw r2, #5000 @ 0x1388 80029e2: 4293 cmp r3, r2 80029e4: d901 bls.n 80029ea { return HAL_TIMEOUT; 80029e6: 2303 movs r3, #3 80029e8: e12a b.n 8002c40 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80029ea: 4b8b ldr r3, [pc, #556] @ (8002c18 ) 80029ec: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80029f0: f003 0302 and.w r3, r3, #2 80029f4: 2b00 cmp r3, #0 80029f6: d0ed beq.n 80029d4 80029f8: e015 b.n 8002a26 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80029fa: f7fe fd8b bl 8001514 80029fe: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8002a00: e00a b.n 8002a18 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002a02: f7fe fd87 bl 8001514 8002a06: 4602 mov r2, r0 8002a08: 693b ldr r3, [r7, #16] 8002a0a: 1ad3 subs r3, r2, r3 8002a0c: f241 3288 movw r2, #5000 @ 0x1388 8002a10: 4293 cmp r3, r2 8002a12: d901 bls.n 8002a18 { return HAL_TIMEOUT; 8002a14: 2303 movs r3, #3 8002a16: e113 b.n 8002c40 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8002a18: 4b7f ldr r3, [pc, #508] @ (8002c18 ) 8002a1a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002a1e: f003 0302 and.w r3, r3, #2 8002a22: 2b00 cmp r3, #0 8002a24: d1ed bne.n 8002a02 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); #endif /* RCC_BDCR_LSESYSDIS */ } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 8002a26: 7ffb ldrb r3, [r7, #31] 8002a28: 2b01 cmp r3, #1 8002a2a: d105 bne.n 8002a38 { __HAL_RCC_PWR_CLK_DISABLE(); 8002a2c: 4b7a ldr r3, [pc, #488] @ (8002c18 ) 8002a2e: 6d9b ldr r3, [r3, #88] @ 0x58 8002a30: 4a79 ldr r2, [pc, #484] @ (8002c18 ) 8002a32: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8002a36: 6593 str r3, [r2, #88] @ 0x58 #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8002a38: 687b ldr r3, [r7, #4] 8002a3a: 6a9b ldr r3, [r3, #40] @ 0x28 8002a3c: 2b00 cmp r3, #0 8002a3e: f000 80fe beq.w 8002c3e { /* PLL On ? */ if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8002a42: 687b ldr r3, [r7, #4] 8002a44: 6a9b ldr r3, [r3, #40] @ 0x28 8002a46: 2b02 cmp r3, #2 8002a48: f040 80d0 bne.w 8002bec #endif /* RCC_PLLP_SUPPORT */ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Do nothing if PLL configuration is the unchanged */ pll_config = RCC->PLLCFGR; 8002a4c: 4b72 ldr r3, [pc, #456] @ (8002c18 ) 8002a4e: 68db ldr r3, [r3, #12] 8002a50: 617b str r3, [r7, #20] if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8002a52: 697b ldr r3, [r7, #20] 8002a54: f003 0203 and.w r2, r3, #3 8002a58: 687b ldr r3, [r7, #4] 8002a5a: 6adb ldr r3, [r3, #44] @ 0x2c 8002a5c: 429a cmp r2, r3 8002a5e: d130 bne.n 8002ac2 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 8002a60: 697b ldr r3, [r7, #20] 8002a62: f003 0270 and.w r2, r3, #112 @ 0x70 8002a66: 687b ldr r3, [r7, #4] 8002a68: 6b1b ldr r3, [r3, #48] @ 0x30 8002a6a: 3b01 subs r3, #1 8002a6c: 011b lsls r3, r3, #4 if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8002a6e: 429a cmp r2, r3 8002a70: d127 bne.n 8002ac2 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8002a72: 697b ldr r3, [r7, #20] 8002a74: f403 42fe and.w r2, r3, #32512 @ 0x7f00 8002a78: 687b ldr r3, [r7, #4] 8002a7a: 6b5b ldr r3, [r3, #52] @ 0x34 8002a7c: 021b lsls r3, r3, #8 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 8002a7e: 429a cmp r2, r3 8002a80: d11f bne.n 8002ac2 #if defined(RCC_PLLP_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) || #else (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) || 8002a82: 697b ldr r3, [r7, #20] 8002a84: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002a88: 687a ldr r2, [r7, #4] 8002a8a: 6b92 ldr r2, [r2, #56] @ 0x38 8002a8c: 2a07 cmp r2, #7 8002a8e: bf14 ite ne 8002a90: 2201 movne r2, #1 8002a92: 2200 moveq r2, #0 8002a94: b2d2 uxtb r2, r2 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8002a96: 4293 cmp r3, r2 8002a98: d113 bne.n 8002ac2 #endif #endif (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 8002a9a: 697b ldr r3, [r7, #20] 8002a9c: f403 02c0 and.w r2, r3, #6291456 @ 0x600000 8002aa0: 687b ldr r3, [r7, #4] 8002aa2: 6bdb ldr r3, [r3, #60] @ 0x3c 8002aa4: 085b lsrs r3, r3, #1 8002aa6: 3b01 subs r3, #1 8002aa8: 055b lsls r3, r3, #21 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) || 8002aaa: 429a cmp r2, r3 8002aac: d109 bne.n 8002ac2 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 8002aae: 697b ldr r3, [r7, #20] 8002ab0: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000 8002ab4: 687b ldr r3, [r7, #4] 8002ab6: 6c1b ldr r3, [r3, #64] @ 0x40 8002ab8: 085b lsrs r3, r3, #1 8002aba: 3b01 subs r3, #1 8002abc: 065b lsls r3, r3, #25 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 8002abe: 429a cmp r2, r3 8002ac0: d06e beq.n 8002ba0 { /* Check if the PLL is used as system clock or not */ if(sysclk_source != RCC_CFGR_SWS_PLL) 8002ac2: 69bb ldr r3, [r7, #24] 8002ac4: 2b0c cmp r3, #12 8002ac6: d069 beq.n 8002b9c { #if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT) /* Check if main PLL can be updated */ /* Not possible if the source is shared by other enabled PLLSAIx */ if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) 8002ac8: 4b53 ldr r3, [pc, #332] @ (8002c18 ) 8002aca: 681b ldr r3, [r3, #0] 8002acc: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8002ad0: 2b00 cmp r3, #0 8002ad2: d105 bne.n 8002ae0 #if defined(RCC_PLLSAI2_SUPPORT) || (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U) 8002ad4: 4b50 ldr r3, [pc, #320] @ (8002c18 ) 8002ad6: 681b ldr r3, [r3, #0] 8002ad8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8002adc: 2b00 cmp r3, #0 8002ade: d001 beq.n 8002ae4 #endif ) { return HAL_ERROR; 8002ae0: 2301 movs r3, #1 8002ae2: e0ad b.n 8002c40 } else #endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */ { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8002ae4: 4b4c ldr r3, [pc, #304] @ (8002c18 ) 8002ae6: 681b ldr r3, [r3, #0] 8002ae8: 4a4b ldr r2, [pc, #300] @ (8002c18 ) 8002aea: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8002aee: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002af0: f7fe fd10 bl 8001514 8002af4: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002af6: e008 b.n 8002b0a { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002af8: f7fe fd0c bl 8001514 8002afc: 4602 mov r2, r0 8002afe: 693b ldr r3, [r7, #16] 8002b00: 1ad3 subs r3, r2, r3 8002b02: 2b02 cmp r3, #2 8002b04: d901 bls.n 8002b0a { return HAL_TIMEOUT; 8002b06: 2303 movs r3, #3 8002b08: e09a b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002b0a: 4b43 ldr r3, [pc, #268] @ (8002c18 ) 8002b0c: 681b ldr r3, [r3, #0] 8002b0e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002b12: 2b00 cmp r3, #0 8002b14: d1f0 bne.n 8002af8 } } /* Configure the main PLL clock source, multiplication and division factors. */ #if defined(RCC_PLLP_SUPPORT) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8002b16: 4b40 ldr r3, [pc, #256] @ (8002c18 ) 8002b18: 68da ldr r2, [r3, #12] 8002b1a: 4b40 ldr r3, [pc, #256] @ (8002c1c ) 8002b1c: 4013 ands r3, r2 8002b1e: 687a ldr r2, [r7, #4] 8002b20: 6ad1 ldr r1, [r2, #44] @ 0x2c 8002b22: 687a ldr r2, [r7, #4] 8002b24: 6b12 ldr r2, [r2, #48] @ 0x30 8002b26: 3a01 subs r2, #1 8002b28: 0112 lsls r2, r2, #4 8002b2a: 4311 orrs r1, r2 8002b2c: 687a ldr r2, [r7, #4] 8002b2e: 6b52 ldr r2, [r2, #52] @ 0x34 8002b30: 0212 lsls r2, r2, #8 8002b32: 4311 orrs r1, r2 8002b34: 687a ldr r2, [r7, #4] 8002b36: 6bd2 ldr r2, [r2, #60] @ 0x3c 8002b38: 0852 lsrs r2, r2, #1 8002b3a: 3a01 subs r2, #1 8002b3c: 0552 lsls r2, r2, #21 8002b3e: 4311 orrs r1, r2 8002b40: 687a ldr r2, [r7, #4] 8002b42: 6c12 ldr r2, [r2, #64] @ 0x40 8002b44: 0852 lsrs r2, r2, #1 8002b46: 3a01 subs r2, #1 8002b48: 0652 lsls r2, r2, #25 8002b4a: 4311 orrs r1, r2 8002b4c: 687a ldr r2, [r7, #4] 8002b4e: 6b92 ldr r2, [r2, #56] @ 0x38 8002b50: 0912 lsrs r2, r2, #4 8002b52: 0452 lsls r2, r2, #17 8002b54: 430a orrs r2, r1 8002b56: 4930 ldr r1, [pc, #192] @ (8002c18 ) 8002b58: 4313 orrs r3, r2 8002b5a: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); #endif /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8002b5c: 4b2e ldr r3, [pc, #184] @ (8002c18 ) 8002b5e: 681b ldr r3, [r3, #0] 8002b60: 4a2d ldr r2, [pc, #180] @ (8002c18 ) 8002b62: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8002b66: 6013 str r3, [r2, #0] /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 8002b68: 4b2b ldr r3, [pc, #172] @ (8002c18 ) 8002b6a: 68db ldr r3, [r3, #12] 8002b6c: 4a2a ldr r2, [pc, #168] @ (8002c18 ) 8002b6e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8002b72: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002b74: f7fe fcce bl 8001514 8002b78: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002b7a: e008 b.n 8002b8e { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002b7c: f7fe fcca bl 8001514 8002b80: 4602 mov r2, r0 8002b82: 693b ldr r3, [r7, #16] 8002b84: 1ad3 subs r3, r2, r3 8002b86: 2b02 cmp r3, #2 8002b88: d901 bls.n 8002b8e { return HAL_TIMEOUT; 8002b8a: 2303 movs r3, #3 8002b8c: e058 b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002b8e: 4b22 ldr r3, [pc, #136] @ (8002c18 ) 8002b90: 681b ldr r3, [r3, #0] 8002b92: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002b96: 2b00 cmp r3, #0 8002b98: d0f0 beq.n 8002b7c if(sysclk_source != RCC_CFGR_SWS_PLL) 8002b9a: e050 b.n 8002c3e } } else { /* PLL is already used as System core clock */ return HAL_ERROR; 8002b9c: 2301 movs r3, #1 8002b9e: e04f b.n 8002c40 } else { /* PLL configuration is unchanged */ /* Re-enable PLL if it was disabled (ie. low power mode) */ if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002ba0: 4b1d ldr r3, [pc, #116] @ (8002c18 ) 8002ba2: 681b ldr r3, [r3, #0] 8002ba4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002ba8: 2b00 cmp r3, #0 8002baa: d148 bne.n 8002c3e { /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8002bac: 4b1a ldr r3, [pc, #104] @ (8002c18 ) 8002bae: 681b ldr r3, [r3, #0] 8002bb0: 4a19 ldr r2, [pc, #100] @ (8002c18 ) 8002bb2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8002bb6: 6013 str r3, [r2, #0] /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 8002bb8: 4b17 ldr r3, [pc, #92] @ (8002c18 ) 8002bba: 68db ldr r3, [r3, #12] 8002bbc: 4a16 ldr r2, [pc, #88] @ (8002c18 ) 8002bbe: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8002bc2: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002bc4: f7fe fca6 bl 8001514 8002bc8: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002bca: e008 b.n 8002bde { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002bcc: f7fe fca2 bl 8001514 8002bd0: 4602 mov r2, r0 8002bd2: 693b ldr r3, [r7, #16] 8002bd4: 1ad3 subs r3, r2, r3 8002bd6: 2b02 cmp r3, #2 8002bd8: d901 bls.n 8002bde { return HAL_TIMEOUT; 8002bda: 2303 movs r3, #3 8002bdc: e030 b.n 8002c40 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002bde: 4b0e ldr r3, [pc, #56] @ (8002c18 ) 8002be0: 681b ldr r3, [r3, #0] 8002be2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002be6: 2b00 cmp r3, #0 8002be8: d0f0 beq.n 8002bcc 8002bea: e028 b.n 8002c3e } } else { /* Check that PLL is not used as system clock or not */ if(sysclk_source != RCC_CFGR_SWS_PLL) 8002bec: 69bb ldr r3, [r7, #24] 8002bee: 2b0c cmp r3, #12 8002bf0: d023 beq.n 8002c3a { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8002bf2: 4b09 ldr r3, [pc, #36] @ (8002c18 ) 8002bf4: 681b ldr r3, [r3, #0] 8002bf6: 4a08 ldr r2, [pc, #32] @ (8002c18 ) 8002bf8: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8002bfc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002bfe: f7fe fc89 bl 8001514 8002c02: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002c04: e00c b.n 8002c20 { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002c06: f7fe fc85 bl 8001514 8002c0a: 4602 mov r2, r0 8002c0c: 693b ldr r3, [r7, #16] 8002c0e: 1ad3 subs r3, r2, r3 8002c10: 2b02 cmp r3, #2 8002c12: d905 bls.n 8002c20 { return HAL_TIMEOUT; 8002c14: 2303 movs r3, #3 8002c16: e013 b.n 8002c40 8002c18: 40021000 .word 0x40021000 8002c1c: f99d808c .word 0xf99d808c while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002c20: 4b09 ldr r3, [pc, #36] @ (8002c48 ) 8002c22: 681b ldr r3, [r3, #0] 8002c24: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002c28: 2b00 cmp r3, #0 8002c2a: d1ec bne.n 8002c06 } } /* Unselect main PLL clock source and disable main PLL outputs to save power */ #if defined(RCC_PLLSAI2_SUPPORT) RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); 8002c2c: 4b06 ldr r3, [pc, #24] @ (8002c48 ) 8002c2e: 68da ldr r2, [r3, #12] 8002c30: 4905 ldr r1, [pc, #20] @ (8002c48 ) 8002c32: 4b06 ldr r3, [pc, #24] @ (8002c4c ) 8002c34: 4013 ands r3, r2 8002c36: 60cb str r3, [r1, #12] 8002c38: e001 b.n 8002c3e #endif /* RCC_PLLSAI2_SUPPORT */ } else { /* PLL is already used as System core clock */ return HAL_ERROR; 8002c3a: 2301 movs r3, #1 8002c3c: e000 b.n 8002c40 } } } return HAL_OK; 8002c3e: 2300 movs r3, #0 } 8002c40: 4618 mov r0, r3 8002c42: 3720 adds r7, #32 8002c44: 46bd mov sp, r7 8002c46: bd80 pop {r7, pc} 8002c48: 40021000 .word 0x40021000 8002c4c: feeefffc .word 0xfeeefffc 08002c50 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8002c50: b580 push {r7, lr} 8002c52: b084 sub sp, #16 8002c54: af00 add r7, sp, #0 8002c56: 6078 str r0, [r7, #4] 8002c58: 6039 str r1, [r7, #0] uint32_t hpre = RCC_SYSCLK_DIV1; #endif HAL_StatusTypeDef status; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8002c5a: 687b ldr r3, [r7, #4] 8002c5c: 2b00 cmp r3, #0 8002c5e: d101 bne.n 8002c64 { return HAL_ERROR; 8002c60: 2301 movs r3, #1 8002c62: e0e7 b.n 8002e34 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8002c64: 4b75 ldr r3, [pc, #468] @ (8002e3c ) 8002c66: 681b ldr r3, [r3, #0] 8002c68: f003 0307 and.w r3, r3, #7 8002c6c: 683a ldr r2, [r7, #0] 8002c6e: 429a cmp r2, r3 8002c70: d910 bls.n 8002c94 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8002c72: 4b72 ldr r3, [pc, #456] @ (8002e3c ) 8002c74: 681b ldr r3, [r3, #0] 8002c76: f023 0207 bic.w r2, r3, #7 8002c7a: 4970 ldr r1, [pc, #448] @ (8002e3c ) 8002c7c: 683b ldr r3, [r7, #0] 8002c7e: 4313 orrs r3, r2 8002c80: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8002c82: 4b6e ldr r3, [pc, #440] @ (8002e3c ) 8002c84: 681b ldr r3, [r3, #0] 8002c86: f003 0307 and.w r3, r3, #7 8002c8a: 683a ldr r2, [r7, #0] 8002c8c: 429a cmp r2, r3 8002c8e: d001 beq.n 8002c94 { return HAL_ERROR; 8002c90: 2301 movs r3, #1 8002c92: e0cf b.n 8002e34 } } /*----------------- HCLK Configuration prior to SYSCLK----------------------*/ /* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8002c94: 687b ldr r3, [r7, #4] 8002c96: 681b ldr r3, [r3, #0] 8002c98: f003 0302 and.w r3, r3, #2 8002c9c: 2b00 cmp r3, #0 8002c9e: d010 beq.n 8002cc2 { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)) 8002ca0: 687b ldr r3, [r7, #4] 8002ca2: 689a ldr r2, [r3, #8] 8002ca4: 4b66 ldr r3, [pc, #408] @ (8002e40 ) 8002ca6: 689b ldr r3, [r3, #8] 8002ca8: f003 03f0 and.w r3, r3, #240 @ 0xf0 8002cac: 429a cmp r2, r3 8002cae: d908 bls.n 8002cc2 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8002cb0: 4b63 ldr r3, [pc, #396] @ (8002e40 ) 8002cb2: 689b ldr r3, [r3, #8] 8002cb4: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8002cb8: 687b ldr r3, [r7, #4] 8002cba: 689b ldr r3, [r3, #8] 8002cbc: 4960 ldr r1, [pc, #384] @ (8002e40 ) 8002cbe: 4313 orrs r3, r2 8002cc0: 608b str r3, [r1, #8] } } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8002cc2: 687b ldr r3, [r7, #4] 8002cc4: 681b ldr r3, [r3, #0] 8002cc6: f003 0301 and.w r3, r3, #1 8002cca: 2b00 cmp r3, #0 8002ccc: d04c beq.n 8002d68 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* PLL is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8002cce: 687b ldr r3, [r7, #4] 8002cd0: 685b ldr r3, [r3, #4] 8002cd2: 2b03 cmp r3, #3 8002cd4: d107 bne.n 8002ce6 { /* Check the PLL ready flag */ if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002cd6: 4b5a ldr r3, [pc, #360] @ (8002e40 ) 8002cd8: 681b ldr r3, [r3, #0] 8002cda: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002cde: 2b00 cmp r3, #0 8002ce0: d121 bne.n 8002d26 { return HAL_ERROR; 8002ce2: 2301 movs r3, #1 8002ce4: e0a6 b.n 8002e34 #endif } else { /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8002ce6: 687b ldr r3, [r7, #4] 8002ce8: 685b ldr r3, [r3, #4] 8002cea: 2b02 cmp r3, #2 8002cec: d107 bne.n 8002cfe { /* Check the HSE ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002cee: 4b54 ldr r3, [pc, #336] @ (8002e40 ) 8002cf0: 681b ldr r3, [r3, #0] 8002cf2: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002cf6: 2b00 cmp r3, #0 8002cf8: d115 bne.n 8002d26 { return HAL_ERROR; 8002cfa: 2301 movs r3, #1 8002cfc: e09a b.n 8002e34 } } /* MSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) 8002cfe: 687b ldr r3, [r7, #4] 8002d00: 685b ldr r3, [r3, #4] 8002d02: 2b00 cmp r3, #0 8002d04: d107 bne.n 8002d16 { /* Check the MSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) 8002d06: 4b4e ldr r3, [pc, #312] @ (8002e40 ) 8002d08: 681b ldr r3, [r3, #0] 8002d0a: f003 0302 and.w r3, r3, #2 8002d0e: 2b00 cmp r3, #0 8002d10: d109 bne.n 8002d26 { return HAL_ERROR; 8002d12: 2301 movs r3, #1 8002d14: e08e b.n 8002e34 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002d16: 4b4a ldr r3, [pc, #296] @ (8002e40 ) 8002d18: 681b ldr r3, [r3, #0] 8002d1a: f403 6380 and.w r3, r3, #1024 @ 0x400 8002d1e: 2b00 cmp r3, #0 8002d20: d101 bne.n 8002d26 { return HAL_ERROR; 8002d22: 2301 movs r3, #1 8002d24: e086 b.n 8002e34 } #endif } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8002d26: 4b46 ldr r3, [pc, #280] @ (8002e40 ) 8002d28: 689b ldr r3, [r3, #8] 8002d2a: f023 0203 bic.w r2, r3, #3 8002d2e: 687b ldr r3, [r7, #4] 8002d30: 685b ldr r3, [r3, #4] 8002d32: 4943 ldr r1, [pc, #268] @ (8002e40 ) 8002d34: 4313 orrs r3, r2 8002d36: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002d38: f7fe fbec bl 8001514 8002d3c: 60f8 str r0, [r7, #12] while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002d3e: e00a b.n 8002d56 { if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8002d40: f7fe fbe8 bl 8001514 8002d44: 4602 mov r2, r0 8002d46: 68fb ldr r3, [r7, #12] 8002d48: 1ad3 subs r3, r2, r3 8002d4a: f241 3288 movw r2, #5000 @ 0x1388 8002d4e: 4293 cmp r3, r2 8002d50: d901 bls.n 8002d56 { return HAL_TIMEOUT; 8002d52: 2303 movs r3, #3 8002d54: e06e b.n 8002e34 while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002d56: 4b3a ldr r3, [pc, #232] @ (8002e40 ) 8002d58: 689b ldr r3, [r3, #8] 8002d5a: f003 020c and.w r2, r3, #12 8002d5e: 687b ldr r3, [r7, #4] 8002d60: 685b ldr r3, [r3, #4] 8002d62: 009b lsls r3, r3, #2 8002d64: 429a cmp r2, r3 8002d66: d1eb bne.n 8002d40 } #endif /*----------------- HCLK Configuration after SYSCLK-------------------------*/ /* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8002d68: 687b ldr r3, [r7, #4] 8002d6a: 681b ldr r3, [r3, #0] 8002d6c: f003 0302 and.w r3, r3, #2 8002d70: 2b00 cmp r3, #0 8002d72: d010 beq.n 8002d96 { if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)) 8002d74: 687b ldr r3, [r7, #4] 8002d76: 689a ldr r2, [r3, #8] 8002d78: 4b31 ldr r3, [pc, #196] @ (8002e40 ) 8002d7a: 689b ldr r3, [r3, #8] 8002d7c: f003 03f0 and.w r3, r3, #240 @ 0xf0 8002d80: 429a cmp r2, r3 8002d82: d208 bcs.n 8002d96 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8002d84: 4b2e ldr r3, [pc, #184] @ (8002e40 ) 8002d86: 689b ldr r3, [r3, #8] 8002d88: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 689b ldr r3, [r3, #8] 8002d90: 492b ldr r1, [pc, #172] @ (8002e40 ) 8002d92: 4313 orrs r3, r2 8002d94: 608b str r3, [r1, #8] } } /* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8002d96: 4b29 ldr r3, [pc, #164] @ (8002e3c ) 8002d98: 681b ldr r3, [r3, #0] 8002d9a: f003 0307 and.w r3, r3, #7 8002d9e: 683a ldr r2, [r7, #0] 8002da0: 429a cmp r2, r3 8002da2: d210 bcs.n 8002dc6 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8002da4: 4b25 ldr r3, [pc, #148] @ (8002e3c ) 8002da6: 681b ldr r3, [r3, #0] 8002da8: f023 0207 bic.w r2, r3, #7 8002dac: 4923 ldr r1, [pc, #140] @ (8002e3c ) 8002dae: 683b ldr r3, [r7, #0] 8002db0: 4313 orrs r3, r2 8002db2: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8002db4: 4b21 ldr r3, [pc, #132] @ (8002e3c ) 8002db6: 681b ldr r3, [r3, #0] 8002db8: f003 0307 and.w r3, r3, #7 8002dbc: 683a ldr r2, [r7, #0] 8002dbe: 429a cmp r2, r3 8002dc0: d001 beq.n 8002dc6 { return HAL_ERROR; 8002dc2: 2301 movs r3, #1 8002dc4: e036 b.n 8002e34 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8002dc6: 687b ldr r3, [r7, #4] 8002dc8: 681b ldr r3, [r3, #0] 8002dca: f003 0304 and.w r3, r3, #4 8002dce: 2b00 cmp r3, #0 8002dd0: d008 beq.n 8002de4 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8002dd2: 4b1b ldr r3, [pc, #108] @ (8002e40 ) 8002dd4: 689b ldr r3, [r3, #8] 8002dd6: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8002dda: 687b ldr r3, [r7, #4] 8002ddc: 68db ldr r3, [r3, #12] 8002dde: 4918 ldr r1, [pc, #96] @ (8002e40 ) 8002de0: 4313 orrs r3, r2 8002de2: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8002de4: 687b ldr r3, [r7, #4] 8002de6: 681b ldr r3, [r3, #0] 8002de8: f003 0308 and.w r3, r3, #8 8002dec: 2b00 cmp r3, #0 8002dee: d009 beq.n 8002e04 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8002df0: 4b13 ldr r3, [pc, #76] @ (8002e40 ) 8002df2: 689b ldr r3, [r3, #8] 8002df4: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8002df8: 687b ldr r3, [r7, #4] 8002dfa: 691b ldr r3, [r3, #16] 8002dfc: 00db lsls r3, r3, #3 8002dfe: 4910 ldr r1, [pc, #64] @ (8002e40 ) 8002e00: 4313 orrs r3, r2 8002e02: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 8002e04: f000 f824 bl 8002e50 8002e08: 4602 mov r2, r0 8002e0a: 4b0d ldr r3, [pc, #52] @ (8002e40 ) 8002e0c: 689b ldr r3, [r3, #8] 8002e0e: 091b lsrs r3, r3, #4 8002e10: f003 030f and.w r3, r3, #15 8002e14: 490b ldr r1, [pc, #44] @ (8002e44 ) 8002e16: 5ccb ldrb r3, [r1, r3] 8002e18: f003 031f and.w r3, r3, #31 8002e1c: fa22 f303 lsr.w r3, r2, r3 8002e20: 4a09 ldr r2, [pc, #36] @ (8002e48 ) 8002e22: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ status = HAL_InitTick(uwTickPrio); 8002e24: 4b09 ldr r3, [pc, #36] @ (8002e4c ) 8002e26: 681b ldr r3, [r3, #0] 8002e28: 4618 mov r0, r3 8002e2a: f7fe fa4f bl 80012cc 8002e2e: 4603 mov r3, r0 8002e30: 72fb strb r3, [r7, #11] return status; 8002e32: 7afb ldrb r3, [r7, #11] } 8002e34: 4618 mov r0, r3 8002e36: 3710 adds r7, #16 8002e38: 46bd mov sp, r7 8002e3a: bd80 pop {r7, pc} 8002e3c: 40022000 .word 0x40022000 8002e40: 40021000 .word 0x40021000 8002e44: 08007eac .word 0x08007eac 8002e48: 20000000 .word 0x20000000 8002e4c: 20000004 .word 0x20000004 08002e50 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8002e50: b480 push {r7} 8002e52: b089 sub sp, #36 @ 0x24 8002e54: af00 add r7, sp, #0 uint32_t msirange = 0U, sysclockfreq = 0U; 8002e56: 2300 movs r3, #0 8002e58: 61fb str r3, [r7, #28] 8002e5a: 2300 movs r3, #0 8002e5c: 61bb str r3, [r7, #24] uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */ uint32_t sysclk_source, pll_oscsource; sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002e5e: 4b3e ldr r3, [pc, #248] @ (8002f58 ) 8002e60: 689b ldr r3, [r3, #8] 8002e62: f003 030c and.w r3, r3, #12 8002e66: 613b str r3, [r7, #16] pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); 8002e68: 4b3b ldr r3, [pc, #236] @ (8002f58 ) 8002e6a: 68db ldr r3, [r3, #12] 8002e6c: f003 0303 and.w r3, r3, #3 8002e70: 60fb str r3, [r7, #12] if((sysclk_source == RCC_CFGR_SWS_MSI) || 8002e72: 693b ldr r3, [r7, #16] 8002e74: 2b00 cmp r3, #0 8002e76: d005 beq.n 8002e84 8002e78: 693b ldr r3, [r7, #16] 8002e7a: 2b0c cmp r3, #12 8002e7c: d121 bne.n 8002ec2 ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI))) 8002e7e: 68fb ldr r3, [r7, #12] 8002e80: 2b01 cmp r3, #1 8002e82: d11e bne.n 8002ec2 { /* MSI or PLL with MSI source used as system clock source */ /* Get SYSCLK source */ if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U) 8002e84: 4b34 ldr r3, [pc, #208] @ (8002f58 ) 8002e86: 681b ldr r3, [r3, #0] 8002e88: f003 0308 and.w r3, r3, #8 8002e8c: 2b00 cmp r3, #0 8002e8e: d107 bne.n 8002ea0 { /* MSISRANGE from RCC_CSR applies */ msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; 8002e90: 4b31 ldr r3, [pc, #196] @ (8002f58 ) 8002e92: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8002e96: 0a1b lsrs r3, r3, #8 8002e98: f003 030f and.w r3, r3, #15 8002e9c: 61fb str r3, [r7, #28] 8002e9e: e005 b.n 8002eac } else { /* MSIRANGE from RCC_CR applies */ msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; 8002ea0: 4b2d ldr r3, [pc, #180] @ (8002f58 ) 8002ea2: 681b ldr r3, [r3, #0] 8002ea4: 091b lsrs r3, r3, #4 8002ea6: f003 030f and.w r3, r3, #15 8002eaa: 61fb str r3, [r7, #28] } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; 8002eac: 4a2b ldr r2, [pc, #172] @ (8002f5c ) 8002eae: 69fb ldr r3, [r7, #28] 8002eb0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8002eb4: 61fb str r3, [r7, #28] if(sysclk_source == RCC_CFGR_SWS_MSI) 8002eb6: 693b ldr r3, [r7, #16] 8002eb8: 2b00 cmp r3, #0 8002eba: d10d bne.n 8002ed8 { /* MSI used as system clock source */ sysclockfreq = msirange; 8002ebc: 69fb ldr r3, [r7, #28] 8002ebe: 61bb str r3, [r7, #24] if(sysclk_source == RCC_CFGR_SWS_MSI) 8002ec0: e00a b.n 8002ed8 } } else if(sysclk_source == RCC_CFGR_SWS_HSI) 8002ec2: 693b ldr r3, [r7, #16] 8002ec4: 2b04 cmp r3, #4 8002ec6: d102 bne.n 8002ece { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; 8002ec8: 4b25 ldr r3, [pc, #148] @ (8002f60 ) 8002eca: 61bb str r3, [r7, #24] 8002ecc: e004 b.n 8002ed8 } else if(sysclk_source == RCC_CFGR_SWS_HSE) 8002ece: 693b ldr r3, [r7, #16] 8002ed0: 2b08 cmp r3, #8 8002ed2: d101 bne.n 8002ed8 { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8002ed4: 4b23 ldr r3, [pc, #140] @ (8002f64 ) 8002ed6: 61bb str r3, [r7, #24] else { /* unexpected case: sysclockfreq at 0 */ } if(sysclk_source == RCC_CFGR_SWS_PLL) 8002ed8: 693b ldr r3, [r7, #16] 8002eda: 2b0c cmp r3, #12 8002edc: d134 bne.n 8002f48 /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8002ede: 4b1e ldr r3, [pc, #120] @ (8002f58 ) 8002ee0: 68db ldr r3, [r3, #12] 8002ee2: f003 0303 and.w r3, r3, #3 8002ee6: 60bb str r3, [r7, #8] switch (pllsource) 8002ee8: 68bb ldr r3, [r7, #8] 8002eea: 2b02 cmp r3, #2 8002eec: d003 beq.n 8002ef6 8002eee: 68bb ldr r3, [r7, #8] 8002ef0: 2b03 cmp r3, #3 8002ef2: d003 beq.n 8002efc 8002ef4: e005 b.n 8002f02 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllvco = HSI_VALUE; 8002ef6: 4b1a ldr r3, [pc, #104] @ (8002f60 ) 8002ef8: 617b str r3, [r7, #20] break; 8002efa: e005 b.n 8002f08 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = HSE_VALUE; 8002efc: 4b19 ldr r3, [pc, #100] @ (8002f64 ) 8002efe: 617b str r3, [r7, #20] break; 8002f00: e002 b.n 8002f08 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: pllvco = msirange; 8002f02: 69fb ldr r3, [r7, #28] 8002f04: 617b str r3, [r7, #20] break; 8002f06: bf00 nop } pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8002f08: 4b13 ldr r3, [pc, #76] @ (8002f58 ) 8002f0a: 68db ldr r3, [r3, #12] 8002f0c: 091b lsrs r3, r3, #4 8002f0e: f003 0307 and.w r3, r3, #7 8002f12: 3301 adds r3, #1 8002f14: 607b str r3, [r7, #4] pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm; 8002f16: 4b10 ldr r3, [pc, #64] @ (8002f58 ) 8002f18: 68db ldr r3, [r3, #12] 8002f1a: 0a1b lsrs r3, r3, #8 8002f1c: f003 037f and.w r3, r3, #127 @ 0x7f 8002f20: 697a ldr r2, [r7, #20] 8002f22: fb03 f202 mul.w r2, r3, r2 8002f26: 687b ldr r3, [r7, #4] 8002f28: fbb2 f3f3 udiv r3, r2, r3 8002f2c: 617b str r3, [r7, #20] pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8002f2e: 4b0a ldr r3, [pc, #40] @ (8002f58 ) 8002f30: 68db ldr r3, [r3, #12] 8002f32: 0e5b lsrs r3, r3, #25 8002f34: f003 0303 and.w r3, r3, #3 8002f38: 3301 adds r3, #1 8002f3a: 005b lsls r3, r3, #1 8002f3c: 603b str r3, [r7, #0] sysclockfreq = pllvco / pllr; 8002f3e: 697a ldr r2, [r7, #20] 8002f40: 683b ldr r3, [r7, #0] 8002f42: fbb2 f3f3 udiv r3, r2, r3 8002f46: 61bb str r3, [r7, #24] } return sysclockfreq; 8002f48: 69bb ldr r3, [r7, #24] } 8002f4a: 4618 mov r0, r3 8002f4c: 3724 adds r7, #36 @ 0x24 8002f4e: 46bd mov sp, r7 8002f50: f85d 7b04 ldr.w r7, [sp], #4 8002f54: 4770 bx lr 8002f56: bf00 nop 8002f58: 40021000 .word 0x40021000 8002f5c: 08007ec4 .word 0x08007ec4 8002f60: 00f42400 .word 0x00f42400 8002f64: 007a1200 .word 0x007a1200 08002f68 : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8002f68: b480 push {r7} 8002f6a: af00 add r7, sp, #0 return SystemCoreClock; 8002f6c: 4b03 ldr r3, [pc, #12] @ (8002f7c ) 8002f6e: 681b ldr r3, [r3, #0] } 8002f70: 4618 mov r0, r3 8002f72: 46bd mov sp, r7 8002f74: f85d 7b04 ldr.w r7, [sp], #4 8002f78: 4770 bx lr 8002f7a: bf00 nop 8002f7c: 20000000 .word 0x20000000 08002f80 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8002f80: b580 push {r7, lr} 8002f82: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); 8002f84: f7ff fff0 bl 8002f68 8002f88: 4602 mov r2, r0 8002f8a: 4b06 ldr r3, [pc, #24] @ (8002fa4 ) 8002f8c: 689b ldr r3, [r3, #8] 8002f8e: 0a1b lsrs r3, r3, #8 8002f90: f003 0307 and.w r3, r3, #7 8002f94: 4904 ldr r1, [pc, #16] @ (8002fa8 ) 8002f96: 5ccb ldrb r3, [r1, r3] 8002f98: f003 031f and.w r3, r3, #31 8002f9c: fa22 f303 lsr.w r3, r2, r3 } 8002fa0: 4618 mov r0, r3 8002fa2: bd80 pop {r7, pc} 8002fa4: 40021000 .word 0x40021000 8002fa8: 08007ebc .word 0x08007ebc 08002fac : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8002fac: b580 push {r7, lr} 8002fae: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); 8002fb0: f7ff ffda bl 8002f68 8002fb4: 4602 mov r2, r0 8002fb6: 4b06 ldr r3, [pc, #24] @ (8002fd0 ) 8002fb8: 689b ldr r3, [r3, #8] 8002fba: 0adb lsrs r3, r3, #11 8002fbc: f003 0307 and.w r3, r3, #7 8002fc0: 4904 ldr r1, [pc, #16] @ (8002fd4 ) 8002fc2: 5ccb ldrb r3, [r1, r3] 8002fc4: f003 031f and.w r3, r3, #31 8002fc8: fa22 f303 lsr.w r3, r2, r3 } 8002fcc: 4618 mov r0, r3 8002fce: bd80 pop {r7, pc} 8002fd0: 40021000 .word 0x40021000 8002fd4: 08007ebc .word 0x08007ebc 08002fd8 : * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8002fd8: b480 push {r7} 8002fda: b083 sub sp, #12 8002fdc: af00 add r7, sp, #0 8002fde: 6078 str r0, [r7, #4] 8002fe0: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(RCC_ClkInitStruct != (void *)NULL); assert_param(pFLatency != (void *)NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 8002fe2: 687b ldr r3, [r7, #4] 8002fe4: 220f movs r2, #15 8002fe6: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); 8002fe8: 4b12 ldr r3, [pc, #72] @ (8003034 ) 8002fea: 689b ldr r3, [r3, #8] 8002fec: f003 0203 and.w r2, r3, #3 8002ff0: 687b ldr r3, [r7, #4] 8002ff2: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); 8002ff4: 4b0f ldr r3, [pc, #60] @ (8003034 ) 8002ff6: 689b ldr r3, [r3, #8] 8002ff8: f003 02f0 and.w r2, r3, #240 @ 0xf0 8002ffc: 687b ldr r3, [r7, #4] 8002ffe: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); 8003000: 4b0c ldr r3, [pc, #48] @ (8003034 ) 8003002: 689b ldr r3, [r3, #8] 8003004: f403 62e0 and.w r2, r3, #1792 @ 0x700 8003008: 687b ldr r3, [r7, #4] 800300a: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); 800300c: 4b09 ldr r3, [pc, #36] @ (8003034 ) 800300e: 689b ldr r3, [r3, #8] 8003010: 08db lsrs r3, r3, #3 8003012: f403 62e0 and.w r2, r3, #1792 @ 0x700 8003016: 687b ldr r3, [r7, #4] 8003018: 611a str r2, [r3, #16] /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = __HAL_FLASH_GET_LATENCY(); 800301a: 4b07 ldr r3, [pc, #28] @ (8003038 ) 800301c: 681b ldr r3, [r3, #0] 800301e: f003 0207 and.w r2, r3, #7 8003022: 683b ldr r3, [r7, #0] 8003024: 601a str r2, [r3, #0] } 8003026: bf00 nop 8003028: 370c adds r7, #12 800302a: 46bd mov sp, r7 800302c: f85d 7b04 ldr.w r7, [sp], #4 8003030: 4770 bx lr 8003032: bf00 nop 8003034: 40021000 .word 0x40021000 8003038: 40022000 .word 0x40022000 0800303c : voltage range. * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) { 800303c: b580 push {r7, lr} 800303e: b086 sub sp, #24 8003040: af00 add r7, sp, #0 8003042: 6078 str r0, [r7, #4] uint32_t vos; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ 8003044: 2300 movs r3, #0 8003046: 613b str r3, [r7, #16] if(__HAL_RCC_PWR_IS_CLK_ENABLED()) 8003048: 4b2a ldr r3, [pc, #168] @ (80030f4 ) 800304a: 6d9b ldr r3, [r3, #88] @ 0x58 800304c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003050: 2b00 cmp r3, #0 8003052: d003 beq.n 800305c { vos = HAL_PWREx_GetVoltageRange(); 8003054: f7ff f8f0 bl 8002238 8003058: 6178 str r0, [r7, #20] 800305a: e014 b.n 8003086 } else { __HAL_RCC_PWR_CLK_ENABLE(); 800305c: 4b25 ldr r3, [pc, #148] @ (80030f4 ) 800305e: 6d9b ldr r3, [r3, #88] @ 0x58 8003060: 4a24 ldr r2, [pc, #144] @ (80030f4 ) 8003062: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003066: 6593 str r3, [r2, #88] @ 0x58 8003068: 4b22 ldr r3, [pc, #136] @ (80030f4 ) 800306a: 6d9b ldr r3, [r3, #88] @ 0x58 800306c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003070: 60fb str r3, [r7, #12] 8003072: 68fb ldr r3, [r7, #12] vos = HAL_PWREx_GetVoltageRange(); 8003074: f7ff f8e0 bl 8002238 8003078: 6178 str r0, [r7, #20] __HAL_RCC_PWR_CLK_DISABLE(); 800307a: 4b1e ldr r3, [pc, #120] @ (80030f4 ) 800307c: 6d9b ldr r3, [r3, #88] @ 0x58 800307e: 4a1d ldr r2, [pc, #116] @ (80030f4 ) 8003080: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8003084: 6593 str r3, [r2, #88] @ 0x58 } if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) 8003086: 697b ldr r3, [r7, #20] 8003088: f5b3 7f00 cmp.w r3, #512 @ 0x200 800308c: d10b bne.n 80030a6 { if(msirange > RCC_MSIRANGE_8) 800308e: 687b ldr r3, [r7, #4] 8003090: 2b80 cmp r3, #128 @ 0x80 8003092: d919 bls.n 80030c8 { /* MSI > 16Mhz */ if(msirange > RCC_MSIRANGE_10) 8003094: 687b ldr r3, [r7, #4] 8003096: 2ba0 cmp r3, #160 @ 0xa0 8003098: d902 bls.n 80030a0 { /* MSI 48Mhz */ latency = FLASH_LATENCY_2; /* 2WS */ 800309a: 2302 movs r3, #2 800309c: 613b str r3, [r7, #16] 800309e: e013 b.n 80030c8 } else { /* MSI 24Mhz or 32Mhz */ latency = FLASH_LATENCY_1; /* 1WS */ 80030a0: 2301 movs r3, #1 80030a2: 613b str r3, [r7, #16] 80030a4: e010 b.n 80030c8 latency = FLASH_LATENCY_1; /* 1WS */ } /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ } #else if(msirange > RCC_MSIRANGE_8) 80030a6: 687b ldr r3, [r7, #4] 80030a8: 2b80 cmp r3, #128 @ 0x80 80030aa: d902 bls.n 80030b2 { /* MSI > 16Mhz */ latency = FLASH_LATENCY_3; /* 3WS */ 80030ac: 2303 movs r3, #3 80030ae: 613b str r3, [r7, #16] 80030b0: e00a b.n 80030c8 } else { if(msirange == RCC_MSIRANGE_8) 80030b2: 687b ldr r3, [r7, #4] 80030b4: 2b80 cmp r3, #128 @ 0x80 80030b6: d102 bne.n 80030be { /* MSI 16Mhz */ latency = FLASH_LATENCY_2; /* 2WS */ 80030b8: 2302 movs r3, #2 80030ba: 613b str r3, [r7, #16] 80030bc: e004 b.n 80030c8 } else if(msirange == RCC_MSIRANGE_7) 80030be: 687b ldr r3, [r7, #4] 80030c0: 2b70 cmp r3, #112 @ 0x70 80030c2: d101 bne.n 80030c8 { /* MSI 8Mhz */ latency = FLASH_LATENCY_1; /* 1WS */ 80030c4: 2301 movs r3, #1 80030c6: 613b str r3, [r7, #16] } } #endif } __HAL_FLASH_SET_LATENCY(latency); 80030c8: 4b0b ldr r3, [pc, #44] @ (80030f8 ) 80030ca: 681b ldr r3, [r3, #0] 80030cc: f023 0207 bic.w r2, r3, #7 80030d0: 4909 ldr r1, [pc, #36] @ (80030f8 ) 80030d2: 693b ldr r3, [r7, #16] 80030d4: 4313 orrs r3, r2 80030d6: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != latency) 80030d8: 4b07 ldr r3, [pc, #28] @ (80030f8 ) 80030da: 681b ldr r3, [r3, #0] 80030dc: f003 0307 and.w r3, r3, #7 80030e0: 693a ldr r2, [r7, #16] 80030e2: 429a cmp r2, r3 80030e4: d001 beq.n 80030ea { return HAL_ERROR; 80030e6: 2301 movs r3, #1 80030e8: e000 b.n 80030ec } return HAL_OK; 80030ea: 2300 movs r3, #0 } 80030ec: 4618 mov r0, r3 80030ee: 3718 adds r7, #24 80030f0: 46bd mov sp, r7 80030f2: bd80 pop {r7, pc} 80030f4: 40021000 .word 0x40021000 80030f8: 40022000 .word 0x40022000 080030fc : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80030fc: b580 push {r7, lr} 80030fe: b086 sub sp, #24 8003100: af00 add r7, sp, #0 8003102: 6078 str r0, [r7, #4] uint32_t tmpregister, tickstart; /* no init needed */ HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8003104: 2300 movs r3, #0 8003106: 74fb strb r3, [r7, #19] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003108: 2300 movs r3, #0 800310a: 74bb strb r3, [r7, #18] assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); #if defined(SAI1) /*-------------------------- SAI1 clock source configuration ---------------------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) 800310c: 687b ldr r3, [r7, #4] 800310e: 681b ldr r3, [r3, #0] 8003110: f403 6300 and.w r3, r3, #2048 @ 0x800 8003114: 2b00 cmp r3, #0 8003116: d041 beq.n 800319c { /* Check the parameters */ assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); switch(PeriphClkInit->Sai1ClockSelection) 8003118: 687b ldr r3, [r7, #4] 800311a: 6e5b ldr r3, [r3, #100] @ 0x64 800311c: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 8003120: d02a beq.n 8003178 8003122: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 8003126: d824 bhi.n 8003172 8003128: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800312c: d008 beq.n 8003140 800312e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8003132: d81e bhi.n 8003172 8003134: 2b00 cmp r3, #0 8003136: d00a beq.n 800314e 8003138: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800313c: d010 beq.n 8003160 800313e: e018 b.n 8003172 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated from System PLL . */ #if defined(RCC_PLLSAI2_SUPPORT) __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); 8003140: 4b86 ldr r3, [pc, #536] @ (800335c ) 8003142: 68db ldr r3, [r3, #12] 8003144: 4a85 ldr r2, [pc, #532] @ (800335c ) 8003146: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800314a: 60d3 str r3, [r2, #12] #else __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK); #endif /* RCC_PLLSAI2_SUPPORT */ /* SAI1 clock source config set later after clock selection check */ break; 800314c: e015 b.n 800317a case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/ /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); 800314e: 687b ldr r3, [r7, #4] 8003150: 3304 adds r3, #4 8003152: 2100 movs r1, #0 8003154: 4618 mov r0, r3 8003156: f000 facb bl 80036f0 800315a: 4603 mov r3, r0 800315c: 74fb strb r3, [r7, #19] /* SAI1 clock source config set later after clock selection check */ break; 800315e: e00c b.n 800317a #if defined(RCC_PLLSAI2_SUPPORT) case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/ /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */ ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); 8003160: 687b ldr r3, [r7, #4] 8003162: 3320 adds r3, #32 8003164: 2100 movs r1, #0 8003166: 4618 mov r0, r3 8003168: f000 fbb6 bl 80038d8 800316c: 4603 mov r3, r0 800316e: 74fb strb r3, [r7, #19] /* SAI1 clock source config set later after clock selection check */ break; 8003170: e003 b.n 800317a #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* SAI1 clock source config set later after clock selection check */ break; default: ret = HAL_ERROR; 8003172: 2301 movs r3, #1 8003174: 74fb strb r3, [r7, #19] break; 8003176: e000 b.n 800317a break; 8003178: bf00 nop } if(ret == HAL_OK) 800317a: 7cfb ldrb r3, [r7, #19] 800317c: 2b00 cmp r3, #0 800317e: d10b bne.n 8003198 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8003180: 4b76 ldr r3, [pc, #472] @ (800335c ) 8003182: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003186: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 800318a: 687b ldr r3, [r7, #4] 800318c: 6e5b ldr r3, [r3, #100] @ 0x64 800318e: 4973 ldr r1, [pc, #460] @ (800335c ) 8003190: 4313 orrs r3, r2 8003192: f8c1 3088 str.w r3, [r1, #136] @ 0x88 8003196: e001 b.n 800319c } else { /* set overall return value */ status = ret; 8003198: 7cfb ldrb r3, [r7, #19] 800319a: 74bb strb r3, [r7, #18] #endif /* SAI1 */ #if defined(SAI2) /*-------------------------- SAI2 clock source configuration ---------------------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) 800319c: 687b ldr r3, [r7, #4] 800319e: 681b ldr r3, [r3, #0] 80031a0: f403 5380 and.w r3, r3, #4096 @ 0x1000 80031a4: 2b00 cmp r3, #0 80031a6: d041 beq.n 800322c { /* Check the parameters */ assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection)); switch(PeriphClkInit->Sai2ClockSelection) 80031a8: 687b ldr r3, [r7, #4] 80031aa: 6e9b ldr r3, [r3, #104] @ 0x68 80031ac: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 80031b0: d02a beq.n 8003208 80031b2: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 80031b6: d824 bhi.n 8003202 80031b8: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80031bc: d008 beq.n 80031d0 80031be: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80031c2: d81e bhi.n 8003202 80031c4: 2b00 cmp r3, #0 80031c6: d00a beq.n 80031de 80031c8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80031cc: d010 beq.n 80031f0 80031ce: e018 b.n 8003202 { case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated from System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); 80031d0: 4b62 ldr r3, [pc, #392] @ (800335c ) 80031d2: 68db ldr r3, [r3, #12] 80031d4: 4a61 ldr r2, [pc, #388] @ (800335c ) 80031d6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80031da: 60d3 str r3, [r2, #12] /* SAI2 clock source config set later after clock selection check */ break; 80031dc: e015 b.n 800320a case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/ /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); 80031de: 687b ldr r3, [r7, #4] 80031e0: 3304 adds r3, #4 80031e2: 2100 movs r1, #0 80031e4: 4618 mov r0, r3 80031e6: f000 fa83 bl 80036f0 80031ea: 4603 mov r3, r0 80031ec: 74fb strb r3, [r7, #19] /* SAI2 clock source config set later after clock selection check */ break; 80031ee: e00c b.n 800320a case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/ /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */ ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); 80031f0: 687b ldr r3, [r7, #4] 80031f2: 3320 adds r3, #32 80031f4: 2100 movs r1, #0 80031f6: 4618 mov r0, r3 80031f8: f000 fb6e bl 80038d8 80031fc: 4603 mov r3, r0 80031fe: 74fb strb r3, [r7, #19] /* SAI2 clock source config set later after clock selection check */ break; 8003200: e003 b.n 800320a #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* SAI2 clock source config set later after clock selection check */ break; default: ret = HAL_ERROR; 8003202: 2301 movs r3, #1 8003204: 74fb strb r3, [r7, #19] break; 8003206: e000 b.n 800320a break; 8003208: bf00 nop } if(ret == HAL_OK) 800320a: 7cfb ldrb r3, [r7, #19] 800320c: 2b00 cmp r3, #0 800320e: d10b bne.n 8003228 { /* Set the source of SAI2 clock*/ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 8003210: 4b52 ldr r3, [pc, #328] @ (800335c ) 8003212: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003216: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 800321a: 687b ldr r3, [r7, #4] 800321c: 6e9b ldr r3, [r3, #104] @ 0x68 800321e: 494f ldr r1, [pc, #316] @ (800335c ) 8003220: 4313 orrs r3, r2 8003222: f8c1 3088 str.w r3, [r1, #136] @ 0x88 8003226: e001 b.n 800322c } else { /* set overall return value */ status = ret; 8003228: 7cfb ldrb r3, [r7, #19] 800322a: 74bb strb r3, [r7, #18] } } #endif /* SAI2 */ /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800322c: 687b ldr r3, [r7, #4] 800322e: 681b ldr r3, [r3, #0] 8003230: f403 3300 and.w r3, r3, #131072 @ 0x20000 8003234: 2b00 cmp r3, #0 8003236: f000 80a0 beq.w 800337a { FlagStatus pwrclkchanged = RESET; 800323a: 2300 movs r3, #0 800323c: 747b strb r3, [r7, #17] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 800323e: 4b47 ldr r3, [pc, #284] @ (800335c ) 8003240: 6d9b ldr r3, [r3, #88] @ 0x58 8003242: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003246: 2b00 cmp r3, #0 8003248: d101 bne.n 800324e 800324a: 2301 movs r3, #1 800324c: e000 b.n 8003250 800324e: 2300 movs r3, #0 8003250: 2b00 cmp r3, #0 8003252: d00d beq.n 8003270 { __HAL_RCC_PWR_CLK_ENABLE(); 8003254: 4b41 ldr r3, [pc, #260] @ (800335c ) 8003256: 6d9b ldr r3, [r3, #88] @ 0x58 8003258: 4a40 ldr r2, [pc, #256] @ (800335c ) 800325a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800325e: 6593 str r3, [r2, #88] @ 0x58 8003260: 4b3e ldr r3, [pc, #248] @ (800335c ) 8003262: 6d9b ldr r3, [r3, #88] @ 0x58 8003264: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003268: 60bb str r3, [r7, #8] 800326a: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800326c: 2301 movs r3, #1 800326e: 747b strb r3, [r7, #17] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8003270: 4b3b ldr r3, [pc, #236] @ (8003360 ) 8003272: 681b ldr r3, [r3, #0] 8003274: 4a3a ldr r2, [pc, #232] @ (8003360 ) 8003276: f443 7380 orr.w r3, r3, #256 @ 0x100 800327a: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800327c: f7fe f94a bl 8001514 8003280: 60f8 str r0, [r7, #12] while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) 8003282: e009 b.n 8003298 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003284: f7fe f946 bl 8001514 8003288: 4602 mov r2, r0 800328a: 68fb ldr r3, [r7, #12] 800328c: 1ad3 subs r3, r2, r3 800328e: 2b02 cmp r3, #2 8003290: d902 bls.n 8003298 { ret = HAL_TIMEOUT; 8003292: 2303 movs r3, #3 8003294: 74fb strb r3, [r7, #19] break; 8003296: e005 b.n 80032a4 while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) 8003298: 4b31 ldr r3, [pc, #196] @ (8003360 ) 800329a: 681b ldr r3, [r3, #0] 800329c: f403 7380 and.w r3, r3, #256 @ 0x100 80032a0: 2b00 cmp r3, #0 80032a2: d0ef beq.n 8003284 } } if(ret == HAL_OK) 80032a4: 7cfb ldrb r3, [r7, #19] 80032a6: 2b00 cmp r3, #0 80032a8: d15c bne.n 8003364 { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 80032aa: 4b2c ldr r3, [pc, #176] @ (800335c ) 80032ac: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80032b0: f403 7340 and.w r3, r3, #768 @ 0x300 80032b4: 617b str r3, [r7, #20] if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 80032b6: 697b ldr r3, [r7, #20] 80032b8: 2b00 cmp r3, #0 80032ba: d01f beq.n 80032fc 80032bc: 687b ldr r3, [r7, #4] 80032be: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80032c2: 697a ldr r2, [r7, #20] 80032c4: 429a cmp r2, r3 80032c6: d019 beq.n 80032fc { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 80032c8: 4b24 ldr r3, [pc, #144] @ (800335c ) 80032ca: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80032ce: f423 7340 bic.w r3, r3, #768 @ 0x300 80032d2: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80032d4: 4b21 ldr r3, [pc, #132] @ (800335c ) 80032d6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80032da: 4a20 ldr r2, [pc, #128] @ (800335c ) 80032dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80032e0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 __HAL_RCC_BACKUPRESET_RELEASE(); 80032e4: 4b1d ldr r3, [pc, #116] @ (800335c ) 80032e6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80032ea: 4a1c ldr r2, [pc, #112] @ (800335c ) 80032ec: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80032f0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 80032f4: 4a19 ldr r2, [pc, #100] @ (800335c ) 80032f6: 697b ldr r3, [r7, #20] 80032f8: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 80032fc: 697b ldr r3, [r7, #20] 80032fe: f003 0301 and.w r3, r3, #1 8003302: 2b00 cmp r3, #0 8003304: d016 beq.n 8003334 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003306: f7fe f905 bl 8001514 800330a: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 800330c: e00b b.n 8003326 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800330e: f7fe f901 bl 8001514 8003312: 4602 mov r2, r0 8003314: 68fb ldr r3, [r7, #12] 8003316: 1ad3 subs r3, r2, r3 8003318: f241 3288 movw r2, #5000 @ 0x1388 800331c: 4293 cmp r3, r2 800331e: d902 bls.n 8003326 { ret = HAL_TIMEOUT; 8003320: 2303 movs r3, #3 8003322: 74fb strb r3, [r7, #19] break; 8003324: e006 b.n 8003334 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003326: 4b0d ldr r3, [pc, #52] @ (800335c ) 8003328: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800332c: f003 0302 and.w r3, r3, #2 8003330: 2b00 cmp r3, #0 8003332: d0ec beq.n 800330e } } } if(ret == HAL_OK) 8003334: 7cfb ldrb r3, [r7, #19] 8003336: 2b00 cmp r3, #0 8003338: d10c bne.n 8003354 { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800333a: 4b08 ldr r3, [pc, #32] @ (800335c ) 800333c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003340: f423 7240 bic.w r2, r3, #768 @ 0x300 8003344: 687b ldr r3, [r7, #4] 8003346: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800334a: 4904 ldr r1, [pc, #16] @ (800335c ) 800334c: 4313 orrs r3, r2 800334e: f8c1 3090 str.w r3, [r1, #144] @ 0x90 8003352: e009 b.n 8003368 } else { /* set overall return value */ status = ret; 8003354: 7cfb ldrb r3, [r7, #19] 8003356: 74bb strb r3, [r7, #18] 8003358: e006 b.n 8003368 800335a: bf00 nop 800335c: 40021000 .word 0x40021000 8003360: 40007000 .word 0x40007000 } } else { /* set overall return value */ status = ret; 8003364: 7cfb ldrb r3, [r7, #19] 8003366: 74bb strb r3, [r7, #18] } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 8003368: 7c7b ldrb r3, [r7, #17] 800336a: 2b01 cmp r3, #1 800336c: d105 bne.n 800337a { __HAL_RCC_PWR_CLK_DISABLE(); 800336e: 4b9e ldr r3, [pc, #632] @ (80035e8 ) 8003370: 6d9b ldr r3, [r3, #88] @ 0x58 8003372: 4a9d ldr r2, [pc, #628] @ (80035e8 ) 8003374: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8003378: 6593 str r3, [r2, #88] @ 0x58 } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 800337a: 687b ldr r3, [r7, #4] 800337c: 681b ldr r3, [r3, #0] 800337e: f003 0301 and.w r3, r3, #1 8003382: 2b00 cmp r3, #0 8003384: d00a beq.n 800339c { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8003386: 4b98 ldr r3, [pc, #608] @ (80035e8 ) 8003388: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800338c: f023 0203 bic.w r2, r3, #3 8003390: 687b ldr r3, [r7, #4] 8003392: 6b9b ldr r3, [r3, #56] @ 0x38 8003394: 4994 ldr r1, [pc, #592] @ (80035e8 ) 8003396: 4313 orrs r3, r2 8003398: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 800339c: 687b ldr r3, [r7, #4] 800339e: 681b ldr r3, [r3, #0] 80033a0: f003 0302 and.w r3, r3, #2 80033a4: 2b00 cmp r3, #0 80033a6: d00a beq.n 80033be { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 80033a8: 4b8f ldr r3, [pc, #572] @ (80035e8 ) 80033aa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80033ae: f023 020c bic.w r2, r3, #12 80033b2: 687b ldr r3, [r7, #4] 80033b4: 6bdb ldr r3, [r3, #60] @ 0x3c 80033b6: 498c ldr r1, [pc, #560] @ (80035e8 ) 80033b8: 4313 orrs r3, r2 80033ba: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(USART3) /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 80033be: 687b ldr r3, [r7, #4] 80033c0: 681b ldr r3, [r3, #0] 80033c2: f003 0304 and.w r3, r3, #4 80033c6: 2b00 cmp r3, #0 80033c8: d00a beq.n 80033e0 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 80033ca: 4b87 ldr r3, [pc, #540] @ (80035e8 ) 80033cc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80033d0: f023 0230 bic.w r2, r3, #48 @ 0x30 80033d4: 687b ldr r3, [r7, #4] 80033d6: 6c1b ldr r3, [r3, #64] @ 0x40 80033d8: 4983 ldr r1, [pc, #524] @ (80035e8 ) 80033da: 4313 orrs r3, r2 80033dc: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* USART3 */ #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 80033e0: 687b ldr r3, [r7, #4] 80033e2: 681b ldr r3, [r3, #0] 80033e4: f003 0308 and.w r3, r3, #8 80033e8: 2b00 cmp r3, #0 80033ea: d00a beq.n 8003402 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 80033ec: 4b7e ldr r3, [pc, #504] @ (80035e8 ) 80033ee: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80033f2: f023 02c0 bic.w r2, r3, #192 @ 0xc0 80033f6: 687b ldr r3, [r7, #4] 80033f8: 6c5b ldr r3, [r3, #68] @ 0x44 80033fa: 497b ldr r1, [pc, #492] @ (80035e8 ) 80033fc: 4313 orrs r3, r2 80033fe: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* UART4 */ #if defined(UART5) /*-------------------------- UART5 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) 8003402: 687b ldr r3, [r7, #4] 8003404: 681b ldr r3, [r3, #0] 8003406: f003 0310 and.w r3, r3, #16 800340a: 2b00 cmp r3, #0 800340c: d00a beq.n 8003424 { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); 800340e: 4b76 ldr r3, [pc, #472] @ (80035e8 ) 8003410: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003414: f423 7240 bic.w r2, r3, #768 @ 0x300 8003418: 687b ldr r3, [r7, #4] 800341a: 6c9b ldr r3, [r3, #72] @ 0x48 800341c: 4972 ldr r1, [pc, #456] @ (80035e8 ) 800341e: 4313 orrs r3, r2 8003420: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8003424: 687b ldr r3, [r7, #4] 8003426: 681b ldr r3, [r3, #0] 8003428: f003 0320 and.w r3, r3, #32 800342c: 2b00 cmp r3, #0 800342e: d00a beq.n 8003446 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUART1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8003430: 4b6d ldr r3, [pc, #436] @ (80035e8 ) 8003432: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003436: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800343a: 687b ldr r3, [r7, #4] 800343c: 6cdb ldr r3, [r3, #76] @ 0x4c 800343e: 496a ldr r1, [pc, #424] @ (80035e8 ) 8003440: 4313 orrs r3, r2 8003442: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- LPTIM1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) 8003446: 687b ldr r3, [r7, #4] 8003448: 681b ldr r3, [r3, #0] 800344a: f403 7300 and.w r3, r3, #512 @ 0x200 800344e: 2b00 cmp r3, #0 8003450: d00a beq.n 8003468 { assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8003452: 4b65 ldr r3, [pc, #404] @ (80035e8 ) 8003454: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003458: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 800345c: 687b ldr r3, [r7, #4] 800345e: 6ddb ldr r3, [r3, #92] @ 0x5c 8003460: 4961 ldr r1, [pc, #388] @ (80035e8 ) 8003462: 4313 orrs r3, r2 8003464: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- LPTIM2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) 8003468: 687b ldr r3, [r7, #4] 800346a: 681b ldr r3, [r3, #0] 800346c: f403 6380 and.w r3, r3, #1024 @ 0x400 8003470: 2b00 cmp r3, #0 8003472: d00a beq.n 800348a { assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 8003474: 4b5c ldr r3, [pc, #368] @ (80035e8 ) 8003476: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800347a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 800347e: 687b ldr r3, [r7, #4] 8003480: 6e1b ldr r3, [r3, #96] @ 0x60 8003482: 4959 ldr r1, [pc, #356] @ (80035e8 ) 8003484: 4313 orrs r3, r2 8003486: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 800348a: 687b ldr r3, [r7, #4] 800348c: 681b ldr r3, [r3, #0] 800348e: f003 0340 and.w r3, r3, #64 @ 0x40 8003492: 2b00 cmp r3, #0 8003494: d00a beq.n 80034ac { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8003496: 4b54 ldr r3, [pc, #336] @ (80035e8 ) 8003498: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800349c: f423 5240 bic.w r2, r3, #12288 @ 0x3000 80034a0: 687b ldr r3, [r7, #4] 80034a2: 6d1b ldr r3, [r3, #80] @ 0x50 80034a4: 4950 ldr r1, [pc, #320] @ (80035e8 ) 80034a6: 4313 orrs r3, r2 80034a8: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(I2C2) /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 80034ac: 687b ldr r3, [r7, #4] 80034ae: 681b ldr r3, [r3, #0] 80034b0: f003 0380 and.w r3, r3, #128 @ 0x80 80034b4: 2b00 cmp r3, #0 80034b6: d00a beq.n 80034ce { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 80034b8: 4b4b ldr r3, [pc, #300] @ (80035e8 ) 80034ba: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80034be: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80034c2: 687b ldr r3, [r7, #4] 80034c4: 6d5b ldr r3, [r3, #84] @ 0x54 80034c6: 4948 ldr r1, [pc, #288] @ (80035e8 ) 80034c8: 4313 orrs r3, r2 80034ca: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* I2C2 */ /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 80034ce: 687b ldr r3, [r7, #4] 80034d0: 681b ldr r3, [r3, #0] 80034d2: f403 7380 and.w r3, r3, #256 @ 0x100 80034d6: 2b00 cmp r3, #0 80034d8: d00a beq.n 80034f0 { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 80034da: 4b43 ldr r3, [pc, #268] @ (80035e8 ) 80034dc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80034e0: f423 3240 bic.w r2, r3, #196608 @ 0x30000 80034e4: 687b ldr r3, [r7, #4] 80034e6: 6d9b ldr r3, [r3, #88] @ 0x58 80034e8: 493f ldr r1, [pc, #252] @ (80035e8 ) 80034ea: 4313 orrs r3, r2 80034ec: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* I2C4 */ #if defined(USB_OTG_FS) || defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 80034f0: 687b ldr r3, [r7, #4] 80034f2: 681b ldr r3, [r3, #0] 80034f4: f403 5300 and.w r3, r3, #8192 @ 0x2000 80034f8: 2b00 cmp r3, #0 80034fa: d028 beq.n 800354e { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80034fc: 4b3a ldr r3, [pc, #232] @ (80035e8 ) 80034fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003502: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 8003506: 687b ldr r3, [r7, #4] 8003508: 6edb ldr r3, [r3, #108] @ 0x6c 800350a: 4937 ldr r1, [pc, #220] @ (80035e8 ) 800350c: 4313 orrs r3, r2 800350e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 8003512: 687b ldr r3, [r7, #4] 8003514: 6edb ldr r3, [r3, #108] @ 0x6c 8003516: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800351a: d106 bne.n 800352a { /* Enable PLL48M1CLK output clock */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 800351c: 4b32 ldr r3, [pc, #200] @ (80035e8 ) 800351e: 68db ldr r3, [r3, #12] 8003520: 4a31 ldr r2, [pc, #196] @ (80035e8 ) 8003522: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8003526: 60d3 str r3, [r2, #12] 8003528: e011 b.n 800354e } else { #if defined(RCC_PLLSAI1_SUPPORT) if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) 800352a: 687b ldr r3, [r7, #4] 800352c: 6edb ldr r3, [r3, #108] @ 0x6c 800352e: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8003532: d10c bne.n 800354e { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 8003534: 687b ldr r3, [r7, #4] 8003536: 3304 adds r3, #4 8003538: 2101 movs r1, #1 800353a: 4618 mov r0, r3 800353c: f000 f8d8 bl 80036f0 8003540: 4603 mov r3, r0 8003542: 74fb strb r3, [r7, #19] if(ret != HAL_OK) 8003544: 7cfb ldrb r3, [r7, #19] 8003546: 2b00 cmp r3, #0 8003548: d001 beq.n 800354e { /* set overall return value */ status = ret; 800354a: 7cfb ldrb r3, [r7, #19] 800354c: 74bb strb r3, [r7, #18] #endif /* USB_OTG_FS || USB */ #if defined(SDMMC1) /*-------------------------- SDMMC1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1)) 800354e: 687b ldr r3, [r7, #4] 8003550: 681b ldr r3, [r3, #0] 8003552: f403 2300 and.w r3, r3, #524288 @ 0x80000 8003556: 2b00 cmp r3, #0 8003558: d028 beq.n 80035ac { assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); 800355a: 4b23 ldr r3, [pc, #140] @ (80035e8 ) 800355c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003560: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 8003564: 687b ldr r3, [r7, #4] 8003566: 6f1b ldr r3, [r3, #112] @ 0x70 8003568: 491f ldr r1, [pc, #124] @ (80035e8 ) 800356a: 4313 orrs r3, r2 800356c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */ 8003570: 687b ldr r3, [r7, #4] 8003572: 6f1b ldr r3, [r3, #112] @ 0x70 8003574: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8003578: d106 bne.n 8003588 { /* Enable PLL48M1CLK output clock */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 800357a: 4b1b ldr r3, [pc, #108] @ (80035e8 ) 800357c: 68db ldr r3, [r3, #12] 800357e: 4a1a ldr r2, [pc, #104] @ (80035e8 ) 8003580: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8003584: 60d3 str r3, [r2, #12] 8003586: e011 b.n 80035ac { /* Enable PLLSAI3CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); } #endif else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1) 8003588: 687b ldr r3, [r7, #4] 800358a: 6f1b ldr r3, [r3, #112] @ 0x70 800358c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8003590: d10c bne.n 80035ac { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 8003592: 687b ldr r3, [r7, #4] 8003594: 3304 adds r3, #4 8003596: 2101 movs r1, #1 8003598: 4618 mov r0, r3 800359a: f000 f8a9 bl 80036f0 800359e: 4603 mov r3, r0 80035a0: 74fb strb r3, [r7, #19] if(ret != HAL_OK) 80035a2: 7cfb ldrb r3, [r7, #19] 80035a4: 2b00 cmp r3, #0 80035a6: d001 beq.n 80035ac { /* set overall return value */ status = ret; 80035a8: 7cfb ldrb r3, [r7, #19] 80035aa: 74bb strb r3, [r7, #18] } #endif /* SDMMC1 */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 80035ac: 687b ldr r3, [r7, #4] 80035ae: 681b ldr r3, [r3, #0] 80035b0: f403 2380 and.w r3, r3, #262144 @ 0x40000 80035b4: 2b00 cmp r3, #0 80035b6: d02b beq.n 8003610 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 80035b8: 4b0b ldr r3, [pc, #44] @ (80035e8 ) 80035ba: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80035be: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 80035c2: 687b ldr r3, [r7, #4] 80035c4: 6f5b ldr r3, [r3, #116] @ 0x74 80035c6: 4908 ldr r1, [pc, #32] @ (80035e8 ) 80035c8: 4313 orrs r3, r2 80035ca: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 80035ce: 687b ldr r3, [r7, #4] 80035d0: 6f5b ldr r3, [r3, #116] @ 0x74 80035d2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80035d6: d109 bne.n 80035ec { /* Enable PLL48M1CLK output clock */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80035d8: 4b03 ldr r3, [pc, #12] @ (80035e8 ) 80035da: 68db ldr r3, [r3, #12] 80035dc: 4a02 ldr r2, [pc, #8] @ (80035e8 ) 80035de: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80035e2: 60d3 str r3, [r2, #12] 80035e4: e014 b.n 8003610 80035e6: bf00 nop 80035e8: 40021000 .word 0x40021000 } #if defined(RCC_PLLSAI1_SUPPORT) else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) 80035ec: 687b ldr r3, [r7, #4] 80035ee: 6f5b ldr r3, [r3, #116] @ 0x74 80035f0: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 80035f4: d10c bne.n 8003610 { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 80035f6: 687b ldr r3, [r7, #4] 80035f8: 3304 adds r3, #4 80035fa: 2101 movs r1, #1 80035fc: 4618 mov r0, r3 80035fe: f000 f877 bl 80036f0 8003602: 4603 mov r3, r0 8003604: 74fb strb r3, [r7, #19] if(ret != HAL_OK) 8003606: 7cfb ldrb r3, [r7, #19] 8003608: 2b00 cmp r3, #0 800360a: d001 beq.n 8003610 { /* set overall return value */ status = ret; 800360c: 7cfb ldrb r3, [r7, #19] 800360e: 74bb strb r3, [r7, #18] } } /*-------------------------- ADC clock source configuration ----------------------*/ #if !defined(STM32L412xx) && !defined(STM32L422xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8003610: 687b ldr r3, [r7, #4] 8003612: 681b ldr r3, [r3, #0] 8003614: f403 4380 and.w r3, r3, #16384 @ 0x4000 8003618: 2b00 cmp r3, #0 800361a: d02f beq.n 800367c { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800361c: 4b2b ldr r3, [pc, #172] @ (80036cc ) 800361e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003622: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 8003626: 687b ldr r3, [r7, #4] 8003628: 6f9b ldr r3, [r3, #120] @ 0x78 800362a: 4928 ldr r1, [pc, #160] @ (80036cc ) 800362c: 4313 orrs r3, r2 800362e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #if defined(RCC_PLLSAI1_SUPPORT) if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) 8003632: 687b ldr r3, [r7, #4] 8003634: 6f9b ldr r3, [r3, #120] @ 0x78 8003636: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800363a: d10d bne.n 8003658 { /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE); 800363c: 687b ldr r3, [r7, #4] 800363e: 3304 adds r3, #4 8003640: 2102 movs r1, #2 8003642: 4618 mov r0, r3 8003644: f000 f854 bl 80036f0 8003648: 4603 mov r3, r0 800364a: 74fb strb r3, [r7, #19] if(ret != HAL_OK) 800364c: 7cfb ldrb r3, [r7, #19] 800364e: 2b00 cmp r3, #0 8003650: d014 beq.n 800367c { /* set overall return value */ status = ret; 8003652: 7cfb ldrb r3, [r7, #19] 8003654: 74bb strb r3, [r7, #18] 8003656: e011 b.n 800367c } #endif /* RCC_PLLSAI1_SUPPORT */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2) 8003658: 687b ldr r3, [r7, #4] 800365a: 6f9b ldr r3, [r3, #120] @ 0x78 800365c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8003660: d10c bne.n 800367c { /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); 8003662: 687b ldr r3, [r7, #4] 8003664: 3320 adds r3, #32 8003666: 2102 movs r1, #2 8003668: 4618 mov r0, r3 800366a: f000 f935 bl 80038d8 800366e: 4603 mov r3, r0 8003670: 74fb strb r3, [r7, #19] if(ret != HAL_OK) 8003672: 7cfb ldrb r3, [r7, #19] 8003674: 2b00 cmp r3, #0 8003676: d001 beq.n 800367c { /* set overall return value */ status = ret; 8003678: 7cfb ldrb r3, [r7, #19] 800367a: 74bb strb r3, [r7, #18] #endif /* !STM32L412xx && !STM32L422xx */ #if defined(SWPMI1) /*-------------------------- SWPMI1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800367c: 687b ldr r3, [r7, #4] 800367e: 681b ldr r3, [r3, #0] 8003680: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003684: 2b00 cmp r3, #0 8003686: d00a beq.n 800369e { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 8003688: 4b10 ldr r3, [pc, #64] @ (80036cc ) 800368a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800368e: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000 8003692: 687b ldr r3, [r7, #4] 8003694: 6fdb ldr r3, [r3, #124] @ 0x7c 8003696: 490d ldr r1, [pc, #52] @ (80036cc ) 8003698: 4313 orrs r3, r2 800369a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* SWPMI1 */ #if defined(DFSDM1_Filter0) /*-------------------------- DFSDM1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800369e: 687b ldr r3, [r7, #4] 80036a0: 681b ldr r3, [r3, #0] 80036a2: f403 3380 and.w r3, r3, #65536 @ 0x10000 80036a6: 2b00 cmp r3, #0 80036a8: d00b beq.n 80036c2 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 80036aa: 4b08 ldr r3, [pc, #32] @ (80036cc ) 80036ac: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80036b0: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 80036b4: 687b ldr r3, [r7, #4] 80036b6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80036ba: 4904 ldr r1, [pc, #16] @ (80036cc ) 80036bc: 4313 orrs r3, r2 80036be: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } } #endif /* OCTOSPI1 || OCTOSPI2 */ return status; 80036c2: 7cbb ldrb r3, [r7, #18] } 80036c4: 4618 mov r0, r3 80036c6: 3718 adds r7, #24 80036c8: 46bd mov sp, r7 80036ca: bd80 pop {r7, pc} 80036cc: 40021000 .word 0x40021000 080036d0 : * @note Prior to enable the PLL-mode of the MSI for automatic hardware * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig(). * @retval None */ void HAL_RCCEx_EnableMSIPLLMode(void) { 80036d0: b480 push {r7} 80036d2: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; 80036d4: 4b05 ldr r3, [pc, #20] @ (80036ec ) 80036d6: 681b ldr r3, [r3, #0] 80036d8: 4a04 ldr r2, [pc, #16] @ (80036ec ) 80036da: f043 0304 orr.w r3, r3, #4 80036de: 6013 str r3, [r2, #0] } 80036e0: bf00 nop 80036e2: 46bd mov sp, r7 80036e4: f85d 7b04 ldr.w r7, [sp], #4 80036e8: 4770 bx lr 80036ea: bf00 nop 80036ec: 40021000 .word 0x40021000 080036f0 : * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) { 80036f0: b580 push {r7, lr} 80036f2: b084 sub sp, #16 80036f4: af00 add r7, sp, #0 80036f6: 6078 str r0, [r7, #4] 80036f8: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 80036fa: 2300 movs r3, #0 80036fc: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); /* Check that PLLSAI1 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) 80036fe: 4b75 ldr r3, [pc, #468] @ (80038d4 ) 8003700: 68db ldr r3, [r3, #12] 8003702: f003 0303 and.w r3, r3, #3 8003706: 2b00 cmp r3, #0 8003708: d018 beq.n 800373c { /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) 800370a: 4b72 ldr r3, [pc, #456] @ (80038d4 ) 800370c: 68db ldr r3, [r3, #12] 800370e: f003 0203 and.w r2, r3, #3 8003712: 687b ldr r3, [r7, #4] 8003714: 681b ldr r3, [r3, #0] 8003716: 429a cmp r2, r3 8003718: d10d bne.n 8003736 || (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) 800371a: 687b ldr r3, [r7, #4] 800371c: 681b ldr r3, [r3, #0] || 800371e: 2b00 cmp r3, #0 8003720: d009 beq.n 8003736 #if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) 8003722: 4b6c ldr r3, [pc, #432] @ (80038d4 ) 8003724: 68db ldr r3, [r3, #12] 8003726: 091b lsrs r3, r3, #4 8003728: f003 0307 and.w r3, r3, #7 800372c: 1c5a adds r2, r3, #1 800372e: 687b ldr r3, [r7, #4] 8003730: 685b ldr r3, [r3, #4] || 8003732: 429a cmp r2, r3 8003734: d047 beq.n 80037c6 #endif ) { status = HAL_ERROR; 8003736: 2301 movs r3, #1 8003738: 73fb strb r3, [r7, #15] 800373a: e044 b.n 80037c6 } } else { /* Check PLLSAI1 clock source availability */ switch(PllSai1->PLLSAI1Source) 800373c: 687b ldr r3, [r7, #4] 800373e: 681b ldr r3, [r3, #0] 8003740: 2b03 cmp r3, #3 8003742: d018 beq.n 8003776 8003744: 2b03 cmp r3, #3 8003746: d825 bhi.n 8003794 8003748: 2b01 cmp r3, #1 800374a: d002 beq.n 8003752 800374c: 2b02 cmp r3, #2 800374e: d009 beq.n 8003764 8003750: e020 b.n 8003794 { case RCC_PLLSOURCE_MSI: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) 8003752: 4b60 ldr r3, [pc, #384] @ (80038d4 ) 8003754: 681b ldr r3, [r3, #0] 8003756: f003 0302 and.w r3, r3, #2 800375a: 2b00 cmp r3, #0 800375c: d11d bne.n 800379a { status = HAL_ERROR; 800375e: 2301 movs r3, #1 8003760: 73fb strb r3, [r7, #15] } break; 8003762: e01a b.n 800379a case RCC_PLLSOURCE_HSI: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) 8003764: 4b5b ldr r3, [pc, #364] @ (80038d4 ) 8003766: 681b ldr r3, [r3, #0] 8003768: f403 6380 and.w r3, r3, #1024 @ 0x400 800376c: 2b00 cmp r3, #0 800376e: d116 bne.n 800379e { status = HAL_ERROR; 8003770: 2301 movs r3, #1 8003772: 73fb strb r3, [r7, #15] } break; 8003774: e013 b.n 800379e case RCC_PLLSOURCE_HSE: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) 8003776: 4b57 ldr r3, [pc, #348] @ (80038d4 ) 8003778: 681b ldr r3, [r3, #0] 800377a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800377e: 2b00 cmp r3, #0 8003780: d10f bne.n 80037a2 { if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) 8003782: 4b54 ldr r3, [pc, #336] @ (80038d4 ) 8003784: 681b ldr r3, [r3, #0] 8003786: f403 2380 and.w r3, r3, #262144 @ 0x40000 800378a: 2b00 cmp r3, #0 800378c: d109 bne.n 80037a2 { status = HAL_ERROR; 800378e: 2301 movs r3, #1 8003790: 73fb strb r3, [r7, #15] } } break; 8003792: e006 b.n 80037a2 default: status = HAL_ERROR; 8003794: 2301 movs r3, #1 8003796: 73fb strb r3, [r7, #15] break; 8003798: e004 b.n 80037a4 break; 800379a: bf00 nop 800379c: e002 b.n 80037a4 break; 800379e: bf00 nop 80037a0: e000 b.n 80037a4 break; 80037a2: bf00 nop } if(status == HAL_OK) 80037a4: 7bfb ldrb r3, [r7, #15] 80037a6: 2b00 cmp r3, #0 80037a8: d10d bne.n 80037c6 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) /* Set PLLSAI1 clock source */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); #else /* Set PLLSAI1 clock source and divider M */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); 80037aa: 4b4a ldr r3, [pc, #296] @ (80038d4 ) 80037ac: 68db ldr r3, [r3, #12] 80037ae: f023 0273 bic.w r2, r3, #115 @ 0x73 80037b2: 687b ldr r3, [r7, #4] 80037b4: 6819 ldr r1, [r3, #0] 80037b6: 687b ldr r3, [r7, #4] 80037b8: 685b ldr r3, [r3, #4] 80037ba: 3b01 subs r3, #1 80037bc: 011b lsls r3, r3, #4 80037be: 430b orrs r3, r1 80037c0: 4944 ldr r1, [pc, #272] @ (80038d4 ) 80037c2: 4313 orrs r3, r2 80037c4: 60cb str r3, [r1, #12] #endif } } if(status == HAL_OK) 80037c6: 7bfb ldrb r3, [r7, #15] 80037c8: 2b00 cmp r3, #0 80037ca: d17d bne.n 80038c8 { /* Disable the PLLSAI1 */ __HAL_RCC_PLLSAI1_DISABLE(); 80037cc: 4b41 ldr r3, [pc, #260] @ (80038d4 ) 80037ce: 681b ldr r3, [r3, #0] 80037d0: 4a40 ldr r2, [pc, #256] @ (80038d4 ) 80037d2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80037d6: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80037d8: f7fd fe9c bl 8001514 80037dc: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready to be updated */ while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) 80037de: e009 b.n 80037f4 { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 80037e0: f7fd fe98 bl 8001514 80037e4: 4602 mov r2, r0 80037e6: 68bb ldr r3, [r7, #8] 80037e8: 1ad3 subs r3, r2, r3 80037ea: 2b02 cmp r3, #2 80037ec: d902 bls.n 80037f4 { status = HAL_TIMEOUT; 80037ee: 2303 movs r3, #3 80037f0: 73fb strb r3, [r7, #15] break; 80037f2: e005 b.n 8003800 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) 80037f4: 4b37 ldr r3, [pc, #220] @ (80038d4 ) 80037f6: 681b ldr r3, [r3, #0] 80037f8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80037fc: 2b00 cmp r3, #0 80037fe: d1ef bne.n 80037e0 } } if(status == HAL_OK) 8003800: 7bfb ldrb r3, [r7, #15] 8003802: 2b00 cmp r3, #0 8003804: d160 bne.n 80038c8 { if(Divider == DIVIDER_P_UPDATE) 8003806: 683b ldr r3, [r7, #0] 8003808: 2b00 cmp r3, #0 800380a: d111 bne.n 8003830 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)); #else MODIFY_REG(RCC->PLLSAI1CFGR, 800380c: 4b31 ldr r3, [pc, #196] @ (80038d4 ) 800380e: 691b ldr r3, [r3, #16] 8003810: f423 331f bic.w r3, r3, #162816 @ 0x27c00 8003814: f423 7340 bic.w r3, r3, #768 @ 0x300 8003818: 687a ldr r2, [r7, #4] 800381a: 6892 ldr r2, [r2, #8] 800381c: 0211 lsls r1, r2, #8 800381e: 687a ldr r2, [r7, #4] 8003820: 68d2 ldr r2, [r2, #12] 8003822: 0912 lsrs r2, r2, #4 8003824: 0452 lsls r2, r2, #17 8003826: 430a orrs r2, r1 8003828: 492a ldr r1, [pc, #168] @ (80038d4 ) 800382a: 4313 orrs r3, r2 800382c: 610b str r3, [r1, #16] 800382e: e027 b.n 8003880 ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } else if(Divider == DIVIDER_Q_UPDATE) 8003830: 683b ldr r3, [r7, #0] 8003832: 2b01 cmp r3, #1 8003834: d112 bne.n 800385c (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); #else /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ MODIFY_REG(RCC->PLLSAI1CFGR, 8003836: 4b27 ldr r3, [pc, #156] @ (80038d4 ) 8003838: 691b ldr r3, [r3, #16] 800383a: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000 800383e: f423 43fe bic.w r3, r3, #32512 @ 0x7f00 8003842: 687a ldr r2, [r7, #4] 8003844: 6892 ldr r2, [r2, #8] 8003846: 0211 lsls r1, r2, #8 8003848: 687a ldr r2, [r7, #4] 800384a: 6912 ldr r2, [r2, #16] 800384c: 0852 lsrs r2, r2, #1 800384e: 3a01 subs r2, #1 8003850: 0552 lsls r2, r2, #21 8003852: 430a orrs r2, r1 8003854: 491f ldr r1, [pc, #124] @ (80038d4 ) 8003856: 4313 orrs r3, r2 8003858: 610b str r3, [r1, #16] 800385a: e011 b.n 8003880 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); #else /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ MODIFY_REG(RCC->PLLSAI1CFGR, 800385c: 4b1d ldr r3, [pc, #116] @ (80038d4 ) 800385e: 691b ldr r3, [r3, #16] 8003860: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000 8003864: f423 43fe bic.w r3, r3, #32512 @ 0x7f00 8003868: 687a ldr r2, [r7, #4] 800386a: 6892 ldr r2, [r2, #8] 800386c: 0211 lsls r1, r2, #8 800386e: 687a ldr r2, [r7, #4] 8003870: 6952 ldr r2, [r2, #20] 8003872: 0852 lsrs r2, r2, #1 8003874: 3a01 subs r2, #1 8003876: 0652 lsls r2, r2, #25 8003878: 430a orrs r2, r1 800387a: 4916 ldr r1, [pc, #88] @ (80038d4 ) 800387c: 4313 orrs r3, r2 800387e: 610b str r3, [r1, #16] (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ __HAL_RCC_PLLSAI1_ENABLE(); 8003880: 4b14 ldr r3, [pc, #80] @ (80038d4 ) 8003882: 681b ldr r3, [r3, #0] 8003884: 4a13 ldr r2, [pc, #76] @ (80038d4 ) 8003886: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800388a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800388c: f7fd fe42 bl 8001514 8003890: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) 8003892: e009 b.n 80038a8 { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 8003894: f7fd fe3e bl 8001514 8003898: 4602 mov r2, r0 800389a: 68bb ldr r3, [r7, #8] 800389c: 1ad3 subs r3, r2, r3 800389e: 2b02 cmp r3, #2 80038a0: d902 bls.n 80038a8 { status = HAL_TIMEOUT; 80038a2: 2303 movs r3, #3 80038a4: 73fb strb r3, [r7, #15] break; 80038a6: e005 b.n 80038b4 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) 80038a8: 4b0a ldr r3, [pc, #40] @ (80038d4 ) 80038aa: 681b ldr r3, [r3, #0] 80038ac: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80038b0: 2b00 cmp r3, #0 80038b2: d0ef beq.n 8003894 } } if(status == HAL_OK) 80038b4: 7bfb ldrb r3, [r7, #15] 80038b6: 2b00 cmp r3, #0 80038b8: d106 bne.n 80038c8 { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); 80038ba: 4b06 ldr r3, [pc, #24] @ (80038d4 ) 80038bc: 691a ldr r2, [r3, #16] 80038be: 687b ldr r3, [r7, #4] 80038c0: 699b ldr r3, [r3, #24] 80038c2: 4904 ldr r1, [pc, #16] @ (80038d4 ) 80038c4: 4313 orrs r3, r2 80038c6: 610b str r3, [r1, #16] } } } return status; 80038c8: 7bfb ldrb r3, [r7, #15] } 80038ca: 4618 mov r0, r3 80038cc: 3710 adds r7, #16 80038ce: 46bd mov sp, r7 80038d0: bd80 pop {r7, pc} 80038d2: bf00 nop 80038d4: 40021000 .word 0x40021000 080038d8 : * @note PLLSAI2 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider) { 80038d8: b580 push {r7, lr} 80038da: b084 sub sp, #16 80038dc: af00 add r7, sp, #0 80038de: 6078 str r0, [r7, #4] 80038e0: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 80038e2: 2300 movs r3, #0 80038e4: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M)); assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N)); assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut)); /* Check that PLLSAI2 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) 80038e6: 4b6a ldr r3, [pc, #424] @ (8003a90 ) 80038e8: 68db ldr r3, [r3, #12] 80038ea: f003 0303 and.w r3, r3, #3 80038ee: 2b00 cmp r3, #0 80038f0: d018 beq.n 8003924 { /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source) 80038f2: 4b67 ldr r3, [pc, #412] @ (8003a90 ) 80038f4: 68db ldr r3, [r3, #12] 80038f6: f003 0203 and.w r2, r3, #3 80038fa: 687b ldr r3, [r7, #4] 80038fc: 681b ldr r3, [r3, #0] 80038fe: 429a cmp r2, r3 8003900: d10d bne.n 800391e || (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE) 8003902: 687b ldr r3, [r7, #4] 8003904: 681b ldr r3, [r3, #0] || 8003906: 2b00 cmp r3, #0 8003908: d009 beq.n 800391e #if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) || (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M) 800390a: 4b61 ldr r3, [pc, #388] @ (8003a90 ) 800390c: 68db ldr r3, [r3, #12] 800390e: 091b lsrs r3, r3, #4 8003910: f003 0307 and.w r3, r3, #7 8003914: 1c5a adds r2, r3, #1 8003916: 687b ldr r3, [r7, #4] 8003918: 685b ldr r3, [r3, #4] || 800391a: 429a cmp r2, r3 800391c: d047 beq.n 80039ae #endif ) { status = HAL_ERROR; 800391e: 2301 movs r3, #1 8003920: 73fb strb r3, [r7, #15] 8003922: e044 b.n 80039ae } } else { /* Check PLLSAI2 clock source availability */ switch(PllSai2->PLLSAI2Source) 8003924: 687b ldr r3, [r7, #4] 8003926: 681b ldr r3, [r3, #0] 8003928: 2b03 cmp r3, #3 800392a: d018 beq.n 800395e 800392c: 2b03 cmp r3, #3 800392e: d825 bhi.n 800397c 8003930: 2b01 cmp r3, #1 8003932: d002 beq.n 800393a 8003934: 2b02 cmp r3, #2 8003936: d009 beq.n 800394c 8003938: e020 b.n 800397c { case RCC_PLLSOURCE_MSI: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) 800393a: 4b55 ldr r3, [pc, #340] @ (8003a90 ) 800393c: 681b ldr r3, [r3, #0] 800393e: f003 0302 and.w r3, r3, #2 8003942: 2b00 cmp r3, #0 8003944: d11d bne.n 8003982 { status = HAL_ERROR; 8003946: 2301 movs r3, #1 8003948: 73fb strb r3, [r7, #15] } break; 800394a: e01a b.n 8003982 case RCC_PLLSOURCE_HSI: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) 800394c: 4b50 ldr r3, [pc, #320] @ (8003a90 ) 800394e: 681b ldr r3, [r3, #0] 8003950: f403 6380 and.w r3, r3, #1024 @ 0x400 8003954: 2b00 cmp r3, #0 8003956: d116 bne.n 8003986 { status = HAL_ERROR; 8003958: 2301 movs r3, #1 800395a: 73fb strb r3, [r7, #15] } break; 800395c: e013 b.n 8003986 case RCC_PLLSOURCE_HSE: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) 800395e: 4b4c ldr r3, [pc, #304] @ (8003a90 ) 8003960: 681b ldr r3, [r3, #0] 8003962: f403 3300 and.w r3, r3, #131072 @ 0x20000 8003966: 2b00 cmp r3, #0 8003968: d10f bne.n 800398a { if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) 800396a: 4b49 ldr r3, [pc, #292] @ (8003a90 ) 800396c: 681b ldr r3, [r3, #0] 800396e: f403 2380 and.w r3, r3, #262144 @ 0x40000 8003972: 2b00 cmp r3, #0 8003974: d109 bne.n 800398a { status = HAL_ERROR; 8003976: 2301 movs r3, #1 8003978: 73fb strb r3, [r7, #15] } } break; 800397a: e006 b.n 800398a default: status = HAL_ERROR; 800397c: 2301 movs r3, #1 800397e: 73fb strb r3, [r7, #15] break; 8003980: e004 b.n 800398c break; 8003982: bf00 nop 8003984: e002 b.n 800398c break; 8003986: bf00 nop 8003988: e000 b.n 800398c break; 800398a: bf00 nop } if(status == HAL_OK) 800398c: 7bfb ldrb r3, [r7, #15] 800398e: 2b00 cmp r3, #0 8003990: d10d bne.n 80039ae #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* Set PLLSAI2 clock source */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source); #else /* Set PLLSAI2 clock source and divider M */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos); 8003992: 4b3f ldr r3, [pc, #252] @ (8003a90 ) 8003994: 68db ldr r3, [r3, #12] 8003996: f023 0273 bic.w r2, r3, #115 @ 0x73 800399a: 687b ldr r3, [r7, #4] 800399c: 6819 ldr r1, [r3, #0] 800399e: 687b ldr r3, [r7, #4] 80039a0: 685b ldr r3, [r3, #4] 80039a2: 3b01 subs r3, #1 80039a4: 011b lsls r3, r3, #4 80039a6: 430b orrs r3, r1 80039a8: 4939 ldr r1, [pc, #228] @ (8003a90 ) 80039aa: 4313 orrs r3, r2 80039ac: 60cb str r3, [r1, #12] #endif } } if(status == HAL_OK) 80039ae: 7bfb ldrb r3, [r7, #15] 80039b0: 2b00 cmp r3, #0 80039b2: d167 bne.n 8003a84 { /* Disable the PLLSAI2 */ __HAL_RCC_PLLSAI2_DISABLE(); 80039b4: 4b36 ldr r3, [pc, #216] @ (8003a90 ) 80039b6: 681b ldr r3, [r3, #0] 80039b8: 4a35 ldr r2, [pc, #212] @ (8003a90 ) 80039ba: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80039be: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80039c0: f7fd fda8 bl 8001514 80039c4: 60b8 str r0, [r7, #8] /* Wait till PLLSAI2 is ready to be updated */ while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) 80039c6: e009 b.n 80039dc { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 80039c8: f7fd fda4 bl 8001514 80039cc: 4602 mov r2, r0 80039ce: 68bb ldr r3, [r7, #8] 80039d0: 1ad3 subs r3, r2, r3 80039d2: 2b02 cmp r3, #2 80039d4: d902 bls.n 80039dc { status = HAL_TIMEOUT; 80039d6: 2303 movs r3, #3 80039d8: 73fb strb r3, [r7, #15] break; 80039da: e005 b.n 80039e8 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) 80039dc: 4b2c ldr r3, [pc, #176] @ (8003a90 ) 80039de: 681b ldr r3, [r3, #0] 80039e0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80039e4: 2b00 cmp r3, #0 80039e6: d1ef bne.n 80039c8 } } if(status == HAL_OK) 80039e8: 7bfb ldrb r3, [r7, #15] 80039ea: 2b00 cmp r3, #0 80039ec: d14a bne.n 8003a84 { if(Divider == DIVIDER_P_UPDATE) 80039ee: 683b ldr r3, [r7, #0] 80039f0: 2b00 cmp r3, #0 80039f2: d111 bne.n 8003a18 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)); #else MODIFY_REG(RCC->PLLSAI2CFGR, 80039f4: 4b26 ldr r3, [pc, #152] @ (8003a90 ) 80039f6: 695b ldr r3, [r3, #20] 80039f8: f423 331f bic.w r3, r3, #162816 @ 0x27c00 80039fc: f423 7340 bic.w r3, r3, #768 @ 0x300 8003a00: 687a ldr r2, [r7, #4] 8003a02: 6892 ldr r2, [r2, #8] 8003a04: 0211 lsls r1, r2, #8 8003a06: 687a ldr r2, [r7, #4] 8003a08: 68d2 ldr r2, [r2, #12] 8003a0a: 0912 lsrs r2, r2, #4 8003a0c: 0452 lsls r2, r2, #17 8003a0e: 430a orrs r2, r1 8003a10: 491f ldr r1, [pc, #124] @ (8003a90 ) 8003a12: 4313 orrs r3, r2 8003a14: 614b str r3, [r1, #20] 8003a16: e011 b.n 8003a3c (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); #else /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/ MODIFY_REG(RCC->PLLSAI2CFGR, 8003a18: 4b1d ldr r3, [pc, #116] @ (8003a90 ) 8003a1a: 695b ldr r3, [r3, #20] 8003a1c: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000 8003a20: f423 43fe bic.w r3, r3, #32512 @ 0x7f00 8003a24: 687a ldr r2, [r7, #4] 8003a26: 6892 ldr r2, [r2, #8] 8003a28: 0211 lsls r1, r2, #8 8003a2a: 687a ldr r2, [r7, #4] 8003a2c: 6912 ldr r2, [r2, #16] 8003a2e: 0852 lsrs r2, r2, #1 8003a30: 3a01 subs r2, #1 8003a32: 0652 lsls r2, r2, #25 8003a34: 430a orrs r2, r1 8003a36: 4916 ldr r1, [pc, #88] @ (8003a90 ) 8003a38: 4313 orrs r3, r2 8003a3a: 614b str r3, [r1, #20] (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)); #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ } /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ __HAL_RCC_PLLSAI2_ENABLE(); 8003a3c: 4b14 ldr r3, [pc, #80] @ (8003a90 ) 8003a3e: 681b ldr r3, [r3, #0] 8003a40: 4a13 ldr r2, [pc, #76] @ (8003a90 ) 8003a42: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003a46: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003a48: f7fd fd64 bl 8001514 8003a4c: 60b8 str r0, [r7, #8] /* Wait till PLLSAI2 is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) 8003a4e: e009 b.n 8003a64 { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 8003a50: f7fd fd60 bl 8001514 8003a54: 4602 mov r2, r0 8003a56: 68bb ldr r3, [r7, #8] 8003a58: 1ad3 subs r3, r2, r3 8003a5a: 2b02 cmp r3, #2 8003a5c: d902 bls.n 8003a64 { status = HAL_TIMEOUT; 8003a5e: 2303 movs r3, #3 8003a60: 73fb strb r3, [r7, #15] break; 8003a62: e005 b.n 8003a70 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) 8003a64: 4b0a ldr r3, [pc, #40] @ (8003a90 ) 8003a66: 681b ldr r3, [r3, #0] 8003a68: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8003a6c: 2b00 cmp r3, #0 8003a6e: d0ef beq.n 8003a50 } } if(status == HAL_OK) 8003a70: 7bfb ldrb r3, [r7, #15] 8003a72: 2b00 cmp r3, #0 8003a74: d106 bne.n 8003a84 { /* Configure the PLLSAI2 Clock output(s) */ __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut); 8003a76: 4b06 ldr r3, [pc, #24] @ (8003a90 ) 8003a78: 695a ldr r2, [r3, #20] 8003a7a: 687b ldr r3, [r7, #4] 8003a7c: 695b ldr r3, [r3, #20] 8003a7e: 4904 ldr r1, [pc, #16] @ (8003a90 ) 8003a80: 4313 orrs r3, r2 8003a82: 614b str r3, [r1, #20] } } } return status; 8003a84: 7bfb ldrb r3, [r7, #15] } 8003a86: 4618 mov r0, r3 8003a88: 3710 adds r7, #16 8003a8a: 46bd mov sp, r7 8003a8c: bd80 pop {r7, pc} 8003a8e: bf00 nop 8003a90: 40021000 .word 0x40021000 08003a94 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 8003a94: b580 push {r7, lr} 8003a96: b084 sub sp, #16 8003a98: af00 add r7, sp, #0 8003a9a: 6078 str r0, [r7, #4] uint32_t frxth; /* Check the SPI handle allocation */ if (hspi == NULL) 8003a9c: 687b ldr r3, [r7, #4] 8003a9e: 2b00 cmp r3, #0 8003aa0: d101 bne.n 8003aa6 { return HAL_ERROR; 8003aa2: 2301 movs r3, #1 8003aa4: e095 b.n 8003bd2 assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 8003aa6: 687b ldr r3, [r7, #4] 8003aa8: 6a5b ldr r3, [r3, #36] @ 0x24 8003aaa: 2b00 cmp r3, #0 8003aac: d108 bne.n 8003ac0 { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 8003aae: 687b ldr r3, [r7, #4] 8003ab0: 685b ldr r3, [r3, #4] 8003ab2: f5b3 7f82 cmp.w r3, #260 @ 0x104 8003ab6: d009 beq.n 8003acc assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8003ab8: 687b ldr r3, [r7, #4] 8003aba: 2200 movs r2, #0 8003abc: 61da str r2, [r3, #28] 8003abe: e005 b.n 8003acc else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 8003ac0: 687b ldr r3, [r7, #4] 8003ac2: 2200 movs r2, #0 8003ac4: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 8003ac6: 687b ldr r3, [r7, #4] 8003ac8: 2200 movs r2, #0 8003aca: 615a str r2, [r3, #20] { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8003acc: 687b ldr r3, [r7, #4] 8003ace: 2200 movs r2, #0 8003ad0: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 8003ad2: 687b ldr r3, [r7, #4] 8003ad4: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 8003ad8: b2db uxtb r3, r3 8003ada: 2b00 cmp r3, #0 8003adc: d106 bne.n 8003aec { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 8003ade: 687b ldr r3, [r7, #4] 8003ae0: 2200 movs r2, #0 8003ae2: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 8003ae6: 6878 ldr r0, [r7, #4] 8003ae8: f7fd fa6c bl 8000fc4 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 8003aec: 687b ldr r3, [r7, #4] 8003aee: 2202 movs r2, #2 8003af0: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8003af4: 687b ldr r3, [r7, #4] 8003af6: 681b ldr r3, [r3, #0] 8003af8: 681a ldr r2, [r3, #0] 8003afa: 687b ldr r3, [r7, #4] 8003afc: 681b ldr r3, [r3, #0] 8003afe: f022 0240 bic.w r2, r2, #64 @ 0x40 8003b02: 601a str r2, [r3, #0] /* Align by default the rs fifo threshold on the data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8003b04: 687b ldr r3, [r7, #4] 8003b06: 68db ldr r3, [r3, #12] 8003b08: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 8003b0c: d902 bls.n 8003b14 { frxth = SPI_RXFIFO_THRESHOLD_HF; 8003b0e: 2300 movs r3, #0 8003b10: 60fb str r3, [r7, #12] 8003b12: e002 b.n 8003b1a } else { frxth = SPI_RXFIFO_THRESHOLD_QF; 8003b14: f44f 5380 mov.w r3, #4096 @ 0x1000 8003b18: 60fb str r3, [r7, #12] } /* CRC calculation is valid only for 16Bit and 8 Bit */ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) 8003b1a: 687b ldr r3, [r7, #4] 8003b1c: 68db ldr r3, [r3, #12] 8003b1e: f5b3 6f70 cmp.w r3, #3840 @ 0xf00 8003b22: d007 beq.n 8003b34 8003b24: 687b ldr r3, [r7, #4] 8003b26: 68db ldr r3, [r3, #12] 8003b28: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 8003b2c: d002 beq.n 8003b34 { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8003b2e: 687b ldr r3, [r7, #4] 8003b30: 2200 movs r2, #0 8003b32: 629a str r2, [r3, #40] @ 0x28 } /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 8003b34: 687b ldr r3, [r7, #4] 8003b36: 685b ldr r3, [r3, #4] 8003b38: f403 7282 and.w r2, r3, #260 @ 0x104 8003b3c: 687b ldr r3, [r7, #4] 8003b3e: 689b ldr r3, [r3, #8] 8003b40: f403 4304 and.w r3, r3, #33792 @ 0x8400 8003b44: 431a orrs r2, r3 8003b46: 687b ldr r3, [r7, #4] 8003b48: 691b ldr r3, [r3, #16] 8003b4a: f003 0302 and.w r3, r3, #2 8003b4e: 431a orrs r2, r3 8003b50: 687b ldr r3, [r7, #4] 8003b52: 695b ldr r3, [r3, #20] 8003b54: f003 0301 and.w r3, r3, #1 8003b58: 431a orrs r2, r3 8003b5a: 687b ldr r3, [r7, #4] 8003b5c: 699b ldr r3, [r3, #24] 8003b5e: f403 7300 and.w r3, r3, #512 @ 0x200 8003b62: 431a orrs r2, r3 8003b64: 687b ldr r3, [r7, #4] 8003b66: 69db ldr r3, [r3, #28] 8003b68: f003 0338 and.w r3, r3, #56 @ 0x38 8003b6c: 431a orrs r2, r3 8003b6e: 687b ldr r3, [r7, #4] 8003b70: 6a1b ldr r3, [r3, #32] 8003b72: f003 0380 and.w r3, r3, #128 @ 0x80 8003b76: ea42 0103 orr.w r1, r2, r3 8003b7a: 687b ldr r3, [r7, #4] 8003b7c: 6a9b ldr r3, [r3, #40] @ 0x28 8003b7e: f403 5200 and.w r2, r3, #8192 @ 0x2000 8003b82: 687b ldr r3, [r7, #4] 8003b84: 681b ldr r3, [r3, #0] 8003b86: 430a orrs r2, r1 8003b88: 601a str r2, [r3, #0] } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | 8003b8a: 687b ldr r3, [r7, #4] 8003b8c: 699b ldr r3, [r3, #24] 8003b8e: 0c1b lsrs r3, r3, #16 8003b90: f003 0204 and.w r2, r3, #4 8003b94: 687b ldr r3, [r7, #4] 8003b96: 6a5b ldr r3, [r3, #36] @ 0x24 8003b98: f003 0310 and.w r3, r3, #16 8003b9c: 431a orrs r2, r3 8003b9e: 687b ldr r3, [r7, #4] 8003ba0: 6b5b ldr r3, [r3, #52] @ 0x34 8003ba2: f003 0308 and.w r3, r3, #8 8003ba6: 431a orrs r2, r3 8003ba8: 687b ldr r3, [r7, #4] 8003baa: 68db ldr r3, [r3, #12] 8003bac: f403 6370 and.w r3, r3, #3840 @ 0xf00 8003bb0: ea42 0103 orr.w r1, r2, r3 8003bb4: 68fb ldr r3, [r7, #12] 8003bb6: f403 5280 and.w r2, r3, #4096 @ 0x1000 8003bba: 687b ldr r3, [r7, #4] 8003bbc: 681b ldr r3, [r3, #0] 8003bbe: 430a orrs r2, r1 8003bc0: 605a str r2, [r3, #4] #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8003bc2: 687b ldr r3, [r7, #4] 8003bc4: 2200 movs r2, #0 8003bc6: 661a str r2, [r3, #96] @ 0x60 hspi->State = HAL_SPI_STATE_READY; 8003bc8: 687b ldr r3, [r7, #4] 8003bca: 2201 movs r2, #1 8003bcc: f883 205d strb.w r2, [r3, #93] @ 0x5d return HAL_OK; 8003bd0: 2300 movs r3, #0 } 8003bd2: 4618 mov r0, r3 8003bd4: 3710 adds r7, #16 8003bd6: 46bd mov sp, r7 8003bd8: bd80 pop {r7, pc} 08003bda : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8003bda: b580 push {r7, lr} 8003bdc: b082 sub sp, #8 8003bde: af00 add r7, sp, #0 8003be0: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8003be2: 687b ldr r3, [r7, #4] 8003be4: 2b00 cmp r3, #0 8003be6: d101 bne.n 8003bec { return HAL_ERROR; 8003be8: 2301 movs r3, #1 8003bea: e049 b.n 8003c80 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8003bec: 687b ldr r3, [r7, #4] 8003bee: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003bf2: b2db uxtb r3, r3 8003bf4: 2b00 cmp r3, #0 8003bf6: d106 bne.n 8003c06 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8003bf8: 687b ldr r3, [r7, #4] 8003bfa: 2200 movs r2, #0 8003bfc: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8003c00: 6878 ldr r0, [r7, #4] 8003c02: f000 f841 bl 8003c88 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8003c06: 687b ldr r3, [r7, #4] 8003c08: 2202 movs r2, #2 8003c0a: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8003c0e: 687b ldr r3, [r7, #4] 8003c10: 681a ldr r2, [r3, #0] 8003c12: 687b ldr r3, [r7, #4] 8003c14: 3304 adds r3, #4 8003c16: 4619 mov r1, r3 8003c18: 4610 mov r0, r2 8003c1a: f000 f9df bl 8003fdc /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8003c1e: 687b ldr r3, [r7, #4] 8003c20: 2201 movs r2, #1 8003c22: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8003c26: 687b ldr r3, [r7, #4] 8003c28: 2201 movs r2, #1 8003c2a: f883 203e strb.w r2, [r3, #62] @ 0x3e 8003c2e: 687b ldr r3, [r7, #4] 8003c30: 2201 movs r2, #1 8003c32: f883 203f strb.w r2, [r3, #63] @ 0x3f 8003c36: 687b ldr r3, [r7, #4] 8003c38: 2201 movs r2, #1 8003c3a: f883 2040 strb.w r2, [r3, #64] @ 0x40 8003c3e: 687b ldr r3, [r7, #4] 8003c40: 2201 movs r2, #1 8003c42: f883 2041 strb.w r2, [r3, #65] @ 0x41 8003c46: 687b ldr r3, [r7, #4] 8003c48: 2201 movs r2, #1 8003c4a: f883 2042 strb.w r2, [r3, #66] @ 0x42 8003c4e: 687b ldr r3, [r7, #4] 8003c50: 2201 movs r2, #1 8003c52: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8003c56: 687b ldr r3, [r7, #4] 8003c58: 2201 movs r2, #1 8003c5a: f883 2044 strb.w r2, [r3, #68] @ 0x44 8003c5e: 687b ldr r3, [r7, #4] 8003c60: 2201 movs r2, #1 8003c62: f883 2045 strb.w r2, [r3, #69] @ 0x45 8003c66: 687b ldr r3, [r7, #4] 8003c68: 2201 movs r2, #1 8003c6a: f883 2046 strb.w r2, [r3, #70] @ 0x46 8003c6e: 687b ldr r3, [r7, #4] 8003c70: 2201 movs r2, #1 8003c72: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8003c76: 687b ldr r3, [r7, #4] 8003c78: 2201 movs r2, #1 8003c7a: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8003c7e: 2300 movs r3, #0 } 8003c80: 4618 mov r0, r3 8003c82: 3708 adds r7, #8 8003c84: 46bd mov sp, r7 8003c86: bd80 pop {r7, pc} 08003c88 : * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { 8003c88: b480 push {r7} 8003c8a: b083 sub sp, #12 8003c8c: af00 add r7, sp, #0 8003c8e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } 8003c90: bf00 nop 8003c92: 370c adds r7, #12 8003c94: 46bd mov sp, r7 8003c96: f85d 7b04 ldr.w r7, [sp], #4 8003c9a: 4770 bx lr 08003c9c : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8003c9c: b480 push {r7} 8003c9e: b085 sub sp, #20 8003ca0: af00 add r7, sp, #0 8003ca2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8003ca4: 687b ldr r3, [r7, #4] 8003ca6: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003caa: b2db uxtb r3, r3 8003cac: 2b01 cmp r3, #1 8003cae: d001 beq.n 8003cb4 { return HAL_ERROR; 8003cb0: 2301 movs r3, #1 8003cb2: e04f b.n 8003d54 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8003cb4: 687b ldr r3, [r7, #4] 8003cb6: 2202 movs r2, #2 8003cb8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8003cbc: 687b ldr r3, [r7, #4] 8003cbe: 681b ldr r3, [r3, #0] 8003cc0: 68da ldr r2, [r3, #12] 8003cc2: 687b ldr r3, [r7, #4] 8003cc4: 681b ldr r3, [r3, #0] 8003cc6: f042 0201 orr.w r2, r2, #1 8003cca: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8003ccc: 687b ldr r3, [r7, #4] 8003cce: 681b ldr r3, [r3, #0] 8003cd0: 4a23 ldr r2, [pc, #140] @ (8003d60 ) 8003cd2: 4293 cmp r3, r2 8003cd4: d01d beq.n 8003d12 8003cd6: 687b ldr r3, [r7, #4] 8003cd8: 681b ldr r3, [r3, #0] 8003cda: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003cde: d018 beq.n 8003d12 8003ce0: 687b ldr r3, [r7, #4] 8003ce2: 681b ldr r3, [r3, #0] 8003ce4: 4a1f ldr r2, [pc, #124] @ (8003d64 ) 8003ce6: 4293 cmp r3, r2 8003ce8: d013 beq.n 8003d12 8003cea: 687b ldr r3, [r7, #4] 8003cec: 681b ldr r3, [r3, #0] 8003cee: 4a1e ldr r2, [pc, #120] @ (8003d68 ) 8003cf0: 4293 cmp r3, r2 8003cf2: d00e beq.n 8003d12 8003cf4: 687b ldr r3, [r7, #4] 8003cf6: 681b ldr r3, [r3, #0] 8003cf8: 4a1c ldr r2, [pc, #112] @ (8003d6c ) 8003cfa: 4293 cmp r3, r2 8003cfc: d009 beq.n 8003d12 8003cfe: 687b ldr r3, [r7, #4] 8003d00: 681b ldr r3, [r3, #0] 8003d02: 4a1b ldr r2, [pc, #108] @ (8003d70 ) 8003d04: 4293 cmp r3, r2 8003d06: d004 beq.n 8003d12 8003d08: 687b ldr r3, [r7, #4] 8003d0a: 681b ldr r3, [r3, #0] 8003d0c: 4a19 ldr r2, [pc, #100] @ (8003d74 ) 8003d0e: 4293 cmp r3, r2 8003d10: d115 bne.n 8003d3e { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8003d12: 687b ldr r3, [r7, #4] 8003d14: 681b ldr r3, [r3, #0] 8003d16: 689a ldr r2, [r3, #8] 8003d18: 4b17 ldr r3, [pc, #92] @ (8003d78 ) 8003d1a: 4013 ands r3, r2 8003d1c: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8003d1e: 68fb ldr r3, [r7, #12] 8003d20: 2b06 cmp r3, #6 8003d22: d015 beq.n 8003d50 8003d24: 68fb ldr r3, [r7, #12] 8003d26: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8003d2a: d011 beq.n 8003d50 { __HAL_TIM_ENABLE(htim); 8003d2c: 687b ldr r3, [r7, #4] 8003d2e: 681b ldr r3, [r3, #0] 8003d30: 681a ldr r2, [r3, #0] 8003d32: 687b ldr r3, [r7, #4] 8003d34: 681b ldr r3, [r3, #0] 8003d36: f042 0201 orr.w r2, r2, #1 8003d3a: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8003d3c: e008 b.n 8003d50 } } else { __HAL_TIM_ENABLE(htim); 8003d3e: 687b ldr r3, [r7, #4] 8003d40: 681b ldr r3, [r3, #0] 8003d42: 681a ldr r2, [r3, #0] 8003d44: 687b ldr r3, [r7, #4] 8003d46: 681b ldr r3, [r3, #0] 8003d48: f042 0201 orr.w r2, r2, #1 8003d4c: 601a str r2, [r3, #0] 8003d4e: e000 b.n 8003d52 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8003d50: bf00 nop } /* Return function status */ return HAL_OK; 8003d52: 2300 movs r3, #0 } 8003d54: 4618 mov r0, r3 8003d56: 3714 adds r7, #20 8003d58: 46bd mov sp, r7 8003d5a: f85d 7b04 ldr.w r7, [sp], #4 8003d5e: 4770 bx lr 8003d60: 40012c00 .word 0x40012c00 8003d64: 40000400 .word 0x40000400 8003d68: 40000800 .word 0x40000800 8003d6c: 40000c00 .word 0x40000c00 8003d70: 40013400 .word 0x40013400 8003d74: 40014000 .word 0x40014000 8003d78: 00010007 .word 0x00010007 08003d7c : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8003d7c: b580 push {r7, lr} 8003d7e: b084 sub sp, #16 8003d80: af00 add r7, sp, #0 8003d82: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8003d84: 687b ldr r3, [r7, #4] 8003d86: 681b ldr r3, [r3, #0] 8003d88: 68db ldr r3, [r3, #12] 8003d8a: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8003d8c: 687b ldr r3, [r7, #4] 8003d8e: 681b ldr r3, [r3, #0] 8003d90: 691b ldr r3, [r3, #16] 8003d92: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8003d94: 68bb ldr r3, [r7, #8] 8003d96: f003 0302 and.w r3, r3, #2 8003d9a: 2b00 cmp r3, #0 8003d9c: d020 beq.n 8003de0 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8003d9e: 68fb ldr r3, [r7, #12] 8003da0: f003 0302 and.w r3, r3, #2 8003da4: 2b00 cmp r3, #0 8003da6: d01b beq.n 8003de0 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8003da8: 687b ldr r3, [r7, #4] 8003daa: 681b ldr r3, [r3, #0] 8003dac: f06f 0202 mvn.w r2, #2 8003db0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8003db2: 687b ldr r3, [r7, #4] 8003db4: 2201 movs r2, #1 8003db6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8003db8: 687b ldr r3, [r7, #4] 8003dba: 681b ldr r3, [r3, #0] 8003dbc: 699b ldr r3, [r3, #24] 8003dbe: f003 0303 and.w r3, r3, #3 8003dc2: 2b00 cmp r3, #0 8003dc4: d003 beq.n 8003dce { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8003dc6: 6878 ldr r0, [r7, #4] 8003dc8: f000 f8e9 bl 8003f9e 8003dcc: e005 b.n 8003dda { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8003dce: 6878 ldr r0, [r7, #4] 8003dd0: f000 f8db bl 8003f8a HAL_TIM_PWM_PulseFinishedCallback(htim); 8003dd4: 6878 ldr r0, [r7, #4] 8003dd6: f000 f8ec bl 8003fb2 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8003dda: 687b ldr r3, [r7, #4] 8003ddc: 2200 movs r2, #0 8003dde: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8003de0: 68bb ldr r3, [r7, #8] 8003de2: f003 0304 and.w r3, r3, #4 8003de6: 2b00 cmp r3, #0 8003de8: d020 beq.n 8003e2c { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8003dea: 68fb ldr r3, [r7, #12] 8003dec: f003 0304 and.w r3, r3, #4 8003df0: 2b00 cmp r3, #0 8003df2: d01b beq.n 8003e2c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8003df4: 687b ldr r3, [r7, #4] 8003df6: 681b ldr r3, [r3, #0] 8003df8: f06f 0204 mvn.w r2, #4 8003dfc: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8003dfe: 687b ldr r3, [r7, #4] 8003e00: 2202 movs r2, #2 8003e02: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8003e04: 687b ldr r3, [r7, #4] 8003e06: 681b ldr r3, [r3, #0] 8003e08: 699b ldr r3, [r3, #24] 8003e0a: f403 7340 and.w r3, r3, #768 @ 0x300 8003e0e: 2b00 cmp r3, #0 8003e10: d003 beq.n 8003e1a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8003e12: 6878 ldr r0, [r7, #4] 8003e14: f000 f8c3 bl 8003f9e 8003e18: e005 b.n 8003e26 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8003e1a: 6878 ldr r0, [r7, #4] 8003e1c: f000 f8b5 bl 8003f8a HAL_TIM_PWM_PulseFinishedCallback(htim); 8003e20: 6878 ldr r0, [r7, #4] 8003e22: f000 f8c6 bl 8003fb2 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8003e26: 687b ldr r3, [r7, #4] 8003e28: 2200 movs r2, #0 8003e2a: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8003e2c: 68bb ldr r3, [r7, #8] 8003e2e: f003 0308 and.w r3, r3, #8 8003e32: 2b00 cmp r3, #0 8003e34: d020 beq.n 8003e78 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8003e36: 68fb ldr r3, [r7, #12] 8003e38: f003 0308 and.w r3, r3, #8 8003e3c: 2b00 cmp r3, #0 8003e3e: d01b beq.n 8003e78 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8003e40: 687b ldr r3, [r7, #4] 8003e42: 681b ldr r3, [r3, #0] 8003e44: f06f 0208 mvn.w r2, #8 8003e48: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8003e4a: 687b ldr r3, [r7, #4] 8003e4c: 2204 movs r2, #4 8003e4e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8003e50: 687b ldr r3, [r7, #4] 8003e52: 681b ldr r3, [r3, #0] 8003e54: 69db ldr r3, [r3, #28] 8003e56: f003 0303 and.w r3, r3, #3 8003e5a: 2b00 cmp r3, #0 8003e5c: d003 beq.n 8003e66 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8003e5e: 6878 ldr r0, [r7, #4] 8003e60: f000 f89d bl 8003f9e 8003e64: e005 b.n 8003e72 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8003e66: 6878 ldr r0, [r7, #4] 8003e68: f000 f88f bl 8003f8a HAL_TIM_PWM_PulseFinishedCallback(htim); 8003e6c: 6878 ldr r0, [r7, #4] 8003e6e: f000 f8a0 bl 8003fb2 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8003e72: 687b ldr r3, [r7, #4] 8003e74: 2200 movs r2, #0 8003e76: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8003e78: 68bb ldr r3, [r7, #8] 8003e7a: f003 0310 and.w r3, r3, #16 8003e7e: 2b00 cmp r3, #0 8003e80: d020 beq.n 8003ec4 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8003e82: 68fb ldr r3, [r7, #12] 8003e84: f003 0310 and.w r3, r3, #16 8003e88: 2b00 cmp r3, #0 8003e8a: d01b beq.n 8003ec4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8003e8c: 687b ldr r3, [r7, #4] 8003e8e: 681b ldr r3, [r3, #0] 8003e90: f06f 0210 mvn.w r2, #16 8003e94: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8003e96: 687b ldr r3, [r7, #4] 8003e98: 2208 movs r2, #8 8003e9a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8003e9c: 687b ldr r3, [r7, #4] 8003e9e: 681b ldr r3, [r3, #0] 8003ea0: 69db ldr r3, [r3, #28] 8003ea2: f403 7340 and.w r3, r3, #768 @ 0x300 8003ea6: 2b00 cmp r3, #0 8003ea8: d003 beq.n 8003eb2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8003eaa: 6878 ldr r0, [r7, #4] 8003eac: f000 f877 bl 8003f9e 8003eb0: e005 b.n 8003ebe { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8003eb2: 6878 ldr r0, [r7, #4] 8003eb4: f000 f869 bl 8003f8a HAL_TIM_PWM_PulseFinishedCallback(htim); 8003eb8: 6878 ldr r0, [r7, #4] 8003eba: f000 f87a bl 8003fb2 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8003ebe: 687b ldr r3, [r7, #4] 8003ec0: 2200 movs r2, #0 8003ec2: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8003ec4: 68bb ldr r3, [r7, #8] 8003ec6: f003 0301 and.w r3, r3, #1 8003eca: 2b00 cmp r3, #0 8003ecc: d00c beq.n 8003ee8 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8003ece: 68fb ldr r3, [r7, #12] 8003ed0: f003 0301 and.w r3, r3, #1 8003ed4: 2b00 cmp r3, #0 8003ed6: d007 beq.n 8003ee8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8003ed8: 687b ldr r3, [r7, #4] 8003eda: 681b ldr r3, [r3, #0] 8003edc: f06f 0201 mvn.w r2, #1 8003ee0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8003ee2: 6878 ldr r0, [r7, #4] 8003ee4: f7fc ff28 bl 8000d38 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8003ee8: 68bb ldr r3, [r7, #8] 8003eea: f003 0380 and.w r3, r3, #128 @ 0x80 8003eee: 2b00 cmp r3, #0 8003ef0: d104 bne.n 8003efc ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 8003ef2: 68bb ldr r3, [r7, #8] 8003ef4: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8003ef8: 2b00 cmp r3, #0 8003efa: d00c beq.n 8003f16 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8003efc: 68fb ldr r3, [r7, #12] 8003efe: f003 0380 and.w r3, r3, #128 @ 0x80 8003f02: 2b00 cmp r3, #0 8003f04: d007 beq.n 8003f16 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 8003f06: 687b ldr r3, [r7, #4] 8003f08: 681b ldr r3, [r3, #0] 8003f0a: f46f 5202 mvn.w r2, #8320 @ 0x2080 8003f0e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8003f10: 6878 ldr r0, [r7, #4] 8003f12: f000 f913 bl 800413c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 8003f16: 68bb ldr r3, [r7, #8] 8003f18: f403 7380 and.w r3, r3, #256 @ 0x100 8003f1c: 2b00 cmp r3, #0 8003f1e: d00c beq.n 8003f3a { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8003f20: 68fb ldr r3, [r7, #12] 8003f22: f003 0380 and.w r3, r3, #128 @ 0x80 8003f26: 2b00 cmp r3, #0 8003f28: d007 beq.n 8003f3a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 8003f2a: 687b ldr r3, [r7, #4] 8003f2c: 681b ldr r3, [r3, #0] 8003f2e: f46f 7280 mvn.w r2, #256 @ 0x100 8003f32: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8003f34: 6878 ldr r0, [r7, #4] 8003f36: f000 f90b bl 8004150 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8003f3a: 68bb ldr r3, [r7, #8] 8003f3c: f003 0340 and.w r3, r3, #64 @ 0x40 8003f40: 2b00 cmp r3, #0 8003f42: d00c beq.n 8003f5e { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8003f44: 68fb ldr r3, [r7, #12] 8003f46: f003 0340 and.w r3, r3, #64 @ 0x40 8003f4a: 2b00 cmp r3, #0 8003f4c: d007 beq.n 8003f5e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8003f4e: 687b ldr r3, [r7, #4] 8003f50: 681b ldr r3, [r3, #0] 8003f52: f06f 0240 mvn.w r2, #64 @ 0x40 8003f56: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8003f58: 6878 ldr r0, [r7, #4] 8003f5a: f000 f834 bl 8003fc6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8003f5e: 68bb ldr r3, [r7, #8] 8003f60: f003 0320 and.w r3, r3, #32 8003f64: 2b00 cmp r3, #0 8003f66: d00c beq.n 8003f82 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8003f68: 68fb ldr r3, [r7, #12] 8003f6a: f003 0320 and.w r3, r3, #32 8003f6e: 2b00 cmp r3, #0 8003f70: d007 beq.n 8003f82 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8003f72: 687b ldr r3, [r7, #4] 8003f74: 681b ldr r3, [r3, #0] 8003f76: f06f 0220 mvn.w r2, #32 8003f7a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8003f7c: 6878 ldr r0, [r7, #4] 8003f7e: f000 f8d3 bl 8004128 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8003f82: bf00 nop 8003f84: 3710 adds r7, #16 8003f86: 46bd mov sp, r7 8003f88: bd80 pop {r7, pc} 08003f8a : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8003f8a: b480 push {r7} 8003f8c: b083 sub sp, #12 8003f8e: af00 add r7, sp, #0 8003f90: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8003f92: bf00 nop 8003f94: 370c adds r7, #12 8003f96: 46bd mov sp, r7 8003f98: f85d 7b04 ldr.w r7, [sp], #4 8003f9c: 4770 bx lr 08003f9e : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8003f9e: b480 push {r7} 8003fa0: b083 sub sp, #12 8003fa2: af00 add r7, sp, #0 8003fa4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8003fa6: bf00 nop 8003fa8: 370c adds r7, #12 8003faa: 46bd mov sp, r7 8003fac: f85d 7b04 ldr.w r7, [sp], #4 8003fb0: 4770 bx lr 08003fb2 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8003fb2: b480 push {r7} 8003fb4: b083 sub sp, #12 8003fb6: af00 add r7, sp, #0 8003fb8: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8003fba: bf00 nop 8003fbc: 370c adds r7, #12 8003fbe: 46bd mov sp, r7 8003fc0: f85d 7b04 ldr.w r7, [sp], #4 8003fc4: 4770 bx lr 08003fc6 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8003fc6: b480 push {r7} 8003fc8: b083 sub sp, #12 8003fca: af00 add r7, sp, #0 8003fcc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8003fce: bf00 nop 8003fd0: 370c adds r7, #12 8003fd2: 46bd mov sp, r7 8003fd4: f85d 7b04 ldr.w r7, [sp], #4 8003fd8: 4770 bx lr ... 08003fdc : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8003fdc: b480 push {r7} 8003fde: b085 sub sp, #20 8003fe0: af00 add r7, sp, #0 8003fe2: 6078 str r0, [r7, #4] 8003fe4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8003fe6: 687b ldr r3, [r7, #4] 8003fe8: 681b ldr r3, [r3, #0] 8003fea: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8003fec: 687b ldr r3, [r7, #4] 8003fee: 4a46 ldr r2, [pc, #280] @ (8004108 ) 8003ff0: 4293 cmp r3, r2 8003ff2: d013 beq.n 800401c 8003ff4: 687b ldr r3, [r7, #4] 8003ff6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003ffa: d00f beq.n 800401c 8003ffc: 687b ldr r3, [r7, #4] 8003ffe: 4a43 ldr r2, [pc, #268] @ (800410c ) 8004000: 4293 cmp r3, r2 8004002: d00b beq.n 800401c 8004004: 687b ldr r3, [r7, #4] 8004006: 4a42 ldr r2, [pc, #264] @ (8004110 ) 8004008: 4293 cmp r3, r2 800400a: d007 beq.n 800401c 800400c: 687b ldr r3, [r7, #4] 800400e: 4a41 ldr r2, [pc, #260] @ (8004114 ) 8004010: 4293 cmp r3, r2 8004012: d003 beq.n 800401c 8004014: 687b ldr r3, [r7, #4] 8004016: 4a40 ldr r2, [pc, #256] @ (8004118 ) 8004018: 4293 cmp r3, r2 800401a: d108 bne.n 800402e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800401c: 68fb ldr r3, [r7, #12] 800401e: f023 0370 bic.w r3, r3, #112 @ 0x70 8004022: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8004024: 683b ldr r3, [r7, #0] 8004026: 685b ldr r3, [r3, #4] 8004028: 68fa ldr r2, [r7, #12] 800402a: 4313 orrs r3, r2 800402c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800402e: 687b ldr r3, [r7, #4] 8004030: 4a35 ldr r2, [pc, #212] @ (8004108 ) 8004032: 4293 cmp r3, r2 8004034: d01f beq.n 8004076 8004036: 687b ldr r3, [r7, #4] 8004038: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800403c: d01b beq.n 8004076 800403e: 687b ldr r3, [r7, #4] 8004040: 4a32 ldr r2, [pc, #200] @ (800410c ) 8004042: 4293 cmp r3, r2 8004044: d017 beq.n 8004076 8004046: 687b ldr r3, [r7, #4] 8004048: 4a31 ldr r2, [pc, #196] @ (8004110 ) 800404a: 4293 cmp r3, r2 800404c: d013 beq.n 8004076 800404e: 687b ldr r3, [r7, #4] 8004050: 4a30 ldr r2, [pc, #192] @ (8004114 ) 8004052: 4293 cmp r3, r2 8004054: d00f beq.n 8004076 8004056: 687b ldr r3, [r7, #4] 8004058: 4a2f ldr r2, [pc, #188] @ (8004118 ) 800405a: 4293 cmp r3, r2 800405c: d00b beq.n 8004076 800405e: 687b ldr r3, [r7, #4] 8004060: 4a2e ldr r2, [pc, #184] @ (800411c ) 8004062: 4293 cmp r3, r2 8004064: d007 beq.n 8004076 8004066: 687b ldr r3, [r7, #4] 8004068: 4a2d ldr r2, [pc, #180] @ (8004120 ) 800406a: 4293 cmp r3, r2 800406c: d003 beq.n 8004076 800406e: 687b ldr r3, [r7, #4] 8004070: 4a2c ldr r2, [pc, #176] @ (8004124 ) 8004072: 4293 cmp r3, r2 8004074: d108 bne.n 8004088 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8004076: 68fb ldr r3, [r7, #12] 8004078: f423 7340 bic.w r3, r3, #768 @ 0x300 800407c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800407e: 683b ldr r3, [r7, #0] 8004080: 68db ldr r3, [r3, #12] 8004082: 68fa ldr r2, [r7, #12] 8004084: 4313 orrs r3, r2 8004086: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004088: 68fb ldr r3, [r7, #12] 800408a: f023 0280 bic.w r2, r3, #128 @ 0x80 800408e: 683b ldr r3, [r7, #0] 8004090: 695b ldr r3, [r3, #20] 8004092: 4313 orrs r3, r2 8004094: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8004096: 687b ldr r3, [r7, #4] 8004098: 68fa ldr r2, [r7, #12] 800409a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800409c: 683b ldr r3, [r7, #0] 800409e: 689a ldr r2, [r3, #8] 80040a0: 687b ldr r3, [r7, #4] 80040a2: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80040a4: 683b ldr r3, [r7, #0] 80040a6: 681a ldr r2, [r3, #0] 80040a8: 687b ldr r3, [r7, #4] 80040aa: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80040ac: 687b ldr r3, [r7, #4] 80040ae: 4a16 ldr r2, [pc, #88] @ (8004108 ) 80040b0: 4293 cmp r3, r2 80040b2: d00f beq.n 80040d4 80040b4: 687b ldr r3, [r7, #4] 80040b6: 4a18 ldr r2, [pc, #96] @ (8004118 ) 80040b8: 4293 cmp r3, r2 80040ba: d00b beq.n 80040d4 80040bc: 687b ldr r3, [r7, #4] 80040be: 4a17 ldr r2, [pc, #92] @ (800411c ) 80040c0: 4293 cmp r3, r2 80040c2: d007 beq.n 80040d4 80040c4: 687b ldr r3, [r7, #4] 80040c6: 4a16 ldr r2, [pc, #88] @ (8004120 ) 80040c8: 4293 cmp r3, r2 80040ca: d003 beq.n 80040d4 80040cc: 687b ldr r3, [r7, #4] 80040ce: 4a15 ldr r2, [pc, #84] @ (8004124 ) 80040d0: 4293 cmp r3, r2 80040d2: d103 bne.n 80040dc { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80040d4: 683b ldr r3, [r7, #0] 80040d6: 691a ldr r2, [r3, #16] 80040d8: 687b ldr r3, [r7, #4] 80040da: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80040dc: 687b ldr r3, [r7, #4] 80040de: 2201 movs r2, #1 80040e0: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 80040e2: 687b ldr r3, [r7, #4] 80040e4: 691b ldr r3, [r3, #16] 80040e6: f003 0301 and.w r3, r3, #1 80040ea: 2b01 cmp r3, #1 80040ec: d105 bne.n 80040fa { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80040ee: 687b ldr r3, [r7, #4] 80040f0: 691b ldr r3, [r3, #16] 80040f2: f023 0201 bic.w r2, r3, #1 80040f6: 687b ldr r3, [r7, #4] 80040f8: 611a str r2, [r3, #16] } } 80040fa: bf00 nop 80040fc: 3714 adds r7, #20 80040fe: 46bd mov sp, r7 8004100: f85d 7b04 ldr.w r7, [sp], #4 8004104: 4770 bx lr 8004106: bf00 nop 8004108: 40012c00 .word 0x40012c00 800410c: 40000400 .word 0x40000400 8004110: 40000800 .word 0x40000800 8004114: 40000c00 .word 0x40000c00 8004118: 40013400 .word 0x40013400 800411c: 40014000 .word 0x40014000 8004120: 40014400 .word 0x40014400 8004124: 40014800 .word 0x40014800 08004128 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8004128: b480 push {r7} 800412a: b083 sub sp, #12 800412c: af00 add r7, sp, #0 800412e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8004130: bf00 nop 8004132: 370c adds r7, #12 8004134: 46bd mov sp, r7 8004136: f85d 7b04 ldr.w r7, [sp], #4 800413a: 4770 bx lr 0800413c : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 800413c: b480 push {r7} 800413e: b083 sub sp, #12 8004140: af00 add r7, sp, #0 8004142: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8004144: bf00 nop 8004146: 370c adds r7, #12 8004148: 46bd mov sp, r7 800414a: f85d 7b04 ldr.w r7, [sp], #4 800414e: 4770 bx lr 08004150 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8004150: b480 push {r7} 8004152: b083 sub sp, #12 8004154: af00 add r7, sp, #0 8004156: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8004158: bf00 nop 800415a: 370c adds r7, #12 800415c: 46bd mov sp, r7 800415e: f85d 7b04 ldr.w r7, [sp], #4 8004162: 4770 bx lr 08004164 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8004164: b580 push {r7, lr} 8004166: b082 sub sp, #8 8004168: af00 add r7, sp, #0 800416a: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 800416c: 687b ldr r3, [r7, #4] 800416e: 2b00 cmp r3, #0 8004170: d101 bne.n 8004176 { return HAL_ERROR; 8004172: 2301 movs r3, #1 8004174: e040 b.n 80041f8 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8004176: 687b ldr r3, [r7, #4] 8004178: 6fdb ldr r3, [r3, #124] @ 0x7c 800417a: 2b00 cmp r3, #0 800417c: d106 bne.n 800418c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800417e: 687b ldr r3, [r7, #4] 8004180: 2200 movs r2, #0 8004182: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8004186: 6878 ldr r0, [r7, #4] 8004188: f7fc ff60 bl 800104c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 800418c: 687b ldr r3, [r7, #4] 800418e: 2224 movs r2, #36 @ 0x24 8004190: 67da str r2, [r3, #124] @ 0x7c __HAL_UART_DISABLE(huart); 8004192: 687b ldr r3, [r7, #4] 8004194: 681b ldr r3, [r3, #0] 8004196: 681a ldr r2, [r3, #0] 8004198: 687b ldr r3, [r7, #4] 800419a: 681b ldr r3, [r3, #0] 800419c: f022 0201 bic.w r2, r2, #1 80041a0: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80041a2: 687b ldr r3, [r7, #4] 80041a4: 6a5b ldr r3, [r3, #36] @ 0x24 80041a6: 2b00 cmp r3, #0 80041a8: d002 beq.n 80041b0 { UART_AdvFeatureConfig(huart); 80041aa: 6878 ldr r0, [r7, #4] 80041ac: f000 fae0 bl 8004770 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 80041b0: 6878 ldr r0, [r7, #4] 80041b2: f000 f825 bl 8004200 80041b6: 4603 mov r3, r0 80041b8: 2b01 cmp r3, #1 80041ba: d101 bne.n 80041c0 { return HAL_ERROR; 80041bc: 2301 movs r3, #1 80041be: e01b b.n 80041f8 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80041c0: 687b ldr r3, [r7, #4] 80041c2: 681b ldr r3, [r3, #0] 80041c4: 685a ldr r2, [r3, #4] 80041c6: 687b ldr r3, [r7, #4] 80041c8: 681b ldr r3, [r3, #0] 80041ca: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80041ce: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80041d0: 687b ldr r3, [r7, #4] 80041d2: 681b ldr r3, [r3, #0] 80041d4: 689a ldr r2, [r3, #8] 80041d6: 687b ldr r3, [r7, #4] 80041d8: 681b ldr r3, [r3, #0] 80041da: f022 022a bic.w r2, r2, #42 @ 0x2a 80041de: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 80041e0: 687b ldr r3, [r7, #4] 80041e2: 681b ldr r3, [r3, #0] 80041e4: 681a ldr r2, [r3, #0] 80041e6: 687b ldr r3, [r7, #4] 80041e8: 681b ldr r3, [r3, #0] 80041ea: f042 0201 orr.w r2, r2, #1 80041ee: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80041f0: 6878 ldr r0, [r7, #4] 80041f2: f000 fb5f bl 80048b4 80041f6: 4603 mov r3, r0 } 80041f8: 4618 mov r0, r3 80041fa: 3708 adds r7, #8 80041fc: 46bd mov sp, r7 80041fe: bd80 pop {r7, pc} 08004200 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8004200: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8004204: b08a sub sp, #40 @ 0x28 8004206: af00 add r7, sp, #0 8004208: 60f8 str r0, [r7, #12] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 800420a: 2300 movs r3, #0 800420c: f887 3022 strb.w r3, [r7, #34] @ 0x22 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8004210: 68fb ldr r3, [r7, #12] 8004212: 689a ldr r2, [r3, #8] 8004214: 68fb ldr r3, [r7, #12] 8004216: 691b ldr r3, [r3, #16] 8004218: 431a orrs r2, r3 800421a: 68fb ldr r3, [r7, #12] 800421c: 695b ldr r3, [r3, #20] 800421e: 431a orrs r2, r3 8004220: 68fb ldr r3, [r7, #12] 8004222: 69db ldr r3, [r3, #28] 8004224: 4313 orrs r3, r2 8004226: 627b str r3, [r7, #36] @ 0x24 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8004228: 68fb ldr r3, [r7, #12] 800422a: 681b ldr r3, [r3, #0] 800422c: 681a ldr r2, [r3, #0] 800422e: 4ba4 ldr r3, [pc, #656] @ (80044c0 ) 8004230: 4013 ands r3, r2 8004232: 68fa ldr r2, [r7, #12] 8004234: 6812 ldr r2, [r2, #0] 8004236: 6a79 ldr r1, [r7, #36] @ 0x24 8004238: 430b orrs r3, r1 800423a: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800423c: 68fb ldr r3, [r7, #12] 800423e: 681b ldr r3, [r3, #0] 8004240: 685b ldr r3, [r3, #4] 8004242: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8004246: 68fb ldr r3, [r7, #12] 8004248: 68da ldr r2, [r3, #12] 800424a: 68fb ldr r3, [r7, #12] 800424c: 681b ldr r3, [r3, #0] 800424e: 430a orrs r2, r1 8004250: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8004252: 68fb ldr r3, [r7, #12] 8004254: 699b ldr r3, [r3, #24] 8004256: 627b str r3, [r7, #36] @ 0x24 if (!(UART_INSTANCE_LOWPOWER(huart))) 8004258: 68fb ldr r3, [r7, #12] 800425a: 681b ldr r3, [r3, #0] 800425c: 4a99 ldr r2, [pc, #612] @ (80044c4 ) 800425e: 4293 cmp r3, r2 8004260: d004 beq.n 800426c { tmpreg |= huart->Init.OneBitSampling; 8004262: 68fb ldr r3, [r7, #12] 8004264: 6a1b ldr r3, [r3, #32] 8004266: 6a7a ldr r2, [r7, #36] @ 0x24 8004268: 4313 orrs r3, r2 800426a: 627b str r3, [r7, #36] @ 0x24 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 800426c: 68fb ldr r3, [r7, #12] 800426e: 681b ldr r3, [r3, #0] 8004270: 689b ldr r3, [r3, #8] 8004272: f423 6130 bic.w r1, r3, #2816 @ 0xb00 8004276: 68fb ldr r3, [r7, #12] 8004278: 681b ldr r3, [r3, #0] 800427a: 6a7a ldr r2, [r7, #36] @ 0x24 800427c: 430a orrs r2, r1 800427e: 609a str r2, [r3, #8] * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); #endif /* USART_PRESC_PRESCALER */ /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8004280: 68fb ldr r3, [r7, #12] 8004282: 681b ldr r3, [r3, #0] 8004284: 4a90 ldr r2, [pc, #576] @ (80044c8 ) 8004286: 4293 cmp r3, r2 8004288: d126 bne.n 80042d8 800428a: 4b90 ldr r3, [pc, #576] @ (80044cc ) 800428c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004290: f003 0303 and.w r3, r3, #3 8004294: 2b03 cmp r3, #3 8004296: d81b bhi.n 80042d0 8004298: a201 add r2, pc, #4 @ (adr r2, 80042a0 ) 800429a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800429e: bf00 nop 80042a0: 080042b1 .word 0x080042b1 80042a4: 080042c1 .word 0x080042c1 80042a8: 080042b9 .word 0x080042b9 80042ac: 080042c9 .word 0x080042c9 80042b0: 2301 movs r3, #1 80042b2: f887 3023 strb.w r3, [r7, #35] @ 0x23 80042b6: e116 b.n 80044e6 80042b8: 2302 movs r3, #2 80042ba: f887 3023 strb.w r3, [r7, #35] @ 0x23 80042be: e112 b.n 80044e6 80042c0: 2304 movs r3, #4 80042c2: f887 3023 strb.w r3, [r7, #35] @ 0x23 80042c6: e10e b.n 80044e6 80042c8: 2308 movs r3, #8 80042ca: f887 3023 strb.w r3, [r7, #35] @ 0x23 80042ce: e10a b.n 80044e6 80042d0: 2310 movs r3, #16 80042d2: f887 3023 strb.w r3, [r7, #35] @ 0x23 80042d6: e106 b.n 80044e6 80042d8: 68fb ldr r3, [r7, #12] 80042da: 681b ldr r3, [r3, #0] 80042dc: 4a7c ldr r2, [pc, #496] @ (80044d0 ) 80042de: 4293 cmp r3, r2 80042e0: d138 bne.n 8004354 80042e2: 4b7a ldr r3, [pc, #488] @ (80044cc ) 80042e4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80042e8: f003 030c and.w r3, r3, #12 80042ec: 2b0c cmp r3, #12 80042ee: d82d bhi.n 800434c 80042f0: a201 add r2, pc, #4 @ (adr r2, 80042f8 ) 80042f2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80042f6: bf00 nop 80042f8: 0800432d .word 0x0800432d 80042fc: 0800434d .word 0x0800434d 8004300: 0800434d .word 0x0800434d 8004304: 0800434d .word 0x0800434d 8004308: 0800433d .word 0x0800433d 800430c: 0800434d .word 0x0800434d 8004310: 0800434d .word 0x0800434d 8004314: 0800434d .word 0x0800434d 8004318: 08004335 .word 0x08004335 800431c: 0800434d .word 0x0800434d 8004320: 0800434d .word 0x0800434d 8004324: 0800434d .word 0x0800434d 8004328: 08004345 .word 0x08004345 800432c: 2300 movs r3, #0 800432e: f887 3023 strb.w r3, [r7, #35] @ 0x23 8004332: e0d8 b.n 80044e6 8004334: 2302 movs r3, #2 8004336: f887 3023 strb.w r3, [r7, #35] @ 0x23 800433a: e0d4 b.n 80044e6 800433c: 2304 movs r3, #4 800433e: f887 3023 strb.w r3, [r7, #35] @ 0x23 8004342: e0d0 b.n 80044e6 8004344: 2308 movs r3, #8 8004346: f887 3023 strb.w r3, [r7, #35] @ 0x23 800434a: e0cc b.n 80044e6 800434c: 2310 movs r3, #16 800434e: f887 3023 strb.w r3, [r7, #35] @ 0x23 8004352: e0c8 b.n 80044e6 8004354: 68fb ldr r3, [r7, #12] 8004356: 681b ldr r3, [r3, #0] 8004358: 4a5e ldr r2, [pc, #376] @ (80044d4 ) 800435a: 4293 cmp r3, r2 800435c: d125 bne.n 80043aa 800435e: 4b5b ldr r3, [pc, #364] @ (80044cc ) 8004360: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004364: f003 0330 and.w r3, r3, #48 @ 0x30 8004368: 2b30 cmp r3, #48 @ 0x30 800436a: d016 beq.n 800439a 800436c: 2b30 cmp r3, #48 @ 0x30 800436e: d818 bhi.n 80043a2 8004370: 2b20 cmp r3, #32 8004372: d00a beq.n 800438a 8004374: 2b20 cmp r3, #32 8004376: d814 bhi.n 80043a2 8004378: 2b00 cmp r3, #0 800437a: d002 beq.n 8004382 800437c: 2b10 cmp r3, #16 800437e: d008 beq.n 8004392 8004380: e00f b.n 80043a2 8004382: 2300 movs r3, #0 8004384: f887 3023 strb.w r3, [r7, #35] @ 0x23 8004388: e0ad b.n 80044e6 800438a: 2302 movs r3, #2 800438c: f887 3023 strb.w r3, [r7, #35] @ 0x23 8004390: e0a9 b.n 80044e6 8004392: 2304 movs r3, #4 8004394: f887 3023 strb.w r3, [r7, #35] @ 0x23 8004398: e0a5 b.n 80044e6 800439a: 2308 movs r3, #8 800439c: f887 3023 strb.w r3, [r7, #35] @ 0x23 80043a0: e0a1 b.n 80044e6 80043a2: 2310 movs r3, #16 80043a4: f887 3023 strb.w r3, [r7, #35] @ 0x23 80043a8: e09d b.n 80044e6 80043aa: 68fb ldr r3, [r7, #12] 80043ac: 681b ldr r3, [r3, #0] 80043ae: 4a4a ldr r2, [pc, #296] @ (80044d8 ) 80043b0: 4293 cmp r3, r2 80043b2: d125 bne.n 8004400 80043b4: 4b45 ldr r3, [pc, #276] @ (80044cc ) 80043b6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80043ba: f003 03c0 and.w r3, r3, #192 @ 0xc0 80043be: 2bc0 cmp r3, #192 @ 0xc0 80043c0: d016 beq.n 80043f0 80043c2: 2bc0 cmp r3, #192 @ 0xc0 80043c4: d818 bhi.n 80043f8 80043c6: 2b80 cmp r3, #128 @ 0x80 80043c8: d00a beq.n 80043e0 80043ca: 2b80 cmp r3, #128 @ 0x80 80043cc: d814 bhi.n 80043f8 80043ce: 2b00 cmp r3, #0 80043d0: d002 beq.n 80043d8 80043d2: 2b40 cmp r3, #64 @ 0x40 80043d4: d008 beq.n 80043e8 80043d6: e00f b.n 80043f8 80043d8: 2300 movs r3, #0 80043da: f887 3023 strb.w r3, [r7, #35] @ 0x23 80043de: e082 b.n 80044e6 80043e0: 2302 movs r3, #2 80043e2: f887 3023 strb.w r3, [r7, #35] @ 0x23 80043e6: e07e b.n 80044e6 80043e8: 2304 movs r3, #4 80043ea: f887 3023 strb.w r3, [r7, #35] @ 0x23 80043ee: e07a b.n 80044e6 80043f0: 2308 movs r3, #8 80043f2: f887 3023 strb.w r3, [r7, #35] @ 0x23 80043f6: e076 b.n 80044e6 80043f8: 2310 movs r3, #16 80043fa: f887 3023 strb.w r3, [r7, #35] @ 0x23 80043fe: e072 b.n 80044e6 8004400: 68fb ldr r3, [r7, #12] 8004402: 681b ldr r3, [r3, #0] 8004404: 4a35 ldr r2, [pc, #212] @ (80044dc ) 8004406: 4293 cmp r3, r2 8004408: d12a bne.n 8004460 800440a: 4b30 ldr r3, [pc, #192] @ (80044cc ) 800440c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004410: f403 7340 and.w r3, r3, #768 @ 0x300 8004414: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004418: d01a beq.n 8004450 800441a: f5b3 7f40 cmp.w r3, #768 @ 0x300 800441e: d81b bhi.n 8004458 8004420: f5b3 7f00 cmp.w r3, #512 @ 0x200 8004424: d00c beq.n 8004440 8004426: f5b3 7f00 cmp.w r3, #512 @ 0x200 800442a: d815 bhi.n 8004458 800442c: 2b00 cmp r3, #0 800442e: d003 beq.n 8004438 8004430: f5b3 7f80 cmp.w r3, #256 @ 0x100 8004434: d008 beq.n 8004448 8004436: e00f b.n 8004458 8004438: 2300 movs r3, #0 800443a: f887 3023 strb.w r3, [r7, #35] @ 0x23 800443e: e052 b.n 80044e6 8004440: 2302 movs r3, #2 8004442: f887 3023 strb.w r3, [r7, #35] @ 0x23 8004446: e04e b.n 80044e6 8004448: 2304 movs r3, #4 800444a: f887 3023 strb.w r3, [r7, #35] @ 0x23 800444e: e04a b.n 80044e6 8004450: 2308 movs r3, #8 8004452: f887 3023 strb.w r3, [r7, #35] @ 0x23 8004456: e046 b.n 80044e6 8004458: 2310 movs r3, #16 800445a: f887 3023 strb.w r3, [r7, #35] @ 0x23 800445e: e042 b.n 80044e6 8004460: 68fb ldr r3, [r7, #12] 8004462: 681b ldr r3, [r3, #0] 8004464: 4a17 ldr r2, [pc, #92] @ (80044c4 ) 8004466: 4293 cmp r3, r2 8004468: d13a bne.n 80044e0 800446a: 4b18 ldr r3, [pc, #96] @ (80044cc ) 800446c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004470: f403 6340 and.w r3, r3, #3072 @ 0xc00 8004474: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8004478: d01a beq.n 80044b0 800447a: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800447e: d81b bhi.n 80044b8 8004480: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004484: d00c beq.n 80044a0 8004486: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800448a: d815 bhi.n 80044b8 800448c: 2b00 cmp r3, #0 800448e: d003 beq.n 8004498 8004490: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004494: d008 beq.n 80044a8 8004496: e00f b.n 80044b8 8004498: 2300 movs r3, #0 800449a: f887 3023 strb.w r3, [r7, #35] @ 0x23 800449e: e022 b.n 80044e6 80044a0: 2302 movs r3, #2 80044a2: f887 3023 strb.w r3, [r7, #35] @ 0x23 80044a6: e01e b.n 80044e6 80044a8: 2304 movs r3, #4 80044aa: f887 3023 strb.w r3, [r7, #35] @ 0x23 80044ae: e01a b.n 80044e6 80044b0: 2308 movs r3, #8 80044b2: f887 3023 strb.w r3, [r7, #35] @ 0x23 80044b6: e016 b.n 80044e6 80044b8: 2310 movs r3, #16 80044ba: f887 3023 strb.w r3, [r7, #35] @ 0x23 80044be: e012 b.n 80044e6 80044c0: efff69f3 .word 0xefff69f3 80044c4: 40008000 .word 0x40008000 80044c8: 40013800 .word 0x40013800 80044cc: 40021000 .word 0x40021000 80044d0: 40004400 .word 0x40004400 80044d4: 40004800 .word 0x40004800 80044d8: 40004c00 .word 0x40004c00 80044dc: 40005000 .word 0x40005000 80044e0: 2310 movs r3, #16 80044e2: f887 3023 strb.w r3, [r7, #35] @ 0x23 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 80044e6: 68fb ldr r3, [r7, #12] 80044e8: 681b ldr r3, [r3, #0] 80044ea: 4a9f ldr r2, [pc, #636] @ (8004768 ) 80044ec: 4293 cmp r3, r2 80044ee: d17a bne.n 80045e6 { /* Retrieve frequency clock */ switch (clocksource) 80044f0: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 80044f4: 2b08 cmp r3, #8 80044f6: d824 bhi.n 8004542 80044f8: a201 add r2, pc, #4 @ (adr r2, 8004500 ) 80044fa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80044fe: bf00 nop 8004500: 08004525 .word 0x08004525 8004504: 08004543 .word 0x08004543 8004508: 0800452d .word 0x0800452d 800450c: 08004543 .word 0x08004543 8004510: 08004533 .word 0x08004533 8004514: 08004543 .word 0x08004543 8004518: 08004543 .word 0x08004543 800451c: 08004543 .word 0x08004543 8004520: 0800453b .word 0x0800453b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8004524: f7fe fd2c bl 8002f80 8004528: 61f8 str r0, [r7, #28] break; 800452a: e010 b.n 800454e case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 800452c: 4b8f ldr r3, [pc, #572] @ (800476c ) 800452e: 61fb str r3, [r7, #28] break; 8004530: e00d b.n 800454e case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8004532: f7fe fc8d bl 8002e50 8004536: 61f8 str r0, [r7, #28] break; 8004538: e009 b.n 800454e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800453a: f44f 4300 mov.w r3, #32768 @ 0x8000 800453e: 61fb str r3, [r7, #28] break; 8004540: e005 b.n 800454e default: pclk = 0U; 8004542: 2300 movs r3, #0 8004544: 61fb str r3, [r7, #28] ret = HAL_ERROR; 8004546: 2301 movs r3, #1 8004548: f887 3022 strb.w r3, [r7, #34] @ 0x22 break; 800454c: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 800454e: 69fb ldr r3, [r7, #28] 8004550: 2b00 cmp r3, #0 8004552: f000 80fb beq.w 800474c } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ #else /* No Prescaler applicable */ /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((pclk < (3U * huart->Init.BaudRate)) || 8004556: 68fb ldr r3, [r7, #12] 8004558: 685a ldr r2, [r3, #4] 800455a: 4613 mov r3, r2 800455c: 005b lsls r3, r3, #1 800455e: 4413 add r3, r2 8004560: 69fa ldr r2, [r7, #28] 8004562: 429a cmp r2, r3 8004564: d305 bcc.n 8004572 (pclk > (4096U * huart->Init.BaudRate))) 8004566: 68fb ldr r3, [r7, #12] 8004568: 685b ldr r3, [r3, #4] 800456a: 031b lsls r3, r3, #12 if ((pclk < (3U * huart->Init.BaudRate)) || 800456c: 69fa ldr r2, [r7, #28] 800456e: 429a cmp r2, r3 8004570: d903 bls.n 800457a { ret = HAL_ERROR; 8004572: 2301 movs r3, #1 8004574: f887 3022 strb.w r3, [r7, #34] @ 0x22 8004578: e0e8 b.n 800474c } else { usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate)); 800457a: 69fb ldr r3, [r7, #28] 800457c: 2200 movs r2, #0 800457e: 461c mov r4, r3 8004580: 4615 mov r5, r2 8004582: f04f 0200 mov.w r2, #0 8004586: f04f 0300 mov.w r3, #0 800458a: 022b lsls r3, r5, #8 800458c: ea43 6314 orr.w r3, r3, r4, lsr #24 8004590: 0222 lsls r2, r4, #8 8004592: 68f9 ldr r1, [r7, #12] 8004594: 6849 ldr r1, [r1, #4] 8004596: 0849 lsrs r1, r1, #1 8004598: 2000 movs r0, #0 800459a: 4688 mov r8, r1 800459c: 4681 mov r9, r0 800459e: eb12 0a08 adds.w sl, r2, r8 80045a2: eb43 0b09 adc.w fp, r3, r9 80045a6: 68fb ldr r3, [r7, #12] 80045a8: 685b ldr r3, [r3, #4] 80045aa: 2200 movs r2, #0 80045ac: 603b str r3, [r7, #0] 80045ae: 607a str r2, [r7, #4] 80045b0: e9d7 2300 ldrd r2, r3, [r7] 80045b4: 4650 mov r0, sl 80045b6: 4659 mov r1, fp 80045b8: f7fb fe0a bl 80001d0 <__aeabi_uldivmod> 80045bc: 4602 mov r2, r0 80045be: 460b mov r3, r1 80045c0: 4613 mov r3, r2 80045c2: 61bb str r3, [r7, #24] if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 80045c4: 69bb ldr r3, [r7, #24] 80045c6: f5b3 7f40 cmp.w r3, #768 @ 0x300 80045ca: d308 bcc.n 80045de 80045cc: 69bb ldr r3, [r7, #24] 80045ce: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80045d2: d204 bcs.n 80045de { huart->Instance->BRR = usartdiv; 80045d4: 68fb ldr r3, [r7, #12] 80045d6: 681b ldr r3, [r3, #0] 80045d8: 69ba ldr r2, [r7, #24] 80045da: 60da str r2, [r3, #12] 80045dc: e0b6 b.n 800474c } else { ret = HAL_ERROR; 80045de: 2301 movs r3, #1 80045e0: f887 3022 strb.w r3, [r7, #34] @ 0x22 80045e4: e0b2 b.n 800474c } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */ #endif /* USART_PRESC_PRESCALER */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 80045e6: 68fb ldr r3, [r7, #12] 80045e8: 69db ldr r3, [r3, #28] 80045ea: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80045ee: d15e bne.n 80046ae { switch (clocksource) 80045f0: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 80045f4: 2b08 cmp r3, #8 80045f6: d828 bhi.n 800464a 80045f8: a201 add r2, pc, #4 @ (adr r2, 8004600 ) 80045fa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80045fe: bf00 nop 8004600: 08004625 .word 0x08004625 8004604: 0800462d .word 0x0800462d 8004608: 08004635 .word 0x08004635 800460c: 0800464b .word 0x0800464b 8004610: 0800463b .word 0x0800463b 8004614: 0800464b .word 0x0800464b 8004618: 0800464b .word 0x0800464b 800461c: 0800464b .word 0x0800464b 8004620: 08004643 .word 0x08004643 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8004624: f7fe fcac bl 8002f80 8004628: 61f8 str r0, [r7, #28] break; 800462a: e014 b.n 8004656 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800462c: f7fe fcbe bl 8002fac 8004630: 61f8 str r0, [r7, #28] break; 8004632: e010 b.n 8004656 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8004634: 4b4d ldr r3, [pc, #308] @ (800476c ) 8004636: 61fb str r3, [r7, #28] break; 8004638: e00d b.n 8004656 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 800463a: f7fe fc09 bl 8002e50 800463e: 61f8 str r0, [r7, #28] break; 8004640: e009 b.n 8004656 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8004642: f44f 4300 mov.w r3, #32768 @ 0x8000 8004646: 61fb str r3, [r7, #28] break; 8004648: e005 b.n 8004656 default: pclk = 0U; 800464a: 2300 movs r3, #0 800464c: 61fb str r3, [r7, #28] ret = HAL_ERROR; 800464e: 2301 movs r3, #1 8004650: f887 3022 strb.w r3, [r7, #34] @ 0x22 break; 8004654: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8004656: 69fb ldr r3, [r7, #28] 8004658: 2b00 cmp r3, #0 800465a: d077 beq.n 800474c { #if defined(USART_PRESC_PRESCALER) usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); 800465c: 69fb ldr r3, [r7, #28] 800465e: 005a lsls r2, r3, #1 8004660: 68fb ldr r3, [r7, #12] 8004662: 685b ldr r3, [r3, #4] 8004664: 085b lsrs r3, r3, #1 8004666: 441a add r2, r3 8004668: 68fb ldr r3, [r7, #12] 800466a: 685b ldr r3, [r3, #4] 800466c: fbb2 f3f3 udiv r3, r2, r3 8004670: 61bb str r3, [r7, #24] #endif /* USART_PRESC_PRESCALER */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8004672: 69bb ldr r3, [r7, #24] 8004674: 2b0f cmp r3, #15 8004676: d916 bls.n 80046a6 8004678: 69bb ldr r3, [r7, #24] 800467a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800467e: d212 bcs.n 80046a6 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8004680: 69bb ldr r3, [r7, #24] 8004682: b29b uxth r3, r3 8004684: f023 030f bic.w r3, r3, #15 8004688: 82fb strh r3, [r7, #22] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 800468a: 69bb ldr r3, [r7, #24] 800468c: 085b lsrs r3, r3, #1 800468e: b29b uxth r3, r3 8004690: f003 0307 and.w r3, r3, #7 8004694: b29a uxth r2, r3 8004696: 8afb ldrh r3, [r7, #22] 8004698: 4313 orrs r3, r2 800469a: 82fb strh r3, [r7, #22] huart->Instance->BRR = brrtemp; 800469c: 68fb ldr r3, [r7, #12] 800469e: 681b ldr r3, [r3, #0] 80046a0: 8afa ldrh r2, [r7, #22] 80046a2: 60da str r2, [r3, #12] 80046a4: e052 b.n 800474c } else { ret = HAL_ERROR; 80046a6: 2301 movs r3, #1 80046a8: f887 3022 strb.w r3, [r7, #34] @ 0x22 80046ac: e04e b.n 800474c } } } else { switch (clocksource) 80046ae: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 80046b2: 2b08 cmp r3, #8 80046b4: d827 bhi.n 8004706 80046b6: a201 add r2, pc, #4 @ (adr r2, 80046bc ) 80046b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80046bc: 080046e1 .word 0x080046e1 80046c0: 080046e9 .word 0x080046e9 80046c4: 080046f1 .word 0x080046f1 80046c8: 08004707 .word 0x08004707 80046cc: 080046f7 .word 0x080046f7 80046d0: 08004707 .word 0x08004707 80046d4: 08004707 .word 0x08004707 80046d8: 08004707 .word 0x08004707 80046dc: 080046ff .word 0x080046ff { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80046e0: f7fe fc4e bl 8002f80 80046e4: 61f8 str r0, [r7, #28] break; 80046e6: e014 b.n 8004712 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 80046e8: f7fe fc60 bl 8002fac 80046ec: 61f8 str r0, [r7, #28] break; 80046ee: e010 b.n 8004712 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 80046f0: 4b1e ldr r3, [pc, #120] @ (800476c ) 80046f2: 61fb str r3, [r7, #28] break; 80046f4: e00d b.n 8004712 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 80046f6: f7fe fbab bl 8002e50 80046fa: 61f8 str r0, [r7, #28] break; 80046fc: e009 b.n 8004712 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80046fe: f44f 4300 mov.w r3, #32768 @ 0x8000 8004702: 61fb str r3, [r7, #28] break; 8004704: e005 b.n 8004712 default: pclk = 0U; 8004706: 2300 movs r3, #0 8004708: 61fb str r3, [r7, #28] ret = HAL_ERROR; 800470a: 2301 movs r3, #1 800470c: f887 3022 strb.w r3, [r7, #34] @ 0x22 break; 8004710: bf00 nop } if (pclk != 0U) 8004712: 69fb ldr r3, [r7, #28] 8004714: 2b00 cmp r3, #0 8004716: d019 beq.n 800474c { /* USARTDIV must be greater than or equal to 0d16 */ #if defined(USART_PRESC_PRESCALER) usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); 8004718: 68fb ldr r3, [r7, #12] 800471a: 685b ldr r3, [r3, #4] 800471c: 085a lsrs r2, r3, #1 800471e: 69fb ldr r3, [r7, #28] 8004720: 441a add r2, r3 8004722: 68fb ldr r3, [r7, #12] 8004724: 685b ldr r3, [r3, #4] 8004726: fbb2 f3f3 udiv r3, r2, r3 800472a: 61bb str r3, [r7, #24] #endif /* USART_PRESC_PRESCALER */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800472c: 69bb ldr r3, [r7, #24] 800472e: 2b0f cmp r3, #15 8004730: d909 bls.n 8004746 8004732: 69bb ldr r3, [r7, #24] 8004734: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004738: d205 bcs.n 8004746 { huart->Instance->BRR = (uint16_t)usartdiv; 800473a: 69bb ldr r3, [r7, #24] 800473c: b29a uxth r2, r3 800473e: 68fb ldr r3, [r7, #12] 8004740: 681b ldr r3, [r3, #0] 8004742: 60da str r2, [r3, #12] 8004744: e002 b.n 800474c } else { ret = HAL_ERROR; 8004746: 2301 movs r3, #1 8004748: f887 3022 strb.w r3, [r7, #34] @ 0x22 huart->NbTxDataToProcess = 1; huart->NbRxDataToProcess = 1; #endif /* USART_CR1_FIFOEN */ /* Clear ISR function pointers */ huart->RxISR = NULL; 800474c: 68fb ldr r3, [r7, #12] 800474e: 2200 movs r2, #0 8004750: 669a str r2, [r3, #104] @ 0x68 huart->TxISR = NULL; 8004752: 68fb ldr r3, [r7, #12] 8004754: 2200 movs r2, #0 8004756: 66da str r2, [r3, #108] @ 0x6c return ret; 8004758: f897 3022 ldrb.w r3, [r7, #34] @ 0x22 } 800475c: 4618 mov r0, r3 800475e: 3728 adds r7, #40 @ 0x28 8004760: 46bd mov sp, r7 8004762: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004766: bf00 nop 8004768: 40008000 .word 0x40008000 800476c: 00f42400 .word 0x00f42400 08004770 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8004770: b480 push {r7} 8004772: b083 sub sp, #12 8004774: af00 add r7, sp, #0 8004776: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8004778: 687b ldr r3, [r7, #4] 800477a: 6a5b ldr r3, [r3, #36] @ 0x24 800477c: f003 0308 and.w r3, r3, #8 8004780: 2b00 cmp r3, #0 8004782: d00a beq.n 800479a { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8004784: 687b ldr r3, [r7, #4] 8004786: 681b ldr r3, [r3, #0] 8004788: 685b ldr r3, [r3, #4] 800478a: f423 4100 bic.w r1, r3, #32768 @ 0x8000 800478e: 687b ldr r3, [r7, #4] 8004790: 6b5a ldr r2, [r3, #52] @ 0x34 8004792: 687b ldr r3, [r7, #4] 8004794: 681b ldr r3, [r3, #0] 8004796: 430a orrs r2, r1 8004798: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800479a: 687b ldr r3, [r7, #4] 800479c: 6a5b ldr r3, [r3, #36] @ 0x24 800479e: f003 0301 and.w r3, r3, #1 80047a2: 2b00 cmp r3, #0 80047a4: d00a beq.n 80047bc { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 80047a6: 687b ldr r3, [r7, #4] 80047a8: 681b ldr r3, [r3, #0] 80047aa: 685b ldr r3, [r3, #4] 80047ac: f423 3100 bic.w r1, r3, #131072 @ 0x20000 80047b0: 687b ldr r3, [r7, #4] 80047b2: 6a9a ldr r2, [r3, #40] @ 0x28 80047b4: 687b ldr r3, [r7, #4] 80047b6: 681b ldr r3, [r3, #0] 80047b8: 430a orrs r2, r1 80047ba: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 80047bc: 687b ldr r3, [r7, #4] 80047be: 6a5b ldr r3, [r3, #36] @ 0x24 80047c0: f003 0302 and.w r3, r3, #2 80047c4: 2b00 cmp r3, #0 80047c6: d00a beq.n 80047de { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 80047c8: 687b ldr r3, [r7, #4] 80047ca: 681b ldr r3, [r3, #0] 80047cc: 685b ldr r3, [r3, #4] 80047ce: f423 3180 bic.w r1, r3, #65536 @ 0x10000 80047d2: 687b ldr r3, [r7, #4] 80047d4: 6ada ldr r2, [r3, #44] @ 0x2c 80047d6: 687b ldr r3, [r7, #4] 80047d8: 681b ldr r3, [r3, #0] 80047da: 430a orrs r2, r1 80047dc: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 80047de: 687b ldr r3, [r7, #4] 80047e0: 6a5b ldr r3, [r3, #36] @ 0x24 80047e2: f003 0304 and.w r3, r3, #4 80047e6: 2b00 cmp r3, #0 80047e8: d00a beq.n 8004800 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 80047ea: 687b ldr r3, [r7, #4] 80047ec: 681b ldr r3, [r3, #0] 80047ee: 685b ldr r3, [r3, #4] 80047f0: f423 2180 bic.w r1, r3, #262144 @ 0x40000 80047f4: 687b ldr r3, [r7, #4] 80047f6: 6b1a ldr r2, [r3, #48] @ 0x30 80047f8: 687b ldr r3, [r7, #4] 80047fa: 681b ldr r3, [r3, #0] 80047fc: 430a orrs r2, r1 80047fe: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8004800: 687b ldr r3, [r7, #4] 8004802: 6a5b ldr r3, [r3, #36] @ 0x24 8004804: f003 0310 and.w r3, r3, #16 8004808: 2b00 cmp r3, #0 800480a: d00a beq.n 8004822 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 800480c: 687b ldr r3, [r7, #4] 800480e: 681b ldr r3, [r3, #0] 8004810: 689b ldr r3, [r3, #8] 8004812: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8004816: 687b ldr r3, [r7, #4] 8004818: 6b9a ldr r2, [r3, #56] @ 0x38 800481a: 687b ldr r3, [r7, #4] 800481c: 681b ldr r3, [r3, #0] 800481e: 430a orrs r2, r1 8004820: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8004822: 687b ldr r3, [r7, #4] 8004824: 6a5b ldr r3, [r3, #36] @ 0x24 8004826: f003 0320 and.w r3, r3, #32 800482a: 2b00 cmp r3, #0 800482c: d00a beq.n 8004844 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 800482e: 687b ldr r3, [r7, #4] 8004830: 681b ldr r3, [r3, #0] 8004832: 689b ldr r3, [r3, #8] 8004834: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8004838: 687b ldr r3, [r7, #4] 800483a: 6bda ldr r2, [r3, #60] @ 0x3c 800483c: 687b ldr r3, [r7, #4] 800483e: 681b ldr r3, [r3, #0] 8004840: 430a orrs r2, r1 8004842: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8004844: 687b ldr r3, [r7, #4] 8004846: 6a5b ldr r3, [r3, #36] @ 0x24 8004848: f003 0340 and.w r3, r3, #64 @ 0x40 800484c: 2b00 cmp r3, #0 800484e: d01a beq.n 8004886 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8004850: 687b ldr r3, [r7, #4] 8004852: 681b ldr r3, [r3, #0] 8004854: 685b ldr r3, [r3, #4] 8004856: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 800485a: 687b ldr r3, [r7, #4] 800485c: 6c1a ldr r2, [r3, #64] @ 0x40 800485e: 687b ldr r3, [r7, #4] 8004860: 681b ldr r3, [r3, #0] 8004862: 430a orrs r2, r1 8004864: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8004866: 687b ldr r3, [r7, #4] 8004868: 6c1b ldr r3, [r3, #64] @ 0x40 800486a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800486e: d10a bne.n 8004886 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8004870: 687b ldr r3, [r7, #4] 8004872: 681b ldr r3, [r3, #0] 8004874: 685b ldr r3, [r3, #4] 8004876: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 800487a: 687b ldr r3, [r7, #4] 800487c: 6c5a ldr r2, [r3, #68] @ 0x44 800487e: 687b ldr r3, [r7, #4] 8004880: 681b ldr r3, [r3, #0] 8004882: 430a orrs r2, r1 8004884: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8004886: 687b ldr r3, [r7, #4] 8004888: 6a5b ldr r3, [r3, #36] @ 0x24 800488a: f003 0380 and.w r3, r3, #128 @ 0x80 800488e: 2b00 cmp r3, #0 8004890: d00a beq.n 80048a8 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8004892: 687b ldr r3, [r7, #4] 8004894: 681b ldr r3, [r3, #0] 8004896: 685b ldr r3, [r3, #4] 8004898: f423 2100 bic.w r1, r3, #524288 @ 0x80000 800489c: 687b ldr r3, [r7, #4] 800489e: 6c9a ldr r2, [r3, #72] @ 0x48 80048a0: 687b ldr r3, [r7, #4] 80048a2: 681b ldr r3, [r3, #0] 80048a4: 430a orrs r2, r1 80048a6: 605a str r2, [r3, #4] } } 80048a8: bf00 nop 80048aa: 370c adds r7, #12 80048ac: 46bd mov sp, r7 80048ae: f85d 7b04 ldr.w r7, [sp], #4 80048b2: 4770 bx lr 080048b4 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 80048b4: b580 push {r7, lr} 80048b6: b098 sub sp, #96 @ 0x60 80048b8: af02 add r7, sp, #8 80048ba: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80048bc: 687b ldr r3, [r7, #4] 80048be: 2200 movs r2, #0 80048c0: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 80048c4: f7fc fe26 bl 8001514 80048c8: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 80048ca: 687b ldr r3, [r7, #4] 80048cc: 681b ldr r3, [r3, #0] 80048ce: 681b ldr r3, [r3, #0] 80048d0: f003 0308 and.w r3, r3, #8 80048d4: 2b08 cmp r3, #8 80048d6: d12e bne.n 8004936 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 80048d8: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 80048dc: 9300 str r3, [sp, #0] 80048de: 6d7b ldr r3, [r7, #84] @ 0x54 80048e0: 2200 movs r2, #0 80048e2: f44f 1100 mov.w r1, #2097152 @ 0x200000 80048e6: 6878 ldr r0, [r7, #4] 80048e8: f000 f88c bl 8004a04 80048ec: 4603 mov r3, r0 80048ee: 2b00 cmp r3, #0 80048f0: d021 beq.n 8004936 { /* Disable TXE interrupt for the interrupt process */ #if defined(USART_CR1_FIFOEN) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); #else ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE)); 80048f2: 687b ldr r3, [r7, #4] 80048f4: 681b ldr r3, [r3, #0] 80048f6: 63bb str r3, [r7, #56] @ 0x38 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80048f8: 6bbb ldr r3, [r7, #56] @ 0x38 80048fa: e853 3f00 ldrex r3, [r3] 80048fe: 637b str r3, [r7, #52] @ 0x34 return(result); 8004900: 6b7b ldr r3, [r7, #52] @ 0x34 8004902: f023 0380 bic.w r3, r3, #128 @ 0x80 8004906: 653b str r3, [r7, #80] @ 0x50 8004908: 687b ldr r3, [r7, #4] 800490a: 681b ldr r3, [r3, #0] 800490c: 461a mov r2, r3 800490e: 6d3b ldr r3, [r7, #80] @ 0x50 8004910: 647b str r3, [r7, #68] @ 0x44 8004912: 643a str r2, [r7, #64] @ 0x40 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004914: 6c39 ldr r1, [r7, #64] @ 0x40 8004916: 6c7a ldr r2, [r7, #68] @ 0x44 8004918: e841 2300 strex r3, r2, [r1] 800491c: 63fb str r3, [r7, #60] @ 0x3c return(result); 800491e: 6bfb ldr r3, [r7, #60] @ 0x3c 8004920: 2b00 cmp r3, #0 8004922: d1e6 bne.n 80048f2 #endif /* USART_CR1_FIFOEN */ huart->gState = HAL_UART_STATE_READY; 8004924: 687b ldr r3, [r7, #4] 8004926: 2220 movs r2, #32 8004928: 67da str r2, [r3, #124] @ 0x7c __HAL_UNLOCK(huart); 800492a: 687b ldr r3, [r7, #4] 800492c: 2200 movs r2, #0 800492e: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Timeout occurred */ return HAL_TIMEOUT; 8004932: 2303 movs r3, #3 8004934: e062 b.n 80049fc } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8004936: 687b ldr r3, [r7, #4] 8004938: 681b ldr r3, [r3, #0] 800493a: 681b ldr r3, [r3, #0] 800493c: f003 0304 and.w r3, r3, #4 8004940: 2b04 cmp r3, #4 8004942: d149 bne.n 80049d8 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8004944: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8004948: 9300 str r3, [sp, #0] 800494a: 6d7b ldr r3, [r7, #84] @ 0x54 800494c: 2200 movs r2, #0 800494e: f44f 0180 mov.w r1, #4194304 @ 0x400000 8004952: 6878 ldr r0, [r7, #4] 8004954: f000 f856 bl 8004a04 8004958: 4603 mov r3, r0 800495a: 2b00 cmp r3, #0 800495c: d03c beq.n 80049d8 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800495e: 687b ldr r3, [r7, #4] 8004960: 681b ldr r3, [r3, #0] 8004962: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004964: 6a7b ldr r3, [r7, #36] @ 0x24 8004966: e853 3f00 ldrex r3, [r3] 800496a: 623b str r3, [r7, #32] return(result); 800496c: 6a3b ldr r3, [r7, #32] 800496e: f423 7390 bic.w r3, r3, #288 @ 0x120 8004972: 64fb str r3, [r7, #76] @ 0x4c 8004974: 687b ldr r3, [r7, #4] 8004976: 681b ldr r3, [r3, #0] 8004978: 461a mov r2, r3 800497a: 6cfb ldr r3, [r7, #76] @ 0x4c 800497c: 633b str r3, [r7, #48] @ 0x30 800497e: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004980: 6af9 ldr r1, [r7, #44] @ 0x2c 8004982: 6b3a ldr r2, [r7, #48] @ 0x30 8004984: e841 2300 strex r3, r2, [r1] 8004988: 62bb str r3, [r7, #40] @ 0x28 return(result); 800498a: 6abb ldr r3, [r7, #40] @ 0x28 800498c: 2b00 cmp r3, #0 800498e: d1e6 bne.n 800495e #endif /* USART_CR1_FIFOEN */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004990: 687b ldr r3, [r7, #4] 8004992: 681b ldr r3, [r3, #0] 8004994: 3308 adds r3, #8 8004996: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004998: 693b ldr r3, [r7, #16] 800499a: e853 3f00 ldrex r3, [r3] 800499e: 60fb str r3, [r7, #12] return(result); 80049a0: 68fb ldr r3, [r7, #12] 80049a2: f023 0301 bic.w r3, r3, #1 80049a6: 64bb str r3, [r7, #72] @ 0x48 80049a8: 687b ldr r3, [r7, #4] 80049aa: 681b ldr r3, [r3, #0] 80049ac: 3308 adds r3, #8 80049ae: 6cba ldr r2, [r7, #72] @ 0x48 80049b0: 61fa str r2, [r7, #28] 80049b2: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80049b4: 69b9 ldr r1, [r7, #24] 80049b6: 69fa ldr r2, [r7, #28] 80049b8: e841 2300 strex r3, r2, [r1] 80049bc: 617b str r3, [r7, #20] return(result); 80049be: 697b ldr r3, [r7, #20] 80049c0: 2b00 cmp r3, #0 80049c2: d1e5 bne.n 8004990 huart->RxState = HAL_UART_STATE_READY; 80049c4: 687b ldr r3, [r7, #4] 80049c6: 2220 movs r2, #32 80049c8: f8c3 2080 str.w r2, [r3, #128] @ 0x80 __HAL_UNLOCK(huart); 80049cc: 687b ldr r3, [r7, #4] 80049ce: 2200 movs r2, #0 80049d0: f883 2078 strb.w r2, [r3, #120] @ 0x78 /* Timeout occurred */ return HAL_TIMEOUT; 80049d4: 2303 movs r3, #3 80049d6: e011 b.n 80049fc } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 80049d8: 687b ldr r3, [r7, #4] 80049da: 2220 movs r2, #32 80049dc: 67da str r2, [r3, #124] @ 0x7c huart->RxState = HAL_UART_STATE_READY; 80049de: 687b ldr r3, [r7, #4] 80049e0: 2220 movs r2, #32 80049e2: f8c3 2080 str.w r2, [r3, #128] @ 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80049e6: 687b ldr r3, [r7, #4] 80049e8: 2200 movs r2, #0 80049ea: 661a str r2, [r3, #96] @ 0x60 huart->RxEventType = HAL_UART_RXEVENT_TC; 80049ec: 687b ldr r3, [r7, #4] 80049ee: 2200 movs r2, #0 80049f0: 665a str r2, [r3, #100] @ 0x64 __HAL_UNLOCK(huart); 80049f2: 687b ldr r3, [r7, #4] 80049f4: 2200 movs r2, #0 80049f6: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_OK; 80049fa: 2300 movs r3, #0 } 80049fc: 4618 mov r0, r3 80049fe: 3758 adds r7, #88 @ 0x58 8004a00: 46bd mov sp, r7 8004a02: bd80 pop {r7, pc} 08004a04 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8004a04: b580 push {r7, lr} 8004a06: b084 sub sp, #16 8004a08: af00 add r7, sp, #0 8004a0a: 60f8 str r0, [r7, #12] 8004a0c: 60b9 str r1, [r7, #8] 8004a0e: 603b str r3, [r7, #0] 8004a10: 4613 mov r3, r2 8004a12: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004a14: e04f b.n 8004ab6 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004a16: 69bb ldr r3, [r7, #24] 8004a18: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8004a1c: d04b beq.n 8004ab6 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8004a1e: f7fc fd79 bl 8001514 8004a22: 4602 mov r2, r0 8004a24: 683b ldr r3, [r7, #0] 8004a26: 1ad3 subs r3, r2, r3 8004a28: 69ba ldr r2, [r7, #24] 8004a2a: 429a cmp r2, r3 8004a2c: d302 bcc.n 8004a34 8004a2e: 69bb ldr r3, [r7, #24] 8004a30: 2b00 cmp r3, #0 8004a32: d101 bne.n 8004a38 { return HAL_TIMEOUT; 8004a34: 2303 movs r3, #3 8004a36: e04e b.n 8004ad6 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8004a38: 68fb ldr r3, [r7, #12] 8004a3a: 681b ldr r3, [r3, #0] 8004a3c: 681b ldr r3, [r3, #0] 8004a3e: f003 0304 and.w r3, r3, #4 8004a42: 2b00 cmp r3, #0 8004a44: d037 beq.n 8004ab6 8004a46: 68bb ldr r3, [r7, #8] 8004a48: 2b80 cmp r3, #128 @ 0x80 8004a4a: d034 beq.n 8004ab6 8004a4c: 68bb ldr r3, [r7, #8] 8004a4e: 2b40 cmp r3, #64 @ 0x40 8004a50: d031 beq.n 8004ab6 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8004a52: 68fb ldr r3, [r7, #12] 8004a54: 681b ldr r3, [r3, #0] 8004a56: 69db ldr r3, [r3, #28] 8004a58: f003 0308 and.w r3, r3, #8 8004a5c: 2b08 cmp r3, #8 8004a5e: d110 bne.n 8004a82 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8004a60: 68fb ldr r3, [r7, #12] 8004a62: 681b ldr r3, [r3, #0] 8004a64: 2208 movs r2, #8 8004a66: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8004a68: 68f8 ldr r0, [r7, #12] 8004a6a: f000 f838 bl 8004ade huart->ErrorCode = HAL_UART_ERROR_ORE; 8004a6e: 68fb ldr r3, [r7, #12] 8004a70: 2208 movs r2, #8 8004a72: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 8004a76: 68fb ldr r3, [r7, #12] 8004a78: 2200 movs r2, #0 8004a7a: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_ERROR; 8004a7e: 2301 movs r3, #1 8004a80: e029 b.n 8004ad6 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8004a82: 68fb ldr r3, [r7, #12] 8004a84: 681b ldr r3, [r3, #0] 8004a86: 69db ldr r3, [r3, #28] 8004a88: f403 6300 and.w r3, r3, #2048 @ 0x800 8004a8c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004a90: d111 bne.n 8004ab6 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8004a92: 68fb ldr r3, [r7, #12] 8004a94: 681b ldr r3, [r3, #0] 8004a96: f44f 6200 mov.w r2, #2048 @ 0x800 8004a9a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8004a9c: 68f8 ldr r0, [r7, #12] 8004a9e: f000 f81e bl 8004ade huart->ErrorCode = HAL_UART_ERROR_RTO; 8004aa2: 68fb ldr r3, [r7, #12] 8004aa4: 2220 movs r2, #32 8004aa6: f8c3 2084 str.w r2, [r3, #132] @ 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 8004aaa: 68fb ldr r3, [r7, #12] 8004aac: 2200 movs r2, #0 8004aae: f883 2078 strb.w r2, [r3, #120] @ 0x78 return HAL_TIMEOUT; 8004ab2: 2303 movs r3, #3 8004ab4: e00f b.n 8004ad6 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004ab6: 68fb ldr r3, [r7, #12] 8004ab8: 681b ldr r3, [r3, #0] 8004aba: 69da ldr r2, [r3, #28] 8004abc: 68bb ldr r3, [r7, #8] 8004abe: 4013 ands r3, r2 8004ac0: 68ba ldr r2, [r7, #8] 8004ac2: 429a cmp r2, r3 8004ac4: bf0c ite eq 8004ac6: 2301 moveq r3, #1 8004ac8: 2300 movne r3, #0 8004aca: b2db uxtb r3, r3 8004acc: 461a mov r2, r3 8004ace: 79fb ldrb r3, [r7, #7] 8004ad0: 429a cmp r2, r3 8004ad2: d0a0 beq.n 8004a16 } } } } return HAL_OK; 8004ad4: 2300 movs r3, #0 } 8004ad6: 4618 mov r0, r3 8004ad8: 3710 adds r7, #16 8004ada: 46bd mov sp, r7 8004adc: bd80 pop {r7, pc} 08004ade : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8004ade: b480 push {r7} 8004ae0: b095 sub sp, #84 @ 0x54 8004ae2: af00 add r7, sp, #0 8004ae4: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); #else ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8004ae6: 687b ldr r3, [r7, #4] 8004ae8: 681b ldr r3, [r3, #0] 8004aea: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004aec: 6b7b ldr r3, [r7, #52] @ 0x34 8004aee: e853 3f00 ldrex r3, [r3] 8004af2: 633b str r3, [r7, #48] @ 0x30 return(result); 8004af4: 6b3b ldr r3, [r7, #48] @ 0x30 8004af6: f423 7390 bic.w r3, r3, #288 @ 0x120 8004afa: 64fb str r3, [r7, #76] @ 0x4c 8004afc: 687b ldr r3, [r7, #4] 8004afe: 681b ldr r3, [r3, #0] 8004b00: 461a mov r2, r3 8004b02: 6cfb ldr r3, [r7, #76] @ 0x4c 8004b04: 643b str r3, [r7, #64] @ 0x40 8004b06: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004b08: 6bf9 ldr r1, [r7, #60] @ 0x3c 8004b0a: 6c3a ldr r2, [r7, #64] @ 0x40 8004b0c: e841 2300 strex r3, r2, [r1] 8004b10: 63bb str r3, [r7, #56] @ 0x38 return(result); 8004b12: 6bbb ldr r3, [r7, #56] @ 0x38 8004b14: 2b00 cmp r3, #0 8004b16: d1e6 bne.n 8004ae6 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004b18: 687b ldr r3, [r7, #4] 8004b1a: 681b ldr r3, [r3, #0] 8004b1c: 3308 adds r3, #8 8004b1e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004b20: 6a3b ldr r3, [r7, #32] 8004b22: e853 3f00 ldrex r3, [r3] 8004b26: 61fb str r3, [r7, #28] return(result); 8004b28: 69fb ldr r3, [r7, #28] 8004b2a: f023 0301 bic.w r3, r3, #1 8004b2e: 64bb str r3, [r7, #72] @ 0x48 8004b30: 687b ldr r3, [r7, #4] 8004b32: 681b ldr r3, [r3, #0] 8004b34: 3308 adds r3, #8 8004b36: 6cba ldr r2, [r7, #72] @ 0x48 8004b38: 62fa str r2, [r7, #44] @ 0x2c 8004b3a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004b3c: 6ab9 ldr r1, [r7, #40] @ 0x28 8004b3e: 6afa ldr r2, [r7, #44] @ 0x2c 8004b40: e841 2300 strex r3, r2, [r1] 8004b44: 627b str r3, [r7, #36] @ 0x24 return(result); 8004b46: 6a7b ldr r3, [r7, #36] @ 0x24 8004b48: 2b00 cmp r3, #0 8004b4a: d1e5 bne.n 8004b18 #endif /* USART_CR1_FIFOEN */ /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8004b4c: 687b ldr r3, [r7, #4] 8004b4e: 6e1b ldr r3, [r3, #96] @ 0x60 8004b50: 2b01 cmp r3, #1 8004b52: d118 bne.n 8004b86 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004b54: 687b ldr r3, [r7, #4] 8004b56: 681b ldr r3, [r3, #0] 8004b58: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004b5a: 68fb ldr r3, [r7, #12] 8004b5c: e853 3f00 ldrex r3, [r3] 8004b60: 60bb str r3, [r7, #8] return(result); 8004b62: 68bb ldr r3, [r7, #8] 8004b64: f023 0310 bic.w r3, r3, #16 8004b68: 647b str r3, [r7, #68] @ 0x44 8004b6a: 687b ldr r3, [r7, #4] 8004b6c: 681b ldr r3, [r3, #0] 8004b6e: 461a mov r2, r3 8004b70: 6c7b ldr r3, [r7, #68] @ 0x44 8004b72: 61bb str r3, [r7, #24] 8004b74: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004b76: 6979 ldr r1, [r7, #20] 8004b78: 69ba ldr r2, [r7, #24] 8004b7a: e841 2300 strex r3, r2, [r1] 8004b7e: 613b str r3, [r7, #16] return(result); 8004b80: 693b ldr r3, [r7, #16] 8004b82: 2b00 cmp r3, #0 8004b84: d1e6 bne.n 8004b54 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004b86: 687b ldr r3, [r7, #4] 8004b88: 2220 movs r2, #32 8004b8a: f8c3 2080 str.w r2, [r3, #128] @ 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004b8e: 687b ldr r3, [r7, #4] 8004b90: 2200 movs r2, #0 8004b92: 661a str r2, [r3, #96] @ 0x60 /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8004b94: 687b ldr r3, [r7, #4] 8004b96: 2200 movs r2, #0 8004b98: 669a str r2, [r3, #104] @ 0x68 } 8004b9a: bf00 nop 8004b9c: 3754 adds r7, #84 @ 0x54 8004b9e: 46bd mov sp, r7 8004ba0: f85d 7b04 ldr.w r7, [sp], #4 8004ba4: 4770 bx lr 08004ba6 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8004ba6: b084 sub sp, #16 8004ba8: b580 push {r7, lr} 8004baa: b084 sub sp, #16 8004bac: af00 add r7, sp, #0 8004bae: 6078 str r0, [r7, #4] 8004bb0: f107 001c add.w r0, r7, #28 8004bb4: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8004bb8: 687b ldr r3, [r7, #4] 8004bba: 68db ldr r3, [r3, #12] 8004bbc: f043 0240 orr.w r2, r3, #64 @ 0x40 8004bc0: 687b ldr r3, [r7, #4] 8004bc2: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8004bc4: 6878 ldr r0, [r7, #4] 8004bc6: f000 fa69 bl 800509c 8004bca: 4603 mov r3, r0 8004bcc: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8004bce: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 8004bd2: 2b00 cmp r3, #0 8004bd4: d106 bne.n 8004be4 { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8004bd6: 687b ldr r3, [r7, #4] 8004bd8: 6b9b ldr r3, [r3, #56] @ 0x38 8004bda: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8004bde: 687b ldr r3, [r7, #4] 8004be0: 639a str r2, [r3, #56] @ 0x38 8004be2: e005 b.n 8004bf0 } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8004be4: 687b ldr r3, [r7, #4] 8004be6: 6b9b ldr r3, [r3, #56] @ 0x38 8004be8: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8004bec: 687b ldr r3, [r7, #4] 8004bee: 639a str r2, [r3, #56] @ 0x38 } return ret; 8004bf0: 7bfb ldrb r3, [r7, #15] } 8004bf2: 4618 mov r0, r3 8004bf4: 3710 adds r7, #16 8004bf6: 46bd mov sp, r7 8004bf8: e8bd 4080 ldmia.w sp!, {r7, lr} 8004bfc: b004 add sp, #16 8004bfe: 4770 bx lr 08004c00 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8004c00: b480 push {r7} 8004c02: b083 sub sp, #12 8004c04: af00 add r7, sp, #0 8004c06: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 8004c08: 687b ldr r3, [r7, #4] 8004c0a: 689b ldr r3, [r3, #8] 8004c0c: f023 0201 bic.w r2, r3, #1 8004c10: 687b ldr r3, [r7, #4] 8004c12: 609a str r2, [r3, #8] return HAL_OK; 8004c14: 2300 movs r3, #0 } 8004c16: 4618 mov r0, r3 8004c18: 370c adds r7, #12 8004c1a: 46bd mov sp, r7 8004c1c: f85d 7b04 ldr.w r7, [sp], #4 8004c20: 4770 bx lr 08004c22 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode) { 8004c22: b580 push {r7, lr} 8004c24: b084 sub sp, #16 8004c26: af00 add r7, sp, #0 8004c28: 6078 str r0, [r7, #4] 8004c2a: 460b mov r3, r1 8004c2c: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 8004c2e: 2300 movs r3, #0 8004c30: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8004c32: 687b ldr r3, [r7, #4] 8004c34: 68db ldr r3, [r3, #12] 8004c36: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 8004c3a: 687b ldr r3, [r7, #4] 8004c3c: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 8004c3e: 78fb ldrb r3, [r7, #3] 8004c40: 2b01 cmp r3, #1 8004c42: d115 bne.n 8004c70 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8004c44: 687b ldr r3, [r7, #4] 8004c46: 68db ldr r3, [r3, #12] 8004c48: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 8004c4c: 687b ldr r3, [r7, #4] 8004c4e: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8004c50: 200a movs r0, #10 8004c52: f7fc fc6b bl 800152c ms += 10U; 8004c56: 68fb ldr r3, [r7, #12] 8004c58: 330a adds r3, #10 8004c5a: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8004c5c: 6878 ldr r0, [r7, #4] 8004c5e: f000 fa0f bl 8005080 8004c62: 4603 mov r3, r0 8004c64: 2b01 cmp r3, #1 8004c66: d01e beq.n 8004ca6 8004c68: 68fb ldr r3, [r7, #12] 8004c6a: 2bc7 cmp r3, #199 @ 0xc7 8004c6c: d9f0 bls.n 8004c50 8004c6e: e01a b.n 8004ca6 } else if (mode == USB_DEVICE_MODE) 8004c70: 78fb ldrb r3, [r7, #3] 8004c72: 2b00 cmp r3, #0 8004c74: d115 bne.n 8004ca2 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8004c76: 687b ldr r3, [r7, #4] 8004c78: 68db ldr r3, [r3, #12] 8004c7a: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 8004c7e: 687b ldr r3, [r7, #4] 8004c80: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8004c82: 200a movs r0, #10 8004c84: f7fc fc52 bl 800152c ms += 10U; 8004c88: 68fb ldr r3, [r7, #12] 8004c8a: 330a adds r3, #10 8004c8c: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8004c8e: 6878 ldr r0, [r7, #4] 8004c90: f000 f9f6 bl 8005080 8004c94: 4603 mov r3, r0 8004c96: 2b00 cmp r3, #0 8004c98: d005 beq.n 8004ca6 8004c9a: 68fb ldr r3, [r7, #12] 8004c9c: 2bc7 cmp r3, #199 @ 0xc7 8004c9e: d9f0 bls.n 8004c82 8004ca0: e001 b.n 8004ca6 } else { return HAL_ERROR; 8004ca2: 2301 movs r3, #1 8004ca4: e005 b.n 8004cb2 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 8004ca6: 68fb ldr r3, [r7, #12] 8004ca8: 2bc8 cmp r3, #200 @ 0xc8 8004caa: d101 bne.n 8004cb0 { return HAL_ERROR; 8004cac: 2301 movs r3, #1 8004cae: e000 b.n 8004cb2 } return HAL_OK; 8004cb0: 2300 movs r3, #0 } 8004cb2: 4618 mov r0, r3 8004cb4: 3710 adds r7, #16 8004cb6: 46bd mov sp, r7 8004cb8: bd80 pop {r7, pc} ... 08004cbc : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8004cbc: b084 sub sp, #16 8004cbe: b580 push {r7, lr} 8004cc0: b086 sub sp, #24 8004cc2: af00 add r7, sp, #0 8004cc4: 6078 str r0, [r7, #4] 8004cc6: f107 0024 add.w r0, r7, #36 @ 0x24 8004cca: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 8004cce: 2300 movs r3, #0 8004cd0: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8004cd2: 687b ldr r3, [r7, #4] 8004cd4: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 8004cd6: 2300 movs r3, #0 8004cd8: 613b str r3, [r7, #16] 8004cda: e009 b.n 8004cf0 { USBx->DIEPTXF[i] = 0U; 8004cdc: 687a ldr r2, [r7, #4] 8004cde: 693b ldr r3, [r7, #16] 8004ce0: 3340 adds r3, #64 @ 0x40 8004ce2: 009b lsls r3, r3, #2 8004ce4: 4413 add r3, r2 8004ce6: 2200 movs r2, #0 8004ce8: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 8004cea: 693b ldr r3, [r7, #16] 8004cec: 3301 adds r3, #1 8004cee: 613b str r3, [r7, #16] 8004cf0: 693b ldr r3, [r7, #16] 8004cf2: 2b0e cmp r3, #14 8004cf4: d9f2 bls.n 8004cdc } /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8004cf6: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8004cfa: 2b00 cmp r3, #0 8004cfc: d11c bne.n 8004d38 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8004cfe: 68fb ldr r3, [r7, #12] 8004d00: f503 6300 add.w r3, r3, #2048 @ 0x800 8004d04: 685b ldr r3, [r3, #4] 8004d06: 68fa ldr r2, [r7, #12] 8004d08: f502 6200 add.w r2, r2, #2048 @ 0x800 8004d0c: f043 0302 orr.w r3, r3, #2 8004d10: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 8004d12: 687b ldr r3, [r7, #4] 8004d14: 6b9b ldr r3, [r3, #56] @ 0x38 8004d16: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 8004d1a: 687b ldr r3, [r7, #4] 8004d1c: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 8004d1e: 687b ldr r3, [r7, #4] 8004d20: 681b ldr r3, [r3, #0] 8004d22: f043 0240 orr.w r2, r3, #64 @ 0x40 8004d26: 687b ldr r3, [r7, #4] 8004d28: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8004d2a: 687b ldr r3, [r7, #4] 8004d2c: 681b ldr r3, [r3, #0] 8004d2e: f043 0280 orr.w r2, r3, #128 @ 0x80 8004d32: 687b ldr r3, [r7, #4] 8004d34: 601a str r2, [r3, #0] 8004d36: e005 b.n 8004d44 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8004d38: 687b ldr r3, [r7, #4] 8004d3a: 6b9b ldr r3, [r3, #56] @ 0x38 8004d3c: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8004d40: 687b ldr r3, [r7, #4] 8004d42: 639a str r2, [r3, #56] @ 0x38 } /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8004d44: 68fb ldr r3, [r7, #12] 8004d46: f503 6360 add.w r3, r3, #3584 @ 0xe00 8004d4a: 461a mov r2, r3 8004d4c: 2300 movs r3, #0 8004d4e: 6013 str r3, [r2, #0] /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 8004d50: 2103 movs r1, #3 8004d52: 6878 ldr r0, [r7, #4] 8004d54: f000 f95a bl 800500c /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 8004d58: 2110 movs r1, #16 8004d5a: 6878 ldr r0, [r7, #4] 8004d5c: f000 f8f6 bl 8004f4c 8004d60: 4603 mov r3, r0 8004d62: 2b00 cmp r3, #0 8004d64: d001 beq.n 8004d6a { ret = HAL_ERROR; 8004d66: 2301 movs r3, #1 8004d68: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 8004d6a: 6878 ldr r0, [r7, #4] 8004d6c: f000 f920 bl 8004fb0 8004d70: 4603 mov r3, r0 8004d72: 2b00 cmp r3, #0 8004d74: d001 beq.n 8004d7a { ret = HAL_ERROR; 8004d76: 2301 movs r3, #1 8004d78: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 8004d7a: 68fb ldr r3, [r7, #12] 8004d7c: f503 6300 add.w r3, r3, #2048 @ 0x800 8004d80: 461a mov r2, r3 8004d82: 2300 movs r3, #0 8004d84: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 8004d86: 68fb ldr r3, [r7, #12] 8004d88: f503 6300 add.w r3, r3, #2048 @ 0x800 8004d8c: 461a mov r2, r3 8004d8e: 2300 movs r3, #0 8004d90: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 8004d92: 68fb ldr r3, [r7, #12] 8004d94: f503 6300 add.w r3, r3, #2048 @ 0x800 8004d98: 461a mov r2, r3 8004d9a: 2300 movs r3, #0 8004d9c: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8004d9e: 2300 movs r3, #0 8004da0: 613b str r3, [r7, #16] 8004da2: e043 b.n 8004e2c { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8004da4: 693b ldr r3, [r7, #16] 8004da6: 015a lsls r2, r3, #5 8004da8: 68fb ldr r3, [r7, #12] 8004daa: 4413 add r3, r2 8004dac: f503 6310 add.w r3, r3, #2304 @ 0x900 8004db0: 681b ldr r3, [r3, #0] 8004db2: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8004db6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8004dba: d118 bne.n 8004dee { if (i == 0U) 8004dbc: 693b ldr r3, [r7, #16] 8004dbe: 2b00 cmp r3, #0 8004dc0: d10a bne.n 8004dd8 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 8004dc2: 693b ldr r3, [r7, #16] 8004dc4: 015a lsls r2, r3, #5 8004dc6: 68fb ldr r3, [r7, #12] 8004dc8: 4413 add r3, r2 8004dca: f503 6310 add.w r3, r3, #2304 @ 0x900 8004dce: 461a mov r2, r3 8004dd0: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8004dd4: 6013 str r3, [r2, #0] 8004dd6: e013 b.n 8004e00 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 8004dd8: 693b ldr r3, [r7, #16] 8004dda: 015a lsls r2, r3, #5 8004ddc: 68fb ldr r3, [r7, #12] 8004dde: 4413 add r3, r2 8004de0: f503 6310 add.w r3, r3, #2304 @ 0x900 8004de4: 461a mov r2, r3 8004de6: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8004dea: 6013 str r3, [r2, #0] 8004dec: e008 b.n 8004e00 } } else { USBx_INEP(i)->DIEPCTL = 0U; 8004dee: 693b ldr r3, [r7, #16] 8004df0: 015a lsls r2, r3, #5 8004df2: 68fb ldr r3, [r7, #12] 8004df4: 4413 add r3, r2 8004df6: f503 6310 add.w r3, r3, #2304 @ 0x900 8004dfa: 461a mov r2, r3 8004dfc: 2300 movs r3, #0 8004dfe: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8004e00: 693b ldr r3, [r7, #16] 8004e02: 015a lsls r2, r3, #5 8004e04: 68fb ldr r3, [r7, #12] 8004e06: 4413 add r3, r2 8004e08: f503 6310 add.w r3, r3, #2304 @ 0x900 8004e0c: 461a mov r2, r3 8004e0e: 2300 movs r3, #0 8004e10: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 8004e12: 693b ldr r3, [r7, #16] 8004e14: 015a lsls r2, r3, #5 8004e16: 68fb ldr r3, [r7, #12] 8004e18: 4413 add r3, r2 8004e1a: f503 6310 add.w r3, r3, #2304 @ 0x900 8004e1e: 461a mov r2, r3 8004e20: f64f 337f movw r3, #64383 @ 0xfb7f 8004e24: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8004e26: 693b ldr r3, [r7, #16] 8004e28: 3301 adds r3, #1 8004e2a: 613b str r3, [r7, #16] 8004e2c: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8004e30: 461a mov r2, r3 8004e32: 693b ldr r3, [r7, #16] 8004e34: 4293 cmp r3, r2 8004e36: d3b5 bcc.n 8004da4 } for (i = 0U; i < cfg.dev_endpoints; i++) 8004e38: 2300 movs r3, #0 8004e3a: 613b str r3, [r7, #16] 8004e3c: e043 b.n 8004ec6 { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8004e3e: 693b ldr r3, [r7, #16] 8004e40: 015a lsls r2, r3, #5 8004e42: 68fb ldr r3, [r7, #12] 8004e44: 4413 add r3, r2 8004e46: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004e4a: 681b ldr r3, [r3, #0] 8004e4c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8004e50: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8004e54: d118 bne.n 8004e88 { if (i == 0U) 8004e56: 693b ldr r3, [r7, #16] 8004e58: 2b00 cmp r3, #0 8004e5a: d10a bne.n 8004e72 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 8004e5c: 693b ldr r3, [r7, #16] 8004e5e: 015a lsls r2, r3, #5 8004e60: 68fb ldr r3, [r7, #12] 8004e62: 4413 add r3, r2 8004e64: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004e68: 461a mov r2, r3 8004e6a: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8004e6e: 6013 str r3, [r2, #0] 8004e70: e013 b.n 8004e9a } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 8004e72: 693b ldr r3, [r7, #16] 8004e74: 015a lsls r2, r3, #5 8004e76: 68fb ldr r3, [r7, #12] 8004e78: 4413 add r3, r2 8004e7a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004e7e: 461a mov r2, r3 8004e80: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8004e84: 6013 str r3, [r2, #0] 8004e86: e008 b.n 8004e9a } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 8004e88: 693b ldr r3, [r7, #16] 8004e8a: 015a lsls r2, r3, #5 8004e8c: 68fb ldr r3, [r7, #12] 8004e8e: 4413 add r3, r2 8004e90: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004e94: 461a mov r2, r3 8004e96: 2300 movs r3, #0 8004e98: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 8004e9a: 693b ldr r3, [r7, #16] 8004e9c: 015a lsls r2, r3, #5 8004e9e: 68fb ldr r3, [r7, #12] 8004ea0: 4413 add r3, r2 8004ea2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004ea6: 461a mov r2, r3 8004ea8: 2300 movs r3, #0 8004eaa: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8004eac: 693b ldr r3, [r7, #16] 8004eae: 015a lsls r2, r3, #5 8004eb0: 68fb ldr r3, [r7, #12] 8004eb2: 4413 add r3, r2 8004eb4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004eb8: 461a mov r2, r3 8004eba: f64f 337f movw r3, #64383 @ 0xfb7f 8004ebe: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8004ec0: 693b ldr r3, [r7, #16] 8004ec2: 3301 adds r3, #1 8004ec4: 613b str r3, [r7, #16] 8004ec6: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8004eca: 461a mov r2, r3 8004ecc: 693b ldr r3, [r7, #16] 8004ece: 4293 cmp r3, r2 8004ed0: d3b5 bcc.n 8004e3e } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 8004ed2: 68fb ldr r3, [r7, #12] 8004ed4: f503 6300 add.w r3, r3, #2048 @ 0x800 8004ed8: 691b ldr r3, [r3, #16] 8004eda: 68fa ldr r2, [r7, #12] 8004edc: f502 6200 add.w r2, r2, #2048 @ 0x800 8004ee0: f423 7380 bic.w r3, r3, #256 @ 0x100 8004ee4: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 8004ee6: 687b ldr r3, [r7, #4] 8004ee8: 2200 movs r2, #0 8004eea: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 8004eec: 687b ldr r3, [r7, #4] 8004eee: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 8004ef2: 615a str r2, [r3, #20] /* Enable the common interrupts */ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 8004ef4: 687b ldr r3, [r7, #4] 8004ef6: 699b ldr r3, [r3, #24] 8004ef8: f043 0210 orr.w r2, r3, #16 8004efc: 687b ldr r3, [r7, #4] 8004efe: 619a str r2, [r3, #24] /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8004f00: 687b ldr r3, [r7, #4] 8004f02: 699a ldr r2, [r3, #24] 8004f04: 4b10 ldr r3, [pc, #64] @ (8004f48 ) 8004f06: 4313 orrs r3, r2 8004f08: 687a ldr r2, [r7, #4] 8004f0a: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 8004f0c: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 8004f10: 2b00 cmp r3, #0 8004f12: d005 beq.n 8004f20 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 8004f14: 687b ldr r3, [r7, #4] 8004f16: 699b ldr r3, [r3, #24] 8004f18: f043 0208 orr.w r2, r3, #8 8004f1c: 687b ldr r3, [r7, #4] 8004f1e: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 8004f20: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8004f24: 2b01 cmp r3, #1 8004f26: d107 bne.n 8004f38 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 8004f28: 687b ldr r3, [r7, #4] 8004f2a: 699b ldr r3, [r3, #24] 8004f2c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8004f30: f043 0304 orr.w r3, r3, #4 8004f34: 687a ldr r2, [r7, #4] 8004f36: 6193 str r3, [r2, #24] } return ret; 8004f38: 7dfb ldrb r3, [r7, #23] } 8004f3a: 4618 mov r0, r3 8004f3c: 3718 adds r7, #24 8004f3e: 46bd mov sp, r7 8004f40: e8bd 4080 ldmia.w sp!, {r7, lr} 8004f44: b004 add sp, #16 8004f46: 4770 bx lr 8004f48: 803c3800 .word 0x803c3800 08004f4c : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 8004f4c: b480 push {r7} 8004f4e: b085 sub sp, #20 8004f50: af00 add r7, sp, #0 8004f52: 6078 str r0, [r7, #4] 8004f54: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8004f56: 2300 movs r3, #0 8004f58: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8004f5a: 68fb ldr r3, [r7, #12] 8004f5c: 3301 adds r3, #1 8004f5e: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8004f60: 68fb ldr r3, [r7, #12] 8004f62: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8004f66: d901 bls.n 8004f6c { return HAL_TIMEOUT; 8004f68: 2303 movs r3, #3 8004f6a: e01b b.n 8004fa4 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8004f6c: 687b ldr r3, [r7, #4] 8004f6e: 691b ldr r3, [r3, #16] 8004f70: 2b00 cmp r3, #0 8004f72: daf2 bge.n 8004f5a /* Flush TX Fifo */ count = 0U; 8004f74: 2300 movs r3, #0 8004f76: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 8004f78: 683b ldr r3, [r7, #0] 8004f7a: 019b lsls r3, r3, #6 8004f7c: f043 0220 orr.w r2, r3, #32 8004f80: 687b ldr r3, [r7, #4] 8004f82: 611a str r2, [r3, #16] do { count++; 8004f84: 68fb ldr r3, [r7, #12] 8004f86: 3301 adds r3, #1 8004f88: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8004f8a: 68fb ldr r3, [r7, #12] 8004f8c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8004f90: d901 bls.n 8004f96 { return HAL_TIMEOUT; 8004f92: 2303 movs r3, #3 8004f94: e006 b.n 8004fa4 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8004f96: 687b ldr r3, [r7, #4] 8004f98: 691b ldr r3, [r3, #16] 8004f9a: f003 0320 and.w r3, r3, #32 8004f9e: 2b20 cmp r3, #32 8004fa0: d0f0 beq.n 8004f84 return HAL_OK; 8004fa2: 2300 movs r3, #0 } 8004fa4: 4618 mov r0, r3 8004fa6: 3714 adds r7, #20 8004fa8: 46bd mov sp, r7 8004faa: f85d 7b04 ldr.w r7, [sp], #4 8004fae: 4770 bx lr 08004fb0 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 8004fb0: b480 push {r7} 8004fb2: b085 sub sp, #20 8004fb4: af00 add r7, sp, #0 8004fb6: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8004fb8: 2300 movs r3, #0 8004fba: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8004fbc: 68fb ldr r3, [r7, #12] 8004fbe: 3301 adds r3, #1 8004fc0: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8004fc2: 68fb ldr r3, [r7, #12] 8004fc4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8004fc8: d901 bls.n 8004fce { return HAL_TIMEOUT; 8004fca: 2303 movs r3, #3 8004fcc: e018 b.n 8005000 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8004fce: 687b ldr r3, [r7, #4] 8004fd0: 691b ldr r3, [r3, #16] 8004fd2: 2b00 cmp r3, #0 8004fd4: daf2 bge.n 8004fbc /* Flush RX Fifo */ count = 0U; 8004fd6: 2300 movs r3, #0 8004fd8: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 8004fda: 687b ldr r3, [r7, #4] 8004fdc: 2210 movs r2, #16 8004fde: 611a str r2, [r3, #16] do { count++; 8004fe0: 68fb ldr r3, [r7, #12] 8004fe2: 3301 adds r3, #1 8004fe4: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8004fe6: 68fb ldr r3, [r7, #12] 8004fe8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8004fec: d901 bls.n 8004ff2 { return HAL_TIMEOUT; 8004fee: 2303 movs r3, #3 8004ff0: e006 b.n 8005000 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 8004ff2: 687b ldr r3, [r7, #4] 8004ff4: 691b ldr r3, [r3, #16] 8004ff6: f003 0310 and.w r3, r3, #16 8004ffa: 2b10 cmp r3, #16 8004ffc: d0f0 beq.n 8004fe0 return HAL_OK; 8004ffe: 2300 movs r3, #0 } 8005000: 4618 mov r0, r3 8005002: 3714 adds r7, #20 8005004: 46bd mov sp, r7 8005006: f85d 7b04 ldr.w r7, [sp], #4 800500a: 4770 bx lr 0800500c : * This parameter can be one of these values: * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 800500c: b480 push {r7} 800500e: b085 sub sp, #20 8005010: af00 add r7, sp, #0 8005012: 6078 str r0, [r7, #4] 8005014: 460b mov r3, r1 8005016: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8005018: 687b ldr r3, [r7, #4] 800501a: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 800501c: 68fb ldr r3, [r7, #12] 800501e: f503 6300 add.w r3, r3, #2048 @ 0x800 8005022: 681a ldr r2, [r3, #0] 8005024: 78fb ldrb r3, [r7, #3] 8005026: 68f9 ldr r1, [r7, #12] 8005028: f501 6100 add.w r1, r1, #2048 @ 0x800 800502c: 4313 orrs r3, r2 800502e: 600b str r3, [r1, #0] return HAL_OK; 8005030: 2300 movs r3, #0 } 8005032: 4618 mov r0, r3 8005034: 3714 adds r7, #20 8005036: 46bd mov sp, r7 8005038: f85d 7b04 ldr.w r7, [sp], #4 800503c: 4770 bx lr 0800503e : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 800503e: b480 push {r7} 8005040: b085 sub sp, #20 8005042: af00 add r7, sp, #0 8005044: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8005046: 687b ldr r3, [r7, #4] 8005048: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 800504a: 68fb ldr r3, [r7, #12] 800504c: f503 6360 add.w r3, r3, #3584 @ 0xe00 8005050: 681b ldr r3, [r3, #0] 8005052: 68fa ldr r2, [r7, #12] 8005054: f502 6260 add.w r2, r2, #3584 @ 0xe00 8005058: f023 0303 bic.w r3, r3, #3 800505c: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 800505e: 68fb ldr r3, [r7, #12] 8005060: f503 6300 add.w r3, r3, #2048 @ 0x800 8005064: 685b ldr r3, [r3, #4] 8005066: 68fa ldr r2, [r7, #12] 8005068: f502 6200 add.w r2, r2, #2048 @ 0x800 800506c: f043 0302 orr.w r3, r3, #2 8005070: 6053 str r3, [r2, #4] return HAL_OK; 8005072: 2300 movs r3, #0 } 8005074: 4618 mov r0, r3 8005076: 3714 adds r7, #20 8005078: 46bd mov sp, r7 800507a: f85d 7b04 ldr.w r7, [sp], #4 800507e: 4770 bx lr 08005080 : * This parameter can be one of these values: * 0 : Host * 1 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 8005080: b480 push {r7} 8005082: b083 sub sp, #12 8005084: af00 add r7, sp, #0 8005086: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 8005088: 687b ldr r3, [r7, #4] 800508a: 695b ldr r3, [r3, #20] 800508c: f003 0301 and.w r3, r3, #1 } 8005090: 4618 mov r0, r3 8005092: 370c adds r7, #12 8005094: 46bd mov sp, r7 8005096: f85d 7b04 ldr.w r7, [sp], #4 800509a: 4770 bx lr 0800509c : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 800509c: b480 push {r7} 800509e: b085 sub sp, #20 80050a0: af00 add r7, sp, #0 80050a2: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80050a4: 2300 movs r3, #0 80050a6: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80050a8: 68fb ldr r3, [r7, #12] 80050aa: 3301 adds r3, #1 80050ac: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80050ae: 68fb ldr r3, [r7, #12] 80050b0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80050b4: d901 bls.n 80050ba { return HAL_TIMEOUT; 80050b6: 2303 movs r3, #3 80050b8: e01b b.n 80050f2 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80050ba: 687b ldr r3, [r7, #4] 80050bc: 691b ldr r3, [r3, #16] 80050be: 2b00 cmp r3, #0 80050c0: daf2 bge.n 80050a8 /* Core Soft Reset */ count = 0U; 80050c2: 2300 movs r3, #0 80050c4: 60fb str r3, [r7, #12] USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 80050c6: 687b ldr r3, [r7, #4] 80050c8: 691b ldr r3, [r3, #16] 80050ca: f043 0201 orr.w r2, r3, #1 80050ce: 687b ldr r3, [r7, #4] 80050d0: 611a str r2, [r3, #16] do { count++; 80050d2: 68fb ldr r3, [r7, #12] 80050d4: 3301 adds r3, #1 80050d6: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80050d8: 68fb ldr r3, [r7, #12] 80050da: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80050de: d901 bls.n 80050e4 { return HAL_TIMEOUT; 80050e0: 2303 movs r3, #3 80050e2: e006 b.n 80050f2 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 80050e4: 687b ldr r3, [r7, #4] 80050e6: 691b ldr r3, [r3, #16] 80050e8: f003 0301 and.w r3, r3, #1 80050ec: 2b01 cmp r3, #1 80050ee: d0f0 beq.n 80050d2 return HAL_OK; 80050f0: 2300 movs r3, #0 } 80050f2: 4618 mov r0, r3 80050f4: 3714 adds r7, #20 80050f6: 46bd mov sp, r7 80050f8: f85d 7b04 ldr.w r7, [sp], #4 80050fc: 4770 bx lr ... 08005100 <__NVIC_SetPriority>: { 8005100: b480 push {r7} 8005102: b083 sub sp, #12 8005104: af00 add r7, sp, #0 8005106: 4603 mov r3, r0 8005108: 6039 str r1, [r7, #0] 800510a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800510c: f997 3007 ldrsb.w r3, [r7, #7] 8005110: 2b00 cmp r3, #0 8005112: db0a blt.n 800512a <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8005114: 683b ldr r3, [r7, #0] 8005116: b2da uxtb r2, r3 8005118: 490c ldr r1, [pc, #48] @ (800514c <__NVIC_SetPriority+0x4c>) 800511a: f997 3007 ldrsb.w r3, [r7, #7] 800511e: 0112 lsls r2, r2, #4 8005120: b2d2 uxtb r2, r2 8005122: 440b add r3, r1 8005124: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8005128: e00a b.n 8005140 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800512a: 683b ldr r3, [r7, #0] 800512c: b2da uxtb r2, r3 800512e: 4908 ldr r1, [pc, #32] @ (8005150 <__NVIC_SetPriority+0x50>) 8005130: 79fb ldrb r3, [r7, #7] 8005132: f003 030f and.w r3, r3, #15 8005136: 3b04 subs r3, #4 8005138: 0112 lsls r2, r2, #4 800513a: b2d2 uxtb r2, r2 800513c: 440b add r3, r1 800513e: 761a strb r2, [r3, #24] } 8005140: bf00 nop 8005142: 370c adds r7, #12 8005144: 46bd mov sp, r7 8005146: f85d 7b04 ldr.w r7, [sp], #4 800514a: 4770 bx lr 800514c: e000e100 .word 0xe000e100 8005150: e000ed00 .word 0xe000ed00 08005154 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 8005154: b580 push {r7, lr} 8005156: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 8005158: 4b05 ldr r3, [pc, #20] @ (8005170 ) 800515a: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 800515c: f001 fd0c bl 8006b78 8005160: 4603 mov r3, r0 8005162: 2b01 cmp r3, #1 8005164: d001 beq.n 800516a /* Call tick handler */ xPortSysTickHandler(); 8005166: f002 fb07 bl 8007778 } } 800516a: bf00 nop 800516c: bd80 pop {r7, pc} 800516e: bf00 nop 8005170: e000e010 .word 0xe000e010 08005174 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 8005174: b580 push {r7, lr} 8005176: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 8005178: 2100 movs r1, #0 800517a: f06f 0004 mvn.w r0, #4 800517e: f7ff ffbf bl 8005100 <__NVIC_SetPriority> #endif } 8005182: bf00 nop 8005184: bd80 pop {r7, pc} ... 08005188 : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 8005188: b480 push {r7} 800518a: b083 sub sp, #12 800518c: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800518e: f3ef 8305 mrs r3, IPSR 8005192: 603b str r3, [r7, #0] return(result); 8005194: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8005196: 2b00 cmp r3, #0 8005198: d003 beq.n 80051a2 stat = osErrorISR; 800519a: f06f 0305 mvn.w r3, #5 800519e: 607b str r3, [r7, #4] 80051a0: e00c b.n 80051bc } else { if (KernelState == osKernelInactive) { 80051a2: 4b0a ldr r3, [pc, #40] @ (80051cc ) 80051a4: 681b ldr r3, [r3, #0] 80051a6: 2b00 cmp r3, #0 80051a8: d105 bne.n 80051b6 EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 80051aa: 4b08 ldr r3, [pc, #32] @ (80051cc ) 80051ac: 2201 movs r2, #1 80051ae: 601a str r2, [r3, #0] stat = osOK; 80051b0: 2300 movs r3, #0 80051b2: 607b str r3, [r7, #4] 80051b4: e002 b.n 80051bc } else { stat = osError; 80051b6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80051ba: 607b str r3, [r7, #4] } } return (stat); 80051bc: 687b ldr r3, [r7, #4] } 80051be: 4618 mov r0, r3 80051c0: 370c adds r7, #12 80051c2: 46bd mov sp, r7 80051c4: f85d 7b04 ldr.w r7, [sp], #4 80051c8: 4770 bx lr 80051ca: bf00 nop 80051cc: 2000081c .word 0x2000081c 080051d0 : } return (state); } osStatus_t osKernelStart (void) { 80051d0: b580 push {r7, lr} 80051d2: b082 sub sp, #8 80051d4: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80051d6: f3ef 8305 mrs r3, IPSR 80051da: 603b str r3, [r7, #0] return(result); 80051dc: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 80051de: 2b00 cmp r3, #0 80051e0: d003 beq.n 80051ea stat = osErrorISR; 80051e2: f06f 0305 mvn.w r3, #5 80051e6: 607b str r3, [r7, #4] 80051e8: e010 b.n 800520c } else { if (KernelState == osKernelReady) { 80051ea: 4b0b ldr r3, [pc, #44] @ (8005218 ) 80051ec: 681b ldr r3, [r3, #0] 80051ee: 2b01 cmp r3, #1 80051f0: d109 bne.n 8005206 /* Ensure SVC priority is at the reset value */ SVC_Setup(); 80051f2: f7ff ffbf bl 8005174 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 80051f6: 4b08 ldr r3, [pc, #32] @ (8005218 ) 80051f8: 2202 movs r2, #2 80051fa: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 80051fc: f001 f858 bl 80062b0 stat = osOK; 8005200: 2300 movs r3, #0 8005202: 607b str r3, [r7, #4] 8005204: e002 b.n 800520c } else { stat = osError; 8005206: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800520a: 607b str r3, [r7, #4] } } return (stat); 800520c: 687b ldr r3, [r7, #4] } 800520e: 4618 mov r0, r3 8005210: 3708 adds r7, #8 8005212: 46bd mov sp, r7 8005214: bd80 pop {r7, pc} 8005216: bf00 nop 8005218: 2000081c .word 0x2000081c 0800521c : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 800521c: b480 push {r7} 800521e: b085 sub sp, #20 8005220: af00 add r7, sp, #0 8005222: 60f8 str r0, [r7, #12] 8005224: 60b9 str r1, [r7, #8] 8005226: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 8005228: 68fb ldr r3, [r7, #12] 800522a: 4a07 ldr r2, [pc, #28] @ (8005248 ) 800522c: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 800522e: 68bb ldr r3, [r7, #8] 8005230: 4a06 ldr r2, [pc, #24] @ (800524c ) 8005232: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8005234: 687b ldr r3, [r7, #4] 8005236: 2280 movs r2, #128 @ 0x80 8005238: 601a str r2, [r3, #0] } 800523a: bf00 nop 800523c: 3714 adds r7, #20 800523e: 46bd mov sp, r7 8005240: f85d 7b04 ldr.w r7, [sp], #4 8005244: 4770 bx lr 8005246: bf00 nop 8005248: 20000820 .word 0x20000820 800524c: 200008c8 .word 0x200008c8 08005250 : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 8005250: b480 push {r7} 8005252: b085 sub sp, #20 8005254: af00 add r7, sp, #0 8005256: 60f8 str r0, [r7, #12] 8005258: 60b9 str r1, [r7, #8] 800525a: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 800525c: 68fb ldr r3, [r7, #12] 800525e: 4a07 ldr r2, [pc, #28] @ (800527c ) 8005260: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 8005262: 68bb ldr r3, [r7, #8] 8005264: 4a06 ldr r2, [pc, #24] @ (8005280 ) 8005266: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8005268: 687b ldr r3, [r7, #4] 800526a: f44f 7280 mov.w r2, #256 @ 0x100 800526e: 601a str r2, [r3, #0] } 8005270: bf00 nop 8005272: 3714 adds r7, #20 8005274: 46bd mov sp, r7 8005276: f85d 7b04 ldr.w r7, [sp], #4 800527a: 4770 bx lr 800527c: 20000ac8 .word 0x20000ac8 8005280: 20000b70 .word 0x20000b70 08005284 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8005284: b480 push {r7} 8005286: b083 sub sp, #12 8005288: af00 add r7, sp, #0 800528a: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 800528c: 687b ldr r3, [r7, #4] 800528e: f103 0208 add.w r2, r3, #8 8005292: 687b ldr r3, [r7, #4] 8005294: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 8005296: 687b ldr r3, [r7, #4] 8005298: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800529c: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 800529e: 687b ldr r3, [r7, #4] 80052a0: f103 0208 add.w r2, r3, #8 80052a4: 687b ldr r3, [r7, #4] 80052a6: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80052a8: 687b ldr r3, [r7, #4] 80052aa: f103 0208 add.w r2, r3, #8 80052ae: 687b ldr r3, [r7, #4] 80052b0: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 80052b2: 687b ldr r3, [r7, #4] 80052b4: 2200 movs r2, #0 80052b6: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 80052b8: bf00 nop 80052ba: 370c adds r7, #12 80052bc: 46bd mov sp, r7 80052be: f85d 7b04 ldr.w r7, [sp], #4 80052c2: 4770 bx lr 080052c4 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 80052c4: b480 push {r7} 80052c6: b083 sub sp, #12 80052c8: af00 add r7, sp, #0 80052ca: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 80052cc: 687b ldr r3, [r7, #4] 80052ce: 2200 movs r2, #0 80052d0: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 80052d2: bf00 nop 80052d4: 370c adds r7, #12 80052d6: 46bd mov sp, r7 80052d8: f85d 7b04 ldr.w r7, [sp], #4 80052dc: 4770 bx lr 080052de : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 80052de: b480 push {r7} 80052e0: b085 sub sp, #20 80052e2: af00 add r7, sp, #0 80052e4: 6078 str r0, [r7, #4] 80052e6: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 80052e8: 687b ldr r3, [r7, #4] 80052ea: 685b ldr r3, [r3, #4] 80052ec: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 80052ee: 683b ldr r3, [r7, #0] 80052f0: 68fa ldr r2, [r7, #12] 80052f2: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 80052f4: 68fb ldr r3, [r7, #12] 80052f6: 689a ldr r2, [r3, #8] 80052f8: 683b ldr r3, [r7, #0] 80052fa: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 80052fc: 68fb ldr r3, [r7, #12] 80052fe: 689b ldr r3, [r3, #8] 8005300: 683a ldr r2, [r7, #0] 8005302: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8005304: 68fb ldr r3, [r7, #12] 8005306: 683a ldr r2, [r7, #0] 8005308: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 800530a: 683b ldr r3, [r7, #0] 800530c: 687a ldr r2, [r7, #4] 800530e: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8005310: 687b ldr r3, [r7, #4] 8005312: 681b ldr r3, [r3, #0] 8005314: 1c5a adds r2, r3, #1 8005316: 687b ldr r3, [r7, #4] 8005318: 601a str r2, [r3, #0] } 800531a: bf00 nop 800531c: 3714 adds r7, #20 800531e: 46bd mov sp, r7 8005320: f85d 7b04 ldr.w r7, [sp], #4 8005324: 4770 bx lr 08005326 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8005326: b480 push {r7} 8005328: b085 sub sp, #20 800532a: af00 add r7, sp, #0 800532c: 6078 str r0, [r7, #4] 800532e: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8005330: 683b ldr r3, [r7, #0] 8005332: 681b ldr r3, [r3, #0] 8005334: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8005336: 68bb ldr r3, [r7, #8] 8005338: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800533c: d103 bne.n 8005346 { pxIterator = pxList->xListEnd.pxPrevious; 800533e: 687b ldr r3, [r7, #4] 8005340: 691b ldr r3, [r3, #16] 8005342: 60fb str r3, [r7, #12] 8005344: e00c b.n 8005360 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8005346: 687b ldr r3, [r7, #4] 8005348: 3308 adds r3, #8 800534a: 60fb str r3, [r7, #12] 800534c: e002 b.n 8005354 800534e: 68fb ldr r3, [r7, #12] 8005350: 685b ldr r3, [r3, #4] 8005352: 60fb str r3, [r7, #12] 8005354: 68fb ldr r3, [r7, #12] 8005356: 685b ldr r3, [r3, #4] 8005358: 681b ldr r3, [r3, #0] 800535a: 68ba ldr r2, [r7, #8] 800535c: 429a cmp r2, r3 800535e: d2f6 bcs.n 800534e /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8005360: 68fb ldr r3, [r7, #12] 8005362: 685a ldr r2, [r3, #4] 8005364: 683b ldr r3, [r7, #0] 8005366: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8005368: 683b ldr r3, [r7, #0] 800536a: 685b ldr r3, [r3, #4] 800536c: 683a ldr r2, [r7, #0] 800536e: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8005370: 683b ldr r3, [r7, #0] 8005372: 68fa ldr r2, [r7, #12] 8005374: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8005376: 68fb ldr r3, [r7, #12] 8005378: 683a ldr r2, [r7, #0] 800537a: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 800537c: 683b ldr r3, [r7, #0] 800537e: 687a ldr r2, [r7, #4] 8005380: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8005382: 687b ldr r3, [r7, #4] 8005384: 681b ldr r3, [r3, #0] 8005386: 1c5a adds r2, r3, #1 8005388: 687b ldr r3, [r7, #4] 800538a: 601a str r2, [r3, #0] } 800538c: bf00 nop 800538e: 3714 adds r7, #20 8005390: 46bd mov sp, r7 8005392: f85d 7b04 ldr.w r7, [sp], #4 8005396: 4770 bx lr 08005398 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8005398: b480 push {r7} 800539a: b085 sub sp, #20 800539c: af00 add r7, sp, #0 800539e: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 80053a0: 687b ldr r3, [r7, #4] 80053a2: 691b ldr r3, [r3, #16] 80053a4: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 80053a6: 687b ldr r3, [r7, #4] 80053a8: 685b ldr r3, [r3, #4] 80053aa: 687a ldr r2, [r7, #4] 80053ac: 6892 ldr r2, [r2, #8] 80053ae: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 80053b0: 687b ldr r3, [r7, #4] 80053b2: 689b ldr r3, [r3, #8] 80053b4: 687a ldr r2, [r7, #4] 80053b6: 6852 ldr r2, [r2, #4] 80053b8: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 80053ba: 68fb ldr r3, [r7, #12] 80053bc: 685b ldr r3, [r3, #4] 80053be: 687a ldr r2, [r7, #4] 80053c0: 429a cmp r2, r3 80053c2: d103 bne.n 80053cc { pxList->pxIndex = pxItemToRemove->pxPrevious; 80053c4: 687b ldr r3, [r7, #4] 80053c6: 689a ldr r2, [r3, #8] 80053c8: 68fb ldr r3, [r7, #12] 80053ca: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 80053cc: 687b ldr r3, [r7, #4] 80053ce: 2200 movs r2, #0 80053d0: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 80053d2: 68fb ldr r3, [r7, #12] 80053d4: 681b ldr r3, [r3, #0] 80053d6: 1e5a subs r2, r3, #1 80053d8: 68fb ldr r3, [r7, #12] 80053da: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 80053dc: 68fb ldr r3, [r7, #12] 80053de: 681b ldr r3, [r3, #0] } 80053e0: 4618 mov r0, r3 80053e2: 3714 adds r7, #20 80053e4: 46bd mov sp, r7 80053e6: f85d 7b04 ldr.w r7, [sp], #4 80053ea: 4770 bx lr 080053ec : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 80053ec: b580 push {r7, lr} 80053ee: b084 sub sp, #16 80053f0: af00 add r7, sp, #0 80053f2: 6078 str r0, [r7, #4] 80053f4: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 80053f6: 687b ldr r3, [r7, #4] 80053f8: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 80053fa: 68fb ldr r3, [r7, #12] 80053fc: 2b00 cmp r3, #0 80053fe: d10b bne.n 8005418 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8005400: f04f 0350 mov.w r3, #80 @ 0x50 8005404: f383 8811 msr BASEPRI, r3 8005408: f3bf 8f6f isb sy 800540c: f3bf 8f4f dsb sy 8005410: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8005412: bf00 nop 8005414: bf00 nop 8005416: e7fd b.n 8005414 taskENTER_CRITICAL(); 8005418: f002 f91e bl 8007658 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800541c: 68fb ldr r3, [r7, #12] 800541e: 681a ldr r2, [r3, #0] 8005420: 68fb ldr r3, [r7, #12] 8005422: 6bdb ldr r3, [r3, #60] @ 0x3c 8005424: 68f9 ldr r1, [r7, #12] 8005426: 6c09 ldr r1, [r1, #64] @ 0x40 8005428: fb01 f303 mul.w r3, r1, r3 800542c: 441a add r2, r3 800542e: 68fb ldr r3, [r7, #12] 8005430: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8005432: 68fb ldr r3, [r7, #12] 8005434: 2200 movs r2, #0 8005436: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8005438: 68fb ldr r3, [r7, #12] 800543a: 681a ldr r2, [r3, #0] 800543c: 68fb ldr r3, [r7, #12] 800543e: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8005440: 68fb ldr r3, [r7, #12] 8005442: 681a ldr r2, [r3, #0] 8005444: 68fb ldr r3, [r7, #12] 8005446: 6bdb ldr r3, [r3, #60] @ 0x3c 8005448: 3b01 subs r3, #1 800544a: 68f9 ldr r1, [r7, #12] 800544c: 6c09 ldr r1, [r1, #64] @ 0x40 800544e: fb01 f303 mul.w r3, r1, r3 8005452: 441a add r2, r3 8005454: 68fb ldr r3, [r7, #12] 8005456: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8005458: 68fb ldr r3, [r7, #12] 800545a: 22ff movs r2, #255 @ 0xff 800545c: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8005460: 68fb ldr r3, [r7, #12] 8005462: 22ff movs r2, #255 @ 0xff 8005464: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8005468: 683b ldr r3, [r7, #0] 800546a: 2b00 cmp r3, #0 800546c: d114 bne.n 8005498 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800546e: 68fb ldr r3, [r7, #12] 8005470: 691b ldr r3, [r3, #16] 8005472: 2b00 cmp r3, #0 8005474: d01a beq.n 80054ac { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8005476: 68fb ldr r3, [r7, #12] 8005478: 3310 adds r3, #16 800547a: 4618 mov r0, r3 800547c: f001 f9b6 bl 80067ec 8005480: 4603 mov r3, r0 8005482: 2b00 cmp r3, #0 8005484: d012 beq.n 80054ac { queueYIELD_IF_USING_PREEMPTION(); 8005486: 4b0d ldr r3, [pc, #52] @ (80054bc ) 8005488: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800548c: 601a str r2, [r3, #0] 800548e: f3bf 8f4f dsb sy 8005492: f3bf 8f6f isb sy 8005496: e009 b.n 80054ac } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8005498: 68fb ldr r3, [r7, #12] 800549a: 3310 adds r3, #16 800549c: 4618 mov r0, r3 800549e: f7ff fef1 bl 8005284 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 80054a2: 68fb ldr r3, [r7, #12] 80054a4: 3324 adds r3, #36 @ 0x24 80054a6: 4618 mov r0, r3 80054a8: f7ff feec bl 8005284 } } taskEXIT_CRITICAL(); 80054ac: f002 f906 bl 80076bc /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 80054b0: 2301 movs r3, #1 } 80054b2: 4618 mov r0, r3 80054b4: 3710 adds r7, #16 80054b6: 46bd mov sp, r7 80054b8: bd80 pop {r7, pc} 80054ba: bf00 nop 80054bc: e000ed04 .word 0xe000ed04 080054c0 : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 80054c0: b580 push {r7, lr} 80054c2: b08e sub sp, #56 @ 0x38 80054c4: af02 add r7, sp, #8 80054c6: 60f8 str r0, [r7, #12] 80054c8: 60b9 str r1, [r7, #8] 80054ca: 607a str r2, [r7, #4] 80054cc: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 80054ce: 68fb ldr r3, [r7, #12] 80054d0: 2b00 cmp r3, #0 80054d2: d10b bne.n 80054ec __asm volatile 80054d4: f04f 0350 mov.w r3, #80 @ 0x50 80054d8: f383 8811 msr BASEPRI, r3 80054dc: f3bf 8f6f isb sy 80054e0: f3bf 8f4f dsb sy 80054e4: 62bb str r3, [r7, #40] @ 0x28 } 80054e6: bf00 nop 80054e8: bf00 nop 80054ea: e7fd b.n 80054e8 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 80054ec: 683b ldr r3, [r7, #0] 80054ee: 2b00 cmp r3, #0 80054f0: d10b bne.n 800550a __asm volatile 80054f2: f04f 0350 mov.w r3, #80 @ 0x50 80054f6: f383 8811 msr BASEPRI, r3 80054fa: f3bf 8f6f isb sy 80054fe: f3bf 8f4f dsb sy 8005502: 627b str r3, [r7, #36] @ 0x24 } 8005504: bf00 nop 8005506: bf00 nop 8005508: e7fd b.n 8005506 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 800550a: 687b ldr r3, [r7, #4] 800550c: 2b00 cmp r3, #0 800550e: d002 beq.n 8005516 8005510: 68bb ldr r3, [r7, #8] 8005512: 2b00 cmp r3, #0 8005514: d001 beq.n 800551a 8005516: 2301 movs r3, #1 8005518: e000 b.n 800551c 800551a: 2300 movs r3, #0 800551c: 2b00 cmp r3, #0 800551e: d10b bne.n 8005538 __asm volatile 8005520: f04f 0350 mov.w r3, #80 @ 0x50 8005524: f383 8811 msr BASEPRI, r3 8005528: f3bf 8f6f isb sy 800552c: f3bf 8f4f dsb sy 8005530: 623b str r3, [r7, #32] } 8005532: bf00 nop 8005534: bf00 nop 8005536: e7fd b.n 8005534 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8005538: 687b ldr r3, [r7, #4] 800553a: 2b00 cmp r3, #0 800553c: d102 bne.n 8005544 800553e: 68bb ldr r3, [r7, #8] 8005540: 2b00 cmp r3, #0 8005542: d101 bne.n 8005548 8005544: 2301 movs r3, #1 8005546: e000 b.n 800554a 8005548: 2300 movs r3, #0 800554a: 2b00 cmp r3, #0 800554c: d10b bne.n 8005566 __asm volatile 800554e: f04f 0350 mov.w r3, #80 @ 0x50 8005552: f383 8811 msr BASEPRI, r3 8005556: f3bf 8f6f isb sy 800555a: f3bf 8f4f dsb sy 800555e: 61fb str r3, [r7, #28] } 8005560: bf00 nop 8005562: bf00 nop 8005564: e7fd b.n 8005562 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8005566: 2350 movs r3, #80 @ 0x50 8005568: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 800556a: 697b ldr r3, [r7, #20] 800556c: 2b50 cmp r3, #80 @ 0x50 800556e: d00b beq.n 8005588 __asm volatile 8005570: f04f 0350 mov.w r3, #80 @ 0x50 8005574: f383 8811 msr BASEPRI, r3 8005578: f3bf 8f6f isb sy 800557c: f3bf 8f4f dsb sy 8005580: 61bb str r3, [r7, #24] } 8005582: bf00 nop 8005584: bf00 nop 8005586: e7fd b.n 8005584 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8005588: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 800558a: 683b ldr r3, [r7, #0] 800558c: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 800558e: 6afb ldr r3, [r7, #44] @ 0x2c 8005590: 2b00 cmp r3, #0 8005592: d00d beq.n 80055b0 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8005594: 6afb ldr r3, [r7, #44] @ 0x2c 8005596: 2201 movs r2, #1 8005598: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 800559c: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 80055a0: 6afb ldr r3, [r7, #44] @ 0x2c 80055a2: 9300 str r3, [sp, #0] 80055a4: 4613 mov r3, r2 80055a6: 687a ldr r2, [r7, #4] 80055a8: 68b9 ldr r1, [r7, #8] 80055aa: 68f8 ldr r0, [r7, #12] 80055ac: f000 f805 bl 80055ba { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 80055b0: 6afb ldr r3, [r7, #44] @ 0x2c } 80055b2: 4618 mov r0, r3 80055b4: 3730 adds r7, #48 @ 0x30 80055b6: 46bd mov sp, r7 80055b8: bd80 pop {r7, pc} 080055ba : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 80055ba: b580 push {r7, lr} 80055bc: b084 sub sp, #16 80055be: af00 add r7, sp, #0 80055c0: 60f8 str r0, [r7, #12] 80055c2: 60b9 str r1, [r7, #8] 80055c4: 607a str r2, [r7, #4] 80055c6: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 80055c8: 68bb ldr r3, [r7, #8] 80055ca: 2b00 cmp r3, #0 80055cc: d103 bne.n 80055d6 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 80055ce: 69bb ldr r3, [r7, #24] 80055d0: 69ba ldr r2, [r7, #24] 80055d2: 601a str r2, [r3, #0] 80055d4: e002 b.n 80055dc } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 80055d6: 69bb ldr r3, [r7, #24] 80055d8: 687a ldr r2, [r7, #4] 80055da: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 80055dc: 69bb ldr r3, [r7, #24] 80055de: 68fa ldr r2, [r7, #12] 80055e0: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 80055e2: 69bb ldr r3, [r7, #24] 80055e4: 68ba ldr r2, [r7, #8] 80055e6: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 80055e8: 2101 movs r1, #1 80055ea: 69b8 ldr r0, [r7, #24] 80055ec: f7ff fefe bl 80053ec #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 80055f0: 69bb ldr r3, [r7, #24] 80055f2: 78fa ldrb r2, [r7, #3] 80055f4: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 80055f8: bf00 nop 80055fa: 3710 adds r7, #16 80055fc: 46bd mov sp, r7 80055fe: bd80 pop {r7, pc} 08005600 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8005600: b580 push {r7, lr} 8005602: b08e sub sp, #56 @ 0x38 8005604: af00 add r7, sp, #0 8005606: 60f8 str r0, [r7, #12] 8005608: 60b9 str r1, [r7, #8] 800560a: 607a str r2, [r7, #4] 800560c: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 800560e: 2300 movs r3, #0 8005610: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8005612: 68fb ldr r3, [r7, #12] 8005614: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8005616: 6b3b ldr r3, [r7, #48] @ 0x30 8005618: 2b00 cmp r3, #0 800561a: d10b bne.n 8005634 __asm volatile 800561c: f04f 0350 mov.w r3, #80 @ 0x50 8005620: f383 8811 msr BASEPRI, r3 8005624: f3bf 8f6f isb sy 8005628: f3bf 8f4f dsb sy 800562c: 62bb str r3, [r7, #40] @ 0x28 } 800562e: bf00 nop 8005630: bf00 nop 8005632: e7fd b.n 8005630 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8005634: 68bb ldr r3, [r7, #8] 8005636: 2b00 cmp r3, #0 8005638: d103 bne.n 8005642 800563a: 6b3b ldr r3, [r7, #48] @ 0x30 800563c: 6c1b ldr r3, [r3, #64] @ 0x40 800563e: 2b00 cmp r3, #0 8005640: d101 bne.n 8005646 8005642: 2301 movs r3, #1 8005644: e000 b.n 8005648 8005646: 2300 movs r3, #0 8005648: 2b00 cmp r3, #0 800564a: d10b bne.n 8005664 __asm volatile 800564c: f04f 0350 mov.w r3, #80 @ 0x50 8005650: f383 8811 msr BASEPRI, r3 8005654: f3bf 8f6f isb sy 8005658: f3bf 8f4f dsb sy 800565c: 627b str r3, [r7, #36] @ 0x24 } 800565e: bf00 nop 8005660: bf00 nop 8005662: e7fd b.n 8005660 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8005664: 683b ldr r3, [r7, #0] 8005666: 2b02 cmp r3, #2 8005668: d103 bne.n 8005672 800566a: 6b3b ldr r3, [r7, #48] @ 0x30 800566c: 6bdb ldr r3, [r3, #60] @ 0x3c 800566e: 2b01 cmp r3, #1 8005670: d101 bne.n 8005676 8005672: 2301 movs r3, #1 8005674: e000 b.n 8005678 8005676: 2300 movs r3, #0 8005678: 2b00 cmp r3, #0 800567a: d10b bne.n 8005694 __asm volatile 800567c: f04f 0350 mov.w r3, #80 @ 0x50 8005680: f383 8811 msr BASEPRI, r3 8005684: f3bf 8f6f isb sy 8005688: f3bf 8f4f dsb sy 800568c: 623b str r3, [r7, #32] } 800568e: bf00 nop 8005690: bf00 nop 8005692: e7fd b.n 8005690 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8005694: f001 fa70 bl 8006b78 8005698: 4603 mov r3, r0 800569a: 2b00 cmp r3, #0 800569c: d102 bne.n 80056a4 800569e: 687b ldr r3, [r7, #4] 80056a0: 2b00 cmp r3, #0 80056a2: d101 bne.n 80056a8 80056a4: 2301 movs r3, #1 80056a6: e000 b.n 80056aa 80056a8: 2300 movs r3, #0 80056aa: 2b00 cmp r3, #0 80056ac: d10b bne.n 80056c6 __asm volatile 80056ae: f04f 0350 mov.w r3, #80 @ 0x50 80056b2: f383 8811 msr BASEPRI, r3 80056b6: f3bf 8f6f isb sy 80056ba: f3bf 8f4f dsb sy 80056be: 61fb str r3, [r7, #28] } 80056c0: bf00 nop 80056c2: bf00 nop 80056c4: e7fd b.n 80056c2 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80056c6: f001 ffc7 bl 8007658 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80056ca: 6b3b ldr r3, [r7, #48] @ 0x30 80056cc: 6b9a ldr r2, [r3, #56] @ 0x38 80056ce: 6b3b ldr r3, [r7, #48] @ 0x30 80056d0: 6bdb ldr r3, [r3, #60] @ 0x3c 80056d2: 429a cmp r2, r3 80056d4: d302 bcc.n 80056dc 80056d6: 683b ldr r3, [r7, #0] 80056d8: 2b02 cmp r3, #2 80056da: d129 bne.n 8005730 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80056dc: 683a ldr r2, [r7, #0] 80056de: 68b9 ldr r1, [r7, #8] 80056e0: 6b38 ldr r0, [r7, #48] @ 0x30 80056e2: f000 fa0f bl 8005b04 80056e6: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80056e8: 6b3b ldr r3, [r7, #48] @ 0x30 80056ea: 6a5b ldr r3, [r3, #36] @ 0x24 80056ec: 2b00 cmp r3, #0 80056ee: d010 beq.n 8005712 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80056f0: 6b3b ldr r3, [r7, #48] @ 0x30 80056f2: 3324 adds r3, #36 @ 0x24 80056f4: 4618 mov r0, r3 80056f6: f001 f879 bl 80067ec 80056fa: 4603 mov r3, r0 80056fc: 2b00 cmp r3, #0 80056fe: d013 beq.n 8005728 { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8005700: 4b3f ldr r3, [pc, #252] @ (8005800 ) 8005702: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8005706: 601a str r2, [r3, #0] 8005708: f3bf 8f4f dsb sy 800570c: f3bf 8f6f isb sy 8005710: e00a b.n 8005728 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8005712: 6afb ldr r3, [r7, #44] @ 0x2c 8005714: 2b00 cmp r3, #0 8005716: d007 beq.n 8005728 { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8005718: 4b39 ldr r3, [pc, #228] @ (8005800 ) 800571a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800571e: 601a str r2, [r3, #0] 8005720: f3bf 8f4f dsb sy 8005724: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8005728: f001 ffc8 bl 80076bc return pdPASS; 800572c: 2301 movs r3, #1 800572e: e063 b.n 80057f8 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8005730: 687b ldr r3, [r7, #4] 8005732: 2b00 cmp r3, #0 8005734: d103 bne.n 800573e { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8005736: f001 ffc1 bl 80076bc /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 800573a: 2300 movs r3, #0 800573c: e05c b.n 80057f8 } else if( xEntryTimeSet == pdFALSE ) 800573e: 6b7b ldr r3, [r7, #52] @ 0x34 8005740: 2b00 cmp r3, #0 8005742: d106 bne.n 8005752 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8005744: f107 0314 add.w r3, r7, #20 8005748: 4618 mov r0, r3 800574a: f001 f8b3 bl 80068b4 xEntryTimeSet = pdTRUE; 800574e: 2301 movs r3, #1 8005750: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8005752: f001 ffb3 bl 80076bc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8005756: f000 fe1b bl 8006390 prvLockQueue( pxQueue ); 800575a: f001 ff7d bl 8007658 800575e: 6b3b ldr r3, [r7, #48] @ 0x30 8005760: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8005764: b25b sxtb r3, r3 8005766: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800576a: d103 bne.n 8005774 800576c: 6b3b ldr r3, [r7, #48] @ 0x30 800576e: 2200 movs r2, #0 8005770: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005774: 6b3b ldr r3, [r7, #48] @ 0x30 8005776: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800577a: b25b sxtb r3, r3 800577c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005780: d103 bne.n 800578a 8005782: 6b3b ldr r3, [r7, #48] @ 0x30 8005784: 2200 movs r2, #0 8005786: f883 2045 strb.w r2, [r3, #69] @ 0x45 800578a: f001 ff97 bl 80076bc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 800578e: 1d3a adds r2, r7, #4 8005790: f107 0314 add.w r3, r7, #20 8005794: 4611 mov r1, r2 8005796: 4618 mov r0, r3 8005798: f001 f8a2 bl 80068e0 800579c: 4603 mov r3, r0 800579e: 2b00 cmp r3, #0 80057a0: d124 bne.n 80057ec { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 80057a2: 6b38 ldr r0, [r7, #48] @ 0x30 80057a4: f000 faa6 bl 8005cf4 80057a8: 4603 mov r3, r0 80057aa: 2b00 cmp r3, #0 80057ac: d018 beq.n 80057e0 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 80057ae: 6b3b ldr r3, [r7, #48] @ 0x30 80057b0: 3310 adds r3, #16 80057b2: 687a ldr r2, [r7, #4] 80057b4: 4611 mov r1, r2 80057b6: 4618 mov r0, r3 80057b8: f000 ffc6 bl 8006748 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 80057bc: 6b38 ldr r0, [r7, #48] @ 0x30 80057be: f000 fa31 bl 8005c24 /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 80057c2: f000 fdf3 bl 80063ac 80057c6: 4603 mov r3, r0 80057c8: 2b00 cmp r3, #0 80057ca: f47f af7c bne.w 80056c6 { portYIELD_WITHIN_API(); 80057ce: 4b0c ldr r3, [pc, #48] @ (8005800 ) 80057d0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80057d4: 601a str r2, [r3, #0] 80057d6: f3bf 8f4f dsb sy 80057da: f3bf 8f6f isb sy 80057de: e772 b.n 80056c6 } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 80057e0: 6b38 ldr r0, [r7, #48] @ 0x30 80057e2: f000 fa1f bl 8005c24 ( void ) xTaskResumeAll(); 80057e6: f000 fde1 bl 80063ac 80057ea: e76c b.n 80056c6 } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 80057ec: 6b38 ldr r0, [r7, #48] @ 0x30 80057ee: f000 fa19 bl 8005c24 ( void ) xTaskResumeAll(); 80057f2: f000 fddb bl 80063ac traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 80057f6: 2300 movs r3, #0 } } /*lint -restore */ } 80057f8: 4618 mov r0, r3 80057fa: 3738 adds r7, #56 @ 0x38 80057fc: 46bd mov sp, r7 80057fe: bd80 pop {r7, pc} 8005800: e000ed04 .word 0xe000ed04 08005804 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8005804: b580 push {r7, lr} 8005806: b090 sub sp, #64 @ 0x40 8005808: af00 add r7, sp, #0 800580a: 60f8 str r0, [r7, #12] 800580c: 60b9 str r1, [r7, #8] 800580e: 607a str r2, [r7, #4] 8005810: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8005812: 68fb ldr r3, [r7, #12] 8005814: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 8005816: 6bbb ldr r3, [r7, #56] @ 0x38 8005818: 2b00 cmp r3, #0 800581a: d10b bne.n 8005834 __asm volatile 800581c: f04f 0350 mov.w r3, #80 @ 0x50 8005820: f383 8811 msr BASEPRI, r3 8005824: f3bf 8f6f isb sy 8005828: f3bf 8f4f dsb sy 800582c: 62bb str r3, [r7, #40] @ 0x28 } 800582e: bf00 nop 8005830: bf00 nop 8005832: e7fd b.n 8005830 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8005834: 68bb ldr r3, [r7, #8] 8005836: 2b00 cmp r3, #0 8005838: d103 bne.n 8005842 800583a: 6bbb ldr r3, [r7, #56] @ 0x38 800583c: 6c1b ldr r3, [r3, #64] @ 0x40 800583e: 2b00 cmp r3, #0 8005840: d101 bne.n 8005846 8005842: 2301 movs r3, #1 8005844: e000 b.n 8005848 8005846: 2300 movs r3, #0 8005848: 2b00 cmp r3, #0 800584a: d10b bne.n 8005864 __asm volatile 800584c: f04f 0350 mov.w r3, #80 @ 0x50 8005850: f383 8811 msr BASEPRI, r3 8005854: f3bf 8f6f isb sy 8005858: f3bf 8f4f dsb sy 800585c: 627b str r3, [r7, #36] @ 0x24 } 800585e: bf00 nop 8005860: bf00 nop 8005862: e7fd b.n 8005860 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8005864: 683b ldr r3, [r7, #0] 8005866: 2b02 cmp r3, #2 8005868: d103 bne.n 8005872 800586a: 6bbb ldr r3, [r7, #56] @ 0x38 800586c: 6bdb ldr r3, [r3, #60] @ 0x3c 800586e: 2b01 cmp r3, #1 8005870: d101 bne.n 8005876 8005872: 2301 movs r3, #1 8005874: e000 b.n 8005878 8005876: 2300 movs r3, #0 8005878: 2b00 cmp r3, #0 800587a: d10b bne.n 8005894 __asm volatile 800587c: f04f 0350 mov.w r3, #80 @ 0x50 8005880: f383 8811 msr BASEPRI, r3 8005884: f3bf 8f6f isb sy 8005888: f3bf 8f4f dsb sy 800588c: 623b str r3, [r7, #32] } 800588e: bf00 nop 8005890: bf00 nop 8005892: e7fd b.n 8005890 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8005894: f001 ffc0 bl 8007818 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 8005898: f3ef 8211 mrs r2, BASEPRI 800589c: f04f 0350 mov.w r3, #80 @ 0x50 80058a0: f383 8811 msr BASEPRI, r3 80058a4: f3bf 8f6f isb sy 80058a8: f3bf 8f4f dsb sy 80058ac: 61fa str r2, [r7, #28] 80058ae: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 80058b0: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80058b2: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80058b4: 6bbb ldr r3, [r7, #56] @ 0x38 80058b6: 6b9a ldr r2, [r3, #56] @ 0x38 80058b8: 6bbb ldr r3, [r7, #56] @ 0x38 80058ba: 6bdb ldr r3, [r3, #60] @ 0x3c 80058bc: 429a cmp r2, r3 80058be: d302 bcc.n 80058c6 80058c0: 683b ldr r3, [r7, #0] 80058c2: 2b02 cmp r3, #2 80058c4: d12f bne.n 8005926 { const int8_t cTxLock = pxQueue->cTxLock; 80058c6: 6bbb ldr r3, [r7, #56] @ 0x38 80058c8: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80058cc: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 80058d0: 6bbb ldr r3, [r7, #56] @ 0x38 80058d2: 6b9b ldr r3, [r3, #56] @ 0x38 80058d4: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80058d6: 683a ldr r2, [r7, #0] 80058d8: 68b9 ldr r1, [r7, #8] 80058da: 6bb8 ldr r0, [r7, #56] @ 0x38 80058dc: f000 f912 bl 8005b04 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80058e0: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 80058e4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80058e8: d112 bne.n 8005910 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80058ea: 6bbb ldr r3, [r7, #56] @ 0x38 80058ec: 6a5b ldr r3, [r3, #36] @ 0x24 80058ee: 2b00 cmp r3, #0 80058f0: d016 beq.n 8005920 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80058f2: 6bbb ldr r3, [r7, #56] @ 0x38 80058f4: 3324 adds r3, #36 @ 0x24 80058f6: 4618 mov r0, r3 80058f8: f000 ff78 bl 80067ec 80058fc: 4603 mov r3, r0 80058fe: 2b00 cmp r3, #0 8005900: d00e beq.n 8005920 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8005902: 687b ldr r3, [r7, #4] 8005904: 2b00 cmp r3, #0 8005906: d00b beq.n 8005920 { *pxHigherPriorityTaskWoken = pdTRUE; 8005908: 687b ldr r3, [r7, #4] 800590a: 2201 movs r2, #1 800590c: 601a str r2, [r3, #0] 800590e: e007 b.n 8005920 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 8005910: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8005914: 3301 adds r3, #1 8005916: b2db uxtb r3, r3 8005918: b25a sxtb r2, r3 800591a: 6bbb ldr r3, [r7, #56] @ 0x38 800591c: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8005920: 2301 movs r3, #1 8005922: 63fb str r3, [r7, #60] @ 0x3c { 8005924: e001 b.n 800592a } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 8005926: 2300 movs r3, #0 8005928: 63fb str r3, [r7, #60] @ 0x3c 800592a: 6b7b ldr r3, [r7, #52] @ 0x34 800592c: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 800592e: 697b ldr r3, [r7, #20] 8005930: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 8005934: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8005936: 6bfb ldr r3, [r7, #60] @ 0x3c } 8005938: 4618 mov r0, r3 800593a: 3740 adds r7, #64 @ 0x40 800593c: 46bd mov sp, r7 800593e: bd80 pop {r7, pc} 08005940 : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 8005940: b580 push {r7, lr} 8005942: b08c sub sp, #48 @ 0x30 8005944: af00 add r7, sp, #0 8005946: 60f8 str r0, [r7, #12] 8005948: 60b9 str r1, [r7, #8] 800594a: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 800594c: 2300 movs r3, #0 800594e: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8005950: 68fb ldr r3, [r7, #12] 8005952: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8005954: 6abb ldr r3, [r7, #40] @ 0x28 8005956: 2b00 cmp r3, #0 8005958: d10b bne.n 8005972 __asm volatile 800595a: f04f 0350 mov.w r3, #80 @ 0x50 800595e: f383 8811 msr BASEPRI, r3 8005962: f3bf 8f6f isb sy 8005966: f3bf 8f4f dsb sy 800596a: 623b str r3, [r7, #32] } 800596c: bf00 nop 800596e: bf00 nop 8005970: e7fd b.n 800596e /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8005972: 68bb ldr r3, [r7, #8] 8005974: 2b00 cmp r3, #0 8005976: d103 bne.n 8005980 8005978: 6abb ldr r3, [r7, #40] @ 0x28 800597a: 6c1b ldr r3, [r3, #64] @ 0x40 800597c: 2b00 cmp r3, #0 800597e: d101 bne.n 8005984 8005980: 2301 movs r3, #1 8005982: e000 b.n 8005986 8005984: 2300 movs r3, #0 8005986: 2b00 cmp r3, #0 8005988: d10b bne.n 80059a2 __asm volatile 800598a: f04f 0350 mov.w r3, #80 @ 0x50 800598e: f383 8811 msr BASEPRI, r3 8005992: f3bf 8f6f isb sy 8005996: f3bf 8f4f dsb sy 800599a: 61fb str r3, [r7, #28] } 800599c: bf00 nop 800599e: bf00 nop 80059a0: e7fd b.n 800599e /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80059a2: f001 f8e9 bl 8006b78 80059a6: 4603 mov r3, r0 80059a8: 2b00 cmp r3, #0 80059aa: d102 bne.n 80059b2 80059ac: 687b ldr r3, [r7, #4] 80059ae: 2b00 cmp r3, #0 80059b0: d101 bne.n 80059b6 80059b2: 2301 movs r3, #1 80059b4: e000 b.n 80059b8 80059b6: 2300 movs r3, #0 80059b8: 2b00 cmp r3, #0 80059ba: d10b bne.n 80059d4 __asm volatile 80059bc: f04f 0350 mov.w r3, #80 @ 0x50 80059c0: f383 8811 msr BASEPRI, r3 80059c4: f3bf 8f6f isb sy 80059c8: f3bf 8f4f dsb sy 80059cc: 61bb str r3, [r7, #24] } 80059ce: bf00 nop 80059d0: bf00 nop 80059d2: e7fd b.n 80059d0 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80059d4: f001 fe40 bl 8007658 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80059d8: 6abb ldr r3, [r7, #40] @ 0x28 80059da: 6b9b ldr r3, [r3, #56] @ 0x38 80059dc: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80059de: 6a7b ldr r3, [r7, #36] @ 0x24 80059e0: 2b00 cmp r3, #0 80059e2: d01f beq.n 8005a24 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 80059e4: 68b9 ldr r1, [r7, #8] 80059e6: 6ab8 ldr r0, [r7, #40] @ 0x28 80059e8: f000 f8f6 bl 8005bd8 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80059ec: 6a7b ldr r3, [r7, #36] @ 0x24 80059ee: 1e5a subs r2, r3, #1 80059f0: 6abb ldr r3, [r7, #40] @ 0x28 80059f2: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80059f4: 6abb ldr r3, [r7, #40] @ 0x28 80059f6: 691b ldr r3, [r3, #16] 80059f8: 2b00 cmp r3, #0 80059fa: d00f beq.n 8005a1c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80059fc: 6abb ldr r3, [r7, #40] @ 0x28 80059fe: 3310 adds r3, #16 8005a00: 4618 mov r0, r3 8005a02: f000 fef3 bl 80067ec 8005a06: 4603 mov r3, r0 8005a08: 2b00 cmp r3, #0 8005a0a: d007 beq.n 8005a1c { queueYIELD_IF_USING_PREEMPTION(); 8005a0c: 4b3c ldr r3, [pc, #240] @ (8005b00 ) 8005a0e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8005a12: 601a str r2, [r3, #0] 8005a14: f3bf 8f4f dsb sy 8005a18: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8005a1c: f001 fe4e bl 80076bc return pdPASS; 8005a20: 2301 movs r3, #1 8005a22: e069 b.n 8005af8 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8005a24: 687b ldr r3, [r7, #4] 8005a26: 2b00 cmp r3, #0 8005a28: d103 bne.n 8005a32 { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8005a2a: f001 fe47 bl 80076bc traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8005a2e: 2300 movs r3, #0 8005a30: e062 b.n 8005af8 } else if( xEntryTimeSet == pdFALSE ) 8005a32: 6afb ldr r3, [r7, #44] @ 0x2c 8005a34: 2b00 cmp r3, #0 8005a36: d106 bne.n 8005a46 { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8005a38: f107 0310 add.w r3, r7, #16 8005a3c: 4618 mov r0, r3 8005a3e: f000 ff39 bl 80068b4 xEntryTimeSet = pdTRUE; 8005a42: 2301 movs r3, #1 8005a44: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8005a46: f001 fe39 bl 80076bc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8005a4a: f000 fca1 bl 8006390 prvLockQueue( pxQueue ); 8005a4e: f001 fe03 bl 8007658 8005a52: 6abb ldr r3, [r7, #40] @ 0x28 8005a54: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8005a58: b25b sxtb r3, r3 8005a5a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005a5e: d103 bne.n 8005a68 8005a60: 6abb ldr r3, [r7, #40] @ 0x28 8005a62: 2200 movs r2, #0 8005a64: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005a68: 6abb ldr r3, [r7, #40] @ 0x28 8005a6a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8005a6e: b25b sxtb r3, r3 8005a70: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005a74: d103 bne.n 8005a7e 8005a76: 6abb ldr r3, [r7, #40] @ 0x28 8005a78: 2200 movs r2, #0 8005a7a: f883 2045 strb.w r2, [r3, #69] @ 0x45 8005a7e: f001 fe1d bl 80076bc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8005a82: 1d3a adds r2, r7, #4 8005a84: f107 0310 add.w r3, r7, #16 8005a88: 4611 mov r1, r2 8005a8a: 4618 mov r0, r3 8005a8c: f000 ff28 bl 80068e0 8005a90: 4603 mov r3, r0 8005a92: 2b00 cmp r3, #0 8005a94: d123 bne.n 8005ade { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8005a96: 6ab8 ldr r0, [r7, #40] @ 0x28 8005a98: f000 f916 bl 8005cc8 8005a9c: 4603 mov r3, r0 8005a9e: 2b00 cmp r3, #0 8005aa0: d017 beq.n 8005ad2 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8005aa2: 6abb ldr r3, [r7, #40] @ 0x28 8005aa4: 3324 adds r3, #36 @ 0x24 8005aa6: 687a ldr r2, [r7, #4] 8005aa8: 4611 mov r1, r2 8005aaa: 4618 mov r0, r3 8005aac: f000 fe4c bl 8006748 prvUnlockQueue( pxQueue ); 8005ab0: 6ab8 ldr r0, [r7, #40] @ 0x28 8005ab2: f000 f8b7 bl 8005c24 if( xTaskResumeAll() == pdFALSE ) 8005ab6: f000 fc79 bl 80063ac 8005aba: 4603 mov r3, r0 8005abc: 2b00 cmp r3, #0 8005abe: d189 bne.n 80059d4 { portYIELD_WITHIN_API(); 8005ac0: 4b0f ldr r3, [pc, #60] @ (8005b00 ) 8005ac2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8005ac6: 601a str r2, [r3, #0] 8005ac8: f3bf 8f4f dsb sy 8005acc: f3bf 8f6f isb sy 8005ad0: e780 b.n 80059d4 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 8005ad2: 6ab8 ldr r0, [r7, #40] @ 0x28 8005ad4: f000 f8a6 bl 8005c24 ( void ) xTaskResumeAll(); 8005ad8: f000 fc68 bl 80063ac 8005adc: e77a b.n 80059d4 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 8005ade: 6ab8 ldr r0, [r7, #40] @ 0x28 8005ae0: f000 f8a0 bl 8005c24 ( void ) xTaskResumeAll(); 8005ae4: f000 fc62 bl 80063ac if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8005ae8: 6ab8 ldr r0, [r7, #40] @ 0x28 8005aea: f000 f8ed bl 8005cc8 8005aee: 4603 mov r3, r0 8005af0: 2b00 cmp r3, #0 8005af2: f43f af6f beq.w 80059d4 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8005af6: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8005af8: 4618 mov r0, r3 8005afa: 3730 adds r7, #48 @ 0x30 8005afc: 46bd mov sp, r7 8005afe: bd80 pop {r7, pc} 8005b00: e000ed04 .word 0xe000ed04 08005b04 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 8005b04: b580 push {r7, lr} 8005b06: b086 sub sp, #24 8005b08: af00 add r7, sp, #0 8005b0a: 60f8 str r0, [r7, #12] 8005b0c: 60b9 str r1, [r7, #8] 8005b0e: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8005b10: 2300 movs r3, #0 8005b12: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8005b14: 68fb ldr r3, [r7, #12] 8005b16: 6b9b ldr r3, [r3, #56] @ 0x38 8005b18: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 8005b1a: 68fb ldr r3, [r7, #12] 8005b1c: 6c1b ldr r3, [r3, #64] @ 0x40 8005b1e: 2b00 cmp r3, #0 8005b20: d10d bne.n 8005b3e { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8005b22: 68fb ldr r3, [r7, #12] 8005b24: 681b ldr r3, [r3, #0] 8005b26: 2b00 cmp r3, #0 8005b28: d14d bne.n 8005bc6 { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 8005b2a: 68fb ldr r3, [r7, #12] 8005b2c: 689b ldr r3, [r3, #8] 8005b2e: 4618 mov r0, r3 8005b30: f001 f840 bl 8006bb4 8005b34: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 8005b36: 68fb ldr r3, [r7, #12] 8005b38: 2200 movs r2, #0 8005b3a: 609a str r2, [r3, #8] 8005b3c: e043 b.n 8005bc6 mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8005b3e: 687b ldr r3, [r7, #4] 8005b40: 2b00 cmp r3, #0 8005b42: d119 bne.n 8005b78 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8005b44: 68fb ldr r3, [r7, #12] 8005b46: 6858 ldr r0, [r3, #4] 8005b48: 68fb ldr r3, [r7, #12] 8005b4a: 6c1b ldr r3, [r3, #64] @ 0x40 8005b4c: 461a mov r2, r3 8005b4e: 68b9 ldr r1, [r7, #8] 8005b50: f002 f91e bl 8007d90 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8005b54: 68fb ldr r3, [r7, #12] 8005b56: 685a ldr r2, [r3, #4] 8005b58: 68fb ldr r3, [r7, #12] 8005b5a: 6c1b ldr r3, [r3, #64] @ 0x40 8005b5c: 441a add r2, r3 8005b5e: 68fb ldr r3, [r7, #12] 8005b60: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8005b62: 68fb ldr r3, [r7, #12] 8005b64: 685a ldr r2, [r3, #4] 8005b66: 68fb ldr r3, [r7, #12] 8005b68: 689b ldr r3, [r3, #8] 8005b6a: 429a cmp r2, r3 8005b6c: d32b bcc.n 8005bc6 { pxQueue->pcWriteTo = pxQueue->pcHead; 8005b6e: 68fb ldr r3, [r7, #12] 8005b70: 681a ldr r2, [r3, #0] 8005b72: 68fb ldr r3, [r7, #12] 8005b74: 605a str r2, [r3, #4] 8005b76: e026 b.n 8005bc6 mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 8005b78: 68fb ldr r3, [r7, #12] 8005b7a: 68d8 ldr r0, [r3, #12] 8005b7c: 68fb ldr r3, [r7, #12] 8005b7e: 6c1b ldr r3, [r3, #64] @ 0x40 8005b80: 461a mov r2, r3 8005b82: 68b9 ldr r1, [r7, #8] 8005b84: f002 f904 bl 8007d90 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 8005b88: 68fb ldr r3, [r7, #12] 8005b8a: 68da ldr r2, [r3, #12] 8005b8c: 68fb ldr r3, [r7, #12] 8005b8e: 6c1b ldr r3, [r3, #64] @ 0x40 8005b90: 425b negs r3, r3 8005b92: 441a add r2, r3 8005b94: 68fb ldr r3, [r7, #12] 8005b96: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8005b98: 68fb ldr r3, [r7, #12] 8005b9a: 68da ldr r2, [r3, #12] 8005b9c: 68fb ldr r3, [r7, #12] 8005b9e: 681b ldr r3, [r3, #0] 8005ba0: 429a cmp r2, r3 8005ba2: d207 bcs.n 8005bb4 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 8005ba4: 68fb ldr r3, [r7, #12] 8005ba6: 689a ldr r2, [r3, #8] 8005ba8: 68fb ldr r3, [r7, #12] 8005baa: 6c1b ldr r3, [r3, #64] @ 0x40 8005bac: 425b negs r3, r3 8005bae: 441a add r2, r3 8005bb0: 68fb ldr r3, [r7, #12] 8005bb2: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8005bb4: 687b ldr r3, [r7, #4] 8005bb6: 2b02 cmp r3, #2 8005bb8: d105 bne.n 8005bc6 { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8005bba: 693b ldr r3, [r7, #16] 8005bbc: 2b00 cmp r3, #0 8005bbe: d002 beq.n 8005bc6 { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8005bc0: 693b ldr r3, [r7, #16] 8005bc2: 3b01 subs r3, #1 8005bc4: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8005bc6: 693b ldr r3, [r7, #16] 8005bc8: 1c5a adds r2, r3, #1 8005bca: 68fb ldr r3, [r7, #12] 8005bcc: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8005bce: 697b ldr r3, [r7, #20] } 8005bd0: 4618 mov r0, r3 8005bd2: 3718 adds r7, #24 8005bd4: 46bd mov sp, r7 8005bd6: bd80 pop {r7, pc} 08005bd8 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8005bd8: b580 push {r7, lr} 8005bda: b082 sub sp, #8 8005bdc: af00 add r7, sp, #0 8005bde: 6078 str r0, [r7, #4] 8005be0: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 8005be2: 687b ldr r3, [r7, #4] 8005be4: 6c1b ldr r3, [r3, #64] @ 0x40 8005be6: 2b00 cmp r3, #0 8005be8: d018 beq.n 8005c1c { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8005bea: 687b ldr r3, [r7, #4] 8005bec: 68da ldr r2, [r3, #12] 8005bee: 687b ldr r3, [r7, #4] 8005bf0: 6c1b ldr r3, [r3, #64] @ 0x40 8005bf2: 441a add r2, r3 8005bf4: 687b ldr r3, [r7, #4] 8005bf6: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8005bf8: 687b ldr r3, [r7, #4] 8005bfa: 68da ldr r2, [r3, #12] 8005bfc: 687b ldr r3, [r7, #4] 8005bfe: 689b ldr r3, [r3, #8] 8005c00: 429a cmp r2, r3 8005c02: d303 bcc.n 8005c0c { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 8005c04: 687b ldr r3, [r7, #4] 8005c06: 681a ldr r2, [r3, #0] 8005c08: 687b ldr r3, [r7, #4] 8005c0a: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8005c0c: 687b ldr r3, [r7, #4] 8005c0e: 68d9 ldr r1, [r3, #12] 8005c10: 687b ldr r3, [r7, #4] 8005c12: 6c1b ldr r3, [r3, #64] @ 0x40 8005c14: 461a mov r2, r3 8005c16: 6838 ldr r0, [r7, #0] 8005c18: f002 f8ba bl 8007d90 } } 8005c1c: bf00 nop 8005c1e: 3708 adds r7, #8 8005c20: 46bd mov sp, r7 8005c22: bd80 pop {r7, pc} 08005c24 : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 8005c24: b580 push {r7, lr} 8005c26: b084 sub sp, #16 8005c28: af00 add r7, sp, #0 8005c2a: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 8005c2c: f001 fd14 bl 8007658 { int8_t cTxLock = pxQueue->cTxLock; 8005c30: 687b ldr r3, [r7, #4] 8005c32: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8005c36: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8005c38: e011 b.n 8005c5e } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8005c3a: 687b ldr r3, [r7, #4] 8005c3c: 6a5b ldr r3, [r3, #36] @ 0x24 8005c3e: 2b00 cmp r3, #0 8005c40: d012 beq.n 8005c68 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8005c42: 687b ldr r3, [r7, #4] 8005c44: 3324 adds r3, #36 @ 0x24 8005c46: 4618 mov r0, r3 8005c48: f000 fdd0 bl 80067ec 8005c4c: 4603 mov r3, r0 8005c4e: 2b00 cmp r3, #0 8005c50: d001 beq.n 8005c56 { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 8005c52: f000 fea9 bl 80069a8 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 8005c56: 7bfb ldrb r3, [r7, #15] 8005c58: 3b01 subs r3, #1 8005c5a: b2db uxtb r3, r3 8005c5c: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8005c5e: f997 300f ldrsb.w r3, [r7, #15] 8005c62: 2b00 cmp r3, #0 8005c64: dce9 bgt.n 8005c3a 8005c66: e000 b.n 8005c6a break; 8005c68: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 8005c6a: 687b ldr r3, [r7, #4] 8005c6c: 22ff movs r2, #255 @ 0xff 8005c6e: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 8005c72: f001 fd23 bl 80076bc /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 8005c76: f001 fcef bl 8007658 { int8_t cRxLock = pxQueue->cRxLock; 8005c7a: 687b ldr r3, [r7, #4] 8005c7c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8005c80: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8005c82: e011 b.n 8005ca8 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8005c84: 687b ldr r3, [r7, #4] 8005c86: 691b ldr r3, [r3, #16] 8005c88: 2b00 cmp r3, #0 8005c8a: d012 beq.n 8005cb2 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8005c8c: 687b ldr r3, [r7, #4] 8005c8e: 3310 adds r3, #16 8005c90: 4618 mov r0, r3 8005c92: f000 fdab bl 80067ec 8005c96: 4603 mov r3, r0 8005c98: 2b00 cmp r3, #0 8005c9a: d001 beq.n 8005ca0 { vTaskMissedYield(); 8005c9c: f000 fe84 bl 80069a8 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 8005ca0: 7bbb ldrb r3, [r7, #14] 8005ca2: 3b01 subs r3, #1 8005ca4: b2db uxtb r3, r3 8005ca6: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8005ca8: f997 300e ldrsb.w r3, [r7, #14] 8005cac: 2b00 cmp r3, #0 8005cae: dce9 bgt.n 8005c84 8005cb0: e000 b.n 8005cb4 } else { break; 8005cb2: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8005cb4: 687b ldr r3, [r7, #4] 8005cb6: 22ff movs r2, #255 @ 0xff 8005cb8: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 8005cbc: f001 fcfe bl 80076bc } 8005cc0: bf00 nop 8005cc2: 3710 adds r7, #16 8005cc4: 46bd mov sp, r7 8005cc6: bd80 pop {r7, pc} 08005cc8 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 8005cc8: b580 push {r7, lr} 8005cca: b084 sub sp, #16 8005ccc: af00 add r7, sp, #0 8005cce: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8005cd0: f001 fcc2 bl 8007658 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 8005cd4: 687b ldr r3, [r7, #4] 8005cd6: 6b9b ldr r3, [r3, #56] @ 0x38 8005cd8: 2b00 cmp r3, #0 8005cda: d102 bne.n 8005ce2 { xReturn = pdTRUE; 8005cdc: 2301 movs r3, #1 8005cde: 60fb str r3, [r7, #12] 8005ce0: e001 b.n 8005ce6 } else { xReturn = pdFALSE; 8005ce2: 2300 movs r3, #0 8005ce4: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8005ce6: f001 fce9 bl 80076bc return xReturn; 8005cea: 68fb ldr r3, [r7, #12] } 8005cec: 4618 mov r0, r3 8005cee: 3710 adds r7, #16 8005cf0: 46bd mov sp, r7 8005cf2: bd80 pop {r7, pc} 08005cf4 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 8005cf4: b580 push {r7, lr} 8005cf6: b084 sub sp, #16 8005cf8: af00 add r7, sp, #0 8005cfa: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8005cfc: f001 fcac bl 8007658 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8005d00: 687b ldr r3, [r7, #4] 8005d02: 6b9a ldr r2, [r3, #56] @ 0x38 8005d04: 687b ldr r3, [r7, #4] 8005d06: 6bdb ldr r3, [r3, #60] @ 0x3c 8005d08: 429a cmp r2, r3 8005d0a: d102 bne.n 8005d12 { xReturn = pdTRUE; 8005d0c: 2301 movs r3, #1 8005d0e: 60fb str r3, [r7, #12] 8005d10: e001 b.n 8005d16 } else { xReturn = pdFALSE; 8005d12: 2300 movs r3, #0 8005d14: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8005d16: f001 fcd1 bl 80076bc return xReturn; 8005d1a: 68fb ldr r3, [r7, #12] } 8005d1c: 4618 mov r0, r3 8005d1e: 3710 adds r7, #16 8005d20: 46bd mov sp, r7 8005d22: bd80 pop {r7, pc} 08005d24 : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 8005d24: b480 push {r7} 8005d26: b085 sub sp, #20 8005d28: af00 add r7, sp, #0 8005d2a: 6078 str r0, [r7, #4] 8005d2c: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8005d2e: 2300 movs r3, #0 8005d30: 60fb str r3, [r7, #12] 8005d32: e014 b.n 8005d5e { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 8005d34: 4a0f ldr r2, [pc, #60] @ (8005d74 ) 8005d36: 68fb ldr r3, [r7, #12] 8005d38: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8005d3c: 2b00 cmp r3, #0 8005d3e: d10b bne.n 8005d58 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8005d40: 490c ldr r1, [pc, #48] @ (8005d74 ) 8005d42: 68fb ldr r3, [r7, #12] 8005d44: 683a ldr r2, [r7, #0] 8005d46: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 8005d4a: 4a0a ldr r2, [pc, #40] @ (8005d74 ) 8005d4c: 68fb ldr r3, [r7, #12] 8005d4e: 00db lsls r3, r3, #3 8005d50: 4413 add r3, r2 8005d52: 687a ldr r2, [r7, #4] 8005d54: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 8005d56: e006 b.n 8005d66 for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8005d58: 68fb ldr r3, [r7, #12] 8005d5a: 3301 adds r3, #1 8005d5c: 60fb str r3, [r7, #12] 8005d5e: 68fb ldr r3, [r7, #12] 8005d60: 2b07 cmp r3, #7 8005d62: d9e7 bls.n 8005d34 else { mtCOVERAGE_TEST_MARKER(); } } } 8005d64: bf00 nop 8005d66: bf00 nop 8005d68: 3714 adds r7, #20 8005d6a: 46bd mov sp, r7 8005d6c: f85d 7b04 ldr.w r7, [sp], #4 8005d70: 4770 bx lr 8005d72: bf00 nop 8005d74: 20000f70 .word 0x20000f70 08005d78 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8005d78: b580 push {r7, lr} 8005d7a: b086 sub sp, #24 8005d7c: af00 add r7, sp, #0 8005d7e: 60f8 str r0, [r7, #12] 8005d80: 60b9 str r1, [r7, #8] 8005d82: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 8005d84: 68fb ldr r3, [r7, #12] 8005d86: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 8005d88: f001 fc66 bl 8007658 8005d8c: 697b ldr r3, [r7, #20] 8005d8e: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8005d92: b25b sxtb r3, r3 8005d94: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005d98: d103 bne.n 8005da2 8005d9a: 697b ldr r3, [r7, #20] 8005d9c: 2200 movs r2, #0 8005d9e: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005da2: 697b ldr r3, [r7, #20] 8005da4: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8005da8: b25b sxtb r3, r3 8005daa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005dae: d103 bne.n 8005db8 8005db0: 697b ldr r3, [r7, #20] 8005db2: 2200 movs r2, #0 8005db4: f883 2045 strb.w r2, [r3, #69] @ 0x45 8005db8: f001 fc80 bl 80076bc if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8005dbc: 697b ldr r3, [r7, #20] 8005dbe: 6b9b ldr r3, [r3, #56] @ 0x38 8005dc0: 2b00 cmp r3, #0 8005dc2: d106 bne.n 8005dd2 { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8005dc4: 697b ldr r3, [r7, #20] 8005dc6: 3324 adds r3, #36 @ 0x24 8005dc8: 687a ldr r2, [r7, #4] 8005dca: 68b9 ldr r1, [r7, #8] 8005dcc: 4618 mov r0, r3 8005dce: f000 fce1 bl 8006794 } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8005dd2: 6978 ldr r0, [r7, #20] 8005dd4: f7ff ff26 bl 8005c24 } 8005dd8: bf00 nop 8005dda: 3718 adds r7, #24 8005ddc: 46bd mov sp, r7 8005dde: bd80 pop {r7, pc} 08005de0 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8005de0: b580 push {r7, lr} 8005de2: b08e sub sp, #56 @ 0x38 8005de4: af04 add r7, sp, #16 8005de6: 60f8 str r0, [r7, #12] 8005de8: 60b9 str r1, [r7, #8] 8005dea: 607a str r2, [r7, #4] 8005dec: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8005dee: 6b7b ldr r3, [r7, #52] @ 0x34 8005df0: 2b00 cmp r3, #0 8005df2: d10b bne.n 8005e0c __asm volatile 8005df4: f04f 0350 mov.w r3, #80 @ 0x50 8005df8: f383 8811 msr BASEPRI, r3 8005dfc: f3bf 8f6f isb sy 8005e00: f3bf 8f4f dsb sy 8005e04: 623b str r3, [r7, #32] } 8005e06: bf00 nop 8005e08: bf00 nop 8005e0a: e7fd b.n 8005e08 configASSERT( pxTaskBuffer != NULL ); 8005e0c: 6bbb ldr r3, [r7, #56] @ 0x38 8005e0e: 2b00 cmp r3, #0 8005e10: d10b bne.n 8005e2a __asm volatile 8005e12: f04f 0350 mov.w r3, #80 @ 0x50 8005e16: f383 8811 msr BASEPRI, r3 8005e1a: f3bf 8f6f isb sy 8005e1e: f3bf 8f4f dsb sy 8005e22: 61fb str r3, [r7, #28] } 8005e24: bf00 nop 8005e26: bf00 nop 8005e28: e7fd b.n 8005e26 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8005e2a: 23a8 movs r3, #168 @ 0xa8 8005e2c: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8005e2e: 693b ldr r3, [r7, #16] 8005e30: 2ba8 cmp r3, #168 @ 0xa8 8005e32: d00b beq.n 8005e4c __asm volatile 8005e34: f04f 0350 mov.w r3, #80 @ 0x50 8005e38: f383 8811 msr BASEPRI, r3 8005e3c: f3bf 8f6f isb sy 8005e40: f3bf 8f4f dsb sy 8005e44: 61bb str r3, [r7, #24] } 8005e46: bf00 nop 8005e48: bf00 nop 8005e4a: e7fd b.n 8005e48 ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8005e4c: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8005e4e: 6bbb ldr r3, [r7, #56] @ 0x38 8005e50: 2b00 cmp r3, #0 8005e52: d01e beq.n 8005e92 8005e54: 6b7b ldr r3, [r7, #52] @ 0x34 8005e56: 2b00 cmp r3, #0 8005e58: d01b beq.n 8005e92 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8005e5a: 6bbb ldr r3, [r7, #56] @ 0x38 8005e5c: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8005e5e: 6a7b ldr r3, [r7, #36] @ 0x24 8005e60: 6b7a ldr r2, [r7, #52] @ 0x34 8005e62: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 8005e64: 6a7b ldr r3, [r7, #36] @ 0x24 8005e66: 2202 movs r2, #2 8005e68: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8005e6c: 2300 movs r3, #0 8005e6e: 9303 str r3, [sp, #12] 8005e70: 6a7b ldr r3, [r7, #36] @ 0x24 8005e72: 9302 str r3, [sp, #8] 8005e74: f107 0314 add.w r3, r7, #20 8005e78: 9301 str r3, [sp, #4] 8005e7a: 6b3b ldr r3, [r7, #48] @ 0x30 8005e7c: 9300 str r3, [sp, #0] 8005e7e: 683b ldr r3, [r7, #0] 8005e80: 687a ldr r2, [r7, #4] 8005e82: 68b9 ldr r1, [r7, #8] 8005e84: 68f8 ldr r0, [r7, #12] 8005e86: f000 f851 bl 8005f2c prvAddNewTaskToReadyList( pxNewTCB ); 8005e8a: 6a78 ldr r0, [r7, #36] @ 0x24 8005e8c: f000 f8f6 bl 800607c 8005e90: e001 b.n 8005e96 } else { xReturn = NULL; 8005e92: 2300 movs r3, #0 8005e94: 617b str r3, [r7, #20] } return xReturn; 8005e96: 697b ldr r3, [r7, #20] } 8005e98: 4618 mov r0, r3 8005e9a: 3728 adds r7, #40 @ 0x28 8005e9c: 46bd mov sp, r7 8005e9e: bd80 pop {r7, pc} 08005ea0 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8005ea0: b580 push {r7, lr} 8005ea2: b08c sub sp, #48 @ 0x30 8005ea4: af04 add r7, sp, #16 8005ea6: 60f8 str r0, [r7, #12] 8005ea8: 60b9 str r1, [r7, #8] 8005eaa: 603b str r3, [r7, #0] 8005eac: 4613 mov r3, r2 8005eae: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8005eb0: 88fb ldrh r3, [r7, #6] 8005eb2: 009b lsls r3, r3, #2 8005eb4: 4618 mov r0, r3 8005eb6: f001 fcf1 bl 800789c 8005eba: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8005ebc: 697b ldr r3, [r7, #20] 8005ebe: 2b00 cmp r3, #0 8005ec0: d00e beq.n 8005ee0 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8005ec2: 20a8 movs r0, #168 @ 0xa8 8005ec4: f001 fcea bl 800789c 8005ec8: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8005eca: 69fb ldr r3, [r7, #28] 8005ecc: 2b00 cmp r3, #0 8005ece: d003 beq.n 8005ed8 { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8005ed0: 69fb ldr r3, [r7, #28] 8005ed2: 697a ldr r2, [r7, #20] 8005ed4: 631a str r2, [r3, #48] @ 0x30 8005ed6: e005 b.n 8005ee4 } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 8005ed8: 6978 ldr r0, [r7, #20] 8005eda: f001 fdad bl 8007a38 8005ede: e001 b.n 8005ee4 } } else { pxNewTCB = NULL; 8005ee0: 2300 movs r3, #0 8005ee2: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 8005ee4: 69fb ldr r3, [r7, #28] 8005ee6: 2b00 cmp r3, #0 8005ee8: d017 beq.n 8005f1a { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8005eea: 69fb ldr r3, [r7, #28] 8005eec: 2200 movs r2, #0 8005eee: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 8005ef2: 88fa ldrh r2, [r7, #6] 8005ef4: 2300 movs r3, #0 8005ef6: 9303 str r3, [sp, #12] 8005ef8: 69fb ldr r3, [r7, #28] 8005efa: 9302 str r3, [sp, #8] 8005efc: 6afb ldr r3, [r7, #44] @ 0x2c 8005efe: 9301 str r3, [sp, #4] 8005f00: 6abb ldr r3, [r7, #40] @ 0x28 8005f02: 9300 str r3, [sp, #0] 8005f04: 683b ldr r3, [r7, #0] 8005f06: 68b9 ldr r1, [r7, #8] 8005f08: 68f8 ldr r0, [r7, #12] 8005f0a: f000 f80f bl 8005f2c prvAddNewTaskToReadyList( pxNewTCB ); 8005f0e: 69f8 ldr r0, [r7, #28] 8005f10: f000 f8b4 bl 800607c xReturn = pdPASS; 8005f14: 2301 movs r3, #1 8005f16: 61bb str r3, [r7, #24] 8005f18: e002 b.n 8005f20 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8005f1a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8005f1e: 61bb str r3, [r7, #24] } return xReturn; 8005f20: 69bb ldr r3, [r7, #24] } 8005f22: 4618 mov r0, r3 8005f24: 3720 adds r7, #32 8005f26: 46bd mov sp, r7 8005f28: bd80 pop {r7, pc} ... 08005f2c : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8005f2c: b580 push {r7, lr} 8005f2e: b088 sub sp, #32 8005f30: af00 add r7, sp, #0 8005f32: 60f8 str r0, [r7, #12] 8005f34: 60b9 str r1, [r7, #8] 8005f36: 607a str r2, [r7, #4] 8005f38: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 8005f3a: 6b3b ldr r3, [r7, #48] @ 0x30 8005f3c: 6b18 ldr r0, [r3, #48] @ 0x30 8005f3e: 687b ldr r3, [r7, #4] 8005f40: 009b lsls r3, r3, #2 8005f42: 461a mov r2, r3 8005f44: 21a5 movs r1, #165 @ 0xa5 8005f46: f001 fe97 bl 8007c78 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 8005f4a: 6b3b ldr r3, [r7, #48] @ 0x30 8005f4c: 6b1a ldr r2, [r3, #48] @ 0x30 8005f4e: 687b ldr r3, [r7, #4] 8005f50: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 8005f54: 3b01 subs r3, #1 8005f56: 009b lsls r3, r3, #2 8005f58: 4413 add r3, r2 8005f5a: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8005f5c: 69bb ldr r3, [r7, #24] 8005f5e: f023 0307 bic.w r3, r3, #7 8005f62: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8005f64: 69bb ldr r3, [r7, #24] 8005f66: f003 0307 and.w r3, r3, #7 8005f6a: 2b00 cmp r3, #0 8005f6c: d00b beq.n 8005f86 __asm volatile 8005f6e: f04f 0350 mov.w r3, #80 @ 0x50 8005f72: f383 8811 msr BASEPRI, r3 8005f76: f3bf 8f6f isb sy 8005f7a: f3bf 8f4f dsb sy 8005f7e: 617b str r3, [r7, #20] } 8005f80: bf00 nop 8005f82: bf00 nop 8005f84: e7fd b.n 8005f82 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 8005f86: 68bb ldr r3, [r7, #8] 8005f88: 2b00 cmp r3, #0 8005f8a: d01f beq.n 8005fcc { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8005f8c: 2300 movs r3, #0 8005f8e: 61fb str r3, [r7, #28] 8005f90: e012 b.n 8005fb8 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8005f92: 68ba ldr r2, [r7, #8] 8005f94: 69fb ldr r3, [r7, #28] 8005f96: 4413 add r3, r2 8005f98: 7819 ldrb r1, [r3, #0] 8005f9a: 6b3a ldr r2, [r7, #48] @ 0x30 8005f9c: 69fb ldr r3, [r7, #28] 8005f9e: 4413 add r3, r2 8005fa0: 3334 adds r3, #52 @ 0x34 8005fa2: 460a mov r2, r1 8005fa4: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 8005fa6: 68ba ldr r2, [r7, #8] 8005fa8: 69fb ldr r3, [r7, #28] 8005faa: 4413 add r3, r2 8005fac: 781b ldrb r3, [r3, #0] 8005fae: 2b00 cmp r3, #0 8005fb0: d006 beq.n 8005fc0 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8005fb2: 69fb ldr r3, [r7, #28] 8005fb4: 3301 adds r3, #1 8005fb6: 61fb str r3, [r7, #28] 8005fb8: 69fb ldr r3, [r7, #28] 8005fba: 2b0f cmp r3, #15 8005fbc: d9e9 bls.n 8005f92 8005fbe: e000 b.n 8005fc2 { break; 8005fc0: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 8005fc2: 6b3b ldr r3, [r7, #48] @ 0x30 8005fc4: 2200 movs r2, #0 8005fc6: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005fca: e003 b.n 8005fd4 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 8005fcc: 6b3b ldr r3, [r7, #48] @ 0x30 8005fce: 2200 movs r2, #0 8005fd0: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8005fd4: 6abb ldr r3, [r7, #40] @ 0x28 8005fd6: 2b37 cmp r3, #55 @ 0x37 8005fd8: d901 bls.n 8005fde { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8005fda: 2337 movs r3, #55 @ 0x37 8005fdc: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 8005fde: 6b3b ldr r3, [r7, #48] @ 0x30 8005fe0: 6aba ldr r2, [r7, #40] @ 0x28 8005fe2: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 8005fe4: 6b3b ldr r3, [r7, #48] @ 0x30 8005fe6: 6aba ldr r2, [r7, #40] @ 0x28 8005fe8: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 8005fea: 6b3b ldr r3, [r7, #48] @ 0x30 8005fec: 2200 movs r2, #0 8005fee: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8005ff0: 6b3b ldr r3, [r7, #48] @ 0x30 8005ff2: 3304 adds r3, #4 8005ff4: 4618 mov r0, r3 8005ff6: f7ff f965 bl 80052c4 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8005ffa: 6b3b ldr r3, [r7, #48] @ 0x30 8005ffc: 3318 adds r3, #24 8005ffe: 4618 mov r0, r3 8006000: f7ff f960 bl 80052c4 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 8006004: 6b3b ldr r3, [r7, #48] @ 0x30 8006006: 6b3a ldr r2, [r7, #48] @ 0x30 8006008: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800600a: 6abb ldr r3, [r7, #40] @ 0x28 800600c: f1c3 0238 rsb r2, r3, #56 @ 0x38 8006010: 6b3b ldr r3, [r7, #48] @ 0x30 8006012: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 8006014: 6b3b ldr r3, [r7, #48] @ 0x30 8006016: 6b3a ldr r2, [r7, #48] @ 0x30 8006018: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 800601a: 6b3b ldr r3, [r7, #48] @ 0x30 800601c: 2200 movs r2, #0 800601e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8006022: 6b3b ldr r3, [r7, #48] @ 0x30 8006024: 2200 movs r2, #0 8006026: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 800602a: 6b3b ldr r3, [r7, #48] @ 0x30 800602c: 3354 adds r3, #84 @ 0x54 800602e: 224c movs r2, #76 @ 0x4c 8006030: 2100 movs r1, #0 8006032: 4618 mov r0, r3 8006034: f001 fe20 bl 8007c78 8006038: 6b3b ldr r3, [r7, #48] @ 0x30 800603a: 4a0d ldr r2, [pc, #52] @ (8006070 ) 800603c: 659a str r2, [r3, #88] @ 0x58 800603e: 6b3b ldr r3, [r7, #48] @ 0x30 8006040: 4a0c ldr r2, [pc, #48] @ (8006074 ) 8006042: 65da str r2, [r3, #92] @ 0x5c 8006044: 6b3b ldr r3, [r7, #48] @ 0x30 8006046: 4a0c ldr r2, [pc, #48] @ (8006078 ) 8006048: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 800604a: 683a ldr r2, [r7, #0] 800604c: 68f9 ldr r1, [r7, #12] 800604e: 69b8 ldr r0, [r7, #24] 8006050: f001 f9ce bl 80073f0 8006054: 4602 mov r2, r0 8006056: 6b3b ldr r3, [r7, #48] @ 0x30 8006058: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 800605a: 6afb ldr r3, [r7, #44] @ 0x2c 800605c: 2b00 cmp r3, #0 800605e: d002 beq.n 8006066 { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8006060: 6afb ldr r3, [r7, #44] @ 0x2c 8006062: 6b3a ldr r2, [r7, #48] @ 0x30 8006064: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8006066: bf00 nop 8006068: 3720 adds r7, #32 800606a: 46bd mov sp, r7 800606c: bd80 pop {r7, pc} 800606e: bf00 nop 8006070: 20008b34 .word 0x20008b34 8006074: 20008b9c .word 0x20008b9c 8006078: 20008c04 .word 0x20008c04 0800607c : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 800607c: b580 push {r7, lr} 800607e: b082 sub sp, #8 8006080: af00 add r7, sp, #0 8006082: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8006084: f001 fae8 bl 8007658 { uxCurrentNumberOfTasks++; 8006088: 4b2d ldr r3, [pc, #180] @ (8006140 ) 800608a: 681b ldr r3, [r3, #0] 800608c: 3301 adds r3, #1 800608e: 4a2c ldr r2, [pc, #176] @ (8006140 ) 8006090: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8006092: 4b2c ldr r3, [pc, #176] @ (8006144 ) 8006094: 681b ldr r3, [r3, #0] 8006096: 2b00 cmp r3, #0 8006098: d109 bne.n 80060ae { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 800609a: 4a2a ldr r2, [pc, #168] @ (8006144 ) 800609c: 687b ldr r3, [r7, #4] 800609e: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 80060a0: 4b27 ldr r3, [pc, #156] @ (8006140 ) 80060a2: 681b ldr r3, [r3, #0] 80060a4: 2b01 cmp r3, #1 80060a6: d110 bne.n 80060ca { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 80060a8: f000 fca2 bl 80069f0 80060ac: e00d b.n 80060ca else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 80060ae: 4b26 ldr r3, [pc, #152] @ (8006148 ) 80060b0: 681b ldr r3, [r3, #0] 80060b2: 2b00 cmp r3, #0 80060b4: d109 bne.n 80060ca { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 80060b6: 4b23 ldr r3, [pc, #140] @ (8006144 ) 80060b8: 681b ldr r3, [r3, #0] 80060ba: 6ada ldr r2, [r3, #44] @ 0x2c 80060bc: 687b ldr r3, [r7, #4] 80060be: 6adb ldr r3, [r3, #44] @ 0x2c 80060c0: 429a cmp r2, r3 80060c2: d802 bhi.n 80060ca { pxCurrentTCB = pxNewTCB; 80060c4: 4a1f ldr r2, [pc, #124] @ (8006144 ) 80060c6: 687b ldr r3, [r7, #4] 80060c8: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 80060ca: 4b20 ldr r3, [pc, #128] @ (800614c ) 80060cc: 681b ldr r3, [r3, #0] 80060ce: 3301 adds r3, #1 80060d0: 4a1e ldr r2, [pc, #120] @ (800614c ) 80060d2: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 80060d4: 4b1d ldr r3, [pc, #116] @ (800614c ) 80060d6: 681a ldr r2, [r3, #0] 80060d8: 687b ldr r3, [r7, #4] 80060da: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 80060dc: 687b ldr r3, [r7, #4] 80060de: 6ada ldr r2, [r3, #44] @ 0x2c 80060e0: 4b1b ldr r3, [pc, #108] @ (8006150 ) 80060e2: 681b ldr r3, [r3, #0] 80060e4: 429a cmp r2, r3 80060e6: d903 bls.n 80060f0 80060e8: 687b ldr r3, [r7, #4] 80060ea: 6adb ldr r3, [r3, #44] @ 0x2c 80060ec: 4a18 ldr r2, [pc, #96] @ (8006150 ) 80060ee: 6013 str r3, [r2, #0] 80060f0: 687b ldr r3, [r7, #4] 80060f2: 6ada ldr r2, [r3, #44] @ 0x2c 80060f4: 4613 mov r3, r2 80060f6: 009b lsls r3, r3, #2 80060f8: 4413 add r3, r2 80060fa: 009b lsls r3, r3, #2 80060fc: 4a15 ldr r2, [pc, #84] @ (8006154 ) 80060fe: 441a add r2, r3 8006100: 687b ldr r3, [r7, #4] 8006102: 3304 adds r3, #4 8006104: 4619 mov r1, r3 8006106: 4610 mov r0, r2 8006108: f7ff f8e9 bl 80052de portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 800610c: f001 fad6 bl 80076bc if( xSchedulerRunning != pdFALSE ) 8006110: 4b0d ldr r3, [pc, #52] @ (8006148 ) 8006112: 681b ldr r3, [r3, #0] 8006114: 2b00 cmp r3, #0 8006116: d00e beq.n 8006136 { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8006118: 4b0a ldr r3, [pc, #40] @ (8006144 ) 800611a: 681b ldr r3, [r3, #0] 800611c: 6ada ldr r2, [r3, #44] @ 0x2c 800611e: 687b ldr r3, [r7, #4] 8006120: 6adb ldr r3, [r3, #44] @ 0x2c 8006122: 429a cmp r2, r3 8006124: d207 bcs.n 8006136 { taskYIELD_IF_USING_PREEMPTION(); 8006126: 4b0c ldr r3, [pc, #48] @ (8006158 ) 8006128: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800612c: 601a str r2, [r3, #0] 800612e: f3bf 8f4f dsb sy 8006132: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8006136: bf00 nop 8006138: 3708 adds r7, #8 800613a: 46bd mov sp, r7 800613c: bd80 pop {r7, pc} 800613e: bf00 nop 8006140: 20001484 .word 0x20001484 8006144: 20000fb0 .word 0x20000fb0 8006148: 20001490 .word 0x20001490 800614c: 200014a0 .word 0x200014a0 8006150: 2000148c .word 0x2000148c 8006154: 20000fb4 .word 0x20000fb4 8006158: e000ed04 .word 0xe000ed04 0800615c : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) void vTaskDelete( TaskHandle_t xTaskToDelete ) { 800615c: b580 push {r7, lr} 800615e: b084 sub sp, #16 8006160: af00 add r7, sp, #0 8006162: 6078 str r0, [r7, #4] TCB_t *pxTCB; taskENTER_CRITICAL(); 8006164: f001 fa78 bl 8007658 { /* If null is passed in here then it is the calling task that is being deleted. */ pxTCB = prvGetTCBFromHandle( xTaskToDelete ); 8006168: 687b ldr r3, [r7, #4] 800616a: 2b00 cmp r3, #0 800616c: d102 bne.n 8006174 800616e: 4b2d ldr r3, [pc, #180] @ (8006224 ) 8006170: 681b ldr r3, [r3, #0] 8006172: e000 b.n 8006176 8006174: 687b ldr r3, [r7, #4] 8006176: 60fb str r3, [r7, #12] /* Remove task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8006178: 68fb ldr r3, [r7, #12] 800617a: 3304 adds r3, #4 800617c: 4618 mov r0, r3 800617e: f7ff f90b bl 8005398 { mtCOVERAGE_TEST_MARKER(); } /* Is the task waiting on an event also? */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 8006182: 68fb ldr r3, [r7, #12] 8006184: 6a9b ldr r3, [r3, #40] @ 0x28 8006186: 2b00 cmp r3, #0 8006188: d004 beq.n 8006194 { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 800618a: 68fb ldr r3, [r7, #12] 800618c: 3318 adds r3, #24 800618e: 4618 mov r0, r3 8006190: f7ff f902 bl 8005398 /* Increment the uxTaskNumber also so kernel aware debuggers can detect that the task lists need re-generating. This is done before portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will not return. */ uxTaskNumber++; 8006194: 4b24 ldr r3, [pc, #144] @ (8006228 ) 8006196: 681b ldr r3, [r3, #0] 8006198: 3301 adds r3, #1 800619a: 4a23 ldr r2, [pc, #140] @ (8006228 ) 800619c: 6013 str r3, [r2, #0] if( pxTCB == pxCurrentTCB ) 800619e: 4b21 ldr r3, [pc, #132] @ (8006224 ) 80061a0: 681b ldr r3, [r3, #0] 80061a2: 68fa ldr r2, [r7, #12] 80061a4: 429a cmp r2, r3 80061a6: d10b bne.n 80061c0 /* A task is deleting itself. This cannot complete within the task itself, as a context switch to another task is required. Place the task in the termination list. The idle task will check the termination list and free up any memory allocated by the scheduler for the TCB and stack of the deleted task. */ vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) ); 80061a8: 68fb ldr r3, [r7, #12] 80061aa: 3304 adds r3, #4 80061ac: 4619 mov r1, r3 80061ae: 481f ldr r0, [pc, #124] @ (800622c ) 80061b0: f7ff f895 bl 80052de /* Increment the ucTasksDeleted variable so the idle task knows there is a task that has been deleted and that it should therefore check the xTasksWaitingTermination list. */ ++uxDeletedTasksWaitingCleanUp; 80061b4: 4b1e ldr r3, [pc, #120] @ (8006230 ) 80061b6: 681b ldr r3, [r3, #0] 80061b8: 3301 adds r3, #1 80061ba: 4a1d ldr r2, [pc, #116] @ (8006230 ) 80061bc: 6013 str r3, [r2, #0] 80061be: e009 b.n 80061d4 required. */ portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending ); } else { --uxCurrentNumberOfTasks; 80061c0: 4b1c ldr r3, [pc, #112] @ (8006234 ) 80061c2: 681b ldr r3, [r3, #0] 80061c4: 3b01 subs r3, #1 80061c6: 4a1b ldr r2, [pc, #108] @ (8006234 ) 80061c8: 6013 str r3, [r2, #0] traceTASK_DELETE( pxTCB ); prvDeleteTCB( pxTCB ); 80061ca: 68f8 ldr r0, [r7, #12] 80061cc: f000 fc7e bl 8006acc /* Reset the next expected unblock time in case it referred to the task that has just been deleted. */ prvResetNextTaskUnblockTime(); 80061d0: f000 fcb2 bl 8006b38 } } taskEXIT_CRITICAL(); 80061d4: f001 fa72 bl 80076bc /* Force a reschedule if it is the currently running task that has just been deleted. */ if( xSchedulerRunning != pdFALSE ) 80061d8: 4b17 ldr r3, [pc, #92] @ (8006238 ) 80061da: 681b ldr r3, [r3, #0] 80061dc: 2b00 cmp r3, #0 80061de: d01c beq.n 800621a { if( pxTCB == pxCurrentTCB ) 80061e0: 4b10 ldr r3, [pc, #64] @ (8006224 ) 80061e2: 681b ldr r3, [r3, #0] 80061e4: 68fa ldr r2, [r7, #12] 80061e6: 429a cmp r2, r3 80061e8: d117 bne.n 800621a { configASSERT( uxSchedulerSuspended == 0 ); 80061ea: 4b14 ldr r3, [pc, #80] @ (800623c ) 80061ec: 681b ldr r3, [r3, #0] 80061ee: 2b00 cmp r3, #0 80061f0: d00b beq.n 800620a __asm volatile 80061f2: f04f 0350 mov.w r3, #80 @ 0x50 80061f6: f383 8811 msr BASEPRI, r3 80061fa: f3bf 8f6f isb sy 80061fe: f3bf 8f4f dsb sy 8006202: 60bb str r3, [r7, #8] } 8006204: bf00 nop 8006206: bf00 nop 8006208: e7fd b.n 8006206 portYIELD_WITHIN_API(); 800620a: 4b0d ldr r3, [pc, #52] @ (8006240 ) 800620c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006210: 601a str r2, [r3, #0] 8006212: f3bf 8f4f dsb sy 8006216: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } } 800621a: bf00 nop 800621c: 3710 adds r7, #16 800621e: 46bd mov sp, r7 8006220: bd80 pop {r7, pc} 8006222: bf00 nop 8006224: 20000fb0 .word 0x20000fb0 8006228: 200014a0 .word 0x200014a0 800622c: 20001458 .word 0x20001458 8006230: 2000146c .word 0x2000146c 8006234: 20001484 .word 0x20001484 8006238: 20001490 .word 0x20001490 800623c: 200014ac .word 0x200014ac 8006240: e000ed04 .word 0xe000ed04 08006244 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8006244: b580 push {r7, lr} 8006246: b084 sub sp, #16 8006248: af00 add r7, sp, #0 800624a: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 800624c: 2300 movs r3, #0 800624e: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 8006250: 687b ldr r3, [r7, #4] 8006252: 2b00 cmp r3, #0 8006254: d018 beq.n 8006288 { configASSERT( uxSchedulerSuspended == 0 ); 8006256: 4b14 ldr r3, [pc, #80] @ (80062a8 ) 8006258: 681b ldr r3, [r3, #0] 800625a: 2b00 cmp r3, #0 800625c: d00b beq.n 8006276 __asm volatile 800625e: f04f 0350 mov.w r3, #80 @ 0x50 8006262: f383 8811 msr BASEPRI, r3 8006266: f3bf 8f6f isb sy 800626a: f3bf 8f4f dsb sy 800626e: 60bb str r3, [r7, #8] } 8006270: bf00 nop 8006272: bf00 nop 8006274: e7fd b.n 8006272 vTaskSuspendAll(); 8006276: f000 f88b bl 8006390 list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 800627a: 2100 movs r1, #0 800627c: 6878 ldr r0, [r7, #4] 800627e: f000 fd09 bl 8006c94 } xAlreadyYielded = xTaskResumeAll(); 8006282: f000 f893 bl 80063ac 8006286: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 8006288: 68fb ldr r3, [r7, #12] 800628a: 2b00 cmp r3, #0 800628c: d107 bne.n 800629e { portYIELD_WITHIN_API(); 800628e: 4b07 ldr r3, [pc, #28] @ (80062ac ) 8006290: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006294: 601a str r2, [r3, #0] 8006296: f3bf 8f4f dsb sy 800629a: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 800629e: bf00 nop 80062a0: 3710 adds r7, #16 80062a2: 46bd mov sp, r7 80062a4: bd80 pop {r7, pc} 80062a6: bf00 nop 80062a8: 200014ac .word 0x200014ac 80062ac: e000ed04 .word 0xe000ed04 080062b0 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 80062b0: b580 push {r7, lr} 80062b2: b08a sub sp, #40 @ 0x28 80062b4: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 80062b6: 2300 movs r3, #0 80062b8: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 80062ba: 2300 movs r3, #0 80062bc: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 80062be: 463a mov r2, r7 80062c0: 1d39 adds r1, r7, #4 80062c2: f107 0308 add.w r3, r7, #8 80062c6: 4618 mov r0, r3 80062c8: f7fe ffa8 bl 800521c xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 80062cc: 6839 ldr r1, [r7, #0] 80062ce: 687b ldr r3, [r7, #4] 80062d0: 68ba ldr r2, [r7, #8] 80062d2: 9202 str r2, [sp, #8] 80062d4: 9301 str r3, [sp, #4] 80062d6: 2300 movs r3, #0 80062d8: 9300 str r3, [sp, #0] 80062da: 2300 movs r3, #0 80062dc: 460a mov r2, r1 80062de: 4924 ldr r1, [pc, #144] @ (8006370 ) 80062e0: 4824 ldr r0, [pc, #144] @ (8006374 ) 80062e2: f7ff fd7d bl 8005de0 80062e6: 4603 mov r3, r0 80062e8: 4a23 ldr r2, [pc, #140] @ (8006378 ) 80062ea: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 80062ec: 4b22 ldr r3, [pc, #136] @ (8006378 ) 80062ee: 681b ldr r3, [r3, #0] 80062f0: 2b00 cmp r3, #0 80062f2: d002 beq.n 80062fa { xReturn = pdPASS; 80062f4: 2301 movs r3, #1 80062f6: 617b str r3, [r7, #20] 80062f8: e001 b.n 80062fe } else { xReturn = pdFAIL; 80062fa: 2300 movs r3, #0 80062fc: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 80062fe: 697b ldr r3, [r7, #20] 8006300: 2b01 cmp r3, #1 8006302: d102 bne.n 800630a { xReturn = xTimerCreateTimerTask(); 8006304: f000 fd1a bl 8006d3c 8006308: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 800630a: 697b ldr r3, [r7, #20] 800630c: 2b01 cmp r3, #1 800630e: d11b bne.n 8006348 __asm volatile 8006310: f04f 0350 mov.w r3, #80 @ 0x50 8006314: f383 8811 msr BASEPRI, r3 8006318: f3bf 8f6f isb sy 800631c: f3bf 8f4f dsb sy 8006320: 613b str r3, [r7, #16] } 8006322: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8006324: 4b15 ldr r3, [pc, #84] @ (800637c ) 8006326: 681b ldr r3, [r3, #0] 8006328: 3354 adds r3, #84 @ 0x54 800632a: 4a15 ldr r2, [pc, #84] @ (8006380 ) 800632c: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 800632e: 4b15 ldr r3, [pc, #84] @ (8006384 ) 8006330: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8006334: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8006336: 4b14 ldr r3, [pc, #80] @ (8006388 ) 8006338: 2201 movs r2, #1 800633a: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 800633c: 4b13 ldr r3, [pc, #76] @ (800638c ) 800633e: 2200 movs r2, #0 8006340: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 8006342: f001 f8e5 bl 8007510 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 8006346: e00f b.n 8006368 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8006348: 697b ldr r3, [r7, #20] 800634a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800634e: d10b bne.n 8006368 __asm volatile 8006350: f04f 0350 mov.w r3, #80 @ 0x50 8006354: f383 8811 msr BASEPRI, r3 8006358: f3bf 8f6f isb sy 800635c: f3bf 8f4f dsb sy 8006360: 60fb str r3, [r7, #12] } 8006362: bf00 nop 8006364: bf00 nop 8006366: e7fd b.n 8006364 } 8006368: bf00 nop 800636a: 3718 adds r7, #24 800636c: 46bd mov sp, r7 800636e: bd80 pop {r7, pc} 8006370: 08007e94 .word 0x08007e94 8006374: 080069c1 .word 0x080069c1 8006378: 200014a8 .word 0x200014a8 800637c: 20000fb0 .word 0x20000fb0 8006380: 20000010 .word 0x20000010 8006384: 200014a4 .word 0x200014a4 8006388: 20001490 .word 0x20001490 800638c: 20001488 .word 0x20001488 08006390 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 8006390: b480 push {r7} 8006392: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8006394: 4b04 ldr r3, [pc, #16] @ (80063a8 ) 8006396: 681b ldr r3, [r3, #0] 8006398: 3301 adds r3, #1 800639a: 4a03 ldr r2, [pc, #12] @ (80063a8 ) 800639c: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 800639e: bf00 nop 80063a0: 46bd mov sp, r7 80063a2: f85d 7b04 ldr.w r7, [sp], #4 80063a6: 4770 bx lr 80063a8: 200014ac .word 0x200014ac 080063ac : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 80063ac: b580 push {r7, lr} 80063ae: b084 sub sp, #16 80063b0: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 80063b2: 2300 movs r3, #0 80063b4: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 80063b6: 2300 movs r3, #0 80063b8: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 80063ba: 4b42 ldr r3, [pc, #264] @ (80064c4 ) 80063bc: 681b ldr r3, [r3, #0] 80063be: 2b00 cmp r3, #0 80063c0: d10b bne.n 80063da __asm volatile 80063c2: f04f 0350 mov.w r3, #80 @ 0x50 80063c6: f383 8811 msr BASEPRI, r3 80063ca: f3bf 8f6f isb sy 80063ce: f3bf 8f4f dsb sy 80063d2: 603b str r3, [r7, #0] } 80063d4: bf00 nop 80063d6: bf00 nop 80063d8: e7fd b.n 80063d6 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 80063da: f001 f93d bl 8007658 { --uxSchedulerSuspended; 80063de: 4b39 ldr r3, [pc, #228] @ (80064c4 ) 80063e0: 681b ldr r3, [r3, #0] 80063e2: 3b01 subs r3, #1 80063e4: 4a37 ldr r2, [pc, #220] @ (80064c4 ) 80063e6: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80063e8: 4b36 ldr r3, [pc, #216] @ (80064c4 ) 80063ea: 681b ldr r3, [r3, #0] 80063ec: 2b00 cmp r3, #0 80063ee: d162 bne.n 80064b6 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80063f0: 4b35 ldr r3, [pc, #212] @ (80064c8 ) 80063f2: 681b ldr r3, [r3, #0] 80063f4: 2b00 cmp r3, #0 80063f6: d05e beq.n 80064b6 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80063f8: e02f b.n 800645a { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80063fa: 4b34 ldr r3, [pc, #208] @ (80064cc ) 80063fc: 68db ldr r3, [r3, #12] 80063fe: 68db ldr r3, [r3, #12] 8006400: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8006402: 68fb ldr r3, [r7, #12] 8006404: 3318 adds r3, #24 8006406: 4618 mov r0, r3 8006408: f7fe ffc6 bl 8005398 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800640c: 68fb ldr r3, [r7, #12] 800640e: 3304 adds r3, #4 8006410: 4618 mov r0, r3 8006412: f7fe ffc1 bl 8005398 prvAddTaskToReadyList( pxTCB ); 8006416: 68fb ldr r3, [r7, #12] 8006418: 6ada ldr r2, [r3, #44] @ 0x2c 800641a: 4b2d ldr r3, [pc, #180] @ (80064d0 ) 800641c: 681b ldr r3, [r3, #0] 800641e: 429a cmp r2, r3 8006420: d903 bls.n 800642a 8006422: 68fb ldr r3, [r7, #12] 8006424: 6adb ldr r3, [r3, #44] @ 0x2c 8006426: 4a2a ldr r2, [pc, #168] @ (80064d0 ) 8006428: 6013 str r3, [r2, #0] 800642a: 68fb ldr r3, [r7, #12] 800642c: 6ada ldr r2, [r3, #44] @ 0x2c 800642e: 4613 mov r3, r2 8006430: 009b lsls r3, r3, #2 8006432: 4413 add r3, r2 8006434: 009b lsls r3, r3, #2 8006436: 4a27 ldr r2, [pc, #156] @ (80064d4 ) 8006438: 441a add r2, r3 800643a: 68fb ldr r3, [r7, #12] 800643c: 3304 adds r3, #4 800643e: 4619 mov r1, r3 8006440: 4610 mov r0, r2 8006442: f7fe ff4c bl 80052de /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8006446: 68fb ldr r3, [r7, #12] 8006448: 6ada ldr r2, [r3, #44] @ 0x2c 800644a: 4b23 ldr r3, [pc, #140] @ (80064d8 ) 800644c: 681b ldr r3, [r3, #0] 800644e: 6adb ldr r3, [r3, #44] @ 0x2c 8006450: 429a cmp r2, r3 8006452: d302 bcc.n 800645a { xYieldPending = pdTRUE; 8006454: 4b21 ldr r3, [pc, #132] @ (80064dc ) 8006456: 2201 movs r2, #1 8006458: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 800645a: 4b1c ldr r3, [pc, #112] @ (80064cc ) 800645c: 681b ldr r3, [r3, #0] 800645e: 2b00 cmp r3, #0 8006460: d1cb bne.n 80063fa { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 8006462: 68fb ldr r3, [r7, #12] 8006464: 2b00 cmp r3, #0 8006466: d001 beq.n 800646c which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 8006468: f000 fb66 bl 8006b38 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 800646c: 4b1c ldr r3, [pc, #112] @ (80064e0 ) 800646e: 681b ldr r3, [r3, #0] 8006470: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 8006472: 687b ldr r3, [r7, #4] 8006474: 2b00 cmp r3, #0 8006476: d010 beq.n 800649a { do { if( xTaskIncrementTick() != pdFALSE ) 8006478: f000 f846 bl 8006508 800647c: 4603 mov r3, r0 800647e: 2b00 cmp r3, #0 8006480: d002 beq.n 8006488 { xYieldPending = pdTRUE; 8006482: 4b16 ldr r3, [pc, #88] @ (80064dc ) 8006484: 2201 movs r2, #1 8006486: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8006488: 687b ldr r3, [r7, #4] 800648a: 3b01 subs r3, #1 800648c: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 800648e: 687b ldr r3, [r7, #4] 8006490: 2b00 cmp r3, #0 8006492: d1f1 bne.n 8006478 xPendedTicks = 0; 8006494: 4b12 ldr r3, [pc, #72] @ (80064e0 ) 8006496: 2200 movs r2, #0 8006498: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 800649a: 4b10 ldr r3, [pc, #64] @ (80064dc ) 800649c: 681b ldr r3, [r3, #0] 800649e: 2b00 cmp r3, #0 80064a0: d009 beq.n 80064b6 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 80064a2: 2301 movs r3, #1 80064a4: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 80064a6: 4b0f ldr r3, [pc, #60] @ (80064e4 ) 80064a8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80064ac: 601a str r2, [r3, #0] 80064ae: f3bf 8f4f dsb sy 80064b2: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80064b6: f001 f901 bl 80076bc return xAlreadyYielded; 80064ba: 68bb ldr r3, [r7, #8] } 80064bc: 4618 mov r0, r3 80064be: 3710 adds r7, #16 80064c0: 46bd mov sp, r7 80064c2: bd80 pop {r7, pc} 80064c4: 200014ac .word 0x200014ac 80064c8: 20001484 .word 0x20001484 80064cc: 20001444 .word 0x20001444 80064d0: 2000148c .word 0x2000148c 80064d4: 20000fb4 .word 0x20000fb4 80064d8: 20000fb0 .word 0x20000fb0 80064dc: 20001498 .word 0x20001498 80064e0: 20001494 .word 0x20001494 80064e4: e000ed04 .word 0xe000ed04 080064e8 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 80064e8: b480 push {r7} 80064ea: b083 sub sp, #12 80064ec: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 80064ee: 4b05 ldr r3, [pc, #20] @ (8006504 ) 80064f0: 681b ldr r3, [r3, #0] 80064f2: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 80064f4: 687b ldr r3, [r7, #4] } 80064f6: 4618 mov r0, r3 80064f8: 370c adds r7, #12 80064fa: 46bd mov sp, r7 80064fc: f85d 7b04 ldr.w r7, [sp], #4 8006500: 4770 bx lr 8006502: bf00 nop 8006504: 20001488 .word 0x20001488 08006508 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 8006508: b580 push {r7, lr} 800650a: b086 sub sp, #24 800650c: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 800650e: 2300 movs r3, #0 8006510: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8006512: 4b4f ldr r3, [pc, #316] @ (8006650 ) 8006514: 681b ldr r3, [r3, #0] 8006516: 2b00 cmp r3, #0 8006518: f040 8090 bne.w 800663c { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 800651c: 4b4d ldr r3, [pc, #308] @ (8006654 ) 800651e: 681b ldr r3, [r3, #0] 8006520: 3301 adds r3, #1 8006522: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8006524: 4a4b ldr r2, [pc, #300] @ (8006654 ) 8006526: 693b ldr r3, [r7, #16] 8006528: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 800652a: 693b ldr r3, [r7, #16] 800652c: 2b00 cmp r3, #0 800652e: d121 bne.n 8006574 { taskSWITCH_DELAYED_LISTS(); 8006530: 4b49 ldr r3, [pc, #292] @ (8006658 ) 8006532: 681b ldr r3, [r3, #0] 8006534: 681b ldr r3, [r3, #0] 8006536: 2b00 cmp r3, #0 8006538: d00b beq.n 8006552 __asm volatile 800653a: f04f 0350 mov.w r3, #80 @ 0x50 800653e: f383 8811 msr BASEPRI, r3 8006542: f3bf 8f6f isb sy 8006546: f3bf 8f4f dsb sy 800654a: 603b str r3, [r7, #0] } 800654c: bf00 nop 800654e: bf00 nop 8006550: e7fd b.n 800654e 8006552: 4b41 ldr r3, [pc, #260] @ (8006658 ) 8006554: 681b ldr r3, [r3, #0] 8006556: 60fb str r3, [r7, #12] 8006558: 4b40 ldr r3, [pc, #256] @ (800665c ) 800655a: 681b ldr r3, [r3, #0] 800655c: 4a3e ldr r2, [pc, #248] @ (8006658 ) 800655e: 6013 str r3, [r2, #0] 8006560: 4a3e ldr r2, [pc, #248] @ (800665c ) 8006562: 68fb ldr r3, [r7, #12] 8006564: 6013 str r3, [r2, #0] 8006566: 4b3e ldr r3, [pc, #248] @ (8006660 ) 8006568: 681b ldr r3, [r3, #0] 800656a: 3301 adds r3, #1 800656c: 4a3c ldr r2, [pc, #240] @ (8006660 ) 800656e: 6013 str r3, [r2, #0] 8006570: f000 fae2 bl 8006b38 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8006574: 4b3b ldr r3, [pc, #236] @ (8006664 ) 8006576: 681b ldr r3, [r3, #0] 8006578: 693a ldr r2, [r7, #16] 800657a: 429a cmp r2, r3 800657c: d349 bcc.n 8006612 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800657e: 4b36 ldr r3, [pc, #216] @ (8006658 ) 8006580: 681b ldr r3, [r3, #0] 8006582: 681b ldr r3, [r3, #0] 8006584: 2b00 cmp r3, #0 8006586: d104 bne.n 8006592 /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8006588: 4b36 ldr r3, [pc, #216] @ (8006664 ) 800658a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800658e: 601a str r2, [r3, #0] break; 8006590: e03f b.n 8006612 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8006592: 4b31 ldr r3, [pc, #196] @ (8006658 ) 8006594: 681b ldr r3, [r3, #0] 8006596: 68db ldr r3, [r3, #12] 8006598: 68db ldr r3, [r3, #12] 800659a: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 800659c: 68bb ldr r3, [r7, #8] 800659e: 685b ldr r3, [r3, #4] 80065a0: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 80065a2: 693a ldr r2, [r7, #16] 80065a4: 687b ldr r3, [r7, #4] 80065a6: 429a cmp r2, r3 80065a8: d203 bcs.n 80065b2 /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 80065aa: 4a2e ldr r2, [pc, #184] @ (8006664 ) 80065ac: 687b ldr r3, [r7, #4] 80065ae: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 80065b0: e02f b.n 8006612 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80065b2: 68bb ldr r3, [r7, #8] 80065b4: 3304 adds r3, #4 80065b6: 4618 mov r0, r3 80065b8: f7fe feee bl 8005398 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 80065bc: 68bb ldr r3, [r7, #8] 80065be: 6a9b ldr r3, [r3, #40] @ 0x28 80065c0: 2b00 cmp r3, #0 80065c2: d004 beq.n 80065ce { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80065c4: 68bb ldr r3, [r7, #8] 80065c6: 3318 adds r3, #24 80065c8: 4618 mov r0, r3 80065ca: f7fe fee5 bl 8005398 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 80065ce: 68bb ldr r3, [r7, #8] 80065d0: 6ada ldr r2, [r3, #44] @ 0x2c 80065d2: 4b25 ldr r3, [pc, #148] @ (8006668 ) 80065d4: 681b ldr r3, [r3, #0] 80065d6: 429a cmp r2, r3 80065d8: d903 bls.n 80065e2 80065da: 68bb ldr r3, [r7, #8] 80065dc: 6adb ldr r3, [r3, #44] @ 0x2c 80065de: 4a22 ldr r2, [pc, #136] @ (8006668 ) 80065e0: 6013 str r3, [r2, #0] 80065e2: 68bb ldr r3, [r7, #8] 80065e4: 6ada ldr r2, [r3, #44] @ 0x2c 80065e6: 4613 mov r3, r2 80065e8: 009b lsls r3, r3, #2 80065ea: 4413 add r3, r2 80065ec: 009b lsls r3, r3, #2 80065ee: 4a1f ldr r2, [pc, #124] @ (800666c ) 80065f0: 441a add r2, r3 80065f2: 68bb ldr r3, [r7, #8] 80065f4: 3304 adds r3, #4 80065f6: 4619 mov r1, r3 80065f8: 4610 mov r0, r2 80065fa: f7fe fe70 bl 80052de { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80065fe: 68bb ldr r3, [r7, #8] 8006600: 6ada ldr r2, [r3, #44] @ 0x2c 8006602: 4b1b ldr r3, [pc, #108] @ (8006670 ) 8006604: 681b ldr r3, [r3, #0] 8006606: 6adb ldr r3, [r3, #44] @ 0x2c 8006608: 429a cmp r2, r3 800660a: d3b8 bcc.n 800657e { xSwitchRequired = pdTRUE; 800660c: 2301 movs r3, #1 800660e: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8006610: e7b5 b.n 800657e /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 8006612: 4b17 ldr r3, [pc, #92] @ (8006670 ) 8006614: 681b ldr r3, [r3, #0] 8006616: 6ada ldr r2, [r3, #44] @ 0x2c 8006618: 4914 ldr r1, [pc, #80] @ (800666c ) 800661a: 4613 mov r3, r2 800661c: 009b lsls r3, r3, #2 800661e: 4413 add r3, r2 8006620: 009b lsls r3, r3, #2 8006622: 440b add r3, r1 8006624: 681b ldr r3, [r3, #0] 8006626: 2b01 cmp r3, #1 8006628: d901 bls.n 800662e { xSwitchRequired = pdTRUE; 800662a: 2301 movs r3, #1 800662c: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 800662e: 4b11 ldr r3, [pc, #68] @ (8006674 ) 8006630: 681b ldr r3, [r3, #0] 8006632: 2b00 cmp r3, #0 8006634: d007 beq.n 8006646 { xSwitchRequired = pdTRUE; 8006636: 2301 movs r3, #1 8006638: 617b str r3, [r7, #20] 800663a: e004 b.n 8006646 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 800663c: 4b0e ldr r3, [pc, #56] @ (8006678 ) 800663e: 681b ldr r3, [r3, #0] 8006640: 3301 adds r3, #1 8006642: 4a0d ldr r2, [pc, #52] @ (8006678 ) 8006644: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8006646: 697b ldr r3, [r7, #20] } 8006648: 4618 mov r0, r3 800664a: 3718 adds r7, #24 800664c: 46bd mov sp, r7 800664e: bd80 pop {r7, pc} 8006650: 200014ac .word 0x200014ac 8006654: 20001488 .word 0x20001488 8006658: 2000143c .word 0x2000143c 800665c: 20001440 .word 0x20001440 8006660: 2000149c .word 0x2000149c 8006664: 200014a4 .word 0x200014a4 8006668: 2000148c .word 0x2000148c 800666c: 20000fb4 .word 0x20000fb4 8006670: 20000fb0 .word 0x20000fb0 8006674: 20001498 .word 0x20001498 8006678: 20001494 .word 0x20001494 0800667c : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 800667c: b480 push {r7} 800667e: b085 sub sp, #20 8006680: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 8006682: 4b2b ldr r3, [pc, #172] @ (8006730 ) 8006684: 681b ldr r3, [r3, #0] 8006686: 2b00 cmp r3, #0 8006688: d003 beq.n 8006692 { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 800668a: 4b2a ldr r3, [pc, #168] @ (8006734 ) 800668c: 2201 movs r2, #1 800668e: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 8006690: e047 b.n 8006722 xYieldPending = pdFALSE; 8006692: 4b28 ldr r3, [pc, #160] @ (8006734 ) 8006694: 2200 movs r2, #0 8006696: 601a str r2, [r3, #0] taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8006698: 4b27 ldr r3, [pc, #156] @ (8006738 ) 800669a: 681b ldr r3, [r3, #0] 800669c: 60fb str r3, [r7, #12] 800669e: e011 b.n 80066c4 80066a0: 68fb ldr r3, [r7, #12] 80066a2: 2b00 cmp r3, #0 80066a4: d10b bne.n 80066be __asm volatile 80066a6: f04f 0350 mov.w r3, #80 @ 0x50 80066aa: f383 8811 msr BASEPRI, r3 80066ae: f3bf 8f6f isb sy 80066b2: f3bf 8f4f dsb sy 80066b6: 607b str r3, [r7, #4] } 80066b8: bf00 nop 80066ba: bf00 nop 80066bc: e7fd b.n 80066ba 80066be: 68fb ldr r3, [r7, #12] 80066c0: 3b01 subs r3, #1 80066c2: 60fb str r3, [r7, #12] 80066c4: 491d ldr r1, [pc, #116] @ (800673c ) 80066c6: 68fa ldr r2, [r7, #12] 80066c8: 4613 mov r3, r2 80066ca: 009b lsls r3, r3, #2 80066cc: 4413 add r3, r2 80066ce: 009b lsls r3, r3, #2 80066d0: 440b add r3, r1 80066d2: 681b ldr r3, [r3, #0] 80066d4: 2b00 cmp r3, #0 80066d6: d0e3 beq.n 80066a0 80066d8: 68fa ldr r2, [r7, #12] 80066da: 4613 mov r3, r2 80066dc: 009b lsls r3, r3, #2 80066de: 4413 add r3, r2 80066e0: 009b lsls r3, r3, #2 80066e2: 4a16 ldr r2, [pc, #88] @ (800673c ) 80066e4: 4413 add r3, r2 80066e6: 60bb str r3, [r7, #8] 80066e8: 68bb ldr r3, [r7, #8] 80066ea: 685b ldr r3, [r3, #4] 80066ec: 685a ldr r2, [r3, #4] 80066ee: 68bb ldr r3, [r7, #8] 80066f0: 605a str r2, [r3, #4] 80066f2: 68bb ldr r3, [r7, #8] 80066f4: 685a ldr r2, [r3, #4] 80066f6: 68bb ldr r3, [r7, #8] 80066f8: 3308 adds r3, #8 80066fa: 429a cmp r2, r3 80066fc: d104 bne.n 8006708 80066fe: 68bb ldr r3, [r7, #8] 8006700: 685b ldr r3, [r3, #4] 8006702: 685a ldr r2, [r3, #4] 8006704: 68bb ldr r3, [r7, #8] 8006706: 605a str r2, [r3, #4] 8006708: 68bb ldr r3, [r7, #8] 800670a: 685b ldr r3, [r3, #4] 800670c: 68db ldr r3, [r3, #12] 800670e: 4a0c ldr r2, [pc, #48] @ (8006740 ) 8006710: 6013 str r3, [r2, #0] 8006712: 4a09 ldr r2, [pc, #36] @ (8006738 ) 8006714: 68fb ldr r3, [r7, #12] 8006716: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8006718: 4b09 ldr r3, [pc, #36] @ (8006740 ) 800671a: 681b ldr r3, [r3, #0] 800671c: 3354 adds r3, #84 @ 0x54 800671e: 4a09 ldr r2, [pc, #36] @ (8006744 ) 8006720: 6013 str r3, [r2, #0] } 8006722: bf00 nop 8006724: 3714 adds r7, #20 8006726: 46bd mov sp, r7 8006728: f85d 7b04 ldr.w r7, [sp], #4 800672c: 4770 bx lr 800672e: bf00 nop 8006730: 200014ac .word 0x200014ac 8006734: 20001498 .word 0x20001498 8006738: 2000148c .word 0x2000148c 800673c: 20000fb4 .word 0x20000fb4 8006740: 20000fb0 .word 0x20000fb0 8006744: 20000010 .word 0x20000010 08006748 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8006748: b580 push {r7, lr} 800674a: b084 sub sp, #16 800674c: af00 add r7, sp, #0 800674e: 6078 str r0, [r7, #4] 8006750: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 8006752: 687b ldr r3, [r7, #4] 8006754: 2b00 cmp r3, #0 8006756: d10b bne.n 8006770 __asm volatile 8006758: f04f 0350 mov.w r3, #80 @ 0x50 800675c: f383 8811 msr BASEPRI, r3 8006760: f3bf 8f6f isb sy 8006764: f3bf 8f4f dsb sy 8006768: 60fb str r3, [r7, #12] } 800676a: bf00 nop 800676c: bf00 nop 800676e: e7fd b.n 800676c /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8006770: 4b07 ldr r3, [pc, #28] @ (8006790 ) 8006772: 681b ldr r3, [r3, #0] 8006774: 3318 adds r3, #24 8006776: 4619 mov r1, r3 8006778: 6878 ldr r0, [r7, #4] 800677a: f7fe fdd4 bl 8005326 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 800677e: 2101 movs r1, #1 8006780: 6838 ldr r0, [r7, #0] 8006782: f000 fa87 bl 8006c94 } 8006786: bf00 nop 8006788: 3710 adds r7, #16 800678a: 46bd mov sp, r7 800678c: bd80 pop {r7, pc} 800678e: bf00 nop 8006790: 20000fb0 .word 0x20000fb0 08006794 : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8006794: b580 push {r7, lr} 8006796: b086 sub sp, #24 8006798: af00 add r7, sp, #0 800679a: 60f8 str r0, [r7, #12] 800679c: 60b9 str r1, [r7, #8] 800679e: 607a str r2, [r7, #4] configASSERT( pxEventList ); 80067a0: 68fb ldr r3, [r7, #12] 80067a2: 2b00 cmp r3, #0 80067a4: d10b bne.n 80067be __asm volatile 80067a6: f04f 0350 mov.w r3, #80 @ 0x50 80067aa: f383 8811 msr BASEPRI, r3 80067ae: f3bf 8f6f isb sy 80067b2: f3bf 8f4f dsb sy 80067b6: 617b str r3, [r7, #20] } 80067b8: bf00 nop 80067ba: bf00 nop 80067bc: e7fd b.n 80067ba /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80067be: 4b0a ldr r3, [pc, #40] @ (80067e8 ) 80067c0: 681b ldr r3, [r3, #0] 80067c2: 3318 adds r3, #24 80067c4: 4619 mov r1, r3 80067c6: 68f8 ldr r0, [r7, #12] 80067c8: f7fe fd89 bl 80052de /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 80067cc: 687b ldr r3, [r7, #4] 80067ce: 2b00 cmp r3, #0 80067d0: d002 beq.n 80067d8 { xTicksToWait = portMAX_DELAY; 80067d2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80067d6: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 80067d8: 6879 ldr r1, [r7, #4] 80067da: 68b8 ldr r0, [r7, #8] 80067dc: f000 fa5a bl 8006c94 } 80067e0: bf00 nop 80067e2: 3718 adds r7, #24 80067e4: 46bd mov sp, r7 80067e6: bd80 pop {r7, pc} 80067e8: 20000fb0 .word 0x20000fb0 080067ec : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 80067ec: b580 push {r7, lr} 80067ee: b086 sub sp, #24 80067f0: af00 add r7, sp, #0 80067f2: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80067f4: 687b ldr r3, [r7, #4] 80067f6: 68db ldr r3, [r3, #12] 80067f8: 68db ldr r3, [r3, #12] 80067fa: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 80067fc: 693b ldr r3, [r7, #16] 80067fe: 2b00 cmp r3, #0 8006800: d10b bne.n 800681a __asm volatile 8006802: f04f 0350 mov.w r3, #80 @ 0x50 8006806: f383 8811 msr BASEPRI, r3 800680a: f3bf 8f6f isb sy 800680e: f3bf 8f4f dsb sy 8006812: 60fb str r3, [r7, #12] } 8006814: bf00 nop 8006816: bf00 nop 8006818: e7fd b.n 8006816 ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 800681a: 693b ldr r3, [r7, #16] 800681c: 3318 adds r3, #24 800681e: 4618 mov r0, r3 8006820: f7fe fdba bl 8005398 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8006824: 4b1d ldr r3, [pc, #116] @ (800689c ) 8006826: 681b ldr r3, [r3, #0] 8006828: 2b00 cmp r3, #0 800682a: d11d bne.n 8006868 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 800682c: 693b ldr r3, [r7, #16] 800682e: 3304 adds r3, #4 8006830: 4618 mov r0, r3 8006832: f7fe fdb1 bl 8005398 prvAddTaskToReadyList( pxUnblockedTCB ); 8006836: 693b ldr r3, [r7, #16] 8006838: 6ada ldr r2, [r3, #44] @ 0x2c 800683a: 4b19 ldr r3, [pc, #100] @ (80068a0 ) 800683c: 681b ldr r3, [r3, #0] 800683e: 429a cmp r2, r3 8006840: d903 bls.n 800684a 8006842: 693b ldr r3, [r7, #16] 8006844: 6adb ldr r3, [r3, #44] @ 0x2c 8006846: 4a16 ldr r2, [pc, #88] @ (80068a0 ) 8006848: 6013 str r3, [r2, #0] 800684a: 693b ldr r3, [r7, #16] 800684c: 6ada ldr r2, [r3, #44] @ 0x2c 800684e: 4613 mov r3, r2 8006850: 009b lsls r3, r3, #2 8006852: 4413 add r3, r2 8006854: 009b lsls r3, r3, #2 8006856: 4a13 ldr r2, [pc, #76] @ (80068a4 ) 8006858: 441a add r2, r3 800685a: 693b ldr r3, [r7, #16] 800685c: 3304 adds r3, #4 800685e: 4619 mov r1, r3 8006860: 4610 mov r0, r2 8006862: f7fe fd3c bl 80052de 8006866: e005 b.n 8006874 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8006868: 693b ldr r3, [r7, #16] 800686a: 3318 adds r3, #24 800686c: 4619 mov r1, r3 800686e: 480e ldr r0, [pc, #56] @ (80068a8 ) 8006870: f7fe fd35 bl 80052de } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 8006874: 693b ldr r3, [r7, #16] 8006876: 6ada ldr r2, [r3, #44] @ 0x2c 8006878: 4b0c ldr r3, [pc, #48] @ (80068ac ) 800687a: 681b ldr r3, [r3, #0] 800687c: 6adb ldr r3, [r3, #44] @ 0x2c 800687e: 429a cmp r2, r3 8006880: d905 bls.n 800688e { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 8006882: 2301 movs r3, #1 8006884: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 8006886: 4b0a ldr r3, [pc, #40] @ (80068b0 ) 8006888: 2201 movs r2, #1 800688a: 601a str r2, [r3, #0] 800688c: e001 b.n 8006892 } else { xReturn = pdFALSE; 800688e: 2300 movs r3, #0 8006890: 617b str r3, [r7, #20] } return xReturn; 8006892: 697b ldr r3, [r7, #20] } 8006894: 4618 mov r0, r3 8006896: 3718 adds r7, #24 8006898: 46bd mov sp, r7 800689a: bd80 pop {r7, pc} 800689c: 200014ac .word 0x200014ac 80068a0: 2000148c .word 0x2000148c 80068a4: 20000fb4 .word 0x20000fb4 80068a8: 20001444 .word 0x20001444 80068ac: 20000fb0 .word 0x20000fb0 80068b0: 20001498 .word 0x20001498 080068b4 : taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 80068b4: b480 push {r7} 80068b6: b083 sub sp, #12 80068b8: af00 add r7, sp, #0 80068ba: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 80068bc: 4b06 ldr r3, [pc, #24] @ (80068d8 ) 80068be: 681a ldr r2, [r3, #0] 80068c0: 687b ldr r3, [r7, #4] 80068c2: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 80068c4: 4b05 ldr r3, [pc, #20] @ (80068dc ) 80068c6: 681a ldr r2, [r3, #0] 80068c8: 687b ldr r3, [r7, #4] 80068ca: 605a str r2, [r3, #4] } 80068cc: bf00 nop 80068ce: 370c adds r7, #12 80068d0: 46bd mov sp, r7 80068d2: f85d 7b04 ldr.w r7, [sp], #4 80068d6: 4770 bx lr 80068d8: 2000149c .word 0x2000149c 80068dc: 20001488 .word 0x20001488 080068e0 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 80068e0: b580 push {r7, lr} 80068e2: b088 sub sp, #32 80068e4: af00 add r7, sp, #0 80068e6: 6078 str r0, [r7, #4] 80068e8: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 80068ea: 687b ldr r3, [r7, #4] 80068ec: 2b00 cmp r3, #0 80068ee: d10b bne.n 8006908 __asm volatile 80068f0: f04f 0350 mov.w r3, #80 @ 0x50 80068f4: f383 8811 msr BASEPRI, r3 80068f8: f3bf 8f6f isb sy 80068fc: f3bf 8f4f dsb sy 8006900: 613b str r3, [r7, #16] } 8006902: bf00 nop 8006904: bf00 nop 8006906: e7fd b.n 8006904 configASSERT( pxTicksToWait ); 8006908: 683b ldr r3, [r7, #0] 800690a: 2b00 cmp r3, #0 800690c: d10b bne.n 8006926 __asm volatile 800690e: f04f 0350 mov.w r3, #80 @ 0x50 8006912: f383 8811 msr BASEPRI, r3 8006916: f3bf 8f6f isb sy 800691a: f3bf 8f4f dsb sy 800691e: 60fb str r3, [r7, #12] } 8006920: bf00 nop 8006922: bf00 nop 8006924: e7fd b.n 8006922 taskENTER_CRITICAL(); 8006926: f000 fe97 bl 8007658 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 800692a: 4b1d ldr r3, [pc, #116] @ (80069a0 ) 800692c: 681b ldr r3, [r3, #0] 800692e: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8006930: 687b ldr r3, [r7, #4] 8006932: 685b ldr r3, [r3, #4] 8006934: 69ba ldr r2, [r7, #24] 8006936: 1ad3 subs r3, r2, r3 8006938: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 800693a: 683b ldr r3, [r7, #0] 800693c: 681b ldr r3, [r3, #0] 800693e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006942: d102 bne.n 800694a { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8006944: 2300 movs r3, #0 8006946: 61fb str r3, [r7, #28] 8006948: e023 b.n 8006992 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 800694a: 687b ldr r3, [r7, #4] 800694c: 681a ldr r2, [r3, #0] 800694e: 4b15 ldr r3, [pc, #84] @ (80069a4 ) 8006950: 681b ldr r3, [r3, #0] 8006952: 429a cmp r2, r3 8006954: d007 beq.n 8006966 8006956: 687b ldr r3, [r7, #4] 8006958: 685b ldr r3, [r3, #4] 800695a: 69ba ldr r2, [r7, #24] 800695c: 429a cmp r2, r3 800695e: d302 bcc.n 8006966 /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 8006960: 2301 movs r3, #1 8006962: 61fb str r3, [r7, #28] 8006964: e015 b.n 8006992 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 8006966: 683b ldr r3, [r7, #0] 8006968: 681b ldr r3, [r3, #0] 800696a: 697a ldr r2, [r7, #20] 800696c: 429a cmp r2, r3 800696e: d20b bcs.n 8006988 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 8006970: 683b ldr r3, [r7, #0] 8006972: 681a ldr r2, [r3, #0] 8006974: 697b ldr r3, [r7, #20] 8006976: 1ad2 subs r2, r2, r3 8006978: 683b ldr r3, [r7, #0] 800697a: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 800697c: 6878 ldr r0, [r7, #4] 800697e: f7ff ff99 bl 80068b4 xReturn = pdFALSE; 8006982: 2300 movs r3, #0 8006984: 61fb str r3, [r7, #28] 8006986: e004 b.n 8006992 } else { *pxTicksToWait = 0; 8006988: 683b ldr r3, [r7, #0] 800698a: 2200 movs r2, #0 800698c: 601a str r2, [r3, #0] xReturn = pdTRUE; 800698e: 2301 movs r3, #1 8006990: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 8006992: f000 fe93 bl 80076bc return xReturn; 8006996: 69fb ldr r3, [r7, #28] } 8006998: 4618 mov r0, r3 800699a: 3720 adds r7, #32 800699c: 46bd mov sp, r7 800699e: bd80 pop {r7, pc} 80069a0: 20001488 .word 0x20001488 80069a4: 2000149c .word 0x2000149c 080069a8 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 80069a8: b480 push {r7} 80069aa: af00 add r7, sp, #0 xYieldPending = pdTRUE; 80069ac: 4b03 ldr r3, [pc, #12] @ (80069bc ) 80069ae: 2201 movs r2, #1 80069b0: 601a str r2, [r3, #0] } 80069b2: bf00 nop 80069b4: 46bd mov sp, r7 80069b6: f85d 7b04 ldr.w r7, [sp], #4 80069ba: 4770 bx lr 80069bc: 20001498 .word 0x20001498 080069c0 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 80069c0: b580 push {r7, lr} 80069c2: b082 sub sp, #8 80069c4: af00 add r7, sp, #0 80069c6: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 80069c8: f000 f852 bl 8006a70 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 80069cc: 4b06 ldr r3, [pc, #24] @ (80069e8 ) 80069ce: 681b ldr r3, [r3, #0] 80069d0: 2b01 cmp r3, #1 80069d2: d9f9 bls.n 80069c8 { taskYIELD(); 80069d4: 4b05 ldr r3, [pc, #20] @ (80069ec ) 80069d6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80069da: 601a str r2, [r3, #0] 80069dc: f3bf 8f4f dsb sy 80069e0: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 80069e4: e7f0 b.n 80069c8 80069e6: bf00 nop 80069e8: 20000fb4 .word 0x20000fb4 80069ec: e000ed04 .word 0xe000ed04 080069f0 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 80069f0: b580 push {r7, lr} 80069f2: b082 sub sp, #8 80069f4: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 80069f6: 2300 movs r3, #0 80069f8: 607b str r3, [r7, #4] 80069fa: e00c b.n 8006a16 { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 80069fc: 687a ldr r2, [r7, #4] 80069fe: 4613 mov r3, r2 8006a00: 009b lsls r3, r3, #2 8006a02: 4413 add r3, r2 8006a04: 009b lsls r3, r3, #2 8006a06: 4a12 ldr r2, [pc, #72] @ (8006a50 ) 8006a08: 4413 add r3, r2 8006a0a: 4618 mov r0, r3 8006a0c: f7fe fc3a bl 8005284 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8006a10: 687b ldr r3, [r7, #4] 8006a12: 3301 adds r3, #1 8006a14: 607b str r3, [r7, #4] 8006a16: 687b ldr r3, [r7, #4] 8006a18: 2b37 cmp r3, #55 @ 0x37 8006a1a: d9ef bls.n 80069fc } vListInitialise( &xDelayedTaskList1 ); 8006a1c: 480d ldr r0, [pc, #52] @ (8006a54 ) 8006a1e: f7fe fc31 bl 8005284 vListInitialise( &xDelayedTaskList2 ); 8006a22: 480d ldr r0, [pc, #52] @ (8006a58 ) 8006a24: f7fe fc2e bl 8005284 vListInitialise( &xPendingReadyList ); 8006a28: 480c ldr r0, [pc, #48] @ (8006a5c ) 8006a2a: f7fe fc2b bl 8005284 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 8006a2e: 480c ldr r0, [pc, #48] @ (8006a60 ) 8006a30: f7fe fc28 bl 8005284 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8006a34: 480b ldr r0, [pc, #44] @ (8006a64 ) 8006a36: f7fe fc25 bl 8005284 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8006a3a: 4b0b ldr r3, [pc, #44] @ (8006a68 ) 8006a3c: 4a05 ldr r2, [pc, #20] @ (8006a54 ) 8006a3e: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8006a40: 4b0a ldr r3, [pc, #40] @ (8006a6c ) 8006a42: 4a05 ldr r2, [pc, #20] @ (8006a58 ) 8006a44: 601a str r2, [r3, #0] } 8006a46: bf00 nop 8006a48: 3708 adds r7, #8 8006a4a: 46bd mov sp, r7 8006a4c: bd80 pop {r7, pc} 8006a4e: bf00 nop 8006a50: 20000fb4 .word 0x20000fb4 8006a54: 20001414 .word 0x20001414 8006a58: 20001428 .word 0x20001428 8006a5c: 20001444 .word 0x20001444 8006a60: 20001458 .word 0x20001458 8006a64: 20001470 .word 0x20001470 8006a68: 2000143c .word 0x2000143c 8006a6c: 20001440 .word 0x20001440 08006a70 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 8006a70: b580 push {r7, lr} 8006a72: b082 sub sp, #8 8006a74: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8006a76: e019 b.n 8006aac { taskENTER_CRITICAL(); 8006a78: f000 fdee bl 8007658 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8006a7c: 4b10 ldr r3, [pc, #64] @ (8006ac0 ) 8006a7e: 68db ldr r3, [r3, #12] 8006a80: 68db ldr r3, [r3, #12] 8006a82: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8006a84: 687b ldr r3, [r7, #4] 8006a86: 3304 adds r3, #4 8006a88: 4618 mov r0, r3 8006a8a: f7fe fc85 bl 8005398 --uxCurrentNumberOfTasks; 8006a8e: 4b0d ldr r3, [pc, #52] @ (8006ac4 ) 8006a90: 681b ldr r3, [r3, #0] 8006a92: 3b01 subs r3, #1 8006a94: 4a0b ldr r2, [pc, #44] @ (8006ac4 ) 8006a96: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 8006a98: 4b0b ldr r3, [pc, #44] @ (8006ac8 ) 8006a9a: 681b ldr r3, [r3, #0] 8006a9c: 3b01 subs r3, #1 8006a9e: 4a0a ldr r2, [pc, #40] @ (8006ac8 ) 8006aa0: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 8006aa2: f000 fe0b bl 80076bc prvDeleteTCB( pxTCB ); 8006aa6: 6878 ldr r0, [r7, #4] 8006aa8: f000 f810 bl 8006acc while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8006aac: 4b06 ldr r3, [pc, #24] @ (8006ac8 ) 8006aae: 681b ldr r3, [r3, #0] 8006ab0: 2b00 cmp r3, #0 8006ab2: d1e1 bne.n 8006a78 } } #endif /* INCLUDE_vTaskDelete */ } 8006ab4: bf00 nop 8006ab6: bf00 nop 8006ab8: 3708 adds r7, #8 8006aba: 46bd mov sp, r7 8006abc: bd80 pop {r7, pc} 8006abe: bf00 nop 8006ac0: 20001458 .word 0x20001458 8006ac4: 20001484 .word 0x20001484 8006ac8: 2000146c .word 0x2000146c 08006acc : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 8006acc: b580 push {r7, lr} 8006ace: b084 sub sp, #16 8006ad0: af00 add r7, sp, #0 8006ad2: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 8006ad4: 687b ldr r3, [r7, #4] 8006ad6: 3354 adds r3, #84 @ 0x54 8006ad8: 4618 mov r0, r3 8006ada: f001 f8d5 bl 8007c88 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8006ade: 687b ldr r3, [r7, #4] 8006ae0: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8006ae4: 2b00 cmp r3, #0 8006ae6: d108 bne.n 8006afa { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 8006ae8: 687b ldr r3, [r7, #4] 8006aea: 6b1b ldr r3, [r3, #48] @ 0x30 8006aec: 4618 mov r0, r3 8006aee: f000 ffa3 bl 8007a38 vPortFree( pxTCB ); 8006af2: 6878 ldr r0, [r7, #4] 8006af4: f000 ffa0 bl 8007a38 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8006af8: e019 b.n 8006b2e else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8006afa: 687b ldr r3, [r7, #4] 8006afc: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8006b00: 2b01 cmp r3, #1 8006b02: d103 bne.n 8006b0c vPortFree( pxTCB ); 8006b04: 6878 ldr r0, [r7, #4] 8006b06: f000 ff97 bl 8007a38 } 8006b0a: e010 b.n 8006b2e configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8006b0c: 687b ldr r3, [r7, #4] 8006b0e: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8006b12: 2b02 cmp r3, #2 8006b14: d00b beq.n 8006b2e __asm volatile 8006b16: f04f 0350 mov.w r3, #80 @ 0x50 8006b1a: f383 8811 msr BASEPRI, r3 8006b1e: f3bf 8f6f isb sy 8006b22: f3bf 8f4f dsb sy 8006b26: 60fb str r3, [r7, #12] } 8006b28: bf00 nop 8006b2a: bf00 nop 8006b2c: e7fd b.n 8006b2a } 8006b2e: bf00 nop 8006b30: 3710 adds r7, #16 8006b32: 46bd mov sp, r7 8006b34: bd80 pop {r7, pc} ... 08006b38 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8006b38: b480 push {r7} 8006b3a: b083 sub sp, #12 8006b3c: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8006b3e: 4b0c ldr r3, [pc, #48] @ (8006b70 ) 8006b40: 681b ldr r3, [r3, #0] 8006b42: 681b ldr r3, [r3, #0] 8006b44: 2b00 cmp r3, #0 8006b46: d104 bne.n 8006b52 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8006b48: 4b0a ldr r3, [pc, #40] @ (8006b74 ) 8006b4a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8006b4e: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8006b50: e008 b.n 8006b64 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8006b52: 4b07 ldr r3, [pc, #28] @ (8006b70 ) 8006b54: 681b ldr r3, [r3, #0] 8006b56: 68db ldr r3, [r3, #12] 8006b58: 68db ldr r3, [r3, #12] 8006b5a: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 8006b5c: 687b ldr r3, [r7, #4] 8006b5e: 685b ldr r3, [r3, #4] 8006b60: 4a04 ldr r2, [pc, #16] @ (8006b74 ) 8006b62: 6013 str r3, [r2, #0] } 8006b64: bf00 nop 8006b66: 370c adds r7, #12 8006b68: 46bd mov sp, r7 8006b6a: f85d 7b04 ldr.w r7, [sp], #4 8006b6e: 4770 bx lr 8006b70: 2000143c .word 0x2000143c 8006b74: 200014a4 .word 0x200014a4 08006b78 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8006b78: b480 push {r7} 8006b7a: b083 sub sp, #12 8006b7c: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8006b7e: 4b0b ldr r3, [pc, #44] @ (8006bac ) 8006b80: 681b ldr r3, [r3, #0] 8006b82: 2b00 cmp r3, #0 8006b84: d102 bne.n 8006b8c { xReturn = taskSCHEDULER_NOT_STARTED; 8006b86: 2301 movs r3, #1 8006b88: 607b str r3, [r7, #4] 8006b8a: e008 b.n 8006b9e } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8006b8c: 4b08 ldr r3, [pc, #32] @ (8006bb0 ) 8006b8e: 681b ldr r3, [r3, #0] 8006b90: 2b00 cmp r3, #0 8006b92: d102 bne.n 8006b9a { xReturn = taskSCHEDULER_RUNNING; 8006b94: 2302 movs r3, #2 8006b96: 607b str r3, [r7, #4] 8006b98: e001 b.n 8006b9e } else { xReturn = taskSCHEDULER_SUSPENDED; 8006b9a: 2300 movs r3, #0 8006b9c: 607b str r3, [r7, #4] } } return xReturn; 8006b9e: 687b ldr r3, [r7, #4] } 8006ba0: 4618 mov r0, r3 8006ba2: 370c adds r7, #12 8006ba4: 46bd mov sp, r7 8006ba6: f85d 7b04 ldr.w r7, [sp], #4 8006baa: 4770 bx lr 8006bac: 20001490 .word 0x20001490 8006bb0: 200014ac .word 0x200014ac 08006bb4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8006bb4: b580 push {r7, lr} 8006bb6: b086 sub sp, #24 8006bb8: af00 add r7, sp, #0 8006bba: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8006bbc: 687b ldr r3, [r7, #4] 8006bbe: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8006bc0: 2300 movs r3, #0 8006bc2: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8006bc4: 687b ldr r3, [r7, #4] 8006bc6: 2b00 cmp r3, #0 8006bc8: d058 beq.n 8006c7c { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8006bca: 4b2f ldr r3, [pc, #188] @ (8006c88 ) 8006bcc: 681b ldr r3, [r3, #0] 8006bce: 693a ldr r2, [r7, #16] 8006bd0: 429a cmp r2, r3 8006bd2: d00b beq.n 8006bec __asm volatile 8006bd4: f04f 0350 mov.w r3, #80 @ 0x50 8006bd8: f383 8811 msr BASEPRI, r3 8006bdc: f3bf 8f6f isb sy 8006be0: f3bf 8f4f dsb sy 8006be4: 60fb str r3, [r7, #12] } 8006be6: bf00 nop 8006be8: bf00 nop 8006bea: e7fd b.n 8006be8 configASSERT( pxTCB->uxMutexesHeld ); 8006bec: 693b ldr r3, [r7, #16] 8006bee: 6d1b ldr r3, [r3, #80] @ 0x50 8006bf0: 2b00 cmp r3, #0 8006bf2: d10b bne.n 8006c0c __asm volatile 8006bf4: f04f 0350 mov.w r3, #80 @ 0x50 8006bf8: f383 8811 msr BASEPRI, r3 8006bfc: f3bf 8f6f isb sy 8006c00: f3bf 8f4f dsb sy 8006c04: 60bb str r3, [r7, #8] } 8006c06: bf00 nop 8006c08: bf00 nop 8006c0a: e7fd b.n 8006c08 ( pxTCB->uxMutexesHeld )--; 8006c0c: 693b ldr r3, [r7, #16] 8006c0e: 6d1b ldr r3, [r3, #80] @ 0x50 8006c10: 1e5a subs r2, r3, #1 8006c12: 693b ldr r3, [r7, #16] 8006c14: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 8006c16: 693b ldr r3, [r7, #16] 8006c18: 6ada ldr r2, [r3, #44] @ 0x2c 8006c1a: 693b ldr r3, [r7, #16] 8006c1c: 6cdb ldr r3, [r3, #76] @ 0x4c 8006c1e: 429a cmp r2, r3 8006c20: d02c beq.n 8006c7c { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 8006c22: 693b ldr r3, [r7, #16] 8006c24: 6d1b ldr r3, [r3, #80] @ 0x50 8006c26: 2b00 cmp r3, #0 8006c28: d128 bne.n 8006c7c /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8006c2a: 693b ldr r3, [r7, #16] 8006c2c: 3304 adds r3, #4 8006c2e: 4618 mov r0, r3 8006c30: f7fe fbb2 bl 8005398 } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8006c34: 693b ldr r3, [r7, #16] 8006c36: 6cda ldr r2, [r3, #76] @ 0x4c 8006c38: 693b ldr r3, [r7, #16] 8006c3a: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8006c3c: 693b ldr r3, [r7, #16] 8006c3e: 6adb ldr r3, [r3, #44] @ 0x2c 8006c40: f1c3 0238 rsb r2, r3, #56 @ 0x38 8006c44: 693b ldr r3, [r7, #16] 8006c46: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8006c48: 693b ldr r3, [r7, #16] 8006c4a: 6ada ldr r2, [r3, #44] @ 0x2c 8006c4c: 4b0f ldr r3, [pc, #60] @ (8006c8c ) 8006c4e: 681b ldr r3, [r3, #0] 8006c50: 429a cmp r2, r3 8006c52: d903 bls.n 8006c5c 8006c54: 693b ldr r3, [r7, #16] 8006c56: 6adb ldr r3, [r3, #44] @ 0x2c 8006c58: 4a0c ldr r2, [pc, #48] @ (8006c8c ) 8006c5a: 6013 str r3, [r2, #0] 8006c5c: 693b ldr r3, [r7, #16] 8006c5e: 6ada ldr r2, [r3, #44] @ 0x2c 8006c60: 4613 mov r3, r2 8006c62: 009b lsls r3, r3, #2 8006c64: 4413 add r3, r2 8006c66: 009b lsls r3, r3, #2 8006c68: 4a09 ldr r2, [pc, #36] @ (8006c90 ) 8006c6a: 441a add r2, r3 8006c6c: 693b ldr r3, [r7, #16] 8006c6e: 3304 adds r3, #4 8006c70: 4619 mov r1, r3 8006c72: 4610 mov r0, r2 8006c74: f7fe fb33 bl 80052de in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8006c78: 2301 movs r3, #1 8006c7a: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8006c7c: 697b ldr r3, [r7, #20] } 8006c7e: 4618 mov r0, r3 8006c80: 3718 adds r7, #24 8006c82: 46bd mov sp, r7 8006c84: bd80 pop {r7, pc} 8006c86: bf00 nop 8006c88: 20000fb0 .word 0x20000fb0 8006c8c: 2000148c .word 0x2000148c 8006c90: 20000fb4 .word 0x20000fb4 08006c94 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8006c94: b580 push {r7, lr} 8006c96: b084 sub sp, #16 8006c98: af00 add r7, sp, #0 8006c9a: 6078 str r0, [r7, #4] 8006c9c: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8006c9e: 4b21 ldr r3, [pc, #132] @ (8006d24 ) 8006ca0: 681b ldr r3, [r3, #0] 8006ca2: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8006ca4: 4b20 ldr r3, [pc, #128] @ (8006d28 ) 8006ca6: 681b ldr r3, [r3, #0] 8006ca8: 3304 adds r3, #4 8006caa: 4618 mov r0, r3 8006cac: f7fe fb74 bl 8005398 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8006cb0: 687b ldr r3, [r7, #4] 8006cb2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006cb6: d10a bne.n 8006cce 8006cb8: 683b ldr r3, [r7, #0] 8006cba: 2b00 cmp r3, #0 8006cbc: d007 beq.n 8006cce { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8006cbe: 4b1a ldr r3, [pc, #104] @ (8006d28 ) 8006cc0: 681b ldr r3, [r3, #0] 8006cc2: 3304 adds r3, #4 8006cc4: 4619 mov r1, r3 8006cc6: 4819 ldr r0, [pc, #100] @ (8006d2c ) 8006cc8: f7fe fb09 bl 80052de /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8006ccc: e026 b.n 8006d1c xTimeToWake = xConstTickCount + xTicksToWait; 8006cce: 68fa ldr r2, [r7, #12] 8006cd0: 687b ldr r3, [r7, #4] 8006cd2: 4413 add r3, r2 8006cd4: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 8006cd6: 4b14 ldr r3, [pc, #80] @ (8006d28 ) 8006cd8: 681b ldr r3, [r3, #0] 8006cda: 68ba ldr r2, [r7, #8] 8006cdc: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 8006cde: 68ba ldr r2, [r7, #8] 8006ce0: 68fb ldr r3, [r7, #12] 8006ce2: 429a cmp r2, r3 8006ce4: d209 bcs.n 8006cfa vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8006ce6: 4b12 ldr r3, [pc, #72] @ (8006d30 ) 8006ce8: 681a ldr r2, [r3, #0] 8006cea: 4b0f ldr r3, [pc, #60] @ (8006d28 ) 8006cec: 681b ldr r3, [r3, #0] 8006cee: 3304 adds r3, #4 8006cf0: 4619 mov r1, r3 8006cf2: 4610 mov r0, r2 8006cf4: f7fe fb17 bl 8005326 } 8006cf8: e010 b.n 8006d1c vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8006cfa: 4b0e ldr r3, [pc, #56] @ (8006d34 ) 8006cfc: 681a ldr r2, [r3, #0] 8006cfe: 4b0a ldr r3, [pc, #40] @ (8006d28 ) 8006d00: 681b ldr r3, [r3, #0] 8006d02: 3304 adds r3, #4 8006d04: 4619 mov r1, r3 8006d06: 4610 mov r0, r2 8006d08: f7fe fb0d bl 8005326 if( xTimeToWake < xNextTaskUnblockTime ) 8006d0c: 4b0a ldr r3, [pc, #40] @ (8006d38 ) 8006d0e: 681b ldr r3, [r3, #0] 8006d10: 68ba ldr r2, [r7, #8] 8006d12: 429a cmp r2, r3 8006d14: d202 bcs.n 8006d1c xNextTaskUnblockTime = xTimeToWake; 8006d16: 4a08 ldr r2, [pc, #32] @ (8006d38 ) 8006d18: 68bb ldr r3, [r7, #8] 8006d1a: 6013 str r3, [r2, #0] } 8006d1c: bf00 nop 8006d1e: 3710 adds r7, #16 8006d20: 46bd mov sp, r7 8006d22: bd80 pop {r7, pc} 8006d24: 20001488 .word 0x20001488 8006d28: 20000fb0 .word 0x20000fb0 8006d2c: 20001470 .word 0x20001470 8006d30: 20001440 .word 0x20001440 8006d34: 2000143c .word 0x2000143c 8006d38: 200014a4 .word 0x200014a4 08006d3c : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8006d3c: b580 push {r7, lr} 8006d3e: b08a sub sp, #40 @ 0x28 8006d40: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 8006d42: 2300 movs r3, #0 8006d44: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 8006d46: f000 fb13 bl 8007370 if( xTimerQueue != NULL ) 8006d4a: 4b1d ldr r3, [pc, #116] @ (8006dc0 ) 8006d4c: 681b ldr r3, [r3, #0] 8006d4e: 2b00 cmp r3, #0 8006d50: d021 beq.n 8006d96 { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 8006d52: 2300 movs r3, #0 8006d54: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 8006d56: 2300 movs r3, #0 8006d58: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 8006d5a: 1d3a adds r2, r7, #4 8006d5c: f107 0108 add.w r1, r7, #8 8006d60: f107 030c add.w r3, r7, #12 8006d64: 4618 mov r0, r3 8006d66: f7fe fa73 bl 8005250 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 8006d6a: 6879 ldr r1, [r7, #4] 8006d6c: 68bb ldr r3, [r7, #8] 8006d6e: 68fa ldr r2, [r7, #12] 8006d70: 9202 str r2, [sp, #8] 8006d72: 9301 str r3, [sp, #4] 8006d74: 2302 movs r3, #2 8006d76: 9300 str r3, [sp, #0] 8006d78: 2300 movs r3, #0 8006d7a: 460a mov r2, r1 8006d7c: 4911 ldr r1, [pc, #68] @ (8006dc4 ) 8006d7e: 4812 ldr r0, [pc, #72] @ (8006dc8 ) 8006d80: f7ff f82e bl 8005de0 8006d84: 4603 mov r3, r0 8006d86: 4a11 ldr r2, [pc, #68] @ (8006dcc ) 8006d88: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 8006d8a: 4b10 ldr r3, [pc, #64] @ (8006dcc ) 8006d8c: 681b ldr r3, [r3, #0] 8006d8e: 2b00 cmp r3, #0 8006d90: d001 beq.n 8006d96 { xReturn = pdPASS; 8006d92: 2301 movs r3, #1 8006d94: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 8006d96: 697b ldr r3, [r7, #20] 8006d98: 2b00 cmp r3, #0 8006d9a: d10b bne.n 8006db4 __asm volatile 8006d9c: f04f 0350 mov.w r3, #80 @ 0x50 8006da0: f383 8811 msr BASEPRI, r3 8006da4: f3bf 8f6f isb sy 8006da8: f3bf 8f4f dsb sy 8006dac: 613b str r3, [r7, #16] } 8006dae: bf00 nop 8006db0: bf00 nop 8006db2: e7fd b.n 8006db0 return xReturn; 8006db4: 697b ldr r3, [r7, #20] } 8006db6: 4618 mov r0, r3 8006db8: 3718 adds r7, #24 8006dba: 46bd mov sp, r7 8006dbc: bd80 pop {r7, pc} 8006dbe: bf00 nop 8006dc0: 200014e0 .word 0x200014e0 8006dc4: 08007e9c .word 0x08007e9c 8006dc8: 08006f09 .word 0x08006f09 8006dcc: 200014e4 .word 0x200014e4 08006dd0 : } } /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 8006dd0: b580 push {r7, lr} 8006dd2: b08a sub sp, #40 @ 0x28 8006dd4: af00 add r7, sp, #0 8006dd6: 60f8 str r0, [r7, #12] 8006dd8: 60b9 str r1, [r7, #8] 8006dda: 607a str r2, [r7, #4] 8006ddc: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 8006dde: 2300 movs r3, #0 8006de0: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 8006de2: 68fb ldr r3, [r7, #12] 8006de4: 2b00 cmp r3, #0 8006de6: d10b bne.n 8006e00 __asm volatile 8006de8: f04f 0350 mov.w r3, #80 @ 0x50 8006dec: f383 8811 msr BASEPRI, r3 8006df0: f3bf 8f6f isb sy 8006df4: f3bf 8f4f dsb sy 8006df8: 623b str r3, [r7, #32] } 8006dfa: bf00 nop 8006dfc: bf00 nop 8006dfe: e7fd b.n 8006dfc /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8006e00: 4b19 ldr r3, [pc, #100] @ (8006e68 ) 8006e02: 681b ldr r3, [r3, #0] 8006e04: 2b00 cmp r3, #0 8006e06: d02a beq.n 8006e5e { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 8006e08: 68bb ldr r3, [r7, #8] 8006e0a: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 8006e0c: 687b ldr r3, [r7, #4] 8006e0e: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 8006e10: 68fb ldr r3, [r7, #12] 8006e12: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 8006e14: 68bb ldr r3, [r7, #8] 8006e16: 2b05 cmp r3, #5 8006e18: dc18 bgt.n 8006e4c { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 8006e1a: f7ff fead bl 8006b78 8006e1e: 4603 mov r3, r0 8006e20: 2b02 cmp r3, #2 8006e22: d109 bne.n 8006e38 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 8006e24: 4b10 ldr r3, [pc, #64] @ (8006e68 ) 8006e26: 6818 ldr r0, [r3, #0] 8006e28: f107 0110 add.w r1, r7, #16 8006e2c: 2300 movs r3, #0 8006e2e: 6b3a ldr r2, [r7, #48] @ 0x30 8006e30: f7fe fbe6 bl 8005600 8006e34: 6278 str r0, [r7, #36] @ 0x24 8006e36: e012 b.n 8006e5e } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 8006e38: 4b0b ldr r3, [pc, #44] @ (8006e68 ) 8006e3a: 6818 ldr r0, [r3, #0] 8006e3c: f107 0110 add.w r1, r7, #16 8006e40: 2300 movs r3, #0 8006e42: 2200 movs r2, #0 8006e44: f7fe fbdc bl 8005600 8006e48: 6278 str r0, [r7, #36] @ 0x24 8006e4a: e008 b.n 8006e5e } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 8006e4c: 4b06 ldr r3, [pc, #24] @ (8006e68 ) 8006e4e: 6818 ldr r0, [r3, #0] 8006e50: f107 0110 add.w r1, r7, #16 8006e54: 2300 movs r3, #0 8006e56: 683a ldr r2, [r7, #0] 8006e58: f7fe fcd4 bl 8005804 8006e5c: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8006e5e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8006e60: 4618 mov r0, r3 8006e62: 3728 adds r7, #40 @ 0x28 8006e64: 46bd mov sp, r7 8006e66: bd80 pop {r7, pc} 8006e68: 200014e0 .word 0x200014e0 08006e6c : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 8006e6c: b580 push {r7, lr} 8006e6e: b088 sub sp, #32 8006e70: af02 add r7, sp, #8 8006e72: 6078 str r0, [r7, #4] 8006e74: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8006e76: 4b23 ldr r3, [pc, #140] @ (8006f04 ) 8006e78: 681b ldr r3, [r3, #0] 8006e7a: 68db ldr r3, [r3, #12] 8006e7c: 68db ldr r3, [r3, #12] 8006e7e: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8006e80: 697b ldr r3, [r7, #20] 8006e82: 3304 adds r3, #4 8006e84: 4618 mov r0, r3 8006e86: f7fe fa87 bl 8005398 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8006e8a: 697b ldr r3, [r7, #20] 8006e8c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8006e90: f003 0304 and.w r3, r3, #4 8006e94: 2b00 cmp r3, #0 8006e96: d023 beq.n 8006ee0 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 8006e98: 697b ldr r3, [r7, #20] 8006e9a: 699a ldr r2, [r3, #24] 8006e9c: 687b ldr r3, [r7, #4] 8006e9e: 18d1 adds r1, r2, r3 8006ea0: 687b ldr r3, [r7, #4] 8006ea2: 683a ldr r2, [r7, #0] 8006ea4: 6978 ldr r0, [r7, #20] 8006ea6: f000 f8d5 bl 8007054 8006eaa: 4603 mov r3, r0 8006eac: 2b00 cmp r3, #0 8006eae: d020 beq.n 8006ef2 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8006eb0: 2300 movs r3, #0 8006eb2: 9300 str r3, [sp, #0] 8006eb4: 2300 movs r3, #0 8006eb6: 687a ldr r2, [r7, #4] 8006eb8: 2100 movs r1, #0 8006eba: 6978 ldr r0, [r7, #20] 8006ebc: f7ff ff88 bl 8006dd0 8006ec0: 6138 str r0, [r7, #16] configASSERT( xResult ); 8006ec2: 693b ldr r3, [r7, #16] 8006ec4: 2b00 cmp r3, #0 8006ec6: d114 bne.n 8006ef2 __asm volatile 8006ec8: f04f 0350 mov.w r3, #80 @ 0x50 8006ecc: f383 8811 msr BASEPRI, r3 8006ed0: f3bf 8f6f isb sy 8006ed4: f3bf 8f4f dsb sy 8006ed8: 60fb str r3, [r7, #12] } 8006eda: bf00 nop 8006edc: bf00 nop 8006ede: e7fd b.n 8006edc mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8006ee0: 697b ldr r3, [r7, #20] 8006ee2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8006ee6: f023 0301 bic.w r3, r3, #1 8006eea: b2da uxtb r2, r3 8006eec: 697b ldr r3, [r7, #20] 8006eee: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8006ef2: 697b ldr r3, [r7, #20] 8006ef4: 6a1b ldr r3, [r3, #32] 8006ef6: 6978 ldr r0, [r7, #20] 8006ef8: 4798 blx r3 } 8006efa: bf00 nop 8006efc: 3718 adds r7, #24 8006efe: 46bd mov sp, r7 8006f00: bd80 pop {r7, pc} 8006f02: bf00 nop 8006f04: 200014d8 .word 0x200014d8 08006f08 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8006f08: b580 push {r7, lr} 8006f0a: b084 sub sp, #16 8006f0c: af00 add r7, sp, #0 8006f0e: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8006f10: f107 0308 add.w r3, r7, #8 8006f14: 4618 mov r0, r3 8006f16: f000 f859 bl 8006fcc 8006f1a: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 8006f1c: 68bb ldr r3, [r7, #8] 8006f1e: 4619 mov r1, r3 8006f20: 68f8 ldr r0, [r7, #12] 8006f22: f000 f805 bl 8006f30 /* Empty the command queue. */ prvProcessReceivedCommands(); 8006f26: f000 f8d7 bl 80070d8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8006f2a: bf00 nop 8006f2c: e7f0 b.n 8006f10 ... 08006f30 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8006f30: b580 push {r7, lr} 8006f32: b084 sub sp, #16 8006f34: af00 add r7, sp, #0 8006f36: 6078 str r0, [r7, #4] 8006f38: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 8006f3a: f7ff fa29 bl 8006390 /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8006f3e: f107 0308 add.w r3, r7, #8 8006f42: 4618 mov r0, r3 8006f44: f000 f866 bl 8007014 8006f48: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 8006f4a: 68bb ldr r3, [r7, #8] 8006f4c: 2b00 cmp r3, #0 8006f4e: d130 bne.n 8006fb2 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8006f50: 683b ldr r3, [r7, #0] 8006f52: 2b00 cmp r3, #0 8006f54: d10a bne.n 8006f6c 8006f56: 687a ldr r2, [r7, #4] 8006f58: 68fb ldr r3, [r7, #12] 8006f5a: 429a cmp r2, r3 8006f5c: d806 bhi.n 8006f6c { ( void ) xTaskResumeAll(); 8006f5e: f7ff fa25 bl 80063ac prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8006f62: 68f9 ldr r1, [r7, #12] 8006f64: 6878 ldr r0, [r7, #4] 8006f66: f7ff ff81 bl 8006e6c else { ( void ) xTaskResumeAll(); } } } 8006f6a: e024 b.n 8006fb6 if( xListWasEmpty != pdFALSE ) 8006f6c: 683b ldr r3, [r7, #0] 8006f6e: 2b00 cmp r3, #0 8006f70: d008 beq.n 8006f84 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8006f72: 4b13 ldr r3, [pc, #76] @ (8006fc0 ) 8006f74: 681b ldr r3, [r3, #0] 8006f76: 681b ldr r3, [r3, #0] 8006f78: 2b00 cmp r3, #0 8006f7a: d101 bne.n 8006f80 8006f7c: 2301 movs r3, #1 8006f7e: e000 b.n 8006f82 8006f80: 2300 movs r3, #0 8006f82: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 8006f84: 4b0f ldr r3, [pc, #60] @ (8006fc4 ) 8006f86: 6818 ldr r0, [r3, #0] 8006f88: 687a ldr r2, [r7, #4] 8006f8a: 68fb ldr r3, [r7, #12] 8006f8c: 1ad3 subs r3, r2, r3 8006f8e: 683a ldr r2, [r7, #0] 8006f90: 4619 mov r1, r3 8006f92: f7fe fef1 bl 8005d78 if( xTaskResumeAll() == pdFALSE ) 8006f96: f7ff fa09 bl 80063ac 8006f9a: 4603 mov r3, r0 8006f9c: 2b00 cmp r3, #0 8006f9e: d10a bne.n 8006fb6 portYIELD_WITHIN_API(); 8006fa0: 4b09 ldr r3, [pc, #36] @ (8006fc8 ) 8006fa2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006fa6: 601a str r2, [r3, #0] 8006fa8: f3bf 8f4f dsb sy 8006fac: f3bf 8f6f isb sy } 8006fb0: e001 b.n 8006fb6 ( void ) xTaskResumeAll(); 8006fb2: f7ff f9fb bl 80063ac } 8006fb6: bf00 nop 8006fb8: 3710 adds r7, #16 8006fba: 46bd mov sp, r7 8006fbc: bd80 pop {r7, pc} 8006fbe: bf00 nop 8006fc0: 200014dc .word 0x200014dc 8006fc4: 200014e0 .word 0x200014e0 8006fc8: e000ed04 .word 0xe000ed04 08006fcc : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 8006fcc: b480 push {r7} 8006fce: b085 sub sp, #20 8006fd0: af00 add r7, sp, #0 8006fd2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 8006fd4: 4b0e ldr r3, [pc, #56] @ (8007010 ) 8006fd6: 681b ldr r3, [r3, #0] 8006fd8: 681b ldr r3, [r3, #0] 8006fda: 2b00 cmp r3, #0 8006fdc: d101 bne.n 8006fe2 8006fde: 2201 movs r2, #1 8006fe0: e000 b.n 8006fe4 8006fe2: 2200 movs r2, #0 8006fe4: 687b ldr r3, [r7, #4] 8006fe6: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8006fe8: 687b ldr r3, [r7, #4] 8006fea: 681b ldr r3, [r3, #0] 8006fec: 2b00 cmp r3, #0 8006fee: d105 bne.n 8006ffc { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8006ff0: 4b07 ldr r3, [pc, #28] @ (8007010 ) 8006ff2: 681b ldr r3, [r3, #0] 8006ff4: 68db ldr r3, [r3, #12] 8006ff6: 681b ldr r3, [r3, #0] 8006ff8: 60fb str r3, [r7, #12] 8006ffa: e001 b.n 8007000 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8006ffc: 2300 movs r3, #0 8006ffe: 60fb str r3, [r7, #12] } return xNextExpireTime; 8007000: 68fb ldr r3, [r7, #12] } 8007002: 4618 mov r0, r3 8007004: 3714 adds r7, #20 8007006: 46bd mov sp, r7 8007008: f85d 7b04 ldr.w r7, [sp], #4 800700c: 4770 bx lr 800700e: bf00 nop 8007010: 200014d8 .word 0x200014d8 08007014 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 8007014: b580 push {r7, lr} 8007016: b084 sub sp, #16 8007018: af00 add r7, sp, #0 800701a: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 800701c: f7ff fa64 bl 80064e8 8007020: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8007022: 4b0b ldr r3, [pc, #44] @ (8007050 ) 8007024: 681b ldr r3, [r3, #0] 8007026: 68fa ldr r2, [r7, #12] 8007028: 429a cmp r2, r3 800702a: d205 bcs.n 8007038 { prvSwitchTimerLists(); 800702c: f000 f93a bl 80072a4 *pxTimerListsWereSwitched = pdTRUE; 8007030: 687b ldr r3, [r7, #4] 8007032: 2201 movs r2, #1 8007034: 601a str r2, [r3, #0] 8007036: e002 b.n 800703e } else { *pxTimerListsWereSwitched = pdFALSE; 8007038: 687b ldr r3, [r7, #4] 800703a: 2200 movs r2, #0 800703c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 800703e: 4a04 ldr r2, [pc, #16] @ (8007050 ) 8007040: 68fb ldr r3, [r7, #12] 8007042: 6013 str r3, [r2, #0] return xTimeNow; 8007044: 68fb ldr r3, [r7, #12] } 8007046: 4618 mov r0, r3 8007048: 3710 adds r7, #16 800704a: 46bd mov sp, r7 800704c: bd80 pop {r7, pc} 800704e: bf00 nop 8007050: 200014e8 .word 0x200014e8 08007054 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8007054: b580 push {r7, lr} 8007056: b086 sub sp, #24 8007058: af00 add r7, sp, #0 800705a: 60f8 str r0, [r7, #12] 800705c: 60b9 str r1, [r7, #8] 800705e: 607a str r2, [r7, #4] 8007060: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8007062: 2300 movs r3, #0 8007064: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8007066: 68fb ldr r3, [r7, #12] 8007068: 68ba ldr r2, [r7, #8] 800706a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 800706c: 68fb ldr r3, [r7, #12] 800706e: 68fa ldr r2, [r7, #12] 8007070: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8007072: 68ba ldr r2, [r7, #8] 8007074: 687b ldr r3, [r7, #4] 8007076: 429a cmp r2, r3 8007078: d812 bhi.n 80070a0 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800707a: 687a ldr r2, [r7, #4] 800707c: 683b ldr r3, [r7, #0] 800707e: 1ad2 subs r2, r2, r3 8007080: 68fb ldr r3, [r7, #12] 8007082: 699b ldr r3, [r3, #24] 8007084: 429a cmp r2, r3 8007086: d302 bcc.n 800708e { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8007088: 2301 movs r3, #1 800708a: 617b str r3, [r7, #20] 800708c: e01b b.n 80070c6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 800708e: 4b10 ldr r3, [pc, #64] @ (80070d0 ) 8007090: 681a ldr r2, [r3, #0] 8007092: 68fb ldr r3, [r7, #12] 8007094: 3304 adds r3, #4 8007096: 4619 mov r1, r3 8007098: 4610 mov r0, r2 800709a: f7fe f944 bl 8005326 800709e: e012 b.n 80070c6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 80070a0: 687a ldr r2, [r7, #4] 80070a2: 683b ldr r3, [r7, #0] 80070a4: 429a cmp r2, r3 80070a6: d206 bcs.n 80070b6 80070a8: 68ba ldr r2, [r7, #8] 80070aa: 683b ldr r3, [r7, #0] 80070ac: 429a cmp r2, r3 80070ae: d302 bcc.n 80070b6 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 80070b0: 2301 movs r3, #1 80070b2: 617b str r3, [r7, #20] 80070b4: e007 b.n 80070c6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80070b6: 4b07 ldr r3, [pc, #28] @ (80070d4 ) 80070b8: 681a ldr r2, [r3, #0] 80070ba: 68fb ldr r3, [r7, #12] 80070bc: 3304 adds r3, #4 80070be: 4619 mov r1, r3 80070c0: 4610 mov r0, r2 80070c2: f7fe f930 bl 8005326 } } return xProcessTimerNow; 80070c6: 697b ldr r3, [r7, #20] } 80070c8: 4618 mov r0, r3 80070ca: 3718 adds r7, #24 80070cc: 46bd mov sp, r7 80070ce: bd80 pop {r7, pc} 80070d0: 200014dc .word 0x200014dc 80070d4: 200014d8 .word 0x200014d8 080070d8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 80070d8: b580 push {r7, lr} 80070da: b08e sub sp, #56 @ 0x38 80070dc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 80070de: e0ce b.n 800727e { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 80070e0: 687b ldr r3, [r7, #4] 80070e2: 2b00 cmp r3, #0 80070e4: da19 bge.n 800711a { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 80070e6: 1d3b adds r3, r7, #4 80070e8: 3304 adds r3, #4 80070ea: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 80070ec: 6afb ldr r3, [r7, #44] @ 0x2c 80070ee: 2b00 cmp r3, #0 80070f0: d10b bne.n 800710a __asm volatile 80070f2: f04f 0350 mov.w r3, #80 @ 0x50 80070f6: f383 8811 msr BASEPRI, r3 80070fa: f3bf 8f6f isb sy 80070fe: f3bf 8f4f dsb sy 8007102: 61fb str r3, [r7, #28] } 8007104: bf00 nop 8007106: bf00 nop 8007108: e7fd b.n 8007106 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 800710a: 6afb ldr r3, [r7, #44] @ 0x2c 800710c: 681b ldr r3, [r3, #0] 800710e: 6afa ldr r2, [r7, #44] @ 0x2c 8007110: 6850 ldr r0, [r2, #4] 8007112: 6afa ldr r2, [r7, #44] @ 0x2c 8007114: 6892 ldr r2, [r2, #8] 8007116: 4611 mov r1, r2 8007118: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 800711a: 687b ldr r3, [r7, #4] 800711c: 2b00 cmp r3, #0 800711e: f2c0 80ae blt.w 800727e { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8007122: 68fb ldr r3, [r7, #12] 8007124: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8007126: 6abb ldr r3, [r7, #40] @ 0x28 8007128: 695b ldr r3, [r3, #20] 800712a: 2b00 cmp r3, #0 800712c: d004 beq.n 8007138 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 800712e: 6abb ldr r3, [r7, #40] @ 0x28 8007130: 3304 adds r3, #4 8007132: 4618 mov r0, r3 8007134: f7fe f930 bl 8005398 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8007138: 463b mov r3, r7 800713a: 4618 mov r0, r3 800713c: f7ff ff6a bl 8007014 8007140: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 8007142: 687b ldr r3, [r7, #4] 8007144: 2b09 cmp r3, #9 8007146: f200 8097 bhi.w 8007278 800714a: a201 add r2, pc, #4 @ (adr r2, 8007150 ) 800714c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007150: 08007179 .word 0x08007179 8007154: 08007179 .word 0x08007179 8007158: 08007179 .word 0x08007179 800715c: 080071ef .word 0x080071ef 8007160: 08007203 .word 0x08007203 8007164: 0800724f .word 0x0800724f 8007168: 08007179 .word 0x08007179 800716c: 08007179 .word 0x08007179 8007170: 080071ef .word 0x080071ef 8007174: 08007203 .word 0x08007203 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8007178: 6abb ldr r3, [r7, #40] @ 0x28 800717a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800717e: f043 0301 orr.w r3, r3, #1 8007182: b2da uxtb r2, r3 8007184: 6abb ldr r3, [r7, #40] @ 0x28 8007186: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 800718a: 68ba ldr r2, [r7, #8] 800718c: 6abb ldr r3, [r7, #40] @ 0x28 800718e: 699b ldr r3, [r3, #24] 8007190: 18d1 adds r1, r2, r3 8007192: 68bb ldr r3, [r7, #8] 8007194: 6a7a ldr r2, [r7, #36] @ 0x24 8007196: 6ab8 ldr r0, [r7, #40] @ 0x28 8007198: f7ff ff5c bl 8007054 800719c: 4603 mov r3, r0 800719e: 2b00 cmp r3, #0 80071a0: d06c beq.n 800727c { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80071a2: 6abb ldr r3, [r7, #40] @ 0x28 80071a4: 6a1b ldr r3, [r3, #32] 80071a6: 6ab8 ldr r0, [r7, #40] @ 0x28 80071a8: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80071aa: 6abb ldr r3, [r7, #40] @ 0x28 80071ac: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80071b0: f003 0304 and.w r3, r3, #4 80071b4: 2b00 cmp r3, #0 80071b6: d061 beq.n 800727c { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 80071b8: 68ba ldr r2, [r7, #8] 80071ba: 6abb ldr r3, [r7, #40] @ 0x28 80071bc: 699b ldr r3, [r3, #24] 80071be: 441a add r2, r3 80071c0: 2300 movs r3, #0 80071c2: 9300 str r3, [sp, #0] 80071c4: 2300 movs r3, #0 80071c6: 2100 movs r1, #0 80071c8: 6ab8 ldr r0, [r7, #40] @ 0x28 80071ca: f7ff fe01 bl 8006dd0 80071ce: 6238 str r0, [r7, #32] configASSERT( xResult ); 80071d0: 6a3b ldr r3, [r7, #32] 80071d2: 2b00 cmp r3, #0 80071d4: d152 bne.n 800727c __asm volatile 80071d6: f04f 0350 mov.w r3, #80 @ 0x50 80071da: f383 8811 msr BASEPRI, r3 80071de: f3bf 8f6f isb sy 80071e2: f3bf 8f4f dsb sy 80071e6: 61bb str r3, [r7, #24] } 80071e8: bf00 nop 80071ea: bf00 nop 80071ec: e7fd b.n 80071ea break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80071ee: 6abb ldr r3, [r7, #40] @ 0x28 80071f0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80071f4: f023 0301 bic.w r3, r3, #1 80071f8: b2da uxtb r2, r3 80071fa: 6abb ldr r3, [r7, #40] @ 0x28 80071fc: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8007200: e03d b.n 800727e case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8007202: 6abb ldr r3, [r7, #40] @ 0x28 8007204: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8007208: f043 0301 orr.w r3, r3, #1 800720c: b2da uxtb r2, r3 800720e: 6abb ldr r3, [r7, #40] @ 0x28 8007210: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 8007214: 68ba ldr r2, [r7, #8] 8007216: 6abb ldr r3, [r7, #40] @ 0x28 8007218: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 800721a: 6abb ldr r3, [r7, #40] @ 0x28 800721c: 699b ldr r3, [r3, #24] 800721e: 2b00 cmp r3, #0 8007220: d10b bne.n 800723a __asm volatile 8007222: f04f 0350 mov.w r3, #80 @ 0x50 8007226: f383 8811 msr BASEPRI, r3 800722a: f3bf 8f6f isb sy 800722e: f3bf 8f4f dsb sy 8007232: 617b str r3, [r7, #20] } 8007234: bf00 nop 8007236: bf00 nop 8007238: e7fd b.n 8007236 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 800723a: 6abb ldr r3, [r7, #40] @ 0x28 800723c: 699a ldr r2, [r3, #24] 800723e: 6a7b ldr r3, [r7, #36] @ 0x24 8007240: 18d1 adds r1, r2, r3 8007242: 6a7b ldr r3, [r7, #36] @ 0x24 8007244: 6a7a ldr r2, [r7, #36] @ 0x24 8007246: 6ab8 ldr r0, [r7, #40] @ 0x28 8007248: f7ff ff04 bl 8007054 break; 800724c: e017 b.n 800727e #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 800724e: 6abb ldr r3, [r7, #40] @ 0x28 8007250: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8007254: f003 0302 and.w r3, r3, #2 8007258: 2b00 cmp r3, #0 800725a: d103 bne.n 8007264 { vPortFree( pxTimer ); 800725c: 6ab8 ldr r0, [r7, #40] @ 0x28 800725e: f000 fbeb bl 8007a38 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 8007262: e00c b.n 800727e pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8007264: 6abb ldr r3, [r7, #40] @ 0x28 8007266: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800726a: f023 0301 bic.w r3, r3, #1 800726e: b2da uxtb r2, r3 8007270: 6abb ldr r3, [r7, #40] @ 0x28 8007272: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8007276: e002 b.n 800727e default : /* Don't expect to get here. */ break; 8007278: bf00 nop 800727a: e000 b.n 800727e break; 800727c: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 800727e: 4b08 ldr r3, [pc, #32] @ (80072a0 ) 8007280: 681b ldr r3, [r3, #0] 8007282: 1d39 adds r1, r7, #4 8007284: 2200 movs r2, #0 8007286: 4618 mov r0, r3 8007288: f7fe fb5a bl 8005940 800728c: 4603 mov r3, r0 800728e: 2b00 cmp r3, #0 8007290: f47f af26 bne.w 80070e0 } } } } 8007294: bf00 nop 8007296: bf00 nop 8007298: 3730 adds r7, #48 @ 0x30 800729a: 46bd mov sp, r7 800729c: bd80 pop {r7, pc} 800729e: bf00 nop 80072a0: 200014e0 .word 0x200014e0 080072a4 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 80072a4: b580 push {r7, lr} 80072a6: b088 sub sp, #32 80072a8: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 80072aa: e049 b.n 8007340 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 80072ac: 4b2e ldr r3, [pc, #184] @ (8007368 ) 80072ae: 681b ldr r3, [r3, #0] 80072b0: 68db ldr r3, [r3, #12] 80072b2: 681b ldr r3, [r3, #0] 80072b4: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80072b6: 4b2c ldr r3, [pc, #176] @ (8007368 ) 80072b8: 681b ldr r3, [r3, #0] 80072ba: 68db ldr r3, [r3, #12] 80072bc: 68db ldr r3, [r3, #12] 80072be: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 80072c0: 68fb ldr r3, [r7, #12] 80072c2: 3304 adds r3, #4 80072c4: 4618 mov r0, r3 80072c6: f7fe f867 bl 8005398 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80072ca: 68fb ldr r3, [r7, #12] 80072cc: 6a1b ldr r3, [r3, #32] 80072ce: 68f8 ldr r0, [r7, #12] 80072d0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80072d2: 68fb ldr r3, [r7, #12] 80072d4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80072d8: f003 0304 and.w r3, r3, #4 80072dc: 2b00 cmp r3, #0 80072de: d02f beq.n 8007340 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 80072e0: 68fb ldr r3, [r7, #12] 80072e2: 699b ldr r3, [r3, #24] 80072e4: 693a ldr r2, [r7, #16] 80072e6: 4413 add r3, r2 80072e8: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 80072ea: 68ba ldr r2, [r7, #8] 80072ec: 693b ldr r3, [r7, #16] 80072ee: 429a cmp r2, r3 80072f0: d90e bls.n 8007310 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 80072f2: 68fb ldr r3, [r7, #12] 80072f4: 68ba ldr r2, [r7, #8] 80072f6: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 80072f8: 68fb ldr r3, [r7, #12] 80072fa: 68fa ldr r2, [r7, #12] 80072fc: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80072fe: 4b1a ldr r3, [pc, #104] @ (8007368 ) 8007300: 681a ldr r2, [r3, #0] 8007302: 68fb ldr r3, [r7, #12] 8007304: 3304 adds r3, #4 8007306: 4619 mov r1, r3 8007308: 4610 mov r0, r2 800730a: f7fe f80c bl 8005326 800730e: e017 b.n 8007340 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8007310: 2300 movs r3, #0 8007312: 9300 str r3, [sp, #0] 8007314: 2300 movs r3, #0 8007316: 693a ldr r2, [r7, #16] 8007318: 2100 movs r1, #0 800731a: 68f8 ldr r0, [r7, #12] 800731c: f7ff fd58 bl 8006dd0 8007320: 6078 str r0, [r7, #4] configASSERT( xResult ); 8007322: 687b ldr r3, [r7, #4] 8007324: 2b00 cmp r3, #0 8007326: d10b bne.n 8007340 __asm volatile 8007328: f04f 0350 mov.w r3, #80 @ 0x50 800732c: f383 8811 msr BASEPRI, r3 8007330: f3bf 8f6f isb sy 8007334: f3bf 8f4f dsb sy 8007338: 603b str r3, [r7, #0] } 800733a: bf00 nop 800733c: bf00 nop 800733e: e7fd b.n 800733c while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8007340: 4b09 ldr r3, [pc, #36] @ (8007368 ) 8007342: 681b ldr r3, [r3, #0] 8007344: 681b ldr r3, [r3, #0] 8007346: 2b00 cmp r3, #0 8007348: d1b0 bne.n 80072ac { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 800734a: 4b07 ldr r3, [pc, #28] @ (8007368 ) 800734c: 681b ldr r3, [r3, #0] 800734e: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8007350: 4b06 ldr r3, [pc, #24] @ (800736c ) 8007352: 681b ldr r3, [r3, #0] 8007354: 4a04 ldr r2, [pc, #16] @ (8007368 ) 8007356: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8007358: 4a04 ldr r2, [pc, #16] @ (800736c ) 800735a: 697b ldr r3, [r7, #20] 800735c: 6013 str r3, [r2, #0] } 800735e: bf00 nop 8007360: 3718 adds r7, #24 8007362: 46bd mov sp, r7 8007364: bd80 pop {r7, pc} 8007366: bf00 nop 8007368: 200014d8 .word 0x200014d8 800736c: 200014dc .word 0x200014dc 08007370 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8007370: b580 push {r7, lr} 8007372: b082 sub sp, #8 8007374: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 8007376: f000 f96f bl 8007658 { if( xTimerQueue == NULL ) 800737a: 4b15 ldr r3, [pc, #84] @ (80073d0 ) 800737c: 681b ldr r3, [r3, #0] 800737e: 2b00 cmp r3, #0 8007380: d120 bne.n 80073c4 { vListInitialise( &xActiveTimerList1 ); 8007382: 4814 ldr r0, [pc, #80] @ (80073d4 ) 8007384: f7fd ff7e bl 8005284 vListInitialise( &xActiveTimerList2 ); 8007388: 4813 ldr r0, [pc, #76] @ (80073d8 ) 800738a: f7fd ff7b bl 8005284 pxCurrentTimerList = &xActiveTimerList1; 800738e: 4b13 ldr r3, [pc, #76] @ (80073dc ) 8007390: 4a10 ldr r2, [pc, #64] @ (80073d4 ) 8007392: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8007394: 4b12 ldr r3, [pc, #72] @ (80073e0 ) 8007396: 4a10 ldr r2, [pc, #64] @ (80073d8 ) 8007398: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800739a: 2300 movs r3, #0 800739c: 9300 str r3, [sp, #0] 800739e: 4b11 ldr r3, [pc, #68] @ (80073e4 ) 80073a0: 4a11 ldr r2, [pc, #68] @ (80073e8 ) 80073a2: 2110 movs r1, #16 80073a4: 200a movs r0, #10 80073a6: f7fe f88b bl 80054c0 80073aa: 4603 mov r3, r0 80073ac: 4a08 ldr r2, [pc, #32] @ (80073d0 ) 80073ae: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 80073b0: 4b07 ldr r3, [pc, #28] @ (80073d0 ) 80073b2: 681b ldr r3, [r3, #0] 80073b4: 2b00 cmp r3, #0 80073b6: d005 beq.n 80073c4 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 80073b8: 4b05 ldr r3, [pc, #20] @ (80073d0 ) 80073ba: 681b ldr r3, [r3, #0] 80073bc: 490b ldr r1, [pc, #44] @ (80073ec ) 80073be: 4618 mov r0, r3 80073c0: f7fe fcb0 bl 8005d24 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80073c4: f000 f97a bl 80076bc } 80073c8: bf00 nop 80073ca: 46bd mov sp, r7 80073cc: bd80 pop {r7, pc} 80073ce: bf00 nop 80073d0: 200014e0 .word 0x200014e0 80073d4: 200014b0 .word 0x200014b0 80073d8: 200014c4 .word 0x200014c4 80073dc: 200014d8 .word 0x200014d8 80073e0: 200014dc .word 0x200014dc 80073e4: 2000158c .word 0x2000158c 80073e8: 200014ec .word 0x200014ec 80073ec: 08007ea4 .word 0x08007ea4 080073f0 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 80073f0: b480 push {r7} 80073f2: b085 sub sp, #20 80073f4: af00 add r7, sp, #0 80073f6: 60f8 str r0, [r7, #12] 80073f8: 60b9 str r1, [r7, #8] 80073fa: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 80073fc: 68fb ldr r3, [r7, #12] 80073fe: 3b04 subs r3, #4 8007400: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 8007402: 68fb ldr r3, [r7, #12] 8007404: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8007408: 601a str r2, [r3, #0] pxTopOfStack--; 800740a: 68fb ldr r3, [r7, #12] 800740c: 3b04 subs r3, #4 800740e: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 8007410: 68bb ldr r3, [r7, #8] 8007412: f023 0201 bic.w r2, r3, #1 8007416: 68fb ldr r3, [r7, #12] 8007418: 601a str r2, [r3, #0] pxTopOfStack--; 800741a: 68fb ldr r3, [r7, #12] 800741c: 3b04 subs r3, #4 800741e: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 8007420: 4a0c ldr r2, [pc, #48] @ (8007454 ) 8007422: 68fb ldr r3, [r7, #12] 8007424: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8007426: 68fb ldr r3, [r7, #12] 8007428: 3b14 subs r3, #20 800742a: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 800742c: 687a ldr r2, [r7, #4] 800742e: 68fb ldr r3, [r7, #12] 8007430: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 8007432: 68fb ldr r3, [r7, #12] 8007434: 3b04 subs r3, #4 8007436: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8007438: 68fb ldr r3, [r7, #12] 800743a: f06f 0202 mvn.w r2, #2 800743e: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8007440: 68fb ldr r3, [r7, #12] 8007442: 3b20 subs r3, #32 8007444: 60fb str r3, [r7, #12] return pxTopOfStack; 8007446: 68fb ldr r3, [r7, #12] } 8007448: 4618 mov r0, r3 800744a: 3714 adds r7, #20 800744c: 46bd mov sp, r7 800744e: f85d 7b04 ldr.w r7, [sp], #4 8007452: 4770 bx lr 8007454: 08007459 .word 0x08007459 08007458 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8007458: b480 push {r7} 800745a: b085 sub sp, #20 800745c: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 800745e: 2300 movs r3, #0 8007460: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8007462: 4b13 ldr r3, [pc, #76] @ (80074b0 ) 8007464: 681b ldr r3, [r3, #0] 8007466: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800746a: d00b beq.n 8007484 __asm volatile 800746c: f04f 0350 mov.w r3, #80 @ 0x50 8007470: f383 8811 msr BASEPRI, r3 8007474: f3bf 8f6f isb sy 8007478: f3bf 8f4f dsb sy 800747c: 60fb str r3, [r7, #12] } 800747e: bf00 nop 8007480: bf00 nop 8007482: e7fd b.n 8007480 __asm volatile 8007484: f04f 0350 mov.w r3, #80 @ 0x50 8007488: f383 8811 msr BASEPRI, r3 800748c: f3bf 8f6f isb sy 8007490: f3bf 8f4f dsb sy 8007494: 60bb str r3, [r7, #8] } 8007496: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8007498: bf00 nop 800749a: 687b ldr r3, [r7, #4] 800749c: 2b00 cmp r3, #0 800749e: d0fc beq.n 800749a about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 80074a0: bf00 nop 80074a2: bf00 nop 80074a4: 3714 adds r7, #20 80074a6: 46bd mov sp, r7 80074a8: f85d 7b04 ldr.w r7, [sp], #4 80074ac: 4770 bx lr 80074ae: bf00 nop 80074b0: 2000000c .word 0x2000000c ... 080074c0 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 80074c0: 4b07 ldr r3, [pc, #28] @ (80074e0 ) 80074c2: 6819 ldr r1, [r3, #0] 80074c4: 6808 ldr r0, [r1, #0] 80074c6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80074ca: f380 8809 msr PSP, r0 80074ce: f3bf 8f6f isb sy 80074d2: f04f 0000 mov.w r0, #0 80074d6: f380 8811 msr BASEPRI, r0 80074da: 4770 bx lr 80074dc: f3af 8000 nop.w 080074e0 : 80074e0: 20000fb0 .word 0x20000fb0 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 80074e4: bf00 nop 80074e6: bf00 nop 080074e8 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 80074e8: 4808 ldr r0, [pc, #32] @ (800750c ) 80074ea: 6800 ldr r0, [r0, #0] 80074ec: 6800 ldr r0, [r0, #0] 80074ee: f380 8808 msr MSP, r0 80074f2: f04f 0000 mov.w r0, #0 80074f6: f380 8814 msr CONTROL, r0 80074fa: b662 cpsie i 80074fc: b661 cpsie f 80074fe: f3bf 8f4f dsb sy 8007502: f3bf 8f6f isb sy 8007506: df00 svc 0 8007508: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 800750a: bf00 nop 800750c: e000ed08 .word 0xe000ed08 08007510 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 8007510: b580 push {r7, lr} 8007512: b086 sub sp, #24 8007514: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 8007516: 4b47 ldr r3, [pc, #284] @ (8007634 ) 8007518: 681b ldr r3, [r3, #0] 800751a: 4a47 ldr r2, [pc, #284] @ (8007638 ) 800751c: 4293 cmp r3, r2 800751e: d10b bne.n 8007538 __asm volatile 8007520: f04f 0350 mov.w r3, #80 @ 0x50 8007524: f383 8811 msr BASEPRI, r3 8007528: f3bf 8f6f isb sy 800752c: f3bf 8f4f dsb sy 8007530: 60fb str r3, [r7, #12] } 8007532: bf00 nop 8007534: bf00 nop 8007536: e7fd b.n 8007534 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 8007538: 4b3e ldr r3, [pc, #248] @ (8007634 ) 800753a: 681b ldr r3, [r3, #0] 800753c: 4a3f ldr r2, [pc, #252] @ (800763c ) 800753e: 4293 cmp r3, r2 8007540: d10b bne.n 800755a __asm volatile 8007542: f04f 0350 mov.w r3, #80 @ 0x50 8007546: f383 8811 msr BASEPRI, r3 800754a: f3bf 8f6f isb sy 800754e: f3bf 8f4f dsb sy 8007552: 613b str r3, [r7, #16] } 8007554: bf00 nop 8007556: bf00 nop 8007558: e7fd b.n 8007556 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 800755a: 4b39 ldr r3, [pc, #228] @ (8007640 ) 800755c: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 800755e: 697b ldr r3, [r7, #20] 8007560: 781b ldrb r3, [r3, #0] 8007562: b2db uxtb r3, r3 8007564: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8007566: 697b ldr r3, [r7, #20] 8007568: 22ff movs r2, #255 @ 0xff 800756a: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 800756c: 697b ldr r3, [r7, #20] 800756e: 781b ldrb r3, [r3, #0] 8007570: b2db uxtb r3, r3 8007572: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8007574: 78fb ldrb r3, [r7, #3] 8007576: b2db uxtb r3, r3 8007578: f003 0350 and.w r3, r3, #80 @ 0x50 800757c: b2da uxtb r2, r3 800757e: 4b31 ldr r3, [pc, #196] @ (8007644 ) 8007580: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8007582: 4b31 ldr r3, [pc, #196] @ (8007648 ) 8007584: 2207 movs r2, #7 8007586: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8007588: e009 b.n 800759e { ulMaxPRIGROUPValue--; 800758a: 4b2f ldr r3, [pc, #188] @ (8007648 ) 800758c: 681b ldr r3, [r3, #0] 800758e: 3b01 subs r3, #1 8007590: 4a2d ldr r2, [pc, #180] @ (8007648 ) 8007592: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8007594: 78fb ldrb r3, [r7, #3] 8007596: b2db uxtb r3, r3 8007598: 005b lsls r3, r3, #1 800759a: b2db uxtb r3, r3 800759c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 800759e: 78fb ldrb r3, [r7, #3] 80075a0: b2db uxtb r3, r3 80075a2: f003 0380 and.w r3, r3, #128 @ 0x80 80075a6: 2b80 cmp r3, #128 @ 0x80 80075a8: d0ef beq.n 800758a #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 80075aa: 4b27 ldr r3, [pc, #156] @ (8007648 ) 80075ac: 681b ldr r3, [r3, #0] 80075ae: f1c3 0307 rsb r3, r3, #7 80075b2: 2b04 cmp r3, #4 80075b4: d00b beq.n 80075ce __asm volatile 80075b6: f04f 0350 mov.w r3, #80 @ 0x50 80075ba: f383 8811 msr BASEPRI, r3 80075be: f3bf 8f6f isb sy 80075c2: f3bf 8f4f dsb sy 80075c6: 60bb str r3, [r7, #8] } 80075c8: bf00 nop 80075ca: bf00 nop 80075cc: e7fd b.n 80075ca } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 80075ce: 4b1e ldr r3, [pc, #120] @ (8007648 ) 80075d0: 681b ldr r3, [r3, #0] 80075d2: 021b lsls r3, r3, #8 80075d4: 4a1c ldr r2, [pc, #112] @ (8007648 ) 80075d6: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 80075d8: 4b1b ldr r3, [pc, #108] @ (8007648 ) 80075da: 681b ldr r3, [r3, #0] 80075dc: f403 63e0 and.w r3, r3, #1792 @ 0x700 80075e0: 4a19 ldr r2, [pc, #100] @ (8007648 ) 80075e2: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 80075e4: 687b ldr r3, [r7, #4] 80075e6: b2da uxtb r2, r3 80075e8: 697b ldr r3, [r7, #20] 80075ea: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 80075ec: 4b17 ldr r3, [pc, #92] @ (800764c ) 80075ee: 681b ldr r3, [r3, #0] 80075f0: 4a16 ldr r2, [pc, #88] @ (800764c ) 80075f2: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80075f6: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 80075f8: 4b14 ldr r3, [pc, #80] @ (800764c ) 80075fa: 681b ldr r3, [r3, #0] 80075fc: 4a13 ldr r2, [pc, #76] @ (800764c ) 80075fe: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 8007602: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 8007604: f000 f8da bl 80077bc /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8007608: 4b11 ldr r3, [pc, #68] @ (8007650 ) 800760a: 2200 movs r2, #0 800760c: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 800760e: f000 f8f9 bl 8007804 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8007612: 4b10 ldr r3, [pc, #64] @ (8007654 ) 8007614: 681b ldr r3, [r3, #0] 8007616: 4a0f ldr r2, [pc, #60] @ (8007654 ) 8007618: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 800761c: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 800761e: f7ff ff63 bl 80074e8 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 8007622: f7ff f82b bl 800667c prvTaskExitError(); 8007626: f7ff ff17 bl 8007458 /* Should not get here! */ return 0; 800762a: 2300 movs r3, #0 } 800762c: 4618 mov r0, r3 800762e: 3718 adds r7, #24 8007630: 46bd mov sp, r7 8007632: bd80 pop {r7, pc} 8007634: e000ed00 .word 0xe000ed00 8007638: 410fc271 .word 0x410fc271 800763c: 410fc270 .word 0x410fc270 8007640: e000e400 .word 0xe000e400 8007644: 200015dc .word 0x200015dc 8007648: 200015e0 .word 0x200015e0 800764c: e000ed20 .word 0xe000ed20 8007650: 2000000c .word 0x2000000c 8007654: e000ef34 .word 0xe000ef34 08007658 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8007658: b480 push {r7} 800765a: b083 sub sp, #12 800765c: af00 add r7, sp, #0 __asm volatile 800765e: f04f 0350 mov.w r3, #80 @ 0x50 8007662: f383 8811 msr BASEPRI, r3 8007666: f3bf 8f6f isb sy 800766a: f3bf 8f4f dsb sy 800766e: 607b str r3, [r7, #4] } 8007670: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8007672: 4b10 ldr r3, [pc, #64] @ (80076b4 ) 8007674: 681b ldr r3, [r3, #0] 8007676: 3301 adds r3, #1 8007678: 4a0e ldr r2, [pc, #56] @ (80076b4 ) 800767a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 800767c: 4b0d ldr r3, [pc, #52] @ (80076b4 ) 800767e: 681b ldr r3, [r3, #0] 8007680: 2b01 cmp r3, #1 8007682: d110 bne.n 80076a6 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8007684: 4b0c ldr r3, [pc, #48] @ (80076b8 ) 8007686: 681b ldr r3, [r3, #0] 8007688: b2db uxtb r3, r3 800768a: 2b00 cmp r3, #0 800768c: d00b beq.n 80076a6 __asm volatile 800768e: f04f 0350 mov.w r3, #80 @ 0x50 8007692: f383 8811 msr BASEPRI, r3 8007696: f3bf 8f6f isb sy 800769a: f3bf 8f4f dsb sy 800769e: 603b str r3, [r7, #0] } 80076a0: bf00 nop 80076a2: bf00 nop 80076a4: e7fd b.n 80076a2 } } 80076a6: bf00 nop 80076a8: 370c adds r7, #12 80076aa: 46bd mov sp, r7 80076ac: f85d 7b04 ldr.w r7, [sp], #4 80076b0: 4770 bx lr 80076b2: bf00 nop 80076b4: 2000000c .word 0x2000000c 80076b8: e000ed04 .word 0xe000ed04 080076bc : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 80076bc: b480 push {r7} 80076be: b083 sub sp, #12 80076c0: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 80076c2: 4b12 ldr r3, [pc, #72] @ (800770c ) 80076c4: 681b ldr r3, [r3, #0] 80076c6: 2b00 cmp r3, #0 80076c8: d10b bne.n 80076e2 __asm volatile 80076ca: f04f 0350 mov.w r3, #80 @ 0x50 80076ce: f383 8811 msr BASEPRI, r3 80076d2: f3bf 8f6f isb sy 80076d6: f3bf 8f4f dsb sy 80076da: 607b str r3, [r7, #4] } 80076dc: bf00 nop 80076de: bf00 nop 80076e0: e7fd b.n 80076de uxCriticalNesting--; 80076e2: 4b0a ldr r3, [pc, #40] @ (800770c ) 80076e4: 681b ldr r3, [r3, #0] 80076e6: 3b01 subs r3, #1 80076e8: 4a08 ldr r2, [pc, #32] @ (800770c ) 80076ea: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 80076ec: 4b07 ldr r3, [pc, #28] @ (800770c ) 80076ee: 681b ldr r3, [r3, #0] 80076f0: 2b00 cmp r3, #0 80076f2: d105 bne.n 8007700 80076f4: 2300 movs r3, #0 80076f6: 603b str r3, [r7, #0] __asm volatile 80076f8: 683b ldr r3, [r7, #0] 80076fa: f383 8811 msr BASEPRI, r3 } 80076fe: bf00 nop { portENABLE_INTERRUPTS(); } } 8007700: bf00 nop 8007702: 370c adds r7, #12 8007704: 46bd mov sp, r7 8007706: f85d 7b04 ldr.w r7, [sp], #4 800770a: 4770 bx lr 800770c: 2000000c .word 0x2000000c 08007710 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8007710: f3ef 8009 mrs r0, PSP 8007714: f3bf 8f6f isb sy 8007718: 4b15 ldr r3, [pc, #84] @ (8007770 ) 800771a: 681a ldr r2, [r3, #0] 800771c: f01e 0f10 tst.w lr, #16 8007720: bf08 it eq 8007722: ed20 8a10 vstmdbeq r0!, {s16-s31} 8007726: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800772a: 6010 str r0, [r2, #0] 800772c: e92d 0009 stmdb sp!, {r0, r3} 8007730: f04f 0050 mov.w r0, #80 @ 0x50 8007734: f380 8811 msr BASEPRI, r0 8007738: f3bf 8f4f dsb sy 800773c: f3bf 8f6f isb sy 8007740: f7fe ff9c bl 800667c 8007744: f04f 0000 mov.w r0, #0 8007748: f380 8811 msr BASEPRI, r0 800774c: bc09 pop {r0, r3} 800774e: 6819 ldr r1, [r3, #0] 8007750: 6808 ldr r0, [r1, #0] 8007752: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007756: f01e 0f10 tst.w lr, #16 800775a: bf08 it eq 800775c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8007760: f380 8809 msr PSP, r0 8007764: f3bf 8f6f isb sy 8007768: 4770 bx lr 800776a: bf00 nop 800776c: f3af 8000 nop.w 08007770 : 8007770: 20000fb0 .word 0x20000fb0 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8007774: bf00 nop 8007776: bf00 nop 08007778 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8007778: b580 push {r7, lr} 800777a: b082 sub sp, #8 800777c: af00 add r7, sp, #0 __asm volatile 800777e: f04f 0350 mov.w r3, #80 @ 0x50 8007782: f383 8811 msr BASEPRI, r3 8007786: f3bf 8f6f isb sy 800778a: f3bf 8f4f dsb sy 800778e: 607b str r3, [r7, #4] } 8007790: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8007792: f7fe feb9 bl 8006508 8007796: 4603 mov r3, r0 8007798: 2b00 cmp r3, #0 800779a: d003 beq.n 80077a4 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 800779c: 4b06 ldr r3, [pc, #24] @ (80077b8 ) 800779e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80077a2: 601a str r2, [r3, #0] 80077a4: 2300 movs r3, #0 80077a6: 603b str r3, [r7, #0] __asm volatile 80077a8: 683b ldr r3, [r7, #0] 80077aa: f383 8811 msr BASEPRI, r3 } 80077ae: bf00 nop } } portENABLE_INTERRUPTS(); } 80077b0: bf00 nop 80077b2: 3708 adds r7, #8 80077b4: 46bd mov sp, r7 80077b6: bd80 pop {r7, pc} 80077b8: e000ed04 .word 0xe000ed04 080077bc : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 80077bc: b480 push {r7} 80077be: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 80077c0: 4b0b ldr r3, [pc, #44] @ (80077f0 ) 80077c2: 2200 movs r2, #0 80077c4: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 80077c6: 4b0b ldr r3, [pc, #44] @ (80077f4 ) 80077c8: 2200 movs r2, #0 80077ca: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 80077cc: 4b0a ldr r3, [pc, #40] @ (80077f8 ) 80077ce: 681b ldr r3, [r3, #0] 80077d0: 4a0a ldr r2, [pc, #40] @ (80077fc ) 80077d2: fba2 2303 umull r2, r3, r2, r3 80077d6: 099b lsrs r3, r3, #6 80077d8: 4a09 ldr r2, [pc, #36] @ (8007800 ) 80077da: 3b01 subs r3, #1 80077dc: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 80077de: 4b04 ldr r3, [pc, #16] @ (80077f0 ) 80077e0: 2207 movs r2, #7 80077e2: 601a str r2, [r3, #0] } 80077e4: bf00 nop 80077e6: 46bd mov sp, r7 80077e8: f85d 7b04 ldr.w r7, [sp], #4 80077ec: 4770 bx lr 80077ee: bf00 nop 80077f0: e000e010 .word 0xe000e010 80077f4: e000e018 .word 0xe000e018 80077f8: 20000000 .word 0x20000000 80077fc: 10624dd3 .word 0x10624dd3 8007800: e000e014 .word 0xe000e014 08007804 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8007804: f8df 000c ldr.w r0, [pc, #12] @ 8007814 8007808: 6801 ldr r1, [r0, #0] 800780a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800780e: 6001 str r1, [r0, #0] 8007810: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 8007812: bf00 nop 8007814: e000ed88 .word 0xe000ed88 08007818 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8007818: b480 push {r7} 800781a: b085 sub sp, #20 800781c: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 800781e: f3ef 8305 mrs r3, IPSR 8007822: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8007824: 68fb ldr r3, [r7, #12] 8007826: 2b0f cmp r3, #15 8007828: d915 bls.n 8007856 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 800782a: 4a18 ldr r2, [pc, #96] @ (800788c ) 800782c: 68fb ldr r3, [r7, #12] 800782e: 4413 add r3, r2 8007830: 781b ldrb r3, [r3, #0] 8007832: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8007834: 4b16 ldr r3, [pc, #88] @ (8007890 ) 8007836: 781b ldrb r3, [r3, #0] 8007838: 7afa ldrb r2, [r7, #11] 800783a: 429a cmp r2, r3 800783c: d20b bcs.n 8007856 __asm volatile 800783e: f04f 0350 mov.w r3, #80 @ 0x50 8007842: f383 8811 msr BASEPRI, r3 8007846: f3bf 8f6f isb sy 800784a: f3bf 8f4f dsb sy 800784e: 607b str r3, [r7, #4] } 8007850: bf00 nop 8007852: bf00 nop 8007854: e7fd b.n 8007852 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8007856: 4b0f ldr r3, [pc, #60] @ (8007894 ) 8007858: 681b ldr r3, [r3, #0] 800785a: f403 62e0 and.w r2, r3, #1792 @ 0x700 800785e: 4b0e ldr r3, [pc, #56] @ (8007898 ) 8007860: 681b ldr r3, [r3, #0] 8007862: 429a cmp r2, r3 8007864: d90b bls.n 800787e __asm volatile 8007866: f04f 0350 mov.w r3, #80 @ 0x50 800786a: f383 8811 msr BASEPRI, r3 800786e: f3bf 8f6f isb sy 8007872: f3bf 8f4f dsb sy 8007876: 603b str r3, [r7, #0] } 8007878: bf00 nop 800787a: bf00 nop 800787c: e7fd b.n 800787a } 800787e: bf00 nop 8007880: 3714 adds r7, #20 8007882: 46bd mov sp, r7 8007884: f85d 7b04 ldr.w r7, [sp], #4 8007888: 4770 bx lr 800788a: bf00 nop 800788c: e000e3f0 .word 0xe000e3f0 8007890: 200015dc .word 0x200015dc 8007894: e000ed0c .word 0xe000ed0c 8007898: 200015e0 .word 0x200015e0 0800789c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 800789c: b580 push {r7, lr} 800789e: b08a sub sp, #40 @ 0x28 80078a0: af00 add r7, sp, #0 80078a2: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 80078a4: 2300 movs r3, #0 80078a6: 61fb str r3, [r7, #28] vTaskSuspendAll(); 80078a8: f7fe fd72 bl 8006390 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 80078ac: 4b5c ldr r3, [pc, #368] @ (8007a20 ) 80078ae: 681b ldr r3, [r3, #0] 80078b0: 2b00 cmp r3, #0 80078b2: d101 bne.n 80078b8 { prvHeapInit(); 80078b4: f000 f924 bl 8007b00 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 80078b8: 4b5a ldr r3, [pc, #360] @ (8007a24 ) 80078ba: 681a ldr r2, [r3, #0] 80078bc: 687b ldr r3, [r7, #4] 80078be: 4013 ands r3, r2 80078c0: 2b00 cmp r3, #0 80078c2: f040 8095 bne.w 80079f0 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 80078c6: 687b ldr r3, [r7, #4] 80078c8: 2b00 cmp r3, #0 80078ca: d01e beq.n 800790a { xWantedSize += xHeapStructSize; 80078cc: 2208 movs r2, #8 80078ce: 687b ldr r3, [r7, #4] 80078d0: 4413 add r3, r2 80078d2: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 80078d4: 687b ldr r3, [r7, #4] 80078d6: f003 0307 and.w r3, r3, #7 80078da: 2b00 cmp r3, #0 80078dc: d015 beq.n 800790a { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 80078de: 687b ldr r3, [r7, #4] 80078e0: f023 0307 bic.w r3, r3, #7 80078e4: 3308 adds r3, #8 80078e6: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 80078e8: 687b ldr r3, [r7, #4] 80078ea: f003 0307 and.w r3, r3, #7 80078ee: 2b00 cmp r3, #0 80078f0: d00b beq.n 800790a __asm volatile 80078f2: f04f 0350 mov.w r3, #80 @ 0x50 80078f6: f383 8811 msr BASEPRI, r3 80078fa: f3bf 8f6f isb sy 80078fe: f3bf 8f4f dsb sy 8007902: 617b str r3, [r7, #20] } 8007904: bf00 nop 8007906: bf00 nop 8007908: e7fd b.n 8007906 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 800790a: 687b ldr r3, [r7, #4] 800790c: 2b00 cmp r3, #0 800790e: d06f beq.n 80079f0 8007910: 4b45 ldr r3, [pc, #276] @ (8007a28 ) 8007912: 681b ldr r3, [r3, #0] 8007914: 687a ldr r2, [r7, #4] 8007916: 429a cmp r2, r3 8007918: d86a bhi.n 80079f0 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 800791a: 4b44 ldr r3, [pc, #272] @ (8007a2c ) 800791c: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 800791e: 4b43 ldr r3, [pc, #268] @ (8007a2c ) 8007920: 681b ldr r3, [r3, #0] 8007922: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8007924: e004 b.n 8007930 { pxPreviousBlock = pxBlock; 8007926: 6a7b ldr r3, [r7, #36] @ 0x24 8007928: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 800792a: 6a7b ldr r3, [r7, #36] @ 0x24 800792c: 681b ldr r3, [r3, #0] 800792e: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8007930: 6a7b ldr r3, [r7, #36] @ 0x24 8007932: 685b ldr r3, [r3, #4] 8007934: 687a ldr r2, [r7, #4] 8007936: 429a cmp r2, r3 8007938: d903 bls.n 8007942 800793a: 6a7b ldr r3, [r7, #36] @ 0x24 800793c: 681b ldr r3, [r3, #0] 800793e: 2b00 cmp r3, #0 8007940: d1f1 bne.n 8007926 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 8007942: 4b37 ldr r3, [pc, #220] @ (8007a20 ) 8007944: 681b ldr r3, [r3, #0] 8007946: 6a7a ldr r2, [r7, #36] @ 0x24 8007948: 429a cmp r2, r3 800794a: d051 beq.n 80079f0 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 800794c: 6a3b ldr r3, [r7, #32] 800794e: 681b ldr r3, [r3, #0] 8007950: 2208 movs r2, #8 8007952: 4413 add r3, r2 8007954: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8007956: 6a7b ldr r3, [r7, #36] @ 0x24 8007958: 681a ldr r2, [r3, #0] 800795a: 6a3b ldr r3, [r7, #32] 800795c: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 800795e: 6a7b ldr r3, [r7, #36] @ 0x24 8007960: 685a ldr r2, [r3, #4] 8007962: 687b ldr r3, [r7, #4] 8007964: 1ad2 subs r2, r2, r3 8007966: 2308 movs r3, #8 8007968: 005b lsls r3, r3, #1 800796a: 429a cmp r2, r3 800796c: d920 bls.n 80079b0 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 800796e: 6a7a ldr r2, [r7, #36] @ 0x24 8007970: 687b ldr r3, [r7, #4] 8007972: 4413 add r3, r2 8007974: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8007976: 69bb ldr r3, [r7, #24] 8007978: f003 0307 and.w r3, r3, #7 800797c: 2b00 cmp r3, #0 800797e: d00b beq.n 8007998 __asm volatile 8007980: f04f 0350 mov.w r3, #80 @ 0x50 8007984: f383 8811 msr BASEPRI, r3 8007988: f3bf 8f6f isb sy 800798c: f3bf 8f4f dsb sy 8007990: 613b str r3, [r7, #16] } 8007992: bf00 nop 8007994: bf00 nop 8007996: e7fd b.n 8007994 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8007998: 6a7b ldr r3, [r7, #36] @ 0x24 800799a: 685a ldr r2, [r3, #4] 800799c: 687b ldr r3, [r7, #4] 800799e: 1ad2 subs r2, r2, r3 80079a0: 69bb ldr r3, [r7, #24] 80079a2: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 80079a4: 6a7b ldr r3, [r7, #36] @ 0x24 80079a6: 687a ldr r2, [r7, #4] 80079a8: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 80079aa: 69b8 ldr r0, [r7, #24] 80079ac: f000 f90a bl 8007bc4 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 80079b0: 4b1d ldr r3, [pc, #116] @ (8007a28 ) 80079b2: 681a ldr r2, [r3, #0] 80079b4: 6a7b ldr r3, [r7, #36] @ 0x24 80079b6: 685b ldr r3, [r3, #4] 80079b8: 1ad3 subs r3, r2, r3 80079ba: 4a1b ldr r2, [pc, #108] @ (8007a28 ) 80079bc: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 80079be: 4b1a ldr r3, [pc, #104] @ (8007a28 ) 80079c0: 681a ldr r2, [r3, #0] 80079c2: 4b1b ldr r3, [pc, #108] @ (8007a30 ) 80079c4: 681b ldr r3, [r3, #0] 80079c6: 429a cmp r2, r3 80079c8: d203 bcs.n 80079d2 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 80079ca: 4b17 ldr r3, [pc, #92] @ (8007a28 ) 80079cc: 681b ldr r3, [r3, #0] 80079ce: 4a18 ldr r2, [pc, #96] @ (8007a30 ) 80079d0: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 80079d2: 6a7b ldr r3, [r7, #36] @ 0x24 80079d4: 685a ldr r2, [r3, #4] 80079d6: 4b13 ldr r3, [pc, #76] @ (8007a24 ) 80079d8: 681b ldr r3, [r3, #0] 80079da: 431a orrs r2, r3 80079dc: 6a7b ldr r3, [r7, #36] @ 0x24 80079de: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 80079e0: 6a7b ldr r3, [r7, #36] @ 0x24 80079e2: 2200 movs r2, #0 80079e4: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 80079e6: 4b13 ldr r3, [pc, #76] @ (8007a34 ) 80079e8: 681b ldr r3, [r3, #0] 80079ea: 3301 adds r3, #1 80079ec: 4a11 ldr r2, [pc, #68] @ (8007a34 ) 80079ee: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 80079f0: f7fe fcdc bl 80063ac mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 80079f4: 69fb ldr r3, [r7, #28] 80079f6: f003 0307 and.w r3, r3, #7 80079fa: 2b00 cmp r3, #0 80079fc: d00b beq.n 8007a16 __asm volatile 80079fe: f04f 0350 mov.w r3, #80 @ 0x50 8007a02: f383 8811 msr BASEPRI, r3 8007a06: f3bf 8f6f isb sy 8007a0a: f3bf 8f4f dsb sy 8007a0e: 60fb str r3, [r7, #12] } 8007a10: bf00 nop 8007a12: bf00 nop 8007a14: e7fd b.n 8007a12 return pvReturn; 8007a16: 69fb ldr r3, [r7, #28] } 8007a18: 4618 mov r0, r3 8007a1a: 3728 adds r7, #40 @ 0x28 8007a1c: 46bd mov sp, r7 8007a1e: bd80 pop {r7, pc} 8007a20: 20008b1c .word 0x20008b1c 8007a24: 20008b30 .word 0x20008b30 8007a28: 20008b20 .word 0x20008b20 8007a2c: 20008b14 .word 0x20008b14 8007a30: 20008b24 .word 0x20008b24 8007a34: 20008b28 .word 0x20008b28 08007a38 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 8007a38: b580 push {r7, lr} 8007a3a: b086 sub sp, #24 8007a3c: af00 add r7, sp, #0 8007a3e: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 8007a40: 687b ldr r3, [r7, #4] 8007a42: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 8007a44: 687b ldr r3, [r7, #4] 8007a46: 2b00 cmp r3, #0 8007a48: d04f beq.n 8007aea { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 8007a4a: 2308 movs r3, #8 8007a4c: 425b negs r3, r3 8007a4e: 697a ldr r2, [r7, #20] 8007a50: 4413 add r3, r2 8007a52: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 8007a54: 697b ldr r3, [r7, #20] 8007a56: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 8007a58: 693b ldr r3, [r7, #16] 8007a5a: 685a ldr r2, [r3, #4] 8007a5c: 4b25 ldr r3, [pc, #148] @ (8007af4 ) 8007a5e: 681b ldr r3, [r3, #0] 8007a60: 4013 ands r3, r2 8007a62: 2b00 cmp r3, #0 8007a64: d10b bne.n 8007a7e __asm volatile 8007a66: f04f 0350 mov.w r3, #80 @ 0x50 8007a6a: f383 8811 msr BASEPRI, r3 8007a6e: f3bf 8f6f isb sy 8007a72: f3bf 8f4f dsb sy 8007a76: 60fb str r3, [r7, #12] } 8007a78: bf00 nop 8007a7a: bf00 nop 8007a7c: e7fd b.n 8007a7a configASSERT( pxLink->pxNextFreeBlock == NULL ); 8007a7e: 693b ldr r3, [r7, #16] 8007a80: 681b ldr r3, [r3, #0] 8007a82: 2b00 cmp r3, #0 8007a84: d00b beq.n 8007a9e __asm volatile 8007a86: f04f 0350 mov.w r3, #80 @ 0x50 8007a8a: f383 8811 msr BASEPRI, r3 8007a8e: f3bf 8f6f isb sy 8007a92: f3bf 8f4f dsb sy 8007a96: 60bb str r3, [r7, #8] } 8007a98: bf00 nop 8007a9a: bf00 nop 8007a9c: e7fd b.n 8007a9a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 8007a9e: 693b ldr r3, [r7, #16] 8007aa0: 685a ldr r2, [r3, #4] 8007aa2: 4b14 ldr r3, [pc, #80] @ (8007af4 ) 8007aa4: 681b ldr r3, [r3, #0] 8007aa6: 4013 ands r3, r2 8007aa8: 2b00 cmp r3, #0 8007aaa: d01e beq.n 8007aea { if( pxLink->pxNextFreeBlock == NULL ) 8007aac: 693b ldr r3, [r7, #16] 8007aae: 681b ldr r3, [r3, #0] 8007ab0: 2b00 cmp r3, #0 8007ab2: d11a bne.n 8007aea { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 8007ab4: 693b ldr r3, [r7, #16] 8007ab6: 685a ldr r2, [r3, #4] 8007ab8: 4b0e ldr r3, [pc, #56] @ (8007af4 ) 8007aba: 681b ldr r3, [r3, #0] 8007abc: 43db mvns r3, r3 8007abe: 401a ands r2, r3 8007ac0: 693b ldr r3, [r7, #16] 8007ac2: 605a str r2, [r3, #4] vTaskSuspendAll(); 8007ac4: f7fe fc64 bl 8006390 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 8007ac8: 693b ldr r3, [r7, #16] 8007aca: 685a ldr r2, [r3, #4] 8007acc: 4b0a ldr r3, [pc, #40] @ (8007af8 ) 8007ace: 681b ldr r3, [r3, #0] 8007ad0: 4413 add r3, r2 8007ad2: 4a09 ldr r2, [pc, #36] @ (8007af8 ) 8007ad4: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 8007ad6: 6938 ldr r0, [r7, #16] 8007ad8: f000 f874 bl 8007bc4 xNumberOfSuccessfulFrees++; 8007adc: 4b07 ldr r3, [pc, #28] @ (8007afc ) 8007ade: 681b ldr r3, [r3, #0] 8007ae0: 3301 adds r3, #1 8007ae2: 4a06 ldr r2, [pc, #24] @ (8007afc ) 8007ae4: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8007ae6: f7fe fc61 bl 80063ac else { mtCOVERAGE_TEST_MARKER(); } } } 8007aea: bf00 nop 8007aec: 3718 adds r7, #24 8007aee: 46bd mov sp, r7 8007af0: bd80 pop {r7, pc} 8007af2: bf00 nop 8007af4: 20008b30 .word 0x20008b30 8007af8: 20008b20 .word 0x20008b20 8007afc: 20008b2c .word 0x20008b2c 08007b00 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 8007b00: b480 push {r7} 8007b02: b085 sub sp, #20 8007b04: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 8007b06: f247 5330 movw r3, #30000 @ 0x7530 8007b0a: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 8007b0c: 4b27 ldr r3, [pc, #156] @ (8007bac ) 8007b0e: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 8007b10: 68fb ldr r3, [r7, #12] 8007b12: f003 0307 and.w r3, r3, #7 8007b16: 2b00 cmp r3, #0 8007b18: d00c beq.n 8007b34 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 8007b1a: 68fb ldr r3, [r7, #12] 8007b1c: 3307 adds r3, #7 8007b1e: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8007b20: 68fb ldr r3, [r7, #12] 8007b22: f023 0307 bic.w r3, r3, #7 8007b26: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 8007b28: 68ba ldr r2, [r7, #8] 8007b2a: 68fb ldr r3, [r7, #12] 8007b2c: 1ad3 subs r3, r2, r3 8007b2e: 4a1f ldr r2, [pc, #124] @ (8007bac ) 8007b30: 4413 add r3, r2 8007b32: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 8007b34: 68fb ldr r3, [r7, #12] 8007b36: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 8007b38: 4a1d ldr r2, [pc, #116] @ (8007bb0 ) 8007b3a: 687b ldr r3, [r7, #4] 8007b3c: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 8007b3e: 4b1c ldr r3, [pc, #112] @ (8007bb0 ) 8007b40: 2200 movs r2, #0 8007b42: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 8007b44: 687b ldr r3, [r7, #4] 8007b46: 68ba ldr r2, [r7, #8] 8007b48: 4413 add r3, r2 8007b4a: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 8007b4c: 2208 movs r2, #8 8007b4e: 68fb ldr r3, [r7, #12] 8007b50: 1a9b subs r3, r3, r2 8007b52: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8007b54: 68fb ldr r3, [r7, #12] 8007b56: f023 0307 bic.w r3, r3, #7 8007b5a: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 8007b5c: 68fb ldr r3, [r7, #12] 8007b5e: 4a15 ldr r2, [pc, #84] @ (8007bb4 ) 8007b60: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 8007b62: 4b14 ldr r3, [pc, #80] @ (8007bb4 ) 8007b64: 681b ldr r3, [r3, #0] 8007b66: 2200 movs r2, #0 8007b68: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 8007b6a: 4b12 ldr r3, [pc, #72] @ (8007bb4 ) 8007b6c: 681b ldr r3, [r3, #0] 8007b6e: 2200 movs r2, #0 8007b70: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8007b72: 687b ldr r3, [r7, #4] 8007b74: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 8007b76: 683b ldr r3, [r7, #0] 8007b78: 68fa ldr r2, [r7, #12] 8007b7a: 1ad2 subs r2, r2, r3 8007b7c: 683b ldr r3, [r7, #0] 8007b7e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 8007b80: 4b0c ldr r3, [pc, #48] @ (8007bb4 ) 8007b82: 681a ldr r2, [r3, #0] 8007b84: 683b ldr r3, [r7, #0] 8007b86: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8007b88: 683b ldr r3, [r7, #0] 8007b8a: 685b ldr r3, [r3, #4] 8007b8c: 4a0a ldr r2, [pc, #40] @ (8007bb8 ) 8007b8e: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8007b90: 683b ldr r3, [r7, #0] 8007b92: 685b ldr r3, [r3, #4] 8007b94: 4a09 ldr r2, [pc, #36] @ (8007bbc ) 8007b96: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 8007b98: 4b09 ldr r3, [pc, #36] @ (8007bc0 ) 8007b9a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 8007b9e: 601a str r2, [r3, #0] } 8007ba0: bf00 nop 8007ba2: 3714 adds r7, #20 8007ba4: 46bd mov sp, r7 8007ba6: f85d 7b04 ldr.w r7, [sp], #4 8007baa: 4770 bx lr 8007bac: 200015e4 .word 0x200015e4 8007bb0: 20008b14 .word 0x20008b14 8007bb4: 20008b1c .word 0x20008b1c 8007bb8: 20008b24 .word 0x20008b24 8007bbc: 20008b20 .word 0x20008b20 8007bc0: 20008b30 .word 0x20008b30 08007bc4 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 8007bc4: b480 push {r7} 8007bc6: b085 sub sp, #20 8007bc8: af00 add r7, sp, #0 8007bca: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 8007bcc: 4b28 ldr r3, [pc, #160] @ (8007c70 ) 8007bce: 60fb str r3, [r7, #12] 8007bd0: e002 b.n 8007bd8 8007bd2: 68fb ldr r3, [r7, #12] 8007bd4: 681b ldr r3, [r3, #0] 8007bd6: 60fb str r3, [r7, #12] 8007bd8: 68fb ldr r3, [r7, #12] 8007bda: 681b ldr r3, [r3, #0] 8007bdc: 687a ldr r2, [r7, #4] 8007bde: 429a cmp r2, r3 8007be0: d8f7 bhi.n 8007bd2 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8007be2: 68fb ldr r3, [r7, #12] 8007be4: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8007be6: 68fb ldr r3, [r7, #12] 8007be8: 685b ldr r3, [r3, #4] 8007bea: 68ba ldr r2, [r7, #8] 8007bec: 4413 add r3, r2 8007bee: 687a ldr r2, [r7, #4] 8007bf0: 429a cmp r2, r3 8007bf2: d108 bne.n 8007c06 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 8007bf4: 68fb ldr r3, [r7, #12] 8007bf6: 685a ldr r2, [r3, #4] 8007bf8: 687b ldr r3, [r7, #4] 8007bfa: 685b ldr r3, [r3, #4] 8007bfc: 441a add r2, r3 8007bfe: 68fb ldr r3, [r7, #12] 8007c00: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 8007c02: 68fb ldr r3, [r7, #12] 8007c04: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 8007c06: 687b ldr r3, [r7, #4] 8007c08: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 8007c0a: 687b ldr r3, [r7, #4] 8007c0c: 685b ldr r3, [r3, #4] 8007c0e: 68ba ldr r2, [r7, #8] 8007c10: 441a add r2, r3 8007c12: 68fb ldr r3, [r7, #12] 8007c14: 681b ldr r3, [r3, #0] 8007c16: 429a cmp r2, r3 8007c18: d118 bne.n 8007c4c { if( pxIterator->pxNextFreeBlock != pxEnd ) 8007c1a: 68fb ldr r3, [r7, #12] 8007c1c: 681a ldr r2, [r3, #0] 8007c1e: 4b15 ldr r3, [pc, #84] @ (8007c74 ) 8007c20: 681b ldr r3, [r3, #0] 8007c22: 429a cmp r2, r3 8007c24: d00d beq.n 8007c42 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 8007c26: 687b ldr r3, [r7, #4] 8007c28: 685a ldr r2, [r3, #4] 8007c2a: 68fb ldr r3, [r7, #12] 8007c2c: 681b ldr r3, [r3, #0] 8007c2e: 685b ldr r3, [r3, #4] 8007c30: 441a add r2, r3 8007c32: 687b ldr r3, [r7, #4] 8007c34: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 8007c36: 68fb ldr r3, [r7, #12] 8007c38: 681b ldr r3, [r3, #0] 8007c3a: 681a ldr r2, [r3, #0] 8007c3c: 687b ldr r3, [r7, #4] 8007c3e: 601a str r2, [r3, #0] 8007c40: e008 b.n 8007c54 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 8007c42: 4b0c ldr r3, [pc, #48] @ (8007c74 ) 8007c44: 681a ldr r2, [r3, #0] 8007c46: 687b ldr r3, [r7, #4] 8007c48: 601a str r2, [r3, #0] 8007c4a: e003 b.n 8007c54 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 8007c4c: 68fb ldr r3, [r7, #12] 8007c4e: 681a ldr r2, [r3, #0] 8007c50: 687b ldr r3, [r7, #4] 8007c52: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 8007c54: 68fa ldr r2, [r7, #12] 8007c56: 687b ldr r3, [r7, #4] 8007c58: 429a cmp r2, r3 8007c5a: d002 beq.n 8007c62 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 8007c5c: 68fb ldr r3, [r7, #12] 8007c5e: 687a ldr r2, [r7, #4] 8007c60: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8007c62: bf00 nop 8007c64: 3714 adds r7, #20 8007c66: 46bd mov sp, r7 8007c68: f85d 7b04 ldr.w r7, [sp], #4 8007c6c: 4770 bx lr 8007c6e: bf00 nop 8007c70: 20008b14 .word 0x20008b14 8007c74: 20008b1c .word 0x20008b1c 08007c78 : 8007c78: 4402 add r2, r0 8007c7a: 4603 mov r3, r0 8007c7c: 4293 cmp r3, r2 8007c7e: d100 bne.n 8007c82 8007c80: 4770 bx lr 8007c82: f803 1b01 strb.w r1, [r3], #1 8007c86: e7f9 b.n 8007c7c 08007c88 <_reclaim_reent>: 8007c88: 4b2d ldr r3, [pc, #180] @ (8007d40 <_reclaim_reent+0xb8>) 8007c8a: 681b ldr r3, [r3, #0] 8007c8c: 4283 cmp r3, r0 8007c8e: b570 push {r4, r5, r6, lr} 8007c90: 4604 mov r4, r0 8007c92: d053 beq.n 8007d3c <_reclaim_reent+0xb4> 8007c94: 69c3 ldr r3, [r0, #28] 8007c96: b31b cbz r3, 8007ce0 <_reclaim_reent+0x58> 8007c98: 68db ldr r3, [r3, #12] 8007c9a: b163 cbz r3, 8007cb6 <_reclaim_reent+0x2e> 8007c9c: 2500 movs r5, #0 8007c9e: 69e3 ldr r3, [r4, #28] 8007ca0: 68db ldr r3, [r3, #12] 8007ca2: 5959 ldr r1, [r3, r5] 8007ca4: b9b1 cbnz r1, 8007cd4 <_reclaim_reent+0x4c> 8007ca6: 3504 adds r5, #4 8007ca8: 2d80 cmp r5, #128 @ 0x80 8007caa: d1f8 bne.n 8007c9e <_reclaim_reent+0x16> 8007cac: 69e3 ldr r3, [r4, #28] 8007cae: 4620 mov r0, r4 8007cb0: 68d9 ldr r1, [r3, #12] 8007cb2: f000 f87b bl 8007dac <_free_r> 8007cb6: 69e3 ldr r3, [r4, #28] 8007cb8: 6819 ldr r1, [r3, #0] 8007cba: b111 cbz r1, 8007cc2 <_reclaim_reent+0x3a> 8007cbc: 4620 mov r0, r4 8007cbe: f000 f875 bl 8007dac <_free_r> 8007cc2: 69e3 ldr r3, [r4, #28] 8007cc4: 689d ldr r5, [r3, #8] 8007cc6: b15d cbz r5, 8007ce0 <_reclaim_reent+0x58> 8007cc8: 4629 mov r1, r5 8007cca: 4620 mov r0, r4 8007ccc: 682d ldr r5, [r5, #0] 8007cce: f000 f86d bl 8007dac <_free_r> 8007cd2: e7f8 b.n 8007cc6 <_reclaim_reent+0x3e> 8007cd4: 680e ldr r6, [r1, #0] 8007cd6: 4620 mov r0, r4 8007cd8: f000 f868 bl 8007dac <_free_r> 8007cdc: 4631 mov r1, r6 8007cde: e7e1 b.n 8007ca4 <_reclaim_reent+0x1c> 8007ce0: 6961 ldr r1, [r4, #20] 8007ce2: b111 cbz r1, 8007cea <_reclaim_reent+0x62> 8007ce4: 4620 mov r0, r4 8007ce6: f000 f861 bl 8007dac <_free_r> 8007cea: 69e1 ldr r1, [r4, #28] 8007cec: b111 cbz r1, 8007cf4 <_reclaim_reent+0x6c> 8007cee: 4620 mov r0, r4 8007cf0: f000 f85c bl 8007dac <_free_r> 8007cf4: 6b21 ldr r1, [r4, #48] @ 0x30 8007cf6: b111 cbz r1, 8007cfe <_reclaim_reent+0x76> 8007cf8: 4620 mov r0, r4 8007cfa: f000 f857 bl 8007dac <_free_r> 8007cfe: 6b61 ldr r1, [r4, #52] @ 0x34 8007d00: b111 cbz r1, 8007d08 <_reclaim_reent+0x80> 8007d02: 4620 mov r0, r4 8007d04: f000 f852 bl 8007dac <_free_r> 8007d08: 6ba1 ldr r1, [r4, #56] @ 0x38 8007d0a: b111 cbz r1, 8007d12 <_reclaim_reent+0x8a> 8007d0c: 4620 mov r0, r4 8007d0e: f000 f84d bl 8007dac <_free_r> 8007d12: 6ca1 ldr r1, [r4, #72] @ 0x48 8007d14: b111 cbz r1, 8007d1c <_reclaim_reent+0x94> 8007d16: 4620 mov r0, r4 8007d18: f000 f848 bl 8007dac <_free_r> 8007d1c: 6c61 ldr r1, [r4, #68] @ 0x44 8007d1e: b111 cbz r1, 8007d26 <_reclaim_reent+0x9e> 8007d20: 4620 mov r0, r4 8007d22: f000 f843 bl 8007dac <_free_r> 8007d26: 6ae1 ldr r1, [r4, #44] @ 0x2c 8007d28: b111 cbz r1, 8007d30 <_reclaim_reent+0xa8> 8007d2a: 4620 mov r0, r4 8007d2c: f000 f83e bl 8007dac <_free_r> 8007d30: 6a23 ldr r3, [r4, #32] 8007d32: b11b cbz r3, 8007d3c <_reclaim_reent+0xb4> 8007d34: 4620 mov r0, r4 8007d36: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 8007d3a: 4718 bx r3 8007d3c: bd70 pop {r4, r5, r6, pc} 8007d3e: bf00 nop 8007d40: 20000010 .word 0x20000010 08007d44 <__libc_init_array>: 8007d44: b570 push {r4, r5, r6, lr} 8007d46: 4d0d ldr r5, [pc, #52] @ (8007d7c <__libc_init_array+0x38>) 8007d48: 4c0d ldr r4, [pc, #52] @ (8007d80 <__libc_init_array+0x3c>) 8007d4a: 1b64 subs r4, r4, r5 8007d4c: 10a4 asrs r4, r4, #2 8007d4e: 2600 movs r6, #0 8007d50: 42a6 cmp r6, r4 8007d52: d109 bne.n 8007d68 <__libc_init_array+0x24> 8007d54: 4d0b ldr r5, [pc, #44] @ (8007d84 <__libc_init_array+0x40>) 8007d56: 4c0c ldr r4, [pc, #48] @ (8007d88 <__libc_init_array+0x44>) 8007d58: f000 f87e bl 8007e58 <_init> 8007d5c: 1b64 subs r4, r4, r5 8007d5e: 10a4 asrs r4, r4, #2 8007d60: 2600 movs r6, #0 8007d62: 42a6 cmp r6, r4 8007d64: d105 bne.n 8007d72 <__libc_init_array+0x2e> 8007d66: bd70 pop {r4, r5, r6, pc} 8007d68: f855 3b04 ldr.w r3, [r5], #4 8007d6c: 4798 blx r3 8007d6e: 3601 adds r6, #1 8007d70: e7ee b.n 8007d50 <__libc_init_array+0xc> 8007d72: f855 3b04 ldr.w r3, [r5], #4 8007d76: 4798 blx r3 8007d78: 3601 adds r6, #1 8007d7a: e7f2 b.n 8007d62 <__libc_init_array+0x1e> 8007d7c: 08007efc .word 0x08007efc 8007d80: 08007efc .word 0x08007efc 8007d84: 08007efc .word 0x08007efc 8007d88: 08007f00 .word 0x08007f00 08007d8c <__retarget_lock_acquire_recursive>: 8007d8c: 4770 bx lr 08007d8e <__retarget_lock_release_recursive>: 8007d8e: 4770 bx lr 08007d90 : 8007d90: 440a add r2, r1 8007d92: 4291 cmp r1, r2 8007d94: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8007d98: d100 bne.n 8007d9c 8007d9a: 4770 bx lr 8007d9c: b510 push {r4, lr} 8007d9e: f811 4b01 ldrb.w r4, [r1], #1 8007da2: f803 4f01 strb.w r4, [r3, #1]! 8007da6: 4291 cmp r1, r2 8007da8: d1f9 bne.n 8007d9e 8007daa: bd10 pop {r4, pc} 08007dac <_free_r>: 8007dac: b538 push {r3, r4, r5, lr} 8007dae: 4605 mov r5, r0 8007db0: 2900 cmp r1, #0 8007db2: d041 beq.n 8007e38 <_free_r+0x8c> 8007db4: f851 3c04 ldr.w r3, [r1, #-4] 8007db8: 1f0c subs r4, r1, #4 8007dba: 2b00 cmp r3, #0 8007dbc: bfb8 it lt 8007dbe: 18e4 addlt r4, r4, r3 8007dc0: f000 f83e bl 8007e40 <__malloc_lock> 8007dc4: 4a1d ldr r2, [pc, #116] @ (8007e3c <_free_r+0x90>) 8007dc6: 6813 ldr r3, [r2, #0] 8007dc8: b933 cbnz r3, 8007dd8 <_free_r+0x2c> 8007dca: 6063 str r3, [r4, #4] 8007dcc: 6014 str r4, [r2, #0] 8007dce: 4628 mov r0, r5 8007dd0: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8007dd4: f000 b83a b.w 8007e4c <__malloc_unlock> 8007dd8: 42a3 cmp r3, r4 8007dda: d908 bls.n 8007dee <_free_r+0x42> 8007ddc: 6820 ldr r0, [r4, #0] 8007dde: 1821 adds r1, r4, r0 8007de0: 428b cmp r3, r1 8007de2: bf01 itttt eq 8007de4: 6819 ldreq r1, [r3, #0] 8007de6: 685b ldreq r3, [r3, #4] 8007de8: 1809 addeq r1, r1, r0 8007dea: 6021 streq r1, [r4, #0] 8007dec: e7ed b.n 8007dca <_free_r+0x1e> 8007dee: 461a mov r2, r3 8007df0: 685b ldr r3, [r3, #4] 8007df2: b10b cbz r3, 8007df8 <_free_r+0x4c> 8007df4: 42a3 cmp r3, r4 8007df6: d9fa bls.n 8007dee <_free_r+0x42> 8007df8: 6811 ldr r1, [r2, #0] 8007dfa: 1850 adds r0, r2, r1 8007dfc: 42a0 cmp r0, r4 8007dfe: d10b bne.n 8007e18 <_free_r+0x6c> 8007e00: 6820 ldr r0, [r4, #0] 8007e02: 4401 add r1, r0 8007e04: 1850 adds r0, r2, r1 8007e06: 4283 cmp r3, r0 8007e08: 6011 str r1, [r2, #0] 8007e0a: d1e0 bne.n 8007dce <_free_r+0x22> 8007e0c: 6818 ldr r0, [r3, #0] 8007e0e: 685b ldr r3, [r3, #4] 8007e10: 6053 str r3, [r2, #4] 8007e12: 4408 add r0, r1 8007e14: 6010 str r0, [r2, #0] 8007e16: e7da b.n 8007dce <_free_r+0x22> 8007e18: d902 bls.n 8007e20 <_free_r+0x74> 8007e1a: 230c movs r3, #12 8007e1c: 602b str r3, [r5, #0] 8007e1e: e7d6 b.n 8007dce <_free_r+0x22> 8007e20: 6820 ldr r0, [r4, #0] 8007e22: 1821 adds r1, r4, r0 8007e24: 428b cmp r3, r1 8007e26: bf04 itt eq 8007e28: 6819 ldreq r1, [r3, #0] 8007e2a: 685b ldreq r3, [r3, #4] 8007e2c: 6063 str r3, [r4, #4] 8007e2e: bf04 itt eq 8007e30: 1809 addeq r1, r1, r0 8007e32: 6021 streq r1, [r4, #0] 8007e34: 6054 str r4, [r2, #4] 8007e36: e7ca b.n 8007dce <_free_r+0x22> 8007e38: bd38 pop {r3, r4, r5, pc} 8007e3a: bf00 nop 8007e3c: 20008c70 .word 0x20008c70 08007e40 <__malloc_lock>: 8007e40: 4801 ldr r0, [pc, #4] @ (8007e48 <__malloc_lock+0x8>) 8007e42: f7ff bfa3 b.w 8007d8c <__retarget_lock_acquire_recursive> 8007e46: bf00 nop 8007e48: 20008c6c .word 0x20008c6c 08007e4c <__malloc_unlock>: 8007e4c: 4801 ldr r0, [pc, #4] @ (8007e54 <__malloc_unlock+0x8>) 8007e4e: f7ff bf9e b.w 8007d8e <__retarget_lock_release_recursive> 8007e52: bf00 nop 8007e54: 20008c6c .word 0x20008c6c 08007e58 <_init>: 8007e58: b5f8 push {r3, r4, r5, r6, r7, lr} 8007e5a: bf00 nop 8007e5c: bcf8 pop {r3, r4, r5, r6, r7} 8007e5e: bc08 pop {r3} 8007e60: 469e mov lr, r3 8007e62: 4770 bx lr 08007e64 <_fini>: 8007e64: b5f8 push {r3, r4, r5, r6, r7, lr} 8007e66: bf00 nop 8007e68: bcf8 pop {r3, r4, r5, r6, r7} 8007e6a: bc08 pop {r3} 8007e6c: 469e mov lr, r3 8007e6e: 4770 bx lr