From 580d746aeb24c77758fc2dc93d11db706a2ff9d6 Mon Sep 17 00:00:00 2001 From: Jose Date: Thu, 9 Oct 2025 19:35:22 +0200 Subject: [PATCH] Add: P1 SETR2 --- P1_SETR2/.cproject | 175 + P1_SETR2/.mxproject | 25 + P1_SETR2/.project | 32 + .../com.st.stm32cube.ide.mcu.sfrview.prefs | 2 + P1_SETR2/.settings/language.settings.xml | 25 + .../org.eclipse.core.resources.prefs | 2 + P1_SETR2/.settings/stm32cubeide.project.prefs | 5 + P1_SETR2/Core/Inc/joystick_driver.h | 15 + P1_SETR2/Core/Inc/led_driver.h | 17 + P1_SETR2/Core/Inc/main.h | 234 + P1_SETR2/Core/Inc/stm32l4xx_hal_conf.h | 482 + P1_SETR2/Core/Inc/stm32l4xx_it.h | 68 + P1_SETR2/Core/Src/joystick.c | 27 + P1_SETR2/Core/Src/led_driver.c | 56 + P1_SETR2/Core/Src/main.c | 736 + P1_SETR2/Core/Src/stm32l4xx_hal_msp.c | 627 + P1_SETR2/Core/Src/stm32l4xx_it.c | 238 + P1_SETR2/Core/Src/syscalls.c | 176 + P1_SETR2/Core/Src/sysmem.c | 79 + P1_SETR2/Core/Src/system_stm32l4xx.c | 332 + P1_SETR2/Core/Startup/startup_stm32l475vgtx.s | 508 + P1_SETR2/Debug/Core/Src/joystick.cyclo | 1 + P1_SETR2/Debug/Core/Src/joystick.d | 72 + P1_SETR2/Debug/Core/Src/joystick.o | Bin 0 -> 1281164 bytes P1_SETR2/Debug/Core/Src/joystick.su | 1 + P1_SETR2/Debug/Core/Src/led_driver.cyclo | 3 + P1_SETR2/Debug/Core/Src/led_driver.d | 72 + P1_SETR2/Debug/Core/Src/led_driver.o | Bin 0 -> 1281808 bytes P1_SETR2/Debug/Core/Src/led_driver.su | 3 + P1_SETR2/Debug/Core/Src/main.cyclo | 14 + P1_SETR2/Debug/Core/Src/main.d | 75 + P1_SETR2/Debug/Core/Src/main.o | Bin 0 -> 1317300 bytes P1_SETR2/Debug/Core/Src/main.su | 14 + .../Debug/Core/Src/stm32l4xx_hal_msp.cyclo | 13 + P1_SETR2/Debug/Core/Src/stm32l4xx_hal_msp.d | 72 + P1_SETR2/Debug/Core/Src/stm32l4xx_hal_msp.o | Bin 0 -> 1312316 bytes P1_SETR2/Debug/Core/Src/stm32l4xx_hal_msp.su | 13 + P1_SETR2/Debug/Core/Src/stm32l4xx_it.cyclo | 11 + P1_SETR2/Debug/Core/Src/stm32l4xx_it.d | 74 + P1_SETR2/Debug/Core/Src/stm32l4xx_it.o | Bin 0 -> 1290860 bytes P1_SETR2/Debug/Core/Src/stm32l4xx_it.su | 11 + P1_SETR2/Debug/Core/Src/subdir.mk | 48 + P1_SETR2/Debug/Core/Src/syscalls.cyclo | 18 + P1_SETR2/Debug/Core/Src/syscalls.d | 1 + P1_SETR2/Debug/Core/Src/syscalls.o | Bin 0 -> 83464 bytes P1_SETR2/Debug/Core/Src/syscalls.su | 18 + P1_SETR2/Debug/Core/Src/sysmem.cyclo | 1 + P1_SETR2/Debug/Core/Src/sysmem.d | 1 + P1_SETR2/Debug/Core/Src/sysmem.o | Bin 0 -> 55916 bytes P1_SETR2/Debug/Core/Src/sysmem.su | 1 + .../Debug/Core/Src/system_stm32l4xx.cyclo | 2 + P1_SETR2/Debug/Core/Src/system_stm32l4xx.d | 71 + P1_SETR2/Debug/Core/Src/system_stm32l4xx.o | Bin 0 -> 1283924 bytes P1_SETR2/Debug/Core/Src/system_stm32l4xx.su | 2 + .../Core/Startup/startup_stm32l475vgtx.d | 2 + .../Core/Startup/startup_stm32l475vgtx.o | Bin 0 -> 7244 bytes P1_SETR2/Debug/Core/Startup/subdir.mk | 27 + .../Src/stm32l4xx_hal.cyclo | 35 + .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d | 72 + .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o | Bin 0 -> 1300176 bytes .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.su | 35 + .../Src/stm32l4xx_hal_cortex.cyclo | 34 + .../Src/stm32l4xx_hal_cortex.d | 72 + .../Src/stm32l4xx_hal_cortex.o | Bin 0 -> 1300324 bytes .../Src/stm32l4xx_hal_cortex.su | 34 + .../Src/stm32l4xx_hal_dfsdm.cyclo | 70 + .../Src/stm32l4xx_hal_dfsdm.d | 72 + .../Src/stm32l4xx_hal_dfsdm.o | Bin 0 -> 1328004 bytes .../Src/stm32l4xx_hal_dfsdm.su | 70 + .../Src/stm32l4xx_hal_dma.cyclo | 13 + .../Src/stm32l4xx_hal_dma.d | 72 + .../Src/stm32l4xx_hal_dma.o | Bin 0 -> 1290884 bytes .../Src/stm32l4xx_hal_dma.su | 13 + .../Src/stm32l4xx_hal_dma_ex.cyclo | 0 .../Src/stm32l4xx_hal_dma_ex.d | 72 + .../Src/stm32l4xx_hal_dma_ex.o | Bin 0 -> 1279088 bytes .../Src/stm32l4xx_hal_dma_ex.su | 0 .../Src/stm32l4xx_hal_exti.cyclo | 9 + .../Src/stm32l4xx_hal_exti.d | 72 + .../Src/stm32l4xx_hal_exti.o | Bin 0 -> 1287400 bytes .../Src/stm32l4xx_hal_exti.su | 9 + .../Src/stm32l4xx_hal_flash.cyclo | 14 + .../Src/stm32l4xx_hal_flash.d | 72 + .../Src/stm32l4xx_hal_flash.o | Bin 0 -> 1290432 bytes .../Src/stm32l4xx_hal_flash.su | 14 + .../Src/stm32l4xx_hal_flash_ex.cyclo | 15 + .../Src/stm32l4xx_hal_flash_ex.d | 72 + .../Src/stm32l4xx_hal_flash_ex.o | Bin 0 -> 1293148 bytes .../Src/stm32l4xx_hal_flash_ex.su | 15 + .../Src/stm32l4xx_hal_flash_ramfunc.cyclo | 2 + .../Src/stm32l4xx_hal_flash_ramfunc.d | 72 + .../Src/stm32l4xx_hal_flash_ramfunc.o | Bin 0 -> 1280988 bytes .../Src/stm32l4xx_hal_flash_ramfunc.su | 2 + .../Src/stm32l4xx_hal_gpio.cyclo | 8 + .../Src/stm32l4xx_hal_gpio.d | 72 + .../Src/stm32l4xx_hal_gpio.o | Bin 0 -> 1288160 bytes .../Src/stm32l4xx_hal_gpio.su | 8 + .../Src/stm32l4xx_hal_i2c.cyclo | 81 + .../Src/stm32l4xx_hal_i2c.d | 72 + .../Src/stm32l4xx_hal_i2c.o | Bin 0 -> 1357628 bytes .../Src/stm32l4xx_hal_i2c.su | 81 + .../Src/stm32l4xx_hal_i2c_ex.cyclo | 6 + .../Src/stm32l4xx_hal_i2c_ex.d | 72 + .../Src/stm32l4xx_hal_i2c_ex.o | Bin 0 -> 1287872 bytes .../Src/stm32l4xx_hal_i2c_ex.su | 6 + .../Src/stm32l4xx_hal_pcd.cyclo | 36 + .../Src/stm32l4xx_hal_pcd.d | 72 + .../Src/stm32l4xx_hal_pcd.o | Bin 0 -> 1310776 bytes .../Src/stm32l4xx_hal_pcd.su | 36 + .../Src/stm32l4xx_hal_pcd_ex.cyclo | 9 + .../Src/stm32l4xx_hal_pcd_ex.d | 72 + .../Src/stm32l4xx_hal_pcd_ex.o | Bin 0 -> 1288488 bytes .../Src/stm32l4xx_hal_pcd_ex.su | 9 + .../Src/stm32l4xx_hal_pwr.cyclo | 16 + .../Src/stm32l4xx_hal_pwr.d | 72 + .../Src/stm32l4xx_hal_pwr.o | Bin 0 -> 1290100 bytes .../Src/stm32l4xx_hal_pwr.su | 16 + .../Src/stm32l4xx_hal_pwr_ex.cyclo | 39 + .../Src/stm32l4xx_hal_pwr_ex.d | 72 + .../Src/stm32l4xx_hal_pwr_ex.o | Bin 0 -> 1300916 bytes .../Src/stm32l4xx_hal_pwr_ex.su | 39 + .../Src/stm32l4xx_hal_qspi.cyclo | 41 + .../Src/stm32l4xx_hal_qspi.d | 72 + .../Src/stm32l4xx_hal_qspi.o | Bin 0 -> 1310440 bytes .../Src/stm32l4xx_hal_qspi.su | 41 + .../Src/stm32l4xx_hal_rcc.cyclo | 15 + .../Src/stm32l4xx_hal_rcc.d | 72 + .../Src/stm32l4xx_hal_rcc.o | Bin 0 -> 1298408 bytes .../Src/stm32l4xx_hal_rcc.su | 15 + .../Src/stm32l4xx_hal_rcc_ex.cyclo | 21 + .../Src/stm32l4xx_hal_rcc_ex.d | 72 + .../Src/stm32l4xx_hal_rcc_ex.o | Bin 0 -> 1306460 bytes .../Src/stm32l4xx_hal_rcc_ex.su | 21 + .../Src/stm32l4xx_hal_spi.cyclo | 56 + .../Src/stm32l4xx_hal_spi.d | 72 + .../Src/stm32l4xx_hal_spi.o | Bin 0 -> 1324928 bytes .../Src/stm32l4xx_hal_spi.su | 56 + .../Src/stm32l4xx_hal_spi_ex.cyclo | 1 + .../Src/stm32l4xx_hal_spi_ex.d | 72 + .../Src/stm32l4xx_hal_spi_ex.o | Bin 0 -> 1283408 bytes .../Src/stm32l4xx_hal_spi_ex.su | 1 + .../Src/stm32l4xx_hal_uart.cyclo | 66 + .../Src/stm32l4xx_hal_uart.d | 72 + .../Src/stm32l4xx_hal_uart.o | Bin 0 -> 1347468 bytes .../Src/stm32l4xx_hal_uart.su | 66 + .../Src/stm32l4xx_hal_uart_ex.cyclo | 13 + .../Src/stm32l4xx_hal_uart_ex.d | 72 + .../Src/stm32l4xx_hal_uart_ex.o | Bin 0 -> 1293964 bytes .../Src/stm32l4xx_hal_uart_ex.su | 13 + .../Src/stm32l4xx_ll_usb.cyclo | 49 + .../Src/stm32l4xx_ll_usb.d | 72 + .../Src/stm32l4xx_ll_usb.o | Bin 0 -> 1318808 bytes .../Src/stm32l4xx_ll_usb.su | 49 + .../STM32L4xx_HAL_Driver/Src/subdir.mk | 96 + P1_SETR2/Debug/P1_SETR2.elf | Bin 0 -> 1425532 bytes P1_SETR2/Debug/P1_SETR2.list | 13125 +++++++++++ P1_SETR2/Debug/P1_SETR2.map | 5370 +++++ P1_SETR2/Debug/makefile | 94 + P1_SETR2/Debug/objects.list | 33 + P1_SETR2/Debug/objects.mk | 9 + P1_SETR2/Debug/sources.mk | 28 + .../Device/ST/STM32L4xx/Include/stm32l475xx.h | 18342 ++++++++++++++++ .../Device/ST/STM32L4xx/Include/stm32l4xx.h | 303 + .../ST/STM32L4xx/Include/system_stm32l4xx.h | 106 + .../CMSIS/Device/ST/STM32L4xx/LICENSE.txt | 6 + .../CMSIS/Device/ST/STM32L4xx/License.md | 83 + P1_SETR2/Drivers/CMSIS/Include/cmsis_armcc.h | 894 + .../Drivers/CMSIS/Include/cmsis_armclang.h | 1444 ++ .../CMSIS/Include/cmsis_armclang_ltm.h | 1891 ++ .../Drivers/CMSIS/Include/cmsis_compiler.h | 283 + P1_SETR2/Drivers/CMSIS/Include/cmsis_gcc.h | 2168 ++ P1_SETR2/Drivers/CMSIS/Include/cmsis_iccarm.h | 964 + .../Drivers/CMSIS/Include/cmsis_version.h | 39 + .../Drivers/CMSIS/Include/core_armv81mml.h | 2968 +++ .../Drivers/CMSIS/Include/core_armv8mbl.h | 1921 ++ .../Drivers/CMSIS/Include/core_armv8mml.h | 2835 +++ P1_SETR2/Drivers/CMSIS/Include/core_cm0.h | 952 + P1_SETR2/Drivers/CMSIS/Include/core_cm0plus.h | 1085 + P1_SETR2/Drivers/CMSIS/Include/core_cm1.h | 979 + P1_SETR2/Drivers/CMSIS/Include/core_cm23.h | 1996 ++ P1_SETR2/Drivers/CMSIS/Include/core_cm3.h | 1937 ++ P1_SETR2/Drivers/CMSIS/Include/core_cm33.h | 2910 +++ P1_SETR2/Drivers/CMSIS/Include/core_cm35p.h | 2910 +++ P1_SETR2/Drivers/CMSIS/Include/core_cm4.h | 2124 ++ P1_SETR2/Drivers/CMSIS/Include/core_cm7.h | 2725 +++ P1_SETR2/Drivers/CMSIS/Include/core_sc000.h | 1025 + P1_SETR2/Drivers/CMSIS/Include/core_sc300.h | 1912 ++ P1_SETR2/Drivers/CMSIS/Include/mpu_armv7.h | 272 + P1_SETR2/Drivers/CMSIS/Include/mpu_armv8.h | 346 + P1_SETR2/Drivers/CMSIS/Include/tz_context.h | 70 + P1_SETR2/Drivers/CMSIS/LICENSE.txt | 201 + .../Inc/Legacy/stm32_hal_legacy.h | 4374 ++++ .../STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h | 726 + .../Inc/stm32l4xx_hal_cortex.h | 422 + .../Inc/stm32l4xx_hal_def.h | 211 + .../Inc/stm32l4xx_hal_dfsdm.h | 894 + .../Inc/stm32l4xx_hal_dma.h | 861 + .../Inc/stm32l4xx_hal_dma_ex.h | 284 + .../Inc/stm32l4xx_hal_exti.h | 858 + .../Inc/stm32l4xx_hal_flash.h | 1028 + .../Inc/stm32l4xx_hal_flash_ex.h | 125 + .../Inc/stm32l4xx_hal_flash_ramfunc.h | 74 + .../Inc/stm32l4xx_hal_gpio.h | 323 + .../Inc/stm32l4xx_hal_gpio_ex.h | 1060 + .../Inc/stm32l4xx_hal_i2c.h | 838 + .../Inc/stm32l4xx_hal_i2c_ex.h | 184 + .../Inc/stm32l4xx_hal_pcd.h | 1049 + .../Inc/stm32l4xx_hal_pcd_ex.h | 91 + .../Inc/stm32l4xx_hal_pwr.h | 411 + .../Inc/stm32l4xx_hal_pwr_ex.h | 929 + .../Inc/stm32l4xx_hal_qspi.h | 766 + .../Inc/stm32l4xx_hal_rcc.h | 4883 ++++ .../Inc/stm32l4xx_hal_rcc_ex.h | 3045 +++ .../Inc/stm32l4xx_hal_spi.h | 855 + .../Inc/stm32l4xx_hal_spi_ex.h | 73 + .../Inc/stm32l4xx_hal_uart.h | 1810 ++ .../Inc/stm32l4xx_hal_uart_ex.h | 748 + .../Inc/stm32l4xx_ll_bus.h | 1954 ++ .../Inc/stm32l4xx_ll_cortex.h | 637 + .../Inc/stm32l4xx_ll_crs.h | 785 + .../Inc/stm32l4xx_ll_dma.h | 2430 ++ .../Inc/stm32l4xx_ll_dmamux.h | 1981 ++ .../Inc/stm32l4xx_ll_exti.h | 1359 ++ .../Inc/stm32l4xx_ll_gpio.h | 1056 + .../Inc/stm32l4xx_ll_i2c.h | 2279 ++ .../Inc/stm32l4xx_ll_lpuart.h | 2892 +++ .../Inc/stm32l4xx_ll_pwr.h | 1675 ++ .../Inc/stm32l4xx_ll_rcc.h | 6233 ++++++ .../Inc/stm32l4xx_ll_spi.h | 1433 ++ .../Inc/stm32l4xx_ll_system.h | 1629 ++ .../Inc/stm32l4xx_ll_usart.h | 4699 ++++ .../Inc/stm32l4xx_ll_usb.h | 641 + .../Inc/stm32l4xx_ll_utils.h | 329 + .../Drivers/STM32L4xx_HAL_Driver/LICENSE.txt | 6 + .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c | 765 + .../Src/stm32l4xx_hal_cortex.c | 541 + .../Src/stm32l4xx_hal_dfsdm.c | 3576 +++ .../Src/stm32l4xx_hal_dma.c | 1174 + .../Src/stm32l4xx_hal_dma_ex.c | 307 + .../Src/stm32l4xx_hal_exti.c | 638 + .../Src/stm32l4xx_hal_flash.c | 764 + .../Src/stm32l4xx_hal_flash_ex.c | 1316 ++ .../Src/stm32l4xx_hal_flash_ramfunc.c | 251 + .../Src/stm32l4xx_hal_gpio.c | 551 + .../Src/stm32l4xx_hal_i2c.c | 7548 +++++++ .../Src/stm32l4xx_hal_i2c_ex.c | 368 + .../Src/stm32l4xx_hal_pcd.c | 2940 +++ .../Src/stm32l4xx_hal_pcd_ex.c | 559 + .../Src/stm32l4xx_hal_pwr.c | 658 + .../Src/stm32l4xx_hal_pwr_ex.c | 1474 ++ .../Src/stm32l4xx_hal_qspi.c | 2834 +++ .../Src/stm32l4xx_hal_rcc.c | 1942 ++ .../Src/stm32l4xx_hal_rcc_ex.c | 3556 +++ .../Src/stm32l4xx_hal_spi.c | 4472 ++++ .../Src/stm32l4xx_hal_spi_ex.c | 112 + .../Src/stm32l4xx_hal_uart.c | 4919 +++++ .../Src/stm32l4xx_hal_uart_ex.c | 1098 + .../Src/stm32l4xx_ll_usb.c | 2908 +++ P1_SETR2/P1_SETR2.ioc | 619 + P1_SETR2/P1_SETR2.launch | 86 + P1_SETR2/STM32L475VGTX_FLASH.ld | 190 + P1_SETR2/STM32L475VGTX_RAM.ld | 190 + 262 files changed, 187270 insertions(+) create mode 100644 P1_SETR2/.cproject create mode 100644 P1_SETR2/.mxproject create mode 100644 P1_SETR2/.project create mode 100644 P1_SETR2/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs create mode 100644 P1_SETR2/.settings/language.settings.xml create mode 100644 P1_SETR2/.settings/org.eclipse.core.resources.prefs create mode 100644 P1_SETR2/.settings/stm32cubeide.project.prefs create mode 100644 P1_SETR2/Core/Inc/joystick_driver.h create mode 100644 P1_SETR2/Core/Inc/led_driver.h create mode 100644 P1_SETR2/Core/Inc/main.h create mode 100644 P1_SETR2/Core/Inc/stm32l4xx_hal_conf.h create mode 100644 P1_SETR2/Core/Inc/stm32l4xx_it.h create mode 100644 P1_SETR2/Core/Src/joystick.c create mode 100644 P1_SETR2/Core/Src/led_driver.c create mode 100644 P1_SETR2/Core/Src/main.c create mode 100644 P1_SETR2/Core/Src/stm32l4xx_hal_msp.c create mode 100644 P1_SETR2/Core/Src/stm32l4xx_it.c create mode 100644 P1_SETR2/Core/Src/syscalls.c create mode 100644 P1_SETR2/Core/Src/sysmem.c create mode 100644 P1_SETR2/Core/Src/system_stm32l4xx.c create mode 100644 P1_SETR2/Core/Startup/startup_stm32l475vgtx.s create mode 100644 P1_SETR2/Debug/Core/Src/joystick.cyclo create mode 100644 P1_SETR2/Debug/Core/Src/joystick.d create mode 100644 P1_SETR2/Debug/Core/Src/joystick.o create mode 100644 P1_SETR2/Debug/Core/Src/joystick.su create mode 100644 P1_SETR2/Debug/Core/Src/led_driver.cyclo create mode 100644 P1_SETR2/Debug/Core/Src/led_driver.d create mode 100644 P1_SETR2/Debug/Core/Src/led_driver.o create mode 100644 P1_SETR2/Debug/Core/Src/led_driver.su create mode 100644 P1_SETR2/Debug/Core/Src/main.cyclo create mode 100644 P1_SETR2/Debug/Core/Src/main.d create mode 100644 P1_SETR2/Debug/Core/Src/main.o create mode 100644 P1_SETR2/Debug/Core/Src/main.su create mode 100644 P1_SETR2/Debug/Core/Src/stm32l4xx_hal_msp.cyclo create mode 100644 P1_SETR2/Debug/Core/Src/stm32l4xx_hal_msp.d create mode 100644 P1_SETR2/Debug/Core/Src/stm32l4xx_hal_msp.o create mode 100644 P1_SETR2/Debug/Core/Src/stm32l4xx_hal_msp.su create mode 100644 P1_SETR2/Debug/Core/Src/stm32l4xx_it.cyclo create mode 100644 P1_SETR2/Debug/Core/Src/stm32l4xx_it.d create mode 100644 P1_SETR2/Debug/Core/Src/stm32l4xx_it.o create mode 100644 P1_SETR2/Debug/Core/Src/stm32l4xx_it.su create mode 100644 P1_SETR2/Debug/Core/Src/subdir.mk create mode 100644 P1_SETR2/Debug/Core/Src/syscalls.cyclo create mode 100644 P1_SETR2/Debug/Core/Src/syscalls.d create mode 100644 P1_SETR2/Debug/Core/Src/syscalls.o create mode 100644 P1_SETR2/Debug/Core/Src/syscalls.su create mode 100644 P1_SETR2/Debug/Core/Src/sysmem.cyclo create mode 100644 P1_SETR2/Debug/Core/Src/sysmem.d create mode 100644 P1_SETR2/Debug/Core/Src/sysmem.o create mode 100644 P1_SETR2/Debug/Core/Src/sysmem.su create mode 100644 P1_SETR2/Debug/Core/Src/system_stm32l4xx.cyclo create mode 100644 P1_SETR2/Debug/Core/Src/system_stm32l4xx.d create mode 100644 P1_SETR2/Debug/Core/Src/system_stm32l4xx.o create mode 100644 P1_SETR2/Debug/Core/Src/system_stm32l4xx.su create mode 100644 P1_SETR2/Debug/Core/Startup/startup_stm32l475vgtx.d create mode 100644 P1_SETR2/Debug/Core/Startup/startup_stm32l475vgtx.o create mode 100644 P1_SETR2/Debug/Core/Startup/subdir.mk create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.cyclo create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.d create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.su create mode 100644 P1_SETR2/Debug/Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk create mode 100755 P1_SETR2/Debug/P1_SETR2.elf create mode 100644 P1_SETR2/Debug/P1_SETR2.list create mode 100644 P1_SETR2/Debug/P1_SETR2.map create mode 100644 P1_SETR2/Debug/makefile create mode 100644 P1_SETR2/Debug/objects.list create mode 100644 P1_SETR2/Debug/objects.mk create mode 100644 P1_SETR2/Debug/sources.mk create mode 100644 P1_SETR2/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h create mode 100644 P1_SETR2/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h create mode 100644 P1_SETR2/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h create mode 100644 P1_SETR2/Drivers/CMSIS/Device/ST/STM32L4xx/LICENSE.txt create mode 100644 P1_SETR2/Drivers/CMSIS/Device/ST/STM32L4xx/License.md create mode 100644 P1_SETR2/Drivers/CMSIS/Include/cmsis_armcc.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/cmsis_armclang.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/cmsis_armclang_ltm.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/cmsis_compiler.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/cmsis_gcc.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/cmsis_iccarm.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/cmsis_version.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_armv81mml.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_armv8mbl.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_armv8mml.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm0.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm0plus.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm1.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm23.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm3.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm33.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm35p.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm4.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_cm7.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_sc000.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/core_sc300.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/mpu_armv7.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/mpu_armv8.h create mode 100644 P1_SETR2/Drivers/CMSIS/Include/tz_context.h create mode 100644 P1_SETR2/Drivers/CMSIS/LICENSE.txt create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/LICENSE.txt create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c create mode 100644 P1_SETR2/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c create mode 100644 P1_SETR2/P1_SETR2.ioc create mode 100644 P1_SETR2/P1_SETR2.launch create mode 100644 P1_SETR2/STM32L475VGTX_FLASH.ld create mode 100644 P1_SETR2/STM32L475VGTX_RAM.ld diff --git a/P1_SETR2/.cproject b/P1_SETR2/.cproject new file mode 100644 index 0000000..4d23ff3 --- /dev/null +++ b/P1_SETR2/.cproject @@ -0,0 +1,175 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/P1_SETR2/.mxproject b/P1_SETR2/.mxproject new file mode 100644 index 0000000..076f8cd --- /dev/null +++ b/P1_SETR2/.mxproject @@ -0,0 +1,25 @@ +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=../Core/Inc/stm32l4xx_it.h +HeaderFiles#1=../Core/Inc/stm32l4xx_hal_conf.h +HeaderFiles#2=../Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=../Core/Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=../Core/Src/stm32l4xx_it.c +SourceFiles#1=../Core/Src/stm32l4xx_hal_msp.c +SourceFiles#2=../Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=../Core/Src +SourceFiles=; + +[PreviousLibFiles] +LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_cm1.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Core/Src/main.c;Core/Src/stm32l4xx_it.c;Core/Src/stm32l4xx_hal_msp.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core/Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core/Src/system_stm32l4xx.c;;; +HeaderPath=Drivers/STM32L4xx_HAL_Driver/Inc;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32L4xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_HAL_DRIVER;STM32L475xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/P1_SETR2/.project b/P1_SETR2/.project new file mode 100644 index 0000000..8c11f04 --- /dev/null +++ b/P1_SETR2/.project @@ -0,0 +1,32 @@ + + + P1_SETR2 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/P1_SETR2/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/P1_SETR2/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs new file mode 100644 index 0000000..98a69fc --- /dev/null +++ b/P1_SETR2/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} diff --git a/P1_SETR2/.settings/language.settings.xml b/P1_SETR2/.settings/language.settings.xml new file mode 100644 index 0000000..cc0e876 --- /dev/null +++ b/P1_SETR2/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/P1_SETR2/.settings/org.eclipse.core.resources.prefs b/P1_SETR2/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..99f26c0 --- /dev/null +++ b/P1_SETR2/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/P1_SETR2/.settings/stm32cubeide.project.prefs b/P1_SETR2/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..d68abc9 --- /dev/null +++ b/P1_SETR2/.settings/stm32cubeide.project.prefs @@ -0,0 +1,5 @@ +635E684B79701B039C64EA45C3F84D30=148B39F5C8E660B250DE15501797F200 +66BE74F758C12D739921AEA421D593D3=0 +8DF89ED150041C4CBC7CB9A9CAA90856=D61A9D5E0823FD3A26503CBA2CCE68C1 +DC22A860405A8BF2F2C095E5B6529F12=D61A9D5E0823FD3A26503CBA2CCE68C1 +eclipse.preferences.version=1 diff --git a/P1_SETR2/Core/Inc/joystick_driver.h b/P1_SETR2/Core/Inc/joystick_driver.h new file mode 100644 index 0000000..b6d0de8 --- /dev/null +++ b/P1_SETR2/Core/Inc/joystick_driver.h @@ -0,0 +1,15 @@ +/* + * joystick_driver.h + * + * Created on: Oct 6, 2025 + * Author: jomaa + */ + +#ifndef INC_JOYSTICK_DRIVER_H_ +#define INC_JOYSTICK_DRIVER_H_ + +#include "stm32l4xx_hal.h" + +uint8_t ReadJoy(void); + +#endif /* INC_JOYSTICK_DRIVER_H_ */ diff --git a/P1_SETR2/Core/Inc/led_driver.h b/P1_SETR2/Core/Inc/led_driver.h new file mode 100644 index 0000000..9229b49 --- /dev/null +++ b/P1_SETR2/Core/Inc/led_driver.h @@ -0,0 +1,17 @@ +/* + * led_driver.h + * + * Created on: Oct 6, 2025 + * Author: jomaa + */ + +#ifndef INC_LED_DRIVER_H_ +#define INC_LED_DRIVER_H_ + +#include "stm32l4xx_hal.h" + +void LED_On(uint8_t led); +void LED_Off(uint8_t led); +void LED_Toggle(uint8_t led); + +#endif /* INC_LED_DRIVER_H_ */ diff --git a/P1_SETR2/Core/Inc/main.h b/P1_SETR2/Core/Inc/main.h new file mode 100644 index 0000000..b5de1a8 --- /dev/null +++ b/P1_SETR2/Core/Inc/main.h @@ -0,0 +1,234 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define M24SR64_Y_RF_DISABLE_Pin GPIO_PIN_2 +#define M24SR64_Y_RF_DISABLE_GPIO_Port GPIOE +#define USB_OTG_FS_OVRCR_EXTI3_Pin GPIO_PIN_3 +#define USB_OTG_FS_OVRCR_EXTI3_GPIO_Port GPIOE +#define M24SR64_Y_GPO_Pin GPIO_PIN_4 +#define M24SR64_Y_GPO_GPIO_Port GPIOE +#define SPSGRF_915_GPIO3_EXTI5_Pin GPIO_PIN_5 +#define SPSGRF_915_GPIO3_EXTI5_GPIO_Port GPIOE +#define SPSGRF_915_GPIO3_EXTI5_EXTI_IRQn EXTI9_5_IRQn +#define SPBTLE_RF_IRQ_EXTI6_Pin GPIO_PIN_6 +#define SPBTLE_RF_IRQ_EXTI6_GPIO_Port GPIOE +#define SPBTLE_RF_IRQ_EXTI6_EXTI_IRQn EXTI9_5_IRQn +#define BUTTON_EXTI13_Pin GPIO_PIN_13 +#define BUTTON_EXTI13_GPIO_Port GPIOC +#define BUTTON_EXTI13_EXTI_IRQn EXTI15_10_IRQn +#define ARD_A5_Pin GPIO_PIN_0 +#define ARD_A5_GPIO_Port GPIOC +#define ARD_A4_Pin GPIO_PIN_1 +#define ARD_A4_GPIO_Port GPIOC +#define ARD_A3_Pin GPIO_PIN_2 +#define ARD_A3_GPIO_Port GPIOC +#define ARD_A2_Pin GPIO_PIN_3 +#define ARD_A2_GPIO_Port GPIOC +#define ARD_D1_Pin GPIO_PIN_0 +#define ARD_D1_GPIO_Port GPIOA +#define ARD_D0_Pin GPIO_PIN_1 +#define ARD_D0_GPIO_Port GPIOA +#define ARD_D10_Pin GPIO_PIN_2 +#define ARD_D10_GPIO_Port GPIOA +#define ARD_D4_Pin GPIO_PIN_3 +#define ARD_D4_GPIO_Port GPIOA +#define ARD_D7_Pin GPIO_PIN_4 +#define ARD_D7_GPIO_Port GPIOA +#define ARD_D13_Pin GPIO_PIN_5 +#define ARD_D13_GPIO_Port GPIOA +#define ARD_D12_Pin GPIO_PIN_6 +#define ARD_D12_GPIO_Port GPIOA +#define ARD_D11_Pin GPIO_PIN_7 +#define ARD_D11_GPIO_Port GPIOA +#define ARD_A1_Pin GPIO_PIN_4 +#define ARD_A1_GPIO_Port GPIOC +#define ARD_A0_Pin GPIO_PIN_5 +#define ARD_A0_GPIO_Port GPIOC +#define ARD_D3_Pin GPIO_PIN_0 +#define ARD_D3_GPIO_Port GPIOB +#define ARD_D6_Pin GPIO_PIN_1 +#define ARD_D6_GPIO_Port GPIOB +#define ARD_D8_Pin GPIO_PIN_2 +#define ARD_D8_GPIO_Port GPIOB +#define DFSDM1_DATIN2_Pin GPIO_PIN_7 +#define DFSDM1_DATIN2_GPIO_Port GPIOE +#define ISM43362_RST_Pin GPIO_PIN_8 +#define ISM43362_RST_GPIO_Port GPIOE +#define DFSDM1_CKOUT_Pin GPIO_PIN_9 +#define DFSDM1_CKOUT_GPIO_Port GPIOE +#define QUADSPI_CLK_Pin GPIO_PIN_10 +#define QUADSPI_CLK_GPIO_Port GPIOE +#define QUADSPI_NCS_Pin GPIO_PIN_11 +#define QUADSPI_NCS_GPIO_Port GPIOE +#define OQUADSPI_BK1_IO0_Pin GPIO_PIN_12 +#define OQUADSPI_BK1_IO0_GPIO_Port GPIOE +#define QUADSPI_BK1_IO1_Pin GPIO_PIN_13 +#define QUADSPI_BK1_IO1_GPIO_Port GPIOE +#define QUAD_SPI_BK1_IO2_Pin GPIO_PIN_14 +#define QUAD_SPI_BK1_IO2_GPIO_Port GPIOE +#define QUAD_SPI_BK1_IO3_Pin GPIO_PIN_15 +#define QUAD_SPI_BK1_IO3_GPIO_Port GPIOE +#define INTERNAL_I2C2_SCL_Pin GPIO_PIN_10 +#define INTERNAL_I2C2_SCL_GPIO_Port GPIOB +#define INTERNAL_I2C2_SDA_Pin GPIO_PIN_11 +#define INTERNAL_I2C2_SDA_GPIO_Port GPIOB +#define ISM43362_BOOT0_Pin GPIO_PIN_12 +#define ISM43362_BOOT0_GPIO_Port GPIOB +#define ISM43362_WAKEUP_Pin GPIO_PIN_13 +#define ISM43362_WAKEUP_GPIO_Port GPIOB +#define LED2_Pin GPIO_PIN_14 +#define LED2_GPIO_Port GPIOB +#define SPSGRF_915_SDN_Pin GPIO_PIN_15 +#define SPSGRF_915_SDN_GPIO_Port GPIOB +#define INTERNAL_UART3_TX_Pin GPIO_PIN_8 +#define INTERNAL_UART3_TX_GPIO_Port GPIOD +#define INTERNAL_UART3_RX_Pin GPIO_PIN_9 +#define INTERNAL_UART3_RX_GPIO_Port GPIOD +#define LPS22HB_INT_DRDY_EXTI0_Pin GPIO_PIN_10 +#define LPS22HB_INT_DRDY_EXTI0_GPIO_Port GPIOD +#define LPS22HB_INT_DRDY_EXTI0_EXTI_IRQn EXTI15_10_IRQn +#define LSM6DSL_INT1_EXTI11_Pin GPIO_PIN_11 +#define LSM6DSL_INT1_EXTI11_GPIO_Port GPIOD +#define LSM6DSL_INT1_EXTI11_EXTI_IRQn EXTI15_10_IRQn +#define USB_OTG_FS_PWR_EN_Pin GPIO_PIN_12 +#define USB_OTG_FS_PWR_EN_GPIO_Port GPIOD +#define SPBTLE_RF_SPI3_CSN_Pin GPIO_PIN_13 +#define SPBTLE_RF_SPI3_CSN_GPIO_Port GPIOD +#define ARD_D2_Pin GPIO_PIN_14 +#define ARD_D2_GPIO_Port GPIOD +#define ARD_D2_EXTI_IRQn EXTI15_10_IRQn +#define HTS221_DRDY_EXTI15_Pin GPIO_PIN_15 +#define HTS221_DRDY_EXTI15_GPIO_Port GPIOD +#define HTS221_DRDY_EXTI15_EXTI_IRQn EXTI15_10_IRQn +#define VL53L0X_XSHUT_Pin GPIO_PIN_6 +#define VL53L0X_XSHUT_GPIO_Port GPIOC +#define VL53L0X_GPIO1_EXTI7_Pin GPIO_PIN_7 +#define VL53L0X_GPIO1_EXTI7_GPIO_Port GPIOC +#define VL53L0X_GPIO1_EXTI7_EXTI_IRQn EXTI9_5_IRQn +#define LSM3MDL_DRDY_EXTI8_Pin GPIO_PIN_8 +#define LSM3MDL_DRDY_EXTI8_GPIO_Port GPIOC +#define LSM3MDL_DRDY_EXTI8_EXTI_IRQn EXTI9_5_IRQn +#define LED3_WIFI__LED4_BLE_Pin GPIO_PIN_9 +#define LED3_WIFI__LED4_BLE_GPIO_Port GPIOC +#define SPBTLE_RF_RST_Pin GPIO_PIN_8 +#define SPBTLE_RF_RST_GPIO_Port GPIOA +#define USB_OTG_FS_VBUS_Pin GPIO_PIN_9 +#define USB_OTG_FS_VBUS_GPIO_Port GPIOA +#define USB_OTG_FS_ID_Pin GPIO_PIN_10 +#define USB_OTG_FS_ID_GPIO_Port GPIOA +#define USB_OTG_FS_DM_Pin GPIO_PIN_11 +#define USB_OTG_FS_DM_GPIO_Port GPIOA +#define USB_OTG_FS_DP_Pin GPIO_PIN_12 +#define USB_OTG_FS_DP_GPIO_Port GPIOA +#define SYS_JTMS_SWDIO_Pin GPIO_PIN_13 +#define SYS_JTMS_SWDIO_GPIO_Port GPIOA +#define SYS_JTCK_SWCLK_Pin GPIO_PIN_14 +#define SYS_JTCK_SWCLK_GPIO_Port GPIOA +#define ARD_D9_Pin GPIO_PIN_15 +#define ARD_D9_GPIO_Port GPIOA +#define INTERNAL_SPI3_SCK_Pin GPIO_PIN_10 +#define INTERNAL_SPI3_SCK_GPIO_Port GPIOC +#define INTERNAL_SPI3_MISO_Pin GPIO_PIN_11 +#define INTERNAL_SPI3_MISO_GPIO_Port GPIOC +#define INTERNAL_SPI3_MOSI_Pin GPIO_PIN_12 +#define INTERNAL_SPI3_MOSI_GPIO_Port GPIOC +#define PMOD_RESET_Pin GPIO_PIN_0 +#define PMOD_RESET_GPIO_Port GPIOD +#define PMOD_SPI2_SCK_Pin GPIO_PIN_1 +#define PMOD_SPI2_SCK_GPIO_Port GPIOD +#define PMOD_IRQ_EXTI12_Pin GPIO_PIN_2 +#define PMOD_IRQ_EXTI12_GPIO_Port GPIOD +#define PMOD_UART2_CTS_Pin GPIO_PIN_3 +#define PMOD_UART2_CTS_GPIO_Port GPIOD +#define PMOD_UART2_RTS_Pin GPIO_PIN_4 +#define PMOD_UART2_RTS_GPIO_Port GPIOD +#define PMOD_UART2_TX_Pin GPIO_PIN_5 +#define PMOD_UART2_TX_GPIO_Port GPIOD +#define PMOD_UART2_RX_Pin GPIO_PIN_6 +#define PMOD_UART2_RX_GPIO_Port GPIOD +#define STSAFE_A100_RESET_Pin GPIO_PIN_7 +#define STSAFE_A100_RESET_GPIO_Port GPIOD +#define SYS_JTD0_SWO_Pin GPIO_PIN_3 +#define SYS_JTD0_SWO_GPIO_Port GPIOB +#define ARD_D5_Pin GPIO_PIN_4 +#define ARD_D5_GPIO_Port GPIOB +#define SPSGRF_915_SPI3_CSN_Pin GPIO_PIN_5 +#define SPSGRF_915_SPI3_CSN_GPIO_Port GPIOB +#define ST_LINK_UART1_TX_Pin GPIO_PIN_6 +#define ST_LINK_UART1_TX_GPIO_Port GPIOB +#define ST_LINK_UART1_RX_Pin GPIO_PIN_7 +#define ST_LINK_UART1_RX_GPIO_Port GPIOB +#define ARD_D15_Pin GPIO_PIN_8 +#define ARD_D15_GPIO_Port GPIOB +#define ARD_D14_Pin GPIO_PIN_9 +#define ARD_D14_GPIO_Port GPIOB +#define ISM43362_SPI3_CSN_Pin GPIO_PIN_0 +#define ISM43362_SPI3_CSN_GPIO_Port GPIOE +#define ISM43362_DRDY_EXTI1_Pin GPIO_PIN_1 +#define ISM43362_DRDY_EXTI1_GPIO_Port GPIOE + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/P1_SETR2/Core/Inc/stm32l4xx_hal_conf.h b/P1_SETR2/Core/Inc/stm32l4xx_hal_conf.h new file mode 100644 index 0000000..70d89e9 --- /dev/null +++ b/P1_SETR2/Core/Inc/stm32l4xx_hal_conf.h @@ -0,0 +1,482 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_HAL_CONF_H +#define STM32L4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_DFSDM_MODULE_ENABLED +/*#define HAL_DSI_MODULE_ENABLED */ +/*#define HAL_FIREWALL_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +#define HAL_QSPI_MODULE_ENABLED +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_SWPMI_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + #define EXTERNAL_SAI1_CLOCK_VALUE 2097000U /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/** + * @brief External clock source for SAI2 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) + #define EXTERNAL_SAI2_CLOCK_VALUE 2097000U /*!< Value of the SAI2 External clock source in Hz*/ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l4xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32l4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32l4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32l4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32l4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32l4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l4xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32l4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32l4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l4xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32l4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32l4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32l4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32l4xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32l4xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32l4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32l4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32l4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32l4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32l4xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32l4xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_HAL_CONF_H */ diff --git a/P1_SETR2/Core/Inc/stm32l4xx_it.h b/P1_SETR2/Core/Inc/stm32l4xx_it.h new file mode 100644 index 0000000..1849518 --- /dev/null +++ b/P1_SETR2/Core/Inc/stm32l4xx_it.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_IT_H +#define __STM32L4xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI9_5_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_IT_H */ diff --git a/P1_SETR2/Core/Src/joystick.c b/P1_SETR2/Core/Src/joystick.c new file mode 100644 index 0000000..d01f560 --- /dev/null +++ b/P1_SETR2/Core/Src/joystick.c @@ -0,0 +1,27 @@ +/* + * joystick.c + * + * Created on: Oct 6, 2025 + * Author: jomaa + */ + +#include "joystick_driver.h" + +static uint8_t previous_state = GPIO_PIN_SET; +static uint8_t virtual_button = 0; + +uint8_t ReadJoy(void) +{ + GPIO_PinState current_state = HAL_GPIO_ReadPin(GPIOC, GPIO_PIN_13); + + if (previous_state == GPIO_PIN_SET && current_state == GPIO_PIN_RESET) + { + virtual_button++; + if (virtual_button > 4) virtual_button = 1; + } + + previous_state = current_state; + + if (current_state == GPIO_PIN_RESET) return virtual_button; + else return 0; +} diff --git a/P1_SETR2/Core/Src/led_driver.c b/P1_SETR2/Core/Src/led_driver.c new file mode 100644 index 0000000..db9d45d --- /dev/null +++ b/P1_SETR2/Core/Src/led_driver.c @@ -0,0 +1,56 @@ +/* + * led_driver.c + * + * Created on: Oct 6, 2025 + * Author: jomaa + */ + +#include "led_driver.h" + +void LED_On(uint8_t led) +{ + switch(led) + { + case 0: + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); + break; + case 1: + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET); + break; + case 2: + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET); + break; + } +} + +void LED_Off(uint8_t led) +{ + switch(led) + { + case 0: + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET); + break; + case 1: + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET); + break; + case 2: + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_RESET); + break; + } +} + +void LED_Toggle(uint8_t led) +{ + switch(led) + { + case 0: + HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_5); + break; + case 1: + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_14); + break; + case 2: + HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_9); + break; + } +} diff --git a/P1_SETR2/Core/Src/main.c b/P1_SETR2/Core/Src/main.c new file mode 100644 index 0000000..5875104 --- /dev/null +++ b/P1_SETR2/Core/Src/main.c @@ -0,0 +1,736 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "led_driver.h" +#include "joystick_driver.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +DFSDM_Channel_HandleTypeDef hdfsdm1_channel1; + +I2C_HandleTypeDef hi2c2; + +QSPI_HandleTypeDef hqspi; + +SPI_HandleTypeDef hspi3; + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart3; + +PCD_HandleTypeDef hpcd_USB_OTG_FS; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_DFSDM1_Init(void); +static void MX_I2C2_Init(void); +static void MX_QUADSPI_Init(void); +static void MX_SPI3_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_USB_OTG_FS_PCD_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void animation1(void){ + int i; + for(i = 0; i < 3; i++){ + LED_On(i); + HAL_Delay(150); + LED_Off(i); + } + for(i = 1; i > 0; i--){ + LED_On(i); + HAL_Delay(150); + LED_Off(i); + } +} + +void animation2(void){ + int i, j; + for(j = 0; j < 5; j++){ + for(i = 0; i < 3; i++) + LED_On(i); + HAL_Delay(100); + for(i = 0; i < 3; i++) + LED_Off(i); + HAL_Delay(100); + } +} + +void animation3(void){ + int i; + for(i = 0; i < 3; i++){ + LED_On(i); + HAL_Delay(150); + } + for(i = 2; i >= 0; i--){ + LED_Off(i); + HAL_Delay(150); + } +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DFSDM1_Init(); + MX_I2C2_Init(); + MX_QUADSPI_Init(); + MX_SPI3_Init(); + MX_USART1_UART_Init(); + MX_USART3_UART_Init(); + MX_USB_OTG_FS_PCD_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + switch(ReadJoy()) + { + case 0: + // stand-by + LED_Off(0); + LED_Off(1); + LED_Off(2); + break; + case 1: + animation1(); + break; + case 2: + animation2(); + break; + case 3: + animation3(); + break; + } + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = 0; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } + + /** Enable MSI Auto calibration + */ + HAL_RCCEx_EnableMSIPLLMode(); +} + +/** + * @brief DFSDM1 Initialization Function + * @param None + * @retval None + */ +static void MX_DFSDM1_Init(void) +{ + + /* USER CODE BEGIN DFSDM1_Init 0 */ + + /* USER CODE END DFSDM1_Init 0 */ + + /* USER CODE BEGIN DFSDM1_Init 1 */ + + /* USER CODE END DFSDM1_Init 1 */ + hdfsdm1_channel1.Instance = DFSDM1_Channel1; + hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE; + hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM; + hdfsdm1_channel1.Init.OutputClock.Divider = 2; + hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS; + hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE; + hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS; + hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING; + hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL; + hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER; + hdfsdm1_channel1.Init.Awd.Oversampling = 1; + hdfsdm1_channel1.Init.Offset = 0; + hdfsdm1_channel1.Init.RightBitShift = 0x00; + if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DFSDM1_Init 2 */ + + /* USER CODE END DFSDM1_Init 2 */ + +} + +/** + * @brief I2C2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C2_Init(void) +{ + + /* USER CODE BEGIN I2C2_Init 0 */ + + /* USER CODE END I2C2_Init 0 */ + + /* USER CODE BEGIN I2C2_Init 1 */ + + /* USER CODE END I2C2_Init 1 */ + hi2c2.Instance = I2C2; + hi2c2.Init.Timing = 0x00000E14; + hi2c2.Init.OwnAddress1 = 0; + hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c2.Init.OwnAddress2 = 0; + hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c2) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C2_Init 2 */ + + /* USER CODE END I2C2_Init 2 */ + +} + +/** + * @brief QUADSPI Initialization Function + * @param None + * @retval None + */ +static void MX_QUADSPI_Init(void) +{ + + /* USER CODE BEGIN QUADSPI_Init 0 */ + + /* USER CODE END QUADSPI_Init 0 */ + + /* USER CODE BEGIN QUADSPI_Init 1 */ + + /* USER CODE END QUADSPI_Init 1 */ + /* QUADSPI parameter configuration*/ + hqspi.Instance = QUADSPI; + hqspi.Init.ClockPrescaler = 2; + hqspi.Init.FifoThreshold = 4; + hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; + hqspi.Init.FlashSize = 23; + hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE; + hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; + if (HAL_QSPI_Init(&hqspi) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN QUADSPI_Init 2 */ + + /* USER CODE END QUADSPI_Init 2 */ + +} + +/** + * @brief SPI3 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI3_Init(void) +{ + + /* USER CODE BEGIN SPI3_Init 0 */ + + /* USER CODE END SPI3_Init 0 */ + + /* USER CODE BEGIN SPI3_Init 1 */ + + /* USER CODE END SPI3_Init 1 */ + /* SPI3 parameter configuration*/ + hspi3.Instance = SPI3; + hspi3.Init.Mode = SPI_MODE_MASTER; + hspi3.Init.Direction = SPI_DIRECTION_2LINES; + hspi3.Init.DataSize = SPI_DATASIZE_4BIT; + hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi3.Init.NSS = SPI_NSS_SOFT; + hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi3.Init.TIMode = SPI_TIMODE_DISABLE; + hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi3.Init.CRCPolynomial = 7; + hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI3_Init 2 */ + + /* USER CODE END SPI3_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief USB_OTG_FS Initialization Function + * @param None + * @retval None + */ +static void MX_USB_OTG_FS_PCD_Init(void) +{ + + /* USER CODE BEGIN USB_OTG_FS_Init 0 */ + + /* USER CODE END USB_OTG_FS_Init 0 */ + + /* USER CODE BEGIN USB_OTG_FS_Init 1 */ + + /* USER CODE END USB_OTG_FS_Init 1 */ + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; + hpcd_USB_OTG_FS.Init.dev_endpoints = 6; + hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE; + hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_OTG_FS_Init 2 */ + + /* USER CODE END USB_OTG_FS_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin + |SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET); + + /*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */ + GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */ + GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pin : BUTTON_EXTI13_Pin */ + GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin + ARD_A1_Pin ARD_A0_Pin */ + GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin + |ARD_A1_Pin|ARD_A0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */ + GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART4; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : ARD_D10_Pin SPBTLE_RF_RST_Pin ARD_D9_Pin */ + GPIO_InitStruct.Pin = ARD_D10_Pin|SPBTLE_RF_RST_Pin|ARD_D9_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : ARD_D4_Pin */ + GPIO_InitStruct.Pin = ARD_D4_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : ARD_D7_Pin */ + GPIO_InitStruct.Pin = ARD_D7_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : ARD_D13_Pin ARD_D12_Pin ARD_D11_Pin */ + GPIO_InitStruct.Pin = ARD_D13_Pin|ARD_D12_Pin|ARD_D11_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : ARD_D3_Pin */ + GPIO_InitStruct.Pin = ARD_D3_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : ARD_D6_Pin */ + GPIO_InitStruct.Pin = ARD_D6_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin + SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */ + GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin + |SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin + PMOD_IRQ_EXTI12_Pin */ + GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin + |PMOD_IRQ_EXTI12_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */ + GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */ + GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */ + GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PMOD_SPI2_SCK_Pin */ + GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */ + GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */ + GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); + + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/P1_SETR2/Core/Src/stm32l4xx_hal_msp.c b/P1_SETR2/Core/Src/stm32l4xx_hal_msp.c new file mode 100644 index 0000000..fa1266b --- /dev/null +++ b/P1_SETR2/Core/Src/stm32l4xx_hal_msp.c @@ -0,0 +1,627 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +static uint32_t DFSDM1_Init = 0; +/** + * @brief DFSDM_Channel MSP Initialization + * This function configures the hardware resources used in this example + * @param hdfsdm_channel: DFSDM_Channel handle pointer + * @retval None + */ +void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(DFSDM1_Init == 0) + { + /* USER CODE BEGIN DFSDM1_MspInit 0 */ + + /* USER CODE END DFSDM1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1; + PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_DFSDM1_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + /**DFSDM1 GPIO Configuration + PE7 ------> DFSDM1_DATIN2 + PE9 ------> DFSDM1_CKOUT + */ + GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /* USER CODE BEGIN DFSDM1_MspInit 1 */ + + /* USER CODE END DFSDM1_MspInit 1 */ + + DFSDM1_Init++; + } + +} + +/** + * @brief DFSDM_Channel MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hdfsdm_channel: DFSDM_Channel handle pointer + * @retval None + */ +void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel) +{ + DFSDM1_Init-- ; + if(DFSDM1_Init == 0) + { + /* USER CODE BEGIN DFSDM1_MspDeInit 0 */ + + /* USER CODE END DFSDM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DFSDM1_CLK_DISABLE(); + + /**DFSDM1 GPIO Configuration + PE7 ------> DFSDM1_DATIN2 + PE9 ------> DFSDM1_CKOUT + */ + HAL_GPIO_DeInit(GPIOE, DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin); + + /* USER CODE BEGIN DFSDM1_MspDeInit 1 */ + + /* USER CODE END DFSDM1_MspDeInit 1 */ + } + +} + +/** + * @brief I2C MSP Initialization + * This function configures the hardware resources used in this example + * @param hi2c: I2C handle pointer + * @retval None + */ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hi2c->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspInit 0 */ + + /* USER CODE END I2C2_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2; + PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C2 GPIO Configuration + PB10 ------> I2C2_SCL + PB11 ------> I2C2_SDA + */ + GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C2_CLK_ENABLE(); + /* USER CODE BEGIN I2C2_MspInit 1 */ + + /* USER CODE END I2C2_MspInit 1 */ + + } + +} + +/** + * @brief I2C MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hi2c: I2C handle pointer + * @retval None + */ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + if(hi2c->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspDeInit 0 */ + + /* USER CODE END I2C2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C2_CLK_DISABLE(); + + /**I2C2 GPIO Configuration + PB10 ------> I2C2_SCL + PB11 ------> I2C2_SDA + */ + HAL_GPIO_DeInit(INTERNAL_I2C2_SCL_GPIO_Port, INTERNAL_I2C2_SCL_Pin); + + HAL_GPIO_DeInit(INTERNAL_I2C2_SDA_GPIO_Port, INTERNAL_I2C2_SDA_Pin); + + /* USER CODE BEGIN I2C2_MspDeInit 1 */ + + /* USER CODE END I2C2_MspDeInit 1 */ + } + +} + +/** + * @brief QSPI MSP Initialization + * This function configures the hardware resources used in this example + * @param hqspi: QSPI handle pointer + * @retval None + */ +void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspInit 0 */ + + /* USER CODE END QUADSPI_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_QSPI_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + /**QUADSPI GPIO Configuration + PE10 ------> QUADSPI_CLK + PE11 ------> QUADSPI_NCS + PE12 ------> QUADSPI_BK1_IO0 + PE13 ------> QUADSPI_BK1_IO1 + PE14 ------> QUADSPI_BK1_IO2 + PE15 ------> QUADSPI_BK1_IO3 + */ + GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin + |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /* USER CODE BEGIN QUADSPI_MspInit 1 */ + + /* USER CODE END QUADSPI_MspInit 1 */ + + } + +} + +/** + * @brief QSPI MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hqspi: QSPI handle pointer + * @retval None + */ +void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) +{ + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ + + /* USER CODE END QUADSPI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_QSPI_CLK_DISABLE(); + + /**QUADSPI GPIO Configuration + PE10 ------> QUADSPI_CLK + PE11 ------> QUADSPI_NCS + PE12 ------> QUADSPI_BK1_IO0 + PE13 ------> QUADSPI_BK1_IO1 + PE14 ------> QUADSPI_BK1_IO2 + PE15 ------> QUADSPI_BK1_IO3 + */ + HAL_GPIO_DeInit(GPIOE, QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin + |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin); + + /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + + /* USER CODE END QUADSPI_MspDeInit 1 */ + } + +} + +/** + * @brief SPI MSP Initialization + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspInit 0 */ + + /* USER CODE END SPI3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI3_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**SPI3 GPIO Configuration + PC10 ------> SPI3_SCK + PC11 ------> SPI3_MISO + PC12 ------> SPI3_MOSI + */ + GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + + } + +} + +/** + * @brief SPI MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspDeInit 0 */ + + /* USER CODE END SPI3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI3_CLK_DISABLE(); + + /**SPI3 GPIO Configuration + PC10 ------> SPI3_SCK + PC11 ------> SPI3_MISO + PC12 ------> SPI3_MOSI + */ + HAL_GPIO_DeInit(GPIOC, INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin); + + /* USER CODE BEGIN SPI3_MspDeInit 1 */ + + /* USER CODE END SPI3_MspDeInit 1 */ + } + +} + +/** + * @brief UART MSP Initialization + * This function configures the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART1 GPIO Configuration + PB6 ------> USART1_TX + PB7 ------> USART1_RX + */ + GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** + * @brief UART MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PB6 ------> USART1_TX + PB7 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOB, ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOD, INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/** + * @brief PCD MSP Initialization + * This function configures the hardware resources used in this example + * @param hpcd: PCD handle pointer + * @retval None + */ +void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hpcd->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; + PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + PeriphClkInit.PLLSAI1.PLLSAI1N = 24; + PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USB_OTG_FS GPIO Configuration + PA9 ------> USB_OTG_FS_VBUS + PA10 ------> USB_OTG_FS_ID + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + + /* Enable VDDUSB */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_EnableVddUSB(); + __HAL_RCC_PWR_CLK_DISABLE(); + } + else + { + HAL_PWREx_EnableVddUSB(); + } + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + + } + +} + +/** + * @brief PCD MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hpcd: PCD handle pointer + * @retval None + */ +void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) +{ + if(hpcd->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + + /**USB_OTG_FS GPIO Configuration + PA9 ------> USB_OTG_FS_VBUS + PA10 ------> USB_OTG_FS_ID + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + HAL_GPIO_DeInit(GPIOA, USB_OTG_FS_VBUS_Pin|USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin); + + /* Disable VDDUSB */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_DisableVddUSB(); + __HAL_RCC_PWR_CLK_DISABLE(); + } + else + { + HAL_PWREx_DisableVddUSB(); + } + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/P1_SETR2/Core/Src/stm32l4xx_it.c b/P1_SETR2/Core/Src/stm32l4xx_it.c new file mode 100644 index 0000000..8856471 --- /dev/null +++ b/P1_SETR2/Core/Src/stm32l4xx_it.c @@ -0,0 +1,238 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32l4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32L4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32l4xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles EXTI line[9:5] interrupts. + */ +void EXTI9_5_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI9_5_IRQn 0 */ + + /* USER CODE END EXTI9_5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(SPSGRF_915_GPIO3_EXTI5_Pin); + HAL_GPIO_EXTI_IRQHandler(SPBTLE_RF_IRQ_EXTI6_Pin); + HAL_GPIO_EXTI_IRQHandler(VL53L0X_GPIO1_EXTI7_Pin); + HAL_GPIO_EXTI_IRQHandler(LSM3MDL_DRDY_EXTI8_Pin); + /* USER CODE BEGIN EXTI9_5_IRQn 1 */ + + /* USER CODE END EXTI9_5_IRQn 1 */ +} + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(LPS22HB_INT_DRDY_EXTI0_Pin); + HAL_GPIO_EXTI_IRQHandler(LSM6DSL_INT1_EXTI11_Pin); + HAL_GPIO_EXTI_IRQHandler(BUTTON_EXTI13_Pin); + HAL_GPIO_EXTI_IRQHandler(ARD_D2_Pin); + HAL_GPIO_EXTI_IRQHandler(HTS221_DRDY_EXTI15_Pin); + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/P1_SETR2/Core/Src/syscalls.c b/P1_SETR2/Core/Src/syscalls.c new file mode 100644 index 0000000..8884b5a --- /dev/null +++ b/P1_SETR2/Core/Src/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/P1_SETR2/Core/Src/sysmem.c b/P1_SETR2/Core/Src/sysmem.c new file mode 100644 index 0000000..5d9f7e6 --- /dev/null +++ b/P1_SETR2/Core/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/P1_SETR2/Core/Src/system_stm32l4xx.c b/P1_SETR2/Core/Src/system_stm32l4xx.c new file mode 100644 index 0000000..be9cfee --- /dev/null +++ b/P1_SETR2/Core/Src/system_stm32l4xx.c @@ -0,0 +1,332 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * PLLSAI1_P | NA + *----------------------------------------------------------------------------- + * PLLSAI1_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI1_R | NA + *----------------------------------------------------------------------------- + * PLLSAI2_P | NA + *----------------------------------------------------------------------------- + * PLLSAI2_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI2_R | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** @addtogroup STM32L4xx_System_Private_Includes + * @{ + */ + +#include "stm32l4xx.h" + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ + +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ + 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ +#if defined(USER_VECT_TAB_ADDRESS) + /* Configure the Vector Table location -------------------------------------*/ + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr; + + /* Get MSI Range frequency--------------------------------------------------*/ + if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U) + { /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; + + switch (pllsource) + { + case 0x02: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = (msirange / pllm); + break; + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/P1_SETR2/Core/Startup/startup_stm32l475vgtx.s b/P1_SETR2/Core/Startup/startup_stm32l475vgtx.s new file mode 100644 index 0000000..f00efcf --- /dev/null +++ b/P1_SETR2/Core/Startup/startup_stm32l475vgtx.s @@ -0,0 +1,508 @@ +/** + ****************************************************************************** + * @file startup_stm32l475xx.s + * @author MCD Application Team + * @brief STM32L475xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word DFSDM1_FLT3_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word SDMMC1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DFSDM1_FLT0_IRQHandler + .word DFSDM1_FLT1_IRQHandler + .word DFSDM1_FLT2_IRQHandler + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word OTG_FS_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word SAI2_IRQHandler + .word SWPMI1_IRQHandler + .word TSC_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + diff --git a/P1_SETR2/Debug/Core/Src/joystick.cyclo b/P1_SETR2/Debug/Core/Src/joystick.cyclo new file mode 100644 index 0000000..72c89c3 --- /dev/null +++ b/P1_SETR2/Debug/Core/Src/joystick.cyclo @@ -0,0 +1 @@ +../Core/Src/joystick.c:13:9:ReadJoy 5 diff --git a/P1_SETR2/Debug/Core/Src/joystick.d b/P1_SETR2/Debug/Core/Src/joystick.d new file mode 100644 index 0000000..ab95782 --- /dev/null +++ b/P1_SETR2/Debug/Core/Src/joystick.d @@ -0,0 +1,72 @@ +Core/Src/joystick.o: ../Core/Src/joystick.c ../Core/Inc/joystick_driver.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Core/Inc/joystick_driver.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/P1_SETR2/Debug/Core/Src/joystick.o b/P1_SETR2/Debug/Core/Src/joystick.o new file mode 100644 index 0000000000000000000000000000000000000000..52ef4bdfecf03e3d8d9411c8783b622c8ece0370 GIT binary patch literal 1281164 zcmY&=2V7J~)bIA)d-rbdi{033)R@?k7+dT$mZ;IFu_e}M)FdW=BBCM+(i9b`N>dc6 zf&~OYKv7VN^r`|jM8Wp{hw#1kJ$`y;=FBPob8eeCGk5=;Fl{2A&*%NmAD`Eo_y1Zv zUcfdTb%}?yG4$qn^Ss*nN1;6$|A}`D{(s$G{|4o^?e(!JziY3LLpi>^J^|&#_WC50 z-?!H%qny%SpNeu?dwn{}8SV9%C}*|TXQQ0cUZ0C{UVHrql=Iu`3s5d>uP;LRV|#ru z$|ddfr6_-DuP;NnyuJQ2$`$SPl_*!W*MC8|y1l*z<=Xc8I+W|%>%XG>t-Zbh<;M2< zCX}1o>swH6ZLj~1a$9?SJIX)W>pM{HY_IP^`Dc6mFO+|`*LS1*r@j6!O566j9ZLK5 z`W}>f+v^S}_qEp@QSNWAJE1(#UO$NPPB_a?PdE5yz?`gc(Zlie|q!rlW^j@ zEt;t|JNf-oIq!Dy`f)ibY7H&CsF-Tq%%LvoCn#X2^1E3#OQ*csrQ1wgf*dh=cxAlq z=83W|6DQgx@?>q70j%(NpKwu$d3+JonO_Dec^x-)QY@dW9g zi+F;5X1Wmhd|A9o&f^Qj|MUUzt86(>Fv3EY0bd~9cw;Tg6IezuJi$y0odmu} z8hlE?*9(j0F+6Kq-7MU_lH=L5)jNpBPMpK*AXoxZT}0o_nZxVYM(-^= z(2K|G)K>4$c^2$a(BB;uPY*6K4j&=l|DMZxXURaWB4(wB+NztnJ`Syc*HZ zAZQt91&^;_NQVB}?kXQ~OPGYGA|b(1T=V?TcyjsIa-kA!BTuLtDIX;tA)kzAkr1ar zIkKy0lz2o}&1BtIavo0vlI;H{;dw<|d`NXwPu2;{I6GhPNM70-Jslt=6SuV)4Znv{ z2TL}}A50p)+O*5W#72<=SN7;@K45VKr;(sld zqxv6YVpR|1e`9I$0X)4dlXaslMAoR_BZ+ALZ$EsbehptM`PTfm1<~n%|2Px)Yr7rV zY80{m`BR}HZts&4aTS_v0&OjvKA}t^X2jhkJfU1FHflX_xptKO*J&?c#QH5)5L6ph zY#f1`OxRKWUzZ!Mdr~J1;B(?GQ+}24gxwTEMk!{aqJ=ymClE_|y=D=2mDsraFit=R zbsPVGQtd~fLh~O{s1*M1Ua>;UiFhL6H`@P275edYV(XA-IZrrT{~x^_g1^e}Ut4Ue zR;qF33Iq8@ap$;xa^C+oC-fCaMIvD*(|^pu&gTE6ystRYhop4y#tE~ntz5gSLgs#Fq?Y$AgzW?=p z6!#Mw?#$!!;P?$;|Nn?B+<oQ%6qw<{sNAGzu93#II;Mgxt zjAOwqsz(VK9BT*iaf~=G$1$0a;Ao5ML(JQez~T5hj_MlRB+xkyj|kq+-_g;hh%}4c zN!zJ;bnJPYj_>U0I9-DW1kdD4V0!l@{^x0=?SL;KaaEI*>Ixx_yH3!tyA9F%2NJzC zh%~!7kcLoR8~)40GpdLv!;GYJ)uA^17#xUs#|lZaHkUZ3|3lVOrjfS2;|Tes1mgT- z82Q-Wjr3g{QqEjsK2Q`rXPRFQs z@G+_vuyhR55YMiTg!97z(lF9O+D`W&soV|}=j`5ewC_xmajQwna~kp7@gw|i9H=*C z2kCj;hfvKfpx$v4sUCHac&?ozsheL@JngQM7ju52-l@+?Hm)sV{2Jm+!L2Cf70)Jq z;S}=XOAoU9=X2s;wv?=F4X5a}^dvpwMo`3>1%!X_E21Yxwt4M9y-iVcoEb}$m=dZF zm`vKb%q9Nxb!6+}7j%s6K$Hvf387;x@%+&ihnsj5hRQJU=iRL&m8l}@ zE9Vimy$i@|g&ld}ZK5OZAmR6MAlX-&=y>)CA?)}Q={!_Qy=Ava+pgWDZRTBy#;&&5 z`hQQ_ekmi&*Tzuq!#4Vj-lXTjY&s@=M^+9`Ck@Bi>hGOM1G9j`o zc&?ozJ$ZR#YyL^(vUBE+pfKh7@mlE z`mc%ZJcML_u_rvbNmRc*ihOB(MtTl9(s_(uK?tkyj>9wI9m!s4dxkv0ARc#zJ<-F8 z$l`(T$qSEra#N|$xSv-~|BdyS#v z?-Sbi8wi#9Epa-9lh>MA@j~$Ol&u|JQSg=kuk6u-69S8P}2U9IYe# zt1*y=k9Bk$S3x?N2NbdEF2rwJNBke+iSq65q-|$C$=*mOdQAh>drl;a5iKMu-a)YNYqehWt zmu-Y0Q%0Nz%LuvENcG_p$kxh8((m6)^t^Q9kM<&MW7ZQr(22C&%P0O7ZBMr9I|`nJ zcULOGG2sk{qo_ai{yq`&37(`@gyX>RERLZ#j}l(bMTAy4mFV-~orKr42X_L`8$`1IoO% zx6EQAMSfH$+4XRsx~GCX8a{(GyV;TzshNELZ8iCOauOX6PbGT8X_B)4i}c@(CrXQ$ za4vSkJdrnZIpO47q&SW&pr}R-rFv8e@yiwx=bjuo3p*DO<}c$(^T&>4y)T}165fpA zM6cRNvg@YO(H>(S3Gdz#!r24Yzl7(8@uY+|>nPD<=abY5Ji{ft2TRCGqKf>Lv|Tgn zZ<1!`v*g#CITVfl3c88}(=aolajj+GKcMzRhnEQdK|`?uelFdYg?#x=Xer`{lpxlR_>lu4P|V*?&-@bpzctWV z%HJS|pJn{8?r4?s&(iz8g8$<+XsP5cBkNWC=nb$}%|B0Lx*GobB&e?CFIWpLb^OZH zXg%iZcf-&V{t`VrddeT#2%Po&wN0?sz+XnstVVugS15bN|K%o#&-rD@I*4EJjrUQs z@<%LeyIyhP=3*W%9`y`s2=py zC_ouJ!ic`lb0>g4r04`39y$?^`8Gb0_(y1x*e(D9DPsfx*|S%mFi%G!*Fc)O9=?Qg z*n1N)f|C7w5uHgVeq|FbLTCQQW}M~2{HQwIa4!52TCgAC5C00czCV8xGCDZRcQMHm z+X=dNLogf#!Josri=ZRYdSXvOwh8F`1bMA!1qqz~L@P{CmIvTh1aFY|5oZeKZG~Kk z;9v{`9{f|yc85vpfM_sv^$LaVL8+%fAJa1*9?acy8YgLkeL0SY__H@6U_t!W5m0f3 zU;hlPZ2sBdN}i;N?^}#q87XA<+d-jvsvIu#n?@O+{=4yfl?>QhiaTqda1K&ogDBA@ z8QlCF^v}0!2j`F4QbI;?ydy%u1;;_&1UkC;Pm^^w)| z<{u~b1LqWDBqB3sgg5w?<|Kn>t(yUQwm1s_bmw4X#l&{}&X3{Se*P>aB;5FiXF;te ze|<6Z`tc7Gq6p`oUISt@zw3IOnOJ@s_BehU_;`LB`UHL({44x6{E2)5ExEyO^COv0 zj{Fw_>-Vr_h(}^TZ27Y*jy5Bo0d&_16#&;Gr3umOrCWfA573;#@$;3D5F9#%u9*>z zk3ktTgihf%%`~wcUqdg5$+u}*G2@#wz@PisP~@p7*rvTN;d;l}!%*)&Wdm&Vv5CR) z3&|v$gm1E%K%X2;Q?=ey|YF|Gfvar10P6 z!ta}Whx-7S%6ILF)0NA=Pvg@({^MRK9`Jilgm?|VCg^djKsZ zf?Np%Dg@OnaJokDx)%cSRM4~@J~RtfCZJ_2j7Wu?gRt%$!gEO2ml6!l!bwO~h`of~ z$n1!{g}zHEkiyG(Xax!#UExEdFx3|RT@;=|dR=^7I2buX@eSeJneC6LE-_A!>Hcje z96y`<0_c0>-EV&&eOELE8pid_g{kpRra*8KKLV6BH;1=BXsm0};C-L#>)}NIvmbCA zG`RY3*Y`4ke(bdMuroesCpf2ddjZP4`wMYga*bv) zt5$yp_`e;yfcmC!dlBocQ{CXg_H)z06T}bPgN_jXiXVX|f`6_YsxI=~;(Z89zy~__!i$rGLc$g`@Oe3V^e;YA*WRrISVil#euFG<{o`M8=n|TS|R6yBr!B=^}b3)*ND^Pq=@RbvE zo)WB30G6*noebg`L5FH^`U|{%fyV)Y&z}I~Wx+4kVK!Ru?lUOM5eP%kx+my)4i<6+ z=V)q|CnyymHV*~)7)6Qm1x>+FRw!8dn7|8y>FO;Ow9v%9L@+@D&N6{84n?_O$VkAg z6ue7Ct4c74=JGXy83I_Z6@0rF9z7N$7eVfcAh8z=)e8nsgY^c%;#t6AE6jO~K0D#C z)#%$JJVY1RUSZc=5Z@;}i}#J#QRr0%;#r~Ndtf;y>_aE$o^WRa`tA#JcEetta1&Pd(!PyA`HV?lDJfO<1LB`A=8z>3wz#1t6Df} z1>|akifAaS6B>HJ>BqvEQvvs>a2OT!!tcp?qi~P_W}gXycCY^3zjBf zEZwB9g_~%W|3+xPACA2hewqW-t-@O5QN{0s6?8Ft5SpuSHa`k)&@0bQ6t@d4dr|y+ z$T^6LX2beE(Uw%$+beT9~AjJ;=~;iO`-?eVUhJHl(~ow=R@wOXzfIB zx{7`|2rS1$DfiHF7frK4pQk8Lfx=5P;}eJ{L_@ox>ChB5edxDa#OT>G>SA)9SvA-iCn$_XNG9}O|)){RyD&ymPkkm zqHIwoSG4YmJnf(*N0g;NulQNl) zM9L}@#iHb&prusQ{~C~$iHwP0sT7qoLQ9n>_!x>B(arbhs};Rp2`!IBlI|cr5jlTE z(I9Hd1hG++wFlll7u`(<@rCHwTBv>{%HIs|O`>mA0N5;=?T@}UBDaoE)*>2r3w^Dk zfCUhLFUk%^6KzD-q!?iJF$ZWa(l$x&f{X(E6)4^$o7ecUO^xo#ak~z&PjZJ z7~~F!*RDo*4vCW%g40=?IuIVYh_|`J&=K*ge<0^7?$H56H}THiFzX>6-Uk*u#hX}& zdy5_VgLqv0!#Sw-5eu?FJSlb@1M$;hjRC5C#q*q?+D|NA137>3Q;Ke&_;*U?1&N1} zz&Y{L)i4wyen4}wFmVD_gvH_FyHe;pFFs4tz6)Z0CFCxNH*SHwDDnL`cpEL=`Xlbt z7_rL@0E`oNpfpvySVFVNE8_cNa3+cm9fbH*F>?^suZiDXfZRiI@qV=O#j~!WRV1EY z3e}Iq{V6L@BAzlBeWl`27KoRNxpatEh<~I^dzF~sV5nMLQwNq>@$*w)sS__Xqt8~7 zE=OS}5zc_X9!U_5#P>=n3Cli7Un2w@B{lS_aFW>5DCvO2k0w3Nl97}`IxJc7JA6MX z$-^qP*i};e1H$7j>AnsE9+Le>fzwN3!eWisTXOdqSWZa(p){9|qz6SQOHx{iR<`8V zCE(1Fj1$7%J;|%1h;FV#KLrALl3_Q|dMNqx6=Iz)vC??GP$C|WR*_`bD)?S3Dbt}< zBH6MPMVVyq3fL=`Oj!uHm6CwRuuvsg{2or%NIZt1RVzvV4sJe{ObiF-6G^8xFw`J9 zS_nvuk_DJ6i=Rsl&j9BONysH=c_q0)w{MdqBaW^R=}{v3O0#+*1b$NESU~cZW)uNu zpi~zDAA+P!V}a$YG$aqLbJDTCP!=lf^8^;cq!}$h9U%>%WtQ{O74Oj(DgB$42QEsx zKLSgX^de2UE=!-U05L`?UIxxs=}^k!#Y?06p)WzYh}KvVrE^>%kR*LK4XtZZKT2j_ zm(Iw5N6Avxec()y{zhjrRT{M&MVi#(7C6(TFPqTHkba^ZY^GE&16s1ANBY9eJJP?g zeva$dLxjG2(%;9!?0xC`FkpEgUE__`Luq##pe~e37o#YW#?fk1i8N*aye*YZ$^&PG zbix-1NTqbuC}63PE-gb?Yo#4}faQsF*NDf8Tb;+Cvs5VWMrzHWuL zw`HOjsLqrvkiq&LS@pk=yDRfJ1|ROr=F?CySJtZwz(0`n&jQOsSCi^%7eHF5#=@74!MRNdHE#rTSR*h`(Li9bB&9tYG z%W57$yk5q;h*pEF^%unDxh(54iWjmTX1MuEX4e5MO|l}oBAaE&w4C@xR#1e#7Fkyb zidNZ8KES`1B~ONh53;`kf%B7W>IE3GWeUzgnLYC_&2;xLPv^n0eM~P;$T>1qS7FwP z34aHc1I&>h(C5r-dxl^gX8Kovc$A5K2o_gncW;!2i#_|=~n|DqN$7jUR7xTKn#uYN0GpXA zN{zo|q-Vg=!lXWd+&iX#uFv<(DoTcZWO_dW%O_?tEiT!yHZd?{&%SGh_+FOn2ssBf z)g5wWdEe$NIp9`1bu~U8LeLyvA-rmyqG!aU4x{pxQyimB7)`Y$IVby$^JGU0#)n=>~s;=uy-fIP%S$Y$yV_bHt-ILr)&pW z$Y@}Nw9e7U%99b~=WJvrv|g}2=b`fzyZv{FH?e(x2JtQ1{0FeKu+34hepG&U44ihA zXV5iqOs=tl#a%wuf_Qq$zX^nDFZsq=h#!{^&jHR8@{P0%b5b5j$)!{BugAcGulz7Q z8P3S}(OBPKt~(340QrV+U@WsF3#{Elu);ec<$a`E~~2ow%5X5IDenTmeW2xq-;S ziw|+3vC!$v4JifjFn6Aks4iTe*^oQJt(|~AS8n_bfN<;`t40!ThwK{`;MS7}Gkd(U44TYbDm=X$JJ|gAg)~tK=HEODXkq+o zbp9gw`}VhIEQ5uTufhFLX3T+XzHB?KpcTk^(`dX<*1H(QBH1oGv>wU2E=H?Z_GUET zmdFMbfwNRLgciWcWi@q(NQG>klum-oIRFAxvK~X>aIMUfCdGBKoD;a@p2%wHMtLf$ zyn>=Z_DvG-Jd^dMncXYdCU3|!$($+W_*zy?acP!?kg~V3jkH4FBD+KB-&WZvBl_OS zhNJ<~d)dct5U&riMGClT%k;H@PCMpI69nuTV{CE?hl{s-0$lRFgx6pTtN&O8icV;4Jol@Ajz71n*37+Uo?!+h`n(T_Pu;qhmTe?UBd=}51bKt{3-EJ2J*9qa`& zT^6J7Ec2@dkj^m&wU7&8uG3D*P{#i_iZCW+8d$=aH4z9w1T(ZVLU*27K#%nc%&4yr z-AKm%FQ~rAIE@DCOH9Zu^hGfOnwDN>+y^G)Bz*Y9{A7k|TUOc) zzT2_81HfX>e!LFxJ#6rCTqt|lL4Uvp2lgaA8uqdO{0;Dq?2sp5+0PD3hB7C1!d%E5 zV2|{I7H9Ta7E~W*ok}6+!lqCf*pr<`yPUjO0j1KsS(|F8#x+CZloRYFdS?5u*}uZV zNp=$@-A=K7uc7QTdzkj*`LaAmu$*B96f-|IxHGK#vvxF?4`9bnLth|!ns&tnu>;>B zX2ERF7T7z>PM8OP=h(iBP=v7ED8(4c-k_C+Fjn#i;^A!G@30WT2E_oS&Zh?w80>jb=HCy$L{X~Wby3eZP1y( zUd5(XjP1&M081h}9!u@wB(TByRaQ;o;cKjE2rOJ@=ih*`8*B;XN0V8n0w7Caca?zo zCOhyt{7Yp;*rAExUmenB~y`)n4y4szMul%URItCzsu12%~kN*}U(8h;nC z3uxJ*kkw8Hv4|ag4%Q#B9m0X7nC(^ooh9s_KLblCdx@qzWo(}<;4Ei{g@L7lwf6zQ zO7{CZz*5CNu7N-`YezcJHSF8_(u8FPGf#o%8zZKS-+4*$iy*X!mWgLok?7hF?*n9SKIx!#ES^0DE~gjRGCy z8|W18lWSse`W@w`D5Je!zJhjAzx>8GDB|VooxzeQ-}(ovC&^FJ!q!#!bK1gj zO)h6bg@b~1^gV4G! z??Y+JT=|<%2y&i$!3f}dAV1d+t%vfC%V8m3K2L|DKpstR%0jv9KKhE}Dw+p9lAE8x zP_aD!XB1`fr$j85PrHX!g`6J?xk~x5NPwAQbmKc4{`b|Q;q^lv)uR&THeUl&_<@W@@P-6w8(G0hDWXPJle(a zPX3hU>F?#6Xu0Tv{9hXMeU$sAg5{I^PugB*%k5tSEqk~+T3y}CElY%12k!P+gnS=Y z-v zE)E|PVKg2;7v7%Y7S-T9oaUmZg6PZHQC9a1x4aqxe%#o1TKLlqKVuO zS?EjRQs|}aRuDe?Eq28Z7u+@h&%cUMKNbFLZF1ZM;m-fxq(_J zE91f}5Gd!gzrbDv*PE8#syGi?QL5%bXm(S>rJX>lma`3pD|KAy4B&jsje88UPdJAu z5O~V*egI27C;5b;fpff!zDDjYA0c?gaW|mlIXBxEA%DTe4}$fV+-4nO_KK^bMW-eX zNgmuC-0e&Vyy15K2+p_MvawLs!ri1@wym6399Z6QV~bI|=ek8h%Li^M<%U0UOQyqH zTZM0bcx0#eP>YtmLU0D04vIar#ciKr1I@l26^CfM>3)SRJ*=D*b+j6KKvB>DfQJ;t zQ(@0pF^lGThZQecVZlYwbuyejqKID#mZOTF8d10@TpywDn4%{=p4=6^@oA9QL-9!p z)t(ApHwbtssy;xAw_?IW2%J#tDuZ<&MffH-c2aRN5X4i8F*iUwt$0q$puUP(uW$nV z6^X@w8=!bI9IZgbUV5SgDb|W17pxfO0peN3bbqK0Q3UURp-{z_43vc_G7iAoaK)ly zC?XWI{{iv5qACo^A{8-|AHAs95`fkv#jgSsQHr%@uv}I=EQ3I_B7;tNtfHwCAjK&> zX<0p9G5-*vl%SB)(&H6H>nmtURQ$RNeODF5wAgq}@p%%oTvrr-0KglHZnViXS<#8! zBq@r)l&VNocp9NIO(9s0Sl?3oO>s$Abj8e0oS_Jfg1~J>T^E4JQk?o0EZK^Z9gw@D z;BSZAT}4YQ+{{r7xCMcGioC%9k*oOC76N&SssOYeD5lZy?xEtrw>Sa$if>Otpg>Vo z4iH6(zBD3xr1+&L3>7Q+yB0qQb^h&HKLD6ArAsZ^NOp{P>0(_5`t zkw9x6H460(2-GTMv^nRA;&+R|7MV)T~? z-AlzqJ~&?~ex&8FCIy~exY!jPj=_4f!qOA1w~Fsnh-ZspHf=#~RYZkC;GN=G42t)P z)pG#igJRj&u<%LYu@J~?mGiry&raEw)+g+h>9e6_k8)QXT-mF9LFub~$_=!j;i!Dt z43_;$-35p{Dfj6C;(&6PJ?tG+Ufl#O&dO`FFn?G%WE@&9%8XXX9Z@ngvO209Zh^P1 z$}l-B98-R?1pc`zU1)LIL-|!aVg>3s5?Zgg~J3pEJN2q&zQzx53KgJP<>a ziJQR^s%)Uyb(nG~4Ismn#~E-&C_^HF<-9WUGFlgu{P1?q0C<8LMwZFRJVHou7m0gzCsi4Q%$AtII6<*5ZJGBUy0B; zsmfTWKA>`-YvQ14`wSF^RN_Rqa#-~PZDe;*EhvWXM^uTFFF2~orstrmYWjJAa8s3; zVCa}Cl+uXqs)w}U#8Y*OvLjw9%ML*DR{8b?=W*5eLWrMG`O(bON9A=7I!~$&H$&i* z>ev?O^i{nY4lQR?xiYxvr*fy$=&#z=0j&Vlngj?0syu0_B}f(c6n()edmTIqQLUzH zB2@L;TX+Ke>en^RUUx=aZ?pA2s%?$Rd2zPruvJvdfrk+ra?Si^?oKC z%TSH;KqPLfF2_P3QzgiPK(@-6uCqI;9rlRlT~#wZ(sNXef5P59Rd+oM-B%qM24b%2 zSq%j8RMH2qkgt+ZroTXS`yS*9RZVYUp-6R;hB%K@qv*4aVwLS)_)wynJq9>SReNYB zS-I*OO=T-oYdS!@Qe`t5oK>ptTX7z$RsT}9qDB>m@1w=Fsu=o2p-vUP9`>H7a%t`G zsY*yMje3rfs!2|ed#%z2 z0bsLg!U?$YMrBJ+qPMD-BVnOMRqYCaR@DI7mG)lMcMX(%Q03%8*+*3qrD#5>)={$D zR_)LgaP8C?G!M5|+tbu}kJ{xVwCqzCdqRt&`te8f?N|5s7QQ>F<7ivQ0rfUoUplD1 zR1e1vsek(pea`A^AN0AX=cS|Xh2iARbdYQVP*sok7b* z9_rf*A?~g2Pp_rp>Y?+{cS5};3oRe@r^^sHsTTAG+*9ghwAbpi`gjn``l@Zdhev1B z>9lLfPd&Xm-1Ju~vrz=7V|}4BP`&S4^aZJx(f+1j^#l4~;jDTmot1OyYikgR5cTi# z&@8MP&d#%v-9e!bZcKw4~c{;k?OB#I&e`PzaGRWbx$dXm(`1U!%(z(QVA@? zs3W?7C04zQ-hXlG@stgXS65y{aYcQSRxT6O6TSraB=zMqfWNAaP{Qmr^+lTI-cWbm z4Y_1>0Bs9MQP=jsNxiB5^9ck})h8)DY3lS-2*@pU%p#ypSFiX4mfPwi$}487JD6c1 zOI=30h_cn%Bj~%Mu2=&@ch%09AfBU^rvczSb&sv+%T+I;ts8mjQ?z;Tf%=dQI3KES z(3me@ok>Z`0`&me#ayT!PZ^~mbuLyL#l>n74M$4Ur)2<9s*YL)on>m5D=5m<6E6a8 zh588%dn?sq76Mi3uLr_r24ZS=ONSMQ}Ot3e&u z6#|Xw>)p|Mrrt>ltejt0J9v%s0 zZ`JwR!P27MPkZNE)!TN0<(<0ecf|U=dMai4Kd4`5ul^SZzWp$HNF%&C(YDFARf@9(q|M0HKXWpe@Nrq9pIfcv*|iJ ztm#P`w_G&Ro(TC7%_2&!9MvonLe5oFb_s=>X7EM?#9h;!-i98UYWnELQzN8VtCwc) z8VGo6TxnC#am|!TXr0iU=m$eSnhP{jJf-P40$5IKg1&=*uco9gi2jyIjc#g_rp2OrqSRG(G<-=D^xRM0xX1S_S54qToc|AW+OCy zeQ^TLYxdp&&I_8}G{=k7jF|xtmo&;KcpIf@psd(s&8-v=qctAuAP}PoT@KDz&381? ziPQ8L0z>f{p%N$Oie~kG7)sP^v_~sRvyB$!uWQt4Al}f-oQ^9iStI%ds#7#Y?hwDJ zIq(*$Q#I4*Do@i4dI7k%G%1w7PS^bGhE|4V{bbm?t(oBkVy1?n9Y0x`ziH&3t(pA@ zs_$s_QA#LB^Kd&X+|x)haB1Avd`|=UT+OaYa5_(Ox()&lG+Vq;Jk%89Q+RQ{rk4Q% zg_?XCZ5L@`{Sekin)=6xXQ{?WA3~LBTqV#_uFZD1@|?6l7>0JXjLjyL4?XrDX- zvc1}eu0ZCXHBrKCpLQVKe@@zU>tN`Bb|+nR2eo@uh|3{uw@7Gl)=I4)9@d`u5?Wle z@2{cnh&Fl_R3Ftwe-0m9wLaGX-c38O1dxttGbpv=uGP_S%R{U213*u0<1!Rp+F`Wi z+FSc4c1eqmYYW_=?1VNm0m@EkgMR{+)7sA{-{Y&j;sJp(+B7c|e%gF5gxp{IXcIUC zw116;c%W7`7~(nrBy-@9gi|{>6d)@~gg==o^pdT=IcRTfxC(r)sDg{#`<^y$bo?ewt_xUL=a8(3~= ztB?>8Cu_g?2d<=OXU77>O)Yl;tyFEi79mK}ei{ayx3mf8Aa`5)1r0JXwP`fI&eDEQ z*JrkNEv>BI(R$Nlx@>e_AIU009kr+7-zUa-yYo;G~C*&bEd)iK3yoyt{rug@T(N!{W>8FPAA>@6*xx+bfxrF z$w8fh7O@WLyuXAG&N_V#6O?xCg zb%ko6_R@V921wqzOg&o1b#o3v*$G|9ClGyfmsi5VN!?LfXgQ@z(nIxWokJ*)`ReLg z;oljZau34er*ozZmcQ=vQWOEY$-Q7bQ1`C^tsvd1UCzIv%1J7D9-76ZG`F& z-Tf`#4Am+B0i-b9Y1&a3uKV&Ra7O5E(f*3_y8Z@)=YlQ|FHUi!ZWrzTyQs^h>A)qO z2W=R-tmDz1#b}*38H&;Uy#UB!b$u#O#OapNQ!!rWwhQ(WbbfQux}y7gC0t3=U89wQ zBwak^6|d@STOfW-x8ns^uIpH5Sh%4ZHx-=8y5JXRrRWM<;L%MTzZFEf3hYa1XQNVdyXMPWXOx>b=;LOqu{2QUm*4fb-!yR25eamoHC!lO$ zj&Ao(fVig{o{7HuI(0bU=IZ+Y3?K4zyb6ft>p~xar9d}@ws05f7CYdYDAJAdf%qfc zE+<8)a@7wNL9M}9`LAIH~l-bYIMJx z1ZS?JlAd72p?YPG%^rh z=}!4Vu1WWq9Ie+n8C?atq?b9vy0d-@55&XzP+D|x(H9_*AtG+xKEN=Sz15kZT z?@cGpT|agQtb6DqY1!CQf65O!z4W#;T=v$--9~X-?@IfgPw2PKfw+%8ke(VR^`85I z<&@s}8CZPvvpPWTjNYv;%=+n{(Nx`EKbt0+0eXKL+6L-x(AR}Q`s=i@Fjz0z0JCTH zc@7Xirw^8+6{4@8+(oFqcrcWO=|^=(U${PJ2#68-qhF$RUhh!}Z!hSDbh$<9?P%Zg zMSWu^3?=CQ*$BBSdeapkOVsT~clulSl?`8~j2*Z)B)%Qy5t&<65k zz0!b~rRYa!5SN?!JPt*w-ho~kY5MxTkh`V-&59^;61&~ujsq4UqVa6xq8na6nXmJDE*zU ze-;dn3iQQFuoUWZdn1BHdfPvN?2$f*h7QI0$}Z?D(eH}^>QenSEzFkbH`0K-T;EJN zqze80)sU;y8wW#mm0m_4;8g3=#sW)?-t8;|YW3Y-qo~vOtA(=1dO!Ml;fa3CXy|;Z z_x&6=>-F2{LTS*KrUHDU{wta>JkxiJK|r4Cd(q1I3;kmk2)xwarIgoey38 z{>U5s6K}}9)o+~-mKME$fq1K4NOPxm`nZc|z1ROi-%)+gzpsL0AN7CG?{$3A`(WdR z*w*kBEp*r!`cowA4TFzBV2{D07mB@xqEWaM9SkkBRdS!fnvIsDVeNAGx8E?DQe{qt zGqm6DfT4x_J7_pth`vLHs#DPEY)GT+EQbwqUje6!A$vP;9x>detx87?e}_Qa)o}YM zINc20SK_Q3GYkku%iVCF=3^d)XBQ#vX}Cx`CcO+lP>$N$@HcG}J#L6DgSRIP6Y|mW zF?_!YW=|UAhv3*LgOQSrrwx5NLBQ9ra4f{n7;I?sj-Mf{D>(fPreyR57&6n*3NrMF zgj}#e>xP(}HK^(JdCuTPpOJMH&)6FzkH=xrc^kdiUoWcKi+11%_2=2v4EmZ%T(1 z8%|KpxWwRo0pg{G2pSrd8Jy_@-g1KveKA~Nh`a*MO2erfuv8ghdH{U2VapyAHHJy_ zLa8+{Vv#hYFN7&a`lF+^)TCD@c$W6YBU621?MwE34Ou( z+|c(pK)f*2S|Rt+@a6!_zA~(FgItqgGtEL?8!j&fXR{$I6~!BaIvi%-8U{7OLW^Mx ztpKzdI;@43cZM_F(Ry$2c?t_3423jS{Ah@yEqI>{S7`a(*7)rm5bcaxI-#&PUZh3H zJ;sA{Y3w!T(sG`IQR5CR`;7C75J4y7n>B!Rz}S)Az6Xth74Y_uab6rOI2%QJ5DyzS zO@z3MG5aG79Wi>-+RIVnY8I;9i~+B~a?H4u_Di`N|DdO$hw(#4_~2>G=OE{0%-M_mnN!9NjR0}l*o(gS@H4*u0D%6+dfI0dU_99!#6Y9l zaR>w%7tvTa*f?hoESxnKJcIZ-<8fLS4KX&;PRdZD`zPQGGYTnr6mI;m7jPqt)k`6M z-gtd9#4i}XUI5NWqbohkITn8TTn5ciA}94#a5V&vEc5##l-l@?wpP zM}Qb-6k#K(INmspQmYBZNZJK;#n^u;%w99P-2}^ZV-{t2ZWuqC0AjLnDJ^@X7~K+a zQg0fc2O$!vMlbsECe0|JQS&Y1DoP@x8xr-lqL14~vIjORb1RchQqd)mv4$Kz3y8(V12yTaJ3Gx{oxZzy?GW!!Nd%Bqc3 zWVXh*h#t+g#>-ov^NBH;eqQOR@fE#S>W%AsA<$slO!J&Z<0=URo*A=g=Jwq9H@$XW z7^`lB_|n+A2=-nX?{5WXlX3I`D0^*mr&Wx%#v88SY%y-12#;Eg7pvnF>fInoi{}(N1({x&}KWrM%6=q#bEPZBn#5AV@T8^5U zb3r_2I^GG^-A!x&EO?myrjfs=$$bFiyi7AG2jOjc`y9%Sn_6fde!|2YgjpX`1npBj zY1&Hfzf-2yG%i1FD(wXDex@ZGA>eQF{~o>vnC{rYl|a)on)C*l=4fFd*i>mnan`hU z1?0||4j%_gh^aG8<3mmL-y)DHL|nQ3ww4?|g|%Kl)0$m&ruL4 zGmS0-vE0;gF$5}1J1HAeX}W(Cu2h-4Xuwl#3ZxWUov9x^g&&*3c|iTdrqz9&u?l1$#p0 z8&fguczJ6Ic?@EUsg{1`rPVZp-i_}}UUOmLy=fEuoZ1IdFZ!(JqbcSF9J4bg&{)IX zyonZv_L!rSAh6fGq705Xm}T>zWuN(hEv!45Iogx4-+YEfl}_f4l<_=Z?tBLJ4w@4R zKs;prmfqnmW@j2_9Wl?D4M<1Lr#C>()%@xU5Z%m*Mij@)FEb$EZuZkdz{7lLA&_~R zr_zQQFSA<}PMo*-=nfE%oByWg#7T4XGRU1WC(Ca?sV&rXLA!RCtl(0SHeoD9c8%^tKZv;(p>i(ATFBU)64XdxtwxV(dK{XGrAb_HXd5B<`i1$i!<-~ z6D;v&H7$1~m>1Dk(^t$3>4r@-r_ko4By&GXbzU|5(CoZ;l*~U=^5^mFO!pPoeo{ky(+5v+~GX+yzCk z`S>6dCFalQ`BG|r8V|?H%K!_X(@tt%1Tr)KeZXsI_Z-vulUW)GUnG@3U)g1|GgoIX%_ zZeH&MxfkY%t>}Aco=bV?S7!Gxh&P!p^@ZGPbNOWmG@F-=M(d4vK?ZcbH7|aPqQ!iR z-iEE_DqD!ZGw0F>@V!}m4&ooo{ufbvG_N=W&QIn|w3uOQQEmomJ4**jMA}=z>6@-S zmR+OZ^j=F7?Im`!2*TmRe#^Gb(CK7Rr$gX?rD7zCgO+WRq3n>QGd*dYE#n?S;IQS) z&v3=X;ynq@a zUY0@h>hZSxKtDKn+>+!3)h8??Z$R9~(%cB&Pg<6ahn7>8zv<<6+H(C%aQa$Gicy@g zB!7Xz&+-S2U;HgOv!FA;a(D{_0xe4>%P1I1vJCzO{#~`W zP^$Wx<-R}syKZsHgU%b4<+Qmv*&>(;Ln)Ry^cnI^OQ9QDsg_4H_f4}5rI_8a9H4cX zbjzx1P@Q2pM5*fA7I#`;&b0W`HtZ}*_I&8fw%|9EaRXVtq^#{-OEoP|iKX@yI7=-!8M4)I#c zZd%{0vm|tb?~g5mYXIVjWyy00JhfP8Fk5fwK~ZY36g8r+(K2i?R6n!C({F)1x0J6( z>xIRx89HBDqB?@*mBqOneNC3J^o`?d%dhF^YqnIELD?Hi3N8D;wOpl7Kw2!fXic%z z@+0NT-&sZ!K>WRBAf@6zSO(I|^rI!2_Pc$uFqBBPwR+I{ik;Od4TZh6F$?kBV-2Jf z+g|HS`lU_>>-cmO`>e?+2&AKRI{ggpe(RL20O4d!6r(s`ZFU38L93G-77kg*UWYPg zYkk{CZr1bx=yS1Jrvlj#>vUS?JZiP2pItj<{mK{Kx?7`aLG-Y`p~AfInw#9RZyo);!t~5^4=w z2Gn8JRV8SJTbEjZCBo`O+j!4gx6#bzf^{anG$O4=Gl&Z01d6go(0RXX z<})vsVlu%;&h#1-o$7sw@A|Dlv#lJ(Xk z^j)=DXshQn>u_4&x^CT1lk*$aZ>B&?vUU1#*h{eRhGUu5RQhd)EUTWrp~|*CyaSzgtlterao0Mg1Xyyc zV_MLkq7*X&LaL^+X@2&bOY<1hK$6o}yc5HP8l~ zBI_jD+V;r$fifV)RuOF{E3x*Xk#VWjK*{$qYqJTha%+#j(5kSu(&uND*1nfeR9O@0 zhkdH8(e#|JvA%l`WVP0gH0r9e;%De^$658Xhv13Ti}I0At)p6Sa_X(;XgJbfwc7*` zjaCPmi$1e5sUSYLmU|;gFRc6KLGGos-&$ySWsQFb3(eMnFHpR(wrJtXTkC1sIo4wR zg4SqTt^R&E0q?A@r10Urb?s7U`CwJW1K>w%%nitWvW~wBfVMW0RZwkbv+oBK_BO7~ zAnvgVngJ|(Z64EJX$PBH6Xf>UM38Dno8krN+i&9&4tq{EpPd5B0h^&Euy@dA>(|h7 z$fmUev^d*5+Xb_SZCXko;9?V52k=L1`ZWR4Q5z2$=(^hUqiyYOHcLA~{FqH<7{uLe z8t8j`51ZRdVb;^elnVd6Y&Ov@Qg53|a{9Q<(Et!n*o=&aoR3Wx8giVp**OXVr)(VP zk$2kWLKs@UHpNo_;*8BudR_b3ocsx=!{27UJy-&4q`iSN&_+Z)1lc%_gw9}_-@XCP zvo_N!AaKrRFn!4zV)Kkfs-gdfqw9{#y6WPo4RhsaSkK;jPb)`h=4hDaNX@cLEp3+# z%a}3*QIHJ^g6t)-6&V5|2*{8PvK@#BvITv==l$z^?!D)n?>YB*p5O1@bI!dFV}jPS zaSYdskc($XS(uOn#_j+JBr!YpMR=tk#t##fgiSH`%12m8EhBhGED9%T2}$Bj~JWJWKJj2FBkMtZHN&eFLP4agrim&5Vtdb8BIU z=o4#Y%%gR|Eyi!Orfp;7{tF}88Lv`mql3Yx#6u^;_#sqxF}!JC)y=pjhg=Wi9)((N zGwgT3q&tk)sfP6~<2V&K-eUw!!z}eOx@bv!pAk>xU44urmeuy!`2g@+y;CUz;VN_Exag-7FEzrjpdp3b(obi-u z@+TP6?!vOij20&#Oft@Ifk#t}Iy)$P!gz}^;7=K;#{g@?e6t!lZJFG;5U^ujqB<*k z=9x#(>A-BDDrZOL3-qu$%4~~(WlqeGpM@4@rpxQl;=*K8+|8A_y#>mSF`LUE;KrPy zYj@n4w_k&u$C)2elH7xt{09V1FhAS`15Yx)qdO=)na37Erx$Y}JvB}-P4u1cX6{&q zP9Ns;E70;~hS>wpk9nmOK>o}Hqd*8?uA;X^AhVw;xq_I7mVqUhX{2cAX{MhTuxFSz z_Q9kO=2j}93}tTI50B0=_r$`8Fy>0CArEKPZiT=(CZ`ub5zNIOz|BbJ0XkJ1#k88i z8O@waiPRY8914xcGW~7=D31A(6>{;+U>#Zs%>URhH<7uq3@k~^IkW&d&+OccRxC6K9II@^IbW-9XGluRxy2Kn`0g}zks)o~- znGfhEn!|KE3-MfL{ZCMq$Eq$(%uZi&|zT6${ldUk?STXBK{mu?FVYN}x9~f1>j3 zCgx#^YBn=pp*&X$^Dxy)w=xT8@pX$iPVdb&rkY^enPzv$bug<;5a?tsrQlH)^Vh|I z?Pk`OW2}eiOSMh6nN~WCeuue*0$F#NBTpfIk6AJwa=lEOH(Fp4NmgaV(cbXvMRZ(FyGY*46jHlE~sxhB1k?>=3*?&zju>tCLwdwCcLR z${EI33Tyd4kV|DPrbuEMtAMt1>8x|<7|UQ?c0enW)j9_{vsfdP0l&zyIRn*~SVjt? zWwSnb4Xw+poAhhUVQm?KmR#22I&kK(%*_DGXB|!exx)JBYxq~dvIIe(kj0t>QpB2g z9Y9xEGsLj0m}OgxkK-C^>3OIwVacvRXDMqARl8niEv|xi8LOPC^vYQQHQ=mZ{S|<* z8?00=1S(k%CNNgT`sqy=QO!Dh9%D7EehZAh$r`4RP%UfuN5HFNE&Ua(de-NQ&}v}) zM`tt}S$zzUCf58pFt?fY3Z>{w0^$>7o`))>;K->6}Y|V@4^kmO|3F2OCZ3~<}#TIp< z)0=HG9p3t|M=8zX%PtB5@nio%dtZNc3+)C2*pAU4f$R-*@HU9OVKrES*(>PHe45=u z`S3Gr^Us*95ca|lkWlvcA;6wxf7$}PFm}{(;Dxhq#KEz1?02ZNG=eRmy>=w~ABy@# zu|w%m8O@%e^ zs*~AkXvKMf9ZFyC6!t-?-%VwwFNT3>>_{KXU^?4y8$cQC1yoa$$^PLdxS7RvJ^|Q^ z>=dfazQlIngEO1GH4Nl3JB2bhIqW6dpe&dDOb5{O*msMeC7-RN*vu7nIwdm-*yjoW zRLD-)1e1!`0rarC%6@?=Ws2E(C&6-!T}kDYCG1sH{#42~)`MJU$G!nl#*XoV@#XB! z88E4Wok0)W8|>Z=s3>9|G>d-YM6dy_rskFi?zt5jD~$NsJZ zWA*IqxgZVf7ZcIh$o{DluubeQr2uMXZ(5F43%ioGP;Kl!dysbajxkI@2YUytr8?QW z7+~pQSJD2qoBcH&m5o&w$wd+c|N4YSR9*g3*( zI1af{_ParV9b?yi4}o#^*7u-gg1t8ksvol*Y5g+ER(=dEQ|#_cj6Go=GT;Mv%Kr8N zwAgT7ps1}aM|2P^J5DGq{sH41ICCf!=E(Vg$}*2~Dw4tC#Ob^MAZN~S8EkRk z=xAH*$_ah|)yFs=`~_Gyj`=rqx^w)VhtK=mh7^6KFZfxkK+wPmWLo zJTH#*S0J3?B+#bNn`7DlP9M$@dRX~#Zqa=Dao+dEm_H}_2*d+8V<(_9kmJ~hi45Z8 z+y;6u=lN80p5`3>8|Y^^ThF2u!g=NMO+E$#( z&?7j}eo!6B;q*Z+inCS#H={Wl-UdqyXT>&dkTYQbE+sndzsThVeA~vby~&db5wOueT6eX0tKAd zEVK$ayan_dn3L&m0H(w*#0o7j`Jmj zdFwf{EGTQ>NasRJBj*E(TsCpu{0$~GbN)&MY2jRvz?D|c5&DJS;#^dMv~f05`C2{@;K=C~l1|PC#rUFhaY`r((9Jp9jhb6^U%7>sqw(<-s4oz z?Owec!zO$j_c_P6z@$FTj}-iSz*$I-(SFX5Jz5Vr=jgpTz+urDfI-eDZvp5LXFvV^ zhB(vc8#&BzxQek6&N~z~ALT5h0OlBH3%wY|IVrSbnBXi31$oR#q#B+{&cCjh&neEK zHjpQr*Lr~dl(YX;jM;GS9|f!}*Mmwy?6}t{5pK_Yg|<)*+=p~&kt3IV9j&9>v|fli zag(SZ!I`U@1|wX!J7{_C%6pcV(cdn9h^T)YjI#uMs-9Z;%pWtq% z)3GPHQmX9m9UQJ^ z+yQ!T)^cN9z*5Kkj#hH@+<3ZevVrSEG0sM=6K&_3xKbmOHFKk$gIo(&OiR>O?z0=w zy2btLBF5Ud40_15a}7t(*};8Erl+;wya>NYom-kW#0 z9h9}a%jHl8=N>n5HApY_WxBB9KKI*E7}3WyP6OTpu9zN`{amN>z^N^v570e$E9OJs1g|I( zuqSyhQeMWB_Y1`*ym;#=J$j1wEyZxXc?;HI%!jw&SD^dyV!hDv<87o6jX$r=2`mA; zd9+>%DJjM^`>a^CI4aKnzbydzo0?Y&xM9$9t8w)$zPr z-S|)wcqe~{n~A&-J(MN!3YZW$&--^Sv?TMEEr3ZEc(ZAxn!?)^4xOpIB3h8A@&2ZV zRXT5wzET;y`5!?blc%GXX%^4*33OiM#g@Z|OT4|b1Iy-p`~P1YFJv~n&EajOG)pe; zOEnPkc;Ai&AA0FH+Wl$;7TPg#trCIJQIaes(B4m zR#e0Lm};JH^4>TOowdB38z4}}W88q2dR_)CQ5$&6kAXDu`l(d6iTCU`5NPIQlD93q zrv(^m%|RS|c14)j&L z%PUHP&U?III?&V08=rtJ_j%WgAl}Doy#|2?yx%Eb+|Qf+D>xtWf;b=pykITR2YK5f zfcJ>kN-K{cp7j7GYnV6BgwJ+_m+~w)M|pu!8k1Y>NR=RwQD3ErD$!19=PpdAR4 zyxd>GGQ~T42c1uN-xa`!r@XmYFwlmdO{X$#`DNFDXUG409OCx;<$s~&!0+hBm?M8S zIenDBlS=HJ_}&3<#hIV+4?11=DGMRs%6Hn2&SU&9dV%1^e=8T_?)*U7&K>9HQgyTk z{}U>8Il&*GV)c`J{tA2?p8PjySK!58#fHEs{&#Pp)0@9~Ie>ilw%czw=ArH-8A#iTp2~g`G+KHMG=pl9$ov_{F~`T;`Ad z|F#?cDhlc4@&~AnI*-3g4RiDPx!=HuEBxmZ;X?tRvlC;5eCcZ-MSSjN;9cdrPyuxb zzkDZbDdk&>(0QHz2c0q~DN%!%~!QUSr7lh z|7*|r7wJ^P9sczapx@=I0)cRkzoHGU^zud1LGJSx^+9JJzj8fV5BQ#2U|B!^N6Lsj z~C9`loEtvJcQ@)rD?;@f-%@`OJ|7hpZ*-+2oxHUe8V473$Yr^Cv20=FD= z+6(&VQYHt%6dg`+6s)A>w88|VI>3ets?tHu2^3TX6(RVFo{^CPPm20Q2|RM4C0dYw z3qWxK-$WP~FZfac@dUwl^u|jRJi8KdNrHW}P&zMYpx{`tpt=JB7X+ER;9rX1neU+` zRnW+SEop);gW+Ggz$*%48G@O#%gPk!=!(fK!S)sycu}DH1X?Z${-TIywqTOh1(yZy z(bp|U@Jc`Aas_|wMk`NnZYJg>UvPu=+E)ZJ3P%?RuG7A;P>`}5V?}~5C>(uNkfnvP zV!`HekZS@v3b2<5)|fS&Aag3k{CuU)X0N^3dWblw*nrIM;X!N+vp z;R8WJEn5A8E&~jFC}7Y=Wk3)}VVFUIh~mPJ1kRsB%aGvKt8jBzz>~<6~3oxxmh4%>0NqA-yW6nayesH=7_pbzktFVC9 z^T&jRd!X~UFos?s9zxSj%=`&qD58eXofLks2I!u`Pbj$JC7k~sw44&QQO%IIFq{hA ze1w;O29U3?>ld{AgwJmWy1(!umBa-IJzv6Dps=Y6I)jA2HGu>Re<$(N!U_uMoe_@6 z0Tdz($;V`c3O_#&EoX(28xRi@uA!89xUlL2%*#1p>_QkHA^eGA&5^=qzJt}cEpIur zL<`SRygWwOPkW$PA=eROaY9xwtd19E)uJ;&_-+?~5`}Nl8Z$}gK`V&!!auvgnJoN> ze7GR|i>?Vv5q5Y0C{-wJ_16nP)@6hJfV)N;`4<`4?(U7|Da1A3xxfX5HA#-p@e;r z@aj+Cyef2_2JvE{mWqC^2`i`)s6@DlZj&q(`p01guL}*d^eYoCodr@Ze0~Jt6+)l= zkh>w&iqNVQ4$^YDO33*Rc2*1j)57-}VehX%xG7{(46s({;RPe=gvAyZQ7@cBg-Z>> zrUhs<3SAo@-Xt8@3YKQ!Q;H0=2)A-!M5}PqFX+4_Tpb9!HsL#i5NH?fISBC%VIh?n zbP9hs4$HcPzf%oew{YKnkRIXKQgq%HuBFPVJHmPH&~jH8|02jeVaWtYuW-*wAlw%= zP^n;_Fo*t->!ENa6$1|lf1ZH&pzuvP8uLgPeGZ&M!slq$IxH+c2U|vj8Sj9M3V*eO z(__Lh5#+{&Yv>l4385|Jz#a?R-^JLZ(3yg%Q^I`|(t9FIejCO=6|%iCW+PfhhlFfJ zr|9&IohVfVIeXD-UxUR#^!6>tIf@eKm335for362qI6mlIg2JIf#)K6c{W^e6@5)> z+GC=b4bb8yYGuG`chS~CkmDk^B(Qjh-e`l)6QWa{_*71cM(D@vDXOKFznADJ8GlN& zidOL6qBOe1(nr+z8DM=ypQb^zpXi4M*y%4iOtH}b(T^(t6exOqFUEpIAN@b)CVGj! zpQlCB{sYSy(dw_DGel&54?v-!;dJOcE9xpmXP9Vu6?_jDC47akbE0ij-xDGF*%1at zigF)8XO!sPdtiwcZJ`)TjOckf)etM1MOU`OiMDkCJzlhuY8ewmgQdVr6vh9Iu_V!V zSD@^?Xx=eQR0KNq|q6>7II#;xXqRV-rZEpiTU-aBwsJo}#vOqA2>Q)r%(0 zu)0AsLpnb;&Ks8@)dXH0l`n4O{Lxb;({HJ3lLwP!lx1_ zPVj_A>c%LH> z&WV5f4`UHxSIYNCivOaoew27#940GT{Qex^#fUe)34~ZNryo-gC;pi>9P#39U!pTX z?BM~HM6pjK(38Zg#(;NTY_7%hq=@@JLuaaZ6FqR##A0W((#0!=VReT1B>m7c#m-?M zS>l-En3s!UyAJ?+NgSnw57}ZT$|+tJx9)|VIpQ+P737Kq^cc+(&!=TtzPN<;+E>J- zbUL;`e1z6@h2lHYVPKK?IXcsORop_G!ea5)Uqj0^@u38am5BGe3N5AL>GamVE?)8} zRF{bl?*L1=*qyFcs}O63VA2ioorf@~Qmj4;xhgU5DS)cQ?9p0+iN)?vT`zv?V~971TPe%kD6XQAP?Pv=3RyOb6RERB?Eg1rqE)<$jp?~1epd?8 zCf-LE0Ns)0!z;v*E3>lAz615lTE$t<+G#pj;KSdaLS0mk1JXYpX}9r29}m~>aX zbrH1O6aVlDtnL-BJdf6Wabh`G`oya!JMcivTnT0U;*96v%0qE-23Q8fgQsEcpg8nA zOnM|`Q^cC*pFNtf%6oE+96NYktsaE19F*tm zN;p(N?IiiH2Fjcz(~rY47s*FhFg@ogDV_(|W0LhbKyZ^hN5$Ok5}$Q&<+voBYSTO< zqGjkjA-OOPEhi<@B^dLR9M}y3FUfv0Z1Iu&6AKn!$y*CC<$jVhAv*mf;r*~IK;l&a z5-3?CfJs4;S(MNYmh5>RT24#$QV8*k#Fa_{LL~3K40A&z3oY>Btc3R_T49ox`~eg$ zd2c&ZpOY9WArK)s`~TmVq^J;bQIa7_#6?S5?*So3a+20=u@cL(5QvlL_Q2bC$^IIU z1W5#CG!rG)HBg--DSI6rotHc?U@Td3h^h%MNb={Rl_GhDw%nMwl#v~l4Kt}g|j8~v@W5`n0f~8y1qK0EVlEt(! zx-HRFf!vX}egSjuN-8PCaZh5RRY|X8Lk|S*OB@%Y)hC%t>xl=F^?!k-Uy@u7pofw_ z-h(Xz5=|I72PMKM5O^fxOFk(t_bOAhiBH2hAzo!zV9C$X;XXznlE4?s^F+1s=6;Ng`wW0bD2Wcz);vA(m zA7MU^O4pY`r<3$D1L)4u)0DAwk-l~x^XV$J-wQ3rq#45yaFc$u4`c4qiDxi%$E91s zz~Ui|n*s3?(%-!Rdr}&g4&yzg8wxPyC2gXE;isf8(Y^KF(g}K&`$${V0P>Yiv_q$# z^wS*Z^q0O*tAqgQPA0?yr3uNfGf4V?-haW;Luo)bEoH<4_Kft#Zj6OU_fidOs5HP9 zGk8{NM}=--()MrA3YUJD4RTJ}L1C>3sUwA2BBgImgItuf;!7xtmZmL(Wiiq}C}kci z{g@tBanh+zVN1M}xgM|y(yuAvnJ6vngO((zGrhUaOAmL!h-B%PGtqfL>P<&uQlvY* zpe0qBMQhVEsdh2uEM2;bKHCgw`9lC@N|%0&R+jY3?cls9J=X@4E=iXk146cR0~N4b zmhPv=MUHf&3XbJUQ^gp|lk!#rFJJ2K0Q4);ACllhfwcZ6bQVg(sK%v8>K%pFRq41d z#)_rO#-Z$*^pi?-mPj|z6S`E|@D|3dOOKdA%A}`g9a1h`F$hv2J>Unt8&XfQtWr8a zPn#;KUmnn_r3>xRStDJ13y$5C&ZV73tu*ZdSn8y1R0q*0y&VdmCh3AVpru(F5($%9 zq&w&jc3P!#Wx%^79TI`GNwYtO&UR^{83uMp=N3Rqr}X8A80(Uj)7PzA`Vp=9dZcqH z9&%e+L+`jd(m7v1?yhvx6k7MB6Lg%tSNi)-px>9)r2?-{`YR81K9D{-gce)_@JO0Lr6)tu9(tM%OXF-|{D^eqXUL684^e`0OnOEM&T(l) z9>yl5yOzMf$I^rQFg7Xu+X1a9>7j4I@MYV;lvYiy%JSJ27L5rL0 zjZ4t!E;~2~r;p3NrTm|VEcR1;94BOtkHG4avOV-f@stT%(ejeLL1Cs-GR<*l@s^#e z1dxwxc`wj?WjPDb=_fn!GfeWAIYj_HKvwxF5CUbgZQu-&&8!DYuHHtEBllM1H)v0Qvr3jtib^$os%`wBPc@l{SxSml&#B#Nl`M> zIsiq>#wef|BilJ02(hxa;(-?@YoHfVylmdPAPKU0_^h5wlzm7?Ad_UBV-PqmE9^%r zS$2+AoEK!jyaQz^vOTW=HdXc!Rh6a57`O3Br_1uUKs-a%L{}|k%JwXVNta}9bP6q7 z7EY&;F3Vb8##oN5XAwAaWrhuyx;$Bw7RvHvdFP%Z|xmOM{F{ zZ=gmQhk_(cvgd@DkY?G5Wq@swSt)wnDvRf!^Oo#G+E%y8UYmrnc3HU&EFH45;jpYz z7D{)#bjd!N1K4g^2Njz3$YgZnBX{kahna#tpK4D@?4n{Ej7%D$vb;eFXE zGl2SJ(rM87K<1=Ft6!!qM(d$0+6y`dWV1Iwd{E|P3;!O;YACxiB>VUjCTm!>Cj%@a zvTqM!3Pxp|8n`khi=*J?xa{%(5GG`w+rXs9vP{YmP0F67LboYdh92|zM0Sv-;Hhks z%(ankq;0jWJcSCZ?BuSuF=j9Sk+#(i^7DTI-BDisCxDL1XVA9VN&YDnPB_a;(}Cb3 z50=0rSNXeCrhH89Qw$b2c>h ziLaEGyyzjwDfydJ6YMRoqgqBEdFm^$%vavA5}khXDB3>y%m3^JdVoBz8ae~z{_7!k zT7L2_l%0{U9e^z%@_vf&gvxmompUu26T+1+xhw5A!{vTI!H9G6O<^Dr@@Hs89VzcO zLT8k`_6od>mVZABKr!;Yv}=u(f71-kIC|OO&f=m7XN8q({(s zc>~3)lI4F>!P*7+1%D_@k;|mek}5B-gItS{NkR_K= zF8QMTCLJ!iB!8Xibh72lf8fJq`NC9?965t(2y*2Meuc6;c_GbpzI-8tEU(A~_FyTH z_sxMxh4KqdXcft|lsUgDFIx|Di{%@a!lY~RWwT*tiTvjou%%QUN9mdC@;JKMqD-Di zVY_m;X&~u8=Vj38VcA9$g?O*Gbq2e6XK8L zOKH(IB!Bn?Scc^vtb{Ei@^`7sd{jQ2_Nim?UxuM7 z#-`-5{~&Io2&G-Ct)h$p$Ltgz=0eXXMux4S(ofInzFrUtf z!erpNCGj%j+U2#N7v(=Qs^E7)?0DJ6D=RbW{O$)DprMp#ZR$PftJ65GYFOd#l^Wm2vlrZ z2Lpo?gU`T-V8wAG#!f4qr8|1gD2{v%149(SN|+R?_{s;~o>fS=5C~JOzKK@2!sP>4 zc24mrmDoop{-9k*q~d3KSVbuUX!{YZ;Lx@@M&ZeZT&!XzEi&R1w_?E=ugIf|dlD4& zVHitPj8IM^NfAOH+?w_#GU!XpWt7ZhV`c$A_zMn@7;6>|e1m!|mpV*sTqX3#?} zL$RA~>Bv+F=HTPVQm|-kdQqWF1l}bDs|-G5EBccGbXmdJ4wG^emnq1VtGIa&KzWLh zGjKXzv5n%_R}|;yI*v*N-kkQRlk4$4{; zj(GsOrO;79Nr%Fc38y<1dBvEzF2yjF26roFP%%c2VsR5VZz~!%!=yWk-Sg@6s@!1`=DY21>YYj zR`vAE-UnO86{(cfn@|MM-}XFKJY9^jNrjyl za#IQi+L=C4IMH|asbW?nRNE*O+W=&%6w)TfPT4*NtL>FnJ)q1%nL8aGIV%6A1>{j> zniRxI8KDJnR&r=t?V>!<2-U7i7kY0VQ;O-HFE{1O^WdhtGH*Y09#_^-#ixgI4Lz(* zC_i+E&XYY7lC*y6KVP5qa32Ou&;6{JtO^;wiFTcS6&K$ zK!DOf%kw~Gj2W#UC3iMpgO#hO9`m&F;EPawM%nEHmJlUl7sf)By9=TEtddL1!Z4+4 zFiZ+pdVL9UPC3;Jpa|t4o$-rQiaY@nrL?1?chSlzI!7C$Z$`qF3FRmsoR5{` zE)btoK1bCeQ_A_(n9nClV>~Q-sx$_pWur=c1}wI!MfqT{Q>~->1ngBsv@38>HN6BQ z99221!E#h}_!n61r0SuRfwRhC6%brhp*BEwRn4Ry`Z3ja^tN|XZOy}&yQ;Jl;>T6# zOJJvm>bqY+PN-(FKu)SUO|a8b^(RHay;NUN9rY>II{K}6t9X=*@=+9TEbsP*wc|q)0Wr5IV1_?(Bq{#VV5?Q*cey zwh96zs<`>+ELGjB0LyjN?`xs6Ox64WEGt*lUxcy>l`B1kZ>WYlAXlkcLAin|)si)E zvsx8Me_U0g>aK&pP1R3yD{`%Br~(3Ys+TD_Td#VD4u>_UQf@<8qiU31`c0}`REN~8 z8vPEf7M1w~l(njI>1vBxs{T;^csl2Edu~(Huub%s=Me%U6Pu21sS`Sq26s77{ zi7#W89;y~Z0%1V4jiTp+s$WGQk5tp?H8`Y-ngM0QD$}?4G)Gi9J`fmHmHJ^O##E;( z!8xwF+l{daRqIFa;jyZz6P=T)oiCzuN;S&?R@+%1H&N&)fn+pgNQ4mx9#a#>16hwf!OZep($#`~EZPA_?R|)ZQ~8 z5UOTVaQdt|s1-nA>fNCb2v;wNfzEU4g?x-fsMno=&PcUl7Oaj^Pke&0X!VuNn3ou} zU>jy4R?XXlu{ib1^aq;p>bFmWB|$BuJxQW^AwBhz)Vix+Ij{b7HCoAPbrZ%esQ;b| zJ5$u=l|V>UKl%eCO}%Y1yiHec$%KI!>Vs4>l&Ow50w1!};goH;s9yXPT9?!d3Lu`X z-c6@xE~^>zu*y+;(E-d{^+pO)V9V5YbULA2Jzxb(g}NXHV>i^U z3*dC6`V;zDRH+@w>S}d5l^N8ig_KmfseZ)~2(@bKb|BQLIgcP-uWk#0vIe!iCoF4J zvp8UBQvbt1t69B@$_!f6!mpsERlS7P1-I1P7Ra@!yMKkwcJ=xouym*+W?`&TJ=Fy9 zF73 zmb+<2>Y>bCqoeaj$2D;jS@6)5#Q^<;<`PwXoYXwEN6S-FN(VQ+G#wi;FQ+saddPWe zq&}DsAI(+`#(XuY6g~ITBz_4Nf6bjRumot@cz_Mmgyo?Xq}dsQc?s5dq(k7ehVc;) z&S?InA7zLpY6v7$lSWb7vzp7ka4bwSdmlK%HIY;maZVHN1*;=8%c`I(QnRuEcu|@r z%7sL00=_^iMl+~^c&ui|3RoSdNwz{~yyiBYKu^%DOvi*IYFen^H%a46o5}MU7Xy?f zYyLZn&I_7B7idY*APM2CaO}^uHi*MN>&jfC9}7513o1 z3Ec_tB8`ZC7FRV(=&M+)xkc63*EBP!xTR9VcpIcj6Sf@6sx=EJRaC2aehntFP9vwg z2I@82=*8Zo*-mk=X3ZB=S=FNH9tJ|I=8ik$ZfQg>W2{Z{HGN;&HEs0O@6h(;o^2B1f?qW~)QdJsHxp(5Lc5^G82gwpy1_$k}PTQZcRe+8^o1<)D2?H!C=5 zU-pEuquQrWMoWrS4jR0GuA$xo^Yw6Iy{A zS|_zTY=P&gy{`lD(tb}#32*JQv>5WyrczqX$Z@c`{-R0A2P z?MZ+@u=Y!O_@CCkbPblB(T@Fwu@LQ*Ip_@4KK=-Hp4H~bU|^VbFWtKpu1%)o^EvI; z>mVMfT~G?nDD8AwtVe5qUk;WS?W3I#h}Hf{OYk^t*#)2{XuSu(lBlhxEPj&q11o$u zuMKvlah)KB42p7tOGh^}aN9Y<$@miZfuDAXp<8@)(d`wcp; zYG+U-da*X&4xiCA?R#|hMv1nWj@OlHS39G#Tzhf~Ko#1S0d(HbI#5M&rS{n~7^~8z zP-$YdHk{TWwc7GI_&Dmc?yJF4uYI@=V@=wBdLiDd9sdO^E!wF%kT&hVOW<_7w)FtU zI<%n_)V@M#mI1A3 z20DkdZ@2<|SQ~R5WJJ4Z2DFT7_YXjBOxybbW^i2l(q>paseO;i2&c5qkD~QNJC`DR zPqmdFVtQJI;o)=`~^@@h`Hp*+l)vo4b=LR@s=6cBdP zX{c1fT~|yY;N!YcI*@!)*UrU!dg`)TF?C+L*J*+5ql=XQ&sW#I9?JZ5^XU&i{B@)M z4>{``kAfvo_i7yEf^-8*F(JV^>pmzut+V_95~8b{0b4?K&A(&L&gy=qmwuS;5|yrp z>khAhvU9p=w7ZVb743nRNZl}9MH{7iWdN|Tx=2@u$LU_V34wTB10B3g(Ct_VmPFmR z7hz|T?)@hKx}e+p7%VBe`v)&#fPGmqkI2%Xvx=2I|-dvbQkG{-vV8HAwGbsy1C)NE7onK(x_{? z19VNwb=@(#yP-_?J7*4=w8?ZBkt-NX#aOl zw|^mKqF3jJQj+KH>m0s>&OTi^rTQM|9OxO+uRBWBt`Bvue*!H7x;I=gHmLiO&cHp= zy>tw%A)S_f0mHfo5n3aG7Ds%uSy5jOhTYQWm+Wi)4Y`a`iG_IhV~2sr3*(hc8MeTXxBKdOIq z3p$8GR?!kca5=={~toeMS`I&g!q+0!x^Fdnib_-l+sSBlW=)c!|=B7lAWc zKg}DQar!PUjEL7S;D99PHOatB)UT(DAd>WhtKsH(ePbHtEKR?-1FdwuZx31-dd6Wm zmZ>kH!zo$%|FWU_qCRv6fG+80zX{8-^)FCB__Dr>-W@sm&!2)NS3lZ{&OH6AlpD;~ z7Z0L!MgRFW2o&h!-^4@~>g8X+h$4LlP2E-f=rUMVthb>$lSdW;Oa>UjoZb zeLxOKt^P+h7+En{2rCGlq6P+#k9y-L`s_*TE zWw-Q~D5lz`KSYNK+x0$GVCm35cn5BF>i@kA&My72e(1cdZ+r`#cl2jyOLJFWH3^;f z^siC`t5^Sn3tYLcucHGtefn=cgPjlb{ySh`zyAFI82C_MNB@s7puc$@EQ5Lht-T-V zKXQlMkp3?!2^iLEsG?^?|2ZFHqx$j_z#G%A{{o%k`g#hZP3T|z96BHCuTXi(r2gz< zkSYCi+G{`25AT8TPxT*Bio(Vq?gOl?p@=Tpb}%fXt6CimKV1jsQ9}`BDx3`4={@Fb z_>D@KT@35r!I-O|k}BVi85-sQ*3A%q4?5iqqdjOHH>CWEmWLsNo{A?7;TK@bNyB_T zIz0`oK4^Iv{8vKRDZ|~LK)emb|G`@ygI_YxeGME64fq)@g<;I!@cC?X1{h|J!-zn` zGeK}A$iVpuoxz6pIlwz@_{<6)LJc3!LFZY+(SCdj!VDdD&>3!MrQ40q8U8*E5@AUC z3RXuNs$4N=QHK6TutXa^q$;l%!;F8?8EbH%#d@5frVSI4XxK?P;Uq)Li|9OWxJLoL z6hp880;z_*djXVYaH10QbVDH}QZo#zC~lK!F#HPRvkX6Gqw}J{I1gGb89t#9aJC`w z4G3H|NOaJWV~C3><%wa>k#o$3n$X3Jmtq{Lu7?eVFn_(&Kgxd{S5fJY% zXtn^h+tAhx)jb9V?bU7@!hQnh9fMONK9#!$TNPUO3}rEp>oc6A%CQFqXG)g#8$xv; z4-GAJuxh|y?1K@5hQnsS4jV4N03${WUoVE1QNus^=o~XFrFxBVL!Ah%3BxqHwt33X zLiN{A4E?0+sbLMptZa-&LLg^ryvBr`cEH#vZEmb22XP0>TO7D|D3V zq_Oq~sP;5g(7mBv#@{J7ampyqhw<7^5*M;e`|Zad1TE`(gPapNoCj4|f6!1!3>ftS&WGv@yQE%8Qo z`i3MJ6aK_}CK|U;mOII)*o|2_Z@d=|Ey>1Cx|ryKv6ND8DaJJvZAvx1OXUJ-#)PX- zmTtU82j(-3?0GOE)5xb?U6!$zGNBiZAN>gfFBuiTLm=Cj+sm1(t;Sj1n6q2PcX}~rZANP%1lo-s%|ffgxR!PWoyK?QP<4-S$7+z<#%c82y<>cb zelmBBvncX)&**1^v0meWrCfvg9{NA$w%H@g0W)Hp-ug`aq#$w6_P8t7v0D&jQFb*cYHzDx0!3ap?rQooPM&a_mhNi4brw>FVIE zqbY;7okvYUw2^i)WznMB*|aADZn~J#scOg7B+W$Yn5pzfOu3usDy@m!P2rTPJ#Lb` z1OyM$8hVSKFx{iD>q*n-JdAmo5+0gJC`*4r5K zGkLNw1^%Xe6vhrP{ZP43@-<+RE39aw$FRM-i*5YymxjD?!= zmjdXlY2*OL!c4y;f-~GC@c_^{lfzEvj4)L$0*N$jq})rCX(^@9qD`Uc5Qs5NGSP}P zrBNk%oQb&uB;M3U`^E&5#~|bqO}8lRm}Huy4e@zX+t=_m*`&G$&I=}e5o}2@MJ$Du zRFmT|pr@I39fWwgsfR+q8Ky)dY{@jO7=idDlLy5$vQ2>$1;1?CcLzS?m}2ijAlI~- zas_#&wGfB;s_ENZ7%MhK)6t4+rdS(T zR$^MU0zjpvw?bg`b<yH=D{OXtkKm6+?Ba$wGPMzo3TPQI@n~;2Y6^J`AIF$!;aspxnz-*l zZp!3FtHURz%}=2Esi}+N^ET$qlMuHxze~sK?9A3L(P?k~{bS6vgZXXBB|Dk}r$OgY zb0{CP>tz1h2W~o>_fLZlE@n5f%+*};4bYF7f1%SQZf0{f#NEx``~cYF<}LJ5d6<{I z3h@)>Ju^Z4%$K5o=Wp((YM21?13C*8Xb$=qV?pMBW*)BM4bZr&$`K!*9bHR#MVXP$sSmU;XzbY3){C;-bPbLU=s z4%z0ND?l!rou|Rv9P=?sF65f$wLv`3{MtL1iG1?`sy4V{_D_Lj1?J7^Xcd~v_JS0d zr%gcos=0|i)ME3mesJuXd5cxPH4yUl$qy8f|Q$M??QEjIh#%q z-Z0Okn(j*TLaGm`GC!t6z}4o4KhRlY)_x5CZkiiIfLCjFJqQEq%=r!Qq23%=1n~y* zlVS)ontkXu-DI|>kGR=fyAlE|=2$BCZ#Dlz2h%CS zPV+f>>35lTU59wLd50Nx_Lw6oKyI7uY`}8I>_AV39n*uMc5TZ>!( z7CVdnI}m%zZzO%)r4a!_BEQ-OqT7qVS<(TCg zf7t0}dBz5E?v}hLC_8RBNRKWLOY`fP$P*UTa?I{YOJXwQJT3F+Mj|hZfC_g{Sr*&@ zthZ&7j=K9;9EV`1ujMdBiTy0k?1xAGmV{|=Gr)4~09XPoGb!I6WciU6kiiy#Bg9Wz zDk*Mr#vz9#+vJA7Vng#K2%b(kTaL&?t5v>Tzx_=-LX^DOb zc1BrpsXQp!vS=I7V=QdCEGO2IMrE0CmgZWp#9Pi$WG}%o^fT}hEgm&6Fv)U;wtD9+ z7pPt%*;2a^Q*goJN|op-mUcQ)lWJ+EXKR{;-vrCjEk`NZn_)@HgO*H-cqUY5S$?er z&_#>-XH3r}OBbEi$+oyqZt$|j?jWqrv2@Vgr@5A3s%gu!M0TTe?$`W4FzFSH6Q zvvxzE(9&HDmLiL)4Xvw|IC@SLTlUb!1=lR6Xt`BlDWhFhsiovaxOv?&jW$1JmK$4O zXSpSeDrG7xI$w|*mKC4C&Pt0vZFj0HPiR|RZTYPjay6C|PmJBPY@dfouCEZ2U<$8p#4`MbcoXA#l#^jc<2!0G!I z_A#{jEO$Rd>w)Dz7ij6X9MPfm&~l6g*a3^45Ai{ZdJ5u?ET2$Zf5`G09hn`rJV$pI zjac^3+jrD*pU%pTS*AaL__$>$RX|Tza_J=2V~c$nY?-w5q=0kE(&UAicw$LPfR?8g z4P|g_tX~SjVryOE3pqP$38d6T}JhozScepVfa}y-^ZB0b?z9n1X$Z?a~Eh`O^0uS ztbeZnP_WgFO5RUf$9%wY#=7Nou!LB@qZC@0)qN&9!>uX1q4S(|ZVM11tkxayDAM{S zU2Ya-^|%FrXzPtp;Kf)6C@mgqo&Ooe;;aY#0TgdFQ0PCwy15>+lxSVF4aO%~7cRxv zd8>xvD9P5Rl!>`ut^NbBDb}D(P?l;nQNcx;^+UQ=F5T)+Z^I1h;@>d^nbvRnAf9FY zoeoZ4v^p*T!X+z*mWvzA~!= ztzXKm=Ul;AVSV@q&~I3alpvMX>Tz&ZS;O9dc(v7=?lP&d{<{*k+_XN{z_MB^la?xV z*7v?aXTA0P2S8}Brcr{j(faF~Xf;{y4`F(mtv3JT=(^*&th%_F?P0@~sbyB?C`~Q- z?Y;M;VU}iAnw6zyrO6TyS+ch*Q9uD13J3@?L_jtIf(XdoA_$7&`#mrJoX@@YjPJS6 z@43&t=bn3^lS(&i0w`47X7d8gaBteQ(TxS|Htyd-ONY&_Dj4dtv7;LcZrOZ$7Mxu+ z=WoGKugz_m!S~s`w-Mg<+g$q^;0J8{X;XL5=8+YZLpIBs;mWX$UnEqI*yJvS_^8e5 zWVDUhXzAGfZJY1u)Z4gCg9GI5*qG-4^@Pp$w0SvcBc@fsU7G_x0q&Gdwl7N4Hv7*3 z(mk6rn!??;Sxk%b8JjJXdh)>L!zFO@q0Pr~2+Z2ZD8KxXjfFCg>=+N|0E0avrUR%Q z7)M7z92qI(pA+M=Y{(sE?4ZpBXU4X2w7D?+_Mzm;;L`rz5k?2y3FO9j-w2#X8LqTG za%a4<5UM>GAHE7Lo{XpaK)e_^v@zz*h))O0F-A=cDt#EC&!7i=8GqA(T|b7E0vi4d zpHj31FgWzy1~L{?j3tQSM+>oF#t5DJ3}KjQMjgtCrr3QLBXKt#PB??_4GR$r2TGMc z&hXm_xk!d`BRHcNKhPdZG~-h%RL3ypUW1`n#uxd(a)Pl>2Z1=o5Di@?8QV?Jd5V#j z1!akh1$>axjME9ga)yx<1i2(e^BG`CW@Ih|Nnw0Tn;B;rn|_CdRK~IYpfio}3;oK| z87vMSKn9~C06Nbxu8?Er8LjuxmdQw33%M*t0j_zC$Tt?k{ za4e6(qfgyM#+*-3%4amtk;?*x<9k4MiShjwAS-0Nz8yXkF`iwF%3{WDy7jVzVMp5@ zml-y*&{@jh(B{__#stj{%NQ@-g_d%LhDNsv#`pC2uQIm30)Ul_YqUnFVmvtwfojGY zx^9DJByp0FOJ^MJG8)@pXo@lQ8U&^p z3r>LCW32oKhVC=oKL(Fx7!N<{(-F*?W^f*7cD2L5 zNG7ig9T~$+&4FAj^OH?zJHb>&!CoBmS4uBA$^3j3w47od;s9VgbBK}$5}4Vp@F9`; z>LawBW{y9D$}`OGAA^=8=A8gℑB5!)z*3GypAW%&`{$KArjVZnR}E8!kZn9J7En z@Xj+G=KyXd^S9?fvY02!@x-#3VYvWtfq9RPyX7!h+o0?svoal(`OKC(&{@Fz^CEn| z#C$^!fkI|C3zbF8t8^~8m{~_r)Douk7A#z5j?#p#l-alsZC99mD^Xd-)KJ#rRc7Va z5U*rzSq2ML%qIHmRx@85gLn-y?@G9G1s0~5U(wfant7E*se8=J^xM79yhm9=GfWu;&K@us zF%W;qZ0v(8cC6y7DA}`cS3Q37ti9BAj;u|W0m6w@PSy{zk|nU<%zB#^KQ1h}FO<2m zhG=j82+Nk%jczQ5Ja8Um#jFHzXN~Pbr3cHQ2i|(Jk|_${#qy-Dwl`~F9)1PKSbx(b z%7>NnJOq4M^KZhQA4~WTbo#TBXs;)Lb#^}VrZrT`&Vm%!XmS|QGWrW1AYW46vj#Wl6 z+>@+lX;><5`vOKrVsx0fovES>DfqoM!!z4tr-hDv4&|algv8y12|Jy z#Z3Tsmi4d@%2HV?9!F&w>oA2{(pi&qeOd-f`4@1WW3hTsI?r0V3^+4c16QCdi?!o2 zVkaMBO0szhtzw<{5vr?M_FRw}maiK2YFWXQGuyy=sU9rXSVzu4StDzh3GpV@ zU7Aidv!16*7q7GI9!HXD}jvWvfW7)q1)VEm%+7ujTz5WU0?y%fx1e;)`+(++DvfO*Xd6)GJ z{WF3o)~FWZ)2tvl$UWA^B#`^8T>7fbuufD#-~nq<62u>}hR5OGEbH`-sC>lwxeluB z*gX`_vS&|H}(D=o!E(CuyB}NL7P#|>}CHyNXbr%18P_HS2`Fv!d^{p zjvG7w8}!mq_72)raA*Hn1s^=vejex$Pxh{#q0@`~{Ez4*Z}zfySU<+zeI0E+?2TK1 z%$F^r?F&D4*be~V&u;n-Z2|1`LRbi7U!ntbA?%&L@F^Ybg&-7-cH#mvFw0wxN?#mbs8W}vBT)L+IV&s9rI6M=N*F1M0W3L zfH=+O(zuk&o?8#=DeUi0!OgSm#!F~RWk>CYmNfR~^v0#L|D@o8KnwyrfqiI+xXK#N1xe7MpGl00t_Mv?JO7`&o*Y@lsbTMrcTagLzW;VMOrB=4- zWw?2ReQgeuwXs_%jp-)4rvRwi*(3fab+9Ms1kf$^4w}?-u~*%ITsM0#0|Gtl?Q5Z| zm)%3xr}eW}(WGsF?L-Gj2HA16q#0uW)e9`c?2WXiG0HwhCx^z^r*1&!ZT4AOB961K z(K)v}Y&~sMO|U=y6atg%Vftjt1XLFou*E5%XVIOjuQ;V9?hjSzR|JZNP zowku8INohgeVp?dX^G@`QtC+*M`#Za(VSKEq+>Y}GJAqkNkdQ^$No*QoaFe7K<6pW zca%sJ&nc^e>I9CNVpfTq_-c4`nzQj8{94a&me8**iQ`B4St*=83VfdBe3^z)D#t{d z1ZkXM`plAYDdc3)+h4>{KSVDTb8JUosD!iHg6=8hTqps{ z6;7rD{43))&}M!)C$#_q6`ZU8KjFl2+zh#D&IX#~*KnSt4B=W%c??+UI0Is|)pJH@ zv#o(s;s?^m38pw-6UXmk=xpX(q!IHv$3=oC*24LTJ}9l62|5aJgX0$noHsf0E(o-9 zR?#8#4vtp?RCjXTX@{G)IQQs+j4qCA0t$S~*6tx!F}ahwbAqnr(tY&php`W>a)90lDpd57aj$K574Pcoov zlJh5}v)tu`{0#9aPCErY?{loQc{#(`K@0E)oHyH1ddOKtOTAf6R0+f%adKCq&5q0F z1DQSd8_H65;4a$>El%7I_X71{Ze0a9ow+L)LEMFViAFwGZjAyZH*PCs4IJf0(ji25 zZaIZ8Jh}T)pv8;pKnF>@x&LlL&mZG{@CJIxhwJ1^%&Zs zxtcpL6vI8Y3fAMePImD2BsY|yBw(Fxz}jhIDy-_2Hl#-RTV(>Y3`n_5I@76 ze-Uy?+`1L;D4A<+Ku4xs{TwW0a%alGlEvMkhMU=3&L3#Y#Nb9a9Sodw*4PE=mv zF8K{Ch1?t=kQH&?ruAPjS2Z76O1N#O&~_ODAXm6?jp&IoZu1UkDd#>%M`J3uEV{Vh zD)+a?P+7_Sc@(OvxPMc$x0+j=fl>|kvA0pG<+e6KOC9$Sea9NOi^Q;Sjr;dcK;6il zLlf2}u9YHY&D>4%(LL9>cK<=HgFB`nZQ`@QnJoXX)!Z!2Rw?2n=!` zYz7(OYUqxFQSQu}Ff_(p@efM3xu=$cbDS$Y2@rRF3r;*Uodawejaj1c=mLx(v9~yy?94?k2|5{ z&Ra{n;~u=7qSP0=6X&*0?x0B93hVfn}5XX7r^i_-G#eEIVDBc1(bR5sy zu@|KT-iQLo5_!)qg|gGU2s0|r@II#8&?H{e3wTD!yaO))ZVE3g7-rA%1b)Do%3FH@ zB#l?O3>MOPe^h}bgD2kwxaW9#3Ze5nZ=AjznY{HGXv^YNQ}S^(&s~GI3%n9KfRe+T zqSIZuyiEph=J8mm=!uKGk!W;lK5r?_91D0=|3Tmqk4N$3LSFOluu#OiLVK;nynX*b zX9@2R4fmIM8$W~2Qr_M_fb0tI7kV4Zc;UelG&O1~IEq8d==#qg6-cL_JV3KE` zMa5lS9%V&L@!DenX_~kDH)xsRxh;jj175HbkUivyzX6%$CDPmYi04Ad|91RRT6Ws= zZRv=v1K*L(dO7mfP)d~(KZF8chxvK0!v|;n^lhMa;pch$mlp8Opr)K@?r~=I0-PvSa)#T95hgU#kQ0<>yU9ryu`f zJlg#E0!NSleyaf<1@bkNv>e2*JPQ)cPkw;P5WYJdP6_2d^*YRk@pF&DUN|4&R(xLg z??eE^aeliQ;3N6VW1%dHA4xlt(fp@B0ZR=3uYUX(V)?m!PxN&FfLbtdx{{{Ss1{J-Xa^DIA=eweBJ(o?XP z#!spMOFF;iZuBfa0{@f!=#U(K zAMN1e@(aF)&OCnP%Xlgm`HRk=EuZg`3C;rkgLPoJ#9ze&OCeu(7^H}=tpLDc{y%o` zsDz(L3F(*l)5p*urTkYG!m%s-YprN2<6oydk8*y}MQEwutAB&|RsQukAeH>^?GUKq ze=3CU)qE4-tl>XHIRv$Q&wX&Ej-RsuuGI5CBS;PWAWG!B#@C-jsgeJ}PcYlWuN^>T zGk=dW$aVggc_1zPrAaW`%KwKp+>zaY3haXItqP_gLLLt}3_x%WR{rrB~WF6ptL8*{~{B0g64e?jH0rfC{2W@7I z@V9S8X^VpyN%J5U+et`7{&@?&W4`VoKS%YbVqxONT7>;)MgqstuxUnYaa zQ4k@AJtx6Yf0PajmOp?i&VqmczmOJ~SD?~WkV(_!BLXi8h@0R#&E$>>zCRAL?t%kR zsPqu*cn&%}1&pl__YypJ8aTZL`Pa~POz^f9l|F)hXhQBQaC#oZPw?ug_-vT`FV8J4aV}=OUNP#+3FizXeVFCwQBZLczbRZD|uTLOwTyTqC z-$=n0S`I`B&ig?iTJU)%x+g~P3vH6e3jQqvq!WUtGa(Qsn56WllY(`WUUEvX@)-b( z7aSD8Y=Yo>dVYz5wx1w=S`b19Q_l#}bdXCDoOl71$%5w(z)*@{We6(I3O0_Slq&e@ zCv-@ffZK=4bU`}ZG?F2(CoSg$kJAMN=LHx3h7Xwnn~kuZC1B9JE?W?32hIzEiCk#O z5p1C$C|95=hS@xU{vse<6xh)=S-wE?6T}MzM}IK z1l)zseh1-S(Zcz6fjUOmJqILKIOih>oDdFBwn3aQF$ydvg{|M<@t+c| zSD-Rp$cTgL1Yt@7>?I1Hcnfl;g=gp(*%@KvO;jcc#lOQ|vT&LXOQr~iDe`<)*mM+a zslxP+K+=RM4ltB144~^PGK4nQq2-*gCJe~V3nyrh%M|7hqB2X^I}9z^!X`1mUl1;M z5vp^9k1qvFuCRu-OY($ly1MwH@U?FskS{!S7^MQ?-hA}uB_X#4a)rVY0kjkeM`(I? zS@_C+ST7Z(7XbAY;b}UaRVL(8u%leKcMPg4g!z;ydQ}*66>XJ5KYG!tgr$2ys)b6* zB&iXupjmURa1PC^>V$!j5U&>w&~8$Luzw%OHDM(^xJIFu9>|)6DfIZ8g^83qd0ogj z1c4SI?o7fvCRAUAy&FQ?wPK1C<(AFay_#SY3g)24qN%aZOe+Ya1LN^Mg4hUsFFf=H9jkF92|Jw>k!@`fh zghwMnXUc^e6{gYqJ|_Gz1U-0Lc-bACSc!=64zUwJ+pbwvyNcS?dc#Aea4lTz-lNX`dN906P4qwrxXHe-U`mGIS{Y9_S zB}oCISz1X2iiX=@AxKn87vTnr?5hAUL{u~houQ&PD4QZoG&l}>;i4Vu;BZ#ow38Onr$x4IKz2stLLrPK(T-i-PcKIZ;sn1kQ^LL=_C^yeK+) z7WVQ*&%KSx0@3=9;MgURgkofcqP(|Ys7Q3r0XU0A?lg3jh}e{yeOc5&=})C1h7IJd zi0XtWm5G}F1xvZ;v%4r&h>U!+Rf%Q-(4Wu-p)B{|Eij zCMx+0n;undb76c8Q}&CptVRP?tGSjI%z=Rt0Z z66oHManWlutlbgi<-o#($d?WiPKs77K-*nWLo&Rb68(7zWLm_e7w?|vO$rU%7cHXn zgc;FJN~wAv`sgm~JrpJE1(sP+-!2H)iLVWr*bjFEaeGL{) zinDz|PKh_%0;G8HFeQN}h-=Frmne3p!SS@1{WA=m5igq$@g#8%o#LUQe;+H1UfRSV|W+(>shl7F$mNQjK`yY8a{&+fl@&PAqEy>U!~^)hIQHJ(hu76VIV} zd80U;(hr-&Uo@d3o5hdOH}$&s)n16Vh}TnwVypQ28)&;Be(FPzHgN`h|89!e2Vt*W zyqUIAI>dKrLDeaqDu>Qn;#^9z>k@}iSgTw7_)hrHBYx%(+Iq#Iw^8a74@Q9Wi{GXN z&VV@dV}KYGpUp*SNL;xGJuxiS-$d7qh%+hEcU0^~Ne5%%HFPHXws`F~Amd_DB_Q1q zH_?J>LL3tX5R+mr$}qhvUUCfO`3oxViC=gbhVF|$qfqCJIHUst55)T} zf#sq2-EV+;R^0wQN{_^MV!&c2S$zf;>?MOg0GWg2UpmI(D0!^`t~g0n(re)&`Q&d9 zSIJXhuy;g~?g0Te$?&%jI4ZHDokDj>ADwaVkhuAw%~O(3OLZ^F$F^wmmh9J{?U>{r zI?CZASx50KUkQt@vGbGk($>De#Pu}f0wnVvL%#${URVGhf+VFg03R%2NTDo5k}ts% z3zY<3L|d5T&^)*jE~%J>&Irj58nhjkY`u)ONXao;2SiCerI#{Va@`6NBl(@KmWh?* z(4z2!Bs>zFagrbN05D$i*f;3i1j&~a-Aa_qQuODvC76Y?a<_Y^ctmRx%U z{gNW-q{;JH$?718r%Gxm*)mP?#3it#OMa%^qzuVo7C@Ync+%Be=OqXI0Web{qG@lI zWG(HQWJ{cB8F4{U{W|RBNY)*I@41o}e??oKq&p4DE=s)Qu$M1M?nbFVQlx~IOOkzb z-9n+{N*9n7NtVz{QY@KTkG2wt)fQ$iOP-)vWvS$;w}It~B!$xN%Oopkk#cU97p1ud15RbN7`N^+MhR7>K22c#OwqSaujm2@=%M4cp)+^m;K{{g@T$=kny z<(g#G_Yi25?4CraNs>sxm1arLGca^r;(Gz57Kw~P@okcE8_3<1G*RYXyJXi12y{rs zHiM;8@^(F}-;y}FJpPjVs_s{185KNo*4o&lDChe^gt4|0**bD{6Qb7 zS&2JE;T}mk0w8WD4Ic-wmtLg|8wY9OE`WEGemEC!ounb_0PwI>QVU4V(l@u`SKuOj zb`glH^!67JI3m@rhIKb-IDK!AO0QA4&s`ct@d6L2?Nd7So==dboPpDc(uec_PD{mf7tI-IJ7owbNxLW)AX#c^Mq7$>E0!!z&yXIYh0!_bN;XuVm%g+U;+fKL7C5t{vtNK@OM7Xv^n$eF zb+F_}|EA-nxzcw6A)Y6V4}`!)>HGB4&zC;A0W1a5TeRZ4B;81WS z9iiXEm~;~bEpAIc+yc3A>EQsB?nvLFu=0ddK)VW)(x2#9!d+>84Z3GaT2hbFw6u>_ z1^1+r^b@`>Jz#;d8R@eWlY1b2@eV2w$78hOMDSN2~7QAEyv>EIz^V|s^j>#t6z~UoYdk6r1WgWR-@ska_4X6EO zYbiH0NVcE=mBBI%Wfz6W>}V|-DjTG9h%lMvB(#Lf*3#x>gzP0pKsqjSxeK{SnU0)} zl1UCgJX$te34s{d>lC1kmHkWsq7$K085ta*<{$umZg3O3m0VF^!>|`{YJ6aT$wQ&9hoQl`Vz!1%3{|;b-rvJ zz0(CU1qCfG$v&pFtFjA)z)~r5F#<%D>L{b6XSl{wS+QYUM< z1yV2brDU20*?<3m<(jOT3DPK=iU8au*((%gYL?A?3Z?6^uQ+JCAv=)-)orr(X=Qp- zw&npyyG%pbrya6iDLbrF*77-2-;zyGXs1i|DeV<>%TBj}^vISqLT9h+9{mTYKH1)1 zVZC2=?F6(8$d1vve^6GG0l6XB6m`gi>~TK)o0Pr&H=MpJ)2v2mN)|yu*lF2gVs!F7 z*$2dOU$&5@2Q#wGE1~m&>@dyw9?EXfZ7H*|Og~gUl6BXiL+s>nM?mc5Zw|l}2l>|w zsCJaUO-n>4x$R@9JS@MRj*_$d*Hs`c^8fmw+Es2tlbR!PH%AaRxkD<*QMvzpIOZ-_ zeFB{x@~htHB~STDnl*dL_Z@_|xBTofR34Mx`38`D9KzD1`71}%lEgU z3j*XTBB3)-9!}3aNbdPMO2P6RO56>RKS}#5q4KfMARZ?FISZ)6<$usmDnkB4F~pC{ z!=^wYn_Nr}n^y zJb4K%xi89XXeOR7XVGR&fqa~{zAwptm4l^F?oBK2BKgc;Xe*Y7cmZ{Zyz33Xy(||O zLT9PGp3YNVkxRaX^)k7_69VP(?`XDGA$Lzj>8jkP4;CurUsD!FmHe0YP+2X1{b^Lz z$lsa+|7zv$Q$kmroZ$yjFSnlu9~$I)>Bg)kxyK%`G|TtWvES?RvlK*Vk!vZ!(<>+;I2?Fhq#C05d}g#6_#Y!^HLOi4;F7l zGQFwC6dVe?_$Y3^1p$A>hNU0@ihi1F1S)={P<)W$FUm#>R%qx47NV%}0tr62_QR-KM;$SH{IZ>hi9c`x-r(cDCXB1U5txrAa`D|mloNXiiN#k$x=knk0D#}Q5QHb zC|=~__mZP{XDzVgDjsct**wKdi2!j?A&|mCzGBadkSkCur0aVxDf|vWb)h142e1?= zhG_j)tneUZC5jDnr^RK()Y}j*Riu?e*%ieFI_XlTm^+M8xnf-gysc1dc>+4GDqc+h zXQjgU4OprajSo;+t>{&Ovqr%whO%149tlcyiuIHbTd(kL0Hg-RdS_H#Q?$}+*r-@m zfwm^a_DE=HQEXcbr&|?uG+DTzsHOQtn<9>85H}Ux)evY`jA;P3L$P}p{nDv;qZo3x z6np*zXP4qA1?IaICu*UyM{(qR$n`4JOprdsnkx|KS7he{=YS&TO#mEJ3{r4&NU{1a zR1PclQkV((F1au?s@O-t{xOB|6F|DH_}u}9#uZ;tmdPDOb|92ZD3s37GN~A*+a0GB zQH0VzC8( z7j0F_%@j+oRz5>p%GZ_4j{sSVatW<1T9w~cqV0zAmjfuZDSOD!O{IylH`FU7CJn$zoIvC`)PZ z7*w9mfa)RThZoST!^#>8;*BUnRbUxau3U!7G367tQM#=Zhkocr4-%qs$p;Bl4buWHOtqiVpTbqIEK4Fkl&XwYDAB5gl&2G;dh1zOh*e#F66A#HPfu8gQ}@rPn@1wPP#DSyk2VU`bUmG_ang+UEyI>8jUS z(3YW^re)_jl`#k)&Z}Np3C>K_ZxnmVQn^lnGh6i>16VGoVmCuPN44-bfXG!nL5EE8 zR5!NaS8!3az6@IORi`PTt3VZO54e|9U#|f8LREJxR2QkLe@2HCt87OAutYWd2Usqv zIuFB8nTnZ?Qn_j)h2JVvPx^qfS{3a8Qlt9fGuW$DJ@!0Gbt+jZ0M@HE zYbp+X9~xCXnGkPMt$7x0&8qDG0Pwo1%nt%Bs*C<;YgL7JK;VX|G7xQTs`h+Xzp1kS z8W!4BwY2Wb|+f=XWpEPjxsh*rdsb7_xhqeLLBVUXh7#dOSqH%Xrl}JC+G1b1ysJyL8*pA9^)nfYR%Xd`9L;##n zC3OMPr0NIChPkUc^(t7VRE#WpeTC7M1^&7p7cL)A~k z==oVyAB}_dYR@M@9MsvHfXq=HdKHkI)cuqTcUYZQi0*M#U!fEr7q#!ZFzc$$p}n&s z>cf;x;imR=gwCUCRVs+PddWUu@lfyag9T5u%@5%8Qm>`ip|?8z4%&{X9h_juN8L#G z@A|6e(Pb-s>VEoPQ~v4|Jjey8x9HJ5f$HCxFdL-)ipGgh^>egD3{%%`fU)b)2)N>oa8Lc*c4HBc){fe%ORd3q}dneR6^v1=h-=Wm}lj;gO zM0!g7-eKU3S1<8_K!V!z6j&0~apO>ZTD_|oY-IAomap4DSXIOhirhBEWCu^%vN(=LPuUu-=UERu4(oa9_4IqWsQ&j)2;{5p(R!so{rr9?yQKbO0mKW{ITVm8Qol#}ZpG>)&FHKW z^_<7Rd0D-ac2r8$=^_BUqBfj_^)mI}lmk+(ZlXA5g*xyEeiK*KzfiVarTV@H`m;)% zeHkp(>UZZrOO3i-0iCsKH@Xz9POaMsfqL~1l)>JhPN%5RHMQt9lp58B<7jJA_rD4) z&1zu~DzB^AbQwvDy68H@Th)WK0dzy1ejB7sJ@F1)=};HZj!LI`15LhesaH5au1kHS z1J=9MnkbZd)FaU-^{Nx;5%;Mh{(xis>Jf@u4yXg>p(h5_PhSO=A$832s2oX&ard{k{mbCfZ4;41)lTYZk+fN^yq`EW=5#a|GgP)BuwOsacm5_MM{CkL5Q@1{PR zR##HE=$?9KEK2v)&przaGwS?DaO{D);&GsUsQzg$bk3^(rkK?u_2xIA%uW;VC5XMo zogT4+rnv>gQB#-?El!%w8fZDJIYCn~XH6Q7XD*uG1JLHGai;q&j%b>G265AHY+=Yl zqcnokQ*-_u==9QLbVA%)vojbycueztC3@FKGk+&od^IoAT+vVSryENC8rcqr2WT#y z2TPzvvlXQvO=>Sn!J1+Ew1#M6UqLBUQ@b0=!Zc6P`w*^?GvQc-Mzs$t$2D;`z!IsM zp$Siv#zg0fqcz*-qhDe)ugw9LSPhpJuO~EBw09k+X{J4flbX-NA$LmC(gK!v%`zpF zC1^$_p(RnXL;|NzYc{=#(izPoI^~n3*^mej$(rCT(2}D0#~!Yn)wELfX{x4@{_jAV zX3r(Cq-z!#@hiyCd`)Z0bDC|=uy9^en1NEJCd~ojS(>*@P@S#0Os7sSXnv=lVUFgL z{U}}3?6Lq^zNYjASSZkB@uBRJCV`$&p(gWV7%I|qJO-V`8kcamS)vIV0lBPcqy<2! zrk+lPUC{{W-lj6mC@uWTHHVZiTcLUDFX+6gv6P@xsX4R=s;e|Ms~}#j@p}W}HJS~! zDAj6AC*Vq*rt52FBcqShh~|fCRE}zPwm@J^ z^Ogfjw>4ALOXHetAH(b&P1TclwiBA4527@w8KAZOT}>5@ty7w3=~pnV>HG-d_cV(s zMfARg9}asnnj5qjd7$}fKFCAO%ap`8tFcQ0z(<-`%3HJ3er|zkdu=6!7ag>{^sn0- zwVt#m<)nT6eUQW2-tS<+S=&kxRu}CUO|xCKBhipMq8+1{j+?f*0;rE_BX_~9yS8H& z1U$6AtcOld?H)>U@X{7ugFSC;R5mOe(>`_^az5IWP{{de^Bf@Hr)AS+@BUiuG~5i( zzM(=}pmrf$xD}*bN?*KS?ak9L8=}pk-PKSns}Az)26IKN1oKi(RER$v}Z{?UdyBlvlF!6K7{H- z?SIdq?X>n48qdyXQyZZyNgMVQa3*V`XtO&-tE1E6XSG4JQ=h8cNy+MITE=D=O4lx> z-GL14I?Ag&r?sv?7o68-QSxf0wwJbev$O^FkjvKI?E%0GTG#n7l%v&A@HSWbYcxuE zT9y;!E@}?I^FSQ>&N&+*{hUGwqEciQRp1i7Mz8f zW7;?Wzr(LButIKJ`y)-=?`Zowpn5{Pgodt3?SWjh-PKCPAX8e+Jm{R(en%N~_q1#p zukUMHene?TJ4XXU5489FAoo!FUIToX)h?oS&LgcCC8^ly7G}Z+d!2s`Se$e((AMH% zT@xp<(EH%3+ec>=j_A(+2h?u5x<>TNQQZJVRor#5_h86F_v1+@^VIdw zI>1YJFdoEPw~Mlij_JziG=z`tG-WLL>Y_4W$WNEh2W9@c^c5%t=-#4##TBS~qa7qj zR~iFl!MZw%u!iUsaKIU=J4>hR!gRIh|10Pn^?no1qrRZ8rD4o@LQ5sXKPEPB9G~EMQL7&sL?Es|n zy8ASN%+#&;4qCEwHz`1rt?QzY`UPDd?PcZYp8Ei1b9MVDGcHf}1u46zJJ^S|e4X?L zNP+I)4gkEQ+fM(1uTVD@27w}7Kcxp1>$U{KY>BRoe)^YnZM#q^)jj_n$Q9ig+P^K+ zO?(9q<+^u$;X{Qk+XA_(y5hx9R;gS55S>+}d!Nq4RO`Zigz6d{lX9DCb<=b;P@V2~ zTA|eI_ML#T2Hl!jkZZak+A?U=l|2sCO}eM)JVLW>QzHDku2Ua?g%+KFPmV~1{J4=Ou#|4;c?R436pY9@M z!uIRR{{5lJ!virJG8+6@_ z?l$RsptD&AWe;^}p%9qWHPGJRBVBnA8DSoJ$--uE-L^A=$Z6x2I_a2 zU@t_!Edm0edLHdQhUxv@M_af)d=PCB`k^$Gj_buAzbE3JVE~yWh^D?pP~uRY5hS; z2{@y7&O!Gi=^IKQm#k-81WStku{WXfto}_;aHi@dbcI-&eh2+argZ%by>S`(xpe9N zIeiB0g`C$b>6B!qo81l zih1PgwX}a!ptrM!z$LxQr_fobpGQ|z6zNSgJulYVlCl#0viC))I0nIomKi@HUMt5K4LCNjlP(+YHRhE4nv?$UrYaGs9xXv z06H7=u~MMErmtQI@kagZYv63s>pn;KH0xKZf#teB?{QdY(a)ovZ`G%Hp>#u^nS)ZB zK70!-+|;k6>wnty_h{3sL$54{mQMY750q}{lPIj*rJtsmRk!|oCxGwKM?MV@z51t* zf%NH_e4y^vpBjR)0lmk4C>zx8kA%RG{@D;H8`kUEfOABD{{`qA)o-C3i81|$%3U<4eKmYp`1h)P4qsFQLre;JOuZ0fv9*rypq8N@?Fg2F6=x3pRxN zpcG;-+Q43@!KDjY!VDa`$uHax5e7&RhSE5+9XE(+gpM@qehylq3_=RVMH>R701;!5 z{SLWU!+hF@Jz=QG0Ejq)eHO?`!kYyXb-jC;g!EkX20OlAtG(*ZYG*jd&&v1pd&@LKADDx=apxgq01%~TY zuyD!nA4Tg64H{Z^6d5kxfQ4ei&|WxQV(@OGx5}Umgj}g%`%T!pV#v4y-^&bvbgf6Z z;Uxv+Dh%D5p!2FB`y_N$8m8ufR2hU6FQ_&QQ4(>DVcHv7Y7I%WH&JKce*{DIhIJGp zYcNFbhR$n-Z9VX|(NLd_Qj_5%S_6L-4MD6KC~DP)8<~Qp=KIbZWxx+QlZUI z_8;VK8n&KCsnf7IA8oe`0Ro738Qf?^+ihrE1Gyf9Qz9yR4a>?w1`I(;_%LY5W&zTW z;b=Rw3>(VN!RZl04b431h$axt5 zqm`+racTwNdKo|a1)Sc-kr8M)X4F#BosV%hB_{hC>u56MXDqr8aew1ZVhJ#=-URT0 zMn16w83%uZW5LGwdteDMF8Bg0p~kmd03zJ@;1W0^j6-DoxUujgltmg}T>v+ujPWw` zOSJKeEI^7ej$Q!HSfgqWI8PWYW6%<3y!|UIoHS0pgVHHu!%~PR7|*a#N;H-(hwrD2 zJ~|jWWBg12LrF#_S}G(PM`(JGVtkEqo6Z`apd74JqdV;Y^x)`M_J@cW*fS^-YC*SS%dM(e*pfP zvG_d*G#eMtwD7v|ZTfPx7ahM&^Bm%f`+^yWBOcJ z7&e}wQE|lBa~aA;jm!Q(FO3;{SrE8myhBU%3FBu&Xqz+^Qjqel@e%2qG8UcyvT37= z_Q&oSU)=^s_l>VC0+}_=_W|5T#;1;;&CXOxaTI&g>RAXln4EqCaWaLz33AvJPoHvU z)5WhqTue{VW|W)hUpljV)RaN@5V)JlYas4nVp?I{(_};WZr-Nf20@OQ*3mE7$Hb;t zrLXCqM6d*ymQu_k(6sUopbj$CHlQuolt{Cg5YuYB_UD^0MfnRhzu~Ay;D>q%HbdllWhh>P*j2z^2~xZz{ZPFb#*oP@_qH7i~?ZPbi?@Y?YGd`Vp`_~Wo@R{C`I(9>ERtzwwuiYehc^sn_Q+Kcgu8=u9@mFJ@)?t zn5LC9PV|{xr!i~5^ap*w22KCkz}}GQ`Zp*In?C13=ZGnK8l_Rw`i~$!W=dWQfVWMo zub^|>v~n}-O_;i`qBLpRJOqKerV}}+oH7m4Vb^JsALXsxGbPg!W5%?ey8MCZBYG+i zO_koLoHeD=CdeaG-LFt>XU=d1u{Q_PrnQ5)ni2~f&8hTiJDG=@L7dIs(+|wWY@z*B zSMx&p=pQl1*`v?g%)$T&95wsVtqbmEr`Mpx!<;}rSH0opg>p#@u`hoU!K3#{lVsdAS`7#hEi-g4{{-x3oon%Irsb zHt}Ze3iy|37E@T{w0Skf($ARhErOOLbKd{sS!PdHc$;F5UxtoMHOCJFOPcu}&AQUf z&lCZ5hWT%Iw4F2m&;&^5%^CFCXPOsM%5;|5wi^~Mm^1EyPaJe0ZC0o~2aJ0<)VK$}X8pD4VI+{5ZwIO3aJ07RKN z=sG+qH*fs~I4jIw$D#77d4vKJmFD&X5U(~br9P`MKU0NLt@*!rlYAMPq=}VxIFYI9ttYD1-KfdH?rN)@Dwuf=3@k1u-rD!`5o5B%^aEw-!VT=w?0pp z-*tfMNwbAUjl1UF6=<6>3y=c##I)I&VnO%JFDyspeY4A-D9xB_=s4f3dDI0tS?8Xz1k{pI zmZXmX-p%sp5I`KYu-K?{x0FRgnTMtAB*Z-}f_nhrW!X&|GTxS%Dr+DG)S!FO)hYrutdIq9*nab-3&t~E$dD~ z*(uApRd~|zmWdM29mPPadaAsSKi-F~W zB}fDp!!ae4-&0?RuuL*SA{Ov84eB|8Fc7Fm{tL!j7liS8>Yu{50k zq|27d|Gznw6LAo~VyU2&RGH;6d>6qa|b+1ez@K>4x8C%jdM7zHX7Vz?)?XWVat0oXCJZ5^#;IE z3;PLhj$7W;L+2e!O(|F=ET4P}vy+x8`nBG*JV&v-Da$>2JMLRNUIyok<;*F7e_&Bl z*yo`oMvl^~<&$0rJhHq?hh6Qg+vbAUTQAfDnS+&0*>;ZB-zdAm$+{#39dg+E;5mSB zwodEN=3*^(hap#M^t%9Y#44oA0^F>Lbej68^=T7ux?8K`V9&$4Z#6p0)A~AXpnF-9 z-Ti#82f_2`fAcNLaXFt>w766Db|COrFYi)Q!_xMTD#{#S(>%>cW|a#f1}@7hIM8G zAZ1$31K`ZEE~1Zcwsrnj=<5sCxs=wPW6j9`_+0Dre?e!S)qD-)qSev|E&0}UUJx&| zz9K;P6j=jJ)k9Hi1(`!DQOS$9Q4S+(`95*BK#3vWVat@Q?-2(PpL^(u7MTifYU>;|ipwzRHU zD=2*0Xw7{ATAHl>Ng&PEmJWztw@y-8N{f}X1T3xAZ8p$y!&*T9Kd#NX;w{*_X+1^B z-0jv)Kf+Ll^@$IFv(w6d2LiXOqdU;nWerY(y>6>B4ck4|JCq#JZ?)P&*?_f$mO_Kp ztMpWctR_1^8n!w_!0d=s83!_IZP^Q!F>CfHO1G^>dPd{c?&~PsvEHM53n#3vkHFBR z^|e4ehr3qsHndGy?I%&XZ%tSLEHl<6EwJ#wYWo8?A6l2wA>di-By9vdvVKGl$IdqL zEWJmzPt!iLgKg-~aMRItvkVrTY!hgbaoE=7JBT~m9;9tm7u#PS!XsDP)qg?t5!<)Q z@NnF0i_=kg)b?xo&AZ#mOelHSI?|q^r)~QaaN5gu%YP8}wk-(+%Q4$UZvw85Z8CkG zd~M5VM(t<2_*+=_w@sz-Gr-pMAy@+c$I*4iWm$dkra8*YGRv|o%UNkzslT#mX_^fi z@7{aw_q8-*i^@zdnkO0G2mnqo-k*e`IK~J2VP`zUhmNHuFgAoj z!)Zp)PZ)_aj2#pqILj!bZBioRv=&m57=JWCLo!1d2FK1Z-k_6hDUAQo!a9}VvKGUW z#u%rKZ8}5x9*oFf%v8eLOoqK1u4FNKsbb)oi${CIe0GAp6Zh(Omj2Sba?+W9>Mlf7us3>}VjbVs|E!Prh&nAZR77R}_Lqrd!g|UzlD|Z;5%mQBhGCEx*gFj-B&_AsA1 z4(*=Ip6@`pml@*)BUq(2H?&7Yd0Ewn4UYq=gW+ysrdl2<^t3n zWd21T4L|0xwUFY^e1YzbImG<_e=y=O^X{)`3}8Md2NuXodJEyQ${ zysd=VV@y^t>^#n__!pF+Om~XphcSJq06v^KNXxVc=7lJLNamAeXgtCEmX7H}G3Qe% zC7NlbSV9c5D-C_I%r#Fz!%60$H5j^6%ny7nyaGi!5eFU4=)Nm}{1Uq=dPd0z{?E$7sb_#@tN1$a1E_1d}c^Lugx8 z!F(wgYOgT&)j`Tt=Bxu~yvE#1DT6BJn|r{1gPAi2pqiQdB0vrEIXXmhlR1Ox6>FL0 z^I+L+X37tcQqTOFe&`L%9UGvik@@Ev7_%lOI~@;A)06fqoy=%T4&7sR>;z>Ov&9c?b~9IP$4k`1Y@**^ zFLR(AR`)T_QNZ**b96H(`F#kY@n=S(AUmz(cG{ zbZOCHR^0m#9l&as0doUce<$LJ9btWP1|W#_!4gObW}W{UjvZqKMuG1*tBC%=G?X>( z2atrZ3iXf~&bmUku1B!szk?)_)e{AV6D-RzXozAB4q}vIS)~*@KFNA%KN?T5GS-42 zj+N&H_IOqSmEo~L?-Kvd|+9unJob4S?AsbUp6a&K9M;r z8-+e{S+|~m)p@Mxf5Vo1R*MGM1y&N(fE2K76oo5faesghMXVvJ!@bCwwh+RKSx4xn zeTnrw#mh@r(FO=BW$oStH_KR=uRvG@OF_ZSD=epT5O$RnzZ~XXW0~mwkn5~QKZvek z{Yz`i8>~XAldERkEC8rsExr$un=Aw6`){!xhC^Q+>&^)LyUnVi?QuQJWfy#CU^$P1 zq=|KuBD2k`i7D9G!qOgs=sT?14uHF?FI>^r#u9!7DebIJ=&)o5>-et#ovbZ%80H?U zm&D%I^}y%Y#@`&fInK*N1jT`(vISg+9UVUQI{pU4NSRg_j8VhvE% za+vi!twtZRvME|P%3{BV#xd5ktDqcbMeK*0k6258fe(|c$LJ?I#VV$U>cl=hA67fF z)9It(!ggH;bKTh2egbf3zuymG9_-&}JHChgCk6OC+1clT?PFg!0nz)}Kl*^gi>)jG zgExC0A5whSqZCU&z;@KYm4oclgHY?oj-t~+{_HQuF}jD?(G(R6U~jz)rvus7DA;&} zeVx9PLF^ar0t;r_e}$qD_A!58$Jm1XU_Z`I{t8$qd%;dnhOzg*4n+~{qhe@}WIwnB zS5B}Gy2H*Wc4rDSM6)X=Atjc5(~Q28?Ap(v?-W~2Ma%K*_s+qV1a>lQVotLYUxLg; z_T$&^79_C+Yk(!Q$7tVij{P~s4pZ1CYhXkwdx;1#)7S|`5SGrqK&P}a*k|rSZ5F%m zDiob(o6HcM&7MV3@Eo?W8dxs-fDV-TY#-WCU0@G+gR+3#dIZB$$mYHZMMdoCIgojg z{n0IuTw*T?2UfyfxD=vG*){$kDP!jyg|Kq=V%msRu-8+$#})QEngFk|f26YEYwXuT zVCQu~B zv%8?ZfjyHd>KfVoslb}pKaWFnGy4?Xa(jpU)3fm5F8jr7FtoDO@i3x|?P-C&cD8{J z$`1CwHL$ajy?gMgRh(2Hyxmdz33YHdf8J{P0`1`O3CN@>~%U=*3XWmF!lhu z=_^PXWdHRnWIkYXXbUyO?tce;!|ZrUK98_9zTkVvexQf;QT9@rILFvkv9#%VXzO003XU=b3cwbyN1-I~wTsiUkfVpwW$pv%9T7ezq{6XKU5KbXodU}i#WP;k`oZULO8Or&^04$6%i!!L; zoYBpY8Nms*qcM`>{ymIH;7Hej@-*l18_;luGi3uv&toXweVI*YTV9x~5!xb(}(=6vD~z8sD=77V$ZwpTFnd7Lr2u_vGN@mBC% z;A|g(odujhs;eyIn6`kVh{K^Gzl)r05;PWbZl8nNOPq{@041EM+fY=>DVhU2%Q%Jf z4wiFbmO{~GPIWOvS8%q_g+^C66XP)ODyN$k^4B;4uc7ZcXTvDiD>?t8`p7B{o0fMs zIQ$1tRLwa^cGhrCeh4FOa(<%xW-aH#J7BoQ;nK@j$LUOlzT2E>Q~+4daiv{r1INA< zl#QIducEPu^9*I7?r_%8ZtyN=iYBX8P70k{YU3>0kB8IF+4Tezb#TU1FtC$Tmx#uD zoZsn9?&7>WfW~f4YCOiJhx17u`g%E^tp`INr-K%r_c>XuXzb_M4ngz)r|A#q8{|kQ z03L9b{|H-#I9n*4KFmq)hT0L%1qrZ+9N&Ln{3s`#!VP1bx;0=Q=lt~^2I~>$Y#v5p zg7Xg*O-^#0IbfLLm|uVqPTUGB8lAcRlhE$MJ^ebgyK;|w40GMM?o@%|&NWhrng=(A z(hz&NGihD!$t|Wj+`U{6ic9U|dYI6-pX*PPxEJ?jy4S&%+Y=9S4{+b1e853&36+TY zasQ^GJAdxt|3Tj&uI(&rIm}&6NrC|GWIj9!&y9Eu+7r0H&Iie9 zu7)c3&Tu~}fPZJXCWxZX6EXL57ige_Uzoev@GJokNyW@mHnWdqCMdNhGAm)r6&MCWn+qyYI` zXA0L|;6^8*uYh}<&hZs;l@{<7asL>D=!@L=*C4u>n`Op;T;hH~o4XROcseLcxlz*~ zrHp&)Eodm`ezpkMW$quJKxPH^MXHp!!u9(N!me_&lOgOHw~0=jUgxrC<#>Y|L(98r zE|-GgHQaityST+2oB_w`xVE*Bd7Jy=TM$;y_1y*|8n|!12s<0O>SQo9aet!la5Hy> z7eEU)BMvg}aIYr9vb)^CBuHuHIw%6!#yvwPR@%8=XMnPUyMQuxo!lgfiQnV)NT8^T zJ3u#abaU_0+|$GD{{TbY%PrmqhCc4f{{mUu4=5Pk&pk5-iUzoT(;#J#`$Yp9A8&qCigw|WYeJ>qV2g_H^IPCBVH z$$ei3$ELV!`aU@EPS7mn%quwr5*J-i1!5@C_l_AoenI3xA_W40(sxRjK*NzqylP>^1j>wJ41MfD03dlyBrREVZ5QO zz`}V66yJ^D4cGx9d2))$o#1^)DVQkUmsDOE&67rgGKTjCP3f^b1r`0A_lXuGx8ftlGHIR9W zw}JwZb-W&0{odx)y#TD9_f8~01Md$C=r{5{tpj@#Z_a)&H1n3xufK)YUJI*Rc_p+W zYvT!v(AUoU#R6M8c)Q+#uuk3mgS^jbAnXC}lodaqAzoc4Mt7LkPIcQOykyGpJ>+q1 z5IxEh?u371ydXNAKF+&67krO+BlKCC;Qd&PzDZvCi(sGPy?+M!ocMq3h7rzu{X)3n z!k?hm)Rq4#{lB3b|EG57bLTfqgGnCz)=*IH;qMIui6`HQ7M^?guTkD&AAc|w8us&@ zi(rHoKk6+A^XA{Cm&k|TP1Odz{KuYvxd-@5SHYx%{8y-w#E(A_0N~HxRtOD;_)}c4 zALi#%6d-`Vn<_~H`StV|kMP$&3(6pVBW=!u`E%(Y*HQkL5ugm=@1%=Ej`4M~;Mj4# zD@8Iw`Q14HVSFVMeBu0y6(EV=m$?9oh2qTdn^$TPs@n5(F<5T#3Lm)}z|NS-wB#m#O z?RYwW6Qx`;_&aEN%H(HKVNW)HGzB1s{~hJ4a`_vhz>vpx`x79a-?;<&F7UU}(yxHO z-wH*A{2%W?Q4#<1N(j5iPoWiVF+Y7Se80qBK&z(`{_E!KmLR*<@`We z-d*MwP{~*Y|LZvbSNN0F09W}>Z$sZT{sszNUFTQ5hWDkC&!P`|6+dMy^xfdsEka*4 z|FIkN%i(Wjpz$U@s1_u({0&c_?-u{@7Jxc_

&Y^XoE!)$_l}fQANsiwhVU`S1DQ zIW+N)lAX0KOHi06(qVtn1^7U4wQQY*XZl(DcHFQR__;BKfw@q z3HDPw#9Q#gJuvtPMs5K33V07-=K;Yo71$374*!TT^AjXev8=yfemuY-!HOg_9v1A| z0LlQt;{m_|1-mG$bwm)X1WAw}o92*U!48Tw9~JyN3M@q6ppD8gK`k5LxPa3R4WWXC z>(Cb=7#zcZL<)|qhDRp^%PB(~B^aX1a-s!E43NYKHp^jrtl;bUXgn#n{vyCB!Rxdp ziW4mP3Lsu!rzB5;z?rU^I4zj73kIGM)ISGBX9W^ZXh;-zQ)E3!@GO1Rk_DgBO6Q#5 zc{)^`A~V~1+ysnnk7hG32)B}7)jvE7JNwS zQFraI8=eO117qf~+hsToicF(yv%> zg5Hozf;p5LE)l$S3Ojc+m$8cNlUJ|UX7p!nXV}rn*ikcb)T@=V_66~!2d$WKQ10z}lb02{6j^KG6 ze7GxUqeCsN0+%S*(k8f74CC7c=j~v)C-D0YQo00{n_zXfz&{b7N5J?2B)x(+N+GOI z;O&ma`+{^@8ubf24xn*BAg0gtpg=;0d4~n-XrVMB;8D%&L%}#*vNI|u8-TZCf;}cM zj0<*Ay5y1IIZu#G2s--EI4Su07c@=@bpOIK7vWBtCtQWDl(%;iCNUw?UD!^i7CnT% z8VtxDVNoO+_Y3t~Algf4q&23ua2nBn5;h;ibBGf@{v@!|LU|W7oDrr|{nA;Xn6?VZ!WlIEo)bn;+yp2u2oLxbfBk1n79E9<-+B(0lzF9cE(^;2)|XqziYyLx(e*N&?y(9D}@Ul2Uaayy9InT z!k6enbW^yf9#+>0A4vgj3x7NcP%j*$0;DG4Y|`E=oVtnuX%Q~G3nN;Eqql*z3BTP3 z1KWka(Mt86a4sG9?h=0523xv?RdmHHtv=zYIMP4RQ zdWuHqaOPf-2hFYfMBls!(cYpKiVymT+-T3`D>8hCXXGb(it17PMIX}DK!-%jc0*sF zs9y%YBO*^4!61?MOTa=zr(ee?9TN?%0yr*8n1#M@(fDJK86mpD0TwCp{1=u*i~d~? znK7d5;}8}rI&mKQ&WhZA21pcL^9E&-XyOB4$)bhd0Xrx1r#O46D7ggeX`u@dU6U z(JVW_MUnDb*itNFy#qH(MDA2^Rw^o?_qt59<^j}}i>h2;#AVTw^i``6?QR9QDr%HM z*fmim9j?7D+Dhj)D@BXwtXGxjWgSRvh&IvDpBhmfeS~j{9zF!96|MUYl($4_<6y57 z3IBi*^`f7D!?-kvf@%HID7r{Xqb5-|8(6c*lL@{SQSQHZjCVx)#?W_Hv>+RzTSd#F z;d`4X^$3h_7wx$ZVI3l`j{rJF*XTvLCrYHyT$gC-JGj{+T0wX1^oo4wF19|An2Pc5 zi%wL++=ypx?BUSU(*k&f>LGkm4eKnu@4g#cuzDXgBdYG_$*l!|BYO zhj&hx8BE(PGy+XowNFGQb`y zzWzEIPm1SI)bEto=O*lo7q6jZVS@O;^JqLR7QF&+M!c&Uwwx8;7y?KX$1A{|B>o`_ zShD!)3}ENPU(s=f6tRxpr8IFH6+ESjV?Kh_8R9q7Fj$%5U9W*MOYHwONY0BrsSG%WPtZ5ug1Ewp-*ka^E)`f6iodIalp=Ag3>q$q`@R5su{eZ2-j~E~ zUNE9WyfqnoWn!ftuyXMmbZ7Bp@tjXFSQX+Ap9gkDY$P|YiPZ}s^SZeA8-Pl2IHeD( z#Bb5A;D*?<5W`a~{@w}=HR4hjK5^+@Xt*!Vq^g~M@%dLFdO-Z~R*(#d z9rchoEM7;u-4Su-O^ALdp0@@hqvBB7lZ=TyXkRrh&Qqc9k@$lj!8aj(nG&LtVqYD= zl=#jg80aL~MW?%*CCyZ3?jm_R3yrRl_x}4KNUG?#o4e%96m0R3L{O3R9>k2G-BWUd z?%UogIY^7B{gNY;G4hgJ_!Zi{B|CP4(noTl8YI4w9NP69kkpGXbpDd!XW;uG$pJYm zJ1i+F1!aK5L>GAkN*_hi5S{P1B5|ed@l{C`)oWan zw0r>V*CnHLnMI}K6<73COP=6CdyV9a7BJkD?D`D)>Ll}j1;cI0%0MvGOAHZcY?RD8 z1<_5C@7jPhORmshwMaUOp!SZ0N0*efN^mDvGrTVi-=@#1foseq(EBusNX?qnd?UR8$MrsHINvyQL4JMtGZljuvIB8l2`r@TS zRM?Xsok`)T)6#q2!@o099c8x8O8@*FQWB-<>%pERolDbUveeTTMx2wrMp?ZS=~lXp zDOLK+VlZS#+53QHO2rf~&5{luh7UQ?va9IJm0qK3EAyngXM!(Z+C}GcE=Wh|EhvzF zCWI@6(i5~;D3V@T2fm9^;W=1VEOn+Lj!V+%lz1qSj*P;BfhI9!{Pu0>{ z!Dy_JuKp2?H>IC6!OdFf!anG`B|YH)Rww=W1VrDKiYba(FHKnt0~@4IXMnF!`o$Jt zP15lBU}%49_&r5%T)Ep(I0uyprT_%I^ z7Jy_z>hub*NvYRQ;G2@hQ~JV1cIhh^?<%|bI{MsXJzt@3kL*o4-s34-TMcZl>?4Ym z?2}EWIX-fBzeMEKszOtv?fgO;w(6;5EY~=%x_{psFn)=I@ zP{!eqZ0#9fhh^%YAtgXoL_=rnIvE@yn?^Cf zW3qFUtv)XE-VI@)viCD!e3*>$JsQJhztzKs2w5Px5-H23H{^tDgB#q8lC@FEO0=xt zB{0OuRy{yttZX;s_)f}3*F)GT*%_)qPLMrZ0dQJYdkbpM$iAka_F38F=U`8iCD6SG zNwNixLv*sN{W#Q~lTG~!<5OgDwUCl3n{^64q{*5WgCSk^I2oTI+t3OuQoDTHEJ=hx&X%Q>Ltl<8nLY)%vXRZ8%#+1ULT0`!#{yR_$XcqPs6h5y8Q2SDvMV4d zlC5qB!$nz_7_Jn{o>~o(OR}|ZgReyP_GZ{pDr=*&@ny0M+N+hzKA{c&W!W=FK~fSf2Mp07dXpkPO%Y#yBtZ<4K9fMIQx z>FD;Z7THY|z#ZA%Z2)&=uYC)WR@whr0or6whhmi4Wj}p}z7Cnk2awV!Q#_96a8LI8 z?*Lu0R3XgmmZeiwe2*+@Bkb&z?YIiQe%Y^dnsY#wmyNzb*=$Ne4$F#ZK|UgT`CSap zL)nb?pvXy{`5}O_JmMQT<|3a>5f@i^4IPqolfU{AfV=#wA!zrI|4!-AJ@O~+19-|c zdja;z&&NabetF|>5bY)BPC$yce0o0meB|D3u*FwCgNF5>e4+`Ie)6P1X!n=r&x4{v z@^9(5{$cq-`o;yw<8PudP~J)@!Xxq{G<5~Zhwq{>Sk9t7!clqCA~1x=SyYE~OrB5q zoa1uOZ!y-Pa(|l0!sNl70O9gI8fcG@TdF}BDL2v~j1%$}8nY<550!{U%YQowk{J0> zigCuu-RZ>NNx676Tsb9A-UcjAE~da>ynGuK5+%r2{sqd@@(n^@iSlhEEJ?md3=PTh z)nNeVybOn!{&70cyEX)SeGzKe2174lup;JYGc&`J5L z^4jMBuF2QYPWZa~w*;uIl((#cEmiVGdVm}9CdxNf%d5^qN{!t6dr;n#2U04fPOhT@ z|J(BSr$bS_Tu-Z#2KfgRscDpd8V1o#^23x;ZkBh@@~1_<`%g69k?*y`mAi7~b{O9( zFS`WxHu);rP_@g8mq1^KJmkO4fjo-tSh^<{WJ7J2{I^&zbjzQQf%YExjb_N~l@C&V zYoEM_)?oMLJ`}j_m!J3<*ns@CEf75@ue^aL{XpJK)kQ<{gOm>+mJc0*lo7dwf&mZZ zQ!~&wD)*xl{g~X3N_@xVvuHE;Xq%L*$fc^JbBe8W6;X;pLchjTMIhDrrzsAu zf|PWH^L6-;p>X;DjhTu;Dh$a|1g%2jc}2JfT*+4a^$)b?ClOcNLt}%YgpOl2DxM!iW0T?^s(Wfyw8L5&0_hluSIJ?EVg-4=Vo*2c@6#8wz9lE1wt#IHX)eX^+FodAA@sK>0`pEKu1m z2g4ENszV?NQu4M|E>F{Gp@Bb?zws`C6akfbT^{}&-w zvW6iuOBo}BzVpgXy3;pTd6E8~D^L0RH;|IAj1r=;P$_*3d_~GP7o+c@(z6%-l_<~s z0<2Uy{0$V9Df4$jScNiz?7X6MTm-{a<&pqszp30nE8|*aSsHx5rJO^1*gECoSHO2$ ziSx5~g_Xf{8)&2QSvrs2q^zd0lx8I-4T|n6k2j*RRr!#-ZBy?27Jco?+IBQ{DCZr4 zot;YK0r+=M8C#B#=u!?n2}Rw?Hz?lIqul-?7g5)-vj^DD41<+>a=Hm=cm|E$s?_PA^igf2!-T#nwimt0DsD0Q z4yq<8uHmP8mp<2lsu@EdIigCVFLRLUO<#}%t9+LNJF5C61+Ijst}g+@G1WavmmF8w z1~5F4s_5ro=LyvlE1)(?b)LRz(W==Rj9HB81g*$oRjcT-zmuwuA3^3Rl}{%qxx z4t-};&(KFWQS}b}6I7DQbuVm5R$ZqI$2pZK2Uv@4nn7vm zY*io~QpizBXiJl;VpG&FPj!=S3@K1Om5=c(R5jB9jUv@CGq8)Q?{#1(R`pXR?UKsg z56enaC1x;`s+N8VnPsZ8YBZLs&eH1lvdZ-&unN@@Pk`&Hu2&(fQdQIl->X!Oo1pK8 z>f4Jjsakb87OvE&_9_8xs+K(q4fU!*N^~@+Jn56%sPd-!E}B$-(C?vHl~2WwEvg^r z=-nOFz00z|L%S|4cOIs8j!izFhUL3>cWFj-*&# zzFOphfxM`e(&!ee|MxerOX^vajVMuv(0063{WewDl&RNK?7mz*|15-EQ}3sfy4Th3 zQM|QM{g7@psZx*Hpznsd?*-UWt=_c{`fAjJ-mvAi8fkmHXX@Xmtf)aYuUsye+{@