
P2_SETR2.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000188  08000000  08000000  00001000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00008010  08000190  08000190  00001190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       000000a8  080081a0  080081a0  000091a0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  08008248  08008248  0000a064  2**0
                  CONTENTS, READONLY
  4 .ARM          00000008  08008248  08008248  00009248  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  08008250  08008250  0000a064  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08008250  08008250  00009250  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  7 .fini_array   00000004  08008254  08008254  00009254  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  8 .data         00000064  20000000  08008258  0000a000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00008c28  20000064  080082bc  0000a064  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  20008c8c  080082bc  0000ac8c  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  0000a064  2**0
                  CONTENTS, READONLY
 12 .debug_info   0002805f  00000000  00000000  0000a094  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_abbrev 00004f6d  00000000  00000000  000320f3  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_aranges 000023b0  00000000  00000000  00037060  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_rnglists 00001bc9  00000000  00000000  00039410  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_macro  00005578  00000000  00000000  0003afd9  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_line   00027b85  00000000  00000000  00040551  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_str    00108711  00000000  00000000  000680d6  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .comment      00000043  00000000  00000000  001707e7  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00009c5c  00000000  00000000  0017082c  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .debug_line_str 0000005f  00000000  00000000  0017a488  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

08000190 <__do_global_dtors_aux>:
 8000190:	b510      	push	{r4, lr}
 8000192:	4c05      	ldr	r4, [pc, #20]	@ (80001a8 <__do_global_dtors_aux+0x18>)
 8000194:	7823      	ldrb	r3, [r4, #0]
 8000196:	b933      	cbnz	r3, 80001a6 <__do_global_dtors_aux+0x16>
 8000198:	4b04      	ldr	r3, [pc, #16]	@ (80001ac <__do_global_dtors_aux+0x1c>)
 800019a:	b113      	cbz	r3, 80001a2 <__do_global_dtors_aux+0x12>
 800019c:	4804      	ldr	r0, [pc, #16]	@ (80001b0 <__do_global_dtors_aux+0x20>)
 800019e:	f3af 8000 	nop.w
 80001a2:	2301      	movs	r3, #1
 80001a4:	7023      	strb	r3, [r4, #0]
 80001a6:	bd10      	pop	{r4, pc}
 80001a8:	20000064 	.word	0x20000064
 80001ac:	00000000 	.word	0x00000000
 80001b0:	08008188 	.word	0x08008188

080001b4 <frame_dummy>:
 80001b4:	b508      	push	{r3, lr}
 80001b6:	4b03      	ldr	r3, [pc, #12]	@ (80001c4 <frame_dummy+0x10>)
 80001b8:	b11b      	cbz	r3, 80001c2 <frame_dummy+0xe>
 80001ba:	4903      	ldr	r1, [pc, #12]	@ (80001c8 <frame_dummy+0x14>)
 80001bc:	4803      	ldr	r0, [pc, #12]	@ (80001cc <frame_dummy+0x18>)
 80001be:	f3af 8000 	nop.w
 80001c2:	bd08      	pop	{r3, pc}
 80001c4:	00000000 	.word	0x00000000
 80001c8:	20000068 	.word	0x20000068
 80001cc:	08008188 	.word	0x08008188

080001d0 <__aeabi_uldivmod>:
 80001d0:	b953      	cbnz	r3, 80001e8 <__aeabi_uldivmod+0x18>
 80001d2:	b94a      	cbnz	r2, 80001e8 <__aeabi_uldivmod+0x18>
 80001d4:	2900      	cmp	r1, #0
 80001d6:	bf08      	it	eq
 80001d8:	2800      	cmpeq	r0, #0
 80001da:	bf1c      	itt	ne
 80001dc:	f04f 31ff 	movne.w	r1, #4294967295	@ 0xffffffff
 80001e0:	f04f 30ff 	movne.w	r0, #4294967295	@ 0xffffffff
 80001e4:	f000 b988 	b.w	80004f8 <__aeabi_idiv0>
 80001e8:	f1ad 0c08 	sub.w	ip, sp, #8
 80001ec:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 80001f0:	f000 f806 	bl	8000200 <__udivmoddi4>
 80001f4:	f8dd e004 	ldr.w	lr, [sp, #4]
 80001f8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80001fc:	b004      	add	sp, #16
 80001fe:	4770      	bx	lr

08000200 <__udivmoddi4>:
 8000200:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8000204:	9d08      	ldr	r5, [sp, #32]
 8000206:	468e      	mov	lr, r1
 8000208:	4604      	mov	r4, r0
 800020a:	4688      	mov	r8, r1
 800020c:	2b00      	cmp	r3, #0
 800020e:	d14a      	bne.n	80002a6 <__udivmoddi4+0xa6>
 8000210:	428a      	cmp	r2, r1
 8000212:	4617      	mov	r7, r2
 8000214:	d962      	bls.n	80002dc <__udivmoddi4+0xdc>
 8000216:	fab2 f682 	clz	r6, r2
 800021a:	b14e      	cbz	r6, 8000230 <__udivmoddi4+0x30>
 800021c:	f1c6 0320 	rsb	r3, r6, #32
 8000220:	fa01 f806 	lsl.w	r8, r1, r6
 8000224:	fa20 f303 	lsr.w	r3, r0, r3
 8000228:	40b7      	lsls	r7, r6
 800022a:	ea43 0808 	orr.w	r8, r3, r8
 800022e:	40b4      	lsls	r4, r6
 8000230:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000234:	fa1f fc87 	uxth.w	ip, r7
 8000238:	fbb8 f1fe 	udiv	r1, r8, lr
 800023c:	0c23      	lsrs	r3, r4, #16
 800023e:	fb0e 8811 	mls	r8, lr, r1, r8
 8000242:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
 8000246:	fb01 f20c 	mul.w	r2, r1, ip
 800024a:	429a      	cmp	r2, r3
 800024c:	d909      	bls.n	8000262 <__udivmoddi4+0x62>
 800024e:	18fb      	adds	r3, r7, r3
 8000250:	f101 30ff 	add.w	r0, r1, #4294967295	@ 0xffffffff
 8000254:	f080 80ea 	bcs.w	800042c <__udivmoddi4+0x22c>
 8000258:	429a      	cmp	r2, r3
 800025a:	f240 80e7 	bls.w	800042c <__udivmoddi4+0x22c>
 800025e:	3902      	subs	r1, #2
 8000260:	443b      	add	r3, r7
 8000262:	1a9a      	subs	r2, r3, r2
 8000264:	b2a3      	uxth	r3, r4
 8000266:	fbb2 f0fe 	udiv	r0, r2, lr
 800026a:	fb0e 2210 	mls	r2, lr, r0, r2
 800026e:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8000272:	fb00 fc0c 	mul.w	ip, r0, ip
 8000276:	459c      	cmp	ip, r3
 8000278:	d909      	bls.n	800028e <__udivmoddi4+0x8e>
 800027a:	18fb      	adds	r3, r7, r3
 800027c:	f100 32ff 	add.w	r2, r0, #4294967295	@ 0xffffffff
 8000280:	f080 80d6 	bcs.w	8000430 <__udivmoddi4+0x230>
 8000284:	459c      	cmp	ip, r3
 8000286:	f240 80d3 	bls.w	8000430 <__udivmoddi4+0x230>
 800028a:	443b      	add	r3, r7
 800028c:	3802      	subs	r0, #2
 800028e:	ea40 4001 	orr.w	r0, r0, r1, lsl #16
 8000292:	eba3 030c 	sub.w	r3, r3, ip
 8000296:	2100      	movs	r1, #0
 8000298:	b11d      	cbz	r5, 80002a2 <__udivmoddi4+0xa2>
 800029a:	40f3      	lsrs	r3, r6
 800029c:	2200      	movs	r2, #0
 800029e:	e9c5 3200 	strd	r3, r2, [r5]
 80002a2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002a6:	428b      	cmp	r3, r1
 80002a8:	d905      	bls.n	80002b6 <__udivmoddi4+0xb6>
 80002aa:	b10d      	cbz	r5, 80002b0 <__udivmoddi4+0xb0>
 80002ac:	e9c5 0100 	strd	r0, r1, [r5]
 80002b0:	2100      	movs	r1, #0
 80002b2:	4608      	mov	r0, r1
 80002b4:	e7f5      	b.n	80002a2 <__udivmoddi4+0xa2>
 80002b6:	fab3 f183 	clz	r1, r3
 80002ba:	2900      	cmp	r1, #0
 80002bc:	d146      	bne.n	800034c <__udivmoddi4+0x14c>
 80002be:	4573      	cmp	r3, lr
 80002c0:	d302      	bcc.n	80002c8 <__udivmoddi4+0xc8>
 80002c2:	4282      	cmp	r2, r0
 80002c4:	f200 8105 	bhi.w	80004d2 <__udivmoddi4+0x2d2>
 80002c8:	1a84      	subs	r4, r0, r2
 80002ca:	eb6e 0203 	sbc.w	r2, lr, r3
 80002ce:	2001      	movs	r0, #1
 80002d0:	4690      	mov	r8, r2
 80002d2:	2d00      	cmp	r5, #0
 80002d4:	d0e5      	beq.n	80002a2 <__udivmoddi4+0xa2>
 80002d6:	e9c5 4800 	strd	r4, r8, [r5]
 80002da:	e7e2      	b.n	80002a2 <__udivmoddi4+0xa2>
 80002dc:	2a00      	cmp	r2, #0
 80002de:	f000 8090 	beq.w	8000402 <__udivmoddi4+0x202>
 80002e2:	fab2 f682 	clz	r6, r2
 80002e6:	2e00      	cmp	r6, #0
 80002e8:	f040 80a4 	bne.w	8000434 <__udivmoddi4+0x234>
 80002ec:	1a8a      	subs	r2, r1, r2
 80002ee:	0c03      	lsrs	r3, r0, #16
 80002f0:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 80002f4:	b280      	uxth	r0, r0
 80002f6:	b2bc      	uxth	r4, r7
 80002f8:	2101      	movs	r1, #1
 80002fa:	fbb2 fcfe 	udiv	ip, r2, lr
 80002fe:	fb0e 221c 	mls	r2, lr, ip, r2
 8000302:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8000306:	fb04 f20c 	mul.w	r2, r4, ip
 800030a:	429a      	cmp	r2, r3
 800030c:	d907      	bls.n	800031e <__udivmoddi4+0x11e>
 800030e:	18fb      	adds	r3, r7, r3
 8000310:	f10c 38ff 	add.w	r8, ip, #4294967295	@ 0xffffffff
 8000314:	d202      	bcs.n	800031c <__udivmoddi4+0x11c>
 8000316:	429a      	cmp	r2, r3
 8000318:	f200 80e0 	bhi.w	80004dc <__udivmoddi4+0x2dc>
 800031c:	46c4      	mov	ip, r8
 800031e:	1a9b      	subs	r3, r3, r2
 8000320:	fbb3 f2fe 	udiv	r2, r3, lr
 8000324:	fb0e 3312 	mls	r3, lr, r2, r3
 8000328:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
 800032c:	fb02 f404 	mul.w	r4, r2, r4
 8000330:	429c      	cmp	r4, r3
 8000332:	d907      	bls.n	8000344 <__udivmoddi4+0x144>
 8000334:	18fb      	adds	r3, r7, r3
 8000336:	f102 30ff 	add.w	r0, r2, #4294967295	@ 0xffffffff
 800033a:	d202      	bcs.n	8000342 <__udivmoddi4+0x142>
 800033c:	429c      	cmp	r4, r3
 800033e:	f200 80ca 	bhi.w	80004d6 <__udivmoddi4+0x2d6>
 8000342:	4602      	mov	r2, r0
 8000344:	1b1b      	subs	r3, r3, r4
 8000346:	ea42 400c 	orr.w	r0, r2, ip, lsl #16
 800034a:	e7a5      	b.n	8000298 <__udivmoddi4+0x98>
 800034c:	f1c1 0620 	rsb	r6, r1, #32
 8000350:	408b      	lsls	r3, r1
 8000352:	fa22 f706 	lsr.w	r7, r2, r6
 8000356:	431f      	orrs	r7, r3
 8000358:	fa0e f401 	lsl.w	r4, lr, r1
 800035c:	fa20 f306 	lsr.w	r3, r0, r6
 8000360:	fa2e fe06 	lsr.w	lr, lr, r6
 8000364:	ea4f 4917 	mov.w	r9, r7, lsr #16
 8000368:	4323      	orrs	r3, r4
 800036a:	fa00 f801 	lsl.w	r8, r0, r1
 800036e:	fa1f fc87 	uxth.w	ip, r7
 8000372:	fbbe f0f9 	udiv	r0, lr, r9
 8000376:	0c1c      	lsrs	r4, r3, #16
 8000378:	fb09 ee10 	mls	lr, r9, r0, lr
 800037c:	ea44 440e 	orr.w	r4, r4, lr, lsl #16
 8000380:	fb00 fe0c 	mul.w	lr, r0, ip
 8000384:	45a6      	cmp	lr, r4
 8000386:	fa02 f201 	lsl.w	r2, r2, r1
 800038a:	d909      	bls.n	80003a0 <__udivmoddi4+0x1a0>
 800038c:	193c      	adds	r4, r7, r4
 800038e:	f100 3aff 	add.w	sl, r0, #4294967295	@ 0xffffffff
 8000392:	f080 809c 	bcs.w	80004ce <__udivmoddi4+0x2ce>
 8000396:	45a6      	cmp	lr, r4
 8000398:	f240 8099 	bls.w	80004ce <__udivmoddi4+0x2ce>
 800039c:	3802      	subs	r0, #2
 800039e:	443c      	add	r4, r7
 80003a0:	eba4 040e 	sub.w	r4, r4, lr
 80003a4:	fa1f fe83 	uxth.w	lr, r3
 80003a8:	fbb4 f3f9 	udiv	r3, r4, r9
 80003ac:	fb09 4413 	mls	r4, r9, r3, r4
 80003b0:	ea4e 4404 	orr.w	r4, lr, r4, lsl #16
 80003b4:	fb03 fc0c 	mul.w	ip, r3, ip
 80003b8:	45a4      	cmp	ip, r4
 80003ba:	d908      	bls.n	80003ce <__udivmoddi4+0x1ce>
 80003bc:	193c      	adds	r4, r7, r4
 80003be:	f103 3eff 	add.w	lr, r3, #4294967295	@ 0xffffffff
 80003c2:	f080 8082 	bcs.w	80004ca <__udivmoddi4+0x2ca>
 80003c6:	45a4      	cmp	ip, r4
 80003c8:	d97f      	bls.n	80004ca <__udivmoddi4+0x2ca>
 80003ca:	3b02      	subs	r3, #2
 80003cc:	443c      	add	r4, r7
 80003ce:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
 80003d2:	eba4 040c 	sub.w	r4, r4, ip
 80003d6:	fba0 ec02 	umull	lr, ip, r0, r2
 80003da:	4564      	cmp	r4, ip
 80003dc:	4673      	mov	r3, lr
 80003de:	46e1      	mov	r9, ip
 80003e0:	d362      	bcc.n	80004a8 <__udivmoddi4+0x2a8>
 80003e2:	d05f      	beq.n	80004a4 <__udivmoddi4+0x2a4>
 80003e4:	b15d      	cbz	r5, 80003fe <__udivmoddi4+0x1fe>
 80003e6:	ebb8 0203 	subs.w	r2, r8, r3
 80003ea:	eb64 0409 	sbc.w	r4, r4, r9
 80003ee:	fa04 f606 	lsl.w	r6, r4, r6
 80003f2:	fa22 f301 	lsr.w	r3, r2, r1
 80003f6:	431e      	orrs	r6, r3
 80003f8:	40cc      	lsrs	r4, r1
 80003fa:	e9c5 6400 	strd	r6, r4, [r5]
 80003fe:	2100      	movs	r1, #0
 8000400:	e74f      	b.n	80002a2 <__udivmoddi4+0xa2>
 8000402:	fbb1 fcf2 	udiv	ip, r1, r2
 8000406:	0c01      	lsrs	r1, r0, #16
 8000408:	ea41 410e 	orr.w	r1, r1, lr, lsl #16
 800040c:	b280      	uxth	r0, r0
 800040e:	ea40 4201 	orr.w	r2, r0, r1, lsl #16
 8000412:	463b      	mov	r3, r7
 8000414:	4638      	mov	r0, r7
 8000416:	463c      	mov	r4, r7
 8000418:	46b8      	mov	r8, r7
 800041a:	46be      	mov	lr, r7
 800041c:	2620      	movs	r6, #32
 800041e:	fbb1 f1f7 	udiv	r1, r1, r7
 8000422:	eba2 0208 	sub.w	r2, r2, r8
 8000426:	ea41 410c 	orr.w	r1, r1, ip, lsl #16
 800042a:	e766      	b.n	80002fa <__udivmoddi4+0xfa>
 800042c:	4601      	mov	r1, r0
 800042e:	e718      	b.n	8000262 <__udivmoddi4+0x62>
 8000430:	4610      	mov	r0, r2
 8000432:	e72c      	b.n	800028e <__udivmoddi4+0x8e>
 8000434:	f1c6 0220 	rsb	r2, r6, #32
 8000438:	fa2e f302 	lsr.w	r3, lr, r2
 800043c:	40b7      	lsls	r7, r6
 800043e:	40b1      	lsls	r1, r6
 8000440:	fa20 f202 	lsr.w	r2, r0, r2
 8000444:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000448:	430a      	orrs	r2, r1
 800044a:	fbb3 f8fe 	udiv	r8, r3, lr
 800044e:	b2bc      	uxth	r4, r7
 8000450:	fb0e 3318 	mls	r3, lr, r8, r3
 8000454:	0c11      	lsrs	r1, r2, #16
 8000456:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 800045a:	fb08 f904 	mul.w	r9, r8, r4
 800045e:	40b0      	lsls	r0, r6
 8000460:	4589      	cmp	r9, r1
 8000462:	ea4f 4310 	mov.w	r3, r0, lsr #16
 8000466:	b280      	uxth	r0, r0
 8000468:	d93e      	bls.n	80004e8 <__udivmoddi4+0x2e8>
 800046a:	1879      	adds	r1, r7, r1
 800046c:	f108 3cff 	add.w	ip, r8, #4294967295	@ 0xffffffff
 8000470:	d201      	bcs.n	8000476 <__udivmoddi4+0x276>
 8000472:	4589      	cmp	r9, r1
 8000474:	d81f      	bhi.n	80004b6 <__udivmoddi4+0x2b6>
 8000476:	eba1 0109 	sub.w	r1, r1, r9
 800047a:	fbb1 f9fe 	udiv	r9, r1, lr
 800047e:	fb09 f804 	mul.w	r8, r9, r4
 8000482:	fb0e 1119 	mls	r1, lr, r9, r1
 8000486:	b292      	uxth	r2, r2
 8000488:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
 800048c:	4542      	cmp	r2, r8
 800048e:	d229      	bcs.n	80004e4 <__udivmoddi4+0x2e4>
 8000490:	18ba      	adds	r2, r7, r2
 8000492:	f109 31ff 	add.w	r1, r9, #4294967295	@ 0xffffffff
 8000496:	d2c4      	bcs.n	8000422 <__udivmoddi4+0x222>
 8000498:	4542      	cmp	r2, r8
 800049a:	d2c2      	bcs.n	8000422 <__udivmoddi4+0x222>
 800049c:	f1a9 0102 	sub.w	r1, r9, #2
 80004a0:	443a      	add	r2, r7
 80004a2:	e7be      	b.n	8000422 <__udivmoddi4+0x222>
 80004a4:	45f0      	cmp	r8, lr
 80004a6:	d29d      	bcs.n	80003e4 <__udivmoddi4+0x1e4>
 80004a8:	ebbe 0302 	subs.w	r3, lr, r2
 80004ac:	eb6c 0c07 	sbc.w	ip, ip, r7
 80004b0:	3801      	subs	r0, #1
 80004b2:	46e1      	mov	r9, ip
 80004b4:	e796      	b.n	80003e4 <__udivmoddi4+0x1e4>
 80004b6:	eba7 0909 	sub.w	r9, r7, r9
 80004ba:	4449      	add	r1, r9
 80004bc:	f1a8 0c02 	sub.w	ip, r8, #2
 80004c0:	fbb1 f9fe 	udiv	r9, r1, lr
 80004c4:	fb09 f804 	mul.w	r8, r9, r4
 80004c8:	e7db      	b.n	8000482 <__udivmoddi4+0x282>
 80004ca:	4673      	mov	r3, lr
 80004cc:	e77f      	b.n	80003ce <__udivmoddi4+0x1ce>
 80004ce:	4650      	mov	r0, sl
 80004d0:	e766      	b.n	80003a0 <__udivmoddi4+0x1a0>
 80004d2:	4608      	mov	r0, r1
 80004d4:	e6fd      	b.n	80002d2 <__udivmoddi4+0xd2>
 80004d6:	443b      	add	r3, r7
 80004d8:	3a02      	subs	r2, #2
 80004da:	e733      	b.n	8000344 <__udivmoddi4+0x144>
 80004dc:	f1ac 0c02 	sub.w	ip, ip, #2
 80004e0:	443b      	add	r3, r7
 80004e2:	e71c      	b.n	800031e <__udivmoddi4+0x11e>
 80004e4:	4649      	mov	r1, r9
 80004e6:	e79c      	b.n	8000422 <__udivmoddi4+0x222>
 80004e8:	eba1 0109 	sub.w	r1, r1, r9
 80004ec:	46c4      	mov	ip, r8
 80004ee:	fbb1 f9fe 	udiv	r9, r1, lr
 80004f2:	fb09 f804 	mul.w	r8, r9, r4
 80004f6:	e7c4      	b.n	8000482 <__udivmoddi4+0x282>

080004f8 <__aeabi_idiv0>:
 80004f8:	4770      	bx	lr
 80004fa:	bf00      	nop

080004fc <ReadJoy>:

static uint8_t previous_state = GPIO_PIN_SET;
static uint8_t virtual_button = 0;

uint8_t ReadJoy(void)
{
 80004fc:	b580      	push	{r7, lr}
 80004fe:	b082      	sub	sp, #8
 8000500:	af00      	add	r7, sp, #0
	GPIO_PinState current_state = HAL_GPIO_ReadPin(GPIOC, GPIO_PIN_13);
 8000502:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 8000506:	4813      	ldr	r0, [pc, #76]	@ (8000554 <ReadJoy+0x58>)
 8000508:	f001 fccc 	bl	8001ea4 <HAL_GPIO_ReadPin>
 800050c:	4603      	mov	r3, r0
 800050e:	71fb      	strb	r3, [r7, #7]

	if (previous_state == GPIO_PIN_SET && current_state == GPIO_PIN_RESET)
 8000510:	4b11      	ldr	r3, [pc, #68]	@ (8000558 <ReadJoy+0x5c>)
 8000512:	781b      	ldrb	r3, [r3, #0]
 8000514:	2b01      	cmp	r3, #1
 8000516:	d10f      	bne.n	8000538 <ReadJoy+0x3c>
 8000518:	79fb      	ldrb	r3, [r7, #7]
 800051a:	2b00      	cmp	r3, #0
 800051c:	d10c      	bne.n	8000538 <ReadJoy+0x3c>
	{
		virtual_button++;
 800051e:	4b0f      	ldr	r3, [pc, #60]	@ (800055c <ReadJoy+0x60>)
 8000520:	781b      	ldrb	r3, [r3, #0]
 8000522:	3301      	adds	r3, #1
 8000524:	b2da      	uxtb	r2, r3
 8000526:	4b0d      	ldr	r3, [pc, #52]	@ (800055c <ReadJoy+0x60>)
 8000528:	701a      	strb	r2, [r3, #0]
		if (virtual_button > 4)	virtual_button = 1;
 800052a:	4b0c      	ldr	r3, [pc, #48]	@ (800055c <ReadJoy+0x60>)
 800052c:	781b      	ldrb	r3, [r3, #0]
 800052e:	2b04      	cmp	r3, #4
 8000530:	d902      	bls.n	8000538 <ReadJoy+0x3c>
 8000532:	4b0a      	ldr	r3, [pc, #40]	@ (800055c <ReadJoy+0x60>)
 8000534:	2201      	movs	r2, #1
 8000536:	701a      	strb	r2, [r3, #0]
	}

	previous_state = current_state;
 8000538:	4a07      	ldr	r2, [pc, #28]	@ (8000558 <ReadJoy+0x5c>)
 800053a:	79fb      	ldrb	r3, [r7, #7]
 800053c:	7013      	strb	r3, [r2, #0]

	if (current_state == GPIO_PIN_RESET) return virtual_button;
 800053e:	79fb      	ldrb	r3, [r7, #7]
 8000540:	2b00      	cmp	r3, #0
 8000542:	d102      	bne.n	800054a <ReadJoy+0x4e>
 8000544:	4b05      	ldr	r3, [pc, #20]	@ (800055c <ReadJoy+0x60>)
 8000546:	781b      	ldrb	r3, [r3, #0]
 8000548:	e000      	b.n	800054c <ReadJoy+0x50>
	else return 0;
 800054a:	2300      	movs	r3, #0
}
 800054c:	4618      	mov	r0, r3
 800054e:	3708      	adds	r7, #8
 8000550:	46bd      	mov	sp, r7
 8000552:	bd80      	pop	{r7, pc}
 8000554:	48000800 	.word	0x48000800
 8000558:	20000000 	.word	0x20000000
 800055c:	20000080 	.word	0x20000080

08000560 <LED_On>:
 */

#include "led_driver.h"

void LED_On(uint8_t led)
{
 8000560:	b580      	push	{r7, lr}
 8000562:	b082      	sub	sp, #8
 8000564:	af00      	add	r7, sp, #0
 8000566:	4603      	mov	r3, r0
 8000568:	71fb      	strb	r3, [r7, #7]
	switch(led)
 800056a:	79fb      	ldrb	r3, [r7, #7]
 800056c:	2b02      	cmp	r3, #2
 800056e:	d014      	beq.n	800059a <LED_On+0x3a>
 8000570:	2b02      	cmp	r3, #2
 8000572:	dc19      	bgt.n	80005a8 <LED_On+0x48>
 8000574:	2b00      	cmp	r3, #0
 8000576:	d002      	beq.n	800057e <LED_On+0x1e>
 8000578:	2b01      	cmp	r3, #1
 800057a:	d007      	beq.n	800058c <LED_On+0x2c>
		break;
	case 2:
		HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET);
		break;
	}
}
 800057c:	e014      	b.n	80005a8 <LED_On+0x48>
		HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
 800057e:	2201      	movs	r2, #1
 8000580:	2120      	movs	r1, #32
 8000582:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000586:	f001 fca5 	bl	8001ed4 <HAL_GPIO_WritePin>
		break;
 800058a:	e00d      	b.n	80005a8 <LED_On+0x48>
		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET);
 800058c:	2201      	movs	r2, #1
 800058e:	f44f 4180 	mov.w	r1, #16384	@ 0x4000
 8000592:	4807      	ldr	r0, [pc, #28]	@ (80005b0 <LED_On+0x50>)
 8000594:	f001 fc9e 	bl	8001ed4 <HAL_GPIO_WritePin>
		break;
 8000598:	e006      	b.n	80005a8 <LED_On+0x48>
		HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET);
 800059a:	2201      	movs	r2, #1
 800059c:	f44f 7100 	mov.w	r1, #512	@ 0x200
 80005a0:	4804      	ldr	r0, [pc, #16]	@ (80005b4 <LED_On+0x54>)
 80005a2:	f001 fc97 	bl	8001ed4 <HAL_GPIO_WritePin>
		break;
 80005a6:	bf00      	nop
}
 80005a8:	bf00      	nop
 80005aa:	3708      	adds	r7, #8
 80005ac:	46bd      	mov	sp, r7
 80005ae:	bd80      	pop	{r7, pc}
 80005b0:	48000400 	.word	0x48000400
 80005b4:	48000800 	.word	0x48000800

080005b8 <LED_Off>:

void LED_Off(uint8_t led)
{
 80005b8:	b580      	push	{r7, lr}
 80005ba:	b082      	sub	sp, #8
 80005bc:	af00      	add	r7, sp, #0
 80005be:	4603      	mov	r3, r0
 80005c0:	71fb      	strb	r3, [r7, #7]
	switch(led)
 80005c2:	79fb      	ldrb	r3, [r7, #7]
 80005c4:	2b02      	cmp	r3, #2
 80005c6:	d014      	beq.n	80005f2 <LED_Off+0x3a>
 80005c8:	2b02      	cmp	r3, #2
 80005ca:	dc19      	bgt.n	8000600 <LED_Off+0x48>
 80005cc:	2b00      	cmp	r3, #0
 80005ce:	d002      	beq.n	80005d6 <LED_Off+0x1e>
 80005d0:	2b01      	cmp	r3, #1
 80005d2:	d007      	beq.n	80005e4 <LED_Off+0x2c>
		break;
	case 2:
		HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_RESET);
		break;
	}
}
 80005d4:	e014      	b.n	8000600 <LED_Off+0x48>
		HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
 80005d6:	2200      	movs	r2, #0
 80005d8:	2120      	movs	r1, #32
 80005da:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 80005de:	f001 fc79 	bl	8001ed4 <HAL_GPIO_WritePin>
		break;
 80005e2:	e00d      	b.n	8000600 <LED_Off+0x48>
		HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET);
 80005e4:	2200      	movs	r2, #0
 80005e6:	f44f 4180 	mov.w	r1, #16384	@ 0x4000
 80005ea:	4807      	ldr	r0, [pc, #28]	@ (8000608 <LED_Off+0x50>)
 80005ec:	f001 fc72 	bl	8001ed4 <HAL_GPIO_WritePin>
		break;
 80005f0:	e006      	b.n	8000600 <LED_Off+0x48>
		HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_RESET);
 80005f2:	2200      	movs	r2, #0
 80005f4:	f44f 7100 	mov.w	r1, #512	@ 0x200
 80005f8:	4804      	ldr	r0, [pc, #16]	@ (800060c <LED_Off+0x54>)
 80005fa:	f001 fc6b 	bl	8001ed4 <HAL_GPIO_WritePin>
		break;
 80005fe:	bf00      	nop
}
 8000600:	bf00      	nop
 8000602:	3708      	adds	r7, #8
 8000604:	46bd      	mov	sp, r7
 8000606:	bd80      	pop	{r7, pc}
 8000608:	48000400 	.word	0x48000400
 800060c:	48000800 	.word	0x48000800

08000610 <CreateLedTask>:

TaskHandle_t hButtonTask;
TaskHandle_t tH[3];

void CreateLedTask()
{
 8000610:	b580      	push	{r7, lr}
 8000612:	b082      	sub	sp, #8
 8000614:	af02      	add	r7, sp, #8
	xTaskCreate(
 8000616:	4b15      	ldr	r3, [pc, #84]	@ (800066c <CreateLedTask+0x5c>)
 8000618:	9301      	str	r3, [sp, #4]
 800061a:	2301      	movs	r3, #1
 800061c:	9300      	str	r3, [sp, #0]
 800061e:	2300      	movs	r3, #0
 8000620:	2280      	movs	r2, #128	@ 0x80
 8000622:	4913      	ldr	r1, [pc, #76]	@ (8000670 <CreateLedTask+0x60>)
 8000624:	4813      	ldr	r0, [pc, #76]	@ (8000674 <CreateLedTask+0x64>)
 8000626:	f005 fd39 	bl	800609c <xTaskCreate>
		NULL,
		1,
		&hButtonTask
	);

	xTaskCreate(
 800062a:	4b13      	ldr	r3, [pc, #76]	@ (8000678 <CreateLedTask+0x68>)
 800062c:	9301      	str	r3, [sp, #4]
 800062e:	2301      	movs	r3, #1
 8000630:	9300      	str	r3, [sp, #0]
 8000632:	2300      	movs	r3, #0
 8000634:	2280      	movs	r2, #128	@ 0x80
 8000636:	4911      	ldr	r1, [pc, #68]	@ (800067c <CreateLedTask+0x6c>)
 8000638:	4811      	ldr	r0, [pc, #68]	@ (8000680 <CreateLedTask+0x70>)
 800063a:	f005 fd2f 	bl	800609c <xTaskCreate>
		NULL,
		1,
		&tH[0]
	);

	xTaskCreate(
 800063e:	4b11      	ldr	r3, [pc, #68]	@ (8000684 <CreateLedTask+0x74>)
 8000640:	9301      	str	r3, [sp, #4]
 8000642:	2301      	movs	r3, #1
 8000644:	9300      	str	r3, [sp, #0]
 8000646:	2300      	movs	r3, #0
 8000648:	2280      	movs	r2, #128	@ 0x80
 800064a:	490f      	ldr	r1, [pc, #60]	@ (8000688 <CreateLedTask+0x78>)
 800064c:	480f      	ldr	r0, [pc, #60]	@ (800068c <CreateLedTask+0x7c>)
 800064e:	f005 fd25 	bl	800609c <xTaskCreate>
		NULL,
		1,
		&tH[1]
	);

	xTaskCreate(
 8000652:	4b0f      	ldr	r3, [pc, #60]	@ (8000690 <CreateLedTask+0x80>)
 8000654:	9301      	str	r3, [sp, #4]
 8000656:	2301      	movs	r3, #1
 8000658:	9300      	str	r3, [sp, #0]
 800065a:	2300      	movs	r3, #0
 800065c:	2280      	movs	r2, #128	@ 0x80
 800065e:	490d      	ldr	r1, [pc, #52]	@ (8000694 <CreateLedTask+0x84>)
 8000660:	480d      	ldr	r0, [pc, #52]	@ (8000698 <CreateLedTask+0x88>)
 8000662:	f005 fd1b 	bl	800609c <xTaskCreate>
		128,
		NULL,
		1,
		&tH[2]
	);
}
 8000666:	bf00      	nop
 8000668:	46bd      	mov	sp, r7
 800066a:	bd80      	pop	{r7, pc}
 800066c:	20000084 	.word	0x20000084
 8000670:	080081a0 	.word	0x080081a0
 8000674:	0800069d 	.word	0x0800069d
 8000678:	20000088 	.word	0x20000088
 800067c:	080081ac 	.word	0x080081ac
 8000680:	080006d5 	.word	0x080006d5
 8000684:	2000008c 	.word	0x2000008c
 8000688:	080081c0 	.word	0x080081c0
 800068c:	08000741 	.word	0x08000741
 8000690:	20000090 	.word	0x20000090
 8000694:	080081d4 	.word	0x080081d4
 8000698:	080007ab 	.word	0x080007ab

0800069c <ButtonTask>:

void ButtonTask(void* pArgs)
{
 800069c:	b580      	push	{r7, lr}
 800069e:	b084      	sub	sp, #16
 80006a0:	af00      	add	r7, sp, #0
 80006a2:	6078      	str	r0, [r7, #4]
	for(;;)
	{
		uint8_t key = ReadJoy();
 80006a4:	f7ff ff2a 	bl	80004fc <ReadJoy>
 80006a8:	4603      	mov	r3, r0
 80006aa:	73fb      	strb	r3, [r7, #15]
		if(key)
 80006ac:	7bfb      	ldrb	r3, [r7, #15]
 80006ae:	2b00      	cmp	r3, #0
 80006b0:	d009      	beq.n	80006c6 <ButtonTask+0x2a>
			xTaskNotifyGive(tH[key - 1]);
 80006b2:	7bfb      	ldrb	r3, [r7, #15]
 80006b4:	3b01      	subs	r3, #1
 80006b6:	4a06      	ldr	r2, [pc, #24]	@ (80006d0 <ButtonTask+0x34>)
 80006b8:	f852 0023 	ldr.w	r0, [r2, r3, lsl #2]
 80006bc:	2300      	movs	r3, #0
 80006be:	2202      	movs	r2, #2
 80006c0:	2100      	movs	r1, #0
 80006c2:	f006 fbbd 	bl	8006e40 <xTaskGenericNotify>
		vTaskDelay(100);
 80006c6:	2064      	movs	r0, #100	@ 0x64
 80006c8:	f005 fe46 	bl	8006358 <vTaskDelay>
	{
 80006cc:	e7ea      	b.n	80006a4 <ButtonTask+0x8>
 80006ce:	bf00      	nop
 80006d0:	20000088 	.word	0x20000088

080006d4 <LedAnimationTask1>:
	}
}

void LedAnimationTask1(void* pArgs)
{
 80006d4:	b580      	push	{r7, lr}
 80006d6:	b084      	sub	sp, #16
 80006d8:	af00      	add	r7, sp, #0
 80006da:	6078      	str	r0, [r7, #4]
	for(;;)
	{
		ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
 80006dc:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80006e0:	2001      	movs	r0, #1
 80006e2:	f006 fb61 	bl	8006da8 <ulTaskNotifyTake>
		int i;
		for(i = 0; i < 3; i++)
 80006e6:	2300      	movs	r3, #0
 80006e8:	60fb      	str	r3, [r7, #12]
 80006ea:	e00f      	b.n	800070c <LedAnimationTask1+0x38>
		{
			LED_On(i);
 80006ec:	68fb      	ldr	r3, [r7, #12]
 80006ee:	b2db      	uxtb	r3, r3
 80006f0:	4618      	mov	r0, r3
 80006f2:	f7ff ff35 	bl	8000560 <LED_On>
			vTaskDelay(150);
 80006f6:	2096      	movs	r0, #150	@ 0x96
 80006f8:	f005 fe2e 	bl	8006358 <vTaskDelay>
			LED_Off(i);
 80006fc:	68fb      	ldr	r3, [r7, #12]
 80006fe:	b2db      	uxtb	r3, r3
 8000700:	4618      	mov	r0, r3
 8000702:	f7ff ff59 	bl	80005b8 <LED_Off>
		for(i = 0; i < 3; i++)
 8000706:	68fb      	ldr	r3, [r7, #12]
 8000708:	3301      	adds	r3, #1
 800070a:	60fb      	str	r3, [r7, #12]
 800070c:	68fb      	ldr	r3, [r7, #12]
 800070e:	2b02      	cmp	r3, #2
 8000710:	ddec      	ble.n	80006ec <LedAnimationTask1+0x18>
		}
		for(i = 1; i > 0; i--)
 8000712:	2301      	movs	r3, #1
 8000714:	60fb      	str	r3, [r7, #12]
 8000716:	e00f      	b.n	8000738 <LedAnimationTask1+0x64>
		{
			LED_On(i);
 8000718:	68fb      	ldr	r3, [r7, #12]
 800071a:	b2db      	uxtb	r3, r3
 800071c:	4618      	mov	r0, r3
 800071e:	f7ff ff1f 	bl	8000560 <LED_On>
			vTaskDelay(150);
 8000722:	2096      	movs	r0, #150	@ 0x96
 8000724:	f005 fe18 	bl	8006358 <vTaskDelay>
			LED_Off(i);
 8000728:	68fb      	ldr	r3, [r7, #12]
 800072a:	b2db      	uxtb	r3, r3
 800072c:	4618      	mov	r0, r3
 800072e:	f7ff ff43 	bl	80005b8 <LED_Off>
		for(i = 1; i > 0; i--)
 8000732:	68fb      	ldr	r3, [r7, #12]
 8000734:	3b01      	subs	r3, #1
 8000736:	60fb      	str	r3, [r7, #12]
 8000738:	68fb      	ldr	r3, [r7, #12]
 800073a:	2b00      	cmp	r3, #0
 800073c:	dcec      	bgt.n	8000718 <LedAnimationTask1+0x44>
	{
 800073e:	e7cd      	b.n	80006dc <LedAnimationTask1+0x8>

08000740 <LedAnimationTask2>:
		}
	}
}

void LedAnimationTask2(void* pArgs)
{
 8000740:	b580      	push	{r7, lr}
 8000742:	b084      	sub	sp, #16
 8000744:	af00      	add	r7, sp, #0
 8000746:	6078      	str	r0, [r7, #4]
	for(;;)
	{
		ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
 8000748:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 800074c:	2001      	movs	r0, #1
 800074e:	f006 fb2b 	bl	8006da8 <ulTaskNotifyTake>
		int i, j;
		for(j = 0; j < 5; j++)
 8000752:	2300      	movs	r3, #0
 8000754:	60bb      	str	r3, [r7, #8]
 8000756:	e024      	b.n	80007a2 <LedAnimationTask2+0x62>
		{
			for(i = 0; i < 3; i++)
 8000758:	2300      	movs	r3, #0
 800075a:	60fb      	str	r3, [r7, #12]
 800075c:	e007      	b.n	800076e <LedAnimationTask2+0x2e>
				LED_On(i);
 800075e:	68fb      	ldr	r3, [r7, #12]
 8000760:	b2db      	uxtb	r3, r3
 8000762:	4618      	mov	r0, r3
 8000764:	f7ff fefc 	bl	8000560 <LED_On>
			for(i = 0; i < 3; i++)
 8000768:	68fb      	ldr	r3, [r7, #12]
 800076a:	3301      	adds	r3, #1
 800076c:	60fb      	str	r3, [r7, #12]
 800076e:	68fb      	ldr	r3, [r7, #12]
 8000770:	2b02      	cmp	r3, #2
 8000772:	ddf4      	ble.n	800075e <LedAnimationTask2+0x1e>

			vTaskDelay(100);
 8000774:	2064      	movs	r0, #100	@ 0x64
 8000776:	f005 fdef 	bl	8006358 <vTaskDelay>

			for(i = 0; i < 3; i++)
 800077a:	2300      	movs	r3, #0
 800077c:	60fb      	str	r3, [r7, #12]
 800077e:	e007      	b.n	8000790 <LedAnimationTask2+0x50>
				LED_Off(i);
 8000780:	68fb      	ldr	r3, [r7, #12]
 8000782:	b2db      	uxtb	r3, r3
 8000784:	4618      	mov	r0, r3
 8000786:	f7ff ff17 	bl	80005b8 <LED_Off>
			for(i = 0; i < 3; i++)
 800078a:	68fb      	ldr	r3, [r7, #12]
 800078c:	3301      	adds	r3, #1
 800078e:	60fb      	str	r3, [r7, #12]
 8000790:	68fb      	ldr	r3, [r7, #12]
 8000792:	2b02      	cmp	r3, #2
 8000794:	ddf4      	ble.n	8000780 <LedAnimationTask2+0x40>

			vTaskDelay(100);
 8000796:	2064      	movs	r0, #100	@ 0x64
 8000798:	f005 fdde 	bl	8006358 <vTaskDelay>
		for(j = 0; j < 5; j++)
 800079c:	68bb      	ldr	r3, [r7, #8]
 800079e:	3301      	adds	r3, #1
 80007a0:	60bb      	str	r3, [r7, #8]
 80007a2:	68bb      	ldr	r3, [r7, #8]
 80007a4:	2b04      	cmp	r3, #4
 80007a6:	ddd7      	ble.n	8000758 <LedAnimationTask2+0x18>
	{
 80007a8:	e7ce      	b.n	8000748 <LedAnimationTask2+0x8>

080007aa <LedAnimationTask3>:
		}
	}
}

void LedAnimationTask3(void* pArgs)
{
 80007aa:	b580      	push	{r7, lr}
 80007ac:	b084      	sub	sp, #16
 80007ae:	af00      	add	r7, sp, #0
 80007b0:	6078      	str	r0, [r7, #4]
	for(;;)
	{
		ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
 80007b2:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80007b6:	2001      	movs	r0, #1
 80007b8:	f006 faf6 	bl	8006da8 <ulTaskNotifyTake>
		int i;
		for(i = 0; i < 3; i++)
 80007bc:	2300      	movs	r3, #0
 80007be:	60fb      	str	r3, [r7, #12]
 80007c0:	e00a      	b.n	80007d8 <LedAnimationTask3+0x2e>
		{
			LED_On(i);
 80007c2:	68fb      	ldr	r3, [r7, #12]
 80007c4:	b2db      	uxtb	r3, r3
 80007c6:	4618      	mov	r0, r3
 80007c8:	f7ff feca 	bl	8000560 <LED_On>
			vTaskDelay(150);
 80007cc:	2096      	movs	r0, #150	@ 0x96
 80007ce:	f005 fdc3 	bl	8006358 <vTaskDelay>
		for(i = 0; i < 3; i++)
 80007d2:	68fb      	ldr	r3, [r7, #12]
 80007d4:	3301      	adds	r3, #1
 80007d6:	60fb      	str	r3, [r7, #12]
 80007d8:	68fb      	ldr	r3, [r7, #12]
 80007da:	2b02      	cmp	r3, #2
 80007dc:	ddf1      	ble.n	80007c2 <LedAnimationTask3+0x18>
		}
		for(i = 2; i >= 0; i--)
 80007de:	2302      	movs	r3, #2
 80007e0:	60fb      	str	r3, [r7, #12]
 80007e2:	e00a      	b.n	80007fa <LedAnimationTask3+0x50>
		{
			LED_Off(i);
 80007e4:	68fb      	ldr	r3, [r7, #12]
 80007e6:	b2db      	uxtb	r3, r3
 80007e8:	4618      	mov	r0, r3
 80007ea:	f7ff fee5 	bl	80005b8 <LED_Off>
			vTaskDelay(150);
 80007ee:	2096      	movs	r0, #150	@ 0x96
 80007f0:	f005 fdb2 	bl	8006358 <vTaskDelay>
		for(i = 2; i >= 0; i--)
 80007f4:	68fb      	ldr	r3, [r7, #12]
 80007f6:	3b01      	subs	r3, #1
 80007f8:	60fb      	str	r3, [r7, #12]
 80007fa:	68fb      	ldr	r3, [r7, #12]
 80007fc:	2b00      	cmp	r3, #0
 80007fe:	daf1      	bge.n	80007e4 <LedAnimationTask3+0x3a>
	{
 8000800:	e7d7      	b.n	80007b2 <LedAnimationTask3+0x8>

08000802 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8000802:	b580      	push	{r7, lr}
 8000804:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000806:	f000 ff58 	bl	80016ba <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 800080a:	f000 f819 	bl	8000840 <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 800080e:	f000 f9e1 	bl	8000bd4 <MX_GPIO_Init>
  MX_DFSDM1_Init();
 8000812:	f000 f877 	bl	8000904 <MX_DFSDM1_Init>
  MX_I2C2_Init();
 8000816:	f000 f8ad 	bl	8000974 <MX_I2C2_Init>
  MX_QUADSPI_Init();
 800081a:	f000 f8e9 	bl	80009f0 <MX_QUADSPI_Init>
  MX_SPI3_Init();
 800081e:	f000 f90d 	bl	8000a3c <MX_SPI3_Init>
  MX_USART1_UART_Init();
 8000822:	f000 f949 	bl	8000ab8 <MX_USART1_UART_Init>
  MX_USART3_UART_Init();
 8000826:	f000 f977 	bl	8000b18 <MX_USART3_UART_Init>
  MX_USB_OTG_FS_PCD_Init();
 800082a:	f000 f9a5 	bl	8000b78 <MX_USB_OTG_FS_PCD_Init>
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */

  /* Init scheduler */
  osKernelInitialize();
 800082e:	f004 fda9 	bl	8005384 <osKernelInitialize>
  /* Create the thread(s) */
  /* creation of defaultTask */
  //defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);

  /* USER CODE BEGIN RTOS_THREADS */
  CreateLedTask();
 8000832:	f7ff feed 	bl	8000610 <CreateLedTask>
  /* USER CODE BEGIN RTOS_EVENTS */
  /* add events, ... */
  /* USER CODE END RTOS_EVENTS */

  /* Start scheduler */
  osKernelStart();
 8000836:	f004 fdc9 	bl	80053cc <osKernelStart>

  /* We should never get here as control is now taken by the scheduler */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
 800083a:	bf00      	nop
 800083c:	e7fd      	b.n	800083a <main+0x38>
	...

08000840 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8000840:	b580      	push	{r7, lr}
 8000842:	b096      	sub	sp, #88	@ 0x58
 8000844:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8000846:	f107 0314 	add.w	r3, r7, #20
 800084a:	2244      	movs	r2, #68	@ 0x44
 800084c:	2100      	movs	r1, #0
 800084e:	4618      	mov	r0, r3
 8000850:	f007 fbaa 	bl	8007fa8 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8000854:	463b      	mov	r3, r7
 8000856:	2200      	movs	r2, #0
 8000858:	601a      	str	r2, [r3, #0]
 800085a:	605a      	str	r2, [r3, #4]
 800085c:	609a      	str	r2, [r3, #8]
 800085e:	60da      	str	r2, [r3, #12]
 8000860:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
 8000862:	f44f 7000 	mov.w	r0, #512	@ 0x200
 8000866:	f001 fdf3 	bl	8002450 <HAL_PWREx_ControlVoltageScaling>
 800086a:	4603      	mov	r3, r0
 800086c:	2b00      	cmp	r3, #0
 800086e:	d001      	beq.n	8000874 <SystemClock_Config+0x34>
  {
    Error_Handler();
 8000870:	f000 fb74 	bl	8000f5c <Error_Handler>
  }

  /** Configure LSE Drive Capability
  */
  HAL_PWR_EnableBkUpAccess();
 8000874:	f001 fdce 	bl	8002414 <HAL_PWR_EnableBkUpAccess>
  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 8000878:	4b21      	ldr	r3, [pc, #132]	@ (8000900 <SystemClock_Config+0xc0>)
 800087a:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800087e:	4a20      	ldr	r2, [pc, #128]	@ (8000900 <SystemClock_Config+0xc0>)
 8000880:	f023 0318 	bic.w	r3, r3, #24
 8000884:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
 8000888:	2314      	movs	r3, #20
 800088a:	617b      	str	r3, [r7, #20]
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
 800088c:	2301      	movs	r3, #1
 800088e:	61fb      	str	r3, [r7, #28]
  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
 8000890:	2301      	movs	r3, #1
 8000892:	62fb      	str	r3, [r7, #44]	@ 0x2c
  RCC_OscInitStruct.MSICalibrationValue = 0;
 8000894:	2300      	movs	r3, #0
 8000896:	633b      	str	r3, [r7, #48]	@ 0x30
  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
 8000898:	2360      	movs	r3, #96	@ 0x60
 800089a:	637b      	str	r3, [r7, #52]	@ 0x34
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 800089c:	2302      	movs	r3, #2
 800089e:	63fb      	str	r3, [r7, #60]	@ 0x3c
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
 80008a0:	2301      	movs	r3, #1
 80008a2:	643b      	str	r3, [r7, #64]	@ 0x40
  RCC_OscInitStruct.PLL.PLLM = 1;
 80008a4:	2301      	movs	r3, #1
 80008a6:	647b      	str	r3, [r7, #68]	@ 0x44
  RCC_OscInitStruct.PLL.PLLN = 40;
 80008a8:	2328      	movs	r3, #40	@ 0x28
 80008aa:	64bb      	str	r3, [r7, #72]	@ 0x48
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
 80008ac:	2307      	movs	r3, #7
 80008ae:	64fb      	str	r3, [r7, #76]	@ 0x4c
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
 80008b0:	2302      	movs	r3, #2
 80008b2:	653b      	str	r3, [r7, #80]	@ 0x50
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 80008b4:	2302      	movs	r3, #2
 80008b6:	657b      	str	r3, [r7, #84]	@ 0x54
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 80008b8:	f107 0314 	add.w	r3, r7, #20
 80008bc:	4618      	mov	r0, r3
 80008be:	f001 fee9 	bl	8002694 <HAL_RCC_OscConfig>
 80008c2:	4603      	mov	r3, r0
 80008c4:	2b00      	cmp	r3, #0
 80008c6:	d001      	beq.n	80008cc <SystemClock_Config+0x8c>
  {
    Error_Handler();
 80008c8:	f000 fb48 	bl	8000f5c <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 80008cc:	230f      	movs	r3, #15
 80008ce:	603b      	str	r3, [r7, #0]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 80008d0:	2303      	movs	r3, #3
 80008d2:	607b      	str	r3, [r7, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 80008d4:	2300      	movs	r3, #0
 80008d6:	60bb      	str	r3, [r7, #8]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 80008d8:	2300      	movs	r3, #0
 80008da:	60fb      	str	r3, [r7, #12]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 80008dc:	2300      	movs	r3, #0
 80008de:	613b      	str	r3, [r7, #16]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 80008e0:	463b      	mov	r3, r7
 80008e2:	2104      	movs	r1, #4
 80008e4:	4618      	mov	r0, r3
 80008e6:	f002 fab1 	bl	8002e4c <HAL_RCC_ClockConfig>
 80008ea:	4603      	mov	r3, r0
 80008ec:	2b00      	cmp	r3, #0
 80008ee:	d001      	beq.n	80008f4 <SystemClock_Config+0xb4>
  {
    Error_Handler();
 80008f0:	f000 fb34 	bl	8000f5c <Error_Handler>
  }

  /** Enable MSI Auto calibration
  */
  HAL_RCCEx_EnableMSIPLLMode();
 80008f4:	f002 ffea 	bl	80038cc <HAL_RCCEx_EnableMSIPLLMode>
}
 80008f8:	bf00      	nop
 80008fa:	3758      	adds	r7, #88	@ 0x58
 80008fc:	46bd      	mov	sp, r7
 80008fe:	bd80      	pop	{r7, pc}
 8000900:	40021000 	.word	0x40021000

08000904 <MX_DFSDM1_Init>:
  * @brief DFSDM1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_DFSDM1_Init(void)
{
 8000904:	b580      	push	{r7, lr}
 8000906:	af00      	add	r7, sp, #0
  /* USER CODE END DFSDM1_Init 0 */

  /* USER CODE BEGIN DFSDM1_Init 1 */

  /* USER CODE END DFSDM1_Init 1 */
  hdfsdm1_channel1.Instance = DFSDM1_Channel1;
 8000908:	4b18      	ldr	r3, [pc, #96]	@ (800096c <MX_DFSDM1_Init+0x68>)
 800090a:	4a19      	ldr	r2, [pc, #100]	@ (8000970 <MX_DFSDM1_Init+0x6c>)
 800090c:	601a      	str	r2, [r3, #0]
  hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;
 800090e:	4b17      	ldr	r3, [pc, #92]	@ (800096c <MX_DFSDM1_Init+0x68>)
 8000910:	2201      	movs	r2, #1
 8000912:	711a      	strb	r2, [r3, #4]
  hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;
 8000914:	4b15      	ldr	r3, [pc, #84]	@ (800096c <MX_DFSDM1_Init+0x68>)
 8000916:	2200      	movs	r2, #0
 8000918:	609a      	str	r2, [r3, #8]
  hdfsdm1_channel1.Init.OutputClock.Divider = 2;
 800091a:	4b14      	ldr	r3, [pc, #80]	@ (800096c <MX_DFSDM1_Init+0x68>)
 800091c:	2202      	movs	r2, #2
 800091e:	60da      	str	r2, [r3, #12]
  hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
 8000920:	4b12      	ldr	r3, [pc, #72]	@ (800096c <MX_DFSDM1_Init+0x68>)
 8000922:	2200      	movs	r2, #0
 8000924:	611a      	str	r2, [r3, #16]
  hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
 8000926:	4b11      	ldr	r3, [pc, #68]	@ (800096c <MX_DFSDM1_Init+0x68>)
 8000928:	2200      	movs	r2, #0
 800092a:	615a      	str	r2, [r3, #20]
  hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;
 800092c:	4b0f      	ldr	r3, [pc, #60]	@ (800096c <MX_DFSDM1_Init+0x68>)
 800092e:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8000932:	619a      	str	r2, [r3, #24]
  hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
 8000934:	4b0d      	ldr	r3, [pc, #52]	@ (800096c <MX_DFSDM1_Init+0x68>)
 8000936:	2200      	movs	r2, #0
 8000938:	61da      	str	r2, [r3, #28]
  hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
 800093a:	4b0c      	ldr	r3, [pc, #48]	@ (800096c <MX_DFSDM1_Init+0x68>)
 800093c:	2204      	movs	r2, #4
 800093e:	621a      	str	r2, [r3, #32]
  hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
 8000940:	4b0a      	ldr	r3, [pc, #40]	@ (800096c <MX_DFSDM1_Init+0x68>)
 8000942:	2200      	movs	r2, #0
 8000944:	625a      	str	r2, [r3, #36]	@ 0x24
  hdfsdm1_channel1.Init.Awd.Oversampling = 1;
 8000946:	4b09      	ldr	r3, [pc, #36]	@ (800096c <MX_DFSDM1_Init+0x68>)
 8000948:	2201      	movs	r2, #1
 800094a:	629a      	str	r2, [r3, #40]	@ 0x28
  hdfsdm1_channel1.Init.Offset = 0;
 800094c:	4b07      	ldr	r3, [pc, #28]	@ (800096c <MX_DFSDM1_Init+0x68>)
 800094e:	2200      	movs	r2, #0
 8000950:	62da      	str	r2, [r3, #44]	@ 0x2c
  hdfsdm1_channel1.Init.RightBitShift = 0x00;
 8000952:	4b06      	ldr	r3, [pc, #24]	@ (800096c <MX_DFSDM1_Init+0x68>)
 8000954:	2200      	movs	r2, #0
 8000956:	631a      	str	r2, [r3, #48]	@ 0x30
  if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)
 8000958:	4804      	ldr	r0, [pc, #16]	@ (800096c <MX_DFSDM1_Init+0x68>)
 800095a:	f000 ffed 	bl	8001938 <HAL_DFSDM_ChannelInit>
 800095e:	4603      	mov	r3, r0
 8000960:	2b00      	cmp	r3, #0
 8000962:	d001      	beq.n	8000968 <MX_DFSDM1_Init+0x64>
  {
    Error_Handler();
 8000964:	f000 fafa 	bl	8000f5c <Error_Handler>
  }
  /* USER CODE BEGIN DFSDM1_Init 2 */

  /* USER CODE END DFSDM1_Init 2 */

}
 8000968:	bf00      	nop
 800096a:	bd80      	pop	{r7, pc}
 800096c:	20000094 	.word	0x20000094
 8000970:	40016020 	.word	0x40016020

08000974 <MX_I2C2_Init>:
  * @brief I2C2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_I2C2_Init(void)
{
 8000974:	b580      	push	{r7, lr}
 8000976:	af00      	add	r7, sp, #0
  /* USER CODE END I2C2_Init 0 */

  /* USER CODE BEGIN I2C2_Init 1 */

  /* USER CODE END I2C2_Init 1 */
  hi2c2.Instance = I2C2;
 8000978:	4b1b      	ldr	r3, [pc, #108]	@ (80009e8 <MX_I2C2_Init+0x74>)
 800097a:	4a1c      	ldr	r2, [pc, #112]	@ (80009ec <MX_I2C2_Init+0x78>)
 800097c:	601a      	str	r2, [r3, #0]
  hi2c2.Init.Timing = 0x00000E14;
 800097e:	4b1a      	ldr	r3, [pc, #104]	@ (80009e8 <MX_I2C2_Init+0x74>)
 8000980:	f640 6214 	movw	r2, #3604	@ 0xe14
 8000984:	605a      	str	r2, [r3, #4]
  hi2c2.Init.OwnAddress1 = 0;
 8000986:	4b18      	ldr	r3, [pc, #96]	@ (80009e8 <MX_I2C2_Init+0x74>)
 8000988:	2200      	movs	r2, #0
 800098a:	609a      	str	r2, [r3, #8]
  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 800098c:	4b16      	ldr	r3, [pc, #88]	@ (80009e8 <MX_I2C2_Init+0x74>)
 800098e:	2201      	movs	r2, #1
 8000990:	60da      	str	r2, [r3, #12]
  hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 8000992:	4b15      	ldr	r3, [pc, #84]	@ (80009e8 <MX_I2C2_Init+0x74>)
 8000994:	2200      	movs	r2, #0
 8000996:	611a      	str	r2, [r3, #16]
  hi2c2.Init.OwnAddress2 = 0;
 8000998:	4b13      	ldr	r3, [pc, #76]	@ (80009e8 <MX_I2C2_Init+0x74>)
 800099a:	2200      	movs	r2, #0
 800099c:	615a      	str	r2, [r3, #20]
  hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
 800099e:	4b12      	ldr	r3, [pc, #72]	@ (80009e8 <MX_I2C2_Init+0x74>)
 80009a0:	2200      	movs	r2, #0
 80009a2:	619a      	str	r2, [r3, #24]
  hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 80009a4:	4b10      	ldr	r3, [pc, #64]	@ (80009e8 <MX_I2C2_Init+0x74>)
 80009a6:	2200      	movs	r2, #0
 80009a8:	61da      	str	r2, [r3, #28]
  hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 80009aa:	4b0f      	ldr	r3, [pc, #60]	@ (80009e8 <MX_I2C2_Init+0x74>)
 80009ac:	2200      	movs	r2, #0
 80009ae:	621a      	str	r2, [r3, #32]
  if (HAL_I2C_Init(&hi2c2) != HAL_OK)
 80009b0:	480d      	ldr	r0, [pc, #52]	@ (80009e8 <MX_I2C2_Init+0x74>)
 80009b2:	f001 faca 	bl	8001f4a <HAL_I2C_Init>
 80009b6:	4603      	mov	r3, r0
 80009b8:	2b00      	cmp	r3, #0
 80009ba:	d001      	beq.n	80009c0 <MX_I2C2_Init+0x4c>
  {
    Error_Handler();
 80009bc:	f000 face 	bl	8000f5c <Error_Handler>
  }

  /** Configure Analogue filter
  */
  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
 80009c0:	2100      	movs	r1, #0
 80009c2:	4809      	ldr	r0, [pc, #36]	@ (80009e8 <MX_I2C2_Init+0x74>)
 80009c4:	f001 fb5c 	bl	8002080 <HAL_I2CEx_ConfigAnalogFilter>
 80009c8:	4603      	mov	r3, r0
 80009ca:	2b00      	cmp	r3, #0
 80009cc:	d001      	beq.n	80009d2 <MX_I2C2_Init+0x5e>
  {
    Error_Handler();
 80009ce:	f000 fac5 	bl	8000f5c <Error_Handler>
  }

  /** Configure Digital filter
  */
  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
 80009d2:	2100      	movs	r1, #0
 80009d4:	4804      	ldr	r0, [pc, #16]	@ (80009e8 <MX_I2C2_Init+0x74>)
 80009d6:	f001 fb9e 	bl	8002116 <HAL_I2CEx_ConfigDigitalFilter>
 80009da:	4603      	mov	r3, r0
 80009dc:	2b00      	cmp	r3, #0
 80009de:	d001      	beq.n	80009e4 <MX_I2C2_Init+0x70>
  {
    Error_Handler();
 80009e0:	f000 fabc 	bl	8000f5c <Error_Handler>
  }
  /* USER CODE BEGIN I2C2_Init 2 */

  /* USER CODE END I2C2_Init 2 */

}
 80009e4:	bf00      	nop
 80009e6:	bd80      	pop	{r7, pc}
 80009e8:	200000cc 	.word	0x200000cc
 80009ec:	40005800 	.word	0x40005800

080009f0 <MX_QUADSPI_Init>:
  * @brief QUADSPI Initialization Function
  * @param None
  * @retval None
  */
static void MX_QUADSPI_Init(void)
{
 80009f0:	b580      	push	{r7, lr}
 80009f2:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN QUADSPI_Init 1 */

  /* USER CODE END QUADSPI_Init 1 */
  /* QUADSPI parameter configuration*/
  hqspi.Instance = QUADSPI;
 80009f4:	4b0f      	ldr	r3, [pc, #60]	@ (8000a34 <MX_QUADSPI_Init+0x44>)
 80009f6:	4a10      	ldr	r2, [pc, #64]	@ (8000a38 <MX_QUADSPI_Init+0x48>)
 80009f8:	601a      	str	r2, [r3, #0]
  hqspi.Init.ClockPrescaler = 2;
 80009fa:	4b0e      	ldr	r3, [pc, #56]	@ (8000a34 <MX_QUADSPI_Init+0x44>)
 80009fc:	2202      	movs	r2, #2
 80009fe:	605a      	str	r2, [r3, #4]
  hqspi.Init.FifoThreshold = 4;
 8000a00:	4b0c      	ldr	r3, [pc, #48]	@ (8000a34 <MX_QUADSPI_Init+0x44>)
 8000a02:	2204      	movs	r2, #4
 8000a04:	609a      	str	r2, [r3, #8]
  hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
 8000a06:	4b0b      	ldr	r3, [pc, #44]	@ (8000a34 <MX_QUADSPI_Init+0x44>)
 8000a08:	2210      	movs	r2, #16
 8000a0a:	60da      	str	r2, [r3, #12]
  hqspi.Init.FlashSize = 23;
 8000a0c:	4b09      	ldr	r3, [pc, #36]	@ (8000a34 <MX_QUADSPI_Init+0x44>)
 8000a0e:	2217      	movs	r2, #23
 8000a10:	611a      	str	r2, [r3, #16]
  hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
 8000a12:	4b08      	ldr	r3, [pc, #32]	@ (8000a34 <MX_QUADSPI_Init+0x44>)
 8000a14:	2200      	movs	r2, #0
 8000a16:	615a      	str	r2, [r3, #20]
  hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
 8000a18:	4b06      	ldr	r3, [pc, #24]	@ (8000a34 <MX_QUADSPI_Init+0x44>)
 8000a1a:	2200      	movs	r2, #0
 8000a1c:	619a      	str	r2, [r3, #24]
  if (HAL_QSPI_Init(&hqspi) != HAL_OK)
 8000a1e:	4805      	ldr	r0, [pc, #20]	@ (8000a34 <MX_QUADSPI_Init+0x44>)
 8000a20:	f001 fd7c 	bl	800251c <HAL_QSPI_Init>
 8000a24:	4603      	mov	r3, r0
 8000a26:	2b00      	cmp	r3, #0
 8000a28:	d001      	beq.n	8000a2e <MX_QUADSPI_Init+0x3e>
  {
    Error_Handler();
 8000a2a:	f000 fa97 	bl	8000f5c <Error_Handler>
  }
  /* USER CODE BEGIN QUADSPI_Init 2 */

  /* USER CODE END QUADSPI_Init 2 */

}
 8000a2e:	bf00      	nop
 8000a30:	bd80      	pop	{r7, pc}
 8000a32:	bf00      	nop
 8000a34:	20000120 	.word	0x20000120
 8000a38:	a0001000 	.word	0xa0001000

08000a3c <MX_SPI3_Init>:
  * @brief SPI3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_SPI3_Init(void)
{
 8000a3c:	b580      	push	{r7, lr}
 8000a3e:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN SPI3_Init 1 */

  /* USER CODE END SPI3_Init 1 */
  /* SPI3 parameter configuration*/
  hspi3.Instance = SPI3;
 8000a40:	4b1b      	ldr	r3, [pc, #108]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a42:	4a1c      	ldr	r2, [pc, #112]	@ (8000ab4 <MX_SPI3_Init+0x78>)
 8000a44:	601a      	str	r2, [r3, #0]
  hspi3.Init.Mode = SPI_MODE_MASTER;
 8000a46:	4b1a      	ldr	r3, [pc, #104]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a48:	f44f 7282 	mov.w	r2, #260	@ 0x104
 8000a4c:	605a      	str	r2, [r3, #4]
  hspi3.Init.Direction = SPI_DIRECTION_2LINES;
 8000a4e:	4b18      	ldr	r3, [pc, #96]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a50:	2200      	movs	r2, #0
 8000a52:	609a      	str	r2, [r3, #8]
  hspi3.Init.DataSize = SPI_DATASIZE_4BIT;
 8000a54:	4b16      	ldr	r3, [pc, #88]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a56:	f44f 7240 	mov.w	r2, #768	@ 0x300
 8000a5a:	60da      	str	r2, [r3, #12]
  hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
 8000a5c:	4b14      	ldr	r3, [pc, #80]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a5e:	2200      	movs	r2, #0
 8000a60:	611a      	str	r2, [r3, #16]
  hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
 8000a62:	4b13      	ldr	r3, [pc, #76]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a64:	2200      	movs	r2, #0
 8000a66:	615a      	str	r2, [r3, #20]
  hspi3.Init.NSS = SPI_NSS_SOFT;
 8000a68:	4b11      	ldr	r3, [pc, #68]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a6a:	f44f 7200 	mov.w	r2, #512	@ 0x200
 8000a6e:	619a      	str	r2, [r3, #24]
  hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
 8000a70:	4b0f      	ldr	r3, [pc, #60]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a72:	2200      	movs	r2, #0
 8000a74:	61da      	str	r2, [r3, #28]
  hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
 8000a76:	4b0e      	ldr	r3, [pc, #56]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a78:	2200      	movs	r2, #0
 8000a7a:	621a      	str	r2, [r3, #32]
  hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
 8000a7c:	4b0c      	ldr	r3, [pc, #48]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a7e:	2200      	movs	r2, #0
 8000a80:	625a      	str	r2, [r3, #36]	@ 0x24
  hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 8000a82:	4b0b      	ldr	r3, [pc, #44]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a84:	2200      	movs	r2, #0
 8000a86:	629a      	str	r2, [r3, #40]	@ 0x28
  hspi3.Init.CRCPolynomial = 7;
 8000a88:	4b09      	ldr	r3, [pc, #36]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a8a:	2207      	movs	r2, #7
 8000a8c:	62da      	str	r2, [r3, #44]	@ 0x2c
  hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
 8000a8e:	4b08      	ldr	r3, [pc, #32]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a90:	2200      	movs	r2, #0
 8000a92:	631a      	str	r2, [r3, #48]	@ 0x30
  hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
 8000a94:	4b06      	ldr	r3, [pc, #24]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a96:	2208      	movs	r2, #8
 8000a98:	635a      	str	r2, [r3, #52]	@ 0x34
  if (HAL_SPI_Init(&hspi3) != HAL_OK)
 8000a9a:	4805      	ldr	r0, [pc, #20]	@ (8000ab0 <MX_SPI3_Init+0x74>)
 8000a9c:	f003 f8f8 	bl	8003c90 <HAL_SPI_Init>
 8000aa0:	4603      	mov	r3, r0
 8000aa2:	2b00      	cmp	r3, #0
 8000aa4:	d001      	beq.n	8000aaa <MX_SPI3_Init+0x6e>
  {
    Error_Handler();
 8000aa6:	f000 fa59 	bl	8000f5c <Error_Handler>
  }
  /* USER CODE BEGIN SPI3_Init 2 */

  /* USER CODE END SPI3_Init 2 */

}
 8000aaa:	bf00      	nop
 8000aac:	bd80      	pop	{r7, pc}
 8000aae:	bf00      	nop
 8000ab0:	20000164 	.word	0x20000164
 8000ab4:	40003c00 	.word	0x40003c00

08000ab8 <MX_USART1_UART_Init>:
  * @brief USART1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART1_UART_Init(void)
{
 8000ab8:	b580      	push	{r7, lr}
 8000aba:	af00      	add	r7, sp, #0
  /* USER CODE END USART1_Init 0 */

  /* USER CODE BEGIN USART1_Init 1 */

  /* USER CODE END USART1_Init 1 */
  huart1.Instance = USART1;
 8000abc:	4b14      	ldr	r3, [pc, #80]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000abe:	4a15      	ldr	r2, [pc, #84]	@ (8000b14 <MX_USART1_UART_Init+0x5c>)
 8000ac0:	601a      	str	r2, [r3, #0]
  huart1.Init.BaudRate = 115200;
 8000ac2:	4b13      	ldr	r3, [pc, #76]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000ac4:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 8000ac8:	605a      	str	r2, [r3, #4]
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8000aca:	4b11      	ldr	r3, [pc, #68]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000acc:	2200      	movs	r2, #0
 8000ace:	609a      	str	r2, [r3, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 8000ad0:	4b0f      	ldr	r3, [pc, #60]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000ad2:	2200      	movs	r2, #0
 8000ad4:	60da      	str	r2, [r3, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8000ad6:	4b0e      	ldr	r3, [pc, #56]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000ad8:	2200      	movs	r2, #0
 8000ada:	611a      	str	r2, [r3, #16]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8000adc:	4b0c      	ldr	r3, [pc, #48]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000ade:	220c      	movs	r2, #12
 8000ae0:	615a      	str	r2, [r3, #20]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8000ae2:	4b0b      	ldr	r3, [pc, #44]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000ae4:	2200      	movs	r2, #0
 8000ae6:	619a      	str	r2, [r3, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8000ae8:	4b09      	ldr	r3, [pc, #36]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000aea:	2200      	movs	r2, #0
 8000aec:	61da      	str	r2, [r3, #28]
  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 8000aee:	4b08      	ldr	r3, [pc, #32]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000af0:	2200      	movs	r2, #0
 8000af2:	621a      	str	r2, [r3, #32]
  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 8000af4:	4b06      	ldr	r3, [pc, #24]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000af6:	2200      	movs	r2, #0
 8000af8:	625a      	str	r2, [r3, #36]	@ 0x24
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8000afa:	4805      	ldr	r0, [pc, #20]	@ (8000b10 <MX_USART1_UART_Init+0x58>)
 8000afc:	f003 fc30 	bl	8004360 <HAL_UART_Init>
 8000b00:	4603      	mov	r3, r0
 8000b02:	2b00      	cmp	r3, #0
 8000b04:	d001      	beq.n	8000b0a <MX_USART1_UART_Init+0x52>
  {
    Error_Handler();
 8000b06:	f000 fa29 	bl	8000f5c <Error_Handler>
  }
  /* USER CODE BEGIN USART1_Init 2 */

  /* USER CODE END USART1_Init 2 */

}
 8000b0a:	bf00      	nop
 8000b0c:	bd80      	pop	{r7, pc}
 8000b0e:	bf00      	nop
 8000b10:	200001c8 	.word	0x200001c8
 8000b14:	40013800 	.word	0x40013800

08000b18 <MX_USART3_UART_Init>:
  * @brief USART3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART3_UART_Init(void)
{
 8000b18:	b580      	push	{r7, lr}
 8000b1a:	af00      	add	r7, sp, #0
  /* USER CODE END USART3_Init 0 */

  /* USER CODE BEGIN USART3_Init 1 */

  /* USER CODE END USART3_Init 1 */
  huart3.Instance = USART3;
 8000b1c:	4b14      	ldr	r3, [pc, #80]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b1e:	4a15      	ldr	r2, [pc, #84]	@ (8000b74 <MX_USART3_UART_Init+0x5c>)
 8000b20:	601a      	str	r2, [r3, #0]
  huart3.Init.BaudRate = 115200;
 8000b22:	4b13      	ldr	r3, [pc, #76]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b24:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 8000b28:	605a      	str	r2, [r3, #4]
  huart3.Init.WordLength = UART_WORDLENGTH_8B;
 8000b2a:	4b11      	ldr	r3, [pc, #68]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b2c:	2200      	movs	r2, #0
 8000b2e:	609a      	str	r2, [r3, #8]
  huart3.Init.StopBits = UART_STOPBITS_1;
 8000b30:	4b0f      	ldr	r3, [pc, #60]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b32:	2200      	movs	r2, #0
 8000b34:	60da      	str	r2, [r3, #12]
  huart3.Init.Parity = UART_PARITY_NONE;
 8000b36:	4b0e      	ldr	r3, [pc, #56]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b38:	2200      	movs	r2, #0
 8000b3a:	611a      	str	r2, [r3, #16]
  huart3.Init.Mode = UART_MODE_TX_RX;
 8000b3c:	4b0c      	ldr	r3, [pc, #48]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b3e:	220c      	movs	r2, #12
 8000b40:	615a      	str	r2, [r3, #20]
  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8000b42:	4b0b      	ldr	r3, [pc, #44]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b44:	2200      	movs	r2, #0
 8000b46:	619a      	str	r2, [r3, #24]
  huart3.Init.OverSampling = UART_OVERSAMPLING_16;
 8000b48:	4b09      	ldr	r3, [pc, #36]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b4a:	2200      	movs	r2, #0
 8000b4c:	61da      	str	r2, [r3, #28]
  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 8000b4e:	4b08      	ldr	r3, [pc, #32]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b50:	2200      	movs	r2, #0
 8000b52:	621a      	str	r2, [r3, #32]
  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 8000b54:	4b06      	ldr	r3, [pc, #24]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b56:	2200      	movs	r2, #0
 8000b58:	625a      	str	r2, [r3, #36]	@ 0x24
  if (HAL_UART_Init(&huart3) != HAL_OK)
 8000b5a:	4805      	ldr	r0, [pc, #20]	@ (8000b70 <MX_USART3_UART_Init+0x58>)
 8000b5c:	f003 fc00 	bl	8004360 <HAL_UART_Init>
 8000b60:	4603      	mov	r3, r0
 8000b62:	2b00      	cmp	r3, #0
 8000b64:	d001      	beq.n	8000b6a <MX_USART3_UART_Init+0x52>
  {
    Error_Handler();
 8000b66:	f000 f9f9 	bl	8000f5c <Error_Handler>
  }
  /* USER CODE BEGIN USART3_Init 2 */

  /* USER CODE END USART3_Init 2 */

}
 8000b6a:	bf00      	nop
 8000b6c:	bd80      	pop	{r7, pc}
 8000b6e:	bf00      	nop
 8000b70:	20000250 	.word	0x20000250
 8000b74:	40004800 	.word	0x40004800

08000b78 <MX_USB_OTG_FS_PCD_Init>:
  * @brief USB_OTG_FS Initialization Function
  * @param None
  * @retval None
  */
static void MX_USB_OTG_FS_PCD_Init(void)
{
 8000b78:	b580      	push	{r7, lr}
 8000b7a:	af00      	add	r7, sp, #0
  /* USER CODE END USB_OTG_FS_Init 0 */

  /* USER CODE BEGIN USB_OTG_FS_Init 1 */

  /* USER CODE END USB_OTG_FS_Init 1 */
  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
 8000b7c:	4b14      	ldr	r3, [pc, #80]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000b7e:	f04f 42a0 	mov.w	r2, #1342177280	@ 0x50000000
 8000b82:	601a      	str	r2, [r3, #0]
  hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
 8000b84:	4b12      	ldr	r3, [pc, #72]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000b86:	2206      	movs	r2, #6
 8000b88:	711a      	strb	r2, [r3, #4]
  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
 8000b8a:	4b11      	ldr	r3, [pc, #68]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000b8c:	2202      	movs	r2, #2
 8000b8e:	71da      	strb	r2, [r3, #7]
  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
 8000b90:	4b0f      	ldr	r3, [pc, #60]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000b92:	2202      	movs	r2, #2
 8000b94:	725a      	strb	r2, [r3, #9]
  hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
 8000b96:	4b0e      	ldr	r3, [pc, #56]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000b98:	2200      	movs	r2, #0
 8000b9a:	729a      	strb	r2, [r3, #10]
  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
 8000b9c:	4b0c      	ldr	r3, [pc, #48]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000b9e:	2200      	movs	r2, #0
 8000ba0:	72da      	strb	r2, [r3, #11]
  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
 8000ba2:	4b0b      	ldr	r3, [pc, #44]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000ba4:	2200      	movs	r2, #0
 8000ba6:	731a      	strb	r2, [r3, #12]
  hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
 8000ba8:	4b09      	ldr	r3, [pc, #36]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000baa:	2200      	movs	r2, #0
 8000bac:	735a      	strb	r2, [r3, #13]
  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
 8000bae:	4b08      	ldr	r3, [pc, #32]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000bb0:	2200      	movs	r2, #0
 8000bb2:	73da      	strb	r2, [r3, #15]
  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
 8000bb4:	4b06      	ldr	r3, [pc, #24]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000bb6:	2200      	movs	r2, #0
 8000bb8:	739a      	strb	r2, [r3, #14]
  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
 8000bba:	4805      	ldr	r0, [pc, #20]	@ (8000bd0 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000bbc:	f001 faf7 	bl	80021ae <HAL_PCD_Init>
 8000bc0:	4603      	mov	r3, r0
 8000bc2:	2b00      	cmp	r3, #0
 8000bc4:	d001      	beq.n	8000bca <MX_USB_OTG_FS_PCD_Init+0x52>
  {
    Error_Handler();
 8000bc6:	f000 f9c9 	bl	8000f5c <Error_Handler>
  }
  /* USER CODE BEGIN USB_OTG_FS_Init 2 */

  /* USER CODE END USB_OTG_FS_Init 2 */

}
 8000bca:	bf00      	nop
 8000bcc:	bd80      	pop	{r7, pc}
 8000bce:	bf00      	nop
 8000bd0:	200002d8 	.word	0x200002d8

08000bd4 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8000bd4:	b580      	push	{r7, lr}
 8000bd6:	b08a      	sub	sp, #40	@ 0x28
 8000bd8:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000bda:	f107 0314 	add.w	r3, r7, #20
 8000bde:	2200      	movs	r2, #0
 8000be0:	601a      	str	r2, [r3, #0]
 8000be2:	605a      	str	r2, [r3, #4]
 8000be4:	609a      	str	r2, [r3, #8]
 8000be6:	60da      	str	r2, [r3, #12]
 8000be8:	611a      	str	r2, [r3, #16]
  /* USER CODE BEGIN MX_GPIO_Init_1 */

  /* USER CODE END MX_GPIO_Init_1 */

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8000bea:	4bbd      	ldr	r3, [pc, #756]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000bec:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000bee:	4abc      	ldr	r2, [pc, #752]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000bf0:	f043 0310 	orr.w	r3, r3, #16
 8000bf4:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000bf6:	4bba      	ldr	r3, [pc, #744]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000bf8:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000bfa:	f003 0310 	and.w	r3, r3, #16
 8000bfe:	613b      	str	r3, [r7, #16]
 8000c00:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8000c02:	4bb7      	ldr	r3, [pc, #732]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c04:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000c06:	4ab6      	ldr	r2, [pc, #728]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c08:	f043 0304 	orr.w	r3, r3, #4
 8000c0c:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000c0e:	4bb4      	ldr	r3, [pc, #720]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c10:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000c12:	f003 0304 	and.w	r3, r3, #4
 8000c16:	60fb      	str	r3, [r7, #12]
 8000c18:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8000c1a:	4bb1      	ldr	r3, [pc, #708]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c1c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000c1e:	4ab0      	ldr	r2, [pc, #704]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c20:	f043 0301 	orr.w	r3, r3, #1
 8000c24:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000c26:	4bae      	ldr	r3, [pc, #696]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c28:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000c2a:	f003 0301 	and.w	r3, r3, #1
 8000c2e:	60bb      	str	r3, [r7, #8]
 8000c30:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8000c32:	4bab      	ldr	r3, [pc, #684]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c34:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000c36:	4aaa      	ldr	r2, [pc, #680]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c38:	f043 0302 	orr.w	r3, r3, #2
 8000c3c:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000c3e:	4ba8      	ldr	r3, [pc, #672]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c40:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000c42:	f003 0302 	and.w	r3, r3, #2
 8000c46:	607b      	str	r3, [r7, #4]
 8000c48:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8000c4a:	4ba5      	ldr	r3, [pc, #660]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c4c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000c4e:	4aa4      	ldr	r2, [pc, #656]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c50:	f043 0308 	orr.w	r3, r3, #8
 8000c54:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000c56:	4ba2      	ldr	r3, [pc, #648]	@ (8000ee0 <MX_GPIO_Init+0x30c>)
 8000c58:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000c5a:	f003 0308 	and.w	r3, r3, #8
 8000c5e:	603b      	str	r3, [r7, #0]
 8000c60:	683b      	ldr	r3, [r7, #0]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET);
 8000c62:	2200      	movs	r2, #0
 8000c64:	f44f 718a 	mov.w	r1, #276	@ 0x114
 8000c68:	489e      	ldr	r0, [pc, #632]	@ (8000ee4 <MX_GPIO_Init+0x310>)
 8000c6a:	f001 f933 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|GPIO_PIN_5|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET);
 8000c6e:	2200      	movs	r2, #0
 8000c70:	f248 1124 	movw	r1, #33060	@ 0x8124
 8000c74:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000c78:	f001 f92c 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
 8000c7c:	2200      	movs	r2, #0
 8000c7e:	f24f 0114 	movw	r1, #61460	@ 0xf014
 8000c82:	4899      	ldr	r0, [pc, #612]	@ (8000ee8 <MX_GPIO_Init+0x314>)
 8000c84:	f001 f926 	bl	8001ed4 <HAL_GPIO_WritePin>
                          |SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET);
 8000c88:	2200      	movs	r2, #0
 8000c8a:	f241 0181 	movw	r1, #4225	@ 0x1081
 8000c8e:	4897      	ldr	r0, [pc, #604]	@ (8000eec <MX_GPIO_Init+0x318>)
 8000c90:	f001 f920 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET);
 8000c94:	2201      	movs	r2, #1
 8000c96:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 8000c9a:	4894      	ldr	r0, [pc, #592]	@ (8000eec <MX_GPIO_Init+0x318>)
 8000c9c:	f001 f91a 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET);
 8000ca0:	2200      	movs	r2, #0
 8000ca2:	f44f 7110 	mov.w	r1, #576	@ 0x240
 8000ca6:	4892      	ldr	r0, [pc, #584]	@ (8000ef0 <MX_GPIO_Init+0x31c>)
 8000ca8:	f001 f914 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET);
 8000cac:	2201      	movs	r2, #1
 8000cae:	2120      	movs	r1, #32
 8000cb0:	488d      	ldr	r0, [pc, #564]	@ (8000ee8 <MX_GPIO_Init+0x314>)
 8000cb2:	f001 f90f 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET);
 8000cb6:	2201      	movs	r2, #1
 8000cb8:	2101      	movs	r1, #1
 8000cba:	488a      	ldr	r0, [pc, #552]	@ (8000ee4 <MX_GPIO_Init+0x310>)
 8000cbc:	f001 f90a 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */
  GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin;
 8000cc0:	f240 1315 	movw	r3, #277	@ 0x115
 8000cc4:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000cc6:	2301      	movs	r3, #1
 8000cc8:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000cca:	2300      	movs	r3, #0
 8000ccc:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000cce:	2300      	movs	r3, #0
 8000cd0:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8000cd2:	f107 0314 	add.w	r3, r7, #20
 8000cd6:	4619      	mov	r1, r3
 8000cd8:	4882      	ldr	r0, [pc, #520]	@ (8000ee4 <MX_GPIO_Init+0x310>)
 8000cda:	f000 ff39 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */
  GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin;
 8000cde:	236a      	movs	r3, #106	@ 0x6a
 8000ce0:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 8000ce2:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
 8000ce6:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000ce8:	2300      	movs	r3, #0
 8000cea:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8000cec:	f107 0314 	add.w	r3, r7, #20
 8000cf0:	4619      	mov	r1, r3
 8000cf2:	487c      	ldr	r0, [pc, #496]	@ (8000ee4 <MX_GPIO_Init+0x310>)
 8000cf4:	f000 ff2c 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pin : BUTTON_EXTI13_Pin */
  GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin;
 8000cf8:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
 8000cfc:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
 8000cfe:	f44f 1304 	mov.w	r3, #2162688	@ 0x210000
 8000d02:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000d04:	2300      	movs	r3, #0
 8000d06:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct);
 8000d08:	f107 0314 	add.w	r3, r7, #20
 8000d0c:	4619      	mov	r1, r3
 8000d0e:	4878      	ldr	r0, [pc, #480]	@ (8000ef0 <MX_GPIO_Init+0x31c>)
 8000d10:	f000 ff1e 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin
                           ARD_A1_Pin ARD_A0_Pin */
  GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin
 8000d14:	233f      	movs	r3, #63	@ 0x3f
 8000d16:	617b      	str	r3, [r7, #20]
                          |ARD_A1_Pin|ARD_A0_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
 8000d18:	230b      	movs	r3, #11
 8000d1a:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000d1c:	2300      	movs	r3, #0
 8000d1e:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8000d20:	f107 0314 	add.w	r3, r7, #20
 8000d24:	4619      	mov	r1, r3
 8000d26:	4872      	ldr	r0, [pc, #456]	@ (8000ef0 <MX_GPIO_Init+0x31c>)
 8000d28:	f000 ff12 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */
  GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin;
 8000d2c:	2303      	movs	r3, #3
 8000d2e:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000d30:	2302      	movs	r3, #2
 8000d32:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000d34:	2300      	movs	r3, #0
 8000d36:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000d38:	2303      	movs	r3, #3
 8000d3a:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
 8000d3c:	2308      	movs	r3, #8
 8000d3e:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000d40:	f107 0314 	add.w	r3, r7, #20
 8000d44:	4619      	mov	r1, r3
 8000d46:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000d4a:	f000 ff01 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D10_Pin PA5 SPBTLE_RF_RST_Pin ARD_D9_Pin */
  GPIO_InitStruct.Pin = ARD_D10_Pin|GPIO_PIN_5|SPBTLE_RF_RST_Pin|ARD_D9_Pin;
 8000d4e:	f248 1324 	movw	r3, #33060	@ 0x8124
 8000d52:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000d54:	2301      	movs	r3, #1
 8000d56:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000d58:	2300      	movs	r3, #0
 8000d5a:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000d5c:	2300      	movs	r3, #0
 8000d5e:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000d60:	f107 0314 	add.w	r3, r7, #20
 8000d64:	4619      	mov	r1, r3
 8000d66:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000d6a:	f000 fef1 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pin : ARD_D4_Pin */
  GPIO_InitStruct.Pin = ARD_D4_Pin;
 8000d6e:	2308      	movs	r3, #8
 8000d70:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000d72:	2302      	movs	r3, #2
 8000d74:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000d76:	2300      	movs	r3, #0
 8000d78:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000d7a:	2300      	movs	r3, #0
 8000d7c:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
 8000d7e:	2301      	movs	r3, #1
 8000d80:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct);
 8000d82:	f107 0314 	add.w	r3, r7, #20
 8000d86:	4619      	mov	r1, r3
 8000d88:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000d8c:	f000 fee0 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pin : ARD_D7_Pin */
  GPIO_InitStruct.Pin = ARD_D7_Pin;
 8000d90:	2310      	movs	r3, #16
 8000d92:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
 8000d94:	230b      	movs	r3, #11
 8000d96:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000d98:	2300      	movs	r3, #0
 8000d9a:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct);
 8000d9c:	f107 0314 	add.w	r3, r7, #20
 8000da0:	4619      	mov	r1, r3
 8000da2:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000da6:	f000 fed3 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D12_Pin ARD_D11_Pin */
  GPIO_InitStruct.Pin = ARD_D12_Pin|ARD_D11_Pin;
 8000daa:	23c0      	movs	r3, #192	@ 0xc0
 8000dac:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000dae:	2302      	movs	r3, #2
 8000db0:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000db2:	2300      	movs	r3, #0
 8000db4:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000db6:	2303      	movs	r3, #3
 8000db8:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
 8000dba:	2305      	movs	r3, #5
 8000dbc:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000dbe:	f107 0314 	add.w	r3, r7, #20
 8000dc2:	4619      	mov	r1, r3
 8000dc4:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000dc8:	f000 fec2 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pin : ARD_D3_Pin */
  GPIO_InitStruct.Pin = ARD_D3_Pin;
 8000dcc:	2301      	movs	r3, #1
 8000dce:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 8000dd0:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
 8000dd4:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000dd6:	2300      	movs	r3, #0
 8000dd8:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct);
 8000dda:	f107 0314 	add.w	r3, r7, #20
 8000dde:	4619      	mov	r1, r3
 8000de0:	4841      	ldr	r0, [pc, #260]	@ (8000ee8 <MX_GPIO_Init+0x314>)
 8000de2:	f000 feb5 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pin : ARD_D6_Pin */
  GPIO_InitStruct.Pin = ARD_D6_Pin;
 8000de6:	2302      	movs	r3, #2
 8000de8:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
 8000dea:	230b      	movs	r3, #11
 8000dec:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000dee:	2300      	movs	r3, #0
 8000df0:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct);
 8000df2:	f107 0314 	add.w	r3, r7, #20
 8000df6:	4619      	mov	r1, r3
 8000df8:	483b      	ldr	r0, [pc, #236]	@ (8000ee8 <MX_GPIO_Init+0x314>)
 8000dfa:	f000 fea9 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin
                           SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */
  GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
 8000dfe:	f24f 0334 	movw	r3, #61492	@ 0xf034
 8000e02:	617b      	str	r3, [r7, #20]
                          |SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000e04:	2301      	movs	r3, #1
 8000e06:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000e08:	2300      	movs	r3, #0
 8000e0a:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000e0c:	2300      	movs	r3, #0
 8000e0e:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000e10:	f107 0314 	add.w	r3, r7, #20
 8000e14:	4619      	mov	r1, r3
 8000e16:	4834      	ldr	r0, [pc, #208]	@ (8000ee8 <MX_GPIO_Init+0x314>)
 8000e18:	f000 fe9a 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin
                           PMOD_IRQ_EXTI12_Pin */
  GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin
 8000e1c:	f64c 4304 	movw	r3, #52228	@ 0xcc04
 8000e20:	617b      	str	r3, [r7, #20]
                          |PMOD_IRQ_EXTI12_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 8000e22:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
 8000e26:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000e28:	2300      	movs	r3, #0
 8000e2a:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8000e2c:	f107 0314 	add.w	r3, r7, #20
 8000e30:	4619      	mov	r1, r3
 8000e32:	482e      	ldr	r0, [pc, #184]	@ (8000eec <MX_GPIO_Init+0x318>)
 8000e34:	f000 fe8c 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */
  GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin;
 8000e38:	f243 0381 	movw	r3, #12417	@ 0x3081
 8000e3c:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000e3e:	2301      	movs	r3, #1
 8000e40:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000e42:	2300      	movs	r3, #0
 8000e44:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000e46:	2300      	movs	r3, #0
 8000e48:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8000e4a:	f107 0314 	add.w	r3, r7, #20
 8000e4e:	4619      	mov	r1, r3
 8000e50:	4826      	ldr	r0, [pc, #152]	@ (8000eec <MX_GPIO_Init+0x318>)
 8000e52:	f000 fe7d 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */
  GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin;
 8000e56:	f44f 7310 	mov.w	r3, #576	@ 0x240
 8000e5a:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000e5c:	2301      	movs	r3, #1
 8000e5e:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000e60:	2300      	movs	r3, #0
 8000e62:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000e64:	2300      	movs	r3, #0
 8000e66:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8000e68:	f107 0314 	add.w	r3, r7, #20
 8000e6c:	4619      	mov	r1, r3
 8000e6e:	4820      	ldr	r0, [pc, #128]	@ (8000ef0 <MX_GPIO_Init+0x31c>)
 8000e70:	f000 fe6e 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */
  GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin;
 8000e74:	f44f 73c0 	mov.w	r3, #384	@ 0x180
 8000e78:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 8000e7a:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
 8000e7e:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000e80:	2300      	movs	r3, #0
 8000e82:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8000e84:	f107 0314 	add.w	r3, r7, #20
 8000e88:	4619      	mov	r1, r3
 8000e8a:	4819      	ldr	r0, [pc, #100]	@ (8000ef0 <MX_GPIO_Init+0x31c>)
 8000e8c:	f000 fe60 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pin : PMOD_SPI2_SCK_Pin */
  GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin;
 8000e90:	2302      	movs	r3, #2
 8000e92:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000e94:	2302      	movs	r3, #2
 8000e96:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000e98:	2300      	movs	r3, #0
 8000e9a:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000e9c:	2303      	movs	r3, #3
 8000e9e:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
 8000ea0:	2305      	movs	r3, #5
 8000ea2:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct);
 8000ea4:	f107 0314 	add.w	r3, r7, #20
 8000ea8:	4619      	mov	r1, r3
 8000eaa:	4810      	ldr	r0, [pc, #64]	@ (8000eec <MX_GPIO_Init+0x318>)
 8000eac:	f000 fe50 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */
  GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin;
 8000eb0:	2378      	movs	r3, #120	@ 0x78
 8000eb2:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000eb4:	2302      	movs	r3, #2
 8000eb6:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000eb8:	2300      	movs	r3, #0
 8000eba:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000ebc:	2303      	movs	r3, #3
 8000ebe:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
 8000ec0:	2307      	movs	r3, #7
 8000ec2:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8000ec4:	f107 0314 	add.w	r3, r7, #20
 8000ec8:	4619      	mov	r1, r3
 8000eca:	4808      	ldr	r0, [pc, #32]	@ (8000eec <MX_GPIO_Init+0x318>)
 8000ecc:	f000 fe40 	bl	8001b50 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */
  GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin;
 8000ed0:	f44f 7340 	mov.w	r3, #768	@ 0x300
 8000ed4:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 8000ed6:	2312      	movs	r3, #18
 8000ed8:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000eda:	2300      	movs	r3, #0
 8000edc:	e00a      	b.n	8000ef4 <MX_GPIO_Init+0x320>
 8000ede:	bf00      	nop
 8000ee0:	40021000 	.word	0x40021000
 8000ee4:	48001000 	.word	0x48001000
 8000ee8:	48000400 	.word	0x48000400
 8000eec:	48000c00 	.word	0x48000c00
 8000ef0:	48000800 	.word	0x48000800
 8000ef4:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000ef6:	2303      	movs	r3, #3
 8000ef8:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
 8000efa:	2304      	movs	r3, #4
 8000efc:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000efe:	f107 0314 	add.w	r3, r7, #20
 8000f02:	4619      	mov	r1, r3
 8000f04:	480b      	ldr	r0, [pc, #44]	@ (8000f34 <MX_GPIO_Init+0x360>)
 8000f06:	f000 fe23 	bl	8001b50 <HAL_GPIO_Init>

  /* EXTI interrupt init*/
  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
 8000f0a:	2200      	movs	r2, #0
 8000f0c:	2105      	movs	r1, #5
 8000f0e:	2017      	movs	r0, #23
 8000f10:	f000 fce8 	bl	80018e4 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
 8000f14:	2017      	movs	r0, #23
 8000f16:	f000 fd01 	bl	800191c <HAL_NVIC_EnableIRQ>

  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
 8000f1a:	2200      	movs	r2, #0
 8000f1c:	2105      	movs	r1, #5
 8000f1e:	2028      	movs	r0, #40	@ 0x28
 8000f20:	f000 fce0 	bl	80018e4 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
 8000f24:	2028      	movs	r0, #40	@ 0x28
 8000f26:	f000 fcf9 	bl	800191c <HAL_NVIC_EnableIRQ>

  /* USER CODE BEGIN MX_GPIO_Init_2 */

  /* USER CODE END MX_GPIO_Init_2 */
}
 8000f2a:	bf00      	nop
 8000f2c:	3728      	adds	r7, #40	@ 0x28
 8000f2e:	46bd      	mov	sp, r7
 8000f30:	bd80      	pop	{r7, pc}
 8000f32:	bf00      	nop
 8000f34:	48000400 	.word	0x48000400

08000f38 <HAL_TIM_PeriodElapsedCallback>:
  * a global variable "uwTick" used as application time base.
  * @param  htim : TIM handle
  * @retval None
  */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 8000f38:	b580      	push	{r7, lr}
 8000f3a:	b082      	sub	sp, #8
 8000f3c:	af00      	add	r7, sp, #0
 8000f3e:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN Callback 0 */

  /* USER CODE END Callback 0 */
  if (htim->Instance == TIM17)
 8000f40:	687b      	ldr	r3, [r7, #4]
 8000f42:	681b      	ldr	r3, [r3, #0]
 8000f44:	4a04      	ldr	r2, [pc, #16]	@ (8000f58 <HAL_TIM_PeriodElapsedCallback+0x20>)
 8000f46:	4293      	cmp	r3, r2
 8000f48:	d101      	bne.n	8000f4e <HAL_TIM_PeriodElapsedCallback+0x16>
  {
    HAL_IncTick();
 8000f4a:	f000 fbcf 	bl	80016ec <HAL_IncTick>
  }
  /* USER CODE BEGIN Callback 1 */

  /* USER CODE END Callback 1 */
}
 8000f4e:	bf00      	nop
 8000f50:	3708      	adds	r7, #8
 8000f52:	46bd      	mov	sp, r7
 8000f54:	bd80      	pop	{r7, pc}
 8000f56:	bf00      	nop
 8000f58:	40014800 	.word	0x40014800

08000f5c <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8000f5c:	b480      	push	{r7}
 8000f5e:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8000f60:	b672      	cpsid	i
}
 8000f62:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 8000f64:	bf00      	nop
 8000f66:	e7fd      	b.n	8000f64 <Error_Handler+0x8>

08000f68 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8000f68:	b580      	push	{r7, lr}
 8000f6a:	b082      	sub	sp, #8
 8000f6c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8000f6e:	4b11      	ldr	r3, [pc, #68]	@ (8000fb4 <HAL_MspInit+0x4c>)
 8000f70:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8000f72:	4a10      	ldr	r2, [pc, #64]	@ (8000fb4 <HAL_MspInit+0x4c>)
 8000f74:	f043 0301 	orr.w	r3, r3, #1
 8000f78:	6613      	str	r3, [r2, #96]	@ 0x60
 8000f7a:	4b0e      	ldr	r3, [pc, #56]	@ (8000fb4 <HAL_MspInit+0x4c>)
 8000f7c:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8000f7e:	f003 0301 	and.w	r3, r3, #1
 8000f82:	607b      	str	r3, [r7, #4]
 8000f84:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 8000f86:	4b0b      	ldr	r3, [pc, #44]	@ (8000fb4 <HAL_MspInit+0x4c>)
 8000f88:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8000f8a:	4a0a      	ldr	r2, [pc, #40]	@ (8000fb4 <HAL_MspInit+0x4c>)
 8000f8c:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8000f90:	6593      	str	r3, [r2, #88]	@ 0x58
 8000f92:	4b08      	ldr	r3, [pc, #32]	@ (8000fb4 <HAL_MspInit+0x4c>)
 8000f94:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8000f96:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8000f9a:	603b      	str	r3, [r7, #0]
 8000f9c:	683b      	ldr	r3, [r7, #0]

  /* System interrupt init*/
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 8000f9e:	2200      	movs	r2, #0
 8000fa0:	210f      	movs	r1, #15
 8000fa2:	f06f 0001 	mvn.w	r0, #1
 8000fa6:	f000 fc9d 	bl	80018e4 <HAL_NVIC_SetPriority>

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8000faa:	bf00      	nop
 8000fac:	3708      	adds	r7, #8
 8000fae:	46bd      	mov	sp, r7
 8000fb0:	bd80      	pop	{r7, pc}
 8000fb2:	bf00      	nop
 8000fb4:	40021000 	.word	0x40021000

08000fb8 <HAL_DFSDM_ChannelMspInit>:
  * This function configures the hardware resources used in this example
  * @param hdfsdm_channel: DFSDM_Channel handle pointer
  * @retval None
  */
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)
{
 8000fb8:	b580      	push	{r7, lr}
 8000fba:	b0ac      	sub	sp, #176	@ 0xb0
 8000fbc:	af00      	add	r7, sp, #0
 8000fbe:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000fc0:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8000fc4:	2200      	movs	r2, #0
 8000fc6:	601a      	str	r2, [r3, #0]
 8000fc8:	605a      	str	r2, [r3, #4]
 8000fca:	609a      	str	r2, [r3, #8]
 8000fcc:	60da      	str	r2, [r3, #12]
 8000fce:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000fd0:	f107 0314 	add.w	r3, r7, #20
 8000fd4:	2288      	movs	r2, #136	@ 0x88
 8000fd6:	2100      	movs	r1, #0
 8000fd8:	4618      	mov	r0, r3
 8000fda:	f006 ffe5 	bl	8007fa8 <memset>
  if(DFSDM1_Init == 0)
 8000fde:	4b25      	ldr	r3, [pc, #148]	@ (8001074 <HAL_DFSDM_ChannelMspInit+0xbc>)
 8000fe0:	681b      	ldr	r3, [r3, #0]
 8000fe2:	2b00      	cmp	r3, #0
 8000fe4:	d142      	bne.n	800106c <HAL_DFSDM_ChannelMspInit+0xb4>

    /* USER CODE END DFSDM1_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1;
 8000fe6:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
 8000fea:	617b      	str	r3, [r7, #20]
    PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
 8000fec:	2300      	movs	r3, #0
 8000fee:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8000ff2:	f107 0314 	add.w	r3, r7, #20
 8000ff6:	4618      	mov	r0, r3
 8000ff8:	f002 f97e 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 8000ffc:	4603      	mov	r3, r0
 8000ffe:	2b00      	cmp	r3, #0
 8001000:	d001      	beq.n	8001006 <HAL_DFSDM_ChannelMspInit+0x4e>
    {
      Error_Handler();
 8001002:	f7ff ffab 	bl	8000f5c <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_DFSDM1_CLK_ENABLE();
 8001006:	4b1c      	ldr	r3, [pc, #112]	@ (8001078 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8001008:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800100a:	4a1b      	ldr	r2, [pc, #108]	@ (8001078 <HAL_DFSDM_ChannelMspInit+0xc0>)
 800100c:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8001010:	6613      	str	r3, [r2, #96]	@ 0x60
 8001012:	4b19      	ldr	r3, [pc, #100]	@ (8001078 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8001014:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001016:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 800101a:	613b      	str	r3, [r7, #16]
 800101c:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOE_CLK_ENABLE();
 800101e:	4b16      	ldr	r3, [pc, #88]	@ (8001078 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8001020:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001022:	4a15      	ldr	r2, [pc, #84]	@ (8001078 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8001024:	f043 0310 	orr.w	r3, r3, #16
 8001028:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800102a:	4b13      	ldr	r3, [pc, #76]	@ (8001078 <HAL_DFSDM_ChannelMspInit+0xc0>)
 800102c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800102e:	f003 0310 	and.w	r3, r3, #16
 8001032:	60fb      	str	r3, [r7, #12]
 8001034:	68fb      	ldr	r3, [r7, #12]
    /**DFSDM1 GPIO Configuration
    PE7     ------> DFSDM1_DATIN2
    PE9     ------> DFSDM1_CKOUT
    */
    GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin;
 8001036:	f44f 7320 	mov.w	r3, #640	@ 0x280
 800103a:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800103e:	2302      	movs	r3, #2
 8001040:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001044:	2300      	movs	r3, #0
 8001046:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 800104a:	2300      	movs	r3, #0
 800104c:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1;
 8001050:	2306      	movs	r3, #6
 8001052:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8001056:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 800105a:	4619      	mov	r1, r3
 800105c:	4807      	ldr	r0, [pc, #28]	@ (800107c <HAL_DFSDM_ChannelMspInit+0xc4>)
 800105e:	f000 fd77 	bl	8001b50 <HAL_GPIO_Init>

    /* USER CODE BEGIN DFSDM1_MspInit 1 */

    /* USER CODE END DFSDM1_MspInit 1 */

  DFSDM1_Init++;
 8001062:	4b04      	ldr	r3, [pc, #16]	@ (8001074 <HAL_DFSDM_ChannelMspInit+0xbc>)
 8001064:	681b      	ldr	r3, [r3, #0]
 8001066:	3301      	adds	r3, #1
 8001068:	4a02      	ldr	r2, [pc, #8]	@ (8001074 <HAL_DFSDM_ChannelMspInit+0xbc>)
 800106a:	6013      	str	r3, [r2, #0]
  }

}
 800106c:	bf00      	nop
 800106e:	37b0      	adds	r7, #176	@ 0xb0
 8001070:	46bd      	mov	sp, r7
 8001072:	bd80      	pop	{r7, pc}
 8001074:	200007bc 	.word	0x200007bc
 8001078:	40021000 	.word	0x40021000
 800107c:	48001000 	.word	0x48001000

08001080 <HAL_I2C_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hi2c: I2C handle pointer
  * @retval None
  */
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
 8001080:	b580      	push	{r7, lr}
 8001082:	b0ac      	sub	sp, #176	@ 0xb0
 8001084:	af00      	add	r7, sp, #0
 8001086:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001088:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 800108c:	2200      	movs	r2, #0
 800108e:	601a      	str	r2, [r3, #0]
 8001090:	605a      	str	r2, [r3, #4]
 8001092:	609a      	str	r2, [r3, #8]
 8001094:	60da      	str	r2, [r3, #12]
 8001096:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8001098:	f107 0314 	add.w	r3, r7, #20
 800109c:	2288      	movs	r2, #136	@ 0x88
 800109e:	2100      	movs	r1, #0
 80010a0:	4618      	mov	r0, r3
 80010a2:	f006 ff81 	bl	8007fa8 <memset>
  if(hi2c->Instance==I2C2)
 80010a6:	687b      	ldr	r3, [r7, #4]
 80010a8:	681b      	ldr	r3, [r3, #0]
 80010aa:	4a21      	ldr	r2, [pc, #132]	@ (8001130 <HAL_I2C_MspInit+0xb0>)
 80010ac:	4293      	cmp	r3, r2
 80010ae:	d13b      	bne.n	8001128 <HAL_I2C_MspInit+0xa8>

    /* USER CODE END I2C2_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
 80010b0:	2380      	movs	r3, #128	@ 0x80
 80010b2:	617b      	str	r3, [r7, #20]
    PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
 80010b4:	2300      	movs	r3, #0
 80010b6:	66bb      	str	r3, [r7, #104]	@ 0x68
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 80010b8:	f107 0314 	add.w	r3, r7, #20
 80010bc:	4618      	mov	r0, r3
 80010be:	f002 f91b 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 80010c2:	4603      	mov	r3, r0
 80010c4:	2b00      	cmp	r3, #0
 80010c6:	d001      	beq.n	80010cc <HAL_I2C_MspInit+0x4c>
    {
      Error_Handler();
 80010c8:	f7ff ff48 	bl	8000f5c <Error_Handler>
    }

    __HAL_RCC_GPIOB_CLK_ENABLE();
 80010cc:	4b19      	ldr	r3, [pc, #100]	@ (8001134 <HAL_I2C_MspInit+0xb4>)
 80010ce:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80010d0:	4a18      	ldr	r2, [pc, #96]	@ (8001134 <HAL_I2C_MspInit+0xb4>)
 80010d2:	f043 0302 	orr.w	r3, r3, #2
 80010d6:	64d3      	str	r3, [r2, #76]	@ 0x4c
 80010d8:	4b16      	ldr	r3, [pc, #88]	@ (8001134 <HAL_I2C_MspInit+0xb4>)
 80010da:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80010dc:	f003 0302 	and.w	r3, r3, #2
 80010e0:	613b      	str	r3, [r7, #16]
 80010e2:	693b      	ldr	r3, [r7, #16]
    /**I2C2 GPIO Configuration
    PB10     ------> I2C2_SCL
    PB11     ------> I2C2_SDA
    */
    GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin;
 80010e4:	f44f 6340 	mov.w	r3, #3072	@ 0xc00
 80010e8:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 80010ec:	2312      	movs	r3, #18
 80010ee:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    GPIO_InitStruct.Pull = GPIO_PULLUP;
 80010f2:	2301      	movs	r3, #1
 80010f4:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 80010f8:	2303      	movs	r3, #3
 80010fa:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
 80010fe:	2304      	movs	r3, #4
 8001100:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001104:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8001108:	4619      	mov	r1, r3
 800110a:	480b      	ldr	r0, [pc, #44]	@ (8001138 <HAL_I2C_MspInit+0xb8>)
 800110c:	f000 fd20 	bl	8001b50 <HAL_GPIO_Init>

    /* Peripheral clock enable */
    __HAL_RCC_I2C2_CLK_ENABLE();
 8001110:	4b08      	ldr	r3, [pc, #32]	@ (8001134 <HAL_I2C_MspInit+0xb4>)
 8001112:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8001114:	4a07      	ldr	r2, [pc, #28]	@ (8001134 <HAL_I2C_MspInit+0xb4>)
 8001116:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
 800111a:	6593      	str	r3, [r2, #88]	@ 0x58
 800111c:	4b05      	ldr	r3, [pc, #20]	@ (8001134 <HAL_I2C_MspInit+0xb4>)
 800111e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8001120:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 8001124:	60fb      	str	r3, [r7, #12]
 8001126:	68fb      	ldr	r3, [r7, #12]

    /* USER CODE END I2C2_MspInit 1 */

  }

}
 8001128:	bf00      	nop
 800112a:	37b0      	adds	r7, #176	@ 0xb0
 800112c:	46bd      	mov	sp, r7
 800112e:	bd80      	pop	{r7, pc}
 8001130:	40005800 	.word	0x40005800
 8001134:	40021000 	.word	0x40021000
 8001138:	48000400 	.word	0x48000400

0800113c <HAL_QSPI_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hqspi: QSPI handle pointer
  * @retval None
  */
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
{
 800113c:	b580      	push	{r7, lr}
 800113e:	b08a      	sub	sp, #40	@ 0x28
 8001140:	af00      	add	r7, sp, #0
 8001142:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001144:	f107 0314 	add.w	r3, r7, #20
 8001148:	2200      	movs	r2, #0
 800114a:	601a      	str	r2, [r3, #0]
 800114c:	605a      	str	r2, [r3, #4]
 800114e:	609a      	str	r2, [r3, #8]
 8001150:	60da      	str	r2, [r3, #12]
 8001152:	611a      	str	r2, [r3, #16]
  if(hqspi->Instance==QUADSPI)
 8001154:	687b      	ldr	r3, [r7, #4]
 8001156:	681b      	ldr	r3, [r3, #0]
 8001158:	4a17      	ldr	r2, [pc, #92]	@ (80011b8 <HAL_QSPI_MspInit+0x7c>)
 800115a:	4293      	cmp	r3, r2
 800115c:	d128      	bne.n	80011b0 <HAL_QSPI_MspInit+0x74>
  {
    /* USER CODE BEGIN QUADSPI_MspInit 0 */

    /* USER CODE END QUADSPI_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_QSPI_CLK_ENABLE();
 800115e:	4b17      	ldr	r3, [pc, #92]	@ (80011bc <HAL_QSPI_MspInit+0x80>)
 8001160:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8001162:	4a16      	ldr	r2, [pc, #88]	@ (80011bc <HAL_QSPI_MspInit+0x80>)
 8001164:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8001168:	6513      	str	r3, [r2, #80]	@ 0x50
 800116a:	4b14      	ldr	r3, [pc, #80]	@ (80011bc <HAL_QSPI_MspInit+0x80>)
 800116c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800116e:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8001172:	613b      	str	r3, [r7, #16]
 8001174:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOE_CLK_ENABLE();
 8001176:	4b11      	ldr	r3, [pc, #68]	@ (80011bc <HAL_QSPI_MspInit+0x80>)
 8001178:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800117a:	4a10      	ldr	r2, [pc, #64]	@ (80011bc <HAL_QSPI_MspInit+0x80>)
 800117c:	f043 0310 	orr.w	r3, r3, #16
 8001180:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8001182:	4b0e      	ldr	r3, [pc, #56]	@ (80011bc <HAL_QSPI_MspInit+0x80>)
 8001184:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001186:	f003 0310 	and.w	r3, r3, #16
 800118a:	60fb      	str	r3, [r7, #12]
 800118c:	68fb      	ldr	r3, [r7, #12]
    PE12     ------> QUADSPI_BK1_IO0
    PE13     ------> QUADSPI_BK1_IO1
    PE14     ------> QUADSPI_BK1_IO2
    PE15     ------> QUADSPI_BK1_IO3
    */
    GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin
 800118e:	f44f 437c 	mov.w	r3, #64512	@ 0xfc00
 8001192:	617b      	str	r3, [r7, #20]
                          |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8001194:	2302      	movs	r3, #2
 8001196:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001198:	2300      	movs	r3, #0
 800119a:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 800119c:	2303      	movs	r3, #3
 800119e:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
 80011a0:	230a      	movs	r3, #10
 80011a2:	627b      	str	r3, [r7, #36]	@ 0x24
    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 80011a4:	f107 0314 	add.w	r3, r7, #20
 80011a8:	4619      	mov	r1, r3
 80011aa:	4805      	ldr	r0, [pc, #20]	@ (80011c0 <HAL_QSPI_MspInit+0x84>)
 80011ac:	f000 fcd0 	bl	8001b50 <HAL_GPIO_Init>

    /* USER CODE END QUADSPI_MspInit 1 */

  }

}
 80011b0:	bf00      	nop
 80011b2:	3728      	adds	r7, #40	@ 0x28
 80011b4:	46bd      	mov	sp, r7
 80011b6:	bd80      	pop	{r7, pc}
 80011b8:	a0001000 	.word	0xa0001000
 80011bc:	40021000 	.word	0x40021000
 80011c0:	48001000 	.word	0x48001000

080011c4 <HAL_SPI_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hspi: SPI handle pointer
  * @retval None
  */
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
 80011c4:	b580      	push	{r7, lr}
 80011c6:	b08a      	sub	sp, #40	@ 0x28
 80011c8:	af00      	add	r7, sp, #0
 80011ca:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80011cc:	f107 0314 	add.w	r3, r7, #20
 80011d0:	2200      	movs	r2, #0
 80011d2:	601a      	str	r2, [r3, #0]
 80011d4:	605a      	str	r2, [r3, #4]
 80011d6:	609a      	str	r2, [r3, #8]
 80011d8:	60da      	str	r2, [r3, #12]
 80011da:	611a      	str	r2, [r3, #16]
  if(hspi->Instance==SPI3)
 80011dc:	687b      	ldr	r3, [r7, #4]
 80011de:	681b      	ldr	r3, [r3, #0]
 80011e0:	4a17      	ldr	r2, [pc, #92]	@ (8001240 <HAL_SPI_MspInit+0x7c>)
 80011e2:	4293      	cmp	r3, r2
 80011e4:	d128      	bne.n	8001238 <HAL_SPI_MspInit+0x74>
  {
    /* USER CODE BEGIN SPI3_MspInit 0 */

    /* USER CODE END SPI3_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_SPI3_CLK_ENABLE();
 80011e6:	4b17      	ldr	r3, [pc, #92]	@ (8001244 <HAL_SPI_MspInit+0x80>)
 80011e8:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80011ea:	4a16      	ldr	r2, [pc, #88]	@ (8001244 <HAL_SPI_MspInit+0x80>)
 80011ec:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
 80011f0:	6593      	str	r3, [r2, #88]	@ 0x58
 80011f2:	4b14      	ldr	r3, [pc, #80]	@ (8001244 <HAL_SPI_MspInit+0x80>)
 80011f4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80011f6:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 80011fa:	613b      	str	r3, [r7, #16]
 80011fc:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOC_CLK_ENABLE();
 80011fe:	4b11      	ldr	r3, [pc, #68]	@ (8001244 <HAL_SPI_MspInit+0x80>)
 8001200:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001202:	4a10      	ldr	r2, [pc, #64]	@ (8001244 <HAL_SPI_MspInit+0x80>)
 8001204:	f043 0304 	orr.w	r3, r3, #4
 8001208:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800120a:	4b0e      	ldr	r3, [pc, #56]	@ (8001244 <HAL_SPI_MspInit+0x80>)
 800120c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800120e:	f003 0304 	and.w	r3, r3, #4
 8001212:	60fb      	str	r3, [r7, #12]
 8001214:	68fb      	ldr	r3, [r7, #12]
    /**SPI3 GPIO Configuration
    PC10     ------> SPI3_SCK
    PC11     ------> SPI3_MISO
    PC12     ------> SPI3_MOSI
    */
    GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin;
 8001216:	f44f 53e0 	mov.w	r3, #7168	@ 0x1c00
 800121a:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800121c:	2302      	movs	r3, #2
 800121e:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001220:	2300      	movs	r3, #0
 8001222:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8001224:	2303      	movs	r3, #3
 8001226:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
 8001228:	2306      	movs	r3, #6
 800122a:	627b      	str	r3, [r7, #36]	@ 0x24
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800122c:	f107 0314 	add.w	r3, r7, #20
 8001230:	4619      	mov	r1, r3
 8001232:	4805      	ldr	r0, [pc, #20]	@ (8001248 <HAL_SPI_MspInit+0x84>)
 8001234:	f000 fc8c 	bl	8001b50 <HAL_GPIO_Init>

    /* USER CODE END SPI3_MspInit 1 */

  }

}
 8001238:	bf00      	nop
 800123a:	3728      	adds	r7, #40	@ 0x28
 800123c:	46bd      	mov	sp, r7
 800123e:	bd80      	pop	{r7, pc}
 8001240:	40003c00 	.word	0x40003c00
 8001244:	40021000 	.word	0x40021000
 8001248:	48000800 	.word	0x48000800

0800124c <HAL_UART_MspInit>:
  * This function configures the hardware resources used in this example
  * @param huart: UART handle pointer
  * @retval None
  */
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 800124c:	b580      	push	{r7, lr}
 800124e:	b0ae      	sub	sp, #184	@ 0xb8
 8001250:	af00      	add	r7, sp, #0
 8001252:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001254:	f107 03a4 	add.w	r3, r7, #164	@ 0xa4
 8001258:	2200      	movs	r2, #0
 800125a:	601a      	str	r2, [r3, #0]
 800125c:	605a      	str	r2, [r3, #4]
 800125e:	609a      	str	r2, [r3, #8]
 8001260:	60da      	str	r2, [r3, #12]
 8001262:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8001264:	f107 031c 	add.w	r3, r7, #28
 8001268:	2288      	movs	r2, #136	@ 0x88
 800126a:	2100      	movs	r1, #0
 800126c:	4618      	mov	r0, r3
 800126e:	f006 fe9b 	bl	8007fa8 <memset>
  if(huart->Instance==USART1)
 8001272:	687b      	ldr	r3, [r7, #4]
 8001274:	681b      	ldr	r3, [r3, #0]
 8001276:	4a42      	ldr	r2, [pc, #264]	@ (8001380 <HAL_UART_MspInit+0x134>)
 8001278:	4293      	cmp	r3, r2
 800127a:	d13b      	bne.n	80012f4 <HAL_UART_MspInit+0xa8>

    /* USER CODE END USART1_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
 800127c:	2301      	movs	r3, #1
 800127e:	61fb      	str	r3, [r7, #28]
    PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
 8001280:	2300      	movs	r3, #0
 8001282:	657b      	str	r3, [r7, #84]	@ 0x54
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8001284:	f107 031c 	add.w	r3, r7, #28
 8001288:	4618      	mov	r0, r3
 800128a:	f002 f835 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 800128e:	4603      	mov	r3, r0
 8001290:	2b00      	cmp	r3, #0
 8001292:	d001      	beq.n	8001298 <HAL_UART_MspInit+0x4c>
    {
      Error_Handler();
 8001294:	f7ff fe62 	bl	8000f5c <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 8001298:	4b3a      	ldr	r3, [pc, #232]	@ (8001384 <HAL_UART_MspInit+0x138>)
 800129a:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800129c:	4a39      	ldr	r2, [pc, #228]	@ (8001384 <HAL_UART_MspInit+0x138>)
 800129e:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
 80012a2:	6613      	str	r3, [r2, #96]	@ 0x60
 80012a4:	4b37      	ldr	r3, [pc, #220]	@ (8001384 <HAL_UART_MspInit+0x138>)
 80012a6:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80012a8:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 80012ac:	61bb      	str	r3, [r7, #24]
 80012ae:	69bb      	ldr	r3, [r7, #24]

    __HAL_RCC_GPIOB_CLK_ENABLE();
 80012b0:	4b34      	ldr	r3, [pc, #208]	@ (8001384 <HAL_UART_MspInit+0x138>)
 80012b2:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80012b4:	4a33      	ldr	r2, [pc, #204]	@ (8001384 <HAL_UART_MspInit+0x138>)
 80012b6:	f043 0302 	orr.w	r3, r3, #2
 80012ba:	64d3      	str	r3, [r2, #76]	@ 0x4c
 80012bc:	4b31      	ldr	r3, [pc, #196]	@ (8001384 <HAL_UART_MspInit+0x138>)
 80012be:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80012c0:	f003 0302 	and.w	r3, r3, #2
 80012c4:	617b      	str	r3, [r7, #20]
 80012c6:	697b      	ldr	r3, [r7, #20]
    /**USART1 GPIO Configuration
    PB6     ------> USART1_TX
    PB7     ------> USART1_RX
    */
    GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin;
 80012c8:	23c0      	movs	r3, #192	@ 0xc0
 80012ca:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 80012ce:	2302      	movs	r3, #2
 80012d0:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80012d4:	2300      	movs	r3, #0
 80012d6:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 80012da:	2303      	movs	r3, #3
 80012dc:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
 80012e0:	2307      	movs	r3, #7
 80012e2:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 80012e6:	f107 03a4 	add.w	r3, r7, #164	@ 0xa4
 80012ea:	4619      	mov	r1, r3
 80012ec:	4826      	ldr	r0, [pc, #152]	@ (8001388 <HAL_UART_MspInit+0x13c>)
 80012ee:	f000 fc2f 	bl	8001b50 <HAL_GPIO_Init>
    /* USER CODE BEGIN USART3_MspInit 1 */

    /* USER CODE END USART3_MspInit 1 */
  }

}
 80012f2:	e040      	b.n	8001376 <HAL_UART_MspInit+0x12a>
  else if(huart->Instance==USART3)
 80012f4:	687b      	ldr	r3, [r7, #4]
 80012f6:	681b      	ldr	r3, [r3, #0]
 80012f8:	4a24      	ldr	r2, [pc, #144]	@ (800138c <HAL_UART_MspInit+0x140>)
 80012fa:	4293      	cmp	r3, r2
 80012fc:	d13b      	bne.n	8001376 <HAL_UART_MspInit+0x12a>
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3;
 80012fe:	2304      	movs	r3, #4
 8001300:	61fb      	str	r3, [r7, #28]
    PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
 8001302:	2300      	movs	r3, #0
 8001304:	65fb      	str	r3, [r7, #92]	@ 0x5c
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8001306:	f107 031c 	add.w	r3, r7, #28
 800130a:	4618      	mov	r0, r3
 800130c:	f001 fff4 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 8001310:	4603      	mov	r3, r0
 8001312:	2b00      	cmp	r3, #0
 8001314:	d001      	beq.n	800131a <HAL_UART_MspInit+0xce>
      Error_Handler();
 8001316:	f7ff fe21 	bl	8000f5c <Error_Handler>
    __HAL_RCC_USART3_CLK_ENABLE();
 800131a:	4b1a      	ldr	r3, [pc, #104]	@ (8001384 <HAL_UART_MspInit+0x138>)
 800131c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800131e:	4a19      	ldr	r2, [pc, #100]	@ (8001384 <HAL_UART_MspInit+0x138>)
 8001320:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 8001324:	6593      	str	r3, [r2, #88]	@ 0x58
 8001326:	4b17      	ldr	r3, [pc, #92]	@ (8001384 <HAL_UART_MspInit+0x138>)
 8001328:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800132a:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 800132e:	613b      	str	r3, [r7, #16]
 8001330:	693b      	ldr	r3, [r7, #16]
    __HAL_RCC_GPIOD_CLK_ENABLE();
 8001332:	4b14      	ldr	r3, [pc, #80]	@ (8001384 <HAL_UART_MspInit+0x138>)
 8001334:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001336:	4a13      	ldr	r2, [pc, #76]	@ (8001384 <HAL_UART_MspInit+0x138>)
 8001338:	f043 0308 	orr.w	r3, r3, #8
 800133c:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800133e:	4b11      	ldr	r3, [pc, #68]	@ (8001384 <HAL_UART_MspInit+0x138>)
 8001340:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001342:	f003 0308 	and.w	r3, r3, #8
 8001346:	60fb      	str	r3, [r7, #12]
 8001348:	68fb      	ldr	r3, [r7, #12]
    GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin;
 800134a:	f44f 7340 	mov.w	r3, #768	@ 0x300
 800134e:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8001352:	2302      	movs	r3, #2
 8001354:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001358:	2300      	movs	r3, #0
 800135a:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 800135e:	2303      	movs	r3, #3
 8001360:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
 8001364:	2307      	movs	r3, #7
 8001366:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 800136a:	f107 03a4 	add.w	r3, r7, #164	@ 0xa4
 800136e:	4619      	mov	r1, r3
 8001370:	4807      	ldr	r0, [pc, #28]	@ (8001390 <HAL_UART_MspInit+0x144>)
 8001372:	f000 fbed 	bl	8001b50 <HAL_GPIO_Init>
}
 8001376:	bf00      	nop
 8001378:	37b8      	adds	r7, #184	@ 0xb8
 800137a:	46bd      	mov	sp, r7
 800137c:	bd80      	pop	{r7, pc}
 800137e:	bf00      	nop
 8001380:	40013800 	.word	0x40013800
 8001384:	40021000 	.word	0x40021000
 8001388:	48000400 	.word	0x48000400
 800138c:	40004800 	.word	0x40004800
 8001390:	48000c00 	.word	0x48000c00

08001394 <HAL_PCD_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hpcd: PCD handle pointer
  * @retval None
  */
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
 8001394:	b580      	push	{r7, lr}
 8001396:	b0ac      	sub	sp, #176	@ 0xb0
 8001398:	af00      	add	r7, sp, #0
 800139a:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800139c:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 80013a0:	2200      	movs	r2, #0
 80013a2:	601a      	str	r2, [r3, #0]
 80013a4:	605a      	str	r2, [r3, #4]
 80013a6:	609a      	str	r2, [r3, #8]
 80013a8:	60da      	str	r2, [r3, #12]
 80013aa:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 80013ac:	f107 0314 	add.w	r3, r7, #20
 80013b0:	2288      	movs	r2, #136	@ 0x88
 80013b2:	2100      	movs	r1, #0
 80013b4:	4618      	mov	r0, r3
 80013b6:	f006 fdf7 	bl	8007fa8 <memset>
  if(hpcd->Instance==USB_OTG_FS)
 80013ba:	687b      	ldr	r3, [r7, #4]
 80013bc:	681b      	ldr	r3, [r3, #0]
 80013be:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 80013c2:	d17c      	bne.n	80014be <HAL_PCD_MspInit+0x12a>

    /* USER CODE END USB_OTG_FS_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
 80013c4:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
 80013c8:	617b      	str	r3, [r7, #20]
    PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
 80013ca:	f04f 6380 	mov.w	r3, #67108864	@ 0x4000000
 80013ce:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
    PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
 80013d2:	2301      	movs	r3, #1
 80013d4:	61bb      	str	r3, [r7, #24]
    PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
 80013d6:	2301      	movs	r3, #1
 80013d8:	61fb      	str	r3, [r7, #28]
    PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
 80013da:	2318      	movs	r3, #24
 80013dc:	623b      	str	r3, [r7, #32]
    PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
 80013de:	2307      	movs	r3, #7
 80013e0:	627b      	str	r3, [r7, #36]	@ 0x24
    PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
 80013e2:	2302      	movs	r3, #2
 80013e4:	62bb      	str	r3, [r7, #40]	@ 0x28
    PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
 80013e6:	2302      	movs	r3, #2
 80013e8:	62fb      	str	r3, [r7, #44]	@ 0x2c
    PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
 80013ea:	f44f 1380 	mov.w	r3, #1048576	@ 0x100000
 80013ee:	633b      	str	r3, [r7, #48]	@ 0x30
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 80013f0:	f107 0314 	add.w	r3, r7, #20
 80013f4:	4618      	mov	r0, r3
 80013f6:	f001 ff7f 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 80013fa:	4603      	mov	r3, r0
 80013fc:	2b00      	cmp	r3, #0
 80013fe:	d001      	beq.n	8001404 <HAL_PCD_MspInit+0x70>
    {
      Error_Handler();
 8001400:	f7ff fdac 	bl	8000f5c <Error_Handler>
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8001404:	4b30      	ldr	r3, [pc, #192]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 8001406:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001408:	4a2f      	ldr	r2, [pc, #188]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 800140a:	f043 0301 	orr.w	r3, r3, #1
 800140e:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8001410:	4b2d      	ldr	r3, [pc, #180]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 8001412:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001414:	f003 0301 	and.w	r3, r3, #1
 8001418:	613b      	str	r3, [r7, #16]
 800141a:	693b      	ldr	r3, [r7, #16]
    PA9     ------> USB_OTG_FS_VBUS
    PA10     ------> USB_OTG_FS_ID
    PA11     ------> USB_OTG_FS_DM
    PA12     ------> USB_OTG_FS_DP
    */
    GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin;
 800141c:	f44f 7300 	mov.w	r3, #512	@ 0x200
 8001420:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001424:	2300      	movs	r3, #0
 8001426:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800142a:	2300      	movs	r3, #0
 800142c:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
 8001430:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8001434:	4619      	mov	r1, r3
 8001436:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 800143a:	f000 fb89 	bl	8001b50 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin;
 800143e:	f44f 53e0 	mov.w	r3, #7168	@ 0x1c00
 8001442:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8001446:	2302      	movs	r3, #2
 8001448:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800144c:	2300      	movs	r3, #0
 800144e:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8001452:	2303      	movs	r3, #3
 8001454:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
 8001458:	230a      	movs	r3, #10
 800145a:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800145e:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8001462:	4619      	mov	r1, r3
 8001464:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8001468:	f000 fb72 	bl	8001b50 <HAL_GPIO_Init>

    /* Peripheral clock enable */
    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 800146c:	4b16      	ldr	r3, [pc, #88]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 800146e:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001470:	4a15      	ldr	r2, [pc, #84]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 8001472:	f443 5380 	orr.w	r3, r3, #4096	@ 0x1000
 8001476:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8001478:	4b13      	ldr	r3, [pc, #76]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 800147a:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800147c:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 8001480:	60fb      	str	r3, [r7, #12]
 8001482:	68fb      	ldr	r3, [r7, #12]

    /* Enable VDDUSB */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8001484:	4b10      	ldr	r3, [pc, #64]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 8001486:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8001488:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 800148c:	2b00      	cmp	r3, #0
 800148e:	d114      	bne.n	80014ba <HAL_PCD_MspInit+0x126>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8001490:	4b0d      	ldr	r3, [pc, #52]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 8001492:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8001494:	4a0c      	ldr	r2, [pc, #48]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 8001496:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 800149a:	6593      	str	r3, [r2, #88]	@ 0x58
 800149c:	4b0a      	ldr	r3, [pc, #40]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 800149e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80014a0:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 80014a4:	60bb      	str	r3, [r7, #8]
 80014a6:	68bb      	ldr	r3, [r7, #8]
      HAL_PWREx_EnableVddUSB();
 80014a8:	f001 f828 	bl	80024fc <HAL_PWREx_EnableVddUSB>
      __HAL_RCC_PWR_CLK_DISABLE();
 80014ac:	4b06      	ldr	r3, [pc, #24]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 80014ae:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80014b0:	4a05      	ldr	r2, [pc, #20]	@ (80014c8 <HAL_PCD_MspInit+0x134>)
 80014b2:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 80014b6:	6593      	str	r3, [r2, #88]	@ 0x58

    /* USER CODE END USB_OTG_FS_MspInit 1 */

  }

}
 80014b8:	e001      	b.n	80014be <HAL_PCD_MspInit+0x12a>
      HAL_PWREx_EnableVddUSB();
 80014ba:	f001 f81f 	bl	80024fc <HAL_PWREx_EnableVddUSB>
}
 80014be:	bf00      	nop
 80014c0:	37b0      	adds	r7, #176	@ 0xb0
 80014c2:	46bd      	mov	sp, r7
 80014c4:	bd80      	pop	{r7, pc}
 80014c6:	bf00      	nop
 80014c8:	40021000 	.word	0x40021000

080014cc <HAL_InitTick>:
  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
  * @param  TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 80014cc:	b580      	push	{r7, lr}
 80014ce:	b08c      	sub	sp, #48	@ 0x30
 80014d0:	af00      	add	r7, sp, #0
 80014d2:	6078      	str	r0, [r7, #4]
  RCC_ClkInitTypeDef    clkconfig;
  uint32_t              uwTimclock;
  uint32_t              uwPrescalerValue;
  uint32_t              pFLatency;

  HAL_StatusTypeDef     status = HAL_OK;
 80014d4:	2300      	movs	r3, #0
 80014d6:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f

  /* Enable TIM17 clock */
  __HAL_RCC_TIM17_CLK_ENABLE();
 80014da:	4b2e      	ldr	r3, [pc, #184]	@ (8001594 <HAL_InitTick+0xc8>)
 80014dc:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80014de:	4a2d      	ldr	r2, [pc, #180]	@ (8001594 <HAL_InitTick+0xc8>)
 80014e0:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 80014e4:	6613      	str	r3, [r2, #96]	@ 0x60
 80014e6:	4b2b      	ldr	r3, [pc, #172]	@ (8001594 <HAL_InitTick+0xc8>)
 80014e8:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80014ea:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 80014ee:	60bb      	str	r3, [r7, #8]
 80014f0:	68bb      	ldr	r3, [r7, #8]

  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
 80014f2:	f107 020c 	add.w	r2, r7, #12
 80014f6:	f107 0310 	add.w	r3, r7, #16
 80014fa:	4611      	mov	r1, r2
 80014fc:	4618      	mov	r0, r3
 80014fe:	f001 fe69 	bl	80031d4 <HAL_RCC_GetClockConfig>

  /* Compute TIM17 clock */
      uwTimclock = HAL_RCC_GetPCLK2Freq();
 8001502:	f001 fe51 	bl	80031a8 <HAL_RCC_GetPCLK2Freq>
 8001506:	62b8      	str	r0, [r7, #40]	@ 0x28

  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
 8001508:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800150a:	4a23      	ldr	r2, [pc, #140]	@ (8001598 <HAL_InitTick+0xcc>)
 800150c:	fba2 2303 	umull	r2, r3, r2, r3
 8001510:	0c9b      	lsrs	r3, r3, #18
 8001512:	3b01      	subs	r3, #1
 8001514:	627b      	str	r3, [r7, #36]	@ 0x24

  /* Initialize TIM17 */
  htim17.Instance = TIM17;
 8001516:	4b21      	ldr	r3, [pc, #132]	@ (800159c <HAL_InitTick+0xd0>)
 8001518:	4a21      	ldr	r2, [pc, #132]	@ (80015a0 <HAL_InitTick+0xd4>)
 800151a:	601a      	str	r2, [r3, #0]
   * Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
   * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
   * ClockDivision = 0
   * Counter direction = Up
   */
  htim17.Init.Period = (1000000U / 1000U) - 1U;
 800151c:	4b1f      	ldr	r3, [pc, #124]	@ (800159c <HAL_InitTick+0xd0>)
 800151e:	f240 32e7 	movw	r2, #999	@ 0x3e7
 8001522:	60da      	str	r2, [r3, #12]
  htim17.Init.Prescaler = uwPrescalerValue;
 8001524:	4a1d      	ldr	r2, [pc, #116]	@ (800159c <HAL_InitTick+0xd0>)
 8001526:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8001528:	6053      	str	r3, [r2, #4]
  htim17.Init.ClockDivision = 0;
 800152a:	4b1c      	ldr	r3, [pc, #112]	@ (800159c <HAL_InitTick+0xd0>)
 800152c:	2200      	movs	r2, #0
 800152e:	611a      	str	r2, [r3, #16]
  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
 8001530:	4b1a      	ldr	r3, [pc, #104]	@ (800159c <HAL_InitTick+0xd0>)
 8001532:	2200      	movs	r2, #0
 8001534:	609a      	str	r2, [r3, #8]
  htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8001536:	4b19      	ldr	r3, [pc, #100]	@ (800159c <HAL_InitTick+0xd0>)
 8001538:	2200      	movs	r2, #0
 800153a:	619a      	str	r2, [r3, #24]

  status = HAL_TIM_Base_Init(&htim17);
 800153c:	4817      	ldr	r0, [pc, #92]	@ (800159c <HAL_InitTick+0xd0>)
 800153e:	f002 fc4a 	bl	8003dd6 <HAL_TIM_Base_Init>
 8001542:	4603      	mov	r3, r0
 8001544:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
  if (status == HAL_OK)
 8001548:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 800154c:	2b00      	cmp	r3, #0
 800154e:	d11b      	bne.n	8001588 <HAL_InitTick+0xbc>
  {
    /* Start the TIM time Base generation in interrupt mode */
    status = HAL_TIM_Base_Start_IT(&htim17);
 8001550:	4812      	ldr	r0, [pc, #72]	@ (800159c <HAL_InitTick+0xd0>)
 8001552:	f002 fca1 	bl	8003e98 <HAL_TIM_Base_Start_IT>
 8001556:	4603      	mov	r3, r0
 8001558:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    if (status == HAL_OK)
 800155c:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 8001560:	2b00      	cmp	r3, #0
 8001562:	d111      	bne.n	8001588 <HAL_InitTick+0xbc>
    {
    /* Enable the TIM17 global Interrupt */
        HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn);
 8001564:	201a      	movs	r0, #26
 8001566:	f000 f9d9 	bl	800191c <HAL_NVIC_EnableIRQ>
      /* Configure the SysTick IRQ priority */
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 800156a:	687b      	ldr	r3, [r7, #4]
 800156c:	2b0f      	cmp	r3, #15
 800156e:	d808      	bhi.n	8001582 <HAL_InitTick+0xb6>
      {
        /* Configure the TIM IRQ priority */
        HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority, 0U);
 8001570:	2200      	movs	r2, #0
 8001572:	6879      	ldr	r1, [r7, #4]
 8001574:	201a      	movs	r0, #26
 8001576:	f000 f9b5 	bl	80018e4 <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 800157a:	4a0a      	ldr	r2, [pc, #40]	@ (80015a4 <HAL_InitTick+0xd8>)
 800157c:	687b      	ldr	r3, [r7, #4]
 800157e:	6013      	str	r3, [r2, #0]
 8001580:	e002      	b.n	8001588 <HAL_InitTick+0xbc>
      }
      else
      {
        status = HAL_ERROR;
 8001582:	2301      	movs	r3, #1
 8001584:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
      }
    }
  }

 /* Return function status */
  return status;
 8001588:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
}
 800158c:	4618      	mov	r0, r3
 800158e:	3730      	adds	r7, #48	@ 0x30
 8001590:	46bd      	mov	sp, r7
 8001592:	bd80      	pop	{r7, pc}
 8001594:	40021000 	.word	0x40021000
 8001598:	431bde83 	.word	0x431bde83
 800159c:	200007c0 	.word	0x200007c0
 80015a0:	40014800 	.word	0x40014800
 80015a4:	20000008 	.word	0x20000008

080015a8 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 80015a8:	b480      	push	{r7}
 80015aa:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
 80015ac:	bf00      	nop
 80015ae:	e7fd      	b.n	80015ac <NMI_Handler+0x4>

080015b0 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80015b0:	b480      	push	{r7}
 80015b2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 80015b4:	bf00      	nop
 80015b6:	e7fd      	b.n	80015b4 <HardFault_Handler+0x4>

080015b8 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 80015b8:	b480      	push	{r7}
 80015ba:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 80015bc:	bf00      	nop
 80015be:	e7fd      	b.n	80015bc <MemManage_Handler+0x4>

080015c0 <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 80015c0:	b480      	push	{r7}
 80015c2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 80015c4:	bf00      	nop
 80015c6:	e7fd      	b.n	80015c4 <BusFault_Handler+0x4>

080015c8 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 80015c8:	b480      	push	{r7}
 80015ca:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 80015cc:	bf00      	nop
 80015ce:	e7fd      	b.n	80015cc <UsageFault_Handler+0x4>

080015d0 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 80015d0:	b480      	push	{r7}
 80015d2:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 80015d4:	bf00      	nop
 80015d6:	46bd      	mov	sp, r7
 80015d8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80015dc:	4770      	bx	lr

080015de <EXTI9_5_IRQHandler>:

/**
  * @brief This function handles EXTI line[9:5] interrupts.
  */
void EXTI9_5_IRQHandler(void)
{
 80015de:	b580      	push	{r7, lr}
 80015e0:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN EXTI9_5_IRQn 0 */

  /* USER CODE END EXTI9_5_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(SPSGRF_915_GPIO3_EXTI5_Pin);
 80015e2:	2020      	movs	r0, #32
 80015e4:	f000 fc8e 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(SPBTLE_RF_IRQ_EXTI6_Pin);
 80015e8:	2040      	movs	r0, #64	@ 0x40
 80015ea:	f000 fc8b 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(VL53L0X_GPIO1_EXTI7_Pin);
 80015ee:	2080      	movs	r0, #128	@ 0x80
 80015f0:	f000 fc88 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(LSM3MDL_DRDY_EXTI8_Pin);
 80015f4:	f44f 7080 	mov.w	r0, #256	@ 0x100
 80015f8:	f000 fc84 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  /* USER CODE BEGIN EXTI9_5_IRQn 1 */

  /* USER CODE END EXTI9_5_IRQn 1 */
}
 80015fc:	bf00      	nop
 80015fe:	bd80      	pop	{r7, pc}

08001600 <TIM1_TRG_COM_TIM17_IRQHandler>:

/**
  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
  */
void TIM1_TRG_COM_TIM17_IRQHandler(void)
{
 8001600:	b580      	push	{r7, lr}
 8001602:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */

  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
  HAL_TIM_IRQHandler(&htim17);
 8001604:	4802      	ldr	r0, [pc, #8]	@ (8001610 <TIM1_TRG_COM_TIM17_IRQHandler+0x10>)
 8001606:	f002 fcb7 	bl	8003f78 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */

  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
}
 800160a:	bf00      	nop
 800160c:	bd80      	pop	{r7, pc}
 800160e:	bf00      	nop
 8001610:	200007c0 	.word	0x200007c0

08001614 <EXTI15_10_IRQHandler>:

/**
  * @brief This function handles EXTI line[15:10] interrupts.
  */
void EXTI15_10_IRQHandler(void)
{
 8001614:	b580      	push	{r7, lr}
 8001616:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN EXTI15_10_IRQn 0 */

  /* USER CODE END EXTI15_10_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(LPS22HB_INT_DRDY_EXTI0_Pin);
 8001618:	f44f 6080 	mov.w	r0, #1024	@ 0x400
 800161c:	f000 fc72 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(LSM6DSL_INT1_EXTI11_Pin);
 8001620:	f44f 6000 	mov.w	r0, #2048	@ 0x800
 8001624:	f000 fc6e 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(BUTTON_EXTI13_Pin);
 8001628:	f44f 5000 	mov.w	r0, #8192	@ 0x2000
 800162c:	f000 fc6a 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(ARD_D2_Pin);
 8001630:	f44f 4080 	mov.w	r0, #16384	@ 0x4000
 8001634:	f000 fc66 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(HTS221_DRDY_EXTI15_Pin);
 8001638:	f44f 4000 	mov.w	r0, #32768	@ 0x8000
 800163c:	f000 fc62 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  /* USER CODE BEGIN EXTI15_10_IRQn 1 */

  /* USER CODE END EXTI15_10_IRQn 1 */
}
 8001640:	bf00      	nop
 8001642:	bd80      	pop	{r7, pc}

08001644 <SystemInit>:
  * @brief  Setup the microcontroller system.
  * @retval None
  */

void SystemInit(void)
{
 8001644:	b480      	push	{r7}
 8001646:	af00      	add	r7, sp, #0
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif

  /* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
 8001648:	4b06      	ldr	r3, [pc, #24]	@ (8001664 <SystemInit+0x20>)
 800164a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800164e:	4a05      	ldr	r2, [pc, #20]	@ (8001664 <SystemInit+0x20>)
 8001650:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8001654:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
#endif
}
 8001658:	bf00      	nop
 800165a:	46bd      	mov	sp, r7
 800165c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001660:	4770      	bx	lr
 8001662:	bf00      	nop
 8001664:	e000ed00 	.word	0xe000ed00

08001668 <Reset_Handler>:

    .section	.text.Reset_Handler
	.weak	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:
  ldr   sp, =_estack    /* Set stack pointer */
 8001668:	f8df d034 	ldr.w	sp, [pc, #52]	@ 80016a0 <LoopForever+0x2>

/* Call the clock system initialization function.*/
    bl  SystemInit
 800166c:	f7ff ffea 	bl	8001644 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8001670:	480c      	ldr	r0, [pc, #48]	@ (80016a4 <LoopForever+0x6>)
  ldr r1, =_edata
 8001672:	490d      	ldr	r1, [pc, #52]	@ (80016a8 <LoopForever+0xa>)
  ldr r2, =_sidata
 8001674:	4a0d      	ldr	r2, [pc, #52]	@ (80016ac <LoopForever+0xe>)
  movs r3, #0
 8001676:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8001678:	e002      	b.n	8001680 <LoopCopyDataInit>

0800167a <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 800167a:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 800167c:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 800167e:	3304      	adds	r3, #4

08001680 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8001680:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8001682:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8001684:	d3f9      	bcc.n	800167a <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8001686:	4a0a      	ldr	r2, [pc, #40]	@ (80016b0 <LoopForever+0x12>)
  ldr r4, =_ebss
 8001688:	4c0a      	ldr	r4, [pc, #40]	@ (80016b4 <LoopForever+0x16>)
  movs r3, #0
 800168a:	2300      	movs	r3, #0
  b LoopFillZerobss
 800168c:	e001      	b.n	8001692 <LoopFillZerobss>

0800168e <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 800168e:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8001690:	3204      	adds	r2, #4

08001692 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8001692:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8001694:	d3fb      	bcc.n	800168e <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 8001696:	f006 fced 	bl	8008074 <__libc_init_array>
/* Call the application's entry point.*/
	bl	main
 800169a:	f7ff f8b2 	bl	8000802 <main>

0800169e <LoopForever>:

LoopForever:
    b LoopForever
 800169e:	e7fe      	b.n	800169e <LoopForever>
  ldr   sp, =_estack    /* Set stack pointer */
 80016a0:	20018000 	.word	0x20018000
  ldr r0, =_sdata
 80016a4:	20000000 	.word	0x20000000
  ldr r1, =_edata
 80016a8:	20000064 	.word	0x20000064
  ldr r2, =_sidata
 80016ac:	08008258 	.word	0x08008258
  ldr r2, =_sbss
 80016b0:	20000064 	.word	0x20000064
  ldr r4, =_ebss
 80016b4:	20008c8c 	.word	0x20008c8c

080016b8 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section	.text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
	b	Infinite_Loop
 80016b8:	e7fe      	b.n	80016b8 <ADC1_2_IRQHandler>

080016ba <HAL_Init>:
  *         each 1ms in the SysTick_Handler() interrupt handler.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 80016ba:	b580      	push	{r7, lr}
 80016bc:	b082      	sub	sp, #8
 80016be:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef  status = HAL_OK;
 80016c0:	2300      	movs	r3, #0
 80016c2:	71fb      	strb	r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 80016c4:	2003      	movs	r0, #3
 80016c6:	f000 f902 	bl	80018ce <HAL_NVIC_SetPriorityGrouping>

  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 80016ca:	200f      	movs	r0, #15
 80016cc:	f7ff fefe 	bl	80014cc <HAL_InitTick>
 80016d0:	4603      	mov	r3, r0
 80016d2:	2b00      	cmp	r3, #0
 80016d4:	d002      	beq.n	80016dc <HAL_Init+0x22>
  {
    status = HAL_ERROR;
 80016d6:	2301      	movs	r3, #1
 80016d8:	71fb      	strb	r3, [r7, #7]
 80016da:	e001      	b.n	80016e0 <HAL_Init+0x26>
  }
  else
  {
    /* Init the low level hardware */
    HAL_MspInit();
 80016dc:	f7ff fc44 	bl	8000f68 <HAL_MspInit>
  }

  /* Return function status */
  return status;
 80016e0:	79fb      	ldrb	r3, [r7, #7]
}
 80016e2:	4618      	mov	r0, r3
 80016e4:	3708      	adds	r7, #8
 80016e6:	46bd      	mov	sp, r7
 80016e8:	bd80      	pop	{r7, pc}
	...

080016ec <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 80016ec:	b480      	push	{r7}
 80016ee:	af00      	add	r7, sp, #0
  uwTick += (uint32_t)uwTickFreq;
 80016f0:	4b06      	ldr	r3, [pc, #24]	@ (800170c <HAL_IncTick+0x20>)
 80016f2:	781b      	ldrb	r3, [r3, #0]
 80016f4:	461a      	mov	r2, r3
 80016f6:	4b06      	ldr	r3, [pc, #24]	@ (8001710 <HAL_IncTick+0x24>)
 80016f8:	681b      	ldr	r3, [r3, #0]
 80016fa:	4413      	add	r3, r2
 80016fc:	4a04      	ldr	r2, [pc, #16]	@ (8001710 <HAL_IncTick+0x24>)
 80016fe:	6013      	str	r3, [r2, #0]
}
 8001700:	bf00      	nop
 8001702:	46bd      	mov	sp, r7
 8001704:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001708:	4770      	bx	lr
 800170a:	bf00      	nop
 800170c:	2000000c 	.word	0x2000000c
 8001710:	2000080c 	.word	0x2000080c

08001714 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8001714:	b480      	push	{r7}
 8001716:	af00      	add	r7, sp, #0
  return uwTick;
 8001718:	4b03      	ldr	r3, [pc, #12]	@ (8001728 <HAL_GetTick+0x14>)
 800171a:	681b      	ldr	r3, [r3, #0]
}
 800171c:	4618      	mov	r0, r3
 800171e:	46bd      	mov	sp, r7
 8001720:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001724:	4770      	bx	lr
 8001726:	bf00      	nop
 8001728:	2000080c 	.word	0x2000080c

0800172c <HAL_Delay>:
  *       implementations in user file.
  * @param Delay  specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 800172c:	b580      	push	{r7, lr}
 800172e:	b084      	sub	sp, #16
 8001730:	af00      	add	r7, sp, #0
 8001732:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 8001734:	f7ff ffee 	bl	8001714 <HAL_GetTick>
 8001738:	60b8      	str	r0, [r7, #8]
  uint32_t wait = Delay;
 800173a:	687b      	ldr	r3, [r7, #4]
 800173c:	60fb      	str	r3, [r7, #12]

  /* Add a period to guaranty minimum wait */
  if (wait < HAL_MAX_DELAY)
 800173e:	68fb      	ldr	r3, [r7, #12]
 8001740:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8001744:	d005      	beq.n	8001752 <HAL_Delay+0x26>
  {
    wait += (uint32_t)uwTickFreq;
 8001746:	4b0a      	ldr	r3, [pc, #40]	@ (8001770 <HAL_Delay+0x44>)
 8001748:	781b      	ldrb	r3, [r3, #0]
 800174a:	461a      	mov	r2, r3
 800174c:	68fb      	ldr	r3, [r7, #12]
 800174e:	4413      	add	r3, r2
 8001750:	60fb      	str	r3, [r7, #12]
  }

  while ((HAL_GetTick() - tickstart) < wait)
 8001752:	bf00      	nop
 8001754:	f7ff ffde 	bl	8001714 <HAL_GetTick>
 8001758:	4602      	mov	r2, r0
 800175a:	68bb      	ldr	r3, [r7, #8]
 800175c:	1ad3      	subs	r3, r2, r3
 800175e:	68fa      	ldr	r2, [r7, #12]
 8001760:	429a      	cmp	r2, r3
 8001762:	d8f7      	bhi.n	8001754 <HAL_Delay+0x28>
  {
  }
}
 8001764:	bf00      	nop
 8001766:	bf00      	nop
 8001768:	3710      	adds	r7, #16
 800176a:	46bd      	mov	sp, r7
 800176c:	bd80      	pop	{r7, pc}
 800176e:	bf00      	nop
 8001770:	2000000c 	.word	0x2000000c

08001774 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8001774:	b480      	push	{r7}
 8001776:	b085      	sub	sp, #20
 8001778:	af00      	add	r7, sp, #0
 800177a:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 800177c:	687b      	ldr	r3, [r7, #4]
 800177e:	f003 0307 	and.w	r3, r3, #7
 8001782:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8001784:	4b0c      	ldr	r3, [pc, #48]	@ (80017b8 <__NVIC_SetPriorityGrouping+0x44>)
 8001786:	68db      	ldr	r3, [r3, #12]
 8001788:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 800178a:	68ba      	ldr	r2, [r7, #8]
 800178c:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
 8001790:	4013      	ands	r3, r2
 8001792:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 8001794:	68fb      	ldr	r3, [r7, #12]
 8001796:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8001798:	68bb      	ldr	r3, [r7, #8]
 800179a:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 800179c:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
 80017a0:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 80017a4:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 80017a6:	4a04      	ldr	r2, [pc, #16]	@ (80017b8 <__NVIC_SetPriorityGrouping+0x44>)
 80017a8:	68bb      	ldr	r3, [r7, #8]
 80017aa:	60d3      	str	r3, [r2, #12]
}
 80017ac:	bf00      	nop
 80017ae:	3714      	adds	r7, #20
 80017b0:	46bd      	mov	sp, r7
 80017b2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80017b6:	4770      	bx	lr
 80017b8:	e000ed00 	.word	0xe000ed00

080017bc <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 80017bc:	b480      	push	{r7}
 80017be:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 80017c0:	4b04      	ldr	r3, [pc, #16]	@ (80017d4 <__NVIC_GetPriorityGrouping+0x18>)
 80017c2:	68db      	ldr	r3, [r3, #12]
 80017c4:	0a1b      	lsrs	r3, r3, #8
 80017c6:	f003 0307 	and.w	r3, r3, #7
}
 80017ca:	4618      	mov	r0, r3
 80017cc:	46bd      	mov	sp, r7
 80017ce:	f85d 7b04 	ldr.w	r7, [sp], #4
 80017d2:	4770      	bx	lr
 80017d4:	e000ed00 	.word	0xe000ed00

080017d8 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 80017d8:	b480      	push	{r7}
 80017da:	b083      	sub	sp, #12
 80017dc:	af00      	add	r7, sp, #0
 80017de:	4603      	mov	r3, r0
 80017e0:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80017e2:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80017e6:	2b00      	cmp	r3, #0
 80017e8:	db0b      	blt.n	8001802 <__NVIC_EnableIRQ+0x2a>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 80017ea:	79fb      	ldrb	r3, [r7, #7]
 80017ec:	f003 021f 	and.w	r2, r3, #31
 80017f0:	4907      	ldr	r1, [pc, #28]	@ (8001810 <__NVIC_EnableIRQ+0x38>)
 80017f2:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80017f6:	095b      	lsrs	r3, r3, #5
 80017f8:	2001      	movs	r0, #1
 80017fa:	fa00 f202 	lsl.w	r2, r0, r2
 80017fe:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    __COMPILER_BARRIER();
  }
}
 8001802:	bf00      	nop
 8001804:	370c      	adds	r7, #12
 8001806:	46bd      	mov	sp, r7
 8001808:	f85d 7b04 	ldr.w	r7, [sp], #4
 800180c:	4770      	bx	lr
 800180e:	bf00      	nop
 8001810:	e000e100 	.word	0xe000e100

08001814 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8001814:	b480      	push	{r7}
 8001816:	b083      	sub	sp, #12
 8001818:	af00      	add	r7, sp, #0
 800181a:	4603      	mov	r3, r0
 800181c:	6039      	str	r1, [r7, #0]
 800181e:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8001820:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001824:	2b00      	cmp	r3, #0
 8001826:	db0a      	blt.n	800183e <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8001828:	683b      	ldr	r3, [r7, #0]
 800182a:	b2da      	uxtb	r2, r3
 800182c:	490c      	ldr	r1, [pc, #48]	@ (8001860 <__NVIC_SetPriority+0x4c>)
 800182e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001832:	0112      	lsls	r2, r2, #4
 8001834:	b2d2      	uxtb	r2, r2
 8001836:	440b      	add	r3, r1
 8001838:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 800183c:	e00a      	b.n	8001854 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800183e:	683b      	ldr	r3, [r7, #0]
 8001840:	b2da      	uxtb	r2, r3
 8001842:	4908      	ldr	r1, [pc, #32]	@ (8001864 <__NVIC_SetPriority+0x50>)
 8001844:	79fb      	ldrb	r3, [r7, #7]
 8001846:	f003 030f 	and.w	r3, r3, #15
 800184a:	3b04      	subs	r3, #4
 800184c:	0112      	lsls	r2, r2, #4
 800184e:	b2d2      	uxtb	r2, r2
 8001850:	440b      	add	r3, r1
 8001852:	761a      	strb	r2, [r3, #24]
}
 8001854:	bf00      	nop
 8001856:	370c      	adds	r7, #12
 8001858:	46bd      	mov	sp, r7
 800185a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800185e:	4770      	bx	lr
 8001860:	e000e100 	.word	0xe000e100
 8001864:	e000ed00 	.word	0xe000ed00

08001868 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8001868:	b480      	push	{r7}
 800186a:	b089      	sub	sp, #36	@ 0x24
 800186c:	af00      	add	r7, sp, #0
 800186e:	60f8      	str	r0, [r7, #12]
 8001870:	60b9      	str	r1, [r7, #8]
 8001872:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8001874:	68fb      	ldr	r3, [r7, #12]
 8001876:	f003 0307 	and.w	r3, r3, #7
 800187a:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 800187c:	69fb      	ldr	r3, [r7, #28]
 800187e:	f1c3 0307 	rsb	r3, r3, #7
 8001882:	2b04      	cmp	r3, #4
 8001884:	bf28      	it	cs
 8001886:	2304      	movcs	r3, #4
 8001888:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800188a:	69fb      	ldr	r3, [r7, #28]
 800188c:	3304      	adds	r3, #4
 800188e:	2b06      	cmp	r3, #6
 8001890:	d902      	bls.n	8001898 <NVIC_EncodePriority+0x30>
 8001892:	69fb      	ldr	r3, [r7, #28]
 8001894:	3b03      	subs	r3, #3
 8001896:	e000      	b.n	800189a <NVIC_EncodePriority+0x32>
 8001898:	2300      	movs	r3, #0
 800189a:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800189c:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 80018a0:	69bb      	ldr	r3, [r7, #24]
 80018a2:	fa02 f303 	lsl.w	r3, r2, r3
 80018a6:	43da      	mvns	r2, r3
 80018a8:	68bb      	ldr	r3, [r7, #8]
 80018aa:	401a      	ands	r2, r3
 80018ac:	697b      	ldr	r3, [r7, #20]
 80018ae:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 80018b0:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80018b4:	697b      	ldr	r3, [r7, #20]
 80018b6:	fa01 f303 	lsl.w	r3, r1, r3
 80018ba:	43d9      	mvns	r1, r3
 80018bc:	687b      	ldr	r3, [r7, #4]
 80018be:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80018c0:	4313      	orrs	r3, r2
         );
}
 80018c2:	4618      	mov	r0, r3
 80018c4:	3724      	adds	r7, #36	@ 0x24
 80018c6:	46bd      	mov	sp, r7
 80018c8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80018cc:	4770      	bx	lr

080018ce <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
  *         The pending IRQ priority will be managed only by the subpriority.
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80018ce:	b580      	push	{r7, lr}
 80018d0:	b082      	sub	sp, #8
 80018d2:	af00      	add	r7, sp, #0
 80018d4:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 80018d6:	6878      	ldr	r0, [r7, #4]
 80018d8:	f7ff ff4c 	bl	8001774 <__NVIC_SetPriorityGrouping>
}
 80018dc:	bf00      	nop
 80018de:	3708      	adds	r7, #8
 80018e0:	46bd      	mov	sp, r7
 80018e2:	bd80      	pop	{r7, pc}

080018e4 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 80018e4:	b580      	push	{r7, lr}
 80018e6:	b086      	sub	sp, #24
 80018e8:	af00      	add	r7, sp, #0
 80018ea:	4603      	mov	r3, r0
 80018ec:	60b9      	str	r1, [r7, #8]
 80018ee:	607a      	str	r2, [r7, #4]
 80018f0:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00;
 80018f2:	2300      	movs	r3, #0
 80018f4:	617b      	str	r3, [r7, #20]

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();
 80018f6:	f7ff ff61 	bl	80017bc <__NVIC_GetPriorityGrouping>
 80018fa:	6178      	str	r0, [r7, #20]

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 80018fc:	687a      	ldr	r2, [r7, #4]
 80018fe:	68b9      	ldr	r1, [r7, #8]
 8001900:	6978      	ldr	r0, [r7, #20]
 8001902:	f7ff ffb1 	bl	8001868 <NVIC_EncodePriority>
 8001906:	4602      	mov	r2, r0
 8001908:	f997 300f 	ldrsb.w	r3, [r7, #15]
 800190c:	4611      	mov	r1, r2
 800190e:	4618      	mov	r0, r3
 8001910:	f7ff ff80 	bl	8001814 <__NVIC_SetPriority>
}
 8001914:	bf00      	nop
 8001916:	3718      	adds	r7, #24
 8001918:	46bd      	mov	sp, r7
 800191a:	bd80      	pop	{r7, pc}

0800191c <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 800191c:	b580      	push	{r7, lr}
 800191e:	b082      	sub	sp, #8
 8001920:	af00      	add	r7, sp, #0
 8001922:	4603      	mov	r3, r0
 8001924:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8001926:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800192a:	4618      	mov	r0, r3
 800192c:	f7ff ff54 	bl	80017d8 <__NVIC_EnableIRQ>
}
 8001930:	bf00      	nop
 8001932:	3708      	adds	r7, #8
 8001934:	46bd      	mov	sp, r7
 8001936:	bd80      	pop	{r7, pc}

08001938 <HAL_DFSDM_ChannelInit>:
  *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
  * @param  hdfsdm_channel DFSDM channel handle.
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
 8001938:	b580      	push	{r7, lr}
 800193a:	b082      	sub	sp, #8
 800193c:	af00      	add	r7, sp, #0
 800193e:	6078      	str	r0, [r7, #4]
  /* Check DFSDM Channel handle */
  if (hdfsdm_channel == NULL)
 8001940:	687b      	ldr	r3, [r7, #4]
 8001942:	2b00      	cmp	r3, #0
 8001944:	d101      	bne.n	800194a <HAL_DFSDM_ChannelInit+0x12>
  {
    return HAL_ERROR;
 8001946:	2301      	movs	r3, #1
 8001948:	e0ac      	b.n	8001aa4 <HAL_DFSDM_ChannelInit+0x16c>
  assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
  assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
  assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));

  /* Check that channel has not been already initialized */
  if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
 800194a:	687b      	ldr	r3, [r7, #4]
 800194c:	681b      	ldr	r3, [r3, #0]
 800194e:	4618      	mov	r0, r3
 8001950:	f000 f8b2 	bl	8001ab8 <DFSDM_GetChannelFromInstance>
 8001954:	4603      	mov	r3, r0
 8001956:	4a55      	ldr	r2, [pc, #340]	@ (8001aac <HAL_DFSDM_ChannelInit+0x174>)
 8001958:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 800195c:	2b00      	cmp	r3, #0
 800195e:	d001      	beq.n	8001964 <HAL_DFSDM_ChannelInit+0x2c>
  {
    return HAL_ERROR;
 8001960:	2301      	movs	r3, #1
 8001962:	e09f      	b.n	8001aa4 <HAL_DFSDM_ChannelInit+0x16c>
    hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
  }
  hdfsdm_channel->MspInitCallback(hdfsdm_channel);
#else
  /* Call MSP init function */
  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
 8001964:	6878      	ldr	r0, [r7, #4]
 8001966:	f7ff fb27 	bl	8000fb8 <HAL_DFSDM_ChannelMspInit>
#endif

  /* Update the channel counter */
  v_dfsdm1ChannelCounter++;
 800196a:	4b51      	ldr	r3, [pc, #324]	@ (8001ab0 <HAL_DFSDM_ChannelInit+0x178>)
 800196c:	681b      	ldr	r3, [r3, #0]
 800196e:	3301      	adds	r3, #1
 8001970:	4a4f      	ldr	r2, [pc, #316]	@ (8001ab0 <HAL_DFSDM_ChannelInit+0x178>)
 8001972:	6013      	str	r3, [r2, #0]

  /* Configure output serial clock and enable global DFSDM interface only for first channel */
  if (v_dfsdm1ChannelCounter == 1U)
 8001974:	4b4e      	ldr	r3, [pc, #312]	@ (8001ab0 <HAL_DFSDM_ChannelInit+0x178>)
 8001976:	681b      	ldr	r3, [r3, #0]
 8001978:	2b01      	cmp	r3, #1
 800197a:	d125      	bne.n	80019c8 <HAL_DFSDM_ChannelInit+0x90>
  {
    assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
    /* Set the output serial clock source */
    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
 800197c:	4b4d      	ldr	r3, [pc, #308]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 800197e:	681b      	ldr	r3, [r3, #0]
 8001980:	4a4c      	ldr	r2, [pc, #304]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 8001982:	f023 4380 	bic.w	r3, r3, #1073741824	@ 0x40000000
 8001986:	6013      	str	r3, [r2, #0]
    DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
 8001988:	4b4a      	ldr	r3, [pc, #296]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 800198a:	681a      	ldr	r2, [r3, #0]
 800198c:	687b      	ldr	r3, [r7, #4]
 800198e:	689b      	ldr	r3, [r3, #8]
 8001990:	4948      	ldr	r1, [pc, #288]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 8001992:	4313      	orrs	r3, r2
 8001994:	600b      	str	r3, [r1, #0]

    /* Reset clock divider */
    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
 8001996:	4b47      	ldr	r3, [pc, #284]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 8001998:	681b      	ldr	r3, [r3, #0]
 800199a:	4a46      	ldr	r2, [pc, #280]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 800199c:	f423 037f 	bic.w	r3, r3, #16711680	@ 0xff0000
 80019a0:	6013      	str	r3, [r2, #0]
    if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
 80019a2:	687b      	ldr	r3, [r7, #4]
 80019a4:	791b      	ldrb	r3, [r3, #4]
 80019a6:	2b01      	cmp	r3, #1
 80019a8:	d108      	bne.n	80019bc <HAL_DFSDM_ChannelInit+0x84>
    {
      assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
      /* Set the output clock divider */
      DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
 80019aa:	4b42      	ldr	r3, [pc, #264]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 80019ac:	681a      	ldr	r2, [r3, #0]
 80019ae:	687b      	ldr	r3, [r7, #4]
 80019b0:	68db      	ldr	r3, [r3, #12]
 80019b2:	3b01      	subs	r3, #1
 80019b4:	041b      	lsls	r3, r3, #16
 80019b6:	493f      	ldr	r1, [pc, #252]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 80019b8:	4313      	orrs	r3, r2
 80019ba:	600b      	str	r3, [r1, #0]
                                             DFSDM_CHCFGR1_CKOUTDIV_Pos);
    }

    /* enable the DFSDM global interface */
    DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
 80019bc:	4b3d      	ldr	r3, [pc, #244]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 80019be:	681b      	ldr	r3, [r3, #0]
 80019c0:	4a3c      	ldr	r2, [pc, #240]	@ (8001ab4 <HAL_DFSDM_ChannelInit+0x17c>)
 80019c2:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
 80019c6:	6013      	str	r3, [r2, #0]
  }

  /* Set channel input parameters */
  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
 80019c8:	687b      	ldr	r3, [r7, #4]
 80019ca:	681b      	ldr	r3, [r3, #0]
 80019cc:	681a      	ldr	r2, [r3, #0]
 80019ce:	687b      	ldr	r3, [r7, #4]
 80019d0:	681b      	ldr	r3, [r3, #0]
 80019d2:	f422 4271 	bic.w	r2, r2, #61696	@ 0xf100
 80019d6:	601a      	str	r2, [r3, #0]
                                         DFSDM_CHCFGR1_CHINSEL);
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
 80019d8:	687b      	ldr	r3, [r7, #4]
 80019da:	681b      	ldr	r3, [r3, #0]
 80019dc:	6819      	ldr	r1, [r3, #0]
 80019de:	687b      	ldr	r3, [r7, #4]
 80019e0:	691a      	ldr	r2, [r3, #16]
                                        hdfsdm_channel->Init.Input.DataPacking |
 80019e2:	687b      	ldr	r3, [r7, #4]
 80019e4:	695b      	ldr	r3, [r3, #20]
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
 80019e6:	431a      	orrs	r2, r3
                                        hdfsdm_channel->Init.Input.Pins);
 80019e8:	687b      	ldr	r3, [r7, #4]
 80019ea:	699b      	ldr	r3, [r3, #24]
                                        hdfsdm_channel->Init.Input.DataPacking |
 80019ec:	431a      	orrs	r2, r3
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
 80019ee:	687b      	ldr	r3, [r7, #4]
 80019f0:	681b      	ldr	r3, [r3, #0]
 80019f2:	430a      	orrs	r2, r1
 80019f4:	601a      	str	r2, [r3, #0]

  /* Set serial interface parameters */
  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
 80019f6:	687b      	ldr	r3, [r7, #4]
 80019f8:	681b      	ldr	r3, [r3, #0]
 80019fa:	681a      	ldr	r2, [r3, #0]
 80019fc:	687b      	ldr	r3, [r7, #4]
 80019fe:	681b      	ldr	r3, [r3, #0]
 8001a00:	f022 020f 	bic.w	r2, r2, #15
 8001a04:	601a      	str	r2, [r3, #0]
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
 8001a06:	687b      	ldr	r3, [r7, #4]
 8001a08:	681b      	ldr	r3, [r3, #0]
 8001a0a:	6819      	ldr	r1, [r3, #0]
 8001a0c:	687b      	ldr	r3, [r7, #4]
 8001a0e:	69da      	ldr	r2, [r3, #28]
                                        hdfsdm_channel->Init.SerialInterface.SpiClock);
 8001a10:	687b      	ldr	r3, [r7, #4]
 8001a12:	6a1b      	ldr	r3, [r3, #32]
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
 8001a14:	431a      	orrs	r2, r3
 8001a16:	687b      	ldr	r3, [r7, #4]
 8001a18:	681b      	ldr	r3, [r3, #0]
 8001a1a:	430a      	orrs	r2, r1
 8001a1c:	601a      	str	r2, [r3, #0]

  /* Set analog watchdog parameters */
  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
 8001a1e:	687b      	ldr	r3, [r7, #4]
 8001a20:	681b      	ldr	r3, [r3, #0]
 8001a22:	689a      	ldr	r2, [r3, #8]
 8001a24:	687b      	ldr	r3, [r7, #4]
 8001a26:	681b      	ldr	r3, [r3, #0]
 8001a28:	f422 025f 	bic.w	r2, r2, #14614528	@ 0xdf0000
 8001a2c:	609a      	str	r2, [r3, #8]
  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
 8001a2e:	687b      	ldr	r3, [r7, #4]
 8001a30:	681b      	ldr	r3, [r3, #0]
 8001a32:	6899      	ldr	r1, [r3, #8]
 8001a34:	687b      	ldr	r3, [r7, #4]
 8001a36:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
                                         ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
 8001a38:	687b      	ldr	r3, [r7, #4]
 8001a3a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8001a3c:	3b01      	subs	r3, #1
 8001a3e:	041b      	lsls	r3, r3, #16
  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
 8001a40:	431a      	orrs	r2, r3
 8001a42:	687b      	ldr	r3, [r7, #4]
 8001a44:	681b      	ldr	r3, [r3, #0]
 8001a46:	430a      	orrs	r2, r1
 8001a48:	609a      	str	r2, [r3, #8]

  /* Set channel offset and right bit shift */
  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
 8001a4a:	687b      	ldr	r3, [r7, #4]
 8001a4c:	681b      	ldr	r3, [r3, #0]
 8001a4e:	685a      	ldr	r2, [r3, #4]
 8001a50:	687b      	ldr	r3, [r7, #4]
 8001a52:	681b      	ldr	r3, [r3, #0]
 8001a54:	f002 0207 	and.w	r2, r2, #7
 8001a58:	605a      	str	r2, [r3, #4]
  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
 8001a5a:	687b      	ldr	r3, [r7, #4]
 8001a5c:	681b      	ldr	r3, [r3, #0]
 8001a5e:	6859      	ldr	r1, [r3, #4]
 8001a60:	687b      	ldr	r3, [r7, #4]
 8001a62:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001a64:	021a      	lsls	r2, r3, #8
                                        (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
 8001a66:	687b      	ldr	r3, [r7, #4]
 8001a68:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8001a6a:	00db      	lsls	r3, r3, #3
  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
 8001a6c:	431a      	orrs	r2, r3
 8001a6e:	687b      	ldr	r3, [r7, #4]
 8001a70:	681b      	ldr	r3, [r3, #0]
 8001a72:	430a      	orrs	r2, r1
 8001a74:	605a      	str	r2, [r3, #4]

  /* Enable DFSDM channel */
  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
 8001a76:	687b      	ldr	r3, [r7, #4]
 8001a78:	681b      	ldr	r3, [r3, #0]
 8001a7a:	681a      	ldr	r2, [r3, #0]
 8001a7c:	687b      	ldr	r3, [r7, #4]
 8001a7e:	681b      	ldr	r3, [r3, #0]
 8001a80:	f042 0280 	orr.w	r2, r2, #128	@ 0x80
 8001a84:	601a      	str	r2, [r3, #0]

  /* Set DFSDM Channel to ready state */
  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
 8001a86:	687b      	ldr	r3, [r7, #4]
 8001a88:	2201      	movs	r2, #1
 8001a8a:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

  /* Store channel handle in DFSDM channel handle table */
  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
 8001a8e:	687b      	ldr	r3, [r7, #4]
 8001a90:	681b      	ldr	r3, [r3, #0]
 8001a92:	4618      	mov	r0, r3
 8001a94:	f000 f810 	bl	8001ab8 <DFSDM_GetChannelFromInstance>
 8001a98:	4602      	mov	r2, r0
 8001a9a:	4904      	ldr	r1, [pc, #16]	@ (8001aac <HAL_DFSDM_ChannelInit+0x174>)
 8001a9c:	687b      	ldr	r3, [r7, #4]
 8001a9e:	f841 3022 	str.w	r3, [r1, r2, lsl #2]

  return HAL_OK;
 8001aa2:	2300      	movs	r3, #0
}
 8001aa4:	4618      	mov	r0, r3
 8001aa6:	3708      	adds	r7, #8
 8001aa8:	46bd      	mov	sp, r7
 8001aaa:	bd80      	pop	{r7, pc}
 8001aac:	20000814 	.word	0x20000814
 8001ab0:	20000810 	.word	0x20000810
 8001ab4:	40016000 	.word	0x40016000

08001ab8 <DFSDM_GetChannelFromInstance>:
  * @brief  This function allows to get the channel number from channel instance.
  * @param  Instance DFSDM channel instance.
  * @retval Channel number.
  */
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
{
 8001ab8:	b480      	push	{r7}
 8001aba:	b085      	sub	sp, #20
 8001abc:	af00      	add	r7, sp, #0
 8001abe:	6078      	str	r0, [r7, #4]
  uint32_t channel;

  /* Get channel from instance */
  if (Instance == DFSDM1_Channel0)
 8001ac0:	687b      	ldr	r3, [r7, #4]
 8001ac2:	4a1c      	ldr	r2, [pc, #112]	@ (8001b34 <DFSDM_GetChannelFromInstance+0x7c>)
 8001ac4:	4293      	cmp	r3, r2
 8001ac6:	d102      	bne.n	8001ace <DFSDM_GetChannelFromInstance+0x16>
  {
    channel = 0;
 8001ac8:	2300      	movs	r3, #0
 8001aca:	60fb      	str	r3, [r7, #12]
 8001acc:	e02b      	b.n	8001b26 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel1)
 8001ace:	687b      	ldr	r3, [r7, #4]
 8001ad0:	4a19      	ldr	r2, [pc, #100]	@ (8001b38 <DFSDM_GetChannelFromInstance+0x80>)
 8001ad2:	4293      	cmp	r3, r2
 8001ad4:	d102      	bne.n	8001adc <DFSDM_GetChannelFromInstance+0x24>
  {
    channel = 1;
 8001ad6:	2301      	movs	r3, #1
 8001ad8:	60fb      	str	r3, [r7, #12]
 8001ada:	e024      	b.n	8001b26 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel2)
 8001adc:	687b      	ldr	r3, [r7, #4]
 8001ade:	4a17      	ldr	r2, [pc, #92]	@ (8001b3c <DFSDM_GetChannelFromInstance+0x84>)
 8001ae0:	4293      	cmp	r3, r2
 8001ae2:	d102      	bne.n	8001aea <DFSDM_GetChannelFromInstance+0x32>
  {
    channel = 2;
 8001ae4:	2302      	movs	r3, #2
 8001ae6:	60fb      	str	r3, [r7, #12]
 8001ae8:	e01d      	b.n	8001b26 <DFSDM_GetChannelFromInstance+0x6e>
  }
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
    defined(STM32L496xx) || defined(STM32L4A6xx) || \
    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
  else if (Instance == DFSDM1_Channel4)
 8001aea:	687b      	ldr	r3, [r7, #4]
 8001aec:	4a14      	ldr	r2, [pc, #80]	@ (8001b40 <DFSDM_GetChannelFromInstance+0x88>)
 8001aee:	4293      	cmp	r3, r2
 8001af0:	d102      	bne.n	8001af8 <DFSDM_GetChannelFromInstance+0x40>
  {
    channel = 4;
 8001af2:	2304      	movs	r3, #4
 8001af4:	60fb      	str	r3, [r7, #12]
 8001af6:	e016      	b.n	8001b26 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel5)
 8001af8:	687b      	ldr	r3, [r7, #4]
 8001afa:	4a12      	ldr	r2, [pc, #72]	@ (8001b44 <DFSDM_GetChannelFromInstance+0x8c>)
 8001afc:	4293      	cmp	r3, r2
 8001afe:	d102      	bne.n	8001b06 <DFSDM_GetChannelFromInstance+0x4e>
  {
    channel = 5;
 8001b00:	2305      	movs	r3, #5
 8001b02:	60fb      	str	r3, [r7, #12]
 8001b04:	e00f      	b.n	8001b26 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel6)
 8001b06:	687b      	ldr	r3, [r7, #4]
 8001b08:	4a0f      	ldr	r2, [pc, #60]	@ (8001b48 <DFSDM_GetChannelFromInstance+0x90>)
 8001b0a:	4293      	cmp	r3, r2
 8001b0c:	d102      	bne.n	8001b14 <DFSDM_GetChannelFromInstance+0x5c>
  {
    channel = 6;
 8001b0e:	2306      	movs	r3, #6
 8001b10:	60fb      	str	r3, [r7, #12]
 8001b12:	e008      	b.n	8001b26 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel7)
 8001b14:	687b      	ldr	r3, [r7, #4]
 8001b16:	4a0d      	ldr	r2, [pc, #52]	@ (8001b4c <DFSDM_GetChannelFromInstance+0x94>)
 8001b18:	4293      	cmp	r3, r2
 8001b1a:	d102      	bne.n	8001b22 <DFSDM_GetChannelFromInstance+0x6a>
  {
    channel = 7;
 8001b1c:	2307      	movs	r3, #7
 8001b1e:	60fb      	str	r3, [r7, #12]
 8001b20:	e001      	b.n	8001b26 <DFSDM_GetChannelFromInstance+0x6e>
  }
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
  else /* DFSDM1_Channel3 */
  {
    channel = 3;
 8001b22:	2303      	movs	r3, #3
 8001b24:	60fb      	str	r3, [r7, #12]
  }

  return channel;
 8001b26:	68fb      	ldr	r3, [r7, #12]
}
 8001b28:	4618      	mov	r0, r3
 8001b2a:	3714      	adds	r7, #20
 8001b2c:	46bd      	mov	sp, r7
 8001b2e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001b32:	4770      	bx	lr
 8001b34:	40016000 	.word	0x40016000
 8001b38:	40016020 	.word	0x40016020
 8001b3c:	40016040 	.word	0x40016040
 8001b40:	40016080 	.word	0x40016080
 8001b44:	400160a0 	.word	0x400160a0
 8001b48:	400160c0 	.word	0x400160c0
 8001b4c:	400160e0 	.word	0x400160e0

08001b50 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8001b50:	b480      	push	{r7}
 8001b52:	b087      	sub	sp, #28
 8001b54:	af00      	add	r7, sp, #0
 8001b56:	6078      	str	r0, [r7, #4]
 8001b58:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00u;
 8001b5a:	2300      	movs	r3, #0
 8001b5c:	617b      	str	r3, [r7, #20]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8001b5e:	e17f      	b.n	8001e60 <HAL_GPIO_Init+0x310>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1uL << position);
 8001b60:	683b      	ldr	r3, [r7, #0]
 8001b62:	681a      	ldr	r2, [r3, #0]
 8001b64:	2101      	movs	r1, #1
 8001b66:	697b      	ldr	r3, [r7, #20]
 8001b68:	fa01 f303 	lsl.w	r3, r1, r3
 8001b6c:	4013      	ands	r3, r2
 8001b6e:	60fb      	str	r3, [r7, #12]

    if (iocurrent != 0x00u)
 8001b70:	68fb      	ldr	r3, [r7, #12]
 8001b72:	2b00      	cmp	r3, #0
 8001b74:	f000 8171 	beq.w	8001e5a <HAL_GPIO_Init+0x30a>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 8001b78:	683b      	ldr	r3, [r7, #0]
 8001b7a:	685b      	ldr	r3, [r3, #4]
 8001b7c:	f003 0303 	and.w	r3, r3, #3
 8001b80:	2b01      	cmp	r3, #1
 8001b82:	d005      	beq.n	8001b90 <HAL_GPIO_Init+0x40>
 8001b84:	683b      	ldr	r3, [r7, #0]
 8001b86:	685b      	ldr	r3, [r3, #4]
 8001b88:	f003 0303 	and.w	r3, r3, #3
 8001b8c:	2b02      	cmp	r3, #2
 8001b8e:	d130      	bne.n	8001bf2 <HAL_GPIO_Init+0xa2>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));

        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 8001b90:	687b      	ldr	r3, [r7, #4]
 8001b92:	689b      	ldr	r3, [r3, #8]
 8001b94:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
 8001b96:	697b      	ldr	r3, [r7, #20]
 8001b98:	005b      	lsls	r3, r3, #1
 8001b9a:	2203      	movs	r2, #3
 8001b9c:	fa02 f303 	lsl.w	r3, r2, r3
 8001ba0:	43db      	mvns	r3, r3
 8001ba2:	693a      	ldr	r2, [r7, #16]
 8001ba4:	4013      	ands	r3, r2
 8001ba6:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_Init->Speed << (position * 2u));
 8001ba8:	683b      	ldr	r3, [r7, #0]
 8001baa:	68da      	ldr	r2, [r3, #12]
 8001bac:	697b      	ldr	r3, [r7, #20]
 8001bae:	005b      	lsls	r3, r3, #1
 8001bb0:	fa02 f303 	lsl.w	r3, r2, r3
 8001bb4:	693a      	ldr	r2, [r7, #16]
 8001bb6:	4313      	orrs	r3, r2
 8001bb8:	613b      	str	r3, [r7, #16]
        GPIOx->OSPEEDR = temp;
 8001bba:	687b      	ldr	r3, [r7, #4]
 8001bbc:	693a      	ldr	r2, [r7, #16]
 8001bbe:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 8001bc0:	687b      	ldr	r3, [r7, #4]
 8001bc2:	685b      	ldr	r3, [r3, #4]
 8001bc4:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 8001bc6:	2201      	movs	r2, #1
 8001bc8:	697b      	ldr	r3, [r7, #20]
 8001bca:	fa02 f303 	lsl.w	r3, r2, r3
 8001bce:	43db      	mvns	r3, r3
 8001bd0:	693a      	ldr	r2, [r7, #16]
 8001bd2:	4013      	ands	r3, r2
 8001bd4:	613b      	str	r3, [r7, #16]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 8001bd6:	683b      	ldr	r3, [r7, #0]
 8001bd8:	685b      	ldr	r3, [r3, #4]
 8001bda:	091b      	lsrs	r3, r3, #4
 8001bdc:	f003 0201 	and.w	r2, r3, #1
 8001be0:	697b      	ldr	r3, [r7, #20]
 8001be2:	fa02 f303 	lsl.w	r3, r2, r3
 8001be6:	693a      	ldr	r2, [r7, #16]
 8001be8:	4313      	orrs	r3, r2
 8001bea:	613b      	str	r3, [r7, #16]
        GPIOx->OTYPER = temp;
 8001bec:	687b      	ldr	r3, [r7, #4]
 8001bee:	693a      	ldr	r2, [r7, #16]
 8001bf0:	605a      	str	r2, [r3, #4]
      }

#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)

      /* In case of Analog mode, check if ADC control mode is selected */
      if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
 8001bf2:	683b      	ldr	r3, [r7, #0]
 8001bf4:	685b      	ldr	r3, [r3, #4]
 8001bf6:	f003 0303 	and.w	r3, r3, #3
 8001bfa:	2b03      	cmp	r3, #3
 8001bfc:	d118      	bne.n	8001c30 <HAL_GPIO_Init+0xe0>
      {
        /* Configure the IO Output Type */
        temp = GPIOx->ASCR;
 8001bfe:	687b      	ldr	r3, [r7, #4]
 8001c00:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001c02:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_ASCR_ASC0 << position) ;
 8001c04:	2201      	movs	r2, #1
 8001c06:	697b      	ldr	r3, [r7, #20]
 8001c08:	fa02 f303 	lsl.w	r3, r2, r3
 8001c0c:	43db      	mvns	r3, r3
 8001c0e:	693a      	ldr	r2, [r7, #16]
 8001c10:	4013      	ands	r3, r2
 8001c12:	613b      	str	r3, [r7, #16]
        temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
 8001c14:	683b      	ldr	r3, [r7, #0]
 8001c16:	685b      	ldr	r3, [r3, #4]
 8001c18:	08db      	lsrs	r3, r3, #3
 8001c1a:	f003 0201 	and.w	r2, r3, #1
 8001c1e:	697b      	ldr	r3, [r7, #20]
 8001c20:	fa02 f303 	lsl.w	r3, r2, r3
 8001c24:	693a      	ldr	r2, [r7, #16]
 8001c26:	4313      	orrs	r3, r2
 8001c28:	613b      	str	r3, [r7, #16]
        GPIOx->ASCR = temp;
 8001c2a:	687b      	ldr	r3, [r7, #4]
 8001c2c:	693a      	ldr	r2, [r7, #16]
 8001c2e:	62da      	str	r2, [r3, #44]	@ 0x2c
      }

#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */

      /* Activate the Pull-up or Pull down resistor for the current IO */
      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8001c30:	683b      	ldr	r3, [r7, #0]
 8001c32:	685b      	ldr	r3, [r3, #4]
 8001c34:	f003 0303 	and.w	r3, r3, #3
 8001c38:	2b03      	cmp	r3, #3
 8001c3a:	d017      	beq.n	8001c6c <HAL_GPIO_Init+0x11c>
      {
        /* Check the Pull parameter */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

        temp = GPIOx->PUPDR;
 8001c3c:	687b      	ldr	r3, [r7, #4]
 8001c3e:	68db      	ldr	r3, [r3, #12]
 8001c40:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 8001c42:	697b      	ldr	r3, [r7, #20]
 8001c44:	005b      	lsls	r3, r3, #1
 8001c46:	2203      	movs	r2, #3
 8001c48:	fa02 f303 	lsl.w	r3, r2, r3
 8001c4c:	43db      	mvns	r3, r3
 8001c4e:	693a      	ldr	r2, [r7, #16]
 8001c50:	4013      	ands	r3, r2
 8001c52:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 8001c54:	683b      	ldr	r3, [r7, #0]
 8001c56:	689a      	ldr	r2, [r3, #8]
 8001c58:	697b      	ldr	r3, [r7, #20]
 8001c5a:	005b      	lsls	r3, r3, #1
 8001c5c:	fa02 f303 	lsl.w	r3, r2, r3
 8001c60:	693a      	ldr	r2, [r7, #16]
 8001c62:	4313      	orrs	r3, r2
 8001c64:	613b      	str	r3, [r7, #16]
        GPIOx->PUPDR = temp;
 8001c66:	687b      	ldr	r3, [r7, #4]
 8001c68:	693a      	ldr	r2, [r7, #16]
 8001c6a:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8001c6c:	683b      	ldr	r3, [r7, #0]
 8001c6e:	685b      	ldr	r3, [r3, #4]
 8001c70:	f003 0303 	and.w	r3, r3, #3
 8001c74:	2b02      	cmp	r3, #2
 8001c76:	d123      	bne.n	8001cc0 <HAL_GPIO_Init+0x170>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3u];
 8001c78:	697b      	ldr	r3, [r7, #20]
 8001c7a:	08da      	lsrs	r2, r3, #3
 8001c7c:	687b      	ldr	r3, [r7, #4]
 8001c7e:	3208      	adds	r2, #8
 8001c80:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 8001c84:	613b      	str	r3, [r7, #16]
        temp &= ~(0xFu << ((position & 0x07u) * 4u));
 8001c86:	697b      	ldr	r3, [r7, #20]
 8001c88:	f003 0307 	and.w	r3, r3, #7
 8001c8c:	009b      	lsls	r3, r3, #2
 8001c8e:	220f      	movs	r2, #15
 8001c90:	fa02 f303 	lsl.w	r3, r2, r3
 8001c94:	43db      	mvns	r3, r3
 8001c96:	693a      	ldr	r2, [r7, #16]
 8001c98:	4013      	ands	r3, r2
 8001c9a:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
 8001c9c:	683b      	ldr	r3, [r7, #0]
 8001c9e:	691a      	ldr	r2, [r3, #16]
 8001ca0:	697b      	ldr	r3, [r7, #20]
 8001ca2:	f003 0307 	and.w	r3, r3, #7
 8001ca6:	009b      	lsls	r3, r3, #2
 8001ca8:	fa02 f303 	lsl.w	r3, r2, r3
 8001cac:	693a      	ldr	r2, [r7, #16]
 8001cae:	4313      	orrs	r3, r2
 8001cb0:	613b      	str	r3, [r7, #16]
        GPIOx->AFR[position >> 3u] = temp;
 8001cb2:	697b      	ldr	r3, [r7, #20]
 8001cb4:	08da      	lsrs	r2, r3, #3
 8001cb6:	687b      	ldr	r3, [r7, #4]
 8001cb8:	3208      	adds	r2, #8
 8001cba:	6939      	ldr	r1, [r7, #16]
 8001cbc:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 8001cc0:	687b      	ldr	r3, [r7, #4]
 8001cc2:	681b      	ldr	r3, [r3, #0]
 8001cc4:	613b      	str	r3, [r7, #16]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
 8001cc6:	697b      	ldr	r3, [r7, #20]
 8001cc8:	005b      	lsls	r3, r3, #1
 8001cca:	2203      	movs	r2, #3
 8001ccc:	fa02 f303 	lsl.w	r3, r2, r3
 8001cd0:	43db      	mvns	r3, r3
 8001cd2:	693a      	ldr	r2, [r7, #16]
 8001cd4:	4013      	ands	r3, r2
 8001cd6:	613b      	str	r3, [r7, #16]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
 8001cd8:	683b      	ldr	r3, [r7, #0]
 8001cda:	685b      	ldr	r3, [r3, #4]
 8001cdc:	f003 0203 	and.w	r2, r3, #3
 8001ce0:	697b      	ldr	r3, [r7, #20]
 8001ce2:	005b      	lsls	r3, r3, #1
 8001ce4:	fa02 f303 	lsl.w	r3, r2, r3
 8001ce8:	693a      	ldr	r2, [r7, #16]
 8001cea:	4313      	orrs	r3, r2
 8001cec:	613b      	str	r3, [r7, #16]
      GPIOx->MODER = temp;
 8001cee:	687b      	ldr	r3, [r7, #4]
 8001cf0:	693a      	ldr	r2, [r7, #16]
 8001cf2:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 8001cf4:	683b      	ldr	r3, [r7, #0]
 8001cf6:	685b      	ldr	r3, [r3, #4]
 8001cf8:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 8001cfc:	2b00      	cmp	r3, #0
 8001cfe:	f000 80ac 	beq.w	8001e5a <HAL_GPIO_Init+0x30a>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8001d02:	4b5f      	ldr	r3, [pc, #380]	@ (8001e80 <HAL_GPIO_Init+0x330>)
 8001d04:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001d06:	4a5e      	ldr	r2, [pc, #376]	@ (8001e80 <HAL_GPIO_Init+0x330>)
 8001d08:	f043 0301 	orr.w	r3, r3, #1
 8001d0c:	6613      	str	r3, [r2, #96]	@ 0x60
 8001d0e:	4b5c      	ldr	r3, [pc, #368]	@ (8001e80 <HAL_GPIO_Init+0x330>)
 8001d10:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001d12:	f003 0301 	and.w	r3, r3, #1
 8001d16:	60bb      	str	r3, [r7, #8]
 8001d18:	68bb      	ldr	r3, [r7, #8]

        temp = SYSCFG->EXTICR[position >> 2u];
 8001d1a:	4a5a      	ldr	r2, [pc, #360]	@ (8001e84 <HAL_GPIO_Init+0x334>)
 8001d1c:	697b      	ldr	r3, [r7, #20]
 8001d1e:	089b      	lsrs	r3, r3, #2
 8001d20:	3302      	adds	r3, #2
 8001d22:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8001d26:	613b      	str	r3, [r7, #16]
        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
 8001d28:	697b      	ldr	r3, [r7, #20]
 8001d2a:	f003 0303 	and.w	r3, r3, #3
 8001d2e:	009b      	lsls	r3, r3, #2
 8001d30:	220f      	movs	r2, #15
 8001d32:	fa02 f303 	lsl.w	r3, r2, r3
 8001d36:	43db      	mvns	r3, r3
 8001d38:	693a      	ldr	r2, [r7, #16]
 8001d3a:	4013      	ands	r3, r2
 8001d3c:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
 8001d3e:	687b      	ldr	r3, [r7, #4]
 8001d40:	f1b3 4f90 	cmp.w	r3, #1207959552	@ 0x48000000
 8001d44:	d025      	beq.n	8001d92 <HAL_GPIO_Init+0x242>
 8001d46:	687b      	ldr	r3, [r7, #4]
 8001d48:	4a4f      	ldr	r2, [pc, #316]	@ (8001e88 <HAL_GPIO_Init+0x338>)
 8001d4a:	4293      	cmp	r3, r2
 8001d4c:	d01f      	beq.n	8001d8e <HAL_GPIO_Init+0x23e>
 8001d4e:	687b      	ldr	r3, [r7, #4]
 8001d50:	4a4e      	ldr	r2, [pc, #312]	@ (8001e8c <HAL_GPIO_Init+0x33c>)
 8001d52:	4293      	cmp	r3, r2
 8001d54:	d019      	beq.n	8001d8a <HAL_GPIO_Init+0x23a>
 8001d56:	687b      	ldr	r3, [r7, #4]
 8001d58:	4a4d      	ldr	r2, [pc, #308]	@ (8001e90 <HAL_GPIO_Init+0x340>)
 8001d5a:	4293      	cmp	r3, r2
 8001d5c:	d013      	beq.n	8001d86 <HAL_GPIO_Init+0x236>
 8001d5e:	687b      	ldr	r3, [r7, #4]
 8001d60:	4a4c      	ldr	r2, [pc, #304]	@ (8001e94 <HAL_GPIO_Init+0x344>)
 8001d62:	4293      	cmp	r3, r2
 8001d64:	d00d      	beq.n	8001d82 <HAL_GPIO_Init+0x232>
 8001d66:	687b      	ldr	r3, [r7, #4]
 8001d68:	4a4b      	ldr	r2, [pc, #300]	@ (8001e98 <HAL_GPIO_Init+0x348>)
 8001d6a:	4293      	cmp	r3, r2
 8001d6c:	d007      	beq.n	8001d7e <HAL_GPIO_Init+0x22e>
 8001d6e:	687b      	ldr	r3, [r7, #4]
 8001d70:	4a4a      	ldr	r2, [pc, #296]	@ (8001e9c <HAL_GPIO_Init+0x34c>)
 8001d72:	4293      	cmp	r3, r2
 8001d74:	d101      	bne.n	8001d7a <HAL_GPIO_Init+0x22a>
 8001d76:	2306      	movs	r3, #6
 8001d78:	e00c      	b.n	8001d94 <HAL_GPIO_Init+0x244>
 8001d7a:	2307      	movs	r3, #7
 8001d7c:	e00a      	b.n	8001d94 <HAL_GPIO_Init+0x244>
 8001d7e:	2305      	movs	r3, #5
 8001d80:	e008      	b.n	8001d94 <HAL_GPIO_Init+0x244>
 8001d82:	2304      	movs	r3, #4
 8001d84:	e006      	b.n	8001d94 <HAL_GPIO_Init+0x244>
 8001d86:	2303      	movs	r3, #3
 8001d88:	e004      	b.n	8001d94 <HAL_GPIO_Init+0x244>
 8001d8a:	2302      	movs	r3, #2
 8001d8c:	e002      	b.n	8001d94 <HAL_GPIO_Init+0x244>
 8001d8e:	2301      	movs	r3, #1
 8001d90:	e000      	b.n	8001d94 <HAL_GPIO_Init+0x244>
 8001d92:	2300      	movs	r3, #0
 8001d94:	697a      	ldr	r2, [r7, #20]
 8001d96:	f002 0203 	and.w	r2, r2, #3
 8001d9a:	0092      	lsls	r2, r2, #2
 8001d9c:	4093      	lsls	r3, r2
 8001d9e:	693a      	ldr	r2, [r7, #16]
 8001da0:	4313      	orrs	r3, r2
 8001da2:	613b      	str	r3, [r7, #16]
        SYSCFG->EXTICR[position >> 2u] = temp;
 8001da4:	4937      	ldr	r1, [pc, #220]	@ (8001e84 <HAL_GPIO_Init+0x334>)
 8001da6:	697b      	ldr	r3, [r7, #20]
 8001da8:	089b      	lsrs	r3, r3, #2
 8001daa:	3302      	adds	r3, #2
 8001dac:	693a      	ldr	r2, [r7, #16]
 8001dae:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 8001db2:	4b3b      	ldr	r3, [pc, #236]	@ (8001ea0 <HAL_GPIO_Init+0x350>)
 8001db4:	689b      	ldr	r3, [r3, #8]
 8001db6:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001db8:	68fb      	ldr	r3, [r7, #12]
 8001dba:	43db      	mvns	r3, r3
 8001dbc:	693a      	ldr	r2, [r7, #16]
 8001dbe:	4013      	ands	r3, r2
 8001dc0:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
 8001dc2:	683b      	ldr	r3, [r7, #0]
 8001dc4:	685b      	ldr	r3, [r3, #4]
 8001dc6:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 8001dca:	2b00      	cmp	r3, #0
 8001dcc:	d003      	beq.n	8001dd6 <HAL_GPIO_Init+0x286>
        {
          temp |= iocurrent;
 8001dce:	693a      	ldr	r2, [r7, #16]
 8001dd0:	68fb      	ldr	r3, [r7, #12]
 8001dd2:	4313      	orrs	r3, r2
 8001dd4:	613b      	str	r3, [r7, #16]
        }
        EXTI->RTSR1 = temp;
 8001dd6:	4a32      	ldr	r2, [pc, #200]	@ (8001ea0 <HAL_GPIO_Init+0x350>)
 8001dd8:	693b      	ldr	r3, [r7, #16]
 8001dda:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR1;
 8001ddc:	4b30      	ldr	r3, [pc, #192]	@ (8001ea0 <HAL_GPIO_Init+0x350>)
 8001dde:	68db      	ldr	r3, [r3, #12]
 8001de0:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001de2:	68fb      	ldr	r3, [r7, #12]
 8001de4:	43db      	mvns	r3, r3
 8001de6:	693a      	ldr	r2, [r7, #16]
 8001de8:	4013      	ands	r3, r2
 8001dea:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
 8001dec:	683b      	ldr	r3, [r7, #0]
 8001dee:	685b      	ldr	r3, [r3, #4]
 8001df0:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
 8001df4:	2b00      	cmp	r3, #0
 8001df6:	d003      	beq.n	8001e00 <HAL_GPIO_Init+0x2b0>
        {
          temp |= iocurrent;
 8001df8:	693a      	ldr	r2, [r7, #16]
 8001dfa:	68fb      	ldr	r3, [r7, #12]
 8001dfc:	4313      	orrs	r3, r2
 8001dfe:	613b      	str	r3, [r7, #16]
        }
        EXTI->FTSR1 = temp;
 8001e00:	4a27      	ldr	r2, [pc, #156]	@ (8001ea0 <HAL_GPIO_Init+0x350>)
 8001e02:	693b      	ldr	r3, [r7, #16]
 8001e04:	60d3      	str	r3, [r2, #12]

        /* Clear EXTI line configuration */
        temp = EXTI->EMR1;
 8001e06:	4b26      	ldr	r3, [pc, #152]	@ (8001ea0 <HAL_GPIO_Init+0x350>)
 8001e08:	685b      	ldr	r3, [r3, #4]
 8001e0a:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001e0c:	68fb      	ldr	r3, [r7, #12]
 8001e0e:	43db      	mvns	r3, r3
 8001e10:	693a      	ldr	r2, [r7, #16]
 8001e12:	4013      	ands	r3, r2
 8001e14:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
 8001e16:	683b      	ldr	r3, [r7, #0]
 8001e18:	685b      	ldr	r3, [r3, #4]
 8001e1a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8001e1e:	2b00      	cmp	r3, #0
 8001e20:	d003      	beq.n	8001e2a <HAL_GPIO_Init+0x2da>
        {
          temp |= iocurrent;
 8001e22:	693a      	ldr	r2, [r7, #16]
 8001e24:	68fb      	ldr	r3, [r7, #12]
 8001e26:	4313      	orrs	r3, r2
 8001e28:	613b      	str	r3, [r7, #16]
        }
        EXTI->EMR1 = temp;
 8001e2a:	4a1d      	ldr	r2, [pc, #116]	@ (8001ea0 <HAL_GPIO_Init+0x350>)
 8001e2c:	693b      	ldr	r3, [r7, #16]
 8001e2e:	6053      	str	r3, [r2, #4]

        temp = EXTI->IMR1;
 8001e30:	4b1b      	ldr	r3, [pc, #108]	@ (8001ea0 <HAL_GPIO_Init+0x350>)
 8001e32:	681b      	ldr	r3, [r3, #0]
 8001e34:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001e36:	68fb      	ldr	r3, [r7, #12]
 8001e38:	43db      	mvns	r3, r3
 8001e3a:	693a      	ldr	r2, [r7, #16]
 8001e3c:	4013      	ands	r3, r2
 8001e3e:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
 8001e40:	683b      	ldr	r3, [r7, #0]
 8001e42:	685b      	ldr	r3, [r3, #4]
 8001e44:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8001e48:	2b00      	cmp	r3, #0
 8001e4a:	d003      	beq.n	8001e54 <HAL_GPIO_Init+0x304>
        {
          temp |= iocurrent;
 8001e4c:	693a      	ldr	r2, [r7, #16]
 8001e4e:	68fb      	ldr	r3, [r7, #12]
 8001e50:	4313      	orrs	r3, r2
 8001e52:	613b      	str	r3, [r7, #16]
        }
        EXTI->IMR1 = temp;
 8001e54:	4a12      	ldr	r2, [pc, #72]	@ (8001ea0 <HAL_GPIO_Init+0x350>)
 8001e56:	693b      	ldr	r3, [r7, #16]
 8001e58:	6013      	str	r3, [r2, #0]
      }
    }

    position++;
 8001e5a:	697b      	ldr	r3, [r7, #20]
 8001e5c:	3301      	adds	r3, #1
 8001e5e:	617b      	str	r3, [r7, #20]
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8001e60:	683b      	ldr	r3, [r7, #0]
 8001e62:	681a      	ldr	r2, [r3, #0]
 8001e64:	697b      	ldr	r3, [r7, #20]
 8001e66:	fa22 f303 	lsr.w	r3, r2, r3
 8001e6a:	2b00      	cmp	r3, #0
 8001e6c:	f47f ae78 	bne.w	8001b60 <HAL_GPIO_Init+0x10>
  }
}
 8001e70:	bf00      	nop
 8001e72:	bf00      	nop
 8001e74:	371c      	adds	r7, #28
 8001e76:	46bd      	mov	sp, r7
 8001e78:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001e7c:	4770      	bx	lr
 8001e7e:	bf00      	nop
 8001e80:	40021000 	.word	0x40021000
 8001e84:	40010000 	.word	0x40010000
 8001e88:	48000400 	.word	0x48000400
 8001e8c:	48000800 	.word	0x48000800
 8001e90:	48000c00 	.word	0x48000c00
 8001e94:	48001000 	.word	0x48001000
 8001e98:	48001400 	.word	0x48001400
 8001e9c:	48001800 	.word	0x48001800
 8001ea0:	40010400 	.word	0x40010400

08001ea4 <HAL_GPIO_ReadPin>:
  * @param  GPIO_Pin specifies the port bit to read.
  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
  * @retval The input port pin value.
  */
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
 8001ea4:	b480      	push	{r7}
 8001ea6:	b085      	sub	sp, #20
 8001ea8:	af00      	add	r7, sp, #0
 8001eaa:	6078      	str	r0, [r7, #4]
 8001eac:	460b      	mov	r3, r1
 8001eae:	807b      	strh	r3, [r7, #2]
  GPIO_PinState bitstatus;

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
 8001eb0:	687b      	ldr	r3, [r7, #4]
 8001eb2:	691a      	ldr	r2, [r3, #16]
 8001eb4:	887b      	ldrh	r3, [r7, #2]
 8001eb6:	4013      	ands	r3, r2
 8001eb8:	2b00      	cmp	r3, #0
 8001eba:	d002      	beq.n	8001ec2 <HAL_GPIO_ReadPin+0x1e>
  {
    bitstatus = GPIO_PIN_SET;
 8001ebc:	2301      	movs	r3, #1
 8001ebe:	73fb      	strb	r3, [r7, #15]
 8001ec0:	e001      	b.n	8001ec6 <HAL_GPIO_ReadPin+0x22>
  }
  else
  {
    bitstatus = GPIO_PIN_RESET;
 8001ec2:	2300      	movs	r3, #0
 8001ec4:	73fb      	strb	r3, [r7, #15]
  }
  return bitstatus;
 8001ec6:	7bfb      	ldrb	r3, [r7, #15]
}
 8001ec8:	4618      	mov	r0, r3
 8001eca:	3714      	adds	r7, #20
 8001ecc:	46bd      	mov	sp, r7
 8001ece:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001ed2:	4770      	bx	lr

08001ed4 <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 8001ed4:	b480      	push	{r7}
 8001ed6:	b083      	sub	sp, #12
 8001ed8:	af00      	add	r7, sp, #0
 8001eda:	6078      	str	r0, [r7, #4]
 8001edc:	460b      	mov	r3, r1
 8001ede:	807b      	strh	r3, [r7, #2]
 8001ee0:	4613      	mov	r3, r2
 8001ee2:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if(PinState != GPIO_PIN_RESET)
 8001ee4:	787b      	ldrb	r3, [r7, #1]
 8001ee6:	2b00      	cmp	r3, #0
 8001ee8:	d003      	beq.n	8001ef2 <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8001eea:	887a      	ldrh	r2, [r7, #2]
 8001eec:	687b      	ldr	r3, [r7, #4]
 8001eee:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BRR = (uint32_t)GPIO_Pin;
  }
}
 8001ef0:	e002      	b.n	8001ef8 <HAL_GPIO_WritePin+0x24>
    GPIOx->BRR = (uint32_t)GPIO_Pin;
 8001ef2:	887a      	ldrh	r2, [r7, #2]
 8001ef4:	687b      	ldr	r3, [r7, #4]
 8001ef6:	629a      	str	r2, [r3, #40]	@ 0x28
}
 8001ef8:	bf00      	nop
 8001efa:	370c      	adds	r7, #12
 8001efc:	46bd      	mov	sp, r7
 8001efe:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001f02:	4770      	bx	lr

08001f04 <HAL_GPIO_EXTI_IRQHandler>:
  * @brief  Handle EXTI interrupt request.
  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
  * @retval None
  */
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
 8001f04:	b580      	push	{r7, lr}
 8001f06:	b082      	sub	sp, #8
 8001f08:	af00      	add	r7, sp, #0
 8001f0a:	4603      	mov	r3, r0
 8001f0c:	80fb      	strh	r3, [r7, #6]
  /* EXTI line interrupt detected */
  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
 8001f0e:	4b08      	ldr	r3, [pc, #32]	@ (8001f30 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
 8001f10:	695a      	ldr	r2, [r3, #20]
 8001f12:	88fb      	ldrh	r3, [r7, #6]
 8001f14:	4013      	ands	r3, r2
 8001f16:	2b00      	cmp	r3, #0
 8001f18:	d006      	beq.n	8001f28 <HAL_GPIO_EXTI_IRQHandler+0x24>
  {
    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
 8001f1a:	4a05      	ldr	r2, [pc, #20]	@ (8001f30 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
 8001f1c:	88fb      	ldrh	r3, [r7, #6]
 8001f1e:	6153      	str	r3, [r2, #20]
    HAL_GPIO_EXTI_Callback(GPIO_Pin);
 8001f20:	88fb      	ldrh	r3, [r7, #6]
 8001f22:	4618      	mov	r0, r3
 8001f24:	f000 f806 	bl	8001f34 <HAL_GPIO_EXTI_Callback>
  }
}
 8001f28:	bf00      	nop
 8001f2a:	3708      	adds	r7, #8
 8001f2c:	46bd      	mov	sp, r7
 8001f2e:	bd80      	pop	{r7, pc}
 8001f30:	40010400 	.word	0x40010400

08001f34 <HAL_GPIO_EXTI_Callback>:
  * @brief  EXTI line detection callback.
  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
  * @retval None
  */
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
 8001f34:	b480      	push	{r7}
 8001f36:	b083      	sub	sp, #12
 8001f38:	af00      	add	r7, sp, #0
 8001f3a:	4603      	mov	r3, r0
 8001f3c:	80fb      	strh	r3, [r7, #6]
  UNUSED(GPIO_Pin);

  /* NOTE: This function should not be modified, when the callback is needed,
           the HAL_GPIO_EXTI_Callback could be implemented in the user file
   */
}
 8001f3e:	bf00      	nop
 8001f40:	370c      	adds	r7, #12
 8001f42:	46bd      	mov	sp, r7
 8001f44:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001f48:	4770      	bx	lr

08001f4a <HAL_I2C_Init>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *                the configuration information for the specified I2C.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
 8001f4a:	b580      	push	{r7, lr}
 8001f4c:	b082      	sub	sp, #8
 8001f4e:	af00      	add	r7, sp, #0
 8001f50:	6078      	str	r0, [r7, #4]
  /* Check the I2C handle allocation */
  if (hi2c == NULL)
 8001f52:	687b      	ldr	r3, [r7, #4]
 8001f54:	2b00      	cmp	r3, #0
 8001f56:	d101      	bne.n	8001f5c <HAL_I2C_Init+0x12>
  {
    return HAL_ERROR;
 8001f58:	2301      	movs	r3, #1
 8001f5a:	e08d      	b.n	8002078 <HAL_I2C_Init+0x12e>
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));

  if (hi2c->State == HAL_I2C_STATE_RESET)
 8001f5c:	687b      	ldr	r3, [r7, #4]
 8001f5e:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 8001f62:	b2db      	uxtb	r3, r3
 8001f64:	2b00      	cmp	r3, #0
 8001f66:	d106      	bne.n	8001f76 <HAL_I2C_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    hi2c->Lock = HAL_UNLOCKED;
 8001f68:	687b      	ldr	r3, [r7, #4]
 8001f6a:	2200      	movs	r2, #0
 8001f6c:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
    hi2c->MspInitCallback(hi2c);
#else
    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
    HAL_I2C_MspInit(hi2c);
 8001f70:	6878      	ldr	r0, [r7, #4]
 8001f72:	f7ff f885 	bl	8001080 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
  }

  hi2c->State = HAL_I2C_STATE_BUSY;
 8001f76:	687b      	ldr	r3, [r7, #4]
 8001f78:	2224      	movs	r2, #36	@ 0x24
 8001f7a:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

  /* Disable the selected I2C peripheral */
  __HAL_I2C_DISABLE(hi2c);
 8001f7e:	687b      	ldr	r3, [r7, #4]
 8001f80:	681b      	ldr	r3, [r3, #0]
 8001f82:	681a      	ldr	r2, [r3, #0]
 8001f84:	687b      	ldr	r3, [r7, #4]
 8001f86:	681b      	ldr	r3, [r3, #0]
 8001f88:	f022 0201 	bic.w	r2, r2, #1
 8001f8c:	601a      	str	r2, [r3, #0]

  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
  /* Configure I2Cx: Frequency range */
  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
 8001f8e:	687b      	ldr	r3, [r7, #4]
 8001f90:	685a      	ldr	r2, [r3, #4]
 8001f92:	687b      	ldr	r3, [r7, #4]
 8001f94:	681b      	ldr	r3, [r3, #0]
 8001f96:	f022 6270 	bic.w	r2, r2, #251658240	@ 0xf000000
 8001f9a:	611a      	str	r2, [r3, #16]

  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
  /* Disable Own Address1 before set the Own Address1 configuration */
  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
 8001f9c:	687b      	ldr	r3, [r7, #4]
 8001f9e:	681b      	ldr	r3, [r3, #0]
 8001fa0:	689a      	ldr	r2, [r3, #8]
 8001fa2:	687b      	ldr	r3, [r7, #4]
 8001fa4:	681b      	ldr	r3, [r3, #0]
 8001fa6:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
 8001faa:	609a      	str	r2, [r3, #8]

  /* Configure I2Cx: Own Address1 and ack own address1 mode */
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
 8001fac:	687b      	ldr	r3, [r7, #4]
 8001fae:	68db      	ldr	r3, [r3, #12]
 8001fb0:	2b01      	cmp	r3, #1
 8001fb2:	d107      	bne.n	8001fc4 <HAL_I2C_Init+0x7a>
  {
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
 8001fb4:	687b      	ldr	r3, [r7, #4]
 8001fb6:	689a      	ldr	r2, [r3, #8]
 8001fb8:	687b      	ldr	r3, [r7, #4]
 8001fba:	681b      	ldr	r3, [r3, #0]
 8001fbc:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
 8001fc0:	609a      	str	r2, [r3, #8]
 8001fc2:	e006      	b.n	8001fd2 <HAL_I2C_Init+0x88>
  }
  else /* I2C_ADDRESSINGMODE_10BIT */
  {
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
 8001fc4:	687b      	ldr	r3, [r7, #4]
 8001fc6:	689a      	ldr	r2, [r3, #8]
 8001fc8:	687b      	ldr	r3, [r7, #4]
 8001fca:	681b      	ldr	r3, [r3, #0]
 8001fcc:	f442 4204 	orr.w	r2, r2, #33792	@ 0x8400
 8001fd0:	609a      	str	r2, [r3, #8]
  }

  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
  /* Configure I2Cx: Addressing Master mode */
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
 8001fd2:	687b      	ldr	r3, [r7, #4]
 8001fd4:	68db      	ldr	r3, [r3, #12]
 8001fd6:	2b02      	cmp	r3, #2
 8001fd8:	d108      	bne.n	8001fec <HAL_I2C_Init+0xa2>
  {
    SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
 8001fda:	687b      	ldr	r3, [r7, #4]
 8001fdc:	681b      	ldr	r3, [r3, #0]
 8001fde:	685a      	ldr	r2, [r3, #4]
 8001fe0:	687b      	ldr	r3, [r7, #4]
 8001fe2:	681b      	ldr	r3, [r3, #0]
 8001fe4:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
 8001fe8:	605a      	str	r2, [r3, #4]
 8001fea:	e007      	b.n	8001ffc <HAL_I2C_Init+0xb2>
  }
  else
  {
    /* Clear the I2C ADD10 bit */
    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
 8001fec:	687b      	ldr	r3, [r7, #4]
 8001fee:	681b      	ldr	r3, [r3, #0]
 8001ff0:	685a      	ldr	r2, [r3, #4]
 8001ff2:	687b      	ldr	r3, [r7, #4]
 8001ff4:	681b      	ldr	r3, [r3, #0]
 8001ff6:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
 8001ffa:	605a      	str	r2, [r3, #4]
  }
  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
 8001ffc:	687b      	ldr	r3, [r7, #4]
 8001ffe:	681b      	ldr	r3, [r3, #0]
 8002000:	685b      	ldr	r3, [r3, #4]
 8002002:	687a      	ldr	r2, [r7, #4]
 8002004:	6812      	ldr	r2, [r2, #0]
 8002006:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
 800200a:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
 800200e:	6053      	str	r3, [r2, #4]

  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
  /* Disable Own Address2 before set the Own Address2 configuration */
  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
 8002010:	687b      	ldr	r3, [r7, #4]
 8002012:	681b      	ldr	r3, [r3, #0]
 8002014:	68da      	ldr	r2, [r3, #12]
 8002016:	687b      	ldr	r3, [r7, #4]
 8002018:	681b      	ldr	r3, [r3, #0]
 800201a:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
 800201e:	60da      	str	r2, [r3, #12]

  /* Configure I2Cx: Dual mode and Own Address2 */
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
 8002020:	687b      	ldr	r3, [r7, #4]
 8002022:	691a      	ldr	r2, [r3, #16]
 8002024:	687b      	ldr	r3, [r7, #4]
 8002026:	695b      	ldr	r3, [r3, #20]
 8002028:	ea42 0103 	orr.w	r1, r2, r3
                          (hi2c->Init.OwnAddress2Masks << 8));
 800202c:	687b      	ldr	r3, [r7, #4]
 800202e:	699b      	ldr	r3, [r3, #24]
 8002030:	021a      	lsls	r2, r3, #8
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
 8002032:	687b      	ldr	r3, [r7, #4]
 8002034:	681b      	ldr	r3, [r3, #0]
 8002036:	430a      	orrs	r2, r1
 8002038:	60da      	str	r2, [r3, #12]

  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
  /* Configure I2Cx: Generalcall and NoStretch mode */
  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
 800203a:	687b      	ldr	r3, [r7, #4]
 800203c:	69d9      	ldr	r1, [r3, #28]
 800203e:	687b      	ldr	r3, [r7, #4]
 8002040:	6a1a      	ldr	r2, [r3, #32]
 8002042:	687b      	ldr	r3, [r7, #4]
 8002044:	681b      	ldr	r3, [r3, #0]
 8002046:	430a      	orrs	r2, r1
 8002048:	601a      	str	r2, [r3, #0]

  /* Enable the selected I2C peripheral */
  __HAL_I2C_ENABLE(hi2c);
 800204a:	687b      	ldr	r3, [r7, #4]
 800204c:	681b      	ldr	r3, [r3, #0]
 800204e:	681a      	ldr	r2, [r3, #0]
 8002050:	687b      	ldr	r3, [r7, #4]
 8002052:	681b      	ldr	r3, [r3, #0]
 8002054:	f042 0201 	orr.w	r2, r2, #1
 8002058:	601a      	str	r2, [r3, #0]

  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 800205a:	687b      	ldr	r3, [r7, #4]
 800205c:	2200      	movs	r2, #0
 800205e:	645a      	str	r2, [r3, #68]	@ 0x44
  hi2c->State = HAL_I2C_STATE_READY;
 8002060:	687b      	ldr	r3, [r7, #4]
 8002062:	2220      	movs	r2, #32
 8002064:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
  hi2c->PreviousState = I2C_STATE_NONE;
 8002068:	687b      	ldr	r3, [r7, #4]
 800206a:	2200      	movs	r2, #0
 800206c:	631a      	str	r2, [r3, #48]	@ 0x30
  hi2c->Mode = HAL_I2C_MODE_NONE;
 800206e:	687b      	ldr	r3, [r7, #4]
 8002070:	2200      	movs	r2, #0
 8002072:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

  return HAL_OK;
 8002076:	2300      	movs	r3, #0
}
 8002078:	4618      	mov	r0, r3
 800207a:	3708      	adds	r7, #8
 800207c:	46bd      	mov	sp, r7
 800207e:	bd80      	pop	{r7, pc}

08002080 <HAL_I2CEx_ConfigAnalogFilter>:
  *                the configuration information for the specified I2Cx peripheral.
  * @param  AnalogFilter New state of the Analog filter.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
 8002080:	b480      	push	{r7}
 8002082:	b083      	sub	sp, #12
 8002084:	af00      	add	r7, sp, #0
 8002086:	6078      	str	r0, [r7, #4]
 8002088:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));

  if (hi2c->State == HAL_I2C_STATE_READY)
 800208a:	687b      	ldr	r3, [r7, #4]
 800208c:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 8002090:	b2db      	uxtb	r3, r3
 8002092:	2b20      	cmp	r3, #32
 8002094:	d138      	bne.n	8002108 <HAL_I2CEx_ConfigAnalogFilter+0x88>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 8002096:	687b      	ldr	r3, [r7, #4]
 8002098:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 800209c:	2b01      	cmp	r3, #1
 800209e:	d101      	bne.n	80020a4 <HAL_I2CEx_ConfigAnalogFilter+0x24>
 80020a0:	2302      	movs	r3, #2
 80020a2:	e032      	b.n	800210a <HAL_I2CEx_ConfigAnalogFilter+0x8a>
 80020a4:	687b      	ldr	r3, [r7, #4]
 80020a6:	2201      	movs	r2, #1
 80020a8:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    hi2c->State = HAL_I2C_STATE_BUSY;
 80020ac:	687b      	ldr	r3, [r7, #4]
 80020ae:	2224      	movs	r2, #36	@ 0x24
 80020b0:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Disable the selected I2C peripheral */
    __HAL_I2C_DISABLE(hi2c);
 80020b4:	687b      	ldr	r3, [r7, #4]
 80020b6:	681b      	ldr	r3, [r3, #0]
 80020b8:	681a      	ldr	r2, [r3, #0]
 80020ba:	687b      	ldr	r3, [r7, #4]
 80020bc:	681b      	ldr	r3, [r3, #0]
 80020be:	f022 0201 	bic.w	r2, r2, #1
 80020c2:	601a      	str	r2, [r3, #0]

    /* Reset I2Cx ANOFF bit */
    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
 80020c4:	687b      	ldr	r3, [r7, #4]
 80020c6:	681b      	ldr	r3, [r3, #0]
 80020c8:	681a      	ldr	r2, [r3, #0]
 80020ca:	687b      	ldr	r3, [r7, #4]
 80020cc:	681b      	ldr	r3, [r3, #0]
 80020ce:	f422 5280 	bic.w	r2, r2, #4096	@ 0x1000
 80020d2:	601a      	str	r2, [r3, #0]

    /* Set analog filter bit*/
    hi2c->Instance->CR1 |= AnalogFilter;
 80020d4:	687b      	ldr	r3, [r7, #4]
 80020d6:	681b      	ldr	r3, [r3, #0]
 80020d8:	6819      	ldr	r1, [r3, #0]
 80020da:	687b      	ldr	r3, [r7, #4]
 80020dc:	681b      	ldr	r3, [r3, #0]
 80020de:	683a      	ldr	r2, [r7, #0]
 80020e0:	430a      	orrs	r2, r1
 80020e2:	601a      	str	r2, [r3, #0]

    __HAL_I2C_ENABLE(hi2c);
 80020e4:	687b      	ldr	r3, [r7, #4]
 80020e6:	681b      	ldr	r3, [r3, #0]
 80020e8:	681a      	ldr	r2, [r3, #0]
 80020ea:	687b      	ldr	r3, [r7, #4]
 80020ec:	681b      	ldr	r3, [r3, #0]
 80020ee:	f042 0201 	orr.w	r2, r2, #1
 80020f2:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 80020f4:	687b      	ldr	r3, [r7, #4]
 80020f6:	2220      	movs	r2, #32
 80020f8:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 80020fc:	687b      	ldr	r3, [r7, #4]
 80020fe:	2200      	movs	r2, #0
 8002100:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 8002104:	2300      	movs	r3, #0
 8002106:	e000      	b.n	800210a <HAL_I2CEx_ConfigAnalogFilter+0x8a>
  }
  else
  {
    return HAL_BUSY;
 8002108:	2302      	movs	r3, #2
  }
}
 800210a:	4618      	mov	r0, r3
 800210c:	370c      	adds	r7, #12
 800210e:	46bd      	mov	sp, r7
 8002110:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002114:	4770      	bx	lr

08002116 <HAL_I2CEx_ConfigDigitalFilter>:
  *                the configuration information for the specified I2Cx peripheral.
  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
 8002116:	b480      	push	{r7}
 8002118:	b085      	sub	sp, #20
 800211a:	af00      	add	r7, sp, #0
 800211c:	6078      	str	r0, [r7, #4]
 800211e:	6039      	str	r1, [r7, #0]

  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));

  if (hi2c->State == HAL_I2C_STATE_READY)
 8002120:	687b      	ldr	r3, [r7, #4]
 8002122:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 8002126:	b2db      	uxtb	r3, r3
 8002128:	2b20      	cmp	r3, #32
 800212a:	d139      	bne.n	80021a0 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 800212c:	687b      	ldr	r3, [r7, #4]
 800212e:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 8002132:	2b01      	cmp	r3, #1
 8002134:	d101      	bne.n	800213a <HAL_I2CEx_ConfigDigitalFilter+0x24>
 8002136:	2302      	movs	r3, #2
 8002138:	e033      	b.n	80021a2 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
 800213a:	687b      	ldr	r3, [r7, #4]
 800213c:	2201      	movs	r2, #1
 800213e:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    hi2c->State = HAL_I2C_STATE_BUSY;
 8002142:	687b      	ldr	r3, [r7, #4]
 8002144:	2224      	movs	r2, #36	@ 0x24
 8002146:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Disable the selected I2C peripheral */
    __HAL_I2C_DISABLE(hi2c);
 800214a:	687b      	ldr	r3, [r7, #4]
 800214c:	681b      	ldr	r3, [r3, #0]
 800214e:	681a      	ldr	r2, [r3, #0]
 8002150:	687b      	ldr	r3, [r7, #4]
 8002152:	681b      	ldr	r3, [r3, #0]
 8002154:	f022 0201 	bic.w	r2, r2, #1
 8002158:	601a      	str	r2, [r3, #0]

    /* Get the old register value */
    tmpreg = hi2c->Instance->CR1;
 800215a:	687b      	ldr	r3, [r7, #4]
 800215c:	681b      	ldr	r3, [r3, #0]
 800215e:	681b      	ldr	r3, [r3, #0]
 8002160:	60fb      	str	r3, [r7, #12]

    /* Reset I2Cx DNF bits [11:8] */
    tmpreg &= ~(I2C_CR1_DNF);
 8002162:	68fb      	ldr	r3, [r7, #12]
 8002164:	f423 6370 	bic.w	r3, r3, #3840	@ 0xf00
 8002168:	60fb      	str	r3, [r7, #12]

    /* Set I2Cx DNF coefficient */
    tmpreg |= DigitalFilter << 8U;
 800216a:	683b      	ldr	r3, [r7, #0]
 800216c:	021b      	lsls	r3, r3, #8
 800216e:	68fa      	ldr	r2, [r7, #12]
 8002170:	4313      	orrs	r3, r2
 8002172:	60fb      	str	r3, [r7, #12]

    /* Store the new register value */
    hi2c->Instance->CR1 = tmpreg;
 8002174:	687b      	ldr	r3, [r7, #4]
 8002176:	681b      	ldr	r3, [r3, #0]
 8002178:	68fa      	ldr	r2, [r7, #12]
 800217a:	601a      	str	r2, [r3, #0]

    __HAL_I2C_ENABLE(hi2c);
 800217c:	687b      	ldr	r3, [r7, #4]
 800217e:	681b      	ldr	r3, [r3, #0]
 8002180:	681a      	ldr	r2, [r3, #0]
 8002182:	687b      	ldr	r3, [r7, #4]
 8002184:	681b      	ldr	r3, [r3, #0]
 8002186:	f042 0201 	orr.w	r2, r2, #1
 800218a:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 800218c:	687b      	ldr	r3, [r7, #4]
 800218e:	2220      	movs	r2, #32
 8002190:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8002194:	687b      	ldr	r3, [r7, #4]
 8002196:	2200      	movs	r2, #0
 8002198:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 800219c:	2300      	movs	r3, #0
 800219e:	e000      	b.n	80021a2 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
  }
  else
  {
    return HAL_BUSY;
 80021a0:	2302      	movs	r3, #2
  }
}
 80021a2:	4618      	mov	r0, r3
 80021a4:	3714      	adds	r7, #20
 80021a6:	46bd      	mov	sp, r7
 80021a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80021ac:	4770      	bx	lr

080021ae <HAL_PCD_Init>:
  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
  * @param  hpcd PCD handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
 80021ae:	b580      	push	{r7, lr}
 80021b0:	b086      	sub	sp, #24
 80021b2:	af02      	add	r7, sp, #8
 80021b4:	6078      	str	r0, [r7, #4]
  uint8_t i;

  /* Check the PCD handle allocation */
  if (hpcd == NULL)
 80021b6:	687b      	ldr	r3, [r7, #4]
 80021b8:	2b00      	cmp	r3, #0
 80021ba:	d101      	bne.n	80021c0 <HAL_PCD_Init+0x12>
  {
    return HAL_ERROR;
 80021bc:	2301      	movs	r3, #1
 80021be:	e101      	b.n	80023c4 <HAL_PCD_Init+0x216>
  }

  /* Check the parameters */
  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));

  if (hpcd->State == HAL_PCD_STATE_RESET)
 80021c0:	687b      	ldr	r3, [r7, #4]
 80021c2:	f893 3495 	ldrb.w	r3, [r3, #1173]	@ 0x495
 80021c6:	b2db      	uxtb	r3, r3
 80021c8:	2b00      	cmp	r3, #0
 80021ca:	d106      	bne.n	80021da <HAL_PCD_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    hpcd->Lock = HAL_UNLOCKED;
 80021cc:	687b      	ldr	r3, [r7, #4]
 80021ce:	2200      	movs	r2, #0
 80021d0:	f883 2494 	strb.w	r2, [r3, #1172]	@ 0x494

    /* Init the low level hardware */
    hpcd->MspInitCallback(hpcd);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
    HAL_PCD_MspInit(hpcd);
 80021d4:	6878      	ldr	r0, [r7, #4]
 80021d6:	f7ff f8dd 	bl	8001394 <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
  }

  hpcd->State = HAL_PCD_STATE_BUSY;
 80021da:	687b      	ldr	r3, [r7, #4]
 80021dc:	2203      	movs	r2, #3
 80021de:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495

  /* Disable DMA mode for FS instance */
  hpcd->Init.dma_enable = 0U;
 80021e2:	687b      	ldr	r3, [r7, #4]
 80021e4:	2200      	movs	r2, #0
 80021e6:	719a      	strb	r2, [r3, #6]

  /* Disable the Interrupts */
  __HAL_PCD_DISABLE(hpcd);
 80021e8:	687b      	ldr	r3, [r7, #4]
 80021ea:	681b      	ldr	r3, [r3, #0]
 80021ec:	4618      	mov	r0, r3
 80021ee:	f002 fe05 	bl	8004dfc <USB_DisableGlobalInt>

  /*Init the Core (common init.) */
  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
 80021f2:	687b      	ldr	r3, [r7, #4]
 80021f4:	6818      	ldr	r0, [r3, #0]
 80021f6:	687b      	ldr	r3, [r7, #4]
 80021f8:	7c1a      	ldrb	r2, [r3, #16]
 80021fa:	f88d 2000 	strb.w	r2, [sp]
 80021fe:	3304      	adds	r3, #4
 8002200:	cb0e      	ldmia	r3, {r1, r2, r3}
 8002202:	f002 fdce 	bl	8004da2 <USB_CoreInit>
 8002206:	4603      	mov	r3, r0
 8002208:	2b00      	cmp	r3, #0
 800220a:	d005      	beq.n	8002218 <HAL_PCD_Init+0x6a>
  {
    hpcd->State = HAL_PCD_STATE_ERROR;
 800220c:	687b      	ldr	r3, [r7, #4]
 800220e:	2202      	movs	r2, #2
 8002210:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495
    return HAL_ERROR;
 8002214:	2301      	movs	r3, #1
 8002216:	e0d5      	b.n	80023c4 <HAL_PCD_Init+0x216>
  }

  /* Force Device Mode */
  if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
 8002218:	687b      	ldr	r3, [r7, #4]
 800221a:	681b      	ldr	r3, [r3, #0]
 800221c:	2100      	movs	r1, #0
 800221e:	4618      	mov	r0, r3
 8002220:	f002 fdfd 	bl	8004e1e <USB_SetCurrentMode>
 8002224:	4603      	mov	r3, r0
 8002226:	2b00      	cmp	r3, #0
 8002228:	d005      	beq.n	8002236 <HAL_PCD_Init+0x88>
  {
    hpcd->State = HAL_PCD_STATE_ERROR;
 800222a:	687b      	ldr	r3, [r7, #4]
 800222c:	2202      	movs	r2, #2
 800222e:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495
    return HAL_ERROR;
 8002232:	2301      	movs	r3, #1
 8002234:	e0c6      	b.n	80023c4 <HAL_PCD_Init+0x216>
  }

  /* Init endpoints structures */
  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
 8002236:	2300      	movs	r3, #0
 8002238:	73fb      	strb	r3, [r7, #15]
 800223a:	e04a      	b.n	80022d2 <HAL_PCD_Init+0x124>
  {
    /* Init ep structure */
    hpcd->IN_ep[i].is_in = 1U;
 800223c:	7bfa      	ldrb	r2, [r7, #15]
 800223e:	6879      	ldr	r1, [r7, #4]
 8002240:	4613      	mov	r3, r2
 8002242:	00db      	lsls	r3, r3, #3
 8002244:	4413      	add	r3, r2
 8002246:	009b      	lsls	r3, r3, #2
 8002248:	440b      	add	r3, r1
 800224a:	3315      	adds	r3, #21
 800224c:	2201      	movs	r2, #1
 800224e:	701a      	strb	r2, [r3, #0]
    hpcd->IN_ep[i].num = i;
 8002250:	7bfa      	ldrb	r2, [r7, #15]
 8002252:	6879      	ldr	r1, [r7, #4]
 8002254:	4613      	mov	r3, r2
 8002256:	00db      	lsls	r3, r3, #3
 8002258:	4413      	add	r3, r2
 800225a:	009b      	lsls	r3, r3, #2
 800225c:	440b      	add	r3, r1
 800225e:	3314      	adds	r3, #20
 8002260:	7bfa      	ldrb	r2, [r7, #15]
 8002262:	701a      	strb	r2, [r3, #0]
#if defined (USB_OTG_FS)
    hpcd->IN_ep[i].tx_fifo_num = i;
 8002264:	7bfa      	ldrb	r2, [r7, #15]
 8002266:	7bfb      	ldrb	r3, [r7, #15]
 8002268:	b298      	uxth	r0, r3
 800226a:	6879      	ldr	r1, [r7, #4]
 800226c:	4613      	mov	r3, r2
 800226e:	00db      	lsls	r3, r3, #3
 8002270:	4413      	add	r3, r2
 8002272:	009b      	lsls	r3, r3, #2
 8002274:	440b      	add	r3, r1
 8002276:	332e      	adds	r3, #46	@ 0x2e
 8002278:	4602      	mov	r2, r0
 800227a:	801a      	strh	r2, [r3, #0]
#endif /* defined (USB_OTG_FS) */
    /* Control until ep is activated */
    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
 800227c:	7bfa      	ldrb	r2, [r7, #15]
 800227e:	6879      	ldr	r1, [r7, #4]
 8002280:	4613      	mov	r3, r2
 8002282:	00db      	lsls	r3, r3, #3
 8002284:	4413      	add	r3, r2
 8002286:	009b      	lsls	r3, r3, #2
 8002288:	440b      	add	r3, r1
 800228a:	3318      	adds	r3, #24
 800228c:	2200      	movs	r2, #0
 800228e:	701a      	strb	r2, [r3, #0]
    hpcd->IN_ep[i].maxpacket = 0U;
 8002290:	7bfa      	ldrb	r2, [r7, #15]
 8002292:	6879      	ldr	r1, [r7, #4]
 8002294:	4613      	mov	r3, r2
 8002296:	00db      	lsls	r3, r3, #3
 8002298:	4413      	add	r3, r2
 800229a:	009b      	lsls	r3, r3, #2
 800229c:	440b      	add	r3, r1
 800229e:	331c      	adds	r3, #28
 80022a0:	2200      	movs	r2, #0
 80022a2:	601a      	str	r2, [r3, #0]
    hpcd->IN_ep[i].xfer_buff = 0U;
 80022a4:	7bfa      	ldrb	r2, [r7, #15]
 80022a6:	6879      	ldr	r1, [r7, #4]
 80022a8:	4613      	mov	r3, r2
 80022aa:	00db      	lsls	r3, r3, #3
 80022ac:	4413      	add	r3, r2
 80022ae:	009b      	lsls	r3, r3, #2
 80022b0:	440b      	add	r3, r1
 80022b2:	3320      	adds	r3, #32
 80022b4:	2200      	movs	r2, #0
 80022b6:	601a      	str	r2, [r3, #0]
    hpcd->IN_ep[i].xfer_len = 0U;
 80022b8:	7bfa      	ldrb	r2, [r7, #15]
 80022ba:	6879      	ldr	r1, [r7, #4]
 80022bc:	4613      	mov	r3, r2
 80022be:	00db      	lsls	r3, r3, #3
 80022c0:	4413      	add	r3, r2
 80022c2:	009b      	lsls	r3, r3, #2
 80022c4:	440b      	add	r3, r1
 80022c6:	3324      	adds	r3, #36	@ 0x24
 80022c8:	2200      	movs	r2, #0
 80022ca:	601a      	str	r2, [r3, #0]
  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
 80022cc:	7bfb      	ldrb	r3, [r7, #15]
 80022ce:	3301      	adds	r3, #1
 80022d0:	73fb      	strb	r3, [r7, #15]
 80022d2:	687b      	ldr	r3, [r7, #4]
 80022d4:	791b      	ldrb	r3, [r3, #4]
 80022d6:	7bfa      	ldrb	r2, [r7, #15]
 80022d8:	429a      	cmp	r2, r3
 80022da:	d3af      	bcc.n	800223c <HAL_PCD_Init+0x8e>
  }

  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
 80022dc:	2300      	movs	r3, #0
 80022de:	73fb      	strb	r3, [r7, #15]
 80022e0:	e044      	b.n	800236c <HAL_PCD_Init+0x1be>
  {
    hpcd->OUT_ep[i].is_in = 0U;
 80022e2:	7bfa      	ldrb	r2, [r7, #15]
 80022e4:	6879      	ldr	r1, [r7, #4]
 80022e6:	4613      	mov	r3, r2
 80022e8:	00db      	lsls	r3, r3, #3
 80022ea:	4413      	add	r3, r2
 80022ec:	009b      	lsls	r3, r3, #2
 80022ee:	440b      	add	r3, r1
 80022f0:	f203 2355 	addw	r3, r3, #597	@ 0x255
 80022f4:	2200      	movs	r2, #0
 80022f6:	701a      	strb	r2, [r3, #0]
    hpcd->OUT_ep[i].num = i;
 80022f8:	7bfa      	ldrb	r2, [r7, #15]
 80022fa:	6879      	ldr	r1, [r7, #4]
 80022fc:	4613      	mov	r3, r2
 80022fe:	00db      	lsls	r3, r3, #3
 8002300:	4413      	add	r3, r2
 8002302:	009b      	lsls	r3, r3, #2
 8002304:	440b      	add	r3, r1
 8002306:	f503 7315 	add.w	r3, r3, #596	@ 0x254
 800230a:	7bfa      	ldrb	r2, [r7, #15]
 800230c:	701a      	strb	r2, [r3, #0]
    /* Control until ep is activated */
    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
 800230e:	7bfa      	ldrb	r2, [r7, #15]
 8002310:	6879      	ldr	r1, [r7, #4]
 8002312:	4613      	mov	r3, r2
 8002314:	00db      	lsls	r3, r3, #3
 8002316:	4413      	add	r3, r2
 8002318:	009b      	lsls	r3, r3, #2
 800231a:	440b      	add	r3, r1
 800231c:	f503 7316 	add.w	r3, r3, #600	@ 0x258
 8002320:	2200      	movs	r2, #0
 8002322:	701a      	strb	r2, [r3, #0]
    hpcd->OUT_ep[i].maxpacket = 0U;
 8002324:	7bfa      	ldrb	r2, [r7, #15]
 8002326:	6879      	ldr	r1, [r7, #4]
 8002328:	4613      	mov	r3, r2
 800232a:	00db      	lsls	r3, r3, #3
 800232c:	4413      	add	r3, r2
 800232e:	009b      	lsls	r3, r3, #2
 8002330:	440b      	add	r3, r1
 8002332:	f503 7317 	add.w	r3, r3, #604	@ 0x25c
 8002336:	2200      	movs	r2, #0
 8002338:	601a      	str	r2, [r3, #0]
    hpcd->OUT_ep[i].xfer_buff = 0U;
 800233a:	7bfa      	ldrb	r2, [r7, #15]
 800233c:	6879      	ldr	r1, [r7, #4]
 800233e:	4613      	mov	r3, r2
 8002340:	00db      	lsls	r3, r3, #3
 8002342:	4413      	add	r3, r2
 8002344:	009b      	lsls	r3, r3, #2
 8002346:	440b      	add	r3, r1
 8002348:	f503 7318 	add.w	r3, r3, #608	@ 0x260
 800234c:	2200      	movs	r2, #0
 800234e:	601a      	str	r2, [r3, #0]
    hpcd->OUT_ep[i].xfer_len = 0U;
 8002350:	7bfa      	ldrb	r2, [r7, #15]
 8002352:	6879      	ldr	r1, [r7, #4]
 8002354:	4613      	mov	r3, r2
 8002356:	00db      	lsls	r3, r3, #3
 8002358:	4413      	add	r3, r2
 800235a:	009b      	lsls	r3, r3, #2
 800235c:	440b      	add	r3, r1
 800235e:	f503 7319 	add.w	r3, r3, #612	@ 0x264
 8002362:	2200      	movs	r2, #0
 8002364:	601a      	str	r2, [r3, #0]
  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
 8002366:	7bfb      	ldrb	r3, [r7, #15]
 8002368:	3301      	adds	r3, #1
 800236a:	73fb      	strb	r3, [r7, #15]
 800236c:	687b      	ldr	r3, [r7, #4]
 800236e:	791b      	ldrb	r3, [r3, #4]
 8002370:	7bfa      	ldrb	r2, [r7, #15]
 8002372:	429a      	cmp	r2, r3
 8002374:	d3b5      	bcc.n	80022e2 <HAL_PCD_Init+0x134>
  }

  /* Init Device */
  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
 8002376:	687b      	ldr	r3, [r7, #4]
 8002378:	6818      	ldr	r0, [r3, #0]
 800237a:	687b      	ldr	r3, [r7, #4]
 800237c:	7c1a      	ldrb	r2, [r3, #16]
 800237e:	f88d 2000 	strb.w	r2, [sp]
 8002382:	3304      	adds	r3, #4
 8002384:	cb0e      	ldmia	r3, {r1, r2, r3}
 8002386:	f002 fd97 	bl	8004eb8 <USB_DevInit>
 800238a:	4603      	mov	r3, r0
 800238c:	2b00      	cmp	r3, #0
 800238e:	d005      	beq.n	800239c <HAL_PCD_Init+0x1ee>
  {
    hpcd->State = HAL_PCD_STATE_ERROR;
 8002390:	687b      	ldr	r3, [r7, #4]
 8002392:	2202      	movs	r2, #2
 8002394:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495
    return HAL_ERROR;
 8002398:	2301      	movs	r3, #1
 800239a:	e013      	b.n	80023c4 <HAL_PCD_Init+0x216>
  }

  hpcd->USB_Address = 0U;
 800239c:	687b      	ldr	r3, [r7, #4]
 800239e:	2200      	movs	r2, #0
 80023a0:	745a      	strb	r2, [r3, #17]
  hpcd->State = HAL_PCD_STATE_READY;
 80023a2:	687b      	ldr	r3, [r7, #4]
 80023a4:	2201      	movs	r2, #1
 80023a6:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495

  /* Activate LPM */
  if (hpcd->Init.lpm_enable == 1U)
 80023aa:	687b      	ldr	r3, [r7, #4]
 80023ac:	7b1b      	ldrb	r3, [r3, #12]
 80023ae:	2b01      	cmp	r3, #1
 80023b0:	d102      	bne.n	80023b8 <HAL_PCD_Init+0x20a>
  {
    (void)HAL_PCDEx_ActivateLPM(hpcd);
 80023b2:	6878      	ldr	r0, [r7, #4]
 80023b4:	f000 f80a 	bl	80023cc <HAL_PCDEx_ActivateLPM>
  }

  (void)USB_DevDisconnect(hpcd->Instance);
 80023b8:	687b      	ldr	r3, [r7, #4]
 80023ba:	681b      	ldr	r3, [r3, #0]
 80023bc:	4618      	mov	r0, r3
 80023be:	f002 ff3c 	bl	800523a <USB_DevDisconnect>

  return HAL_OK;
 80023c2:	2300      	movs	r3, #0
}
 80023c4:	4618      	mov	r0, r3
 80023c6:	3710      	adds	r7, #16
 80023c8:	46bd      	mov	sp, r7
 80023ca:	bd80      	pop	{r7, pc}

080023cc <HAL_PCDEx_ActivateLPM>:
  * @brief  Activate LPM feature.
  * @param  hpcd PCD handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
 80023cc:	b480      	push	{r7}
 80023ce:	b085      	sub	sp, #20
 80023d0:	af00      	add	r7, sp, #0
 80023d2:	6078      	str	r0, [r7, #4]
  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
 80023d4:	687b      	ldr	r3, [r7, #4]
 80023d6:	681b      	ldr	r3, [r3, #0]
 80023d8:	60fb      	str	r3, [r7, #12]

  hpcd->lpm_active = 1U;
 80023da:	687b      	ldr	r3, [r7, #4]
 80023dc:	2201      	movs	r2, #1
 80023de:	f8c3 24d8 	str.w	r2, [r3, #1240]	@ 0x4d8
  hpcd->LPM_State = LPM_L0;
 80023e2:	687b      	ldr	r3, [r7, #4]
 80023e4:	2200      	movs	r2, #0
 80023e6:	f883 24cc 	strb.w	r2, [r3, #1228]	@ 0x4cc
  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
 80023ea:	68fb      	ldr	r3, [r7, #12]
 80023ec:	699b      	ldr	r3, [r3, #24]
 80023ee:	f043 6200 	orr.w	r2, r3, #134217728	@ 0x8000000
 80023f2:	68fb      	ldr	r3, [r7, #12]
 80023f4:	619a      	str	r2, [r3, #24]
  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
 80023f6:	68fb      	ldr	r3, [r7, #12]
 80023f8:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80023fa:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 80023fe:	f043 0303 	orr.w	r3, r3, #3
 8002402:	68fa      	ldr	r2, [r7, #12]
 8002404:	6553      	str	r3, [r2, #84]	@ 0x54

  return HAL_OK;
 8002406:	2300      	movs	r3, #0
}
 8002408:	4618      	mov	r0, r3
 800240a:	3714      	adds	r7, #20
 800240c:	46bd      	mov	sp, r7
 800240e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002412:	4770      	bx	lr

08002414 <HAL_PWR_EnableBkUpAccess>:
  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
  *        back-up domain.
  * @retval None
  */
void HAL_PWR_EnableBkUpAccess(void)
{
 8002414:	b480      	push	{r7}
 8002416:	af00      	add	r7, sp, #0
  SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8002418:	4b05      	ldr	r3, [pc, #20]	@ (8002430 <HAL_PWR_EnableBkUpAccess+0x1c>)
 800241a:	681b      	ldr	r3, [r3, #0]
 800241c:	4a04      	ldr	r2, [pc, #16]	@ (8002430 <HAL_PWR_EnableBkUpAccess+0x1c>)
 800241e:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8002422:	6013      	str	r3, [r2, #0]
}
 8002424:	bf00      	nop
 8002426:	46bd      	mov	sp, r7
 8002428:	f85d 7b04 	ldr.w	r7, [sp], #4
 800242c:	4770      	bx	lr
 800242e:	bf00      	nop
 8002430:	40007000 	.word	0x40007000

08002434 <HAL_PWREx_GetVoltageRange>:
  * @brief Return Voltage Scaling Range.
  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
  *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
  */
uint32_t HAL_PWREx_GetVoltageRange(void)
{
 8002434:	b480      	push	{r7}
 8002436:	af00      	add	r7, sp, #0
    else
    {
      return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
    }
#else
  return  (PWR->CR1 & PWR_CR1_VOS);
 8002438:	4b04      	ldr	r3, [pc, #16]	@ (800244c <HAL_PWREx_GetVoltageRange+0x18>)
 800243a:	681b      	ldr	r3, [r3, #0]
 800243c:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
#endif
}
 8002440:	4618      	mov	r0, r3
 8002442:	46bd      	mov	sp, r7
 8002444:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002448:	4770      	bx	lr
 800244a:	bf00      	nop
 800244c:	40007000 	.word	0x40007000

08002450 <HAL_PWREx_ControlVoltageScaling>:
  *        cleared before returning the status. If the flag is not cleared within
  *        50 microseconds, HAL_TIMEOUT status is reported.
  * @retval HAL Status
  */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
 8002450:	b480      	push	{r7}
 8002452:	b085      	sub	sp, #20
 8002454:	af00      	add	r7, sp, #0
 8002456:	6078      	str	r0, [r7, #4]
  }

#else

  /* If Set Range 1 */
  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
 8002458:	687b      	ldr	r3, [r7, #4]
 800245a:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800245e:	d130      	bne.n	80024c2 <HAL_PWREx_ControlVoltageScaling+0x72>
  {
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
 8002460:	4b23      	ldr	r3, [pc, #140]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8002462:	681b      	ldr	r3, [r3, #0]
 8002464:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
 8002468:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800246c:	d038      	beq.n	80024e0 <HAL_PWREx_ControlVoltageScaling+0x90>
    {
      /* Set Range 1 */
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 800246e:	4b20      	ldr	r3, [pc, #128]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8002470:	681b      	ldr	r3, [r3, #0]
 8002472:	f423 63c0 	bic.w	r3, r3, #1536	@ 0x600
 8002476:	4a1e      	ldr	r2, [pc, #120]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8002478:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
 800247c:	6013      	str	r3, [r2, #0]

      /* Wait until VOSF is cleared */
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 800247e:	4b1d      	ldr	r3, [pc, #116]	@ (80024f4 <HAL_PWREx_ControlVoltageScaling+0xa4>)
 8002480:	681b      	ldr	r3, [r3, #0]
 8002482:	2232      	movs	r2, #50	@ 0x32
 8002484:	fb02 f303 	mul.w	r3, r2, r3
 8002488:	4a1b      	ldr	r2, [pc, #108]	@ (80024f8 <HAL_PWREx_ControlVoltageScaling+0xa8>)
 800248a:	fba2 2303 	umull	r2, r3, r2, r3
 800248e:	0c9b      	lsrs	r3, r3, #18
 8002490:	3301      	adds	r3, #1
 8002492:	60fb      	str	r3, [r7, #12]
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 8002494:	e002      	b.n	800249c <HAL_PWREx_ControlVoltageScaling+0x4c>
      {
        wait_loop_index--;
 8002496:	68fb      	ldr	r3, [r7, #12]
 8002498:	3b01      	subs	r3, #1
 800249a:	60fb      	str	r3, [r7, #12]
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 800249c:	4b14      	ldr	r3, [pc, #80]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 800249e:	695b      	ldr	r3, [r3, #20]
 80024a0:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80024a4:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 80024a8:	d102      	bne.n	80024b0 <HAL_PWREx_ControlVoltageScaling+0x60>
 80024aa:	68fb      	ldr	r3, [r7, #12]
 80024ac:	2b00      	cmp	r3, #0
 80024ae:	d1f2      	bne.n	8002496 <HAL_PWREx_ControlVoltageScaling+0x46>
      }
      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
 80024b0:	4b0f      	ldr	r3, [pc, #60]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80024b2:	695b      	ldr	r3, [r3, #20]
 80024b4:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80024b8:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 80024bc:	d110      	bne.n	80024e0 <HAL_PWREx_ControlVoltageScaling+0x90>
      {
        return HAL_TIMEOUT;
 80024be:	2303      	movs	r3, #3
 80024c0:	e00f      	b.n	80024e2 <HAL_PWREx_ControlVoltageScaling+0x92>
      }
    }
  }
  else
  {
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
 80024c2:	4b0b      	ldr	r3, [pc, #44]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80024c4:	681b      	ldr	r3, [r3, #0]
 80024c6:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
 80024ca:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 80024ce:	d007      	beq.n	80024e0 <HAL_PWREx_ControlVoltageScaling+0x90>
    {
      /* Set Range 2 */
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
 80024d0:	4b07      	ldr	r3, [pc, #28]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80024d2:	681b      	ldr	r3, [r3, #0]
 80024d4:	f423 63c0 	bic.w	r3, r3, #1536	@ 0x600
 80024d8:	4a05      	ldr	r2, [pc, #20]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80024da:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
 80024de:	6013      	str	r3, [r2, #0]
      /* No need to wait for VOSF to be cleared for this transition */
    }
  }
#endif

  return HAL_OK;
 80024e0:	2300      	movs	r3, #0
}
 80024e2:	4618      	mov	r0, r3
 80024e4:	3714      	adds	r7, #20
 80024e6:	46bd      	mov	sp, r7
 80024e8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80024ec:	4770      	bx	lr
 80024ee:	bf00      	nop
 80024f0:	40007000 	.word	0x40007000
 80024f4:	20000004 	.word	0x20000004
 80024f8:	431bde83 	.word	0x431bde83

080024fc <HAL_PWREx_EnableVddUSB>:
  * @brief Enable VDDUSB supply.
  * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
  * @retval None
  */
void HAL_PWREx_EnableVddUSB(void)
{
 80024fc:	b480      	push	{r7}
 80024fe:	af00      	add	r7, sp, #0
  SET_BIT(PWR->CR2, PWR_CR2_USV);
 8002500:	4b05      	ldr	r3, [pc, #20]	@ (8002518 <HAL_PWREx_EnableVddUSB+0x1c>)
 8002502:	685b      	ldr	r3, [r3, #4]
 8002504:	4a04      	ldr	r2, [pc, #16]	@ (8002518 <HAL_PWREx_EnableVddUSB+0x1c>)
 8002506:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
 800250a:	6053      	str	r3, [r2, #4]
}
 800250c:	bf00      	nop
 800250e:	46bd      	mov	sp, r7
 8002510:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002514:	4770      	bx	lr
 8002516:	bf00      	nop
 8002518:	40007000 	.word	0x40007000

0800251c <HAL_QSPI_Init>:
  *        in the QSPI_InitTypeDef and initialize the associated handle.
  * @param hqspi QSPI handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
{
 800251c:	b580      	push	{r7, lr}
 800251e:	b086      	sub	sp, #24
 8002520:	af02      	add	r7, sp, #8
 8002522:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status;
  uint32_t tickstart = HAL_GetTick();
 8002524:	f7ff f8f6 	bl	8001714 <HAL_GetTick>
 8002528:	60f8      	str	r0, [r7, #12]

  /* Check the QSPI handle allocation */
  if(hqspi == NULL)
 800252a:	687b      	ldr	r3, [r7, #4]
 800252c:	2b00      	cmp	r3, #0
 800252e:	d101      	bne.n	8002534 <HAL_QSPI_Init+0x18>
  {
    return HAL_ERROR;
 8002530:	2301      	movs	r3, #1
 8002532:	e063      	b.n	80025fc <HAL_QSPI_Init+0xe0>
  {
    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
  }
#endif

  if(hqspi->State == HAL_QSPI_STATE_RESET)
 8002534:	687b      	ldr	r3, [r7, #4]
 8002536:	f893 3039 	ldrb.w	r3, [r3, #57]	@ 0x39
 800253a:	b2db      	uxtb	r3, r3
 800253c:	2b00      	cmp	r3, #0
 800253e:	d10b      	bne.n	8002558 <HAL_QSPI_Init+0x3c>
  {
    /* Allocate lock resource and initialize it */
    hqspi->Lock = HAL_UNLOCKED;
 8002540:	687b      	ldr	r3, [r7, #4]
 8002542:	2200      	movs	r2, #0
 8002544:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38

    /* Init the low level hardware */
    hqspi->MspInitCallback(hqspi);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_QSPI_MspInit(hqspi);
 8002548:	6878      	ldr	r0, [r7, #4]
 800254a:	f7fe fdf7 	bl	800113c <HAL_QSPI_MspInit>
#endif

    /* Configure the default timeout for the QSPI memory access */
    HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
 800254e:	f241 3188 	movw	r1, #5000	@ 0x1388
 8002552:	6878      	ldr	r0, [r7, #4]
 8002554:	f000 f858 	bl	8002608 <HAL_QSPI_SetTimeout>
  }

  /* Configure QSPI FIFO Threshold */
  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
 8002558:	687b      	ldr	r3, [r7, #4]
 800255a:	681b      	ldr	r3, [r3, #0]
 800255c:	681b      	ldr	r3, [r3, #0]
 800255e:	f423 6170 	bic.w	r1, r3, #3840	@ 0xf00
 8002562:	687b      	ldr	r3, [r7, #4]
 8002564:	689b      	ldr	r3, [r3, #8]
 8002566:	3b01      	subs	r3, #1
 8002568:	021a      	lsls	r2, r3, #8
 800256a:	687b      	ldr	r3, [r7, #4]
 800256c:	681b      	ldr	r3, [r3, #0]
 800256e:	430a      	orrs	r2, r1
 8002570:	601a      	str	r2, [r3, #0]
             ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));

  /* Wait till BUSY flag reset */
  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
 8002572:	687b      	ldr	r3, [r7, #4]
 8002574:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8002576:	9300      	str	r3, [sp, #0]
 8002578:	68fb      	ldr	r3, [r7, #12]
 800257a:	2200      	movs	r2, #0
 800257c:	2120      	movs	r1, #32
 800257e:	6878      	ldr	r0, [r7, #4]
 8002580:	f000 f850 	bl	8002624 <QSPI_WaitFlagStateUntilTimeout>
 8002584:	4603      	mov	r3, r0
 8002586:	72fb      	strb	r3, [r7, #11]

  if(status == HAL_OK)
 8002588:	7afb      	ldrb	r3, [r7, #11]
 800258a:	2b00      	cmp	r3, #0
 800258c:	d131      	bne.n	80025f2 <HAL_QSPI_Init+0xd6>
#if defined(QUADSPI_CR_DFM)
    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
#else
    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
 800258e:	687b      	ldr	r3, [r7, #4]
 8002590:	681b      	ldr	r3, [r3, #0]
 8002592:	681b      	ldr	r3, [r3, #0]
 8002594:	f023 437f 	bic.w	r3, r3, #4278190080	@ 0xff000000
 8002598:	f023 0310 	bic.w	r3, r3, #16
 800259c:	687a      	ldr	r2, [r7, #4]
 800259e:	6852      	ldr	r2, [r2, #4]
 80025a0:	0611      	lsls	r1, r2, #24
 80025a2:	687a      	ldr	r2, [r7, #4]
 80025a4:	68d2      	ldr	r2, [r2, #12]
 80025a6:	4311      	orrs	r1, r2
 80025a8:	687a      	ldr	r2, [r7, #4]
 80025aa:	6812      	ldr	r2, [r2, #0]
 80025ac:	430b      	orrs	r3, r1
 80025ae:	6013      	str	r3, [r2, #0]
               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
                hqspi->Init.SampleShifting));
#endif

    /* Configure QSPI Flash Size, CS High Time and Clock Mode */
    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
 80025b0:	687b      	ldr	r3, [r7, #4]
 80025b2:	681b      	ldr	r3, [r3, #0]
 80025b4:	685a      	ldr	r2, [r3, #4]
 80025b6:	4b13      	ldr	r3, [pc, #76]	@ (8002604 <HAL_QSPI_Init+0xe8>)
 80025b8:	4013      	ands	r3, r2
 80025ba:	687a      	ldr	r2, [r7, #4]
 80025bc:	6912      	ldr	r2, [r2, #16]
 80025be:	0411      	lsls	r1, r2, #16
 80025c0:	687a      	ldr	r2, [r7, #4]
 80025c2:	6952      	ldr	r2, [r2, #20]
 80025c4:	4311      	orrs	r1, r2
 80025c6:	687a      	ldr	r2, [r7, #4]
 80025c8:	6992      	ldr	r2, [r2, #24]
 80025ca:	4311      	orrs	r1, r2
 80025cc:	687a      	ldr	r2, [r7, #4]
 80025ce:	6812      	ldr	r2, [r2, #0]
 80025d0:	430b      	orrs	r3, r1
 80025d2:	6053      	str	r3, [r2, #4]
               ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));

    /* Enable the QSPI peripheral */
    __HAL_QSPI_ENABLE(hqspi);
 80025d4:	687b      	ldr	r3, [r7, #4]
 80025d6:	681b      	ldr	r3, [r3, #0]
 80025d8:	681a      	ldr	r2, [r3, #0]
 80025da:	687b      	ldr	r3, [r7, #4]
 80025dc:	681b      	ldr	r3, [r3, #0]
 80025de:	f042 0201 	orr.w	r2, r2, #1
 80025e2:	601a      	str	r2, [r3, #0]

    /* Set QSPI error code to none */
    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
 80025e4:	687b      	ldr	r3, [r7, #4]
 80025e6:	2200      	movs	r2, #0
 80025e8:	63da      	str	r2, [r3, #60]	@ 0x3c

    /* Initialize the QSPI state */
    hqspi->State = HAL_QSPI_STATE_READY;
 80025ea:	687b      	ldr	r3, [r7, #4]
 80025ec:	2201      	movs	r2, #1
 80025ee:	f883 2039 	strb.w	r2, [r3, #57]	@ 0x39
  }

  /* Release Lock */
  __HAL_UNLOCK(hqspi);
 80025f2:	687b      	ldr	r3, [r7, #4]
 80025f4:	2200      	movs	r2, #0
 80025f6:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38

  /* Return function status */
  return status;
 80025fa:	7afb      	ldrb	r3, [r7, #11]
}
 80025fc:	4618      	mov	r0, r3
 80025fe:	3710      	adds	r7, #16
 8002600:	46bd      	mov	sp, r7
 8002602:	bd80      	pop	{r7, pc}
 8002604:	ffe0f8fe 	.word	0xffe0f8fe

08002608 <HAL_QSPI_SetTimeout>:
  * @param  hqspi QSPI handle.
  * @param  Timeout Timeout for the QSPI memory access.
  * @retval None
  */
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
{
 8002608:	b480      	push	{r7}
 800260a:	b083      	sub	sp, #12
 800260c:	af00      	add	r7, sp, #0
 800260e:	6078      	str	r0, [r7, #4]
 8002610:	6039      	str	r1, [r7, #0]
  hqspi->Timeout = Timeout;
 8002612:	687b      	ldr	r3, [r7, #4]
 8002614:	683a      	ldr	r2, [r7, #0]
 8002616:	641a      	str	r2, [r3, #64]	@ 0x40
}
 8002618:	bf00      	nop
 800261a:	370c      	adds	r7, #12
 800261c:	46bd      	mov	sp, r7
 800261e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002622:	4770      	bx	lr

08002624 <QSPI_WaitFlagStateUntilTimeout>:
  * @param  Timeout Duration of the timeout
  * @retval HAL status
  */
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
 8002624:	b580      	push	{r7, lr}
 8002626:	b084      	sub	sp, #16
 8002628:	af00      	add	r7, sp, #0
 800262a:	60f8      	str	r0, [r7, #12]
 800262c:	60b9      	str	r1, [r7, #8]
 800262e:	603b      	str	r3, [r7, #0]
 8002630:	4613      	mov	r3, r2
 8002632:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is in expected state */
  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
 8002634:	e01a      	b.n	800266c <QSPI_WaitFlagStateUntilTimeout+0x48>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8002636:	69bb      	ldr	r3, [r7, #24]
 8002638:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 800263c:	d016      	beq.n	800266c <QSPI_WaitFlagStateUntilTimeout+0x48>
    {
      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 800263e:	f7ff f869 	bl	8001714 <HAL_GetTick>
 8002642:	4602      	mov	r2, r0
 8002644:	683b      	ldr	r3, [r7, #0]
 8002646:	1ad3      	subs	r3, r2, r3
 8002648:	69ba      	ldr	r2, [r7, #24]
 800264a:	429a      	cmp	r2, r3
 800264c:	d302      	bcc.n	8002654 <QSPI_WaitFlagStateUntilTimeout+0x30>
 800264e:	69bb      	ldr	r3, [r7, #24]
 8002650:	2b00      	cmp	r3, #0
 8002652:	d10b      	bne.n	800266c <QSPI_WaitFlagStateUntilTimeout+0x48>
      {
        hqspi->State     = HAL_QSPI_STATE_ERROR;
 8002654:	68fb      	ldr	r3, [r7, #12]
 8002656:	2204      	movs	r2, #4
 8002658:	f883 2039 	strb.w	r2, [r3, #57]	@ 0x39
        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
 800265c:	68fb      	ldr	r3, [r7, #12]
 800265e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8002660:	f043 0201 	orr.w	r2, r3, #1
 8002664:	68fb      	ldr	r3, [r7, #12]
 8002666:	63da      	str	r2, [r3, #60]	@ 0x3c

        return HAL_ERROR;
 8002668:	2301      	movs	r3, #1
 800266a:	e00e      	b.n	800268a <QSPI_WaitFlagStateUntilTimeout+0x66>
  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
 800266c:	68fb      	ldr	r3, [r7, #12]
 800266e:	681b      	ldr	r3, [r3, #0]
 8002670:	689a      	ldr	r2, [r3, #8]
 8002672:	68bb      	ldr	r3, [r7, #8]
 8002674:	4013      	ands	r3, r2
 8002676:	2b00      	cmp	r3, #0
 8002678:	bf14      	ite	ne
 800267a:	2301      	movne	r3, #1
 800267c:	2300      	moveq	r3, #0
 800267e:	b2db      	uxtb	r3, r3
 8002680:	461a      	mov	r2, r3
 8002682:	79fb      	ldrb	r3, [r7, #7]
 8002684:	429a      	cmp	r2, r3
 8002686:	d1d6      	bne.n	8002636 <QSPI_WaitFlagStateUntilTimeout+0x12>
      }
    }
  }
  return HAL_OK;
 8002688:	2300      	movs	r3, #0
}
 800268a:	4618      	mov	r0, r3
 800268c:	3710      	adds	r7, #16
 800268e:	46bd      	mov	sp, r7
 8002690:	bd80      	pop	{r7, pc}
	...

08002694 <HAL_RCC_OscConfig>:
  * @note   If HSE failed to start, HSE should be disabled before recalling
            HAL_RCC_OscConfig().
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8002694:	b580      	push	{r7, lr}
 8002696:	b088      	sub	sp, #32
 8002698:	af00      	add	r7, sp, #0
 800269a:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  HAL_StatusTypeDef status;
  uint32_t sysclk_source, pll_config;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 800269c:	687b      	ldr	r3, [r7, #4]
 800269e:	2b00      	cmp	r3, #0
 80026a0:	d101      	bne.n	80026a6 <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 80026a2:	2301      	movs	r3, #1
 80026a4:	e3ca      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 80026a6:	4b97      	ldr	r3, [pc, #604]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80026a8:	689b      	ldr	r3, [r3, #8]
 80026aa:	f003 030c 	and.w	r3, r3, #12
 80026ae:	61bb      	str	r3, [r7, #24]
  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
 80026b0:	4b94      	ldr	r3, [pc, #592]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80026b2:	68db      	ldr	r3, [r3, #12]
 80026b4:	f003 0303 	and.w	r3, r3, #3
 80026b8:	617b      	str	r3, [r7, #20]

  /*----------------------------- MSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
 80026ba:	687b      	ldr	r3, [r7, #4]
 80026bc:	681b      	ldr	r3, [r3, #0]
 80026be:	f003 0310 	and.w	r3, r3, #16
 80026c2:	2b00      	cmp	r3, #0
 80026c4:	f000 80e4 	beq.w	8002890 <HAL_RCC_OscConfig+0x1fc>
    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
    assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
    assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

    /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_CFGR_SWS_MSI) ||
 80026c8:	69bb      	ldr	r3, [r7, #24]
 80026ca:	2b00      	cmp	r3, #0
 80026cc:	d007      	beq.n	80026de <HAL_RCC_OscConfig+0x4a>
 80026ce:	69bb      	ldr	r3, [r7, #24]
 80026d0:	2b0c      	cmp	r3, #12
 80026d2:	f040 808b 	bne.w	80027ec <HAL_RCC_OscConfig+0x158>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
 80026d6:	697b      	ldr	r3, [r7, #20]
 80026d8:	2b01      	cmp	r3, #1
 80026da:	f040 8087 	bne.w	80027ec <HAL_RCC_OscConfig+0x158>
    {
      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 80026de:	4b89      	ldr	r3, [pc, #548]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80026e0:	681b      	ldr	r3, [r3, #0]
 80026e2:	f003 0302 	and.w	r3, r3, #2
 80026e6:	2b00      	cmp	r3, #0
 80026e8:	d005      	beq.n	80026f6 <HAL_RCC_OscConfig+0x62>
 80026ea:	687b      	ldr	r3, [r7, #4]
 80026ec:	699b      	ldr	r3, [r3, #24]
 80026ee:	2b00      	cmp	r3, #0
 80026f0:	d101      	bne.n	80026f6 <HAL_RCC_OscConfig+0x62>
      {
        return HAL_ERROR;
 80026f2:	2301      	movs	r3, #1
 80026f4:	e3a2      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      else
      {
        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
           must be correctly programmed according to the frequency of the CPU clock
           (HCLK) and the supply voltage of the device. */
        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
 80026f6:	687b      	ldr	r3, [r7, #4]
 80026f8:	6a1a      	ldr	r2, [r3, #32]
 80026fa:	4b82      	ldr	r3, [pc, #520]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80026fc:	681b      	ldr	r3, [r3, #0]
 80026fe:	f003 0308 	and.w	r3, r3, #8
 8002702:	2b00      	cmp	r3, #0
 8002704:	d004      	beq.n	8002710 <HAL_RCC_OscConfig+0x7c>
 8002706:	4b7f      	ldr	r3, [pc, #508]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002708:	681b      	ldr	r3, [r3, #0]
 800270a:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 800270e:	e005      	b.n	800271c <HAL_RCC_OscConfig+0x88>
 8002710:	4b7c      	ldr	r3, [pc, #496]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002712:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002716:	091b      	lsrs	r3, r3, #4
 8002718:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 800271c:	4293      	cmp	r3, r2
 800271e:	d223      	bcs.n	8002768 <HAL_RCC_OscConfig+0xd4>
        {
          /* First increase number of wait states update if necessary */
          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 8002720:	687b      	ldr	r3, [r7, #4]
 8002722:	6a1b      	ldr	r3, [r3, #32]
 8002724:	4618      	mov	r0, r3
 8002726:	f000 fd87 	bl	8003238 <RCC_SetFlashLatencyFromMSIRange>
 800272a:	4603      	mov	r3, r0
 800272c:	2b00      	cmp	r3, #0
 800272e:	d001      	beq.n	8002734 <HAL_RCC_OscConfig+0xa0>
          {
            return HAL_ERROR;
 8002730:	2301      	movs	r3, #1
 8002732:	e383      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
          }

          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8002734:	4b73      	ldr	r3, [pc, #460]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002736:	681b      	ldr	r3, [r3, #0]
 8002738:	4a72      	ldr	r2, [pc, #456]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800273a:	f043 0308 	orr.w	r3, r3, #8
 800273e:	6013      	str	r3, [r2, #0]
 8002740:	4b70      	ldr	r3, [pc, #448]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002742:	681b      	ldr	r3, [r3, #0]
 8002744:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8002748:	687b      	ldr	r3, [r7, #4]
 800274a:	6a1b      	ldr	r3, [r3, #32]
 800274c:	496d      	ldr	r1, [pc, #436]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800274e:	4313      	orrs	r3, r2
 8002750:	600b      	str	r3, [r1, #0]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8002752:	4b6c      	ldr	r3, [pc, #432]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002754:	685b      	ldr	r3, [r3, #4]
 8002756:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 800275a:	687b      	ldr	r3, [r7, #4]
 800275c:	69db      	ldr	r3, [r3, #28]
 800275e:	021b      	lsls	r3, r3, #8
 8002760:	4968      	ldr	r1, [pc, #416]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002762:	4313      	orrs	r3, r2
 8002764:	604b      	str	r3, [r1, #4]
 8002766:	e025      	b.n	80027b4 <HAL_RCC_OscConfig+0x120>
        }
        else
        {
          /* Else, keep current flash latency while decreasing applies */
          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8002768:	4b66      	ldr	r3, [pc, #408]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800276a:	681b      	ldr	r3, [r3, #0]
 800276c:	4a65      	ldr	r2, [pc, #404]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800276e:	f043 0308 	orr.w	r3, r3, #8
 8002772:	6013      	str	r3, [r2, #0]
 8002774:	4b63      	ldr	r3, [pc, #396]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002776:	681b      	ldr	r3, [r3, #0]
 8002778:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 800277c:	687b      	ldr	r3, [r7, #4]
 800277e:	6a1b      	ldr	r3, [r3, #32]
 8002780:	4960      	ldr	r1, [pc, #384]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002782:	4313      	orrs	r3, r2
 8002784:	600b      	str	r3, [r1, #0]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8002786:	4b5f      	ldr	r3, [pc, #380]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002788:	685b      	ldr	r3, [r3, #4]
 800278a:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 800278e:	687b      	ldr	r3, [r7, #4]
 8002790:	69db      	ldr	r3, [r3, #28]
 8002792:	021b      	lsls	r3, r3, #8
 8002794:	495b      	ldr	r1, [pc, #364]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002796:	4313      	orrs	r3, r2
 8002798:	604b      	str	r3, [r1, #4]

          /* Decrease number of wait states update if necessary */
          /* Only possible when MSI is the System clock source  */
          if(sysclk_source == RCC_CFGR_SWS_MSI)
 800279a:	69bb      	ldr	r3, [r7, #24]
 800279c:	2b00      	cmp	r3, #0
 800279e:	d109      	bne.n	80027b4 <HAL_RCC_OscConfig+0x120>
          {
            if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 80027a0:	687b      	ldr	r3, [r7, #4]
 80027a2:	6a1b      	ldr	r3, [r3, #32]
 80027a4:	4618      	mov	r0, r3
 80027a6:	f000 fd47 	bl	8003238 <RCC_SetFlashLatencyFromMSIRange>
 80027aa:	4603      	mov	r3, r0
 80027ac:	2b00      	cmp	r3, #0
 80027ae:	d001      	beq.n	80027b4 <HAL_RCC_OscConfig+0x120>
            {
              return HAL_ERROR;
 80027b0:	2301      	movs	r3, #1
 80027b2:	e343      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
            }
          }
        }

        /* Update the SystemCoreClock global variable */
        SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 80027b4:	f000 fc4a 	bl	800304c <HAL_RCC_GetSysClockFreq>
 80027b8:	4602      	mov	r2, r0
 80027ba:	4b52      	ldr	r3, [pc, #328]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80027bc:	689b      	ldr	r3, [r3, #8]
 80027be:	091b      	lsrs	r3, r3, #4
 80027c0:	f003 030f 	and.w	r3, r3, #15
 80027c4:	4950      	ldr	r1, [pc, #320]	@ (8002908 <HAL_RCC_OscConfig+0x274>)
 80027c6:	5ccb      	ldrb	r3, [r1, r3]
 80027c8:	f003 031f 	and.w	r3, r3, #31
 80027cc:	fa22 f303 	lsr.w	r3, r2, r3
 80027d0:	4a4e      	ldr	r2, [pc, #312]	@ (800290c <HAL_RCC_OscConfig+0x278>)
 80027d2:	6013      	str	r3, [r2, #0]

        /* Configure the source of time base considering new system clocks settings*/
        status = HAL_InitTick(uwTickPrio);
 80027d4:	4b4e      	ldr	r3, [pc, #312]	@ (8002910 <HAL_RCC_OscConfig+0x27c>)
 80027d6:	681b      	ldr	r3, [r3, #0]
 80027d8:	4618      	mov	r0, r3
 80027da:	f7fe fe77 	bl	80014cc <HAL_InitTick>
 80027de:	4603      	mov	r3, r0
 80027e0:	73fb      	strb	r3, [r7, #15]
        if(status != HAL_OK)
 80027e2:	7bfb      	ldrb	r3, [r7, #15]
 80027e4:	2b00      	cmp	r3, #0
 80027e6:	d052      	beq.n	800288e <HAL_RCC_OscConfig+0x1fa>
        {
          return status;
 80027e8:	7bfb      	ldrb	r3, [r7, #15]
 80027ea:	e327      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
    }
    else
    {
      /* Check the MSI State */
      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
 80027ec:	687b      	ldr	r3, [r7, #4]
 80027ee:	699b      	ldr	r3, [r3, #24]
 80027f0:	2b00      	cmp	r3, #0
 80027f2:	d032      	beq.n	800285a <HAL_RCC_OscConfig+0x1c6>
      {
        /* Enable the Internal High Speed oscillator (MSI). */
        __HAL_RCC_MSI_ENABLE();
 80027f4:	4b43      	ldr	r3, [pc, #268]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80027f6:	681b      	ldr	r3, [r3, #0]
 80027f8:	4a42      	ldr	r2, [pc, #264]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80027fa:	f043 0301 	orr.w	r3, r3, #1
 80027fe:	6013      	str	r3, [r2, #0]

        /* Get timeout */
        tickstart = HAL_GetTick();
 8002800:	f7fe ff88 	bl	8001714 <HAL_GetTick>
 8002804:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 8002806:	e008      	b.n	800281a <HAL_RCC_OscConfig+0x186>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8002808:	f7fe ff84 	bl	8001714 <HAL_GetTick>
 800280c:	4602      	mov	r2, r0
 800280e:	693b      	ldr	r3, [r7, #16]
 8002810:	1ad3      	subs	r3, r2, r3
 8002812:	2b02      	cmp	r3, #2
 8002814:	d901      	bls.n	800281a <HAL_RCC_OscConfig+0x186>
          {
            return HAL_TIMEOUT;
 8002816:	2303      	movs	r3, #3
 8002818:	e310      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 800281a:	4b3a      	ldr	r3, [pc, #232]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800281c:	681b      	ldr	r3, [r3, #0]
 800281e:	f003 0302 	and.w	r3, r3, #2
 8002822:	2b00      	cmp	r3, #0
 8002824:	d0f0      	beq.n	8002808 <HAL_RCC_OscConfig+0x174>
          }
        }
         /* Selects the Multiple Speed oscillator (MSI) clock range .*/
        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8002826:	4b37      	ldr	r3, [pc, #220]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002828:	681b      	ldr	r3, [r3, #0]
 800282a:	4a36      	ldr	r2, [pc, #216]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800282c:	f043 0308 	orr.w	r3, r3, #8
 8002830:	6013      	str	r3, [r2, #0]
 8002832:	4b34      	ldr	r3, [pc, #208]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002834:	681b      	ldr	r3, [r3, #0]
 8002836:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 800283a:	687b      	ldr	r3, [r7, #4]
 800283c:	6a1b      	ldr	r3, [r3, #32]
 800283e:	4931      	ldr	r1, [pc, #196]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002840:	4313      	orrs	r3, r2
 8002842:	600b      	str	r3, [r1, #0]
         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8002844:	4b2f      	ldr	r3, [pc, #188]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002846:	685b      	ldr	r3, [r3, #4]
 8002848:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 800284c:	687b      	ldr	r3, [r7, #4]
 800284e:	69db      	ldr	r3, [r3, #28]
 8002850:	021b      	lsls	r3, r3, #8
 8002852:	492c      	ldr	r1, [pc, #176]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002854:	4313      	orrs	r3, r2
 8002856:	604b      	str	r3, [r1, #4]
 8002858:	e01a      	b.n	8002890 <HAL_RCC_OscConfig+0x1fc>

      }
      else
      {
        /* Disable the Internal High Speed oscillator (MSI). */
        __HAL_RCC_MSI_DISABLE();
 800285a:	4b2a      	ldr	r3, [pc, #168]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800285c:	681b      	ldr	r3, [r3, #0]
 800285e:	4a29      	ldr	r2, [pc, #164]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002860:	f023 0301 	bic.w	r3, r3, #1
 8002864:	6013      	str	r3, [r2, #0]

        /* Get timeout */
        tickstart = HAL_GetTick();
 8002866:	f7fe ff55 	bl	8001714 <HAL_GetTick>
 800286a:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
 800286c:	e008      	b.n	8002880 <HAL_RCC_OscConfig+0x1ec>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 800286e:	f7fe ff51 	bl	8001714 <HAL_GetTick>
 8002872:	4602      	mov	r2, r0
 8002874:	693b      	ldr	r3, [r7, #16]
 8002876:	1ad3      	subs	r3, r2, r3
 8002878:	2b02      	cmp	r3, #2
 800287a:	d901      	bls.n	8002880 <HAL_RCC_OscConfig+0x1ec>
          {
            return HAL_TIMEOUT;
 800287c:	2303      	movs	r3, #3
 800287e:	e2dd      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
 8002880:	4b20      	ldr	r3, [pc, #128]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002882:	681b      	ldr	r3, [r3, #0]
 8002884:	f003 0302 	and.w	r3, r3, #2
 8002888:	2b00      	cmp	r3, #0
 800288a:	d1f0      	bne.n	800286e <HAL_RCC_OscConfig+0x1da>
 800288c:	e000      	b.n	8002890 <HAL_RCC_OscConfig+0x1fc>
      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 800288e:	bf00      	nop
        }
      }
    }
  }
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8002890:	687b      	ldr	r3, [r7, #4]
 8002892:	681b      	ldr	r3, [r3, #0]
 8002894:	f003 0301 	and.w	r3, r3, #1
 8002898:	2b00      	cmp	r3, #0
 800289a:	d074      	beq.n	8002986 <HAL_RCC_OscConfig+0x2f2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((sysclk_source == RCC_CFGR_SWS_HSE) ||
 800289c:	69bb      	ldr	r3, [r7, #24]
 800289e:	2b08      	cmp	r3, #8
 80028a0:	d005      	beq.n	80028ae <HAL_RCC_OscConfig+0x21a>
 80028a2:	69bb      	ldr	r3, [r7, #24]
 80028a4:	2b0c      	cmp	r3, #12
 80028a6:	d10e      	bne.n	80028c6 <HAL_RCC_OscConfig+0x232>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
 80028a8:	697b      	ldr	r3, [r7, #20]
 80028aa:	2b03      	cmp	r3, #3
 80028ac:	d10b      	bne.n	80028c6 <HAL_RCC_OscConfig+0x232>
    {
      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80028ae:	4b15      	ldr	r3, [pc, #84]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028b0:	681b      	ldr	r3, [r3, #0]
 80028b2:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80028b6:	2b00      	cmp	r3, #0
 80028b8:	d064      	beq.n	8002984 <HAL_RCC_OscConfig+0x2f0>
 80028ba:	687b      	ldr	r3, [r7, #4]
 80028bc:	685b      	ldr	r3, [r3, #4]
 80028be:	2b00      	cmp	r3, #0
 80028c0:	d160      	bne.n	8002984 <HAL_RCC_OscConfig+0x2f0>
      {
        return HAL_ERROR;
 80028c2:	2301      	movs	r3, #1
 80028c4:	e2ba      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 80028c6:	687b      	ldr	r3, [r7, #4]
 80028c8:	685b      	ldr	r3, [r3, #4]
 80028ca:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 80028ce:	d106      	bne.n	80028de <HAL_RCC_OscConfig+0x24a>
 80028d0:	4b0c      	ldr	r3, [pc, #48]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028d2:	681b      	ldr	r3, [r3, #0]
 80028d4:	4a0b      	ldr	r2, [pc, #44]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028d6:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80028da:	6013      	str	r3, [r2, #0]
 80028dc:	e026      	b.n	800292c <HAL_RCC_OscConfig+0x298>
 80028de:	687b      	ldr	r3, [r7, #4]
 80028e0:	685b      	ldr	r3, [r3, #4]
 80028e2:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 80028e6:	d115      	bne.n	8002914 <HAL_RCC_OscConfig+0x280>
 80028e8:	4b06      	ldr	r3, [pc, #24]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028ea:	681b      	ldr	r3, [r3, #0]
 80028ec:	4a05      	ldr	r2, [pc, #20]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028ee:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 80028f2:	6013      	str	r3, [r2, #0]
 80028f4:	4b03      	ldr	r3, [pc, #12]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028f6:	681b      	ldr	r3, [r3, #0]
 80028f8:	4a02      	ldr	r2, [pc, #8]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028fa:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80028fe:	6013      	str	r3, [r2, #0]
 8002900:	e014      	b.n	800292c <HAL_RCC_OscConfig+0x298>
 8002902:	bf00      	nop
 8002904:	40021000 	.word	0x40021000
 8002908:	08008200 	.word	0x08008200
 800290c:	20000004 	.word	0x20000004
 8002910:	20000008 	.word	0x20000008
 8002914:	4ba0      	ldr	r3, [pc, #640]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002916:	681b      	ldr	r3, [r3, #0]
 8002918:	4a9f      	ldr	r2, [pc, #636]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 800291a:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800291e:	6013      	str	r3, [r2, #0]
 8002920:	4b9d      	ldr	r3, [pc, #628]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002922:	681b      	ldr	r3, [r3, #0]
 8002924:	4a9c      	ldr	r2, [pc, #624]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002926:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 800292a:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 800292c:	687b      	ldr	r3, [r7, #4]
 800292e:	685b      	ldr	r3, [r3, #4]
 8002930:	2b00      	cmp	r3, #0
 8002932:	d013      	beq.n	800295c <HAL_RCC_OscConfig+0x2c8>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8002934:	f7fe feee 	bl	8001714 <HAL_GetTick>
 8002938:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 800293a:	e008      	b.n	800294e <HAL_RCC_OscConfig+0x2ba>
        {
          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800293c:	f7fe feea 	bl	8001714 <HAL_GetTick>
 8002940:	4602      	mov	r2, r0
 8002942:	693b      	ldr	r3, [r7, #16]
 8002944:	1ad3      	subs	r3, r2, r3
 8002946:	2b64      	cmp	r3, #100	@ 0x64
 8002948:	d901      	bls.n	800294e <HAL_RCC_OscConfig+0x2ba>
          {
            return HAL_TIMEOUT;
 800294a:	2303      	movs	r3, #3
 800294c:	e276      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 800294e:	4b92      	ldr	r3, [pc, #584]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002950:	681b      	ldr	r3, [r3, #0]
 8002952:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8002956:	2b00      	cmp	r3, #0
 8002958:	d0f0      	beq.n	800293c <HAL_RCC_OscConfig+0x2a8>
 800295a:	e014      	b.n	8002986 <HAL_RCC_OscConfig+0x2f2>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800295c:	f7fe feda 	bl	8001714 <HAL_GetTick>
 8002960:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 8002962:	e008      	b.n	8002976 <HAL_RCC_OscConfig+0x2e2>
        {
          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8002964:	f7fe fed6 	bl	8001714 <HAL_GetTick>
 8002968:	4602      	mov	r2, r0
 800296a:	693b      	ldr	r3, [r7, #16]
 800296c:	1ad3      	subs	r3, r2, r3
 800296e:	2b64      	cmp	r3, #100	@ 0x64
 8002970:	d901      	bls.n	8002976 <HAL_RCC_OscConfig+0x2e2>
          {
            return HAL_TIMEOUT;
 8002972:	2303      	movs	r3, #3
 8002974:	e262      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 8002976:	4b88      	ldr	r3, [pc, #544]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002978:	681b      	ldr	r3, [r3, #0]
 800297a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800297e:	2b00      	cmp	r3, #0
 8002980:	d1f0      	bne.n	8002964 <HAL_RCC_OscConfig+0x2d0>
 8002982:	e000      	b.n	8002986 <HAL_RCC_OscConfig+0x2f2>
      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8002984:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8002986:	687b      	ldr	r3, [r7, #4]
 8002988:	681b      	ldr	r3, [r3, #0]
 800298a:	f003 0302 	and.w	r3, r3, #2
 800298e:	2b00      	cmp	r3, #0
 8002990:	d060      	beq.n	8002a54 <HAL_RCC_OscConfig+0x3c0>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_CFGR_SWS_HSI) ||
 8002992:	69bb      	ldr	r3, [r7, #24]
 8002994:	2b04      	cmp	r3, #4
 8002996:	d005      	beq.n	80029a4 <HAL_RCC_OscConfig+0x310>
 8002998:	69bb      	ldr	r3, [r7, #24]
 800299a:	2b0c      	cmp	r3, #12
 800299c:	d119      	bne.n	80029d2 <HAL_RCC_OscConfig+0x33e>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
 800299e:	697b      	ldr	r3, [r7, #20]
 80029a0:	2b02      	cmp	r3, #2
 80029a2:	d116      	bne.n	80029d2 <HAL_RCC_OscConfig+0x33e>
    {
      /* When HSI is used as system clock it will not be disabled */
      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 80029a4:	4b7c      	ldr	r3, [pc, #496]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029a6:	681b      	ldr	r3, [r3, #0]
 80029a8:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80029ac:	2b00      	cmp	r3, #0
 80029ae:	d005      	beq.n	80029bc <HAL_RCC_OscConfig+0x328>
 80029b0:	687b      	ldr	r3, [r7, #4]
 80029b2:	68db      	ldr	r3, [r3, #12]
 80029b4:	2b00      	cmp	r3, #0
 80029b6:	d101      	bne.n	80029bc <HAL_RCC_OscConfig+0x328>
      {
        return HAL_ERROR;
 80029b8:	2301      	movs	r3, #1
 80029ba:	e23f      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80029bc:	4b76      	ldr	r3, [pc, #472]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029be:	685b      	ldr	r3, [r3, #4]
 80029c0:	f023 52f8 	bic.w	r2, r3, #520093696	@ 0x1f000000
 80029c4:	687b      	ldr	r3, [r7, #4]
 80029c6:	691b      	ldr	r3, [r3, #16]
 80029c8:	061b      	lsls	r3, r3, #24
 80029ca:	4973      	ldr	r1, [pc, #460]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029cc:	4313      	orrs	r3, r2
 80029ce:	604b      	str	r3, [r1, #4]
      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 80029d0:	e040      	b.n	8002a54 <HAL_RCC_OscConfig+0x3c0>
      }
    }
    else
    {
      /* Check the HSI State */
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 80029d2:	687b      	ldr	r3, [r7, #4]
 80029d4:	68db      	ldr	r3, [r3, #12]
 80029d6:	2b00      	cmp	r3, #0
 80029d8:	d023      	beq.n	8002a22 <HAL_RCC_OscConfig+0x38e>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 80029da:	4b6f      	ldr	r3, [pc, #444]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029dc:	681b      	ldr	r3, [r3, #0]
 80029de:	4a6e      	ldr	r2, [pc, #440]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029e0:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 80029e4:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80029e6:	f7fe fe95 	bl	8001714 <HAL_GetTick>
 80029ea:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 80029ec:	e008      	b.n	8002a00 <HAL_RCC_OscConfig+0x36c>
        {
          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80029ee:	f7fe fe91 	bl	8001714 <HAL_GetTick>
 80029f2:	4602      	mov	r2, r0
 80029f4:	693b      	ldr	r3, [r7, #16]
 80029f6:	1ad3      	subs	r3, r2, r3
 80029f8:	2b02      	cmp	r3, #2
 80029fa:	d901      	bls.n	8002a00 <HAL_RCC_OscConfig+0x36c>
          {
            return HAL_TIMEOUT;
 80029fc:	2303      	movs	r3, #3
 80029fe:	e21d      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8002a00:	4b65      	ldr	r3, [pc, #404]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a02:	681b      	ldr	r3, [r3, #0]
 8002a04:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8002a08:	2b00      	cmp	r3, #0
 8002a0a:	d0f0      	beq.n	80029ee <HAL_RCC_OscConfig+0x35a>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8002a0c:	4b62      	ldr	r3, [pc, #392]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a0e:	685b      	ldr	r3, [r3, #4]
 8002a10:	f023 52f8 	bic.w	r2, r3, #520093696	@ 0x1f000000
 8002a14:	687b      	ldr	r3, [r7, #4]
 8002a16:	691b      	ldr	r3, [r3, #16]
 8002a18:	061b      	lsls	r3, r3, #24
 8002a1a:	495f      	ldr	r1, [pc, #380]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a1c:	4313      	orrs	r3, r2
 8002a1e:	604b      	str	r3, [r1, #4]
 8002a20:	e018      	b.n	8002a54 <HAL_RCC_OscConfig+0x3c0>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 8002a22:	4b5d      	ldr	r3, [pc, #372]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a24:	681b      	ldr	r3, [r3, #0]
 8002a26:	4a5c      	ldr	r2, [pc, #368]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a28:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 8002a2c:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8002a2e:	f7fe fe71 	bl	8001714 <HAL_GetTick>
 8002a32:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 8002a34:	e008      	b.n	8002a48 <HAL_RCC_OscConfig+0x3b4>
        {
          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8002a36:	f7fe fe6d 	bl	8001714 <HAL_GetTick>
 8002a3a:	4602      	mov	r2, r0
 8002a3c:	693b      	ldr	r3, [r7, #16]
 8002a3e:	1ad3      	subs	r3, r2, r3
 8002a40:	2b02      	cmp	r3, #2
 8002a42:	d901      	bls.n	8002a48 <HAL_RCC_OscConfig+0x3b4>
          {
            return HAL_TIMEOUT;
 8002a44:	2303      	movs	r3, #3
 8002a46:	e1f9      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 8002a48:	4b53      	ldr	r3, [pc, #332]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a4a:	681b      	ldr	r3, [r3, #0]
 8002a4c:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8002a50:	2b00      	cmp	r3, #0
 8002a52:	d1f0      	bne.n	8002a36 <HAL_RCC_OscConfig+0x3a2>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8002a54:	687b      	ldr	r3, [r7, #4]
 8002a56:	681b      	ldr	r3, [r3, #0]
 8002a58:	f003 0308 	and.w	r3, r3, #8
 8002a5c:	2b00      	cmp	r3, #0
 8002a5e:	d03c      	beq.n	8002ada <HAL_RCC_OscConfig+0x446>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8002a60:	687b      	ldr	r3, [r7, #4]
 8002a62:	695b      	ldr	r3, [r3, #20]
 8002a64:	2b00      	cmp	r3, #0
 8002a66:	d01c      	beq.n	8002aa2 <HAL_RCC_OscConfig+0x40e>
        MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
      }
#endif /* RCC_CSR_LSIPREDIV */

      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8002a68:	4b4b      	ldr	r3, [pc, #300]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a6a:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002a6e:	4a4a      	ldr	r2, [pc, #296]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a70:	f043 0301 	orr.w	r3, r3, #1
 8002a74:	f8c2 3094 	str.w	r3, [r2, #148]	@ 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002a78:	f7fe fe4c 	bl	8001714 <HAL_GetTick>
 8002a7c:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8002a7e:	e008      	b.n	8002a92 <HAL_RCC_OscConfig+0x3fe>
      {
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8002a80:	f7fe fe48 	bl	8001714 <HAL_GetTick>
 8002a84:	4602      	mov	r2, r0
 8002a86:	693b      	ldr	r3, [r7, #16]
 8002a88:	1ad3      	subs	r3, r2, r3
 8002a8a:	2b02      	cmp	r3, #2
 8002a8c:	d901      	bls.n	8002a92 <HAL_RCC_OscConfig+0x3fe>
        {
          return HAL_TIMEOUT;
 8002a8e:	2303      	movs	r3, #3
 8002a90:	e1d4      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8002a92:	4b41      	ldr	r3, [pc, #260]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a94:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002a98:	f003 0302 	and.w	r3, r3, #2
 8002a9c:	2b00      	cmp	r3, #0
 8002a9e:	d0ef      	beq.n	8002a80 <HAL_RCC_OscConfig+0x3ec>
 8002aa0:	e01b      	b.n	8002ada <HAL_RCC_OscConfig+0x446>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8002aa2:	4b3d      	ldr	r3, [pc, #244]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002aa4:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002aa8:	4a3b      	ldr	r2, [pc, #236]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002aaa:	f023 0301 	bic.w	r3, r3, #1
 8002aae:	f8c2 3094 	str.w	r3, [r2, #148]	@ 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002ab2:	f7fe fe2f 	bl	8001714 <HAL_GetTick>
 8002ab6:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is disabled */
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8002ab8:	e008      	b.n	8002acc <HAL_RCC_OscConfig+0x438>
      {
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8002aba:	f7fe fe2b 	bl	8001714 <HAL_GetTick>
 8002abe:	4602      	mov	r2, r0
 8002ac0:	693b      	ldr	r3, [r7, #16]
 8002ac2:	1ad3      	subs	r3, r2, r3
 8002ac4:	2b02      	cmp	r3, #2
 8002ac6:	d901      	bls.n	8002acc <HAL_RCC_OscConfig+0x438>
        {
          return HAL_TIMEOUT;
 8002ac8:	2303      	movs	r3, #3
 8002aca:	e1b7      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8002acc:	4b32      	ldr	r3, [pc, #200]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002ace:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002ad2:	f003 0302 	and.w	r3, r3, #2
 8002ad6:	2b00      	cmp	r3, #0
 8002ad8:	d1ef      	bne.n	8002aba <HAL_RCC_OscConfig+0x426>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8002ada:	687b      	ldr	r3, [r7, #4]
 8002adc:	681b      	ldr	r3, [r3, #0]
 8002ade:	f003 0304 	and.w	r3, r3, #4
 8002ae2:	2b00      	cmp	r3, #0
 8002ae4:	f000 80a6 	beq.w	8002c34 <HAL_RCC_OscConfig+0x5a0>
  {
    FlagStatus       pwrclkchanged = RESET;
 8002ae8:	2300      	movs	r3, #0
 8002aea:	77fb      	strb	r3, [r7, #31]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
 8002aec:	4b2a      	ldr	r3, [pc, #168]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002aee:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8002af0:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8002af4:	2b00      	cmp	r3, #0
 8002af6:	d10d      	bne.n	8002b14 <HAL_RCC_OscConfig+0x480>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8002af8:	4b27      	ldr	r3, [pc, #156]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002afa:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8002afc:	4a26      	ldr	r2, [pc, #152]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002afe:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8002b02:	6593      	str	r3, [r2, #88]	@ 0x58
 8002b04:	4b24      	ldr	r3, [pc, #144]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b06:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8002b08:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8002b0c:	60bb      	str	r3, [r7, #8]
 8002b0e:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8002b10:	2301      	movs	r3, #1
 8002b12:	77fb      	strb	r3, [r7, #31]
    }

    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8002b14:	4b21      	ldr	r3, [pc, #132]	@ (8002b9c <HAL_RCC_OscConfig+0x508>)
 8002b16:	681b      	ldr	r3, [r3, #0]
 8002b18:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8002b1c:	2b00      	cmp	r3, #0
 8002b1e:	d118      	bne.n	8002b52 <HAL_RCC_OscConfig+0x4be>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8002b20:	4b1e      	ldr	r3, [pc, #120]	@ (8002b9c <HAL_RCC_OscConfig+0x508>)
 8002b22:	681b      	ldr	r3, [r3, #0]
 8002b24:	4a1d      	ldr	r2, [pc, #116]	@ (8002b9c <HAL_RCC_OscConfig+0x508>)
 8002b26:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8002b2a:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8002b2c:	f7fe fdf2 	bl	8001714 <HAL_GetTick>
 8002b30:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8002b32:	e008      	b.n	8002b46 <HAL_RCC_OscConfig+0x4b2>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8002b34:	f7fe fdee 	bl	8001714 <HAL_GetTick>
 8002b38:	4602      	mov	r2, r0
 8002b3a:	693b      	ldr	r3, [r7, #16]
 8002b3c:	1ad3      	subs	r3, r2, r3
 8002b3e:	2b02      	cmp	r3, #2
 8002b40:	d901      	bls.n	8002b46 <HAL_RCC_OscConfig+0x4b2>
        {
          return HAL_TIMEOUT;
 8002b42:	2303      	movs	r3, #3
 8002b44:	e17a      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8002b46:	4b15      	ldr	r3, [pc, #84]	@ (8002b9c <HAL_RCC_OscConfig+0x508>)
 8002b48:	681b      	ldr	r3, [r3, #0]
 8002b4a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8002b4e:	2b00      	cmp	r3, #0
 8002b50:	d0f0      	beq.n	8002b34 <HAL_RCC_OscConfig+0x4a0>
    {
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
    }
#else
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8002b52:	687b      	ldr	r3, [r7, #4]
 8002b54:	689b      	ldr	r3, [r3, #8]
 8002b56:	2b01      	cmp	r3, #1
 8002b58:	d108      	bne.n	8002b6c <HAL_RCC_OscConfig+0x4d8>
 8002b5a:	4b0f      	ldr	r3, [pc, #60]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b5c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002b60:	4a0d      	ldr	r2, [pc, #52]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b62:	f043 0301 	orr.w	r3, r3, #1
 8002b66:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8002b6a:	e029      	b.n	8002bc0 <HAL_RCC_OscConfig+0x52c>
 8002b6c:	687b      	ldr	r3, [r7, #4]
 8002b6e:	689b      	ldr	r3, [r3, #8]
 8002b70:	2b05      	cmp	r3, #5
 8002b72:	d115      	bne.n	8002ba0 <HAL_RCC_OscConfig+0x50c>
 8002b74:	4b08      	ldr	r3, [pc, #32]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b76:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002b7a:	4a07      	ldr	r2, [pc, #28]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b7c:	f043 0304 	orr.w	r3, r3, #4
 8002b80:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8002b84:	4b04      	ldr	r3, [pc, #16]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b86:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002b8a:	4a03      	ldr	r2, [pc, #12]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b8c:	f043 0301 	orr.w	r3, r3, #1
 8002b90:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8002b94:	e014      	b.n	8002bc0 <HAL_RCC_OscConfig+0x52c>
 8002b96:	bf00      	nop
 8002b98:	40021000 	.word	0x40021000
 8002b9c:	40007000 	.word	0x40007000
 8002ba0:	4b9c      	ldr	r3, [pc, #624]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ba2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002ba6:	4a9b      	ldr	r2, [pc, #620]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ba8:	f023 0301 	bic.w	r3, r3, #1
 8002bac:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8002bb0:	4b98      	ldr	r3, [pc, #608]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002bb2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002bb6:	4a97      	ldr	r2, [pc, #604]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002bb8:	f023 0304 	bic.w	r3, r3, #4
 8002bbc:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
#endif /* RCC_BDCR_LSESYSDIS */

    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8002bc0:	687b      	ldr	r3, [r7, #4]
 8002bc2:	689b      	ldr	r3, [r3, #8]
 8002bc4:	2b00      	cmp	r3, #0
 8002bc6:	d016      	beq.n	8002bf6 <HAL_RCC_OscConfig+0x562>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002bc8:	f7fe fda4 	bl	8001714 <HAL_GetTick>
 8002bcc:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8002bce:	e00a      	b.n	8002be6 <HAL_RCC_OscConfig+0x552>
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8002bd0:	f7fe fda0 	bl	8001714 <HAL_GetTick>
 8002bd4:	4602      	mov	r2, r0
 8002bd6:	693b      	ldr	r3, [r7, #16]
 8002bd8:	1ad3      	subs	r3, r2, r3
 8002bda:	f241 3288 	movw	r2, #5000	@ 0x1388
 8002bde:	4293      	cmp	r3, r2
 8002be0:	d901      	bls.n	8002be6 <HAL_RCC_OscConfig+0x552>
        {
          return HAL_TIMEOUT;
 8002be2:	2303      	movs	r3, #3
 8002be4:	e12a      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8002be6:	4b8b      	ldr	r3, [pc, #556]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002be8:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002bec:	f003 0302 	and.w	r3, r3, #2
 8002bf0:	2b00      	cmp	r3, #0
 8002bf2:	d0ed      	beq.n	8002bd0 <HAL_RCC_OscConfig+0x53c>
 8002bf4:	e015      	b.n	8002c22 <HAL_RCC_OscConfig+0x58e>
      }
    }
    else
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002bf6:	f7fe fd8d 	bl	8001714 <HAL_GetTick>
 8002bfa:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is disabled */
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8002bfc:	e00a      	b.n	8002c14 <HAL_RCC_OscConfig+0x580>
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8002bfe:	f7fe fd89 	bl	8001714 <HAL_GetTick>
 8002c02:	4602      	mov	r2, r0
 8002c04:	693b      	ldr	r3, [r7, #16]
 8002c06:	1ad3      	subs	r3, r2, r3
 8002c08:	f241 3288 	movw	r2, #5000	@ 0x1388
 8002c0c:	4293      	cmp	r3, r2
 8002c0e:	d901      	bls.n	8002c14 <HAL_RCC_OscConfig+0x580>
        {
          return HAL_TIMEOUT;
 8002c10:	2303      	movs	r3, #3
 8002c12:	e113      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8002c14:	4b7f      	ldr	r3, [pc, #508]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002c16:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002c1a:	f003 0302 	and.w	r3, r3, #2
 8002c1e:	2b00      	cmp	r3, #0
 8002c20:	d1ed      	bne.n	8002bfe <HAL_RCC_OscConfig+0x56a>
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8002c22:	7ffb      	ldrb	r3, [r7, #31]
 8002c24:	2b01      	cmp	r3, #1
 8002c26:	d105      	bne.n	8002c34 <HAL_RCC_OscConfig+0x5a0>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8002c28:	4b7a      	ldr	r3, [pc, #488]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002c2a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8002c2c:	4a79      	ldr	r2, [pc, #484]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002c2e:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8002c32:	6593      	str	r3, [r2, #88]	@ 0x58
#endif /* RCC_HSI48_SUPPORT */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
 8002c34:	687b      	ldr	r3, [r7, #4]
 8002c36:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002c38:	2b00      	cmp	r3, #0
 8002c3a:	f000 80fe 	beq.w	8002e3a <HAL_RCC_OscConfig+0x7a6>
  {
    /* PLL On ? */
    if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
 8002c3e:	687b      	ldr	r3, [r7, #4]
 8002c40:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002c42:	2b02      	cmp	r3, #2
 8002c44:	f040 80d0 	bne.w	8002de8 <HAL_RCC_OscConfig+0x754>
#endif /* RCC_PLLP_SUPPORT */
      assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
      assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));

      /* Do nothing if PLL configuration is the unchanged */
      pll_config = RCC->PLLCFGR;
 8002c48:	4b72      	ldr	r3, [pc, #456]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002c4a:	68db      	ldr	r3, [r3, #12]
 8002c4c:	617b      	str	r3, [r7, #20]
      if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8002c4e:	697b      	ldr	r3, [r7, #20]
 8002c50:	f003 0203 	and.w	r2, r3, #3
 8002c54:	687b      	ldr	r3, [r7, #4]
 8002c56:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8002c58:	429a      	cmp	r2, r3
 8002c5a:	d130      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8002c5c:	697b      	ldr	r3, [r7, #20]
 8002c5e:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 8002c62:	687b      	ldr	r3, [r7, #4]
 8002c64:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8002c66:	3b01      	subs	r3, #1
 8002c68:	011b      	lsls	r3, r3, #4
      if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8002c6a:	429a      	cmp	r2, r3
 8002c6c:	d127      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8002c6e:	697b      	ldr	r3, [r7, #20]
 8002c70:	f403 42fe 	and.w	r2, r3, #32512	@ 0x7f00
 8002c74:	687b      	ldr	r3, [r7, #4]
 8002c76:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8002c78:	021b      	lsls	r3, r3, #8
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8002c7a:	429a      	cmp	r2, r3
 8002c7c:	d11f      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
#else
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
 8002c7e:	697b      	ldr	r3, [r7, #20]
 8002c80:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8002c84:	687a      	ldr	r2, [r7, #4]
 8002c86:	6b92      	ldr	r2, [r2, #56]	@ 0x38
 8002c88:	2a07      	cmp	r2, #7
 8002c8a:	bf14      	ite	ne
 8002c8c:	2201      	movne	r2, #1
 8002c8e:	2200      	moveq	r2, #0
 8002c90:	b2d2      	uxtb	r2, r2
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8002c92:	4293      	cmp	r3, r2
 8002c94:	d113      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
#endif
#endif
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8002c96:	697b      	ldr	r3, [r7, #20]
 8002c98:	f403 02c0 	and.w	r2, r3, #6291456	@ 0x600000
 8002c9c:	687b      	ldr	r3, [r7, #4]
 8002c9e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8002ca0:	085b      	lsrs	r3, r3, #1
 8002ca2:	3b01      	subs	r3, #1
 8002ca4:	055b      	lsls	r3, r3, #21
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
 8002ca6:	429a      	cmp	r2, r3
 8002ca8:	d109      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLR)    != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
 8002caa:	697b      	ldr	r3, [r7, #20]
 8002cac:	f003 62c0 	and.w	r2, r3, #100663296	@ 0x6000000
 8002cb0:	687b      	ldr	r3, [r7, #4]
 8002cb2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8002cb4:	085b      	lsrs	r3, r3, #1
 8002cb6:	3b01      	subs	r3, #1
 8002cb8:	065b      	lsls	r3, r3, #25
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8002cba:	429a      	cmp	r2, r3
 8002cbc:	d06e      	beq.n	8002d9c <HAL_RCC_OscConfig+0x708>
      {
        /* Check if the PLL is used as system clock or not */
        if(sysclk_source != RCC_CFGR_SWS_PLL)
 8002cbe:	69bb      	ldr	r3, [r7, #24]
 8002cc0:	2b0c      	cmp	r3, #12
 8002cc2:	d069      	beq.n	8002d98 <HAL_RCC_OscConfig+0x704>
        {
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
          /* Check if main PLL can be updated */
          /* Not possible if the source is shared by other enabled PLLSAIx */
          if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
 8002cc4:	4b53      	ldr	r3, [pc, #332]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002cc6:	681b      	ldr	r3, [r3, #0]
 8002cc8:	f003 6380 	and.w	r3, r3, #67108864	@ 0x4000000
 8002ccc:	2b00      	cmp	r3, #0
 8002cce:	d105      	bne.n	8002cdc <HAL_RCC_OscConfig+0x648>
#if defined(RCC_PLLSAI2_SUPPORT)
             || (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
 8002cd0:	4b50      	ldr	r3, [pc, #320]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002cd2:	681b      	ldr	r3, [r3, #0]
 8002cd4:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8002cd8:	2b00      	cmp	r3, #0
 8002cda:	d001      	beq.n	8002ce0 <HAL_RCC_OscConfig+0x64c>
#endif
            )
          {
            return HAL_ERROR;
 8002cdc:	2301      	movs	r3, #1
 8002cde:	e0ad      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
          }
          else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
          {
            /* Disable the main PLL. */
            __HAL_RCC_PLL_DISABLE();
 8002ce0:	4b4c      	ldr	r3, [pc, #304]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ce2:	681b      	ldr	r3, [r3, #0]
 8002ce4:	4a4b      	ldr	r2, [pc, #300]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ce6:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 8002cea:	6013      	str	r3, [r2, #0]

            /* Get Start Tick*/
            tickstart = HAL_GetTick();
 8002cec:	f7fe fd12 	bl	8001714 <HAL_GetTick>
 8002cf0:	6138      	str	r0, [r7, #16]

            /* Wait till PLL is ready */
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8002cf2:	e008      	b.n	8002d06 <HAL_RCC_OscConfig+0x672>
            {
              if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002cf4:	f7fe fd0e 	bl	8001714 <HAL_GetTick>
 8002cf8:	4602      	mov	r2, r0
 8002cfa:	693b      	ldr	r3, [r7, #16]
 8002cfc:	1ad3      	subs	r3, r2, r3
 8002cfe:	2b02      	cmp	r3, #2
 8002d00:	d901      	bls.n	8002d06 <HAL_RCC_OscConfig+0x672>
              {
                return HAL_TIMEOUT;
 8002d02:	2303      	movs	r3, #3
 8002d04:	e09a      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8002d06:	4b43      	ldr	r3, [pc, #268]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d08:	681b      	ldr	r3, [r3, #0]
 8002d0a:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002d0e:	2b00      	cmp	r3, #0
 8002d10:	d1f0      	bne.n	8002cf4 <HAL_RCC_OscConfig+0x660>
              }
            }

            /* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
            __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8002d12:	4b40      	ldr	r3, [pc, #256]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d14:	68da      	ldr	r2, [r3, #12]
 8002d16:	4b40      	ldr	r3, [pc, #256]	@ (8002e18 <HAL_RCC_OscConfig+0x784>)
 8002d18:	4013      	ands	r3, r2
 8002d1a:	687a      	ldr	r2, [r7, #4]
 8002d1c:	6ad1      	ldr	r1, [r2, #44]	@ 0x2c
 8002d1e:	687a      	ldr	r2, [r7, #4]
 8002d20:	6b12      	ldr	r2, [r2, #48]	@ 0x30
 8002d22:	3a01      	subs	r2, #1
 8002d24:	0112      	lsls	r2, r2, #4
 8002d26:	4311      	orrs	r1, r2
 8002d28:	687a      	ldr	r2, [r7, #4]
 8002d2a:	6b52      	ldr	r2, [r2, #52]	@ 0x34
 8002d2c:	0212      	lsls	r2, r2, #8
 8002d2e:	4311      	orrs	r1, r2
 8002d30:	687a      	ldr	r2, [r7, #4]
 8002d32:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
 8002d34:	0852      	lsrs	r2, r2, #1
 8002d36:	3a01      	subs	r2, #1
 8002d38:	0552      	lsls	r2, r2, #21
 8002d3a:	4311      	orrs	r1, r2
 8002d3c:	687a      	ldr	r2, [r7, #4]
 8002d3e:	6c12      	ldr	r2, [r2, #64]	@ 0x40
 8002d40:	0852      	lsrs	r2, r2, #1
 8002d42:	3a01      	subs	r2, #1
 8002d44:	0652      	lsls	r2, r2, #25
 8002d46:	4311      	orrs	r1, r2
 8002d48:	687a      	ldr	r2, [r7, #4]
 8002d4a:	6b92      	ldr	r2, [r2, #56]	@ 0x38
 8002d4c:	0912      	lsrs	r2, r2, #4
 8002d4e:	0452      	lsls	r2, r2, #17
 8002d50:	430a      	orrs	r2, r1
 8002d52:	4930      	ldr	r1, [pc, #192]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d54:	4313      	orrs	r3, r2
 8002d56:	60cb      	str	r3, [r1, #12]
                                 RCC_OscInitStruct->PLL.PLLQ,
                                 RCC_OscInitStruct->PLL.PLLR);
#endif

            /* Enable the main PLL. */
            __HAL_RCC_PLL_ENABLE();
 8002d58:	4b2e      	ldr	r3, [pc, #184]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d5a:	681b      	ldr	r3, [r3, #0]
 8002d5c:	4a2d      	ldr	r2, [pc, #180]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d5e:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8002d62:	6013      	str	r3, [r2, #0]

            /* Enable PLL System Clock output. */
            __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 8002d64:	4b2b      	ldr	r3, [pc, #172]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d66:	68db      	ldr	r3, [r3, #12]
 8002d68:	4a2a      	ldr	r2, [pc, #168]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d6a:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8002d6e:	60d3      	str	r3, [r2, #12]

            /* Get Start Tick*/
            tickstart = HAL_GetTick();
 8002d70:	f7fe fcd0 	bl	8001714 <HAL_GetTick>
 8002d74:	6138      	str	r0, [r7, #16]

            /* Wait till PLL is ready */
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002d76:	e008      	b.n	8002d8a <HAL_RCC_OscConfig+0x6f6>
            {
              if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002d78:	f7fe fccc 	bl	8001714 <HAL_GetTick>
 8002d7c:	4602      	mov	r2, r0
 8002d7e:	693b      	ldr	r3, [r7, #16]
 8002d80:	1ad3      	subs	r3, r2, r3
 8002d82:	2b02      	cmp	r3, #2
 8002d84:	d901      	bls.n	8002d8a <HAL_RCC_OscConfig+0x6f6>
              {
                return HAL_TIMEOUT;
 8002d86:	2303      	movs	r3, #3
 8002d88:	e058      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002d8a:	4b22      	ldr	r3, [pc, #136]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d8c:	681b      	ldr	r3, [r3, #0]
 8002d8e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002d92:	2b00      	cmp	r3, #0
 8002d94:	d0f0      	beq.n	8002d78 <HAL_RCC_OscConfig+0x6e4>
        if(sysclk_source != RCC_CFGR_SWS_PLL)
 8002d96:	e050      	b.n	8002e3a <HAL_RCC_OscConfig+0x7a6>
          }
        }
        else
        {
          /* PLL is already used as System core clock */
          return HAL_ERROR;
 8002d98:	2301      	movs	r3, #1
 8002d9a:	e04f      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
      else
      {
        /* PLL configuration is unchanged */
        /* Re-enable PLL if it was disabled (ie. low power mode) */
        if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002d9c:	4b1d      	ldr	r3, [pc, #116]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d9e:	681b      	ldr	r3, [r3, #0]
 8002da0:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002da4:	2b00      	cmp	r3, #0
 8002da6:	d148      	bne.n	8002e3a <HAL_RCC_OscConfig+0x7a6>
        {
          /* Enable the main PLL. */
          __HAL_RCC_PLL_ENABLE();
 8002da8:	4b1a      	ldr	r3, [pc, #104]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002daa:	681b      	ldr	r3, [r3, #0]
 8002dac:	4a19      	ldr	r2, [pc, #100]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002dae:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8002db2:	6013      	str	r3, [r2, #0]

          /* Enable PLL System Clock output. */
          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 8002db4:	4b17      	ldr	r3, [pc, #92]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002db6:	68db      	ldr	r3, [r3, #12]
 8002db8:	4a16      	ldr	r2, [pc, #88]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002dba:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8002dbe:	60d3      	str	r3, [r2, #12]

          /* Get Start Tick*/
          tickstart = HAL_GetTick();
 8002dc0:	f7fe fca8 	bl	8001714 <HAL_GetTick>
 8002dc4:	6138      	str	r0, [r7, #16]

          /* Wait till PLL is ready */
          while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002dc6:	e008      	b.n	8002dda <HAL_RCC_OscConfig+0x746>
          {
            if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002dc8:	f7fe fca4 	bl	8001714 <HAL_GetTick>
 8002dcc:	4602      	mov	r2, r0
 8002dce:	693b      	ldr	r3, [r7, #16]
 8002dd0:	1ad3      	subs	r3, r2, r3
 8002dd2:	2b02      	cmp	r3, #2
 8002dd4:	d901      	bls.n	8002dda <HAL_RCC_OscConfig+0x746>
            {
              return HAL_TIMEOUT;
 8002dd6:	2303      	movs	r3, #3
 8002dd8:	e030      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
          while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002dda:	4b0e      	ldr	r3, [pc, #56]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ddc:	681b      	ldr	r3, [r3, #0]
 8002dde:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002de2:	2b00      	cmp	r3, #0
 8002de4:	d0f0      	beq.n	8002dc8 <HAL_RCC_OscConfig+0x734>
 8002de6:	e028      	b.n	8002e3a <HAL_RCC_OscConfig+0x7a6>
      }
    }
    else
    {
      /* Check that PLL is not used as system clock or not */
      if(sysclk_source != RCC_CFGR_SWS_PLL)
 8002de8:	69bb      	ldr	r3, [r7, #24]
 8002dea:	2b0c      	cmp	r3, #12
 8002dec:	d023      	beq.n	8002e36 <HAL_RCC_OscConfig+0x7a2>
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8002dee:	4b09      	ldr	r3, [pc, #36]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002df0:	681b      	ldr	r3, [r3, #0]
 8002df2:	4a08      	ldr	r2, [pc, #32]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002df4:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 8002df8:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8002dfa:	f7fe fc8b 	bl	8001714 <HAL_GetTick>
 8002dfe:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8002e00:	e00c      	b.n	8002e1c <HAL_RCC_OscConfig+0x788>
        {
          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002e02:	f7fe fc87 	bl	8001714 <HAL_GetTick>
 8002e06:	4602      	mov	r2, r0
 8002e08:	693b      	ldr	r3, [r7, #16]
 8002e0a:	1ad3      	subs	r3, r2, r3
 8002e0c:	2b02      	cmp	r3, #2
 8002e0e:	d905      	bls.n	8002e1c <HAL_RCC_OscConfig+0x788>
          {
            return HAL_TIMEOUT;
 8002e10:	2303      	movs	r3, #3
 8002e12:	e013      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
 8002e14:	40021000 	.word	0x40021000
 8002e18:	f99d808c 	.word	0xf99d808c
        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8002e1c:	4b09      	ldr	r3, [pc, #36]	@ (8002e44 <HAL_RCC_OscConfig+0x7b0>)
 8002e1e:	681b      	ldr	r3, [r3, #0]
 8002e20:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002e24:	2b00      	cmp	r3, #0
 8002e26:	d1ec      	bne.n	8002e02 <HAL_RCC_OscConfig+0x76e>
          }
        }
        /* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
 8002e28:	4b06      	ldr	r3, [pc, #24]	@ (8002e44 <HAL_RCC_OscConfig+0x7b0>)
 8002e2a:	68da      	ldr	r2, [r3, #12]
 8002e2c:	4905      	ldr	r1, [pc, #20]	@ (8002e44 <HAL_RCC_OscConfig+0x7b0>)
 8002e2e:	4b06      	ldr	r3, [pc, #24]	@ (8002e48 <HAL_RCC_OscConfig+0x7b4>)
 8002e30:	4013      	ands	r3, r2
 8002e32:	60cb      	str	r3, [r1, #12]
 8002e34:	e001      	b.n	8002e3a <HAL_RCC_OscConfig+0x7a6>
#endif /* RCC_PLLSAI2_SUPPORT */
      }
      else
      {
        /* PLL is already used as System core clock */
        return HAL_ERROR;
 8002e36:	2301      	movs	r3, #1
 8002e38:	e000      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
    }
  }
  return HAL_OK;
 8002e3a:	2300      	movs	r3, #0
}
 8002e3c:	4618      	mov	r0, r3
 8002e3e:	3720      	adds	r7, #32
 8002e40:	46bd      	mov	sp, r7
 8002e42:	bd80      	pop	{r7, pc}
 8002e44:	40021000 	.word	0x40021000
 8002e48:	feeefffc 	.word	0xfeeefffc

08002e4c <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8002e4c:	b580      	push	{r7, lr}
 8002e4e:	b084      	sub	sp, #16
 8002e50:	af00      	add	r7, sp, #0
 8002e52:	6078      	str	r0, [r7, #4]
 8002e54:	6039      	str	r1, [r7, #0]
  uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
  HAL_StatusTypeDef status;

  /* Check Null pointer */
  if(RCC_ClkInitStruct == NULL)
 8002e56:	687b      	ldr	r3, [r7, #4]
 8002e58:	2b00      	cmp	r3, #0
 8002e5a:	d101      	bne.n	8002e60 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8002e5c:	2301      	movs	r3, #1
 8002e5e:	e0e7      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8002e60:	4b75      	ldr	r3, [pc, #468]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002e62:	681b      	ldr	r3, [r3, #0]
 8002e64:	f003 0307 	and.w	r3, r3, #7
 8002e68:	683a      	ldr	r2, [r7, #0]
 8002e6a:	429a      	cmp	r2, r3
 8002e6c:	d910      	bls.n	8002e90 <HAL_RCC_ClockConfig+0x44>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8002e6e:	4b72      	ldr	r3, [pc, #456]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002e70:	681b      	ldr	r3, [r3, #0]
 8002e72:	f023 0207 	bic.w	r2, r3, #7
 8002e76:	4970      	ldr	r1, [pc, #448]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002e78:	683b      	ldr	r3, [r7, #0]
 8002e7a:	4313      	orrs	r3, r2
 8002e7c:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8002e7e:	4b6e      	ldr	r3, [pc, #440]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002e80:	681b      	ldr	r3, [r3, #0]
 8002e82:	f003 0307 	and.w	r3, r3, #7
 8002e86:	683a      	ldr	r2, [r7, #0]
 8002e88:	429a      	cmp	r2, r3
 8002e8a:	d001      	beq.n	8002e90 <HAL_RCC_ClockConfig+0x44>
    {
      return HAL_ERROR;
 8002e8c:	2301      	movs	r3, #1
 8002e8e:	e0cf      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
    }
  }

  /*----------------- HCLK Configuration prior to SYSCLK----------------------*/
  /* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8002e90:	687b      	ldr	r3, [r7, #4]
 8002e92:	681b      	ldr	r3, [r3, #0]
 8002e94:	f003 0302 	and.w	r3, r3, #2
 8002e98:	2b00      	cmp	r3, #0
 8002e9a:	d010      	beq.n	8002ebe <HAL_RCC_ClockConfig+0x72>
  {
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));

    if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
 8002e9c:	687b      	ldr	r3, [r7, #4]
 8002e9e:	689a      	ldr	r2, [r3, #8]
 8002ea0:	4b66      	ldr	r3, [pc, #408]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002ea2:	689b      	ldr	r3, [r3, #8]
 8002ea4:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 8002ea8:	429a      	cmp	r2, r3
 8002eaa:	d908      	bls.n	8002ebe <HAL_RCC_ClockConfig+0x72>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8002eac:	4b63      	ldr	r3, [pc, #396]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002eae:	689b      	ldr	r3, [r3, #8]
 8002eb0:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8002eb4:	687b      	ldr	r3, [r7, #4]
 8002eb6:	689b      	ldr	r3, [r3, #8]
 8002eb8:	4960      	ldr	r1, [pc, #384]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002eba:	4313      	orrs	r3, r2
 8002ebc:	608b      	str	r3, [r1, #8]
    }
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8002ebe:	687b      	ldr	r3, [r7, #4]
 8002ec0:	681b      	ldr	r3, [r3, #0]
 8002ec2:	f003 0301 	and.w	r3, r3, #1
 8002ec6:	2b00      	cmp	r3, #0
 8002ec8:	d04c      	beq.n	8002f64 <HAL_RCC_ClockConfig+0x118>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* PLL is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8002eca:	687b      	ldr	r3, [r7, #4]
 8002ecc:	685b      	ldr	r3, [r3, #4]
 8002ece:	2b03      	cmp	r3, #3
 8002ed0:	d107      	bne.n	8002ee2 <HAL_RCC_ClockConfig+0x96>
    {
      /* Check the PLL ready flag */
      if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002ed2:	4b5a      	ldr	r3, [pc, #360]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002ed4:	681b      	ldr	r3, [r3, #0]
 8002ed6:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002eda:	2b00      	cmp	r3, #0
 8002edc:	d121      	bne.n	8002f22 <HAL_RCC_ClockConfig+0xd6>
      {
        return HAL_ERROR;
 8002ede:	2301      	movs	r3, #1
 8002ee0:	e0a6      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
#endif
    }
    else
    {
      /* HSE is selected as System Clock Source */
      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8002ee2:	687b      	ldr	r3, [r7, #4]
 8002ee4:	685b      	ldr	r3, [r3, #4]
 8002ee6:	2b02      	cmp	r3, #2
 8002ee8:	d107      	bne.n	8002efa <HAL_RCC_ClockConfig+0xae>
      {
        /* Check the HSE ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8002eea:	4b54      	ldr	r3, [pc, #336]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002eec:	681b      	ldr	r3, [r3, #0]
 8002eee:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8002ef2:	2b00      	cmp	r3, #0
 8002ef4:	d115      	bne.n	8002f22 <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8002ef6:	2301      	movs	r3, #1
 8002ef8:	e09a      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
        }
      }
      /* MSI is selected as System Clock Source */
      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
 8002efa:	687b      	ldr	r3, [r7, #4]
 8002efc:	685b      	ldr	r3, [r3, #4]
 8002efe:	2b00      	cmp	r3, #0
 8002f00:	d107      	bne.n	8002f12 <HAL_RCC_ClockConfig+0xc6>
      {
        /* Check the MSI ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 8002f02:	4b4e      	ldr	r3, [pc, #312]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f04:	681b      	ldr	r3, [r3, #0]
 8002f06:	f003 0302 	and.w	r3, r3, #2
 8002f0a:	2b00      	cmp	r3, #0
 8002f0c:	d109      	bne.n	8002f22 <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8002f0e:	2301      	movs	r3, #1
 8002f10:	e08e      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
      }
      /* HSI is selected as System Clock Source */
      else
      {
        /* Check the HSI ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8002f12:	4b4a      	ldr	r3, [pc, #296]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f14:	681b      	ldr	r3, [r3, #0]
 8002f16:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8002f1a:	2b00      	cmp	r3, #0
 8002f1c:	d101      	bne.n	8002f22 <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8002f1e:	2301      	movs	r3, #1
 8002f20:	e086      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
      }
#endif

    }

    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8002f22:	4b46      	ldr	r3, [pc, #280]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f24:	689b      	ldr	r3, [r3, #8]
 8002f26:	f023 0203 	bic.w	r2, r3, #3
 8002f2a:	687b      	ldr	r3, [r7, #4]
 8002f2c:	685b      	ldr	r3, [r3, #4]
 8002f2e:	4943      	ldr	r1, [pc, #268]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f30:	4313      	orrs	r3, r2
 8002f32:	608b      	str	r3, [r1, #8]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8002f34:	f7fe fbee 	bl	8001714 <HAL_GetTick>
 8002f38:	60f8      	str	r0, [r7, #12]

    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8002f3a:	e00a      	b.n	8002f52 <HAL_RCC_ClockConfig+0x106>
    {
      if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8002f3c:	f7fe fbea 	bl	8001714 <HAL_GetTick>
 8002f40:	4602      	mov	r2, r0
 8002f42:	68fb      	ldr	r3, [r7, #12]
 8002f44:	1ad3      	subs	r3, r2, r3
 8002f46:	f241 3288 	movw	r2, #5000	@ 0x1388
 8002f4a:	4293      	cmp	r3, r2
 8002f4c:	d901      	bls.n	8002f52 <HAL_RCC_ClockConfig+0x106>
      {
        return HAL_TIMEOUT;
 8002f4e:	2303      	movs	r3, #3
 8002f50:	e06e      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8002f52:	4b3a      	ldr	r3, [pc, #232]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f54:	689b      	ldr	r3, [r3, #8]
 8002f56:	f003 020c 	and.w	r2, r3, #12
 8002f5a:	687b      	ldr	r3, [r7, #4]
 8002f5c:	685b      	ldr	r3, [r3, #4]
 8002f5e:	009b      	lsls	r3, r3, #2
 8002f60:	429a      	cmp	r2, r3
 8002f62:	d1eb      	bne.n	8002f3c <HAL_RCC_ClockConfig+0xf0>
  }
#endif

  /*----------------- HCLK Configuration after SYSCLK-------------------------*/
  /* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8002f64:	687b      	ldr	r3, [r7, #4]
 8002f66:	681b      	ldr	r3, [r3, #0]
 8002f68:	f003 0302 	and.w	r3, r3, #2
 8002f6c:	2b00      	cmp	r3, #0
 8002f6e:	d010      	beq.n	8002f92 <HAL_RCC_ClockConfig+0x146>
  {
    if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
 8002f70:	687b      	ldr	r3, [r7, #4]
 8002f72:	689a      	ldr	r2, [r3, #8]
 8002f74:	4b31      	ldr	r3, [pc, #196]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f76:	689b      	ldr	r3, [r3, #8]
 8002f78:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 8002f7c:	429a      	cmp	r2, r3
 8002f7e:	d208      	bcs.n	8002f92 <HAL_RCC_ClockConfig+0x146>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8002f80:	4b2e      	ldr	r3, [pc, #184]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f82:	689b      	ldr	r3, [r3, #8]
 8002f84:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8002f88:	687b      	ldr	r3, [r7, #4]
 8002f8a:	689b      	ldr	r3, [r3, #8]
 8002f8c:	492b      	ldr	r1, [pc, #172]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f8e:	4313      	orrs	r3, r2
 8002f90:	608b      	str	r3, [r1, #8]
    }
  }

  /* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8002f92:	4b29      	ldr	r3, [pc, #164]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002f94:	681b      	ldr	r3, [r3, #0]
 8002f96:	f003 0307 	and.w	r3, r3, #7
 8002f9a:	683a      	ldr	r2, [r7, #0]
 8002f9c:	429a      	cmp	r2, r3
 8002f9e:	d210      	bcs.n	8002fc2 <HAL_RCC_ClockConfig+0x176>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8002fa0:	4b25      	ldr	r3, [pc, #148]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002fa2:	681b      	ldr	r3, [r3, #0]
 8002fa4:	f023 0207 	bic.w	r2, r3, #7
 8002fa8:	4923      	ldr	r1, [pc, #140]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002faa:	683b      	ldr	r3, [r7, #0]
 8002fac:	4313      	orrs	r3, r2
 8002fae:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8002fb0:	4b21      	ldr	r3, [pc, #132]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002fb2:	681b      	ldr	r3, [r3, #0]
 8002fb4:	f003 0307 	and.w	r3, r3, #7
 8002fb8:	683a      	ldr	r2, [r7, #0]
 8002fba:	429a      	cmp	r2, r3
 8002fbc:	d001      	beq.n	8002fc2 <HAL_RCC_ClockConfig+0x176>
    {
      return HAL_ERROR;
 8002fbe:	2301      	movs	r3, #1
 8002fc0:	e036      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8002fc2:	687b      	ldr	r3, [r7, #4]
 8002fc4:	681b      	ldr	r3, [r3, #0]
 8002fc6:	f003 0304 	and.w	r3, r3, #4
 8002fca:	2b00      	cmp	r3, #0
 8002fcc:	d008      	beq.n	8002fe0 <HAL_RCC_ClockConfig+0x194>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8002fce:	4b1b      	ldr	r3, [pc, #108]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002fd0:	689b      	ldr	r3, [r3, #8]
 8002fd2:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
 8002fd6:	687b      	ldr	r3, [r7, #4]
 8002fd8:	68db      	ldr	r3, [r3, #12]
 8002fda:	4918      	ldr	r1, [pc, #96]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002fdc:	4313      	orrs	r3, r2
 8002fde:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8002fe0:	687b      	ldr	r3, [r7, #4]
 8002fe2:	681b      	ldr	r3, [r3, #0]
 8002fe4:	f003 0308 	and.w	r3, r3, #8
 8002fe8:	2b00      	cmp	r3, #0
 8002fea:	d009      	beq.n	8003000 <HAL_RCC_ClockConfig+0x1b4>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8002fec:	4b13      	ldr	r3, [pc, #76]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002fee:	689b      	ldr	r3, [r3, #8]
 8002ff0:	f423 5260 	bic.w	r2, r3, #14336	@ 0x3800
 8002ff4:	687b      	ldr	r3, [r7, #4]
 8002ff6:	691b      	ldr	r3, [r3, #16]
 8002ff8:	00db      	lsls	r3, r3, #3
 8002ffa:	4910      	ldr	r1, [pc, #64]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002ffc:	4313      	orrs	r3, r2
 8002ffe:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 8003000:	f000 f824 	bl	800304c <HAL_RCC_GetSysClockFreq>
 8003004:	4602      	mov	r2, r0
 8003006:	4b0d      	ldr	r3, [pc, #52]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8003008:	689b      	ldr	r3, [r3, #8]
 800300a:	091b      	lsrs	r3, r3, #4
 800300c:	f003 030f 	and.w	r3, r3, #15
 8003010:	490b      	ldr	r1, [pc, #44]	@ (8003040 <HAL_RCC_ClockConfig+0x1f4>)
 8003012:	5ccb      	ldrb	r3, [r1, r3]
 8003014:	f003 031f 	and.w	r3, r3, #31
 8003018:	fa22 f303 	lsr.w	r3, r2, r3
 800301c:	4a09      	ldr	r2, [pc, #36]	@ (8003044 <HAL_RCC_ClockConfig+0x1f8>)
 800301e:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings*/
  status = HAL_InitTick(uwTickPrio);
 8003020:	4b09      	ldr	r3, [pc, #36]	@ (8003048 <HAL_RCC_ClockConfig+0x1fc>)
 8003022:	681b      	ldr	r3, [r3, #0]
 8003024:	4618      	mov	r0, r3
 8003026:	f7fe fa51 	bl	80014cc <HAL_InitTick>
 800302a:	4603      	mov	r3, r0
 800302c:	72fb      	strb	r3, [r7, #11]

  return status;
 800302e:	7afb      	ldrb	r3, [r7, #11]
}
 8003030:	4618      	mov	r0, r3
 8003032:	3710      	adds	r7, #16
 8003034:	46bd      	mov	sp, r7
 8003036:	bd80      	pop	{r7, pc}
 8003038:	40022000 	.word	0x40022000
 800303c:	40021000 	.word	0x40021000
 8003040:	08008200 	.word	0x08008200
 8003044:	20000004 	.word	0x20000004
 8003048:	20000008 	.word	0x20000008

0800304c <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 800304c:	b480      	push	{r7}
 800304e:	b089      	sub	sp, #36	@ 0x24
 8003050:	af00      	add	r7, sp, #0
  uint32_t msirange = 0U, sysclockfreq = 0U;
 8003052:	2300      	movs	r3, #0
 8003054:	61fb      	str	r3, [r7, #28]
 8003056:	2300      	movs	r3, #0
 8003058:	61bb      	str	r3, [r7, #24]
  uint32_t pllvco, pllsource, pllr, pllm;    /* no init needed */
  uint32_t sysclk_source, pll_oscsource;

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 800305a:	4b3e      	ldr	r3, [pc, #248]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 800305c:	689b      	ldr	r3, [r3, #8]
 800305e:	f003 030c 	and.w	r3, r3, #12
 8003062:	613b      	str	r3, [r7, #16]
  pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
 8003064:	4b3b      	ldr	r3, [pc, #236]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 8003066:	68db      	ldr	r3, [r3, #12]
 8003068:	f003 0303 	and.w	r3, r3, #3
 800306c:	60fb      	str	r3, [r7, #12]

  if((sysclk_source == RCC_CFGR_SWS_MSI) ||
 800306e:	693b      	ldr	r3, [r7, #16]
 8003070:	2b00      	cmp	r3, #0
 8003072:	d005      	beq.n	8003080 <HAL_RCC_GetSysClockFreq+0x34>
 8003074:	693b      	ldr	r3, [r7, #16]
 8003076:	2b0c      	cmp	r3, #12
 8003078:	d121      	bne.n	80030be <HAL_RCC_GetSysClockFreq+0x72>
     ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
 800307a:	68fb      	ldr	r3, [r7, #12]
 800307c:	2b01      	cmp	r3, #1
 800307e:	d11e      	bne.n	80030be <HAL_RCC_GetSysClockFreq+0x72>
  {
    /* MSI or PLL with MSI source used as system clock source */

    /* Get SYSCLK source */
    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
 8003080:	4b34      	ldr	r3, [pc, #208]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 8003082:	681b      	ldr	r3, [r3, #0]
 8003084:	f003 0308 	and.w	r3, r3, #8
 8003088:	2b00      	cmp	r3, #0
 800308a:	d107      	bne.n	800309c <HAL_RCC_GetSysClockFreq+0x50>
    { /* MSISRANGE from RCC_CSR applies */
      msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
 800308c:	4b31      	ldr	r3, [pc, #196]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 800308e:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8003092:	0a1b      	lsrs	r3, r3, #8
 8003094:	f003 030f 	and.w	r3, r3, #15
 8003098:	61fb      	str	r3, [r7, #28]
 800309a:	e005      	b.n	80030a8 <HAL_RCC_GetSysClockFreq+0x5c>
    }
    else
    { /* MSIRANGE from RCC_CR applies */
      msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
 800309c:	4b2d      	ldr	r3, [pc, #180]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 800309e:	681b      	ldr	r3, [r3, #0]
 80030a0:	091b      	lsrs	r3, r3, #4
 80030a2:	f003 030f 	and.w	r3, r3, #15
 80030a6:	61fb      	str	r3, [r7, #28]
    }
    /*MSI frequency range in HZ*/
    msirange = MSIRangeTable[msirange];
 80030a8:	4a2b      	ldr	r2, [pc, #172]	@ (8003158 <HAL_RCC_GetSysClockFreq+0x10c>)
 80030aa:	69fb      	ldr	r3, [r7, #28]
 80030ac:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 80030b0:	61fb      	str	r3, [r7, #28]

    if(sysclk_source == RCC_CFGR_SWS_MSI)
 80030b2:	693b      	ldr	r3, [r7, #16]
 80030b4:	2b00      	cmp	r3, #0
 80030b6:	d10d      	bne.n	80030d4 <HAL_RCC_GetSysClockFreq+0x88>
    {
      /* MSI used as system clock source */
      sysclockfreq = msirange;
 80030b8:	69fb      	ldr	r3, [r7, #28]
 80030ba:	61bb      	str	r3, [r7, #24]
    if(sysclk_source == RCC_CFGR_SWS_MSI)
 80030bc:	e00a      	b.n	80030d4 <HAL_RCC_GetSysClockFreq+0x88>
    }
  }
  else if(sysclk_source == RCC_CFGR_SWS_HSI)
 80030be:	693b      	ldr	r3, [r7, #16]
 80030c0:	2b04      	cmp	r3, #4
 80030c2:	d102      	bne.n	80030ca <HAL_RCC_GetSysClockFreq+0x7e>
  {
    /* HSI used as system clock source */
    sysclockfreq = HSI_VALUE;
 80030c4:	4b25      	ldr	r3, [pc, #148]	@ (800315c <HAL_RCC_GetSysClockFreq+0x110>)
 80030c6:	61bb      	str	r3, [r7, #24]
 80030c8:	e004      	b.n	80030d4 <HAL_RCC_GetSysClockFreq+0x88>
  }
  else if(sysclk_source == RCC_CFGR_SWS_HSE)
 80030ca:	693b      	ldr	r3, [r7, #16]
 80030cc:	2b08      	cmp	r3, #8
 80030ce:	d101      	bne.n	80030d4 <HAL_RCC_GetSysClockFreq+0x88>
  {
    /* HSE used as system clock source */
    sysclockfreq = HSE_VALUE;
 80030d0:	4b23      	ldr	r3, [pc, #140]	@ (8003160 <HAL_RCC_GetSysClockFreq+0x114>)
 80030d2:	61bb      	str	r3, [r7, #24]
  else
  {
    /* unexpected case: sysclockfreq at 0 */
  }

  if(sysclk_source == RCC_CFGR_SWS_PLL)
 80030d4:	693b      	ldr	r3, [r7, #16]
 80030d6:	2b0c      	cmp	r3, #12
 80030d8:	d134      	bne.n	8003144 <HAL_RCC_GetSysClockFreq+0xf8>
    /* PLL used as system clock  source */

    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
    SYSCLK = PLL_VCO / PLLR
    */
    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
 80030da:	4b1e      	ldr	r3, [pc, #120]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 80030dc:	68db      	ldr	r3, [r3, #12]
 80030de:	f003 0303 	and.w	r3, r3, #3
 80030e2:	60bb      	str	r3, [r7, #8]

    switch (pllsource)
 80030e4:	68bb      	ldr	r3, [r7, #8]
 80030e6:	2b02      	cmp	r3, #2
 80030e8:	d003      	beq.n	80030f2 <HAL_RCC_GetSysClockFreq+0xa6>
 80030ea:	68bb      	ldr	r3, [r7, #8]
 80030ec:	2b03      	cmp	r3, #3
 80030ee:	d003      	beq.n	80030f8 <HAL_RCC_GetSysClockFreq+0xac>
 80030f0:	e005      	b.n	80030fe <HAL_RCC_GetSysClockFreq+0xb2>
    {
    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
      pllvco = HSI_VALUE;
 80030f2:	4b1a      	ldr	r3, [pc, #104]	@ (800315c <HAL_RCC_GetSysClockFreq+0x110>)
 80030f4:	617b      	str	r3, [r7, #20]
      break;
 80030f6:	e005      	b.n	8003104 <HAL_RCC_GetSysClockFreq+0xb8>

    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
      pllvco = HSE_VALUE;
 80030f8:	4b19      	ldr	r3, [pc, #100]	@ (8003160 <HAL_RCC_GetSysClockFreq+0x114>)
 80030fa:	617b      	str	r3, [r7, #20]
      break;
 80030fc:	e002      	b.n	8003104 <HAL_RCC_GetSysClockFreq+0xb8>

    case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
    default:
      pllvco = msirange;
 80030fe:	69fb      	ldr	r3, [r7, #28]
 8003100:	617b      	str	r3, [r7, #20]
      break;
 8003102:	bf00      	nop
    }
    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 8003104:	4b13      	ldr	r3, [pc, #76]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 8003106:	68db      	ldr	r3, [r3, #12]
 8003108:	091b      	lsrs	r3, r3, #4
 800310a:	f003 0307 	and.w	r3, r3, #7
 800310e:	3301      	adds	r3, #1
 8003110:	607b      	str	r3, [r7, #4]
    pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
 8003112:	4b10      	ldr	r3, [pc, #64]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 8003114:	68db      	ldr	r3, [r3, #12]
 8003116:	0a1b      	lsrs	r3, r3, #8
 8003118:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800311c:	697a      	ldr	r2, [r7, #20]
 800311e:	fb03 f202 	mul.w	r2, r3, r2
 8003122:	687b      	ldr	r3, [r7, #4]
 8003124:	fbb2 f3f3 	udiv	r3, r2, r3
 8003128:	617b      	str	r3, [r7, #20]
    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 800312a:	4b0a      	ldr	r3, [pc, #40]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 800312c:	68db      	ldr	r3, [r3, #12]
 800312e:	0e5b      	lsrs	r3, r3, #25
 8003130:	f003 0303 	and.w	r3, r3, #3
 8003134:	3301      	adds	r3, #1
 8003136:	005b      	lsls	r3, r3, #1
 8003138:	603b      	str	r3, [r7, #0]
    sysclockfreq = pllvco / pllr;
 800313a:	697a      	ldr	r2, [r7, #20]
 800313c:	683b      	ldr	r3, [r7, #0]
 800313e:	fbb2 f3f3 	udiv	r3, r2, r3
 8003142:	61bb      	str	r3, [r7, #24]
  }

  return sysclockfreq;
 8003144:	69bb      	ldr	r3, [r7, #24]
}
 8003146:	4618      	mov	r0, r3
 8003148:	3724      	adds	r7, #36	@ 0x24
 800314a:	46bd      	mov	sp, r7
 800314c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003150:	4770      	bx	lr
 8003152:	bf00      	nop
 8003154:	40021000 	.word	0x40021000
 8003158:	08008218 	.word	0x08008218
 800315c:	00f42400 	.word	0x00f42400
 8003160:	007a1200 	.word	0x007a1200

08003164 <HAL_RCC_GetHCLKFreq>:
  *
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
  * @retval HCLK frequency in Hz
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 8003164:	b480      	push	{r7}
 8003166:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 8003168:	4b03      	ldr	r3, [pc, #12]	@ (8003178 <HAL_RCC_GetHCLKFreq+0x14>)
 800316a:	681b      	ldr	r3, [r3, #0]
}
 800316c:	4618      	mov	r0, r3
 800316e:	46bd      	mov	sp, r7
 8003170:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003174:	4770      	bx	lr
 8003176:	bf00      	nop
 8003178:	20000004 	.word	0x20000004

0800317c <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency in Hz
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 800317c:	b580      	push	{r7, lr}
 800317e:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
 8003180:	f7ff fff0 	bl	8003164 <HAL_RCC_GetHCLKFreq>
 8003184:	4602      	mov	r2, r0
 8003186:	4b06      	ldr	r3, [pc, #24]	@ (80031a0 <HAL_RCC_GetPCLK1Freq+0x24>)
 8003188:	689b      	ldr	r3, [r3, #8]
 800318a:	0a1b      	lsrs	r3, r3, #8
 800318c:	f003 0307 	and.w	r3, r3, #7
 8003190:	4904      	ldr	r1, [pc, #16]	@ (80031a4 <HAL_RCC_GetPCLK1Freq+0x28>)
 8003192:	5ccb      	ldrb	r3, [r1, r3]
 8003194:	f003 031f 	and.w	r3, r3, #31
 8003198:	fa22 f303 	lsr.w	r3, r2, r3
}
 800319c:	4618      	mov	r0, r3
 800319e:	bd80      	pop	{r7, pc}
 80031a0:	40021000 	.word	0x40021000
 80031a4:	08008210 	.word	0x08008210

080031a8 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency in Hz
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 80031a8:	b580      	push	{r7, lr}
 80031aa:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
 80031ac:	f7ff ffda 	bl	8003164 <HAL_RCC_GetHCLKFreq>
 80031b0:	4602      	mov	r2, r0
 80031b2:	4b06      	ldr	r3, [pc, #24]	@ (80031cc <HAL_RCC_GetPCLK2Freq+0x24>)
 80031b4:	689b      	ldr	r3, [r3, #8]
 80031b6:	0adb      	lsrs	r3, r3, #11
 80031b8:	f003 0307 	and.w	r3, r3, #7
 80031bc:	4904      	ldr	r1, [pc, #16]	@ (80031d0 <HAL_RCC_GetPCLK2Freq+0x28>)
 80031be:	5ccb      	ldrb	r3, [r1, r3]
 80031c0:	f003 031f 	and.w	r3, r3, #31
 80031c4:	fa22 f303 	lsr.w	r3, r2, r3
}
 80031c8:	4618      	mov	r0, r3
 80031ca:	bd80      	pop	{r7, pc}
 80031cc:	40021000 	.word	0x40021000
 80031d0:	08008210 	.word	0x08008210

080031d4 <HAL_RCC_GetClockConfig>:
  *         will be configured.
  * @param  pFLatency  Pointer on the Flash Latency.
  * @retval None
  */
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
{
 80031d4:	b480      	push	{r7}
 80031d6:	b083      	sub	sp, #12
 80031d8:	af00      	add	r7, sp, #0
 80031da:	6078      	str	r0, [r7, #4]
 80031dc:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(RCC_ClkInitStruct != (void  *)NULL);
  assert_param(pFLatency != (void *)NULL);

  /* Set all possible values for the Clock type parameter --------------------*/
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 80031de:	687b      	ldr	r3, [r7, #4]
 80031e0:	220f      	movs	r2, #15
 80031e2:	601a      	str	r2, [r3, #0]

  /* Get the SYSCLK configuration --------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
 80031e4:	4b12      	ldr	r3, [pc, #72]	@ (8003230 <HAL_RCC_GetClockConfig+0x5c>)
 80031e6:	689b      	ldr	r3, [r3, #8]
 80031e8:	f003 0203 	and.w	r2, r3, #3
 80031ec:	687b      	ldr	r3, [r7, #4]
 80031ee:	605a      	str	r2, [r3, #4]

  /* Get the HCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
 80031f0:	4b0f      	ldr	r3, [pc, #60]	@ (8003230 <HAL_RCC_GetClockConfig+0x5c>)
 80031f2:	689b      	ldr	r3, [r3, #8]
 80031f4:	f003 02f0 	and.w	r2, r3, #240	@ 0xf0
 80031f8:	687b      	ldr	r3, [r7, #4]
 80031fa:	609a      	str	r2, [r3, #8]

  /* Get the APB1 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
 80031fc:	4b0c      	ldr	r3, [pc, #48]	@ (8003230 <HAL_RCC_GetClockConfig+0x5c>)
 80031fe:	689b      	ldr	r3, [r3, #8]
 8003200:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 8003204:	687b      	ldr	r3, [r7, #4]
 8003206:	60da      	str	r2, [r3, #12]

  /* Get the APB2 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
 8003208:	4b09      	ldr	r3, [pc, #36]	@ (8003230 <HAL_RCC_GetClockConfig+0x5c>)
 800320a:	689b      	ldr	r3, [r3, #8]
 800320c:	08db      	lsrs	r3, r3, #3
 800320e:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 8003212:	687b      	ldr	r3, [r7, #4]
 8003214:	611a      	str	r2, [r3, #16]

  /* Get the Flash Wait State (Latency) configuration ------------------------*/
  *pFLatency = __HAL_FLASH_GET_LATENCY();
 8003216:	4b07      	ldr	r3, [pc, #28]	@ (8003234 <HAL_RCC_GetClockConfig+0x60>)
 8003218:	681b      	ldr	r3, [r3, #0]
 800321a:	f003 0207 	and.w	r2, r3, #7
 800321e:	683b      	ldr	r3, [r7, #0]
 8003220:	601a      	str	r2, [r3, #0]
}
 8003222:	bf00      	nop
 8003224:	370c      	adds	r7, #12
 8003226:	46bd      	mov	sp, r7
 8003228:	f85d 7b04 	ldr.w	r7, [sp], #4
 800322c:	4770      	bx	lr
 800322e:	bf00      	nop
 8003230:	40021000 	.word	0x40021000
 8003234:	40022000 	.word	0x40022000

08003238 <RCC_SetFlashLatencyFromMSIRange>:
            voltage range.
  * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
  * @retval HAL status
  */
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
 8003238:	b580      	push	{r7, lr}
 800323a:	b086      	sub	sp, #24
 800323c:	af00      	add	r7, sp, #0
 800323e:	6078      	str	r0, [r7, #4]
  uint32_t vos;
  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
 8003240:	2300      	movs	r3, #0
 8003242:	613b      	str	r3, [r7, #16]

  if(__HAL_RCC_PWR_IS_CLK_ENABLED())
 8003244:	4b2a      	ldr	r3, [pc, #168]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8003246:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003248:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 800324c:	2b00      	cmp	r3, #0
 800324e:	d003      	beq.n	8003258 <RCC_SetFlashLatencyFromMSIRange+0x20>
  {
    vos = HAL_PWREx_GetVoltageRange();
 8003250:	f7ff f8f0 	bl	8002434 <HAL_PWREx_GetVoltageRange>
 8003254:	6178      	str	r0, [r7, #20]
 8003256:	e014      	b.n	8003282 <RCC_SetFlashLatencyFromMSIRange+0x4a>
  }
  else
  {
    __HAL_RCC_PWR_CLK_ENABLE();
 8003258:	4b25      	ldr	r3, [pc, #148]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800325a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800325c:	4a24      	ldr	r2, [pc, #144]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800325e:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8003262:	6593      	str	r3, [r2, #88]	@ 0x58
 8003264:	4b22      	ldr	r3, [pc, #136]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8003266:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003268:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 800326c:	60fb      	str	r3, [r7, #12]
 800326e:	68fb      	ldr	r3, [r7, #12]
    vos = HAL_PWREx_GetVoltageRange();
 8003270:	f7ff f8e0 	bl	8002434 <HAL_PWREx_GetVoltageRange>
 8003274:	6178      	str	r0, [r7, #20]
    __HAL_RCC_PWR_CLK_DISABLE();
 8003276:	4b1e      	ldr	r3, [pc, #120]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8003278:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800327a:	4a1d      	ldr	r2, [pc, #116]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800327c:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8003280:	6593      	str	r3, [r2, #88]	@ 0x58
  }

  if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
 8003282:	697b      	ldr	r3, [r7, #20]
 8003284:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 8003288:	d10b      	bne.n	80032a2 <RCC_SetFlashLatencyFromMSIRange+0x6a>
  {
    if(msirange > RCC_MSIRANGE_8)
 800328a:	687b      	ldr	r3, [r7, #4]
 800328c:	2b80      	cmp	r3, #128	@ 0x80
 800328e:	d919      	bls.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
    {
      /* MSI > 16Mhz */
      if(msirange > RCC_MSIRANGE_10)
 8003290:	687b      	ldr	r3, [r7, #4]
 8003292:	2ba0      	cmp	r3, #160	@ 0xa0
 8003294:	d902      	bls.n	800329c <RCC_SetFlashLatencyFromMSIRange+0x64>
      {
        /* MSI 48Mhz */
        latency = FLASH_LATENCY_2; /* 2WS */
 8003296:	2302      	movs	r3, #2
 8003298:	613b      	str	r3, [r7, #16]
 800329a:	e013      	b.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      }
      else
      {
        /* MSI 24Mhz or 32Mhz */
        latency = FLASH_LATENCY_1; /* 1WS */
 800329c:	2301      	movs	r3, #1
 800329e:	613b      	str	r3, [r7, #16]
 80032a0:	e010      	b.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
        latency = FLASH_LATENCY_1; /* 1WS */
      }
      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
    }
#else
    if(msirange > RCC_MSIRANGE_8)
 80032a2:	687b      	ldr	r3, [r7, #4]
 80032a4:	2b80      	cmp	r3, #128	@ 0x80
 80032a6:	d902      	bls.n	80032ae <RCC_SetFlashLatencyFromMSIRange+0x76>
    {
      /* MSI > 16Mhz */
      latency = FLASH_LATENCY_3; /* 3WS */
 80032a8:	2303      	movs	r3, #3
 80032aa:	613b      	str	r3, [r7, #16]
 80032ac:	e00a      	b.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
    }
    else
    {
      if(msirange == RCC_MSIRANGE_8)
 80032ae:	687b      	ldr	r3, [r7, #4]
 80032b0:	2b80      	cmp	r3, #128	@ 0x80
 80032b2:	d102      	bne.n	80032ba <RCC_SetFlashLatencyFromMSIRange+0x82>
      {
        /* MSI 16Mhz */
        latency = FLASH_LATENCY_2; /* 2WS */
 80032b4:	2302      	movs	r3, #2
 80032b6:	613b      	str	r3, [r7, #16]
 80032b8:	e004      	b.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      }
      else if(msirange == RCC_MSIRANGE_7)
 80032ba:	687b      	ldr	r3, [r7, #4]
 80032bc:	2b70      	cmp	r3, #112	@ 0x70
 80032be:	d101      	bne.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      {
        /* MSI 8Mhz */
        latency = FLASH_LATENCY_1; /* 1WS */
 80032c0:	2301      	movs	r3, #1
 80032c2:	613b      	str	r3, [r7, #16]
      }
    }
#endif
  }

  __HAL_FLASH_SET_LATENCY(latency);
 80032c4:	4b0b      	ldr	r3, [pc, #44]	@ (80032f4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80032c6:	681b      	ldr	r3, [r3, #0]
 80032c8:	f023 0207 	bic.w	r2, r3, #7
 80032cc:	4909      	ldr	r1, [pc, #36]	@ (80032f4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80032ce:	693b      	ldr	r3, [r7, #16]
 80032d0:	4313      	orrs	r3, r2
 80032d2:	600b      	str	r3, [r1, #0]

  /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
  if(__HAL_FLASH_GET_LATENCY() != latency)
 80032d4:	4b07      	ldr	r3, [pc, #28]	@ (80032f4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80032d6:	681b      	ldr	r3, [r3, #0]
 80032d8:	f003 0307 	and.w	r3, r3, #7
 80032dc:	693a      	ldr	r2, [r7, #16]
 80032de:	429a      	cmp	r2, r3
 80032e0:	d001      	beq.n	80032e6 <RCC_SetFlashLatencyFromMSIRange+0xae>
  {
    return HAL_ERROR;
 80032e2:	2301      	movs	r3, #1
 80032e4:	e000      	b.n	80032e8 <RCC_SetFlashLatencyFromMSIRange+0xb0>
  }

  return HAL_OK;
 80032e6:	2300      	movs	r3, #0
}
 80032e8:	4618      	mov	r0, r3
 80032ea:	3718      	adds	r7, #24
 80032ec:	46bd      	mov	sp, r7
 80032ee:	bd80      	pop	{r7, pc}
 80032f0:	40021000 	.word	0x40021000
 80032f4:	40022000 	.word	0x40022000

080032f8 <HAL_RCCEx_PeriphCLKConfig>:
  *         the RTC clock source: in this case the access to Backup domain is enabled.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 80032f8:	b580      	push	{r7, lr}
 80032fa:	b086      	sub	sp, #24
 80032fc:	af00      	add	r7, sp, #0
 80032fe:	6078      	str	r0, [r7, #4]
  uint32_t tmpregister, tickstart;     /* no init needed */
  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
 8003300:	2300      	movs	r3, #0
 8003302:	74fb      	strb	r3, [r7, #19]
  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
 8003304:	2300      	movs	r3, #0
 8003306:	74bb      	strb	r3, [r7, #18]
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

#if defined(SAI1)

  /*-------------------------- SAI1 clock source configuration ---------------------*/
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
 8003308:	687b      	ldr	r3, [r7, #4]
 800330a:	681b      	ldr	r3, [r3, #0]
 800330c:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 8003310:	2b00      	cmp	r3, #0
 8003312:	d041      	beq.n	8003398 <HAL_RCCEx_PeriphCLKConfig+0xa0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));

    switch(PeriphClkInit->Sai1ClockSelection)
 8003314:	687b      	ldr	r3, [r7, #4]
 8003316:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8003318:	f5b3 0f40 	cmp.w	r3, #12582912	@ 0xc00000
 800331c:	d02a      	beq.n	8003374 <HAL_RCCEx_PeriphCLKConfig+0x7c>
 800331e:	f5b3 0f40 	cmp.w	r3, #12582912	@ 0xc00000
 8003322:	d824      	bhi.n	800336e <HAL_RCCEx_PeriphCLKConfig+0x76>
 8003324:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 8003328:	d008      	beq.n	800333c <HAL_RCCEx_PeriphCLKConfig+0x44>
 800332a:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800332e:	d81e      	bhi.n	800336e <HAL_RCCEx_PeriphCLKConfig+0x76>
 8003330:	2b00      	cmp	r3, #0
 8003332:	d00a      	beq.n	800334a <HAL_RCCEx_PeriphCLKConfig+0x52>
 8003334:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 8003338:	d010      	beq.n	800335c <HAL_RCCEx_PeriphCLKConfig+0x64>
 800333a:	e018      	b.n	800336e <HAL_RCCEx_PeriphCLKConfig+0x76>
    {
    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
      /* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
 800333c:	4b86      	ldr	r3, [pc, #536]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800333e:	68db      	ldr	r3, [r3, #12]
 8003340:	4a85      	ldr	r2, [pc, #532]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003342:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8003346:	60d3      	str	r3, [r2, #12]
#else
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
      /* SAI1 clock source config set later after clock selection check */
      break;
 8003348:	e015      	b.n	8003376 <HAL_RCCEx_PeriphCLKConfig+0x7e>

    case RCC_SAI1CLKSOURCE_PLLSAI1:  /* PLLSAI1 is used as clock source for SAI1*/
      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
 800334a:	687b      	ldr	r3, [r7, #4]
 800334c:	3304      	adds	r3, #4
 800334e:	2100      	movs	r1, #0
 8003350:	4618      	mov	r0, r3
 8003352:	f000 facb 	bl	80038ec <RCCEx_PLLSAI1_Config>
 8003356:	4603      	mov	r3, r0
 8003358:	74fb      	strb	r3, [r7, #19]
      /* SAI1 clock source config set later after clock selection check */
      break;
 800335a:	e00c      	b.n	8003376 <HAL_RCCEx_PeriphCLKConfig+0x7e>

#if defined(RCC_PLLSAI2_SUPPORT)

    case RCC_SAI1CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI1*/
      /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
 800335c:	687b      	ldr	r3, [r7, #4]
 800335e:	3320      	adds	r3, #32
 8003360:	2100      	movs	r1, #0
 8003362:	4618      	mov	r0, r3
 8003364:	f000 fbb6 	bl	8003ad4 <RCCEx_PLLSAI2_Config>
 8003368:	4603      	mov	r3, r0
 800336a:	74fb      	strb	r3, [r7, #19]
      /* SAI1 clock source config set later after clock selection check */
      break;
 800336c:	e003      	b.n	8003376 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
      /* SAI1 clock source config set later after clock selection check */
      break;

    default:
      ret = HAL_ERROR;
 800336e:	2301      	movs	r3, #1
 8003370:	74fb      	strb	r3, [r7, #19]
      break;
 8003372:	e000      	b.n	8003376 <HAL_RCCEx_PeriphCLKConfig+0x7e>
      break;
 8003374:	bf00      	nop
    }

    if(ret == HAL_OK)
 8003376:	7cfb      	ldrb	r3, [r7, #19]
 8003378:	2b00      	cmp	r3, #0
 800337a:	d10b      	bne.n	8003394 <HAL_RCCEx_PeriphCLKConfig+0x9c>
    {
      /* Set the source of SAI1 clock*/
      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
 800337c:	4b76      	ldr	r3, [pc, #472]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800337e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003382:	f423 0240 	bic.w	r2, r3, #12582912	@ 0xc00000
 8003386:	687b      	ldr	r3, [r7, #4]
 8003388:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 800338a:	4973      	ldr	r1, [pc, #460]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800338c:	4313      	orrs	r3, r2
 800338e:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
 8003392:	e001      	b.n	8003398 <HAL_RCCEx_PeriphCLKConfig+0xa0>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8003394:	7cfb      	ldrb	r3, [r7, #19]
 8003396:	74bb      	strb	r3, [r7, #18]
#endif /* SAI1 */

#if defined(SAI2)

  /*-------------------------- SAI2 clock source configuration ---------------------*/
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
 8003398:	687b      	ldr	r3, [r7, #4]
 800339a:	681b      	ldr	r3, [r3, #0]
 800339c:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 80033a0:	2b00      	cmp	r3, #0
 80033a2:	d041      	beq.n	8003428 <HAL_RCCEx_PeriphCLKConfig+0x130>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));

    switch(PeriphClkInit->Sai2ClockSelection)
 80033a4:	687b      	ldr	r3, [r7, #4]
 80033a6:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 80033a8:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 80033ac:	d02a      	beq.n	8003404 <HAL_RCCEx_PeriphCLKConfig+0x10c>
 80033ae:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 80033b2:	d824      	bhi.n	80033fe <HAL_RCCEx_PeriphCLKConfig+0x106>
 80033b4:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 80033b8:	d008      	beq.n	80033cc <HAL_RCCEx_PeriphCLKConfig+0xd4>
 80033ba:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 80033be:	d81e      	bhi.n	80033fe <HAL_RCCEx_PeriphCLKConfig+0x106>
 80033c0:	2b00      	cmp	r3, #0
 80033c2:	d00a      	beq.n	80033da <HAL_RCCEx_PeriphCLKConfig+0xe2>
 80033c4:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 80033c8:	d010      	beq.n	80033ec <HAL_RCCEx_PeriphCLKConfig+0xf4>
 80033ca:	e018      	b.n	80033fe <HAL_RCCEx_PeriphCLKConfig+0x106>
    {
    case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
      /* Enable SAI Clock output generated from System PLL . */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
 80033cc:	4b62      	ldr	r3, [pc, #392]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80033ce:	68db      	ldr	r3, [r3, #12]
 80033d0:	4a61      	ldr	r2, [pc, #388]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80033d2:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80033d6:	60d3      	str	r3, [r2, #12]
      /* SAI2 clock source config set later after clock selection check */
      break;
 80033d8:	e015      	b.n	8003406 <HAL_RCCEx_PeriphCLKConfig+0x10e>

    case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
 80033da:	687b      	ldr	r3, [r7, #4]
 80033dc:	3304      	adds	r3, #4
 80033de:	2100      	movs	r1, #0
 80033e0:	4618      	mov	r0, r3
 80033e2:	f000 fa83 	bl	80038ec <RCCEx_PLLSAI1_Config>
 80033e6:	4603      	mov	r3, r0
 80033e8:	74fb      	strb	r3, [r7, #19]
      /* SAI2 clock source config set later after clock selection check */
      break;
 80033ea:	e00c      	b.n	8003406 <HAL_RCCEx_PeriphCLKConfig+0x10e>

    case RCC_SAI2CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI2*/
      /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
 80033ec:	687b      	ldr	r3, [r7, #4]
 80033ee:	3320      	adds	r3, #32
 80033f0:	2100      	movs	r1, #0
 80033f2:	4618      	mov	r0, r3
 80033f4:	f000 fb6e 	bl	8003ad4 <RCCEx_PLLSAI2_Config>
 80033f8:	4603      	mov	r3, r0
 80033fa:	74fb      	strb	r3, [r7, #19]
      /* SAI2 clock source config set later after clock selection check */
      break;
 80033fc:	e003      	b.n	8003406 <HAL_RCCEx_PeriphCLKConfig+0x10e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
      /* SAI2 clock source config set later after clock selection check */
      break;

    default:
      ret = HAL_ERROR;
 80033fe:	2301      	movs	r3, #1
 8003400:	74fb      	strb	r3, [r7, #19]
      break;
 8003402:	e000      	b.n	8003406 <HAL_RCCEx_PeriphCLKConfig+0x10e>
      break;
 8003404:	bf00      	nop
    }

    if(ret == HAL_OK)
 8003406:	7cfb      	ldrb	r3, [r7, #19]
 8003408:	2b00      	cmp	r3, #0
 800340a:	d10b      	bne.n	8003424 <HAL_RCCEx_PeriphCLKConfig+0x12c>
    {
      /* Set the source of SAI2 clock*/
      __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
 800340c:	4b52      	ldr	r3, [pc, #328]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800340e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003412:	f023 7240 	bic.w	r2, r3, #50331648	@ 0x3000000
 8003416:	687b      	ldr	r3, [r7, #4]
 8003418:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 800341a:	494f      	ldr	r1, [pc, #316]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800341c:	4313      	orrs	r3, r2
 800341e:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
 8003422:	e001      	b.n	8003428 <HAL_RCCEx_PeriphCLKConfig+0x130>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8003424:	7cfb      	ldrb	r3, [r7, #19]
 8003426:	74bb      	strb	r3, [r7, #18]
    }
  }
#endif /* SAI2 */

  /*-------------------------- RTC clock source configuration ----------------------*/
  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 8003428:	687b      	ldr	r3, [r7, #4]
 800342a:	681b      	ldr	r3, [r3, #0]
 800342c:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8003430:	2b00      	cmp	r3, #0
 8003432:	f000 80a0 	beq.w	8003576 <HAL_RCCEx_PeriphCLKConfig+0x27e>
  {
    FlagStatus       pwrclkchanged = RESET;
 8003436:	2300      	movs	r3, #0
 8003438:	747b      	strb	r3, [r7, #17]

    /* Check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    /* Enable Power Clock */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
 800343a:	4b47      	ldr	r3, [pc, #284]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800343c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800343e:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8003442:	2b00      	cmp	r3, #0
 8003444:	d101      	bne.n	800344a <HAL_RCCEx_PeriphCLKConfig+0x152>
 8003446:	2301      	movs	r3, #1
 8003448:	e000      	b.n	800344c <HAL_RCCEx_PeriphCLKConfig+0x154>
 800344a:	2300      	movs	r3, #0
 800344c:	2b00      	cmp	r3, #0
 800344e:	d00d      	beq.n	800346c <HAL_RCCEx_PeriphCLKConfig+0x174>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8003450:	4b41      	ldr	r3, [pc, #260]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003452:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003454:	4a40      	ldr	r2, [pc, #256]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003456:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 800345a:	6593      	str	r3, [r2, #88]	@ 0x58
 800345c:	4b3e      	ldr	r3, [pc, #248]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800345e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003460:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8003464:	60bb      	str	r3, [r7, #8]
 8003466:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8003468:	2301      	movs	r3, #1
 800346a:	747b      	strb	r3, [r7, #17]
    }

    /* Enable write access to Backup domain */
    SET_BIT(PWR->CR1, PWR_CR1_DBP);
 800346c:	4b3b      	ldr	r3, [pc, #236]	@ (800355c <HAL_RCCEx_PeriphCLKConfig+0x264>)
 800346e:	681b      	ldr	r3, [r3, #0]
 8003470:	4a3a      	ldr	r2, [pc, #232]	@ (800355c <HAL_RCCEx_PeriphCLKConfig+0x264>)
 8003472:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8003476:	6013      	str	r3, [r2, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 8003478:	f7fe f94c 	bl	8001714 <HAL_GetTick>
 800347c:	60f8      	str	r0, [r7, #12]

    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
 800347e:	e009      	b.n	8003494 <HAL_RCCEx_PeriphCLKConfig+0x19c>
    {
      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8003480:	f7fe f948 	bl	8001714 <HAL_GetTick>
 8003484:	4602      	mov	r2, r0
 8003486:	68fb      	ldr	r3, [r7, #12]
 8003488:	1ad3      	subs	r3, r2, r3
 800348a:	2b02      	cmp	r3, #2
 800348c:	d902      	bls.n	8003494 <HAL_RCCEx_PeriphCLKConfig+0x19c>
      {
        ret = HAL_TIMEOUT;
 800348e:	2303      	movs	r3, #3
 8003490:	74fb      	strb	r3, [r7, #19]
        break;
 8003492:	e005      	b.n	80034a0 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
 8003494:	4b31      	ldr	r3, [pc, #196]	@ (800355c <HAL_RCCEx_PeriphCLKConfig+0x264>)
 8003496:	681b      	ldr	r3, [r3, #0]
 8003498:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800349c:	2b00      	cmp	r3, #0
 800349e:	d0ef      	beq.n	8003480 <HAL_RCCEx_PeriphCLKConfig+0x188>
      }
    }

    if(ret == HAL_OK)
 80034a0:	7cfb      	ldrb	r3, [r7, #19]
 80034a2:	2b00      	cmp	r3, #0
 80034a4:	d15c      	bne.n	8003560 <HAL_RCCEx_PeriphCLKConfig+0x268>
    {
      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
 80034a6:	4b2c      	ldr	r3, [pc, #176]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034a8:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80034ac:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 80034b0:	617b      	str	r3, [r7, #20]

      if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
 80034b2:	697b      	ldr	r3, [r7, #20]
 80034b4:	2b00      	cmp	r3, #0
 80034b6:	d01f      	beq.n	80034f8 <HAL_RCCEx_PeriphCLKConfig+0x200>
 80034b8:	687b      	ldr	r3, [r7, #4]
 80034ba:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 80034be:	697a      	ldr	r2, [r7, #20]
 80034c0:	429a      	cmp	r2, r3
 80034c2:	d019      	beq.n	80034f8 <HAL_RCCEx_PeriphCLKConfig+0x200>
      {
        /* Store the content of BDCR register before the reset of Backup Domain */
        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
 80034c4:	4b24      	ldr	r3, [pc, #144]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034c6:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80034ca:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 80034ce:	617b      	str	r3, [r7, #20]
        /* RTC Clock selection can be changed only if the Backup Domain is reset */
        __HAL_RCC_BACKUPRESET_FORCE();
 80034d0:	4b21      	ldr	r3, [pc, #132]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034d2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80034d6:	4a20      	ldr	r2, [pc, #128]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034d8:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80034dc:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
        __HAL_RCC_BACKUPRESET_RELEASE();
 80034e0:	4b1d      	ldr	r3, [pc, #116]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034e2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80034e6:	4a1c      	ldr	r2, [pc, #112]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034e8:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 80034ec:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
        /* Restore the Content of BDCR register */
        RCC->BDCR = tmpregister;
 80034f0:	4a19      	ldr	r2, [pc, #100]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034f2:	697b      	ldr	r3, [r7, #20]
 80034f4:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
      }

      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
 80034f8:	697b      	ldr	r3, [r7, #20]
 80034fa:	f003 0301 	and.w	r3, r3, #1
 80034fe:	2b00      	cmp	r3, #0
 8003500:	d016      	beq.n	8003530 <HAL_RCCEx_PeriphCLKConfig+0x238>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8003502:	f7fe f907 	bl	8001714 <HAL_GetTick>
 8003506:	60f8      	str	r0, [r7, #12]

        /* Wait till LSE is ready */
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8003508:	e00b      	b.n	8003522 <HAL_RCCEx_PeriphCLKConfig+0x22a>
        {
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800350a:	f7fe f903 	bl	8001714 <HAL_GetTick>
 800350e:	4602      	mov	r2, r0
 8003510:	68fb      	ldr	r3, [r7, #12]
 8003512:	1ad3      	subs	r3, r2, r3
 8003514:	f241 3288 	movw	r2, #5000	@ 0x1388
 8003518:	4293      	cmp	r3, r2
 800351a:	d902      	bls.n	8003522 <HAL_RCCEx_PeriphCLKConfig+0x22a>
          {
            ret = HAL_TIMEOUT;
 800351c:	2303      	movs	r3, #3
 800351e:	74fb      	strb	r3, [r7, #19]
            break;
 8003520:	e006      	b.n	8003530 <HAL_RCCEx_PeriphCLKConfig+0x238>
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8003522:	4b0d      	ldr	r3, [pc, #52]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003524:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8003528:	f003 0302 	and.w	r3, r3, #2
 800352c:	2b00      	cmp	r3, #0
 800352e:	d0ec      	beq.n	800350a <HAL_RCCEx_PeriphCLKConfig+0x212>
          }
        }
      }

      if(ret == HAL_OK)
 8003530:	7cfb      	ldrb	r3, [r7, #19]
 8003532:	2b00      	cmp	r3, #0
 8003534:	d10c      	bne.n	8003550 <HAL_RCCEx_PeriphCLKConfig+0x258>
      {
        /* Apply new RTC clock source selection */
        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 8003536:	4b08      	ldr	r3, [pc, #32]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003538:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800353c:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 8003540:	687b      	ldr	r3, [r7, #4]
 8003542:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 8003546:	4904      	ldr	r1, [pc, #16]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003548:	4313      	orrs	r3, r2
 800354a:	f8c1 3090 	str.w	r3, [r1, #144]	@ 0x90
 800354e:	e009      	b.n	8003564 <HAL_RCCEx_PeriphCLKConfig+0x26c>
      }
      else
      {
        /* set overall return value */
        status = ret;
 8003550:	7cfb      	ldrb	r3, [r7, #19]
 8003552:	74bb      	strb	r3, [r7, #18]
 8003554:	e006      	b.n	8003564 <HAL_RCCEx_PeriphCLKConfig+0x26c>
 8003556:	bf00      	nop
 8003558:	40021000 	.word	0x40021000
 800355c:	40007000 	.word	0x40007000
      }
    }
    else
    {
      /* set overall return value */
      status = ret;
 8003560:	7cfb      	ldrb	r3, [r7, #19]
 8003562:	74bb      	strb	r3, [r7, #18]
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8003564:	7c7b      	ldrb	r3, [r7, #17]
 8003566:	2b01      	cmp	r3, #1
 8003568:	d105      	bne.n	8003576 <HAL_RCCEx_PeriphCLKConfig+0x27e>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 800356a:	4b9e      	ldr	r3, [pc, #632]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800356c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800356e:	4a9d      	ldr	r2, [pc, #628]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003570:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8003574:	6593      	str	r3, [r2, #88]	@ 0x58
    }
  }

  /*-------------------------- USART1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
 8003576:	687b      	ldr	r3, [r7, #4]
 8003578:	681b      	ldr	r3, [r3, #0]
 800357a:	f003 0301 	and.w	r3, r3, #1
 800357e:	2b00      	cmp	r3, #0
 8003580:	d00a      	beq.n	8003598 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));

    /* Configure the USART1 clock source */
    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
 8003582:	4b98      	ldr	r3, [pc, #608]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003584:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003588:	f023 0203 	bic.w	r2, r3, #3
 800358c:	687b      	ldr	r3, [r7, #4]
 800358e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8003590:	4994      	ldr	r1, [pc, #592]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003592:	4313      	orrs	r3, r2
 8003594:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- USART2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
 8003598:	687b      	ldr	r3, [r7, #4]
 800359a:	681b      	ldr	r3, [r3, #0]
 800359c:	f003 0302 	and.w	r3, r3, #2
 80035a0:	2b00      	cmp	r3, #0
 80035a2:	d00a      	beq.n	80035ba <HAL_RCCEx_PeriphCLKConfig+0x2c2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));

    /* Configure the USART2 clock source */
    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
 80035a4:	4b8f      	ldr	r3, [pc, #572]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035a6:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80035aa:	f023 020c 	bic.w	r2, r3, #12
 80035ae:	687b      	ldr	r3, [r7, #4]
 80035b0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80035b2:	498c      	ldr	r1, [pc, #560]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035b4:	4313      	orrs	r3, r2
 80035b6:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#if defined(USART3)

  /*-------------------------- USART3 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
 80035ba:	687b      	ldr	r3, [r7, #4]
 80035bc:	681b      	ldr	r3, [r3, #0]
 80035be:	f003 0304 	and.w	r3, r3, #4
 80035c2:	2b00      	cmp	r3, #0
 80035c4:	d00a      	beq.n	80035dc <HAL_RCCEx_PeriphCLKConfig+0x2e4>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));

    /* Configure the USART3 clock source */
    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
 80035c6:	4b87      	ldr	r3, [pc, #540]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035c8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80035cc:	f023 0230 	bic.w	r2, r3, #48	@ 0x30
 80035d0:	687b      	ldr	r3, [r7, #4]
 80035d2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80035d4:	4983      	ldr	r1, [pc, #524]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035d6:	4313      	orrs	r3, r2
 80035d8:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* USART3 */

#if defined(UART4)

  /*-------------------------- UART4 clock source configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
 80035dc:	687b      	ldr	r3, [r7, #4]
 80035de:	681b      	ldr	r3, [r3, #0]
 80035e0:	f003 0308 	and.w	r3, r3, #8
 80035e4:	2b00      	cmp	r3, #0
 80035e6:	d00a      	beq.n	80035fe <HAL_RCCEx_PeriphCLKConfig+0x306>
  {
    /* Check the parameters */
    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));

    /* Configure the UART4 clock source */
    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
 80035e8:	4b7e      	ldr	r3, [pc, #504]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035ea:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80035ee:	f023 02c0 	bic.w	r2, r3, #192	@ 0xc0
 80035f2:	687b      	ldr	r3, [r7, #4]
 80035f4:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80035f6:	497b      	ldr	r1, [pc, #492]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035f8:	4313      	orrs	r3, r2
 80035fa:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* UART4 */

#if defined(UART5)

  /*-------------------------- UART5 clock source configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
 80035fe:	687b      	ldr	r3, [r7, #4]
 8003600:	681b      	ldr	r3, [r3, #0]
 8003602:	f003 0310 	and.w	r3, r3, #16
 8003606:	2b00      	cmp	r3, #0
 8003608:	d00a      	beq.n	8003620 <HAL_RCCEx_PeriphCLKConfig+0x328>
  {
    /* Check the parameters */
    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));

    /* Configure the UART5 clock source */
    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
 800360a:	4b76      	ldr	r3, [pc, #472]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800360c:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003610:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 8003614:	687b      	ldr	r3, [r7, #4]
 8003616:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8003618:	4972      	ldr	r1, [pc, #456]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800361a:	4313      	orrs	r3, r2
 800361c:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#endif /* UART5 */

  /*-------------------------- LPUART1 clock source configuration ------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
 8003620:	687b      	ldr	r3, [r7, #4]
 8003622:	681b      	ldr	r3, [r3, #0]
 8003624:	f003 0320 	and.w	r3, r3, #32
 8003628:	2b00      	cmp	r3, #0
 800362a:	d00a      	beq.n	8003642 <HAL_RCCEx_PeriphCLKConfig+0x34a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));

    /* Configure the LPUART1 clock source */
    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
 800362c:	4b6d      	ldr	r3, [pc, #436]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800362e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003632:	f423 6240 	bic.w	r2, r3, #3072	@ 0xc00
 8003636:	687b      	ldr	r3, [r7, #4]
 8003638:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800363a:	496a      	ldr	r1, [pc, #424]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800363c:	4313      	orrs	r3, r2
 800363e:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- LPTIM1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
 8003642:	687b      	ldr	r3, [r7, #4]
 8003644:	681b      	ldr	r3, [r3, #0]
 8003646:	f403 7300 	and.w	r3, r3, #512	@ 0x200
 800364a:	2b00      	cmp	r3, #0
 800364c:	d00a      	beq.n	8003664 <HAL_RCCEx_PeriphCLKConfig+0x36c>
  {
    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
 800364e:	4b65      	ldr	r3, [pc, #404]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003650:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003654:	f423 2240 	bic.w	r2, r3, #786432	@ 0xc0000
 8003658:	687b      	ldr	r3, [r7, #4]
 800365a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800365c:	4961      	ldr	r1, [pc, #388]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800365e:	4313      	orrs	r3, r2
 8003660:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- LPTIM2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
 8003664:	687b      	ldr	r3, [r7, #4]
 8003666:	681b      	ldr	r3, [r3, #0]
 8003668:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 800366c:	2b00      	cmp	r3, #0
 800366e:	d00a      	beq.n	8003686 <HAL_RCCEx_PeriphCLKConfig+0x38e>
  {
    assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
 8003670:	4b5c      	ldr	r3, [pc, #368]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003672:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003676:	f423 1240 	bic.w	r2, r3, #3145728	@ 0x300000
 800367a:	687b      	ldr	r3, [r7, #4]
 800367c:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800367e:	4959      	ldr	r1, [pc, #356]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003680:	4313      	orrs	r3, r2
 8003682:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- I2C1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
 8003686:	687b      	ldr	r3, [r7, #4]
 8003688:	681b      	ldr	r3, [r3, #0]
 800368a:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800368e:	2b00      	cmp	r3, #0
 8003690:	d00a      	beq.n	80036a8 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));

    /* Configure the I2C1 clock source */
    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
 8003692:	4b54      	ldr	r3, [pc, #336]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003694:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003698:	f423 5240 	bic.w	r2, r3, #12288	@ 0x3000
 800369c:	687b      	ldr	r3, [r7, #4]
 800369e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80036a0:	4950      	ldr	r1, [pc, #320]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036a2:	4313      	orrs	r3, r2
 80036a4:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#if defined(I2C2)

  /*-------------------------- I2C2 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
 80036a8:	687b      	ldr	r3, [r7, #4]
 80036aa:	681b      	ldr	r3, [r3, #0]
 80036ac:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80036b0:	2b00      	cmp	r3, #0
 80036b2:	d00a      	beq.n	80036ca <HAL_RCCEx_PeriphCLKConfig+0x3d2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));

    /* Configure the I2C2 clock source */
    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
 80036b4:	4b4b      	ldr	r3, [pc, #300]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036b6:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80036ba:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
 80036be:	687b      	ldr	r3, [r7, #4]
 80036c0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80036c2:	4948      	ldr	r1, [pc, #288]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036c4:	4313      	orrs	r3, r2
 80036c6:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#endif /* I2C2 */

  /*-------------------------- I2C3 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
 80036ca:	687b      	ldr	r3, [r7, #4]
 80036cc:	681b      	ldr	r3, [r3, #0]
 80036ce:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 80036d2:	2b00      	cmp	r3, #0
 80036d4:	d00a      	beq.n	80036ec <HAL_RCCEx_PeriphCLKConfig+0x3f4>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));

    /* Configure the I2C3 clock source */
    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
 80036d6:	4b43      	ldr	r3, [pc, #268]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036d8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80036dc:	f423 3240 	bic.w	r2, r3, #196608	@ 0x30000
 80036e0:	687b      	ldr	r3, [r7, #4]
 80036e2:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80036e4:	493f      	ldr	r1, [pc, #252]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036e6:	4313      	orrs	r3, r2
 80036e8:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* I2C4 */

#if defined(USB_OTG_FS) || defined(USB)

  /*-------------------------- USB clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
 80036ec:	687b      	ldr	r3, [r7, #4]
 80036ee:	681b      	ldr	r3, [r3, #0]
 80036f0:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 80036f4:	2b00      	cmp	r3, #0
 80036f6:	d028      	beq.n	800374a <HAL_RCCEx_PeriphCLKConfig+0x452>
  {
    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 80036f8:	4b3a      	ldr	r3, [pc, #232]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036fa:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80036fe:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 8003702:	687b      	ldr	r3, [r7, #4]
 8003704:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8003706:	4937      	ldr	r1, [pc, #220]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003708:	4313      	orrs	r3, r2
 800370a:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
 800370e:	687b      	ldr	r3, [r7, #4]
 8003710:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8003712:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 8003716:	d106      	bne.n	8003726 <HAL_RCCEx_PeriphCLKConfig+0x42e>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8003718:	4b32      	ldr	r3, [pc, #200]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800371a:	68db      	ldr	r3, [r3, #12]
 800371c:	4a31      	ldr	r2, [pc, #196]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800371e:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 8003722:	60d3      	str	r3, [r2, #12]
 8003724:	e011      	b.n	800374a <HAL_RCCEx_PeriphCLKConfig+0x452>
    }
    else
    {
#if defined(RCC_PLLSAI1_SUPPORT)
      if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
 8003726:	687b      	ldr	r3, [r7, #4]
 8003728:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800372a:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800372e:	d10c      	bne.n	800374a <HAL_RCCEx_PeriphCLKConfig+0x452>
      {
        /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
        ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 8003730:	687b      	ldr	r3, [r7, #4]
 8003732:	3304      	adds	r3, #4
 8003734:	2101      	movs	r1, #1
 8003736:	4618      	mov	r0, r3
 8003738:	f000 f8d8 	bl	80038ec <RCCEx_PLLSAI1_Config>
 800373c:	4603      	mov	r3, r0
 800373e:	74fb      	strb	r3, [r7, #19]

        if(ret != HAL_OK)
 8003740:	7cfb      	ldrb	r3, [r7, #19]
 8003742:	2b00      	cmp	r3, #0
 8003744:	d001      	beq.n	800374a <HAL_RCCEx_PeriphCLKConfig+0x452>
        {
          /* set overall return value */
          status = ret;
 8003746:	7cfb      	ldrb	r3, [r7, #19]
 8003748:	74bb      	strb	r3, [r7, #18]
#endif /* USB_OTG_FS || USB */

#if defined(SDMMC1)

  /*-------------------------- SDMMC1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
 800374a:	687b      	ldr	r3, [r7, #4]
 800374c:	681b      	ldr	r3, [r3, #0]
 800374e:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 8003752:	2b00      	cmp	r3, #0
 8003754:	d028      	beq.n	80037a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
  {
    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
 8003756:	4b23      	ldr	r3, [pc, #140]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003758:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800375c:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 8003760:	687b      	ldr	r3, [r7, #4]
 8003762:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8003764:	491f      	ldr	r1, [pc, #124]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003766:	4313      	orrs	r3, r2
 8003768:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)   /* PLL "Q" ? */
 800376c:	687b      	ldr	r3, [r7, #4]
 800376e:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8003770:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 8003774:	d106      	bne.n	8003784 <HAL_RCCEx_PeriphCLKConfig+0x48c>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8003776:	4b1b      	ldr	r3, [pc, #108]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003778:	68db      	ldr	r3, [r3, #12]
 800377a:	4a1a      	ldr	r2, [pc, #104]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800377c:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 8003780:	60d3      	str	r3, [r2, #12]
 8003782:	e011      	b.n	80037a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
    {
      /* Enable PLLSAI3CLK output */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
    }
#endif
    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
 8003784:	687b      	ldr	r3, [r7, #4]
 8003786:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8003788:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800378c:	d10c      	bne.n	80037a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
    {
      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 800378e:	687b      	ldr	r3, [r7, #4]
 8003790:	3304      	adds	r3, #4
 8003792:	2101      	movs	r1, #1
 8003794:	4618      	mov	r0, r3
 8003796:	f000 f8a9 	bl	80038ec <RCCEx_PLLSAI1_Config>
 800379a:	4603      	mov	r3, r0
 800379c:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 800379e:	7cfb      	ldrb	r3, [r7, #19]
 80037a0:	2b00      	cmp	r3, #0
 80037a2:	d001      	beq.n	80037a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
      {
        /* set overall return value */
        status = ret;
 80037a4:	7cfb      	ldrb	r3, [r7, #19]
 80037a6:	74bb      	strb	r3, [r7, #18]
  }

#endif /* SDMMC1 */

  /*-------------------------- RNG clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
 80037a8:	687b      	ldr	r3, [r7, #4]
 80037aa:	681b      	ldr	r3, [r3, #0]
 80037ac:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 80037b0:	2b00      	cmp	r3, #0
 80037b2:	d02b      	beq.n	800380c <HAL_RCCEx_PeriphCLKConfig+0x514>
  {
    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
 80037b4:	4b0b      	ldr	r3, [pc, #44]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80037b6:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80037ba:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 80037be:	687b      	ldr	r3, [r7, #4]
 80037c0:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80037c2:	4908      	ldr	r1, [pc, #32]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80037c4:	4313      	orrs	r3, r2
 80037c6:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
 80037ca:	687b      	ldr	r3, [r7, #4]
 80037cc:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80037ce:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 80037d2:	d109      	bne.n	80037e8 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 80037d4:	4b03      	ldr	r3, [pc, #12]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80037d6:	68db      	ldr	r3, [r3, #12]
 80037d8:	4a02      	ldr	r2, [pc, #8]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80037da:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 80037de:	60d3      	str	r3, [r2, #12]
 80037e0:	e014      	b.n	800380c <HAL_RCCEx_PeriphCLKConfig+0x514>
 80037e2:	bf00      	nop
 80037e4:	40021000 	.word	0x40021000
    }
#if defined(RCC_PLLSAI1_SUPPORT)
    else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
 80037e8:	687b      	ldr	r3, [r7, #4]
 80037ea:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80037ec:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 80037f0:	d10c      	bne.n	800380c <HAL_RCCEx_PeriphCLKConfig+0x514>
    {
      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 80037f2:	687b      	ldr	r3, [r7, #4]
 80037f4:	3304      	adds	r3, #4
 80037f6:	2101      	movs	r1, #1
 80037f8:	4618      	mov	r0, r3
 80037fa:	f000 f877 	bl	80038ec <RCCEx_PLLSAI1_Config>
 80037fe:	4603      	mov	r3, r0
 8003800:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 8003802:	7cfb      	ldrb	r3, [r7, #19]
 8003804:	2b00      	cmp	r3, #0
 8003806:	d001      	beq.n	800380c <HAL_RCCEx_PeriphCLKConfig+0x514>
      {
        /* set overall return value */
        status = ret;
 8003808:	7cfb      	ldrb	r3, [r7, #19]
 800380a:	74bb      	strb	r3, [r7, #18]
    }
  }

  /*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 800380c:	687b      	ldr	r3, [r7, #4]
 800380e:	681b      	ldr	r3, [r3, #0]
 8003810:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 8003814:	2b00      	cmp	r3, #0
 8003816:	d02f      	beq.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC interface clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 8003818:	4b2b      	ldr	r3, [pc, #172]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 800381a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800381e:	f023 5240 	bic.w	r2, r3, #805306368	@ 0x30000000
 8003822:	687b      	ldr	r3, [r7, #4]
 8003824:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 8003826:	4928      	ldr	r1, [pc, #160]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8003828:	4313      	orrs	r3, r2
 800382a:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

#if defined(RCC_PLLSAI1_SUPPORT)
    if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
 800382e:	687b      	ldr	r3, [r7, #4]
 8003830:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 8003832:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 8003836:	d10d      	bne.n	8003854 <HAL_RCCEx_PeriphCLKConfig+0x55c>
    {
      /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
 8003838:	687b      	ldr	r3, [r7, #4]
 800383a:	3304      	adds	r3, #4
 800383c:	2102      	movs	r1, #2
 800383e:	4618      	mov	r0, r3
 8003840:	f000 f854 	bl	80038ec <RCCEx_PLLSAI1_Config>
 8003844:	4603      	mov	r3, r0
 8003846:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 8003848:	7cfb      	ldrb	r3, [r7, #19]
 800384a:	2b00      	cmp	r3, #0
 800384c:	d014      	beq.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
      {
        /* set overall return value */
        status = ret;
 800384e:	7cfb      	ldrb	r3, [r7, #19]
 8003850:	74bb      	strb	r3, [r7, #18]
 8003852:	e011      	b.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
    }
#endif /* RCC_PLLSAI1_SUPPORT */

#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)

    else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
 8003854:	687b      	ldr	r3, [r7, #4]
 8003856:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 8003858:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800385c:	d10c      	bne.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
    {
      /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
 800385e:	687b      	ldr	r3, [r7, #4]
 8003860:	3320      	adds	r3, #32
 8003862:	2102      	movs	r1, #2
 8003864:	4618      	mov	r0, r3
 8003866:	f000 f935 	bl	8003ad4 <RCCEx_PLLSAI2_Config>
 800386a:	4603      	mov	r3, r0
 800386c:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 800386e:	7cfb      	ldrb	r3, [r7, #19]
 8003870:	2b00      	cmp	r3, #0
 8003872:	d001      	beq.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
      {
        /* set overall return value */
        status = ret;
 8003874:	7cfb      	ldrb	r3, [r7, #19]
 8003876:	74bb      	strb	r3, [r7, #18]
#endif /* !STM32L412xx && !STM32L422xx */

#if defined(SWPMI1)

  /*-------------------------- SWPMI1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
 8003878:	687b      	ldr	r3, [r7, #4]
 800387a:	681b      	ldr	r3, [r3, #0]
 800387c:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8003880:	2b00      	cmp	r3, #0
 8003882:	d00a      	beq.n	800389a <HAL_RCCEx_PeriphCLKConfig+0x5a2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));

    /* Configure the SWPMI1 clock source */
    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
 8003884:	4b10      	ldr	r3, [pc, #64]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8003886:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800388a:	f023 4280 	bic.w	r2, r3, #1073741824	@ 0x40000000
 800388e:	687b      	ldr	r3, [r7, #4]
 8003890:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 8003892:	490d      	ldr	r1, [pc, #52]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8003894:	4313      	orrs	r3, r2
 8003896:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* SWPMI1 */

#if defined(DFSDM1_Filter0)

  /*-------------------------- DFSDM1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
 800389a:	687b      	ldr	r3, [r7, #4]
 800389c:	681b      	ldr	r3, [r3, #0]
 800389e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 80038a2:	2b00      	cmp	r3, #0
 80038a4:	d00b      	beq.n	80038be <HAL_RCCEx_PeriphCLKConfig+0x5c6>
  {
    /* Check the parameters */
    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));

    /* Configure the DFSDM1 interface clock source */
    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
 80038a6:	4b08      	ldr	r3, [pc, #32]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 80038a8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80038ac:	f023 4200 	bic.w	r2, r3, #2147483648	@ 0x80000000
 80038b0:	687b      	ldr	r3, [r7, #4]
 80038b2:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 80038b6:	4904      	ldr	r1, [pc, #16]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 80038b8:	4313      	orrs	r3, r2
 80038ba:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
    }
  }

#endif /* OCTOSPI1 || OCTOSPI2 */

  return status;
 80038be:	7cbb      	ldrb	r3, [r7, #18]
}
 80038c0:	4618      	mov	r0, r3
 80038c2:	3718      	adds	r7, #24
 80038c4:	46bd      	mov	sp, r7
 80038c6:	bd80      	pop	{r7, pc}
 80038c8:	40021000 	.word	0x40021000

080038cc <HAL_RCCEx_EnableMSIPLLMode>:
  * @note   Prior to enable the PLL-mode of the MSI for automatic hardware
  *         calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
  * @retval None
  */
void HAL_RCCEx_EnableMSIPLLMode(void)
{
 80038cc:	b480      	push	{r7}
 80038ce:	af00      	add	r7, sp, #0
  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
 80038d0:	4b05      	ldr	r3, [pc, #20]	@ (80038e8 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
 80038d2:	681b      	ldr	r3, [r3, #0]
 80038d4:	4a04      	ldr	r2, [pc, #16]	@ (80038e8 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
 80038d6:	f043 0304 	orr.w	r3, r3, #4
 80038da:	6013      	str	r3, [r2, #0]
}
 80038dc:	bf00      	nop
 80038de:	46bd      	mov	sp, r7
 80038e0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80038e4:	4770      	bx	lr
 80038e6:	bf00      	nop
 80038e8:	40021000 	.word	0x40021000

080038ec <RCCEx_PLLSAI1_Config>:
  * @note   PLLSAI1 is temporary disable to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
 80038ec:	b580      	push	{r7, lr}
 80038ee:	b084      	sub	sp, #16
 80038f0:	af00      	add	r7, sp, #0
 80038f2:	6078      	str	r0, [r7, #4]
 80038f4:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 80038f6:	2300      	movs	r3, #0
 80038f8:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));

  /* Check that PLLSAI1 clock source and divider M can be applied */
  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
 80038fa:	4b75      	ldr	r3, [pc, #468]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80038fc:	68db      	ldr	r3, [r3, #12]
 80038fe:	f003 0303 	and.w	r3, r3, #3
 8003902:	2b00      	cmp	r3, #0
 8003904:	d018      	beq.n	8003938 <RCCEx_PLLSAI1_Config+0x4c>
  {
    /* PLL clock source and divider M already set, check that no request for change  */
    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
 8003906:	4b72      	ldr	r3, [pc, #456]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003908:	68db      	ldr	r3, [r3, #12]
 800390a:	f003 0203 	and.w	r2, r3, #3
 800390e:	687b      	ldr	r3, [r7, #4]
 8003910:	681b      	ldr	r3, [r3, #0]
 8003912:	429a      	cmp	r2, r3
 8003914:	d10d      	bne.n	8003932 <RCCEx_PLLSAI1_Config+0x46>
       ||
       (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
 8003916:	687b      	ldr	r3, [r7, #4]
 8003918:	681b      	ldr	r3, [r3, #0]
       ||
 800391a:	2b00      	cmp	r3, #0
 800391c:	d009      	beq.n	8003932 <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
       ||
       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
 800391e:	4b6c      	ldr	r3, [pc, #432]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003920:	68db      	ldr	r3, [r3, #12]
 8003922:	091b      	lsrs	r3, r3, #4
 8003924:	f003 0307 	and.w	r3, r3, #7
 8003928:	1c5a      	adds	r2, r3, #1
 800392a:	687b      	ldr	r3, [r7, #4]
 800392c:	685b      	ldr	r3, [r3, #4]
       ||
 800392e:	429a      	cmp	r2, r3
 8003930:	d047      	beq.n	80039c2 <RCCEx_PLLSAI1_Config+0xd6>
#endif
      )
    {
      status = HAL_ERROR;
 8003932:	2301      	movs	r3, #1
 8003934:	73fb      	strb	r3, [r7, #15]
 8003936:	e044      	b.n	80039c2 <RCCEx_PLLSAI1_Config+0xd6>
    }
  }
  else
  {
    /* Check PLLSAI1 clock source availability */
    switch(PllSai1->PLLSAI1Source)
 8003938:	687b      	ldr	r3, [r7, #4]
 800393a:	681b      	ldr	r3, [r3, #0]
 800393c:	2b03      	cmp	r3, #3
 800393e:	d018      	beq.n	8003972 <RCCEx_PLLSAI1_Config+0x86>
 8003940:	2b03      	cmp	r3, #3
 8003942:	d825      	bhi.n	8003990 <RCCEx_PLLSAI1_Config+0xa4>
 8003944:	2b01      	cmp	r3, #1
 8003946:	d002      	beq.n	800394e <RCCEx_PLLSAI1_Config+0x62>
 8003948:	2b02      	cmp	r3, #2
 800394a:	d009      	beq.n	8003960 <RCCEx_PLLSAI1_Config+0x74>
 800394c:	e020      	b.n	8003990 <RCCEx_PLLSAI1_Config+0xa4>
    {
    case RCC_PLLSOURCE_MSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
 800394e:	4b60      	ldr	r3, [pc, #384]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003950:	681b      	ldr	r3, [r3, #0]
 8003952:	f003 0302 	and.w	r3, r3, #2
 8003956:	2b00      	cmp	r3, #0
 8003958:	d11d      	bne.n	8003996 <RCCEx_PLLSAI1_Config+0xaa>
      {
        status = HAL_ERROR;
 800395a:	2301      	movs	r3, #1
 800395c:	73fb      	strb	r3, [r7, #15]
      }
      break;
 800395e:	e01a      	b.n	8003996 <RCCEx_PLLSAI1_Config+0xaa>
    case RCC_PLLSOURCE_HSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
 8003960:	4b5b      	ldr	r3, [pc, #364]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003962:	681b      	ldr	r3, [r3, #0]
 8003964:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8003968:	2b00      	cmp	r3, #0
 800396a:	d116      	bne.n	800399a <RCCEx_PLLSAI1_Config+0xae>
      {
        status = HAL_ERROR;
 800396c:	2301      	movs	r3, #1
 800396e:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8003970:	e013      	b.n	800399a <RCCEx_PLLSAI1_Config+0xae>
    case RCC_PLLSOURCE_HSE:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
 8003972:	4b57      	ldr	r3, [pc, #348]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003974:	681b      	ldr	r3, [r3, #0]
 8003976:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800397a:	2b00      	cmp	r3, #0
 800397c:	d10f      	bne.n	800399e <RCCEx_PLLSAI1_Config+0xb2>
      {
        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
 800397e:	4b54      	ldr	r3, [pc, #336]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003980:	681b      	ldr	r3, [r3, #0]
 8003982:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 8003986:	2b00      	cmp	r3, #0
 8003988:	d109      	bne.n	800399e <RCCEx_PLLSAI1_Config+0xb2>
        {
          status = HAL_ERROR;
 800398a:	2301      	movs	r3, #1
 800398c:	73fb      	strb	r3, [r7, #15]
        }
      }
      break;
 800398e:	e006      	b.n	800399e <RCCEx_PLLSAI1_Config+0xb2>
    default:
      status = HAL_ERROR;
 8003990:	2301      	movs	r3, #1
 8003992:	73fb      	strb	r3, [r7, #15]
      break;
 8003994:	e004      	b.n	80039a0 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 8003996:	bf00      	nop
 8003998:	e002      	b.n	80039a0 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 800399a:	bf00      	nop
 800399c:	e000      	b.n	80039a0 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 800399e:	bf00      	nop
    }

    if(status == HAL_OK)
 80039a0:	7bfb      	ldrb	r3, [r7, #15]
 80039a2:	2b00      	cmp	r3, #0
 80039a4:	d10d      	bne.n	80039c2 <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
      /* Set PLLSAI1 clock source */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
      /* Set PLLSAI1 clock source and divider M */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
 80039a6:	4b4a      	ldr	r3, [pc, #296]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039a8:	68db      	ldr	r3, [r3, #12]
 80039aa:	f023 0273 	bic.w	r2, r3, #115	@ 0x73
 80039ae:	687b      	ldr	r3, [r7, #4]
 80039b0:	6819      	ldr	r1, [r3, #0]
 80039b2:	687b      	ldr	r3, [r7, #4]
 80039b4:	685b      	ldr	r3, [r3, #4]
 80039b6:	3b01      	subs	r3, #1
 80039b8:	011b      	lsls	r3, r3, #4
 80039ba:	430b      	orrs	r3, r1
 80039bc:	4944      	ldr	r1, [pc, #272]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039be:	4313      	orrs	r3, r2
 80039c0:	60cb      	str	r3, [r1, #12]
#endif
    }
  }

  if(status == HAL_OK)
 80039c2:	7bfb      	ldrb	r3, [r7, #15]
 80039c4:	2b00      	cmp	r3, #0
 80039c6:	d17d      	bne.n	8003ac4 <RCCEx_PLLSAI1_Config+0x1d8>
  {
    /* Disable the PLLSAI1 */
    __HAL_RCC_PLLSAI1_DISABLE();
 80039c8:	4b41      	ldr	r3, [pc, #260]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039ca:	681b      	ldr	r3, [r3, #0]
 80039cc:	4a40      	ldr	r2, [pc, #256]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039ce:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 80039d2:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 80039d4:	f7fd fe9e 	bl	8001714 <HAL_GetTick>
 80039d8:	60b8      	str	r0, [r7, #8]

    /* Wait till PLLSAI1 is ready to be updated */
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
 80039da:	e009      	b.n	80039f0 <RCCEx_PLLSAI1_Config+0x104>
    {
      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
 80039dc:	f7fd fe9a 	bl	8001714 <HAL_GetTick>
 80039e0:	4602      	mov	r2, r0
 80039e2:	68bb      	ldr	r3, [r7, #8]
 80039e4:	1ad3      	subs	r3, r2, r3
 80039e6:	2b02      	cmp	r3, #2
 80039e8:	d902      	bls.n	80039f0 <RCCEx_PLLSAI1_Config+0x104>
      {
        status = HAL_TIMEOUT;
 80039ea:	2303      	movs	r3, #3
 80039ec:	73fb      	strb	r3, [r7, #15]
        break;
 80039ee:	e005      	b.n	80039fc <RCCEx_PLLSAI1_Config+0x110>
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
 80039f0:	4b37      	ldr	r3, [pc, #220]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039f2:	681b      	ldr	r3, [r3, #0]
 80039f4:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 80039f8:	2b00      	cmp	r3, #0
 80039fa:	d1ef      	bne.n	80039dc <RCCEx_PLLSAI1_Config+0xf0>
      }
    }

    if(status == HAL_OK)
 80039fc:	7bfb      	ldrb	r3, [r7, #15]
 80039fe:	2b00      	cmp	r3, #0
 8003a00:	d160      	bne.n	8003ac4 <RCCEx_PLLSAI1_Config+0x1d8>
    {
      if(Divider == DIVIDER_P_UPDATE)
 8003a02:	683b      	ldr	r3, [r7, #0]
 8003a04:	2b00      	cmp	r3, #0
 8003a06:	d111      	bne.n	8003a2c <RCCEx_PLLSAI1_Config+0x140>
        MODIFY_REG(RCC->PLLSAI1CFGR,
                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
#else
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8003a08:	4b31      	ldr	r3, [pc, #196]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a0a:	691b      	ldr	r3, [r3, #16]
 8003a0c:	f423 331f 	bic.w	r3, r3, #162816	@ 0x27c00
 8003a10:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8003a14:	687a      	ldr	r2, [r7, #4]
 8003a16:	6892      	ldr	r2, [r2, #8]
 8003a18:	0211      	lsls	r1, r2, #8
 8003a1a:	687a      	ldr	r2, [r7, #4]
 8003a1c:	68d2      	ldr	r2, [r2, #12]
 8003a1e:	0912      	lsrs	r2, r2, #4
 8003a20:	0452      	lsls	r2, r2, #17
 8003a22:	430a      	orrs	r2, r1
 8003a24:	492a      	ldr	r1, [pc, #168]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a26:	4313      	orrs	r3, r2
 8003a28:	610b      	str	r3, [r1, #16]
 8003a2a:	e027      	b.n	8003a7c <RCCEx_PLLSAI1_Config+0x190>
                   ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */

#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
      }
      else if(Divider == DIVIDER_Q_UPDATE)
 8003a2c:	683b      	ldr	r3, [r7, #0]
 8003a2e:	2b01      	cmp	r3, #1
 8003a30:	d112      	bne.n	8003a58 <RCCEx_PLLSAI1_Config+0x16c>
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
        /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8003a32:	4b27      	ldr	r3, [pc, #156]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a34:	691b      	ldr	r3, [r3, #16]
 8003a36:	f423 03c0 	bic.w	r3, r3, #6291456	@ 0x600000
 8003a3a:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 8003a3e:	687a      	ldr	r2, [r7, #4]
 8003a40:	6892      	ldr	r2, [r2, #8]
 8003a42:	0211      	lsls	r1, r2, #8
 8003a44:	687a      	ldr	r2, [r7, #4]
 8003a46:	6912      	ldr	r2, [r2, #16]
 8003a48:	0852      	lsrs	r2, r2, #1
 8003a4a:	3a01      	subs	r2, #1
 8003a4c:	0552      	lsls	r2, r2, #21
 8003a4e:	430a      	orrs	r2, r1
 8003a50:	491f      	ldr	r1, [pc, #124]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a52:	4313      	orrs	r3, r2
 8003a54:	610b      	str	r3, [r1, #16]
 8003a56:	e011      	b.n	8003a7c <RCCEx_PLLSAI1_Config+0x190>
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
        /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8003a58:	4b1d      	ldr	r3, [pc, #116]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a5a:	691b      	ldr	r3, [r3, #16]
 8003a5c:	f023 63c0 	bic.w	r3, r3, #100663296	@ 0x6000000
 8003a60:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 8003a64:	687a      	ldr	r2, [r7, #4]
 8003a66:	6892      	ldr	r2, [r2, #8]
 8003a68:	0211      	lsls	r1, r2, #8
 8003a6a:	687a      	ldr	r2, [r7, #4]
 8003a6c:	6952      	ldr	r2, [r2, #20]
 8003a6e:	0852      	lsrs	r2, r2, #1
 8003a70:	3a01      	subs	r2, #1
 8003a72:	0652      	lsls	r2, r2, #25
 8003a74:	430a      	orrs	r2, r1
 8003a76:	4916      	ldr	r1, [pc, #88]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a78:	4313      	orrs	r3, r2
 8003a7a:	610b      	str	r3, [r1, #16]
                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
      }

      /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
      __HAL_RCC_PLLSAI1_ENABLE();
 8003a7c:	4b14      	ldr	r3, [pc, #80]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a7e:	681b      	ldr	r3, [r3, #0]
 8003a80:	4a13      	ldr	r2, [pc, #76]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a82:	f043 6380 	orr.w	r3, r3, #67108864	@ 0x4000000
 8003a86:	6013      	str	r3, [r2, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8003a88:	f7fd fe44 	bl	8001714 <HAL_GetTick>
 8003a8c:	60b8      	str	r0, [r7, #8]

      /* Wait till PLLSAI1 is ready */
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
 8003a8e:	e009      	b.n	8003aa4 <RCCEx_PLLSAI1_Config+0x1b8>
      {
        if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
 8003a90:	f7fd fe40 	bl	8001714 <HAL_GetTick>
 8003a94:	4602      	mov	r2, r0
 8003a96:	68bb      	ldr	r3, [r7, #8]
 8003a98:	1ad3      	subs	r3, r2, r3
 8003a9a:	2b02      	cmp	r3, #2
 8003a9c:	d902      	bls.n	8003aa4 <RCCEx_PLLSAI1_Config+0x1b8>
        {
          status = HAL_TIMEOUT;
 8003a9e:	2303      	movs	r3, #3
 8003aa0:	73fb      	strb	r3, [r7, #15]
          break;
 8003aa2:	e005      	b.n	8003ab0 <RCCEx_PLLSAI1_Config+0x1c4>
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
 8003aa4:	4b0a      	ldr	r3, [pc, #40]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003aa6:	681b      	ldr	r3, [r3, #0]
 8003aa8:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 8003aac:	2b00      	cmp	r3, #0
 8003aae:	d0ef      	beq.n	8003a90 <RCCEx_PLLSAI1_Config+0x1a4>
        }
      }

      if(status == HAL_OK)
 8003ab0:	7bfb      	ldrb	r3, [r7, #15]
 8003ab2:	2b00      	cmp	r3, #0
 8003ab4:	d106      	bne.n	8003ac4 <RCCEx_PLLSAI1_Config+0x1d8>
      {
        /* Configure the PLLSAI1 Clock output(s) */
        __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
 8003ab6:	4b06      	ldr	r3, [pc, #24]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003ab8:	691a      	ldr	r2, [r3, #16]
 8003aba:	687b      	ldr	r3, [r7, #4]
 8003abc:	699b      	ldr	r3, [r3, #24]
 8003abe:	4904      	ldr	r1, [pc, #16]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003ac0:	4313      	orrs	r3, r2
 8003ac2:	610b      	str	r3, [r1, #16]
      }
    }
  }

  return status;
 8003ac4:	7bfb      	ldrb	r3, [r7, #15]
}
 8003ac6:	4618      	mov	r0, r3
 8003ac8:	3710      	adds	r7, #16
 8003aca:	46bd      	mov	sp, r7
 8003acc:	bd80      	pop	{r7, pc}
 8003ace:	bf00      	nop
 8003ad0:	40021000 	.word	0x40021000

08003ad4 <RCCEx_PLLSAI2_Config>:
  * @note   PLLSAI2 is temporary disable to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
{
 8003ad4:	b580      	push	{r7, lr}
 8003ad6:	b084      	sub	sp, #16
 8003ad8:	af00      	add	r7, sp, #0
 8003ada:	6078      	str	r0, [r7, #4]
 8003adc:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 8003ade:	2300      	movs	r3, #0
 8003ae0:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));

  /* Check that PLLSAI2 clock source and divider M can be applied */
  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
 8003ae2:	4b6a      	ldr	r3, [pc, #424]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003ae4:	68db      	ldr	r3, [r3, #12]
 8003ae6:	f003 0303 	and.w	r3, r3, #3
 8003aea:	2b00      	cmp	r3, #0
 8003aec:	d018      	beq.n	8003b20 <RCCEx_PLLSAI2_Config+0x4c>
  {
    /* PLL clock source and divider M already set, check that no request for change  */
    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
 8003aee:	4b67      	ldr	r3, [pc, #412]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003af0:	68db      	ldr	r3, [r3, #12]
 8003af2:	f003 0203 	and.w	r2, r3, #3
 8003af6:	687b      	ldr	r3, [r7, #4]
 8003af8:	681b      	ldr	r3, [r3, #0]
 8003afa:	429a      	cmp	r2, r3
 8003afc:	d10d      	bne.n	8003b1a <RCCEx_PLLSAI2_Config+0x46>
       ||
       (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
 8003afe:	687b      	ldr	r3, [r7, #4]
 8003b00:	681b      	ldr	r3, [r3, #0]
       ||
 8003b02:	2b00      	cmp	r3, #0
 8003b04:	d009      	beq.n	8003b1a <RCCEx_PLLSAI2_Config+0x46>
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
       ||
       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
 8003b06:	4b61      	ldr	r3, [pc, #388]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b08:	68db      	ldr	r3, [r3, #12]
 8003b0a:	091b      	lsrs	r3, r3, #4
 8003b0c:	f003 0307 	and.w	r3, r3, #7
 8003b10:	1c5a      	adds	r2, r3, #1
 8003b12:	687b      	ldr	r3, [r7, #4]
 8003b14:	685b      	ldr	r3, [r3, #4]
       ||
 8003b16:	429a      	cmp	r2, r3
 8003b18:	d047      	beq.n	8003baa <RCCEx_PLLSAI2_Config+0xd6>
#endif
      )
    {
      status = HAL_ERROR;
 8003b1a:	2301      	movs	r3, #1
 8003b1c:	73fb      	strb	r3, [r7, #15]
 8003b1e:	e044      	b.n	8003baa <RCCEx_PLLSAI2_Config+0xd6>
    }
  }
  else
  {
    /* Check PLLSAI2 clock source availability */
    switch(PllSai2->PLLSAI2Source)
 8003b20:	687b      	ldr	r3, [r7, #4]
 8003b22:	681b      	ldr	r3, [r3, #0]
 8003b24:	2b03      	cmp	r3, #3
 8003b26:	d018      	beq.n	8003b5a <RCCEx_PLLSAI2_Config+0x86>
 8003b28:	2b03      	cmp	r3, #3
 8003b2a:	d825      	bhi.n	8003b78 <RCCEx_PLLSAI2_Config+0xa4>
 8003b2c:	2b01      	cmp	r3, #1
 8003b2e:	d002      	beq.n	8003b36 <RCCEx_PLLSAI2_Config+0x62>
 8003b30:	2b02      	cmp	r3, #2
 8003b32:	d009      	beq.n	8003b48 <RCCEx_PLLSAI2_Config+0x74>
 8003b34:	e020      	b.n	8003b78 <RCCEx_PLLSAI2_Config+0xa4>
    {
    case RCC_PLLSOURCE_MSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
 8003b36:	4b55      	ldr	r3, [pc, #340]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b38:	681b      	ldr	r3, [r3, #0]
 8003b3a:	f003 0302 	and.w	r3, r3, #2
 8003b3e:	2b00      	cmp	r3, #0
 8003b40:	d11d      	bne.n	8003b7e <RCCEx_PLLSAI2_Config+0xaa>
      {
        status = HAL_ERROR;
 8003b42:	2301      	movs	r3, #1
 8003b44:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8003b46:	e01a      	b.n	8003b7e <RCCEx_PLLSAI2_Config+0xaa>
    case RCC_PLLSOURCE_HSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
 8003b48:	4b50      	ldr	r3, [pc, #320]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b4a:	681b      	ldr	r3, [r3, #0]
 8003b4c:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8003b50:	2b00      	cmp	r3, #0
 8003b52:	d116      	bne.n	8003b82 <RCCEx_PLLSAI2_Config+0xae>
      {
        status = HAL_ERROR;
 8003b54:	2301      	movs	r3, #1
 8003b56:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8003b58:	e013      	b.n	8003b82 <RCCEx_PLLSAI2_Config+0xae>
    case RCC_PLLSOURCE_HSE:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
 8003b5a:	4b4c      	ldr	r3, [pc, #304]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b5c:	681b      	ldr	r3, [r3, #0]
 8003b5e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8003b62:	2b00      	cmp	r3, #0
 8003b64:	d10f      	bne.n	8003b86 <RCCEx_PLLSAI2_Config+0xb2>
      {
        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
 8003b66:	4b49      	ldr	r3, [pc, #292]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b68:	681b      	ldr	r3, [r3, #0]
 8003b6a:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 8003b6e:	2b00      	cmp	r3, #0
 8003b70:	d109      	bne.n	8003b86 <RCCEx_PLLSAI2_Config+0xb2>
        {
          status = HAL_ERROR;
 8003b72:	2301      	movs	r3, #1
 8003b74:	73fb      	strb	r3, [r7, #15]
        }
      }
      break;
 8003b76:	e006      	b.n	8003b86 <RCCEx_PLLSAI2_Config+0xb2>
    default:
      status = HAL_ERROR;
 8003b78:	2301      	movs	r3, #1
 8003b7a:	73fb      	strb	r3, [r7, #15]
      break;
 8003b7c:	e004      	b.n	8003b88 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8003b7e:	bf00      	nop
 8003b80:	e002      	b.n	8003b88 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8003b82:	bf00      	nop
 8003b84:	e000      	b.n	8003b88 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8003b86:	bf00      	nop
    }

    if(status == HAL_OK)
 8003b88:	7bfb      	ldrb	r3, [r7, #15]
 8003b8a:	2b00      	cmp	r3, #0
 8003b8c:	d10d      	bne.n	8003baa <RCCEx_PLLSAI2_Config+0xd6>
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
      /* Set PLLSAI2 clock source */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
#else
      /* Set PLLSAI2 clock source and divider M */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
 8003b8e:	4b3f      	ldr	r3, [pc, #252]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b90:	68db      	ldr	r3, [r3, #12]
 8003b92:	f023 0273 	bic.w	r2, r3, #115	@ 0x73
 8003b96:	687b      	ldr	r3, [r7, #4]
 8003b98:	6819      	ldr	r1, [r3, #0]
 8003b9a:	687b      	ldr	r3, [r7, #4]
 8003b9c:	685b      	ldr	r3, [r3, #4]
 8003b9e:	3b01      	subs	r3, #1
 8003ba0:	011b      	lsls	r3, r3, #4
 8003ba2:	430b      	orrs	r3, r1
 8003ba4:	4939      	ldr	r1, [pc, #228]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003ba6:	4313      	orrs	r3, r2
 8003ba8:	60cb      	str	r3, [r1, #12]
#endif
    }
  }

  if(status == HAL_OK)
 8003baa:	7bfb      	ldrb	r3, [r7, #15]
 8003bac:	2b00      	cmp	r3, #0
 8003bae:	d167      	bne.n	8003c80 <RCCEx_PLLSAI2_Config+0x1ac>
  {
    /* Disable the PLLSAI2 */
    __HAL_RCC_PLLSAI2_DISABLE();
 8003bb0:	4b36      	ldr	r3, [pc, #216]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003bb2:	681b      	ldr	r3, [r3, #0]
 8003bb4:	4a35      	ldr	r2, [pc, #212]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003bb6:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8003bba:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8003bbc:	f7fd fdaa 	bl	8001714 <HAL_GetTick>
 8003bc0:	60b8      	str	r0, [r7, #8]

    /* Wait till PLLSAI2 is ready to be updated */
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
 8003bc2:	e009      	b.n	8003bd8 <RCCEx_PLLSAI2_Config+0x104>
    {
      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
 8003bc4:	f7fd fda6 	bl	8001714 <HAL_GetTick>
 8003bc8:	4602      	mov	r2, r0
 8003bca:	68bb      	ldr	r3, [r7, #8]
 8003bcc:	1ad3      	subs	r3, r2, r3
 8003bce:	2b02      	cmp	r3, #2
 8003bd0:	d902      	bls.n	8003bd8 <RCCEx_PLLSAI2_Config+0x104>
      {
        status = HAL_TIMEOUT;
 8003bd2:	2303      	movs	r3, #3
 8003bd4:	73fb      	strb	r3, [r7, #15]
        break;
 8003bd6:	e005      	b.n	8003be4 <RCCEx_PLLSAI2_Config+0x110>
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
 8003bd8:	4b2c      	ldr	r3, [pc, #176]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003bda:	681b      	ldr	r3, [r3, #0]
 8003bdc:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 8003be0:	2b00      	cmp	r3, #0
 8003be2:	d1ef      	bne.n	8003bc4 <RCCEx_PLLSAI2_Config+0xf0>
      }
    }

    if(status == HAL_OK)
 8003be4:	7bfb      	ldrb	r3, [r7, #15]
 8003be6:	2b00      	cmp	r3, #0
 8003be8:	d14a      	bne.n	8003c80 <RCCEx_PLLSAI2_Config+0x1ac>
    {
      if(Divider == DIVIDER_P_UPDATE)
 8003bea:	683b      	ldr	r3, [r7, #0]
 8003bec:	2b00      	cmp	r3, #0
 8003bee:	d111      	bne.n	8003c14 <RCCEx_PLLSAI2_Config+0x140>
        MODIFY_REG(RCC->PLLSAI2CFGR,
                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
                   (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
#else
        MODIFY_REG(RCC->PLLSAI2CFGR,
 8003bf0:	4b26      	ldr	r3, [pc, #152]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003bf2:	695b      	ldr	r3, [r3, #20]
 8003bf4:	f423 331f 	bic.w	r3, r3, #162816	@ 0x27c00
 8003bf8:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8003bfc:	687a      	ldr	r2, [r7, #4]
 8003bfe:	6892      	ldr	r2, [r2, #8]
 8003c00:	0211      	lsls	r1, r2, #8
 8003c02:	687a      	ldr	r2, [r7, #4]
 8003c04:	68d2      	ldr	r2, [r2, #12]
 8003c06:	0912      	lsrs	r2, r2, #4
 8003c08:	0452      	lsls	r2, r2, #17
 8003c0a:	430a      	orrs	r2, r1
 8003c0c:	491f      	ldr	r1, [pc, #124]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c0e:	4313      	orrs	r3, r2
 8003c10:	614b      	str	r3, [r1, #20]
 8003c12:	e011      	b.n	8003c38 <RCCEx_PLLSAI2_Config+0x164>
                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
#else
        /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI2CFGR,
 8003c14:	4b1d      	ldr	r3, [pc, #116]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c16:	695b      	ldr	r3, [r3, #20]
 8003c18:	f023 63c0 	bic.w	r3, r3, #100663296	@ 0x6000000
 8003c1c:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 8003c20:	687a      	ldr	r2, [r7, #4]
 8003c22:	6892      	ldr	r2, [r2, #8]
 8003c24:	0211      	lsls	r1, r2, #8
 8003c26:	687a      	ldr	r2, [r7, #4]
 8003c28:	6912      	ldr	r2, [r2, #16]
 8003c2a:	0852      	lsrs	r2, r2, #1
 8003c2c:	3a01      	subs	r2, #1
 8003c2e:	0652      	lsls	r2, r2, #25
 8003c30:	430a      	orrs	r2, r1
 8003c32:	4916      	ldr	r1, [pc, #88]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c34:	4313      	orrs	r3, r2
 8003c36:	614b      	str	r3, [r1, #20]
                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
      }

      /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
      __HAL_RCC_PLLSAI2_ENABLE();
 8003c38:	4b14      	ldr	r3, [pc, #80]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c3a:	681b      	ldr	r3, [r3, #0]
 8003c3c:	4a13      	ldr	r2, [pc, #76]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c3e:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8003c42:	6013      	str	r3, [r2, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8003c44:	f7fd fd66 	bl	8001714 <HAL_GetTick>
 8003c48:	60b8      	str	r0, [r7, #8]

      /* Wait till PLLSAI2 is ready */
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
 8003c4a:	e009      	b.n	8003c60 <RCCEx_PLLSAI2_Config+0x18c>
      {
        if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
 8003c4c:	f7fd fd62 	bl	8001714 <HAL_GetTick>
 8003c50:	4602      	mov	r2, r0
 8003c52:	68bb      	ldr	r3, [r7, #8]
 8003c54:	1ad3      	subs	r3, r2, r3
 8003c56:	2b02      	cmp	r3, #2
 8003c58:	d902      	bls.n	8003c60 <RCCEx_PLLSAI2_Config+0x18c>
        {
          status = HAL_TIMEOUT;
 8003c5a:	2303      	movs	r3, #3
 8003c5c:	73fb      	strb	r3, [r7, #15]
          break;
 8003c5e:	e005      	b.n	8003c6c <RCCEx_PLLSAI2_Config+0x198>
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
 8003c60:	4b0a      	ldr	r3, [pc, #40]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c62:	681b      	ldr	r3, [r3, #0]
 8003c64:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 8003c68:	2b00      	cmp	r3, #0
 8003c6a:	d0ef      	beq.n	8003c4c <RCCEx_PLLSAI2_Config+0x178>
        }
      }

      if(status == HAL_OK)
 8003c6c:	7bfb      	ldrb	r3, [r7, #15]
 8003c6e:	2b00      	cmp	r3, #0
 8003c70:	d106      	bne.n	8003c80 <RCCEx_PLLSAI2_Config+0x1ac>
      {
        /* Configure the PLLSAI2 Clock output(s) */
        __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
 8003c72:	4b06      	ldr	r3, [pc, #24]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c74:	695a      	ldr	r2, [r3, #20]
 8003c76:	687b      	ldr	r3, [r7, #4]
 8003c78:	695b      	ldr	r3, [r3, #20]
 8003c7a:	4904      	ldr	r1, [pc, #16]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c7c:	4313      	orrs	r3, r2
 8003c7e:	614b      	str	r3, [r1, #20]
      }
    }
  }

  return status;
 8003c80:	7bfb      	ldrb	r3, [r7, #15]
}
 8003c82:	4618      	mov	r0, r3
 8003c84:	3710      	adds	r7, #16
 8003c86:	46bd      	mov	sp, r7
 8003c88:	bd80      	pop	{r7, pc}
 8003c8a:	bf00      	nop
 8003c8c:	40021000 	.word	0x40021000

08003c90 <HAL_SPI_Init>:
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  *               the configuration information for SPI module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
 8003c90:	b580      	push	{r7, lr}
 8003c92:	b084      	sub	sp, #16
 8003c94:	af00      	add	r7, sp, #0
 8003c96:	6078      	str	r0, [r7, #4]
  uint32_t frxth;

  /* Check the SPI handle allocation */
  if (hspi == NULL)
 8003c98:	687b      	ldr	r3, [r7, #4]
 8003c9a:	2b00      	cmp	r3, #0
 8003c9c:	d101      	bne.n	8003ca2 <HAL_SPI_Init+0x12>
  {
    return HAL_ERROR;
 8003c9e:	2301      	movs	r3, #1
 8003ca0:	e095      	b.n	8003dce <HAL_SPI_Init+0x13e>
  assert_param(IS_SPI_NSS(hspi->Init.NSS));
  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
 8003ca2:	687b      	ldr	r3, [r7, #4]
 8003ca4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003ca6:	2b00      	cmp	r3, #0
 8003ca8:	d108      	bne.n	8003cbc <HAL_SPI_Init+0x2c>
  {
    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));

    if (hspi->Init.Mode == SPI_MODE_MASTER)
 8003caa:	687b      	ldr	r3, [r7, #4]
 8003cac:	685b      	ldr	r3, [r3, #4]
 8003cae:	f5b3 7f82 	cmp.w	r3, #260	@ 0x104
 8003cb2:	d009      	beq.n	8003cc8 <HAL_SPI_Init+0x38>
      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
    }
    else
    {
      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
 8003cb4:	687b      	ldr	r3, [r7, #4]
 8003cb6:	2200      	movs	r2, #0
 8003cb8:	61da      	str	r2, [r3, #28]
 8003cba:	e005      	b.n	8003cc8 <HAL_SPI_Init+0x38>
  else
  {
    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));

    /* Force polarity and phase to TI protocaol requirements */
    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
 8003cbc:	687b      	ldr	r3, [r7, #4]
 8003cbe:	2200      	movs	r2, #0
 8003cc0:	611a      	str	r2, [r3, #16]
    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
 8003cc2:	687b      	ldr	r3, [r7, #4]
 8003cc4:	2200      	movs	r2, #0
 8003cc6:	615a      	str	r2, [r3, #20]
  {
    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
  }
#else
  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 8003cc8:	687b      	ldr	r3, [r7, #4]
 8003cca:	2200      	movs	r2, #0
 8003ccc:	629a      	str	r2, [r3, #40]	@ 0x28
#endif /* USE_SPI_CRC */

  if (hspi->State == HAL_SPI_STATE_RESET)
 8003cce:	687b      	ldr	r3, [r7, #4]
 8003cd0:	f893 305d 	ldrb.w	r3, [r3, #93]	@ 0x5d
 8003cd4:	b2db      	uxtb	r3, r3
 8003cd6:	2b00      	cmp	r3, #0
 8003cd8:	d106      	bne.n	8003ce8 <HAL_SPI_Init+0x58>
  {
    /* Allocate lock resource and initialize it */
    hspi->Lock = HAL_UNLOCKED;
 8003cda:	687b      	ldr	r3, [r7, #4]
 8003cdc:	2200      	movs	r2, #0
 8003cde:	f883 205c 	strb.w	r2, [r3, #92]	@ 0x5c

    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
    hspi->MspInitCallback(hspi);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
    HAL_SPI_MspInit(hspi);
 8003ce2:	6878      	ldr	r0, [r7, #4]
 8003ce4:	f7fd fa6e 	bl	80011c4 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  }

  hspi->State = HAL_SPI_STATE_BUSY;
 8003ce8:	687b      	ldr	r3, [r7, #4]
 8003cea:	2202      	movs	r2, #2
 8003cec:	f883 205d 	strb.w	r2, [r3, #93]	@ 0x5d

  /* Disable the selected SPI peripheral */
  __HAL_SPI_DISABLE(hspi);
 8003cf0:	687b      	ldr	r3, [r7, #4]
 8003cf2:	681b      	ldr	r3, [r3, #0]
 8003cf4:	681a      	ldr	r2, [r3, #0]
 8003cf6:	687b      	ldr	r3, [r7, #4]
 8003cf8:	681b      	ldr	r3, [r3, #0]
 8003cfa:	f022 0240 	bic.w	r2, r2, #64	@ 0x40
 8003cfe:	601a      	str	r2, [r3, #0]

  /* Align by default the rs fifo threshold on the data size */
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 8003d00:	687b      	ldr	r3, [r7, #4]
 8003d02:	68db      	ldr	r3, [r3, #12]
 8003d04:	f5b3 6fe0 	cmp.w	r3, #1792	@ 0x700
 8003d08:	d902      	bls.n	8003d10 <HAL_SPI_Init+0x80>
  {
    frxth = SPI_RXFIFO_THRESHOLD_HF;
 8003d0a:	2300      	movs	r3, #0
 8003d0c:	60fb      	str	r3, [r7, #12]
 8003d0e:	e002      	b.n	8003d16 <HAL_SPI_Init+0x86>
  }
  else
  {
    frxth = SPI_RXFIFO_THRESHOLD_QF;
 8003d10:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
 8003d14:	60fb      	str	r3, [r7, #12]
  }

  /* CRC calculation is valid only for 16Bit and 8 Bit */
  if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
 8003d16:	687b      	ldr	r3, [r7, #4]
 8003d18:	68db      	ldr	r3, [r3, #12]
 8003d1a:	f5b3 6f70 	cmp.w	r3, #3840	@ 0xf00
 8003d1e:	d007      	beq.n	8003d30 <HAL_SPI_Init+0xa0>
 8003d20:	687b      	ldr	r3, [r7, #4]
 8003d22:	68db      	ldr	r3, [r3, #12]
 8003d24:	f5b3 6fe0 	cmp.w	r3, #1792	@ 0x700
 8003d28:	d002      	beq.n	8003d30 <HAL_SPI_Init+0xa0>
  {
    /* CRC must be disabled */
    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 8003d2a:	687b      	ldr	r3, [r7, #4]
 8003d2c:	2200      	movs	r2, #0
 8003d2e:	629a      	str	r2, [r3, #40]	@ 0x28
  }

  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
  Communication speed, First bit and CRC calculation state */
  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
 8003d30:	687b      	ldr	r3, [r7, #4]
 8003d32:	685b      	ldr	r3, [r3, #4]
 8003d34:	f403 7282 	and.w	r2, r3, #260	@ 0x104
 8003d38:	687b      	ldr	r3, [r7, #4]
 8003d3a:	689b      	ldr	r3, [r3, #8]
 8003d3c:	f403 4304 	and.w	r3, r3, #33792	@ 0x8400
 8003d40:	431a      	orrs	r2, r3
 8003d42:	687b      	ldr	r3, [r7, #4]
 8003d44:	691b      	ldr	r3, [r3, #16]
 8003d46:	f003 0302 	and.w	r3, r3, #2
 8003d4a:	431a      	orrs	r2, r3
 8003d4c:	687b      	ldr	r3, [r7, #4]
 8003d4e:	695b      	ldr	r3, [r3, #20]
 8003d50:	f003 0301 	and.w	r3, r3, #1
 8003d54:	431a      	orrs	r2, r3
 8003d56:	687b      	ldr	r3, [r7, #4]
 8003d58:	699b      	ldr	r3, [r3, #24]
 8003d5a:	f403 7300 	and.w	r3, r3, #512	@ 0x200
 8003d5e:	431a      	orrs	r2, r3
 8003d60:	687b      	ldr	r3, [r7, #4]
 8003d62:	69db      	ldr	r3, [r3, #28]
 8003d64:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 8003d68:	431a      	orrs	r2, r3
 8003d6a:	687b      	ldr	r3, [r7, #4]
 8003d6c:	6a1b      	ldr	r3, [r3, #32]
 8003d6e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8003d72:	ea42 0103 	orr.w	r1, r2, r3
 8003d76:	687b      	ldr	r3, [r7, #4]
 8003d78:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8003d7a:	f403 5200 	and.w	r2, r3, #8192	@ 0x2000
 8003d7e:	687b      	ldr	r3, [r7, #4]
 8003d80:	681b      	ldr	r3, [r3, #0]
 8003d82:	430a      	orrs	r2, r1
 8003d84:	601a      	str	r2, [r3, #0]
    }
  }
#endif /* USE_SPI_CRC */

  /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
 8003d86:	687b      	ldr	r3, [r7, #4]
 8003d88:	699b      	ldr	r3, [r3, #24]
 8003d8a:	0c1b      	lsrs	r3, r3, #16
 8003d8c:	f003 0204 	and.w	r2, r3, #4
 8003d90:	687b      	ldr	r3, [r7, #4]
 8003d92:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003d94:	f003 0310 	and.w	r3, r3, #16
 8003d98:	431a      	orrs	r2, r3
 8003d9a:	687b      	ldr	r3, [r7, #4]
 8003d9c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8003d9e:	f003 0308 	and.w	r3, r3, #8
 8003da2:	431a      	orrs	r2, r3
 8003da4:	687b      	ldr	r3, [r7, #4]
 8003da6:	68db      	ldr	r3, [r3, #12]
 8003da8:	f403 6370 	and.w	r3, r3, #3840	@ 0xf00
 8003dac:	ea42 0103 	orr.w	r1, r2, r3
 8003db0:	68fb      	ldr	r3, [r7, #12]
 8003db2:	f403 5280 	and.w	r2, r3, #4096	@ 0x1000
 8003db6:	687b      	ldr	r3, [r7, #4]
 8003db8:	681b      	ldr	r3, [r3, #0]
 8003dba:	430a      	orrs	r2, r1
 8003dbc:	605a      	str	r2, [r3, #4]
#if defined(SPI_I2SCFGR_I2SMOD)
  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
#endif /* SPI_I2SCFGR_I2SMOD */

  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 8003dbe:	687b      	ldr	r3, [r7, #4]
 8003dc0:	2200      	movs	r2, #0
 8003dc2:	661a      	str	r2, [r3, #96]	@ 0x60
  hspi->State     = HAL_SPI_STATE_READY;
 8003dc4:	687b      	ldr	r3, [r7, #4]
 8003dc6:	2201      	movs	r2, #1
 8003dc8:	f883 205d 	strb.w	r2, [r3, #93]	@ 0x5d

  return HAL_OK;
 8003dcc:	2300      	movs	r3, #0
}
 8003dce:	4618      	mov	r0, r3
 8003dd0:	3710      	adds	r7, #16
 8003dd2:	46bd      	mov	sp, r7
 8003dd4:	bd80      	pop	{r7, pc}

08003dd6 <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 8003dd6:	b580      	push	{r7, lr}
 8003dd8:	b082      	sub	sp, #8
 8003dda:	af00      	add	r7, sp, #0
 8003ddc:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 8003dde:	687b      	ldr	r3, [r7, #4]
 8003de0:	2b00      	cmp	r3, #0
 8003de2:	d101      	bne.n	8003de8 <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 8003de4:	2301      	movs	r3, #1
 8003de6:	e049      	b.n	8003e7c <HAL_TIM_Base_Init+0xa6>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8003de8:	687b      	ldr	r3, [r7, #4]
 8003dea:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 8003dee:	b2db      	uxtb	r3, r3
 8003df0:	2b00      	cmp	r3, #0
 8003df2:	d106      	bne.n	8003e02 <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 8003df4:	687b      	ldr	r3, [r7, #4]
 8003df6:	2200      	movs	r2, #0
 8003df8:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 8003dfc:	6878      	ldr	r0, [r7, #4]
 8003dfe:	f000 f841 	bl	8003e84 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8003e02:	687b      	ldr	r3, [r7, #4]
 8003e04:	2202      	movs	r2, #2
 8003e06:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8003e0a:	687b      	ldr	r3, [r7, #4]
 8003e0c:	681a      	ldr	r2, [r3, #0]
 8003e0e:	687b      	ldr	r3, [r7, #4]
 8003e10:	3304      	adds	r3, #4
 8003e12:	4619      	mov	r1, r3
 8003e14:	4610      	mov	r0, r2
 8003e16:	f000 f9df 	bl	80041d8 <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8003e1a:	687b      	ldr	r3, [r7, #4]
 8003e1c:	2201      	movs	r2, #1
 8003e1e:	f883 2048 	strb.w	r2, [r3, #72]	@ 0x48

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8003e22:	687b      	ldr	r3, [r7, #4]
 8003e24:	2201      	movs	r2, #1
 8003e26:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 8003e2a:	687b      	ldr	r3, [r7, #4]
 8003e2c:	2201      	movs	r2, #1
 8003e2e:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 8003e32:	687b      	ldr	r3, [r7, #4]
 8003e34:	2201      	movs	r2, #1
 8003e36:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 8003e3a:	687b      	ldr	r3, [r7, #4]
 8003e3c:	2201      	movs	r2, #1
 8003e3e:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 8003e42:	687b      	ldr	r3, [r7, #4]
 8003e44:	2201      	movs	r2, #1
 8003e46:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 8003e4a:	687b      	ldr	r3, [r7, #4]
 8003e4c:	2201      	movs	r2, #1
 8003e4e:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8003e52:	687b      	ldr	r3, [r7, #4]
 8003e54:	2201      	movs	r2, #1
 8003e56:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8003e5a:	687b      	ldr	r3, [r7, #4]
 8003e5c:	2201      	movs	r2, #1
 8003e5e:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8003e62:	687b      	ldr	r3, [r7, #4]
 8003e64:	2201      	movs	r2, #1
 8003e66:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
 8003e6a:	687b      	ldr	r3, [r7, #4]
 8003e6c:	2201      	movs	r2, #1
 8003e6e:	f883 2047 	strb.w	r2, [r3, #71]	@ 0x47

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 8003e72:	687b      	ldr	r3, [r7, #4]
 8003e74:	2201      	movs	r2, #1
 8003e76:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  return HAL_OK;
 8003e7a:	2300      	movs	r3, #0
}
 8003e7c:	4618      	mov	r0, r3
 8003e7e:	3708      	adds	r7, #8
 8003e80:	46bd      	mov	sp, r7
 8003e82:	bd80      	pop	{r7, pc}

08003e84 <HAL_TIM_Base_MspInit>:
  * @brief  Initializes the TIM Base MSP.
  * @param  htim TIM Base handle
  * @retval None
  */
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
 8003e84:	b480      	push	{r7}
 8003e86:	b083      	sub	sp, #12
 8003e88:	af00      	add	r7, sp, #0
 8003e8a:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_Base_MspInit could be implemented in the user file
   */
}
 8003e8c:	bf00      	nop
 8003e8e:	370c      	adds	r7, #12
 8003e90:	46bd      	mov	sp, r7
 8003e92:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e96:	4770      	bx	lr

08003e98 <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 8003e98:	b480      	push	{r7}
 8003e9a:	b085      	sub	sp, #20
 8003e9c:	af00      	add	r7, sp, #0
 8003e9e:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 8003ea0:	687b      	ldr	r3, [r7, #4]
 8003ea2:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 8003ea6:	b2db      	uxtb	r3, r3
 8003ea8:	2b01      	cmp	r3, #1
 8003eaa:	d001      	beq.n	8003eb0 <HAL_TIM_Base_Start_IT+0x18>
  {
    return HAL_ERROR;
 8003eac:	2301      	movs	r3, #1
 8003eae:	e04f      	b.n	8003f50 <HAL_TIM_Base_Start_IT+0xb8>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8003eb0:	687b      	ldr	r3, [r7, #4]
 8003eb2:	2202      	movs	r2, #2
 8003eb4:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 8003eb8:	687b      	ldr	r3, [r7, #4]
 8003eba:	681b      	ldr	r3, [r3, #0]
 8003ebc:	68da      	ldr	r2, [r3, #12]
 8003ebe:	687b      	ldr	r3, [r7, #4]
 8003ec0:	681b      	ldr	r3, [r3, #0]
 8003ec2:	f042 0201 	orr.w	r2, r2, #1
 8003ec6:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8003ec8:	687b      	ldr	r3, [r7, #4]
 8003eca:	681b      	ldr	r3, [r3, #0]
 8003ecc:	4a23      	ldr	r2, [pc, #140]	@ (8003f5c <HAL_TIM_Base_Start_IT+0xc4>)
 8003ece:	4293      	cmp	r3, r2
 8003ed0:	d01d      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003ed2:	687b      	ldr	r3, [r7, #4]
 8003ed4:	681b      	ldr	r3, [r3, #0]
 8003ed6:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8003eda:	d018      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003edc:	687b      	ldr	r3, [r7, #4]
 8003ede:	681b      	ldr	r3, [r3, #0]
 8003ee0:	4a1f      	ldr	r2, [pc, #124]	@ (8003f60 <HAL_TIM_Base_Start_IT+0xc8>)
 8003ee2:	4293      	cmp	r3, r2
 8003ee4:	d013      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003ee6:	687b      	ldr	r3, [r7, #4]
 8003ee8:	681b      	ldr	r3, [r3, #0]
 8003eea:	4a1e      	ldr	r2, [pc, #120]	@ (8003f64 <HAL_TIM_Base_Start_IT+0xcc>)
 8003eec:	4293      	cmp	r3, r2
 8003eee:	d00e      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003ef0:	687b      	ldr	r3, [r7, #4]
 8003ef2:	681b      	ldr	r3, [r3, #0]
 8003ef4:	4a1c      	ldr	r2, [pc, #112]	@ (8003f68 <HAL_TIM_Base_Start_IT+0xd0>)
 8003ef6:	4293      	cmp	r3, r2
 8003ef8:	d009      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003efa:	687b      	ldr	r3, [r7, #4]
 8003efc:	681b      	ldr	r3, [r3, #0]
 8003efe:	4a1b      	ldr	r2, [pc, #108]	@ (8003f6c <HAL_TIM_Base_Start_IT+0xd4>)
 8003f00:	4293      	cmp	r3, r2
 8003f02:	d004      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003f04:	687b      	ldr	r3, [r7, #4]
 8003f06:	681b      	ldr	r3, [r3, #0]
 8003f08:	4a19      	ldr	r2, [pc, #100]	@ (8003f70 <HAL_TIM_Base_Start_IT+0xd8>)
 8003f0a:	4293      	cmp	r3, r2
 8003f0c:	d115      	bne.n	8003f3a <HAL_TIM_Base_Start_IT+0xa2>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8003f0e:	687b      	ldr	r3, [r7, #4]
 8003f10:	681b      	ldr	r3, [r3, #0]
 8003f12:	689a      	ldr	r2, [r3, #8]
 8003f14:	4b17      	ldr	r3, [pc, #92]	@ (8003f74 <HAL_TIM_Base_Start_IT+0xdc>)
 8003f16:	4013      	ands	r3, r2
 8003f18:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003f1a:	68fb      	ldr	r3, [r7, #12]
 8003f1c:	2b06      	cmp	r3, #6
 8003f1e:	d015      	beq.n	8003f4c <HAL_TIM_Base_Start_IT+0xb4>
 8003f20:	68fb      	ldr	r3, [r7, #12]
 8003f22:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8003f26:	d011      	beq.n	8003f4c <HAL_TIM_Base_Start_IT+0xb4>
    {
      __HAL_TIM_ENABLE(htim);
 8003f28:	687b      	ldr	r3, [r7, #4]
 8003f2a:	681b      	ldr	r3, [r3, #0]
 8003f2c:	681a      	ldr	r2, [r3, #0]
 8003f2e:	687b      	ldr	r3, [r7, #4]
 8003f30:	681b      	ldr	r3, [r3, #0]
 8003f32:	f042 0201 	orr.w	r2, r2, #1
 8003f36:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003f38:	e008      	b.n	8003f4c <HAL_TIM_Base_Start_IT+0xb4>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 8003f3a:	687b      	ldr	r3, [r7, #4]
 8003f3c:	681b      	ldr	r3, [r3, #0]
 8003f3e:	681a      	ldr	r2, [r3, #0]
 8003f40:	687b      	ldr	r3, [r7, #4]
 8003f42:	681b      	ldr	r3, [r3, #0]
 8003f44:	f042 0201 	orr.w	r2, r2, #1
 8003f48:	601a      	str	r2, [r3, #0]
 8003f4a:	e000      	b.n	8003f4e <HAL_TIM_Base_Start_IT+0xb6>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003f4c:	bf00      	nop
  }

  /* Return function status */
  return HAL_OK;
 8003f4e:	2300      	movs	r3, #0
}
 8003f50:	4618      	mov	r0, r3
 8003f52:	3714      	adds	r7, #20
 8003f54:	46bd      	mov	sp, r7
 8003f56:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f5a:	4770      	bx	lr
 8003f5c:	40012c00 	.word	0x40012c00
 8003f60:	40000400 	.word	0x40000400
 8003f64:	40000800 	.word	0x40000800
 8003f68:	40000c00 	.word	0x40000c00
 8003f6c:	40013400 	.word	0x40013400
 8003f70:	40014000 	.word	0x40014000
 8003f74:	00010007 	.word	0x00010007

08003f78 <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 8003f78:	b580      	push	{r7, lr}
 8003f7a:	b084      	sub	sp, #16
 8003f7c:	af00      	add	r7, sp, #0
 8003f7e:	6078      	str	r0, [r7, #4]
  uint32_t itsource = htim->Instance->DIER;
 8003f80:	687b      	ldr	r3, [r7, #4]
 8003f82:	681b      	ldr	r3, [r3, #0]
 8003f84:	68db      	ldr	r3, [r3, #12]
 8003f86:	60fb      	str	r3, [r7, #12]
  uint32_t itflag   = htim->Instance->SR;
 8003f88:	687b      	ldr	r3, [r7, #4]
 8003f8a:	681b      	ldr	r3, [r3, #0]
 8003f8c:	691b      	ldr	r3, [r3, #16]
 8003f8e:	60bb      	str	r3, [r7, #8]

  /* Capture compare 1 event */
  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
 8003f90:	68bb      	ldr	r3, [r7, #8]
 8003f92:	f003 0302 	and.w	r3, r3, #2
 8003f96:	2b00      	cmp	r3, #0
 8003f98:	d020      	beq.n	8003fdc <HAL_TIM_IRQHandler+0x64>
  {
    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
 8003f9a:	68fb      	ldr	r3, [r7, #12]
 8003f9c:	f003 0302 	and.w	r3, r3, #2
 8003fa0:	2b00      	cmp	r3, #0
 8003fa2:	d01b      	beq.n	8003fdc <HAL_TIM_IRQHandler+0x64>
    {
      {
        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
 8003fa4:	687b      	ldr	r3, [r7, #4]
 8003fa6:	681b      	ldr	r3, [r3, #0]
 8003fa8:	f06f 0202 	mvn.w	r2, #2
 8003fac:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 8003fae:	687b      	ldr	r3, [r7, #4]
 8003fb0:	2201      	movs	r2, #1
 8003fb2:	771a      	strb	r2, [r3, #28]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 8003fb4:	687b      	ldr	r3, [r7, #4]
 8003fb6:	681b      	ldr	r3, [r3, #0]
 8003fb8:	699b      	ldr	r3, [r3, #24]
 8003fba:	f003 0303 	and.w	r3, r3, #3
 8003fbe:	2b00      	cmp	r3, #0
 8003fc0:	d003      	beq.n	8003fca <HAL_TIM_IRQHandler+0x52>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 8003fc2:	6878      	ldr	r0, [r7, #4]
 8003fc4:	f000 f8e9 	bl	800419a <HAL_TIM_IC_CaptureCallback>
 8003fc8:	e005      	b.n	8003fd6 <HAL_TIM_IRQHandler+0x5e>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 8003fca:	6878      	ldr	r0, [r7, #4]
 8003fcc:	f000 f8db 	bl	8004186 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003fd0:	6878      	ldr	r0, [r7, #4]
 8003fd2:	f000 f8ec 	bl	80041ae <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8003fd6:	687b      	ldr	r3, [r7, #4]
 8003fd8:	2200      	movs	r2, #0
 8003fda:	771a      	strb	r2, [r3, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
 8003fdc:	68bb      	ldr	r3, [r7, #8]
 8003fde:	f003 0304 	and.w	r3, r3, #4
 8003fe2:	2b00      	cmp	r3, #0
 8003fe4:	d020      	beq.n	8004028 <HAL_TIM_IRQHandler+0xb0>
  {
    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
 8003fe6:	68fb      	ldr	r3, [r7, #12]
 8003fe8:	f003 0304 	and.w	r3, r3, #4
 8003fec:	2b00      	cmp	r3, #0
 8003fee:	d01b      	beq.n	8004028 <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
 8003ff0:	687b      	ldr	r3, [r7, #4]
 8003ff2:	681b      	ldr	r3, [r3, #0]
 8003ff4:	f06f 0204 	mvn.w	r2, #4
 8003ff8:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8003ffa:	687b      	ldr	r3, [r7, #4]
 8003ffc:	2202      	movs	r2, #2
 8003ffe:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8004000:	687b      	ldr	r3, [r7, #4]
 8004002:	681b      	ldr	r3, [r3, #0]
 8004004:	699b      	ldr	r3, [r3, #24]
 8004006:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 800400a:	2b00      	cmp	r3, #0
 800400c:	d003      	beq.n	8004016 <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800400e:	6878      	ldr	r0, [r7, #4]
 8004010:	f000 f8c3 	bl	800419a <HAL_TIM_IC_CaptureCallback>
 8004014:	e005      	b.n	8004022 <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8004016:	6878      	ldr	r0, [r7, #4]
 8004018:	f000 f8b5 	bl	8004186 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800401c:	6878      	ldr	r0, [r7, #4]
 800401e:	f000 f8c6 	bl	80041ae <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8004022:	687b      	ldr	r3, [r7, #4]
 8004024:	2200      	movs	r2, #0
 8004026:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 3 event */
  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
 8004028:	68bb      	ldr	r3, [r7, #8]
 800402a:	f003 0308 	and.w	r3, r3, #8
 800402e:	2b00      	cmp	r3, #0
 8004030:	d020      	beq.n	8004074 <HAL_TIM_IRQHandler+0xfc>
  {
    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
 8004032:	68fb      	ldr	r3, [r7, #12]
 8004034:	f003 0308 	and.w	r3, r3, #8
 8004038:	2b00      	cmp	r3, #0
 800403a:	d01b      	beq.n	8004074 <HAL_TIM_IRQHandler+0xfc>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
 800403c:	687b      	ldr	r3, [r7, #4]
 800403e:	681b      	ldr	r3, [r3, #0]
 8004040:	f06f 0208 	mvn.w	r2, #8
 8004044:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8004046:	687b      	ldr	r3, [r7, #4]
 8004048:	2204      	movs	r2, #4
 800404a:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800404c:	687b      	ldr	r3, [r7, #4]
 800404e:	681b      	ldr	r3, [r3, #0]
 8004050:	69db      	ldr	r3, [r3, #28]
 8004052:	f003 0303 	and.w	r3, r3, #3
 8004056:	2b00      	cmp	r3, #0
 8004058:	d003      	beq.n	8004062 <HAL_TIM_IRQHandler+0xea>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800405a:	6878      	ldr	r0, [r7, #4]
 800405c:	f000 f89d 	bl	800419a <HAL_TIM_IC_CaptureCallback>
 8004060:	e005      	b.n	800406e <HAL_TIM_IRQHandler+0xf6>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8004062:	6878      	ldr	r0, [r7, #4]
 8004064:	f000 f88f 	bl	8004186 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8004068:	6878      	ldr	r0, [r7, #4]
 800406a:	f000 f8a0 	bl	80041ae <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800406e:	687b      	ldr	r3, [r7, #4]
 8004070:	2200      	movs	r2, #0
 8004072:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 4 event */
  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
 8004074:	68bb      	ldr	r3, [r7, #8]
 8004076:	f003 0310 	and.w	r3, r3, #16
 800407a:	2b00      	cmp	r3, #0
 800407c:	d020      	beq.n	80040c0 <HAL_TIM_IRQHandler+0x148>
  {
    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
 800407e:	68fb      	ldr	r3, [r7, #12]
 8004080:	f003 0310 	and.w	r3, r3, #16
 8004084:	2b00      	cmp	r3, #0
 8004086:	d01b      	beq.n	80040c0 <HAL_TIM_IRQHandler+0x148>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
 8004088:	687b      	ldr	r3, [r7, #4]
 800408a:	681b      	ldr	r3, [r3, #0]
 800408c:	f06f 0210 	mvn.w	r2, #16
 8004090:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8004092:	687b      	ldr	r3, [r7, #4]
 8004094:	2208      	movs	r2, #8
 8004096:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8004098:	687b      	ldr	r3, [r7, #4]
 800409a:	681b      	ldr	r3, [r3, #0]
 800409c:	69db      	ldr	r3, [r3, #28]
 800409e:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 80040a2:	2b00      	cmp	r3, #0
 80040a4:	d003      	beq.n	80040ae <HAL_TIM_IRQHandler+0x136>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 80040a6:	6878      	ldr	r0, [r7, #4]
 80040a8:	f000 f877 	bl	800419a <HAL_TIM_IC_CaptureCallback>
 80040ac:	e005      	b.n	80040ba <HAL_TIM_IRQHandler+0x142>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80040ae:	6878      	ldr	r0, [r7, #4]
 80040b0:	f000 f869 	bl	8004186 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80040b4:	6878      	ldr	r0, [r7, #4]
 80040b6:	f000 f87a 	bl	80041ae <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80040ba:	687b      	ldr	r3, [r7, #4]
 80040bc:	2200      	movs	r2, #0
 80040be:	771a      	strb	r2, [r3, #28]
    }
  }
  /* TIM Update event */
  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
 80040c0:	68bb      	ldr	r3, [r7, #8]
 80040c2:	f003 0301 	and.w	r3, r3, #1
 80040c6:	2b00      	cmp	r3, #0
 80040c8:	d00c      	beq.n	80040e4 <HAL_TIM_IRQHandler+0x16c>
  {
    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
 80040ca:	68fb      	ldr	r3, [r7, #12]
 80040cc:	f003 0301 	and.w	r3, r3, #1
 80040d0:	2b00      	cmp	r3, #0
 80040d2:	d007      	beq.n	80040e4 <HAL_TIM_IRQHandler+0x16c>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
 80040d4:	687b      	ldr	r3, [r7, #4]
 80040d6:	681b      	ldr	r3, [r3, #0]
 80040d8:	f06f 0201 	mvn.w	r2, #1
 80040dc:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 80040de:	6878      	ldr	r0, [r7, #4]
 80040e0:	f7fc ff2a 	bl	8000f38 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 80040e4:	68bb      	ldr	r3, [r7, #8]
 80040e6:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80040ea:	2b00      	cmp	r3, #0
 80040ec:	d104      	bne.n	80040f8 <HAL_TIM_IRQHandler+0x180>
      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
 80040ee:	68bb      	ldr	r3, [r7, #8]
 80040f0:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 80040f4:	2b00      	cmp	r3, #0
 80040f6:	d00c      	beq.n	8004112 <HAL_TIM_IRQHandler+0x19a>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 80040f8:	68fb      	ldr	r3, [r7, #12]
 80040fa:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80040fe:	2b00      	cmp	r3, #0
 8004100:	d007      	beq.n	8004112 <HAL_TIM_IRQHandler+0x19a>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
 8004102:	687b      	ldr	r3, [r7, #4]
 8004104:	681b      	ldr	r3, [r3, #0]
 8004106:	f46f 5202 	mvn.w	r2, #8320	@ 0x2080
 800410a:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 800410c:	6878      	ldr	r0, [r7, #4]
 800410e:	f000 f913 	bl	8004338 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break2 input event */
  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
 8004112:	68bb      	ldr	r3, [r7, #8]
 8004114:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8004118:	2b00      	cmp	r3, #0
 800411a:	d00c      	beq.n	8004136 <HAL_TIM_IRQHandler+0x1be>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 800411c:	68fb      	ldr	r3, [r7, #12]
 800411e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8004122:	2b00      	cmp	r3, #0
 8004124:	d007      	beq.n	8004136 <HAL_TIM_IRQHandler+0x1be>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
 8004126:	687b      	ldr	r3, [r7, #4]
 8004128:	681b      	ldr	r3, [r3, #0]
 800412a:	f46f 7280 	mvn.w	r2, #256	@ 0x100
 800412e:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->Break2Callback(htim);
#else
      HAL_TIMEx_Break2Callback(htim);
 8004130:	6878      	ldr	r0, [r7, #4]
 8004132:	f000 f90b 	bl	800434c <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
 8004136:	68bb      	ldr	r3, [r7, #8]
 8004138:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800413c:	2b00      	cmp	r3, #0
 800413e:	d00c      	beq.n	800415a <HAL_TIM_IRQHandler+0x1e2>
  {
    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
 8004140:	68fb      	ldr	r3, [r7, #12]
 8004142:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8004146:	2b00      	cmp	r3, #0
 8004148:	d007      	beq.n	800415a <HAL_TIM_IRQHandler+0x1e2>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
 800414a:	687b      	ldr	r3, [r7, #4]
 800414c:	681b      	ldr	r3, [r3, #0]
 800414e:	f06f 0240 	mvn.w	r2, #64	@ 0x40
 8004152:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 8004154:	6878      	ldr	r0, [r7, #4]
 8004156:	f000 f834 	bl	80041c2 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
 800415a:	68bb      	ldr	r3, [r7, #8]
 800415c:	f003 0320 	and.w	r3, r3, #32
 8004160:	2b00      	cmp	r3, #0
 8004162:	d00c      	beq.n	800417e <HAL_TIM_IRQHandler+0x206>
  {
    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
 8004164:	68fb      	ldr	r3, [r7, #12]
 8004166:	f003 0320 	and.w	r3, r3, #32
 800416a:	2b00      	cmp	r3, #0
 800416c:	d007      	beq.n	800417e <HAL_TIM_IRQHandler+0x206>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
 800416e:	687b      	ldr	r3, [r7, #4]
 8004170:	681b      	ldr	r3, [r3, #0]
 8004172:	f06f 0220 	mvn.w	r2, #32
 8004176:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 8004178:	6878      	ldr	r0, [r7, #4]
 800417a:	f000 f8d3 	bl	8004324 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 800417e:	bf00      	nop
 8004180:	3710      	adds	r7, #16
 8004182:	46bd      	mov	sp, r7
 8004184:	bd80      	pop	{r7, pc}

08004186 <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 8004186:	b480      	push	{r7}
 8004188:	b083      	sub	sp, #12
 800418a:	af00      	add	r7, sp, #0
 800418c:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 800418e:	bf00      	nop
 8004190:	370c      	adds	r7, #12
 8004192:	46bd      	mov	sp, r7
 8004194:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004198:	4770      	bx	lr

0800419a <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 800419a:	b480      	push	{r7}
 800419c:	b083      	sub	sp, #12
 800419e:	af00      	add	r7, sp, #0
 80041a0:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 80041a2:	bf00      	nop
 80041a4:	370c      	adds	r7, #12
 80041a6:	46bd      	mov	sp, r7
 80041a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041ac:	4770      	bx	lr

080041ae <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 80041ae:	b480      	push	{r7}
 80041b0:	b083      	sub	sp, #12
 80041b2:	af00      	add	r7, sp, #0
 80041b4:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 80041b6:	bf00      	nop
 80041b8:	370c      	adds	r7, #12
 80041ba:	46bd      	mov	sp, r7
 80041bc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041c0:	4770      	bx	lr

080041c2 <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 80041c2:	b480      	push	{r7}
 80041c4:	b083      	sub	sp, #12
 80041c6:	af00      	add	r7, sp, #0
 80041c8:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 80041ca:	bf00      	nop
 80041cc:	370c      	adds	r7, #12
 80041ce:	46bd      	mov	sp, r7
 80041d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041d4:	4770      	bx	lr
	...

080041d8 <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
 80041d8:	b480      	push	{r7}
 80041da:	b085      	sub	sp, #20
 80041dc:	af00      	add	r7, sp, #0
 80041de:	6078      	str	r0, [r7, #4]
 80041e0:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 80041e2:	687b      	ldr	r3, [r7, #4]
 80041e4:	681b      	ldr	r3, [r3, #0]
 80041e6:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 80041e8:	687b      	ldr	r3, [r7, #4]
 80041ea:	4a46      	ldr	r2, [pc, #280]	@ (8004304 <TIM_Base_SetConfig+0x12c>)
 80041ec:	4293      	cmp	r3, r2
 80041ee:	d013      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 80041f0:	687b      	ldr	r3, [r7, #4]
 80041f2:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 80041f6:	d00f      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 80041f8:	687b      	ldr	r3, [r7, #4]
 80041fa:	4a43      	ldr	r2, [pc, #268]	@ (8004308 <TIM_Base_SetConfig+0x130>)
 80041fc:	4293      	cmp	r3, r2
 80041fe:	d00b      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 8004200:	687b      	ldr	r3, [r7, #4]
 8004202:	4a42      	ldr	r2, [pc, #264]	@ (800430c <TIM_Base_SetConfig+0x134>)
 8004204:	4293      	cmp	r3, r2
 8004206:	d007      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 8004208:	687b      	ldr	r3, [r7, #4]
 800420a:	4a41      	ldr	r2, [pc, #260]	@ (8004310 <TIM_Base_SetConfig+0x138>)
 800420c:	4293      	cmp	r3, r2
 800420e:	d003      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 8004210:	687b      	ldr	r3, [r7, #4]
 8004212:	4a40      	ldr	r2, [pc, #256]	@ (8004314 <TIM_Base_SetConfig+0x13c>)
 8004214:	4293      	cmp	r3, r2
 8004216:	d108      	bne.n	800422a <TIM_Base_SetConfig+0x52>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8004218:	68fb      	ldr	r3, [r7, #12]
 800421a:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 800421e:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 8004220:	683b      	ldr	r3, [r7, #0]
 8004222:	685b      	ldr	r3, [r3, #4]
 8004224:	68fa      	ldr	r2, [r7, #12]
 8004226:	4313      	orrs	r3, r2
 8004228:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 800422a:	687b      	ldr	r3, [r7, #4]
 800422c:	4a35      	ldr	r2, [pc, #212]	@ (8004304 <TIM_Base_SetConfig+0x12c>)
 800422e:	4293      	cmp	r3, r2
 8004230:	d01f      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 8004232:	687b      	ldr	r3, [r7, #4]
 8004234:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8004238:	d01b      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 800423a:	687b      	ldr	r3, [r7, #4]
 800423c:	4a32      	ldr	r2, [pc, #200]	@ (8004308 <TIM_Base_SetConfig+0x130>)
 800423e:	4293      	cmp	r3, r2
 8004240:	d017      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 8004242:	687b      	ldr	r3, [r7, #4]
 8004244:	4a31      	ldr	r2, [pc, #196]	@ (800430c <TIM_Base_SetConfig+0x134>)
 8004246:	4293      	cmp	r3, r2
 8004248:	d013      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 800424a:	687b      	ldr	r3, [r7, #4]
 800424c:	4a30      	ldr	r2, [pc, #192]	@ (8004310 <TIM_Base_SetConfig+0x138>)
 800424e:	4293      	cmp	r3, r2
 8004250:	d00f      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 8004252:	687b      	ldr	r3, [r7, #4]
 8004254:	4a2f      	ldr	r2, [pc, #188]	@ (8004314 <TIM_Base_SetConfig+0x13c>)
 8004256:	4293      	cmp	r3, r2
 8004258:	d00b      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 800425a:	687b      	ldr	r3, [r7, #4]
 800425c:	4a2e      	ldr	r2, [pc, #184]	@ (8004318 <TIM_Base_SetConfig+0x140>)
 800425e:	4293      	cmp	r3, r2
 8004260:	d007      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 8004262:	687b      	ldr	r3, [r7, #4]
 8004264:	4a2d      	ldr	r2, [pc, #180]	@ (800431c <TIM_Base_SetConfig+0x144>)
 8004266:	4293      	cmp	r3, r2
 8004268:	d003      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 800426a:	687b      	ldr	r3, [r7, #4]
 800426c:	4a2c      	ldr	r2, [pc, #176]	@ (8004320 <TIM_Base_SetConfig+0x148>)
 800426e:	4293      	cmp	r3, r2
 8004270:	d108      	bne.n	8004284 <TIM_Base_SetConfig+0xac>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 8004272:	68fb      	ldr	r3, [r7, #12]
 8004274:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8004278:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800427a:	683b      	ldr	r3, [r7, #0]
 800427c:	68db      	ldr	r3, [r3, #12]
 800427e:	68fa      	ldr	r2, [r7, #12]
 8004280:	4313      	orrs	r3, r2
 8004282:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8004284:	68fb      	ldr	r3, [r7, #12]
 8004286:	f023 0280 	bic.w	r2, r3, #128	@ 0x80
 800428a:	683b      	ldr	r3, [r7, #0]
 800428c:	695b      	ldr	r3, [r3, #20]
 800428e:	4313      	orrs	r3, r2
 8004290:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 8004292:	687b      	ldr	r3, [r7, #4]
 8004294:	68fa      	ldr	r2, [r7, #12]
 8004296:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8004298:	683b      	ldr	r3, [r7, #0]
 800429a:	689a      	ldr	r2, [r3, #8]
 800429c:	687b      	ldr	r3, [r7, #4]
 800429e:	62da      	str	r2, [r3, #44]	@ 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 80042a0:	683b      	ldr	r3, [r7, #0]
 80042a2:	681a      	ldr	r2, [r3, #0]
 80042a4:	687b      	ldr	r3, [r7, #4]
 80042a6:	629a      	str	r2, [r3, #40]	@ 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 80042a8:	687b      	ldr	r3, [r7, #4]
 80042aa:	4a16      	ldr	r2, [pc, #88]	@ (8004304 <TIM_Base_SetConfig+0x12c>)
 80042ac:	4293      	cmp	r3, r2
 80042ae:	d00f      	beq.n	80042d0 <TIM_Base_SetConfig+0xf8>
 80042b0:	687b      	ldr	r3, [r7, #4]
 80042b2:	4a18      	ldr	r2, [pc, #96]	@ (8004314 <TIM_Base_SetConfig+0x13c>)
 80042b4:	4293      	cmp	r3, r2
 80042b6:	d00b      	beq.n	80042d0 <TIM_Base_SetConfig+0xf8>
 80042b8:	687b      	ldr	r3, [r7, #4]
 80042ba:	4a17      	ldr	r2, [pc, #92]	@ (8004318 <TIM_Base_SetConfig+0x140>)
 80042bc:	4293      	cmp	r3, r2
 80042be:	d007      	beq.n	80042d0 <TIM_Base_SetConfig+0xf8>
 80042c0:	687b      	ldr	r3, [r7, #4]
 80042c2:	4a16      	ldr	r2, [pc, #88]	@ (800431c <TIM_Base_SetConfig+0x144>)
 80042c4:	4293      	cmp	r3, r2
 80042c6:	d003      	beq.n	80042d0 <TIM_Base_SetConfig+0xf8>
 80042c8:	687b      	ldr	r3, [r7, #4]
 80042ca:	4a15      	ldr	r2, [pc, #84]	@ (8004320 <TIM_Base_SetConfig+0x148>)
 80042cc:	4293      	cmp	r3, r2
 80042ce:	d103      	bne.n	80042d8 <TIM_Base_SetConfig+0x100>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 80042d0:	683b      	ldr	r3, [r7, #0]
 80042d2:	691a      	ldr	r2, [r3, #16]
 80042d4:	687b      	ldr	r3, [r7, #4]
 80042d6:	631a      	str	r2, [r3, #48]	@ 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 80042d8:	687b      	ldr	r3, [r7, #4]
 80042da:	2201      	movs	r2, #1
 80042dc:	615a      	str	r2, [r3, #20]

  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
 80042de:	687b      	ldr	r3, [r7, #4]
 80042e0:	691b      	ldr	r3, [r3, #16]
 80042e2:	f003 0301 	and.w	r3, r3, #1
 80042e6:	2b01      	cmp	r3, #1
 80042e8:	d105      	bne.n	80042f6 <TIM_Base_SetConfig+0x11e>
  {
    /* Clear the update flag */
    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
 80042ea:	687b      	ldr	r3, [r7, #4]
 80042ec:	691b      	ldr	r3, [r3, #16]
 80042ee:	f023 0201 	bic.w	r2, r3, #1
 80042f2:	687b      	ldr	r3, [r7, #4]
 80042f4:	611a      	str	r2, [r3, #16]
  }
}
 80042f6:	bf00      	nop
 80042f8:	3714      	adds	r7, #20
 80042fa:	46bd      	mov	sp, r7
 80042fc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004300:	4770      	bx	lr
 8004302:	bf00      	nop
 8004304:	40012c00 	.word	0x40012c00
 8004308:	40000400 	.word	0x40000400
 800430c:	40000800 	.word	0x40000800
 8004310:	40000c00 	.word	0x40000c00
 8004314:	40013400 	.word	0x40013400
 8004318:	40014000 	.word	0x40014000
 800431c:	40014400 	.word	0x40014400
 8004320:	40014800 	.word	0x40014800

08004324 <HAL_TIMEx_CommutCallback>:
  * @brief  Commutation callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
 8004324:	b480      	push	{r7}
 8004326:	b083      	sub	sp, #12
 8004328:	af00      	add	r7, sp, #0
 800432a:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
 800432c:	bf00      	nop
 800432e:	370c      	adds	r7, #12
 8004330:	46bd      	mov	sp, r7
 8004332:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004336:	4770      	bx	lr

08004338 <HAL_TIMEx_BreakCallback>:
  * @brief  Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8004338:	b480      	push	{r7}
 800433a:	b083      	sub	sp, #12
 800433c:	af00      	add	r7, sp, #0
 800433e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
 8004340:	bf00      	nop
 8004342:	370c      	adds	r7, #12
 8004344:	46bd      	mov	sp, r7
 8004346:	f85d 7b04 	ldr.w	r7, [sp], #4
 800434a:	4770      	bx	lr

0800434c <HAL_TIMEx_Break2Callback>:
  * @brief  Break2 detection callback in non blocking mode
  * @param  htim: TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
 800434c:	b480      	push	{r7}
 800434e:	b083      	sub	sp, #12
 8004350:	af00      	add	r7, sp, #0
 8004352:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_TIMEx_Break2Callback could be implemented in the user file
   */
}
 8004354:	bf00      	nop
 8004356:	370c      	adds	r7, #12
 8004358:	46bd      	mov	sp, r7
 800435a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800435e:	4770      	bx	lr

08004360 <HAL_UART_Init>:
  *        parameters in the UART_InitTypeDef and initialize the associated handle.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 8004360:	b580      	push	{r7, lr}
 8004362:	b082      	sub	sp, #8
 8004364:	af00      	add	r7, sp, #0
 8004366:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8004368:	687b      	ldr	r3, [r7, #4]
 800436a:	2b00      	cmp	r3, #0
 800436c:	d101      	bne.n	8004372 <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 800436e:	2301      	movs	r3, #1
 8004370:	e040      	b.n	80043f4 <HAL_UART_Init+0x94>
  {
    /* Check the parameters */
    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
  }

  if (huart->gState == HAL_UART_STATE_RESET)
 8004372:	687b      	ldr	r3, [r7, #4]
 8004374:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 8004376:	2b00      	cmp	r3, #0
 8004378:	d106      	bne.n	8004388 <HAL_UART_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 800437a:	687b      	ldr	r3, [r7, #4]
 800437c:	2200      	movs	r2, #0
 800437e:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 8004382:	6878      	ldr	r0, [r7, #4]
 8004384:	f7fc ff62 	bl	800124c <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 8004388:	687b      	ldr	r3, [r7, #4]
 800438a:	2224      	movs	r2, #36	@ 0x24
 800438c:	67da      	str	r2, [r3, #124]	@ 0x7c

  __HAL_UART_DISABLE(huart);
 800438e:	687b      	ldr	r3, [r7, #4]
 8004390:	681b      	ldr	r3, [r3, #0]
 8004392:	681a      	ldr	r2, [r3, #0]
 8004394:	687b      	ldr	r3, [r7, #4]
 8004396:	681b      	ldr	r3, [r3, #0]
 8004398:	f022 0201 	bic.w	r2, r2, #1
 800439c:	601a      	str	r2, [r3, #0]

  /* Perform advanced settings configuration */
  /* For some items, configuration requires to be done prior TE and RE bits are set */
  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 800439e:	687b      	ldr	r3, [r7, #4]
 80043a0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80043a2:	2b00      	cmp	r3, #0
 80043a4:	d002      	beq.n	80043ac <HAL_UART_Init+0x4c>
  {
    UART_AdvFeatureConfig(huart);
 80043a6:	6878      	ldr	r0, [r7, #4]
 80043a8:	f000 fae0 	bl	800496c <UART_AdvFeatureConfig>
  }

  /* Set the UART Communication parameters */
  if (UART_SetConfig(huart) == HAL_ERROR)
 80043ac:	6878      	ldr	r0, [r7, #4]
 80043ae:	f000 f825 	bl	80043fc <UART_SetConfig>
 80043b2:	4603      	mov	r3, r0
 80043b4:	2b01      	cmp	r3, #1
 80043b6:	d101      	bne.n	80043bc <HAL_UART_Init+0x5c>
  {
    return HAL_ERROR;
 80043b8:	2301      	movs	r3, #1
 80043ba:	e01b      	b.n	80043f4 <HAL_UART_Init+0x94>
  }

  /* In asynchronous mode, the following bits must be kept cleared:
  - LINEN and CLKEN bits in the USART_CR2 register,
  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 80043bc:	687b      	ldr	r3, [r7, #4]
 80043be:	681b      	ldr	r3, [r3, #0]
 80043c0:	685a      	ldr	r2, [r3, #4]
 80043c2:	687b      	ldr	r3, [r7, #4]
 80043c4:	681b      	ldr	r3, [r3, #0]
 80043c6:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
 80043ca:	605a      	str	r2, [r3, #4]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 80043cc:	687b      	ldr	r3, [r7, #4]
 80043ce:	681b      	ldr	r3, [r3, #0]
 80043d0:	689a      	ldr	r2, [r3, #8]
 80043d2:	687b      	ldr	r3, [r7, #4]
 80043d4:	681b      	ldr	r3, [r3, #0]
 80043d6:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
 80043da:	609a      	str	r2, [r3, #8]

  __HAL_UART_ENABLE(huart);
 80043dc:	687b      	ldr	r3, [r7, #4]
 80043de:	681b      	ldr	r3, [r3, #0]
 80043e0:	681a      	ldr	r2, [r3, #0]
 80043e2:	687b      	ldr	r3, [r7, #4]
 80043e4:	681b      	ldr	r3, [r3, #0]
 80043e6:	f042 0201 	orr.w	r2, r2, #1
 80043ea:	601a      	str	r2, [r3, #0]

  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
  return (UART_CheckIdleState(huart));
 80043ec:	6878      	ldr	r0, [r7, #4]
 80043ee:	f000 fb5f 	bl	8004ab0 <UART_CheckIdleState>
 80043f2:	4603      	mov	r3, r0
}
 80043f4:	4618      	mov	r0, r3
 80043f6:	3708      	adds	r7, #8
 80043f8:	46bd      	mov	sp, r7
 80043fa:	bd80      	pop	{r7, pc}

080043fc <UART_SetConfig>:
  * @brief Configure the UART peripheral.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
 80043fc:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8004400:	b08a      	sub	sp, #40	@ 0x28
 8004402:	af00      	add	r7, sp, #0
 8004404:	60f8      	str	r0, [r7, #12]
  uint32_t tmpreg;
  uint16_t brrtemp;
  UART_ClockSourceTypeDef clocksource;
  uint32_t usartdiv;
  HAL_StatusTypeDef ret               = HAL_OK;
 8004406:	2300      	movs	r3, #0
 8004408:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
  *  the UART Word Length, Parity, Mode and oversampling:
  *  set the M bits according to huart->Init.WordLength value
  *  set PCE and PS bits according to huart->Init.Parity value
  *  set TE and RE bits according to huart->Init.Mode value
  *  set OVER8 bit according to huart->Init.OverSampling value */
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 800440c:	68fb      	ldr	r3, [r7, #12]
 800440e:	689a      	ldr	r2, [r3, #8]
 8004410:	68fb      	ldr	r3, [r7, #12]
 8004412:	691b      	ldr	r3, [r3, #16]
 8004414:	431a      	orrs	r2, r3
 8004416:	68fb      	ldr	r3, [r7, #12]
 8004418:	695b      	ldr	r3, [r3, #20]
 800441a:	431a      	orrs	r2, r3
 800441c:	68fb      	ldr	r3, [r7, #12]
 800441e:	69db      	ldr	r3, [r3, #28]
 8004420:	4313      	orrs	r3, r2
 8004422:	627b      	str	r3, [r7, #36]	@ 0x24
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 8004424:	68fb      	ldr	r3, [r7, #12]
 8004426:	681b      	ldr	r3, [r3, #0]
 8004428:	681a      	ldr	r2, [r3, #0]
 800442a:	4ba4      	ldr	r3, [pc, #656]	@ (80046bc <UART_SetConfig+0x2c0>)
 800442c:	4013      	ands	r3, r2
 800442e:	68fa      	ldr	r2, [r7, #12]
 8004430:	6812      	ldr	r2, [r2, #0]
 8004432:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 8004434:	430b      	orrs	r3, r1
 8004436:	6013      	str	r3, [r2, #0]

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
  * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8004438:	68fb      	ldr	r3, [r7, #12]
 800443a:	681b      	ldr	r3, [r3, #0]
 800443c:	685b      	ldr	r3, [r3, #4]
 800443e:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
 8004442:	68fb      	ldr	r3, [r7, #12]
 8004444:	68da      	ldr	r2, [r3, #12]
 8004446:	68fb      	ldr	r3, [r7, #12]
 8004448:	681b      	ldr	r3, [r3, #0]
 800444a:	430a      	orrs	r2, r1
 800444c:	605a      	str	r2, [r3, #4]
  /* Configure
  * - UART HardWare Flow Control: set CTSE and RTSE bits according
  *   to huart->Init.HwFlowCtl value
  * - one-bit sampling method versus three samples' majority rule according
  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
 800444e:	68fb      	ldr	r3, [r7, #12]
 8004450:	699b      	ldr	r3, [r3, #24]
 8004452:	627b      	str	r3, [r7, #36]	@ 0x24

  if (!(UART_INSTANCE_LOWPOWER(huart)))
 8004454:	68fb      	ldr	r3, [r7, #12]
 8004456:	681b      	ldr	r3, [r3, #0]
 8004458:	4a99      	ldr	r2, [pc, #612]	@ (80046c0 <UART_SetConfig+0x2c4>)
 800445a:	4293      	cmp	r3, r2
 800445c:	d004      	beq.n	8004468 <UART_SetConfig+0x6c>
  {
    tmpreg |= huart->Init.OneBitSampling;
 800445e:	68fb      	ldr	r3, [r7, #12]
 8004460:	6a1b      	ldr	r3, [r3, #32]
 8004462:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8004464:	4313      	orrs	r3, r2
 8004466:	627b      	str	r3, [r7, #36]	@ 0x24
  }
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 8004468:	68fb      	ldr	r3, [r7, #12]
 800446a:	681b      	ldr	r3, [r3, #0]
 800446c:	689b      	ldr	r3, [r3, #8]
 800446e:	f423 6130 	bic.w	r1, r3, #2816	@ 0xb00
 8004472:	68fb      	ldr	r3, [r7, #12]
 8004474:	681b      	ldr	r3, [r3, #0]
 8004476:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8004478:	430a      	orrs	r2, r1
 800447a:	609a      	str	r2, [r3, #8]
  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
#endif /* USART_PRESC_PRESCALER */

  /*-------------------------- USART BRR Configuration -----------------------*/
  UART_GETCLOCKSOURCE(huart, clocksource);
 800447c:	68fb      	ldr	r3, [r7, #12]
 800447e:	681b      	ldr	r3, [r3, #0]
 8004480:	4a90      	ldr	r2, [pc, #576]	@ (80046c4 <UART_SetConfig+0x2c8>)
 8004482:	4293      	cmp	r3, r2
 8004484:	d126      	bne.n	80044d4 <UART_SetConfig+0xd8>
 8004486:	4b90      	ldr	r3, [pc, #576]	@ (80046c8 <UART_SetConfig+0x2cc>)
 8004488:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800448c:	f003 0303 	and.w	r3, r3, #3
 8004490:	2b03      	cmp	r3, #3
 8004492:	d81b      	bhi.n	80044cc <UART_SetConfig+0xd0>
 8004494:	a201      	add	r2, pc, #4	@ (adr r2, 800449c <UART_SetConfig+0xa0>)
 8004496:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800449a:	bf00      	nop
 800449c:	080044ad 	.word	0x080044ad
 80044a0:	080044bd 	.word	0x080044bd
 80044a4:	080044b5 	.word	0x080044b5
 80044a8:	080044c5 	.word	0x080044c5
 80044ac:	2301      	movs	r3, #1
 80044ae:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80044b2:	e116      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80044b4:	2302      	movs	r3, #2
 80044b6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80044ba:	e112      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80044bc:	2304      	movs	r3, #4
 80044be:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80044c2:	e10e      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80044c4:	2308      	movs	r3, #8
 80044c6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80044ca:	e10a      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80044cc:	2310      	movs	r3, #16
 80044ce:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80044d2:	e106      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80044d4:	68fb      	ldr	r3, [r7, #12]
 80044d6:	681b      	ldr	r3, [r3, #0]
 80044d8:	4a7c      	ldr	r2, [pc, #496]	@ (80046cc <UART_SetConfig+0x2d0>)
 80044da:	4293      	cmp	r3, r2
 80044dc:	d138      	bne.n	8004550 <UART_SetConfig+0x154>
 80044de:	4b7a      	ldr	r3, [pc, #488]	@ (80046c8 <UART_SetConfig+0x2cc>)
 80044e0:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80044e4:	f003 030c 	and.w	r3, r3, #12
 80044e8:	2b0c      	cmp	r3, #12
 80044ea:	d82d      	bhi.n	8004548 <UART_SetConfig+0x14c>
 80044ec:	a201      	add	r2, pc, #4	@ (adr r2, 80044f4 <UART_SetConfig+0xf8>)
 80044ee:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80044f2:	bf00      	nop
 80044f4:	08004529 	.word	0x08004529
 80044f8:	08004549 	.word	0x08004549
 80044fc:	08004549 	.word	0x08004549
 8004500:	08004549 	.word	0x08004549
 8004504:	08004539 	.word	0x08004539
 8004508:	08004549 	.word	0x08004549
 800450c:	08004549 	.word	0x08004549
 8004510:	08004549 	.word	0x08004549
 8004514:	08004531 	.word	0x08004531
 8004518:	08004549 	.word	0x08004549
 800451c:	08004549 	.word	0x08004549
 8004520:	08004549 	.word	0x08004549
 8004524:	08004541 	.word	0x08004541
 8004528:	2300      	movs	r3, #0
 800452a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800452e:	e0d8      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004530:	2302      	movs	r3, #2
 8004532:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004536:	e0d4      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004538:	2304      	movs	r3, #4
 800453a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800453e:	e0d0      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004540:	2308      	movs	r3, #8
 8004542:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004546:	e0cc      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004548:	2310      	movs	r3, #16
 800454a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800454e:	e0c8      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004550:	68fb      	ldr	r3, [r7, #12]
 8004552:	681b      	ldr	r3, [r3, #0]
 8004554:	4a5e      	ldr	r2, [pc, #376]	@ (80046d0 <UART_SetConfig+0x2d4>)
 8004556:	4293      	cmp	r3, r2
 8004558:	d125      	bne.n	80045a6 <UART_SetConfig+0x1aa>
 800455a:	4b5b      	ldr	r3, [pc, #364]	@ (80046c8 <UART_SetConfig+0x2cc>)
 800455c:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8004560:	f003 0330 	and.w	r3, r3, #48	@ 0x30
 8004564:	2b30      	cmp	r3, #48	@ 0x30
 8004566:	d016      	beq.n	8004596 <UART_SetConfig+0x19a>
 8004568:	2b30      	cmp	r3, #48	@ 0x30
 800456a:	d818      	bhi.n	800459e <UART_SetConfig+0x1a2>
 800456c:	2b20      	cmp	r3, #32
 800456e:	d00a      	beq.n	8004586 <UART_SetConfig+0x18a>
 8004570:	2b20      	cmp	r3, #32
 8004572:	d814      	bhi.n	800459e <UART_SetConfig+0x1a2>
 8004574:	2b00      	cmp	r3, #0
 8004576:	d002      	beq.n	800457e <UART_SetConfig+0x182>
 8004578:	2b10      	cmp	r3, #16
 800457a:	d008      	beq.n	800458e <UART_SetConfig+0x192>
 800457c:	e00f      	b.n	800459e <UART_SetConfig+0x1a2>
 800457e:	2300      	movs	r3, #0
 8004580:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004584:	e0ad      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004586:	2302      	movs	r3, #2
 8004588:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800458c:	e0a9      	b.n	80046e2 <UART_SetConfig+0x2e6>
 800458e:	2304      	movs	r3, #4
 8004590:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004594:	e0a5      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004596:	2308      	movs	r3, #8
 8004598:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800459c:	e0a1      	b.n	80046e2 <UART_SetConfig+0x2e6>
 800459e:	2310      	movs	r3, #16
 80045a0:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80045a4:	e09d      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80045a6:	68fb      	ldr	r3, [r7, #12]
 80045a8:	681b      	ldr	r3, [r3, #0]
 80045aa:	4a4a      	ldr	r2, [pc, #296]	@ (80046d4 <UART_SetConfig+0x2d8>)
 80045ac:	4293      	cmp	r3, r2
 80045ae:	d125      	bne.n	80045fc <UART_SetConfig+0x200>
 80045b0:	4b45      	ldr	r3, [pc, #276]	@ (80046c8 <UART_SetConfig+0x2cc>)
 80045b2:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80045b6:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
 80045ba:	2bc0      	cmp	r3, #192	@ 0xc0
 80045bc:	d016      	beq.n	80045ec <UART_SetConfig+0x1f0>
 80045be:	2bc0      	cmp	r3, #192	@ 0xc0
 80045c0:	d818      	bhi.n	80045f4 <UART_SetConfig+0x1f8>
 80045c2:	2b80      	cmp	r3, #128	@ 0x80
 80045c4:	d00a      	beq.n	80045dc <UART_SetConfig+0x1e0>
 80045c6:	2b80      	cmp	r3, #128	@ 0x80
 80045c8:	d814      	bhi.n	80045f4 <UART_SetConfig+0x1f8>
 80045ca:	2b00      	cmp	r3, #0
 80045cc:	d002      	beq.n	80045d4 <UART_SetConfig+0x1d8>
 80045ce:	2b40      	cmp	r3, #64	@ 0x40
 80045d0:	d008      	beq.n	80045e4 <UART_SetConfig+0x1e8>
 80045d2:	e00f      	b.n	80045f4 <UART_SetConfig+0x1f8>
 80045d4:	2300      	movs	r3, #0
 80045d6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80045da:	e082      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80045dc:	2302      	movs	r3, #2
 80045de:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80045e2:	e07e      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80045e4:	2304      	movs	r3, #4
 80045e6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80045ea:	e07a      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80045ec:	2308      	movs	r3, #8
 80045ee:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80045f2:	e076      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80045f4:	2310      	movs	r3, #16
 80045f6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80045fa:	e072      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80045fc:	68fb      	ldr	r3, [r7, #12]
 80045fe:	681b      	ldr	r3, [r3, #0]
 8004600:	4a35      	ldr	r2, [pc, #212]	@ (80046d8 <UART_SetConfig+0x2dc>)
 8004602:	4293      	cmp	r3, r2
 8004604:	d12a      	bne.n	800465c <UART_SetConfig+0x260>
 8004606:	4b30      	ldr	r3, [pc, #192]	@ (80046c8 <UART_SetConfig+0x2cc>)
 8004608:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800460c:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 8004610:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 8004614:	d01a      	beq.n	800464c <UART_SetConfig+0x250>
 8004616:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 800461a:	d81b      	bhi.n	8004654 <UART_SetConfig+0x258>
 800461c:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 8004620:	d00c      	beq.n	800463c <UART_SetConfig+0x240>
 8004622:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 8004626:	d815      	bhi.n	8004654 <UART_SetConfig+0x258>
 8004628:	2b00      	cmp	r3, #0
 800462a:	d003      	beq.n	8004634 <UART_SetConfig+0x238>
 800462c:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 8004630:	d008      	beq.n	8004644 <UART_SetConfig+0x248>
 8004632:	e00f      	b.n	8004654 <UART_SetConfig+0x258>
 8004634:	2300      	movs	r3, #0
 8004636:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800463a:	e052      	b.n	80046e2 <UART_SetConfig+0x2e6>
 800463c:	2302      	movs	r3, #2
 800463e:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004642:	e04e      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004644:	2304      	movs	r3, #4
 8004646:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800464a:	e04a      	b.n	80046e2 <UART_SetConfig+0x2e6>
 800464c:	2308      	movs	r3, #8
 800464e:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004652:	e046      	b.n	80046e2 <UART_SetConfig+0x2e6>
 8004654:	2310      	movs	r3, #16
 8004656:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800465a:	e042      	b.n	80046e2 <UART_SetConfig+0x2e6>
 800465c:	68fb      	ldr	r3, [r7, #12]
 800465e:	681b      	ldr	r3, [r3, #0]
 8004660:	4a17      	ldr	r2, [pc, #92]	@ (80046c0 <UART_SetConfig+0x2c4>)
 8004662:	4293      	cmp	r3, r2
 8004664:	d13a      	bne.n	80046dc <UART_SetConfig+0x2e0>
 8004666:	4b18      	ldr	r3, [pc, #96]	@ (80046c8 <UART_SetConfig+0x2cc>)
 8004668:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800466c:	f403 6340 	and.w	r3, r3, #3072	@ 0xc00
 8004670:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 8004674:	d01a      	beq.n	80046ac <UART_SetConfig+0x2b0>
 8004676:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 800467a:	d81b      	bhi.n	80046b4 <UART_SetConfig+0x2b8>
 800467c:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8004680:	d00c      	beq.n	800469c <UART_SetConfig+0x2a0>
 8004682:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8004686:	d815      	bhi.n	80046b4 <UART_SetConfig+0x2b8>
 8004688:	2b00      	cmp	r3, #0
 800468a:	d003      	beq.n	8004694 <UART_SetConfig+0x298>
 800468c:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 8004690:	d008      	beq.n	80046a4 <UART_SetConfig+0x2a8>
 8004692:	e00f      	b.n	80046b4 <UART_SetConfig+0x2b8>
 8004694:	2300      	movs	r3, #0
 8004696:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 800469a:	e022      	b.n	80046e2 <UART_SetConfig+0x2e6>
 800469c:	2302      	movs	r3, #2
 800469e:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80046a2:	e01e      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80046a4:	2304      	movs	r3, #4
 80046a6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80046aa:	e01a      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80046ac:	2308      	movs	r3, #8
 80046ae:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80046b2:	e016      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80046b4:	2310      	movs	r3, #16
 80046b6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 80046ba:	e012      	b.n	80046e2 <UART_SetConfig+0x2e6>
 80046bc:	efff69f3 	.word	0xefff69f3
 80046c0:	40008000 	.word	0x40008000
 80046c4:	40013800 	.word	0x40013800
 80046c8:	40021000 	.word	0x40021000
 80046cc:	40004400 	.word	0x40004400
 80046d0:	40004800 	.word	0x40004800
 80046d4:	40004c00 	.word	0x40004c00
 80046d8:	40005000 	.word	0x40005000
 80046dc:	2310      	movs	r3, #16
 80046de:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23

  /* Check LPUART instance */
  if (UART_INSTANCE_LOWPOWER(huart))
 80046e2:	68fb      	ldr	r3, [r7, #12]
 80046e4:	681b      	ldr	r3, [r3, #0]
 80046e6:	4a9f      	ldr	r2, [pc, #636]	@ (8004964 <UART_SetConfig+0x568>)
 80046e8:	4293      	cmp	r3, r2
 80046ea:	d17a      	bne.n	80047e2 <UART_SetConfig+0x3e6>
  {
    /* Retrieve frequency clock */
    switch (clocksource)
 80046ec:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 80046f0:	2b08      	cmp	r3, #8
 80046f2:	d824      	bhi.n	800473e <UART_SetConfig+0x342>
 80046f4:	a201      	add	r2, pc, #4	@ (adr r2, 80046fc <UART_SetConfig+0x300>)
 80046f6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80046fa:	bf00      	nop
 80046fc:	08004721 	.word	0x08004721
 8004700:	0800473f 	.word	0x0800473f
 8004704:	08004729 	.word	0x08004729
 8004708:	0800473f 	.word	0x0800473f
 800470c:	0800472f 	.word	0x0800472f
 8004710:	0800473f 	.word	0x0800473f
 8004714:	0800473f 	.word	0x0800473f
 8004718:	0800473f 	.word	0x0800473f
 800471c:	08004737 	.word	0x08004737
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8004720:	f7fe fd2c 	bl	800317c <HAL_RCC_GetPCLK1Freq>
 8004724:	61f8      	str	r0, [r7, #28]
        break;
 8004726:	e010      	b.n	800474a <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8004728:	4b8f      	ldr	r3, [pc, #572]	@ (8004968 <UART_SetConfig+0x56c>)
 800472a:	61fb      	str	r3, [r7, #28]
        break;
 800472c:	e00d      	b.n	800474a <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 800472e:	f7fe fc8d 	bl	800304c <HAL_RCC_GetSysClockFreq>
 8004732:	61f8      	str	r0, [r7, #28]
        break;
 8004734:	e009      	b.n	800474a <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8004736:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 800473a:	61fb      	str	r3, [r7, #28]
        break;
 800473c:	e005      	b.n	800474a <UART_SetConfig+0x34e>
      default:
        pclk = 0U;
 800473e:	2300      	movs	r3, #0
 8004740:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8004742:	2301      	movs	r3, #1
 8004744:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 8004748:	bf00      	nop
    }

    /* If proper clock source reported */
    if (pclk != 0U)
 800474a:	69fb      	ldr	r3, [r7, #28]
 800474c:	2b00      	cmp	r3, #0
 800474e:	f000 80fb 	beq.w	8004948 <UART_SetConfig+0x54c>
      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
#else
      /* No Prescaler applicable */
      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
      if ((pclk < (3U * huart->Init.BaudRate)) ||
 8004752:	68fb      	ldr	r3, [r7, #12]
 8004754:	685a      	ldr	r2, [r3, #4]
 8004756:	4613      	mov	r3, r2
 8004758:	005b      	lsls	r3, r3, #1
 800475a:	4413      	add	r3, r2
 800475c:	69fa      	ldr	r2, [r7, #28]
 800475e:	429a      	cmp	r2, r3
 8004760:	d305      	bcc.n	800476e <UART_SetConfig+0x372>
          (pclk > (4096U * huart->Init.BaudRate)))
 8004762:	68fb      	ldr	r3, [r7, #12]
 8004764:	685b      	ldr	r3, [r3, #4]
 8004766:	031b      	lsls	r3, r3, #12
      if ((pclk < (3U * huart->Init.BaudRate)) ||
 8004768:	69fa      	ldr	r2, [r7, #28]
 800476a:	429a      	cmp	r2, r3
 800476c:	d903      	bls.n	8004776 <UART_SetConfig+0x37a>
      {
        ret = HAL_ERROR;
 800476e:	2301      	movs	r3, #1
 8004770:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 8004774:	e0e8      	b.n	8004948 <UART_SetConfig+0x54c>
      }
      else
      {
        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
 8004776:	69fb      	ldr	r3, [r7, #28]
 8004778:	2200      	movs	r2, #0
 800477a:	461c      	mov	r4, r3
 800477c:	4615      	mov	r5, r2
 800477e:	f04f 0200 	mov.w	r2, #0
 8004782:	f04f 0300 	mov.w	r3, #0
 8004786:	022b      	lsls	r3, r5, #8
 8004788:	ea43 6314 	orr.w	r3, r3, r4, lsr #24
 800478c:	0222      	lsls	r2, r4, #8
 800478e:	68f9      	ldr	r1, [r7, #12]
 8004790:	6849      	ldr	r1, [r1, #4]
 8004792:	0849      	lsrs	r1, r1, #1
 8004794:	2000      	movs	r0, #0
 8004796:	4688      	mov	r8, r1
 8004798:	4681      	mov	r9, r0
 800479a:	eb12 0a08 	adds.w	sl, r2, r8
 800479e:	eb43 0b09 	adc.w	fp, r3, r9
 80047a2:	68fb      	ldr	r3, [r7, #12]
 80047a4:	685b      	ldr	r3, [r3, #4]
 80047a6:	2200      	movs	r2, #0
 80047a8:	603b      	str	r3, [r7, #0]
 80047aa:	607a      	str	r2, [r7, #4]
 80047ac:	e9d7 2300 	ldrd	r2, r3, [r7]
 80047b0:	4650      	mov	r0, sl
 80047b2:	4659      	mov	r1, fp
 80047b4:	f7fb fd0c 	bl	80001d0 <__aeabi_uldivmod>
 80047b8:	4602      	mov	r2, r0
 80047ba:	460b      	mov	r3, r1
 80047bc:	4613      	mov	r3, r2
 80047be:	61bb      	str	r3, [r7, #24]
        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
 80047c0:	69bb      	ldr	r3, [r7, #24]
 80047c2:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 80047c6:	d308      	bcc.n	80047da <UART_SetConfig+0x3de>
 80047c8:	69bb      	ldr	r3, [r7, #24]
 80047ca:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 80047ce:	d204      	bcs.n	80047da <UART_SetConfig+0x3de>
        {
          huart->Instance->BRR = usartdiv;
 80047d0:	68fb      	ldr	r3, [r7, #12]
 80047d2:	681b      	ldr	r3, [r3, #0]
 80047d4:	69ba      	ldr	r2, [r7, #24]
 80047d6:	60da      	str	r2, [r3, #12]
 80047d8:	e0b6      	b.n	8004948 <UART_SetConfig+0x54c>
        }
        else
        {
          ret = HAL_ERROR;
 80047da:	2301      	movs	r3, #1
 80047dc:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 80047e0:	e0b2      	b.n	8004948 <UART_SetConfig+0x54c>
      } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
#endif /* USART_PRESC_PRESCALER */
    } /* if (pclk != 0) */
  }
  /* Check UART Over Sampling to set Baud Rate Register */
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 80047e2:	68fb      	ldr	r3, [r7, #12]
 80047e4:	69db      	ldr	r3, [r3, #28]
 80047e6:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 80047ea:	d15e      	bne.n	80048aa <UART_SetConfig+0x4ae>
  {
    switch (clocksource)
 80047ec:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 80047f0:	2b08      	cmp	r3, #8
 80047f2:	d828      	bhi.n	8004846 <UART_SetConfig+0x44a>
 80047f4:	a201      	add	r2, pc, #4	@ (adr r2, 80047fc <UART_SetConfig+0x400>)
 80047f6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80047fa:	bf00      	nop
 80047fc:	08004821 	.word	0x08004821
 8004800:	08004829 	.word	0x08004829
 8004804:	08004831 	.word	0x08004831
 8004808:	08004847 	.word	0x08004847
 800480c:	08004837 	.word	0x08004837
 8004810:	08004847 	.word	0x08004847
 8004814:	08004847 	.word	0x08004847
 8004818:	08004847 	.word	0x08004847
 800481c:	0800483f 	.word	0x0800483f
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8004820:	f7fe fcac 	bl	800317c <HAL_RCC_GetPCLK1Freq>
 8004824:	61f8      	str	r0, [r7, #28]
        break;
 8004826:	e014      	b.n	8004852 <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 8004828:	f7fe fcbe 	bl	80031a8 <HAL_RCC_GetPCLK2Freq>
 800482c:	61f8      	str	r0, [r7, #28]
        break;
 800482e:	e010      	b.n	8004852 <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8004830:	4b4d      	ldr	r3, [pc, #308]	@ (8004968 <UART_SetConfig+0x56c>)
 8004832:	61fb      	str	r3, [r7, #28]
        break;
 8004834:	e00d      	b.n	8004852 <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 8004836:	f7fe fc09 	bl	800304c <HAL_RCC_GetSysClockFreq>
 800483a:	61f8      	str	r0, [r7, #28]
        break;
 800483c:	e009      	b.n	8004852 <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 800483e:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8004842:	61fb      	str	r3, [r7, #28]
        break;
 8004844:	e005      	b.n	8004852 <UART_SetConfig+0x456>
      default:
        pclk = 0U;
 8004846:	2300      	movs	r3, #0
 8004848:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 800484a:	2301      	movs	r3, #1
 800484c:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 8004850:	bf00      	nop
    }

    /* USARTDIV must be greater than or equal to 0d16 */
    if (pclk != 0U)
 8004852:	69fb      	ldr	r3, [r7, #28]
 8004854:	2b00      	cmp	r3, #0
 8004856:	d077      	beq.n	8004948 <UART_SetConfig+0x54c>
    {
#if defined(USART_PRESC_PRESCALER)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
 8004858:	69fb      	ldr	r3, [r7, #28]
 800485a:	005a      	lsls	r2, r3, #1
 800485c:	68fb      	ldr	r3, [r7, #12]
 800485e:	685b      	ldr	r3, [r3, #4]
 8004860:	085b      	lsrs	r3, r3, #1
 8004862:	441a      	add	r2, r3
 8004864:	68fb      	ldr	r3, [r7, #12]
 8004866:	685b      	ldr	r3, [r3, #4]
 8004868:	fbb2 f3f3 	udiv	r3, r2, r3
 800486c:	61bb      	str	r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 800486e:	69bb      	ldr	r3, [r7, #24]
 8004870:	2b0f      	cmp	r3, #15
 8004872:	d916      	bls.n	80048a2 <UART_SetConfig+0x4a6>
 8004874:	69bb      	ldr	r3, [r7, #24]
 8004876:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800487a:	d212      	bcs.n	80048a2 <UART_SetConfig+0x4a6>
      {
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 800487c:	69bb      	ldr	r3, [r7, #24]
 800487e:	b29b      	uxth	r3, r3
 8004880:	f023 030f 	bic.w	r3, r3, #15
 8004884:	82fb      	strh	r3, [r7, #22]
        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
 8004886:	69bb      	ldr	r3, [r7, #24]
 8004888:	085b      	lsrs	r3, r3, #1
 800488a:	b29b      	uxth	r3, r3
 800488c:	f003 0307 	and.w	r3, r3, #7
 8004890:	b29a      	uxth	r2, r3
 8004892:	8afb      	ldrh	r3, [r7, #22]
 8004894:	4313      	orrs	r3, r2
 8004896:	82fb      	strh	r3, [r7, #22]
        huart->Instance->BRR = brrtemp;
 8004898:	68fb      	ldr	r3, [r7, #12]
 800489a:	681b      	ldr	r3, [r3, #0]
 800489c:	8afa      	ldrh	r2, [r7, #22]
 800489e:	60da      	str	r2, [r3, #12]
 80048a0:	e052      	b.n	8004948 <UART_SetConfig+0x54c>
      }
      else
      {
        ret = HAL_ERROR;
 80048a2:	2301      	movs	r3, #1
 80048a4:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 80048a8:	e04e      	b.n	8004948 <UART_SetConfig+0x54c>
      }
    }
  }
  else
  {
    switch (clocksource)
 80048aa:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 80048ae:	2b08      	cmp	r3, #8
 80048b0:	d827      	bhi.n	8004902 <UART_SetConfig+0x506>
 80048b2:	a201      	add	r2, pc, #4	@ (adr r2, 80048b8 <UART_SetConfig+0x4bc>)
 80048b4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80048b8:	080048dd 	.word	0x080048dd
 80048bc:	080048e5 	.word	0x080048e5
 80048c0:	080048ed 	.word	0x080048ed
 80048c4:	08004903 	.word	0x08004903
 80048c8:	080048f3 	.word	0x080048f3
 80048cc:	08004903 	.word	0x08004903
 80048d0:	08004903 	.word	0x08004903
 80048d4:	08004903 	.word	0x08004903
 80048d8:	080048fb 	.word	0x080048fb
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 80048dc:	f7fe fc4e 	bl	800317c <HAL_RCC_GetPCLK1Freq>
 80048e0:	61f8      	str	r0, [r7, #28]
        break;
 80048e2:	e014      	b.n	800490e <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 80048e4:	f7fe fc60 	bl	80031a8 <HAL_RCC_GetPCLK2Freq>
 80048e8:	61f8      	str	r0, [r7, #28]
        break;
 80048ea:	e010      	b.n	800490e <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 80048ec:	4b1e      	ldr	r3, [pc, #120]	@ (8004968 <UART_SetConfig+0x56c>)
 80048ee:	61fb      	str	r3, [r7, #28]
        break;
 80048f0:	e00d      	b.n	800490e <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 80048f2:	f7fe fbab 	bl	800304c <HAL_RCC_GetSysClockFreq>
 80048f6:	61f8      	str	r0, [r7, #28]
        break;
 80048f8:	e009      	b.n	800490e <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 80048fa:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 80048fe:	61fb      	str	r3, [r7, #28]
        break;
 8004900:	e005      	b.n	800490e <UART_SetConfig+0x512>
      default:
        pclk = 0U;
 8004902:	2300      	movs	r3, #0
 8004904:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8004906:	2301      	movs	r3, #1
 8004908:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 800490c:	bf00      	nop
    }

    if (pclk != 0U)
 800490e:	69fb      	ldr	r3, [r7, #28]
 8004910:	2b00      	cmp	r3, #0
 8004912:	d019      	beq.n	8004948 <UART_SetConfig+0x54c>
    {
      /* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
 8004914:	68fb      	ldr	r3, [r7, #12]
 8004916:	685b      	ldr	r3, [r3, #4]
 8004918:	085a      	lsrs	r2, r3, #1
 800491a:	69fb      	ldr	r3, [r7, #28]
 800491c:	441a      	add	r2, r3
 800491e:	68fb      	ldr	r3, [r7, #12]
 8004920:	685b      	ldr	r3, [r3, #4]
 8004922:	fbb2 f3f3 	udiv	r3, r2, r3
 8004926:	61bb      	str	r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8004928:	69bb      	ldr	r3, [r7, #24]
 800492a:	2b0f      	cmp	r3, #15
 800492c:	d909      	bls.n	8004942 <UART_SetConfig+0x546>
 800492e:	69bb      	ldr	r3, [r7, #24]
 8004930:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8004934:	d205      	bcs.n	8004942 <UART_SetConfig+0x546>
      {
        huart->Instance->BRR = (uint16_t)usartdiv;
 8004936:	69bb      	ldr	r3, [r7, #24]
 8004938:	b29a      	uxth	r2, r3
 800493a:	68fb      	ldr	r3, [r7, #12]
 800493c:	681b      	ldr	r3, [r3, #0]
 800493e:	60da      	str	r2, [r3, #12]
 8004940:	e002      	b.n	8004948 <UART_SetConfig+0x54c>
      }
      else
      {
        ret = HAL_ERROR;
 8004942:	2301      	movs	r3, #1
 8004944:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
  huart->NbTxDataToProcess = 1;
  huart->NbRxDataToProcess = 1;
#endif /* USART_CR1_FIFOEN */

  /* Clear ISR function pointers */
  huart->RxISR = NULL;
 8004948:	68fb      	ldr	r3, [r7, #12]
 800494a:	2200      	movs	r2, #0
 800494c:	669a      	str	r2, [r3, #104]	@ 0x68
  huart->TxISR = NULL;
 800494e:	68fb      	ldr	r3, [r7, #12]
 8004950:	2200      	movs	r2, #0
 8004952:	66da      	str	r2, [r3, #108]	@ 0x6c

  return ret;
 8004954:	f897 3022 	ldrb.w	r3, [r7, #34]	@ 0x22
}
 8004958:	4618      	mov	r0, r3
 800495a:	3728      	adds	r7, #40	@ 0x28
 800495c:	46bd      	mov	sp, r7
 800495e:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8004962:	bf00      	nop
 8004964:	40008000 	.word	0x40008000
 8004968:	00f42400 	.word	0x00f42400

0800496c <UART_AdvFeatureConfig>:
  * @brief Configure the UART peripheral advanced features.
  * @param huart UART handle.
  * @retval None
  */
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
 800496c:	b480      	push	{r7}
 800496e:	b083      	sub	sp, #12
 8004970:	af00      	add	r7, sp, #0
 8004972:	6078      	str	r0, [r7, #4]
  /* Check whether the set of advanced features to configure is properly set */
  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));

  /* if required, configure RX/TX pins swap */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 8004974:	687b      	ldr	r3, [r7, #4]
 8004976:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004978:	f003 0308 	and.w	r3, r3, #8
 800497c:	2b00      	cmp	r3, #0
 800497e:	d00a      	beq.n	8004996 <UART_AdvFeatureConfig+0x2a>
  {
    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
 8004980:	687b      	ldr	r3, [r7, #4]
 8004982:	681b      	ldr	r3, [r3, #0]
 8004984:	685b      	ldr	r3, [r3, #4]
 8004986:	f423 4100 	bic.w	r1, r3, #32768	@ 0x8000
 800498a:	687b      	ldr	r3, [r7, #4]
 800498c:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 800498e:	687b      	ldr	r3, [r7, #4]
 8004990:	681b      	ldr	r3, [r3, #0]
 8004992:	430a      	orrs	r2, r1
 8004994:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure TX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
 8004996:	687b      	ldr	r3, [r7, #4]
 8004998:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800499a:	f003 0301 	and.w	r3, r3, #1
 800499e:	2b00      	cmp	r3, #0
 80049a0:	d00a      	beq.n	80049b8 <UART_AdvFeatureConfig+0x4c>
  {
    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
 80049a2:	687b      	ldr	r3, [r7, #4]
 80049a4:	681b      	ldr	r3, [r3, #0]
 80049a6:	685b      	ldr	r3, [r3, #4]
 80049a8:	f423 3100 	bic.w	r1, r3, #131072	@ 0x20000
 80049ac:	687b      	ldr	r3, [r7, #4]
 80049ae:	6a9a      	ldr	r2, [r3, #40]	@ 0x28
 80049b0:	687b      	ldr	r3, [r7, #4]
 80049b2:	681b      	ldr	r3, [r3, #0]
 80049b4:	430a      	orrs	r2, r1
 80049b6:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
 80049b8:	687b      	ldr	r3, [r7, #4]
 80049ba:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80049bc:	f003 0302 	and.w	r3, r3, #2
 80049c0:	2b00      	cmp	r3, #0
 80049c2:	d00a      	beq.n	80049da <UART_AdvFeatureConfig+0x6e>
  {
    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
 80049c4:	687b      	ldr	r3, [r7, #4]
 80049c6:	681b      	ldr	r3, [r3, #0]
 80049c8:	685b      	ldr	r3, [r3, #4]
 80049ca:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
 80049ce:	687b      	ldr	r3, [r7, #4]
 80049d0:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80049d2:	687b      	ldr	r3, [r7, #4]
 80049d4:	681b      	ldr	r3, [r3, #0]
 80049d6:	430a      	orrs	r2, r1
 80049d8:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure data inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
 80049da:	687b      	ldr	r3, [r7, #4]
 80049dc:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80049de:	f003 0304 	and.w	r3, r3, #4
 80049e2:	2b00      	cmp	r3, #0
 80049e4:	d00a      	beq.n	80049fc <UART_AdvFeatureConfig+0x90>
  {
    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
 80049e6:	687b      	ldr	r3, [r7, #4]
 80049e8:	681b      	ldr	r3, [r3, #0]
 80049ea:	685b      	ldr	r3, [r3, #4]
 80049ec:	f423 2180 	bic.w	r1, r3, #262144	@ 0x40000
 80049f0:	687b      	ldr	r3, [r7, #4]
 80049f2:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 80049f4:	687b      	ldr	r3, [r7, #4]
 80049f6:	681b      	ldr	r3, [r3, #0]
 80049f8:	430a      	orrs	r2, r1
 80049fa:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX overrun detection disabling */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
 80049fc:	687b      	ldr	r3, [r7, #4]
 80049fe:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004a00:	f003 0310 	and.w	r3, r3, #16
 8004a04:	2b00      	cmp	r3, #0
 8004a06:	d00a      	beq.n	8004a1e <UART_AdvFeatureConfig+0xb2>
  {
    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
 8004a08:	687b      	ldr	r3, [r7, #4]
 8004a0a:	681b      	ldr	r3, [r3, #0]
 8004a0c:	689b      	ldr	r3, [r3, #8]
 8004a0e:	f423 5180 	bic.w	r1, r3, #4096	@ 0x1000
 8004a12:	687b      	ldr	r3, [r7, #4]
 8004a14:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8004a16:	687b      	ldr	r3, [r7, #4]
 8004a18:	681b      	ldr	r3, [r3, #0]
 8004a1a:	430a      	orrs	r2, r1
 8004a1c:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure DMA disabling on reception error */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
 8004a1e:	687b      	ldr	r3, [r7, #4]
 8004a20:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004a22:	f003 0320 	and.w	r3, r3, #32
 8004a26:	2b00      	cmp	r3, #0
 8004a28:	d00a      	beq.n	8004a40 <UART_AdvFeatureConfig+0xd4>
  {
    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
 8004a2a:	687b      	ldr	r3, [r7, #4]
 8004a2c:	681b      	ldr	r3, [r3, #0]
 8004a2e:	689b      	ldr	r3, [r3, #8]
 8004a30:	f423 5100 	bic.w	r1, r3, #8192	@ 0x2000
 8004a34:	687b      	ldr	r3, [r7, #4]
 8004a36:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 8004a38:	687b      	ldr	r3, [r7, #4]
 8004a3a:	681b      	ldr	r3, [r3, #0]
 8004a3c:	430a      	orrs	r2, r1
 8004a3e:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure auto Baud rate detection scheme */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
 8004a40:	687b      	ldr	r3, [r7, #4]
 8004a42:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004a44:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8004a48:	2b00      	cmp	r3, #0
 8004a4a:	d01a      	beq.n	8004a82 <UART_AdvFeatureConfig+0x116>
  {
    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 8004a4c:	687b      	ldr	r3, [r7, #4]
 8004a4e:	681b      	ldr	r3, [r3, #0]
 8004a50:	685b      	ldr	r3, [r3, #4]
 8004a52:	f423 1180 	bic.w	r1, r3, #1048576	@ 0x100000
 8004a56:	687b      	ldr	r3, [r7, #4]
 8004a58:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
 8004a5a:	687b      	ldr	r3, [r7, #4]
 8004a5c:	681b      	ldr	r3, [r3, #0]
 8004a5e:	430a      	orrs	r2, r1
 8004a60:	605a      	str	r2, [r3, #4]
    /* set auto Baudrate detection parameters if detection is enabled */
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 8004a62:	687b      	ldr	r3, [r7, #4]
 8004a64:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8004a66:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 8004a6a:	d10a      	bne.n	8004a82 <UART_AdvFeatureConfig+0x116>
    {
      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
 8004a6c:	687b      	ldr	r3, [r7, #4]
 8004a6e:	681b      	ldr	r3, [r3, #0]
 8004a70:	685b      	ldr	r3, [r3, #4]
 8004a72:	f423 01c0 	bic.w	r1, r3, #6291456	@ 0x600000
 8004a76:	687b      	ldr	r3, [r7, #4]
 8004a78:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 8004a7a:	687b      	ldr	r3, [r7, #4]
 8004a7c:	681b      	ldr	r3, [r3, #0]
 8004a7e:	430a      	orrs	r2, r1
 8004a80:	605a      	str	r2, [r3, #4]
    }
  }

  /* if required, configure MSB first on communication line */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
 8004a82:	687b      	ldr	r3, [r7, #4]
 8004a84:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004a86:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8004a8a:	2b00      	cmp	r3, #0
 8004a8c:	d00a      	beq.n	8004aa4 <UART_AdvFeatureConfig+0x138>
  {
    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
 8004a8e:	687b      	ldr	r3, [r7, #4]
 8004a90:	681b      	ldr	r3, [r3, #0]
 8004a92:	685b      	ldr	r3, [r3, #4]
 8004a94:	f423 2100 	bic.w	r1, r3, #524288	@ 0x80000
 8004a98:	687b      	ldr	r3, [r7, #4]
 8004a9a:	6c9a      	ldr	r2, [r3, #72]	@ 0x48
 8004a9c:	687b      	ldr	r3, [r7, #4]
 8004a9e:	681b      	ldr	r3, [r3, #0]
 8004aa0:	430a      	orrs	r2, r1
 8004aa2:	605a      	str	r2, [r3, #4]
  }
}
 8004aa4:	bf00      	nop
 8004aa6:	370c      	adds	r7, #12
 8004aa8:	46bd      	mov	sp, r7
 8004aaa:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004aae:	4770      	bx	lr

08004ab0 <UART_CheckIdleState>:
  * @brief Check the UART Idle State.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
 8004ab0:	b580      	push	{r7, lr}
 8004ab2:	b098      	sub	sp, #96	@ 0x60
 8004ab4:	af02      	add	r7, sp, #8
 8004ab6:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  /* Initialize the UART ErrorCode */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8004ab8:	687b      	ldr	r3, [r7, #4]
 8004aba:	2200      	movs	r2, #0
 8004abc:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

  /* Init tickstart for timeout management */
  tickstart = HAL_GetTick();
 8004ac0:	f7fc fe28 	bl	8001714 <HAL_GetTick>
 8004ac4:	6578      	str	r0, [r7, #84]	@ 0x54

  /* Check if the Transmitter is enabled */
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 8004ac6:	687b      	ldr	r3, [r7, #4]
 8004ac8:	681b      	ldr	r3, [r3, #0]
 8004aca:	681b      	ldr	r3, [r3, #0]
 8004acc:	f003 0308 	and.w	r3, r3, #8
 8004ad0:	2b08      	cmp	r3, #8
 8004ad2:	d12e      	bne.n	8004b32 <UART_CheckIdleState+0x82>
  {
    /* Wait until TEACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 8004ad4:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 8004ad8:	9300      	str	r3, [sp, #0]
 8004ada:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8004adc:	2200      	movs	r2, #0
 8004ade:	f44f 1100 	mov.w	r1, #2097152	@ 0x200000
 8004ae2:	6878      	ldr	r0, [r7, #4]
 8004ae4:	f000 f88c 	bl	8004c00 <UART_WaitOnFlagUntilTimeout>
 8004ae8:	4603      	mov	r3, r0
 8004aea:	2b00      	cmp	r3, #0
 8004aec:	d021      	beq.n	8004b32 <UART_CheckIdleState+0x82>
    {
      /* Disable TXE interrupt for the interrupt process */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
 8004aee:	687b      	ldr	r3, [r7, #4]
 8004af0:	681b      	ldr	r3, [r3, #0]
 8004af2:	63bb      	str	r3, [r7, #56]	@ 0x38
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004af4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8004af6:	e853 3f00 	ldrex	r3, [r3]
 8004afa:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 8004afc:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8004afe:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 8004b02:	653b      	str	r3, [r7, #80]	@ 0x50
 8004b04:	687b      	ldr	r3, [r7, #4]
 8004b06:	681b      	ldr	r3, [r3, #0]
 8004b08:	461a      	mov	r2, r3
 8004b0a:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8004b0c:	647b      	str	r3, [r7, #68]	@ 0x44
 8004b0e:	643a      	str	r2, [r7, #64]	@ 0x40
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004b10:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 8004b12:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 8004b14:	e841 2300 	strex	r3, r2, [r1]
 8004b18:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 8004b1a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8004b1c:	2b00      	cmp	r3, #0
 8004b1e:	d1e6      	bne.n	8004aee <UART_CheckIdleState+0x3e>
#endif /* USART_CR1_FIFOEN */

      huart->gState = HAL_UART_STATE_READY;
 8004b20:	687b      	ldr	r3, [r7, #4]
 8004b22:	2220      	movs	r2, #32
 8004b24:	67da      	str	r2, [r3, #124]	@ 0x7c

      __HAL_UNLOCK(huart);
 8004b26:	687b      	ldr	r3, [r7, #4]
 8004b28:	2200      	movs	r2, #0
 8004b2a:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

      /* Timeout occurred */
      return HAL_TIMEOUT;
 8004b2e:	2303      	movs	r3, #3
 8004b30:	e062      	b.n	8004bf8 <UART_CheckIdleState+0x148>
    }
  }

  /* Check if the Receiver is enabled */
  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
 8004b32:	687b      	ldr	r3, [r7, #4]
 8004b34:	681b      	ldr	r3, [r3, #0]
 8004b36:	681b      	ldr	r3, [r3, #0]
 8004b38:	f003 0304 	and.w	r3, r3, #4
 8004b3c:	2b04      	cmp	r3, #4
 8004b3e:	d149      	bne.n	8004bd4 <UART_CheckIdleState+0x124>
  {
    /* Wait until REACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 8004b40:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 8004b44:	9300      	str	r3, [sp, #0]
 8004b46:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8004b48:	2200      	movs	r2, #0
 8004b4a:	f44f 0180 	mov.w	r1, #4194304	@ 0x400000
 8004b4e:	6878      	ldr	r0, [r7, #4]
 8004b50:	f000 f856 	bl	8004c00 <UART_WaitOnFlagUntilTimeout>
 8004b54:	4603      	mov	r3, r0
 8004b56:	2b00      	cmp	r3, #0
 8004b58:	d03c      	beq.n	8004bd4 <UART_CheckIdleState+0x124>
      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
      interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8004b5a:	687b      	ldr	r3, [r7, #4]
 8004b5c:	681b      	ldr	r3, [r3, #0]
 8004b5e:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004b60:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8004b62:	e853 3f00 	ldrex	r3, [r3]
 8004b66:	623b      	str	r3, [r7, #32]
   return(result);
 8004b68:	6a3b      	ldr	r3, [r7, #32]
 8004b6a:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8004b6e:	64fb      	str	r3, [r7, #76]	@ 0x4c
 8004b70:	687b      	ldr	r3, [r7, #4]
 8004b72:	681b      	ldr	r3, [r3, #0]
 8004b74:	461a      	mov	r2, r3
 8004b76:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8004b78:	633b      	str	r3, [r7, #48]	@ 0x30
 8004b7a:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004b7c:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 8004b7e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8004b80:	e841 2300 	strex	r3, r2, [r1]
 8004b84:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 8004b86:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8004b88:	2b00      	cmp	r3, #0
 8004b8a:	d1e6      	bne.n	8004b5a <UART_CheckIdleState+0xaa>
#endif /* USART_CR1_FIFOEN */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8004b8c:	687b      	ldr	r3, [r7, #4]
 8004b8e:	681b      	ldr	r3, [r3, #0]
 8004b90:	3308      	adds	r3, #8
 8004b92:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004b94:	693b      	ldr	r3, [r7, #16]
 8004b96:	e853 3f00 	ldrex	r3, [r3]
 8004b9a:	60fb      	str	r3, [r7, #12]
   return(result);
 8004b9c:	68fb      	ldr	r3, [r7, #12]
 8004b9e:	f023 0301 	bic.w	r3, r3, #1
 8004ba2:	64bb      	str	r3, [r7, #72]	@ 0x48
 8004ba4:	687b      	ldr	r3, [r7, #4]
 8004ba6:	681b      	ldr	r3, [r3, #0]
 8004ba8:	3308      	adds	r3, #8
 8004baa:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 8004bac:	61fa      	str	r2, [r7, #28]
 8004bae:	61bb      	str	r3, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004bb0:	69b9      	ldr	r1, [r7, #24]
 8004bb2:	69fa      	ldr	r2, [r7, #28]
 8004bb4:	e841 2300 	strex	r3, r2, [r1]
 8004bb8:	617b      	str	r3, [r7, #20]
   return(result);
 8004bba:	697b      	ldr	r3, [r7, #20]
 8004bbc:	2b00      	cmp	r3, #0
 8004bbe:	d1e5      	bne.n	8004b8c <UART_CheckIdleState+0xdc>

      huart->RxState = HAL_UART_STATE_READY;
 8004bc0:	687b      	ldr	r3, [r7, #4]
 8004bc2:	2220      	movs	r2, #32
 8004bc4:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80

      __HAL_UNLOCK(huart);
 8004bc8:	687b      	ldr	r3, [r7, #4]
 8004bca:	2200      	movs	r2, #0
 8004bcc:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

      /* Timeout occurred */
      return HAL_TIMEOUT;
 8004bd0:	2303      	movs	r3, #3
 8004bd2:	e011      	b.n	8004bf8 <UART_CheckIdleState+0x148>
    }
  }

  /* Initialize the UART State */
  huart->gState = HAL_UART_STATE_READY;
 8004bd4:	687b      	ldr	r3, [r7, #4]
 8004bd6:	2220      	movs	r2, #32
 8004bd8:	67da      	str	r2, [r3, #124]	@ 0x7c
  huart->RxState = HAL_UART_STATE_READY;
 8004bda:	687b      	ldr	r3, [r7, #4]
 8004bdc:	2220      	movs	r2, #32
 8004bde:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8004be2:	687b      	ldr	r3, [r7, #4]
 8004be4:	2200      	movs	r2, #0
 8004be6:	661a      	str	r2, [r3, #96]	@ 0x60
  huart->RxEventType = HAL_UART_RXEVENT_TC;
 8004be8:	687b      	ldr	r3, [r7, #4]
 8004bea:	2200      	movs	r2, #0
 8004bec:	665a      	str	r2, [r3, #100]	@ 0x64

  __HAL_UNLOCK(huart);
 8004bee:	687b      	ldr	r3, [r7, #4]
 8004bf0:	2200      	movs	r2, #0
 8004bf2:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

  return HAL_OK;
 8004bf6:	2300      	movs	r3, #0
}
 8004bf8:	4618      	mov	r0, r3
 8004bfa:	3758      	adds	r7, #88	@ 0x58
 8004bfc:	46bd      	mov	sp, r7
 8004bfe:	bd80      	pop	{r7, pc}

08004c00 <UART_WaitOnFlagUntilTimeout>:
  * @param Timeout   Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                              uint32_t Tickstart, uint32_t Timeout)
{
 8004c00:	b580      	push	{r7, lr}
 8004c02:	b084      	sub	sp, #16
 8004c04:	af00      	add	r7, sp, #0
 8004c06:	60f8      	str	r0, [r7, #12]
 8004c08:	60b9      	str	r1, [r7, #8]
 8004c0a:	603b      	str	r3, [r7, #0]
 8004c0c:	4613      	mov	r3, r2
 8004c0e:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8004c10:	e04f      	b.n	8004cb2 <UART_WaitOnFlagUntilTimeout+0xb2>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8004c12:	69bb      	ldr	r3, [r7, #24]
 8004c14:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8004c18:	d04b      	beq.n	8004cb2 <UART_WaitOnFlagUntilTimeout+0xb2>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8004c1a:	f7fc fd7b 	bl	8001714 <HAL_GetTick>
 8004c1e:	4602      	mov	r2, r0
 8004c20:	683b      	ldr	r3, [r7, #0]
 8004c22:	1ad3      	subs	r3, r2, r3
 8004c24:	69ba      	ldr	r2, [r7, #24]
 8004c26:	429a      	cmp	r2, r3
 8004c28:	d302      	bcc.n	8004c30 <UART_WaitOnFlagUntilTimeout+0x30>
 8004c2a:	69bb      	ldr	r3, [r7, #24]
 8004c2c:	2b00      	cmp	r3, #0
 8004c2e:	d101      	bne.n	8004c34 <UART_WaitOnFlagUntilTimeout+0x34>
      {

        return HAL_TIMEOUT;
 8004c30:	2303      	movs	r3, #3
 8004c32:	e04e      	b.n	8004cd2 <UART_WaitOnFlagUntilTimeout+0xd2>
      }

      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 8004c34:	68fb      	ldr	r3, [r7, #12]
 8004c36:	681b      	ldr	r3, [r3, #0]
 8004c38:	681b      	ldr	r3, [r3, #0]
 8004c3a:	f003 0304 	and.w	r3, r3, #4
 8004c3e:	2b00      	cmp	r3, #0
 8004c40:	d037      	beq.n	8004cb2 <UART_WaitOnFlagUntilTimeout+0xb2>
 8004c42:	68bb      	ldr	r3, [r7, #8]
 8004c44:	2b80      	cmp	r3, #128	@ 0x80
 8004c46:	d034      	beq.n	8004cb2 <UART_WaitOnFlagUntilTimeout+0xb2>
 8004c48:	68bb      	ldr	r3, [r7, #8]
 8004c4a:	2b40      	cmp	r3, #64	@ 0x40
 8004c4c:	d031      	beq.n	8004cb2 <UART_WaitOnFlagUntilTimeout+0xb2>
      {
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 8004c4e:	68fb      	ldr	r3, [r7, #12]
 8004c50:	681b      	ldr	r3, [r3, #0]
 8004c52:	69db      	ldr	r3, [r3, #28]
 8004c54:	f003 0308 	and.w	r3, r3, #8
 8004c58:	2b08      	cmp	r3, #8
 8004c5a:	d110      	bne.n	8004c7e <UART_WaitOnFlagUntilTimeout+0x7e>
        {
          /* Clear Overrun Error flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 8004c5c:	68fb      	ldr	r3, [r7, #12]
 8004c5e:	681b      	ldr	r3, [r3, #0]
 8004c60:	2208      	movs	r2, #8
 8004c62:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 8004c64:	68f8      	ldr	r0, [r7, #12]
 8004c66:	f000 f838 	bl	8004cda <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_ORE;
 8004c6a:	68fb      	ldr	r3, [r7, #12]
 8004c6c:	2208      	movs	r2, #8
 8004c6e:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 8004c72:	68fb      	ldr	r3, [r7, #12]
 8004c74:	2200      	movs	r2, #0
 8004c76:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

          return HAL_ERROR;
 8004c7a:	2301      	movs	r3, #1
 8004c7c:	e029      	b.n	8004cd2 <UART_WaitOnFlagUntilTimeout+0xd2>
        }
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 8004c7e:	68fb      	ldr	r3, [r7, #12]
 8004c80:	681b      	ldr	r3, [r3, #0]
 8004c82:	69db      	ldr	r3, [r3, #28]
 8004c84:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 8004c88:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8004c8c:	d111      	bne.n	8004cb2 <UART_WaitOnFlagUntilTimeout+0xb2>
        {
          /* Clear Receiver Timeout flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 8004c8e:	68fb      	ldr	r3, [r7, #12]
 8004c90:	681b      	ldr	r3, [r3, #0]
 8004c92:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8004c96:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 8004c98:	68f8      	ldr	r0, [r7, #12]
 8004c9a:	f000 f81e 	bl	8004cda <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_RTO;
 8004c9e:	68fb      	ldr	r3, [r7, #12]
 8004ca0:	2220      	movs	r2, #32
 8004ca2:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 8004ca6:	68fb      	ldr	r3, [r7, #12]
 8004ca8:	2200      	movs	r2, #0
 8004caa:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

          return HAL_TIMEOUT;
 8004cae:	2303      	movs	r3, #3
 8004cb0:	e00f      	b.n	8004cd2 <UART_WaitOnFlagUntilTimeout+0xd2>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8004cb2:	68fb      	ldr	r3, [r7, #12]
 8004cb4:	681b      	ldr	r3, [r3, #0]
 8004cb6:	69da      	ldr	r2, [r3, #28]
 8004cb8:	68bb      	ldr	r3, [r7, #8]
 8004cba:	4013      	ands	r3, r2
 8004cbc:	68ba      	ldr	r2, [r7, #8]
 8004cbe:	429a      	cmp	r2, r3
 8004cc0:	bf0c      	ite	eq
 8004cc2:	2301      	moveq	r3, #1
 8004cc4:	2300      	movne	r3, #0
 8004cc6:	b2db      	uxtb	r3, r3
 8004cc8:	461a      	mov	r2, r3
 8004cca:	79fb      	ldrb	r3, [r7, #7]
 8004ccc:	429a      	cmp	r2, r3
 8004cce:	d0a0      	beq.n	8004c12 <UART_WaitOnFlagUntilTimeout+0x12>
        }
      }
    }
  }
  return HAL_OK;
 8004cd0:	2300      	movs	r3, #0
}
 8004cd2:	4618      	mov	r0, r3
 8004cd4:	3710      	adds	r7, #16
 8004cd6:	46bd      	mov	sp, r7
 8004cd8:	bd80      	pop	{r7, pc}

08004cda <UART_EndRxTransfer>:
  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
  * @param  huart UART handle.
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
 8004cda:	b480      	push	{r7}
 8004cdc:	b095      	sub	sp, #84	@ 0x54
 8004cde:	af00      	add	r7, sp, #0
 8004ce0:	6078      	str	r0, [r7, #4]
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8004ce2:	687b      	ldr	r3, [r7, #4]
 8004ce4:	681b      	ldr	r3, [r3, #0]
 8004ce6:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004ce8:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8004cea:	e853 3f00 	ldrex	r3, [r3]
 8004cee:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 8004cf0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8004cf2:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8004cf6:	64fb      	str	r3, [r7, #76]	@ 0x4c
 8004cf8:	687b      	ldr	r3, [r7, #4]
 8004cfa:	681b      	ldr	r3, [r3, #0]
 8004cfc:	461a      	mov	r2, r3
 8004cfe:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8004d00:	643b      	str	r3, [r7, #64]	@ 0x40
 8004d02:	63fa      	str	r2, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004d04:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 8004d06:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 8004d08:	e841 2300 	strex	r3, r2, [r1]
 8004d0c:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 8004d0e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8004d10:	2b00      	cmp	r3, #0
 8004d12:	d1e6      	bne.n	8004ce2 <UART_EndRxTransfer+0x8>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8004d14:	687b      	ldr	r3, [r7, #4]
 8004d16:	681b      	ldr	r3, [r3, #0]
 8004d18:	3308      	adds	r3, #8
 8004d1a:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004d1c:	6a3b      	ldr	r3, [r7, #32]
 8004d1e:	e853 3f00 	ldrex	r3, [r3]
 8004d22:	61fb      	str	r3, [r7, #28]
   return(result);
 8004d24:	69fb      	ldr	r3, [r7, #28]
 8004d26:	f023 0301 	bic.w	r3, r3, #1
 8004d2a:	64bb      	str	r3, [r7, #72]	@ 0x48
 8004d2c:	687b      	ldr	r3, [r7, #4]
 8004d2e:	681b      	ldr	r3, [r3, #0]
 8004d30:	3308      	adds	r3, #8
 8004d32:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 8004d34:	62fa      	str	r2, [r7, #44]	@ 0x2c
 8004d36:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004d38:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8004d3a:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8004d3c:	e841 2300 	strex	r3, r2, [r1]
 8004d40:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 8004d42:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8004d44:	2b00      	cmp	r3, #0
 8004d46:	d1e5      	bne.n	8004d14 <UART_EndRxTransfer+0x3a>
#endif /* USART_CR1_FIFOEN */

  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8004d48:	687b      	ldr	r3, [r7, #4]
 8004d4a:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8004d4c:	2b01      	cmp	r3, #1
 8004d4e:	d118      	bne.n	8004d82 <UART_EndRxTransfer+0xa8>
  {
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8004d50:	687b      	ldr	r3, [r7, #4]
 8004d52:	681b      	ldr	r3, [r3, #0]
 8004d54:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004d56:	68fb      	ldr	r3, [r7, #12]
 8004d58:	e853 3f00 	ldrex	r3, [r3]
 8004d5c:	60bb      	str	r3, [r7, #8]
   return(result);
 8004d5e:	68bb      	ldr	r3, [r7, #8]
 8004d60:	f023 0310 	bic.w	r3, r3, #16
 8004d64:	647b      	str	r3, [r7, #68]	@ 0x44
 8004d66:	687b      	ldr	r3, [r7, #4]
 8004d68:	681b      	ldr	r3, [r3, #0]
 8004d6a:	461a      	mov	r2, r3
 8004d6c:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8004d6e:	61bb      	str	r3, [r7, #24]
 8004d70:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004d72:	6979      	ldr	r1, [r7, #20]
 8004d74:	69ba      	ldr	r2, [r7, #24]
 8004d76:	e841 2300 	strex	r3, r2, [r1]
 8004d7a:	613b      	str	r3, [r7, #16]
   return(result);
 8004d7c:	693b      	ldr	r3, [r7, #16]
 8004d7e:	2b00      	cmp	r3, #0
 8004d80:	d1e6      	bne.n	8004d50 <UART_EndRxTransfer+0x76>
  }

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 8004d82:	687b      	ldr	r3, [r7, #4]
 8004d84:	2220      	movs	r2, #32
 8004d86:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8004d8a:	687b      	ldr	r3, [r7, #4]
 8004d8c:	2200      	movs	r2, #0
 8004d8e:	661a      	str	r2, [r3, #96]	@ 0x60

  /* Reset RxIsr function pointer */
  huart->RxISR = NULL;
 8004d90:	687b      	ldr	r3, [r7, #4]
 8004d92:	2200      	movs	r2, #0
 8004d94:	669a      	str	r2, [r3, #104]	@ 0x68
}
 8004d96:	bf00      	nop
 8004d98:	3754      	adds	r7, #84	@ 0x54
 8004d9a:	46bd      	mov	sp, r7
 8004d9c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004da0:	4770      	bx	lr

08004da2 <USB_CoreInit>:
  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains
  *         the configuration information for the specified USBx peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
 8004da2:	b084      	sub	sp, #16
 8004da4:	b580      	push	{r7, lr}
 8004da6:	b084      	sub	sp, #16
 8004da8:	af00      	add	r7, sp, #0
 8004daa:	6078      	str	r0, [r7, #4]
 8004dac:	f107 001c 	add.w	r0, r7, #28
 8004db0:	e880 000e 	stmia.w	r0, {r1, r2, r3}
  HAL_StatusTypeDef ret;

  /* Select FS Embedded PHY */
  USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
 8004db4:	687b      	ldr	r3, [r7, #4]
 8004db6:	68db      	ldr	r3, [r3, #12]
 8004db8:	f043 0240 	orr.w	r2, r3, #64	@ 0x40
 8004dbc:	687b      	ldr	r3, [r7, #4]
 8004dbe:	60da      	str	r2, [r3, #12]

  /* Reset after a PHY select */
  ret = USB_CoreReset(USBx);
 8004dc0:	6878      	ldr	r0, [r7, #4]
 8004dc2:	f000 fa69 	bl	8005298 <USB_CoreReset>
 8004dc6:	4603      	mov	r3, r0
 8004dc8:	73fb      	strb	r3, [r7, #15]

  if (cfg.battery_charging_enable == 0U)
 8004dca:	f897 3025 	ldrb.w	r3, [r7, #37]	@ 0x25
 8004dce:	2b00      	cmp	r3, #0
 8004dd0:	d106      	bne.n	8004de0 <USB_CoreInit+0x3e>
  {
    /* Activate the USB Transceiver */
    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
 8004dd2:	687b      	ldr	r3, [r7, #4]
 8004dd4:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8004dd6:	f443 3280 	orr.w	r2, r3, #65536	@ 0x10000
 8004dda:	687b      	ldr	r3, [r7, #4]
 8004ddc:	639a      	str	r2, [r3, #56]	@ 0x38
 8004dde:	e005      	b.n	8004dec <USB_CoreInit+0x4a>
  }
  else
  {
    /* Deactivate the USB Transceiver */
    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
 8004de0:	687b      	ldr	r3, [r7, #4]
 8004de2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8004de4:	f423 3280 	bic.w	r2, r3, #65536	@ 0x10000
 8004de8:	687b      	ldr	r3, [r7, #4]
 8004dea:	639a      	str	r2, [r3, #56]	@ 0x38
  }

  return ret;
 8004dec:	7bfb      	ldrb	r3, [r7, #15]
}
 8004dee:	4618      	mov	r0, r3
 8004df0:	3710      	adds	r7, #16
 8004df2:	46bd      	mov	sp, r7
 8004df4:	e8bd 4080 	ldmia.w	sp!, {r7, lr}
 8004df8:	b004      	add	sp, #16
 8004dfa:	4770      	bx	lr

08004dfc <USB_DisableGlobalInt>:
  *         Disable the controller's Global Int in the AHB Config reg
  * @param  USBx  Selected device
  * @retval HAL status
  */
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
 8004dfc:	b480      	push	{r7}
 8004dfe:	b083      	sub	sp, #12
 8004e00:	af00      	add	r7, sp, #0
 8004e02:	6078      	str	r0, [r7, #4]
  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
 8004e04:	687b      	ldr	r3, [r7, #4]
 8004e06:	689b      	ldr	r3, [r3, #8]
 8004e08:	f023 0201 	bic.w	r2, r3, #1
 8004e0c:	687b      	ldr	r3, [r7, #4]
 8004e0e:	609a      	str	r2, [r3, #8]
  return HAL_OK;
 8004e10:	2300      	movs	r3, #0
}
 8004e12:	4618      	mov	r0, r3
 8004e14:	370c      	adds	r7, #12
 8004e16:	46bd      	mov	sp, r7
 8004e18:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004e1c:	4770      	bx	lr

08004e1e <USB_SetCurrentMode>:
  *            @arg USB_DEVICE_MODE Peripheral mode
  *            @arg USB_HOST_MODE Host mode
  * @retval HAL status
  */
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
{
 8004e1e:	b580      	push	{r7, lr}
 8004e20:	b084      	sub	sp, #16
 8004e22:	af00      	add	r7, sp, #0
 8004e24:	6078      	str	r0, [r7, #4]
 8004e26:	460b      	mov	r3, r1
 8004e28:	70fb      	strb	r3, [r7, #3]
  uint32_t ms = 0U;
 8004e2a:	2300      	movs	r3, #0
 8004e2c:	60fb      	str	r3, [r7, #12]

  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
 8004e2e:	687b      	ldr	r3, [r7, #4]
 8004e30:	68db      	ldr	r3, [r3, #12]
 8004e32:	f023 42c0 	bic.w	r2, r3, #1610612736	@ 0x60000000
 8004e36:	687b      	ldr	r3, [r7, #4]
 8004e38:	60da      	str	r2, [r3, #12]

  if (mode == USB_HOST_MODE)
 8004e3a:	78fb      	ldrb	r3, [r7, #3]
 8004e3c:	2b01      	cmp	r3, #1
 8004e3e:	d115      	bne.n	8004e6c <USB_SetCurrentMode+0x4e>
  {
    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
 8004e40:	687b      	ldr	r3, [r7, #4]
 8004e42:	68db      	ldr	r3, [r3, #12]
 8004e44:	f043 5200 	orr.w	r2, r3, #536870912	@ 0x20000000
 8004e48:	687b      	ldr	r3, [r7, #4]
 8004e4a:	60da      	str	r2, [r3, #12]

    do
    {
      HAL_Delay(10U);
 8004e4c:	200a      	movs	r0, #10
 8004e4e:	f7fc fc6d 	bl	800172c <HAL_Delay>
      ms += 10U;
 8004e52:	68fb      	ldr	r3, [r7, #12]
 8004e54:	330a      	adds	r3, #10
 8004e56:	60fb      	str	r3, [r7, #12]
    } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
 8004e58:	6878      	ldr	r0, [r7, #4]
 8004e5a:	f000 fa0f 	bl	800527c <USB_GetMode>
 8004e5e:	4603      	mov	r3, r0
 8004e60:	2b01      	cmp	r3, #1
 8004e62:	d01e      	beq.n	8004ea2 <USB_SetCurrentMode+0x84>
 8004e64:	68fb      	ldr	r3, [r7, #12]
 8004e66:	2bc7      	cmp	r3, #199	@ 0xc7
 8004e68:	d9f0      	bls.n	8004e4c <USB_SetCurrentMode+0x2e>
 8004e6a:	e01a      	b.n	8004ea2 <USB_SetCurrentMode+0x84>
  }
  else if (mode == USB_DEVICE_MODE)
 8004e6c:	78fb      	ldrb	r3, [r7, #3]
 8004e6e:	2b00      	cmp	r3, #0
 8004e70:	d115      	bne.n	8004e9e <USB_SetCurrentMode+0x80>
  {
    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
 8004e72:	687b      	ldr	r3, [r7, #4]
 8004e74:	68db      	ldr	r3, [r3, #12]
 8004e76:	f043 4280 	orr.w	r2, r3, #1073741824	@ 0x40000000
 8004e7a:	687b      	ldr	r3, [r7, #4]
 8004e7c:	60da      	str	r2, [r3, #12]

    do
    {
      HAL_Delay(10U);
 8004e7e:	200a      	movs	r0, #10
 8004e80:	f7fc fc54 	bl	800172c <HAL_Delay>
      ms += 10U;
 8004e84:	68fb      	ldr	r3, [r7, #12]
 8004e86:	330a      	adds	r3, #10
 8004e88:	60fb      	str	r3, [r7, #12]
    } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
 8004e8a:	6878      	ldr	r0, [r7, #4]
 8004e8c:	f000 f9f6 	bl	800527c <USB_GetMode>
 8004e90:	4603      	mov	r3, r0
 8004e92:	2b00      	cmp	r3, #0
 8004e94:	d005      	beq.n	8004ea2 <USB_SetCurrentMode+0x84>
 8004e96:	68fb      	ldr	r3, [r7, #12]
 8004e98:	2bc7      	cmp	r3, #199	@ 0xc7
 8004e9a:	d9f0      	bls.n	8004e7e <USB_SetCurrentMode+0x60>
 8004e9c:	e001      	b.n	8004ea2 <USB_SetCurrentMode+0x84>
  }
  else
  {
    return HAL_ERROR;
 8004e9e:	2301      	movs	r3, #1
 8004ea0:	e005      	b.n	8004eae <USB_SetCurrentMode+0x90>
  }

  if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
 8004ea2:	68fb      	ldr	r3, [r7, #12]
 8004ea4:	2bc8      	cmp	r3, #200	@ 0xc8
 8004ea6:	d101      	bne.n	8004eac <USB_SetCurrentMode+0x8e>
  {
    return HAL_ERROR;
 8004ea8:	2301      	movs	r3, #1
 8004eaa:	e000      	b.n	8004eae <USB_SetCurrentMode+0x90>
  }

  return HAL_OK;
 8004eac:	2300      	movs	r3, #0
}
 8004eae:	4618      	mov	r0, r3
 8004eb0:	3710      	adds	r7, #16
 8004eb2:	46bd      	mov	sp, r7
 8004eb4:	bd80      	pop	{r7, pc}
	...

08004eb8 <USB_DevInit>:
  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
  *         the configuration information for the specified USBx peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
 8004eb8:	b084      	sub	sp, #16
 8004eba:	b580      	push	{r7, lr}
 8004ebc:	b086      	sub	sp, #24
 8004ebe:	af00      	add	r7, sp, #0
 8004ec0:	6078      	str	r0, [r7, #4]
 8004ec2:	f107 0024 	add.w	r0, r7, #36	@ 0x24
 8004ec6:	e880 000e 	stmia.w	r0, {r1, r2, r3}
  HAL_StatusTypeDef ret = HAL_OK;
 8004eca:	2300      	movs	r3, #0
 8004ecc:	75fb      	strb	r3, [r7, #23]
  uint32_t USBx_BASE = (uint32_t)USBx;
 8004ece:	687b      	ldr	r3, [r7, #4]
 8004ed0:	60fb      	str	r3, [r7, #12]
  uint32_t i;

  for (i = 0U; i < 15U; i++)
 8004ed2:	2300      	movs	r3, #0
 8004ed4:	613b      	str	r3, [r7, #16]
 8004ed6:	e009      	b.n	8004eec <USB_DevInit+0x34>
  {
    USBx->DIEPTXF[i] = 0U;
 8004ed8:	687a      	ldr	r2, [r7, #4]
 8004eda:	693b      	ldr	r3, [r7, #16]
 8004edc:	3340      	adds	r3, #64	@ 0x40
 8004ede:	009b      	lsls	r3, r3, #2
 8004ee0:	4413      	add	r3, r2
 8004ee2:	2200      	movs	r2, #0
 8004ee4:	605a      	str	r2, [r3, #4]
  for (i = 0U; i < 15U; i++)
 8004ee6:	693b      	ldr	r3, [r7, #16]
 8004ee8:	3301      	adds	r3, #1
 8004eea:	613b      	str	r3, [r7, #16]
 8004eec:	693b      	ldr	r3, [r7, #16]
 8004eee:	2b0e      	cmp	r3, #14
 8004ef0:	d9f2      	bls.n	8004ed8 <USB_DevInit+0x20>
  }

  /* VBUS Sensing setup */
  if (cfg.vbus_sensing_enable == 0U)
 8004ef2:	f897 302e 	ldrb.w	r3, [r7, #46]	@ 0x2e
 8004ef6:	2b00      	cmp	r3, #0
 8004ef8:	d11c      	bne.n	8004f34 <USB_DevInit+0x7c>
  {
    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
 8004efa:	68fb      	ldr	r3, [r7, #12]
 8004efc:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8004f00:	685b      	ldr	r3, [r3, #4]
 8004f02:	68fa      	ldr	r2, [r7, #12]
 8004f04:	f502 6200 	add.w	r2, r2, #2048	@ 0x800
 8004f08:	f043 0302 	orr.w	r3, r3, #2
 8004f0c:	6053      	str	r3, [r2, #4]

    /* Deactivate VBUS Sensing B */
    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 8004f0e:	687b      	ldr	r3, [r7, #4]
 8004f10:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8004f12:	f423 1200 	bic.w	r2, r3, #2097152	@ 0x200000
 8004f16:	687b      	ldr	r3, [r7, #4]
 8004f18:	639a      	str	r2, [r3, #56]	@ 0x38

    /* B-peripheral session valid override enable */
    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
 8004f1a:	687b      	ldr	r3, [r7, #4]
 8004f1c:	681b      	ldr	r3, [r3, #0]
 8004f1e:	f043 0240 	orr.w	r2, r3, #64	@ 0x40
 8004f22:	687b      	ldr	r3, [r7, #4]
 8004f24:	601a      	str	r2, [r3, #0]
    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 8004f26:	687b      	ldr	r3, [r7, #4]
 8004f28:	681b      	ldr	r3, [r3, #0]
 8004f2a:	f043 0280 	orr.w	r2, r3, #128	@ 0x80
 8004f2e:	687b      	ldr	r3, [r7, #4]
 8004f30:	601a      	str	r2, [r3, #0]
 8004f32:	e005      	b.n	8004f40 <USB_DevInit+0x88>
  }
  else
  {
    /* Enable HW VBUS sensing */
    USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
 8004f34:	687b      	ldr	r3, [r7, #4]
 8004f36:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8004f38:	f443 1200 	orr.w	r2, r3, #2097152	@ 0x200000
 8004f3c:	687b      	ldr	r3, [r7, #4]
 8004f3e:	639a      	str	r2, [r3, #56]	@ 0x38
  }

  /* Restart the Phy Clock */
  USBx_PCGCCTL = 0U;
 8004f40:	68fb      	ldr	r3, [r7, #12]
 8004f42:	f503 6360 	add.w	r3, r3, #3584	@ 0xe00
 8004f46:	461a      	mov	r2, r3
 8004f48:	2300      	movs	r3, #0
 8004f4a:	6013      	str	r3, [r2, #0]

  /* Set Core speed to Full speed mode */
  (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
 8004f4c:	2103      	movs	r1, #3
 8004f4e:	6878      	ldr	r0, [r7, #4]
 8004f50:	f000 f95a 	bl	8005208 <USB_SetDevSpeed>

  /* Flush the FIFOs */
  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
 8004f54:	2110      	movs	r1, #16
 8004f56:	6878      	ldr	r0, [r7, #4]
 8004f58:	f000 f8f6 	bl	8005148 <USB_FlushTxFifo>
 8004f5c:	4603      	mov	r3, r0
 8004f5e:	2b00      	cmp	r3, #0
 8004f60:	d001      	beq.n	8004f66 <USB_DevInit+0xae>
  {
    ret = HAL_ERROR;
 8004f62:	2301      	movs	r3, #1
 8004f64:	75fb      	strb	r3, [r7, #23]
  }

  if (USB_FlushRxFifo(USBx) != HAL_OK)
 8004f66:	6878      	ldr	r0, [r7, #4]
 8004f68:	f000 f920 	bl	80051ac <USB_FlushRxFifo>
 8004f6c:	4603      	mov	r3, r0
 8004f6e:	2b00      	cmp	r3, #0
 8004f70:	d001      	beq.n	8004f76 <USB_DevInit+0xbe>
  {
    ret = HAL_ERROR;
 8004f72:	2301      	movs	r3, #1
 8004f74:	75fb      	strb	r3, [r7, #23]
  }

  /* Clear all pending Device Interrupts */
  USBx_DEVICE->DIEPMSK = 0U;
 8004f76:	68fb      	ldr	r3, [r7, #12]
 8004f78:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8004f7c:	461a      	mov	r2, r3
 8004f7e:	2300      	movs	r3, #0
 8004f80:	6113      	str	r3, [r2, #16]
  USBx_DEVICE->DOEPMSK = 0U;
 8004f82:	68fb      	ldr	r3, [r7, #12]
 8004f84:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8004f88:	461a      	mov	r2, r3
 8004f8a:	2300      	movs	r3, #0
 8004f8c:	6153      	str	r3, [r2, #20]
  USBx_DEVICE->DAINTMSK = 0U;
 8004f8e:	68fb      	ldr	r3, [r7, #12]
 8004f90:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8004f94:	461a      	mov	r2, r3
 8004f96:	2300      	movs	r3, #0
 8004f98:	61d3      	str	r3, [r2, #28]

  for (i = 0U; i < cfg.dev_endpoints; i++)
 8004f9a:	2300      	movs	r3, #0
 8004f9c:	613b      	str	r3, [r7, #16]
 8004f9e:	e043      	b.n	8005028 <USB_DevInit+0x170>
  {
    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
 8004fa0:	693b      	ldr	r3, [r7, #16]
 8004fa2:	015a      	lsls	r2, r3, #5
 8004fa4:	68fb      	ldr	r3, [r7, #12]
 8004fa6:	4413      	add	r3, r2
 8004fa8:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8004fac:	681b      	ldr	r3, [r3, #0]
 8004fae:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8004fb2:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
 8004fb6:	d118      	bne.n	8004fea <USB_DevInit+0x132>
    {
      if (i == 0U)
 8004fb8:	693b      	ldr	r3, [r7, #16]
 8004fba:	2b00      	cmp	r3, #0
 8004fbc:	d10a      	bne.n	8004fd4 <USB_DevInit+0x11c>
      {
        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
 8004fbe:	693b      	ldr	r3, [r7, #16]
 8004fc0:	015a      	lsls	r2, r3, #5
 8004fc2:	68fb      	ldr	r3, [r7, #12]
 8004fc4:	4413      	add	r3, r2
 8004fc6:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8004fca:	461a      	mov	r2, r3
 8004fcc:	f04f 6300 	mov.w	r3, #134217728	@ 0x8000000
 8004fd0:	6013      	str	r3, [r2, #0]
 8004fd2:	e013      	b.n	8004ffc <USB_DevInit+0x144>
      }
      else
      {
        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
 8004fd4:	693b      	ldr	r3, [r7, #16]
 8004fd6:	015a      	lsls	r2, r3, #5
 8004fd8:	68fb      	ldr	r3, [r7, #12]
 8004fda:	4413      	add	r3, r2
 8004fdc:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8004fe0:	461a      	mov	r2, r3
 8004fe2:	f04f 4390 	mov.w	r3, #1207959552	@ 0x48000000
 8004fe6:	6013      	str	r3, [r2, #0]
 8004fe8:	e008      	b.n	8004ffc <USB_DevInit+0x144>
      }
    }
    else
    {
      USBx_INEP(i)->DIEPCTL = 0U;
 8004fea:	693b      	ldr	r3, [r7, #16]
 8004fec:	015a      	lsls	r2, r3, #5
 8004fee:	68fb      	ldr	r3, [r7, #12]
 8004ff0:	4413      	add	r3, r2
 8004ff2:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8004ff6:	461a      	mov	r2, r3
 8004ff8:	2300      	movs	r3, #0
 8004ffa:	6013      	str	r3, [r2, #0]
    }

    USBx_INEP(i)->DIEPTSIZ = 0U;
 8004ffc:	693b      	ldr	r3, [r7, #16]
 8004ffe:	015a      	lsls	r2, r3, #5
 8005000:	68fb      	ldr	r3, [r7, #12]
 8005002:	4413      	add	r3, r2
 8005004:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8005008:	461a      	mov	r2, r3
 800500a:	2300      	movs	r3, #0
 800500c:	6113      	str	r3, [r2, #16]
    USBx_INEP(i)->DIEPINT  = 0xFB7FU;
 800500e:	693b      	ldr	r3, [r7, #16]
 8005010:	015a      	lsls	r2, r3, #5
 8005012:	68fb      	ldr	r3, [r7, #12]
 8005014:	4413      	add	r3, r2
 8005016:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 800501a:	461a      	mov	r2, r3
 800501c:	f64f 337f 	movw	r3, #64383	@ 0xfb7f
 8005020:	6093      	str	r3, [r2, #8]
  for (i = 0U; i < cfg.dev_endpoints; i++)
 8005022:	693b      	ldr	r3, [r7, #16]
 8005024:	3301      	adds	r3, #1
 8005026:	613b      	str	r3, [r7, #16]
 8005028:	f897 3024 	ldrb.w	r3, [r7, #36]	@ 0x24
 800502c:	461a      	mov	r2, r3
 800502e:	693b      	ldr	r3, [r7, #16]
 8005030:	4293      	cmp	r3, r2
 8005032:	d3b5      	bcc.n	8004fa0 <USB_DevInit+0xe8>
  }

  for (i = 0U; i < cfg.dev_endpoints; i++)
 8005034:	2300      	movs	r3, #0
 8005036:	613b      	str	r3, [r7, #16]
 8005038:	e043      	b.n	80050c2 <USB_DevInit+0x20a>
  {
    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
 800503a:	693b      	ldr	r3, [r7, #16]
 800503c:	015a      	lsls	r2, r3, #5
 800503e:	68fb      	ldr	r3, [r7, #12]
 8005040:	4413      	add	r3, r2
 8005042:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005046:	681b      	ldr	r3, [r3, #0]
 8005048:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 800504c:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
 8005050:	d118      	bne.n	8005084 <USB_DevInit+0x1cc>
    {
      if (i == 0U)
 8005052:	693b      	ldr	r3, [r7, #16]
 8005054:	2b00      	cmp	r3, #0
 8005056:	d10a      	bne.n	800506e <USB_DevInit+0x1b6>
      {
        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
 8005058:	693b      	ldr	r3, [r7, #16]
 800505a:	015a      	lsls	r2, r3, #5
 800505c:	68fb      	ldr	r3, [r7, #12]
 800505e:	4413      	add	r3, r2
 8005060:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005064:	461a      	mov	r2, r3
 8005066:	f04f 6300 	mov.w	r3, #134217728	@ 0x8000000
 800506a:	6013      	str	r3, [r2, #0]
 800506c:	e013      	b.n	8005096 <USB_DevInit+0x1de>
      }
      else
      {
        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
 800506e:	693b      	ldr	r3, [r7, #16]
 8005070:	015a      	lsls	r2, r3, #5
 8005072:	68fb      	ldr	r3, [r7, #12]
 8005074:	4413      	add	r3, r2
 8005076:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 800507a:	461a      	mov	r2, r3
 800507c:	f04f 4390 	mov.w	r3, #1207959552	@ 0x48000000
 8005080:	6013      	str	r3, [r2, #0]
 8005082:	e008      	b.n	8005096 <USB_DevInit+0x1de>
      }
    }
    else
    {
      USBx_OUTEP(i)->DOEPCTL = 0U;
 8005084:	693b      	ldr	r3, [r7, #16]
 8005086:	015a      	lsls	r2, r3, #5
 8005088:	68fb      	ldr	r3, [r7, #12]
 800508a:	4413      	add	r3, r2
 800508c:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005090:	461a      	mov	r2, r3
 8005092:	2300      	movs	r3, #0
 8005094:	6013      	str	r3, [r2, #0]
    }

    USBx_OUTEP(i)->DOEPTSIZ = 0U;
 8005096:	693b      	ldr	r3, [r7, #16]
 8005098:	015a      	lsls	r2, r3, #5
 800509a:	68fb      	ldr	r3, [r7, #12]
 800509c:	4413      	add	r3, r2
 800509e:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 80050a2:	461a      	mov	r2, r3
 80050a4:	2300      	movs	r3, #0
 80050a6:	6113      	str	r3, [r2, #16]
    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;
 80050a8:	693b      	ldr	r3, [r7, #16]
 80050aa:	015a      	lsls	r2, r3, #5
 80050ac:	68fb      	ldr	r3, [r7, #12]
 80050ae:	4413      	add	r3, r2
 80050b0:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 80050b4:	461a      	mov	r2, r3
 80050b6:	f64f 337f 	movw	r3, #64383	@ 0xfb7f
 80050ba:	6093      	str	r3, [r2, #8]
  for (i = 0U; i < cfg.dev_endpoints; i++)
 80050bc:	693b      	ldr	r3, [r7, #16]
 80050be:	3301      	adds	r3, #1
 80050c0:	613b      	str	r3, [r7, #16]
 80050c2:	f897 3024 	ldrb.w	r3, [r7, #36]	@ 0x24
 80050c6:	461a      	mov	r2, r3
 80050c8:	693b      	ldr	r3, [r7, #16]
 80050ca:	4293      	cmp	r3, r2
 80050cc:	d3b5      	bcc.n	800503a <USB_DevInit+0x182>
  }

  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
 80050ce:	68fb      	ldr	r3, [r7, #12]
 80050d0:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 80050d4:	691b      	ldr	r3, [r3, #16]
 80050d6:	68fa      	ldr	r2, [r7, #12]
 80050d8:	f502 6200 	add.w	r2, r2, #2048	@ 0x800
 80050dc:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 80050e0:	6113      	str	r3, [r2, #16]

  /* Disable all interrupts. */
  USBx->GINTMSK = 0U;
 80050e2:	687b      	ldr	r3, [r7, #4]
 80050e4:	2200      	movs	r2, #0
 80050e6:	619a      	str	r2, [r3, #24]

  /* Clear any pending interrupts */
  USBx->GINTSTS = 0xBFFFFFFFU;
 80050e8:	687b      	ldr	r3, [r7, #4]
 80050ea:	f06f 4280 	mvn.w	r2, #1073741824	@ 0x40000000
 80050ee:	615a      	str	r2, [r3, #20]

  /* Enable the common interrupts */
  USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
 80050f0:	687b      	ldr	r3, [r7, #4]
 80050f2:	699b      	ldr	r3, [r3, #24]
 80050f4:	f043 0210 	orr.w	r2, r3, #16
 80050f8:	687b      	ldr	r3, [r7, #4]
 80050fa:	619a      	str	r2, [r3, #24]

  /* Enable interrupts matching to the Device mode ONLY */
  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
 80050fc:	687b      	ldr	r3, [r7, #4]
 80050fe:	699a      	ldr	r2, [r3, #24]
 8005100:	4b10      	ldr	r3, [pc, #64]	@ (8005144 <USB_DevInit+0x28c>)
 8005102:	4313      	orrs	r3, r2
 8005104:	687a      	ldr	r2, [r7, #4]
 8005106:	6193      	str	r3, [r2, #24]
                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |
                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;

  if (cfg.Sof_enable != 0U)
 8005108:	f897 302a 	ldrb.w	r3, [r7, #42]	@ 0x2a
 800510c:	2b00      	cmp	r3, #0
 800510e:	d005      	beq.n	800511c <USB_DevInit+0x264>
  {
    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
 8005110:	687b      	ldr	r3, [r7, #4]
 8005112:	699b      	ldr	r3, [r3, #24]
 8005114:	f043 0208 	orr.w	r2, r3, #8
 8005118:	687b      	ldr	r3, [r7, #4]
 800511a:	619a      	str	r2, [r3, #24]
  }

  if (cfg.vbus_sensing_enable == 1U)
 800511c:	f897 302e 	ldrb.w	r3, [r7, #46]	@ 0x2e
 8005120:	2b01      	cmp	r3, #1
 8005122:	d107      	bne.n	8005134 <USB_DevInit+0x27c>
  {
    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
 8005124:	687b      	ldr	r3, [r7, #4]
 8005126:	699b      	ldr	r3, [r3, #24]
 8005128:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
 800512c:	f043 0304 	orr.w	r3, r3, #4
 8005130:	687a      	ldr	r2, [r7, #4]
 8005132:	6193      	str	r3, [r2, #24]
  }

  return ret;
 8005134:	7dfb      	ldrb	r3, [r7, #23]
}
 8005136:	4618      	mov	r0, r3
 8005138:	3718      	adds	r7, #24
 800513a:	46bd      	mov	sp, r7
 800513c:	e8bd 4080 	ldmia.w	sp!, {r7, lr}
 8005140:	b004      	add	sp, #16
 8005142:	4770      	bx	lr
 8005144:	803c3800 	.word	0x803c3800

08005148 <USB_FlushTxFifo>:
  *         This parameter can be a value from 1 to 15
            15 means Flush all Tx FIFOs
  * @retval HAL status
  */
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
 8005148:	b480      	push	{r7}
 800514a:	b085      	sub	sp, #20
 800514c:	af00      	add	r7, sp, #0
 800514e:	6078      	str	r0, [r7, #4]
 8005150:	6039      	str	r1, [r7, #0]
  __IO uint32_t count = 0U;
 8005152:	2300      	movs	r3, #0
 8005154:	60fb      	str	r3, [r7, #12]

  /* Wait for AHB master IDLE state. */
  do
  {
    count++;
 8005156:	68fb      	ldr	r3, [r7, #12]
 8005158:	3301      	adds	r3, #1
 800515a:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 800515c:	68fb      	ldr	r3, [r7, #12]
 800515e:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 8005162:	d901      	bls.n	8005168 <USB_FlushTxFifo+0x20>
    {
      return HAL_TIMEOUT;
 8005164:	2303      	movs	r3, #3
 8005166:	e01b      	b.n	80051a0 <USB_FlushTxFifo+0x58>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
 8005168:	687b      	ldr	r3, [r7, #4]
 800516a:	691b      	ldr	r3, [r3, #16]
 800516c:	2b00      	cmp	r3, #0
 800516e:	daf2      	bge.n	8005156 <USB_FlushTxFifo+0xe>

  /* Flush TX Fifo */
  count = 0U;
 8005170:	2300      	movs	r3, #0
 8005172:	60fb      	str	r3, [r7, #12]
  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
 8005174:	683b      	ldr	r3, [r7, #0]
 8005176:	019b      	lsls	r3, r3, #6
 8005178:	f043 0220 	orr.w	r2, r3, #32
 800517c:	687b      	ldr	r3, [r7, #4]
 800517e:	611a      	str	r2, [r3, #16]

  do
  {
    count++;
 8005180:	68fb      	ldr	r3, [r7, #12]
 8005182:	3301      	adds	r3, #1
 8005184:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 8005186:	68fb      	ldr	r3, [r7, #12]
 8005188:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 800518c:	d901      	bls.n	8005192 <USB_FlushTxFifo+0x4a>
    {
      return HAL_TIMEOUT;
 800518e:	2303      	movs	r3, #3
 8005190:	e006      	b.n	80051a0 <USB_FlushTxFifo+0x58>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
 8005192:	687b      	ldr	r3, [r7, #4]
 8005194:	691b      	ldr	r3, [r3, #16]
 8005196:	f003 0320 	and.w	r3, r3, #32
 800519a:	2b20      	cmp	r3, #32
 800519c:	d0f0      	beq.n	8005180 <USB_FlushTxFifo+0x38>

  return HAL_OK;
 800519e:	2300      	movs	r3, #0
}
 80051a0:	4618      	mov	r0, r3
 80051a2:	3714      	adds	r7, #20
 80051a4:	46bd      	mov	sp, r7
 80051a6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80051aa:	4770      	bx	lr

080051ac <USB_FlushRxFifo>:
  * @brief  USB_FlushRxFifo  Flush Rx FIFO
  * @param  USBx  Selected device
  * @retval HAL status
  */
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
 80051ac:	b480      	push	{r7}
 80051ae:	b085      	sub	sp, #20
 80051b0:	af00      	add	r7, sp, #0
 80051b2:	6078      	str	r0, [r7, #4]
  __IO uint32_t count = 0U;
 80051b4:	2300      	movs	r3, #0
 80051b6:	60fb      	str	r3, [r7, #12]

  /* Wait for AHB master IDLE state. */
  do
  {
    count++;
 80051b8:	68fb      	ldr	r3, [r7, #12]
 80051ba:	3301      	adds	r3, #1
 80051bc:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 80051be:	68fb      	ldr	r3, [r7, #12]
 80051c0:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 80051c4:	d901      	bls.n	80051ca <USB_FlushRxFifo+0x1e>
    {
      return HAL_TIMEOUT;
 80051c6:	2303      	movs	r3, #3
 80051c8:	e018      	b.n	80051fc <USB_FlushRxFifo+0x50>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
 80051ca:	687b      	ldr	r3, [r7, #4]
 80051cc:	691b      	ldr	r3, [r3, #16]
 80051ce:	2b00      	cmp	r3, #0
 80051d0:	daf2      	bge.n	80051b8 <USB_FlushRxFifo+0xc>

  /* Flush RX Fifo */
  count = 0U;
 80051d2:	2300      	movs	r3, #0
 80051d4:	60fb      	str	r3, [r7, #12]
  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
 80051d6:	687b      	ldr	r3, [r7, #4]
 80051d8:	2210      	movs	r2, #16
 80051da:	611a      	str	r2, [r3, #16]

  do
  {
    count++;
 80051dc:	68fb      	ldr	r3, [r7, #12]
 80051de:	3301      	adds	r3, #1
 80051e0:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 80051e2:	68fb      	ldr	r3, [r7, #12]
 80051e4:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 80051e8:	d901      	bls.n	80051ee <USB_FlushRxFifo+0x42>
    {
      return HAL_TIMEOUT;
 80051ea:	2303      	movs	r3, #3
 80051ec:	e006      	b.n	80051fc <USB_FlushRxFifo+0x50>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
 80051ee:	687b      	ldr	r3, [r7, #4]
 80051f0:	691b      	ldr	r3, [r3, #16]
 80051f2:	f003 0310 	and.w	r3, r3, #16
 80051f6:	2b10      	cmp	r3, #16
 80051f8:	d0f0      	beq.n	80051dc <USB_FlushRxFifo+0x30>

  return HAL_OK;
 80051fa:	2300      	movs	r3, #0
}
 80051fc:	4618      	mov	r0, r3
 80051fe:	3714      	adds	r7, #20
 8005200:	46bd      	mov	sp, r7
 8005202:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005206:	4770      	bx	lr

08005208 <USB_SetDevSpeed>:
  *          This parameter can be one of these values:
  *            @arg USB_OTG_SPEED_FULL: Full speed mode
  * @retval  Hal status
  */
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
 8005208:	b480      	push	{r7}
 800520a:	b085      	sub	sp, #20
 800520c:	af00      	add	r7, sp, #0
 800520e:	6078      	str	r0, [r7, #4]
 8005210:	460b      	mov	r3, r1
 8005212:	70fb      	strb	r3, [r7, #3]
  uint32_t USBx_BASE = (uint32_t)USBx;
 8005214:	687b      	ldr	r3, [r7, #4]
 8005216:	60fb      	str	r3, [r7, #12]

  USBx_DEVICE->DCFG |= speed;
 8005218:	68fb      	ldr	r3, [r7, #12]
 800521a:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 800521e:	681a      	ldr	r2, [r3, #0]
 8005220:	78fb      	ldrb	r3, [r7, #3]
 8005222:	68f9      	ldr	r1, [r7, #12]
 8005224:	f501 6100 	add.w	r1, r1, #2048	@ 0x800
 8005228:	4313      	orrs	r3, r2
 800522a:	600b      	str	r3, [r1, #0]
  return HAL_OK;
 800522c:	2300      	movs	r3, #0
}
 800522e:	4618      	mov	r0, r3
 8005230:	3714      	adds	r7, #20
 8005232:	46bd      	mov	sp, r7
 8005234:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005238:	4770      	bx	lr

0800523a <USB_DevDisconnect>:
  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling Rpu
  * @param  USBx  Selected device
  * @retval HAL status
  */
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
 800523a:	b480      	push	{r7}
 800523c:	b085      	sub	sp, #20
 800523e:	af00      	add	r7, sp, #0
 8005240:	6078      	str	r0, [r7, #4]
  uint32_t USBx_BASE = (uint32_t)USBx;
 8005242:	687b      	ldr	r3, [r7, #4]
 8005244:	60fb      	str	r3, [r7, #12]

  /* In case phy is stopped, ensure to ungate and restore the phy CLK */
  USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
 8005246:	68fb      	ldr	r3, [r7, #12]
 8005248:	f503 6360 	add.w	r3, r3, #3584	@ 0xe00
 800524c:	681b      	ldr	r3, [r3, #0]
 800524e:	68fa      	ldr	r2, [r7, #12]
 8005250:	f502 6260 	add.w	r2, r2, #3584	@ 0xe00
 8005254:	f023 0303 	bic.w	r3, r3, #3
 8005258:	6013      	str	r3, [r2, #0]

  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
 800525a:	68fb      	ldr	r3, [r7, #12]
 800525c:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8005260:	685b      	ldr	r3, [r3, #4]
 8005262:	68fa      	ldr	r2, [r7, #12]
 8005264:	f502 6200 	add.w	r2, r2, #2048	@ 0x800
 8005268:	f043 0302 	orr.w	r3, r3, #2
 800526c:	6053      	str	r3, [r2, #4]

  return HAL_OK;
 800526e:	2300      	movs	r3, #0
}
 8005270:	4618      	mov	r0, r3
 8005272:	3714      	adds	r7, #20
 8005274:	46bd      	mov	sp, r7
 8005276:	f85d 7b04 	ldr.w	r7, [sp], #4
 800527a:	4770      	bx	lr

0800527c <USB_GetMode>:
  *          This parameter can be one of these values:
  *           0 : Host
  *           1 : Device
  */
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
 800527c:	b480      	push	{r7}
 800527e:	b083      	sub	sp, #12
 8005280:	af00      	add	r7, sp, #0
 8005282:	6078      	str	r0, [r7, #4]
  return ((USBx->GINTSTS) & 0x1U);
 8005284:	687b      	ldr	r3, [r7, #4]
 8005286:	695b      	ldr	r3, [r3, #20]
 8005288:	f003 0301 	and.w	r3, r3, #1
}
 800528c:	4618      	mov	r0, r3
 800528e:	370c      	adds	r7, #12
 8005290:	46bd      	mov	sp, r7
 8005292:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005296:	4770      	bx	lr

08005298 <USB_CoreReset>:
  * @brief  Reset the USB Core (needed after USB clock settings change)
  * @param  USBx  Selected device
  * @retval HAL status
  */
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
 8005298:	b480      	push	{r7}
 800529a:	b085      	sub	sp, #20
 800529c:	af00      	add	r7, sp, #0
 800529e:	6078      	str	r0, [r7, #4]
  __IO uint32_t count = 0U;
 80052a0:	2300      	movs	r3, #0
 80052a2:	60fb      	str	r3, [r7, #12]

  /* Wait for AHB master IDLE state. */
  do
  {
    count++;
 80052a4:	68fb      	ldr	r3, [r7, #12]
 80052a6:	3301      	adds	r3, #1
 80052a8:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 80052aa:	68fb      	ldr	r3, [r7, #12]
 80052ac:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 80052b0:	d901      	bls.n	80052b6 <USB_CoreReset+0x1e>
    {
      return HAL_TIMEOUT;
 80052b2:	2303      	movs	r3, #3
 80052b4:	e01b      	b.n	80052ee <USB_CoreReset+0x56>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
 80052b6:	687b      	ldr	r3, [r7, #4]
 80052b8:	691b      	ldr	r3, [r3, #16]
 80052ba:	2b00      	cmp	r3, #0
 80052bc:	daf2      	bge.n	80052a4 <USB_CoreReset+0xc>

  /* Core Soft Reset */
  count = 0U;
 80052be:	2300      	movs	r3, #0
 80052c0:	60fb      	str	r3, [r7, #12]
  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
 80052c2:	687b      	ldr	r3, [r7, #4]
 80052c4:	691b      	ldr	r3, [r3, #16]
 80052c6:	f043 0201 	orr.w	r2, r3, #1
 80052ca:	687b      	ldr	r3, [r7, #4]
 80052cc:	611a      	str	r2, [r3, #16]

  do
  {
    count++;
 80052ce:	68fb      	ldr	r3, [r7, #12]
 80052d0:	3301      	adds	r3, #1
 80052d2:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 80052d4:	68fb      	ldr	r3, [r7, #12]
 80052d6:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 80052da:	d901      	bls.n	80052e0 <USB_CoreReset+0x48>
    {
      return HAL_TIMEOUT;
 80052dc:	2303      	movs	r3, #3
 80052de:	e006      	b.n	80052ee <USB_CoreReset+0x56>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
 80052e0:	687b      	ldr	r3, [r7, #4]
 80052e2:	691b      	ldr	r3, [r3, #16]
 80052e4:	f003 0301 	and.w	r3, r3, #1
 80052e8:	2b01      	cmp	r3, #1
 80052ea:	d0f0      	beq.n	80052ce <USB_CoreReset+0x36>

  return HAL_OK;
 80052ec:	2300      	movs	r3, #0
}
 80052ee:	4618      	mov	r0, r3
 80052f0:	3714      	adds	r7, #20
 80052f2:	46bd      	mov	sp, r7
 80052f4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80052f8:	4770      	bx	lr
	...

080052fc <__NVIC_SetPriority>:
{
 80052fc:	b480      	push	{r7}
 80052fe:	b083      	sub	sp, #12
 8005300:	af00      	add	r7, sp, #0
 8005302:	4603      	mov	r3, r0
 8005304:	6039      	str	r1, [r7, #0]
 8005306:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8005308:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800530c:	2b00      	cmp	r3, #0
 800530e:	db0a      	blt.n	8005326 <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8005310:	683b      	ldr	r3, [r7, #0]
 8005312:	b2da      	uxtb	r2, r3
 8005314:	490c      	ldr	r1, [pc, #48]	@ (8005348 <__NVIC_SetPriority+0x4c>)
 8005316:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800531a:	0112      	lsls	r2, r2, #4
 800531c:	b2d2      	uxtb	r2, r2
 800531e:	440b      	add	r3, r1
 8005320:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
}
 8005324:	e00a      	b.n	800533c <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8005326:	683b      	ldr	r3, [r7, #0]
 8005328:	b2da      	uxtb	r2, r3
 800532a:	4908      	ldr	r1, [pc, #32]	@ (800534c <__NVIC_SetPriority+0x50>)
 800532c:	79fb      	ldrb	r3, [r7, #7]
 800532e:	f003 030f 	and.w	r3, r3, #15
 8005332:	3b04      	subs	r3, #4
 8005334:	0112      	lsls	r2, r2, #4
 8005336:	b2d2      	uxtb	r2, r2
 8005338:	440b      	add	r3, r1
 800533a:	761a      	strb	r2, [r3, #24]
}
 800533c:	bf00      	nop
 800533e:	370c      	adds	r7, #12
 8005340:	46bd      	mov	sp, r7
 8005342:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005346:	4770      	bx	lr
 8005348:	e000e100 	.word	0xe000e100
 800534c:	e000ed00 	.word	0xe000ed00

08005350 <SysTick_Handler>:

/*
  SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
 8005350:	b580      	push	{r7, lr}
 8005352:	af00      	add	r7, sp, #0
  /* Clear overflow flag */
  SysTick->CTRL;
 8005354:	4b05      	ldr	r3, [pc, #20]	@ (800536c <SysTick_Handler+0x1c>)
 8005356:	681b      	ldr	r3, [r3, #0]

  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
 8005358:	f001 fc98 	bl	8006c8c <xTaskGetSchedulerState>
 800535c:	4603      	mov	r3, r0
 800535e:	2b01      	cmp	r3, #1
 8005360:	d001      	beq.n	8005366 <SysTick_Handler+0x16>
    /* Call tick handler */
    xPortSysTickHandler();
 8005362:	f002 fba1 	bl	8007aa8 <xPortSysTickHandler>
  }
}
 8005366:	bf00      	nop
 8005368:	bd80      	pop	{r7, pc}
 800536a:	bf00      	nop
 800536c:	e000e010 	.word	0xe000e010

08005370 <SVC_Setup>:
#endif /* SysTick */

/*
  Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
 8005370:	b580      	push	{r7, lr}
 8005372:	af00      	add	r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
  /* Service Call interrupt might be configured before kernel start     */
  /* and when its priority is lower or equal to BASEPRI, svc intruction */
  /* causes a Hard Fault.                                               */
  NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
 8005374:	2100      	movs	r1, #0
 8005376:	f06f 0004 	mvn.w	r0, #4
 800537a:	f7ff ffbf 	bl	80052fc <__NVIC_SetPriority>
#endif
}
 800537e:	bf00      	nop
 8005380:	bd80      	pop	{r7, pc}
	...

08005384 <osKernelInitialize>:
static uint32_t OS_Tick_GetOverflow (void);
/* Get OS Tick interval */
static uint32_t OS_Tick_GetInterval (void);
/*---------------------------------------------------------------------------*/

osStatus_t osKernelInitialize (void) {
 8005384:	b480      	push	{r7}
 8005386:	b083      	sub	sp, #12
 8005388:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800538a:	f3ef 8305 	mrs	r3, IPSR
 800538e:	603b      	str	r3, [r7, #0]
  return(result);
 8005390:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 8005392:	2b00      	cmp	r3, #0
 8005394:	d003      	beq.n	800539e <osKernelInitialize+0x1a>
    stat = osErrorISR;
 8005396:	f06f 0305 	mvn.w	r3, #5
 800539a:	607b      	str	r3, [r7, #4]
 800539c:	e00c      	b.n	80053b8 <osKernelInitialize+0x34>
  }
  else {
    if (KernelState == osKernelInactive) {
 800539e:	4b0a      	ldr	r3, [pc, #40]	@ (80053c8 <osKernelInitialize+0x44>)
 80053a0:	681b      	ldr	r3, [r3, #0]
 80053a2:	2b00      	cmp	r3, #0
 80053a4:	d105      	bne.n	80053b2 <osKernelInitialize+0x2e>
        EvrFreeRTOSSetup(0U);
      #endif
      #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
        vPortDefineHeapRegions (configHEAP_5_REGIONS);
      #endif
      KernelState = osKernelReady;
 80053a6:	4b08      	ldr	r3, [pc, #32]	@ (80053c8 <osKernelInitialize+0x44>)
 80053a8:	2201      	movs	r2, #1
 80053aa:	601a      	str	r2, [r3, #0]
      stat = osOK;
 80053ac:	2300      	movs	r3, #0
 80053ae:	607b      	str	r3, [r7, #4]
 80053b0:	e002      	b.n	80053b8 <osKernelInitialize+0x34>
    } else {
      stat = osError;
 80053b2:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80053b6:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 80053b8:	687b      	ldr	r3, [r7, #4]
}
 80053ba:	4618      	mov	r0, r3
 80053bc:	370c      	adds	r7, #12
 80053be:	46bd      	mov	sp, r7
 80053c0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80053c4:	4770      	bx	lr
 80053c6:	bf00      	nop
 80053c8:	20000834 	.word	0x20000834

080053cc <osKernelStart>:
  }

  return (state);
}

osStatus_t osKernelStart (void) {
 80053cc:	b580      	push	{r7, lr}
 80053ce:	b082      	sub	sp, #8
 80053d0:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 80053d2:	f3ef 8305 	mrs	r3, IPSR
 80053d6:	603b      	str	r3, [r7, #0]
  return(result);
 80053d8:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 80053da:	2b00      	cmp	r3, #0
 80053dc:	d003      	beq.n	80053e6 <osKernelStart+0x1a>
    stat = osErrorISR;
 80053de:	f06f 0305 	mvn.w	r3, #5
 80053e2:	607b      	str	r3, [r7, #4]
 80053e4:	e010      	b.n	8005408 <osKernelStart+0x3c>
  }
  else {
    if (KernelState == osKernelReady) {
 80053e6:	4b0b      	ldr	r3, [pc, #44]	@ (8005414 <osKernelStart+0x48>)
 80053e8:	681b      	ldr	r3, [r3, #0]
 80053ea:	2b01      	cmp	r3, #1
 80053ec:	d109      	bne.n	8005402 <osKernelStart+0x36>
      /* Ensure SVC priority is at the reset value */
      SVC_Setup();
 80053ee:	f7ff ffbf 	bl	8005370 <SVC_Setup>
      /* Change state to enable IRQ masking check */
      KernelState = osKernelRunning;
 80053f2:	4b08      	ldr	r3, [pc, #32]	@ (8005414 <osKernelStart+0x48>)
 80053f4:	2202      	movs	r2, #2
 80053f6:	601a      	str	r2, [r3, #0]
      /* Start the kernel scheduler */
      vTaskStartScheduler();
 80053f8:	f000 ffe4 	bl	80063c4 <vTaskStartScheduler>
      stat = osOK;
 80053fc:	2300      	movs	r3, #0
 80053fe:	607b      	str	r3, [r7, #4]
 8005400:	e002      	b.n	8005408 <osKernelStart+0x3c>
    } else {
      stat = osError;
 8005402:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8005406:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 8005408:	687b      	ldr	r3, [r7, #4]
}
 800540a:	4618      	mov	r0, r3
 800540c:	3708      	adds	r7, #8
 800540e:	46bd      	mov	sp, r7
 8005410:	bd80      	pop	{r7, pc}
 8005412:	bf00      	nop
 8005414:	20000834 	.word	0x20000834

08005418 <vApplicationGetIdleTaskMemory>:

/*
  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
 8005418:	b480      	push	{r7}
 800541a:	b085      	sub	sp, #20
 800541c:	af00      	add	r7, sp, #0
 800541e:	60f8      	str	r0, [r7, #12]
 8005420:	60b9      	str	r1, [r7, #8]
 8005422:	607a      	str	r2, [r7, #4]
  /* Idle task control block and stack */
  static StaticTask_t Idle_TCB;
  static StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];

  *ppxIdleTaskTCBBuffer   = &Idle_TCB;
 8005424:	68fb      	ldr	r3, [r7, #12]
 8005426:	4a07      	ldr	r2, [pc, #28]	@ (8005444 <vApplicationGetIdleTaskMemory+0x2c>)
 8005428:	601a      	str	r2, [r3, #0]
  *ppxIdleTaskStackBuffer = &Idle_Stack[0];
 800542a:	68bb      	ldr	r3, [r7, #8]
 800542c:	4a06      	ldr	r2, [pc, #24]	@ (8005448 <vApplicationGetIdleTaskMemory+0x30>)
 800542e:	601a      	str	r2, [r3, #0]
  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;
 8005430:	687b      	ldr	r3, [r7, #4]
 8005432:	2280      	movs	r2, #128	@ 0x80
 8005434:	601a      	str	r2, [r3, #0]
}
 8005436:	bf00      	nop
 8005438:	3714      	adds	r7, #20
 800543a:	46bd      	mov	sp, r7
 800543c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005440:	4770      	bx	lr
 8005442:	bf00      	nop
 8005444:	20000838 	.word	0x20000838
 8005448:	200008e0 	.word	0x200008e0

0800544c <vApplicationGetTimerTaskMemory>:

/*
  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
 800544c:	b480      	push	{r7}
 800544e:	b085      	sub	sp, #20
 8005450:	af00      	add	r7, sp, #0
 8005452:	60f8      	str	r0, [r7, #12]
 8005454:	60b9      	str	r1, [r7, #8]
 8005456:	607a      	str	r2, [r7, #4]
  /* Timer task control block and stack */
  static StaticTask_t Timer_TCB;
  static StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];

  *ppxTimerTaskTCBBuffer   = &Timer_TCB;
 8005458:	68fb      	ldr	r3, [r7, #12]
 800545a:	4a07      	ldr	r2, [pc, #28]	@ (8005478 <vApplicationGetTimerTaskMemory+0x2c>)
 800545c:	601a      	str	r2, [r3, #0]
  *ppxTimerTaskStackBuffer = &Timer_Stack[0];
 800545e:	68bb      	ldr	r3, [r7, #8]
 8005460:	4a06      	ldr	r2, [pc, #24]	@ (800547c <vApplicationGetTimerTaskMemory+0x30>)
 8005462:	601a      	str	r2, [r3, #0]
  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;
 8005464:	687b      	ldr	r3, [r7, #4]
 8005466:	f44f 7280 	mov.w	r2, #256	@ 0x100
 800546a:	601a      	str	r2, [r3, #0]
}
 800546c:	bf00      	nop
 800546e:	3714      	adds	r7, #20
 8005470:	46bd      	mov	sp, r7
 8005472:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005476:	4770      	bx	lr
 8005478:	20000ae0 	.word	0x20000ae0
 800547c:	20000b88 	.word	0x20000b88

08005480 <vListInitialise>:
/*-----------------------------------------------------------
 * PUBLIC LIST API documented in list.h
 *----------------------------------------------------------*/

void vListInitialise( List_t * const pxList )
{
 8005480:	b480      	push	{r7}
 8005482:	b083      	sub	sp, #12
 8005484:	af00      	add	r7, sp, #0
 8005486:	6078      	str	r0, [r7, #4]
	/* The list structure contains a list item which is used to mark the
	end of the list.  To initialise the list the list end is inserted
	as the only list entry. */
	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 8005488:	687b      	ldr	r3, [r7, #4]
 800548a:	f103 0208 	add.w	r2, r3, #8
 800548e:	687b      	ldr	r3, [r7, #4]
 8005490:	605a      	str	r2, [r3, #4]

	/* The list end value is the highest possible value in the list to
	ensure it remains at the end of the list. */
	pxList->xListEnd.xItemValue = portMAX_DELAY;
 8005492:	687b      	ldr	r3, [r7, #4]
 8005494:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8005498:	609a      	str	r2, [r3, #8]

	/* The list end next and previous pointers point to itself so we know
	when the list is empty. */
	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 800549a:	687b      	ldr	r3, [r7, #4]
 800549c:	f103 0208 	add.w	r2, r3, #8
 80054a0:	687b      	ldr	r3, [r7, #4]
 80054a2:	60da      	str	r2, [r3, #12]
	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 80054a4:	687b      	ldr	r3, [r7, #4]
 80054a6:	f103 0208 	add.w	r2, r3, #8
 80054aa:	687b      	ldr	r3, [r7, #4]
 80054ac:	611a      	str	r2, [r3, #16]

	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
 80054ae:	687b      	ldr	r3, [r7, #4]
 80054b0:	2200      	movs	r2, #0
 80054b2:	601a      	str	r2, [r3, #0]

	/* Write known values into the list if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
 80054b4:	bf00      	nop
 80054b6:	370c      	adds	r7, #12
 80054b8:	46bd      	mov	sp, r7
 80054ba:	f85d 7b04 	ldr.w	r7, [sp], #4
 80054be:	4770      	bx	lr

080054c0 <vListInitialiseItem>:
/*-----------------------------------------------------------*/

void vListInitialiseItem( ListItem_t * const pxItem )
{
 80054c0:	b480      	push	{r7}
 80054c2:	b083      	sub	sp, #12
 80054c4:	af00      	add	r7, sp, #0
 80054c6:	6078      	str	r0, [r7, #4]
	/* Make sure the list item is not recorded as being on a list. */
	pxItem->pxContainer = NULL;
 80054c8:	687b      	ldr	r3, [r7, #4]
 80054ca:	2200      	movs	r2, #0
 80054cc:	611a      	str	r2, [r3, #16]

	/* Write known values into the list item if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
 80054ce:	bf00      	nop
 80054d0:	370c      	adds	r7, #12
 80054d2:	46bd      	mov	sp, r7
 80054d4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80054d8:	4770      	bx	lr

080054da <vListInsertEnd>:
/*-----------------------------------------------------------*/

void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 80054da:	b480      	push	{r7}
 80054dc:	b085      	sub	sp, #20
 80054de:	af00      	add	r7, sp, #0
 80054e0:	6078      	str	r0, [r7, #4]
 80054e2:	6039      	str	r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
 80054e4:	687b      	ldr	r3, [r7, #4]
 80054e6:	685b      	ldr	r3, [r3, #4]
 80054e8:	60fb      	str	r3, [r7, #12]
	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );

	/* Insert a new list item into pxList, but rather than sort the list,
	makes the new list item the last item to be removed by a call to
	listGET_OWNER_OF_NEXT_ENTRY(). */
	pxNewListItem->pxNext = pxIndex;
 80054ea:	683b      	ldr	r3, [r7, #0]
 80054ec:	68fa      	ldr	r2, [r7, #12]
 80054ee:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
 80054f0:	68fb      	ldr	r3, [r7, #12]
 80054f2:	689a      	ldr	r2, [r3, #8]
 80054f4:	683b      	ldr	r3, [r7, #0]
 80054f6:	609a      	str	r2, [r3, #8]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	pxIndex->pxPrevious->pxNext = pxNewListItem;
 80054f8:	68fb      	ldr	r3, [r7, #12]
 80054fa:	689b      	ldr	r3, [r3, #8]
 80054fc:	683a      	ldr	r2, [r7, #0]
 80054fe:	605a      	str	r2, [r3, #4]
	pxIndex->pxPrevious = pxNewListItem;
 8005500:	68fb      	ldr	r3, [r7, #12]
 8005502:	683a      	ldr	r2, [r7, #0]
 8005504:	609a      	str	r2, [r3, #8]

	/* Remember which list the item is in. */
	pxNewListItem->pxContainer = pxList;
 8005506:	683b      	ldr	r3, [r7, #0]
 8005508:	687a      	ldr	r2, [r7, #4]
 800550a:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 800550c:	687b      	ldr	r3, [r7, #4]
 800550e:	681b      	ldr	r3, [r3, #0]
 8005510:	1c5a      	adds	r2, r3, #1
 8005512:	687b      	ldr	r3, [r7, #4]
 8005514:	601a      	str	r2, [r3, #0]
}
 8005516:	bf00      	nop
 8005518:	3714      	adds	r7, #20
 800551a:	46bd      	mov	sp, r7
 800551c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005520:	4770      	bx	lr

08005522 <vListInsert>:
/*-----------------------------------------------------------*/

void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 8005522:	b480      	push	{r7}
 8005524:	b085      	sub	sp, #20
 8005526:	af00      	add	r7, sp, #0
 8005528:	6078      	str	r0, [r7, #4]
 800552a:	6039      	str	r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 800552c:	683b      	ldr	r3, [r7, #0]
 800552e:	681b      	ldr	r3, [r3, #0]
 8005530:	60bb      	str	r3, [r7, #8]
	new list item should be placed after it.  This ensures that TCBs which are
	stored in ready lists (all of which have the same xItemValue value) get a
	share of the CPU.  However, if the xItemValue is the same as the back marker
	the iteration loop below will not end.  Therefore the value is checked
	first, and the algorithm slightly modified if necessary. */
	if( xValueOfInsertion == portMAX_DELAY )
 8005532:	68bb      	ldr	r3, [r7, #8]
 8005534:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8005538:	d103      	bne.n	8005542 <vListInsert+0x20>
	{
		pxIterator = pxList->xListEnd.pxPrevious;
 800553a:	687b      	ldr	r3, [r7, #4]
 800553c:	691b      	ldr	r3, [r3, #16]
 800553e:	60fb      	str	r3, [r7, #12]
 8005540:	e00c      	b.n	800555c <vListInsert+0x3a>
			4) Using a queue or semaphore before it has been initialised or
			   before the scheduler has been started (are interrupts firing
			   before vTaskStartScheduler() has been called?).
		**********************************************************************/

		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
 8005542:	687b      	ldr	r3, [r7, #4]
 8005544:	3308      	adds	r3, #8
 8005546:	60fb      	str	r3, [r7, #12]
 8005548:	e002      	b.n	8005550 <vListInsert+0x2e>
 800554a:	68fb      	ldr	r3, [r7, #12]
 800554c:	685b      	ldr	r3, [r3, #4]
 800554e:	60fb      	str	r3, [r7, #12]
 8005550:	68fb      	ldr	r3, [r7, #12]
 8005552:	685b      	ldr	r3, [r3, #4]
 8005554:	681b      	ldr	r3, [r3, #0]
 8005556:	68ba      	ldr	r2, [r7, #8]
 8005558:	429a      	cmp	r2, r3
 800555a:	d2f6      	bcs.n	800554a <vListInsert+0x28>
			/* There is nothing to do here, just iterating to the wanted
			insertion position. */
		}
	}

	pxNewListItem->pxNext = pxIterator->pxNext;
 800555c:	68fb      	ldr	r3, [r7, #12]
 800555e:	685a      	ldr	r2, [r3, #4]
 8005560:	683b      	ldr	r3, [r7, #0]
 8005562:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
 8005564:	683b      	ldr	r3, [r7, #0]
 8005566:	685b      	ldr	r3, [r3, #4]
 8005568:	683a      	ldr	r2, [r7, #0]
 800556a:	609a      	str	r2, [r3, #8]
	pxNewListItem->pxPrevious = pxIterator;
 800556c:	683b      	ldr	r3, [r7, #0]
 800556e:	68fa      	ldr	r2, [r7, #12]
 8005570:	609a      	str	r2, [r3, #8]
	pxIterator->pxNext = pxNewListItem;
 8005572:	68fb      	ldr	r3, [r7, #12]
 8005574:	683a      	ldr	r2, [r7, #0]
 8005576:	605a      	str	r2, [r3, #4]

	/* Remember which list the item is in.  This allows fast removal of the
	item later. */
	pxNewListItem->pxContainer = pxList;
 8005578:	683b      	ldr	r3, [r7, #0]
 800557a:	687a      	ldr	r2, [r7, #4]
 800557c:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 800557e:	687b      	ldr	r3, [r7, #4]
 8005580:	681b      	ldr	r3, [r3, #0]
 8005582:	1c5a      	adds	r2, r3, #1
 8005584:	687b      	ldr	r3, [r7, #4]
 8005586:	601a      	str	r2, [r3, #0]
}
 8005588:	bf00      	nop
 800558a:	3714      	adds	r7, #20
 800558c:	46bd      	mov	sp, r7
 800558e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005592:	4770      	bx	lr

08005594 <uxListRemove>:
/*-----------------------------------------------------------*/

UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
 8005594:	b480      	push	{r7}
 8005596:	b085      	sub	sp, #20
 8005598:	af00      	add	r7, sp, #0
 800559a:	6078      	str	r0, [r7, #4]
/* The list item knows which list it is in.  Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
 800559c:	687b      	ldr	r3, [r7, #4]
 800559e:	691b      	ldr	r3, [r3, #16]
 80055a0:	60fb      	str	r3, [r7, #12]

	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
 80055a2:	687b      	ldr	r3, [r7, #4]
 80055a4:	685b      	ldr	r3, [r3, #4]
 80055a6:	687a      	ldr	r2, [r7, #4]
 80055a8:	6892      	ldr	r2, [r2, #8]
 80055aa:	609a      	str	r2, [r3, #8]
	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 80055ac:	687b      	ldr	r3, [r7, #4]
 80055ae:	689b      	ldr	r3, [r3, #8]
 80055b0:	687a      	ldr	r2, [r7, #4]
 80055b2:	6852      	ldr	r2, [r2, #4]
 80055b4:	605a      	str	r2, [r3, #4]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	/* Make sure the index is left pointing to a valid item. */
	if( pxList->pxIndex == pxItemToRemove )
 80055b6:	68fb      	ldr	r3, [r7, #12]
 80055b8:	685b      	ldr	r3, [r3, #4]
 80055ba:	687a      	ldr	r2, [r7, #4]
 80055bc:	429a      	cmp	r2, r3
 80055be:	d103      	bne.n	80055c8 <uxListRemove+0x34>
	{
		pxList->pxIndex = pxItemToRemove->pxPrevious;
 80055c0:	687b      	ldr	r3, [r7, #4]
 80055c2:	689a      	ldr	r2, [r3, #8]
 80055c4:	68fb      	ldr	r3, [r7, #12]
 80055c6:	605a      	str	r2, [r3, #4]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxItemToRemove->pxContainer = NULL;
 80055c8:	687b      	ldr	r3, [r7, #4]
 80055ca:	2200      	movs	r2, #0
 80055cc:	611a      	str	r2, [r3, #16]
	( pxList->uxNumberOfItems )--;
 80055ce:	68fb      	ldr	r3, [r7, #12]
 80055d0:	681b      	ldr	r3, [r3, #0]
 80055d2:	1e5a      	subs	r2, r3, #1
 80055d4:	68fb      	ldr	r3, [r7, #12]
 80055d6:	601a      	str	r2, [r3, #0]

	return pxList->uxNumberOfItems;
 80055d8:	68fb      	ldr	r3, [r7, #12]
 80055da:	681b      	ldr	r3, [r3, #0]
}
 80055dc:	4618      	mov	r0, r3
 80055de:	3714      	adds	r7, #20
 80055e0:	46bd      	mov	sp, r7
 80055e2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80055e6:	4770      	bx	lr

080055e8 <xQueueGenericReset>:
	}														\
	taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
 80055e8:	b580      	push	{r7, lr}
 80055ea:	b084      	sub	sp, #16
 80055ec:	af00      	add	r7, sp, #0
 80055ee:	6078      	str	r0, [r7, #4]
 80055f0:	6039      	str	r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
 80055f2:	687b      	ldr	r3, [r7, #4]
 80055f4:	60fb      	str	r3, [r7, #12]

	configASSERT( pxQueue );
 80055f6:	68fb      	ldr	r3, [r7, #12]
 80055f8:	2b00      	cmp	r3, #0
 80055fa:	d10b      	bne.n	8005614 <xQueueGenericReset+0x2c>

portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;

	__asm volatile
 80055fc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005600:	f383 8811 	msr	BASEPRI, r3
 8005604:	f3bf 8f6f 	isb	sy
 8005608:	f3bf 8f4f 	dsb	sy
 800560c:	60bb      	str	r3, [r7, #8]
		"	msr basepri, %0											\n" \
		"	isb														\n" \
		"	dsb														\n" \
		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);
}
 800560e:	bf00      	nop
 8005610:	bf00      	nop
 8005612:	e7fd      	b.n	8005610 <xQueueGenericReset+0x28>

	taskENTER_CRITICAL();
 8005614:	f002 f9b8 	bl	8007988 <vPortEnterCritical>
	{
		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 8005618:	68fb      	ldr	r3, [r7, #12]
 800561a:	681a      	ldr	r2, [r3, #0]
 800561c:	68fb      	ldr	r3, [r7, #12]
 800561e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8005620:	68f9      	ldr	r1, [r7, #12]
 8005622:	6c09      	ldr	r1, [r1, #64]	@ 0x40
 8005624:	fb01 f303 	mul.w	r3, r1, r3
 8005628:	441a      	add	r2, r3
 800562a:	68fb      	ldr	r3, [r7, #12]
 800562c:	609a      	str	r2, [r3, #8]
		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
 800562e:	68fb      	ldr	r3, [r7, #12]
 8005630:	2200      	movs	r2, #0
 8005632:	639a      	str	r2, [r3, #56]	@ 0x38
		pxQueue->pcWriteTo = pxQueue->pcHead;
 8005634:	68fb      	ldr	r3, [r7, #12]
 8005636:	681a      	ldr	r2, [r3, #0]
 8005638:	68fb      	ldr	r3, [r7, #12]
 800563a:	605a      	str	r2, [r3, #4]
		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 800563c:	68fb      	ldr	r3, [r7, #12]
 800563e:	681a      	ldr	r2, [r3, #0]
 8005640:	68fb      	ldr	r3, [r7, #12]
 8005642:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8005644:	3b01      	subs	r3, #1
 8005646:	68f9      	ldr	r1, [r7, #12]
 8005648:	6c09      	ldr	r1, [r1, #64]	@ 0x40
 800564a:	fb01 f303 	mul.w	r3, r1, r3
 800564e:	441a      	add	r2, r3
 8005650:	68fb      	ldr	r3, [r7, #12]
 8005652:	60da      	str	r2, [r3, #12]
		pxQueue->cRxLock = queueUNLOCKED;
 8005654:	68fb      	ldr	r3, [r7, #12]
 8005656:	22ff      	movs	r2, #255	@ 0xff
 8005658:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
		pxQueue->cTxLock = queueUNLOCKED;
 800565c:	68fb      	ldr	r3, [r7, #12]
 800565e:	22ff      	movs	r2, #255	@ 0xff
 8005660:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45

		if( xNewQueue == pdFALSE )
 8005664:	683b      	ldr	r3, [r7, #0]
 8005666:	2b00      	cmp	r3, #0
 8005668:	d114      	bne.n	8005694 <xQueueGenericReset+0xac>
			/* If there are tasks blocked waiting to read from the queue, then
			the tasks will remain blocked as after this function exits the queue
			will still be empty.  If there are tasks blocked waiting to write to
			the queue, then one should be unblocked as after this function exits
			it will be possible to write to it. */
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 800566a:	68fb      	ldr	r3, [r7, #12]
 800566c:	691b      	ldr	r3, [r3, #16]
 800566e:	2b00      	cmp	r3, #0
 8005670:	d01a      	beq.n	80056a8 <xQueueGenericReset+0xc0>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8005672:	68fb      	ldr	r3, [r7, #12]
 8005674:	3310      	adds	r3, #16
 8005676:	4618      	mov	r0, r3
 8005678:	f001 f942 	bl	8006900 <xTaskRemoveFromEventList>
 800567c:	4603      	mov	r3, r0
 800567e:	2b00      	cmp	r3, #0
 8005680:	d012      	beq.n	80056a8 <xQueueGenericReset+0xc0>
				{
					queueYIELD_IF_USING_PREEMPTION();
 8005682:	4b0d      	ldr	r3, [pc, #52]	@ (80056b8 <xQueueGenericReset+0xd0>)
 8005684:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8005688:	601a      	str	r2, [r3, #0]
 800568a:	f3bf 8f4f 	dsb	sy
 800568e:	f3bf 8f6f 	isb	sy
 8005692:	e009      	b.n	80056a8 <xQueueGenericReset+0xc0>
			}
		}
		else
		{
			/* Ensure the event queues start in the correct state. */
			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
 8005694:	68fb      	ldr	r3, [r7, #12]
 8005696:	3310      	adds	r3, #16
 8005698:	4618      	mov	r0, r3
 800569a:	f7ff fef1 	bl	8005480 <vListInitialise>
			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
 800569e:	68fb      	ldr	r3, [r7, #12]
 80056a0:	3324      	adds	r3, #36	@ 0x24
 80056a2:	4618      	mov	r0, r3
 80056a4:	f7ff feec 	bl	8005480 <vListInitialise>
		}
	}
	taskEXIT_CRITICAL();
 80056a8:	f002 f9a0 	bl	80079ec <vPortExitCritical>

	/* A value is returned for calling semantic consistency with previous
	versions. */
	return pdPASS;
 80056ac:	2301      	movs	r3, #1
}
 80056ae:	4618      	mov	r0, r3
 80056b0:	3710      	adds	r7, #16
 80056b2:	46bd      	mov	sp, r7
 80056b4:	bd80      	pop	{r7, pc}
 80056b6:	bf00      	nop
 80056b8:	e000ed04 	.word	0xe000ed04

080056bc <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_STATIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
	{
 80056bc:	b580      	push	{r7, lr}
 80056be:	b08e      	sub	sp, #56	@ 0x38
 80056c0:	af02      	add	r7, sp, #8
 80056c2:	60f8      	str	r0, [r7, #12]
 80056c4:	60b9      	str	r1, [r7, #8]
 80056c6:	607a      	str	r2, [r7, #4]
 80056c8:	603b      	str	r3, [r7, #0]
	Queue_t *pxNewQueue;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 80056ca:	68fb      	ldr	r3, [r7, #12]
 80056cc:	2b00      	cmp	r3, #0
 80056ce:	d10b      	bne.n	80056e8 <xQueueGenericCreateStatic+0x2c>
	__asm volatile
 80056d0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80056d4:	f383 8811 	msr	BASEPRI, r3
 80056d8:	f3bf 8f6f 	isb	sy
 80056dc:	f3bf 8f4f 	dsb	sy
 80056e0:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 80056e2:	bf00      	nop
 80056e4:	bf00      	nop
 80056e6:	e7fd      	b.n	80056e4 <xQueueGenericCreateStatic+0x28>

		/* The StaticQueue_t structure and the queue storage area must be
		supplied. */
		configASSERT( pxStaticQueue != NULL );
 80056e8:	683b      	ldr	r3, [r7, #0]
 80056ea:	2b00      	cmp	r3, #0
 80056ec:	d10b      	bne.n	8005706 <xQueueGenericCreateStatic+0x4a>
	__asm volatile
 80056ee:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80056f2:	f383 8811 	msr	BASEPRI, r3
 80056f6:	f3bf 8f6f 	isb	sy
 80056fa:	f3bf 8f4f 	dsb	sy
 80056fe:	627b      	str	r3, [r7, #36]	@ 0x24
}
 8005700:	bf00      	nop
 8005702:	bf00      	nop
 8005704:	e7fd      	b.n	8005702 <xQueueGenericCreateStatic+0x46>

		/* A queue storage area should be provided if the item size is not 0, and
		should not be provided if the item size is 0. */
		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
 8005706:	687b      	ldr	r3, [r7, #4]
 8005708:	2b00      	cmp	r3, #0
 800570a:	d002      	beq.n	8005712 <xQueueGenericCreateStatic+0x56>
 800570c:	68bb      	ldr	r3, [r7, #8]
 800570e:	2b00      	cmp	r3, #0
 8005710:	d001      	beq.n	8005716 <xQueueGenericCreateStatic+0x5a>
 8005712:	2301      	movs	r3, #1
 8005714:	e000      	b.n	8005718 <xQueueGenericCreateStatic+0x5c>
 8005716:	2300      	movs	r3, #0
 8005718:	2b00      	cmp	r3, #0
 800571a:	d10b      	bne.n	8005734 <xQueueGenericCreateStatic+0x78>
	__asm volatile
 800571c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005720:	f383 8811 	msr	BASEPRI, r3
 8005724:	f3bf 8f6f 	isb	sy
 8005728:	f3bf 8f4f 	dsb	sy
 800572c:	623b      	str	r3, [r7, #32]
}
 800572e:	bf00      	nop
 8005730:	bf00      	nop
 8005732:	e7fd      	b.n	8005730 <xQueueGenericCreateStatic+0x74>
		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
 8005734:	687b      	ldr	r3, [r7, #4]
 8005736:	2b00      	cmp	r3, #0
 8005738:	d102      	bne.n	8005740 <xQueueGenericCreateStatic+0x84>
 800573a:	68bb      	ldr	r3, [r7, #8]
 800573c:	2b00      	cmp	r3, #0
 800573e:	d101      	bne.n	8005744 <xQueueGenericCreateStatic+0x88>
 8005740:	2301      	movs	r3, #1
 8005742:	e000      	b.n	8005746 <xQueueGenericCreateStatic+0x8a>
 8005744:	2300      	movs	r3, #0
 8005746:	2b00      	cmp	r3, #0
 8005748:	d10b      	bne.n	8005762 <xQueueGenericCreateStatic+0xa6>
	__asm volatile
 800574a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800574e:	f383 8811 	msr	BASEPRI, r3
 8005752:	f3bf 8f6f 	isb	sy
 8005756:	f3bf 8f4f 	dsb	sy
 800575a:	61fb      	str	r3, [r7, #28]
}
 800575c:	bf00      	nop
 800575e:	bf00      	nop
 8005760:	e7fd      	b.n	800575e <xQueueGenericCreateStatic+0xa2>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
			the real queue and semaphore structures. */
			volatile size_t xSize = sizeof( StaticQueue_t );
 8005762:	2350      	movs	r3, #80	@ 0x50
 8005764:	617b      	str	r3, [r7, #20]
			configASSERT( xSize == sizeof( Queue_t ) );
 8005766:	697b      	ldr	r3, [r7, #20]
 8005768:	2b50      	cmp	r3, #80	@ 0x50
 800576a:	d00b      	beq.n	8005784 <xQueueGenericCreateStatic+0xc8>
	__asm volatile
 800576c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005770:	f383 8811 	msr	BASEPRI, r3
 8005774:	f3bf 8f6f 	isb	sy
 8005778:	f3bf 8f4f 	dsb	sy
 800577c:	61bb      	str	r3, [r7, #24]
}
 800577e:	bf00      	nop
 8005780:	bf00      	nop
 8005782:	e7fd      	b.n	8005780 <xQueueGenericCreateStatic+0xc4>
			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 8005784:	697b      	ldr	r3, [r7, #20]
		#endif /* configASSERT_DEFINED */

		/* The address of a statically allocated queue was passed in, use it.
		The address of a statically allocated storage area was also passed in
		but is already set. */
		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 8005786:	683b      	ldr	r3, [r7, #0]
 8005788:	62fb      	str	r3, [r7, #44]	@ 0x2c

		if( pxNewQueue != NULL )
 800578a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800578c:	2b00      	cmp	r3, #0
 800578e:	d00d      	beq.n	80057ac <xQueueGenericCreateStatic+0xf0>
			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
			{
				/* Queues can be allocated wither statically or dynamically, so
				note this queue was allocated statically in case the queue is
				later deleted. */
				pxNewQueue->ucStaticallyAllocated = pdTRUE;
 8005790:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8005792:	2201      	movs	r2, #1
 8005794:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
			}
			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 8005798:	f897 2038 	ldrb.w	r2, [r7, #56]	@ 0x38
 800579c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800579e:	9300      	str	r3, [sp, #0]
 80057a0:	4613      	mov	r3, r2
 80057a2:	687a      	ldr	r2, [r7, #4]
 80057a4:	68b9      	ldr	r1, [r7, #8]
 80057a6:	68f8      	ldr	r0, [r7, #12]
 80057a8:	f000 f805 	bl	80057b6 <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 80057ac:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
	}
 80057ae:	4618      	mov	r0, r3
 80057b0:	3730      	adds	r7, #48	@ 0x30
 80057b2:	46bd      	mov	sp, r7
 80057b4:	bd80      	pop	{r7, pc}

080057b6 <prvInitialiseNewQueue>:

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
 80057b6:	b580      	push	{r7, lr}
 80057b8:	b084      	sub	sp, #16
 80057ba:	af00      	add	r7, sp, #0
 80057bc:	60f8      	str	r0, [r7, #12]
 80057be:	60b9      	str	r1, [r7, #8]
 80057c0:	607a      	str	r2, [r7, #4]
 80057c2:	70fb      	strb	r3, [r7, #3]
	/* Remove compiler warnings about unused parameters should
	configUSE_TRACE_FACILITY not be set to 1. */
	( void ) ucQueueType;

	if( uxItemSize == ( UBaseType_t ) 0 )
 80057c4:	68bb      	ldr	r3, [r7, #8]
 80057c6:	2b00      	cmp	r3, #0
 80057c8:	d103      	bne.n	80057d2 <prvInitialiseNewQueue+0x1c>
	{
		/* No RAM was allocated for the queue storage area, but PC head cannot
		be set to NULL because NULL is used as a key to say the queue is used as
		a mutex.  Therefore just set pcHead to point to the queue as a benign
		value that is known to be within the memory map. */
		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
 80057ca:	69bb      	ldr	r3, [r7, #24]
 80057cc:	69ba      	ldr	r2, [r7, #24]
 80057ce:	601a      	str	r2, [r3, #0]
 80057d0:	e002      	b.n	80057d8 <prvInitialiseNewQueue+0x22>
	}
	else
	{
		/* Set the head to the start of the queue storage area. */
		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
 80057d2:	69bb      	ldr	r3, [r7, #24]
 80057d4:	687a      	ldr	r2, [r7, #4]
 80057d6:	601a      	str	r2, [r3, #0]
	}

	/* Initialise the queue members as described where the queue type is
	defined. */
	pxNewQueue->uxLength = uxQueueLength;
 80057d8:	69bb      	ldr	r3, [r7, #24]
 80057da:	68fa      	ldr	r2, [r7, #12]
 80057dc:	63da      	str	r2, [r3, #60]	@ 0x3c
	pxNewQueue->uxItemSize = uxItemSize;
 80057de:	69bb      	ldr	r3, [r7, #24]
 80057e0:	68ba      	ldr	r2, [r7, #8]
 80057e2:	641a      	str	r2, [r3, #64]	@ 0x40
	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
 80057e4:	2101      	movs	r1, #1
 80057e6:	69b8      	ldr	r0, [r7, #24]
 80057e8:	f7ff fefe 	bl	80055e8 <xQueueGenericReset>

	#if ( configUSE_TRACE_FACILITY == 1 )
	{
		pxNewQueue->ucQueueType = ucQueueType;
 80057ec:	69bb      	ldr	r3, [r7, #24]
 80057ee:	78fa      	ldrb	r2, [r7, #3]
 80057f0:	f883 204c 	strb.w	r2, [r3, #76]	@ 0x4c
		pxNewQueue->pxQueueSetContainer = NULL;
	}
	#endif /* configUSE_QUEUE_SETS */

	traceQUEUE_CREATE( pxNewQueue );
}
 80057f4:	bf00      	nop
 80057f6:	3710      	adds	r7, #16
 80057f8:	46bd      	mov	sp, r7
 80057fa:	bd80      	pop	{r7, pc}

080057fc <xQueueGenericSend>:

#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
 80057fc:	b580      	push	{r7, lr}
 80057fe:	b08e      	sub	sp, #56	@ 0x38
 8005800:	af00      	add	r7, sp, #0
 8005802:	60f8      	str	r0, [r7, #12]
 8005804:	60b9      	str	r1, [r7, #8]
 8005806:	607a      	str	r2, [r7, #4]
 8005808:	603b      	str	r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
 800580a:	2300      	movs	r3, #0
 800580c:	637b      	str	r3, [r7, #52]	@ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 800580e:	68fb      	ldr	r3, [r7, #12]
 8005810:	633b      	str	r3, [r7, #48]	@ 0x30

	configASSERT( pxQueue );
 8005812:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8005814:	2b00      	cmp	r3, #0
 8005816:	d10b      	bne.n	8005830 <xQueueGenericSend+0x34>
	__asm volatile
 8005818:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800581c:	f383 8811 	msr	BASEPRI, r3
 8005820:	f3bf 8f6f 	isb	sy
 8005824:	f3bf 8f4f 	dsb	sy
 8005828:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 800582a:	bf00      	nop
 800582c:	bf00      	nop
 800582e:	e7fd      	b.n	800582c <xQueueGenericSend+0x30>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8005830:	68bb      	ldr	r3, [r7, #8]
 8005832:	2b00      	cmp	r3, #0
 8005834:	d103      	bne.n	800583e <xQueueGenericSend+0x42>
 8005836:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8005838:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800583a:	2b00      	cmp	r3, #0
 800583c:	d101      	bne.n	8005842 <xQueueGenericSend+0x46>
 800583e:	2301      	movs	r3, #1
 8005840:	e000      	b.n	8005844 <xQueueGenericSend+0x48>
 8005842:	2300      	movs	r3, #0
 8005844:	2b00      	cmp	r3, #0
 8005846:	d10b      	bne.n	8005860 <xQueueGenericSend+0x64>
	__asm volatile
 8005848:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800584c:	f383 8811 	msr	BASEPRI, r3
 8005850:	f3bf 8f6f 	isb	sy
 8005854:	f3bf 8f4f 	dsb	sy
 8005858:	627b      	str	r3, [r7, #36]	@ 0x24
}
 800585a:	bf00      	nop
 800585c:	bf00      	nop
 800585e:	e7fd      	b.n	800585c <xQueueGenericSend+0x60>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 8005860:	683b      	ldr	r3, [r7, #0]
 8005862:	2b02      	cmp	r3, #2
 8005864:	d103      	bne.n	800586e <xQueueGenericSend+0x72>
 8005866:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8005868:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800586a:	2b01      	cmp	r3, #1
 800586c:	d101      	bne.n	8005872 <xQueueGenericSend+0x76>
 800586e:	2301      	movs	r3, #1
 8005870:	e000      	b.n	8005874 <xQueueGenericSend+0x78>
 8005872:	2300      	movs	r3, #0
 8005874:	2b00      	cmp	r3, #0
 8005876:	d10b      	bne.n	8005890 <xQueueGenericSend+0x94>
	__asm volatile
 8005878:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800587c:	f383 8811 	msr	BASEPRI, r3
 8005880:	f3bf 8f6f 	isb	sy
 8005884:	f3bf 8f4f 	dsb	sy
 8005888:	623b      	str	r3, [r7, #32]
}
 800588a:	bf00      	nop
 800588c:	bf00      	nop
 800588e:	e7fd      	b.n	800588c <xQueueGenericSend+0x90>
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8005890:	f001 f9fc 	bl	8006c8c <xTaskGetSchedulerState>
 8005894:	4603      	mov	r3, r0
 8005896:	2b00      	cmp	r3, #0
 8005898:	d102      	bne.n	80058a0 <xQueueGenericSend+0xa4>
 800589a:	687b      	ldr	r3, [r7, #4]
 800589c:	2b00      	cmp	r3, #0
 800589e:	d101      	bne.n	80058a4 <xQueueGenericSend+0xa8>
 80058a0:	2301      	movs	r3, #1
 80058a2:	e000      	b.n	80058a6 <xQueueGenericSend+0xaa>
 80058a4:	2300      	movs	r3, #0
 80058a6:	2b00      	cmp	r3, #0
 80058a8:	d10b      	bne.n	80058c2 <xQueueGenericSend+0xc6>
	__asm volatile
 80058aa:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80058ae:	f383 8811 	msr	BASEPRI, r3
 80058b2:	f3bf 8f6f 	isb	sy
 80058b6:	f3bf 8f4f 	dsb	sy
 80058ba:	61fb      	str	r3, [r7, #28]
}
 80058bc:	bf00      	nop
 80058be:	bf00      	nop
 80058c0:	e7fd      	b.n	80058be <xQueueGenericSend+0xc2>
	/*lint -save -e904 This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 80058c2:	f002 f861 	bl	8007988 <vPortEnterCritical>
		{
			/* Is there room on the queue now?  The running task must be the
			highest priority task wanting to access the queue.  If the head item
			in the queue is to be overwritten then it does not matter if the
			queue is full. */
			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 80058c6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80058c8:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 80058ca:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80058cc:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80058ce:	429a      	cmp	r2, r3
 80058d0:	d302      	bcc.n	80058d8 <xQueueGenericSend+0xdc>
 80058d2:	683b      	ldr	r3, [r7, #0]
 80058d4:	2b02      	cmp	r3, #2
 80058d6:	d129      	bne.n	800592c <xQueueGenericSend+0x130>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 80058d8:	683a      	ldr	r2, [r7, #0]
 80058da:	68b9      	ldr	r1, [r7, #8]
 80058dc:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 80058de:	f000 fa0f 	bl	8005d00 <prvCopyDataToQueue>
 80058e2:	62f8      	str	r0, [r7, #44]	@ 0x2c

					/* If there was a task waiting for data to arrive on the
					queue then unblock it now. */
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 80058e4:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80058e6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80058e8:	2b00      	cmp	r3, #0
 80058ea:	d010      	beq.n	800590e <xQueueGenericSend+0x112>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 80058ec:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80058ee:	3324      	adds	r3, #36	@ 0x24
 80058f0:	4618      	mov	r0, r3
 80058f2:	f001 f805 	bl	8006900 <xTaskRemoveFromEventList>
 80058f6:	4603      	mov	r3, r0
 80058f8:	2b00      	cmp	r3, #0
 80058fa:	d013      	beq.n	8005924 <xQueueGenericSend+0x128>
						{
							/* The unblocked task has a priority higher than
							our own so yield immediately.  Yes it is ok to do
							this from within the critical section - the kernel
							takes care of that. */
							queueYIELD_IF_USING_PREEMPTION();
 80058fc:	4b3f      	ldr	r3, [pc, #252]	@ (80059fc <xQueueGenericSend+0x200>)
 80058fe:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8005902:	601a      	str	r2, [r3, #0]
 8005904:	f3bf 8f4f 	dsb	sy
 8005908:	f3bf 8f6f 	isb	sy
 800590c:	e00a      	b.n	8005924 <xQueueGenericSend+0x128>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}
					}
					else if( xYieldRequired != pdFALSE )
 800590e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8005910:	2b00      	cmp	r3, #0
 8005912:	d007      	beq.n	8005924 <xQueueGenericSend+0x128>
					{
						/* This path is a special case that will only get
						executed if the task was holding multiple mutexes and
						the mutexes were given back in an order that is
						different to that in which they were taken. */
						queueYIELD_IF_USING_PREEMPTION();
 8005914:	4b39      	ldr	r3, [pc, #228]	@ (80059fc <xQueueGenericSend+0x200>)
 8005916:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 800591a:	601a      	str	r2, [r3, #0]
 800591c:	f3bf 8f4f 	dsb	sy
 8005920:	f3bf 8f6f 	isb	sy
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif /* configUSE_QUEUE_SETS */

				taskEXIT_CRITICAL();
 8005924:	f002 f862 	bl	80079ec <vPortExitCritical>
				return pdPASS;
 8005928:	2301      	movs	r3, #1
 800592a:	e063      	b.n	80059f4 <xQueueGenericSend+0x1f8>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 800592c:	687b      	ldr	r3, [r7, #4]
 800592e:	2b00      	cmp	r3, #0
 8005930:	d103      	bne.n	800593a <xQueueGenericSend+0x13e>
				{
					/* The queue was full and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 8005932:	f002 f85b 	bl	80079ec <vPortExitCritical>

					/* Return to the original privilege level before exiting
					the function. */
					traceQUEUE_SEND_FAILED( pxQueue );
					return errQUEUE_FULL;
 8005936:	2300      	movs	r3, #0
 8005938:	e05c      	b.n	80059f4 <xQueueGenericSend+0x1f8>
				}
				else if( xEntryTimeSet == pdFALSE )
 800593a:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800593c:	2b00      	cmp	r3, #0
 800593e:	d106      	bne.n	800594e <xQueueGenericSend+0x152>
				{
					/* The queue was full and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 8005940:	f107 0314 	add.w	r3, r7, #20
 8005944:	4618      	mov	r0, r3
 8005946:	f001 f83f 	bl	80069c8 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 800594a:	2301      	movs	r3, #1
 800594c:	637b      	str	r3, [r7, #52]	@ 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 800594e:	f002 f84d 	bl	80079ec <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 8005952:	f000 fda7 	bl	80064a4 <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 8005956:	f002 f817 	bl	8007988 <vPortEnterCritical>
 800595a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800595c:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8005960:	b25b      	sxtb	r3, r3
 8005962:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8005966:	d103      	bne.n	8005970 <xQueueGenericSend+0x174>
 8005968:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800596a:	2200      	movs	r2, #0
 800596c:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8005970:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8005972:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8005976:	b25b      	sxtb	r3, r3
 8005978:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 800597c:	d103      	bne.n	8005986 <xQueueGenericSend+0x18a>
 800597e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8005980:	2200      	movs	r2, #0
 8005982:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8005986:	f002 f831 	bl	80079ec <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 800598a:	1d3a      	adds	r2, r7, #4
 800598c:	f107 0314 	add.w	r3, r7, #20
 8005990:	4611      	mov	r1, r2
 8005992:	4618      	mov	r0, r3
 8005994:	f001 f82e 	bl	80069f4 <xTaskCheckForTimeOut>
 8005998:	4603      	mov	r3, r0
 800599a:	2b00      	cmp	r3, #0
 800599c:	d124      	bne.n	80059e8 <xQueueGenericSend+0x1ec>
		{
			if( prvIsQueueFull( pxQueue ) != pdFALSE )
 800599e:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 80059a0:	f000 faa6 	bl	8005ef0 <prvIsQueueFull>
 80059a4:	4603      	mov	r3, r0
 80059a6:	2b00      	cmp	r3, #0
 80059a8:	d018      	beq.n	80059dc <xQueueGenericSend+0x1e0>
			{
				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
 80059aa:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80059ac:	3310      	adds	r3, #16
 80059ae:	687a      	ldr	r2, [r7, #4]
 80059b0:	4611      	mov	r1, r2
 80059b2:	4618      	mov	r0, r3
 80059b4:	f000 ff52 	bl	800685c <vTaskPlaceOnEventList>
				/* Unlocking the queue means queue events can effect the
				event list.  It is possible that interrupts occurring now
				remove this task from the event list again - but as the
				scheduler is suspended the task will go onto the pending
				ready last instead of the actual ready list. */
				prvUnlockQueue( pxQueue );
 80059b8:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 80059ba:	f000 fa31 	bl	8005e20 <prvUnlockQueue>
				/* Resuming the scheduler will move tasks from the pending
				ready list into the ready list - so it is feasible that this
				task is already in a ready list before it yields - in which
				case the yield will not cause a context switch unless there
				is also a higher priority task in the pending ready list. */
				if( xTaskResumeAll() == pdFALSE )
 80059be:	f000 fd7f 	bl	80064c0 <xTaskResumeAll>
 80059c2:	4603      	mov	r3, r0
 80059c4:	2b00      	cmp	r3, #0
 80059c6:	f47f af7c 	bne.w	80058c2 <xQueueGenericSend+0xc6>
				{
					portYIELD_WITHIN_API();
 80059ca:	4b0c      	ldr	r3, [pc, #48]	@ (80059fc <xQueueGenericSend+0x200>)
 80059cc:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80059d0:	601a      	str	r2, [r3, #0]
 80059d2:	f3bf 8f4f 	dsb	sy
 80059d6:	f3bf 8f6f 	isb	sy
 80059da:	e772      	b.n	80058c2 <xQueueGenericSend+0xc6>
				}
			}
			else
			{
				/* Try again. */
				prvUnlockQueue( pxQueue );
 80059dc:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 80059de:	f000 fa1f 	bl	8005e20 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 80059e2:	f000 fd6d 	bl	80064c0 <xTaskResumeAll>
 80059e6:	e76c      	b.n	80058c2 <xQueueGenericSend+0xc6>
			}
		}
		else
		{
			/* The timeout has expired. */
			prvUnlockQueue( pxQueue );
 80059e8:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 80059ea:	f000 fa19 	bl	8005e20 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 80059ee:	f000 fd67 	bl	80064c0 <xTaskResumeAll>

			traceQUEUE_SEND_FAILED( pxQueue );
			return errQUEUE_FULL;
 80059f2:	2300      	movs	r3, #0
		}
	} /*lint -restore */
}
 80059f4:	4618      	mov	r0, r3
 80059f6:	3738      	adds	r7, #56	@ 0x38
 80059f8:	46bd      	mov	sp, r7
 80059fa:	bd80      	pop	{r7, pc}
 80059fc:	e000ed04 	.word	0xe000ed04

08005a00 <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
 8005a00:	b580      	push	{r7, lr}
 8005a02:	b090      	sub	sp, #64	@ 0x40
 8005a04:	af00      	add	r7, sp, #0
 8005a06:	60f8      	str	r0, [r7, #12]
 8005a08:	60b9      	str	r1, [r7, #8]
 8005a0a:	607a      	str	r2, [r7, #4]
 8005a0c:	603b      	str	r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 8005a0e:	68fb      	ldr	r3, [r7, #12]
 8005a10:	63bb      	str	r3, [r7, #56]	@ 0x38

	configASSERT( pxQueue );
 8005a12:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005a14:	2b00      	cmp	r3, #0
 8005a16:	d10b      	bne.n	8005a30 <xQueueGenericSendFromISR+0x30>
	__asm volatile
 8005a18:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005a1c:	f383 8811 	msr	BASEPRI, r3
 8005a20:	f3bf 8f6f 	isb	sy
 8005a24:	f3bf 8f4f 	dsb	sy
 8005a28:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 8005a2a:	bf00      	nop
 8005a2c:	bf00      	nop
 8005a2e:	e7fd      	b.n	8005a2c <xQueueGenericSendFromISR+0x2c>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8005a30:	68bb      	ldr	r3, [r7, #8]
 8005a32:	2b00      	cmp	r3, #0
 8005a34:	d103      	bne.n	8005a3e <xQueueGenericSendFromISR+0x3e>
 8005a36:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005a38:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005a3a:	2b00      	cmp	r3, #0
 8005a3c:	d101      	bne.n	8005a42 <xQueueGenericSendFromISR+0x42>
 8005a3e:	2301      	movs	r3, #1
 8005a40:	e000      	b.n	8005a44 <xQueueGenericSendFromISR+0x44>
 8005a42:	2300      	movs	r3, #0
 8005a44:	2b00      	cmp	r3, #0
 8005a46:	d10b      	bne.n	8005a60 <xQueueGenericSendFromISR+0x60>
	__asm volatile
 8005a48:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005a4c:	f383 8811 	msr	BASEPRI, r3
 8005a50:	f3bf 8f6f 	isb	sy
 8005a54:	f3bf 8f4f 	dsb	sy
 8005a58:	627b      	str	r3, [r7, #36]	@ 0x24
}
 8005a5a:	bf00      	nop
 8005a5c:	bf00      	nop
 8005a5e:	e7fd      	b.n	8005a5c <xQueueGenericSendFromISR+0x5c>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 8005a60:	683b      	ldr	r3, [r7, #0]
 8005a62:	2b02      	cmp	r3, #2
 8005a64:	d103      	bne.n	8005a6e <xQueueGenericSendFromISR+0x6e>
 8005a66:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005a68:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8005a6a:	2b01      	cmp	r3, #1
 8005a6c:	d101      	bne.n	8005a72 <xQueueGenericSendFromISR+0x72>
 8005a6e:	2301      	movs	r3, #1
 8005a70:	e000      	b.n	8005a74 <xQueueGenericSendFromISR+0x74>
 8005a72:	2300      	movs	r3, #0
 8005a74:	2b00      	cmp	r3, #0
 8005a76:	d10b      	bne.n	8005a90 <xQueueGenericSendFromISR+0x90>
	__asm volatile
 8005a78:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005a7c:	f383 8811 	msr	BASEPRI, r3
 8005a80:	f3bf 8f6f 	isb	sy
 8005a84:	f3bf 8f4f 	dsb	sy
 8005a88:	623b      	str	r3, [r7, #32]
}
 8005a8a:	bf00      	nop
 8005a8c:	bf00      	nop
 8005a8e:	e7fd      	b.n	8005a8c <xQueueGenericSendFromISR+0x8c>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 8005a90:	f002 f85a 	bl	8007b48 <vPortValidateInterruptPriority>

portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;

	__asm volatile
 8005a94:	f3ef 8211 	mrs	r2, BASEPRI
 8005a98:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005a9c:	f383 8811 	msr	BASEPRI, r3
 8005aa0:	f3bf 8f6f 	isb	sy
 8005aa4:	f3bf 8f4f 	dsb	sy
 8005aa8:	61fa      	str	r2, [r7, #28]
 8005aaa:	61bb      	str	r3, [r7, #24]
		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);

	/* This return will not be reached but is necessary to prevent compiler
	warnings. */
	return ulOriginalBASEPRI;
 8005aac:	69fb      	ldr	r3, [r7, #28]
	/* Similar to xQueueGenericSend, except without blocking if there is no room
	in the queue.  Also don't directly wake a task that was blocked on a queue
	read, instead return a flag to say whether a context switch is required or
	not (i.e. has a task with a higher priority than us been woken by this
	post). */
	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8005aae:	637b      	str	r3, [r7, #52]	@ 0x34
	{
		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 8005ab0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005ab2:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8005ab4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005ab6:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8005ab8:	429a      	cmp	r2, r3
 8005aba:	d302      	bcc.n	8005ac2 <xQueueGenericSendFromISR+0xc2>
 8005abc:	683b      	ldr	r3, [r7, #0]
 8005abe:	2b02      	cmp	r3, #2
 8005ac0:	d12f      	bne.n	8005b22 <xQueueGenericSendFromISR+0x122>
		{
			const int8_t cTxLock = pxQueue->cTxLock;
 8005ac2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005ac4:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8005ac8:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
 8005acc:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005ace:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005ad0:	62fb      	str	r3, [r7, #44]	@ 0x2c
			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
			in a task disinheriting a priority and prvCopyDataToQueue() can be
			called here even though the disinherit function does not check if
			the scheduler is suspended before accessing the ready lists. */
			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 8005ad2:	683a      	ldr	r2, [r7, #0]
 8005ad4:	68b9      	ldr	r1, [r7, #8]
 8005ad6:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
 8005ad8:	f000 f912 	bl	8005d00 <prvCopyDataToQueue>

			/* The event list is not altered if the queue is locked.  This will
			be done when the queue is unlocked later. */
			if( cTxLock == queueUNLOCKED )
 8005adc:	f997 3033 	ldrsb.w	r3, [r7, #51]	@ 0x33
 8005ae0:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8005ae4:	d112      	bne.n	8005b0c <xQueueGenericSendFromISR+0x10c>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8005ae6:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005ae8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005aea:	2b00      	cmp	r3, #0
 8005aec:	d016      	beq.n	8005b1c <xQueueGenericSendFromISR+0x11c>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8005aee:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005af0:	3324      	adds	r3, #36	@ 0x24
 8005af2:	4618      	mov	r0, r3
 8005af4:	f000 ff04 	bl	8006900 <xTaskRemoveFromEventList>
 8005af8:	4603      	mov	r3, r0
 8005afa:	2b00      	cmp	r3, #0
 8005afc:	d00e      	beq.n	8005b1c <xQueueGenericSendFromISR+0x11c>
						{
							/* The task waiting has a higher priority so record that a
							context	switch is required. */
							if( pxHigherPriorityTaskWoken != NULL )
 8005afe:	687b      	ldr	r3, [r7, #4]
 8005b00:	2b00      	cmp	r3, #0
 8005b02:	d00b      	beq.n	8005b1c <xQueueGenericSendFromISR+0x11c>
							{
								*pxHigherPriorityTaskWoken = pdTRUE;
 8005b04:	687b      	ldr	r3, [r7, #4]
 8005b06:	2201      	movs	r2, #1
 8005b08:	601a      	str	r2, [r3, #0]
 8005b0a:	e007      	b.n	8005b1c <xQueueGenericSendFromISR+0x11c>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was posted while it was locked. */
				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
 8005b0c:	f897 3033 	ldrb.w	r3, [r7, #51]	@ 0x33
 8005b10:	3301      	adds	r3, #1
 8005b12:	b2db      	uxtb	r3, r3
 8005b14:	b25a      	sxtb	r2, r3
 8005b16:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005b18:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
			}

			xReturn = pdPASS;
 8005b1c:	2301      	movs	r3, #1
 8005b1e:	63fb      	str	r3, [r7, #60]	@ 0x3c
		{
 8005b20:	e001      	b.n	8005b26 <xQueueGenericSendFromISR+0x126>
		}
		else
		{
			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
			xReturn = errQUEUE_FULL;
 8005b22:	2300      	movs	r3, #0
 8005b24:	63fb      	str	r3, [r7, #60]	@ 0x3c
 8005b26:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8005b28:	617b      	str	r3, [r7, #20]
}
/*-----------------------------------------------------------*/

portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
	__asm volatile
 8005b2a:	697b      	ldr	r3, [r7, #20]
 8005b2c:	f383 8811 	msr	BASEPRI, r3
	(
		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
	);
}
 8005b30:	bf00      	nop
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 8005b32:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
}
 8005b34:	4618      	mov	r0, r3
 8005b36:	3740      	adds	r7, #64	@ 0x40
 8005b38:	46bd      	mov	sp, r7
 8005b3a:	bd80      	pop	{r7, pc}

08005b3c <xQueueReceive>:
	return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
 8005b3c:	b580      	push	{r7, lr}
 8005b3e:	b08c      	sub	sp, #48	@ 0x30
 8005b40:	af00      	add	r7, sp, #0
 8005b42:	60f8      	str	r0, [r7, #12]
 8005b44:	60b9      	str	r1, [r7, #8]
 8005b46:	607a      	str	r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
 8005b48:	2300      	movs	r3, #0
 8005b4a:	62fb      	str	r3, [r7, #44]	@ 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 8005b4c:	68fb      	ldr	r3, [r7, #12]
 8005b4e:	62bb      	str	r3, [r7, #40]	@ 0x28

	/* Check the pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 8005b50:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005b52:	2b00      	cmp	r3, #0
 8005b54:	d10b      	bne.n	8005b6e <xQueueReceive+0x32>
	__asm volatile
 8005b56:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005b5a:	f383 8811 	msr	BASEPRI, r3
 8005b5e:	f3bf 8f6f 	isb	sy
 8005b62:	f3bf 8f4f 	dsb	sy
 8005b66:	623b      	str	r3, [r7, #32]
}
 8005b68:	bf00      	nop
 8005b6a:	bf00      	nop
 8005b6c:	e7fd      	b.n	8005b6a <xQueueReceive+0x2e>

	/* The buffer into which data is received can only be NULL if the data size
	is zero (so no data is copied into the buffer. */
	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8005b6e:	68bb      	ldr	r3, [r7, #8]
 8005b70:	2b00      	cmp	r3, #0
 8005b72:	d103      	bne.n	8005b7c <xQueueReceive+0x40>
 8005b74:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005b76:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005b78:	2b00      	cmp	r3, #0
 8005b7a:	d101      	bne.n	8005b80 <xQueueReceive+0x44>
 8005b7c:	2301      	movs	r3, #1
 8005b7e:	e000      	b.n	8005b82 <xQueueReceive+0x46>
 8005b80:	2300      	movs	r3, #0
 8005b82:	2b00      	cmp	r3, #0
 8005b84:	d10b      	bne.n	8005b9e <xQueueReceive+0x62>
	__asm volatile
 8005b86:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005b8a:	f383 8811 	msr	BASEPRI, r3
 8005b8e:	f3bf 8f6f 	isb	sy
 8005b92:	f3bf 8f4f 	dsb	sy
 8005b96:	61fb      	str	r3, [r7, #28]
}
 8005b98:	bf00      	nop
 8005b9a:	bf00      	nop
 8005b9c:	e7fd      	b.n	8005b9a <xQueueReceive+0x5e>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8005b9e:	f001 f875 	bl	8006c8c <xTaskGetSchedulerState>
 8005ba2:	4603      	mov	r3, r0
 8005ba4:	2b00      	cmp	r3, #0
 8005ba6:	d102      	bne.n	8005bae <xQueueReceive+0x72>
 8005ba8:	687b      	ldr	r3, [r7, #4]
 8005baa:	2b00      	cmp	r3, #0
 8005bac:	d101      	bne.n	8005bb2 <xQueueReceive+0x76>
 8005bae:	2301      	movs	r3, #1
 8005bb0:	e000      	b.n	8005bb4 <xQueueReceive+0x78>
 8005bb2:	2300      	movs	r3, #0
 8005bb4:	2b00      	cmp	r3, #0
 8005bb6:	d10b      	bne.n	8005bd0 <xQueueReceive+0x94>
	__asm volatile
 8005bb8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005bbc:	f383 8811 	msr	BASEPRI, r3
 8005bc0:	f3bf 8f6f 	isb	sy
 8005bc4:	f3bf 8f4f 	dsb	sy
 8005bc8:	61bb      	str	r3, [r7, #24]
}
 8005bca:	bf00      	nop
 8005bcc:	bf00      	nop
 8005bce:	e7fd      	b.n	8005bcc <xQueueReceive+0x90>
	/*lint -save -e904  This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8005bd0:	f001 feda 	bl	8007988 <vPortEnterCritical>
		{
			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8005bd4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005bd6:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005bd8:	627b      	str	r3, [r7, #36]	@ 0x24

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8005bda:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8005bdc:	2b00      	cmp	r3, #0
 8005bde:	d01f      	beq.n	8005c20 <xQueueReceive+0xe4>
			{
				/* Data available, remove one item. */
				prvCopyDataFromQueue( pxQueue, pvBuffer );
 8005be0:	68b9      	ldr	r1, [r7, #8]
 8005be2:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8005be4:	f000 f8f6 	bl	8005dd4 <prvCopyDataFromQueue>
				traceQUEUE_RECEIVE( pxQueue );
				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 8005be8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8005bea:	1e5a      	subs	r2, r3, #1
 8005bec:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005bee:	639a      	str	r2, [r3, #56]	@ 0x38

				/* There is now space in the queue, were any tasks waiting to
				post to the queue?  If so, unblock the highest priority waiting
				task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8005bf0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005bf2:	691b      	ldr	r3, [r3, #16]
 8005bf4:	2b00      	cmp	r3, #0
 8005bf6:	d00f      	beq.n	8005c18 <xQueueReceive+0xdc>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8005bf8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005bfa:	3310      	adds	r3, #16
 8005bfc:	4618      	mov	r0, r3
 8005bfe:	f000 fe7f 	bl	8006900 <xTaskRemoveFromEventList>
 8005c02:	4603      	mov	r3, r0
 8005c04:	2b00      	cmp	r3, #0
 8005c06:	d007      	beq.n	8005c18 <xQueueReceive+0xdc>
					{
						queueYIELD_IF_USING_PREEMPTION();
 8005c08:	4b3c      	ldr	r3, [pc, #240]	@ (8005cfc <xQueueReceive+0x1c0>)
 8005c0a:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8005c0e:	601a      	str	r2, [r3, #0]
 8005c10:	f3bf 8f4f 	dsb	sy
 8005c14:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 8005c18:	f001 fee8 	bl	80079ec <vPortExitCritical>
				return pdPASS;
 8005c1c:	2301      	movs	r3, #1
 8005c1e:	e069      	b.n	8005cf4 <xQueueReceive+0x1b8>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 8005c20:	687b      	ldr	r3, [r7, #4]
 8005c22:	2b00      	cmp	r3, #0
 8005c24:	d103      	bne.n	8005c2e <xQueueReceive+0xf2>
				{
					/* The queue was empty and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 8005c26:	f001 fee1 	bl	80079ec <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 8005c2a:	2300      	movs	r3, #0
 8005c2c:	e062      	b.n	8005cf4 <xQueueReceive+0x1b8>
				}
				else if( xEntryTimeSet == pdFALSE )
 8005c2e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8005c30:	2b00      	cmp	r3, #0
 8005c32:	d106      	bne.n	8005c42 <xQueueReceive+0x106>
				{
					/* The queue was empty and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 8005c34:	f107 0310 	add.w	r3, r7, #16
 8005c38:	4618      	mov	r0, r3
 8005c3a:	f000 fec5 	bl	80069c8 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 8005c3e:	2301      	movs	r3, #1
 8005c40:	62fb      	str	r3, [r7, #44]	@ 0x2c
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 8005c42:	f001 fed3 	bl	80079ec <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 8005c46:	f000 fc2d 	bl	80064a4 <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 8005c4a:	f001 fe9d 	bl	8007988 <vPortEnterCritical>
 8005c4e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005c50:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8005c54:	b25b      	sxtb	r3, r3
 8005c56:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8005c5a:	d103      	bne.n	8005c64 <xQueueReceive+0x128>
 8005c5c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005c5e:	2200      	movs	r2, #0
 8005c60:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8005c64:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005c66:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8005c6a:	b25b      	sxtb	r3, r3
 8005c6c:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8005c70:	d103      	bne.n	8005c7a <xQueueReceive+0x13e>
 8005c72:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005c74:	2200      	movs	r2, #0
 8005c76:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8005c7a:	f001 feb7 	bl	80079ec <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 8005c7e:	1d3a      	adds	r2, r7, #4
 8005c80:	f107 0310 	add.w	r3, r7, #16
 8005c84:	4611      	mov	r1, r2
 8005c86:	4618      	mov	r0, r3
 8005c88:	f000 feb4 	bl	80069f4 <xTaskCheckForTimeOut>
 8005c8c:	4603      	mov	r3, r0
 8005c8e:	2b00      	cmp	r3, #0
 8005c90:	d123      	bne.n	8005cda <xQueueReceive+0x19e>
		{
			/* The timeout has not expired.  If the queue is still empty place
			the task on the list of tasks waiting to receive from the queue. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8005c92:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8005c94:	f000 f916 	bl	8005ec4 <prvIsQueueEmpty>
 8005c98:	4603      	mov	r3, r0
 8005c9a:	2b00      	cmp	r3, #0
 8005c9c:	d017      	beq.n	8005cce <xQueueReceive+0x192>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 8005c9e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005ca0:	3324      	adds	r3, #36	@ 0x24
 8005ca2:	687a      	ldr	r2, [r7, #4]
 8005ca4:	4611      	mov	r1, r2
 8005ca6:	4618      	mov	r0, r3
 8005ca8:	f000 fdd8 	bl	800685c <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8005cac:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8005cae:	f000 f8b7 	bl	8005e20 <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 8005cb2:	f000 fc05 	bl	80064c0 <xTaskResumeAll>
 8005cb6:	4603      	mov	r3, r0
 8005cb8:	2b00      	cmp	r3, #0
 8005cba:	d189      	bne.n	8005bd0 <xQueueReceive+0x94>
				{
					portYIELD_WITHIN_API();
 8005cbc:	4b0f      	ldr	r3, [pc, #60]	@ (8005cfc <xQueueReceive+0x1c0>)
 8005cbe:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8005cc2:	601a      	str	r2, [r3, #0]
 8005cc4:	f3bf 8f4f 	dsb	sy
 8005cc8:	f3bf 8f6f 	isb	sy
 8005ccc:	e780      	b.n	8005bd0 <xQueueReceive+0x94>
			}
			else
			{
				/* The queue contains data again.  Loop back to try and read the
				data. */
				prvUnlockQueue( pxQueue );
 8005cce:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8005cd0:	f000 f8a6 	bl	8005e20 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 8005cd4:	f000 fbf4 	bl	80064c0 <xTaskResumeAll>
 8005cd8:	e77a      	b.n	8005bd0 <xQueueReceive+0x94>
		}
		else
		{
			/* Timed out.  If there is no data in the queue exit, otherwise loop
			back and attempt to read the data. */
			prvUnlockQueue( pxQueue );
 8005cda:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8005cdc:	f000 f8a0 	bl	8005e20 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8005ce0:	f000 fbee 	bl	80064c0 <xTaskResumeAll>

			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8005ce4:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8005ce6:	f000 f8ed 	bl	8005ec4 <prvIsQueueEmpty>
 8005cea:	4603      	mov	r3, r0
 8005cec:	2b00      	cmp	r3, #0
 8005cee:	f43f af6f 	beq.w	8005bd0 <xQueueReceive+0x94>
			{
				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 8005cf2:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 8005cf4:	4618      	mov	r0, r3
 8005cf6:	3730      	adds	r7, #48	@ 0x30
 8005cf8:	46bd      	mov	sp, r7
 8005cfa:	bd80      	pop	{r7, pc}
 8005cfc:	e000ed04 	.word	0xe000ed04

08005d00 <prvCopyDataToQueue>:

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
 8005d00:	b580      	push	{r7, lr}
 8005d02:	b086      	sub	sp, #24
 8005d04:	af00      	add	r7, sp, #0
 8005d06:	60f8      	str	r0, [r7, #12]
 8005d08:	60b9      	str	r1, [r7, #8]
 8005d0a:	607a      	str	r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
 8005d0c:	2300      	movs	r3, #0
 8005d0e:	617b      	str	r3, [r7, #20]
UBaseType_t uxMessagesWaiting;

	/* This function is called from a critical section. */

	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8005d10:	68fb      	ldr	r3, [r7, #12]
 8005d12:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005d14:	613b      	str	r3, [r7, #16]

	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
 8005d16:	68fb      	ldr	r3, [r7, #12]
 8005d18:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005d1a:	2b00      	cmp	r3, #0
 8005d1c:	d10d      	bne.n	8005d3a <prvCopyDataToQueue+0x3a>
	{
		#if ( configUSE_MUTEXES == 1 )
		{
			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 8005d1e:	68fb      	ldr	r3, [r7, #12]
 8005d20:	681b      	ldr	r3, [r3, #0]
 8005d22:	2b00      	cmp	r3, #0
 8005d24:	d14d      	bne.n	8005dc2 <prvCopyDataToQueue+0xc2>
			{
				/* The mutex is no longer being held. */
				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
 8005d26:	68fb      	ldr	r3, [r7, #12]
 8005d28:	689b      	ldr	r3, [r3, #8]
 8005d2a:	4618      	mov	r0, r3
 8005d2c:	f000 ffcc 	bl	8006cc8 <xTaskPriorityDisinherit>
 8005d30:	6178      	str	r0, [r7, #20]
				pxQueue->u.xSemaphore.xMutexHolder = NULL;
 8005d32:	68fb      	ldr	r3, [r7, #12]
 8005d34:	2200      	movs	r2, #0
 8005d36:	609a      	str	r2, [r3, #8]
 8005d38:	e043      	b.n	8005dc2 <prvCopyDataToQueue+0xc2>
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configUSE_MUTEXES */
	}
	else if( xPosition == queueSEND_TO_BACK )
 8005d3a:	687b      	ldr	r3, [r7, #4]
 8005d3c:	2b00      	cmp	r3, #0
 8005d3e:	d119      	bne.n	8005d74 <prvCopyDataToQueue+0x74>
	{
		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8005d40:	68fb      	ldr	r3, [r7, #12]
 8005d42:	6858      	ldr	r0, [r3, #4]
 8005d44:	68fb      	ldr	r3, [r7, #12]
 8005d46:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005d48:	461a      	mov	r2, r3
 8005d4a:	68b9      	ldr	r1, [r7, #8]
 8005d4c:	f002 f9b8 	bl	80080c0 <memcpy>
		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 8005d50:	68fb      	ldr	r3, [r7, #12]
 8005d52:	685a      	ldr	r2, [r3, #4]
 8005d54:	68fb      	ldr	r3, [r7, #12]
 8005d56:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005d58:	441a      	add	r2, r3
 8005d5a:	68fb      	ldr	r3, [r7, #12]
 8005d5c:	605a      	str	r2, [r3, #4]
		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 8005d5e:	68fb      	ldr	r3, [r7, #12]
 8005d60:	685a      	ldr	r2, [r3, #4]
 8005d62:	68fb      	ldr	r3, [r7, #12]
 8005d64:	689b      	ldr	r3, [r3, #8]
 8005d66:	429a      	cmp	r2, r3
 8005d68:	d32b      	bcc.n	8005dc2 <prvCopyDataToQueue+0xc2>
		{
			pxQueue->pcWriteTo = pxQueue->pcHead;
 8005d6a:	68fb      	ldr	r3, [r7, #12]
 8005d6c:	681a      	ldr	r2, [r3, #0]
 8005d6e:	68fb      	ldr	r3, [r7, #12]
 8005d70:	605a      	str	r2, [r3, #4]
 8005d72:	e026      	b.n	8005dc2 <prvCopyDataToQueue+0xc2>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
 8005d74:	68fb      	ldr	r3, [r7, #12]
 8005d76:	68d8      	ldr	r0, [r3, #12]
 8005d78:	68fb      	ldr	r3, [r7, #12]
 8005d7a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005d7c:	461a      	mov	r2, r3
 8005d7e:	68b9      	ldr	r1, [r7, #8]
 8005d80:	f002 f99e 	bl	80080c0 <memcpy>
		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
 8005d84:	68fb      	ldr	r3, [r7, #12]
 8005d86:	68da      	ldr	r2, [r3, #12]
 8005d88:	68fb      	ldr	r3, [r7, #12]
 8005d8a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005d8c:	425b      	negs	r3, r3
 8005d8e:	441a      	add	r2, r3
 8005d90:	68fb      	ldr	r3, [r7, #12]
 8005d92:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 8005d94:	68fb      	ldr	r3, [r7, #12]
 8005d96:	68da      	ldr	r2, [r3, #12]
 8005d98:	68fb      	ldr	r3, [r7, #12]
 8005d9a:	681b      	ldr	r3, [r3, #0]
 8005d9c:	429a      	cmp	r2, r3
 8005d9e:	d207      	bcs.n	8005db0 <prvCopyDataToQueue+0xb0>
		{
			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
 8005da0:	68fb      	ldr	r3, [r7, #12]
 8005da2:	689a      	ldr	r2, [r3, #8]
 8005da4:	68fb      	ldr	r3, [r7, #12]
 8005da6:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005da8:	425b      	negs	r3, r3
 8005daa:	441a      	add	r2, r3
 8005dac:	68fb      	ldr	r3, [r7, #12]
 8005dae:	60da      	str	r2, [r3, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		if( xPosition == queueOVERWRITE )
 8005db0:	687b      	ldr	r3, [r7, #4]
 8005db2:	2b02      	cmp	r3, #2
 8005db4:	d105      	bne.n	8005dc2 <prvCopyDataToQueue+0xc2>
		{
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8005db6:	693b      	ldr	r3, [r7, #16]
 8005db8:	2b00      	cmp	r3, #0
 8005dba:	d002      	beq.n	8005dc2 <prvCopyDataToQueue+0xc2>
			{
				/* An item is not being added but overwritten, so subtract
				one from the recorded number of items in the queue so when
				one is added again below the number of recorded items remains
				correct. */
				--uxMessagesWaiting;
 8005dbc:	693b      	ldr	r3, [r7, #16]
 8005dbe:	3b01      	subs	r3, #1
 8005dc0:	613b      	str	r3, [r7, #16]
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 8005dc2:	693b      	ldr	r3, [r7, #16]
 8005dc4:	1c5a      	adds	r2, r3, #1
 8005dc6:	68fb      	ldr	r3, [r7, #12]
 8005dc8:	639a      	str	r2, [r3, #56]	@ 0x38

	return xReturn;
 8005dca:	697b      	ldr	r3, [r7, #20]
}
 8005dcc:	4618      	mov	r0, r3
 8005dce:	3718      	adds	r7, #24
 8005dd0:	46bd      	mov	sp, r7
 8005dd2:	bd80      	pop	{r7, pc}

08005dd4 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/

static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
 8005dd4:	b580      	push	{r7, lr}
 8005dd6:	b082      	sub	sp, #8
 8005dd8:	af00      	add	r7, sp, #0
 8005dda:	6078      	str	r0, [r7, #4]
 8005ddc:	6039      	str	r1, [r7, #0]
	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
 8005dde:	687b      	ldr	r3, [r7, #4]
 8005de0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005de2:	2b00      	cmp	r3, #0
 8005de4:	d018      	beq.n	8005e18 <prvCopyDataFromQueue+0x44>
	{
		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 8005de6:	687b      	ldr	r3, [r7, #4]
 8005de8:	68da      	ldr	r2, [r3, #12]
 8005dea:	687b      	ldr	r3, [r7, #4]
 8005dec:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005dee:	441a      	add	r2, r3
 8005df0:	687b      	ldr	r3, [r7, #4]
 8005df2:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
 8005df4:	687b      	ldr	r3, [r7, #4]
 8005df6:	68da      	ldr	r2, [r3, #12]
 8005df8:	687b      	ldr	r3, [r7, #4]
 8005dfa:	689b      	ldr	r3, [r3, #8]
 8005dfc:	429a      	cmp	r2, r3
 8005dfe:	d303      	bcc.n	8005e08 <prvCopyDataFromQueue+0x34>
		{
			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 8005e00:	687b      	ldr	r3, [r7, #4]
 8005e02:	681a      	ldr	r2, [r3, #0]
 8005e04:	687b      	ldr	r3, [r7, #4]
 8005e06:	60da      	str	r2, [r3, #12]
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8005e08:	687b      	ldr	r3, [r7, #4]
 8005e0a:	68d9      	ldr	r1, [r3, #12]
 8005e0c:	687b      	ldr	r3, [r7, #4]
 8005e0e:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005e10:	461a      	mov	r2, r3
 8005e12:	6838      	ldr	r0, [r7, #0]
 8005e14:	f002 f954 	bl	80080c0 <memcpy>
	}
}
 8005e18:	bf00      	nop
 8005e1a:	3708      	adds	r7, #8
 8005e1c:	46bd      	mov	sp, r7
 8005e1e:	bd80      	pop	{r7, pc}

08005e20 <prvUnlockQueue>:
/*-----------------------------------------------------------*/

static void prvUnlockQueue( Queue_t * const pxQueue )
{
 8005e20:	b580      	push	{r7, lr}
 8005e22:	b084      	sub	sp, #16
 8005e24:	af00      	add	r7, sp, #0
 8005e26:	6078      	str	r0, [r7, #4]

	/* The lock counts contains the number of extra data items placed or
	removed from the queue while the queue was locked.  When a queue is
	locked items can be added or removed, but the event lists cannot be
	updated. */
	taskENTER_CRITICAL();
 8005e28:	f001 fdae 	bl	8007988 <vPortEnterCritical>
	{
		int8_t cTxLock = pxQueue->cTxLock;
 8005e2c:	687b      	ldr	r3, [r7, #4]
 8005e2e:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8005e32:	73fb      	strb	r3, [r7, #15]

		/* See if data was added to the queue while it was locked. */
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8005e34:	e011      	b.n	8005e5a <prvUnlockQueue+0x3a>
			}
			#else /* configUSE_QUEUE_SETS */
			{
				/* Tasks that are removed from the event list will get added to
				the pending ready list as the scheduler is still suspended. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8005e36:	687b      	ldr	r3, [r7, #4]
 8005e38:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005e3a:	2b00      	cmp	r3, #0
 8005e3c:	d012      	beq.n	8005e64 <prvUnlockQueue+0x44>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8005e3e:	687b      	ldr	r3, [r7, #4]
 8005e40:	3324      	adds	r3, #36	@ 0x24
 8005e42:	4618      	mov	r0, r3
 8005e44:	f000 fd5c 	bl	8006900 <xTaskRemoveFromEventList>
 8005e48:	4603      	mov	r3, r0
 8005e4a:	2b00      	cmp	r3, #0
 8005e4c:	d001      	beq.n	8005e52 <prvUnlockQueue+0x32>
					{
						/* The task waiting has a higher priority so record that
						a context switch is required. */
						vTaskMissedYield();
 8005e4e:	f000 fe35 	bl	8006abc <vTaskMissedYield>
					break;
				}
			}
			#endif /* configUSE_QUEUE_SETS */

			--cTxLock;
 8005e52:	7bfb      	ldrb	r3, [r7, #15]
 8005e54:	3b01      	subs	r3, #1
 8005e56:	b2db      	uxtb	r3, r3
 8005e58:	73fb      	strb	r3, [r7, #15]
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8005e5a:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8005e5e:	2b00      	cmp	r3, #0
 8005e60:	dce9      	bgt.n	8005e36 <prvUnlockQueue+0x16>
 8005e62:	e000      	b.n	8005e66 <prvUnlockQueue+0x46>
					break;
 8005e64:	bf00      	nop
		}

		pxQueue->cTxLock = queueUNLOCKED;
 8005e66:	687b      	ldr	r3, [r7, #4]
 8005e68:	22ff      	movs	r2, #255	@ 0xff
 8005e6a:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
	}
	taskEXIT_CRITICAL();
 8005e6e:	f001 fdbd 	bl	80079ec <vPortExitCritical>

	/* Do the same for the Rx lock. */
	taskENTER_CRITICAL();
 8005e72:	f001 fd89 	bl	8007988 <vPortEnterCritical>
	{
		int8_t cRxLock = pxQueue->cRxLock;
 8005e76:	687b      	ldr	r3, [r7, #4]
 8005e78:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8005e7c:	73bb      	strb	r3, [r7, #14]

		while( cRxLock > queueLOCKED_UNMODIFIED )
 8005e7e:	e011      	b.n	8005ea4 <prvUnlockQueue+0x84>
		{
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8005e80:	687b      	ldr	r3, [r7, #4]
 8005e82:	691b      	ldr	r3, [r3, #16]
 8005e84:	2b00      	cmp	r3, #0
 8005e86:	d012      	beq.n	8005eae <prvUnlockQueue+0x8e>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8005e88:	687b      	ldr	r3, [r7, #4]
 8005e8a:	3310      	adds	r3, #16
 8005e8c:	4618      	mov	r0, r3
 8005e8e:	f000 fd37 	bl	8006900 <xTaskRemoveFromEventList>
 8005e92:	4603      	mov	r3, r0
 8005e94:	2b00      	cmp	r3, #0
 8005e96:	d001      	beq.n	8005e9c <prvUnlockQueue+0x7c>
				{
					vTaskMissedYield();
 8005e98:	f000 fe10 	bl	8006abc <vTaskMissedYield>
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				--cRxLock;
 8005e9c:	7bbb      	ldrb	r3, [r7, #14]
 8005e9e:	3b01      	subs	r3, #1
 8005ea0:	b2db      	uxtb	r3, r3
 8005ea2:	73bb      	strb	r3, [r7, #14]
		while( cRxLock > queueLOCKED_UNMODIFIED )
 8005ea4:	f997 300e 	ldrsb.w	r3, [r7, #14]
 8005ea8:	2b00      	cmp	r3, #0
 8005eaa:	dce9      	bgt.n	8005e80 <prvUnlockQueue+0x60>
 8005eac:	e000      	b.n	8005eb0 <prvUnlockQueue+0x90>
			}
			else
			{
				break;
 8005eae:	bf00      	nop
			}
		}

		pxQueue->cRxLock = queueUNLOCKED;
 8005eb0:	687b      	ldr	r3, [r7, #4]
 8005eb2:	22ff      	movs	r2, #255	@ 0xff
 8005eb4:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
	}
	taskEXIT_CRITICAL();
 8005eb8:	f001 fd98 	bl	80079ec <vPortExitCritical>
}
 8005ebc:	bf00      	nop
 8005ebe:	3710      	adds	r7, #16
 8005ec0:	46bd      	mov	sp, r7
 8005ec2:	bd80      	pop	{r7, pc}

08005ec4 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
 8005ec4:	b580      	push	{r7, lr}
 8005ec6:	b084      	sub	sp, #16
 8005ec8:	af00      	add	r7, sp, #0
 8005eca:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8005ecc:	f001 fd5c 	bl	8007988 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
 8005ed0:	687b      	ldr	r3, [r7, #4]
 8005ed2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005ed4:	2b00      	cmp	r3, #0
 8005ed6:	d102      	bne.n	8005ede <prvIsQueueEmpty+0x1a>
		{
			xReturn = pdTRUE;
 8005ed8:	2301      	movs	r3, #1
 8005eda:	60fb      	str	r3, [r7, #12]
 8005edc:	e001      	b.n	8005ee2 <prvIsQueueEmpty+0x1e>
		}
		else
		{
			xReturn = pdFALSE;
 8005ede:	2300      	movs	r3, #0
 8005ee0:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 8005ee2:	f001 fd83 	bl	80079ec <vPortExitCritical>

	return xReturn;
 8005ee6:	68fb      	ldr	r3, [r7, #12]
}
 8005ee8:	4618      	mov	r0, r3
 8005eea:	3710      	adds	r7, #16
 8005eec:	46bd      	mov	sp, r7
 8005eee:	bd80      	pop	{r7, pc}

08005ef0 <prvIsQueueFull>:
	return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
 8005ef0:	b580      	push	{r7, lr}
 8005ef2:	b084      	sub	sp, #16
 8005ef4:	af00      	add	r7, sp, #0
 8005ef6:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8005ef8:	f001 fd46 	bl	8007988 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
 8005efc:	687b      	ldr	r3, [r7, #4]
 8005efe:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8005f00:	687b      	ldr	r3, [r7, #4]
 8005f02:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8005f04:	429a      	cmp	r2, r3
 8005f06:	d102      	bne.n	8005f0e <prvIsQueueFull+0x1e>
		{
			xReturn = pdTRUE;
 8005f08:	2301      	movs	r3, #1
 8005f0a:	60fb      	str	r3, [r7, #12]
 8005f0c:	e001      	b.n	8005f12 <prvIsQueueFull+0x22>
		}
		else
		{
			xReturn = pdFALSE;
 8005f0e:	2300      	movs	r3, #0
 8005f10:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 8005f12:	f001 fd6b 	bl	80079ec <vPortExitCritical>

	return xReturn;
 8005f16:	68fb      	ldr	r3, [r7, #12]
}
 8005f18:	4618      	mov	r0, r3
 8005f1a:	3710      	adds	r7, #16
 8005f1c:	46bd      	mov	sp, r7
 8005f1e:	bd80      	pop	{r7, pc}

08005f20 <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
	{
 8005f20:	b480      	push	{r7}
 8005f22:	b085      	sub	sp, #20
 8005f24:	af00      	add	r7, sp, #0
 8005f26:	6078      	str	r0, [r7, #4]
 8005f28:	6039      	str	r1, [r7, #0]
	UBaseType_t ux;

		/* See if there is an empty space in the registry.  A NULL name denotes
		a free slot. */
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8005f2a:	2300      	movs	r3, #0
 8005f2c:	60fb      	str	r3, [r7, #12]
 8005f2e:	e014      	b.n	8005f5a <vQueueAddToRegistry+0x3a>
		{
			if( xQueueRegistry[ ux ].pcQueueName == NULL )
 8005f30:	4a0f      	ldr	r2, [pc, #60]	@ (8005f70 <vQueueAddToRegistry+0x50>)
 8005f32:	68fb      	ldr	r3, [r7, #12]
 8005f34:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
 8005f38:	2b00      	cmp	r3, #0
 8005f3a:	d10b      	bne.n	8005f54 <vQueueAddToRegistry+0x34>
			{
				/* Store the information on this queue. */
				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
 8005f3c:	490c      	ldr	r1, [pc, #48]	@ (8005f70 <vQueueAddToRegistry+0x50>)
 8005f3e:	68fb      	ldr	r3, [r7, #12]
 8005f40:	683a      	ldr	r2, [r7, #0]
 8005f42:	f841 2033 	str.w	r2, [r1, r3, lsl #3]
				xQueueRegistry[ ux ].xHandle = xQueue;
 8005f46:	4a0a      	ldr	r2, [pc, #40]	@ (8005f70 <vQueueAddToRegistry+0x50>)
 8005f48:	68fb      	ldr	r3, [r7, #12]
 8005f4a:	00db      	lsls	r3, r3, #3
 8005f4c:	4413      	add	r3, r2
 8005f4e:	687a      	ldr	r2, [r7, #4]
 8005f50:	605a      	str	r2, [r3, #4]

				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
				break;
 8005f52:	e006      	b.n	8005f62 <vQueueAddToRegistry+0x42>
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8005f54:	68fb      	ldr	r3, [r7, #12]
 8005f56:	3301      	adds	r3, #1
 8005f58:	60fb      	str	r3, [r7, #12]
 8005f5a:	68fb      	ldr	r3, [r7, #12]
 8005f5c:	2b07      	cmp	r3, #7
 8005f5e:	d9e7      	bls.n	8005f30 <vQueueAddToRegistry+0x10>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	}
 8005f60:	bf00      	nop
 8005f62:	bf00      	nop
 8005f64:	3714      	adds	r7, #20
 8005f66:	46bd      	mov	sp, r7
 8005f68:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005f6c:	4770      	bx	lr
 8005f6e:	bf00      	nop
 8005f70:	20000f88 	.word	0x20000f88

08005f74 <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/

#if ( configUSE_TIMERS == 1 )

	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8005f74:	b580      	push	{r7, lr}
 8005f76:	b086      	sub	sp, #24
 8005f78:	af00      	add	r7, sp, #0
 8005f7a:	60f8      	str	r0, [r7, #12]
 8005f7c:	60b9      	str	r1, [r7, #8]
 8005f7e:	607a      	str	r2, [r7, #4]
	Queue_t * const pxQueue = xQueue;
 8005f80:	68fb      	ldr	r3, [r7, #12]
 8005f82:	617b      	str	r3, [r7, #20]
		will not actually cause the task to block, just place it on a blocked
		list.  It will not block until the scheduler is unlocked - at which
		time a yield will be performed.  If an item is added to the queue while
		the queue is locked, and the calling task blocks on the queue, then the
		calling task will be immediately unblocked when the queue is unlocked. */
		prvLockQueue( pxQueue );
 8005f84:	f001 fd00 	bl	8007988 <vPortEnterCritical>
 8005f88:	697b      	ldr	r3, [r7, #20]
 8005f8a:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8005f8e:	b25b      	sxtb	r3, r3
 8005f90:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8005f94:	d103      	bne.n	8005f9e <vQueueWaitForMessageRestricted+0x2a>
 8005f96:	697b      	ldr	r3, [r7, #20]
 8005f98:	2200      	movs	r2, #0
 8005f9a:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8005f9e:	697b      	ldr	r3, [r7, #20]
 8005fa0:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8005fa4:	b25b      	sxtb	r3, r3
 8005fa6:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8005faa:	d103      	bne.n	8005fb4 <vQueueWaitForMessageRestricted+0x40>
 8005fac:	697b      	ldr	r3, [r7, #20]
 8005fae:	2200      	movs	r2, #0
 8005fb0:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8005fb4:	f001 fd1a 	bl	80079ec <vPortExitCritical>
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
 8005fb8:	697b      	ldr	r3, [r7, #20]
 8005fba:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005fbc:	2b00      	cmp	r3, #0
 8005fbe:	d106      	bne.n	8005fce <vQueueWaitForMessageRestricted+0x5a>
		{
			/* There is nothing in the queue, block for the specified period. */
			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
 8005fc0:	697b      	ldr	r3, [r7, #20]
 8005fc2:	3324      	adds	r3, #36	@ 0x24
 8005fc4:	687a      	ldr	r2, [r7, #4]
 8005fc6:	68b9      	ldr	r1, [r7, #8]
 8005fc8:	4618      	mov	r0, r3
 8005fca:	f000 fc6d 	bl	80068a8 <vTaskPlaceOnEventListRestricted>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		prvUnlockQueue( pxQueue );
 8005fce:	6978      	ldr	r0, [r7, #20]
 8005fd0:	f7ff ff26 	bl	8005e20 <prvUnlockQueue>
	}
 8005fd4:	bf00      	nop
 8005fd6:	3718      	adds	r7, #24
 8005fd8:	46bd      	mov	sp, r7
 8005fda:	bd80      	pop	{r7, pc}

08005fdc <xTaskCreateStatic>:
									const uint32_t ulStackDepth,
									void * const pvParameters,
									UBaseType_t uxPriority,
									StackType_t * const puxStackBuffer,
									StaticTask_t * const pxTaskBuffer )
	{
 8005fdc:	b580      	push	{r7, lr}
 8005fde:	b08e      	sub	sp, #56	@ 0x38
 8005fe0:	af04      	add	r7, sp, #16
 8005fe2:	60f8      	str	r0, [r7, #12]
 8005fe4:	60b9      	str	r1, [r7, #8]
 8005fe6:	607a      	str	r2, [r7, #4]
 8005fe8:	603b      	str	r3, [r7, #0]
	TCB_t *pxNewTCB;
	TaskHandle_t xReturn;

		configASSERT( puxStackBuffer != NULL );
 8005fea:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8005fec:	2b00      	cmp	r3, #0
 8005fee:	d10b      	bne.n	8006008 <xTaskCreateStatic+0x2c>
	__asm volatile
 8005ff0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8005ff4:	f383 8811 	msr	BASEPRI, r3
 8005ff8:	f3bf 8f6f 	isb	sy
 8005ffc:	f3bf 8f4f 	dsb	sy
 8006000:	623b      	str	r3, [r7, #32]
}
 8006002:	bf00      	nop
 8006004:	bf00      	nop
 8006006:	e7fd      	b.n	8006004 <xTaskCreateStatic+0x28>
		configASSERT( pxTaskBuffer != NULL );
 8006008:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800600a:	2b00      	cmp	r3, #0
 800600c:	d10b      	bne.n	8006026 <xTaskCreateStatic+0x4a>
	__asm volatile
 800600e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006012:	f383 8811 	msr	BASEPRI, r3
 8006016:	f3bf 8f6f 	isb	sy
 800601a:	f3bf 8f4f 	dsb	sy
 800601e:	61fb      	str	r3, [r7, #28]
}
 8006020:	bf00      	nop
 8006022:	bf00      	nop
 8006024:	e7fd      	b.n	8006022 <xTaskCreateStatic+0x46>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticTask_t equals the size of the real task
			structure. */
			volatile size_t xSize = sizeof( StaticTask_t );
 8006026:	23a8      	movs	r3, #168	@ 0xa8
 8006028:	613b      	str	r3, [r7, #16]
			configASSERT( xSize == sizeof( TCB_t ) );
 800602a:	693b      	ldr	r3, [r7, #16]
 800602c:	2ba8      	cmp	r3, #168	@ 0xa8
 800602e:	d00b      	beq.n	8006048 <xTaskCreateStatic+0x6c>
	__asm volatile
 8006030:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006034:	f383 8811 	msr	BASEPRI, r3
 8006038:	f3bf 8f6f 	isb	sy
 800603c:	f3bf 8f4f 	dsb	sy
 8006040:	61bb      	str	r3, [r7, #24]
}
 8006042:	bf00      	nop
 8006044:	bf00      	nop
 8006046:	e7fd      	b.n	8006044 <xTaskCreateStatic+0x68>
			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
 8006048:	693b      	ldr	r3, [r7, #16]
		}
		#endif /* configASSERT_DEFINED */


		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
 800604a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800604c:	2b00      	cmp	r3, #0
 800604e:	d01e      	beq.n	800608e <xTaskCreateStatic+0xb2>
 8006050:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8006052:	2b00      	cmp	r3, #0
 8006054:	d01b      	beq.n	800608e <xTaskCreateStatic+0xb2>
		{
			/* The memory used for the task's TCB and stack are passed into this
			function - use them. */
			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 8006056:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006058:	627b      	str	r3, [r7, #36]	@ 0x24
			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 800605a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800605c:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 800605e:	631a      	str	r2, [r3, #48]	@ 0x30

			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created statically in case the task is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
 8006060:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8006062:	2202      	movs	r2, #2
 8006064:	f883 20a5 	strb.w	r2, [r3, #165]	@ 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
 8006068:	2300      	movs	r3, #0
 800606a:	9303      	str	r3, [sp, #12]
 800606c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800606e:	9302      	str	r3, [sp, #8]
 8006070:	f107 0314 	add.w	r3, r7, #20
 8006074:	9301      	str	r3, [sp, #4]
 8006076:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006078:	9300      	str	r3, [sp, #0]
 800607a:	683b      	ldr	r3, [r7, #0]
 800607c:	687a      	ldr	r2, [r7, #4]
 800607e:	68b9      	ldr	r1, [r7, #8]
 8006080:	68f8      	ldr	r0, [r7, #12]
 8006082:	f000 f851 	bl	8006128 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 8006086:	6a78      	ldr	r0, [r7, #36]	@ 0x24
 8006088:	f000 f8f6 	bl	8006278 <prvAddNewTaskToReadyList>
 800608c:	e001      	b.n	8006092 <xTaskCreateStatic+0xb6>
		}
		else
		{
			xReturn = NULL;
 800608e:	2300      	movs	r3, #0
 8006090:	617b      	str	r3, [r7, #20]
		}

		return xReturn;
 8006092:	697b      	ldr	r3, [r7, #20]
	}
 8006094:	4618      	mov	r0, r3
 8006096:	3728      	adds	r7, #40	@ 0x28
 8006098:	46bd      	mov	sp, r7
 800609a:	bd80      	pop	{r7, pc}

0800609c <xTaskCreate>:
							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
							const configSTACK_DEPTH_TYPE usStackDepth,
							void * const pvParameters,
							UBaseType_t uxPriority,
							TaskHandle_t * const pxCreatedTask )
	{
 800609c:	b580      	push	{r7, lr}
 800609e:	b08c      	sub	sp, #48	@ 0x30
 80060a0:	af04      	add	r7, sp, #16
 80060a2:	60f8      	str	r0, [r7, #12]
 80060a4:	60b9      	str	r1, [r7, #8]
 80060a6:	603b      	str	r3, [r7, #0]
 80060a8:	4613      	mov	r3, r2
 80060aa:	80fb      	strh	r3, [r7, #6]
		#else /* portSTACK_GROWTH */
		{
		StackType_t *pxStack;

			/* Allocate space for the stack used by the task being created. */
			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
 80060ac:	88fb      	ldrh	r3, [r7, #6]
 80060ae:	009b      	lsls	r3, r3, #2
 80060b0:	4618      	mov	r0, r3
 80060b2:	f001 fd8b 	bl	8007bcc <pvPortMalloc>
 80060b6:	6178      	str	r0, [r7, #20]

			if( pxStack != NULL )
 80060b8:	697b      	ldr	r3, [r7, #20]
 80060ba:	2b00      	cmp	r3, #0
 80060bc:	d00e      	beq.n	80060dc <xTaskCreate+0x40>
			{
				/* Allocate space for the TCB. */
				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
 80060be:	20a8      	movs	r0, #168	@ 0xa8
 80060c0:	f001 fd84 	bl	8007bcc <pvPortMalloc>
 80060c4:	61f8      	str	r0, [r7, #28]

				if( pxNewTCB != NULL )
 80060c6:	69fb      	ldr	r3, [r7, #28]
 80060c8:	2b00      	cmp	r3, #0
 80060ca:	d003      	beq.n	80060d4 <xTaskCreate+0x38>
				{
					/* Store the stack location in the TCB. */
					pxNewTCB->pxStack = pxStack;
 80060cc:	69fb      	ldr	r3, [r7, #28]
 80060ce:	697a      	ldr	r2, [r7, #20]
 80060d0:	631a      	str	r2, [r3, #48]	@ 0x30
 80060d2:	e005      	b.n	80060e0 <xTaskCreate+0x44>
				}
				else
				{
					/* The stack cannot be used as the TCB was not created.  Free
					it again. */
					vPortFree( pxStack );
 80060d4:	6978      	ldr	r0, [r7, #20]
 80060d6:	f001 fe47 	bl	8007d68 <vPortFree>
 80060da:	e001      	b.n	80060e0 <xTaskCreate+0x44>
				}
			}
			else
			{
				pxNewTCB = NULL;
 80060dc:	2300      	movs	r3, #0
 80060de:	61fb      	str	r3, [r7, #28]
			}
		}
		#endif /* portSTACK_GROWTH */

		if( pxNewTCB != NULL )
 80060e0:	69fb      	ldr	r3, [r7, #28]
 80060e2:	2b00      	cmp	r3, #0
 80060e4:	d017      	beq.n	8006116 <xTaskCreate+0x7a>
		{
			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created dynamically in case it is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
 80060e6:	69fb      	ldr	r3, [r7, #28]
 80060e8:	2200      	movs	r2, #0
 80060ea:	f883 20a5 	strb.w	r2, [r3, #165]	@ 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
 80060ee:	88fa      	ldrh	r2, [r7, #6]
 80060f0:	2300      	movs	r3, #0
 80060f2:	9303      	str	r3, [sp, #12]
 80060f4:	69fb      	ldr	r3, [r7, #28]
 80060f6:	9302      	str	r3, [sp, #8]
 80060f8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80060fa:	9301      	str	r3, [sp, #4]
 80060fc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80060fe:	9300      	str	r3, [sp, #0]
 8006100:	683b      	ldr	r3, [r7, #0]
 8006102:	68b9      	ldr	r1, [r7, #8]
 8006104:	68f8      	ldr	r0, [r7, #12]
 8006106:	f000 f80f 	bl	8006128 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 800610a:	69f8      	ldr	r0, [r7, #28]
 800610c:	f000 f8b4 	bl	8006278 <prvAddNewTaskToReadyList>
			xReturn = pdPASS;
 8006110:	2301      	movs	r3, #1
 8006112:	61bb      	str	r3, [r7, #24]
 8006114:	e002      	b.n	800611c <xTaskCreate+0x80>
		}
		else
		{
			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
 8006116:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 800611a:	61bb      	str	r3, [r7, #24]
		}

		return xReturn;
 800611c:	69bb      	ldr	r3, [r7, #24]
	}
 800611e:	4618      	mov	r0, r3
 8006120:	3720      	adds	r7, #32
 8006122:	46bd      	mov	sp, r7
 8006124:	bd80      	pop	{r7, pc}
	...

08006128 <prvInitialiseNewTask>:
									void * const pvParameters,
									UBaseType_t uxPriority,
									TaskHandle_t * const pxCreatedTask,
									TCB_t *pxNewTCB,
									const MemoryRegion_t * const xRegions )
{
 8006128:	b580      	push	{r7, lr}
 800612a:	b088      	sub	sp, #32
 800612c:	af00      	add	r7, sp, #0
 800612e:	60f8      	str	r0, [r7, #12]
 8006130:	60b9      	str	r1, [r7, #8]
 8006132:	607a      	str	r2, [r7, #4]
 8006134:	603b      	str	r3, [r7, #0]

	/* Avoid dependency on memset() if it is not required. */
	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
	{
		/* Fill the stack with a known value to assist debugging. */
		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
 8006136:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006138:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 800613a:	687b      	ldr	r3, [r7, #4]
 800613c:	009b      	lsls	r3, r3, #2
 800613e:	461a      	mov	r2, r3
 8006140:	21a5      	movs	r1, #165	@ 0xa5
 8006142:	f001 ff31 	bl	8007fa8 <memset>
	grows from high memory to low (as per the 80x86) or vice versa.
	portSTACK_GROWTH is used to make the result positive or negative as required
	by the port. */
	#if( portSTACK_GROWTH < 0 )
	{
		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
 8006146:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006148:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 800614a:	687b      	ldr	r3, [r7, #4]
 800614c:	f103 4380 	add.w	r3, r3, #1073741824	@ 0x40000000
 8006150:	3b01      	subs	r3, #1
 8006152:	009b      	lsls	r3, r3, #2
 8006154:	4413      	add	r3, r2
 8006156:	61bb      	str	r3, [r7, #24]
		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 8006158:	69bb      	ldr	r3, [r7, #24]
 800615a:	f023 0307 	bic.w	r3, r3, #7
 800615e:	61bb      	str	r3, [r7, #24]

		/* Check the alignment of the calculated top of stack is correct. */
		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
 8006160:	69bb      	ldr	r3, [r7, #24]
 8006162:	f003 0307 	and.w	r3, r3, #7
 8006166:	2b00      	cmp	r3, #0
 8006168:	d00b      	beq.n	8006182 <prvInitialiseNewTask+0x5a>
	__asm volatile
 800616a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800616e:	f383 8811 	msr	BASEPRI, r3
 8006172:	f3bf 8f6f 	isb	sy
 8006176:	f3bf 8f4f 	dsb	sy
 800617a:	617b      	str	r3, [r7, #20]
}
 800617c:	bf00      	nop
 800617e:	bf00      	nop
 8006180:	e7fd      	b.n	800617e <prvInitialiseNewTask+0x56>
		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
	}
	#endif /* portSTACK_GROWTH */

	/* Store the task name in the TCB. */
	if( pcName != NULL )
 8006182:	68bb      	ldr	r3, [r7, #8]
 8006184:	2b00      	cmp	r3, #0
 8006186:	d01f      	beq.n	80061c8 <prvInitialiseNewTask+0xa0>
	{
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 8006188:	2300      	movs	r3, #0
 800618a:	61fb      	str	r3, [r7, #28]
 800618c:	e012      	b.n	80061b4 <prvInitialiseNewTask+0x8c>
		{
			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
 800618e:	68ba      	ldr	r2, [r7, #8]
 8006190:	69fb      	ldr	r3, [r7, #28]
 8006192:	4413      	add	r3, r2
 8006194:	7819      	ldrb	r1, [r3, #0]
 8006196:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8006198:	69fb      	ldr	r3, [r7, #28]
 800619a:	4413      	add	r3, r2
 800619c:	3334      	adds	r3, #52	@ 0x34
 800619e:	460a      	mov	r2, r1
 80061a0:	701a      	strb	r2, [r3, #0]

			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
			configMAX_TASK_NAME_LEN characters just in case the memory after the
			string is not accessible (extremely unlikely). */
			if( pcName[ x ] == ( char ) 0x00 )
 80061a2:	68ba      	ldr	r2, [r7, #8]
 80061a4:	69fb      	ldr	r3, [r7, #28]
 80061a6:	4413      	add	r3, r2
 80061a8:	781b      	ldrb	r3, [r3, #0]
 80061aa:	2b00      	cmp	r3, #0
 80061ac:	d006      	beq.n	80061bc <prvInitialiseNewTask+0x94>
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 80061ae:	69fb      	ldr	r3, [r7, #28]
 80061b0:	3301      	adds	r3, #1
 80061b2:	61fb      	str	r3, [r7, #28]
 80061b4:	69fb      	ldr	r3, [r7, #28]
 80061b6:	2b0f      	cmp	r3, #15
 80061b8:	d9e9      	bls.n	800618e <prvInitialiseNewTask+0x66>
 80061ba:	e000      	b.n	80061be <prvInitialiseNewTask+0x96>
			{
				break;
 80061bc:	bf00      	nop
			}
		}

		/* Ensure the name string is terminated in the case that the string length
		was greater or equal to configMAX_TASK_NAME_LEN. */
		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
 80061be:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80061c0:	2200      	movs	r2, #0
 80061c2:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
 80061c6:	e003      	b.n	80061d0 <prvInitialiseNewTask+0xa8>
	}
	else
	{
		/* The task has not been given a name, so just ensure there is a NULL
		terminator when it is read out. */
		pxNewTCB->pcTaskName[ 0 ] = 0x00;
 80061c8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80061ca:	2200      	movs	r2, #0
 80061cc:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
	}

	/* This is used as an array index so must ensure it's not too large.  First
	remove the privilege bit if one is present. */
	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
 80061d0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80061d2:	2b37      	cmp	r3, #55	@ 0x37
 80061d4:	d901      	bls.n	80061da <prvInitialiseNewTask+0xb2>
	{
		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
 80061d6:	2337      	movs	r3, #55	@ 0x37
 80061d8:	62bb      	str	r3, [r7, #40]	@ 0x28
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxNewTCB->uxPriority = uxPriority;
 80061da:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80061dc:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 80061de:	62da      	str	r2, [r3, #44]	@ 0x2c
	#if ( configUSE_MUTEXES == 1 )
	{
		pxNewTCB->uxBasePriority = uxPriority;
 80061e0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80061e2:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 80061e4:	64da      	str	r2, [r3, #76]	@ 0x4c
		pxNewTCB->uxMutexesHeld = 0;
 80061e6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80061e8:	2200      	movs	r2, #0
 80061ea:	651a      	str	r2, [r3, #80]	@ 0x50
	}
	#endif /* configUSE_MUTEXES */

	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
 80061ec:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80061ee:	3304      	adds	r3, #4
 80061f0:	4618      	mov	r0, r3
 80061f2:	f7ff f965 	bl	80054c0 <vListInitialiseItem>
	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
 80061f6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80061f8:	3318      	adds	r3, #24
 80061fa:	4618      	mov	r0, r3
 80061fc:	f7ff f960 	bl	80054c0 <vListInitialiseItem>

	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
	back to	the containing TCB from a generic item in a list. */
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
 8006200:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006202:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8006204:	611a      	str	r2, [r3, #16]

	/* Event lists are always in priority order. */
	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8006206:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006208:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 800620c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800620e:	619a      	str	r2, [r3, #24]
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
 8006210:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006212:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8006214:	625a      	str	r2, [r3, #36]	@ 0x24
	}
	#endif

	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
	{
		pxNewTCB->ulNotifiedValue = 0;
 8006216:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006218:	2200      	movs	r2, #0
 800621a:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 800621e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006220:	2200      	movs	r2, #0
 8006222:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
	#if ( configUSE_NEWLIB_REENTRANT == 1 )
	{
		/* Initialise this task's Newlib reent structure.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
 8006226:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006228:	3354      	adds	r3, #84	@ 0x54
 800622a:	224c      	movs	r2, #76	@ 0x4c
 800622c:	2100      	movs	r1, #0
 800622e:	4618      	mov	r0, r3
 8006230:	f001 feba 	bl	8007fa8 <memset>
 8006234:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006236:	4a0d      	ldr	r2, [pc, #52]	@ (800626c <prvInitialiseNewTask+0x144>)
 8006238:	659a      	str	r2, [r3, #88]	@ 0x58
 800623a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800623c:	4a0c      	ldr	r2, [pc, #48]	@ (8006270 <prvInitialiseNewTask+0x148>)
 800623e:	65da      	str	r2, [r3, #92]	@ 0x5c
 8006240:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006242:	4a0c      	ldr	r2, [pc, #48]	@ (8006274 <prvInitialiseNewTask+0x14c>)
 8006244:	661a      	str	r2, [r3, #96]	@ 0x60
			}
			#endif /* portSTACK_GROWTH */
		}
		#else /* portHAS_STACK_OVERFLOW_CHECKING */
		{
			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
 8006246:	683a      	ldr	r2, [r7, #0]
 8006248:	68f9      	ldr	r1, [r7, #12]
 800624a:	69b8      	ldr	r0, [r7, #24]
 800624c:	f001 fa68 	bl	8007720 <pxPortInitialiseStack>
 8006250:	4602      	mov	r2, r0
 8006252:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006254:	601a      	str	r2, [r3, #0]
		}
		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
	}
	#endif /* portUSING_MPU_WRAPPERS */

	if( pxCreatedTask != NULL )
 8006256:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006258:	2b00      	cmp	r3, #0
 800625a:	d002      	beq.n	8006262 <prvInitialiseNewTask+0x13a>
	{
		/* Pass the handle out in an anonymous way.  The handle can be used to
		change the created task's priority, delete the created task, etc.*/
		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
 800625c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800625e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8006260:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8006262:	bf00      	nop
 8006264:	3720      	adds	r7, #32
 8006266:	46bd      	mov	sp, r7
 8006268:	bd80      	pop	{r7, pc}
 800626a:	bf00      	nop
 800626c:	20008b4c 	.word	0x20008b4c
 8006270:	20008bb4 	.word	0x20008bb4
 8006274:	20008c1c 	.word	0x20008c1c

08006278 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/

static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
 8006278:	b580      	push	{r7, lr}
 800627a:	b082      	sub	sp, #8
 800627c:	af00      	add	r7, sp, #0
 800627e:	6078      	str	r0, [r7, #4]
	/* Ensure interrupts don't access the task lists while the lists are being
	updated. */
	taskENTER_CRITICAL();
 8006280:	f001 fb82 	bl	8007988 <vPortEnterCritical>
	{
		uxCurrentNumberOfTasks++;
 8006284:	4b2d      	ldr	r3, [pc, #180]	@ (800633c <prvAddNewTaskToReadyList+0xc4>)
 8006286:	681b      	ldr	r3, [r3, #0]
 8006288:	3301      	adds	r3, #1
 800628a:	4a2c      	ldr	r2, [pc, #176]	@ (800633c <prvAddNewTaskToReadyList+0xc4>)
 800628c:	6013      	str	r3, [r2, #0]
		if( pxCurrentTCB == NULL )
 800628e:	4b2c      	ldr	r3, [pc, #176]	@ (8006340 <prvAddNewTaskToReadyList+0xc8>)
 8006290:	681b      	ldr	r3, [r3, #0]
 8006292:	2b00      	cmp	r3, #0
 8006294:	d109      	bne.n	80062aa <prvAddNewTaskToReadyList+0x32>
		{
			/* There are no other tasks, or all the other tasks are in
			the suspended state - make this the current task. */
			pxCurrentTCB = pxNewTCB;
 8006296:	4a2a      	ldr	r2, [pc, #168]	@ (8006340 <prvAddNewTaskToReadyList+0xc8>)
 8006298:	687b      	ldr	r3, [r7, #4]
 800629a:	6013      	str	r3, [r2, #0]

			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
 800629c:	4b27      	ldr	r3, [pc, #156]	@ (800633c <prvAddNewTaskToReadyList+0xc4>)
 800629e:	681b      	ldr	r3, [r3, #0]
 80062a0:	2b01      	cmp	r3, #1
 80062a2:	d110      	bne.n	80062c6 <prvAddNewTaskToReadyList+0x4e>
			{
				/* This is the first task to be created so do the preliminary
				initialisation required.  We will not recover if this call
				fails, but we will report the failure. */
				prvInitialiseTaskLists();
 80062a4:	f000 fc2e 	bl	8006b04 <prvInitialiseTaskLists>
 80062a8:	e00d      	b.n	80062c6 <prvAddNewTaskToReadyList+0x4e>
		else
		{
			/* If the scheduler is not already running, make this task the
			current task if it is the highest priority task to be created
			so far. */
			if( xSchedulerRunning == pdFALSE )
 80062aa:	4b26      	ldr	r3, [pc, #152]	@ (8006344 <prvAddNewTaskToReadyList+0xcc>)
 80062ac:	681b      	ldr	r3, [r3, #0]
 80062ae:	2b00      	cmp	r3, #0
 80062b0:	d109      	bne.n	80062c6 <prvAddNewTaskToReadyList+0x4e>
			{
				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
 80062b2:	4b23      	ldr	r3, [pc, #140]	@ (8006340 <prvAddNewTaskToReadyList+0xc8>)
 80062b4:	681b      	ldr	r3, [r3, #0]
 80062b6:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80062b8:	687b      	ldr	r3, [r7, #4]
 80062ba:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80062bc:	429a      	cmp	r2, r3
 80062be:	d802      	bhi.n	80062c6 <prvAddNewTaskToReadyList+0x4e>
				{
					pxCurrentTCB = pxNewTCB;
 80062c0:	4a1f      	ldr	r2, [pc, #124]	@ (8006340 <prvAddNewTaskToReadyList+0xc8>)
 80062c2:	687b      	ldr	r3, [r7, #4]
 80062c4:	6013      	str	r3, [r2, #0]
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}

		uxTaskNumber++;
 80062c6:	4b20      	ldr	r3, [pc, #128]	@ (8006348 <prvAddNewTaskToReadyList+0xd0>)
 80062c8:	681b      	ldr	r3, [r3, #0]
 80062ca:	3301      	adds	r3, #1
 80062cc:	4a1e      	ldr	r2, [pc, #120]	@ (8006348 <prvAddNewTaskToReadyList+0xd0>)
 80062ce:	6013      	str	r3, [r2, #0]

		#if ( configUSE_TRACE_FACILITY == 1 )
		{
			/* Add a counter into the TCB for tracing only. */
			pxNewTCB->uxTCBNumber = uxTaskNumber;
 80062d0:	4b1d      	ldr	r3, [pc, #116]	@ (8006348 <prvAddNewTaskToReadyList+0xd0>)
 80062d2:	681a      	ldr	r2, [r3, #0]
 80062d4:	687b      	ldr	r3, [r7, #4]
 80062d6:	645a      	str	r2, [r3, #68]	@ 0x44
		}
		#endif /* configUSE_TRACE_FACILITY */
		traceTASK_CREATE( pxNewTCB );

		prvAddTaskToReadyList( pxNewTCB );
 80062d8:	687b      	ldr	r3, [r7, #4]
 80062da:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80062dc:	4b1b      	ldr	r3, [pc, #108]	@ (800634c <prvAddNewTaskToReadyList+0xd4>)
 80062de:	681b      	ldr	r3, [r3, #0]
 80062e0:	429a      	cmp	r2, r3
 80062e2:	d903      	bls.n	80062ec <prvAddNewTaskToReadyList+0x74>
 80062e4:	687b      	ldr	r3, [r7, #4]
 80062e6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80062e8:	4a18      	ldr	r2, [pc, #96]	@ (800634c <prvAddNewTaskToReadyList+0xd4>)
 80062ea:	6013      	str	r3, [r2, #0]
 80062ec:	687b      	ldr	r3, [r7, #4]
 80062ee:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80062f0:	4613      	mov	r3, r2
 80062f2:	009b      	lsls	r3, r3, #2
 80062f4:	4413      	add	r3, r2
 80062f6:	009b      	lsls	r3, r3, #2
 80062f8:	4a15      	ldr	r2, [pc, #84]	@ (8006350 <prvAddNewTaskToReadyList+0xd8>)
 80062fa:	441a      	add	r2, r3
 80062fc:	687b      	ldr	r3, [r7, #4]
 80062fe:	3304      	adds	r3, #4
 8006300:	4619      	mov	r1, r3
 8006302:	4610      	mov	r0, r2
 8006304:	f7ff f8e9 	bl	80054da <vListInsertEnd>

		portSETUP_TCB( pxNewTCB );
	}
	taskEXIT_CRITICAL();
 8006308:	f001 fb70 	bl	80079ec <vPortExitCritical>

	if( xSchedulerRunning != pdFALSE )
 800630c:	4b0d      	ldr	r3, [pc, #52]	@ (8006344 <prvAddNewTaskToReadyList+0xcc>)
 800630e:	681b      	ldr	r3, [r3, #0]
 8006310:	2b00      	cmp	r3, #0
 8006312:	d00e      	beq.n	8006332 <prvAddNewTaskToReadyList+0xba>
	{
		/* If the created task is of a higher priority than the current task
		then it should run now. */
		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
 8006314:	4b0a      	ldr	r3, [pc, #40]	@ (8006340 <prvAddNewTaskToReadyList+0xc8>)
 8006316:	681b      	ldr	r3, [r3, #0]
 8006318:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800631a:	687b      	ldr	r3, [r7, #4]
 800631c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800631e:	429a      	cmp	r2, r3
 8006320:	d207      	bcs.n	8006332 <prvAddNewTaskToReadyList+0xba>
		{
			taskYIELD_IF_USING_PREEMPTION();
 8006322:	4b0c      	ldr	r3, [pc, #48]	@ (8006354 <prvAddNewTaskToReadyList+0xdc>)
 8006324:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006328:	601a      	str	r2, [r3, #0]
 800632a:	f3bf 8f4f 	dsb	sy
 800632e:	f3bf 8f6f 	isb	sy
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8006332:	bf00      	nop
 8006334:	3708      	adds	r7, #8
 8006336:	46bd      	mov	sp, r7
 8006338:	bd80      	pop	{r7, pc}
 800633a:	bf00      	nop
 800633c:	2000149c 	.word	0x2000149c
 8006340:	20000fc8 	.word	0x20000fc8
 8006344:	200014a8 	.word	0x200014a8
 8006348:	200014b8 	.word	0x200014b8
 800634c:	200014a4 	.word	0x200014a4
 8006350:	20000fcc 	.word	0x20000fcc
 8006354:	e000ed04 	.word	0xe000ed04

08006358 <vTaskDelay>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelay == 1 )

	void vTaskDelay( const TickType_t xTicksToDelay )
	{
 8006358:	b580      	push	{r7, lr}
 800635a:	b084      	sub	sp, #16
 800635c:	af00      	add	r7, sp, #0
 800635e:	6078      	str	r0, [r7, #4]
	BaseType_t xAlreadyYielded = pdFALSE;
 8006360:	2300      	movs	r3, #0
 8006362:	60fb      	str	r3, [r7, #12]

		/* A delay time of zero just forces a reschedule. */
		if( xTicksToDelay > ( TickType_t ) 0U )
 8006364:	687b      	ldr	r3, [r7, #4]
 8006366:	2b00      	cmp	r3, #0
 8006368:	d018      	beq.n	800639c <vTaskDelay+0x44>
		{
			configASSERT( uxSchedulerSuspended == 0 );
 800636a:	4b14      	ldr	r3, [pc, #80]	@ (80063bc <vTaskDelay+0x64>)
 800636c:	681b      	ldr	r3, [r3, #0]
 800636e:	2b00      	cmp	r3, #0
 8006370:	d00b      	beq.n	800638a <vTaskDelay+0x32>
	__asm volatile
 8006372:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006376:	f383 8811 	msr	BASEPRI, r3
 800637a:	f3bf 8f6f 	isb	sy
 800637e:	f3bf 8f4f 	dsb	sy
 8006382:	60bb      	str	r3, [r7, #8]
}
 8006384:	bf00      	nop
 8006386:	bf00      	nop
 8006388:	e7fd      	b.n	8006386 <vTaskDelay+0x2e>
			vTaskSuspendAll();
 800638a:	f000 f88b 	bl	80064a4 <vTaskSuspendAll>
				list or removed from the blocked list until the scheduler
				is resumed.

				This task cannot be in an event list as it is the currently
				executing task. */
				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
 800638e:	2100      	movs	r1, #0
 8006390:	6878      	ldr	r0, [r7, #4]
 8006392:	f000 fe17 	bl	8006fc4 <prvAddCurrentTaskToDelayedList>
			}
			xAlreadyYielded = xTaskResumeAll();
 8006396:	f000 f893 	bl	80064c0 <xTaskResumeAll>
 800639a:	60f8      	str	r0, [r7, #12]
			mtCOVERAGE_TEST_MARKER();
		}

		/* Force a reschedule if xTaskResumeAll has not already done so, we may
		have put ourselves to sleep. */
		if( xAlreadyYielded == pdFALSE )
 800639c:	68fb      	ldr	r3, [r7, #12]
 800639e:	2b00      	cmp	r3, #0
 80063a0:	d107      	bne.n	80063b2 <vTaskDelay+0x5a>
		{
			portYIELD_WITHIN_API();
 80063a2:	4b07      	ldr	r3, [pc, #28]	@ (80063c0 <vTaskDelay+0x68>)
 80063a4:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80063a8:	601a      	str	r2, [r3, #0]
 80063aa:	f3bf 8f4f 	dsb	sy
 80063ae:	f3bf 8f6f 	isb	sy
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 80063b2:	bf00      	nop
 80063b4:	3710      	adds	r7, #16
 80063b6:	46bd      	mov	sp, r7
 80063b8:	bd80      	pop	{r7, pc}
 80063ba:	bf00      	nop
 80063bc:	200014c4 	.word	0x200014c4
 80063c0:	e000ed04 	.word	0xe000ed04

080063c4 <vTaskStartScheduler>:

#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/

void vTaskStartScheduler( void )
{
 80063c4:	b580      	push	{r7, lr}
 80063c6:	b08a      	sub	sp, #40	@ 0x28
 80063c8:	af04      	add	r7, sp, #16
BaseType_t xReturn;

	/* Add the idle task at the lowest priority. */
	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
	{
		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
 80063ca:	2300      	movs	r3, #0
 80063cc:	60bb      	str	r3, [r7, #8]
		StackType_t *pxIdleTaskStackBuffer = NULL;
 80063ce:	2300      	movs	r3, #0
 80063d0:	607b      	str	r3, [r7, #4]
		uint32_t ulIdleTaskStackSize;

		/* The Idle task is created using user provided RAM - obtain the
		address of the RAM then create the idle task. */
		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
 80063d2:	463a      	mov	r2, r7
 80063d4:	1d39      	adds	r1, r7, #4
 80063d6:	f107 0308 	add.w	r3, r7, #8
 80063da:	4618      	mov	r0, r3
 80063dc:	f7ff f81c 	bl	8005418 <vApplicationGetIdleTaskMemory>
		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
 80063e0:	6839      	ldr	r1, [r7, #0]
 80063e2:	687b      	ldr	r3, [r7, #4]
 80063e4:	68ba      	ldr	r2, [r7, #8]
 80063e6:	9202      	str	r2, [sp, #8]
 80063e8:	9301      	str	r3, [sp, #4]
 80063ea:	2300      	movs	r3, #0
 80063ec:	9300      	str	r3, [sp, #0]
 80063ee:	2300      	movs	r3, #0
 80063f0:	460a      	mov	r2, r1
 80063f2:	4924      	ldr	r1, [pc, #144]	@ (8006484 <vTaskStartScheduler+0xc0>)
 80063f4:	4824      	ldr	r0, [pc, #144]	@ (8006488 <vTaskStartScheduler+0xc4>)
 80063f6:	f7ff fdf1 	bl	8005fdc <xTaskCreateStatic>
 80063fa:	4603      	mov	r3, r0
 80063fc:	4a23      	ldr	r2, [pc, #140]	@ (800648c <vTaskStartScheduler+0xc8>)
 80063fe:	6013      	str	r3, [r2, #0]
												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
												pxIdleTaskStackBuffer,
												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */

		if( xIdleTaskHandle != NULL )
 8006400:	4b22      	ldr	r3, [pc, #136]	@ (800648c <vTaskStartScheduler+0xc8>)
 8006402:	681b      	ldr	r3, [r3, #0]
 8006404:	2b00      	cmp	r3, #0
 8006406:	d002      	beq.n	800640e <vTaskStartScheduler+0x4a>
		{
			xReturn = pdPASS;
 8006408:	2301      	movs	r3, #1
 800640a:	617b      	str	r3, [r7, #20]
 800640c:	e001      	b.n	8006412 <vTaskStartScheduler+0x4e>
		}
		else
		{
			xReturn = pdFAIL;
 800640e:	2300      	movs	r3, #0
 8006410:	617b      	str	r3, [r7, #20]
	}
	#endif /* configSUPPORT_STATIC_ALLOCATION */

	#if ( configUSE_TIMERS == 1 )
	{
		if( xReturn == pdPASS )
 8006412:	697b      	ldr	r3, [r7, #20]
 8006414:	2b01      	cmp	r3, #1
 8006416:	d102      	bne.n	800641e <vTaskStartScheduler+0x5a>
		{
			xReturn = xTimerCreateTimerTask();
 8006418:	f000 fe28 	bl	800706c <xTimerCreateTimerTask>
 800641c:	6178      	str	r0, [r7, #20]
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif /* configUSE_TIMERS */

	if( xReturn == pdPASS )
 800641e:	697b      	ldr	r3, [r7, #20]
 8006420:	2b01      	cmp	r3, #1
 8006422:	d11b      	bne.n	800645c <vTaskStartScheduler+0x98>
	__asm volatile
 8006424:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006428:	f383 8811 	msr	BASEPRI, r3
 800642c:	f3bf 8f6f 	isb	sy
 8006430:	f3bf 8f4f 	dsb	sy
 8006434:	613b      	str	r3, [r7, #16]
}
 8006436:	bf00      	nop
		{
			/* Switch Newlib's _impure_ptr variable to point to the _reent
			structure specific to the task that will run first.
			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 8006438:	4b15      	ldr	r3, [pc, #84]	@ (8006490 <vTaskStartScheduler+0xcc>)
 800643a:	681b      	ldr	r3, [r3, #0]
 800643c:	3354      	adds	r3, #84	@ 0x54
 800643e:	4a15      	ldr	r2, [pc, #84]	@ (8006494 <vTaskStartScheduler+0xd0>)
 8006440:	6013      	str	r3, [r2, #0]
		}
		#endif /* configUSE_NEWLIB_REENTRANT */

		xNextTaskUnblockTime = portMAX_DELAY;
 8006442:	4b15      	ldr	r3, [pc, #84]	@ (8006498 <vTaskStartScheduler+0xd4>)
 8006444:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8006448:	601a      	str	r2, [r3, #0]
		xSchedulerRunning = pdTRUE;
 800644a:	4b14      	ldr	r3, [pc, #80]	@ (800649c <vTaskStartScheduler+0xd8>)
 800644c:	2201      	movs	r2, #1
 800644e:	601a      	str	r2, [r3, #0]
		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
 8006450:	4b13      	ldr	r3, [pc, #76]	@ (80064a0 <vTaskStartScheduler+0xdc>)
 8006452:	2200      	movs	r2, #0
 8006454:	601a      	str	r2, [r3, #0]

		traceTASK_SWITCHED_IN();

		/* Setting up the timer tick is hardware specific and thus in the
		portable interface. */
		if( xPortStartScheduler() != pdFALSE )
 8006456:	f001 f9f3 	bl	8007840 <xPortStartScheduler>
	}

	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
	meaning xIdleTaskHandle is not used anywhere else. */
	( void ) xIdleTaskHandle;
}
 800645a:	e00f      	b.n	800647c <vTaskStartScheduler+0xb8>
		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
 800645c:	697b      	ldr	r3, [r7, #20]
 800645e:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006462:	d10b      	bne.n	800647c <vTaskStartScheduler+0xb8>
	__asm volatile
 8006464:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006468:	f383 8811 	msr	BASEPRI, r3
 800646c:	f3bf 8f6f 	isb	sy
 8006470:	f3bf 8f4f 	dsb	sy
 8006474:	60fb      	str	r3, [r7, #12]
}
 8006476:	bf00      	nop
 8006478:	bf00      	nop
 800647a:	e7fd      	b.n	8006478 <vTaskStartScheduler+0xb4>
}
 800647c:	bf00      	nop
 800647e:	3718      	adds	r7, #24
 8006480:	46bd      	mov	sp, r7
 8006482:	bd80      	pop	{r7, pc}
 8006484:	080081e8 	.word	0x080081e8
 8006488:	08006ad5 	.word	0x08006ad5
 800648c:	200014c0 	.word	0x200014c0
 8006490:	20000fc8 	.word	0x20000fc8
 8006494:	20000014 	.word	0x20000014
 8006498:	200014bc 	.word	0x200014bc
 800649c:	200014a8 	.word	0x200014a8
 80064a0:	200014a0 	.word	0x200014a0

080064a4 <vTaskSuspendAll>:
	vPortEndScheduler();
}
/*----------------------------------------------------------*/

void vTaskSuspendAll( void )
{
 80064a4:	b480      	push	{r7}
 80064a6:	af00      	add	r7, sp, #0
	do not otherwise exhibit real time behaviour. */
	portSOFTWARE_BARRIER();

	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
	is used to allow calls to vTaskSuspendAll() to nest. */
	++uxSchedulerSuspended;
 80064a8:	4b04      	ldr	r3, [pc, #16]	@ (80064bc <vTaskSuspendAll+0x18>)
 80064aa:	681b      	ldr	r3, [r3, #0]
 80064ac:	3301      	adds	r3, #1
 80064ae:	4a03      	ldr	r2, [pc, #12]	@ (80064bc <vTaskSuspendAll+0x18>)
 80064b0:	6013      	str	r3, [r2, #0]

	/* Enforces ordering for ports and optimised compilers that may otherwise place
	the above increment elsewhere. */
	portMEMORY_BARRIER();
}
 80064b2:	bf00      	nop
 80064b4:	46bd      	mov	sp, r7
 80064b6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80064ba:	4770      	bx	lr
 80064bc:	200014c4 	.word	0x200014c4

080064c0 <xTaskResumeAll>:

#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/

BaseType_t xTaskResumeAll( void )
{
 80064c0:	b580      	push	{r7, lr}
 80064c2:	b084      	sub	sp, #16
 80064c4:	af00      	add	r7, sp, #0
TCB_t *pxTCB = NULL;
 80064c6:	2300      	movs	r3, #0
 80064c8:	60fb      	str	r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
 80064ca:	2300      	movs	r3, #0
 80064cc:	60bb      	str	r3, [r7, #8]

	/* If uxSchedulerSuspended is zero then this function does not match a
	previous call to vTaskSuspendAll(). */
	configASSERT( uxSchedulerSuspended );
 80064ce:	4b42      	ldr	r3, [pc, #264]	@ (80065d8 <xTaskResumeAll+0x118>)
 80064d0:	681b      	ldr	r3, [r3, #0]
 80064d2:	2b00      	cmp	r3, #0
 80064d4:	d10b      	bne.n	80064ee <xTaskResumeAll+0x2e>
	__asm volatile
 80064d6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80064da:	f383 8811 	msr	BASEPRI, r3
 80064de:	f3bf 8f6f 	isb	sy
 80064e2:	f3bf 8f4f 	dsb	sy
 80064e6:	603b      	str	r3, [r7, #0]
}
 80064e8:	bf00      	nop
 80064ea:	bf00      	nop
 80064ec:	e7fd      	b.n	80064ea <xTaskResumeAll+0x2a>
	/* It is possible that an ISR caused a task to be removed from an event
	list while the scheduler was suspended.  If this was the case then the
	removed task will have been added to the xPendingReadyList.  Once the
	scheduler has been resumed it is safe to move all the pending ready
	tasks from this list into their appropriate ready list. */
	taskENTER_CRITICAL();
 80064ee:	f001 fa4b 	bl	8007988 <vPortEnterCritical>
	{
		--uxSchedulerSuspended;
 80064f2:	4b39      	ldr	r3, [pc, #228]	@ (80065d8 <xTaskResumeAll+0x118>)
 80064f4:	681b      	ldr	r3, [r3, #0]
 80064f6:	3b01      	subs	r3, #1
 80064f8:	4a37      	ldr	r2, [pc, #220]	@ (80065d8 <xTaskResumeAll+0x118>)
 80064fa:	6013      	str	r3, [r2, #0]

		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 80064fc:	4b36      	ldr	r3, [pc, #216]	@ (80065d8 <xTaskResumeAll+0x118>)
 80064fe:	681b      	ldr	r3, [r3, #0]
 8006500:	2b00      	cmp	r3, #0
 8006502:	d162      	bne.n	80065ca <xTaskResumeAll+0x10a>
		{
			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
 8006504:	4b35      	ldr	r3, [pc, #212]	@ (80065dc <xTaskResumeAll+0x11c>)
 8006506:	681b      	ldr	r3, [r3, #0]
 8006508:	2b00      	cmp	r3, #0
 800650a:	d05e      	beq.n	80065ca <xTaskResumeAll+0x10a>
			{
				/* Move any readied tasks from the pending list into the
				appropriate ready list. */
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 800650c:	e02f      	b.n	800656e <xTaskResumeAll+0xae>
				{
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 800650e:	4b34      	ldr	r3, [pc, #208]	@ (80065e0 <xTaskResumeAll+0x120>)
 8006510:	68db      	ldr	r3, [r3, #12]
 8006512:	68db      	ldr	r3, [r3, #12]
 8006514:	60fb      	str	r3, [r7, #12]
					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 8006516:	68fb      	ldr	r3, [r7, #12]
 8006518:	3318      	adds	r3, #24
 800651a:	4618      	mov	r0, r3
 800651c:	f7ff f83a 	bl	8005594 <uxListRemove>
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8006520:	68fb      	ldr	r3, [r7, #12]
 8006522:	3304      	adds	r3, #4
 8006524:	4618      	mov	r0, r3
 8006526:	f7ff f835 	bl	8005594 <uxListRemove>
					prvAddTaskToReadyList( pxTCB );
 800652a:	68fb      	ldr	r3, [r7, #12]
 800652c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800652e:	4b2d      	ldr	r3, [pc, #180]	@ (80065e4 <xTaskResumeAll+0x124>)
 8006530:	681b      	ldr	r3, [r3, #0]
 8006532:	429a      	cmp	r2, r3
 8006534:	d903      	bls.n	800653e <xTaskResumeAll+0x7e>
 8006536:	68fb      	ldr	r3, [r7, #12]
 8006538:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800653a:	4a2a      	ldr	r2, [pc, #168]	@ (80065e4 <xTaskResumeAll+0x124>)
 800653c:	6013      	str	r3, [r2, #0]
 800653e:	68fb      	ldr	r3, [r7, #12]
 8006540:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006542:	4613      	mov	r3, r2
 8006544:	009b      	lsls	r3, r3, #2
 8006546:	4413      	add	r3, r2
 8006548:	009b      	lsls	r3, r3, #2
 800654a:	4a27      	ldr	r2, [pc, #156]	@ (80065e8 <xTaskResumeAll+0x128>)
 800654c:	441a      	add	r2, r3
 800654e:	68fb      	ldr	r3, [r7, #12]
 8006550:	3304      	adds	r3, #4
 8006552:	4619      	mov	r1, r3
 8006554:	4610      	mov	r0, r2
 8006556:	f7fe ffc0 	bl	80054da <vListInsertEnd>

					/* If the moved task has a priority higher than the current
					task then a yield must be performed. */
					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 800655a:	68fb      	ldr	r3, [r7, #12]
 800655c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800655e:	4b23      	ldr	r3, [pc, #140]	@ (80065ec <xTaskResumeAll+0x12c>)
 8006560:	681b      	ldr	r3, [r3, #0]
 8006562:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8006564:	429a      	cmp	r2, r3
 8006566:	d302      	bcc.n	800656e <xTaskResumeAll+0xae>
					{
						xYieldPending = pdTRUE;
 8006568:	4b21      	ldr	r3, [pc, #132]	@ (80065f0 <xTaskResumeAll+0x130>)
 800656a:	2201      	movs	r2, #1
 800656c:	601a      	str	r2, [r3, #0]
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 800656e:	4b1c      	ldr	r3, [pc, #112]	@ (80065e0 <xTaskResumeAll+0x120>)
 8006570:	681b      	ldr	r3, [r3, #0]
 8006572:	2b00      	cmp	r3, #0
 8006574:	d1cb      	bne.n	800650e <xTaskResumeAll+0x4e>
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( pxTCB != NULL )
 8006576:	68fb      	ldr	r3, [r7, #12]
 8006578:	2b00      	cmp	r3, #0
 800657a:	d001      	beq.n	8006580 <xTaskResumeAll+0xc0>
					which may have prevented the next unblock time from being
					re-calculated, in which case re-calculate it now.  Mainly
					important for low power tickless implementations, where
					this can prevent an unnecessary exit from low power
					state. */
					prvResetNextTaskUnblockTime();
 800657c:	f000 fb66 	bl	8006c4c <prvResetNextTaskUnblockTime>
				/* If any ticks occurred while the scheduler was suspended then
				they should be processed now.  This ensures the tick count does
				not	slip, and that any delayed tasks are resumed at the correct
				time. */
				{
					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
 8006580:	4b1c      	ldr	r3, [pc, #112]	@ (80065f4 <xTaskResumeAll+0x134>)
 8006582:	681b      	ldr	r3, [r3, #0]
 8006584:	607b      	str	r3, [r7, #4]

					if( xPendedCounts > ( TickType_t ) 0U )
 8006586:	687b      	ldr	r3, [r7, #4]
 8006588:	2b00      	cmp	r3, #0
 800658a:	d010      	beq.n	80065ae <xTaskResumeAll+0xee>
					{
						do
						{
							if( xTaskIncrementTick() != pdFALSE )
 800658c:	f000 f846 	bl	800661c <xTaskIncrementTick>
 8006590:	4603      	mov	r3, r0
 8006592:	2b00      	cmp	r3, #0
 8006594:	d002      	beq.n	800659c <xTaskResumeAll+0xdc>
							{
								xYieldPending = pdTRUE;
 8006596:	4b16      	ldr	r3, [pc, #88]	@ (80065f0 <xTaskResumeAll+0x130>)
 8006598:	2201      	movs	r2, #1
 800659a:	601a      	str	r2, [r3, #0]
							}
							else
							{
								mtCOVERAGE_TEST_MARKER();
							}
							--xPendedCounts;
 800659c:	687b      	ldr	r3, [r7, #4]
 800659e:	3b01      	subs	r3, #1
 80065a0:	607b      	str	r3, [r7, #4]
						} while( xPendedCounts > ( TickType_t ) 0U );
 80065a2:	687b      	ldr	r3, [r7, #4]
 80065a4:	2b00      	cmp	r3, #0
 80065a6:	d1f1      	bne.n	800658c <xTaskResumeAll+0xcc>

						xPendedTicks = 0;
 80065a8:	4b12      	ldr	r3, [pc, #72]	@ (80065f4 <xTaskResumeAll+0x134>)
 80065aa:	2200      	movs	r2, #0
 80065ac:	601a      	str	r2, [r3, #0]
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( xYieldPending != pdFALSE )
 80065ae:	4b10      	ldr	r3, [pc, #64]	@ (80065f0 <xTaskResumeAll+0x130>)
 80065b0:	681b      	ldr	r3, [r3, #0]
 80065b2:	2b00      	cmp	r3, #0
 80065b4:	d009      	beq.n	80065ca <xTaskResumeAll+0x10a>
				{
					#if( configUSE_PREEMPTION != 0 )
					{
						xAlreadyYielded = pdTRUE;
 80065b6:	2301      	movs	r3, #1
 80065b8:	60bb      	str	r3, [r7, #8]
					}
					#endif
					taskYIELD_IF_USING_PREEMPTION();
 80065ba:	4b0f      	ldr	r3, [pc, #60]	@ (80065f8 <xTaskResumeAll+0x138>)
 80065bc:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80065c0:	601a      	str	r2, [r3, #0]
 80065c2:	f3bf 8f4f 	dsb	sy
 80065c6:	f3bf 8f6f 	isb	sy
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 80065ca:	f001 fa0f 	bl	80079ec <vPortExitCritical>

	return xAlreadyYielded;
 80065ce:	68bb      	ldr	r3, [r7, #8]
}
 80065d0:	4618      	mov	r0, r3
 80065d2:	3710      	adds	r7, #16
 80065d4:	46bd      	mov	sp, r7
 80065d6:	bd80      	pop	{r7, pc}
 80065d8:	200014c4 	.word	0x200014c4
 80065dc:	2000149c 	.word	0x2000149c
 80065e0:	2000145c 	.word	0x2000145c
 80065e4:	200014a4 	.word	0x200014a4
 80065e8:	20000fcc 	.word	0x20000fcc
 80065ec:	20000fc8 	.word	0x20000fc8
 80065f0:	200014b0 	.word	0x200014b0
 80065f4:	200014ac 	.word	0x200014ac
 80065f8:	e000ed04 	.word	0xe000ed04

080065fc <xTaskGetTickCount>:
/*-----------------------------------------------------------*/

TickType_t xTaskGetTickCount( void )
{
 80065fc:	b480      	push	{r7}
 80065fe:	b083      	sub	sp, #12
 8006600:	af00      	add	r7, sp, #0
TickType_t xTicks;

	/* Critical section required if running on a 16 bit processor. */
	portTICK_TYPE_ENTER_CRITICAL();
	{
		xTicks = xTickCount;
 8006602:	4b05      	ldr	r3, [pc, #20]	@ (8006618 <xTaskGetTickCount+0x1c>)
 8006604:	681b      	ldr	r3, [r3, #0]
 8006606:	607b      	str	r3, [r7, #4]
	}
	portTICK_TYPE_EXIT_CRITICAL();

	return xTicks;
 8006608:	687b      	ldr	r3, [r7, #4]
}
 800660a:	4618      	mov	r0, r3
 800660c:	370c      	adds	r7, #12
 800660e:	46bd      	mov	sp, r7
 8006610:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006614:	4770      	bx	lr
 8006616:	bf00      	nop
 8006618:	200014a0 	.word	0x200014a0

0800661c <xTaskIncrementTick>:

#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/

BaseType_t xTaskIncrementTick( void )
{
 800661c:	b580      	push	{r7, lr}
 800661e:	b086      	sub	sp, #24
 8006620:	af00      	add	r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
 8006622:	2300      	movs	r3, #0
 8006624:	617b      	str	r3, [r7, #20]

	/* Called by the portable layer each time a tick interrupt occurs.
	Increments the tick then checks to see if the new tick value will cause any
	tasks to be unblocked. */
	traceTASK_INCREMENT_TICK( xTickCount );
	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8006626:	4b4f      	ldr	r3, [pc, #316]	@ (8006764 <xTaskIncrementTick+0x148>)
 8006628:	681b      	ldr	r3, [r3, #0]
 800662a:	2b00      	cmp	r3, #0
 800662c:	f040 8090 	bne.w	8006750 <xTaskIncrementTick+0x134>
	{
		/* Minor optimisation.  The tick count cannot change in this
		block. */
		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
 8006630:	4b4d      	ldr	r3, [pc, #308]	@ (8006768 <xTaskIncrementTick+0x14c>)
 8006632:	681b      	ldr	r3, [r3, #0]
 8006634:	3301      	adds	r3, #1
 8006636:	613b      	str	r3, [r7, #16]

		/* Increment the RTOS tick, switching the delayed and overflowed
		delayed lists if it wraps to 0. */
		xTickCount = xConstTickCount;
 8006638:	4a4b      	ldr	r2, [pc, #300]	@ (8006768 <xTaskIncrementTick+0x14c>)
 800663a:	693b      	ldr	r3, [r7, #16]
 800663c:	6013      	str	r3, [r2, #0]

		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
 800663e:	693b      	ldr	r3, [r7, #16]
 8006640:	2b00      	cmp	r3, #0
 8006642:	d121      	bne.n	8006688 <xTaskIncrementTick+0x6c>
		{
			taskSWITCH_DELAYED_LISTS();
 8006644:	4b49      	ldr	r3, [pc, #292]	@ (800676c <xTaskIncrementTick+0x150>)
 8006646:	681b      	ldr	r3, [r3, #0]
 8006648:	681b      	ldr	r3, [r3, #0]
 800664a:	2b00      	cmp	r3, #0
 800664c:	d00b      	beq.n	8006666 <xTaskIncrementTick+0x4a>
	__asm volatile
 800664e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006652:	f383 8811 	msr	BASEPRI, r3
 8006656:	f3bf 8f6f 	isb	sy
 800665a:	f3bf 8f4f 	dsb	sy
 800665e:	603b      	str	r3, [r7, #0]
}
 8006660:	bf00      	nop
 8006662:	bf00      	nop
 8006664:	e7fd      	b.n	8006662 <xTaskIncrementTick+0x46>
 8006666:	4b41      	ldr	r3, [pc, #260]	@ (800676c <xTaskIncrementTick+0x150>)
 8006668:	681b      	ldr	r3, [r3, #0]
 800666a:	60fb      	str	r3, [r7, #12]
 800666c:	4b40      	ldr	r3, [pc, #256]	@ (8006770 <xTaskIncrementTick+0x154>)
 800666e:	681b      	ldr	r3, [r3, #0]
 8006670:	4a3e      	ldr	r2, [pc, #248]	@ (800676c <xTaskIncrementTick+0x150>)
 8006672:	6013      	str	r3, [r2, #0]
 8006674:	4a3e      	ldr	r2, [pc, #248]	@ (8006770 <xTaskIncrementTick+0x154>)
 8006676:	68fb      	ldr	r3, [r7, #12]
 8006678:	6013      	str	r3, [r2, #0]
 800667a:	4b3e      	ldr	r3, [pc, #248]	@ (8006774 <xTaskIncrementTick+0x158>)
 800667c:	681b      	ldr	r3, [r3, #0]
 800667e:	3301      	adds	r3, #1
 8006680:	4a3c      	ldr	r2, [pc, #240]	@ (8006774 <xTaskIncrementTick+0x158>)
 8006682:	6013      	str	r3, [r2, #0]
 8006684:	f000 fae2 	bl	8006c4c <prvResetNextTaskUnblockTime>

		/* See if this tick has made a timeout expire.  Tasks are stored in
		the	queue in the order of their wake time - meaning once one task
		has been found whose block time has not expired there is no need to
		look any further down the list. */
		if( xConstTickCount >= xNextTaskUnblockTime )
 8006688:	4b3b      	ldr	r3, [pc, #236]	@ (8006778 <xTaskIncrementTick+0x15c>)
 800668a:	681b      	ldr	r3, [r3, #0]
 800668c:	693a      	ldr	r2, [r7, #16]
 800668e:	429a      	cmp	r2, r3
 8006690:	d349      	bcc.n	8006726 <xTaskIncrementTick+0x10a>
		{
			for( ;; )
			{
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8006692:	4b36      	ldr	r3, [pc, #216]	@ (800676c <xTaskIncrementTick+0x150>)
 8006694:	681b      	ldr	r3, [r3, #0]
 8006696:	681b      	ldr	r3, [r3, #0]
 8006698:	2b00      	cmp	r3, #0
 800669a:	d104      	bne.n	80066a6 <xTaskIncrementTick+0x8a>
					/* The delayed list is empty.  Set xNextTaskUnblockTime
					to the maximum possible value so it is extremely
					unlikely that the
					if( xTickCount >= xNextTaskUnblockTime ) test will pass
					next time through. */
					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 800669c:	4b36      	ldr	r3, [pc, #216]	@ (8006778 <xTaskIncrementTick+0x15c>)
 800669e:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 80066a2:	601a      	str	r2, [r3, #0]
					break;
 80066a4:	e03f      	b.n	8006726 <xTaskIncrementTick+0x10a>
				{
					/* The delayed list is not empty, get the value of the
					item at the head of the delayed list.  This is the time
					at which the task at the head of the delayed list must
					be removed from the Blocked state. */
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80066a6:	4b31      	ldr	r3, [pc, #196]	@ (800676c <xTaskIncrementTick+0x150>)
 80066a8:	681b      	ldr	r3, [r3, #0]
 80066aa:	68db      	ldr	r3, [r3, #12]
 80066ac:	68db      	ldr	r3, [r3, #12]
 80066ae:	60bb      	str	r3, [r7, #8]
					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 80066b0:	68bb      	ldr	r3, [r7, #8]
 80066b2:	685b      	ldr	r3, [r3, #4]
 80066b4:	607b      	str	r3, [r7, #4]

					if( xConstTickCount < xItemValue )
 80066b6:	693a      	ldr	r2, [r7, #16]
 80066b8:	687b      	ldr	r3, [r7, #4]
 80066ba:	429a      	cmp	r2, r3
 80066bc:	d203      	bcs.n	80066c6 <xTaskIncrementTick+0xaa>
						/* It is not time to unblock this item yet, but the
						item value is the time at which the task at the head
						of the blocked list must be removed from the Blocked
						state -	so record the item value in
						xNextTaskUnblockTime. */
						xNextTaskUnblockTime = xItemValue;
 80066be:	4a2e      	ldr	r2, [pc, #184]	@ (8006778 <xTaskIncrementTick+0x15c>)
 80066c0:	687b      	ldr	r3, [r7, #4]
 80066c2:	6013      	str	r3, [r2, #0]
						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
 80066c4:	e02f      	b.n	8006726 <xTaskIncrementTick+0x10a>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* It is time to remove the item from the Blocked state. */
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 80066c6:	68bb      	ldr	r3, [r7, #8]
 80066c8:	3304      	adds	r3, #4
 80066ca:	4618      	mov	r0, r3
 80066cc:	f7fe ff62 	bl	8005594 <uxListRemove>

					/* Is the task waiting on an event also?  If so remove
					it from the event list. */
					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
 80066d0:	68bb      	ldr	r3, [r7, #8]
 80066d2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 80066d4:	2b00      	cmp	r3, #0
 80066d6:	d004      	beq.n	80066e2 <xTaskIncrementTick+0xc6>
					{
						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 80066d8:	68bb      	ldr	r3, [r7, #8]
 80066da:	3318      	adds	r3, #24
 80066dc:	4618      	mov	r0, r3
 80066de:	f7fe ff59 	bl	8005594 <uxListRemove>
						mtCOVERAGE_TEST_MARKER();
					}

					/* Place the unblocked task into the appropriate ready
					list. */
					prvAddTaskToReadyList( pxTCB );
 80066e2:	68bb      	ldr	r3, [r7, #8]
 80066e4:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80066e6:	4b25      	ldr	r3, [pc, #148]	@ (800677c <xTaskIncrementTick+0x160>)
 80066e8:	681b      	ldr	r3, [r3, #0]
 80066ea:	429a      	cmp	r2, r3
 80066ec:	d903      	bls.n	80066f6 <xTaskIncrementTick+0xda>
 80066ee:	68bb      	ldr	r3, [r7, #8]
 80066f0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80066f2:	4a22      	ldr	r2, [pc, #136]	@ (800677c <xTaskIncrementTick+0x160>)
 80066f4:	6013      	str	r3, [r2, #0]
 80066f6:	68bb      	ldr	r3, [r7, #8]
 80066f8:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80066fa:	4613      	mov	r3, r2
 80066fc:	009b      	lsls	r3, r3, #2
 80066fe:	4413      	add	r3, r2
 8006700:	009b      	lsls	r3, r3, #2
 8006702:	4a1f      	ldr	r2, [pc, #124]	@ (8006780 <xTaskIncrementTick+0x164>)
 8006704:	441a      	add	r2, r3
 8006706:	68bb      	ldr	r3, [r7, #8]
 8006708:	3304      	adds	r3, #4
 800670a:	4619      	mov	r1, r3
 800670c:	4610      	mov	r0, r2
 800670e:	f7fe fee4 	bl	80054da <vListInsertEnd>
					{
						/* Preemption is on, but a context switch should
						only be performed if the unblocked task has a
						priority that is equal to or higher than the
						currently executing task. */
						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 8006712:	68bb      	ldr	r3, [r7, #8]
 8006714:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006716:	4b1b      	ldr	r3, [pc, #108]	@ (8006784 <xTaskIncrementTick+0x168>)
 8006718:	681b      	ldr	r3, [r3, #0]
 800671a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800671c:	429a      	cmp	r2, r3
 800671e:	d3b8      	bcc.n	8006692 <xTaskIncrementTick+0x76>
						{
							xSwitchRequired = pdTRUE;
 8006720:	2301      	movs	r3, #1
 8006722:	617b      	str	r3, [r7, #20]
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8006724:	e7b5      	b.n	8006692 <xTaskIncrementTick+0x76>
		/* Tasks of equal priority to the currently running task will share
		processing time (time slice) if preemption is on, and the application
		writer has not explicitly turned time slicing off. */
		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
		{
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
 8006726:	4b17      	ldr	r3, [pc, #92]	@ (8006784 <xTaskIncrementTick+0x168>)
 8006728:	681b      	ldr	r3, [r3, #0]
 800672a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800672c:	4914      	ldr	r1, [pc, #80]	@ (8006780 <xTaskIncrementTick+0x164>)
 800672e:	4613      	mov	r3, r2
 8006730:	009b      	lsls	r3, r3, #2
 8006732:	4413      	add	r3, r2
 8006734:	009b      	lsls	r3, r3, #2
 8006736:	440b      	add	r3, r1
 8006738:	681b      	ldr	r3, [r3, #0]
 800673a:	2b01      	cmp	r3, #1
 800673c:	d901      	bls.n	8006742 <xTaskIncrementTick+0x126>
			{
				xSwitchRequired = pdTRUE;
 800673e:	2301      	movs	r3, #1
 8006740:	617b      	str	r3, [r7, #20]
		}
		#endif /* configUSE_TICK_HOOK */

		#if ( configUSE_PREEMPTION == 1 )
		{
			if( xYieldPending != pdFALSE )
 8006742:	4b11      	ldr	r3, [pc, #68]	@ (8006788 <xTaskIncrementTick+0x16c>)
 8006744:	681b      	ldr	r3, [r3, #0]
 8006746:	2b00      	cmp	r3, #0
 8006748:	d007      	beq.n	800675a <xTaskIncrementTick+0x13e>
			{
				xSwitchRequired = pdTRUE;
 800674a:	2301      	movs	r3, #1
 800674c:	617b      	str	r3, [r7, #20]
 800674e:	e004      	b.n	800675a <xTaskIncrementTick+0x13e>
		}
		#endif /* configUSE_PREEMPTION */
	}
	else
	{
		++xPendedTicks;
 8006750:	4b0e      	ldr	r3, [pc, #56]	@ (800678c <xTaskIncrementTick+0x170>)
 8006752:	681b      	ldr	r3, [r3, #0]
 8006754:	3301      	adds	r3, #1
 8006756:	4a0d      	ldr	r2, [pc, #52]	@ (800678c <xTaskIncrementTick+0x170>)
 8006758:	6013      	str	r3, [r2, #0]
			vApplicationTickHook();
		}
		#endif
	}

	return xSwitchRequired;
 800675a:	697b      	ldr	r3, [r7, #20]
}
 800675c:	4618      	mov	r0, r3
 800675e:	3718      	adds	r7, #24
 8006760:	46bd      	mov	sp, r7
 8006762:	bd80      	pop	{r7, pc}
 8006764:	200014c4 	.word	0x200014c4
 8006768:	200014a0 	.word	0x200014a0
 800676c:	20001454 	.word	0x20001454
 8006770:	20001458 	.word	0x20001458
 8006774:	200014b4 	.word	0x200014b4
 8006778:	200014bc 	.word	0x200014bc
 800677c:	200014a4 	.word	0x200014a4
 8006780:	20000fcc 	.word	0x20000fcc
 8006784:	20000fc8 	.word	0x20000fc8
 8006788:	200014b0 	.word	0x200014b0
 800678c:	200014ac 	.word	0x200014ac

08006790 <vTaskSwitchContext>:

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

void vTaskSwitchContext( void )
{
 8006790:	b480      	push	{r7}
 8006792:	b085      	sub	sp, #20
 8006794:	af00      	add	r7, sp, #0
	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
 8006796:	4b2b      	ldr	r3, [pc, #172]	@ (8006844 <vTaskSwitchContext+0xb4>)
 8006798:	681b      	ldr	r3, [r3, #0]
 800679a:	2b00      	cmp	r3, #0
 800679c:	d003      	beq.n	80067a6 <vTaskSwitchContext+0x16>
	{
		/* The scheduler is currently suspended - do not allow a context
		switch. */
		xYieldPending = pdTRUE;
 800679e:	4b2a      	ldr	r3, [pc, #168]	@ (8006848 <vTaskSwitchContext+0xb8>)
 80067a0:	2201      	movs	r2, #1
 80067a2:	601a      	str	r2, [r3, #0]
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
		}
		#endif /* configUSE_NEWLIB_REENTRANT */
	}
}
 80067a4:	e047      	b.n	8006836 <vTaskSwitchContext+0xa6>
		xYieldPending = pdFALSE;
 80067a6:	4b28      	ldr	r3, [pc, #160]	@ (8006848 <vTaskSwitchContext+0xb8>)
 80067a8:	2200      	movs	r2, #0
 80067aa:	601a      	str	r2, [r3, #0]
		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80067ac:	4b27      	ldr	r3, [pc, #156]	@ (800684c <vTaskSwitchContext+0xbc>)
 80067ae:	681b      	ldr	r3, [r3, #0]
 80067b0:	60fb      	str	r3, [r7, #12]
 80067b2:	e011      	b.n	80067d8 <vTaskSwitchContext+0x48>
 80067b4:	68fb      	ldr	r3, [r7, #12]
 80067b6:	2b00      	cmp	r3, #0
 80067b8:	d10b      	bne.n	80067d2 <vTaskSwitchContext+0x42>
	__asm volatile
 80067ba:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80067be:	f383 8811 	msr	BASEPRI, r3
 80067c2:	f3bf 8f6f 	isb	sy
 80067c6:	f3bf 8f4f 	dsb	sy
 80067ca:	607b      	str	r3, [r7, #4]
}
 80067cc:	bf00      	nop
 80067ce:	bf00      	nop
 80067d0:	e7fd      	b.n	80067ce <vTaskSwitchContext+0x3e>
 80067d2:	68fb      	ldr	r3, [r7, #12]
 80067d4:	3b01      	subs	r3, #1
 80067d6:	60fb      	str	r3, [r7, #12]
 80067d8:	491d      	ldr	r1, [pc, #116]	@ (8006850 <vTaskSwitchContext+0xc0>)
 80067da:	68fa      	ldr	r2, [r7, #12]
 80067dc:	4613      	mov	r3, r2
 80067de:	009b      	lsls	r3, r3, #2
 80067e0:	4413      	add	r3, r2
 80067e2:	009b      	lsls	r3, r3, #2
 80067e4:	440b      	add	r3, r1
 80067e6:	681b      	ldr	r3, [r3, #0]
 80067e8:	2b00      	cmp	r3, #0
 80067ea:	d0e3      	beq.n	80067b4 <vTaskSwitchContext+0x24>
 80067ec:	68fa      	ldr	r2, [r7, #12]
 80067ee:	4613      	mov	r3, r2
 80067f0:	009b      	lsls	r3, r3, #2
 80067f2:	4413      	add	r3, r2
 80067f4:	009b      	lsls	r3, r3, #2
 80067f6:	4a16      	ldr	r2, [pc, #88]	@ (8006850 <vTaskSwitchContext+0xc0>)
 80067f8:	4413      	add	r3, r2
 80067fa:	60bb      	str	r3, [r7, #8]
 80067fc:	68bb      	ldr	r3, [r7, #8]
 80067fe:	685b      	ldr	r3, [r3, #4]
 8006800:	685a      	ldr	r2, [r3, #4]
 8006802:	68bb      	ldr	r3, [r7, #8]
 8006804:	605a      	str	r2, [r3, #4]
 8006806:	68bb      	ldr	r3, [r7, #8]
 8006808:	685a      	ldr	r2, [r3, #4]
 800680a:	68bb      	ldr	r3, [r7, #8]
 800680c:	3308      	adds	r3, #8
 800680e:	429a      	cmp	r2, r3
 8006810:	d104      	bne.n	800681c <vTaskSwitchContext+0x8c>
 8006812:	68bb      	ldr	r3, [r7, #8]
 8006814:	685b      	ldr	r3, [r3, #4]
 8006816:	685a      	ldr	r2, [r3, #4]
 8006818:	68bb      	ldr	r3, [r7, #8]
 800681a:	605a      	str	r2, [r3, #4]
 800681c:	68bb      	ldr	r3, [r7, #8]
 800681e:	685b      	ldr	r3, [r3, #4]
 8006820:	68db      	ldr	r3, [r3, #12]
 8006822:	4a0c      	ldr	r2, [pc, #48]	@ (8006854 <vTaskSwitchContext+0xc4>)
 8006824:	6013      	str	r3, [r2, #0]
 8006826:	4a09      	ldr	r2, [pc, #36]	@ (800684c <vTaskSwitchContext+0xbc>)
 8006828:	68fb      	ldr	r3, [r7, #12]
 800682a:	6013      	str	r3, [r2, #0]
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 800682c:	4b09      	ldr	r3, [pc, #36]	@ (8006854 <vTaskSwitchContext+0xc4>)
 800682e:	681b      	ldr	r3, [r3, #0]
 8006830:	3354      	adds	r3, #84	@ 0x54
 8006832:	4a09      	ldr	r2, [pc, #36]	@ (8006858 <vTaskSwitchContext+0xc8>)
 8006834:	6013      	str	r3, [r2, #0]
}
 8006836:	bf00      	nop
 8006838:	3714      	adds	r7, #20
 800683a:	46bd      	mov	sp, r7
 800683c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006840:	4770      	bx	lr
 8006842:	bf00      	nop
 8006844:	200014c4 	.word	0x200014c4
 8006848:	200014b0 	.word	0x200014b0
 800684c:	200014a4 	.word	0x200014a4
 8006850:	20000fcc 	.word	0x20000fcc
 8006854:	20000fc8 	.word	0x20000fc8
 8006858:	20000014 	.word	0x20000014

0800685c <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/

void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
 800685c:	b580      	push	{r7, lr}
 800685e:	b084      	sub	sp, #16
 8006860:	af00      	add	r7, sp, #0
 8006862:	6078      	str	r0, [r7, #4]
 8006864:	6039      	str	r1, [r7, #0]
	configASSERT( pxEventList );
 8006866:	687b      	ldr	r3, [r7, #4]
 8006868:	2b00      	cmp	r3, #0
 800686a:	d10b      	bne.n	8006884 <vTaskPlaceOnEventList+0x28>
	__asm volatile
 800686c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006870:	f383 8811 	msr	BASEPRI, r3
 8006874:	f3bf 8f6f 	isb	sy
 8006878:	f3bf 8f4f 	dsb	sy
 800687c:	60fb      	str	r3, [r7, #12]
}
 800687e:	bf00      	nop
 8006880:	bf00      	nop
 8006882:	e7fd      	b.n	8006880 <vTaskPlaceOnEventList+0x24>

	/* Place the event list item of the TCB in the appropriate event list.
	This is placed in the list in priority order so the highest priority task
	is the first to be woken by the event.  The queue that contains the event
	list is locked, preventing simultaneous access from interrupts. */
	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8006884:	4b07      	ldr	r3, [pc, #28]	@ (80068a4 <vTaskPlaceOnEventList+0x48>)
 8006886:	681b      	ldr	r3, [r3, #0]
 8006888:	3318      	adds	r3, #24
 800688a:	4619      	mov	r1, r3
 800688c:	6878      	ldr	r0, [r7, #4]
 800688e:	f7fe fe48 	bl	8005522 <vListInsert>

	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 8006892:	2101      	movs	r1, #1
 8006894:	6838      	ldr	r0, [r7, #0]
 8006896:	f000 fb95 	bl	8006fc4 <prvAddCurrentTaskToDelayedList>
}
 800689a:	bf00      	nop
 800689c:	3710      	adds	r7, #16
 800689e:	46bd      	mov	sp, r7
 80068a0:	bd80      	pop	{r7, pc}
 80068a2:	bf00      	nop
 80068a4:	20000fc8 	.word	0x20000fc8

080068a8 <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/

#if( configUSE_TIMERS == 1 )

	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 80068a8:	b580      	push	{r7, lr}
 80068aa:	b086      	sub	sp, #24
 80068ac:	af00      	add	r7, sp, #0
 80068ae:	60f8      	str	r0, [r7, #12]
 80068b0:	60b9      	str	r1, [r7, #8]
 80068b2:	607a      	str	r2, [r7, #4]
		configASSERT( pxEventList );
 80068b4:	68fb      	ldr	r3, [r7, #12]
 80068b6:	2b00      	cmp	r3, #0
 80068b8:	d10b      	bne.n	80068d2 <vTaskPlaceOnEventListRestricted+0x2a>
	__asm volatile
 80068ba:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80068be:	f383 8811 	msr	BASEPRI, r3
 80068c2:	f3bf 8f6f 	isb	sy
 80068c6:	f3bf 8f4f 	dsb	sy
 80068ca:	617b      	str	r3, [r7, #20]
}
 80068cc:	bf00      	nop
 80068ce:	bf00      	nop
 80068d0:	e7fd      	b.n	80068ce <vTaskPlaceOnEventListRestricted+0x26>

		/* Place the event list item of the TCB in the appropriate event list.
		In this case it is assume that this is the only task that is going to
		be waiting on this event list, so the faster vListInsertEnd() function
		can be used in place of vListInsert. */
		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 80068d2:	4b0a      	ldr	r3, [pc, #40]	@ (80068fc <vTaskPlaceOnEventListRestricted+0x54>)
 80068d4:	681b      	ldr	r3, [r3, #0]
 80068d6:	3318      	adds	r3, #24
 80068d8:	4619      	mov	r1, r3
 80068da:	68f8      	ldr	r0, [r7, #12]
 80068dc:	f7fe fdfd 	bl	80054da <vListInsertEnd>

		/* If the task should block indefinitely then set the block time to a
		value that will be recognised as an indefinite delay inside the
		prvAddCurrentTaskToDelayedList() function. */
		if( xWaitIndefinitely != pdFALSE )
 80068e0:	687b      	ldr	r3, [r7, #4]
 80068e2:	2b00      	cmp	r3, #0
 80068e4:	d002      	beq.n	80068ec <vTaskPlaceOnEventListRestricted+0x44>
		{
			xTicksToWait = portMAX_DELAY;
 80068e6:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80068ea:	60bb      	str	r3, [r7, #8]
		}

		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
 80068ec:	6879      	ldr	r1, [r7, #4]
 80068ee:	68b8      	ldr	r0, [r7, #8]
 80068f0:	f000 fb68 	bl	8006fc4 <prvAddCurrentTaskToDelayedList>
	}
 80068f4:	bf00      	nop
 80068f6:	3718      	adds	r7, #24
 80068f8:	46bd      	mov	sp, r7
 80068fa:	bd80      	pop	{r7, pc}
 80068fc:	20000fc8 	.word	0x20000fc8

08006900 <xTaskRemoveFromEventList>:

#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/

BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
 8006900:	b580      	push	{r7, lr}
 8006902:	b086      	sub	sp, #24
 8006904:	af00      	add	r7, sp, #0
 8006906:	6078      	str	r0, [r7, #4]
	get called - the lock count on the queue will get modified instead.  This
	means exclusive access to the event list is guaranteed here.

	This function assumes that a check has already been made to ensure that
	pxEventList is not empty. */
	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8006908:	687b      	ldr	r3, [r7, #4]
 800690a:	68db      	ldr	r3, [r3, #12]
 800690c:	68db      	ldr	r3, [r3, #12]
 800690e:	613b      	str	r3, [r7, #16]
	configASSERT( pxUnblockedTCB );
 8006910:	693b      	ldr	r3, [r7, #16]
 8006912:	2b00      	cmp	r3, #0
 8006914:	d10b      	bne.n	800692e <xTaskRemoveFromEventList+0x2e>
	__asm volatile
 8006916:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800691a:	f383 8811 	msr	BASEPRI, r3
 800691e:	f3bf 8f6f 	isb	sy
 8006922:	f3bf 8f4f 	dsb	sy
 8006926:	60fb      	str	r3, [r7, #12]
}
 8006928:	bf00      	nop
 800692a:	bf00      	nop
 800692c:	e7fd      	b.n	800692a <xTaskRemoveFromEventList+0x2a>
	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
 800692e:	693b      	ldr	r3, [r7, #16]
 8006930:	3318      	adds	r3, #24
 8006932:	4618      	mov	r0, r3
 8006934:	f7fe fe2e 	bl	8005594 <uxListRemove>

	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8006938:	4b1d      	ldr	r3, [pc, #116]	@ (80069b0 <xTaskRemoveFromEventList+0xb0>)
 800693a:	681b      	ldr	r3, [r3, #0]
 800693c:	2b00      	cmp	r3, #0
 800693e:	d11d      	bne.n	800697c <xTaskRemoveFromEventList+0x7c>
	{
		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
 8006940:	693b      	ldr	r3, [r7, #16]
 8006942:	3304      	adds	r3, #4
 8006944:	4618      	mov	r0, r3
 8006946:	f7fe fe25 	bl	8005594 <uxListRemove>
		prvAddTaskToReadyList( pxUnblockedTCB );
 800694a:	693b      	ldr	r3, [r7, #16]
 800694c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800694e:	4b19      	ldr	r3, [pc, #100]	@ (80069b4 <xTaskRemoveFromEventList+0xb4>)
 8006950:	681b      	ldr	r3, [r3, #0]
 8006952:	429a      	cmp	r2, r3
 8006954:	d903      	bls.n	800695e <xTaskRemoveFromEventList+0x5e>
 8006956:	693b      	ldr	r3, [r7, #16]
 8006958:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800695a:	4a16      	ldr	r2, [pc, #88]	@ (80069b4 <xTaskRemoveFromEventList+0xb4>)
 800695c:	6013      	str	r3, [r2, #0]
 800695e:	693b      	ldr	r3, [r7, #16]
 8006960:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006962:	4613      	mov	r3, r2
 8006964:	009b      	lsls	r3, r3, #2
 8006966:	4413      	add	r3, r2
 8006968:	009b      	lsls	r3, r3, #2
 800696a:	4a13      	ldr	r2, [pc, #76]	@ (80069b8 <xTaskRemoveFromEventList+0xb8>)
 800696c:	441a      	add	r2, r3
 800696e:	693b      	ldr	r3, [r7, #16]
 8006970:	3304      	adds	r3, #4
 8006972:	4619      	mov	r1, r3
 8006974:	4610      	mov	r0, r2
 8006976:	f7fe fdb0 	bl	80054da <vListInsertEnd>
 800697a:	e005      	b.n	8006988 <xTaskRemoveFromEventList+0x88>
	}
	else
	{
		/* The delayed and ready lists cannot be accessed, so hold this task
		pending until the scheduler is resumed. */
		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
 800697c:	693b      	ldr	r3, [r7, #16]
 800697e:	3318      	adds	r3, #24
 8006980:	4619      	mov	r1, r3
 8006982:	480e      	ldr	r0, [pc, #56]	@ (80069bc <xTaskRemoveFromEventList+0xbc>)
 8006984:	f7fe fda9 	bl	80054da <vListInsertEnd>
	}

	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
 8006988:	693b      	ldr	r3, [r7, #16]
 800698a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800698c:	4b0c      	ldr	r3, [pc, #48]	@ (80069c0 <xTaskRemoveFromEventList+0xc0>)
 800698e:	681b      	ldr	r3, [r3, #0]
 8006990:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8006992:	429a      	cmp	r2, r3
 8006994:	d905      	bls.n	80069a2 <xTaskRemoveFromEventList+0xa2>
	{
		/* Return true if the task removed from the event list has a higher
		priority than the calling task.  This allows the calling task to know if
		it should force a context switch now. */
		xReturn = pdTRUE;
 8006996:	2301      	movs	r3, #1
 8006998:	617b      	str	r3, [r7, #20]

		/* Mark that a yield is pending in case the user is not using the
		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
		xYieldPending = pdTRUE;
 800699a:	4b0a      	ldr	r3, [pc, #40]	@ (80069c4 <xTaskRemoveFromEventList+0xc4>)
 800699c:	2201      	movs	r2, #1
 800699e:	601a      	str	r2, [r3, #0]
 80069a0:	e001      	b.n	80069a6 <xTaskRemoveFromEventList+0xa6>
	}
	else
	{
		xReturn = pdFALSE;
 80069a2:	2300      	movs	r3, #0
 80069a4:	617b      	str	r3, [r7, #20]
	}

	return xReturn;
 80069a6:	697b      	ldr	r3, [r7, #20]
}
 80069a8:	4618      	mov	r0, r3
 80069aa:	3718      	adds	r7, #24
 80069ac:	46bd      	mov	sp, r7
 80069ae:	bd80      	pop	{r7, pc}
 80069b0:	200014c4 	.word	0x200014c4
 80069b4:	200014a4 	.word	0x200014a4
 80069b8:	20000fcc 	.word	0x20000fcc
 80069bc:	2000145c 	.word	0x2000145c
 80069c0:	20000fc8 	.word	0x20000fc8
 80069c4:	200014b0 	.word	0x200014b0

080069c8 <vTaskInternalSetTimeOutState>:
	taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/

void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
 80069c8:	b480      	push	{r7}
 80069ca:	b083      	sub	sp, #12
 80069cc:	af00      	add	r7, sp, #0
 80069ce:	6078      	str	r0, [r7, #4]
	/* For internal use only as it does not use a critical section. */
	pxTimeOut->xOverflowCount = xNumOfOverflows;
 80069d0:	4b06      	ldr	r3, [pc, #24]	@ (80069ec <vTaskInternalSetTimeOutState+0x24>)
 80069d2:	681a      	ldr	r2, [r3, #0]
 80069d4:	687b      	ldr	r3, [r7, #4]
 80069d6:	601a      	str	r2, [r3, #0]
	pxTimeOut->xTimeOnEntering = xTickCount;
 80069d8:	4b05      	ldr	r3, [pc, #20]	@ (80069f0 <vTaskInternalSetTimeOutState+0x28>)
 80069da:	681a      	ldr	r2, [r3, #0]
 80069dc:	687b      	ldr	r3, [r7, #4]
 80069de:	605a      	str	r2, [r3, #4]
}
 80069e0:	bf00      	nop
 80069e2:	370c      	adds	r7, #12
 80069e4:	46bd      	mov	sp, r7
 80069e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80069ea:	4770      	bx	lr
 80069ec:	200014b4 	.word	0x200014b4
 80069f0:	200014a0 	.word	0x200014a0

080069f4 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/

BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
 80069f4:	b580      	push	{r7, lr}
 80069f6:	b088      	sub	sp, #32
 80069f8:	af00      	add	r7, sp, #0
 80069fa:	6078      	str	r0, [r7, #4]
 80069fc:	6039      	str	r1, [r7, #0]
BaseType_t xReturn;

	configASSERT( pxTimeOut );
 80069fe:	687b      	ldr	r3, [r7, #4]
 8006a00:	2b00      	cmp	r3, #0
 8006a02:	d10b      	bne.n	8006a1c <xTaskCheckForTimeOut+0x28>
	__asm volatile
 8006a04:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006a08:	f383 8811 	msr	BASEPRI, r3
 8006a0c:	f3bf 8f6f 	isb	sy
 8006a10:	f3bf 8f4f 	dsb	sy
 8006a14:	613b      	str	r3, [r7, #16]
}
 8006a16:	bf00      	nop
 8006a18:	bf00      	nop
 8006a1a:	e7fd      	b.n	8006a18 <xTaskCheckForTimeOut+0x24>
	configASSERT( pxTicksToWait );
 8006a1c:	683b      	ldr	r3, [r7, #0]
 8006a1e:	2b00      	cmp	r3, #0
 8006a20:	d10b      	bne.n	8006a3a <xTaskCheckForTimeOut+0x46>
	__asm volatile
 8006a22:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006a26:	f383 8811 	msr	BASEPRI, r3
 8006a2a:	f3bf 8f6f 	isb	sy
 8006a2e:	f3bf 8f4f 	dsb	sy
 8006a32:	60fb      	str	r3, [r7, #12]
}
 8006a34:	bf00      	nop
 8006a36:	bf00      	nop
 8006a38:	e7fd      	b.n	8006a36 <xTaskCheckForTimeOut+0x42>

	taskENTER_CRITICAL();
 8006a3a:	f000 ffa5 	bl	8007988 <vPortEnterCritical>
	{
		/* Minor optimisation.  The tick count cannot change in this block. */
		const TickType_t xConstTickCount = xTickCount;
 8006a3e:	4b1d      	ldr	r3, [pc, #116]	@ (8006ab4 <xTaskCheckForTimeOut+0xc0>)
 8006a40:	681b      	ldr	r3, [r3, #0]
 8006a42:	61bb      	str	r3, [r7, #24]
		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
 8006a44:	687b      	ldr	r3, [r7, #4]
 8006a46:	685b      	ldr	r3, [r3, #4]
 8006a48:	69ba      	ldr	r2, [r7, #24]
 8006a4a:	1ad3      	subs	r3, r2, r3
 8006a4c:	617b      	str	r3, [r7, #20]
			}
			else
		#endif

		#if ( INCLUDE_vTaskSuspend == 1 )
			if( *pxTicksToWait == portMAX_DELAY )
 8006a4e:	683b      	ldr	r3, [r7, #0]
 8006a50:	681b      	ldr	r3, [r3, #0]
 8006a52:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006a56:	d102      	bne.n	8006a5e <xTaskCheckForTimeOut+0x6a>
			{
				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
				specified is the maximum block time then the task should block
				indefinitely, and therefore never time out. */
				xReturn = pdFALSE;
 8006a58:	2300      	movs	r3, #0
 8006a5a:	61fb      	str	r3, [r7, #28]
 8006a5c:	e023      	b.n	8006aa6 <xTaskCheckForTimeOut+0xb2>
			}
			else
		#endif

		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
 8006a5e:	687b      	ldr	r3, [r7, #4]
 8006a60:	681a      	ldr	r2, [r3, #0]
 8006a62:	4b15      	ldr	r3, [pc, #84]	@ (8006ab8 <xTaskCheckForTimeOut+0xc4>)
 8006a64:	681b      	ldr	r3, [r3, #0]
 8006a66:	429a      	cmp	r2, r3
 8006a68:	d007      	beq.n	8006a7a <xTaskCheckForTimeOut+0x86>
 8006a6a:	687b      	ldr	r3, [r7, #4]
 8006a6c:	685b      	ldr	r3, [r3, #4]
 8006a6e:	69ba      	ldr	r2, [r7, #24]
 8006a70:	429a      	cmp	r2, r3
 8006a72:	d302      	bcc.n	8006a7a <xTaskCheckForTimeOut+0x86>
			/* The tick count is greater than the time at which
			vTaskSetTimeout() was called, but has also overflowed since
			vTaskSetTimeOut() was called.  It must have wrapped all the way
			around and gone past again. This passed since vTaskSetTimeout()
			was called. */
			xReturn = pdTRUE;
 8006a74:	2301      	movs	r3, #1
 8006a76:	61fb      	str	r3, [r7, #28]
 8006a78:	e015      	b.n	8006aa6 <xTaskCheckForTimeOut+0xb2>
		}
		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
 8006a7a:	683b      	ldr	r3, [r7, #0]
 8006a7c:	681b      	ldr	r3, [r3, #0]
 8006a7e:	697a      	ldr	r2, [r7, #20]
 8006a80:	429a      	cmp	r2, r3
 8006a82:	d20b      	bcs.n	8006a9c <xTaskCheckForTimeOut+0xa8>
		{
			/* Not a genuine timeout. Adjust parameters for time remaining. */
			*pxTicksToWait -= xElapsedTime;
 8006a84:	683b      	ldr	r3, [r7, #0]
 8006a86:	681a      	ldr	r2, [r3, #0]
 8006a88:	697b      	ldr	r3, [r7, #20]
 8006a8a:	1ad2      	subs	r2, r2, r3
 8006a8c:	683b      	ldr	r3, [r7, #0]
 8006a8e:	601a      	str	r2, [r3, #0]
			vTaskInternalSetTimeOutState( pxTimeOut );
 8006a90:	6878      	ldr	r0, [r7, #4]
 8006a92:	f7ff ff99 	bl	80069c8 <vTaskInternalSetTimeOutState>
			xReturn = pdFALSE;
 8006a96:	2300      	movs	r3, #0
 8006a98:	61fb      	str	r3, [r7, #28]
 8006a9a:	e004      	b.n	8006aa6 <xTaskCheckForTimeOut+0xb2>
		}
		else
		{
			*pxTicksToWait = 0;
 8006a9c:	683b      	ldr	r3, [r7, #0]
 8006a9e:	2200      	movs	r2, #0
 8006aa0:	601a      	str	r2, [r3, #0]
			xReturn = pdTRUE;
 8006aa2:	2301      	movs	r3, #1
 8006aa4:	61fb      	str	r3, [r7, #28]
		}
	}
	taskEXIT_CRITICAL();
 8006aa6:	f000 ffa1 	bl	80079ec <vPortExitCritical>

	return xReturn;
 8006aaa:	69fb      	ldr	r3, [r7, #28]
}
 8006aac:	4618      	mov	r0, r3
 8006aae:	3720      	adds	r7, #32
 8006ab0:	46bd      	mov	sp, r7
 8006ab2:	bd80      	pop	{r7, pc}
 8006ab4:	200014a0 	.word	0x200014a0
 8006ab8:	200014b4 	.word	0x200014b4

08006abc <vTaskMissedYield>:
/*-----------------------------------------------------------*/

void vTaskMissedYield( void )
{
 8006abc:	b480      	push	{r7}
 8006abe:	af00      	add	r7, sp, #0
	xYieldPending = pdTRUE;
 8006ac0:	4b03      	ldr	r3, [pc, #12]	@ (8006ad0 <vTaskMissedYield+0x14>)
 8006ac2:	2201      	movs	r2, #1
 8006ac4:	601a      	str	r2, [r3, #0]
}
 8006ac6:	bf00      	nop
 8006ac8:	46bd      	mov	sp, r7
 8006aca:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006ace:	4770      	bx	lr
 8006ad0:	200014b0 	.word	0x200014b0

08006ad4 <prvIdleTask>:
 *
 * void prvIdleTask( void *pvParameters );
 *
 */
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
 8006ad4:	b580      	push	{r7, lr}
 8006ad6:	b082      	sub	sp, #8
 8006ad8:	af00      	add	r7, sp, #0
 8006ada:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* See if any tasks have deleted themselves - if so then the idle task
		is responsible for freeing the deleted task's TCB and stack. */
		prvCheckTasksWaitingTermination();
 8006adc:	f000 f852 	bl	8006b84 <prvCheckTasksWaitingTermination>

			A critical region is not required here as we are just reading from
			the list, and an occasional incorrect value will not matter.  If
			the ready list at the idle priority contains more than one task
			then a task other than the idle task is ready to execute. */
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
 8006ae0:	4b06      	ldr	r3, [pc, #24]	@ (8006afc <prvIdleTask+0x28>)
 8006ae2:	681b      	ldr	r3, [r3, #0]
 8006ae4:	2b01      	cmp	r3, #1
 8006ae6:	d9f9      	bls.n	8006adc <prvIdleTask+0x8>
			{
				taskYIELD();
 8006ae8:	4b05      	ldr	r3, [pc, #20]	@ (8006b00 <prvIdleTask+0x2c>)
 8006aea:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006aee:	601a      	str	r2, [r3, #0]
 8006af0:	f3bf 8f4f 	dsb	sy
 8006af4:	f3bf 8f6f 	isb	sy
		prvCheckTasksWaitingTermination();
 8006af8:	e7f0      	b.n	8006adc <prvIdleTask+0x8>
 8006afa:	bf00      	nop
 8006afc:	20000fcc 	.word	0x20000fcc
 8006b00:	e000ed04 	.word	0xe000ed04

08006b04 <prvInitialiseTaskLists>:

#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

static void prvInitialiseTaskLists( void )
{
 8006b04:	b580      	push	{r7, lr}
 8006b06:	b082      	sub	sp, #8
 8006b08:	af00      	add	r7, sp, #0
UBaseType_t uxPriority;

	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8006b0a:	2300      	movs	r3, #0
 8006b0c:	607b      	str	r3, [r7, #4]
 8006b0e:	e00c      	b.n	8006b2a <prvInitialiseTaskLists+0x26>
	{
		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
 8006b10:	687a      	ldr	r2, [r7, #4]
 8006b12:	4613      	mov	r3, r2
 8006b14:	009b      	lsls	r3, r3, #2
 8006b16:	4413      	add	r3, r2
 8006b18:	009b      	lsls	r3, r3, #2
 8006b1a:	4a12      	ldr	r2, [pc, #72]	@ (8006b64 <prvInitialiseTaskLists+0x60>)
 8006b1c:	4413      	add	r3, r2
 8006b1e:	4618      	mov	r0, r3
 8006b20:	f7fe fcae 	bl	8005480 <vListInitialise>
	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8006b24:	687b      	ldr	r3, [r7, #4]
 8006b26:	3301      	adds	r3, #1
 8006b28:	607b      	str	r3, [r7, #4]
 8006b2a:	687b      	ldr	r3, [r7, #4]
 8006b2c:	2b37      	cmp	r3, #55	@ 0x37
 8006b2e:	d9ef      	bls.n	8006b10 <prvInitialiseTaskLists+0xc>
	}

	vListInitialise( &xDelayedTaskList1 );
 8006b30:	480d      	ldr	r0, [pc, #52]	@ (8006b68 <prvInitialiseTaskLists+0x64>)
 8006b32:	f7fe fca5 	bl	8005480 <vListInitialise>
	vListInitialise( &xDelayedTaskList2 );
 8006b36:	480d      	ldr	r0, [pc, #52]	@ (8006b6c <prvInitialiseTaskLists+0x68>)
 8006b38:	f7fe fca2 	bl	8005480 <vListInitialise>
	vListInitialise( &xPendingReadyList );
 8006b3c:	480c      	ldr	r0, [pc, #48]	@ (8006b70 <prvInitialiseTaskLists+0x6c>)
 8006b3e:	f7fe fc9f 	bl	8005480 <vListInitialise>

	#if ( INCLUDE_vTaskDelete == 1 )
	{
		vListInitialise( &xTasksWaitingTermination );
 8006b42:	480c      	ldr	r0, [pc, #48]	@ (8006b74 <prvInitialiseTaskLists+0x70>)
 8006b44:	f7fe fc9c 	bl	8005480 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskDelete */

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		vListInitialise( &xSuspendedTaskList );
 8006b48:	480b      	ldr	r0, [pc, #44]	@ (8006b78 <prvInitialiseTaskLists+0x74>)
 8006b4a:	f7fe fc99 	bl	8005480 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskSuspend */

	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
	using list2. */
	pxDelayedTaskList = &xDelayedTaskList1;
 8006b4e:	4b0b      	ldr	r3, [pc, #44]	@ (8006b7c <prvInitialiseTaskLists+0x78>)
 8006b50:	4a05      	ldr	r2, [pc, #20]	@ (8006b68 <prvInitialiseTaskLists+0x64>)
 8006b52:	601a      	str	r2, [r3, #0]
	pxOverflowDelayedTaskList = &xDelayedTaskList2;
 8006b54:	4b0a      	ldr	r3, [pc, #40]	@ (8006b80 <prvInitialiseTaskLists+0x7c>)
 8006b56:	4a05      	ldr	r2, [pc, #20]	@ (8006b6c <prvInitialiseTaskLists+0x68>)
 8006b58:	601a      	str	r2, [r3, #0]
}
 8006b5a:	bf00      	nop
 8006b5c:	3708      	adds	r7, #8
 8006b5e:	46bd      	mov	sp, r7
 8006b60:	bd80      	pop	{r7, pc}
 8006b62:	bf00      	nop
 8006b64:	20000fcc 	.word	0x20000fcc
 8006b68:	2000142c 	.word	0x2000142c
 8006b6c:	20001440 	.word	0x20001440
 8006b70:	2000145c 	.word	0x2000145c
 8006b74:	20001470 	.word	0x20001470
 8006b78:	20001488 	.word	0x20001488
 8006b7c:	20001454 	.word	0x20001454
 8006b80:	20001458 	.word	0x20001458

08006b84 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/

static void prvCheckTasksWaitingTermination( void )
{
 8006b84:	b580      	push	{r7, lr}
 8006b86:	b082      	sub	sp, #8
 8006b88:	af00      	add	r7, sp, #0
	{
		TCB_t *pxTCB;

		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
		being called too often in the idle task. */
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8006b8a:	e019      	b.n	8006bc0 <prvCheckTasksWaitingTermination+0x3c>
		{
			taskENTER_CRITICAL();
 8006b8c:	f000 fefc 	bl	8007988 <vPortEnterCritical>
			{
				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8006b90:	4b10      	ldr	r3, [pc, #64]	@ (8006bd4 <prvCheckTasksWaitingTermination+0x50>)
 8006b92:	68db      	ldr	r3, [r3, #12]
 8006b94:	68db      	ldr	r3, [r3, #12]
 8006b96:	607b      	str	r3, [r7, #4]
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8006b98:	687b      	ldr	r3, [r7, #4]
 8006b9a:	3304      	adds	r3, #4
 8006b9c:	4618      	mov	r0, r3
 8006b9e:	f7fe fcf9 	bl	8005594 <uxListRemove>
				--uxCurrentNumberOfTasks;
 8006ba2:	4b0d      	ldr	r3, [pc, #52]	@ (8006bd8 <prvCheckTasksWaitingTermination+0x54>)
 8006ba4:	681b      	ldr	r3, [r3, #0]
 8006ba6:	3b01      	subs	r3, #1
 8006ba8:	4a0b      	ldr	r2, [pc, #44]	@ (8006bd8 <prvCheckTasksWaitingTermination+0x54>)
 8006baa:	6013      	str	r3, [r2, #0]
				--uxDeletedTasksWaitingCleanUp;
 8006bac:	4b0b      	ldr	r3, [pc, #44]	@ (8006bdc <prvCheckTasksWaitingTermination+0x58>)
 8006bae:	681b      	ldr	r3, [r3, #0]
 8006bb0:	3b01      	subs	r3, #1
 8006bb2:	4a0a      	ldr	r2, [pc, #40]	@ (8006bdc <prvCheckTasksWaitingTermination+0x58>)
 8006bb4:	6013      	str	r3, [r2, #0]
			}
			taskEXIT_CRITICAL();
 8006bb6:	f000 ff19 	bl	80079ec <vPortExitCritical>

			prvDeleteTCB( pxTCB );
 8006bba:	6878      	ldr	r0, [r7, #4]
 8006bbc:	f000 f810 	bl	8006be0 <prvDeleteTCB>
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8006bc0:	4b06      	ldr	r3, [pc, #24]	@ (8006bdc <prvCheckTasksWaitingTermination+0x58>)
 8006bc2:	681b      	ldr	r3, [r3, #0]
 8006bc4:	2b00      	cmp	r3, #0
 8006bc6:	d1e1      	bne.n	8006b8c <prvCheckTasksWaitingTermination+0x8>
		}
	}
	#endif /* INCLUDE_vTaskDelete */
}
 8006bc8:	bf00      	nop
 8006bca:	bf00      	nop
 8006bcc:	3708      	adds	r7, #8
 8006bce:	46bd      	mov	sp, r7
 8006bd0:	bd80      	pop	{r7, pc}
 8006bd2:	bf00      	nop
 8006bd4:	20001470 	.word	0x20001470
 8006bd8:	2000149c 	.word	0x2000149c
 8006bdc:	20001484 	.word	0x20001484

08006be0 <prvDeleteTCB>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelete == 1 )

	static void prvDeleteTCB( TCB_t *pxTCB )
	{
 8006be0:	b580      	push	{r7, lr}
 8006be2:	b084      	sub	sp, #16
 8006be4:	af00      	add	r7, sp, #0
 8006be6:	6078      	str	r0, [r7, #4]
		to the task to free any memory allocated at the application level.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		#if ( configUSE_NEWLIB_REENTRANT == 1 )
		{
			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
 8006be8:	687b      	ldr	r3, [r7, #4]
 8006bea:	3354      	adds	r3, #84	@ 0x54
 8006bec:	4618      	mov	r0, r3
 8006bee:	f001 f9e3 	bl	8007fb8 <_reclaim_reent>
		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
		{
			/* The task could have been allocated statically or dynamically, so
			check what was statically allocated before trying to free the
			memory. */
			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
 8006bf2:	687b      	ldr	r3, [r7, #4]
 8006bf4:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8006bf8:	2b00      	cmp	r3, #0
 8006bfa:	d108      	bne.n	8006c0e <prvDeleteTCB+0x2e>
			{
				/* Both the stack and TCB were allocated dynamically, so both
				must be freed. */
				vPortFree( pxTCB->pxStack );
 8006bfc:	687b      	ldr	r3, [r7, #4]
 8006bfe:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8006c00:	4618      	mov	r0, r3
 8006c02:	f001 f8b1 	bl	8007d68 <vPortFree>
				vPortFree( pxTCB );
 8006c06:	6878      	ldr	r0, [r7, #4]
 8006c08:	f001 f8ae 	bl	8007d68 <vPortFree>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
	}
 8006c0c:	e019      	b.n	8006c42 <prvDeleteTCB+0x62>
			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
 8006c0e:	687b      	ldr	r3, [r7, #4]
 8006c10:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8006c14:	2b01      	cmp	r3, #1
 8006c16:	d103      	bne.n	8006c20 <prvDeleteTCB+0x40>
				vPortFree( pxTCB );
 8006c18:	6878      	ldr	r0, [r7, #4]
 8006c1a:	f001 f8a5 	bl	8007d68 <vPortFree>
	}
 8006c1e:	e010      	b.n	8006c42 <prvDeleteTCB+0x62>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
 8006c20:	687b      	ldr	r3, [r7, #4]
 8006c22:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8006c26:	2b02      	cmp	r3, #2
 8006c28:	d00b      	beq.n	8006c42 <prvDeleteTCB+0x62>
	__asm volatile
 8006c2a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006c2e:	f383 8811 	msr	BASEPRI, r3
 8006c32:	f3bf 8f6f 	isb	sy
 8006c36:	f3bf 8f4f 	dsb	sy
 8006c3a:	60fb      	str	r3, [r7, #12]
}
 8006c3c:	bf00      	nop
 8006c3e:	bf00      	nop
 8006c40:	e7fd      	b.n	8006c3e <prvDeleteTCB+0x5e>
	}
 8006c42:	bf00      	nop
 8006c44:	3710      	adds	r7, #16
 8006c46:	46bd      	mov	sp, r7
 8006c48:	bd80      	pop	{r7, pc}
	...

08006c4c <prvResetNextTaskUnblockTime>:

#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/

static void prvResetNextTaskUnblockTime( void )
{
 8006c4c:	b480      	push	{r7}
 8006c4e:	b083      	sub	sp, #12
 8006c50:	af00      	add	r7, sp, #0
TCB_t *pxTCB;

	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8006c52:	4b0c      	ldr	r3, [pc, #48]	@ (8006c84 <prvResetNextTaskUnblockTime+0x38>)
 8006c54:	681b      	ldr	r3, [r3, #0]
 8006c56:	681b      	ldr	r3, [r3, #0]
 8006c58:	2b00      	cmp	r3, #0
 8006c5a:	d104      	bne.n	8006c66 <prvResetNextTaskUnblockTime+0x1a>
	{
		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
		the maximum possible value so it is	extremely unlikely that the
		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
		there is an item in the delayed list. */
		xNextTaskUnblockTime = portMAX_DELAY;
 8006c5c:	4b0a      	ldr	r3, [pc, #40]	@ (8006c88 <prvResetNextTaskUnblockTime+0x3c>)
 8006c5e:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8006c62:	601a      	str	r2, [r3, #0]
		which the task at the head of the delayed list should be removed
		from the Blocked state. */
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
	}
}
 8006c64:	e008      	b.n	8006c78 <prvResetNextTaskUnblockTime+0x2c>
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8006c66:	4b07      	ldr	r3, [pc, #28]	@ (8006c84 <prvResetNextTaskUnblockTime+0x38>)
 8006c68:	681b      	ldr	r3, [r3, #0]
 8006c6a:	68db      	ldr	r3, [r3, #12]
 8006c6c:	68db      	ldr	r3, [r3, #12]
 8006c6e:	607b      	str	r3, [r7, #4]
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
 8006c70:	687b      	ldr	r3, [r7, #4]
 8006c72:	685b      	ldr	r3, [r3, #4]
 8006c74:	4a04      	ldr	r2, [pc, #16]	@ (8006c88 <prvResetNextTaskUnblockTime+0x3c>)
 8006c76:	6013      	str	r3, [r2, #0]
}
 8006c78:	bf00      	nop
 8006c7a:	370c      	adds	r7, #12
 8006c7c:	46bd      	mov	sp, r7
 8006c7e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006c82:	4770      	bx	lr
 8006c84:	20001454 	.word	0x20001454
 8006c88:	200014bc 	.word	0x200014bc

08006c8c <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

	BaseType_t xTaskGetSchedulerState( void )
	{
 8006c8c:	b480      	push	{r7}
 8006c8e:	b083      	sub	sp, #12
 8006c90:	af00      	add	r7, sp, #0
	BaseType_t xReturn;

		if( xSchedulerRunning == pdFALSE )
 8006c92:	4b0b      	ldr	r3, [pc, #44]	@ (8006cc0 <xTaskGetSchedulerState+0x34>)
 8006c94:	681b      	ldr	r3, [r3, #0]
 8006c96:	2b00      	cmp	r3, #0
 8006c98:	d102      	bne.n	8006ca0 <xTaskGetSchedulerState+0x14>
		{
			xReturn = taskSCHEDULER_NOT_STARTED;
 8006c9a:	2301      	movs	r3, #1
 8006c9c:	607b      	str	r3, [r7, #4]
 8006c9e:	e008      	b.n	8006cb2 <xTaskGetSchedulerState+0x26>
		}
		else
		{
			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8006ca0:	4b08      	ldr	r3, [pc, #32]	@ (8006cc4 <xTaskGetSchedulerState+0x38>)
 8006ca2:	681b      	ldr	r3, [r3, #0]
 8006ca4:	2b00      	cmp	r3, #0
 8006ca6:	d102      	bne.n	8006cae <xTaskGetSchedulerState+0x22>
			{
				xReturn = taskSCHEDULER_RUNNING;
 8006ca8:	2302      	movs	r3, #2
 8006caa:	607b      	str	r3, [r7, #4]
 8006cac:	e001      	b.n	8006cb2 <xTaskGetSchedulerState+0x26>
			}
			else
			{
				xReturn = taskSCHEDULER_SUSPENDED;
 8006cae:	2300      	movs	r3, #0
 8006cb0:	607b      	str	r3, [r7, #4]
			}
		}

		return xReturn;
 8006cb2:	687b      	ldr	r3, [r7, #4]
	}
 8006cb4:	4618      	mov	r0, r3
 8006cb6:	370c      	adds	r7, #12
 8006cb8:	46bd      	mov	sp, r7
 8006cba:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006cbe:	4770      	bx	lr
 8006cc0:	200014a8 	.word	0x200014a8
 8006cc4:	200014c4 	.word	0x200014c4

08006cc8 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
	{
 8006cc8:	b580      	push	{r7, lr}
 8006cca:	b086      	sub	sp, #24
 8006ccc:	af00      	add	r7, sp, #0
 8006cce:	6078      	str	r0, [r7, #4]
	TCB_t * const pxTCB = pxMutexHolder;
 8006cd0:	687b      	ldr	r3, [r7, #4]
 8006cd2:	613b      	str	r3, [r7, #16]
	BaseType_t xReturn = pdFALSE;
 8006cd4:	2300      	movs	r3, #0
 8006cd6:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 8006cd8:	687b      	ldr	r3, [r7, #4]
 8006cda:	2b00      	cmp	r3, #0
 8006cdc:	d058      	beq.n	8006d90 <xTaskPriorityDisinherit+0xc8>
		{
			/* A task can only have an inherited priority if it holds the mutex.
			If the mutex is held by a task then it cannot be given from an
			interrupt, and if a mutex is given by the holding task then it must
			be the running state task. */
			configASSERT( pxTCB == pxCurrentTCB );
 8006cde:	4b2f      	ldr	r3, [pc, #188]	@ (8006d9c <xTaskPriorityDisinherit+0xd4>)
 8006ce0:	681b      	ldr	r3, [r3, #0]
 8006ce2:	693a      	ldr	r2, [r7, #16]
 8006ce4:	429a      	cmp	r2, r3
 8006ce6:	d00b      	beq.n	8006d00 <xTaskPriorityDisinherit+0x38>
	__asm volatile
 8006ce8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006cec:	f383 8811 	msr	BASEPRI, r3
 8006cf0:	f3bf 8f6f 	isb	sy
 8006cf4:	f3bf 8f4f 	dsb	sy
 8006cf8:	60fb      	str	r3, [r7, #12]
}
 8006cfa:	bf00      	nop
 8006cfc:	bf00      	nop
 8006cfe:	e7fd      	b.n	8006cfc <xTaskPriorityDisinherit+0x34>
			configASSERT( pxTCB->uxMutexesHeld );
 8006d00:	693b      	ldr	r3, [r7, #16]
 8006d02:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8006d04:	2b00      	cmp	r3, #0
 8006d06:	d10b      	bne.n	8006d20 <xTaskPriorityDisinherit+0x58>
	__asm volatile
 8006d08:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006d0c:	f383 8811 	msr	BASEPRI, r3
 8006d10:	f3bf 8f6f 	isb	sy
 8006d14:	f3bf 8f4f 	dsb	sy
 8006d18:	60bb      	str	r3, [r7, #8]
}
 8006d1a:	bf00      	nop
 8006d1c:	bf00      	nop
 8006d1e:	e7fd      	b.n	8006d1c <xTaskPriorityDisinherit+0x54>
			( pxTCB->uxMutexesHeld )--;
 8006d20:	693b      	ldr	r3, [r7, #16]
 8006d22:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8006d24:	1e5a      	subs	r2, r3, #1
 8006d26:	693b      	ldr	r3, [r7, #16]
 8006d28:	651a      	str	r2, [r3, #80]	@ 0x50

			/* Has the holder of the mutex inherited the priority of another
			task? */
			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
 8006d2a:	693b      	ldr	r3, [r7, #16]
 8006d2c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006d2e:	693b      	ldr	r3, [r7, #16]
 8006d30:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8006d32:	429a      	cmp	r2, r3
 8006d34:	d02c      	beq.n	8006d90 <xTaskPriorityDisinherit+0xc8>
			{
				/* Only disinherit if no other mutexes are held. */
				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
 8006d36:	693b      	ldr	r3, [r7, #16]
 8006d38:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8006d3a:	2b00      	cmp	r3, #0
 8006d3c:	d128      	bne.n	8006d90 <xTaskPriorityDisinherit+0xc8>
					/* A task can only have an inherited priority if it holds
					the mutex.  If the mutex is held by a task then it cannot be
					given from an interrupt, and if a mutex is given by the
					holding task then it must be the running state task.  Remove
					the holding task from the ready/delayed list. */
					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8006d3e:	693b      	ldr	r3, [r7, #16]
 8006d40:	3304      	adds	r3, #4
 8006d42:	4618      	mov	r0, r3
 8006d44:	f7fe fc26 	bl	8005594 <uxListRemove>
					}

					/* Disinherit the priority before adding the task into the
					new	ready list. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					pxTCB->uxPriority = pxTCB->uxBasePriority;
 8006d48:	693b      	ldr	r3, [r7, #16]
 8006d4a:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 8006d4c:	693b      	ldr	r3, [r7, #16]
 8006d4e:	62da      	str	r2, [r3, #44]	@ 0x2c

					/* Reset the event list item value.  It cannot be in use for
					any other purpose if this task is running, and it must be
					running to give back the mutex. */
					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8006d50:	693b      	ldr	r3, [r7, #16]
 8006d52:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8006d54:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 8006d58:	693b      	ldr	r3, [r7, #16]
 8006d5a:	619a      	str	r2, [r3, #24]
					prvAddTaskToReadyList( pxTCB );
 8006d5c:	693b      	ldr	r3, [r7, #16]
 8006d5e:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006d60:	4b0f      	ldr	r3, [pc, #60]	@ (8006da0 <xTaskPriorityDisinherit+0xd8>)
 8006d62:	681b      	ldr	r3, [r3, #0]
 8006d64:	429a      	cmp	r2, r3
 8006d66:	d903      	bls.n	8006d70 <xTaskPriorityDisinherit+0xa8>
 8006d68:	693b      	ldr	r3, [r7, #16]
 8006d6a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8006d6c:	4a0c      	ldr	r2, [pc, #48]	@ (8006da0 <xTaskPriorityDisinherit+0xd8>)
 8006d6e:	6013      	str	r3, [r2, #0]
 8006d70:	693b      	ldr	r3, [r7, #16]
 8006d72:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006d74:	4613      	mov	r3, r2
 8006d76:	009b      	lsls	r3, r3, #2
 8006d78:	4413      	add	r3, r2
 8006d7a:	009b      	lsls	r3, r3, #2
 8006d7c:	4a09      	ldr	r2, [pc, #36]	@ (8006da4 <xTaskPriorityDisinherit+0xdc>)
 8006d7e:	441a      	add	r2, r3
 8006d80:	693b      	ldr	r3, [r7, #16]
 8006d82:	3304      	adds	r3, #4
 8006d84:	4619      	mov	r1, r3
 8006d86:	4610      	mov	r0, r2
 8006d88:	f7fe fba7 	bl	80054da <vListInsertEnd>
					in an order different to that in which they were taken.
					If a context switch did not occur when the first mutex was
					returned, even if a task was waiting on it, then a context
					switch should occur when the last mutex is returned whether
					a task is waiting on it or not. */
					xReturn = pdTRUE;
 8006d8c:	2301      	movs	r3, #1
 8006d8e:	617b      	str	r3, [r7, #20]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 8006d90:	697b      	ldr	r3, [r7, #20]
	}
 8006d92:	4618      	mov	r0, r3
 8006d94:	3718      	adds	r7, #24
 8006d96:	46bd      	mov	sp, r7
 8006d98:	bd80      	pop	{r7, pc}
 8006d9a:	bf00      	nop
 8006d9c:	20000fc8 	.word	0x20000fc8
 8006da0:	200014a4 	.word	0x200014a4
 8006da4:	20000fcc 	.word	0x20000fcc

08006da8 <ulTaskNotifyTake>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
	{
 8006da8:	b580      	push	{r7, lr}
 8006daa:	b084      	sub	sp, #16
 8006dac:	af00      	add	r7, sp, #0
 8006dae:	6078      	str	r0, [r7, #4]
 8006db0:	6039      	str	r1, [r7, #0]
	uint32_t ulReturn;

		taskENTER_CRITICAL();
 8006db2:	f000 fde9 	bl	8007988 <vPortEnterCritical>
		{
			/* Only block if the notification count is not already non-zero. */
			if( pxCurrentTCB->ulNotifiedValue == 0UL )
 8006db6:	4b20      	ldr	r3, [pc, #128]	@ (8006e38 <ulTaskNotifyTake+0x90>)
 8006db8:	681b      	ldr	r3, [r3, #0]
 8006dba:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 8006dbe:	2b00      	cmp	r3, #0
 8006dc0:	d113      	bne.n	8006dea <ulTaskNotifyTake+0x42>
			{
				/* Mark this task as waiting for a notification. */
				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
 8006dc2:	4b1d      	ldr	r3, [pc, #116]	@ (8006e38 <ulTaskNotifyTake+0x90>)
 8006dc4:	681b      	ldr	r3, [r3, #0]
 8006dc6:	2201      	movs	r2, #1
 8006dc8:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4

				if( xTicksToWait > ( TickType_t ) 0 )
 8006dcc:	683b      	ldr	r3, [r7, #0]
 8006dce:	2b00      	cmp	r3, #0
 8006dd0:	d00b      	beq.n	8006dea <ulTaskNotifyTake+0x42>
				{
					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 8006dd2:	2101      	movs	r1, #1
 8006dd4:	6838      	ldr	r0, [r7, #0]
 8006dd6:	f000 f8f5 	bl	8006fc4 <prvAddCurrentTaskToDelayedList>

					/* All ports are written to allow a yield in a critical
					section (some will yield immediately, others wait until the
					critical section exits) - but it is not something that
					application code should ever do. */
					portYIELD_WITHIN_API();
 8006dda:	4b18      	ldr	r3, [pc, #96]	@ (8006e3c <ulTaskNotifyTake+0x94>)
 8006ddc:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006de0:	601a      	str	r2, [r3, #0]
 8006de2:	f3bf 8f4f 	dsb	sy
 8006de6:	f3bf 8f6f 	isb	sy
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
		taskEXIT_CRITICAL();
 8006dea:	f000 fdff 	bl	80079ec <vPortExitCritical>

		taskENTER_CRITICAL();
 8006dee:	f000 fdcb 	bl	8007988 <vPortEnterCritical>
		{
			traceTASK_NOTIFY_TAKE();
			ulReturn = pxCurrentTCB->ulNotifiedValue;
 8006df2:	4b11      	ldr	r3, [pc, #68]	@ (8006e38 <ulTaskNotifyTake+0x90>)
 8006df4:	681b      	ldr	r3, [r3, #0]
 8006df6:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 8006dfa:	60fb      	str	r3, [r7, #12]

			if( ulReturn != 0UL )
 8006dfc:	68fb      	ldr	r3, [r7, #12]
 8006dfe:	2b00      	cmp	r3, #0
 8006e00:	d00e      	beq.n	8006e20 <ulTaskNotifyTake+0x78>
			{
				if( xClearCountOnExit != pdFALSE )
 8006e02:	687b      	ldr	r3, [r7, #4]
 8006e04:	2b00      	cmp	r3, #0
 8006e06:	d005      	beq.n	8006e14 <ulTaskNotifyTake+0x6c>
				{
					pxCurrentTCB->ulNotifiedValue = 0UL;
 8006e08:	4b0b      	ldr	r3, [pc, #44]	@ (8006e38 <ulTaskNotifyTake+0x90>)
 8006e0a:	681b      	ldr	r3, [r3, #0]
 8006e0c:	2200      	movs	r2, #0
 8006e0e:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
 8006e12:	e005      	b.n	8006e20 <ulTaskNotifyTake+0x78>
				}
				else
				{
					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
 8006e14:	4b08      	ldr	r3, [pc, #32]	@ (8006e38 <ulTaskNotifyTake+0x90>)
 8006e16:	681b      	ldr	r3, [r3, #0]
 8006e18:	68fa      	ldr	r2, [r7, #12]
 8006e1a:	3a01      	subs	r2, #1
 8006e1c:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 8006e20:	4b05      	ldr	r3, [pc, #20]	@ (8006e38 <ulTaskNotifyTake+0x90>)
 8006e22:	681b      	ldr	r3, [r3, #0]
 8006e24:	2200      	movs	r2, #0
 8006e26:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
		}
		taskEXIT_CRITICAL();
 8006e2a:	f000 fddf 	bl	80079ec <vPortExitCritical>

		return ulReturn;
 8006e2e:	68fb      	ldr	r3, [r7, #12]
	}
 8006e30:	4618      	mov	r0, r3
 8006e32:	3710      	adds	r7, #16
 8006e34:	46bd      	mov	sp, r7
 8006e36:	bd80      	pop	{r7, pc}
 8006e38:	20000fc8 	.word	0x20000fc8
 8006e3c:	e000ed04 	.word	0xe000ed04

08006e40 <xTaskGenericNotify>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
	{
 8006e40:	b580      	push	{r7, lr}
 8006e42:	b08a      	sub	sp, #40	@ 0x28
 8006e44:	af00      	add	r7, sp, #0
 8006e46:	60f8      	str	r0, [r7, #12]
 8006e48:	60b9      	str	r1, [r7, #8]
 8006e4a:	603b      	str	r3, [r7, #0]
 8006e4c:	4613      	mov	r3, r2
 8006e4e:	71fb      	strb	r3, [r7, #7]
	TCB_t * pxTCB;
	BaseType_t xReturn = pdPASS;
 8006e50:	2301      	movs	r3, #1
 8006e52:	627b      	str	r3, [r7, #36]	@ 0x24
	uint8_t ucOriginalNotifyState;

		configASSERT( xTaskToNotify );
 8006e54:	68fb      	ldr	r3, [r7, #12]
 8006e56:	2b00      	cmp	r3, #0
 8006e58:	d10b      	bne.n	8006e72 <xTaskGenericNotify+0x32>
	__asm volatile
 8006e5a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006e5e:	f383 8811 	msr	BASEPRI, r3
 8006e62:	f3bf 8f6f 	isb	sy
 8006e66:	f3bf 8f4f 	dsb	sy
 8006e6a:	61bb      	str	r3, [r7, #24]
}
 8006e6c:	bf00      	nop
 8006e6e:	bf00      	nop
 8006e70:	e7fd      	b.n	8006e6e <xTaskGenericNotify+0x2e>
		pxTCB = xTaskToNotify;
 8006e72:	68fb      	ldr	r3, [r7, #12]
 8006e74:	623b      	str	r3, [r7, #32]

		taskENTER_CRITICAL();
 8006e76:	f000 fd87 	bl	8007988 <vPortEnterCritical>
		{
			if( pulPreviousNotificationValue != NULL )
 8006e7a:	683b      	ldr	r3, [r7, #0]
 8006e7c:	2b00      	cmp	r3, #0
 8006e7e:	d004      	beq.n	8006e8a <xTaskGenericNotify+0x4a>
			{
				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
 8006e80:	6a3b      	ldr	r3, [r7, #32]
 8006e82:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 8006e86:	683b      	ldr	r3, [r7, #0]
 8006e88:	601a      	str	r2, [r3, #0]
			}

			ucOriginalNotifyState = pxTCB->ucNotifyState;
 8006e8a:	6a3b      	ldr	r3, [r7, #32]
 8006e8c:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 8006e90:	77fb      	strb	r3, [r7, #31]

			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
 8006e92:	6a3b      	ldr	r3, [r7, #32]
 8006e94:	2202      	movs	r2, #2
 8006e96:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4

			switch( eAction )
 8006e9a:	79fb      	ldrb	r3, [r7, #7]
 8006e9c:	2b04      	cmp	r3, #4
 8006e9e:	d82e      	bhi.n	8006efe <xTaskGenericNotify+0xbe>
 8006ea0:	a201      	add	r2, pc, #4	@ (adr r2, 8006ea8 <xTaskGenericNotify+0x68>)
 8006ea2:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8006ea6:	bf00      	nop
 8006ea8:	08006f23 	.word	0x08006f23
 8006eac:	08006ebd 	.word	0x08006ebd
 8006eb0:	08006ecf 	.word	0x08006ecf
 8006eb4:	08006edf 	.word	0x08006edf
 8006eb8:	08006ee9 	.word	0x08006ee9
			{
				case eSetBits	:
					pxTCB->ulNotifiedValue |= ulValue;
 8006ebc:	6a3b      	ldr	r3, [r7, #32]
 8006ebe:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 8006ec2:	68bb      	ldr	r3, [r7, #8]
 8006ec4:	431a      	orrs	r2, r3
 8006ec6:	6a3b      	ldr	r3, [r7, #32]
 8006ec8:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 8006ecc:	e02c      	b.n	8006f28 <xTaskGenericNotify+0xe8>

				case eIncrement	:
					( pxTCB->ulNotifiedValue )++;
 8006ece:	6a3b      	ldr	r3, [r7, #32]
 8006ed0:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 8006ed4:	1c5a      	adds	r2, r3, #1
 8006ed6:	6a3b      	ldr	r3, [r7, #32]
 8006ed8:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 8006edc:	e024      	b.n	8006f28 <xTaskGenericNotify+0xe8>

				case eSetValueWithOverwrite	:
					pxTCB->ulNotifiedValue = ulValue;
 8006ede:	6a3b      	ldr	r3, [r7, #32]
 8006ee0:	68ba      	ldr	r2, [r7, #8]
 8006ee2:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 8006ee6:	e01f      	b.n	8006f28 <xTaskGenericNotify+0xe8>

				case eSetValueWithoutOverwrite :
					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
 8006ee8:	7ffb      	ldrb	r3, [r7, #31]
 8006eea:	2b02      	cmp	r3, #2
 8006eec:	d004      	beq.n	8006ef8 <xTaskGenericNotify+0xb8>
					{
						pxTCB->ulNotifiedValue = ulValue;
 8006eee:	6a3b      	ldr	r3, [r7, #32]
 8006ef0:	68ba      	ldr	r2, [r7, #8]
 8006ef2:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					else
					{
						/* The value could not be written to the task. */
						xReturn = pdFAIL;
					}
					break;
 8006ef6:	e017      	b.n	8006f28 <xTaskGenericNotify+0xe8>
						xReturn = pdFAIL;
 8006ef8:	2300      	movs	r3, #0
 8006efa:	627b      	str	r3, [r7, #36]	@ 0x24
					break;
 8006efc:	e014      	b.n	8006f28 <xTaskGenericNotify+0xe8>

				default:
					/* Should not get here if all enums are handled.
					Artificially force an assert by testing a value the
					compiler can't assume is const. */
					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
 8006efe:	6a3b      	ldr	r3, [r7, #32]
 8006f00:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 8006f04:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006f08:	d00d      	beq.n	8006f26 <xTaskGenericNotify+0xe6>
	__asm volatile
 8006f0a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006f0e:	f383 8811 	msr	BASEPRI, r3
 8006f12:	f3bf 8f6f 	isb	sy
 8006f16:	f3bf 8f4f 	dsb	sy
 8006f1a:	617b      	str	r3, [r7, #20]
}
 8006f1c:	bf00      	nop
 8006f1e:	bf00      	nop
 8006f20:	e7fd      	b.n	8006f1e <xTaskGenericNotify+0xde>
					break;
 8006f22:	bf00      	nop
 8006f24:	e000      	b.n	8006f28 <xTaskGenericNotify+0xe8>

					break;
 8006f26:	bf00      	nop

			traceTASK_NOTIFY();

			/* If the task is in the blocked state specifically to wait for a
			notification then unblock it now. */
			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
 8006f28:	7ffb      	ldrb	r3, [r7, #31]
 8006f2a:	2b01      	cmp	r3, #1
 8006f2c:	d13b      	bne.n	8006fa6 <xTaskGenericNotify+0x166>
			{
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8006f2e:	6a3b      	ldr	r3, [r7, #32]
 8006f30:	3304      	adds	r3, #4
 8006f32:	4618      	mov	r0, r3
 8006f34:	f7fe fb2e 	bl	8005594 <uxListRemove>
				prvAddTaskToReadyList( pxTCB );
 8006f38:	6a3b      	ldr	r3, [r7, #32]
 8006f3a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006f3c:	4b1d      	ldr	r3, [pc, #116]	@ (8006fb4 <xTaskGenericNotify+0x174>)
 8006f3e:	681b      	ldr	r3, [r3, #0]
 8006f40:	429a      	cmp	r2, r3
 8006f42:	d903      	bls.n	8006f4c <xTaskGenericNotify+0x10c>
 8006f44:	6a3b      	ldr	r3, [r7, #32]
 8006f46:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8006f48:	4a1a      	ldr	r2, [pc, #104]	@ (8006fb4 <xTaskGenericNotify+0x174>)
 8006f4a:	6013      	str	r3, [r2, #0]
 8006f4c:	6a3b      	ldr	r3, [r7, #32]
 8006f4e:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006f50:	4613      	mov	r3, r2
 8006f52:	009b      	lsls	r3, r3, #2
 8006f54:	4413      	add	r3, r2
 8006f56:	009b      	lsls	r3, r3, #2
 8006f58:	4a17      	ldr	r2, [pc, #92]	@ (8006fb8 <xTaskGenericNotify+0x178>)
 8006f5a:	441a      	add	r2, r3
 8006f5c:	6a3b      	ldr	r3, [r7, #32]
 8006f5e:	3304      	adds	r3, #4
 8006f60:	4619      	mov	r1, r3
 8006f62:	4610      	mov	r0, r2
 8006f64:	f7fe fab9 	bl	80054da <vListInsertEnd>

				/* The task should not have been on an event list. */
				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
 8006f68:	6a3b      	ldr	r3, [r7, #32]
 8006f6a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8006f6c:	2b00      	cmp	r3, #0
 8006f6e:	d00b      	beq.n	8006f88 <xTaskGenericNotify+0x148>
	__asm volatile
 8006f70:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006f74:	f383 8811 	msr	BASEPRI, r3
 8006f78:	f3bf 8f6f 	isb	sy
 8006f7c:	f3bf 8f4f 	dsb	sy
 8006f80:	613b      	str	r3, [r7, #16]
}
 8006f82:	bf00      	nop
 8006f84:	bf00      	nop
 8006f86:	e7fd      	b.n	8006f84 <xTaskGenericNotify+0x144>
					earliest possible time. */
					prvResetNextTaskUnblockTime();
				}
				#endif

				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
 8006f88:	6a3b      	ldr	r3, [r7, #32]
 8006f8a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006f8c:	4b0b      	ldr	r3, [pc, #44]	@ (8006fbc <xTaskGenericNotify+0x17c>)
 8006f8e:	681b      	ldr	r3, [r3, #0]
 8006f90:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8006f92:	429a      	cmp	r2, r3
 8006f94:	d907      	bls.n	8006fa6 <xTaskGenericNotify+0x166>
				{
					/* The notified task has a priority above the currently
					executing task so a yield is required. */
					taskYIELD_IF_USING_PREEMPTION();
 8006f96:	4b0a      	ldr	r3, [pc, #40]	@ (8006fc0 <xTaskGenericNotify+0x180>)
 8006f98:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006f9c:	601a      	str	r2, [r3, #0]
 8006f9e:	f3bf 8f4f 	dsb	sy
 8006fa2:	f3bf 8f6f 	isb	sy
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
		taskEXIT_CRITICAL();
 8006fa6:	f000 fd21 	bl	80079ec <vPortExitCritical>

		return xReturn;
 8006faa:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
	}
 8006fac:	4618      	mov	r0, r3
 8006fae:	3728      	adds	r7, #40	@ 0x28
 8006fb0:	46bd      	mov	sp, r7
 8006fb2:	bd80      	pop	{r7, pc}
 8006fb4:	200014a4 	.word	0x200014a4
 8006fb8:	20000fcc 	.word	0x20000fcc
 8006fbc:	20000fc8 	.word	0x20000fc8
 8006fc0:	e000ed04 	.word	0xe000ed04

08006fc4 <prvAddCurrentTaskToDelayedList>:

#endif
/*-----------------------------------------------------------*/

static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
 8006fc4:	b580      	push	{r7, lr}
 8006fc6:	b084      	sub	sp, #16
 8006fc8:	af00      	add	r7, sp, #0
 8006fca:	6078      	str	r0, [r7, #4]
 8006fcc:	6039      	str	r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
 8006fce:	4b21      	ldr	r3, [pc, #132]	@ (8007054 <prvAddCurrentTaskToDelayedList+0x90>)
 8006fd0:	681b      	ldr	r3, [r3, #0]
 8006fd2:	60fb      	str	r3, [r7, #12]
	}
	#endif

	/* Remove the task from the ready list before adding it to the blocked list
	as the same list item is used for both lists. */
	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8006fd4:	4b20      	ldr	r3, [pc, #128]	@ (8007058 <prvAddCurrentTaskToDelayedList+0x94>)
 8006fd6:	681b      	ldr	r3, [r3, #0]
 8006fd8:	3304      	adds	r3, #4
 8006fda:	4618      	mov	r0, r3
 8006fdc:	f7fe fada 	bl	8005594 <uxListRemove>
		mtCOVERAGE_TEST_MARKER();
	}

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
 8006fe0:	687b      	ldr	r3, [r7, #4]
 8006fe2:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006fe6:	d10a      	bne.n	8006ffe <prvAddCurrentTaskToDelayedList+0x3a>
 8006fe8:	683b      	ldr	r3, [r7, #0]
 8006fea:	2b00      	cmp	r3, #0
 8006fec:	d007      	beq.n	8006ffe <prvAddCurrentTaskToDelayedList+0x3a>
		{
			/* Add the task to the suspended task list instead of a delayed task
			list to ensure it is not woken by a timing event.  It will block
			indefinitely. */
			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8006fee:	4b1a      	ldr	r3, [pc, #104]	@ (8007058 <prvAddCurrentTaskToDelayedList+0x94>)
 8006ff0:	681b      	ldr	r3, [r3, #0]
 8006ff2:	3304      	adds	r3, #4
 8006ff4:	4619      	mov	r1, r3
 8006ff6:	4819      	ldr	r0, [pc, #100]	@ (800705c <prvAddCurrentTaskToDelayedList+0x98>)
 8006ff8:	f7fe fa6f 	bl	80054da <vListInsertEnd>

		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
		( void ) xCanBlockIndefinitely;
	}
	#endif /* INCLUDE_vTaskSuspend */
}
 8006ffc:	e026      	b.n	800704c <prvAddCurrentTaskToDelayedList+0x88>
			xTimeToWake = xConstTickCount + xTicksToWait;
 8006ffe:	68fa      	ldr	r2, [r7, #12]
 8007000:	687b      	ldr	r3, [r7, #4]
 8007002:	4413      	add	r3, r2
 8007004:	60bb      	str	r3, [r7, #8]
			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
 8007006:	4b14      	ldr	r3, [pc, #80]	@ (8007058 <prvAddCurrentTaskToDelayedList+0x94>)
 8007008:	681b      	ldr	r3, [r3, #0]
 800700a:	68ba      	ldr	r2, [r7, #8]
 800700c:	605a      	str	r2, [r3, #4]
			if( xTimeToWake < xConstTickCount )
 800700e:	68ba      	ldr	r2, [r7, #8]
 8007010:	68fb      	ldr	r3, [r7, #12]
 8007012:	429a      	cmp	r2, r3
 8007014:	d209      	bcs.n	800702a <prvAddCurrentTaskToDelayedList+0x66>
				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8007016:	4b12      	ldr	r3, [pc, #72]	@ (8007060 <prvAddCurrentTaskToDelayedList+0x9c>)
 8007018:	681a      	ldr	r2, [r3, #0]
 800701a:	4b0f      	ldr	r3, [pc, #60]	@ (8007058 <prvAddCurrentTaskToDelayedList+0x94>)
 800701c:	681b      	ldr	r3, [r3, #0]
 800701e:	3304      	adds	r3, #4
 8007020:	4619      	mov	r1, r3
 8007022:	4610      	mov	r0, r2
 8007024:	f7fe fa7d 	bl	8005522 <vListInsert>
}
 8007028:	e010      	b.n	800704c <prvAddCurrentTaskToDelayedList+0x88>
				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 800702a:	4b0e      	ldr	r3, [pc, #56]	@ (8007064 <prvAddCurrentTaskToDelayedList+0xa0>)
 800702c:	681a      	ldr	r2, [r3, #0]
 800702e:	4b0a      	ldr	r3, [pc, #40]	@ (8007058 <prvAddCurrentTaskToDelayedList+0x94>)
 8007030:	681b      	ldr	r3, [r3, #0]
 8007032:	3304      	adds	r3, #4
 8007034:	4619      	mov	r1, r3
 8007036:	4610      	mov	r0, r2
 8007038:	f7fe fa73 	bl	8005522 <vListInsert>
				if( xTimeToWake < xNextTaskUnblockTime )
 800703c:	4b0a      	ldr	r3, [pc, #40]	@ (8007068 <prvAddCurrentTaskToDelayedList+0xa4>)
 800703e:	681b      	ldr	r3, [r3, #0]
 8007040:	68ba      	ldr	r2, [r7, #8]
 8007042:	429a      	cmp	r2, r3
 8007044:	d202      	bcs.n	800704c <prvAddCurrentTaskToDelayedList+0x88>
					xNextTaskUnblockTime = xTimeToWake;
 8007046:	4a08      	ldr	r2, [pc, #32]	@ (8007068 <prvAddCurrentTaskToDelayedList+0xa4>)
 8007048:	68bb      	ldr	r3, [r7, #8]
 800704a:	6013      	str	r3, [r2, #0]
}
 800704c:	bf00      	nop
 800704e:	3710      	adds	r7, #16
 8007050:	46bd      	mov	sp, r7
 8007052:	bd80      	pop	{r7, pc}
 8007054:	200014a0 	.word	0x200014a0
 8007058:	20000fc8 	.word	0x20000fc8
 800705c:	20001488 	.word	0x20001488
 8007060:	20001458 	.word	0x20001458
 8007064:	20001454 	.word	0x20001454
 8007068:	200014bc 	.word	0x200014bc

0800706c <xTimerCreateTimerTask>:
									TimerCallbackFunction_t pxCallbackFunction,
									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/

BaseType_t xTimerCreateTimerTask( void )
{
 800706c:	b580      	push	{r7, lr}
 800706e:	b08a      	sub	sp, #40	@ 0x28
 8007070:	af04      	add	r7, sp, #16
BaseType_t xReturn = pdFAIL;
 8007072:	2300      	movs	r3, #0
 8007074:	617b      	str	r3, [r7, #20]

	/* This function is called when the scheduler is started if
	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
	timer service task has been created/initialised.  If timers have already
	been created then the initialisation will already have been performed. */
	prvCheckForValidListAndQueue();
 8007076:	f000 fb13 	bl	80076a0 <prvCheckForValidListAndQueue>

	if( xTimerQueue != NULL )
 800707a:	4b1d      	ldr	r3, [pc, #116]	@ (80070f0 <xTimerCreateTimerTask+0x84>)
 800707c:	681b      	ldr	r3, [r3, #0]
 800707e:	2b00      	cmp	r3, #0
 8007080:	d021      	beq.n	80070c6 <xTimerCreateTimerTask+0x5a>
	{
		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
		{
			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
 8007082:	2300      	movs	r3, #0
 8007084:	60fb      	str	r3, [r7, #12]
			StackType_t *pxTimerTaskStackBuffer = NULL;
 8007086:	2300      	movs	r3, #0
 8007088:	60bb      	str	r3, [r7, #8]
			uint32_t ulTimerTaskStackSize;

			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
 800708a:	1d3a      	adds	r2, r7, #4
 800708c:	f107 0108 	add.w	r1, r7, #8
 8007090:	f107 030c 	add.w	r3, r7, #12
 8007094:	4618      	mov	r0, r3
 8007096:	f7fe f9d9 	bl	800544c <vApplicationGetTimerTaskMemory>
			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
 800709a:	6879      	ldr	r1, [r7, #4]
 800709c:	68bb      	ldr	r3, [r7, #8]
 800709e:	68fa      	ldr	r2, [r7, #12]
 80070a0:	9202      	str	r2, [sp, #8]
 80070a2:	9301      	str	r3, [sp, #4]
 80070a4:	2302      	movs	r3, #2
 80070a6:	9300      	str	r3, [sp, #0]
 80070a8:	2300      	movs	r3, #0
 80070aa:	460a      	mov	r2, r1
 80070ac:	4911      	ldr	r1, [pc, #68]	@ (80070f4 <xTimerCreateTimerTask+0x88>)
 80070ae:	4812      	ldr	r0, [pc, #72]	@ (80070f8 <xTimerCreateTimerTask+0x8c>)
 80070b0:	f7fe ff94 	bl	8005fdc <xTaskCreateStatic>
 80070b4:	4603      	mov	r3, r0
 80070b6:	4a11      	ldr	r2, [pc, #68]	@ (80070fc <xTimerCreateTimerTask+0x90>)
 80070b8:	6013      	str	r3, [r2, #0]
													NULL,
													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
													pxTimerTaskStackBuffer,
													pxTimerTaskTCBBuffer );

			if( xTimerTaskHandle != NULL )
 80070ba:	4b10      	ldr	r3, [pc, #64]	@ (80070fc <xTimerCreateTimerTask+0x90>)
 80070bc:	681b      	ldr	r3, [r3, #0]
 80070be:	2b00      	cmp	r3, #0
 80070c0:	d001      	beq.n	80070c6 <xTimerCreateTimerTask+0x5a>
			{
				xReturn = pdPASS;
 80070c2:	2301      	movs	r3, #1
 80070c4:	617b      	str	r3, [r7, #20]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	configASSERT( xReturn );
 80070c6:	697b      	ldr	r3, [r7, #20]
 80070c8:	2b00      	cmp	r3, #0
 80070ca:	d10b      	bne.n	80070e4 <xTimerCreateTimerTask+0x78>
	__asm volatile
 80070cc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80070d0:	f383 8811 	msr	BASEPRI, r3
 80070d4:	f3bf 8f6f 	isb	sy
 80070d8:	f3bf 8f4f 	dsb	sy
 80070dc:	613b      	str	r3, [r7, #16]
}
 80070de:	bf00      	nop
 80070e0:	bf00      	nop
 80070e2:	e7fd      	b.n	80070e0 <xTimerCreateTimerTask+0x74>
	return xReturn;
 80070e4:	697b      	ldr	r3, [r7, #20]
}
 80070e6:	4618      	mov	r0, r3
 80070e8:	3718      	adds	r7, #24
 80070ea:	46bd      	mov	sp, r7
 80070ec:	bd80      	pop	{r7, pc}
 80070ee:	bf00      	nop
 80070f0:	200014f8 	.word	0x200014f8
 80070f4:	080081f0 	.word	0x080081f0
 80070f8:	08007239 	.word	0x08007239
 80070fc:	200014fc 	.word	0x200014fc

08007100 <xTimerGenericCommand>:
	}
}
/*-----------------------------------------------------------*/

BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
 8007100:	b580      	push	{r7, lr}
 8007102:	b08a      	sub	sp, #40	@ 0x28
 8007104:	af00      	add	r7, sp, #0
 8007106:	60f8      	str	r0, [r7, #12]
 8007108:	60b9      	str	r1, [r7, #8]
 800710a:	607a      	str	r2, [r7, #4]
 800710c:	603b      	str	r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
 800710e:	2300      	movs	r3, #0
 8007110:	627b      	str	r3, [r7, #36]	@ 0x24
DaemonTaskMessage_t xMessage;

	configASSERT( xTimer );
 8007112:	68fb      	ldr	r3, [r7, #12]
 8007114:	2b00      	cmp	r3, #0
 8007116:	d10b      	bne.n	8007130 <xTimerGenericCommand+0x30>
	__asm volatile
 8007118:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800711c:	f383 8811 	msr	BASEPRI, r3
 8007120:	f3bf 8f6f 	isb	sy
 8007124:	f3bf 8f4f 	dsb	sy
 8007128:	623b      	str	r3, [r7, #32]
}
 800712a:	bf00      	nop
 800712c:	bf00      	nop
 800712e:	e7fd      	b.n	800712c <xTimerGenericCommand+0x2c>

	/* Send a message to the timer service task to perform a particular action
	on a particular timer definition. */
	if( xTimerQueue != NULL )
 8007130:	4b19      	ldr	r3, [pc, #100]	@ (8007198 <xTimerGenericCommand+0x98>)
 8007132:	681b      	ldr	r3, [r3, #0]
 8007134:	2b00      	cmp	r3, #0
 8007136:	d02a      	beq.n	800718e <xTimerGenericCommand+0x8e>
	{
		/* Send a command to the timer service task to start the xTimer timer. */
		xMessage.xMessageID = xCommandID;
 8007138:	68bb      	ldr	r3, [r7, #8]
 800713a:	613b      	str	r3, [r7, #16]
		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
 800713c:	687b      	ldr	r3, [r7, #4]
 800713e:	617b      	str	r3, [r7, #20]
		xMessage.u.xTimerParameters.pxTimer = xTimer;
 8007140:	68fb      	ldr	r3, [r7, #12]
 8007142:	61bb      	str	r3, [r7, #24]

		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
 8007144:	68bb      	ldr	r3, [r7, #8]
 8007146:	2b05      	cmp	r3, #5
 8007148:	dc18      	bgt.n	800717c <xTimerGenericCommand+0x7c>
		{
			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
 800714a:	f7ff fd9f 	bl	8006c8c <xTaskGetSchedulerState>
 800714e:	4603      	mov	r3, r0
 8007150:	2b02      	cmp	r3, #2
 8007152:	d109      	bne.n	8007168 <xTimerGenericCommand+0x68>
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
 8007154:	4b10      	ldr	r3, [pc, #64]	@ (8007198 <xTimerGenericCommand+0x98>)
 8007156:	6818      	ldr	r0, [r3, #0]
 8007158:	f107 0110 	add.w	r1, r7, #16
 800715c:	2300      	movs	r3, #0
 800715e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8007160:	f7fe fb4c 	bl	80057fc <xQueueGenericSend>
 8007164:	6278      	str	r0, [r7, #36]	@ 0x24
 8007166:	e012      	b.n	800718e <xTimerGenericCommand+0x8e>
			}
			else
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
 8007168:	4b0b      	ldr	r3, [pc, #44]	@ (8007198 <xTimerGenericCommand+0x98>)
 800716a:	6818      	ldr	r0, [r3, #0]
 800716c:	f107 0110 	add.w	r1, r7, #16
 8007170:	2300      	movs	r3, #0
 8007172:	2200      	movs	r2, #0
 8007174:	f7fe fb42 	bl	80057fc <xQueueGenericSend>
 8007178:	6278      	str	r0, [r7, #36]	@ 0x24
 800717a:	e008      	b.n	800718e <xTimerGenericCommand+0x8e>
			}
		}
		else
		{
			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
 800717c:	4b06      	ldr	r3, [pc, #24]	@ (8007198 <xTimerGenericCommand+0x98>)
 800717e:	6818      	ldr	r0, [r3, #0]
 8007180:	f107 0110 	add.w	r1, r7, #16
 8007184:	2300      	movs	r3, #0
 8007186:	683a      	ldr	r2, [r7, #0]
 8007188:	f7fe fc3a 	bl	8005a00 <xQueueGenericSendFromISR>
 800718c:	6278      	str	r0, [r7, #36]	@ 0x24
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xReturn;
 800718e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
}
 8007190:	4618      	mov	r0, r3
 8007192:	3728      	adds	r7, #40	@ 0x28
 8007194:	46bd      	mov	sp, r7
 8007196:	bd80      	pop	{r7, pc}
 8007198:	200014f8 	.word	0x200014f8

0800719c <prvProcessExpiredTimer>:
	return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/

static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
 800719c:	b580      	push	{r7, lr}
 800719e:	b088      	sub	sp, #32
 80071a0:	af02      	add	r7, sp, #8
 80071a2:	6078      	str	r0, [r7, #4]
 80071a4:	6039      	str	r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80071a6:	4b23      	ldr	r3, [pc, #140]	@ (8007234 <prvProcessExpiredTimer+0x98>)
 80071a8:	681b      	ldr	r3, [r3, #0]
 80071aa:	68db      	ldr	r3, [r3, #12]
 80071ac:	68db      	ldr	r3, [r3, #12]
 80071ae:	617b      	str	r3, [r7, #20]

	/* Remove the timer from the list of active timers.  A check has already
	been performed to ensure the list is not empty. */
	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 80071b0:	697b      	ldr	r3, [r7, #20]
 80071b2:	3304      	adds	r3, #4
 80071b4:	4618      	mov	r0, r3
 80071b6:	f7fe f9ed 	bl	8005594 <uxListRemove>
	traceTIMER_EXPIRED( pxTimer );

	/* If the timer is an auto-reload timer then calculate the next
	expiry time and re-insert the timer in the list of active timers. */
	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 80071ba:	697b      	ldr	r3, [r7, #20]
 80071bc:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80071c0:	f003 0304 	and.w	r3, r3, #4
 80071c4:	2b00      	cmp	r3, #0
 80071c6:	d023      	beq.n	8007210 <prvProcessExpiredTimer+0x74>
	{
		/* The timer is inserted into a list using a time relative to anything
		other than the current time.  It will therefore be inserted into the
		correct list relative to the time this task thinks it is now. */
		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
 80071c8:	697b      	ldr	r3, [r7, #20]
 80071ca:	699a      	ldr	r2, [r3, #24]
 80071cc:	687b      	ldr	r3, [r7, #4]
 80071ce:	18d1      	adds	r1, r2, r3
 80071d0:	687b      	ldr	r3, [r7, #4]
 80071d2:	683a      	ldr	r2, [r7, #0]
 80071d4:	6978      	ldr	r0, [r7, #20]
 80071d6:	f000 f8d5 	bl	8007384 <prvInsertTimerInActiveList>
 80071da:	4603      	mov	r3, r0
 80071dc:	2b00      	cmp	r3, #0
 80071de:	d020      	beq.n	8007222 <prvProcessExpiredTimer+0x86>
		{
			/* The timer expired before it was added to the active timer
			list.  Reload it now.  */
			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 80071e0:	2300      	movs	r3, #0
 80071e2:	9300      	str	r3, [sp, #0]
 80071e4:	2300      	movs	r3, #0
 80071e6:	687a      	ldr	r2, [r7, #4]
 80071e8:	2100      	movs	r1, #0
 80071ea:	6978      	ldr	r0, [r7, #20]
 80071ec:	f7ff ff88 	bl	8007100 <xTimerGenericCommand>
 80071f0:	6138      	str	r0, [r7, #16]
			configASSERT( xResult );
 80071f2:	693b      	ldr	r3, [r7, #16]
 80071f4:	2b00      	cmp	r3, #0
 80071f6:	d114      	bne.n	8007222 <prvProcessExpiredTimer+0x86>
	__asm volatile
 80071f8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80071fc:	f383 8811 	msr	BASEPRI, r3
 8007200:	f3bf 8f6f 	isb	sy
 8007204:	f3bf 8f4f 	dsb	sy
 8007208:	60fb      	str	r3, [r7, #12]
}
 800720a:	bf00      	nop
 800720c:	bf00      	nop
 800720e:	e7fd      	b.n	800720c <prvProcessExpiredTimer+0x70>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8007210:	697b      	ldr	r3, [r7, #20]
 8007212:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8007216:	f023 0301 	bic.w	r3, r3, #1
 800721a:	b2da      	uxtb	r2, r3
 800721c:	697b      	ldr	r3, [r7, #20]
 800721e:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
		mtCOVERAGE_TEST_MARKER();
	}

	/* Call the timer callback. */
	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8007222:	697b      	ldr	r3, [r7, #20]
 8007224:	6a1b      	ldr	r3, [r3, #32]
 8007226:	6978      	ldr	r0, [r7, #20]
 8007228:	4798      	blx	r3
}
 800722a:	bf00      	nop
 800722c:	3718      	adds	r7, #24
 800722e:	46bd      	mov	sp, r7
 8007230:	bd80      	pop	{r7, pc}
 8007232:	bf00      	nop
 8007234:	200014f0 	.word	0x200014f0

08007238 <prvTimerTask>:
/*-----------------------------------------------------------*/

static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
 8007238:	b580      	push	{r7, lr}
 800723a:	b084      	sub	sp, #16
 800723c:	af00      	add	r7, sp, #0
 800723e:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* Query the timers list to see if it contains any timers, and if so,
		obtain the time at which the next timer will expire. */
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8007240:	f107 0308 	add.w	r3, r7, #8
 8007244:	4618      	mov	r0, r3
 8007246:	f000 f859 	bl	80072fc <prvGetNextExpireTime>
 800724a:	60f8      	str	r0, [r7, #12]

		/* If a timer has expired, process it.  Otherwise, block this task
		until either a timer does expire, or a command is received. */
		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
 800724c:	68bb      	ldr	r3, [r7, #8]
 800724e:	4619      	mov	r1, r3
 8007250:	68f8      	ldr	r0, [r7, #12]
 8007252:	f000 f805 	bl	8007260 <prvProcessTimerOrBlockTask>

		/* Empty the command queue. */
		prvProcessReceivedCommands();
 8007256:	f000 f8d7 	bl	8007408 <prvProcessReceivedCommands>
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 800725a:	bf00      	nop
 800725c:	e7f0      	b.n	8007240 <prvTimerTask+0x8>
	...

08007260 <prvProcessTimerOrBlockTask>:
	}
}
/*-----------------------------------------------------------*/

static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
 8007260:	b580      	push	{r7, lr}
 8007262:	b084      	sub	sp, #16
 8007264:	af00      	add	r7, sp, #0
 8007266:	6078      	str	r0, [r7, #4]
 8007268:	6039      	str	r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;

	vTaskSuspendAll();
 800726a:	f7ff f91b 	bl	80064a4 <vTaskSuspendAll>
		/* Obtain the time now to make an assessment as to whether the timer
		has expired or not.  If obtaining the time causes the lists to switch
		then don't process this timer as any timers that remained in the list
		when the lists were switched will have been processed within the
		prvSampleTimeNow() function. */
		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 800726e:	f107 0308 	add.w	r3, r7, #8
 8007272:	4618      	mov	r0, r3
 8007274:	f000 f866 	bl	8007344 <prvSampleTimeNow>
 8007278:	60f8      	str	r0, [r7, #12]
		if( xTimerListsWereSwitched == pdFALSE )
 800727a:	68bb      	ldr	r3, [r7, #8]
 800727c:	2b00      	cmp	r3, #0
 800727e:	d130      	bne.n	80072e2 <prvProcessTimerOrBlockTask+0x82>
		{
			/* The tick count has not overflowed, has the timer expired? */
			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
 8007280:	683b      	ldr	r3, [r7, #0]
 8007282:	2b00      	cmp	r3, #0
 8007284:	d10a      	bne.n	800729c <prvProcessTimerOrBlockTask+0x3c>
 8007286:	687a      	ldr	r2, [r7, #4]
 8007288:	68fb      	ldr	r3, [r7, #12]
 800728a:	429a      	cmp	r2, r3
 800728c:	d806      	bhi.n	800729c <prvProcessTimerOrBlockTask+0x3c>
			{
				( void ) xTaskResumeAll();
 800728e:	f7ff f917 	bl	80064c0 <xTaskResumeAll>
				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
 8007292:	68f9      	ldr	r1, [r7, #12]
 8007294:	6878      	ldr	r0, [r7, #4]
 8007296:	f7ff ff81 	bl	800719c <prvProcessExpiredTimer>
		else
		{
			( void ) xTaskResumeAll();
		}
	}
}
 800729a:	e024      	b.n	80072e6 <prvProcessTimerOrBlockTask+0x86>
				if( xListWasEmpty != pdFALSE )
 800729c:	683b      	ldr	r3, [r7, #0]
 800729e:	2b00      	cmp	r3, #0
 80072a0:	d008      	beq.n	80072b4 <prvProcessTimerOrBlockTask+0x54>
					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
 80072a2:	4b13      	ldr	r3, [pc, #76]	@ (80072f0 <prvProcessTimerOrBlockTask+0x90>)
 80072a4:	681b      	ldr	r3, [r3, #0]
 80072a6:	681b      	ldr	r3, [r3, #0]
 80072a8:	2b00      	cmp	r3, #0
 80072aa:	d101      	bne.n	80072b0 <prvProcessTimerOrBlockTask+0x50>
 80072ac:	2301      	movs	r3, #1
 80072ae:	e000      	b.n	80072b2 <prvProcessTimerOrBlockTask+0x52>
 80072b0:	2300      	movs	r3, #0
 80072b2:	603b      	str	r3, [r7, #0]
				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
 80072b4:	4b0f      	ldr	r3, [pc, #60]	@ (80072f4 <prvProcessTimerOrBlockTask+0x94>)
 80072b6:	6818      	ldr	r0, [r3, #0]
 80072b8:	687a      	ldr	r2, [r7, #4]
 80072ba:	68fb      	ldr	r3, [r7, #12]
 80072bc:	1ad3      	subs	r3, r2, r3
 80072be:	683a      	ldr	r2, [r7, #0]
 80072c0:	4619      	mov	r1, r3
 80072c2:	f7fe fe57 	bl	8005f74 <vQueueWaitForMessageRestricted>
				if( xTaskResumeAll() == pdFALSE )
 80072c6:	f7ff f8fb 	bl	80064c0 <xTaskResumeAll>
 80072ca:	4603      	mov	r3, r0
 80072cc:	2b00      	cmp	r3, #0
 80072ce:	d10a      	bne.n	80072e6 <prvProcessTimerOrBlockTask+0x86>
					portYIELD_WITHIN_API();
 80072d0:	4b09      	ldr	r3, [pc, #36]	@ (80072f8 <prvProcessTimerOrBlockTask+0x98>)
 80072d2:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80072d6:	601a      	str	r2, [r3, #0]
 80072d8:	f3bf 8f4f 	dsb	sy
 80072dc:	f3bf 8f6f 	isb	sy
}
 80072e0:	e001      	b.n	80072e6 <prvProcessTimerOrBlockTask+0x86>
			( void ) xTaskResumeAll();
 80072e2:	f7ff f8ed 	bl	80064c0 <xTaskResumeAll>
}
 80072e6:	bf00      	nop
 80072e8:	3710      	adds	r7, #16
 80072ea:	46bd      	mov	sp, r7
 80072ec:	bd80      	pop	{r7, pc}
 80072ee:	bf00      	nop
 80072f0:	200014f4 	.word	0x200014f4
 80072f4:	200014f8 	.word	0x200014f8
 80072f8:	e000ed04 	.word	0xe000ed04

080072fc <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/

static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
 80072fc:	b480      	push	{r7}
 80072fe:	b085      	sub	sp, #20
 8007300:	af00      	add	r7, sp, #0
 8007302:	6078      	str	r0, [r7, #4]
	the timer with the nearest expiry time will expire.  If there are no
	active timers then just set the next expire time to 0.  That will cause
	this task to unblock when the tick count overflows, at which point the
	timer lists will be switched and the next expiry time can be
	re-assessed.  */
	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
 8007304:	4b0e      	ldr	r3, [pc, #56]	@ (8007340 <prvGetNextExpireTime+0x44>)
 8007306:	681b      	ldr	r3, [r3, #0]
 8007308:	681b      	ldr	r3, [r3, #0]
 800730a:	2b00      	cmp	r3, #0
 800730c:	d101      	bne.n	8007312 <prvGetNextExpireTime+0x16>
 800730e:	2201      	movs	r2, #1
 8007310:	e000      	b.n	8007314 <prvGetNextExpireTime+0x18>
 8007312:	2200      	movs	r2, #0
 8007314:	687b      	ldr	r3, [r7, #4]
 8007316:	601a      	str	r2, [r3, #0]
	if( *pxListWasEmpty == pdFALSE )
 8007318:	687b      	ldr	r3, [r7, #4]
 800731a:	681b      	ldr	r3, [r3, #0]
 800731c:	2b00      	cmp	r3, #0
 800731e:	d105      	bne.n	800732c <prvGetNextExpireTime+0x30>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 8007320:	4b07      	ldr	r3, [pc, #28]	@ (8007340 <prvGetNextExpireTime+0x44>)
 8007322:	681b      	ldr	r3, [r3, #0]
 8007324:	68db      	ldr	r3, [r3, #12]
 8007326:	681b      	ldr	r3, [r3, #0]
 8007328:	60fb      	str	r3, [r7, #12]
 800732a:	e001      	b.n	8007330 <prvGetNextExpireTime+0x34>
	}
	else
	{
		/* Ensure the task unblocks when the tick count rolls over. */
		xNextExpireTime = ( TickType_t ) 0U;
 800732c:	2300      	movs	r3, #0
 800732e:	60fb      	str	r3, [r7, #12]
	}

	return xNextExpireTime;
 8007330:	68fb      	ldr	r3, [r7, #12]
}
 8007332:	4618      	mov	r0, r3
 8007334:	3714      	adds	r7, #20
 8007336:	46bd      	mov	sp, r7
 8007338:	f85d 7b04 	ldr.w	r7, [sp], #4
 800733c:	4770      	bx	lr
 800733e:	bf00      	nop
 8007340:	200014f0 	.word	0x200014f0

08007344 <prvSampleTimeNow>:
/*-----------------------------------------------------------*/

static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
 8007344:	b580      	push	{r7, lr}
 8007346:	b084      	sub	sp, #16
 8007348:	af00      	add	r7, sp, #0
 800734a:	6078      	str	r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */

	xTimeNow = xTaskGetTickCount();
 800734c:	f7ff f956 	bl	80065fc <xTaskGetTickCount>
 8007350:	60f8      	str	r0, [r7, #12]

	if( xTimeNow < xLastTime )
 8007352:	4b0b      	ldr	r3, [pc, #44]	@ (8007380 <prvSampleTimeNow+0x3c>)
 8007354:	681b      	ldr	r3, [r3, #0]
 8007356:	68fa      	ldr	r2, [r7, #12]
 8007358:	429a      	cmp	r2, r3
 800735a:	d205      	bcs.n	8007368 <prvSampleTimeNow+0x24>
	{
		prvSwitchTimerLists();
 800735c:	f000 f93a 	bl	80075d4 <prvSwitchTimerLists>
		*pxTimerListsWereSwitched = pdTRUE;
 8007360:	687b      	ldr	r3, [r7, #4]
 8007362:	2201      	movs	r2, #1
 8007364:	601a      	str	r2, [r3, #0]
 8007366:	e002      	b.n	800736e <prvSampleTimeNow+0x2a>
	}
	else
	{
		*pxTimerListsWereSwitched = pdFALSE;
 8007368:	687b      	ldr	r3, [r7, #4]
 800736a:	2200      	movs	r2, #0
 800736c:	601a      	str	r2, [r3, #0]
	}

	xLastTime = xTimeNow;
 800736e:	4a04      	ldr	r2, [pc, #16]	@ (8007380 <prvSampleTimeNow+0x3c>)
 8007370:	68fb      	ldr	r3, [r7, #12]
 8007372:	6013      	str	r3, [r2, #0]

	return xTimeNow;
 8007374:	68fb      	ldr	r3, [r7, #12]
}
 8007376:	4618      	mov	r0, r3
 8007378:	3710      	adds	r7, #16
 800737a:	46bd      	mov	sp, r7
 800737c:	bd80      	pop	{r7, pc}
 800737e:	bf00      	nop
 8007380:	20001500 	.word	0x20001500

08007384 <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/

static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
 8007384:	b580      	push	{r7, lr}
 8007386:	b086      	sub	sp, #24
 8007388:	af00      	add	r7, sp, #0
 800738a:	60f8      	str	r0, [r7, #12]
 800738c:	60b9      	str	r1, [r7, #8]
 800738e:	607a      	str	r2, [r7, #4]
 8007390:	603b      	str	r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
 8007392:	2300      	movs	r3, #0
 8007394:	617b      	str	r3, [r7, #20]

	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
 8007396:	68fb      	ldr	r3, [r7, #12]
 8007398:	68ba      	ldr	r2, [r7, #8]
 800739a:	605a      	str	r2, [r3, #4]
	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 800739c:	68fb      	ldr	r3, [r7, #12]
 800739e:	68fa      	ldr	r2, [r7, #12]
 80073a0:	611a      	str	r2, [r3, #16]

	if( xNextExpiryTime <= xTimeNow )
 80073a2:	68ba      	ldr	r2, [r7, #8]
 80073a4:	687b      	ldr	r3, [r7, #4]
 80073a6:	429a      	cmp	r2, r3
 80073a8:	d812      	bhi.n	80073d0 <prvInsertTimerInActiveList+0x4c>
	{
		/* Has the expiry time elapsed between the command to start/reset a
		timer was issued, and the time the command was processed? */
		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80073aa:	687a      	ldr	r2, [r7, #4]
 80073ac:	683b      	ldr	r3, [r7, #0]
 80073ae:	1ad2      	subs	r2, r2, r3
 80073b0:	68fb      	ldr	r3, [r7, #12]
 80073b2:	699b      	ldr	r3, [r3, #24]
 80073b4:	429a      	cmp	r2, r3
 80073b6:	d302      	bcc.n	80073be <prvInsertTimerInActiveList+0x3a>
		{
			/* The time between a command being issued and the command being
			processed actually exceeds the timers period.  */
			xProcessTimerNow = pdTRUE;
 80073b8:	2301      	movs	r3, #1
 80073ba:	617b      	str	r3, [r7, #20]
 80073bc:	e01b      	b.n	80073f6 <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
 80073be:	4b10      	ldr	r3, [pc, #64]	@ (8007400 <prvInsertTimerInActiveList+0x7c>)
 80073c0:	681a      	ldr	r2, [r3, #0]
 80073c2:	68fb      	ldr	r3, [r7, #12]
 80073c4:	3304      	adds	r3, #4
 80073c6:	4619      	mov	r1, r3
 80073c8:	4610      	mov	r0, r2
 80073ca:	f7fe f8aa 	bl	8005522 <vListInsert>
 80073ce:	e012      	b.n	80073f6 <prvInsertTimerInActiveList+0x72>
		}
	}
	else
	{
		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
 80073d0:	687a      	ldr	r2, [r7, #4]
 80073d2:	683b      	ldr	r3, [r7, #0]
 80073d4:	429a      	cmp	r2, r3
 80073d6:	d206      	bcs.n	80073e6 <prvInsertTimerInActiveList+0x62>
 80073d8:	68ba      	ldr	r2, [r7, #8]
 80073da:	683b      	ldr	r3, [r7, #0]
 80073dc:	429a      	cmp	r2, r3
 80073de:	d302      	bcc.n	80073e6 <prvInsertTimerInActiveList+0x62>
		{
			/* If, since the command was issued, the tick count has overflowed
			but the expiry time has not, then the timer must have already passed
			its expiry time and should be processed immediately. */
			xProcessTimerNow = pdTRUE;
 80073e0:	2301      	movs	r3, #1
 80073e2:	617b      	str	r3, [r7, #20]
 80073e4:	e007      	b.n	80073f6 <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 80073e6:	4b07      	ldr	r3, [pc, #28]	@ (8007404 <prvInsertTimerInActiveList+0x80>)
 80073e8:	681a      	ldr	r2, [r3, #0]
 80073ea:	68fb      	ldr	r3, [r7, #12]
 80073ec:	3304      	adds	r3, #4
 80073ee:	4619      	mov	r1, r3
 80073f0:	4610      	mov	r0, r2
 80073f2:	f7fe f896 	bl	8005522 <vListInsert>
		}
	}

	return xProcessTimerNow;
 80073f6:	697b      	ldr	r3, [r7, #20]
}
 80073f8:	4618      	mov	r0, r3
 80073fa:	3718      	adds	r7, #24
 80073fc:	46bd      	mov	sp, r7
 80073fe:	bd80      	pop	{r7, pc}
 8007400:	200014f4 	.word	0x200014f4
 8007404:	200014f0 	.word	0x200014f0

08007408 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/

static void	prvProcessReceivedCommands( void )
{
 8007408:	b580      	push	{r7, lr}
 800740a:	b08e      	sub	sp, #56	@ 0x38
 800740c:	af02      	add	r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;

	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 800740e:	e0ce      	b.n	80075ae <prvProcessReceivedCommands+0x1a6>
	{
		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
		{
			/* Negative commands are pended function calls rather than timer
			commands. */
			if( xMessage.xMessageID < ( BaseType_t ) 0 )
 8007410:	687b      	ldr	r3, [r7, #4]
 8007412:	2b00      	cmp	r3, #0
 8007414:	da19      	bge.n	800744a <prvProcessReceivedCommands+0x42>
			{
				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
 8007416:	1d3b      	adds	r3, r7, #4
 8007418:	3304      	adds	r3, #4
 800741a:	62fb      	str	r3, [r7, #44]	@ 0x2c

				/* The timer uses the xCallbackParameters member to request a
				callback be executed.  Check the callback is not NULL. */
				configASSERT( pxCallback );
 800741c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800741e:	2b00      	cmp	r3, #0
 8007420:	d10b      	bne.n	800743a <prvProcessReceivedCommands+0x32>
	__asm volatile
 8007422:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007426:	f383 8811 	msr	BASEPRI, r3
 800742a:	f3bf 8f6f 	isb	sy
 800742e:	f3bf 8f4f 	dsb	sy
 8007432:	61fb      	str	r3, [r7, #28]
}
 8007434:	bf00      	nop
 8007436:	bf00      	nop
 8007438:	e7fd      	b.n	8007436 <prvProcessReceivedCommands+0x2e>

				/* Call the function. */
				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
 800743a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800743c:	681b      	ldr	r3, [r3, #0]
 800743e:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8007440:	6850      	ldr	r0, [r2, #4]
 8007442:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8007444:	6892      	ldr	r2, [r2, #8]
 8007446:	4611      	mov	r1, r2
 8007448:	4798      	blx	r3
		}
		#endif /* INCLUDE_xTimerPendFunctionCall */

		/* Commands that are positive are timer commands rather than pended
		function calls. */
		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
 800744a:	687b      	ldr	r3, [r7, #4]
 800744c:	2b00      	cmp	r3, #0
 800744e:	f2c0 80ae 	blt.w	80075ae <prvProcessReceivedCommands+0x1a6>
		{
			/* The messages uses the xTimerParameters member to work on a
			software timer. */
			pxTimer = xMessage.u.xTimerParameters.pxTimer;
 8007452:	68fb      	ldr	r3, [r7, #12]
 8007454:	62bb      	str	r3, [r7, #40]	@ 0x28

			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
 8007456:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8007458:	695b      	ldr	r3, [r3, #20]
 800745a:	2b00      	cmp	r3, #0
 800745c:	d004      	beq.n	8007468 <prvProcessReceivedCommands+0x60>
			{
				/* The timer is in a list, remove it. */
				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 800745e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8007460:	3304      	adds	r3, #4
 8007462:	4618      	mov	r0, r3
 8007464:	f7fe f896 	bl	8005594 <uxListRemove>
			it must be present in the function call.  prvSampleTimeNow() must be
			called after the message is received from xTimerQueue so there is no
			possibility of a higher priority task adding a message to the message
			queue with a time that is ahead of the timer daemon task (because it
			pre-empted the timer daemon task after the xTimeNow value was set). */
			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8007468:	463b      	mov	r3, r7
 800746a:	4618      	mov	r0, r3
 800746c:	f7ff ff6a 	bl	8007344 <prvSampleTimeNow>
 8007470:	6278      	str	r0, [r7, #36]	@ 0x24

			switch( xMessage.xMessageID )
 8007472:	687b      	ldr	r3, [r7, #4]
 8007474:	2b09      	cmp	r3, #9
 8007476:	f200 8097 	bhi.w	80075a8 <prvProcessReceivedCommands+0x1a0>
 800747a:	a201      	add	r2, pc, #4	@ (adr r2, 8007480 <prvProcessReceivedCommands+0x78>)
 800747c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8007480:	080074a9 	.word	0x080074a9
 8007484:	080074a9 	.word	0x080074a9
 8007488:	080074a9 	.word	0x080074a9
 800748c:	0800751f 	.word	0x0800751f
 8007490:	08007533 	.word	0x08007533
 8007494:	0800757f 	.word	0x0800757f
 8007498:	080074a9 	.word	0x080074a9
 800749c:	080074a9 	.word	0x080074a9
 80074a0:	0800751f 	.word	0x0800751f
 80074a4:	08007533 	.word	0x08007533
				case tmrCOMMAND_START_FROM_ISR :
				case tmrCOMMAND_RESET :
				case tmrCOMMAND_RESET_FROM_ISR :
				case tmrCOMMAND_START_DONT_TRACE :
					/* Start or restart a timer. */
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 80074a8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80074aa:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80074ae:	f043 0301 	orr.w	r3, r3, #1
 80074b2:	b2da      	uxtb	r2, r3
 80074b4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80074b6:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
 80074ba:	68ba      	ldr	r2, [r7, #8]
 80074bc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80074be:	699b      	ldr	r3, [r3, #24]
 80074c0:	18d1      	adds	r1, r2, r3
 80074c2:	68bb      	ldr	r3, [r7, #8]
 80074c4:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80074c6:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 80074c8:	f7ff ff5c 	bl	8007384 <prvInsertTimerInActiveList>
 80074cc:	4603      	mov	r3, r0
 80074ce:	2b00      	cmp	r3, #0
 80074d0:	d06c      	beq.n	80075ac <prvProcessReceivedCommands+0x1a4>
					{
						/* The timer expired before it was added to the active
						timer list.  Process it now. */
						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 80074d2:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80074d4:	6a1b      	ldr	r3, [r3, #32]
 80074d6:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 80074d8:	4798      	blx	r3
						traceTIMER_EXPIRED( pxTimer );

						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 80074da:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80074dc:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80074e0:	f003 0304 	and.w	r3, r3, #4
 80074e4:	2b00      	cmp	r3, #0
 80074e6:	d061      	beq.n	80075ac <prvProcessReceivedCommands+0x1a4>
						{
							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
 80074e8:	68ba      	ldr	r2, [r7, #8]
 80074ea:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80074ec:	699b      	ldr	r3, [r3, #24]
 80074ee:	441a      	add	r2, r3
 80074f0:	2300      	movs	r3, #0
 80074f2:	9300      	str	r3, [sp, #0]
 80074f4:	2300      	movs	r3, #0
 80074f6:	2100      	movs	r1, #0
 80074f8:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 80074fa:	f7ff fe01 	bl	8007100 <xTimerGenericCommand>
 80074fe:	6238      	str	r0, [r7, #32]
							configASSERT( xResult );
 8007500:	6a3b      	ldr	r3, [r7, #32]
 8007502:	2b00      	cmp	r3, #0
 8007504:	d152      	bne.n	80075ac <prvProcessReceivedCommands+0x1a4>
	__asm volatile
 8007506:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800750a:	f383 8811 	msr	BASEPRI, r3
 800750e:	f3bf 8f6f 	isb	sy
 8007512:	f3bf 8f4f 	dsb	sy
 8007516:	61bb      	str	r3, [r7, #24]
}
 8007518:	bf00      	nop
 800751a:	bf00      	nop
 800751c:	e7fd      	b.n	800751a <prvProcessReceivedCommands+0x112>
					break;

				case tmrCOMMAND_STOP :
				case tmrCOMMAND_STOP_FROM_ISR :
					/* The timer has already been removed from the active list. */
					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 800751e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8007520:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8007524:	f023 0301 	bic.w	r3, r3, #1
 8007528:	b2da      	uxtb	r2, r3
 800752a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800752c:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					break;
 8007530:	e03d      	b.n	80075ae <prvProcessReceivedCommands+0x1a6>

				case tmrCOMMAND_CHANGE_PERIOD :
				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 8007532:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8007534:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8007538:	f043 0301 	orr.w	r3, r3, #1
 800753c:	b2da      	uxtb	r2, r3
 800753e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8007540:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
 8007544:	68ba      	ldr	r2, [r7, #8]
 8007546:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8007548:	619a      	str	r2, [r3, #24]
					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
 800754a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800754c:	699b      	ldr	r3, [r3, #24]
 800754e:	2b00      	cmp	r3, #0
 8007550:	d10b      	bne.n	800756a <prvProcessReceivedCommands+0x162>
	__asm volatile
 8007552:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007556:	f383 8811 	msr	BASEPRI, r3
 800755a:	f3bf 8f6f 	isb	sy
 800755e:	f3bf 8f4f 	dsb	sy
 8007562:	617b      	str	r3, [r7, #20]
}
 8007564:	bf00      	nop
 8007566:	bf00      	nop
 8007568:	e7fd      	b.n	8007566 <prvProcessReceivedCommands+0x15e>
					be longer or shorter than the old one.  The command time is
					therefore set to the current time, and as the period cannot
					be zero the next expiry time can only be in the future,
					meaning (unlike for the xTimerStart() case above) there is
					no fail case that needs to be handled here. */
					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
 800756a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800756c:	699a      	ldr	r2, [r3, #24]
 800756e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007570:	18d1      	adds	r1, r2, r3
 8007572:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007574:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8007576:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8007578:	f7ff ff04 	bl	8007384 <prvInsertTimerInActiveList>
					break;
 800757c:	e017      	b.n	80075ae <prvProcessReceivedCommands+0x1a6>
					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
					{
						/* The timer has already been removed from the active list,
						just free up the memory if the memory was dynamically
						allocated. */
						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
 800757e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8007580:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8007584:	f003 0302 	and.w	r3, r3, #2
 8007588:	2b00      	cmp	r3, #0
 800758a:	d103      	bne.n	8007594 <prvProcessReceivedCommands+0x18c>
						{
							vPortFree( pxTimer );
 800758c:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 800758e:	f000 fbeb 	bl	8007d68 <vPortFree>
						no need to free the memory - just mark the timer as
						"not active". */
						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
					}
					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
					break;
 8007592:	e00c      	b.n	80075ae <prvProcessReceivedCommands+0x1a6>
							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8007594:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8007596:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 800759a:	f023 0301 	bic.w	r3, r3, #1
 800759e:	b2da      	uxtb	r2, r3
 80075a0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80075a2:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					break;
 80075a6:	e002      	b.n	80075ae <prvProcessReceivedCommands+0x1a6>

				default	:
					/* Don't expect to get here. */
					break;
 80075a8:	bf00      	nop
 80075aa:	e000      	b.n	80075ae <prvProcessReceivedCommands+0x1a6>
					break;
 80075ac:	bf00      	nop
	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 80075ae:	4b08      	ldr	r3, [pc, #32]	@ (80075d0 <prvProcessReceivedCommands+0x1c8>)
 80075b0:	681b      	ldr	r3, [r3, #0]
 80075b2:	1d39      	adds	r1, r7, #4
 80075b4:	2200      	movs	r2, #0
 80075b6:	4618      	mov	r0, r3
 80075b8:	f7fe fac0 	bl	8005b3c <xQueueReceive>
 80075bc:	4603      	mov	r3, r0
 80075be:	2b00      	cmp	r3, #0
 80075c0:	f47f af26 	bne.w	8007410 <prvProcessReceivedCommands+0x8>
			}
		}
	}
}
 80075c4:	bf00      	nop
 80075c6:	bf00      	nop
 80075c8:	3730      	adds	r7, #48	@ 0x30
 80075ca:	46bd      	mov	sp, r7
 80075cc:	bd80      	pop	{r7, pc}
 80075ce:	bf00      	nop
 80075d0:	200014f8 	.word	0x200014f8

080075d4 <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/

static void prvSwitchTimerLists( void )
{
 80075d4:	b580      	push	{r7, lr}
 80075d6:	b088      	sub	sp, #32
 80075d8:	af02      	add	r7, sp, #8

	/* The tick count has overflowed.  The timer lists must be switched.
	If there are any timers still referenced from the current timer list
	then they must have expired and should be processed before the lists
	are switched. */
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 80075da:	e049      	b.n	8007670 <prvSwitchTimerLists+0x9c>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 80075dc:	4b2e      	ldr	r3, [pc, #184]	@ (8007698 <prvSwitchTimerLists+0xc4>)
 80075de:	681b      	ldr	r3, [r3, #0]
 80075e0:	68db      	ldr	r3, [r3, #12]
 80075e2:	681b      	ldr	r3, [r3, #0]
 80075e4:	613b      	str	r3, [r7, #16]

		/* Remove the timer from the list. */
		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80075e6:	4b2c      	ldr	r3, [pc, #176]	@ (8007698 <prvSwitchTimerLists+0xc4>)
 80075e8:	681b      	ldr	r3, [r3, #0]
 80075ea:	68db      	ldr	r3, [r3, #12]
 80075ec:	68db      	ldr	r3, [r3, #12]
 80075ee:	60fb      	str	r3, [r7, #12]
		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 80075f0:	68fb      	ldr	r3, [r7, #12]
 80075f2:	3304      	adds	r3, #4
 80075f4:	4618      	mov	r0, r3
 80075f6:	f7fd ffcd 	bl	8005594 <uxListRemove>
		traceTIMER_EXPIRED( pxTimer );

		/* Execute its callback, then send a command to restart the timer if
		it is an auto-reload timer.  It cannot be restarted here as the lists
		have not yet been switched. */
		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 80075fa:	68fb      	ldr	r3, [r7, #12]
 80075fc:	6a1b      	ldr	r3, [r3, #32]
 80075fe:	68f8      	ldr	r0, [r7, #12]
 8007600:	4798      	blx	r3

		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8007602:	68fb      	ldr	r3, [r7, #12]
 8007604:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8007608:	f003 0304 	and.w	r3, r3, #4
 800760c:	2b00      	cmp	r3, #0
 800760e:	d02f      	beq.n	8007670 <prvSwitchTimerLists+0x9c>
			the timer going into the same timer list then it has already expired
			and the timer should be re-inserted into the current list so it is
			processed again within this loop.  Otherwise a command should be sent
			to restart the timer to ensure it is only inserted into a list after
			the lists have been swapped. */
			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
 8007610:	68fb      	ldr	r3, [r7, #12]
 8007612:	699b      	ldr	r3, [r3, #24]
 8007614:	693a      	ldr	r2, [r7, #16]
 8007616:	4413      	add	r3, r2
 8007618:	60bb      	str	r3, [r7, #8]
			if( xReloadTime > xNextExpireTime )
 800761a:	68ba      	ldr	r2, [r7, #8]
 800761c:	693b      	ldr	r3, [r7, #16]
 800761e:	429a      	cmp	r2, r3
 8007620:	d90e      	bls.n	8007640 <prvSwitchTimerLists+0x6c>
			{
				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
 8007622:	68fb      	ldr	r3, [r7, #12]
 8007624:	68ba      	ldr	r2, [r7, #8]
 8007626:	605a      	str	r2, [r3, #4]
				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 8007628:	68fb      	ldr	r3, [r7, #12]
 800762a:	68fa      	ldr	r2, [r7, #12]
 800762c:	611a      	str	r2, [r3, #16]
				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 800762e:	4b1a      	ldr	r3, [pc, #104]	@ (8007698 <prvSwitchTimerLists+0xc4>)
 8007630:	681a      	ldr	r2, [r3, #0]
 8007632:	68fb      	ldr	r3, [r7, #12]
 8007634:	3304      	adds	r3, #4
 8007636:	4619      	mov	r1, r3
 8007638:	4610      	mov	r0, r2
 800763a:	f7fd ff72 	bl	8005522 <vListInsert>
 800763e:	e017      	b.n	8007670 <prvSwitchTimerLists+0x9c>
			}
			else
			{
				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 8007640:	2300      	movs	r3, #0
 8007642:	9300      	str	r3, [sp, #0]
 8007644:	2300      	movs	r3, #0
 8007646:	693a      	ldr	r2, [r7, #16]
 8007648:	2100      	movs	r1, #0
 800764a:	68f8      	ldr	r0, [r7, #12]
 800764c:	f7ff fd58 	bl	8007100 <xTimerGenericCommand>
 8007650:	6078      	str	r0, [r7, #4]
				configASSERT( xResult );
 8007652:	687b      	ldr	r3, [r7, #4]
 8007654:	2b00      	cmp	r3, #0
 8007656:	d10b      	bne.n	8007670 <prvSwitchTimerLists+0x9c>
	__asm volatile
 8007658:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800765c:	f383 8811 	msr	BASEPRI, r3
 8007660:	f3bf 8f6f 	isb	sy
 8007664:	f3bf 8f4f 	dsb	sy
 8007668:	603b      	str	r3, [r7, #0]
}
 800766a:	bf00      	nop
 800766c:	bf00      	nop
 800766e:	e7fd      	b.n	800766c <prvSwitchTimerLists+0x98>
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 8007670:	4b09      	ldr	r3, [pc, #36]	@ (8007698 <prvSwitchTimerLists+0xc4>)
 8007672:	681b      	ldr	r3, [r3, #0]
 8007674:	681b      	ldr	r3, [r3, #0]
 8007676:	2b00      	cmp	r3, #0
 8007678:	d1b0      	bne.n	80075dc <prvSwitchTimerLists+0x8>
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxTemp = pxCurrentTimerList;
 800767a:	4b07      	ldr	r3, [pc, #28]	@ (8007698 <prvSwitchTimerLists+0xc4>)
 800767c:	681b      	ldr	r3, [r3, #0]
 800767e:	617b      	str	r3, [r7, #20]
	pxCurrentTimerList = pxOverflowTimerList;
 8007680:	4b06      	ldr	r3, [pc, #24]	@ (800769c <prvSwitchTimerLists+0xc8>)
 8007682:	681b      	ldr	r3, [r3, #0]
 8007684:	4a04      	ldr	r2, [pc, #16]	@ (8007698 <prvSwitchTimerLists+0xc4>)
 8007686:	6013      	str	r3, [r2, #0]
	pxOverflowTimerList = pxTemp;
 8007688:	4a04      	ldr	r2, [pc, #16]	@ (800769c <prvSwitchTimerLists+0xc8>)
 800768a:	697b      	ldr	r3, [r7, #20]
 800768c:	6013      	str	r3, [r2, #0]
}
 800768e:	bf00      	nop
 8007690:	3718      	adds	r7, #24
 8007692:	46bd      	mov	sp, r7
 8007694:	bd80      	pop	{r7, pc}
 8007696:	bf00      	nop
 8007698:	200014f0 	.word	0x200014f0
 800769c:	200014f4 	.word	0x200014f4

080076a0 <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/

static void prvCheckForValidListAndQueue( void )
{
 80076a0:	b580      	push	{r7, lr}
 80076a2:	b082      	sub	sp, #8
 80076a4:	af02      	add	r7, sp, #8
	/* Check that the list from which active timers are referenced, and the
	queue used to communicate with the timer service, have been
	initialised. */
	taskENTER_CRITICAL();
 80076a6:	f000 f96f 	bl	8007988 <vPortEnterCritical>
	{
		if( xTimerQueue == NULL )
 80076aa:	4b15      	ldr	r3, [pc, #84]	@ (8007700 <prvCheckForValidListAndQueue+0x60>)
 80076ac:	681b      	ldr	r3, [r3, #0]
 80076ae:	2b00      	cmp	r3, #0
 80076b0:	d120      	bne.n	80076f4 <prvCheckForValidListAndQueue+0x54>
		{
			vListInitialise( &xActiveTimerList1 );
 80076b2:	4814      	ldr	r0, [pc, #80]	@ (8007704 <prvCheckForValidListAndQueue+0x64>)
 80076b4:	f7fd fee4 	bl	8005480 <vListInitialise>
			vListInitialise( &xActiveTimerList2 );
 80076b8:	4813      	ldr	r0, [pc, #76]	@ (8007708 <prvCheckForValidListAndQueue+0x68>)
 80076ba:	f7fd fee1 	bl	8005480 <vListInitialise>
			pxCurrentTimerList = &xActiveTimerList1;
 80076be:	4b13      	ldr	r3, [pc, #76]	@ (800770c <prvCheckForValidListAndQueue+0x6c>)
 80076c0:	4a10      	ldr	r2, [pc, #64]	@ (8007704 <prvCheckForValidListAndQueue+0x64>)
 80076c2:	601a      	str	r2, [r3, #0]
			pxOverflowTimerList = &xActiveTimerList2;
 80076c4:	4b12      	ldr	r3, [pc, #72]	@ (8007710 <prvCheckForValidListAndQueue+0x70>)
 80076c6:	4a10      	ldr	r2, [pc, #64]	@ (8007708 <prvCheckForValidListAndQueue+0x68>)
 80076c8:	601a      	str	r2, [r3, #0]
				/* The timer queue is allocated statically in case
				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */

				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
 80076ca:	2300      	movs	r3, #0
 80076cc:	9300      	str	r3, [sp, #0]
 80076ce:	4b11      	ldr	r3, [pc, #68]	@ (8007714 <prvCheckForValidListAndQueue+0x74>)
 80076d0:	4a11      	ldr	r2, [pc, #68]	@ (8007718 <prvCheckForValidListAndQueue+0x78>)
 80076d2:	2110      	movs	r1, #16
 80076d4:	200a      	movs	r0, #10
 80076d6:	f7fd fff1 	bl	80056bc <xQueueGenericCreateStatic>
 80076da:	4603      	mov	r3, r0
 80076dc:	4a08      	ldr	r2, [pc, #32]	@ (8007700 <prvCheckForValidListAndQueue+0x60>)
 80076de:	6013      	str	r3, [r2, #0]
			}
			#endif

			#if ( configQUEUE_REGISTRY_SIZE > 0 )
			{
				if( xTimerQueue != NULL )
 80076e0:	4b07      	ldr	r3, [pc, #28]	@ (8007700 <prvCheckForValidListAndQueue+0x60>)
 80076e2:	681b      	ldr	r3, [r3, #0]
 80076e4:	2b00      	cmp	r3, #0
 80076e6:	d005      	beq.n	80076f4 <prvCheckForValidListAndQueue+0x54>
				{
					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
 80076e8:	4b05      	ldr	r3, [pc, #20]	@ (8007700 <prvCheckForValidListAndQueue+0x60>)
 80076ea:	681b      	ldr	r3, [r3, #0]
 80076ec:	490b      	ldr	r1, [pc, #44]	@ (800771c <prvCheckForValidListAndQueue+0x7c>)
 80076ee:	4618      	mov	r0, r3
 80076f0:	f7fe fc16 	bl	8005f20 <vQueueAddToRegistry>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 80076f4:	f000 f97a 	bl	80079ec <vPortExitCritical>
}
 80076f8:	bf00      	nop
 80076fa:	46bd      	mov	sp, r7
 80076fc:	bd80      	pop	{r7, pc}
 80076fe:	bf00      	nop
 8007700:	200014f8 	.word	0x200014f8
 8007704:	200014c8 	.word	0x200014c8
 8007708:	200014dc 	.word	0x200014dc
 800770c:	200014f0 	.word	0x200014f0
 8007710:	200014f4 	.word	0x200014f4
 8007714:	200015a4 	.word	0x200015a4
 8007718:	20001504 	.word	0x20001504
 800771c:	080081f8 	.word	0x080081f8

08007720 <pxPortInitialiseStack>:

/*
 * See header file for description.
 */
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
 8007720:	b480      	push	{r7}
 8007722:	b085      	sub	sp, #20
 8007724:	af00      	add	r7, sp, #0
 8007726:	60f8      	str	r0, [r7, #12]
 8007728:	60b9      	str	r1, [r7, #8]
 800772a:	607a      	str	r2, [r7, #4]
	/* Simulate the stack frame as it would be created by a context switch
	interrupt. */

	/* Offset added to account for the way the MCU uses the stack on entry/exit
	of interrupts, and to ensure alignment. */
	pxTopOfStack--;
 800772c:	68fb      	ldr	r3, [r7, #12]
 800772e:	3b04      	subs	r3, #4
 8007730:	60fb      	str	r3, [r7, #12]

	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
 8007732:	68fb      	ldr	r3, [r7, #12]
 8007734:	f04f 7280 	mov.w	r2, #16777216	@ 0x1000000
 8007738:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 800773a:	68fb      	ldr	r3, [r7, #12]
 800773c:	3b04      	subs	r3, #4
 800773e:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
 8007740:	68bb      	ldr	r3, [r7, #8]
 8007742:	f023 0201 	bic.w	r2, r3, #1
 8007746:	68fb      	ldr	r3, [r7, #12]
 8007748:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 800774a:	68fb      	ldr	r3, [r7, #12]
 800774c:	3b04      	subs	r3, #4
 800774e:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
 8007750:	4a0c      	ldr	r2, [pc, #48]	@ (8007784 <pxPortInitialiseStack+0x64>)
 8007752:	68fb      	ldr	r3, [r7, #12]
 8007754:	601a      	str	r2, [r3, #0]

	/* Save code space by skipping register initialisation. */
	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
 8007756:	68fb      	ldr	r3, [r7, #12]
 8007758:	3b14      	subs	r3, #20
 800775a:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
 800775c:	687a      	ldr	r2, [r7, #4]
 800775e:	68fb      	ldr	r3, [r7, #12]
 8007760:	601a      	str	r2, [r3, #0]

	/* A save method is being used that requires each task to maintain its
	own exec return value. */
	pxTopOfStack--;
 8007762:	68fb      	ldr	r3, [r7, #12]
 8007764:	3b04      	subs	r3, #4
 8007766:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = portINITIAL_EXC_RETURN;
 8007768:	68fb      	ldr	r3, [r7, #12]
 800776a:	f06f 0202 	mvn.w	r2, #2
 800776e:	601a      	str	r2, [r3, #0]

	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
 8007770:	68fb      	ldr	r3, [r7, #12]
 8007772:	3b20      	subs	r3, #32
 8007774:	60fb      	str	r3, [r7, #12]

	return pxTopOfStack;
 8007776:	68fb      	ldr	r3, [r7, #12]
}
 8007778:	4618      	mov	r0, r3
 800777a:	3714      	adds	r7, #20
 800777c:	46bd      	mov	sp, r7
 800777e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007782:	4770      	bx	lr
 8007784:	08007789 	.word	0x08007789

08007788 <prvTaskExitError>:
/*-----------------------------------------------------------*/

static void prvTaskExitError( void )
{
 8007788:	b480      	push	{r7}
 800778a:	b085      	sub	sp, #20
 800778c:	af00      	add	r7, sp, #0
volatile uint32_t ulDummy = 0;
 800778e:	2300      	movs	r3, #0
 8007790:	607b      	str	r3, [r7, #4]
	its caller as there is nothing to return to.  If a task wants to exit it
	should instead call vTaskDelete( NULL ).

	Artificially force an assert() to be triggered if configASSERT() is
	defined, then stop here so application writers can catch the error. */
	configASSERT( uxCriticalNesting == ~0UL );
 8007792:	4b13      	ldr	r3, [pc, #76]	@ (80077e0 <prvTaskExitError+0x58>)
 8007794:	681b      	ldr	r3, [r3, #0]
 8007796:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 800779a:	d00b      	beq.n	80077b4 <prvTaskExitError+0x2c>
	__asm volatile
 800779c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80077a0:	f383 8811 	msr	BASEPRI, r3
 80077a4:	f3bf 8f6f 	isb	sy
 80077a8:	f3bf 8f4f 	dsb	sy
 80077ac:	60fb      	str	r3, [r7, #12]
}
 80077ae:	bf00      	nop
 80077b0:	bf00      	nop
 80077b2:	e7fd      	b.n	80077b0 <prvTaskExitError+0x28>
	__asm volatile
 80077b4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80077b8:	f383 8811 	msr	BASEPRI, r3
 80077bc:	f3bf 8f6f 	isb	sy
 80077c0:	f3bf 8f4f 	dsb	sy
 80077c4:	60bb      	str	r3, [r7, #8]
}
 80077c6:	bf00      	nop
	portDISABLE_INTERRUPTS();
	while( ulDummy == 0 )
 80077c8:	bf00      	nop
 80077ca:	687b      	ldr	r3, [r7, #4]
 80077cc:	2b00      	cmp	r3, #0
 80077ce:	d0fc      	beq.n	80077ca <prvTaskExitError+0x42>
		about code appearing after this function is called - making ulDummy
		volatile makes the compiler think the function could return and
		therefore not output an 'unreachable code' warning for code that appears
		after it. */
	}
}
 80077d0:	bf00      	nop
 80077d2:	bf00      	nop
 80077d4:	3714      	adds	r7, #20
 80077d6:	46bd      	mov	sp, r7
 80077d8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80077dc:	4770      	bx	lr
 80077de:	bf00      	nop
 80077e0:	20000010 	.word	0x20000010
	...

080077f0 <SVC_Handler>:
/*-----------------------------------------------------------*/

void vPortSVCHandler( void )
{
	__asm volatile (
 80077f0:	4b07      	ldr	r3, [pc, #28]	@ (8007810 <pxCurrentTCBConst2>)
 80077f2:	6819      	ldr	r1, [r3, #0]
 80077f4:	6808      	ldr	r0, [r1, #0]
 80077f6:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80077fa:	f380 8809 	msr	PSP, r0
 80077fe:	f3bf 8f6f 	isb	sy
 8007802:	f04f 0000 	mov.w	r0, #0
 8007806:	f380 8811 	msr	BASEPRI, r0
 800780a:	4770      	bx	lr
 800780c:	f3af 8000 	nop.w

08007810 <pxCurrentTCBConst2>:
 8007810:	20000fc8 	.word	0x20000fc8
					"	bx r14							\n"
					"									\n"
					"	.align 4						\n"
					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
				);
}
 8007814:	bf00      	nop
 8007816:	bf00      	nop

08007818 <prvPortStartFirstTask>:
{
	/* Start the first task.  This also clears the bit that indicates the FPU is
	in use in case the FPU was used before the scheduler was started - which
	would otherwise result in the unnecessary leaving of space in the SVC stack
	for lazy saving of FPU registers. */
	__asm volatile(
 8007818:	4808      	ldr	r0, [pc, #32]	@ (800783c <prvPortStartFirstTask+0x24>)
 800781a:	6800      	ldr	r0, [r0, #0]
 800781c:	6800      	ldr	r0, [r0, #0]
 800781e:	f380 8808 	msr	MSP, r0
 8007822:	f04f 0000 	mov.w	r0, #0
 8007826:	f380 8814 	msr	CONTROL, r0
 800782a:	b662      	cpsie	i
 800782c:	b661      	cpsie	f
 800782e:	f3bf 8f4f 	dsb	sy
 8007832:	f3bf 8f6f 	isb	sy
 8007836:	df00      	svc	0
 8007838:	bf00      	nop
					" dsb					\n"
					" isb					\n"
					" svc 0					\n" /* System call to start first task. */
					" nop					\n"
				);
}
 800783a:	bf00      	nop
 800783c:	e000ed08 	.word	0xe000ed08

08007840 <xPortStartScheduler>:

/*
 * See header file for description.
 */
BaseType_t xPortStartScheduler( void )
{
 8007840:	b580      	push	{r7, lr}
 8007842:	b086      	sub	sp, #24
 8007844:	af00      	add	r7, sp, #0
	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );

	/* This port can be used on all revisions of the Cortex-M7 core other than
	the r0p1 parts.  r0p1 parts should use the port from the
	/source/portable/GCC/ARM_CM7/r0p1 directory. */
	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
 8007846:	4b47      	ldr	r3, [pc, #284]	@ (8007964 <xPortStartScheduler+0x124>)
 8007848:	681b      	ldr	r3, [r3, #0]
 800784a:	4a47      	ldr	r2, [pc, #284]	@ (8007968 <xPortStartScheduler+0x128>)
 800784c:	4293      	cmp	r3, r2
 800784e:	d10b      	bne.n	8007868 <xPortStartScheduler+0x28>
	__asm volatile
 8007850:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007854:	f383 8811 	msr	BASEPRI, r3
 8007858:	f3bf 8f6f 	isb	sy
 800785c:	f3bf 8f4f 	dsb	sy
 8007860:	60fb      	str	r3, [r7, #12]
}
 8007862:	bf00      	nop
 8007864:	bf00      	nop
 8007866:	e7fd      	b.n	8007864 <xPortStartScheduler+0x24>
	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 8007868:	4b3e      	ldr	r3, [pc, #248]	@ (8007964 <xPortStartScheduler+0x124>)
 800786a:	681b      	ldr	r3, [r3, #0]
 800786c:	4a3f      	ldr	r2, [pc, #252]	@ (800796c <xPortStartScheduler+0x12c>)
 800786e:	4293      	cmp	r3, r2
 8007870:	d10b      	bne.n	800788a <xPortStartScheduler+0x4a>
	__asm volatile
 8007872:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007876:	f383 8811 	msr	BASEPRI, r3
 800787a:	f3bf 8f6f 	isb	sy
 800787e:	f3bf 8f4f 	dsb	sy
 8007882:	613b      	str	r3, [r7, #16]
}
 8007884:	bf00      	nop
 8007886:	bf00      	nop
 8007888:	e7fd      	b.n	8007886 <xPortStartScheduler+0x46>

	#if( configASSERT_DEFINED == 1 )
	{
		volatile uint32_t ulOriginalPriority;
		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
 800788a:	4b39      	ldr	r3, [pc, #228]	@ (8007970 <xPortStartScheduler+0x130>)
 800788c:	617b      	str	r3, [r7, #20]
		functions can be called.  ISR safe functions are those that end in
		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
		ensure interrupt entry is as fast and simple as possible.

		Save the interrupt priority value that is about to be clobbered. */
		ulOriginalPriority = *pucFirstUserPriorityRegister;
 800788e:	697b      	ldr	r3, [r7, #20]
 8007890:	781b      	ldrb	r3, [r3, #0]
 8007892:	b2db      	uxtb	r3, r3
 8007894:	607b      	str	r3, [r7, #4]

		/* Determine the number of priority bits available.  First write to all
		possible bits. */
		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 8007896:	697b      	ldr	r3, [r7, #20]
 8007898:	22ff      	movs	r2, #255	@ 0xff
 800789a:	701a      	strb	r2, [r3, #0]

		/* Read the value back to see how many bits stuck. */
		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 800789c:	697b      	ldr	r3, [r7, #20]
 800789e:	781b      	ldrb	r3, [r3, #0]
 80078a0:	b2db      	uxtb	r3, r3
 80078a2:	70fb      	strb	r3, [r7, #3]

		/* Use the same mask on the maximum system call priority. */
		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 80078a4:	78fb      	ldrb	r3, [r7, #3]
 80078a6:	b2db      	uxtb	r3, r3
 80078a8:	f003 0350 	and.w	r3, r3, #80	@ 0x50
 80078ac:	b2da      	uxtb	r2, r3
 80078ae:	4b31      	ldr	r3, [pc, #196]	@ (8007974 <xPortStartScheduler+0x134>)
 80078b0:	701a      	strb	r2, [r3, #0]

		/* Calculate the maximum acceptable priority group value for the number
		of bits read back. */
		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
 80078b2:	4b31      	ldr	r3, [pc, #196]	@ (8007978 <xPortStartScheduler+0x138>)
 80078b4:	2207      	movs	r2, #7
 80078b6:	601a      	str	r2, [r3, #0]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 80078b8:	e009      	b.n	80078ce <xPortStartScheduler+0x8e>
		{
			ulMaxPRIGROUPValue--;
 80078ba:	4b2f      	ldr	r3, [pc, #188]	@ (8007978 <xPortStartScheduler+0x138>)
 80078bc:	681b      	ldr	r3, [r3, #0]
 80078be:	3b01      	subs	r3, #1
 80078c0:	4a2d      	ldr	r2, [pc, #180]	@ (8007978 <xPortStartScheduler+0x138>)
 80078c2:	6013      	str	r3, [r2, #0]
			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 80078c4:	78fb      	ldrb	r3, [r7, #3]
 80078c6:	b2db      	uxtb	r3, r3
 80078c8:	005b      	lsls	r3, r3, #1
 80078ca:	b2db      	uxtb	r3, r3
 80078cc:	70fb      	strb	r3, [r7, #3]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 80078ce:	78fb      	ldrb	r3, [r7, #3]
 80078d0:	b2db      	uxtb	r3, r3
 80078d2:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80078d6:	2b80      	cmp	r3, #128	@ 0x80
 80078d8:	d0ef      	beq.n	80078ba <xPortStartScheduler+0x7a>
		#ifdef configPRIO_BITS
		{
			/* Check the FreeRTOS configuration that defines the number of
			priority bits matches the number of priority bits actually queried
			from the hardware. */
			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
 80078da:	4b27      	ldr	r3, [pc, #156]	@ (8007978 <xPortStartScheduler+0x138>)
 80078dc:	681b      	ldr	r3, [r3, #0]
 80078de:	f1c3 0307 	rsb	r3, r3, #7
 80078e2:	2b04      	cmp	r3, #4
 80078e4:	d00b      	beq.n	80078fe <xPortStartScheduler+0xbe>
	__asm volatile
 80078e6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80078ea:	f383 8811 	msr	BASEPRI, r3
 80078ee:	f3bf 8f6f 	isb	sy
 80078f2:	f3bf 8f4f 	dsb	sy
 80078f6:	60bb      	str	r3, [r7, #8]
}
 80078f8:	bf00      	nop
 80078fa:	bf00      	nop
 80078fc:	e7fd      	b.n	80078fa <xPortStartScheduler+0xba>
		}
		#endif

		/* Shift the priority group value back to its position within the AIRCR
		register. */
		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
 80078fe:	4b1e      	ldr	r3, [pc, #120]	@ (8007978 <xPortStartScheduler+0x138>)
 8007900:	681b      	ldr	r3, [r3, #0]
 8007902:	021b      	lsls	r3, r3, #8
 8007904:	4a1c      	ldr	r2, [pc, #112]	@ (8007978 <xPortStartScheduler+0x138>)
 8007906:	6013      	str	r3, [r2, #0]
		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
 8007908:	4b1b      	ldr	r3, [pc, #108]	@ (8007978 <xPortStartScheduler+0x138>)
 800790a:	681b      	ldr	r3, [r3, #0]
 800790c:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
 8007910:	4a19      	ldr	r2, [pc, #100]	@ (8007978 <xPortStartScheduler+0x138>)
 8007912:	6013      	str	r3, [r2, #0]

		/* Restore the clobbered interrupt priority register to its original
		value. */
		*pucFirstUserPriorityRegister = ulOriginalPriority;
 8007914:	687b      	ldr	r3, [r7, #4]
 8007916:	b2da      	uxtb	r2, r3
 8007918:	697b      	ldr	r3, [r7, #20]
 800791a:	701a      	strb	r2, [r3, #0]
	}
	#endif /* conifgASSERT_DEFINED */

	/* Make PendSV and SysTick the lowest priority interrupts. */
	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
 800791c:	4b17      	ldr	r3, [pc, #92]	@ (800797c <xPortStartScheduler+0x13c>)
 800791e:	681b      	ldr	r3, [r3, #0]
 8007920:	4a16      	ldr	r2, [pc, #88]	@ (800797c <xPortStartScheduler+0x13c>)
 8007922:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8007926:	6013      	str	r3, [r2, #0]
	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
 8007928:	4b14      	ldr	r3, [pc, #80]	@ (800797c <xPortStartScheduler+0x13c>)
 800792a:	681b      	ldr	r3, [r3, #0]
 800792c:	4a13      	ldr	r2, [pc, #76]	@ (800797c <xPortStartScheduler+0x13c>)
 800792e:	f043 4370 	orr.w	r3, r3, #4026531840	@ 0xf0000000
 8007932:	6013      	str	r3, [r2, #0]

	/* Start the timer that generates the tick ISR.  Interrupts are disabled
	here already. */
	vPortSetupTimerInterrupt();
 8007934:	f000 f8da 	bl	8007aec <vPortSetupTimerInterrupt>

	/* Initialise the critical nesting count ready for the first task. */
	uxCriticalNesting = 0;
 8007938:	4b11      	ldr	r3, [pc, #68]	@ (8007980 <xPortStartScheduler+0x140>)
 800793a:	2200      	movs	r2, #0
 800793c:	601a      	str	r2, [r3, #0]

	/* Ensure the VFP is enabled - it should be anyway. */
	vPortEnableVFP();
 800793e:	f000 f8f9 	bl	8007b34 <vPortEnableVFP>

	/* Lazy save always. */
	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
 8007942:	4b10      	ldr	r3, [pc, #64]	@ (8007984 <xPortStartScheduler+0x144>)
 8007944:	681b      	ldr	r3, [r3, #0]
 8007946:	4a0f      	ldr	r2, [pc, #60]	@ (8007984 <xPortStartScheduler+0x144>)
 8007948:	f043 4340 	orr.w	r3, r3, #3221225472	@ 0xc0000000
 800794c:	6013      	str	r3, [r2, #0]

	/* Start the first task. */
	prvPortStartFirstTask();
 800794e:	f7ff ff63 	bl	8007818 <prvPortStartFirstTask>
	exit error function to prevent compiler warnings about a static function
	not being called in the case that the application writer overrides this
	functionality by defining configTASK_RETURN_ADDRESS.  Call
	vTaskSwitchContext() so link time optimisation does not remove the
	symbol. */
	vTaskSwitchContext();
 8007952:	f7fe ff1d 	bl	8006790 <vTaskSwitchContext>
	prvTaskExitError();
 8007956:	f7ff ff17 	bl	8007788 <prvTaskExitError>

	/* Should not get here! */
	return 0;
 800795a:	2300      	movs	r3, #0
}
 800795c:	4618      	mov	r0, r3
 800795e:	3718      	adds	r7, #24
 8007960:	46bd      	mov	sp, r7
 8007962:	bd80      	pop	{r7, pc}
 8007964:	e000ed00 	.word	0xe000ed00
 8007968:	410fc271 	.word	0x410fc271
 800796c:	410fc270 	.word	0x410fc270
 8007970:	e000e400 	.word	0xe000e400
 8007974:	200015f4 	.word	0x200015f4
 8007978:	200015f8 	.word	0x200015f8
 800797c:	e000ed20 	.word	0xe000ed20
 8007980:	20000010 	.word	0x20000010
 8007984:	e000ef34 	.word	0xe000ef34

08007988 <vPortEnterCritical>:
	configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/

void vPortEnterCritical( void )
{
 8007988:	b480      	push	{r7}
 800798a:	b083      	sub	sp, #12
 800798c:	af00      	add	r7, sp, #0
	__asm volatile
 800798e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007992:	f383 8811 	msr	BASEPRI, r3
 8007996:	f3bf 8f6f 	isb	sy
 800799a:	f3bf 8f4f 	dsb	sy
 800799e:	607b      	str	r3, [r7, #4]
}
 80079a0:	bf00      	nop
	portDISABLE_INTERRUPTS();
	uxCriticalNesting++;
 80079a2:	4b10      	ldr	r3, [pc, #64]	@ (80079e4 <vPortEnterCritical+0x5c>)
 80079a4:	681b      	ldr	r3, [r3, #0]
 80079a6:	3301      	adds	r3, #1
 80079a8:	4a0e      	ldr	r2, [pc, #56]	@ (80079e4 <vPortEnterCritical+0x5c>)
 80079aa:	6013      	str	r3, [r2, #0]
	/* This is not the interrupt safe version of the enter critical function so
	assert() if it is being called from an interrupt context.  Only API
	functions that end in "FromISR" can be used in an interrupt.  Only assert if
	the critical nesting count is 1 to protect against recursive calls if the
	assert function also uses a critical section. */
	if( uxCriticalNesting == 1 )
 80079ac:	4b0d      	ldr	r3, [pc, #52]	@ (80079e4 <vPortEnterCritical+0x5c>)
 80079ae:	681b      	ldr	r3, [r3, #0]
 80079b0:	2b01      	cmp	r3, #1
 80079b2:	d110      	bne.n	80079d6 <vPortEnterCritical+0x4e>
	{
		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
 80079b4:	4b0c      	ldr	r3, [pc, #48]	@ (80079e8 <vPortEnterCritical+0x60>)
 80079b6:	681b      	ldr	r3, [r3, #0]
 80079b8:	b2db      	uxtb	r3, r3
 80079ba:	2b00      	cmp	r3, #0
 80079bc:	d00b      	beq.n	80079d6 <vPortEnterCritical+0x4e>
	__asm volatile
 80079be:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80079c2:	f383 8811 	msr	BASEPRI, r3
 80079c6:	f3bf 8f6f 	isb	sy
 80079ca:	f3bf 8f4f 	dsb	sy
 80079ce:	603b      	str	r3, [r7, #0]
}
 80079d0:	bf00      	nop
 80079d2:	bf00      	nop
 80079d4:	e7fd      	b.n	80079d2 <vPortEnterCritical+0x4a>
	}
}
 80079d6:	bf00      	nop
 80079d8:	370c      	adds	r7, #12
 80079da:	46bd      	mov	sp, r7
 80079dc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80079e0:	4770      	bx	lr
 80079e2:	bf00      	nop
 80079e4:	20000010 	.word	0x20000010
 80079e8:	e000ed04 	.word	0xe000ed04

080079ec <vPortExitCritical>:
/*-----------------------------------------------------------*/

void vPortExitCritical( void )
{
 80079ec:	b480      	push	{r7}
 80079ee:	b083      	sub	sp, #12
 80079f0:	af00      	add	r7, sp, #0
	configASSERT( uxCriticalNesting );
 80079f2:	4b12      	ldr	r3, [pc, #72]	@ (8007a3c <vPortExitCritical+0x50>)
 80079f4:	681b      	ldr	r3, [r3, #0]
 80079f6:	2b00      	cmp	r3, #0
 80079f8:	d10b      	bne.n	8007a12 <vPortExitCritical+0x26>
	__asm volatile
 80079fa:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80079fe:	f383 8811 	msr	BASEPRI, r3
 8007a02:	f3bf 8f6f 	isb	sy
 8007a06:	f3bf 8f4f 	dsb	sy
 8007a0a:	607b      	str	r3, [r7, #4]
}
 8007a0c:	bf00      	nop
 8007a0e:	bf00      	nop
 8007a10:	e7fd      	b.n	8007a0e <vPortExitCritical+0x22>
	uxCriticalNesting--;
 8007a12:	4b0a      	ldr	r3, [pc, #40]	@ (8007a3c <vPortExitCritical+0x50>)
 8007a14:	681b      	ldr	r3, [r3, #0]
 8007a16:	3b01      	subs	r3, #1
 8007a18:	4a08      	ldr	r2, [pc, #32]	@ (8007a3c <vPortExitCritical+0x50>)
 8007a1a:	6013      	str	r3, [r2, #0]
	if( uxCriticalNesting == 0 )
 8007a1c:	4b07      	ldr	r3, [pc, #28]	@ (8007a3c <vPortExitCritical+0x50>)
 8007a1e:	681b      	ldr	r3, [r3, #0]
 8007a20:	2b00      	cmp	r3, #0
 8007a22:	d105      	bne.n	8007a30 <vPortExitCritical+0x44>
 8007a24:	2300      	movs	r3, #0
 8007a26:	603b      	str	r3, [r7, #0]
	__asm volatile
 8007a28:	683b      	ldr	r3, [r7, #0]
 8007a2a:	f383 8811 	msr	BASEPRI, r3
}
 8007a2e:	bf00      	nop
	{
		portENABLE_INTERRUPTS();
	}
}
 8007a30:	bf00      	nop
 8007a32:	370c      	adds	r7, #12
 8007a34:	46bd      	mov	sp, r7
 8007a36:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007a3a:	4770      	bx	lr
 8007a3c:	20000010 	.word	0x20000010

08007a40 <PendSV_Handler>:

void xPortPendSVHandler( void )
{
	/* This is a naked function. */

	__asm volatile
 8007a40:	f3ef 8009 	mrs	r0, PSP
 8007a44:	f3bf 8f6f 	isb	sy
 8007a48:	4b15      	ldr	r3, [pc, #84]	@ (8007aa0 <pxCurrentTCBConst>)
 8007a4a:	681a      	ldr	r2, [r3, #0]
 8007a4c:	f01e 0f10 	tst.w	lr, #16
 8007a50:	bf08      	it	eq
 8007a52:	ed20 8a10 	vstmdbeq	r0!, {s16-s31}
 8007a56:	e920 4ff0 	stmdb	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8007a5a:	6010      	str	r0, [r2, #0]
 8007a5c:	e92d 0009 	stmdb	sp!, {r0, r3}
 8007a60:	f04f 0050 	mov.w	r0, #80	@ 0x50
 8007a64:	f380 8811 	msr	BASEPRI, r0
 8007a68:	f3bf 8f4f 	dsb	sy
 8007a6c:	f3bf 8f6f 	isb	sy
 8007a70:	f7fe fe8e 	bl	8006790 <vTaskSwitchContext>
 8007a74:	f04f 0000 	mov.w	r0, #0
 8007a78:	f380 8811 	msr	BASEPRI, r0
 8007a7c:	bc09      	pop	{r0, r3}
 8007a7e:	6819      	ldr	r1, [r3, #0]
 8007a80:	6808      	ldr	r0, [r1, #0]
 8007a82:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8007a86:	f01e 0f10 	tst.w	lr, #16
 8007a8a:	bf08      	it	eq
 8007a8c:	ecb0 8a10 	vldmiaeq	r0!, {s16-s31}
 8007a90:	f380 8809 	msr	PSP, r0
 8007a94:	f3bf 8f6f 	isb	sy
 8007a98:	4770      	bx	lr
 8007a9a:	bf00      	nop
 8007a9c:	f3af 8000 	nop.w

08007aa0 <pxCurrentTCBConst>:
 8007aa0:	20000fc8 	.word	0x20000fc8
	"										\n"
	"	.align 4							\n"
	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
	);
}
 8007aa4:	bf00      	nop
 8007aa6:	bf00      	nop

08007aa8 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/

void xPortSysTickHandler( void )
{
 8007aa8:	b580      	push	{r7, lr}
 8007aaa:	b082      	sub	sp, #8
 8007aac:	af00      	add	r7, sp, #0
	__asm volatile
 8007aae:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007ab2:	f383 8811 	msr	BASEPRI, r3
 8007ab6:	f3bf 8f6f 	isb	sy
 8007aba:	f3bf 8f4f 	dsb	sy
 8007abe:	607b      	str	r3, [r7, #4]
}
 8007ac0:	bf00      	nop
	save and then restore the interrupt mask value as its value is already
	known. */
	portDISABLE_INTERRUPTS();
	{
		/* Increment the RTOS tick. */
		if( xTaskIncrementTick() != pdFALSE )
 8007ac2:	f7fe fdab 	bl	800661c <xTaskIncrementTick>
 8007ac6:	4603      	mov	r3, r0
 8007ac8:	2b00      	cmp	r3, #0
 8007aca:	d003      	beq.n	8007ad4 <xPortSysTickHandler+0x2c>
		{
			/* A context switch is required.  Context switching is performed in
			the PendSV interrupt.  Pend the PendSV interrupt. */
			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
 8007acc:	4b06      	ldr	r3, [pc, #24]	@ (8007ae8 <xPortSysTickHandler+0x40>)
 8007ace:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8007ad2:	601a      	str	r2, [r3, #0]
 8007ad4:	2300      	movs	r3, #0
 8007ad6:	603b      	str	r3, [r7, #0]
	__asm volatile
 8007ad8:	683b      	ldr	r3, [r7, #0]
 8007ada:	f383 8811 	msr	BASEPRI, r3
}
 8007ade:	bf00      	nop
		}
	}
	portENABLE_INTERRUPTS();
}
 8007ae0:	bf00      	nop
 8007ae2:	3708      	adds	r7, #8
 8007ae4:	46bd      	mov	sp, r7
 8007ae6:	bd80      	pop	{r7, pc}
 8007ae8:	e000ed04 	.word	0xe000ed04

08007aec <vPortSetupTimerInterrupt>:
/*
 * Setup the systick timer to generate the tick interrupts at the required
 * frequency.
 */
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
 8007aec:	b480      	push	{r7}
 8007aee:	af00      	add	r7, sp, #0
		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
	}
	#endif /* configUSE_TICKLESS_IDLE */

	/* Stop and clear the SysTick. */
	portNVIC_SYSTICK_CTRL_REG = 0UL;
 8007af0:	4b0b      	ldr	r3, [pc, #44]	@ (8007b20 <vPortSetupTimerInterrupt+0x34>)
 8007af2:	2200      	movs	r2, #0
 8007af4:	601a      	str	r2, [r3, #0]
	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 8007af6:	4b0b      	ldr	r3, [pc, #44]	@ (8007b24 <vPortSetupTimerInterrupt+0x38>)
 8007af8:	2200      	movs	r2, #0
 8007afa:	601a      	str	r2, [r3, #0]

	/* Configure SysTick to interrupt at the requested rate. */
	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
 8007afc:	4b0a      	ldr	r3, [pc, #40]	@ (8007b28 <vPortSetupTimerInterrupt+0x3c>)
 8007afe:	681b      	ldr	r3, [r3, #0]
 8007b00:	4a0a      	ldr	r2, [pc, #40]	@ (8007b2c <vPortSetupTimerInterrupt+0x40>)
 8007b02:	fba2 2303 	umull	r2, r3, r2, r3
 8007b06:	099b      	lsrs	r3, r3, #6
 8007b08:	4a09      	ldr	r2, [pc, #36]	@ (8007b30 <vPortSetupTimerInterrupt+0x44>)
 8007b0a:	3b01      	subs	r3, #1
 8007b0c:	6013      	str	r3, [r2, #0]
	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
 8007b0e:	4b04      	ldr	r3, [pc, #16]	@ (8007b20 <vPortSetupTimerInterrupt+0x34>)
 8007b10:	2207      	movs	r2, #7
 8007b12:	601a      	str	r2, [r3, #0]
}
 8007b14:	bf00      	nop
 8007b16:	46bd      	mov	sp, r7
 8007b18:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007b1c:	4770      	bx	lr
 8007b1e:	bf00      	nop
 8007b20:	e000e010 	.word	0xe000e010
 8007b24:	e000e018 	.word	0xe000e018
 8007b28:	20000004 	.word	0x20000004
 8007b2c:	10624dd3 	.word	0x10624dd3
 8007b30:	e000e014 	.word	0xe000e014

08007b34 <vPortEnableVFP>:
/*-----------------------------------------------------------*/

/* This is a naked function. */
static void vPortEnableVFP( void )
{
	__asm volatile
 8007b34:	f8df 000c 	ldr.w	r0, [pc, #12]	@ 8007b44 <vPortEnableVFP+0x10>
 8007b38:	6801      	ldr	r1, [r0, #0]
 8007b3a:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
 8007b3e:	6001      	str	r1, [r0, #0]
 8007b40:	4770      	bx	lr
		"								\n"
		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
		"	str r1, [r0]				\n"
		"	bx r14						"
	);
}
 8007b42:	bf00      	nop
 8007b44:	e000ed88 	.word	0xe000ed88

08007b48 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/

#if( configASSERT_DEFINED == 1 )

	void vPortValidateInterruptPriority( void )
	{
 8007b48:	b480      	push	{r7}
 8007b4a:	b085      	sub	sp, #20
 8007b4c:	af00      	add	r7, sp, #0
	uint32_t ulCurrentInterrupt;
	uint8_t ucCurrentPriority;

		/* Obtain the number of the currently executing interrupt. */
		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 8007b4e:	f3ef 8305 	mrs	r3, IPSR
 8007b52:	60fb      	str	r3, [r7, #12]

		/* Is the interrupt number a user defined interrupt? */
		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
 8007b54:	68fb      	ldr	r3, [r7, #12]
 8007b56:	2b0f      	cmp	r3, #15
 8007b58:	d915      	bls.n	8007b86 <vPortValidateInterruptPriority+0x3e>
		{
			/* Look up the interrupt's priority. */
			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
 8007b5a:	4a18      	ldr	r2, [pc, #96]	@ (8007bbc <vPortValidateInterruptPriority+0x74>)
 8007b5c:	68fb      	ldr	r3, [r7, #12]
 8007b5e:	4413      	add	r3, r2
 8007b60:	781b      	ldrb	r3, [r3, #0]
 8007b62:	72fb      	strb	r3, [r7, #11]
			interrupt entry is as fast and simple as possible.

			The following links provide detailed information:
			http://www.freertos.org/RTOS-Cortex-M3-M4.html
			http://www.freertos.org/FAQHelp.html */
			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
 8007b64:	4b16      	ldr	r3, [pc, #88]	@ (8007bc0 <vPortValidateInterruptPriority+0x78>)
 8007b66:	781b      	ldrb	r3, [r3, #0]
 8007b68:	7afa      	ldrb	r2, [r7, #11]
 8007b6a:	429a      	cmp	r2, r3
 8007b6c:	d20b      	bcs.n	8007b86 <vPortValidateInterruptPriority+0x3e>
	__asm volatile
 8007b6e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007b72:	f383 8811 	msr	BASEPRI, r3
 8007b76:	f3bf 8f6f 	isb	sy
 8007b7a:	f3bf 8f4f 	dsb	sy
 8007b7e:	607b      	str	r3, [r7, #4]
}
 8007b80:	bf00      	nop
 8007b82:	bf00      	nop
 8007b84:	e7fd      	b.n	8007b82 <vPortValidateInterruptPriority+0x3a>
		configuration then the correct setting can be achieved on all Cortex-M
		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
		scheduler.  Note however that some vendor specific peripheral libraries
		assume a non-zero priority group setting, in which cases using a value
		of zero will result in unpredictable behaviour. */
		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
 8007b86:	4b0f      	ldr	r3, [pc, #60]	@ (8007bc4 <vPortValidateInterruptPriority+0x7c>)
 8007b88:	681b      	ldr	r3, [r3, #0]
 8007b8a:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 8007b8e:	4b0e      	ldr	r3, [pc, #56]	@ (8007bc8 <vPortValidateInterruptPriority+0x80>)
 8007b90:	681b      	ldr	r3, [r3, #0]
 8007b92:	429a      	cmp	r2, r3
 8007b94:	d90b      	bls.n	8007bae <vPortValidateInterruptPriority+0x66>
	__asm volatile
 8007b96:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007b9a:	f383 8811 	msr	BASEPRI, r3
 8007b9e:	f3bf 8f6f 	isb	sy
 8007ba2:	f3bf 8f4f 	dsb	sy
 8007ba6:	603b      	str	r3, [r7, #0]
}
 8007ba8:	bf00      	nop
 8007baa:	bf00      	nop
 8007bac:	e7fd      	b.n	8007baa <vPortValidateInterruptPriority+0x62>
	}
 8007bae:	bf00      	nop
 8007bb0:	3714      	adds	r7, #20
 8007bb2:	46bd      	mov	sp, r7
 8007bb4:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007bb8:	4770      	bx	lr
 8007bba:	bf00      	nop
 8007bbc:	e000e3f0 	.word	0xe000e3f0
 8007bc0:	200015f4 	.word	0x200015f4
 8007bc4:	e000ed0c 	.word	0xe000ed0c
 8007bc8:	200015f8 	.word	0x200015f8

08007bcc <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;

/*-----------------------------------------------------------*/

void *pvPortMalloc( size_t xWantedSize )
{
 8007bcc:	b580      	push	{r7, lr}
 8007bce:	b08a      	sub	sp, #40	@ 0x28
 8007bd0:	af00      	add	r7, sp, #0
 8007bd2:	6078      	str	r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
 8007bd4:	2300      	movs	r3, #0
 8007bd6:	61fb      	str	r3, [r7, #28]

	vTaskSuspendAll();
 8007bd8:	f7fe fc64 	bl	80064a4 <vTaskSuspendAll>
	{
		/* If this is the first call to malloc then the heap will require
		initialisation to setup the list of free blocks. */
		if( pxEnd == NULL )
 8007bdc:	4b5c      	ldr	r3, [pc, #368]	@ (8007d50 <pvPortMalloc+0x184>)
 8007bde:	681b      	ldr	r3, [r3, #0]
 8007be0:	2b00      	cmp	r3, #0
 8007be2:	d101      	bne.n	8007be8 <pvPortMalloc+0x1c>
		{
			prvHeapInit();
 8007be4:	f000 f924 	bl	8007e30 <prvHeapInit>

		/* Check the requested block size is not so large that the top bit is
		set.  The top bit of the block size member of the BlockLink_t structure
		is used to determine who owns the block - the application or the
		kernel, so it must be free. */
		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
 8007be8:	4b5a      	ldr	r3, [pc, #360]	@ (8007d54 <pvPortMalloc+0x188>)
 8007bea:	681a      	ldr	r2, [r3, #0]
 8007bec:	687b      	ldr	r3, [r7, #4]
 8007bee:	4013      	ands	r3, r2
 8007bf0:	2b00      	cmp	r3, #0
 8007bf2:	f040 8095 	bne.w	8007d20 <pvPortMalloc+0x154>
		{
			/* The wanted size is increased so it can contain a BlockLink_t
			structure in addition to the requested amount of bytes. */
			if( xWantedSize > 0 )
 8007bf6:	687b      	ldr	r3, [r7, #4]
 8007bf8:	2b00      	cmp	r3, #0
 8007bfa:	d01e      	beq.n	8007c3a <pvPortMalloc+0x6e>
			{
				xWantedSize += xHeapStructSize;
 8007bfc:	2208      	movs	r2, #8
 8007bfe:	687b      	ldr	r3, [r7, #4]
 8007c00:	4413      	add	r3, r2
 8007c02:	607b      	str	r3, [r7, #4]

				/* Ensure that blocks are always aligned to the required number
				of bytes. */
				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
 8007c04:	687b      	ldr	r3, [r7, #4]
 8007c06:	f003 0307 	and.w	r3, r3, #7
 8007c0a:	2b00      	cmp	r3, #0
 8007c0c:	d015      	beq.n	8007c3a <pvPortMalloc+0x6e>
				{
					/* Byte alignment required. */
					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
 8007c0e:	687b      	ldr	r3, [r7, #4]
 8007c10:	f023 0307 	bic.w	r3, r3, #7
 8007c14:	3308      	adds	r3, #8
 8007c16:	607b      	str	r3, [r7, #4]
					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
 8007c18:	687b      	ldr	r3, [r7, #4]
 8007c1a:	f003 0307 	and.w	r3, r3, #7
 8007c1e:	2b00      	cmp	r3, #0
 8007c20:	d00b      	beq.n	8007c3a <pvPortMalloc+0x6e>
	__asm volatile
 8007c22:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007c26:	f383 8811 	msr	BASEPRI, r3
 8007c2a:	f3bf 8f6f 	isb	sy
 8007c2e:	f3bf 8f4f 	dsb	sy
 8007c32:	617b      	str	r3, [r7, #20]
}
 8007c34:	bf00      	nop
 8007c36:	bf00      	nop
 8007c38:	e7fd      	b.n	8007c36 <pvPortMalloc+0x6a>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
 8007c3a:	687b      	ldr	r3, [r7, #4]
 8007c3c:	2b00      	cmp	r3, #0
 8007c3e:	d06f      	beq.n	8007d20 <pvPortMalloc+0x154>
 8007c40:	4b45      	ldr	r3, [pc, #276]	@ (8007d58 <pvPortMalloc+0x18c>)
 8007c42:	681b      	ldr	r3, [r3, #0]
 8007c44:	687a      	ldr	r2, [r7, #4]
 8007c46:	429a      	cmp	r2, r3
 8007c48:	d86a      	bhi.n	8007d20 <pvPortMalloc+0x154>
			{
				/* Traverse the list from the start	(lowest address) block until
				one	of adequate size is found. */
				pxPreviousBlock = &xStart;
 8007c4a:	4b44      	ldr	r3, [pc, #272]	@ (8007d5c <pvPortMalloc+0x190>)
 8007c4c:	623b      	str	r3, [r7, #32]
				pxBlock = xStart.pxNextFreeBlock;
 8007c4e:	4b43      	ldr	r3, [pc, #268]	@ (8007d5c <pvPortMalloc+0x190>)
 8007c50:	681b      	ldr	r3, [r3, #0]
 8007c52:	627b      	str	r3, [r7, #36]	@ 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8007c54:	e004      	b.n	8007c60 <pvPortMalloc+0x94>
				{
					pxPreviousBlock = pxBlock;
 8007c56:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007c58:	623b      	str	r3, [r7, #32]
					pxBlock = pxBlock->pxNextFreeBlock;
 8007c5a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007c5c:	681b      	ldr	r3, [r3, #0]
 8007c5e:	627b      	str	r3, [r7, #36]	@ 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8007c60:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007c62:	685b      	ldr	r3, [r3, #4]
 8007c64:	687a      	ldr	r2, [r7, #4]
 8007c66:	429a      	cmp	r2, r3
 8007c68:	d903      	bls.n	8007c72 <pvPortMalloc+0xa6>
 8007c6a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007c6c:	681b      	ldr	r3, [r3, #0]
 8007c6e:	2b00      	cmp	r3, #0
 8007c70:	d1f1      	bne.n	8007c56 <pvPortMalloc+0x8a>
				}

				/* If the end marker was reached then a block of adequate size
				was	not found. */
				if( pxBlock != pxEnd )
 8007c72:	4b37      	ldr	r3, [pc, #220]	@ (8007d50 <pvPortMalloc+0x184>)
 8007c74:	681b      	ldr	r3, [r3, #0]
 8007c76:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8007c78:	429a      	cmp	r2, r3
 8007c7a:	d051      	beq.n	8007d20 <pvPortMalloc+0x154>
				{
					/* Return the memory space pointed to - jumping over the
					BlockLink_t structure at its start. */
					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
 8007c7c:	6a3b      	ldr	r3, [r7, #32]
 8007c7e:	681b      	ldr	r3, [r3, #0]
 8007c80:	2208      	movs	r2, #8
 8007c82:	4413      	add	r3, r2
 8007c84:	61fb      	str	r3, [r7, #28]

					/* This block is being returned for use so must be taken out
					of the list of free blocks. */
					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
 8007c86:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007c88:	681a      	ldr	r2, [r3, #0]
 8007c8a:	6a3b      	ldr	r3, [r7, #32]
 8007c8c:	601a      	str	r2, [r3, #0]

					/* If the block is larger than required it can be split into
					two. */
					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
 8007c8e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007c90:	685a      	ldr	r2, [r3, #4]
 8007c92:	687b      	ldr	r3, [r7, #4]
 8007c94:	1ad2      	subs	r2, r2, r3
 8007c96:	2308      	movs	r3, #8
 8007c98:	005b      	lsls	r3, r3, #1
 8007c9a:	429a      	cmp	r2, r3
 8007c9c:	d920      	bls.n	8007ce0 <pvPortMalloc+0x114>
					{
						/* This block is to be split into two.  Create a new
						block following the number of bytes requested. The void
						cast is used to prevent byte alignment warnings from the
						compiler. */
						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
 8007c9e:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8007ca0:	687b      	ldr	r3, [r7, #4]
 8007ca2:	4413      	add	r3, r2
 8007ca4:	61bb      	str	r3, [r7, #24]
						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
 8007ca6:	69bb      	ldr	r3, [r7, #24]
 8007ca8:	f003 0307 	and.w	r3, r3, #7
 8007cac:	2b00      	cmp	r3, #0
 8007cae:	d00b      	beq.n	8007cc8 <pvPortMalloc+0xfc>
	__asm volatile
 8007cb0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007cb4:	f383 8811 	msr	BASEPRI, r3
 8007cb8:	f3bf 8f6f 	isb	sy
 8007cbc:	f3bf 8f4f 	dsb	sy
 8007cc0:	613b      	str	r3, [r7, #16]
}
 8007cc2:	bf00      	nop
 8007cc4:	bf00      	nop
 8007cc6:	e7fd      	b.n	8007cc4 <pvPortMalloc+0xf8>

						/* Calculate the sizes of two blocks split from the
						single block. */
						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
 8007cc8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007cca:	685a      	ldr	r2, [r3, #4]
 8007ccc:	687b      	ldr	r3, [r7, #4]
 8007cce:	1ad2      	subs	r2, r2, r3
 8007cd0:	69bb      	ldr	r3, [r7, #24]
 8007cd2:	605a      	str	r2, [r3, #4]
						pxBlock->xBlockSize = xWantedSize;
 8007cd4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007cd6:	687a      	ldr	r2, [r7, #4]
 8007cd8:	605a      	str	r2, [r3, #4]

						/* Insert the new block into the list of free blocks. */
						prvInsertBlockIntoFreeList( pxNewBlockLink );
 8007cda:	69b8      	ldr	r0, [r7, #24]
 8007cdc:	f000 f90a 	bl	8007ef4 <prvInsertBlockIntoFreeList>
					else
					{
						mtCOVERAGE_TEST_MARKER();
					}

					xFreeBytesRemaining -= pxBlock->xBlockSize;
 8007ce0:	4b1d      	ldr	r3, [pc, #116]	@ (8007d58 <pvPortMalloc+0x18c>)
 8007ce2:	681a      	ldr	r2, [r3, #0]
 8007ce4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007ce6:	685b      	ldr	r3, [r3, #4]
 8007ce8:	1ad3      	subs	r3, r2, r3
 8007cea:	4a1b      	ldr	r2, [pc, #108]	@ (8007d58 <pvPortMalloc+0x18c>)
 8007cec:	6013      	str	r3, [r2, #0]

					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
 8007cee:	4b1a      	ldr	r3, [pc, #104]	@ (8007d58 <pvPortMalloc+0x18c>)
 8007cf0:	681a      	ldr	r2, [r3, #0]
 8007cf2:	4b1b      	ldr	r3, [pc, #108]	@ (8007d60 <pvPortMalloc+0x194>)
 8007cf4:	681b      	ldr	r3, [r3, #0]
 8007cf6:	429a      	cmp	r2, r3
 8007cf8:	d203      	bcs.n	8007d02 <pvPortMalloc+0x136>
					{
						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
 8007cfa:	4b17      	ldr	r3, [pc, #92]	@ (8007d58 <pvPortMalloc+0x18c>)
 8007cfc:	681b      	ldr	r3, [r3, #0]
 8007cfe:	4a18      	ldr	r2, [pc, #96]	@ (8007d60 <pvPortMalloc+0x194>)
 8007d00:	6013      	str	r3, [r2, #0]
						mtCOVERAGE_TEST_MARKER();
					}

					/* The block is being returned - it is allocated and owned
					by the application and has no "next" block. */
					pxBlock->xBlockSize |= xBlockAllocatedBit;
 8007d02:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007d04:	685a      	ldr	r2, [r3, #4]
 8007d06:	4b13      	ldr	r3, [pc, #76]	@ (8007d54 <pvPortMalloc+0x188>)
 8007d08:	681b      	ldr	r3, [r3, #0]
 8007d0a:	431a      	orrs	r2, r3
 8007d0c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007d0e:	605a      	str	r2, [r3, #4]
					pxBlock->pxNextFreeBlock = NULL;
 8007d10:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007d12:	2200      	movs	r2, #0
 8007d14:	601a      	str	r2, [r3, #0]
					xNumberOfSuccessfulAllocations++;
 8007d16:	4b13      	ldr	r3, [pc, #76]	@ (8007d64 <pvPortMalloc+0x198>)
 8007d18:	681b      	ldr	r3, [r3, #0]
 8007d1a:	3301      	adds	r3, #1
 8007d1c:	4a11      	ldr	r2, [pc, #68]	@ (8007d64 <pvPortMalloc+0x198>)
 8007d1e:	6013      	str	r3, [r2, #0]
			mtCOVERAGE_TEST_MARKER();
		}

		traceMALLOC( pvReturn, xWantedSize );
	}
	( void ) xTaskResumeAll();
 8007d20:	f7fe fbce 	bl	80064c0 <xTaskResumeAll>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif

	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
 8007d24:	69fb      	ldr	r3, [r7, #28]
 8007d26:	f003 0307 	and.w	r3, r3, #7
 8007d2a:	2b00      	cmp	r3, #0
 8007d2c:	d00b      	beq.n	8007d46 <pvPortMalloc+0x17a>
	__asm volatile
 8007d2e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007d32:	f383 8811 	msr	BASEPRI, r3
 8007d36:	f3bf 8f6f 	isb	sy
 8007d3a:	f3bf 8f4f 	dsb	sy
 8007d3e:	60fb      	str	r3, [r7, #12]
}
 8007d40:	bf00      	nop
 8007d42:	bf00      	nop
 8007d44:	e7fd      	b.n	8007d42 <pvPortMalloc+0x176>
	return pvReturn;
 8007d46:	69fb      	ldr	r3, [r7, #28]
}
 8007d48:	4618      	mov	r0, r3
 8007d4a:	3728      	adds	r7, #40	@ 0x28
 8007d4c:	46bd      	mov	sp, r7
 8007d4e:	bd80      	pop	{r7, pc}
 8007d50:	20008b34 	.word	0x20008b34
 8007d54:	20008b48 	.word	0x20008b48
 8007d58:	20008b38 	.word	0x20008b38
 8007d5c:	20008b2c 	.word	0x20008b2c
 8007d60:	20008b3c 	.word	0x20008b3c
 8007d64:	20008b40 	.word	0x20008b40

08007d68 <vPortFree>:
/*-----------------------------------------------------------*/

void vPortFree( void *pv )
{
 8007d68:	b580      	push	{r7, lr}
 8007d6a:	b086      	sub	sp, #24
 8007d6c:	af00      	add	r7, sp, #0
 8007d6e:	6078      	str	r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
 8007d70:	687b      	ldr	r3, [r7, #4]
 8007d72:	617b      	str	r3, [r7, #20]
BlockLink_t *pxLink;

	if( pv != NULL )
 8007d74:	687b      	ldr	r3, [r7, #4]
 8007d76:	2b00      	cmp	r3, #0
 8007d78:	d04f      	beq.n	8007e1a <vPortFree+0xb2>
	{
		/* The memory being freed will have an BlockLink_t structure immediately
		before it. */
		puc -= xHeapStructSize;
 8007d7a:	2308      	movs	r3, #8
 8007d7c:	425b      	negs	r3, r3
 8007d7e:	697a      	ldr	r2, [r7, #20]
 8007d80:	4413      	add	r3, r2
 8007d82:	617b      	str	r3, [r7, #20]

		/* This casting is to keep the compiler from issuing warnings. */
		pxLink = ( void * ) puc;
 8007d84:	697b      	ldr	r3, [r7, #20]
 8007d86:	613b      	str	r3, [r7, #16]

		/* Check the block is actually allocated. */
		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
 8007d88:	693b      	ldr	r3, [r7, #16]
 8007d8a:	685a      	ldr	r2, [r3, #4]
 8007d8c:	4b25      	ldr	r3, [pc, #148]	@ (8007e24 <vPortFree+0xbc>)
 8007d8e:	681b      	ldr	r3, [r3, #0]
 8007d90:	4013      	ands	r3, r2
 8007d92:	2b00      	cmp	r3, #0
 8007d94:	d10b      	bne.n	8007dae <vPortFree+0x46>
	__asm volatile
 8007d96:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007d9a:	f383 8811 	msr	BASEPRI, r3
 8007d9e:	f3bf 8f6f 	isb	sy
 8007da2:	f3bf 8f4f 	dsb	sy
 8007da6:	60fb      	str	r3, [r7, #12]
}
 8007da8:	bf00      	nop
 8007daa:	bf00      	nop
 8007dac:	e7fd      	b.n	8007daa <vPortFree+0x42>
		configASSERT( pxLink->pxNextFreeBlock == NULL );
 8007dae:	693b      	ldr	r3, [r7, #16]
 8007db0:	681b      	ldr	r3, [r3, #0]
 8007db2:	2b00      	cmp	r3, #0
 8007db4:	d00b      	beq.n	8007dce <vPortFree+0x66>
	__asm volatile
 8007db6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007dba:	f383 8811 	msr	BASEPRI, r3
 8007dbe:	f3bf 8f6f 	isb	sy
 8007dc2:	f3bf 8f4f 	dsb	sy
 8007dc6:	60bb      	str	r3, [r7, #8]
}
 8007dc8:	bf00      	nop
 8007dca:	bf00      	nop
 8007dcc:	e7fd      	b.n	8007dca <vPortFree+0x62>

		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
 8007dce:	693b      	ldr	r3, [r7, #16]
 8007dd0:	685a      	ldr	r2, [r3, #4]
 8007dd2:	4b14      	ldr	r3, [pc, #80]	@ (8007e24 <vPortFree+0xbc>)
 8007dd4:	681b      	ldr	r3, [r3, #0]
 8007dd6:	4013      	ands	r3, r2
 8007dd8:	2b00      	cmp	r3, #0
 8007dda:	d01e      	beq.n	8007e1a <vPortFree+0xb2>
		{
			if( pxLink->pxNextFreeBlock == NULL )
 8007ddc:	693b      	ldr	r3, [r7, #16]
 8007dde:	681b      	ldr	r3, [r3, #0]
 8007de0:	2b00      	cmp	r3, #0
 8007de2:	d11a      	bne.n	8007e1a <vPortFree+0xb2>
			{
				/* The block is being returned to the heap - it is no longer
				allocated. */
				pxLink->xBlockSize &= ~xBlockAllocatedBit;
 8007de4:	693b      	ldr	r3, [r7, #16]
 8007de6:	685a      	ldr	r2, [r3, #4]
 8007de8:	4b0e      	ldr	r3, [pc, #56]	@ (8007e24 <vPortFree+0xbc>)
 8007dea:	681b      	ldr	r3, [r3, #0]
 8007dec:	43db      	mvns	r3, r3
 8007dee:	401a      	ands	r2, r3
 8007df0:	693b      	ldr	r3, [r7, #16]
 8007df2:	605a      	str	r2, [r3, #4]

				vTaskSuspendAll();
 8007df4:	f7fe fb56 	bl	80064a4 <vTaskSuspendAll>
				{
					/* Add this block to the list of free blocks. */
					xFreeBytesRemaining += pxLink->xBlockSize;
 8007df8:	693b      	ldr	r3, [r7, #16]
 8007dfa:	685a      	ldr	r2, [r3, #4]
 8007dfc:	4b0a      	ldr	r3, [pc, #40]	@ (8007e28 <vPortFree+0xc0>)
 8007dfe:	681b      	ldr	r3, [r3, #0]
 8007e00:	4413      	add	r3, r2
 8007e02:	4a09      	ldr	r2, [pc, #36]	@ (8007e28 <vPortFree+0xc0>)
 8007e04:	6013      	str	r3, [r2, #0]
					traceFREE( pv, pxLink->xBlockSize );
					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
 8007e06:	6938      	ldr	r0, [r7, #16]
 8007e08:	f000 f874 	bl	8007ef4 <prvInsertBlockIntoFreeList>
					xNumberOfSuccessfulFrees++;
 8007e0c:	4b07      	ldr	r3, [pc, #28]	@ (8007e2c <vPortFree+0xc4>)
 8007e0e:	681b      	ldr	r3, [r3, #0]
 8007e10:	3301      	adds	r3, #1
 8007e12:	4a06      	ldr	r2, [pc, #24]	@ (8007e2c <vPortFree+0xc4>)
 8007e14:	6013      	str	r3, [r2, #0]
				}
				( void ) xTaskResumeAll();
 8007e16:	f7fe fb53 	bl	80064c0 <xTaskResumeAll>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
}
 8007e1a:	bf00      	nop
 8007e1c:	3718      	adds	r7, #24
 8007e1e:	46bd      	mov	sp, r7
 8007e20:	bd80      	pop	{r7, pc}
 8007e22:	bf00      	nop
 8007e24:	20008b48 	.word	0x20008b48
 8007e28:	20008b38 	.word	0x20008b38
 8007e2c:	20008b44 	.word	0x20008b44

08007e30 <prvHeapInit>:
	/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/

static void prvHeapInit( void )
{
 8007e30:	b480      	push	{r7}
 8007e32:	b085      	sub	sp, #20
 8007e34:	af00      	add	r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
 8007e36:	f247 5330 	movw	r3, #30000	@ 0x7530
 8007e3a:	60bb      	str	r3, [r7, #8]

	/* Ensure the heap starts on a correctly aligned boundary. */
	uxAddress = ( size_t ) ucHeap;
 8007e3c:	4b27      	ldr	r3, [pc, #156]	@ (8007edc <prvHeapInit+0xac>)
 8007e3e:	60fb      	str	r3, [r7, #12]

	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
 8007e40:	68fb      	ldr	r3, [r7, #12]
 8007e42:	f003 0307 	and.w	r3, r3, #7
 8007e46:	2b00      	cmp	r3, #0
 8007e48:	d00c      	beq.n	8007e64 <prvHeapInit+0x34>
	{
		uxAddress += ( portBYTE_ALIGNMENT - 1 );
 8007e4a:	68fb      	ldr	r3, [r7, #12]
 8007e4c:	3307      	adds	r3, #7
 8007e4e:	60fb      	str	r3, [r7, #12]
		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8007e50:	68fb      	ldr	r3, [r7, #12]
 8007e52:	f023 0307 	bic.w	r3, r3, #7
 8007e56:	60fb      	str	r3, [r7, #12]
		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
 8007e58:	68ba      	ldr	r2, [r7, #8]
 8007e5a:	68fb      	ldr	r3, [r7, #12]
 8007e5c:	1ad3      	subs	r3, r2, r3
 8007e5e:	4a1f      	ldr	r2, [pc, #124]	@ (8007edc <prvHeapInit+0xac>)
 8007e60:	4413      	add	r3, r2
 8007e62:	60bb      	str	r3, [r7, #8]
	}

	pucAlignedHeap = ( uint8_t * ) uxAddress;
 8007e64:	68fb      	ldr	r3, [r7, #12]
 8007e66:	607b      	str	r3, [r7, #4]

	/* xStart is used to hold a pointer to the first item in the list of free
	blocks.  The void cast is used to prevent compiler warnings. */
	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
 8007e68:	4a1d      	ldr	r2, [pc, #116]	@ (8007ee0 <prvHeapInit+0xb0>)
 8007e6a:	687b      	ldr	r3, [r7, #4]
 8007e6c:	6013      	str	r3, [r2, #0]
	xStart.xBlockSize = ( size_t ) 0;
 8007e6e:	4b1c      	ldr	r3, [pc, #112]	@ (8007ee0 <prvHeapInit+0xb0>)
 8007e70:	2200      	movs	r2, #0
 8007e72:	605a      	str	r2, [r3, #4]

	/* pxEnd is used to mark the end of the list of free blocks and is inserted
	at the end of the heap space. */
	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
 8007e74:	687b      	ldr	r3, [r7, #4]
 8007e76:	68ba      	ldr	r2, [r7, #8]
 8007e78:	4413      	add	r3, r2
 8007e7a:	60fb      	str	r3, [r7, #12]
	uxAddress -= xHeapStructSize;
 8007e7c:	2208      	movs	r2, #8
 8007e7e:	68fb      	ldr	r3, [r7, #12]
 8007e80:	1a9b      	subs	r3, r3, r2
 8007e82:	60fb      	str	r3, [r7, #12]
	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8007e84:	68fb      	ldr	r3, [r7, #12]
 8007e86:	f023 0307 	bic.w	r3, r3, #7
 8007e8a:	60fb      	str	r3, [r7, #12]
	pxEnd = ( void * ) uxAddress;
 8007e8c:	68fb      	ldr	r3, [r7, #12]
 8007e8e:	4a15      	ldr	r2, [pc, #84]	@ (8007ee4 <prvHeapInit+0xb4>)
 8007e90:	6013      	str	r3, [r2, #0]
	pxEnd->xBlockSize = 0;
 8007e92:	4b14      	ldr	r3, [pc, #80]	@ (8007ee4 <prvHeapInit+0xb4>)
 8007e94:	681b      	ldr	r3, [r3, #0]
 8007e96:	2200      	movs	r2, #0
 8007e98:	605a      	str	r2, [r3, #4]
	pxEnd->pxNextFreeBlock = NULL;
 8007e9a:	4b12      	ldr	r3, [pc, #72]	@ (8007ee4 <prvHeapInit+0xb4>)
 8007e9c:	681b      	ldr	r3, [r3, #0]
 8007e9e:	2200      	movs	r2, #0
 8007ea0:	601a      	str	r2, [r3, #0]

	/* To start with there is a single free block that is sized to take up the
	entire heap space, minus the space taken by pxEnd. */
	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
 8007ea2:	687b      	ldr	r3, [r7, #4]
 8007ea4:	603b      	str	r3, [r7, #0]
	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
 8007ea6:	683b      	ldr	r3, [r7, #0]
 8007ea8:	68fa      	ldr	r2, [r7, #12]
 8007eaa:	1ad2      	subs	r2, r2, r3
 8007eac:	683b      	ldr	r3, [r7, #0]
 8007eae:	605a      	str	r2, [r3, #4]
	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
 8007eb0:	4b0c      	ldr	r3, [pc, #48]	@ (8007ee4 <prvHeapInit+0xb4>)
 8007eb2:	681a      	ldr	r2, [r3, #0]
 8007eb4:	683b      	ldr	r3, [r7, #0]
 8007eb6:	601a      	str	r2, [r3, #0]

	/* Only one block exists - and it covers the entire usable heap space. */
	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 8007eb8:	683b      	ldr	r3, [r7, #0]
 8007eba:	685b      	ldr	r3, [r3, #4]
 8007ebc:	4a0a      	ldr	r2, [pc, #40]	@ (8007ee8 <prvHeapInit+0xb8>)
 8007ebe:	6013      	str	r3, [r2, #0]
	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 8007ec0:	683b      	ldr	r3, [r7, #0]
 8007ec2:	685b      	ldr	r3, [r3, #4]
 8007ec4:	4a09      	ldr	r2, [pc, #36]	@ (8007eec <prvHeapInit+0xbc>)
 8007ec6:	6013      	str	r3, [r2, #0]

	/* Work out the position of the top bit in a size_t variable. */
	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
 8007ec8:	4b09      	ldr	r3, [pc, #36]	@ (8007ef0 <prvHeapInit+0xc0>)
 8007eca:	f04f 4200 	mov.w	r2, #2147483648	@ 0x80000000
 8007ece:	601a      	str	r2, [r3, #0]
}
 8007ed0:	bf00      	nop
 8007ed2:	3714      	adds	r7, #20
 8007ed4:	46bd      	mov	sp, r7
 8007ed6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007eda:	4770      	bx	lr
 8007edc:	200015fc 	.word	0x200015fc
 8007ee0:	20008b2c 	.word	0x20008b2c
 8007ee4:	20008b34 	.word	0x20008b34
 8007ee8:	20008b3c 	.word	0x20008b3c
 8007eec:	20008b38 	.word	0x20008b38
 8007ef0:	20008b48 	.word	0x20008b48

08007ef4 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/

static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
 8007ef4:	b480      	push	{r7}
 8007ef6:	b085      	sub	sp, #20
 8007ef8:	af00      	add	r7, sp, #0
 8007efa:	6078      	str	r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;

	/* Iterate through the list until a block is found that has a higher address
	than the block being inserted. */
	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
 8007efc:	4b28      	ldr	r3, [pc, #160]	@ (8007fa0 <prvInsertBlockIntoFreeList+0xac>)
 8007efe:	60fb      	str	r3, [r7, #12]
 8007f00:	e002      	b.n	8007f08 <prvInsertBlockIntoFreeList+0x14>
 8007f02:	68fb      	ldr	r3, [r7, #12]
 8007f04:	681b      	ldr	r3, [r3, #0]
 8007f06:	60fb      	str	r3, [r7, #12]
 8007f08:	68fb      	ldr	r3, [r7, #12]
 8007f0a:	681b      	ldr	r3, [r3, #0]
 8007f0c:	687a      	ldr	r2, [r7, #4]
 8007f0e:	429a      	cmp	r2, r3
 8007f10:	d8f7      	bhi.n	8007f02 <prvInsertBlockIntoFreeList+0xe>
		/* Nothing to do here, just iterate to the right position. */
	}

	/* Do the block being inserted, and the block it is being inserted after
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxIterator;
 8007f12:	68fb      	ldr	r3, [r7, #12]
 8007f14:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
 8007f16:	68fb      	ldr	r3, [r7, #12]
 8007f18:	685b      	ldr	r3, [r3, #4]
 8007f1a:	68ba      	ldr	r2, [r7, #8]
 8007f1c:	4413      	add	r3, r2
 8007f1e:	687a      	ldr	r2, [r7, #4]
 8007f20:	429a      	cmp	r2, r3
 8007f22:	d108      	bne.n	8007f36 <prvInsertBlockIntoFreeList+0x42>
	{
		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
 8007f24:	68fb      	ldr	r3, [r7, #12]
 8007f26:	685a      	ldr	r2, [r3, #4]
 8007f28:	687b      	ldr	r3, [r7, #4]
 8007f2a:	685b      	ldr	r3, [r3, #4]
 8007f2c:	441a      	add	r2, r3
 8007f2e:	68fb      	ldr	r3, [r7, #12]
 8007f30:	605a      	str	r2, [r3, #4]
		pxBlockToInsert = pxIterator;
 8007f32:	68fb      	ldr	r3, [r7, #12]
 8007f34:	607b      	str	r3, [r7, #4]
		mtCOVERAGE_TEST_MARKER();
	}

	/* Do the block being inserted, and the block it is being inserted before
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxBlockToInsert;
 8007f36:	687b      	ldr	r3, [r7, #4]
 8007f38:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
 8007f3a:	687b      	ldr	r3, [r7, #4]
 8007f3c:	685b      	ldr	r3, [r3, #4]
 8007f3e:	68ba      	ldr	r2, [r7, #8]
 8007f40:	441a      	add	r2, r3
 8007f42:	68fb      	ldr	r3, [r7, #12]
 8007f44:	681b      	ldr	r3, [r3, #0]
 8007f46:	429a      	cmp	r2, r3
 8007f48:	d118      	bne.n	8007f7c <prvInsertBlockIntoFreeList+0x88>
	{
		if( pxIterator->pxNextFreeBlock != pxEnd )
 8007f4a:	68fb      	ldr	r3, [r7, #12]
 8007f4c:	681a      	ldr	r2, [r3, #0]
 8007f4e:	4b15      	ldr	r3, [pc, #84]	@ (8007fa4 <prvInsertBlockIntoFreeList+0xb0>)
 8007f50:	681b      	ldr	r3, [r3, #0]
 8007f52:	429a      	cmp	r2, r3
 8007f54:	d00d      	beq.n	8007f72 <prvInsertBlockIntoFreeList+0x7e>
		{
			/* Form one big block from the two blocks. */
			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
 8007f56:	687b      	ldr	r3, [r7, #4]
 8007f58:	685a      	ldr	r2, [r3, #4]
 8007f5a:	68fb      	ldr	r3, [r7, #12]
 8007f5c:	681b      	ldr	r3, [r3, #0]
 8007f5e:	685b      	ldr	r3, [r3, #4]
 8007f60:	441a      	add	r2, r3
 8007f62:	687b      	ldr	r3, [r7, #4]
 8007f64:	605a      	str	r2, [r3, #4]
			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
 8007f66:	68fb      	ldr	r3, [r7, #12]
 8007f68:	681b      	ldr	r3, [r3, #0]
 8007f6a:	681a      	ldr	r2, [r3, #0]
 8007f6c:	687b      	ldr	r3, [r7, #4]
 8007f6e:	601a      	str	r2, [r3, #0]
 8007f70:	e008      	b.n	8007f84 <prvInsertBlockIntoFreeList+0x90>
		}
		else
		{
			pxBlockToInsert->pxNextFreeBlock = pxEnd;
 8007f72:	4b0c      	ldr	r3, [pc, #48]	@ (8007fa4 <prvInsertBlockIntoFreeList+0xb0>)
 8007f74:	681a      	ldr	r2, [r3, #0]
 8007f76:	687b      	ldr	r3, [r7, #4]
 8007f78:	601a      	str	r2, [r3, #0]
 8007f7a:	e003      	b.n	8007f84 <prvInsertBlockIntoFreeList+0x90>
		}
	}
	else
	{
		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
 8007f7c:	68fb      	ldr	r3, [r7, #12]
 8007f7e:	681a      	ldr	r2, [r3, #0]
 8007f80:	687b      	ldr	r3, [r7, #4]
 8007f82:	601a      	str	r2, [r3, #0]

	/* If the block being inserted plugged a gab, so was merged with the block
	before and the block after, then it's pxNextFreeBlock pointer will have
	already been set, and should not be set here as that would make it point
	to itself. */
	if( pxIterator != pxBlockToInsert )
 8007f84:	68fa      	ldr	r2, [r7, #12]
 8007f86:	687b      	ldr	r3, [r7, #4]
 8007f88:	429a      	cmp	r2, r3
 8007f8a:	d002      	beq.n	8007f92 <prvInsertBlockIntoFreeList+0x9e>
	{
		pxIterator->pxNextFreeBlock = pxBlockToInsert;
 8007f8c:	68fb      	ldr	r3, [r7, #12]
 8007f8e:	687a      	ldr	r2, [r7, #4]
 8007f90:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8007f92:	bf00      	nop
 8007f94:	3714      	adds	r7, #20
 8007f96:	46bd      	mov	sp, r7
 8007f98:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007f9c:	4770      	bx	lr
 8007f9e:	bf00      	nop
 8007fa0:	20008b2c 	.word	0x20008b2c
 8007fa4:	20008b34 	.word	0x20008b34

08007fa8 <memset>:
 8007fa8:	4402      	add	r2, r0
 8007faa:	4603      	mov	r3, r0
 8007fac:	4293      	cmp	r3, r2
 8007fae:	d100      	bne.n	8007fb2 <memset+0xa>
 8007fb0:	4770      	bx	lr
 8007fb2:	f803 1b01 	strb.w	r1, [r3], #1
 8007fb6:	e7f9      	b.n	8007fac <memset+0x4>

08007fb8 <_reclaim_reent>:
 8007fb8:	4b2d      	ldr	r3, [pc, #180]	@ (8008070 <_reclaim_reent+0xb8>)
 8007fba:	681b      	ldr	r3, [r3, #0]
 8007fbc:	4283      	cmp	r3, r0
 8007fbe:	b570      	push	{r4, r5, r6, lr}
 8007fc0:	4604      	mov	r4, r0
 8007fc2:	d053      	beq.n	800806c <_reclaim_reent+0xb4>
 8007fc4:	69c3      	ldr	r3, [r0, #28]
 8007fc6:	b31b      	cbz	r3, 8008010 <_reclaim_reent+0x58>
 8007fc8:	68db      	ldr	r3, [r3, #12]
 8007fca:	b163      	cbz	r3, 8007fe6 <_reclaim_reent+0x2e>
 8007fcc:	2500      	movs	r5, #0
 8007fce:	69e3      	ldr	r3, [r4, #28]
 8007fd0:	68db      	ldr	r3, [r3, #12]
 8007fd2:	5959      	ldr	r1, [r3, r5]
 8007fd4:	b9b1      	cbnz	r1, 8008004 <_reclaim_reent+0x4c>
 8007fd6:	3504      	adds	r5, #4
 8007fd8:	2d80      	cmp	r5, #128	@ 0x80
 8007fda:	d1f8      	bne.n	8007fce <_reclaim_reent+0x16>
 8007fdc:	69e3      	ldr	r3, [r4, #28]
 8007fde:	4620      	mov	r0, r4
 8007fe0:	68d9      	ldr	r1, [r3, #12]
 8007fe2:	f000 f87b 	bl	80080dc <_free_r>
 8007fe6:	69e3      	ldr	r3, [r4, #28]
 8007fe8:	6819      	ldr	r1, [r3, #0]
 8007fea:	b111      	cbz	r1, 8007ff2 <_reclaim_reent+0x3a>
 8007fec:	4620      	mov	r0, r4
 8007fee:	f000 f875 	bl	80080dc <_free_r>
 8007ff2:	69e3      	ldr	r3, [r4, #28]
 8007ff4:	689d      	ldr	r5, [r3, #8]
 8007ff6:	b15d      	cbz	r5, 8008010 <_reclaim_reent+0x58>
 8007ff8:	4629      	mov	r1, r5
 8007ffa:	4620      	mov	r0, r4
 8007ffc:	682d      	ldr	r5, [r5, #0]
 8007ffe:	f000 f86d 	bl	80080dc <_free_r>
 8008002:	e7f8      	b.n	8007ff6 <_reclaim_reent+0x3e>
 8008004:	680e      	ldr	r6, [r1, #0]
 8008006:	4620      	mov	r0, r4
 8008008:	f000 f868 	bl	80080dc <_free_r>
 800800c:	4631      	mov	r1, r6
 800800e:	e7e1      	b.n	8007fd4 <_reclaim_reent+0x1c>
 8008010:	6961      	ldr	r1, [r4, #20]
 8008012:	b111      	cbz	r1, 800801a <_reclaim_reent+0x62>
 8008014:	4620      	mov	r0, r4
 8008016:	f000 f861 	bl	80080dc <_free_r>
 800801a:	69e1      	ldr	r1, [r4, #28]
 800801c:	b111      	cbz	r1, 8008024 <_reclaim_reent+0x6c>
 800801e:	4620      	mov	r0, r4
 8008020:	f000 f85c 	bl	80080dc <_free_r>
 8008024:	6b21      	ldr	r1, [r4, #48]	@ 0x30
 8008026:	b111      	cbz	r1, 800802e <_reclaim_reent+0x76>
 8008028:	4620      	mov	r0, r4
 800802a:	f000 f857 	bl	80080dc <_free_r>
 800802e:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 8008030:	b111      	cbz	r1, 8008038 <_reclaim_reent+0x80>
 8008032:	4620      	mov	r0, r4
 8008034:	f000 f852 	bl	80080dc <_free_r>
 8008038:	6ba1      	ldr	r1, [r4, #56]	@ 0x38
 800803a:	b111      	cbz	r1, 8008042 <_reclaim_reent+0x8a>
 800803c:	4620      	mov	r0, r4
 800803e:	f000 f84d 	bl	80080dc <_free_r>
 8008042:	6ca1      	ldr	r1, [r4, #72]	@ 0x48
 8008044:	b111      	cbz	r1, 800804c <_reclaim_reent+0x94>
 8008046:	4620      	mov	r0, r4
 8008048:	f000 f848 	bl	80080dc <_free_r>
 800804c:	6c61      	ldr	r1, [r4, #68]	@ 0x44
 800804e:	b111      	cbz	r1, 8008056 <_reclaim_reent+0x9e>
 8008050:	4620      	mov	r0, r4
 8008052:	f000 f843 	bl	80080dc <_free_r>
 8008056:	6ae1      	ldr	r1, [r4, #44]	@ 0x2c
 8008058:	b111      	cbz	r1, 8008060 <_reclaim_reent+0xa8>
 800805a:	4620      	mov	r0, r4
 800805c:	f000 f83e 	bl	80080dc <_free_r>
 8008060:	6a23      	ldr	r3, [r4, #32]
 8008062:	b11b      	cbz	r3, 800806c <_reclaim_reent+0xb4>
 8008064:	4620      	mov	r0, r4
 8008066:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
 800806a:	4718      	bx	r3
 800806c:	bd70      	pop	{r4, r5, r6, pc}
 800806e:	bf00      	nop
 8008070:	20000014 	.word	0x20000014

08008074 <__libc_init_array>:
 8008074:	b570      	push	{r4, r5, r6, lr}
 8008076:	4d0d      	ldr	r5, [pc, #52]	@ (80080ac <__libc_init_array+0x38>)
 8008078:	4c0d      	ldr	r4, [pc, #52]	@ (80080b0 <__libc_init_array+0x3c>)
 800807a:	1b64      	subs	r4, r4, r5
 800807c:	10a4      	asrs	r4, r4, #2
 800807e:	2600      	movs	r6, #0
 8008080:	42a6      	cmp	r6, r4
 8008082:	d109      	bne.n	8008098 <__libc_init_array+0x24>
 8008084:	4d0b      	ldr	r5, [pc, #44]	@ (80080b4 <__libc_init_array+0x40>)
 8008086:	4c0c      	ldr	r4, [pc, #48]	@ (80080b8 <__libc_init_array+0x44>)
 8008088:	f000 f87e 	bl	8008188 <_init>
 800808c:	1b64      	subs	r4, r4, r5
 800808e:	10a4      	asrs	r4, r4, #2
 8008090:	2600      	movs	r6, #0
 8008092:	42a6      	cmp	r6, r4
 8008094:	d105      	bne.n	80080a2 <__libc_init_array+0x2e>
 8008096:	bd70      	pop	{r4, r5, r6, pc}
 8008098:	f855 3b04 	ldr.w	r3, [r5], #4
 800809c:	4798      	blx	r3
 800809e:	3601      	adds	r6, #1
 80080a0:	e7ee      	b.n	8008080 <__libc_init_array+0xc>
 80080a2:	f855 3b04 	ldr.w	r3, [r5], #4
 80080a6:	4798      	blx	r3
 80080a8:	3601      	adds	r6, #1
 80080aa:	e7f2      	b.n	8008092 <__libc_init_array+0x1e>
 80080ac:	08008250 	.word	0x08008250
 80080b0:	08008250 	.word	0x08008250
 80080b4:	08008250 	.word	0x08008250
 80080b8:	08008254 	.word	0x08008254

080080bc <__retarget_lock_acquire_recursive>:
 80080bc:	4770      	bx	lr

080080be <__retarget_lock_release_recursive>:
 80080be:	4770      	bx	lr

080080c0 <memcpy>:
 80080c0:	440a      	add	r2, r1
 80080c2:	4291      	cmp	r1, r2
 80080c4:	f100 33ff 	add.w	r3, r0, #4294967295	@ 0xffffffff
 80080c8:	d100      	bne.n	80080cc <memcpy+0xc>
 80080ca:	4770      	bx	lr
 80080cc:	b510      	push	{r4, lr}
 80080ce:	f811 4b01 	ldrb.w	r4, [r1], #1
 80080d2:	f803 4f01 	strb.w	r4, [r3, #1]!
 80080d6:	4291      	cmp	r1, r2
 80080d8:	d1f9      	bne.n	80080ce <memcpy+0xe>
 80080da:	bd10      	pop	{r4, pc}

080080dc <_free_r>:
 80080dc:	b538      	push	{r3, r4, r5, lr}
 80080de:	4605      	mov	r5, r0
 80080e0:	2900      	cmp	r1, #0
 80080e2:	d041      	beq.n	8008168 <_free_r+0x8c>
 80080e4:	f851 3c04 	ldr.w	r3, [r1, #-4]
 80080e8:	1f0c      	subs	r4, r1, #4
 80080ea:	2b00      	cmp	r3, #0
 80080ec:	bfb8      	it	lt
 80080ee:	18e4      	addlt	r4, r4, r3
 80080f0:	f000 f83e 	bl	8008170 <__malloc_lock>
 80080f4:	4a1d      	ldr	r2, [pc, #116]	@ (800816c <_free_r+0x90>)
 80080f6:	6813      	ldr	r3, [r2, #0]
 80080f8:	b933      	cbnz	r3, 8008108 <_free_r+0x2c>
 80080fa:	6063      	str	r3, [r4, #4]
 80080fc:	6014      	str	r4, [r2, #0]
 80080fe:	4628      	mov	r0, r5
 8008100:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8008104:	f000 b83a 	b.w	800817c <__malloc_unlock>
 8008108:	42a3      	cmp	r3, r4
 800810a:	d908      	bls.n	800811e <_free_r+0x42>
 800810c:	6820      	ldr	r0, [r4, #0]
 800810e:	1821      	adds	r1, r4, r0
 8008110:	428b      	cmp	r3, r1
 8008112:	bf01      	itttt	eq
 8008114:	6819      	ldreq	r1, [r3, #0]
 8008116:	685b      	ldreq	r3, [r3, #4]
 8008118:	1809      	addeq	r1, r1, r0
 800811a:	6021      	streq	r1, [r4, #0]
 800811c:	e7ed      	b.n	80080fa <_free_r+0x1e>
 800811e:	461a      	mov	r2, r3
 8008120:	685b      	ldr	r3, [r3, #4]
 8008122:	b10b      	cbz	r3, 8008128 <_free_r+0x4c>
 8008124:	42a3      	cmp	r3, r4
 8008126:	d9fa      	bls.n	800811e <_free_r+0x42>
 8008128:	6811      	ldr	r1, [r2, #0]
 800812a:	1850      	adds	r0, r2, r1
 800812c:	42a0      	cmp	r0, r4
 800812e:	d10b      	bne.n	8008148 <_free_r+0x6c>
 8008130:	6820      	ldr	r0, [r4, #0]
 8008132:	4401      	add	r1, r0
 8008134:	1850      	adds	r0, r2, r1
 8008136:	4283      	cmp	r3, r0
 8008138:	6011      	str	r1, [r2, #0]
 800813a:	d1e0      	bne.n	80080fe <_free_r+0x22>
 800813c:	6818      	ldr	r0, [r3, #0]
 800813e:	685b      	ldr	r3, [r3, #4]
 8008140:	6053      	str	r3, [r2, #4]
 8008142:	4408      	add	r0, r1
 8008144:	6010      	str	r0, [r2, #0]
 8008146:	e7da      	b.n	80080fe <_free_r+0x22>
 8008148:	d902      	bls.n	8008150 <_free_r+0x74>
 800814a:	230c      	movs	r3, #12
 800814c:	602b      	str	r3, [r5, #0]
 800814e:	e7d6      	b.n	80080fe <_free_r+0x22>
 8008150:	6820      	ldr	r0, [r4, #0]
 8008152:	1821      	adds	r1, r4, r0
 8008154:	428b      	cmp	r3, r1
 8008156:	bf04      	itt	eq
 8008158:	6819      	ldreq	r1, [r3, #0]
 800815a:	685b      	ldreq	r3, [r3, #4]
 800815c:	6063      	str	r3, [r4, #4]
 800815e:	bf04      	itt	eq
 8008160:	1809      	addeq	r1, r1, r0
 8008162:	6021      	streq	r1, [r4, #0]
 8008164:	6054      	str	r4, [r2, #4]
 8008166:	e7ca      	b.n	80080fe <_free_r+0x22>
 8008168:	bd38      	pop	{r3, r4, r5, pc}
 800816a:	bf00      	nop
 800816c:	20008c88 	.word	0x20008c88

08008170 <__malloc_lock>:
 8008170:	4801      	ldr	r0, [pc, #4]	@ (8008178 <__malloc_lock+0x8>)
 8008172:	f7ff bfa3 	b.w	80080bc <__retarget_lock_acquire_recursive>
 8008176:	bf00      	nop
 8008178:	20008c84 	.word	0x20008c84

0800817c <__malloc_unlock>:
 800817c:	4801      	ldr	r0, [pc, #4]	@ (8008184 <__malloc_unlock+0x8>)
 800817e:	f7ff bf9e 	b.w	80080be <__retarget_lock_release_recursive>
 8008182:	bf00      	nop
 8008184:	20008c84 	.word	0x20008c84

08008188 <_init>:
 8008188:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800818a:	bf00      	nop
 800818c:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800818e:	bc08      	pop	{r3}
 8008190:	469e      	mov	lr, r3
 8008192:	4770      	bx	lr

08008194 <_fini>:
 8008194:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8008196:	bf00      	nop
 8008198:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800819a:	bc08      	pop	{r3}
 800819c:	469e      	mov	lr, r3
 800819e:	4770      	bx	lr
