
P4_SETR2.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000188  08000000  08000000  00001000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000093d0  08000190  08000190  00001190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       000000b0  08009560  08009560  0000a560  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  08009610  08009610  0000b060  2**0
                  CONTENTS, READONLY
  4 .ARM          00000008  08009610  08009610  0000a610  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  08009618  08009618  0000b060  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08009618  08009618  0000a618  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  7 .fini_array   00000004  0800961c  0800961c  0000a61c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  8 .data         00000060  20000000  08009620  0000b000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00008c34  20000060  08009680  0000b060  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  20008c94  08009680  0000bc94  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  0000b060  2**0
                  CONTENTS, READONLY
 12 .debug_info   00029dd9  00000000  00000000  0000b090  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_abbrev 0000526b  00000000  00000000  00034e69  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_aranges 00002468  00000000  00000000  0003a0d8  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_rnglists 00001c60  00000000  00000000  0003c540  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_macro  0000557c  00000000  00000000  0003e1a0  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_line   0002846c  00000000  00000000  0004371c  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_str    00108a7e  00000000  00000000  0006bb88  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .comment      00000043  00000000  00000000  00174606  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00009fd0  00000000  00000000  0017464c  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .debug_line_str 00000061  00000000  00000000  0017e61c  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

08000190 <__do_global_dtors_aux>:
 8000190:	b510      	push	{r4, lr}
 8000192:	4c05      	ldr	r4, [pc, #20]	@ (80001a8 <__do_global_dtors_aux+0x18>)
 8000194:	7823      	ldrb	r3, [r4, #0]
 8000196:	b933      	cbnz	r3, 80001a6 <__do_global_dtors_aux+0x16>
 8000198:	4b04      	ldr	r3, [pc, #16]	@ (80001ac <__do_global_dtors_aux+0x1c>)
 800019a:	b113      	cbz	r3, 80001a2 <__do_global_dtors_aux+0x12>
 800019c:	4804      	ldr	r0, [pc, #16]	@ (80001b0 <__do_global_dtors_aux+0x20>)
 800019e:	f3af 8000 	nop.w
 80001a2:	2301      	movs	r3, #1
 80001a4:	7023      	strb	r3, [r4, #0]
 80001a6:	bd10      	pop	{r4, pc}
 80001a8:	20000060 	.word	0x20000060
 80001ac:	00000000 	.word	0x00000000
 80001b0:	08009548 	.word	0x08009548

080001b4 <frame_dummy>:
 80001b4:	b508      	push	{r3, lr}
 80001b6:	4b03      	ldr	r3, [pc, #12]	@ (80001c4 <frame_dummy+0x10>)
 80001b8:	b11b      	cbz	r3, 80001c2 <frame_dummy+0xe>
 80001ba:	4903      	ldr	r1, [pc, #12]	@ (80001c8 <frame_dummy+0x14>)
 80001bc:	4803      	ldr	r0, [pc, #12]	@ (80001cc <frame_dummy+0x18>)
 80001be:	f3af 8000 	nop.w
 80001c2:	bd08      	pop	{r3, pc}
 80001c4:	00000000 	.word	0x00000000
 80001c8:	20000064 	.word	0x20000064
 80001cc:	08009548 	.word	0x08009548

080001d0 <__aeabi_uldivmod>:
 80001d0:	b953      	cbnz	r3, 80001e8 <__aeabi_uldivmod+0x18>
 80001d2:	b94a      	cbnz	r2, 80001e8 <__aeabi_uldivmod+0x18>
 80001d4:	2900      	cmp	r1, #0
 80001d6:	bf08      	it	eq
 80001d8:	2800      	cmpeq	r0, #0
 80001da:	bf1c      	itt	ne
 80001dc:	f04f 31ff 	movne.w	r1, #4294967295	@ 0xffffffff
 80001e0:	f04f 30ff 	movne.w	r0, #4294967295	@ 0xffffffff
 80001e4:	f000 b988 	b.w	80004f8 <__aeabi_idiv0>
 80001e8:	f1ad 0c08 	sub.w	ip, sp, #8
 80001ec:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 80001f0:	f000 f806 	bl	8000200 <__udivmoddi4>
 80001f4:	f8dd e004 	ldr.w	lr, [sp, #4]
 80001f8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80001fc:	b004      	add	sp, #16
 80001fe:	4770      	bx	lr

08000200 <__udivmoddi4>:
 8000200:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8000204:	9d08      	ldr	r5, [sp, #32]
 8000206:	468e      	mov	lr, r1
 8000208:	4604      	mov	r4, r0
 800020a:	4688      	mov	r8, r1
 800020c:	2b00      	cmp	r3, #0
 800020e:	d14a      	bne.n	80002a6 <__udivmoddi4+0xa6>
 8000210:	428a      	cmp	r2, r1
 8000212:	4617      	mov	r7, r2
 8000214:	d962      	bls.n	80002dc <__udivmoddi4+0xdc>
 8000216:	fab2 f682 	clz	r6, r2
 800021a:	b14e      	cbz	r6, 8000230 <__udivmoddi4+0x30>
 800021c:	f1c6 0320 	rsb	r3, r6, #32
 8000220:	fa01 f806 	lsl.w	r8, r1, r6
 8000224:	fa20 f303 	lsr.w	r3, r0, r3
 8000228:	40b7      	lsls	r7, r6
 800022a:	ea43 0808 	orr.w	r8, r3, r8
 800022e:	40b4      	lsls	r4, r6
 8000230:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000234:	fa1f fc87 	uxth.w	ip, r7
 8000238:	fbb8 f1fe 	udiv	r1, r8, lr
 800023c:	0c23      	lsrs	r3, r4, #16
 800023e:	fb0e 8811 	mls	r8, lr, r1, r8
 8000242:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
 8000246:	fb01 f20c 	mul.w	r2, r1, ip
 800024a:	429a      	cmp	r2, r3
 800024c:	d909      	bls.n	8000262 <__udivmoddi4+0x62>
 800024e:	18fb      	adds	r3, r7, r3
 8000250:	f101 30ff 	add.w	r0, r1, #4294967295	@ 0xffffffff
 8000254:	f080 80ea 	bcs.w	800042c <__udivmoddi4+0x22c>
 8000258:	429a      	cmp	r2, r3
 800025a:	f240 80e7 	bls.w	800042c <__udivmoddi4+0x22c>
 800025e:	3902      	subs	r1, #2
 8000260:	443b      	add	r3, r7
 8000262:	1a9a      	subs	r2, r3, r2
 8000264:	b2a3      	uxth	r3, r4
 8000266:	fbb2 f0fe 	udiv	r0, r2, lr
 800026a:	fb0e 2210 	mls	r2, lr, r0, r2
 800026e:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8000272:	fb00 fc0c 	mul.w	ip, r0, ip
 8000276:	459c      	cmp	ip, r3
 8000278:	d909      	bls.n	800028e <__udivmoddi4+0x8e>
 800027a:	18fb      	adds	r3, r7, r3
 800027c:	f100 32ff 	add.w	r2, r0, #4294967295	@ 0xffffffff
 8000280:	f080 80d6 	bcs.w	8000430 <__udivmoddi4+0x230>
 8000284:	459c      	cmp	ip, r3
 8000286:	f240 80d3 	bls.w	8000430 <__udivmoddi4+0x230>
 800028a:	443b      	add	r3, r7
 800028c:	3802      	subs	r0, #2
 800028e:	ea40 4001 	orr.w	r0, r0, r1, lsl #16
 8000292:	eba3 030c 	sub.w	r3, r3, ip
 8000296:	2100      	movs	r1, #0
 8000298:	b11d      	cbz	r5, 80002a2 <__udivmoddi4+0xa2>
 800029a:	40f3      	lsrs	r3, r6
 800029c:	2200      	movs	r2, #0
 800029e:	e9c5 3200 	strd	r3, r2, [r5]
 80002a2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002a6:	428b      	cmp	r3, r1
 80002a8:	d905      	bls.n	80002b6 <__udivmoddi4+0xb6>
 80002aa:	b10d      	cbz	r5, 80002b0 <__udivmoddi4+0xb0>
 80002ac:	e9c5 0100 	strd	r0, r1, [r5]
 80002b0:	2100      	movs	r1, #0
 80002b2:	4608      	mov	r0, r1
 80002b4:	e7f5      	b.n	80002a2 <__udivmoddi4+0xa2>
 80002b6:	fab3 f183 	clz	r1, r3
 80002ba:	2900      	cmp	r1, #0
 80002bc:	d146      	bne.n	800034c <__udivmoddi4+0x14c>
 80002be:	4573      	cmp	r3, lr
 80002c0:	d302      	bcc.n	80002c8 <__udivmoddi4+0xc8>
 80002c2:	4282      	cmp	r2, r0
 80002c4:	f200 8105 	bhi.w	80004d2 <__udivmoddi4+0x2d2>
 80002c8:	1a84      	subs	r4, r0, r2
 80002ca:	eb6e 0203 	sbc.w	r2, lr, r3
 80002ce:	2001      	movs	r0, #1
 80002d0:	4690      	mov	r8, r2
 80002d2:	2d00      	cmp	r5, #0
 80002d4:	d0e5      	beq.n	80002a2 <__udivmoddi4+0xa2>
 80002d6:	e9c5 4800 	strd	r4, r8, [r5]
 80002da:	e7e2      	b.n	80002a2 <__udivmoddi4+0xa2>
 80002dc:	2a00      	cmp	r2, #0
 80002de:	f000 8090 	beq.w	8000402 <__udivmoddi4+0x202>
 80002e2:	fab2 f682 	clz	r6, r2
 80002e6:	2e00      	cmp	r6, #0
 80002e8:	f040 80a4 	bne.w	8000434 <__udivmoddi4+0x234>
 80002ec:	1a8a      	subs	r2, r1, r2
 80002ee:	0c03      	lsrs	r3, r0, #16
 80002f0:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 80002f4:	b280      	uxth	r0, r0
 80002f6:	b2bc      	uxth	r4, r7
 80002f8:	2101      	movs	r1, #1
 80002fa:	fbb2 fcfe 	udiv	ip, r2, lr
 80002fe:	fb0e 221c 	mls	r2, lr, ip, r2
 8000302:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8000306:	fb04 f20c 	mul.w	r2, r4, ip
 800030a:	429a      	cmp	r2, r3
 800030c:	d907      	bls.n	800031e <__udivmoddi4+0x11e>
 800030e:	18fb      	adds	r3, r7, r3
 8000310:	f10c 38ff 	add.w	r8, ip, #4294967295	@ 0xffffffff
 8000314:	d202      	bcs.n	800031c <__udivmoddi4+0x11c>
 8000316:	429a      	cmp	r2, r3
 8000318:	f200 80e0 	bhi.w	80004dc <__udivmoddi4+0x2dc>
 800031c:	46c4      	mov	ip, r8
 800031e:	1a9b      	subs	r3, r3, r2
 8000320:	fbb3 f2fe 	udiv	r2, r3, lr
 8000324:	fb0e 3312 	mls	r3, lr, r2, r3
 8000328:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
 800032c:	fb02 f404 	mul.w	r4, r2, r4
 8000330:	429c      	cmp	r4, r3
 8000332:	d907      	bls.n	8000344 <__udivmoddi4+0x144>
 8000334:	18fb      	adds	r3, r7, r3
 8000336:	f102 30ff 	add.w	r0, r2, #4294967295	@ 0xffffffff
 800033a:	d202      	bcs.n	8000342 <__udivmoddi4+0x142>
 800033c:	429c      	cmp	r4, r3
 800033e:	f200 80ca 	bhi.w	80004d6 <__udivmoddi4+0x2d6>
 8000342:	4602      	mov	r2, r0
 8000344:	1b1b      	subs	r3, r3, r4
 8000346:	ea42 400c 	orr.w	r0, r2, ip, lsl #16
 800034a:	e7a5      	b.n	8000298 <__udivmoddi4+0x98>
 800034c:	f1c1 0620 	rsb	r6, r1, #32
 8000350:	408b      	lsls	r3, r1
 8000352:	fa22 f706 	lsr.w	r7, r2, r6
 8000356:	431f      	orrs	r7, r3
 8000358:	fa0e f401 	lsl.w	r4, lr, r1
 800035c:	fa20 f306 	lsr.w	r3, r0, r6
 8000360:	fa2e fe06 	lsr.w	lr, lr, r6
 8000364:	ea4f 4917 	mov.w	r9, r7, lsr #16
 8000368:	4323      	orrs	r3, r4
 800036a:	fa00 f801 	lsl.w	r8, r0, r1
 800036e:	fa1f fc87 	uxth.w	ip, r7
 8000372:	fbbe f0f9 	udiv	r0, lr, r9
 8000376:	0c1c      	lsrs	r4, r3, #16
 8000378:	fb09 ee10 	mls	lr, r9, r0, lr
 800037c:	ea44 440e 	orr.w	r4, r4, lr, lsl #16
 8000380:	fb00 fe0c 	mul.w	lr, r0, ip
 8000384:	45a6      	cmp	lr, r4
 8000386:	fa02 f201 	lsl.w	r2, r2, r1
 800038a:	d909      	bls.n	80003a0 <__udivmoddi4+0x1a0>
 800038c:	193c      	adds	r4, r7, r4
 800038e:	f100 3aff 	add.w	sl, r0, #4294967295	@ 0xffffffff
 8000392:	f080 809c 	bcs.w	80004ce <__udivmoddi4+0x2ce>
 8000396:	45a6      	cmp	lr, r4
 8000398:	f240 8099 	bls.w	80004ce <__udivmoddi4+0x2ce>
 800039c:	3802      	subs	r0, #2
 800039e:	443c      	add	r4, r7
 80003a0:	eba4 040e 	sub.w	r4, r4, lr
 80003a4:	fa1f fe83 	uxth.w	lr, r3
 80003a8:	fbb4 f3f9 	udiv	r3, r4, r9
 80003ac:	fb09 4413 	mls	r4, r9, r3, r4
 80003b0:	ea4e 4404 	orr.w	r4, lr, r4, lsl #16
 80003b4:	fb03 fc0c 	mul.w	ip, r3, ip
 80003b8:	45a4      	cmp	ip, r4
 80003ba:	d908      	bls.n	80003ce <__udivmoddi4+0x1ce>
 80003bc:	193c      	adds	r4, r7, r4
 80003be:	f103 3eff 	add.w	lr, r3, #4294967295	@ 0xffffffff
 80003c2:	f080 8082 	bcs.w	80004ca <__udivmoddi4+0x2ca>
 80003c6:	45a4      	cmp	ip, r4
 80003c8:	d97f      	bls.n	80004ca <__udivmoddi4+0x2ca>
 80003ca:	3b02      	subs	r3, #2
 80003cc:	443c      	add	r4, r7
 80003ce:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
 80003d2:	eba4 040c 	sub.w	r4, r4, ip
 80003d6:	fba0 ec02 	umull	lr, ip, r0, r2
 80003da:	4564      	cmp	r4, ip
 80003dc:	4673      	mov	r3, lr
 80003de:	46e1      	mov	r9, ip
 80003e0:	d362      	bcc.n	80004a8 <__udivmoddi4+0x2a8>
 80003e2:	d05f      	beq.n	80004a4 <__udivmoddi4+0x2a4>
 80003e4:	b15d      	cbz	r5, 80003fe <__udivmoddi4+0x1fe>
 80003e6:	ebb8 0203 	subs.w	r2, r8, r3
 80003ea:	eb64 0409 	sbc.w	r4, r4, r9
 80003ee:	fa04 f606 	lsl.w	r6, r4, r6
 80003f2:	fa22 f301 	lsr.w	r3, r2, r1
 80003f6:	431e      	orrs	r6, r3
 80003f8:	40cc      	lsrs	r4, r1
 80003fa:	e9c5 6400 	strd	r6, r4, [r5]
 80003fe:	2100      	movs	r1, #0
 8000400:	e74f      	b.n	80002a2 <__udivmoddi4+0xa2>
 8000402:	fbb1 fcf2 	udiv	ip, r1, r2
 8000406:	0c01      	lsrs	r1, r0, #16
 8000408:	ea41 410e 	orr.w	r1, r1, lr, lsl #16
 800040c:	b280      	uxth	r0, r0
 800040e:	ea40 4201 	orr.w	r2, r0, r1, lsl #16
 8000412:	463b      	mov	r3, r7
 8000414:	4638      	mov	r0, r7
 8000416:	463c      	mov	r4, r7
 8000418:	46b8      	mov	r8, r7
 800041a:	46be      	mov	lr, r7
 800041c:	2620      	movs	r6, #32
 800041e:	fbb1 f1f7 	udiv	r1, r1, r7
 8000422:	eba2 0208 	sub.w	r2, r2, r8
 8000426:	ea41 410c 	orr.w	r1, r1, ip, lsl #16
 800042a:	e766      	b.n	80002fa <__udivmoddi4+0xfa>
 800042c:	4601      	mov	r1, r0
 800042e:	e718      	b.n	8000262 <__udivmoddi4+0x62>
 8000430:	4610      	mov	r0, r2
 8000432:	e72c      	b.n	800028e <__udivmoddi4+0x8e>
 8000434:	f1c6 0220 	rsb	r2, r6, #32
 8000438:	fa2e f302 	lsr.w	r3, lr, r2
 800043c:	40b7      	lsls	r7, r6
 800043e:	40b1      	lsls	r1, r6
 8000440:	fa20 f202 	lsr.w	r2, r0, r2
 8000444:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000448:	430a      	orrs	r2, r1
 800044a:	fbb3 f8fe 	udiv	r8, r3, lr
 800044e:	b2bc      	uxth	r4, r7
 8000450:	fb0e 3318 	mls	r3, lr, r8, r3
 8000454:	0c11      	lsrs	r1, r2, #16
 8000456:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 800045a:	fb08 f904 	mul.w	r9, r8, r4
 800045e:	40b0      	lsls	r0, r6
 8000460:	4589      	cmp	r9, r1
 8000462:	ea4f 4310 	mov.w	r3, r0, lsr #16
 8000466:	b280      	uxth	r0, r0
 8000468:	d93e      	bls.n	80004e8 <__udivmoddi4+0x2e8>
 800046a:	1879      	adds	r1, r7, r1
 800046c:	f108 3cff 	add.w	ip, r8, #4294967295	@ 0xffffffff
 8000470:	d201      	bcs.n	8000476 <__udivmoddi4+0x276>
 8000472:	4589      	cmp	r9, r1
 8000474:	d81f      	bhi.n	80004b6 <__udivmoddi4+0x2b6>
 8000476:	eba1 0109 	sub.w	r1, r1, r9
 800047a:	fbb1 f9fe 	udiv	r9, r1, lr
 800047e:	fb09 f804 	mul.w	r8, r9, r4
 8000482:	fb0e 1119 	mls	r1, lr, r9, r1
 8000486:	b292      	uxth	r2, r2
 8000488:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
 800048c:	4542      	cmp	r2, r8
 800048e:	d229      	bcs.n	80004e4 <__udivmoddi4+0x2e4>
 8000490:	18ba      	adds	r2, r7, r2
 8000492:	f109 31ff 	add.w	r1, r9, #4294967295	@ 0xffffffff
 8000496:	d2c4      	bcs.n	8000422 <__udivmoddi4+0x222>
 8000498:	4542      	cmp	r2, r8
 800049a:	d2c2      	bcs.n	8000422 <__udivmoddi4+0x222>
 800049c:	f1a9 0102 	sub.w	r1, r9, #2
 80004a0:	443a      	add	r2, r7
 80004a2:	e7be      	b.n	8000422 <__udivmoddi4+0x222>
 80004a4:	45f0      	cmp	r8, lr
 80004a6:	d29d      	bcs.n	80003e4 <__udivmoddi4+0x1e4>
 80004a8:	ebbe 0302 	subs.w	r3, lr, r2
 80004ac:	eb6c 0c07 	sbc.w	ip, ip, r7
 80004b0:	3801      	subs	r0, #1
 80004b2:	46e1      	mov	r9, ip
 80004b4:	e796      	b.n	80003e4 <__udivmoddi4+0x1e4>
 80004b6:	eba7 0909 	sub.w	r9, r7, r9
 80004ba:	4449      	add	r1, r9
 80004bc:	f1a8 0c02 	sub.w	ip, r8, #2
 80004c0:	fbb1 f9fe 	udiv	r9, r1, lr
 80004c4:	fb09 f804 	mul.w	r8, r9, r4
 80004c8:	e7db      	b.n	8000482 <__udivmoddi4+0x282>
 80004ca:	4673      	mov	r3, lr
 80004cc:	e77f      	b.n	80003ce <__udivmoddi4+0x1ce>
 80004ce:	4650      	mov	r0, sl
 80004d0:	e766      	b.n	80003a0 <__udivmoddi4+0x1a0>
 80004d2:	4608      	mov	r0, r1
 80004d4:	e6fd      	b.n	80002d2 <__udivmoddi4+0xd2>
 80004d6:	443b      	add	r3, r7
 80004d8:	3a02      	subs	r2, #2
 80004da:	e733      	b.n	8000344 <__udivmoddi4+0x144>
 80004dc:	f1ac 0c02 	sub.w	ip, ip, #2
 80004e0:	443b      	add	r3, r7
 80004e2:	e71c      	b.n	800031e <__udivmoddi4+0x11e>
 80004e4:	4649      	mov	r1, r9
 80004e6:	e79c      	b.n	8000422 <__udivmoddi4+0x222>
 80004e8:	eba1 0109 	sub.w	r1, r1, r9
 80004ec:	46c4      	mov	ip, r8
 80004ee:	fbb1 f9fe 	udiv	r9, r1, lr
 80004f2:	fb09 f804 	mul.w	r8, r9, r4
 80004f6:	e7c4      	b.n	8000482 <__udivmoddi4+0x282>

080004f8 <__aeabi_idiv0>:
 80004f8:	4770      	bx	lr
 80004fa:	bf00      	nop

080004fc <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 80004fc:	b580      	push	{r7, lr}
 80004fe:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000500:	f001 f873 	bl	80015ea <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 8000504:	f000 f828 	bl	8000558 <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 8000508:	f000 f9f0 	bl	80008ec <MX_GPIO_Init>
  MX_DFSDM1_Init();
 800050c:	f000 f886 	bl	800061c <MX_DFSDM1_Init>
  MX_I2C2_Init();
 8000510:	f000 f8bc 	bl	800068c <MX_I2C2_Init>
  MX_QUADSPI_Init();
 8000514:	f000 f8f8 	bl	8000708 <MX_QUADSPI_Init>
  MX_SPI3_Init();
 8000518:	f000 f91c 	bl	8000754 <MX_SPI3_Init>
  MX_USART1_UART_Init();
 800051c:	f000 f958 	bl	80007d0 <MX_USART1_UART_Init>
  MX_USART3_UART_Init();
 8000520:	f000 f986 	bl	8000830 <MX_USART3_UART_Init>
  MX_USB_OTG_FS_PCD_Init();
 8000524:	f000 f9b4 	bl	8000890 <MX_USB_OTG_FS_PCD_Init>
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */

  /* Init scheduler */
  osKernelInitialize();
 8000528:	f005 fe7a 	bl	8006220 <osKernelInitialize>
  /* add queues, ... */
  /* USER CODE END RTOS_QUEUES */

  /* Create the thread(s) */
  /* creation of defaultTask */
  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
 800052c:	4a07      	ldr	r2, [pc, #28]	@ (800054c <main+0x50>)
 800052e:	2100      	movs	r1, #0
 8000530:	4807      	ldr	r0, [pc, #28]	@ (8000550 <main+0x54>)
 8000532:	f005 febf 	bl	80062b4 <osThreadNew>
 8000536:	4603      	mov	r3, r0
 8000538:	4a06      	ldr	r2, [pc, #24]	@ (8000554 <main+0x58>)
 800053a:	6013      	str	r3, [r2, #0]

  /* USER CODE BEGIN RTOS_THREADS */
  CreateSerialObjects();
 800053c:	f000 fba8 	bl	8000c90 <CreateSerialObjects>
  CreateSerialTask();
 8000540:	f000 fbc6 	bl	8000cd0 <CreateSerialTask>
  /* USER CODE BEGIN RTOS_EVENTS */
  /* add events, ... */
  /* USER CODE END RTOS_EVENTS */

  /* Start scheduler */
  osKernelStart();
 8000544:	f005 fe90 	bl	8006268 <osKernelStart>

  /* We should never get here as control is now taken by the scheduler */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
 8000548:	bf00      	nop
 800054a:	e7fd      	b.n	8000548 <main+0x4c>
 800054c:	080095a4 	.word	0x080095a4
 8000550:	08000c51 	.word	0x08000c51
 8000554:	200007a4 	.word	0x200007a4

08000558 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8000558:	b580      	push	{r7, lr}
 800055a:	b096      	sub	sp, #88	@ 0x58
 800055c:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 800055e:	f107 0314 	add.w	r3, r7, #20
 8000562:	2244      	movs	r2, #68	@ 0x44
 8000564:	2100      	movs	r1, #0
 8000566:	4618      	mov	r0, r3
 8000568:	f008 fefe 	bl	8009368 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 800056c:	463b      	mov	r3, r7
 800056e:	2200      	movs	r2, #0
 8000570:	601a      	str	r2, [r3, #0]
 8000572:	605a      	str	r2, [r3, #4]
 8000574:	609a      	str	r2, [r3, #8]
 8000576:	60da      	str	r2, [r3, #12]
 8000578:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
 800057a:	f44f 7000 	mov.w	r0, #512	@ 0x200
 800057e:	f001 ff67 	bl	8002450 <HAL_PWREx_ControlVoltageScaling>
 8000582:	4603      	mov	r3, r0
 8000584:	2b00      	cmp	r3, #0
 8000586:	d001      	beq.n	800058c <SystemClock_Config+0x34>
  {
    Error_Handler();
 8000588:	f000 fb7c 	bl	8000c84 <Error_Handler>
  }

  /** Configure LSE Drive Capability
  */
  HAL_PWR_EnableBkUpAccess();
 800058c:	f001 ff42 	bl	8002414 <HAL_PWR_EnableBkUpAccess>
  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 8000590:	4b21      	ldr	r3, [pc, #132]	@ (8000618 <SystemClock_Config+0xc0>)
 8000592:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8000596:	4a20      	ldr	r2, [pc, #128]	@ (8000618 <SystemClock_Config+0xc0>)
 8000598:	f023 0318 	bic.w	r3, r3, #24
 800059c:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
 80005a0:	2314      	movs	r3, #20
 80005a2:	617b      	str	r3, [r7, #20]
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
 80005a4:	2301      	movs	r3, #1
 80005a6:	61fb      	str	r3, [r7, #28]
  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
 80005a8:	2301      	movs	r3, #1
 80005aa:	62fb      	str	r3, [r7, #44]	@ 0x2c
  RCC_OscInitStruct.MSICalibrationValue = 0;
 80005ac:	2300      	movs	r3, #0
 80005ae:	633b      	str	r3, [r7, #48]	@ 0x30
  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
 80005b0:	2360      	movs	r3, #96	@ 0x60
 80005b2:	637b      	str	r3, [r7, #52]	@ 0x34
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 80005b4:	2302      	movs	r3, #2
 80005b6:	63fb      	str	r3, [r7, #60]	@ 0x3c
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
 80005b8:	2301      	movs	r3, #1
 80005ba:	643b      	str	r3, [r7, #64]	@ 0x40
  RCC_OscInitStruct.PLL.PLLM = 1;
 80005bc:	2301      	movs	r3, #1
 80005be:	647b      	str	r3, [r7, #68]	@ 0x44
  RCC_OscInitStruct.PLL.PLLN = 40;
 80005c0:	2328      	movs	r3, #40	@ 0x28
 80005c2:	64bb      	str	r3, [r7, #72]	@ 0x48
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
 80005c4:	2307      	movs	r3, #7
 80005c6:	64fb      	str	r3, [r7, #76]	@ 0x4c
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
 80005c8:	2302      	movs	r3, #2
 80005ca:	653b      	str	r3, [r7, #80]	@ 0x50
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 80005cc:	2302      	movs	r3, #2
 80005ce:	657b      	str	r3, [r7, #84]	@ 0x54
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 80005d0:	f107 0314 	add.w	r3, r7, #20
 80005d4:	4618      	mov	r0, r3
 80005d6:	f002 f85d 	bl	8002694 <HAL_RCC_OscConfig>
 80005da:	4603      	mov	r3, r0
 80005dc:	2b00      	cmp	r3, #0
 80005de:	d001      	beq.n	80005e4 <SystemClock_Config+0x8c>
  {
    Error_Handler();
 80005e0:	f000 fb50 	bl	8000c84 <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 80005e4:	230f      	movs	r3, #15
 80005e6:	603b      	str	r3, [r7, #0]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 80005e8:	2303      	movs	r3, #3
 80005ea:	607b      	str	r3, [r7, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 80005ec:	2300      	movs	r3, #0
 80005ee:	60bb      	str	r3, [r7, #8]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 80005f0:	2300      	movs	r3, #0
 80005f2:	60fb      	str	r3, [r7, #12]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 80005f4:	2300      	movs	r3, #0
 80005f6:	613b      	str	r3, [r7, #16]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 80005f8:	463b      	mov	r3, r7
 80005fa:	2104      	movs	r1, #4
 80005fc:	4618      	mov	r0, r3
 80005fe:	f002 fc25 	bl	8002e4c <HAL_RCC_ClockConfig>
 8000602:	4603      	mov	r3, r0
 8000604:	2b00      	cmp	r3, #0
 8000606:	d001      	beq.n	800060c <SystemClock_Config+0xb4>
  {
    Error_Handler();
 8000608:	f000 fb3c 	bl	8000c84 <Error_Handler>
  }

  /** Enable MSI Auto calibration
  */
  HAL_RCCEx_EnableMSIPLLMode();
 800060c:	f003 f95e 	bl	80038cc <HAL_RCCEx_EnableMSIPLLMode>
}
 8000610:	bf00      	nop
 8000612:	3758      	adds	r7, #88	@ 0x58
 8000614:	46bd      	mov	sp, r7
 8000616:	bd80      	pop	{r7, pc}
 8000618:	40021000 	.word	0x40021000

0800061c <MX_DFSDM1_Init>:
  * @brief DFSDM1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_DFSDM1_Init(void)
{
 800061c:	b580      	push	{r7, lr}
 800061e:	af00      	add	r7, sp, #0
  /* USER CODE END DFSDM1_Init 0 */

  /* USER CODE BEGIN DFSDM1_Init 1 */

  /* USER CODE END DFSDM1_Init 1 */
  hdfsdm1_channel1.Instance = DFSDM1_Channel1;
 8000620:	4b18      	ldr	r3, [pc, #96]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000622:	4a19      	ldr	r2, [pc, #100]	@ (8000688 <MX_DFSDM1_Init+0x6c>)
 8000624:	601a      	str	r2, [r3, #0]
  hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;
 8000626:	4b17      	ldr	r3, [pc, #92]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000628:	2201      	movs	r2, #1
 800062a:	711a      	strb	r2, [r3, #4]
  hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;
 800062c:	4b15      	ldr	r3, [pc, #84]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 800062e:	2200      	movs	r2, #0
 8000630:	609a      	str	r2, [r3, #8]
  hdfsdm1_channel1.Init.OutputClock.Divider = 2;
 8000632:	4b14      	ldr	r3, [pc, #80]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000634:	2202      	movs	r2, #2
 8000636:	60da      	str	r2, [r3, #12]
  hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
 8000638:	4b12      	ldr	r3, [pc, #72]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 800063a:	2200      	movs	r2, #0
 800063c:	611a      	str	r2, [r3, #16]
  hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
 800063e:	4b11      	ldr	r3, [pc, #68]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000640:	2200      	movs	r2, #0
 8000642:	615a      	str	r2, [r3, #20]
  hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;
 8000644:	4b0f      	ldr	r3, [pc, #60]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000646:	f44f 7280 	mov.w	r2, #256	@ 0x100
 800064a:	619a      	str	r2, [r3, #24]
  hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
 800064c:	4b0d      	ldr	r3, [pc, #52]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 800064e:	2200      	movs	r2, #0
 8000650:	61da      	str	r2, [r3, #28]
  hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
 8000652:	4b0c      	ldr	r3, [pc, #48]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000654:	2204      	movs	r2, #4
 8000656:	621a      	str	r2, [r3, #32]
  hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
 8000658:	4b0a      	ldr	r3, [pc, #40]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 800065a:	2200      	movs	r2, #0
 800065c:	625a      	str	r2, [r3, #36]	@ 0x24
  hdfsdm1_channel1.Init.Awd.Oversampling = 1;
 800065e:	4b09      	ldr	r3, [pc, #36]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000660:	2201      	movs	r2, #1
 8000662:	629a      	str	r2, [r3, #40]	@ 0x28
  hdfsdm1_channel1.Init.Offset = 0;
 8000664:	4b07      	ldr	r3, [pc, #28]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000666:	2200      	movs	r2, #0
 8000668:	62da      	str	r2, [r3, #44]	@ 0x2c
  hdfsdm1_channel1.Init.RightBitShift = 0x00;
 800066a:	4b06      	ldr	r3, [pc, #24]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 800066c:	2200      	movs	r2, #0
 800066e:	631a      	str	r2, [r3, #48]	@ 0x30
  if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)
 8000670:	4804      	ldr	r0, [pc, #16]	@ (8000684 <MX_DFSDM1_Init+0x68>)
 8000672:	f001 f8f9 	bl	8001868 <HAL_DFSDM_ChannelInit>
 8000676:	4603      	mov	r3, r0
 8000678:	2b00      	cmp	r3, #0
 800067a:	d001      	beq.n	8000680 <MX_DFSDM1_Init+0x64>
  {
    Error_Handler();
 800067c:	f000 fb02 	bl	8000c84 <Error_Handler>
  }
  /* USER CODE BEGIN DFSDM1_Init 2 */

  /* USER CODE END DFSDM1_Init 2 */

}
 8000680:	bf00      	nop
 8000682:	bd80      	pop	{r7, pc}
 8000684:	2000007c 	.word	0x2000007c
 8000688:	40016020 	.word	0x40016020

0800068c <MX_I2C2_Init>:
  * @brief I2C2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_I2C2_Init(void)
{
 800068c:	b580      	push	{r7, lr}
 800068e:	af00      	add	r7, sp, #0
  /* USER CODE END I2C2_Init 0 */

  /* USER CODE BEGIN I2C2_Init 1 */

  /* USER CODE END I2C2_Init 1 */
  hi2c2.Instance = I2C2;
 8000690:	4b1b      	ldr	r3, [pc, #108]	@ (8000700 <MX_I2C2_Init+0x74>)
 8000692:	4a1c      	ldr	r2, [pc, #112]	@ (8000704 <MX_I2C2_Init+0x78>)
 8000694:	601a      	str	r2, [r3, #0]
  hi2c2.Init.Timing = 0x00000E14;
 8000696:	4b1a      	ldr	r3, [pc, #104]	@ (8000700 <MX_I2C2_Init+0x74>)
 8000698:	f640 6214 	movw	r2, #3604	@ 0xe14
 800069c:	605a      	str	r2, [r3, #4]
  hi2c2.Init.OwnAddress1 = 0;
 800069e:	4b18      	ldr	r3, [pc, #96]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006a0:	2200      	movs	r2, #0
 80006a2:	609a      	str	r2, [r3, #8]
  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 80006a4:	4b16      	ldr	r3, [pc, #88]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006a6:	2201      	movs	r2, #1
 80006a8:	60da      	str	r2, [r3, #12]
  hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 80006aa:	4b15      	ldr	r3, [pc, #84]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006ac:	2200      	movs	r2, #0
 80006ae:	611a      	str	r2, [r3, #16]
  hi2c2.Init.OwnAddress2 = 0;
 80006b0:	4b13      	ldr	r3, [pc, #76]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006b2:	2200      	movs	r2, #0
 80006b4:	615a      	str	r2, [r3, #20]
  hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
 80006b6:	4b12      	ldr	r3, [pc, #72]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006b8:	2200      	movs	r2, #0
 80006ba:	619a      	str	r2, [r3, #24]
  hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 80006bc:	4b10      	ldr	r3, [pc, #64]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006be:	2200      	movs	r2, #0
 80006c0:	61da      	str	r2, [r3, #28]
  hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 80006c2:	4b0f      	ldr	r3, [pc, #60]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006c4:	2200      	movs	r2, #0
 80006c6:	621a      	str	r2, [r3, #32]
  if (HAL_I2C_Init(&hi2c2) != HAL_OK)
 80006c8:	480d      	ldr	r0, [pc, #52]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006ca:	f001 fc3e 	bl	8001f4a <HAL_I2C_Init>
 80006ce:	4603      	mov	r3, r0
 80006d0:	2b00      	cmp	r3, #0
 80006d2:	d001      	beq.n	80006d8 <MX_I2C2_Init+0x4c>
  {
    Error_Handler();
 80006d4:	f000 fad6 	bl	8000c84 <Error_Handler>
  }

  /** Configure Analogue filter
  */
  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
 80006d8:	2100      	movs	r1, #0
 80006da:	4809      	ldr	r0, [pc, #36]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006dc:	f001 fcd0 	bl	8002080 <HAL_I2CEx_ConfigAnalogFilter>
 80006e0:	4603      	mov	r3, r0
 80006e2:	2b00      	cmp	r3, #0
 80006e4:	d001      	beq.n	80006ea <MX_I2C2_Init+0x5e>
  {
    Error_Handler();
 80006e6:	f000 facd 	bl	8000c84 <Error_Handler>
  }

  /** Configure Digital filter
  */
  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
 80006ea:	2100      	movs	r1, #0
 80006ec:	4804      	ldr	r0, [pc, #16]	@ (8000700 <MX_I2C2_Init+0x74>)
 80006ee:	f001 fd12 	bl	8002116 <HAL_I2CEx_ConfigDigitalFilter>
 80006f2:	4603      	mov	r3, r0
 80006f4:	2b00      	cmp	r3, #0
 80006f6:	d001      	beq.n	80006fc <MX_I2C2_Init+0x70>
  {
    Error_Handler();
 80006f8:	f000 fac4 	bl	8000c84 <Error_Handler>
  }
  /* USER CODE BEGIN I2C2_Init 2 */

  /* USER CODE END I2C2_Init 2 */

}
 80006fc:	bf00      	nop
 80006fe:	bd80      	pop	{r7, pc}
 8000700:	200000b4 	.word	0x200000b4
 8000704:	40005800 	.word	0x40005800

08000708 <MX_QUADSPI_Init>:
  * @brief QUADSPI Initialization Function
  * @param None
  * @retval None
  */
static void MX_QUADSPI_Init(void)
{
 8000708:	b580      	push	{r7, lr}
 800070a:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN QUADSPI_Init 1 */

  /* USER CODE END QUADSPI_Init 1 */
  /* QUADSPI parameter configuration*/
  hqspi.Instance = QUADSPI;
 800070c:	4b0f      	ldr	r3, [pc, #60]	@ (800074c <MX_QUADSPI_Init+0x44>)
 800070e:	4a10      	ldr	r2, [pc, #64]	@ (8000750 <MX_QUADSPI_Init+0x48>)
 8000710:	601a      	str	r2, [r3, #0]
  hqspi.Init.ClockPrescaler = 2;
 8000712:	4b0e      	ldr	r3, [pc, #56]	@ (800074c <MX_QUADSPI_Init+0x44>)
 8000714:	2202      	movs	r2, #2
 8000716:	605a      	str	r2, [r3, #4]
  hqspi.Init.FifoThreshold = 4;
 8000718:	4b0c      	ldr	r3, [pc, #48]	@ (800074c <MX_QUADSPI_Init+0x44>)
 800071a:	2204      	movs	r2, #4
 800071c:	609a      	str	r2, [r3, #8]
  hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
 800071e:	4b0b      	ldr	r3, [pc, #44]	@ (800074c <MX_QUADSPI_Init+0x44>)
 8000720:	2210      	movs	r2, #16
 8000722:	60da      	str	r2, [r3, #12]
  hqspi.Init.FlashSize = 23;
 8000724:	4b09      	ldr	r3, [pc, #36]	@ (800074c <MX_QUADSPI_Init+0x44>)
 8000726:	2217      	movs	r2, #23
 8000728:	611a      	str	r2, [r3, #16]
  hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
 800072a:	4b08      	ldr	r3, [pc, #32]	@ (800074c <MX_QUADSPI_Init+0x44>)
 800072c:	2200      	movs	r2, #0
 800072e:	615a      	str	r2, [r3, #20]
  hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
 8000730:	4b06      	ldr	r3, [pc, #24]	@ (800074c <MX_QUADSPI_Init+0x44>)
 8000732:	2200      	movs	r2, #0
 8000734:	619a      	str	r2, [r3, #24]
  if (HAL_QSPI_Init(&hqspi) != HAL_OK)
 8000736:	4805      	ldr	r0, [pc, #20]	@ (800074c <MX_QUADSPI_Init+0x44>)
 8000738:	f001 fef0 	bl	800251c <HAL_QSPI_Init>
 800073c:	4603      	mov	r3, r0
 800073e:	2b00      	cmp	r3, #0
 8000740:	d001      	beq.n	8000746 <MX_QUADSPI_Init+0x3e>
  {
    Error_Handler();
 8000742:	f000 fa9f 	bl	8000c84 <Error_Handler>
  }
  /* USER CODE BEGIN QUADSPI_Init 2 */

  /* USER CODE END QUADSPI_Init 2 */

}
 8000746:	bf00      	nop
 8000748:	bd80      	pop	{r7, pc}
 800074a:	bf00      	nop
 800074c:	20000108 	.word	0x20000108
 8000750:	a0001000 	.word	0xa0001000

08000754 <MX_SPI3_Init>:
  * @brief SPI3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_SPI3_Init(void)
{
 8000754:	b580      	push	{r7, lr}
 8000756:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN SPI3_Init 1 */

  /* USER CODE END SPI3_Init 1 */
  /* SPI3 parameter configuration*/
  hspi3.Instance = SPI3;
 8000758:	4b1b      	ldr	r3, [pc, #108]	@ (80007c8 <MX_SPI3_Init+0x74>)
 800075a:	4a1c      	ldr	r2, [pc, #112]	@ (80007cc <MX_SPI3_Init+0x78>)
 800075c:	601a      	str	r2, [r3, #0]
  hspi3.Init.Mode = SPI_MODE_MASTER;
 800075e:	4b1a      	ldr	r3, [pc, #104]	@ (80007c8 <MX_SPI3_Init+0x74>)
 8000760:	f44f 7282 	mov.w	r2, #260	@ 0x104
 8000764:	605a      	str	r2, [r3, #4]
  hspi3.Init.Direction = SPI_DIRECTION_2LINES;
 8000766:	4b18      	ldr	r3, [pc, #96]	@ (80007c8 <MX_SPI3_Init+0x74>)
 8000768:	2200      	movs	r2, #0
 800076a:	609a      	str	r2, [r3, #8]
  hspi3.Init.DataSize = SPI_DATASIZE_4BIT;
 800076c:	4b16      	ldr	r3, [pc, #88]	@ (80007c8 <MX_SPI3_Init+0x74>)
 800076e:	f44f 7240 	mov.w	r2, #768	@ 0x300
 8000772:	60da      	str	r2, [r3, #12]
  hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
 8000774:	4b14      	ldr	r3, [pc, #80]	@ (80007c8 <MX_SPI3_Init+0x74>)
 8000776:	2200      	movs	r2, #0
 8000778:	611a      	str	r2, [r3, #16]
  hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
 800077a:	4b13      	ldr	r3, [pc, #76]	@ (80007c8 <MX_SPI3_Init+0x74>)
 800077c:	2200      	movs	r2, #0
 800077e:	615a      	str	r2, [r3, #20]
  hspi3.Init.NSS = SPI_NSS_SOFT;
 8000780:	4b11      	ldr	r3, [pc, #68]	@ (80007c8 <MX_SPI3_Init+0x74>)
 8000782:	f44f 7200 	mov.w	r2, #512	@ 0x200
 8000786:	619a      	str	r2, [r3, #24]
  hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
 8000788:	4b0f      	ldr	r3, [pc, #60]	@ (80007c8 <MX_SPI3_Init+0x74>)
 800078a:	2200      	movs	r2, #0
 800078c:	61da      	str	r2, [r3, #28]
  hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
 800078e:	4b0e      	ldr	r3, [pc, #56]	@ (80007c8 <MX_SPI3_Init+0x74>)
 8000790:	2200      	movs	r2, #0
 8000792:	621a      	str	r2, [r3, #32]
  hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
 8000794:	4b0c      	ldr	r3, [pc, #48]	@ (80007c8 <MX_SPI3_Init+0x74>)
 8000796:	2200      	movs	r2, #0
 8000798:	625a      	str	r2, [r3, #36]	@ 0x24
  hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 800079a:	4b0b      	ldr	r3, [pc, #44]	@ (80007c8 <MX_SPI3_Init+0x74>)
 800079c:	2200      	movs	r2, #0
 800079e:	629a      	str	r2, [r3, #40]	@ 0x28
  hspi3.Init.CRCPolynomial = 7;
 80007a0:	4b09      	ldr	r3, [pc, #36]	@ (80007c8 <MX_SPI3_Init+0x74>)
 80007a2:	2207      	movs	r2, #7
 80007a4:	62da      	str	r2, [r3, #44]	@ 0x2c
  hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
 80007a6:	4b08      	ldr	r3, [pc, #32]	@ (80007c8 <MX_SPI3_Init+0x74>)
 80007a8:	2200      	movs	r2, #0
 80007aa:	631a      	str	r2, [r3, #48]	@ 0x30
  hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
 80007ac:	4b06      	ldr	r3, [pc, #24]	@ (80007c8 <MX_SPI3_Init+0x74>)
 80007ae:	2208      	movs	r2, #8
 80007b0:	635a      	str	r2, [r3, #52]	@ 0x34
  if (HAL_SPI_Init(&hspi3) != HAL_OK)
 80007b2:	4805      	ldr	r0, [pc, #20]	@ (80007c8 <MX_SPI3_Init+0x74>)
 80007b4:	f003 fa6c 	bl	8003c90 <HAL_SPI_Init>
 80007b8:	4603      	mov	r3, r0
 80007ba:	2b00      	cmp	r3, #0
 80007bc:	d001      	beq.n	80007c2 <MX_SPI3_Init+0x6e>
  {
    Error_Handler();
 80007be:	f000 fa61 	bl	8000c84 <Error_Handler>
  }
  /* USER CODE BEGIN SPI3_Init 2 */

  /* USER CODE END SPI3_Init 2 */

}
 80007c2:	bf00      	nop
 80007c4:	bd80      	pop	{r7, pc}
 80007c6:	bf00      	nop
 80007c8:	2000014c 	.word	0x2000014c
 80007cc:	40003c00 	.word	0x40003c00

080007d0 <MX_USART1_UART_Init>:
  * @brief USART1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART1_UART_Init(void)
{
 80007d0:	b580      	push	{r7, lr}
 80007d2:	af00      	add	r7, sp, #0
  /* USER CODE END USART1_Init 0 */

  /* USER CODE BEGIN USART1_Init 1 */

  /* USER CODE END USART1_Init 1 */
  huart1.Instance = USART1;
 80007d4:	4b14      	ldr	r3, [pc, #80]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 80007d6:	4a15      	ldr	r2, [pc, #84]	@ (800082c <MX_USART1_UART_Init+0x5c>)
 80007d8:	601a      	str	r2, [r3, #0]
  huart1.Init.BaudRate = 115200;
 80007da:	4b13      	ldr	r3, [pc, #76]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 80007dc:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 80007e0:	605a      	str	r2, [r3, #4]
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 80007e2:	4b11      	ldr	r3, [pc, #68]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 80007e4:	2200      	movs	r2, #0
 80007e6:	609a      	str	r2, [r3, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 80007e8:	4b0f      	ldr	r3, [pc, #60]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 80007ea:	2200      	movs	r2, #0
 80007ec:	60da      	str	r2, [r3, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 80007ee:	4b0e      	ldr	r3, [pc, #56]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 80007f0:	2200      	movs	r2, #0
 80007f2:	611a      	str	r2, [r3, #16]
  huart1.Init.Mode = UART_MODE_TX_RX;
 80007f4:	4b0c      	ldr	r3, [pc, #48]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 80007f6:	220c      	movs	r2, #12
 80007f8:	615a      	str	r2, [r3, #20]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 80007fa:	4b0b      	ldr	r3, [pc, #44]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 80007fc:	2200      	movs	r2, #0
 80007fe:	619a      	str	r2, [r3, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8000800:	4b09      	ldr	r3, [pc, #36]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 8000802:	2200      	movs	r2, #0
 8000804:	61da      	str	r2, [r3, #28]
  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 8000806:	4b08      	ldr	r3, [pc, #32]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 8000808:	2200      	movs	r2, #0
 800080a:	621a      	str	r2, [r3, #32]
  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 800080c:	4b06      	ldr	r3, [pc, #24]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 800080e:	2200      	movs	r2, #0
 8000810:	625a      	str	r2, [r3, #36]	@ 0x24
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8000812:	4805      	ldr	r0, [pc, #20]	@ (8000828 <MX_USART1_UART_Init+0x58>)
 8000814:	f003 fda4 	bl	8004360 <HAL_UART_Init>
 8000818:	4603      	mov	r3, r0
 800081a:	2b00      	cmp	r3, #0
 800081c:	d001      	beq.n	8000822 <MX_USART1_UART_Init+0x52>
  {
    Error_Handler();
 800081e:	f000 fa31 	bl	8000c84 <Error_Handler>
  }
  /* USER CODE BEGIN USART1_Init 2 */

  /* USER CODE END USART1_Init 2 */

}
 8000822:	bf00      	nop
 8000824:	bd80      	pop	{r7, pc}
 8000826:	bf00      	nop
 8000828:	200001b0 	.word	0x200001b0
 800082c:	40013800 	.word	0x40013800

08000830 <MX_USART3_UART_Init>:
  * @brief USART3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART3_UART_Init(void)
{
 8000830:	b580      	push	{r7, lr}
 8000832:	af00      	add	r7, sp, #0
  /* USER CODE END USART3_Init 0 */

  /* USER CODE BEGIN USART3_Init 1 */

  /* USER CODE END USART3_Init 1 */
  huart3.Instance = USART3;
 8000834:	4b14      	ldr	r3, [pc, #80]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 8000836:	4a15      	ldr	r2, [pc, #84]	@ (800088c <MX_USART3_UART_Init+0x5c>)
 8000838:	601a      	str	r2, [r3, #0]
  huart3.Init.BaudRate = 115200;
 800083a:	4b13      	ldr	r3, [pc, #76]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 800083c:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 8000840:	605a      	str	r2, [r3, #4]
  huart3.Init.WordLength = UART_WORDLENGTH_8B;
 8000842:	4b11      	ldr	r3, [pc, #68]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 8000844:	2200      	movs	r2, #0
 8000846:	609a      	str	r2, [r3, #8]
  huart3.Init.StopBits = UART_STOPBITS_1;
 8000848:	4b0f      	ldr	r3, [pc, #60]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 800084a:	2200      	movs	r2, #0
 800084c:	60da      	str	r2, [r3, #12]
  huart3.Init.Parity = UART_PARITY_NONE;
 800084e:	4b0e      	ldr	r3, [pc, #56]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 8000850:	2200      	movs	r2, #0
 8000852:	611a      	str	r2, [r3, #16]
  huart3.Init.Mode = UART_MODE_TX_RX;
 8000854:	4b0c      	ldr	r3, [pc, #48]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 8000856:	220c      	movs	r2, #12
 8000858:	615a      	str	r2, [r3, #20]
  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 800085a:	4b0b      	ldr	r3, [pc, #44]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 800085c:	2200      	movs	r2, #0
 800085e:	619a      	str	r2, [r3, #24]
  huart3.Init.OverSampling = UART_OVERSAMPLING_16;
 8000860:	4b09      	ldr	r3, [pc, #36]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 8000862:	2200      	movs	r2, #0
 8000864:	61da      	str	r2, [r3, #28]
  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 8000866:	4b08      	ldr	r3, [pc, #32]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 8000868:	2200      	movs	r2, #0
 800086a:	621a      	str	r2, [r3, #32]
  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 800086c:	4b06      	ldr	r3, [pc, #24]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 800086e:	2200      	movs	r2, #0
 8000870:	625a      	str	r2, [r3, #36]	@ 0x24
  if (HAL_UART_Init(&huart3) != HAL_OK)
 8000872:	4805      	ldr	r0, [pc, #20]	@ (8000888 <MX_USART3_UART_Init+0x58>)
 8000874:	f003 fd74 	bl	8004360 <HAL_UART_Init>
 8000878:	4603      	mov	r3, r0
 800087a:	2b00      	cmp	r3, #0
 800087c:	d001      	beq.n	8000882 <MX_USART3_UART_Init+0x52>
  {
    Error_Handler();
 800087e:	f000 fa01 	bl	8000c84 <Error_Handler>
  }
  /* USER CODE BEGIN USART3_Init 2 */

  /* USER CODE END USART3_Init 2 */

}
 8000882:	bf00      	nop
 8000884:	bd80      	pop	{r7, pc}
 8000886:	bf00      	nop
 8000888:	20000238 	.word	0x20000238
 800088c:	40004800 	.word	0x40004800

08000890 <MX_USB_OTG_FS_PCD_Init>:
  * @brief USB_OTG_FS Initialization Function
  * @param None
  * @retval None
  */
static void MX_USB_OTG_FS_PCD_Init(void)
{
 8000890:	b580      	push	{r7, lr}
 8000892:	af00      	add	r7, sp, #0
  /* USER CODE END USB_OTG_FS_Init 0 */

  /* USER CODE BEGIN USB_OTG_FS_Init 1 */

  /* USER CODE END USB_OTG_FS_Init 1 */
  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
 8000894:	4b14      	ldr	r3, [pc, #80]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 8000896:	f04f 42a0 	mov.w	r2, #1342177280	@ 0x50000000
 800089a:	601a      	str	r2, [r3, #0]
  hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
 800089c:	4b12      	ldr	r3, [pc, #72]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 800089e:	2206      	movs	r2, #6
 80008a0:	711a      	strb	r2, [r3, #4]
  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
 80008a2:	4b11      	ldr	r3, [pc, #68]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008a4:	2202      	movs	r2, #2
 80008a6:	71da      	strb	r2, [r3, #7]
  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
 80008a8:	4b0f      	ldr	r3, [pc, #60]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008aa:	2202      	movs	r2, #2
 80008ac:	725a      	strb	r2, [r3, #9]
  hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
 80008ae:	4b0e      	ldr	r3, [pc, #56]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008b0:	2200      	movs	r2, #0
 80008b2:	729a      	strb	r2, [r3, #10]
  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
 80008b4:	4b0c      	ldr	r3, [pc, #48]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008b6:	2200      	movs	r2, #0
 80008b8:	72da      	strb	r2, [r3, #11]
  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
 80008ba:	4b0b      	ldr	r3, [pc, #44]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008bc:	2200      	movs	r2, #0
 80008be:	731a      	strb	r2, [r3, #12]
  hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
 80008c0:	4b09      	ldr	r3, [pc, #36]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008c2:	2200      	movs	r2, #0
 80008c4:	735a      	strb	r2, [r3, #13]
  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
 80008c6:	4b08      	ldr	r3, [pc, #32]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008c8:	2200      	movs	r2, #0
 80008ca:	73da      	strb	r2, [r3, #15]
  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
 80008cc:	4b06      	ldr	r3, [pc, #24]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008ce:	2200      	movs	r2, #0
 80008d0:	739a      	strb	r2, [r3, #14]
  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
 80008d2:	4805      	ldr	r0, [pc, #20]	@ (80008e8 <MX_USB_OTG_FS_PCD_Init+0x58>)
 80008d4:	f001 fc6b 	bl	80021ae <HAL_PCD_Init>
 80008d8:	4603      	mov	r3, r0
 80008da:	2b00      	cmp	r3, #0
 80008dc:	d001      	beq.n	80008e2 <MX_USB_OTG_FS_PCD_Init+0x52>
  {
    Error_Handler();
 80008de:	f000 f9d1 	bl	8000c84 <Error_Handler>
  }
  /* USER CODE BEGIN USB_OTG_FS_Init 2 */

  /* USER CODE END USB_OTG_FS_Init 2 */

}
 80008e2:	bf00      	nop
 80008e4:	bd80      	pop	{r7, pc}
 80008e6:	bf00      	nop
 80008e8:	200002c0 	.word	0x200002c0

080008ec <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 80008ec:	b580      	push	{r7, lr}
 80008ee:	b08a      	sub	sp, #40	@ 0x28
 80008f0:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80008f2:	f107 0314 	add.w	r3, r7, #20
 80008f6:	2200      	movs	r2, #0
 80008f8:	601a      	str	r2, [r3, #0]
 80008fa:	605a      	str	r2, [r3, #4]
 80008fc:	609a      	str	r2, [r3, #8]
 80008fe:	60da      	str	r2, [r3, #12]
 8000900:	611a      	str	r2, [r3, #16]
  /* USER CODE BEGIN MX_GPIO_Init_1 */

  /* USER CODE END MX_GPIO_Init_1 */

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8000902:	4bbd      	ldr	r3, [pc, #756]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000904:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000906:	4abc      	ldr	r2, [pc, #752]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000908:	f043 0310 	orr.w	r3, r3, #16
 800090c:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800090e:	4bba      	ldr	r3, [pc, #744]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000910:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000912:	f003 0310 	and.w	r3, r3, #16
 8000916:	613b      	str	r3, [r7, #16]
 8000918:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 800091a:	4bb7      	ldr	r3, [pc, #732]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 800091c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800091e:	4ab6      	ldr	r2, [pc, #728]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000920:	f043 0304 	orr.w	r3, r3, #4
 8000924:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000926:	4bb4      	ldr	r3, [pc, #720]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000928:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800092a:	f003 0304 	and.w	r3, r3, #4
 800092e:	60fb      	str	r3, [r7, #12]
 8000930:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8000932:	4bb1      	ldr	r3, [pc, #708]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000934:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000936:	4ab0      	ldr	r2, [pc, #704]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000938:	f043 0301 	orr.w	r3, r3, #1
 800093c:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800093e:	4bae      	ldr	r3, [pc, #696]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000940:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000942:	f003 0301 	and.w	r3, r3, #1
 8000946:	60bb      	str	r3, [r7, #8]
 8000948:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 800094a:	4bab      	ldr	r3, [pc, #684]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 800094c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800094e:	4aaa      	ldr	r2, [pc, #680]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000950:	f043 0302 	orr.w	r3, r3, #2
 8000954:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000956:	4ba8      	ldr	r3, [pc, #672]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000958:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800095a:	f003 0302 	and.w	r3, r3, #2
 800095e:	607b      	str	r3, [r7, #4]
 8000960:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8000962:	4ba5      	ldr	r3, [pc, #660]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000964:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000966:	4aa4      	ldr	r2, [pc, #656]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000968:	f043 0308 	orr.w	r3, r3, #8
 800096c:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800096e:	4ba2      	ldr	r3, [pc, #648]	@ (8000bf8 <MX_GPIO_Init+0x30c>)
 8000970:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000972:	f003 0308 	and.w	r3, r3, #8
 8000976:	603b      	str	r3, [r7, #0]
 8000978:	683b      	ldr	r3, [r7, #0]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET);
 800097a:	2200      	movs	r2, #0
 800097c:	f44f 718a 	mov.w	r1, #276	@ 0x114
 8000980:	489e      	ldr	r0, [pc, #632]	@ (8000bfc <MX_GPIO_Init+0x310>)
 8000982:	f001 faa7 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, ARD_D10_Pin|GPIO_PIN_5|SPBTLE_RF_RST_Pin|ARD_D9_Pin, GPIO_PIN_RESET);
 8000986:	2200      	movs	r2, #0
 8000988:	f248 1124 	movw	r1, #33060	@ 0x8124
 800098c:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000990:	f001 faa0 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOB, ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
 8000994:	2200      	movs	r2, #0
 8000996:	f24f 0114 	movw	r1, #61460	@ 0xf014
 800099a:	4899      	ldr	r0, [pc, #612]	@ (8000c00 <MX_GPIO_Init+0x314>)
 800099c:	f001 fa9a 	bl	8001ed4 <HAL_GPIO_WritePin>
                          |SPSGRF_915_SDN_Pin|ARD_D5_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET);
 80009a0:	2200      	movs	r2, #0
 80009a2:	f241 0181 	movw	r1, #4225	@ 0x1081
 80009a6:	4897      	ldr	r0, [pc, #604]	@ (8000c04 <MX_GPIO_Init+0x318>)
 80009a8:	f001 fa94 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET);
 80009ac:	2201      	movs	r2, #1
 80009ae:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 80009b2:	4894      	ldr	r0, [pc, #592]	@ (8000c04 <MX_GPIO_Init+0x318>)
 80009b4:	f001 fa8e 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET);
 80009b8:	2200      	movs	r2, #0
 80009ba:	f44f 7110 	mov.w	r1, #576	@ 0x240
 80009be:	4892      	ldr	r0, [pc, #584]	@ (8000c08 <MX_GPIO_Init+0x31c>)
 80009c0:	f001 fa88 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET);
 80009c4:	2201      	movs	r2, #1
 80009c6:	2120      	movs	r1, #32
 80009c8:	488d      	ldr	r0, [pc, #564]	@ (8000c00 <MX_GPIO_Init+0x314>)
 80009ca:	f001 fa83 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET);
 80009ce:	2201      	movs	r2, #1
 80009d0:	2101      	movs	r1, #1
 80009d2:	488a      	ldr	r0, [pc, #552]	@ (8000bfc <MX_GPIO_Init+0x310>)
 80009d4:	f001 fa7e 	bl	8001ed4 <HAL_GPIO_WritePin>

  /*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */
  GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin;
 80009d8:	f240 1315 	movw	r3, #277	@ 0x115
 80009dc:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80009de:	2301      	movs	r3, #1
 80009e0:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80009e2:	2300      	movs	r3, #0
 80009e4:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80009e6:	2300      	movs	r3, #0
 80009e8:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 80009ea:	f107 0314 	add.w	r3, r7, #20
 80009ee:	4619      	mov	r1, r3
 80009f0:	4882      	ldr	r0, [pc, #520]	@ (8000bfc <MX_GPIO_Init+0x310>)
 80009f2:	f001 f8c5 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */
  GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin;
 80009f6:	236a      	movs	r3, #106	@ 0x6a
 80009f8:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 80009fa:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
 80009fe:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000a00:	2300      	movs	r3, #0
 8000a02:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8000a04:	f107 0314 	add.w	r3, r7, #20
 8000a08:	4619      	mov	r1, r3
 8000a0a:	487c      	ldr	r0, [pc, #496]	@ (8000bfc <MX_GPIO_Init+0x310>)
 8000a0c:	f001 f8b8 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pin : BUTTON_EXTI13_Pin */
  GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin;
 8000a10:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
 8000a14:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
 8000a16:	f44f 1304 	mov.w	r3, #2162688	@ 0x210000
 8000a1a:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000a1c:	2300      	movs	r3, #0
 8000a1e:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct);
 8000a20:	f107 0314 	add.w	r3, r7, #20
 8000a24:	4619      	mov	r1, r3
 8000a26:	4878      	ldr	r0, [pc, #480]	@ (8000c08 <MX_GPIO_Init+0x31c>)
 8000a28:	f001 f8aa 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_A5_Pin ARD_A4_Pin ARD_A3_Pin ARD_A2_Pin
                           ARD_A1_Pin ARD_A0_Pin */
  GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin
 8000a2c:	233f      	movs	r3, #63	@ 0x3f
 8000a2e:	617b      	str	r3, [r7, #20]
                          |ARD_A1_Pin|ARD_A0_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
 8000a30:	230b      	movs	r3, #11
 8000a32:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000a34:	2300      	movs	r3, #0
 8000a36:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8000a38:	f107 0314 	add.w	r3, r7, #20
 8000a3c:	4619      	mov	r1, r3
 8000a3e:	4872      	ldr	r0, [pc, #456]	@ (8000c08 <MX_GPIO_Init+0x31c>)
 8000a40:	f001 f89e 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */
  GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin;
 8000a44:	2303      	movs	r3, #3
 8000a46:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000a48:	2302      	movs	r3, #2
 8000a4a:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000a4c:	2300      	movs	r3, #0
 8000a4e:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000a50:	2303      	movs	r3, #3
 8000a52:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
 8000a54:	2308      	movs	r3, #8
 8000a56:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000a58:	f107 0314 	add.w	r3, r7, #20
 8000a5c:	4619      	mov	r1, r3
 8000a5e:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000a62:	f001 f88d 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D10_Pin PA5 SPBTLE_RF_RST_Pin ARD_D9_Pin */
  GPIO_InitStruct.Pin = ARD_D10_Pin|GPIO_PIN_5|SPBTLE_RF_RST_Pin|ARD_D9_Pin;
 8000a66:	f248 1324 	movw	r3, #33060	@ 0x8124
 8000a6a:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000a6c:	2301      	movs	r3, #1
 8000a6e:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000a70:	2300      	movs	r3, #0
 8000a72:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000a74:	2300      	movs	r3, #0
 8000a76:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000a78:	f107 0314 	add.w	r3, r7, #20
 8000a7c:	4619      	mov	r1, r3
 8000a7e:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000a82:	f001 f87d 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pin : ARD_D4_Pin */
  GPIO_InitStruct.Pin = ARD_D4_Pin;
 8000a86:	2308      	movs	r3, #8
 8000a88:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000a8a:	2302      	movs	r3, #2
 8000a8c:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000a8e:	2300      	movs	r3, #0
 8000a90:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000a92:	2300      	movs	r3, #0
 8000a94:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
 8000a96:	2301      	movs	r3, #1
 8000a98:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(ARD_D4_GPIO_Port, &GPIO_InitStruct);
 8000a9a:	f107 0314 	add.w	r3, r7, #20
 8000a9e:	4619      	mov	r1, r3
 8000aa0:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000aa4:	f001 f86c 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pin : ARD_D7_Pin */
  GPIO_InitStruct.Pin = ARD_D7_Pin;
 8000aa8:	2310      	movs	r3, #16
 8000aaa:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
 8000aac:	230b      	movs	r3, #11
 8000aae:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000ab0:	2300      	movs	r3, #0
 8000ab2:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(ARD_D7_GPIO_Port, &GPIO_InitStruct);
 8000ab4:	f107 0314 	add.w	r3, r7, #20
 8000ab8:	4619      	mov	r1, r3
 8000aba:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000abe:	f001 f85f 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D12_Pin ARD_D11_Pin */
  GPIO_InitStruct.Pin = ARD_D12_Pin|ARD_D11_Pin;
 8000ac2:	23c0      	movs	r3, #192	@ 0xc0
 8000ac4:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000ac6:	2302      	movs	r3, #2
 8000ac8:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000aca:	2300      	movs	r3, #0
 8000acc:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000ace:	2303      	movs	r3, #3
 8000ad0:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
 8000ad2:	2305      	movs	r3, #5
 8000ad4:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000ad6:	f107 0314 	add.w	r3, r7, #20
 8000ada:	4619      	mov	r1, r3
 8000adc:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8000ae0:	f001 f84e 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pin : ARD_D3_Pin */
  GPIO_InitStruct.Pin = ARD_D3_Pin;
 8000ae4:	2301      	movs	r3, #1
 8000ae6:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 8000ae8:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
 8000aec:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000aee:	2300      	movs	r3, #0
 8000af0:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct);
 8000af2:	f107 0314 	add.w	r3, r7, #20
 8000af6:	4619      	mov	r1, r3
 8000af8:	4841      	ldr	r0, [pc, #260]	@ (8000c00 <MX_GPIO_Init+0x314>)
 8000afa:	f001 f841 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pin : ARD_D6_Pin */
  GPIO_InitStruct.Pin = ARD_D6_Pin;
 8000afe:	2302      	movs	r3, #2
 8000b00:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
 8000b02:	230b      	movs	r3, #11
 8000b04:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000b06:	2300      	movs	r3, #0
 8000b08:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(ARD_D6_GPIO_Port, &GPIO_InitStruct);
 8000b0a:	f107 0314 	add.w	r3, r7, #20
 8000b0e:	4619      	mov	r1, r3
 8000b10:	483b      	ldr	r0, [pc, #236]	@ (8000c00 <MX_GPIO_Init+0x314>)
 8000b12:	f001 f835 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D8_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin LED2_Pin
                           SPSGRF_915_SDN_Pin ARD_D5_Pin SPSGRF_915_SPI3_CSN_Pin */
  GPIO_InitStruct.Pin = ARD_D8_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin|LED2_Pin
 8000b16:	f24f 0334 	movw	r3, #61492	@ 0xf034
 8000b1a:	617b      	str	r3, [r7, #20]
                          |SPSGRF_915_SDN_Pin|ARD_D5_Pin|SPSGRF_915_SPI3_CSN_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000b1c:	2301      	movs	r3, #1
 8000b1e:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000b20:	2300      	movs	r3, #0
 8000b22:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000b24:	2300      	movs	r3, #0
 8000b26:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000b28:	f107 0314 	add.w	r3, r7, #20
 8000b2c:	4619      	mov	r1, r3
 8000b2e:	4834      	ldr	r0, [pc, #208]	@ (8000c00 <MX_GPIO_Init+0x314>)
 8000b30:	f001 f826 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin
                           PMOD_IRQ_EXTI12_Pin */
  GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin
 8000b34:	f64c 4304 	movw	r3, #52228	@ 0xcc04
 8000b38:	617b      	str	r3, [r7, #20]
                          |PMOD_IRQ_EXTI12_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 8000b3a:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
 8000b3e:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000b40:	2300      	movs	r3, #0
 8000b42:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8000b44:	f107 0314 	add.w	r3, r7, #20
 8000b48:	4619      	mov	r1, r3
 8000b4a:	482e      	ldr	r0, [pc, #184]	@ (8000c04 <MX_GPIO_Init+0x318>)
 8000b4c:	f001 f818 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */
  GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin;
 8000b50:	f243 0381 	movw	r3, #12417	@ 0x3081
 8000b54:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000b56:	2301      	movs	r3, #1
 8000b58:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000b5a:	2300      	movs	r3, #0
 8000b5c:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000b5e:	2300      	movs	r3, #0
 8000b60:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8000b62:	f107 0314 	add.w	r3, r7, #20
 8000b66:	4619      	mov	r1, r3
 8000b68:	4826      	ldr	r0, [pc, #152]	@ (8000c04 <MX_GPIO_Init+0x318>)
 8000b6a:	f001 f809 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */
  GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin;
 8000b6e:	f44f 7310 	mov.w	r3, #576	@ 0x240
 8000b72:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000b74:	2301      	movs	r3, #1
 8000b76:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000b78:	2300      	movs	r3, #0
 8000b7a:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000b7c:	2300      	movs	r3, #0
 8000b7e:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8000b80:	f107 0314 	add.w	r3, r7, #20
 8000b84:	4619      	mov	r1, r3
 8000b86:	4820      	ldr	r0, [pc, #128]	@ (8000c08 <MX_GPIO_Init+0x31c>)
 8000b88:	f000 fffa 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */
  GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin;
 8000b8c:	f44f 73c0 	mov.w	r3, #384	@ 0x180
 8000b90:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 8000b92:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
 8000b96:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000b98:	2300      	movs	r3, #0
 8000b9a:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8000b9c:	f107 0314 	add.w	r3, r7, #20
 8000ba0:	4619      	mov	r1, r3
 8000ba2:	4819      	ldr	r0, [pc, #100]	@ (8000c08 <MX_GPIO_Init+0x31c>)
 8000ba4:	f000 ffec 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pin : PMOD_SPI2_SCK_Pin */
  GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin;
 8000ba8:	2302      	movs	r3, #2
 8000baa:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000bac:	2302      	movs	r3, #2
 8000bae:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000bb0:	2300      	movs	r3, #0
 8000bb2:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000bb4:	2303      	movs	r3, #3
 8000bb6:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
 8000bb8:	2305      	movs	r3, #5
 8000bba:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct);
 8000bbc:	f107 0314 	add.w	r3, r7, #20
 8000bc0:	4619      	mov	r1, r3
 8000bc2:	4810      	ldr	r0, [pc, #64]	@ (8000c04 <MX_GPIO_Init+0x318>)
 8000bc4:	f000 ffdc 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */
  GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin;
 8000bc8:	2378      	movs	r3, #120	@ 0x78
 8000bca:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000bcc:	2302      	movs	r3, #2
 8000bce:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000bd0:	2300      	movs	r3, #0
 8000bd2:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000bd4:	2303      	movs	r3, #3
 8000bd6:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
 8000bd8:	2307      	movs	r3, #7
 8000bda:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8000bdc:	f107 0314 	add.w	r3, r7, #20
 8000be0:	4619      	mov	r1, r3
 8000be2:	4808      	ldr	r0, [pc, #32]	@ (8000c04 <MX_GPIO_Init+0x318>)
 8000be4:	f000 ffcc 	bl	8001b80 <HAL_GPIO_Init>

  /*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */
  GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin;
 8000be8:	f44f 7340 	mov.w	r3, #768	@ 0x300
 8000bec:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 8000bee:	2312      	movs	r3, #18
 8000bf0:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000bf2:	2300      	movs	r3, #0
 8000bf4:	e00a      	b.n	8000c0c <MX_GPIO_Init+0x320>
 8000bf6:	bf00      	nop
 8000bf8:	40021000 	.word	0x40021000
 8000bfc:	48001000 	.word	0x48001000
 8000c00:	48000400 	.word	0x48000400
 8000c04:	48000c00 	.word	0x48000c00
 8000c08:	48000800 	.word	0x48000800
 8000c0c:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000c0e:	2303      	movs	r3, #3
 8000c10:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
 8000c12:	2304      	movs	r3, #4
 8000c14:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000c16:	f107 0314 	add.w	r3, r7, #20
 8000c1a:	4619      	mov	r1, r3
 8000c1c:	480b      	ldr	r0, [pc, #44]	@ (8000c4c <MX_GPIO_Init+0x360>)
 8000c1e:	f000 ffaf 	bl	8001b80 <HAL_GPIO_Init>

  /* EXTI interrupt init*/
  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
 8000c22:	2200      	movs	r2, #0
 8000c24:	2105      	movs	r1, #5
 8000c26:	2017      	movs	r0, #23
 8000c28:	f000 fdf4 	bl	8001814 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
 8000c2c:	2017      	movs	r0, #23
 8000c2e:	f000 fe0d 	bl	800184c <HAL_NVIC_EnableIRQ>

  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
 8000c32:	2200      	movs	r2, #0
 8000c34:	2105      	movs	r1, #5
 8000c36:	2028      	movs	r0, #40	@ 0x28
 8000c38:	f000 fdec 	bl	8001814 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
 8000c3c:	2028      	movs	r0, #40	@ 0x28
 8000c3e:	f000 fe05 	bl	800184c <HAL_NVIC_EnableIRQ>

  /* USER CODE BEGIN MX_GPIO_Init_2 */

  /* USER CODE END MX_GPIO_Init_2 */
}
 8000c42:	bf00      	nop
 8000c44:	3728      	adds	r7, #40	@ 0x28
 8000c46:	46bd      	mov	sp, r7
 8000c48:	bd80      	pop	{r7, pc}
 8000c4a:	bf00      	nop
 8000c4c:	48000400 	.word	0x48000400

08000c50 <StartDefaultTask>:
  * @param  argument: Not used
  * @retval None
  */
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void *argument)
{
 8000c50:	b580      	push	{r7, lr}
 8000c52:	b082      	sub	sp, #8
 8000c54:	af00      	add	r7, sp, #0
 8000c56:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN 5 */
  /* Infinite loop */
  for(;;)
  {
    osDelay(1);
 8000c58:	2001      	movs	r0, #1
 8000c5a:	f005 fbbd 	bl	80063d8 <osDelay>
 8000c5e:	e7fb      	b.n	8000c58 <StartDefaultTask+0x8>

08000c60 <HAL_TIM_PeriodElapsedCallback>:
  * a global variable "uwTick" used as application time base.
  * @param  htim : TIM handle
  * @retval None
  */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 8000c60:	b580      	push	{r7, lr}
 8000c62:	b082      	sub	sp, #8
 8000c64:	af00      	add	r7, sp, #0
 8000c66:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN Callback 0 */

  /* USER CODE END Callback 0 */
  if (htim->Instance == TIM17)
 8000c68:	687b      	ldr	r3, [r7, #4]
 8000c6a:	681b      	ldr	r3, [r3, #0]
 8000c6c:	4a04      	ldr	r2, [pc, #16]	@ (8000c80 <HAL_TIM_PeriodElapsedCallback+0x20>)
 8000c6e:	4293      	cmp	r3, r2
 8000c70:	d101      	bne.n	8000c76 <HAL_TIM_PeriodElapsedCallback+0x16>
  {
    HAL_IncTick();
 8000c72:	f000 fcd3 	bl	800161c <HAL_IncTick>
  }
  /* USER CODE BEGIN Callback 1 */

  /* USER CODE END Callback 1 */
}
 8000c76:	bf00      	nop
 8000c78:	3708      	adds	r7, #8
 8000c7a:	46bd      	mov	sp, r7
 8000c7c:	bd80      	pop	{r7, pc}
 8000c7e:	bf00      	nop
 8000c80:	40014800 	.word	0x40014800

08000c84 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8000c84:	b480      	push	{r7}
 8000c86:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8000c88:	b672      	cpsid	i
}
 8000c8a:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 8000c8c:	bf00      	nop
 8000c8e:	e7fd      	b.n	8000c8c <Error_Handler+0x8>

08000c90 <CreateSerialObjects>:
TaskHandle_t hTxTask;

extern UART_HandleTypeDef huart1;

void CreateSerialObjects(void)
{
 8000c90:	b580      	push	{r7, lr}
 8000c92:	af00      	add	r7, sp, #0
	xSemaphore = xSemaphoreCreateBinary();
 8000c94:	2203      	movs	r2, #3
 8000c96:	2100      	movs	r1, #0
 8000c98:	2001      	movs	r0, #1
 8000c9a:	f005 fd88 	bl	80067ae <xQueueGenericCreate>
 8000c9e:	4603      	mov	r3, r0
 8000ca0:	4a09      	ldr	r2, [pc, #36]	@ (8000cc8 <CreateSerialObjects+0x38>)
 8000ca2:	6013      	str	r3, [r2, #0]
	xSemaphoreGive(xSemaphore);
 8000ca4:	4b08      	ldr	r3, [pc, #32]	@ (8000cc8 <CreateSerialObjects+0x38>)
 8000ca6:	6818      	ldr	r0, [r3, #0]
 8000ca8:	2300      	movs	r3, #0
 8000caa:	2200      	movs	r2, #0
 8000cac:	2100      	movs	r1, #0
 8000cae:	f005 fddd 	bl	800686c <xQueueGenericSend>
	xQueue = xQueueCreate(16, sizeof(char));
 8000cb2:	2200      	movs	r2, #0
 8000cb4:	2101      	movs	r1, #1
 8000cb6:	2010      	movs	r0, #16
 8000cb8:	f005 fd79 	bl	80067ae <xQueueGenericCreate>
 8000cbc:	4603      	mov	r3, r0
 8000cbe:	4a03      	ldr	r2, [pc, #12]	@ (8000ccc <CreateSerialObjects+0x3c>)
 8000cc0:	6013      	str	r3, [r2, #0]
}
 8000cc2:	bf00      	nop
 8000cc4:	bd80      	pop	{r7, pc}
 8000cc6:	bf00      	nop
 8000cc8:	200007b0 	.word	0x200007b0
 8000ccc:	200007ac 	.word	0x200007ac

08000cd0 <CreateSerialTask>:

void CreateSerialTask(void)
{
 8000cd0:	b580      	push	{r7, lr}
 8000cd2:	b082      	sub	sp, #8
 8000cd4:	af02      	add	r7, sp, #8
	xTaskCreate(
 8000cd6:	4b0b      	ldr	r3, [pc, #44]	@ (8000d04 <CreateSerialTask+0x34>)
 8000cd8:	9301      	str	r3, [sp, #4]
 8000cda:	2301      	movs	r3, #1
 8000cdc:	9300      	str	r3, [sp, #0]
 8000cde:	2300      	movs	r3, #0
 8000ce0:	2280      	movs	r2, #128	@ 0x80
 8000ce2:	4909      	ldr	r1, [pc, #36]	@ (8000d08 <CreateSerialTask+0x38>)
 8000ce4:	4809      	ldr	r0, [pc, #36]	@ (8000d0c <CreateSerialTask+0x3c>)
 8000ce6:	f006 fbc9 	bl	800747c <xTaskCreate>
		NULL,
		1,
		&hTxTask
	);

	xTaskCreate(
 8000cea:	4b09      	ldr	r3, [pc, #36]	@ (8000d10 <CreateSerialTask+0x40>)
 8000cec:	9301      	str	r3, [sp, #4]
 8000cee:	2301      	movs	r3, #1
 8000cf0:	9300      	str	r3, [sp, #0]
 8000cf2:	2300      	movs	r3, #0
 8000cf4:	2280      	movs	r2, #128	@ 0x80
 8000cf6:	4907      	ldr	r1, [pc, #28]	@ (8000d14 <CreateSerialTask+0x44>)
 8000cf8:	4807      	ldr	r0, [pc, #28]	@ (8000d18 <CreateSerialTask+0x48>)
 8000cfa:	f006 fbbf 	bl	800747c <xTaskCreate>
		128,
		NULL,
		1,
		&hRxTask
	);
}
 8000cfe:	bf00      	nop
 8000d00:	46bd      	mov	sp, r7
 8000d02:	bd80      	pop	{r7, pc}
 8000d04:	200007b8 	.word	0x200007b8
 8000d08:	0800956c 	.word	0x0800956c
 8000d0c:	08000d1d 	.word	0x08000d1d
 8000d10:	200007b4 	.word	0x200007b4
 8000d14:	0800957c 	.word	0x0800957c
 8000d18:	08000d59 	.word	0x08000d59

08000d1c <SerialTxTask>:

void SerialTxTask(void* pArgs)
{
 8000d1c:	b580      	push	{r7, lr}
 8000d1e:	b082      	sub	sp, #8
 8000d20:	af00      	add	r7, sp, #0
 8000d22:	6078      	str	r0, [r7, #4]
	for(;;) {
		SerialSendByte('h');
 8000d24:	2068      	movs	r0, #104	@ 0x68
 8000d26:	f000 f835 	bl	8000d94 <SerialSendByte>
		vTaskDelay(200);
 8000d2a:	20c8      	movs	r0, #200	@ 0xc8
 8000d2c:	f006 fd04 	bl	8007738 <vTaskDelay>
		SerialSendByte('o');
 8000d30:	206f      	movs	r0, #111	@ 0x6f
 8000d32:	f000 f82f 	bl	8000d94 <SerialSendByte>
		vTaskDelay(200);
 8000d36:	20c8      	movs	r0, #200	@ 0xc8
 8000d38:	f006 fcfe 	bl	8007738 <vTaskDelay>
		SerialSendByte('l');
 8000d3c:	206c      	movs	r0, #108	@ 0x6c
 8000d3e:	f000 f829 	bl	8000d94 <SerialSendByte>
		vTaskDelay(200);
 8000d42:	20c8      	movs	r0, #200	@ 0xc8
 8000d44:	f006 fcf8 	bl	8007738 <vTaskDelay>
		SerialSendByte('a');
 8000d48:	2061      	movs	r0, #97	@ 0x61
 8000d4a:	f000 f823 	bl	8000d94 <SerialSendByte>
		vTaskDelay(200);
 8000d4e:	20c8      	movs	r0, #200	@ 0xc8
 8000d50:	f006 fcf2 	bl	8007738 <vTaskDelay>
		SerialSendByte('h');
 8000d54:	bf00      	nop
 8000d56:	e7e5      	b.n	8000d24 <SerialTxTask+0x8>

08000d58 <SerialRxTask>:
	}
}

void SerialRxTask(void* pArgs)
{
 8000d58:	b580      	push	{r7, lr}
 8000d5a:	b084      	sub	sp, #16
 8000d5c:	af00      	add	r7, sp, #0
 8000d5e:	6078      	str	r0, [r7, #4]
	for(;;) {
		HAL_UART_Receive_IT(&huart1, &c, 1);
 8000d60:	2201      	movs	r2, #1
 8000d62:	4909      	ldr	r1, [pc, #36]	@ (8000d88 <SerialRxTask+0x30>)
 8000d64:	4809      	ldr	r0, [pc, #36]	@ (8000d8c <SerialRxTask+0x34>)
 8000d66:	f003 fba7 	bl	80044b8 <HAL_UART_Receive_IT>

		char data;
		while(1)
		{
			xQueueReceive(xQueue, &data, portMAX_DELAY);
 8000d6a:	4b09      	ldr	r3, [pc, #36]	@ (8000d90 <SerialRxTask+0x38>)
 8000d6c:	681b      	ldr	r3, [r3, #0]
 8000d6e:	f107 010f 	add.w	r1, r7, #15
 8000d72:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8000d76:	4618      	mov	r0, r3
 8000d78:	f005 ffa8 	bl	8006ccc <xQueueReceive>
			SerialSendByte(data);
 8000d7c:	7bfb      	ldrb	r3, [r7, #15]
 8000d7e:	4618      	mov	r0, r3
 8000d80:	f000 f808 	bl	8000d94 <SerialSendByte>
			xQueueReceive(xQueue, &data, portMAX_DELAY);
 8000d84:	bf00      	nop
 8000d86:	e7f0      	b.n	8000d6a <SerialRxTask+0x12>
 8000d88:	200007a8 	.word	0x200007a8
 8000d8c:	200001b0 	.word	0x200001b0
 8000d90:	200007ac 	.word	0x200007ac

08000d94 <SerialSendByte>:
		}
	}
}

void SerialSendByte(char data)
{
 8000d94:	b580      	push	{r7, lr}
 8000d96:	b084      	sub	sp, #16
 8000d98:	af00      	add	r7, sp, #0
 8000d9a:	4603      	mov	r3, r0
 8000d9c:	71fb      	strb	r3, [r7, #7]
	BaseType_t status = xSemaphoreTake(xSemaphore, -1);
 8000d9e:	4b0a      	ldr	r3, [pc, #40]	@ (8000dc8 <SerialSendByte+0x34>)
 8000da0:	681b      	ldr	r3, [r3, #0]
 8000da2:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8000da6:	4618      	mov	r0, r3
 8000da8:	f006 f872 	bl	8006e90 <xQueueSemaphoreTake>
 8000dac:	60f8      	str	r0, [r7, #12]
	if(status == pdTRUE)
 8000dae:	68fb      	ldr	r3, [r7, #12]
 8000db0:	2b01      	cmp	r3, #1
 8000db2:	d105      	bne.n	8000dc0 <SerialSendByte+0x2c>
		HAL_UART_Transmit_IT(&huart1, &data, 1);
 8000db4:	1dfb      	adds	r3, r7, #7
 8000db6:	2201      	movs	r2, #1
 8000db8:	4619      	mov	r1, r3
 8000dba:	4804      	ldr	r0, [pc, #16]	@ (8000dcc <SerialSendByte+0x38>)
 8000dbc:	f003 fb1e 	bl	80043fc <HAL_UART_Transmit_IT>
}
 8000dc0:	bf00      	nop
 8000dc2:	3710      	adds	r7, #16
 8000dc4:	46bd      	mov	sp, r7
 8000dc6:	bd80      	pop	{r7, pc}
 8000dc8:	200007b0 	.word	0x200007b0
 8000dcc:	200001b0 	.word	0x200001b0

08000dd0 <HAL_UART_TxCpltCallback>:

void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
 8000dd0:	b580      	push	{r7, lr}
 8000dd2:	b082      	sub	sp, #8
 8000dd4:	af00      	add	r7, sp, #0
 8000dd6:	6078      	str	r0, [r7, #4]
	static BaseType_t xHigherPriorityTaskWoken;
	xHigherPriorityTaskWoken = pdFALSE;
 8000dd8:	4b0c      	ldr	r3, [pc, #48]	@ (8000e0c <HAL_UART_TxCpltCallback+0x3c>)
 8000dda:	2200      	movs	r2, #0
 8000ddc:	601a      	str	r2, [r3, #0]
	xSemaphoreGiveFromISR(xSemaphore, &xHigherPriorityTaskWoken);
 8000dde:	4b0c      	ldr	r3, [pc, #48]	@ (8000e10 <HAL_UART_TxCpltCallback+0x40>)
 8000de0:	681b      	ldr	r3, [r3, #0]
 8000de2:	490a      	ldr	r1, [pc, #40]	@ (8000e0c <HAL_UART_TxCpltCallback+0x3c>)
 8000de4:	4618      	mov	r0, r3
 8000de6:	f005 fee1 	bl	8006bac <xQueueGiveFromISR>
	portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
 8000dea:	4b08      	ldr	r3, [pc, #32]	@ (8000e0c <HAL_UART_TxCpltCallback+0x3c>)
 8000dec:	681b      	ldr	r3, [r3, #0]
 8000dee:	2b00      	cmp	r3, #0
 8000df0:	d007      	beq.n	8000e02 <HAL_UART_TxCpltCallback+0x32>
 8000df2:	4b08      	ldr	r3, [pc, #32]	@ (8000e14 <HAL_UART_TxCpltCallback+0x44>)
 8000df4:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8000df8:	601a      	str	r2, [r3, #0]
 8000dfa:	f3bf 8f4f 	dsb	sy
 8000dfe:	f3bf 8f6f 	isb	sy
}
 8000e02:	bf00      	nop
 8000e04:	3708      	adds	r7, #8
 8000e06:	46bd      	mov	sp, r7
 8000e08:	bd80      	pop	{r7, pc}
 8000e0a:	bf00      	nop
 8000e0c:	200007bc 	.word	0x200007bc
 8000e10:	200007b0 	.word	0x200007b0
 8000e14:	e000ed04 	.word	0xe000ed04

08000e18 <HAL_UART_RxCpltCallback>:

void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
 8000e18:	b580      	push	{r7, lr}
 8000e1a:	b082      	sub	sp, #8
 8000e1c:	af00      	add	r7, sp, #0
 8000e1e:	6078      	str	r0, [r7, #4]
	static BaseType_t xHigherPriorityTaskWoken;
	xHigherPriorityTaskWoken = pdFALSE;
 8000e20:	4b0f      	ldr	r3, [pc, #60]	@ (8000e60 <HAL_UART_RxCpltCallback+0x48>)
 8000e22:	2200      	movs	r2, #0
 8000e24:	601a      	str	r2, [r3, #0]
	xQueueSendFromISR(xQueue, &c, &xHigherPriorityTaskWoken);
 8000e26:	4b0f      	ldr	r3, [pc, #60]	@ (8000e64 <HAL_UART_RxCpltCallback+0x4c>)
 8000e28:	6818      	ldr	r0, [r3, #0]
 8000e2a:	2300      	movs	r3, #0
 8000e2c:	4a0c      	ldr	r2, [pc, #48]	@ (8000e60 <HAL_UART_RxCpltCallback+0x48>)
 8000e2e:	490e      	ldr	r1, [pc, #56]	@ (8000e68 <HAL_UART_RxCpltCallback+0x50>)
 8000e30:	f005 fe1e 	bl	8006a70 <xQueueGenericSendFromISR>
	HAL_UART_Receive_IT(&huart1, &c, 1);
 8000e34:	2201      	movs	r2, #1
 8000e36:	490c      	ldr	r1, [pc, #48]	@ (8000e68 <HAL_UART_RxCpltCallback+0x50>)
 8000e38:	480c      	ldr	r0, [pc, #48]	@ (8000e6c <HAL_UART_RxCpltCallback+0x54>)
 8000e3a:	f003 fb3d 	bl	80044b8 <HAL_UART_Receive_IT>
	portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
 8000e3e:	4b08      	ldr	r3, [pc, #32]	@ (8000e60 <HAL_UART_RxCpltCallback+0x48>)
 8000e40:	681b      	ldr	r3, [r3, #0]
 8000e42:	2b00      	cmp	r3, #0
 8000e44:	d007      	beq.n	8000e56 <HAL_UART_RxCpltCallback+0x3e>
 8000e46:	4b0a      	ldr	r3, [pc, #40]	@ (8000e70 <HAL_UART_RxCpltCallback+0x58>)
 8000e48:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8000e4c:	601a      	str	r2, [r3, #0]
 8000e4e:	f3bf 8f4f 	dsb	sy
 8000e52:	f3bf 8f6f 	isb	sy

}
 8000e56:	bf00      	nop
 8000e58:	3708      	adds	r7, #8
 8000e5a:	46bd      	mov	sp, r7
 8000e5c:	bd80      	pop	{r7, pc}
 8000e5e:	bf00      	nop
 8000e60:	200007c0 	.word	0x200007c0
 8000e64:	200007ac 	.word	0x200007ac
 8000e68:	200007a8 	.word	0x200007a8
 8000e6c:	200001b0 	.word	0x200001b0
 8000e70:	e000ed04 	.word	0xe000ed04

08000e74 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8000e74:	b580      	push	{r7, lr}
 8000e76:	b082      	sub	sp, #8
 8000e78:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8000e7a:	4b11      	ldr	r3, [pc, #68]	@ (8000ec0 <HAL_MspInit+0x4c>)
 8000e7c:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8000e7e:	4a10      	ldr	r2, [pc, #64]	@ (8000ec0 <HAL_MspInit+0x4c>)
 8000e80:	f043 0301 	orr.w	r3, r3, #1
 8000e84:	6613      	str	r3, [r2, #96]	@ 0x60
 8000e86:	4b0e      	ldr	r3, [pc, #56]	@ (8000ec0 <HAL_MspInit+0x4c>)
 8000e88:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8000e8a:	f003 0301 	and.w	r3, r3, #1
 8000e8e:	607b      	str	r3, [r7, #4]
 8000e90:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 8000e92:	4b0b      	ldr	r3, [pc, #44]	@ (8000ec0 <HAL_MspInit+0x4c>)
 8000e94:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8000e96:	4a0a      	ldr	r2, [pc, #40]	@ (8000ec0 <HAL_MspInit+0x4c>)
 8000e98:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8000e9c:	6593      	str	r3, [r2, #88]	@ 0x58
 8000e9e:	4b08      	ldr	r3, [pc, #32]	@ (8000ec0 <HAL_MspInit+0x4c>)
 8000ea0:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8000ea2:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8000ea6:	603b      	str	r3, [r7, #0]
 8000ea8:	683b      	ldr	r3, [r7, #0]

  /* System interrupt init*/
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 8000eaa:	2200      	movs	r2, #0
 8000eac:	210f      	movs	r1, #15
 8000eae:	f06f 0001 	mvn.w	r0, #1
 8000eb2:	f000 fcaf 	bl	8001814 <HAL_NVIC_SetPriority>

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8000eb6:	bf00      	nop
 8000eb8:	3708      	adds	r7, #8
 8000eba:	46bd      	mov	sp, r7
 8000ebc:	bd80      	pop	{r7, pc}
 8000ebe:	bf00      	nop
 8000ec0:	40021000 	.word	0x40021000

08000ec4 <HAL_DFSDM_ChannelMspInit>:
  * This function configures the hardware resources used in this example
  * @param hdfsdm_channel: DFSDM_Channel handle pointer
  * @retval None
  */
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)
{
 8000ec4:	b580      	push	{r7, lr}
 8000ec6:	b0ac      	sub	sp, #176	@ 0xb0
 8000ec8:	af00      	add	r7, sp, #0
 8000eca:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000ecc:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8000ed0:	2200      	movs	r2, #0
 8000ed2:	601a      	str	r2, [r3, #0]
 8000ed4:	605a      	str	r2, [r3, #4]
 8000ed6:	609a      	str	r2, [r3, #8]
 8000ed8:	60da      	str	r2, [r3, #12]
 8000eda:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000edc:	f107 0314 	add.w	r3, r7, #20
 8000ee0:	2288      	movs	r2, #136	@ 0x88
 8000ee2:	2100      	movs	r1, #0
 8000ee4:	4618      	mov	r0, r3
 8000ee6:	f008 fa3f 	bl	8009368 <memset>
  if(DFSDM1_Init == 0)
 8000eea:	4b25      	ldr	r3, [pc, #148]	@ (8000f80 <HAL_DFSDM_ChannelMspInit+0xbc>)
 8000eec:	681b      	ldr	r3, [r3, #0]
 8000eee:	2b00      	cmp	r3, #0
 8000ef0:	d142      	bne.n	8000f78 <HAL_DFSDM_ChannelMspInit+0xb4>

    /* USER CODE END DFSDM1_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1;
 8000ef2:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
 8000ef6:	617b      	str	r3, [r7, #20]
    PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
 8000ef8:	2300      	movs	r3, #0
 8000efa:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8000efe:	f107 0314 	add.w	r3, r7, #20
 8000f02:	4618      	mov	r0, r3
 8000f04:	f002 f9f8 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 8000f08:	4603      	mov	r3, r0
 8000f0a:	2b00      	cmp	r3, #0
 8000f0c:	d001      	beq.n	8000f12 <HAL_DFSDM_ChannelMspInit+0x4e>
    {
      Error_Handler();
 8000f0e:	f7ff feb9 	bl	8000c84 <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_DFSDM1_CLK_ENABLE();
 8000f12:	4b1c      	ldr	r3, [pc, #112]	@ (8000f84 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8000f14:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8000f16:	4a1b      	ldr	r2, [pc, #108]	@ (8000f84 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8000f18:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8000f1c:	6613      	str	r3, [r2, #96]	@ 0x60
 8000f1e:	4b19      	ldr	r3, [pc, #100]	@ (8000f84 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8000f20:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8000f22:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 8000f26:	613b      	str	r3, [r7, #16]
 8000f28:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOE_CLK_ENABLE();
 8000f2a:	4b16      	ldr	r3, [pc, #88]	@ (8000f84 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8000f2c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000f2e:	4a15      	ldr	r2, [pc, #84]	@ (8000f84 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8000f30:	f043 0310 	orr.w	r3, r3, #16
 8000f34:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000f36:	4b13      	ldr	r3, [pc, #76]	@ (8000f84 <HAL_DFSDM_ChannelMspInit+0xc0>)
 8000f38:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000f3a:	f003 0310 	and.w	r3, r3, #16
 8000f3e:	60fb      	str	r3, [r7, #12]
 8000f40:	68fb      	ldr	r3, [r7, #12]
    /**DFSDM1 GPIO Configuration
    PE7     ------> DFSDM1_DATIN2
    PE9     ------> DFSDM1_CKOUT
    */
    GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin;
 8000f42:	f44f 7320 	mov.w	r3, #640	@ 0x280
 8000f46:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000f4a:	2302      	movs	r3, #2
 8000f4c:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000f50:	2300      	movs	r3, #0
 8000f52:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000f56:	2300      	movs	r3, #0
 8000f58:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1;
 8000f5c:	2306      	movs	r3, #6
 8000f5e:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8000f62:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8000f66:	4619      	mov	r1, r3
 8000f68:	4807      	ldr	r0, [pc, #28]	@ (8000f88 <HAL_DFSDM_ChannelMspInit+0xc4>)
 8000f6a:	f000 fe09 	bl	8001b80 <HAL_GPIO_Init>

    /* USER CODE BEGIN DFSDM1_MspInit 1 */

    /* USER CODE END DFSDM1_MspInit 1 */

  DFSDM1_Init++;
 8000f6e:	4b04      	ldr	r3, [pc, #16]	@ (8000f80 <HAL_DFSDM_ChannelMspInit+0xbc>)
 8000f70:	681b      	ldr	r3, [r3, #0]
 8000f72:	3301      	adds	r3, #1
 8000f74:	4a02      	ldr	r2, [pc, #8]	@ (8000f80 <HAL_DFSDM_ChannelMspInit+0xbc>)
 8000f76:	6013      	str	r3, [r2, #0]
  }

}
 8000f78:	bf00      	nop
 8000f7a:	37b0      	adds	r7, #176	@ 0xb0
 8000f7c:	46bd      	mov	sp, r7
 8000f7e:	bd80      	pop	{r7, pc}
 8000f80:	200007c4 	.word	0x200007c4
 8000f84:	40021000 	.word	0x40021000
 8000f88:	48001000 	.word	0x48001000

08000f8c <HAL_I2C_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hi2c: I2C handle pointer
  * @retval None
  */
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
 8000f8c:	b580      	push	{r7, lr}
 8000f8e:	b0ac      	sub	sp, #176	@ 0xb0
 8000f90:	af00      	add	r7, sp, #0
 8000f92:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000f94:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8000f98:	2200      	movs	r2, #0
 8000f9a:	601a      	str	r2, [r3, #0]
 8000f9c:	605a      	str	r2, [r3, #4]
 8000f9e:	609a      	str	r2, [r3, #8]
 8000fa0:	60da      	str	r2, [r3, #12]
 8000fa2:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000fa4:	f107 0314 	add.w	r3, r7, #20
 8000fa8:	2288      	movs	r2, #136	@ 0x88
 8000faa:	2100      	movs	r1, #0
 8000fac:	4618      	mov	r0, r3
 8000fae:	f008 f9db 	bl	8009368 <memset>
  if(hi2c->Instance==I2C2)
 8000fb2:	687b      	ldr	r3, [r7, #4]
 8000fb4:	681b      	ldr	r3, [r3, #0]
 8000fb6:	4a21      	ldr	r2, [pc, #132]	@ (800103c <HAL_I2C_MspInit+0xb0>)
 8000fb8:	4293      	cmp	r3, r2
 8000fba:	d13b      	bne.n	8001034 <HAL_I2C_MspInit+0xa8>

    /* USER CODE END I2C2_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
 8000fbc:	2380      	movs	r3, #128	@ 0x80
 8000fbe:	617b      	str	r3, [r7, #20]
    PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
 8000fc0:	2300      	movs	r3, #0
 8000fc2:	66bb      	str	r3, [r7, #104]	@ 0x68
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8000fc4:	f107 0314 	add.w	r3, r7, #20
 8000fc8:	4618      	mov	r0, r3
 8000fca:	f002 f995 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 8000fce:	4603      	mov	r3, r0
 8000fd0:	2b00      	cmp	r3, #0
 8000fd2:	d001      	beq.n	8000fd8 <HAL_I2C_MspInit+0x4c>
    {
      Error_Handler();
 8000fd4:	f7ff fe56 	bl	8000c84 <Error_Handler>
    }

    __HAL_RCC_GPIOB_CLK_ENABLE();
 8000fd8:	4b19      	ldr	r3, [pc, #100]	@ (8001040 <HAL_I2C_MspInit+0xb4>)
 8000fda:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000fdc:	4a18      	ldr	r2, [pc, #96]	@ (8001040 <HAL_I2C_MspInit+0xb4>)
 8000fde:	f043 0302 	orr.w	r3, r3, #2
 8000fe2:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8000fe4:	4b16      	ldr	r3, [pc, #88]	@ (8001040 <HAL_I2C_MspInit+0xb4>)
 8000fe6:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8000fe8:	f003 0302 	and.w	r3, r3, #2
 8000fec:	613b      	str	r3, [r7, #16]
 8000fee:	693b      	ldr	r3, [r7, #16]
    /**I2C2 GPIO Configuration
    PB10     ------> I2C2_SCL
    PB11     ------> I2C2_SDA
    */
    GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin;
 8000ff0:	f44f 6340 	mov.w	r3, #3072	@ 0xc00
 8000ff4:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 8000ff8:	2312      	movs	r3, #18
 8000ffa:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    GPIO_InitStruct.Pull = GPIO_PULLUP;
 8000ffe:	2301      	movs	r3, #1
 8001000:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8001004:	2303      	movs	r3, #3
 8001006:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
 800100a:	2304      	movs	r3, #4
 800100c:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001010:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8001014:	4619      	mov	r1, r3
 8001016:	480b      	ldr	r0, [pc, #44]	@ (8001044 <HAL_I2C_MspInit+0xb8>)
 8001018:	f000 fdb2 	bl	8001b80 <HAL_GPIO_Init>

    /* Peripheral clock enable */
    __HAL_RCC_I2C2_CLK_ENABLE();
 800101c:	4b08      	ldr	r3, [pc, #32]	@ (8001040 <HAL_I2C_MspInit+0xb4>)
 800101e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8001020:	4a07      	ldr	r2, [pc, #28]	@ (8001040 <HAL_I2C_MspInit+0xb4>)
 8001022:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
 8001026:	6593      	str	r3, [r2, #88]	@ 0x58
 8001028:	4b05      	ldr	r3, [pc, #20]	@ (8001040 <HAL_I2C_MspInit+0xb4>)
 800102a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800102c:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 8001030:	60fb      	str	r3, [r7, #12]
 8001032:	68fb      	ldr	r3, [r7, #12]

    /* USER CODE END I2C2_MspInit 1 */

  }

}
 8001034:	bf00      	nop
 8001036:	37b0      	adds	r7, #176	@ 0xb0
 8001038:	46bd      	mov	sp, r7
 800103a:	bd80      	pop	{r7, pc}
 800103c:	40005800 	.word	0x40005800
 8001040:	40021000 	.word	0x40021000
 8001044:	48000400 	.word	0x48000400

08001048 <HAL_QSPI_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hqspi: QSPI handle pointer
  * @retval None
  */
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
{
 8001048:	b580      	push	{r7, lr}
 800104a:	b08a      	sub	sp, #40	@ 0x28
 800104c:	af00      	add	r7, sp, #0
 800104e:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001050:	f107 0314 	add.w	r3, r7, #20
 8001054:	2200      	movs	r2, #0
 8001056:	601a      	str	r2, [r3, #0]
 8001058:	605a      	str	r2, [r3, #4]
 800105a:	609a      	str	r2, [r3, #8]
 800105c:	60da      	str	r2, [r3, #12]
 800105e:	611a      	str	r2, [r3, #16]
  if(hqspi->Instance==QUADSPI)
 8001060:	687b      	ldr	r3, [r7, #4]
 8001062:	681b      	ldr	r3, [r3, #0]
 8001064:	4a17      	ldr	r2, [pc, #92]	@ (80010c4 <HAL_QSPI_MspInit+0x7c>)
 8001066:	4293      	cmp	r3, r2
 8001068:	d128      	bne.n	80010bc <HAL_QSPI_MspInit+0x74>
  {
    /* USER CODE BEGIN QUADSPI_MspInit 0 */

    /* USER CODE END QUADSPI_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_QSPI_CLK_ENABLE();
 800106a:	4b17      	ldr	r3, [pc, #92]	@ (80010c8 <HAL_QSPI_MspInit+0x80>)
 800106c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800106e:	4a16      	ldr	r2, [pc, #88]	@ (80010c8 <HAL_QSPI_MspInit+0x80>)
 8001070:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8001074:	6513      	str	r3, [r2, #80]	@ 0x50
 8001076:	4b14      	ldr	r3, [pc, #80]	@ (80010c8 <HAL_QSPI_MspInit+0x80>)
 8001078:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800107a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800107e:	613b      	str	r3, [r7, #16]
 8001080:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOE_CLK_ENABLE();
 8001082:	4b11      	ldr	r3, [pc, #68]	@ (80010c8 <HAL_QSPI_MspInit+0x80>)
 8001084:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001086:	4a10      	ldr	r2, [pc, #64]	@ (80010c8 <HAL_QSPI_MspInit+0x80>)
 8001088:	f043 0310 	orr.w	r3, r3, #16
 800108c:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800108e:	4b0e      	ldr	r3, [pc, #56]	@ (80010c8 <HAL_QSPI_MspInit+0x80>)
 8001090:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001092:	f003 0310 	and.w	r3, r3, #16
 8001096:	60fb      	str	r3, [r7, #12]
 8001098:	68fb      	ldr	r3, [r7, #12]
    PE12     ------> QUADSPI_BK1_IO0
    PE13     ------> QUADSPI_BK1_IO1
    PE14     ------> QUADSPI_BK1_IO2
    PE15     ------> QUADSPI_BK1_IO3
    */
    GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin
 800109a:	f44f 437c 	mov.w	r3, #64512	@ 0xfc00
 800109e:	617b      	str	r3, [r7, #20]
                          |QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 80010a0:	2302      	movs	r3, #2
 80010a2:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80010a4:	2300      	movs	r3, #0
 80010a6:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 80010a8:	2303      	movs	r3, #3
 80010aa:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
 80010ac:	230a      	movs	r3, #10
 80010ae:	627b      	str	r3, [r7, #36]	@ 0x24
    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 80010b0:	f107 0314 	add.w	r3, r7, #20
 80010b4:	4619      	mov	r1, r3
 80010b6:	4805      	ldr	r0, [pc, #20]	@ (80010cc <HAL_QSPI_MspInit+0x84>)
 80010b8:	f000 fd62 	bl	8001b80 <HAL_GPIO_Init>

    /* USER CODE END QUADSPI_MspInit 1 */

  }

}
 80010bc:	bf00      	nop
 80010be:	3728      	adds	r7, #40	@ 0x28
 80010c0:	46bd      	mov	sp, r7
 80010c2:	bd80      	pop	{r7, pc}
 80010c4:	a0001000 	.word	0xa0001000
 80010c8:	40021000 	.word	0x40021000
 80010cc:	48001000 	.word	0x48001000

080010d0 <HAL_SPI_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hspi: SPI handle pointer
  * @retval None
  */
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
 80010d0:	b580      	push	{r7, lr}
 80010d2:	b08a      	sub	sp, #40	@ 0x28
 80010d4:	af00      	add	r7, sp, #0
 80010d6:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80010d8:	f107 0314 	add.w	r3, r7, #20
 80010dc:	2200      	movs	r2, #0
 80010de:	601a      	str	r2, [r3, #0]
 80010e0:	605a      	str	r2, [r3, #4]
 80010e2:	609a      	str	r2, [r3, #8]
 80010e4:	60da      	str	r2, [r3, #12]
 80010e6:	611a      	str	r2, [r3, #16]
  if(hspi->Instance==SPI3)
 80010e8:	687b      	ldr	r3, [r7, #4]
 80010ea:	681b      	ldr	r3, [r3, #0]
 80010ec:	4a17      	ldr	r2, [pc, #92]	@ (800114c <HAL_SPI_MspInit+0x7c>)
 80010ee:	4293      	cmp	r3, r2
 80010f0:	d128      	bne.n	8001144 <HAL_SPI_MspInit+0x74>
  {
    /* USER CODE BEGIN SPI3_MspInit 0 */

    /* USER CODE END SPI3_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_SPI3_CLK_ENABLE();
 80010f2:	4b17      	ldr	r3, [pc, #92]	@ (8001150 <HAL_SPI_MspInit+0x80>)
 80010f4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80010f6:	4a16      	ldr	r2, [pc, #88]	@ (8001150 <HAL_SPI_MspInit+0x80>)
 80010f8:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
 80010fc:	6593      	str	r3, [r2, #88]	@ 0x58
 80010fe:	4b14      	ldr	r3, [pc, #80]	@ (8001150 <HAL_SPI_MspInit+0x80>)
 8001100:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8001102:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8001106:	613b      	str	r3, [r7, #16]
 8001108:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOC_CLK_ENABLE();
 800110a:	4b11      	ldr	r3, [pc, #68]	@ (8001150 <HAL_SPI_MspInit+0x80>)
 800110c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800110e:	4a10      	ldr	r2, [pc, #64]	@ (8001150 <HAL_SPI_MspInit+0x80>)
 8001110:	f043 0304 	orr.w	r3, r3, #4
 8001114:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8001116:	4b0e      	ldr	r3, [pc, #56]	@ (8001150 <HAL_SPI_MspInit+0x80>)
 8001118:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800111a:	f003 0304 	and.w	r3, r3, #4
 800111e:	60fb      	str	r3, [r7, #12]
 8001120:	68fb      	ldr	r3, [r7, #12]
    /**SPI3 GPIO Configuration
    PC10     ------> SPI3_SCK
    PC11     ------> SPI3_MISO
    PC12     ------> SPI3_MOSI
    */
    GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin;
 8001122:	f44f 53e0 	mov.w	r3, #7168	@ 0x1c00
 8001126:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8001128:	2302      	movs	r3, #2
 800112a:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800112c:	2300      	movs	r3, #0
 800112e:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8001130:	2303      	movs	r3, #3
 8001132:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
 8001134:	2306      	movs	r3, #6
 8001136:	627b      	str	r3, [r7, #36]	@ 0x24
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001138:	f107 0314 	add.w	r3, r7, #20
 800113c:	4619      	mov	r1, r3
 800113e:	4805      	ldr	r0, [pc, #20]	@ (8001154 <HAL_SPI_MspInit+0x84>)
 8001140:	f000 fd1e 	bl	8001b80 <HAL_GPIO_Init>

    /* USER CODE END SPI3_MspInit 1 */

  }

}
 8001144:	bf00      	nop
 8001146:	3728      	adds	r7, #40	@ 0x28
 8001148:	46bd      	mov	sp, r7
 800114a:	bd80      	pop	{r7, pc}
 800114c:	40003c00 	.word	0x40003c00
 8001150:	40021000 	.word	0x40021000
 8001154:	48000800 	.word	0x48000800

08001158 <HAL_UART_MspInit>:
  * This function configures the hardware resources used in this example
  * @param huart: UART handle pointer
  * @retval None
  */
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8001158:	b580      	push	{r7, lr}
 800115a:	b0ae      	sub	sp, #184	@ 0xb8
 800115c:	af00      	add	r7, sp, #0
 800115e:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001160:	f107 03a4 	add.w	r3, r7, #164	@ 0xa4
 8001164:	2200      	movs	r2, #0
 8001166:	601a      	str	r2, [r3, #0]
 8001168:	605a      	str	r2, [r3, #4]
 800116a:	609a      	str	r2, [r3, #8]
 800116c:	60da      	str	r2, [r3, #12]
 800116e:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8001170:	f107 031c 	add.w	r3, r7, #28
 8001174:	2288      	movs	r2, #136	@ 0x88
 8001176:	2100      	movs	r1, #0
 8001178:	4618      	mov	r0, r3
 800117a:	f008 f8f5 	bl	8009368 <memset>
  if(huart->Instance==USART1)
 800117e:	687b      	ldr	r3, [r7, #4]
 8001180:	681b      	ldr	r3, [r3, #0]
 8001182:	4a46      	ldr	r2, [pc, #280]	@ (800129c <HAL_UART_MspInit+0x144>)
 8001184:	4293      	cmp	r3, r2
 8001186:	d143      	bne.n	8001210 <HAL_UART_MspInit+0xb8>

    /* USER CODE END USART1_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
 8001188:	2301      	movs	r3, #1
 800118a:	61fb      	str	r3, [r7, #28]
    PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
 800118c:	2300      	movs	r3, #0
 800118e:	657b      	str	r3, [r7, #84]	@ 0x54
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8001190:	f107 031c 	add.w	r3, r7, #28
 8001194:	4618      	mov	r0, r3
 8001196:	f002 f8af 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 800119a:	4603      	mov	r3, r0
 800119c:	2b00      	cmp	r3, #0
 800119e:	d001      	beq.n	80011a4 <HAL_UART_MspInit+0x4c>
    {
      Error_Handler();
 80011a0:	f7ff fd70 	bl	8000c84 <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 80011a4:	4b3e      	ldr	r3, [pc, #248]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 80011a6:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80011a8:	4a3d      	ldr	r2, [pc, #244]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 80011aa:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
 80011ae:	6613      	str	r3, [r2, #96]	@ 0x60
 80011b0:	4b3b      	ldr	r3, [pc, #236]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 80011b2:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80011b4:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 80011b8:	61bb      	str	r3, [r7, #24]
 80011ba:	69bb      	ldr	r3, [r7, #24]

    __HAL_RCC_GPIOB_CLK_ENABLE();
 80011bc:	4b38      	ldr	r3, [pc, #224]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 80011be:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80011c0:	4a37      	ldr	r2, [pc, #220]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 80011c2:	f043 0302 	orr.w	r3, r3, #2
 80011c6:	64d3      	str	r3, [r2, #76]	@ 0x4c
 80011c8:	4b35      	ldr	r3, [pc, #212]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 80011ca:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80011cc:	f003 0302 	and.w	r3, r3, #2
 80011d0:	617b      	str	r3, [r7, #20]
 80011d2:	697b      	ldr	r3, [r7, #20]
    /**USART1 GPIO Configuration
    PB6     ------> USART1_TX
    PB7     ------> USART1_RX
    */
    GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin;
 80011d4:	23c0      	movs	r3, #192	@ 0xc0
 80011d6:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 80011da:	2302      	movs	r3, #2
 80011dc:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80011e0:	2300      	movs	r3, #0
 80011e2:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 80011e6:	2303      	movs	r3, #3
 80011e8:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
 80011ec:	2307      	movs	r3, #7
 80011ee:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 80011f2:	f107 03a4 	add.w	r3, r7, #164	@ 0xa4
 80011f6:	4619      	mov	r1, r3
 80011f8:	482a      	ldr	r0, [pc, #168]	@ (80012a4 <HAL_UART_MspInit+0x14c>)
 80011fa:	f000 fcc1 	bl	8001b80 <HAL_GPIO_Init>

    /* USART1 interrupt Init */
    HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
 80011fe:	2200      	movs	r2, #0
 8001200:	2105      	movs	r1, #5
 8001202:	2025      	movs	r0, #37	@ 0x25
 8001204:	f000 fb06 	bl	8001814 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(USART1_IRQn);
 8001208:	2025      	movs	r0, #37	@ 0x25
 800120a:	f000 fb1f 	bl	800184c <HAL_NVIC_EnableIRQ>
    /* USER CODE BEGIN USART3_MspInit 1 */

    /* USER CODE END USART3_MspInit 1 */
  }

}
 800120e:	e040      	b.n	8001292 <HAL_UART_MspInit+0x13a>
  else if(huart->Instance==USART3)
 8001210:	687b      	ldr	r3, [r7, #4]
 8001212:	681b      	ldr	r3, [r3, #0]
 8001214:	4a24      	ldr	r2, [pc, #144]	@ (80012a8 <HAL_UART_MspInit+0x150>)
 8001216:	4293      	cmp	r3, r2
 8001218:	d13b      	bne.n	8001292 <HAL_UART_MspInit+0x13a>
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3;
 800121a:	2304      	movs	r3, #4
 800121c:	61fb      	str	r3, [r7, #28]
    PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
 800121e:	2300      	movs	r3, #0
 8001220:	65fb      	str	r3, [r7, #92]	@ 0x5c
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8001222:	f107 031c 	add.w	r3, r7, #28
 8001226:	4618      	mov	r0, r3
 8001228:	f002 f866 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 800122c:	4603      	mov	r3, r0
 800122e:	2b00      	cmp	r3, #0
 8001230:	d001      	beq.n	8001236 <HAL_UART_MspInit+0xde>
      Error_Handler();
 8001232:	f7ff fd27 	bl	8000c84 <Error_Handler>
    __HAL_RCC_USART3_CLK_ENABLE();
 8001236:	4b1a      	ldr	r3, [pc, #104]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 8001238:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800123a:	4a19      	ldr	r2, [pc, #100]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 800123c:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 8001240:	6593      	str	r3, [r2, #88]	@ 0x58
 8001242:	4b17      	ldr	r3, [pc, #92]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 8001244:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8001246:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 800124a:	613b      	str	r3, [r7, #16]
 800124c:	693b      	ldr	r3, [r7, #16]
    __HAL_RCC_GPIOD_CLK_ENABLE();
 800124e:	4b14      	ldr	r3, [pc, #80]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 8001250:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001252:	4a13      	ldr	r2, [pc, #76]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 8001254:	f043 0308 	orr.w	r3, r3, #8
 8001258:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800125a:	4b11      	ldr	r3, [pc, #68]	@ (80012a0 <HAL_UART_MspInit+0x148>)
 800125c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800125e:	f003 0308 	and.w	r3, r3, #8
 8001262:	60fb      	str	r3, [r7, #12]
 8001264:	68fb      	ldr	r3, [r7, #12]
    GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin;
 8001266:	f44f 7340 	mov.w	r3, #768	@ 0x300
 800126a:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800126e:	2302      	movs	r3, #2
 8001270:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001274:	2300      	movs	r3, #0
 8001276:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 800127a:	2303      	movs	r3, #3
 800127c:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
 8001280:	2307      	movs	r3, #7
 8001282:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8001286:	f107 03a4 	add.w	r3, r7, #164	@ 0xa4
 800128a:	4619      	mov	r1, r3
 800128c:	4807      	ldr	r0, [pc, #28]	@ (80012ac <HAL_UART_MspInit+0x154>)
 800128e:	f000 fc77 	bl	8001b80 <HAL_GPIO_Init>
}
 8001292:	bf00      	nop
 8001294:	37b8      	adds	r7, #184	@ 0xb8
 8001296:	46bd      	mov	sp, r7
 8001298:	bd80      	pop	{r7, pc}
 800129a:	bf00      	nop
 800129c:	40013800 	.word	0x40013800
 80012a0:	40021000 	.word	0x40021000
 80012a4:	48000400 	.word	0x48000400
 80012a8:	40004800 	.word	0x40004800
 80012ac:	48000c00 	.word	0x48000c00

080012b0 <HAL_PCD_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hpcd: PCD handle pointer
  * @retval None
  */
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
 80012b0:	b580      	push	{r7, lr}
 80012b2:	b0ac      	sub	sp, #176	@ 0xb0
 80012b4:	af00      	add	r7, sp, #0
 80012b6:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80012b8:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 80012bc:	2200      	movs	r2, #0
 80012be:	601a      	str	r2, [r3, #0]
 80012c0:	605a      	str	r2, [r3, #4]
 80012c2:	609a      	str	r2, [r3, #8]
 80012c4:	60da      	str	r2, [r3, #12]
 80012c6:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 80012c8:	f107 0314 	add.w	r3, r7, #20
 80012cc:	2288      	movs	r2, #136	@ 0x88
 80012ce:	2100      	movs	r1, #0
 80012d0:	4618      	mov	r0, r3
 80012d2:	f008 f849 	bl	8009368 <memset>
  if(hpcd->Instance==USB_OTG_FS)
 80012d6:	687b      	ldr	r3, [r7, #4]
 80012d8:	681b      	ldr	r3, [r3, #0]
 80012da:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 80012de:	d17c      	bne.n	80013da <HAL_PCD_MspInit+0x12a>

    /* USER CODE END USB_OTG_FS_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
 80012e0:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
 80012e4:	617b      	str	r3, [r7, #20]
    PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
 80012e6:	f04f 6380 	mov.w	r3, #67108864	@ 0x4000000
 80012ea:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
    PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
 80012ee:	2301      	movs	r3, #1
 80012f0:	61bb      	str	r3, [r7, #24]
    PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
 80012f2:	2301      	movs	r3, #1
 80012f4:	61fb      	str	r3, [r7, #28]
    PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
 80012f6:	2318      	movs	r3, #24
 80012f8:	623b      	str	r3, [r7, #32]
    PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
 80012fa:	2307      	movs	r3, #7
 80012fc:	627b      	str	r3, [r7, #36]	@ 0x24
    PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
 80012fe:	2302      	movs	r3, #2
 8001300:	62bb      	str	r3, [r7, #40]	@ 0x28
    PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
 8001302:	2302      	movs	r3, #2
 8001304:	62fb      	str	r3, [r7, #44]	@ 0x2c
    PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
 8001306:	f44f 1380 	mov.w	r3, #1048576	@ 0x100000
 800130a:	633b      	str	r3, [r7, #48]	@ 0x30
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 800130c:	f107 0314 	add.w	r3, r7, #20
 8001310:	4618      	mov	r0, r3
 8001312:	f001 fff1 	bl	80032f8 <HAL_RCCEx_PeriphCLKConfig>
 8001316:	4603      	mov	r3, r0
 8001318:	2b00      	cmp	r3, #0
 800131a:	d001      	beq.n	8001320 <HAL_PCD_MspInit+0x70>
    {
      Error_Handler();
 800131c:	f7ff fcb2 	bl	8000c84 <Error_Handler>
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8001320:	4b30      	ldr	r3, [pc, #192]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 8001322:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001324:	4a2f      	ldr	r2, [pc, #188]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 8001326:	f043 0301 	orr.w	r3, r3, #1
 800132a:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800132c:	4b2d      	ldr	r3, [pc, #180]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 800132e:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001330:	f003 0301 	and.w	r3, r3, #1
 8001334:	613b      	str	r3, [r7, #16]
 8001336:	693b      	ldr	r3, [r7, #16]
    PA9     ------> USB_OTG_FS_VBUS
    PA10     ------> USB_OTG_FS_ID
    PA11     ------> USB_OTG_FS_DM
    PA12     ------> USB_OTG_FS_DP
    */
    GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin;
 8001338:	f44f 7300 	mov.w	r3, #512	@ 0x200
 800133c:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001340:	2300      	movs	r3, #0
 8001342:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001346:	2300      	movs	r3, #0
 8001348:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
 800134c:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8001350:	4619      	mov	r1, r3
 8001352:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8001356:	f000 fc13 	bl	8001b80 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin;
 800135a:	f44f 53e0 	mov.w	r3, #7168	@ 0x1c00
 800135e:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8001362:	2302      	movs	r3, #2
 8001364:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001368:	2300      	movs	r3, #0
 800136a:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 800136e:	2303      	movs	r3, #3
 8001370:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
 8001374:	230a      	movs	r3, #10
 8001376:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800137a:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 800137e:	4619      	mov	r1, r3
 8001380:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8001384:	f000 fbfc 	bl	8001b80 <HAL_GPIO_Init>

    /* Peripheral clock enable */
    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 8001388:	4b16      	ldr	r3, [pc, #88]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 800138a:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800138c:	4a15      	ldr	r2, [pc, #84]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 800138e:	f443 5380 	orr.w	r3, r3, #4096	@ 0x1000
 8001392:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8001394:	4b13      	ldr	r3, [pc, #76]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 8001396:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8001398:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 800139c:	60fb      	str	r3, [r7, #12]
 800139e:	68fb      	ldr	r3, [r7, #12]

    /* Enable VDDUSB */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 80013a0:	4b10      	ldr	r3, [pc, #64]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 80013a2:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80013a4:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 80013a8:	2b00      	cmp	r3, #0
 80013aa:	d114      	bne.n	80013d6 <HAL_PCD_MspInit+0x126>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 80013ac:	4b0d      	ldr	r3, [pc, #52]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 80013ae:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80013b0:	4a0c      	ldr	r2, [pc, #48]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 80013b2:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 80013b6:	6593      	str	r3, [r2, #88]	@ 0x58
 80013b8:	4b0a      	ldr	r3, [pc, #40]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 80013ba:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80013bc:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 80013c0:	60bb      	str	r3, [r7, #8]
 80013c2:	68bb      	ldr	r3, [r7, #8]
      HAL_PWREx_EnableVddUSB();
 80013c4:	f001 f89a 	bl	80024fc <HAL_PWREx_EnableVddUSB>
      __HAL_RCC_PWR_CLK_DISABLE();
 80013c8:	4b06      	ldr	r3, [pc, #24]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 80013ca:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80013cc:	4a05      	ldr	r2, [pc, #20]	@ (80013e4 <HAL_PCD_MspInit+0x134>)
 80013ce:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 80013d2:	6593      	str	r3, [r2, #88]	@ 0x58

    /* USER CODE END USB_OTG_FS_MspInit 1 */

  }

}
 80013d4:	e001      	b.n	80013da <HAL_PCD_MspInit+0x12a>
      HAL_PWREx_EnableVddUSB();
 80013d6:	f001 f891 	bl	80024fc <HAL_PWREx_EnableVddUSB>
}
 80013da:	bf00      	nop
 80013dc:	37b0      	adds	r7, #176	@ 0xb0
 80013de:	46bd      	mov	sp, r7
 80013e0:	bd80      	pop	{r7, pc}
 80013e2:	bf00      	nop
 80013e4:	40021000 	.word	0x40021000

080013e8 <HAL_InitTick>:
  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
  * @param  TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 80013e8:	b580      	push	{r7, lr}
 80013ea:	b08c      	sub	sp, #48	@ 0x30
 80013ec:	af00      	add	r7, sp, #0
 80013ee:	6078      	str	r0, [r7, #4]
  RCC_ClkInitTypeDef    clkconfig;
  uint32_t              uwTimclock;
  uint32_t              uwPrescalerValue;
  uint32_t              pFLatency;

  HAL_StatusTypeDef     status = HAL_OK;
 80013f0:	2300      	movs	r3, #0
 80013f2:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f

  /* Enable TIM17 clock */
  __HAL_RCC_TIM17_CLK_ENABLE();
 80013f6:	4b2e      	ldr	r3, [pc, #184]	@ (80014b0 <HAL_InitTick+0xc8>)
 80013f8:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80013fa:	4a2d      	ldr	r2, [pc, #180]	@ (80014b0 <HAL_InitTick+0xc8>)
 80013fc:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 8001400:	6613      	str	r3, [r2, #96]	@ 0x60
 8001402:	4b2b      	ldr	r3, [pc, #172]	@ (80014b0 <HAL_InitTick+0xc8>)
 8001404:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001406:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 800140a:	60bb      	str	r3, [r7, #8]
 800140c:	68bb      	ldr	r3, [r7, #8]

  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
 800140e:	f107 020c 	add.w	r2, r7, #12
 8001412:	f107 0310 	add.w	r3, r7, #16
 8001416:	4611      	mov	r1, r2
 8001418:	4618      	mov	r0, r3
 800141a:	f001 fedb 	bl	80031d4 <HAL_RCC_GetClockConfig>

  /* Compute TIM17 clock */
      uwTimclock = HAL_RCC_GetPCLK2Freq();
 800141e:	f001 fec3 	bl	80031a8 <HAL_RCC_GetPCLK2Freq>
 8001422:	62b8      	str	r0, [r7, #40]	@ 0x28

  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
 8001424:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8001426:	4a23      	ldr	r2, [pc, #140]	@ (80014b4 <HAL_InitTick+0xcc>)
 8001428:	fba2 2303 	umull	r2, r3, r2, r3
 800142c:	0c9b      	lsrs	r3, r3, #18
 800142e:	3b01      	subs	r3, #1
 8001430:	627b      	str	r3, [r7, #36]	@ 0x24

  /* Initialize TIM17 */
  htim17.Instance = TIM17;
 8001432:	4b21      	ldr	r3, [pc, #132]	@ (80014b8 <HAL_InitTick+0xd0>)
 8001434:	4a21      	ldr	r2, [pc, #132]	@ (80014bc <HAL_InitTick+0xd4>)
 8001436:	601a      	str	r2, [r3, #0]
   * Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
   * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
   * ClockDivision = 0
   * Counter direction = Up
   */
  htim17.Init.Period = (1000000U / 1000U) - 1U;
 8001438:	4b1f      	ldr	r3, [pc, #124]	@ (80014b8 <HAL_InitTick+0xd0>)
 800143a:	f240 32e7 	movw	r2, #999	@ 0x3e7
 800143e:	60da      	str	r2, [r3, #12]
  htim17.Init.Prescaler = uwPrescalerValue;
 8001440:	4a1d      	ldr	r2, [pc, #116]	@ (80014b8 <HAL_InitTick+0xd0>)
 8001442:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8001444:	6053      	str	r3, [r2, #4]
  htim17.Init.ClockDivision = 0;
 8001446:	4b1c      	ldr	r3, [pc, #112]	@ (80014b8 <HAL_InitTick+0xd0>)
 8001448:	2200      	movs	r2, #0
 800144a:	611a      	str	r2, [r3, #16]
  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
 800144c:	4b1a      	ldr	r3, [pc, #104]	@ (80014b8 <HAL_InitTick+0xd0>)
 800144e:	2200      	movs	r2, #0
 8001450:	609a      	str	r2, [r3, #8]
  htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8001452:	4b19      	ldr	r3, [pc, #100]	@ (80014b8 <HAL_InitTick+0xd0>)
 8001454:	2200      	movs	r2, #0
 8001456:	619a      	str	r2, [r3, #24]

  status = HAL_TIM_Base_Init(&htim17);
 8001458:	4817      	ldr	r0, [pc, #92]	@ (80014b8 <HAL_InitTick+0xd0>)
 800145a:	f002 fcbc 	bl	8003dd6 <HAL_TIM_Base_Init>
 800145e:	4603      	mov	r3, r0
 8001460:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
  if (status == HAL_OK)
 8001464:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 8001468:	2b00      	cmp	r3, #0
 800146a:	d11b      	bne.n	80014a4 <HAL_InitTick+0xbc>
  {
    /* Start the TIM time Base generation in interrupt mode */
    status = HAL_TIM_Base_Start_IT(&htim17);
 800146c:	4812      	ldr	r0, [pc, #72]	@ (80014b8 <HAL_InitTick+0xd0>)
 800146e:	f002 fd13 	bl	8003e98 <HAL_TIM_Base_Start_IT>
 8001472:	4603      	mov	r3, r0
 8001474:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    if (status == HAL_OK)
 8001478:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 800147c:	2b00      	cmp	r3, #0
 800147e:	d111      	bne.n	80014a4 <HAL_InitTick+0xbc>
    {
    /* Enable the TIM17 global Interrupt */
        HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn);
 8001480:	201a      	movs	r0, #26
 8001482:	f000 f9e3 	bl	800184c <HAL_NVIC_EnableIRQ>
      /* Configure the SysTick IRQ priority */
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8001486:	687b      	ldr	r3, [r7, #4]
 8001488:	2b0f      	cmp	r3, #15
 800148a:	d808      	bhi.n	800149e <HAL_InitTick+0xb6>
      {
        /* Configure the TIM IRQ priority */
        HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority, 0U);
 800148c:	2200      	movs	r2, #0
 800148e:	6879      	ldr	r1, [r7, #4]
 8001490:	201a      	movs	r0, #26
 8001492:	f000 f9bf 	bl	8001814 <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 8001496:	4a0a      	ldr	r2, [pc, #40]	@ (80014c0 <HAL_InitTick+0xd8>)
 8001498:	687b      	ldr	r3, [r7, #4]
 800149a:	6013      	str	r3, [r2, #0]
 800149c:	e002      	b.n	80014a4 <HAL_InitTick+0xbc>
      }
      else
      {
        status = HAL_ERROR;
 800149e:	2301      	movs	r3, #1
 80014a0:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
      }
    }
  }

 /* Return function status */
  return status;
 80014a4:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
}
 80014a8:	4618      	mov	r0, r3
 80014aa:	3730      	adds	r7, #48	@ 0x30
 80014ac:	46bd      	mov	sp, r7
 80014ae:	bd80      	pop	{r7, pc}
 80014b0:	40021000 	.word	0x40021000
 80014b4:	431bde83 	.word	0x431bde83
 80014b8:	200007c8 	.word	0x200007c8
 80014bc:	40014800 	.word	0x40014800
 80014c0:	20000004 	.word	0x20000004

080014c4 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 80014c4:	b480      	push	{r7}
 80014c6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
 80014c8:	bf00      	nop
 80014ca:	e7fd      	b.n	80014c8 <NMI_Handler+0x4>

080014cc <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80014cc:	b480      	push	{r7}
 80014ce:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 80014d0:	bf00      	nop
 80014d2:	e7fd      	b.n	80014d0 <HardFault_Handler+0x4>

080014d4 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 80014d4:	b480      	push	{r7}
 80014d6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 80014d8:	bf00      	nop
 80014da:	e7fd      	b.n	80014d8 <MemManage_Handler+0x4>

080014dc <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 80014dc:	b480      	push	{r7}
 80014de:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 80014e0:	bf00      	nop
 80014e2:	e7fd      	b.n	80014e0 <BusFault_Handler+0x4>

080014e4 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 80014e4:	b480      	push	{r7}
 80014e6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 80014e8:	bf00      	nop
 80014ea:	e7fd      	b.n	80014e8 <UsageFault_Handler+0x4>

080014ec <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 80014ec:	b480      	push	{r7}
 80014ee:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 80014f0:	bf00      	nop
 80014f2:	46bd      	mov	sp, r7
 80014f4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80014f8:	4770      	bx	lr

080014fa <EXTI9_5_IRQHandler>:

/**
  * @brief This function handles EXTI line[9:5] interrupts.
  */
void EXTI9_5_IRQHandler(void)
{
 80014fa:	b580      	push	{r7, lr}
 80014fc:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN EXTI9_5_IRQn 0 */

  /* USER CODE END EXTI9_5_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(SPSGRF_915_GPIO3_EXTI5_Pin);
 80014fe:	2020      	movs	r0, #32
 8001500:	f000 fd00 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(SPBTLE_RF_IRQ_EXTI6_Pin);
 8001504:	2040      	movs	r0, #64	@ 0x40
 8001506:	f000 fcfd 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(VL53L0X_GPIO1_EXTI7_Pin);
 800150a:	2080      	movs	r0, #128	@ 0x80
 800150c:	f000 fcfa 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(LSM3MDL_DRDY_EXTI8_Pin);
 8001510:	f44f 7080 	mov.w	r0, #256	@ 0x100
 8001514:	f000 fcf6 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  /* USER CODE BEGIN EXTI9_5_IRQn 1 */

  /* USER CODE END EXTI9_5_IRQn 1 */
}
 8001518:	bf00      	nop
 800151a:	bd80      	pop	{r7, pc}

0800151c <TIM1_TRG_COM_TIM17_IRQHandler>:

/**
  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
  */
void TIM1_TRG_COM_TIM17_IRQHandler(void)
{
 800151c:	b580      	push	{r7, lr}
 800151e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */

  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
  HAL_TIM_IRQHandler(&htim17);
 8001520:	4802      	ldr	r0, [pc, #8]	@ (800152c <TIM1_TRG_COM_TIM17_IRQHandler+0x10>)
 8001522:	f002 fd29 	bl	8003f78 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */

  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
}
 8001526:	bf00      	nop
 8001528:	bd80      	pop	{r7, pc}
 800152a:	bf00      	nop
 800152c:	200007c8 	.word	0x200007c8

08001530 <USART1_IRQHandler>:

/**
  * @brief This function handles USART1 global interrupt.
  */
void USART1_IRQHandler(void)
{
 8001530:	b580      	push	{r7, lr}
 8001532:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 8001534:	4802      	ldr	r0, [pc, #8]	@ (8001540 <USART1_IRQHandler+0x10>)
 8001536:	f003 f80b 	bl	8004550 <HAL_UART_IRQHandler>
  /* USER CODE BEGIN USART1_IRQn 1 */

  /* USER CODE END USART1_IRQn 1 */
}
 800153a:	bf00      	nop
 800153c:	bd80      	pop	{r7, pc}
 800153e:	bf00      	nop
 8001540:	200001b0 	.word	0x200001b0

08001544 <EXTI15_10_IRQHandler>:

/**
  * @brief This function handles EXTI line[15:10] interrupts.
  */
void EXTI15_10_IRQHandler(void)
{
 8001544:	b580      	push	{r7, lr}
 8001546:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN EXTI15_10_IRQn 0 */

  /* USER CODE END EXTI15_10_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(LPS22HB_INT_DRDY_EXTI0_Pin);
 8001548:	f44f 6080 	mov.w	r0, #1024	@ 0x400
 800154c:	f000 fcda 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(LSM6DSL_INT1_EXTI11_Pin);
 8001550:	f44f 6000 	mov.w	r0, #2048	@ 0x800
 8001554:	f000 fcd6 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(BUTTON_EXTI13_Pin);
 8001558:	f44f 5000 	mov.w	r0, #8192	@ 0x2000
 800155c:	f000 fcd2 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(ARD_D2_Pin);
 8001560:	f44f 4080 	mov.w	r0, #16384	@ 0x4000
 8001564:	f000 fcce 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(HTS221_DRDY_EXTI15_Pin);
 8001568:	f44f 4000 	mov.w	r0, #32768	@ 0x8000
 800156c:	f000 fcca 	bl	8001f04 <HAL_GPIO_EXTI_IRQHandler>
  /* USER CODE BEGIN EXTI15_10_IRQn 1 */

  /* USER CODE END EXTI15_10_IRQn 1 */
}
 8001570:	bf00      	nop
 8001572:	bd80      	pop	{r7, pc}

08001574 <SystemInit>:
  * @brief  Setup the microcontroller system.
  * @retval None
  */

void SystemInit(void)
{
 8001574:	b480      	push	{r7}
 8001576:	af00      	add	r7, sp, #0
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif

  /* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
 8001578:	4b06      	ldr	r3, [pc, #24]	@ (8001594 <SystemInit+0x20>)
 800157a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800157e:	4a05      	ldr	r2, [pc, #20]	@ (8001594 <SystemInit+0x20>)
 8001580:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8001584:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
#endif
}
 8001588:	bf00      	nop
 800158a:	46bd      	mov	sp, r7
 800158c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001590:	4770      	bx	lr
 8001592:	bf00      	nop
 8001594:	e000ed00 	.word	0xe000ed00

08001598 <Reset_Handler>:

    .section	.text.Reset_Handler
	.weak	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:
  ldr   sp, =_estack    /* Set stack pointer */
 8001598:	f8df d034 	ldr.w	sp, [pc, #52]	@ 80015d0 <LoopForever+0x2>

/* Call the clock system initialization function.*/
    bl  SystemInit
 800159c:	f7ff ffea 	bl	8001574 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 80015a0:	480c      	ldr	r0, [pc, #48]	@ (80015d4 <LoopForever+0x6>)
  ldr r1, =_edata
 80015a2:	490d      	ldr	r1, [pc, #52]	@ (80015d8 <LoopForever+0xa>)
  ldr r2, =_sidata
 80015a4:	4a0d      	ldr	r2, [pc, #52]	@ (80015dc <LoopForever+0xe>)
  movs r3, #0
 80015a6:	2300      	movs	r3, #0
  b LoopCopyDataInit
 80015a8:	e002      	b.n	80015b0 <LoopCopyDataInit>

080015aa <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 80015aa:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 80015ac:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 80015ae:	3304      	adds	r3, #4

080015b0 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 80015b0:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 80015b2:	428c      	cmp	r4, r1
  bcc CopyDataInit
 80015b4:	d3f9      	bcc.n	80015aa <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 80015b6:	4a0a      	ldr	r2, [pc, #40]	@ (80015e0 <LoopForever+0x12>)
  ldr r4, =_ebss
 80015b8:	4c0a      	ldr	r4, [pc, #40]	@ (80015e4 <LoopForever+0x16>)
  movs r3, #0
 80015ba:	2300      	movs	r3, #0
  b LoopFillZerobss
 80015bc:	e001      	b.n	80015c2 <LoopFillZerobss>

080015be <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 80015be:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 80015c0:	3204      	adds	r2, #4

080015c2 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 80015c2:	42a2      	cmp	r2, r4
  bcc FillZerobss
 80015c4:	d3fb      	bcc.n	80015be <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 80015c6:	f007 ff35 	bl	8009434 <__libc_init_array>
/* Call the application's entry point.*/
	bl	main
 80015ca:	f7fe ff97 	bl	80004fc <main>

080015ce <LoopForever>:

LoopForever:
    b LoopForever
 80015ce:	e7fe      	b.n	80015ce <LoopForever>
  ldr   sp, =_estack    /* Set stack pointer */
 80015d0:	20018000 	.word	0x20018000
  ldr r0, =_sdata
 80015d4:	20000000 	.word	0x20000000
  ldr r1, =_edata
 80015d8:	20000060 	.word	0x20000060
  ldr r2, =_sidata
 80015dc:	08009620 	.word	0x08009620
  ldr r2, =_sbss
 80015e0:	20000060 	.word	0x20000060
  ldr r4, =_ebss
 80015e4:	20008c94 	.word	0x20008c94

080015e8 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section	.text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
	b	Infinite_Loop
 80015e8:	e7fe      	b.n	80015e8 <ADC1_2_IRQHandler>

080015ea <HAL_Init>:
  *         each 1ms in the SysTick_Handler() interrupt handler.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 80015ea:	b580      	push	{r7, lr}
 80015ec:	b082      	sub	sp, #8
 80015ee:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef  status = HAL_OK;
 80015f0:	2300      	movs	r3, #0
 80015f2:	71fb      	strb	r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 80015f4:	2003      	movs	r0, #3
 80015f6:	f000 f902 	bl	80017fe <HAL_NVIC_SetPriorityGrouping>

  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 80015fa:	200f      	movs	r0, #15
 80015fc:	f7ff fef4 	bl	80013e8 <HAL_InitTick>
 8001600:	4603      	mov	r3, r0
 8001602:	2b00      	cmp	r3, #0
 8001604:	d002      	beq.n	800160c <HAL_Init+0x22>
  {
    status = HAL_ERROR;
 8001606:	2301      	movs	r3, #1
 8001608:	71fb      	strb	r3, [r7, #7]
 800160a:	e001      	b.n	8001610 <HAL_Init+0x26>
  }
  else
  {
    /* Init the low level hardware */
    HAL_MspInit();
 800160c:	f7ff fc32 	bl	8000e74 <HAL_MspInit>
  }

  /* Return function status */
  return status;
 8001610:	79fb      	ldrb	r3, [r7, #7]
}
 8001612:	4618      	mov	r0, r3
 8001614:	3708      	adds	r7, #8
 8001616:	46bd      	mov	sp, r7
 8001618:	bd80      	pop	{r7, pc}
	...

0800161c <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 800161c:	b480      	push	{r7}
 800161e:	af00      	add	r7, sp, #0
  uwTick += (uint32_t)uwTickFreq;
 8001620:	4b06      	ldr	r3, [pc, #24]	@ (800163c <HAL_IncTick+0x20>)
 8001622:	781b      	ldrb	r3, [r3, #0]
 8001624:	461a      	mov	r2, r3
 8001626:	4b06      	ldr	r3, [pc, #24]	@ (8001640 <HAL_IncTick+0x24>)
 8001628:	681b      	ldr	r3, [r3, #0]
 800162a:	4413      	add	r3, r2
 800162c:	4a04      	ldr	r2, [pc, #16]	@ (8001640 <HAL_IncTick+0x24>)
 800162e:	6013      	str	r3, [r2, #0]
}
 8001630:	bf00      	nop
 8001632:	46bd      	mov	sp, r7
 8001634:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001638:	4770      	bx	lr
 800163a:	bf00      	nop
 800163c:	20000008 	.word	0x20000008
 8001640:	20000814 	.word	0x20000814

08001644 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8001644:	b480      	push	{r7}
 8001646:	af00      	add	r7, sp, #0
  return uwTick;
 8001648:	4b03      	ldr	r3, [pc, #12]	@ (8001658 <HAL_GetTick+0x14>)
 800164a:	681b      	ldr	r3, [r3, #0]
}
 800164c:	4618      	mov	r0, r3
 800164e:	46bd      	mov	sp, r7
 8001650:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001654:	4770      	bx	lr
 8001656:	bf00      	nop
 8001658:	20000814 	.word	0x20000814

0800165c <HAL_Delay>:
  *       implementations in user file.
  * @param Delay  specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 800165c:	b580      	push	{r7, lr}
 800165e:	b084      	sub	sp, #16
 8001660:	af00      	add	r7, sp, #0
 8001662:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 8001664:	f7ff ffee 	bl	8001644 <HAL_GetTick>
 8001668:	60b8      	str	r0, [r7, #8]
  uint32_t wait = Delay;
 800166a:	687b      	ldr	r3, [r7, #4]
 800166c:	60fb      	str	r3, [r7, #12]

  /* Add a period to guaranty minimum wait */
  if (wait < HAL_MAX_DELAY)
 800166e:	68fb      	ldr	r3, [r7, #12]
 8001670:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8001674:	d005      	beq.n	8001682 <HAL_Delay+0x26>
  {
    wait += (uint32_t)uwTickFreq;
 8001676:	4b0a      	ldr	r3, [pc, #40]	@ (80016a0 <HAL_Delay+0x44>)
 8001678:	781b      	ldrb	r3, [r3, #0]
 800167a:	461a      	mov	r2, r3
 800167c:	68fb      	ldr	r3, [r7, #12]
 800167e:	4413      	add	r3, r2
 8001680:	60fb      	str	r3, [r7, #12]
  }

  while ((HAL_GetTick() - tickstart) < wait)
 8001682:	bf00      	nop
 8001684:	f7ff ffde 	bl	8001644 <HAL_GetTick>
 8001688:	4602      	mov	r2, r0
 800168a:	68bb      	ldr	r3, [r7, #8]
 800168c:	1ad3      	subs	r3, r2, r3
 800168e:	68fa      	ldr	r2, [r7, #12]
 8001690:	429a      	cmp	r2, r3
 8001692:	d8f7      	bhi.n	8001684 <HAL_Delay+0x28>
  {
  }
}
 8001694:	bf00      	nop
 8001696:	bf00      	nop
 8001698:	3710      	adds	r7, #16
 800169a:	46bd      	mov	sp, r7
 800169c:	bd80      	pop	{r7, pc}
 800169e:	bf00      	nop
 80016a0:	20000008 	.word	0x20000008

080016a4 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80016a4:	b480      	push	{r7}
 80016a6:	b085      	sub	sp, #20
 80016a8:	af00      	add	r7, sp, #0
 80016aa:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 80016ac:	687b      	ldr	r3, [r7, #4]
 80016ae:	f003 0307 	and.w	r3, r3, #7
 80016b2:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80016b4:	4b0c      	ldr	r3, [pc, #48]	@ (80016e8 <__NVIC_SetPriorityGrouping+0x44>)
 80016b6:	68db      	ldr	r3, [r3, #12]
 80016b8:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 80016ba:	68ba      	ldr	r2, [r7, #8]
 80016bc:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
 80016c0:	4013      	ands	r3, r2
 80016c2:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 80016c4:	68fb      	ldr	r3, [r7, #12]
 80016c6:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 80016c8:	68bb      	ldr	r3, [r7, #8]
 80016ca:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 80016cc:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
 80016d0:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 80016d4:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 80016d6:	4a04      	ldr	r2, [pc, #16]	@ (80016e8 <__NVIC_SetPriorityGrouping+0x44>)
 80016d8:	68bb      	ldr	r3, [r7, #8]
 80016da:	60d3      	str	r3, [r2, #12]
}
 80016dc:	bf00      	nop
 80016de:	3714      	adds	r7, #20
 80016e0:	46bd      	mov	sp, r7
 80016e2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80016e6:	4770      	bx	lr
 80016e8:	e000ed00 	.word	0xe000ed00

080016ec <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 80016ec:	b480      	push	{r7}
 80016ee:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 80016f0:	4b04      	ldr	r3, [pc, #16]	@ (8001704 <__NVIC_GetPriorityGrouping+0x18>)
 80016f2:	68db      	ldr	r3, [r3, #12]
 80016f4:	0a1b      	lsrs	r3, r3, #8
 80016f6:	f003 0307 	and.w	r3, r3, #7
}
 80016fa:	4618      	mov	r0, r3
 80016fc:	46bd      	mov	sp, r7
 80016fe:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001702:	4770      	bx	lr
 8001704:	e000ed00 	.word	0xe000ed00

08001708 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8001708:	b480      	push	{r7}
 800170a:	b083      	sub	sp, #12
 800170c:	af00      	add	r7, sp, #0
 800170e:	4603      	mov	r3, r0
 8001710:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8001712:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001716:	2b00      	cmp	r3, #0
 8001718:	db0b      	blt.n	8001732 <__NVIC_EnableIRQ+0x2a>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 800171a:	79fb      	ldrb	r3, [r7, #7]
 800171c:	f003 021f 	and.w	r2, r3, #31
 8001720:	4907      	ldr	r1, [pc, #28]	@ (8001740 <__NVIC_EnableIRQ+0x38>)
 8001722:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001726:	095b      	lsrs	r3, r3, #5
 8001728:	2001      	movs	r0, #1
 800172a:	fa00 f202 	lsl.w	r2, r0, r2
 800172e:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    __COMPILER_BARRIER();
  }
}
 8001732:	bf00      	nop
 8001734:	370c      	adds	r7, #12
 8001736:	46bd      	mov	sp, r7
 8001738:	f85d 7b04 	ldr.w	r7, [sp], #4
 800173c:	4770      	bx	lr
 800173e:	bf00      	nop
 8001740:	e000e100 	.word	0xe000e100

08001744 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8001744:	b480      	push	{r7}
 8001746:	b083      	sub	sp, #12
 8001748:	af00      	add	r7, sp, #0
 800174a:	4603      	mov	r3, r0
 800174c:	6039      	str	r1, [r7, #0]
 800174e:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8001750:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001754:	2b00      	cmp	r3, #0
 8001756:	db0a      	blt.n	800176e <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8001758:	683b      	ldr	r3, [r7, #0]
 800175a:	b2da      	uxtb	r2, r3
 800175c:	490c      	ldr	r1, [pc, #48]	@ (8001790 <__NVIC_SetPriority+0x4c>)
 800175e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001762:	0112      	lsls	r2, r2, #4
 8001764:	b2d2      	uxtb	r2, r2
 8001766:	440b      	add	r3, r1
 8001768:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 800176c:	e00a      	b.n	8001784 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800176e:	683b      	ldr	r3, [r7, #0]
 8001770:	b2da      	uxtb	r2, r3
 8001772:	4908      	ldr	r1, [pc, #32]	@ (8001794 <__NVIC_SetPriority+0x50>)
 8001774:	79fb      	ldrb	r3, [r7, #7]
 8001776:	f003 030f 	and.w	r3, r3, #15
 800177a:	3b04      	subs	r3, #4
 800177c:	0112      	lsls	r2, r2, #4
 800177e:	b2d2      	uxtb	r2, r2
 8001780:	440b      	add	r3, r1
 8001782:	761a      	strb	r2, [r3, #24]
}
 8001784:	bf00      	nop
 8001786:	370c      	adds	r7, #12
 8001788:	46bd      	mov	sp, r7
 800178a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800178e:	4770      	bx	lr
 8001790:	e000e100 	.word	0xe000e100
 8001794:	e000ed00 	.word	0xe000ed00

08001798 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8001798:	b480      	push	{r7}
 800179a:	b089      	sub	sp, #36	@ 0x24
 800179c:	af00      	add	r7, sp, #0
 800179e:	60f8      	str	r0, [r7, #12]
 80017a0:	60b9      	str	r1, [r7, #8]
 80017a2:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 80017a4:	68fb      	ldr	r3, [r7, #12]
 80017a6:	f003 0307 	and.w	r3, r3, #7
 80017aa:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 80017ac:	69fb      	ldr	r3, [r7, #28]
 80017ae:	f1c3 0307 	rsb	r3, r3, #7
 80017b2:	2b04      	cmp	r3, #4
 80017b4:	bf28      	it	cs
 80017b6:	2304      	movcs	r3, #4
 80017b8:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 80017ba:	69fb      	ldr	r3, [r7, #28]
 80017bc:	3304      	adds	r3, #4
 80017be:	2b06      	cmp	r3, #6
 80017c0:	d902      	bls.n	80017c8 <NVIC_EncodePriority+0x30>
 80017c2:	69fb      	ldr	r3, [r7, #28]
 80017c4:	3b03      	subs	r3, #3
 80017c6:	e000      	b.n	80017ca <NVIC_EncodePriority+0x32>
 80017c8:	2300      	movs	r3, #0
 80017ca:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80017cc:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 80017d0:	69bb      	ldr	r3, [r7, #24]
 80017d2:	fa02 f303 	lsl.w	r3, r2, r3
 80017d6:	43da      	mvns	r2, r3
 80017d8:	68bb      	ldr	r3, [r7, #8]
 80017da:	401a      	ands	r2, r3
 80017dc:	697b      	ldr	r3, [r7, #20]
 80017de:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 80017e0:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80017e4:	697b      	ldr	r3, [r7, #20]
 80017e6:	fa01 f303 	lsl.w	r3, r1, r3
 80017ea:	43d9      	mvns	r1, r3
 80017ec:	687b      	ldr	r3, [r7, #4]
 80017ee:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80017f0:	4313      	orrs	r3, r2
         );
}
 80017f2:	4618      	mov	r0, r3
 80017f4:	3724      	adds	r7, #36	@ 0x24
 80017f6:	46bd      	mov	sp, r7
 80017f8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80017fc:	4770      	bx	lr

080017fe <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
  *         The pending IRQ priority will be managed only by the subpriority.
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80017fe:	b580      	push	{r7, lr}
 8001800:	b082      	sub	sp, #8
 8001802:	af00      	add	r7, sp, #0
 8001804:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 8001806:	6878      	ldr	r0, [r7, #4]
 8001808:	f7ff ff4c 	bl	80016a4 <__NVIC_SetPriorityGrouping>
}
 800180c:	bf00      	nop
 800180e:	3708      	adds	r7, #8
 8001810:	46bd      	mov	sp, r7
 8001812:	bd80      	pop	{r7, pc}

08001814 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8001814:	b580      	push	{r7, lr}
 8001816:	b086      	sub	sp, #24
 8001818:	af00      	add	r7, sp, #0
 800181a:	4603      	mov	r3, r0
 800181c:	60b9      	str	r1, [r7, #8]
 800181e:	607a      	str	r2, [r7, #4]
 8001820:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00;
 8001822:	2300      	movs	r3, #0
 8001824:	617b      	str	r3, [r7, #20]

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();
 8001826:	f7ff ff61 	bl	80016ec <__NVIC_GetPriorityGrouping>
 800182a:	6178      	str	r0, [r7, #20]

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 800182c:	687a      	ldr	r2, [r7, #4]
 800182e:	68b9      	ldr	r1, [r7, #8]
 8001830:	6978      	ldr	r0, [r7, #20]
 8001832:	f7ff ffb1 	bl	8001798 <NVIC_EncodePriority>
 8001836:	4602      	mov	r2, r0
 8001838:	f997 300f 	ldrsb.w	r3, [r7, #15]
 800183c:	4611      	mov	r1, r2
 800183e:	4618      	mov	r0, r3
 8001840:	f7ff ff80 	bl	8001744 <__NVIC_SetPriority>
}
 8001844:	bf00      	nop
 8001846:	3718      	adds	r7, #24
 8001848:	46bd      	mov	sp, r7
 800184a:	bd80      	pop	{r7, pc}

0800184c <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 800184c:	b580      	push	{r7, lr}
 800184e:	b082      	sub	sp, #8
 8001850:	af00      	add	r7, sp, #0
 8001852:	4603      	mov	r3, r0
 8001854:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8001856:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800185a:	4618      	mov	r0, r3
 800185c:	f7ff ff54 	bl	8001708 <__NVIC_EnableIRQ>
}
 8001860:	bf00      	nop
 8001862:	3708      	adds	r7, #8
 8001864:	46bd      	mov	sp, r7
 8001866:	bd80      	pop	{r7, pc}

08001868 <HAL_DFSDM_ChannelInit>:
  *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
  * @param  hdfsdm_channel DFSDM channel handle.
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
 8001868:	b580      	push	{r7, lr}
 800186a:	b082      	sub	sp, #8
 800186c:	af00      	add	r7, sp, #0
 800186e:	6078      	str	r0, [r7, #4]
  /* Check DFSDM Channel handle */
  if (hdfsdm_channel == NULL)
 8001870:	687b      	ldr	r3, [r7, #4]
 8001872:	2b00      	cmp	r3, #0
 8001874:	d101      	bne.n	800187a <HAL_DFSDM_ChannelInit+0x12>
  {
    return HAL_ERROR;
 8001876:	2301      	movs	r3, #1
 8001878:	e0ac      	b.n	80019d4 <HAL_DFSDM_ChannelInit+0x16c>
  assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
  assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
  assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));

  /* Check that channel has not been already initialized */
  if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
 800187a:	687b      	ldr	r3, [r7, #4]
 800187c:	681b      	ldr	r3, [r3, #0]
 800187e:	4618      	mov	r0, r3
 8001880:	f000 f8b2 	bl	80019e8 <DFSDM_GetChannelFromInstance>
 8001884:	4603      	mov	r3, r0
 8001886:	4a55      	ldr	r2, [pc, #340]	@ (80019dc <HAL_DFSDM_ChannelInit+0x174>)
 8001888:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 800188c:	2b00      	cmp	r3, #0
 800188e:	d001      	beq.n	8001894 <HAL_DFSDM_ChannelInit+0x2c>
  {
    return HAL_ERROR;
 8001890:	2301      	movs	r3, #1
 8001892:	e09f      	b.n	80019d4 <HAL_DFSDM_ChannelInit+0x16c>
    hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
  }
  hdfsdm_channel->MspInitCallback(hdfsdm_channel);
#else
  /* Call MSP init function */
  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
 8001894:	6878      	ldr	r0, [r7, #4]
 8001896:	f7ff fb15 	bl	8000ec4 <HAL_DFSDM_ChannelMspInit>
#endif

  /* Update the channel counter */
  v_dfsdm1ChannelCounter++;
 800189a:	4b51      	ldr	r3, [pc, #324]	@ (80019e0 <HAL_DFSDM_ChannelInit+0x178>)
 800189c:	681b      	ldr	r3, [r3, #0]
 800189e:	3301      	adds	r3, #1
 80018a0:	4a4f      	ldr	r2, [pc, #316]	@ (80019e0 <HAL_DFSDM_ChannelInit+0x178>)
 80018a2:	6013      	str	r3, [r2, #0]

  /* Configure output serial clock and enable global DFSDM interface only for first channel */
  if (v_dfsdm1ChannelCounter == 1U)
 80018a4:	4b4e      	ldr	r3, [pc, #312]	@ (80019e0 <HAL_DFSDM_ChannelInit+0x178>)
 80018a6:	681b      	ldr	r3, [r3, #0]
 80018a8:	2b01      	cmp	r3, #1
 80018aa:	d125      	bne.n	80018f8 <HAL_DFSDM_ChannelInit+0x90>
  {
    assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
    /* Set the output serial clock source */
    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
 80018ac:	4b4d      	ldr	r3, [pc, #308]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018ae:	681b      	ldr	r3, [r3, #0]
 80018b0:	4a4c      	ldr	r2, [pc, #304]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018b2:	f023 4380 	bic.w	r3, r3, #1073741824	@ 0x40000000
 80018b6:	6013      	str	r3, [r2, #0]
    DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
 80018b8:	4b4a      	ldr	r3, [pc, #296]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018ba:	681a      	ldr	r2, [r3, #0]
 80018bc:	687b      	ldr	r3, [r7, #4]
 80018be:	689b      	ldr	r3, [r3, #8]
 80018c0:	4948      	ldr	r1, [pc, #288]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018c2:	4313      	orrs	r3, r2
 80018c4:	600b      	str	r3, [r1, #0]

    /* Reset clock divider */
    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
 80018c6:	4b47      	ldr	r3, [pc, #284]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018c8:	681b      	ldr	r3, [r3, #0]
 80018ca:	4a46      	ldr	r2, [pc, #280]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018cc:	f423 037f 	bic.w	r3, r3, #16711680	@ 0xff0000
 80018d0:	6013      	str	r3, [r2, #0]
    if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
 80018d2:	687b      	ldr	r3, [r7, #4]
 80018d4:	791b      	ldrb	r3, [r3, #4]
 80018d6:	2b01      	cmp	r3, #1
 80018d8:	d108      	bne.n	80018ec <HAL_DFSDM_ChannelInit+0x84>
    {
      assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
      /* Set the output clock divider */
      DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
 80018da:	4b42      	ldr	r3, [pc, #264]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018dc:	681a      	ldr	r2, [r3, #0]
 80018de:	687b      	ldr	r3, [r7, #4]
 80018e0:	68db      	ldr	r3, [r3, #12]
 80018e2:	3b01      	subs	r3, #1
 80018e4:	041b      	lsls	r3, r3, #16
 80018e6:	493f      	ldr	r1, [pc, #252]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018e8:	4313      	orrs	r3, r2
 80018ea:	600b      	str	r3, [r1, #0]
                                             DFSDM_CHCFGR1_CKOUTDIV_Pos);
    }

    /* enable the DFSDM global interface */
    DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
 80018ec:	4b3d      	ldr	r3, [pc, #244]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018ee:	681b      	ldr	r3, [r3, #0]
 80018f0:	4a3c      	ldr	r2, [pc, #240]	@ (80019e4 <HAL_DFSDM_ChannelInit+0x17c>)
 80018f2:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
 80018f6:	6013      	str	r3, [r2, #0]
  }

  /* Set channel input parameters */
  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
 80018f8:	687b      	ldr	r3, [r7, #4]
 80018fa:	681b      	ldr	r3, [r3, #0]
 80018fc:	681a      	ldr	r2, [r3, #0]
 80018fe:	687b      	ldr	r3, [r7, #4]
 8001900:	681b      	ldr	r3, [r3, #0]
 8001902:	f422 4271 	bic.w	r2, r2, #61696	@ 0xf100
 8001906:	601a      	str	r2, [r3, #0]
                                         DFSDM_CHCFGR1_CHINSEL);
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
 8001908:	687b      	ldr	r3, [r7, #4]
 800190a:	681b      	ldr	r3, [r3, #0]
 800190c:	6819      	ldr	r1, [r3, #0]
 800190e:	687b      	ldr	r3, [r7, #4]
 8001910:	691a      	ldr	r2, [r3, #16]
                                        hdfsdm_channel->Init.Input.DataPacking |
 8001912:	687b      	ldr	r3, [r7, #4]
 8001914:	695b      	ldr	r3, [r3, #20]
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
 8001916:	431a      	orrs	r2, r3
                                        hdfsdm_channel->Init.Input.Pins);
 8001918:	687b      	ldr	r3, [r7, #4]
 800191a:	699b      	ldr	r3, [r3, #24]
                                        hdfsdm_channel->Init.Input.DataPacking |
 800191c:	431a      	orrs	r2, r3
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
 800191e:	687b      	ldr	r3, [r7, #4]
 8001920:	681b      	ldr	r3, [r3, #0]
 8001922:	430a      	orrs	r2, r1
 8001924:	601a      	str	r2, [r3, #0]

  /* Set serial interface parameters */
  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
 8001926:	687b      	ldr	r3, [r7, #4]
 8001928:	681b      	ldr	r3, [r3, #0]
 800192a:	681a      	ldr	r2, [r3, #0]
 800192c:	687b      	ldr	r3, [r7, #4]
 800192e:	681b      	ldr	r3, [r3, #0]
 8001930:	f022 020f 	bic.w	r2, r2, #15
 8001934:	601a      	str	r2, [r3, #0]
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
 8001936:	687b      	ldr	r3, [r7, #4]
 8001938:	681b      	ldr	r3, [r3, #0]
 800193a:	6819      	ldr	r1, [r3, #0]
 800193c:	687b      	ldr	r3, [r7, #4]
 800193e:	69da      	ldr	r2, [r3, #28]
                                        hdfsdm_channel->Init.SerialInterface.SpiClock);
 8001940:	687b      	ldr	r3, [r7, #4]
 8001942:	6a1b      	ldr	r3, [r3, #32]
  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
 8001944:	431a      	orrs	r2, r3
 8001946:	687b      	ldr	r3, [r7, #4]
 8001948:	681b      	ldr	r3, [r3, #0]
 800194a:	430a      	orrs	r2, r1
 800194c:	601a      	str	r2, [r3, #0]

  /* Set analog watchdog parameters */
  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
 800194e:	687b      	ldr	r3, [r7, #4]
 8001950:	681b      	ldr	r3, [r3, #0]
 8001952:	689a      	ldr	r2, [r3, #8]
 8001954:	687b      	ldr	r3, [r7, #4]
 8001956:	681b      	ldr	r3, [r3, #0]
 8001958:	f422 025f 	bic.w	r2, r2, #14614528	@ 0xdf0000
 800195c:	609a      	str	r2, [r3, #8]
  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
 800195e:	687b      	ldr	r3, [r7, #4]
 8001960:	681b      	ldr	r3, [r3, #0]
 8001962:	6899      	ldr	r1, [r3, #8]
 8001964:	687b      	ldr	r3, [r7, #4]
 8001966:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
                                         ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
 8001968:	687b      	ldr	r3, [r7, #4]
 800196a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800196c:	3b01      	subs	r3, #1
 800196e:	041b      	lsls	r3, r3, #16
  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
 8001970:	431a      	orrs	r2, r3
 8001972:	687b      	ldr	r3, [r7, #4]
 8001974:	681b      	ldr	r3, [r3, #0]
 8001976:	430a      	orrs	r2, r1
 8001978:	609a      	str	r2, [r3, #8]

  /* Set channel offset and right bit shift */
  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
 800197a:	687b      	ldr	r3, [r7, #4]
 800197c:	681b      	ldr	r3, [r3, #0]
 800197e:	685a      	ldr	r2, [r3, #4]
 8001980:	687b      	ldr	r3, [r7, #4]
 8001982:	681b      	ldr	r3, [r3, #0]
 8001984:	f002 0207 	and.w	r2, r2, #7
 8001988:	605a      	str	r2, [r3, #4]
  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
 800198a:	687b      	ldr	r3, [r7, #4]
 800198c:	681b      	ldr	r3, [r3, #0]
 800198e:	6859      	ldr	r1, [r3, #4]
 8001990:	687b      	ldr	r3, [r7, #4]
 8001992:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001994:	021a      	lsls	r2, r3, #8
                                        (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
 8001996:	687b      	ldr	r3, [r7, #4]
 8001998:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800199a:	00db      	lsls	r3, r3, #3
  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
 800199c:	431a      	orrs	r2, r3
 800199e:	687b      	ldr	r3, [r7, #4]
 80019a0:	681b      	ldr	r3, [r3, #0]
 80019a2:	430a      	orrs	r2, r1
 80019a4:	605a      	str	r2, [r3, #4]

  /* Enable DFSDM channel */
  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
 80019a6:	687b      	ldr	r3, [r7, #4]
 80019a8:	681b      	ldr	r3, [r3, #0]
 80019aa:	681a      	ldr	r2, [r3, #0]
 80019ac:	687b      	ldr	r3, [r7, #4]
 80019ae:	681b      	ldr	r3, [r3, #0]
 80019b0:	f042 0280 	orr.w	r2, r2, #128	@ 0x80
 80019b4:	601a      	str	r2, [r3, #0]

  /* Set DFSDM Channel to ready state */
  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
 80019b6:	687b      	ldr	r3, [r7, #4]
 80019b8:	2201      	movs	r2, #1
 80019ba:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

  /* Store channel handle in DFSDM channel handle table */
  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
 80019be:	687b      	ldr	r3, [r7, #4]
 80019c0:	681b      	ldr	r3, [r3, #0]
 80019c2:	4618      	mov	r0, r3
 80019c4:	f000 f810 	bl	80019e8 <DFSDM_GetChannelFromInstance>
 80019c8:	4602      	mov	r2, r0
 80019ca:	4904      	ldr	r1, [pc, #16]	@ (80019dc <HAL_DFSDM_ChannelInit+0x174>)
 80019cc:	687b      	ldr	r3, [r7, #4]
 80019ce:	f841 3022 	str.w	r3, [r1, r2, lsl #2]

  return HAL_OK;
 80019d2:	2300      	movs	r3, #0
}
 80019d4:	4618      	mov	r0, r3
 80019d6:	3708      	adds	r7, #8
 80019d8:	46bd      	mov	sp, r7
 80019da:	bd80      	pop	{r7, pc}
 80019dc:	2000081c 	.word	0x2000081c
 80019e0:	20000818 	.word	0x20000818
 80019e4:	40016000 	.word	0x40016000

080019e8 <DFSDM_GetChannelFromInstance>:
  * @brief  This function allows to get the channel number from channel instance.
  * @param  Instance DFSDM channel instance.
  * @retval Channel number.
  */
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
{
 80019e8:	b480      	push	{r7}
 80019ea:	b085      	sub	sp, #20
 80019ec:	af00      	add	r7, sp, #0
 80019ee:	6078      	str	r0, [r7, #4]
  uint32_t channel;

  /* Get channel from instance */
  if (Instance == DFSDM1_Channel0)
 80019f0:	687b      	ldr	r3, [r7, #4]
 80019f2:	4a1c      	ldr	r2, [pc, #112]	@ (8001a64 <DFSDM_GetChannelFromInstance+0x7c>)
 80019f4:	4293      	cmp	r3, r2
 80019f6:	d102      	bne.n	80019fe <DFSDM_GetChannelFromInstance+0x16>
  {
    channel = 0;
 80019f8:	2300      	movs	r3, #0
 80019fa:	60fb      	str	r3, [r7, #12]
 80019fc:	e02b      	b.n	8001a56 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel1)
 80019fe:	687b      	ldr	r3, [r7, #4]
 8001a00:	4a19      	ldr	r2, [pc, #100]	@ (8001a68 <DFSDM_GetChannelFromInstance+0x80>)
 8001a02:	4293      	cmp	r3, r2
 8001a04:	d102      	bne.n	8001a0c <DFSDM_GetChannelFromInstance+0x24>
  {
    channel = 1;
 8001a06:	2301      	movs	r3, #1
 8001a08:	60fb      	str	r3, [r7, #12]
 8001a0a:	e024      	b.n	8001a56 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel2)
 8001a0c:	687b      	ldr	r3, [r7, #4]
 8001a0e:	4a17      	ldr	r2, [pc, #92]	@ (8001a6c <DFSDM_GetChannelFromInstance+0x84>)
 8001a10:	4293      	cmp	r3, r2
 8001a12:	d102      	bne.n	8001a1a <DFSDM_GetChannelFromInstance+0x32>
  {
    channel = 2;
 8001a14:	2302      	movs	r3, #2
 8001a16:	60fb      	str	r3, [r7, #12]
 8001a18:	e01d      	b.n	8001a56 <DFSDM_GetChannelFromInstance+0x6e>
  }
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
    defined(STM32L496xx) || defined(STM32L4A6xx) || \
    defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
  else if (Instance == DFSDM1_Channel4)
 8001a1a:	687b      	ldr	r3, [r7, #4]
 8001a1c:	4a14      	ldr	r2, [pc, #80]	@ (8001a70 <DFSDM_GetChannelFromInstance+0x88>)
 8001a1e:	4293      	cmp	r3, r2
 8001a20:	d102      	bne.n	8001a28 <DFSDM_GetChannelFromInstance+0x40>
  {
    channel = 4;
 8001a22:	2304      	movs	r3, #4
 8001a24:	60fb      	str	r3, [r7, #12]
 8001a26:	e016      	b.n	8001a56 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel5)
 8001a28:	687b      	ldr	r3, [r7, #4]
 8001a2a:	4a12      	ldr	r2, [pc, #72]	@ (8001a74 <DFSDM_GetChannelFromInstance+0x8c>)
 8001a2c:	4293      	cmp	r3, r2
 8001a2e:	d102      	bne.n	8001a36 <DFSDM_GetChannelFromInstance+0x4e>
  {
    channel = 5;
 8001a30:	2305      	movs	r3, #5
 8001a32:	60fb      	str	r3, [r7, #12]
 8001a34:	e00f      	b.n	8001a56 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel6)
 8001a36:	687b      	ldr	r3, [r7, #4]
 8001a38:	4a0f      	ldr	r2, [pc, #60]	@ (8001a78 <DFSDM_GetChannelFromInstance+0x90>)
 8001a3a:	4293      	cmp	r3, r2
 8001a3c:	d102      	bne.n	8001a44 <DFSDM_GetChannelFromInstance+0x5c>
  {
    channel = 6;
 8001a3e:	2306      	movs	r3, #6
 8001a40:	60fb      	str	r3, [r7, #12]
 8001a42:	e008      	b.n	8001a56 <DFSDM_GetChannelFromInstance+0x6e>
  }
  else if (Instance == DFSDM1_Channel7)
 8001a44:	687b      	ldr	r3, [r7, #4]
 8001a46:	4a0d      	ldr	r2, [pc, #52]	@ (8001a7c <DFSDM_GetChannelFromInstance+0x94>)
 8001a48:	4293      	cmp	r3, r2
 8001a4a:	d102      	bne.n	8001a52 <DFSDM_GetChannelFromInstance+0x6a>
  {
    channel = 7;
 8001a4c:	2307      	movs	r3, #7
 8001a4e:	60fb      	str	r3, [r7, #12]
 8001a50:	e001      	b.n	8001a56 <DFSDM_GetChannelFromInstance+0x6e>
  }
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
  else /* DFSDM1_Channel3 */
  {
    channel = 3;
 8001a52:	2303      	movs	r3, #3
 8001a54:	60fb      	str	r3, [r7, #12]
  }

  return channel;
 8001a56:	68fb      	ldr	r3, [r7, #12]
}
 8001a58:	4618      	mov	r0, r3
 8001a5a:	3714      	adds	r7, #20
 8001a5c:	46bd      	mov	sp, r7
 8001a5e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001a62:	4770      	bx	lr
 8001a64:	40016000 	.word	0x40016000
 8001a68:	40016020 	.word	0x40016020
 8001a6c:	40016040 	.word	0x40016040
 8001a70:	40016080 	.word	0x40016080
 8001a74:	400160a0 	.word	0x400160a0
 8001a78:	400160c0 	.word	0x400160c0
 8001a7c:	400160e0 	.word	0x400160e0

08001a80 <HAL_DMA_Abort>:
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
    * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
 8001a80:	b480      	push	{r7}
 8001a82:	b085      	sub	sp, #20
 8001a84:	af00      	add	r7, sp, #0
 8001a86:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 8001a88:	2300      	movs	r3, #0
 8001a8a:	73fb      	strb	r3, [r7, #15]

  /* Check the DMA peripheral state */
  if (hdma->State != HAL_DMA_STATE_BUSY)
 8001a8c:	687b      	ldr	r3, [r7, #4]
 8001a8e:	f893 3025 	ldrb.w	r3, [r3, #37]	@ 0x25
 8001a92:	b2db      	uxtb	r3, r3
 8001a94:	2b02      	cmp	r3, #2
 8001a96:	d008      	beq.n	8001aaa <HAL_DMA_Abort+0x2a>
  {
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 8001a98:	687b      	ldr	r3, [r7, #4]
 8001a9a:	2204      	movs	r2, #4
 8001a9c:	63da      	str	r2, [r3, #60]	@ 0x3c

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8001a9e:	687b      	ldr	r3, [r7, #4]
 8001aa0:	2200      	movs	r2, #0
 8001aa2:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24

    return HAL_ERROR;
 8001aa6:	2301      	movs	r3, #1
 8001aa8:	e022      	b.n	8001af0 <HAL_DMA_Abort+0x70>
  }
  else
  {
    /* Disable DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8001aaa:	687b      	ldr	r3, [r7, #4]
 8001aac:	681b      	ldr	r3, [r3, #0]
 8001aae:	681a      	ldr	r2, [r3, #0]
 8001ab0:	687b      	ldr	r3, [r7, #4]
 8001ab2:	681b      	ldr	r3, [r3, #0]
 8001ab4:	f022 020e 	bic.w	r2, r2, #14
 8001ab8:	601a      	str	r2, [r3, #0]
    /* disable the DMAMUX sync overrun IT*/
    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
#endif /* DMAMUX1 */

    /* Disable the channel */
    __HAL_DMA_DISABLE(hdma);
 8001aba:	687b      	ldr	r3, [r7, #4]
 8001abc:	681b      	ldr	r3, [r3, #0]
 8001abe:	681a      	ldr	r2, [r3, #0]
 8001ac0:	687b      	ldr	r3, [r7, #4]
 8001ac2:	681b      	ldr	r3, [r3, #0]
 8001ac4:	f022 0201 	bic.w	r2, r2, #1
 8001ac8:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 8001aca:	687b      	ldr	r3, [r7, #4]
 8001acc:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8001ace:	f003 021c 	and.w	r2, r3, #28
 8001ad2:	687b      	ldr	r3, [r7, #4]
 8001ad4:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8001ad6:	2101      	movs	r1, #1
 8001ad8:	fa01 f202 	lsl.w	r2, r1, r2
 8001adc:	605a      	str	r2, [r3, #4]
    }

#endif /* DMAMUX1 */

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 8001ade:	687b      	ldr	r3, [r7, #4]
 8001ae0:	2201      	movs	r2, #1
 8001ae2:	f883 2025 	strb.w	r2, [r3, #37]	@ 0x25

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8001ae6:	687b      	ldr	r3, [r7, #4]
 8001ae8:	2200      	movs	r2, #0
 8001aea:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24

    return status;
 8001aee:	7bfb      	ldrb	r3, [r7, #15]
  }
}
 8001af0:	4618      	mov	r0, r3
 8001af2:	3714      	adds	r7, #20
 8001af4:	46bd      	mov	sp, r7
 8001af6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001afa:	4770      	bx	lr

08001afc <HAL_DMA_Abort_IT>:
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  *                 the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
 8001afc:	b580      	push	{r7, lr}
 8001afe:	b084      	sub	sp, #16
 8001b00:	af00      	add	r7, sp, #0
 8001b02:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 8001b04:	2300      	movs	r3, #0
 8001b06:	73fb      	strb	r3, [r7, #15]

  if (HAL_DMA_STATE_BUSY != hdma->State)
 8001b08:	687b      	ldr	r3, [r7, #4]
 8001b0a:	f893 3025 	ldrb.w	r3, [r3, #37]	@ 0x25
 8001b0e:	b2db      	uxtb	r3, r3
 8001b10:	2b02      	cmp	r3, #2
 8001b12:	d005      	beq.n	8001b20 <HAL_DMA_Abort_IT+0x24>
  {
    /* no transfer ongoing */
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 8001b14:	687b      	ldr	r3, [r7, #4]
 8001b16:	2204      	movs	r2, #4
 8001b18:	63da      	str	r2, [r3, #60]	@ 0x3c

    status = HAL_ERROR;
 8001b1a:	2301      	movs	r3, #1
 8001b1c:	73fb      	strb	r3, [r7, #15]
 8001b1e:	e029      	b.n	8001b74 <HAL_DMA_Abort_IT+0x78>
  }
  else
  {
    /* Disable DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8001b20:	687b      	ldr	r3, [r7, #4]
 8001b22:	681b      	ldr	r3, [r3, #0]
 8001b24:	681a      	ldr	r2, [r3, #0]
 8001b26:	687b      	ldr	r3, [r7, #4]
 8001b28:	681b      	ldr	r3, [r3, #0]
 8001b2a:	f022 020e 	bic.w	r2, r2, #14
 8001b2e:	601a      	str	r2, [r3, #0]

    /* Disable the channel */
    __HAL_DMA_DISABLE(hdma);
 8001b30:	687b      	ldr	r3, [r7, #4]
 8001b32:	681b      	ldr	r3, [r3, #0]
 8001b34:	681a      	ldr	r2, [r3, #0]
 8001b36:	687b      	ldr	r3, [r7, #4]
 8001b38:	681b      	ldr	r3, [r3, #0]
 8001b3a:	f022 0201 	bic.w	r2, r2, #1
 8001b3e:	601a      	str	r2, [r3, #0]
      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
    }

#else
    /* Clear all flags */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 8001b40:	687b      	ldr	r3, [r7, #4]
 8001b42:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8001b44:	f003 021c 	and.w	r2, r3, #28
 8001b48:	687b      	ldr	r3, [r7, #4]
 8001b4a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8001b4c:	2101      	movs	r1, #1
 8001b4e:	fa01 f202 	lsl.w	r2, r1, r2
 8001b52:	605a      	str	r2, [r3, #4]
#endif /* DMAMUX1 */

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 8001b54:	687b      	ldr	r3, [r7, #4]
 8001b56:	2201      	movs	r2, #1
 8001b58:	f883 2025 	strb.w	r2, [r3, #37]	@ 0x25

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8001b5c:	687b      	ldr	r3, [r7, #4]
 8001b5e:	2200      	movs	r2, #0
 8001b60:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24

    /* Call User Abort callback */
    if (hdma->XferAbortCallback != NULL)
 8001b64:	687b      	ldr	r3, [r7, #4]
 8001b66:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8001b68:	2b00      	cmp	r3, #0
 8001b6a:	d003      	beq.n	8001b74 <HAL_DMA_Abort_IT+0x78>
    {
      hdma->XferAbortCallback(hdma);
 8001b6c:	687b      	ldr	r3, [r7, #4]
 8001b6e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8001b70:	6878      	ldr	r0, [r7, #4]
 8001b72:	4798      	blx	r3
    }
  }
  return status;
 8001b74:	7bfb      	ldrb	r3, [r7, #15]
}
 8001b76:	4618      	mov	r0, r3
 8001b78:	3710      	adds	r7, #16
 8001b7a:	46bd      	mov	sp, r7
 8001b7c:	bd80      	pop	{r7, pc}
	...

08001b80 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8001b80:	b480      	push	{r7}
 8001b82:	b087      	sub	sp, #28
 8001b84:	af00      	add	r7, sp, #0
 8001b86:	6078      	str	r0, [r7, #4]
 8001b88:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00u;
 8001b8a:	2300      	movs	r3, #0
 8001b8c:	617b      	str	r3, [r7, #20]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8001b8e:	e17f      	b.n	8001e90 <HAL_GPIO_Init+0x310>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1uL << position);
 8001b90:	683b      	ldr	r3, [r7, #0]
 8001b92:	681a      	ldr	r2, [r3, #0]
 8001b94:	2101      	movs	r1, #1
 8001b96:	697b      	ldr	r3, [r7, #20]
 8001b98:	fa01 f303 	lsl.w	r3, r1, r3
 8001b9c:	4013      	ands	r3, r2
 8001b9e:	60fb      	str	r3, [r7, #12]

    if (iocurrent != 0x00u)
 8001ba0:	68fb      	ldr	r3, [r7, #12]
 8001ba2:	2b00      	cmp	r3, #0
 8001ba4:	f000 8171 	beq.w	8001e8a <HAL_GPIO_Init+0x30a>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 8001ba8:	683b      	ldr	r3, [r7, #0]
 8001baa:	685b      	ldr	r3, [r3, #4]
 8001bac:	f003 0303 	and.w	r3, r3, #3
 8001bb0:	2b01      	cmp	r3, #1
 8001bb2:	d005      	beq.n	8001bc0 <HAL_GPIO_Init+0x40>
 8001bb4:	683b      	ldr	r3, [r7, #0]
 8001bb6:	685b      	ldr	r3, [r3, #4]
 8001bb8:	f003 0303 	and.w	r3, r3, #3
 8001bbc:	2b02      	cmp	r3, #2
 8001bbe:	d130      	bne.n	8001c22 <HAL_GPIO_Init+0xa2>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));

        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 8001bc0:	687b      	ldr	r3, [r7, #4]
 8001bc2:	689b      	ldr	r3, [r3, #8]
 8001bc4:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
 8001bc6:	697b      	ldr	r3, [r7, #20]
 8001bc8:	005b      	lsls	r3, r3, #1
 8001bca:	2203      	movs	r2, #3
 8001bcc:	fa02 f303 	lsl.w	r3, r2, r3
 8001bd0:	43db      	mvns	r3, r3
 8001bd2:	693a      	ldr	r2, [r7, #16]
 8001bd4:	4013      	ands	r3, r2
 8001bd6:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_Init->Speed << (position * 2u));
 8001bd8:	683b      	ldr	r3, [r7, #0]
 8001bda:	68da      	ldr	r2, [r3, #12]
 8001bdc:	697b      	ldr	r3, [r7, #20]
 8001bde:	005b      	lsls	r3, r3, #1
 8001be0:	fa02 f303 	lsl.w	r3, r2, r3
 8001be4:	693a      	ldr	r2, [r7, #16]
 8001be6:	4313      	orrs	r3, r2
 8001be8:	613b      	str	r3, [r7, #16]
        GPIOx->OSPEEDR = temp;
 8001bea:	687b      	ldr	r3, [r7, #4]
 8001bec:	693a      	ldr	r2, [r7, #16]
 8001bee:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 8001bf0:	687b      	ldr	r3, [r7, #4]
 8001bf2:	685b      	ldr	r3, [r3, #4]
 8001bf4:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 8001bf6:	2201      	movs	r2, #1
 8001bf8:	697b      	ldr	r3, [r7, #20]
 8001bfa:	fa02 f303 	lsl.w	r3, r2, r3
 8001bfe:	43db      	mvns	r3, r3
 8001c00:	693a      	ldr	r2, [r7, #16]
 8001c02:	4013      	ands	r3, r2
 8001c04:	613b      	str	r3, [r7, #16]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 8001c06:	683b      	ldr	r3, [r7, #0]
 8001c08:	685b      	ldr	r3, [r3, #4]
 8001c0a:	091b      	lsrs	r3, r3, #4
 8001c0c:	f003 0201 	and.w	r2, r3, #1
 8001c10:	697b      	ldr	r3, [r7, #20]
 8001c12:	fa02 f303 	lsl.w	r3, r2, r3
 8001c16:	693a      	ldr	r2, [r7, #16]
 8001c18:	4313      	orrs	r3, r2
 8001c1a:	613b      	str	r3, [r7, #16]
        GPIOx->OTYPER = temp;
 8001c1c:	687b      	ldr	r3, [r7, #4]
 8001c1e:	693a      	ldr	r2, [r7, #16]
 8001c20:	605a      	str	r2, [r3, #4]
      }

#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)

      /* In case of Analog mode, check if ADC control mode is selected */
      if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
 8001c22:	683b      	ldr	r3, [r7, #0]
 8001c24:	685b      	ldr	r3, [r3, #4]
 8001c26:	f003 0303 	and.w	r3, r3, #3
 8001c2a:	2b03      	cmp	r3, #3
 8001c2c:	d118      	bne.n	8001c60 <HAL_GPIO_Init+0xe0>
      {
        /* Configure the IO Output Type */
        temp = GPIOx->ASCR;
 8001c2e:	687b      	ldr	r3, [r7, #4]
 8001c30:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001c32:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_ASCR_ASC0 << position) ;
 8001c34:	2201      	movs	r2, #1
 8001c36:	697b      	ldr	r3, [r7, #20]
 8001c38:	fa02 f303 	lsl.w	r3, r2, r3
 8001c3c:	43db      	mvns	r3, r3
 8001c3e:	693a      	ldr	r2, [r7, #16]
 8001c40:	4013      	ands	r3, r2
 8001c42:	613b      	str	r3, [r7, #16]
        temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
 8001c44:	683b      	ldr	r3, [r7, #0]
 8001c46:	685b      	ldr	r3, [r3, #4]
 8001c48:	08db      	lsrs	r3, r3, #3
 8001c4a:	f003 0201 	and.w	r2, r3, #1
 8001c4e:	697b      	ldr	r3, [r7, #20]
 8001c50:	fa02 f303 	lsl.w	r3, r2, r3
 8001c54:	693a      	ldr	r2, [r7, #16]
 8001c56:	4313      	orrs	r3, r2
 8001c58:	613b      	str	r3, [r7, #16]
        GPIOx->ASCR = temp;
 8001c5a:	687b      	ldr	r3, [r7, #4]
 8001c5c:	693a      	ldr	r2, [r7, #16]
 8001c5e:	62da      	str	r2, [r3, #44]	@ 0x2c
      }

#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */

      /* Activate the Pull-up or Pull down resistor for the current IO */
      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8001c60:	683b      	ldr	r3, [r7, #0]
 8001c62:	685b      	ldr	r3, [r3, #4]
 8001c64:	f003 0303 	and.w	r3, r3, #3
 8001c68:	2b03      	cmp	r3, #3
 8001c6a:	d017      	beq.n	8001c9c <HAL_GPIO_Init+0x11c>
      {
        /* Check the Pull parameter */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

        temp = GPIOx->PUPDR;
 8001c6c:	687b      	ldr	r3, [r7, #4]
 8001c6e:	68db      	ldr	r3, [r3, #12]
 8001c70:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 8001c72:	697b      	ldr	r3, [r7, #20]
 8001c74:	005b      	lsls	r3, r3, #1
 8001c76:	2203      	movs	r2, #3
 8001c78:	fa02 f303 	lsl.w	r3, r2, r3
 8001c7c:	43db      	mvns	r3, r3
 8001c7e:	693a      	ldr	r2, [r7, #16]
 8001c80:	4013      	ands	r3, r2
 8001c82:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 8001c84:	683b      	ldr	r3, [r7, #0]
 8001c86:	689a      	ldr	r2, [r3, #8]
 8001c88:	697b      	ldr	r3, [r7, #20]
 8001c8a:	005b      	lsls	r3, r3, #1
 8001c8c:	fa02 f303 	lsl.w	r3, r2, r3
 8001c90:	693a      	ldr	r2, [r7, #16]
 8001c92:	4313      	orrs	r3, r2
 8001c94:	613b      	str	r3, [r7, #16]
        GPIOx->PUPDR = temp;
 8001c96:	687b      	ldr	r3, [r7, #4]
 8001c98:	693a      	ldr	r2, [r7, #16]
 8001c9a:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8001c9c:	683b      	ldr	r3, [r7, #0]
 8001c9e:	685b      	ldr	r3, [r3, #4]
 8001ca0:	f003 0303 	and.w	r3, r3, #3
 8001ca4:	2b02      	cmp	r3, #2
 8001ca6:	d123      	bne.n	8001cf0 <HAL_GPIO_Init+0x170>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3u];
 8001ca8:	697b      	ldr	r3, [r7, #20]
 8001caa:	08da      	lsrs	r2, r3, #3
 8001cac:	687b      	ldr	r3, [r7, #4]
 8001cae:	3208      	adds	r2, #8
 8001cb0:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 8001cb4:	613b      	str	r3, [r7, #16]
        temp &= ~(0xFu << ((position & 0x07u) * 4u));
 8001cb6:	697b      	ldr	r3, [r7, #20]
 8001cb8:	f003 0307 	and.w	r3, r3, #7
 8001cbc:	009b      	lsls	r3, r3, #2
 8001cbe:	220f      	movs	r2, #15
 8001cc0:	fa02 f303 	lsl.w	r3, r2, r3
 8001cc4:	43db      	mvns	r3, r3
 8001cc6:	693a      	ldr	r2, [r7, #16]
 8001cc8:	4013      	ands	r3, r2
 8001cca:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
 8001ccc:	683b      	ldr	r3, [r7, #0]
 8001cce:	691a      	ldr	r2, [r3, #16]
 8001cd0:	697b      	ldr	r3, [r7, #20]
 8001cd2:	f003 0307 	and.w	r3, r3, #7
 8001cd6:	009b      	lsls	r3, r3, #2
 8001cd8:	fa02 f303 	lsl.w	r3, r2, r3
 8001cdc:	693a      	ldr	r2, [r7, #16]
 8001cde:	4313      	orrs	r3, r2
 8001ce0:	613b      	str	r3, [r7, #16]
        GPIOx->AFR[position >> 3u] = temp;
 8001ce2:	697b      	ldr	r3, [r7, #20]
 8001ce4:	08da      	lsrs	r2, r3, #3
 8001ce6:	687b      	ldr	r3, [r7, #4]
 8001ce8:	3208      	adds	r2, #8
 8001cea:	6939      	ldr	r1, [r7, #16]
 8001cec:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 8001cf0:	687b      	ldr	r3, [r7, #4]
 8001cf2:	681b      	ldr	r3, [r3, #0]
 8001cf4:	613b      	str	r3, [r7, #16]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
 8001cf6:	697b      	ldr	r3, [r7, #20]
 8001cf8:	005b      	lsls	r3, r3, #1
 8001cfa:	2203      	movs	r2, #3
 8001cfc:	fa02 f303 	lsl.w	r3, r2, r3
 8001d00:	43db      	mvns	r3, r3
 8001d02:	693a      	ldr	r2, [r7, #16]
 8001d04:	4013      	ands	r3, r2
 8001d06:	613b      	str	r3, [r7, #16]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
 8001d08:	683b      	ldr	r3, [r7, #0]
 8001d0a:	685b      	ldr	r3, [r3, #4]
 8001d0c:	f003 0203 	and.w	r2, r3, #3
 8001d10:	697b      	ldr	r3, [r7, #20]
 8001d12:	005b      	lsls	r3, r3, #1
 8001d14:	fa02 f303 	lsl.w	r3, r2, r3
 8001d18:	693a      	ldr	r2, [r7, #16]
 8001d1a:	4313      	orrs	r3, r2
 8001d1c:	613b      	str	r3, [r7, #16]
      GPIOx->MODER = temp;
 8001d1e:	687b      	ldr	r3, [r7, #4]
 8001d20:	693a      	ldr	r2, [r7, #16]
 8001d22:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 8001d24:	683b      	ldr	r3, [r7, #0]
 8001d26:	685b      	ldr	r3, [r3, #4]
 8001d28:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 8001d2c:	2b00      	cmp	r3, #0
 8001d2e:	f000 80ac 	beq.w	8001e8a <HAL_GPIO_Init+0x30a>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8001d32:	4b5f      	ldr	r3, [pc, #380]	@ (8001eb0 <HAL_GPIO_Init+0x330>)
 8001d34:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001d36:	4a5e      	ldr	r2, [pc, #376]	@ (8001eb0 <HAL_GPIO_Init+0x330>)
 8001d38:	f043 0301 	orr.w	r3, r3, #1
 8001d3c:	6613      	str	r3, [r2, #96]	@ 0x60
 8001d3e:	4b5c      	ldr	r3, [pc, #368]	@ (8001eb0 <HAL_GPIO_Init+0x330>)
 8001d40:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001d42:	f003 0301 	and.w	r3, r3, #1
 8001d46:	60bb      	str	r3, [r7, #8]
 8001d48:	68bb      	ldr	r3, [r7, #8]

        temp = SYSCFG->EXTICR[position >> 2u];
 8001d4a:	4a5a      	ldr	r2, [pc, #360]	@ (8001eb4 <HAL_GPIO_Init+0x334>)
 8001d4c:	697b      	ldr	r3, [r7, #20]
 8001d4e:	089b      	lsrs	r3, r3, #2
 8001d50:	3302      	adds	r3, #2
 8001d52:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8001d56:	613b      	str	r3, [r7, #16]
        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
 8001d58:	697b      	ldr	r3, [r7, #20]
 8001d5a:	f003 0303 	and.w	r3, r3, #3
 8001d5e:	009b      	lsls	r3, r3, #2
 8001d60:	220f      	movs	r2, #15
 8001d62:	fa02 f303 	lsl.w	r3, r2, r3
 8001d66:	43db      	mvns	r3, r3
 8001d68:	693a      	ldr	r2, [r7, #16]
 8001d6a:	4013      	ands	r3, r2
 8001d6c:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
 8001d6e:	687b      	ldr	r3, [r7, #4]
 8001d70:	f1b3 4f90 	cmp.w	r3, #1207959552	@ 0x48000000
 8001d74:	d025      	beq.n	8001dc2 <HAL_GPIO_Init+0x242>
 8001d76:	687b      	ldr	r3, [r7, #4]
 8001d78:	4a4f      	ldr	r2, [pc, #316]	@ (8001eb8 <HAL_GPIO_Init+0x338>)
 8001d7a:	4293      	cmp	r3, r2
 8001d7c:	d01f      	beq.n	8001dbe <HAL_GPIO_Init+0x23e>
 8001d7e:	687b      	ldr	r3, [r7, #4]
 8001d80:	4a4e      	ldr	r2, [pc, #312]	@ (8001ebc <HAL_GPIO_Init+0x33c>)
 8001d82:	4293      	cmp	r3, r2
 8001d84:	d019      	beq.n	8001dba <HAL_GPIO_Init+0x23a>
 8001d86:	687b      	ldr	r3, [r7, #4]
 8001d88:	4a4d      	ldr	r2, [pc, #308]	@ (8001ec0 <HAL_GPIO_Init+0x340>)
 8001d8a:	4293      	cmp	r3, r2
 8001d8c:	d013      	beq.n	8001db6 <HAL_GPIO_Init+0x236>
 8001d8e:	687b      	ldr	r3, [r7, #4]
 8001d90:	4a4c      	ldr	r2, [pc, #304]	@ (8001ec4 <HAL_GPIO_Init+0x344>)
 8001d92:	4293      	cmp	r3, r2
 8001d94:	d00d      	beq.n	8001db2 <HAL_GPIO_Init+0x232>
 8001d96:	687b      	ldr	r3, [r7, #4]
 8001d98:	4a4b      	ldr	r2, [pc, #300]	@ (8001ec8 <HAL_GPIO_Init+0x348>)
 8001d9a:	4293      	cmp	r3, r2
 8001d9c:	d007      	beq.n	8001dae <HAL_GPIO_Init+0x22e>
 8001d9e:	687b      	ldr	r3, [r7, #4]
 8001da0:	4a4a      	ldr	r2, [pc, #296]	@ (8001ecc <HAL_GPIO_Init+0x34c>)
 8001da2:	4293      	cmp	r3, r2
 8001da4:	d101      	bne.n	8001daa <HAL_GPIO_Init+0x22a>
 8001da6:	2306      	movs	r3, #6
 8001da8:	e00c      	b.n	8001dc4 <HAL_GPIO_Init+0x244>
 8001daa:	2307      	movs	r3, #7
 8001dac:	e00a      	b.n	8001dc4 <HAL_GPIO_Init+0x244>
 8001dae:	2305      	movs	r3, #5
 8001db0:	e008      	b.n	8001dc4 <HAL_GPIO_Init+0x244>
 8001db2:	2304      	movs	r3, #4
 8001db4:	e006      	b.n	8001dc4 <HAL_GPIO_Init+0x244>
 8001db6:	2303      	movs	r3, #3
 8001db8:	e004      	b.n	8001dc4 <HAL_GPIO_Init+0x244>
 8001dba:	2302      	movs	r3, #2
 8001dbc:	e002      	b.n	8001dc4 <HAL_GPIO_Init+0x244>
 8001dbe:	2301      	movs	r3, #1
 8001dc0:	e000      	b.n	8001dc4 <HAL_GPIO_Init+0x244>
 8001dc2:	2300      	movs	r3, #0
 8001dc4:	697a      	ldr	r2, [r7, #20]
 8001dc6:	f002 0203 	and.w	r2, r2, #3
 8001dca:	0092      	lsls	r2, r2, #2
 8001dcc:	4093      	lsls	r3, r2
 8001dce:	693a      	ldr	r2, [r7, #16]
 8001dd0:	4313      	orrs	r3, r2
 8001dd2:	613b      	str	r3, [r7, #16]
        SYSCFG->EXTICR[position >> 2u] = temp;
 8001dd4:	4937      	ldr	r1, [pc, #220]	@ (8001eb4 <HAL_GPIO_Init+0x334>)
 8001dd6:	697b      	ldr	r3, [r7, #20]
 8001dd8:	089b      	lsrs	r3, r3, #2
 8001dda:	3302      	adds	r3, #2
 8001ddc:	693a      	ldr	r2, [r7, #16]
 8001dde:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 8001de2:	4b3b      	ldr	r3, [pc, #236]	@ (8001ed0 <HAL_GPIO_Init+0x350>)
 8001de4:	689b      	ldr	r3, [r3, #8]
 8001de6:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001de8:	68fb      	ldr	r3, [r7, #12]
 8001dea:	43db      	mvns	r3, r3
 8001dec:	693a      	ldr	r2, [r7, #16]
 8001dee:	4013      	ands	r3, r2
 8001df0:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
 8001df2:	683b      	ldr	r3, [r7, #0]
 8001df4:	685b      	ldr	r3, [r3, #4]
 8001df6:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 8001dfa:	2b00      	cmp	r3, #0
 8001dfc:	d003      	beq.n	8001e06 <HAL_GPIO_Init+0x286>
        {
          temp |= iocurrent;
 8001dfe:	693a      	ldr	r2, [r7, #16]
 8001e00:	68fb      	ldr	r3, [r7, #12]
 8001e02:	4313      	orrs	r3, r2
 8001e04:	613b      	str	r3, [r7, #16]
        }
        EXTI->RTSR1 = temp;
 8001e06:	4a32      	ldr	r2, [pc, #200]	@ (8001ed0 <HAL_GPIO_Init+0x350>)
 8001e08:	693b      	ldr	r3, [r7, #16]
 8001e0a:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR1;
 8001e0c:	4b30      	ldr	r3, [pc, #192]	@ (8001ed0 <HAL_GPIO_Init+0x350>)
 8001e0e:	68db      	ldr	r3, [r3, #12]
 8001e10:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001e12:	68fb      	ldr	r3, [r7, #12]
 8001e14:	43db      	mvns	r3, r3
 8001e16:	693a      	ldr	r2, [r7, #16]
 8001e18:	4013      	ands	r3, r2
 8001e1a:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
 8001e1c:	683b      	ldr	r3, [r7, #0]
 8001e1e:	685b      	ldr	r3, [r3, #4]
 8001e20:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
 8001e24:	2b00      	cmp	r3, #0
 8001e26:	d003      	beq.n	8001e30 <HAL_GPIO_Init+0x2b0>
        {
          temp |= iocurrent;
 8001e28:	693a      	ldr	r2, [r7, #16]
 8001e2a:	68fb      	ldr	r3, [r7, #12]
 8001e2c:	4313      	orrs	r3, r2
 8001e2e:	613b      	str	r3, [r7, #16]
        }
        EXTI->FTSR1 = temp;
 8001e30:	4a27      	ldr	r2, [pc, #156]	@ (8001ed0 <HAL_GPIO_Init+0x350>)
 8001e32:	693b      	ldr	r3, [r7, #16]
 8001e34:	60d3      	str	r3, [r2, #12]

        /* Clear EXTI line configuration */
        temp = EXTI->EMR1;
 8001e36:	4b26      	ldr	r3, [pc, #152]	@ (8001ed0 <HAL_GPIO_Init+0x350>)
 8001e38:	685b      	ldr	r3, [r3, #4]
 8001e3a:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001e3c:	68fb      	ldr	r3, [r7, #12]
 8001e3e:	43db      	mvns	r3, r3
 8001e40:	693a      	ldr	r2, [r7, #16]
 8001e42:	4013      	ands	r3, r2
 8001e44:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
 8001e46:	683b      	ldr	r3, [r7, #0]
 8001e48:	685b      	ldr	r3, [r3, #4]
 8001e4a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8001e4e:	2b00      	cmp	r3, #0
 8001e50:	d003      	beq.n	8001e5a <HAL_GPIO_Init+0x2da>
        {
          temp |= iocurrent;
 8001e52:	693a      	ldr	r2, [r7, #16]
 8001e54:	68fb      	ldr	r3, [r7, #12]
 8001e56:	4313      	orrs	r3, r2
 8001e58:	613b      	str	r3, [r7, #16]
        }
        EXTI->EMR1 = temp;
 8001e5a:	4a1d      	ldr	r2, [pc, #116]	@ (8001ed0 <HAL_GPIO_Init+0x350>)
 8001e5c:	693b      	ldr	r3, [r7, #16]
 8001e5e:	6053      	str	r3, [r2, #4]

        temp = EXTI->IMR1;
 8001e60:	4b1b      	ldr	r3, [pc, #108]	@ (8001ed0 <HAL_GPIO_Init+0x350>)
 8001e62:	681b      	ldr	r3, [r3, #0]
 8001e64:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001e66:	68fb      	ldr	r3, [r7, #12]
 8001e68:	43db      	mvns	r3, r3
 8001e6a:	693a      	ldr	r2, [r7, #16]
 8001e6c:	4013      	ands	r3, r2
 8001e6e:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
 8001e70:	683b      	ldr	r3, [r7, #0]
 8001e72:	685b      	ldr	r3, [r3, #4]
 8001e74:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8001e78:	2b00      	cmp	r3, #0
 8001e7a:	d003      	beq.n	8001e84 <HAL_GPIO_Init+0x304>
        {
          temp |= iocurrent;
 8001e7c:	693a      	ldr	r2, [r7, #16]
 8001e7e:	68fb      	ldr	r3, [r7, #12]
 8001e80:	4313      	orrs	r3, r2
 8001e82:	613b      	str	r3, [r7, #16]
        }
        EXTI->IMR1 = temp;
 8001e84:	4a12      	ldr	r2, [pc, #72]	@ (8001ed0 <HAL_GPIO_Init+0x350>)
 8001e86:	693b      	ldr	r3, [r7, #16]
 8001e88:	6013      	str	r3, [r2, #0]
      }
    }

    position++;
 8001e8a:	697b      	ldr	r3, [r7, #20]
 8001e8c:	3301      	adds	r3, #1
 8001e8e:	617b      	str	r3, [r7, #20]
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8001e90:	683b      	ldr	r3, [r7, #0]
 8001e92:	681a      	ldr	r2, [r3, #0]
 8001e94:	697b      	ldr	r3, [r7, #20]
 8001e96:	fa22 f303 	lsr.w	r3, r2, r3
 8001e9a:	2b00      	cmp	r3, #0
 8001e9c:	f47f ae78 	bne.w	8001b90 <HAL_GPIO_Init+0x10>
  }
}
 8001ea0:	bf00      	nop
 8001ea2:	bf00      	nop
 8001ea4:	371c      	adds	r7, #28
 8001ea6:	46bd      	mov	sp, r7
 8001ea8:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001eac:	4770      	bx	lr
 8001eae:	bf00      	nop
 8001eb0:	40021000 	.word	0x40021000
 8001eb4:	40010000 	.word	0x40010000
 8001eb8:	48000400 	.word	0x48000400
 8001ebc:	48000800 	.word	0x48000800
 8001ec0:	48000c00 	.word	0x48000c00
 8001ec4:	48001000 	.word	0x48001000
 8001ec8:	48001400 	.word	0x48001400
 8001ecc:	48001800 	.word	0x48001800
 8001ed0:	40010400 	.word	0x40010400

08001ed4 <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 8001ed4:	b480      	push	{r7}
 8001ed6:	b083      	sub	sp, #12
 8001ed8:	af00      	add	r7, sp, #0
 8001eda:	6078      	str	r0, [r7, #4]
 8001edc:	460b      	mov	r3, r1
 8001ede:	807b      	strh	r3, [r7, #2]
 8001ee0:	4613      	mov	r3, r2
 8001ee2:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if(PinState != GPIO_PIN_RESET)
 8001ee4:	787b      	ldrb	r3, [r7, #1]
 8001ee6:	2b00      	cmp	r3, #0
 8001ee8:	d003      	beq.n	8001ef2 <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8001eea:	887a      	ldrh	r2, [r7, #2]
 8001eec:	687b      	ldr	r3, [r7, #4]
 8001eee:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BRR = (uint32_t)GPIO_Pin;
  }
}
 8001ef0:	e002      	b.n	8001ef8 <HAL_GPIO_WritePin+0x24>
    GPIOx->BRR = (uint32_t)GPIO_Pin;
 8001ef2:	887a      	ldrh	r2, [r7, #2]
 8001ef4:	687b      	ldr	r3, [r7, #4]
 8001ef6:	629a      	str	r2, [r3, #40]	@ 0x28
}
 8001ef8:	bf00      	nop
 8001efa:	370c      	adds	r7, #12
 8001efc:	46bd      	mov	sp, r7
 8001efe:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001f02:	4770      	bx	lr

08001f04 <HAL_GPIO_EXTI_IRQHandler>:
  * @brief  Handle EXTI interrupt request.
  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
  * @retval None
  */
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
 8001f04:	b580      	push	{r7, lr}
 8001f06:	b082      	sub	sp, #8
 8001f08:	af00      	add	r7, sp, #0
 8001f0a:	4603      	mov	r3, r0
 8001f0c:	80fb      	strh	r3, [r7, #6]
  /* EXTI line interrupt detected */
  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
 8001f0e:	4b08      	ldr	r3, [pc, #32]	@ (8001f30 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
 8001f10:	695a      	ldr	r2, [r3, #20]
 8001f12:	88fb      	ldrh	r3, [r7, #6]
 8001f14:	4013      	ands	r3, r2
 8001f16:	2b00      	cmp	r3, #0
 8001f18:	d006      	beq.n	8001f28 <HAL_GPIO_EXTI_IRQHandler+0x24>
  {
    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
 8001f1a:	4a05      	ldr	r2, [pc, #20]	@ (8001f30 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
 8001f1c:	88fb      	ldrh	r3, [r7, #6]
 8001f1e:	6153      	str	r3, [r2, #20]
    HAL_GPIO_EXTI_Callback(GPIO_Pin);
 8001f20:	88fb      	ldrh	r3, [r7, #6]
 8001f22:	4618      	mov	r0, r3
 8001f24:	f000 f806 	bl	8001f34 <HAL_GPIO_EXTI_Callback>
  }
}
 8001f28:	bf00      	nop
 8001f2a:	3708      	adds	r7, #8
 8001f2c:	46bd      	mov	sp, r7
 8001f2e:	bd80      	pop	{r7, pc}
 8001f30:	40010400 	.word	0x40010400

08001f34 <HAL_GPIO_EXTI_Callback>:
  * @brief  EXTI line detection callback.
  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
  * @retval None
  */
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
 8001f34:	b480      	push	{r7}
 8001f36:	b083      	sub	sp, #12
 8001f38:	af00      	add	r7, sp, #0
 8001f3a:	4603      	mov	r3, r0
 8001f3c:	80fb      	strh	r3, [r7, #6]
  UNUSED(GPIO_Pin);

  /* NOTE: This function should not be modified, when the callback is needed,
           the HAL_GPIO_EXTI_Callback could be implemented in the user file
   */
}
 8001f3e:	bf00      	nop
 8001f40:	370c      	adds	r7, #12
 8001f42:	46bd      	mov	sp, r7
 8001f44:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001f48:	4770      	bx	lr

08001f4a <HAL_I2C_Init>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *                the configuration information for the specified I2C.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
 8001f4a:	b580      	push	{r7, lr}
 8001f4c:	b082      	sub	sp, #8
 8001f4e:	af00      	add	r7, sp, #0
 8001f50:	6078      	str	r0, [r7, #4]
  /* Check the I2C handle allocation */
  if (hi2c == NULL)
 8001f52:	687b      	ldr	r3, [r7, #4]
 8001f54:	2b00      	cmp	r3, #0
 8001f56:	d101      	bne.n	8001f5c <HAL_I2C_Init+0x12>
  {
    return HAL_ERROR;
 8001f58:	2301      	movs	r3, #1
 8001f5a:	e08d      	b.n	8002078 <HAL_I2C_Init+0x12e>
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));

  if (hi2c->State == HAL_I2C_STATE_RESET)
 8001f5c:	687b      	ldr	r3, [r7, #4]
 8001f5e:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 8001f62:	b2db      	uxtb	r3, r3
 8001f64:	2b00      	cmp	r3, #0
 8001f66:	d106      	bne.n	8001f76 <HAL_I2C_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    hi2c->Lock = HAL_UNLOCKED;
 8001f68:	687b      	ldr	r3, [r7, #4]
 8001f6a:	2200      	movs	r2, #0
 8001f6c:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
    hi2c->MspInitCallback(hi2c);
#else
    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
    HAL_I2C_MspInit(hi2c);
 8001f70:	6878      	ldr	r0, [r7, #4]
 8001f72:	f7ff f80b 	bl	8000f8c <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
  }

  hi2c->State = HAL_I2C_STATE_BUSY;
 8001f76:	687b      	ldr	r3, [r7, #4]
 8001f78:	2224      	movs	r2, #36	@ 0x24
 8001f7a:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

  /* Disable the selected I2C peripheral */
  __HAL_I2C_DISABLE(hi2c);
 8001f7e:	687b      	ldr	r3, [r7, #4]
 8001f80:	681b      	ldr	r3, [r3, #0]
 8001f82:	681a      	ldr	r2, [r3, #0]
 8001f84:	687b      	ldr	r3, [r7, #4]
 8001f86:	681b      	ldr	r3, [r3, #0]
 8001f88:	f022 0201 	bic.w	r2, r2, #1
 8001f8c:	601a      	str	r2, [r3, #0]

  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
  /* Configure I2Cx: Frequency range */
  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
 8001f8e:	687b      	ldr	r3, [r7, #4]
 8001f90:	685a      	ldr	r2, [r3, #4]
 8001f92:	687b      	ldr	r3, [r7, #4]
 8001f94:	681b      	ldr	r3, [r3, #0]
 8001f96:	f022 6270 	bic.w	r2, r2, #251658240	@ 0xf000000
 8001f9a:	611a      	str	r2, [r3, #16]

  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
  /* Disable Own Address1 before set the Own Address1 configuration */
  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
 8001f9c:	687b      	ldr	r3, [r7, #4]
 8001f9e:	681b      	ldr	r3, [r3, #0]
 8001fa0:	689a      	ldr	r2, [r3, #8]
 8001fa2:	687b      	ldr	r3, [r7, #4]
 8001fa4:	681b      	ldr	r3, [r3, #0]
 8001fa6:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
 8001faa:	609a      	str	r2, [r3, #8]

  /* Configure I2Cx: Own Address1 and ack own address1 mode */
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
 8001fac:	687b      	ldr	r3, [r7, #4]
 8001fae:	68db      	ldr	r3, [r3, #12]
 8001fb0:	2b01      	cmp	r3, #1
 8001fb2:	d107      	bne.n	8001fc4 <HAL_I2C_Init+0x7a>
  {
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
 8001fb4:	687b      	ldr	r3, [r7, #4]
 8001fb6:	689a      	ldr	r2, [r3, #8]
 8001fb8:	687b      	ldr	r3, [r7, #4]
 8001fba:	681b      	ldr	r3, [r3, #0]
 8001fbc:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
 8001fc0:	609a      	str	r2, [r3, #8]
 8001fc2:	e006      	b.n	8001fd2 <HAL_I2C_Init+0x88>
  }
  else /* I2C_ADDRESSINGMODE_10BIT */
  {
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
 8001fc4:	687b      	ldr	r3, [r7, #4]
 8001fc6:	689a      	ldr	r2, [r3, #8]
 8001fc8:	687b      	ldr	r3, [r7, #4]
 8001fca:	681b      	ldr	r3, [r3, #0]
 8001fcc:	f442 4204 	orr.w	r2, r2, #33792	@ 0x8400
 8001fd0:	609a      	str	r2, [r3, #8]
  }

  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
  /* Configure I2Cx: Addressing Master mode */
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
 8001fd2:	687b      	ldr	r3, [r7, #4]
 8001fd4:	68db      	ldr	r3, [r3, #12]
 8001fd6:	2b02      	cmp	r3, #2
 8001fd8:	d108      	bne.n	8001fec <HAL_I2C_Init+0xa2>
  {
    SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
 8001fda:	687b      	ldr	r3, [r7, #4]
 8001fdc:	681b      	ldr	r3, [r3, #0]
 8001fde:	685a      	ldr	r2, [r3, #4]
 8001fe0:	687b      	ldr	r3, [r7, #4]
 8001fe2:	681b      	ldr	r3, [r3, #0]
 8001fe4:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
 8001fe8:	605a      	str	r2, [r3, #4]
 8001fea:	e007      	b.n	8001ffc <HAL_I2C_Init+0xb2>
  }
  else
  {
    /* Clear the I2C ADD10 bit */
    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
 8001fec:	687b      	ldr	r3, [r7, #4]
 8001fee:	681b      	ldr	r3, [r3, #0]
 8001ff0:	685a      	ldr	r2, [r3, #4]
 8001ff2:	687b      	ldr	r3, [r7, #4]
 8001ff4:	681b      	ldr	r3, [r3, #0]
 8001ff6:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
 8001ffa:	605a      	str	r2, [r3, #4]
  }
  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
 8001ffc:	687b      	ldr	r3, [r7, #4]
 8001ffe:	681b      	ldr	r3, [r3, #0]
 8002000:	685b      	ldr	r3, [r3, #4]
 8002002:	687a      	ldr	r2, [r7, #4]
 8002004:	6812      	ldr	r2, [r2, #0]
 8002006:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
 800200a:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
 800200e:	6053      	str	r3, [r2, #4]

  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
  /* Disable Own Address2 before set the Own Address2 configuration */
  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
 8002010:	687b      	ldr	r3, [r7, #4]
 8002012:	681b      	ldr	r3, [r3, #0]
 8002014:	68da      	ldr	r2, [r3, #12]
 8002016:	687b      	ldr	r3, [r7, #4]
 8002018:	681b      	ldr	r3, [r3, #0]
 800201a:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
 800201e:	60da      	str	r2, [r3, #12]

  /* Configure I2Cx: Dual mode and Own Address2 */
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
 8002020:	687b      	ldr	r3, [r7, #4]
 8002022:	691a      	ldr	r2, [r3, #16]
 8002024:	687b      	ldr	r3, [r7, #4]
 8002026:	695b      	ldr	r3, [r3, #20]
 8002028:	ea42 0103 	orr.w	r1, r2, r3
                          (hi2c->Init.OwnAddress2Masks << 8));
 800202c:	687b      	ldr	r3, [r7, #4]
 800202e:	699b      	ldr	r3, [r3, #24]
 8002030:	021a      	lsls	r2, r3, #8
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
 8002032:	687b      	ldr	r3, [r7, #4]
 8002034:	681b      	ldr	r3, [r3, #0]
 8002036:	430a      	orrs	r2, r1
 8002038:	60da      	str	r2, [r3, #12]

  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
  /* Configure I2Cx: Generalcall and NoStretch mode */
  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
 800203a:	687b      	ldr	r3, [r7, #4]
 800203c:	69d9      	ldr	r1, [r3, #28]
 800203e:	687b      	ldr	r3, [r7, #4]
 8002040:	6a1a      	ldr	r2, [r3, #32]
 8002042:	687b      	ldr	r3, [r7, #4]
 8002044:	681b      	ldr	r3, [r3, #0]
 8002046:	430a      	orrs	r2, r1
 8002048:	601a      	str	r2, [r3, #0]

  /* Enable the selected I2C peripheral */
  __HAL_I2C_ENABLE(hi2c);
 800204a:	687b      	ldr	r3, [r7, #4]
 800204c:	681b      	ldr	r3, [r3, #0]
 800204e:	681a      	ldr	r2, [r3, #0]
 8002050:	687b      	ldr	r3, [r7, #4]
 8002052:	681b      	ldr	r3, [r3, #0]
 8002054:	f042 0201 	orr.w	r2, r2, #1
 8002058:	601a      	str	r2, [r3, #0]

  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 800205a:	687b      	ldr	r3, [r7, #4]
 800205c:	2200      	movs	r2, #0
 800205e:	645a      	str	r2, [r3, #68]	@ 0x44
  hi2c->State = HAL_I2C_STATE_READY;
 8002060:	687b      	ldr	r3, [r7, #4]
 8002062:	2220      	movs	r2, #32
 8002064:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
  hi2c->PreviousState = I2C_STATE_NONE;
 8002068:	687b      	ldr	r3, [r7, #4]
 800206a:	2200      	movs	r2, #0
 800206c:	631a      	str	r2, [r3, #48]	@ 0x30
  hi2c->Mode = HAL_I2C_MODE_NONE;
 800206e:	687b      	ldr	r3, [r7, #4]
 8002070:	2200      	movs	r2, #0
 8002072:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

  return HAL_OK;
 8002076:	2300      	movs	r3, #0
}
 8002078:	4618      	mov	r0, r3
 800207a:	3708      	adds	r7, #8
 800207c:	46bd      	mov	sp, r7
 800207e:	bd80      	pop	{r7, pc}

08002080 <HAL_I2CEx_ConfigAnalogFilter>:
  *                the configuration information for the specified I2Cx peripheral.
  * @param  AnalogFilter New state of the Analog filter.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
 8002080:	b480      	push	{r7}
 8002082:	b083      	sub	sp, #12
 8002084:	af00      	add	r7, sp, #0
 8002086:	6078      	str	r0, [r7, #4]
 8002088:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));

  if (hi2c->State == HAL_I2C_STATE_READY)
 800208a:	687b      	ldr	r3, [r7, #4]
 800208c:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 8002090:	b2db      	uxtb	r3, r3
 8002092:	2b20      	cmp	r3, #32
 8002094:	d138      	bne.n	8002108 <HAL_I2CEx_ConfigAnalogFilter+0x88>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 8002096:	687b      	ldr	r3, [r7, #4]
 8002098:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 800209c:	2b01      	cmp	r3, #1
 800209e:	d101      	bne.n	80020a4 <HAL_I2CEx_ConfigAnalogFilter+0x24>
 80020a0:	2302      	movs	r3, #2
 80020a2:	e032      	b.n	800210a <HAL_I2CEx_ConfigAnalogFilter+0x8a>
 80020a4:	687b      	ldr	r3, [r7, #4]
 80020a6:	2201      	movs	r2, #1
 80020a8:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    hi2c->State = HAL_I2C_STATE_BUSY;
 80020ac:	687b      	ldr	r3, [r7, #4]
 80020ae:	2224      	movs	r2, #36	@ 0x24
 80020b0:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Disable the selected I2C peripheral */
    __HAL_I2C_DISABLE(hi2c);
 80020b4:	687b      	ldr	r3, [r7, #4]
 80020b6:	681b      	ldr	r3, [r3, #0]
 80020b8:	681a      	ldr	r2, [r3, #0]
 80020ba:	687b      	ldr	r3, [r7, #4]
 80020bc:	681b      	ldr	r3, [r3, #0]
 80020be:	f022 0201 	bic.w	r2, r2, #1
 80020c2:	601a      	str	r2, [r3, #0]

    /* Reset I2Cx ANOFF bit */
    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
 80020c4:	687b      	ldr	r3, [r7, #4]
 80020c6:	681b      	ldr	r3, [r3, #0]
 80020c8:	681a      	ldr	r2, [r3, #0]
 80020ca:	687b      	ldr	r3, [r7, #4]
 80020cc:	681b      	ldr	r3, [r3, #0]
 80020ce:	f422 5280 	bic.w	r2, r2, #4096	@ 0x1000
 80020d2:	601a      	str	r2, [r3, #0]

    /* Set analog filter bit*/
    hi2c->Instance->CR1 |= AnalogFilter;
 80020d4:	687b      	ldr	r3, [r7, #4]
 80020d6:	681b      	ldr	r3, [r3, #0]
 80020d8:	6819      	ldr	r1, [r3, #0]
 80020da:	687b      	ldr	r3, [r7, #4]
 80020dc:	681b      	ldr	r3, [r3, #0]
 80020de:	683a      	ldr	r2, [r7, #0]
 80020e0:	430a      	orrs	r2, r1
 80020e2:	601a      	str	r2, [r3, #0]

    __HAL_I2C_ENABLE(hi2c);
 80020e4:	687b      	ldr	r3, [r7, #4]
 80020e6:	681b      	ldr	r3, [r3, #0]
 80020e8:	681a      	ldr	r2, [r3, #0]
 80020ea:	687b      	ldr	r3, [r7, #4]
 80020ec:	681b      	ldr	r3, [r3, #0]
 80020ee:	f042 0201 	orr.w	r2, r2, #1
 80020f2:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 80020f4:	687b      	ldr	r3, [r7, #4]
 80020f6:	2220      	movs	r2, #32
 80020f8:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 80020fc:	687b      	ldr	r3, [r7, #4]
 80020fe:	2200      	movs	r2, #0
 8002100:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 8002104:	2300      	movs	r3, #0
 8002106:	e000      	b.n	800210a <HAL_I2CEx_ConfigAnalogFilter+0x8a>
  }
  else
  {
    return HAL_BUSY;
 8002108:	2302      	movs	r3, #2
  }
}
 800210a:	4618      	mov	r0, r3
 800210c:	370c      	adds	r7, #12
 800210e:	46bd      	mov	sp, r7
 8002110:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002114:	4770      	bx	lr

08002116 <HAL_I2CEx_ConfigDigitalFilter>:
  *                the configuration information for the specified I2Cx peripheral.
  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
 8002116:	b480      	push	{r7}
 8002118:	b085      	sub	sp, #20
 800211a:	af00      	add	r7, sp, #0
 800211c:	6078      	str	r0, [r7, #4]
 800211e:	6039      	str	r1, [r7, #0]

  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));

  if (hi2c->State == HAL_I2C_STATE_READY)
 8002120:	687b      	ldr	r3, [r7, #4]
 8002122:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 8002126:	b2db      	uxtb	r3, r3
 8002128:	2b20      	cmp	r3, #32
 800212a:	d139      	bne.n	80021a0 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 800212c:	687b      	ldr	r3, [r7, #4]
 800212e:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 8002132:	2b01      	cmp	r3, #1
 8002134:	d101      	bne.n	800213a <HAL_I2CEx_ConfigDigitalFilter+0x24>
 8002136:	2302      	movs	r3, #2
 8002138:	e033      	b.n	80021a2 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
 800213a:	687b      	ldr	r3, [r7, #4]
 800213c:	2201      	movs	r2, #1
 800213e:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    hi2c->State = HAL_I2C_STATE_BUSY;
 8002142:	687b      	ldr	r3, [r7, #4]
 8002144:	2224      	movs	r2, #36	@ 0x24
 8002146:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Disable the selected I2C peripheral */
    __HAL_I2C_DISABLE(hi2c);
 800214a:	687b      	ldr	r3, [r7, #4]
 800214c:	681b      	ldr	r3, [r3, #0]
 800214e:	681a      	ldr	r2, [r3, #0]
 8002150:	687b      	ldr	r3, [r7, #4]
 8002152:	681b      	ldr	r3, [r3, #0]
 8002154:	f022 0201 	bic.w	r2, r2, #1
 8002158:	601a      	str	r2, [r3, #0]

    /* Get the old register value */
    tmpreg = hi2c->Instance->CR1;
 800215a:	687b      	ldr	r3, [r7, #4]
 800215c:	681b      	ldr	r3, [r3, #0]
 800215e:	681b      	ldr	r3, [r3, #0]
 8002160:	60fb      	str	r3, [r7, #12]

    /* Reset I2Cx DNF bits [11:8] */
    tmpreg &= ~(I2C_CR1_DNF);
 8002162:	68fb      	ldr	r3, [r7, #12]
 8002164:	f423 6370 	bic.w	r3, r3, #3840	@ 0xf00
 8002168:	60fb      	str	r3, [r7, #12]

    /* Set I2Cx DNF coefficient */
    tmpreg |= DigitalFilter << 8U;
 800216a:	683b      	ldr	r3, [r7, #0]
 800216c:	021b      	lsls	r3, r3, #8
 800216e:	68fa      	ldr	r2, [r7, #12]
 8002170:	4313      	orrs	r3, r2
 8002172:	60fb      	str	r3, [r7, #12]

    /* Store the new register value */
    hi2c->Instance->CR1 = tmpreg;
 8002174:	687b      	ldr	r3, [r7, #4]
 8002176:	681b      	ldr	r3, [r3, #0]
 8002178:	68fa      	ldr	r2, [r7, #12]
 800217a:	601a      	str	r2, [r3, #0]

    __HAL_I2C_ENABLE(hi2c);
 800217c:	687b      	ldr	r3, [r7, #4]
 800217e:	681b      	ldr	r3, [r3, #0]
 8002180:	681a      	ldr	r2, [r3, #0]
 8002182:	687b      	ldr	r3, [r7, #4]
 8002184:	681b      	ldr	r3, [r3, #0]
 8002186:	f042 0201 	orr.w	r2, r2, #1
 800218a:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 800218c:	687b      	ldr	r3, [r7, #4]
 800218e:	2220      	movs	r2, #32
 8002190:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8002194:	687b      	ldr	r3, [r7, #4]
 8002196:	2200      	movs	r2, #0
 8002198:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 800219c:	2300      	movs	r3, #0
 800219e:	e000      	b.n	80021a2 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
  }
  else
  {
    return HAL_BUSY;
 80021a0:	2302      	movs	r3, #2
  }
}
 80021a2:	4618      	mov	r0, r3
 80021a4:	3714      	adds	r7, #20
 80021a6:	46bd      	mov	sp, r7
 80021a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80021ac:	4770      	bx	lr

080021ae <HAL_PCD_Init>:
  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
  * @param  hpcd PCD handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
 80021ae:	b580      	push	{r7, lr}
 80021b0:	b086      	sub	sp, #24
 80021b2:	af02      	add	r7, sp, #8
 80021b4:	6078      	str	r0, [r7, #4]
  uint8_t i;

  /* Check the PCD handle allocation */
  if (hpcd == NULL)
 80021b6:	687b      	ldr	r3, [r7, #4]
 80021b8:	2b00      	cmp	r3, #0
 80021ba:	d101      	bne.n	80021c0 <HAL_PCD_Init+0x12>
  {
    return HAL_ERROR;
 80021bc:	2301      	movs	r3, #1
 80021be:	e101      	b.n	80023c4 <HAL_PCD_Init+0x216>
  }

  /* Check the parameters */
  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));

  if (hpcd->State == HAL_PCD_STATE_RESET)
 80021c0:	687b      	ldr	r3, [r7, #4]
 80021c2:	f893 3495 	ldrb.w	r3, [r3, #1173]	@ 0x495
 80021c6:	b2db      	uxtb	r3, r3
 80021c8:	2b00      	cmp	r3, #0
 80021ca:	d106      	bne.n	80021da <HAL_PCD_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    hpcd->Lock = HAL_UNLOCKED;
 80021cc:	687b      	ldr	r3, [r7, #4]
 80021ce:	2200      	movs	r2, #0
 80021d0:	f883 2494 	strb.w	r2, [r3, #1172]	@ 0x494

    /* Init the low level hardware */
    hpcd->MspInitCallback(hpcd);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
    HAL_PCD_MspInit(hpcd);
 80021d4:	6878      	ldr	r0, [r7, #4]
 80021d6:	f7ff f86b 	bl	80012b0 <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
  }

  hpcd->State = HAL_PCD_STATE_BUSY;
 80021da:	687b      	ldr	r3, [r7, #4]
 80021dc:	2203      	movs	r2, #3
 80021de:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495

  /* Disable DMA mode for FS instance */
  hpcd->Init.dma_enable = 0U;
 80021e2:	687b      	ldr	r3, [r7, #4]
 80021e4:	2200      	movs	r2, #0
 80021e6:	719a      	strb	r2, [r3, #6]

  /* Disable the Interrupts */
  __HAL_PCD_DISABLE(hpcd);
 80021e8:	687b      	ldr	r3, [r7, #4]
 80021ea:	681b      	ldr	r3, [r3, #0]
 80021ec:	4618      	mov	r0, r3
 80021ee:	f003 fd54 	bl	8005c9a <USB_DisableGlobalInt>

  /*Init the Core (common init.) */
  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
 80021f2:	687b      	ldr	r3, [r7, #4]
 80021f4:	6818      	ldr	r0, [r3, #0]
 80021f6:	687b      	ldr	r3, [r7, #4]
 80021f8:	7c1a      	ldrb	r2, [r3, #16]
 80021fa:	f88d 2000 	strb.w	r2, [sp]
 80021fe:	3304      	adds	r3, #4
 8002200:	cb0e      	ldmia	r3, {r1, r2, r3}
 8002202:	f003 fd1d 	bl	8005c40 <USB_CoreInit>
 8002206:	4603      	mov	r3, r0
 8002208:	2b00      	cmp	r3, #0
 800220a:	d005      	beq.n	8002218 <HAL_PCD_Init+0x6a>
  {
    hpcd->State = HAL_PCD_STATE_ERROR;
 800220c:	687b      	ldr	r3, [r7, #4]
 800220e:	2202      	movs	r2, #2
 8002210:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495
    return HAL_ERROR;
 8002214:	2301      	movs	r3, #1
 8002216:	e0d5      	b.n	80023c4 <HAL_PCD_Init+0x216>
  }

  /* Force Device Mode */
  if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
 8002218:	687b      	ldr	r3, [r7, #4]
 800221a:	681b      	ldr	r3, [r3, #0]
 800221c:	2100      	movs	r1, #0
 800221e:	4618      	mov	r0, r3
 8002220:	f003 fd4c 	bl	8005cbc <USB_SetCurrentMode>
 8002224:	4603      	mov	r3, r0
 8002226:	2b00      	cmp	r3, #0
 8002228:	d005      	beq.n	8002236 <HAL_PCD_Init+0x88>
  {
    hpcd->State = HAL_PCD_STATE_ERROR;
 800222a:	687b      	ldr	r3, [r7, #4]
 800222c:	2202      	movs	r2, #2
 800222e:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495
    return HAL_ERROR;
 8002232:	2301      	movs	r3, #1
 8002234:	e0c6      	b.n	80023c4 <HAL_PCD_Init+0x216>
  }

  /* Init endpoints structures */
  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
 8002236:	2300      	movs	r3, #0
 8002238:	73fb      	strb	r3, [r7, #15]
 800223a:	e04a      	b.n	80022d2 <HAL_PCD_Init+0x124>
  {
    /* Init ep structure */
    hpcd->IN_ep[i].is_in = 1U;
 800223c:	7bfa      	ldrb	r2, [r7, #15]
 800223e:	6879      	ldr	r1, [r7, #4]
 8002240:	4613      	mov	r3, r2
 8002242:	00db      	lsls	r3, r3, #3
 8002244:	4413      	add	r3, r2
 8002246:	009b      	lsls	r3, r3, #2
 8002248:	440b      	add	r3, r1
 800224a:	3315      	adds	r3, #21
 800224c:	2201      	movs	r2, #1
 800224e:	701a      	strb	r2, [r3, #0]
    hpcd->IN_ep[i].num = i;
 8002250:	7bfa      	ldrb	r2, [r7, #15]
 8002252:	6879      	ldr	r1, [r7, #4]
 8002254:	4613      	mov	r3, r2
 8002256:	00db      	lsls	r3, r3, #3
 8002258:	4413      	add	r3, r2
 800225a:	009b      	lsls	r3, r3, #2
 800225c:	440b      	add	r3, r1
 800225e:	3314      	adds	r3, #20
 8002260:	7bfa      	ldrb	r2, [r7, #15]
 8002262:	701a      	strb	r2, [r3, #0]
#if defined (USB_OTG_FS)
    hpcd->IN_ep[i].tx_fifo_num = i;
 8002264:	7bfa      	ldrb	r2, [r7, #15]
 8002266:	7bfb      	ldrb	r3, [r7, #15]
 8002268:	b298      	uxth	r0, r3
 800226a:	6879      	ldr	r1, [r7, #4]
 800226c:	4613      	mov	r3, r2
 800226e:	00db      	lsls	r3, r3, #3
 8002270:	4413      	add	r3, r2
 8002272:	009b      	lsls	r3, r3, #2
 8002274:	440b      	add	r3, r1
 8002276:	332e      	adds	r3, #46	@ 0x2e
 8002278:	4602      	mov	r2, r0
 800227a:	801a      	strh	r2, [r3, #0]
#endif /* defined (USB_OTG_FS) */
    /* Control until ep is activated */
    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
 800227c:	7bfa      	ldrb	r2, [r7, #15]
 800227e:	6879      	ldr	r1, [r7, #4]
 8002280:	4613      	mov	r3, r2
 8002282:	00db      	lsls	r3, r3, #3
 8002284:	4413      	add	r3, r2
 8002286:	009b      	lsls	r3, r3, #2
 8002288:	440b      	add	r3, r1
 800228a:	3318      	adds	r3, #24
 800228c:	2200      	movs	r2, #0
 800228e:	701a      	strb	r2, [r3, #0]
    hpcd->IN_ep[i].maxpacket = 0U;
 8002290:	7bfa      	ldrb	r2, [r7, #15]
 8002292:	6879      	ldr	r1, [r7, #4]
 8002294:	4613      	mov	r3, r2
 8002296:	00db      	lsls	r3, r3, #3
 8002298:	4413      	add	r3, r2
 800229a:	009b      	lsls	r3, r3, #2
 800229c:	440b      	add	r3, r1
 800229e:	331c      	adds	r3, #28
 80022a0:	2200      	movs	r2, #0
 80022a2:	601a      	str	r2, [r3, #0]
    hpcd->IN_ep[i].xfer_buff = 0U;
 80022a4:	7bfa      	ldrb	r2, [r7, #15]
 80022a6:	6879      	ldr	r1, [r7, #4]
 80022a8:	4613      	mov	r3, r2
 80022aa:	00db      	lsls	r3, r3, #3
 80022ac:	4413      	add	r3, r2
 80022ae:	009b      	lsls	r3, r3, #2
 80022b0:	440b      	add	r3, r1
 80022b2:	3320      	adds	r3, #32
 80022b4:	2200      	movs	r2, #0
 80022b6:	601a      	str	r2, [r3, #0]
    hpcd->IN_ep[i].xfer_len = 0U;
 80022b8:	7bfa      	ldrb	r2, [r7, #15]
 80022ba:	6879      	ldr	r1, [r7, #4]
 80022bc:	4613      	mov	r3, r2
 80022be:	00db      	lsls	r3, r3, #3
 80022c0:	4413      	add	r3, r2
 80022c2:	009b      	lsls	r3, r3, #2
 80022c4:	440b      	add	r3, r1
 80022c6:	3324      	adds	r3, #36	@ 0x24
 80022c8:	2200      	movs	r2, #0
 80022ca:	601a      	str	r2, [r3, #0]
  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
 80022cc:	7bfb      	ldrb	r3, [r7, #15]
 80022ce:	3301      	adds	r3, #1
 80022d0:	73fb      	strb	r3, [r7, #15]
 80022d2:	687b      	ldr	r3, [r7, #4]
 80022d4:	791b      	ldrb	r3, [r3, #4]
 80022d6:	7bfa      	ldrb	r2, [r7, #15]
 80022d8:	429a      	cmp	r2, r3
 80022da:	d3af      	bcc.n	800223c <HAL_PCD_Init+0x8e>
  }

  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
 80022dc:	2300      	movs	r3, #0
 80022de:	73fb      	strb	r3, [r7, #15]
 80022e0:	e044      	b.n	800236c <HAL_PCD_Init+0x1be>
  {
    hpcd->OUT_ep[i].is_in = 0U;
 80022e2:	7bfa      	ldrb	r2, [r7, #15]
 80022e4:	6879      	ldr	r1, [r7, #4]
 80022e6:	4613      	mov	r3, r2
 80022e8:	00db      	lsls	r3, r3, #3
 80022ea:	4413      	add	r3, r2
 80022ec:	009b      	lsls	r3, r3, #2
 80022ee:	440b      	add	r3, r1
 80022f0:	f203 2355 	addw	r3, r3, #597	@ 0x255
 80022f4:	2200      	movs	r2, #0
 80022f6:	701a      	strb	r2, [r3, #0]
    hpcd->OUT_ep[i].num = i;
 80022f8:	7bfa      	ldrb	r2, [r7, #15]
 80022fa:	6879      	ldr	r1, [r7, #4]
 80022fc:	4613      	mov	r3, r2
 80022fe:	00db      	lsls	r3, r3, #3
 8002300:	4413      	add	r3, r2
 8002302:	009b      	lsls	r3, r3, #2
 8002304:	440b      	add	r3, r1
 8002306:	f503 7315 	add.w	r3, r3, #596	@ 0x254
 800230a:	7bfa      	ldrb	r2, [r7, #15]
 800230c:	701a      	strb	r2, [r3, #0]
    /* Control until ep is activated */
    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
 800230e:	7bfa      	ldrb	r2, [r7, #15]
 8002310:	6879      	ldr	r1, [r7, #4]
 8002312:	4613      	mov	r3, r2
 8002314:	00db      	lsls	r3, r3, #3
 8002316:	4413      	add	r3, r2
 8002318:	009b      	lsls	r3, r3, #2
 800231a:	440b      	add	r3, r1
 800231c:	f503 7316 	add.w	r3, r3, #600	@ 0x258
 8002320:	2200      	movs	r2, #0
 8002322:	701a      	strb	r2, [r3, #0]
    hpcd->OUT_ep[i].maxpacket = 0U;
 8002324:	7bfa      	ldrb	r2, [r7, #15]
 8002326:	6879      	ldr	r1, [r7, #4]
 8002328:	4613      	mov	r3, r2
 800232a:	00db      	lsls	r3, r3, #3
 800232c:	4413      	add	r3, r2
 800232e:	009b      	lsls	r3, r3, #2
 8002330:	440b      	add	r3, r1
 8002332:	f503 7317 	add.w	r3, r3, #604	@ 0x25c
 8002336:	2200      	movs	r2, #0
 8002338:	601a      	str	r2, [r3, #0]
    hpcd->OUT_ep[i].xfer_buff = 0U;
 800233a:	7bfa      	ldrb	r2, [r7, #15]
 800233c:	6879      	ldr	r1, [r7, #4]
 800233e:	4613      	mov	r3, r2
 8002340:	00db      	lsls	r3, r3, #3
 8002342:	4413      	add	r3, r2
 8002344:	009b      	lsls	r3, r3, #2
 8002346:	440b      	add	r3, r1
 8002348:	f503 7318 	add.w	r3, r3, #608	@ 0x260
 800234c:	2200      	movs	r2, #0
 800234e:	601a      	str	r2, [r3, #0]
    hpcd->OUT_ep[i].xfer_len = 0U;
 8002350:	7bfa      	ldrb	r2, [r7, #15]
 8002352:	6879      	ldr	r1, [r7, #4]
 8002354:	4613      	mov	r3, r2
 8002356:	00db      	lsls	r3, r3, #3
 8002358:	4413      	add	r3, r2
 800235a:	009b      	lsls	r3, r3, #2
 800235c:	440b      	add	r3, r1
 800235e:	f503 7319 	add.w	r3, r3, #612	@ 0x264
 8002362:	2200      	movs	r2, #0
 8002364:	601a      	str	r2, [r3, #0]
  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
 8002366:	7bfb      	ldrb	r3, [r7, #15]
 8002368:	3301      	adds	r3, #1
 800236a:	73fb      	strb	r3, [r7, #15]
 800236c:	687b      	ldr	r3, [r7, #4]
 800236e:	791b      	ldrb	r3, [r3, #4]
 8002370:	7bfa      	ldrb	r2, [r7, #15]
 8002372:	429a      	cmp	r2, r3
 8002374:	d3b5      	bcc.n	80022e2 <HAL_PCD_Init+0x134>
  }

  /* Init Device */
  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
 8002376:	687b      	ldr	r3, [r7, #4]
 8002378:	6818      	ldr	r0, [r3, #0]
 800237a:	687b      	ldr	r3, [r7, #4]
 800237c:	7c1a      	ldrb	r2, [r3, #16]
 800237e:	f88d 2000 	strb.w	r2, [sp]
 8002382:	3304      	adds	r3, #4
 8002384:	cb0e      	ldmia	r3, {r1, r2, r3}
 8002386:	f003 fce5 	bl	8005d54 <USB_DevInit>
 800238a:	4603      	mov	r3, r0
 800238c:	2b00      	cmp	r3, #0
 800238e:	d005      	beq.n	800239c <HAL_PCD_Init+0x1ee>
  {
    hpcd->State = HAL_PCD_STATE_ERROR;
 8002390:	687b      	ldr	r3, [r7, #4]
 8002392:	2202      	movs	r2, #2
 8002394:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495
    return HAL_ERROR;
 8002398:	2301      	movs	r3, #1
 800239a:	e013      	b.n	80023c4 <HAL_PCD_Init+0x216>
  }

  hpcd->USB_Address = 0U;
 800239c:	687b      	ldr	r3, [r7, #4]
 800239e:	2200      	movs	r2, #0
 80023a0:	745a      	strb	r2, [r3, #17]
  hpcd->State = HAL_PCD_STATE_READY;
 80023a2:	687b      	ldr	r3, [r7, #4]
 80023a4:	2201      	movs	r2, #1
 80023a6:	f883 2495 	strb.w	r2, [r3, #1173]	@ 0x495

  /* Activate LPM */
  if (hpcd->Init.lpm_enable == 1U)
 80023aa:	687b      	ldr	r3, [r7, #4]
 80023ac:	7b1b      	ldrb	r3, [r3, #12]
 80023ae:	2b01      	cmp	r3, #1
 80023b0:	d102      	bne.n	80023b8 <HAL_PCD_Init+0x20a>
  {
    (void)HAL_PCDEx_ActivateLPM(hpcd);
 80023b2:	6878      	ldr	r0, [r7, #4]
 80023b4:	f000 f80a 	bl	80023cc <HAL_PCDEx_ActivateLPM>
  }

  (void)USB_DevDisconnect(hpcd->Instance);
 80023b8:	687b      	ldr	r3, [r7, #4]
 80023ba:	681b      	ldr	r3, [r3, #0]
 80023bc:	4618      	mov	r0, r3
 80023be:	f003 fe8a 	bl	80060d6 <USB_DevDisconnect>

  return HAL_OK;
 80023c2:	2300      	movs	r3, #0
}
 80023c4:	4618      	mov	r0, r3
 80023c6:	3710      	adds	r7, #16
 80023c8:	46bd      	mov	sp, r7
 80023ca:	bd80      	pop	{r7, pc}

080023cc <HAL_PCDEx_ActivateLPM>:
  * @brief  Activate LPM feature.
  * @param  hpcd PCD handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
 80023cc:	b480      	push	{r7}
 80023ce:	b085      	sub	sp, #20
 80023d0:	af00      	add	r7, sp, #0
 80023d2:	6078      	str	r0, [r7, #4]
  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
 80023d4:	687b      	ldr	r3, [r7, #4]
 80023d6:	681b      	ldr	r3, [r3, #0]
 80023d8:	60fb      	str	r3, [r7, #12]

  hpcd->lpm_active = 1U;
 80023da:	687b      	ldr	r3, [r7, #4]
 80023dc:	2201      	movs	r2, #1
 80023de:	f8c3 24d8 	str.w	r2, [r3, #1240]	@ 0x4d8
  hpcd->LPM_State = LPM_L0;
 80023e2:	687b      	ldr	r3, [r7, #4]
 80023e4:	2200      	movs	r2, #0
 80023e6:	f883 24cc 	strb.w	r2, [r3, #1228]	@ 0x4cc
  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
 80023ea:	68fb      	ldr	r3, [r7, #12]
 80023ec:	699b      	ldr	r3, [r3, #24]
 80023ee:	f043 6200 	orr.w	r2, r3, #134217728	@ 0x8000000
 80023f2:	68fb      	ldr	r3, [r7, #12]
 80023f4:	619a      	str	r2, [r3, #24]
  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
 80023f6:	68fb      	ldr	r3, [r7, #12]
 80023f8:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80023fa:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 80023fe:	f043 0303 	orr.w	r3, r3, #3
 8002402:	68fa      	ldr	r2, [r7, #12]
 8002404:	6553      	str	r3, [r2, #84]	@ 0x54

  return HAL_OK;
 8002406:	2300      	movs	r3, #0
}
 8002408:	4618      	mov	r0, r3
 800240a:	3714      	adds	r7, #20
 800240c:	46bd      	mov	sp, r7
 800240e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002412:	4770      	bx	lr

08002414 <HAL_PWR_EnableBkUpAccess>:
  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
  *        back-up domain.
  * @retval None
  */
void HAL_PWR_EnableBkUpAccess(void)
{
 8002414:	b480      	push	{r7}
 8002416:	af00      	add	r7, sp, #0
  SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8002418:	4b05      	ldr	r3, [pc, #20]	@ (8002430 <HAL_PWR_EnableBkUpAccess+0x1c>)
 800241a:	681b      	ldr	r3, [r3, #0]
 800241c:	4a04      	ldr	r2, [pc, #16]	@ (8002430 <HAL_PWR_EnableBkUpAccess+0x1c>)
 800241e:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8002422:	6013      	str	r3, [r2, #0]
}
 8002424:	bf00      	nop
 8002426:	46bd      	mov	sp, r7
 8002428:	f85d 7b04 	ldr.w	r7, [sp], #4
 800242c:	4770      	bx	lr
 800242e:	bf00      	nop
 8002430:	40007000 	.word	0x40007000

08002434 <HAL_PWREx_GetVoltageRange>:
  * @brief Return Voltage Scaling Range.
  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
  *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
  */
uint32_t HAL_PWREx_GetVoltageRange(void)
{
 8002434:	b480      	push	{r7}
 8002436:	af00      	add	r7, sp, #0
    else
    {
      return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
    }
#else
  return  (PWR->CR1 & PWR_CR1_VOS);
 8002438:	4b04      	ldr	r3, [pc, #16]	@ (800244c <HAL_PWREx_GetVoltageRange+0x18>)
 800243a:	681b      	ldr	r3, [r3, #0]
 800243c:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
#endif
}
 8002440:	4618      	mov	r0, r3
 8002442:	46bd      	mov	sp, r7
 8002444:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002448:	4770      	bx	lr
 800244a:	bf00      	nop
 800244c:	40007000 	.word	0x40007000

08002450 <HAL_PWREx_ControlVoltageScaling>:
  *        cleared before returning the status. If the flag is not cleared within
  *        50 microseconds, HAL_TIMEOUT status is reported.
  * @retval HAL Status
  */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
 8002450:	b480      	push	{r7}
 8002452:	b085      	sub	sp, #20
 8002454:	af00      	add	r7, sp, #0
 8002456:	6078      	str	r0, [r7, #4]
  }

#else

  /* If Set Range 1 */
  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
 8002458:	687b      	ldr	r3, [r7, #4]
 800245a:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800245e:	d130      	bne.n	80024c2 <HAL_PWREx_ControlVoltageScaling+0x72>
  {
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
 8002460:	4b23      	ldr	r3, [pc, #140]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8002462:	681b      	ldr	r3, [r3, #0]
 8002464:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
 8002468:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800246c:	d038      	beq.n	80024e0 <HAL_PWREx_ControlVoltageScaling+0x90>
    {
      /* Set Range 1 */
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 800246e:	4b20      	ldr	r3, [pc, #128]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8002470:	681b      	ldr	r3, [r3, #0]
 8002472:	f423 63c0 	bic.w	r3, r3, #1536	@ 0x600
 8002476:	4a1e      	ldr	r2, [pc, #120]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8002478:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
 800247c:	6013      	str	r3, [r2, #0]

      /* Wait until VOSF is cleared */
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 800247e:	4b1d      	ldr	r3, [pc, #116]	@ (80024f4 <HAL_PWREx_ControlVoltageScaling+0xa4>)
 8002480:	681b      	ldr	r3, [r3, #0]
 8002482:	2232      	movs	r2, #50	@ 0x32
 8002484:	fb02 f303 	mul.w	r3, r2, r3
 8002488:	4a1b      	ldr	r2, [pc, #108]	@ (80024f8 <HAL_PWREx_ControlVoltageScaling+0xa8>)
 800248a:	fba2 2303 	umull	r2, r3, r2, r3
 800248e:	0c9b      	lsrs	r3, r3, #18
 8002490:	3301      	adds	r3, #1
 8002492:	60fb      	str	r3, [r7, #12]
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 8002494:	e002      	b.n	800249c <HAL_PWREx_ControlVoltageScaling+0x4c>
      {
        wait_loop_index--;
 8002496:	68fb      	ldr	r3, [r7, #12]
 8002498:	3b01      	subs	r3, #1
 800249a:	60fb      	str	r3, [r7, #12]
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 800249c:	4b14      	ldr	r3, [pc, #80]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 800249e:	695b      	ldr	r3, [r3, #20]
 80024a0:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80024a4:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 80024a8:	d102      	bne.n	80024b0 <HAL_PWREx_ControlVoltageScaling+0x60>
 80024aa:	68fb      	ldr	r3, [r7, #12]
 80024ac:	2b00      	cmp	r3, #0
 80024ae:	d1f2      	bne.n	8002496 <HAL_PWREx_ControlVoltageScaling+0x46>
      }
      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
 80024b0:	4b0f      	ldr	r3, [pc, #60]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80024b2:	695b      	ldr	r3, [r3, #20]
 80024b4:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80024b8:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 80024bc:	d110      	bne.n	80024e0 <HAL_PWREx_ControlVoltageScaling+0x90>
      {
        return HAL_TIMEOUT;
 80024be:	2303      	movs	r3, #3
 80024c0:	e00f      	b.n	80024e2 <HAL_PWREx_ControlVoltageScaling+0x92>
      }
    }
  }
  else
  {
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
 80024c2:	4b0b      	ldr	r3, [pc, #44]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80024c4:	681b      	ldr	r3, [r3, #0]
 80024c6:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
 80024ca:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 80024ce:	d007      	beq.n	80024e0 <HAL_PWREx_ControlVoltageScaling+0x90>
    {
      /* Set Range 2 */
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
 80024d0:	4b07      	ldr	r3, [pc, #28]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80024d2:	681b      	ldr	r3, [r3, #0]
 80024d4:	f423 63c0 	bic.w	r3, r3, #1536	@ 0x600
 80024d8:	4a05      	ldr	r2, [pc, #20]	@ (80024f0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80024da:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
 80024de:	6013      	str	r3, [r2, #0]
      /* No need to wait for VOSF to be cleared for this transition */
    }
  }
#endif

  return HAL_OK;
 80024e0:	2300      	movs	r3, #0
}
 80024e2:	4618      	mov	r0, r3
 80024e4:	3714      	adds	r7, #20
 80024e6:	46bd      	mov	sp, r7
 80024e8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80024ec:	4770      	bx	lr
 80024ee:	bf00      	nop
 80024f0:	40007000 	.word	0x40007000
 80024f4:	20000000 	.word	0x20000000
 80024f8:	431bde83 	.word	0x431bde83

080024fc <HAL_PWREx_EnableVddUSB>:
  * @brief Enable VDDUSB supply.
  * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
  * @retval None
  */
void HAL_PWREx_EnableVddUSB(void)
{
 80024fc:	b480      	push	{r7}
 80024fe:	af00      	add	r7, sp, #0
  SET_BIT(PWR->CR2, PWR_CR2_USV);
 8002500:	4b05      	ldr	r3, [pc, #20]	@ (8002518 <HAL_PWREx_EnableVddUSB+0x1c>)
 8002502:	685b      	ldr	r3, [r3, #4]
 8002504:	4a04      	ldr	r2, [pc, #16]	@ (8002518 <HAL_PWREx_EnableVddUSB+0x1c>)
 8002506:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
 800250a:	6053      	str	r3, [r2, #4]
}
 800250c:	bf00      	nop
 800250e:	46bd      	mov	sp, r7
 8002510:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002514:	4770      	bx	lr
 8002516:	bf00      	nop
 8002518:	40007000 	.word	0x40007000

0800251c <HAL_QSPI_Init>:
  *        in the QSPI_InitTypeDef and initialize the associated handle.
  * @param hqspi QSPI handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
{
 800251c:	b580      	push	{r7, lr}
 800251e:	b086      	sub	sp, #24
 8002520:	af02      	add	r7, sp, #8
 8002522:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status;
  uint32_t tickstart = HAL_GetTick();
 8002524:	f7ff f88e 	bl	8001644 <HAL_GetTick>
 8002528:	60f8      	str	r0, [r7, #12]

  /* Check the QSPI handle allocation */
  if(hqspi == NULL)
 800252a:	687b      	ldr	r3, [r7, #4]
 800252c:	2b00      	cmp	r3, #0
 800252e:	d101      	bne.n	8002534 <HAL_QSPI_Init+0x18>
  {
    return HAL_ERROR;
 8002530:	2301      	movs	r3, #1
 8002532:	e063      	b.n	80025fc <HAL_QSPI_Init+0xe0>
  {
    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
  }
#endif

  if(hqspi->State == HAL_QSPI_STATE_RESET)
 8002534:	687b      	ldr	r3, [r7, #4]
 8002536:	f893 3039 	ldrb.w	r3, [r3, #57]	@ 0x39
 800253a:	b2db      	uxtb	r3, r3
 800253c:	2b00      	cmp	r3, #0
 800253e:	d10b      	bne.n	8002558 <HAL_QSPI_Init+0x3c>
  {
    /* Allocate lock resource and initialize it */
    hqspi->Lock = HAL_UNLOCKED;
 8002540:	687b      	ldr	r3, [r7, #4]
 8002542:	2200      	movs	r2, #0
 8002544:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38

    /* Init the low level hardware */
    hqspi->MspInitCallback(hqspi);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_QSPI_MspInit(hqspi);
 8002548:	6878      	ldr	r0, [r7, #4]
 800254a:	f7fe fd7d 	bl	8001048 <HAL_QSPI_MspInit>
#endif

    /* Configure the default timeout for the QSPI memory access */
    HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
 800254e:	f241 3188 	movw	r1, #5000	@ 0x1388
 8002552:	6878      	ldr	r0, [r7, #4]
 8002554:	f000 f858 	bl	8002608 <HAL_QSPI_SetTimeout>
  }

  /* Configure QSPI FIFO Threshold */
  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
 8002558:	687b      	ldr	r3, [r7, #4]
 800255a:	681b      	ldr	r3, [r3, #0]
 800255c:	681b      	ldr	r3, [r3, #0]
 800255e:	f423 6170 	bic.w	r1, r3, #3840	@ 0xf00
 8002562:	687b      	ldr	r3, [r7, #4]
 8002564:	689b      	ldr	r3, [r3, #8]
 8002566:	3b01      	subs	r3, #1
 8002568:	021a      	lsls	r2, r3, #8
 800256a:	687b      	ldr	r3, [r7, #4]
 800256c:	681b      	ldr	r3, [r3, #0]
 800256e:	430a      	orrs	r2, r1
 8002570:	601a      	str	r2, [r3, #0]
             ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));

  /* Wait till BUSY flag reset */
  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
 8002572:	687b      	ldr	r3, [r7, #4]
 8002574:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8002576:	9300      	str	r3, [sp, #0]
 8002578:	68fb      	ldr	r3, [r7, #12]
 800257a:	2200      	movs	r2, #0
 800257c:	2120      	movs	r1, #32
 800257e:	6878      	ldr	r0, [r7, #4]
 8002580:	f000 f850 	bl	8002624 <QSPI_WaitFlagStateUntilTimeout>
 8002584:	4603      	mov	r3, r0
 8002586:	72fb      	strb	r3, [r7, #11]

  if(status == HAL_OK)
 8002588:	7afb      	ldrb	r3, [r7, #11]
 800258a:	2b00      	cmp	r3, #0
 800258c:	d131      	bne.n	80025f2 <HAL_QSPI_Init+0xd6>
#if defined(QUADSPI_CR_DFM)
    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
#else
    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
 800258e:	687b      	ldr	r3, [r7, #4]
 8002590:	681b      	ldr	r3, [r3, #0]
 8002592:	681b      	ldr	r3, [r3, #0]
 8002594:	f023 437f 	bic.w	r3, r3, #4278190080	@ 0xff000000
 8002598:	f023 0310 	bic.w	r3, r3, #16
 800259c:	687a      	ldr	r2, [r7, #4]
 800259e:	6852      	ldr	r2, [r2, #4]
 80025a0:	0611      	lsls	r1, r2, #24
 80025a2:	687a      	ldr	r2, [r7, #4]
 80025a4:	68d2      	ldr	r2, [r2, #12]
 80025a6:	4311      	orrs	r1, r2
 80025a8:	687a      	ldr	r2, [r7, #4]
 80025aa:	6812      	ldr	r2, [r2, #0]
 80025ac:	430b      	orrs	r3, r1
 80025ae:	6013      	str	r3, [r2, #0]
               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
                hqspi->Init.SampleShifting));
#endif

    /* Configure QSPI Flash Size, CS High Time and Clock Mode */
    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
 80025b0:	687b      	ldr	r3, [r7, #4]
 80025b2:	681b      	ldr	r3, [r3, #0]
 80025b4:	685a      	ldr	r2, [r3, #4]
 80025b6:	4b13      	ldr	r3, [pc, #76]	@ (8002604 <HAL_QSPI_Init+0xe8>)
 80025b8:	4013      	ands	r3, r2
 80025ba:	687a      	ldr	r2, [r7, #4]
 80025bc:	6912      	ldr	r2, [r2, #16]
 80025be:	0411      	lsls	r1, r2, #16
 80025c0:	687a      	ldr	r2, [r7, #4]
 80025c2:	6952      	ldr	r2, [r2, #20]
 80025c4:	4311      	orrs	r1, r2
 80025c6:	687a      	ldr	r2, [r7, #4]
 80025c8:	6992      	ldr	r2, [r2, #24]
 80025ca:	4311      	orrs	r1, r2
 80025cc:	687a      	ldr	r2, [r7, #4]
 80025ce:	6812      	ldr	r2, [r2, #0]
 80025d0:	430b      	orrs	r3, r1
 80025d2:	6053      	str	r3, [r2, #4]
               ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));

    /* Enable the QSPI peripheral */
    __HAL_QSPI_ENABLE(hqspi);
 80025d4:	687b      	ldr	r3, [r7, #4]
 80025d6:	681b      	ldr	r3, [r3, #0]
 80025d8:	681a      	ldr	r2, [r3, #0]
 80025da:	687b      	ldr	r3, [r7, #4]
 80025dc:	681b      	ldr	r3, [r3, #0]
 80025de:	f042 0201 	orr.w	r2, r2, #1
 80025e2:	601a      	str	r2, [r3, #0]

    /* Set QSPI error code to none */
    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
 80025e4:	687b      	ldr	r3, [r7, #4]
 80025e6:	2200      	movs	r2, #0
 80025e8:	63da      	str	r2, [r3, #60]	@ 0x3c

    /* Initialize the QSPI state */
    hqspi->State = HAL_QSPI_STATE_READY;
 80025ea:	687b      	ldr	r3, [r7, #4]
 80025ec:	2201      	movs	r2, #1
 80025ee:	f883 2039 	strb.w	r2, [r3, #57]	@ 0x39
  }

  /* Release Lock */
  __HAL_UNLOCK(hqspi);
 80025f2:	687b      	ldr	r3, [r7, #4]
 80025f4:	2200      	movs	r2, #0
 80025f6:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38

  /* Return function status */
  return status;
 80025fa:	7afb      	ldrb	r3, [r7, #11]
}
 80025fc:	4618      	mov	r0, r3
 80025fe:	3710      	adds	r7, #16
 8002600:	46bd      	mov	sp, r7
 8002602:	bd80      	pop	{r7, pc}
 8002604:	ffe0f8fe 	.word	0xffe0f8fe

08002608 <HAL_QSPI_SetTimeout>:
  * @param  hqspi QSPI handle.
  * @param  Timeout Timeout for the QSPI memory access.
  * @retval None
  */
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
{
 8002608:	b480      	push	{r7}
 800260a:	b083      	sub	sp, #12
 800260c:	af00      	add	r7, sp, #0
 800260e:	6078      	str	r0, [r7, #4]
 8002610:	6039      	str	r1, [r7, #0]
  hqspi->Timeout = Timeout;
 8002612:	687b      	ldr	r3, [r7, #4]
 8002614:	683a      	ldr	r2, [r7, #0]
 8002616:	641a      	str	r2, [r3, #64]	@ 0x40
}
 8002618:	bf00      	nop
 800261a:	370c      	adds	r7, #12
 800261c:	46bd      	mov	sp, r7
 800261e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002622:	4770      	bx	lr

08002624 <QSPI_WaitFlagStateUntilTimeout>:
  * @param  Timeout Duration of the timeout
  * @retval HAL status
  */
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
 8002624:	b580      	push	{r7, lr}
 8002626:	b084      	sub	sp, #16
 8002628:	af00      	add	r7, sp, #0
 800262a:	60f8      	str	r0, [r7, #12]
 800262c:	60b9      	str	r1, [r7, #8]
 800262e:	603b      	str	r3, [r7, #0]
 8002630:	4613      	mov	r3, r2
 8002632:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is in expected state */
  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
 8002634:	e01a      	b.n	800266c <QSPI_WaitFlagStateUntilTimeout+0x48>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8002636:	69bb      	ldr	r3, [r7, #24]
 8002638:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 800263c:	d016      	beq.n	800266c <QSPI_WaitFlagStateUntilTimeout+0x48>
    {
      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 800263e:	f7ff f801 	bl	8001644 <HAL_GetTick>
 8002642:	4602      	mov	r2, r0
 8002644:	683b      	ldr	r3, [r7, #0]
 8002646:	1ad3      	subs	r3, r2, r3
 8002648:	69ba      	ldr	r2, [r7, #24]
 800264a:	429a      	cmp	r2, r3
 800264c:	d302      	bcc.n	8002654 <QSPI_WaitFlagStateUntilTimeout+0x30>
 800264e:	69bb      	ldr	r3, [r7, #24]
 8002650:	2b00      	cmp	r3, #0
 8002652:	d10b      	bne.n	800266c <QSPI_WaitFlagStateUntilTimeout+0x48>
      {
        hqspi->State     = HAL_QSPI_STATE_ERROR;
 8002654:	68fb      	ldr	r3, [r7, #12]
 8002656:	2204      	movs	r2, #4
 8002658:	f883 2039 	strb.w	r2, [r3, #57]	@ 0x39
        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
 800265c:	68fb      	ldr	r3, [r7, #12]
 800265e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8002660:	f043 0201 	orr.w	r2, r3, #1
 8002664:	68fb      	ldr	r3, [r7, #12]
 8002666:	63da      	str	r2, [r3, #60]	@ 0x3c

        return HAL_ERROR;
 8002668:	2301      	movs	r3, #1
 800266a:	e00e      	b.n	800268a <QSPI_WaitFlagStateUntilTimeout+0x66>
  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
 800266c:	68fb      	ldr	r3, [r7, #12]
 800266e:	681b      	ldr	r3, [r3, #0]
 8002670:	689a      	ldr	r2, [r3, #8]
 8002672:	68bb      	ldr	r3, [r7, #8]
 8002674:	4013      	ands	r3, r2
 8002676:	2b00      	cmp	r3, #0
 8002678:	bf14      	ite	ne
 800267a:	2301      	movne	r3, #1
 800267c:	2300      	moveq	r3, #0
 800267e:	b2db      	uxtb	r3, r3
 8002680:	461a      	mov	r2, r3
 8002682:	79fb      	ldrb	r3, [r7, #7]
 8002684:	429a      	cmp	r2, r3
 8002686:	d1d6      	bne.n	8002636 <QSPI_WaitFlagStateUntilTimeout+0x12>
      }
    }
  }
  return HAL_OK;
 8002688:	2300      	movs	r3, #0
}
 800268a:	4618      	mov	r0, r3
 800268c:	3710      	adds	r7, #16
 800268e:	46bd      	mov	sp, r7
 8002690:	bd80      	pop	{r7, pc}
	...

08002694 <HAL_RCC_OscConfig>:
  * @note   If HSE failed to start, HSE should be disabled before recalling
            HAL_RCC_OscConfig().
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8002694:	b580      	push	{r7, lr}
 8002696:	b088      	sub	sp, #32
 8002698:	af00      	add	r7, sp, #0
 800269a:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  HAL_StatusTypeDef status;
  uint32_t sysclk_source, pll_config;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 800269c:	687b      	ldr	r3, [r7, #4]
 800269e:	2b00      	cmp	r3, #0
 80026a0:	d101      	bne.n	80026a6 <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 80026a2:	2301      	movs	r3, #1
 80026a4:	e3ca      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 80026a6:	4b97      	ldr	r3, [pc, #604]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80026a8:	689b      	ldr	r3, [r3, #8]
 80026aa:	f003 030c 	and.w	r3, r3, #12
 80026ae:	61bb      	str	r3, [r7, #24]
  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
 80026b0:	4b94      	ldr	r3, [pc, #592]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80026b2:	68db      	ldr	r3, [r3, #12]
 80026b4:	f003 0303 	and.w	r3, r3, #3
 80026b8:	617b      	str	r3, [r7, #20]

  /*----------------------------- MSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
 80026ba:	687b      	ldr	r3, [r7, #4]
 80026bc:	681b      	ldr	r3, [r3, #0]
 80026be:	f003 0310 	and.w	r3, r3, #16
 80026c2:	2b00      	cmp	r3, #0
 80026c4:	f000 80e4 	beq.w	8002890 <HAL_RCC_OscConfig+0x1fc>
    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
    assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
    assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

    /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_CFGR_SWS_MSI) ||
 80026c8:	69bb      	ldr	r3, [r7, #24]
 80026ca:	2b00      	cmp	r3, #0
 80026cc:	d007      	beq.n	80026de <HAL_RCC_OscConfig+0x4a>
 80026ce:	69bb      	ldr	r3, [r7, #24]
 80026d0:	2b0c      	cmp	r3, #12
 80026d2:	f040 808b 	bne.w	80027ec <HAL_RCC_OscConfig+0x158>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
 80026d6:	697b      	ldr	r3, [r7, #20]
 80026d8:	2b01      	cmp	r3, #1
 80026da:	f040 8087 	bne.w	80027ec <HAL_RCC_OscConfig+0x158>
    {
      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 80026de:	4b89      	ldr	r3, [pc, #548]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80026e0:	681b      	ldr	r3, [r3, #0]
 80026e2:	f003 0302 	and.w	r3, r3, #2
 80026e6:	2b00      	cmp	r3, #0
 80026e8:	d005      	beq.n	80026f6 <HAL_RCC_OscConfig+0x62>
 80026ea:	687b      	ldr	r3, [r7, #4]
 80026ec:	699b      	ldr	r3, [r3, #24]
 80026ee:	2b00      	cmp	r3, #0
 80026f0:	d101      	bne.n	80026f6 <HAL_RCC_OscConfig+0x62>
      {
        return HAL_ERROR;
 80026f2:	2301      	movs	r3, #1
 80026f4:	e3a2      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      else
      {
        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
           must be correctly programmed according to the frequency of the CPU clock
           (HCLK) and the supply voltage of the device. */
        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
 80026f6:	687b      	ldr	r3, [r7, #4]
 80026f8:	6a1a      	ldr	r2, [r3, #32]
 80026fa:	4b82      	ldr	r3, [pc, #520]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80026fc:	681b      	ldr	r3, [r3, #0]
 80026fe:	f003 0308 	and.w	r3, r3, #8
 8002702:	2b00      	cmp	r3, #0
 8002704:	d004      	beq.n	8002710 <HAL_RCC_OscConfig+0x7c>
 8002706:	4b7f      	ldr	r3, [pc, #508]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002708:	681b      	ldr	r3, [r3, #0]
 800270a:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 800270e:	e005      	b.n	800271c <HAL_RCC_OscConfig+0x88>
 8002710:	4b7c      	ldr	r3, [pc, #496]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002712:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002716:	091b      	lsrs	r3, r3, #4
 8002718:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 800271c:	4293      	cmp	r3, r2
 800271e:	d223      	bcs.n	8002768 <HAL_RCC_OscConfig+0xd4>
        {
          /* First increase number of wait states update if necessary */
          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 8002720:	687b      	ldr	r3, [r7, #4]
 8002722:	6a1b      	ldr	r3, [r3, #32]
 8002724:	4618      	mov	r0, r3
 8002726:	f000 fd87 	bl	8003238 <RCC_SetFlashLatencyFromMSIRange>
 800272a:	4603      	mov	r3, r0
 800272c:	2b00      	cmp	r3, #0
 800272e:	d001      	beq.n	8002734 <HAL_RCC_OscConfig+0xa0>
          {
            return HAL_ERROR;
 8002730:	2301      	movs	r3, #1
 8002732:	e383      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
          }

          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8002734:	4b73      	ldr	r3, [pc, #460]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002736:	681b      	ldr	r3, [r3, #0]
 8002738:	4a72      	ldr	r2, [pc, #456]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800273a:	f043 0308 	orr.w	r3, r3, #8
 800273e:	6013      	str	r3, [r2, #0]
 8002740:	4b70      	ldr	r3, [pc, #448]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002742:	681b      	ldr	r3, [r3, #0]
 8002744:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8002748:	687b      	ldr	r3, [r7, #4]
 800274a:	6a1b      	ldr	r3, [r3, #32]
 800274c:	496d      	ldr	r1, [pc, #436]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800274e:	4313      	orrs	r3, r2
 8002750:	600b      	str	r3, [r1, #0]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8002752:	4b6c      	ldr	r3, [pc, #432]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002754:	685b      	ldr	r3, [r3, #4]
 8002756:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 800275a:	687b      	ldr	r3, [r7, #4]
 800275c:	69db      	ldr	r3, [r3, #28]
 800275e:	021b      	lsls	r3, r3, #8
 8002760:	4968      	ldr	r1, [pc, #416]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002762:	4313      	orrs	r3, r2
 8002764:	604b      	str	r3, [r1, #4]
 8002766:	e025      	b.n	80027b4 <HAL_RCC_OscConfig+0x120>
        }
        else
        {
          /* Else, keep current flash latency while decreasing applies */
          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8002768:	4b66      	ldr	r3, [pc, #408]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800276a:	681b      	ldr	r3, [r3, #0]
 800276c:	4a65      	ldr	r2, [pc, #404]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800276e:	f043 0308 	orr.w	r3, r3, #8
 8002772:	6013      	str	r3, [r2, #0]
 8002774:	4b63      	ldr	r3, [pc, #396]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002776:	681b      	ldr	r3, [r3, #0]
 8002778:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 800277c:	687b      	ldr	r3, [r7, #4]
 800277e:	6a1b      	ldr	r3, [r3, #32]
 8002780:	4960      	ldr	r1, [pc, #384]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002782:	4313      	orrs	r3, r2
 8002784:	600b      	str	r3, [r1, #0]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8002786:	4b5f      	ldr	r3, [pc, #380]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002788:	685b      	ldr	r3, [r3, #4]
 800278a:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 800278e:	687b      	ldr	r3, [r7, #4]
 8002790:	69db      	ldr	r3, [r3, #28]
 8002792:	021b      	lsls	r3, r3, #8
 8002794:	495b      	ldr	r1, [pc, #364]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002796:	4313      	orrs	r3, r2
 8002798:	604b      	str	r3, [r1, #4]

          /* Decrease number of wait states update if necessary */
          /* Only possible when MSI is the System clock source  */
          if(sysclk_source == RCC_CFGR_SWS_MSI)
 800279a:	69bb      	ldr	r3, [r7, #24]
 800279c:	2b00      	cmp	r3, #0
 800279e:	d109      	bne.n	80027b4 <HAL_RCC_OscConfig+0x120>
          {
            if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 80027a0:	687b      	ldr	r3, [r7, #4]
 80027a2:	6a1b      	ldr	r3, [r3, #32]
 80027a4:	4618      	mov	r0, r3
 80027a6:	f000 fd47 	bl	8003238 <RCC_SetFlashLatencyFromMSIRange>
 80027aa:	4603      	mov	r3, r0
 80027ac:	2b00      	cmp	r3, #0
 80027ae:	d001      	beq.n	80027b4 <HAL_RCC_OscConfig+0x120>
            {
              return HAL_ERROR;
 80027b0:	2301      	movs	r3, #1
 80027b2:	e343      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
            }
          }
        }

        /* Update the SystemCoreClock global variable */
        SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 80027b4:	f000 fc4a 	bl	800304c <HAL_RCC_GetSysClockFreq>
 80027b8:	4602      	mov	r2, r0
 80027ba:	4b52      	ldr	r3, [pc, #328]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80027bc:	689b      	ldr	r3, [r3, #8]
 80027be:	091b      	lsrs	r3, r3, #4
 80027c0:	f003 030f 	and.w	r3, r3, #15
 80027c4:	4950      	ldr	r1, [pc, #320]	@ (8002908 <HAL_RCC_OscConfig+0x274>)
 80027c6:	5ccb      	ldrb	r3, [r1, r3]
 80027c8:	f003 031f 	and.w	r3, r3, #31
 80027cc:	fa22 f303 	lsr.w	r3, r2, r3
 80027d0:	4a4e      	ldr	r2, [pc, #312]	@ (800290c <HAL_RCC_OscConfig+0x278>)
 80027d2:	6013      	str	r3, [r2, #0]

        /* Configure the source of time base considering new system clocks settings*/
        status = HAL_InitTick(uwTickPrio);
 80027d4:	4b4e      	ldr	r3, [pc, #312]	@ (8002910 <HAL_RCC_OscConfig+0x27c>)
 80027d6:	681b      	ldr	r3, [r3, #0]
 80027d8:	4618      	mov	r0, r3
 80027da:	f7fe fe05 	bl	80013e8 <HAL_InitTick>
 80027de:	4603      	mov	r3, r0
 80027e0:	73fb      	strb	r3, [r7, #15]
        if(status != HAL_OK)
 80027e2:	7bfb      	ldrb	r3, [r7, #15]
 80027e4:	2b00      	cmp	r3, #0
 80027e6:	d052      	beq.n	800288e <HAL_RCC_OscConfig+0x1fa>
        {
          return status;
 80027e8:	7bfb      	ldrb	r3, [r7, #15]
 80027ea:	e327      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
    }
    else
    {
      /* Check the MSI State */
      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
 80027ec:	687b      	ldr	r3, [r7, #4]
 80027ee:	699b      	ldr	r3, [r3, #24]
 80027f0:	2b00      	cmp	r3, #0
 80027f2:	d032      	beq.n	800285a <HAL_RCC_OscConfig+0x1c6>
      {
        /* Enable the Internal High Speed oscillator (MSI). */
        __HAL_RCC_MSI_ENABLE();
 80027f4:	4b43      	ldr	r3, [pc, #268]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80027f6:	681b      	ldr	r3, [r3, #0]
 80027f8:	4a42      	ldr	r2, [pc, #264]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80027fa:	f043 0301 	orr.w	r3, r3, #1
 80027fe:	6013      	str	r3, [r2, #0]

        /* Get timeout */
        tickstart = HAL_GetTick();
 8002800:	f7fe ff20 	bl	8001644 <HAL_GetTick>
 8002804:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 8002806:	e008      	b.n	800281a <HAL_RCC_OscConfig+0x186>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8002808:	f7fe ff1c 	bl	8001644 <HAL_GetTick>
 800280c:	4602      	mov	r2, r0
 800280e:	693b      	ldr	r3, [r7, #16]
 8002810:	1ad3      	subs	r3, r2, r3
 8002812:	2b02      	cmp	r3, #2
 8002814:	d901      	bls.n	800281a <HAL_RCC_OscConfig+0x186>
          {
            return HAL_TIMEOUT;
 8002816:	2303      	movs	r3, #3
 8002818:	e310      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 800281a:	4b3a      	ldr	r3, [pc, #232]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800281c:	681b      	ldr	r3, [r3, #0]
 800281e:	f003 0302 	and.w	r3, r3, #2
 8002822:	2b00      	cmp	r3, #0
 8002824:	d0f0      	beq.n	8002808 <HAL_RCC_OscConfig+0x174>
          }
        }
         /* Selects the Multiple Speed oscillator (MSI) clock range .*/
        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8002826:	4b37      	ldr	r3, [pc, #220]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002828:	681b      	ldr	r3, [r3, #0]
 800282a:	4a36      	ldr	r2, [pc, #216]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800282c:	f043 0308 	orr.w	r3, r3, #8
 8002830:	6013      	str	r3, [r2, #0]
 8002832:	4b34      	ldr	r3, [pc, #208]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002834:	681b      	ldr	r3, [r3, #0]
 8002836:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 800283a:	687b      	ldr	r3, [r7, #4]
 800283c:	6a1b      	ldr	r3, [r3, #32]
 800283e:	4931      	ldr	r1, [pc, #196]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002840:	4313      	orrs	r3, r2
 8002842:	600b      	str	r3, [r1, #0]
         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8002844:	4b2f      	ldr	r3, [pc, #188]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002846:	685b      	ldr	r3, [r3, #4]
 8002848:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 800284c:	687b      	ldr	r3, [r7, #4]
 800284e:	69db      	ldr	r3, [r3, #28]
 8002850:	021b      	lsls	r3, r3, #8
 8002852:	492c      	ldr	r1, [pc, #176]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002854:	4313      	orrs	r3, r2
 8002856:	604b      	str	r3, [r1, #4]
 8002858:	e01a      	b.n	8002890 <HAL_RCC_OscConfig+0x1fc>

      }
      else
      {
        /* Disable the Internal High Speed oscillator (MSI). */
        __HAL_RCC_MSI_DISABLE();
 800285a:	4b2a      	ldr	r3, [pc, #168]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 800285c:	681b      	ldr	r3, [r3, #0]
 800285e:	4a29      	ldr	r2, [pc, #164]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002860:	f023 0301 	bic.w	r3, r3, #1
 8002864:	6013      	str	r3, [r2, #0]

        /* Get timeout */
        tickstart = HAL_GetTick();
 8002866:	f7fe feed 	bl	8001644 <HAL_GetTick>
 800286a:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
 800286c:	e008      	b.n	8002880 <HAL_RCC_OscConfig+0x1ec>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 800286e:	f7fe fee9 	bl	8001644 <HAL_GetTick>
 8002872:	4602      	mov	r2, r0
 8002874:	693b      	ldr	r3, [r7, #16]
 8002876:	1ad3      	subs	r3, r2, r3
 8002878:	2b02      	cmp	r3, #2
 800287a:	d901      	bls.n	8002880 <HAL_RCC_OscConfig+0x1ec>
          {
            return HAL_TIMEOUT;
 800287c:	2303      	movs	r3, #3
 800287e:	e2dd      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
 8002880:	4b20      	ldr	r3, [pc, #128]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 8002882:	681b      	ldr	r3, [r3, #0]
 8002884:	f003 0302 	and.w	r3, r3, #2
 8002888:	2b00      	cmp	r3, #0
 800288a:	d1f0      	bne.n	800286e <HAL_RCC_OscConfig+0x1da>
 800288c:	e000      	b.n	8002890 <HAL_RCC_OscConfig+0x1fc>
      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 800288e:	bf00      	nop
        }
      }
    }
  }
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8002890:	687b      	ldr	r3, [r7, #4]
 8002892:	681b      	ldr	r3, [r3, #0]
 8002894:	f003 0301 	and.w	r3, r3, #1
 8002898:	2b00      	cmp	r3, #0
 800289a:	d074      	beq.n	8002986 <HAL_RCC_OscConfig+0x2f2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((sysclk_source == RCC_CFGR_SWS_HSE) ||
 800289c:	69bb      	ldr	r3, [r7, #24]
 800289e:	2b08      	cmp	r3, #8
 80028a0:	d005      	beq.n	80028ae <HAL_RCC_OscConfig+0x21a>
 80028a2:	69bb      	ldr	r3, [r7, #24]
 80028a4:	2b0c      	cmp	r3, #12
 80028a6:	d10e      	bne.n	80028c6 <HAL_RCC_OscConfig+0x232>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
 80028a8:	697b      	ldr	r3, [r7, #20]
 80028aa:	2b03      	cmp	r3, #3
 80028ac:	d10b      	bne.n	80028c6 <HAL_RCC_OscConfig+0x232>
    {
      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80028ae:	4b15      	ldr	r3, [pc, #84]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028b0:	681b      	ldr	r3, [r3, #0]
 80028b2:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80028b6:	2b00      	cmp	r3, #0
 80028b8:	d064      	beq.n	8002984 <HAL_RCC_OscConfig+0x2f0>
 80028ba:	687b      	ldr	r3, [r7, #4]
 80028bc:	685b      	ldr	r3, [r3, #4]
 80028be:	2b00      	cmp	r3, #0
 80028c0:	d160      	bne.n	8002984 <HAL_RCC_OscConfig+0x2f0>
      {
        return HAL_ERROR;
 80028c2:	2301      	movs	r3, #1
 80028c4:	e2ba      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 80028c6:	687b      	ldr	r3, [r7, #4]
 80028c8:	685b      	ldr	r3, [r3, #4]
 80028ca:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 80028ce:	d106      	bne.n	80028de <HAL_RCC_OscConfig+0x24a>
 80028d0:	4b0c      	ldr	r3, [pc, #48]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028d2:	681b      	ldr	r3, [r3, #0]
 80028d4:	4a0b      	ldr	r2, [pc, #44]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028d6:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80028da:	6013      	str	r3, [r2, #0]
 80028dc:	e026      	b.n	800292c <HAL_RCC_OscConfig+0x298>
 80028de:	687b      	ldr	r3, [r7, #4]
 80028e0:	685b      	ldr	r3, [r3, #4]
 80028e2:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 80028e6:	d115      	bne.n	8002914 <HAL_RCC_OscConfig+0x280>
 80028e8:	4b06      	ldr	r3, [pc, #24]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028ea:	681b      	ldr	r3, [r3, #0]
 80028ec:	4a05      	ldr	r2, [pc, #20]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028ee:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 80028f2:	6013      	str	r3, [r2, #0]
 80028f4:	4b03      	ldr	r3, [pc, #12]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028f6:	681b      	ldr	r3, [r3, #0]
 80028f8:	4a02      	ldr	r2, [pc, #8]	@ (8002904 <HAL_RCC_OscConfig+0x270>)
 80028fa:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80028fe:	6013      	str	r3, [r2, #0]
 8002900:	e014      	b.n	800292c <HAL_RCC_OscConfig+0x298>
 8002902:	bf00      	nop
 8002904:	40021000 	.word	0x40021000
 8002908:	080095c8 	.word	0x080095c8
 800290c:	20000000 	.word	0x20000000
 8002910:	20000004 	.word	0x20000004
 8002914:	4ba0      	ldr	r3, [pc, #640]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002916:	681b      	ldr	r3, [r3, #0]
 8002918:	4a9f      	ldr	r2, [pc, #636]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 800291a:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800291e:	6013      	str	r3, [r2, #0]
 8002920:	4b9d      	ldr	r3, [pc, #628]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002922:	681b      	ldr	r3, [r3, #0]
 8002924:	4a9c      	ldr	r2, [pc, #624]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002926:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 800292a:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 800292c:	687b      	ldr	r3, [r7, #4]
 800292e:	685b      	ldr	r3, [r3, #4]
 8002930:	2b00      	cmp	r3, #0
 8002932:	d013      	beq.n	800295c <HAL_RCC_OscConfig+0x2c8>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8002934:	f7fe fe86 	bl	8001644 <HAL_GetTick>
 8002938:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 800293a:	e008      	b.n	800294e <HAL_RCC_OscConfig+0x2ba>
        {
          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800293c:	f7fe fe82 	bl	8001644 <HAL_GetTick>
 8002940:	4602      	mov	r2, r0
 8002942:	693b      	ldr	r3, [r7, #16]
 8002944:	1ad3      	subs	r3, r2, r3
 8002946:	2b64      	cmp	r3, #100	@ 0x64
 8002948:	d901      	bls.n	800294e <HAL_RCC_OscConfig+0x2ba>
          {
            return HAL_TIMEOUT;
 800294a:	2303      	movs	r3, #3
 800294c:	e276      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 800294e:	4b92      	ldr	r3, [pc, #584]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002950:	681b      	ldr	r3, [r3, #0]
 8002952:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8002956:	2b00      	cmp	r3, #0
 8002958:	d0f0      	beq.n	800293c <HAL_RCC_OscConfig+0x2a8>
 800295a:	e014      	b.n	8002986 <HAL_RCC_OscConfig+0x2f2>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800295c:	f7fe fe72 	bl	8001644 <HAL_GetTick>
 8002960:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 8002962:	e008      	b.n	8002976 <HAL_RCC_OscConfig+0x2e2>
        {
          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8002964:	f7fe fe6e 	bl	8001644 <HAL_GetTick>
 8002968:	4602      	mov	r2, r0
 800296a:	693b      	ldr	r3, [r7, #16]
 800296c:	1ad3      	subs	r3, r2, r3
 800296e:	2b64      	cmp	r3, #100	@ 0x64
 8002970:	d901      	bls.n	8002976 <HAL_RCC_OscConfig+0x2e2>
          {
            return HAL_TIMEOUT;
 8002972:	2303      	movs	r3, #3
 8002974:	e262      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 8002976:	4b88      	ldr	r3, [pc, #544]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002978:	681b      	ldr	r3, [r3, #0]
 800297a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800297e:	2b00      	cmp	r3, #0
 8002980:	d1f0      	bne.n	8002964 <HAL_RCC_OscConfig+0x2d0>
 8002982:	e000      	b.n	8002986 <HAL_RCC_OscConfig+0x2f2>
      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8002984:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8002986:	687b      	ldr	r3, [r7, #4]
 8002988:	681b      	ldr	r3, [r3, #0]
 800298a:	f003 0302 	and.w	r3, r3, #2
 800298e:	2b00      	cmp	r3, #0
 8002990:	d060      	beq.n	8002a54 <HAL_RCC_OscConfig+0x3c0>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_CFGR_SWS_HSI) ||
 8002992:	69bb      	ldr	r3, [r7, #24]
 8002994:	2b04      	cmp	r3, #4
 8002996:	d005      	beq.n	80029a4 <HAL_RCC_OscConfig+0x310>
 8002998:	69bb      	ldr	r3, [r7, #24]
 800299a:	2b0c      	cmp	r3, #12
 800299c:	d119      	bne.n	80029d2 <HAL_RCC_OscConfig+0x33e>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
 800299e:	697b      	ldr	r3, [r7, #20]
 80029a0:	2b02      	cmp	r3, #2
 80029a2:	d116      	bne.n	80029d2 <HAL_RCC_OscConfig+0x33e>
    {
      /* When HSI is used as system clock it will not be disabled */
      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 80029a4:	4b7c      	ldr	r3, [pc, #496]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029a6:	681b      	ldr	r3, [r3, #0]
 80029a8:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80029ac:	2b00      	cmp	r3, #0
 80029ae:	d005      	beq.n	80029bc <HAL_RCC_OscConfig+0x328>
 80029b0:	687b      	ldr	r3, [r7, #4]
 80029b2:	68db      	ldr	r3, [r3, #12]
 80029b4:	2b00      	cmp	r3, #0
 80029b6:	d101      	bne.n	80029bc <HAL_RCC_OscConfig+0x328>
      {
        return HAL_ERROR;
 80029b8:	2301      	movs	r3, #1
 80029ba:	e23f      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80029bc:	4b76      	ldr	r3, [pc, #472]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029be:	685b      	ldr	r3, [r3, #4]
 80029c0:	f023 52f8 	bic.w	r2, r3, #520093696	@ 0x1f000000
 80029c4:	687b      	ldr	r3, [r7, #4]
 80029c6:	691b      	ldr	r3, [r3, #16]
 80029c8:	061b      	lsls	r3, r3, #24
 80029ca:	4973      	ldr	r1, [pc, #460]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029cc:	4313      	orrs	r3, r2
 80029ce:	604b      	str	r3, [r1, #4]
      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 80029d0:	e040      	b.n	8002a54 <HAL_RCC_OscConfig+0x3c0>
      }
    }
    else
    {
      /* Check the HSI State */
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 80029d2:	687b      	ldr	r3, [r7, #4]
 80029d4:	68db      	ldr	r3, [r3, #12]
 80029d6:	2b00      	cmp	r3, #0
 80029d8:	d023      	beq.n	8002a22 <HAL_RCC_OscConfig+0x38e>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 80029da:	4b6f      	ldr	r3, [pc, #444]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029dc:	681b      	ldr	r3, [r3, #0]
 80029de:	4a6e      	ldr	r2, [pc, #440]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 80029e0:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 80029e4:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80029e6:	f7fe fe2d 	bl	8001644 <HAL_GetTick>
 80029ea:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 80029ec:	e008      	b.n	8002a00 <HAL_RCC_OscConfig+0x36c>
        {
          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80029ee:	f7fe fe29 	bl	8001644 <HAL_GetTick>
 80029f2:	4602      	mov	r2, r0
 80029f4:	693b      	ldr	r3, [r7, #16]
 80029f6:	1ad3      	subs	r3, r2, r3
 80029f8:	2b02      	cmp	r3, #2
 80029fa:	d901      	bls.n	8002a00 <HAL_RCC_OscConfig+0x36c>
          {
            return HAL_TIMEOUT;
 80029fc:	2303      	movs	r3, #3
 80029fe:	e21d      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8002a00:	4b65      	ldr	r3, [pc, #404]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a02:	681b      	ldr	r3, [r3, #0]
 8002a04:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8002a08:	2b00      	cmp	r3, #0
 8002a0a:	d0f0      	beq.n	80029ee <HAL_RCC_OscConfig+0x35a>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8002a0c:	4b62      	ldr	r3, [pc, #392]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a0e:	685b      	ldr	r3, [r3, #4]
 8002a10:	f023 52f8 	bic.w	r2, r3, #520093696	@ 0x1f000000
 8002a14:	687b      	ldr	r3, [r7, #4]
 8002a16:	691b      	ldr	r3, [r3, #16]
 8002a18:	061b      	lsls	r3, r3, #24
 8002a1a:	495f      	ldr	r1, [pc, #380]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a1c:	4313      	orrs	r3, r2
 8002a1e:	604b      	str	r3, [r1, #4]
 8002a20:	e018      	b.n	8002a54 <HAL_RCC_OscConfig+0x3c0>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 8002a22:	4b5d      	ldr	r3, [pc, #372]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a24:	681b      	ldr	r3, [r3, #0]
 8002a26:	4a5c      	ldr	r2, [pc, #368]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a28:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 8002a2c:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8002a2e:	f7fe fe09 	bl	8001644 <HAL_GetTick>
 8002a32:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 8002a34:	e008      	b.n	8002a48 <HAL_RCC_OscConfig+0x3b4>
        {
          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8002a36:	f7fe fe05 	bl	8001644 <HAL_GetTick>
 8002a3a:	4602      	mov	r2, r0
 8002a3c:	693b      	ldr	r3, [r7, #16]
 8002a3e:	1ad3      	subs	r3, r2, r3
 8002a40:	2b02      	cmp	r3, #2
 8002a42:	d901      	bls.n	8002a48 <HAL_RCC_OscConfig+0x3b4>
          {
            return HAL_TIMEOUT;
 8002a44:	2303      	movs	r3, #3
 8002a46:	e1f9      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 8002a48:	4b53      	ldr	r3, [pc, #332]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a4a:	681b      	ldr	r3, [r3, #0]
 8002a4c:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8002a50:	2b00      	cmp	r3, #0
 8002a52:	d1f0      	bne.n	8002a36 <HAL_RCC_OscConfig+0x3a2>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8002a54:	687b      	ldr	r3, [r7, #4]
 8002a56:	681b      	ldr	r3, [r3, #0]
 8002a58:	f003 0308 	and.w	r3, r3, #8
 8002a5c:	2b00      	cmp	r3, #0
 8002a5e:	d03c      	beq.n	8002ada <HAL_RCC_OscConfig+0x446>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8002a60:	687b      	ldr	r3, [r7, #4]
 8002a62:	695b      	ldr	r3, [r3, #20]
 8002a64:	2b00      	cmp	r3, #0
 8002a66:	d01c      	beq.n	8002aa2 <HAL_RCC_OscConfig+0x40e>
        MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
      }
#endif /* RCC_CSR_LSIPREDIV */

      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8002a68:	4b4b      	ldr	r3, [pc, #300]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a6a:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002a6e:	4a4a      	ldr	r2, [pc, #296]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a70:	f043 0301 	orr.w	r3, r3, #1
 8002a74:	f8c2 3094 	str.w	r3, [r2, #148]	@ 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002a78:	f7fe fde4 	bl	8001644 <HAL_GetTick>
 8002a7c:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8002a7e:	e008      	b.n	8002a92 <HAL_RCC_OscConfig+0x3fe>
      {
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8002a80:	f7fe fde0 	bl	8001644 <HAL_GetTick>
 8002a84:	4602      	mov	r2, r0
 8002a86:	693b      	ldr	r3, [r7, #16]
 8002a88:	1ad3      	subs	r3, r2, r3
 8002a8a:	2b02      	cmp	r3, #2
 8002a8c:	d901      	bls.n	8002a92 <HAL_RCC_OscConfig+0x3fe>
        {
          return HAL_TIMEOUT;
 8002a8e:	2303      	movs	r3, #3
 8002a90:	e1d4      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8002a92:	4b41      	ldr	r3, [pc, #260]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002a94:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002a98:	f003 0302 	and.w	r3, r3, #2
 8002a9c:	2b00      	cmp	r3, #0
 8002a9e:	d0ef      	beq.n	8002a80 <HAL_RCC_OscConfig+0x3ec>
 8002aa0:	e01b      	b.n	8002ada <HAL_RCC_OscConfig+0x446>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8002aa2:	4b3d      	ldr	r3, [pc, #244]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002aa4:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002aa8:	4a3b      	ldr	r2, [pc, #236]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002aaa:	f023 0301 	bic.w	r3, r3, #1
 8002aae:	f8c2 3094 	str.w	r3, [r2, #148]	@ 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002ab2:	f7fe fdc7 	bl	8001644 <HAL_GetTick>
 8002ab6:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is disabled */
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8002ab8:	e008      	b.n	8002acc <HAL_RCC_OscConfig+0x438>
      {
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8002aba:	f7fe fdc3 	bl	8001644 <HAL_GetTick>
 8002abe:	4602      	mov	r2, r0
 8002ac0:	693b      	ldr	r3, [r7, #16]
 8002ac2:	1ad3      	subs	r3, r2, r3
 8002ac4:	2b02      	cmp	r3, #2
 8002ac6:	d901      	bls.n	8002acc <HAL_RCC_OscConfig+0x438>
        {
          return HAL_TIMEOUT;
 8002ac8:	2303      	movs	r3, #3
 8002aca:	e1b7      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8002acc:	4b32      	ldr	r3, [pc, #200]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002ace:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8002ad2:	f003 0302 	and.w	r3, r3, #2
 8002ad6:	2b00      	cmp	r3, #0
 8002ad8:	d1ef      	bne.n	8002aba <HAL_RCC_OscConfig+0x426>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8002ada:	687b      	ldr	r3, [r7, #4]
 8002adc:	681b      	ldr	r3, [r3, #0]
 8002ade:	f003 0304 	and.w	r3, r3, #4
 8002ae2:	2b00      	cmp	r3, #0
 8002ae4:	f000 80a6 	beq.w	8002c34 <HAL_RCC_OscConfig+0x5a0>
  {
    FlagStatus       pwrclkchanged = RESET;
 8002ae8:	2300      	movs	r3, #0
 8002aea:	77fb      	strb	r3, [r7, #31]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
 8002aec:	4b2a      	ldr	r3, [pc, #168]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002aee:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8002af0:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8002af4:	2b00      	cmp	r3, #0
 8002af6:	d10d      	bne.n	8002b14 <HAL_RCC_OscConfig+0x480>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8002af8:	4b27      	ldr	r3, [pc, #156]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002afa:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8002afc:	4a26      	ldr	r2, [pc, #152]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002afe:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8002b02:	6593      	str	r3, [r2, #88]	@ 0x58
 8002b04:	4b24      	ldr	r3, [pc, #144]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b06:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8002b08:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8002b0c:	60bb      	str	r3, [r7, #8]
 8002b0e:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8002b10:	2301      	movs	r3, #1
 8002b12:	77fb      	strb	r3, [r7, #31]
    }

    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8002b14:	4b21      	ldr	r3, [pc, #132]	@ (8002b9c <HAL_RCC_OscConfig+0x508>)
 8002b16:	681b      	ldr	r3, [r3, #0]
 8002b18:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8002b1c:	2b00      	cmp	r3, #0
 8002b1e:	d118      	bne.n	8002b52 <HAL_RCC_OscConfig+0x4be>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8002b20:	4b1e      	ldr	r3, [pc, #120]	@ (8002b9c <HAL_RCC_OscConfig+0x508>)
 8002b22:	681b      	ldr	r3, [r3, #0]
 8002b24:	4a1d      	ldr	r2, [pc, #116]	@ (8002b9c <HAL_RCC_OscConfig+0x508>)
 8002b26:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8002b2a:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8002b2c:	f7fe fd8a 	bl	8001644 <HAL_GetTick>
 8002b30:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8002b32:	e008      	b.n	8002b46 <HAL_RCC_OscConfig+0x4b2>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8002b34:	f7fe fd86 	bl	8001644 <HAL_GetTick>
 8002b38:	4602      	mov	r2, r0
 8002b3a:	693b      	ldr	r3, [r7, #16]
 8002b3c:	1ad3      	subs	r3, r2, r3
 8002b3e:	2b02      	cmp	r3, #2
 8002b40:	d901      	bls.n	8002b46 <HAL_RCC_OscConfig+0x4b2>
        {
          return HAL_TIMEOUT;
 8002b42:	2303      	movs	r3, #3
 8002b44:	e17a      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8002b46:	4b15      	ldr	r3, [pc, #84]	@ (8002b9c <HAL_RCC_OscConfig+0x508>)
 8002b48:	681b      	ldr	r3, [r3, #0]
 8002b4a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8002b4e:	2b00      	cmp	r3, #0
 8002b50:	d0f0      	beq.n	8002b34 <HAL_RCC_OscConfig+0x4a0>
    {
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
    }
#else
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8002b52:	687b      	ldr	r3, [r7, #4]
 8002b54:	689b      	ldr	r3, [r3, #8]
 8002b56:	2b01      	cmp	r3, #1
 8002b58:	d108      	bne.n	8002b6c <HAL_RCC_OscConfig+0x4d8>
 8002b5a:	4b0f      	ldr	r3, [pc, #60]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b5c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002b60:	4a0d      	ldr	r2, [pc, #52]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b62:	f043 0301 	orr.w	r3, r3, #1
 8002b66:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8002b6a:	e029      	b.n	8002bc0 <HAL_RCC_OscConfig+0x52c>
 8002b6c:	687b      	ldr	r3, [r7, #4]
 8002b6e:	689b      	ldr	r3, [r3, #8]
 8002b70:	2b05      	cmp	r3, #5
 8002b72:	d115      	bne.n	8002ba0 <HAL_RCC_OscConfig+0x50c>
 8002b74:	4b08      	ldr	r3, [pc, #32]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b76:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002b7a:	4a07      	ldr	r2, [pc, #28]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b7c:	f043 0304 	orr.w	r3, r3, #4
 8002b80:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8002b84:	4b04      	ldr	r3, [pc, #16]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b86:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002b8a:	4a03      	ldr	r2, [pc, #12]	@ (8002b98 <HAL_RCC_OscConfig+0x504>)
 8002b8c:	f043 0301 	orr.w	r3, r3, #1
 8002b90:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8002b94:	e014      	b.n	8002bc0 <HAL_RCC_OscConfig+0x52c>
 8002b96:	bf00      	nop
 8002b98:	40021000 	.word	0x40021000
 8002b9c:	40007000 	.word	0x40007000
 8002ba0:	4b9c      	ldr	r3, [pc, #624]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ba2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002ba6:	4a9b      	ldr	r2, [pc, #620]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ba8:	f023 0301 	bic.w	r3, r3, #1
 8002bac:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8002bb0:	4b98      	ldr	r3, [pc, #608]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002bb2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002bb6:	4a97      	ldr	r2, [pc, #604]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002bb8:	f023 0304 	bic.w	r3, r3, #4
 8002bbc:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
#endif /* RCC_BDCR_LSESYSDIS */

    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8002bc0:	687b      	ldr	r3, [r7, #4]
 8002bc2:	689b      	ldr	r3, [r3, #8]
 8002bc4:	2b00      	cmp	r3, #0
 8002bc6:	d016      	beq.n	8002bf6 <HAL_RCC_OscConfig+0x562>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002bc8:	f7fe fd3c 	bl	8001644 <HAL_GetTick>
 8002bcc:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8002bce:	e00a      	b.n	8002be6 <HAL_RCC_OscConfig+0x552>
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8002bd0:	f7fe fd38 	bl	8001644 <HAL_GetTick>
 8002bd4:	4602      	mov	r2, r0
 8002bd6:	693b      	ldr	r3, [r7, #16]
 8002bd8:	1ad3      	subs	r3, r2, r3
 8002bda:	f241 3288 	movw	r2, #5000	@ 0x1388
 8002bde:	4293      	cmp	r3, r2
 8002be0:	d901      	bls.n	8002be6 <HAL_RCC_OscConfig+0x552>
        {
          return HAL_TIMEOUT;
 8002be2:	2303      	movs	r3, #3
 8002be4:	e12a      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8002be6:	4b8b      	ldr	r3, [pc, #556]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002be8:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002bec:	f003 0302 	and.w	r3, r3, #2
 8002bf0:	2b00      	cmp	r3, #0
 8002bf2:	d0ed      	beq.n	8002bd0 <HAL_RCC_OscConfig+0x53c>
 8002bf4:	e015      	b.n	8002c22 <HAL_RCC_OscConfig+0x58e>
      }
    }
    else
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002bf6:	f7fe fd25 	bl	8001644 <HAL_GetTick>
 8002bfa:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is disabled */
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8002bfc:	e00a      	b.n	8002c14 <HAL_RCC_OscConfig+0x580>
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8002bfe:	f7fe fd21 	bl	8001644 <HAL_GetTick>
 8002c02:	4602      	mov	r2, r0
 8002c04:	693b      	ldr	r3, [r7, #16]
 8002c06:	1ad3      	subs	r3, r2, r3
 8002c08:	f241 3288 	movw	r2, #5000	@ 0x1388
 8002c0c:	4293      	cmp	r3, r2
 8002c0e:	d901      	bls.n	8002c14 <HAL_RCC_OscConfig+0x580>
        {
          return HAL_TIMEOUT;
 8002c10:	2303      	movs	r3, #3
 8002c12:	e113      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8002c14:	4b7f      	ldr	r3, [pc, #508]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002c16:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8002c1a:	f003 0302 	and.w	r3, r3, #2
 8002c1e:	2b00      	cmp	r3, #0
 8002c20:	d1ed      	bne.n	8002bfe <HAL_RCC_OscConfig+0x56a>
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8002c22:	7ffb      	ldrb	r3, [r7, #31]
 8002c24:	2b01      	cmp	r3, #1
 8002c26:	d105      	bne.n	8002c34 <HAL_RCC_OscConfig+0x5a0>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8002c28:	4b7a      	ldr	r3, [pc, #488]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002c2a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8002c2c:	4a79      	ldr	r2, [pc, #484]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002c2e:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8002c32:	6593      	str	r3, [r2, #88]	@ 0x58
#endif /* RCC_HSI48_SUPPORT */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
 8002c34:	687b      	ldr	r3, [r7, #4]
 8002c36:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002c38:	2b00      	cmp	r3, #0
 8002c3a:	f000 80fe 	beq.w	8002e3a <HAL_RCC_OscConfig+0x7a6>
  {
    /* PLL On ? */
    if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
 8002c3e:	687b      	ldr	r3, [r7, #4]
 8002c40:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002c42:	2b02      	cmp	r3, #2
 8002c44:	f040 80d0 	bne.w	8002de8 <HAL_RCC_OscConfig+0x754>
#endif /* RCC_PLLP_SUPPORT */
      assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
      assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));

      /* Do nothing if PLL configuration is the unchanged */
      pll_config = RCC->PLLCFGR;
 8002c48:	4b72      	ldr	r3, [pc, #456]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002c4a:	68db      	ldr	r3, [r3, #12]
 8002c4c:	617b      	str	r3, [r7, #20]
      if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8002c4e:	697b      	ldr	r3, [r7, #20]
 8002c50:	f003 0203 	and.w	r2, r3, #3
 8002c54:	687b      	ldr	r3, [r7, #4]
 8002c56:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8002c58:	429a      	cmp	r2, r3
 8002c5a:	d130      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8002c5c:	697b      	ldr	r3, [r7, #20]
 8002c5e:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 8002c62:	687b      	ldr	r3, [r7, #4]
 8002c64:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8002c66:	3b01      	subs	r3, #1
 8002c68:	011b      	lsls	r3, r3, #4
      if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8002c6a:	429a      	cmp	r2, r3
 8002c6c:	d127      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8002c6e:	697b      	ldr	r3, [r7, #20]
 8002c70:	f403 42fe 	and.w	r2, r3, #32512	@ 0x7f00
 8002c74:	687b      	ldr	r3, [r7, #4]
 8002c76:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8002c78:	021b      	lsls	r3, r3, #8
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8002c7a:	429a      	cmp	r2, r3
 8002c7c:	d11f      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
#else
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
 8002c7e:	697b      	ldr	r3, [r7, #20]
 8002c80:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8002c84:	687a      	ldr	r2, [r7, #4]
 8002c86:	6b92      	ldr	r2, [r2, #56]	@ 0x38
 8002c88:	2a07      	cmp	r2, #7
 8002c8a:	bf14      	ite	ne
 8002c8c:	2201      	movne	r2, #1
 8002c8e:	2200      	moveq	r2, #0
 8002c90:	b2d2      	uxtb	r2, r2
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8002c92:	4293      	cmp	r3, r2
 8002c94:	d113      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
#endif
#endif
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8002c96:	697b      	ldr	r3, [r7, #20]
 8002c98:	f403 02c0 	and.w	r2, r3, #6291456	@ 0x600000
 8002c9c:	687b      	ldr	r3, [r7, #4]
 8002c9e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8002ca0:	085b      	lsrs	r3, r3, #1
 8002ca2:	3b01      	subs	r3, #1
 8002ca4:	055b      	lsls	r3, r3, #21
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
 8002ca6:	429a      	cmp	r2, r3
 8002ca8:	d109      	bne.n	8002cbe <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLR)    != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
 8002caa:	697b      	ldr	r3, [r7, #20]
 8002cac:	f003 62c0 	and.w	r2, r3, #100663296	@ 0x6000000
 8002cb0:	687b      	ldr	r3, [r7, #4]
 8002cb2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8002cb4:	085b      	lsrs	r3, r3, #1
 8002cb6:	3b01      	subs	r3, #1
 8002cb8:	065b      	lsls	r3, r3, #25
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8002cba:	429a      	cmp	r2, r3
 8002cbc:	d06e      	beq.n	8002d9c <HAL_RCC_OscConfig+0x708>
      {
        /* Check if the PLL is used as system clock or not */
        if(sysclk_source != RCC_CFGR_SWS_PLL)
 8002cbe:	69bb      	ldr	r3, [r7, #24]
 8002cc0:	2b0c      	cmp	r3, #12
 8002cc2:	d069      	beq.n	8002d98 <HAL_RCC_OscConfig+0x704>
        {
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
          /* Check if main PLL can be updated */
          /* Not possible if the source is shared by other enabled PLLSAIx */
          if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
 8002cc4:	4b53      	ldr	r3, [pc, #332]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002cc6:	681b      	ldr	r3, [r3, #0]
 8002cc8:	f003 6380 	and.w	r3, r3, #67108864	@ 0x4000000
 8002ccc:	2b00      	cmp	r3, #0
 8002cce:	d105      	bne.n	8002cdc <HAL_RCC_OscConfig+0x648>
#if defined(RCC_PLLSAI2_SUPPORT)
             || (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
 8002cd0:	4b50      	ldr	r3, [pc, #320]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002cd2:	681b      	ldr	r3, [r3, #0]
 8002cd4:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8002cd8:	2b00      	cmp	r3, #0
 8002cda:	d001      	beq.n	8002ce0 <HAL_RCC_OscConfig+0x64c>
#endif
            )
          {
            return HAL_ERROR;
 8002cdc:	2301      	movs	r3, #1
 8002cde:	e0ad      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
          }
          else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
          {
            /* Disable the main PLL. */
            __HAL_RCC_PLL_DISABLE();
 8002ce0:	4b4c      	ldr	r3, [pc, #304]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ce2:	681b      	ldr	r3, [r3, #0]
 8002ce4:	4a4b      	ldr	r2, [pc, #300]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ce6:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 8002cea:	6013      	str	r3, [r2, #0]

            /* Get Start Tick*/
            tickstart = HAL_GetTick();
 8002cec:	f7fe fcaa 	bl	8001644 <HAL_GetTick>
 8002cf0:	6138      	str	r0, [r7, #16]

            /* Wait till PLL is ready */
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8002cf2:	e008      	b.n	8002d06 <HAL_RCC_OscConfig+0x672>
            {
              if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002cf4:	f7fe fca6 	bl	8001644 <HAL_GetTick>
 8002cf8:	4602      	mov	r2, r0
 8002cfa:	693b      	ldr	r3, [r7, #16]
 8002cfc:	1ad3      	subs	r3, r2, r3
 8002cfe:	2b02      	cmp	r3, #2
 8002d00:	d901      	bls.n	8002d06 <HAL_RCC_OscConfig+0x672>
              {
                return HAL_TIMEOUT;
 8002d02:	2303      	movs	r3, #3
 8002d04:	e09a      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8002d06:	4b43      	ldr	r3, [pc, #268]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d08:	681b      	ldr	r3, [r3, #0]
 8002d0a:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002d0e:	2b00      	cmp	r3, #0
 8002d10:	d1f0      	bne.n	8002cf4 <HAL_RCC_OscConfig+0x660>
              }
            }

            /* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
            __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8002d12:	4b40      	ldr	r3, [pc, #256]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d14:	68da      	ldr	r2, [r3, #12]
 8002d16:	4b40      	ldr	r3, [pc, #256]	@ (8002e18 <HAL_RCC_OscConfig+0x784>)
 8002d18:	4013      	ands	r3, r2
 8002d1a:	687a      	ldr	r2, [r7, #4]
 8002d1c:	6ad1      	ldr	r1, [r2, #44]	@ 0x2c
 8002d1e:	687a      	ldr	r2, [r7, #4]
 8002d20:	6b12      	ldr	r2, [r2, #48]	@ 0x30
 8002d22:	3a01      	subs	r2, #1
 8002d24:	0112      	lsls	r2, r2, #4
 8002d26:	4311      	orrs	r1, r2
 8002d28:	687a      	ldr	r2, [r7, #4]
 8002d2a:	6b52      	ldr	r2, [r2, #52]	@ 0x34
 8002d2c:	0212      	lsls	r2, r2, #8
 8002d2e:	4311      	orrs	r1, r2
 8002d30:	687a      	ldr	r2, [r7, #4]
 8002d32:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
 8002d34:	0852      	lsrs	r2, r2, #1
 8002d36:	3a01      	subs	r2, #1
 8002d38:	0552      	lsls	r2, r2, #21
 8002d3a:	4311      	orrs	r1, r2
 8002d3c:	687a      	ldr	r2, [r7, #4]
 8002d3e:	6c12      	ldr	r2, [r2, #64]	@ 0x40
 8002d40:	0852      	lsrs	r2, r2, #1
 8002d42:	3a01      	subs	r2, #1
 8002d44:	0652      	lsls	r2, r2, #25
 8002d46:	4311      	orrs	r1, r2
 8002d48:	687a      	ldr	r2, [r7, #4]
 8002d4a:	6b92      	ldr	r2, [r2, #56]	@ 0x38
 8002d4c:	0912      	lsrs	r2, r2, #4
 8002d4e:	0452      	lsls	r2, r2, #17
 8002d50:	430a      	orrs	r2, r1
 8002d52:	4930      	ldr	r1, [pc, #192]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d54:	4313      	orrs	r3, r2
 8002d56:	60cb      	str	r3, [r1, #12]
                                 RCC_OscInitStruct->PLL.PLLQ,
                                 RCC_OscInitStruct->PLL.PLLR);
#endif

            /* Enable the main PLL. */
            __HAL_RCC_PLL_ENABLE();
 8002d58:	4b2e      	ldr	r3, [pc, #184]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d5a:	681b      	ldr	r3, [r3, #0]
 8002d5c:	4a2d      	ldr	r2, [pc, #180]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d5e:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8002d62:	6013      	str	r3, [r2, #0]

            /* Enable PLL System Clock output. */
            __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 8002d64:	4b2b      	ldr	r3, [pc, #172]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d66:	68db      	ldr	r3, [r3, #12]
 8002d68:	4a2a      	ldr	r2, [pc, #168]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d6a:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8002d6e:	60d3      	str	r3, [r2, #12]

            /* Get Start Tick*/
            tickstart = HAL_GetTick();
 8002d70:	f7fe fc68 	bl	8001644 <HAL_GetTick>
 8002d74:	6138      	str	r0, [r7, #16]

            /* Wait till PLL is ready */
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002d76:	e008      	b.n	8002d8a <HAL_RCC_OscConfig+0x6f6>
            {
              if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002d78:	f7fe fc64 	bl	8001644 <HAL_GetTick>
 8002d7c:	4602      	mov	r2, r0
 8002d7e:	693b      	ldr	r3, [r7, #16]
 8002d80:	1ad3      	subs	r3, r2, r3
 8002d82:	2b02      	cmp	r3, #2
 8002d84:	d901      	bls.n	8002d8a <HAL_RCC_OscConfig+0x6f6>
              {
                return HAL_TIMEOUT;
 8002d86:	2303      	movs	r3, #3
 8002d88:	e058      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002d8a:	4b22      	ldr	r3, [pc, #136]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d8c:	681b      	ldr	r3, [r3, #0]
 8002d8e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002d92:	2b00      	cmp	r3, #0
 8002d94:	d0f0      	beq.n	8002d78 <HAL_RCC_OscConfig+0x6e4>
        if(sysclk_source != RCC_CFGR_SWS_PLL)
 8002d96:	e050      	b.n	8002e3a <HAL_RCC_OscConfig+0x7a6>
          }
        }
        else
        {
          /* PLL is already used as System core clock */
          return HAL_ERROR;
 8002d98:	2301      	movs	r3, #1
 8002d9a:	e04f      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
      else
      {
        /* PLL configuration is unchanged */
        /* Re-enable PLL if it was disabled (ie. low power mode) */
        if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002d9c:	4b1d      	ldr	r3, [pc, #116]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002d9e:	681b      	ldr	r3, [r3, #0]
 8002da0:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002da4:	2b00      	cmp	r3, #0
 8002da6:	d148      	bne.n	8002e3a <HAL_RCC_OscConfig+0x7a6>
        {
          /* Enable the main PLL. */
          __HAL_RCC_PLL_ENABLE();
 8002da8:	4b1a      	ldr	r3, [pc, #104]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002daa:	681b      	ldr	r3, [r3, #0]
 8002dac:	4a19      	ldr	r2, [pc, #100]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002dae:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8002db2:	6013      	str	r3, [r2, #0]

          /* Enable PLL System Clock output. */
          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 8002db4:	4b17      	ldr	r3, [pc, #92]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002db6:	68db      	ldr	r3, [r3, #12]
 8002db8:	4a16      	ldr	r2, [pc, #88]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002dba:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8002dbe:	60d3      	str	r3, [r2, #12]

          /* Get Start Tick*/
          tickstart = HAL_GetTick();
 8002dc0:	f7fe fc40 	bl	8001644 <HAL_GetTick>
 8002dc4:	6138      	str	r0, [r7, #16]

          /* Wait till PLL is ready */
          while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002dc6:	e008      	b.n	8002dda <HAL_RCC_OscConfig+0x746>
          {
            if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002dc8:	f7fe fc3c 	bl	8001644 <HAL_GetTick>
 8002dcc:	4602      	mov	r2, r0
 8002dce:	693b      	ldr	r3, [r7, #16]
 8002dd0:	1ad3      	subs	r3, r2, r3
 8002dd2:	2b02      	cmp	r3, #2
 8002dd4:	d901      	bls.n	8002dda <HAL_RCC_OscConfig+0x746>
            {
              return HAL_TIMEOUT;
 8002dd6:	2303      	movs	r3, #3
 8002dd8:	e030      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
          while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002dda:	4b0e      	ldr	r3, [pc, #56]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002ddc:	681b      	ldr	r3, [r3, #0]
 8002dde:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002de2:	2b00      	cmp	r3, #0
 8002de4:	d0f0      	beq.n	8002dc8 <HAL_RCC_OscConfig+0x734>
 8002de6:	e028      	b.n	8002e3a <HAL_RCC_OscConfig+0x7a6>
      }
    }
    else
    {
      /* Check that PLL is not used as system clock or not */
      if(sysclk_source != RCC_CFGR_SWS_PLL)
 8002de8:	69bb      	ldr	r3, [r7, #24]
 8002dea:	2b0c      	cmp	r3, #12
 8002dec:	d023      	beq.n	8002e36 <HAL_RCC_OscConfig+0x7a2>
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8002dee:	4b09      	ldr	r3, [pc, #36]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002df0:	681b      	ldr	r3, [r3, #0]
 8002df2:	4a08      	ldr	r2, [pc, #32]	@ (8002e14 <HAL_RCC_OscConfig+0x780>)
 8002df4:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 8002df8:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8002dfa:	f7fe fc23 	bl	8001644 <HAL_GetTick>
 8002dfe:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8002e00:	e00c      	b.n	8002e1c <HAL_RCC_OscConfig+0x788>
        {
          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002e02:	f7fe fc1f 	bl	8001644 <HAL_GetTick>
 8002e06:	4602      	mov	r2, r0
 8002e08:	693b      	ldr	r3, [r7, #16]
 8002e0a:	1ad3      	subs	r3, r2, r3
 8002e0c:	2b02      	cmp	r3, #2
 8002e0e:	d905      	bls.n	8002e1c <HAL_RCC_OscConfig+0x788>
          {
            return HAL_TIMEOUT;
 8002e10:	2303      	movs	r3, #3
 8002e12:	e013      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
 8002e14:	40021000 	.word	0x40021000
 8002e18:	f99d808c 	.word	0xf99d808c
        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8002e1c:	4b09      	ldr	r3, [pc, #36]	@ (8002e44 <HAL_RCC_OscConfig+0x7b0>)
 8002e1e:	681b      	ldr	r3, [r3, #0]
 8002e20:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002e24:	2b00      	cmp	r3, #0
 8002e26:	d1ec      	bne.n	8002e02 <HAL_RCC_OscConfig+0x76e>
          }
        }
        /* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
 8002e28:	4b06      	ldr	r3, [pc, #24]	@ (8002e44 <HAL_RCC_OscConfig+0x7b0>)
 8002e2a:	68da      	ldr	r2, [r3, #12]
 8002e2c:	4905      	ldr	r1, [pc, #20]	@ (8002e44 <HAL_RCC_OscConfig+0x7b0>)
 8002e2e:	4b06      	ldr	r3, [pc, #24]	@ (8002e48 <HAL_RCC_OscConfig+0x7b4>)
 8002e30:	4013      	ands	r3, r2
 8002e32:	60cb      	str	r3, [r1, #12]
 8002e34:	e001      	b.n	8002e3a <HAL_RCC_OscConfig+0x7a6>
#endif /* RCC_PLLSAI2_SUPPORT */
      }
      else
      {
        /* PLL is already used as System core clock */
        return HAL_ERROR;
 8002e36:	2301      	movs	r3, #1
 8002e38:	e000      	b.n	8002e3c <HAL_RCC_OscConfig+0x7a8>
      }
    }
  }
  return HAL_OK;
 8002e3a:	2300      	movs	r3, #0
}
 8002e3c:	4618      	mov	r0, r3
 8002e3e:	3720      	adds	r7, #32
 8002e40:	46bd      	mov	sp, r7
 8002e42:	bd80      	pop	{r7, pc}
 8002e44:	40021000 	.word	0x40021000
 8002e48:	feeefffc 	.word	0xfeeefffc

08002e4c <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8002e4c:	b580      	push	{r7, lr}
 8002e4e:	b084      	sub	sp, #16
 8002e50:	af00      	add	r7, sp, #0
 8002e52:	6078      	str	r0, [r7, #4]
 8002e54:	6039      	str	r1, [r7, #0]
  uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
  HAL_StatusTypeDef status;

  /* Check Null pointer */
  if(RCC_ClkInitStruct == NULL)
 8002e56:	687b      	ldr	r3, [r7, #4]
 8002e58:	2b00      	cmp	r3, #0
 8002e5a:	d101      	bne.n	8002e60 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8002e5c:	2301      	movs	r3, #1
 8002e5e:	e0e7      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8002e60:	4b75      	ldr	r3, [pc, #468]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002e62:	681b      	ldr	r3, [r3, #0]
 8002e64:	f003 0307 	and.w	r3, r3, #7
 8002e68:	683a      	ldr	r2, [r7, #0]
 8002e6a:	429a      	cmp	r2, r3
 8002e6c:	d910      	bls.n	8002e90 <HAL_RCC_ClockConfig+0x44>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8002e6e:	4b72      	ldr	r3, [pc, #456]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002e70:	681b      	ldr	r3, [r3, #0]
 8002e72:	f023 0207 	bic.w	r2, r3, #7
 8002e76:	4970      	ldr	r1, [pc, #448]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002e78:	683b      	ldr	r3, [r7, #0]
 8002e7a:	4313      	orrs	r3, r2
 8002e7c:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8002e7e:	4b6e      	ldr	r3, [pc, #440]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002e80:	681b      	ldr	r3, [r3, #0]
 8002e82:	f003 0307 	and.w	r3, r3, #7
 8002e86:	683a      	ldr	r2, [r7, #0]
 8002e88:	429a      	cmp	r2, r3
 8002e8a:	d001      	beq.n	8002e90 <HAL_RCC_ClockConfig+0x44>
    {
      return HAL_ERROR;
 8002e8c:	2301      	movs	r3, #1
 8002e8e:	e0cf      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
    }
  }

  /*----------------- HCLK Configuration prior to SYSCLK----------------------*/
  /* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8002e90:	687b      	ldr	r3, [r7, #4]
 8002e92:	681b      	ldr	r3, [r3, #0]
 8002e94:	f003 0302 	and.w	r3, r3, #2
 8002e98:	2b00      	cmp	r3, #0
 8002e9a:	d010      	beq.n	8002ebe <HAL_RCC_ClockConfig+0x72>
  {
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));

    if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
 8002e9c:	687b      	ldr	r3, [r7, #4]
 8002e9e:	689a      	ldr	r2, [r3, #8]
 8002ea0:	4b66      	ldr	r3, [pc, #408]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002ea2:	689b      	ldr	r3, [r3, #8]
 8002ea4:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 8002ea8:	429a      	cmp	r2, r3
 8002eaa:	d908      	bls.n	8002ebe <HAL_RCC_ClockConfig+0x72>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8002eac:	4b63      	ldr	r3, [pc, #396]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002eae:	689b      	ldr	r3, [r3, #8]
 8002eb0:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8002eb4:	687b      	ldr	r3, [r7, #4]
 8002eb6:	689b      	ldr	r3, [r3, #8]
 8002eb8:	4960      	ldr	r1, [pc, #384]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002eba:	4313      	orrs	r3, r2
 8002ebc:	608b      	str	r3, [r1, #8]
    }
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8002ebe:	687b      	ldr	r3, [r7, #4]
 8002ec0:	681b      	ldr	r3, [r3, #0]
 8002ec2:	f003 0301 	and.w	r3, r3, #1
 8002ec6:	2b00      	cmp	r3, #0
 8002ec8:	d04c      	beq.n	8002f64 <HAL_RCC_ClockConfig+0x118>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* PLL is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8002eca:	687b      	ldr	r3, [r7, #4]
 8002ecc:	685b      	ldr	r3, [r3, #4]
 8002ece:	2b03      	cmp	r3, #3
 8002ed0:	d107      	bne.n	8002ee2 <HAL_RCC_ClockConfig+0x96>
    {
      /* Check the PLL ready flag */
      if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8002ed2:	4b5a      	ldr	r3, [pc, #360]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002ed4:	681b      	ldr	r3, [r3, #0]
 8002ed6:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8002eda:	2b00      	cmp	r3, #0
 8002edc:	d121      	bne.n	8002f22 <HAL_RCC_ClockConfig+0xd6>
      {
        return HAL_ERROR;
 8002ede:	2301      	movs	r3, #1
 8002ee0:	e0a6      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
#endif
    }
    else
    {
      /* HSE is selected as System Clock Source */
      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8002ee2:	687b      	ldr	r3, [r7, #4]
 8002ee4:	685b      	ldr	r3, [r3, #4]
 8002ee6:	2b02      	cmp	r3, #2
 8002ee8:	d107      	bne.n	8002efa <HAL_RCC_ClockConfig+0xae>
      {
        /* Check the HSE ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8002eea:	4b54      	ldr	r3, [pc, #336]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002eec:	681b      	ldr	r3, [r3, #0]
 8002eee:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8002ef2:	2b00      	cmp	r3, #0
 8002ef4:	d115      	bne.n	8002f22 <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8002ef6:	2301      	movs	r3, #1
 8002ef8:	e09a      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
        }
      }
      /* MSI is selected as System Clock Source */
      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
 8002efa:	687b      	ldr	r3, [r7, #4]
 8002efc:	685b      	ldr	r3, [r3, #4]
 8002efe:	2b00      	cmp	r3, #0
 8002f00:	d107      	bne.n	8002f12 <HAL_RCC_ClockConfig+0xc6>
      {
        /* Check the MSI ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 8002f02:	4b4e      	ldr	r3, [pc, #312]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f04:	681b      	ldr	r3, [r3, #0]
 8002f06:	f003 0302 	and.w	r3, r3, #2
 8002f0a:	2b00      	cmp	r3, #0
 8002f0c:	d109      	bne.n	8002f22 <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8002f0e:	2301      	movs	r3, #1
 8002f10:	e08e      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
      }
      /* HSI is selected as System Clock Source */
      else
      {
        /* Check the HSI ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8002f12:	4b4a      	ldr	r3, [pc, #296]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f14:	681b      	ldr	r3, [r3, #0]
 8002f16:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8002f1a:	2b00      	cmp	r3, #0
 8002f1c:	d101      	bne.n	8002f22 <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8002f1e:	2301      	movs	r3, #1
 8002f20:	e086      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
      }
#endif

    }

    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8002f22:	4b46      	ldr	r3, [pc, #280]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f24:	689b      	ldr	r3, [r3, #8]
 8002f26:	f023 0203 	bic.w	r2, r3, #3
 8002f2a:	687b      	ldr	r3, [r7, #4]
 8002f2c:	685b      	ldr	r3, [r3, #4]
 8002f2e:	4943      	ldr	r1, [pc, #268]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f30:	4313      	orrs	r3, r2
 8002f32:	608b      	str	r3, [r1, #8]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8002f34:	f7fe fb86 	bl	8001644 <HAL_GetTick>
 8002f38:	60f8      	str	r0, [r7, #12]

    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8002f3a:	e00a      	b.n	8002f52 <HAL_RCC_ClockConfig+0x106>
    {
      if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8002f3c:	f7fe fb82 	bl	8001644 <HAL_GetTick>
 8002f40:	4602      	mov	r2, r0
 8002f42:	68fb      	ldr	r3, [r7, #12]
 8002f44:	1ad3      	subs	r3, r2, r3
 8002f46:	f241 3288 	movw	r2, #5000	@ 0x1388
 8002f4a:	4293      	cmp	r3, r2
 8002f4c:	d901      	bls.n	8002f52 <HAL_RCC_ClockConfig+0x106>
      {
        return HAL_TIMEOUT;
 8002f4e:	2303      	movs	r3, #3
 8002f50:	e06e      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8002f52:	4b3a      	ldr	r3, [pc, #232]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f54:	689b      	ldr	r3, [r3, #8]
 8002f56:	f003 020c 	and.w	r2, r3, #12
 8002f5a:	687b      	ldr	r3, [r7, #4]
 8002f5c:	685b      	ldr	r3, [r3, #4]
 8002f5e:	009b      	lsls	r3, r3, #2
 8002f60:	429a      	cmp	r2, r3
 8002f62:	d1eb      	bne.n	8002f3c <HAL_RCC_ClockConfig+0xf0>
  }
#endif

  /*----------------- HCLK Configuration after SYSCLK-------------------------*/
  /* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8002f64:	687b      	ldr	r3, [r7, #4]
 8002f66:	681b      	ldr	r3, [r3, #0]
 8002f68:	f003 0302 	and.w	r3, r3, #2
 8002f6c:	2b00      	cmp	r3, #0
 8002f6e:	d010      	beq.n	8002f92 <HAL_RCC_ClockConfig+0x146>
  {
    if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
 8002f70:	687b      	ldr	r3, [r7, #4]
 8002f72:	689a      	ldr	r2, [r3, #8]
 8002f74:	4b31      	ldr	r3, [pc, #196]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f76:	689b      	ldr	r3, [r3, #8]
 8002f78:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 8002f7c:	429a      	cmp	r2, r3
 8002f7e:	d208      	bcs.n	8002f92 <HAL_RCC_ClockConfig+0x146>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8002f80:	4b2e      	ldr	r3, [pc, #184]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f82:	689b      	ldr	r3, [r3, #8]
 8002f84:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8002f88:	687b      	ldr	r3, [r7, #4]
 8002f8a:	689b      	ldr	r3, [r3, #8]
 8002f8c:	492b      	ldr	r1, [pc, #172]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002f8e:	4313      	orrs	r3, r2
 8002f90:	608b      	str	r3, [r1, #8]
    }
  }

  /* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8002f92:	4b29      	ldr	r3, [pc, #164]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002f94:	681b      	ldr	r3, [r3, #0]
 8002f96:	f003 0307 	and.w	r3, r3, #7
 8002f9a:	683a      	ldr	r2, [r7, #0]
 8002f9c:	429a      	cmp	r2, r3
 8002f9e:	d210      	bcs.n	8002fc2 <HAL_RCC_ClockConfig+0x176>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8002fa0:	4b25      	ldr	r3, [pc, #148]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002fa2:	681b      	ldr	r3, [r3, #0]
 8002fa4:	f023 0207 	bic.w	r2, r3, #7
 8002fa8:	4923      	ldr	r1, [pc, #140]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002faa:	683b      	ldr	r3, [r7, #0]
 8002fac:	4313      	orrs	r3, r2
 8002fae:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8002fb0:	4b21      	ldr	r3, [pc, #132]	@ (8003038 <HAL_RCC_ClockConfig+0x1ec>)
 8002fb2:	681b      	ldr	r3, [r3, #0]
 8002fb4:	f003 0307 	and.w	r3, r3, #7
 8002fb8:	683a      	ldr	r2, [r7, #0]
 8002fba:	429a      	cmp	r2, r3
 8002fbc:	d001      	beq.n	8002fc2 <HAL_RCC_ClockConfig+0x176>
    {
      return HAL_ERROR;
 8002fbe:	2301      	movs	r3, #1
 8002fc0:	e036      	b.n	8003030 <HAL_RCC_ClockConfig+0x1e4>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8002fc2:	687b      	ldr	r3, [r7, #4]
 8002fc4:	681b      	ldr	r3, [r3, #0]
 8002fc6:	f003 0304 	and.w	r3, r3, #4
 8002fca:	2b00      	cmp	r3, #0
 8002fcc:	d008      	beq.n	8002fe0 <HAL_RCC_ClockConfig+0x194>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8002fce:	4b1b      	ldr	r3, [pc, #108]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002fd0:	689b      	ldr	r3, [r3, #8]
 8002fd2:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
 8002fd6:	687b      	ldr	r3, [r7, #4]
 8002fd8:	68db      	ldr	r3, [r3, #12]
 8002fda:	4918      	ldr	r1, [pc, #96]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002fdc:	4313      	orrs	r3, r2
 8002fde:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8002fe0:	687b      	ldr	r3, [r7, #4]
 8002fe2:	681b      	ldr	r3, [r3, #0]
 8002fe4:	f003 0308 	and.w	r3, r3, #8
 8002fe8:	2b00      	cmp	r3, #0
 8002fea:	d009      	beq.n	8003000 <HAL_RCC_ClockConfig+0x1b4>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8002fec:	4b13      	ldr	r3, [pc, #76]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002fee:	689b      	ldr	r3, [r3, #8]
 8002ff0:	f423 5260 	bic.w	r2, r3, #14336	@ 0x3800
 8002ff4:	687b      	ldr	r3, [r7, #4]
 8002ff6:	691b      	ldr	r3, [r3, #16]
 8002ff8:	00db      	lsls	r3, r3, #3
 8002ffa:	4910      	ldr	r1, [pc, #64]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8002ffc:	4313      	orrs	r3, r2
 8002ffe:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 8003000:	f000 f824 	bl	800304c <HAL_RCC_GetSysClockFreq>
 8003004:	4602      	mov	r2, r0
 8003006:	4b0d      	ldr	r3, [pc, #52]	@ (800303c <HAL_RCC_ClockConfig+0x1f0>)
 8003008:	689b      	ldr	r3, [r3, #8]
 800300a:	091b      	lsrs	r3, r3, #4
 800300c:	f003 030f 	and.w	r3, r3, #15
 8003010:	490b      	ldr	r1, [pc, #44]	@ (8003040 <HAL_RCC_ClockConfig+0x1f4>)
 8003012:	5ccb      	ldrb	r3, [r1, r3]
 8003014:	f003 031f 	and.w	r3, r3, #31
 8003018:	fa22 f303 	lsr.w	r3, r2, r3
 800301c:	4a09      	ldr	r2, [pc, #36]	@ (8003044 <HAL_RCC_ClockConfig+0x1f8>)
 800301e:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings*/
  status = HAL_InitTick(uwTickPrio);
 8003020:	4b09      	ldr	r3, [pc, #36]	@ (8003048 <HAL_RCC_ClockConfig+0x1fc>)
 8003022:	681b      	ldr	r3, [r3, #0]
 8003024:	4618      	mov	r0, r3
 8003026:	f7fe f9df 	bl	80013e8 <HAL_InitTick>
 800302a:	4603      	mov	r3, r0
 800302c:	72fb      	strb	r3, [r7, #11]

  return status;
 800302e:	7afb      	ldrb	r3, [r7, #11]
}
 8003030:	4618      	mov	r0, r3
 8003032:	3710      	adds	r7, #16
 8003034:	46bd      	mov	sp, r7
 8003036:	bd80      	pop	{r7, pc}
 8003038:	40022000 	.word	0x40022000
 800303c:	40021000 	.word	0x40021000
 8003040:	080095c8 	.word	0x080095c8
 8003044:	20000000 	.word	0x20000000
 8003048:	20000004 	.word	0x20000004

0800304c <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 800304c:	b480      	push	{r7}
 800304e:	b089      	sub	sp, #36	@ 0x24
 8003050:	af00      	add	r7, sp, #0
  uint32_t msirange = 0U, sysclockfreq = 0U;
 8003052:	2300      	movs	r3, #0
 8003054:	61fb      	str	r3, [r7, #28]
 8003056:	2300      	movs	r3, #0
 8003058:	61bb      	str	r3, [r7, #24]
  uint32_t pllvco, pllsource, pllr, pllm;    /* no init needed */
  uint32_t sysclk_source, pll_oscsource;

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 800305a:	4b3e      	ldr	r3, [pc, #248]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 800305c:	689b      	ldr	r3, [r3, #8]
 800305e:	f003 030c 	and.w	r3, r3, #12
 8003062:	613b      	str	r3, [r7, #16]
  pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
 8003064:	4b3b      	ldr	r3, [pc, #236]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 8003066:	68db      	ldr	r3, [r3, #12]
 8003068:	f003 0303 	and.w	r3, r3, #3
 800306c:	60fb      	str	r3, [r7, #12]

  if((sysclk_source == RCC_CFGR_SWS_MSI) ||
 800306e:	693b      	ldr	r3, [r7, #16]
 8003070:	2b00      	cmp	r3, #0
 8003072:	d005      	beq.n	8003080 <HAL_RCC_GetSysClockFreq+0x34>
 8003074:	693b      	ldr	r3, [r7, #16]
 8003076:	2b0c      	cmp	r3, #12
 8003078:	d121      	bne.n	80030be <HAL_RCC_GetSysClockFreq+0x72>
     ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
 800307a:	68fb      	ldr	r3, [r7, #12]
 800307c:	2b01      	cmp	r3, #1
 800307e:	d11e      	bne.n	80030be <HAL_RCC_GetSysClockFreq+0x72>
  {
    /* MSI or PLL with MSI source used as system clock source */

    /* Get SYSCLK source */
    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
 8003080:	4b34      	ldr	r3, [pc, #208]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 8003082:	681b      	ldr	r3, [r3, #0]
 8003084:	f003 0308 	and.w	r3, r3, #8
 8003088:	2b00      	cmp	r3, #0
 800308a:	d107      	bne.n	800309c <HAL_RCC_GetSysClockFreq+0x50>
    { /* MSISRANGE from RCC_CSR applies */
      msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
 800308c:	4b31      	ldr	r3, [pc, #196]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 800308e:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8003092:	0a1b      	lsrs	r3, r3, #8
 8003094:	f003 030f 	and.w	r3, r3, #15
 8003098:	61fb      	str	r3, [r7, #28]
 800309a:	e005      	b.n	80030a8 <HAL_RCC_GetSysClockFreq+0x5c>
    }
    else
    { /* MSIRANGE from RCC_CR applies */
      msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
 800309c:	4b2d      	ldr	r3, [pc, #180]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 800309e:	681b      	ldr	r3, [r3, #0]
 80030a0:	091b      	lsrs	r3, r3, #4
 80030a2:	f003 030f 	and.w	r3, r3, #15
 80030a6:	61fb      	str	r3, [r7, #28]
    }
    /*MSI frequency range in HZ*/
    msirange = MSIRangeTable[msirange];
 80030a8:	4a2b      	ldr	r2, [pc, #172]	@ (8003158 <HAL_RCC_GetSysClockFreq+0x10c>)
 80030aa:	69fb      	ldr	r3, [r7, #28]
 80030ac:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 80030b0:	61fb      	str	r3, [r7, #28]

    if(sysclk_source == RCC_CFGR_SWS_MSI)
 80030b2:	693b      	ldr	r3, [r7, #16]
 80030b4:	2b00      	cmp	r3, #0
 80030b6:	d10d      	bne.n	80030d4 <HAL_RCC_GetSysClockFreq+0x88>
    {
      /* MSI used as system clock source */
      sysclockfreq = msirange;
 80030b8:	69fb      	ldr	r3, [r7, #28]
 80030ba:	61bb      	str	r3, [r7, #24]
    if(sysclk_source == RCC_CFGR_SWS_MSI)
 80030bc:	e00a      	b.n	80030d4 <HAL_RCC_GetSysClockFreq+0x88>
    }
  }
  else if(sysclk_source == RCC_CFGR_SWS_HSI)
 80030be:	693b      	ldr	r3, [r7, #16]
 80030c0:	2b04      	cmp	r3, #4
 80030c2:	d102      	bne.n	80030ca <HAL_RCC_GetSysClockFreq+0x7e>
  {
    /* HSI used as system clock source */
    sysclockfreq = HSI_VALUE;
 80030c4:	4b25      	ldr	r3, [pc, #148]	@ (800315c <HAL_RCC_GetSysClockFreq+0x110>)
 80030c6:	61bb      	str	r3, [r7, #24]
 80030c8:	e004      	b.n	80030d4 <HAL_RCC_GetSysClockFreq+0x88>
  }
  else if(sysclk_source == RCC_CFGR_SWS_HSE)
 80030ca:	693b      	ldr	r3, [r7, #16]
 80030cc:	2b08      	cmp	r3, #8
 80030ce:	d101      	bne.n	80030d4 <HAL_RCC_GetSysClockFreq+0x88>
  {
    /* HSE used as system clock source */
    sysclockfreq = HSE_VALUE;
 80030d0:	4b23      	ldr	r3, [pc, #140]	@ (8003160 <HAL_RCC_GetSysClockFreq+0x114>)
 80030d2:	61bb      	str	r3, [r7, #24]
  else
  {
    /* unexpected case: sysclockfreq at 0 */
  }

  if(sysclk_source == RCC_CFGR_SWS_PLL)
 80030d4:	693b      	ldr	r3, [r7, #16]
 80030d6:	2b0c      	cmp	r3, #12
 80030d8:	d134      	bne.n	8003144 <HAL_RCC_GetSysClockFreq+0xf8>
    /* PLL used as system clock  source */

    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
    SYSCLK = PLL_VCO / PLLR
    */
    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
 80030da:	4b1e      	ldr	r3, [pc, #120]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 80030dc:	68db      	ldr	r3, [r3, #12]
 80030de:	f003 0303 	and.w	r3, r3, #3
 80030e2:	60bb      	str	r3, [r7, #8]

    switch (pllsource)
 80030e4:	68bb      	ldr	r3, [r7, #8]
 80030e6:	2b02      	cmp	r3, #2
 80030e8:	d003      	beq.n	80030f2 <HAL_RCC_GetSysClockFreq+0xa6>
 80030ea:	68bb      	ldr	r3, [r7, #8]
 80030ec:	2b03      	cmp	r3, #3
 80030ee:	d003      	beq.n	80030f8 <HAL_RCC_GetSysClockFreq+0xac>
 80030f0:	e005      	b.n	80030fe <HAL_RCC_GetSysClockFreq+0xb2>
    {
    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
      pllvco = HSI_VALUE;
 80030f2:	4b1a      	ldr	r3, [pc, #104]	@ (800315c <HAL_RCC_GetSysClockFreq+0x110>)
 80030f4:	617b      	str	r3, [r7, #20]
      break;
 80030f6:	e005      	b.n	8003104 <HAL_RCC_GetSysClockFreq+0xb8>

    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
      pllvco = HSE_VALUE;
 80030f8:	4b19      	ldr	r3, [pc, #100]	@ (8003160 <HAL_RCC_GetSysClockFreq+0x114>)
 80030fa:	617b      	str	r3, [r7, #20]
      break;
 80030fc:	e002      	b.n	8003104 <HAL_RCC_GetSysClockFreq+0xb8>

    case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
    default:
      pllvco = msirange;
 80030fe:	69fb      	ldr	r3, [r7, #28]
 8003100:	617b      	str	r3, [r7, #20]
      break;
 8003102:	bf00      	nop
    }
    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 8003104:	4b13      	ldr	r3, [pc, #76]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 8003106:	68db      	ldr	r3, [r3, #12]
 8003108:	091b      	lsrs	r3, r3, #4
 800310a:	f003 0307 	and.w	r3, r3, #7
 800310e:	3301      	adds	r3, #1
 8003110:	607b      	str	r3, [r7, #4]
    pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
 8003112:	4b10      	ldr	r3, [pc, #64]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 8003114:	68db      	ldr	r3, [r3, #12]
 8003116:	0a1b      	lsrs	r3, r3, #8
 8003118:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800311c:	697a      	ldr	r2, [r7, #20]
 800311e:	fb03 f202 	mul.w	r2, r3, r2
 8003122:	687b      	ldr	r3, [r7, #4]
 8003124:	fbb2 f3f3 	udiv	r3, r2, r3
 8003128:	617b      	str	r3, [r7, #20]
    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 800312a:	4b0a      	ldr	r3, [pc, #40]	@ (8003154 <HAL_RCC_GetSysClockFreq+0x108>)
 800312c:	68db      	ldr	r3, [r3, #12]
 800312e:	0e5b      	lsrs	r3, r3, #25
 8003130:	f003 0303 	and.w	r3, r3, #3
 8003134:	3301      	adds	r3, #1
 8003136:	005b      	lsls	r3, r3, #1
 8003138:	603b      	str	r3, [r7, #0]
    sysclockfreq = pllvco / pllr;
 800313a:	697a      	ldr	r2, [r7, #20]
 800313c:	683b      	ldr	r3, [r7, #0]
 800313e:	fbb2 f3f3 	udiv	r3, r2, r3
 8003142:	61bb      	str	r3, [r7, #24]
  }

  return sysclockfreq;
 8003144:	69bb      	ldr	r3, [r7, #24]
}
 8003146:	4618      	mov	r0, r3
 8003148:	3724      	adds	r7, #36	@ 0x24
 800314a:	46bd      	mov	sp, r7
 800314c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003150:	4770      	bx	lr
 8003152:	bf00      	nop
 8003154:	40021000 	.word	0x40021000
 8003158:	080095e0 	.word	0x080095e0
 800315c:	00f42400 	.word	0x00f42400
 8003160:	007a1200 	.word	0x007a1200

08003164 <HAL_RCC_GetHCLKFreq>:
  *
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
  * @retval HCLK frequency in Hz
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 8003164:	b480      	push	{r7}
 8003166:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 8003168:	4b03      	ldr	r3, [pc, #12]	@ (8003178 <HAL_RCC_GetHCLKFreq+0x14>)
 800316a:	681b      	ldr	r3, [r3, #0]
}
 800316c:	4618      	mov	r0, r3
 800316e:	46bd      	mov	sp, r7
 8003170:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003174:	4770      	bx	lr
 8003176:	bf00      	nop
 8003178:	20000000 	.word	0x20000000

0800317c <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency in Hz
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 800317c:	b580      	push	{r7, lr}
 800317e:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
 8003180:	f7ff fff0 	bl	8003164 <HAL_RCC_GetHCLKFreq>
 8003184:	4602      	mov	r2, r0
 8003186:	4b06      	ldr	r3, [pc, #24]	@ (80031a0 <HAL_RCC_GetPCLK1Freq+0x24>)
 8003188:	689b      	ldr	r3, [r3, #8]
 800318a:	0a1b      	lsrs	r3, r3, #8
 800318c:	f003 0307 	and.w	r3, r3, #7
 8003190:	4904      	ldr	r1, [pc, #16]	@ (80031a4 <HAL_RCC_GetPCLK1Freq+0x28>)
 8003192:	5ccb      	ldrb	r3, [r1, r3]
 8003194:	f003 031f 	and.w	r3, r3, #31
 8003198:	fa22 f303 	lsr.w	r3, r2, r3
}
 800319c:	4618      	mov	r0, r3
 800319e:	bd80      	pop	{r7, pc}
 80031a0:	40021000 	.word	0x40021000
 80031a4:	080095d8 	.word	0x080095d8

080031a8 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency in Hz
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 80031a8:	b580      	push	{r7, lr}
 80031aa:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
 80031ac:	f7ff ffda 	bl	8003164 <HAL_RCC_GetHCLKFreq>
 80031b0:	4602      	mov	r2, r0
 80031b2:	4b06      	ldr	r3, [pc, #24]	@ (80031cc <HAL_RCC_GetPCLK2Freq+0x24>)
 80031b4:	689b      	ldr	r3, [r3, #8]
 80031b6:	0adb      	lsrs	r3, r3, #11
 80031b8:	f003 0307 	and.w	r3, r3, #7
 80031bc:	4904      	ldr	r1, [pc, #16]	@ (80031d0 <HAL_RCC_GetPCLK2Freq+0x28>)
 80031be:	5ccb      	ldrb	r3, [r1, r3]
 80031c0:	f003 031f 	and.w	r3, r3, #31
 80031c4:	fa22 f303 	lsr.w	r3, r2, r3
}
 80031c8:	4618      	mov	r0, r3
 80031ca:	bd80      	pop	{r7, pc}
 80031cc:	40021000 	.word	0x40021000
 80031d0:	080095d8 	.word	0x080095d8

080031d4 <HAL_RCC_GetClockConfig>:
  *         will be configured.
  * @param  pFLatency  Pointer on the Flash Latency.
  * @retval None
  */
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
{
 80031d4:	b480      	push	{r7}
 80031d6:	b083      	sub	sp, #12
 80031d8:	af00      	add	r7, sp, #0
 80031da:	6078      	str	r0, [r7, #4]
 80031dc:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(RCC_ClkInitStruct != (void  *)NULL);
  assert_param(pFLatency != (void *)NULL);

  /* Set all possible values for the Clock type parameter --------------------*/
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 80031de:	687b      	ldr	r3, [r7, #4]
 80031e0:	220f      	movs	r2, #15
 80031e2:	601a      	str	r2, [r3, #0]

  /* Get the SYSCLK configuration --------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
 80031e4:	4b12      	ldr	r3, [pc, #72]	@ (8003230 <HAL_RCC_GetClockConfig+0x5c>)
 80031e6:	689b      	ldr	r3, [r3, #8]
 80031e8:	f003 0203 	and.w	r2, r3, #3
 80031ec:	687b      	ldr	r3, [r7, #4]
 80031ee:	605a      	str	r2, [r3, #4]

  /* Get the HCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
 80031f0:	4b0f      	ldr	r3, [pc, #60]	@ (8003230 <HAL_RCC_GetClockConfig+0x5c>)
 80031f2:	689b      	ldr	r3, [r3, #8]
 80031f4:	f003 02f0 	and.w	r2, r3, #240	@ 0xf0
 80031f8:	687b      	ldr	r3, [r7, #4]
 80031fa:	609a      	str	r2, [r3, #8]

  /* Get the APB1 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
 80031fc:	4b0c      	ldr	r3, [pc, #48]	@ (8003230 <HAL_RCC_GetClockConfig+0x5c>)
 80031fe:	689b      	ldr	r3, [r3, #8]
 8003200:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 8003204:	687b      	ldr	r3, [r7, #4]
 8003206:	60da      	str	r2, [r3, #12]

  /* Get the APB2 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
 8003208:	4b09      	ldr	r3, [pc, #36]	@ (8003230 <HAL_RCC_GetClockConfig+0x5c>)
 800320a:	689b      	ldr	r3, [r3, #8]
 800320c:	08db      	lsrs	r3, r3, #3
 800320e:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 8003212:	687b      	ldr	r3, [r7, #4]
 8003214:	611a      	str	r2, [r3, #16]

  /* Get the Flash Wait State (Latency) configuration ------------------------*/
  *pFLatency = __HAL_FLASH_GET_LATENCY();
 8003216:	4b07      	ldr	r3, [pc, #28]	@ (8003234 <HAL_RCC_GetClockConfig+0x60>)
 8003218:	681b      	ldr	r3, [r3, #0]
 800321a:	f003 0207 	and.w	r2, r3, #7
 800321e:	683b      	ldr	r3, [r7, #0]
 8003220:	601a      	str	r2, [r3, #0]
}
 8003222:	bf00      	nop
 8003224:	370c      	adds	r7, #12
 8003226:	46bd      	mov	sp, r7
 8003228:	f85d 7b04 	ldr.w	r7, [sp], #4
 800322c:	4770      	bx	lr
 800322e:	bf00      	nop
 8003230:	40021000 	.word	0x40021000
 8003234:	40022000 	.word	0x40022000

08003238 <RCC_SetFlashLatencyFromMSIRange>:
            voltage range.
  * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
  * @retval HAL status
  */
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
 8003238:	b580      	push	{r7, lr}
 800323a:	b086      	sub	sp, #24
 800323c:	af00      	add	r7, sp, #0
 800323e:	6078      	str	r0, [r7, #4]
  uint32_t vos;
  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
 8003240:	2300      	movs	r3, #0
 8003242:	613b      	str	r3, [r7, #16]

  if(__HAL_RCC_PWR_IS_CLK_ENABLED())
 8003244:	4b2a      	ldr	r3, [pc, #168]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8003246:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003248:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 800324c:	2b00      	cmp	r3, #0
 800324e:	d003      	beq.n	8003258 <RCC_SetFlashLatencyFromMSIRange+0x20>
  {
    vos = HAL_PWREx_GetVoltageRange();
 8003250:	f7ff f8f0 	bl	8002434 <HAL_PWREx_GetVoltageRange>
 8003254:	6178      	str	r0, [r7, #20]
 8003256:	e014      	b.n	8003282 <RCC_SetFlashLatencyFromMSIRange+0x4a>
  }
  else
  {
    __HAL_RCC_PWR_CLK_ENABLE();
 8003258:	4b25      	ldr	r3, [pc, #148]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800325a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800325c:	4a24      	ldr	r2, [pc, #144]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800325e:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8003262:	6593      	str	r3, [r2, #88]	@ 0x58
 8003264:	4b22      	ldr	r3, [pc, #136]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8003266:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003268:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 800326c:	60fb      	str	r3, [r7, #12]
 800326e:	68fb      	ldr	r3, [r7, #12]
    vos = HAL_PWREx_GetVoltageRange();
 8003270:	f7ff f8e0 	bl	8002434 <HAL_PWREx_GetVoltageRange>
 8003274:	6178      	str	r0, [r7, #20]
    __HAL_RCC_PWR_CLK_DISABLE();
 8003276:	4b1e      	ldr	r3, [pc, #120]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8003278:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800327a:	4a1d      	ldr	r2, [pc, #116]	@ (80032f0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800327c:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8003280:	6593      	str	r3, [r2, #88]	@ 0x58
  }

  if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
 8003282:	697b      	ldr	r3, [r7, #20]
 8003284:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 8003288:	d10b      	bne.n	80032a2 <RCC_SetFlashLatencyFromMSIRange+0x6a>
  {
    if(msirange > RCC_MSIRANGE_8)
 800328a:	687b      	ldr	r3, [r7, #4]
 800328c:	2b80      	cmp	r3, #128	@ 0x80
 800328e:	d919      	bls.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
    {
      /* MSI > 16Mhz */
      if(msirange > RCC_MSIRANGE_10)
 8003290:	687b      	ldr	r3, [r7, #4]
 8003292:	2ba0      	cmp	r3, #160	@ 0xa0
 8003294:	d902      	bls.n	800329c <RCC_SetFlashLatencyFromMSIRange+0x64>
      {
        /* MSI 48Mhz */
        latency = FLASH_LATENCY_2; /* 2WS */
 8003296:	2302      	movs	r3, #2
 8003298:	613b      	str	r3, [r7, #16]
 800329a:	e013      	b.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      }
      else
      {
        /* MSI 24Mhz or 32Mhz */
        latency = FLASH_LATENCY_1; /* 1WS */
 800329c:	2301      	movs	r3, #1
 800329e:	613b      	str	r3, [r7, #16]
 80032a0:	e010      	b.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
        latency = FLASH_LATENCY_1; /* 1WS */
      }
      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
    }
#else
    if(msirange > RCC_MSIRANGE_8)
 80032a2:	687b      	ldr	r3, [r7, #4]
 80032a4:	2b80      	cmp	r3, #128	@ 0x80
 80032a6:	d902      	bls.n	80032ae <RCC_SetFlashLatencyFromMSIRange+0x76>
    {
      /* MSI > 16Mhz */
      latency = FLASH_LATENCY_3; /* 3WS */
 80032a8:	2303      	movs	r3, #3
 80032aa:	613b      	str	r3, [r7, #16]
 80032ac:	e00a      	b.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
    }
    else
    {
      if(msirange == RCC_MSIRANGE_8)
 80032ae:	687b      	ldr	r3, [r7, #4]
 80032b0:	2b80      	cmp	r3, #128	@ 0x80
 80032b2:	d102      	bne.n	80032ba <RCC_SetFlashLatencyFromMSIRange+0x82>
      {
        /* MSI 16Mhz */
        latency = FLASH_LATENCY_2; /* 2WS */
 80032b4:	2302      	movs	r3, #2
 80032b6:	613b      	str	r3, [r7, #16]
 80032b8:	e004      	b.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      }
      else if(msirange == RCC_MSIRANGE_7)
 80032ba:	687b      	ldr	r3, [r7, #4]
 80032bc:	2b70      	cmp	r3, #112	@ 0x70
 80032be:	d101      	bne.n	80032c4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      {
        /* MSI 8Mhz */
        latency = FLASH_LATENCY_1; /* 1WS */
 80032c0:	2301      	movs	r3, #1
 80032c2:	613b      	str	r3, [r7, #16]
      }
    }
#endif
  }

  __HAL_FLASH_SET_LATENCY(latency);
 80032c4:	4b0b      	ldr	r3, [pc, #44]	@ (80032f4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80032c6:	681b      	ldr	r3, [r3, #0]
 80032c8:	f023 0207 	bic.w	r2, r3, #7
 80032cc:	4909      	ldr	r1, [pc, #36]	@ (80032f4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80032ce:	693b      	ldr	r3, [r7, #16]
 80032d0:	4313      	orrs	r3, r2
 80032d2:	600b      	str	r3, [r1, #0]

  /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
  if(__HAL_FLASH_GET_LATENCY() != latency)
 80032d4:	4b07      	ldr	r3, [pc, #28]	@ (80032f4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80032d6:	681b      	ldr	r3, [r3, #0]
 80032d8:	f003 0307 	and.w	r3, r3, #7
 80032dc:	693a      	ldr	r2, [r7, #16]
 80032de:	429a      	cmp	r2, r3
 80032e0:	d001      	beq.n	80032e6 <RCC_SetFlashLatencyFromMSIRange+0xae>
  {
    return HAL_ERROR;
 80032e2:	2301      	movs	r3, #1
 80032e4:	e000      	b.n	80032e8 <RCC_SetFlashLatencyFromMSIRange+0xb0>
  }

  return HAL_OK;
 80032e6:	2300      	movs	r3, #0
}
 80032e8:	4618      	mov	r0, r3
 80032ea:	3718      	adds	r7, #24
 80032ec:	46bd      	mov	sp, r7
 80032ee:	bd80      	pop	{r7, pc}
 80032f0:	40021000 	.word	0x40021000
 80032f4:	40022000 	.word	0x40022000

080032f8 <HAL_RCCEx_PeriphCLKConfig>:
  *         the RTC clock source: in this case the access to Backup domain is enabled.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 80032f8:	b580      	push	{r7, lr}
 80032fa:	b086      	sub	sp, #24
 80032fc:	af00      	add	r7, sp, #0
 80032fe:	6078      	str	r0, [r7, #4]
  uint32_t tmpregister, tickstart;     /* no init needed */
  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
 8003300:	2300      	movs	r3, #0
 8003302:	74fb      	strb	r3, [r7, #19]
  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
 8003304:	2300      	movs	r3, #0
 8003306:	74bb      	strb	r3, [r7, #18]
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

#if defined(SAI1)

  /*-------------------------- SAI1 clock source configuration ---------------------*/
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
 8003308:	687b      	ldr	r3, [r7, #4]
 800330a:	681b      	ldr	r3, [r3, #0]
 800330c:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 8003310:	2b00      	cmp	r3, #0
 8003312:	d041      	beq.n	8003398 <HAL_RCCEx_PeriphCLKConfig+0xa0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));

    switch(PeriphClkInit->Sai1ClockSelection)
 8003314:	687b      	ldr	r3, [r7, #4]
 8003316:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8003318:	f5b3 0f40 	cmp.w	r3, #12582912	@ 0xc00000
 800331c:	d02a      	beq.n	8003374 <HAL_RCCEx_PeriphCLKConfig+0x7c>
 800331e:	f5b3 0f40 	cmp.w	r3, #12582912	@ 0xc00000
 8003322:	d824      	bhi.n	800336e <HAL_RCCEx_PeriphCLKConfig+0x76>
 8003324:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 8003328:	d008      	beq.n	800333c <HAL_RCCEx_PeriphCLKConfig+0x44>
 800332a:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800332e:	d81e      	bhi.n	800336e <HAL_RCCEx_PeriphCLKConfig+0x76>
 8003330:	2b00      	cmp	r3, #0
 8003332:	d00a      	beq.n	800334a <HAL_RCCEx_PeriphCLKConfig+0x52>
 8003334:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 8003338:	d010      	beq.n	800335c <HAL_RCCEx_PeriphCLKConfig+0x64>
 800333a:	e018      	b.n	800336e <HAL_RCCEx_PeriphCLKConfig+0x76>
    {
    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
      /* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
 800333c:	4b86      	ldr	r3, [pc, #536]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800333e:	68db      	ldr	r3, [r3, #12]
 8003340:	4a85      	ldr	r2, [pc, #532]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003342:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8003346:	60d3      	str	r3, [r2, #12]
#else
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
      /* SAI1 clock source config set later after clock selection check */
      break;
 8003348:	e015      	b.n	8003376 <HAL_RCCEx_PeriphCLKConfig+0x7e>

    case RCC_SAI1CLKSOURCE_PLLSAI1:  /* PLLSAI1 is used as clock source for SAI1*/
      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
 800334a:	687b      	ldr	r3, [r7, #4]
 800334c:	3304      	adds	r3, #4
 800334e:	2100      	movs	r1, #0
 8003350:	4618      	mov	r0, r3
 8003352:	f000 facb 	bl	80038ec <RCCEx_PLLSAI1_Config>
 8003356:	4603      	mov	r3, r0
 8003358:	74fb      	strb	r3, [r7, #19]
      /* SAI1 clock source config set later after clock selection check */
      break;
 800335a:	e00c      	b.n	8003376 <HAL_RCCEx_PeriphCLKConfig+0x7e>

#if defined(RCC_PLLSAI2_SUPPORT)

    case RCC_SAI1CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI1*/
      /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
 800335c:	687b      	ldr	r3, [r7, #4]
 800335e:	3320      	adds	r3, #32
 8003360:	2100      	movs	r1, #0
 8003362:	4618      	mov	r0, r3
 8003364:	f000 fbb6 	bl	8003ad4 <RCCEx_PLLSAI2_Config>
 8003368:	4603      	mov	r3, r0
 800336a:	74fb      	strb	r3, [r7, #19]
      /* SAI1 clock source config set later after clock selection check */
      break;
 800336c:	e003      	b.n	8003376 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
      /* SAI1 clock source config set later after clock selection check */
      break;

    default:
      ret = HAL_ERROR;
 800336e:	2301      	movs	r3, #1
 8003370:	74fb      	strb	r3, [r7, #19]
      break;
 8003372:	e000      	b.n	8003376 <HAL_RCCEx_PeriphCLKConfig+0x7e>
      break;
 8003374:	bf00      	nop
    }

    if(ret == HAL_OK)
 8003376:	7cfb      	ldrb	r3, [r7, #19]
 8003378:	2b00      	cmp	r3, #0
 800337a:	d10b      	bne.n	8003394 <HAL_RCCEx_PeriphCLKConfig+0x9c>
    {
      /* Set the source of SAI1 clock*/
      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
 800337c:	4b76      	ldr	r3, [pc, #472]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800337e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003382:	f423 0240 	bic.w	r2, r3, #12582912	@ 0xc00000
 8003386:	687b      	ldr	r3, [r7, #4]
 8003388:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 800338a:	4973      	ldr	r1, [pc, #460]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800338c:	4313      	orrs	r3, r2
 800338e:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
 8003392:	e001      	b.n	8003398 <HAL_RCCEx_PeriphCLKConfig+0xa0>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8003394:	7cfb      	ldrb	r3, [r7, #19]
 8003396:	74bb      	strb	r3, [r7, #18]
#endif /* SAI1 */

#if defined(SAI2)

  /*-------------------------- SAI2 clock source configuration ---------------------*/
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
 8003398:	687b      	ldr	r3, [r7, #4]
 800339a:	681b      	ldr	r3, [r3, #0]
 800339c:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 80033a0:	2b00      	cmp	r3, #0
 80033a2:	d041      	beq.n	8003428 <HAL_RCCEx_PeriphCLKConfig+0x130>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));

    switch(PeriphClkInit->Sai2ClockSelection)
 80033a4:	687b      	ldr	r3, [r7, #4]
 80033a6:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 80033a8:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 80033ac:	d02a      	beq.n	8003404 <HAL_RCCEx_PeriphCLKConfig+0x10c>
 80033ae:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 80033b2:	d824      	bhi.n	80033fe <HAL_RCCEx_PeriphCLKConfig+0x106>
 80033b4:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 80033b8:	d008      	beq.n	80033cc <HAL_RCCEx_PeriphCLKConfig+0xd4>
 80033ba:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 80033be:	d81e      	bhi.n	80033fe <HAL_RCCEx_PeriphCLKConfig+0x106>
 80033c0:	2b00      	cmp	r3, #0
 80033c2:	d00a      	beq.n	80033da <HAL_RCCEx_PeriphCLKConfig+0xe2>
 80033c4:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 80033c8:	d010      	beq.n	80033ec <HAL_RCCEx_PeriphCLKConfig+0xf4>
 80033ca:	e018      	b.n	80033fe <HAL_RCCEx_PeriphCLKConfig+0x106>
    {
    case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
      /* Enable SAI Clock output generated from System PLL . */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
 80033cc:	4b62      	ldr	r3, [pc, #392]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80033ce:	68db      	ldr	r3, [r3, #12]
 80033d0:	4a61      	ldr	r2, [pc, #388]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80033d2:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80033d6:	60d3      	str	r3, [r2, #12]
      /* SAI2 clock source config set later after clock selection check */
      break;
 80033d8:	e015      	b.n	8003406 <HAL_RCCEx_PeriphCLKConfig+0x10e>

    case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
 80033da:	687b      	ldr	r3, [r7, #4]
 80033dc:	3304      	adds	r3, #4
 80033de:	2100      	movs	r1, #0
 80033e0:	4618      	mov	r0, r3
 80033e2:	f000 fa83 	bl	80038ec <RCCEx_PLLSAI1_Config>
 80033e6:	4603      	mov	r3, r0
 80033e8:	74fb      	strb	r3, [r7, #19]
      /* SAI2 clock source config set later after clock selection check */
      break;
 80033ea:	e00c      	b.n	8003406 <HAL_RCCEx_PeriphCLKConfig+0x10e>

    case RCC_SAI2CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI2*/
      /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
 80033ec:	687b      	ldr	r3, [r7, #4]
 80033ee:	3320      	adds	r3, #32
 80033f0:	2100      	movs	r1, #0
 80033f2:	4618      	mov	r0, r3
 80033f4:	f000 fb6e 	bl	8003ad4 <RCCEx_PLLSAI2_Config>
 80033f8:	4603      	mov	r3, r0
 80033fa:	74fb      	strb	r3, [r7, #19]
      /* SAI2 clock source config set later after clock selection check */
      break;
 80033fc:	e003      	b.n	8003406 <HAL_RCCEx_PeriphCLKConfig+0x10e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
      /* SAI2 clock source config set later after clock selection check */
      break;

    default:
      ret = HAL_ERROR;
 80033fe:	2301      	movs	r3, #1
 8003400:	74fb      	strb	r3, [r7, #19]
      break;
 8003402:	e000      	b.n	8003406 <HAL_RCCEx_PeriphCLKConfig+0x10e>
      break;
 8003404:	bf00      	nop
    }

    if(ret == HAL_OK)
 8003406:	7cfb      	ldrb	r3, [r7, #19]
 8003408:	2b00      	cmp	r3, #0
 800340a:	d10b      	bne.n	8003424 <HAL_RCCEx_PeriphCLKConfig+0x12c>
    {
      /* Set the source of SAI2 clock*/
      __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
 800340c:	4b52      	ldr	r3, [pc, #328]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800340e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003412:	f023 7240 	bic.w	r2, r3, #50331648	@ 0x3000000
 8003416:	687b      	ldr	r3, [r7, #4]
 8003418:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 800341a:	494f      	ldr	r1, [pc, #316]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800341c:	4313      	orrs	r3, r2
 800341e:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
 8003422:	e001      	b.n	8003428 <HAL_RCCEx_PeriphCLKConfig+0x130>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8003424:	7cfb      	ldrb	r3, [r7, #19]
 8003426:	74bb      	strb	r3, [r7, #18]
    }
  }
#endif /* SAI2 */

  /*-------------------------- RTC clock source configuration ----------------------*/
  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 8003428:	687b      	ldr	r3, [r7, #4]
 800342a:	681b      	ldr	r3, [r3, #0]
 800342c:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8003430:	2b00      	cmp	r3, #0
 8003432:	f000 80a0 	beq.w	8003576 <HAL_RCCEx_PeriphCLKConfig+0x27e>
  {
    FlagStatus       pwrclkchanged = RESET;
 8003436:	2300      	movs	r3, #0
 8003438:	747b      	strb	r3, [r7, #17]

    /* Check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    /* Enable Power Clock */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
 800343a:	4b47      	ldr	r3, [pc, #284]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800343c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800343e:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8003442:	2b00      	cmp	r3, #0
 8003444:	d101      	bne.n	800344a <HAL_RCCEx_PeriphCLKConfig+0x152>
 8003446:	2301      	movs	r3, #1
 8003448:	e000      	b.n	800344c <HAL_RCCEx_PeriphCLKConfig+0x154>
 800344a:	2300      	movs	r3, #0
 800344c:	2b00      	cmp	r3, #0
 800344e:	d00d      	beq.n	800346c <HAL_RCCEx_PeriphCLKConfig+0x174>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8003450:	4b41      	ldr	r3, [pc, #260]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003452:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003454:	4a40      	ldr	r2, [pc, #256]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003456:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 800345a:	6593      	str	r3, [r2, #88]	@ 0x58
 800345c:	4b3e      	ldr	r3, [pc, #248]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800345e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003460:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8003464:	60bb      	str	r3, [r7, #8]
 8003466:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8003468:	2301      	movs	r3, #1
 800346a:	747b      	strb	r3, [r7, #17]
    }

    /* Enable write access to Backup domain */
    SET_BIT(PWR->CR1, PWR_CR1_DBP);
 800346c:	4b3b      	ldr	r3, [pc, #236]	@ (800355c <HAL_RCCEx_PeriphCLKConfig+0x264>)
 800346e:	681b      	ldr	r3, [r3, #0]
 8003470:	4a3a      	ldr	r2, [pc, #232]	@ (800355c <HAL_RCCEx_PeriphCLKConfig+0x264>)
 8003472:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8003476:	6013      	str	r3, [r2, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 8003478:	f7fe f8e4 	bl	8001644 <HAL_GetTick>
 800347c:	60f8      	str	r0, [r7, #12]

    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
 800347e:	e009      	b.n	8003494 <HAL_RCCEx_PeriphCLKConfig+0x19c>
    {
      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8003480:	f7fe f8e0 	bl	8001644 <HAL_GetTick>
 8003484:	4602      	mov	r2, r0
 8003486:	68fb      	ldr	r3, [r7, #12]
 8003488:	1ad3      	subs	r3, r2, r3
 800348a:	2b02      	cmp	r3, #2
 800348c:	d902      	bls.n	8003494 <HAL_RCCEx_PeriphCLKConfig+0x19c>
      {
        ret = HAL_TIMEOUT;
 800348e:	2303      	movs	r3, #3
 8003490:	74fb      	strb	r3, [r7, #19]
        break;
 8003492:	e005      	b.n	80034a0 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
 8003494:	4b31      	ldr	r3, [pc, #196]	@ (800355c <HAL_RCCEx_PeriphCLKConfig+0x264>)
 8003496:	681b      	ldr	r3, [r3, #0]
 8003498:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800349c:	2b00      	cmp	r3, #0
 800349e:	d0ef      	beq.n	8003480 <HAL_RCCEx_PeriphCLKConfig+0x188>
      }
    }

    if(ret == HAL_OK)
 80034a0:	7cfb      	ldrb	r3, [r7, #19]
 80034a2:	2b00      	cmp	r3, #0
 80034a4:	d15c      	bne.n	8003560 <HAL_RCCEx_PeriphCLKConfig+0x268>
    {
      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
 80034a6:	4b2c      	ldr	r3, [pc, #176]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034a8:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80034ac:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 80034b0:	617b      	str	r3, [r7, #20]

      if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
 80034b2:	697b      	ldr	r3, [r7, #20]
 80034b4:	2b00      	cmp	r3, #0
 80034b6:	d01f      	beq.n	80034f8 <HAL_RCCEx_PeriphCLKConfig+0x200>
 80034b8:	687b      	ldr	r3, [r7, #4]
 80034ba:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 80034be:	697a      	ldr	r2, [r7, #20]
 80034c0:	429a      	cmp	r2, r3
 80034c2:	d019      	beq.n	80034f8 <HAL_RCCEx_PeriphCLKConfig+0x200>
      {
        /* Store the content of BDCR register before the reset of Backup Domain */
        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
 80034c4:	4b24      	ldr	r3, [pc, #144]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034c6:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80034ca:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 80034ce:	617b      	str	r3, [r7, #20]
        /* RTC Clock selection can be changed only if the Backup Domain is reset */
        __HAL_RCC_BACKUPRESET_FORCE();
 80034d0:	4b21      	ldr	r3, [pc, #132]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034d2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80034d6:	4a20      	ldr	r2, [pc, #128]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034d8:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80034dc:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
        __HAL_RCC_BACKUPRESET_RELEASE();
 80034e0:	4b1d      	ldr	r3, [pc, #116]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034e2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80034e6:	4a1c      	ldr	r2, [pc, #112]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034e8:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 80034ec:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
        /* Restore the Content of BDCR register */
        RCC->BDCR = tmpregister;
 80034f0:	4a19      	ldr	r2, [pc, #100]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80034f2:	697b      	ldr	r3, [r7, #20]
 80034f4:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
      }

      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
 80034f8:	697b      	ldr	r3, [r7, #20]
 80034fa:	f003 0301 	and.w	r3, r3, #1
 80034fe:	2b00      	cmp	r3, #0
 8003500:	d016      	beq.n	8003530 <HAL_RCCEx_PeriphCLKConfig+0x238>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8003502:	f7fe f89f 	bl	8001644 <HAL_GetTick>
 8003506:	60f8      	str	r0, [r7, #12]

        /* Wait till LSE is ready */
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8003508:	e00b      	b.n	8003522 <HAL_RCCEx_PeriphCLKConfig+0x22a>
        {
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800350a:	f7fe f89b 	bl	8001644 <HAL_GetTick>
 800350e:	4602      	mov	r2, r0
 8003510:	68fb      	ldr	r3, [r7, #12]
 8003512:	1ad3      	subs	r3, r2, r3
 8003514:	f241 3288 	movw	r2, #5000	@ 0x1388
 8003518:	4293      	cmp	r3, r2
 800351a:	d902      	bls.n	8003522 <HAL_RCCEx_PeriphCLKConfig+0x22a>
          {
            ret = HAL_TIMEOUT;
 800351c:	2303      	movs	r3, #3
 800351e:	74fb      	strb	r3, [r7, #19]
            break;
 8003520:	e006      	b.n	8003530 <HAL_RCCEx_PeriphCLKConfig+0x238>
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8003522:	4b0d      	ldr	r3, [pc, #52]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003524:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8003528:	f003 0302 	and.w	r3, r3, #2
 800352c:	2b00      	cmp	r3, #0
 800352e:	d0ec      	beq.n	800350a <HAL_RCCEx_PeriphCLKConfig+0x212>
          }
        }
      }

      if(ret == HAL_OK)
 8003530:	7cfb      	ldrb	r3, [r7, #19]
 8003532:	2b00      	cmp	r3, #0
 8003534:	d10c      	bne.n	8003550 <HAL_RCCEx_PeriphCLKConfig+0x258>
      {
        /* Apply new RTC clock source selection */
        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 8003536:	4b08      	ldr	r3, [pc, #32]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003538:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800353c:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 8003540:	687b      	ldr	r3, [r7, #4]
 8003542:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 8003546:	4904      	ldr	r1, [pc, #16]	@ (8003558 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8003548:	4313      	orrs	r3, r2
 800354a:	f8c1 3090 	str.w	r3, [r1, #144]	@ 0x90
 800354e:	e009      	b.n	8003564 <HAL_RCCEx_PeriphCLKConfig+0x26c>
      }
      else
      {
        /* set overall return value */
        status = ret;
 8003550:	7cfb      	ldrb	r3, [r7, #19]
 8003552:	74bb      	strb	r3, [r7, #18]
 8003554:	e006      	b.n	8003564 <HAL_RCCEx_PeriphCLKConfig+0x26c>
 8003556:	bf00      	nop
 8003558:	40021000 	.word	0x40021000
 800355c:	40007000 	.word	0x40007000
      }
    }
    else
    {
      /* set overall return value */
      status = ret;
 8003560:	7cfb      	ldrb	r3, [r7, #19]
 8003562:	74bb      	strb	r3, [r7, #18]
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8003564:	7c7b      	ldrb	r3, [r7, #17]
 8003566:	2b01      	cmp	r3, #1
 8003568:	d105      	bne.n	8003576 <HAL_RCCEx_PeriphCLKConfig+0x27e>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 800356a:	4b9e      	ldr	r3, [pc, #632]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800356c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800356e:	4a9d      	ldr	r2, [pc, #628]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003570:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8003574:	6593      	str	r3, [r2, #88]	@ 0x58
    }
  }

  /*-------------------------- USART1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
 8003576:	687b      	ldr	r3, [r7, #4]
 8003578:	681b      	ldr	r3, [r3, #0]
 800357a:	f003 0301 	and.w	r3, r3, #1
 800357e:	2b00      	cmp	r3, #0
 8003580:	d00a      	beq.n	8003598 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));

    /* Configure the USART1 clock source */
    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
 8003582:	4b98      	ldr	r3, [pc, #608]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003584:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003588:	f023 0203 	bic.w	r2, r3, #3
 800358c:	687b      	ldr	r3, [r7, #4]
 800358e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8003590:	4994      	ldr	r1, [pc, #592]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003592:	4313      	orrs	r3, r2
 8003594:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- USART2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
 8003598:	687b      	ldr	r3, [r7, #4]
 800359a:	681b      	ldr	r3, [r3, #0]
 800359c:	f003 0302 	and.w	r3, r3, #2
 80035a0:	2b00      	cmp	r3, #0
 80035a2:	d00a      	beq.n	80035ba <HAL_RCCEx_PeriphCLKConfig+0x2c2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));

    /* Configure the USART2 clock source */
    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
 80035a4:	4b8f      	ldr	r3, [pc, #572]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035a6:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80035aa:	f023 020c 	bic.w	r2, r3, #12
 80035ae:	687b      	ldr	r3, [r7, #4]
 80035b0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80035b2:	498c      	ldr	r1, [pc, #560]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035b4:	4313      	orrs	r3, r2
 80035b6:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#if defined(USART3)

  /*-------------------------- USART3 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
 80035ba:	687b      	ldr	r3, [r7, #4]
 80035bc:	681b      	ldr	r3, [r3, #0]
 80035be:	f003 0304 	and.w	r3, r3, #4
 80035c2:	2b00      	cmp	r3, #0
 80035c4:	d00a      	beq.n	80035dc <HAL_RCCEx_PeriphCLKConfig+0x2e4>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));

    /* Configure the USART3 clock source */
    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
 80035c6:	4b87      	ldr	r3, [pc, #540]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035c8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80035cc:	f023 0230 	bic.w	r2, r3, #48	@ 0x30
 80035d0:	687b      	ldr	r3, [r7, #4]
 80035d2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80035d4:	4983      	ldr	r1, [pc, #524]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035d6:	4313      	orrs	r3, r2
 80035d8:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* USART3 */

#if defined(UART4)

  /*-------------------------- UART4 clock source configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
 80035dc:	687b      	ldr	r3, [r7, #4]
 80035de:	681b      	ldr	r3, [r3, #0]
 80035e0:	f003 0308 	and.w	r3, r3, #8
 80035e4:	2b00      	cmp	r3, #0
 80035e6:	d00a      	beq.n	80035fe <HAL_RCCEx_PeriphCLKConfig+0x306>
  {
    /* Check the parameters */
    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));

    /* Configure the UART4 clock source */
    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
 80035e8:	4b7e      	ldr	r3, [pc, #504]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035ea:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80035ee:	f023 02c0 	bic.w	r2, r3, #192	@ 0xc0
 80035f2:	687b      	ldr	r3, [r7, #4]
 80035f4:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80035f6:	497b      	ldr	r1, [pc, #492]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80035f8:	4313      	orrs	r3, r2
 80035fa:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* UART4 */

#if defined(UART5)

  /*-------------------------- UART5 clock source configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
 80035fe:	687b      	ldr	r3, [r7, #4]
 8003600:	681b      	ldr	r3, [r3, #0]
 8003602:	f003 0310 	and.w	r3, r3, #16
 8003606:	2b00      	cmp	r3, #0
 8003608:	d00a      	beq.n	8003620 <HAL_RCCEx_PeriphCLKConfig+0x328>
  {
    /* Check the parameters */
    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));

    /* Configure the UART5 clock source */
    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
 800360a:	4b76      	ldr	r3, [pc, #472]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800360c:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003610:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 8003614:	687b      	ldr	r3, [r7, #4]
 8003616:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8003618:	4972      	ldr	r1, [pc, #456]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800361a:	4313      	orrs	r3, r2
 800361c:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#endif /* UART5 */

  /*-------------------------- LPUART1 clock source configuration ------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
 8003620:	687b      	ldr	r3, [r7, #4]
 8003622:	681b      	ldr	r3, [r3, #0]
 8003624:	f003 0320 	and.w	r3, r3, #32
 8003628:	2b00      	cmp	r3, #0
 800362a:	d00a      	beq.n	8003642 <HAL_RCCEx_PeriphCLKConfig+0x34a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));

    /* Configure the LPUART1 clock source */
    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
 800362c:	4b6d      	ldr	r3, [pc, #436]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800362e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003632:	f423 6240 	bic.w	r2, r3, #3072	@ 0xc00
 8003636:	687b      	ldr	r3, [r7, #4]
 8003638:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800363a:	496a      	ldr	r1, [pc, #424]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800363c:	4313      	orrs	r3, r2
 800363e:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- LPTIM1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
 8003642:	687b      	ldr	r3, [r7, #4]
 8003644:	681b      	ldr	r3, [r3, #0]
 8003646:	f403 7300 	and.w	r3, r3, #512	@ 0x200
 800364a:	2b00      	cmp	r3, #0
 800364c:	d00a      	beq.n	8003664 <HAL_RCCEx_PeriphCLKConfig+0x36c>
  {
    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
 800364e:	4b65      	ldr	r3, [pc, #404]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003650:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003654:	f423 2240 	bic.w	r2, r3, #786432	@ 0xc0000
 8003658:	687b      	ldr	r3, [r7, #4]
 800365a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800365c:	4961      	ldr	r1, [pc, #388]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800365e:	4313      	orrs	r3, r2
 8003660:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- LPTIM2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
 8003664:	687b      	ldr	r3, [r7, #4]
 8003666:	681b      	ldr	r3, [r3, #0]
 8003668:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 800366c:	2b00      	cmp	r3, #0
 800366e:	d00a      	beq.n	8003686 <HAL_RCCEx_PeriphCLKConfig+0x38e>
  {
    assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
 8003670:	4b5c      	ldr	r3, [pc, #368]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003672:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003676:	f423 1240 	bic.w	r2, r3, #3145728	@ 0x300000
 800367a:	687b      	ldr	r3, [r7, #4]
 800367c:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800367e:	4959      	ldr	r1, [pc, #356]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003680:	4313      	orrs	r3, r2
 8003682:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- I2C1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
 8003686:	687b      	ldr	r3, [r7, #4]
 8003688:	681b      	ldr	r3, [r3, #0]
 800368a:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800368e:	2b00      	cmp	r3, #0
 8003690:	d00a      	beq.n	80036a8 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));

    /* Configure the I2C1 clock source */
    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
 8003692:	4b54      	ldr	r3, [pc, #336]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003694:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003698:	f423 5240 	bic.w	r2, r3, #12288	@ 0x3000
 800369c:	687b      	ldr	r3, [r7, #4]
 800369e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80036a0:	4950      	ldr	r1, [pc, #320]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036a2:	4313      	orrs	r3, r2
 80036a4:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#if defined(I2C2)

  /*-------------------------- I2C2 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
 80036a8:	687b      	ldr	r3, [r7, #4]
 80036aa:	681b      	ldr	r3, [r3, #0]
 80036ac:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80036b0:	2b00      	cmp	r3, #0
 80036b2:	d00a      	beq.n	80036ca <HAL_RCCEx_PeriphCLKConfig+0x3d2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));

    /* Configure the I2C2 clock source */
    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
 80036b4:	4b4b      	ldr	r3, [pc, #300]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036b6:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80036ba:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
 80036be:	687b      	ldr	r3, [r7, #4]
 80036c0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80036c2:	4948      	ldr	r1, [pc, #288]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036c4:	4313      	orrs	r3, r2
 80036c6:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#endif /* I2C2 */

  /*-------------------------- I2C3 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
 80036ca:	687b      	ldr	r3, [r7, #4]
 80036cc:	681b      	ldr	r3, [r3, #0]
 80036ce:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 80036d2:	2b00      	cmp	r3, #0
 80036d4:	d00a      	beq.n	80036ec <HAL_RCCEx_PeriphCLKConfig+0x3f4>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));

    /* Configure the I2C3 clock source */
    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
 80036d6:	4b43      	ldr	r3, [pc, #268]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036d8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80036dc:	f423 3240 	bic.w	r2, r3, #196608	@ 0x30000
 80036e0:	687b      	ldr	r3, [r7, #4]
 80036e2:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80036e4:	493f      	ldr	r1, [pc, #252]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036e6:	4313      	orrs	r3, r2
 80036e8:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* I2C4 */

#if defined(USB_OTG_FS) || defined(USB)

  /*-------------------------- USB clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
 80036ec:	687b      	ldr	r3, [r7, #4]
 80036ee:	681b      	ldr	r3, [r3, #0]
 80036f0:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 80036f4:	2b00      	cmp	r3, #0
 80036f6:	d028      	beq.n	800374a <HAL_RCCEx_PeriphCLKConfig+0x452>
  {
    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 80036f8:	4b3a      	ldr	r3, [pc, #232]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80036fa:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80036fe:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 8003702:	687b      	ldr	r3, [r7, #4]
 8003704:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8003706:	4937      	ldr	r1, [pc, #220]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003708:	4313      	orrs	r3, r2
 800370a:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
 800370e:	687b      	ldr	r3, [r7, #4]
 8003710:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8003712:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 8003716:	d106      	bne.n	8003726 <HAL_RCCEx_PeriphCLKConfig+0x42e>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8003718:	4b32      	ldr	r3, [pc, #200]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800371a:	68db      	ldr	r3, [r3, #12]
 800371c:	4a31      	ldr	r2, [pc, #196]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800371e:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 8003722:	60d3      	str	r3, [r2, #12]
 8003724:	e011      	b.n	800374a <HAL_RCCEx_PeriphCLKConfig+0x452>
    }
    else
    {
#if defined(RCC_PLLSAI1_SUPPORT)
      if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
 8003726:	687b      	ldr	r3, [r7, #4]
 8003728:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800372a:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800372e:	d10c      	bne.n	800374a <HAL_RCCEx_PeriphCLKConfig+0x452>
      {
        /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
        ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 8003730:	687b      	ldr	r3, [r7, #4]
 8003732:	3304      	adds	r3, #4
 8003734:	2101      	movs	r1, #1
 8003736:	4618      	mov	r0, r3
 8003738:	f000 f8d8 	bl	80038ec <RCCEx_PLLSAI1_Config>
 800373c:	4603      	mov	r3, r0
 800373e:	74fb      	strb	r3, [r7, #19]

        if(ret != HAL_OK)
 8003740:	7cfb      	ldrb	r3, [r7, #19]
 8003742:	2b00      	cmp	r3, #0
 8003744:	d001      	beq.n	800374a <HAL_RCCEx_PeriphCLKConfig+0x452>
        {
          /* set overall return value */
          status = ret;
 8003746:	7cfb      	ldrb	r3, [r7, #19]
 8003748:	74bb      	strb	r3, [r7, #18]
#endif /* USB_OTG_FS || USB */

#if defined(SDMMC1)

  /*-------------------------- SDMMC1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
 800374a:	687b      	ldr	r3, [r7, #4]
 800374c:	681b      	ldr	r3, [r3, #0]
 800374e:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 8003752:	2b00      	cmp	r3, #0
 8003754:	d028      	beq.n	80037a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
  {
    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
 8003756:	4b23      	ldr	r3, [pc, #140]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003758:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800375c:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 8003760:	687b      	ldr	r3, [r7, #4]
 8003762:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8003764:	491f      	ldr	r1, [pc, #124]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003766:	4313      	orrs	r3, r2
 8003768:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)   /* PLL "Q" ? */
 800376c:	687b      	ldr	r3, [r7, #4]
 800376e:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8003770:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 8003774:	d106      	bne.n	8003784 <HAL_RCCEx_PeriphCLKConfig+0x48c>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8003776:	4b1b      	ldr	r3, [pc, #108]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8003778:	68db      	ldr	r3, [r3, #12]
 800377a:	4a1a      	ldr	r2, [pc, #104]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800377c:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 8003780:	60d3      	str	r3, [r2, #12]
 8003782:	e011      	b.n	80037a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
    {
      /* Enable PLLSAI3CLK output */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
    }
#endif
    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
 8003784:	687b      	ldr	r3, [r7, #4]
 8003786:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8003788:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800378c:	d10c      	bne.n	80037a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
    {
      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 800378e:	687b      	ldr	r3, [r7, #4]
 8003790:	3304      	adds	r3, #4
 8003792:	2101      	movs	r1, #1
 8003794:	4618      	mov	r0, r3
 8003796:	f000 f8a9 	bl	80038ec <RCCEx_PLLSAI1_Config>
 800379a:	4603      	mov	r3, r0
 800379c:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 800379e:	7cfb      	ldrb	r3, [r7, #19]
 80037a0:	2b00      	cmp	r3, #0
 80037a2:	d001      	beq.n	80037a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
      {
        /* set overall return value */
        status = ret;
 80037a4:	7cfb      	ldrb	r3, [r7, #19]
 80037a6:	74bb      	strb	r3, [r7, #18]
  }

#endif /* SDMMC1 */

  /*-------------------------- RNG clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
 80037a8:	687b      	ldr	r3, [r7, #4]
 80037aa:	681b      	ldr	r3, [r3, #0]
 80037ac:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 80037b0:	2b00      	cmp	r3, #0
 80037b2:	d02b      	beq.n	800380c <HAL_RCCEx_PeriphCLKConfig+0x514>
  {
    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
 80037b4:	4b0b      	ldr	r3, [pc, #44]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80037b6:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80037ba:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 80037be:	687b      	ldr	r3, [r7, #4]
 80037c0:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80037c2:	4908      	ldr	r1, [pc, #32]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80037c4:	4313      	orrs	r3, r2
 80037c6:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
 80037ca:	687b      	ldr	r3, [r7, #4]
 80037cc:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80037ce:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 80037d2:	d109      	bne.n	80037e8 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 80037d4:	4b03      	ldr	r3, [pc, #12]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80037d6:	68db      	ldr	r3, [r3, #12]
 80037d8:	4a02      	ldr	r2, [pc, #8]	@ (80037e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80037da:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 80037de:	60d3      	str	r3, [r2, #12]
 80037e0:	e014      	b.n	800380c <HAL_RCCEx_PeriphCLKConfig+0x514>
 80037e2:	bf00      	nop
 80037e4:	40021000 	.word	0x40021000
    }
#if defined(RCC_PLLSAI1_SUPPORT)
    else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
 80037e8:	687b      	ldr	r3, [r7, #4]
 80037ea:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80037ec:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 80037f0:	d10c      	bne.n	800380c <HAL_RCCEx_PeriphCLKConfig+0x514>
    {
      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 80037f2:	687b      	ldr	r3, [r7, #4]
 80037f4:	3304      	adds	r3, #4
 80037f6:	2101      	movs	r1, #1
 80037f8:	4618      	mov	r0, r3
 80037fa:	f000 f877 	bl	80038ec <RCCEx_PLLSAI1_Config>
 80037fe:	4603      	mov	r3, r0
 8003800:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 8003802:	7cfb      	ldrb	r3, [r7, #19]
 8003804:	2b00      	cmp	r3, #0
 8003806:	d001      	beq.n	800380c <HAL_RCCEx_PeriphCLKConfig+0x514>
      {
        /* set overall return value */
        status = ret;
 8003808:	7cfb      	ldrb	r3, [r7, #19]
 800380a:	74bb      	strb	r3, [r7, #18]
    }
  }

  /*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 800380c:	687b      	ldr	r3, [r7, #4]
 800380e:	681b      	ldr	r3, [r3, #0]
 8003810:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 8003814:	2b00      	cmp	r3, #0
 8003816:	d02f      	beq.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC interface clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 8003818:	4b2b      	ldr	r3, [pc, #172]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 800381a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800381e:	f023 5240 	bic.w	r2, r3, #805306368	@ 0x30000000
 8003822:	687b      	ldr	r3, [r7, #4]
 8003824:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 8003826:	4928      	ldr	r1, [pc, #160]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8003828:	4313      	orrs	r3, r2
 800382a:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

#if defined(RCC_PLLSAI1_SUPPORT)
    if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
 800382e:	687b      	ldr	r3, [r7, #4]
 8003830:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 8003832:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 8003836:	d10d      	bne.n	8003854 <HAL_RCCEx_PeriphCLKConfig+0x55c>
    {
      /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
 8003838:	687b      	ldr	r3, [r7, #4]
 800383a:	3304      	adds	r3, #4
 800383c:	2102      	movs	r1, #2
 800383e:	4618      	mov	r0, r3
 8003840:	f000 f854 	bl	80038ec <RCCEx_PLLSAI1_Config>
 8003844:	4603      	mov	r3, r0
 8003846:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 8003848:	7cfb      	ldrb	r3, [r7, #19]
 800384a:	2b00      	cmp	r3, #0
 800384c:	d014      	beq.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
      {
        /* set overall return value */
        status = ret;
 800384e:	7cfb      	ldrb	r3, [r7, #19]
 8003850:	74bb      	strb	r3, [r7, #18]
 8003852:	e011      	b.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
    }
#endif /* RCC_PLLSAI1_SUPPORT */

#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)

    else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
 8003854:	687b      	ldr	r3, [r7, #4]
 8003856:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 8003858:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800385c:	d10c      	bne.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
    {
      /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
 800385e:	687b      	ldr	r3, [r7, #4]
 8003860:	3320      	adds	r3, #32
 8003862:	2102      	movs	r1, #2
 8003864:	4618      	mov	r0, r3
 8003866:	f000 f935 	bl	8003ad4 <RCCEx_PLLSAI2_Config>
 800386a:	4603      	mov	r3, r0
 800386c:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 800386e:	7cfb      	ldrb	r3, [r7, #19]
 8003870:	2b00      	cmp	r3, #0
 8003872:	d001      	beq.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0x580>
      {
        /* set overall return value */
        status = ret;
 8003874:	7cfb      	ldrb	r3, [r7, #19]
 8003876:	74bb      	strb	r3, [r7, #18]
#endif /* !STM32L412xx && !STM32L422xx */

#if defined(SWPMI1)

  /*-------------------------- SWPMI1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
 8003878:	687b      	ldr	r3, [r7, #4]
 800387a:	681b      	ldr	r3, [r3, #0]
 800387c:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8003880:	2b00      	cmp	r3, #0
 8003882:	d00a      	beq.n	800389a <HAL_RCCEx_PeriphCLKConfig+0x5a2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));

    /* Configure the SWPMI1 clock source */
    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
 8003884:	4b10      	ldr	r3, [pc, #64]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8003886:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800388a:	f023 4280 	bic.w	r2, r3, #1073741824	@ 0x40000000
 800388e:	687b      	ldr	r3, [r7, #4]
 8003890:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 8003892:	490d      	ldr	r1, [pc, #52]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8003894:	4313      	orrs	r3, r2
 8003896:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* SWPMI1 */

#if defined(DFSDM1_Filter0)

  /*-------------------------- DFSDM1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
 800389a:	687b      	ldr	r3, [r7, #4]
 800389c:	681b      	ldr	r3, [r3, #0]
 800389e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 80038a2:	2b00      	cmp	r3, #0
 80038a4:	d00b      	beq.n	80038be <HAL_RCCEx_PeriphCLKConfig+0x5c6>
  {
    /* Check the parameters */
    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));

    /* Configure the DFSDM1 interface clock source */
    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
 80038a6:	4b08      	ldr	r3, [pc, #32]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 80038a8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80038ac:	f023 4200 	bic.w	r2, r3, #2147483648	@ 0x80000000
 80038b0:	687b      	ldr	r3, [r7, #4]
 80038b2:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 80038b6:	4904      	ldr	r1, [pc, #16]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 80038b8:	4313      	orrs	r3, r2
 80038ba:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
    }
  }

#endif /* OCTOSPI1 || OCTOSPI2 */

  return status;
 80038be:	7cbb      	ldrb	r3, [r7, #18]
}
 80038c0:	4618      	mov	r0, r3
 80038c2:	3718      	adds	r7, #24
 80038c4:	46bd      	mov	sp, r7
 80038c6:	bd80      	pop	{r7, pc}
 80038c8:	40021000 	.word	0x40021000

080038cc <HAL_RCCEx_EnableMSIPLLMode>:
  * @note   Prior to enable the PLL-mode of the MSI for automatic hardware
  *         calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
  * @retval None
  */
void HAL_RCCEx_EnableMSIPLLMode(void)
{
 80038cc:	b480      	push	{r7}
 80038ce:	af00      	add	r7, sp, #0
  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
 80038d0:	4b05      	ldr	r3, [pc, #20]	@ (80038e8 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
 80038d2:	681b      	ldr	r3, [r3, #0]
 80038d4:	4a04      	ldr	r2, [pc, #16]	@ (80038e8 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
 80038d6:	f043 0304 	orr.w	r3, r3, #4
 80038da:	6013      	str	r3, [r2, #0]
}
 80038dc:	bf00      	nop
 80038de:	46bd      	mov	sp, r7
 80038e0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80038e4:	4770      	bx	lr
 80038e6:	bf00      	nop
 80038e8:	40021000 	.word	0x40021000

080038ec <RCCEx_PLLSAI1_Config>:
  * @note   PLLSAI1 is temporary disable to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
 80038ec:	b580      	push	{r7, lr}
 80038ee:	b084      	sub	sp, #16
 80038f0:	af00      	add	r7, sp, #0
 80038f2:	6078      	str	r0, [r7, #4]
 80038f4:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 80038f6:	2300      	movs	r3, #0
 80038f8:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));

  /* Check that PLLSAI1 clock source and divider M can be applied */
  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
 80038fa:	4b75      	ldr	r3, [pc, #468]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80038fc:	68db      	ldr	r3, [r3, #12]
 80038fe:	f003 0303 	and.w	r3, r3, #3
 8003902:	2b00      	cmp	r3, #0
 8003904:	d018      	beq.n	8003938 <RCCEx_PLLSAI1_Config+0x4c>
  {
    /* PLL clock source and divider M already set, check that no request for change  */
    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
 8003906:	4b72      	ldr	r3, [pc, #456]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003908:	68db      	ldr	r3, [r3, #12]
 800390a:	f003 0203 	and.w	r2, r3, #3
 800390e:	687b      	ldr	r3, [r7, #4]
 8003910:	681b      	ldr	r3, [r3, #0]
 8003912:	429a      	cmp	r2, r3
 8003914:	d10d      	bne.n	8003932 <RCCEx_PLLSAI1_Config+0x46>
       ||
       (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
 8003916:	687b      	ldr	r3, [r7, #4]
 8003918:	681b      	ldr	r3, [r3, #0]
       ||
 800391a:	2b00      	cmp	r3, #0
 800391c:	d009      	beq.n	8003932 <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
       ||
       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
 800391e:	4b6c      	ldr	r3, [pc, #432]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003920:	68db      	ldr	r3, [r3, #12]
 8003922:	091b      	lsrs	r3, r3, #4
 8003924:	f003 0307 	and.w	r3, r3, #7
 8003928:	1c5a      	adds	r2, r3, #1
 800392a:	687b      	ldr	r3, [r7, #4]
 800392c:	685b      	ldr	r3, [r3, #4]
       ||
 800392e:	429a      	cmp	r2, r3
 8003930:	d047      	beq.n	80039c2 <RCCEx_PLLSAI1_Config+0xd6>
#endif
      )
    {
      status = HAL_ERROR;
 8003932:	2301      	movs	r3, #1
 8003934:	73fb      	strb	r3, [r7, #15]
 8003936:	e044      	b.n	80039c2 <RCCEx_PLLSAI1_Config+0xd6>
    }
  }
  else
  {
    /* Check PLLSAI1 clock source availability */
    switch(PllSai1->PLLSAI1Source)
 8003938:	687b      	ldr	r3, [r7, #4]
 800393a:	681b      	ldr	r3, [r3, #0]
 800393c:	2b03      	cmp	r3, #3
 800393e:	d018      	beq.n	8003972 <RCCEx_PLLSAI1_Config+0x86>
 8003940:	2b03      	cmp	r3, #3
 8003942:	d825      	bhi.n	8003990 <RCCEx_PLLSAI1_Config+0xa4>
 8003944:	2b01      	cmp	r3, #1
 8003946:	d002      	beq.n	800394e <RCCEx_PLLSAI1_Config+0x62>
 8003948:	2b02      	cmp	r3, #2
 800394a:	d009      	beq.n	8003960 <RCCEx_PLLSAI1_Config+0x74>
 800394c:	e020      	b.n	8003990 <RCCEx_PLLSAI1_Config+0xa4>
    {
    case RCC_PLLSOURCE_MSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
 800394e:	4b60      	ldr	r3, [pc, #384]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003950:	681b      	ldr	r3, [r3, #0]
 8003952:	f003 0302 	and.w	r3, r3, #2
 8003956:	2b00      	cmp	r3, #0
 8003958:	d11d      	bne.n	8003996 <RCCEx_PLLSAI1_Config+0xaa>
      {
        status = HAL_ERROR;
 800395a:	2301      	movs	r3, #1
 800395c:	73fb      	strb	r3, [r7, #15]
      }
      break;
 800395e:	e01a      	b.n	8003996 <RCCEx_PLLSAI1_Config+0xaa>
    case RCC_PLLSOURCE_HSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
 8003960:	4b5b      	ldr	r3, [pc, #364]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003962:	681b      	ldr	r3, [r3, #0]
 8003964:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8003968:	2b00      	cmp	r3, #0
 800396a:	d116      	bne.n	800399a <RCCEx_PLLSAI1_Config+0xae>
      {
        status = HAL_ERROR;
 800396c:	2301      	movs	r3, #1
 800396e:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8003970:	e013      	b.n	800399a <RCCEx_PLLSAI1_Config+0xae>
    case RCC_PLLSOURCE_HSE:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
 8003972:	4b57      	ldr	r3, [pc, #348]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003974:	681b      	ldr	r3, [r3, #0]
 8003976:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800397a:	2b00      	cmp	r3, #0
 800397c:	d10f      	bne.n	800399e <RCCEx_PLLSAI1_Config+0xb2>
      {
        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
 800397e:	4b54      	ldr	r3, [pc, #336]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003980:	681b      	ldr	r3, [r3, #0]
 8003982:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 8003986:	2b00      	cmp	r3, #0
 8003988:	d109      	bne.n	800399e <RCCEx_PLLSAI1_Config+0xb2>
        {
          status = HAL_ERROR;
 800398a:	2301      	movs	r3, #1
 800398c:	73fb      	strb	r3, [r7, #15]
        }
      }
      break;
 800398e:	e006      	b.n	800399e <RCCEx_PLLSAI1_Config+0xb2>
    default:
      status = HAL_ERROR;
 8003990:	2301      	movs	r3, #1
 8003992:	73fb      	strb	r3, [r7, #15]
      break;
 8003994:	e004      	b.n	80039a0 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 8003996:	bf00      	nop
 8003998:	e002      	b.n	80039a0 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 800399a:	bf00      	nop
 800399c:	e000      	b.n	80039a0 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 800399e:	bf00      	nop
    }

    if(status == HAL_OK)
 80039a0:	7bfb      	ldrb	r3, [r7, #15]
 80039a2:	2b00      	cmp	r3, #0
 80039a4:	d10d      	bne.n	80039c2 <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
      /* Set PLLSAI1 clock source */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
      /* Set PLLSAI1 clock source and divider M */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
 80039a6:	4b4a      	ldr	r3, [pc, #296]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039a8:	68db      	ldr	r3, [r3, #12]
 80039aa:	f023 0273 	bic.w	r2, r3, #115	@ 0x73
 80039ae:	687b      	ldr	r3, [r7, #4]
 80039b0:	6819      	ldr	r1, [r3, #0]
 80039b2:	687b      	ldr	r3, [r7, #4]
 80039b4:	685b      	ldr	r3, [r3, #4]
 80039b6:	3b01      	subs	r3, #1
 80039b8:	011b      	lsls	r3, r3, #4
 80039ba:	430b      	orrs	r3, r1
 80039bc:	4944      	ldr	r1, [pc, #272]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039be:	4313      	orrs	r3, r2
 80039c0:	60cb      	str	r3, [r1, #12]
#endif
    }
  }

  if(status == HAL_OK)
 80039c2:	7bfb      	ldrb	r3, [r7, #15]
 80039c4:	2b00      	cmp	r3, #0
 80039c6:	d17d      	bne.n	8003ac4 <RCCEx_PLLSAI1_Config+0x1d8>
  {
    /* Disable the PLLSAI1 */
    __HAL_RCC_PLLSAI1_DISABLE();
 80039c8:	4b41      	ldr	r3, [pc, #260]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039ca:	681b      	ldr	r3, [r3, #0]
 80039cc:	4a40      	ldr	r2, [pc, #256]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039ce:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 80039d2:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 80039d4:	f7fd fe36 	bl	8001644 <HAL_GetTick>
 80039d8:	60b8      	str	r0, [r7, #8]

    /* Wait till PLLSAI1 is ready to be updated */
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
 80039da:	e009      	b.n	80039f0 <RCCEx_PLLSAI1_Config+0x104>
    {
      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
 80039dc:	f7fd fe32 	bl	8001644 <HAL_GetTick>
 80039e0:	4602      	mov	r2, r0
 80039e2:	68bb      	ldr	r3, [r7, #8]
 80039e4:	1ad3      	subs	r3, r2, r3
 80039e6:	2b02      	cmp	r3, #2
 80039e8:	d902      	bls.n	80039f0 <RCCEx_PLLSAI1_Config+0x104>
      {
        status = HAL_TIMEOUT;
 80039ea:	2303      	movs	r3, #3
 80039ec:	73fb      	strb	r3, [r7, #15]
        break;
 80039ee:	e005      	b.n	80039fc <RCCEx_PLLSAI1_Config+0x110>
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
 80039f0:	4b37      	ldr	r3, [pc, #220]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 80039f2:	681b      	ldr	r3, [r3, #0]
 80039f4:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 80039f8:	2b00      	cmp	r3, #0
 80039fa:	d1ef      	bne.n	80039dc <RCCEx_PLLSAI1_Config+0xf0>
      }
    }

    if(status == HAL_OK)
 80039fc:	7bfb      	ldrb	r3, [r7, #15]
 80039fe:	2b00      	cmp	r3, #0
 8003a00:	d160      	bne.n	8003ac4 <RCCEx_PLLSAI1_Config+0x1d8>
    {
      if(Divider == DIVIDER_P_UPDATE)
 8003a02:	683b      	ldr	r3, [r7, #0]
 8003a04:	2b00      	cmp	r3, #0
 8003a06:	d111      	bne.n	8003a2c <RCCEx_PLLSAI1_Config+0x140>
        MODIFY_REG(RCC->PLLSAI1CFGR,
                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
#else
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8003a08:	4b31      	ldr	r3, [pc, #196]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a0a:	691b      	ldr	r3, [r3, #16]
 8003a0c:	f423 331f 	bic.w	r3, r3, #162816	@ 0x27c00
 8003a10:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8003a14:	687a      	ldr	r2, [r7, #4]
 8003a16:	6892      	ldr	r2, [r2, #8]
 8003a18:	0211      	lsls	r1, r2, #8
 8003a1a:	687a      	ldr	r2, [r7, #4]
 8003a1c:	68d2      	ldr	r2, [r2, #12]
 8003a1e:	0912      	lsrs	r2, r2, #4
 8003a20:	0452      	lsls	r2, r2, #17
 8003a22:	430a      	orrs	r2, r1
 8003a24:	492a      	ldr	r1, [pc, #168]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a26:	4313      	orrs	r3, r2
 8003a28:	610b      	str	r3, [r1, #16]
 8003a2a:	e027      	b.n	8003a7c <RCCEx_PLLSAI1_Config+0x190>
                   ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */

#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
      }
      else if(Divider == DIVIDER_Q_UPDATE)
 8003a2c:	683b      	ldr	r3, [r7, #0]
 8003a2e:	2b01      	cmp	r3, #1
 8003a30:	d112      	bne.n	8003a58 <RCCEx_PLLSAI1_Config+0x16c>
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
        /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8003a32:	4b27      	ldr	r3, [pc, #156]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a34:	691b      	ldr	r3, [r3, #16]
 8003a36:	f423 03c0 	bic.w	r3, r3, #6291456	@ 0x600000
 8003a3a:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 8003a3e:	687a      	ldr	r2, [r7, #4]
 8003a40:	6892      	ldr	r2, [r2, #8]
 8003a42:	0211      	lsls	r1, r2, #8
 8003a44:	687a      	ldr	r2, [r7, #4]
 8003a46:	6912      	ldr	r2, [r2, #16]
 8003a48:	0852      	lsrs	r2, r2, #1
 8003a4a:	3a01      	subs	r2, #1
 8003a4c:	0552      	lsls	r2, r2, #21
 8003a4e:	430a      	orrs	r2, r1
 8003a50:	491f      	ldr	r1, [pc, #124]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a52:	4313      	orrs	r3, r2
 8003a54:	610b      	str	r3, [r1, #16]
 8003a56:	e011      	b.n	8003a7c <RCCEx_PLLSAI1_Config+0x190>
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
        /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8003a58:	4b1d      	ldr	r3, [pc, #116]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a5a:	691b      	ldr	r3, [r3, #16]
 8003a5c:	f023 63c0 	bic.w	r3, r3, #100663296	@ 0x6000000
 8003a60:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 8003a64:	687a      	ldr	r2, [r7, #4]
 8003a66:	6892      	ldr	r2, [r2, #8]
 8003a68:	0211      	lsls	r1, r2, #8
 8003a6a:	687a      	ldr	r2, [r7, #4]
 8003a6c:	6952      	ldr	r2, [r2, #20]
 8003a6e:	0852      	lsrs	r2, r2, #1
 8003a70:	3a01      	subs	r2, #1
 8003a72:	0652      	lsls	r2, r2, #25
 8003a74:	430a      	orrs	r2, r1
 8003a76:	4916      	ldr	r1, [pc, #88]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a78:	4313      	orrs	r3, r2
 8003a7a:	610b      	str	r3, [r1, #16]
                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
      }

      /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
      __HAL_RCC_PLLSAI1_ENABLE();
 8003a7c:	4b14      	ldr	r3, [pc, #80]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a7e:	681b      	ldr	r3, [r3, #0]
 8003a80:	4a13      	ldr	r2, [pc, #76]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003a82:	f043 6380 	orr.w	r3, r3, #67108864	@ 0x4000000
 8003a86:	6013      	str	r3, [r2, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8003a88:	f7fd fddc 	bl	8001644 <HAL_GetTick>
 8003a8c:	60b8      	str	r0, [r7, #8]

      /* Wait till PLLSAI1 is ready */
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
 8003a8e:	e009      	b.n	8003aa4 <RCCEx_PLLSAI1_Config+0x1b8>
      {
        if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
 8003a90:	f7fd fdd8 	bl	8001644 <HAL_GetTick>
 8003a94:	4602      	mov	r2, r0
 8003a96:	68bb      	ldr	r3, [r7, #8]
 8003a98:	1ad3      	subs	r3, r2, r3
 8003a9a:	2b02      	cmp	r3, #2
 8003a9c:	d902      	bls.n	8003aa4 <RCCEx_PLLSAI1_Config+0x1b8>
        {
          status = HAL_TIMEOUT;
 8003a9e:	2303      	movs	r3, #3
 8003aa0:	73fb      	strb	r3, [r7, #15]
          break;
 8003aa2:	e005      	b.n	8003ab0 <RCCEx_PLLSAI1_Config+0x1c4>
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
 8003aa4:	4b0a      	ldr	r3, [pc, #40]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003aa6:	681b      	ldr	r3, [r3, #0]
 8003aa8:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 8003aac:	2b00      	cmp	r3, #0
 8003aae:	d0ef      	beq.n	8003a90 <RCCEx_PLLSAI1_Config+0x1a4>
        }
      }

      if(status == HAL_OK)
 8003ab0:	7bfb      	ldrb	r3, [r7, #15]
 8003ab2:	2b00      	cmp	r3, #0
 8003ab4:	d106      	bne.n	8003ac4 <RCCEx_PLLSAI1_Config+0x1d8>
      {
        /* Configure the PLLSAI1 Clock output(s) */
        __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
 8003ab6:	4b06      	ldr	r3, [pc, #24]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003ab8:	691a      	ldr	r2, [r3, #16]
 8003aba:	687b      	ldr	r3, [r7, #4]
 8003abc:	699b      	ldr	r3, [r3, #24]
 8003abe:	4904      	ldr	r1, [pc, #16]	@ (8003ad0 <RCCEx_PLLSAI1_Config+0x1e4>)
 8003ac0:	4313      	orrs	r3, r2
 8003ac2:	610b      	str	r3, [r1, #16]
      }
    }
  }

  return status;
 8003ac4:	7bfb      	ldrb	r3, [r7, #15]
}
 8003ac6:	4618      	mov	r0, r3
 8003ac8:	3710      	adds	r7, #16
 8003aca:	46bd      	mov	sp, r7
 8003acc:	bd80      	pop	{r7, pc}
 8003ace:	bf00      	nop
 8003ad0:	40021000 	.word	0x40021000

08003ad4 <RCCEx_PLLSAI2_Config>:
  * @note   PLLSAI2 is temporary disable to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
{
 8003ad4:	b580      	push	{r7, lr}
 8003ad6:	b084      	sub	sp, #16
 8003ad8:	af00      	add	r7, sp, #0
 8003ada:	6078      	str	r0, [r7, #4]
 8003adc:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 8003ade:	2300      	movs	r3, #0
 8003ae0:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));

  /* Check that PLLSAI2 clock source and divider M can be applied */
  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
 8003ae2:	4b6a      	ldr	r3, [pc, #424]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003ae4:	68db      	ldr	r3, [r3, #12]
 8003ae6:	f003 0303 	and.w	r3, r3, #3
 8003aea:	2b00      	cmp	r3, #0
 8003aec:	d018      	beq.n	8003b20 <RCCEx_PLLSAI2_Config+0x4c>
  {
    /* PLL clock source and divider M already set, check that no request for change  */
    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
 8003aee:	4b67      	ldr	r3, [pc, #412]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003af0:	68db      	ldr	r3, [r3, #12]
 8003af2:	f003 0203 	and.w	r2, r3, #3
 8003af6:	687b      	ldr	r3, [r7, #4]
 8003af8:	681b      	ldr	r3, [r3, #0]
 8003afa:	429a      	cmp	r2, r3
 8003afc:	d10d      	bne.n	8003b1a <RCCEx_PLLSAI2_Config+0x46>
       ||
       (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
 8003afe:	687b      	ldr	r3, [r7, #4]
 8003b00:	681b      	ldr	r3, [r3, #0]
       ||
 8003b02:	2b00      	cmp	r3, #0
 8003b04:	d009      	beq.n	8003b1a <RCCEx_PLLSAI2_Config+0x46>
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
       ||
       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
 8003b06:	4b61      	ldr	r3, [pc, #388]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b08:	68db      	ldr	r3, [r3, #12]
 8003b0a:	091b      	lsrs	r3, r3, #4
 8003b0c:	f003 0307 	and.w	r3, r3, #7
 8003b10:	1c5a      	adds	r2, r3, #1
 8003b12:	687b      	ldr	r3, [r7, #4]
 8003b14:	685b      	ldr	r3, [r3, #4]
       ||
 8003b16:	429a      	cmp	r2, r3
 8003b18:	d047      	beq.n	8003baa <RCCEx_PLLSAI2_Config+0xd6>
#endif
      )
    {
      status = HAL_ERROR;
 8003b1a:	2301      	movs	r3, #1
 8003b1c:	73fb      	strb	r3, [r7, #15]
 8003b1e:	e044      	b.n	8003baa <RCCEx_PLLSAI2_Config+0xd6>
    }
  }
  else
  {
    /* Check PLLSAI2 clock source availability */
    switch(PllSai2->PLLSAI2Source)
 8003b20:	687b      	ldr	r3, [r7, #4]
 8003b22:	681b      	ldr	r3, [r3, #0]
 8003b24:	2b03      	cmp	r3, #3
 8003b26:	d018      	beq.n	8003b5a <RCCEx_PLLSAI2_Config+0x86>
 8003b28:	2b03      	cmp	r3, #3
 8003b2a:	d825      	bhi.n	8003b78 <RCCEx_PLLSAI2_Config+0xa4>
 8003b2c:	2b01      	cmp	r3, #1
 8003b2e:	d002      	beq.n	8003b36 <RCCEx_PLLSAI2_Config+0x62>
 8003b30:	2b02      	cmp	r3, #2
 8003b32:	d009      	beq.n	8003b48 <RCCEx_PLLSAI2_Config+0x74>
 8003b34:	e020      	b.n	8003b78 <RCCEx_PLLSAI2_Config+0xa4>
    {
    case RCC_PLLSOURCE_MSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
 8003b36:	4b55      	ldr	r3, [pc, #340]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b38:	681b      	ldr	r3, [r3, #0]
 8003b3a:	f003 0302 	and.w	r3, r3, #2
 8003b3e:	2b00      	cmp	r3, #0
 8003b40:	d11d      	bne.n	8003b7e <RCCEx_PLLSAI2_Config+0xaa>
      {
        status = HAL_ERROR;
 8003b42:	2301      	movs	r3, #1
 8003b44:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8003b46:	e01a      	b.n	8003b7e <RCCEx_PLLSAI2_Config+0xaa>
    case RCC_PLLSOURCE_HSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
 8003b48:	4b50      	ldr	r3, [pc, #320]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b4a:	681b      	ldr	r3, [r3, #0]
 8003b4c:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8003b50:	2b00      	cmp	r3, #0
 8003b52:	d116      	bne.n	8003b82 <RCCEx_PLLSAI2_Config+0xae>
      {
        status = HAL_ERROR;
 8003b54:	2301      	movs	r3, #1
 8003b56:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8003b58:	e013      	b.n	8003b82 <RCCEx_PLLSAI2_Config+0xae>
    case RCC_PLLSOURCE_HSE:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
 8003b5a:	4b4c      	ldr	r3, [pc, #304]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b5c:	681b      	ldr	r3, [r3, #0]
 8003b5e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8003b62:	2b00      	cmp	r3, #0
 8003b64:	d10f      	bne.n	8003b86 <RCCEx_PLLSAI2_Config+0xb2>
      {
        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
 8003b66:	4b49      	ldr	r3, [pc, #292]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b68:	681b      	ldr	r3, [r3, #0]
 8003b6a:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 8003b6e:	2b00      	cmp	r3, #0
 8003b70:	d109      	bne.n	8003b86 <RCCEx_PLLSAI2_Config+0xb2>
        {
          status = HAL_ERROR;
 8003b72:	2301      	movs	r3, #1
 8003b74:	73fb      	strb	r3, [r7, #15]
        }
      }
      break;
 8003b76:	e006      	b.n	8003b86 <RCCEx_PLLSAI2_Config+0xb2>
    default:
      status = HAL_ERROR;
 8003b78:	2301      	movs	r3, #1
 8003b7a:	73fb      	strb	r3, [r7, #15]
      break;
 8003b7c:	e004      	b.n	8003b88 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8003b7e:	bf00      	nop
 8003b80:	e002      	b.n	8003b88 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8003b82:	bf00      	nop
 8003b84:	e000      	b.n	8003b88 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8003b86:	bf00      	nop
    }

    if(status == HAL_OK)
 8003b88:	7bfb      	ldrb	r3, [r7, #15]
 8003b8a:	2b00      	cmp	r3, #0
 8003b8c:	d10d      	bne.n	8003baa <RCCEx_PLLSAI2_Config+0xd6>
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
      /* Set PLLSAI2 clock source */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
#else
      /* Set PLLSAI2 clock source and divider M */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
 8003b8e:	4b3f      	ldr	r3, [pc, #252]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003b90:	68db      	ldr	r3, [r3, #12]
 8003b92:	f023 0273 	bic.w	r2, r3, #115	@ 0x73
 8003b96:	687b      	ldr	r3, [r7, #4]
 8003b98:	6819      	ldr	r1, [r3, #0]
 8003b9a:	687b      	ldr	r3, [r7, #4]
 8003b9c:	685b      	ldr	r3, [r3, #4]
 8003b9e:	3b01      	subs	r3, #1
 8003ba0:	011b      	lsls	r3, r3, #4
 8003ba2:	430b      	orrs	r3, r1
 8003ba4:	4939      	ldr	r1, [pc, #228]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003ba6:	4313      	orrs	r3, r2
 8003ba8:	60cb      	str	r3, [r1, #12]
#endif
    }
  }

  if(status == HAL_OK)
 8003baa:	7bfb      	ldrb	r3, [r7, #15]
 8003bac:	2b00      	cmp	r3, #0
 8003bae:	d167      	bne.n	8003c80 <RCCEx_PLLSAI2_Config+0x1ac>
  {
    /* Disable the PLLSAI2 */
    __HAL_RCC_PLLSAI2_DISABLE();
 8003bb0:	4b36      	ldr	r3, [pc, #216]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003bb2:	681b      	ldr	r3, [r3, #0]
 8003bb4:	4a35      	ldr	r2, [pc, #212]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003bb6:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8003bba:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8003bbc:	f7fd fd42 	bl	8001644 <HAL_GetTick>
 8003bc0:	60b8      	str	r0, [r7, #8]

    /* Wait till PLLSAI2 is ready to be updated */
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
 8003bc2:	e009      	b.n	8003bd8 <RCCEx_PLLSAI2_Config+0x104>
    {
      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
 8003bc4:	f7fd fd3e 	bl	8001644 <HAL_GetTick>
 8003bc8:	4602      	mov	r2, r0
 8003bca:	68bb      	ldr	r3, [r7, #8]
 8003bcc:	1ad3      	subs	r3, r2, r3
 8003bce:	2b02      	cmp	r3, #2
 8003bd0:	d902      	bls.n	8003bd8 <RCCEx_PLLSAI2_Config+0x104>
      {
        status = HAL_TIMEOUT;
 8003bd2:	2303      	movs	r3, #3
 8003bd4:	73fb      	strb	r3, [r7, #15]
        break;
 8003bd6:	e005      	b.n	8003be4 <RCCEx_PLLSAI2_Config+0x110>
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
 8003bd8:	4b2c      	ldr	r3, [pc, #176]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003bda:	681b      	ldr	r3, [r3, #0]
 8003bdc:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 8003be0:	2b00      	cmp	r3, #0
 8003be2:	d1ef      	bne.n	8003bc4 <RCCEx_PLLSAI2_Config+0xf0>
      }
    }

    if(status == HAL_OK)
 8003be4:	7bfb      	ldrb	r3, [r7, #15]
 8003be6:	2b00      	cmp	r3, #0
 8003be8:	d14a      	bne.n	8003c80 <RCCEx_PLLSAI2_Config+0x1ac>
    {
      if(Divider == DIVIDER_P_UPDATE)
 8003bea:	683b      	ldr	r3, [r7, #0]
 8003bec:	2b00      	cmp	r3, #0
 8003bee:	d111      	bne.n	8003c14 <RCCEx_PLLSAI2_Config+0x140>
        MODIFY_REG(RCC->PLLSAI2CFGR,
                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
                   (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
#else
        MODIFY_REG(RCC->PLLSAI2CFGR,
 8003bf0:	4b26      	ldr	r3, [pc, #152]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003bf2:	695b      	ldr	r3, [r3, #20]
 8003bf4:	f423 331f 	bic.w	r3, r3, #162816	@ 0x27c00
 8003bf8:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8003bfc:	687a      	ldr	r2, [r7, #4]
 8003bfe:	6892      	ldr	r2, [r2, #8]
 8003c00:	0211      	lsls	r1, r2, #8
 8003c02:	687a      	ldr	r2, [r7, #4]
 8003c04:	68d2      	ldr	r2, [r2, #12]
 8003c06:	0912      	lsrs	r2, r2, #4
 8003c08:	0452      	lsls	r2, r2, #17
 8003c0a:	430a      	orrs	r2, r1
 8003c0c:	491f      	ldr	r1, [pc, #124]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c0e:	4313      	orrs	r3, r2
 8003c10:	614b      	str	r3, [r1, #20]
 8003c12:	e011      	b.n	8003c38 <RCCEx_PLLSAI2_Config+0x164>
                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
#else
        /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI2CFGR,
 8003c14:	4b1d      	ldr	r3, [pc, #116]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c16:	695b      	ldr	r3, [r3, #20]
 8003c18:	f023 63c0 	bic.w	r3, r3, #100663296	@ 0x6000000
 8003c1c:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 8003c20:	687a      	ldr	r2, [r7, #4]
 8003c22:	6892      	ldr	r2, [r2, #8]
 8003c24:	0211      	lsls	r1, r2, #8
 8003c26:	687a      	ldr	r2, [r7, #4]
 8003c28:	6912      	ldr	r2, [r2, #16]
 8003c2a:	0852      	lsrs	r2, r2, #1
 8003c2c:	3a01      	subs	r2, #1
 8003c2e:	0652      	lsls	r2, r2, #25
 8003c30:	430a      	orrs	r2, r1
 8003c32:	4916      	ldr	r1, [pc, #88]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c34:	4313      	orrs	r3, r2
 8003c36:	614b      	str	r3, [r1, #20]
                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
      }

      /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
      __HAL_RCC_PLLSAI2_ENABLE();
 8003c38:	4b14      	ldr	r3, [pc, #80]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c3a:	681b      	ldr	r3, [r3, #0]
 8003c3c:	4a13      	ldr	r2, [pc, #76]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c3e:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8003c42:	6013      	str	r3, [r2, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8003c44:	f7fd fcfe 	bl	8001644 <HAL_GetTick>
 8003c48:	60b8      	str	r0, [r7, #8]

      /* Wait till PLLSAI2 is ready */
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
 8003c4a:	e009      	b.n	8003c60 <RCCEx_PLLSAI2_Config+0x18c>
      {
        if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
 8003c4c:	f7fd fcfa 	bl	8001644 <HAL_GetTick>
 8003c50:	4602      	mov	r2, r0
 8003c52:	68bb      	ldr	r3, [r7, #8]
 8003c54:	1ad3      	subs	r3, r2, r3
 8003c56:	2b02      	cmp	r3, #2
 8003c58:	d902      	bls.n	8003c60 <RCCEx_PLLSAI2_Config+0x18c>
        {
          status = HAL_TIMEOUT;
 8003c5a:	2303      	movs	r3, #3
 8003c5c:	73fb      	strb	r3, [r7, #15]
          break;
 8003c5e:	e005      	b.n	8003c6c <RCCEx_PLLSAI2_Config+0x198>
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
 8003c60:	4b0a      	ldr	r3, [pc, #40]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c62:	681b      	ldr	r3, [r3, #0]
 8003c64:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 8003c68:	2b00      	cmp	r3, #0
 8003c6a:	d0ef      	beq.n	8003c4c <RCCEx_PLLSAI2_Config+0x178>
        }
      }

      if(status == HAL_OK)
 8003c6c:	7bfb      	ldrb	r3, [r7, #15]
 8003c6e:	2b00      	cmp	r3, #0
 8003c70:	d106      	bne.n	8003c80 <RCCEx_PLLSAI2_Config+0x1ac>
      {
        /* Configure the PLLSAI2 Clock output(s) */
        __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
 8003c72:	4b06      	ldr	r3, [pc, #24]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c74:	695a      	ldr	r2, [r3, #20]
 8003c76:	687b      	ldr	r3, [r7, #4]
 8003c78:	695b      	ldr	r3, [r3, #20]
 8003c7a:	4904      	ldr	r1, [pc, #16]	@ (8003c8c <RCCEx_PLLSAI2_Config+0x1b8>)
 8003c7c:	4313      	orrs	r3, r2
 8003c7e:	614b      	str	r3, [r1, #20]
      }
    }
  }

  return status;
 8003c80:	7bfb      	ldrb	r3, [r7, #15]
}
 8003c82:	4618      	mov	r0, r3
 8003c84:	3710      	adds	r7, #16
 8003c86:	46bd      	mov	sp, r7
 8003c88:	bd80      	pop	{r7, pc}
 8003c8a:	bf00      	nop
 8003c8c:	40021000 	.word	0x40021000

08003c90 <HAL_SPI_Init>:
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  *               the configuration information for SPI module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
 8003c90:	b580      	push	{r7, lr}
 8003c92:	b084      	sub	sp, #16
 8003c94:	af00      	add	r7, sp, #0
 8003c96:	6078      	str	r0, [r7, #4]
  uint32_t frxth;

  /* Check the SPI handle allocation */
  if (hspi == NULL)
 8003c98:	687b      	ldr	r3, [r7, #4]
 8003c9a:	2b00      	cmp	r3, #0
 8003c9c:	d101      	bne.n	8003ca2 <HAL_SPI_Init+0x12>
  {
    return HAL_ERROR;
 8003c9e:	2301      	movs	r3, #1
 8003ca0:	e095      	b.n	8003dce <HAL_SPI_Init+0x13e>
  assert_param(IS_SPI_NSS(hspi->Init.NSS));
  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
 8003ca2:	687b      	ldr	r3, [r7, #4]
 8003ca4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003ca6:	2b00      	cmp	r3, #0
 8003ca8:	d108      	bne.n	8003cbc <HAL_SPI_Init+0x2c>
  {
    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));

    if (hspi->Init.Mode == SPI_MODE_MASTER)
 8003caa:	687b      	ldr	r3, [r7, #4]
 8003cac:	685b      	ldr	r3, [r3, #4]
 8003cae:	f5b3 7f82 	cmp.w	r3, #260	@ 0x104
 8003cb2:	d009      	beq.n	8003cc8 <HAL_SPI_Init+0x38>
      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
    }
    else
    {
      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
 8003cb4:	687b      	ldr	r3, [r7, #4]
 8003cb6:	2200      	movs	r2, #0
 8003cb8:	61da      	str	r2, [r3, #28]
 8003cba:	e005      	b.n	8003cc8 <HAL_SPI_Init+0x38>
  else
  {
    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));

    /* Force polarity and phase to TI protocaol requirements */
    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
 8003cbc:	687b      	ldr	r3, [r7, #4]
 8003cbe:	2200      	movs	r2, #0
 8003cc0:	611a      	str	r2, [r3, #16]
    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
 8003cc2:	687b      	ldr	r3, [r7, #4]
 8003cc4:	2200      	movs	r2, #0
 8003cc6:	615a      	str	r2, [r3, #20]
  {
    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
  }
#else
  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 8003cc8:	687b      	ldr	r3, [r7, #4]
 8003cca:	2200      	movs	r2, #0
 8003ccc:	629a      	str	r2, [r3, #40]	@ 0x28
#endif /* USE_SPI_CRC */

  if (hspi->State == HAL_SPI_STATE_RESET)
 8003cce:	687b      	ldr	r3, [r7, #4]
 8003cd0:	f893 305d 	ldrb.w	r3, [r3, #93]	@ 0x5d
 8003cd4:	b2db      	uxtb	r3, r3
 8003cd6:	2b00      	cmp	r3, #0
 8003cd8:	d106      	bne.n	8003ce8 <HAL_SPI_Init+0x58>
  {
    /* Allocate lock resource and initialize it */
    hspi->Lock = HAL_UNLOCKED;
 8003cda:	687b      	ldr	r3, [r7, #4]
 8003cdc:	2200      	movs	r2, #0
 8003cde:	f883 205c 	strb.w	r2, [r3, #92]	@ 0x5c

    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
    hspi->MspInitCallback(hspi);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
    HAL_SPI_MspInit(hspi);
 8003ce2:	6878      	ldr	r0, [r7, #4]
 8003ce4:	f7fd f9f4 	bl	80010d0 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  }

  hspi->State = HAL_SPI_STATE_BUSY;
 8003ce8:	687b      	ldr	r3, [r7, #4]
 8003cea:	2202      	movs	r2, #2
 8003cec:	f883 205d 	strb.w	r2, [r3, #93]	@ 0x5d

  /* Disable the selected SPI peripheral */
  __HAL_SPI_DISABLE(hspi);
 8003cf0:	687b      	ldr	r3, [r7, #4]
 8003cf2:	681b      	ldr	r3, [r3, #0]
 8003cf4:	681a      	ldr	r2, [r3, #0]
 8003cf6:	687b      	ldr	r3, [r7, #4]
 8003cf8:	681b      	ldr	r3, [r3, #0]
 8003cfa:	f022 0240 	bic.w	r2, r2, #64	@ 0x40
 8003cfe:	601a      	str	r2, [r3, #0]

  /* Align by default the rs fifo threshold on the data size */
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 8003d00:	687b      	ldr	r3, [r7, #4]
 8003d02:	68db      	ldr	r3, [r3, #12]
 8003d04:	f5b3 6fe0 	cmp.w	r3, #1792	@ 0x700
 8003d08:	d902      	bls.n	8003d10 <HAL_SPI_Init+0x80>
  {
    frxth = SPI_RXFIFO_THRESHOLD_HF;
 8003d0a:	2300      	movs	r3, #0
 8003d0c:	60fb      	str	r3, [r7, #12]
 8003d0e:	e002      	b.n	8003d16 <HAL_SPI_Init+0x86>
  }
  else
  {
    frxth = SPI_RXFIFO_THRESHOLD_QF;
 8003d10:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
 8003d14:	60fb      	str	r3, [r7, #12]
  }

  /* CRC calculation is valid only for 16Bit and 8 Bit */
  if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
 8003d16:	687b      	ldr	r3, [r7, #4]
 8003d18:	68db      	ldr	r3, [r3, #12]
 8003d1a:	f5b3 6f70 	cmp.w	r3, #3840	@ 0xf00
 8003d1e:	d007      	beq.n	8003d30 <HAL_SPI_Init+0xa0>
 8003d20:	687b      	ldr	r3, [r7, #4]
 8003d22:	68db      	ldr	r3, [r3, #12]
 8003d24:	f5b3 6fe0 	cmp.w	r3, #1792	@ 0x700
 8003d28:	d002      	beq.n	8003d30 <HAL_SPI_Init+0xa0>
  {
    /* CRC must be disabled */
    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 8003d2a:	687b      	ldr	r3, [r7, #4]
 8003d2c:	2200      	movs	r2, #0
 8003d2e:	629a      	str	r2, [r3, #40]	@ 0x28
  }

  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
  Communication speed, First bit and CRC calculation state */
  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
 8003d30:	687b      	ldr	r3, [r7, #4]
 8003d32:	685b      	ldr	r3, [r3, #4]
 8003d34:	f403 7282 	and.w	r2, r3, #260	@ 0x104
 8003d38:	687b      	ldr	r3, [r7, #4]
 8003d3a:	689b      	ldr	r3, [r3, #8]
 8003d3c:	f403 4304 	and.w	r3, r3, #33792	@ 0x8400
 8003d40:	431a      	orrs	r2, r3
 8003d42:	687b      	ldr	r3, [r7, #4]
 8003d44:	691b      	ldr	r3, [r3, #16]
 8003d46:	f003 0302 	and.w	r3, r3, #2
 8003d4a:	431a      	orrs	r2, r3
 8003d4c:	687b      	ldr	r3, [r7, #4]
 8003d4e:	695b      	ldr	r3, [r3, #20]
 8003d50:	f003 0301 	and.w	r3, r3, #1
 8003d54:	431a      	orrs	r2, r3
 8003d56:	687b      	ldr	r3, [r7, #4]
 8003d58:	699b      	ldr	r3, [r3, #24]
 8003d5a:	f403 7300 	and.w	r3, r3, #512	@ 0x200
 8003d5e:	431a      	orrs	r2, r3
 8003d60:	687b      	ldr	r3, [r7, #4]
 8003d62:	69db      	ldr	r3, [r3, #28]
 8003d64:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 8003d68:	431a      	orrs	r2, r3
 8003d6a:	687b      	ldr	r3, [r7, #4]
 8003d6c:	6a1b      	ldr	r3, [r3, #32]
 8003d6e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8003d72:	ea42 0103 	orr.w	r1, r2, r3
 8003d76:	687b      	ldr	r3, [r7, #4]
 8003d78:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8003d7a:	f403 5200 	and.w	r2, r3, #8192	@ 0x2000
 8003d7e:	687b      	ldr	r3, [r7, #4]
 8003d80:	681b      	ldr	r3, [r3, #0]
 8003d82:	430a      	orrs	r2, r1
 8003d84:	601a      	str	r2, [r3, #0]
    }
  }
#endif /* USE_SPI_CRC */

  /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
 8003d86:	687b      	ldr	r3, [r7, #4]
 8003d88:	699b      	ldr	r3, [r3, #24]
 8003d8a:	0c1b      	lsrs	r3, r3, #16
 8003d8c:	f003 0204 	and.w	r2, r3, #4
 8003d90:	687b      	ldr	r3, [r7, #4]
 8003d92:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003d94:	f003 0310 	and.w	r3, r3, #16
 8003d98:	431a      	orrs	r2, r3
 8003d9a:	687b      	ldr	r3, [r7, #4]
 8003d9c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8003d9e:	f003 0308 	and.w	r3, r3, #8
 8003da2:	431a      	orrs	r2, r3
 8003da4:	687b      	ldr	r3, [r7, #4]
 8003da6:	68db      	ldr	r3, [r3, #12]
 8003da8:	f403 6370 	and.w	r3, r3, #3840	@ 0xf00
 8003dac:	ea42 0103 	orr.w	r1, r2, r3
 8003db0:	68fb      	ldr	r3, [r7, #12]
 8003db2:	f403 5280 	and.w	r2, r3, #4096	@ 0x1000
 8003db6:	687b      	ldr	r3, [r7, #4]
 8003db8:	681b      	ldr	r3, [r3, #0]
 8003dba:	430a      	orrs	r2, r1
 8003dbc:	605a      	str	r2, [r3, #4]
#if defined(SPI_I2SCFGR_I2SMOD)
  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
#endif /* SPI_I2SCFGR_I2SMOD */

  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 8003dbe:	687b      	ldr	r3, [r7, #4]
 8003dc0:	2200      	movs	r2, #0
 8003dc2:	661a      	str	r2, [r3, #96]	@ 0x60
  hspi->State     = HAL_SPI_STATE_READY;
 8003dc4:	687b      	ldr	r3, [r7, #4]
 8003dc6:	2201      	movs	r2, #1
 8003dc8:	f883 205d 	strb.w	r2, [r3, #93]	@ 0x5d

  return HAL_OK;
 8003dcc:	2300      	movs	r3, #0
}
 8003dce:	4618      	mov	r0, r3
 8003dd0:	3710      	adds	r7, #16
 8003dd2:	46bd      	mov	sp, r7
 8003dd4:	bd80      	pop	{r7, pc}

08003dd6 <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 8003dd6:	b580      	push	{r7, lr}
 8003dd8:	b082      	sub	sp, #8
 8003dda:	af00      	add	r7, sp, #0
 8003ddc:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 8003dde:	687b      	ldr	r3, [r7, #4]
 8003de0:	2b00      	cmp	r3, #0
 8003de2:	d101      	bne.n	8003de8 <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 8003de4:	2301      	movs	r3, #1
 8003de6:	e049      	b.n	8003e7c <HAL_TIM_Base_Init+0xa6>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8003de8:	687b      	ldr	r3, [r7, #4]
 8003dea:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 8003dee:	b2db      	uxtb	r3, r3
 8003df0:	2b00      	cmp	r3, #0
 8003df2:	d106      	bne.n	8003e02 <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 8003df4:	687b      	ldr	r3, [r7, #4]
 8003df6:	2200      	movs	r2, #0
 8003df8:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 8003dfc:	6878      	ldr	r0, [r7, #4]
 8003dfe:	f000 f841 	bl	8003e84 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8003e02:	687b      	ldr	r3, [r7, #4]
 8003e04:	2202      	movs	r2, #2
 8003e06:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8003e0a:	687b      	ldr	r3, [r7, #4]
 8003e0c:	681a      	ldr	r2, [r3, #0]
 8003e0e:	687b      	ldr	r3, [r7, #4]
 8003e10:	3304      	adds	r3, #4
 8003e12:	4619      	mov	r1, r3
 8003e14:	4610      	mov	r0, r2
 8003e16:	f000 f9df 	bl	80041d8 <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8003e1a:	687b      	ldr	r3, [r7, #4]
 8003e1c:	2201      	movs	r2, #1
 8003e1e:	f883 2048 	strb.w	r2, [r3, #72]	@ 0x48

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8003e22:	687b      	ldr	r3, [r7, #4]
 8003e24:	2201      	movs	r2, #1
 8003e26:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 8003e2a:	687b      	ldr	r3, [r7, #4]
 8003e2c:	2201      	movs	r2, #1
 8003e2e:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 8003e32:	687b      	ldr	r3, [r7, #4]
 8003e34:	2201      	movs	r2, #1
 8003e36:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 8003e3a:	687b      	ldr	r3, [r7, #4]
 8003e3c:	2201      	movs	r2, #1
 8003e3e:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 8003e42:	687b      	ldr	r3, [r7, #4]
 8003e44:	2201      	movs	r2, #1
 8003e46:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 8003e4a:	687b      	ldr	r3, [r7, #4]
 8003e4c:	2201      	movs	r2, #1
 8003e4e:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8003e52:	687b      	ldr	r3, [r7, #4]
 8003e54:	2201      	movs	r2, #1
 8003e56:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8003e5a:	687b      	ldr	r3, [r7, #4]
 8003e5c:	2201      	movs	r2, #1
 8003e5e:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8003e62:	687b      	ldr	r3, [r7, #4]
 8003e64:	2201      	movs	r2, #1
 8003e66:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
 8003e6a:	687b      	ldr	r3, [r7, #4]
 8003e6c:	2201      	movs	r2, #1
 8003e6e:	f883 2047 	strb.w	r2, [r3, #71]	@ 0x47

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 8003e72:	687b      	ldr	r3, [r7, #4]
 8003e74:	2201      	movs	r2, #1
 8003e76:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  return HAL_OK;
 8003e7a:	2300      	movs	r3, #0
}
 8003e7c:	4618      	mov	r0, r3
 8003e7e:	3708      	adds	r7, #8
 8003e80:	46bd      	mov	sp, r7
 8003e82:	bd80      	pop	{r7, pc}

08003e84 <HAL_TIM_Base_MspInit>:
  * @brief  Initializes the TIM Base MSP.
  * @param  htim TIM Base handle
  * @retval None
  */
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
 8003e84:	b480      	push	{r7}
 8003e86:	b083      	sub	sp, #12
 8003e88:	af00      	add	r7, sp, #0
 8003e8a:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_Base_MspInit could be implemented in the user file
   */
}
 8003e8c:	bf00      	nop
 8003e8e:	370c      	adds	r7, #12
 8003e90:	46bd      	mov	sp, r7
 8003e92:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e96:	4770      	bx	lr

08003e98 <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 8003e98:	b480      	push	{r7}
 8003e9a:	b085      	sub	sp, #20
 8003e9c:	af00      	add	r7, sp, #0
 8003e9e:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 8003ea0:	687b      	ldr	r3, [r7, #4]
 8003ea2:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 8003ea6:	b2db      	uxtb	r3, r3
 8003ea8:	2b01      	cmp	r3, #1
 8003eaa:	d001      	beq.n	8003eb0 <HAL_TIM_Base_Start_IT+0x18>
  {
    return HAL_ERROR;
 8003eac:	2301      	movs	r3, #1
 8003eae:	e04f      	b.n	8003f50 <HAL_TIM_Base_Start_IT+0xb8>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8003eb0:	687b      	ldr	r3, [r7, #4]
 8003eb2:	2202      	movs	r2, #2
 8003eb4:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 8003eb8:	687b      	ldr	r3, [r7, #4]
 8003eba:	681b      	ldr	r3, [r3, #0]
 8003ebc:	68da      	ldr	r2, [r3, #12]
 8003ebe:	687b      	ldr	r3, [r7, #4]
 8003ec0:	681b      	ldr	r3, [r3, #0]
 8003ec2:	f042 0201 	orr.w	r2, r2, #1
 8003ec6:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8003ec8:	687b      	ldr	r3, [r7, #4]
 8003eca:	681b      	ldr	r3, [r3, #0]
 8003ecc:	4a23      	ldr	r2, [pc, #140]	@ (8003f5c <HAL_TIM_Base_Start_IT+0xc4>)
 8003ece:	4293      	cmp	r3, r2
 8003ed0:	d01d      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003ed2:	687b      	ldr	r3, [r7, #4]
 8003ed4:	681b      	ldr	r3, [r3, #0]
 8003ed6:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8003eda:	d018      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003edc:	687b      	ldr	r3, [r7, #4]
 8003ede:	681b      	ldr	r3, [r3, #0]
 8003ee0:	4a1f      	ldr	r2, [pc, #124]	@ (8003f60 <HAL_TIM_Base_Start_IT+0xc8>)
 8003ee2:	4293      	cmp	r3, r2
 8003ee4:	d013      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003ee6:	687b      	ldr	r3, [r7, #4]
 8003ee8:	681b      	ldr	r3, [r3, #0]
 8003eea:	4a1e      	ldr	r2, [pc, #120]	@ (8003f64 <HAL_TIM_Base_Start_IT+0xcc>)
 8003eec:	4293      	cmp	r3, r2
 8003eee:	d00e      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003ef0:	687b      	ldr	r3, [r7, #4]
 8003ef2:	681b      	ldr	r3, [r3, #0]
 8003ef4:	4a1c      	ldr	r2, [pc, #112]	@ (8003f68 <HAL_TIM_Base_Start_IT+0xd0>)
 8003ef6:	4293      	cmp	r3, r2
 8003ef8:	d009      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003efa:	687b      	ldr	r3, [r7, #4]
 8003efc:	681b      	ldr	r3, [r3, #0]
 8003efe:	4a1b      	ldr	r2, [pc, #108]	@ (8003f6c <HAL_TIM_Base_Start_IT+0xd4>)
 8003f00:	4293      	cmp	r3, r2
 8003f02:	d004      	beq.n	8003f0e <HAL_TIM_Base_Start_IT+0x76>
 8003f04:	687b      	ldr	r3, [r7, #4]
 8003f06:	681b      	ldr	r3, [r3, #0]
 8003f08:	4a19      	ldr	r2, [pc, #100]	@ (8003f70 <HAL_TIM_Base_Start_IT+0xd8>)
 8003f0a:	4293      	cmp	r3, r2
 8003f0c:	d115      	bne.n	8003f3a <HAL_TIM_Base_Start_IT+0xa2>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8003f0e:	687b      	ldr	r3, [r7, #4]
 8003f10:	681b      	ldr	r3, [r3, #0]
 8003f12:	689a      	ldr	r2, [r3, #8]
 8003f14:	4b17      	ldr	r3, [pc, #92]	@ (8003f74 <HAL_TIM_Base_Start_IT+0xdc>)
 8003f16:	4013      	ands	r3, r2
 8003f18:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003f1a:	68fb      	ldr	r3, [r7, #12]
 8003f1c:	2b06      	cmp	r3, #6
 8003f1e:	d015      	beq.n	8003f4c <HAL_TIM_Base_Start_IT+0xb4>
 8003f20:	68fb      	ldr	r3, [r7, #12]
 8003f22:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8003f26:	d011      	beq.n	8003f4c <HAL_TIM_Base_Start_IT+0xb4>
    {
      __HAL_TIM_ENABLE(htim);
 8003f28:	687b      	ldr	r3, [r7, #4]
 8003f2a:	681b      	ldr	r3, [r3, #0]
 8003f2c:	681a      	ldr	r2, [r3, #0]
 8003f2e:	687b      	ldr	r3, [r7, #4]
 8003f30:	681b      	ldr	r3, [r3, #0]
 8003f32:	f042 0201 	orr.w	r2, r2, #1
 8003f36:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003f38:	e008      	b.n	8003f4c <HAL_TIM_Base_Start_IT+0xb4>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 8003f3a:	687b      	ldr	r3, [r7, #4]
 8003f3c:	681b      	ldr	r3, [r3, #0]
 8003f3e:	681a      	ldr	r2, [r3, #0]
 8003f40:	687b      	ldr	r3, [r7, #4]
 8003f42:	681b      	ldr	r3, [r3, #0]
 8003f44:	f042 0201 	orr.w	r2, r2, #1
 8003f48:	601a      	str	r2, [r3, #0]
 8003f4a:	e000      	b.n	8003f4e <HAL_TIM_Base_Start_IT+0xb6>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003f4c:	bf00      	nop
  }

  /* Return function status */
  return HAL_OK;
 8003f4e:	2300      	movs	r3, #0
}
 8003f50:	4618      	mov	r0, r3
 8003f52:	3714      	adds	r7, #20
 8003f54:	46bd      	mov	sp, r7
 8003f56:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f5a:	4770      	bx	lr
 8003f5c:	40012c00 	.word	0x40012c00
 8003f60:	40000400 	.word	0x40000400
 8003f64:	40000800 	.word	0x40000800
 8003f68:	40000c00 	.word	0x40000c00
 8003f6c:	40013400 	.word	0x40013400
 8003f70:	40014000 	.word	0x40014000
 8003f74:	00010007 	.word	0x00010007

08003f78 <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 8003f78:	b580      	push	{r7, lr}
 8003f7a:	b084      	sub	sp, #16
 8003f7c:	af00      	add	r7, sp, #0
 8003f7e:	6078      	str	r0, [r7, #4]
  uint32_t itsource = htim->Instance->DIER;
 8003f80:	687b      	ldr	r3, [r7, #4]
 8003f82:	681b      	ldr	r3, [r3, #0]
 8003f84:	68db      	ldr	r3, [r3, #12]
 8003f86:	60fb      	str	r3, [r7, #12]
  uint32_t itflag   = htim->Instance->SR;
 8003f88:	687b      	ldr	r3, [r7, #4]
 8003f8a:	681b      	ldr	r3, [r3, #0]
 8003f8c:	691b      	ldr	r3, [r3, #16]
 8003f8e:	60bb      	str	r3, [r7, #8]

  /* Capture compare 1 event */
  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
 8003f90:	68bb      	ldr	r3, [r7, #8]
 8003f92:	f003 0302 	and.w	r3, r3, #2
 8003f96:	2b00      	cmp	r3, #0
 8003f98:	d020      	beq.n	8003fdc <HAL_TIM_IRQHandler+0x64>
  {
    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
 8003f9a:	68fb      	ldr	r3, [r7, #12]
 8003f9c:	f003 0302 	and.w	r3, r3, #2
 8003fa0:	2b00      	cmp	r3, #0
 8003fa2:	d01b      	beq.n	8003fdc <HAL_TIM_IRQHandler+0x64>
    {
      {
        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
 8003fa4:	687b      	ldr	r3, [r7, #4]
 8003fa6:	681b      	ldr	r3, [r3, #0]
 8003fa8:	f06f 0202 	mvn.w	r2, #2
 8003fac:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 8003fae:	687b      	ldr	r3, [r7, #4]
 8003fb0:	2201      	movs	r2, #1
 8003fb2:	771a      	strb	r2, [r3, #28]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 8003fb4:	687b      	ldr	r3, [r7, #4]
 8003fb6:	681b      	ldr	r3, [r3, #0]
 8003fb8:	699b      	ldr	r3, [r3, #24]
 8003fba:	f003 0303 	and.w	r3, r3, #3
 8003fbe:	2b00      	cmp	r3, #0
 8003fc0:	d003      	beq.n	8003fca <HAL_TIM_IRQHandler+0x52>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 8003fc2:	6878      	ldr	r0, [r7, #4]
 8003fc4:	f000 f8e9 	bl	800419a <HAL_TIM_IC_CaptureCallback>
 8003fc8:	e005      	b.n	8003fd6 <HAL_TIM_IRQHandler+0x5e>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 8003fca:	6878      	ldr	r0, [r7, #4]
 8003fcc:	f000 f8db 	bl	8004186 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003fd0:	6878      	ldr	r0, [r7, #4]
 8003fd2:	f000 f8ec 	bl	80041ae <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8003fd6:	687b      	ldr	r3, [r7, #4]
 8003fd8:	2200      	movs	r2, #0
 8003fda:	771a      	strb	r2, [r3, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
 8003fdc:	68bb      	ldr	r3, [r7, #8]
 8003fde:	f003 0304 	and.w	r3, r3, #4
 8003fe2:	2b00      	cmp	r3, #0
 8003fe4:	d020      	beq.n	8004028 <HAL_TIM_IRQHandler+0xb0>
  {
    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
 8003fe6:	68fb      	ldr	r3, [r7, #12]
 8003fe8:	f003 0304 	and.w	r3, r3, #4
 8003fec:	2b00      	cmp	r3, #0
 8003fee:	d01b      	beq.n	8004028 <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
 8003ff0:	687b      	ldr	r3, [r7, #4]
 8003ff2:	681b      	ldr	r3, [r3, #0]
 8003ff4:	f06f 0204 	mvn.w	r2, #4
 8003ff8:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8003ffa:	687b      	ldr	r3, [r7, #4]
 8003ffc:	2202      	movs	r2, #2
 8003ffe:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8004000:	687b      	ldr	r3, [r7, #4]
 8004002:	681b      	ldr	r3, [r3, #0]
 8004004:	699b      	ldr	r3, [r3, #24]
 8004006:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 800400a:	2b00      	cmp	r3, #0
 800400c:	d003      	beq.n	8004016 <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800400e:	6878      	ldr	r0, [r7, #4]
 8004010:	f000 f8c3 	bl	800419a <HAL_TIM_IC_CaptureCallback>
 8004014:	e005      	b.n	8004022 <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8004016:	6878      	ldr	r0, [r7, #4]
 8004018:	f000 f8b5 	bl	8004186 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800401c:	6878      	ldr	r0, [r7, #4]
 800401e:	f000 f8c6 	bl	80041ae <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8004022:	687b      	ldr	r3, [r7, #4]
 8004024:	2200      	movs	r2, #0
 8004026:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 3 event */
  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
 8004028:	68bb      	ldr	r3, [r7, #8]
 800402a:	f003 0308 	and.w	r3, r3, #8
 800402e:	2b00      	cmp	r3, #0
 8004030:	d020      	beq.n	8004074 <HAL_TIM_IRQHandler+0xfc>
  {
    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
 8004032:	68fb      	ldr	r3, [r7, #12]
 8004034:	f003 0308 	and.w	r3, r3, #8
 8004038:	2b00      	cmp	r3, #0
 800403a:	d01b      	beq.n	8004074 <HAL_TIM_IRQHandler+0xfc>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
 800403c:	687b      	ldr	r3, [r7, #4]
 800403e:	681b      	ldr	r3, [r3, #0]
 8004040:	f06f 0208 	mvn.w	r2, #8
 8004044:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8004046:	687b      	ldr	r3, [r7, #4]
 8004048:	2204      	movs	r2, #4
 800404a:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800404c:	687b      	ldr	r3, [r7, #4]
 800404e:	681b      	ldr	r3, [r3, #0]
 8004050:	69db      	ldr	r3, [r3, #28]
 8004052:	f003 0303 	and.w	r3, r3, #3
 8004056:	2b00      	cmp	r3, #0
 8004058:	d003      	beq.n	8004062 <HAL_TIM_IRQHandler+0xea>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800405a:	6878      	ldr	r0, [r7, #4]
 800405c:	f000 f89d 	bl	800419a <HAL_TIM_IC_CaptureCallback>
 8004060:	e005      	b.n	800406e <HAL_TIM_IRQHandler+0xf6>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8004062:	6878      	ldr	r0, [r7, #4]
 8004064:	f000 f88f 	bl	8004186 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8004068:	6878      	ldr	r0, [r7, #4]
 800406a:	f000 f8a0 	bl	80041ae <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800406e:	687b      	ldr	r3, [r7, #4]
 8004070:	2200      	movs	r2, #0
 8004072:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 4 event */
  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
 8004074:	68bb      	ldr	r3, [r7, #8]
 8004076:	f003 0310 	and.w	r3, r3, #16
 800407a:	2b00      	cmp	r3, #0
 800407c:	d020      	beq.n	80040c0 <HAL_TIM_IRQHandler+0x148>
  {
    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
 800407e:	68fb      	ldr	r3, [r7, #12]
 8004080:	f003 0310 	and.w	r3, r3, #16
 8004084:	2b00      	cmp	r3, #0
 8004086:	d01b      	beq.n	80040c0 <HAL_TIM_IRQHandler+0x148>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
 8004088:	687b      	ldr	r3, [r7, #4]
 800408a:	681b      	ldr	r3, [r3, #0]
 800408c:	f06f 0210 	mvn.w	r2, #16
 8004090:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8004092:	687b      	ldr	r3, [r7, #4]
 8004094:	2208      	movs	r2, #8
 8004096:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8004098:	687b      	ldr	r3, [r7, #4]
 800409a:	681b      	ldr	r3, [r3, #0]
 800409c:	69db      	ldr	r3, [r3, #28]
 800409e:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 80040a2:	2b00      	cmp	r3, #0
 80040a4:	d003      	beq.n	80040ae <HAL_TIM_IRQHandler+0x136>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 80040a6:	6878      	ldr	r0, [r7, #4]
 80040a8:	f000 f877 	bl	800419a <HAL_TIM_IC_CaptureCallback>
 80040ac:	e005      	b.n	80040ba <HAL_TIM_IRQHandler+0x142>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80040ae:	6878      	ldr	r0, [r7, #4]
 80040b0:	f000 f869 	bl	8004186 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80040b4:	6878      	ldr	r0, [r7, #4]
 80040b6:	f000 f87a 	bl	80041ae <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80040ba:	687b      	ldr	r3, [r7, #4]
 80040bc:	2200      	movs	r2, #0
 80040be:	771a      	strb	r2, [r3, #28]
    }
  }
  /* TIM Update event */
  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
 80040c0:	68bb      	ldr	r3, [r7, #8]
 80040c2:	f003 0301 	and.w	r3, r3, #1
 80040c6:	2b00      	cmp	r3, #0
 80040c8:	d00c      	beq.n	80040e4 <HAL_TIM_IRQHandler+0x16c>
  {
    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
 80040ca:	68fb      	ldr	r3, [r7, #12]
 80040cc:	f003 0301 	and.w	r3, r3, #1
 80040d0:	2b00      	cmp	r3, #0
 80040d2:	d007      	beq.n	80040e4 <HAL_TIM_IRQHandler+0x16c>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
 80040d4:	687b      	ldr	r3, [r7, #4]
 80040d6:	681b      	ldr	r3, [r3, #0]
 80040d8:	f06f 0201 	mvn.w	r2, #1
 80040dc:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 80040de:	6878      	ldr	r0, [r7, #4]
 80040e0:	f7fc fdbe 	bl	8000c60 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 80040e4:	68bb      	ldr	r3, [r7, #8]
 80040e6:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80040ea:	2b00      	cmp	r3, #0
 80040ec:	d104      	bne.n	80040f8 <HAL_TIM_IRQHandler+0x180>
      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
 80040ee:	68bb      	ldr	r3, [r7, #8]
 80040f0:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 80040f4:	2b00      	cmp	r3, #0
 80040f6:	d00c      	beq.n	8004112 <HAL_TIM_IRQHandler+0x19a>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 80040f8:	68fb      	ldr	r3, [r7, #12]
 80040fa:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80040fe:	2b00      	cmp	r3, #0
 8004100:	d007      	beq.n	8004112 <HAL_TIM_IRQHandler+0x19a>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
 8004102:	687b      	ldr	r3, [r7, #4]
 8004104:	681b      	ldr	r3, [r3, #0]
 8004106:	f46f 5202 	mvn.w	r2, #8320	@ 0x2080
 800410a:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 800410c:	6878      	ldr	r0, [r7, #4]
 800410e:	f000 f913 	bl	8004338 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break2 input event */
  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
 8004112:	68bb      	ldr	r3, [r7, #8]
 8004114:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8004118:	2b00      	cmp	r3, #0
 800411a:	d00c      	beq.n	8004136 <HAL_TIM_IRQHandler+0x1be>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 800411c:	68fb      	ldr	r3, [r7, #12]
 800411e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8004122:	2b00      	cmp	r3, #0
 8004124:	d007      	beq.n	8004136 <HAL_TIM_IRQHandler+0x1be>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
 8004126:	687b      	ldr	r3, [r7, #4]
 8004128:	681b      	ldr	r3, [r3, #0]
 800412a:	f46f 7280 	mvn.w	r2, #256	@ 0x100
 800412e:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->Break2Callback(htim);
#else
      HAL_TIMEx_Break2Callback(htim);
 8004130:	6878      	ldr	r0, [r7, #4]
 8004132:	f000 f90b 	bl	800434c <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
 8004136:	68bb      	ldr	r3, [r7, #8]
 8004138:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800413c:	2b00      	cmp	r3, #0
 800413e:	d00c      	beq.n	800415a <HAL_TIM_IRQHandler+0x1e2>
  {
    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
 8004140:	68fb      	ldr	r3, [r7, #12]
 8004142:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8004146:	2b00      	cmp	r3, #0
 8004148:	d007      	beq.n	800415a <HAL_TIM_IRQHandler+0x1e2>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
 800414a:	687b      	ldr	r3, [r7, #4]
 800414c:	681b      	ldr	r3, [r3, #0]
 800414e:	f06f 0240 	mvn.w	r2, #64	@ 0x40
 8004152:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 8004154:	6878      	ldr	r0, [r7, #4]
 8004156:	f000 f834 	bl	80041c2 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
 800415a:	68bb      	ldr	r3, [r7, #8]
 800415c:	f003 0320 	and.w	r3, r3, #32
 8004160:	2b00      	cmp	r3, #0
 8004162:	d00c      	beq.n	800417e <HAL_TIM_IRQHandler+0x206>
  {
    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
 8004164:	68fb      	ldr	r3, [r7, #12]
 8004166:	f003 0320 	and.w	r3, r3, #32
 800416a:	2b00      	cmp	r3, #0
 800416c:	d007      	beq.n	800417e <HAL_TIM_IRQHandler+0x206>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
 800416e:	687b      	ldr	r3, [r7, #4]
 8004170:	681b      	ldr	r3, [r3, #0]
 8004172:	f06f 0220 	mvn.w	r2, #32
 8004176:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 8004178:	6878      	ldr	r0, [r7, #4]
 800417a:	f000 f8d3 	bl	8004324 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 800417e:	bf00      	nop
 8004180:	3710      	adds	r7, #16
 8004182:	46bd      	mov	sp, r7
 8004184:	bd80      	pop	{r7, pc}

08004186 <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 8004186:	b480      	push	{r7}
 8004188:	b083      	sub	sp, #12
 800418a:	af00      	add	r7, sp, #0
 800418c:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 800418e:	bf00      	nop
 8004190:	370c      	adds	r7, #12
 8004192:	46bd      	mov	sp, r7
 8004194:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004198:	4770      	bx	lr

0800419a <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 800419a:	b480      	push	{r7}
 800419c:	b083      	sub	sp, #12
 800419e:	af00      	add	r7, sp, #0
 80041a0:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 80041a2:	bf00      	nop
 80041a4:	370c      	adds	r7, #12
 80041a6:	46bd      	mov	sp, r7
 80041a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041ac:	4770      	bx	lr

080041ae <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 80041ae:	b480      	push	{r7}
 80041b0:	b083      	sub	sp, #12
 80041b2:	af00      	add	r7, sp, #0
 80041b4:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 80041b6:	bf00      	nop
 80041b8:	370c      	adds	r7, #12
 80041ba:	46bd      	mov	sp, r7
 80041bc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041c0:	4770      	bx	lr

080041c2 <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 80041c2:	b480      	push	{r7}
 80041c4:	b083      	sub	sp, #12
 80041c6:	af00      	add	r7, sp, #0
 80041c8:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 80041ca:	bf00      	nop
 80041cc:	370c      	adds	r7, #12
 80041ce:	46bd      	mov	sp, r7
 80041d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041d4:	4770      	bx	lr
	...

080041d8 <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
 80041d8:	b480      	push	{r7}
 80041da:	b085      	sub	sp, #20
 80041dc:	af00      	add	r7, sp, #0
 80041de:	6078      	str	r0, [r7, #4]
 80041e0:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 80041e2:	687b      	ldr	r3, [r7, #4]
 80041e4:	681b      	ldr	r3, [r3, #0]
 80041e6:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 80041e8:	687b      	ldr	r3, [r7, #4]
 80041ea:	4a46      	ldr	r2, [pc, #280]	@ (8004304 <TIM_Base_SetConfig+0x12c>)
 80041ec:	4293      	cmp	r3, r2
 80041ee:	d013      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 80041f0:	687b      	ldr	r3, [r7, #4]
 80041f2:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 80041f6:	d00f      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 80041f8:	687b      	ldr	r3, [r7, #4]
 80041fa:	4a43      	ldr	r2, [pc, #268]	@ (8004308 <TIM_Base_SetConfig+0x130>)
 80041fc:	4293      	cmp	r3, r2
 80041fe:	d00b      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 8004200:	687b      	ldr	r3, [r7, #4]
 8004202:	4a42      	ldr	r2, [pc, #264]	@ (800430c <TIM_Base_SetConfig+0x134>)
 8004204:	4293      	cmp	r3, r2
 8004206:	d007      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 8004208:	687b      	ldr	r3, [r7, #4]
 800420a:	4a41      	ldr	r2, [pc, #260]	@ (8004310 <TIM_Base_SetConfig+0x138>)
 800420c:	4293      	cmp	r3, r2
 800420e:	d003      	beq.n	8004218 <TIM_Base_SetConfig+0x40>
 8004210:	687b      	ldr	r3, [r7, #4]
 8004212:	4a40      	ldr	r2, [pc, #256]	@ (8004314 <TIM_Base_SetConfig+0x13c>)
 8004214:	4293      	cmp	r3, r2
 8004216:	d108      	bne.n	800422a <TIM_Base_SetConfig+0x52>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8004218:	68fb      	ldr	r3, [r7, #12]
 800421a:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 800421e:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 8004220:	683b      	ldr	r3, [r7, #0]
 8004222:	685b      	ldr	r3, [r3, #4]
 8004224:	68fa      	ldr	r2, [r7, #12]
 8004226:	4313      	orrs	r3, r2
 8004228:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 800422a:	687b      	ldr	r3, [r7, #4]
 800422c:	4a35      	ldr	r2, [pc, #212]	@ (8004304 <TIM_Base_SetConfig+0x12c>)
 800422e:	4293      	cmp	r3, r2
 8004230:	d01f      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 8004232:	687b      	ldr	r3, [r7, #4]
 8004234:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8004238:	d01b      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 800423a:	687b      	ldr	r3, [r7, #4]
 800423c:	4a32      	ldr	r2, [pc, #200]	@ (8004308 <TIM_Base_SetConfig+0x130>)
 800423e:	4293      	cmp	r3, r2
 8004240:	d017      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 8004242:	687b      	ldr	r3, [r7, #4]
 8004244:	4a31      	ldr	r2, [pc, #196]	@ (800430c <TIM_Base_SetConfig+0x134>)
 8004246:	4293      	cmp	r3, r2
 8004248:	d013      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 800424a:	687b      	ldr	r3, [r7, #4]
 800424c:	4a30      	ldr	r2, [pc, #192]	@ (8004310 <TIM_Base_SetConfig+0x138>)
 800424e:	4293      	cmp	r3, r2
 8004250:	d00f      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 8004252:	687b      	ldr	r3, [r7, #4]
 8004254:	4a2f      	ldr	r2, [pc, #188]	@ (8004314 <TIM_Base_SetConfig+0x13c>)
 8004256:	4293      	cmp	r3, r2
 8004258:	d00b      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 800425a:	687b      	ldr	r3, [r7, #4]
 800425c:	4a2e      	ldr	r2, [pc, #184]	@ (8004318 <TIM_Base_SetConfig+0x140>)
 800425e:	4293      	cmp	r3, r2
 8004260:	d007      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 8004262:	687b      	ldr	r3, [r7, #4]
 8004264:	4a2d      	ldr	r2, [pc, #180]	@ (800431c <TIM_Base_SetConfig+0x144>)
 8004266:	4293      	cmp	r3, r2
 8004268:	d003      	beq.n	8004272 <TIM_Base_SetConfig+0x9a>
 800426a:	687b      	ldr	r3, [r7, #4]
 800426c:	4a2c      	ldr	r2, [pc, #176]	@ (8004320 <TIM_Base_SetConfig+0x148>)
 800426e:	4293      	cmp	r3, r2
 8004270:	d108      	bne.n	8004284 <TIM_Base_SetConfig+0xac>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 8004272:	68fb      	ldr	r3, [r7, #12]
 8004274:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8004278:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800427a:	683b      	ldr	r3, [r7, #0]
 800427c:	68db      	ldr	r3, [r3, #12]
 800427e:	68fa      	ldr	r2, [r7, #12]
 8004280:	4313      	orrs	r3, r2
 8004282:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8004284:	68fb      	ldr	r3, [r7, #12]
 8004286:	f023 0280 	bic.w	r2, r3, #128	@ 0x80
 800428a:	683b      	ldr	r3, [r7, #0]
 800428c:	695b      	ldr	r3, [r3, #20]
 800428e:	4313      	orrs	r3, r2
 8004290:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 8004292:	687b      	ldr	r3, [r7, #4]
 8004294:	68fa      	ldr	r2, [r7, #12]
 8004296:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8004298:	683b      	ldr	r3, [r7, #0]
 800429a:	689a      	ldr	r2, [r3, #8]
 800429c:	687b      	ldr	r3, [r7, #4]
 800429e:	62da      	str	r2, [r3, #44]	@ 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 80042a0:	683b      	ldr	r3, [r7, #0]
 80042a2:	681a      	ldr	r2, [r3, #0]
 80042a4:	687b      	ldr	r3, [r7, #4]
 80042a6:	629a      	str	r2, [r3, #40]	@ 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 80042a8:	687b      	ldr	r3, [r7, #4]
 80042aa:	4a16      	ldr	r2, [pc, #88]	@ (8004304 <TIM_Base_SetConfig+0x12c>)
 80042ac:	4293      	cmp	r3, r2
 80042ae:	d00f      	beq.n	80042d0 <TIM_Base_SetConfig+0xf8>
 80042b0:	687b      	ldr	r3, [r7, #4]
 80042b2:	4a18      	ldr	r2, [pc, #96]	@ (8004314 <TIM_Base_SetConfig+0x13c>)
 80042b4:	4293      	cmp	r3, r2
 80042b6:	d00b      	beq.n	80042d0 <TIM_Base_SetConfig+0xf8>
 80042b8:	687b      	ldr	r3, [r7, #4]
 80042ba:	4a17      	ldr	r2, [pc, #92]	@ (8004318 <TIM_Base_SetConfig+0x140>)
 80042bc:	4293      	cmp	r3, r2
 80042be:	d007      	beq.n	80042d0 <TIM_Base_SetConfig+0xf8>
 80042c0:	687b      	ldr	r3, [r7, #4]
 80042c2:	4a16      	ldr	r2, [pc, #88]	@ (800431c <TIM_Base_SetConfig+0x144>)
 80042c4:	4293      	cmp	r3, r2
 80042c6:	d003      	beq.n	80042d0 <TIM_Base_SetConfig+0xf8>
 80042c8:	687b      	ldr	r3, [r7, #4]
 80042ca:	4a15      	ldr	r2, [pc, #84]	@ (8004320 <TIM_Base_SetConfig+0x148>)
 80042cc:	4293      	cmp	r3, r2
 80042ce:	d103      	bne.n	80042d8 <TIM_Base_SetConfig+0x100>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 80042d0:	683b      	ldr	r3, [r7, #0]
 80042d2:	691a      	ldr	r2, [r3, #16]
 80042d4:	687b      	ldr	r3, [r7, #4]
 80042d6:	631a      	str	r2, [r3, #48]	@ 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 80042d8:	687b      	ldr	r3, [r7, #4]
 80042da:	2201      	movs	r2, #1
 80042dc:	615a      	str	r2, [r3, #20]

  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
 80042de:	687b      	ldr	r3, [r7, #4]
 80042e0:	691b      	ldr	r3, [r3, #16]
 80042e2:	f003 0301 	and.w	r3, r3, #1
 80042e6:	2b01      	cmp	r3, #1
 80042e8:	d105      	bne.n	80042f6 <TIM_Base_SetConfig+0x11e>
  {
    /* Clear the update flag */
    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
 80042ea:	687b      	ldr	r3, [r7, #4]
 80042ec:	691b      	ldr	r3, [r3, #16]
 80042ee:	f023 0201 	bic.w	r2, r3, #1
 80042f2:	687b      	ldr	r3, [r7, #4]
 80042f4:	611a      	str	r2, [r3, #16]
  }
}
 80042f6:	bf00      	nop
 80042f8:	3714      	adds	r7, #20
 80042fa:	46bd      	mov	sp, r7
 80042fc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004300:	4770      	bx	lr
 8004302:	bf00      	nop
 8004304:	40012c00 	.word	0x40012c00
 8004308:	40000400 	.word	0x40000400
 800430c:	40000800 	.word	0x40000800
 8004310:	40000c00 	.word	0x40000c00
 8004314:	40013400 	.word	0x40013400
 8004318:	40014000 	.word	0x40014000
 800431c:	40014400 	.word	0x40014400
 8004320:	40014800 	.word	0x40014800

08004324 <HAL_TIMEx_CommutCallback>:
  * @brief  Commutation callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
 8004324:	b480      	push	{r7}
 8004326:	b083      	sub	sp, #12
 8004328:	af00      	add	r7, sp, #0
 800432a:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
 800432c:	bf00      	nop
 800432e:	370c      	adds	r7, #12
 8004330:	46bd      	mov	sp, r7
 8004332:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004336:	4770      	bx	lr

08004338 <HAL_TIMEx_BreakCallback>:
  * @brief  Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8004338:	b480      	push	{r7}
 800433a:	b083      	sub	sp, #12
 800433c:	af00      	add	r7, sp, #0
 800433e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
 8004340:	bf00      	nop
 8004342:	370c      	adds	r7, #12
 8004344:	46bd      	mov	sp, r7
 8004346:	f85d 7b04 	ldr.w	r7, [sp], #4
 800434a:	4770      	bx	lr

0800434c <HAL_TIMEx_Break2Callback>:
  * @brief  Break2 detection callback in non blocking mode
  * @param  htim: TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
 800434c:	b480      	push	{r7}
 800434e:	b083      	sub	sp, #12
 8004350:	af00      	add	r7, sp, #0
 8004352:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_TIMEx_Break2Callback could be implemented in the user file
   */
}
 8004354:	bf00      	nop
 8004356:	370c      	adds	r7, #12
 8004358:	46bd      	mov	sp, r7
 800435a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800435e:	4770      	bx	lr

08004360 <HAL_UART_Init>:
  *        parameters in the UART_InitTypeDef and initialize the associated handle.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 8004360:	b580      	push	{r7, lr}
 8004362:	b082      	sub	sp, #8
 8004364:	af00      	add	r7, sp, #0
 8004366:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8004368:	687b      	ldr	r3, [r7, #4]
 800436a:	2b00      	cmp	r3, #0
 800436c:	d101      	bne.n	8004372 <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 800436e:	2301      	movs	r3, #1
 8004370:	e040      	b.n	80043f4 <HAL_UART_Init+0x94>
  {
    /* Check the parameters */
    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
  }

  if (huart->gState == HAL_UART_STATE_RESET)
 8004372:	687b      	ldr	r3, [r7, #4]
 8004374:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 8004376:	2b00      	cmp	r3, #0
 8004378:	d106      	bne.n	8004388 <HAL_UART_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 800437a:	687b      	ldr	r3, [r7, #4]
 800437c:	2200      	movs	r2, #0
 800437e:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 8004382:	6878      	ldr	r0, [r7, #4]
 8004384:	f7fc fee8 	bl	8001158 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 8004388:	687b      	ldr	r3, [r7, #4]
 800438a:	2224      	movs	r2, #36	@ 0x24
 800438c:	67da      	str	r2, [r3, #124]	@ 0x7c

  __HAL_UART_DISABLE(huart);
 800438e:	687b      	ldr	r3, [r7, #4]
 8004390:	681b      	ldr	r3, [r3, #0]
 8004392:	681a      	ldr	r2, [r3, #0]
 8004394:	687b      	ldr	r3, [r7, #4]
 8004396:	681b      	ldr	r3, [r3, #0]
 8004398:	f022 0201 	bic.w	r2, r2, #1
 800439c:	601a      	str	r2, [r3, #0]

  /* Perform advanced settings configuration */
  /* For some items, configuration requires to be done prior TE and RE bits are set */
  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 800439e:	687b      	ldr	r3, [r7, #4]
 80043a0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80043a2:	2b00      	cmp	r3, #0
 80043a4:	d002      	beq.n	80043ac <HAL_UART_Init+0x4c>
  {
    UART_AdvFeatureConfig(huart);
 80043a6:	6878      	ldr	r0, [r7, #4]
 80043a8:	f000 fea6 	bl	80050f8 <UART_AdvFeatureConfig>
  }

  /* Set the UART Communication parameters */
  if (UART_SetConfig(huart) == HAL_ERROR)
 80043ac:	6878      	ldr	r0, [r7, #4]
 80043ae:	f000 fbeb 	bl	8004b88 <UART_SetConfig>
 80043b2:	4603      	mov	r3, r0
 80043b4:	2b01      	cmp	r3, #1
 80043b6:	d101      	bne.n	80043bc <HAL_UART_Init+0x5c>
  {
    return HAL_ERROR;
 80043b8:	2301      	movs	r3, #1
 80043ba:	e01b      	b.n	80043f4 <HAL_UART_Init+0x94>
  }

  /* In asynchronous mode, the following bits must be kept cleared:
  - LINEN and CLKEN bits in the USART_CR2 register,
  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 80043bc:	687b      	ldr	r3, [r7, #4]
 80043be:	681b      	ldr	r3, [r3, #0]
 80043c0:	685a      	ldr	r2, [r3, #4]
 80043c2:	687b      	ldr	r3, [r7, #4]
 80043c4:	681b      	ldr	r3, [r3, #0]
 80043c6:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
 80043ca:	605a      	str	r2, [r3, #4]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 80043cc:	687b      	ldr	r3, [r7, #4]
 80043ce:	681b      	ldr	r3, [r3, #0]
 80043d0:	689a      	ldr	r2, [r3, #8]
 80043d2:	687b      	ldr	r3, [r7, #4]
 80043d4:	681b      	ldr	r3, [r3, #0]
 80043d6:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
 80043da:	609a      	str	r2, [r3, #8]

  __HAL_UART_ENABLE(huart);
 80043dc:	687b      	ldr	r3, [r7, #4]
 80043de:	681b      	ldr	r3, [r3, #0]
 80043e0:	681a      	ldr	r2, [r3, #0]
 80043e2:	687b      	ldr	r3, [r7, #4]
 80043e4:	681b      	ldr	r3, [r3, #0]
 80043e6:	f042 0201 	orr.w	r2, r2, #1
 80043ea:	601a      	str	r2, [r3, #0]

  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
  return (UART_CheckIdleState(huart));
 80043ec:	6878      	ldr	r0, [r7, #4]
 80043ee:	f000 ff25 	bl	800523c <UART_CheckIdleState>
 80043f2:	4603      	mov	r3, r0
}
 80043f4:	4618      	mov	r0, r3
 80043f6:	3708      	adds	r7, #8
 80043f8:	46bd      	mov	sp, r7
 80043fa:	bd80      	pop	{r7, pc}

080043fc <HAL_UART_Transmit_IT>:
  * @param pData Pointer to data buffer (u8 or u16 data elements).
  * @param Size  Amount of data elements (u8 or u16) to be sent.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
 80043fc:	b480      	push	{r7}
 80043fe:	b08b      	sub	sp, #44	@ 0x2c
 8004400:	af00      	add	r7, sp, #0
 8004402:	60f8      	str	r0, [r7, #12]
 8004404:	60b9      	str	r1, [r7, #8]
 8004406:	4613      	mov	r3, r2
 8004408:	80fb      	strh	r3, [r7, #6]
  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 800440a:	68fb      	ldr	r3, [r7, #12]
 800440c:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 800440e:	2b20      	cmp	r3, #32
 8004410:	d147      	bne.n	80044a2 <HAL_UART_Transmit_IT+0xa6>
  {
    if ((pData == NULL) || (Size == 0U))
 8004412:	68bb      	ldr	r3, [r7, #8]
 8004414:	2b00      	cmp	r3, #0
 8004416:	d002      	beq.n	800441e <HAL_UART_Transmit_IT+0x22>
 8004418:	88fb      	ldrh	r3, [r7, #6]
 800441a:	2b00      	cmp	r3, #0
 800441c:	d101      	bne.n	8004422 <HAL_UART_Transmit_IT+0x26>
    {
      return HAL_ERROR;
 800441e:	2301      	movs	r3, #1
 8004420:	e040      	b.n	80044a4 <HAL_UART_Transmit_IT+0xa8>
    }

    huart->pTxBuffPtr  = pData;
 8004422:	68fb      	ldr	r3, [r7, #12]
 8004424:	68ba      	ldr	r2, [r7, #8]
 8004426:	64da      	str	r2, [r3, #76]	@ 0x4c
    huart->TxXferSize  = Size;
 8004428:	68fb      	ldr	r3, [r7, #12]
 800442a:	88fa      	ldrh	r2, [r7, #6]
 800442c:	f8a3 2050 	strh.w	r2, [r3, #80]	@ 0x50
    huart->TxXferCount = Size;
 8004430:	68fb      	ldr	r3, [r7, #12]
 8004432:	88fa      	ldrh	r2, [r7, #6]
 8004434:	f8a3 2052 	strh.w	r2, [r3, #82]	@ 0x52
    huart->TxISR       = NULL;
 8004438:	68fb      	ldr	r3, [r7, #12]
 800443a:	2200      	movs	r2, #0
 800443c:	66da      	str	r2, [r3, #108]	@ 0x6c

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 800443e:	68fb      	ldr	r3, [r7, #12]
 8004440:	2200      	movs	r2, #0
 8004442:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8004446:	68fb      	ldr	r3, [r7, #12]
 8004448:	2221      	movs	r2, #33	@ 0x21
 800444a:	67da      	str	r2, [r3, #124]	@ 0x7c
      /* Enable the Transmit Data Register Empty interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
    }
#else
    /* Set the Tx ISR function pointer according to the data word length */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 800444c:	68fb      	ldr	r3, [r7, #12]
 800444e:	689b      	ldr	r3, [r3, #8]
 8004450:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8004454:	d107      	bne.n	8004466 <HAL_UART_Transmit_IT+0x6a>
 8004456:	68fb      	ldr	r3, [r7, #12]
 8004458:	691b      	ldr	r3, [r3, #16]
 800445a:	2b00      	cmp	r3, #0
 800445c:	d103      	bne.n	8004466 <HAL_UART_Transmit_IT+0x6a>
    {
      huart->TxISR = UART_TxISR_16BIT;
 800445e:	68fb      	ldr	r3, [r7, #12]
 8004460:	4a13      	ldr	r2, [pc, #76]	@ (80044b0 <HAL_UART_Transmit_IT+0xb4>)
 8004462:	66da      	str	r2, [r3, #108]	@ 0x6c
 8004464:	e002      	b.n	800446c <HAL_UART_Transmit_IT+0x70>
    }
    else
    {
      huart->TxISR = UART_TxISR_8BIT;
 8004466:	68fb      	ldr	r3, [r7, #12]
 8004468:	4a12      	ldr	r2, [pc, #72]	@ (80044b4 <HAL_UART_Transmit_IT+0xb8>)
 800446a:	66da      	str	r2, [r3, #108]	@ 0x6c
    }

    /* Enable the Transmit Data Register Empty interrupt */
    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
 800446c:	68fb      	ldr	r3, [r7, #12]
 800446e:	681b      	ldr	r3, [r3, #0]
 8004470:	617b      	str	r3, [r7, #20]
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004472:	697b      	ldr	r3, [r7, #20]
 8004474:	e853 3f00 	ldrex	r3, [r3]
 8004478:	613b      	str	r3, [r7, #16]
   return(result);
 800447a:	693b      	ldr	r3, [r7, #16]
 800447c:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8004480:	627b      	str	r3, [r7, #36]	@ 0x24
 8004482:	68fb      	ldr	r3, [r7, #12]
 8004484:	681b      	ldr	r3, [r3, #0]
 8004486:	461a      	mov	r2, r3
 8004488:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800448a:	623b      	str	r3, [r7, #32]
 800448c:	61fa      	str	r2, [r7, #28]
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800448e:	69f9      	ldr	r1, [r7, #28]
 8004490:	6a3a      	ldr	r2, [r7, #32]
 8004492:	e841 2300 	strex	r3, r2, [r1]
 8004496:	61bb      	str	r3, [r7, #24]
   return(result);
 8004498:	69bb      	ldr	r3, [r7, #24]
 800449a:	2b00      	cmp	r3, #0
 800449c:	d1e6      	bne.n	800446c <HAL_UART_Transmit_IT+0x70>
#endif /* USART_CR1_FIFOEN */

    return HAL_OK;
 800449e:	2300      	movs	r3, #0
 80044a0:	e000      	b.n	80044a4 <HAL_UART_Transmit_IT+0xa8>
  }
  else
  {
    return HAL_BUSY;
 80044a2:	2302      	movs	r3, #2
  }
}
 80044a4:	4618      	mov	r0, r3
 80044a6:	372c      	adds	r7, #44	@ 0x2c
 80044a8:	46bd      	mov	sp, r7
 80044aa:	f85d 7b04 	ldr.w	r7, [sp], #4
 80044ae:	4770      	bx	lr
 80044b0:	0800579f 	.word	0x0800579f
 80044b4:	080056e9 	.word	0x080056e9

080044b8 <HAL_UART_Receive_IT>:
  * @param pData Pointer to data buffer (u8 or u16 data elements).
  * @param Size  Amount of data elements (u8 or u16) to be received.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 80044b8:	b580      	push	{r7, lr}
 80044ba:	b08a      	sub	sp, #40	@ 0x28
 80044bc:	af00      	add	r7, sp, #0
 80044be:	60f8      	str	r0, [r7, #12]
 80044c0:	60b9      	str	r1, [r7, #8]
 80044c2:	4613      	mov	r3, r2
 80044c4:	80fb      	strh	r3, [r7, #6]
  /* Check that a Rx process is not already ongoing */
  if (huart->RxState == HAL_UART_STATE_READY)
 80044c6:	68fb      	ldr	r3, [r7, #12]
 80044c8:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 80044cc:	2b20      	cmp	r3, #32
 80044ce:	d137      	bne.n	8004540 <HAL_UART_Receive_IT+0x88>
  {
    if ((pData == NULL) || (Size == 0U))
 80044d0:	68bb      	ldr	r3, [r7, #8]
 80044d2:	2b00      	cmp	r3, #0
 80044d4:	d002      	beq.n	80044dc <HAL_UART_Receive_IT+0x24>
 80044d6:	88fb      	ldrh	r3, [r7, #6]
 80044d8:	2b00      	cmp	r3, #0
 80044da:	d101      	bne.n	80044e0 <HAL_UART_Receive_IT+0x28>
    {
      return HAL_ERROR;
 80044dc:	2301      	movs	r3, #1
 80044de:	e030      	b.n	8004542 <HAL_UART_Receive_IT+0x8a>
    }

    /* Set Reception type to Standard reception */
    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80044e0:	68fb      	ldr	r3, [r7, #12]
 80044e2:	2200      	movs	r2, #0
 80044e4:	661a      	str	r2, [r3, #96]	@ 0x60

    if (!(IS_LPUART_INSTANCE(huart->Instance)))
 80044e6:	68fb      	ldr	r3, [r7, #12]
 80044e8:	681b      	ldr	r3, [r3, #0]
 80044ea:	4a18      	ldr	r2, [pc, #96]	@ (800454c <HAL_UART_Receive_IT+0x94>)
 80044ec:	4293      	cmp	r3, r2
 80044ee:	d01f      	beq.n	8004530 <HAL_UART_Receive_IT+0x78>
    {
      /* Check that USART RTOEN bit is set */
      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 80044f0:	68fb      	ldr	r3, [r7, #12]
 80044f2:	681b      	ldr	r3, [r3, #0]
 80044f4:	685b      	ldr	r3, [r3, #4]
 80044f6:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 80044fa:	2b00      	cmp	r3, #0
 80044fc:	d018      	beq.n	8004530 <HAL_UART_Receive_IT+0x78>
      {
        /* Enable the UART Receiver Timeout Interrupt */
        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 80044fe:	68fb      	ldr	r3, [r7, #12]
 8004500:	681b      	ldr	r3, [r3, #0]
 8004502:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004504:	697b      	ldr	r3, [r7, #20]
 8004506:	e853 3f00 	ldrex	r3, [r3]
 800450a:	613b      	str	r3, [r7, #16]
   return(result);
 800450c:	693b      	ldr	r3, [r7, #16]
 800450e:	f043 6380 	orr.w	r3, r3, #67108864	@ 0x4000000
 8004512:	627b      	str	r3, [r7, #36]	@ 0x24
 8004514:	68fb      	ldr	r3, [r7, #12]
 8004516:	681b      	ldr	r3, [r3, #0]
 8004518:	461a      	mov	r2, r3
 800451a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800451c:	623b      	str	r3, [r7, #32]
 800451e:	61fa      	str	r2, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004520:	69f9      	ldr	r1, [r7, #28]
 8004522:	6a3a      	ldr	r2, [r7, #32]
 8004524:	e841 2300 	strex	r3, r2, [r1]
 8004528:	61bb      	str	r3, [r7, #24]
   return(result);
 800452a:	69bb      	ldr	r3, [r7, #24]
 800452c:	2b00      	cmp	r3, #0
 800452e:	d1e6      	bne.n	80044fe <HAL_UART_Receive_IT+0x46>
      }
    }

    return (UART_Start_Receive_IT(huart, pData, Size));
 8004530:	88fb      	ldrh	r3, [r7, #6]
 8004532:	461a      	mov	r2, r3
 8004534:	68b9      	ldr	r1, [r7, #8]
 8004536:	68f8      	ldr	r0, [r7, #12]
 8004538:	f000 ff96 	bl	8005468 <UART_Start_Receive_IT>
 800453c:	4603      	mov	r3, r0
 800453e:	e000      	b.n	8004542 <HAL_UART_Receive_IT+0x8a>
  }
  else
  {
    return HAL_BUSY;
 8004540:	2302      	movs	r3, #2
  }
}
 8004542:	4618      	mov	r0, r3
 8004544:	3728      	adds	r7, #40	@ 0x28
 8004546:	46bd      	mov	sp, r7
 8004548:	bd80      	pop	{r7, pc}
 800454a:	bf00      	nop
 800454c:	40008000 	.word	0x40008000

08004550 <HAL_UART_IRQHandler>:
  * @brief Handle UART interrupt request.
  * @param huart UART handle.
  * @retval None
  */
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
 8004550:	b580      	push	{r7, lr}
 8004552:	b0ba      	sub	sp, #232	@ 0xe8
 8004554:	af00      	add	r7, sp, #0
 8004556:	6078      	str	r0, [r7, #4]
  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
 8004558:	687b      	ldr	r3, [r7, #4]
 800455a:	681b      	ldr	r3, [r3, #0]
 800455c:	69db      	ldr	r3, [r3, #28]
 800455e:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 8004562:	687b      	ldr	r3, [r7, #4]
 8004564:	681b      	ldr	r3, [r3, #0]
 8004566:	681b      	ldr	r3, [r3, #0]
 8004568:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 800456c:	687b      	ldr	r3, [r7, #4]
 800456e:	681b      	ldr	r3, [r3, #0]
 8004570:	689b      	ldr	r3, [r3, #8]
 8004572:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc

  uint32_t errorflags;
  uint32_t errorcode;

  /* If no error occurs */
  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
 8004576:	f8d7 20e4 	ldr.w	r2, [r7, #228]	@ 0xe4
 800457a:	f640 030f 	movw	r3, #2063	@ 0x80f
 800457e:	4013      	ands	r3, r2
 8004580:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
  if (errorflags == 0U)
 8004584:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
 8004588:	2b00      	cmp	r3, #0
 800458a:	d115      	bne.n	80045b8 <HAL_UART_IRQHandler+0x68>
#if defined(USART_CR1_FIFOEN)
    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
#else
    if (((isrflags & USART_ISR_RXNE) != 0U)
 800458c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8004590:	f003 0320 	and.w	r3, r3, #32
 8004594:	2b00      	cmp	r3, #0
 8004596:	d00f      	beq.n	80045b8 <HAL_UART_IRQHandler+0x68>
        && ((cr1its & USART_CR1_RXNEIE) != 0U))
 8004598:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800459c:	f003 0320 	and.w	r3, r3, #32
 80045a0:	2b00      	cmp	r3, #0
 80045a2:	d009      	beq.n	80045b8 <HAL_UART_IRQHandler+0x68>
#endif /* USART_CR1_FIFOEN */
    {
      if (huart->RxISR != NULL)
 80045a4:	687b      	ldr	r3, [r7, #4]
 80045a6:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 80045a8:	2b00      	cmp	r3, #0
 80045aa:	f000 82ca 	beq.w	8004b42 <HAL_UART_IRQHandler+0x5f2>
      {
        huart->RxISR(huart);
 80045ae:	687b      	ldr	r3, [r7, #4]
 80045b0:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 80045b2:	6878      	ldr	r0, [r7, #4]
 80045b4:	4798      	blx	r3
      }
      return;
 80045b6:	e2c4      	b.n	8004b42 <HAL_UART_IRQHandler+0x5f2>
#if defined(USART_CR1_FIFOEN)
  if ((errorflags != 0U)
      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
#else
  if ((errorflags != 0U)
 80045b8:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
 80045bc:	2b00      	cmp	r3, #0
 80045be:	f000 8117 	beq.w	80047f0 <HAL_UART_IRQHandler+0x2a0>
      && (((cr3its & USART_CR3_EIE) != 0U)
 80045c2:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 80045c6:	f003 0301 	and.w	r3, r3, #1
 80045ca:	2b00      	cmp	r3, #0
 80045cc:	d106      	bne.n	80045dc <HAL_UART_IRQHandler+0x8c>
          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
 80045ce:	f8d7 20e0 	ldr.w	r2, [r7, #224]	@ 0xe0
 80045d2:	4b85      	ldr	r3, [pc, #532]	@ (80047e8 <HAL_UART_IRQHandler+0x298>)
 80045d4:	4013      	ands	r3, r2
 80045d6:	2b00      	cmp	r3, #0
 80045d8:	f000 810a 	beq.w	80047f0 <HAL_UART_IRQHandler+0x2a0>
#endif /* USART_CR1_FIFOEN */
  {
    /* UART parity error interrupt occurred -------------------------------------*/
    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
 80045dc:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 80045e0:	f003 0301 	and.w	r3, r3, #1
 80045e4:	2b00      	cmp	r3, #0
 80045e6:	d011      	beq.n	800460c <HAL_UART_IRQHandler+0xbc>
 80045e8:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 80045ec:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 80045f0:	2b00      	cmp	r3, #0
 80045f2:	d00b      	beq.n	800460c <HAL_UART_IRQHandler+0xbc>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
 80045f4:	687b      	ldr	r3, [r7, #4]
 80045f6:	681b      	ldr	r3, [r3, #0]
 80045f8:	2201      	movs	r2, #1
 80045fa:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_PE;
 80045fc:	687b      	ldr	r3, [r7, #4]
 80045fe:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 8004602:	f043 0201 	orr.w	r2, r3, #1
 8004606:	687b      	ldr	r3, [r7, #4]
 8004608:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
    }

    /* UART frame error interrupt occurred --------------------------------------*/
    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 800460c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8004610:	f003 0302 	and.w	r3, r3, #2
 8004614:	2b00      	cmp	r3, #0
 8004616:	d011      	beq.n	800463c <HAL_UART_IRQHandler+0xec>
 8004618:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800461c:	f003 0301 	and.w	r3, r3, #1
 8004620:	2b00      	cmp	r3, #0
 8004622:	d00b      	beq.n	800463c <HAL_UART_IRQHandler+0xec>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
 8004624:	687b      	ldr	r3, [r7, #4]
 8004626:	681b      	ldr	r3, [r3, #0]
 8004628:	2202      	movs	r2, #2
 800462a:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_FE;
 800462c:	687b      	ldr	r3, [r7, #4]
 800462e:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 8004632:	f043 0204 	orr.w	r2, r3, #4
 8004636:	687b      	ldr	r3, [r7, #4]
 8004638:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
    }

    /* UART noise error interrupt occurred --------------------------------------*/
    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 800463c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8004640:	f003 0304 	and.w	r3, r3, #4
 8004644:	2b00      	cmp	r3, #0
 8004646:	d011      	beq.n	800466c <HAL_UART_IRQHandler+0x11c>
 8004648:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800464c:	f003 0301 	and.w	r3, r3, #1
 8004650:	2b00      	cmp	r3, #0
 8004652:	d00b      	beq.n	800466c <HAL_UART_IRQHandler+0x11c>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
 8004654:	687b      	ldr	r3, [r7, #4]
 8004656:	681b      	ldr	r3, [r3, #0]
 8004658:	2204      	movs	r2, #4
 800465a:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_NE;
 800465c:	687b      	ldr	r3, [r7, #4]
 800465e:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 8004662:	f043 0202 	orr.w	r2, r3, #2
 8004666:	687b      	ldr	r3, [r7, #4]
 8004668:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
#if defined(USART_CR1_FIFOEN)
    if (((isrflags & USART_ISR_ORE) != 0U)
        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
#else
    if (((isrflags & USART_ISR_ORE) != 0U)
 800466c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8004670:	f003 0308 	and.w	r3, r3, #8
 8004674:	2b00      	cmp	r3, #0
 8004676:	d017      	beq.n	80046a8 <HAL_UART_IRQHandler+0x158>
        && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
 8004678:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800467c:	f003 0320 	and.w	r3, r3, #32
 8004680:	2b00      	cmp	r3, #0
 8004682:	d105      	bne.n	8004690 <HAL_UART_IRQHandler+0x140>
            ((cr3its & USART_CR3_EIE) != 0U)))
 8004684:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 8004688:	f003 0301 	and.w	r3, r3, #1
        && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
 800468c:	2b00      	cmp	r3, #0
 800468e:	d00b      	beq.n	80046a8 <HAL_UART_IRQHandler+0x158>
#endif /* USART_CR1_FIFOEN */
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 8004690:	687b      	ldr	r3, [r7, #4]
 8004692:	681b      	ldr	r3, [r3, #0]
 8004694:	2208      	movs	r2, #8
 8004696:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 8004698:	687b      	ldr	r3, [r7, #4]
 800469a:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800469e:	f043 0208 	orr.w	r2, r3, #8
 80046a2:	687b      	ldr	r3, [r7, #4]
 80046a4:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
    }

    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
 80046a8:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 80046ac:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 80046b0:	2b00      	cmp	r3, #0
 80046b2:	d012      	beq.n	80046da <HAL_UART_IRQHandler+0x18a>
 80046b4:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 80046b8:	f003 6380 	and.w	r3, r3, #67108864	@ 0x4000000
 80046bc:	2b00      	cmp	r3, #0
 80046be:	d00c      	beq.n	80046da <HAL_UART_IRQHandler+0x18a>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 80046c0:	687b      	ldr	r3, [r7, #4]
 80046c2:	681b      	ldr	r3, [r3, #0]
 80046c4:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 80046c8:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_RTO;
 80046ca:	687b      	ldr	r3, [r7, #4]
 80046cc:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 80046d0:	f043 0220 	orr.w	r2, r3, #32
 80046d4:	687b      	ldr	r3, [r7, #4]
 80046d6:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
    }

    /* Call UART Error Call back function if need be ----------------------------*/
    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 80046da:	687b      	ldr	r3, [r7, #4]
 80046dc:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 80046e0:	2b00      	cmp	r3, #0
 80046e2:	f000 8230 	beq.w	8004b46 <HAL_UART_IRQHandler+0x5f6>
#if defined(USART_CR1_FIFOEN)
      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
#else
      if (((isrflags & USART_ISR_RXNE) != 0U)
 80046e6:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 80046ea:	f003 0320 	and.w	r3, r3, #32
 80046ee:	2b00      	cmp	r3, #0
 80046f0:	d00d      	beq.n	800470e <HAL_UART_IRQHandler+0x1be>
          && ((cr1its & USART_CR1_RXNEIE) != 0U))
 80046f2:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 80046f6:	f003 0320 	and.w	r3, r3, #32
 80046fa:	2b00      	cmp	r3, #0
 80046fc:	d007      	beq.n	800470e <HAL_UART_IRQHandler+0x1be>
#endif /* USART_CR1_FIFOEN */
      {
        if (huart->RxISR != NULL)
 80046fe:	687b      	ldr	r3, [r7, #4]
 8004700:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 8004702:	2b00      	cmp	r3, #0
 8004704:	d003      	beq.n	800470e <HAL_UART_IRQHandler+0x1be>
        {
          huart->RxISR(huart);
 8004706:	687b      	ldr	r3, [r7, #4]
 8004708:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 800470a:	6878      	ldr	r0, [r7, #4]
 800470c:	4798      	blx	r3
      /* If Error is to be considered as blocking :
          - Receiver Timeout error in Reception
          - Overrun error in Reception
          - any error occurs in DMA mode reception
      */
      errorcode = huart->ErrorCode;
 800470e:	687b      	ldr	r3, [r7, #4]
 8004710:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 8004714:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
 8004718:	687b      	ldr	r3, [r7, #4]
 800471a:	681b      	ldr	r3, [r3, #0]
 800471c:	689b      	ldr	r3, [r3, #8]
 800471e:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8004722:	2b40      	cmp	r3, #64	@ 0x40
 8004724:	d005      	beq.n	8004732 <HAL_UART_IRQHandler+0x1e2>
          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
 8004726:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
 800472a:	f003 0328 	and.w	r3, r3, #40	@ 0x28
      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
 800472e:	2b00      	cmp	r3, #0
 8004730:	d04f      	beq.n	80047d2 <HAL_UART_IRQHandler+0x282>
      {
        /* Blocking error : transfer is aborted
           Set the UART state ready to be able to start again the process,
           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
        UART_EndRxTransfer(huart);
 8004732:	6878      	ldr	r0, [r7, #4]
 8004734:	f000 ff5e 	bl	80055f4 <UART_EndRxTransfer>

        /* Abort the UART DMA Rx channel if enabled */
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8004738:	687b      	ldr	r3, [r7, #4]
 800473a:	681b      	ldr	r3, [r3, #0]
 800473c:	689b      	ldr	r3, [r3, #8]
 800473e:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8004742:	2b40      	cmp	r3, #64	@ 0x40
 8004744:	d141      	bne.n	80047ca <HAL_UART_IRQHandler+0x27a>
        {
          /* Disable the UART DMA Rx request if enabled */
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8004746:	687b      	ldr	r3, [r7, #4]
 8004748:	681b      	ldr	r3, [r3, #0]
 800474a:	3308      	adds	r3, #8
 800474c:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004750:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
 8004754:	e853 3f00 	ldrex	r3, [r3]
 8004758:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
   return(result);
 800475c:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
 8004760:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 8004764:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
 8004768:	687b      	ldr	r3, [r7, #4]
 800476a:	681b      	ldr	r3, [r3, #0]
 800476c:	3308      	adds	r3, #8
 800476e:	f8d7 20d0 	ldr.w	r2, [r7, #208]	@ 0xd0
 8004772:	f8c7 20a8 	str.w	r2, [r7, #168]	@ 0xa8
 8004776:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800477a:	f8d7 10a4 	ldr.w	r1, [r7, #164]	@ 0xa4
 800477e:	f8d7 20a8 	ldr.w	r2, [r7, #168]	@ 0xa8
 8004782:	e841 2300 	strex	r3, r2, [r1]
 8004786:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
   return(result);
 800478a:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 800478e:	2b00      	cmp	r3, #0
 8004790:	d1d9      	bne.n	8004746 <HAL_UART_IRQHandler+0x1f6>

          /* Abort the UART DMA Rx channel */
          if (huart->hdmarx != NULL)
 8004792:	687b      	ldr	r3, [r7, #4]
 8004794:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8004796:	2b00      	cmp	r3, #0
 8004798:	d013      	beq.n	80047c2 <HAL_UART_IRQHandler+0x272>
          {
            /* Set the UART DMA Abort callback :
               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 800479a:	687b      	ldr	r3, [r7, #4]
 800479c:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800479e:	4a13      	ldr	r2, [pc, #76]	@ (80047ec <HAL_UART_IRQHandler+0x29c>)
 80047a0:	639a      	str	r2, [r3, #56]	@ 0x38

            /* Abort DMA RX */
            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 80047a2:	687b      	ldr	r3, [r7, #4]
 80047a4:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80047a6:	4618      	mov	r0, r3
 80047a8:	f7fd f9a8 	bl	8001afc <HAL_DMA_Abort_IT>
 80047ac:	4603      	mov	r3, r0
 80047ae:	2b00      	cmp	r3, #0
 80047b0:	d017      	beq.n	80047e2 <HAL_UART_IRQHandler+0x292>
            {
              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 80047b2:	687b      	ldr	r3, [r7, #4]
 80047b4:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80047b6:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 80047b8:	687a      	ldr	r2, [r7, #4]
 80047ba:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 80047bc:	4610      	mov	r0, r2
 80047be:	4798      	blx	r3
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 80047c0:	e00f      	b.n	80047e2 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
            /*Call registered error callback*/
            huart->ErrorCallback(huart);
#else
            /*Call legacy weak error callback*/
            HAL_UART_ErrorCallback(huart);
 80047c2:	6878      	ldr	r0, [r7, #4]
 80047c4:	f000 f9ca 	bl	8004b5c <HAL_UART_ErrorCallback>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 80047c8:	e00b      	b.n	80047e2 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered error callback*/
          huart->ErrorCallback(huart);
#else
          /*Call legacy weak error callback*/
          HAL_UART_ErrorCallback(huart);
 80047ca:	6878      	ldr	r0, [r7, #4]
 80047cc:	f000 f9c6 	bl	8004b5c <HAL_UART_ErrorCallback>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 80047d0:	e007      	b.n	80047e2 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered error callback*/
        huart->ErrorCallback(huart);
#else
        /*Call legacy weak error callback*/
        HAL_UART_ErrorCallback(huart);
 80047d2:	6878      	ldr	r0, [r7, #4]
 80047d4:	f000 f9c2 	bl	8004b5c <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 80047d8:	687b      	ldr	r3, [r7, #4]
 80047da:	2200      	movs	r2, #0
 80047dc:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
      }
    }
    return;
 80047e0:	e1b1      	b.n	8004b46 <HAL_UART_IRQHandler+0x5f6>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 80047e2:	bf00      	nop
    return;
 80047e4:	e1af      	b.n	8004b46 <HAL_UART_IRQHandler+0x5f6>
 80047e6:	bf00      	nop
 80047e8:	04000120 	.word	0x04000120
 80047ec:	080056bd 	.word	0x080056bd

  } /* End if some error occurs */

  /* Check current reception Mode :
     If Reception till IDLE event has been selected : */
  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 80047f0:	687b      	ldr	r3, [r7, #4]
 80047f2:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80047f4:	2b01      	cmp	r3, #1
 80047f6:	f040 816a 	bne.w	8004ace <HAL_UART_IRQHandler+0x57e>
      && ((isrflags & USART_ISR_IDLE) != 0U)
 80047fa:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 80047fe:	f003 0310 	and.w	r3, r3, #16
 8004802:	2b00      	cmp	r3, #0
 8004804:	f000 8163 	beq.w	8004ace <HAL_UART_IRQHandler+0x57e>
      && ((cr1its & USART_ISR_IDLE) != 0U))
 8004808:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800480c:	f003 0310 	and.w	r3, r3, #16
 8004810:	2b00      	cmp	r3, #0
 8004812:	f000 815c 	beq.w	8004ace <HAL_UART_IRQHandler+0x57e>
  {
    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 8004816:	687b      	ldr	r3, [r7, #4]
 8004818:	681b      	ldr	r3, [r3, #0]
 800481a:	2210      	movs	r2, #16
 800481c:	621a      	str	r2, [r3, #32]

    /* Check if DMA mode is enabled in UART */
    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800481e:	687b      	ldr	r3, [r7, #4]
 8004820:	681b      	ldr	r3, [r3, #0]
 8004822:	689b      	ldr	r3, [r3, #8]
 8004824:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8004828:	2b40      	cmp	r3, #64	@ 0x40
 800482a:	f040 80d4 	bne.w	80049d6 <HAL_UART_IRQHandler+0x486>
    {
      /* DMA mode enabled */
      /* Check received length : If all expected data are received, do nothing,
         (DMA cplt callback will be called).
         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
 800482e:	687b      	ldr	r3, [r7, #4]
 8004830:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8004832:	681b      	ldr	r3, [r3, #0]
 8004834:	685b      	ldr	r3, [r3, #4]
 8004836:	f8a7 30be 	strh.w	r3, [r7, #190]	@ 0xbe
      if ((nb_remaining_rx_data > 0U)
 800483a:	f8b7 30be 	ldrh.w	r3, [r7, #190]	@ 0xbe
 800483e:	2b00      	cmp	r3, #0
 8004840:	f000 80ad 	beq.w	800499e <HAL_UART_IRQHandler+0x44e>
          && (nb_remaining_rx_data < huart->RxXferSize))
 8004844:	687b      	ldr	r3, [r7, #4]
 8004846:	f8b3 3058 	ldrh.w	r3, [r3, #88]	@ 0x58
 800484a:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
 800484e:	429a      	cmp	r2, r3
 8004850:	f080 80a5 	bcs.w	800499e <HAL_UART_IRQHandler+0x44e>
      {
        /* Reception is not complete */
        huart->RxXferCount = nb_remaining_rx_data;
 8004854:	687b      	ldr	r3, [r7, #4]
 8004856:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
 800485a:	f8a3 205a 	strh.w	r2, [r3, #90]	@ 0x5a

        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
        if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
 800485e:	687b      	ldr	r3, [r7, #4]
 8004860:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8004862:	681b      	ldr	r3, [r3, #0]
 8004864:	681b      	ldr	r3, [r3, #0]
 8004866:	f003 0320 	and.w	r3, r3, #32
 800486a:	2b00      	cmp	r3, #0
 800486c:	f040 8086 	bne.w	800497c <HAL_UART_IRQHandler+0x42c>
        {
          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 8004870:	687b      	ldr	r3, [r7, #4]
 8004872:	681b      	ldr	r3, [r3, #0]
 8004874:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004878:	f8d7 3088 	ldr.w	r3, [r7, #136]	@ 0x88
 800487c:	e853 3f00 	ldrex	r3, [r3]
 8004880:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
   return(result);
 8004884:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
 8004888:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 800488c:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
 8004890:	687b      	ldr	r3, [r7, #4]
 8004892:	681b      	ldr	r3, [r3, #0]
 8004894:	461a      	mov	r2, r3
 8004896:	f8d7 30b8 	ldr.w	r3, [r7, #184]	@ 0xb8
 800489a:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 800489e:	f8c7 2090 	str.w	r2, [r7, #144]	@ 0x90
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80048a2:	f8d7 1090 	ldr.w	r1, [r7, #144]	@ 0x90
 80048a6:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
 80048aa:	e841 2300 	strex	r3, r2, [r1]
 80048ae:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
   return(result);
 80048b2:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
 80048b6:	2b00      	cmp	r3, #0
 80048b8:	d1da      	bne.n	8004870 <HAL_UART_IRQHandler+0x320>
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80048ba:	687b      	ldr	r3, [r7, #4]
 80048bc:	681b      	ldr	r3, [r3, #0]
 80048be:	3308      	adds	r3, #8
 80048c0:	677b      	str	r3, [r7, #116]	@ 0x74
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80048c2:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 80048c4:	e853 3f00 	ldrex	r3, [r3]
 80048c8:	673b      	str	r3, [r7, #112]	@ 0x70
   return(result);
 80048ca:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 80048cc:	f023 0301 	bic.w	r3, r3, #1
 80048d0:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
 80048d4:	687b      	ldr	r3, [r7, #4]
 80048d6:	681b      	ldr	r3, [r3, #0]
 80048d8:	3308      	adds	r3, #8
 80048da:	f8d7 20b4 	ldr.w	r2, [r7, #180]	@ 0xb4
 80048de:	f8c7 2080 	str.w	r2, [r7, #128]	@ 0x80
 80048e2:	67fb      	str	r3, [r7, #124]	@ 0x7c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80048e4:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
 80048e6:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
 80048ea:	e841 2300 	strex	r3, r2, [r1]
 80048ee:	67bb      	str	r3, [r7, #120]	@ 0x78
   return(result);
 80048f0:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 80048f2:	2b00      	cmp	r3, #0
 80048f4:	d1e1      	bne.n	80048ba <HAL_UART_IRQHandler+0x36a>

          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
             in the UART CR3 register */
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80048f6:	687b      	ldr	r3, [r7, #4]
 80048f8:	681b      	ldr	r3, [r3, #0]
 80048fa:	3308      	adds	r3, #8
 80048fc:	663b      	str	r3, [r7, #96]	@ 0x60
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80048fe:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8004900:	e853 3f00 	ldrex	r3, [r3]
 8004904:	65fb      	str	r3, [r7, #92]	@ 0x5c
   return(result);
 8004906:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8004908:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 800490c:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
 8004910:	687b      	ldr	r3, [r7, #4]
 8004912:	681b      	ldr	r3, [r3, #0]
 8004914:	3308      	adds	r3, #8
 8004916:	f8d7 20b0 	ldr.w	r2, [r7, #176]	@ 0xb0
 800491a:	66fa      	str	r2, [r7, #108]	@ 0x6c
 800491c:	66bb      	str	r3, [r7, #104]	@ 0x68
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800491e:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
 8004920:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 8004922:	e841 2300 	strex	r3, r2, [r1]
 8004926:	667b      	str	r3, [r7, #100]	@ 0x64
   return(result);
 8004928:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 800492a:	2b00      	cmp	r3, #0
 800492c:	d1e3      	bne.n	80048f6 <HAL_UART_IRQHandler+0x3a6>

          /* At end of Rx process, restore huart->RxState to Ready */
          huart->RxState = HAL_UART_STATE_READY;
 800492e:	687b      	ldr	r3, [r7, #4]
 8004930:	2220      	movs	r2, #32
 8004932:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8004936:	687b      	ldr	r3, [r7, #4]
 8004938:	2200      	movs	r2, #0
 800493a:	661a      	str	r2, [r3, #96]	@ 0x60

          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800493c:	687b      	ldr	r3, [r7, #4]
 800493e:	681b      	ldr	r3, [r3, #0]
 8004940:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004942:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8004944:	e853 3f00 	ldrex	r3, [r3]
 8004948:	64bb      	str	r3, [r7, #72]	@ 0x48
   return(result);
 800494a:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 800494c:	f023 0310 	bic.w	r3, r3, #16
 8004950:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
 8004954:	687b      	ldr	r3, [r7, #4]
 8004956:	681b      	ldr	r3, [r3, #0]
 8004958:	461a      	mov	r2, r3
 800495a:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 800495e:	65bb      	str	r3, [r7, #88]	@ 0x58
 8004960:	657a      	str	r2, [r7, #84]	@ 0x54
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004962:	6d79      	ldr	r1, [r7, #84]	@ 0x54
 8004964:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 8004966:	e841 2300 	strex	r3, r2, [r1]
 800496a:	653b      	str	r3, [r7, #80]	@ 0x50
   return(result);
 800496c:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 800496e:	2b00      	cmp	r3, #0
 8004970:	d1e4      	bne.n	800493c <HAL_UART_IRQHandler+0x3ec>

          /* Last bytes received, so no need as the abort is immediate */
          (void)HAL_DMA_Abort(huart->hdmarx);
 8004972:	687b      	ldr	r3, [r7, #4]
 8004974:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8004976:	4618      	mov	r0, r3
 8004978:	f7fd f882 	bl	8001a80 <HAL_DMA_Abort>
        }

        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
           In this case, Rx Event type is Idle Event */
        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
 800497c:	687b      	ldr	r3, [r7, #4]
 800497e:	2202      	movs	r2, #2
 8004980:	665a      	str	r2, [r3, #100]	@ 0x64
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
 8004982:	687b      	ldr	r3, [r7, #4]
 8004984:	f8b3 2058 	ldrh.w	r2, [r3, #88]	@ 0x58
 8004988:	687b      	ldr	r3, [r7, #4]
 800498a:	f8b3 305a 	ldrh.w	r3, [r3, #90]	@ 0x5a
 800498e:	b29b      	uxth	r3, r3
 8004990:	1ad3      	subs	r3, r2, r3
 8004992:	b29b      	uxth	r3, r3
 8004994:	4619      	mov	r1, r3
 8004996:	6878      	ldr	r0, [r7, #4]
 8004998:	f000 f8ea 	bl	8004b70 <HAL_UARTEx_RxEventCallback>
            HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
          }
        }
      }
      return;
 800499c:	e0d5      	b.n	8004b4a <HAL_UART_IRQHandler+0x5fa>
        if (nb_remaining_rx_data == huart->RxXferSize)
 800499e:	687b      	ldr	r3, [r7, #4]
 80049a0:	f8b3 3058 	ldrh.w	r3, [r3, #88]	@ 0x58
 80049a4:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
 80049a8:	429a      	cmp	r2, r3
 80049aa:	f040 80ce 	bne.w	8004b4a <HAL_UART_IRQHandler+0x5fa>
          if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
 80049ae:	687b      	ldr	r3, [r7, #4]
 80049b0:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80049b2:	681b      	ldr	r3, [r3, #0]
 80049b4:	681b      	ldr	r3, [r3, #0]
 80049b6:	f003 0320 	and.w	r3, r3, #32
 80049ba:	2b20      	cmp	r3, #32
 80049bc:	f040 80c5 	bne.w	8004b4a <HAL_UART_IRQHandler+0x5fa>
            huart->RxEventType = HAL_UART_RXEVENT_IDLE;
 80049c0:	687b      	ldr	r3, [r7, #4]
 80049c2:	2202      	movs	r2, #2
 80049c4:	665a      	str	r2, [r3, #100]	@ 0x64
            HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 80049c6:	687b      	ldr	r3, [r7, #4]
 80049c8:	f8b3 3058 	ldrh.w	r3, [r3, #88]	@ 0x58
 80049cc:	4619      	mov	r1, r3
 80049ce:	6878      	ldr	r0, [r7, #4]
 80049d0:	f000 f8ce 	bl	8004b70 <HAL_UARTEx_RxEventCallback>
      return;
 80049d4:	e0b9      	b.n	8004b4a <HAL_UART_IRQHandler+0x5fa>
    else
    {
      /* DMA mode not enabled */
      /* Check received length : If all expected data are received, do nothing.
         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
 80049d6:	687b      	ldr	r3, [r7, #4]
 80049d8:	f8b3 2058 	ldrh.w	r2, [r3, #88]	@ 0x58
 80049dc:	687b      	ldr	r3, [r7, #4]
 80049de:	f8b3 305a 	ldrh.w	r3, [r3, #90]	@ 0x5a
 80049e2:	b29b      	uxth	r3, r3
 80049e4:	1ad3      	subs	r3, r2, r3
 80049e6:	f8a7 30ce 	strh.w	r3, [r7, #206]	@ 0xce
      if ((huart->RxXferCount > 0U)
 80049ea:	687b      	ldr	r3, [r7, #4]
 80049ec:	f8b3 305a 	ldrh.w	r3, [r3, #90]	@ 0x5a
 80049f0:	b29b      	uxth	r3, r3
 80049f2:	2b00      	cmp	r3, #0
 80049f4:	f000 80ab 	beq.w	8004b4e <HAL_UART_IRQHandler+0x5fe>
          && (nb_rx_data > 0U))
 80049f8:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
 80049fc:	2b00      	cmp	r3, #0
 80049fe:	f000 80a6 	beq.w	8004b4e <HAL_UART_IRQHandler+0x5fe>

        /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8004a02:	687b      	ldr	r3, [r7, #4]
 8004a04:	681b      	ldr	r3, [r3, #0]
 8004a06:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004a08:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8004a0a:	e853 3f00 	ldrex	r3, [r3]
 8004a0e:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 8004a10:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8004a12:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8004a16:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
 8004a1a:	687b      	ldr	r3, [r7, #4]
 8004a1c:	681b      	ldr	r3, [r3, #0]
 8004a1e:	461a      	mov	r2, r3
 8004a20:	f8d7 30c8 	ldr.w	r3, [r7, #200]	@ 0xc8
 8004a24:	647b      	str	r3, [r7, #68]	@ 0x44
 8004a26:	643a      	str	r2, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004a28:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 8004a2a:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 8004a2c:	e841 2300 	strex	r3, r2, [r1]
 8004a30:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 8004a32:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8004a34:	2b00      	cmp	r3, #0
 8004a36:	d1e4      	bne.n	8004a02 <HAL_UART_IRQHandler+0x4b2>

        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8004a38:	687b      	ldr	r3, [r7, #4]
 8004a3a:	681b      	ldr	r3, [r3, #0]
 8004a3c:	3308      	adds	r3, #8
 8004a3e:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004a40:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8004a42:	e853 3f00 	ldrex	r3, [r3]
 8004a46:	623b      	str	r3, [r7, #32]
   return(result);
 8004a48:	6a3b      	ldr	r3, [r7, #32]
 8004a4a:	f023 0301 	bic.w	r3, r3, #1
 8004a4e:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
 8004a52:	687b      	ldr	r3, [r7, #4]
 8004a54:	681b      	ldr	r3, [r3, #0]
 8004a56:	3308      	adds	r3, #8
 8004a58:	f8d7 20c4 	ldr.w	r2, [r7, #196]	@ 0xc4
 8004a5c:	633a      	str	r2, [r7, #48]	@ 0x30
 8004a5e:	62fb      	str	r3, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004a60:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 8004a62:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8004a64:	e841 2300 	strex	r3, r2, [r1]
 8004a68:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 8004a6a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8004a6c:	2b00      	cmp	r3, #0
 8004a6e:	d1e3      	bne.n	8004a38 <HAL_UART_IRQHandler+0x4e8>
#endif /* USART_CR1_FIFOEN */

        /* Rx process is completed, restore huart->RxState to Ready */
        huart->RxState = HAL_UART_STATE_READY;
 8004a70:	687b      	ldr	r3, [r7, #4]
 8004a72:	2220      	movs	r2, #32
 8004a74:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8004a78:	687b      	ldr	r3, [r7, #4]
 8004a7a:	2200      	movs	r2, #0
 8004a7c:	661a      	str	r2, [r3, #96]	@ 0x60

        /* Clear RxISR function pointer */
        huart->RxISR = NULL;
 8004a7e:	687b      	ldr	r3, [r7, #4]
 8004a80:	2200      	movs	r2, #0
 8004a82:	669a      	str	r2, [r3, #104]	@ 0x68

        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8004a84:	687b      	ldr	r3, [r7, #4]
 8004a86:	681b      	ldr	r3, [r3, #0]
 8004a88:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8004a8a:	693b      	ldr	r3, [r7, #16]
 8004a8c:	e853 3f00 	ldrex	r3, [r3]
 8004a90:	60fb      	str	r3, [r7, #12]
   return(result);
 8004a92:	68fb      	ldr	r3, [r7, #12]
 8004a94:	f023 0310 	bic.w	r3, r3, #16
 8004a98:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
 8004a9c:	687b      	ldr	r3, [r7, #4]
 8004a9e:	681b      	ldr	r3, [r3, #0]
 8004aa0:	461a      	mov	r2, r3
 8004aa2:	f8d7 30c0 	ldr.w	r3, [r7, #192]	@ 0xc0
 8004aa6:	61fb      	str	r3, [r7, #28]
 8004aa8:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8004aaa:	69b9      	ldr	r1, [r7, #24]
 8004aac:	69fa      	ldr	r2, [r7, #28]
 8004aae:	e841 2300 	strex	r3, r2, [r1]
 8004ab2:	617b      	str	r3, [r7, #20]
   return(result);
 8004ab4:	697b      	ldr	r3, [r7, #20]
 8004ab6:	2b00      	cmp	r3, #0
 8004ab8:	d1e4      	bne.n	8004a84 <HAL_UART_IRQHandler+0x534>

        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
           In this case, Rx Event type is Idle Event */
        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
 8004aba:	687b      	ldr	r3, [r7, #4]
 8004abc:	2202      	movs	r2, #2
 8004abe:	665a      	str	r2, [r3, #100]	@ 0x64
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx complete callback*/
        huart->RxEventCallback(huart, nb_rx_data);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
 8004ac0:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
 8004ac4:	4619      	mov	r1, r3
 8004ac6:	6878      	ldr	r0, [r7, #4]
 8004ac8:	f000 f852 	bl	8004b70 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
      }
      return;
 8004acc:	e03f      	b.n	8004b4e <HAL_UART_IRQHandler+0x5fe>
    }
  }

  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
 8004ace:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8004ad2:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 8004ad6:	2b00      	cmp	r3, #0
 8004ad8:	d00e      	beq.n	8004af8 <HAL_UART_IRQHandler+0x5a8>
 8004ada:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 8004ade:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 8004ae2:	2b00      	cmp	r3, #0
 8004ae4:	d008      	beq.n	8004af8 <HAL_UART_IRQHandler+0x5a8>
  {
    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
 8004ae6:	687b      	ldr	r3, [r7, #4]
 8004ae8:	681b      	ldr	r3, [r3, #0]
 8004aea:	f44f 1280 	mov.w	r2, #1048576	@ 0x100000
 8004aee:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    /* Call registered Wakeup Callback */
    huart->WakeupCallback(huart);
#else
    /* Call legacy weak Wakeup Callback */
    HAL_UARTEx_WakeupCallback(huart);
 8004af0:	6878      	ldr	r0, [r7, #4]
 8004af2:	f001 f89b 	bl	8005c2c <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    return;
 8004af6:	e02d      	b.n	8004b54 <HAL_UART_IRQHandler+0x604>
#if defined(USART_CR1_FIFOEN)
  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
#else
  if (((isrflags & USART_ISR_TXE) != 0U)
 8004af8:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8004afc:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8004b00:	2b00      	cmp	r3, #0
 8004b02:	d00e      	beq.n	8004b22 <HAL_UART_IRQHandler+0x5d2>
      && ((cr1its & USART_CR1_TXEIE) != 0U))
 8004b04:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8004b08:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8004b0c:	2b00      	cmp	r3, #0
 8004b0e:	d008      	beq.n	8004b22 <HAL_UART_IRQHandler+0x5d2>
#endif /* USART_CR1_FIFOEN */
  {
    if (huart->TxISR != NULL)
 8004b10:	687b      	ldr	r3, [r7, #4]
 8004b12:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8004b14:	2b00      	cmp	r3, #0
 8004b16:	d01c      	beq.n	8004b52 <HAL_UART_IRQHandler+0x602>
    {
      huart->TxISR(huart);
 8004b18:	687b      	ldr	r3, [r7, #4]
 8004b1a:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8004b1c:	6878      	ldr	r0, [r7, #4]
 8004b1e:	4798      	blx	r3
    }
    return;
 8004b20:	e017      	b.n	8004b52 <HAL_UART_IRQHandler+0x602>
  }

  /* UART in mode Transmitter (transmission end) -----------------------------*/
  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
 8004b22:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8004b26:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8004b2a:	2b00      	cmp	r3, #0
 8004b2c:	d012      	beq.n	8004b54 <HAL_UART_IRQHandler+0x604>
 8004b2e:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8004b32:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8004b36:	2b00      	cmp	r3, #0
 8004b38:	d00c      	beq.n	8004b54 <HAL_UART_IRQHandler+0x604>
  {
    UART_EndTransmit_IT(huart);
 8004b3a:	6878      	ldr	r0, [r7, #4]
 8004b3c:	f000 fe8f 	bl	800585e <UART_EndTransmit_IT>
    return;
 8004b40:	e008      	b.n	8004b54 <HAL_UART_IRQHandler+0x604>
      return;
 8004b42:	bf00      	nop
 8004b44:	e006      	b.n	8004b54 <HAL_UART_IRQHandler+0x604>
    return;
 8004b46:	bf00      	nop
 8004b48:	e004      	b.n	8004b54 <HAL_UART_IRQHandler+0x604>
      return;
 8004b4a:	bf00      	nop
 8004b4c:	e002      	b.n	8004b54 <HAL_UART_IRQHandler+0x604>
      return;
 8004b4e:	bf00      	nop
 8004b50:	e000      	b.n	8004b54 <HAL_UART_IRQHandler+0x604>
    return;
 8004b52:	bf00      	nop
    HAL_UARTEx_RxFifoFullCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    return;
  }
#endif /* USART_CR1_FIFOEN */
}
 8004b54:	37e8      	adds	r7, #232	@ 0xe8
 8004b56:	46bd      	mov	sp, r7
 8004b58:	bd80      	pop	{r7, pc}
 8004b5a:	bf00      	nop

08004b5c <HAL_UART_ErrorCallback>:
  * @brief  UART error callback.
  * @param  huart UART handle.
  * @retval None
  */
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
 8004b5c:	b480      	push	{r7}
 8004b5e:	b083      	sub	sp, #12
 8004b60:	af00      	add	r7, sp, #0
 8004b62:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UART_ErrorCallback can be implemented in the user file.
   */
}
 8004b64:	bf00      	nop
 8004b66:	370c      	adds	r7, #12
 8004b68:	46bd      	mov	sp, r7
 8004b6a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004b6e:	4770      	bx	lr

08004b70 <HAL_UARTEx_RxEventCallback>:
  * @param  Size  Number of data available in application reception buffer (indicates a position in
  *               reception buffer until which, data are available)
  * @retval None
  */
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
 8004b70:	b480      	push	{r7}
 8004b72:	b083      	sub	sp, #12
 8004b74:	af00      	add	r7, sp, #0
 8004b76:	6078      	str	r0, [r7, #4]
 8004b78:	460b      	mov	r3, r1
 8004b7a:	807b      	strh	r3, [r7, #2]
  UNUSED(Size);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
   */
}
 8004b7c:	bf00      	nop
 8004b7e:	370c      	adds	r7, #12
 8004b80:	46bd      	mov	sp, r7
 8004b82:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004b86:	4770      	bx	lr

08004b88 <UART_SetConfig>:
  * @brief Configure the UART peripheral.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
 8004b88:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8004b8c:	b08a      	sub	sp, #40	@ 0x28
 8004b8e:	af00      	add	r7, sp, #0
 8004b90:	60f8      	str	r0, [r7, #12]
  uint32_t tmpreg;
  uint16_t brrtemp;
  UART_ClockSourceTypeDef clocksource;
  uint32_t usartdiv;
  HAL_StatusTypeDef ret               = HAL_OK;
 8004b92:	2300      	movs	r3, #0
 8004b94:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
  *  the UART Word Length, Parity, Mode and oversampling:
  *  set the M bits according to huart->Init.WordLength value
  *  set PCE and PS bits according to huart->Init.Parity value
  *  set TE and RE bits according to huart->Init.Mode value
  *  set OVER8 bit according to huart->Init.OverSampling value */
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 8004b98:	68fb      	ldr	r3, [r7, #12]
 8004b9a:	689a      	ldr	r2, [r3, #8]
 8004b9c:	68fb      	ldr	r3, [r7, #12]
 8004b9e:	691b      	ldr	r3, [r3, #16]
 8004ba0:	431a      	orrs	r2, r3
 8004ba2:	68fb      	ldr	r3, [r7, #12]
 8004ba4:	695b      	ldr	r3, [r3, #20]
 8004ba6:	431a      	orrs	r2, r3
 8004ba8:	68fb      	ldr	r3, [r7, #12]
 8004baa:	69db      	ldr	r3, [r3, #28]
 8004bac:	4313      	orrs	r3, r2
 8004bae:	627b      	str	r3, [r7, #36]	@ 0x24
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 8004bb0:	68fb      	ldr	r3, [r7, #12]
 8004bb2:	681b      	ldr	r3, [r3, #0]
 8004bb4:	681a      	ldr	r2, [r3, #0]
 8004bb6:	4ba4      	ldr	r3, [pc, #656]	@ (8004e48 <UART_SetConfig+0x2c0>)
 8004bb8:	4013      	ands	r3, r2
 8004bba:	68fa      	ldr	r2, [r7, #12]
 8004bbc:	6812      	ldr	r2, [r2, #0]
 8004bbe:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 8004bc0:	430b      	orrs	r3, r1
 8004bc2:	6013      	str	r3, [r2, #0]

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
  * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8004bc4:	68fb      	ldr	r3, [r7, #12]
 8004bc6:	681b      	ldr	r3, [r3, #0]
 8004bc8:	685b      	ldr	r3, [r3, #4]
 8004bca:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
 8004bce:	68fb      	ldr	r3, [r7, #12]
 8004bd0:	68da      	ldr	r2, [r3, #12]
 8004bd2:	68fb      	ldr	r3, [r7, #12]
 8004bd4:	681b      	ldr	r3, [r3, #0]
 8004bd6:	430a      	orrs	r2, r1
 8004bd8:	605a      	str	r2, [r3, #4]
  /* Configure
  * - UART HardWare Flow Control: set CTSE and RTSE bits according
  *   to huart->Init.HwFlowCtl value
  * - one-bit sampling method versus three samples' majority rule according
  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
 8004bda:	68fb      	ldr	r3, [r7, #12]
 8004bdc:	699b      	ldr	r3, [r3, #24]
 8004bde:	627b      	str	r3, [r7, #36]	@ 0x24

  if (!(UART_INSTANCE_LOWPOWER(huart)))
 8004be0:	68fb      	ldr	r3, [r7, #12]
 8004be2:	681b      	ldr	r3, [r3, #0]
 8004be4:	4a99      	ldr	r2, [pc, #612]	@ (8004e4c <UART_SetConfig+0x2c4>)
 8004be6:	4293      	cmp	r3, r2
 8004be8:	d004      	beq.n	8004bf4 <UART_SetConfig+0x6c>
  {
    tmpreg |= huart->Init.OneBitSampling;
 8004bea:	68fb      	ldr	r3, [r7, #12]
 8004bec:	6a1b      	ldr	r3, [r3, #32]
 8004bee:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8004bf0:	4313      	orrs	r3, r2
 8004bf2:	627b      	str	r3, [r7, #36]	@ 0x24
  }
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 8004bf4:	68fb      	ldr	r3, [r7, #12]
 8004bf6:	681b      	ldr	r3, [r3, #0]
 8004bf8:	689b      	ldr	r3, [r3, #8]
 8004bfa:	f423 6130 	bic.w	r1, r3, #2816	@ 0xb00
 8004bfe:	68fb      	ldr	r3, [r7, #12]
 8004c00:	681b      	ldr	r3, [r3, #0]
 8004c02:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8004c04:	430a      	orrs	r2, r1
 8004c06:	609a      	str	r2, [r3, #8]
  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
#endif /* USART_PRESC_PRESCALER */

  /*-------------------------- USART BRR Configuration -----------------------*/
  UART_GETCLOCKSOURCE(huart, clocksource);
 8004c08:	68fb      	ldr	r3, [r7, #12]
 8004c0a:	681b      	ldr	r3, [r3, #0]
 8004c0c:	4a90      	ldr	r2, [pc, #576]	@ (8004e50 <UART_SetConfig+0x2c8>)
 8004c0e:	4293      	cmp	r3, r2
 8004c10:	d126      	bne.n	8004c60 <UART_SetConfig+0xd8>
 8004c12:	4b90      	ldr	r3, [pc, #576]	@ (8004e54 <UART_SetConfig+0x2cc>)
 8004c14:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8004c18:	f003 0303 	and.w	r3, r3, #3
 8004c1c:	2b03      	cmp	r3, #3
 8004c1e:	d81b      	bhi.n	8004c58 <UART_SetConfig+0xd0>
 8004c20:	a201      	add	r2, pc, #4	@ (adr r2, 8004c28 <UART_SetConfig+0xa0>)
 8004c22:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8004c26:	bf00      	nop
 8004c28:	08004c39 	.word	0x08004c39
 8004c2c:	08004c49 	.word	0x08004c49
 8004c30:	08004c41 	.word	0x08004c41
 8004c34:	08004c51 	.word	0x08004c51
 8004c38:	2301      	movs	r3, #1
 8004c3a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004c3e:	e116      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004c40:	2302      	movs	r3, #2
 8004c42:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004c46:	e112      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004c48:	2304      	movs	r3, #4
 8004c4a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004c4e:	e10e      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004c50:	2308      	movs	r3, #8
 8004c52:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004c56:	e10a      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004c58:	2310      	movs	r3, #16
 8004c5a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004c5e:	e106      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004c60:	68fb      	ldr	r3, [r7, #12]
 8004c62:	681b      	ldr	r3, [r3, #0]
 8004c64:	4a7c      	ldr	r2, [pc, #496]	@ (8004e58 <UART_SetConfig+0x2d0>)
 8004c66:	4293      	cmp	r3, r2
 8004c68:	d138      	bne.n	8004cdc <UART_SetConfig+0x154>
 8004c6a:	4b7a      	ldr	r3, [pc, #488]	@ (8004e54 <UART_SetConfig+0x2cc>)
 8004c6c:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8004c70:	f003 030c 	and.w	r3, r3, #12
 8004c74:	2b0c      	cmp	r3, #12
 8004c76:	d82d      	bhi.n	8004cd4 <UART_SetConfig+0x14c>
 8004c78:	a201      	add	r2, pc, #4	@ (adr r2, 8004c80 <UART_SetConfig+0xf8>)
 8004c7a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8004c7e:	bf00      	nop
 8004c80:	08004cb5 	.word	0x08004cb5
 8004c84:	08004cd5 	.word	0x08004cd5
 8004c88:	08004cd5 	.word	0x08004cd5
 8004c8c:	08004cd5 	.word	0x08004cd5
 8004c90:	08004cc5 	.word	0x08004cc5
 8004c94:	08004cd5 	.word	0x08004cd5
 8004c98:	08004cd5 	.word	0x08004cd5
 8004c9c:	08004cd5 	.word	0x08004cd5
 8004ca0:	08004cbd 	.word	0x08004cbd
 8004ca4:	08004cd5 	.word	0x08004cd5
 8004ca8:	08004cd5 	.word	0x08004cd5
 8004cac:	08004cd5 	.word	0x08004cd5
 8004cb0:	08004ccd 	.word	0x08004ccd
 8004cb4:	2300      	movs	r3, #0
 8004cb6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004cba:	e0d8      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004cbc:	2302      	movs	r3, #2
 8004cbe:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004cc2:	e0d4      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004cc4:	2304      	movs	r3, #4
 8004cc6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004cca:	e0d0      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004ccc:	2308      	movs	r3, #8
 8004cce:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004cd2:	e0cc      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004cd4:	2310      	movs	r3, #16
 8004cd6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004cda:	e0c8      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004cdc:	68fb      	ldr	r3, [r7, #12]
 8004cde:	681b      	ldr	r3, [r3, #0]
 8004ce0:	4a5e      	ldr	r2, [pc, #376]	@ (8004e5c <UART_SetConfig+0x2d4>)
 8004ce2:	4293      	cmp	r3, r2
 8004ce4:	d125      	bne.n	8004d32 <UART_SetConfig+0x1aa>
 8004ce6:	4b5b      	ldr	r3, [pc, #364]	@ (8004e54 <UART_SetConfig+0x2cc>)
 8004ce8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8004cec:	f003 0330 	and.w	r3, r3, #48	@ 0x30
 8004cf0:	2b30      	cmp	r3, #48	@ 0x30
 8004cf2:	d016      	beq.n	8004d22 <UART_SetConfig+0x19a>
 8004cf4:	2b30      	cmp	r3, #48	@ 0x30
 8004cf6:	d818      	bhi.n	8004d2a <UART_SetConfig+0x1a2>
 8004cf8:	2b20      	cmp	r3, #32
 8004cfa:	d00a      	beq.n	8004d12 <UART_SetConfig+0x18a>
 8004cfc:	2b20      	cmp	r3, #32
 8004cfe:	d814      	bhi.n	8004d2a <UART_SetConfig+0x1a2>
 8004d00:	2b00      	cmp	r3, #0
 8004d02:	d002      	beq.n	8004d0a <UART_SetConfig+0x182>
 8004d04:	2b10      	cmp	r3, #16
 8004d06:	d008      	beq.n	8004d1a <UART_SetConfig+0x192>
 8004d08:	e00f      	b.n	8004d2a <UART_SetConfig+0x1a2>
 8004d0a:	2300      	movs	r3, #0
 8004d0c:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d10:	e0ad      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d12:	2302      	movs	r3, #2
 8004d14:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d18:	e0a9      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d1a:	2304      	movs	r3, #4
 8004d1c:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d20:	e0a5      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d22:	2308      	movs	r3, #8
 8004d24:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d28:	e0a1      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d2a:	2310      	movs	r3, #16
 8004d2c:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d30:	e09d      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d32:	68fb      	ldr	r3, [r7, #12]
 8004d34:	681b      	ldr	r3, [r3, #0]
 8004d36:	4a4a      	ldr	r2, [pc, #296]	@ (8004e60 <UART_SetConfig+0x2d8>)
 8004d38:	4293      	cmp	r3, r2
 8004d3a:	d125      	bne.n	8004d88 <UART_SetConfig+0x200>
 8004d3c:	4b45      	ldr	r3, [pc, #276]	@ (8004e54 <UART_SetConfig+0x2cc>)
 8004d3e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8004d42:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
 8004d46:	2bc0      	cmp	r3, #192	@ 0xc0
 8004d48:	d016      	beq.n	8004d78 <UART_SetConfig+0x1f0>
 8004d4a:	2bc0      	cmp	r3, #192	@ 0xc0
 8004d4c:	d818      	bhi.n	8004d80 <UART_SetConfig+0x1f8>
 8004d4e:	2b80      	cmp	r3, #128	@ 0x80
 8004d50:	d00a      	beq.n	8004d68 <UART_SetConfig+0x1e0>
 8004d52:	2b80      	cmp	r3, #128	@ 0x80
 8004d54:	d814      	bhi.n	8004d80 <UART_SetConfig+0x1f8>
 8004d56:	2b00      	cmp	r3, #0
 8004d58:	d002      	beq.n	8004d60 <UART_SetConfig+0x1d8>
 8004d5a:	2b40      	cmp	r3, #64	@ 0x40
 8004d5c:	d008      	beq.n	8004d70 <UART_SetConfig+0x1e8>
 8004d5e:	e00f      	b.n	8004d80 <UART_SetConfig+0x1f8>
 8004d60:	2300      	movs	r3, #0
 8004d62:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d66:	e082      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d68:	2302      	movs	r3, #2
 8004d6a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d6e:	e07e      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d70:	2304      	movs	r3, #4
 8004d72:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d76:	e07a      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d78:	2308      	movs	r3, #8
 8004d7a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d7e:	e076      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d80:	2310      	movs	r3, #16
 8004d82:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004d86:	e072      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004d88:	68fb      	ldr	r3, [r7, #12]
 8004d8a:	681b      	ldr	r3, [r3, #0]
 8004d8c:	4a35      	ldr	r2, [pc, #212]	@ (8004e64 <UART_SetConfig+0x2dc>)
 8004d8e:	4293      	cmp	r3, r2
 8004d90:	d12a      	bne.n	8004de8 <UART_SetConfig+0x260>
 8004d92:	4b30      	ldr	r3, [pc, #192]	@ (8004e54 <UART_SetConfig+0x2cc>)
 8004d94:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8004d98:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 8004d9c:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 8004da0:	d01a      	beq.n	8004dd8 <UART_SetConfig+0x250>
 8004da2:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 8004da6:	d81b      	bhi.n	8004de0 <UART_SetConfig+0x258>
 8004da8:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 8004dac:	d00c      	beq.n	8004dc8 <UART_SetConfig+0x240>
 8004dae:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 8004db2:	d815      	bhi.n	8004de0 <UART_SetConfig+0x258>
 8004db4:	2b00      	cmp	r3, #0
 8004db6:	d003      	beq.n	8004dc0 <UART_SetConfig+0x238>
 8004db8:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 8004dbc:	d008      	beq.n	8004dd0 <UART_SetConfig+0x248>
 8004dbe:	e00f      	b.n	8004de0 <UART_SetConfig+0x258>
 8004dc0:	2300      	movs	r3, #0
 8004dc2:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004dc6:	e052      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004dc8:	2302      	movs	r3, #2
 8004dca:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004dce:	e04e      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004dd0:	2304      	movs	r3, #4
 8004dd2:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004dd6:	e04a      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004dd8:	2308      	movs	r3, #8
 8004dda:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004dde:	e046      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004de0:	2310      	movs	r3, #16
 8004de2:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004de6:	e042      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004de8:	68fb      	ldr	r3, [r7, #12]
 8004dea:	681b      	ldr	r3, [r3, #0]
 8004dec:	4a17      	ldr	r2, [pc, #92]	@ (8004e4c <UART_SetConfig+0x2c4>)
 8004dee:	4293      	cmp	r3, r2
 8004df0:	d13a      	bne.n	8004e68 <UART_SetConfig+0x2e0>
 8004df2:	4b18      	ldr	r3, [pc, #96]	@ (8004e54 <UART_SetConfig+0x2cc>)
 8004df4:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8004df8:	f403 6340 	and.w	r3, r3, #3072	@ 0xc00
 8004dfc:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 8004e00:	d01a      	beq.n	8004e38 <UART_SetConfig+0x2b0>
 8004e02:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 8004e06:	d81b      	bhi.n	8004e40 <UART_SetConfig+0x2b8>
 8004e08:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8004e0c:	d00c      	beq.n	8004e28 <UART_SetConfig+0x2a0>
 8004e0e:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8004e12:	d815      	bhi.n	8004e40 <UART_SetConfig+0x2b8>
 8004e14:	2b00      	cmp	r3, #0
 8004e16:	d003      	beq.n	8004e20 <UART_SetConfig+0x298>
 8004e18:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 8004e1c:	d008      	beq.n	8004e30 <UART_SetConfig+0x2a8>
 8004e1e:	e00f      	b.n	8004e40 <UART_SetConfig+0x2b8>
 8004e20:	2300      	movs	r3, #0
 8004e22:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004e26:	e022      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004e28:	2302      	movs	r3, #2
 8004e2a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004e2e:	e01e      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004e30:	2304      	movs	r3, #4
 8004e32:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004e36:	e01a      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004e38:	2308      	movs	r3, #8
 8004e3a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004e3e:	e016      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004e40:	2310      	movs	r3, #16
 8004e42:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8004e46:	e012      	b.n	8004e6e <UART_SetConfig+0x2e6>
 8004e48:	efff69f3 	.word	0xefff69f3
 8004e4c:	40008000 	.word	0x40008000
 8004e50:	40013800 	.word	0x40013800
 8004e54:	40021000 	.word	0x40021000
 8004e58:	40004400 	.word	0x40004400
 8004e5c:	40004800 	.word	0x40004800
 8004e60:	40004c00 	.word	0x40004c00
 8004e64:	40005000 	.word	0x40005000
 8004e68:	2310      	movs	r3, #16
 8004e6a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23

  /* Check LPUART instance */
  if (UART_INSTANCE_LOWPOWER(huart))
 8004e6e:	68fb      	ldr	r3, [r7, #12]
 8004e70:	681b      	ldr	r3, [r3, #0]
 8004e72:	4a9f      	ldr	r2, [pc, #636]	@ (80050f0 <UART_SetConfig+0x568>)
 8004e74:	4293      	cmp	r3, r2
 8004e76:	d17a      	bne.n	8004f6e <UART_SetConfig+0x3e6>
  {
    /* Retrieve frequency clock */
    switch (clocksource)
 8004e78:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 8004e7c:	2b08      	cmp	r3, #8
 8004e7e:	d824      	bhi.n	8004eca <UART_SetConfig+0x342>
 8004e80:	a201      	add	r2, pc, #4	@ (adr r2, 8004e88 <UART_SetConfig+0x300>)
 8004e82:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8004e86:	bf00      	nop
 8004e88:	08004ead 	.word	0x08004ead
 8004e8c:	08004ecb 	.word	0x08004ecb
 8004e90:	08004eb5 	.word	0x08004eb5
 8004e94:	08004ecb 	.word	0x08004ecb
 8004e98:	08004ebb 	.word	0x08004ebb
 8004e9c:	08004ecb 	.word	0x08004ecb
 8004ea0:	08004ecb 	.word	0x08004ecb
 8004ea4:	08004ecb 	.word	0x08004ecb
 8004ea8:	08004ec3 	.word	0x08004ec3
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8004eac:	f7fe f966 	bl	800317c <HAL_RCC_GetPCLK1Freq>
 8004eb0:	61f8      	str	r0, [r7, #28]
        break;
 8004eb2:	e010      	b.n	8004ed6 <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8004eb4:	4b8f      	ldr	r3, [pc, #572]	@ (80050f4 <UART_SetConfig+0x56c>)
 8004eb6:	61fb      	str	r3, [r7, #28]
        break;
 8004eb8:	e00d      	b.n	8004ed6 <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 8004eba:	f7fe f8c7 	bl	800304c <HAL_RCC_GetSysClockFreq>
 8004ebe:	61f8      	str	r0, [r7, #28]
        break;
 8004ec0:	e009      	b.n	8004ed6 <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8004ec2:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8004ec6:	61fb      	str	r3, [r7, #28]
        break;
 8004ec8:	e005      	b.n	8004ed6 <UART_SetConfig+0x34e>
      default:
        pclk = 0U;
 8004eca:	2300      	movs	r3, #0
 8004ecc:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8004ece:	2301      	movs	r3, #1
 8004ed0:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 8004ed4:	bf00      	nop
    }

    /* If proper clock source reported */
    if (pclk != 0U)
 8004ed6:	69fb      	ldr	r3, [r7, #28]
 8004ed8:	2b00      	cmp	r3, #0
 8004eda:	f000 80fb 	beq.w	80050d4 <UART_SetConfig+0x54c>
      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
#else
      /* No Prescaler applicable */
      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
      if ((pclk < (3U * huart->Init.BaudRate)) ||
 8004ede:	68fb      	ldr	r3, [r7, #12]
 8004ee0:	685a      	ldr	r2, [r3, #4]
 8004ee2:	4613      	mov	r3, r2
 8004ee4:	005b      	lsls	r3, r3, #1
 8004ee6:	4413      	add	r3, r2
 8004ee8:	69fa      	ldr	r2, [r7, #28]
 8004eea:	429a      	cmp	r2, r3
 8004eec:	d305      	bcc.n	8004efa <UART_SetConfig+0x372>
          (pclk > (4096U * huart->Init.BaudRate)))
 8004eee:	68fb      	ldr	r3, [r7, #12]
 8004ef0:	685b      	ldr	r3, [r3, #4]
 8004ef2:	031b      	lsls	r3, r3, #12
      if ((pclk < (3U * huart->Init.BaudRate)) ||
 8004ef4:	69fa      	ldr	r2, [r7, #28]
 8004ef6:	429a      	cmp	r2, r3
 8004ef8:	d903      	bls.n	8004f02 <UART_SetConfig+0x37a>
      {
        ret = HAL_ERROR;
 8004efa:	2301      	movs	r3, #1
 8004efc:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 8004f00:	e0e8      	b.n	80050d4 <UART_SetConfig+0x54c>
      }
      else
      {
        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
 8004f02:	69fb      	ldr	r3, [r7, #28]
 8004f04:	2200      	movs	r2, #0
 8004f06:	461c      	mov	r4, r3
 8004f08:	4615      	mov	r5, r2
 8004f0a:	f04f 0200 	mov.w	r2, #0
 8004f0e:	f04f 0300 	mov.w	r3, #0
 8004f12:	022b      	lsls	r3, r5, #8
 8004f14:	ea43 6314 	orr.w	r3, r3, r4, lsr #24
 8004f18:	0222      	lsls	r2, r4, #8
 8004f1a:	68f9      	ldr	r1, [r7, #12]
 8004f1c:	6849      	ldr	r1, [r1, #4]
 8004f1e:	0849      	lsrs	r1, r1, #1
 8004f20:	2000      	movs	r0, #0
 8004f22:	4688      	mov	r8, r1
 8004f24:	4681      	mov	r9, r0
 8004f26:	eb12 0a08 	adds.w	sl, r2, r8
 8004f2a:	eb43 0b09 	adc.w	fp, r3, r9
 8004f2e:	68fb      	ldr	r3, [r7, #12]
 8004f30:	685b      	ldr	r3, [r3, #4]
 8004f32:	2200      	movs	r2, #0
 8004f34:	603b      	str	r3, [r7, #0]
 8004f36:	607a      	str	r2, [r7, #4]
 8004f38:	e9d7 2300 	ldrd	r2, r3, [r7]
 8004f3c:	4650      	mov	r0, sl
 8004f3e:	4659      	mov	r1, fp
 8004f40:	f7fb f946 	bl	80001d0 <__aeabi_uldivmod>
 8004f44:	4602      	mov	r2, r0
 8004f46:	460b      	mov	r3, r1
 8004f48:	4613      	mov	r3, r2
 8004f4a:	61bb      	str	r3, [r7, #24]
        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
 8004f4c:	69bb      	ldr	r3, [r7, #24]
 8004f4e:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 8004f52:	d308      	bcc.n	8004f66 <UART_SetConfig+0x3de>
 8004f54:	69bb      	ldr	r3, [r7, #24]
 8004f56:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 8004f5a:	d204      	bcs.n	8004f66 <UART_SetConfig+0x3de>
        {
          huart->Instance->BRR = usartdiv;
 8004f5c:	68fb      	ldr	r3, [r7, #12]
 8004f5e:	681b      	ldr	r3, [r3, #0]
 8004f60:	69ba      	ldr	r2, [r7, #24]
 8004f62:	60da      	str	r2, [r3, #12]
 8004f64:	e0b6      	b.n	80050d4 <UART_SetConfig+0x54c>
        }
        else
        {
          ret = HAL_ERROR;
 8004f66:	2301      	movs	r3, #1
 8004f68:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 8004f6c:	e0b2      	b.n	80050d4 <UART_SetConfig+0x54c>
      } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
#endif /* USART_PRESC_PRESCALER */
    } /* if (pclk != 0) */
  }
  /* Check UART Over Sampling to set Baud Rate Register */
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8004f6e:	68fb      	ldr	r3, [r7, #12]
 8004f70:	69db      	ldr	r3, [r3, #28]
 8004f72:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 8004f76:	d15e      	bne.n	8005036 <UART_SetConfig+0x4ae>
  {
    switch (clocksource)
 8004f78:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 8004f7c:	2b08      	cmp	r3, #8
 8004f7e:	d828      	bhi.n	8004fd2 <UART_SetConfig+0x44a>
 8004f80:	a201      	add	r2, pc, #4	@ (adr r2, 8004f88 <UART_SetConfig+0x400>)
 8004f82:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8004f86:	bf00      	nop
 8004f88:	08004fad 	.word	0x08004fad
 8004f8c:	08004fb5 	.word	0x08004fb5
 8004f90:	08004fbd 	.word	0x08004fbd
 8004f94:	08004fd3 	.word	0x08004fd3
 8004f98:	08004fc3 	.word	0x08004fc3
 8004f9c:	08004fd3 	.word	0x08004fd3
 8004fa0:	08004fd3 	.word	0x08004fd3
 8004fa4:	08004fd3 	.word	0x08004fd3
 8004fa8:	08004fcb 	.word	0x08004fcb
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8004fac:	f7fe f8e6 	bl	800317c <HAL_RCC_GetPCLK1Freq>
 8004fb0:	61f8      	str	r0, [r7, #28]
        break;
 8004fb2:	e014      	b.n	8004fde <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 8004fb4:	f7fe f8f8 	bl	80031a8 <HAL_RCC_GetPCLK2Freq>
 8004fb8:	61f8      	str	r0, [r7, #28]
        break;
 8004fba:	e010      	b.n	8004fde <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8004fbc:	4b4d      	ldr	r3, [pc, #308]	@ (80050f4 <UART_SetConfig+0x56c>)
 8004fbe:	61fb      	str	r3, [r7, #28]
        break;
 8004fc0:	e00d      	b.n	8004fde <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 8004fc2:	f7fe f843 	bl	800304c <HAL_RCC_GetSysClockFreq>
 8004fc6:	61f8      	str	r0, [r7, #28]
        break;
 8004fc8:	e009      	b.n	8004fde <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8004fca:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8004fce:	61fb      	str	r3, [r7, #28]
        break;
 8004fd0:	e005      	b.n	8004fde <UART_SetConfig+0x456>
      default:
        pclk = 0U;
 8004fd2:	2300      	movs	r3, #0
 8004fd4:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8004fd6:	2301      	movs	r3, #1
 8004fd8:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 8004fdc:	bf00      	nop
    }

    /* USARTDIV must be greater than or equal to 0d16 */
    if (pclk != 0U)
 8004fde:	69fb      	ldr	r3, [r7, #28]
 8004fe0:	2b00      	cmp	r3, #0
 8004fe2:	d077      	beq.n	80050d4 <UART_SetConfig+0x54c>
    {
#if defined(USART_PRESC_PRESCALER)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
 8004fe4:	69fb      	ldr	r3, [r7, #28]
 8004fe6:	005a      	lsls	r2, r3, #1
 8004fe8:	68fb      	ldr	r3, [r7, #12]
 8004fea:	685b      	ldr	r3, [r3, #4]
 8004fec:	085b      	lsrs	r3, r3, #1
 8004fee:	441a      	add	r2, r3
 8004ff0:	68fb      	ldr	r3, [r7, #12]
 8004ff2:	685b      	ldr	r3, [r3, #4]
 8004ff4:	fbb2 f3f3 	udiv	r3, r2, r3
 8004ff8:	61bb      	str	r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8004ffa:	69bb      	ldr	r3, [r7, #24]
 8004ffc:	2b0f      	cmp	r3, #15
 8004ffe:	d916      	bls.n	800502e <UART_SetConfig+0x4a6>
 8005000:	69bb      	ldr	r3, [r7, #24]
 8005002:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8005006:	d212      	bcs.n	800502e <UART_SetConfig+0x4a6>
      {
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 8005008:	69bb      	ldr	r3, [r7, #24]
 800500a:	b29b      	uxth	r3, r3
 800500c:	f023 030f 	bic.w	r3, r3, #15
 8005010:	82fb      	strh	r3, [r7, #22]
        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
 8005012:	69bb      	ldr	r3, [r7, #24]
 8005014:	085b      	lsrs	r3, r3, #1
 8005016:	b29b      	uxth	r3, r3
 8005018:	f003 0307 	and.w	r3, r3, #7
 800501c:	b29a      	uxth	r2, r3
 800501e:	8afb      	ldrh	r3, [r7, #22]
 8005020:	4313      	orrs	r3, r2
 8005022:	82fb      	strh	r3, [r7, #22]
        huart->Instance->BRR = brrtemp;
 8005024:	68fb      	ldr	r3, [r7, #12]
 8005026:	681b      	ldr	r3, [r3, #0]
 8005028:	8afa      	ldrh	r2, [r7, #22]
 800502a:	60da      	str	r2, [r3, #12]
 800502c:	e052      	b.n	80050d4 <UART_SetConfig+0x54c>
      }
      else
      {
        ret = HAL_ERROR;
 800502e:	2301      	movs	r3, #1
 8005030:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 8005034:	e04e      	b.n	80050d4 <UART_SetConfig+0x54c>
      }
    }
  }
  else
  {
    switch (clocksource)
 8005036:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 800503a:	2b08      	cmp	r3, #8
 800503c:	d827      	bhi.n	800508e <UART_SetConfig+0x506>
 800503e:	a201      	add	r2, pc, #4	@ (adr r2, 8005044 <UART_SetConfig+0x4bc>)
 8005040:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8005044:	08005069 	.word	0x08005069
 8005048:	08005071 	.word	0x08005071
 800504c:	08005079 	.word	0x08005079
 8005050:	0800508f 	.word	0x0800508f
 8005054:	0800507f 	.word	0x0800507f
 8005058:	0800508f 	.word	0x0800508f
 800505c:	0800508f 	.word	0x0800508f
 8005060:	0800508f 	.word	0x0800508f
 8005064:	08005087 	.word	0x08005087
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8005068:	f7fe f888 	bl	800317c <HAL_RCC_GetPCLK1Freq>
 800506c:	61f8      	str	r0, [r7, #28]
        break;
 800506e:	e014      	b.n	800509a <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 8005070:	f7fe f89a 	bl	80031a8 <HAL_RCC_GetPCLK2Freq>
 8005074:	61f8      	str	r0, [r7, #28]
        break;
 8005076:	e010      	b.n	800509a <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8005078:	4b1e      	ldr	r3, [pc, #120]	@ (80050f4 <UART_SetConfig+0x56c>)
 800507a:	61fb      	str	r3, [r7, #28]
        break;
 800507c:	e00d      	b.n	800509a <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 800507e:	f7fd ffe5 	bl	800304c <HAL_RCC_GetSysClockFreq>
 8005082:	61f8      	str	r0, [r7, #28]
        break;
 8005084:	e009      	b.n	800509a <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8005086:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 800508a:	61fb      	str	r3, [r7, #28]
        break;
 800508c:	e005      	b.n	800509a <UART_SetConfig+0x512>
      default:
        pclk = 0U;
 800508e:	2300      	movs	r3, #0
 8005090:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8005092:	2301      	movs	r3, #1
 8005094:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 8005098:	bf00      	nop
    }

    if (pclk != 0U)
 800509a:	69fb      	ldr	r3, [r7, #28]
 800509c:	2b00      	cmp	r3, #0
 800509e:	d019      	beq.n	80050d4 <UART_SetConfig+0x54c>
    {
      /* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
 80050a0:	68fb      	ldr	r3, [r7, #12]
 80050a2:	685b      	ldr	r3, [r3, #4]
 80050a4:	085a      	lsrs	r2, r3, #1
 80050a6:	69fb      	ldr	r3, [r7, #28]
 80050a8:	441a      	add	r2, r3
 80050aa:	68fb      	ldr	r3, [r7, #12]
 80050ac:	685b      	ldr	r3, [r3, #4]
 80050ae:	fbb2 f3f3 	udiv	r3, r2, r3
 80050b2:	61bb      	str	r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 80050b4:	69bb      	ldr	r3, [r7, #24]
 80050b6:	2b0f      	cmp	r3, #15
 80050b8:	d909      	bls.n	80050ce <UART_SetConfig+0x546>
 80050ba:	69bb      	ldr	r3, [r7, #24]
 80050bc:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 80050c0:	d205      	bcs.n	80050ce <UART_SetConfig+0x546>
      {
        huart->Instance->BRR = (uint16_t)usartdiv;
 80050c2:	69bb      	ldr	r3, [r7, #24]
 80050c4:	b29a      	uxth	r2, r3
 80050c6:	68fb      	ldr	r3, [r7, #12]
 80050c8:	681b      	ldr	r3, [r3, #0]
 80050ca:	60da      	str	r2, [r3, #12]
 80050cc:	e002      	b.n	80050d4 <UART_SetConfig+0x54c>
      }
      else
      {
        ret = HAL_ERROR;
 80050ce:	2301      	movs	r3, #1
 80050d0:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
  huart->NbTxDataToProcess = 1;
  huart->NbRxDataToProcess = 1;
#endif /* USART_CR1_FIFOEN */

  /* Clear ISR function pointers */
  huart->RxISR = NULL;
 80050d4:	68fb      	ldr	r3, [r7, #12]
 80050d6:	2200      	movs	r2, #0
 80050d8:	669a      	str	r2, [r3, #104]	@ 0x68
  huart->TxISR = NULL;
 80050da:	68fb      	ldr	r3, [r7, #12]
 80050dc:	2200      	movs	r2, #0
 80050de:	66da      	str	r2, [r3, #108]	@ 0x6c

  return ret;
 80050e0:	f897 3022 	ldrb.w	r3, [r7, #34]	@ 0x22
}
 80050e4:	4618      	mov	r0, r3
 80050e6:	3728      	adds	r7, #40	@ 0x28
 80050e8:	46bd      	mov	sp, r7
 80050ea:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 80050ee:	bf00      	nop
 80050f0:	40008000 	.word	0x40008000
 80050f4:	00f42400 	.word	0x00f42400

080050f8 <UART_AdvFeatureConfig>:
  * @brief Configure the UART peripheral advanced features.
  * @param huart UART handle.
  * @retval None
  */
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
 80050f8:	b480      	push	{r7}
 80050fa:	b083      	sub	sp, #12
 80050fc:	af00      	add	r7, sp, #0
 80050fe:	6078      	str	r0, [r7, #4]
  /* Check whether the set of advanced features to configure is properly set */
  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));

  /* if required, configure RX/TX pins swap */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 8005100:	687b      	ldr	r3, [r7, #4]
 8005102:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005104:	f003 0308 	and.w	r3, r3, #8
 8005108:	2b00      	cmp	r3, #0
 800510a:	d00a      	beq.n	8005122 <UART_AdvFeatureConfig+0x2a>
  {
    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
 800510c:	687b      	ldr	r3, [r7, #4]
 800510e:	681b      	ldr	r3, [r3, #0]
 8005110:	685b      	ldr	r3, [r3, #4]
 8005112:	f423 4100 	bic.w	r1, r3, #32768	@ 0x8000
 8005116:	687b      	ldr	r3, [r7, #4]
 8005118:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 800511a:	687b      	ldr	r3, [r7, #4]
 800511c:	681b      	ldr	r3, [r3, #0]
 800511e:	430a      	orrs	r2, r1
 8005120:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure TX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
 8005122:	687b      	ldr	r3, [r7, #4]
 8005124:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005126:	f003 0301 	and.w	r3, r3, #1
 800512a:	2b00      	cmp	r3, #0
 800512c:	d00a      	beq.n	8005144 <UART_AdvFeatureConfig+0x4c>
  {
    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
 800512e:	687b      	ldr	r3, [r7, #4]
 8005130:	681b      	ldr	r3, [r3, #0]
 8005132:	685b      	ldr	r3, [r3, #4]
 8005134:	f423 3100 	bic.w	r1, r3, #131072	@ 0x20000
 8005138:	687b      	ldr	r3, [r7, #4]
 800513a:	6a9a      	ldr	r2, [r3, #40]	@ 0x28
 800513c:	687b      	ldr	r3, [r7, #4]
 800513e:	681b      	ldr	r3, [r3, #0]
 8005140:	430a      	orrs	r2, r1
 8005142:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
 8005144:	687b      	ldr	r3, [r7, #4]
 8005146:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005148:	f003 0302 	and.w	r3, r3, #2
 800514c:	2b00      	cmp	r3, #0
 800514e:	d00a      	beq.n	8005166 <UART_AdvFeatureConfig+0x6e>
  {
    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
 8005150:	687b      	ldr	r3, [r7, #4]
 8005152:	681b      	ldr	r3, [r3, #0]
 8005154:	685b      	ldr	r3, [r3, #4]
 8005156:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
 800515a:	687b      	ldr	r3, [r7, #4]
 800515c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800515e:	687b      	ldr	r3, [r7, #4]
 8005160:	681b      	ldr	r3, [r3, #0]
 8005162:	430a      	orrs	r2, r1
 8005164:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure data inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
 8005166:	687b      	ldr	r3, [r7, #4]
 8005168:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800516a:	f003 0304 	and.w	r3, r3, #4
 800516e:	2b00      	cmp	r3, #0
 8005170:	d00a      	beq.n	8005188 <UART_AdvFeatureConfig+0x90>
  {
    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
 8005172:	687b      	ldr	r3, [r7, #4]
 8005174:	681b      	ldr	r3, [r3, #0]
 8005176:	685b      	ldr	r3, [r3, #4]
 8005178:	f423 2180 	bic.w	r1, r3, #262144	@ 0x40000
 800517c:	687b      	ldr	r3, [r7, #4]
 800517e:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 8005180:	687b      	ldr	r3, [r7, #4]
 8005182:	681b      	ldr	r3, [r3, #0]
 8005184:	430a      	orrs	r2, r1
 8005186:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX overrun detection disabling */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
 8005188:	687b      	ldr	r3, [r7, #4]
 800518a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800518c:	f003 0310 	and.w	r3, r3, #16
 8005190:	2b00      	cmp	r3, #0
 8005192:	d00a      	beq.n	80051aa <UART_AdvFeatureConfig+0xb2>
  {
    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
 8005194:	687b      	ldr	r3, [r7, #4]
 8005196:	681b      	ldr	r3, [r3, #0]
 8005198:	689b      	ldr	r3, [r3, #8]
 800519a:	f423 5180 	bic.w	r1, r3, #4096	@ 0x1000
 800519e:	687b      	ldr	r3, [r7, #4]
 80051a0:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 80051a2:	687b      	ldr	r3, [r7, #4]
 80051a4:	681b      	ldr	r3, [r3, #0]
 80051a6:	430a      	orrs	r2, r1
 80051a8:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure DMA disabling on reception error */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
 80051aa:	687b      	ldr	r3, [r7, #4]
 80051ac:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80051ae:	f003 0320 	and.w	r3, r3, #32
 80051b2:	2b00      	cmp	r3, #0
 80051b4:	d00a      	beq.n	80051cc <UART_AdvFeatureConfig+0xd4>
  {
    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
 80051b6:	687b      	ldr	r3, [r7, #4]
 80051b8:	681b      	ldr	r3, [r3, #0]
 80051ba:	689b      	ldr	r3, [r3, #8]
 80051bc:	f423 5100 	bic.w	r1, r3, #8192	@ 0x2000
 80051c0:	687b      	ldr	r3, [r7, #4]
 80051c2:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 80051c4:	687b      	ldr	r3, [r7, #4]
 80051c6:	681b      	ldr	r3, [r3, #0]
 80051c8:	430a      	orrs	r2, r1
 80051ca:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure auto Baud rate detection scheme */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
 80051cc:	687b      	ldr	r3, [r7, #4]
 80051ce:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80051d0:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 80051d4:	2b00      	cmp	r3, #0
 80051d6:	d01a      	beq.n	800520e <UART_AdvFeatureConfig+0x116>
  {
    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 80051d8:	687b      	ldr	r3, [r7, #4]
 80051da:	681b      	ldr	r3, [r3, #0]
 80051dc:	685b      	ldr	r3, [r3, #4]
 80051de:	f423 1180 	bic.w	r1, r3, #1048576	@ 0x100000
 80051e2:	687b      	ldr	r3, [r7, #4]
 80051e4:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
 80051e6:	687b      	ldr	r3, [r7, #4]
 80051e8:	681b      	ldr	r3, [r3, #0]
 80051ea:	430a      	orrs	r2, r1
 80051ec:	605a      	str	r2, [r3, #4]
    /* set auto Baudrate detection parameters if detection is enabled */
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 80051ee:	687b      	ldr	r3, [r7, #4]
 80051f0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80051f2:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 80051f6:	d10a      	bne.n	800520e <UART_AdvFeatureConfig+0x116>
    {
      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
 80051f8:	687b      	ldr	r3, [r7, #4]
 80051fa:	681b      	ldr	r3, [r3, #0]
 80051fc:	685b      	ldr	r3, [r3, #4]
 80051fe:	f423 01c0 	bic.w	r1, r3, #6291456	@ 0x600000
 8005202:	687b      	ldr	r3, [r7, #4]
 8005204:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 8005206:	687b      	ldr	r3, [r7, #4]
 8005208:	681b      	ldr	r3, [r3, #0]
 800520a:	430a      	orrs	r2, r1
 800520c:	605a      	str	r2, [r3, #4]
    }
  }

  /* if required, configure MSB first on communication line */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
 800520e:	687b      	ldr	r3, [r7, #4]
 8005210:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005212:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8005216:	2b00      	cmp	r3, #0
 8005218:	d00a      	beq.n	8005230 <UART_AdvFeatureConfig+0x138>
  {
    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
 800521a:	687b      	ldr	r3, [r7, #4]
 800521c:	681b      	ldr	r3, [r3, #0]
 800521e:	685b      	ldr	r3, [r3, #4]
 8005220:	f423 2100 	bic.w	r1, r3, #524288	@ 0x80000
 8005224:	687b      	ldr	r3, [r7, #4]
 8005226:	6c9a      	ldr	r2, [r3, #72]	@ 0x48
 8005228:	687b      	ldr	r3, [r7, #4]
 800522a:	681b      	ldr	r3, [r3, #0]
 800522c:	430a      	orrs	r2, r1
 800522e:	605a      	str	r2, [r3, #4]
  }
}
 8005230:	bf00      	nop
 8005232:	370c      	adds	r7, #12
 8005234:	46bd      	mov	sp, r7
 8005236:	f85d 7b04 	ldr.w	r7, [sp], #4
 800523a:	4770      	bx	lr

0800523c <UART_CheckIdleState>:
  * @brief Check the UART Idle State.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
 800523c:	b580      	push	{r7, lr}
 800523e:	b098      	sub	sp, #96	@ 0x60
 8005240:	af02      	add	r7, sp, #8
 8005242:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  /* Initialize the UART ErrorCode */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005244:	687b      	ldr	r3, [r7, #4]
 8005246:	2200      	movs	r2, #0
 8005248:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

  /* Init tickstart for timeout management */
  tickstart = HAL_GetTick();
 800524c:	f7fc f9fa 	bl	8001644 <HAL_GetTick>
 8005250:	6578      	str	r0, [r7, #84]	@ 0x54

  /* Check if the Transmitter is enabled */
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 8005252:	687b      	ldr	r3, [r7, #4]
 8005254:	681b      	ldr	r3, [r3, #0]
 8005256:	681b      	ldr	r3, [r3, #0]
 8005258:	f003 0308 	and.w	r3, r3, #8
 800525c:	2b08      	cmp	r3, #8
 800525e:	d12e      	bne.n	80052be <UART_CheckIdleState+0x82>
  {
    /* Wait until TEACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 8005260:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 8005264:	9300      	str	r3, [sp, #0]
 8005266:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8005268:	2200      	movs	r2, #0
 800526a:	f44f 1100 	mov.w	r1, #2097152	@ 0x200000
 800526e:	6878      	ldr	r0, [r7, #4]
 8005270:	f000 f88c 	bl	800538c <UART_WaitOnFlagUntilTimeout>
 8005274:	4603      	mov	r3, r0
 8005276:	2b00      	cmp	r3, #0
 8005278:	d021      	beq.n	80052be <UART_CheckIdleState+0x82>
    {
      /* Disable TXE interrupt for the interrupt process */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
 800527a:	687b      	ldr	r3, [r7, #4]
 800527c:	681b      	ldr	r3, [r3, #0]
 800527e:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005280:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005282:	e853 3f00 	ldrex	r3, [r3]
 8005286:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 8005288:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800528a:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 800528e:	653b      	str	r3, [r7, #80]	@ 0x50
 8005290:	687b      	ldr	r3, [r7, #4]
 8005292:	681b      	ldr	r3, [r3, #0]
 8005294:	461a      	mov	r2, r3
 8005296:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8005298:	647b      	str	r3, [r7, #68]	@ 0x44
 800529a:	643a      	str	r2, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800529c:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 800529e:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 80052a0:	e841 2300 	strex	r3, r2, [r1]
 80052a4:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 80052a6:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 80052a8:	2b00      	cmp	r3, #0
 80052aa:	d1e6      	bne.n	800527a <UART_CheckIdleState+0x3e>
#endif /* USART_CR1_FIFOEN */

      huart->gState = HAL_UART_STATE_READY;
 80052ac:	687b      	ldr	r3, [r7, #4]
 80052ae:	2220      	movs	r2, #32
 80052b0:	67da      	str	r2, [r3, #124]	@ 0x7c

      __HAL_UNLOCK(huart);
 80052b2:	687b      	ldr	r3, [r7, #4]
 80052b4:	2200      	movs	r2, #0
 80052b6:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

      /* Timeout occurred */
      return HAL_TIMEOUT;
 80052ba:	2303      	movs	r3, #3
 80052bc:	e062      	b.n	8005384 <UART_CheckIdleState+0x148>
    }
  }

  /* Check if the Receiver is enabled */
  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
 80052be:	687b      	ldr	r3, [r7, #4]
 80052c0:	681b      	ldr	r3, [r3, #0]
 80052c2:	681b      	ldr	r3, [r3, #0]
 80052c4:	f003 0304 	and.w	r3, r3, #4
 80052c8:	2b04      	cmp	r3, #4
 80052ca:	d149      	bne.n	8005360 <UART_CheckIdleState+0x124>
  {
    /* Wait until REACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 80052cc:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 80052d0:	9300      	str	r3, [sp, #0]
 80052d2:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 80052d4:	2200      	movs	r2, #0
 80052d6:	f44f 0180 	mov.w	r1, #4194304	@ 0x400000
 80052da:	6878      	ldr	r0, [r7, #4]
 80052dc:	f000 f856 	bl	800538c <UART_WaitOnFlagUntilTimeout>
 80052e0:	4603      	mov	r3, r0
 80052e2:	2b00      	cmp	r3, #0
 80052e4:	d03c      	beq.n	8005360 <UART_CheckIdleState+0x124>
      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
      interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 80052e6:	687b      	ldr	r3, [r7, #4]
 80052e8:	681b      	ldr	r3, [r3, #0]
 80052ea:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80052ec:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80052ee:	e853 3f00 	ldrex	r3, [r3]
 80052f2:	623b      	str	r3, [r7, #32]
   return(result);
 80052f4:	6a3b      	ldr	r3, [r7, #32]
 80052f6:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 80052fa:	64fb      	str	r3, [r7, #76]	@ 0x4c
 80052fc:	687b      	ldr	r3, [r7, #4]
 80052fe:	681b      	ldr	r3, [r3, #0]
 8005300:	461a      	mov	r2, r3
 8005302:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8005304:	633b      	str	r3, [r7, #48]	@ 0x30
 8005306:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005308:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 800530a:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800530c:	e841 2300 	strex	r3, r2, [r1]
 8005310:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 8005312:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005314:	2b00      	cmp	r3, #0
 8005316:	d1e6      	bne.n	80052e6 <UART_CheckIdleState+0xaa>
#endif /* USART_CR1_FIFOEN */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8005318:	687b      	ldr	r3, [r7, #4]
 800531a:	681b      	ldr	r3, [r3, #0]
 800531c:	3308      	adds	r3, #8
 800531e:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005320:	693b      	ldr	r3, [r7, #16]
 8005322:	e853 3f00 	ldrex	r3, [r3]
 8005326:	60fb      	str	r3, [r7, #12]
   return(result);
 8005328:	68fb      	ldr	r3, [r7, #12]
 800532a:	f023 0301 	bic.w	r3, r3, #1
 800532e:	64bb      	str	r3, [r7, #72]	@ 0x48
 8005330:	687b      	ldr	r3, [r7, #4]
 8005332:	681b      	ldr	r3, [r3, #0]
 8005334:	3308      	adds	r3, #8
 8005336:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 8005338:	61fa      	str	r2, [r7, #28]
 800533a:	61bb      	str	r3, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800533c:	69b9      	ldr	r1, [r7, #24]
 800533e:	69fa      	ldr	r2, [r7, #28]
 8005340:	e841 2300 	strex	r3, r2, [r1]
 8005344:	617b      	str	r3, [r7, #20]
   return(result);
 8005346:	697b      	ldr	r3, [r7, #20]
 8005348:	2b00      	cmp	r3, #0
 800534a:	d1e5      	bne.n	8005318 <UART_CheckIdleState+0xdc>

      huart->RxState = HAL_UART_STATE_READY;
 800534c:	687b      	ldr	r3, [r7, #4]
 800534e:	2220      	movs	r2, #32
 8005350:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80

      __HAL_UNLOCK(huart);
 8005354:	687b      	ldr	r3, [r7, #4]
 8005356:	2200      	movs	r2, #0
 8005358:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

      /* Timeout occurred */
      return HAL_TIMEOUT;
 800535c:	2303      	movs	r3, #3
 800535e:	e011      	b.n	8005384 <UART_CheckIdleState+0x148>
    }
  }

  /* Initialize the UART State */
  huart->gState = HAL_UART_STATE_READY;
 8005360:	687b      	ldr	r3, [r7, #4]
 8005362:	2220      	movs	r2, #32
 8005364:	67da      	str	r2, [r3, #124]	@ 0x7c
  huart->RxState = HAL_UART_STATE_READY;
 8005366:	687b      	ldr	r3, [r7, #4]
 8005368:	2220      	movs	r2, #32
 800536a:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800536e:	687b      	ldr	r3, [r7, #4]
 8005370:	2200      	movs	r2, #0
 8005372:	661a      	str	r2, [r3, #96]	@ 0x60
  huart->RxEventType = HAL_UART_RXEVENT_TC;
 8005374:	687b      	ldr	r3, [r7, #4]
 8005376:	2200      	movs	r2, #0
 8005378:	665a      	str	r2, [r3, #100]	@ 0x64

  __HAL_UNLOCK(huart);
 800537a:	687b      	ldr	r3, [r7, #4]
 800537c:	2200      	movs	r2, #0
 800537e:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

  return HAL_OK;
 8005382:	2300      	movs	r3, #0
}
 8005384:	4618      	mov	r0, r3
 8005386:	3758      	adds	r7, #88	@ 0x58
 8005388:	46bd      	mov	sp, r7
 800538a:	bd80      	pop	{r7, pc}

0800538c <UART_WaitOnFlagUntilTimeout>:
  * @param Timeout   Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                              uint32_t Tickstart, uint32_t Timeout)
{
 800538c:	b580      	push	{r7, lr}
 800538e:	b084      	sub	sp, #16
 8005390:	af00      	add	r7, sp, #0
 8005392:	60f8      	str	r0, [r7, #12]
 8005394:	60b9      	str	r1, [r7, #8]
 8005396:	603b      	str	r3, [r7, #0]
 8005398:	4613      	mov	r3, r2
 800539a:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 800539c:	e04f      	b.n	800543e <UART_WaitOnFlagUntilTimeout+0xb2>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 800539e:	69bb      	ldr	r3, [r7, #24]
 80053a0:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80053a4:	d04b      	beq.n	800543e <UART_WaitOnFlagUntilTimeout+0xb2>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 80053a6:	f7fc f94d 	bl	8001644 <HAL_GetTick>
 80053aa:	4602      	mov	r2, r0
 80053ac:	683b      	ldr	r3, [r7, #0]
 80053ae:	1ad3      	subs	r3, r2, r3
 80053b0:	69ba      	ldr	r2, [r7, #24]
 80053b2:	429a      	cmp	r2, r3
 80053b4:	d302      	bcc.n	80053bc <UART_WaitOnFlagUntilTimeout+0x30>
 80053b6:	69bb      	ldr	r3, [r7, #24]
 80053b8:	2b00      	cmp	r3, #0
 80053ba:	d101      	bne.n	80053c0 <UART_WaitOnFlagUntilTimeout+0x34>
      {

        return HAL_TIMEOUT;
 80053bc:	2303      	movs	r3, #3
 80053be:	e04e      	b.n	800545e <UART_WaitOnFlagUntilTimeout+0xd2>
      }

      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 80053c0:	68fb      	ldr	r3, [r7, #12]
 80053c2:	681b      	ldr	r3, [r3, #0]
 80053c4:	681b      	ldr	r3, [r3, #0]
 80053c6:	f003 0304 	and.w	r3, r3, #4
 80053ca:	2b00      	cmp	r3, #0
 80053cc:	d037      	beq.n	800543e <UART_WaitOnFlagUntilTimeout+0xb2>
 80053ce:	68bb      	ldr	r3, [r7, #8]
 80053d0:	2b80      	cmp	r3, #128	@ 0x80
 80053d2:	d034      	beq.n	800543e <UART_WaitOnFlagUntilTimeout+0xb2>
 80053d4:	68bb      	ldr	r3, [r7, #8]
 80053d6:	2b40      	cmp	r3, #64	@ 0x40
 80053d8:	d031      	beq.n	800543e <UART_WaitOnFlagUntilTimeout+0xb2>
      {
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 80053da:	68fb      	ldr	r3, [r7, #12]
 80053dc:	681b      	ldr	r3, [r3, #0]
 80053de:	69db      	ldr	r3, [r3, #28]
 80053e0:	f003 0308 	and.w	r3, r3, #8
 80053e4:	2b08      	cmp	r3, #8
 80053e6:	d110      	bne.n	800540a <UART_WaitOnFlagUntilTimeout+0x7e>
        {
          /* Clear Overrun Error flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 80053e8:	68fb      	ldr	r3, [r7, #12]
 80053ea:	681b      	ldr	r3, [r3, #0]
 80053ec:	2208      	movs	r2, #8
 80053ee:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 80053f0:	68f8      	ldr	r0, [r7, #12]
 80053f2:	f000 f8ff 	bl	80055f4 <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_ORE;
 80053f6:	68fb      	ldr	r3, [r7, #12]
 80053f8:	2208      	movs	r2, #8
 80053fa:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 80053fe:	68fb      	ldr	r3, [r7, #12]
 8005400:	2200      	movs	r2, #0
 8005402:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

          return HAL_ERROR;
 8005406:	2301      	movs	r3, #1
 8005408:	e029      	b.n	800545e <UART_WaitOnFlagUntilTimeout+0xd2>
        }
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 800540a:	68fb      	ldr	r3, [r7, #12]
 800540c:	681b      	ldr	r3, [r3, #0]
 800540e:	69db      	ldr	r3, [r3, #28]
 8005410:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 8005414:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8005418:	d111      	bne.n	800543e <UART_WaitOnFlagUntilTimeout+0xb2>
        {
          /* Clear Receiver Timeout flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 800541a:	68fb      	ldr	r3, [r7, #12]
 800541c:	681b      	ldr	r3, [r3, #0]
 800541e:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8005422:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 8005424:	68f8      	ldr	r0, [r7, #12]
 8005426:	f000 f8e5 	bl	80055f4 <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_RTO;
 800542a:	68fb      	ldr	r3, [r7, #12]
 800542c:	2220      	movs	r2, #32
 800542e:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 8005432:	68fb      	ldr	r3, [r7, #12]
 8005434:	2200      	movs	r2, #0
 8005436:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

          return HAL_TIMEOUT;
 800543a:	2303      	movs	r3, #3
 800543c:	e00f      	b.n	800545e <UART_WaitOnFlagUntilTimeout+0xd2>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 800543e:	68fb      	ldr	r3, [r7, #12]
 8005440:	681b      	ldr	r3, [r3, #0]
 8005442:	69da      	ldr	r2, [r3, #28]
 8005444:	68bb      	ldr	r3, [r7, #8]
 8005446:	4013      	ands	r3, r2
 8005448:	68ba      	ldr	r2, [r7, #8]
 800544a:	429a      	cmp	r2, r3
 800544c:	bf0c      	ite	eq
 800544e:	2301      	moveq	r3, #1
 8005450:	2300      	movne	r3, #0
 8005452:	b2db      	uxtb	r3, r3
 8005454:	461a      	mov	r2, r3
 8005456:	79fb      	ldrb	r3, [r7, #7]
 8005458:	429a      	cmp	r2, r3
 800545a:	d0a0      	beq.n	800539e <UART_WaitOnFlagUntilTimeout+0x12>
        }
      }
    }
  }
  return HAL_OK;
 800545c:	2300      	movs	r3, #0
}
 800545e:	4618      	mov	r0, r3
 8005460:	3710      	adds	r7, #16
 8005462:	46bd      	mov	sp, r7
 8005464:	bd80      	pop	{r7, pc}
	...

08005468 <UART_Start_Receive_IT>:
  * @param  pData Pointer to data buffer (u8 or u16 data elements).
  * @param  Size  Amount of data elements (u8 or u16) to be received.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 8005468:	b480      	push	{r7}
 800546a:	b097      	sub	sp, #92	@ 0x5c
 800546c:	af00      	add	r7, sp, #0
 800546e:	60f8      	str	r0, [r7, #12]
 8005470:	60b9      	str	r1, [r7, #8]
 8005472:	4613      	mov	r3, r2
 8005474:	80fb      	strh	r3, [r7, #6]
  huart->pRxBuffPtr  = pData;
 8005476:	68fb      	ldr	r3, [r7, #12]
 8005478:	68ba      	ldr	r2, [r7, #8]
 800547a:	655a      	str	r2, [r3, #84]	@ 0x54
  huart->RxXferSize  = Size;
 800547c:	68fb      	ldr	r3, [r7, #12]
 800547e:	88fa      	ldrh	r2, [r7, #6]
 8005480:	f8a3 2058 	strh.w	r2, [r3, #88]	@ 0x58
  huart->RxXferCount = Size;
 8005484:	68fb      	ldr	r3, [r7, #12]
 8005486:	88fa      	ldrh	r2, [r7, #6]
 8005488:	f8a3 205a 	strh.w	r2, [r3, #90]	@ 0x5a
  huart->RxISR       = NULL;
 800548c:	68fb      	ldr	r3, [r7, #12]
 800548e:	2200      	movs	r2, #0
 8005490:	669a      	str	r2, [r3, #104]	@ 0x68

  /* Computation of UART mask to apply to RDR register */
  UART_MASK_COMPUTATION(huart);
 8005492:	68fb      	ldr	r3, [r7, #12]
 8005494:	689b      	ldr	r3, [r3, #8]
 8005496:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800549a:	d10e      	bne.n	80054ba <UART_Start_Receive_IT+0x52>
 800549c:	68fb      	ldr	r3, [r7, #12]
 800549e:	691b      	ldr	r3, [r3, #16]
 80054a0:	2b00      	cmp	r3, #0
 80054a2:	d105      	bne.n	80054b0 <UART_Start_Receive_IT+0x48>
 80054a4:	68fb      	ldr	r3, [r7, #12]
 80054a6:	f240 12ff 	movw	r2, #511	@ 0x1ff
 80054aa:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
 80054ae:	e02d      	b.n	800550c <UART_Start_Receive_IT+0xa4>
 80054b0:	68fb      	ldr	r3, [r7, #12]
 80054b2:	22ff      	movs	r2, #255	@ 0xff
 80054b4:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
 80054b8:	e028      	b.n	800550c <UART_Start_Receive_IT+0xa4>
 80054ba:	68fb      	ldr	r3, [r7, #12]
 80054bc:	689b      	ldr	r3, [r3, #8]
 80054be:	2b00      	cmp	r3, #0
 80054c0:	d10d      	bne.n	80054de <UART_Start_Receive_IT+0x76>
 80054c2:	68fb      	ldr	r3, [r7, #12]
 80054c4:	691b      	ldr	r3, [r3, #16]
 80054c6:	2b00      	cmp	r3, #0
 80054c8:	d104      	bne.n	80054d4 <UART_Start_Receive_IT+0x6c>
 80054ca:	68fb      	ldr	r3, [r7, #12]
 80054cc:	22ff      	movs	r2, #255	@ 0xff
 80054ce:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
 80054d2:	e01b      	b.n	800550c <UART_Start_Receive_IT+0xa4>
 80054d4:	68fb      	ldr	r3, [r7, #12]
 80054d6:	227f      	movs	r2, #127	@ 0x7f
 80054d8:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
 80054dc:	e016      	b.n	800550c <UART_Start_Receive_IT+0xa4>
 80054de:	68fb      	ldr	r3, [r7, #12]
 80054e0:	689b      	ldr	r3, [r3, #8]
 80054e2:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 80054e6:	d10d      	bne.n	8005504 <UART_Start_Receive_IT+0x9c>
 80054e8:	68fb      	ldr	r3, [r7, #12]
 80054ea:	691b      	ldr	r3, [r3, #16]
 80054ec:	2b00      	cmp	r3, #0
 80054ee:	d104      	bne.n	80054fa <UART_Start_Receive_IT+0x92>
 80054f0:	68fb      	ldr	r3, [r7, #12]
 80054f2:	227f      	movs	r2, #127	@ 0x7f
 80054f4:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
 80054f8:	e008      	b.n	800550c <UART_Start_Receive_IT+0xa4>
 80054fa:	68fb      	ldr	r3, [r7, #12]
 80054fc:	223f      	movs	r2, #63	@ 0x3f
 80054fe:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
 8005502:	e003      	b.n	800550c <UART_Start_Receive_IT+0xa4>
 8005504:	68fb      	ldr	r3, [r7, #12]
 8005506:	2200      	movs	r2, #0
 8005508:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c

  huart->ErrorCode = HAL_UART_ERROR_NONE;
 800550c:	68fb      	ldr	r3, [r7, #12]
 800550e:	2200      	movs	r2, #0
 8005510:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
  huart->RxState = HAL_UART_STATE_BUSY_RX;
 8005514:	68fb      	ldr	r3, [r7, #12]
 8005516:	2222      	movs	r2, #34	@ 0x22
 8005518:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80

  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800551c:	68fb      	ldr	r3, [r7, #12]
 800551e:	681b      	ldr	r3, [r3, #0]
 8005520:	3308      	adds	r3, #8
 8005522:	63fb      	str	r3, [r7, #60]	@ 0x3c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005524:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8005526:	e853 3f00 	ldrex	r3, [r3]
 800552a:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 800552c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800552e:	f043 0301 	orr.w	r3, r3, #1
 8005532:	657b      	str	r3, [r7, #84]	@ 0x54
 8005534:	68fb      	ldr	r3, [r7, #12]
 8005536:	681b      	ldr	r3, [r3, #0]
 8005538:	3308      	adds	r3, #8
 800553a:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
 800553c:	64ba      	str	r2, [r7, #72]	@ 0x48
 800553e:	647b      	str	r3, [r7, #68]	@ 0x44
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005540:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 8005542:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 8005544:	e841 2300 	strex	r3, r2, [r1]
 8005548:	643b      	str	r3, [r7, #64]	@ 0x40
   return(result);
 800554a:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 800554c:	2b00      	cmp	r3, #0
 800554e:	d1e5      	bne.n	800551c <UART_Start_Receive_IT+0xb4>
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
    }
  }
#else
  /* Set the Rx ISR function pointer according to the data word length */
  if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8005550:	68fb      	ldr	r3, [r7, #12]
 8005552:	689b      	ldr	r3, [r3, #8]
 8005554:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8005558:	d107      	bne.n	800556a <UART_Start_Receive_IT+0x102>
 800555a:	68fb      	ldr	r3, [r7, #12]
 800555c:	691b      	ldr	r3, [r3, #16]
 800555e:	2b00      	cmp	r3, #0
 8005560:	d103      	bne.n	800556a <UART_Start_Receive_IT+0x102>
  {
    huart->RxISR = UART_RxISR_16BIT;
 8005562:	68fb      	ldr	r3, [r7, #12]
 8005564:	4a21      	ldr	r2, [pc, #132]	@ (80055ec <UART_Start_Receive_IT+0x184>)
 8005566:	669a      	str	r2, [r3, #104]	@ 0x68
 8005568:	e002      	b.n	8005570 <UART_Start_Receive_IT+0x108>
  }
  else
  {
    huart->RxISR = UART_RxISR_8BIT;
 800556a:	68fb      	ldr	r3, [r7, #12]
 800556c:	4a20      	ldr	r2, [pc, #128]	@ (80055f0 <UART_Start_Receive_IT+0x188>)
 800556e:	669a      	str	r2, [r3, #104]	@ 0x68
  }

  /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
  if (huart->Init.Parity != UART_PARITY_NONE)
 8005570:	68fb      	ldr	r3, [r7, #12]
 8005572:	691b      	ldr	r3, [r3, #16]
 8005574:	2b00      	cmp	r3, #0
 8005576:	d019      	beq.n	80055ac <UART_Start_Receive_IT+0x144>
  {
    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
 8005578:	68fb      	ldr	r3, [r7, #12]
 800557a:	681b      	ldr	r3, [r3, #0]
 800557c:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800557e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8005580:	e853 3f00 	ldrex	r3, [r3]
 8005584:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 8005586:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8005588:	f443 7390 	orr.w	r3, r3, #288	@ 0x120
 800558c:	64fb      	str	r3, [r7, #76]	@ 0x4c
 800558e:	68fb      	ldr	r3, [r7, #12]
 8005590:	681b      	ldr	r3, [r3, #0]
 8005592:	461a      	mov	r2, r3
 8005594:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8005596:	637b      	str	r3, [r7, #52]	@ 0x34
 8005598:	633a      	str	r2, [r7, #48]	@ 0x30
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800559a:	6b39      	ldr	r1, [r7, #48]	@ 0x30
 800559c:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 800559e:	e841 2300 	strex	r3, r2, [r1]
 80055a2:	62fb      	str	r3, [r7, #44]	@ 0x2c
   return(result);
 80055a4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80055a6:	2b00      	cmp	r3, #0
 80055a8:	d1e6      	bne.n	8005578 <UART_Start_Receive_IT+0x110>
 80055aa:	e018      	b.n	80055de <UART_Start_Receive_IT+0x176>
  }
  else
  {
    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
 80055ac:	68fb      	ldr	r3, [r7, #12]
 80055ae:	681b      	ldr	r3, [r3, #0]
 80055b0:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80055b2:	697b      	ldr	r3, [r7, #20]
 80055b4:	e853 3f00 	ldrex	r3, [r3]
 80055b8:	613b      	str	r3, [r7, #16]
   return(result);
 80055ba:	693b      	ldr	r3, [r7, #16]
 80055bc:	f043 0320 	orr.w	r3, r3, #32
 80055c0:	653b      	str	r3, [r7, #80]	@ 0x50
 80055c2:	68fb      	ldr	r3, [r7, #12]
 80055c4:	681b      	ldr	r3, [r3, #0]
 80055c6:	461a      	mov	r2, r3
 80055c8:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 80055ca:	623b      	str	r3, [r7, #32]
 80055cc:	61fa      	str	r2, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80055ce:	69f9      	ldr	r1, [r7, #28]
 80055d0:	6a3a      	ldr	r2, [r7, #32]
 80055d2:	e841 2300 	strex	r3, r2, [r1]
 80055d6:	61bb      	str	r3, [r7, #24]
   return(result);
 80055d8:	69bb      	ldr	r3, [r7, #24]
 80055da:	2b00      	cmp	r3, #0
 80055dc:	d1e6      	bne.n	80055ac <UART_Start_Receive_IT+0x144>
  }
#endif /* USART_CR1_FIFOEN */
  return HAL_OK;
 80055de:	2300      	movs	r3, #0
}
 80055e0:	4618      	mov	r0, r3
 80055e2:	375c      	adds	r7, #92	@ 0x5c
 80055e4:	46bd      	mov	sp, r7
 80055e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80055ea:	4770      	bx	lr
 80055ec:	08005a71 	.word	0x08005a71
 80055f0:	080058b5 	.word	0x080058b5

080055f4 <UART_EndRxTransfer>:
  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
  * @param  huart UART handle.
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
 80055f4:	b480      	push	{r7}
 80055f6:	b095      	sub	sp, #84	@ 0x54
 80055f8:	af00      	add	r7, sp, #0
 80055fa:	6078      	str	r0, [r7, #4]
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 80055fc:	687b      	ldr	r3, [r7, #4]
 80055fe:	681b      	ldr	r3, [r3, #0]
 8005600:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005602:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8005604:	e853 3f00 	ldrex	r3, [r3]
 8005608:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 800560a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800560c:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8005610:	64fb      	str	r3, [r7, #76]	@ 0x4c
 8005612:	687b      	ldr	r3, [r7, #4]
 8005614:	681b      	ldr	r3, [r3, #0]
 8005616:	461a      	mov	r2, r3
 8005618:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800561a:	643b      	str	r3, [r7, #64]	@ 0x40
 800561c:	63fa      	str	r2, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800561e:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 8005620:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 8005622:	e841 2300 	strex	r3, r2, [r1]
 8005626:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 8005628:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800562a:	2b00      	cmp	r3, #0
 800562c:	d1e6      	bne.n	80055fc <UART_EndRxTransfer+0x8>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800562e:	687b      	ldr	r3, [r7, #4]
 8005630:	681b      	ldr	r3, [r3, #0]
 8005632:	3308      	adds	r3, #8
 8005634:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005636:	6a3b      	ldr	r3, [r7, #32]
 8005638:	e853 3f00 	ldrex	r3, [r3]
 800563c:	61fb      	str	r3, [r7, #28]
   return(result);
 800563e:	69fb      	ldr	r3, [r7, #28]
 8005640:	f023 0301 	bic.w	r3, r3, #1
 8005644:	64bb      	str	r3, [r7, #72]	@ 0x48
 8005646:	687b      	ldr	r3, [r7, #4]
 8005648:	681b      	ldr	r3, [r3, #0]
 800564a:	3308      	adds	r3, #8
 800564c:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 800564e:	62fa      	str	r2, [r7, #44]	@ 0x2c
 8005650:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005652:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8005654:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8005656:	e841 2300 	strex	r3, r2, [r1]
 800565a:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800565c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800565e:	2b00      	cmp	r3, #0
 8005660:	d1e5      	bne.n	800562e <UART_EndRxTransfer+0x3a>
#endif /* USART_CR1_FIFOEN */

  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8005662:	687b      	ldr	r3, [r7, #4]
 8005664:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8005666:	2b01      	cmp	r3, #1
 8005668:	d118      	bne.n	800569c <UART_EndRxTransfer+0xa8>
  {
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800566a:	687b      	ldr	r3, [r7, #4]
 800566c:	681b      	ldr	r3, [r3, #0]
 800566e:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005670:	68fb      	ldr	r3, [r7, #12]
 8005672:	e853 3f00 	ldrex	r3, [r3]
 8005676:	60bb      	str	r3, [r7, #8]
   return(result);
 8005678:	68bb      	ldr	r3, [r7, #8]
 800567a:	f023 0310 	bic.w	r3, r3, #16
 800567e:	647b      	str	r3, [r7, #68]	@ 0x44
 8005680:	687b      	ldr	r3, [r7, #4]
 8005682:	681b      	ldr	r3, [r3, #0]
 8005684:	461a      	mov	r2, r3
 8005686:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8005688:	61bb      	str	r3, [r7, #24]
 800568a:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800568c:	6979      	ldr	r1, [r7, #20]
 800568e:	69ba      	ldr	r2, [r7, #24]
 8005690:	e841 2300 	strex	r3, r2, [r1]
 8005694:	613b      	str	r3, [r7, #16]
   return(result);
 8005696:	693b      	ldr	r3, [r7, #16]
 8005698:	2b00      	cmp	r3, #0
 800569a:	d1e6      	bne.n	800566a <UART_EndRxTransfer+0x76>
  }

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 800569c:	687b      	ldr	r3, [r7, #4]
 800569e:	2220      	movs	r2, #32
 80056a0:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80056a4:	687b      	ldr	r3, [r7, #4]
 80056a6:	2200      	movs	r2, #0
 80056a8:	661a      	str	r2, [r3, #96]	@ 0x60

  /* Reset RxIsr function pointer */
  huart->RxISR = NULL;
 80056aa:	687b      	ldr	r3, [r7, #4]
 80056ac:	2200      	movs	r2, #0
 80056ae:	669a      	str	r2, [r3, #104]	@ 0x68
}
 80056b0:	bf00      	nop
 80056b2:	3754      	adds	r7, #84	@ 0x54
 80056b4:	46bd      	mov	sp, r7
 80056b6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80056ba:	4770      	bx	lr

080056bc <UART_DMAAbortOnError>:
  *         (To be called at end of DMA Abort procedure following error occurrence).
  * @param  hdma DMA handle.
  * @retval None
  */
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
 80056bc:	b580      	push	{r7, lr}
 80056be:	b084      	sub	sp, #16
 80056c0:	af00      	add	r7, sp, #0
 80056c2:	6078      	str	r0, [r7, #4]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
 80056c4:	687b      	ldr	r3, [r7, #4]
 80056c6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 80056c8:	60fb      	str	r3, [r7, #12]
  huart->RxXferCount = 0U;
 80056ca:	68fb      	ldr	r3, [r7, #12]
 80056cc:	2200      	movs	r2, #0
 80056ce:	f8a3 205a 	strh.w	r2, [r3, #90]	@ 0x5a
  huart->TxXferCount = 0U;
 80056d2:	68fb      	ldr	r3, [r7, #12]
 80056d4:	2200      	movs	r2, #0
 80056d6:	f8a3 2052 	strh.w	r2, [r3, #82]	@ 0x52
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered error callback*/
  huart->ErrorCallback(huart);
#else
  /*Call legacy weak error callback*/
  HAL_UART_ErrorCallback(huart);
 80056da:	68f8      	ldr	r0, [r7, #12]
 80056dc:	f7ff fa3e 	bl	8004b5c <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 80056e0:	bf00      	nop
 80056e2:	3710      	adds	r7, #16
 80056e4:	46bd      	mov	sp, r7
 80056e6:	bd80      	pop	{r7, pc}

080056e8 <UART_TxISR_8BIT>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
{
 80056e8:	b480      	push	{r7}
 80056ea:	b08f      	sub	sp, #60	@ 0x3c
 80056ec:	af00      	add	r7, sp, #0
 80056ee:	6078      	str	r0, [r7, #4]
  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 80056f0:	687b      	ldr	r3, [r7, #4]
 80056f2:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 80056f4:	2b21      	cmp	r3, #33	@ 0x21
 80056f6:	d14c      	bne.n	8005792 <UART_TxISR_8BIT+0xaa>
  {
    if (huart->TxXferCount == 0U)
 80056f8:	687b      	ldr	r3, [r7, #4]
 80056fa:	f8b3 3052 	ldrh.w	r3, [r3, #82]	@ 0x52
 80056fe:	b29b      	uxth	r3, r3
 8005700:	2b00      	cmp	r3, #0
 8005702:	d132      	bne.n	800576a <UART_TxISR_8BIT+0x82>
    {
      /* Disable the UART Transmit Data Register Empty Interrupt */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
 8005704:	687b      	ldr	r3, [r7, #4]
 8005706:	681b      	ldr	r3, [r3, #0]
 8005708:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800570a:	6a3b      	ldr	r3, [r7, #32]
 800570c:	e853 3f00 	ldrex	r3, [r3]
 8005710:	61fb      	str	r3, [r7, #28]
   return(result);
 8005712:	69fb      	ldr	r3, [r7, #28]
 8005714:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 8005718:	637b      	str	r3, [r7, #52]	@ 0x34
 800571a:	687b      	ldr	r3, [r7, #4]
 800571c:	681b      	ldr	r3, [r3, #0]
 800571e:	461a      	mov	r2, r3
 8005720:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8005722:	62fb      	str	r3, [r7, #44]	@ 0x2c
 8005724:	62ba      	str	r2, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005726:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8005728:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 800572a:	e841 2300 	strex	r3, r2, [r1]
 800572e:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 8005730:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8005732:	2b00      	cmp	r3, #0
 8005734:	d1e6      	bne.n	8005704 <UART_TxISR_8BIT+0x1c>
#endif /* USART_CR1_FIFOEN */

      /* Enable the UART Transmit Complete Interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 8005736:	687b      	ldr	r3, [r7, #4]
 8005738:	681b      	ldr	r3, [r3, #0]
 800573a:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800573c:	68fb      	ldr	r3, [r7, #12]
 800573e:	e853 3f00 	ldrex	r3, [r3]
 8005742:	60bb      	str	r3, [r7, #8]
   return(result);
 8005744:	68bb      	ldr	r3, [r7, #8]
 8005746:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 800574a:	633b      	str	r3, [r7, #48]	@ 0x30
 800574c:	687b      	ldr	r3, [r7, #4]
 800574e:	681b      	ldr	r3, [r3, #0]
 8005750:	461a      	mov	r2, r3
 8005752:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8005754:	61bb      	str	r3, [r7, #24]
 8005756:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005758:	6979      	ldr	r1, [r7, #20]
 800575a:	69ba      	ldr	r2, [r7, #24]
 800575c:	e841 2300 	strex	r3, r2, [r1]
 8005760:	613b      	str	r3, [r7, #16]
   return(result);
 8005762:	693b      	ldr	r3, [r7, #16]
 8005764:	2b00      	cmp	r3, #0
 8005766:	d1e6      	bne.n	8005736 <UART_TxISR_8BIT+0x4e>
      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
      huart->pTxBuffPtr++;
      huart->TxXferCount--;
    }
  }
}
 8005768:	e013      	b.n	8005792 <UART_TxISR_8BIT+0xaa>
      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
 800576a:	687b      	ldr	r3, [r7, #4]
 800576c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800576e:	781a      	ldrb	r2, [r3, #0]
 8005770:	687b      	ldr	r3, [r7, #4]
 8005772:	681b      	ldr	r3, [r3, #0]
 8005774:	851a      	strh	r2, [r3, #40]	@ 0x28
      huart->pTxBuffPtr++;
 8005776:	687b      	ldr	r3, [r7, #4]
 8005778:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800577a:	1c5a      	adds	r2, r3, #1
 800577c:	687b      	ldr	r3, [r7, #4]
 800577e:	64da      	str	r2, [r3, #76]	@ 0x4c
      huart->TxXferCount--;
 8005780:	687b      	ldr	r3, [r7, #4]
 8005782:	f8b3 3052 	ldrh.w	r3, [r3, #82]	@ 0x52
 8005786:	b29b      	uxth	r3, r3
 8005788:	3b01      	subs	r3, #1
 800578a:	b29a      	uxth	r2, r3
 800578c:	687b      	ldr	r3, [r7, #4]
 800578e:	f8a3 2052 	strh.w	r2, [r3, #82]	@ 0x52
}
 8005792:	bf00      	nop
 8005794:	373c      	adds	r7, #60	@ 0x3c
 8005796:	46bd      	mov	sp, r7
 8005798:	f85d 7b04 	ldr.w	r7, [sp], #4
 800579c:	4770      	bx	lr

0800579e <UART_TxISR_16BIT>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
 800579e:	b480      	push	{r7}
 80057a0:	b091      	sub	sp, #68	@ 0x44
 80057a2:	af00      	add	r7, sp, #0
 80057a4:	6078      	str	r0, [r7, #4]
  const uint16_t *tmp;

  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 80057a6:	687b      	ldr	r3, [r7, #4]
 80057a8:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 80057aa:	2b21      	cmp	r3, #33	@ 0x21
 80057ac:	d151      	bne.n	8005852 <UART_TxISR_16BIT+0xb4>
  {
    if (huart->TxXferCount == 0U)
 80057ae:	687b      	ldr	r3, [r7, #4]
 80057b0:	f8b3 3052 	ldrh.w	r3, [r3, #82]	@ 0x52
 80057b4:	b29b      	uxth	r3, r3
 80057b6:	2b00      	cmp	r3, #0
 80057b8:	d132      	bne.n	8005820 <UART_TxISR_16BIT+0x82>
    {
      /* Disable the UART Transmit Data Register Empty Interrupt */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
 80057ba:	687b      	ldr	r3, [r7, #4]
 80057bc:	681b      	ldr	r3, [r3, #0]
 80057be:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80057c0:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80057c2:	e853 3f00 	ldrex	r3, [r3]
 80057c6:	623b      	str	r3, [r7, #32]
   return(result);
 80057c8:	6a3b      	ldr	r3, [r7, #32]
 80057ca:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 80057ce:	63bb      	str	r3, [r7, #56]	@ 0x38
 80057d0:	687b      	ldr	r3, [r7, #4]
 80057d2:	681b      	ldr	r3, [r3, #0]
 80057d4:	461a      	mov	r2, r3
 80057d6:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80057d8:	633b      	str	r3, [r7, #48]	@ 0x30
 80057da:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80057dc:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 80057de:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80057e0:	e841 2300 	strex	r3, r2, [r1]
 80057e4:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 80057e6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80057e8:	2b00      	cmp	r3, #0
 80057ea:	d1e6      	bne.n	80057ba <UART_TxISR_16BIT+0x1c>
#endif /* USART_CR1_FIFOEN */

      /* Enable the UART Transmit Complete Interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 80057ec:	687b      	ldr	r3, [r7, #4]
 80057ee:	681b      	ldr	r3, [r3, #0]
 80057f0:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80057f2:	693b      	ldr	r3, [r7, #16]
 80057f4:	e853 3f00 	ldrex	r3, [r3]
 80057f8:	60fb      	str	r3, [r7, #12]
   return(result);
 80057fa:	68fb      	ldr	r3, [r7, #12]
 80057fc:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8005800:	637b      	str	r3, [r7, #52]	@ 0x34
 8005802:	687b      	ldr	r3, [r7, #4]
 8005804:	681b      	ldr	r3, [r3, #0]
 8005806:	461a      	mov	r2, r3
 8005808:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800580a:	61fb      	str	r3, [r7, #28]
 800580c:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800580e:	69b9      	ldr	r1, [r7, #24]
 8005810:	69fa      	ldr	r2, [r7, #28]
 8005812:	e841 2300 	strex	r3, r2, [r1]
 8005816:	617b      	str	r3, [r7, #20]
   return(result);
 8005818:	697b      	ldr	r3, [r7, #20]
 800581a:	2b00      	cmp	r3, #0
 800581c:	d1e6      	bne.n	80057ec <UART_TxISR_16BIT+0x4e>
      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
      huart->pTxBuffPtr += 2U;
      huart->TxXferCount--;
    }
  }
}
 800581e:	e018      	b.n	8005852 <UART_TxISR_16BIT+0xb4>
      tmp = (const uint16_t *) huart->pTxBuffPtr;
 8005820:	687b      	ldr	r3, [r7, #4]
 8005822:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8005824:	63fb      	str	r3, [r7, #60]	@ 0x3c
      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
 8005826:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8005828:	881a      	ldrh	r2, [r3, #0]
 800582a:	687b      	ldr	r3, [r7, #4]
 800582c:	681b      	ldr	r3, [r3, #0]
 800582e:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8005832:	b292      	uxth	r2, r2
 8005834:	851a      	strh	r2, [r3, #40]	@ 0x28
      huart->pTxBuffPtr += 2U;
 8005836:	687b      	ldr	r3, [r7, #4]
 8005838:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800583a:	1c9a      	adds	r2, r3, #2
 800583c:	687b      	ldr	r3, [r7, #4]
 800583e:	64da      	str	r2, [r3, #76]	@ 0x4c
      huart->TxXferCount--;
 8005840:	687b      	ldr	r3, [r7, #4]
 8005842:	f8b3 3052 	ldrh.w	r3, [r3, #82]	@ 0x52
 8005846:	b29b      	uxth	r3, r3
 8005848:	3b01      	subs	r3, #1
 800584a:	b29a      	uxth	r2, r3
 800584c:	687b      	ldr	r3, [r7, #4]
 800584e:	f8a3 2052 	strh.w	r2, [r3, #82]	@ 0x52
}
 8005852:	bf00      	nop
 8005854:	3744      	adds	r7, #68	@ 0x44
 8005856:	46bd      	mov	sp, r7
 8005858:	f85d 7b04 	ldr.w	r7, [sp], #4
 800585c:	4770      	bx	lr

0800585e <UART_EndTransmit_IT>:
  * @param  huart pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
 800585e:	b580      	push	{r7, lr}
 8005860:	b088      	sub	sp, #32
 8005862:	af00      	add	r7, sp, #0
 8005864:	6078      	str	r0, [r7, #4]
  /* Disable the UART Transmit Complete Interrupt */
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 8005866:	687b      	ldr	r3, [r7, #4]
 8005868:	681b      	ldr	r3, [r3, #0]
 800586a:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800586c:	68fb      	ldr	r3, [r7, #12]
 800586e:	e853 3f00 	ldrex	r3, [r3]
 8005872:	60bb      	str	r3, [r7, #8]
   return(result);
 8005874:	68bb      	ldr	r3, [r7, #8]
 8005876:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 800587a:	61fb      	str	r3, [r7, #28]
 800587c:	687b      	ldr	r3, [r7, #4]
 800587e:	681b      	ldr	r3, [r3, #0]
 8005880:	461a      	mov	r2, r3
 8005882:	69fb      	ldr	r3, [r7, #28]
 8005884:	61bb      	str	r3, [r7, #24]
 8005886:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005888:	6979      	ldr	r1, [r7, #20]
 800588a:	69ba      	ldr	r2, [r7, #24]
 800588c:	e841 2300 	strex	r3, r2, [r1]
 8005890:	613b      	str	r3, [r7, #16]
   return(result);
 8005892:	693b      	ldr	r3, [r7, #16]
 8005894:	2b00      	cmp	r3, #0
 8005896:	d1e6      	bne.n	8005866 <UART_EndTransmit_IT+0x8>

  /* Tx process is ended, restore huart->gState to Ready */
  huart->gState = HAL_UART_STATE_READY;
 8005898:	687b      	ldr	r3, [r7, #4]
 800589a:	2220      	movs	r2, #32
 800589c:	67da      	str	r2, [r3, #124]	@ 0x7c

  /* Cleat TxISR function pointer */
  huart->TxISR = NULL;
 800589e:	687b      	ldr	r3, [r7, #4]
 80058a0:	2200      	movs	r2, #0
 80058a2:	66da      	str	r2, [r3, #108]	@ 0x6c
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered Tx complete callback*/
  huart->TxCpltCallback(huart);
#else
  /*Call legacy weak Tx complete callback*/
  HAL_UART_TxCpltCallback(huart);
 80058a4:	6878      	ldr	r0, [r7, #4]
 80058a6:	f7fb fa93 	bl	8000dd0 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 80058aa:	bf00      	nop
 80058ac:	3720      	adds	r7, #32
 80058ae:	46bd      	mov	sp, r7
 80058b0:	bd80      	pop	{r7, pc}
	...

080058b4 <UART_RxISR_8BIT>:
  * @brief RX interrupt handler for 7 or 8 bits data word length .
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
 80058b4:	b580      	push	{r7, lr}
 80058b6:	b09c      	sub	sp, #112	@ 0x70
 80058b8:	af00      	add	r7, sp, #0
 80058ba:	6078      	str	r0, [r7, #4]
  uint16_t uhMask = huart->Mask;
 80058bc:	687b      	ldr	r3, [r7, #4]
 80058be:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 80058c2:	f8a7 306e 	strh.w	r3, [r7, #110]	@ 0x6e
  uint16_t  uhdata;

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 80058c6:	687b      	ldr	r3, [r7, #4]
 80058c8:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 80058cc:	2b22      	cmp	r3, #34	@ 0x22
 80058ce:	f040 80be 	bne.w	8005a4e <UART_RxISR_8BIT+0x19a>
  {
    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 80058d2:	687b      	ldr	r3, [r7, #4]
 80058d4:	681b      	ldr	r3, [r3, #0]
 80058d6:	8c9b      	ldrh	r3, [r3, #36]	@ 0x24
 80058d8:	f8a7 306c 	strh.w	r3, [r7, #108]	@ 0x6c
    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
 80058dc:	f8b7 306c 	ldrh.w	r3, [r7, #108]	@ 0x6c
 80058e0:	b2d9      	uxtb	r1, r3
 80058e2:	f8b7 306e 	ldrh.w	r3, [r7, #110]	@ 0x6e
 80058e6:	b2da      	uxtb	r2, r3
 80058e8:	687b      	ldr	r3, [r7, #4]
 80058ea:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80058ec:	400a      	ands	r2, r1
 80058ee:	b2d2      	uxtb	r2, r2
 80058f0:	701a      	strb	r2, [r3, #0]
    huart->pRxBuffPtr++;
 80058f2:	687b      	ldr	r3, [r7, #4]
 80058f4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80058f6:	1c5a      	adds	r2, r3, #1
 80058f8:	687b      	ldr	r3, [r7, #4]
 80058fa:	655a      	str	r2, [r3, #84]	@ 0x54
    huart->RxXferCount--;
 80058fc:	687b      	ldr	r3, [r7, #4]
 80058fe:	f8b3 305a 	ldrh.w	r3, [r3, #90]	@ 0x5a
 8005902:	b29b      	uxth	r3, r3
 8005904:	3b01      	subs	r3, #1
 8005906:	b29a      	uxth	r2, r3
 8005908:	687b      	ldr	r3, [r7, #4]
 800590a:	f8a3 205a 	strh.w	r2, [r3, #90]	@ 0x5a

    if (huart->RxXferCount == 0U)
 800590e:	687b      	ldr	r3, [r7, #4]
 8005910:	f8b3 305a 	ldrh.w	r3, [r3, #90]	@ 0x5a
 8005914:	b29b      	uxth	r3, r3
 8005916:	2b00      	cmp	r3, #0
 8005918:	f040 80a3 	bne.w	8005a62 <UART_RxISR_8BIT+0x1ae>
    {
      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 800591c:	687b      	ldr	r3, [r7, #4]
 800591e:	681b      	ldr	r3, [r3, #0]
 8005920:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005922:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8005924:	e853 3f00 	ldrex	r3, [r3]
 8005928:	64bb      	str	r3, [r7, #72]	@ 0x48
   return(result);
 800592a:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 800592c:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8005930:	66bb      	str	r3, [r7, #104]	@ 0x68
 8005932:	687b      	ldr	r3, [r7, #4]
 8005934:	681b      	ldr	r3, [r3, #0]
 8005936:	461a      	mov	r2, r3
 8005938:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 800593a:	65bb      	str	r3, [r7, #88]	@ 0x58
 800593c:	657a      	str	r2, [r7, #84]	@ 0x54
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800593e:	6d79      	ldr	r1, [r7, #84]	@ 0x54
 8005940:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 8005942:	e841 2300 	strex	r3, r2, [r1]
 8005946:	653b      	str	r3, [r7, #80]	@ 0x50
   return(result);
 8005948:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 800594a:	2b00      	cmp	r3, #0
 800594c:	d1e6      	bne.n	800591c <UART_RxISR_8BIT+0x68>
#endif /* USART_CR1_FIFOEN */

      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800594e:	687b      	ldr	r3, [r7, #4]
 8005950:	681b      	ldr	r3, [r3, #0]
 8005952:	3308      	adds	r3, #8
 8005954:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005956:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005958:	e853 3f00 	ldrex	r3, [r3]
 800595c:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 800595e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8005960:	f023 0301 	bic.w	r3, r3, #1
 8005964:	667b      	str	r3, [r7, #100]	@ 0x64
 8005966:	687b      	ldr	r3, [r7, #4]
 8005968:	681b      	ldr	r3, [r3, #0]
 800596a:	3308      	adds	r3, #8
 800596c:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
 800596e:	647a      	str	r2, [r7, #68]	@ 0x44
 8005970:	643b      	str	r3, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005972:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 8005974:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 8005976:	e841 2300 	strex	r3, r2, [r1]
 800597a:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 800597c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800597e:	2b00      	cmp	r3, #0
 8005980:	d1e5      	bne.n	800594e <UART_RxISR_8BIT+0x9a>

      /* Rx process is completed, restore huart->RxState to Ready */
      huart->RxState = HAL_UART_STATE_READY;
 8005982:	687b      	ldr	r3, [r7, #4]
 8005984:	2220      	movs	r2, #32
 8005986:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80

      /* Clear RxISR function pointer */
      huart->RxISR = NULL;
 800598a:	687b      	ldr	r3, [r7, #4]
 800598c:	2200      	movs	r2, #0
 800598e:	669a      	str	r2, [r3, #104]	@ 0x68

      /* Initialize type of RxEvent to Transfer Complete */
      huart->RxEventType = HAL_UART_RXEVENT_TC;
 8005990:	687b      	ldr	r3, [r7, #4]
 8005992:	2200      	movs	r2, #0
 8005994:	665a      	str	r2, [r3, #100]	@ 0x64

      if (!(IS_LPUART_INSTANCE(huart->Instance)))
 8005996:	687b      	ldr	r3, [r7, #4]
 8005998:	681b      	ldr	r3, [r3, #0]
 800599a:	4a34      	ldr	r2, [pc, #208]	@ (8005a6c <UART_RxISR_8BIT+0x1b8>)
 800599c:	4293      	cmp	r3, r2
 800599e:	d01f      	beq.n	80059e0 <UART_RxISR_8BIT+0x12c>
      {
        /* Check that USART RTOEN bit is set */
        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 80059a0:	687b      	ldr	r3, [r7, #4]
 80059a2:	681b      	ldr	r3, [r3, #0]
 80059a4:	685b      	ldr	r3, [r3, #4]
 80059a6:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 80059aa:	2b00      	cmp	r3, #0
 80059ac:	d018      	beq.n	80059e0 <UART_RxISR_8BIT+0x12c>
        {
          /* Enable the UART Receiver Timeout Interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 80059ae:	687b      	ldr	r3, [r7, #4]
 80059b0:	681b      	ldr	r3, [r3, #0]
 80059b2:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80059b4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80059b6:	e853 3f00 	ldrex	r3, [r3]
 80059ba:	623b      	str	r3, [r7, #32]
   return(result);
 80059bc:	6a3b      	ldr	r3, [r7, #32]
 80059be:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 80059c2:	663b      	str	r3, [r7, #96]	@ 0x60
 80059c4:	687b      	ldr	r3, [r7, #4]
 80059c6:	681b      	ldr	r3, [r3, #0]
 80059c8:	461a      	mov	r2, r3
 80059ca:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 80059cc:	633b      	str	r3, [r7, #48]	@ 0x30
 80059ce:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80059d0:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 80059d2:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80059d4:	e841 2300 	strex	r3, r2, [r1]
 80059d8:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 80059da:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80059dc:	2b00      	cmp	r3, #0
 80059de:	d1e6      	bne.n	80059ae <UART_RxISR_8BIT+0xfa>
        }
      }

      /* Check current reception Mode :
         If Reception till IDLE event has been selected : */
      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 80059e0:	687b      	ldr	r3, [r7, #4]
 80059e2:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80059e4:	2b01      	cmp	r3, #1
 80059e6:	d12e      	bne.n	8005a46 <UART_RxISR_8BIT+0x192>
      {
        /* Set reception type to Standard */
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80059e8:	687b      	ldr	r3, [r7, #4]
 80059ea:	2200      	movs	r2, #0
 80059ec:	661a      	str	r2, [r3, #96]	@ 0x60

        /* Disable IDLE interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 80059ee:	687b      	ldr	r3, [r7, #4]
 80059f0:	681b      	ldr	r3, [r3, #0]
 80059f2:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80059f4:	693b      	ldr	r3, [r7, #16]
 80059f6:	e853 3f00 	ldrex	r3, [r3]
 80059fa:	60fb      	str	r3, [r7, #12]
   return(result);
 80059fc:	68fb      	ldr	r3, [r7, #12]
 80059fe:	f023 0310 	bic.w	r3, r3, #16
 8005a02:	65fb      	str	r3, [r7, #92]	@ 0x5c
 8005a04:	687b      	ldr	r3, [r7, #4]
 8005a06:	681b      	ldr	r3, [r3, #0]
 8005a08:	461a      	mov	r2, r3
 8005a0a:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8005a0c:	61fb      	str	r3, [r7, #28]
 8005a0e:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005a10:	69b9      	ldr	r1, [r7, #24]
 8005a12:	69fa      	ldr	r2, [r7, #28]
 8005a14:	e841 2300 	strex	r3, r2, [r1]
 8005a18:	617b      	str	r3, [r7, #20]
   return(result);
 8005a1a:	697b      	ldr	r3, [r7, #20]
 8005a1c:	2b00      	cmp	r3, #0
 8005a1e:	d1e6      	bne.n	80059ee <UART_RxISR_8BIT+0x13a>

        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 8005a20:	687b      	ldr	r3, [r7, #4]
 8005a22:	681b      	ldr	r3, [r3, #0]
 8005a24:	69db      	ldr	r3, [r3, #28]
 8005a26:	f003 0310 	and.w	r3, r3, #16
 8005a2a:	2b10      	cmp	r3, #16
 8005a2c:	d103      	bne.n	8005a36 <UART_RxISR_8BIT+0x182>
        {
          /* Clear IDLE Flag */
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 8005a2e:	687b      	ldr	r3, [r7, #4]
 8005a30:	681b      	ldr	r3, [r3, #0]
 8005a32:	2210      	movs	r2, #16
 8005a34:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, huart->RxXferSize);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 8005a36:	687b      	ldr	r3, [r7, #4]
 8005a38:	f8b3 3058 	ldrh.w	r3, [r3, #88]	@ 0x58
 8005a3c:	4619      	mov	r1, r3
 8005a3e:	6878      	ldr	r0, [r7, #4]
 8005a40:	f7ff f896 	bl	8004b70 <HAL_UARTEx_RxEventCallback>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 8005a44:	e00d      	b.n	8005a62 <UART_RxISR_8BIT+0x1ae>
        HAL_UART_RxCpltCallback(huart);
 8005a46:	6878      	ldr	r0, [r7, #4]
 8005a48:	f7fb f9e6 	bl	8000e18 <HAL_UART_RxCpltCallback>
}
 8005a4c:	e009      	b.n	8005a62 <UART_RxISR_8BIT+0x1ae>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 8005a4e:	687b      	ldr	r3, [r7, #4]
 8005a50:	681b      	ldr	r3, [r3, #0]
 8005a52:	8b1b      	ldrh	r3, [r3, #24]
 8005a54:	b29a      	uxth	r2, r3
 8005a56:	687b      	ldr	r3, [r7, #4]
 8005a58:	681b      	ldr	r3, [r3, #0]
 8005a5a:	f042 0208 	orr.w	r2, r2, #8
 8005a5e:	b292      	uxth	r2, r2
 8005a60:	831a      	strh	r2, [r3, #24]
}
 8005a62:	bf00      	nop
 8005a64:	3770      	adds	r7, #112	@ 0x70
 8005a66:	46bd      	mov	sp, r7
 8005a68:	bd80      	pop	{r7, pc}
 8005a6a:	bf00      	nop
 8005a6c:	40008000 	.word	0x40008000

08005a70 <UART_RxISR_16BIT>:
  *         interruptions have been enabled by HAL_UART_Receive_IT()
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
 8005a70:	b580      	push	{r7, lr}
 8005a72:	b09c      	sub	sp, #112	@ 0x70
 8005a74:	af00      	add	r7, sp, #0
 8005a76:	6078      	str	r0, [r7, #4]
  uint16_t *tmp;
  uint16_t uhMask = huart->Mask;
 8005a78:	687b      	ldr	r3, [r7, #4]
 8005a7a:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 8005a7e:	f8a7 306e 	strh.w	r3, [r7, #110]	@ 0x6e
  uint16_t  uhdata;

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 8005a82:	687b      	ldr	r3, [r7, #4]
 8005a84:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8005a88:	2b22      	cmp	r3, #34	@ 0x22
 8005a8a:	f040 80be 	bne.w	8005c0a <UART_RxISR_16BIT+0x19a>
  {
    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 8005a8e:	687b      	ldr	r3, [r7, #4]
 8005a90:	681b      	ldr	r3, [r3, #0]
 8005a92:	8c9b      	ldrh	r3, [r3, #36]	@ 0x24
 8005a94:	f8a7 306c 	strh.w	r3, [r7, #108]	@ 0x6c
    tmp = (uint16_t *) huart->pRxBuffPtr ;
 8005a98:	687b      	ldr	r3, [r7, #4]
 8005a9a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8005a9c:	66bb      	str	r3, [r7, #104]	@ 0x68
    *tmp = (uint16_t)(uhdata & uhMask);
 8005a9e:	f8b7 206c 	ldrh.w	r2, [r7, #108]	@ 0x6c
 8005aa2:	f8b7 306e 	ldrh.w	r3, [r7, #110]	@ 0x6e
 8005aa6:	4013      	ands	r3, r2
 8005aa8:	b29a      	uxth	r2, r3
 8005aaa:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8005aac:	801a      	strh	r2, [r3, #0]
    huart->pRxBuffPtr += 2U;
 8005aae:	687b      	ldr	r3, [r7, #4]
 8005ab0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8005ab2:	1c9a      	adds	r2, r3, #2
 8005ab4:	687b      	ldr	r3, [r7, #4]
 8005ab6:	655a      	str	r2, [r3, #84]	@ 0x54
    huart->RxXferCount--;
 8005ab8:	687b      	ldr	r3, [r7, #4]
 8005aba:	f8b3 305a 	ldrh.w	r3, [r3, #90]	@ 0x5a
 8005abe:	b29b      	uxth	r3, r3
 8005ac0:	3b01      	subs	r3, #1
 8005ac2:	b29a      	uxth	r2, r3
 8005ac4:	687b      	ldr	r3, [r7, #4]
 8005ac6:	f8a3 205a 	strh.w	r2, [r3, #90]	@ 0x5a

    if (huart->RxXferCount == 0U)
 8005aca:	687b      	ldr	r3, [r7, #4]
 8005acc:	f8b3 305a 	ldrh.w	r3, [r3, #90]	@ 0x5a
 8005ad0:	b29b      	uxth	r3, r3
 8005ad2:	2b00      	cmp	r3, #0
 8005ad4:	f040 80a3 	bne.w	8005c1e <UART_RxISR_16BIT+0x1ae>
    {
      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8005ad8:	687b      	ldr	r3, [r7, #4]
 8005ada:	681b      	ldr	r3, [r3, #0]
 8005adc:	64bb      	str	r3, [r7, #72]	@ 0x48
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005ade:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 8005ae0:	e853 3f00 	ldrex	r3, [r3]
 8005ae4:	647b      	str	r3, [r7, #68]	@ 0x44
   return(result);
 8005ae6:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8005ae8:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8005aec:	667b      	str	r3, [r7, #100]	@ 0x64
 8005aee:	687b      	ldr	r3, [r7, #4]
 8005af0:	681b      	ldr	r3, [r3, #0]
 8005af2:	461a      	mov	r2, r3
 8005af4:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 8005af6:	657b      	str	r3, [r7, #84]	@ 0x54
 8005af8:	653a      	str	r2, [r7, #80]	@ 0x50
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005afa:	6d39      	ldr	r1, [r7, #80]	@ 0x50
 8005afc:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
 8005afe:	e841 2300 	strex	r3, r2, [r1]
 8005b02:	64fb      	str	r3, [r7, #76]	@ 0x4c
   return(result);
 8005b04:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8005b06:	2b00      	cmp	r3, #0
 8005b08:	d1e6      	bne.n	8005ad8 <UART_RxISR_16BIT+0x68>
#endif /* USART_CR1_FIFOEN */

      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8005b0a:	687b      	ldr	r3, [r7, #4]
 8005b0c:	681b      	ldr	r3, [r3, #0]
 8005b0e:	3308      	adds	r3, #8
 8005b10:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005b12:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8005b14:	e853 3f00 	ldrex	r3, [r3]
 8005b18:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 8005b1a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8005b1c:	f023 0301 	bic.w	r3, r3, #1
 8005b20:	663b      	str	r3, [r7, #96]	@ 0x60
 8005b22:	687b      	ldr	r3, [r7, #4]
 8005b24:	681b      	ldr	r3, [r3, #0]
 8005b26:	3308      	adds	r3, #8
 8005b28:	6e3a      	ldr	r2, [r7, #96]	@ 0x60
 8005b2a:	643a      	str	r2, [r7, #64]	@ 0x40
 8005b2c:	63fb      	str	r3, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005b2e:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 8005b30:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 8005b32:	e841 2300 	strex	r3, r2, [r1]
 8005b36:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 8005b38:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8005b3a:	2b00      	cmp	r3, #0
 8005b3c:	d1e5      	bne.n	8005b0a <UART_RxISR_16BIT+0x9a>

      /* Rx process is completed, restore huart->RxState to Ready */
      huart->RxState = HAL_UART_STATE_READY;
 8005b3e:	687b      	ldr	r3, [r7, #4]
 8005b40:	2220      	movs	r2, #32
 8005b42:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80

      /* Clear RxISR function pointer */
      huart->RxISR = NULL;
 8005b46:	687b      	ldr	r3, [r7, #4]
 8005b48:	2200      	movs	r2, #0
 8005b4a:	669a      	str	r2, [r3, #104]	@ 0x68

      /* Initialize type of RxEvent to Transfer Complete */
      huart->RxEventType = HAL_UART_RXEVENT_TC;
 8005b4c:	687b      	ldr	r3, [r7, #4]
 8005b4e:	2200      	movs	r2, #0
 8005b50:	665a      	str	r2, [r3, #100]	@ 0x64

      if (!(IS_LPUART_INSTANCE(huart->Instance)))
 8005b52:	687b      	ldr	r3, [r7, #4]
 8005b54:	681b      	ldr	r3, [r3, #0]
 8005b56:	4a34      	ldr	r2, [pc, #208]	@ (8005c28 <UART_RxISR_16BIT+0x1b8>)
 8005b58:	4293      	cmp	r3, r2
 8005b5a:	d01f      	beq.n	8005b9c <UART_RxISR_16BIT+0x12c>
      {
        /* Check that USART RTOEN bit is set */
        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 8005b5c:	687b      	ldr	r3, [r7, #4]
 8005b5e:	681b      	ldr	r3, [r3, #0]
 8005b60:	685b      	ldr	r3, [r3, #4]
 8005b62:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 8005b66:	2b00      	cmp	r3, #0
 8005b68:	d018      	beq.n	8005b9c <UART_RxISR_16BIT+0x12c>
        {
          /* Enable the UART Receiver Timeout Interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 8005b6a:	687b      	ldr	r3, [r7, #4]
 8005b6c:	681b      	ldr	r3, [r3, #0]
 8005b6e:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005b70:	6a3b      	ldr	r3, [r7, #32]
 8005b72:	e853 3f00 	ldrex	r3, [r3]
 8005b76:	61fb      	str	r3, [r7, #28]
   return(result);
 8005b78:	69fb      	ldr	r3, [r7, #28]
 8005b7a:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 8005b7e:	65fb      	str	r3, [r7, #92]	@ 0x5c
 8005b80:	687b      	ldr	r3, [r7, #4]
 8005b82:	681b      	ldr	r3, [r3, #0]
 8005b84:	461a      	mov	r2, r3
 8005b86:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8005b88:	62fb      	str	r3, [r7, #44]	@ 0x2c
 8005b8a:	62ba      	str	r2, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005b8c:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8005b8e:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8005b90:	e841 2300 	strex	r3, r2, [r1]
 8005b94:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 8005b96:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8005b98:	2b00      	cmp	r3, #0
 8005b9a:	d1e6      	bne.n	8005b6a <UART_RxISR_16BIT+0xfa>
        }
      }

      /* Check current reception Mode :
         If Reception till IDLE event has been selected : */
      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8005b9c:	687b      	ldr	r3, [r7, #4]
 8005b9e:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8005ba0:	2b01      	cmp	r3, #1
 8005ba2:	d12e      	bne.n	8005c02 <UART_RxISR_16BIT+0x192>
      {
        /* Set reception type to Standard */
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8005ba4:	687b      	ldr	r3, [r7, #4]
 8005ba6:	2200      	movs	r2, #0
 8005ba8:	661a      	str	r2, [r3, #96]	@ 0x60

        /* Disable IDLE interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8005baa:	687b      	ldr	r3, [r7, #4]
 8005bac:	681b      	ldr	r3, [r3, #0]
 8005bae:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8005bb0:	68fb      	ldr	r3, [r7, #12]
 8005bb2:	e853 3f00 	ldrex	r3, [r3]
 8005bb6:	60bb      	str	r3, [r7, #8]
   return(result);
 8005bb8:	68bb      	ldr	r3, [r7, #8]
 8005bba:	f023 0310 	bic.w	r3, r3, #16
 8005bbe:	65bb      	str	r3, [r7, #88]	@ 0x58
 8005bc0:	687b      	ldr	r3, [r7, #4]
 8005bc2:	681b      	ldr	r3, [r3, #0]
 8005bc4:	461a      	mov	r2, r3
 8005bc6:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 8005bc8:	61bb      	str	r3, [r7, #24]
 8005bca:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8005bcc:	6979      	ldr	r1, [r7, #20]
 8005bce:	69ba      	ldr	r2, [r7, #24]
 8005bd0:	e841 2300 	strex	r3, r2, [r1]
 8005bd4:	613b      	str	r3, [r7, #16]
   return(result);
 8005bd6:	693b      	ldr	r3, [r7, #16]
 8005bd8:	2b00      	cmp	r3, #0
 8005bda:	d1e6      	bne.n	8005baa <UART_RxISR_16BIT+0x13a>

        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 8005bdc:	687b      	ldr	r3, [r7, #4]
 8005bde:	681b      	ldr	r3, [r3, #0]
 8005be0:	69db      	ldr	r3, [r3, #28]
 8005be2:	f003 0310 	and.w	r3, r3, #16
 8005be6:	2b10      	cmp	r3, #16
 8005be8:	d103      	bne.n	8005bf2 <UART_RxISR_16BIT+0x182>
        {
          /* Clear IDLE Flag */
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 8005bea:	687b      	ldr	r3, [r7, #4]
 8005bec:	681b      	ldr	r3, [r3, #0]
 8005bee:	2210      	movs	r2, #16
 8005bf0:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, huart->RxXferSize);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 8005bf2:	687b      	ldr	r3, [r7, #4]
 8005bf4:	f8b3 3058 	ldrh.w	r3, [r3, #88]	@ 0x58
 8005bf8:	4619      	mov	r1, r3
 8005bfa:	6878      	ldr	r0, [r7, #4]
 8005bfc:	f7fe ffb8 	bl	8004b70 <HAL_UARTEx_RxEventCallback>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 8005c00:	e00d      	b.n	8005c1e <UART_RxISR_16BIT+0x1ae>
        HAL_UART_RxCpltCallback(huart);
 8005c02:	6878      	ldr	r0, [r7, #4]
 8005c04:	f7fb f908 	bl	8000e18 <HAL_UART_RxCpltCallback>
}
 8005c08:	e009      	b.n	8005c1e <UART_RxISR_16BIT+0x1ae>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 8005c0a:	687b      	ldr	r3, [r7, #4]
 8005c0c:	681b      	ldr	r3, [r3, #0]
 8005c0e:	8b1b      	ldrh	r3, [r3, #24]
 8005c10:	b29a      	uxth	r2, r3
 8005c12:	687b      	ldr	r3, [r7, #4]
 8005c14:	681b      	ldr	r3, [r3, #0]
 8005c16:	f042 0208 	orr.w	r2, r2, #8
 8005c1a:	b292      	uxth	r2, r2
 8005c1c:	831a      	strh	r2, [r3, #24]
}
 8005c1e:	bf00      	nop
 8005c20:	3770      	adds	r7, #112	@ 0x70
 8005c22:	46bd      	mov	sp, r7
 8005c24:	bd80      	pop	{r7, pc}
 8005c26:	bf00      	nop
 8005c28:	40008000 	.word	0x40008000

08005c2c <HAL_UARTEx_WakeupCallback>:
  * @brief UART wakeup from Stop mode callback.
  * @param huart UART handle.
  * @retval None
  */
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
 8005c2c:	b480      	push	{r7}
 8005c2e:	b083      	sub	sp, #12
 8005c30:	af00      	add	r7, sp, #0
 8005c32:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
   */
}
 8005c34:	bf00      	nop
 8005c36:	370c      	adds	r7, #12
 8005c38:	46bd      	mov	sp, r7
 8005c3a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005c3e:	4770      	bx	lr

08005c40 <USB_CoreInit>:
  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains
  *         the configuration information for the specified USBx peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
 8005c40:	b084      	sub	sp, #16
 8005c42:	b580      	push	{r7, lr}
 8005c44:	b084      	sub	sp, #16
 8005c46:	af00      	add	r7, sp, #0
 8005c48:	6078      	str	r0, [r7, #4]
 8005c4a:	f107 001c 	add.w	r0, r7, #28
 8005c4e:	e880 000e 	stmia.w	r0, {r1, r2, r3}
  HAL_StatusTypeDef ret;

  /* Select FS Embedded PHY */
  USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
 8005c52:	687b      	ldr	r3, [r7, #4]
 8005c54:	68db      	ldr	r3, [r3, #12]
 8005c56:	f043 0240 	orr.w	r2, r3, #64	@ 0x40
 8005c5a:	687b      	ldr	r3, [r7, #4]
 8005c5c:	60da      	str	r2, [r3, #12]

  /* Reset after a PHY select */
  ret = USB_CoreReset(USBx);
 8005c5e:	6878      	ldr	r0, [r7, #4]
 8005c60:	f000 fa68 	bl	8006134 <USB_CoreReset>
 8005c64:	4603      	mov	r3, r0
 8005c66:	73fb      	strb	r3, [r7, #15]

  if (cfg.battery_charging_enable == 0U)
 8005c68:	f897 3025 	ldrb.w	r3, [r7, #37]	@ 0x25
 8005c6c:	2b00      	cmp	r3, #0
 8005c6e:	d106      	bne.n	8005c7e <USB_CoreInit+0x3e>
  {
    /* Activate the USB Transceiver */
    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
 8005c70:	687b      	ldr	r3, [r7, #4]
 8005c72:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005c74:	f443 3280 	orr.w	r2, r3, #65536	@ 0x10000
 8005c78:	687b      	ldr	r3, [r7, #4]
 8005c7a:	639a      	str	r2, [r3, #56]	@ 0x38
 8005c7c:	e005      	b.n	8005c8a <USB_CoreInit+0x4a>
  }
  else
  {
    /* Deactivate the USB Transceiver */
    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
 8005c7e:	687b      	ldr	r3, [r7, #4]
 8005c80:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005c82:	f423 3280 	bic.w	r2, r3, #65536	@ 0x10000
 8005c86:	687b      	ldr	r3, [r7, #4]
 8005c88:	639a      	str	r2, [r3, #56]	@ 0x38
  }

  return ret;
 8005c8a:	7bfb      	ldrb	r3, [r7, #15]
}
 8005c8c:	4618      	mov	r0, r3
 8005c8e:	3710      	adds	r7, #16
 8005c90:	46bd      	mov	sp, r7
 8005c92:	e8bd 4080 	ldmia.w	sp!, {r7, lr}
 8005c96:	b004      	add	sp, #16
 8005c98:	4770      	bx	lr

08005c9a <USB_DisableGlobalInt>:
  *         Disable the controller's Global Int in the AHB Config reg
  * @param  USBx  Selected device
  * @retval HAL status
  */
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
 8005c9a:	b480      	push	{r7}
 8005c9c:	b083      	sub	sp, #12
 8005c9e:	af00      	add	r7, sp, #0
 8005ca0:	6078      	str	r0, [r7, #4]
  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
 8005ca2:	687b      	ldr	r3, [r7, #4]
 8005ca4:	689b      	ldr	r3, [r3, #8]
 8005ca6:	f023 0201 	bic.w	r2, r3, #1
 8005caa:	687b      	ldr	r3, [r7, #4]
 8005cac:	609a      	str	r2, [r3, #8]
  return HAL_OK;
 8005cae:	2300      	movs	r3, #0
}
 8005cb0:	4618      	mov	r0, r3
 8005cb2:	370c      	adds	r7, #12
 8005cb4:	46bd      	mov	sp, r7
 8005cb6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005cba:	4770      	bx	lr

08005cbc <USB_SetCurrentMode>:
  *            @arg USB_DEVICE_MODE Peripheral mode
  *            @arg USB_HOST_MODE Host mode
  * @retval HAL status
  */
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
{
 8005cbc:	b580      	push	{r7, lr}
 8005cbe:	b084      	sub	sp, #16
 8005cc0:	af00      	add	r7, sp, #0
 8005cc2:	6078      	str	r0, [r7, #4]
 8005cc4:	460b      	mov	r3, r1
 8005cc6:	70fb      	strb	r3, [r7, #3]
  uint32_t ms = 0U;
 8005cc8:	2300      	movs	r3, #0
 8005cca:	60fb      	str	r3, [r7, #12]

  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
 8005ccc:	687b      	ldr	r3, [r7, #4]
 8005cce:	68db      	ldr	r3, [r3, #12]
 8005cd0:	f023 42c0 	bic.w	r2, r3, #1610612736	@ 0x60000000
 8005cd4:	687b      	ldr	r3, [r7, #4]
 8005cd6:	60da      	str	r2, [r3, #12]

  if (mode == USB_HOST_MODE)
 8005cd8:	78fb      	ldrb	r3, [r7, #3]
 8005cda:	2b01      	cmp	r3, #1
 8005cdc:	d115      	bne.n	8005d0a <USB_SetCurrentMode+0x4e>
  {
    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
 8005cde:	687b      	ldr	r3, [r7, #4]
 8005ce0:	68db      	ldr	r3, [r3, #12]
 8005ce2:	f043 5200 	orr.w	r2, r3, #536870912	@ 0x20000000
 8005ce6:	687b      	ldr	r3, [r7, #4]
 8005ce8:	60da      	str	r2, [r3, #12]

    do
    {
      HAL_Delay(10U);
 8005cea:	200a      	movs	r0, #10
 8005cec:	f7fb fcb6 	bl	800165c <HAL_Delay>
      ms += 10U;
 8005cf0:	68fb      	ldr	r3, [r7, #12]
 8005cf2:	330a      	adds	r3, #10
 8005cf4:	60fb      	str	r3, [r7, #12]
    } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
 8005cf6:	6878      	ldr	r0, [r7, #4]
 8005cf8:	f000 fa0e 	bl	8006118 <USB_GetMode>
 8005cfc:	4603      	mov	r3, r0
 8005cfe:	2b01      	cmp	r3, #1
 8005d00:	d01e      	beq.n	8005d40 <USB_SetCurrentMode+0x84>
 8005d02:	68fb      	ldr	r3, [r7, #12]
 8005d04:	2bc7      	cmp	r3, #199	@ 0xc7
 8005d06:	d9f0      	bls.n	8005cea <USB_SetCurrentMode+0x2e>
 8005d08:	e01a      	b.n	8005d40 <USB_SetCurrentMode+0x84>
  }
  else if (mode == USB_DEVICE_MODE)
 8005d0a:	78fb      	ldrb	r3, [r7, #3]
 8005d0c:	2b00      	cmp	r3, #0
 8005d0e:	d115      	bne.n	8005d3c <USB_SetCurrentMode+0x80>
  {
    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
 8005d10:	687b      	ldr	r3, [r7, #4]
 8005d12:	68db      	ldr	r3, [r3, #12]
 8005d14:	f043 4280 	orr.w	r2, r3, #1073741824	@ 0x40000000
 8005d18:	687b      	ldr	r3, [r7, #4]
 8005d1a:	60da      	str	r2, [r3, #12]

    do
    {
      HAL_Delay(10U);
 8005d1c:	200a      	movs	r0, #10
 8005d1e:	f7fb fc9d 	bl	800165c <HAL_Delay>
      ms += 10U;
 8005d22:	68fb      	ldr	r3, [r7, #12]
 8005d24:	330a      	adds	r3, #10
 8005d26:	60fb      	str	r3, [r7, #12]
    } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
 8005d28:	6878      	ldr	r0, [r7, #4]
 8005d2a:	f000 f9f5 	bl	8006118 <USB_GetMode>
 8005d2e:	4603      	mov	r3, r0
 8005d30:	2b00      	cmp	r3, #0
 8005d32:	d005      	beq.n	8005d40 <USB_SetCurrentMode+0x84>
 8005d34:	68fb      	ldr	r3, [r7, #12]
 8005d36:	2bc7      	cmp	r3, #199	@ 0xc7
 8005d38:	d9f0      	bls.n	8005d1c <USB_SetCurrentMode+0x60>
 8005d3a:	e001      	b.n	8005d40 <USB_SetCurrentMode+0x84>
  }
  else
  {
    return HAL_ERROR;
 8005d3c:	2301      	movs	r3, #1
 8005d3e:	e005      	b.n	8005d4c <USB_SetCurrentMode+0x90>
  }

  if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
 8005d40:	68fb      	ldr	r3, [r7, #12]
 8005d42:	2bc8      	cmp	r3, #200	@ 0xc8
 8005d44:	d101      	bne.n	8005d4a <USB_SetCurrentMode+0x8e>
  {
    return HAL_ERROR;
 8005d46:	2301      	movs	r3, #1
 8005d48:	e000      	b.n	8005d4c <USB_SetCurrentMode+0x90>
  }

  return HAL_OK;
 8005d4a:	2300      	movs	r3, #0
}
 8005d4c:	4618      	mov	r0, r3
 8005d4e:	3710      	adds	r7, #16
 8005d50:	46bd      	mov	sp, r7
 8005d52:	bd80      	pop	{r7, pc}

08005d54 <USB_DevInit>:
  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
  *         the configuration information for the specified USBx peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
 8005d54:	b084      	sub	sp, #16
 8005d56:	b580      	push	{r7, lr}
 8005d58:	b086      	sub	sp, #24
 8005d5a:	af00      	add	r7, sp, #0
 8005d5c:	6078      	str	r0, [r7, #4]
 8005d5e:	f107 0024 	add.w	r0, r7, #36	@ 0x24
 8005d62:	e880 000e 	stmia.w	r0, {r1, r2, r3}
  HAL_StatusTypeDef ret = HAL_OK;
 8005d66:	2300      	movs	r3, #0
 8005d68:	75fb      	strb	r3, [r7, #23]
  uint32_t USBx_BASE = (uint32_t)USBx;
 8005d6a:	687b      	ldr	r3, [r7, #4]
 8005d6c:	60fb      	str	r3, [r7, #12]
  uint32_t i;

  for (i = 0U; i < 15U; i++)
 8005d6e:	2300      	movs	r3, #0
 8005d70:	613b      	str	r3, [r7, #16]
 8005d72:	e009      	b.n	8005d88 <USB_DevInit+0x34>
  {
    USBx->DIEPTXF[i] = 0U;
 8005d74:	687a      	ldr	r2, [r7, #4]
 8005d76:	693b      	ldr	r3, [r7, #16]
 8005d78:	3340      	adds	r3, #64	@ 0x40
 8005d7a:	009b      	lsls	r3, r3, #2
 8005d7c:	4413      	add	r3, r2
 8005d7e:	2200      	movs	r2, #0
 8005d80:	605a      	str	r2, [r3, #4]
  for (i = 0U; i < 15U; i++)
 8005d82:	693b      	ldr	r3, [r7, #16]
 8005d84:	3301      	adds	r3, #1
 8005d86:	613b      	str	r3, [r7, #16]
 8005d88:	693b      	ldr	r3, [r7, #16]
 8005d8a:	2b0e      	cmp	r3, #14
 8005d8c:	d9f2      	bls.n	8005d74 <USB_DevInit+0x20>
  }

  /* VBUS Sensing setup */
  if (cfg.vbus_sensing_enable == 0U)
 8005d8e:	f897 302e 	ldrb.w	r3, [r7, #46]	@ 0x2e
 8005d92:	2b00      	cmp	r3, #0
 8005d94:	d11c      	bne.n	8005dd0 <USB_DevInit+0x7c>
  {
    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
 8005d96:	68fb      	ldr	r3, [r7, #12]
 8005d98:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8005d9c:	685b      	ldr	r3, [r3, #4]
 8005d9e:	68fa      	ldr	r2, [r7, #12]
 8005da0:	f502 6200 	add.w	r2, r2, #2048	@ 0x800
 8005da4:	f043 0302 	orr.w	r3, r3, #2
 8005da8:	6053      	str	r3, [r2, #4]

    /* Deactivate VBUS Sensing B */
    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 8005daa:	687b      	ldr	r3, [r7, #4]
 8005dac:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005dae:	f423 1200 	bic.w	r2, r3, #2097152	@ 0x200000
 8005db2:	687b      	ldr	r3, [r7, #4]
 8005db4:	639a      	str	r2, [r3, #56]	@ 0x38

    /* B-peripheral session valid override enable */
    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
 8005db6:	687b      	ldr	r3, [r7, #4]
 8005db8:	681b      	ldr	r3, [r3, #0]
 8005dba:	f043 0240 	orr.w	r2, r3, #64	@ 0x40
 8005dbe:	687b      	ldr	r3, [r7, #4]
 8005dc0:	601a      	str	r2, [r3, #0]
    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 8005dc2:	687b      	ldr	r3, [r7, #4]
 8005dc4:	681b      	ldr	r3, [r3, #0]
 8005dc6:	f043 0280 	orr.w	r2, r3, #128	@ 0x80
 8005dca:	687b      	ldr	r3, [r7, #4]
 8005dcc:	601a      	str	r2, [r3, #0]
 8005dce:	e005      	b.n	8005ddc <USB_DevInit+0x88>
  }
  else
  {
    /* Enable HW VBUS sensing */
    USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
 8005dd0:	687b      	ldr	r3, [r7, #4]
 8005dd2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005dd4:	f443 1200 	orr.w	r2, r3, #2097152	@ 0x200000
 8005dd8:	687b      	ldr	r3, [r7, #4]
 8005dda:	639a      	str	r2, [r3, #56]	@ 0x38
  }

  /* Restart the Phy Clock */
  USBx_PCGCCTL = 0U;
 8005ddc:	68fb      	ldr	r3, [r7, #12]
 8005dde:	f503 6360 	add.w	r3, r3, #3584	@ 0xe00
 8005de2:	461a      	mov	r2, r3
 8005de4:	2300      	movs	r3, #0
 8005de6:	6013      	str	r3, [r2, #0]

  /* Set Core speed to Full speed mode */
  (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
 8005de8:	2103      	movs	r1, #3
 8005dea:	6878      	ldr	r0, [r7, #4]
 8005dec:	f000 f95a 	bl	80060a4 <USB_SetDevSpeed>

  /* Flush the FIFOs */
  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
 8005df0:	2110      	movs	r1, #16
 8005df2:	6878      	ldr	r0, [r7, #4]
 8005df4:	f000 f8f6 	bl	8005fe4 <USB_FlushTxFifo>
 8005df8:	4603      	mov	r3, r0
 8005dfa:	2b00      	cmp	r3, #0
 8005dfc:	d001      	beq.n	8005e02 <USB_DevInit+0xae>
  {
    ret = HAL_ERROR;
 8005dfe:	2301      	movs	r3, #1
 8005e00:	75fb      	strb	r3, [r7, #23]
  }

  if (USB_FlushRxFifo(USBx) != HAL_OK)
 8005e02:	6878      	ldr	r0, [r7, #4]
 8005e04:	f000 f920 	bl	8006048 <USB_FlushRxFifo>
 8005e08:	4603      	mov	r3, r0
 8005e0a:	2b00      	cmp	r3, #0
 8005e0c:	d001      	beq.n	8005e12 <USB_DevInit+0xbe>
  {
    ret = HAL_ERROR;
 8005e0e:	2301      	movs	r3, #1
 8005e10:	75fb      	strb	r3, [r7, #23]
  }

  /* Clear all pending Device Interrupts */
  USBx_DEVICE->DIEPMSK = 0U;
 8005e12:	68fb      	ldr	r3, [r7, #12]
 8005e14:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8005e18:	461a      	mov	r2, r3
 8005e1a:	2300      	movs	r3, #0
 8005e1c:	6113      	str	r3, [r2, #16]
  USBx_DEVICE->DOEPMSK = 0U;
 8005e1e:	68fb      	ldr	r3, [r7, #12]
 8005e20:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8005e24:	461a      	mov	r2, r3
 8005e26:	2300      	movs	r3, #0
 8005e28:	6153      	str	r3, [r2, #20]
  USBx_DEVICE->DAINTMSK = 0U;
 8005e2a:	68fb      	ldr	r3, [r7, #12]
 8005e2c:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8005e30:	461a      	mov	r2, r3
 8005e32:	2300      	movs	r3, #0
 8005e34:	61d3      	str	r3, [r2, #28]

  for (i = 0U; i < cfg.dev_endpoints; i++)
 8005e36:	2300      	movs	r3, #0
 8005e38:	613b      	str	r3, [r7, #16]
 8005e3a:	e043      	b.n	8005ec4 <USB_DevInit+0x170>
  {
    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
 8005e3c:	693b      	ldr	r3, [r7, #16]
 8005e3e:	015a      	lsls	r2, r3, #5
 8005e40:	68fb      	ldr	r3, [r7, #12]
 8005e42:	4413      	add	r3, r2
 8005e44:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8005e48:	681b      	ldr	r3, [r3, #0]
 8005e4a:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8005e4e:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
 8005e52:	d118      	bne.n	8005e86 <USB_DevInit+0x132>
    {
      if (i == 0U)
 8005e54:	693b      	ldr	r3, [r7, #16]
 8005e56:	2b00      	cmp	r3, #0
 8005e58:	d10a      	bne.n	8005e70 <USB_DevInit+0x11c>
      {
        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
 8005e5a:	693b      	ldr	r3, [r7, #16]
 8005e5c:	015a      	lsls	r2, r3, #5
 8005e5e:	68fb      	ldr	r3, [r7, #12]
 8005e60:	4413      	add	r3, r2
 8005e62:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8005e66:	461a      	mov	r2, r3
 8005e68:	f04f 6300 	mov.w	r3, #134217728	@ 0x8000000
 8005e6c:	6013      	str	r3, [r2, #0]
 8005e6e:	e013      	b.n	8005e98 <USB_DevInit+0x144>
      }
      else
      {
        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
 8005e70:	693b      	ldr	r3, [r7, #16]
 8005e72:	015a      	lsls	r2, r3, #5
 8005e74:	68fb      	ldr	r3, [r7, #12]
 8005e76:	4413      	add	r3, r2
 8005e78:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8005e7c:	461a      	mov	r2, r3
 8005e7e:	f04f 4390 	mov.w	r3, #1207959552	@ 0x48000000
 8005e82:	6013      	str	r3, [r2, #0]
 8005e84:	e008      	b.n	8005e98 <USB_DevInit+0x144>
      }
    }
    else
    {
      USBx_INEP(i)->DIEPCTL = 0U;
 8005e86:	693b      	ldr	r3, [r7, #16]
 8005e88:	015a      	lsls	r2, r3, #5
 8005e8a:	68fb      	ldr	r3, [r7, #12]
 8005e8c:	4413      	add	r3, r2
 8005e8e:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8005e92:	461a      	mov	r2, r3
 8005e94:	2300      	movs	r3, #0
 8005e96:	6013      	str	r3, [r2, #0]
    }

    USBx_INEP(i)->DIEPTSIZ = 0U;
 8005e98:	693b      	ldr	r3, [r7, #16]
 8005e9a:	015a      	lsls	r2, r3, #5
 8005e9c:	68fb      	ldr	r3, [r7, #12]
 8005e9e:	4413      	add	r3, r2
 8005ea0:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8005ea4:	461a      	mov	r2, r3
 8005ea6:	2300      	movs	r3, #0
 8005ea8:	6113      	str	r3, [r2, #16]
    USBx_INEP(i)->DIEPINT  = 0xFB7FU;
 8005eaa:	693b      	ldr	r3, [r7, #16]
 8005eac:	015a      	lsls	r2, r3, #5
 8005eae:	68fb      	ldr	r3, [r7, #12]
 8005eb0:	4413      	add	r3, r2
 8005eb2:	f503 6310 	add.w	r3, r3, #2304	@ 0x900
 8005eb6:	461a      	mov	r2, r3
 8005eb8:	f64f 337f 	movw	r3, #64383	@ 0xfb7f
 8005ebc:	6093      	str	r3, [r2, #8]
  for (i = 0U; i < cfg.dev_endpoints; i++)
 8005ebe:	693b      	ldr	r3, [r7, #16]
 8005ec0:	3301      	adds	r3, #1
 8005ec2:	613b      	str	r3, [r7, #16]
 8005ec4:	f897 3024 	ldrb.w	r3, [r7, #36]	@ 0x24
 8005ec8:	461a      	mov	r2, r3
 8005eca:	693b      	ldr	r3, [r7, #16]
 8005ecc:	4293      	cmp	r3, r2
 8005ece:	d3b5      	bcc.n	8005e3c <USB_DevInit+0xe8>
  }

  for (i = 0U; i < cfg.dev_endpoints; i++)
 8005ed0:	2300      	movs	r3, #0
 8005ed2:	613b      	str	r3, [r7, #16]
 8005ed4:	e043      	b.n	8005f5e <USB_DevInit+0x20a>
  {
    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
 8005ed6:	693b      	ldr	r3, [r7, #16]
 8005ed8:	015a      	lsls	r2, r3, #5
 8005eda:	68fb      	ldr	r3, [r7, #12]
 8005edc:	4413      	add	r3, r2
 8005ede:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005ee2:	681b      	ldr	r3, [r3, #0]
 8005ee4:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8005ee8:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
 8005eec:	d118      	bne.n	8005f20 <USB_DevInit+0x1cc>
    {
      if (i == 0U)
 8005eee:	693b      	ldr	r3, [r7, #16]
 8005ef0:	2b00      	cmp	r3, #0
 8005ef2:	d10a      	bne.n	8005f0a <USB_DevInit+0x1b6>
      {
        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
 8005ef4:	693b      	ldr	r3, [r7, #16]
 8005ef6:	015a      	lsls	r2, r3, #5
 8005ef8:	68fb      	ldr	r3, [r7, #12]
 8005efa:	4413      	add	r3, r2
 8005efc:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005f00:	461a      	mov	r2, r3
 8005f02:	f04f 6300 	mov.w	r3, #134217728	@ 0x8000000
 8005f06:	6013      	str	r3, [r2, #0]
 8005f08:	e013      	b.n	8005f32 <USB_DevInit+0x1de>
      }
      else
      {
        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
 8005f0a:	693b      	ldr	r3, [r7, #16]
 8005f0c:	015a      	lsls	r2, r3, #5
 8005f0e:	68fb      	ldr	r3, [r7, #12]
 8005f10:	4413      	add	r3, r2
 8005f12:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005f16:	461a      	mov	r2, r3
 8005f18:	f04f 4390 	mov.w	r3, #1207959552	@ 0x48000000
 8005f1c:	6013      	str	r3, [r2, #0]
 8005f1e:	e008      	b.n	8005f32 <USB_DevInit+0x1de>
      }
    }
    else
    {
      USBx_OUTEP(i)->DOEPCTL = 0U;
 8005f20:	693b      	ldr	r3, [r7, #16]
 8005f22:	015a      	lsls	r2, r3, #5
 8005f24:	68fb      	ldr	r3, [r7, #12]
 8005f26:	4413      	add	r3, r2
 8005f28:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005f2c:	461a      	mov	r2, r3
 8005f2e:	2300      	movs	r3, #0
 8005f30:	6013      	str	r3, [r2, #0]
    }

    USBx_OUTEP(i)->DOEPTSIZ = 0U;
 8005f32:	693b      	ldr	r3, [r7, #16]
 8005f34:	015a      	lsls	r2, r3, #5
 8005f36:	68fb      	ldr	r3, [r7, #12]
 8005f38:	4413      	add	r3, r2
 8005f3a:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005f3e:	461a      	mov	r2, r3
 8005f40:	2300      	movs	r3, #0
 8005f42:	6113      	str	r3, [r2, #16]
    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;
 8005f44:	693b      	ldr	r3, [r7, #16]
 8005f46:	015a      	lsls	r2, r3, #5
 8005f48:	68fb      	ldr	r3, [r7, #12]
 8005f4a:	4413      	add	r3, r2
 8005f4c:	f503 6330 	add.w	r3, r3, #2816	@ 0xb00
 8005f50:	461a      	mov	r2, r3
 8005f52:	f64f 337f 	movw	r3, #64383	@ 0xfb7f
 8005f56:	6093      	str	r3, [r2, #8]
  for (i = 0U; i < cfg.dev_endpoints; i++)
 8005f58:	693b      	ldr	r3, [r7, #16]
 8005f5a:	3301      	adds	r3, #1
 8005f5c:	613b      	str	r3, [r7, #16]
 8005f5e:	f897 3024 	ldrb.w	r3, [r7, #36]	@ 0x24
 8005f62:	461a      	mov	r2, r3
 8005f64:	693b      	ldr	r3, [r7, #16]
 8005f66:	4293      	cmp	r3, r2
 8005f68:	d3b5      	bcc.n	8005ed6 <USB_DevInit+0x182>
  }

  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
 8005f6a:	68fb      	ldr	r3, [r7, #12]
 8005f6c:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 8005f70:	691b      	ldr	r3, [r3, #16]
 8005f72:	68fa      	ldr	r2, [r7, #12]
 8005f74:	f502 6200 	add.w	r2, r2, #2048	@ 0x800
 8005f78:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 8005f7c:	6113      	str	r3, [r2, #16]

  /* Disable all interrupts. */
  USBx->GINTMSK = 0U;
 8005f7e:	687b      	ldr	r3, [r7, #4]
 8005f80:	2200      	movs	r2, #0
 8005f82:	619a      	str	r2, [r3, #24]

  /* Clear any pending interrupts */
  USBx->GINTSTS = 0xBFFFFFFFU;
 8005f84:	687b      	ldr	r3, [r7, #4]
 8005f86:	f06f 4280 	mvn.w	r2, #1073741824	@ 0x40000000
 8005f8a:	615a      	str	r2, [r3, #20]

  /* Enable the common interrupts */
  USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
 8005f8c:	687b      	ldr	r3, [r7, #4]
 8005f8e:	699b      	ldr	r3, [r3, #24]
 8005f90:	f043 0210 	orr.w	r2, r3, #16
 8005f94:	687b      	ldr	r3, [r7, #4]
 8005f96:	619a      	str	r2, [r3, #24]

  /* Enable interrupts matching to the Device mode ONLY */
  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
 8005f98:	687b      	ldr	r3, [r7, #4]
 8005f9a:	699a      	ldr	r2, [r3, #24]
 8005f9c:	4b10      	ldr	r3, [pc, #64]	@ (8005fe0 <USB_DevInit+0x28c>)
 8005f9e:	4313      	orrs	r3, r2
 8005fa0:	687a      	ldr	r2, [r7, #4]
 8005fa2:	6193      	str	r3, [r2, #24]
                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |
                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;

  if (cfg.Sof_enable != 0U)
 8005fa4:	f897 302a 	ldrb.w	r3, [r7, #42]	@ 0x2a
 8005fa8:	2b00      	cmp	r3, #0
 8005faa:	d005      	beq.n	8005fb8 <USB_DevInit+0x264>
  {
    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
 8005fac:	687b      	ldr	r3, [r7, #4]
 8005fae:	699b      	ldr	r3, [r3, #24]
 8005fb0:	f043 0208 	orr.w	r2, r3, #8
 8005fb4:	687b      	ldr	r3, [r7, #4]
 8005fb6:	619a      	str	r2, [r3, #24]
  }

  if (cfg.vbus_sensing_enable == 1U)
 8005fb8:	f897 302e 	ldrb.w	r3, [r7, #46]	@ 0x2e
 8005fbc:	2b01      	cmp	r3, #1
 8005fbe:	d107      	bne.n	8005fd0 <USB_DevInit+0x27c>
  {
    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
 8005fc0:	687b      	ldr	r3, [r7, #4]
 8005fc2:	699b      	ldr	r3, [r3, #24]
 8005fc4:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
 8005fc8:	f043 0304 	orr.w	r3, r3, #4
 8005fcc:	687a      	ldr	r2, [r7, #4]
 8005fce:	6193      	str	r3, [r2, #24]
  }

  return ret;
 8005fd0:	7dfb      	ldrb	r3, [r7, #23]
}
 8005fd2:	4618      	mov	r0, r3
 8005fd4:	3718      	adds	r7, #24
 8005fd6:	46bd      	mov	sp, r7
 8005fd8:	e8bd 4080 	ldmia.w	sp!, {r7, lr}
 8005fdc:	b004      	add	sp, #16
 8005fde:	4770      	bx	lr
 8005fe0:	803c3800 	.word	0x803c3800

08005fe4 <USB_FlushTxFifo>:
  *         This parameter can be a value from 1 to 15
            15 means Flush all Tx FIFOs
  * @retval HAL status
  */
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
 8005fe4:	b480      	push	{r7}
 8005fe6:	b085      	sub	sp, #20
 8005fe8:	af00      	add	r7, sp, #0
 8005fea:	6078      	str	r0, [r7, #4]
 8005fec:	6039      	str	r1, [r7, #0]
  __IO uint32_t count = 0U;
 8005fee:	2300      	movs	r3, #0
 8005ff0:	60fb      	str	r3, [r7, #12]

  /* Wait for AHB master IDLE state. */
  do
  {
    count++;
 8005ff2:	68fb      	ldr	r3, [r7, #12]
 8005ff4:	3301      	adds	r3, #1
 8005ff6:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 8005ff8:	68fb      	ldr	r3, [r7, #12]
 8005ffa:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 8005ffe:	d901      	bls.n	8006004 <USB_FlushTxFifo+0x20>
    {
      return HAL_TIMEOUT;
 8006000:	2303      	movs	r3, #3
 8006002:	e01b      	b.n	800603c <USB_FlushTxFifo+0x58>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
 8006004:	687b      	ldr	r3, [r7, #4]
 8006006:	691b      	ldr	r3, [r3, #16]
 8006008:	2b00      	cmp	r3, #0
 800600a:	daf2      	bge.n	8005ff2 <USB_FlushTxFifo+0xe>

  /* Flush TX Fifo */
  count = 0U;
 800600c:	2300      	movs	r3, #0
 800600e:	60fb      	str	r3, [r7, #12]
  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
 8006010:	683b      	ldr	r3, [r7, #0]
 8006012:	019b      	lsls	r3, r3, #6
 8006014:	f043 0220 	orr.w	r2, r3, #32
 8006018:	687b      	ldr	r3, [r7, #4]
 800601a:	611a      	str	r2, [r3, #16]

  do
  {
    count++;
 800601c:	68fb      	ldr	r3, [r7, #12]
 800601e:	3301      	adds	r3, #1
 8006020:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 8006022:	68fb      	ldr	r3, [r7, #12]
 8006024:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 8006028:	d901      	bls.n	800602e <USB_FlushTxFifo+0x4a>
    {
      return HAL_TIMEOUT;
 800602a:	2303      	movs	r3, #3
 800602c:	e006      	b.n	800603c <USB_FlushTxFifo+0x58>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
 800602e:	687b      	ldr	r3, [r7, #4]
 8006030:	691b      	ldr	r3, [r3, #16]
 8006032:	f003 0320 	and.w	r3, r3, #32
 8006036:	2b20      	cmp	r3, #32
 8006038:	d0f0      	beq.n	800601c <USB_FlushTxFifo+0x38>

  return HAL_OK;
 800603a:	2300      	movs	r3, #0
}
 800603c:	4618      	mov	r0, r3
 800603e:	3714      	adds	r7, #20
 8006040:	46bd      	mov	sp, r7
 8006042:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006046:	4770      	bx	lr

08006048 <USB_FlushRxFifo>:
  * @brief  USB_FlushRxFifo  Flush Rx FIFO
  * @param  USBx  Selected device
  * @retval HAL status
  */
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
 8006048:	b480      	push	{r7}
 800604a:	b085      	sub	sp, #20
 800604c:	af00      	add	r7, sp, #0
 800604e:	6078      	str	r0, [r7, #4]
  __IO uint32_t count = 0U;
 8006050:	2300      	movs	r3, #0
 8006052:	60fb      	str	r3, [r7, #12]

  /* Wait for AHB master IDLE state. */
  do
  {
    count++;
 8006054:	68fb      	ldr	r3, [r7, #12]
 8006056:	3301      	adds	r3, #1
 8006058:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 800605a:	68fb      	ldr	r3, [r7, #12]
 800605c:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 8006060:	d901      	bls.n	8006066 <USB_FlushRxFifo+0x1e>
    {
      return HAL_TIMEOUT;
 8006062:	2303      	movs	r3, #3
 8006064:	e018      	b.n	8006098 <USB_FlushRxFifo+0x50>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
 8006066:	687b      	ldr	r3, [r7, #4]
 8006068:	691b      	ldr	r3, [r3, #16]
 800606a:	2b00      	cmp	r3, #0
 800606c:	daf2      	bge.n	8006054 <USB_FlushRxFifo+0xc>

  /* Flush RX Fifo */
  count = 0U;
 800606e:	2300      	movs	r3, #0
 8006070:	60fb      	str	r3, [r7, #12]
  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
 8006072:	687b      	ldr	r3, [r7, #4]
 8006074:	2210      	movs	r2, #16
 8006076:	611a      	str	r2, [r3, #16]

  do
  {
    count++;
 8006078:	68fb      	ldr	r3, [r7, #12]
 800607a:	3301      	adds	r3, #1
 800607c:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 800607e:	68fb      	ldr	r3, [r7, #12]
 8006080:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 8006084:	d901      	bls.n	800608a <USB_FlushRxFifo+0x42>
    {
      return HAL_TIMEOUT;
 8006086:	2303      	movs	r3, #3
 8006088:	e006      	b.n	8006098 <USB_FlushRxFifo+0x50>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
 800608a:	687b      	ldr	r3, [r7, #4]
 800608c:	691b      	ldr	r3, [r3, #16]
 800608e:	f003 0310 	and.w	r3, r3, #16
 8006092:	2b10      	cmp	r3, #16
 8006094:	d0f0      	beq.n	8006078 <USB_FlushRxFifo+0x30>

  return HAL_OK;
 8006096:	2300      	movs	r3, #0
}
 8006098:	4618      	mov	r0, r3
 800609a:	3714      	adds	r7, #20
 800609c:	46bd      	mov	sp, r7
 800609e:	f85d 7b04 	ldr.w	r7, [sp], #4
 80060a2:	4770      	bx	lr

080060a4 <USB_SetDevSpeed>:
  *          This parameter can be one of these values:
  *            @arg USB_OTG_SPEED_FULL: Full speed mode
  * @retval  Hal status
  */
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
 80060a4:	b480      	push	{r7}
 80060a6:	b085      	sub	sp, #20
 80060a8:	af00      	add	r7, sp, #0
 80060aa:	6078      	str	r0, [r7, #4]
 80060ac:	460b      	mov	r3, r1
 80060ae:	70fb      	strb	r3, [r7, #3]
  uint32_t USBx_BASE = (uint32_t)USBx;
 80060b0:	687b      	ldr	r3, [r7, #4]
 80060b2:	60fb      	str	r3, [r7, #12]

  USBx_DEVICE->DCFG |= speed;
 80060b4:	68fb      	ldr	r3, [r7, #12]
 80060b6:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 80060ba:	681a      	ldr	r2, [r3, #0]
 80060bc:	78fb      	ldrb	r3, [r7, #3]
 80060be:	68f9      	ldr	r1, [r7, #12]
 80060c0:	f501 6100 	add.w	r1, r1, #2048	@ 0x800
 80060c4:	4313      	orrs	r3, r2
 80060c6:	600b      	str	r3, [r1, #0]
  return HAL_OK;
 80060c8:	2300      	movs	r3, #0
}
 80060ca:	4618      	mov	r0, r3
 80060cc:	3714      	adds	r7, #20
 80060ce:	46bd      	mov	sp, r7
 80060d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80060d4:	4770      	bx	lr

080060d6 <USB_DevDisconnect>:
  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling Rpu
  * @param  USBx  Selected device
  * @retval HAL status
  */
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
 80060d6:	b480      	push	{r7}
 80060d8:	b085      	sub	sp, #20
 80060da:	af00      	add	r7, sp, #0
 80060dc:	6078      	str	r0, [r7, #4]
  uint32_t USBx_BASE = (uint32_t)USBx;
 80060de:	687b      	ldr	r3, [r7, #4]
 80060e0:	60fb      	str	r3, [r7, #12]

  /* In case phy is stopped, ensure to ungate and restore the phy CLK */
  USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
 80060e2:	68fb      	ldr	r3, [r7, #12]
 80060e4:	f503 6360 	add.w	r3, r3, #3584	@ 0xe00
 80060e8:	681b      	ldr	r3, [r3, #0]
 80060ea:	68fa      	ldr	r2, [r7, #12]
 80060ec:	f502 6260 	add.w	r2, r2, #3584	@ 0xe00
 80060f0:	f023 0303 	bic.w	r3, r3, #3
 80060f4:	6013      	str	r3, [r2, #0]

  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
 80060f6:	68fb      	ldr	r3, [r7, #12]
 80060f8:	f503 6300 	add.w	r3, r3, #2048	@ 0x800
 80060fc:	685b      	ldr	r3, [r3, #4]
 80060fe:	68fa      	ldr	r2, [r7, #12]
 8006100:	f502 6200 	add.w	r2, r2, #2048	@ 0x800
 8006104:	f043 0302 	orr.w	r3, r3, #2
 8006108:	6053      	str	r3, [r2, #4]

  return HAL_OK;
 800610a:	2300      	movs	r3, #0
}
 800610c:	4618      	mov	r0, r3
 800610e:	3714      	adds	r7, #20
 8006110:	46bd      	mov	sp, r7
 8006112:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006116:	4770      	bx	lr

08006118 <USB_GetMode>:
  *          This parameter can be one of these values:
  *           0 : Host
  *           1 : Device
  */
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
 8006118:	b480      	push	{r7}
 800611a:	b083      	sub	sp, #12
 800611c:	af00      	add	r7, sp, #0
 800611e:	6078      	str	r0, [r7, #4]
  return ((USBx->GINTSTS) & 0x1U);
 8006120:	687b      	ldr	r3, [r7, #4]
 8006122:	695b      	ldr	r3, [r3, #20]
 8006124:	f003 0301 	and.w	r3, r3, #1
}
 8006128:	4618      	mov	r0, r3
 800612a:	370c      	adds	r7, #12
 800612c:	46bd      	mov	sp, r7
 800612e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006132:	4770      	bx	lr

08006134 <USB_CoreReset>:
  * @brief  Reset the USB Core (needed after USB clock settings change)
  * @param  USBx  Selected device
  * @retval HAL status
  */
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
 8006134:	b480      	push	{r7}
 8006136:	b085      	sub	sp, #20
 8006138:	af00      	add	r7, sp, #0
 800613a:	6078      	str	r0, [r7, #4]
  __IO uint32_t count = 0U;
 800613c:	2300      	movs	r3, #0
 800613e:	60fb      	str	r3, [r7, #12]

  /* Wait for AHB master IDLE state. */
  do
  {
    count++;
 8006140:	68fb      	ldr	r3, [r7, #12]
 8006142:	3301      	adds	r3, #1
 8006144:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 8006146:	68fb      	ldr	r3, [r7, #12]
 8006148:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 800614c:	d901      	bls.n	8006152 <USB_CoreReset+0x1e>
    {
      return HAL_TIMEOUT;
 800614e:	2303      	movs	r3, #3
 8006150:	e01b      	b.n	800618a <USB_CoreReset+0x56>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
 8006152:	687b      	ldr	r3, [r7, #4]
 8006154:	691b      	ldr	r3, [r3, #16]
 8006156:	2b00      	cmp	r3, #0
 8006158:	daf2      	bge.n	8006140 <USB_CoreReset+0xc>

  /* Core Soft Reset */
  count = 0U;
 800615a:	2300      	movs	r3, #0
 800615c:	60fb      	str	r3, [r7, #12]
  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
 800615e:	687b      	ldr	r3, [r7, #4]
 8006160:	691b      	ldr	r3, [r3, #16]
 8006162:	f043 0201 	orr.w	r2, r3, #1
 8006166:	687b      	ldr	r3, [r7, #4]
 8006168:	611a      	str	r2, [r3, #16]

  do
  {
    count++;
 800616a:	68fb      	ldr	r3, [r7, #12]
 800616c:	3301      	adds	r3, #1
 800616e:	60fb      	str	r3, [r7, #12]

    if (count > HAL_USB_TIMEOUT)
 8006170:	68fb      	ldr	r3, [r7, #12]
 8006172:	f1b3 6f70 	cmp.w	r3, #251658240	@ 0xf000000
 8006176:	d901      	bls.n	800617c <USB_CoreReset+0x48>
    {
      return HAL_TIMEOUT;
 8006178:	2303      	movs	r3, #3
 800617a:	e006      	b.n	800618a <USB_CoreReset+0x56>
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
 800617c:	687b      	ldr	r3, [r7, #4]
 800617e:	691b      	ldr	r3, [r3, #16]
 8006180:	f003 0301 	and.w	r3, r3, #1
 8006184:	2b01      	cmp	r3, #1
 8006186:	d0f0      	beq.n	800616a <USB_CoreReset+0x36>

  return HAL_OK;
 8006188:	2300      	movs	r3, #0
}
 800618a:	4618      	mov	r0, r3
 800618c:	3714      	adds	r7, #20
 800618e:	46bd      	mov	sp, r7
 8006190:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006194:	4770      	bx	lr
	...

08006198 <__NVIC_SetPriority>:
{
 8006198:	b480      	push	{r7}
 800619a:	b083      	sub	sp, #12
 800619c:	af00      	add	r7, sp, #0
 800619e:	4603      	mov	r3, r0
 80061a0:	6039      	str	r1, [r7, #0]
 80061a2:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80061a4:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80061a8:	2b00      	cmp	r3, #0
 80061aa:	db0a      	blt.n	80061c2 <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80061ac:	683b      	ldr	r3, [r7, #0]
 80061ae:	b2da      	uxtb	r2, r3
 80061b0:	490c      	ldr	r1, [pc, #48]	@ (80061e4 <__NVIC_SetPriority+0x4c>)
 80061b2:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80061b6:	0112      	lsls	r2, r2, #4
 80061b8:	b2d2      	uxtb	r2, r2
 80061ba:	440b      	add	r3, r1
 80061bc:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
}
 80061c0:	e00a      	b.n	80061d8 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80061c2:	683b      	ldr	r3, [r7, #0]
 80061c4:	b2da      	uxtb	r2, r3
 80061c6:	4908      	ldr	r1, [pc, #32]	@ (80061e8 <__NVIC_SetPriority+0x50>)
 80061c8:	79fb      	ldrb	r3, [r7, #7]
 80061ca:	f003 030f 	and.w	r3, r3, #15
 80061ce:	3b04      	subs	r3, #4
 80061d0:	0112      	lsls	r2, r2, #4
 80061d2:	b2d2      	uxtb	r2, r2
 80061d4:	440b      	add	r3, r1
 80061d6:	761a      	strb	r2, [r3, #24]
}
 80061d8:	bf00      	nop
 80061da:	370c      	adds	r7, #12
 80061dc:	46bd      	mov	sp, r7
 80061de:	f85d 7b04 	ldr.w	r7, [sp], #4
 80061e2:	4770      	bx	lr
 80061e4:	e000e100 	.word	0xe000e100
 80061e8:	e000ed00 	.word	0xe000ed00

080061ec <SysTick_Handler>:

/*
  SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
 80061ec:	b580      	push	{r7, lr}
 80061ee:	af00      	add	r7, sp, #0
  /* Clear overflow flag */
  SysTick->CTRL;
 80061f0:	4b05      	ldr	r3, [pc, #20]	@ (8006208 <SysTick_Handler+0x1c>)
 80061f2:	681b      	ldr	r3, [r3, #0]

  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
 80061f4:	f001 ff3a 	bl	800806c <xTaskGetSchedulerState>
 80061f8:	4603      	mov	r3, r0
 80061fa:	2b01      	cmp	r3, #1
 80061fc:	d001      	beq.n	8006202 <SysTick_Handler+0x16>
    /* Call tick handler */
    xPortSysTickHandler();
 80061fe:	f002 fe33 	bl	8008e68 <xPortSysTickHandler>
  }
}
 8006202:	bf00      	nop
 8006204:	bd80      	pop	{r7, pc}
 8006206:	bf00      	nop
 8006208:	e000e010 	.word	0xe000e010

0800620c <SVC_Setup>:
#endif /* SysTick */

/*
  Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
 800620c:	b580      	push	{r7, lr}
 800620e:	af00      	add	r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
  /* Service Call interrupt might be configured before kernel start     */
  /* and when its priority is lower or equal to BASEPRI, svc intruction */
  /* causes a Hard Fault.                                               */
  NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
 8006210:	2100      	movs	r1, #0
 8006212:	f06f 0004 	mvn.w	r0, #4
 8006216:	f7ff ffbf 	bl	8006198 <__NVIC_SetPriority>
#endif
}
 800621a:	bf00      	nop
 800621c:	bd80      	pop	{r7, pc}
	...

08006220 <osKernelInitialize>:
static uint32_t OS_Tick_GetOverflow (void);
/* Get OS Tick interval */
static uint32_t OS_Tick_GetInterval (void);
/*---------------------------------------------------------------------------*/

osStatus_t osKernelInitialize (void) {
 8006220:	b480      	push	{r7}
 8006222:	b083      	sub	sp, #12
 8006224:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8006226:	f3ef 8305 	mrs	r3, IPSR
 800622a:	603b      	str	r3, [r7, #0]
  return(result);
 800622c:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 800622e:	2b00      	cmp	r3, #0
 8006230:	d003      	beq.n	800623a <osKernelInitialize+0x1a>
    stat = osErrorISR;
 8006232:	f06f 0305 	mvn.w	r3, #5
 8006236:	607b      	str	r3, [r7, #4]
 8006238:	e00c      	b.n	8006254 <osKernelInitialize+0x34>
  }
  else {
    if (KernelState == osKernelInactive) {
 800623a:	4b0a      	ldr	r3, [pc, #40]	@ (8006264 <osKernelInitialize+0x44>)
 800623c:	681b      	ldr	r3, [r3, #0]
 800623e:	2b00      	cmp	r3, #0
 8006240:	d105      	bne.n	800624e <osKernelInitialize+0x2e>
        EvrFreeRTOSSetup(0U);
      #endif
      #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
        vPortDefineHeapRegions (configHEAP_5_REGIONS);
      #endif
      KernelState = osKernelReady;
 8006242:	4b08      	ldr	r3, [pc, #32]	@ (8006264 <osKernelInitialize+0x44>)
 8006244:	2201      	movs	r2, #1
 8006246:	601a      	str	r2, [r3, #0]
      stat = osOK;
 8006248:	2300      	movs	r3, #0
 800624a:	607b      	str	r3, [r7, #4]
 800624c:	e002      	b.n	8006254 <osKernelInitialize+0x34>
    } else {
      stat = osError;
 800624e:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8006252:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 8006254:	687b      	ldr	r3, [r7, #4]
}
 8006256:	4618      	mov	r0, r3
 8006258:	370c      	adds	r7, #12
 800625a:	46bd      	mov	sp, r7
 800625c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006260:	4770      	bx	lr
 8006262:	bf00      	nop
 8006264:	2000083c 	.word	0x2000083c

08006268 <osKernelStart>:
  }

  return (state);
}

osStatus_t osKernelStart (void) {
 8006268:	b580      	push	{r7, lr}
 800626a:	b082      	sub	sp, #8
 800626c:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800626e:	f3ef 8305 	mrs	r3, IPSR
 8006272:	603b      	str	r3, [r7, #0]
  return(result);
 8006274:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 8006276:	2b00      	cmp	r3, #0
 8006278:	d003      	beq.n	8006282 <osKernelStart+0x1a>
    stat = osErrorISR;
 800627a:	f06f 0305 	mvn.w	r3, #5
 800627e:	607b      	str	r3, [r7, #4]
 8006280:	e010      	b.n	80062a4 <osKernelStart+0x3c>
  }
  else {
    if (KernelState == osKernelReady) {
 8006282:	4b0b      	ldr	r3, [pc, #44]	@ (80062b0 <osKernelStart+0x48>)
 8006284:	681b      	ldr	r3, [r3, #0]
 8006286:	2b01      	cmp	r3, #1
 8006288:	d109      	bne.n	800629e <osKernelStart+0x36>
      /* Ensure SVC priority is at the reset value */
      SVC_Setup();
 800628a:	f7ff ffbf 	bl	800620c <SVC_Setup>
      /* Change state to enable IRQ masking check */
      KernelState = osKernelRunning;
 800628e:	4b08      	ldr	r3, [pc, #32]	@ (80062b0 <osKernelStart+0x48>)
 8006290:	2202      	movs	r2, #2
 8006292:	601a      	str	r2, [r3, #0]
      /* Start the kernel scheduler */
      vTaskStartScheduler();
 8006294:	f001 fa86 	bl	80077a4 <vTaskStartScheduler>
      stat = osOK;
 8006298:	2300      	movs	r3, #0
 800629a:	607b      	str	r3, [r7, #4]
 800629c:	e002      	b.n	80062a4 <osKernelStart+0x3c>
    } else {
      stat = osError;
 800629e:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80062a2:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 80062a4:	687b      	ldr	r3, [r7, #4]
}
 80062a6:	4618      	mov	r0, r3
 80062a8:	3708      	adds	r7, #8
 80062aa:	46bd      	mov	sp, r7
 80062ac:	bd80      	pop	{r7, pc}
 80062ae:	bf00      	nop
 80062b0:	2000083c 	.word	0x2000083c

080062b4 <osThreadNew>:
  return (configCPU_CLOCK_HZ);
}

/*---------------------------------------------------------------------------*/

osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
 80062b4:	b580      	push	{r7, lr}
 80062b6:	b08e      	sub	sp, #56	@ 0x38
 80062b8:	af04      	add	r7, sp, #16
 80062ba:	60f8      	str	r0, [r7, #12]
 80062bc:	60b9      	str	r1, [r7, #8]
 80062be:	607a      	str	r2, [r7, #4]
  uint32_t stack;
  TaskHandle_t hTask;
  UBaseType_t prio;
  int32_t mem;

  hTask = NULL;
 80062c0:	2300      	movs	r3, #0
 80062c2:	613b      	str	r3, [r7, #16]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 80062c4:	f3ef 8305 	mrs	r3, IPSR
 80062c8:	617b      	str	r3, [r7, #20]
  return(result);
 80062ca:	697b      	ldr	r3, [r7, #20]

  if (!IS_IRQ() && (func != NULL)) {
 80062cc:	2b00      	cmp	r3, #0
 80062ce:	d17e      	bne.n	80063ce <osThreadNew+0x11a>
 80062d0:	68fb      	ldr	r3, [r7, #12]
 80062d2:	2b00      	cmp	r3, #0
 80062d4:	d07b      	beq.n	80063ce <osThreadNew+0x11a>
    stack = configMINIMAL_STACK_SIZE;
 80062d6:	2380      	movs	r3, #128	@ 0x80
 80062d8:	623b      	str	r3, [r7, #32]
    prio  = (UBaseType_t)osPriorityNormal;
 80062da:	2318      	movs	r3, #24
 80062dc:	61fb      	str	r3, [r7, #28]

    name = NULL;
 80062de:	2300      	movs	r3, #0
 80062e0:	627b      	str	r3, [r7, #36]	@ 0x24
    mem  = -1;
 80062e2:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80062e6:	61bb      	str	r3, [r7, #24]

    if (attr != NULL) {
 80062e8:	687b      	ldr	r3, [r7, #4]
 80062ea:	2b00      	cmp	r3, #0
 80062ec:	d045      	beq.n	800637a <osThreadNew+0xc6>
      if (attr->name != NULL) {
 80062ee:	687b      	ldr	r3, [r7, #4]
 80062f0:	681b      	ldr	r3, [r3, #0]
 80062f2:	2b00      	cmp	r3, #0
 80062f4:	d002      	beq.n	80062fc <osThreadNew+0x48>
        name = attr->name;
 80062f6:	687b      	ldr	r3, [r7, #4]
 80062f8:	681b      	ldr	r3, [r3, #0]
 80062fa:	627b      	str	r3, [r7, #36]	@ 0x24
      }
      if (attr->priority != osPriorityNone) {
 80062fc:	687b      	ldr	r3, [r7, #4]
 80062fe:	699b      	ldr	r3, [r3, #24]
 8006300:	2b00      	cmp	r3, #0
 8006302:	d002      	beq.n	800630a <osThreadNew+0x56>
        prio = (UBaseType_t)attr->priority;
 8006304:	687b      	ldr	r3, [r7, #4]
 8006306:	699b      	ldr	r3, [r3, #24]
 8006308:	61fb      	str	r3, [r7, #28]
      }

      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
 800630a:	69fb      	ldr	r3, [r7, #28]
 800630c:	2b00      	cmp	r3, #0
 800630e:	d008      	beq.n	8006322 <osThreadNew+0x6e>
 8006310:	69fb      	ldr	r3, [r7, #28]
 8006312:	2b38      	cmp	r3, #56	@ 0x38
 8006314:	d805      	bhi.n	8006322 <osThreadNew+0x6e>
 8006316:	687b      	ldr	r3, [r7, #4]
 8006318:	685b      	ldr	r3, [r3, #4]
 800631a:	f003 0301 	and.w	r3, r3, #1
 800631e:	2b00      	cmp	r3, #0
 8006320:	d001      	beq.n	8006326 <osThreadNew+0x72>
        return (NULL);
 8006322:	2300      	movs	r3, #0
 8006324:	e054      	b.n	80063d0 <osThreadNew+0x11c>
      }

      if (attr->stack_size > 0U) {
 8006326:	687b      	ldr	r3, [r7, #4]
 8006328:	695b      	ldr	r3, [r3, #20]
 800632a:	2b00      	cmp	r3, #0
 800632c:	d003      	beq.n	8006336 <osThreadNew+0x82>
        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */
        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
        stack = attr->stack_size / sizeof(StackType_t);
 800632e:	687b      	ldr	r3, [r7, #4]
 8006330:	695b      	ldr	r3, [r3, #20]
 8006332:	089b      	lsrs	r3, r3, #2
 8006334:	623b      	str	r3, [r7, #32]
      }

      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 8006336:	687b      	ldr	r3, [r7, #4]
 8006338:	689b      	ldr	r3, [r3, #8]
 800633a:	2b00      	cmp	r3, #0
 800633c:	d00e      	beq.n	800635c <osThreadNew+0xa8>
 800633e:	687b      	ldr	r3, [r7, #4]
 8006340:	68db      	ldr	r3, [r3, #12]
 8006342:	2ba7      	cmp	r3, #167	@ 0xa7
 8006344:	d90a      	bls.n	800635c <osThreadNew+0xa8>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 8006346:	687b      	ldr	r3, [r7, #4]
 8006348:	691b      	ldr	r3, [r3, #16]
      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 800634a:	2b00      	cmp	r3, #0
 800634c:	d006      	beq.n	800635c <osThreadNew+0xa8>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 800634e:	687b      	ldr	r3, [r7, #4]
 8006350:	695b      	ldr	r3, [r3, #20]
 8006352:	2b00      	cmp	r3, #0
 8006354:	d002      	beq.n	800635c <osThreadNew+0xa8>
        mem = 1;
 8006356:	2301      	movs	r3, #1
 8006358:	61bb      	str	r3, [r7, #24]
 800635a:	e010      	b.n	800637e <osThreadNew+0xca>
      }
      else {
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
 800635c:	687b      	ldr	r3, [r7, #4]
 800635e:	689b      	ldr	r3, [r3, #8]
 8006360:	2b00      	cmp	r3, #0
 8006362:	d10c      	bne.n	800637e <osThreadNew+0xca>
 8006364:	687b      	ldr	r3, [r7, #4]
 8006366:	68db      	ldr	r3, [r3, #12]
 8006368:	2b00      	cmp	r3, #0
 800636a:	d108      	bne.n	800637e <osThreadNew+0xca>
 800636c:	687b      	ldr	r3, [r7, #4]
 800636e:	691b      	ldr	r3, [r3, #16]
 8006370:	2b00      	cmp	r3, #0
 8006372:	d104      	bne.n	800637e <osThreadNew+0xca>
          mem = 0;
 8006374:	2300      	movs	r3, #0
 8006376:	61bb      	str	r3, [r7, #24]
 8006378:	e001      	b.n	800637e <osThreadNew+0xca>
        }
      }
    }
    else {
      mem = 0;
 800637a:	2300      	movs	r3, #0
 800637c:	61bb      	str	r3, [r7, #24]
    }

    if (mem == 1) {
 800637e:	69bb      	ldr	r3, [r7, #24]
 8006380:	2b01      	cmp	r3, #1
 8006382:	d110      	bne.n	80063a6 <osThreadNew+0xf2>
      #if (configSUPPORT_STATIC_ALLOCATION == 1)
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 8006384:	687b      	ldr	r3, [r7, #4]
 8006386:	691b      	ldr	r3, [r3, #16]
                                                                                      (StaticTask_t *)attr->cb_mem);
 8006388:	687a      	ldr	r2, [r7, #4]
 800638a:	6892      	ldr	r2, [r2, #8]
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 800638c:	9202      	str	r2, [sp, #8]
 800638e:	9301      	str	r3, [sp, #4]
 8006390:	69fb      	ldr	r3, [r7, #28]
 8006392:	9300      	str	r3, [sp, #0]
 8006394:	68bb      	ldr	r3, [r7, #8]
 8006396:	6a3a      	ldr	r2, [r7, #32]
 8006398:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 800639a:	68f8      	ldr	r0, [r7, #12]
 800639c:	f001 f80e 	bl	80073bc <xTaskCreateStatic>
 80063a0:	4603      	mov	r3, r0
 80063a2:	613b      	str	r3, [r7, #16]
 80063a4:	e013      	b.n	80063ce <osThreadNew+0x11a>
      #endif
    }
    else {
      if (mem == 0) {
 80063a6:	69bb      	ldr	r3, [r7, #24]
 80063a8:	2b00      	cmp	r3, #0
 80063aa:	d110      	bne.n	80063ce <osThreadNew+0x11a>
        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
          if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
 80063ac:	6a3b      	ldr	r3, [r7, #32]
 80063ae:	b29a      	uxth	r2, r3
 80063b0:	f107 0310 	add.w	r3, r7, #16
 80063b4:	9301      	str	r3, [sp, #4]
 80063b6:	69fb      	ldr	r3, [r7, #28]
 80063b8:	9300      	str	r3, [sp, #0]
 80063ba:	68bb      	ldr	r3, [r7, #8]
 80063bc:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 80063be:	68f8      	ldr	r0, [r7, #12]
 80063c0:	f001 f85c 	bl	800747c <xTaskCreate>
 80063c4:	4603      	mov	r3, r0
 80063c6:	2b01      	cmp	r3, #1
 80063c8:	d001      	beq.n	80063ce <osThreadNew+0x11a>
            hTask = NULL;
 80063ca:	2300      	movs	r3, #0
 80063cc:	613b      	str	r3, [r7, #16]
        #endif
      }
    }
  }

  return ((osThreadId_t)hTask);
 80063ce:	693b      	ldr	r3, [r7, #16]
}
 80063d0:	4618      	mov	r0, r3
 80063d2:	3728      	adds	r7, #40	@ 0x28
 80063d4:	46bd      	mov	sp, r7
 80063d6:	bd80      	pop	{r7, pc}

080063d8 <osDelay>:
  /* Return flags before clearing */
  return (rflags);
}
#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */

osStatus_t osDelay (uint32_t ticks) {
 80063d8:	b580      	push	{r7, lr}
 80063da:	b084      	sub	sp, #16
 80063dc:	af00      	add	r7, sp, #0
 80063de:	6078      	str	r0, [r7, #4]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 80063e0:	f3ef 8305 	mrs	r3, IPSR
 80063e4:	60bb      	str	r3, [r7, #8]
  return(result);
 80063e6:	68bb      	ldr	r3, [r7, #8]
  osStatus_t stat;

  if (IS_IRQ()) {
 80063e8:	2b00      	cmp	r3, #0
 80063ea:	d003      	beq.n	80063f4 <osDelay+0x1c>
    stat = osErrorISR;
 80063ec:	f06f 0305 	mvn.w	r3, #5
 80063f0:	60fb      	str	r3, [r7, #12]
 80063f2:	e007      	b.n	8006404 <osDelay+0x2c>
  }
  else {
    stat = osOK;
 80063f4:	2300      	movs	r3, #0
 80063f6:	60fb      	str	r3, [r7, #12]

    if (ticks != 0U) {
 80063f8:	687b      	ldr	r3, [r7, #4]
 80063fa:	2b00      	cmp	r3, #0
 80063fc:	d002      	beq.n	8006404 <osDelay+0x2c>
      vTaskDelay(ticks);
 80063fe:	6878      	ldr	r0, [r7, #4]
 8006400:	f001 f99a 	bl	8007738 <vTaskDelay>
    }
  }

  return (stat);
 8006404:	68fb      	ldr	r3, [r7, #12]
}
 8006406:	4618      	mov	r0, r3
 8006408:	3710      	adds	r7, #16
 800640a:	46bd      	mov	sp, r7
 800640c:	bd80      	pop	{r7, pc}
	...

08006410 <vApplicationGetIdleTaskMemory>:

/*
  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
 8006410:	b480      	push	{r7}
 8006412:	b085      	sub	sp, #20
 8006414:	af00      	add	r7, sp, #0
 8006416:	60f8      	str	r0, [r7, #12]
 8006418:	60b9      	str	r1, [r7, #8]
 800641a:	607a      	str	r2, [r7, #4]
  /* Idle task control block and stack */
  static StaticTask_t Idle_TCB;
  static StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];

  *ppxIdleTaskTCBBuffer   = &Idle_TCB;
 800641c:	68fb      	ldr	r3, [r7, #12]
 800641e:	4a07      	ldr	r2, [pc, #28]	@ (800643c <vApplicationGetIdleTaskMemory+0x2c>)
 8006420:	601a      	str	r2, [r3, #0]
  *ppxIdleTaskStackBuffer = &Idle_Stack[0];
 8006422:	68bb      	ldr	r3, [r7, #8]
 8006424:	4a06      	ldr	r2, [pc, #24]	@ (8006440 <vApplicationGetIdleTaskMemory+0x30>)
 8006426:	601a      	str	r2, [r3, #0]
  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;
 8006428:	687b      	ldr	r3, [r7, #4]
 800642a:	2280      	movs	r2, #128	@ 0x80
 800642c:	601a      	str	r2, [r3, #0]
}
 800642e:	bf00      	nop
 8006430:	3714      	adds	r7, #20
 8006432:	46bd      	mov	sp, r7
 8006434:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006438:	4770      	bx	lr
 800643a:	bf00      	nop
 800643c:	20000840 	.word	0x20000840
 8006440:	200008e8 	.word	0x200008e8

08006444 <vApplicationGetTimerTaskMemory>:

/*
  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
 8006444:	b480      	push	{r7}
 8006446:	b085      	sub	sp, #20
 8006448:	af00      	add	r7, sp, #0
 800644a:	60f8      	str	r0, [r7, #12]
 800644c:	60b9      	str	r1, [r7, #8]
 800644e:	607a      	str	r2, [r7, #4]
  /* Timer task control block and stack */
  static StaticTask_t Timer_TCB;
  static StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];

  *ppxTimerTaskTCBBuffer   = &Timer_TCB;
 8006450:	68fb      	ldr	r3, [r7, #12]
 8006452:	4a07      	ldr	r2, [pc, #28]	@ (8006470 <vApplicationGetTimerTaskMemory+0x2c>)
 8006454:	601a      	str	r2, [r3, #0]
  *ppxTimerTaskStackBuffer = &Timer_Stack[0];
 8006456:	68bb      	ldr	r3, [r7, #8]
 8006458:	4a06      	ldr	r2, [pc, #24]	@ (8006474 <vApplicationGetTimerTaskMemory+0x30>)
 800645a:	601a      	str	r2, [r3, #0]
  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;
 800645c:	687b      	ldr	r3, [r7, #4]
 800645e:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8006462:	601a      	str	r2, [r3, #0]
}
 8006464:	bf00      	nop
 8006466:	3714      	adds	r7, #20
 8006468:	46bd      	mov	sp, r7
 800646a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800646e:	4770      	bx	lr
 8006470:	20000ae8 	.word	0x20000ae8
 8006474:	20000b90 	.word	0x20000b90

08006478 <vListInitialise>:
/*-----------------------------------------------------------
 * PUBLIC LIST API documented in list.h
 *----------------------------------------------------------*/

void vListInitialise( List_t * const pxList )
{
 8006478:	b480      	push	{r7}
 800647a:	b083      	sub	sp, #12
 800647c:	af00      	add	r7, sp, #0
 800647e:	6078      	str	r0, [r7, #4]
	/* The list structure contains a list item which is used to mark the
	end of the list.  To initialise the list the list end is inserted
	as the only list entry. */
	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 8006480:	687b      	ldr	r3, [r7, #4]
 8006482:	f103 0208 	add.w	r2, r3, #8
 8006486:	687b      	ldr	r3, [r7, #4]
 8006488:	605a      	str	r2, [r3, #4]

	/* The list end value is the highest possible value in the list to
	ensure it remains at the end of the list. */
	pxList->xListEnd.xItemValue = portMAX_DELAY;
 800648a:	687b      	ldr	r3, [r7, #4]
 800648c:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8006490:	609a      	str	r2, [r3, #8]

	/* The list end next and previous pointers point to itself so we know
	when the list is empty. */
	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 8006492:	687b      	ldr	r3, [r7, #4]
 8006494:	f103 0208 	add.w	r2, r3, #8
 8006498:	687b      	ldr	r3, [r7, #4]
 800649a:	60da      	str	r2, [r3, #12]
	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 800649c:	687b      	ldr	r3, [r7, #4]
 800649e:	f103 0208 	add.w	r2, r3, #8
 80064a2:	687b      	ldr	r3, [r7, #4]
 80064a4:	611a      	str	r2, [r3, #16]

	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
 80064a6:	687b      	ldr	r3, [r7, #4]
 80064a8:	2200      	movs	r2, #0
 80064aa:	601a      	str	r2, [r3, #0]

	/* Write known values into the list if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
 80064ac:	bf00      	nop
 80064ae:	370c      	adds	r7, #12
 80064b0:	46bd      	mov	sp, r7
 80064b2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80064b6:	4770      	bx	lr

080064b8 <vListInitialiseItem>:
/*-----------------------------------------------------------*/

void vListInitialiseItem( ListItem_t * const pxItem )
{
 80064b8:	b480      	push	{r7}
 80064ba:	b083      	sub	sp, #12
 80064bc:	af00      	add	r7, sp, #0
 80064be:	6078      	str	r0, [r7, #4]
	/* Make sure the list item is not recorded as being on a list. */
	pxItem->pxContainer = NULL;
 80064c0:	687b      	ldr	r3, [r7, #4]
 80064c2:	2200      	movs	r2, #0
 80064c4:	611a      	str	r2, [r3, #16]

	/* Write known values into the list item if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
 80064c6:	bf00      	nop
 80064c8:	370c      	adds	r7, #12
 80064ca:	46bd      	mov	sp, r7
 80064cc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80064d0:	4770      	bx	lr

080064d2 <vListInsertEnd>:
/*-----------------------------------------------------------*/

void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 80064d2:	b480      	push	{r7}
 80064d4:	b085      	sub	sp, #20
 80064d6:	af00      	add	r7, sp, #0
 80064d8:	6078      	str	r0, [r7, #4]
 80064da:	6039      	str	r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
 80064dc:	687b      	ldr	r3, [r7, #4]
 80064de:	685b      	ldr	r3, [r3, #4]
 80064e0:	60fb      	str	r3, [r7, #12]
	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );

	/* Insert a new list item into pxList, but rather than sort the list,
	makes the new list item the last item to be removed by a call to
	listGET_OWNER_OF_NEXT_ENTRY(). */
	pxNewListItem->pxNext = pxIndex;
 80064e2:	683b      	ldr	r3, [r7, #0]
 80064e4:	68fa      	ldr	r2, [r7, #12]
 80064e6:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
 80064e8:	68fb      	ldr	r3, [r7, #12]
 80064ea:	689a      	ldr	r2, [r3, #8]
 80064ec:	683b      	ldr	r3, [r7, #0]
 80064ee:	609a      	str	r2, [r3, #8]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	pxIndex->pxPrevious->pxNext = pxNewListItem;
 80064f0:	68fb      	ldr	r3, [r7, #12]
 80064f2:	689b      	ldr	r3, [r3, #8]
 80064f4:	683a      	ldr	r2, [r7, #0]
 80064f6:	605a      	str	r2, [r3, #4]
	pxIndex->pxPrevious = pxNewListItem;
 80064f8:	68fb      	ldr	r3, [r7, #12]
 80064fa:	683a      	ldr	r2, [r7, #0]
 80064fc:	609a      	str	r2, [r3, #8]

	/* Remember which list the item is in. */
	pxNewListItem->pxContainer = pxList;
 80064fe:	683b      	ldr	r3, [r7, #0]
 8006500:	687a      	ldr	r2, [r7, #4]
 8006502:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 8006504:	687b      	ldr	r3, [r7, #4]
 8006506:	681b      	ldr	r3, [r3, #0]
 8006508:	1c5a      	adds	r2, r3, #1
 800650a:	687b      	ldr	r3, [r7, #4]
 800650c:	601a      	str	r2, [r3, #0]
}
 800650e:	bf00      	nop
 8006510:	3714      	adds	r7, #20
 8006512:	46bd      	mov	sp, r7
 8006514:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006518:	4770      	bx	lr

0800651a <vListInsert>:
/*-----------------------------------------------------------*/

void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 800651a:	b480      	push	{r7}
 800651c:	b085      	sub	sp, #20
 800651e:	af00      	add	r7, sp, #0
 8006520:	6078      	str	r0, [r7, #4]
 8006522:	6039      	str	r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 8006524:	683b      	ldr	r3, [r7, #0]
 8006526:	681b      	ldr	r3, [r3, #0]
 8006528:	60bb      	str	r3, [r7, #8]
	new list item should be placed after it.  This ensures that TCBs which are
	stored in ready lists (all of which have the same xItemValue value) get a
	share of the CPU.  However, if the xItemValue is the same as the back marker
	the iteration loop below will not end.  Therefore the value is checked
	first, and the algorithm slightly modified if necessary. */
	if( xValueOfInsertion == portMAX_DELAY )
 800652a:	68bb      	ldr	r3, [r7, #8]
 800652c:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006530:	d103      	bne.n	800653a <vListInsert+0x20>
	{
		pxIterator = pxList->xListEnd.pxPrevious;
 8006532:	687b      	ldr	r3, [r7, #4]
 8006534:	691b      	ldr	r3, [r3, #16]
 8006536:	60fb      	str	r3, [r7, #12]
 8006538:	e00c      	b.n	8006554 <vListInsert+0x3a>
			4) Using a queue or semaphore before it has been initialised or
			   before the scheduler has been started (are interrupts firing
			   before vTaskStartScheduler() has been called?).
		**********************************************************************/

		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
 800653a:	687b      	ldr	r3, [r7, #4]
 800653c:	3308      	adds	r3, #8
 800653e:	60fb      	str	r3, [r7, #12]
 8006540:	e002      	b.n	8006548 <vListInsert+0x2e>
 8006542:	68fb      	ldr	r3, [r7, #12]
 8006544:	685b      	ldr	r3, [r3, #4]
 8006546:	60fb      	str	r3, [r7, #12]
 8006548:	68fb      	ldr	r3, [r7, #12]
 800654a:	685b      	ldr	r3, [r3, #4]
 800654c:	681b      	ldr	r3, [r3, #0]
 800654e:	68ba      	ldr	r2, [r7, #8]
 8006550:	429a      	cmp	r2, r3
 8006552:	d2f6      	bcs.n	8006542 <vListInsert+0x28>
			/* There is nothing to do here, just iterating to the wanted
			insertion position. */
		}
	}

	pxNewListItem->pxNext = pxIterator->pxNext;
 8006554:	68fb      	ldr	r3, [r7, #12]
 8006556:	685a      	ldr	r2, [r3, #4]
 8006558:	683b      	ldr	r3, [r7, #0]
 800655a:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
 800655c:	683b      	ldr	r3, [r7, #0]
 800655e:	685b      	ldr	r3, [r3, #4]
 8006560:	683a      	ldr	r2, [r7, #0]
 8006562:	609a      	str	r2, [r3, #8]
	pxNewListItem->pxPrevious = pxIterator;
 8006564:	683b      	ldr	r3, [r7, #0]
 8006566:	68fa      	ldr	r2, [r7, #12]
 8006568:	609a      	str	r2, [r3, #8]
	pxIterator->pxNext = pxNewListItem;
 800656a:	68fb      	ldr	r3, [r7, #12]
 800656c:	683a      	ldr	r2, [r7, #0]
 800656e:	605a      	str	r2, [r3, #4]

	/* Remember which list the item is in.  This allows fast removal of the
	item later. */
	pxNewListItem->pxContainer = pxList;
 8006570:	683b      	ldr	r3, [r7, #0]
 8006572:	687a      	ldr	r2, [r7, #4]
 8006574:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 8006576:	687b      	ldr	r3, [r7, #4]
 8006578:	681b      	ldr	r3, [r3, #0]
 800657a:	1c5a      	adds	r2, r3, #1
 800657c:	687b      	ldr	r3, [r7, #4]
 800657e:	601a      	str	r2, [r3, #0]
}
 8006580:	bf00      	nop
 8006582:	3714      	adds	r7, #20
 8006584:	46bd      	mov	sp, r7
 8006586:	f85d 7b04 	ldr.w	r7, [sp], #4
 800658a:	4770      	bx	lr

0800658c <uxListRemove>:
/*-----------------------------------------------------------*/

UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
 800658c:	b480      	push	{r7}
 800658e:	b085      	sub	sp, #20
 8006590:	af00      	add	r7, sp, #0
 8006592:	6078      	str	r0, [r7, #4]
/* The list item knows which list it is in.  Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
 8006594:	687b      	ldr	r3, [r7, #4]
 8006596:	691b      	ldr	r3, [r3, #16]
 8006598:	60fb      	str	r3, [r7, #12]

	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
 800659a:	687b      	ldr	r3, [r7, #4]
 800659c:	685b      	ldr	r3, [r3, #4]
 800659e:	687a      	ldr	r2, [r7, #4]
 80065a0:	6892      	ldr	r2, [r2, #8]
 80065a2:	609a      	str	r2, [r3, #8]
	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 80065a4:	687b      	ldr	r3, [r7, #4]
 80065a6:	689b      	ldr	r3, [r3, #8]
 80065a8:	687a      	ldr	r2, [r7, #4]
 80065aa:	6852      	ldr	r2, [r2, #4]
 80065ac:	605a      	str	r2, [r3, #4]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	/* Make sure the index is left pointing to a valid item. */
	if( pxList->pxIndex == pxItemToRemove )
 80065ae:	68fb      	ldr	r3, [r7, #12]
 80065b0:	685b      	ldr	r3, [r3, #4]
 80065b2:	687a      	ldr	r2, [r7, #4]
 80065b4:	429a      	cmp	r2, r3
 80065b6:	d103      	bne.n	80065c0 <uxListRemove+0x34>
	{
		pxList->pxIndex = pxItemToRemove->pxPrevious;
 80065b8:	687b      	ldr	r3, [r7, #4]
 80065ba:	689a      	ldr	r2, [r3, #8]
 80065bc:	68fb      	ldr	r3, [r7, #12]
 80065be:	605a      	str	r2, [r3, #4]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxItemToRemove->pxContainer = NULL;
 80065c0:	687b      	ldr	r3, [r7, #4]
 80065c2:	2200      	movs	r2, #0
 80065c4:	611a      	str	r2, [r3, #16]
	( pxList->uxNumberOfItems )--;
 80065c6:	68fb      	ldr	r3, [r7, #12]
 80065c8:	681b      	ldr	r3, [r3, #0]
 80065ca:	1e5a      	subs	r2, r3, #1
 80065cc:	68fb      	ldr	r3, [r7, #12]
 80065ce:	601a      	str	r2, [r3, #0]

	return pxList->uxNumberOfItems;
 80065d0:	68fb      	ldr	r3, [r7, #12]
 80065d2:	681b      	ldr	r3, [r3, #0]
}
 80065d4:	4618      	mov	r0, r3
 80065d6:	3714      	adds	r7, #20
 80065d8:	46bd      	mov	sp, r7
 80065da:	f85d 7b04 	ldr.w	r7, [sp], #4
 80065de:	4770      	bx	lr

080065e0 <xQueueGenericReset>:
	}														\
	taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
 80065e0:	b580      	push	{r7, lr}
 80065e2:	b084      	sub	sp, #16
 80065e4:	af00      	add	r7, sp, #0
 80065e6:	6078      	str	r0, [r7, #4]
 80065e8:	6039      	str	r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
 80065ea:	687b      	ldr	r3, [r7, #4]
 80065ec:	60fb      	str	r3, [r7, #12]

	configASSERT( pxQueue );
 80065ee:	68fb      	ldr	r3, [r7, #12]
 80065f0:	2b00      	cmp	r3, #0
 80065f2:	d10b      	bne.n	800660c <xQueueGenericReset+0x2c>

portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;

	__asm volatile
 80065f4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80065f8:	f383 8811 	msr	BASEPRI, r3
 80065fc:	f3bf 8f6f 	isb	sy
 8006600:	f3bf 8f4f 	dsb	sy
 8006604:	60bb      	str	r3, [r7, #8]
		"	msr basepri, %0											\n" \
		"	isb														\n" \
		"	dsb														\n" \
		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);
}
 8006606:	bf00      	nop
 8006608:	bf00      	nop
 800660a:	e7fd      	b.n	8006608 <xQueueGenericReset+0x28>

	taskENTER_CRITICAL();
 800660c:	f002 fb9c 	bl	8008d48 <vPortEnterCritical>
	{
		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 8006610:	68fb      	ldr	r3, [r7, #12]
 8006612:	681a      	ldr	r2, [r3, #0]
 8006614:	68fb      	ldr	r3, [r7, #12]
 8006616:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8006618:	68f9      	ldr	r1, [r7, #12]
 800661a:	6c09      	ldr	r1, [r1, #64]	@ 0x40
 800661c:	fb01 f303 	mul.w	r3, r1, r3
 8006620:	441a      	add	r2, r3
 8006622:	68fb      	ldr	r3, [r7, #12]
 8006624:	609a      	str	r2, [r3, #8]
		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
 8006626:	68fb      	ldr	r3, [r7, #12]
 8006628:	2200      	movs	r2, #0
 800662a:	639a      	str	r2, [r3, #56]	@ 0x38
		pxQueue->pcWriteTo = pxQueue->pcHead;
 800662c:	68fb      	ldr	r3, [r7, #12]
 800662e:	681a      	ldr	r2, [r3, #0]
 8006630:	68fb      	ldr	r3, [r7, #12]
 8006632:	605a      	str	r2, [r3, #4]
		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 8006634:	68fb      	ldr	r3, [r7, #12]
 8006636:	681a      	ldr	r2, [r3, #0]
 8006638:	68fb      	ldr	r3, [r7, #12]
 800663a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800663c:	3b01      	subs	r3, #1
 800663e:	68f9      	ldr	r1, [r7, #12]
 8006640:	6c09      	ldr	r1, [r1, #64]	@ 0x40
 8006642:	fb01 f303 	mul.w	r3, r1, r3
 8006646:	441a      	add	r2, r3
 8006648:	68fb      	ldr	r3, [r7, #12]
 800664a:	60da      	str	r2, [r3, #12]
		pxQueue->cRxLock = queueUNLOCKED;
 800664c:	68fb      	ldr	r3, [r7, #12]
 800664e:	22ff      	movs	r2, #255	@ 0xff
 8006650:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
		pxQueue->cTxLock = queueUNLOCKED;
 8006654:	68fb      	ldr	r3, [r7, #12]
 8006656:	22ff      	movs	r2, #255	@ 0xff
 8006658:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45

		if( xNewQueue == pdFALSE )
 800665c:	683b      	ldr	r3, [r7, #0]
 800665e:	2b00      	cmp	r3, #0
 8006660:	d114      	bne.n	800668c <xQueueGenericReset+0xac>
			/* If there are tasks blocked waiting to read from the queue, then
			the tasks will remain blocked as after this function exits the queue
			will still be empty.  If there are tasks blocked waiting to write to
			the queue, then one should be unblocked as after this function exits
			it will be possible to write to it. */
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8006662:	68fb      	ldr	r3, [r7, #12]
 8006664:	691b      	ldr	r3, [r3, #16]
 8006666:	2b00      	cmp	r3, #0
 8006668:	d01a      	beq.n	80066a0 <xQueueGenericReset+0xc0>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 800666a:	68fb      	ldr	r3, [r7, #12]
 800666c:	3310      	adds	r3, #16
 800666e:	4618      	mov	r0, r3
 8006670:	f001 fb36 	bl	8007ce0 <xTaskRemoveFromEventList>
 8006674:	4603      	mov	r3, r0
 8006676:	2b00      	cmp	r3, #0
 8006678:	d012      	beq.n	80066a0 <xQueueGenericReset+0xc0>
				{
					queueYIELD_IF_USING_PREEMPTION();
 800667a:	4b0d      	ldr	r3, [pc, #52]	@ (80066b0 <xQueueGenericReset+0xd0>)
 800667c:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006680:	601a      	str	r2, [r3, #0]
 8006682:	f3bf 8f4f 	dsb	sy
 8006686:	f3bf 8f6f 	isb	sy
 800668a:	e009      	b.n	80066a0 <xQueueGenericReset+0xc0>
			}
		}
		else
		{
			/* Ensure the event queues start in the correct state. */
			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
 800668c:	68fb      	ldr	r3, [r7, #12]
 800668e:	3310      	adds	r3, #16
 8006690:	4618      	mov	r0, r3
 8006692:	f7ff fef1 	bl	8006478 <vListInitialise>
			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
 8006696:	68fb      	ldr	r3, [r7, #12]
 8006698:	3324      	adds	r3, #36	@ 0x24
 800669a:	4618      	mov	r0, r3
 800669c:	f7ff feec 	bl	8006478 <vListInitialise>
		}
	}
	taskEXIT_CRITICAL();
 80066a0:	f002 fb84 	bl	8008dac <vPortExitCritical>

	/* A value is returned for calling semantic consistency with previous
	versions. */
	return pdPASS;
 80066a4:	2301      	movs	r3, #1
}
 80066a6:	4618      	mov	r0, r3
 80066a8:	3710      	adds	r7, #16
 80066aa:	46bd      	mov	sp, r7
 80066ac:	bd80      	pop	{r7, pc}
 80066ae:	bf00      	nop
 80066b0:	e000ed04 	.word	0xe000ed04

080066b4 <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_STATIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
	{
 80066b4:	b580      	push	{r7, lr}
 80066b6:	b08e      	sub	sp, #56	@ 0x38
 80066b8:	af02      	add	r7, sp, #8
 80066ba:	60f8      	str	r0, [r7, #12]
 80066bc:	60b9      	str	r1, [r7, #8]
 80066be:	607a      	str	r2, [r7, #4]
 80066c0:	603b      	str	r3, [r7, #0]
	Queue_t *pxNewQueue;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 80066c2:	68fb      	ldr	r3, [r7, #12]
 80066c4:	2b00      	cmp	r3, #0
 80066c6:	d10b      	bne.n	80066e0 <xQueueGenericCreateStatic+0x2c>
	__asm volatile
 80066c8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80066cc:	f383 8811 	msr	BASEPRI, r3
 80066d0:	f3bf 8f6f 	isb	sy
 80066d4:	f3bf 8f4f 	dsb	sy
 80066d8:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 80066da:	bf00      	nop
 80066dc:	bf00      	nop
 80066de:	e7fd      	b.n	80066dc <xQueueGenericCreateStatic+0x28>

		/* The StaticQueue_t structure and the queue storage area must be
		supplied. */
		configASSERT( pxStaticQueue != NULL );
 80066e0:	683b      	ldr	r3, [r7, #0]
 80066e2:	2b00      	cmp	r3, #0
 80066e4:	d10b      	bne.n	80066fe <xQueueGenericCreateStatic+0x4a>
	__asm volatile
 80066e6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80066ea:	f383 8811 	msr	BASEPRI, r3
 80066ee:	f3bf 8f6f 	isb	sy
 80066f2:	f3bf 8f4f 	dsb	sy
 80066f6:	627b      	str	r3, [r7, #36]	@ 0x24
}
 80066f8:	bf00      	nop
 80066fa:	bf00      	nop
 80066fc:	e7fd      	b.n	80066fa <xQueueGenericCreateStatic+0x46>

		/* A queue storage area should be provided if the item size is not 0, and
		should not be provided if the item size is 0. */
		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
 80066fe:	687b      	ldr	r3, [r7, #4]
 8006700:	2b00      	cmp	r3, #0
 8006702:	d002      	beq.n	800670a <xQueueGenericCreateStatic+0x56>
 8006704:	68bb      	ldr	r3, [r7, #8]
 8006706:	2b00      	cmp	r3, #0
 8006708:	d001      	beq.n	800670e <xQueueGenericCreateStatic+0x5a>
 800670a:	2301      	movs	r3, #1
 800670c:	e000      	b.n	8006710 <xQueueGenericCreateStatic+0x5c>
 800670e:	2300      	movs	r3, #0
 8006710:	2b00      	cmp	r3, #0
 8006712:	d10b      	bne.n	800672c <xQueueGenericCreateStatic+0x78>
	__asm volatile
 8006714:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006718:	f383 8811 	msr	BASEPRI, r3
 800671c:	f3bf 8f6f 	isb	sy
 8006720:	f3bf 8f4f 	dsb	sy
 8006724:	623b      	str	r3, [r7, #32]
}
 8006726:	bf00      	nop
 8006728:	bf00      	nop
 800672a:	e7fd      	b.n	8006728 <xQueueGenericCreateStatic+0x74>
		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
 800672c:	687b      	ldr	r3, [r7, #4]
 800672e:	2b00      	cmp	r3, #0
 8006730:	d102      	bne.n	8006738 <xQueueGenericCreateStatic+0x84>
 8006732:	68bb      	ldr	r3, [r7, #8]
 8006734:	2b00      	cmp	r3, #0
 8006736:	d101      	bne.n	800673c <xQueueGenericCreateStatic+0x88>
 8006738:	2301      	movs	r3, #1
 800673a:	e000      	b.n	800673e <xQueueGenericCreateStatic+0x8a>
 800673c:	2300      	movs	r3, #0
 800673e:	2b00      	cmp	r3, #0
 8006740:	d10b      	bne.n	800675a <xQueueGenericCreateStatic+0xa6>
	__asm volatile
 8006742:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006746:	f383 8811 	msr	BASEPRI, r3
 800674a:	f3bf 8f6f 	isb	sy
 800674e:	f3bf 8f4f 	dsb	sy
 8006752:	61fb      	str	r3, [r7, #28]
}
 8006754:	bf00      	nop
 8006756:	bf00      	nop
 8006758:	e7fd      	b.n	8006756 <xQueueGenericCreateStatic+0xa2>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
			the real queue and semaphore structures. */
			volatile size_t xSize = sizeof( StaticQueue_t );
 800675a:	2350      	movs	r3, #80	@ 0x50
 800675c:	617b      	str	r3, [r7, #20]
			configASSERT( xSize == sizeof( Queue_t ) );
 800675e:	697b      	ldr	r3, [r7, #20]
 8006760:	2b50      	cmp	r3, #80	@ 0x50
 8006762:	d00b      	beq.n	800677c <xQueueGenericCreateStatic+0xc8>
	__asm volatile
 8006764:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006768:	f383 8811 	msr	BASEPRI, r3
 800676c:	f3bf 8f6f 	isb	sy
 8006770:	f3bf 8f4f 	dsb	sy
 8006774:	61bb      	str	r3, [r7, #24]
}
 8006776:	bf00      	nop
 8006778:	bf00      	nop
 800677a:	e7fd      	b.n	8006778 <xQueueGenericCreateStatic+0xc4>
			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 800677c:	697b      	ldr	r3, [r7, #20]
		#endif /* configASSERT_DEFINED */

		/* The address of a statically allocated queue was passed in, use it.
		The address of a statically allocated storage area was also passed in
		but is already set. */
		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 800677e:	683b      	ldr	r3, [r7, #0]
 8006780:	62fb      	str	r3, [r7, #44]	@ 0x2c

		if( pxNewQueue != NULL )
 8006782:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006784:	2b00      	cmp	r3, #0
 8006786:	d00d      	beq.n	80067a4 <xQueueGenericCreateStatic+0xf0>
			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
			{
				/* Queues can be allocated wither statically or dynamically, so
				note this queue was allocated statically in case the queue is
				later deleted. */
				pxNewQueue->ucStaticallyAllocated = pdTRUE;
 8006788:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800678a:	2201      	movs	r2, #1
 800678c:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
			}
			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 8006790:	f897 2038 	ldrb.w	r2, [r7, #56]	@ 0x38
 8006794:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006796:	9300      	str	r3, [sp, #0]
 8006798:	4613      	mov	r3, r2
 800679a:	687a      	ldr	r2, [r7, #4]
 800679c:	68b9      	ldr	r1, [r7, #8]
 800679e:	68f8      	ldr	r0, [r7, #12]
 80067a0:	f000 f840 	bl	8006824 <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 80067a4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
	}
 80067a6:	4618      	mov	r0, r3
 80067a8:	3730      	adds	r7, #48	@ 0x30
 80067aa:	46bd      	mov	sp, r7
 80067ac:	bd80      	pop	{r7, pc}

080067ae <xQueueGenericCreate>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
	{
 80067ae:	b580      	push	{r7, lr}
 80067b0:	b08a      	sub	sp, #40	@ 0x28
 80067b2:	af02      	add	r7, sp, #8
 80067b4:	60f8      	str	r0, [r7, #12]
 80067b6:	60b9      	str	r1, [r7, #8]
 80067b8:	4613      	mov	r3, r2
 80067ba:	71fb      	strb	r3, [r7, #7]
	Queue_t *pxNewQueue;
	size_t xQueueSizeInBytes;
	uint8_t *pucQueueStorage;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 80067bc:	68fb      	ldr	r3, [r7, #12]
 80067be:	2b00      	cmp	r3, #0
 80067c0:	d10b      	bne.n	80067da <xQueueGenericCreate+0x2c>
	__asm volatile
 80067c2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80067c6:	f383 8811 	msr	BASEPRI, r3
 80067ca:	f3bf 8f6f 	isb	sy
 80067ce:	f3bf 8f4f 	dsb	sy
 80067d2:	613b      	str	r3, [r7, #16]
}
 80067d4:	bf00      	nop
 80067d6:	bf00      	nop
 80067d8:	e7fd      	b.n	80067d6 <xQueueGenericCreate+0x28>

		/* Allocate enough space to hold the maximum number of items that
		can be in the queue at any time.  It is valid for uxItemSize to be
		zero in the case the queue is used as a semaphore. */
		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80067da:	68fb      	ldr	r3, [r7, #12]
 80067dc:	68ba      	ldr	r2, [r7, #8]
 80067de:	fb02 f303 	mul.w	r3, r2, r3
 80067e2:	61fb      	str	r3, [r7, #28]
		alignment requirements of the Queue_t structure - which in this case
		is an int8_t *.  Therefore, whenever the stack alignment requirements
		are greater than or equal to the pointer to char requirements the cast
		is safe.  In other cases alignment requirements are not strict (one or
		two bytes). */
		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
 80067e4:	69fb      	ldr	r3, [r7, #28]
 80067e6:	3350      	adds	r3, #80	@ 0x50
 80067e8:	4618      	mov	r0, r3
 80067ea:	f002 fbcf 	bl	8008f8c <pvPortMalloc>
 80067ee:	61b8      	str	r0, [r7, #24]

		if( pxNewQueue != NULL )
 80067f0:	69bb      	ldr	r3, [r7, #24]
 80067f2:	2b00      	cmp	r3, #0
 80067f4:	d011      	beq.n	800681a <xQueueGenericCreate+0x6c>
		{
			/* Jump past the queue structure to find the location of the queue
			storage area. */
			pucQueueStorage = ( uint8_t * ) pxNewQueue;
 80067f6:	69bb      	ldr	r3, [r7, #24]
 80067f8:	617b      	str	r3, [r7, #20]
			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 80067fa:	697b      	ldr	r3, [r7, #20]
 80067fc:	3350      	adds	r3, #80	@ 0x50
 80067fe:	617b      	str	r3, [r7, #20]
			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
			{
				/* Queues can be created either statically or dynamically, so
				note this task was created dynamically in case it is later
				deleted. */
				pxNewQueue->ucStaticallyAllocated = pdFALSE;
 8006800:	69bb      	ldr	r3, [r7, #24]
 8006802:	2200      	movs	r2, #0
 8006804:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
			}
			#endif /* configSUPPORT_STATIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 8006808:	79fa      	ldrb	r2, [r7, #7]
 800680a:	69bb      	ldr	r3, [r7, #24]
 800680c:	9300      	str	r3, [sp, #0]
 800680e:	4613      	mov	r3, r2
 8006810:	697a      	ldr	r2, [r7, #20]
 8006812:	68b9      	ldr	r1, [r7, #8]
 8006814:	68f8      	ldr	r0, [r7, #12]
 8006816:	f000 f805 	bl	8006824 <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 800681a:	69bb      	ldr	r3, [r7, #24]
	}
 800681c:	4618      	mov	r0, r3
 800681e:	3720      	adds	r7, #32
 8006820:	46bd      	mov	sp, r7
 8006822:	bd80      	pop	{r7, pc}

08006824 <prvInitialiseNewQueue>:

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
 8006824:	b580      	push	{r7, lr}
 8006826:	b084      	sub	sp, #16
 8006828:	af00      	add	r7, sp, #0
 800682a:	60f8      	str	r0, [r7, #12]
 800682c:	60b9      	str	r1, [r7, #8]
 800682e:	607a      	str	r2, [r7, #4]
 8006830:	70fb      	strb	r3, [r7, #3]
	/* Remove compiler warnings about unused parameters should
	configUSE_TRACE_FACILITY not be set to 1. */
	( void ) ucQueueType;

	if( uxItemSize == ( UBaseType_t ) 0 )
 8006832:	68bb      	ldr	r3, [r7, #8]
 8006834:	2b00      	cmp	r3, #0
 8006836:	d103      	bne.n	8006840 <prvInitialiseNewQueue+0x1c>
	{
		/* No RAM was allocated for the queue storage area, but PC head cannot
		be set to NULL because NULL is used as a key to say the queue is used as
		a mutex.  Therefore just set pcHead to point to the queue as a benign
		value that is known to be within the memory map. */
		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
 8006838:	69bb      	ldr	r3, [r7, #24]
 800683a:	69ba      	ldr	r2, [r7, #24]
 800683c:	601a      	str	r2, [r3, #0]
 800683e:	e002      	b.n	8006846 <prvInitialiseNewQueue+0x22>
	}
	else
	{
		/* Set the head to the start of the queue storage area. */
		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
 8006840:	69bb      	ldr	r3, [r7, #24]
 8006842:	687a      	ldr	r2, [r7, #4]
 8006844:	601a      	str	r2, [r3, #0]
	}

	/* Initialise the queue members as described where the queue type is
	defined. */
	pxNewQueue->uxLength = uxQueueLength;
 8006846:	69bb      	ldr	r3, [r7, #24]
 8006848:	68fa      	ldr	r2, [r7, #12]
 800684a:	63da      	str	r2, [r3, #60]	@ 0x3c
	pxNewQueue->uxItemSize = uxItemSize;
 800684c:	69bb      	ldr	r3, [r7, #24]
 800684e:	68ba      	ldr	r2, [r7, #8]
 8006850:	641a      	str	r2, [r3, #64]	@ 0x40
	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
 8006852:	2101      	movs	r1, #1
 8006854:	69b8      	ldr	r0, [r7, #24]
 8006856:	f7ff fec3 	bl	80065e0 <xQueueGenericReset>

	#if ( configUSE_TRACE_FACILITY == 1 )
	{
		pxNewQueue->ucQueueType = ucQueueType;
 800685a:	69bb      	ldr	r3, [r7, #24]
 800685c:	78fa      	ldrb	r2, [r7, #3]
 800685e:	f883 204c 	strb.w	r2, [r3, #76]	@ 0x4c
		pxNewQueue->pxQueueSetContainer = NULL;
	}
	#endif /* configUSE_QUEUE_SETS */

	traceQUEUE_CREATE( pxNewQueue );
}
 8006862:	bf00      	nop
 8006864:	3710      	adds	r7, #16
 8006866:	46bd      	mov	sp, r7
 8006868:	bd80      	pop	{r7, pc}
	...

0800686c <xQueueGenericSend>:

#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
 800686c:	b580      	push	{r7, lr}
 800686e:	b08e      	sub	sp, #56	@ 0x38
 8006870:	af00      	add	r7, sp, #0
 8006872:	60f8      	str	r0, [r7, #12]
 8006874:	60b9      	str	r1, [r7, #8]
 8006876:	607a      	str	r2, [r7, #4]
 8006878:	603b      	str	r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
 800687a:	2300      	movs	r3, #0
 800687c:	637b      	str	r3, [r7, #52]	@ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 800687e:	68fb      	ldr	r3, [r7, #12]
 8006880:	633b      	str	r3, [r7, #48]	@ 0x30

	configASSERT( pxQueue );
 8006882:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006884:	2b00      	cmp	r3, #0
 8006886:	d10b      	bne.n	80068a0 <xQueueGenericSend+0x34>
	__asm volatile
 8006888:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800688c:	f383 8811 	msr	BASEPRI, r3
 8006890:	f3bf 8f6f 	isb	sy
 8006894:	f3bf 8f4f 	dsb	sy
 8006898:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 800689a:	bf00      	nop
 800689c:	bf00      	nop
 800689e:	e7fd      	b.n	800689c <xQueueGenericSend+0x30>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80068a0:	68bb      	ldr	r3, [r7, #8]
 80068a2:	2b00      	cmp	r3, #0
 80068a4:	d103      	bne.n	80068ae <xQueueGenericSend+0x42>
 80068a6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80068a8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80068aa:	2b00      	cmp	r3, #0
 80068ac:	d101      	bne.n	80068b2 <xQueueGenericSend+0x46>
 80068ae:	2301      	movs	r3, #1
 80068b0:	e000      	b.n	80068b4 <xQueueGenericSend+0x48>
 80068b2:	2300      	movs	r3, #0
 80068b4:	2b00      	cmp	r3, #0
 80068b6:	d10b      	bne.n	80068d0 <xQueueGenericSend+0x64>
	__asm volatile
 80068b8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80068bc:	f383 8811 	msr	BASEPRI, r3
 80068c0:	f3bf 8f6f 	isb	sy
 80068c4:	f3bf 8f4f 	dsb	sy
 80068c8:	627b      	str	r3, [r7, #36]	@ 0x24
}
 80068ca:	bf00      	nop
 80068cc:	bf00      	nop
 80068ce:	e7fd      	b.n	80068cc <xQueueGenericSend+0x60>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 80068d0:	683b      	ldr	r3, [r7, #0]
 80068d2:	2b02      	cmp	r3, #2
 80068d4:	d103      	bne.n	80068de <xQueueGenericSend+0x72>
 80068d6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80068d8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80068da:	2b01      	cmp	r3, #1
 80068dc:	d101      	bne.n	80068e2 <xQueueGenericSend+0x76>
 80068de:	2301      	movs	r3, #1
 80068e0:	e000      	b.n	80068e4 <xQueueGenericSend+0x78>
 80068e2:	2300      	movs	r3, #0
 80068e4:	2b00      	cmp	r3, #0
 80068e6:	d10b      	bne.n	8006900 <xQueueGenericSend+0x94>
	__asm volatile
 80068e8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80068ec:	f383 8811 	msr	BASEPRI, r3
 80068f0:	f3bf 8f6f 	isb	sy
 80068f4:	f3bf 8f4f 	dsb	sy
 80068f8:	623b      	str	r3, [r7, #32]
}
 80068fa:	bf00      	nop
 80068fc:	bf00      	nop
 80068fe:	e7fd      	b.n	80068fc <xQueueGenericSend+0x90>
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8006900:	f001 fbb4 	bl	800806c <xTaskGetSchedulerState>
 8006904:	4603      	mov	r3, r0
 8006906:	2b00      	cmp	r3, #0
 8006908:	d102      	bne.n	8006910 <xQueueGenericSend+0xa4>
 800690a:	687b      	ldr	r3, [r7, #4]
 800690c:	2b00      	cmp	r3, #0
 800690e:	d101      	bne.n	8006914 <xQueueGenericSend+0xa8>
 8006910:	2301      	movs	r3, #1
 8006912:	e000      	b.n	8006916 <xQueueGenericSend+0xaa>
 8006914:	2300      	movs	r3, #0
 8006916:	2b00      	cmp	r3, #0
 8006918:	d10b      	bne.n	8006932 <xQueueGenericSend+0xc6>
	__asm volatile
 800691a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800691e:	f383 8811 	msr	BASEPRI, r3
 8006922:	f3bf 8f6f 	isb	sy
 8006926:	f3bf 8f4f 	dsb	sy
 800692a:	61fb      	str	r3, [r7, #28]
}
 800692c:	bf00      	nop
 800692e:	bf00      	nop
 8006930:	e7fd      	b.n	800692e <xQueueGenericSend+0xc2>
	/*lint -save -e904 This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8006932:	f002 fa09 	bl	8008d48 <vPortEnterCritical>
		{
			/* Is there room on the queue now?  The running task must be the
			highest priority task wanting to access the queue.  If the head item
			in the queue is to be overwritten then it does not matter if the
			queue is full. */
			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 8006936:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006938:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 800693a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800693c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800693e:	429a      	cmp	r2, r3
 8006940:	d302      	bcc.n	8006948 <xQueueGenericSend+0xdc>
 8006942:	683b      	ldr	r3, [r7, #0]
 8006944:	2b02      	cmp	r3, #2
 8006946:	d129      	bne.n	800699c <xQueueGenericSend+0x130>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 8006948:	683a      	ldr	r2, [r7, #0]
 800694a:	68b9      	ldr	r1, [r7, #8]
 800694c:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 800694e:	f000 fbc7 	bl	80070e0 <prvCopyDataToQueue>
 8006952:	62f8      	str	r0, [r7, #44]	@ 0x2c

					/* If there was a task waiting for data to arrive on the
					queue then unblock it now. */
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8006954:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006956:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8006958:	2b00      	cmp	r3, #0
 800695a:	d010      	beq.n	800697e <xQueueGenericSend+0x112>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 800695c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800695e:	3324      	adds	r3, #36	@ 0x24
 8006960:	4618      	mov	r0, r3
 8006962:	f001 f9bd 	bl	8007ce0 <xTaskRemoveFromEventList>
 8006966:	4603      	mov	r3, r0
 8006968:	2b00      	cmp	r3, #0
 800696a:	d013      	beq.n	8006994 <xQueueGenericSend+0x128>
						{
							/* The unblocked task has a priority higher than
							our own so yield immediately.  Yes it is ok to do
							this from within the critical section - the kernel
							takes care of that. */
							queueYIELD_IF_USING_PREEMPTION();
 800696c:	4b3f      	ldr	r3, [pc, #252]	@ (8006a6c <xQueueGenericSend+0x200>)
 800696e:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006972:	601a      	str	r2, [r3, #0]
 8006974:	f3bf 8f4f 	dsb	sy
 8006978:	f3bf 8f6f 	isb	sy
 800697c:	e00a      	b.n	8006994 <xQueueGenericSend+0x128>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}
					}
					else if( xYieldRequired != pdFALSE )
 800697e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006980:	2b00      	cmp	r3, #0
 8006982:	d007      	beq.n	8006994 <xQueueGenericSend+0x128>
					{
						/* This path is a special case that will only get
						executed if the task was holding multiple mutexes and
						the mutexes were given back in an order that is
						different to that in which they were taken. */
						queueYIELD_IF_USING_PREEMPTION();
 8006984:	4b39      	ldr	r3, [pc, #228]	@ (8006a6c <xQueueGenericSend+0x200>)
 8006986:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 800698a:	601a      	str	r2, [r3, #0]
 800698c:	f3bf 8f4f 	dsb	sy
 8006990:	f3bf 8f6f 	isb	sy
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif /* configUSE_QUEUE_SETS */

				taskEXIT_CRITICAL();
 8006994:	f002 fa0a 	bl	8008dac <vPortExitCritical>
				return pdPASS;
 8006998:	2301      	movs	r3, #1
 800699a:	e063      	b.n	8006a64 <xQueueGenericSend+0x1f8>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 800699c:	687b      	ldr	r3, [r7, #4]
 800699e:	2b00      	cmp	r3, #0
 80069a0:	d103      	bne.n	80069aa <xQueueGenericSend+0x13e>
				{
					/* The queue was full and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 80069a2:	f002 fa03 	bl	8008dac <vPortExitCritical>

					/* Return to the original privilege level before exiting
					the function. */
					traceQUEUE_SEND_FAILED( pxQueue );
					return errQUEUE_FULL;
 80069a6:	2300      	movs	r3, #0
 80069a8:	e05c      	b.n	8006a64 <xQueueGenericSend+0x1f8>
				}
				else if( xEntryTimeSet == pdFALSE )
 80069aa:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80069ac:	2b00      	cmp	r3, #0
 80069ae:	d106      	bne.n	80069be <xQueueGenericSend+0x152>
				{
					/* The queue was full and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 80069b0:	f107 0314 	add.w	r3, r7, #20
 80069b4:	4618      	mov	r0, r3
 80069b6:	f001 f9f7 	bl	8007da8 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 80069ba:	2301      	movs	r3, #1
 80069bc:	637b      	str	r3, [r7, #52]	@ 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 80069be:	f002 f9f5 	bl	8008dac <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 80069c2:	f000 ff5f 	bl	8007884 <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 80069c6:	f002 f9bf 	bl	8008d48 <vPortEnterCritical>
 80069ca:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80069cc:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 80069d0:	b25b      	sxtb	r3, r3
 80069d2:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80069d6:	d103      	bne.n	80069e0 <xQueueGenericSend+0x174>
 80069d8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80069da:	2200      	movs	r2, #0
 80069dc:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 80069e0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80069e2:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 80069e6:	b25b      	sxtb	r3, r3
 80069e8:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80069ec:	d103      	bne.n	80069f6 <xQueueGenericSend+0x18a>
 80069ee:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80069f0:	2200      	movs	r2, #0
 80069f2:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 80069f6:	f002 f9d9 	bl	8008dac <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 80069fa:	1d3a      	adds	r2, r7, #4
 80069fc:	f107 0314 	add.w	r3, r7, #20
 8006a00:	4611      	mov	r1, r2
 8006a02:	4618      	mov	r0, r3
 8006a04:	f001 f9e6 	bl	8007dd4 <xTaskCheckForTimeOut>
 8006a08:	4603      	mov	r3, r0
 8006a0a:	2b00      	cmp	r3, #0
 8006a0c:	d124      	bne.n	8006a58 <xQueueGenericSend+0x1ec>
		{
			if( prvIsQueueFull( pxQueue ) != pdFALSE )
 8006a0e:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8006a10:	f000 fc5e 	bl	80072d0 <prvIsQueueFull>
 8006a14:	4603      	mov	r3, r0
 8006a16:	2b00      	cmp	r3, #0
 8006a18:	d018      	beq.n	8006a4c <xQueueGenericSend+0x1e0>
			{
				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
 8006a1a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006a1c:	3310      	adds	r3, #16
 8006a1e:	687a      	ldr	r2, [r7, #4]
 8006a20:	4611      	mov	r1, r2
 8006a22:	4618      	mov	r0, r3
 8006a24:	f001 f90a 	bl	8007c3c <vTaskPlaceOnEventList>
				/* Unlocking the queue means queue events can effect the
				event list.  It is possible that interrupts occurring now
				remove this task from the event list again - but as the
				scheduler is suspended the task will go onto the pending
				ready last instead of the actual ready list. */
				prvUnlockQueue( pxQueue );
 8006a28:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8006a2a:	f000 fbe9 	bl	8007200 <prvUnlockQueue>
				/* Resuming the scheduler will move tasks from the pending
				ready list into the ready list - so it is feasible that this
				task is already in a ready list before it yields - in which
				case the yield will not cause a context switch unless there
				is also a higher priority task in the pending ready list. */
				if( xTaskResumeAll() == pdFALSE )
 8006a2e:	f000 ff37 	bl	80078a0 <xTaskResumeAll>
 8006a32:	4603      	mov	r3, r0
 8006a34:	2b00      	cmp	r3, #0
 8006a36:	f47f af7c 	bne.w	8006932 <xQueueGenericSend+0xc6>
				{
					portYIELD_WITHIN_API();
 8006a3a:	4b0c      	ldr	r3, [pc, #48]	@ (8006a6c <xQueueGenericSend+0x200>)
 8006a3c:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006a40:	601a      	str	r2, [r3, #0]
 8006a42:	f3bf 8f4f 	dsb	sy
 8006a46:	f3bf 8f6f 	isb	sy
 8006a4a:	e772      	b.n	8006932 <xQueueGenericSend+0xc6>
				}
			}
			else
			{
				/* Try again. */
				prvUnlockQueue( pxQueue );
 8006a4c:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8006a4e:	f000 fbd7 	bl	8007200 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 8006a52:	f000 ff25 	bl	80078a0 <xTaskResumeAll>
 8006a56:	e76c      	b.n	8006932 <xQueueGenericSend+0xc6>
			}
		}
		else
		{
			/* The timeout has expired. */
			prvUnlockQueue( pxQueue );
 8006a58:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8006a5a:	f000 fbd1 	bl	8007200 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8006a5e:	f000 ff1f 	bl	80078a0 <xTaskResumeAll>

			traceQUEUE_SEND_FAILED( pxQueue );
			return errQUEUE_FULL;
 8006a62:	2300      	movs	r3, #0
		}
	} /*lint -restore */
}
 8006a64:	4618      	mov	r0, r3
 8006a66:	3738      	adds	r7, #56	@ 0x38
 8006a68:	46bd      	mov	sp, r7
 8006a6a:	bd80      	pop	{r7, pc}
 8006a6c:	e000ed04 	.word	0xe000ed04

08006a70 <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
 8006a70:	b580      	push	{r7, lr}
 8006a72:	b090      	sub	sp, #64	@ 0x40
 8006a74:	af00      	add	r7, sp, #0
 8006a76:	60f8      	str	r0, [r7, #12]
 8006a78:	60b9      	str	r1, [r7, #8]
 8006a7a:	607a      	str	r2, [r7, #4]
 8006a7c:	603b      	str	r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 8006a7e:	68fb      	ldr	r3, [r7, #12]
 8006a80:	63bb      	str	r3, [r7, #56]	@ 0x38

	configASSERT( pxQueue );
 8006a82:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006a84:	2b00      	cmp	r3, #0
 8006a86:	d10b      	bne.n	8006aa0 <xQueueGenericSendFromISR+0x30>
	__asm volatile
 8006a88:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006a8c:	f383 8811 	msr	BASEPRI, r3
 8006a90:	f3bf 8f6f 	isb	sy
 8006a94:	f3bf 8f4f 	dsb	sy
 8006a98:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 8006a9a:	bf00      	nop
 8006a9c:	bf00      	nop
 8006a9e:	e7fd      	b.n	8006a9c <xQueueGenericSendFromISR+0x2c>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8006aa0:	68bb      	ldr	r3, [r7, #8]
 8006aa2:	2b00      	cmp	r3, #0
 8006aa4:	d103      	bne.n	8006aae <xQueueGenericSendFromISR+0x3e>
 8006aa6:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006aa8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8006aaa:	2b00      	cmp	r3, #0
 8006aac:	d101      	bne.n	8006ab2 <xQueueGenericSendFromISR+0x42>
 8006aae:	2301      	movs	r3, #1
 8006ab0:	e000      	b.n	8006ab4 <xQueueGenericSendFromISR+0x44>
 8006ab2:	2300      	movs	r3, #0
 8006ab4:	2b00      	cmp	r3, #0
 8006ab6:	d10b      	bne.n	8006ad0 <xQueueGenericSendFromISR+0x60>
	__asm volatile
 8006ab8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006abc:	f383 8811 	msr	BASEPRI, r3
 8006ac0:	f3bf 8f6f 	isb	sy
 8006ac4:	f3bf 8f4f 	dsb	sy
 8006ac8:	627b      	str	r3, [r7, #36]	@ 0x24
}
 8006aca:	bf00      	nop
 8006acc:	bf00      	nop
 8006ace:	e7fd      	b.n	8006acc <xQueueGenericSendFromISR+0x5c>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 8006ad0:	683b      	ldr	r3, [r7, #0]
 8006ad2:	2b02      	cmp	r3, #2
 8006ad4:	d103      	bne.n	8006ade <xQueueGenericSendFromISR+0x6e>
 8006ad6:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006ad8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8006ada:	2b01      	cmp	r3, #1
 8006adc:	d101      	bne.n	8006ae2 <xQueueGenericSendFromISR+0x72>
 8006ade:	2301      	movs	r3, #1
 8006ae0:	e000      	b.n	8006ae4 <xQueueGenericSendFromISR+0x74>
 8006ae2:	2300      	movs	r3, #0
 8006ae4:	2b00      	cmp	r3, #0
 8006ae6:	d10b      	bne.n	8006b00 <xQueueGenericSendFromISR+0x90>
	__asm volatile
 8006ae8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006aec:	f383 8811 	msr	BASEPRI, r3
 8006af0:	f3bf 8f6f 	isb	sy
 8006af4:	f3bf 8f4f 	dsb	sy
 8006af8:	623b      	str	r3, [r7, #32]
}
 8006afa:	bf00      	nop
 8006afc:	bf00      	nop
 8006afe:	e7fd      	b.n	8006afc <xQueueGenericSendFromISR+0x8c>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 8006b00:	f002 fa02 	bl	8008f08 <vPortValidateInterruptPriority>

portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;

	__asm volatile
 8006b04:	f3ef 8211 	mrs	r2, BASEPRI
 8006b08:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006b0c:	f383 8811 	msr	BASEPRI, r3
 8006b10:	f3bf 8f6f 	isb	sy
 8006b14:	f3bf 8f4f 	dsb	sy
 8006b18:	61fa      	str	r2, [r7, #28]
 8006b1a:	61bb      	str	r3, [r7, #24]
		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);

	/* This return will not be reached but is necessary to prevent compiler
	warnings. */
	return ulOriginalBASEPRI;
 8006b1c:	69fb      	ldr	r3, [r7, #28]
	/* Similar to xQueueGenericSend, except without blocking if there is no room
	in the queue.  Also don't directly wake a task that was blocked on a queue
	read, instead return a flag to say whether a context switch is required or
	not (i.e. has a task with a higher priority than us been woken by this
	post). */
	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8006b1e:	637b      	str	r3, [r7, #52]	@ 0x34
	{
		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 8006b20:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006b22:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8006b24:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006b26:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8006b28:	429a      	cmp	r2, r3
 8006b2a:	d302      	bcc.n	8006b32 <xQueueGenericSendFromISR+0xc2>
 8006b2c:	683b      	ldr	r3, [r7, #0]
 8006b2e:	2b02      	cmp	r3, #2
 8006b30:	d12f      	bne.n	8006b92 <xQueueGenericSendFromISR+0x122>
		{
			const int8_t cTxLock = pxQueue->cTxLock;
 8006b32:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006b34:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8006b38:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
 8006b3c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006b3e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8006b40:	62fb      	str	r3, [r7, #44]	@ 0x2c
			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
			in a task disinheriting a priority and prvCopyDataToQueue() can be
			called here even though the disinherit function does not check if
			the scheduler is suspended before accessing the ready lists. */
			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 8006b42:	683a      	ldr	r2, [r7, #0]
 8006b44:	68b9      	ldr	r1, [r7, #8]
 8006b46:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
 8006b48:	f000 faca 	bl	80070e0 <prvCopyDataToQueue>

			/* The event list is not altered if the queue is locked.  This will
			be done when the queue is unlocked later. */
			if( cTxLock == queueUNLOCKED )
 8006b4c:	f997 3033 	ldrsb.w	r3, [r7, #51]	@ 0x33
 8006b50:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006b54:	d112      	bne.n	8006b7c <xQueueGenericSendFromISR+0x10c>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8006b56:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006b58:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8006b5a:	2b00      	cmp	r3, #0
 8006b5c:	d016      	beq.n	8006b8c <xQueueGenericSendFromISR+0x11c>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8006b5e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006b60:	3324      	adds	r3, #36	@ 0x24
 8006b62:	4618      	mov	r0, r3
 8006b64:	f001 f8bc 	bl	8007ce0 <xTaskRemoveFromEventList>
 8006b68:	4603      	mov	r3, r0
 8006b6a:	2b00      	cmp	r3, #0
 8006b6c:	d00e      	beq.n	8006b8c <xQueueGenericSendFromISR+0x11c>
						{
							/* The task waiting has a higher priority so record that a
							context	switch is required. */
							if( pxHigherPriorityTaskWoken != NULL )
 8006b6e:	687b      	ldr	r3, [r7, #4]
 8006b70:	2b00      	cmp	r3, #0
 8006b72:	d00b      	beq.n	8006b8c <xQueueGenericSendFromISR+0x11c>
							{
								*pxHigherPriorityTaskWoken = pdTRUE;
 8006b74:	687b      	ldr	r3, [r7, #4]
 8006b76:	2201      	movs	r2, #1
 8006b78:	601a      	str	r2, [r3, #0]
 8006b7a:	e007      	b.n	8006b8c <xQueueGenericSendFromISR+0x11c>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was posted while it was locked. */
				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
 8006b7c:	f897 3033 	ldrb.w	r3, [r7, #51]	@ 0x33
 8006b80:	3301      	adds	r3, #1
 8006b82:	b2db      	uxtb	r3, r3
 8006b84:	b25a      	sxtb	r2, r3
 8006b86:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8006b88:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
			}

			xReturn = pdPASS;
 8006b8c:	2301      	movs	r3, #1
 8006b8e:	63fb      	str	r3, [r7, #60]	@ 0x3c
		{
 8006b90:	e001      	b.n	8006b96 <xQueueGenericSendFromISR+0x126>
		}
		else
		{
			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
			xReturn = errQUEUE_FULL;
 8006b92:	2300      	movs	r3, #0
 8006b94:	63fb      	str	r3, [r7, #60]	@ 0x3c
 8006b96:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8006b98:	617b      	str	r3, [r7, #20]
}
/*-----------------------------------------------------------*/

portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
	__asm volatile
 8006b9a:	697b      	ldr	r3, [r7, #20]
 8006b9c:	f383 8811 	msr	BASEPRI, r3
	(
		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
	);
}
 8006ba0:	bf00      	nop
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 8006ba2:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
}
 8006ba4:	4618      	mov	r0, r3
 8006ba6:	3740      	adds	r7, #64	@ 0x40
 8006ba8:	46bd      	mov	sp, r7
 8006baa:	bd80      	pop	{r7, pc}

08006bac <xQueueGiveFromISR>:
/*-----------------------------------------------------------*/

BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
{
 8006bac:	b580      	push	{r7, lr}
 8006bae:	b08e      	sub	sp, #56	@ 0x38
 8006bb0:	af00      	add	r7, sp, #0
 8006bb2:	6078      	str	r0, [r7, #4]
 8006bb4:	6039      	str	r1, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 8006bb6:	687b      	ldr	r3, [r7, #4]
 8006bb8:	633b      	str	r3, [r7, #48]	@ 0x30
	item size is 0.  Don't directly wake a task that was blocked on a queue
	read, instead return a flag to say whether a context switch is required or
	not (i.e. has a task with a higher priority than us been woken by this
	post). */

	configASSERT( pxQueue );
 8006bba:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006bbc:	2b00      	cmp	r3, #0
 8006bbe:	d10b      	bne.n	8006bd8 <xQueueGiveFromISR+0x2c>
	__asm volatile
 8006bc0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006bc4:	f383 8811 	msr	BASEPRI, r3
 8006bc8:	f3bf 8f6f 	isb	sy
 8006bcc:	f3bf 8f4f 	dsb	sy
 8006bd0:	623b      	str	r3, [r7, #32]
}
 8006bd2:	bf00      	nop
 8006bd4:	bf00      	nop
 8006bd6:	e7fd      	b.n	8006bd4 <xQueueGiveFromISR+0x28>

	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
	if the item size is not 0. */
	configASSERT( pxQueue->uxItemSize == 0 );
 8006bd8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006bda:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8006bdc:	2b00      	cmp	r3, #0
 8006bde:	d00b      	beq.n	8006bf8 <xQueueGiveFromISR+0x4c>
	__asm volatile
 8006be0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006be4:	f383 8811 	msr	BASEPRI, r3
 8006be8:	f3bf 8f6f 	isb	sy
 8006bec:	f3bf 8f4f 	dsb	sy
 8006bf0:	61fb      	str	r3, [r7, #28]
}
 8006bf2:	bf00      	nop
 8006bf4:	bf00      	nop
 8006bf6:	e7fd      	b.n	8006bf4 <xQueueGiveFromISR+0x48>

	/* Normally a mutex would not be given from an interrupt, especially if
	there is a mutex holder, as priority inheritance makes no sense for an
	interrupts, only tasks. */
	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
 8006bf8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006bfa:	681b      	ldr	r3, [r3, #0]
 8006bfc:	2b00      	cmp	r3, #0
 8006bfe:	d103      	bne.n	8006c08 <xQueueGiveFromISR+0x5c>
 8006c00:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006c02:	689b      	ldr	r3, [r3, #8]
 8006c04:	2b00      	cmp	r3, #0
 8006c06:	d101      	bne.n	8006c0c <xQueueGiveFromISR+0x60>
 8006c08:	2301      	movs	r3, #1
 8006c0a:	e000      	b.n	8006c0e <xQueueGiveFromISR+0x62>
 8006c0c:	2300      	movs	r3, #0
 8006c0e:	2b00      	cmp	r3, #0
 8006c10:	d10b      	bne.n	8006c2a <xQueueGiveFromISR+0x7e>
	__asm volatile
 8006c12:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006c16:	f383 8811 	msr	BASEPRI, r3
 8006c1a:	f3bf 8f6f 	isb	sy
 8006c1e:	f3bf 8f4f 	dsb	sy
 8006c22:	61bb      	str	r3, [r7, #24]
}
 8006c24:	bf00      	nop
 8006c26:	bf00      	nop
 8006c28:	e7fd      	b.n	8006c26 <xQueueGiveFromISR+0x7a>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 8006c2a:	f002 f96d 	bl	8008f08 <vPortValidateInterruptPriority>
	__asm volatile
 8006c2e:	f3ef 8211 	mrs	r2, BASEPRI
 8006c32:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006c36:	f383 8811 	msr	BASEPRI, r3
 8006c3a:	f3bf 8f6f 	isb	sy
 8006c3e:	f3bf 8f4f 	dsb	sy
 8006c42:	617a      	str	r2, [r7, #20]
 8006c44:	613b      	str	r3, [r7, #16]
	return ulOriginalBASEPRI;
 8006c46:	697b      	ldr	r3, [r7, #20]

	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8006c48:	62fb      	str	r3, [r7, #44]	@ 0x2c
	{
		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8006c4a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006c4c:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8006c4e:	62bb      	str	r3, [r7, #40]	@ 0x28

		/* When the queue is used to implement a semaphore no data is ever
		moved through the queue but it is still valid to see if the queue 'has
		space'. */
		if( uxMessagesWaiting < pxQueue->uxLength )
 8006c50:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006c52:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8006c54:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 8006c56:	429a      	cmp	r2, r3
 8006c58:	d22b      	bcs.n	8006cb2 <xQueueGiveFromISR+0x106>
		{
			const int8_t cTxLock = pxQueue->cTxLock;
 8006c5a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006c5c:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8006c60:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
			holder - and if there is a mutex holder then the mutex cannot be
			given from an ISR.  As this is the ISR version of the function it
			can be assumed there is no mutex holder and no need to determine if
			priority disinheritance is needed.  Simply increase the count of
			messages (semaphores) available. */
			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 8006c64:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006c66:	1c5a      	adds	r2, r3, #1
 8006c68:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006c6a:	639a      	str	r2, [r3, #56]	@ 0x38

			/* The event list is not altered if the queue is locked.  This will
			be done when the queue is unlocked later. */
			if( cTxLock == queueUNLOCKED )
 8006c6c:	f997 3027 	ldrsb.w	r3, [r7, #39]	@ 0x27
 8006c70:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006c74:	d112      	bne.n	8006c9c <xQueueGiveFromISR+0xf0>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8006c76:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006c78:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8006c7a:	2b00      	cmp	r3, #0
 8006c7c:	d016      	beq.n	8006cac <xQueueGiveFromISR+0x100>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8006c7e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006c80:	3324      	adds	r3, #36	@ 0x24
 8006c82:	4618      	mov	r0, r3
 8006c84:	f001 f82c 	bl	8007ce0 <xTaskRemoveFromEventList>
 8006c88:	4603      	mov	r3, r0
 8006c8a:	2b00      	cmp	r3, #0
 8006c8c:	d00e      	beq.n	8006cac <xQueueGiveFromISR+0x100>
						{
							/* The task waiting has a higher priority so record that a
							context	switch is required. */
							if( pxHigherPriorityTaskWoken != NULL )
 8006c8e:	683b      	ldr	r3, [r7, #0]
 8006c90:	2b00      	cmp	r3, #0
 8006c92:	d00b      	beq.n	8006cac <xQueueGiveFromISR+0x100>
							{
								*pxHigherPriorityTaskWoken = pdTRUE;
 8006c94:	683b      	ldr	r3, [r7, #0]
 8006c96:	2201      	movs	r2, #1
 8006c98:	601a      	str	r2, [r3, #0]
 8006c9a:	e007      	b.n	8006cac <xQueueGiveFromISR+0x100>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was posted while it was locked. */
				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
 8006c9c:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8006ca0:	3301      	adds	r3, #1
 8006ca2:	b2db      	uxtb	r3, r3
 8006ca4:	b25a      	sxtb	r2, r3
 8006ca6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006ca8:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
			}

			xReturn = pdPASS;
 8006cac:	2301      	movs	r3, #1
 8006cae:	637b      	str	r3, [r7, #52]	@ 0x34
 8006cb0:	e001      	b.n	8006cb6 <xQueueGiveFromISR+0x10a>
		}
		else
		{
			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
			xReturn = errQUEUE_FULL;
 8006cb2:	2300      	movs	r3, #0
 8006cb4:	637b      	str	r3, [r7, #52]	@ 0x34
 8006cb6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006cb8:	60fb      	str	r3, [r7, #12]
	__asm volatile
 8006cba:	68fb      	ldr	r3, [r7, #12]
 8006cbc:	f383 8811 	msr	BASEPRI, r3
}
 8006cc0:	bf00      	nop
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 8006cc2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
}
 8006cc4:	4618      	mov	r0, r3
 8006cc6:	3738      	adds	r7, #56	@ 0x38
 8006cc8:	46bd      	mov	sp, r7
 8006cca:	bd80      	pop	{r7, pc}

08006ccc <xQueueReceive>:
/*-----------------------------------------------------------*/

BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
 8006ccc:	b580      	push	{r7, lr}
 8006cce:	b08c      	sub	sp, #48	@ 0x30
 8006cd0:	af00      	add	r7, sp, #0
 8006cd2:	60f8      	str	r0, [r7, #12]
 8006cd4:	60b9      	str	r1, [r7, #8]
 8006cd6:	607a      	str	r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
 8006cd8:	2300      	movs	r3, #0
 8006cda:	62fb      	str	r3, [r7, #44]	@ 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 8006cdc:	68fb      	ldr	r3, [r7, #12]
 8006cde:	62bb      	str	r3, [r7, #40]	@ 0x28

	/* Check the pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 8006ce0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006ce2:	2b00      	cmp	r3, #0
 8006ce4:	d10b      	bne.n	8006cfe <xQueueReceive+0x32>
	__asm volatile
 8006ce6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006cea:	f383 8811 	msr	BASEPRI, r3
 8006cee:	f3bf 8f6f 	isb	sy
 8006cf2:	f3bf 8f4f 	dsb	sy
 8006cf6:	623b      	str	r3, [r7, #32]
}
 8006cf8:	bf00      	nop
 8006cfa:	bf00      	nop
 8006cfc:	e7fd      	b.n	8006cfa <xQueueReceive+0x2e>

	/* The buffer into which data is received can only be NULL if the data size
	is zero (so no data is copied into the buffer. */
	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8006cfe:	68bb      	ldr	r3, [r7, #8]
 8006d00:	2b00      	cmp	r3, #0
 8006d02:	d103      	bne.n	8006d0c <xQueueReceive+0x40>
 8006d04:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006d06:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8006d08:	2b00      	cmp	r3, #0
 8006d0a:	d101      	bne.n	8006d10 <xQueueReceive+0x44>
 8006d0c:	2301      	movs	r3, #1
 8006d0e:	e000      	b.n	8006d12 <xQueueReceive+0x46>
 8006d10:	2300      	movs	r3, #0
 8006d12:	2b00      	cmp	r3, #0
 8006d14:	d10b      	bne.n	8006d2e <xQueueReceive+0x62>
	__asm volatile
 8006d16:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006d1a:	f383 8811 	msr	BASEPRI, r3
 8006d1e:	f3bf 8f6f 	isb	sy
 8006d22:	f3bf 8f4f 	dsb	sy
 8006d26:	61fb      	str	r3, [r7, #28]
}
 8006d28:	bf00      	nop
 8006d2a:	bf00      	nop
 8006d2c:	e7fd      	b.n	8006d2a <xQueueReceive+0x5e>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8006d2e:	f001 f99d 	bl	800806c <xTaskGetSchedulerState>
 8006d32:	4603      	mov	r3, r0
 8006d34:	2b00      	cmp	r3, #0
 8006d36:	d102      	bne.n	8006d3e <xQueueReceive+0x72>
 8006d38:	687b      	ldr	r3, [r7, #4]
 8006d3a:	2b00      	cmp	r3, #0
 8006d3c:	d101      	bne.n	8006d42 <xQueueReceive+0x76>
 8006d3e:	2301      	movs	r3, #1
 8006d40:	e000      	b.n	8006d44 <xQueueReceive+0x78>
 8006d42:	2300      	movs	r3, #0
 8006d44:	2b00      	cmp	r3, #0
 8006d46:	d10b      	bne.n	8006d60 <xQueueReceive+0x94>
	__asm volatile
 8006d48:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006d4c:	f383 8811 	msr	BASEPRI, r3
 8006d50:	f3bf 8f6f 	isb	sy
 8006d54:	f3bf 8f4f 	dsb	sy
 8006d58:	61bb      	str	r3, [r7, #24]
}
 8006d5a:	bf00      	nop
 8006d5c:	bf00      	nop
 8006d5e:	e7fd      	b.n	8006d5c <xQueueReceive+0x90>
	/*lint -save -e904  This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8006d60:	f001 fff2 	bl	8008d48 <vPortEnterCritical>
		{
			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8006d64:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006d66:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8006d68:	627b      	str	r3, [r7, #36]	@ 0x24

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8006d6a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8006d6c:	2b00      	cmp	r3, #0
 8006d6e:	d01f      	beq.n	8006db0 <xQueueReceive+0xe4>
			{
				/* Data available, remove one item. */
				prvCopyDataFromQueue( pxQueue, pvBuffer );
 8006d70:	68b9      	ldr	r1, [r7, #8]
 8006d72:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8006d74:	f000 fa1e 	bl	80071b4 <prvCopyDataFromQueue>
				traceQUEUE_RECEIVE( pxQueue );
				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 8006d78:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8006d7a:	1e5a      	subs	r2, r3, #1
 8006d7c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006d7e:	639a      	str	r2, [r3, #56]	@ 0x38

				/* There is now space in the queue, were any tasks waiting to
				post to the queue?  If so, unblock the highest priority waiting
				task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8006d80:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006d82:	691b      	ldr	r3, [r3, #16]
 8006d84:	2b00      	cmp	r3, #0
 8006d86:	d00f      	beq.n	8006da8 <xQueueReceive+0xdc>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8006d88:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006d8a:	3310      	adds	r3, #16
 8006d8c:	4618      	mov	r0, r3
 8006d8e:	f000 ffa7 	bl	8007ce0 <xTaskRemoveFromEventList>
 8006d92:	4603      	mov	r3, r0
 8006d94:	2b00      	cmp	r3, #0
 8006d96:	d007      	beq.n	8006da8 <xQueueReceive+0xdc>
					{
						queueYIELD_IF_USING_PREEMPTION();
 8006d98:	4b3c      	ldr	r3, [pc, #240]	@ (8006e8c <xQueueReceive+0x1c0>)
 8006d9a:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006d9e:	601a      	str	r2, [r3, #0]
 8006da0:	f3bf 8f4f 	dsb	sy
 8006da4:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 8006da8:	f002 f800 	bl	8008dac <vPortExitCritical>
				return pdPASS;
 8006dac:	2301      	movs	r3, #1
 8006dae:	e069      	b.n	8006e84 <xQueueReceive+0x1b8>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 8006db0:	687b      	ldr	r3, [r7, #4]
 8006db2:	2b00      	cmp	r3, #0
 8006db4:	d103      	bne.n	8006dbe <xQueueReceive+0xf2>
				{
					/* The queue was empty and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 8006db6:	f001 fff9 	bl	8008dac <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 8006dba:	2300      	movs	r3, #0
 8006dbc:	e062      	b.n	8006e84 <xQueueReceive+0x1b8>
				}
				else if( xEntryTimeSet == pdFALSE )
 8006dbe:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006dc0:	2b00      	cmp	r3, #0
 8006dc2:	d106      	bne.n	8006dd2 <xQueueReceive+0x106>
				{
					/* The queue was empty and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 8006dc4:	f107 0310 	add.w	r3, r7, #16
 8006dc8:	4618      	mov	r0, r3
 8006dca:	f000 ffed 	bl	8007da8 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 8006dce:	2301      	movs	r3, #1
 8006dd0:	62fb      	str	r3, [r7, #44]	@ 0x2c
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 8006dd2:	f001 ffeb 	bl	8008dac <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 8006dd6:	f000 fd55 	bl	8007884 <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 8006dda:	f001 ffb5 	bl	8008d48 <vPortEnterCritical>
 8006dde:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006de0:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8006de4:	b25b      	sxtb	r3, r3
 8006de6:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006dea:	d103      	bne.n	8006df4 <xQueueReceive+0x128>
 8006dec:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006dee:	2200      	movs	r2, #0
 8006df0:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8006df4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006df6:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8006dfa:	b25b      	sxtb	r3, r3
 8006dfc:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006e00:	d103      	bne.n	8006e0a <xQueueReceive+0x13e>
 8006e02:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006e04:	2200      	movs	r2, #0
 8006e06:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8006e0a:	f001 ffcf 	bl	8008dac <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 8006e0e:	1d3a      	adds	r2, r7, #4
 8006e10:	f107 0310 	add.w	r3, r7, #16
 8006e14:	4611      	mov	r1, r2
 8006e16:	4618      	mov	r0, r3
 8006e18:	f000 ffdc 	bl	8007dd4 <xTaskCheckForTimeOut>
 8006e1c:	4603      	mov	r3, r0
 8006e1e:	2b00      	cmp	r3, #0
 8006e20:	d123      	bne.n	8006e6a <xQueueReceive+0x19e>
		{
			/* The timeout has not expired.  If the queue is still empty place
			the task on the list of tasks waiting to receive from the queue. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8006e22:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8006e24:	f000 fa3e 	bl	80072a4 <prvIsQueueEmpty>
 8006e28:	4603      	mov	r3, r0
 8006e2a:	2b00      	cmp	r3, #0
 8006e2c:	d017      	beq.n	8006e5e <xQueueReceive+0x192>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 8006e2e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006e30:	3324      	adds	r3, #36	@ 0x24
 8006e32:	687a      	ldr	r2, [r7, #4]
 8006e34:	4611      	mov	r1, r2
 8006e36:	4618      	mov	r0, r3
 8006e38:	f000 ff00 	bl	8007c3c <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8006e3c:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8006e3e:	f000 f9df 	bl	8007200 <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 8006e42:	f000 fd2d 	bl	80078a0 <xTaskResumeAll>
 8006e46:	4603      	mov	r3, r0
 8006e48:	2b00      	cmp	r3, #0
 8006e4a:	d189      	bne.n	8006d60 <xQueueReceive+0x94>
				{
					portYIELD_WITHIN_API();
 8006e4c:	4b0f      	ldr	r3, [pc, #60]	@ (8006e8c <xQueueReceive+0x1c0>)
 8006e4e:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006e52:	601a      	str	r2, [r3, #0]
 8006e54:	f3bf 8f4f 	dsb	sy
 8006e58:	f3bf 8f6f 	isb	sy
 8006e5c:	e780      	b.n	8006d60 <xQueueReceive+0x94>
			}
			else
			{
				/* The queue contains data again.  Loop back to try and read the
				data. */
				prvUnlockQueue( pxQueue );
 8006e5e:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8006e60:	f000 f9ce 	bl	8007200 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 8006e64:	f000 fd1c 	bl	80078a0 <xTaskResumeAll>
 8006e68:	e77a      	b.n	8006d60 <xQueueReceive+0x94>
		}
		else
		{
			/* Timed out.  If there is no data in the queue exit, otherwise loop
			back and attempt to read the data. */
			prvUnlockQueue( pxQueue );
 8006e6a:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8006e6c:	f000 f9c8 	bl	8007200 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8006e70:	f000 fd16 	bl	80078a0 <xTaskResumeAll>

			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8006e74:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8006e76:	f000 fa15 	bl	80072a4 <prvIsQueueEmpty>
 8006e7a:	4603      	mov	r3, r0
 8006e7c:	2b00      	cmp	r3, #0
 8006e7e:	f43f af6f 	beq.w	8006d60 <xQueueReceive+0x94>
			{
				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 8006e82:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 8006e84:	4618      	mov	r0, r3
 8006e86:	3730      	adds	r7, #48	@ 0x30
 8006e88:	46bd      	mov	sp, r7
 8006e8a:	bd80      	pop	{r7, pc}
 8006e8c:	e000ed04 	.word	0xe000ed04

08006e90 <xQueueSemaphoreTake>:
/*-----------------------------------------------------------*/

BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
{
 8006e90:	b580      	push	{r7, lr}
 8006e92:	b08e      	sub	sp, #56	@ 0x38
 8006e94:	af00      	add	r7, sp, #0
 8006e96:	6078      	str	r0, [r7, #4]
 8006e98:	6039      	str	r1, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE;
 8006e9a:	2300      	movs	r3, #0
 8006e9c:	637b      	str	r3, [r7, #52]	@ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 8006e9e:	687b      	ldr	r3, [r7, #4]
 8006ea0:	62fb      	str	r3, [r7, #44]	@ 0x2c

#if( configUSE_MUTEXES == 1 )
	BaseType_t xInheritanceOccurred = pdFALSE;
 8006ea2:	2300      	movs	r3, #0
 8006ea4:	633b      	str	r3, [r7, #48]	@ 0x30
#endif

	/* Check the queue pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 8006ea6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006ea8:	2b00      	cmp	r3, #0
 8006eaa:	d10b      	bne.n	8006ec4 <xQueueSemaphoreTake+0x34>
	__asm volatile
 8006eac:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006eb0:	f383 8811 	msr	BASEPRI, r3
 8006eb4:	f3bf 8f6f 	isb	sy
 8006eb8:	f3bf 8f4f 	dsb	sy
 8006ebc:	623b      	str	r3, [r7, #32]
}
 8006ebe:	bf00      	nop
 8006ec0:	bf00      	nop
 8006ec2:	e7fd      	b.n	8006ec0 <xQueueSemaphoreTake+0x30>

	/* Check this really is a semaphore, in which case the item size will be
	0. */
	configASSERT( pxQueue->uxItemSize == 0 );
 8006ec4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006ec6:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8006ec8:	2b00      	cmp	r3, #0
 8006eca:	d00b      	beq.n	8006ee4 <xQueueSemaphoreTake+0x54>
	__asm volatile
 8006ecc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006ed0:	f383 8811 	msr	BASEPRI, r3
 8006ed4:	f3bf 8f6f 	isb	sy
 8006ed8:	f3bf 8f4f 	dsb	sy
 8006edc:	61fb      	str	r3, [r7, #28]
}
 8006ede:	bf00      	nop
 8006ee0:	bf00      	nop
 8006ee2:	e7fd      	b.n	8006ee0 <xQueueSemaphoreTake+0x50>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8006ee4:	f001 f8c2 	bl	800806c <xTaskGetSchedulerState>
 8006ee8:	4603      	mov	r3, r0
 8006eea:	2b00      	cmp	r3, #0
 8006eec:	d102      	bne.n	8006ef4 <xQueueSemaphoreTake+0x64>
 8006eee:	683b      	ldr	r3, [r7, #0]
 8006ef0:	2b00      	cmp	r3, #0
 8006ef2:	d101      	bne.n	8006ef8 <xQueueSemaphoreTake+0x68>
 8006ef4:	2301      	movs	r3, #1
 8006ef6:	e000      	b.n	8006efa <xQueueSemaphoreTake+0x6a>
 8006ef8:	2300      	movs	r3, #0
 8006efa:	2b00      	cmp	r3, #0
 8006efc:	d10b      	bne.n	8006f16 <xQueueSemaphoreTake+0x86>
	__asm volatile
 8006efe:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006f02:	f383 8811 	msr	BASEPRI, r3
 8006f06:	f3bf 8f6f 	isb	sy
 8006f0a:	f3bf 8f4f 	dsb	sy
 8006f0e:	61bb      	str	r3, [r7, #24]
}
 8006f10:	bf00      	nop
 8006f12:	bf00      	nop
 8006f14:	e7fd      	b.n	8006f12 <xQueueSemaphoreTake+0x82>
	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
	statements within the function itself.  This is done in the interest
	of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8006f16:	f001 ff17 	bl	8008d48 <vPortEnterCritical>
		{
			/* Semaphores are queues with an item size of 0, and where the
			number of messages in the queue is the semaphore's count value. */
			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
 8006f1a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006f1c:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8006f1e:	62bb      	str	r3, [r7, #40]	@ 0x28

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
 8006f20:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006f22:	2b00      	cmp	r3, #0
 8006f24:	d024      	beq.n	8006f70 <xQueueSemaphoreTake+0xe0>
			{
				traceQUEUE_RECEIVE( pxQueue );

				/* Semaphores are queues with a data size of zero and where the
				messages waiting is the semaphore's count.  Reduce the count. */
				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
 8006f26:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8006f28:	1e5a      	subs	r2, r3, #1
 8006f2a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006f2c:	639a      	str	r2, [r3, #56]	@ 0x38

				#if ( configUSE_MUTEXES == 1 )
				{
					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 8006f2e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006f30:	681b      	ldr	r3, [r3, #0]
 8006f32:	2b00      	cmp	r3, #0
 8006f34:	d104      	bne.n	8006f40 <xQueueSemaphoreTake+0xb0>
					{
						/* Record the information required to implement
						priority inheritance should it become necessary. */
						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
 8006f36:	f001 fa13 	bl	8008360 <pvTaskIncrementMutexHeldCount>
 8006f3a:	4602      	mov	r2, r0
 8006f3c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006f3e:	609a      	str	r2, [r3, #8]
				}
				#endif /* configUSE_MUTEXES */

				/* Check to see if other tasks are blocked waiting to give the
				semaphore, and if so, unblock the highest priority such task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8006f40:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006f42:	691b      	ldr	r3, [r3, #16]
 8006f44:	2b00      	cmp	r3, #0
 8006f46:	d00f      	beq.n	8006f68 <xQueueSemaphoreTake+0xd8>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8006f48:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006f4a:	3310      	adds	r3, #16
 8006f4c:	4618      	mov	r0, r3
 8006f4e:	f000 fec7 	bl	8007ce0 <xTaskRemoveFromEventList>
 8006f52:	4603      	mov	r3, r0
 8006f54:	2b00      	cmp	r3, #0
 8006f56:	d007      	beq.n	8006f68 <xQueueSemaphoreTake+0xd8>
					{
						queueYIELD_IF_USING_PREEMPTION();
 8006f58:	4b54      	ldr	r3, [pc, #336]	@ (80070ac <xQueueSemaphoreTake+0x21c>)
 8006f5a:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8006f5e:	601a      	str	r2, [r3, #0]
 8006f60:	f3bf 8f4f 	dsb	sy
 8006f64:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 8006f68:	f001 ff20 	bl	8008dac <vPortExitCritical>
				return pdPASS;
 8006f6c:	2301      	movs	r3, #1
 8006f6e:	e098      	b.n	80070a2 <xQueueSemaphoreTake+0x212>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 8006f70:	683b      	ldr	r3, [r7, #0]
 8006f72:	2b00      	cmp	r3, #0
 8006f74:	d112      	bne.n	8006f9c <xQueueSemaphoreTake+0x10c>
					/* For inheritance to have occurred there must have been an
					initial timeout, and an adjusted timeout cannot become 0, as
					if it were 0 the function would have exited. */
					#if( configUSE_MUTEXES == 1 )
					{
						configASSERT( xInheritanceOccurred == pdFALSE );
 8006f76:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006f78:	2b00      	cmp	r3, #0
 8006f7a:	d00b      	beq.n	8006f94 <xQueueSemaphoreTake+0x104>
	__asm volatile
 8006f7c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8006f80:	f383 8811 	msr	BASEPRI, r3
 8006f84:	f3bf 8f6f 	isb	sy
 8006f88:	f3bf 8f4f 	dsb	sy
 8006f8c:	617b      	str	r3, [r7, #20]
}
 8006f8e:	bf00      	nop
 8006f90:	bf00      	nop
 8006f92:	e7fd      	b.n	8006f90 <xQueueSemaphoreTake+0x100>
					}
					#endif /* configUSE_MUTEXES */

					/* The semaphore count was 0 and no block time is specified
					(or the block time has expired) so exit now. */
					taskEXIT_CRITICAL();
 8006f94:	f001 ff0a 	bl	8008dac <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 8006f98:	2300      	movs	r3, #0
 8006f9a:	e082      	b.n	80070a2 <xQueueSemaphoreTake+0x212>
				}
				else if( xEntryTimeSet == pdFALSE )
 8006f9c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8006f9e:	2b00      	cmp	r3, #0
 8006fa0:	d106      	bne.n	8006fb0 <xQueueSemaphoreTake+0x120>
				{
					/* The semaphore count was 0 and a block time was specified
					so configure the timeout structure ready to block. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 8006fa2:	f107 030c 	add.w	r3, r7, #12
 8006fa6:	4618      	mov	r0, r3
 8006fa8:	f000 fefe 	bl	8007da8 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 8006fac:	2301      	movs	r3, #1
 8006fae:	637b      	str	r3, [r7, #52]	@ 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 8006fb0:	f001 fefc 	bl	8008dac <vPortExitCritical>

		/* Interrupts and other tasks can give to and take from the semaphore
		now the critical section has been exited. */

		vTaskSuspendAll();
 8006fb4:	f000 fc66 	bl	8007884 <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 8006fb8:	f001 fec6 	bl	8008d48 <vPortEnterCritical>
 8006fbc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006fbe:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8006fc2:	b25b      	sxtb	r3, r3
 8006fc4:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006fc8:	d103      	bne.n	8006fd2 <xQueueSemaphoreTake+0x142>
 8006fca:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006fcc:	2200      	movs	r2, #0
 8006fce:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8006fd2:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006fd4:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8006fd8:	b25b      	sxtb	r3, r3
 8006fda:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8006fde:	d103      	bne.n	8006fe8 <xQueueSemaphoreTake+0x158>
 8006fe0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8006fe2:	2200      	movs	r2, #0
 8006fe4:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8006fe8:	f001 fee0 	bl	8008dac <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 8006fec:	463a      	mov	r2, r7
 8006fee:	f107 030c 	add.w	r3, r7, #12
 8006ff2:	4611      	mov	r1, r2
 8006ff4:	4618      	mov	r0, r3
 8006ff6:	f000 feed 	bl	8007dd4 <xTaskCheckForTimeOut>
 8006ffa:	4603      	mov	r3, r0
 8006ffc:	2b00      	cmp	r3, #0
 8006ffe:	d132      	bne.n	8007066 <xQueueSemaphoreTake+0x1d6>
		{
			/* A block time is specified and not expired.  If the semaphore
			count is 0 then enter the Blocked state to wait for a semaphore to
			become available.  As semaphores are implemented with queues the
			queue being empty is equivalent to the semaphore count being 0. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8007000:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8007002:	f000 f94f 	bl	80072a4 <prvIsQueueEmpty>
 8007006:	4603      	mov	r3, r0
 8007008:	2b00      	cmp	r3, #0
 800700a:	d026      	beq.n	800705a <xQueueSemaphoreTake+0x1ca>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );

				#if ( configUSE_MUTEXES == 1 )
				{
					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 800700c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800700e:	681b      	ldr	r3, [r3, #0]
 8007010:	2b00      	cmp	r3, #0
 8007012:	d109      	bne.n	8007028 <xQueueSemaphoreTake+0x198>
					{
						taskENTER_CRITICAL();
 8007014:	f001 fe98 	bl	8008d48 <vPortEnterCritical>
						{
							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
 8007018:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800701a:	689b      	ldr	r3, [r3, #8]
 800701c:	4618      	mov	r0, r3
 800701e:	f001 f843 	bl	80080a8 <xTaskPriorityInherit>
 8007022:	6338      	str	r0, [r7, #48]	@ 0x30
						}
						taskEXIT_CRITICAL();
 8007024:	f001 fec2 	bl	8008dac <vPortExitCritical>
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif

				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 8007028:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800702a:	3324      	adds	r3, #36	@ 0x24
 800702c:	683a      	ldr	r2, [r7, #0]
 800702e:	4611      	mov	r1, r2
 8007030:	4618      	mov	r0, r3
 8007032:	f000 fe03 	bl	8007c3c <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8007036:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8007038:	f000 f8e2 	bl	8007200 <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 800703c:	f000 fc30 	bl	80078a0 <xTaskResumeAll>
 8007040:	4603      	mov	r3, r0
 8007042:	2b00      	cmp	r3, #0
 8007044:	f47f af67 	bne.w	8006f16 <xQueueSemaphoreTake+0x86>
				{
					portYIELD_WITHIN_API();
 8007048:	4b18      	ldr	r3, [pc, #96]	@ (80070ac <xQueueSemaphoreTake+0x21c>)
 800704a:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 800704e:	601a      	str	r2, [r3, #0]
 8007050:	f3bf 8f4f 	dsb	sy
 8007054:	f3bf 8f6f 	isb	sy
 8007058:	e75d      	b.n	8006f16 <xQueueSemaphoreTake+0x86>
			}
			else
			{
				/* There was no timeout and the semaphore count was not 0, so
				attempt to take the semaphore again. */
				prvUnlockQueue( pxQueue );
 800705a:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 800705c:	f000 f8d0 	bl	8007200 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 8007060:	f000 fc1e 	bl	80078a0 <xTaskResumeAll>
 8007064:	e757      	b.n	8006f16 <xQueueSemaphoreTake+0x86>
			}
		}
		else
		{
			/* Timed out. */
			prvUnlockQueue( pxQueue );
 8007066:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8007068:	f000 f8ca 	bl	8007200 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 800706c:	f000 fc18 	bl	80078a0 <xTaskResumeAll>

			/* If the semaphore count is 0 exit now as the timeout has
			expired.  Otherwise return to attempt to take the semaphore that is
			known to be available.  As semaphores are implemented by queues the
			queue being empty is equivalent to the semaphore count being 0. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8007070:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8007072:	f000 f917 	bl	80072a4 <prvIsQueueEmpty>
 8007076:	4603      	mov	r3, r0
 8007078:	2b00      	cmp	r3, #0
 800707a:	f43f af4c 	beq.w	8006f16 <xQueueSemaphoreTake+0x86>
				#if ( configUSE_MUTEXES == 1 )
				{
					/* xInheritanceOccurred could only have be set if
					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
					test the mutex type again to check it is actually a mutex. */
					if( xInheritanceOccurred != pdFALSE )
 800707e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007080:	2b00      	cmp	r3, #0
 8007082:	d00d      	beq.n	80070a0 <xQueueSemaphoreTake+0x210>
					{
						taskENTER_CRITICAL();
 8007084:	f001 fe60 	bl	8008d48 <vPortEnterCritical>
							/* This task blocking on the mutex caused another
							task to inherit this task's priority.  Now this task
							has timed out the priority should be disinherited
							again, but only as low as the next highest priority
							task that is waiting for the same mutex. */
							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
 8007088:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 800708a:	f000 f811 	bl	80070b0 <prvGetDisinheritPriorityAfterTimeout>
 800708e:	6278      	str	r0, [r7, #36]	@ 0x24
							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
 8007090:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8007092:	689b      	ldr	r3, [r3, #8]
 8007094:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 8007096:	4618      	mov	r0, r3
 8007098:	f001 f8de 	bl	8008258 <vTaskPriorityDisinheritAfterTimeout>
						}
						taskEXIT_CRITICAL();
 800709c:	f001 fe86 	bl	8008dac <vPortExitCritical>
					}
				}
				#endif /* configUSE_MUTEXES */

				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 80070a0:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 80070a2:	4618      	mov	r0, r3
 80070a4:	3738      	adds	r7, #56	@ 0x38
 80070a6:	46bd      	mov	sp, r7
 80070a8:	bd80      	pop	{r7, pc}
 80070aa:	bf00      	nop
 80070ac:	e000ed04 	.word	0xe000ed04

080070b0 <prvGetDisinheritPriorityAfterTimeout>:
/*-----------------------------------------------------------*/

#if( configUSE_MUTEXES == 1 )

	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
	{
 80070b0:	b480      	push	{r7}
 80070b2:	b085      	sub	sp, #20
 80070b4:	af00      	add	r7, sp, #0
 80070b6:	6078      	str	r0, [r7, #4]
		priority, but the waiting task times out, then the holder should
		disinherit the priority - but only down to the highest priority of any
		other tasks that are waiting for the same mutex.  For this purpose,
		return the priority of the highest priority task that is waiting for the
		mutex. */
		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
 80070b8:	687b      	ldr	r3, [r7, #4]
 80070ba:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80070bc:	2b00      	cmp	r3, #0
 80070be:	d006      	beq.n	80070ce <prvGetDisinheritPriorityAfterTimeout+0x1e>
		{
			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
 80070c0:	687b      	ldr	r3, [r7, #4]
 80070c2:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 80070c4:	681b      	ldr	r3, [r3, #0]
 80070c6:	f1c3 0338 	rsb	r3, r3, #56	@ 0x38
 80070ca:	60fb      	str	r3, [r7, #12]
 80070cc:	e001      	b.n	80070d2 <prvGetDisinheritPriorityAfterTimeout+0x22>
		}
		else
		{
			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
 80070ce:	2300      	movs	r3, #0
 80070d0:	60fb      	str	r3, [r7, #12]
		}

		return uxHighestPriorityOfWaitingTasks;
 80070d2:	68fb      	ldr	r3, [r7, #12]
	}
 80070d4:	4618      	mov	r0, r3
 80070d6:	3714      	adds	r7, #20
 80070d8:	46bd      	mov	sp, r7
 80070da:	f85d 7b04 	ldr.w	r7, [sp], #4
 80070de:	4770      	bx	lr

080070e0 <prvCopyDataToQueue>:

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
 80070e0:	b580      	push	{r7, lr}
 80070e2:	b086      	sub	sp, #24
 80070e4:	af00      	add	r7, sp, #0
 80070e6:	60f8      	str	r0, [r7, #12]
 80070e8:	60b9      	str	r1, [r7, #8]
 80070ea:	607a      	str	r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
 80070ec:	2300      	movs	r3, #0
 80070ee:	617b      	str	r3, [r7, #20]
UBaseType_t uxMessagesWaiting;

	/* This function is called from a critical section. */

	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 80070f0:	68fb      	ldr	r3, [r7, #12]
 80070f2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 80070f4:	613b      	str	r3, [r7, #16]

	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
 80070f6:	68fb      	ldr	r3, [r7, #12]
 80070f8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80070fa:	2b00      	cmp	r3, #0
 80070fc:	d10d      	bne.n	800711a <prvCopyDataToQueue+0x3a>
	{
		#if ( configUSE_MUTEXES == 1 )
		{
			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 80070fe:	68fb      	ldr	r3, [r7, #12]
 8007100:	681b      	ldr	r3, [r3, #0]
 8007102:	2b00      	cmp	r3, #0
 8007104:	d14d      	bne.n	80071a2 <prvCopyDataToQueue+0xc2>
			{
				/* The mutex is no longer being held. */
				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
 8007106:	68fb      	ldr	r3, [r7, #12]
 8007108:	689b      	ldr	r3, [r3, #8]
 800710a:	4618      	mov	r0, r3
 800710c:	f001 f834 	bl	8008178 <xTaskPriorityDisinherit>
 8007110:	6178      	str	r0, [r7, #20]
				pxQueue->u.xSemaphore.xMutexHolder = NULL;
 8007112:	68fb      	ldr	r3, [r7, #12]
 8007114:	2200      	movs	r2, #0
 8007116:	609a      	str	r2, [r3, #8]
 8007118:	e043      	b.n	80071a2 <prvCopyDataToQueue+0xc2>
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configUSE_MUTEXES */
	}
	else if( xPosition == queueSEND_TO_BACK )
 800711a:	687b      	ldr	r3, [r7, #4]
 800711c:	2b00      	cmp	r3, #0
 800711e:	d119      	bne.n	8007154 <prvCopyDataToQueue+0x74>
	{
		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8007120:	68fb      	ldr	r3, [r7, #12]
 8007122:	6858      	ldr	r0, [r3, #4]
 8007124:	68fb      	ldr	r3, [r7, #12]
 8007126:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8007128:	461a      	mov	r2, r3
 800712a:	68b9      	ldr	r1, [r7, #8]
 800712c:	f002 f9a8 	bl	8009480 <memcpy>
		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 8007130:	68fb      	ldr	r3, [r7, #12]
 8007132:	685a      	ldr	r2, [r3, #4]
 8007134:	68fb      	ldr	r3, [r7, #12]
 8007136:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8007138:	441a      	add	r2, r3
 800713a:	68fb      	ldr	r3, [r7, #12]
 800713c:	605a      	str	r2, [r3, #4]
		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 800713e:	68fb      	ldr	r3, [r7, #12]
 8007140:	685a      	ldr	r2, [r3, #4]
 8007142:	68fb      	ldr	r3, [r7, #12]
 8007144:	689b      	ldr	r3, [r3, #8]
 8007146:	429a      	cmp	r2, r3
 8007148:	d32b      	bcc.n	80071a2 <prvCopyDataToQueue+0xc2>
		{
			pxQueue->pcWriteTo = pxQueue->pcHead;
 800714a:	68fb      	ldr	r3, [r7, #12]
 800714c:	681a      	ldr	r2, [r3, #0]
 800714e:	68fb      	ldr	r3, [r7, #12]
 8007150:	605a      	str	r2, [r3, #4]
 8007152:	e026      	b.n	80071a2 <prvCopyDataToQueue+0xc2>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
 8007154:	68fb      	ldr	r3, [r7, #12]
 8007156:	68d8      	ldr	r0, [r3, #12]
 8007158:	68fb      	ldr	r3, [r7, #12]
 800715a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800715c:	461a      	mov	r2, r3
 800715e:	68b9      	ldr	r1, [r7, #8]
 8007160:	f002 f98e 	bl	8009480 <memcpy>
		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
 8007164:	68fb      	ldr	r3, [r7, #12]
 8007166:	68da      	ldr	r2, [r3, #12]
 8007168:	68fb      	ldr	r3, [r7, #12]
 800716a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800716c:	425b      	negs	r3, r3
 800716e:	441a      	add	r2, r3
 8007170:	68fb      	ldr	r3, [r7, #12]
 8007172:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 8007174:	68fb      	ldr	r3, [r7, #12]
 8007176:	68da      	ldr	r2, [r3, #12]
 8007178:	68fb      	ldr	r3, [r7, #12]
 800717a:	681b      	ldr	r3, [r3, #0]
 800717c:	429a      	cmp	r2, r3
 800717e:	d207      	bcs.n	8007190 <prvCopyDataToQueue+0xb0>
		{
			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
 8007180:	68fb      	ldr	r3, [r7, #12]
 8007182:	689a      	ldr	r2, [r3, #8]
 8007184:	68fb      	ldr	r3, [r7, #12]
 8007186:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8007188:	425b      	negs	r3, r3
 800718a:	441a      	add	r2, r3
 800718c:	68fb      	ldr	r3, [r7, #12]
 800718e:	60da      	str	r2, [r3, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		if( xPosition == queueOVERWRITE )
 8007190:	687b      	ldr	r3, [r7, #4]
 8007192:	2b02      	cmp	r3, #2
 8007194:	d105      	bne.n	80071a2 <prvCopyDataToQueue+0xc2>
		{
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8007196:	693b      	ldr	r3, [r7, #16]
 8007198:	2b00      	cmp	r3, #0
 800719a:	d002      	beq.n	80071a2 <prvCopyDataToQueue+0xc2>
			{
				/* An item is not being added but overwritten, so subtract
				one from the recorded number of items in the queue so when
				one is added again below the number of recorded items remains
				correct. */
				--uxMessagesWaiting;
 800719c:	693b      	ldr	r3, [r7, #16]
 800719e:	3b01      	subs	r3, #1
 80071a0:	613b      	str	r3, [r7, #16]
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 80071a2:	693b      	ldr	r3, [r7, #16]
 80071a4:	1c5a      	adds	r2, r3, #1
 80071a6:	68fb      	ldr	r3, [r7, #12]
 80071a8:	639a      	str	r2, [r3, #56]	@ 0x38

	return xReturn;
 80071aa:	697b      	ldr	r3, [r7, #20]
}
 80071ac:	4618      	mov	r0, r3
 80071ae:	3718      	adds	r7, #24
 80071b0:	46bd      	mov	sp, r7
 80071b2:	bd80      	pop	{r7, pc}

080071b4 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/

static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
 80071b4:	b580      	push	{r7, lr}
 80071b6:	b082      	sub	sp, #8
 80071b8:	af00      	add	r7, sp, #0
 80071ba:	6078      	str	r0, [r7, #4]
 80071bc:	6039      	str	r1, [r7, #0]
	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
 80071be:	687b      	ldr	r3, [r7, #4]
 80071c0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80071c2:	2b00      	cmp	r3, #0
 80071c4:	d018      	beq.n	80071f8 <prvCopyDataFromQueue+0x44>
	{
		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 80071c6:	687b      	ldr	r3, [r7, #4]
 80071c8:	68da      	ldr	r2, [r3, #12]
 80071ca:	687b      	ldr	r3, [r7, #4]
 80071cc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80071ce:	441a      	add	r2, r3
 80071d0:	687b      	ldr	r3, [r7, #4]
 80071d2:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
 80071d4:	687b      	ldr	r3, [r7, #4]
 80071d6:	68da      	ldr	r2, [r3, #12]
 80071d8:	687b      	ldr	r3, [r7, #4]
 80071da:	689b      	ldr	r3, [r3, #8]
 80071dc:	429a      	cmp	r2, r3
 80071de:	d303      	bcc.n	80071e8 <prvCopyDataFromQueue+0x34>
		{
			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 80071e0:	687b      	ldr	r3, [r7, #4]
 80071e2:	681a      	ldr	r2, [r3, #0]
 80071e4:	687b      	ldr	r3, [r7, #4]
 80071e6:	60da      	str	r2, [r3, #12]
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 80071e8:	687b      	ldr	r3, [r7, #4]
 80071ea:	68d9      	ldr	r1, [r3, #12]
 80071ec:	687b      	ldr	r3, [r7, #4]
 80071ee:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80071f0:	461a      	mov	r2, r3
 80071f2:	6838      	ldr	r0, [r7, #0]
 80071f4:	f002 f944 	bl	8009480 <memcpy>
	}
}
 80071f8:	bf00      	nop
 80071fa:	3708      	adds	r7, #8
 80071fc:	46bd      	mov	sp, r7
 80071fe:	bd80      	pop	{r7, pc}

08007200 <prvUnlockQueue>:
/*-----------------------------------------------------------*/

static void prvUnlockQueue( Queue_t * const pxQueue )
{
 8007200:	b580      	push	{r7, lr}
 8007202:	b084      	sub	sp, #16
 8007204:	af00      	add	r7, sp, #0
 8007206:	6078      	str	r0, [r7, #4]

	/* The lock counts contains the number of extra data items placed or
	removed from the queue while the queue was locked.  When a queue is
	locked items can be added or removed, but the event lists cannot be
	updated. */
	taskENTER_CRITICAL();
 8007208:	f001 fd9e 	bl	8008d48 <vPortEnterCritical>
	{
		int8_t cTxLock = pxQueue->cTxLock;
 800720c:	687b      	ldr	r3, [r7, #4]
 800720e:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8007212:	73fb      	strb	r3, [r7, #15]

		/* See if data was added to the queue while it was locked. */
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8007214:	e011      	b.n	800723a <prvUnlockQueue+0x3a>
			}
			#else /* configUSE_QUEUE_SETS */
			{
				/* Tasks that are removed from the event list will get added to
				the pending ready list as the scheduler is still suspended. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8007216:	687b      	ldr	r3, [r7, #4]
 8007218:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800721a:	2b00      	cmp	r3, #0
 800721c:	d012      	beq.n	8007244 <prvUnlockQueue+0x44>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 800721e:	687b      	ldr	r3, [r7, #4]
 8007220:	3324      	adds	r3, #36	@ 0x24
 8007222:	4618      	mov	r0, r3
 8007224:	f000 fd5c 	bl	8007ce0 <xTaskRemoveFromEventList>
 8007228:	4603      	mov	r3, r0
 800722a:	2b00      	cmp	r3, #0
 800722c:	d001      	beq.n	8007232 <prvUnlockQueue+0x32>
					{
						/* The task waiting has a higher priority so record that
						a context switch is required. */
						vTaskMissedYield();
 800722e:	f000 fe35 	bl	8007e9c <vTaskMissedYield>
					break;
				}
			}
			#endif /* configUSE_QUEUE_SETS */

			--cTxLock;
 8007232:	7bfb      	ldrb	r3, [r7, #15]
 8007234:	3b01      	subs	r3, #1
 8007236:	b2db      	uxtb	r3, r3
 8007238:	73fb      	strb	r3, [r7, #15]
		while( cTxLock > queueLOCKED_UNMODIFIED )
 800723a:	f997 300f 	ldrsb.w	r3, [r7, #15]
 800723e:	2b00      	cmp	r3, #0
 8007240:	dce9      	bgt.n	8007216 <prvUnlockQueue+0x16>
 8007242:	e000      	b.n	8007246 <prvUnlockQueue+0x46>
					break;
 8007244:	bf00      	nop
		}

		pxQueue->cTxLock = queueUNLOCKED;
 8007246:	687b      	ldr	r3, [r7, #4]
 8007248:	22ff      	movs	r2, #255	@ 0xff
 800724a:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
	}
	taskEXIT_CRITICAL();
 800724e:	f001 fdad 	bl	8008dac <vPortExitCritical>

	/* Do the same for the Rx lock. */
	taskENTER_CRITICAL();
 8007252:	f001 fd79 	bl	8008d48 <vPortEnterCritical>
	{
		int8_t cRxLock = pxQueue->cRxLock;
 8007256:	687b      	ldr	r3, [r7, #4]
 8007258:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 800725c:	73bb      	strb	r3, [r7, #14]

		while( cRxLock > queueLOCKED_UNMODIFIED )
 800725e:	e011      	b.n	8007284 <prvUnlockQueue+0x84>
		{
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8007260:	687b      	ldr	r3, [r7, #4]
 8007262:	691b      	ldr	r3, [r3, #16]
 8007264:	2b00      	cmp	r3, #0
 8007266:	d012      	beq.n	800728e <prvUnlockQueue+0x8e>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8007268:	687b      	ldr	r3, [r7, #4]
 800726a:	3310      	adds	r3, #16
 800726c:	4618      	mov	r0, r3
 800726e:	f000 fd37 	bl	8007ce0 <xTaskRemoveFromEventList>
 8007272:	4603      	mov	r3, r0
 8007274:	2b00      	cmp	r3, #0
 8007276:	d001      	beq.n	800727c <prvUnlockQueue+0x7c>
				{
					vTaskMissedYield();
 8007278:	f000 fe10 	bl	8007e9c <vTaskMissedYield>
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				--cRxLock;
 800727c:	7bbb      	ldrb	r3, [r7, #14]
 800727e:	3b01      	subs	r3, #1
 8007280:	b2db      	uxtb	r3, r3
 8007282:	73bb      	strb	r3, [r7, #14]
		while( cRxLock > queueLOCKED_UNMODIFIED )
 8007284:	f997 300e 	ldrsb.w	r3, [r7, #14]
 8007288:	2b00      	cmp	r3, #0
 800728a:	dce9      	bgt.n	8007260 <prvUnlockQueue+0x60>
 800728c:	e000      	b.n	8007290 <prvUnlockQueue+0x90>
			}
			else
			{
				break;
 800728e:	bf00      	nop
			}
		}

		pxQueue->cRxLock = queueUNLOCKED;
 8007290:	687b      	ldr	r3, [r7, #4]
 8007292:	22ff      	movs	r2, #255	@ 0xff
 8007294:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
	}
	taskEXIT_CRITICAL();
 8007298:	f001 fd88 	bl	8008dac <vPortExitCritical>
}
 800729c:	bf00      	nop
 800729e:	3710      	adds	r7, #16
 80072a0:	46bd      	mov	sp, r7
 80072a2:	bd80      	pop	{r7, pc}

080072a4 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
 80072a4:	b580      	push	{r7, lr}
 80072a6:	b084      	sub	sp, #16
 80072a8:	af00      	add	r7, sp, #0
 80072aa:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 80072ac:	f001 fd4c 	bl	8008d48 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
 80072b0:	687b      	ldr	r3, [r7, #4]
 80072b2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 80072b4:	2b00      	cmp	r3, #0
 80072b6:	d102      	bne.n	80072be <prvIsQueueEmpty+0x1a>
		{
			xReturn = pdTRUE;
 80072b8:	2301      	movs	r3, #1
 80072ba:	60fb      	str	r3, [r7, #12]
 80072bc:	e001      	b.n	80072c2 <prvIsQueueEmpty+0x1e>
		}
		else
		{
			xReturn = pdFALSE;
 80072be:	2300      	movs	r3, #0
 80072c0:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 80072c2:	f001 fd73 	bl	8008dac <vPortExitCritical>

	return xReturn;
 80072c6:	68fb      	ldr	r3, [r7, #12]
}
 80072c8:	4618      	mov	r0, r3
 80072ca:	3710      	adds	r7, #16
 80072cc:	46bd      	mov	sp, r7
 80072ce:	bd80      	pop	{r7, pc}

080072d0 <prvIsQueueFull>:
	return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
 80072d0:	b580      	push	{r7, lr}
 80072d2:	b084      	sub	sp, #16
 80072d4:	af00      	add	r7, sp, #0
 80072d6:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 80072d8:	f001 fd36 	bl	8008d48 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
 80072dc:	687b      	ldr	r3, [r7, #4]
 80072de:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 80072e0:	687b      	ldr	r3, [r7, #4]
 80072e2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80072e4:	429a      	cmp	r2, r3
 80072e6:	d102      	bne.n	80072ee <prvIsQueueFull+0x1e>
		{
			xReturn = pdTRUE;
 80072e8:	2301      	movs	r3, #1
 80072ea:	60fb      	str	r3, [r7, #12]
 80072ec:	e001      	b.n	80072f2 <prvIsQueueFull+0x22>
		}
		else
		{
			xReturn = pdFALSE;
 80072ee:	2300      	movs	r3, #0
 80072f0:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 80072f2:	f001 fd5b 	bl	8008dac <vPortExitCritical>

	return xReturn;
 80072f6:	68fb      	ldr	r3, [r7, #12]
}
 80072f8:	4618      	mov	r0, r3
 80072fa:	3710      	adds	r7, #16
 80072fc:	46bd      	mov	sp, r7
 80072fe:	bd80      	pop	{r7, pc}

08007300 <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
	{
 8007300:	b480      	push	{r7}
 8007302:	b085      	sub	sp, #20
 8007304:	af00      	add	r7, sp, #0
 8007306:	6078      	str	r0, [r7, #4]
 8007308:	6039      	str	r1, [r7, #0]
	UBaseType_t ux;

		/* See if there is an empty space in the registry.  A NULL name denotes
		a free slot. */
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 800730a:	2300      	movs	r3, #0
 800730c:	60fb      	str	r3, [r7, #12]
 800730e:	e014      	b.n	800733a <vQueueAddToRegistry+0x3a>
		{
			if( xQueueRegistry[ ux ].pcQueueName == NULL )
 8007310:	4a0f      	ldr	r2, [pc, #60]	@ (8007350 <vQueueAddToRegistry+0x50>)
 8007312:	68fb      	ldr	r3, [r7, #12]
 8007314:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
 8007318:	2b00      	cmp	r3, #0
 800731a:	d10b      	bne.n	8007334 <vQueueAddToRegistry+0x34>
			{
				/* Store the information on this queue. */
				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
 800731c:	490c      	ldr	r1, [pc, #48]	@ (8007350 <vQueueAddToRegistry+0x50>)
 800731e:	68fb      	ldr	r3, [r7, #12]
 8007320:	683a      	ldr	r2, [r7, #0]
 8007322:	f841 2033 	str.w	r2, [r1, r3, lsl #3]
				xQueueRegistry[ ux ].xHandle = xQueue;
 8007326:	4a0a      	ldr	r2, [pc, #40]	@ (8007350 <vQueueAddToRegistry+0x50>)
 8007328:	68fb      	ldr	r3, [r7, #12]
 800732a:	00db      	lsls	r3, r3, #3
 800732c:	4413      	add	r3, r2
 800732e:	687a      	ldr	r2, [r7, #4]
 8007330:	605a      	str	r2, [r3, #4]

				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
				break;
 8007332:	e006      	b.n	8007342 <vQueueAddToRegistry+0x42>
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8007334:	68fb      	ldr	r3, [r7, #12]
 8007336:	3301      	adds	r3, #1
 8007338:	60fb      	str	r3, [r7, #12]
 800733a:	68fb      	ldr	r3, [r7, #12]
 800733c:	2b07      	cmp	r3, #7
 800733e:	d9e7      	bls.n	8007310 <vQueueAddToRegistry+0x10>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	}
 8007340:	bf00      	nop
 8007342:	bf00      	nop
 8007344:	3714      	adds	r7, #20
 8007346:	46bd      	mov	sp, r7
 8007348:	f85d 7b04 	ldr.w	r7, [sp], #4
 800734c:	4770      	bx	lr
 800734e:	bf00      	nop
 8007350:	20000f90 	.word	0x20000f90

08007354 <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/

#if ( configUSE_TIMERS == 1 )

	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8007354:	b580      	push	{r7, lr}
 8007356:	b086      	sub	sp, #24
 8007358:	af00      	add	r7, sp, #0
 800735a:	60f8      	str	r0, [r7, #12]
 800735c:	60b9      	str	r1, [r7, #8]
 800735e:	607a      	str	r2, [r7, #4]
	Queue_t * const pxQueue = xQueue;
 8007360:	68fb      	ldr	r3, [r7, #12]
 8007362:	617b      	str	r3, [r7, #20]
		will not actually cause the task to block, just place it on a blocked
		list.  It will not block until the scheduler is unlocked - at which
		time a yield will be performed.  If an item is added to the queue while
		the queue is locked, and the calling task blocks on the queue, then the
		calling task will be immediately unblocked when the queue is unlocked. */
		prvLockQueue( pxQueue );
 8007364:	f001 fcf0 	bl	8008d48 <vPortEnterCritical>
 8007368:	697b      	ldr	r3, [r7, #20]
 800736a:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 800736e:	b25b      	sxtb	r3, r3
 8007370:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8007374:	d103      	bne.n	800737e <vQueueWaitForMessageRestricted+0x2a>
 8007376:	697b      	ldr	r3, [r7, #20]
 8007378:	2200      	movs	r2, #0
 800737a:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 800737e:	697b      	ldr	r3, [r7, #20]
 8007380:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8007384:	b25b      	sxtb	r3, r3
 8007386:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 800738a:	d103      	bne.n	8007394 <vQueueWaitForMessageRestricted+0x40>
 800738c:	697b      	ldr	r3, [r7, #20]
 800738e:	2200      	movs	r2, #0
 8007390:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8007394:	f001 fd0a 	bl	8008dac <vPortExitCritical>
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
 8007398:	697b      	ldr	r3, [r7, #20]
 800739a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800739c:	2b00      	cmp	r3, #0
 800739e:	d106      	bne.n	80073ae <vQueueWaitForMessageRestricted+0x5a>
		{
			/* There is nothing in the queue, block for the specified period. */
			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
 80073a0:	697b      	ldr	r3, [r7, #20]
 80073a2:	3324      	adds	r3, #36	@ 0x24
 80073a4:	687a      	ldr	r2, [r7, #4]
 80073a6:	68b9      	ldr	r1, [r7, #8]
 80073a8:	4618      	mov	r0, r3
 80073aa:	f000 fc6d 	bl	8007c88 <vTaskPlaceOnEventListRestricted>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		prvUnlockQueue( pxQueue );
 80073ae:	6978      	ldr	r0, [r7, #20]
 80073b0:	f7ff ff26 	bl	8007200 <prvUnlockQueue>
	}
 80073b4:	bf00      	nop
 80073b6:	3718      	adds	r7, #24
 80073b8:	46bd      	mov	sp, r7
 80073ba:	bd80      	pop	{r7, pc}

080073bc <xTaskCreateStatic>:
									const uint32_t ulStackDepth,
									void * const pvParameters,
									UBaseType_t uxPriority,
									StackType_t * const puxStackBuffer,
									StaticTask_t * const pxTaskBuffer )
	{
 80073bc:	b580      	push	{r7, lr}
 80073be:	b08e      	sub	sp, #56	@ 0x38
 80073c0:	af04      	add	r7, sp, #16
 80073c2:	60f8      	str	r0, [r7, #12]
 80073c4:	60b9      	str	r1, [r7, #8]
 80073c6:	607a      	str	r2, [r7, #4]
 80073c8:	603b      	str	r3, [r7, #0]
	TCB_t *pxNewTCB;
	TaskHandle_t xReturn;

		configASSERT( puxStackBuffer != NULL );
 80073ca:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80073cc:	2b00      	cmp	r3, #0
 80073ce:	d10b      	bne.n	80073e8 <xTaskCreateStatic+0x2c>
	__asm volatile
 80073d0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80073d4:	f383 8811 	msr	BASEPRI, r3
 80073d8:	f3bf 8f6f 	isb	sy
 80073dc:	f3bf 8f4f 	dsb	sy
 80073e0:	623b      	str	r3, [r7, #32]
}
 80073e2:	bf00      	nop
 80073e4:	bf00      	nop
 80073e6:	e7fd      	b.n	80073e4 <xTaskCreateStatic+0x28>
		configASSERT( pxTaskBuffer != NULL );
 80073e8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80073ea:	2b00      	cmp	r3, #0
 80073ec:	d10b      	bne.n	8007406 <xTaskCreateStatic+0x4a>
	__asm volatile
 80073ee:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80073f2:	f383 8811 	msr	BASEPRI, r3
 80073f6:	f3bf 8f6f 	isb	sy
 80073fa:	f3bf 8f4f 	dsb	sy
 80073fe:	61fb      	str	r3, [r7, #28]
}
 8007400:	bf00      	nop
 8007402:	bf00      	nop
 8007404:	e7fd      	b.n	8007402 <xTaskCreateStatic+0x46>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticTask_t equals the size of the real task
			structure. */
			volatile size_t xSize = sizeof( StaticTask_t );
 8007406:	23a8      	movs	r3, #168	@ 0xa8
 8007408:	613b      	str	r3, [r7, #16]
			configASSERT( xSize == sizeof( TCB_t ) );
 800740a:	693b      	ldr	r3, [r7, #16]
 800740c:	2ba8      	cmp	r3, #168	@ 0xa8
 800740e:	d00b      	beq.n	8007428 <xTaskCreateStatic+0x6c>
	__asm volatile
 8007410:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007414:	f383 8811 	msr	BASEPRI, r3
 8007418:	f3bf 8f6f 	isb	sy
 800741c:	f3bf 8f4f 	dsb	sy
 8007420:	61bb      	str	r3, [r7, #24]
}
 8007422:	bf00      	nop
 8007424:	bf00      	nop
 8007426:	e7fd      	b.n	8007424 <xTaskCreateStatic+0x68>
			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
 8007428:	693b      	ldr	r3, [r7, #16]
		}
		#endif /* configASSERT_DEFINED */


		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
 800742a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800742c:	2b00      	cmp	r3, #0
 800742e:	d01e      	beq.n	800746e <xTaskCreateStatic+0xb2>
 8007430:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8007432:	2b00      	cmp	r3, #0
 8007434:	d01b      	beq.n	800746e <xTaskCreateStatic+0xb2>
		{
			/* The memory used for the task's TCB and stack are passed into this
			function - use them. */
			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 8007436:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8007438:	627b      	str	r3, [r7, #36]	@ 0x24
			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 800743a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800743c:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 800743e:	631a      	str	r2, [r3, #48]	@ 0x30

			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created statically in case the task is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
 8007440:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8007442:	2202      	movs	r2, #2
 8007444:	f883 20a5 	strb.w	r2, [r3, #165]	@ 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
 8007448:	2300      	movs	r3, #0
 800744a:	9303      	str	r3, [sp, #12]
 800744c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800744e:	9302      	str	r3, [sp, #8]
 8007450:	f107 0314 	add.w	r3, r7, #20
 8007454:	9301      	str	r3, [sp, #4]
 8007456:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007458:	9300      	str	r3, [sp, #0]
 800745a:	683b      	ldr	r3, [r7, #0]
 800745c:	687a      	ldr	r2, [r7, #4]
 800745e:	68b9      	ldr	r1, [r7, #8]
 8007460:	68f8      	ldr	r0, [r7, #12]
 8007462:	f000 f851 	bl	8007508 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 8007466:	6a78      	ldr	r0, [r7, #36]	@ 0x24
 8007468:	f000 f8f6 	bl	8007658 <prvAddNewTaskToReadyList>
 800746c:	e001      	b.n	8007472 <xTaskCreateStatic+0xb6>
		}
		else
		{
			xReturn = NULL;
 800746e:	2300      	movs	r3, #0
 8007470:	617b      	str	r3, [r7, #20]
		}

		return xReturn;
 8007472:	697b      	ldr	r3, [r7, #20]
	}
 8007474:	4618      	mov	r0, r3
 8007476:	3728      	adds	r7, #40	@ 0x28
 8007478:	46bd      	mov	sp, r7
 800747a:	bd80      	pop	{r7, pc}

0800747c <xTaskCreate>:
							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
							const configSTACK_DEPTH_TYPE usStackDepth,
							void * const pvParameters,
							UBaseType_t uxPriority,
							TaskHandle_t * const pxCreatedTask )
	{
 800747c:	b580      	push	{r7, lr}
 800747e:	b08c      	sub	sp, #48	@ 0x30
 8007480:	af04      	add	r7, sp, #16
 8007482:	60f8      	str	r0, [r7, #12]
 8007484:	60b9      	str	r1, [r7, #8]
 8007486:	603b      	str	r3, [r7, #0]
 8007488:	4613      	mov	r3, r2
 800748a:	80fb      	strh	r3, [r7, #6]
		#else /* portSTACK_GROWTH */
		{
		StackType_t *pxStack;

			/* Allocate space for the stack used by the task being created. */
			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
 800748c:	88fb      	ldrh	r3, [r7, #6]
 800748e:	009b      	lsls	r3, r3, #2
 8007490:	4618      	mov	r0, r3
 8007492:	f001 fd7b 	bl	8008f8c <pvPortMalloc>
 8007496:	6178      	str	r0, [r7, #20]

			if( pxStack != NULL )
 8007498:	697b      	ldr	r3, [r7, #20]
 800749a:	2b00      	cmp	r3, #0
 800749c:	d00e      	beq.n	80074bc <xTaskCreate+0x40>
			{
				/* Allocate space for the TCB. */
				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
 800749e:	20a8      	movs	r0, #168	@ 0xa8
 80074a0:	f001 fd74 	bl	8008f8c <pvPortMalloc>
 80074a4:	61f8      	str	r0, [r7, #28]

				if( pxNewTCB != NULL )
 80074a6:	69fb      	ldr	r3, [r7, #28]
 80074a8:	2b00      	cmp	r3, #0
 80074aa:	d003      	beq.n	80074b4 <xTaskCreate+0x38>
				{
					/* Store the stack location in the TCB. */
					pxNewTCB->pxStack = pxStack;
 80074ac:	69fb      	ldr	r3, [r7, #28]
 80074ae:	697a      	ldr	r2, [r7, #20]
 80074b0:	631a      	str	r2, [r3, #48]	@ 0x30
 80074b2:	e005      	b.n	80074c0 <xTaskCreate+0x44>
				}
				else
				{
					/* The stack cannot be used as the TCB was not created.  Free
					it again. */
					vPortFree( pxStack );
 80074b4:	6978      	ldr	r0, [r7, #20]
 80074b6:	f001 fe37 	bl	8009128 <vPortFree>
 80074ba:	e001      	b.n	80074c0 <xTaskCreate+0x44>
				}
			}
			else
			{
				pxNewTCB = NULL;
 80074bc:	2300      	movs	r3, #0
 80074be:	61fb      	str	r3, [r7, #28]
			}
		}
		#endif /* portSTACK_GROWTH */

		if( pxNewTCB != NULL )
 80074c0:	69fb      	ldr	r3, [r7, #28]
 80074c2:	2b00      	cmp	r3, #0
 80074c4:	d017      	beq.n	80074f6 <xTaskCreate+0x7a>
		{
			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created dynamically in case it is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
 80074c6:	69fb      	ldr	r3, [r7, #28]
 80074c8:	2200      	movs	r2, #0
 80074ca:	f883 20a5 	strb.w	r2, [r3, #165]	@ 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
 80074ce:	88fa      	ldrh	r2, [r7, #6]
 80074d0:	2300      	movs	r3, #0
 80074d2:	9303      	str	r3, [sp, #12]
 80074d4:	69fb      	ldr	r3, [r7, #28]
 80074d6:	9302      	str	r3, [sp, #8]
 80074d8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80074da:	9301      	str	r3, [sp, #4]
 80074dc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80074de:	9300      	str	r3, [sp, #0]
 80074e0:	683b      	ldr	r3, [r7, #0]
 80074e2:	68b9      	ldr	r1, [r7, #8]
 80074e4:	68f8      	ldr	r0, [r7, #12]
 80074e6:	f000 f80f 	bl	8007508 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 80074ea:	69f8      	ldr	r0, [r7, #28]
 80074ec:	f000 f8b4 	bl	8007658 <prvAddNewTaskToReadyList>
			xReturn = pdPASS;
 80074f0:	2301      	movs	r3, #1
 80074f2:	61bb      	str	r3, [r7, #24]
 80074f4:	e002      	b.n	80074fc <xTaskCreate+0x80>
		}
		else
		{
			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
 80074f6:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80074fa:	61bb      	str	r3, [r7, #24]
		}

		return xReturn;
 80074fc:	69bb      	ldr	r3, [r7, #24]
	}
 80074fe:	4618      	mov	r0, r3
 8007500:	3720      	adds	r7, #32
 8007502:	46bd      	mov	sp, r7
 8007504:	bd80      	pop	{r7, pc}
	...

08007508 <prvInitialiseNewTask>:
									void * const pvParameters,
									UBaseType_t uxPriority,
									TaskHandle_t * const pxCreatedTask,
									TCB_t *pxNewTCB,
									const MemoryRegion_t * const xRegions )
{
 8007508:	b580      	push	{r7, lr}
 800750a:	b088      	sub	sp, #32
 800750c:	af00      	add	r7, sp, #0
 800750e:	60f8      	str	r0, [r7, #12]
 8007510:	60b9      	str	r1, [r7, #8]
 8007512:	607a      	str	r2, [r7, #4]
 8007514:	603b      	str	r3, [r7, #0]

	/* Avoid dependency on memset() if it is not required. */
	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
	{
		/* Fill the stack with a known value to assist debugging. */
		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
 8007516:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007518:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 800751a:	687b      	ldr	r3, [r7, #4]
 800751c:	009b      	lsls	r3, r3, #2
 800751e:	461a      	mov	r2, r3
 8007520:	21a5      	movs	r1, #165	@ 0xa5
 8007522:	f001 ff21 	bl	8009368 <memset>
	grows from high memory to low (as per the 80x86) or vice versa.
	portSTACK_GROWTH is used to make the result positive or negative as required
	by the port. */
	#if( portSTACK_GROWTH < 0 )
	{
		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
 8007526:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007528:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 800752a:	687b      	ldr	r3, [r7, #4]
 800752c:	f103 4380 	add.w	r3, r3, #1073741824	@ 0x40000000
 8007530:	3b01      	subs	r3, #1
 8007532:	009b      	lsls	r3, r3, #2
 8007534:	4413      	add	r3, r2
 8007536:	61bb      	str	r3, [r7, #24]
		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 8007538:	69bb      	ldr	r3, [r7, #24]
 800753a:	f023 0307 	bic.w	r3, r3, #7
 800753e:	61bb      	str	r3, [r7, #24]

		/* Check the alignment of the calculated top of stack is correct. */
		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
 8007540:	69bb      	ldr	r3, [r7, #24]
 8007542:	f003 0307 	and.w	r3, r3, #7
 8007546:	2b00      	cmp	r3, #0
 8007548:	d00b      	beq.n	8007562 <prvInitialiseNewTask+0x5a>
	__asm volatile
 800754a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800754e:	f383 8811 	msr	BASEPRI, r3
 8007552:	f3bf 8f6f 	isb	sy
 8007556:	f3bf 8f4f 	dsb	sy
 800755a:	617b      	str	r3, [r7, #20]
}
 800755c:	bf00      	nop
 800755e:	bf00      	nop
 8007560:	e7fd      	b.n	800755e <prvInitialiseNewTask+0x56>
		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
	}
	#endif /* portSTACK_GROWTH */

	/* Store the task name in the TCB. */
	if( pcName != NULL )
 8007562:	68bb      	ldr	r3, [r7, #8]
 8007564:	2b00      	cmp	r3, #0
 8007566:	d01f      	beq.n	80075a8 <prvInitialiseNewTask+0xa0>
	{
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 8007568:	2300      	movs	r3, #0
 800756a:	61fb      	str	r3, [r7, #28]
 800756c:	e012      	b.n	8007594 <prvInitialiseNewTask+0x8c>
		{
			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
 800756e:	68ba      	ldr	r2, [r7, #8]
 8007570:	69fb      	ldr	r3, [r7, #28]
 8007572:	4413      	add	r3, r2
 8007574:	7819      	ldrb	r1, [r3, #0]
 8007576:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8007578:	69fb      	ldr	r3, [r7, #28]
 800757a:	4413      	add	r3, r2
 800757c:	3334      	adds	r3, #52	@ 0x34
 800757e:	460a      	mov	r2, r1
 8007580:	701a      	strb	r2, [r3, #0]

			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
			configMAX_TASK_NAME_LEN characters just in case the memory after the
			string is not accessible (extremely unlikely). */
			if( pcName[ x ] == ( char ) 0x00 )
 8007582:	68ba      	ldr	r2, [r7, #8]
 8007584:	69fb      	ldr	r3, [r7, #28]
 8007586:	4413      	add	r3, r2
 8007588:	781b      	ldrb	r3, [r3, #0]
 800758a:	2b00      	cmp	r3, #0
 800758c:	d006      	beq.n	800759c <prvInitialiseNewTask+0x94>
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 800758e:	69fb      	ldr	r3, [r7, #28]
 8007590:	3301      	adds	r3, #1
 8007592:	61fb      	str	r3, [r7, #28]
 8007594:	69fb      	ldr	r3, [r7, #28]
 8007596:	2b0f      	cmp	r3, #15
 8007598:	d9e9      	bls.n	800756e <prvInitialiseNewTask+0x66>
 800759a:	e000      	b.n	800759e <prvInitialiseNewTask+0x96>
			{
				break;
 800759c:	bf00      	nop
			}
		}

		/* Ensure the name string is terminated in the case that the string length
		was greater or equal to configMAX_TASK_NAME_LEN. */
		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
 800759e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075a0:	2200      	movs	r2, #0
 80075a2:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
 80075a6:	e003      	b.n	80075b0 <prvInitialiseNewTask+0xa8>
	}
	else
	{
		/* The task has not been given a name, so just ensure there is a NULL
		terminator when it is read out. */
		pxNewTCB->pcTaskName[ 0 ] = 0x00;
 80075a8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075aa:	2200      	movs	r2, #0
 80075ac:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
	}

	/* This is used as an array index so must ensure it's not too large.  First
	remove the privilege bit if one is present. */
	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
 80075b0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80075b2:	2b37      	cmp	r3, #55	@ 0x37
 80075b4:	d901      	bls.n	80075ba <prvInitialiseNewTask+0xb2>
	{
		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
 80075b6:	2337      	movs	r3, #55	@ 0x37
 80075b8:	62bb      	str	r3, [r7, #40]	@ 0x28
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxNewTCB->uxPriority = uxPriority;
 80075ba:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075bc:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 80075be:	62da      	str	r2, [r3, #44]	@ 0x2c
	#if ( configUSE_MUTEXES == 1 )
	{
		pxNewTCB->uxBasePriority = uxPriority;
 80075c0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075c2:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 80075c4:	64da      	str	r2, [r3, #76]	@ 0x4c
		pxNewTCB->uxMutexesHeld = 0;
 80075c6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075c8:	2200      	movs	r2, #0
 80075ca:	651a      	str	r2, [r3, #80]	@ 0x50
	}
	#endif /* configUSE_MUTEXES */

	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
 80075cc:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075ce:	3304      	adds	r3, #4
 80075d0:	4618      	mov	r0, r3
 80075d2:	f7fe ff71 	bl	80064b8 <vListInitialiseItem>
	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
 80075d6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075d8:	3318      	adds	r3, #24
 80075da:	4618      	mov	r0, r3
 80075dc:	f7fe ff6c 	bl	80064b8 <vListInitialiseItem>

	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
	back to	the containing TCB from a generic item in a list. */
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
 80075e0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075e2:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80075e4:	611a      	str	r2, [r3, #16]

	/* Event lists are always in priority order. */
	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80075e6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80075e8:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 80075ec:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075ee:	619a      	str	r2, [r3, #24]
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
 80075f0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075f2:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80075f4:	625a      	str	r2, [r3, #36]	@ 0x24
	}
	#endif

	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
	{
		pxNewTCB->ulNotifiedValue = 0;
 80075f6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80075f8:	2200      	movs	r2, #0
 80075fa:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 80075fe:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007600:	2200      	movs	r2, #0
 8007602:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
	#if ( configUSE_NEWLIB_REENTRANT == 1 )
	{
		/* Initialise this task's Newlib reent structure.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
 8007606:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007608:	3354      	adds	r3, #84	@ 0x54
 800760a:	224c      	movs	r2, #76	@ 0x4c
 800760c:	2100      	movs	r1, #0
 800760e:	4618      	mov	r0, r3
 8007610:	f001 feaa 	bl	8009368 <memset>
 8007614:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007616:	4a0d      	ldr	r2, [pc, #52]	@ (800764c <prvInitialiseNewTask+0x144>)
 8007618:	659a      	str	r2, [r3, #88]	@ 0x58
 800761a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800761c:	4a0c      	ldr	r2, [pc, #48]	@ (8007650 <prvInitialiseNewTask+0x148>)
 800761e:	65da      	str	r2, [r3, #92]	@ 0x5c
 8007620:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007622:	4a0c      	ldr	r2, [pc, #48]	@ (8007654 <prvInitialiseNewTask+0x14c>)
 8007624:	661a      	str	r2, [r3, #96]	@ 0x60
			}
			#endif /* portSTACK_GROWTH */
		}
		#else /* portHAS_STACK_OVERFLOW_CHECKING */
		{
			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
 8007626:	683a      	ldr	r2, [r7, #0]
 8007628:	68f9      	ldr	r1, [r7, #12]
 800762a:	69b8      	ldr	r0, [r7, #24]
 800762c:	f001 fa5a 	bl	8008ae4 <pxPortInitialiseStack>
 8007630:	4602      	mov	r2, r0
 8007632:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8007634:	601a      	str	r2, [r3, #0]
		}
		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
	}
	#endif /* portUSING_MPU_WRAPPERS */

	if( pxCreatedTask != NULL )
 8007636:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8007638:	2b00      	cmp	r3, #0
 800763a:	d002      	beq.n	8007642 <prvInitialiseNewTask+0x13a>
	{
		/* Pass the handle out in an anonymous way.  The handle can be used to
		change the created task's priority, delete the created task, etc.*/
		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
 800763c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800763e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8007640:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8007642:	bf00      	nop
 8007644:	3720      	adds	r7, #32
 8007646:	46bd      	mov	sp, r7
 8007648:	bd80      	pop	{r7, pc}
 800764a:	bf00      	nop
 800764c:	20008b54 	.word	0x20008b54
 8007650:	20008bbc 	.word	0x20008bbc
 8007654:	20008c24 	.word	0x20008c24

08007658 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/

static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
 8007658:	b580      	push	{r7, lr}
 800765a:	b082      	sub	sp, #8
 800765c:	af00      	add	r7, sp, #0
 800765e:	6078      	str	r0, [r7, #4]
	/* Ensure interrupts don't access the task lists while the lists are being
	updated. */
	taskENTER_CRITICAL();
 8007660:	f001 fb72 	bl	8008d48 <vPortEnterCritical>
	{
		uxCurrentNumberOfTasks++;
 8007664:	4b2d      	ldr	r3, [pc, #180]	@ (800771c <prvAddNewTaskToReadyList+0xc4>)
 8007666:	681b      	ldr	r3, [r3, #0]
 8007668:	3301      	adds	r3, #1
 800766a:	4a2c      	ldr	r2, [pc, #176]	@ (800771c <prvAddNewTaskToReadyList+0xc4>)
 800766c:	6013      	str	r3, [r2, #0]
		if( pxCurrentTCB == NULL )
 800766e:	4b2c      	ldr	r3, [pc, #176]	@ (8007720 <prvAddNewTaskToReadyList+0xc8>)
 8007670:	681b      	ldr	r3, [r3, #0]
 8007672:	2b00      	cmp	r3, #0
 8007674:	d109      	bne.n	800768a <prvAddNewTaskToReadyList+0x32>
		{
			/* There are no other tasks, or all the other tasks are in
			the suspended state - make this the current task. */
			pxCurrentTCB = pxNewTCB;
 8007676:	4a2a      	ldr	r2, [pc, #168]	@ (8007720 <prvAddNewTaskToReadyList+0xc8>)
 8007678:	687b      	ldr	r3, [r7, #4]
 800767a:	6013      	str	r3, [r2, #0]

			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
 800767c:	4b27      	ldr	r3, [pc, #156]	@ (800771c <prvAddNewTaskToReadyList+0xc4>)
 800767e:	681b      	ldr	r3, [r3, #0]
 8007680:	2b01      	cmp	r3, #1
 8007682:	d110      	bne.n	80076a6 <prvAddNewTaskToReadyList+0x4e>
			{
				/* This is the first task to be created so do the preliminary
				initialisation required.  We will not recover if this call
				fails, but we will report the failure. */
				prvInitialiseTaskLists();
 8007684:	f000 fc2e 	bl	8007ee4 <prvInitialiseTaskLists>
 8007688:	e00d      	b.n	80076a6 <prvAddNewTaskToReadyList+0x4e>
		else
		{
			/* If the scheduler is not already running, make this task the
			current task if it is the highest priority task to be created
			so far. */
			if( xSchedulerRunning == pdFALSE )
 800768a:	4b26      	ldr	r3, [pc, #152]	@ (8007724 <prvAddNewTaskToReadyList+0xcc>)
 800768c:	681b      	ldr	r3, [r3, #0]
 800768e:	2b00      	cmp	r3, #0
 8007690:	d109      	bne.n	80076a6 <prvAddNewTaskToReadyList+0x4e>
			{
				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
 8007692:	4b23      	ldr	r3, [pc, #140]	@ (8007720 <prvAddNewTaskToReadyList+0xc8>)
 8007694:	681b      	ldr	r3, [r3, #0]
 8007696:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007698:	687b      	ldr	r3, [r7, #4]
 800769a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800769c:	429a      	cmp	r2, r3
 800769e:	d802      	bhi.n	80076a6 <prvAddNewTaskToReadyList+0x4e>
				{
					pxCurrentTCB = pxNewTCB;
 80076a0:	4a1f      	ldr	r2, [pc, #124]	@ (8007720 <prvAddNewTaskToReadyList+0xc8>)
 80076a2:	687b      	ldr	r3, [r7, #4]
 80076a4:	6013      	str	r3, [r2, #0]
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}

		uxTaskNumber++;
 80076a6:	4b20      	ldr	r3, [pc, #128]	@ (8007728 <prvAddNewTaskToReadyList+0xd0>)
 80076a8:	681b      	ldr	r3, [r3, #0]
 80076aa:	3301      	adds	r3, #1
 80076ac:	4a1e      	ldr	r2, [pc, #120]	@ (8007728 <prvAddNewTaskToReadyList+0xd0>)
 80076ae:	6013      	str	r3, [r2, #0]

		#if ( configUSE_TRACE_FACILITY == 1 )
		{
			/* Add a counter into the TCB for tracing only. */
			pxNewTCB->uxTCBNumber = uxTaskNumber;
 80076b0:	4b1d      	ldr	r3, [pc, #116]	@ (8007728 <prvAddNewTaskToReadyList+0xd0>)
 80076b2:	681a      	ldr	r2, [r3, #0]
 80076b4:	687b      	ldr	r3, [r7, #4]
 80076b6:	645a      	str	r2, [r3, #68]	@ 0x44
		}
		#endif /* configUSE_TRACE_FACILITY */
		traceTASK_CREATE( pxNewTCB );

		prvAddTaskToReadyList( pxNewTCB );
 80076b8:	687b      	ldr	r3, [r7, #4]
 80076ba:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80076bc:	4b1b      	ldr	r3, [pc, #108]	@ (800772c <prvAddNewTaskToReadyList+0xd4>)
 80076be:	681b      	ldr	r3, [r3, #0]
 80076c0:	429a      	cmp	r2, r3
 80076c2:	d903      	bls.n	80076cc <prvAddNewTaskToReadyList+0x74>
 80076c4:	687b      	ldr	r3, [r7, #4]
 80076c6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80076c8:	4a18      	ldr	r2, [pc, #96]	@ (800772c <prvAddNewTaskToReadyList+0xd4>)
 80076ca:	6013      	str	r3, [r2, #0]
 80076cc:	687b      	ldr	r3, [r7, #4]
 80076ce:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80076d0:	4613      	mov	r3, r2
 80076d2:	009b      	lsls	r3, r3, #2
 80076d4:	4413      	add	r3, r2
 80076d6:	009b      	lsls	r3, r3, #2
 80076d8:	4a15      	ldr	r2, [pc, #84]	@ (8007730 <prvAddNewTaskToReadyList+0xd8>)
 80076da:	441a      	add	r2, r3
 80076dc:	687b      	ldr	r3, [r7, #4]
 80076de:	3304      	adds	r3, #4
 80076e0:	4619      	mov	r1, r3
 80076e2:	4610      	mov	r0, r2
 80076e4:	f7fe fef5 	bl	80064d2 <vListInsertEnd>

		portSETUP_TCB( pxNewTCB );
	}
	taskEXIT_CRITICAL();
 80076e8:	f001 fb60 	bl	8008dac <vPortExitCritical>

	if( xSchedulerRunning != pdFALSE )
 80076ec:	4b0d      	ldr	r3, [pc, #52]	@ (8007724 <prvAddNewTaskToReadyList+0xcc>)
 80076ee:	681b      	ldr	r3, [r3, #0]
 80076f0:	2b00      	cmp	r3, #0
 80076f2:	d00e      	beq.n	8007712 <prvAddNewTaskToReadyList+0xba>
	{
		/* If the created task is of a higher priority than the current task
		then it should run now. */
		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
 80076f4:	4b0a      	ldr	r3, [pc, #40]	@ (8007720 <prvAddNewTaskToReadyList+0xc8>)
 80076f6:	681b      	ldr	r3, [r3, #0]
 80076f8:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80076fa:	687b      	ldr	r3, [r7, #4]
 80076fc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80076fe:	429a      	cmp	r2, r3
 8007700:	d207      	bcs.n	8007712 <prvAddNewTaskToReadyList+0xba>
		{
			taskYIELD_IF_USING_PREEMPTION();
 8007702:	4b0c      	ldr	r3, [pc, #48]	@ (8007734 <prvAddNewTaskToReadyList+0xdc>)
 8007704:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8007708:	601a      	str	r2, [r3, #0]
 800770a:	f3bf 8f4f 	dsb	sy
 800770e:	f3bf 8f6f 	isb	sy
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8007712:	bf00      	nop
 8007714:	3708      	adds	r7, #8
 8007716:	46bd      	mov	sp, r7
 8007718:	bd80      	pop	{r7, pc}
 800771a:	bf00      	nop
 800771c:	200014a4 	.word	0x200014a4
 8007720:	20000fd0 	.word	0x20000fd0
 8007724:	200014b0 	.word	0x200014b0
 8007728:	200014c0 	.word	0x200014c0
 800772c:	200014ac 	.word	0x200014ac
 8007730:	20000fd4 	.word	0x20000fd4
 8007734:	e000ed04 	.word	0xe000ed04

08007738 <vTaskDelay>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelay == 1 )

	void vTaskDelay( const TickType_t xTicksToDelay )
	{
 8007738:	b580      	push	{r7, lr}
 800773a:	b084      	sub	sp, #16
 800773c:	af00      	add	r7, sp, #0
 800773e:	6078      	str	r0, [r7, #4]
	BaseType_t xAlreadyYielded = pdFALSE;
 8007740:	2300      	movs	r3, #0
 8007742:	60fb      	str	r3, [r7, #12]

		/* A delay time of zero just forces a reschedule. */
		if( xTicksToDelay > ( TickType_t ) 0U )
 8007744:	687b      	ldr	r3, [r7, #4]
 8007746:	2b00      	cmp	r3, #0
 8007748:	d018      	beq.n	800777c <vTaskDelay+0x44>
		{
			configASSERT( uxSchedulerSuspended == 0 );
 800774a:	4b14      	ldr	r3, [pc, #80]	@ (800779c <vTaskDelay+0x64>)
 800774c:	681b      	ldr	r3, [r3, #0]
 800774e:	2b00      	cmp	r3, #0
 8007750:	d00b      	beq.n	800776a <vTaskDelay+0x32>
	__asm volatile
 8007752:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007756:	f383 8811 	msr	BASEPRI, r3
 800775a:	f3bf 8f6f 	isb	sy
 800775e:	f3bf 8f4f 	dsb	sy
 8007762:	60bb      	str	r3, [r7, #8]
}
 8007764:	bf00      	nop
 8007766:	bf00      	nop
 8007768:	e7fd      	b.n	8007766 <vTaskDelay+0x2e>
			vTaskSuspendAll();
 800776a:	f000 f88b 	bl	8007884 <vTaskSuspendAll>
				list or removed from the blocked list until the scheduler
				is resumed.

				This task cannot be in an event list as it is the currently
				executing task. */
				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
 800776e:	2100      	movs	r1, #0
 8007770:	6878      	ldr	r0, [r7, #4]
 8007772:	f000 fe09 	bl	8008388 <prvAddCurrentTaskToDelayedList>
			}
			xAlreadyYielded = xTaskResumeAll();
 8007776:	f000 f893 	bl	80078a0 <xTaskResumeAll>
 800777a:	60f8      	str	r0, [r7, #12]
			mtCOVERAGE_TEST_MARKER();
		}

		/* Force a reschedule if xTaskResumeAll has not already done so, we may
		have put ourselves to sleep. */
		if( xAlreadyYielded == pdFALSE )
 800777c:	68fb      	ldr	r3, [r7, #12]
 800777e:	2b00      	cmp	r3, #0
 8007780:	d107      	bne.n	8007792 <vTaskDelay+0x5a>
		{
			portYIELD_WITHIN_API();
 8007782:	4b07      	ldr	r3, [pc, #28]	@ (80077a0 <vTaskDelay+0x68>)
 8007784:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8007788:	601a      	str	r2, [r3, #0]
 800778a:	f3bf 8f4f 	dsb	sy
 800778e:	f3bf 8f6f 	isb	sy
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 8007792:	bf00      	nop
 8007794:	3710      	adds	r7, #16
 8007796:	46bd      	mov	sp, r7
 8007798:	bd80      	pop	{r7, pc}
 800779a:	bf00      	nop
 800779c:	200014cc 	.word	0x200014cc
 80077a0:	e000ed04 	.word	0xe000ed04

080077a4 <vTaskStartScheduler>:

#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/

void vTaskStartScheduler( void )
{
 80077a4:	b580      	push	{r7, lr}
 80077a6:	b08a      	sub	sp, #40	@ 0x28
 80077a8:	af04      	add	r7, sp, #16
BaseType_t xReturn;

	/* Add the idle task at the lowest priority. */
	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
	{
		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
 80077aa:	2300      	movs	r3, #0
 80077ac:	60bb      	str	r3, [r7, #8]
		StackType_t *pxIdleTaskStackBuffer = NULL;
 80077ae:	2300      	movs	r3, #0
 80077b0:	607b      	str	r3, [r7, #4]
		uint32_t ulIdleTaskStackSize;

		/* The Idle task is created using user provided RAM - obtain the
		address of the RAM then create the idle task. */
		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
 80077b2:	463a      	mov	r2, r7
 80077b4:	1d39      	adds	r1, r7, #4
 80077b6:	f107 0308 	add.w	r3, r7, #8
 80077ba:	4618      	mov	r0, r3
 80077bc:	f7fe fe28 	bl	8006410 <vApplicationGetIdleTaskMemory>
		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
 80077c0:	6839      	ldr	r1, [r7, #0]
 80077c2:	687b      	ldr	r3, [r7, #4]
 80077c4:	68ba      	ldr	r2, [r7, #8]
 80077c6:	9202      	str	r2, [sp, #8]
 80077c8:	9301      	str	r3, [sp, #4]
 80077ca:	2300      	movs	r3, #0
 80077cc:	9300      	str	r3, [sp, #0]
 80077ce:	2300      	movs	r3, #0
 80077d0:	460a      	mov	r2, r1
 80077d2:	4924      	ldr	r1, [pc, #144]	@ (8007864 <vTaskStartScheduler+0xc0>)
 80077d4:	4824      	ldr	r0, [pc, #144]	@ (8007868 <vTaskStartScheduler+0xc4>)
 80077d6:	f7ff fdf1 	bl	80073bc <xTaskCreateStatic>
 80077da:	4603      	mov	r3, r0
 80077dc:	4a23      	ldr	r2, [pc, #140]	@ (800786c <vTaskStartScheduler+0xc8>)
 80077de:	6013      	str	r3, [r2, #0]
												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
												pxIdleTaskStackBuffer,
												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */

		if( xIdleTaskHandle != NULL )
 80077e0:	4b22      	ldr	r3, [pc, #136]	@ (800786c <vTaskStartScheduler+0xc8>)
 80077e2:	681b      	ldr	r3, [r3, #0]
 80077e4:	2b00      	cmp	r3, #0
 80077e6:	d002      	beq.n	80077ee <vTaskStartScheduler+0x4a>
		{
			xReturn = pdPASS;
 80077e8:	2301      	movs	r3, #1
 80077ea:	617b      	str	r3, [r7, #20]
 80077ec:	e001      	b.n	80077f2 <vTaskStartScheduler+0x4e>
		}
		else
		{
			xReturn = pdFAIL;
 80077ee:	2300      	movs	r3, #0
 80077f0:	617b      	str	r3, [r7, #20]
	}
	#endif /* configSUPPORT_STATIC_ALLOCATION */

	#if ( configUSE_TIMERS == 1 )
	{
		if( xReturn == pdPASS )
 80077f2:	697b      	ldr	r3, [r7, #20]
 80077f4:	2b01      	cmp	r3, #1
 80077f6:	d102      	bne.n	80077fe <vTaskStartScheduler+0x5a>
		{
			xReturn = xTimerCreateTimerTask();
 80077f8:	f000 fe1a 	bl	8008430 <xTimerCreateTimerTask>
 80077fc:	6178      	str	r0, [r7, #20]
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif /* configUSE_TIMERS */

	if( xReturn == pdPASS )
 80077fe:	697b      	ldr	r3, [r7, #20]
 8007800:	2b01      	cmp	r3, #1
 8007802:	d11b      	bne.n	800783c <vTaskStartScheduler+0x98>
	__asm volatile
 8007804:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007808:	f383 8811 	msr	BASEPRI, r3
 800780c:	f3bf 8f6f 	isb	sy
 8007810:	f3bf 8f4f 	dsb	sy
 8007814:	613b      	str	r3, [r7, #16]
}
 8007816:	bf00      	nop
		{
			/* Switch Newlib's _impure_ptr variable to point to the _reent
			structure specific to the task that will run first.
			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 8007818:	4b15      	ldr	r3, [pc, #84]	@ (8007870 <vTaskStartScheduler+0xcc>)
 800781a:	681b      	ldr	r3, [r3, #0]
 800781c:	3354      	adds	r3, #84	@ 0x54
 800781e:	4a15      	ldr	r2, [pc, #84]	@ (8007874 <vTaskStartScheduler+0xd0>)
 8007820:	6013      	str	r3, [r2, #0]
		}
		#endif /* configUSE_NEWLIB_REENTRANT */

		xNextTaskUnblockTime = portMAX_DELAY;
 8007822:	4b15      	ldr	r3, [pc, #84]	@ (8007878 <vTaskStartScheduler+0xd4>)
 8007824:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8007828:	601a      	str	r2, [r3, #0]
		xSchedulerRunning = pdTRUE;
 800782a:	4b14      	ldr	r3, [pc, #80]	@ (800787c <vTaskStartScheduler+0xd8>)
 800782c:	2201      	movs	r2, #1
 800782e:	601a      	str	r2, [r3, #0]
		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
 8007830:	4b13      	ldr	r3, [pc, #76]	@ (8007880 <vTaskStartScheduler+0xdc>)
 8007832:	2200      	movs	r2, #0
 8007834:	601a      	str	r2, [r3, #0]

		traceTASK_SWITCHED_IN();

		/* Setting up the timer tick is hardware specific and thus in the
		portable interface. */
		if( xPortStartScheduler() != pdFALSE )
 8007836:	f001 f9e3 	bl	8008c00 <xPortStartScheduler>
	}

	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
	meaning xIdleTaskHandle is not used anywhere else. */
	( void ) xIdleTaskHandle;
}
 800783a:	e00f      	b.n	800785c <vTaskStartScheduler+0xb8>
		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
 800783c:	697b      	ldr	r3, [r7, #20]
 800783e:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8007842:	d10b      	bne.n	800785c <vTaskStartScheduler+0xb8>
	__asm volatile
 8007844:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007848:	f383 8811 	msr	BASEPRI, r3
 800784c:	f3bf 8f6f 	isb	sy
 8007850:	f3bf 8f4f 	dsb	sy
 8007854:	60fb      	str	r3, [r7, #12]
}
 8007856:	bf00      	nop
 8007858:	bf00      	nop
 800785a:	e7fd      	b.n	8007858 <vTaskStartScheduler+0xb4>
}
 800785c:	bf00      	nop
 800785e:	3718      	adds	r7, #24
 8007860:	46bd      	mov	sp, r7
 8007862:	bd80      	pop	{r7, pc}
 8007864:	0800958c 	.word	0x0800958c
 8007868:	08007eb5 	.word	0x08007eb5
 800786c:	200014c8 	.word	0x200014c8
 8007870:	20000fd0 	.word	0x20000fd0
 8007874:	20000010 	.word	0x20000010
 8007878:	200014c4 	.word	0x200014c4
 800787c:	200014b0 	.word	0x200014b0
 8007880:	200014a8 	.word	0x200014a8

08007884 <vTaskSuspendAll>:
	vPortEndScheduler();
}
/*----------------------------------------------------------*/

void vTaskSuspendAll( void )
{
 8007884:	b480      	push	{r7}
 8007886:	af00      	add	r7, sp, #0
	do not otherwise exhibit real time behaviour. */
	portSOFTWARE_BARRIER();

	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
	is used to allow calls to vTaskSuspendAll() to nest. */
	++uxSchedulerSuspended;
 8007888:	4b04      	ldr	r3, [pc, #16]	@ (800789c <vTaskSuspendAll+0x18>)
 800788a:	681b      	ldr	r3, [r3, #0]
 800788c:	3301      	adds	r3, #1
 800788e:	4a03      	ldr	r2, [pc, #12]	@ (800789c <vTaskSuspendAll+0x18>)
 8007890:	6013      	str	r3, [r2, #0]

	/* Enforces ordering for ports and optimised compilers that may otherwise place
	the above increment elsewhere. */
	portMEMORY_BARRIER();
}
 8007892:	bf00      	nop
 8007894:	46bd      	mov	sp, r7
 8007896:	f85d 7b04 	ldr.w	r7, [sp], #4
 800789a:	4770      	bx	lr
 800789c:	200014cc 	.word	0x200014cc

080078a0 <xTaskResumeAll>:

#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/

BaseType_t xTaskResumeAll( void )
{
 80078a0:	b580      	push	{r7, lr}
 80078a2:	b084      	sub	sp, #16
 80078a4:	af00      	add	r7, sp, #0
TCB_t *pxTCB = NULL;
 80078a6:	2300      	movs	r3, #0
 80078a8:	60fb      	str	r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
 80078aa:	2300      	movs	r3, #0
 80078ac:	60bb      	str	r3, [r7, #8]

	/* If uxSchedulerSuspended is zero then this function does not match a
	previous call to vTaskSuspendAll(). */
	configASSERT( uxSchedulerSuspended );
 80078ae:	4b42      	ldr	r3, [pc, #264]	@ (80079b8 <xTaskResumeAll+0x118>)
 80078b0:	681b      	ldr	r3, [r3, #0]
 80078b2:	2b00      	cmp	r3, #0
 80078b4:	d10b      	bne.n	80078ce <xTaskResumeAll+0x2e>
	__asm volatile
 80078b6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80078ba:	f383 8811 	msr	BASEPRI, r3
 80078be:	f3bf 8f6f 	isb	sy
 80078c2:	f3bf 8f4f 	dsb	sy
 80078c6:	603b      	str	r3, [r7, #0]
}
 80078c8:	bf00      	nop
 80078ca:	bf00      	nop
 80078cc:	e7fd      	b.n	80078ca <xTaskResumeAll+0x2a>
	/* It is possible that an ISR caused a task to be removed from an event
	list while the scheduler was suspended.  If this was the case then the
	removed task will have been added to the xPendingReadyList.  Once the
	scheduler has been resumed it is safe to move all the pending ready
	tasks from this list into their appropriate ready list. */
	taskENTER_CRITICAL();
 80078ce:	f001 fa3b 	bl	8008d48 <vPortEnterCritical>
	{
		--uxSchedulerSuspended;
 80078d2:	4b39      	ldr	r3, [pc, #228]	@ (80079b8 <xTaskResumeAll+0x118>)
 80078d4:	681b      	ldr	r3, [r3, #0]
 80078d6:	3b01      	subs	r3, #1
 80078d8:	4a37      	ldr	r2, [pc, #220]	@ (80079b8 <xTaskResumeAll+0x118>)
 80078da:	6013      	str	r3, [r2, #0]

		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 80078dc:	4b36      	ldr	r3, [pc, #216]	@ (80079b8 <xTaskResumeAll+0x118>)
 80078de:	681b      	ldr	r3, [r3, #0]
 80078e0:	2b00      	cmp	r3, #0
 80078e2:	d162      	bne.n	80079aa <xTaskResumeAll+0x10a>
		{
			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
 80078e4:	4b35      	ldr	r3, [pc, #212]	@ (80079bc <xTaskResumeAll+0x11c>)
 80078e6:	681b      	ldr	r3, [r3, #0]
 80078e8:	2b00      	cmp	r3, #0
 80078ea:	d05e      	beq.n	80079aa <xTaskResumeAll+0x10a>
			{
				/* Move any readied tasks from the pending list into the
				appropriate ready list. */
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 80078ec:	e02f      	b.n	800794e <xTaskResumeAll+0xae>
				{
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80078ee:	4b34      	ldr	r3, [pc, #208]	@ (80079c0 <xTaskResumeAll+0x120>)
 80078f0:	68db      	ldr	r3, [r3, #12]
 80078f2:	68db      	ldr	r3, [r3, #12]
 80078f4:	60fb      	str	r3, [r7, #12]
					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 80078f6:	68fb      	ldr	r3, [r7, #12]
 80078f8:	3318      	adds	r3, #24
 80078fa:	4618      	mov	r0, r3
 80078fc:	f7fe fe46 	bl	800658c <uxListRemove>
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8007900:	68fb      	ldr	r3, [r7, #12]
 8007902:	3304      	adds	r3, #4
 8007904:	4618      	mov	r0, r3
 8007906:	f7fe fe41 	bl	800658c <uxListRemove>
					prvAddTaskToReadyList( pxTCB );
 800790a:	68fb      	ldr	r3, [r7, #12]
 800790c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800790e:	4b2d      	ldr	r3, [pc, #180]	@ (80079c4 <xTaskResumeAll+0x124>)
 8007910:	681b      	ldr	r3, [r3, #0]
 8007912:	429a      	cmp	r2, r3
 8007914:	d903      	bls.n	800791e <xTaskResumeAll+0x7e>
 8007916:	68fb      	ldr	r3, [r7, #12]
 8007918:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800791a:	4a2a      	ldr	r2, [pc, #168]	@ (80079c4 <xTaskResumeAll+0x124>)
 800791c:	6013      	str	r3, [r2, #0]
 800791e:	68fb      	ldr	r3, [r7, #12]
 8007920:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007922:	4613      	mov	r3, r2
 8007924:	009b      	lsls	r3, r3, #2
 8007926:	4413      	add	r3, r2
 8007928:	009b      	lsls	r3, r3, #2
 800792a:	4a27      	ldr	r2, [pc, #156]	@ (80079c8 <xTaskResumeAll+0x128>)
 800792c:	441a      	add	r2, r3
 800792e:	68fb      	ldr	r3, [r7, #12]
 8007930:	3304      	adds	r3, #4
 8007932:	4619      	mov	r1, r3
 8007934:	4610      	mov	r0, r2
 8007936:	f7fe fdcc 	bl	80064d2 <vListInsertEnd>

					/* If the moved task has a priority higher than the current
					task then a yield must be performed. */
					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 800793a:	68fb      	ldr	r3, [r7, #12]
 800793c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800793e:	4b23      	ldr	r3, [pc, #140]	@ (80079cc <xTaskResumeAll+0x12c>)
 8007940:	681b      	ldr	r3, [r3, #0]
 8007942:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007944:	429a      	cmp	r2, r3
 8007946:	d302      	bcc.n	800794e <xTaskResumeAll+0xae>
					{
						xYieldPending = pdTRUE;
 8007948:	4b21      	ldr	r3, [pc, #132]	@ (80079d0 <xTaskResumeAll+0x130>)
 800794a:	2201      	movs	r2, #1
 800794c:	601a      	str	r2, [r3, #0]
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 800794e:	4b1c      	ldr	r3, [pc, #112]	@ (80079c0 <xTaskResumeAll+0x120>)
 8007950:	681b      	ldr	r3, [r3, #0]
 8007952:	2b00      	cmp	r3, #0
 8007954:	d1cb      	bne.n	80078ee <xTaskResumeAll+0x4e>
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( pxTCB != NULL )
 8007956:	68fb      	ldr	r3, [r7, #12]
 8007958:	2b00      	cmp	r3, #0
 800795a:	d001      	beq.n	8007960 <xTaskResumeAll+0xc0>
					which may have prevented the next unblock time from being
					re-calculated, in which case re-calculate it now.  Mainly
					important for low power tickless implementations, where
					this can prevent an unnecessary exit from low power
					state. */
					prvResetNextTaskUnblockTime();
 800795c:	f000 fb66 	bl	800802c <prvResetNextTaskUnblockTime>
				/* If any ticks occurred while the scheduler was suspended then
				they should be processed now.  This ensures the tick count does
				not	slip, and that any delayed tasks are resumed at the correct
				time. */
				{
					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
 8007960:	4b1c      	ldr	r3, [pc, #112]	@ (80079d4 <xTaskResumeAll+0x134>)
 8007962:	681b      	ldr	r3, [r3, #0]
 8007964:	607b      	str	r3, [r7, #4]

					if( xPendedCounts > ( TickType_t ) 0U )
 8007966:	687b      	ldr	r3, [r7, #4]
 8007968:	2b00      	cmp	r3, #0
 800796a:	d010      	beq.n	800798e <xTaskResumeAll+0xee>
					{
						do
						{
							if( xTaskIncrementTick() != pdFALSE )
 800796c:	f000 f846 	bl	80079fc <xTaskIncrementTick>
 8007970:	4603      	mov	r3, r0
 8007972:	2b00      	cmp	r3, #0
 8007974:	d002      	beq.n	800797c <xTaskResumeAll+0xdc>
							{
								xYieldPending = pdTRUE;
 8007976:	4b16      	ldr	r3, [pc, #88]	@ (80079d0 <xTaskResumeAll+0x130>)
 8007978:	2201      	movs	r2, #1
 800797a:	601a      	str	r2, [r3, #0]
							}
							else
							{
								mtCOVERAGE_TEST_MARKER();
							}
							--xPendedCounts;
 800797c:	687b      	ldr	r3, [r7, #4]
 800797e:	3b01      	subs	r3, #1
 8007980:	607b      	str	r3, [r7, #4]
						} while( xPendedCounts > ( TickType_t ) 0U );
 8007982:	687b      	ldr	r3, [r7, #4]
 8007984:	2b00      	cmp	r3, #0
 8007986:	d1f1      	bne.n	800796c <xTaskResumeAll+0xcc>

						xPendedTicks = 0;
 8007988:	4b12      	ldr	r3, [pc, #72]	@ (80079d4 <xTaskResumeAll+0x134>)
 800798a:	2200      	movs	r2, #0
 800798c:	601a      	str	r2, [r3, #0]
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( xYieldPending != pdFALSE )
 800798e:	4b10      	ldr	r3, [pc, #64]	@ (80079d0 <xTaskResumeAll+0x130>)
 8007990:	681b      	ldr	r3, [r3, #0]
 8007992:	2b00      	cmp	r3, #0
 8007994:	d009      	beq.n	80079aa <xTaskResumeAll+0x10a>
				{
					#if( configUSE_PREEMPTION != 0 )
					{
						xAlreadyYielded = pdTRUE;
 8007996:	2301      	movs	r3, #1
 8007998:	60bb      	str	r3, [r7, #8]
					}
					#endif
					taskYIELD_IF_USING_PREEMPTION();
 800799a:	4b0f      	ldr	r3, [pc, #60]	@ (80079d8 <xTaskResumeAll+0x138>)
 800799c:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80079a0:	601a      	str	r2, [r3, #0]
 80079a2:	f3bf 8f4f 	dsb	sy
 80079a6:	f3bf 8f6f 	isb	sy
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 80079aa:	f001 f9ff 	bl	8008dac <vPortExitCritical>

	return xAlreadyYielded;
 80079ae:	68bb      	ldr	r3, [r7, #8]
}
 80079b0:	4618      	mov	r0, r3
 80079b2:	3710      	adds	r7, #16
 80079b4:	46bd      	mov	sp, r7
 80079b6:	bd80      	pop	{r7, pc}
 80079b8:	200014cc 	.word	0x200014cc
 80079bc:	200014a4 	.word	0x200014a4
 80079c0:	20001464 	.word	0x20001464
 80079c4:	200014ac 	.word	0x200014ac
 80079c8:	20000fd4 	.word	0x20000fd4
 80079cc:	20000fd0 	.word	0x20000fd0
 80079d0:	200014b8 	.word	0x200014b8
 80079d4:	200014b4 	.word	0x200014b4
 80079d8:	e000ed04 	.word	0xe000ed04

080079dc <xTaskGetTickCount>:
/*-----------------------------------------------------------*/

TickType_t xTaskGetTickCount( void )
{
 80079dc:	b480      	push	{r7}
 80079de:	b083      	sub	sp, #12
 80079e0:	af00      	add	r7, sp, #0
TickType_t xTicks;

	/* Critical section required if running on a 16 bit processor. */
	portTICK_TYPE_ENTER_CRITICAL();
	{
		xTicks = xTickCount;
 80079e2:	4b05      	ldr	r3, [pc, #20]	@ (80079f8 <xTaskGetTickCount+0x1c>)
 80079e4:	681b      	ldr	r3, [r3, #0]
 80079e6:	607b      	str	r3, [r7, #4]
	}
	portTICK_TYPE_EXIT_CRITICAL();

	return xTicks;
 80079e8:	687b      	ldr	r3, [r7, #4]
}
 80079ea:	4618      	mov	r0, r3
 80079ec:	370c      	adds	r7, #12
 80079ee:	46bd      	mov	sp, r7
 80079f0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80079f4:	4770      	bx	lr
 80079f6:	bf00      	nop
 80079f8:	200014a8 	.word	0x200014a8

080079fc <xTaskIncrementTick>:

#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/

BaseType_t xTaskIncrementTick( void )
{
 80079fc:	b580      	push	{r7, lr}
 80079fe:	b086      	sub	sp, #24
 8007a00:	af00      	add	r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
 8007a02:	2300      	movs	r3, #0
 8007a04:	617b      	str	r3, [r7, #20]

	/* Called by the portable layer each time a tick interrupt occurs.
	Increments the tick then checks to see if the new tick value will cause any
	tasks to be unblocked. */
	traceTASK_INCREMENT_TICK( xTickCount );
	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8007a06:	4b4f      	ldr	r3, [pc, #316]	@ (8007b44 <xTaskIncrementTick+0x148>)
 8007a08:	681b      	ldr	r3, [r3, #0]
 8007a0a:	2b00      	cmp	r3, #0
 8007a0c:	f040 8090 	bne.w	8007b30 <xTaskIncrementTick+0x134>
	{
		/* Minor optimisation.  The tick count cannot change in this
		block. */
		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
 8007a10:	4b4d      	ldr	r3, [pc, #308]	@ (8007b48 <xTaskIncrementTick+0x14c>)
 8007a12:	681b      	ldr	r3, [r3, #0]
 8007a14:	3301      	adds	r3, #1
 8007a16:	613b      	str	r3, [r7, #16]

		/* Increment the RTOS tick, switching the delayed and overflowed
		delayed lists if it wraps to 0. */
		xTickCount = xConstTickCount;
 8007a18:	4a4b      	ldr	r2, [pc, #300]	@ (8007b48 <xTaskIncrementTick+0x14c>)
 8007a1a:	693b      	ldr	r3, [r7, #16]
 8007a1c:	6013      	str	r3, [r2, #0]

		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
 8007a1e:	693b      	ldr	r3, [r7, #16]
 8007a20:	2b00      	cmp	r3, #0
 8007a22:	d121      	bne.n	8007a68 <xTaskIncrementTick+0x6c>
		{
			taskSWITCH_DELAYED_LISTS();
 8007a24:	4b49      	ldr	r3, [pc, #292]	@ (8007b4c <xTaskIncrementTick+0x150>)
 8007a26:	681b      	ldr	r3, [r3, #0]
 8007a28:	681b      	ldr	r3, [r3, #0]
 8007a2a:	2b00      	cmp	r3, #0
 8007a2c:	d00b      	beq.n	8007a46 <xTaskIncrementTick+0x4a>
	__asm volatile
 8007a2e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007a32:	f383 8811 	msr	BASEPRI, r3
 8007a36:	f3bf 8f6f 	isb	sy
 8007a3a:	f3bf 8f4f 	dsb	sy
 8007a3e:	603b      	str	r3, [r7, #0]
}
 8007a40:	bf00      	nop
 8007a42:	bf00      	nop
 8007a44:	e7fd      	b.n	8007a42 <xTaskIncrementTick+0x46>
 8007a46:	4b41      	ldr	r3, [pc, #260]	@ (8007b4c <xTaskIncrementTick+0x150>)
 8007a48:	681b      	ldr	r3, [r3, #0]
 8007a4a:	60fb      	str	r3, [r7, #12]
 8007a4c:	4b40      	ldr	r3, [pc, #256]	@ (8007b50 <xTaskIncrementTick+0x154>)
 8007a4e:	681b      	ldr	r3, [r3, #0]
 8007a50:	4a3e      	ldr	r2, [pc, #248]	@ (8007b4c <xTaskIncrementTick+0x150>)
 8007a52:	6013      	str	r3, [r2, #0]
 8007a54:	4a3e      	ldr	r2, [pc, #248]	@ (8007b50 <xTaskIncrementTick+0x154>)
 8007a56:	68fb      	ldr	r3, [r7, #12]
 8007a58:	6013      	str	r3, [r2, #0]
 8007a5a:	4b3e      	ldr	r3, [pc, #248]	@ (8007b54 <xTaskIncrementTick+0x158>)
 8007a5c:	681b      	ldr	r3, [r3, #0]
 8007a5e:	3301      	adds	r3, #1
 8007a60:	4a3c      	ldr	r2, [pc, #240]	@ (8007b54 <xTaskIncrementTick+0x158>)
 8007a62:	6013      	str	r3, [r2, #0]
 8007a64:	f000 fae2 	bl	800802c <prvResetNextTaskUnblockTime>

		/* See if this tick has made a timeout expire.  Tasks are stored in
		the	queue in the order of their wake time - meaning once one task
		has been found whose block time has not expired there is no need to
		look any further down the list. */
		if( xConstTickCount >= xNextTaskUnblockTime )
 8007a68:	4b3b      	ldr	r3, [pc, #236]	@ (8007b58 <xTaskIncrementTick+0x15c>)
 8007a6a:	681b      	ldr	r3, [r3, #0]
 8007a6c:	693a      	ldr	r2, [r7, #16]
 8007a6e:	429a      	cmp	r2, r3
 8007a70:	d349      	bcc.n	8007b06 <xTaskIncrementTick+0x10a>
		{
			for( ;; )
			{
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8007a72:	4b36      	ldr	r3, [pc, #216]	@ (8007b4c <xTaskIncrementTick+0x150>)
 8007a74:	681b      	ldr	r3, [r3, #0]
 8007a76:	681b      	ldr	r3, [r3, #0]
 8007a78:	2b00      	cmp	r3, #0
 8007a7a:	d104      	bne.n	8007a86 <xTaskIncrementTick+0x8a>
					/* The delayed list is empty.  Set xNextTaskUnblockTime
					to the maximum possible value so it is extremely
					unlikely that the
					if( xTickCount >= xNextTaskUnblockTime ) test will pass
					next time through. */
					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8007a7c:	4b36      	ldr	r3, [pc, #216]	@ (8007b58 <xTaskIncrementTick+0x15c>)
 8007a7e:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8007a82:	601a      	str	r2, [r3, #0]
					break;
 8007a84:	e03f      	b.n	8007b06 <xTaskIncrementTick+0x10a>
				{
					/* The delayed list is not empty, get the value of the
					item at the head of the delayed list.  This is the time
					at which the task at the head of the delayed list must
					be removed from the Blocked state. */
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8007a86:	4b31      	ldr	r3, [pc, #196]	@ (8007b4c <xTaskIncrementTick+0x150>)
 8007a88:	681b      	ldr	r3, [r3, #0]
 8007a8a:	68db      	ldr	r3, [r3, #12]
 8007a8c:	68db      	ldr	r3, [r3, #12]
 8007a8e:	60bb      	str	r3, [r7, #8]
					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 8007a90:	68bb      	ldr	r3, [r7, #8]
 8007a92:	685b      	ldr	r3, [r3, #4]
 8007a94:	607b      	str	r3, [r7, #4]

					if( xConstTickCount < xItemValue )
 8007a96:	693a      	ldr	r2, [r7, #16]
 8007a98:	687b      	ldr	r3, [r7, #4]
 8007a9a:	429a      	cmp	r2, r3
 8007a9c:	d203      	bcs.n	8007aa6 <xTaskIncrementTick+0xaa>
						/* It is not time to unblock this item yet, but the
						item value is the time at which the task at the head
						of the blocked list must be removed from the Blocked
						state -	so record the item value in
						xNextTaskUnblockTime. */
						xNextTaskUnblockTime = xItemValue;
 8007a9e:	4a2e      	ldr	r2, [pc, #184]	@ (8007b58 <xTaskIncrementTick+0x15c>)
 8007aa0:	687b      	ldr	r3, [r7, #4]
 8007aa2:	6013      	str	r3, [r2, #0]
						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
 8007aa4:	e02f      	b.n	8007b06 <xTaskIncrementTick+0x10a>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* It is time to remove the item from the Blocked state. */
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8007aa6:	68bb      	ldr	r3, [r7, #8]
 8007aa8:	3304      	adds	r3, #4
 8007aaa:	4618      	mov	r0, r3
 8007aac:	f7fe fd6e 	bl	800658c <uxListRemove>

					/* Is the task waiting on an event also?  If so remove
					it from the event list. */
					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
 8007ab0:	68bb      	ldr	r3, [r7, #8]
 8007ab2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8007ab4:	2b00      	cmp	r3, #0
 8007ab6:	d004      	beq.n	8007ac2 <xTaskIncrementTick+0xc6>
					{
						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 8007ab8:	68bb      	ldr	r3, [r7, #8]
 8007aba:	3318      	adds	r3, #24
 8007abc:	4618      	mov	r0, r3
 8007abe:	f7fe fd65 	bl	800658c <uxListRemove>
						mtCOVERAGE_TEST_MARKER();
					}

					/* Place the unblocked task into the appropriate ready
					list. */
					prvAddTaskToReadyList( pxTCB );
 8007ac2:	68bb      	ldr	r3, [r7, #8]
 8007ac4:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007ac6:	4b25      	ldr	r3, [pc, #148]	@ (8007b5c <xTaskIncrementTick+0x160>)
 8007ac8:	681b      	ldr	r3, [r3, #0]
 8007aca:	429a      	cmp	r2, r3
 8007acc:	d903      	bls.n	8007ad6 <xTaskIncrementTick+0xda>
 8007ace:	68bb      	ldr	r3, [r7, #8]
 8007ad0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007ad2:	4a22      	ldr	r2, [pc, #136]	@ (8007b5c <xTaskIncrementTick+0x160>)
 8007ad4:	6013      	str	r3, [r2, #0]
 8007ad6:	68bb      	ldr	r3, [r7, #8]
 8007ad8:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007ada:	4613      	mov	r3, r2
 8007adc:	009b      	lsls	r3, r3, #2
 8007ade:	4413      	add	r3, r2
 8007ae0:	009b      	lsls	r3, r3, #2
 8007ae2:	4a1f      	ldr	r2, [pc, #124]	@ (8007b60 <xTaskIncrementTick+0x164>)
 8007ae4:	441a      	add	r2, r3
 8007ae6:	68bb      	ldr	r3, [r7, #8]
 8007ae8:	3304      	adds	r3, #4
 8007aea:	4619      	mov	r1, r3
 8007aec:	4610      	mov	r0, r2
 8007aee:	f7fe fcf0 	bl	80064d2 <vListInsertEnd>
					{
						/* Preemption is on, but a context switch should
						only be performed if the unblocked task has a
						priority that is equal to or higher than the
						currently executing task. */
						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 8007af2:	68bb      	ldr	r3, [r7, #8]
 8007af4:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007af6:	4b1b      	ldr	r3, [pc, #108]	@ (8007b64 <xTaskIncrementTick+0x168>)
 8007af8:	681b      	ldr	r3, [r3, #0]
 8007afa:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007afc:	429a      	cmp	r2, r3
 8007afe:	d3b8      	bcc.n	8007a72 <xTaskIncrementTick+0x76>
						{
							xSwitchRequired = pdTRUE;
 8007b00:	2301      	movs	r3, #1
 8007b02:	617b      	str	r3, [r7, #20]
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8007b04:	e7b5      	b.n	8007a72 <xTaskIncrementTick+0x76>
		/* Tasks of equal priority to the currently running task will share
		processing time (time slice) if preemption is on, and the application
		writer has not explicitly turned time slicing off. */
		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
		{
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
 8007b06:	4b17      	ldr	r3, [pc, #92]	@ (8007b64 <xTaskIncrementTick+0x168>)
 8007b08:	681b      	ldr	r3, [r3, #0]
 8007b0a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007b0c:	4914      	ldr	r1, [pc, #80]	@ (8007b60 <xTaskIncrementTick+0x164>)
 8007b0e:	4613      	mov	r3, r2
 8007b10:	009b      	lsls	r3, r3, #2
 8007b12:	4413      	add	r3, r2
 8007b14:	009b      	lsls	r3, r3, #2
 8007b16:	440b      	add	r3, r1
 8007b18:	681b      	ldr	r3, [r3, #0]
 8007b1a:	2b01      	cmp	r3, #1
 8007b1c:	d901      	bls.n	8007b22 <xTaskIncrementTick+0x126>
			{
				xSwitchRequired = pdTRUE;
 8007b1e:	2301      	movs	r3, #1
 8007b20:	617b      	str	r3, [r7, #20]
		}
		#endif /* configUSE_TICK_HOOK */

		#if ( configUSE_PREEMPTION == 1 )
		{
			if( xYieldPending != pdFALSE )
 8007b22:	4b11      	ldr	r3, [pc, #68]	@ (8007b68 <xTaskIncrementTick+0x16c>)
 8007b24:	681b      	ldr	r3, [r3, #0]
 8007b26:	2b00      	cmp	r3, #0
 8007b28:	d007      	beq.n	8007b3a <xTaskIncrementTick+0x13e>
			{
				xSwitchRequired = pdTRUE;
 8007b2a:	2301      	movs	r3, #1
 8007b2c:	617b      	str	r3, [r7, #20]
 8007b2e:	e004      	b.n	8007b3a <xTaskIncrementTick+0x13e>
		}
		#endif /* configUSE_PREEMPTION */
	}
	else
	{
		++xPendedTicks;
 8007b30:	4b0e      	ldr	r3, [pc, #56]	@ (8007b6c <xTaskIncrementTick+0x170>)
 8007b32:	681b      	ldr	r3, [r3, #0]
 8007b34:	3301      	adds	r3, #1
 8007b36:	4a0d      	ldr	r2, [pc, #52]	@ (8007b6c <xTaskIncrementTick+0x170>)
 8007b38:	6013      	str	r3, [r2, #0]
			vApplicationTickHook();
		}
		#endif
	}

	return xSwitchRequired;
 8007b3a:	697b      	ldr	r3, [r7, #20]
}
 8007b3c:	4618      	mov	r0, r3
 8007b3e:	3718      	adds	r7, #24
 8007b40:	46bd      	mov	sp, r7
 8007b42:	bd80      	pop	{r7, pc}
 8007b44:	200014cc 	.word	0x200014cc
 8007b48:	200014a8 	.word	0x200014a8
 8007b4c:	2000145c 	.word	0x2000145c
 8007b50:	20001460 	.word	0x20001460
 8007b54:	200014bc 	.word	0x200014bc
 8007b58:	200014c4 	.word	0x200014c4
 8007b5c:	200014ac 	.word	0x200014ac
 8007b60:	20000fd4 	.word	0x20000fd4
 8007b64:	20000fd0 	.word	0x20000fd0
 8007b68:	200014b8 	.word	0x200014b8
 8007b6c:	200014b4 	.word	0x200014b4

08007b70 <vTaskSwitchContext>:

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

void vTaskSwitchContext( void )
{
 8007b70:	b480      	push	{r7}
 8007b72:	b085      	sub	sp, #20
 8007b74:	af00      	add	r7, sp, #0
	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
 8007b76:	4b2b      	ldr	r3, [pc, #172]	@ (8007c24 <vTaskSwitchContext+0xb4>)
 8007b78:	681b      	ldr	r3, [r3, #0]
 8007b7a:	2b00      	cmp	r3, #0
 8007b7c:	d003      	beq.n	8007b86 <vTaskSwitchContext+0x16>
	{
		/* The scheduler is currently suspended - do not allow a context
		switch. */
		xYieldPending = pdTRUE;
 8007b7e:	4b2a      	ldr	r3, [pc, #168]	@ (8007c28 <vTaskSwitchContext+0xb8>)
 8007b80:	2201      	movs	r2, #1
 8007b82:	601a      	str	r2, [r3, #0]
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
		}
		#endif /* configUSE_NEWLIB_REENTRANT */
	}
}
 8007b84:	e047      	b.n	8007c16 <vTaskSwitchContext+0xa6>
		xYieldPending = pdFALSE;
 8007b86:	4b28      	ldr	r3, [pc, #160]	@ (8007c28 <vTaskSwitchContext+0xb8>)
 8007b88:	2200      	movs	r2, #0
 8007b8a:	601a      	str	r2, [r3, #0]
		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8007b8c:	4b27      	ldr	r3, [pc, #156]	@ (8007c2c <vTaskSwitchContext+0xbc>)
 8007b8e:	681b      	ldr	r3, [r3, #0]
 8007b90:	60fb      	str	r3, [r7, #12]
 8007b92:	e011      	b.n	8007bb8 <vTaskSwitchContext+0x48>
 8007b94:	68fb      	ldr	r3, [r7, #12]
 8007b96:	2b00      	cmp	r3, #0
 8007b98:	d10b      	bne.n	8007bb2 <vTaskSwitchContext+0x42>
	__asm volatile
 8007b9a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007b9e:	f383 8811 	msr	BASEPRI, r3
 8007ba2:	f3bf 8f6f 	isb	sy
 8007ba6:	f3bf 8f4f 	dsb	sy
 8007baa:	607b      	str	r3, [r7, #4]
}
 8007bac:	bf00      	nop
 8007bae:	bf00      	nop
 8007bb0:	e7fd      	b.n	8007bae <vTaskSwitchContext+0x3e>
 8007bb2:	68fb      	ldr	r3, [r7, #12]
 8007bb4:	3b01      	subs	r3, #1
 8007bb6:	60fb      	str	r3, [r7, #12]
 8007bb8:	491d      	ldr	r1, [pc, #116]	@ (8007c30 <vTaskSwitchContext+0xc0>)
 8007bba:	68fa      	ldr	r2, [r7, #12]
 8007bbc:	4613      	mov	r3, r2
 8007bbe:	009b      	lsls	r3, r3, #2
 8007bc0:	4413      	add	r3, r2
 8007bc2:	009b      	lsls	r3, r3, #2
 8007bc4:	440b      	add	r3, r1
 8007bc6:	681b      	ldr	r3, [r3, #0]
 8007bc8:	2b00      	cmp	r3, #0
 8007bca:	d0e3      	beq.n	8007b94 <vTaskSwitchContext+0x24>
 8007bcc:	68fa      	ldr	r2, [r7, #12]
 8007bce:	4613      	mov	r3, r2
 8007bd0:	009b      	lsls	r3, r3, #2
 8007bd2:	4413      	add	r3, r2
 8007bd4:	009b      	lsls	r3, r3, #2
 8007bd6:	4a16      	ldr	r2, [pc, #88]	@ (8007c30 <vTaskSwitchContext+0xc0>)
 8007bd8:	4413      	add	r3, r2
 8007bda:	60bb      	str	r3, [r7, #8]
 8007bdc:	68bb      	ldr	r3, [r7, #8]
 8007bde:	685b      	ldr	r3, [r3, #4]
 8007be0:	685a      	ldr	r2, [r3, #4]
 8007be2:	68bb      	ldr	r3, [r7, #8]
 8007be4:	605a      	str	r2, [r3, #4]
 8007be6:	68bb      	ldr	r3, [r7, #8]
 8007be8:	685a      	ldr	r2, [r3, #4]
 8007bea:	68bb      	ldr	r3, [r7, #8]
 8007bec:	3308      	adds	r3, #8
 8007bee:	429a      	cmp	r2, r3
 8007bf0:	d104      	bne.n	8007bfc <vTaskSwitchContext+0x8c>
 8007bf2:	68bb      	ldr	r3, [r7, #8]
 8007bf4:	685b      	ldr	r3, [r3, #4]
 8007bf6:	685a      	ldr	r2, [r3, #4]
 8007bf8:	68bb      	ldr	r3, [r7, #8]
 8007bfa:	605a      	str	r2, [r3, #4]
 8007bfc:	68bb      	ldr	r3, [r7, #8]
 8007bfe:	685b      	ldr	r3, [r3, #4]
 8007c00:	68db      	ldr	r3, [r3, #12]
 8007c02:	4a0c      	ldr	r2, [pc, #48]	@ (8007c34 <vTaskSwitchContext+0xc4>)
 8007c04:	6013      	str	r3, [r2, #0]
 8007c06:	4a09      	ldr	r2, [pc, #36]	@ (8007c2c <vTaskSwitchContext+0xbc>)
 8007c08:	68fb      	ldr	r3, [r7, #12]
 8007c0a:	6013      	str	r3, [r2, #0]
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 8007c0c:	4b09      	ldr	r3, [pc, #36]	@ (8007c34 <vTaskSwitchContext+0xc4>)
 8007c0e:	681b      	ldr	r3, [r3, #0]
 8007c10:	3354      	adds	r3, #84	@ 0x54
 8007c12:	4a09      	ldr	r2, [pc, #36]	@ (8007c38 <vTaskSwitchContext+0xc8>)
 8007c14:	6013      	str	r3, [r2, #0]
}
 8007c16:	bf00      	nop
 8007c18:	3714      	adds	r7, #20
 8007c1a:	46bd      	mov	sp, r7
 8007c1c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007c20:	4770      	bx	lr
 8007c22:	bf00      	nop
 8007c24:	200014cc 	.word	0x200014cc
 8007c28:	200014b8 	.word	0x200014b8
 8007c2c:	200014ac 	.word	0x200014ac
 8007c30:	20000fd4 	.word	0x20000fd4
 8007c34:	20000fd0 	.word	0x20000fd0
 8007c38:	20000010 	.word	0x20000010

08007c3c <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/

void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
 8007c3c:	b580      	push	{r7, lr}
 8007c3e:	b084      	sub	sp, #16
 8007c40:	af00      	add	r7, sp, #0
 8007c42:	6078      	str	r0, [r7, #4]
 8007c44:	6039      	str	r1, [r7, #0]
	configASSERT( pxEventList );
 8007c46:	687b      	ldr	r3, [r7, #4]
 8007c48:	2b00      	cmp	r3, #0
 8007c4a:	d10b      	bne.n	8007c64 <vTaskPlaceOnEventList+0x28>
	__asm volatile
 8007c4c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007c50:	f383 8811 	msr	BASEPRI, r3
 8007c54:	f3bf 8f6f 	isb	sy
 8007c58:	f3bf 8f4f 	dsb	sy
 8007c5c:	60fb      	str	r3, [r7, #12]
}
 8007c5e:	bf00      	nop
 8007c60:	bf00      	nop
 8007c62:	e7fd      	b.n	8007c60 <vTaskPlaceOnEventList+0x24>

	/* Place the event list item of the TCB in the appropriate event list.
	This is placed in the list in priority order so the highest priority task
	is the first to be woken by the event.  The queue that contains the event
	list is locked, preventing simultaneous access from interrupts. */
	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8007c64:	4b07      	ldr	r3, [pc, #28]	@ (8007c84 <vTaskPlaceOnEventList+0x48>)
 8007c66:	681b      	ldr	r3, [r3, #0]
 8007c68:	3318      	adds	r3, #24
 8007c6a:	4619      	mov	r1, r3
 8007c6c:	6878      	ldr	r0, [r7, #4]
 8007c6e:	f7fe fc54 	bl	800651a <vListInsert>

	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 8007c72:	2101      	movs	r1, #1
 8007c74:	6838      	ldr	r0, [r7, #0]
 8007c76:	f000 fb87 	bl	8008388 <prvAddCurrentTaskToDelayedList>
}
 8007c7a:	bf00      	nop
 8007c7c:	3710      	adds	r7, #16
 8007c7e:	46bd      	mov	sp, r7
 8007c80:	bd80      	pop	{r7, pc}
 8007c82:	bf00      	nop
 8007c84:	20000fd0 	.word	0x20000fd0

08007c88 <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/

#if( configUSE_TIMERS == 1 )

	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8007c88:	b580      	push	{r7, lr}
 8007c8a:	b086      	sub	sp, #24
 8007c8c:	af00      	add	r7, sp, #0
 8007c8e:	60f8      	str	r0, [r7, #12]
 8007c90:	60b9      	str	r1, [r7, #8]
 8007c92:	607a      	str	r2, [r7, #4]
		configASSERT( pxEventList );
 8007c94:	68fb      	ldr	r3, [r7, #12]
 8007c96:	2b00      	cmp	r3, #0
 8007c98:	d10b      	bne.n	8007cb2 <vTaskPlaceOnEventListRestricted+0x2a>
	__asm volatile
 8007c9a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007c9e:	f383 8811 	msr	BASEPRI, r3
 8007ca2:	f3bf 8f6f 	isb	sy
 8007ca6:	f3bf 8f4f 	dsb	sy
 8007caa:	617b      	str	r3, [r7, #20]
}
 8007cac:	bf00      	nop
 8007cae:	bf00      	nop
 8007cb0:	e7fd      	b.n	8007cae <vTaskPlaceOnEventListRestricted+0x26>

		/* Place the event list item of the TCB in the appropriate event list.
		In this case it is assume that this is the only task that is going to
		be waiting on this event list, so the faster vListInsertEnd() function
		can be used in place of vListInsert. */
		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8007cb2:	4b0a      	ldr	r3, [pc, #40]	@ (8007cdc <vTaskPlaceOnEventListRestricted+0x54>)
 8007cb4:	681b      	ldr	r3, [r3, #0]
 8007cb6:	3318      	adds	r3, #24
 8007cb8:	4619      	mov	r1, r3
 8007cba:	68f8      	ldr	r0, [r7, #12]
 8007cbc:	f7fe fc09 	bl	80064d2 <vListInsertEnd>

		/* If the task should block indefinitely then set the block time to a
		value that will be recognised as an indefinite delay inside the
		prvAddCurrentTaskToDelayedList() function. */
		if( xWaitIndefinitely != pdFALSE )
 8007cc0:	687b      	ldr	r3, [r7, #4]
 8007cc2:	2b00      	cmp	r3, #0
 8007cc4:	d002      	beq.n	8007ccc <vTaskPlaceOnEventListRestricted+0x44>
		{
			xTicksToWait = portMAX_DELAY;
 8007cc6:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8007cca:	60bb      	str	r3, [r7, #8]
		}

		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
 8007ccc:	6879      	ldr	r1, [r7, #4]
 8007cce:	68b8      	ldr	r0, [r7, #8]
 8007cd0:	f000 fb5a 	bl	8008388 <prvAddCurrentTaskToDelayedList>
	}
 8007cd4:	bf00      	nop
 8007cd6:	3718      	adds	r7, #24
 8007cd8:	46bd      	mov	sp, r7
 8007cda:	bd80      	pop	{r7, pc}
 8007cdc:	20000fd0 	.word	0x20000fd0

08007ce0 <xTaskRemoveFromEventList>:

#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/

BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
 8007ce0:	b580      	push	{r7, lr}
 8007ce2:	b086      	sub	sp, #24
 8007ce4:	af00      	add	r7, sp, #0
 8007ce6:	6078      	str	r0, [r7, #4]
	get called - the lock count on the queue will get modified instead.  This
	means exclusive access to the event list is guaranteed here.

	This function assumes that a check has already been made to ensure that
	pxEventList is not empty. */
	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8007ce8:	687b      	ldr	r3, [r7, #4]
 8007cea:	68db      	ldr	r3, [r3, #12]
 8007cec:	68db      	ldr	r3, [r3, #12]
 8007cee:	613b      	str	r3, [r7, #16]
	configASSERT( pxUnblockedTCB );
 8007cf0:	693b      	ldr	r3, [r7, #16]
 8007cf2:	2b00      	cmp	r3, #0
 8007cf4:	d10b      	bne.n	8007d0e <xTaskRemoveFromEventList+0x2e>
	__asm volatile
 8007cf6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007cfa:	f383 8811 	msr	BASEPRI, r3
 8007cfe:	f3bf 8f6f 	isb	sy
 8007d02:	f3bf 8f4f 	dsb	sy
 8007d06:	60fb      	str	r3, [r7, #12]
}
 8007d08:	bf00      	nop
 8007d0a:	bf00      	nop
 8007d0c:	e7fd      	b.n	8007d0a <xTaskRemoveFromEventList+0x2a>
	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
 8007d0e:	693b      	ldr	r3, [r7, #16]
 8007d10:	3318      	adds	r3, #24
 8007d12:	4618      	mov	r0, r3
 8007d14:	f7fe fc3a 	bl	800658c <uxListRemove>

	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8007d18:	4b1d      	ldr	r3, [pc, #116]	@ (8007d90 <xTaskRemoveFromEventList+0xb0>)
 8007d1a:	681b      	ldr	r3, [r3, #0]
 8007d1c:	2b00      	cmp	r3, #0
 8007d1e:	d11d      	bne.n	8007d5c <xTaskRemoveFromEventList+0x7c>
	{
		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
 8007d20:	693b      	ldr	r3, [r7, #16]
 8007d22:	3304      	adds	r3, #4
 8007d24:	4618      	mov	r0, r3
 8007d26:	f7fe fc31 	bl	800658c <uxListRemove>
		prvAddTaskToReadyList( pxUnblockedTCB );
 8007d2a:	693b      	ldr	r3, [r7, #16]
 8007d2c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007d2e:	4b19      	ldr	r3, [pc, #100]	@ (8007d94 <xTaskRemoveFromEventList+0xb4>)
 8007d30:	681b      	ldr	r3, [r3, #0]
 8007d32:	429a      	cmp	r2, r3
 8007d34:	d903      	bls.n	8007d3e <xTaskRemoveFromEventList+0x5e>
 8007d36:	693b      	ldr	r3, [r7, #16]
 8007d38:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007d3a:	4a16      	ldr	r2, [pc, #88]	@ (8007d94 <xTaskRemoveFromEventList+0xb4>)
 8007d3c:	6013      	str	r3, [r2, #0]
 8007d3e:	693b      	ldr	r3, [r7, #16]
 8007d40:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007d42:	4613      	mov	r3, r2
 8007d44:	009b      	lsls	r3, r3, #2
 8007d46:	4413      	add	r3, r2
 8007d48:	009b      	lsls	r3, r3, #2
 8007d4a:	4a13      	ldr	r2, [pc, #76]	@ (8007d98 <xTaskRemoveFromEventList+0xb8>)
 8007d4c:	441a      	add	r2, r3
 8007d4e:	693b      	ldr	r3, [r7, #16]
 8007d50:	3304      	adds	r3, #4
 8007d52:	4619      	mov	r1, r3
 8007d54:	4610      	mov	r0, r2
 8007d56:	f7fe fbbc 	bl	80064d2 <vListInsertEnd>
 8007d5a:	e005      	b.n	8007d68 <xTaskRemoveFromEventList+0x88>
	}
	else
	{
		/* The delayed and ready lists cannot be accessed, so hold this task
		pending until the scheduler is resumed. */
		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
 8007d5c:	693b      	ldr	r3, [r7, #16]
 8007d5e:	3318      	adds	r3, #24
 8007d60:	4619      	mov	r1, r3
 8007d62:	480e      	ldr	r0, [pc, #56]	@ (8007d9c <xTaskRemoveFromEventList+0xbc>)
 8007d64:	f7fe fbb5 	bl	80064d2 <vListInsertEnd>
	}

	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
 8007d68:	693b      	ldr	r3, [r7, #16]
 8007d6a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007d6c:	4b0c      	ldr	r3, [pc, #48]	@ (8007da0 <xTaskRemoveFromEventList+0xc0>)
 8007d6e:	681b      	ldr	r3, [r3, #0]
 8007d70:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007d72:	429a      	cmp	r2, r3
 8007d74:	d905      	bls.n	8007d82 <xTaskRemoveFromEventList+0xa2>
	{
		/* Return true if the task removed from the event list has a higher
		priority than the calling task.  This allows the calling task to know if
		it should force a context switch now. */
		xReturn = pdTRUE;
 8007d76:	2301      	movs	r3, #1
 8007d78:	617b      	str	r3, [r7, #20]

		/* Mark that a yield is pending in case the user is not using the
		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
		xYieldPending = pdTRUE;
 8007d7a:	4b0a      	ldr	r3, [pc, #40]	@ (8007da4 <xTaskRemoveFromEventList+0xc4>)
 8007d7c:	2201      	movs	r2, #1
 8007d7e:	601a      	str	r2, [r3, #0]
 8007d80:	e001      	b.n	8007d86 <xTaskRemoveFromEventList+0xa6>
	}
	else
	{
		xReturn = pdFALSE;
 8007d82:	2300      	movs	r3, #0
 8007d84:	617b      	str	r3, [r7, #20]
	}

	return xReturn;
 8007d86:	697b      	ldr	r3, [r7, #20]
}
 8007d88:	4618      	mov	r0, r3
 8007d8a:	3718      	adds	r7, #24
 8007d8c:	46bd      	mov	sp, r7
 8007d8e:	bd80      	pop	{r7, pc}
 8007d90:	200014cc 	.word	0x200014cc
 8007d94:	200014ac 	.word	0x200014ac
 8007d98:	20000fd4 	.word	0x20000fd4
 8007d9c:	20001464 	.word	0x20001464
 8007da0:	20000fd0 	.word	0x20000fd0
 8007da4:	200014b8 	.word	0x200014b8

08007da8 <vTaskInternalSetTimeOutState>:
	taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/

void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
 8007da8:	b480      	push	{r7}
 8007daa:	b083      	sub	sp, #12
 8007dac:	af00      	add	r7, sp, #0
 8007dae:	6078      	str	r0, [r7, #4]
	/* For internal use only as it does not use a critical section. */
	pxTimeOut->xOverflowCount = xNumOfOverflows;
 8007db0:	4b06      	ldr	r3, [pc, #24]	@ (8007dcc <vTaskInternalSetTimeOutState+0x24>)
 8007db2:	681a      	ldr	r2, [r3, #0]
 8007db4:	687b      	ldr	r3, [r7, #4]
 8007db6:	601a      	str	r2, [r3, #0]
	pxTimeOut->xTimeOnEntering = xTickCount;
 8007db8:	4b05      	ldr	r3, [pc, #20]	@ (8007dd0 <vTaskInternalSetTimeOutState+0x28>)
 8007dba:	681a      	ldr	r2, [r3, #0]
 8007dbc:	687b      	ldr	r3, [r7, #4]
 8007dbe:	605a      	str	r2, [r3, #4]
}
 8007dc0:	bf00      	nop
 8007dc2:	370c      	adds	r7, #12
 8007dc4:	46bd      	mov	sp, r7
 8007dc6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007dca:	4770      	bx	lr
 8007dcc:	200014bc 	.word	0x200014bc
 8007dd0:	200014a8 	.word	0x200014a8

08007dd4 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/

BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
 8007dd4:	b580      	push	{r7, lr}
 8007dd6:	b088      	sub	sp, #32
 8007dd8:	af00      	add	r7, sp, #0
 8007dda:	6078      	str	r0, [r7, #4]
 8007ddc:	6039      	str	r1, [r7, #0]
BaseType_t xReturn;

	configASSERT( pxTimeOut );
 8007dde:	687b      	ldr	r3, [r7, #4]
 8007de0:	2b00      	cmp	r3, #0
 8007de2:	d10b      	bne.n	8007dfc <xTaskCheckForTimeOut+0x28>
	__asm volatile
 8007de4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007de8:	f383 8811 	msr	BASEPRI, r3
 8007dec:	f3bf 8f6f 	isb	sy
 8007df0:	f3bf 8f4f 	dsb	sy
 8007df4:	613b      	str	r3, [r7, #16]
}
 8007df6:	bf00      	nop
 8007df8:	bf00      	nop
 8007dfa:	e7fd      	b.n	8007df8 <xTaskCheckForTimeOut+0x24>
	configASSERT( pxTicksToWait );
 8007dfc:	683b      	ldr	r3, [r7, #0]
 8007dfe:	2b00      	cmp	r3, #0
 8007e00:	d10b      	bne.n	8007e1a <xTaskCheckForTimeOut+0x46>
	__asm volatile
 8007e02:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8007e06:	f383 8811 	msr	BASEPRI, r3
 8007e0a:	f3bf 8f6f 	isb	sy
 8007e0e:	f3bf 8f4f 	dsb	sy
 8007e12:	60fb      	str	r3, [r7, #12]
}
 8007e14:	bf00      	nop
 8007e16:	bf00      	nop
 8007e18:	e7fd      	b.n	8007e16 <xTaskCheckForTimeOut+0x42>

	taskENTER_CRITICAL();
 8007e1a:	f000 ff95 	bl	8008d48 <vPortEnterCritical>
	{
		/* Minor optimisation.  The tick count cannot change in this block. */
		const TickType_t xConstTickCount = xTickCount;
 8007e1e:	4b1d      	ldr	r3, [pc, #116]	@ (8007e94 <xTaskCheckForTimeOut+0xc0>)
 8007e20:	681b      	ldr	r3, [r3, #0]
 8007e22:	61bb      	str	r3, [r7, #24]
		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
 8007e24:	687b      	ldr	r3, [r7, #4]
 8007e26:	685b      	ldr	r3, [r3, #4]
 8007e28:	69ba      	ldr	r2, [r7, #24]
 8007e2a:	1ad3      	subs	r3, r2, r3
 8007e2c:	617b      	str	r3, [r7, #20]
			}
			else
		#endif

		#if ( INCLUDE_vTaskSuspend == 1 )
			if( *pxTicksToWait == portMAX_DELAY )
 8007e2e:	683b      	ldr	r3, [r7, #0]
 8007e30:	681b      	ldr	r3, [r3, #0]
 8007e32:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8007e36:	d102      	bne.n	8007e3e <xTaskCheckForTimeOut+0x6a>
			{
				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
				specified is the maximum block time then the task should block
				indefinitely, and therefore never time out. */
				xReturn = pdFALSE;
 8007e38:	2300      	movs	r3, #0
 8007e3a:	61fb      	str	r3, [r7, #28]
 8007e3c:	e023      	b.n	8007e86 <xTaskCheckForTimeOut+0xb2>
			}
			else
		#endif

		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
 8007e3e:	687b      	ldr	r3, [r7, #4]
 8007e40:	681a      	ldr	r2, [r3, #0]
 8007e42:	4b15      	ldr	r3, [pc, #84]	@ (8007e98 <xTaskCheckForTimeOut+0xc4>)
 8007e44:	681b      	ldr	r3, [r3, #0]
 8007e46:	429a      	cmp	r2, r3
 8007e48:	d007      	beq.n	8007e5a <xTaskCheckForTimeOut+0x86>
 8007e4a:	687b      	ldr	r3, [r7, #4]
 8007e4c:	685b      	ldr	r3, [r3, #4]
 8007e4e:	69ba      	ldr	r2, [r7, #24]
 8007e50:	429a      	cmp	r2, r3
 8007e52:	d302      	bcc.n	8007e5a <xTaskCheckForTimeOut+0x86>
			/* The tick count is greater than the time at which
			vTaskSetTimeout() was called, but has also overflowed since
			vTaskSetTimeOut() was called.  It must have wrapped all the way
			around and gone past again. This passed since vTaskSetTimeout()
			was called. */
			xReturn = pdTRUE;
 8007e54:	2301      	movs	r3, #1
 8007e56:	61fb      	str	r3, [r7, #28]
 8007e58:	e015      	b.n	8007e86 <xTaskCheckForTimeOut+0xb2>
		}
		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
 8007e5a:	683b      	ldr	r3, [r7, #0]
 8007e5c:	681b      	ldr	r3, [r3, #0]
 8007e5e:	697a      	ldr	r2, [r7, #20]
 8007e60:	429a      	cmp	r2, r3
 8007e62:	d20b      	bcs.n	8007e7c <xTaskCheckForTimeOut+0xa8>
		{
			/* Not a genuine timeout. Adjust parameters for time remaining. */
			*pxTicksToWait -= xElapsedTime;
 8007e64:	683b      	ldr	r3, [r7, #0]
 8007e66:	681a      	ldr	r2, [r3, #0]
 8007e68:	697b      	ldr	r3, [r7, #20]
 8007e6a:	1ad2      	subs	r2, r2, r3
 8007e6c:	683b      	ldr	r3, [r7, #0]
 8007e6e:	601a      	str	r2, [r3, #0]
			vTaskInternalSetTimeOutState( pxTimeOut );
 8007e70:	6878      	ldr	r0, [r7, #4]
 8007e72:	f7ff ff99 	bl	8007da8 <vTaskInternalSetTimeOutState>
			xReturn = pdFALSE;
 8007e76:	2300      	movs	r3, #0
 8007e78:	61fb      	str	r3, [r7, #28]
 8007e7a:	e004      	b.n	8007e86 <xTaskCheckForTimeOut+0xb2>
		}
		else
		{
			*pxTicksToWait = 0;
 8007e7c:	683b      	ldr	r3, [r7, #0]
 8007e7e:	2200      	movs	r2, #0
 8007e80:	601a      	str	r2, [r3, #0]
			xReturn = pdTRUE;
 8007e82:	2301      	movs	r3, #1
 8007e84:	61fb      	str	r3, [r7, #28]
		}
	}
	taskEXIT_CRITICAL();
 8007e86:	f000 ff91 	bl	8008dac <vPortExitCritical>

	return xReturn;
 8007e8a:	69fb      	ldr	r3, [r7, #28]
}
 8007e8c:	4618      	mov	r0, r3
 8007e8e:	3720      	adds	r7, #32
 8007e90:	46bd      	mov	sp, r7
 8007e92:	bd80      	pop	{r7, pc}
 8007e94:	200014a8 	.word	0x200014a8
 8007e98:	200014bc 	.word	0x200014bc

08007e9c <vTaskMissedYield>:
/*-----------------------------------------------------------*/

void vTaskMissedYield( void )
{
 8007e9c:	b480      	push	{r7}
 8007e9e:	af00      	add	r7, sp, #0
	xYieldPending = pdTRUE;
 8007ea0:	4b03      	ldr	r3, [pc, #12]	@ (8007eb0 <vTaskMissedYield+0x14>)
 8007ea2:	2201      	movs	r2, #1
 8007ea4:	601a      	str	r2, [r3, #0]
}
 8007ea6:	bf00      	nop
 8007ea8:	46bd      	mov	sp, r7
 8007eaa:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007eae:	4770      	bx	lr
 8007eb0:	200014b8 	.word	0x200014b8

08007eb4 <prvIdleTask>:
 *
 * void prvIdleTask( void *pvParameters );
 *
 */
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
 8007eb4:	b580      	push	{r7, lr}
 8007eb6:	b082      	sub	sp, #8
 8007eb8:	af00      	add	r7, sp, #0
 8007eba:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* See if any tasks have deleted themselves - if so then the idle task
		is responsible for freeing the deleted task's TCB and stack. */
		prvCheckTasksWaitingTermination();
 8007ebc:	f000 f852 	bl	8007f64 <prvCheckTasksWaitingTermination>

			A critical region is not required here as we are just reading from
			the list, and an occasional incorrect value will not matter.  If
			the ready list at the idle priority contains more than one task
			then a task other than the idle task is ready to execute. */
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
 8007ec0:	4b06      	ldr	r3, [pc, #24]	@ (8007edc <prvIdleTask+0x28>)
 8007ec2:	681b      	ldr	r3, [r3, #0]
 8007ec4:	2b01      	cmp	r3, #1
 8007ec6:	d9f9      	bls.n	8007ebc <prvIdleTask+0x8>
			{
				taskYIELD();
 8007ec8:	4b05      	ldr	r3, [pc, #20]	@ (8007ee0 <prvIdleTask+0x2c>)
 8007eca:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8007ece:	601a      	str	r2, [r3, #0]
 8007ed0:	f3bf 8f4f 	dsb	sy
 8007ed4:	f3bf 8f6f 	isb	sy
		prvCheckTasksWaitingTermination();
 8007ed8:	e7f0      	b.n	8007ebc <prvIdleTask+0x8>
 8007eda:	bf00      	nop
 8007edc:	20000fd4 	.word	0x20000fd4
 8007ee0:	e000ed04 	.word	0xe000ed04

08007ee4 <prvInitialiseTaskLists>:

#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

static void prvInitialiseTaskLists( void )
{
 8007ee4:	b580      	push	{r7, lr}
 8007ee6:	b082      	sub	sp, #8
 8007ee8:	af00      	add	r7, sp, #0
UBaseType_t uxPriority;

	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8007eea:	2300      	movs	r3, #0
 8007eec:	607b      	str	r3, [r7, #4]
 8007eee:	e00c      	b.n	8007f0a <prvInitialiseTaskLists+0x26>
	{
		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
 8007ef0:	687a      	ldr	r2, [r7, #4]
 8007ef2:	4613      	mov	r3, r2
 8007ef4:	009b      	lsls	r3, r3, #2
 8007ef6:	4413      	add	r3, r2
 8007ef8:	009b      	lsls	r3, r3, #2
 8007efa:	4a12      	ldr	r2, [pc, #72]	@ (8007f44 <prvInitialiseTaskLists+0x60>)
 8007efc:	4413      	add	r3, r2
 8007efe:	4618      	mov	r0, r3
 8007f00:	f7fe faba 	bl	8006478 <vListInitialise>
	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8007f04:	687b      	ldr	r3, [r7, #4]
 8007f06:	3301      	adds	r3, #1
 8007f08:	607b      	str	r3, [r7, #4]
 8007f0a:	687b      	ldr	r3, [r7, #4]
 8007f0c:	2b37      	cmp	r3, #55	@ 0x37
 8007f0e:	d9ef      	bls.n	8007ef0 <prvInitialiseTaskLists+0xc>
	}

	vListInitialise( &xDelayedTaskList1 );
 8007f10:	480d      	ldr	r0, [pc, #52]	@ (8007f48 <prvInitialiseTaskLists+0x64>)
 8007f12:	f7fe fab1 	bl	8006478 <vListInitialise>
	vListInitialise( &xDelayedTaskList2 );
 8007f16:	480d      	ldr	r0, [pc, #52]	@ (8007f4c <prvInitialiseTaskLists+0x68>)
 8007f18:	f7fe faae 	bl	8006478 <vListInitialise>
	vListInitialise( &xPendingReadyList );
 8007f1c:	480c      	ldr	r0, [pc, #48]	@ (8007f50 <prvInitialiseTaskLists+0x6c>)
 8007f1e:	f7fe faab 	bl	8006478 <vListInitialise>

	#if ( INCLUDE_vTaskDelete == 1 )
	{
		vListInitialise( &xTasksWaitingTermination );
 8007f22:	480c      	ldr	r0, [pc, #48]	@ (8007f54 <prvInitialiseTaskLists+0x70>)
 8007f24:	f7fe faa8 	bl	8006478 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskDelete */

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		vListInitialise( &xSuspendedTaskList );
 8007f28:	480b      	ldr	r0, [pc, #44]	@ (8007f58 <prvInitialiseTaskLists+0x74>)
 8007f2a:	f7fe faa5 	bl	8006478 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskSuspend */

	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
	using list2. */
	pxDelayedTaskList = &xDelayedTaskList1;
 8007f2e:	4b0b      	ldr	r3, [pc, #44]	@ (8007f5c <prvInitialiseTaskLists+0x78>)
 8007f30:	4a05      	ldr	r2, [pc, #20]	@ (8007f48 <prvInitialiseTaskLists+0x64>)
 8007f32:	601a      	str	r2, [r3, #0]
	pxOverflowDelayedTaskList = &xDelayedTaskList2;
 8007f34:	4b0a      	ldr	r3, [pc, #40]	@ (8007f60 <prvInitialiseTaskLists+0x7c>)
 8007f36:	4a05      	ldr	r2, [pc, #20]	@ (8007f4c <prvInitialiseTaskLists+0x68>)
 8007f38:	601a      	str	r2, [r3, #0]
}
 8007f3a:	bf00      	nop
 8007f3c:	3708      	adds	r7, #8
 8007f3e:	46bd      	mov	sp, r7
 8007f40:	bd80      	pop	{r7, pc}
 8007f42:	bf00      	nop
 8007f44:	20000fd4 	.word	0x20000fd4
 8007f48:	20001434 	.word	0x20001434
 8007f4c:	20001448 	.word	0x20001448
 8007f50:	20001464 	.word	0x20001464
 8007f54:	20001478 	.word	0x20001478
 8007f58:	20001490 	.word	0x20001490
 8007f5c:	2000145c 	.word	0x2000145c
 8007f60:	20001460 	.word	0x20001460

08007f64 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/

static void prvCheckTasksWaitingTermination( void )
{
 8007f64:	b580      	push	{r7, lr}
 8007f66:	b082      	sub	sp, #8
 8007f68:	af00      	add	r7, sp, #0
	{
		TCB_t *pxTCB;

		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
		being called too often in the idle task. */
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8007f6a:	e019      	b.n	8007fa0 <prvCheckTasksWaitingTermination+0x3c>
		{
			taskENTER_CRITICAL();
 8007f6c:	f000 feec 	bl	8008d48 <vPortEnterCritical>
			{
				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8007f70:	4b10      	ldr	r3, [pc, #64]	@ (8007fb4 <prvCheckTasksWaitingTermination+0x50>)
 8007f72:	68db      	ldr	r3, [r3, #12]
 8007f74:	68db      	ldr	r3, [r3, #12]
 8007f76:	607b      	str	r3, [r7, #4]
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8007f78:	687b      	ldr	r3, [r7, #4]
 8007f7a:	3304      	adds	r3, #4
 8007f7c:	4618      	mov	r0, r3
 8007f7e:	f7fe fb05 	bl	800658c <uxListRemove>
				--uxCurrentNumberOfTasks;
 8007f82:	4b0d      	ldr	r3, [pc, #52]	@ (8007fb8 <prvCheckTasksWaitingTermination+0x54>)
 8007f84:	681b      	ldr	r3, [r3, #0]
 8007f86:	3b01      	subs	r3, #1
 8007f88:	4a0b      	ldr	r2, [pc, #44]	@ (8007fb8 <prvCheckTasksWaitingTermination+0x54>)
 8007f8a:	6013      	str	r3, [r2, #0]
				--uxDeletedTasksWaitingCleanUp;
 8007f8c:	4b0b      	ldr	r3, [pc, #44]	@ (8007fbc <prvCheckTasksWaitingTermination+0x58>)
 8007f8e:	681b      	ldr	r3, [r3, #0]
 8007f90:	3b01      	subs	r3, #1
 8007f92:	4a0a      	ldr	r2, [pc, #40]	@ (8007fbc <prvCheckTasksWaitingTermination+0x58>)
 8007f94:	6013      	str	r3, [r2, #0]
			}
			taskEXIT_CRITICAL();
 8007f96:	f000 ff09 	bl	8008dac <vPortExitCritical>

			prvDeleteTCB( pxTCB );
 8007f9a:	6878      	ldr	r0, [r7, #4]
 8007f9c:	f000 f810 	bl	8007fc0 <prvDeleteTCB>
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8007fa0:	4b06      	ldr	r3, [pc, #24]	@ (8007fbc <prvCheckTasksWaitingTermination+0x58>)
 8007fa2:	681b      	ldr	r3, [r3, #0]
 8007fa4:	2b00      	cmp	r3, #0
 8007fa6:	d1e1      	bne.n	8007f6c <prvCheckTasksWaitingTermination+0x8>
		}
	}
	#endif /* INCLUDE_vTaskDelete */
}
 8007fa8:	bf00      	nop
 8007faa:	bf00      	nop
 8007fac:	3708      	adds	r7, #8
 8007fae:	46bd      	mov	sp, r7
 8007fb0:	bd80      	pop	{r7, pc}
 8007fb2:	bf00      	nop
 8007fb4:	20001478 	.word	0x20001478
 8007fb8:	200014a4 	.word	0x200014a4
 8007fbc:	2000148c 	.word	0x2000148c

08007fc0 <prvDeleteTCB>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelete == 1 )

	static void prvDeleteTCB( TCB_t *pxTCB )
	{
 8007fc0:	b580      	push	{r7, lr}
 8007fc2:	b084      	sub	sp, #16
 8007fc4:	af00      	add	r7, sp, #0
 8007fc6:	6078      	str	r0, [r7, #4]
		to the task to free any memory allocated at the application level.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		#if ( configUSE_NEWLIB_REENTRANT == 1 )
		{
			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
 8007fc8:	687b      	ldr	r3, [r7, #4]
 8007fca:	3354      	adds	r3, #84	@ 0x54
 8007fcc:	4618      	mov	r0, r3
 8007fce:	f001 f9d3 	bl	8009378 <_reclaim_reent>
		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
		{
			/* The task could have been allocated statically or dynamically, so
			check what was statically allocated before trying to free the
			memory. */
			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
 8007fd2:	687b      	ldr	r3, [r7, #4]
 8007fd4:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8007fd8:	2b00      	cmp	r3, #0
 8007fda:	d108      	bne.n	8007fee <prvDeleteTCB+0x2e>
			{
				/* Both the stack and TCB were allocated dynamically, so both
				must be freed. */
				vPortFree( pxTCB->pxStack );
 8007fdc:	687b      	ldr	r3, [r7, #4]
 8007fde:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8007fe0:	4618      	mov	r0, r3
 8007fe2:	f001 f8a1 	bl	8009128 <vPortFree>
				vPortFree( pxTCB );
 8007fe6:	6878      	ldr	r0, [r7, #4]
 8007fe8:	f001 f89e 	bl	8009128 <vPortFree>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
	}
 8007fec:	e019      	b.n	8008022 <prvDeleteTCB+0x62>
			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
 8007fee:	687b      	ldr	r3, [r7, #4]
 8007ff0:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8007ff4:	2b01      	cmp	r3, #1
 8007ff6:	d103      	bne.n	8008000 <prvDeleteTCB+0x40>
				vPortFree( pxTCB );
 8007ff8:	6878      	ldr	r0, [r7, #4]
 8007ffa:	f001 f895 	bl	8009128 <vPortFree>
	}
 8007ffe:	e010      	b.n	8008022 <prvDeleteTCB+0x62>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
 8008000:	687b      	ldr	r3, [r7, #4]
 8008002:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8008006:	2b02      	cmp	r3, #2
 8008008:	d00b      	beq.n	8008022 <prvDeleteTCB+0x62>
	__asm volatile
 800800a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800800e:	f383 8811 	msr	BASEPRI, r3
 8008012:	f3bf 8f6f 	isb	sy
 8008016:	f3bf 8f4f 	dsb	sy
 800801a:	60fb      	str	r3, [r7, #12]
}
 800801c:	bf00      	nop
 800801e:	bf00      	nop
 8008020:	e7fd      	b.n	800801e <prvDeleteTCB+0x5e>
	}
 8008022:	bf00      	nop
 8008024:	3710      	adds	r7, #16
 8008026:	46bd      	mov	sp, r7
 8008028:	bd80      	pop	{r7, pc}
	...

0800802c <prvResetNextTaskUnblockTime>:

#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/

static void prvResetNextTaskUnblockTime( void )
{
 800802c:	b480      	push	{r7}
 800802e:	b083      	sub	sp, #12
 8008030:	af00      	add	r7, sp, #0
TCB_t *pxTCB;

	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8008032:	4b0c      	ldr	r3, [pc, #48]	@ (8008064 <prvResetNextTaskUnblockTime+0x38>)
 8008034:	681b      	ldr	r3, [r3, #0]
 8008036:	681b      	ldr	r3, [r3, #0]
 8008038:	2b00      	cmp	r3, #0
 800803a:	d104      	bne.n	8008046 <prvResetNextTaskUnblockTime+0x1a>
	{
		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
		the maximum possible value so it is	extremely unlikely that the
		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
		there is an item in the delayed list. */
		xNextTaskUnblockTime = portMAX_DELAY;
 800803c:	4b0a      	ldr	r3, [pc, #40]	@ (8008068 <prvResetNextTaskUnblockTime+0x3c>)
 800803e:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8008042:	601a      	str	r2, [r3, #0]
		which the task at the head of the delayed list should be removed
		from the Blocked state. */
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
	}
}
 8008044:	e008      	b.n	8008058 <prvResetNextTaskUnblockTime+0x2c>
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8008046:	4b07      	ldr	r3, [pc, #28]	@ (8008064 <prvResetNextTaskUnblockTime+0x38>)
 8008048:	681b      	ldr	r3, [r3, #0]
 800804a:	68db      	ldr	r3, [r3, #12]
 800804c:	68db      	ldr	r3, [r3, #12]
 800804e:	607b      	str	r3, [r7, #4]
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
 8008050:	687b      	ldr	r3, [r7, #4]
 8008052:	685b      	ldr	r3, [r3, #4]
 8008054:	4a04      	ldr	r2, [pc, #16]	@ (8008068 <prvResetNextTaskUnblockTime+0x3c>)
 8008056:	6013      	str	r3, [r2, #0]
}
 8008058:	bf00      	nop
 800805a:	370c      	adds	r7, #12
 800805c:	46bd      	mov	sp, r7
 800805e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008062:	4770      	bx	lr
 8008064:	2000145c 	.word	0x2000145c
 8008068:	200014c4 	.word	0x200014c4

0800806c <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

	BaseType_t xTaskGetSchedulerState( void )
	{
 800806c:	b480      	push	{r7}
 800806e:	b083      	sub	sp, #12
 8008070:	af00      	add	r7, sp, #0
	BaseType_t xReturn;

		if( xSchedulerRunning == pdFALSE )
 8008072:	4b0b      	ldr	r3, [pc, #44]	@ (80080a0 <xTaskGetSchedulerState+0x34>)
 8008074:	681b      	ldr	r3, [r3, #0]
 8008076:	2b00      	cmp	r3, #0
 8008078:	d102      	bne.n	8008080 <xTaskGetSchedulerState+0x14>
		{
			xReturn = taskSCHEDULER_NOT_STARTED;
 800807a:	2301      	movs	r3, #1
 800807c:	607b      	str	r3, [r7, #4]
 800807e:	e008      	b.n	8008092 <xTaskGetSchedulerState+0x26>
		}
		else
		{
			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8008080:	4b08      	ldr	r3, [pc, #32]	@ (80080a4 <xTaskGetSchedulerState+0x38>)
 8008082:	681b      	ldr	r3, [r3, #0]
 8008084:	2b00      	cmp	r3, #0
 8008086:	d102      	bne.n	800808e <xTaskGetSchedulerState+0x22>
			{
				xReturn = taskSCHEDULER_RUNNING;
 8008088:	2302      	movs	r3, #2
 800808a:	607b      	str	r3, [r7, #4]
 800808c:	e001      	b.n	8008092 <xTaskGetSchedulerState+0x26>
			}
			else
			{
				xReturn = taskSCHEDULER_SUSPENDED;
 800808e:	2300      	movs	r3, #0
 8008090:	607b      	str	r3, [r7, #4]
			}
		}

		return xReturn;
 8008092:	687b      	ldr	r3, [r7, #4]
	}
 8008094:	4618      	mov	r0, r3
 8008096:	370c      	adds	r7, #12
 8008098:	46bd      	mov	sp, r7
 800809a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800809e:	4770      	bx	lr
 80080a0:	200014b0 	.word	0x200014b0
 80080a4:	200014cc 	.word	0x200014cc

080080a8 <xTaskPriorityInherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
	{
 80080a8:	b580      	push	{r7, lr}
 80080aa:	b084      	sub	sp, #16
 80080ac:	af00      	add	r7, sp, #0
 80080ae:	6078      	str	r0, [r7, #4]
	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
 80080b0:	687b      	ldr	r3, [r7, #4]
 80080b2:	60bb      	str	r3, [r7, #8]
	BaseType_t xReturn = pdFALSE;
 80080b4:	2300      	movs	r3, #0
 80080b6:	60fb      	str	r3, [r7, #12]

		/* If the mutex was given back by an interrupt while the queue was
		locked then the mutex holder might now be NULL.  _RB_ Is this still
		needed as interrupts can no longer use mutexes? */
		if( pxMutexHolder != NULL )
 80080b8:	687b      	ldr	r3, [r7, #4]
 80080ba:	2b00      	cmp	r3, #0
 80080bc:	d051      	beq.n	8008162 <xTaskPriorityInherit+0xba>
		{
			/* If the holder of the mutex has a priority below the priority of
			the task attempting to obtain the mutex then it will temporarily
			inherit the priority of the task attempting to obtain the mutex. */
			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
 80080be:	68bb      	ldr	r3, [r7, #8]
 80080c0:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80080c2:	4b2a      	ldr	r3, [pc, #168]	@ (800816c <xTaskPriorityInherit+0xc4>)
 80080c4:	681b      	ldr	r3, [r3, #0]
 80080c6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80080c8:	429a      	cmp	r2, r3
 80080ca:	d241      	bcs.n	8008150 <xTaskPriorityInherit+0xa8>
			{
				/* Adjust the mutex holder state to account for its new
				priority.  Only reset the event list item value if the value is
				not being used for anything else. */
				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
 80080cc:	68bb      	ldr	r3, [r7, #8]
 80080ce:	699b      	ldr	r3, [r3, #24]
 80080d0:	2b00      	cmp	r3, #0
 80080d2:	db06      	blt.n	80080e2 <xTaskPriorityInherit+0x3a>
				{
					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80080d4:	4b25      	ldr	r3, [pc, #148]	@ (800816c <xTaskPriorityInherit+0xc4>)
 80080d6:	681b      	ldr	r3, [r3, #0]
 80080d8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80080da:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 80080de:	68bb      	ldr	r3, [r7, #8]
 80080e0:	619a      	str	r2, [r3, #24]
					mtCOVERAGE_TEST_MARKER();
				}

				/* If the task being modified is in the ready state it will need
				to be moved into a new list. */
				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
 80080e2:	68bb      	ldr	r3, [r7, #8]
 80080e4:	6959      	ldr	r1, [r3, #20]
 80080e6:	68bb      	ldr	r3, [r7, #8]
 80080e8:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80080ea:	4613      	mov	r3, r2
 80080ec:	009b      	lsls	r3, r3, #2
 80080ee:	4413      	add	r3, r2
 80080f0:	009b      	lsls	r3, r3, #2
 80080f2:	4a1f      	ldr	r2, [pc, #124]	@ (8008170 <xTaskPriorityInherit+0xc8>)
 80080f4:	4413      	add	r3, r2
 80080f6:	4299      	cmp	r1, r3
 80080f8:	d122      	bne.n	8008140 <xTaskPriorityInherit+0x98>
				{
					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 80080fa:	68bb      	ldr	r3, [r7, #8]
 80080fc:	3304      	adds	r3, #4
 80080fe:	4618      	mov	r0, r3
 8008100:	f7fe fa44 	bl	800658c <uxListRemove>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* Inherit the priority before being moved into the new list. */
					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
 8008104:	4b19      	ldr	r3, [pc, #100]	@ (800816c <xTaskPriorityInherit+0xc4>)
 8008106:	681b      	ldr	r3, [r3, #0]
 8008108:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800810a:	68bb      	ldr	r3, [r7, #8]
 800810c:	62da      	str	r2, [r3, #44]	@ 0x2c
					prvAddTaskToReadyList( pxMutexHolderTCB );
 800810e:	68bb      	ldr	r3, [r7, #8]
 8008110:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8008112:	4b18      	ldr	r3, [pc, #96]	@ (8008174 <xTaskPriorityInherit+0xcc>)
 8008114:	681b      	ldr	r3, [r3, #0]
 8008116:	429a      	cmp	r2, r3
 8008118:	d903      	bls.n	8008122 <xTaskPriorityInherit+0x7a>
 800811a:	68bb      	ldr	r3, [r7, #8]
 800811c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800811e:	4a15      	ldr	r2, [pc, #84]	@ (8008174 <xTaskPriorityInherit+0xcc>)
 8008120:	6013      	str	r3, [r2, #0]
 8008122:	68bb      	ldr	r3, [r7, #8]
 8008124:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8008126:	4613      	mov	r3, r2
 8008128:	009b      	lsls	r3, r3, #2
 800812a:	4413      	add	r3, r2
 800812c:	009b      	lsls	r3, r3, #2
 800812e:	4a10      	ldr	r2, [pc, #64]	@ (8008170 <xTaskPriorityInherit+0xc8>)
 8008130:	441a      	add	r2, r3
 8008132:	68bb      	ldr	r3, [r7, #8]
 8008134:	3304      	adds	r3, #4
 8008136:	4619      	mov	r1, r3
 8008138:	4610      	mov	r0, r2
 800813a:	f7fe f9ca 	bl	80064d2 <vListInsertEnd>
 800813e:	e004      	b.n	800814a <xTaskPriorityInherit+0xa2>
				}
				else
				{
					/* Just inherit the priority. */
					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
 8008140:	4b0a      	ldr	r3, [pc, #40]	@ (800816c <xTaskPriorityInherit+0xc4>)
 8008142:	681b      	ldr	r3, [r3, #0]
 8008144:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8008146:	68bb      	ldr	r3, [r7, #8]
 8008148:	62da      	str	r2, [r3, #44]	@ 0x2c
				}

				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );

				/* Inheritance occurred. */
				xReturn = pdTRUE;
 800814a:	2301      	movs	r3, #1
 800814c:	60fb      	str	r3, [r7, #12]
 800814e:	e008      	b.n	8008162 <xTaskPriorityInherit+0xba>
			}
			else
			{
				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
 8008150:	68bb      	ldr	r3, [r7, #8]
 8008152:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 8008154:	4b05      	ldr	r3, [pc, #20]	@ (800816c <xTaskPriorityInherit+0xc4>)
 8008156:	681b      	ldr	r3, [r3, #0]
 8008158:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800815a:	429a      	cmp	r2, r3
 800815c:	d201      	bcs.n	8008162 <xTaskPriorityInherit+0xba>
					current priority of the mutex holder is not lower than the
					priority of the task attempting to take the mutex.
					Therefore the mutex holder must have already inherited a
					priority, but inheritance would have occurred if that had
					not been the case. */
					xReturn = pdTRUE;
 800815e:	2301      	movs	r3, #1
 8008160:	60fb      	str	r3, [r7, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 8008162:	68fb      	ldr	r3, [r7, #12]
	}
 8008164:	4618      	mov	r0, r3
 8008166:	3710      	adds	r7, #16
 8008168:	46bd      	mov	sp, r7
 800816a:	bd80      	pop	{r7, pc}
 800816c:	20000fd0 	.word	0x20000fd0
 8008170:	20000fd4 	.word	0x20000fd4
 8008174:	200014ac 	.word	0x200014ac

08008178 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
	{
 8008178:	b580      	push	{r7, lr}
 800817a:	b086      	sub	sp, #24
 800817c:	af00      	add	r7, sp, #0
 800817e:	6078      	str	r0, [r7, #4]
	TCB_t * const pxTCB = pxMutexHolder;
 8008180:	687b      	ldr	r3, [r7, #4]
 8008182:	613b      	str	r3, [r7, #16]
	BaseType_t xReturn = pdFALSE;
 8008184:	2300      	movs	r3, #0
 8008186:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 8008188:	687b      	ldr	r3, [r7, #4]
 800818a:	2b00      	cmp	r3, #0
 800818c:	d058      	beq.n	8008240 <xTaskPriorityDisinherit+0xc8>
		{
			/* A task can only have an inherited priority if it holds the mutex.
			If the mutex is held by a task then it cannot be given from an
			interrupt, and if a mutex is given by the holding task then it must
			be the running state task. */
			configASSERT( pxTCB == pxCurrentTCB );
 800818e:	4b2f      	ldr	r3, [pc, #188]	@ (800824c <xTaskPriorityDisinherit+0xd4>)
 8008190:	681b      	ldr	r3, [r3, #0]
 8008192:	693a      	ldr	r2, [r7, #16]
 8008194:	429a      	cmp	r2, r3
 8008196:	d00b      	beq.n	80081b0 <xTaskPriorityDisinherit+0x38>
	__asm volatile
 8008198:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800819c:	f383 8811 	msr	BASEPRI, r3
 80081a0:	f3bf 8f6f 	isb	sy
 80081a4:	f3bf 8f4f 	dsb	sy
 80081a8:	60fb      	str	r3, [r7, #12]
}
 80081aa:	bf00      	nop
 80081ac:	bf00      	nop
 80081ae:	e7fd      	b.n	80081ac <xTaskPriorityDisinherit+0x34>
			configASSERT( pxTCB->uxMutexesHeld );
 80081b0:	693b      	ldr	r3, [r7, #16]
 80081b2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80081b4:	2b00      	cmp	r3, #0
 80081b6:	d10b      	bne.n	80081d0 <xTaskPriorityDisinherit+0x58>
	__asm volatile
 80081b8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80081bc:	f383 8811 	msr	BASEPRI, r3
 80081c0:	f3bf 8f6f 	isb	sy
 80081c4:	f3bf 8f4f 	dsb	sy
 80081c8:	60bb      	str	r3, [r7, #8]
}
 80081ca:	bf00      	nop
 80081cc:	bf00      	nop
 80081ce:	e7fd      	b.n	80081cc <xTaskPriorityDisinherit+0x54>
			( pxTCB->uxMutexesHeld )--;
 80081d0:	693b      	ldr	r3, [r7, #16]
 80081d2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80081d4:	1e5a      	subs	r2, r3, #1
 80081d6:	693b      	ldr	r3, [r7, #16]
 80081d8:	651a      	str	r2, [r3, #80]	@ 0x50

			/* Has the holder of the mutex inherited the priority of another
			task? */
			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
 80081da:	693b      	ldr	r3, [r7, #16]
 80081dc:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80081de:	693b      	ldr	r3, [r7, #16]
 80081e0:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80081e2:	429a      	cmp	r2, r3
 80081e4:	d02c      	beq.n	8008240 <xTaskPriorityDisinherit+0xc8>
			{
				/* Only disinherit if no other mutexes are held. */
				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
 80081e6:	693b      	ldr	r3, [r7, #16]
 80081e8:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80081ea:	2b00      	cmp	r3, #0
 80081ec:	d128      	bne.n	8008240 <xTaskPriorityDisinherit+0xc8>
					/* A task can only have an inherited priority if it holds
					the mutex.  If the mutex is held by a task then it cannot be
					given from an interrupt, and if a mutex is given by the
					holding task then it must be the running state task.  Remove
					the holding task from the ready/delayed list. */
					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 80081ee:	693b      	ldr	r3, [r7, #16]
 80081f0:	3304      	adds	r3, #4
 80081f2:	4618      	mov	r0, r3
 80081f4:	f7fe f9ca 	bl	800658c <uxListRemove>
					}

					/* Disinherit the priority before adding the task into the
					new	ready list. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					pxTCB->uxPriority = pxTCB->uxBasePriority;
 80081f8:	693b      	ldr	r3, [r7, #16]
 80081fa:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 80081fc:	693b      	ldr	r3, [r7, #16]
 80081fe:	62da      	str	r2, [r3, #44]	@ 0x2c

					/* Reset the event list item value.  It cannot be in use for
					any other purpose if this task is running, and it must be
					running to give back the mutex. */
					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8008200:	693b      	ldr	r3, [r7, #16]
 8008202:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008204:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 8008208:	693b      	ldr	r3, [r7, #16]
 800820a:	619a      	str	r2, [r3, #24]
					prvAddTaskToReadyList( pxTCB );
 800820c:	693b      	ldr	r3, [r7, #16]
 800820e:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8008210:	4b0f      	ldr	r3, [pc, #60]	@ (8008250 <xTaskPriorityDisinherit+0xd8>)
 8008212:	681b      	ldr	r3, [r3, #0]
 8008214:	429a      	cmp	r2, r3
 8008216:	d903      	bls.n	8008220 <xTaskPriorityDisinherit+0xa8>
 8008218:	693b      	ldr	r3, [r7, #16]
 800821a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800821c:	4a0c      	ldr	r2, [pc, #48]	@ (8008250 <xTaskPriorityDisinherit+0xd8>)
 800821e:	6013      	str	r3, [r2, #0]
 8008220:	693b      	ldr	r3, [r7, #16]
 8008222:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8008224:	4613      	mov	r3, r2
 8008226:	009b      	lsls	r3, r3, #2
 8008228:	4413      	add	r3, r2
 800822a:	009b      	lsls	r3, r3, #2
 800822c:	4a09      	ldr	r2, [pc, #36]	@ (8008254 <xTaskPriorityDisinherit+0xdc>)
 800822e:	441a      	add	r2, r3
 8008230:	693b      	ldr	r3, [r7, #16]
 8008232:	3304      	adds	r3, #4
 8008234:	4619      	mov	r1, r3
 8008236:	4610      	mov	r0, r2
 8008238:	f7fe f94b 	bl	80064d2 <vListInsertEnd>
					in an order different to that in which they were taken.
					If a context switch did not occur when the first mutex was
					returned, even if a task was waiting on it, then a context
					switch should occur when the last mutex is returned whether
					a task is waiting on it or not. */
					xReturn = pdTRUE;
 800823c:	2301      	movs	r3, #1
 800823e:	617b      	str	r3, [r7, #20]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 8008240:	697b      	ldr	r3, [r7, #20]
	}
 8008242:	4618      	mov	r0, r3
 8008244:	3718      	adds	r7, #24
 8008246:	46bd      	mov	sp, r7
 8008248:	bd80      	pop	{r7, pc}
 800824a:	bf00      	nop
 800824c:	20000fd0 	.word	0x20000fd0
 8008250:	200014ac 	.word	0x200014ac
 8008254:	20000fd4 	.word	0x20000fd4

08008258 <vTaskPriorityDisinheritAfterTimeout>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
	{
 8008258:	b580      	push	{r7, lr}
 800825a:	b088      	sub	sp, #32
 800825c:	af00      	add	r7, sp, #0
 800825e:	6078      	str	r0, [r7, #4]
 8008260:	6039      	str	r1, [r7, #0]
	TCB_t * const pxTCB = pxMutexHolder;
 8008262:	687b      	ldr	r3, [r7, #4]
 8008264:	61bb      	str	r3, [r7, #24]
	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
 8008266:	2301      	movs	r3, #1
 8008268:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 800826a:	687b      	ldr	r3, [r7, #4]
 800826c:	2b00      	cmp	r3, #0
 800826e:	d06c      	beq.n	800834a <vTaskPriorityDisinheritAfterTimeout+0xf2>
		{
			/* If pxMutexHolder is not NULL then the holder must hold at least
			one mutex. */
			configASSERT( pxTCB->uxMutexesHeld );
 8008270:	69bb      	ldr	r3, [r7, #24]
 8008272:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8008274:	2b00      	cmp	r3, #0
 8008276:	d10b      	bne.n	8008290 <vTaskPriorityDisinheritAfterTimeout+0x38>
	__asm volatile
 8008278:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800827c:	f383 8811 	msr	BASEPRI, r3
 8008280:	f3bf 8f6f 	isb	sy
 8008284:	f3bf 8f4f 	dsb	sy
 8008288:	60fb      	str	r3, [r7, #12]
}
 800828a:	bf00      	nop
 800828c:	bf00      	nop
 800828e:	e7fd      	b.n	800828c <vTaskPriorityDisinheritAfterTimeout+0x34>

			/* Determine the priority to which the priority of the task that
			holds the mutex should be set.  This will be the greater of the
			holding task's base priority and the priority of the highest
			priority task that is waiting to obtain the mutex. */
			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
 8008290:	69bb      	ldr	r3, [r7, #24]
 8008292:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8008294:	683a      	ldr	r2, [r7, #0]
 8008296:	429a      	cmp	r2, r3
 8008298:	d902      	bls.n	80082a0 <vTaskPriorityDisinheritAfterTimeout+0x48>
			{
				uxPriorityToUse = uxHighestPriorityWaitingTask;
 800829a:	683b      	ldr	r3, [r7, #0]
 800829c:	61fb      	str	r3, [r7, #28]
 800829e:	e002      	b.n	80082a6 <vTaskPriorityDisinheritAfterTimeout+0x4e>
			}
			else
			{
				uxPriorityToUse = pxTCB->uxBasePriority;
 80082a0:	69bb      	ldr	r3, [r7, #24]
 80082a2:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80082a4:	61fb      	str	r3, [r7, #28]
			}

			/* Does the priority need to change? */
			if( pxTCB->uxPriority != uxPriorityToUse )
 80082a6:	69bb      	ldr	r3, [r7, #24]
 80082a8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80082aa:	69fa      	ldr	r2, [r7, #28]
 80082ac:	429a      	cmp	r2, r3
 80082ae:	d04c      	beq.n	800834a <vTaskPriorityDisinheritAfterTimeout+0xf2>
			{
				/* Only disinherit if no other mutexes are held.  This is a
				simplification in the priority inheritance implementation.  If
				the task that holds the mutex is also holding other mutexes then
				the other mutexes may have caused the priority inheritance. */
				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
 80082b0:	69bb      	ldr	r3, [r7, #24]
 80082b2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80082b4:	697a      	ldr	r2, [r7, #20]
 80082b6:	429a      	cmp	r2, r3
 80082b8:	d147      	bne.n	800834a <vTaskPriorityDisinheritAfterTimeout+0xf2>
				{
					/* If a task has timed out because it already holds the
					mutex it was trying to obtain then it cannot of inherited
					its own priority. */
					configASSERT( pxTCB != pxCurrentTCB );
 80082ba:	4b26      	ldr	r3, [pc, #152]	@ (8008354 <vTaskPriorityDisinheritAfterTimeout+0xfc>)
 80082bc:	681b      	ldr	r3, [r3, #0]
 80082be:	69ba      	ldr	r2, [r7, #24]
 80082c0:	429a      	cmp	r2, r3
 80082c2:	d10b      	bne.n	80082dc <vTaskPriorityDisinheritAfterTimeout+0x84>
	__asm volatile
 80082c4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80082c8:	f383 8811 	msr	BASEPRI, r3
 80082cc:	f3bf 8f6f 	isb	sy
 80082d0:	f3bf 8f4f 	dsb	sy
 80082d4:	60bb      	str	r3, [r7, #8]
}
 80082d6:	bf00      	nop
 80082d8:	bf00      	nop
 80082da:	e7fd      	b.n	80082d8 <vTaskPriorityDisinheritAfterTimeout+0x80>

					/* Disinherit the priority, remembering the previous
					priority to facilitate determining the subject task's
					state. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					uxPriorityUsedOnEntry = pxTCB->uxPriority;
 80082dc:	69bb      	ldr	r3, [r7, #24]
 80082de:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80082e0:	613b      	str	r3, [r7, #16]
					pxTCB->uxPriority = uxPriorityToUse;
 80082e2:	69bb      	ldr	r3, [r7, #24]
 80082e4:	69fa      	ldr	r2, [r7, #28]
 80082e6:	62da      	str	r2, [r3, #44]	@ 0x2c

					/* Only reset the event list item value if the value is not
					being used for anything else. */
					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
 80082e8:	69bb      	ldr	r3, [r7, #24]
 80082ea:	699b      	ldr	r3, [r3, #24]
 80082ec:	2b00      	cmp	r3, #0
 80082ee:	db04      	blt.n	80082fa <vTaskPriorityDisinheritAfterTimeout+0xa2>
					{
						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80082f0:	69fb      	ldr	r3, [r7, #28]
 80082f2:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 80082f6:	69bb      	ldr	r3, [r7, #24]
 80082f8:	619a      	str	r2, [r3, #24]
					then the task that holds the mutex could be in either the
					Ready, Blocked or Suspended states.  Only remove the task
					from its current state list if it is in the Ready state as
					the task's priority is going to change and there is one
					Ready list per priority. */
					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
 80082fa:	69bb      	ldr	r3, [r7, #24]
 80082fc:	6959      	ldr	r1, [r3, #20]
 80082fe:	693a      	ldr	r2, [r7, #16]
 8008300:	4613      	mov	r3, r2
 8008302:	009b      	lsls	r3, r3, #2
 8008304:	4413      	add	r3, r2
 8008306:	009b      	lsls	r3, r3, #2
 8008308:	4a13      	ldr	r2, [pc, #76]	@ (8008358 <vTaskPriorityDisinheritAfterTimeout+0x100>)
 800830a:	4413      	add	r3, r2
 800830c:	4299      	cmp	r1, r3
 800830e:	d11c      	bne.n	800834a <vTaskPriorityDisinheritAfterTimeout+0xf2>
					{
						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8008310:	69bb      	ldr	r3, [r7, #24]
 8008312:	3304      	adds	r3, #4
 8008314:	4618      	mov	r0, r3
 8008316:	f7fe f939 	bl	800658c <uxListRemove>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}

						prvAddTaskToReadyList( pxTCB );
 800831a:	69bb      	ldr	r3, [r7, #24]
 800831c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800831e:	4b0f      	ldr	r3, [pc, #60]	@ (800835c <vTaskPriorityDisinheritAfterTimeout+0x104>)
 8008320:	681b      	ldr	r3, [r3, #0]
 8008322:	429a      	cmp	r2, r3
 8008324:	d903      	bls.n	800832e <vTaskPriorityDisinheritAfterTimeout+0xd6>
 8008326:	69bb      	ldr	r3, [r7, #24]
 8008328:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800832a:	4a0c      	ldr	r2, [pc, #48]	@ (800835c <vTaskPriorityDisinheritAfterTimeout+0x104>)
 800832c:	6013      	str	r3, [r2, #0]
 800832e:	69bb      	ldr	r3, [r7, #24]
 8008330:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8008332:	4613      	mov	r3, r2
 8008334:	009b      	lsls	r3, r3, #2
 8008336:	4413      	add	r3, r2
 8008338:	009b      	lsls	r3, r3, #2
 800833a:	4a07      	ldr	r2, [pc, #28]	@ (8008358 <vTaskPriorityDisinheritAfterTimeout+0x100>)
 800833c:	441a      	add	r2, r3
 800833e:	69bb      	ldr	r3, [r7, #24]
 8008340:	3304      	adds	r3, #4
 8008342:	4619      	mov	r1, r3
 8008344:	4610      	mov	r0, r2
 8008346:	f7fe f8c4 	bl	80064d2 <vListInsertEnd>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 800834a:	bf00      	nop
 800834c:	3720      	adds	r7, #32
 800834e:	46bd      	mov	sp, r7
 8008350:	bd80      	pop	{r7, pc}
 8008352:	bf00      	nop
 8008354:	20000fd0 	.word	0x20000fd0
 8008358:	20000fd4 	.word	0x20000fd4
 800835c:	200014ac 	.word	0x200014ac

08008360 <pvTaskIncrementMutexHeldCount>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
	{
 8008360:	b480      	push	{r7}
 8008362:	af00      	add	r7, sp, #0
		/* If xSemaphoreCreateMutex() is called before any tasks have been created
		then pxCurrentTCB will be NULL. */
		if( pxCurrentTCB != NULL )
 8008364:	4b07      	ldr	r3, [pc, #28]	@ (8008384 <pvTaskIncrementMutexHeldCount+0x24>)
 8008366:	681b      	ldr	r3, [r3, #0]
 8008368:	2b00      	cmp	r3, #0
 800836a:	d004      	beq.n	8008376 <pvTaskIncrementMutexHeldCount+0x16>
		{
			( pxCurrentTCB->uxMutexesHeld )++;
 800836c:	4b05      	ldr	r3, [pc, #20]	@ (8008384 <pvTaskIncrementMutexHeldCount+0x24>)
 800836e:	681b      	ldr	r3, [r3, #0]
 8008370:	6d1a      	ldr	r2, [r3, #80]	@ 0x50
 8008372:	3201      	adds	r2, #1
 8008374:	651a      	str	r2, [r3, #80]	@ 0x50
		}

		return pxCurrentTCB;
 8008376:	4b03      	ldr	r3, [pc, #12]	@ (8008384 <pvTaskIncrementMutexHeldCount+0x24>)
 8008378:	681b      	ldr	r3, [r3, #0]
	}
 800837a:	4618      	mov	r0, r3
 800837c:	46bd      	mov	sp, r7
 800837e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008382:	4770      	bx	lr
 8008384:	20000fd0 	.word	0x20000fd0

08008388 <prvAddCurrentTaskToDelayedList>:

#endif
/*-----------------------------------------------------------*/

static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
 8008388:	b580      	push	{r7, lr}
 800838a:	b084      	sub	sp, #16
 800838c:	af00      	add	r7, sp, #0
 800838e:	6078      	str	r0, [r7, #4]
 8008390:	6039      	str	r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
 8008392:	4b21      	ldr	r3, [pc, #132]	@ (8008418 <prvAddCurrentTaskToDelayedList+0x90>)
 8008394:	681b      	ldr	r3, [r3, #0]
 8008396:	60fb      	str	r3, [r7, #12]
	}
	#endif

	/* Remove the task from the ready list before adding it to the blocked list
	as the same list item is used for both lists. */
	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8008398:	4b20      	ldr	r3, [pc, #128]	@ (800841c <prvAddCurrentTaskToDelayedList+0x94>)
 800839a:	681b      	ldr	r3, [r3, #0]
 800839c:	3304      	adds	r3, #4
 800839e:	4618      	mov	r0, r3
 80083a0:	f7fe f8f4 	bl	800658c <uxListRemove>
		mtCOVERAGE_TEST_MARKER();
	}

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
 80083a4:	687b      	ldr	r3, [r7, #4]
 80083a6:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80083aa:	d10a      	bne.n	80083c2 <prvAddCurrentTaskToDelayedList+0x3a>
 80083ac:	683b      	ldr	r3, [r7, #0]
 80083ae:	2b00      	cmp	r3, #0
 80083b0:	d007      	beq.n	80083c2 <prvAddCurrentTaskToDelayedList+0x3a>
		{
			/* Add the task to the suspended task list instead of a delayed task
			list to ensure it is not woken by a timing event.  It will block
			indefinitely. */
			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
 80083b2:	4b1a      	ldr	r3, [pc, #104]	@ (800841c <prvAddCurrentTaskToDelayedList+0x94>)
 80083b4:	681b      	ldr	r3, [r3, #0]
 80083b6:	3304      	adds	r3, #4
 80083b8:	4619      	mov	r1, r3
 80083ba:	4819      	ldr	r0, [pc, #100]	@ (8008420 <prvAddCurrentTaskToDelayedList+0x98>)
 80083bc:	f7fe f889 	bl	80064d2 <vListInsertEnd>

		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
		( void ) xCanBlockIndefinitely;
	}
	#endif /* INCLUDE_vTaskSuspend */
}
 80083c0:	e026      	b.n	8008410 <prvAddCurrentTaskToDelayedList+0x88>
			xTimeToWake = xConstTickCount + xTicksToWait;
 80083c2:	68fa      	ldr	r2, [r7, #12]
 80083c4:	687b      	ldr	r3, [r7, #4]
 80083c6:	4413      	add	r3, r2
 80083c8:	60bb      	str	r3, [r7, #8]
			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
 80083ca:	4b14      	ldr	r3, [pc, #80]	@ (800841c <prvAddCurrentTaskToDelayedList+0x94>)
 80083cc:	681b      	ldr	r3, [r3, #0]
 80083ce:	68ba      	ldr	r2, [r7, #8]
 80083d0:	605a      	str	r2, [r3, #4]
			if( xTimeToWake < xConstTickCount )
 80083d2:	68ba      	ldr	r2, [r7, #8]
 80083d4:	68fb      	ldr	r3, [r7, #12]
 80083d6:	429a      	cmp	r2, r3
 80083d8:	d209      	bcs.n	80083ee <prvAddCurrentTaskToDelayedList+0x66>
				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 80083da:	4b12      	ldr	r3, [pc, #72]	@ (8008424 <prvAddCurrentTaskToDelayedList+0x9c>)
 80083dc:	681a      	ldr	r2, [r3, #0]
 80083de:	4b0f      	ldr	r3, [pc, #60]	@ (800841c <prvAddCurrentTaskToDelayedList+0x94>)
 80083e0:	681b      	ldr	r3, [r3, #0]
 80083e2:	3304      	adds	r3, #4
 80083e4:	4619      	mov	r1, r3
 80083e6:	4610      	mov	r0, r2
 80083e8:	f7fe f897 	bl	800651a <vListInsert>
}
 80083ec:	e010      	b.n	8008410 <prvAddCurrentTaskToDelayedList+0x88>
				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 80083ee:	4b0e      	ldr	r3, [pc, #56]	@ (8008428 <prvAddCurrentTaskToDelayedList+0xa0>)
 80083f0:	681a      	ldr	r2, [r3, #0]
 80083f2:	4b0a      	ldr	r3, [pc, #40]	@ (800841c <prvAddCurrentTaskToDelayedList+0x94>)
 80083f4:	681b      	ldr	r3, [r3, #0]
 80083f6:	3304      	adds	r3, #4
 80083f8:	4619      	mov	r1, r3
 80083fa:	4610      	mov	r0, r2
 80083fc:	f7fe f88d 	bl	800651a <vListInsert>
				if( xTimeToWake < xNextTaskUnblockTime )
 8008400:	4b0a      	ldr	r3, [pc, #40]	@ (800842c <prvAddCurrentTaskToDelayedList+0xa4>)
 8008402:	681b      	ldr	r3, [r3, #0]
 8008404:	68ba      	ldr	r2, [r7, #8]
 8008406:	429a      	cmp	r2, r3
 8008408:	d202      	bcs.n	8008410 <prvAddCurrentTaskToDelayedList+0x88>
					xNextTaskUnblockTime = xTimeToWake;
 800840a:	4a08      	ldr	r2, [pc, #32]	@ (800842c <prvAddCurrentTaskToDelayedList+0xa4>)
 800840c:	68bb      	ldr	r3, [r7, #8]
 800840e:	6013      	str	r3, [r2, #0]
}
 8008410:	bf00      	nop
 8008412:	3710      	adds	r7, #16
 8008414:	46bd      	mov	sp, r7
 8008416:	bd80      	pop	{r7, pc}
 8008418:	200014a8 	.word	0x200014a8
 800841c:	20000fd0 	.word	0x20000fd0
 8008420:	20001490 	.word	0x20001490
 8008424:	20001460 	.word	0x20001460
 8008428:	2000145c 	.word	0x2000145c
 800842c:	200014c4 	.word	0x200014c4

08008430 <xTimerCreateTimerTask>:
									TimerCallbackFunction_t pxCallbackFunction,
									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/

BaseType_t xTimerCreateTimerTask( void )
{
 8008430:	b580      	push	{r7, lr}
 8008432:	b08a      	sub	sp, #40	@ 0x28
 8008434:	af04      	add	r7, sp, #16
BaseType_t xReturn = pdFAIL;
 8008436:	2300      	movs	r3, #0
 8008438:	617b      	str	r3, [r7, #20]

	/* This function is called when the scheduler is started if
	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
	timer service task has been created/initialised.  If timers have already
	been created then the initialisation will already have been performed. */
	prvCheckForValidListAndQueue();
 800843a:	f000 fb13 	bl	8008a64 <prvCheckForValidListAndQueue>

	if( xTimerQueue != NULL )
 800843e:	4b1d      	ldr	r3, [pc, #116]	@ (80084b4 <xTimerCreateTimerTask+0x84>)
 8008440:	681b      	ldr	r3, [r3, #0]
 8008442:	2b00      	cmp	r3, #0
 8008444:	d021      	beq.n	800848a <xTimerCreateTimerTask+0x5a>
	{
		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
		{
			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
 8008446:	2300      	movs	r3, #0
 8008448:	60fb      	str	r3, [r7, #12]
			StackType_t *pxTimerTaskStackBuffer = NULL;
 800844a:	2300      	movs	r3, #0
 800844c:	60bb      	str	r3, [r7, #8]
			uint32_t ulTimerTaskStackSize;

			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
 800844e:	1d3a      	adds	r2, r7, #4
 8008450:	f107 0108 	add.w	r1, r7, #8
 8008454:	f107 030c 	add.w	r3, r7, #12
 8008458:	4618      	mov	r0, r3
 800845a:	f7fd fff3 	bl	8006444 <vApplicationGetTimerTaskMemory>
			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
 800845e:	6879      	ldr	r1, [r7, #4]
 8008460:	68bb      	ldr	r3, [r7, #8]
 8008462:	68fa      	ldr	r2, [r7, #12]
 8008464:	9202      	str	r2, [sp, #8]
 8008466:	9301      	str	r3, [sp, #4]
 8008468:	2302      	movs	r3, #2
 800846a:	9300      	str	r3, [sp, #0]
 800846c:	2300      	movs	r3, #0
 800846e:	460a      	mov	r2, r1
 8008470:	4911      	ldr	r1, [pc, #68]	@ (80084b8 <xTimerCreateTimerTask+0x88>)
 8008472:	4812      	ldr	r0, [pc, #72]	@ (80084bc <xTimerCreateTimerTask+0x8c>)
 8008474:	f7fe ffa2 	bl	80073bc <xTaskCreateStatic>
 8008478:	4603      	mov	r3, r0
 800847a:	4a11      	ldr	r2, [pc, #68]	@ (80084c0 <xTimerCreateTimerTask+0x90>)
 800847c:	6013      	str	r3, [r2, #0]
													NULL,
													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
													pxTimerTaskStackBuffer,
													pxTimerTaskTCBBuffer );

			if( xTimerTaskHandle != NULL )
 800847e:	4b10      	ldr	r3, [pc, #64]	@ (80084c0 <xTimerCreateTimerTask+0x90>)
 8008480:	681b      	ldr	r3, [r3, #0]
 8008482:	2b00      	cmp	r3, #0
 8008484:	d001      	beq.n	800848a <xTimerCreateTimerTask+0x5a>
			{
				xReturn = pdPASS;
 8008486:	2301      	movs	r3, #1
 8008488:	617b      	str	r3, [r7, #20]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	configASSERT( xReturn );
 800848a:	697b      	ldr	r3, [r7, #20]
 800848c:	2b00      	cmp	r3, #0
 800848e:	d10b      	bne.n	80084a8 <xTimerCreateTimerTask+0x78>
	__asm volatile
 8008490:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008494:	f383 8811 	msr	BASEPRI, r3
 8008498:	f3bf 8f6f 	isb	sy
 800849c:	f3bf 8f4f 	dsb	sy
 80084a0:	613b      	str	r3, [r7, #16]
}
 80084a2:	bf00      	nop
 80084a4:	bf00      	nop
 80084a6:	e7fd      	b.n	80084a4 <xTimerCreateTimerTask+0x74>
	return xReturn;
 80084a8:	697b      	ldr	r3, [r7, #20]
}
 80084aa:	4618      	mov	r0, r3
 80084ac:	3718      	adds	r7, #24
 80084ae:	46bd      	mov	sp, r7
 80084b0:	bd80      	pop	{r7, pc}
 80084b2:	bf00      	nop
 80084b4:	20001500 	.word	0x20001500
 80084b8:	08009594 	.word	0x08009594
 80084bc:	080085fd 	.word	0x080085fd
 80084c0:	20001504 	.word	0x20001504

080084c4 <xTimerGenericCommand>:
	}
}
/*-----------------------------------------------------------*/

BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
 80084c4:	b580      	push	{r7, lr}
 80084c6:	b08a      	sub	sp, #40	@ 0x28
 80084c8:	af00      	add	r7, sp, #0
 80084ca:	60f8      	str	r0, [r7, #12]
 80084cc:	60b9      	str	r1, [r7, #8]
 80084ce:	607a      	str	r2, [r7, #4]
 80084d0:	603b      	str	r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
 80084d2:	2300      	movs	r3, #0
 80084d4:	627b      	str	r3, [r7, #36]	@ 0x24
DaemonTaskMessage_t xMessage;

	configASSERT( xTimer );
 80084d6:	68fb      	ldr	r3, [r7, #12]
 80084d8:	2b00      	cmp	r3, #0
 80084da:	d10b      	bne.n	80084f4 <xTimerGenericCommand+0x30>
	__asm volatile
 80084dc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80084e0:	f383 8811 	msr	BASEPRI, r3
 80084e4:	f3bf 8f6f 	isb	sy
 80084e8:	f3bf 8f4f 	dsb	sy
 80084ec:	623b      	str	r3, [r7, #32]
}
 80084ee:	bf00      	nop
 80084f0:	bf00      	nop
 80084f2:	e7fd      	b.n	80084f0 <xTimerGenericCommand+0x2c>

	/* Send a message to the timer service task to perform a particular action
	on a particular timer definition. */
	if( xTimerQueue != NULL )
 80084f4:	4b19      	ldr	r3, [pc, #100]	@ (800855c <xTimerGenericCommand+0x98>)
 80084f6:	681b      	ldr	r3, [r3, #0]
 80084f8:	2b00      	cmp	r3, #0
 80084fa:	d02a      	beq.n	8008552 <xTimerGenericCommand+0x8e>
	{
		/* Send a command to the timer service task to start the xTimer timer. */
		xMessage.xMessageID = xCommandID;
 80084fc:	68bb      	ldr	r3, [r7, #8]
 80084fe:	613b      	str	r3, [r7, #16]
		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
 8008500:	687b      	ldr	r3, [r7, #4]
 8008502:	617b      	str	r3, [r7, #20]
		xMessage.u.xTimerParameters.pxTimer = xTimer;
 8008504:	68fb      	ldr	r3, [r7, #12]
 8008506:	61bb      	str	r3, [r7, #24]

		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
 8008508:	68bb      	ldr	r3, [r7, #8]
 800850a:	2b05      	cmp	r3, #5
 800850c:	dc18      	bgt.n	8008540 <xTimerGenericCommand+0x7c>
		{
			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
 800850e:	f7ff fdad 	bl	800806c <xTaskGetSchedulerState>
 8008512:	4603      	mov	r3, r0
 8008514:	2b02      	cmp	r3, #2
 8008516:	d109      	bne.n	800852c <xTimerGenericCommand+0x68>
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
 8008518:	4b10      	ldr	r3, [pc, #64]	@ (800855c <xTimerGenericCommand+0x98>)
 800851a:	6818      	ldr	r0, [r3, #0]
 800851c:	f107 0110 	add.w	r1, r7, #16
 8008520:	2300      	movs	r3, #0
 8008522:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8008524:	f7fe f9a2 	bl	800686c <xQueueGenericSend>
 8008528:	6278      	str	r0, [r7, #36]	@ 0x24
 800852a:	e012      	b.n	8008552 <xTimerGenericCommand+0x8e>
			}
			else
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
 800852c:	4b0b      	ldr	r3, [pc, #44]	@ (800855c <xTimerGenericCommand+0x98>)
 800852e:	6818      	ldr	r0, [r3, #0]
 8008530:	f107 0110 	add.w	r1, r7, #16
 8008534:	2300      	movs	r3, #0
 8008536:	2200      	movs	r2, #0
 8008538:	f7fe f998 	bl	800686c <xQueueGenericSend>
 800853c:	6278      	str	r0, [r7, #36]	@ 0x24
 800853e:	e008      	b.n	8008552 <xTimerGenericCommand+0x8e>
			}
		}
		else
		{
			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
 8008540:	4b06      	ldr	r3, [pc, #24]	@ (800855c <xTimerGenericCommand+0x98>)
 8008542:	6818      	ldr	r0, [r3, #0]
 8008544:	f107 0110 	add.w	r1, r7, #16
 8008548:	2300      	movs	r3, #0
 800854a:	683a      	ldr	r2, [r7, #0]
 800854c:	f7fe fa90 	bl	8006a70 <xQueueGenericSendFromISR>
 8008550:	6278      	str	r0, [r7, #36]	@ 0x24
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xReturn;
 8008552:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
}
 8008554:	4618      	mov	r0, r3
 8008556:	3728      	adds	r7, #40	@ 0x28
 8008558:	46bd      	mov	sp, r7
 800855a:	bd80      	pop	{r7, pc}
 800855c:	20001500 	.word	0x20001500

08008560 <prvProcessExpiredTimer>:
	return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/

static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
 8008560:	b580      	push	{r7, lr}
 8008562:	b088      	sub	sp, #32
 8008564:	af02      	add	r7, sp, #8
 8008566:	6078      	str	r0, [r7, #4]
 8008568:	6039      	str	r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 800856a:	4b23      	ldr	r3, [pc, #140]	@ (80085f8 <prvProcessExpiredTimer+0x98>)
 800856c:	681b      	ldr	r3, [r3, #0]
 800856e:	68db      	ldr	r3, [r3, #12]
 8008570:	68db      	ldr	r3, [r3, #12]
 8008572:	617b      	str	r3, [r7, #20]

	/* Remove the timer from the list of active timers.  A check has already
	been performed to ensure the list is not empty. */
	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8008574:	697b      	ldr	r3, [r7, #20]
 8008576:	3304      	adds	r3, #4
 8008578:	4618      	mov	r0, r3
 800857a:	f7fe f807 	bl	800658c <uxListRemove>
	traceTIMER_EXPIRED( pxTimer );

	/* If the timer is an auto-reload timer then calculate the next
	expiry time and re-insert the timer in the list of active timers. */
	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 800857e:	697b      	ldr	r3, [r7, #20]
 8008580:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8008584:	f003 0304 	and.w	r3, r3, #4
 8008588:	2b00      	cmp	r3, #0
 800858a:	d023      	beq.n	80085d4 <prvProcessExpiredTimer+0x74>
	{
		/* The timer is inserted into a list using a time relative to anything
		other than the current time.  It will therefore be inserted into the
		correct list relative to the time this task thinks it is now. */
		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
 800858c:	697b      	ldr	r3, [r7, #20]
 800858e:	699a      	ldr	r2, [r3, #24]
 8008590:	687b      	ldr	r3, [r7, #4]
 8008592:	18d1      	adds	r1, r2, r3
 8008594:	687b      	ldr	r3, [r7, #4]
 8008596:	683a      	ldr	r2, [r7, #0]
 8008598:	6978      	ldr	r0, [r7, #20]
 800859a:	f000 f8d5 	bl	8008748 <prvInsertTimerInActiveList>
 800859e:	4603      	mov	r3, r0
 80085a0:	2b00      	cmp	r3, #0
 80085a2:	d020      	beq.n	80085e6 <prvProcessExpiredTimer+0x86>
		{
			/* The timer expired before it was added to the active timer
			list.  Reload it now.  */
			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 80085a4:	2300      	movs	r3, #0
 80085a6:	9300      	str	r3, [sp, #0]
 80085a8:	2300      	movs	r3, #0
 80085aa:	687a      	ldr	r2, [r7, #4]
 80085ac:	2100      	movs	r1, #0
 80085ae:	6978      	ldr	r0, [r7, #20]
 80085b0:	f7ff ff88 	bl	80084c4 <xTimerGenericCommand>
 80085b4:	6138      	str	r0, [r7, #16]
			configASSERT( xResult );
 80085b6:	693b      	ldr	r3, [r7, #16]
 80085b8:	2b00      	cmp	r3, #0
 80085ba:	d114      	bne.n	80085e6 <prvProcessExpiredTimer+0x86>
	__asm volatile
 80085bc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80085c0:	f383 8811 	msr	BASEPRI, r3
 80085c4:	f3bf 8f6f 	isb	sy
 80085c8:	f3bf 8f4f 	dsb	sy
 80085cc:	60fb      	str	r3, [r7, #12]
}
 80085ce:	bf00      	nop
 80085d0:	bf00      	nop
 80085d2:	e7fd      	b.n	80085d0 <prvProcessExpiredTimer+0x70>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 80085d4:	697b      	ldr	r3, [r7, #20]
 80085d6:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80085da:	f023 0301 	bic.w	r3, r3, #1
 80085de:	b2da      	uxtb	r2, r3
 80085e0:	697b      	ldr	r3, [r7, #20]
 80085e2:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
		mtCOVERAGE_TEST_MARKER();
	}

	/* Call the timer callback. */
	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 80085e6:	697b      	ldr	r3, [r7, #20]
 80085e8:	6a1b      	ldr	r3, [r3, #32]
 80085ea:	6978      	ldr	r0, [r7, #20]
 80085ec:	4798      	blx	r3
}
 80085ee:	bf00      	nop
 80085f0:	3718      	adds	r7, #24
 80085f2:	46bd      	mov	sp, r7
 80085f4:	bd80      	pop	{r7, pc}
 80085f6:	bf00      	nop
 80085f8:	200014f8 	.word	0x200014f8

080085fc <prvTimerTask>:
/*-----------------------------------------------------------*/

static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
 80085fc:	b580      	push	{r7, lr}
 80085fe:	b084      	sub	sp, #16
 8008600:	af00      	add	r7, sp, #0
 8008602:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* Query the timers list to see if it contains any timers, and if so,
		obtain the time at which the next timer will expire. */
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8008604:	f107 0308 	add.w	r3, r7, #8
 8008608:	4618      	mov	r0, r3
 800860a:	f000 f859 	bl	80086c0 <prvGetNextExpireTime>
 800860e:	60f8      	str	r0, [r7, #12]

		/* If a timer has expired, process it.  Otherwise, block this task
		until either a timer does expire, or a command is received. */
		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
 8008610:	68bb      	ldr	r3, [r7, #8]
 8008612:	4619      	mov	r1, r3
 8008614:	68f8      	ldr	r0, [r7, #12]
 8008616:	f000 f805 	bl	8008624 <prvProcessTimerOrBlockTask>

		/* Empty the command queue. */
		prvProcessReceivedCommands();
 800861a:	f000 f8d7 	bl	80087cc <prvProcessReceivedCommands>
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 800861e:	bf00      	nop
 8008620:	e7f0      	b.n	8008604 <prvTimerTask+0x8>
	...

08008624 <prvProcessTimerOrBlockTask>:
	}
}
/*-----------------------------------------------------------*/

static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
 8008624:	b580      	push	{r7, lr}
 8008626:	b084      	sub	sp, #16
 8008628:	af00      	add	r7, sp, #0
 800862a:	6078      	str	r0, [r7, #4]
 800862c:	6039      	str	r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;

	vTaskSuspendAll();
 800862e:	f7ff f929 	bl	8007884 <vTaskSuspendAll>
		/* Obtain the time now to make an assessment as to whether the timer
		has expired or not.  If obtaining the time causes the lists to switch
		then don't process this timer as any timers that remained in the list
		when the lists were switched will have been processed within the
		prvSampleTimeNow() function. */
		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8008632:	f107 0308 	add.w	r3, r7, #8
 8008636:	4618      	mov	r0, r3
 8008638:	f000 f866 	bl	8008708 <prvSampleTimeNow>
 800863c:	60f8      	str	r0, [r7, #12]
		if( xTimerListsWereSwitched == pdFALSE )
 800863e:	68bb      	ldr	r3, [r7, #8]
 8008640:	2b00      	cmp	r3, #0
 8008642:	d130      	bne.n	80086a6 <prvProcessTimerOrBlockTask+0x82>
		{
			/* The tick count has not overflowed, has the timer expired? */
			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
 8008644:	683b      	ldr	r3, [r7, #0]
 8008646:	2b00      	cmp	r3, #0
 8008648:	d10a      	bne.n	8008660 <prvProcessTimerOrBlockTask+0x3c>
 800864a:	687a      	ldr	r2, [r7, #4]
 800864c:	68fb      	ldr	r3, [r7, #12]
 800864e:	429a      	cmp	r2, r3
 8008650:	d806      	bhi.n	8008660 <prvProcessTimerOrBlockTask+0x3c>
			{
				( void ) xTaskResumeAll();
 8008652:	f7ff f925 	bl	80078a0 <xTaskResumeAll>
				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
 8008656:	68f9      	ldr	r1, [r7, #12]
 8008658:	6878      	ldr	r0, [r7, #4]
 800865a:	f7ff ff81 	bl	8008560 <prvProcessExpiredTimer>
		else
		{
			( void ) xTaskResumeAll();
		}
	}
}
 800865e:	e024      	b.n	80086aa <prvProcessTimerOrBlockTask+0x86>
				if( xListWasEmpty != pdFALSE )
 8008660:	683b      	ldr	r3, [r7, #0]
 8008662:	2b00      	cmp	r3, #0
 8008664:	d008      	beq.n	8008678 <prvProcessTimerOrBlockTask+0x54>
					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
 8008666:	4b13      	ldr	r3, [pc, #76]	@ (80086b4 <prvProcessTimerOrBlockTask+0x90>)
 8008668:	681b      	ldr	r3, [r3, #0]
 800866a:	681b      	ldr	r3, [r3, #0]
 800866c:	2b00      	cmp	r3, #0
 800866e:	d101      	bne.n	8008674 <prvProcessTimerOrBlockTask+0x50>
 8008670:	2301      	movs	r3, #1
 8008672:	e000      	b.n	8008676 <prvProcessTimerOrBlockTask+0x52>
 8008674:	2300      	movs	r3, #0
 8008676:	603b      	str	r3, [r7, #0]
				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
 8008678:	4b0f      	ldr	r3, [pc, #60]	@ (80086b8 <prvProcessTimerOrBlockTask+0x94>)
 800867a:	6818      	ldr	r0, [r3, #0]
 800867c:	687a      	ldr	r2, [r7, #4]
 800867e:	68fb      	ldr	r3, [r7, #12]
 8008680:	1ad3      	subs	r3, r2, r3
 8008682:	683a      	ldr	r2, [r7, #0]
 8008684:	4619      	mov	r1, r3
 8008686:	f7fe fe65 	bl	8007354 <vQueueWaitForMessageRestricted>
				if( xTaskResumeAll() == pdFALSE )
 800868a:	f7ff f909 	bl	80078a0 <xTaskResumeAll>
 800868e:	4603      	mov	r3, r0
 8008690:	2b00      	cmp	r3, #0
 8008692:	d10a      	bne.n	80086aa <prvProcessTimerOrBlockTask+0x86>
					portYIELD_WITHIN_API();
 8008694:	4b09      	ldr	r3, [pc, #36]	@ (80086bc <prvProcessTimerOrBlockTask+0x98>)
 8008696:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 800869a:	601a      	str	r2, [r3, #0]
 800869c:	f3bf 8f4f 	dsb	sy
 80086a0:	f3bf 8f6f 	isb	sy
}
 80086a4:	e001      	b.n	80086aa <prvProcessTimerOrBlockTask+0x86>
			( void ) xTaskResumeAll();
 80086a6:	f7ff f8fb 	bl	80078a0 <xTaskResumeAll>
}
 80086aa:	bf00      	nop
 80086ac:	3710      	adds	r7, #16
 80086ae:	46bd      	mov	sp, r7
 80086b0:	bd80      	pop	{r7, pc}
 80086b2:	bf00      	nop
 80086b4:	200014fc 	.word	0x200014fc
 80086b8:	20001500 	.word	0x20001500
 80086bc:	e000ed04 	.word	0xe000ed04

080086c0 <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/

static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
 80086c0:	b480      	push	{r7}
 80086c2:	b085      	sub	sp, #20
 80086c4:	af00      	add	r7, sp, #0
 80086c6:	6078      	str	r0, [r7, #4]
	the timer with the nearest expiry time will expire.  If there are no
	active timers then just set the next expire time to 0.  That will cause
	this task to unblock when the tick count overflows, at which point the
	timer lists will be switched and the next expiry time can be
	re-assessed.  */
	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
 80086c8:	4b0e      	ldr	r3, [pc, #56]	@ (8008704 <prvGetNextExpireTime+0x44>)
 80086ca:	681b      	ldr	r3, [r3, #0]
 80086cc:	681b      	ldr	r3, [r3, #0]
 80086ce:	2b00      	cmp	r3, #0
 80086d0:	d101      	bne.n	80086d6 <prvGetNextExpireTime+0x16>
 80086d2:	2201      	movs	r2, #1
 80086d4:	e000      	b.n	80086d8 <prvGetNextExpireTime+0x18>
 80086d6:	2200      	movs	r2, #0
 80086d8:	687b      	ldr	r3, [r7, #4]
 80086da:	601a      	str	r2, [r3, #0]
	if( *pxListWasEmpty == pdFALSE )
 80086dc:	687b      	ldr	r3, [r7, #4]
 80086de:	681b      	ldr	r3, [r3, #0]
 80086e0:	2b00      	cmp	r3, #0
 80086e2:	d105      	bne.n	80086f0 <prvGetNextExpireTime+0x30>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 80086e4:	4b07      	ldr	r3, [pc, #28]	@ (8008704 <prvGetNextExpireTime+0x44>)
 80086e6:	681b      	ldr	r3, [r3, #0]
 80086e8:	68db      	ldr	r3, [r3, #12]
 80086ea:	681b      	ldr	r3, [r3, #0]
 80086ec:	60fb      	str	r3, [r7, #12]
 80086ee:	e001      	b.n	80086f4 <prvGetNextExpireTime+0x34>
	}
	else
	{
		/* Ensure the task unblocks when the tick count rolls over. */
		xNextExpireTime = ( TickType_t ) 0U;
 80086f0:	2300      	movs	r3, #0
 80086f2:	60fb      	str	r3, [r7, #12]
	}

	return xNextExpireTime;
 80086f4:	68fb      	ldr	r3, [r7, #12]
}
 80086f6:	4618      	mov	r0, r3
 80086f8:	3714      	adds	r7, #20
 80086fa:	46bd      	mov	sp, r7
 80086fc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008700:	4770      	bx	lr
 8008702:	bf00      	nop
 8008704:	200014f8 	.word	0x200014f8

08008708 <prvSampleTimeNow>:
/*-----------------------------------------------------------*/

static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
 8008708:	b580      	push	{r7, lr}
 800870a:	b084      	sub	sp, #16
 800870c:	af00      	add	r7, sp, #0
 800870e:	6078      	str	r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */

	xTimeNow = xTaskGetTickCount();
 8008710:	f7ff f964 	bl	80079dc <xTaskGetTickCount>
 8008714:	60f8      	str	r0, [r7, #12]

	if( xTimeNow < xLastTime )
 8008716:	4b0b      	ldr	r3, [pc, #44]	@ (8008744 <prvSampleTimeNow+0x3c>)
 8008718:	681b      	ldr	r3, [r3, #0]
 800871a:	68fa      	ldr	r2, [r7, #12]
 800871c:	429a      	cmp	r2, r3
 800871e:	d205      	bcs.n	800872c <prvSampleTimeNow+0x24>
	{
		prvSwitchTimerLists();
 8008720:	f000 f93a 	bl	8008998 <prvSwitchTimerLists>
		*pxTimerListsWereSwitched = pdTRUE;
 8008724:	687b      	ldr	r3, [r7, #4]
 8008726:	2201      	movs	r2, #1
 8008728:	601a      	str	r2, [r3, #0]
 800872a:	e002      	b.n	8008732 <prvSampleTimeNow+0x2a>
	}
	else
	{
		*pxTimerListsWereSwitched = pdFALSE;
 800872c:	687b      	ldr	r3, [r7, #4]
 800872e:	2200      	movs	r2, #0
 8008730:	601a      	str	r2, [r3, #0]
	}

	xLastTime = xTimeNow;
 8008732:	4a04      	ldr	r2, [pc, #16]	@ (8008744 <prvSampleTimeNow+0x3c>)
 8008734:	68fb      	ldr	r3, [r7, #12]
 8008736:	6013      	str	r3, [r2, #0]

	return xTimeNow;
 8008738:	68fb      	ldr	r3, [r7, #12]
}
 800873a:	4618      	mov	r0, r3
 800873c:	3710      	adds	r7, #16
 800873e:	46bd      	mov	sp, r7
 8008740:	bd80      	pop	{r7, pc}
 8008742:	bf00      	nop
 8008744:	20001508 	.word	0x20001508

08008748 <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/

static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
 8008748:	b580      	push	{r7, lr}
 800874a:	b086      	sub	sp, #24
 800874c:	af00      	add	r7, sp, #0
 800874e:	60f8      	str	r0, [r7, #12]
 8008750:	60b9      	str	r1, [r7, #8]
 8008752:	607a      	str	r2, [r7, #4]
 8008754:	603b      	str	r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
 8008756:	2300      	movs	r3, #0
 8008758:	617b      	str	r3, [r7, #20]

	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
 800875a:	68fb      	ldr	r3, [r7, #12]
 800875c:	68ba      	ldr	r2, [r7, #8]
 800875e:	605a      	str	r2, [r3, #4]
	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 8008760:	68fb      	ldr	r3, [r7, #12]
 8008762:	68fa      	ldr	r2, [r7, #12]
 8008764:	611a      	str	r2, [r3, #16]

	if( xNextExpiryTime <= xTimeNow )
 8008766:	68ba      	ldr	r2, [r7, #8]
 8008768:	687b      	ldr	r3, [r7, #4]
 800876a:	429a      	cmp	r2, r3
 800876c:	d812      	bhi.n	8008794 <prvInsertTimerInActiveList+0x4c>
	{
		/* Has the expiry time elapsed between the command to start/reset a
		timer was issued, and the time the command was processed? */
		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 800876e:	687a      	ldr	r2, [r7, #4]
 8008770:	683b      	ldr	r3, [r7, #0]
 8008772:	1ad2      	subs	r2, r2, r3
 8008774:	68fb      	ldr	r3, [r7, #12]
 8008776:	699b      	ldr	r3, [r3, #24]
 8008778:	429a      	cmp	r2, r3
 800877a:	d302      	bcc.n	8008782 <prvInsertTimerInActiveList+0x3a>
		{
			/* The time between a command being issued and the command being
			processed actually exceeds the timers period.  */
			xProcessTimerNow = pdTRUE;
 800877c:	2301      	movs	r3, #1
 800877e:	617b      	str	r3, [r7, #20]
 8008780:	e01b      	b.n	80087ba <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
 8008782:	4b10      	ldr	r3, [pc, #64]	@ (80087c4 <prvInsertTimerInActiveList+0x7c>)
 8008784:	681a      	ldr	r2, [r3, #0]
 8008786:	68fb      	ldr	r3, [r7, #12]
 8008788:	3304      	adds	r3, #4
 800878a:	4619      	mov	r1, r3
 800878c:	4610      	mov	r0, r2
 800878e:	f7fd fec4 	bl	800651a <vListInsert>
 8008792:	e012      	b.n	80087ba <prvInsertTimerInActiveList+0x72>
		}
	}
	else
	{
		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
 8008794:	687a      	ldr	r2, [r7, #4]
 8008796:	683b      	ldr	r3, [r7, #0]
 8008798:	429a      	cmp	r2, r3
 800879a:	d206      	bcs.n	80087aa <prvInsertTimerInActiveList+0x62>
 800879c:	68ba      	ldr	r2, [r7, #8]
 800879e:	683b      	ldr	r3, [r7, #0]
 80087a0:	429a      	cmp	r2, r3
 80087a2:	d302      	bcc.n	80087aa <prvInsertTimerInActiveList+0x62>
		{
			/* If, since the command was issued, the tick count has overflowed
			but the expiry time has not, then the timer must have already passed
			its expiry time and should be processed immediately. */
			xProcessTimerNow = pdTRUE;
 80087a4:	2301      	movs	r3, #1
 80087a6:	617b      	str	r3, [r7, #20]
 80087a8:	e007      	b.n	80087ba <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 80087aa:	4b07      	ldr	r3, [pc, #28]	@ (80087c8 <prvInsertTimerInActiveList+0x80>)
 80087ac:	681a      	ldr	r2, [r3, #0]
 80087ae:	68fb      	ldr	r3, [r7, #12]
 80087b0:	3304      	adds	r3, #4
 80087b2:	4619      	mov	r1, r3
 80087b4:	4610      	mov	r0, r2
 80087b6:	f7fd feb0 	bl	800651a <vListInsert>
		}
	}

	return xProcessTimerNow;
 80087ba:	697b      	ldr	r3, [r7, #20]
}
 80087bc:	4618      	mov	r0, r3
 80087be:	3718      	adds	r7, #24
 80087c0:	46bd      	mov	sp, r7
 80087c2:	bd80      	pop	{r7, pc}
 80087c4:	200014fc 	.word	0x200014fc
 80087c8:	200014f8 	.word	0x200014f8

080087cc <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/

static void	prvProcessReceivedCommands( void )
{
 80087cc:	b580      	push	{r7, lr}
 80087ce:	b08e      	sub	sp, #56	@ 0x38
 80087d0:	af02      	add	r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;

	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 80087d2:	e0ce      	b.n	8008972 <prvProcessReceivedCommands+0x1a6>
	{
		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
		{
			/* Negative commands are pended function calls rather than timer
			commands. */
			if( xMessage.xMessageID < ( BaseType_t ) 0 )
 80087d4:	687b      	ldr	r3, [r7, #4]
 80087d6:	2b00      	cmp	r3, #0
 80087d8:	da19      	bge.n	800880e <prvProcessReceivedCommands+0x42>
			{
				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
 80087da:	1d3b      	adds	r3, r7, #4
 80087dc:	3304      	adds	r3, #4
 80087de:	62fb      	str	r3, [r7, #44]	@ 0x2c

				/* The timer uses the xCallbackParameters member to request a
				callback be executed.  Check the callback is not NULL. */
				configASSERT( pxCallback );
 80087e0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80087e2:	2b00      	cmp	r3, #0
 80087e4:	d10b      	bne.n	80087fe <prvProcessReceivedCommands+0x32>
	__asm volatile
 80087e6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80087ea:	f383 8811 	msr	BASEPRI, r3
 80087ee:	f3bf 8f6f 	isb	sy
 80087f2:	f3bf 8f4f 	dsb	sy
 80087f6:	61fb      	str	r3, [r7, #28]
}
 80087f8:	bf00      	nop
 80087fa:	bf00      	nop
 80087fc:	e7fd      	b.n	80087fa <prvProcessReceivedCommands+0x2e>

				/* Call the function. */
				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
 80087fe:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8008800:	681b      	ldr	r3, [r3, #0]
 8008802:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8008804:	6850      	ldr	r0, [r2, #4]
 8008806:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8008808:	6892      	ldr	r2, [r2, #8]
 800880a:	4611      	mov	r1, r2
 800880c:	4798      	blx	r3
		}
		#endif /* INCLUDE_xTimerPendFunctionCall */

		/* Commands that are positive are timer commands rather than pended
		function calls. */
		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
 800880e:	687b      	ldr	r3, [r7, #4]
 8008810:	2b00      	cmp	r3, #0
 8008812:	f2c0 80ae 	blt.w	8008972 <prvProcessReceivedCommands+0x1a6>
		{
			/* The messages uses the xTimerParameters member to work on a
			software timer. */
			pxTimer = xMessage.u.xTimerParameters.pxTimer;
 8008816:	68fb      	ldr	r3, [r7, #12]
 8008818:	62bb      	str	r3, [r7, #40]	@ 0x28

			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
 800881a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800881c:	695b      	ldr	r3, [r3, #20]
 800881e:	2b00      	cmp	r3, #0
 8008820:	d004      	beq.n	800882c <prvProcessReceivedCommands+0x60>
			{
				/* The timer is in a list, remove it. */
				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8008822:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8008824:	3304      	adds	r3, #4
 8008826:	4618      	mov	r0, r3
 8008828:	f7fd feb0 	bl	800658c <uxListRemove>
			it must be present in the function call.  prvSampleTimeNow() must be
			called after the message is received from xTimerQueue so there is no
			possibility of a higher priority task adding a message to the message
			queue with a time that is ahead of the timer daemon task (because it
			pre-empted the timer daemon task after the xTimeNow value was set). */
			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 800882c:	463b      	mov	r3, r7
 800882e:	4618      	mov	r0, r3
 8008830:	f7ff ff6a 	bl	8008708 <prvSampleTimeNow>
 8008834:	6278      	str	r0, [r7, #36]	@ 0x24

			switch( xMessage.xMessageID )
 8008836:	687b      	ldr	r3, [r7, #4]
 8008838:	2b09      	cmp	r3, #9
 800883a:	f200 8097 	bhi.w	800896c <prvProcessReceivedCommands+0x1a0>
 800883e:	a201      	add	r2, pc, #4	@ (adr r2, 8008844 <prvProcessReceivedCommands+0x78>)
 8008840:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8008844:	0800886d 	.word	0x0800886d
 8008848:	0800886d 	.word	0x0800886d
 800884c:	0800886d 	.word	0x0800886d
 8008850:	080088e3 	.word	0x080088e3
 8008854:	080088f7 	.word	0x080088f7
 8008858:	08008943 	.word	0x08008943
 800885c:	0800886d 	.word	0x0800886d
 8008860:	0800886d 	.word	0x0800886d
 8008864:	080088e3 	.word	0x080088e3
 8008868:	080088f7 	.word	0x080088f7
				case tmrCOMMAND_START_FROM_ISR :
				case tmrCOMMAND_RESET :
				case tmrCOMMAND_RESET_FROM_ISR :
				case tmrCOMMAND_START_DONT_TRACE :
					/* Start or restart a timer. */
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 800886c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800886e:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8008872:	f043 0301 	orr.w	r3, r3, #1
 8008876:	b2da      	uxtb	r2, r3
 8008878:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800887a:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
 800887e:	68ba      	ldr	r2, [r7, #8]
 8008880:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8008882:	699b      	ldr	r3, [r3, #24]
 8008884:	18d1      	adds	r1, r2, r3
 8008886:	68bb      	ldr	r3, [r7, #8]
 8008888:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 800888a:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 800888c:	f7ff ff5c 	bl	8008748 <prvInsertTimerInActiveList>
 8008890:	4603      	mov	r3, r0
 8008892:	2b00      	cmp	r3, #0
 8008894:	d06c      	beq.n	8008970 <prvProcessReceivedCommands+0x1a4>
					{
						/* The timer expired before it was added to the active
						timer list.  Process it now. */
						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8008896:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8008898:	6a1b      	ldr	r3, [r3, #32]
 800889a:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 800889c:	4798      	blx	r3
						traceTIMER_EXPIRED( pxTimer );

						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 800889e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80088a0:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80088a4:	f003 0304 	and.w	r3, r3, #4
 80088a8:	2b00      	cmp	r3, #0
 80088aa:	d061      	beq.n	8008970 <prvProcessReceivedCommands+0x1a4>
						{
							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
 80088ac:	68ba      	ldr	r2, [r7, #8]
 80088ae:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80088b0:	699b      	ldr	r3, [r3, #24]
 80088b2:	441a      	add	r2, r3
 80088b4:	2300      	movs	r3, #0
 80088b6:	9300      	str	r3, [sp, #0]
 80088b8:	2300      	movs	r3, #0
 80088ba:	2100      	movs	r1, #0
 80088bc:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 80088be:	f7ff fe01 	bl	80084c4 <xTimerGenericCommand>
 80088c2:	6238      	str	r0, [r7, #32]
							configASSERT( xResult );
 80088c4:	6a3b      	ldr	r3, [r7, #32]
 80088c6:	2b00      	cmp	r3, #0
 80088c8:	d152      	bne.n	8008970 <prvProcessReceivedCommands+0x1a4>
	__asm volatile
 80088ca:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80088ce:	f383 8811 	msr	BASEPRI, r3
 80088d2:	f3bf 8f6f 	isb	sy
 80088d6:	f3bf 8f4f 	dsb	sy
 80088da:	61bb      	str	r3, [r7, #24]
}
 80088dc:	bf00      	nop
 80088de:	bf00      	nop
 80088e0:	e7fd      	b.n	80088de <prvProcessReceivedCommands+0x112>
					break;

				case tmrCOMMAND_STOP :
				case tmrCOMMAND_STOP_FROM_ISR :
					/* The timer has already been removed from the active list. */
					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 80088e2:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80088e4:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80088e8:	f023 0301 	bic.w	r3, r3, #1
 80088ec:	b2da      	uxtb	r2, r3
 80088ee:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80088f0:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					break;
 80088f4:	e03d      	b.n	8008972 <prvProcessReceivedCommands+0x1a6>

				case tmrCOMMAND_CHANGE_PERIOD :
				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 80088f6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80088f8:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80088fc:	f043 0301 	orr.w	r3, r3, #1
 8008900:	b2da      	uxtb	r2, r3
 8008902:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8008904:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
 8008908:	68ba      	ldr	r2, [r7, #8]
 800890a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800890c:	619a      	str	r2, [r3, #24]
					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
 800890e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8008910:	699b      	ldr	r3, [r3, #24]
 8008912:	2b00      	cmp	r3, #0
 8008914:	d10b      	bne.n	800892e <prvProcessReceivedCommands+0x162>
	__asm volatile
 8008916:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800891a:	f383 8811 	msr	BASEPRI, r3
 800891e:	f3bf 8f6f 	isb	sy
 8008922:	f3bf 8f4f 	dsb	sy
 8008926:	617b      	str	r3, [r7, #20]
}
 8008928:	bf00      	nop
 800892a:	bf00      	nop
 800892c:	e7fd      	b.n	800892a <prvProcessReceivedCommands+0x15e>
					be longer or shorter than the old one.  The command time is
					therefore set to the current time, and as the period cannot
					be zero the next expiry time can only be in the future,
					meaning (unlike for the xTimerStart() case above) there is
					no fail case that needs to be handled here. */
					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
 800892e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8008930:	699a      	ldr	r2, [r3, #24]
 8008932:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008934:	18d1      	adds	r1, r2, r3
 8008936:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008938:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 800893a:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 800893c:	f7ff ff04 	bl	8008748 <prvInsertTimerInActiveList>
					break;
 8008940:	e017      	b.n	8008972 <prvProcessReceivedCommands+0x1a6>
					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
					{
						/* The timer has already been removed from the active list,
						just free up the memory if the memory was dynamically
						allocated. */
						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
 8008942:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8008944:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8008948:	f003 0302 	and.w	r3, r3, #2
 800894c:	2b00      	cmp	r3, #0
 800894e:	d103      	bne.n	8008958 <prvProcessReceivedCommands+0x18c>
						{
							vPortFree( pxTimer );
 8008950:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8008952:	f000 fbe9 	bl	8009128 <vPortFree>
						no need to free the memory - just mark the timer as
						"not active". */
						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
					}
					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
					break;
 8008956:	e00c      	b.n	8008972 <prvProcessReceivedCommands+0x1a6>
							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8008958:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800895a:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 800895e:	f023 0301 	bic.w	r3, r3, #1
 8008962:	b2da      	uxtb	r2, r3
 8008964:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8008966:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					break;
 800896a:	e002      	b.n	8008972 <prvProcessReceivedCommands+0x1a6>

				default	:
					/* Don't expect to get here. */
					break;
 800896c:	bf00      	nop
 800896e:	e000      	b.n	8008972 <prvProcessReceivedCommands+0x1a6>
					break;
 8008970:	bf00      	nop
	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 8008972:	4b08      	ldr	r3, [pc, #32]	@ (8008994 <prvProcessReceivedCommands+0x1c8>)
 8008974:	681b      	ldr	r3, [r3, #0]
 8008976:	1d39      	adds	r1, r7, #4
 8008978:	2200      	movs	r2, #0
 800897a:	4618      	mov	r0, r3
 800897c:	f7fe f9a6 	bl	8006ccc <xQueueReceive>
 8008980:	4603      	mov	r3, r0
 8008982:	2b00      	cmp	r3, #0
 8008984:	f47f af26 	bne.w	80087d4 <prvProcessReceivedCommands+0x8>
			}
		}
	}
}
 8008988:	bf00      	nop
 800898a:	bf00      	nop
 800898c:	3730      	adds	r7, #48	@ 0x30
 800898e:	46bd      	mov	sp, r7
 8008990:	bd80      	pop	{r7, pc}
 8008992:	bf00      	nop
 8008994:	20001500 	.word	0x20001500

08008998 <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/

static void prvSwitchTimerLists( void )
{
 8008998:	b580      	push	{r7, lr}
 800899a:	b088      	sub	sp, #32
 800899c:	af02      	add	r7, sp, #8

	/* The tick count has overflowed.  The timer lists must be switched.
	If there are any timers still referenced from the current timer list
	then they must have expired and should be processed before the lists
	are switched. */
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 800899e:	e049      	b.n	8008a34 <prvSwitchTimerLists+0x9c>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 80089a0:	4b2e      	ldr	r3, [pc, #184]	@ (8008a5c <prvSwitchTimerLists+0xc4>)
 80089a2:	681b      	ldr	r3, [r3, #0]
 80089a4:	68db      	ldr	r3, [r3, #12]
 80089a6:	681b      	ldr	r3, [r3, #0]
 80089a8:	613b      	str	r3, [r7, #16]

		/* Remove the timer from the list. */
		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80089aa:	4b2c      	ldr	r3, [pc, #176]	@ (8008a5c <prvSwitchTimerLists+0xc4>)
 80089ac:	681b      	ldr	r3, [r3, #0]
 80089ae:	68db      	ldr	r3, [r3, #12]
 80089b0:	68db      	ldr	r3, [r3, #12]
 80089b2:	60fb      	str	r3, [r7, #12]
		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 80089b4:	68fb      	ldr	r3, [r7, #12]
 80089b6:	3304      	adds	r3, #4
 80089b8:	4618      	mov	r0, r3
 80089ba:	f7fd fde7 	bl	800658c <uxListRemove>
		traceTIMER_EXPIRED( pxTimer );

		/* Execute its callback, then send a command to restart the timer if
		it is an auto-reload timer.  It cannot be restarted here as the lists
		have not yet been switched. */
		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 80089be:	68fb      	ldr	r3, [r7, #12]
 80089c0:	6a1b      	ldr	r3, [r3, #32]
 80089c2:	68f8      	ldr	r0, [r7, #12]
 80089c4:	4798      	blx	r3

		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 80089c6:	68fb      	ldr	r3, [r7, #12]
 80089c8:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80089cc:	f003 0304 	and.w	r3, r3, #4
 80089d0:	2b00      	cmp	r3, #0
 80089d2:	d02f      	beq.n	8008a34 <prvSwitchTimerLists+0x9c>
			the timer going into the same timer list then it has already expired
			and the timer should be re-inserted into the current list so it is
			processed again within this loop.  Otherwise a command should be sent
			to restart the timer to ensure it is only inserted into a list after
			the lists have been swapped. */
			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
 80089d4:	68fb      	ldr	r3, [r7, #12]
 80089d6:	699b      	ldr	r3, [r3, #24]
 80089d8:	693a      	ldr	r2, [r7, #16]
 80089da:	4413      	add	r3, r2
 80089dc:	60bb      	str	r3, [r7, #8]
			if( xReloadTime > xNextExpireTime )
 80089de:	68ba      	ldr	r2, [r7, #8]
 80089e0:	693b      	ldr	r3, [r7, #16]
 80089e2:	429a      	cmp	r2, r3
 80089e4:	d90e      	bls.n	8008a04 <prvSwitchTimerLists+0x6c>
			{
				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
 80089e6:	68fb      	ldr	r3, [r7, #12]
 80089e8:	68ba      	ldr	r2, [r7, #8]
 80089ea:	605a      	str	r2, [r3, #4]
				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 80089ec:	68fb      	ldr	r3, [r7, #12]
 80089ee:	68fa      	ldr	r2, [r7, #12]
 80089f0:	611a      	str	r2, [r3, #16]
				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 80089f2:	4b1a      	ldr	r3, [pc, #104]	@ (8008a5c <prvSwitchTimerLists+0xc4>)
 80089f4:	681a      	ldr	r2, [r3, #0]
 80089f6:	68fb      	ldr	r3, [r7, #12]
 80089f8:	3304      	adds	r3, #4
 80089fa:	4619      	mov	r1, r3
 80089fc:	4610      	mov	r0, r2
 80089fe:	f7fd fd8c 	bl	800651a <vListInsert>
 8008a02:	e017      	b.n	8008a34 <prvSwitchTimerLists+0x9c>
			}
			else
			{
				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 8008a04:	2300      	movs	r3, #0
 8008a06:	9300      	str	r3, [sp, #0]
 8008a08:	2300      	movs	r3, #0
 8008a0a:	693a      	ldr	r2, [r7, #16]
 8008a0c:	2100      	movs	r1, #0
 8008a0e:	68f8      	ldr	r0, [r7, #12]
 8008a10:	f7ff fd58 	bl	80084c4 <xTimerGenericCommand>
 8008a14:	6078      	str	r0, [r7, #4]
				configASSERT( xResult );
 8008a16:	687b      	ldr	r3, [r7, #4]
 8008a18:	2b00      	cmp	r3, #0
 8008a1a:	d10b      	bne.n	8008a34 <prvSwitchTimerLists+0x9c>
	__asm volatile
 8008a1c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008a20:	f383 8811 	msr	BASEPRI, r3
 8008a24:	f3bf 8f6f 	isb	sy
 8008a28:	f3bf 8f4f 	dsb	sy
 8008a2c:	603b      	str	r3, [r7, #0]
}
 8008a2e:	bf00      	nop
 8008a30:	bf00      	nop
 8008a32:	e7fd      	b.n	8008a30 <prvSwitchTimerLists+0x98>
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 8008a34:	4b09      	ldr	r3, [pc, #36]	@ (8008a5c <prvSwitchTimerLists+0xc4>)
 8008a36:	681b      	ldr	r3, [r3, #0]
 8008a38:	681b      	ldr	r3, [r3, #0]
 8008a3a:	2b00      	cmp	r3, #0
 8008a3c:	d1b0      	bne.n	80089a0 <prvSwitchTimerLists+0x8>
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxTemp = pxCurrentTimerList;
 8008a3e:	4b07      	ldr	r3, [pc, #28]	@ (8008a5c <prvSwitchTimerLists+0xc4>)
 8008a40:	681b      	ldr	r3, [r3, #0]
 8008a42:	617b      	str	r3, [r7, #20]
	pxCurrentTimerList = pxOverflowTimerList;
 8008a44:	4b06      	ldr	r3, [pc, #24]	@ (8008a60 <prvSwitchTimerLists+0xc8>)
 8008a46:	681b      	ldr	r3, [r3, #0]
 8008a48:	4a04      	ldr	r2, [pc, #16]	@ (8008a5c <prvSwitchTimerLists+0xc4>)
 8008a4a:	6013      	str	r3, [r2, #0]
	pxOverflowTimerList = pxTemp;
 8008a4c:	4a04      	ldr	r2, [pc, #16]	@ (8008a60 <prvSwitchTimerLists+0xc8>)
 8008a4e:	697b      	ldr	r3, [r7, #20]
 8008a50:	6013      	str	r3, [r2, #0]
}
 8008a52:	bf00      	nop
 8008a54:	3718      	adds	r7, #24
 8008a56:	46bd      	mov	sp, r7
 8008a58:	bd80      	pop	{r7, pc}
 8008a5a:	bf00      	nop
 8008a5c:	200014f8 	.word	0x200014f8
 8008a60:	200014fc 	.word	0x200014fc

08008a64 <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/

static void prvCheckForValidListAndQueue( void )
{
 8008a64:	b580      	push	{r7, lr}
 8008a66:	b082      	sub	sp, #8
 8008a68:	af02      	add	r7, sp, #8
	/* Check that the list from which active timers are referenced, and the
	queue used to communicate with the timer service, have been
	initialised. */
	taskENTER_CRITICAL();
 8008a6a:	f000 f96d 	bl	8008d48 <vPortEnterCritical>
	{
		if( xTimerQueue == NULL )
 8008a6e:	4b15      	ldr	r3, [pc, #84]	@ (8008ac4 <prvCheckForValidListAndQueue+0x60>)
 8008a70:	681b      	ldr	r3, [r3, #0]
 8008a72:	2b00      	cmp	r3, #0
 8008a74:	d120      	bne.n	8008ab8 <prvCheckForValidListAndQueue+0x54>
		{
			vListInitialise( &xActiveTimerList1 );
 8008a76:	4814      	ldr	r0, [pc, #80]	@ (8008ac8 <prvCheckForValidListAndQueue+0x64>)
 8008a78:	f7fd fcfe 	bl	8006478 <vListInitialise>
			vListInitialise( &xActiveTimerList2 );
 8008a7c:	4813      	ldr	r0, [pc, #76]	@ (8008acc <prvCheckForValidListAndQueue+0x68>)
 8008a7e:	f7fd fcfb 	bl	8006478 <vListInitialise>
			pxCurrentTimerList = &xActiveTimerList1;
 8008a82:	4b13      	ldr	r3, [pc, #76]	@ (8008ad0 <prvCheckForValidListAndQueue+0x6c>)
 8008a84:	4a10      	ldr	r2, [pc, #64]	@ (8008ac8 <prvCheckForValidListAndQueue+0x64>)
 8008a86:	601a      	str	r2, [r3, #0]
			pxOverflowTimerList = &xActiveTimerList2;
 8008a88:	4b12      	ldr	r3, [pc, #72]	@ (8008ad4 <prvCheckForValidListAndQueue+0x70>)
 8008a8a:	4a10      	ldr	r2, [pc, #64]	@ (8008acc <prvCheckForValidListAndQueue+0x68>)
 8008a8c:	601a      	str	r2, [r3, #0]
				/* The timer queue is allocated statically in case
				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */

				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
 8008a8e:	2300      	movs	r3, #0
 8008a90:	9300      	str	r3, [sp, #0]
 8008a92:	4b11      	ldr	r3, [pc, #68]	@ (8008ad8 <prvCheckForValidListAndQueue+0x74>)
 8008a94:	4a11      	ldr	r2, [pc, #68]	@ (8008adc <prvCheckForValidListAndQueue+0x78>)
 8008a96:	2110      	movs	r1, #16
 8008a98:	200a      	movs	r0, #10
 8008a9a:	f7fd fe0b 	bl	80066b4 <xQueueGenericCreateStatic>
 8008a9e:	4603      	mov	r3, r0
 8008aa0:	4a08      	ldr	r2, [pc, #32]	@ (8008ac4 <prvCheckForValidListAndQueue+0x60>)
 8008aa2:	6013      	str	r3, [r2, #0]
			}
			#endif

			#if ( configQUEUE_REGISTRY_SIZE > 0 )
			{
				if( xTimerQueue != NULL )
 8008aa4:	4b07      	ldr	r3, [pc, #28]	@ (8008ac4 <prvCheckForValidListAndQueue+0x60>)
 8008aa6:	681b      	ldr	r3, [r3, #0]
 8008aa8:	2b00      	cmp	r3, #0
 8008aaa:	d005      	beq.n	8008ab8 <prvCheckForValidListAndQueue+0x54>
				{
					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
 8008aac:	4b05      	ldr	r3, [pc, #20]	@ (8008ac4 <prvCheckForValidListAndQueue+0x60>)
 8008aae:	681b      	ldr	r3, [r3, #0]
 8008ab0:	490b      	ldr	r1, [pc, #44]	@ (8008ae0 <prvCheckForValidListAndQueue+0x7c>)
 8008ab2:	4618      	mov	r0, r3
 8008ab4:	f7fe fc24 	bl	8007300 <vQueueAddToRegistry>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 8008ab8:	f000 f978 	bl	8008dac <vPortExitCritical>
}
 8008abc:	bf00      	nop
 8008abe:	46bd      	mov	sp, r7
 8008ac0:	bd80      	pop	{r7, pc}
 8008ac2:	bf00      	nop
 8008ac4:	20001500 	.word	0x20001500
 8008ac8:	200014d0 	.word	0x200014d0
 8008acc:	200014e4 	.word	0x200014e4
 8008ad0:	200014f8 	.word	0x200014f8
 8008ad4:	200014fc 	.word	0x200014fc
 8008ad8:	200015ac 	.word	0x200015ac
 8008adc:	2000150c 	.word	0x2000150c
 8008ae0:	0800959c 	.word	0x0800959c

08008ae4 <pxPortInitialiseStack>:

/*
 * See header file for description.
 */
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
 8008ae4:	b480      	push	{r7}
 8008ae6:	b085      	sub	sp, #20
 8008ae8:	af00      	add	r7, sp, #0
 8008aea:	60f8      	str	r0, [r7, #12]
 8008aec:	60b9      	str	r1, [r7, #8]
 8008aee:	607a      	str	r2, [r7, #4]
	/* Simulate the stack frame as it would be created by a context switch
	interrupt. */

	/* Offset added to account for the way the MCU uses the stack on entry/exit
	of interrupts, and to ensure alignment. */
	pxTopOfStack--;
 8008af0:	68fb      	ldr	r3, [r7, #12]
 8008af2:	3b04      	subs	r3, #4
 8008af4:	60fb      	str	r3, [r7, #12]

	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
 8008af6:	68fb      	ldr	r3, [r7, #12]
 8008af8:	f04f 7280 	mov.w	r2, #16777216	@ 0x1000000
 8008afc:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 8008afe:	68fb      	ldr	r3, [r7, #12]
 8008b00:	3b04      	subs	r3, #4
 8008b02:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
 8008b04:	68bb      	ldr	r3, [r7, #8]
 8008b06:	f023 0201 	bic.w	r2, r3, #1
 8008b0a:	68fb      	ldr	r3, [r7, #12]
 8008b0c:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 8008b0e:	68fb      	ldr	r3, [r7, #12]
 8008b10:	3b04      	subs	r3, #4
 8008b12:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
 8008b14:	4a0c      	ldr	r2, [pc, #48]	@ (8008b48 <pxPortInitialiseStack+0x64>)
 8008b16:	68fb      	ldr	r3, [r7, #12]
 8008b18:	601a      	str	r2, [r3, #0]

	/* Save code space by skipping register initialisation. */
	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
 8008b1a:	68fb      	ldr	r3, [r7, #12]
 8008b1c:	3b14      	subs	r3, #20
 8008b1e:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
 8008b20:	687a      	ldr	r2, [r7, #4]
 8008b22:	68fb      	ldr	r3, [r7, #12]
 8008b24:	601a      	str	r2, [r3, #0]

	/* A save method is being used that requires each task to maintain its
	own exec return value. */
	pxTopOfStack--;
 8008b26:	68fb      	ldr	r3, [r7, #12]
 8008b28:	3b04      	subs	r3, #4
 8008b2a:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = portINITIAL_EXC_RETURN;
 8008b2c:	68fb      	ldr	r3, [r7, #12]
 8008b2e:	f06f 0202 	mvn.w	r2, #2
 8008b32:	601a      	str	r2, [r3, #0]

	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
 8008b34:	68fb      	ldr	r3, [r7, #12]
 8008b36:	3b20      	subs	r3, #32
 8008b38:	60fb      	str	r3, [r7, #12]

	return pxTopOfStack;
 8008b3a:	68fb      	ldr	r3, [r7, #12]
}
 8008b3c:	4618      	mov	r0, r3
 8008b3e:	3714      	adds	r7, #20
 8008b40:	46bd      	mov	sp, r7
 8008b42:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008b46:	4770      	bx	lr
 8008b48:	08008b4d 	.word	0x08008b4d

08008b4c <prvTaskExitError>:
/*-----------------------------------------------------------*/

static void prvTaskExitError( void )
{
 8008b4c:	b480      	push	{r7}
 8008b4e:	b085      	sub	sp, #20
 8008b50:	af00      	add	r7, sp, #0
volatile uint32_t ulDummy = 0;
 8008b52:	2300      	movs	r3, #0
 8008b54:	607b      	str	r3, [r7, #4]
	its caller as there is nothing to return to.  If a task wants to exit it
	should instead call vTaskDelete( NULL ).

	Artificially force an assert() to be triggered if configASSERT() is
	defined, then stop here so application writers can catch the error. */
	configASSERT( uxCriticalNesting == ~0UL );
 8008b56:	4b13      	ldr	r3, [pc, #76]	@ (8008ba4 <prvTaskExitError+0x58>)
 8008b58:	681b      	ldr	r3, [r3, #0]
 8008b5a:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8008b5e:	d00b      	beq.n	8008b78 <prvTaskExitError+0x2c>
	__asm volatile
 8008b60:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008b64:	f383 8811 	msr	BASEPRI, r3
 8008b68:	f3bf 8f6f 	isb	sy
 8008b6c:	f3bf 8f4f 	dsb	sy
 8008b70:	60fb      	str	r3, [r7, #12]
}
 8008b72:	bf00      	nop
 8008b74:	bf00      	nop
 8008b76:	e7fd      	b.n	8008b74 <prvTaskExitError+0x28>
	__asm volatile
 8008b78:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008b7c:	f383 8811 	msr	BASEPRI, r3
 8008b80:	f3bf 8f6f 	isb	sy
 8008b84:	f3bf 8f4f 	dsb	sy
 8008b88:	60bb      	str	r3, [r7, #8]
}
 8008b8a:	bf00      	nop
	portDISABLE_INTERRUPTS();
	while( ulDummy == 0 )
 8008b8c:	bf00      	nop
 8008b8e:	687b      	ldr	r3, [r7, #4]
 8008b90:	2b00      	cmp	r3, #0
 8008b92:	d0fc      	beq.n	8008b8e <prvTaskExitError+0x42>
		about code appearing after this function is called - making ulDummy
		volatile makes the compiler think the function could return and
		therefore not output an 'unreachable code' warning for code that appears
		after it. */
	}
}
 8008b94:	bf00      	nop
 8008b96:	bf00      	nop
 8008b98:	3714      	adds	r7, #20
 8008b9a:	46bd      	mov	sp, r7
 8008b9c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008ba0:	4770      	bx	lr
 8008ba2:	bf00      	nop
 8008ba4:	2000000c 	.word	0x2000000c
	...

08008bb0 <SVC_Handler>:
/*-----------------------------------------------------------*/

void vPortSVCHandler( void )
{
	__asm volatile (
 8008bb0:	4b07      	ldr	r3, [pc, #28]	@ (8008bd0 <pxCurrentTCBConst2>)
 8008bb2:	6819      	ldr	r1, [r3, #0]
 8008bb4:	6808      	ldr	r0, [r1, #0]
 8008bb6:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8008bba:	f380 8809 	msr	PSP, r0
 8008bbe:	f3bf 8f6f 	isb	sy
 8008bc2:	f04f 0000 	mov.w	r0, #0
 8008bc6:	f380 8811 	msr	BASEPRI, r0
 8008bca:	4770      	bx	lr
 8008bcc:	f3af 8000 	nop.w

08008bd0 <pxCurrentTCBConst2>:
 8008bd0:	20000fd0 	.word	0x20000fd0
					"	bx r14							\n"
					"									\n"
					"	.align 4						\n"
					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
				);
}
 8008bd4:	bf00      	nop
 8008bd6:	bf00      	nop

08008bd8 <prvPortStartFirstTask>:
{
	/* Start the first task.  This also clears the bit that indicates the FPU is
	in use in case the FPU was used before the scheduler was started - which
	would otherwise result in the unnecessary leaving of space in the SVC stack
	for lazy saving of FPU registers. */
	__asm volatile(
 8008bd8:	4808      	ldr	r0, [pc, #32]	@ (8008bfc <prvPortStartFirstTask+0x24>)
 8008bda:	6800      	ldr	r0, [r0, #0]
 8008bdc:	6800      	ldr	r0, [r0, #0]
 8008bde:	f380 8808 	msr	MSP, r0
 8008be2:	f04f 0000 	mov.w	r0, #0
 8008be6:	f380 8814 	msr	CONTROL, r0
 8008bea:	b662      	cpsie	i
 8008bec:	b661      	cpsie	f
 8008bee:	f3bf 8f4f 	dsb	sy
 8008bf2:	f3bf 8f6f 	isb	sy
 8008bf6:	df00      	svc	0
 8008bf8:	bf00      	nop
					" dsb					\n"
					" isb					\n"
					" svc 0					\n" /* System call to start first task. */
					" nop					\n"
				);
}
 8008bfa:	bf00      	nop
 8008bfc:	e000ed08 	.word	0xe000ed08

08008c00 <xPortStartScheduler>:

/*
 * See header file for description.
 */
BaseType_t xPortStartScheduler( void )
{
 8008c00:	b580      	push	{r7, lr}
 8008c02:	b086      	sub	sp, #24
 8008c04:	af00      	add	r7, sp, #0
	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );

	/* This port can be used on all revisions of the Cortex-M7 core other than
	the r0p1 parts.  r0p1 parts should use the port from the
	/source/portable/GCC/ARM_CM7/r0p1 directory. */
	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
 8008c06:	4b47      	ldr	r3, [pc, #284]	@ (8008d24 <xPortStartScheduler+0x124>)
 8008c08:	681b      	ldr	r3, [r3, #0]
 8008c0a:	4a47      	ldr	r2, [pc, #284]	@ (8008d28 <xPortStartScheduler+0x128>)
 8008c0c:	4293      	cmp	r3, r2
 8008c0e:	d10b      	bne.n	8008c28 <xPortStartScheduler+0x28>
	__asm volatile
 8008c10:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008c14:	f383 8811 	msr	BASEPRI, r3
 8008c18:	f3bf 8f6f 	isb	sy
 8008c1c:	f3bf 8f4f 	dsb	sy
 8008c20:	60fb      	str	r3, [r7, #12]
}
 8008c22:	bf00      	nop
 8008c24:	bf00      	nop
 8008c26:	e7fd      	b.n	8008c24 <xPortStartScheduler+0x24>
	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 8008c28:	4b3e      	ldr	r3, [pc, #248]	@ (8008d24 <xPortStartScheduler+0x124>)
 8008c2a:	681b      	ldr	r3, [r3, #0]
 8008c2c:	4a3f      	ldr	r2, [pc, #252]	@ (8008d2c <xPortStartScheduler+0x12c>)
 8008c2e:	4293      	cmp	r3, r2
 8008c30:	d10b      	bne.n	8008c4a <xPortStartScheduler+0x4a>
	__asm volatile
 8008c32:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008c36:	f383 8811 	msr	BASEPRI, r3
 8008c3a:	f3bf 8f6f 	isb	sy
 8008c3e:	f3bf 8f4f 	dsb	sy
 8008c42:	613b      	str	r3, [r7, #16]
}
 8008c44:	bf00      	nop
 8008c46:	bf00      	nop
 8008c48:	e7fd      	b.n	8008c46 <xPortStartScheduler+0x46>

	#if( configASSERT_DEFINED == 1 )
	{
		volatile uint32_t ulOriginalPriority;
		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
 8008c4a:	4b39      	ldr	r3, [pc, #228]	@ (8008d30 <xPortStartScheduler+0x130>)
 8008c4c:	617b      	str	r3, [r7, #20]
		functions can be called.  ISR safe functions are those that end in
		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
		ensure interrupt entry is as fast and simple as possible.

		Save the interrupt priority value that is about to be clobbered. */
		ulOriginalPriority = *pucFirstUserPriorityRegister;
 8008c4e:	697b      	ldr	r3, [r7, #20]
 8008c50:	781b      	ldrb	r3, [r3, #0]
 8008c52:	b2db      	uxtb	r3, r3
 8008c54:	607b      	str	r3, [r7, #4]

		/* Determine the number of priority bits available.  First write to all
		possible bits. */
		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 8008c56:	697b      	ldr	r3, [r7, #20]
 8008c58:	22ff      	movs	r2, #255	@ 0xff
 8008c5a:	701a      	strb	r2, [r3, #0]

		/* Read the value back to see how many bits stuck. */
		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 8008c5c:	697b      	ldr	r3, [r7, #20]
 8008c5e:	781b      	ldrb	r3, [r3, #0]
 8008c60:	b2db      	uxtb	r3, r3
 8008c62:	70fb      	strb	r3, [r7, #3]

		/* Use the same mask on the maximum system call priority. */
		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 8008c64:	78fb      	ldrb	r3, [r7, #3]
 8008c66:	b2db      	uxtb	r3, r3
 8008c68:	f003 0350 	and.w	r3, r3, #80	@ 0x50
 8008c6c:	b2da      	uxtb	r2, r3
 8008c6e:	4b31      	ldr	r3, [pc, #196]	@ (8008d34 <xPortStartScheduler+0x134>)
 8008c70:	701a      	strb	r2, [r3, #0]

		/* Calculate the maximum acceptable priority group value for the number
		of bits read back. */
		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
 8008c72:	4b31      	ldr	r3, [pc, #196]	@ (8008d38 <xPortStartScheduler+0x138>)
 8008c74:	2207      	movs	r2, #7
 8008c76:	601a      	str	r2, [r3, #0]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 8008c78:	e009      	b.n	8008c8e <xPortStartScheduler+0x8e>
		{
			ulMaxPRIGROUPValue--;
 8008c7a:	4b2f      	ldr	r3, [pc, #188]	@ (8008d38 <xPortStartScheduler+0x138>)
 8008c7c:	681b      	ldr	r3, [r3, #0]
 8008c7e:	3b01      	subs	r3, #1
 8008c80:	4a2d      	ldr	r2, [pc, #180]	@ (8008d38 <xPortStartScheduler+0x138>)
 8008c82:	6013      	str	r3, [r2, #0]
			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 8008c84:	78fb      	ldrb	r3, [r7, #3]
 8008c86:	b2db      	uxtb	r3, r3
 8008c88:	005b      	lsls	r3, r3, #1
 8008c8a:	b2db      	uxtb	r3, r3
 8008c8c:	70fb      	strb	r3, [r7, #3]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 8008c8e:	78fb      	ldrb	r3, [r7, #3]
 8008c90:	b2db      	uxtb	r3, r3
 8008c92:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8008c96:	2b80      	cmp	r3, #128	@ 0x80
 8008c98:	d0ef      	beq.n	8008c7a <xPortStartScheduler+0x7a>
		#ifdef configPRIO_BITS
		{
			/* Check the FreeRTOS configuration that defines the number of
			priority bits matches the number of priority bits actually queried
			from the hardware. */
			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
 8008c9a:	4b27      	ldr	r3, [pc, #156]	@ (8008d38 <xPortStartScheduler+0x138>)
 8008c9c:	681b      	ldr	r3, [r3, #0]
 8008c9e:	f1c3 0307 	rsb	r3, r3, #7
 8008ca2:	2b04      	cmp	r3, #4
 8008ca4:	d00b      	beq.n	8008cbe <xPortStartScheduler+0xbe>
	__asm volatile
 8008ca6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008caa:	f383 8811 	msr	BASEPRI, r3
 8008cae:	f3bf 8f6f 	isb	sy
 8008cb2:	f3bf 8f4f 	dsb	sy
 8008cb6:	60bb      	str	r3, [r7, #8]
}
 8008cb8:	bf00      	nop
 8008cba:	bf00      	nop
 8008cbc:	e7fd      	b.n	8008cba <xPortStartScheduler+0xba>
		}
		#endif

		/* Shift the priority group value back to its position within the AIRCR
		register. */
		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
 8008cbe:	4b1e      	ldr	r3, [pc, #120]	@ (8008d38 <xPortStartScheduler+0x138>)
 8008cc0:	681b      	ldr	r3, [r3, #0]
 8008cc2:	021b      	lsls	r3, r3, #8
 8008cc4:	4a1c      	ldr	r2, [pc, #112]	@ (8008d38 <xPortStartScheduler+0x138>)
 8008cc6:	6013      	str	r3, [r2, #0]
		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
 8008cc8:	4b1b      	ldr	r3, [pc, #108]	@ (8008d38 <xPortStartScheduler+0x138>)
 8008cca:	681b      	ldr	r3, [r3, #0]
 8008ccc:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
 8008cd0:	4a19      	ldr	r2, [pc, #100]	@ (8008d38 <xPortStartScheduler+0x138>)
 8008cd2:	6013      	str	r3, [r2, #0]

		/* Restore the clobbered interrupt priority register to its original
		value. */
		*pucFirstUserPriorityRegister = ulOriginalPriority;
 8008cd4:	687b      	ldr	r3, [r7, #4]
 8008cd6:	b2da      	uxtb	r2, r3
 8008cd8:	697b      	ldr	r3, [r7, #20]
 8008cda:	701a      	strb	r2, [r3, #0]
	}
	#endif /* conifgASSERT_DEFINED */

	/* Make PendSV and SysTick the lowest priority interrupts. */
	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
 8008cdc:	4b17      	ldr	r3, [pc, #92]	@ (8008d3c <xPortStartScheduler+0x13c>)
 8008cde:	681b      	ldr	r3, [r3, #0]
 8008ce0:	4a16      	ldr	r2, [pc, #88]	@ (8008d3c <xPortStartScheduler+0x13c>)
 8008ce2:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8008ce6:	6013      	str	r3, [r2, #0]
	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
 8008ce8:	4b14      	ldr	r3, [pc, #80]	@ (8008d3c <xPortStartScheduler+0x13c>)
 8008cea:	681b      	ldr	r3, [r3, #0]
 8008cec:	4a13      	ldr	r2, [pc, #76]	@ (8008d3c <xPortStartScheduler+0x13c>)
 8008cee:	f043 4370 	orr.w	r3, r3, #4026531840	@ 0xf0000000
 8008cf2:	6013      	str	r3, [r2, #0]

	/* Start the timer that generates the tick ISR.  Interrupts are disabled
	here already. */
	vPortSetupTimerInterrupt();
 8008cf4:	f000 f8da 	bl	8008eac <vPortSetupTimerInterrupt>

	/* Initialise the critical nesting count ready for the first task. */
	uxCriticalNesting = 0;
 8008cf8:	4b11      	ldr	r3, [pc, #68]	@ (8008d40 <xPortStartScheduler+0x140>)
 8008cfa:	2200      	movs	r2, #0
 8008cfc:	601a      	str	r2, [r3, #0]

	/* Ensure the VFP is enabled - it should be anyway. */
	vPortEnableVFP();
 8008cfe:	f000 f8f9 	bl	8008ef4 <vPortEnableVFP>

	/* Lazy save always. */
	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
 8008d02:	4b10      	ldr	r3, [pc, #64]	@ (8008d44 <xPortStartScheduler+0x144>)
 8008d04:	681b      	ldr	r3, [r3, #0]
 8008d06:	4a0f      	ldr	r2, [pc, #60]	@ (8008d44 <xPortStartScheduler+0x144>)
 8008d08:	f043 4340 	orr.w	r3, r3, #3221225472	@ 0xc0000000
 8008d0c:	6013      	str	r3, [r2, #0]

	/* Start the first task. */
	prvPortStartFirstTask();
 8008d0e:	f7ff ff63 	bl	8008bd8 <prvPortStartFirstTask>
	exit error function to prevent compiler warnings about a static function
	not being called in the case that the application writer overrides this
	functionality by defining configTASK_RETURN_ADDRESS.  Call
	vTaskSwitchContext() so link time optimisation does not remove the
	symbol. */
	vTaskSwitchContext();
 8008d12:	f7fe ff2d 	bl	8007b70 <vTaskSwitchContext>
	prvTaskExitError();
 8008d16:	f7ff ff19 	bl	8008b4c <prvTaskExitError>

	/* Should not get here! */
	return 0;
 8008d1a:	2300      	movs	r3, #0
}
 8008d1c:	4618      	mov	r0, r3
 8008d1e:	3718      	adds	r7, #24
 8008d20:	46bd      	mov	sp, r7
 8008d22:	bd80      	pop	{r7, pc}
 8008d24:	e000ed00 	.word	0xe000ed00
 8008d28:	410fc271 	.word	0x410fc271
 8008d2c:	410fc270 	.word	0x410fc270
 8008d30:	e000e400 	.word	0xe000e400
 8008d34:	200015fc 	.word	0x200015fc
 8008d38:	20001600 	.word	0x20001600
 8008d3c:	e000ed20 	.word	0xe000ed20
 8008d40:	2000000c 	.word	0x2000000c
 8008d44:	e000ef34 	.word	0xe000ef34

08008d48 <vPortEnterCritical>:
	configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/

void vPortEnterCritical( void )
{
 8008d48:	b480      	push	{r7}
 8008d4a:	b083      	sub	sp, #12
 8008d4c:	af00      	add	r7, sp, #0
	__asm volatile
 8008d4e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008d52:	f383 8811 	msr	BASEPRI, r3
 8008d56:	f3bf 8f6f 	isb	sy
 8008d5a:	f3bf 8f4f 	dsb	sy
 8008d5e:	607b      	str	r3, [r7, #4]
}
 8008d60:	bf00      	nop
	portDISABLE_INTERRUPTS();
	uxCriticalNesting++;
 8008d62:	4b10      	ldr	r3, [pc, #64]	@ (8008da4 <vPortEnterCritical+0x5c>)
 8008d64:	681b      	ldr	r3, [r3, #0]
 8008d66:	3301      	adds	r3, #1
 8008d68:	4a0e      	ldr	r2, [pc, #56]	@ (8008da4 <vPortEnterCritical+0x5c>)
 8008d6a:	6013      	str	r3, [r2, #0]
	/* This is not the interrupt safe version of the enter critical function so
	assert() if it is being called from an interrupt context.  Only API
	functions that end in "FromISR" can be used in an interrupt.  Only assert if
	the critical nesting count is 1 to protect against recursive calls if the
	assert function also uses a critical section. */
	if( uxCriticalNesting == 1 )
 8008d6c:	4b0d      	ldr	r3, [pc, #52]	@ (8008da4 <vPortEnterCritical+0x5c>)
 8008d6e:	681b      	ldr	r3, [r3, #0]
 8008d70:	2b01      	cmp	r3, #1
 8008d72:	d110      	bne.n	8008d96 <vPortEnterCritical+0x4e>
	{
		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
 8008d74:	4b0c      	ldr	r3, [pc, #48]	@ (8008da8 <vPortEnterCritical+0x60>)
 8008d76:	681b      	ldr	r3, [r3, #0]
 8008d78:	b2db      	uxtb	r3, r3
 8008d7a:	2b00      	cmp	r3, #0
 8008d7c:	d00b      	beq.n	8008d96 <vPortEnterCritical+0x4e>
	__asm volatile
 8008d7e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008d82:	f383 8811 	msr	BASEPRI, r3
 8008d86:	f3bf 8f6f 	isb	sy
 8008d8a:	f3bf 8f4f 	dsb	sy
 8008d8e:	603b      	str	r3, [r7, #0]
}
 8008d90:	bf00      	nop
 8008d92:	bf00      	nop
 8008d94:	e7fd      	b.n	8008d92 <vPortEnterCritical+0x4a>
	}
}
 8008d96:	bf00      	nop
 8008d98:	370c      	adds	r7, #12
 8008d9a:	46bd      	mov	sp, r7
 8008d9c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008da0:	4770      	bx	lr
 8008da2:	bf00      	nop
 8008da4:	2000000c 	.word	0x2000000c
 8008da8:	e000ed04 	.word	0xe000ed04

08008dac <vPortExitCritical>:
/*-----------------------------------------------------------*/

void vPortExitCritical( void )
{
 8008dac:	b480      	push	{r7}
 8008dae:	b083      	sub	sp, #12
 8008db0:	af00      	add	r7, sp, #0
	configASSERT( uxCriticalNesting );
 8008db2:	4b12      	ldr	r3, [pc, #72]	@ (8008dfc <vPortExitCritical+0x50>)
 8008db4:	681b      	ldr	r3, [r3, #0]
 8008db6:	2b00      	cmp	r3, #0
 8008db8:	d10b      	bne.n	8008dd2 <vPortExitCritical+0x26>
	__asm volatile
 8008dba:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008dbe:	f383 8811 	msr	BASEPRI, r3
 8008dc2:	f3bf 8f6f 	isb	sy
 8008dc6:	f3bf 8f4f 	dsb	sy
 8008dca:	607b      	str	r3, [r7, #4]
}
 8008dcc:	bf00      	nop
 8008dce:	bf00      	nop
 8008dd0:	e7fd      	b.n	8008dce <vPortExitCritical+0x22>
	uxCriticalNesting--;
 8008dd2:	4b0a      	ldr	r3, [pc, #40]	@ (8008dfc <vPortExitCritical+0x50>)
 8008dd4:	681b      	ldr	r3, [r3, #0]
 8008dd6:	3b01      	subs	r3, #1
 8008dd8:	4a08      	ldr	r2, [pc, #32]	@ (8008dfc <vPortExitCritical+0x50>)
 8008dda:	6013      	str	r3, [r2, #0]
	if( uxCriticalNesting == 0 )
 8008ddc:	4b07      	ldr	r3, [pc, #28]	@ (8008dfc <vPortExitCritical+0x50>)
 8008dde:	681b      	ldr	r3, [r3, #0]
 8008de0:	2b00      	cmp	r3, #0
 8008de2:	d105      	bne.n	8008df0 <vPortExitCritical+0x44>
 8008de4:	2300      	movs	r3, #0
 8008de6:	603b      	str	r3, [r7, #0]
	__asm volatile
 8008de8:	683b      	ldr	r3, [r7, #0]
 8008dea:	f383 8811 	msr	BASEPRI, r3
}
 8008dee:	bf00      	nop
	{
		portENABLE_INTERRUPTS();
	}
}
 8008df0:	bf00      	nop
 8008df2:	370c      	adds	r7, #12
 8008df4:	46bd      	mov	sp, r7
 8008df6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008dfa:	4770      	bx	lr
 8008dfc:	2000000c 	.word	0x2000000c

08008e00 <PendSV_Handler>:

void xPortPendSVHandler( void )
{
	/* This is a naked function. */

	__asm volatile
 8008e00:	f3ef 8009 	mrs	r0, PSP
 8008e04:	f3bf 8f6f 	isb	sy
 8008e08:	4b15      	ldr	r3, [pc, #84]	@ (8008e60 <pxCurrentTCBConst>)
 8008e0a:	681a      	ldr	r2, [r3, #0]
 8008e0c:	f01e 0f10 	tst.w	lr, #16
 8008e10:	bf08      	it	eq
 8008e12:	ed20 8a10 	vstmdbeq	r0!, {s16-s31}
 8008e16:	e920 4ff0 	stmdb	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8008e1a:	6010      	str	r0, [r2, #0]
 8008e1c:	e92d 0009 	stmdb	sp!, {r0, r3}
 8008e20:	f04f 0050 	mov.w	r0, #80	@ 0x50
 8008e24:	f380 8811 	msr	BASEPRI, r0
 8008e28:	f3bf 8f4f 	dsb	sy
 8008e2c:	f3bf 8f6f 	isb	sy
 8008e30:	f7fe fe9e 	bl	8007b70 <vTaskSwitchContext>
 8008e34:	f04f 0000 	mov.w	r0, #0
 8008e38:	f380 8811 	msr	BASEPRI, r0
 8008e3c:	bc09      	pop	{r0, r3}
 8008e3e:	6819      	ldr	r1, [r3, #0]
 8008e40:	6808      	ldr	r0, [r1, #0]
 8008e42:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8008e46:	f01e 0f10 	tst.w	lr, #16
 8008e4a:	bf08      	it	eq
 8008e4c:	ecb0 8a10 	vldmiaeq	r0!, {s16-s31}
 8008e50:	f380 8809 	msr	PSP, r0
 8008e54:	f3bf 8f6f 	isb	sy
 8008e58:	4770      	bx	lr
 8008e5a:	bf00      	nop
 8008e5c:	f3af 8000 	nop.w

08008e60 <pxCurrentTCBConst>:
 8008e60:	20000fd0 	.word	0x20000fd0
	"										\n"
	"	.align 4							\n"
	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
	);
}
 8008e64:	bf00      	nop
 8008e66:	bf00      	nop

08008e68 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/

void xPortSysTickHandler( void )
{
 8008e68:	b580      	push	{r7, lr}
 8008e6a:	b082      	sub	sp, #8
 8008e6c:	af00      	add	r7, sp, #0
	__asm volatile
 8008e6e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008e72:	f383 8811 	msr	BASEPRI, r3
 8008e76:	f3bf 8f6f 	isb	sy
 8008e7a:	f3bf 8f4f 	dsb	sy
 8008e7e:	607b      	str	r3, [r7, #4]
}
 8008e80:	bf00      	nop
	save and then restore the interrupt mask value as its value is already
	known. */
	portDISABLE_INTERRUPTS();
	{
		/* Increment the RTOS tick. */
		if( xTaskIncrementTick() != pdFALSE )
 8008e82:	f7fe fdbb 	bl	80079fc <xTaskIncrementTick>
 8008e86:	4603      	mov	r3, r0
 8008e88:	2b00      	cmp	r3, #0
 8008e8a:	d003      	beq.n	8008e94 <xPortSysTickHandler+0x2c>
		{
			/* A context switch is required.  Context switching is performed in
			the PendSV interrupt.  Pend the PendSV interrupt. */
			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
 8008e8c:	4b06      	ldr	r3, [pc, #24]	@ (8008ea8 <xPortSysTickHandler+0x40>)
 8008e8e:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8008e92:	601a      	str	r2, [r3, #0]
 8008e94:	2300      	movs	r3, #0
 8008e96:	603b      	str	r3, [r7, #0]
	__asm volatile
 8008e98:	683b      	ldr	r3, [r7, #0]
 8008e9a:	f383 8811 	msr	BASEPRI, r3
}
 8008e9e:	bf00      	nop
		}
	}
	portENABLE_INTERRUPTS();
}
 8008ea0:	bf00      	nop
 8008ea2:	3708      	adds	r7, #8
 8008ea4:	46bd      	mov	sp, r7
 8008ea6:	bd80      	pop	{r7, pc}
 8008ea8:	e000ed04 	.word	0xe000ed04

08008eac <vPortSetupTimerInterrupt>:
/*
 * Setup the systick timer to generate the tick interrupts at the required
 * frequency.
 */
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
 8008eac:	b480      	push	{r7}
 8008eae:	af00      	add	r7, sp, #0
		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
	}
	#endif /* configUSE_TICKLESS_IDLE */

	/* Stop and clear the SysTick. */
	portNVIC_SYSTICK_CTRL_REG = 0UL;
 8008eb0:	4b0b      	ldr	r3, [pc, #44]	@ (8008ee0 <vPortSetupTimerInterrupt+0x34>)
 8008eb2:	2200      	movs	r2, #0
 8008eb4:	601a      	str	r2, [r3, #0]
	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 8008eb6:	4b0b      	ldr	r3, [pc, #44]	@ (8008ee4 <vPortSetupTimerInterrupt+0x38>)
 8008eb8:	2200      	movs	r2, #0
 8008eba:	601a      	str	r2, [r3, #0]

	/* Configure SysTick to interrupt at the requested rate. */
	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
 8008ebc:	4b0a      	ldr	r3, [pc, #40]	@ (8008ee8 <vPortSetupTimerInterrupt+0x3c>)
 8008ebe:	681b      	ldr	r3, [r3, #0]
 8008ec0:	4a0a      	ldr	r2, [pc, #40]	@ (8008eec <vPortSetupTimerInterrupt+0x40>)
 8008ec2:	fba2 2303 	umull	r2, r3, r2, r3
 8008ec6:	099b      	lsrs	r3, r3, #6
 8008ec8:	4a09      	ldr	r2, [pc, #36]	@ (8008ef0 <vPortSetupTimerInterrupt+0x44>)
 8008eca:	3b01      	subs	r3, #1
 8008ecc:	6013      	str	r3, [r2, #0]
	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
 8008ece:	4b04      	ldr	r3, [pc, #16]	@ (8008ee0 <vPortSetupTimerInterrupt+0x34>)
 8008ed0:	2207      	movs	r2, #7
 8008ed2:	601a      	str	r2, [r3, #0]
}
 8008ed4:	bf00      	nop
 8008ed6:	46bd      	mov	sp, r7
 8008ed8:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008edc:	4770      	bx	lr
 8008ede:	bf00      	nop
 8008ee0:	e000e010 	.word	0xe000e010
 8008ee4:	e000e018 	.word	0xe000e018
 8008ee8:	20000000 	.word	0x20000000
 8008eec:	10624dd3 	.word	0x10624dd3
 8008ef0:	e000e014 	.word	0xe000e014

08008ef4 <vPortEnableVFP>:
/*-----------------------------------------------------------*/

/* This is a naked function. */
static void vPortEnableVFP( void )
{
	__asm volatile
 8008ef4:	f8df 000c 	ldr.w	r0, [pc, #12]	@ 8008f04 <vPortEnableVFP+0x10>
 8008ef8:	6801      	ldr	r1, [r0, #0]
 8008efa:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
 8008efe:	6001      	str	r1, [r0, #0]
 8008f00:	4770      	bx	lr
		"								\n"
		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
		"	str r1, [r0]				\n"
		"	bx r14						"
	);
}
 8008f02:	bf00      	nop
 8008f04:	e000ed88 	.word	0xe000ed88

08008f08 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/

#if( configASSERT_DEFINED == 1 )

	void vPortValidateInterruptPriority( void )
	{
 8008f08:	b480      	push	{r7}
 8008f0a:	b085      	sub	sp, #20
 8008f0c:	af00      	add	r7, sp, #0
	uint32_t ulCurrentInterrupt;
	uint8_t ucCurrentPriority;

		/* Obtain the number of the currently executing interrupt. */
		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 8008f0e:	f3ef 8305 	mrs	r3, IPSR
 8008f12:	60fb      	str	r3, [r7, #12]

		/* Is the interrupt number a user defined interrupt? */
		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
 8008f14:	68fb      	ldr	r3, [r7, #12]
 8008f16:	2b0f      	cmp	r3, #15
 8008f18:	d915      	bls.n	8008f46 <vPortValidateInterruptPriority+0x3e>
		{
			/* Look up the interrupt's priority. */
			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
 8008f1a:	4a18      	ldr	r2, [pc, #96]	@ (8008f7c <vPortValidateInterruptPriority+0x74>)
 8008f1c:	68fb      	ldr	r3, [r7, #12]
 8008f1e:	4413      	add	r3, r2
 8008f20:	781b      	ldrb	r3, [r3, #0]
 8008f22:	72fb      	strb	r3, [r7, #11]
			interrupt entry is as fast and simple as possible.

			The following links provide detailed information:
			http://www.freertos.org/RTOS-Cortex-M3-M4.html
			http://www.freertos.org/FAQHelp.html */
			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
 8008f24:	4b16      	ldr	r3, [pc, #88]	@ (8008f80 <vPortValidateInterruptPriority+0x78>)
 8008f26:	781b      	ldrb	r3, [r3, #0]
 8008f28:	7afa      	ldrb	r2, [r7, #11]
 8008f2a:	429a      	cmp	r2, r3
 8008f2c:	d20b      	bcs.n	8008f46 <vPortValidateInterruptPriority+0x3e>
	__asm volatile
 8008f2e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008f32:	f383 8811 	msr	BASEPRI, r3
 8008f36:	f3bf 8f6f 	isb	sy
 8008f3a:	f3bf 8f4f 	dsb	sy
 8008f3e:	607b      	str	r3, [r7, #4]
}
 8008f40:	bf00      	nop
 8008f42:	bf00      	nop
 8008f44:	e7fd      	b.n	8008f42 <vPortValidateInterruptPriority+0x3a>
		configuration then the correct setting can be achieved on all Cortex-M
		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
		scheduler.  Note however that some vendor specific peripheral libraries
		assume a non-zero priority group setting, in which cases using a value
		of zero will result in unpredictable behaviour. */
		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
 8008f46:	4b0f      	ldr	r3, [pc, #60]	@ (8008f84 <vPortValidateInterruptPriority+0x7c>)
 8008f48:	681b      	ldr	r3, [r3, #0]
 8008f4a:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 8008f4e:	4b0e      	ldr	r3, [pc, #56]	@ (8008f88 <vPortValidateInterruptPriority+0x80>)
 8008f50:	681b      	ldr	r3, [r3, #0]
 8008f52:	429a      	cmp	r2, r3
 8008f54:	d90b      	bls.n	8008f6e <vPortValidateInterruptPriority+0x66>
	__asm volatile
 8008f56:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008f5a:	f383 8811 	msr	BASEPRI, r3
 8008f5e:	f3bf 8f6f 	isb	sy
 8008f62:	f3bf 8f4f 	dsb	sy
 8008f66:	603b      	str	r3, [r7, #0]
}
 8008f68:	bf00      	nop
 8008f6a:	bf00      	nop
 8008f6c:	e7fd      	b.n	8008f6a <vPortValidateInterruptPriority+0x62>
	}
 8008f6e:	bf00      	nop
 8008f70:	3714      	adds	r7, #20
 8008f72:	46bd      	mov	sp, r7
 8008f74:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008f78:	4770      	bx	lr
 8008f7a:	bf00      	nop
 8008f7c:	e000e3f0 	.word	0xe000e3f0
 8008f80:	200015fc 	.word	0x200015fc
 8008f84:	e000ed0c 	.word	0xe000ed0c
 8008f88:	20001600 	.word	0x20001600

08008f8c <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;

/*-----------------------------------------------------------*/

void *pvPortMalloc( size_t xWantedSize )
{
 8008f8c:	b580      	push	{r7, lr}
 8008f8e:	b08a      	sub	sp, #40	@ 0x28
 8008f90:	af00      	add	r7, sp, #0
 8008f92:	6078      	str	r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
 8008f94:	2300      	movs	r3, #0
 8008f96:	61fb      	str	r3, [r7, #28]

	vTaskSuspendAll();
 8008f98:	f7fe fc74 	bl	8007884 <vTaskSuspendAll>
	{
		/* If this is the first call to malloc then the heap will require
		initialisation to setup the list of free blocks. */
		if( pxEnd == NULL )
 8008f9c:	4b5c      	ldr	r3, [pc, #368]	@ (8009110 <pvPortMalloc+0x184>)
 8008f9e:	681b      	ldr	r3, [r3, #0]
 8008fa0:	2b00      	cmp	r3, #0
 8008fa2:	d101      	bne.n	8008fa8 <pvPortMalloc+0x1c>
		{
			prvHeapInit();
 8008fa4:	f000 f924 	bl	80091f0 <prvHeapInit>

		/* Check the requested block size is not so large that the top bit is
		set.  The top bit of the block size member of the BlockLink_t structure
		is used to determine who owns the block - the application or the
		kernel, so it must be free. */
		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
 8008fa8:	4b5a      	ldr	r3, [pc, #360]	@ (8009114 <pvPortMalloc+0x188>)
 8008faa:	681a      	ldr	r2, [r3, #0]
 8008fac:	687b      	ldr	r3, [r7, #4]
 8008fae:	4013      	ands	r3, r2
 8008fb0:	2b00      	cmp	r3, #0
 8008fb2:	f040 8095 	bne.w	80090e0 <pvPortMalloc+0x154>
		{
			/* The wanted size is increased so it can contain a BlockLink_t
			structure in addition to the requested amount of bytes. */
			if( xWantedSize > 0 )
 8008fb6:	687b      	ldr	r3, [r7, #4]
 8008fb8:	2b00      	cmp	r3, #0
 8008fba:	d01e      	beq.n	8008ffa <pvPortMalloc+0x6e>
			{
				xWantedSize += xHeapStructSize;
 8008fbc:	2208      	movs	r2, #8
 8008fbe:	687b      	ldr	r3, [r7, #4]
 8008fc0:	4413      	add	r3, r2
 8008fc2:	607b      	str	r3, [r7, #4]

				/* Ensure that blocks are always aligned to the required number
				of bytes. */
				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
 8008fc4:	687b      	ldr	r3, [r7, #4]
 8008fc6:	f003 0307 	and.w	r3, r3, #7
 8008fca:	2b00      	cmp	r3, #0
 8008fcc:	d015      	beq.n	8008ffa <pvPortMalloc+0x6e>
				{
					/* Byte alignment required. */
					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
 8008fce:	687b      	ldr	r3, [r7, #4]
 8008fd0:	f023 0307 	bic.w	r3, r3, #7
 8008fd4:	3308      	adds	r3, #8
 8008fd6:	607b      	str	r3, [r7, #4]
					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
 8008fd8:	687b      	ldr	r3, [r7, #4]
 8008fda:	f003 0307 	and.w	r3, r3, #7
 8008fde:	2b00      	cmp	r3, #0
 8008fe0:	d00b      	beq.n	8008ffa <pvPortMalloc+0x6e>
	__asm volatile
 8008fe2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8008fe6:	f383 8811 	msr	BASEPRI, r3
 8008fea:	f3bf 8f6f 	isb	sy
 8008fee:	f3bf 8f4f 	dsb	sy
 8008ff2:	617b      	str	r3, [r7, #20]
}
 8008ff4:	bf00      	nop
 8008ff6:	bf00      	nop
 8008ff8:	e7fd      	b.n	8008ff6 <pvPortMalloc+0x6a>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
 8008ffa:	687b      	ldr	r3, [r7, #4]
 8008ffc:	2b00      	cmp	r3, #0
 8008ffe:	d06f      	beq.n	80090e0 <pvPortMalloc+0x154>
 8009000:	4b45      	ldr	r3, [pc, #276]	@ (8009118 <pvPortMalloc+0x18c>)
 8009002:	681b      	ldr	r3, [r3, #0]
 8009004:	687a      	ldr	r2, [r7, #4]
 8009006:	429a      	cmp	r2, r3
 8009008:	d86a      	bhi.n	80090e0 <pvPortMalloc+0x154>
			{
				/* Traverse the list from the start	(lowest address) block until
				one	of adequate size is found. */
				pxPreviousBlock = &xStart;
 800900a:	4b44      	ldr	r3, [pc, #272]	@ (800911c <pvPortMalloc+0x190>)
 800900c:	623b      	str	r3, [r7, #32]
				pxBlock = xStart.pxNextFreeBlock;
 800900e:	4b43      	ldr	r3, [pc, #268]	@ (800911c <pvPortMalloc+0x190>)
 8009010:	681b      	ldr	r3, [r3, #0]
 8009012:	627b      	str	r3, [r7, #36]	@ 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8009014:	e004      	b.n	8009020 <pvPortMalloc+0x94>
				{
					pxPreviousBlock = pxBlock;
 8009016:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8009018:	623b      	str	r3, [r7, #32]
					pxBlock = pxBlock->pxNextFreeBlock;
 800901a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800901c:	681b      	ldr	r3, [r3, #0]
 800901e:	627b      	str	r3, [r7, #36]	@ 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8009020:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8009022:	685b      	ldr	r3, [r3, #4]
 8009024:	687a      	ldr	r2, [r7, #4]
 8009026:	429a      	cmp	r2, r3
 8009028:	d903      	bls.n	8009032 <pvPortMalloc+0xa6>
 800902a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800902c:	681b      	ldr	r3, [r3, #0]
 800902e:	2b00      	cmp	r3, #0
 8009030:	d1f1      	bne.n	8009016 <pvPortMalloc+0x8a>
				}

				/* If the end marker was reached then a block of adequate size
				was	not found. */
				if( pxBlock != pxEnd )
 8009032:	4b37      	ldr	r3, [pc, #220]	@ (8009110 <pvPortMalloc+0x184>)
 8009034:	681b      	ldr	r3, [r3, #0]
 8009036:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8009038:	429a      	cmp	r2, r3
 800903a:	d051      	beq.n	80090e0 <pvPortMalloc+0x154>
				{
					/* Return the memory space pointed to - jumping over the
					BlockLink_t structure at its start. */
					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
 800903c:	6a3b      	ldr	r3, [r7, #32]
 800903e:	681b      	ldr	r3, [r3, #0]
 8009040:	2208      	movs	r2, #8
 8009042:	4413      	add	r3, r2
 8009044:	61fb      	str	r3, [r7, #28]

					/* This block is being returned for use so must be taken out
					of the list of free blocks. */
					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
 8009046:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8009048:	681a      	ldr	r2, [r3, #0]
 800904a:	6a3b      	ldr	r3, [r7, #32]
 800904c:	601a      	str	r2, [r3, #0]

					/* If the block is larger than required it can be split into
					two. */
					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
 800904e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8009050:	685a      	ldr	r2, [r3, #4]
 8009052:	687b      	ldr	r3, [r7, #4]
 8009054:	1ad2      	subs	r2, r2, r3
 8009056:	2308      	movs	r3, #8
 8009058:	005b      	lsls	r3, r3, #1
 800905a:	429a      	cmp	r2, r3
 800905c:	d920      	bls.n	80090a0 <pvPortMalloc+0x114>
					{
						/* This block is to be split into two.  Create a new
						block following the number of bytes requested. The void
						cast is used to prevent byte alignment warnings from the
						compiler. */
						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
 800905e:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8009060:	687b      	ldr	r3, [r7, #4]
 8009062:	4413      	add	r3, r2
 8009064:	61bb      	str	r3, [r7, #24]
						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
 8009066:	69bb      	ldr	r3, [r7, #24]
 8009068:	f003 0307 	and.w	r3, r3, #7
 800906c:	2b00      	cmp	r3, #0
 800906e:	d00b      	beq.n	8009088 <pvPortMalloc+0xfc>
	__asm volatile
 8009070:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8009074:	f383 8811 	msr	BASEPRI, r3
 8009078:	f3bf 8f6f 	isb	sy
 800907c:	f3bf 8f4f 	dsb	sy
 8009080:	613b      	str	r3, [r7, #16]
}
 8009082:	bf00      	nop
 8009084:	bf00      	nop
 8009086:	e7fd      	b.n	8009084 <pvPortMalloc+0xf8>

						/* Calculate the sizes of two blocks split from the
						single block. */
						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
 8009088:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800908a:	685a      	ldr	r2, [r3, #4]
 800908c:	687b      	ldr	r3, [r7, #4]
 800908e:	1ad2      	subs	r2, r2, r3
 8009090:	69bb      	ldr	r3, [r7, #24]
 8009092:	605a      	str	r2, [r3, #4]
						pxBlock->xBlockSize = xWantedSize;
 8009094:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8009096:	687a      	ldr	r2, [r7, #4]
 8009098:	605a      	str	r2, [r3, #4]

						/* Insert the new block into the list of free blocks. */
						prvInsertBlockIntoFreeList( pxNewBlockLink );
 800909a:	69b8      	ldr	r0, [r7, #24]
 800909c:	f000 f90a 	bl	80092b4 <prvInsertBlockIntoFreeList>
					else
					{
						mtCOVERAGE_TEST_MARKER();
					}

					xFreeBytesRemaining -= pxBlock->xBlockSize;
 80090a0:	4b1d      	ldr	r3, [pc, #116]	@ (8009118 <pvPortMalloc+0x18c>)
 80090a2:	681a      	ldr	r2, [r3, #0]
 80090a4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80090a6:	685b      	ldr	r3, [r3, #4]
 80090a8:	1ad3      	subs	r3, r2, r3
 80090aa:	4a1b      	ldr	r2, [pc, #108]	@ (8009118 <pvPortMalloc+0x18c>)
 80090ac:	6013      	str	r3, [r2, #0]

					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
 80090ae:	4b1a      	ldr	r3, [pc, #104]	@ (8009118 <pvPortMalloc+0x18c>)
 80090b0:	681a      	ldr	r2, [r3, #0]
 80090b2:	4b1b      	ldr	r3, [pc, #108]	@ (8009120 <pvPortMalloc+0x194>)
 80090b4:	681b      	ldr	r3, [r3, #0]
 80090b6:	429a      	cmp	r2, r3
 80090b8:	d203      	bcs.n	80090c2 <pvPortMalloc+0x136>
					{
						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
 80090ba:	4b17      	ldr	r3, [pc, #92]	@ (8009118 <pvPortMalloc+0x18c>)
 80090bc:	681b      	ldr	r3, [r3, #0]
 80090be:	4a18      	ldr	r2, [pc, #96]	@ (8009120 <pvPortMalloc+0x194>)
 80090c0:	6013      	str	r3, [r2, #0]
						mtCOVERAGE_TEST_MARKER();
					}

					/* The block is being returned - it is allocated and owned
					by the application and has no "next" block. */
					pxBlock->xBlockSize |= xBlockAllocatedBit;
 80090c2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80090c4:	685a      	ldr	r2, [r3, #4]
 80090c6:	4b13      	ldr	r3, [pc, #76]	@ (8009114 <pvPortMalloc+0x188>)
 80090c8:	681b      	ldr	r3, [r3, #0]
 80090ca:	431a      	orrs	r2, r3
 80090cc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80090ce:	605a      	str	r2, [r3, #4]
					pxBlock->pxNextFreeBlock = NULL;
 80090d0:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80090d2:	2200      	movs	r2, #0
 80090d4:	601a      	str	r2, [r3, #0]
					xNumberOfSuccessfulAllocations++;
 80090d6:	4b13      	ldr	r3, [pc, #76]	@ (8009124 <pvPortMalloc+0x198>)
 80090d8:	681b      	ldr	r3, [r3, #0]
 80090da:	3301      	adds	r3, #1
 80090dc:	4a11      	ldr	r2, [pc, #68]	@ (8009124 <pvPortMalloc+0x198>)
 80090de:	6013      	str	r3, [r2, #0]
			mtCOVERAGE_TEST_MARKER();
		}

		traceMALLOC( pvReturn, xWantedSize );
	}
	( void ) xTaskResumeAll();
 80090e0:	f7fe fbde 	bl	80078a0 <xTaskResumeAll>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif

	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
 80090e4:	69fb      	ldr	r3, [r7, #28]
 80090e6:	f003 0307 	and.w	r3, r3, #7
 80090ea:	2b00      	cmp	r3, #0
 80090ec:	d00b      	beq.n	8009106 <pvPortMalloc+0x17a>
	__asm volatile
 80090ee:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80090f2:	f383 8811 	msr	BASEPRI, r3
 80090f6:	f3bf 8f6f 	isb	sy
 80090fa:	f3bf 8f4f 	dsb	sy
 80090fe:	60fb      	str	r3, [r7, #12]
}
 8009100:	bf00      	nop
 8009102:	bf00      	nop
 8009104:	e7fd      	b.n	8009102 <pvPortMalloc+0x176>
	return pvReturn;
 8009106:	69fb      	ldr	r3, [r7, #28]
}
 8009108:	4618      	mov	r0, r3
 800910a:	3728      	adds	r7, #40	@ 0x28
 800910c:	46bd      	mov	sp, r7
 800910e:	bd80      	pop	{r7, pc}
 8009110:	20008b3c 	.word	0x20008b3c
 8009114:	20008b50 	.word	0x20008b50
 8009118:	20008b40 	.word	0x20008b40
 800911c:	20008b34 	.word	0x20008b34
 8009120:	20008b44 	.word	0x20008b44
 8009124:	20008b48 	.word	0x20008b48

08009128 <vPortFree>:
/*-----------------------------------------------------------*/

void vPortFree( void *pv )
{
 8009128:	b580      	push	{r7, lr}
 800912a:	b086      	sub	sp, #24
 800912c:	af00      	add	r7, sp, #0
 800912e:	6078      	str	r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
 8009130:	687b      	ldr	r3, [r7, #4]
 8009132:	617b      	str	r3, [r7, #20]
BlockLink_t *pxLink;

	if( pv != NULL )
 8009134:	687b      	ldr	r3, [r7, #4]
 8009136:	2b00      	cmp	r3, #0
 8009138:	d04f      	beq.n	80091da <vPortFree+0xb2>
	{
		/* The memory being freed will have an BlockLink_t structure immediately
		before it. */
		puc -= xHeapStructSize;
 800913a:	2308      	movs	r3, #8
 800913c:	425b      	negs	r3, r3
 800913e:	697a      	ldr	r2, [r7, #20]
 8009140:	4413      	add	r3, r2
 8009142:	617b      	str	r3, [r7, #20]

		/* This casting is to keep the compiler from issuing warnings. */
		pxLink = ( void * ) puc;
 8009144:	697b      	ldr	r3, [r7, #20]
 8009146:	613b      	str	r3, [r7, #16]

		/* Check the block is actually allocated. */
		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
 8009148:	693b      	ldr	r3, [r7, #16]
 800914a:	685a      	ldr	r2, [r3, #4]
 800914c:	4b25      	ldr	r3, [pc, #148]	@ (80091e4 <vPortFree+0xbc>)
 800914e:	681b      	ldr	r3, [r3, #0]
 8009150:	4013      	ands	r3, r2
 8009152:	2b00      	cmp	r3, #0
 8009154:	d10b      	bne.n	800916e <vPortFree+0x46>
	__asm volatile
 8009156:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800915a:	f383 8811 	msr	BASEPRI, r3
 800915e:	f3bf 8f6f 	isb	sy
 8009162:	f3bf 8f4f 	dsb	sy
 8009166:	60fb      	str	r3, [r7, #12]
}
 8009168:	bf00      	nop
 800916a:	bf00      	nop
 800916c:	e7fd      	b.n	800916a <vPortFree+0x42>
		configASSERT( pxLink->pxNextFreeBlock == NULL );
 800916e:	693b      	ldr	r3, [r7, #16]
 8009170:	681b      	ldr	r3, [r3, #0]
 8009172:	2b00      	cmp	r3, #0
 8009174:	d00b      	beq.n	800918e <vPortFree+0x66>
	__asm volatile
 8009176:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800917a:	f383 8811 	msr	BASEPRI, r3
 800917e:	f3bf 8f6f 	isb	sy
 8009182:	f3bf 8f4f 	dsb	sy
 8009186:	60bb      	str	r3, [r7, #8]
}
 8009188:	bf00      	nop
 800918a:	bf00      	nop
 800918c:	e7fd      	b.n	800918a <vPortFree+0x62>

		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
 800918e:	693b      	ldr	r3, [r7, #16]
 8009190:	685a      	ldr	r2, [r3, #4]
 8009192:	4b14      	ldr	r3, [pc, #80]	@ (80091e4 <vPortFree+0xbc>)
 8009194:	681b      	ldr	r3, [r3, #0]
 8009196:	4013      	ands	r3, r2
 8009198:	2b00      	cmp	r3, #0
 800919a:	d01e      	beq.n	80091da <vPortFree+0xb2>
		{
			if( pxLink->pxNextFreeBlock == NULL )
 800919c:	693b      	ldr	r3, [r7, #16]
 800919e:	681b      	ldr	r3, [r3, #0]
 80091a0:	2b00      	cmp	r3, #0
 80091a2:	d11a      	bne.n	80091da <vPortFree+0xb2>
			{
				/* The block is being returned to the heap - it is no longer
				allocated. */
				pxLink->xBlockSize &= ~xBlockAllocatedBit;
 80091a4:	693b      	ldr	r3, [r7, #16]
 80091a6:	685a      	ldr	r2, [r3, #4]
 80091a8:	4b0e      	ldr	r3, [pc, #56]	@ (80091e4 <vPortFree+0xbc>)
 80091aa:	681b      	ldr	r3, [r3, #0]
 80091ac:	43db      	mvns	r3, r3
 80091ae:	401a      	ands	r2, r3
 80091b0:	693b      	ldr	r3, [r7, #16]
 80091b2:	605a      	str	r2, [r3, #4]

				vTaskSuspendAll();
 80091b4:	f7fe fb66 	bl	8007884 <vTaskSuspendAll>
				{
					/* Add this block to the list of free blocks. */
					xFreeBytesRemaining += pxLink->xBlockSize;
 80091b8:	693b      	ldr	r3, [r7, #16]
 80091ba:	685a      	ldr	r2, [r3, #4]
 80091bc:	4b0a      	ldr	r3, [pc, #40]	@ (80091e8 <vPortFree+0xc0>)
 80091be:	681b      	ldr	r3, [r3, #0]
 80091c0:	4413      	add	r3, r2
 80091c2:	4a09      	ldr	r2, [pc, #36]	@ (80091e8 <vPortFree+0xc0>)
 80091c4:	6013      	str	r3, [r2, #0]
					traceFREE( pv, pxLink->xBlockSize );
					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
 80091c6:	6938      	ldr	r0, [r7, #16]
 80091c8:	f000 f874 	bl	80092b4 <prvInsertBlockIntoFreeList>
					xNumberOfSuccessfulFrees++;
 80091cc:	4b07      	ldr	r3, [pc, #28]	@ (80091ec <vPortFree+0xc4>)
 80091ce:	681b      	ldr	r3, [r3, #0]
 80091d0:	3301      	adds	r3, #1
 80091d2:	4a06      	ldr	r2, [pc, #24]	@ (80091ec <vPortFree+0xc4>)
 80091d4:	6013      	str	r3, [r2, #0]
				}
				( void ) xTaskResumeAll();
 80091d6:	f7fe fb63 	bl	80078a0 <xTaskResumeAll>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
}
 80091da:	bf00      	nop
 80091dc:	3718      	adds	r7, #24
 80091de:	46bd      	mov	sp, r7
 80091e0:	bd80      	pop	{r7, pc}
 80091e2:	bf00      	nop
 80091e4:	20008b50 	.word	0x20008b50
 80091e8:	20008b40 	.word	0x20008b40
 80091ec:	20008b4c 	.word	0x20008b4c

080091f0 <prvHeapInit>:
	/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/

static void prvHeapInit( void )
{
 80091f0:	b480      	push	{r7}
 80091f2:	b085      	sub	sp, #20
 80091f4:	af00      	add	r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
 80091f6:	f247 5330 	movw	r3, #30000	@ 0x7530
 80091fa:	60bb      	str	r3, [r7, #8]

	/* Ensure the heap starts on a correctly aligned boundary. */
	uxAddress = ( size_t ) ucHeap;
 80091fc:	4b27      	ldr	r3, [pc, #156]	@ (800929c <prvHeapInit+0xac>)
 80091fe:	60fb      	str	r3, [r7, #12]

	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
 8009200:	68fb      	ldr	r3, [r7, #12]
 8009202:	f003 0307 	and.w	r3, r3, #7
 8009206:	2b00      	cmp	r3, #0
 8009208:	d00c      	beq.n	8009224 <prvHeapInit+0x34>
	{
		uxAddress += ( portBYTE_ALIGNMENT - 1 );
 800920a:	68fb      	ldr	r3, [r7, #12]
 800920c:	3307      	adds	r3, #7
 800920e:	60fb      	str	r3, [r7, #12]
		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8009210:	68fb      	ldr	r3, [r7, #12]
 8009212:	f023 0307 	bic.w	r3, r3, #7
 8009216:	60fb      	str	r3, [r7, #12]
		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
 8009218:	68ba      	ldr	r2, [r7, #8]
 800921a:	68fb      	ldr	r3, [r7, #12]
 800921c:	1ad3      	subs	r3, r2, r3
 800921e:	4a1f      	ldr	r2, [pc, #124]	@ (800929c <prvHeapInit+0xac>)
 8009220:	4413      	add	r3, r2
 8009222:	60bb      	str	r3, [r7, #8]
	}

	pucAlignedHeap = ( uint8_t * ) uxAddress;
 8009224:	68fb      	ldr	r3, [r7, #12]
 8009226:	607b      	str	r3, [r7, #4]

	/* xStart is used to hold a pointer to the first item in the list of free
	blocks.  The void cast is used to prevent compiler warnings. */
	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
 8009228:	4a1d      	ldr	r2, [pc, #116]	@ (80092a0 <prvHeapInit+0xb0>)
 800922a:	687b      	ldr	r3, [r7, #4]
 800922c:	6013      	str	r3, [r2, #0]
	xStart.xBlockSize = ( size_t ) 0;
 800922e:	4b1c      	ldr	r3, [pc, #112]	@ (80092a0 <prvHeapInit+0xb0>)
 8009230:	2200      	movs	r2, #0
 8009232:	605a      	str	r2, [r3, #4]

	/* pxEnd is used to mark the end of the list of free blocks and is inserted
	at the end of the heap space. */
	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
 8009234:	687b      	ldr	r3, [r7, #4]
 8009236:	68ba      	ldr	r2, [r7, #8]
 8009238:	4413      	add	r3, r2
 800923a:	60fb      	str	r3, [r7, #12]
	uxAddress -= xHeapStructSize;
 800923c:	2208      	movs	r2, #8
 800923e:	68fb      	ldr	r3, [r7, #12]
 8009240:	1a9b      	subs	r3, r3, r2
 8009242:	60fb      	str	r3, [r7, #12]
	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8009244:	68fb      	ldr	r3, [r7, #12]
 8009246:	f023 0307 	bic.w	r3, r3, #7
 800924a:	60fb      	str	r3, [r7, #12]
	pxEnd = ( void * ) uxAddress;
 800924c:	68fb      	ldr	r3, [r7, #12]
 800924e:	4a15      	ldr	r2, [pc, #84]	@ (80092a4 <prvHeapInit+0xb4>)
 8009250:	6013      	str	r3, [r2, #0]
	pxEnd->xBlockSize = 0;
 8009252:	4b14      	ldr	r3, [pc, #80]	@ (80092a4 <prvHeapInit+0xb4>)
 8009254:	681b      	ldr	r3, [r3, #0]
 8009256:	2200      	movs	r2, #0
 8009258:	605a      	str	r2, [r3, #4]
	pxEnd->pxNextFreeBlock = NULL;
 800925a:	4b12      	ldr	r3, [pc, #72]	@ (80092a4 <prvHeapInit+0xb4>)
 800925c:	681b      	ldr	r3, [r3, #0]
 800925e:	2200      	movs	r2, #0
 8009260:	601a      	str	r2, [r3, #0]

	/* To start with there is a single free block that is sized to take up the
	entire heap space, minus the space taken by pxEnd. */
	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
 8009262:	687b      	ldr	r3, [r7, #4]
 8009264:	603b      	str	r3, [r7, #0]
	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
 8009266:	683b      	ldr	r3, [r7, #0]
 8009268:	68fa      	ldr	r2, [r7, #12]
 800926a:	1ad2      	subs	r2, r2, r3
 800926c:	683b      	ldr	r3, [r7, #0]
 800926e:	605a      	str	r2, [r3, #4]
	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
 8009270:	4b0c      	ldr	r3, [pc, #48]	@ (80092a4 <prvHeapInit+0xb4>)
 8009272:	681a      	ldr	r2, [r3, #0]
 8009274:	683b      	ldr	r3, [r7, #0]
 8009276:	601a      	str	r2, [r3, #0]

	/* Only one block exists - and it covers the entire usable heap space. */
	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 8009278:	683b      	ldr	r3, [r7, #0]
 800927a:	685b      	ldr	r3, [r3, #4]
 800927c:	4a0a      	ldr	r2, [pc, #40]	@ (80092a8 <prvHeapInit+0xb8>)
 800927e:	6013      	str	r3, [r2, #0]
	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 8009280:	683b      	ldr	r3, [r7, #0]
 8009282:	685b      	ldr	r3, [r3, #4]
 8009284:	4a09      	ldr	r2, [pc, #36]	@ (80092ac <prvHeapInit+0xbc>)
 8009286:	6013      	str	r3, [r2, #0]

	/* Work out the position of the top bit in a size_t variable. */
	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
 8009288:	4b09      	ldr	r3, [pc, #36]	@ (80092b0 <prvHeapInit+0xc0>)
 800928a:	f04f 4200 	mov.w	r2, #2147483648	@ 0x80000000
 800928e:	601a      	str	r2, [r3, #0]
}
 8009290:	bf00      	nop
 8009292:	3714      	adds	r7, #20
 8009294:	46bd      	mov	sp, r7
 8009296:	f85d 7b04 	ldr.w	r7, [sp], #4
 800929a:	4770      	bx	lr
 800929c:	20001604 	.word	0x20001604
 80092a0:	20008b34 	.word	0x20008b34
 80092a4:	20008b3c 	.word	0x20008b3c
 80092a8:	20008b44 	.word	0x20008b44
 80092ac:	20008b40 	.word	0x20008b40
 80092b0:	20008b50 	.word	0x20008b50

080092b4 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/

static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
 80092b4:	b480      	push	{r7}
 80092b6:	b085      	sub	sp, #20
 80092b8:	af00      	add	r7, sp, #0
 80092ba:	6078      	str	r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;

	/* Iterate through the list until a block is found that has a higher address
	than the block being inserted. */
	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
 80092bc:	4b28      	ldr	r3, [pc, #160]	@ (8009360 <prvInsertBlockIntoFreeList+0xac>)
 80092be:	60fb      	str	r3, [r7, #12]
 80092c0:	e002      	b.n	80092c8 <prvInsertBlockIntoFreeList+0x14>
 80092c2:	68fb      	ldr	r3, [r7, #12]
 80092c4:	681b      	ldr	r3, [r3, #0]
 80092c6:	60fb      	str	r3, [r7, #12]
 80092c8:	68fb      	ldr	r3, [r7, #12]
 80092ca:	681b      	ldr	r3, [r3, #0]
 80092cc:	687a      	ldr	r2, [r7, #4]
 80092ce:	429a      	cmp	r2, r3
 80092d0:	d8f7      	bhi.n	80092c2 <prvInsertBlockIntoFreeList+0xe>
		/* Nothing to do here, just iterate to the right position. */
	}

	/* Do the block being inserted, and the block it is being inserted after
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxIterator;
 80092d2:	68fb      	ldr	r3, [r7, #12]
 80092d4:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
 80092d6:	68fb      	ldr	r3, [r7, #12]
 80092d8:	685b      	ldr	r3, [r3, #4]
 80092da:	68ba      	ldr	r2, [r7, #8]
 80092dc:	4413      	add	r3, r2
 80092de:	687a      	ldr	r2, [r7, #4]
 80092e0:	429a      	cmp	r2, r3
 80092e2:	d108      	bne.n	80092f6 <prvInsertBlockIntoFreeList+0x42>
	{
		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
 80092e4:	68fb      	ldr	r3, [r7, #12]
 80092e6:	685a      	ldr	r2, [r3, #4]
 80092e8:	687b      	ldr	r3, [r7, #4]
 80092ea:	685b      	ldr	r3, [r3, #4]
 80092ec:	441a      	add	r2, r3
 80092ee:	68fb      	ldr	r3, [r7, #12]
 80092f0:	605a      	str	r2, [r3, #4]
		pxBlockToInsert = pxIterator;
 80092f2:	68fb      	ldr	r3, [r7, #12]
 80092f4:	607b      	str	r3, [r7, #4]
		mtCOVERAGE_TEST_MARKER();
	}

	/* Do the block being inserted, and the block it is being inserted before
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxBlockToInsert;
 80092f6:	687b      	ldr	r3, [r7, #4]
 80092f8:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
 80092fa:	687b      	ldr	r3, [r7, #4]
 80092fc:	685b      	ldr	r3, [r3, #4]
 80092fe:	68ba      	ldr	r2, [r7, #8]
 8009300:	441a      	add	r2, r3
 8009302:	68fb      	ldr	r3, [r7, #12]
 8009304:	681b      	ldr	r3, [r3, #0]
 8009306:	429a      	cmp	r2, r3
 8009308:	d118      	bne.n	800933c <prvInsertBlockIntoFreeList+0x88>
	{
		if( pxIterator->pxNextFreeBlock != pxEnd )
 800930a:	68fb      	ldr	r3, [r7, #12]
 800930c:	681a      	ldr	r2, [r3, #0]
 800930e:	4b15      	ldr	r3, [pc, #84]	@ (8009364 <prvInsertBlockIntoFreeList+0xb0>)
 8009310:	681b      	ldr	r3, [r3, #0]
 8009312:	429a      	cmp	r2, r3
 8009314:	d00d      	beq.n	8009332 <prvInsertBlockIntoFreeList+0x7e>
		{
			/* Form one big block from the two blocks. */
			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
 8009316:	687b      	ldr	r3, [r7, #4]
 8009318:	685a      	ldr	r2, [r3, #4]
 800931a:	68fb      	ldr	r3, [r7, #12]
 800931c:	681b      	ldr	r3, [r3, #0]
 800931e:	685b      	ldr	r3, [r3, #4]
 8009320:	441a      	add	r2, r3
 8009322:	687b      	ldr	r3, [r7, #4]
 8009324:	605a      	str	r2, [r3, #4]
			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
 8009326:	68fb      	ldr	r3, [r7, #12]
 8009328:	681b      	ldr	r3, [r3, #0]
 800932a:	681a      	ldr	r2, [r3, #0]
 800932c:	687b      	ldr	r3, [r7, #4]
 800932e:	601a      	str	r2, [r3, #0]
 8009330:	e008      	b.n	8009344 <prvInsertBlockIntoFreeList+0x90>
		}
		else
		{
			pxBlockToInsert->pxNextFreeBlock = pxEnd;
 8009332:	4b0c      	ldr	r3, [pc, #48]	@ (8009364 <prvInsertBlockIntoFreeList+0xb0>)
 8009334:	681a      	ldr	r2, [r3, #0]
 8009336:	687b      	ldr	r3, [r7, #4]
 8009338:	601a      	str	r2, [r3, #0]
 800933a:	e003      	b.n	8009344 <prvInsertBlockIntoFreeList+0x90>
		}
	}
	else
	{
		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
 800933c:	68fb      	ldr	r3, [r7, #12]
 800933e:	681a      	ldr	r2, [r3, #0]
 8009340:	687b      	ldr	r3, [r7, #4]
 8009342:	601a      	str	r2, [r3, #0]

	/* If the block being inserted plugged a gab, so was merged with the block
	before and the block after, then it's pxNextFreeBlock pointer will have
	already been set, and should not be set here as that would make it point
	to itself. */
	if( pxIterator != pxBlockToInsert )
 8009344:	68fa      	ldr	r2, [r7, #12]
 8009346:	687b      	ldr	r3, [r7, #4]
 8009348:	429a      	cmp	r2, r3
 800934a:	d002      	beq.n	8009352 <prvInsertBlockIntoFreeList+0x9e>
	{
		pxIterator->pxNextFreeBlock = pxBlockToInsert;
 800934c:	68fb      	ldr	r3, [r7, #12]
 800934e:	687a      	ldr	r2, [r7, #4]
 8009350:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8009352:	bf00      	nop
 8009354:	3714      	adds	r7, #20
 8009356:	46bd      	mov	sp, r7
 8009358:	f85d 7b04 	ldr.w	r7, [sp], #4
 800935c:	4770      	bx	lr
 800935e:	bf00      	nop
 8009360:	20008b34 	.word	0x20008b34
 8009364:	20008b3c 	.word	0x20008b3c

08009368 <memset>:
 8009368:	4402      	add	r2, r0
 800936a:	4603      	mov	r3, r0
 800936c:	4293      	cmp	r3, r2
 800936e:	d100      	bne.n	8009372 <memset+0xa>
 8009370:	4770      	bx	lr
 8009372:	f803 1b01 	strb.w	r1, [r3], #1
 8009376:	e7f9      	b.n	800936c <memset+0x4>

08009378 <_reclaim_reent>:
 8009378:	4b2d      	ldr	r3, [pc, #180]	@ (8009430 <_reclaim_reent+0xb8>)
 800937a:	681b      	ldr	r3, [r3, #0]
 800937c:	4283      	cmp	r3, r0
 800937e:	b570      	push	{r4, r5, r6, lr}
 8009380:	4604      	mov	r4, r0
 8009382:	d053      	beq.n	800942c <_reclaim_reent+0xb4>
 8009384:	69c3      	ldr	r3, [r0, #28]
 8009386:	b31b      	cbz	r3, 80093d0 <_reclaim_reent+0x58>
 8009388:	68db      	ldr	r3, [r3, #12]
 800938a:	b163      	cbz	r3, 80093a6 <_reclaim_reent+0x2e>
 800938c:	2500      	movs	r5, #0
 800938e:	69e3      	ldr	r3, [r4, #28]
 8009390:	68db      	ldr	r3, [r3, #12]
 8009392:	5959      	ldr	r1, [r3, r5]
 8009394:	b9b1      	cbnz	r1, 80093c4 <_reclaim_reent+0x4c>
 8009396:	3504      	adds	r5, #4
 8009398:	2d80      	cmp	r5, #128	@ 0x80
 800939a:	d1f8      	bne.n	800938e <_reclaim_reent+0x16>
 800939c:	69e3      	ldr	r3, [r4, #28]
 800939e:	4620      	mov	r0, r4
 80093a0:	68d9      	ldr	r1, [r3, #12]
 80093a2:	f000 f87b 	bl	800949c <_free_r>
 80093a6:	69e3      	ldr	r3, [r4, #28]
 80093a8:	6819      	ldr	r1, [r3, #0]
 80093aa:	b111      	cbz	r1, 80093b2 <_reclaim_reent+0x3a>
 80093ac:	4620      	mov	r0, r4
 80093ae:	f000 f875 	bl	800949c <_free_r>
 80093b2:	69e3      	ldr	r3, [r4, #28]
 80093b4:	689d      	ldr	r5, [r3, #8]
 80093b6:	b15d      	cbz	r5, 80093d0 <_reclaim_reent+0x58>
 80093b8:	4629      	mov	r1, r5
 80093ba:	4620      	mov	r0, r4
 80093bc:	682d      	ldr	r5, [r5, #0]
 80093be:	f000 f86d 	bl	800949c <_free_r>
 80093c2:	e7f8      	b.n	80093b6 <_reclaim_reent+0x3e>
 80093c4:	680e      	ldr	r6, [r1, #0]
 80093c6:	4620      	mov	r0, r4
 80093c8:	f000 f868 	bl	800949c <_free_r>
 80093cc:	4631      	mov	r1, r6
 80093ce:	e7e1      	b.n	8009394 <_reclaim_reent+0x1c>
 80093d0:	6961      	ldr	r1, [r4, #20]
 80093d2:	b111      	cbz	r1, 80093da <_reclaim_reent+0x62>
 80093d4:	4620      	mov	r0, r4
 80093d6:	f000 f861 	bl	800949c <_free_r>
 80093da:	69e1      	ldr	r1, [r4, #28]
 80093dc:	b111      	cbz	r1, 80093e4 <_reclaim_reent+0x6c>
 80093de:	4620      	mov	r0, r4
 80093e0:	f000 f85c 	bl	800949c <_free_r>
 80093e4:	6b21      	ldr	r1, [r4, #48]	@ 0x30
 80093e6:	b111      	cbz	r1, 80093ee <_reclaim_reent+0x76>
 80093e8:	4620      	mov	r0, r4
 80093ea:	f000 f857 	bl	800949c <_free_r>
 80093ee:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 80093f0:	b111      	cbz	r1, 80093f8 <_reclaim_reent+0x80>
 80093f2:	4620      	mov	r0, r4
 80093f4:	f000 f852 	bl	800949c <_free_r>
 80093f8:	6ba1      	ldr	r1, [r4, #56]	@ 0x38
 80093fa:	b111      	cbz	r1, 8009402 <_reclaim_reent+0x8a>
 80093fc:	4620      	mov	r0, r4
 80093fe:	f000 f84d 	bl	800949c <_free_r>
 8009402:	6ca1      	ldr	r1, [r4, #72]	@ 0x48
 8009404:	b111      	cbz	r1, 800940c <_reclaim_reent+0x94>
 8009406:	4620      	mov	r0, r4
 8009408:	f000 f848 	bl	800949c <_free_r>
 800940c:	6c61      	ldr	r1, [r4, #68]	@ 0x44
 800940e:	b111      	cbz	r1, 8009416 <_reclaim_reent+0x9e>
 8009410:	4620      	mov	r0, r4
 8009412:	f000 f843 	bl	800949c <_free_r>
 8009416:	6ae1      	ldr	r1, [r4, #44]	@ 0x2c
 8009418:	b111      	cbz	r1, 8009420 <_reclaim_reent+0xa8>
 800941a:	4620      	mov	r0, r4
 800941c:	f000 f83e 	bl	800949c <_free_r>
 8009420:	6a23      	ldr	r3, [r4, #32]
 8009422:	b11b      	cbz	r3, 800942c <_reclaim_reent+0xb4>
 8009424:	4620      	mov	r0, r4
 8009426:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
 800942a:	4718      	bx	r3
 800942c:	bd70      	pop	{r4, r5, r6, pc}
 800942e:	bf00      	nop
 8009430:	20000010 	.word	0x20000010

08009434 <__libc_init_array>:
 8009434:	b570      	push	{r4, r5, r6, lr}
 8009436:	4d0d      	ldr	r5, [pc, #52]	@ (800946c <__libc_init_array+0x38>)
 8009438:	4c0d      	ldr	r4, [pc, #52]	@ (8009470 <__libc_init_array+0x3c>)
 800943a:	1b64      	subs	r4, r4, r5
 800943c:	10a4      	asrs	r4, r4, #2
 800943e:	2600      	movs	r6, #0
 8009440:	42a6      	cmp	r6, r4
 8009442:	d109      	bne.n	8009458 <__libc_init_array+0x24>
 8009444:	4d0b      	ldr	r5, [pc, #44]	@ (8009474 <__libc_init_array+0x40>)
 8009446:	4c0c      	ldr	r4, [pc, #48]	@ (8009478 <__libc_init_array+0x44>)
 8009448:	f000 f87e 	bl	8009548 <_init>
 800944c:	1b64      	subs	r4, r4, r5
 800944e:	10a4      	asrs	r4, r4, #2
 8009450:	2600      	movs	r6, #0
 8009452:	42a6      	cmp	r6, r4
 8009454:	d105      	bne.n	8009462 <__libc_init_array+0x2e>
 8009456:	bd70      	pop	{r4, r5, r6, pc}
 8009458:	f855 3b04 	ldr.w	r3, [r5], #4
 800945c:	4798      	blx	r3
 800945e:	3601      	adds	r6, #1
 8009460:	e7ee      	b.n	8009440 <__libc_init_array+0xc>
 8009462:	f855 3b04 	ldr.w	r3, [r5], #4
 8009466:	4798      	blx	r3
 8009468:	3601      	adds	r6, #1
 800946a:	e7f2      	b.n	8009452 <__libc_init_array+0x1e>
 800946c:	08009618 	.word	0x08009618
 8009470:	08009618 	.word	0x08009618
 8009474:	08009618 	.word	0x08009618
 8009478:	0800961c 	.word	0x0800961c

0800947c <__retarget_lock_acquire_recursive>:
 800947c:	4770      	bx	lr

0800947e <__retarget_lock_release_recursive>:
 800947e:	4770      	bx	lr

08009480 <memcpy>:
 8009480:	440a      	add	r2, r1
 8009482:	4291      	cmp	r1, r2
 8009484:	f100 33ff 	add.w	r3, r0, #4294967295	@ 0xffffffff
 8009488:	d100      	bne.n	800948c <memcpy+0xc>
 800948a:	4770      	bx	lr
 800948c:	b510      	push	{r4, lr}
 800948e:	f811 4b01 	ldrb.w	r4, [r1], #1
 8009492:	f803 4f01 	strb.w	r4, [r3, #1]!
 8009496:	4291      	cmp	r1, r2
 8009498:	d1f9      	bne.n	800948e <memcpy+0xe>
 800949a:	bd10      	pop	{r4, pc}

0800949c <_free_r>:
 800949c:	b538      	push	{r3, r4, r5, lr}
 800949e:	4605      	mov	r5, r0
 80094a0:	2900      	cmp	r1, #0
 80094a2:	d041      	beq.n	8009528 <_free_r+0x8c>
 80094a4:	f851 3c04 	ldr.w	r3, [r1, #-4]
 80094a8:	1f0c      	subs	r4, r1, #4
 80094aa:	2b00      	cmp	r3, #0
 80094ac:	bfb8      	it	lt
 80094ae:	18e4      	addlt	r4, r4, r3
 80094b0:	f000 f83e 	bl	8009530 <__malloc_lock>
 80094b4:	4a1d      	ldr	r2, [pc, #116]	@ (800952c <_free_r+0x90>)
 80094b6:	6813      	ldr	r3, [r2, #0]
 80094b8:	b933      	cbnz	r3, 80094c8 <_free_r+0x2c>
 80094ba:	6063      	str	r3, [r4, #4]
 80094bc:	6014      	str	r4, [r2, #0]
 80094be:	4628      	mov	r0, r5
 80094c0:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 80094c4:	f000 b83a 	b.w	800953c <__malloc_unlock>
 80094c8:	42a3      	cmp	r3, r4
 80094ca:	d908      	bls.n	80094de <_free_r+0x42>
 80094cc:	6820      	ldr	r0, [r4, #0]
 80094ce:	1821      	adds	r1, r4, r0
 80094d0:	428b      	cmp	r3, r1
 80094d2:	bf01      	itttt	eq
 80094d4:	6819      	ldreq	r1, [r3, #0]
 80094d6:	685b      	ldreq	r3, [r3, #4]
 80094d8:	1809      	addeq	r1, r1, r0
 80094da:	6021      	streq	r1, [r4, #0]
 80094dc:	e7ed      	b.n	80094ba <_free_r+0x1e>
 80094de:	461a      	mov	r2, r3
 80094e0:	685b      	ldr	r3, [r3, #4]
 80094e2:	b10b      	cbz	r3, 80094e8 <_free_r+0x4c>
 80094e4:	42a3      	cmp	r3, r4
 80094e6:	d9fa      	bls.n	80094de <_free_r+0x42>
 80094e8:	6811      	ldr	r1, [r2, #0]
 80094ea:	1850      	adds	r0, r2, r1
 80094ec:	42a0      	cmp	r0, r4
 80094ee:	d10b      	bne.n	8009508 <_free_r+0x6c>
 80094f0:	6820      	ldr	r0, [r4, #0]
 80094f2:	4401      	add	r1, r0
 80094f4:	1850      	adds	r0, r2, r1
 80094f6:	4283      	cmp	r3, r0
 80094f8:	6011      	str	r1, [r2, #0]
 80094fa:	d1e0      	bne.n	80094be <_free_r+0x22>
 80094fc:	6818      	ldr	r0, [r3, #0]
 80094fe:	685b      	ldr	r3, [r3, #4]
 8009500:	6053      	str	r3, [r2, #4]
 8009502:	4408      	add	r0, r1
 8009504:	6010      	str	r0, [r2, #0]
 8009506:	e7da      	b.n	80094be <_free_r+0x22>
 8009508:	d902      	bls.n	8009510 <_free_r+0x74>
 800950a:	230c      	movs	r3, #12
 800950c:	602b      	str	r3, [r5, #0]
 800950e:	e7d6      	b.n	80094be <_free_r+0x22>
 8009510:	6820      	ldr	r0, [r4, #0]
 8009512:	1821      	adds	r1, r4, r0
 8009514:	428b      	cmp	r3, r1
 8009516:	bf04      	itt	eq
 8009518:	6819      	ldreq	r1, [r3, #0]
 800951a:	685b      	ldreq	r3, [r3, #4]
 800951c:	6063      	str	r3, [r4, #4]
 800951e:	bf04      	itt	eq
 8009520:	1809      	addeq	r1, r1, r0
 8009522:	6021      	streq	r1, [r4, #0]
 8009524:	6054      	str	r4, [r2, #4]
 8009526:	e7ca      	b.n	80094be <_free_r+0x22>
 8009528:	bd38      	pop	{r3, r4, r5, pc}
 800952a:	bf00      	nop
 800952c:	20008c90 	.word	0x20008c90

08009530 <__malloc_lock>:
 8009530:	4801      	ldr	r0, [pc, #4]	@ (8009538 <__malloc_lock+0x8>)
 8009532:	f7ff bfa3 	b.w	800947c <__retarget_lock_acquire_recursive>
 8009536:	bf00      	nop
 8009538:	20008c8c 	.word	0x20008c8c

0800953c <__malloc_unlock>:
 800953c:	4801      	ldr	r0, [pc, #4]	@ (8009544 <__malloc_unlock+0x8>)
 800953e:	f7ff bf9e 	b.w	800947e <__retarget_lock_release_recursive>
 8009542:	bf00      	nop
 8009544:	20008c8c 	.word	0x20008c8c

08009548 <_init>:
 8009548:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800954a:	bf00      	nop
 800954c:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800954e:	bc08      	pop	{r3}
 8009550:	469e      	mov	lr, r3
 8009552:	4770      	bx	lr

08009554 <_fini>:
 8009554:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8009556:	bf00      	nop
 8009558:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800955a:	bc08      	pop	{r3}
 800955c:	469e      	mov	lr, r3
 800955e:	4770      	bx	lr
