Gallardo7761/setr1-monorepo
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85e60bcc395d54bac7c45fdfeb66aee5b9aa7fed
setr1-monorepo/P7_SETR1/Debug/P7_MIDI_SETR1.list
Jose 85e60bcc39 monorepo
2025-10-10 02:20:31 +02:00

35246 lines
1.3 MiB
Executable File
Raw Blame History

P7_MIDI_SETR1.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000dfe0 08000190 08000190 00001190 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000040c 0800e170 0800e170 0000f170 2**3
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800e57c 0800e57c 00010300 2**0
CONTENTS, READONLY
4 .ARM 00000008 0800e57c 0800e57c 0000f57c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800e584 0800e584 00010300 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800e584 0800e584 0000f584 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800e588 0800e588 0000f588 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000300 20000000 0800e58c 00010000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000ef0 20000300 0800e88c 00010300 2**2
ALLOC
10 ._user_heap_stack 00000600 200011f0 0800e88c 000111f0 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00010300 2**0
CONTENTS, READONLY
12 .debug_info 000279a5 00000000 00000000 00010330 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00005119 00000000 00000000 00037cd5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00002440 00000000 00000000 0003cdf0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00001c1d 00000000 00000000 0003f230 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0002f325 00000000 00000000 00040e4d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0002bbef 00000000 00000000 00070172 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0011625a 00000000 00000000 0009bd61 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 001b1fbb 2**0
CONTENTS, READONLY
20 .debug_frame 0000ac68 00000000 00000000 001b2000 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000069 00000000 00000000 001bcc68 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000190 <__do_global_dtors_aux>:
8000190: b510 push {r4, lr}
8000192: 4c05 ldr r4, [pc, #20] @ (80001a8 <__do_global_dtors_aux+0x18>)
8000194: 7823 ldrb r3, [r4, #0]
8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16>
8000198: 4b04 ldr r3, [pc, #16] @ (80001ac <__do_global_dtors_aux+0x1c>)
800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12>
800019c: 4804 ldr r0, [pc, #16] @ (80001b0 <__do_global_dtors_aux+0x20>)
800019e: f3af 8000 nop.w
80001a2: 2301 movs r3, #1
80001a4: 7023 strb r3, [r4, #0]
80001a6: bd10 pop {r4, pc}
80001a8: 20000300 .word 0x20000300
80001ac: 00000000 .word 0x00000000
80001b0: 0800e158 .word 0x0800e158
080001b4 <frame_dummy>:
80001b4: b508 push {r3, lr}
80001b6: 4b03 ldr r3, [pc, #12] @ (80001c4 <frame_dummy+0x10>)
80001b8: b11b cbz r3, 80001c2 <frame_dummy+0xe>
80001ba: 4903 ldr r1, [pc, #12] @ (80001c8 <frame_dummy+0x14>)
80001bc: 4803 ldr r0, [pc, #12] @ (80001cc <frame_dummy+0x18>)
80001be: f3af 8000 nop.w
80001c2: bd08 pop {r3, pc}
80001c4: 00000000 .word 0x00000000
80001c8: 20000304 .word 0x20000304
80001cc: 0800e158 .word 0x0800e158
080001d0 <memchr>:
80001d0: f001 01ff and.w r1, r1, #255 @ 0xff
80001d4: 2a10 cmp r2, #16
80001d6: db2b blt.n 8000230 <memchr+0x60>
80001d8: f010 0f07 tst.w r0, #7
80001dc: d008 beq.n 80001f0 <memchr+0x20>
80001de: f810 3b01 ldrb.w r3, [r0], #1
80001e2: 3a01 subs r2, #1
80001e4: 428b cmp r3, r1
80001e6: d02d beq.n 8000244 <memchr+0x74>
80001e8: f010 0f07 tst.w r0, #7
80001ec: b342 cbz r2, 8000240 <memchr+0x70>
80001ee: d1f6 bne.n 80001de <memchr+0xe>
80001f0: b4f0 push {r4, r5, r6, r7}
80001f2: ea41 2101 orr.w r1, r1, r1, lsl #8
80001f6: ea41 4101 orr.w r1, r1, r1, lsl #16
80001fa: f022 0407 bic.w r4, r2, #7
80001fe: f07f 0700 mvns.w r7, #0
8000202: 2300 movs r3, #0
8000204: e8f0 5602 ldrd r5, r6, [r0], #8
8000208: 3c08 subs r4, #8
800020a: ea85 0501 eor.w r5, r5, r1
800020e: ea86 0601 eor.w r6, r6, r1
8000212: fa85 f547 uadd8 r5, r5, r7
8000216: faa3 f587 sel r5, r3, r7
800021a: fa86 f647 uadd8 r6, r6, r7
800021e: faa5 f687 sel r6, r5, r7
8000222: b98e cbnz r6, 8000248 <memchr+0x78>
8000224: d1ee bne.n 8000204 <memchr+0x34>
8000226: bcf0 pop {r4, r5, r6, r7}
8000228: f001 01ff and.w r1, r1, #255 @ 0xff
800022c: f002 0207 and.w r2, r2, #7
8000230: b132 cbz r2, 8000240 <memchr+0x70>
8000232: f810 3b01 ldrb.w r3, [r0], #1
8000236: 3a01 subs r2, #1
8000238: ea83 0301 eor.w r3, r3, r1
800023c: b113 cbz r3, 8000244 <memchr+0x74>
800023e: d1f8 bne.n 8000232 <memchr+0x62>
8000240: 2000 movs r0, #0
8000242: 4770 bx lr
8000244: 3801 subs r0, #1
8000246: 4770 bx lr
8000248: 2d00 cmp r5, #0
800024a: bf06 itte eq
800024c: 4635 moveq r5, r6
800024e: 3803 subeq r0, #3
8000250: 3807 subne r0, #7
8000252: f015 0f01 tst.w r5, #1
8000256: d107 bne.n 8000268 <memchr+0x98>
8000258: 3001 adds r0, #1
800025a: f415 7f80 tst.w r5, #256 @ 0x100
800025e: bf02 ittt eq
8000260: 3001 addeq r0, #1
8000262: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
8000266: 3001 addeq r0, #1
8000268: bcf0 pop {r4, r5, r6, r7}
800026a: 3801 subs r0, #1
800026c: 4770 bx lr
800026e: bf00 nop
08000270 <strlen>:
8000270: 4603 mov r3, r0
8000272: f813 2b01 ldrb.w r2, [r3], #1
8000276: 2a00 cmp r2, #0
8000278: d1fb bne.n 8000272 <strlen+0x2>
800027a: 1a18 subs r0, r3, r0
800027c: 3801 subs r0, #1
800027e: 4770 bx lr
08000280 <__aeabi_drsub>:
8000280: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
8000284: e002 b.n 800028c <__adddf3>
8000286: bf00 nop
08000288 <__aeabi_dsub>:
8000288: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
0800028c <__adddf3>:
800028c: b530 push {r4, r5, lr}
800028e: ea4f 0441 mov.w r4, r1, lsl #1
8000292: ea4f 0543 mov.w r5, r3, lsl #1
8000296: ea94 0f05 teq r4, r5
800029a: bf08 it eq
800029c: ea90 0f02 teqeq r0, r2
80002a0: bf1f itttt ne
80002a2: ea54 0c00 orrsne.w ip, r4, r0
80002a6: ea55 0c02 orrsne.w ip, r5, r2
80002aa: ea7f 5c64 mvnsne.w ip, r4, asr #21
80002ae: ea7f 5c65 mvnsne.w ip, r5, asr #21
80002b2: f000 80e2 beq.w 800047a <__adddf3+0x1ee>
80002b6: ea4f 5454 mov.w r4, r4, lsr #21
80002ba: ebd4 5555 rsbs r5, r4, r5, lsr #21
80002be: bfb8 it lt
80002c0: 426d neglt r5, r5
80002c2: dd0c ble.n 80002de <__adddf3+0x52>
80002c4: 442c add r4, r5
80002c6: ea80 0202 eor.w r2, r0, r2
80002ca: ea81 0303 eor.w r3, r1, r3
80002ce: ea82 0000 eor.w r0, r2, r0
80002d2: ea83 0101 eor.w r1, r3, r1
80002d6: ea80 0202 eor.w r2, r0, r2
80002da: ea81 0303 eor.w r3, r1, r3
80002de: 2d36 cmp r5, #54 @ 0x36
80002e0: bf88 it hi
80002e2: bd30 pophi {r4, r5, pc}
80002e4: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80002e8: ea4f 3101 mov.w r1, r1, lsl #12
80002ec: f44f 1c80 mov.w ip, #1048576 @ 0x100000
80002f0: ea4c 3111 orr.w r1, ip, r1, lsr #12
80002f4: d002 beq.n 80002fc <__adddf3+0x70>
80002f6: 4240 negs r0, r0
80002f8: eb61 0141 sbc.w r1, r1, r1, lsl #1
80002fc: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
8000300: ea4f 3303 mov.w r3, r3, lsl #12
8000304: ea4c 3313 orr.w r3, ip, r3, lsr #12
8000308: d002 beq.n 8000310 <__adddf3+0x84>
800030a: 4252 negs r2, r2
800030c: eb63 0343 sbc.w r3, r3, r3, lsl #1
8000310: ea94 0f05 teq r4, r5
8000314: f000 80a7 beq.w 8000466 <__adddf3+0x1da>
8000318: f1a4 0401 sub.w r4, r4, #1
800031c: f1d5 0e20 rsbs lr, r5, #32
8000320: db0d blt.n 800033e <__adddf3+0xb2>
8000322: fa02 fc0e lsl.w ip, r2, lr
8000326: fa22 f205 lsr.w r2, r2, r5
800032a: 1880 adds r0, r0, r2
800032c: f141 0100 adc.w r1, r1, #0
8000330: fa03 f20e lsl.w r2, r3, lr
8000334: 1880 adds r0, r0, r2
8000336: fa43 f305 asr.w r3, r3, r5
800033a: 4159 adcs r1, r3
800033c: e00e b.n 800035c <__adddf3+0xd0>
800033e: f1a5 0520 sub.w r5, r5, #32
8000342: f10e 0e20 add.w lr, lr, #32
8000346: 2a01 cmp r2, #1
8000348: fa03 fc0e lsl.w ip, r3, lr
800034c: bf28 it cs
800034e: f04c 0c02 orrcs.w ip, ip, #2
8000352: fa43 f305 asr.w r3, r3, r5
8000356: 18c0 adds r0, r0, r3
8000358: eb51 71e3 adcs.w r1, r1, r3, asr #31
800035c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000360: d507 bpl.n 8000372 <__adddf3+0xe6>
8000362: f04f 0e00 mov.w lr, #0
8000366: f1dc 0c00 rsbs ip, ip, #0
800036a: eb7e 0000 sbcs.w r0, lr, r0
800036e: eb6e 0101 sbc.w r1, lr, r1
8000372: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
8000376: d31b bcc.n 80003b0 <__adddf3+0x124>
8000378: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
800037c: d30c bcc.n 8000398 <__adddf3+0x10c>
800037e: 0849 lsrs r1, r1, #1
8000380: ea5f 0030 movs.w r0, r0, rrx
8000384: ea4f 0c3c mov.w ip, ip, rrx
8000388: f104 0401 add.w r4, r4, #1
800038c: ea4f 5244 mov.w r2, r4, lsl #21
8000390: f512 0f80 cmn.w r2, #4194304 @ 0x400000
8000394: f080 809a bcs.w 80004cc <__adddf3+0x240>
8000398: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
800039c: bf08 it eq
800039e: ea5f 0c50 movseq.w ip, r0, lsr #1
80003a2: f150 0000 adcs.w r0, r0, #0
80003a6: eb41 5104 adc.w r1, r1, r4, lsl #20
80003aa: ea41 0105 orr.w r1, r1, r5
80003ae: bd30 pop {r4, r5, pc}
80003b0: ea5f 0c4c movs.w ip, ip, lsl #1
80003b4: 4140 adcs r0, r0
80003b6: eb41 0101 adc.w r1, r1, r1
80003ba: 3c01 subs r4, #1
80003bc: bf28 it cs
80003be: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80003c2: d2e9 bcs.n 8000398 <__adddf3+0x10c>
80003c4: f091 0f00 teq r1, #0
80003c8: bf04 itt eq
80003ca: 4601 moveq r1, r0
80003cc: 2000 moveq r0, #0
80003ce: fab1 f381 clz r3, r1
80003d2: bf08 it eq
80003d4: 3320 addeq r3, #32
80003d6: f1a3 030b sub.w r3, r3, #11
80003da: f1b3 0220 subs.w r2, r3, #32
80003de: da0c bge.n 80003fa <__adddf3+0x16e>
80003e0: 320c adds r2, #12
80003e2: dd08 ble.n 80003f6 <__adddf3+0x16a>
80003e4: f102 0c14 add.w ip, r2, #20
80003e8: f1c2 020c rsb r2, r2, #12
80003ec: fa01 f00c lsl.w r0, r1, ip
80003f0: fa21 f102 lsr.w r1, r1, r2
80003f4: e00c b.n 8000410 <__adddf3+0x184>
80003f6: f102 0214 add.w r2, r2, #20
80003fa: bfd8 it le
80003fc: f1c2 0c20 rsble ip, r2, #32
8000400: fa01 f102 lsl.w r1, r1, r2
8000404: fa20 fc0c lsr.w ip, r0, ip
8000408: bfdc itt le
800040a: ea41 010c orrle.w r1, r1, ip
800040e: 4090 lslle r0, r2
8000410: 1ae4 subs r4, r4, r3
8000412: bfa2 ittt ge
8000414: eb01 5104 addge.w r1, r1, r4, lsl #20
8000418: 4329 orrge r1, r5
800041a: bd30 popge {r4, r5, pc}
800041c: ea6f 0404 mvn.w r4, r4
8000420: 3c1f subs r4, #31
8000422: da1c bge.n 800045e <__adddf3+0x1d2>
8000424: 340c adds r4, #12
8000426: dc0e bgt.n 8000446 <__adddf3+0x1ba>
8000428: f104 0414 add.w r4, r4, #20
800042c: f1c4 0220 rsb r2, r4, #32
8000430: fa20 f004 lsr.w r0, r0, r4
8000434: fa01 f302 lsl.w r3, r1, r2
8000438: ea40 0003 orr.w r0, r0, r3
800043c: fa21 f304 lsr.w r3, r1, r4
8000440: ea45 0103 orr.w r1, r5, r3
8000444: bd30 pop {r4, r5, pc}
8000446: f1c4 040c rsb r4, r4, #12
800044a: f1c4 0220 rsb r2, r4, #32
800044e: fa20 f002 lsr.w r0, r0, r2
8000452: fa01 f304 lsl.w r3, r1, r4
8000456: ea40 0003 orr.w r0, r0, r3
800045a: 4629 mov r1, r5
800045c: bd30 pop {r4, r5, pc}
800045e: fa21 f004 lsr.w r0, r1, r4
8000462: 4629 mov r1, r5
8000464: bd30 pop {r4, r5, pc}
8000466: f094 0f00 teq r4, #0
800046a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800046e: bf06 itte eq
8000470: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
8000474: 3401 addeq r4, #1
8000476: 3d01 subne r5, #1
8000478: e74e b.n 8000318 <__adddf3+0x8c>
800047a: ea7f 5c64 mvns.w ip, r4, asr #21
800047e: bf18 it ne
8000480: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000484: d029 beq.n 80004da <__adddf3+0x24e>
8000486: ea94 0f05 teq r4, r5
800048a: bf08 it eq
800048c: ea90 0f02 teqeq r0, r2
8000490: d005 beq.n 800049e <__adddf3+0x212>
8000492: ea54 0c00 orrs.w ip, r4, r0
8000496: bf04 itt eq
8000498: 4619 moveq r1, r3
800049a: 4610 moveq r0, r2
800049c: bd30 pop {r4, r5, pc}
800049e: ea91 0f03 teq r1, r3
80004a2: bf1e ittt ne
80004a4: 2100 movne r1, #0
80004a6: 2000 movne r0, #0
80004a8: bd30 popne {r4, r5, pc}
80004aa: ea5f 5c54 movs.w ip, r4, lsr #21
80004ae: d105 bne.n 80004bc <__adddf3+0x230>
80004b0: 0040 lsls r0, r0, #1
80004b2: 4149 adcs r1, r1
80004b4: bf28 it cs
80004b6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80004ba: bd30 pop {r4, r5, pc}
80004bc: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80004c0: bf3c itt cc
80004c2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80004c6: bd30 popcc {r4, r5, pc}
80004c8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80004cc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
80004d0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80004d4: f04f 0000 mov.w r0, #0
80004d8: bd30 pop {r4, r5, pc}
80004da: ea7f 5c64 mvns.w ip, r4, asr #21
80004de: bf1a itte ne
80004e0: 4619 movne r1, r3
80004e2: 4610 movne r0, r2
80004e4: ea7f 5c65 mvnseq.w ip, r5, asr #21
80004e8: bf1c itt ne
80004ea: 460b movne r3, r1
80004ec: 4602 movne r2, r0
80004ee: ea50 3401 orrs.w r4, r0, r1, lsl #12
80004f2: bf06 itte eq
80004f4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
80004f8: ea91 0f03 teqeq r1, r3
80004fc: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
8000500: bd30 pop {r4, r5, pc}
8000502: bf00 nop
08000504 <__aeabi_ui2d>:
8000504: f090 0f00 teq r0, #0
8000508: bf04 itt eq
800050a: 2100 moveq r1, #0
800050c: 4770 bxeq lr
800050e: b530 push {r4, r5, lr}
8000510: f44f 6480 mov.w r4, #1024 @ 0x400
8000514: f104 0432 add.w r4, r4, #50 @ 0x32
8000518: f04f 0500 mov.w r5, #0
800051c: f04f 0100 mov.w r1, #0
8000520: e750 b.n 80003c4 <__adddf3+0x138>
8000522: bf00 nop
08000524 <__aeabi_i2d>:
8000524: f090 0f00 teq r0, #0
8000528: bf04 itt eq
800052a: 2100 moveq r1, #0
800052c: 4770 bxeq lr
800052e: b530 push {r4, r5, lr}
8000530: f44f 6480 mov.w r4, #1024 @ 0x400
8000534: f104 0432 add.w r4, r4, #50 @ 0x32
8000538: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
800053c: bf48 it mi
800053e: 4240 negmi r0, r0
8000540: f04f 0100 mov.w r1, #0
8000544: e73e b.n 80003c4 <__adddf3+0x138>
8000546: bf00 nop
08000548 <__aeabi_f2d>:
8000548: 0042 lsls r2, r0, #1
800054a: ea4f 01e2 mov.w r1, r2, asr #3
800054e: ea4f 0131 mov.w r1, r1, rrx
8000552: ea4f 7002 mov.w r0, r2, lsl #28
8000556: bf1f itttt ne
8000558: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
800055c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
8000560: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000564: 4770 bxne lr
8000566: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
800056a: bf08 it eq
800056c: 4770 bxeq lr
800056e: f093 4f7f teq r3, #4278190080 @ 0xff000000
8000572: bf04 itt eq
8000574: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
8000578: 4770 bxeq lr
800057a: b530 push {r4, r5, lr}
800057c: f44f 7460 mov.w r4, #896 @ 0x380
8000580: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000584: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000588: e71c b.n 80003c4 <__adddf3+0x138>
800058a: bf00 nop
0800058c <__aeabi_ul2d>:
800058c: ea50 0201 orrs.w r2, r0, r1
8000590: bf08 it eq
8000592: 4770 bxeq lr
8000594: b530 push {r4, r5, lr}
8000596: f04f 0500 mov.w r5, #0
800059a: e00a b.n 80005b2 <__aeabi_l2d+0x16>
0800059c <__aeabi_l2d>:
800059c: ea50 0201 orrs.w r2, r0, r1
80005a0: bf08 it eq
80005a2: 4770 bxeq lr
80005a4: b530 push {r4, r5, lr}
80005a6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
80005aa: d502 bpl.n 80005b2 <__aeabi_l2d+0x16>
80005ac: 4240 negs r0, r0
80005ae: eb61 0141 sbc.w r1, r1, r1, lsl #1
80005b2: f44f 6480 mov.w r4, #1024 @ 0x400
80005b6: f104 0432 add.w r4, r4, #50 @ 0x32
80005ba: ea5f 5c91 movs.w ip, r1, lsr #22
80005be: f43f aed8 beq.w 8000372 <__adddf3+0xe6>
80005c2: f04f 0203 mov.w r2, #3
80005c6: ea5f 0cdc movs.w ip, ip, lsr #3
80005ca: bf18 it ne
80005cc: 3203 addne r2, #3
80005ce: ea5f 0cdc movs.w ip, ip, lsr #3
80005d2: bf18 it ne
80005d4: 3203 addne r2, #3
80005d6: eb02 02dc add.w r2, r2, ip, lsr #3
80005da: f1c2 0320 rsb r3, r2, #32
80005de: fa00 fc03 lsl.w ip, r0, r3
80005e2: fa20 f002 lsr.w r0, r0, r2
80005e6: fa01 fe03 lsl.w lr, r1, r3
80005ea: ea40 000e orr.w r0, r0, lr
80005ee: fa21 f102 lsr.w r1, r1, r2
80005f2: 4414 add r4, r2
80005f4: e6bd b.n 8000372 <__adddf3+0xe6>
80005f6: bf00 nop
080005f8 <__aeabi_dmul>:
80005f8: b570 push {r4, r5, r6, lr}
80005fa: f04f 0cff mov.w ip, #255 @ 0xff
80005fe: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000602: ea1c 5411 ands.w r4, ip, r1, lsr #20
8000606: bf1d ittte ne
8000608: ea1c 5513 andsne.w r5, ip, r3, lsr #20
800060c: ea94 0f0c teqne r4, ip
8000610: ea95 0f0c teqne r5, ip
8000614: f000 f8de bleq 80007d4 <__aeabi_dmul+0x1dc>
8000618: 442c add r4, r5
800061a: ea81 0603 eor.w r6, r1, r3
800061e: ea21 514c bic.w r1, r1, ip, lsl #21
8000622: ea23 534c bic.w r3, r3, ip, lsl #21
8000626: ea50 3501 orrs.w r5, r0, r1, lsl #12
800062a: bf18 it ne
800062c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000630: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000634: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8000638: d038 beq.n 80006ac <__aeabi_dmul+0xb4>
800063a: fba0 ce02 umull ip, lr, r0, r2
800063e: f04f 0500 mov.w r5, #0
8000642: fbe1 e502 umlal lr, r5, r1, r2
8000646: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
800064a: fbe0 e503 umlal lr, r5, r0, r3
800064e: f04f 0600 mov.w r6, #0
8000652: fbe1 5603 umlal r5, r6, r1, r3
8000656: f09c 0f00 teq ip, #0
800065a: bf18 it ne
800065c: f04e 0e01 orrne.w lr, lr, #1
8000660: f1a4 04ff sub.w r4, r4, #255 @ 0xff
8000664: f5b6 7f00 cmp.w r6, #512 @ 0x200
8000668: f564 7440 sbc.w r4, r4, #768 @ 0x300
800066c: d204 bcs.n 8000678 <__aeabi_dmul+0x80>
800066e: ea5f 0e4e movs.w lr, lr, lsl #1
8000672: 416d adcs r5, r5
8000674: eb46 0606 adc.w r6, r6, r6
8000678: ea42 21c6 orr.w r1, r2, r6, lsl #11
800067c: ea41 5155 orr.w r1, r1, r5, lsr #21
8000680: ea4f 20c5 mov.w r0, r5, lsl #11
8000684: ea40 505e orr.w r0, r0, lr, lsr #21
8000688: ea4f 2ece mov.w lr, lr, lsl #11
800068c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
8000690: bf88 it hi
8000692: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
8000696: d81e bhi.n 80006d6 <__aeabi_dmul+0xde>
8000698: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
800069c: bf08 it eq
800069e: ea5f 0e50 movseq.w lr, r0, lsr #1
80006a2: f150 0000 adcs.w r0, r0, #0
80006a6: eb41 5104 adc.w r1, r1, r4, lsl #20
80006aa: bd70 pop {r4, r5, r6, pc}
80006ac: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
80006b0: ea46 0101 orr.w r1, r6, r1
80006b4: ea40 0002 orr.w r0, r0, r2
80006b8: ea81 0103 eor.w r1, r1, r3
80006bc: ebb4 045c subs.w r4, r4, ip, lsr #1
80006c0: bfc2 ittt gt
80006c2: ebd4 050c rsbsgt r5, r4, ip
80006c6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
80006ca: bd70 popgt {r4, r5, r6, pc}
80006cc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80006d0: f04f 0e00 mov.w lr, #0
80006d4: 3c01 subs r4, #1
80006d6: f300 80ab bgt.w 8000830 <__aeabi_dmul+0x238>
80006da: f114 0f36 cmn.w r4, #54 @ 0x36
80006de: bfde ittt le
80006e0: 2000 movle r0, #0
80006e2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
80006e6: bd70 pople {r4, r5, r6, pc}
80006e8: f1c4 0400 rsb r4, r4, #0
80006ec: 3c20 subs r4, #32
80006ee: da35 bge.n 800075c <__aeabi_dmul+0x164>
80006f0: 340c adds r4, #12
80006f2: dc1b bgt.n 800072c <__aeabi_dmul+0x134>
80006f4: f104 0414 add.w r4, r4, #20
80006f8: f1c4 0520 rsb r5, r4, #32
80006fc: fa00 f305 lsl.w r3, r0, r5
8000700: fa20 f004 lsr.w r0, r0, r4
8000704: fa01 f205 lsl.w r2, r1, r5
8000708: ea40 0002 orr.w r0, r0, r2
800070c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000710: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31
8000718: fa21 f604 lsr.w r6, r1, r4
800071c: eb42 0106 adc.w r1, r2, r6
8000720: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000724: bf08 it eq
8000726: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800072a: bd70 pop {r4, r5, r6, pc}
800072c: f1c4 040c rsb r4, r4, #12
8000730: f1c4 0520 rsb r5, r4, #32
8000734: fa00 f304 lsl.w r3, r0, r4
8000738: fa20 f005 lsr.w r0, r0, r5
800073c: fa01 f204 lsl.w r2, r1, r4
8000740: ea40 0002 orr.w r0, r0, r2
8000744: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000748: eb10 70d3 adds.w r0, r0, r3, lsr #31
800074c: f141 0100 adc.w r1, r1, #0
8000750: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000754: bf08 it eq
8000756: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800075a: bd70 pop {r4, r5, r6, pc}
800075c: f1c4 0520 rsb r5, r4, #32
8000760: fa00 f205 lsl.w r2, r0, r5
8000764: ea4e 0e02 orr.w lr, lr, r2
8000768: fa20 f304 lsr.w r3, r0, r4
800076c: fa01 f205 lsl.w r2, r1, r5
8000770: ea43 0302 orr.w r3, r3, r2
8000774: fa21 f004 lsr.w r0, r1, r4
8000778: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800077c: fa21 f204 lsr.w r2, r1, r4
8000780: ea20 0002 bic.w r0, r0, r2
8000784: eb00 70d3 add.w r0, r0, r3, lsr #31
8000788: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
800078c: bf08 it eq
800078e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
8000792: bd70 pop {r4, r5, r6, pc}
8000794: f094 0f00 teq r4, #0
8000798: d10f bne.n 80007ba <__aeabi_dmul+0x1c2>
800079a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
800079e: 0040 lsls r0, r0, #1
80007a0: eb41 0101 adc.w r1, r1, r1
80007a4: f411 1f80 tst.w r1, #1048576 @ 0x100000
80007a8: bf08 it eq
80007aa: 3c01 subeq r4, #1
80007ac: d0f7 beq.n 800079e <__aeabi_dmul+0x1a6>
80007ae: ea41 0106 orr.w r1, r1, r6
80007b2: f095 0f00 teq r5, #0
80007b6: bf18 it ne
80007b8: 4770 bxne lr
80007ba: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
80007be: 0052 lsls r2, r2, #1
80007c0: eb43 0303 adc.w r3, r3, r3
80007c4: f413 1f80 tst.w r3, #1048576 @ 0x100000
80007c8: bf08 it eq
80007ca: 3d01 subeq r5, #1
80007cc: d0f7 beq.n 80007be <__aeabi_dmul+0x1c6>
80007ce: ea43 0306 orr.w r3, r3, r6
80007d2: 4770 bx lr
80007d4: ea94 0f0c teq r4, ip
80007d8: ea0c 5513 and.w r5, ip, r3, lsr #20
80007dc: bf18 it ne
80007de: ea95 0f0c teqne r5, ip
80007e2: d00c beq.n 80007fe <__aeabi_dmul+0x206>
80007e4: ea50 0641 orrs.w r6, r0, r1, lsl #1
80007e8: bf18 it ne
80007ea: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80007ee: d1d1 bne.n 8000794 <__aeabi_dmul+0x19c>
80007f0: ea81 0103 eor.w r1, r1, r3
80007f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80007f8: f04f 0000 mov.w r0, #0
80007fc: bd70 pop {r4, r5, r6, pc}
80007fe: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000802: bf06 itte eq
8000804: 4610 moveq r0, r2
8000806: 4619 moveq r1, r3
8000808: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800080c: d019 beq.n 8000842 <__aeabi_dmul+0x24a>
800080e: ea94 0f0c teq r4, ip
8000812: d102 bne.n 800081a <__aeabi_dmul+0x222>
8000814: ea50 3601 orrs.w r6, r0, r1, lsl #12
8000818: d113 bne.n 8000842 <__aeabi_dmul+0x24a>
800081a: ea95 0f0c teq r5, ip
800081e: d105 bne.n 800082c <__aeabi_dmul+0x234>
8000820: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000824: bf1c itt ne
8000826: 4610 movne r0, r2
8000828: 4619 movne r1, r3
800082a: d10a bne.n 8000842 <__aeabi_dmul+0x24a>
800082c: ea81 0103 eor.w r1, r1, r3
8000830: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000834: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000838: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
800083c: f04f 0000 mov.w r0, #0
8000840: bd70 pop {r4, r5, r6, pc}
8000842: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000846: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
800084a: bd70 pop {r4, r5, r6, pc}
0800084c <__aeabi_ddiv>:
800084c: b570 push {r4, r5, r6, lr}
800084e: f04f 0cff mov.w ip, #255 @ 0xff
8000852: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000856: ea1c 5411 ands.w r4, ip, r1, lsr #20
800085a: bf1d ittte ne
800085c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000860: ea94 0f0c teqne r4, ip
8000864: ea95 0f0c teqne r5, ip
8000868: f000 f8a7 bleq 80009ba <__aeabi_ddiv+0x16e>
800086c: eba4 0405 sub.w r4, r4, r5
8000870: ea81 0e03 eor.w lr, r1, r3
8000874: ea52 3503 orrs.w r5, r2, r3, lsl #12
8000878: ea4f 3101 mov.w r1, r1, lsl #12
800087c: f000 8088 beq.w 8000990 <__aeabi_ddiv+0x144>
8000880: ea4f 3303 mov.w r3, r3, lsl #12
8000884: f04f 5580 mov.w r5, #268435456 @ 0x10000000
8000888: ea45 1313 orr.w r3, r5, r3, lsr #4
800088c: ea43 6312 orr.w r3, r3, r2, lsr #24
8000890: ea4f 2202 mov.w r2, r2, lsl #8
8000894: ea45 1511 orr.w r5, r5, r1, lsr #4
8000898: ea45 6510 orr.w r5, r5, r0, lsr #24
800089c: ea4f 2600 mov.w r6, r0, lsl #8
80008a0: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
80008a4: 429d cmp r5, r3
80008a6: bf08 it eq
80008a8: 4296 cmpeq r6, r2
80008aa: f144 04fd adc.w r4, r4, #253 @ 0xfd
80008ae: f504 7440 add.w r4, r4, #768 @ 0x300
80008b2: d202 bcs.n 80008ba <__aeabi_ddiv+0x6e>
80008b4: 085b lsrs r3, r3, #1
80008b6: ea4f 0232 mov.w r2, r2, rrx
80008ba: 1ab6 subs r6, r6, r2
80008bc: eb65 0503 sbc.w r5, r5, r3
80008c0: 085b lsrs r3, r3, #1
80008c2: ea4f 0232 mov.w r2, r2, rrx
80008c6: f44f 1080 mov.w r0, #1048576 @ 0x100000
80008ca: f44f 2c00 mov.w ip, #524288 @ 0x80000
80008ce: ebb6 0e02 subs.w lr, r6, r2
80008d2: eb75 0e03 sbcs.w lr, r5, r3
80008d6: bf22 ittt cs
80008d8: 1ab6 subcs r6, r6, r2
80008da: 4675 movcs r5, lr
80008dc: ea40 000c orrcs.w r0, r0, ip
80008e0: 085b lsrs r3, r3, #1
80008e2: ea4f 0232 mov.w r2, r2, rrx
80008e6: ebb6 0e02 subs.w lr, r6, r2
80008ea: eb75 0e03 sbcs.w lr, r5, r3
80008ee: bf22 ittt cs
80008f0: 1ab6 subcs r6, r6, r2
80008f2: 4675 movcs r5, lr
80008f4: ea40 005c orrcs.w r0, r0, ip, lsr #1
80008f8: 085b lsrs r3, r3, #1
80008fa: ea4f 0232 mov.w r2, r2, rrx
80008fe: ebb6 0e02 subs.w lr, r6, r2
8000902: eb75 0e03 sbcs.w lr, r5, r3
8000906: bf22 ittt cs
8000908: 1ab6 subcs r6, r6, r2
800090a: 4675 movcs r5, lr
800090c: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000910: 085b lsrs r3, r3, #1
8000912: ea4f 0232 mov.w r2, r2, rrx
8000916: ebb6 0e02 subs.w lr, r6, r2
800091a: eb75 0e03 sbcs.w lr, r5, r3
800091e: bf22 ittt cs
8000920: 1ab6 subcs r6, r6, r2
8000922: 4675 movcs r5, lr
8000924: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000928: ea55 0e06 orrs.w lr, r5, r6
800092c: d018 beq.n 8000960 <__aeabi_ddiv+0x114>
800092e: ea4f 1505 mov.w r5, r5, lsl #4
8000932: ea45 7516 orr.w r5, r5, r6, lsr #28
8000936: ea4f 1606 mov.w r6, r6, lsl #4
800093a: ea4f 03c3 mov.w r3, r3, lsl #3
800093e: ea43 7352 orr.w r3, r3, r2, lsr #29
8000942: ea4f 02c2 mov.w r2, r2, lsl #3
8000946: ea5f 1c1c movs.w ip, ip, lsr #4
800094a: d1c0 bne.n 80008ce <__aeabi_ddiv+0x82>
800094c: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000950: d10b bne.n 800096a <__aeabi_ddiv+0x11e>
8000952: ea41 0100 orr.w r1, r1, r0
8000956: f04f 0000 mov.w r0, #0
800095a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
800095e: e7b6 b.n 80008ce <__aeabi_ddiv+0x82>
8000960: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000964: bf04 itt eq
8000966: 4301 orreq r1, r0
8000968: 2000 moveq r0, #0
800096a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
800096e: bf88 it hi
8000970: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
8000974: f63f aeaf bhi.w 80006d6 <__aeabi_dmul+0xde>
8000978: ebb5 0c03 subs.w ip, r5, r3
800097c: bf04 itt eq
800097e: ebb6 0c02 subseq.w ip, r6, r2
8000982: ea5f 0c50 movseq.w ip, r0, lsr #1
8000986: f150 0000 adcs.w r0, r0, #0
800098a: eb41 5104 adc.w r1, r1, r4, lsl #20
800098e: bd70 pop {r4, r5, r6, pc}
8000990: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
8000994: ea4e 3111 orr.w r1, lr, r1, lsr #12
8000998: eb14 045c adds.w r4, r4, ip, lsr #1
800099c: bfc2 ittt gt
800099e: ebd4 050c rsbsgt r5, r4, ip
80009a2: ea41 5104 orrgt.w r1, r1, r4, lsl #20
80009a6: bd70 popgt {r4, r5, r6, pc}
80009a8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80009ac: f04f 0e00 mov.w lr, #0
80009b0: 3c01 subs r4, #1
80009b2: e690 b.n 80006d6 <__aeabi_dmul+0xde>
80009b4: ea45 0e06 orr.w lr, r5, r6
80009b8: e68d b.n 80006d6 <__aeabi_dmul+0xde>
80009ba: ea0c 5513 and.w r5, ip, r3, lsr #20
80009be: ea94 0f0c teq r4, ip
80009c2: bf08 it eq
80009c4: ea95 0f0c teqeq r5, ip
80009c8: f43f af3b beq.w 8000842 <__aeabi_dmul+0x24a>
80009cc: ea94 0f0c teq r4, ip
80009d0: d10a bne.n 80009e8 <__aeabi_ddiv+0x19c>
80009d2: ea50 3401 orrs.w r4, r0, r1, lsl #12
80009d6: f47f af34 bne.w 8000842 <__aeabi_dmul+0x24a>
80009da: ea95 0f0c teq r5, ip
80009de: f47f af25 bne.w 800082c <__aeabi_dmul+0x234>
80009e2: 4610 mov r0, r2
80009e4: 4619 mov r1, r3
80009e6: e72c b.n 8000842 <__aeabi_dmul+0x24a>
80009e8: ea95 0f0c teq r5, ip
80009ec: d106 bne.n 80009fc <__aeabi_ddiv+0x1b0>
80009ee: ea52 3503 orrs.w r5, r2, r3, lsl #12
80009f2: f43f aefd beq.w 80007f0 <__aeabi_dmul+0x1f8>
80009f6: 4610 mov r0, r2
80009f8: 4619 mov r1, r3
80009fa: e722 b.n 8000842 <__aeabi_dmul+0x24a>
80009fc: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000a00: bf18 it ne
8000a02: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000a06: f47f aec5 bne.w 8000794 <__aeabi_dmul+0x19c>
8000a0a: ea50 0441 orrs.w r4, r0, r1, lsl #1
8000a0e: f47f af0d bne.w 800082c <__aeabi_dmul+0x234>
8000a12: ea52 0543 orrs.w r5, r2, r3, lsl #1
8000a16: f47f aeeb bne.w 80007f0 <__aeabi_dmul+0x1f8>
8000a1a: e712 b.n 8000842 <__aeabi_dmul+0x24a>
08000a1c <__gedf2>:
8000a1c: f04f 3cff mov.w ip, #4294967295
8000a20: e006 b.n 8000a30 <__cmpdf2+0x4>
8000a22: bf00 nop
08000a24 <__ledf2>:
8000a24: f04f 0c01 mov.w ip, #1
8000a28: e002 b.n 8000a30 <__cmpdf2+0x4>
8000a2a: bf00 nop
08000a2c <__cmpdf2>:
8000a2c: f04f 0c01 mov.w ip, #1
8000a30: f84d cd04 str.w ip, [sp, #-4]!
8000a34: ea4f 0c41 mov.w ip, r1, lsl #1
8000a38: ea7f 5c6c mvns.w ip, ip, asr #21
8000a3c: ea4f 0c43 mov.w ip, r3, lsl #1
8000a40: bf18 it ne
8000a42: ea7f 5c6c mvnsne.w ip, ip, asr #21
8000a46: d01b beq.n 8000a80 <__cmpdf2+0x54>
8000a48: b001 add sp, #4
8000a4a: ea50 0c41 orrs.w ip, r0, r1, lsl #1
8000a4e: bf0c ite eq
8000a50: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
8000a54: ea91 0f03 teqne r1, r3
8000a58: bf02 ittt eq
8000a5a: ea90 0f02 teqeq r0, r2
8000a5e: 2000 moveq r0, #0
8000a60: 4770 bxeq lr
8000a62: f110 0f00 cmn.w r0, #0
8000a66: ea91 0f03 teq r1, r3
8000a6a: bf58 it pl
8000a6c: 4299 cmppl r1, r3
8000a6e: bf08 it eq
8000a70: 4290 cmpeq r0, r2
8000a72: bf2c ite cs
8000a74: 17d8 asrcs r0, r3, #31
8000a76: ea6f 70e3 mvncc.w r0, r3, asr #31
8000a7a: f040 0001 orr.w r0, r0, #1
8000a7e: 4770 bx lr
8000a80: ea4f 0c41 mov.w ip, r1, lsl #1
8000a84: ea7f 5c6c mvns.w ip, ip, asr #21
8000a88: d102 bne.n 8000a90 <__cmpdf2+0x64>
8000a8a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
8000a8e: d107 bne.n 8000aa0 <__cmpdf2+0x74>
8000a90: ea4f 0c43 mov.w ip, r3, lsl #1
8000a94: ea7f 5c6c mvns.w ip, ip, asr #21
8000a98: d1d6 bne.n 8000a48 <__cmpdf2+0x1c>
8000a9a: ea52 3c03 orrs.w ip, r2, r3, lsl #12
8000a9e: d0d3 beq.n 8000a48 <__cmpdf2+0x1c>
8000aa0: f85d 0b04 ldr.w r0, [sp], #4
8000aa4: 4770 bx lr
8000aa6: bf00 nop
08000aa8 <__aeabi_cdrcmple>:
8000aa8: 4684 mov ip, r0
8000aaa: 4610 mov r0, r2
8000aac: 4662 mov r2, ip
8000aae: 468c mov ip, r1
8000ab0: 4619 mov r1, r3
8000ab2: 4663 mov r3, ip
8000ab4: e000 b.n 8000ab8 <__aeabi_cdcmpeq>
8000ab6: bf00 nop
08000ab8 <__aeabi_cdcmpeq>:
8000ab8: b501 push {r0, lr}
8000aba: f7ff ffb7 bl 8000a2c <__cmpdf2>
8000abe: 2800 cmp r0, #0
8000ac0: bf48 it mi
8000ac2: f110 0f00 cmnmi.w r0, #0
8000ac6: bd01 pop {r0, pc}
08000ac8 <__aeabi_dcmpeq>:
8000ac8: f84d ed08 str.w lr, [sp, #-8]!
8000acc: f7ff fff4 bl 8000ab8 <__aeabi_cdcmpeq>
8000ad0: bf0c ite eq
8000ad2: 2001 moveq r0, #1
8000ad4: 2000 movne r0, #0
8000ad6: f85d fb08 ldr.w pc, [sp], #8
8000ada: bf00 nop
08000adc <__aeabi_dcmplt>:
8000adc: f84d ed08 str.w lr, [sp, #-8]!
8000ae0: f7ff ffea bl 8000ab8 <__aeabi_cdcmpeq>
8000ae4: bf34 ite cc
8000ae6: 2001 movcc r0, #1
8000ae8: 2000 movcs r0, #0
8000aea: f85d fb08 ldr.w pc, [sp], #8
8000aee: bf00 nop
08000af0 <__aeabi_dcmple>:
8000af0: f84d ed08 str.w lr, [sp, #-8]!
8000af4: f7ff ffe0 bl 8000ab8 <__aeabi_cdcmpeq>
8000af8: bf94 ite ls
8000afa: 2001 movls r0, #1
8000afc: 2000 movhi r0, #0
8000afe: f85d fb08 ldr.w pc, [sp], #8
8000b02: bf00 nop
08000b04 <__aeabi_dcmpge>:
8000b04: f84d ed08 str.w lr, [sp, #-8]!
8000b08: f7ff ffce bl 8000aa8 <__aeabi_cdrcmple>
8000b0c: bf94 ite ls
8000b0e: 2001 movls r0, #1
8000b10: 2000 movhi r0, #0
8000b12: f85d fb08 ldr.w pc, [sp], #8
8000b16: bf00 nop
08000b18 <__aeabi_dcmpgt>:
8000b18: f84d ed08 str.w lr, [sp, #-8]!
8000b1c: f7ff ffc4 bl 8000aa8 <__aeabi_cdrcmple>
8000b20: bf34 ite cc
8000b22: 2001 movcc r0, #1
8000b24: 2000 movcs r0, #0
8000b26: f85d fb08 ldr.w pc, [sp], #8
8000b2a: bf00 nop
08000b2c <__aeabi_dcmpun>:
8000b2c: ea4f 0c41 mov.w ip, r1, lsl #1
8000b30: ea7f 5c6c mvns.w ip, ip, asr #21
8000b34: d102 bne.n 8000b3c <__aeabi_dcmpun+0x10>
8000b36: ea50 3c01 orrs.w ip, r0, r1, lsl #12
8000b3a: d10a bne.n 8000b52 <__aeabi_dcmpun+0x26>
8000b3c: ea4f 0c43 mov.w ip, r3, lsl #1
8000b40: ea7f 5c6c mvns.w ip, ip, asr #21
8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x20>
8000b46: ea52 3c03 orrs.w ip, r2, r3, lsl #12
8000b4a: d102 bne.n 8000b52 <__aeabi_dcmpun+0x26>
8000b4c: f04f 0000 mov.w r0, #0
8000b50: 4770 bx lr
8000b52: f04f 0001 mov.w r0, #1
8000b56: 4770 bx lr
08000b58 <__aeabi_d2iz>:
8000b58: ea4f 0241 mov.w r2, r1, lsl #1
8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000b60: d215 bcs.n 8000b8e <__aeabi_d2iz+0x36>
8000b62: d511 bpl.n 8000b88 <__aeabi_d2iz+0x30>
8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0
8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21
8000b6c: d912 bls.n 8000b94 <__aeabi_d2iz+0x3c>
8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11
8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21
8000b7a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
8000b7e: fa23 f002 lsr.w r0, r3, r2
8000b82: bf18 it ne
8000b84: 4240 negne r0, r0
8000b86: 4770 bx lr
8000b88: f04f 0000 mov.w r0, #0
8000b8c: 4770 bx lr
8000b8e: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000b92: d105 bne.n 8000ba0 <__aeabi_d2iz+0x48>
8000b94: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
8000b98: bf08 it eq
8000b9a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
8000b9e: 4770 bx lr
8000ba0: f04f 0000 mov.w r0, #0
8000ba4: 4770 bx lr
8000ba6: bf00 nop
08000ba8 <__aeabi_uldivmod>:
8000ba8: b953 cbnz r3, 8000bc0 <__aeabi_uldivmod+0x18>
8000baa: b94a cbnz r2, 8000bc0 <__aeabi_uldivmod+0x18>
8000bac: 2900 cmp r1, #0
8000bae: bf08 it eq
8000bb0: 2800 cmpeq r0, #0
8000bb2: bf1c itt ne
8000bb4: f04f 31ff movne.w r1, #4294967295
8000bb8: f04f 30ff movne.w r0, #4294967295
8000bbc: f000 b988 b.w 8000ed0 <__aeabi_idiv0>
8000bc0: f1ad 0c08 sub.w ip, sp, #8
8000bc4: e96d ce04 strd ip, lr, [sp, #-16]!
8000bc8: f000 f806 bl 8000bd8 <__udivmoddi4>
8000bcc: f8dd e004 ldr.w lr, [sp, #4]
8000bd0: e9dd 2302 ldrd r2, r3, [sp, #8]
8000bd4: b004 add sp, #16
8000bd6: 4770 bx lr
08000bd8 <__udivmoddi4>:
8000bd8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000bdc: 9d08 ldr r5, [sp, #32]
8000bde: 468e mov lr, r1
8000be0: 4604 mov r4, r0
8000be2: 4688 mov r8, r1
8000be4: 2b00 cmp r3, #0
8000be6: d14a bne.n 8000c7e <__udivmoddi4+0xa6>
8000be8: 428a cmp r2, r1
8000bea: 4617 mov r7, r2
8000bec: d962 bls.n 8000cb4 <__udivmoddi4+0xdc>
8000bee: fab2 f682 clz r6, r2
8000bf2: b14e cbz r6, 8000c08 <__udivmoddi4+0x30>
8000bf4: f1c6 0320 rsb r3, r6, #32
8000bf8: fa01 f806 lsl.w r8, r1, r6
8000bfc: fa20 f303 lsr.w r3, r0, r3
8000c00: 40b7 lsls r7, r6
8000c02: ea43 0808 orr.w r8, r3, r8
8000c06: 40b4 lsls r4, r6
8000c08: ea4f 4e17 mov.w lr, r7, lsr #16
8000c0c: fa1f fc87 uxth.w ip, r7
8000c10: fbb8 f1fe udiv r1, r8, lr
8000c14: 0c23 lsrs r3, r4, #16
8000c16: fb0e 8811 mls r8, lr, r1, r8
8000c1a: ea43 4308 orr.w r3, r3, r8, lsl #16
8000c1e: fb01 f20c mul.w r2, r1, ip
8000c22: 429a cmp r2, r3
8000c24: d909 bls.n 8000c3a <__udivmoddi4+0x62>
8000c26: 18fb adds r3, r7, r3
8000c28: f101 30ff add.w r0, r1, #4294967295
8000c2c: f080 80ea bcs.w 8000e04 <__udivmoddi4+0x22c>
8000c30: 429a cmp r2, r3
8000c32: f240 80e7 bls.w 8000e04 <__udivmoddi4+0x22c>
8000c36: 3902 subs r1, #2
8000c38: 443b add r3, r7
8000c3a: 1a9a subs r2, r3, r2
8000c3c: b2a3 uxth r3, r4
8000c3e: fbb2 f0fe udiv r0, r2, lr
8000c42: fb0e 2210 mls r2, lr, r0, r2
8000c46: ea43 4302 orr.w r3, r3, r2, lsl #16
8000c4a: fb00 fc0c mul.w ip, r0, ip
8000c4e: 459c cmp ip, r3
8000c50: d909 bls.n 8000c66 <__udivmoddi4+0x8e>
8000c52: 18fb adds r3, r7, r3
8000c54: f100 32ff add.w r2, r0, #4294967295
8000c58: f080 80d6 bcs.w 8000e08 <__udivmoddi4+0x230>
8000c5c: 459c cmp ip, r3
8000c5e: f240 80d3 bls.w 8000e08 <__udivmoddi4+0x230>
8000c62: 443b add r3, r7
8000c64: 3802 subs r0, #2
8000c66: ea40 4001 orr.w r0, r0, r1, lsl #16
8000c6a: eba3 030c sub.w r3, r3, ip
8000c6e: 2100 movs r1, #0
8000c70: b11d cbz r5, 8000c7a <__udivmoddi4+0xa2>
8000c72: 40f3 lsrs r3, r6
8000c74: 2200 movs r2, #0
8000c76: e9c5 3200 strd r3, r2, [r5]
8000c7a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000c7e: 428b cmp r3, r1
8000c80: d905 bls.n 8000c8e <__udivmoddi4+0xb6>
8000c82: b10d cbz r5, 8000c88 <__udivmoddi4+0xb0>
8000c84: e9c5 0100 strd r0, r1, [r5]
8000c88: 2100 movs r1, #0
8000c8a: 4608 mov r0, r1
8000c8c: e7f5 b.n 8000c7a <__udivmoddi4+0xa2>
8000c8e: fab3 f183 clz r1, r3
8000c92: 2900 cmp r1, #0
8000c94: d146 bne.n 8000d24 <__udivmoddi4+0x14c>
8000c96: 4573 cmp r3, lr
8000c98: d302 bcc.n 8000ca0 <__udivmoddi4+0xc8>
8000c9a: 4282 cmp r2, r0
8000c9c: f200 8105 bhi.w 8000eaa <__udivmoddi4+0x2d2>
8000ca0: 1a84 subs r4, r0, r2
8000ca2: eb6e 0203 sbc.w r2, lr, r3
8000ca6: 2001 movs r0, #1
8000ca8: 4690 mov r8, r2
8000caa: 2d00 cmp r5, #0
8000cac: d0e5 beq.n 8000c7a <__udivmoddi4+0xa2>
8000cae: e9c5 4800 strd r4, r8, [r5]
8000cb2: e7e2 b.n 8000c7a <__udivmoddi4+0xa2>
8000cb4: 2a00 cmp r2, #0
8000cb6: f000 8090 beq.w 8000dda <__udivmoddi4+0x202>
8000cba: fab2 f682 clz r6, r2
8000cbe: 2e00 cmp r6, #0
8000cc0: f040 80a4 bne.w 8000e0c <__udivmoddi4+0x234>
8000cc4: 1a8a subs r2, r1, r2
8000cc6: 0c03 lsrs r3, r0, #16
8000cc8: ea4f 4e17 mov.w lr, r7, lsr #16
8000ccc: b280 uxth r0, r0
8000cce: b2bc uxth r4, r7
8000cd0: 2101 movs r1, #1
8000cd2: fbb2 fcfe udiv ip, r2, lr
8000cd6: fb0e 221c mls r2, lr, ip, r2
8000cda: ea43 4302 orr.w r3, r3, r2, lsl #16
8000cde: fb04 f20c mul.w r2, r4, ip
8000ce2: 429a cmp r2, r3
8000ce4: d907 bls.n 8000cf6 <__udivmoddi4+0x11e>
8000ce6: 18fb adds r3, r7, r3
8000ce8: f10c 38ff add.w r8, ip, #4294967295
8000cec: d202 bcs.n 8000cf4 <__udivmoddi4+0x11c>
8000cee: 429a cmp r2, r3
8000cf0: f200 80e0 bhi.w 8000eb4 <__udivmoddi4+0x2dc>
8000cf4: 46c4 mov ip, r8
8000cf6: 1a9b subs r3, r3, r2
8000cf8: fbb3 f2fe udiv r2, r3, lr
8000cfc: fb0e 3312 mls r3, lr, r2, r3
8000d00: ea40 4303 orr.w r3, r0, r3, lsl #16
8000d04: fb02 f404 mul.w r4, r2, r4
8000d08: 429c cmp r4, r3
8000d0a: d907 bls.n 8000d1c <__udivmoddi4+0x144>
8000d0c: 18fb adds r3, r7, r3
8000d0e: f102 30ff add.w r0, r2, #4294967295
8000d12: d202 bcs.n 8000d1a <__udivmoddi4+0x142>
8000d14: 429c cmp r4, r3
8000d16: f200 80ca bhi.w 8000eae <__udivmoddi4+0x2d6>
8000d1a: 4602 mov r2, r0
8000d1c: 1b1b subs r3, r3, r4
8000d1e: ea42 400c orr.w r0, r2, ip, lsl #16
8000d22: e7a5 b.n 8000c70 <__udivmoddi4+0x98>
8000d24: f1c1 0620 rsb r6, r1, #32
8000d28: 408b lsls r3, r1
8000d2a: fa22 f706 lsr.w r7, r2, r6
8000d2e: 431f orrs r7, r3
8000d30: fa0e f401 lsl.w r4, lr, r1
8000d34: fa20 f306 lsr.w r3, r0, r6
8000d38: fa2e fe06 lsr.w lr, lr, r6
8000d3c: ea4f 4917 mov.w r9, r7, lsr #16
8000d40: 4323 orrs r3, r4
8000d42: fa00 f801 lsl.w r8, r0, r1
8000d46: fa1f fc87 uxth.w ip, r7
8000d4a: fbbe f0f9 udiv r0, lr, r9
8000d4e: 0c1c lsrs r4, r3, #16
8000d50: fb09 ee10 mls lr, r9, r0, lr
8000d54: ea44 440e orr.w r4, r4, lr, lsl #16
8000d58: fb00 fe0c mul.w lr, r0, ip
8000d5c: 45a6 cmp lr, r4
8000d5e: fa02 f201 lsl.w r2, r2, r1
8000d62: d909 bls.n 8000d78 <__udivmoddi4+0x1a0>
8000d64: 193c adds r4, r7, r4
8000d66: f100 3aff add.w sl, r0, #4294967295
8000d6a: f080 809c bcs.w 8000ea6 <__udivmoddi4+0x2ce>
8000d6e: 45a6 cmp lr, r4
8000d70: f240 8099 bls.w 8000ea6 <__udivmoddi4+0x2ce>
8000d74: 3802 subs r0, #2
8000d76: 443c add r4, r7
8000d78: eba4 040e sub.w r4, r4, lr
8000d7c: fa1f fe83 uxth.w lr, r3
8000d80: fbb4 f3f9 udiv r3, r4, r9
8000d84: fb09 4413 mls r4, r9, r3, r4
8000d88: ea4e 4404 orr.w r4, lr, r4, lsl #16
8000d8c: fb03 fc0c mul.w ip, r3, ip
8000d90: 45a4 cmp ip, r4
8000d92: d908 bls.n 8000da6 <__udivmoddi4+0x1ce>
8000d94: 193c adds r4, r7, r4
8000d96: f103 3eff add.w lr, r3, #4294967295
8000d9a: f080 8082 bcs.w 8000ea2 <__udivmoddi4+0x2ca>
8000d9e: 45a4 cmp ip, r4
8000da0: d97f bls.n 8000ea2 <__udivmoddi4+0x2ca>
8000da2: 3b02 subs r3, #2
8000da4: 443c add r4, r7
8000da6: ea43 4000 orr.w r0, r3, r0, lsl #16
8000daa: eba4 040c sub.w r4, r4, ip
8000dae: fba0 ec02 umull lr, ip, r0, r2
8000db2: 4564 cmp r4, ip
8000db4: 4673 mov r3, lr
8000db6: 46e1 mov r9, ip
8000db8: d362 bcc.n 8000e80 <__udivmoddi4+0x2a8>
8000dba: d05f beq.n 8000e7c <__udivmoddi4+0x2a4>
8000dbc: b15d cbz r5, 8000dd6 <__udivmoddi4+0x1fe>
8000dbe: ebb8 0203 subs.w r2, r8, r3
8000dc2: eb64 0409 sbc.w r4, r4, r9
8000dc6: fa04 f606 lsl.w r6, r4, r6
8000dca: fa22 f301 lsr.w r3, r2, r1
8000dce: 431e orrs r6, r3
8000dd0: 40cc lsrs r4, r1
8000dd2: e9c5 6400 strd r6, r4, [r5]
8000dd6: 2100 movs r1, #0
8000dd8: e74f b.n 8000c7a <__udivmoddi4+0xa2>
8000dda: fbb1 fcf2 udiv ip, r1, r2
8000dde: 0c01 lsrs r1, r0, #16
8000de0: ea41 410e orr.w r1, r1, lr, lsl #16
8000de4: b280 uxth r0, r0
8000de6: ea40 4201 orr.w r2, r0, r1, lsl #16
8000dea: 463b mov r3, r7
8000dec: 4638 mov r0, r7
8000dee: 463c mov r4, r7
8000df0: 46b8 mov r8, r7
8000df2: 46be mov lr, r7
8000df4: 2620 movs r6, #32
8000df6: fbb1 f1f7 udiv r1, r1, r7
8000dfa: eba2 0208 sub.w r2, r2, r8
8000dfe: ea41 410c orr.w r1, r1, ip, lsl #16
8000e02: e766 b.n 8000cd2 <__udivmoddi4+0xfa>
8000e04: 4601 mov r1, r0
8000e06: e718 b.n 8000c3a <__udivmoddi4+0x62>
8000e08: 4610 mov r0, r2
8000e0a: e72c b.n 8000c66 <__udivmoddi4+0x8e>
8000e0c: f1c6 0220 rsb r2, r6, #32
8000e10: fa2e f302 lsr.w r3, lr, r2
8000e14: 40b7 lsls r7, r6
8000e16: 40b1 lsls r1, r6
8000e18: fa20 f202 lsr.w r2, r0, r2
8000e1c: ea4f 4e17 mov.w lr, r7, lsr #16
8000e20: 430a orrs r2, r1
8000e22: fbb3 f8fe udiv r8, r3, lr
8000e26: b2bc uxth r4, r7
8000e28: fb0e 3318 mls r3, lr, r8, r3
8000e2c: 0c11 lsrs r1, r2, #16
8000e2e: ea41 4103 orr.w r1, r1, r3, lsl #16
8000e32: fb08 f904 mul.w r9, r8, r4
8000e36: 40b0 lsls r0, r6
8000e38: 4589 cmp r9, r1
8000e3a: ea4f 4310 mov.w r3, r0, lsr #16
8000e3e: b280 uxth r0, r0
8000e40: d93e bls.n 8000ec0 <__udivmoddi4+0x2e8>
8000e42: 1879 adds r1, r7, r1
8000e44: f108 3cff add.w ip, r8, #4294967295
8000e48: d201 bcs.n 8000e4e <__udivmoddi4+0x276>
8000e4a: 4589 cmp r9, r1
8000e4c: d81f bhi.n 8000e8e <__udivmoddi4+0x2b6>
8000e4e: eba1 0109 sub.w r1, r1, r9
8000e52: fbb1 f9fe udiv r9, r1, lr
8000e56: fb09 f804 mul.w r8, r9, r4
8000e5a: fb0e 1119 mls r1, lr, r9, r1
8000e5e: b292 uxth r2, r2
8000e60: ea42 4201 orr.w r2, r2, r1, lsl #16
8000e64: 4542 cmp r2, r8
8000e66: d229 bcs.n 8000ebc <__udivmoddi4+0x2e4>
8000e68: 18ba adds r2, r7, r2
8000e6a: f109 31ff add.w r1, r9, #4294967295
8000e6e: d2c4 bcs.n 8000dfa <__udivmoddi4+0x222>
8000e70: 4542 cmp r2, r8
8000e72: d2c2 bcs.n 8000dfa <__udivmoddi4+0x222>
8000e74: f1a9 0102 sub.w r1, r9, #2
8000e78: 443a add r2, r7
8000e7a: e7be b.n 8000dfa <__udivmoddi4+0x222>
8000e7c: 45f0 cmp r8, lr
8000e7e: d29d bcs.n 8000dbc <__udivmoddi4+0x1e4>
8000e80: ebbe 0302 subs.w r3, lr, r2
8000e84: eb6c 0c07 sbc.w ip, ip, r7
8000e88: 3801 subs r0, #1
8000e8a: 46e1 mov r9, ip
8000e8c: e796 b.n 8000dbc <__udivmoddi4+0x1e4>
8000e8e: eba7 0909 sub.w r9, r7, r9
8000e92: 4449 add r1, r9
8000e94: f1a8 0c02 sub.w ip, r8, #2
8000e98: fbb1 f9fe udiv r9, r1, lr
8000e9c: fb09 f804 mul.w r8, r9, r4
8000ea0: e7db b.n 8000e5a <__udivmoddi4+0x282>
8000ea2: 4673 mov r3, lr
8000ea4: e77f b.n 8000da6 <__udivmoddi4+0x1ce>
8000ea6: 4650 mov r0, sl
8000ea8: e766 b.n 8000d78 <__udivmoddi4+0x1a0>
8000eaa: 4608 mov r0, r1
8000eac: e6fd b.n 8000caa <__udivmoddi4+0xd2>
8000eae: 443b add r3, r7
8000eb0: 3a02 subs r2, #2
8000eb2: e733 b.n 8000d1c <__udivmoddi4+0x144>
8000eb4: f1ac 0c02 sub.w ip, ip, #2
8000eb8: 443b add r3, r7
8000eba: e71c b.n 8000cf6 <__udivmoddi4+0x11e>
8000ebc: 4649 mov r1, r9
8000ebe: e79c b.n 8000dfa <__udivmoddi4+0x222>
8000ec0: eba1 0109 sub.w r1, r1, r9
8000ec4: 46c4 mov ip, r8
8000ec6: fbb1 f9fe udiv r9, r1, lr
8000eca: fb09 f804 mul.w r8, r9, r4
8000ece: e7c4 b.n 8000e5a <__udivmoddi4+0x282>
08000ed0 <__aeabi_idiv0>:
8000ed0: 4770 bx lr
8000ed2: bf00 nop
08000ed4 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000ed4: b580 push {r7, lr}
8000ed6: b084 sub sp, #16
8000ed8: af00 add r7, sp, #0
int main(void)
8000eda: f107 0318 add.w r3, r7, #24
8000ede: 60fb str r3, [r7, #12]
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000ee0: f001 f8af bl 8002042 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000ee4: f000 f826 bl 8000f34 <SystemClock_Config>
/* Configure the peripherals common clocks */
PeriphCommonClock_Config();
8000ee8: f000 f886 bl 8000ff8 <PeriphCommonClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000eec: f000 faf4 bl 80014d8 <MX_GPIO_Init>
MX_DFSDM1_Init();
8000ef0: f000 f926 bl 8001140 <MX_DFSDM1_Init>
MX_I2C2_Init();
8000ef4: f000 f95c bl 80011b0 <MX_I2C2_Init>
MX_QUADSPI_Init();
8000ef8: f000 f99a bl 8001230 <MX_QUADSPI_Init>
MX_SPI3_Init();
8000efc: f000 f9be bl 800127c <MX_SPI3_Init>
MX_USART1_UART_Init();
8000f00: f000 fa8a bl 8001418 <MX_USART1_UART_Init>
MX_USART3_UART_Init();
8000f04: f000 fab8 bl 8001478 <MX_USART3_UART_Init>
MX_TIM7_Init();
8000f08: f000 fa50 bl 80013ac <MX_TIM7_Init>
MX_USB_DEVICE_Init();
8000f0c: f009 ff1e bl 800ad4c <MX_USB_DEVICE_Init>
MX_ADC1_Init();
8000f10: f000 f8a0 bl 8001054 <MX_ADC1_Init>
MX_TIM2_Init();
8000f14: f000 f9f0 bl 80012f8 <MX_TIM2_Init>
/* USER CODE BEGIN 2 */
uint8_t escala[] = {60, 62, 64, 65, 67, 69, 71}; // Do Re Mi Fa Sol La Si
8000f18: 4a05 ldr r2, [pc, #20] @ (8000f30 <main+0x5c>)
8000f1a: 1d3b adds r3, r7, #4
8000f1c: e892 0003 ldmia.w r2, {r0, r1}
8000f20: 6018 str r0, [r3, #0]
8000f22: 3304 adds r3, #4
8000f24: 8019 strh r1, [r3, #0]
8000f26: 3302 adds r3, #2
8000f28: 0c0a lsrs r2, r1, #16
8000f2a: 701a strb r2, [r3, #0]
}
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000f2c: bf00 nop
8000f2e: e7fd b.n 8000f2c <main+0x58>
8000f30: 0800e170 .word 0x0800e170
08000f34 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000f34: b580 push {r7, lr}
8000f36: b096 sub sp, #88 @ 0x58
8000f38: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000f3a: f107 0314 add.w r3, r7, #20
8000f3e: 2244 movs r2, #68 @ 0x44
8000f40: 2100 movs r1, #0
8000f42: 4618 mov r0, r3
8000f44: f00b f9e3 bl 800c30e <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000f48: 463b mov r3, r7
8000f4a: 2200 movs r2, #0
8000f4c: 601a str r2, [r3, #0]
8000f4e: 605a str r2, [r3, #4]
8000f50: 609a str r2, [r3, #8]
8000f52: 60da str r2, [r3, #12]
8000f54: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
8000f56: f44f 7000 mov.w r0, #512 @ 0x200
8000f5a: f003 ff81 bl 8004e60 <HAL_PWREx_ControlVoltageScaling>
8000f5e: 4603 mov r3, r0
8000f60: 2b00 cmp r3, #0
8000f62: d001 beq.n 8000f68 <SystemClock_Config+0x34>
{
Error_Handler();
8000f64: f000 fc30 bl 80017c8 <Error_Handler>
}
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
8000f68: f003 ff5c bl 8004e24 <HAL_PWR_EnableBkUpAccess>
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
8000f6c: 4b21 ldr r3, [pc, #132] @ (8000ff4 <SystemClock_Config+0xc0>)
8000f6e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8000f72: 4a20 ldr r2, [pc, #128] @ (8000ff4 <SystemClock_Config+0xc0>)
8000f74: f023 0318 bic.w r3, r3, #24
8000f78: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
8000f7c: 2314 movs r3, #20
8000f7e: 617b str r3, [r7, #20]
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
8000f80: 2301 movs r3, #1
8000f82: 61fb str r3, [r7, #28]
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
8000f84: 2301 movs r3, #1
8000f86: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.MSICalibrationValue = 0;
8000f88: 2300 movs r3, #0
8000f8a: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
8000f8c: 2360 movs r3, #96 @ 0x60
8000f8e: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000f90: 2302 movs r3, #2
8000f92: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
8000f94: 2301 movs r3, #1
8000f96: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLM = 1;
8000f98: 2301 movs r3, #1
8000f9a: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLN = 40;
8000f9c: 2328 movs r3, #40 @ 0x28
8000f9e: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
8000fa0: 2307 movs r3, #7
8000fa2: 64fb str r3, [r7, #76] @ 0x4c
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
8000fa4: 2302 movs r3, #2
8000fa6: 653b str r3, [r7, #80] @ 0x50
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
8000fa8: 2302 movs r3, #2
8000faa: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000fac: f107 0314 add.w r3, r7, #20
8000fb0: 4618 mov r0, r3
8000fb2: f004 f877 bl 80050a4 <HAL_RCC_OscConfig>
8000fb6: 4603 mov r3, r0
8000fb8: 2b00 cmp r3, #0
8000fba: d001 beq.n 8000fc0 <SystemClock_Config+0x8c>
{
Error_Handler();
8000fbc: f000 fc04 bl 80017c8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000fc0: 230f movs r3, #15
8000fc2: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000fc4: 2303 movs r3, #3
8000fc6: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000fc8: 2300 movs r3, #0
8000fca: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000fcc: 2300 movs r3, #0
8000fce: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000fd0: 2300 movs r3, #0
8000fd2: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
8000fd4: 463b mov r3, r7
8000fd6: 2104 movs r1, #4
8000fd8: 4618 mov r0, r3
8000fda: f004 fc3f bl 800585c <HAL_RCC_ClockConfig>
8000fde: 4603 mov r3, r0
8000fe0: 2b00 cmp r3, #0
8000fe2: d001 beq.n 8000fe8 <SystemClock_Config+0xb4>
{
Error_Handler();
8000fe4: f000 fbf0 bl 80017c8 <Error_Handler>
}
/** Enable MSI Auto calibration
*/
HAL_RCCEx_EnableMSIPLLMode();
8000fe8: f005 f946 bl 8006278 <HAL_RCCEx_EnableMSIPLLMode>
}
8000fec: bf00 nop
8000fee: 3758 adds r7, #88 @ 0x58
8000ff0: 46bd mov sp, r7
8000ff2: bd80 pop {r7, pc}
8000ff4: 40021000 .word 0x40021000
08000ff8 <PeriphCommonClock_Config>:
/**
* @brief Peripherals Common Clock Configuration
* @retval None
*/
void PeriphCommonClock_Config(void)
{
8000ff8: b580 push {r7, lr}
8000ffa: b0a2 sub sp, #136 @ 0x88
8000ffc: af00 add r7, sp, #0
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000ffe: 463b mov r3, r7
8001000: 2288 movs r2, #136 @ 0x88
8001002: 2100 movs r1, #0
8001004: 4618 mov r0, r3
8001006: f00b f982 bl 800c30e <memset>
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC;
800100a: f44f 43c0 mov.w r3, #24576 @ 0x6000
800100e: 603b str r3, [r7, #0]
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
8001010: f04f 5380 mov.w r3, #268435456 @ 0x10000000
8001014: 67bb str r3, [r7, #120] @ 0x78
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
8001016: f04f 6380 mov.w r3, #67108864 @ 0x4000000
800101a: 66fb str r3, [r7, #108] @ 0x6c
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
800101c: 2301 movs r3, #1
800101e: 607b str r3, [r7, #4]
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
8001020: 2301 movs r3, #1
8001022: 60bb str r3, [r7, #8]
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
8001024: 2318 movs r3, #24
8001026: 60fb str r3, [r7, #12]
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
8001028: 2307 movs r3, #7
800102a: 613b str r3, [r7, #16]
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
800102c: 2302 movs r3, #2
800102e: 617b str r3, [r7, #20]
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
8001030: 2302 movs r3, #2
8001032: 61bb str r3, [r7, #24]
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK;
8001034: f04f 7388 mov.w r3, #17825792 @ 0x1100000
8001038: 61fb str r3, [r7, #28]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
800103a: 463b mov r3, r7
800103c: 4618 mov r0, r3
800103e: f004 fe31 bl 8005ca4 <HAL_RCCEx_PeriphCLKConfig>
8001042: 4603 mov r3, r0
8001044: 2b00 cmp r3, #0
8001046: d001 beq.n 800104c <PeriphCommonClock_Config+0x54>
{
Error_Handler();
8001048: f000 fbbe bl 80017c8 <Error_Handler>
}
}
800104c: bf00 nop
800104e: 3788 adds r7, #136 @ 0x88
8001050: 46bd mov sp, r7
8001052: bd80 pop {r7, pc}
08001054 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8001054: b580 push {r7, lr}
8001056: b08a sub sp, #40 @ 0x28
8001058: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
800105a: f107 031c add.w r3, r7, #28
800105e: 2200 movs r2, #0
8001060: 601a str r2, [r3, #0]
8001062: 605a str r2, [r3, #4]
8001064: 609a str r2, [r3, #8]
ADC_ChannelConfTypeDef sConfig = {0};
8001066: 1d3b adds r3, r7, #4
8001068: 2200 movs r2, #0
800106a: 601a str r2, [r3, #0]
800106c: 605a str r2, [r3, #4]
800106e: 609a str r2, [r3, #8]
8001070: 60da str r2, [r3, #12]
8001072: 611a str r2, [r3, #16]
8001074: 615a str r2, [r3, #20]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8001076: 4b2f ldr r3, [pc, #188] @ (8001134 <MX_ADC1_Init+0xe0>)
8001078: 4a2f ldr r2, [pc, #188] @ (8001138 <MX_ADC1_Init+0xe4>)
800107a: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
800107c: 4b2d ldr r3, [pc, #180] @ (8001134 <MX_ADC1_Init+0xe0>)
800107e: 2200 movs r2, #0
8001080: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8001082: 4b2c ldr r3, [pc, #176] @ (8001134 <MX_ADC1_Init+0xe0>)
8001084: 2200 movs r2, #0
8001086: 609a str r2, [r3, #8]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001088: 4b2a ldr r3, [pc, #168] @ (8001134 <MX_ADC1_Init+0xe0>)
800108a: 2200 movs r2, #0
800108c: 60da str r2, [r3, #12]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
800108e: 4b29 ldr r3, [pc, #164] @ (8001134 <MX_ADC1_Init+0xe0>)
8001090: 2200 movs r2, #0
8001092: 611a str r2, [r3, #16]
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8001094: 4b27 ldr r3, [pc, #156] @ (8001134 <MX_ADC1_Init+0xe0>)
8001096: 2204 movs r2, #4
8001098: 615a str r2, [r3, #20]
hadc1.Init.LowPowerAutoWait = DISABLE;
800109a: 4b26 ldr r3, [pc, #152] @ (8001134 <MX_ADC1_Init+0xe0>)
800109c: 2200 movs r2, #0
800109e: 761a strb r2, [r3, #24]
hadc1.Init.ContinuousConvMode = DISABLE;
80010a0: 4b24 ldr r3, [pc, #144] @ (8001134 <MX_ADC1_Init+0xe0>)
80010a2: 2200 movs r2, #0
80010a4: 765a strb r2, [r3, #25]
hadc1.Init.NbrOfConversion = 1;
80010a6: 4b23 ldr r3, [pc, #140] @ (8001134 <MX_ADC1_Init+0xe0>)
80010a8: 2201 movs r2, #1
80010aa: 61da str r2, [r3, #28]
hadc1.Init.DiscontinuousConvMode = DISABLE;
80010ac: 4b21 ldr r3, [pc, #132] @ (8001134 <MX_ADC1_Init+0xe0>)
80010ae: 2200 movs r2, #0
80010b0: f883 2020 strb.w r2, [r3, #32]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80010b4: 4b1f ldr r3, [pc, #124] @ (8001134 <MX_ADC1_Init+0xe0>)
80010b6: 2200 movs r2, #0
80010b8: 629a str r2, [r3, #40] @ 0x28
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
80010ba: 4b1e ldr r3, [pc, #120] @ (8001134 <MX_ADC1_Init+0xe0>)
80010bc: 2200 movs r2, #0
80010be: 62da str r2, [r3, #44] @ 0x2c
hadc1.Init.DMAContinuousRequests = DISABLE;
80010c0: 4b1c ldr r3, [pc, #112] @ (8001134 <MX_ADC1_Init+0xe0>)
80010c2: 2200 movs r2, #0
80010c4: f883 2030 strb.w r2, [r3, #48] @ 0x30
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
80010c8: 4b1a ldr r3, [pc, #104] @ (8001134 <MX_ADC1_Init+0xe0>)
80010ca: 2200 movs r2, #0
80010cc: 635a str r2, [r3, #52] @ 0x34
hadc1.Init.OversamplingMode = DISABLE;
80010ce: 4b19 ldr r3, [pc, #100] @ (8001134 <MX_ADC1_Init+0xe0>)
80010d0: 2200 movs r2, #0
80010d2: f883 2038 strb.w r2, [r3, #56] @ 0x38
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80010d6: 4817 ldr r0, [pc, #92] @ (8001134 <MX_ADC1_Init+0xe0>)
80010d8: f001 f9d8 bl 800248c <HAL_ADC_Init>
80010dc: 4603 mov r3, r0
80010de: 2b00 cmp r3, #0
80010e0: d001 beq.n 80010e6 <MX_ADC1_Init+0x92>
{
Error_Handler();
80010e2: f000 fb71 bl 80017c8 <Error_Handler>
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
80010e6: 2300 movs r3, #0
80010e8: 61fb str r3, [r7, #28]
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
80010ea: f107 031c add.w r3, r7, #28
80010ee: 4619 mov r1, r3
80010f0: 4810 ldr r0, [pc, #64] @ (8001134 <MX_ADC1_Init+0xe0>)
80010f2: f001 ff33 bl 8002f5c <HAL_ADCEx_MultiModeConfigChannel>
80010f6: 4603 mov r3, r0
80010f8: 2b00 cmp r3, #0
80010fa: d001 beq.n 8001100 <MX_ADC1_Init+0xac>
{
Error_Handler();
80010fc: f000 fb64 bl 80017c8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_14;
8001100: 4b0e ldr r3, [pc, #56] @ (800113c <MX_ADC1_Init+0xe8>)
8001102: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
8001104: 2306 movs r3, #6
8001106: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
8001108: 2300 movs r3, #0
800110a: 60fb str r3, [r7, #12]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
800110c: 237f movs r3, #127 @ 0x7f
800110e: 613b str r3, [r7, #16]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8001110: 2304 movs r3, #4
8001112: 617b str r3, [r7, #20]
sConfig.Offset = 0;
8001114: 2300 movs r3, #0
8001116: 61bb str r3, [r7, #24]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001118: 1d3b adds r3, r7, #4
800111a: 4619 mov r1, r3
800111c: 4805 ldr r0, [pc, #20] @ (8001134 <MX_ADC1_Init+0xe0>)
800111e: f001 fb05 bl 800272c <HAL_ADC_ConfigChannel>
8001122: 4603 mov r3, r0
8001124: 2b00 cmp r3, #0
8001126: d001 beq.n 800112c <MX_ADC1_Init+0xd8>
{
Error_Handler();
8001128: f000 fb4e bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
800112c: bf00 nop
800112e: 3728 adds r7, #40 @ 0x28
8001130: 46bd mov sp, r7
8001132: bd80 pop {r7, pc}
8001134: 2000031c .word 0x2000031c
8001138: 50040000 .word 0x50040000
800113c: 3ac04000 .word 0x3ac04000
08001140 <MX_DFSDM1_Init>:
* @brief DFSDM1 Initialization Function
* @param None
* @retval None
*/
static void MX_DFSDM1_Init(void)
{
8001140: b580 push {r7, lr}
8001142: af00 add r7, sp, #0
/* USER CODE END DFSDM1_Init 0 */
/* USER CODE BEGIN DFSDM1_Init 1 */
/* USER CODE END DFSDM1_Init 1 */
hdfsdm1_channel1.Instance = DFSDM1_Channel1;
8001144: 4b18 ldr r3, [pc, #96] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001146: 4a19 ldr r2, [pc, #100] @ (80011ac <MX_DFSDM1_Init+0x6c>)
8001148: 601a str r2, [r3, #0]
hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;
800114a: 4b17 ldr r3, [pc, #92] @ (80011a8 <MX_DFSDM1_Init+0x68>)
800114c: 2201 movs r2, #1
800114e: 711a strb r2, [r3, #4]
hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM;
8001150: 4b15 ldr r3, [pc, #84] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001152: 2200 movs r2, #0
8001154: 609a str r2, [r3, #8]
hdfsdm1_channel1.Init.OutputClock.Divider = 2;
8001156: 4b14 ldr r3, [pc, #80] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001158: 2202 movs r2, #2
800115a: 60da str r2, [r3, #12]
hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
800115c: 4b12 ldr r3, [pc, #72] @ (80011a8 <MX_DFSDM1_Init+0x68>)
800115e: 2200 movs r2, #0
8001160: 611a str r2, [r3, #16]
hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
8001162: 4b11 ldr r3, [pc, #68] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001164: 2200 movs r2, #0
8001166: 615a str r2, [r3, #20]
hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;
8001168: 4b0f ldr r3, [pc, #60] @ (80011a8 <MX_DFSDM1_Init+0x68>)
800116a: f44f 7280 mov.w r2, #256 @ 0x100
800116e: 619a str r2, [r3, #24]
hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
8001170: 4b0d ldr r3, [pc, #52] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001172: 2200 movs r2, #0
8001174: 61da str r2, [r3, #28]
hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
8001176: 4b0c ldr r3, [pc, #48] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001178: 2204 movs r2, #4
800117a: 621a str r2, [r3, #32]
hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
800117c: 4b0a ldr r3, [pc, #40] @ (80011a8 <MX_DFSDM1_Init+0x68>)
800117e: 2200 movs r2, #0
8001180: 625a str r2, [r3, #36] @ 0x24
hdfsdm1_channel1.Init.Awd.Oversampling = 1;
8001182: 4b09 ldr r3, [pc, #36] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001184: 2201 movs r2, #1
8001186: 629a str r2, [r3, #40] @ 0x28
hdfsdm1_channel1.Init.Offset = 0;
8001188: 4b07 ldr r3, [pc, #28] @ (80011a8 <MX_DFSDM1_Init+0x68>)
800118a: 2200 movs r2, #0
800118c: 62da str r2, [r3, #44] @ 0x2c
hdfsdm1_channel1.Init.RightBitShift = 0x00;
800118e: 4b06 ldr r3, [pc, #24] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001190: 2200 movs r2, #0
8001192: 631a str r2, [r3, #48] @ 0x30
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)
8001194: 4804 ldr r0, [pc, #16] @ (80011a8 <MX_DFSDM1_Init+0x68>)
8001196: f002 f8a3 bl 80032e0 <HAL_DFSDM_ChannelInit>
800119a: 4603 mov r3, r0
800119c: 2b00 cmp r3, #0
800119e: d001 beq.n 80011a4 <MX_DFSDM1_Init+0x64>
{
Error_Handler();
80011a0: f000 fb12 bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN DFSDM1_Init 2 */
/* USER CODE END DFSDM1_Init 2 */
}
80011a4: bf00 nop
80011a6: bd80 pop {r7, pc}
80011a8: 20000380 .word 0x20000380
80011ac: 40016020 .word 0x40016020
080011b0 <MX_I2C2_Init>:
* @brief I2C2 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C2_Init(void)
{
80011b0: b580 push {r7, lr}
80011b2: af00 add r7, sp, #0
/* USER CODE END I2C2_Init 0 */
/* USER CODE BEGIN I2C2_Init 1 */
/* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2;
80011b4: 4b1b ldr r3, [pc, #108] @ (8001224 <MX_I2C2_Init+0x74>)
80011b6: 4a1c ldr r2, [pc, #112] @ (8001228 <MX_I2C2_Init+0x78>)
80011b8: 601a str r2, [r3, #0]
hi2c2.Init.Timing = 0x10D19CE4;
80011ba: 4b1a ldr r3, [pc, #104] @ (8001224 <MX_I2C2_Init+0x74>)
80011bc: 4a1b ldr r2, [pc, #108] @ (800122c <MX_I2C2_Init+0x7c>)
80011be: 605a str r2, [r3, #4]
hi2c2.Init.OwnAddress1 = 0;
80011c0: 4b18 ldr r3, [pc, #96] @ (8001224 <MX_I2C2_Init+0x74>)
80011c2: 2200 movs r2, #0
80011c4: 609a str r2, [r3, #8]
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
80011c6: 4b17 ldr r3, [pc, #92] @ (8001224 <MX_I2C2_Init+0x74>)
80011c8: 2201 movs r2, #1
80011ca: 60da str r2, [r3, #12]
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80011cc: 4b15 ldr r3, [pc, #84] @ (8001224 <MX_I2C2_Init+0x74>)
80011ce: 2200 movs r2, #0
80011d0: 611a str r2, [r3, #16]
hi2c2.Init.OwnAddress2 = 0;
80011d2: 4b14 ldr r3, [pc, #80] @ (8001224 <MX_I2C2_Init+0x74>)
80011d4: 2200 movs r2, #0
80011d6: 615a str r2, [r3, #20]
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
80011d8: 4b12 ldr r3, [pc, #72] @ (8001224 <MX_I2C2_Init+0x74>)
80011da: 2200 movs r2, #0
80011dc: 619a str r2, [r3, #24]
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
80011de: 4b11 ldr r3, [pc, #68] @ (8001224 <MX_I2C2_Init+0x74>)
80011e0: 2200 movs r2, #0
80011e2: 61da str r2, [r3, #28]
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80011e4: 4b0f ldr r3, [pc, #60] @ (8001224 <MX_I2C2_Init+0x74>)
80011e6: 2200 movs r2, #0
80011e8: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
80011ea: 480e ldr r0, [pc, #56] @ (8001224 <MX_I2C2_Init+0x74>)
80011ec: f002 fb69 bl 80038c2 <HAL_I2C_Init>
80011f0: 4603 mov r3, r0
80011f2: 2b00 cmp r3, #0
80011f4: d001 beq.n 80011fa <MX_I2C2_Init+0x4a>
{
Error_Handler();
80011f6: f000 fae7 bl 80017c8 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
80011fa: 2100 movs r1, #0
80011fc: 4809 ldr r0, [pc, #36] @ (8001224 <MX_I2C2_Init+0x74>)
80011fe: f002 fbfb bl 80039f8 <HAL_I2CEx_ConfigAnalogFilter>
8001202: 4603 mov r3, r0
8001204: 2b00 cmp r3, #0
8001206: d001 beq.n 800120c <MX_I2C2_Init+0x5c>
{
Error_Handler();
8001208: f000 fade bl 80017c8 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
800120c: 2100 movs r1, #0
800120e: 4805 ldr r0, [pc, #20] @ (8001224 <MX_I2C2_Init+0x74>)
8001210: f002 fc3d bl 8003a8e <HAL_I2CEx_ConfigDigitalFilter>
8001214: 4603 mov r3, r0
8001216: 2b00 cmp r3, #0
8001218: d001 beq.n 800121e <MX_I2C2_Init+0x6e>
{
Error_Handler();
800121a: f000 fad5 bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN I2C2_Init 2 */
/* USER CODE END I2C2_Init 2 */
}
800121e: bf00 nop
8001220: bd80 pop {r7, pc}
8001222: bf00 nop
8001224: 200003b8 .word 0x200003b8
8001228: 40005800 .word 0x40005800
800122c: 10d19ce4 .word 0x10d19ce4
08001230 <MX_QUADSPI_Init>:
* @brief QUADSPI Initialization Function
* @param None
* @retval None
*/
static void MX_QUADSPI_Init(void)
{
8001230: b580 push {r7, lr}
8001232: af00 add r7, sp, #0
/* USER CODE BEGIN QUADSPI_Init 1 */
/* USER CODE END QUADSPI_Init 1 */
/* QUADSPI parameter configuration*/
hqspi.Instance = QUADSPI;
8001234: 4b0f ldr r3, [pc, #60] @ (8001274 <MX_QUADSPI_Init+0x44>)
8001236: 4a10 ldr r2, [pc, #64] @ (8001278 <MX_QUADSPI_Init+0x48>)
8001238: 601a str r2, [r3, #0]
hqspi.Init.ClockPrescaler = 2;
800123a: 4b0e ldr r3, [pc, #56] @ (8001274 <MX_QUADSPI_Init+0x44>)
800123c: 2202 movs r2, #2
800123e: 605a str r2, [r3, #4]
hqspi.Init.FifoThreshold = 4;
8001240: 4b0c ldr r3, [pc, #48] @ (8001274 <MX_QUADSPI_Init+0x44>)
8001242: 2204 movs r2, #4
8001244: 609a str r2, [r3, #8]
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
8001246: 4b0b ldr r3, [pc, #44] @ (8001274 <MX_QUADSPI_Init+0x44>)
8001248: 2210 movs r2, #16
800124a: 60da str r2, [r3, #12]
hqspi.Init.FlashSize = 23;
800124c: 4b09 ldr r3, [pc, #36] @ (8001274 <MX_QUADSPI_Init+0x44>)
800124e: 2217 movs r2, #23
8001250: 611a str r2, [r3, #16]
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
8001252: 4b08 ldr r3, [pc, #32] @ (8001274 <MX_QUADSPI_Init+0x44>)
8001254: 2200 movs r2, #0
8001256: 615a str r2, [r3, #20]
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
8001258: 4b06 ldr r3, [pc, #24] @ (8001274 <MX_QUADSPI_Init+0x44>)
800125a: 2200 movs r2, #0
800125c: 619a str r2, [r3, #24]
if (HAL_QSPI_Init(&hqspi) != HAL_OK)
800125e: 4805 ldr r0, [pc, #20] @ (8001274 <MX_QUADSPI_Init+0x44>)
8001260: f003 fe64 bl 8004f2c <HAL_QSPI_Init>
8001264: 4603 mov r3, r0
8001266: 2b00 cmp r3, #0
8001268: d001 beq.n 800126e <MX_QUADSPI_Init+0x3e>
{
Error_Handler();
800126a: f000 faad bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN QUADSPI_Init 2 */
/* USER CODE END QUADSPI_Init 2 */
}
800126e: bf00 nop
8001270: bd80 pop {r7, pc}
8001272: bf00 nop
8001274: 2000040c .word 0x2000040c
8001278: a0001000 .word 0xa0001000
0800127c <MX_SPI3_Init>:
* @brief SPI3 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI3_Init(void)
{
800127c: b580 push {r7, lr}
800127e: af00 add r7, sp, #0
/* USER CODE BEGIN SPI3_Init 1 */
/* USER CODE END SPI3_Init 1 */
/* SPI3 parameter configuration*/
hspi3.Instance = SPI3;
8001280: 4b1b ldr r3, [pc, #108] @ (80012f0 <MX_SPI3_Init+0x74>)
8001282: 4a1c ldr r2, [pc, #112] @ (80012f4 <MX_SPI3_Init+0x78>)
8001284: 601a str r2, [r3, #0]
hspi3.Init.Mode = SPI_MODE_MASTER;
8001286: 4b1a ldr r3, [pc, #104] @ (80012f0 <MX_SPI3_Init+0x74>)
8001288: f44f 7282 mov.w r2, #260 @ 0x104
800128c: 605a str r2, [r3, #4]
hspi3.Init.Direction = SPI_DIRECTION_2LINES;
800128e: 4b18 ldr r3, [pc, #96] @ (80012f0 <MX_SPI3_Init+0x74>)
8001290: 2200 movs r2, #0
8001292: 609a str r2, [r3, #8]
hspi3.Init.DataSize = SPI_DATASIZE_4BIT;
8001294: 4b16 ldr r3, [pc, #88] @ (80012f0 <MX_SPI3_Init+0x74>)
8001296: f44f 7240 mov.w r2, #768 @ 0x300
800129a: 60da str r2, [r3, #12]
hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
800129c: 4b14 ldr r3, [pc, #80] @ (80012f0 <MX_SPI3_Init+0x74>)
800129e: 2200 movs r2, #0
80012a0: 611a str r2, [r3, #16]
hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
80012a2: 4b13 ldr r3, [pc, #76] @ (80012f0 <MX_SPI3_Init+0x74>)
80012a4: 2200 movs r2, #0
80012a6: 615a str r2, [r3, #20]
hspi3.Init.NSS = SPI_NSS_SOFT;
80012a8: 4b11 ldr r3, [pc, #68] @ (80012f0 <MX_SPI3_Init+0x74>)
80012aa: f44f 7200 mov.w r2, #512 @ 0x200
80012ae: 619a str r2, [r3, #24]
hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80012b0: 4b0f ldr r3, [pc, #60] @ (80012f0 <MX_SPI3_Init+0x74>)
80012b2: 2200 movs r2, #0
80012b4: 61da str r2, [r3, #28]
hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
80012b6: 4b0e ldr r3, [pc, #56] @ (80012f0 <MX_SPI3_Init+0x74>)
80012b8: 2200 movs r2, #0
80012ba: 621a str r2, [r3, #32]
hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
80012bc: 4b0c ldr r3, [pc, #48] @ (80012f0 <MX_SPI3_Init+0x74>)
80012be: 2200 movs r2, #0
80012c0: 625a str r2, [r3, #36] @ 0x24
hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80012c2: 4b0b ldr r3, [pc, #44] @ (80012f0 <MX_SPI3_Init+0x74>)
80012c4: 2200 movs r2, #0
80012c6: 629a str r2, [r3, #40] @ 0x28
hspi3.Init.CRCPolynomial = 7;
80012c8: 4b09 ldr r3, [pc, #36] @ (80012f0 <MX_SPI3_Init+0x74>)
80012ca: 2207 movs r2, #7
80012cc: 62da str r2, [r3, #44] @ 0x2c
hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
80012ce: 4b08 ldr r3, [pc, #32] @ (80012f0 <MX_SPI3_Init+0x74>)
80012d0: 2200 movs r2, #0
80012d2: 631a str r2, [r3, #48] @ 0x30
hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
80012d4: 4b06 ldr r3, [pc, #24] @ (80012f0 <MX_SPI3_Init+0x74>)
80012d6: 2208 movs r2, #8
80012d8: 635a str r2, [r3, #52] @ 0x34
if (HAL_SPI_Init(&hspi3) != HAL_OK)
80012da: 4805 ldr r0, [pc, #20] @ (80012f0 <MX_SPI3_Init+0x74>)
80012dc: f005 f9ae bl 800663c <HAL_SPI_Init>
80012e0: 4603 mov r3, r0
80012e2: 2b00 cmp r3, #0
80012e4: d001 beq.n 80012ea <MX_SPI3_Init+0x6e>
{
Error_Handler();
80012e6: f000 fa6f bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN SPI3_Init 2 */
/* USER CODE END SPI3_Init 2 */
}
80012ea: bf00 nop
80012ec: bd80 pop {r7, pc}
80012ee: bf00 nop
80012f0: 20000450 .word 0x20000450
80012f4: 40003c00 .word 0x40003c00
080012f8 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
80012f8: b580 push {r7, lr}
80012fa: b08a sub sp, #40 @ 0x28
80012fc: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
80012fe: f107 031c add.w r3, r7, #28
8001302: 2200 movs r2, #0
8001304: 601a str r2, [r3, #0]
8001306: 605a str r2, [r3, #4]
8001308: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
800130a: 463b mov r3, r7
800130c: 2200 movs r2, #0
800130e: 601a str r2, [r3, #0]
8001310: 605a str r2, [r3, #4]
8001312: 609a str r2, [r3, #8]
8001314: 60da str r2, [r3, #12]
8001316: 611a str r2, [r3, #16]
8001318: 615a str r2, [r3, #20]
800131a: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
800131c: 4b22 ldr r3, [pc, #136] @ (80013a8 <MX_TIM2_Init+0xb0>)
800131e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8001322: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
8001324: 4b20 ldr r3, [pc, #128] @ (80013a8 <MX_TIM2_Init+0xb0>)
8001326: 2200 movs r2, #0
8001328: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_DOWN;
800132a: 4b1f ldr r3, [pc, #124] @ (80013a8 <MX_TIM2_Init+0xb0>)
800132c: 2210 movs r2, #16
800132e: 609a str r2, [r3, #8]
htim2.Init.Period = 1000;
8001330: 4b1d ldr r3, [pc, #116] @ (80013a8 <MX_TIM2_Init+0xb0>)
8001332: f44f 727a mov.w r2, #1000 @ 0x3e8
8001336: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001338: 4b1b ldr r3, [pc, #108] @ (80013a8 <MX_TIM2_Init+0xb0>)
800133a: 2200 movs r2, #0
800133c: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800133e: 4b1a ldr r3, [pc, #104] @ (80013a8 <MX_TIM2_Init+0xb0>)
8001340: 2200 movs r2, #0
8001342: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8001344: 4818 ldr r0, [pc, #96] @ (80013a8 <MX_TIM2_Init+0xb0>)
8001346: f005 fa73 bl 8006830 <HAL_TIM_PWM_Init>
800134a: 4603 mov r3, r0
800134c: 2b00 cmp r3, #0
800134e: d001 beq.n 8001354 <MX_TIM2_Init+0x5c>
{
Error_Handler();
8001350: f000 fa3a bl 80017c8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001354: 2300 movs r3, #0
8001356: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001358: 2300 movs r3, #0
800135a: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
800135c: f107 031c add.w r3, r7, #28
8001360: 4619 mov r1, r3
8001362: 4811 ldr r0, [pc, #68] @ (80013a8 <MX_TIM2_Init+0xb0>)
8001364: f006 f884 bl 8007470 <HAL_TIMEx_MasterConfigSynchronization>
8001368: 4603 mov r3, r0
800136a: 2b00 cmp r3, #0
800136c: d001 beq.n 8001372 <MX_TIM2_Init+0x7a>
{
Error_Handler();
800136e: f000 fa2b bl 80017c8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001372: 2360 movs r3, #96 @ 0x60
8001374: 603b str r3, [r7, #0]
sConfigOC.Pulse = 0;
8001376: 2300 movs r3, #0
8001378: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800137a: 2300 movs r3, #0
800137c: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
800137e: 2300 movs r3, #0
8001380: 613b str r3, [r7, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8001382: 463b mov r3, r7
8001384: 2200 movs r2, #0
8001386: 4619 mov r1, r3
8001388: 4807 ldr r0, [pc, #28] @ (80013a8 <MX_TIM2_Init+0xb0>)
800138a: f005 fbaf bl 8006aec <HAL_TIM_PWM_ConfigChannel>
800138e: 4603 mov r3, r0
8001390: 2b00 cmp r3, #0
8001392: d001 beq.n 8001398 <MX_TIM2_Init+0xa0>
{
Error_Handler();
8001394: f000 fa18 bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
8001398: 4803 ldr r0, [pc, #12] @ (80013a8 <MX_TIM2_Init+0xb0>)
800139a: f000 fc0d bl 8001bb8 <HAL_TIM_MspPostInit>
}
800139e: bf00 nop
80013a0: 3728 adds r7, #40 @ 0x28
80013a2: 46bd mov sp, r7
80013a4: bd80 pop {r7, pc}
80013a6: bf00 nop
80013a8: 200004b4 .word 0x200004b4
080013ac <MX_TIM7_Init>:
* @brief TIM7 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM7_Init(void)
{
80013ac: b580 push {r7, lr}
80013ae: b084 sub sp, #16
80013b0: af00 add r7, sp, #0
/* USER CODE BEGIN TIM7_Init 0 */
/* USER CODE END TIM7_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
80013b2: 1d3b adds r3, r7, #4
80013b4: 2200 movs r2, #0
80013b6: 601a str r2, [r3, #0]
80013b8: 605a str r2, [r3, #4]
80013ba: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM7_Init 1 */
/* USER CODE END TIM7_Init 1 */
htim7.Instance = TIM7;
80013bc: 4b14 ldr r3, [pc, #80] @ (8001410 <MX_TIM7_Init+0x64>)
80013be: 4a15 ldr r2, [pc, #84] @ (8001414 <MX_TIM7_Init+0x68>)
80013c0: 601a str r2, [r3, #0]
htim7.Init.Prescaler = 0;
80013c2: 4b13 ldr r3, [pc, #76] @ (8001410 <MX_TIM7_Init+0x64>)
80013c4: 2200 movs r2, #0
80013c6: 605a str r2, [r3, #4]
htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
80013c8: 4b11 ldr r3, [pc, #68] @ (8001410 <MX_TIM7_Init+0x64>)
80013ca: 2200 movs r2, #0
80013cc: 609a str r2, [r3, #8]
htim7.Init.Period = 3300;
80013ce: 4b10 ldr r3, [pc, #64] @ (8001410 <MX_TIM7_Init+0x64>)
80013d0: f640 42e4 movw r2, #3300 @ 0xce4
80013d4: 60da str r2, [r3, #12]
htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80013d6: 4b0e ldr r3, [pc, #56] @ (8001410 <MX_TIM7_Init+0x64>)
80013d8: 2200 movs r2, #0
80013da: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
80013dc: 480c ldr r0, [pc, #48] @ (8001410 <MX_TIM7_Init+0x64>)
80013de: f005 f9d0 bl 8006782 <HAL_TIM_Base_Init>
80013e2: 4603 mov r3, r0
80013e4: 2b00 cmp r3, #0
80013e6: d001 beq.n 80013ec <MX_TIM7_Init+0x40>
{
Error_Handler();
80013e8: f000 f9ee bl 80017c8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80013ec: 2300 movs r3, #0
80013ee: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80013f0: 2300 movs r3, #0
80013f2: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
80013f4: 1d3b adds r3, r7, #4
80013f6: 4619 mov r1, r3
80013f8: 4805 ldr r0, [pc, #20] @ (8001410 <MX_TIM7_Init+0x64>)
80013fa: f006 f839 bl 8007470 <HAL_TIMEx_MasterConfigSynchronization>
80013fe: 4603 mov r3, r0
8001400: 2b00 cmp r3, #0
8001402: d001 beq.n 8001408 <MX_TIM7_Init+0x5c>
{
Error_Handler();
8001404: f000 f9e0 bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN TIM7_Init 2 */
/* USER CODE END TIM7_Init 2 */
}
8001408: bf00 nop
800140a: 3710 adds r7, #16
800140c: 46bd mov sp, r7
800140e: bd80 pop {r7, pc}
8001410: 20000500 .word 0x20000500
8001414: 40001400 .word 0x40001400
08001418 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8001418: b580 push {r7, lr}
800141a: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
800141c: 4b14 ldr r3, [pc, #80] @ (8001470 <MX_USART1_UART_Init+0x58>)
800141e: 4a15 ldr r2, [pc, #84] @ (8001474 <MX_USART1_UART_Init+0x5c>)
8001420: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8001422: 4b13 ldr r3, [pc, #76] @ (8001470 <MX_USART1_UART_Init+0x58>)
8001424: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8001428: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
800142a: 4b11 ldr r3, [pc, #68] @ (8001470 <MX_USART1_UART_Init+0x58>)
800142c: 2200 movs r2, #0
800142e: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8001430: 4b0f ldr r3, [pc, #60] @ (8001470 <MX_USART1_UART_Init+0x58>)
8001432: 2200 movs r2, #0
8001434: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8001436: 4b0e ldr r3, [pc, #56] @ (8001470 <MX_USART1_UART_Init+0x58>)
8001438: 2200 movs r2, #0
800143a: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
800143c: 4b0c ldr r3, [pc, #48] @ (8001470 <MX_USART1_UART_Init+0x58>)
800143e: 220c movs r2, #12
8001440: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8001442: 4b0b ldr r3, [pc, #44] @ (8001470 <MX_USART1_UART_Init+0x58>)
8001444: 2200 movs r2, #0
8001446: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8001448: 4b09 ldr r3, [pc, #36] @ (8001470 <MX_USART1_UART_Init+0x58>)
800144a: 2200 movs r2, #0
800144c: 61da str r2, [r3, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
800144e: 4b08 ldr r3, [pc, #32] @ (8001470 <MX_USART1_UART_Init+0x58>)
8001450: 2200 movs r2, #0
8001452: 621a str r2, [r3, #32]
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8001454: 4b06 ldr r3, [pc, #24] @ (8001470 <MX_USART1_UART_Init+0x58>)
8001456: 2200 movs r2, #0
8001458: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart1) != HAL_OK)
800145a: 4805 ldr r0, [pc, #20] @ (8001470 <MX_USART1_UART_Init+0x58>)
800145c: f006 f8ae bl 80075bc <HAL_UART_Init>
8001460: 4603 mov r3, r0
8001462: 2b00 cmp r3, #0
8001464: d001 beq.n 800146a <MX_USART1_UART_Init+0x52>
{
Error_Handler();
8001466: f000 f9af bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
800146a: bf00 nop
800146c: bd80 pop {r7, pc}
800146e: bf00 nop
8001470: 2000054c .word 0x2000054c
8001474: 40013800 .word 0x40013800
08001478 <MX_USART3_UART_Init>:
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static void MX_USART3_UART_Init(void)
{
8001478: b580 push {r7, lr}
800147a: af00 add r7, sp, #0
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
800147c: 4b14 ldr r3, [pc, #80] @ (80014d0 <MX_USART3_UART_Init+0x58>)
800147e: 4a15 ldr r2, [pc, #84] @ (80014d4 <MX_USART3_UART_Init+0x5c>)
8001480: 601a str r2, [r3, #0]
huart3.Init.BaudRate = 115200;
8001482: 4b13 ldr r3, [pc, #76] @ (80014d0 <MX_USART3_UART_Init+0x58>)
8001484: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8001488: 605a str r2, [r3, #4]
huart3.Init.WordLength = UART_WORDLENGTH_8B;
800148a: 4b11 ldr r3, [pc, #68] @ (80014d0 <MX_USART3_UART_Init+0x58>)
800148c: 2200 movs r2, #0
800148e: 609a str r2, [r3, #8]
huart3.Init.StopBits = UART_STOPBITS_1;
8001490: 4b0f ldr r3, [pc, #60] @ (80014d0 <MX_USART3_UART_Init+0x58>)
8001492: 2200 movs r2, #0
8001494: 60da str r2, [r3, #12]
huart3.Init.Parity = UART_PARITY_NONE;
8001496: 4b0e ldr r3, [pc, #56] @ (80014d0 <MX_USART3_UART_Init+0x58>)
8001498: 2200 movs r2, #0
800149a: 611a str r2, [r3, #16]
huart3.Init.Mode = UART_MODE_TX_RX;
800149c: 4b0c ldr r3, [pc, #48] @ (80014d0 <MX_USART3_UART_Init+0x58>)
800149e: 220c movs r2, #12
80014a0: 615a str r2, [r3, #20]
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80014a2: 4b0b ldr r3, [pc, #44] @ (80014d0 <MX_USART3_UART_Init+0x58>)
80014a4: 2200 movs r2, #0
80014a6: 619a str r2, [r3, #24]
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
80014a8: 4b09 ldr r3, [pc, #36] @ (80014d0 <MX_USART3_UART_Init+0x58>)
80014aa: 2200 movs r2, #0
80014ac: 61da str r2, [r3, #28]
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80014ae: 4b08 ldr r3, [pc, #32] @ (80014d0 <MX_USART3_UART_Init+0x58>)
80014b0: 2200 movs r2, #0
80014b2: 621a str r2, [r3, #32]
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80014b4: 4b06 ldr r3, [pc, #24] @ (80014d0 <MX_USART3_UART_Init+0x58>)
80014b6: 2200 movs r2, #0
80014b8: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart3) != HAL_OK)
80014ba: 4805 ldr r0, [pc, #20] @ (80014d0 <MX_USART3_UART_Init+0x58>)
80014bc: f006 f87e bl 80075bc <HAL_UART_Init>
80014c0: 4603 mov r3, r0
80014c2: 2b00 cmp r3, #0
80014c4: d001 beq.n 80014ca <MX_USART3_UART_Init+0x52>
{
Error_Handler();
80014c6: f000 f97f bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
80014ca: bf00 nop
80014cc: bd80 pop {r7, pc}
80014ce: bf00 nop
80014d0: 200005d4 .word 0x200005d4
80014d4: 40004800 .word 0x40004800
080014d8 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80014d8: b580 push {r7, lr}
80014da: b08a sub sp, #40 @ 0x28
80014dc: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80014de: f107 0314 add.w r3, r7, #20
80014e2: 2200 movs r2, #0
80014e4: 601a str r2, [r3, #0]
80014e6: 605a str r2, [r3, #4]
80014e8: 609a str r2, [r3, #8]
80014ea: 60da str r2, [r3, #12]
80014ec: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
80014ee: 4bb1 ldr r3, [pc, #708] @ (80017b4 <MX_GPIO_Init+0x2dc>)
80014f0: 6cdb ldr r3, [r3, #76] @ 0x4c
80014f2: 4ab0 ldr r2, [pc, #704] @ (80017b4 <MX_GPIO_Init+0x2dc>)
80014f4: f043 0310 orr.w r3, r3, #16
80014f8: 64d3 str r3, [r2, #76] @ 0x4c
80014fa: 4bae ldr r3, [pc, #696] @ (80017b4 <MX_GPIO_Init+0x2dc>)
80014fc: 6cdb ldr r3, [r3, #76] @ 0x4c
80014fe: f003 0310 and.w r3, r3, #16
8001502: 613b str r3, [r7, #16]
8001504: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001506: 4bab ldr r3, [pc, #684] @ (80017b4 <MX_GPIO_Init+0x2dc>)
8001508: 6cdb ldr r3, [r3, #76] @ 0x4c
800150a: 4aaa ldr r2, [pc, #680] @ (80017b4 <MX_GPIO_Init+0x2dc>)
800150c: f043 0304 orr.w r3, r3, #4
8001510: 64d3 str r3, [r2, #76] @ 0x4c
8001512: 4ba8 ldr r3, [pc, #672] @ (80017b4 <MX_GPIO_Init+0x2dc>)
8001514: 6cdb ldr r3, [r3, #76] @ 0x4c
8001516: f003 0304 and.w r3, r3, #4
800151a: 60fb str r3, [r7, #12]
800151c: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800151e: 4ba5 ldr r3, [pc, #660] @ (80017b4 <MX_GPIO_Init+0x2dc>)
8001520: 6cdb ldr r3, [r3, #76] @ 0x4c
8001522: 4aa4 ldr r2, [pc, #656] @ (80017b4 <MX_GPIO_Init+0x2dc>)
8001524: f043 0301 orr.w r3, r3, #1
8001528: 64d3 str r3, [r2, #76] @ 0x4c
800152a: 4ba2 ldr r3, [pc, #648] @ (80017b4 <MX_GPIO_Init+0x2dc>)
800152c: 6cdb ldr r3, [r3, #76] @ 0x4c
800152e: f003 0301 and.w r3, r3, #1
8001532: 60bb str r3, [r7, #8]
8001534: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001536: 4b9f ldr r3, [pc, #636] @ (80017b4 <MX_GPIO_Init+0x2dc>)
8001538: 6cdb ldr r3, [r3, #76] @ 0x4c
800153a: 4a9e ldr r2, [pc, #632] @ (80017b4 <MX_GPIO_Init+0x2dc>)
800153c: f043 0302 orr.w r3, r3, #2
8001540: 64d3 str r3, [r2, #76] @ 0x4c
8001542: 4b9c ldr r3, [pc, #624] @ (80017b4 <MX_GPIO_Init+0x2dc>)
8001544: 6cdb ldr r3, [r3, #76] @ 0x4c
8001546: f003 0302 and.w r3, r3, #2
800154a: 607b str r3, [r7, #4]
800154c: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOD_CLK_ENABLE();
800154e: 4b99 ldr r3, [pc, #612] @ (80017b4 <MX_GPIO_Init+0x2dc>)
8001550: 6cdb ldr r3, [r3, #76] @ 0x4c
8001552: 4a98 ldr r2, [pc, #608] @ (80017b4 <MX_GPIO_Init+0x2dc>)
8001554: f043 0308 orr.w r3, r3, #8
8001558: 64d3 str r3, [r2, #76] @ 0x4c
800155a: 4b96 ldr r3, [pc, #600] @ (80017b4 <MX_GPIO_Init+0x2dc>)
800155c: 6cdb ldr r3, [r3, #76] @ 0x4c
800155e: f003 0308 and.w r3, r3, #8
8001562: 603b str r3, [r7, #0]
8001564: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin, GPIO_PIN_RESET);
8001566: 2200 movs r2, #0
8001568: f44f 718a mov.w r1, #276 @ 0x114
800156c: 4892 ldr r0, [pc, #584] @ (80017b8 <MX_GPIO_Init+0x2e0>)
800156e: f002 f96d bl 800384c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, Led_LCD_Pin|D4_LCD_Pin|D7_LCD_Pin|SPBTLE_RF_RST_Pin
8001572: 2200 movs r2, #0
8001574: f248 111c movw r1, #33052 @ 0x811c
8001578: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800157c: f002 f966 bl 800384c <HAL_GPIO_WritePin>
|E_LCD_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, D6_LCD_Pin|RS_LCD_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin
8001580: 2200 movs r2, #0
8001582: f24f 0116 movw r1, #61462 @ 0xf016
8001586: 488d ldr r0, [pc, #564] @ (80017bc <MX_GPIO_Init+0x2e4>)
8001588: f002 f960 bl 800384c <HAL_GPIO_WritePin>
|LED2_Pin|SPSGRF_915_SDN_Pin|D5_LCD_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin, GPIO_PIN_RESET);
800158c: 2200 movs r2, #0
800158e: f241 0181 movw r1, #4225 @ 0x1081
8001592: 488b ldr r0, [pc, #556] @ (80017c0 <MX_GPIO_Init+0x2e8>)
8001594: f002 f95a bl 800384c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(SPBTLE_RF_SPI3_CSN_GPIO_Port, SPBTLE_RF_SPI3_CSN_Pin, GPIO_PIN_SET);
8001598: 2201 movs r2, #1
800159a: f44f 5100 mov.w r1, #8192 @ 0x2000
800159e: 4888 ldr r0, [pc, #544] @ (80017c0 <MX_GPIO_Init+0x2e8>)
80015a0: f002 f954 bl 800384c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin, GPIO_PIN_RESET);
80015a4: 2200 movs r2, #0
80015a6: f44f 7110 mov.w r1, #576 @ 0x240
80015aa: 4886 ldr r0, [pc, #536] @ (80017c4 <MX_GPIO_Init+0x2ec>)
80015ac: f002 f94e bl 800384c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(SPSGRF_915_SPI3_CSN_GPIO_Port, SPSGRF_915_SPI3_CSN_Pin, GPIO_PIN_SET);
80015b0: 2201 movs r2, #1
80015b2: 2120 movs r1, #32
80015b4: 4881 ldr r0, [pc, #516] @ (80017bc <MX_GPIO_Init+0x2e4>)
80015b6: f002 f949 bl 800384c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(ISM43362_SPI3_CSN_GPIO_Port, ISM43362_SPI3_CSN_Pin, GPIO_PIN_SET);
80015ba: 2201 movs r2, #1
80015bc: 2101 movs r1, #1
80015be: 487e ldr r0, [pc, #504] @ (80017b8 <MX_GPIO_Init+0x2e0>)
80015c0: f002 f944 bl 800384c <HAL_GPIO_WritePin>
/*Configure GPIO pins : M24SR64_Y_RF_DISABLE_Pin M24SR64_Y_GPO_Pin ISM43362_RST_Pin ISM43362_SPI3_CSN_Pin */
GPIO_InitStruct.Pin = M24SR64_Y_RF_DISABLE_Pin|M24SR64_Y_GPO_Pin|ISM43362_RST_Pin|ISM43362_SPI3_CSN_Pin;
80015c4: f240 1315 movw r3, #277 @ 0x115
80015c8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80015ca: 2301 movs r3, #1
80015cc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80015ce: 2300 movs r3, #0
80015d0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80015d2: 2300 movs r3, #0
80015d4: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
80015d6: f107 0314 add.w r3, r7, #20
80015da: 4619 mov r1, r3
80015dc: 4876 ldr r0, [pc, #472] @ (80017b8 <MX_GPIO_Init+0x2e0>)
80015de: f001 ff8b bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_FS_OVRCR_EXTI3_Pin SPSGRF_915_GPIO3_EXTI5_Pin SPBTLE_RF_IRQ_EXTI6_Pin ISM43362_DRDY_EXTI1_Pin */
GPIO_InitStruct.Pin = USB_OTG_FS_OVRCR_EXTI3_Pin|SPSGRF_915_GPIO3_EXTI5_Pin|SPBTLE_RF_IRQ_EXTI6_Pin|ISM43362_DRDY_EXTI1_Pin;
80015e2: 236a movs r3, #106 @ 0x6a
80015e4: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80015e6: f44f 1388 mov.w r3, #1114112 @ 0x110000
80015ea: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80015ec: 2300 movs r3, #0
80015ee: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
80015f0: f107 0314 add.w r3, r7, #20
80015f4: 4619 mov r1, r3
80015f6: 4870 ldr r0, [pc, #448] @ (80017b8 <MX_GPIO_Init+0x2e0>)
80015f8: f001 ff7e bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pin : BUTTON_EXTI13_Pin */
GPIO_InitStruct.Pin = BUTTON_EXTI13_Pin;
80015fc: f44f 5300 mov.w r3, #8192 @ 0x2000
8001600: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
8001602: f44f 1304 mov.w r3, #2162688 @ 0x210000
8001606: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001608: 2300 movs r3, #0
800160a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(BUTTON_EXTI13_GPIO_Port, &GPIO_InitStruct);
800160c: f107 0314 add.w r3, r7, #20
8001610: 4619 mov r1, r3
8001612: 486c ldr r0, [pc, #432] @ (80017c4 <MX_GPIO_Init+0x2ec>)
8001614: f001 ff70 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D1_Pin ARD_D0_Pin */
GPIO_InitStruct.Pin = ARD_D1_Pin|ARD_D0_Pin;
8001618: 2303 movs r3, #3
800161a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800161c: 2302 movs r3, #2
800161e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001620: 2300 movs r3, #0
8001622: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001624: 2303 movs r3, #3
8001626: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
8001628: 2308 movs r3, #8
800162a: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800162c: f107 0314 add.w r3, r7, #20
8001630: 4619 mov r1, r3
8001632: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001636: f001 ff5f bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : Led_LCD_Pin D4_LCD_Pin D7_LCD_Pin SPBTLE_RF_RST_Pin
E_LCD_Pin */
GPIO_InitStruct.Pin = Led_LCD_Pin|D4_LCD_Pin|D7_LCD_Pin|SPBTLE_RF_RST_Pin
800163a: f248 131c movw r3, #33052 @ 0x811c
800163e: 617b str r3, [r7, #20]
|E_LCD_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001640: 2301 movs r3, #1
8001642: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001644: 2300 movs r3, #0
8001646: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001648: 2300 movs r3, #0
800164a: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800164c: f107 0314 add.w r3, r7, #20
8001650: 4619 mov r1, r3
8001652: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001656: f001 ff4f bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D12_Pin ARD_D11_Pin */
GPIO_InitStruct.Pin = ARD_D12_Pin|ARD_D11_Pin;
800165a: 23c0 movs r3, #192 @ 0xc0
800165c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800165e: 2302 movs r3, #2
8001660: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001662: 2300 movs r3, #0
8001664: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001666: 2303 movs r3, #3
8001668: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
800166a: 2305 movs r3, #5
800166c: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800166e: f107 0314 add.w r3, r7, #20
8001672: 4619 mov r1, r3
8001674: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001678: f001 ff3e bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pin : ARD_D3_Pin */
GPIO_InitStruct.Pin = ARD_D3_Pin;
800167c: 2301 movs r3, #1
800167e: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8001680: f44f 1388 mov.w r3, #1114112 @ 0x110000
8001684: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001686: 2300 movs r3, #0
8001688: 61fb str r3, [r7, #28]
HAL_GPIO_Init(ARD_D3_GPIO_Port, &GPIO_InitStruct);
800168a: f107 0314 add.w r3, r7, #20
800168e: 4619 mov r1, r3
8001690: 484a ldr r0, [pc, #296] @ (80017bc <MX_GPIO_Init+0x2e4>)
8001692: f001 ff31 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : D6_LCD_Pin RS_LCD_Pin ISM43362_BOOT0_Pin ISM43362_WAKEUP_Pin
LED2_Pin SPSGRF_915_SDN_Pin D5_LCD_Pin SPSGRF_915_SPI3_CSN_Pin */
GPIO_InitStruct.Pin = D6_LCD_Pin|RS_LCD_Pin|ISM43362_BOOT0_Pin|ISM43362_WAKEUP_Pin
8001696: f24f 0336 movw r3, #61494 @ 0xf036
800169a: 617b str r3, [r7, #20]
|LED2_Pin|SPSGRF_915_SDN_Pin|D5_LCD_Pin|SPSGRF_915_SPI3_CSN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800169c: 2301 movs r3, #1
800169e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016a0: 2300 movs r3, #0
80016a2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80016a4: 2300 movs r3, #0
80016a6: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80016a8: f107 0314 add.w r3, r7, #20
80016ac: 4619 mov r1, r3
80016ae: 4843 ldr r0, [pc, #268] @ (80017bc <MX_GPIO_Init+0x2e4>)
80016b0: f001 ff22 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : LPS22HB_INT_DRDY_EXTI0_Pin LSM6DSL_INT1_EXTI11_Pin ARD_D2_Pin HTS221_DRDY_EXTI15_Pin
PMOD_IRQ_EXTI12_Pin */
GPIO_InitStruct.Pin = LPS22HB_INT_DRDY_EXTI0_Pin|LSM6DSL_INT1_EXTI11_Pin|ARD_D2_Pin|HTS221_DRDY_EXTI15_Pin
80016b4: f64c 4304 movw r3, #52228 @ 0xcc04
80016b8: 617b str r3, [r7, #20]
|PMOD_IRQ_EXTI12_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80016ba: f44f 1388 mov.w r3, #1114112 @ 0x110000
80016be: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016c0: 2300 movs r3, #0
80016c2: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80016c4: f107 0314 add.w r3, r7, #20
80016c8: 4619 mov r1, r3
80016ca: 483d ldr r0, [pc, #244] @ (80017c0 <MX_GPIO_Init+0x2e8>)
80016cc: f001 ff14 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : USB_OTG_FS_PWR_EN_Pin SPBTLE_RF_SPI3_CSN_Pin PMOD_RESET_Pin STSAFE_A100_RESET_Pin */
GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|SPBTLE_RF_SPI3_CSN_Pin|PMOD_RESET_Pin|STSAFE_A100_RESET_Pin;
80016d0: f243 0381 movw r3, #12417 @ 0x3081
80016d4: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80016d6: 2301 movs r3, #1
80016d8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016da: 2300 movs r3, #0
80016dc: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80016de: 2300 movs r3, #0
80016e0: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80016e2: f107 0314 add.w r3, r7, #20
80016e6: 4619 mov r1, r3
80016e8: 4835 ldr r0, [pc, #212] @ (80017c0 <MX_GPIO_Init+0x2e8>)
80016ea: f001 ff05 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : VL53L0X_XSHUT_Pin LED3_WIFI__LED4_BLE_Pin */
GPIO_InitStruct.Pin = VL53L0X_XSHUT_Pin|LED3_WIFI__LED4_BLE_Pin;
80016ee: f44f 7310 mov.w r3, #576 @ 0x240
80016f2: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80016f4: 2301 movs r3, #1
80016f6: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016f8: 2300 movs r3, #0
80016fa: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80016fc: 2300 movs r3, #0
80016fe: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001700: f107 0314 add.w r3, r7, #20
8001704: 4619 mov r1, r3
8001706: 482f ldr r0, [pc, #188] @ (80017c4 <MX_GPIO_Init+0x2ec>)
8001708: f001 fef6 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : VL53L0X_GPIO1_EXTI7_Pin LSM3MDL_DRDY_EXTI8_Pin */
GPIO_InitStruct.Pin = VL53L0X_GPIO1_EXTI7_Pin|LSM3MDL_DRDY_EXTI8_Pin;
800170c: f44f 73c0 mov.w r3, #384 @ 0x180
8001710: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8001712: f44f 1388 mov.w r3, #1114112 @ 0x110000
8001716: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001718: 2300 movs r3, #0
800171a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800171c: f107 0314 add.w r3, r7, #20
8001720: 4619 mov r1, r3
8001722: 4828 ldr r0, [pc, #160] @ (80017c4 <MX_GPIO_Init+0x2ec>)
8001724: f001 fee8 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pin : PMOD_SPI2_SCK_Pin */
GPIO_InitStruct.Pin = PMOD_SPI2_SCK_Pin;
8001728: 2302 movs r3, #2
800172a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800172c: 2302 movs r3, #2
800172e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001730: 2300 movs r3, #0
8001732: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001734: 2303 movs r3, #3
8001736: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001738: 2305 movs r3, #5
800173a: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(PMOD_SPI2_SCK_GPIO_Port, &GPIO_InitStruct);
800173c: f107 0314 add.w r3, r7, #20
8001740: 4619 mov r1, r3
8001742: 481f ldr r0, [pc, #124] @ (80017c0 <MX_GPIO_Init+0x2e8>)
8001744: f001 fed8 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : PMOD_UART2_CTS_Pin PMOD_UART2_RTS_Pin PMOD_UART2_TX_Pin PMOD_UART2_RX_Pin */
GPIO_InitStruct.Pin = PMOD_UART2_CTS_Pin|PMOD_UART2_RTS_Pin|PMOD_UART2_TX_Pin|PMOD_UART2_RX_Pin;
8001748: 2378 movs r3, #120 @ 0x78
800174a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800174c: 2302 movs r3, #2
800174e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001750: 2300 movs r3, #0
8001752: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001754: 2303 movs r3, #3
8001756: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8001758: 2307 movs r3, #7
800175a: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
800175c: f107 0314 add.w r3, r7, #20
8001760: 4619 mov r1, r3
8001762: 4817 ldr r0, [pc, #92] @ (80017c0 <MX_GPIO_Init+0x2e8>)
8001764: f001 fec8 bl 80034f8 <HAL_GPIO_Init>
/*Configure GPIO pins : ARD_D15_Pin ARD_D14_Pin */
GPIO_InitStruct.Pin = ARD_D15_Pin|ARD_D14_Pin;
8001768: f44f 7340 mov.w r3, #768 @ 0x300
800176c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
800176e: 2312 movs r3, #18
8001770: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001772: 2300 movs r3, #0
8001774: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001776: 2303 movs r3, #3
8001778: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
800177a: 2304 movs r3, #4
800177c: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800177e: f107 0314 add.w r3, r7, #20
8001782: 4619 mov r1, r3
8001784: 480d ldr r0, [pc, #52] @ (80017bc <MX_GPIO_Init+0x2e4>)
8001786: f001 feb7 bl 80034f8 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
800178a: 2200 movs r2, #0
800178c: 2100 movs r1, #0
800178e: 2017 movs r0, #23
8001790: f001 fd6f bl 8003272 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
8001794: 2017 movs r0, #23
8001796: f001 fd88 bl 80032aa <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
800179a: 2200 movs r2, #0
800179c: 2100 movs r1, #0
800179e: 2028 movs r0, #40 @ 0x28
80017a0: f001 fd67 bl 8003272 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
80017a4: 2028 movs r0, #40 @ 0x28
80017a6: f001 fd80 bl 80032aa <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80017aa: bf00 nop
80017ac: 3728 adds r7, #40 @ 0x28
80017ae: 46bd mov sp, r7
80017b0: bd80 pop {r7, pc}
80017b2: bf00 nop
80017b4: 40021000 .word 0x40021000
80017b8: 48001000 .word 0x48001000
80017bc: 48000400 .word 0x48000400
80017c0: 48000c00 .word 0x48000c00
80017c4: 48000800 .word 0x48000800
080017c8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80017c8: b480 push {r7}
80017ca: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80017cc: b672 cpsid i
}
80017ce: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80017d0: bf00 nop
80017d2: e7fd b.n 80017d0 <Error_Handler+0x8>
080017d4 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80017d4: b480 push {r7}
80017d6: b083 sub sp, #12
80017d8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80017da: 4b0f ldr r3, [pc, #60] @ (8001818 <HAL_MspInit+0x44>)
80017dc: 6e1b ldr r3, [r3, #96] @ 0x60
80017de: 4a0e ldr r2, [pc, #56] @ (8001818 <HAL_MspInit+0x44>)
80017e0: f043 0301 orr.w r3, r3, #1
80017e4: 6613 str r3, [r2, #96] @ 0x60
80017e6: 4b0c ldr r3, [pc, #48] @ (8001818 <HAL_MspInit+0x44>)
80017e8: 6e1b ldr r3, [r3, #96] @ 0x60
80017ea: f003 0301 and.w r3, r3, #1
80017ee: 607b str r3, [r7, #4]
80017f0: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80017f2: 4b09 ldr r3, [pc, #36] @ (8001818 <HAL_MspInit+0x44>)
80017f4: 6d9b ldr r3, [r3, #88] @ 0x58
80017f6: 4a08 ldr r2, [pc, #32] @ (8001818 <HAL_MspInit+0x44>)
80017f8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80017fc: 6593 str r3, [r2, #88] @ 0x58
80017fe: 4b06 ldr r3, [pc, #24] @ (8001818 <HAL_MspInit+0x44>)
8001800: 6d9b ldr r3, [r3, #88] @ 0x58
8001802: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001806: 603b str r3, [r7, #0]
8001808: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800180a: bf00 nop
800180c: 370c adds r7, #12
800180e: 46bd mov sp, r7
8001810: f85d 7b04 ldr.w r7, [sp], #4
8001814: 4770 bx lr
8001816: bf00 nop
8001818: 40021000 .word 0x40021000
0800181c <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
800181c: b580 push {r7, lr}
800181e: b08a sub sp, #40 @ 0x28
8001820: af00 add r7, sp, #0
8001822: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001824: f107 0314 add.w r3, r7, #20
8001828: 2200 movs r2, #0
800182a: 601a str r2, [r3, #0]
800182c: 605a str r2, [r3, #4]
800182e: 609a str r2, [r3, #8]
8001830: 60da str r2, [r3, #12]
8001832: 611a str r2, [r3, #16]
if(hadc->Instance==ADC1)
8001834: 687b ldr r3, [r7, #4]
8001836: 681b ldr r3, [r3, #0]
8001838: 4a15 ldr r2, [pc, #84] @ (8001890 <HAL_ADC_MspInit+0x74>)
800183a: 4293 cmp r3, r2
800183c: d123 bne.n 8001886 <HAL_ADC_MspInit+0x6a>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC_CLK_ENABLE();
800183e: 4b15 ldr r3, [pc, #84] @ (8001894 <HAL_ADC_MspInit+0x78>)
8001840: 6cdb ldr r3, [r3, #76] @ 0x4c
8001842: 4a14 ldr r2, [pc, #80] @ (8001894 <HAL_ADC_MspInit+0x78>)
8001844: f443 5300 orr.w r3, r3, #8192 @ 0x2000
8001848: 64d3 str r3, [r2, #76] @ 0x4c
800184a: 4b12 ldr r3, [pc, #72] @ (8001894 <HAL_ADC_MspInit+0x78>)
800184c: 6cdb ldr r3, [r3, #76] @ 0x4c
800184e: f403 5300 and.w r3, r3, #8192 @ 0x2000
8001852: 613b str r3, [r7, #16]
8001854: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001856: 4b0f ldr r3, [pc, #60] @ (8001894 <HAL_ADC_MspInit+0x78>)
8001858: 6cdb ldr r3, [r3, #76] @ 0x4c
800185a: 4a0e ldr r2, [pc, #56] @ (8001894 <HAL_ADC_MspInit+0x78>)
800185c: f043 0304 orr.w r3, r3, #4
8001860: 64d3 str r3, [r2, #76] @ 0x4c
8001862: 4b0c ldr r3, [pc, #48] @ (8001894 <HAL_ADC_MspInit+0x78>)
8001864: 6cdb ldr r3, [r3, #76] @ 0x4c
8001866: f003 0304 and.w r3, r3, #4
800186a: 60fb str r3, [r7, #12]
800186c: 68fb ldr r3, [r7, #12]
PC2 ------> ADC1_IN3
PC3 ------> ADC1_IN4
PC4 ------> ADC1_IN13
PC5 ------> ADC1_IN14
*/
GPIO_InitStruct.Pin = ARD_A5_Pin|ARD_A4_Pin|ARD_A3_Pin|ARD_A2_Pin
800186e: 233f movs r3, #63 @ 0x3f
8001870: 617b str r3, [r7, #20]
|ARD_A1_Pin|ARD_A0_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
8001872: 230b movs r3, #11
8001874: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001876: 2300 movs r3, #0
8001878: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800187a: f107 0314 add.w r3, r7, #20
800187e: 4619 mov r1, r3
8001880: 4805 ldr r0, [pc, #20] @ (8001898 <HAL_ADC_MspInit+0x7c>)
8001882: f001 fe39 bl 80034f8 <HAL_GPIO_Init>
/* USER CODE END ADC1_MspInit 1 */
}
}
8001886: bf00 nop
8001888: 3728 adds r7, #40 @ 0x28
800188a: 46bd mov sp, r7
800188c: bd80 pop {r7, pc}
800188e: bf00 nop
8001890: 50040000 .word 0x50040000
8001894: 40021000 .word 0x40021000
8001898: 48000800 .word 0x48000800
0800189c <HAL_DFSDM_ChannelMspInit>:
* This function configures the hardware resources used in this example
* @param hdfsdm_channel: DFSDM_Channel handle pointer
* @retval None
*/
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel)
{
800189c: b580 push {r7, lr}
800189e: b0ac sub sp, #176 @ 0xb0
80018a0: af00 add r7, sp, #0
80018a2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80018a4: f107 039c add.w r3, r7, #156 @ 0x9c
80018a8: 2200 movs r2, #0
80018aa: 601a str r2, [r3, #0]
80018ac: 605a str r2, [r3, #4]
80018ae: 609a str r2, [r3, #8]
80018b0: 60da str r2, [r3, #12]
80018b2: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
80018b4: f107 0314 add.w r3, r7, #20
80018b8: 2288 movs r2, #136 @ 0x88
80018ba: 2100 movs r1, #0
80018bc: 4618 mov r0, r3
80018be: f00a fd26 bl 800c30e <memset>
if(DFSDM1_Init == 0)
80018c2: 4b25 ldr r3, [pc, #148] @ (8001958 <HAL_DFSDM_ChannelMspInit+0xbc>)
80018c4: 681b ldr r3, [r3, #0]
80018c6: 2b00 cmp r3, #0
80018c8: d142 bne.n 8001950 <HAL_DFSDM_ChannelMspInit+0xb4>
/* USER CODE END DFSDM1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1;
80018ca: f44f 3380 mov.w r3, #65536 @ 0x10000
80018ce: 617b str r3, [r7, #20]
PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
80018d0: 2300 movs r3, #0
80018d2: f8c7 3094 str.w r3, [r7, #148] @ 0x94
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80018d6: f107 0314 add.w r3, r7, #20
80018da: 4618 mov r0, r3
80018dc: f004 f9e2 bl 8005ca4 <HAL_RCCEx_PeriphCLKConfig>
80018e0: 4603 mov r3, r0
80018e2: 2b00 cmp r3, #0
80018e4: d001 beq.n 80018ea <HAL_DFSDM_ChannelMspInit+0x4e>
{
Error_Handler();
80018e6: f7ff ff6f bl 80017c8 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_DFSDM1_CLK_ENABLE();
80018ea: 4b1c ldr r3, [pc, #112] @ (800195c <HAL_DFSDM_ChannelMspInit+0xc0>)
80018ec: 6e1b ldr r3, [r3, #96] @ 0x60
80018ee: 4a1b ldr r2, [pc, #108] @ (800195c <HAL_DFSDM_ChannelMspInit+0xc0>)
80018f0: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80018f4: 6613 str r3, [r2, #96] @ 0x60
80018f6: 4b19 ldr r3, [pc, #100] @ (800195c <HAL_DFSDM_ChannelMspInit+0xc0>)
80018f8: 6e1b ldr r3, [r3, #96] @ 0x60
80018fa: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
80018fe: 613b str r3, [r7, #16]
8001900: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOE_CLK_ENABLE();
8001902: 4b16 ldr r3, [pc, #88] @ (800195c <HAL_DFSDM_ChannelMspInit+0xc0>)
8001904: 6cdb ldr r3, [r3, #76] @ 0x4c
8001906: 4a15 ldr r2, [pc, #84] @ (800195c <HAL_DFSDM_ChannelMspInit+0xc0>)
8001908: f043 0310 orr.w r3, r3, #16
800190c: 64d3 str r3, [r2, #76] @ 0x4c
800190e: 4b13 ldr r3, [pc, #76] @ (800195c <HAL_DFSDM_ChannelMspInit+0xc0>)
8001910: 6cdb ldr r3, [r3, #76] @ 0x4c
8001912: f003 0310 and.w r3, r3, #16
8001916: 60fb str r3, [r7, #12]
8001918: 68fb ldr r3, [r7, #12]
/**DFSDM1 GPIO Configuration
PE7 ------> DFSDM1_DATIN2
PE9 ------> DFSDM1_CKOUT
*/
GPIO_InitStruct.Pin = DFSDM1_DATIN2_Pin|DFSDM1_CKOUT_Pin;
800191a: f44f 7320 mov.w r3, #640 @ 0x280
800191e: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001922: 2302 movs r3, #2
8001924: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001928: 2300 movs r3, #0
800192a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800192e: 2300 movs r3, #0
8001930: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1;
8001934: 2306 movs r3, #6
8001936: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
800193a: f107 039c add.w r3, r7, #156 @ 0x9c
800193e: 4619 mov r1, r3
8001940: 4807 ldr r0, [pc, #28] @ (8001960 <HAL_DFSDM_ChannelMspInit+0xc4>)
8001942: f001 fdd9 bl 80034f8 <HAL_GPIO_Init>
/* USER CODE BEGIN DFSDM1_MspInit 1 */
/* USER CODE END DFSDM1_MspInit 1 */
DFSDM1_Init++;
8001946: 4b04 ldr r3, [pc, #16] @ (8001958 <HAL_DFSDM_ChannelMspInit+0xbc>)
8001948: 681b ldr r3, [r3, #0]
800194a: 3301 adds r3, #1
800194c: 4a02 ldr r2, [pc, #8] @ (8001958 <HAL_DFSDM_ChannelMspInit+0xbc>)
800194e: 6013 str r3, [r2, #0]
}
}
8001950: bf00 nop
8001952: 37b0 adds r7, #176 @ 0xb0
8001954: 46bd mov sp, r7
8001956: bd80 pop {r7, pc}
8001958: 2000065c .word 0x2000065c
800195c: 40021000 .word 0x40021000
8001960: 48001000 .word 0x48001000
08001964 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8001964: b580 push {r7, lr}
8001966: b0ac sub sp, #176 @ 0xb0
8001968: af00 add r7, sp, #0
800196a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800196c: f107 039c add.w r3, r7, #156 @ 0x9c
8001970: 2200 movs r2, #0
8001972: 601a str r2, [r3, #0]
8001974: 605a str r2, [r3, #4]
8001976: 609a str r2, [r3, #8]
8001978: 60da str r2, [r3, #12]
800197a: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
800197c: f107 0314 add.w r3, r7, #20
8001980: 2288 movs r2, #136 @ 0x88
8001982: 2100 movs r1, #0
8001984: 4618 mov r0, r3
8001986: f00a fcc2 bl 800c30e <memset>
if(hi2c->Instance==I2C2)
800198a: 687b ldr r3, [r7, #4]
800198c: 681b ldr r3, [r3, #0]
800198e: 4a21 ldr r2, [pc, #132] @ (8001a14 <HAL_I2C_MspInit+0xb0>)
8001990: 4293 cmp r3, r2
8001992: d13b bne.n 8001a0c <HAL_I2C_MspInit+0xa8>
/* USER CODE END I2C2_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
8001994: 2380 movs r3, #128 @ 0x80
8001996: 617b str r3, [r7, #20]
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
8001998: 2300 movs r3, #0
800199a: 66bb str r3, [r7, #104] @ 0x68
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
800199c: f107 0314 add.w r3, r7, #20
80019a0: 4618 mov r0, r3
80019a2: f004 f97f bl 8005ca4 <HAL_RCCEx_PeriphCLKConfig>
80019a6: 4603 mov r3, r0
80019a8: 2b00 cmp r3, #0
80019aa: d001 beq.n 80019b0 <HAL_I2C_MspInit+0x4c>
{
Error_Handler();
80019ac: f7ff ff0c bl 80017c8 <Error_Handler>
}
__HAL_RCC_GPIOB_CLK_ENABLE();
80019b0: 4b19 ldr r3, [pc, #100] @ (8001a18 <HAL_I2C_MspInit+0xb4>)
80019b2: 6cdb ldr r3, [r3, #76] @ 0x4c
80019b4: 4a18 ldr r2, [pc, #96] @ (8001a18 <HAL_I2C_MspInit+0xb4>)
80019b6: f043 0302 orr.w r3, r3, #2
80019ba: 64d3 str r3, [r2, #76] @ 0x4c
80019bc: 4b16 ldr r3, [pc, #88] @ (8001a18 <HAL_I2C_MspInit+0xb4>)
80019be: 6cdb ldr r3, [r3, #76] @ 0x4c
80019c0: f003 0302 and.w r3, r3, #2
80019c4: 613b str r3, [r7, #16]
80019c6: 693b ldr r3, [r7, #16]
/**I2C2 GPIO Configuration
PB10 ------> I2C2_SCL
PB11 ------> I2C2_SDA
*/
GPIO_InitStruct.Pin = INTERNAL_I2C2_SCL_Pin|INTERNAL_I2C2_SDA_Pin;
80019c8: f44f 6340 mov.w r3, #3072 @ 0xc00
80019cc: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80019d0: 2312 movs r3, #18
80019d2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_PULLUP;
80019d6: 2301 movs r3, #1
80019d8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80019dc: 2303 movs r3, #3
80019de: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
80019e2: 2304 movs r3, #4
80019e4: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80019e8: f107 039c add.w r3, r7, #156 @ 0x9c
80019ec: 4619 mov r1, r3
80019ee: 480b ldr r0, [pc, #44] @ (8001a1c <HAL_I2C_MspInit+0xb8>)
80019f0: f001 fd82 bl 80034f8 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C2_CLK_ENABLE();
80019f4: 4b08 ldr r3, [pc, #32] @ (8001a18 <HAL_I2C_MspInit+0xb4>)
80019f6: 6d9b ldr r3, [r3, #88] @ 0x58
80019f8: 4a07 ldr r2, [pc, #28] @ (8001a18 <HAL_I2C_MspInit+0xb4>)
80019fa: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
80019fe: 6593 str r3, [r2, #88] @ 0x58
8001a00: 4b05 ldr r3, [pc, #20] @ (8001a18 <HAL_I2C_MspInit+0xb4>)
8001a02: 6d9b ldr r3, [r3, #88] @ 0x58
8001a04: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8001a08: 60fb str r3, [r7, #12]
8001a0a: 68fb ldr r3, [r7, #12]
/* USER CODE END I2C2_MspInit 1 */
}
}
8001a0c: bf00 nop
8001a0e: 37b0 adds r7, #176 @ 0xb0
8001a10: 46bd mov sp, r7
8001a12: bd80 pop {r7, pc}
8001a14: 40005800 .word 0x40005800
8001a18: 40021000 .word 0x40021000
8001a1c: 48000400 .word 0x48000400
08001a20 <HAL_QSPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hqspi: QSPI handle pointer
* @retval None
*/
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
{
8001a20: b580 push {r7, lr}
8001a22: b08a sub sp, #40 @ 0x28
8001a24: af00 add r7, sp, #0
8001a26: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001a28: f107 0314 add.w r3, r7, #20
8001a2c: 2200 movs r2, #0
8001a2e: 601a str r2, [r3, #0]
8001a30: 605a str r2, [r3, #4]
8001a32: 609a str r2, [r3, #8]
8001a34: 60da str r2, [r3, #12]
8001a36: 611a str r2, [r3, #16]
if(hqspi->Instance==QUADSPI)
8001a38: 687b ldr r3, [r7, #4]
8001a3a: 681b ldr r3, [r3, #0]
8001a3c: 4a17 ldr r2, [pc, #92] @ (8001a9c <HAL_QSPI_MspInit+0x7c>)
8001a3e: 4293 cmp r3, r2
8001a40: d128 bne.n 8001a94 <HAL_QSPI_MspInit+0x74>
{
/* USER CODE BEGIN QUADSPI_MspInit 0 */
/* USER CODE END QUADSPI_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_QSPI_CLK_ENABLE();
8001a42: 4b17 ldr r3, [pc, #92] @ (8001aa0 <HAL_QSPI_MspInit+0x80>)
8001a44: 6d1b ldr r3, [r3, #80] @ 0x50
8001a46: 4a16 ldr r2, [pc, #88] @ (8001aa0 <HAL_QSPI_MspInit+0x80>)
8001a48: f443 7380 orr.w r3, r3, #256 @ 0x100
8001a4c: 6513 str r3, [r2, #80] @ 0x50
8001a4e: 4b14 ldr r3, [pc, #80] @ (8001aa0 <HAL_QSPI_MspInit+0x80>)
8001a50: 6d1b ldr r3, [r3, #80] @ 0x50
8001a52: f403 7380 and.w r3, r3, #256 @ 0x100
8001a56: 613b str r3, [r7, #16]
8001a58: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOE_CLK_ENABLE();
8001a5a: 4b11 ldr r3, [pc, #68] @ (8001aa0 <HAL_QSPI_MspInit+0x80>)
8001a5c: 6cdb ldr r3, [r3, #76] @ 0x4c
8001a5e: 4a10 ldr r2, [pc, #64] @ (8001aa0 <HAL_QSPI_MspInit+0x80>)
8001a60: f043 0310 orr.w r3, r3, #16
8001a64: 64d3 str r3, [r2, #76] @ 0x4c
8001a66: 4b0e ldr r3, [pc, #56] @ (8001aa0 <HAL_QSPI_MspInit+0x80>)
8001a68: 6cdb ldr r3, [r3, #76] @ 0x4c
8001a6a: f003 0310 and.w r3, r3, #16
8001a6e: 60fb str r3, [r7, #12]
8001a70: 68fb ldr r3, [r7, #12]
PE12 ------> QUADSPI_BK1_IO0
PE13 ------> QUADSPI_BK1_IO1
PE14 ------> QUADSPI_BK1_IO2
PE15 ------> QUADSPI_BK1_IO3
*/
GPIO_InitStruct.Pin = QUADSPI_CLK_Pin|QUADSPI_NCS_Pin|OQUADSPI_BK1_IO0_Pin|QUADSPI_BK1_IO1_Pin
8001a72: f44f 437c mov.w r3, #64512 @ 0xfc00
8001a76: 617b str r3, [r7, #20]
|QUAD_SPI_BK1_IO2_Pin|QUAD_SPI_BK1_IO3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001a78: 2302 movs r3, #2
8001a7a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a7c: 2300 movs r3, #0
8001a7e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001a80: 2303 movs r3, #3
8001a82: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
8001a84: 230a movs r3, #10
8001a86: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001a88: f107 0314 add.w r3, r7, #20
8001a8c: 4619 mov r1, r3
8001a8e: 4805 ldr r0, [pc, #20] @ (8001aa4 <HAL_QSPI_MspInit+0x84>)
8001a90: f001 fd32 bl 80034f8 <HAL_GPIO_Init>
/* USER CODE END QUADSPI_MspInit 1 */
}
}
8001a94: bf00 nop
8001a96: 3728 adds r7, #40 @ 0x28
8001a98: 46bd mov sp, r7
8001a9a: bd80 pop {r7, pc}
8001a9c: a0001000 .word 0xa0001000
8001aa0: 40021000 .word 0x40021000
8001aa4: 48001000 .word 0x48001000
08001aa8 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8001aa8: b580 push {r7, lr}
8001aaa: b08a sub sp, #40 @ 0x28
8001aac: af00 add r7, sp, #0
8001aae: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001ab0: f107 0314 add.w r3, r7, #20
8001ab4: 2200 movs r2, #0
8001ab6: 601a str r2, [r3, #0]
8001ab8: 605a str r2, [r3, #4]
8001aba: 609a str r2, [r3, #8]
8001abc: 60da str r2, [r3, #12]
8001abe: 611a str r2, [r3, #16]
if(hspi->Instance==SPI3)
8001ac0: 687b ldr r3, [r7, #4]
8001ac2: 681b ldr r3, [r3, #0]
8001ac4: 4a17 ldr r2, [pc, #92] @ (8001b24 <HAL_SPI_MspInit+0x7c>)
8001ac6: 4293 cmp r3, r2
8001ac8: d128 bne.n 8001b1c <HAL_SPI_MspInit+0x74>
{
/* USER CODE BEGIN SPI3_MspInit 0 */
/* USER CODE END SPI3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI3_CLK_ENABLE();
8001aca: 4b17 ldr r3, [pc, #92] @ (8001b28 <HAL_SPI_MspInit+0x80>)
8001acc: 6d9b ldr r3, [r3, #88] @ 0x58
8001ace: 4a16 ldr r2, [pc, #88] @ (8001b28 <HAL_SPI_MspInit+0x80>)
8001ad0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8001ad4: 6593 str r3, [r2, #88] @ 0x58
8001ad6: 4b14 ldr r3, [pc, #80] @ (8001b28 <HAL_SPI_MspInit+0x80>)
8001ad8: 6d9b ldr r3, [r3, #88] @ 0x58
8001ada: f403 4300 and.w r3, r3, #32768 @ 0x8000
8001ade: 613b str r3, [r7, #16]
8001ae0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001ae2: 4b11 ldr r3, [pc, #68] @ (8001b28 <HAL_SPI_MspInit+0x80>)
8001ae4: 6cdb ldr r3, [r3, #76] @ 0x4c
8001ae6: 4a10 ldr r2, [pc, #64] @ (8001b28 <HAL_SPI_MspInit+0x80>)
8001ae8: f043 0304 orr.w r3, r3, #4
8001aec: 64d3 str r3, [r2, #76] @ 0x4c
8001aee: 4b0e ldr r3, [pc, #56] @ (8001b28 <HAL_SPI_MspInit+0x80>)
8001af0: 6cdb ldr r3, [r3, #76] @ 0x4c
8001af2: f003 0304 and.w r3, r3, #4
8001af6: 60fb str r3, [r7, #12]
8001af8: 68fb ldr r3, [r7, #12]
/**SPI3 GPIO Configuration
PC10 ------> SPI3_SCK
PC11 ------> SPI3_MISO
PC12 ------> SPI3_MOSI
*/
GPIO_InitStruct.Pin = INTERNAL_SPI3_SCK_Pin|INTERNAL_SPI3_MISO_Pin|INTERNAL_SPI3_MOSI_Pin;
8001afa: f44f 53e0 mov.w r3, #7168 @ 0x1c00
8001afe: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b00: 2302 movs r3, #2
8001b02: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b04: 2300 movs r3, #0
8001b06: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001b08: 2303 movs r3, #3
8001b0a: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
8001b0c: 2306 movs r3, #6
8001b0e: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001b10: f107 0314 add.w r3, r7, #20
8001b14: 4619 mov r1, r3
8001b16: 4805 ldr r0, [pc, #20] @ (8001b2c <HAL_SPI_MspInit+0x84>)
8001b18: f001 fcee bl 80034f8 <HAL_GPIO_Init>
/* USER CODE END SPI3_MspInit 1 */
}
}
8001b1c: bf00 nop
8001b1e: 3728 adds r7, #40 @ 0x28
8001b20: 46bd mov sp, r7
8001b22: bd80 pop {r7, pc}
8001b24: 40003c00 .word 0x40003c00
8001b28: 40021000 .word 0x40021000
8001b2c: 48000800 .word 0x48000800
08001b30 <HAL_TIM_PWM_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{
8001b30: b480 push {r7}
8001b32: b085 sub sp, #20
8001b34: af00 add r7, sp, #0
8001b36: 6078 str r0, [r7, #4]
if(htim_pwm->Instance==TIM2)
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 681b ldr r3, [r3, #0]
8001b3c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001b40: d10b bne.n 8001b5a <HAL_TIM_PWM_MspInit+0x2a>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001b42: 4b09 ldr r3, [pc, #36] @ (8001b68 <HAL_TIM_PWM_MspInit+0x38>)
8001b44: 6d9b ldr r3, [r3, #88] @ 0x58
8001b46: 4a08 ldr r2, [pc, #32] @ (8001b68 <HAL_TIM_PWM_MspInit+0x38>)
8001b48: f043 0301 orr.w r3, r3, #1
8001b4c: 6593 str r3, [r2, #88] @ 0x58
8001b4e: 4b06 ldr r3, [pc, #24] @ (8001b68 <HAL_TIM_PWM_MspInit+0x38>)
8001b50: 6d9b ldr r3, [r3, #88] @ 0x58
8001b52: f003 0301 and.w r3, r3, #1
8001b56: 60fb str r3, [r7, #12]
8001b58: 68fb ldr r3, [r7, #12]
/* USER CODE END TIM2_MspInit 1 */
}
}
8001b5a: bf00 nop
8001b5c: 3714 adds r7, #20
8001b5e: 46bd mov sp, r7
8001b60: f85d 7b04 ldr.w r7, [sp], #4
8001b64: 4770 bx lr
8001b66: bf00 nop
8001b68: 40021000 .word 0x40021000
08001b6c <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001b6c: b580 push {r7, lr}
8001b6e: b084 sub sp, #16
8001b70: af00 add r7, sp, #0
8001b72: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM7)
8001b74: 687b ldr r3, [r7, #4]
8001b76: 681b ldr r3, [r3, #0]
8001b78: 4a0d ldr r2, [pc, #52] @ (8001bb0 <HAL_TIM_Base_MspInit+0x44>)
8001b7a: 4293 cmp r3, r2
8001b7c: d113 bne.n 8001ba6 <HAL_TIM_Base_MspInit+0x3a>
{
/* USER CODE BEGIN TIM7_MspInit 0 */
/* USER CODE END TIM7_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM7_CLK_ENABLE();
8001b7e: 4b0d ldr r3, [pc, #52] @ (8001bb4 <HAL_TIM_Base_MspInit+0x48>)
8001b80: 6d9b ldr r3, [r3, #88] @ 0x58
8001b82: 4a0c ldr r2, [pc, #48] @ (8001bb4 <HAL_TIM_Base_MspInit+0x48>)
8001b84: f043 0320 orr.w r3, r3, #32
8001b88: 6593 str r3, [r2, #88] @ 0x58
8001b8a: 4b0a ldr r3, [pc, #40] @ (8001bb4 <HAL_TIM_Base_MspInit+0x48>)
8001b8c: 6d9b ldr r3, [r3, #88] @ 0x58
8001b8e: f003 0320 and.w r3, r3, #32
8001b92: 60fb str r3, [r7, #12]
8001b94: 68fb ldr r3, [r7, #12]
/* TIM7 interrupt Init */
HAL_NVIC_SetPriority(TIM7_IRQn, 0, 0);
8001b96: 2200 movs r2, #0
8001b98: 2100 movs r1, #0
8001b9a: 2037 movs r0, #55 @ 0x37
8001b9c: f001 fb69 bl 8003272 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM7_IRQn);
8001ba0: 2037 movs r0, #55 @ 0x37
8001ba2: f001 fb82 bl 80032aa <HAL_NVIC_EnableIRQ>
/* USER CODE END TIM7_MspInit 1 */
}
}
8001ba6: bf00 nop
8001ba8: 3710 adds r7, #16
8001baa: 46bd mov sp, r7
8001bac: bd80 pop {r7, pc}
8001bae: bf00 nop
8001bb0: 40001400 .word 0x40001400
8001bb4: 40021000 .word 0x40021000
08001bb8 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001bb8: b580 push {r7, lr}
8001bba: b088 sub sp, #32
8001bbc: af00 add r7, sp, #0
8001bbe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001bc0: f107 030c add.w r3, r7, #12
8001bc4: 2200 movs r2, #0
8001bc6: 601a str r2, [r3, #0]
8001bc8: 605a str r2, [r3, #4]
8001bca: 609a str r2, [r3, #8]
8001bcc: 60da str r2, [r3, #12]
8001bce: 611a str r2, [r3, #16]
if(htim->Instance==TIM2)
8001bd0: 687b ldr r3, [r7, #4]
8001bd2: 681b ldr r3, [r3, #0]
8001bd4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001bd8: d11c bne.n 8001c14 <HAL_TIM_MspPostInit+0x5c>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001bda: 4b10 ldr r3, [pc, #64] @ (8001c1c <HAL_TIM_MspPostInit+0x64>)
8001bdc: 6cdb ldr r3, [r3, #76] @ 0x4c
8001bde: 4a0f ldr r2, [pc, #60] @ (8001c1c <HAL_TIM_MspPostInit+0x64>)
8001be0: f043 0301 orr.w r3, r3, #1
8001be4: 64d3 str r3, [r2, #76] @ 0x4c
8001be6: 4b0d ldr r3, [pc, #52] @ (8001c1c <HAL_TIM_MspPostInit+0x64>)
8001be8: 6cdb ldr r3, [r3, #76] @ 0x4c
8001bea: f003 0301 and.w r3, r3, #1
8001bee: 60bb str r3, [r7, #8]
8001bf0: 68bb ldr r3, [r7, #8]
/**TIM2 GPIO Configuration
PA5 ------> TIM2_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_5;
8001bf2: 2320 movs r3, #32
8001bf4: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bf6: 2302 movs r3, #2
8001bf8: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bfa: 2300 movs r3, #0
8001bfc: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001bfe: 2300 movs r3, #0
8001c00: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8001c02: 2301 movs r3, #1
8001c04: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001c06: f107 030c add.w r3, r7, #12
8001c0a: 4619 mov r1, r3
8001c0c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001c10: f001 fc72 bl 80034f8 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM2_MspPostInit 1 */
/* USER CODE END TIM2_MspPostInit 1 */
}
}
8001c14: bf00 nop
8001c16: 3720 adds r7, #32
8001c18: 46bd mov sp, r7
8001c1a: bd80 pop {r7, pc}
8001c1c: 40021000 .word 0x40021000
08001c20 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001c20: b580 push {r7, lr}
8001c22: b0ae sub sp, #184 @ 0xb8
8001c24: af00 add r7, sp, #0
8001c26: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001c28: f107 03a4 add.w r3, r7, #164 @ 0xa4
8001c2c: 2200 movs r2, #0
8001c2e: 601a str r2, [r3, #0]
8001c30: 605a str r2, [r3, #4]
8001c32: 609a str r2, [r3, #8]
8001c34: 60da str r2, [r3, #12]
8001c36: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8001c38: f107 031c add.w r3, r7, #28
8001c3c: 2288 movs r2, #136 @ 0x88
8001c3e: 2100 movs r1, #0
8001c40: 4618 mov r0, r3
8001c42: f00a fb64 bl 800c30e <memset>
if(huart->Instance==USART1)
8001c46: 687b ldr r3, [r7, #4]
8001c48: 681b ldr r3, [r3, #0]
8001c4a: 4a42 ldr r2, [pc, #264] @ (8001d54 <HAL_UART_MspInit+0x134>)
8001c4c: 4293 cmp r3, r2
8001c4e: d13b bne.n 8001cc8 <HAL_UART_MspInit+0xa8>
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
8001c50: 2301 movs r3, #1
8001c52: 61fb str r3, [r7, #28]
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
8001c54: 2300 movs r3, #0
8001c56: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001c58: f107 031c add.w r3, r7, #28
8001c5c: 4618 mov r0, r3
8001c5e: f004 f821 bl 8005ca4 <HAL_RCCEx_PeriphCLKConfig>
8001c62: 4603 mov r3, r0
8001c64: 2b00 cmp r3, #0
8001c66: d001 beq.n 8001c6c <HAL_UART_MspInit+0x4c>
{
Error_Handler();
8001c68: f7ff fdae bl 80017c8 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8001c6c: 4b3a ldr r3, [pc, #232] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001c6e: 6e1b ldr r3, [r3, #96] @ 0x60
8001c70: 4a39 ldr r2, [pc, #228] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001c72: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001c76: 6613 str r3, [r2, #96] @ 0x60
8001c78: 4b37 ldr r3, [pc, #220] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001c7a: 6e1b ldr r3, [r3, #96] @ 0x60
8001c7c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001c80: 61bb str r3, [r7, #24]
8001c82: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001c84: 4b34 ldr r3, [pc, #208] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001c86: 6cdb ldr r3, [r3, #76] @ 0x4c
8001c88: 4a33 ldr r2, [pc, #204] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001c8a: f043 0302 orr.w r3, r3, #2
8001c8e: 64d3 str r3, [r2, #76] @ 0x4c
8001c90: 4b31 ldr r3, [pc, #196] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001c92: 6cdb ldr r3, [r3, #76] @ 0x4c
8001c94: f003 0302 and.w r3, r3, #2
8001c98: 617b str r3, [r7, #20]
8001c9a: 697b ldr r3, [r7, #20]
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = ST_LINK_UART1_TX_Pin|ST_LINK_UART1_RX_Pin;
8001c9c: 23c0 movs r3, #192 @ 0xc0
8001c9e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001ca2: 2302 movs r3, #2
8001ca4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ca8: 2300 movs r3, #0
8001caa: f8c7 30ac str.w r3, [r7, #172] @ 0xac
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001cae: 2303 movs r3, #3
8001cb0: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001cb4: 2307 movs r3, #7
8001cb6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001cba: f107 03a4 add.w r3, r7, #164 @ 0xa4
8001cbe: 4619 mov r1, r3
8001cc0: 4826 ldr r0, [pc, #152] @ (8001d5c <HAL_UART_MspInit+0x13c>)
8001cc2: f001 fc19 bl 80034f8 <HAL_GPIO_Init>
/* USER CODE BEGIN USART3_MspInit 1 */
/* USER CODE END USART3_MspInit 1 */
}
}
8001cc6: e040 b.n 8001d4a <HAL_UART_MspInit+0x12a>
else if(huart->Instance==USART3)
8001cc8: 687b ldr r3, [r7, #4]
8001cca: 681b ldr r3, [r3, #0]
8001ccc: 4a24 ldr r2, [pc, #144] @ (8001d60 <HAL_UART_MspInit+0x140>)
8001cce: 4293 cmp r3, r2
8001cd0: d13b bne.n 8001d4a <HAL_UART_MspInit+0x12a>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3;
8001cd2: 2304 movs r3, #4
8001cd4: 61fb str r3, [r7, #28]
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
8001cd6: 2300 movs r3, #0
8001cd8: 65fb str r3, [r7, #92] @ 0x5c
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001cda: f107 031c add.w r3, r7, #28
8001cde: 4618 mov r0, r3
8001ce0: f003 ffe0 bl 8005ca4 <HAL_RCCEx_PeriphCLKConfig>
8001ce4: 4603 mov r3, r0
8001ce6: 2b00 cmp r3, #0
8001ce8: d001 beq.n 8001cee <HAL_UART_MspInit+0xce>
Error_Handler();
8001cea: f7ff fd6d bl 80017c8 <Error_Handler>
__HAL_RCC_USART3_CLK_ENABLE();
8001cee: 4b1a ldr r3, [pc, #104] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001cf0: 6d9b ldr r3, [r3, #88] @ 0x58
8001cf2: 4a19 ldr r2, [pc, #100] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001cf4: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8001cf8: 6593 str r3, [r2, #88] @ 0x58
8001cfa: 4b17 ldr r3, [pc, #92] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001cfc: 6d9b ldr r3, [r3, #88] @ 0x58
8001cfe: f403 2380 and.w r3, r3, #262144 @ 0x40000
8001d02: 613b str r3, [r7, #16]
8001d04: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOD_CLK_ENABLE();
8001d06: 4b14 ldr r3, [pc, #80] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001d08: 6cdb ldr r3, [r3, #76] @ 0x4c
8001d0a: 4a13 ldr r2, [pc, #76] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001d0c: f043 0308 orr.w r3, r3, #8
8001d10: 64d3 str r3, [r2, #76] @ 0x4c
8001d12: 4b11 ldr r3, [pc, #68] @ (8001d58 <HAL_UART_MspInit+0x138>)
8001d14: 6cdb ldr r3, [r3, #76] @ 0x4c
8001d16: f003 0308 and.w r3, r3, #8
8001d1a: 60fb str r3, [r7, #12]
8001d1c: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = INTERNAL_UART3_TX_Pin|INTERNAL_UART3_RX_Pin;
8001d1e: f44f 7340 mov.w r3, #768 @ 0x300
8001d22: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001d26: 2302 movs r3, #2
8001d28: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001d2c: 2300 movs r3, #0
8001d2e: f8c7 30ac str.w r3, [r7, #172] @ 0xac
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001d32: 2303 movs r3, #3
8001d34: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
8001d38: 2307 movs r3, #7
8001d3a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8001d3e: f107 03a4 add.w r3, r7, #164 @ 0xa4
8001d42: 4619 mov r1, r3
8001d44: 4807 ldr r0, [pc, #28] @ (8001d64 <HAL_UART_MspInit+0x144>)
8001d46: f001 fbd7 bl 80034f8 <HAL_GPIO_Init>
}
8001d4a: bf00 nop
8001d4c: 37b8 adds r7, #184 @ 0xb8
8001d4e: 46bd mov sp, r7
8001d50: bd80 pop {r7, pc}
8001d52: bf00 nop
8001d54: 40013800 .word 0x40013800
8001d58: 40021000 .word 0x40021000
8001d5c: 48000400 .word 0x48000400
8001d60: 40004800 .word 0x40004800
8001d64: 48000c00 .word 0x48000c00
08001d68 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001d68: b480 push {r7}
8001d6a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001d6c: bf00 nop
8001d6e: e7fd b.n 8001d6c <NMI_Handler+0x4>
08001d70 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001d70: b480 push {r7}
8001d72: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001d74: bf00 nop
8001d76: e7fd b.n 8001d74 <HardFault_Handler+0x4>
08001d78 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001d78: b480 push {r7}
8001d7a: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001d7c: bf00 nop
8001d7e: e7fd b.n 8001d7c <MemManage_Handler+0x4>
08001d80 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001d80: b480 push {r7}
8001d82: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001d84: bf00 nop
8001d86: e7fd b.n 8001d84 <BusFault_Handler+0x4>
08001d88 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001d88: b480 push {r7}
8001d8a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001d8c: bf00 nop
8001d8e: e7fd b.n 8001d8c <UsageFault_Handler+0x4>
08001d90 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001d90: b480 push {r7}
8001d92: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001d94: bf00 nop
8001d96: 46bd mov sp, r7
8001d98: f85d 7b04 ldr.w r7, [sp], #4
8001d9c: 4770 bx lr
08001d9e <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001d9e: b480 push {r7}
8001da0: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001da2: bf00 nop
8001da4: 46bd mov sp, r7
8001da6: f85d 7b04 ldr.w r7, [sp], #4
8001daa: 4770 bx lr
08001dac <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001dac: b480 push {r7}
8001dae: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001db0: bf00 nop
8001db2: 46bd mov sp, r7
8001db4: f85d 7b04 ldr.w r7, [sp], #4
8001db8: 4770 bx lr
08001dba <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001dba: b580 push {r7, lr}
8001dbc: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001dbe: f000 f995 bl 80020ec <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001dc2: bf00 nop
8001dc4: bd80 pop {r7, pc}
08001dc6 <EXTI9_5_IRQHandler>:
/**
* @brief This function handles EXTI line[9:5] interrupts.
*/
void EXTI9_5_IRQHandler(void)
{
8001dc6: b580 push {r7, lr}
8001dc8: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI9_5_IRQn 0 */
/* USER CODE END EXTI9_5_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(SPSGRF_915_GPIO3_EXTI5_Pin);
8001dca: 2020 movs r0, #32
8001dcc: f001 fd56 bl 800387c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(SPBTLE_RF_IRQ_EXTI6_Pin);
8001dd0: 2040 movs r0, #64 @ 0x40
8001dd2: f001 fd53 bl 800387c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(VL53L0X_GPIO1_EXTI7_Pin);
8001dd6: 2080 movs r0, #128 @ 0x80
8001dd8: f001 fd50 bl 800387c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(LSM3MDL_DRDY_EXTI8_Pin);
8001ddc: f44f 7080 mov.w r0, #256 @ 0x100
8001de0: f001 fd4c bl 800387c <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI9_5_IRQn 1 */
/* USER CODE END EXTI9_5_IRQn 1 */
}
8001de4: bf00 nop
8001de6: bd80 pop {r7, pc}
08001de8 <EXTI15_10_IRQHandler>:
/**
* @brief This function handles EXTI line[15:10] interrupts.
*/
void EXTI15_10_IRQHandler(void)
{
8001de8: b580 push {r7, lr}
8001dea: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(LPS22HB_INT_DRDY_EXTI0_Pin);
8001dec: f44f 6080 mov.w r0, #1024 @ 0x400
8001df0: f001 fd44 bl 800387c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(LSM6DSL_INT1_EXTI11_Pin);
8001df4: f44f 6000 mov.w r0, #2048 @ 0x800
8001df8: f001 fd40 bl 800387c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(BUTTON_EXTI13_Pin);
8001dfc: f44f 5000 mov.w r0, #8192 @ 0x2000
8001e00: f001 fd3c bl 800387c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(ARD_D2_Pin);
8001e04: f44f 4080 mov.w r0, #16384 @ 0x4000
8001e08: f001 fd38 bl 800387c <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(HTS221_DRDY_EXTI15_Pin);
8001e0c: f44f 4000 mov.w r0, #32768 @ 0x8000
8001e10: f001 fd34 bl 800387c <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 1 */
}
8001e14: bf00 nop
8001e16: bd80 pop {r7, pc}
08001e18 <TIM7_IRQHandler>:
/**
* @brief This function handles TIM7 global interrupt.
*/
void TIM7_IRQHandler(void)
{
8001e18: b580 push {r7, lr}
8001e1a: af00 add r7, sp, #0
/* USER CODE BEGIN TIM7_IRQn 0 */
/* USER CODE END TIM7_IRQn 0 */
HAL_TIM_IRQHandler(&htim7);
8001e1c: 4802 ldr r0, [pc, #8] @ (8001e28 <TIM7_IRQHandler+0x10>)
8001e1e: f004 fd5e bl 80068de <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM7_IRQn 1 */
/* USER CODE END TIM7_IRQn 1 */
}
8001e22: bf00 nop
8001e24: bd80 pop {r7, pc}
8001e26: bf00 nop
8001e28: 20000500 .word 0x20000500
08001e2c <OTG_FS_IRQHandler>:
/**
* @brief This function handles USB OTG FS global interrupt.
*/
void OTG_FS_IRQHandler(void)
{
8001e2c: b580 push {r7, lr}
8001e2e: af00 add r7, sp, #0
/* USER CODE BEGIN OTG_FS_IRQn 0 */
/* USER CODE END OTG_FS_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
8001e30: 4802 ldr r0, [pc, #8] @ (8001e3c <OTG_FS_IRQHandler+0x10>)
8001e32: f001 ffb6 bl 8003da2 <HAL_PCD_IRQHandler>
/* USER CODE BEGIN OTG_FS_IRQn 1 */
/* USER CODE END OTG_FS_IRQn 1 */
}
8001e36: bf00 nop
8001e38: bd80 pop {r7, pc}
8001e3a: bf00 nop
8001e3c: 20000bac .word 0x20000bac
08001e40 <_getpid>:
void initialise_monitor_handles()
{
}
int _getpid(void)
{
8001e40: b480 push {r7}
8001e42: af00 add r7, sp, #0
return 1;
8001e44: 2301 movs r3, #1
}
8001e46: 4618 mov r0, r3
8001e48: 46bd mov sp, r7
8001e4a: f85d 7b04 ldr.w r7, [sp], #4
8001e4e: 4770 bx lr
08001e50 <_kill>:
int _kill(int pid, int sig)
{
8001e50: b580 push {r7, lr}
8001e52: b082 sub sp, #8
8001e54: af00 add r7, sp, #0
8001e56: 6078 str r0, [r7, #4]
8001e58: 6039 str r1, [r7, #0]
(void)pid;
(void)sig;
errno = EINVAL;
8001e5a: f00a faab bl 800c3b4 <__errno>
8001e5e: 4603 mov r3, r0
8001e60: 2216 movs r2, #22
8001e62: 601a str r2, [r3, #0]
return -1;
8001e64: f04f 33ff mov.w r3, #4294967295
}
8001e68: 4618 mov r0, r3
8001e6a: 3708 adds r7, #8
8001e6c: 46bd mov sp, r7
8001e6e: bd80 pop {r7, pc}
08001e70 <_exit>:
void _exit (int status)
{
8001e70: b580 push {r7, lr}
8001e72: b082 sub sp, #8
8001e74: af00 add r7, sp, #0
8001e76: 6078 str r0, [r7, #4]
_kill(status, -1);
8001e78: f04f 31ff mov.w r1, #4294967295
8001e7c: 6878 ldr r0, [r7, #4]
8001e7e: f7ff ffe7 bl 8001e50 <_kill>
while (1) {} /* Make sure we hang here */
8001e82: bf00 nop
8001e84: e7fd b.n 8001e82 <_exit+0x12>
08001e86 <_read>:
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
8001e86: b580 push {r7, lr}
8001e88: b086 sub sp, #24
8001e8a: af00 add r7, sp, #0
8001e8c: 60f8 str r0, [r7, #12]
8001e8e: 60b9 str r1, [r7, #8]
8001e90: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001e92: 2300 movs r3, #0
8001e94: 617b str r3, [r7, #20]
8001e96: e00a b.n 8001eae <_read+0x28>
{
*ptr++ = __io_getchar();
8001e98: f3af 8000 nop.w
8001e9c: 4601 mov r1, r0
8001e9e: 68bb ldr r3, [r7, #8]
8001ea0: 1c5a adds r2, r3, #1
8001ea2: 60ba str r2, [r7, #8]
8001ea4: b2ca uxtb r2, r1
8001ea6: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001ea8: 697b ldr r3, [r7, #20]
8001eaa: 3301 adds r3, #1
8001eac: 617b str r3, [r7, #20]
8001eae: 697a ldr r2, [r7, #20]
8001eb0: 687b ldr r3, [r7, #4]
8001eb2: 429a cmp r2, r3
8001eb4: dbf0 blt.n 8001e98 <_read+0x12>
}
return len;
8001eb6: 687b ldr r3, [r7, #4]
}
8001eb8: 4618 mov r0, r3
8001eba: 3718 adds r7, #24
8001ebc: 46bd mov sp, r7
8001ebe: bd80 pop {r7, pc}
08001ec0 <_write>:
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
8001ec0: b580 push {r7, lr}
8001ec2: b086 sub sp, #24
8001ec4: af00 add r7, sp, #0
8001ec6: 60f8 str r0, [r7, #12]
8001ec8: 60b9 str r1, [r7, #8]
8001eca: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001ecc: 2300 movs r3, #0
8001ece: 617b str r3, [r7, #20]
8001ed0: e009 b.n 8001ee6 <_write+0x26>
{
__io_putchar(*ptr++);
8001ed2: 68bb ldr r3, [r7, #8]
8001ed4: 1c5a adds r2, r3, #1
8001ed6: 60ba str r2, [r7, #8]
8001ed8: 781b ldrb r3, [r3, #0]
8001eda: 4618 mov r0, r3
8001edc: f3af 8000 nop.w
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001ee0: 697b ldr r3, [r7, #20]
8001ee2: 3301 adds r3, #1
8001ee4: 617b str r3, [r7, #20]
8001ee6: 697a ldr r2, [r7, #20]
8001ee8: 687b ldr r3, [r7, #4]
8001eea: 429a cmp r2, r3
8001eec: dbf1 blt.n 8001ed2 <_write+0x12>
}
return len;
8001eee: 687b ldr r3, [r7, #4]
}
8001ef0: 4618 mov r0, r3
8001ef2: 3718 adds r7, #24
8001ef4: 46bd mov sp, r7
8001ef6: bd80 pop {r7, pc}
08001ef8 <_close>:
int _close(int file)
{
8001ef8: b480 push {r7}
8001efa: b083 sub sp, #12
8001efc: af00 add r7, sp, #0
8001efe: 6078 str r0, [r7, #4]
(void)file;
return -1;
8001f00: f04f 33ff mov.w r3, #4294967295
}
8001f04: 4618 mov r0, r3
8001f06: 370c adds r7, #12
8001f08: 46bd mov sp, r7
8001f0a: f85d 7b04 ldr.w r7, [sp], #4
8001f0e: 4770 bx lr
08001f10 <_fstat>:
int _fstat(int file, struct stat *st)
{
8001f10: b480 push {r7}
8001f12: b083 sub sp, #12
8001f14: af00 add r7, sp, #0
8001f16: 6078 str r0, [r7, #4]
8001f18: 6039 str r1, [r7, #0]
(void)file;
st->st_mode = S_IFCHR;
8001f1a: 683b ldr r3, [r7, #0]
8001f1c: f44f 5200 mov.w r2, #8192 @ 0x2000
8001f20: 605a str r2, [r3, #4]
return 0;
8001f22: 2300 movs r3, #0
}
8001f24: 4618 mov r0, r3
8001f26: 370c adds r7, #12
8001f28: 46bd mov sp, r7
8001f2a: f85d 7b04 ldr.w r7, [sp], #4
8001f2e: 4770 bx lr
08001f30 <_isatty>:
int _isatty(int file)
{
8001f30: b480 push {r7}
8001f32: b083 sub sp, #12
8001f34: af00 add r7, sp, #0
8001f36: 6078 str r0, [r7, #4]
(void)file;
return 1;
8001f38: 2301 movs r3, #1
}
8001f3a: 4618 mov r0, r3
8001f3c: 370c adds r7, #12
8001f3e: 46bd mov sp, r7
8001f40: f85d 7b04 ldr.w r7, [sp], #4
8001f44: 4770 bx lr
08001f46 <_lseek>:
int _lseek(int file, int ptr, int dir)
{
8001f46: b480 push {r7}
8001f48: b085 sub sp, #20
8001f4a: af00 add r7, sp, #0
8001f4c: 60f8 str r0, [r7, #12]
8001f4e: 60b9 str r1, [r7, #8]
8001f50: 607a str r2, [r7, #4]
(void)file;
(void)ptr;
(void)dir;
return 0;
8001f52: 2300 movs r3, #0
}
8001f54: 4618 mov r0, r3
8001f56: 3714 adds r7, #20
8001f58: 46bd mov sp, r7
8001f5a: f85d 7b04 ldr.w r7, [sp], #4
8001f5e: 4770 bx lr
08001f60 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8001f60: b580 push {r7, lr}
8001f62: b086 sub sp, #24
8001f64: af00 add r7, sp, #0
8001f66: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8001f68: 4a14 ldr r2, [pc, #80] @ (8001fbc <_sbrk+0x5c>)
8001f6a: 4b15 ldr r3, [pc, #84] @ (8001fc0 <_sbrk+0x60>)
8001f6c: 1ad3 subs r3, r2, r3
8001f6e: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8001f70: 697b ldr r3, [r7, #20]
8001f72: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8001f74: 4b13 ldr r3, [pc, #76] @ (8001fc4 <_sbrk+0x64>)
8001f76: 681b ldr r3, [r3, #0]
8001f78: 2b00 cmp r3, #0
8001f7a: d102 bne.n 8001f82 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8001f7c: 4b11 ldr r3, [pc, #68] @ (8001fc4 <_sbrk+0x64>)
8001f7e: 4a12 ldr r2, [pc, #72] @ (8001fc8 <_sbrk+0x68>)
8001f80: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8001f82: 4b10 ldr r3, [pc, #64] @ (8001fc4 <_sbrk+0x64>)
8001f84: 681a ldr r2, [r3, #0]
8001f86: 687b ldr r3, [r7, #4]
8001f88: 4413 add r3, r2
8001f8a: 693a ldr r2, [r7, #16]
8001f8c: 429a cmp r2, r3
8001f8e: d207 bcs.n 8001fa0 <_sbrk+0x40>
{
errno = ENOMEM;
8001f90: f00a fa10 bl 800c3b4 <__errno>
8001f94: 4603 mov r3, r0
8001f96: 220c movs r2, #12
8001f98: 601a str r2, [r3, #0]
return (void *)-1;
8001f9a: f04f 33ff mov.w r3, #4294967295
8001f9e: e009 b.n 8001fb4 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8001fa0: 4b08 ldr r3, [pc, #32] @ (8001fc4 <_sbrk+0x64>)
8001fa2: 681b ldr r3, [r3, #0]
8001fa4: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
8001fa6: 4b07 ldr r3, [pc, #28] @ (8001fc4 <_sbrk+0x64>)
8001fa8: 681a ldr r2, [r3, #0]
8001faa: 687b ldr r3, [r7, #4]
8001fac: 4413 add r3, r2
8001fae: 4a05 ldr r2, [pc, #20] @ (8001fc4 <_sbrk+0x64>)
8001fb0: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8001fb2: 68fb ldr r3, [r7, #12]
}
8001fb4: 4618 mov r0, r3
8001fb6: 3718 adds r7, #24
8001fb8: 46bd mov sp, r7
8001fba: bd80 pop {r7, pc}
8001fbc: 20018000 .word 0x20018000
8001fc0: 00000400 .word 0x00000400
8001fc4: 20000660 .word 0x20000660
8001fc8: 200011f0 .word 0x200011f0
08001fcc <SystemInit>:
* @brief Setup the microcontroller system.
* @retval None
*/
void SystemInit(void)
{
8001fcc: b480 push {r7}
8001fce: af00 add r7, sp, #0
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
8001fd0: 4b06 ldr r3, [pc, #24] @ (8001fec <SystemInit+0x20>)
8001fd2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8001fd6: 4a05 ldr r2, [pc, #20] @ (8001fec <SystemInit+0x20>)
8001fd8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8001fdc: f8c2 3088 str.w r3, [r2, #136] @ 0x88
#endif
}
8001fe0: bf00 nop
8001fe2: 46bd mov sp, r7
8001fe4: f85d 7b04 ldr.w r7, [sp], #4
8001fe8: 4770 bx lr
8001fea: bf00 nop
8001fec: e000ed00 .word 0xe000ed00
08001ff0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
8001ff0: f8df d034 ldr.w sp, [pc, #52] @ 8002028 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
8001ff4: f7ff ffea bl 8001fcc <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001ff8: 480c ldr r0, [pc, #48] @ (800202c <LoopForever+0x6>)
ldr r1, =_edata
8001ffa: 490d ldr r1, [pc, #52] @ (8002030 <LoopForever+0xa>)
ldr r2, =_sidata
8001ffc: 4a0d ldr r2, [pc, #52] @ (8002034 <LoopForever+0xe>)
movs r3, #0
8001ffe: 2300 movs r3, #0
b LoopCopyDataInit
8002000: e002 b.n 8002008 <LoopCopyDataInit>
08002002 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8002002: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8002004: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8002006: 3304 adds r3, #4
08002008 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8002008: 18c4 adds r4, r0, r3
cmp r4, r1
800200a: 428c cmp r4, r1
bcc CopyDataInit
800200c: d3f9 bcc.n 8002002 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800200e: 4a0a ldr r2, [pc, #40] @ (8002038 <LoopForever+0x12>)
ldr r4, =_ebss
8002010: 4c0a ldr r4, [pc, #40] @ (800203c <LoopForever+0x16>)
movs r3, #0
8002012: 2300 movs r3, #0
b LoopFillZerobss
8002014: e001 b.n 800201a <LoopFillZerobss>
08002016 <FillZerobss>:
FillZerobss:
str r3, [r2]
8002016: 6013 str r3, [r2, #0]
adds r2, r2, #4
8002018: 3204 adds r2, #4
0800201a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800201a: 42a2 cmp r2, r4
bcc FillZerobss
800201c: d3fb bcc.n 8002016 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800201e: f00a f9cf bl 800c3c0 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8002022: f7fe ff57 bl 8000ed4 <main>
08002026 <LoopForever>:
LoopForever:
b LoopForever
8002026: e7fe b.n 8002026 <LoopForever>
ldr sp, =_estack /* Set stack pointer */
8002028: 20018000 .word 0x20018000
ldr r0, =_sdata
800202c: 20000000 .word 0x20000000
ldr r1, =_edata
8002030: 20000300 .word 0x20000300
ldr r2, =_sidata
8002034: 0800e58c .word 0x0800e58c
ldr r2, =_sbss
8002038: 20000300 .word 0x20000300
ldr r4, =_ebss
800203c: 200011f0 .word 0x200011f0
08002040 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8002040: e7fe b.n 8002040 <ADC1_2_IRQHandler>
08002042 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8002042: b580 push {r7, lr}
8002044: b082 sub sp, #8
8002046: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8002048: 2300 movs r3, #0
800204a: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800204c: 2003 movs r0, #3
800204e: f001 f905 bl 800325c <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8002052: 2000 movs r0, #0
8002054: f000 f80e bl 8002074 <HAL_InitTick>
8002058: 4603 mov r3, r0
800205a: 2b00 cmp r3, #0
800205c: d002 beq.n 8002064 <HAL_Init+0x22>
{
status = HAL_ERROR;
800205e: 2301 movs r3, #1
8002060: 71fb strb r3, [r7, #7]
8002062: e001 b.n 8002068 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8002064: f7ff fbb6 bl 80017d4 <HAL_MspInit>
}
/* Return function status */
return status;
8002068: 79fb ldrb r3, [r7, #7]
}
800206a: 4618 mov r0, r3
800206c: 3708 adds r7, #8
800206e: 46bd mov sp, r7
8002070: bd80 pop {r7, pc}
...
08002074 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8002074: b580 push {r7, lr}
8002076: b084 sub sp, #16
8002078: af00 add r7, sp, #0
800207a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800207c: 2300 movs r3, #0
800207e: 73fb strb r3, [r7, #15]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8002080: 4b17 ldr r3, [pc, #92] @ (80020e0 <HAL_InitTick+0x6c>)
8002082: 781b ldrb r3, [r3, #0]
8002084: 2b00 cmp r3, #0
8002086: d023 beq.n 80020d0 <HAL_InitTick+0x5c>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
8002088: 4b16 ldr r3, [pc, #88] @ (80020e4 <HAL_InitTick+0x70>)
800208a: 681a ldr r2, [r3, #0]
800208c: 4b14 ldr r3, [pc, #80] @ (80020e0 <HAL_InitTick+0x6c>)
800208e: 781b ldrb r3, [r3, #0]
8002090: 4619 mov r1, r3
8002092: f44f 737a mov.w r3, #1000 @ 0x3e8
8002096: fbb3 f3f1 udiv r3, r3, r1
800209a: fbb2 f3f3 udiv r3, r2, r3
800209e: 4618 mov r0, r3
80020a0: f001 f911 bl 80032c6 <HAL_SYSTICK_Config>
80020a4: 4603 mov r3, r0
80020a6: 2b00 cmp r3, #0
80020a8: d10f bne.n 80020ca <HAL_InitTick+0x56>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80020aa: 687b ldr r3, [r7, #4]
80020ac: 2b0f cmp r3, #15
80020ae: d809 bhi.n 80020c4 <HAL_InitTick+0x50>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80020b0: 2200 movs r2, #0
80020b2: 6879 ldr r1, [r7, #4]
80020b4: f04f 30ff mov.w r0, #4294967295
80020b8: f001 f8db bl 8003272 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80020bc: 4a0a ldr r2, [pc, #40] @ (80020e8 <HAL_InitTick+0x74>)
80020be: 687b ldr r3, [r7, #4]
80020c0: 6013 str r3, [r2, #0]
80020c2: e007 b.n 80020d4 <HAL_InitTick+0x60>
}
else
{
status = HAL_ERROR;
80020c4: 2301 movs r3, #1
80020c6: 73fb strb r3, [r7, #15]
80020c8: e004 b.n 80020d4 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
80020ca: 2301 movs r3, #1
80020cc: 73fb strb r3, [r7, #15]
80020ce: e001 b.n 80020d4 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
80020d0: 2301 movs r3, #1
80020d2: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
80020d4: 7bfb ldrb r3, [r7, #15]
}
80020d6: 4618 mov r0, r3
80020d8: 3710 adds r7, #16
80020da: 46bd mov sp, r7
80020dc: bd80 pop {r7, pc}
80020de: bf00 nop
80020e0: 20000008 .word 0x20000008
80020e4: 20000000 .word 0x20000000
80020e8: 20000004 .word 0x20000004
080020ec <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80020ec: b480 push {r7}
80020ee: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
80020f0: 4b06 ldr r3, [pc, #24] @ (800210c <HAL_IncTick+0x20>)
80020f2: 781b ldrb r3, [r3, #0]
80020f4: 461a mov r2, r3
80020f6: 4b06 ldr r3, [pc, #24] @ (8002110 <HAL_IncTick+0x24>)
80020f8: 681b ldr r3, [r3, #0]
80020fa: 4413 add r3, r2
80020fc: 4a04 ldr r2, [pc, #16] @ (8002110 <HAL_IncTick+0x24>)
80020fe: 6013 str r3, [r2, #0]
}
8002100: bf00 nop
8002102: 46bd mov sp, r7
8002104: f85d 7b04 ldr.w r7, [sp], #4
8002108: 4770 bx lr
800210a: bf00 nop
800210c: 20000008 .word 0x20000008
8002110: 20000664 .word 0x20000664
08002114 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8002114: b480 push {r7}
8002116: af00 add r7, sp, #0
return uwTick;
8002118: 4b03 ldr r3, [pc, #12] @ (8002128 <HAL_GetTick+0x14>)
800211a: 681b ldr r3, [r3, #0]
}
800211c: 4618 mov r0, r3
800211e: 46bd mov sp, r7
8002120: f85d 7b04 ldr.w r7, [sp], #4
8002124: 4770 bx lr
8002126: bf00 nop
8002128: 20000664 .word 0x20000664
0800212c <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
800212c: b580 push {r7, lr}
800212e: b084 sub sp, #16
8002130: af00 add r7, sp, #0
8002132: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8002134: f7ff ffee bl 8002114 <HAL_GetTick>
8002138: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
800213a: 687b ldr r3, [r7, #4]
800213c: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
800213e: 68fb ldr r3, [r7, #12]
8002140: f1b3 3fff cmp.w r3, #4294967295
8002144: d005 beq.n 8002152 <HAL_Delay+0x26>
{
wait += (uint32_t)uwTickFreq;
8002146: 4b0a ldr r3, [pc, #40] @ (8002170 <HAL_Delay+0x44>)
8002148: 781b ldrb r3, [r3, #0]
800214a: 461a mov r2, r3
800214c: 68fb ldr r3, [r7, #12]
800214e: 4413 add r3, r2
8002150: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8002152: bf00 nop
8002154: f7ff ffde bl 8002114 <HAL_GetTick>
8002158: 4602 mov r2, r0
800215a: 68bb ldr r3, [r7, #8]
800215c: 1ad3 subs r3, r2, r3
800215e: 68fa ldr r2, [r7, #12]
8002160: 429a cmp r2, r3
8002162: d8f7 bhi.n 8002154 <HAL_Delay+0x28>
{
}
}
8002164: bf00 nop
8002166: bf00 nop
8002168: 3710 adds r7, #16
800216a: 46bd mov sp, r7
800216c: bd80 pop {r7, pc}
800216e: bf00 nop
8002170: 20000008 .word 0x20000008
08002174 <LL_ADC_SetCommonClock>:
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
8002174: b480 push {r7}
8002176: b083 sub sp, #12
8002178: af00 add r7, sp, #0
800217a: 6078 str r0, [r7, #4]
800217c: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
800217e: 687b ldr r3, [r7, #4]
8002180: 689b ldr r3, [r3, #8]
8002182: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000
8002186: 683b ldr r3, [r7, #0]
8002188: 431a orrs r2, r3
800218a: 687b ldr r3, [r7, #4]
800218c: 609a str r2, [r3, #8]
}
800218e: bf00 nop
8002190: 370c adds r7, #12
8002192: 46bd mov sp, r7
8002194: f85d 7b04 ldr.w r7, [sp], #4
8002198: 4770 bx lr
0800219a <LL_ADC_SetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
800219a: b480 push {r7}
800219c: b083 sub sp, #12
800219e: af00 add r7, sp, #0
80021a0: 6078 str r0, [r7, #4]
80021a2: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
80021a4: 687b ldr r3, [r7, #4]
80021a6: 689b ldr r3, [r3, #8]
80021a8: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000
80021ac: 683b ldr r3, [r7, #0]
80021ae: 431a orrs r2, r3
80021b0: 687b ldr r3, [r7, #4]
80021b2: 609a str r2, [r3, #8]
}
80021b4: bf00 nop
80021b6: 370c adds r7, #12
80021b8: 46bd mov sp, r7
80021ba: f85d 7b04 ldr.w r7, [sp], #4
80021be: 4770 bx lr
080021c0 <LL_ADC_GetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
{
80021c0: b480 push {r7}
80021c2: b083 sub sp, #12
80021c4: af00 add r7, sp, #0
80021c6: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
80021c8: 687b ldr r3, [r7, #4]
80021ca: 689b ldr r3, [r3, #8]
80021cc: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000
}
80021d0: 4618 mov r0, r3
80021d2: 370c adds r7, #12
80021d4: 46bd mov sp, r7
80021d6: f85d 7b04 ldr.w r7, [sp], #4
80021da: 4770 bx lr
080021dc <LL_ADC_SetOffset>:
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
80021dc: b480 push {r7}
80021de: b087 sub sp, #28
80021e0: af00 add r7, sp, #0
80021e2: 60f8 str r0, [r7, #12]
80021e4: 60b9 str r1, [r7, #8]
80021e6: 607a str r2, [r7, #4]
80021e8: 603b str r3, [r7, #0]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
80021ea: 68fb ldr r3, [r7, #12]
80021ec: 3360 adds r3, #96 @ 0x60
80021ee: 461a mov r2, r3
80021f0: 68bb ldr r3, [r7, #8]
80021f2: 009b lsls r3, r3, #2
80021f4: 4413 add r3, r2
80021f6: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
80021f8: 697b ldr r3, [r7, #20]
80021fa: 681a ldr r2, [r3, #0]
80021fc: 4b08 ldr r3, [pc, #32] @ (8002220 <LL_ADC_SetOffset+0x44>)
80021fe: 4013 ands r3, r2
8002200: 687a ldr r2, [r7, #4]
8002202: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000
8002206: 683a ldr r2, [r7, #0]
8002208: 430a orrs r2, r1
800220a: 4313 orrs r3, r2
800220c: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
8002210: 697b ldr r3, [r7, #20]
8002212: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
}
8002214: bf00 nop
8002216: 371c adds r7, #28
8002218: 46bd mov sp, r7
800221a: f85d 7b04 ldr.w r7, [sp], #4
800221e: 4770 bx lr
8002220: 03fff000 .word 0x03fff000
08002224 <LL_ADC_GetOffsetChannel>:
* (1, 2, 3, 4) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
8002224: b480 push {r7}
8002226: b085 sub sp, #20
8002228: af00 add r7, sp, #0
800222a: 6078 str r0, [r7, #4]
800222c: 6039 str r1, [r7, #0]
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
800222e: 687b ldr r3, [r7, #4]
8002230: 3360 adds r3, #96 @ 0x60
8002232: 461a mov r2, r3
8002234: 683b ldr r3, [r7, #0]
8002236: 009b lsls r3, r3, #2
8002238: 4413 add r3, r2
800223a: 60fb str r3, [r7, #12]
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
800223c: 68fb ldr r3, [r7, #12]
800223e: 681b ldr r3, [r3, #0]
8002240: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
}
8002244: 4618 mov r0, r3
8002246: 3714 adds r7, #20
8002248: 46bd mov sp, r7
800224a: f85d 7b04 ldr.w r7, [sp], #4
800224e: 4770 bx lr
08002250 <LL_ADC_SetOffsetState>:
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
8002250: b480 push {r7}
8002252: b087 sub sp, #28
8002254: af00 add r7, sp, #0
8002256: 60f8 str r0, [r7, #12]
8002258: 60b9 str r1, [r7, #8]
800225a: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
800225c: 68fb ldr r3, [r7, #12]
800225e: 3360 adds r3, #96 @ 0x60
8002260: 461a mov r2, r3
8002262: 68bb ldr r3, [r7, #8]
8002264: 009b lsls r3, r3, #2
8002266: 4413 add r3, r2
8002268: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
800226a: 697b ldr r3, [r7, #20]
800226c: 681b ldr r3, [r3, #0]
800226e: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8002272: 687b ldr r3, [r7, #4]
8002274: 431a orrs r2, r3
8002276: 697b ldr r3, [r7, #20]
8002278: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN,
OffsetState);
}
800227a: bf00 nop
800227c: 371c adds r7, #28
800227e: 46bd mov sp, r7
8002280: f85d 7b04 ldr.w r7, [sp], #4
8002284: 4770 bx lr
08002286 <LL_ADC_REG_SetSequencerRanks>:
* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
8002286: b480 push {r7}
8002288: b087 sub sp, #28
800228a: af00 add r7, sp, #0
800228c: 60f8 str r0, [r7, #12]
800228e: 60b9 str r1, [r7, #8]
8002290: 607a str r2, [r7, #4]
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
8002292: 68fb ldr r3, [r7, #12]
8002294: 3330 adds r3, #48 @ 0x30
8002296: 461a mov r2, r3
8002298: 68bb ldr r3, [r7, #8]
800229a: 0a1b lsrs r3, r3, #8
800229c: 009b lsls r3, r3, #2
800229e: f003 030c and.w r3, r3, #12
80022a2: 4413 add r3, r2
80022a4: 617b str r3, [r7, #20]
((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
80022a6: 697b ldr r3, [r7, #20]
80022a8: 681a ldr r2, [r3, #0]
80022aa: 68bb ldr r3, [r7, #8]
80022ac: f003 031f and.w r3, r3, #31
80022b0: 211f movs r1, #31
80022b2: fa01 f303 lsl.w r3, r1, r3
80022b6: 43db mvns r3, r3
80022b8: 401a ands r2, r3
80022ba: 687b ldr r3, [r7, #4]
80022bc: 0e9b lsrs r3, r3, #26
80022be: f003 011f and.w r1, r3, #31
80022c2: 68bb ldr r3, [r7, #8]
80022c4: f003 031f and.w r3, r3, #31
80022c8: fa01 f303 lsl.w r3, r1, r3
80022cc: 431a orrs r2, r3
80022ce: 697b ldr r3, [r7, #20]
80022d0: 601a str r2, [r3, #0]
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<< (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
80022d2: bf00 nop
80022d4: 371c adds r7, #28
80022d6: 46bd mov sp, r7
80022d8: f85d 7b04 ldr.w r7, [sp], #4
80022dc: 4770 bx lr
080022de <LL_ADC_SetChannelSamplingTime>:
* can be replaced by 3.5 ADC clock cycles.
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
80022de: b480 push {r7}
80022e0: b087 sub sp, #28
80022e2: af00 add r7, sp, #0
80022e4: 60f8 str r0, [r7, #12]
80022e6: 60b9 str r1, [r7, #8]
80022e8: 607a str r2, [r7, #4]
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
80022ea: 68fb ldr r3, [r7, #12]
80022ec: 3314 adds r3, #20
80022ee: 461a mov r2, r3
80022f0: 68bb ldr r3, [r7, #8]
80022f2: 0e5b lsrs r3, r3, #25
80022f4: 009b lsls r3, r3, #2
80022f6: f003 0304 and.w r3, r3, #4
80022fa: 4413 add r3, r2
80022fc: 617b str r3, [r7, #20]
((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
80022fe: 697b ldr r3, [r7, #20]
8002300: 681a ldr r2, [r3, #0]
8002302: 68bb ldr r3, [r7, #8]
8002304: 0d1b lsrs r3, r3, #20
8002306: f003 031f and.w r3, r3, #31
800230a: 2107 movs r1, #7
800230c: fa01 f303 lsl.w r3, r1, r3
8002310: 43db mvns r3, r3
8002312: 401a ands r2, r3
8002314: 68bb ldr r3, [r7, #8]
8002316: 0d1b lsrs r3, r3, #20
8002318: f003 031f and.w r3, r3, #31
800231c: 6879 ldr r1, [r7, #4]
800231e: fa01 f303 lsl.w r3, r1, r3
8002322: 431a orrs r2, r3
8002324: 697b ldr r3, [r7, #20]
8002326: 601a str r2, [r3, #0]
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
8002328: bf00 nop
800232a: 371c adds r7, #28
800232c: 46bd mov sp, r7
800232e: f85d 7b04 ldr.w r7, [sp], #4
8002332: 4770 bx lr
08002334 <LL_ADC_SetChannelSingleDiff>:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
8002334: b480 push {r7}
8002336: b085 sub sp, #20
8002338: af00 add r7, sp, #0
800233a: 60f8 str r0, [r7, #12]
800233c: 60b9 str r1, [r7, #8]
800233e: 607a str r2, [r7, #4]
/* Bits of channels in single or differential mode are set only for */
/* differential mode (for single mode, mask of bits allowed to be set is */
/* shifted out of range of bits of channels in single or differential mode. */
MODIFY_REG(ADCx->DIFSEL,
8002340: 68fb ldr r3, [r7, #12]
8002342: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0
8002346: 68bb ldr r3, [r7, #8]
8002348: f3c3 0312 ubfx r3, r3, #0, #19
800234c: 43db mvns r3, r3
800234e: 401a ands r2, r3
8002350: 687b ldr r3, [r7, #4]
8002352: f003 0318 and.w r3, r3, #24
8002356: 4908 ldr r1, [pc, #32] @ (8002378 <LL_ADC_SetChannelSingleDiff+0x44>)
8002358: 40d9 lsrs r1, r3
800235a: 68bb ldr r3, [r7, #8]
800235c: 400b ands r3, r1
800235e: f3c3 0312 ubfx r3, r3, #0, #19
8002362: 431a orrs r2, r3
8002364: 68fb ldr r3, [r7, #12]
8002366: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
& (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
}
800236a: bf00 nop
800236c: 3714 adds r7, #20
800236e: 46bd mov sp, r7
8002370: f85d 7b04 ldr.w r7, [sp], #4
8002374: 4770 bx lr
8002376: bf00 nop
8002378: 0007ffff .word 0x0007ffff
0800237c <LL_ADC_DisableDeepPowerDown>:
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
800237c: b480 push {r7}
800237e: b083 sub sp, #12
8002380: af00 add r7, sp, #0
8002382: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
8002384: 687b ldr r3, [r7, #4]
8002386: 689b ldr r3, [r3, #8]
8002388: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000
800238c: f023 033f bic.w r3, r3, #63 @ 0x3f
8002390: 687a ldr r2, [r7, #4]
8002392: 6093 str r3, [r2, #8]
}
8002394: bf00 nop
8002396: 370c adds r7, #12
8002398: 46bd mov sp, r7
800239a: f85d 7b04 ldr.w r7, [sp], #4
800239e: 4770 bx lr
080023a0 <LL_ADC_IsDeepPowerDownEnabled>:
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
{
80023a0: b480 push {r7}
80023a2: b083 sub sp, #12
80023a4: af00 add r7, sp, #0
80023a6: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
80023a8: 687b ldr r3, [r7, #4]
80023aa: 689b ldr r3, [r3, #8]
80023ac: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80023b0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80023b4: d101 bne.n 80023ba <LL_ADC_IsDeepPowerDownEnabled+0x1a>
80023b6: 2301 movs r3, #1
80023b8: e000 b.n 80023bc <LL_ADC_IsDeepPowerDownEnabled+0x1c>
80023ba: 2300 movs r3, #0
}
80023bc: 4618 mov r0, r3
80023be: 370c adds r7, #12
80023c0: 46bd mov sp, r7
80023c2: f85d 7b04 ldr.w r7, [sp], #4
80023c6: 4770 bx lr
080023c8 <LL_ADC_EnableInternalRegulator>:
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
80023c8: b480 push {r7}
80023ca: b083 sub sp, #12
80023cc: af00 add r7, sp, #0
80023ce: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
80023d0: 687b ldr r3, [r7, #4]
80023d2: 689b ldr r3, [r3, #8]
80023d4: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000
80023d8: f023 033f bic.w r3, r3, #63 @ 0x3f
80023dc: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000
80023e0: 687b ldr r3, [r7, #4]
80023e2: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
80023e4: bf00 nop
80023e6: 370c adds r7, #12
80023e8: 46bd mov sp, r7
80023ea: f85d 7b04 ldr.w r7, [sp], #4
80023ee: 4770 bx lr
080023f0 <LL_ADC_IsInternalRegulatorEnabled>:
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
{
80023f0: b480 push {r7}
80023f2: b083 sub sp, #12
80023f4: af00 add r7, sp, #0
80023f6: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
80023f8: 687b ldr r3, [r7, #4]
80023fa: 689b ldr r3, [r3, #8]
80023fc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002400: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8002404: d101 bne.n 800240a <LL_ADC_IsInternalRegulatorEnabled+0x1a>
8002406: 2301 movs r3, #1
8002408: e000 b.n 800240c <LL_ADC_IsInternalRegulatorEnabled+0x1c>
800240a: 2300 movs r3, #0
}
800240c: 4618 mov r0, r3
800240e: 370c adds r7, #12
8002410: 46bd mov sp, r7
8002412: f85d 7b04 ldr.w r7, [sp], #4
8002416: 4770 bx lr
08002418 <LL_ADC_IsEnabled>:
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
{
8002418: b480 push {r7}
800241a: b083 sub sp, #12
800241c: af00 add r7, sp, #0
800241e: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8002420: 687b ldr r3, [r7, #4]
8002422: 689b ldr r3, [r3, #8]
8002424: f003 0301 and.w r3, r3, #1
8002428: 2b01 cmp r3, #1
800242a: d101 bne.n 8002430 <LL_ADC_IsEnabled+0x18>
800242c: 2301 movs r3, #1
800242e: e000 b.n 8002432 <LL_ADC_IsEnabled+0x1a>
8002430: 2300 movs r3, #0
}
8002432: 4618 mov r0, r3
8002434: 370c adds r7, #12
8002436: 46bd mov sp, r7
8002438: f85d 7b04 ldr.w r7, [sp], #4
800243c: 4770 bx lr
0800243e <LL_ADC_REG_IsConversionOngoing>:
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
800243e: b480 push {r7}
8002440: b083 sub sp, #12
8002442: af00 add r7, sp, #0
8002444: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8002446: 687b ldr r3, [r7, #4]
8002448: 689b ldr r3, [r3, #8]
800244a: f003 0304 and.w r3, r3, #4
800244e: 2b04 cmp r3, #4
8002450: d101 bne.n 8002456 <LL_ADC_REG_IsConversionOngoing+0x18>
8002452: 2301 movs r3, #1
8002454: e000 b.n 8002458 <LL_ADC_REG_IsConversionOngoing+0x1a>
8002456: 2300 movs r3, #0
}
8002458: 4618 mov r0, r3
800245a: 370c adds r7, #12
800245c: 46bd mov sp, r7
800245e: f85d 7b04 ldr.w r7, [sp], #4
8002462: 4770 bx lr
08002464 <LL_ADC_INJ_IsConversionOngoing>:
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
8002464: b480 push {r7}
8002466: b083 sub sp, #12
8002468: af00 add r7, sp, #0
800246a: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
800246c: 687b ldr r3, [r7, #4]
800246e: 689b ldr r3, [r3, #8]
8002470: f003 0308 and.w r3, r3, #8
8002474: 2b08 cmp r3, #8
8002476: d101 bne.n 800247c <LL_ADC_INJ_IsConversionOngoing+0x18>
8002478: 2301 movs r3, #1
800247a: e000 b.n 800247e <LL_ADC_INJ_IsConversionOngoing+0x1a>
800247c: 2300 movs r3, #0
}
800247e: 4618 mov r0, r3
8002480: 370c adds r7, #12
8002482: 46bd mov sp, r7
8002484: f85d 7b04 ldr.w r7, [sp], #4
8002488: 4770 bx lr
...
0800248c <HAL_ADC_Init>:
* without disabling the other ADCs.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
800248c: b590 push {r4, r7, lr}
800248e: b089 sub sp, #36 @ 0x24
8002490: af00 add r7, sp, #0
8002492: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002494: 2300 movs r3, #0
8002496: 77fb strb r3, [r7, #31]
uint32_t tmp_cfgr;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0UL;
8002498: 2300 movs r3, #0
800249a: 60fb str r3, [r7, #12]
/* Check ADC handle */
if (hadc == NULL)
800249c: 687b ldr r3, [r7, #4]
800249e: 2b00 cmp r3, #0
80024a0: d101 bne.n 80024a6 <HAL_ADC_Init+0x1a>
{
return HAL_ERROR;
80024a2: 2301 movs r3, #1
80024a4: e130 b.n 8002708 <HAL_ADC_Init+0x27c>
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
80024a6: 687b ldr r3, [r7, #4]
80024a8: 691b ldr r3, [r3, #16]
80024aa: 2b00 cmp r3, #0
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
80024ac: 687b ldr r3, [r7, #4]
80024ae: 6d5b ldr r3, [r3, #84] @ 0x54
80024b0: 2b00 cmp r3, #0
80024b2: d109 bne.n 80024c8 <HAL_ADC_Init+0x3c>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80024b4: 6878 ldr r0, [r7, #4]
80024b6: f7ff f9b1 bl 800181c <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
80024ba: 687b ldr r3, [r7, #4]
80024bc: 2200 movs r2, #0
80024be: 659a str r2, [r3, #88] @ 0x58
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
80024c0: 687b ldr r3, [r7, #4]
80024c2: 2200 movs r2, #0
80024c4: f883 2050 strb.w r2, [r3, #80] @ 0x50
}
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
80024c8: 687b ldr r3, [r7, #4]
80024ca: 681b ldr r3, [r3, #0]
80024cc: 4618 mov r0, r3
80024ce: f7ff ff67 bl 80023a0 <LL_ADC_IsDeepPowerDownEnabled>
80024d2: 4603 mov r3, r0
80024d4: 2b00 cmp r3, #0
80024d6: d004 beq.n 80024e2 <HAL_ADC_Init+0x56>
{
/* Disable ADC deep power down mode */
LL_ADC_DisableDeepPowerDown(hadc->Instance);
80024d8: 687b ldr r3, [r7, #4]
80024da: 681b ldr r3, [r3, #0]
80024dc: 4618 mov r0, r3
80024de: f7ff ff4d bl 800237c <LL_ADC_DisableDeepPowerDown>
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
80024e2: 687b ldr r3, [r7, #4]
80024e4: 681b ldr r3, [r3, #0]
80024e6: 4618 mov r0, r3
80024e8: f7ff ff82 bl 80023f0 <LL_ADC_IsInternalRegulatorEnabled>
80024ec: 4603 mov r3, r0
80024ee: 2b00 cmp r3, #0
80024f0: d115 bne.n 800251e <HAL_ADC_Init+0x92>
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
80024f2: 687b ldr r3, [r7, #4]
80024f4: 681b ldr r3, [r3, #0]
80024f6: 4618 mov r0, r3
80024f8: f7ff ff66 bl 80023c8 <LL_ADC_EnableInternalRegulator>
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
80024fc: 4b84 ldr r3, [pc, #528] @ (8002710 <HAL_ADC_Init+0x284>)
80024fe: 681b ldr r3, [r3, #0]
8002500: 099b lsrs r3, r3, #6
8002502: 4a84 ldr r2, [pc, #528] @ (8002714 <HAL_ADC_Init+0x288>)
8002504: fba2 2303 umull r2, r3, r2, r3
8002508: 099b lsrs r3, r3, #6
800250a: 3301 adds r3, #1
800250c: 005b lsls r3, r3, #1
800250e: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002510: e002 b.n 8002518 <HAL_ADC_Init+0x8c>
{
wait_loop_index--;
8002512: 68fb ldr r3, [r7, #12]
8002514: 3b01 subs r3, #1
8002516: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002518: 68fb ldr r3, [r7, #12]
800251a: 2b00 cmp r3, #0
800251c: d1f9 bne.n 8002512 <HAL_ADC_Init+0x86>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
800251e: 687b ldr r3, [r7, #4]
8002520: 681b ldr r3, [r3, #0]
8002522: 4618 mov r0, r3
8002524: f7ff ff64 bl 80023f0 <LL_ADC_IsInternalRegulatorEnabled>
8002528: 4603 mov r3, r0
800252a: 2b00 cmp r3, #0
800252c: d10d bne.n 800254a <HAL_ADC_Init+0xbe>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800252e: 687b ldr r3, [r7, #4]
8002530: 6d5b ldr r3, [r3, #84] @ 0x54
8002532: f043 0210 orr.w r2, r3, #16
8002536: 687b ldr r3, [r7, #4]
8002538: 655a str r2, [r3, #84] @ 0x54
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800253a: 687b ldr r3, [r7, #4]
800253c: 6d9b ldr r3, [r3, #88] @ 0x58
800253e: f043 0201 orr.w r2, r3, #1
8002542: 687b ldr r3, [r7, #4]
8002544: 659a str r2, [r3, #88] @ 0x58
tmp_hal_status = HAL_ERROR;
8002546: 2301 movs r3, #1
8002548: 77fb strb r3, [r7, #31]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
800254a: 687b ldr r3, [r7, #4]
800254c: 681b ldr r3, [r3, #0]
800254e: 4618 mov r0, r3
8002550: f7ff ff75 bl 800243e <LL_ADC_REG_IsConversionOngoing>
8002554: 6178 str r0, [r7, #20]
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8002556: 687b ldr r3, [r7, #4]
8002558: 6d5b ldr r3, [r3, #84] @ 0x54
800255a: f003 0310 and.w r3, r3, #16
800255e: 2b00 cmp r3, #0
8002560: f040 80c9 bne.w 80026f6 <HAL_ADC_Init+0x26a>
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
8002564: 697b ldr r3, [r7, #20]
8002566: 2b00 cmp r3, #0
8002568: f040 80c5 bne.w 80026f6 <HAL_ADC_Init+0x26a>
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800256c: 687b ldr r3, [r7, #4]
800256e: 6d5b ldr r3, [r3, #84] @ 0x54
8002570: f423 7381 bic.w r3, r3, #258 @ 0x102
8002574: f043 0202 orr.w r2, r3, #2
8002578: 687b ldr r3, [r7, #4]
800257a: 655a str r2, [r3, #84] @ 0x54
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - clock configuration */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
800257c: 687b ldr r3, [r7, #4]
800257e: 681b ldr r3, [r3, #0]
8002580: 4618 mov r0, r3
8002582: f7ff ff49 bl 8002418 <LL_ADC_IsEnabled>
8002586: 4603 mov r3, r0
8002588: 2b00 cmp r3, #0
800258a: d115 bne.n 80025b8 <HAL_ADC_Init+0x12c>
{
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
800258c: 4862 ldr r0, [pc, #392] @ (8002718 <HAL_ADC_Init+0x28c>)
800258e: f7ff ff43 bl 8002418 <LL_ADC_IsEnabled>
8002592: 4604 mov r4, r0
8002594: 4861 ldr r0, [pc, #388] @ (800271c <HAL_ADC_Init+0x290>)
8002596: f7ff ff3f bl 8002418 <LL_ADC_IsEnabled>
800259a: 4603 mov r3, r0
800259c: 431c orrs r4, r3
800259e: 4860 ldr r0, [pc, #384] @ (8002720 <HAL_ADC_Init+0x294>)
80025a0: f7ff ff3a bl 8002418 <LL_ADC_IsEnabled>
80025a4: 4603 mov r3, r0
80025a6: 4323 orrs r3, r4
80025a8: 2b00 cmp r3, #0
80025aa: d105 bne.n 80025b8 <HAL_ADC_Init+0x12c>
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
/* HAL_ADCEx_MultiModeConfigChannel() ) */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
80025ac: 687b ldr r3, [r7, #4]
80025ae: 685b ldr r3, [r3, #4]
80025b0: 4619 mov r1, r3
80025b2: 485c ldr r0, [pc, #368] @ (8002724 <HAL_ADC_Init+0x298>)
80025b4: f7ff fdde bl 8002174 <LL_ADC_SetCommonClock>
/* - external trigger polarity Init.ExternalTrigConvEdge */
/* - continuous conversion mode Init.ContinuousConvMode */
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80025b8: 687b ldr r3, [r7, #4]
80025ba: 7e5b ldrb r3, [r3, #25]
80025bc: 035a lsls r2, r3, #13
hadc->Init.Overrun |
80025be: 687b ldr r3, [r7, #4]
80025c0: 6b5b ldr r3, [r3, #52] @ 0x34
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80025c2: 431a orrs r2, r3
hadc->Init.DataAlign |
80025c4: 687b ldr r3, [r7, #4]
80025c6: 68db ldr r3, [r3, #12]
hadc->Init.Overrun |
80025c8: 431a orrs r2, r3
hadc->Init.Resolution |
80025ca: 687b ldr r3, [r7, #4]
80025cc: 689b ldr r3, [r3, #8]
hadc->Init.DataAlign |
80025ce: 431a orrs r2, r3
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
80025d0: 687b ldr r3, [r7, #4]
80025d2: f893 3020 ldrb.w r3, [r3, #32]
80025d6: 041b lsls r3, r3, #16
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80025d8: 4313 orrs r3, r2
80025da: 61bb str r3, [r7, #24]
if (hadc->Init.DiscontinuousConvMode == ENABLE)
80025dc: 687b ldr r3, [r7, #4]
80025de: f893 3020 ldrb.w r3, [r3, #32]
80025e2: 2b01 cmp r3, #1
80025e4: d106 bne.n 80025f4 <HAL_ADC_Init+0x168>
{
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
80025e6: 687b ldr r3, [r7, #4]
80025e8: 6a5b ldr r3, [r3, #36] @ 0x24
80025ea: 3b01 subs r3, #1
80025ec: 045b lsls r3, r3, #17
80025ee: 69ba ldr r2, [r7, #24]
80025f0: 4313 orrs r3, r2
80025f2: 61bb str r3, [r7, #24]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
80025f4: 687b ldr r3, [r7, #4]
80025f6: 6a9b ldr r3, [r3, #40] @ 0x28
80025f8: 2b00 cmp r3, #0
80025fa: d009 beq.n 8002610 <HAL_ADC_Init+0x184>
{
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
80025fc: 687b ldr r3, [r7, #4]
80025fe: 6a9b ldr r3, [r3, #40] @ 0x28
8002600: f403 7270 and.w r2, r3, #960 @ 0x3c0
| hadc->Init.ExternalTrigConvEdge
8002604: 687b ldr r3, [r7, #4]
8002606: 6adb ldr r3, [r3, #44] @ 0x2c
8002608: 4313 orrs r3, r2
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
800260a: 69ba ldr r2, [r7, #24]
800260c: 4313 orrs r3, r2
800260e: 61bb str r3, [r7, #24]
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
8002610: 687b ldr r3, [r7, #4]
8002612: 681b ldr r3, [r3, #0]
8002614: 68da ldr r2, [r3, #12]
8002616: 4b44 ldr r3, [pc, #272] @ (8002728 <HAL_ADC_Init+0x29c>)
8002618: 4013 ands r3, r2
800261a: 687a ldr r2, [r7, #4]
800261c: 6812 ldr r2, [r2, #0]
800261e: 69b9 ldr r1, [r7, #24]
8002620: 430b orrs r3, r1
8002622: 60d3 str r3, [r2, #12]
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular and injected groups: */
/* - DMA continuous request Init.DMAContinuousRequests */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8002624: 687b ldr r3, [r7, #4]
8002626: 681b ldr r3, [r3, #0]
8002628: 4618 mov r0, r3
800262a: f7ff ff1b bl 8002464 <LL_ADC_INJ_IsConversionOngoing>
800262e: 6138 str r0, [r7, #16]
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
8002630: 697b ldr r3, [r7, #20]
8002632: 2b00 cmp r3, #0
8002634: d13d bne.n 80026b2 <HAL_ADC_Init+0x226>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
8002636: 693b ldr r3, [r7, #16]
8002638: 2b00 cmp r3, #0
800263a: d13a bne.n 80026b2 <HAL_ADC_Init+0x226>
)
{
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
800263c: 687b ldr r3, [r7, #4]
800263e: 7e1b ldrb r3, [r3, #24]
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
8002640: 039a lsls r2, r3, #14
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
8002642: 687b ldr r3, [r7, #4]
8002644: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
8002648: 005b lsls r3, r3, #1
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
800264a: 4313 orrs r3, r2
800264c: 61bb str r3, [r7, #24]
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
800264e: 687b ldr r3, [r7, #4]
8002650: 681b ldr r3, [r3, #0]
8002652: 68db ldr r3, [r3, #12]
8002654: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8002658: f023 0302 bic.w r3, r3, #2
800265c: 687a ldr r2, [r7, #4]
800265e: 6812 ldr r2, [r2, #0]
8002660: 69b9 ldr r1, [r7, #24]
8002662: 430b orrs r3, r1
8002664: 60d3 str r3, [r2, #12]
if (hadc->Init.OversamplingMode == ENABLE)
8002666: 687b ldr r3, [r7, #4]
8002668: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
800266c: 2b01 cmp r3, #1
800266e: d118 bne.n 80026a2 <HAL_ADC_Init+0x216>
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2,
8002670: 687b ldr r3, [r7, #4]
8002672: 681b ldr r3, [r3, #0]
8002674: 691b ldr r3, [r3, #16]
8002676: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
800267a: f023 0304 bic.w r3, r3, #4
800267e: 687a ldr r2, [r7, #4]
8002680: 6bd1 ldr r1, [r2, #60] @ 0x3c
8002682: 687a ldr r2, [r7, #4]
8002684: 6c12 ldr r2, [r2, #64] @ 0x40
8002686: 4311 orrs r1, r2
8002688: 687a ldr r2, [r7, #4]
800268a: 6c52 ldr r2, [r2, #68] @ 0x44
800268c: 4311 orrs r1, r2
800268e: 687a ldr r2, [r7, #4]
8002690: 6c92 ldr r2, [r2, #72] @ 0x48
8002692: 430a orrs r2, r1
8002694: 431a orrs r2, r3
8002696: 687b ldr r3, [r7, #4]
8002698: 681b ldr r3, [r3, #0]
800269a: f042 0201 orr.w r2, r2, #1
800269e: 611a str r2, [r3, #16]
80026a0: e007 b.n 80026b2 <HAL_ADC_Init+0x226>
);
}
else
{
/* Disable ADC oversampling scope on ADC group regular */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
80026a2: 687b ldr r3, [r7, #4]
80026a4: 681b ldr r3, [r3, #0]
80026a6: 691a ldr r2, [r3, #16]
80026a8: 687b ldr r3, [r7, #4]
80026aa: 681b ldr r3, [r3, #0]
80026ac: f022 0201 bic.w r2, r2, #1
80026b0: 611a str r2, [r3, #16]
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
80026b2: 687b ldr r3, [r7, #4]
80026b4: 691b ldr r3, [r3, #16]
80026b6: 2b01 cmp r3, #1
80026b8: d10c bne.n 80026d4 <HAL_ADC_Init+0x248>
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
80026ba: 687b ldr r3, [r7, #4]
80026bc: 681b ldr r3, [r3, #0]
80026be: 6b1b ldr r3, [r3, #48] @ 0x30
80026c0: f023 010f bic.w r1, r3, #15
80026c4: 687b ldr r3, [r7, #4]
80026c6: 69db ldr r3, [r3, #28]
80026c8: 1e5a subs r2, r3, #1
80026ca: 687b ldr r3, [r7, #4]
80026cc: 681b ldr r3, [r3, #0]
80026ce: 430a orrs r2, r1
80026d0: 631a str r2, [r3, #48] @ 0x30
80026d2: e007 b.n 80026e4 <HAL_ADC_Init+0x258>
}
else
{
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
80026d4: 687b ldr r3, [r7, #4]
80026d6: 681b ldr r3, [r3, #0]
80026d8: 6b1a ldr r2, [r3, #48] @ 0x30
80026da: 687b ldr r3, [r7, #4]
80026dc: 681b ldr r3, [r3, #0]
80026de: f022 020f bic.w r2, r2, #15
80026e2: 631a str r2, [r3, #48] @ 0x30
}
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
80026e4: 687b ldr r3, [r7, #4]
80026e6: 6d5b ldr r3, [r3, #84] @ 0x54
80026e8: f023 0303 bic.w r3, r3, #3
80026ec: f043 0201 orr.w r2, r3, #1
80026f0: 687b ldr r3, [r7, #4]
80026f2: 655a str r2, [r3, #84] @ 0x54
80026f4: e007 b.n 8002706 <HAL_ADC_Init+0x27a>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80026f6: 687b ldr r3, [r7, #4]
80026f8: 6d5b ldr r3, [r3, #84] @ 0x54
80026fa: f043 0210 orr.w r2, r3, #16
80026fe: 687b ldr r3, [r7, #4]
8002700: 655a str r2, [r3, #84] @ 0x54
tmp_hal_status = HAL_ERROR;
8002702: 2301 movs r3, #1
8002704: 77fb strb r3, [r7, #31]
}
/* Return function status */
return tmp_hal_status;
8002706: 7ffb ldrb r3, [r7, #31]
}
8002708: 4618 mov r0, r3
800270a: 3724 adds r7, #36 @ 0x24
800270c: 46bd mov sp, r7
800270e: bd90 pop {r4, r7, pc}
8002710: 20000000 .word 0x20000000
8002714: 053e2d63 .word 0x053e2d63
8002718: 50040000 .word 0x50040000
800271c: 50040100 .word 0x50040100
8002720: 50040200 .word 0x50040200
8002724: 50040300 .word 0x50040300
8002728: fff0c007 .word 0xfff0c007
0800272c <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
{
800272c: b580 push {r7, lr}
800272e: b0b6 sub sp, #216 @ 0xd8
8002730: af00 add r7, sp, #0
8002732: 6078 str r0, [r7, #4]
8002734: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002736: 2300 movs r3, #0
8002738: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
800273c: 2300 movs r3, #0
800273e: 60bb str r3, [r7, #8]
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
}
/* Process locked */
__HAL_LOCK(hadc);
8002740: 687b ldr r3, [r7, #4]
8002742: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
8002746: 2b01 cmp r3, #1
8002748: d101 bne.n 800274e <HAL_ADC_ConfigChannel+0x22>
800274a: 2302 movs r3, #2
800274c: e3c9 b.n 8002ee2 <HAL_ADC_ConfigChannel+0x7b6>
800274e: 687b ldr r3, [r7, #4]
8002750: 2201 movs r2, #1
8002752: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002756: 687b ldr r3, [r7, #4]
8002758: 681b ldr r3, [r3, #0]
800275a: 4618 mov r0, r3
800275c: f7ff fe6f bl 800243e <LL_ADC_REG_IsConversionOngoing>
8002760: 4603 mov r3, r0
8002762: 2b00 cmp r3, #0
8002764: f040 83aa bne.w 8002ebc <HAL_ADC_ConfigChannel+0x790>
{
#if !defined (USE_FULL_ASSERT)
uint32_t config_rank = pConfig->Rank;
8002768: 683b ldr r3, [r7, #0]
800276a: 685b ldr r3, [r3, #4]
800276c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
/* Correspondence for compatibility with legacy definition of */
/* sequencer ranks in direct number format. This correspondence can */
/* be done only on ranks 1 to 5 due to literal values. */
/* Note: Sequencer ranks in direct number format are no more used */
/* and are detected by activating USE_FULL_ASSERT feature. */
if (pConfig->Rank <= 5U)
8002770: 683b ldr r3, [r7, #0]
8002772: 685b ldr r3, [r3, #4]
8002774: 2b05 cmp r3, #5
8002776: d824 bhi.n 80027c2 <HAL_ADC_ConfigChannel+0x96>
{
switch (pConfig->Rank)
8002778: 683b ldr r3, [r7, #0]
800277a: 685b ldr r3, [r3, #4]
800277c: 3b02 subs r3, #2
800277e: 2b03 cmp r3, #3
8002780: d81b bhi.n 80027ba <HAL_ADC_ConfigChannel+0x8e>
8002782: a201 add r2, pc, #4 @ (adr r2, 8002788 <HAL_ADC_ConfigChannel+0x5c>)
8002784: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002788: 08002799 .word 0x08002799
800278c: 080027a1 .word 0x080027a1
8002790: 080027a9 .word 0x080027a9
8002794: 080027b1 .word 0x080027b1
{
case 2U:
config_rank = ADC_REGULAR_RANK_2;
8002798: 230c movs r3, #12
800279a: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
break;
800279e: e010 b.n 80027c2 <HAL_ADC_ConfigChannel+0x96>
case 3U:
config_rank = ADC_REGULAR_RANK_3;
80027a0: 2312 movs r3, #18
80027a2: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
break;
80027a6: e00c b.n 80027c2 <HAL_ADC_ConfigChannel+0x96>
case 4U:
config_rank = ADC_REGULAR_RANK_4;
80027a8: 2318 movs r3, #24
80027aa: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
break;
80027ae: e008 b.n 80027c2 <HAL_ADC_ConfigChannel+0x96>
case 5U:
config_rank = ADC_REGULAR_RANK_5;
80027b0: f44f 7380 mov.w r3, #256 @ 0x100
80027b4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
break;
80027b8: e003 b.n 80027c2 <HAL_ADC_ConfigChannel+0x96>
/* case 1U */
default:
config_rank = ADC_REGULAR_RANK_1;
80027ba: 2306 movs r3, #6
80027bc: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
break;
80027c0: bf00 nop
}
}
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, config_rank, pConfig->Channel);
80027c2: 687b ldr r3, [r7, #4]
80027c4: 6818 ldr r0, [r3, #0]
80027c6: 683b ldr r3, [r7, #0]
80027c8: 681b ldr r3, [r3, #0]
80027ca: 461a mov r2, r3
80027cc: f8d7 10d0 ldr.w r1, [r7, #208] @ 0xd0
80027d0: f7ff fd59 bl 8002286 <LL_ADC_REG_SetSequencerRanks>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
80027d4: 687b ldr r3, [r7, #4]
80027d6: 681b ldr r3, [r3, #0]
80027d8: 4618 mov r0, r3
80027da: f7ff fe30 bl 800243e <LL_ADC_REG_IsConversionOngoing>
80027de: f8c7 00cc str.w r0, [r7, #204] @ 0xcc
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
80027e2: 687b ldr r3, [r7, #4]
80027e4: 681b ldr r3, [r3, #0]
80027e6: 4618 mov r0, r3
80027e8: f7ff fe3c bl 8002464 <LL_ADC_INJ_IsConversionOngoing>
80027ec: f8c7 00c8 str.w r0, [r7, #200] @ 0xc8
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
80027f0: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
80027f4: 2b00 cmp r3, #0
80027f6: f040 81a4 bne.w 8002b42 <HAL_ADC_ConfigChannel+0x416>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
80027fa: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
80027fe: 2b00 cmp r3, #0
8002800: f040 819f bne.w 8002b42 <HAL_ADC_ConfigChannel+0x416>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
}
#else
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
8002804: 687b ldr r3, [r7, #4]
8002806: 6818 ldr r0, [r3, #0]
8002808: 683b ldr r3, [r7, #0]
800280a: 6819 ldr r1, [r3, #0]
800280c: 683b ldr r3, [r7, #0]
800280e: 689b ldr r3, [r3, #8]
8002810: 461a mov r2, r3
8002812: f7ff fd64 bl 80022de <LL_ADC_SetChannelSamplingTime>
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
8002816: 683b ldr r3, [r7, #0]
8002818: 695a ldr r2, [r3, #20]
800281a: 687b ldr r3, [r7, #4]
800281c: 681b ldr r3, [r3, #0]
800281e: 68db ldr r3, [r3, #12]
8002820: 08db lsrs r3, r3, #3
8002822: f003 0303 and.w r3, r3, #3
8002826: 005b lsls r3, r3, #1
8002828: fa02 f303 lsl.w r3, r2, r3
800282c: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
8002830: 683b ldr r3, [r7, #0]
8002832: 691b ldr r3, [r3, #16]
8002834: 2b04 cmp r3, #4
8002836: d00a beq.n 800284e <HAL_ADC_ConfigChannel+0x122>
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
8002838: 687b ldr r3, [r7, #4]
800283a: 6818 ldr r0, [r3, #0]
800283c: 683b ldr r3, [r7, #0]
800283e: 6919 ldr r1, [r3, #16]
8002840: 683b ldr r3, [r7, #0]
8002842: 681a ldr r2, [r3, #0]
8002844: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002848: f7ff fcc8 bl 80021dc <LL_ADC_SetOffset>
800284c: e179 b.n 8002b42 <HAL_ADC_ConfigChannel+0x416>
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
800284e: 687b ldr r3, [r7, #4]
8002850: 681b ldr r3, [r3, #0]
8002852: 2100 movs r1, #0
8002854: 4618 mov r0, r3
8002856: f7ff fce5 bl 8002224 <LL_ADC_GetOffsetChannel>
800285a: 4603 mov r3, r0
800285c: f3c3 0312 ubfx r3, r3, #0, #19
8002860: 2b00 cmp r3, #0
8002862: d10a bne.n 800287a <HAL_ADC_ConfigChannel+0x14e>
8002864: 687b ldr r3, [r7, #4]
8002866: 681b ldr r3, [r3, #0]
8002868: 2100 movs r1, #0
800286a: 4618 mov r0, r3
800286c: f7ff fcda bl 8002224 <LL_ADC_GetOffsetChannel>
8002870: 4603 mov r3, r0
8002872: 0e9b lsrs r3, r3, #26
8002874: f003 021f and.w r2, r3, #31
8002878: e01e b.n 80028b8 <HAL_ADC_ConfigChannel+0x18c>
800287a: 687b ldr r3, [r7, #4]
800287c: 681b ldr r3, [r3, #0]
800287e: 2100 movs r1, #0
8002880: 4618 mov r0, r3
8002882: f7ff fccf bl 8002224 <LL_ADC_GetOffsetChannel>
8002886: 4603 mov r3, r0
8002888: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800288c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8002890: fa93 f3a3 rbit r3, r3
8002894: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8002898: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
800289c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
80028a0: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80028a4: 2b00 cmp r3, #0
80028a6: d101 bne.n 80028ac <HAL_ADC_ConfigChannel+0x180>
{
return 32U;
80028a8: 2320 movs r3, #32
80028aa: e004 b.n 80028b6 <HAL_ADC_ConfigChannel+0x18a>
}
return __builtin_clz(value);
80028ac: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80028b0: fab3 f383 clz r3, r3
80028b4: b2db uxtb r3, r3
80028b6: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
80028b8: 683b ldr r3, [r7, #0]
80028ba: 681b ldr r3, [r3, #0]
80028bc: f3c3 0312 ubfx r3, r3, #0, #19
80028c0: 2b00 cmp r3, #0
80028c2: d105 bne.n 80028d0 <HAL_ADC_ConfigChannel+0x1a4>
80028c4: 683b ldr r3, [r7, #0]
80028c6: 681b ldr r3, [r3, #0]
80028c8: 0e9b lsrs r3, r3, #26
80028ca: f003 031f and.w r3, r3, #31
80028ce: e018 b.n 8002902 <HAL_ADC_ConfigChannel+0x1d6>
80028d0: 683b ldr r3, [r7, #0]
80028d2: 681b ldr r3, [r3, #0]
80028d4: f8c7 30ac str.w r3, [r7, #172] @ 0xac
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80028d8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
80028dc: fa93 f3a3 rbit r3, r3
80028e0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
return result;
80028e4: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80028e8: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
if (value == 0U)
80028ec: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
80028f0: 2b00 cmp r3, #0
80028f2: d101 bne.n 80028f8 <HAL_ADC_ConfigChannel+0x1cc>
return 32U;
80028f4: 2320 movs r3, #32
80028f6: e004 b.n 8002902 <HAL_ADC_ConfigChannel+0x1d6>
return __builtin_clz(value);
80028f8: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
80028fc: fab3 f383 clz r3, r3
8002900: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
8002902: 429a cmp r2, r3
8002904: d106 bne.n 8002914 <HAL_ADC_ConfigChannel+0x1e8>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
8002906: 687b ldr r3, [r7, #4]
8002908: 681b ldr r3, [r3, #0]
800290a: 2200 movs r2, #0
800290c: 2100 movs r1, #0
800290e: 4618 mov r0, r3
8002910: f7ff fc9e bl 8002250 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
8002914: 687b ldr r3, [r7, #4]
8002916: 681b ldr r3, [r3, #0]
8002918: 2101 movs r1, #1
800291a: 4618 mov r0, r3
800291c: f7ff fc82 bl 8002224 <LL_ADC_GetOffsetChannel>
8002920: 4603 mov r3, r0
8002922: f3c3 0312 ubfx r3, r3, #0, #19
8002926: 2b00 cmp r3, #0
8002928: d10a bne.n 8002940 <HAL_ADC_ConfigChannel+0x214>
800292a: 687b ldr r3, [r7, #4]
800292c: 681b ldr r3, [r3, #0]
800292e: 2101 movs r1, #1
8002930: 4618 mov r0, r3
8002932: f7ff fc77 bl 8002224 <LL_ADC_GetOffsetChannel>
8002936: 4603 mov r3, r0
8002938: 0e9b lsrs r3, r3, #26
800293a: f003 021f and.w r2, r3, #31
800293e: e01e b.n 800297e <HAL_ADC_ConfigChannel+0x252>
8002940: 687b ldr r3, [r7, #4]
8002942: 681b ldr r3, [r3, #0]
8002944: 2101 movs r1, #1
8002946: 4618 mov r0, r3
8002948: f7ff fc6c bl 8002224 <LL_ADC_GetOffsetChannel>
800294c: 4603 mov r3, r0
800294e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002952: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8002956: fa93 f3a3 rbit r3, r3
800295a: f8c7 309c str.w r3, [r7, #156] @ 0x9c
return result;
800295e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8002962: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
if (value == 0U)
8002966: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
800296a: 2b00 cmp r3, #0
800296c: d101 bne.n 8002972 <HAL_ADC_ConfigChannel+0x246>
return 32U;
800296e: 2320 movs r3, #32
8002970: e004 b.n 800297c <HAL_ADC_ConfigChannel+0x250>
return __builtin_clz(value);
8002972: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8002976: fab3 f383 clz r3, r3
800297a: b2db uxtb r3, r3
800297c: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
800297e: 683b ldr r3, [r7, #0]
8002980: 681b ldr r3, [r3, #0]
8002982: f3c3 0312 ubfx r3, r3, #0, #19
8002986: 2b00 cmp r3, #0
8002988: d105 bne.n 8002996 <HAL_ADC_ConfigChannel+0x26a>
800298a: 683b ldr r3, [r7, #0]
800298c: 681b ldr r3, [r3, #0]
800298e: 0e9b lsrs r3, r3, #26
8002990: f003 031f and.w r3, r3, #31
8002994: e018 b.n 80029c8 <HAL_ADC_ConfigChannel+0x29c>
8002996: 683b ldr r3, [r7, #0]
8002998: 681b ldr r3, [r3, #0]
800299a: f8c7 3094 str.w r3, [r7, #148] @ 0x94
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800299e: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
80029a2: fa93 f3a3 rbit r3, r3
80029a6: f8c7 3090 str.w r3, [r7, #144] @ 0x90
return result;
80029aa: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
80029ae: f8c7 3098 str.w r3, [r7, #152] @ 0x98
if (value == 0U)
80029b2: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80029b6: 2b00 cmp r3, #0
80029b8: d101 bne.n 80029be <HAL_ADC_ConfigChannel+0x292>
return 32U;
80029ba: 2320 movs r3, #32
80029bc: e004 b.n 80029c8 <HAL_ADC_ConfigChannel+0x29c>
return __builtin_clz(value);
80029be: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80029c2: fab3 f383 clz r3, r3
80029c6: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
80029c8: 429a cmp r2, r3
80029ca: d106 bne.n 80029da <HAL_ADC_ConfigChannel+0x2ae>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
80029cc: 687b ldr r3, [r7, #4]
80029ce: 681b ldr r3, [r3, #0]
80029d0: 2200 movs r2, #0
80029d2: 2101 movs r1, #1
80029d4: 4618 mov r0, r3
80029d6: f7ff fc3b bl 8002250 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
80029da: 687b ldr r3, [r7, #4]
80029dc: 681b ldr r3, [r3, #0]
80029de: 2102 movs r1, #2
80029e0: 4618 mov r0, r3
80029e2: f7ff fc1f bl 8002224 <LL_ADC_GetOffsetChannel>
80029e6: 4603 mov r3, r0
80029e8: f3c3 0312 ubfx r3, r3, #0, #19
80029ec: 2b00 cmp r3, #0
80029ee: d10a bne.n 8002a06 <HAL_ADC_ConfigChannel+0x2da>
80029f0: 687b ldr r3, [r7, #4]
80029f2: 681b ldr r3, [r3, #0]
80029f4: 2102 movs r1, #2
80029f6: 4618 mov r0, r3
80029f8: f7ff fc14 bl 8002224 <LL_ADC_GetOffsetChannel>
80029fc: 4603 mov r3, r0
80029fe: 0e9b lsrs r3, r3, #26
8002a00: f003 021f and.w r2, r3, #31
8002a04: e01e b.n 8002a44 <HAL_ADC_ConfigChannel+0x318>
8002a06: 687b ldr r3, [r7, #4]
8002a08: 681b ldr r3, [r3, #0]
8002a0a: 2102 movs r1, #2
8002a0c: 4618 mov r0, r3
8002a0e: f7ff fc09 bl 8002224 <LL_ADC_GetOffsetChannel>
8002a12: 4603 mov r3, r0
8002a14: f8c7 3088 str.w r3, [r7, #136] @ 0x88
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a18: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8002a1c: fa93 f3a3 rbit r3, r3
8002a20: f8c7 3084 str.w r3, [r7, #132] @ 0x84
return result;
8002a24: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8002a28: f8c7 308c str.w r3, [r7, #140] @ 0x8c
if (value == 0U)
8002a2c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002a30: 2b00 cmp r3, #0
8002a32: d101 bne.n 8002a38 <HAL_ADC_ConfigChannel+0x30c>
return 32U;
8002a34: 2320 movs r3, #32
8002a36: e004 b.n 8002a42 <HAL_ADC_ConfigChannel+0x316>
return __builtin_clz(value);
8002a38: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002a3c: fab3 f383 clz r3, r3
8002a40: b2db uxtb r3, r3
8002a42: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002a44: 683b ldr r3, [r7, #0]
8002a46: 681b ldr r3, [r3, #0]
8002a48: f3c3 0312 ubfx r3, r3, #0, #19
8002a4c: 2b00 cmp r3, #0
8002a4e: d105 bne.n 8002a5c <HAL_ADC_ConfigChannel+0x330>
8002a50: 683b ldr r3, [r7, #0]
8002a52: 681b ldr r3, [r3, #0]
8002a54: 0e9b lsrs r3, r3, #26
8002a56: f003 031f and.w r3, r3, #31
8002a5a: e014 b.n 8002a86 <HAL_ADC_ConfigChannel+0x35a>
8002a5c: 683b ldr r3, [r7, #0]
8002a5e: 681b ldr r3, [r3, #0]
8002a60: 67fb str r3, [r7, #124] @ 0x7c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a62: 6ffb ldr r3, [r7, #124] @ 0x7c
8002a64: fa93 f3a3 rbit r3, r3
8002a68: 67bb str r3, [r7, #120] @ 0x78
return result;
8002a6a: 6fbb ldr r3, [r7, #120] @ 0x78
8002a6c: f8c7 3080 str.w r3, [r7, #128] @ 0x80
if (value == 0U)
8002a70: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002a74: 2b00 cmp r3, #0
8002a76: d101 bne.n 8002a7c <HAL_ADC_ConfigChannel+0x350>
return 32U;
8002a78: 2320 movs r3, #32
8002a7a: e004 b.n 8002a86 <HAL_ADC_ConfigChannel+0x35a>
return __builtin_clz(value);
8002a7c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002a80: fab3 f383 clz r3, r3
8002a84: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002a86: 429a cmp r2, r3
8002a88: d106 bne.n 8002a98 <HAL_ADC_ConfigChannel+0x36c>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
8002a8a: 687b ldr r3, [r7, #4]
8002a8c: 681b ldr r3, [r3, #0]
8002a8e: 2200 movs r2, #0
8002a90: 2102 movs r1, #2
8002a92: 4618 mov r0, r3
8002a94: f7ff fbdc bl 8002250 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002a98: 687b ldr r3, [r7, #4]
8002a9a: 681b ldr r3, [r3, #0]
8002a9c: 2103 movs r1, #3
8002a9e: 4618 mov r0, r3
8002aa0: f7ff fbc0 bl 8002224 <LL_ADC_GetOffsetChannel>
8002aa4: 4603 mov r3, r0
8002aa6: f3c3 0312 ubfx r3, r3, #0, #19
8002aaa: 2b00 cmp r3, #0
8002aac: d10a bne.n 8002ac4 <HAL_ADC_ConfigChannel+0x398>
8002aae: 687b ldr r3, [r7, #4]
8002ab0: 681b ldr r3, [r3, #0]
8002ab2: 2103 movs r1, #3
8002ab4: 4618 mov r0, r3
8002ab6: f7ff fbb5 bl 8002224 <LL_ADC_GetOffsetChannel>
8002aba: 4603 mov r3, r0
8002abc: 0e9b lsrs r3, r3, #26
8002abe: f003 021f and.w r2, r3, #31
8002ac2: e017 b.n 8002af4 <HAL_ADC_ConfigChannel+0x3c8>
8002ac4: 687b ldr r3, [r7, #4]
8002ac6: 681b ldr r3, [r3, #0]
8002ac8: 2103 movs r1, #3
8002aca: 4618 mov r0, r3
8002acc: f7ff fbaa bl 8002224 <LL_ADC_GetOffsetChannel>
8002ad0: 4603 mov r3, r0
8002ad2: 673b str r3, [r7, #112] @ 0x70
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ad4: 6f3b ldr r3, [r7, #112] @ 0x70
8002ad6: fa93 f3a3 rbit r3, r3
8002ada: 66fb str r3, [r7, #108] @ 0x6c
return result;
8002adc: 6efb ldr r3, [r7, #108] @ 0x6c
8002ade: 677b str r3, [r7, #116] @ 0x74
if (value == 0U)
8002ae0: 6f7b ldr r3, [r7, #116] @ 0x74
8002ae2: 2b00 cmp r3, #0
8002ae4: d101 bne.n 8002aea <HAL_ADC_ConfigChannel+0x3be>
return 32U;
8002ae6: 2320 movs r3, #32
8002ae8: e003 b.n 8002af2 <HAL_ADC_ConfigChannel+0x3c6>
return __builtin_clz(value);
8002aea: 6f7b ldr r3, [r7, #116] @ 0x74
8002aec: fab3 f383 clz r3, r3
8002af0: b2db uxtb r3, r3
8002af2: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002af4: 683b ldr r3, [r7, #0]
8002af6: 681b ldr r3, [r3, #0]
8002af8: f3c3 0312 ubfx r3, r3, #0, #19
8002afc: 2b00 cmp r3, #0
8002afe: d105 bne.n 8002b0c <HAL_ADC_ConfigChannel+0x3e0>
8002b00: 683b ldr r3, [r7, #0]
8002b02: 681b ldr r3, [r3, #0]
8002b04: 0e9b lsrs r3, r3, #26
8002b06: f003 031f and.w r3, r3, #31
8002b0a: e011 b.n 8002b30 <HAL_ADC_ConfigChannel+0x404>
8002b0c: 683b ldr r3, [r7, #0]
8002b0e: 681b ldr r3, [r3, #0]
8002b10: 667b str r3, [r7, #100] @ 0x64
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002b12: 6e7b ldr r3, [r7, #100] @ 0x64
8002b14: fa93 f3a3 rbit r3, r3
8002b18: 663b str r3, [r7, #96] @ 0x60
return result;
8002b1a: 6e3b ldr r3, [r7, #96] @ 0x60
8002b1c: 66bb str r3, [r7, #104] @ 0x68
if (value == 0U)
8002b1e: 6ebb ldr r3, [r7, #104] @ 0x68
8002b20: 2b00 cmp r3, #0
8002b22: d101 bne.n 8002b28 <HAL_ADC_ConfigChannel+0x3fc>
return 32U;
8002b24: 2320 movs r3, #32
8002b26: e003 b.n 8002b30 <HAL_ADC_ConfigChannel+0x404>
return __builtin_clz(value);
8002b28: 6ebb ldr r3, [r7, #104] @ 0x68
8002b2a: fab3 f383 clz r3, r3
8002b2e: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002b30: 429a cmp r2, r3
8002b32: d106 bne.n 8002b42 <HAL_ADC_ConfigChannel+0x416>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
8002b34: 687b ldr r3, [r7, #4]
8002b36: 681b ldr r3, [r3, #0]
8002b38: 2200 movs r2, #0
8002b3a: 2103 movs r1, #3
8002b3c: 4618 mov r0, r3
8002b3e: f7ff fb87 bl 8002250 <LL_ADC_SetOffsetState>
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002b42: 687b ldr r3, [r7, #4]
8002b44: 681b ldr r3, [r3, #0]
8002b46: 4618 mov r0, r3
8002b48: f7ff fc66 bl 8002418 <LL_ADC_IsEnabled>
8002b4c: 4603 mov r3, r0
8002b4e: 2b00 cmp r3, #0
8002b50: f040 8140 bne.w 8002dd4 <HAL_ADC_ConfigChannel+0x6a8>
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
8002b54: 687b ldr r3, [r7, #4]
8002b56: 6818 ldr r0, [r3, #0]
8002b58: 683b ldr r3, [r7, #0]
8002b5a: 6819 ldr r1, [r3, #0]
8002b5c: 683b ldr r3, [r7, #0]
8002b5e: 68db ldr r3, [r3, #12]
8002b60: 461a mov r2, r3
8002b62: f7ff fbe7 bl 8002334 <LL_ADC_SetChannelSingleDiff>
/* Configuration of differential mode */
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
8002b66: 683b ldr r3, [r7, #0]
8002b68: 68db ldr r3, [r3, #12]
8002b6a: 4a8f ldr r2, [pc, #572] @ (8002da8 <HAL_ADC_ConfigChannel+0x67c>)
8002b6c: 4293 cmp r3, r2
8002b6e: f040 8131 bne.w 8002dd4 <HAL_ADC_ConfigChannel+0x6a8>
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002b72: 687b ldr r3, [r7, #4]
8002b74: 6818 ldr r0, [r3, #0]
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002b76: 683b ldr r3, [r7, #0]
8002b78: 681b ldr r3, [r3, #0]
8002b7a: f3c3 0312 ubfx r3, r3, #0, #19
8002b7e: 2b00 cmp r3, #0
8002b80: d10b bne.n 8002b9a <HAL_ADC_ConfigChannel+0x46e>
8002b82: 683b ldr r3, [r7, #0]
8002b84: 681b ldr r3, [r3, #0]
8002b86: 0e9b lsrs r3, r3, #26
8002b88: 3301 adds r3, #1
8002b8a: f003 031f and.w r3, r3, #31
8002b8e: 2b09 cmp r3, #9
8002b90: bf94 ite ls
8002b92: 2301 movls r3, #1
8002b94: 2300 movhi r3, #0
8002b96: b2db uxtb r3, r3
8002b98: e019 b.n 8002bce <HAL_ADC_ConfigChannel+0x4a2>
8002b9a: 683b ldr r3, [r7, #0]
8002b9c: 681b ldr r3, [r3, #0]
8002b9e: 65bb str r3, [r7, #88] @ 0x58
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ba0: 6dbb ldr r3, [r7, #88] @ 0x58
8002ba2: fa93 f3a3 rbit r3, r3
8002ba6: 657b str r3, [r7, #84] @ 0x54
return result;
8002ba8: 6d7b ldr r3, [r7, #84] @ 0x54
8002baa: 65fb str r3, [r7, #92] @ 0x5c
if (value == 0U)
8002bac: 6dfb ldr r3, [r7, #92] @ 0x5c
8002bae: 2b00 cmp r3, #0
8002bb0: d101 bne.n 8002bb6 <HAL_ADC_ConfigChannel+0x48a>
return 32U;
8002bb2: 2320 movs r3, #32
8002bb4: e003 b.n 8002bbe <HAL_ADC_ConfigChannel+0x492>
return __builtin_clz(value);
8002bb6: 6dfb ldr r3, [r7, #92] @ 0x5c
8002bb8: fab3 f383 clz r3, r3
8002bbc: b2db uxtb r3, r3
8002bbe: 3301 adds r3, #1
8002bc0: f003 031f and.w r3, r3, #31
8002bc4: 2b09 cmp r3, #9
8002bc6: bf94 ite ls
8002bc8: 2301 movls r3, #1
8002bca: 2300 movhi r3, #0
8002bcc: b2db uxtb r3, r3
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002bce: 2b00 cmp r3, #0
8002bd0: d079 beq.n 8002cc6 <HAL_ADC_ConfigChannel+0x59a>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002bd2: 683b ldr r3, [r7, #0]
8002bd4: 681b ldr r3, [r3, #0]
8002bd6: f3c3 0312 ubfx r3, r3, #0, #19
8002bda: 2b00 cmp r3, #0
8002bdc: d107 bne.n 8002bee <HAL_ADC_ConfigChannel+0x4c2>
8002bde: 683b ldr r3, [r7, #0]
8002be0: 681b ldr r3, [r3, #0]
8002be2: 0e9b lsrs r3, r3, #26
8002be4: 3301 adds r3, #1
8002be6: 069b lsls r3, r3, #26
8002be8: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002bec: e015 b.n 8002c1a <HAL_ADC_ConfigChannel+0x4ee>
8002bee: 683b ldr r3, [r7, #0]
8002bf0: 681b ldr r3, [r3, #0]
8002bf2: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002bf4: 6cfb ldr r3, [r7, #76] @ 0x4c
8002bf6: fa93 f3a3 rbit r3, r3
8002bfa: 64bb str r3, [r7, #72] @ 0x48
return result;
8002bfc: 6cbb ldr r3, [r7, #72] @ 0x48
8002bfe: 653b str r3, [r7, #80] @ 0x50
if (value == 0U)
8002c00: 6d3b ldr r3, [r7, #80] @ 0x50
8002c02: 2b00 cmp r3, #0
8002c04: d101 bne.n 8002c0a <HAL_ADC_ConfigChannel+0x4de>
return 32U;
8002c06: 2320 movs r3, #32
8002c08: e003 b.n 8002c12 <HAL_ADC_ConfigChannel+0x4e6>
return __builtin_clz(value);
8002c0a: 6d3b ldr r3, [r7, #80] @ 0x50
8002c0c: fab3 f383 clz r3, r3
8002c10: b2db uxtb r3, r3
8002c12: 3301 adds r3, #1
8002c14: 069b lsls r3, r3, #26
8002c16: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002c1a: 683b ldr r3, [r7, #0]
8002c1c: 681b ldr r3, [r3, #0]
8002c1e: f3c3 0312 ubfx r3, r3, #0, #19
8002c22: 2b00 cmp r3, #0
8002c24: d109 bne.n 8002c3a <HAL_ADC_ConfigChannel+0x50e>
8002c26: 683b ldr r3, [r7, #0]
8002c28: 681b ldr r3, [r3, #0]
8002c2a: 0e9b lsrs r3, r3, #26
8002c2c: 3301 adds r3, #1
8002c2e: f003 031f and.w r3, r3, #31
8002c32: 2101 movs r1, #1
8002c34: fa01 f303 lsl.w r3, r1, r3
8002c38: e017 b.n 8002c6a <HAL_ADC_ConfigChannel+0x53e>
8002c3a: 683b ldr r3, [r7, #0]
8002c3c: 681b ldr r3, [r3, #0]
8002c3e: 643b str r3, [r7, #64] @ 0x40
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c40: 6c3b ldr r3, [r7, #64] @ 0x40
8002c42: fa93 f3a3 rbit r3, r3
8002c46: 63fb str r3, [r7, #60] @ 0x3c
return result;
8002c48: 6bfb ldr r3, [r7, #60] @ 0x3c
8002c4a: 647b str r3, [r7, #68] @ 0x44
if (value == 0U)
8002c4c: 6c7b ldr r3, [r7, #68] @ 0x44
8002c4e: 2b00 cmp r3, #0
8002c50: d101 bne.n 8002c56 <HAL_ADC_ConfigChannel+0x52a>
return 32U;
8002c52: 2320 movs r3, #32
8002c54: e003 b.n 8002c5e <HAL_ADC_ConfigChannel+0x532>
return __builtin_clz(value);
8002c56: 6c7b ldr r3, [r7, #68] @ 0x44
8002c58: fab3 f383 clz r3, r3
8002c5c: b2db uxtb r3, r3
8002c5e: 3301 adds r3, #1
8002c60: f003 031f and.w r3, r3, #31
8002c64: 2101 movs r1, #1
8002c66: fa01 f303 lsl.w r3, r1, r3
8002c6a: ea42 0103 orr.w r1, r2, r3
8002c6e: 683b ldr r3, [r7, #0]
8002c70: 681b ldr r3, [r3, #0]
8002c72: f3c3 0312 ubfx r3, r3, #0, #19
8002c76: 2b00 cmp r3, #0
8002c78: d10a bne.n 8002c90 <HAL_ADC_ConfigChannel+0x564>
8002c7a: 683b ldr r3, [r7, #0]
8002c7c: 681b ldr r3, [r3, #0]
8002c7e: 0e9b lsrs r3, r3, #26
8002c80: 3301 adds r3, #1
8002c82: f003 021f and.w r2, r3, #31
8002c86: 4613 mov r3, r2
8002c88: 005b lsls r3, r3, #1
8002c8a: 4413 add r3, r2
8002c8c: 051b lsls r3, r3, #20
8002c8e: e018 b.n 8002cc2 <HAL_ADC_ConfigChannel+0x596>
8002c90: 683b ldr r3, [r7, #0]
8002c92: 681b ldr r3, [r3, #0]
8002c94: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c96: 6b7b ldr r3, [r7, #52] @ 0x34
8002c98: fa93 f3a3 rbit r3, r3
8002c9c: 633b str r3, [r7, #48] @ 0x30
return result;
8002c9e: 6b3b ldr r3, [r7, #48] @ 0x30
8002ca0: 63bb str r3, [r7, #56] @ 0x38
if (value == 0U)
8002ca2: 6bbb ldr r3, [r7, #56] @ 0x38
8002ca4: 2b00 cmp r3, #0
8002ca6: d101 bne.n 8002cac <HAL_ADC_ConfigChannel+0x580>
return 32U;
8002ca8: 2320 movs r3, #32
8002caa: e003 b.n 8002cb4 <HAL_ADC_ConfigChannel+0x588>
return __builtin_clz(value);
8002cac: 6bbb ldr r3, [r7, #56] @ 0x38
8002cae: fab3 f383 clz r3, r3
8002cb2: b2db uxtb r3, r3
8002cb4: 3301 adds r3, #1
8002cb6: f003 021f and.w r2, r3, #31
8002cba: 4613 mov r3, r2
8002cbc: 005b lsls r3, r3, #1
8002cbe: 4413 add r3, r2
8002cc0: 051b lsls r3, r3, #20
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002cc2: 430b orrs r3, r1
8002cc4: e081 b.n 8002dca <HAL_ADC_ConfigChannel+0x69e>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002cc6: 683b ldr r3, [r7, #0]
8002cc8: 681b ldr r3, [r3, #0]
8002cca: f3c3 0312 ubfx r3, r3, #0, #19
8002cce: 2b00 cmp r3, #0
8002cd0: d107 bne.n 8002ce2 <HAL_ADC_ConfigChannel+0x5b6>
8002cd2: 683b ldr r3, [r7, #0]
8002cd4: 681b ldr r3, [r3, #0]
8002cd6: 0e9b lsrs r3, r3, #26
8002cd8: 3301 adds r3, #1
8002cda: 069b lsls r3, r3, #26
8002cdc: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002ce0: e015 b.n 8002d0e <HAL_ADC_ConfigChannel+0x5e2>
8002ce2: 683b ldr r3, [r7, #0]
8002ce4: 681b ldr r3, [r3, #0]
8002ce6: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ce8: 6abb ldr r3, [r7, #40] @ 0x28
8002cea: fa93 f3a3 rbit r3, r3
8002cee: 627b str r3, [r7, #36] @ 0x24
return result;
8002cf0: 6a7b ldr r3, [r7, #36] @ 0x24
8002cf2: 62fb str r3, [r7, #44] @ 0x2c
if (value == 0U)
8002cf4: 6afb ldr r3, [r7, #44] @ 0x2c
8002cf6: 2b00 cmp r3, #0
8002cf8: d101 bne.n 8002cfe <HAL_ADC_ConfigChannel+0x5d2>
return 32U;
8002cfa: 2320 movs r3, #32
8002cfc: e003 b.n 8002d06 <HAL_ADC_ConfigChannel+0x5da>
return __builtin_clz(value);
8002cfe: 6afb ldr r3, [r7, #44] @ 0x2c
8002d00: fab3 f383 clz r3, r3
8002d04: b2db uxtb r3, r3
8002d06: 3301 adds r3, #1
8002d08: 069b lsls r3, r3, #26
8002d0a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002d0e: 683b ldr r3, [r7, #0]
8002d10: 681b ldr r3, [r3, #0]
8002d12: f3c3 0312 ubfx r3, r3, #0, #19
8002d16: 2b00 cmp r3, #0
8002d18: d109 bne.n 8002d2e <HAL_ADC_ConfigChannel+0x602>
8002d1a: 683b ldr r3, [r7, #0]
8002d1c: 681b ldr r3, [r3, #0]
8002d1e: 0e9b lsrs r3, r3, #26
8002d20: 3301 adds r3, #1
8002d22: f003 031f and.w r3, r3, #31
8002d26: 2101 movs r1, #1
8002d28: fa01 f303 lsl.w r3, r1, r3
8002d2c: e017 b.n 8002d5e <HAL_ADC_ConfigChannel+0x632>
8002d2e: 683b ldr r3, [r7, #0]
8002d30: 681b ldr r3, [r3, #0]
8002d32: 61fb str r3, [r7, #28]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d34: 69fb ldr r3, [r7, #28]
8002d36: fa93 f3a3 rbit r3, r3
8002d3a: 61bb str r3, [r7, #24]
return result;
8002d3c: 69bb ldr r3, [r7, #24]
8002d3e: 623b str r3, [r7, #32]
if (value == 0U)
8002d40: 6a3b ldr r3, [r7, #32]
8002d42: 2b00 cmp r3, #0
8002d44: d101 bne.n 8002d4a <HAL_ADC_ConfigChannel+0x61e>
return 32U;
8002d46: 2320 movs r3, #32
8002d48: e003 b.n 8002d52 <HAL_ADC_ConfigChannel+0x626>
return __builtin_clz(value);
8002d4a: 6a3b ldr r3, [r7, #32]
8002d4c: fab3 f383 clz r3, r3
8002d50: b2db uxtb r3, r3
8002d52: 3301 adds r3, #1
8002d54: f003 031f and.w r3, r3, #31
8002d58: 2101 movs r1, #1
8002d5a: fa01 f303 lsl.w r3, r1, r3
8002d5e: ea42 0103 orr.w r1, r2, r3
8002d62: 683b ldr r3, [r7, #0]
8002d64: 681b ldr r3, [r3, #0]
8002d66: f3c3 0312 ubfx r3, r3, #0, #19
8002d6a: 2b00 cmp r3, #0
8002d6c: d10d bne.n 8002d8a <HAL_ADC_ConfigChannel+0x65e>
8002d6e: 683b ldr r3, [r7, #0]
8002d70: 681b ldr r3, [r3, #0]
8002d72: 0e9b lsrs r3, r3, #26
8002d74: 3301 adds r3, #1
8002d76: f003 021f and.w r2, r3, #31
8002d7a: 4613 mov r3, r2
8002d7c: 005b lsls r3, r3, #1
8002d7e: 4413 add r3, r2
8002d80: 3b1e subs r3, #30
8002d82: 051b lsls r3, r3, #20
8002d84: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8002d88: e01e b.n 8002dc8 <HAL_ADC_ConfigChannel+0x69c>
8002d8a: 683b ldr r3, [r7, #0]
8002d8c: 681b ldr r3, [r3, #0]
8002d8e: 613b str r3, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d90: 693b ldr r3, [r7, #16]
8002d92: fa93 f3a3 rbit r3, r3
8002d96: 60fb str r3, [r7, #12]
return result;
8002d98: 68fb ldr r3, [r7, #12]
8002d9a: 617b str r3, [r7, #20]
if (value == 0U)
8002d9c: 697b ldr r3, [r7, #20]
8002d9e: 2b00 cmp r3, #0
8002da0: d104 bne.n 8002dac <HAL_ADC_ConfigChannel+0x680>
return 32U;
8002da2: 2320 movs r3, #32
8002da4: e006 b.n 8002db4 <HAL_ADC_ConfigChannel+0x688>
8002da6: bf00 nop
8002da8: 407f0000 .word 0x407f0000
return __builtin_clz(value);
8002dac: 697b ldr r3, [r7, #20]
8002dae: fab3 f383 clz r3, r3
8002db2: b2db uxtb r3, r3
8002db4: 3301 adds r3, #1
8002db6: f003 021f and.w r2, r3, #31
8002dba: 4613 mov r3, r2
8002dbc: 005b lsls r3, r3, #1
8002dbe: 4413 add r3, r2
8002dc0: 3b1e subs r3, #30
8002dc2: 051b lsls r3, r3, #20
8002dc4: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002dc8: 430b orrs r3, r1
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
+ 1UL) & 0x1FUL)),
pConfig->SamplingTime);
8002dca: 683a ldr r2, [r7, #0]
8002dcc: 6892 ldr r2, [r2, #8]
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002dce: 4619 mov r1, r3
8002dd0: f7ff fa85 bl 80022de <LL_ADC_SetChannelSamplingTime>
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
8002dd4: 683b ldr r3, [r7, #0]
8002dd6: 681a ldr r2, [r3, #0]
8002dd8: 4b44 ldr r3, [pc, #272] @ (8002eec <HAL_ADC_ConfigChannel+0x7c0>)
8002dda: 4013 ands r3, r2
8002ddc: 2b00 cmp r3, #0
8002dde: d07a beq.n 8002ed6 <HAL_ADC_ConfigChannel+0x7aa>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8002de0: 4843 ldr r0, [pc, #268] @ (8002ef0 <HAL_ADC_ConfigChannel+0x7c4>)
8002de2: f7ff f9ed bl 80021c0 <LL_ADC_GetCommonPathInternalCh>
8002de6: f8c7 00c0 str.w r0, [r7, #192] @ 0xc0
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8002dea: 683b ldr r3, [r7, #0]
8002dec: 681b ldr r3, [r3, #0]
8002dee: 4a41 ldr r2, [pc, #260] @ (8002ef4 <HAL_ADC_ConfigChannel+0x7c8>)
8002df0: 4293 cmp r3, r2
8002df2: d12c bne.n 8002e4e <HAL_ADC_ConfigChannel+0x722>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8002df4: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002df8: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002dfc: 2b00 cmp r3, #0
8002dfe: d126 bne.n 8002e4e <HAL_ADC_ConfigChannel+0x722>
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8002e00: 687b ldr r3, [r7, #4]
8002e02: 681b ldr r3, [r3, #0]
8002e04: 4a3c ldr r2, [pc, #240] @ (8002ef8 <HAL_ADC_ConfigChannel+0x7cc>)
8002e06: 4293 cmp r3, r2
8002e08: d004 beq.n 8002e14 <HAL_ADC_ConfigChannel+0x6e8>
8002e0a: 687b ldr r3, [r7, #4]
8002e0c: 681b ldr r3, [r3, #0]
8002e0e: 4a3b ldr r2, [pc, #236] @ (8002efc <HAL_ADC_ConfigChannel+0x7d0>)
8002e10: 4293 cmp r3, r2
8002e12: d15d bne.n 8002ed0 <HAL_ADC_ConfigChannel+0x7a4>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002e14: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002e18: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8002e1c: 4619 mov r1, r3
8002e1e: 4834 ldr r0, [pc, #208] @ (8002ef0 <HAL_ADC_ConfigChannel+0x7c4>)
8002e20: f7ff f9bb bl 800219a <LL_ADC_SetCommonPathInternalCh>
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002e24: 4b36 ldr r3, [pc, #216] @ (8002f00 <HAL_ADC_ConfigChannel+0x7d4>)
8002e26: 681b ldr r3, [r3, #0]
8002e28: 099b lsrs r3, r3, #6
8002e2a: 4a36 ldr r2, [pc, #216] @ (8002f04 <HAL_ADC_ConfigChannel+0x7d8>)
8002e2c: fba2 2303 umull r2, r3, r2, r3
8002e30: 099b lsrs r3, r3, #6
8002e32: 1c5a adds r2, r3, #1
8002e34: 4613 mov r3, r2
8002e36: 005b lsls r3, r3, #1
8002e38: 4413 add r3, r2
8002e3a: 009b lsls r3, r3, #2
8002e3c: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002e3e: e002 b.n 8002e46 <HAL_ADC_ConfigChannel+0x71a>
{
wait_loop_index--;
8002e40: 68bb ldr r3, [r7, #8]
8002e42: 3b01 subs r3, #1
8002e44: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002e46: 68bb ldr r3, [r7, #8]
8002e48: 2b00 cmp r3, #0
8002e4a: d1f9 bne.n 8002e40 <HAL_ADC_ConfigChannel+0x714>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8002e4c: e040 b.n 8002ed0 <HAL_ADC_ConfigChannel+0x7a4>
}
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
8002e4e: 683b ldr r3, [r7, #0]
8002e50: 681b ldr r3, [r3, #0]
8002e52: 4a2d ldr r2, [pc, #180] @ (8002f08 <HAL_ADC_ConfigChannel+0x7dc>)
8002e54: 4293 cmp r3, r2
8002e56: d118 bne.n 8002e8a <HAL_ADC_ConfigChannel+0x75e>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
8002e58: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002e5c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8002e60: 2b00 cmp r3, #0
8002e62: d112 bne.n 8002e8a <HAL_ADC_ConfigChannel+0x75e>
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8002e64: 687b ldr r3, [r7, #4]
8002e66: 681b ldr r3, [r3, #0]
8002e68: 4a23 ldr r2, [pc, #140] @ (8002ef8 <HAL_ADC_ConfigChannel+0x7cc>)
8002e6a: 4293 cmp r3, r2
8002e6c: d004 beq.n 8002e78 <HAL_ADC_ConfigChannel+0x74c>
8002e6e: 687b ldr r3, [r7, #4]
8002e70: 681b ldr r3, [r3, #0]
8002e72: 4a22 ldr r2, [pc, #136] @ (8002efc <HAL_ADC_ConfigChannel+0x7d0>)
8002e74: 4293 cmp r3, r2
8002e76: d12d bne.n 8002ed4 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002e78: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002e7c: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002e80: 4619 mov r1, r3
8002e82: 481b ldr r0, [pc, #108] @ (8002ef0 <HAL_ADC_ConfigChannel+0x7c4>)
8002e84: f7ff f989 bl 800219a <LL_ADC_SetCommonPathInternalCh>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8002e88: e024 b.n 8002ed4 <HAL_ADC_ConfigChannel+0x7a8>
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
8002e8a: 683b ldr r3, [r7, #0]
8002e8c: 681b ldr r3, [r3, #0]
8002e8e: 4a1f ldr r2, [pc, #124] @ (8002f0c <HAL_ADC_ConfigChannel+0x7e0>)
8002e90: 4293 cmp r3, r2
8002e92: d120 bne.n 8002ed6 <HAL_ADC_ConfigChannel+0x7aa>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
8002e94: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002e98: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8002e9c: 2b00 cmp r3, #0
8002e9e: d11a bne.n 8002ed6 <HAL_ADC_ConfigChannel+0x7aa>
{
if (ADC_VREFINT_INSTANCE(hadc))
8002ea0: 687b ldr r3, [r7, #4]
8002ea2: 681b ldr r3, [r3, #0]
8002ea4: 4a14 ldr r2, [pc, #80] @ (8002ef8 <HAL_ADC_ConfigChannel+0x7cc>)
8002ea6: 4293 cmp r3, r2
8002ea8: d115 bne.n 8002ed6 <HAL_ADC_ConfigChannel+0x7aa>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002eaa: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002eae: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8002eb2: 4619 mov r1, r3
8002eb4: 480e ldr r0, [pc, #56] @ (8002ef0 <HAL_ADC_ConfigChannel+0x7c4>)
8002eb6: f7ff f970 bl 800219a <LL_ADC_SetCommonPathInternalCh>
8002eba: e00c b.n 8002ed6 <HAL_ADC_ConfigChannel+0x7aa>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002ebc: 687b ldr r3, [r7, #4]
8002ebe: 6d5b ldr r3, [r3, #84] @ 0x54
8002ec0: f043 0220 orr.w r2, r3, #32
8002ec4: 687b ldr r3, [r7, #4]
8002ec6: 655a str r2, [r3, #84] @ 0x54
tmp_hal_status = HAL_ERROR;
8002ec8: 2301 movs r3, #1
8002eca: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
8002ece: e002 b.n 8002ed6 <HAL_ADC_ConfigChannel+0x7aa>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8002ed0: bf00 nop
8002ed2: e000 b.n 8002ed6 <HAL_ADC_ConfigChannel+0x7aa>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8002ed4: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002ed6: 687b ldr r3, [r7, #4]
8002ed8: 2200 movs r2, #0
8002eda: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Return function status */
return tmp_hal_status;
8002ede: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7
}
8002ee2: 4618 mov r0, r3
8002ee4: 37d8 adds r7, #216 @ 0xd8
8002ee6: 46bd mov sp, r7
8002ee8: bd80 pop {r7, pc}
8002eea: bf00 nop
8002eec: 80080000 .word 0x80080000
8002ef0: 50040300 .word 0x50040300
8002ef4: c7520000 .word 0xc7520000
8002ef8: 50040000 .word 0x50040000
8002efc: 50040200 .word 0x50040200
8002f00: 20000000 .word 0x20000000
8002f04: 053e2d63 .word 0x053e2d63
8002f08: cb840000 .word 0xcb840000
8002f0c: 80000001 .word 0x80000001
08002f10 <LL_ADC_IsEnabled>:
{
8002f10: b480 push {r7}
8002f12: b083 sub sp, #12
8002f14: af00 add r7, sp, #0
8002f16: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8002f18: 687b ldr r3, [r7, #4]
8002f1a: 689b ldr r3, [r3, #8]
8002f1c: f003 0301 and.w r3, r3, #1
8002f20: 2b01 cmp r3, #1
8002f22: d101 bne.n 8002f28 <LL_ADC_IsEnabled+0x18>
8002f24: 2301 movs r3, #1
8002f26: e000 b.n 8002f2a <LL_ADC_IsEnabled+0x1a>
8002f28: 2300 movs r3, #0
}
8002f2a: 4618 mov r0, r3
8002f2c: 370c adds r7, #12
8002f2e: 46bd mov sp, r7
8002f30: f85d 7b04 ldr.w r7, [sp], #4
8002f34: 4770 bx lr
08002f36 <LL_ADC_REG_IsConversionOngoing>:
{
8002f36: b480 push {r7}
8002f38: b083 sub sp, #12
8002f3a: af00 add r7, sp, #0
8002f3c: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8002f3e: 687b ldr r3, [r7, #4]
8002f40: 689b ldr r3, [r3, #8]
8002f42: f003 0304 and.w r3, r3, #4
8002f46: 2b04 cmp r3, #4
8002f48: d101 bne.n 8002f4e <LL_ADC_REG_IsConversionOngoing+0x18>
8002f4a: 2301 movs r3, #1
8002f4c: e000 b.n 8002f50 <LL_ADC_REG_IsConversionOngoing+0x1a>
8002f4e: 2300 movs r3, #0
}
8002f50: 4618 mov r0, r3
8002f52: 370c adds r7, #12
8002f54: 46bd mov sp, r7
8002f56: f85d 7b04 ldr.w r7, [sp], #4
8002f5a: 4770 bx lr
08002f5c <HAL_ADCEx_MultiModeConfigChannel>:
* @param hadc Master ADC handle
* @param pMultimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
{
8002f5c: b590 push {r4, r7, lr}
8002f5e: b09f sub sp, #124 @ 0x7c
8002f60: af00 add r7, sp, #0
8002f62: 6078 str r0, [r7, #4]
8002f64: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002f66: 2300 movs r3, #0
8002f68: f887 3077 strb.w r3, [r7, #119] @ 0x77
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
8002f6c: 687b ldr r3, [r7, #4]
8002f6e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
8002f72: 2b01 cmp r3, #1
8002f74: d101 bne.n 8002f7a <HAL_ADCEx_MultiModeConfigChannel+0x1e>
8002f76: 2302 movs r3, #2
8002f78: e093 b.n 80030a2 <HAL_ADCEx_MultiModeConfigChannel+0x146>
8002f7a: 687b ldr r3, [r7, #4]
8002f7c: 2201 movs r2, #1
8002f7e: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
8002f82: 2300 movs r3, #0
8002f84: 65fb str r3, [r7, #92] @ 0x5c
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
8002f86: 2300 movs r3, #0
8002f88: 663b str r3, [r7, #96] @ 0x60
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
8002f8a: 687b ldr r3, [r7, #4]
8002f8c: 681b ldr r3, [r3, #0]
8002f8e: 4a47 ldr r2, [pc, #284] @ (80030ac <HAL_ADCEx_MultiModeConfigChannel+0x150>)
8002f90: 4293 cmp r3, r2
8002f92: d102 bne.n 8002f9a <HAL_ADCEx_MultiModeConfigChannel+0x3e>
8002f94: 4b46 ldr r3, [pc, #280] @ (80030b0 <HAL_ADCEx_MultiModeConfigChannel+0x154>)
8002f96: 60bb str r3, [r7, #8]
8002f98: e001 b.n 8002f9e <HAL_ADCEx_MultiModeConfigChannel+0x42>
8002f9a: 2300 movs r3, #0
8002f9c: 60bb str r3, [r7, #8]
if (tmp_hadc_slave.Instance == NULL)
8002f9e: 68bb ldr r3, [r7, #8]
8002fa0: 2b00 cmp r3, #0
8002fa2: d10b bne.n 8002fbc <HAL_ADCEx_MultiModeConfigChannel+0x60>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002fa4: 687b ldr r3, [r7, #4]
8002fa6: 6d5b ldr r3, [r3, #84] @ 0x54
8002fa8: f043 0220 orr.w r2, r3, #32
8002fac: 687b ldr r3, [r7, #4]
8002fae: 655a str r2, [r3, #84] @ 0x54
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002fb0: 687b ldr r3, [r7, #4]
8002fb2: 2200 movs r2, #0
8002fb4: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_ERROR;
8002fb8: 2301 movs r3, #1
8002fba: e072 b.n 80030a2 <HAL_ADCEx_MultiModeConfigChannel+0x146>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
8002fbc: 68bb ldr r3, [r7, #8]
8002fbe: 4618 mov r0, r3
8002fc0: f7ff ffb9 bl 8002f36 <LL_ADC_REG_IsConversionOngoing>
8002fc4: 6738 str r0, [r7, #112] @ 0x70
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002fc6: 687b ldr r3, [r7, #4]
8002fc8: 681b ldr r3, [r3, #0]
8002fca: 4618 mov r0, r3
8002fcc: f7ff ffb3 bl 8002f36 <LL_ADC_REG_IsConversionOngoing>
8002fd0: 4603 mov r3, r0
8002fd2: 2b00 cmp r3, #0
8002fd4: d154 bne.n 8003080 <HAL_ADCEx_MultiModeConfigChannel+0x124>
&& (tmp_hadc_slave_conversion_on_going == 0UL))
8002fd6: 6f3b ldr r3, [r7, #112] @ 0x70
8002fd8: 2b00 cmp r3, #0
8002fda: d151 bne.n 8003080 <HAL_ADCEx_MultiModeConfigChannel+0x124>
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
8002fdc: 4b35 ldr r3, [pc, #212] @ (80030b4 <HAL_ADCEx_MultiModeConfigChannel+0x158>)
8002fde: 66fb str r3, [r7, #108] @ 0x6c
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8002fe0: 683b ldr r3, [r7, #0]
8002fe2: 681b ldr r3, [r3, #0]
8002fe4: 2b00 cmp r3, #0
8002fe6: d02c beq.n 8003042 <HAL_ADCEx_MultiModeConfigChannel+0xe6>
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
8002fe8: 6efb ldr r3, [r7, #108] @ 0x6c
8002fea: 689b ldr r3, [r3, #8]
8002fec: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8002ff0: 683b ldr r3, [r7, #0]
8002ff2: 6859 ldr r1, [r3, #4]
8002ff4: 687b ldr r3, [r7, #4]
8002ff6: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
8002ffa: 035b lsls r3, r3, #13
8002ffc: 430b orrs r3, r1
8002ffe: 431a orrs r2, r3
8003000: 6efb ldr r3, [r7, #108] @ 0x6c
8003002: 609a str r2, [r3, #8]
/* from 1 to 10 clock cycles for 10 bits, */
/* from 1 to 8 clock cycles for 8 bits */
/* from 1 to 6 clock cycles for 6 bits */
/* If a higher delay is selected, it will be clipped to maximum delay */
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8003004: 4829 ldr r0, [pc, #164] @ (80030ac <HAL_ADCEx_MultiModeConfigChannel+0x150>)
8003006: f7ff ff83 bl 8002f10 <LL_ADC_IsEnabled>
800300a: 4604 mov r4, r0
800300c: 4828 ldr r0, [pc, #160] @ (80030b0 <HAL_ADCEx_MultiModeConfigChannel+0x154>)
800300e: f7ff ff7f bl 8002f10 <LL_ADC_IsEnabled>
8003012: 4603 mov r3, r0
8003014: 431c orrs r4, r3
8003016: 4828 ldr r0, [pc, #160] @ (80030b8 <HAL_ADCEx_MultiModeConfigChannel+0x15c>)
8003018: f7ff ff7a bl 8002f10 <LL_ADC_IsEnabled>
800301c: 4603 mov r3, r0
800301e: 4323 orrs r3, r4
8003020: 2b00 cmp r3, #0
8003022: d137 bne.n 8003094 <HAL_ADCEx_MultiModeConfigChannel+0x138>
{
MODIFY_REG(tmpADC_Common->CCR,
8003024: 6efb ldr r3, [r7, #108] @ 0x6c
8003026: 689b ldr r3, [r3, #8]
8003028: f423 6371 bic.w r3, r3, #3856 @ 0xf10
800302c: f023 030f bic.w r3, r3, #15
8003030: 683a ldr r2, [r7, #0]
8003032: 6811 ldr r1, [r2, #0]
8003034: 683a ldr r2, [r7, #0]
8003036: 6892 ldr r2, [r2, #8]
8003038: 430a orrs r2, r1
800303a: 431a orrs r2, r3
800303c: 6efb ldr r3, [r7, #108] @ 0x6c
800303e: 609a str r2, [r3, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003040: e028 b.n 8003094 <HAL_ADCEx_MultiModeConfigChannel+0x138>
);
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
8003042: 6efb ldr r3, [r7, #108] @ 0x6c
8003044: 689b ldr r3, [r3, #8]
8003046: f423 4260 bic.w r2, r3, #57344 @ 0xe000
800304a: 6efb ldr r3, [r7, #108] @ 0x6c
800304c: 609a str r2, [r3, #8]
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
800304e: 4817 ldr r0, [pc, #92] @ (80030ac <HAL_ADCEx_MultiModeConfigChannel+0x150>)
8003050: f7ff ff5e bl 8002f10 <LL_ADC_IsEnabled>
8003054: 4604 mov r4, r0
8003056: 4816 ldr r0, [pc, #88] @ (80030b0 <HAL_ADCEx_MultiModeConfigChannel+0x154>)
8003058: f7ff ff5a bl 8002f10 <LL_ADC_IsEnabled>
800305c: 4603 mov r3, r0
800305e: 431c orrs r4, r3
8003060: 4815 ldr r0, [pc, #84] @ (80030b8 <HAL_ADCEx_MultiModeConfigChannel+0x15c>)
8003062: f7ff ff55 bl 8002f10 <LL_ADC_IsEnabled>
8003066: 4603 mov r3, r0
8003068: 4323 orrs r3, r4
800306a: 2b00 cmp r3, #0
800306c: d112 bne.n 8003094 <HAL_ADCEx_MultiModeConfigChannel+0x138>
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
800306e: 6efb ldr r3, [r7, #108] @ 0x6c
8003070: 689b ldr r3, [r3, #8]
8003072: f423 6371 bic.w r3, r3, #3856 @ 0xf10
8003076: f023 030f bic.w r3, r3, #15
800307a: 6efa ldr r2, [r7, #108] @ 0x6c
800307c: 6093 str r3, [r2, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
800307e: e009 b.n 8003094 <HAL_ADCEx_MultiModeConfigChannel+0x138>
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003080: 687b ldr r3, [r7, #4]
8003082: 6d5b ldr r3, [r3, #84] @ 0x54
8003084: f043 0220 orr.w r2, r3, #32
8003088: 687b ldr r3, [r7, #4]
800308a: 655a str r2, [r3, #84] @ 0x54
tmp_hal_status = HAL_ERROR;
800308c: 2301 movs r3, #1
800308e: f887 3077 strb.w r3, [r7, #119] @ 0x77
8003092: e000 b.n 8003096 <HAL_ADCEx_MultiModeConfigChannel+0x13a>
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003094: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003096: 687b ldr r3, [r7, #4]
8003098: 2200 movs r2, #0
800309a: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Return function status */
return tmp_hal_status;
800309e: f897 3077 ldrb.w r3, [r7, #119] @ 0x77
}
80030a2: 4618 mov r0, r3
80030a4: 377c adds r7, #124 @ 0x7c
80030a6: 46bd mov sp, r7
80030a8: bd90 pop {r4, r7, pc}
80030aa: bf00 nop
80030ac: 50040000 .word 0x50040000
80030b0: 50040100 .word 0x50040100
80030b4: 50040300 .word 0x50040300
80030b8: 50040200 .word 0x50040200
080030bc <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80030bc: b480 push {r7}
80030be: b085 sub sp, #20
80030c0: af00 add r7, sp, #0
80030c2: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80030c4: 687b ldr r3, [r7, #4]
80030c6: f003 0307 and.w r3, r3, #7
80030ca: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80030cc: 4b0c ldr r3, [pc, #48] @ (8003100 <__NVIC_SetPriorityGrouping+0x44>)
80030ce: 68db ldr r3, [r3, #12]
80030d0: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80030d2: 68ba ldr r2, [r7, #8]
80030d4: f64f 03ff movw r3, #63743 @ 0xf8ff
80030d8: 4013 ands r3, r2
80030da: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80030dc: 68fb ldr r3, [r7, #12]
80030de: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80030e0: 68bb ldr r3, [r7, #8]
80030e2: 4313 orrs r3, r2
reg_value = (reg_value |
80030e4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
80030e8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80030ec: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80030ee: 4a04 ldr r2, [pc, #16] @ (8003100 <__NVIC_SetPriorityGrouping+0x44>)
80030f0: 68bb ldr r3, [r7, #8]
80030f2: 60d3 str r3, [r2, #12]
}
80030f4: bf00 nop
80030f6: 3714 adds r7, #20
80030f8: 46bd mov sp, r7
80030fa: f85d 7b04 ldr.w r7, [sp], #4
80030fe: 4770 bx lr
8003100: e000ed00 .word 0xe000ed00
08003104 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8003104: b480 push {r7}
8003106: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8003108: 4b04 ldr r3, [pc, #16] @ (800311c <__NVIC_GetPriorityGrouping+0x18>)
800310a: 68db ldr r3, [r3, #12]
800310c: 0a1b lsrs r3, r3, #8
800310e: f003 0307 and.w r3, r3, #7
}
8003112: 4618 mov r0, r3
8003114: 46bd mov sp, r7
8003116: f85d 7b04 ldr.w r7, [sp], #4
800311a: 4770 bx lr
800311c: e000ed00 .word 0xe000ed00
08003120 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003120: b480 push {r7}
8003122: b083 sub sp, #12
8003124: af00 add r7, sp, #0
8003126: 4603 mov r3, r0
8003128: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800312a: f997 3007 ldrsb.w r3, [r7, #7]
800312e: 2b00 cmp r3, #0
8003130: db0b blt.n 800314a <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8003132: 79fb ldrb r3, [r7, #7]
8003134: f003 021f and.w r2, r3, #31
8003138: 4907 ldr r1, [pc, #28] @ (8003158 <__NVIC_EnableIRQ+0x38>)
800313a: f997 3007 ldrsb.w r3, [r7, #7]
800313e: 095b lsrs r3, r3, #5
8003140: 2001 movs r0, #1
8003142: fa00 f202 lsl.w r2, r0, r2
8003146: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
800314a: bf00 nop
800314c: 370c adds r7, #12
800314e: 46bd mov sp, r7
8003150: f85d 7b04 ldr.w r7, [sp], #4
8003154: 4770 bx lr
8003156: bf00 nop
8003158: e000e100 .word 0xe000e100
0800315c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
800315c: b480 push {r7}
800315e: b083 sub sp, #12
8003160: af00 add r7, sp, #0
8003162: 4603 mov r3, r0
8003164: 6039 str r1, [r7, #0]
8003166: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003168: f997 3007 ldrsb.w r3, [r7, #7]
800316c: 2b00 cmp r3, #0
800316e: db0a blt.n 8003186 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003170: 683b ldr r3, [r7, #0]
8003172: b2da uxtb r2, r3
8003174: 490c ldr r1, [pc, #48] @ (80031a8 <__NVIC_SetPriority+0x4c>)
8003176: f997 3007 ldrsb.w r3, [r7, #7]
800317a: 0112 lsls r2, r2, #4
800317c: b2d2 uxtb r2, r2
800317e: 440b add r3, r1
8003180: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8003184: e00a b.n 800319c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003186: 683b ldr r3, [r7, #0]
8003188: b2da uxtb r2, r3
800318a: 4908 ldr r1, [pc, #32] @ (80031ac <__NVIC_SetPriority+0x50>)
800318c: 79fb ldrb r3, [r7, #7]
800318e: f003 030f and.w r3, r3, #15
8003192: 3b04 subs r3, #4
8003194: 0112 lsls r2, r2, #4
8003196: b2d2 uxtb r2, r2
8003198: 440b add r3, r1
800319a: 761a strb r2, [r3, #24]
}
800319c: bf00 nop
800319e: 370c adds r7, #12
80031a0: 46bd mov sp, r7
80031a2: f85d 7b04 ldr.w r7, [sp], #4
80031a6: 4770 bx lr
80031a8: e000e100 .word 0xe000e100
80031ac: e000ed00 .word 0xe000ed00
080031b0 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80031b0: b480 push {r7}
80031b2: b089 sub sp, #36 @ 0x24
80031b4: af00 add r7, sp, #0
80031b6: 60f8 str r0, [r7, #12]
80031b8: 60b9 str r1, [r7, #8]
80031ba: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80031bc: 68fb ldr r3, [r7, #12]
80031be: f003 0307 and.w r3, r3, #7
80031c2: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80031c4: 69fb ldr r3, [r7, #28]
80031c6: f1c3 0307 rsb r3, r3, #7
80031ca: 2b04 cmp r3, #4
80031cc: bf28 it cs
80031ce: 2304 movcs r3, #4
80031d0: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80031d2: 69fb ldr r3, [r7, #28]
80031d4: 3304 adds r3, #4
80031d6: 2b06 cmp r3, #6
80031d8: d902 bls.n 80031e0 <NVIC_EncodePriority+0x30>
80031da: 69fb ldr r3, [r7, #28]
80031dc: 3b03 subs r3, #3
80031de: e000 b.n 80031e2 <NVIC_EncodePriority+0x32>
80031e0: 2300 movs r3, #0
80031e2: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80031e4: f04f 32ff mov.w r2, #4294967295
80031e8: 69bb ldr r3, [r7, #24]
80031ea: fa02 f303 lsl.w r3, r2, r3
80031ee: 43da mvns r2, r3
80031f0: 68bb ldr r3, [r7, #8]
80031f2: 401a ands r2, r3
80031f4: 697b ldr r3, [r7, #20]
80031f6: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80031f8: f04f 31ff mov.w r1, #4294967295
80031fc: 697b ldr r3, [r7, #20]
80031fe: fa01 f303 lsl.w r3, r1, r3
8003202: 43d9 mvns r1, r3
8003204: 687b ldr r3, [r7, #4]
8003206: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003208: 4313 orrs r3, r2
);
}
800320a: 4618 mov r0, r3
800320c: 3724 adds r7, #36 @ 0x24
800320e: 46bd mov sp, r7
8003210: f85d 7b04 ldr.w r7, [sp], #4
8003214: 4770 bx lr
...
08003218 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8003218: b580 push {r7, lr}
800321a: b082 sub sp, #8
800321c: af00 add r7, sp, #0
800321e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8003220: 687b ldr r3, [r7, #4]
8003222: 3b01 subs r3, #1
8003224: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8003228: d301 bcc.n 800322e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800322a: 2301 movs r3, #1
800322c: e00f b.n 800324e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800322e: 4a0a ldr r2, [pc, #40] @ (8003258 <SysTick_Config+0x40>)
8003230: 687b ldr r3, [r7, #4]
8003232: 3b01 subs r3, #1
8003234: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8003236: 210f movs r1, #15
8003238: f04f 30ff mov.w r0, #4294967295
800323c: f7ff ff8e bl 800315c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003240: 4b05 ldr r3, [pc, #20] @ (8003258 <SysTick_Config+0x40>)
8003242: 2200 movs r2, #0
8003244: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8003246: 4b04 ldr r3, [pc, #16] @ (8003258 <SysTick_Config+0x40>)
8003248: 2207 movs r2, #7
800324a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
800324c: 2300 movs r3, #0
}
800324e: 4618 mov r0, r3
8003250: 3708 adds r7, #8
8003252: 46bd mov sp, r7
8003254: bd80 pop {r7, pc}
8003256: bf00 nop
8003258: e000e010 .word 0xe000e010
0800325c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800325c: b580 push {r7, lr}
800325e: b082 sub sp, #8
8003260: af00 add r7, sp, #0
8003262: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003264: 6878 ldr r0, [r7, #4]
8003266: f7ff ff29 bl 80030bc <__NVIC_SetPriorityGrouping>
}
800326a: bf00 nop
800326c: 3708 adds r7, #8
800326e: 46bd mov sp, r7
8003270: bd80 pop {r7, pc}
08003272 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003272: b580 push {r7, lr}
8003274: b086 sub sp, #24
8003276: af00 add r7, sp, #0
8003278: 4603 mov r3, r0
800327a: 60b9 str r1, [r7, #8]
800327c: 607a str r2, [r7, #4]
800327e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8003280: 2300 movs r3, #0
8003282: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8003284: f7ff ff3e bl 8003104 <__NVIC_GetPriorityGrouping>
8003288: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800328a: 687a ldr r2, [r7, #4]
800328c: 68b9 ldr r1, [r7, #8]
800328e: 6978 ldr r0, [r7, #20]
8003290: f7ff ff8e bl 80031b0 <NVIC_EncodePriority>
8003294: 4602 mov r2, r0
8003296: f997 300f ldrsb.w r3, [r7, #15]
800329a: 4611 mov r1, r2
800329c: 4618 mov r0, r3
800329e: f7ff ff5d bl 800315c <__NVIC_SetPriority>
}
80032a2: bf00 nop
80032a4: 3718 adds r7, #24
80032a6: 46bd mov sp, r7
80032a8: bd80 pop {r7, pc}
080032aa <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80032aa: b580 push {r7, lr}
80032ac: b082 sub sp, #8
80032ae: af00 add r7, sp, #0
80032b0: 4603 mov r3, r0
80032b2: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80032b4: f997 3007 ldrsb.w r3, [r7, #7]
80032b8: 4618 mov r0, r3
80032ba: f7ff ff31 bl 8003120 <__NVIC_EnableIRQ>
}
80032be: bf00 nop
80032c0: 3708 adds r7, #8
80032c2: 46bd mov sp, r7
80032c4: bd80 pop {r7, pc}
080032c6 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80032c6: b580 push {r7, lr}
80032c8: b082 sub sp, #8
80032ca: af00 add r7, sp, #0
80032cc: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80032ce: 6878 ldr r0, [r7, #4]
80032d0: f7ff ffa2 bl 8003218 <SysTick_Config>
80032d4: 4603 mov r3, r0
}
80032d6: 4618 mov r0, r3
80032d8: 3708 adds r7, #8
80032da: 46bd mov sp, r7
80032dc: bd80 pop {r7, pc}
...
080032e0 <HAL_DFSDM_ChannelInit>:
* in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
80032e0: b580 push {r7, lr}
80032e2: b082 sub sp, #8
80032e4: af00 add r7, sp, #0
80032e6: 6078 str r0, [r7, #4]
/* Check DFSDM Channel handle */
if (hdfsdm_channel == NULL)
80032e8: 687b ldr r3, [r7, #4]
80032ea: 2b00 cmp r3, #0
80032ec: d101 bne.n 80032f2 <HAL_DFSDM_ChannelInit+0x12>
{
return HAL_ERROR;
80032ee: 2301 movs r3, #1
80032f0: e0ac b.n 800344c <HAL_DFSDM_ChannelInit+0x16c>
assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
/* Check that channel has not been already initialized */
if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
80032f2: 687b ldr r3, [r7, #4]
80032f4: 681b ldr r3, [r3, #0]
80032f6: 4618 mov r0, r3
80032f8: f000 f8b2 bl 8003460 <DFSDM_GetChannelFromInstance>
80032fc: 4603 mov r3, r0
80032fe: 4a55 ldr r2, [pc, #340] @ (8003454 <HAL_DFSDM_ChannelInit+0x174>)
8003300: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003304: 2b00 cmp r3, #0
8003306: d001 beq.n 800330c <HAL_DFSDM_ChannelInit+0x2c>
{
return HAL_ERROR;
8003308: 2301 movs r3, #1
800330a: e09f b.n 800344c <HAL_DFSDM_ChannelInit+0x16c>
hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
}
hdfsdm_channel->MspInitCallback(hdfsdm_channel);
#else
/* Call MSP init function */
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
800330c: 6878 ldr r0, [r7, #4]
800330e: f7fe fac5 bl 800189c <HAL_DFSDM_ChannelMspInit>
#endif
/* Update the channel counter */
v_dfsdm1ChannelCounter++;
8003312: 4b51 ldr r3, [pc, #324] @ (8003458 <HAL_DFSDM_ChannelInit+0x178>)
8003314: 681b ldr r3, [r3, #0]
8003316: 3301 adds r3, #1
8003318: 4a4f ldr r2, [pc, #316] @ (8003458 <HAL_DFSDM_ChannelInit+0x178>)
800331a: 6013 str r3, [r2, #0]
/* Configure output serial clock and enable global DFSDM interface only for first channel */
if (v_dfsdm1ChannelCounter == 1U)
800331c: 4b4e ldr r3, [pc, #312] @ (8003458 <HAL_DFSDM_ChannelInit+0x178>)
800331e: 681b ldr r3, [r3, #0]
8003320: 2b01 cmp r3, #1
8003322: d125 bne.n 8003370 <HAL_DFSDM_ChannelInit+0x90>
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
/* Set the output serial clock source */
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
8003324: 4b4d ldr r3, [pc, #308] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
8003326: 681b ldr r3, [r3, #0]
8003328: 4a4c ldr r2, [pc, #304] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
800332a: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
800332e: 6013 str r3, [r2, #0]
DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
8003330: 4b4a ldr r3, [pc, #296] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
8003332: 681a ldr r2, [r3, #0]
8003334: 687b ldr r3, [r7, #4]
8003336: 689b ldr r3, [r3, #8]
8003338: 4948 ldr r1, [pc, #288] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
800333a: 4313 orrs r3, r2
800333c: 600b str r3, [r1, #0]
/* Reset clock divider */
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
800333e: 4b47 ldr r3, [pc, #284] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
8003340: 681b ldr r3, [r3, #0]
8003342: 4a46 ldr r2, [pc, #280] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
8003344: f423 037f bic.w r3, r3, #16711680 @ 0xff0000
8003348: 6013 str r3, [r2, #0]
if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
800334a: 687b ldr r3, [r7, #4]
800334c: 791b ldrb r3, [r3, #4]
800334e: 2b01 cmp r3, #1
8003350: d108 bne.n 8003364 <HAL_DFSDM_ChannelInit+0x84>
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
/* Set the output clock divider */
DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
8003352: 4b42 ldr r3, [pc, #264] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
8003354: 681a ldr r2, [r3, #0]
8003356: 687b ldr r3, [r7, #4]
8003358: 68db ldr r3, [r3, #12]
800335a: 3b01 subs r3, #1
800335c: 041b lsls r3, r3, #16
800335e: 493f ldr r1, [pc, #252] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
8003360: 4313 orrs r3, r2
8003362: 600b str r3, [r1, #0]
DFSDM_CHCFGR1_CKOUTDIV_Pos);
}
/* enable the DFSDM global interface */
DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
8003364: 4b3d ldr r3, [pc, #244] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
8003366: 681b ldr r3, [r3, #0]
8003368: 4a3c ldr r2, [pc, #240] @ (800345c <HAL_DFSDM_ChannelInit+0x17c>)
800336a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
800336e: 6013 str r3, [r2, #0]
}
/* Set channel input parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
8003370: 687b ldr r3, [r7, #4]
8003372: 681b ldr r3, [r3, #0]
8003374: 681a ldr r2, [r3, #0]
8003376: 687b ldr r3, [r7, #4]
8003378: 681b ldr r3, [r3, #0]
800337a: f422 4271 bic.w r2, r2, #61696 @ 0xf100
800337e: 601a str r2, [r3, #0]
DFSDM_CHCFGR1_CHINSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
8003380: 687b ldr r3, [r7, #4]
8003382: 681b ldr r3, [r3, #0]
8003384: 6819 ldr r1, [r3, #0]
8003386: 687b ldr r3, [r7, #4]
8003388: 691a ldr r2, [r3, #16]
hdfsdm_channel->Init.Input.DataPacking |
800338a: 687b ldr r3, [r7, #4]
800338c: 695b ldr r3, [r3, #20]
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
800338e: 431a orrs r2, r3
hdfsdm_channel->Init.Input.Pins);
8003390: 687b ldr r3, [r7, #4]
8003392: 699b ldr r3, [r3, #24]
hdfsdm_channel->Init.Input.DataPacking |
8003394: 431a orrs r2, r3
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
8003396: 687b ldr r3, [r7, #4]
8003398: 681b ldr r3, [r3, #0]
800339a: 430a orrs r2, r1
800339c: 601a str r2, [r3, #0]
/* Set serial interface parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
800339e: 687b ldr r3, [r7, #4]
80033a0: 681b ldr r3, [r3, #0]
80033a2: 681a ldr r2, [r3, #0]
80033a4: 687b ldr r3, [r7, #4]
80033a6: 681b ldr r3, [r3, #0]
80033a8: f022 020f bic.w r2, r2, #15
80033ac: 601a str r2, [r3, #0]
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
80033ae: 687b ldr r3, [r7, #4]
80033b0: 681b ldr r3, [r3, #0]
80033b2: 6819 ldr r1, [r3, #0]
80033b4: 687b ldr r3, [r7, #4]
80033b6: 69da ldr r2, [r3, #28]
hdfsdm_channel->Init.SerialInterface.SpiClock);
80033b8: 687b ldr r3, [r7, #4]
80033ba: 6a1b ldr r3, [r3, #32]
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
80033bc: 431a orrs r2, r3
80033be: 687b ldr r3, [r7, #4]
80033c0: 681b ldr r3, [r3, #0]
80033c2: 430a orrs r2, r1
80033c4: 601a str r2, [r3, #0]
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
80033c6: 687b ldr r3, [r7, #4]
80033c8: 681b ldr r3, [r3, #0]
80033ca: 689a ldr r2, [r3, #8]
80033cc: 687b ldr r3, [r7, #4]
80033ce: 681b ldr r3, [r3, #0]
80033d0: f422 025f bic.w r2, r2, #14614528 @ 0xdf0000
80033d4: 609a str r2, [r3, #8]
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
80033d6: 687b ldr r3, [r7, #4]
80033d8: 681b ldr r3, [r3, #0]
80033da: 6899 ldr r1, [r3, #8]
80033dc: 687b ldr r3, [r7, #4]
80033de: 6a5a ldr r2, [r3, #36] @ 0x24
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
80033e0: 687b ldr r3, [r7, #4]
80033e2: 6a9b ldr r3, [r3, #40] @ 0x28
80033e4: 3b01 subs r3, #1
80033e6: 041b lsls r3, r3, #16
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
80033e8: 431a orrs r2, r3
80033ea: 687b ldr r3, [r7, #4]
80033ec: 681b ldr r3, [r3, #0]
80033ee: 430a orrs r2, r1
80033f0: 609a str r2, [r3, #8]
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
80033f2: 687b ldr r3, [r7, #4]
80033f4: 681b ldr r3, [r3, #0]
80033f6: 685a ldr r2, [r3, #4]
80033f8: 687b ldr r3, [r7, #4]
80033fa: 681b ldr r3, [r3, #0]
80033fc: f002 0207 and.w r2, r2, #7
8003400: 605a str r2, [r3, #4]
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
8003402: 687b ldr r3, [r7, #4]
8003404: 681b ldr r3, [r3, #0]
8003406: 6859 ldr r1, [r3, #4]
8003408: 687b ldr r3, [r7, #4]
800340a: 6adb ldr r3, [r3, #44] @ 0x2c
800340c: 021a lsls r2, r3, #8
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
800340e: 687b ldr r3, [r7, #4]
8003410: 6b1b ldr r3, [r3, #48] @ 0x30
8003412: 00db lsls r3, r3, #3
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
8003414: 431a orrs r2, r3
8003416: 687b ldr r3, [r7, #4]
8003418: 681b ldr r3, [r3, #0]
800341a: 430a orrs r2, r1
800341c: 605a str r2, [r3, #4]
/* Enable DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
800341e: 687b ldr r3, [r7, #4]
8003420: 681b ldr r3, [r3, #0]
8003422: 681a ldr r2, [r3, #0]
8003424: 687b ldr r3, [r7, #4]
8003426: 681b ldr r3, [r3, #0]
8003428: f042 0280 orr.w r2, r2, #128 @ 0x80
800342c: 601a str r2, [r3, #0]
/* Set DFSDM Channel to ready state */
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
800342e: 687b ldr r3, [r7, #4]
8003430: 2201 movs r2, #1
8003432: f883 2034 strb.w r2, [r3, #52] @ 0x34
/* Store channel handle in DFSDM channel handle table */
a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
8003436: 687b ldr r3, [r7, #4]
8003438: 681b ldr r3, [r3, #0]
800343a: 4618 mov r0, r3
800343c: f000 f810 bl 8003460 <DFSDM_GetChannelFromInstance>
8003440: 4602 mov r2, r0
8003442: 4904 ldr r1, [pc, #16] @ (8003454 <HAL_DFSDM_ChannelInit+0x174>)
8003444: 687b ldr r3, [r7, #4]
8003446: f841 3022 str.w r3, [r1, r2, lsl #2]
return HAL_OK;
800344a: 2300 movs r3, #0
}
800344c: 4618 mov r0, r3
800344e: 3708 adds r7, #8
8003450: 46bd mov sp, r7
8003452: bd80 pop {r7, pc}
8003454: 2000066c .word 0x2000066c
8003458: 20000668 .word 0x20000668
800345c: 40016000 .word 0x40016000
08003460 <DFSDM_GetChannelFromInstance>:
* @brief This function allows to get the channel number from channel instance.
* @param Instance DFSDM channel instance.
* @retval Channel number.
*/
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
{
8003460: b480 push {r7}
8003462: b085 sub sp, #20
8003464: af00 add r7, sp, #0
8003466: 6078 str r0, [r7, #4]
uint32_t channel;
/* Get channel from instance */
if (Instance == DFSDM1_Channel0)
8003468: 687b ldr r3, [r7, #4]
800346a: 4a1c ldr r2, [pc, #112] @ (80034dc <DFSDM_GetChannelFromInstance+0x7c>)
800346c: 4293 cmp r3, r2
800346e: d102 bne.n 8003476 <DFSDM_GetChannelFromInstance+0x16>
{
channel = 0;
8003470: 2300 movs r3, #0
8003472: 60fb str r3, [r7, #12]
8003474: e02b b.n 80034ce <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel1)
8003476: 687b ldr r3, [r7, #4]
8003478: 4a19 ldr r2, [pc, #100] @ (80034e0 <DFSDM_GetChannelFromInstance+0x80>)
800347a: 4293 cmp r3, r2
800347c: d102 bne.n 8003484 <DFSDM_GetChannelFromInstance+0x24>
{
channel = 1;
800347e: 2301 movs r3, #1
8003480: 60fb str r3, [r7, #12]
8003482: e024 b.n 80034ce <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel2)
8003484: 687b ldr r3, [r7, #4]
8003486: 4a17 ldr r2, [pc, #92] @ (80034e4 <DFSDM_GetChannelFromInstance+0x84>)
8003488: 4293 cmp r3, r2
800348a: d102 bne.n 8003492 <DFSDM_GetChannelFromInstance+0x32>
{
channel = 2;
800348c: 2302 movs r3, #2
800348e: 60fb str r3, [r7, #12]
8003490: e01d b.n 80034ce <DFSDM_GetChannelFromInstance+0x6e>
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
else if (Instance == DFSDM1_Channel4)
8003492: 687b ldr r3, [r7, #4]
8003494: 4a14 ldr r2, [pc, #80] @ (80034e8 <DFSDM_GetChannelFromInstance+0x88>)
8003496: 4293 cmp r3, r2
8003498: d102 bne.n 80034a0 <DFSDM_GetChannelFromInstance+0x40>
{
channel = 4;
800349a: 2304 movs r3, #4
800349c: 60fb str r3, [r7, #12]
800349e: e016 b.n 80034ce <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel5)
80034a0: 687b ldr r3, [r7, #4]
80034a2: 4a12 ldr r2, [pc, #72] @ (80034ec <DFSDM_GetChannelFromInstance+0x8c>)
80034a4: 4293 cmp r3, r2
80034a6: d102 bne.n 80034ae <DFSDM_GetChannelFromInstance+0x4e>
{
channel = 5;
80034a8: 2305 movs r3, #5
80034aa: 60fb str r3, [r7, #12]
80034ac: e00f b.n 80034ce <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel6)
80034ae: 687b ldr r3, [r7, #4]
80034b0: 4a0f ldr r2, [pc, #60] @ (80034f0 <DFSDM_GetChannelFromInstance+0x90>)
80034b2: 4293 cmp r3, r2
80034b4: d102 bne.n 80034bc <DFSDM_GetChannelFromInstance+0x5c>
{
channel = 6;
80034b6: 2306 movs r3, #6
80034b8: 60fb str r3, [r7, #12]
80034ba: e008 b.n 80034ce <DFSDM_GetChannelFromInstance+0x6e>
}
else if (Instance == DFSDM1_Channel7)
80034bc: 687b ldr r3, [r7, #4]
80034be: 4a0d ldr r2, [pc, #52] @ (80034f4 <DFSDM_GetChannelFromInstance+0x94>)
80034c0: 4293 cmp r3, r2
80034c2: d102 bne.n 80034ca <DFSDM_GetChannelFromInstance+0x6a>
{
channel = 7;
80034c4: 2307 movs r3, #7
80034c6: 60fb str r3, [r7, #12]
80034c8: e001 b.n 80034ce <DFSDM_GetChannelFromInstance+0x6e>
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
else /* DFSDM1_Channel3 */
{
channel = 3;
80034ca: 2303 movs r3, #3
80034cc: 60fb str r3, [r7, #12]
}
return channel;
80034ce: 68fb ldr r3, [r7, #12]
}
80034d0: 4618 mov r0, r3
80034d2: 3714 adds r7, #20
80034d4: 46bd mov sp, r7
80034d6: f85d 7b04 ldr.w r7, [sp], #4
80034da: 4770 bx lr
80034dc: 40016000 .word 0x40016000
80034e0: 40016020 .word 0x40016020
80034e4: 40016040 .word 0x40016040
80034e8: 40016080 .word 0x40016080
80034ec: 400160a0 .word 0x400160a0
80034f0: 400160c0 .word 0x400160c0
80034f4: 400160e0 .word 0x400160e0
080034f8 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80034f8: b480 push {r7}
80034fa: b087 sub sp, #28
80034fc: af00 add r7, sp, #0
80034fe: 6078 str r0, [r7, #4]
8003500: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8003502: 2300 movs r3, #0
8003504: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003506: e17f b.n 8003808 <HAL_GPIO_Init+0x310>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8003508: 683b ldr r3, [r7, #0]
800350a: 681a ldr r2, [r3, #0]
800350c: 2101 movs r1, #1
800350e: 697b ldr r3, [r7, #20]
8003510: fa01 f303 lsl.w r3, r1, r3
8003514: 4013 ands r3, r2
8003516: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8003518: 68fb ldr r3, [r7, #12]
800351a: 2b00 cmp r3, #0
800351c: f000 8171 beq.w 8003802 <HAL_GPIO_Init+0x30a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8003520: 683b ldr r3, [r7, #0]
8003522: 685b ldr r3, [r3, #4]
8003524: f003 0303 and.w r3, r3, #3
8003528: 2b01 cmp r3, #1
800352a: d005 beq.n 8003538 <HAL_GPIO_Init+0x40>
800352c: 683b ldr r3, [r7, #0]
800352e: 685b ldr r3, [r3, #4]
8003530: f003 0303 and.w r3, r3, #3
8003534: 2b02 cmp r3, #2
8003536: d130 bne.n 800359a <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8003538: 687b ldr r3, [r7, #4]
800353a: 689b ldr r3, [r3, #8]
800353c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
800353e: 697b ldr r3, [r7, #20]
8003540: 005b lsls r3, r3, #1
8003542: 2203 movs r2, #3
8003544: fa02 f303 lsl.w r3, r2, r3
8003548: 43db mvns r3, r3
800354a: 693a ldr r2, [r7, #16]
800354c: 4013 ands r3, r2
800354e: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8003550: 683b ldr r3, [r7, #0]
8003552: 68da ldr r2, [r3, #12]
8003554: 697b ldr r3, [r7, #20]
8003556: 005b lsls r3, r3, #1
8003558: fa02 f303 lsl.w r3, r2, r3
800355c: 693a ldr r2, [r7, #16]
800355e: 4313 orrs r3, r2
8003560: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8003562: 687b ldr r3, [r7, #4]
8003564: 693a ldr r2, [r7, #16]
8003566: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8003568: 687b ldr r3, [r7, #4]
800356a: 685b ldr r3, [r3, #4]
800356c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
800356e: 2201 movs r2, #1
8003570: 697b ldr r3, [r7, #20]
8003572: fa02 f303 lsl.w r3, r2, r3
8003576: 43db mvns r3, r3
8003578: 693a ldr r2, [r7, #16]
800357a: 4013 ands r3, r2
800357c: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800357e: 683b ldr r3, [r7, #0]
8003580: 685b ldr r3, [r3, #4]
8003582: 091b lsrs r3, r3, #4
8003584: f003 0201 and.w r2, r3, #1
8003588: 697b ldr r3, [r7, #20]
800358a: fa02 f303 lsl.w r3, r2, r3
800358e: 693a ldr r2, [r7, #16]
8003590: 4313 orrs r3, r2
8003592: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8003594: 687b ldr r3, [r7, #4]
8003596: 693a ldr r2, [r7, #16]
8003598: 605a str r2, [r3, #4]
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* In case of Analog mode, check if ADC control mode is selected */
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
800359a: 683b ldr r3, [r7, #0]
800359c: 685b ldr r3, [r3, #4]
800359e: f003 0303 and.w r3, r3, #3
80035a2: 2b03 cmp r3, #3
80035a4: d118 bne.n 80035d8 <HAL_GPIO_Init+0xe0>
{
/* Configure the IO Output Type */
temp = GPIOx->ASCR;
80035a6: 687b ldr r3, [r7, #4]
80035a8: 6adb ldr r3, [r3, #44] @ 0x2c
80035aa: 613b str r3, [r7, #16]
temp &= ~(GPIO_ASCR_ASC0 << position) ;
80035ac: 2201 movs r2, #1
80035ae: 697b ldr r3, [r7, #20]
80035b0: fa02 f303 lsl.w r3, r2, r3
80035b4: 43db mvns r3, r3
80035b6: 693a ldr r2, [r7, #16]
80035b8: 4013 ands r3, r2
80035ba: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
80035bc: 683b ldr r3, [r7, #0]
80035be: 685b ldr r3, [r3, #4]
80035c0: 08db lsrs r3, r3, #3
80035c2: f003 0201 and.w r2, r3, #1
80035c6: 697b ldr r3, [r7, #20]
80035c8: fa02 f303 lsl.w r3, r2, r3
80035cc: 693a ldr r2, [r7, #16]
80035ce: 4313 orrs r3, r2
80035d0: 613b str r3, [r7, #16]
GPIOx->ASCR = temp;
80035d2: 687b ldr r3, [r7, #4]
80035d4: 693a ldr r2, [r7, #16]
80035d6: 62da str r2, [r3, #44] @ 0x2c
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80035d8: 683b ldr r3, [r7, #0]
80035da: 685b ldr r3, [r3, #4]
80035dc: f003 0303 and.w r3, r3, #3
80035e0: 2b03 cmp r3, #3
80035e2: d017 beq.n 8003614 <HAL_GPIO_Init+0x11c>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
temp = GPIOx->PUPDR;
80035e4: 687b ldr r3, [r7, #4]
80035e6: 68db ldr r3, [r3, #12]
80035e8: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
80035ea: 697b ldr r3, [r7, #20]
80035ec: 005b lsls r3, r3, #1
80035ee: 2203 movs r2, #3
80035f0: fa02 f303 lsl.w r3, r2, r3
80035f4: 43db mvns r3, r3
80035f6: 693a ldr r2, [r7, #16]
80035f8: 4013 ands r3, r2
80035fa: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80035fc: 683b ldr r3, [r7, #0]
80035fe: 689a ldr r2, [r3, #8]
8003600: 697b ldr r3, [r7, #20]
8003602: 005b lsls r3, r3, #1
8003604: fa02 f303 lsl.w r3, r2, r3
8003608: 693a ldr r2, [r7, #16]
800360a: 4313 orrs r3, r2
800360c: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
800360e: 687b ldr r3, [r7, #4]
8003610: 693a ldr r2, [r7, #16]
8003612: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8003614: 683b ldr r3, [r7, #0]
8003616: 685b ldr r3, [r3, #4]
8003618: f003 0303 and.w r3, r3, #3
800361c: 2b02 cmp r3, #2
800361e: d123 bne.n 8003668 <HAL_GPIO_Init+0x170>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8003620: 697b ldr r3, [r7, #20]
8003622: 08da lsrs r2, r3, #3
8003624: 687b ldr r3, [r7, #4]
8003626: 3208 adds r2, #8
8003628: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800362c: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
800362e: 697b ldr r3, [r7, #20]
8003630: f003 0307 and.w r3, r3, #7
8003634: 009b lsls r3, r3, #2
8003636: 220f movs r2, #15
8003638: fa02 f303 lsl.w r3, r2, r3
800363c: 43db mvns r3, r3
800363e: 693a ldr r2, [r7, #16]
8003640: 4013 ands r3, r2
8003642: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8003644: 683b ldr r3, [r7, #0]
8003646: 691a ldr r2, [r3, #16]
8003648: 697b ldr r3, [r7, #20]
800364a: f003 0307 and.w r3, r3, #7
800364e: 009b lsls r3, r3, #2
8003650: fa02 f303 lsl.w r3, r2, r3
8003654: 693a ldr r2, [r7, #16]
8003656: 4313 orrs r3, r2
8003658: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
800365a: 697b ldr r3, [r7, #20]
800365c: 08da lsrs r2, r3, #3
800365e: 687b ldr r3, [r7, #4]
8003660: 3208 adds r2, #8
8003662: 6939 ldr r1, [r7, #16]
8003664: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8003668: 687b ldr r3, [r7, #4]
800366a: 681b ldr r3, [r3, #0]
800366c: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
800366e: 697b ldr r3, [r7, #20]
8003670: 005b lsls r3, r3, #1
8003672: 2203 movs r2, #3
8003674: fa02 f303 lsl.w r3, r2, r3
8003678: 43db mvns r3, r3
800367a: 693a ldr r2, [r7, #16]
800367c: 4013 ands r3, r2
800367e: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8003680: 683b ldr r3, [r7, #0]
8003682: 685b ldr r3, [r3, #4]
8003684: f003 0203 and.w r2, r3, #3
8003688: 697b ldr r3, [r7, #20]
800368a: 005b lsls r3, r3, #1
800368c: fa02 f303 lsl.w r3, r2, r3
8003690: 693a ldr r2, [r7, #16]
8003692: 4313 orrs r3, r2
8003694: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8003696: 687b ldr r3, [r7, #4]
8003698: 693a ldr r2, [r7, #16]
800369a: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800369c: 683b ldr r3, [r7, #0]
800369e: 685b ldr r3, [r3, #4]
80036a0: f403 3340 and.w r3, r3, #196608 @ 0x30000
80036a4: 2b00 cmp r3, #0
80036a6: f000 80ac beq.w 8003802 <HAL_GPIO_Init+0x30a>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80036aa: 4b5f ldr r3, [pc, #380] @ (8003828 <HAL_GPIO_Init+0x330>)
80036ac: 6e1b ldr r3, [r3, #96] @ 0x60
80036ae: 4a5e ldr r2, [pc, #376] @ (8003828 <HAL_GPIO_Init+0x330>)
80036b0: f043 0301 orr.w r3, r3, #1
80036b4: 6613 str r3, [r2, #96] @ 0x60
80036b6: 4b5c ldr r3, [pc, #368] @ (8003828 <HAL_GPIO_Init+0x330>)
80036b8: 6e1b ldr r3, [r3, #96] @ 0x60
80036ba: f003 0301 and.w r3, r3, #1
80036be: 60bb str r3, [r7, #8]
80036c0: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
80036c2: 4a5a ldr r2, [pc, #360] @ (800382c <HAL_GPIO_Init+0x334>)
80036c4: 697b ldr r3, [r7, #20]
80036c6: 089b lsrs r3, r3, #2
80036c8: 3302 adds r3, #2
80036ca: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80036ce: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
80036d0: 697b ldr r3, [r7, #20]
80036d2: f003 0303 and.w r3, r3, #3
80036d6: 009b lsls r3, r3, #2
80036d8: 220f movs r2, #15
80036da: fa02 f303 lsl.w r3, r2, r3
80036de: 43db mvns r3, r3
80036e0: 693a ldr r2, [r7, #16]
80036e2: 4013 ands r3, r2
80036e4: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
80036e6: 687b ldr r3, [r7, #4]
80036e8: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
80036ec: d025 beq.n 800373a <HAL_GPIO_Init+0x242>
80036ee: 687b ldr r3, [r7, #4]
80036f0: 4a4f ldr r2, [pc, #316] @ (8003830 <HAL_GPIO_Init+0x338>)
80036f2: 4293 cmp r3, r2
80036f4: d01f beq.n 8003736 <HAL_GPIO_Init+0x23e>
80036f6: 687b ldr r3, [r7, #4]
80036f8: 4a4e ldr r2, [pc, #312] @ (8003834 <HAL_GPIO_Init+0x33c>)
80036fa: 4293 cmp r3, r2
80036fc: d019 beq.n 8003732 <HAL_GPIO_Init+0x23a>
80036fe: 687b ldr r3, [r7, #4]
8003700: 4a4d ldr r2, [pc, #308] @ (8003838 <HAL_GPIO_Init+0x340>)
8003702: 4293 cmp r3, r2
8003704: d013 beq.n 800372e <HAL_GPIO_Init+0x236>
8003706: 687b ldr r3, [r7, #4]
8003708: 4a4c ldr r2, [pc, #304] @ (800383c <HAL_GPIO_Init+0x344>)
800370a: 4293 cmp r3, r2
800370c: d00d beq.n 800372a <HAL_GPIO_Init+0x232>
800370e: 687b ldr r3, [r7, #4]
8003710: 4a4b ldr r2, [pc, #300] @ (8003840 <HAL_GPIO_Init+0x348>)
8003712: 4293 cmp r3, r2
8003714: d007 beq.n 8003726 <HAL_GPIO_Init+0x22e>
8003716: 687b ldr r3, [r7, #4]
8003718: 4a4a ldr r2, [pc, #296] @ (8003844 <HAL_GPIO_Init+0x34c>)
800371a: 4293 cmp r3, r2
800371c: d101 bne.n 8003722 <HAL_GPIO_Init+0x22a>
800371e: 2306 movs r3, #6
8003720: e00c b.n 800373c <HAL_GPIO_Init+0x244>
8003722: 2307 movs r3, #7
8003724: e00a b.n 800373c <HAL_GPIO_Init+0x244>
8003726: 2305 movs r3, #5
8003728: e008 b.n 800373c <HAL_GPIO_Init+0x244>
800372a: 2304 movs r3, #4
800372c: e006 b.n 800373c <HAL_GPIO_Init+0x244>
800372e: 2303 movs r3, #3
8003730: e004 b.n 800373c <HAL_GPIO_Init+0x244>
8003732: 2302 movs r3, #2
8003734: e002 b.n 800373c <HAL_GPIO_Init+0x244>
8003736: 2301 movs r3, #1
8003738: e000 b.n 800373c <HAL_GPIO_Init+0x244>
800373a: 2300 movs r3, #0
800373c: 697a ldr r2, [r7, #20]
800373e: f002 0203 and.w r2, r2, #3
8003742: 0092 lsls r2, r2, #2
8003744: 4093 lsls r3, r2
8003746: 693a ldr r2, [r7, #16]
8003748: 4313 orrs r3, r2
800374a: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
800374c: 4937 ldr r1, [pc, #220] @ (800382c <HAL_GPIO_Init+0x334>)
800374e: 697b ldr r3, [r7, #20]
8003750: 089b lsrs r3, r3, #2
8003752: 3302 adds r3, #2
8003754: 693a ldr r2, [r7, #16]
8003756: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
800375a: 4b3b ldr r3, [pc, #236] @ (8003848 <HAL_GPIO_Init+0x350>)
800375c: 689b ldr r3, [r3, #8]
800375e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003760: 68fb ldr r3, [r7, #12]
8003762: 43db mvns r3, r3
8003764: 693a ldr r2, [r7, #16]
8003766: 4013 ands r3, r2
8003768: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
800376a: 683b ldr r3, [r7, #0]
800376c: 685b ldr r3, [r3, #4]
800376e: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003772: 2b00 cmp r3, #0
8003774: d003 beq.n 800377e <HAL_GPIO_Init+0x286>
{
temp |= iocurrent;
8003776: 693a ldr r2, [r7, #16]
8003778: 68fb ldr r3, [r7, #12]
800377a: 4313 orrs r3, r2
800377c: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
800377e: 4a32 ldr r2, [pc, #200] @ (8003848 <HAL_GPIO_Init+0x350>)
8003780: 693b ldr r3, [r7, #16]
8003782: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8003784: 4b30 ldr r3, [pc, #192] @ (8003848 <HAL_GPIO_Init+0x350>)
8003786: 68db ldr r3, [r3, #12]
8003788: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800378a: 68fb ldr r3, [r7, #12]
800378c: 43db mvns r3, r3
800378e: 693a ldr r2, [r7, #16]
8003790: 4013 ands r3, r2
8003792: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8003794: 683b ldr r3, [r7, #0]
8003796: 685b ldr r3, [r3, #4]
8003798: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800379c: 2b00 cmp r3, #0
800379e: d003 beq.n 80037a8 <HAL_GPIO_Init+0x2b0>
{
temp |= iocurrent;
80037a0: 693a ldr r2, [r7, #16]
80037a2: 68fb ldr r3, [r7, #12]
80037a4: 4313 orrs r3, r2
80037a6: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
80037a8: 4a27 ldr r2, [pc, #156] @ (8003848 <HAL_GPIO_Init+0x350>)
80037aa: 693b ldr r3, [r7, #16]
80037ac: 60d3 str r3, [r2, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
80037ae: 4b26 ldr r3, [pc, #152] @ (8003848 <HAL_GPIO_Init+0x350>)
80037b0: 685b ldr r3, [r3, #4]
80037b2: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80037b4: 68fb ldr r3, [r7, #12]
80037b6: 43db mvns r3, r3
80037b8: 693a ldr r2, [r7, #16]
80037ba: 4013 ands r3, r2
80037bc: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
80037be: 683b ldr r3, [r7, #0]
80037c0: 685b ldr r3, [r3, #4]
80037c2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80037c6: 2b00 cmp r3, #0
80037c8: d003 beq.n 80037d2 <HAL_GPIO_Init+0x2da>
{
temp |= iocurrent;
80037ca: 693a ldr r2, [r7, #16]
80037cc: 68fb ldr r3, [r7, #12]
80037ce: 4313 orrs r3, r2
80037d0: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
80037d2: 4a1d ldr r2, [pc, #116] @ (8003848 <HAL_GPIO_Init+0x350>)
80037d4: 693b ldr r3, [r7, #16]
80037d6: 6053 str r3, [r2, #4]
temp = EXTI->IMR1;
80037d8: 4b1b ldr r3, [pc, #108] @ (8003848 <HAL_GPIO_Init+0x350>)
80037da: 681b ldr r3, [r3, #0]
80037dc: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80037de: 68fb ldr r3, [r7, #12]
80037e0: 43db mvns r3, r3
80037e2: 693a ldr r2, [r7, #16]
80037e4: 4013 ands r3, r2
80037e6: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
80037e8: 683b ldr r3, [r7, #0]
80037ea: 685b ldr r3, [r3, #4]
80037ec: f403 3380 and.w r3, r3, #65536 @ 0x10000
80037f0: 2b00 cmp r3, #0
80037f2: d003 beq.n 80037fc <HAL_GPIO_Init+0x304>
{
temp |= iocurrent;
80037f4: 693a ldr r2, [r7, #16]
80037f6: 68fb ldr r3, [r7, #12]
80037f8: 4313 orrs r3, r2
80037fa: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
80037fc: 4a12 ldr r2, [pc, #72] @ (8003848 <HAL_GPIO_Init+0x350>)
80037fe: 693b ldr r3, [r7, #16]
8003800: 6013 str r3, [r2, #0]
}
}
position++;
8003802: 697b ldr r3, [r7, #20]
8003804: 3301 adds r3, #1
8003806: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003808: 683b ldr r3, [r7, #0]
800380a: 681a ldr r2, [r3, #0]
800380c: 697b ldr r3, [r7, #20]
800380e: fa22 f303 lsr.w r3, r2, r3
8003812: 2b00 cmp r3, #0
8003814: f47f ae78 bne.w 8003508 <HAL_GPIO_Init+0x10>
}
}
8003818: bf00 nop
800381a: bf00 nop
800381c: 371c adds r7, #28
800381e: 46bd mov sp, r7
8003820: f85d 7b04 ldr.w r7, [sp], #4
8003824: 4770 bx lr
8003826: bf00 nop
8003828: 40021000 .word 0x40021000
800382c: 40010000 .word 0x40010000
8003830: 48000400 .word 0x48000400
8003834: 48000800 .word 0x48000800
8003838: 48000c00 .word 0x48000c00
800383c: 48001000 .word 0x48001000
8003840: 48001400 .word 0x48001400
8003844: 48001800 .word 0x48001800
8003848: 40010400 .word 0x40010400
0800384c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
800384c: b480 push {r7}
800384e: b083 sub sp, #12
8003850: af00 add r7, sp, #0
8003852: 6078 str r0, [r7, #4]
8003854: 460b mov r3, r1
8003856: 807b strh r3, [r7, #2]
8003858: 4613 mov r3, r2
800385a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
800385c: 787b ldrb r3, [r7, #1]
800385e: 2b00 cmp r3, #0
8003860: d003 beq.n 800386a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8003862: 887a ldrh r2, [r7, #2]
8003864: 687b ldr r3, [r7, #4]
8003866: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8003868: e002 b.n 8003870 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
800386a: 887a ldrh r2, [r7, #2]
800386c: 687b ldr r3, [r7, #4]
800386e: 629a str r2, [r3, #40] @ 0x28
}
8003870: bf00 nop
8003872: 370c adds r7, #12
8003874: 46bd mov sp, r7
8003876: f85d 7b04 ldr.w r7, [sp], #4
800387a: 4770 bx lr
0800387c <HAL_GPIO_EXTI_IRQHandler>:
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
800387c: b580 push {r7, lr}
800387e: b082 sub sp, #8
8003880: af00 add r7, sp, #0
8003882: 4603 mov r3, r0
8003884: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
8003886: 4b08 ldr r3, [pc, #32] @ (80038a8 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8003888: 695a ldr r2, [r3, #20]
800388a: 88fb ldrh r3, [r7, #6]
800388c: 4013 ands r3, r2
800388e: 2b00 cmp r3, #0
8003890: d006 beq.n 80038a0 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8003892: 4a05 ldr r2, [pc, #20] @ (80038a8 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8003894: 88fb ldrh r3, [r7, #6]
8003896: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
8003898: 88fb ldrh r3, [r7, #6]
800389a: 4618 mov r0, r3
800389c: f000 f806 bl 80038ac <HAL_GPIO_EXTI_Callback>
}
}
80038a0: bf00 nop
80038a2: 3708 adds r7, #8
80038a4: 46bd mov sp, r7
80038a6: bd80 pop {r7, pc}
80038a8: 40010400 .word 0x40010400
080038ac <HAL_GPIO_EXTI_Callback>:
* @brief EXTI line detection callback.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
80038ac: b480 push {r7}
80038ae: b083 sub sp, #12
80038b0: af00 add r7, sp, #0
80038b2: 4603 mov r3, r0
80038b4: 80fb strh r3, [r7, #6]
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
80038b6: bf00 nop
80038b8: 370c adds r7, #12
80038ba: 46bd mov sp, r7
80038bc: f85d 7b04 ldr.w r7, [sp], #4
80038c0: 4770 bx lr
080038c2 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
80038c2: b580 push {r7, lr}
80038c4: b082 sub sp, #8
80038c6: af00 add r7, sp, #0
80038c8: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
80038ca: 687b ldr r3, [r7, #4]
80038cc: 2b00 cmp r3, #0
80038ce: d101 bne.n 80038d4 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
80038d0: 2301 movs r3, #1
80038d2: e08d b.n 80039f0 <HAL_I2C_Init+0x12e>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
80038d4: 687b ldr r3, [r7, #4]
80038d6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80038da: b2db uxtb r3, r3
80038dc: 2b00 cmp r3, #0
80038de: d106 bne.n 80038ee <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
80038e0: 687b ldr r3, [r7, #4]
80038e2: 2200 movs r2, #0
80038e4: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
80038e8: 6878 ldr r0, [r7, #4]
80038ea: f7fe f83b bl 8001964 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
80038ee: 687b ldr r3, [r7, #4]
80038f0: 2224 movs r2, #36 @ 0x24
80038f2: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80038f6: 687b ldr r3, [r7, #4]
80038f8: 681b ldr r3, [r3, #0]
80038fa: 681a ldr r2, [r3, #0]
80038fc: 687b ldr r3, [r7, #4]
80038fe: 681b ldr r3, [r3, #0]
8003900: f022 0201 bic.w r2, r2, #1
8003904: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8003906: 687b ldr r3, [r7, #4]
8003908: 685a ldr r2, [r3, #4]
800390a: 687b ldr r3, [r7, #4]
800390c: 681b ldr r3, [r3, #0]
800390e: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
8003912: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8003914: 687b ldr r3, [r7, #4]
8003916: 681b ldr r3, [r3, #0]
8003918: 689a ldr r2, [r3, #8]
800391a: 687b ldr r3, [r7, #4]
800391c: 681b ldr r3, [r3, #0]
800391e: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8003922: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8003924: 687b ldr r3, [r7, #4]
8003926: 68db ldr r3, [r3, #12]
8003928: 2b01 cmp r3, #1
800392a: d107 bne.n 800393c <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
800392c: 687b ldr r3, [r7, #4]
800392e: 689a ldr r2, [r3, #8]
8003930: 687b ldr r3, [r7, #4]
8003932: 681b ldr r3, [r3, #0]
8003934: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8003938: 609a str r2, [r3, #8]
800393a: e006 b.n 800394a <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
800393c: 687b ldr r3, [r7, #4]
800393e: 689a ldr r2, [r3, #8]
8003940: 687b ldr r3, [r7, #4]
8003942: 681b ldr r3, [r3, #0]
8003944: f442 4204 orr.w r2, r2, #33792 @ 0x8400
8003948: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
800394a: 687b ldr r3, [r7, #4]
800394c: 68db ldr r3, [r3, #12]
800394e: 2b02 cmp r3, #2
8003950: d108 bne.n 8003964 <HAL_I2C_Init+0xa2>
{
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8003952: 687b ldr r3, [r7, #4]
8003954: 681b ldr r3, [r3, #0]
8003956: 685a ldr r2, [r3, #4]
8003958: 687b ldr r3, [r7, #4]
800395a: 681b ldr r3, [r3, #0]
800395c: f442 6200 orr.w r2, r2, #2048 @ 0x800
8003960: 605a str r2, [r3, #4]
8003962: e007 b.n 8003974 <HAL_I2C_Init+0xb2>
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8003964: 687b ldr r3, [r7, #4]
8003966: 681b ldr r3, [r3, #0]
8003968: 685a ldr r2, [r3, #4]
800396a: 687b ldr r3, [r7, #4]
800396c: 681b ldr r3, [r3, #0]
800396e: f422 6200 bic.w r2, r2, #2048 @ 0x800
8003972: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8003974: 687b ldr r3, [r7, #4]
8003976: 681b ldr r3, [r3, #0]
8003978: 685b ldr r3, [r3, #4]
800397a: 687a ldr r2, [r7, #4]
800397c: 6812 ldr r2, [r2, #0]
800397e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8003982: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8003986: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8003988: 687b ldr r3, [r7, #4]
800398a: 681b ldr r3, [r3, #0]
800398c: 68da ldr r2, [r3, #12]
800398e: 687b ldr r3, [r7, #4]
8003990: 681b ldr r3, [r3, #0]
8003992: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8003996: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8003998: 687b ldr r3, [r7, #4]
800399a: 691a ldr r2, [r3, #16]
800399c: 687b ldr r3, [r7, #4]
800399e: 695b ldr r3, [r3, #20]
80039a0: ea42 0103 orr.w r1, r2, r3
(hi2c->Init.OwnAddress2Masks << 8));
80039a4: 687b ldr r3, [r7, #4]
80039a6: 699b ldr r3, [r3, #24]
80039a8: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
80039aa: 687b ldr r3, [r7, #4]
80039ac: 681b ldr r3, [r3, #0]
80039ae: 430a orrs r2, r1
80039b0: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
80039b2: 687b ldr r3, [r7, #4]
80039b4: 69d9 ldr r1, [r3, #28]
80039b6: 687b ldr r3, [r7, #4]
80039b8: 6a1a ldr r2, [r3, #32]
80039ba: 687b ldr r3, [r7, #4]
80039bc: 681b ldr r3, [r3, #0]
80039be: 430a orrs r2, r1
80039c0: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
80039c2: 687b ldr r3, [r7, #4]
80039c4: 681b ldr r3, [r3, #0]
80039c6: 681a ldr r2, [r3, #0]
80039c8: 687b ldr r3, [r7, #4]
80039ca: 681b ldr r3, [r3, #0]
80039cc: f042 0201 orr.w r2, r2, #1
80039d0: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80039d2: 687b ldr r3, [r7, #4]
80039d4: 2200 movs r2, #0
80039d6: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
80039d8: 687b ldr r3, [r7, #4]
80039da: 2220 movs r2, #32
80039dc: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
80039e0: 687b ldr r3, [r7, #4]
80039e2: 2200 movs r2, #0
80039e4: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80039e6: 687b ldr r3, [r7, #4]
80039e8: 2200 movs r2, #0
80039ea: f883 2042 strb.w r2, [r3, #66] @ 0x42
return HAL_OK;
80039ee: 2300 movs r3, #0
}
80039f0: 4618 mov r0, r3
80039f2: 3708 adds r7, #8
80039f4: 46bd mov sp, r7
80039f6: bd80 pop {r7, pc}
080039f8 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
80039f8: b480 push {r7}
80039fa: b083 sub sp, #12
80039fc: af00 add r7, sp, #0
80039fe: 6078 str r0, [r7, #4]
8003a00: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8003a02: 687b ldr r3, [r7, #4]
8003a04: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8003a08: b2db uxtb r3, r3
8003a0a: 2b20 cmp r3, #32
8003a0c: d138 bne.n 8003a80 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8003a0e: 687b ldr r3, [r7, #4]
8003a10: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8003a14: 2b01 cmp r3, #1
8003a16: d101 bne.n 8003a1c <HAL_I2CEx_ConfigAnalogFilter+0x24>
8003a18: 2302 movs r3, #2
8003a1a: e032 b.n 8003a82 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
8003a1c: 687b ldr r3, [r7, #4]
8003a1e: 2201 movs r2, #1
8003a20: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8003a24: 687b ldr r3, [r7, #4]
8003a26: 2224 movs r2, #36 @ 0x24
8003a28: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003a2c: 687b ldr r3, [r7, #4]
8003a2e: 681b ldr r3, [r3, #0]
8003a30: 681a ldr r2, [r3, #0]
8003a32: 687b ldr r3, [r7, #4]
8003a34: 681b ldr r3, [r3, #0]
8003a36: f022 0201 bic.w r2, r2, #1
8003a3a: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8003a3c: 687b ldr r3, [r7, #4]
8003a3e: 681b ldr r3, [r3, #0]
8003a40: 681a ldr r2, [r3, #0]
8003a42: 687b ldr r3, [r7, #4]
8003a44: 681b ldr r3, [r3, #0]
8003a46: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8003a4a: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
8003a4c: 687b ldr r3, [r7, #4]
8003a4e: 681b ldr r3, [r3, #0]
8003a50: 6819 ldr r1, [r3, #0]
8003a52: 687b ldr r3, [r7, #4]
8003a54: 681b ldr r3, [r3, #0]
8003a56: 683a ldr r2, [r7, #0]
8003a58: 430a orrs r2, r1
8003a5a: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8003a5c: 687b ldr r3, [r7, #4]
8003a5e: 681b ldr r3, [r3, #0]
8003a60: 681a ldr r2, [r3, #0]
8003a62: 687b ldr r3, [r7, #4]
8003a64: 681b ldr r3, [r3, #0]
8003a66: f042 0201 orr.w r2, r2, #1
8003a6a: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8003a6c: 687b ldr r3, [r7, #4]
8003a6e: 2220 movs r2, #32
8003a70: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8003a74: 687b ldr r3, [r7, #4]
8003a76: 2200 movs r2, #0
8003a78: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8003a7c: 2300 movs r3, #0
8003a7e: e000 b.n 8003a82 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8003a80: 2302 movs r3, #2
}
}
8003a82: 4618 mov r0, r3
8003a84: 370c adds r7, #12
8003a86: 46bd mov sp, r7
8003a88: f85d 7b04 ldr.w r7, [sp], #4
8003a8c: 4770 bx lr
08003a8e <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
8003a8e: b480 push {r7}
8003a90: b085 sub sp, #20
8003a92: af00 add r7, sp, #0
8003a94: 6078 str r0, [r7, #4]
8003a96: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8003a98: 687b ldr r3, [r7, #4]
8003a9a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8003a9e: b2db uxtb r3, r3
8003aa0: 2b20 cmp r3, #32
8003aa2: d139 bne.n 8003b18 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8003aa4: 687b ldr r3, [r7, #4]
8003aa6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8003aaa: 2b01 cmp r3, #1
8003aac: d101 bne.n 8003ab2 <HAL_I2CEx_ConfigDigitalFilter+0x24>
8003aae: 2302 movs r3, #2
8003ab0: e033 b.n 8003b1a <HAL_I2CEx_ConfigDigitalFilter+0x8c>
8003ab2: 687b ldr r3, [r7, #4]
8003ab4: 2201 movs r2, #1
8003ab6: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8003aba: 687b ldr r3, [r7, #4]
8003abc: 2224 movs r2, #36 @ 0x24
8003abe: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003ac2: 687b ldr r3, [r7, #4]
8003ac4: 681b ldr r3, [r3, #0]
8003ac6: 681a ldr r2, [r3, #0]
8003ac8: 687b ldr r3, [r7, #4]
8003aca: 681b ldr r3, [r3, #0]
8003acc: f022 0201 bic.w r2, r2, #1
8003ad0: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
8003ad2: 687b ldr r3, [r7, #4]
8003ad4: 681b ldr r3, [r3, #0]
8003ad6: 681b ldr r3, [r3, #0]
8003ad8: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
8003ada: 68fb ldr r3, [r7, #12]
8003adc: f423 6370 bic.w r3, r3, #3840 @ 0xf00
8003ae0: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
8003ae2: 683b ldr r3, [r7, #0]
8003ae4: 021b lsls r3, r3, #8
8003ae6: 68fa ldr r2, [r7, #12]
8003ae8: 4313 orrs r3, r2
8003aea: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
8003aec: 687b ldr r3, [r7, #4]
8003aee: 681b ldr r3, [r3, #0]
8003af0: 68fa ldr r2, [r7, #12]
8003af2: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8003af4: 687b ldr r3, [r7, #4]
8003af6: 681b ldr r3, [r3, #0]
8003af8: 681a ldr r2, [r3, #0]
8003afa: 687b ldr r3, [r7, #4]
8003afc: 681b ldr r3, [r3, #0]
8003afe: f042 0201 orr.w r2, r2, #1
8003b02: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8003b04: 687b ldr r3, [r7, #4]
8003b06: 2220 movs r2, #32
8003b08: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8003b0c: 687b ldr r3, [r7, #4]
8003b0e: 2200 movs r2, #0
8003b10: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8003b14: 2300 movs r3, #0
8003b16: e000 b.n 8003b1a <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
8003b18: 2302 movs r3, #2
}
}
8003b1a: 4618 mov r0, r3
8003b1c: 3714 adds r7, #20
8003b1e: 46bd mov sp, r7
8003b20: f85d 7b04 ldr.w r7, [sp], #4
8003b24: 4770 bx lr
08003b26 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
8003b26: b580 push {r7, lr}
8003b28: b086 sub sp, #24
8003b2a: af02 add r7, sp, #8
8003b2c: 6078 str r0, [r7, #4]
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
8003b2e: 687b ldr r3, [r7, #4]
8003b30: 2b00 cmp r3, #0
8003b32: d101 bne.n 8003b38 <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8003b34: 2301 movs r3, #1
8003b36: e101 b.n 8003d3c <HAL_PCD_Init+0x216>
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
8003b38: 687b ldr r3, [r7, #4]
8003b3a: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
8003b3e: b2db uxtb r3, r3
8003b40: 2b00 cmp r3, #0
8003b42: d106 bne.n 8003b52 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8003b44: 687b ldr r3, [r7, #4]
8003b46: 2200 movs r2, #0
8003b48: f883 2494 strb.w r2, [r3, #1172] @ 0x494
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
8003b4c: 6878 ldr r0, [r7, #4]
8003b4e: f007 fa71 bl 800b034 <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8003b52: 687b ldr r3, [r7, #4]
8003b54: 2203 movs r2, #3
8003b56: f883 2495 strb.w r2, [r3, #1173] @ 0x495
/* Disable DMA mode for FS instance */
hpcd->Init.dma_enable = 0U;
8003b5a: 687b ldr r3, [r7, #4]
8003b5c: 2200 movs r2, #0
8003b5e: 719a strb r2, [r3, #6]
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
8003b60: 687b ldr r3, [r7, #4]
8003b62: 681b ldr r3, [r3, #0]
8003b64: 4618 mov r0, r3
8003b66: f004 fb24 bl 80081b2 <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8003b6a: 687b ldr r3, [r7, #4]
8003b6c: 6818 ldr r0, [r3, #0]
8003b6e: 687b ldr r3, [r7, #4]
8003b70: 7c1a ldrb r2, [r3, #16]
8003b72: f88d 2000 strb.w r2, [sp]
8003b76: 3304 adds r3, #4
8003b78: cb0e ldmia r3, {r1, r2, r3}
8003b7a: f004 fa40 bl 8007ffe <USB_CoreInit>
8003b7e: 4603 mov r3, r0
8003b80: 2b00 cmp r3, #0
8003b82: d005 beq.n 8003b90 <HAL_PCD_Init+0x6a>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8003b84: 687b ldr r3, [r7, #4]
8003b86: 2202 movs r2, #2
8003b88: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
8003b8c: 2301 movs r3, #1
8003b8e: e0d5 b.n 8003d3c <HAL_PCD_Init+0x216>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
8003b90: 687b ldr r3, [r7, #4]
8003b92: 681b ldr r3, [r3, #0]
8003b94: 2100 movs r1, #0
8003b96: 4618 mov r0, r3
8003b98: f004 fb1c bl 80081d4 <USB_SetCurrentMode>
8003b9c: 4603 mov r3, r0
8003b9e: 2b00 cmp r3, #0
8003ba0: d005 beq.n 8003bae <HAL_PCD_Init+0x88>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8003ba2: 687b ldr r3, [r7, #4]
8003ba4: 2202 movs r2, #2
8003ba6: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
8003baa: 2301 movs r3, #1
8003bac: e0c6 b.n 8003d3c <HAL_PCD_Init+0x216>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8003bae: 2300 movs r3, #0
8003bb0: 73fb strb r3, [r7, #15]
8003bb2: e04a b.n 8003c4a <HAL_PCD_Init+0x124>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
8003bb4: 7bfa ldrb r2, [r7, #15]
8003bb6: 6879 ldr r1, [r7, #4]
8003bb8: 4613 mov r3, r2
8003bba: 00db lsls r3, r3, #3
8003bbc: 4413 add r3, r2
8003bbe: 009b lsls r3, r3, #2
8003bc0: 440b add r3, r1
8003bc2: 3315 adds r3, #21
8003bc4: 2201 movs r2, #1
8003bc6: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
8003bc8: 7bfa ldrb r2, [r7, #15]
8003bca: 6879 ldr r1, [r7, #4]
8003bcc: 4613 mov r3, r2
8003bce: 00db lsls r3, r3, #3
8003bd0: 4413 add r3, r2
8003bd2: 009b lsls r3, r3, #2
8003bd4: 440b add r3, r1
8003bd6: 3314 adds r3, #20
8003bd8: 7bfa ldrb r2, [r7, #15]
8003bda: 701a strb r2, [r3, #0]
#if defined (USB_OTG_FS)
hpcd->IN_ep[i].tx_fifo_num = i;
8003bdc: 7bfa ldrb r2, [r7, #15]
8003bde: 7bfb ldrb r3, [r7, #15]
8003be0: b298 uxth r0, r3
8003be2: 6879 ldr r1, [r7, #4]
8003be4: 4613 mov r3, r2
8003be6: 00db lsls r3, r3, #3
8003be8: 4413 add r3, r2
8003bea: 009b lsls r3, r3, #2
8003bec: 440b add r3, r1
8003bee: 332e adds r3, #46 @ 0x2e
8003bf0: 4602 mov r2, r0
8003bf2: 801a strh r2, [r3, #0]
#endif /* defined (USB_OTG_FS) */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8003bf4: 7bfa ldrb r2, [r7, #15]
8003bf6: 6879 ldr r1, [r7, #4]
8003bf8: 4613 mov r3, r2
8003bfa: 00db lsls r3, r3, #3
8003bfc: 4413 add r3, r2
8003bfe: 009b lsls r3, r3, #2
8003c00: 440b add r3, r1
8003c02: 3318 adds r3, #24
8003c04: 2200 movs r2, #0
8003c06: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
8003c08: 7bfa ldrb r2, [r7, #15]
8003c0a: 6879 ldr r1, [r7, #4]
8003c0c: 4613 mov r3, r2
8003c0e: 00db lsls r3, r3, #3
8003c10: 4413 add r3, r2
8003c12: 009b lsls r3, r3, #2
8003c14: 440b add r3, r1
8003c16: 331c adds r3, #28
8003c18: 2200 movs r2, #0
8003c1a: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
8003c1c: 7bfa ldrb r2, [r7, #15]
8003c1e: 6879 ldr r1, [r7, #4]
8003c20: 4613 mov r3, r2
8003c22: 00db lsls r3, r3, #3
8003c24: 4413 add r3, r2
8003c26: 009b lsls r3, r3, #2
8003c28: 440b add r3, r1
8003c2a: 3320 adds r3, #32
8003c2c: 2200 movs r2, #0
8003c2e: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8003c30: 7bfa ldrb r2, [r7, #15]
8003c32: 6879 ldr r1, [r7, #4]
8003c34: 4613 mov r3, r2
8003c36: 00db lsls r3, r3, #3
8003c38: 4413 add r3, r2
8003c3a: 009b lsls r3, r3, #2
8003c3c: 440b add r3, r1
8003c3e: 3324 adds r3, #36 @ 0x24
8003c40: 2200 movs r2, #0
8003c42: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8003c44: 7bfb ldrb r3, [r7, #15]
8003c46: 3301 adds r3, #1
8003c48: 73fb strb r3, [r7, #15]
8003c4a: 687b ldr r3, [r7, #4]
8003c4c: 791b ldrb r3, [r3, #4]
8003c4e: 7bfa ldrb r2, [r7, #15]
8003c50: 429a cmp r2, r3
8003c52: d3af bcc.n 8003bb4 <HAL_PCD_Init+0x8e>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8003c54: 2300 movs r3, #0
8003c56: 73fb strb r3, [r7, #15]
8003c58: e044 b.n 8003ce4 <HAL_PCD_Init+0x1be>
{
hpcd->OUT_ep[i].is_in = 0U;
8003c5a: 7bfa ldrb r2, [r7, #15]
8003c5c: 6879 ldr r1, [r7, #4]
8003c5e: 4613 mov r3, r2
8003c60: 00db lsls r3, r3, #3
8003c62: 4413 add r3, r2
8003c64: 009b lsls r3, r3, #2
8003c66: 440b add r3, r1
8003c68: f203 2355 addw r3, r3, #597 @ 0x255
8003c6c: 2200 movs r2, #0
8003c6e: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8003c70: 7bfa ldrb r2, [r7, #15]
8003c72: 6879 ldr r1, [r7, #4]
8003c74: 4613 mov r3, r2
8003c76: 00db lsls r3, r3, #3
8003c78: 4413 add r3, r2
8003c7a: 009b lsls r3, r3, #2
8003c7c: 440b add r3, r1
8003c7e: f503 7315 add.w r3, r3, #596 @ 0x254
8003c82: 7bfa ldrb r2, [r7, #15]
8003c84: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8003c86: 7bfa ldrb r2, [r7, #15]
8003c88: 6879 ldr r1, [r7, #4]
8003c8a: 4613 mov r3, r2
8003c8c: 00db lsls r3, r3, #3
8003c8e: 4413 add r3, r2
8003c90: 009b lsls r3, r3, #2
8003c92: 440b add r3, r1
8003c94: f503 7316 add.w r3, r3, #600 @ 0x258
8003c98: 2200 movs r2, #0
8003c9a: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
8003c9c: 7bfa ldrb r2, [r7, #15]
8003c9e: 6879 ldr r1, [r7, #4]
8003ca0: 4613 mov r3, r2
8003ca2: 00db lsls r3, r3, #3
8003ca4: 4413 add r3, r2
8003ca6: 009b lsls r3, r3, #2
8003ca8: 440b add r3, r1
8003caa: f503 7317 add.w r3, r3, #604 @ 0x25c
8003cae: 2200 movs r2, #0
8003cb0: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8003cb2: 7bfa ldrb r2, [r7, #15]
8003cb4: 6879 ldr r1, [r7, #4]
8003cb6: 4613 mov r3, r2
8003cb8: 00db lsls r3, r3, #3
8003cba: 4413 add r3, r2
8003cbc: 009b lsls r3, r3, #2
8003cbe: 440b add r3, r1
8003cc0: f503 7318 add.w r3, r3, #608 @ 0x260
8003cc4: 2200 movs r2, #0
8003cc6: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8003cc8: 7bfa ldrb r2, [r7, #15]
8003cca: 6879 ldr r1, [r7, #4]
8003ccc: 4613 mov r3, r2
8003cce: 00db lsls r3, r3, #3
8003cd0: 4413 add r3, r2
8003cd2: 009b lsls r3, r3, #2
8003cd4: 440b add r3, r1
8003cd6: f503 7319 add.w r3, r3, #612 @ 0x264
8003cda: 2200 movs r2, #0
8003cdc: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8003cde: 7bfb ldrb r3, [r7, #15]
8003ce0: 3301 adds r3, #1
8003ce2: 73fb strb r3, [r7, #15]
8003ce4: 687b ldr r3, [r7, #4]
8003ce6: 791b ldrb r3, [r3, #4]
8003ce8: 7bfa ldrb r2, [r7, #15]
8003cea: 429a cmp r2, r3
8003cec: d3b5 bcc.n 8003c5a <HAL_PCD_Init+0x134>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8003cee: 687b ldr r3, [r7, #4]
8003cf0: 6818 ldr r0, [r3, #0]
8003cf2: 687b ldr r3, [r7, #4]
8003cf4: 7c1a ldrb r2, [r3, #16]
8003cf6: f88d 2000 strb.w r2, [sp]
8003cfa: 3304 adds r3, #4
8003cfc: cb0e ldmia r3, {r1, r2, r3}
8003cfe: f004 fab5 bl 800826c <USB_DevInit>
8003d02: 4603 mov r3, r0
8003d04: 2b00 cmp r3, #0
8003d06: d005 beq.n 8003d14 <HAL_PCD_Init+0x1ee>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8003d08: 687b ldr r3, [r7, #4]
8003d0a: 2202 movs r2, #2
8003d0c: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
8003d10: 2301 movs r3, #1
8003d12: e013 b.n 8003d3c <HAL_PCD_Init+0x216>
}
hpcd->USB_Address = 0U;
8003d14: 687b ldr r3, [r7, #4]
8003d16: 2200 movs r2, #0
8003d18: 745a strb r2, [r3, #17]
hpcd->State = HAL_PCD_STATE_READY;
8003d1a: 687b ldr r3, [r7, #4]
8003d1c: 2201 movs r2, #1
8003d1e: f883 2495 strb.w r2, [r3, #1173] @ 0x495
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
8003d22: 687b ldr r3, [r7, #4]
8003d24: 7b1b ldrb r3, [r3, #12]
8003d26: 2b01 cmp r3, #1
8003d28: d102 bne.n 8003d30 <HAL_PCD_Init+0x20a>
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
8003d2a: 6878 ldr r0, [r7, #4]
8003d2c: f001 f856 bl 8004ddc <HAL_PCDEx_ActivateLPM>
}
(void)USB_DevDisconnect(hpcd->Instance);
8003d30: 687b ldr r3, [r7, #4]
8003d32: 681b ldr r3, [r3, #0]
8003d34: 4618 mov r0, r3
8003d36: f005 fa6c bl 8009212 <USB_DevDisconnect>
return HAL_OK;
8003d3a: 2300 movs r3, #0
}
8003d3c: 4618 mov r0, r3
8003d3e: 3710 adds r7, #16
8003d40: 46bd mov sp, r7
8003d42: bd80 pop {r7, pc}
08003d44 <HAL_PCD_Start>:
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
8003d44: b580 push {r7, lr}
8003d46: b084 sub sp, #16
8003d48: af00 add r7, sp, #0
8003d4a: 6078 str r0, [r7, #4]
#if defined (USB_OTG_FS)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8003d4c: 687b ldr r3, [r7, #4]
8003d4e: 681b ldr r3, [r3, #0]
8003d50: 60fb str r3, [r7, #12]
#endif /* defined (USB_OTG_FS) */
__HAL_LOCK(hpcd);
8003d52: 687b ldr r3, [r7, #4]
8003d54: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
8003d58: 2b01 cmp r3, #1
8003d5a: d101 bne.n 8003d60 <HAL_PCD_Start+0x1c>
8003d5c: 2302 movs r3, #2
8003d5e: e01c b.n 8003d9a <HAL_PCD_Start+0x56>
8003d60: 687b ldr r3, [r7, #4]
8003d62: 2201 movs r2, #1
8003d64: f883 2494 strb.w r2, [r3, #1172] @ 0x494
#if defined (USB_OTG_FS)
if (hpcd->Init.battery_charging_enable == 1U)
8003d68: 687b ldr r3, [r7, #4]
8003d6a: 7b5b ldrb r3, [r3, #13]
8003d6c: 2b01 cmp r3, #1
8003d6e: d105 bne.n 8003d7c <HAL_PCD_Start+0x38>
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
8003d70: 68fb ldr r3, [r7, #12]
8003d72: 6b9b ldr r3, [r3, #56] @ 0x38
8003d74: f443 3280 orr.w r2, r3, #65536 @ 0x10000
8003d78: 68fb ldr r3, [r7, #12]
8003d7a: 639a str r2, [r3, #56] @ 0x38
}
#endif /* defined (USB_OTG_FS) */
__HAL_PCD_ENABLE(hpcd);
8003d7c: 687b ldr r3, [r7, #4]
8003d7e: 681b ldr r3, [r3, #0]
8003d80: 4618 mov r0, r3
8003d82: f004 fa05 bl 8008190 <USB_EnableGlobalInt>
(void)USB_DevConnect(hpcd->Instance);
8003d86: 687b ldr r3, [r7, #4]
8003d88: 681b ldr r3, [r3, #0]
8003d8a: 4618 mov r0, r3
8003d8c: f005 fa20 bl 80091d0 <USB_DevConnect>
__HAL_UNLOCK(hpcd);
8003d90: 687b ldr r3, [r7, #4]
8003d92: 2200 movs r2, #0
8003d94: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
8003d98: 2300 movs r3, #0
}
8003d9a: 4618 mov r0, r3
8003d9c: 3710 adds r7, #16
8003d9e: 46bd mov sp, r7
8003da0: bd80 pop {r7, pc}
08003da2 <HAL_PCD_IRQHandler>:
* @brief Handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
8003da2: b590 push {r4, r7, lr}
8003da4: b08d sub sp, #52 @ 0x34
8003da6: af00 add r7, sp, #0
8003da8: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8003daa: 687b ldr r3, [r7, #4]
8003dac: 681b ldr r3, [r3, #0]
8003dae: 623b str r3, [r7, #32]
uint32_t USBx_BASE = (uint32_t)USBx;
8003db0: 6a3b ldr r3, [r7, #32]
8003db2: 61fb str r3, [r7, #28]
uint32_t epnum;
uint32_t fifoemptymsk;
uint32_t RegVal;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
8003db4: 687b ldr r3, [r7, #4]
8003db6: 681b ldr r3, [r3, #0]
8003db8: 4618 mov r0, r3
8003dba: f005 fade bl 800937a <USB_GetMode>
8003dbe: 4603 mov r3, r0
8003dc0: 2b00 cmp r3, #0
8003dc2: f040 8481 bne.w 80046c8 <HAL_PCD_IRQHandler+0x926>
{
/* avoid spurious interrupt */
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
8003dc6: 687b ldr r3, [r7, #4]
8003dc8: 681b ldr r3, [r3, #0]
8003dca: 4618 mov r0, r3
8003dcc: f005 fa42 bl 8009254 <USB_ReadInterrupts>
8003dd0: 4603 mov r3, r0
8003dd2: 2b00 cmp r3, #0
8003dd4: f000 8477 beq.w 80046c6 <HAL_PCD_IRQHandler+0x924>
{
return;
}
/* store current frame number */
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
8003dd8: 69fb ldr r3, [r7, #28]
8003dda: f503 6300 add.w r3, r3, #2048 @ 0x800
8003dde: 689b ldr r3, [r3, #8]
8003de0: 0a1b lsrs r3, r3, #8
8003de2: f3c3 020d ubfx r2, r3, #0, #14
8003de6: 687b ldr r3, [r7, #4]
8003de8: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
8003dec: 687b ldr r3, [r7, #4]
8003dee: 681b ldr r3, [r3, #0]
8003df0: 4618 mov r0, r3
8003df2: f005 fa2f bl 8009254 <USB_ReadInterrupts>
8003df6: 4603 mov r3, r0
8003df8: f003 0302 and.w r3, r3, #2
8003dfc: 2b02 cmp r3, #2
8003dfe: d107 bne.n 8003e10 <HAL_PCD_IRQHandler+0x6e>
{
/* incorrect mode, acknowledge the interrupt */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
8003e00: 687b ldr r3, [r7, #4]
8003e02: 681b ldr r3, [r3, #0]
8003e04: 695a ldr r2, [r3, #20]
8003e06: 687b ldr r3, [r7, #4]
8003e08: 681b ldr r3, [r3, #0]
8003e0a: f002 0202 and.w r2, r2, #2
8003e0e: 615a str r2, [r3, #20]
}
/* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
8003e10: 687b ldr r3, [r7, #4]
8003e12: 681b ldr r3, [r3, #0]
8003e14: 4618 mov r0, r3
8003e16: f005 fa1d bl 8009254 <USB_ReadInterrupts>
8003e1a: 4603 mov r3, r0
8003e1c: f003 0310 and.w r3, r3, #16
8003e20: 2b10 cmp r3, #16
8003e22: d161 bne.n 8003ee8 <HAL_PCD_IRQHandler+0x146>
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
8003e24: 687b ldr r3, [r7, #4]
8003e26: 681b ldr r3, [r3, #0]
8003e28: 699a ldr r2, [r3, #24]
8003e2a: 687b ldr r3, [r7, #4]
8003e2c: 681b ldr r3, [r3, #0]
8003e2e: f022 0210 bic.w r2, r2, #16
8003e32: 619a str r2, [r3, #24]
RegVal = USBx->GRXSTSP;
8003e34: 6a3b ldr r3, [r7, #32]
8003e36: 6a1b ldr r3, [r3, #32]
8003e38: 61bb str r3, [r7, #24]
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
8003e3a: 69bb ldr r3, [r7, #24]
8003e3c: f003 020f and.w r2, r3, #15
8003e40: 4613 mov r3, r2
8003e42: 00db lsls r3, r3, #3
8003e44: 4413 add r3, r2
8003e46: 009b lsls r3, r3, #2
8003e48: f503 7314 add.w r3, r3, #592 @ 0x250
8003e4c: 687a ldr r2, [r7, #4]
8003e4e: 4413 add r3, r2
8003e50: 3304 adds r3, #4
8003e52: 617b str r3, [r7, #20]
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
8003e54: 69bb ldr r3, [r7, #24]
8003e56: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
8003e5a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8003e5e: d124 bne.n 8003eaa <HAL_PCD_IRQHandler+0x108>
{
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
8003e60: 69ba ldr r2, [r7, #24]
8003e62: f647 73f0 movw r3, #32752 @ 0x7ff0
8003e66: 4013 ands r3, r2
8003e68: 2b00 cmp r3, #0
8003e6a: d035 beq.n 8003ed8 <HAL_PCD_IRQHandler+0x136>
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
8003e6c: 697b ldr r3, [r7, #20]
8003e6e: 68d9 ldr r1, [r3, #12]
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
8003e70: 69bb ldr r3, [r7, #24]
8003e72: 091b lsrs r3, r3, #4
8003e74: b29b uxth r3, r3
(void)USB_ReadPacket(USBx, ep->xfer_buff,
8003e76: f3c3 030a ubfx r3, r3, #0, #11
8003e7a: b29b uxth r3, r3
8003e7c: 461a mov r2, r3
8003e7e: 6a38 ldr r0, [r7, #32]
8003e80: f005 f854 bl 8008f2c <USB_ReadPacket>
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
8003e84: 697b ldr r3, [r7, #20]
8003e86: 68da ldr r2, [r3, #12]
8003e88: 69bb ldr r3, [r7, #24]
8003e8a: 091b lsrs r3, r3, #4
8003e8c: f3c3 030a ubfx r3, r3, #0, #11
8003e90: 441a add r2, r3
8003e92: 697b ldr r3, [r7, #20]
8003e94: 60da str r2, [r3, #12]
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
8003e96: 697b ldr r3, [r7, #20]
8003e98: 695a ldr r2, [r3, #20]
8003e9a: 69bb ldr r3, [r7, #24]
8003e9c: 091b lsrs r3, r3, #4
8003e9e: f3c3 030a ubfx r3, r3, #0, #11
8003ea2: 441a add r2, r3
8003ea4: 697b ldr r3, [r7, #20]
8003ea6: 615a str r2, [r3, #20]
8003ea8: e016 b.n 8003ed8 <HAL_PCD_IRQHandler+0x136>
}
}
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
8003eaa: 69bb ldr r3, [r7, #24]
8003eac: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
8003eb0: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
8003eb4: d110 bne.n 8003ed8 <HAL_PCD_IRQHandler+0x136>
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
8003eb6: 687b ldr r3, [r7, #4]
8003eb8: f203 439c addw r3, r3, #1180 @ 0x49c
8003ebc: 2208 movs r2, #8
8003ebe: 4619 mov r1, r3
8003ec0: 6a38 ldr r0, [r7, #32]
8003ec2: f005 f833 bl 8008f2c <USB_ReadPacket>
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
8003ec6: 697b ldr r3, [r7, #20]
8003ec8: 695a ldr r2, [r3, #20]
8003eca: 69bb ldr r3, [r7, #24]
8003ecc: 091b lsrs r3, r3, #4
8003ece: f3c3 030a ubfx r3, r3, #0, #11
8003ed2: 441a add r2, r3
8003ed4: 697b ldr r3, [r7, #20]
8003ed6: 615a str r2, [r3, #20]
else
{
/* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
8003ed8: 687b ldr r3, [r7, #4]
8003eda: 681b ldr r3, [r3, #0]
8003edc: 699a ldr r2, [r3, #24]
8003ede: 687b ldr r3, [r7, #4]
8003ee0: 681b ldr r3, [r3, #0]
8003ee2: f042 0210 orr.w r2, r2, #16
8003ee6: 619a str r2, [r3, #24]
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
8003ee8: 687b ldr r3, [r7, #4]
8003eea: 681b ldr r3, [r3, #0]
8003eec: 4618 mov r0, r3
8003eee: f005 f9b1 bl 8009254 <USB_ReadInterrupts>
8003ef2: 4603 mov r3, r0
8003ef4: f403 2300 and.w r3, r3, #524288 @ 0x80000
8003ef8: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
8003efc: f040 80a7 bne.w 800404e <HAL_PCD_IRQHandler+0x2ac>
{
epnum = 0U;
8003f00: 2300 movs r3, #0
8003f02: 627b str r3, [r7, #36] @ 0x24
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
8003f04: 687b ldr r3, [r7, #4]
8003f06: 681b ldr r3, [r3, #0]
8003f08: 4618 mov r0, r3
8003f0a: f005 f9b6 bl 800927a <USB_ReadDevAllOutEpInterrupt>
8003f0e: 62b8 str r0, [r7, #40] @ 0x28
while (ep_intr != 0U)
8003f10: e099 b.n 8004046 <HAL_PCD_IRQHandler+0x2a4>
{
if ((ep_intr & 0x1U) != 0U)
8003f12: 6abb ldr r3, [r7, #40] @ 0x28
8003f14: f003 0301 and.w r3, r3, #1
8003f18: 2b00 cmp r3, #0
8003f1a: f000 808e beq.w 800403a <HAL_PCD_IRQHandler+0x298>
{
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
8003f1e: 687b ldr r3, [r7, #4]
8003f20: 681b ldr r3, [r3, #0]
8003f22: 6a7a ldr r2, [r7, #36] @ 0x24
8003f24: b2d2 uxtb r2, r2
8003f26: 4611 mov r1, r2
8003f28: 4618 mov r0, r3
8003f2a: f005 f9da bl 80092e2 <USB_ReadDevOutEPInterrupt>
8003f2e: 6138 str r0, [r7, #16]
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
8003f30: 693b ldr r3, [r7, #16]
8003f32: f003 0301 and.w r3, r3, #1
8003f36: 2b00 cmp r3, #0
8003f38: d00c beq.n 8003f54 <HAL_PCD_IRQHandler+0x1b2>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
8003f3a: 6a7b ldr r3, [r7, #36] @ 0x24
8003f3c: 015a lsls r2, r3, #5
8003f3e: 69fb ldr r3, [r7, #28]
8003f40: 4413 add r3, r2
8003f42: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003f46: 461a mov r2, r3
8003f48: 2301 movs r3, #1
8003f4a: 6093 str r3, [r2, #8]
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
8003f4c: 6a79 ldr r1, [r7, #36] @ 0x24
8003f4e: 6878 ldr r0, [r7, #4]
8003f50: f000 fe6a bl 8004c28 <PCD_EP_OutXfrComplete_int>
}
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
8003f54: 693b ldr r3, [r7, #16]
8003f56: f003 0308 and.w r3, r3, #8
8003f5a: 2b00 cmp r3, #0
8003f5c: d00c beq.n 8003f78 <HAL_PCD_IRQHandler+0x1d6>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
8003f5e: 6a7b ldr r3, [r7, #36] @ 0x24
8003f60: 015a lsls r2, r3, #5
8003f62: 69fb ldr r3, [r7, #28]
8003f64: 4413 add r3, r2
8003f66: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003f6a: 461a mov r2, r3
8003f6c: 2308 movs r3, #8
8003f6e: 6093 str r3, [r2, #8]
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
8003f70: 6a79 ldr r1, [r7, #36] @ 0x24
8003f72: 6878 ldr r0, [r7, #4]
8003f74: f000 fea6 bl 8004cc4 <PCD_EP_OutSetupPacket_int>
}
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
8003f78: 693b ldr r3, [r7, #16]
8003f7a: f003 0310 and.w r3, r3, #16
8003f7e: 2b00 cmp r3, #0
8003f80: d008 beq.n 8003f94 <HAL_PCD_IRQHandler+0x1f2>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
8003f82: 6a7b ldr r3, [r7, #36] @ 0x24
8003f84: 015a lsls r2, r3, #5
8003f86: 69fb ldr r3, [r7, #28]
8003f88: 4413 add r3, r2
8003f8a: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003f8e: 461a mov r2, r3
8003f90: 2310 movs r3, #16
8003f92: 6093 str r3, [r2, #8]
}
/* Clear OUT Endpoint disable interrupt */
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
8003f94: 693b ldr r3, [r7, #16]
8003f96: f003 0302 and.w r3, r3, #2
8003f9a: 2b00 cmp r3, #0
8003f9c: d030 beq.n 8004000 <HAL_PCD_IRQHandler+0x25e>
{
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
8003f9e: 6a3b ldr r3, [r7, #32]
8003fa0: 695b ldr r3, [r3, #20]
8003fa2: f003 0380 and.w r3, r3, #128 @ 0x80
8003fa6: 2b80 cmp r3, #128 @ 0x80
8003fa8: d109 bne.n 8003fbe <HAL_PCD_IRQHandler+0x21c>
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
8003faa: 69fb ldr r3, [r7, #28]
8003fac: f503 6300 add.w r3, r3, #2048 @ 0x800
8003fb0: 685b ldr r3, [r3, #4]
8003fb2: 69fa ldr r2, [r7, #28]
8003fb4: f502 6200 add.w r2, r2, #2048 @ 0x800
8003fb8: f443 6380 orr.w r3, r3, #1024 @ 0x400
8003fbc: 6053 str r3, [r2, #4]
}
ep = &hpcd->OUT_ep[epnum];
8003fbe: 6a7a ldr r2, [r7, #36] @ 0x24
8003fc0: 4613 mov r3, r2
8003fc2: 00db lsls r3, r3, #3
8003fc4: 4413 add r3, r2
8003fc6: 009b lsls r3, r3, #2
8003fc8: f503 7314 add.w r3, r3, #592 @ 0x250
8003fcc: 687a ldr r2, [r7, #4]
8003fce: 4413 add r3, r2
8003fd0: 3304 adds r3, #4
8003fd2: 617b str r3, [r7, #20]
if (ep->is_iso_incomplete == 1U)
8003fd4: 697b ldr r3, [r7, #20]
8003fd6: 78db ldrb r3, [r3, #3]
8003fd8: 2b01 cmp r3, #1
8003fda: d108 bne.n 8003fee <HAL_PCD_IRQHandler+0x24c>
{
ep->is_iso_incomplete = 0U;
8003fdc: 697b ldr r3, [r7, #20]
8003fde: 2200 movs r2, #0
8003fe0: 70da strb r2, [r3, #3]
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
8003fe2: 6a7b ldr r3, [r7, #36] @ 0x24
8003fe4: b2db uxtb r3, r3
8003fe6: 4619 mov r1, r3
8003fe8: 6878 ldr r0, [r7, #4]
8003fea: f007 f959 bl 800b2a0 <HAL_PCD_ISOOUTIncompleteCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
8003fee: 6a7b ldr r3, [r7, #36] @ 0x24
8003ff0: 015a lsls r2, r3, #5
8003ff2: 69fb ldr r3, [r7, #28]
8003ff4: 4413 add r3, r2
8003ff6: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003ffa: 461a mov r2, r3
8003ffc: 2302 movs r3, #2
8003ffe: 6093 str r3, [r2, #8]
}
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
8004000: 693b ldr r3, [r7, #16]
8004002: f003 0320 and.w r3, r3, #32
8004006: 2b00 cmp r3, #0
8004008: d008 beq.n 800401c <HAL_PCD_IRQHandler+0x27a>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
800400a: 6a7b ldr r3, [r7, #36] @ 0x24
800400c: 015a lsls r2, r3, #5
800400e: 69fb ldr r3, [r7, #28]
8004010: 4413 add r3, r2
8004012: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004016: 461a mov r2, r3
8004018: 2320 movs r3, #32
800401a: 6093 str r3, [r2, #8]
}
/* Clear OUT NAK interrupt */
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
800401c: 693b ldr r3, [r7, #16]
800401e: f403 5300 and.w r3, r3, #8192 @ 0x2000
8004022: 2b00 cmp r3, #0
8004024: d009 beq.n 800403a <HAL_PCD_IRQHandler+0x298>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
8004026: 6a7b ldr r3, [r7, #36] @ 0x24
8004028: 015a lsls r2, r3, #5
800402a: 69fb ldr r3, [r7, #28]
800402c: 4413 add r3, r2
800402e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004032: 461a mov r2, r3
8004034: f44f 5300 mov.w r3, #8192 @ 0x2000
8004038: 6093 str r3, [r2, #8]
}
}
epnum++;
800403a: 6a7b ldr r3, [r7, #36] @ 0x24
800403c: 3301 adds r3, #1
800403e: 627b str r3, [r7, #36] @ 0x24
ep_intr >>= 1U;
8004040: 6abb ldr r3, [r7, #40] @ 0x28
8004042: 085b lsrs r3, r3, #1
8004044: 62bb str r3, [r7, #40] @ 0x28
while (ep_intr != 0U)
8004046: 6abb ldr r3, [r7, #40] @ 0x28
8004048: 2b00 cmp r3, #0
800404a: f47f af62 bne.w 8003f12 <HAL_PCD_IRQHandler+0x170>
}
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
800404e: 687b ldr r3, [r7, #4]
8004050: 681b ldr r3, [r3, #0]
8004052: 4618 mov r0, r3
8004054: f005 f8fe bl 8009254 <USB_ReadInterrupts>
8004058: 4603 mov r3, r0
800405a: f403 2380 and.w r3, r3, #262144 @ 0x40000
800405e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8004062: f040 80a4 bne.w 80041ae <HAL_PCD_IRQHandler+0x40c>
{
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
8004066: 687b ldr r3, [r7, #4]
8004068: 681b ldr r3, [r3, #0]
800406a: 4618 mov r0, r3
800406c: f005 f91f bl 80092ae <USB_ReadDevAllInEpInterrupt>
8004070: 62b8 str r0, [r7, #40] @ 0x28
epnum = 0U;
8004072: 2300 movs r3, #0
8004074: 627b str r3, [r7, #36] @ 0x24
while (ep_intr != 0U)
8004076: e096 b.n 80041a6 <HAL_PCD_IRQHandler+0x404>
{
if ((ep_intr & 0x1U) != 0U) /* In ITR */
8004078: 6abb ldr r3, [r7, #40] @ 0x28
800407a: f003 0301 and.w r3, r3, #1
800407e: 2b00 cmp r3, #0
8004080: f000 808b beq.w 800419a <HAL_PCD_IRQHandler+0x3f8>
{
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
8004084: 687b ldr r3, [r7, #4]
8004086: 681b ldr r3, [r3, #0]
8004088: 6a7a ldr r2, [r7, #36] @ 0x24
800408a: b2d2 uxtb r2, r2
800408c: 4611 mov r1, r2
800408e: 4618 mov r0, r3
8004090: f005 f945 bl 800931e <USB_ReadDevInEPInterrupt>
8004094: 6138 str r0, [r7, #16]
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
8004096: 693b ldr r3, [r7, #16]
8004098: f003 0301 and.w r3, r3, #1
800409c: 2b00 cmp r3, #0
800409e: d020 beq.n 80040e2 <HAL_PCD_IRQHandler+0x340>
{
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
80040a0: 6a7b ldr r3, [r7, #36] @ 0x24
80040a2: f003 030f and.w r3, r3, #15
80040a6: 2201 movs r2, #1
80040a8: fa02 f303 lsl.w r3, r2, r3
80040ac: 60fb str r3, [r7, #12]
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
80040ae: 69fb ldr r3, [r7, #28]
80040b0: f503 6300 add.w r3, r3, #2048 @ 0x800
80040b4: 6b5a ldr r2, [r3, #52] @ 0x34
80040b6: 68fb ldr r3, [r7, #12]
80040b8: 43db mvns r3, r3
80040ba: 69f9 ldr r1, [r7, #28]
80040bc: f501 6100 add.w r1, r1, #2048 @ 0x800
80040c0: 4013 ands r3, r2
80040c2: 634b str r3, [r1, #52] @ 0x34
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
80040c4: 6a7b ldr r3, [r7, #36] @ 0x24
80040c6: 015a lsls r2, r3, #5
80040c8: 69fb ldr r3, [r7, #28]
80040ca: 4413 add r3, r2
80040cc: f503 6310 add.w r3, r3, #2304 @ 0x900
80040d0: 461a mov r2, r3
80040d2: 2301 movs r3, #1
80040d4: 6093 str r3, [r2, #8]
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
80040d6: 6a7b ldr r3, [r7, #36] @ 0x24
80040d8: b2db uxtb r3, r3
80040da: 4619 mov r1, r3
80040dc: 6878 ldr r0, [r7, #4]
80040de: f007 f84a bl 800b176 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
80040e2: 693b ldr r3, [r7, #16]
80040e4: f003 0308 and.w r3, r3, #8
80040e8: 2b00 cmp r3, #0
80040ea: d008 beq.n 80040fe <HAL_PCD_IRQHandler+0x35c>
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
80040ec: 6a7b ldr r3, [r7, #36] @ 0x24
80040ee: 015a lsls r2, r3, #5
80040f0: 69fb ldr r3, [r7, #28]
80040f2: 4413 add r3, r2
80040f4: f503 6310 add.w r3, r3, #2304 @ 0x900
80040f8: 461a mov r2, r3
80040fa: 2308 movs r3, #8
80040fc: 6093 str r3, [r2, #8]
}
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
80040fe: 693b ldr r3, [r7, #16]
8004100: f003 0310 and.w r3, r3, #16
8004104: 2b00 cmp r3, #0
8004106: d008 beq.n 800411a <HAL_PCD_IRQHandler+0x378>
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
8004108: 6a7b ldr r3, [r7, #36] @ 0x24
800410a: 015a lsls r2, r3, #5
800410c: 69fb ldr r3, [r7, #28]
800410e: 4413 add r3, r2
8004110: f503 6310 add.w r3, r3, #2304 @ 0x900
8004114: 461a mov r2, r3
8004116: 2310 movs r3, #16
8004118: 6093 str r3, [r2, #8]
}
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
800411a: 693b ldr r3, [r7, #16]
800411c: f003 0340 and.w r3, r3, #64 @ 0x40
8004120: 2b00 cmp r3, #0
8004122: d008 beq.n 8004136 <HAL_PCD_IRQHandler+0x394>
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
8004124: 6a7b ldr r3, [r7, #36] @ 0x24
8004126: 015a lsls r2, r3, #5
8004128: 69fb ldr r3, [r7, #28]
800412a: 4413 add r3, r2
800412c: f503 6310 add.w r3, r3, #2304 @ 0x900
8004130: 461a mov r2, r3
8004132: 2340 movs r3, #64 @ 0x40
8004134: 6093 str r3, [r2, #8]
}
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
8004136: 693b ldr r3, [r7, #16]
8004138: f003 0302 and.w r3, r3, #2
800413c: 2b00 cmp r3, #0
800413e: d023 beq.n 8004188 <HAL_PCD_IRQHandler+0x3e6>
{
(void)USB_FlushTxFifo(USBx, epnum);
8004140: 6a79 ldr r1, [r7, #36] @ 0x24
8004142: 6a38 ldr r0, [r7, #32]
8004144: f004 f9da bl 80084fc <USB_FlushTxFifo>
ep = &hpcd->IN_ep[epnum];
8004148: 6a7a ldr r2, [r7, #36] @ 0x24
800414a: 4613 mov r3, r2
800414c: 00db lsls r3, r3, #3
800414e: 4413 add r3, r2
8004150: 009b lsls r3, r3, #2
8004152: 3310 adds r3, #16
8004154: 687a ldr r2, [r7, #4]
8004156: 4413 add r3, r2
8004158: 3304 adds r3, #4
800415a: 617b str r3, [r7, #20]
if (ep->is_iso_incomplete == 1U)
800415c: 697b ldr r3, [r7, #20]
800415e: 78db ldrb r3, [r3, #3]
8004160: 2b01 cmp r3, #1
8004162: d108 bne.n 8004176 <HAL_PCD_IRQHandler+0x3d4>
{
ep->is_iso_incomplete = 0U;
8004164: 697b ldr r3, [r7, #20]
8004166: 2200 movs r2, #0
8004168: 70da strb r2, [r3, #3]
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
800416a: 6a7b ldr r3, [r7, #36] @ 0x24
800416c: b2db uxtb r3, r3
800416e: 4619 mov r1, r3
8004170: 6878 ldr r0, [r7, #4]
8004172: f007 f8a7 bl 800b2c4 <HAL_PCD_ISOINIncompleteCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
8004176: 6a7b ldr r3, [r7, #36] @ 0x24
8004178: 015a lsls r2, r3, #5
800417a: 69fb ldr r3, [r7, #28]
800417c: 4413 add r3, r2
800417e: f503 6310 add.w r3, r3, #2304 @ 0x900
8004182: 461a mov r2, r3
8004184: 2302 movs r3, #2
8004186: 6093 str r3, [r2, #8]
}
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
8004188: 693b ldr r3, [r7, #16]
800418a: f003 0380 and.w r3, r3, #128 @ 0x80
800418e: 2b00 cmp r3, #0
8004190: d003 beq.n 800419a <HAL_PCD_IRQHandler+0x3f8>
{
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
8004192: 6a79 ldr r1, [r7, #36] @ 0x24
8004194: 6878 ldr r0, [r7, #4]
8004196: f000 fcbe bl 8004b16 <PCD_WriteEmptyTxFifo>
}
}
epnum++;
800419a: 6a7b ldr r3, [r7, #36] @ 0x24
800419c: 3301 adds r3, #1
800419e: 627b str r3, [r7, #36] @ 0x24
ep_intr >>= 1U;
80041a0: 6abb ldr r3, [r7, #40] @ 0x28
80041a2: 085b lsrs r3, r3, #1
80041a4: 62bb str r3, [r7, #40] @ 0x28
while (ep_intr != 0U)
80041a6: 6abb ldr r3, [r7, #40] @ 0x28
80041a8: 2b00 cmp r3, #0
80041aa: f47f af65 bne.w 8004078 <HAL_PCD_IRQHandler+0x2d6>
}
}
/* Handle Resume Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
80041ae: 687b ldr r3, [r7, #4]
80041b0: 681b ldr r3, [r3, #0]
80041b2: 4618 mov r0, r3
80041b4: f005 f84e bl 8009254 <USB_ReadInterrupts>
80041b8: 4603 mov r3, r0
80041ba: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80041be: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80041c2: d122 bne.n 800420a <HAL_PCD_IRQHandler+0x468>
{
/* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
80041c4: 69fb ldr r3, [r7, #28]
80041c6: f503 6300 add.w r3, r3, #2048 @ 0x800
80041ca: 685b ldr r3, [r3, #4]
80041cc: 69fa ldr r2, [r7, #28]
80041ce: f502 6200 add.w r2, r2, #2048 @ 0x800
80041d2: f023 0301 bic.w r3, r3, #1
80041d6: 6053 str r3, [r2, #4]
if (hpcd->LPM_State == LPM_L1)
80041d8: 687b ldr r3, [r7, #4]
80041da: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
80041de: 2b01 cmp r3, #1
80041e0: d108 bne.n 80041f4 <HAL_PCD_IRQHandler+0x452>
{
hpcd->LPM_State = LPM_L0;
80041e2: 687b ldr r3, [r7, #4]
80041e4: 2200 movs r2, #0
80041e6: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
80041ea: 2100 movs r1, #0
80041ec: 6878 ldr r0, [r7, #4]
80041ee: f007 fac7 bl 800b780 <HAL_PCDEx_LPM_Callback>
80041f2: e002 b.n 80041fa <HAL_PCD_IRQHandler+0x458>
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
80041f4: 6878 ldr r0, [r7, #4]
80041f6: f007 f82b bl 800b250 <HAL_PCD_ResumeCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
80041fa: 687b ldr r3, [r7, #4]
80041fc: 681b ldr r3, [r3, #0]
80041fe: 695a ldr r2, [r3, #20]
8004200: 687b ldr r3, [r7, #4]
8004202: 681b ldr r3, [r3, #0]
8004204: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000
8004208: 615a str r2, [r3, #20]
}
/* Handle Suspend Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
800420a: 687b ldr r3, [r7, #4]
800420c: 681b ldr r3, [r3, #0]
800420e: 4618 mov r0, r3
8004210: f005 f820 bl 8009254 <USB_ReadInterrupts>
8004214: 4603 mov r3, r0
8004216: f403 6300 and.w r3, r3, #2048 @ 0x800
800421a: f5b3 6f00 cmp.w r3, #2048 @ 0x800
800421e: d112 bne.n 8004246 <HAL_PCD_IRQHandler+0x4a4>
{
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
8004220: 69fb ldr r3, [r7, #28]
8004222: f503 6300 add.w r3, r3, #2048 @ 0x800
8004226: 689b ldr r3, [r3, #8]
8004228: f003 0301 and.w r3, r3, #1
800422c: 2b01 cmp r3, #1
800422e: d102 bne.n 8004236 <HAL_PCD_IRQHandler+0x494>
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
8004230: 6878 ldr r0, [r7, #4]
8004232: f006 ffe7 bl 800b204 <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
8004236: 687b ldr r3, [r7, #4]
8004238: 681b ldr r3, [r3, #0]
800423a: 695a ldr r2, [r3, #20]
800423c: 687b ldr r3, [r7, #4]
800423e: 681b ldr r3, [r3, #0]
8004240: f402 6200 and.w r2, r2, #2048 @ 0x800
8004244: 615a str r2, [r3, #20]
}
/* Handle LPM Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
8004246: 687b ldr r3, [r7, #4]
8004248: 681b ldr r3, [r3, #0]
800424a: 4618 mov r0, r3
800424c: f005 f802 bl 8009254 <USB_ReadInterrupts>
8004250: 4603 mov r3, r0
8004252: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8004256: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
800425a: d121 bne.n 80042a0 <HAL_PCD_IRQHandler+0x4fe>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
800425c: 687b ldr r3, [r7, #4]
800425e: 681b ldr r3, [r3, #0]
8004260: 695a ldr r2, [r3, #20]
8004262: 687b ldr r3, [r7, #4]
8004264: 681b ldr r3, [r3, #0]
8004266: f002 6200 and.w r2, r2, #134217728 @ 0x8000000
800426a: 615a str r2, [r3, #20]
if (hpcd->LPM_State == LPM_L0)
800426c: 687b ldr r3, [r7, #4]
800426e: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
8004272: 2b00 cmp r3, #0
8004274: d111 bne.n 800429a <HAL_PCD_IRQHandler+0x4f8>
{
hpcd->LPM_State = LPM_L1;
8004276: 687b ldr r3, [r7, #4]
8004278: 2201 movs r2, #1
800427a: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
800427e: 687b ldr r3, [r7, #4]
8004280: 681b ldr r3, [r3, #0]
8004282: 6d5b ldr r3, [r3, #84] @ 0x54
8004284: 089b lsrs r3, r3, #2
8004286: f003 020f and.w r2, r3, #15
800428a: 687b ldr r3, [r7, #4]
800428c: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
8004290: 2101 movs r1, #1
8004292: 6878 ldr r0, [r7, #4]
8004294: f007 fa74 bl 800b780 <HAL_PCDEx_LPM_Callback>
8004298: e002 b.n 80042a0 <HAL_PCD_IRQHandler+0x4fe>
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
800429a: 6878 ldr r0, [r7, #4]
800429c: f006 ffb2 bl 800b204 <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Handle Reset Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
80042a0: 687b ldr r3, [r7, #4]
80042a2: 681b ldr r3, [r3, #0]
80042a4: 4618 mov r0, r3
80042a6: f004 ffd5 bl 8009254 <USB_ReadInterrupts>
80042aa: 4603 mov r3, r0
80042ac: f403 5380 and.w r3, r3, #4096 @ 0x1000
80042b0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80042b4: f040 80b6 bne.w 8004424 <HAL_PCD_IRQHandler+0x682>
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
80042b8: 69fb ldr r3, [r7, #28]
80042ba: f503 6300 add.w r3, r3, #2048 @ 0x800
80042be: 685b ldr r3, [r3, #4]
80042c0: 69fa ldr r2, [r7, #28]
80042c2: f502 6200 add.w r2, r2, #2048 @ 0x800
80042c6: f023 0301 bic.w r3, r3, #1
80042ca: 6053 str r3, [r2, #4]
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
80042cc: 687b ldr r3, [r7, #4]
80042ce: 681b ldr r3, [r3, #0]
80042d0: 2110 movs r1, #16
80042d2: 4618 mov r0, r3
80042d4: f004 f912 bl 80084fc <USB_FlushTxFifo>
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80042d8: 2300 movs r3, #0
80042da: 62fb str r3, [r7, #44] @ 0x2c
80042dc: e046 b.n 800436c <HAL_PCD_IRQHandler+0x5ca>
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
80042de: 6afb ldr r3, [r7, #44] @ 0x2c
80042e0: 015a lsls r2, r3, #5
80042e2: 69fb ldr r3, [r7, #28]
80042e4: 4413 add r3, r2
80042e6: f503 6310 add.w r3, r3, #2304 @ 0x900
80042ea: 461a mov r2, r3
80042ec: f64f 337f movw r3, #64383 @ 0xfb7f
80042f0: 6093 str r3, [r2, #8]
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
80042f2: 6afb ldr r3, [r7, #44] @ 0x2c
80042f4: 015a lsls r2, r3, #5
80042f6: 69fb ldr r3, [r7, #28]
80042f8: 4413 add r3, r2
80042fa: f503 6310 add.w r3, r3, #2304 @ 0x900
80042fe: 681b ldr r3, [r3, #0]
8004300: 6afa ldr r2, [r7, #44] @ 0x2c
8004302: 0151 lsls r1, r2, #5
8004304: 69fa ldr r2, [r7, #28]
8004306: 440a add r2, r1
8004308: f502 6210 add.w r2, r2, #2304 @ 0x900
800430c: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8004310: 6013 str r3, [r2, #0]
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
8004312: 6afb ldr r3, [r7, #44] @ 0x2c
8004314: 015a lsls r2, r3, #5
8004316: 69fb ldr r3, [r7, #28]
8004318: 4413 add r3, r2
800431a: f503 6330 add.w r3, r3, #2816 @ 0xb00
800431e: 461a mov r2, r3
8004320: f64f 337f movw r3, #64383 @ 0xfb7f
8004324: 6093 str r3, [r2, #8]
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
8004326: 6afb ldr r3, [r7, #44] @ 0x2c
8004328: 015a lsls r2, r3, #5
800432a: 69fb ldr r3, [r7, #28]
800432c: 4413 add r3, r2
800432e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004332: 681b ldr r3, [r3, #0]
8004334: 6afa ldr r2, [r7, #44] @ 0x2c
8004336: 0151 lsls r1, r2, #5
8004338: 69fa ldr r2, [r7, #28]
800433a: 440a add r2, r1
800433c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004340: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8004344: 6013 str r3, [r2, #0]
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
8004346: 6afb ldr r3, [r7, #44] @ 0x2c
8004348: 015a lsls r2, r3, #5
800434a: 69fb ldr r3, [r7, #28]
800434c: 4413 add r3, r2
800434e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004352: 681b ldr r3, [r3, #0]
8004354: 6afa ldr r2, [r7, #44] @ 0x2c
8004356: 0151 lsls r1, r2, #5
8004358: 69fa ldr r2, [r7, #28]
800435a: 440a add r2, r1
800435c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004360: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
8004364: 6013 str r3, [r2, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8004366: 6afb ldr r3, [r7, #44] @ 0x2c
8004368: 3301 adds r3, #1
800436a: 62fb str r3, [r7, #44] @ 0x2c
800436c: 687b ldr r3, [r7, #4]
800436e: 791b ldrb r3, [r3, #4]
8004370: 461a mov r2, r3
8004372: 6afb ldr r3, [r7, #44] @ 0x2c
8004374: 4293 cmp r3, r2
8004376: d3b2 bcc.n 80042de <HAL_PCD_IRQHandler+0x53c>
}
USBx_DEVICE->DAINTMSK |= 0x10001U;
8004378: 69fb ldr r3, [r7, #28]
800437a: f503 6300 add.w r3, r3, #2048 @ 0x800
800437e: 69db ldr r3, [r3, #28]
8004380: 69fa ldr r2, [r7, #28]
8004382: f502 6200 add.w r2, r2, #2048 @ 0x800
8004386: f043 1301 orr.w r3, r3, #65537 @ 0x10001
800438a: 61d3 str r3, [r2, #28]
if (hpcd->Init.use_dedicated_ep1 != 0U)
800438c: 687b ldr r3, [r7, #4]
800438e: 7bdb ldrb r3, [r3, #15]
8004390: 2b00 cmp r3, #0
8004392: d016 beq.n 80043c2 <HAL_PCD_IRQHandler+0x620>
{
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
8004394: 69fb ldr r3, [r7, #28]
8004396: f503 6300 add.w r3, r3, #2048 @ 0x800
800439a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
800439e: 69fa ldr r2, [r7, #28]
80043a0: f502 6200 add.w r2, r2, #2048 @ 0x800
80043a4: f043 030b orr.w r3, r3, #11
80043a8: f8c2 3084 str.w r3, [r2, #132] @ 0x84
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM;
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
80043ac: 69fb ldr r3, [r7, #28]
80043ae: f503 6300 add.w r3, r3, #2048 @ 0x800
80043b2: 6c5b ldr r3, [r3, #68] @ 0x44
80043b4: 69fa ldr r2, [r7, #28]
80043b6: f502 6200 add.w r2, r2, #2048 @ 0x800
80043ba: f043 030b orr.w r3, r3, #11
80043be: 6453 str r3, [r2, #68] @ 0x44
80043c0: e015 b.n 80043ee <HAL_PCD_IRQHandler+0x64c>
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
else
{
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
80043c2: 69fb ldr r3, [r7, #28]
80043c4: f503 6300 add.w r3, r3, #2048 @ 0x800
80043c8: 695b ldr r3, [r3, #20]
80043ca: 69fa ldr r2, [r7, #28]
80043cc: f502 6200 add.w r2, r2, #2048 @ 0x800
80043d0: f443 5300 orr.w r3, r3, #8192 @ 0x2000
80043d4: f043 032b orr.w r3, r3, #43 @ 0x2b
80043d8: 6153 str r3, [r2, #20]
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM |
USB_OTG_DOEPMSK_OTEPSPRM |
USB_OTG_DOEPMSK_NAKM;
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
80043da: 69fb ldr r3, [r7, #28]
80043dc: f503 6300 add.w r3, r3, #2048 @ 0x800
80043e0: 691b ldr r3, [r3, #16]
80043e2: 69fa ldr r2, [r7, #28]
80043e4: f502 6200 add.w r2, r2, #2048 @ 0x800
80043e8: f043 030b orr.w r3, r3, #11
80043ec: 6113 str r3, [r2, #16]
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
/* Set Default Address to 0 */
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
80043ee: 69fb ldr r3, [r7, #28]
80043f0: f503 6300 add.w r3, r3, #2048 @ 0x800
80043f4: 681b ldr r3, [r3, #0]
80043f6: 69fa ldr r2, [r7, #28]
80043f8: f502 6200 add.w r2, r2, #2048 @ 0x800
80043fc: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
8004400: 6013 str r3, [r2, #0]
/* setup EP0 to receive SETUP packets */
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
8004402: 687b ldr r3, [r7, #4]
8004404: 681a ldr r2, [r3, #0]
8004406: 687b ldr r3, [r7, #4]
8004408: f203 439c addw r3, r3, #1180 @ 0x49c
800440c: 4619 mov r1, r3
800440e: 4610 mov r0, r2
8004410: f004 ffe4 bl 80093dc <USB_EP0_OutStart>
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
8004414: 687b ldr r3, [r7, #4]
8004416: 681b ldr r3, [r3, #0]
8004418: 695a ldr r2, [r3, #20]
800441a: 687b ldr r3, [r7, #4]
800441c: 681b ldr r3, [r3, #0]
800441e: f402 5280 and.w r2, r2, #4096 @ 0x1000
8004422: 615a str r2, [r3, #20]
}
/* Handle Enumeration done Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
8004424: 687b ldr r3, [r7, #4]
8004426: 681b ldr r3, [r3, #0]
8004428: 4618 mov r0, r3
800442a: f004 ff13 bl 8009254 <USB_ReadInterrupts>
800442e: 4603 mov r3, r0
8004430: f403 5300 and.w r3, r3, #8192 @ 0x2000
8004434: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8004438: d123 bne.n 8004482 <HAL_PCD_IRQHandler+0x6e0>
{
(void)USB_ActivateSetup(hpcd->Instance);
800443a: 687b ldr r3, [r7, #4]
800443c: 681b ldr r3, [r3, #0]
800443e: 4618 mov r0, r3
8004440: f004 ffa9 bl 8009396 <USB_ActivateSetup>
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
8004444: 687b ldr r3, [r7, #4]
8004446: 681b ldr r3, [r3, #0]
8004448: 4618 mov r0, r3
800444a: f004 f8d0 bl 80085ee <USB_GetDevSpeed>
800444e: 4603 mov r3, r0
8004450: 461a mov r2, r3
8004452: 687b ldr r3, [r7, #4]
8004454: 71da strb r2, [r3, #7]
/* Set USB Turnaround time */
(void)USB_SetTurnaroundTime(hpcd->Instance,
8004456: 687b ldr r3, [r7, #4]
8004458: 681c ldr r4, [r3, #0]
800445a: f001 fb8b bl 8005b74 <HAL_RCC_GetHCLKFreq>
800445e: 4601 mov r1, r0
HAL_RCC_GetHCLKFreq(),
(uint8_t)hpcd->Init.speed);
8004460: 687b ldr r3, [r7, #4]
8004462: 79db ldrb r3, [r3, #7]
(void)USB_SetTurnaroundTime(hpcd->Instance,
8004464: 461a mov r2, r3
8004466: 4620 mov r0, r4
8004468: f003 fdf6 bl 8008058 <USB_SetTurnaroundTime>
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
800446c: 6878 ldr r0, [r7, #4]
800446e: f006 feaa bl 800b1c6 <HAL_PCD_ResetCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
8004472: 687b ldr r3, [r7, #4]
8004474: 681b ldr r3, [r3, #0]
8004476: 695a ldr r2, [r3, #20]
8004478: 687b ldr r3, [r7, #4]
800447a: 681b ldr r3, [r3, #0]
800447c: f402 5200 and.w r2, r2, #8192 @ 0x2000
8004480: 615a str r2, [r3, #20]
}
/* Handle SOF Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
8004482: 687b ldr r3, [r7, #4]
8004484: 681b ldr r3, [r3, #0]
8004486: 4618 mov r0, r3
8004488: f004 fee4 bl 8009254 <USB_ReadInterrupts>
800448c: 4603 mov r3, r0
800448e: f003 0308 and.w r3, r3, #8
8004492: 2b08 cmp r3, #8
8004494: d10a bne.n 80044ac <HAL_PCD_IRQHandler+0x70a>
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
8004496: 6878 ldr r0, [r7, #4]
8004498: f006 fe87 bl 800b1aa <HAL_PCD_SOFCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
800449c: 687b ldr r3, [r7, #4]
800449e: 681b ldr r3, [r3, #0]
80044a0: 695a ldr r2, [r3, #20]
80044a2: 687b ldr r3, [r7, #4]
80044a4: 681b ldr r3, [r3, #0]
80044a6: f002 0208 and.w r2, r2, #8
80044aa: 615a str r2, [r3, #20]
}
/* Handle Global OUT NAK effective Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
80044ac: 687b ldr r3, [r7, #4]
80044ae: 681b ldr r3, [r3, #0]
80044b0: 4618 mov r0, r3
80044b2: f004 fecf bl 8009254 <USB_ReadInterrupts>
80044b6: 4603 mov r3, r0
80044b8: f003 0380 and.w r3, r3, #128 @ 0x80
80044bc: 2b80 cmp r3, #128 @ 0x80
80044be: d123 bne.n 8004508 <HAL_PCD_IRQHandler+0x766>
{
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
80044c0: 6a3b ldr r3, [r7, #32]
80044c2: 699b ldr r3, [r3, #24]
80044c4: f023 0280 bic.w r2, r3, #128 @ 0x80
80044c8: 6a3b ldr r3, [r7, #32]
80044ca: 619a str r2, [r3, #24]
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
80044cc: 2301 movs r3, #1
80044ce: 627b str r3, [r7, #36] @ 0x24
80044d0: e014 b.n 80044fc <HAL_PCD_IRQHandler+0x75a>
{
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
80044d2: 6879 ldr r1, [r7, #4]
80044d4: 6a7a ldr r2, [r7, #36] @ 0x24
80044d6: 4613 mov r3, r2
80044d8: 00db lsls r3, r3, #3
80044da: 4413 add r3, r2
80044dc: 009b lsls r3, r3, #2
80044de: 440b add r3, r1
80044e0: f203 2357 addw r3, r3, #599 @ 0x257
80044e4: 781b ldrb r3, [r3, #0]
80044e6: 2b01 cmp r3, #1
80044e8: d105 bne.n 80044f6 <HAL_PCD_IRQHandler+0x754>
{
/* Abort current transaction and disable the EP */
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
80044ea: 6a7b ldr r3, [r7, #36] @ 0x24
80044ec: b2db uxtb r3, r3
80044ee: 4619 mov r1, r3
80044f0: 6878 ldr r0, [r7, #4]
80044f2: f000 fadf bl 8004ab4 <HAL_PCD_EP_Abort>
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
80044f6: 6a7b ldr r3, [r7, #36] @ 0x24
80044f8: 3301 adds r3, #1
80044fa: 627b str r3, [r7, #36] @ 0x24
80044fc: 687b ldr r3, [r7, #4]
80044fe: 791b ldrb r3, [r3, #4]
8004500: 461a mov r2, r3
8004502: 6a7b ldr r3, [r7, #36] @ 0x24
8004504: 4293 cmp r3, r2
8004506: d3e4 bcc.n 80044d2 <HAL_PCD_IRQHandler+0x730>
}
}
}
/* Handle Incomplete ISO IN Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
8004508: 687b ldr r3, [r7, #4]
800450a: 681b ldr r3, [r3, #0]
800450c: 4618 mov r0, r3
800450e: f004 fea1 bl 8009254 <USB_ReadInterrupts>
8004512: 4603 mov r3, r0
8004514: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8004518: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800451c: d13c bne.n 8004598 <HAL_PCD_IRQHandler+0x7f6>
{
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
800451e: 2301 movs r3, #1
8004520: 627b str r3, [r7, #36] @ 0x24
8004522: e02b b.n 800457c <HAL_PCD_IRQHandler+0x7da>
{
RegVal = USBx_INEP(epnum)->DIEPCTL;
8004524: 6a7b ldr r3, [r7, #36] @ 0x24
8004526: 015a lsls r2, r3, #5
8004528: 69fb ldr r3, [r7, #28]
800452a: 4413 add r3, r2
800452c: f503 6310 add.w r3, r3, #2304 @ 0x900
8004530: 681b ldr r3, [r3, #0]
8004532: 61bb str r3, [r7, #24]
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
8004534: 6879 ldr r1, [r7, #4]
8004536: 6a7a ldr r2, [r7, #36] @ 0x24
8004538: 4613 mov r3, r2
800453a: 00db lsls r3, r3, #3
800453c: 4413 add r3, r2
800453e: 009b lsls r3, r3, #2
8004540: 440b add r3, r1
8004542: 3318 adds r3, #24
8004544: 781b ldrb r3, [r3, #0]
8004546: 2b01 cmp r3, #1
8004548: d115 bne.n 8004576 <HAL_PCD_IRQHandler+0x7d4>
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
800454a: 69bb ldr r3, [r7, #24]
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
800454c: 2b00 cmp r3, #0
800454e: da12 bge.n 8004576 <HAL_PCD_IRQHandler+0x7d4>
{
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
8004550: 6879 ldr r1, [r7, #4]
8004552: 6a7a ldr r2, [r7, #36] @ 0x24
8004554: 4613 mov r3, r2
8004556: 00db lsls r3, r3, #3
8004558: 4413 add r3, r2
800455a: 009b lsls r3, r3, #2
800455c: 440b add r3, r1
800455e: 3317 adds r3, #23
8004560: 2201 movs r2, #1
8004562: 701a strb r2, [r3, #0]
/* Abort current transaction and disable the EP */
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
8004564: 6a7b ldr r3, [r7, #36] @ 0x24
8004566: b2db uxtb r3, r3
8004568: f063 037f orn r3, r3, #127 @ 0x7f
800456c: b2db uxtb r3, r3
800456e: 4619 mov r1, r3
8004570: 6878 ldr r0, [r7, #4]
8004572: f000 fa9f bl 8004ab4 <HAL_PCD_EP_Abort>
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
8004576: 6a7b ldr r3, [r7, #36] @ 0x24
8004578: 3301 adds r3, #1
800457a: 627b str r3, [r7, #36] @ 0x24
800457c: 687b ldr r3, [r7, #4]
800457e: 791b ldrb r3, [r3, #4]
8004580: 461a mov r2, r3
8004582: 6a7b ldr r3, [r7, #36] @ 0x24
8004584: 4293 cmp r3, r2
8004586: d3cd bcc.n 8004524 <HAL_PCD_IRQHandler+0x782>
}
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
8004588: 687b ldr r3, [r7, #4]
800458a: 681b ldr r3, [r3, #0]
800458c: 695a ldr r2, [r3, #20]
800458e: 687b ldr r3, [r7, #4]
8004590: 681b ldr r3, [r3, #0]
8004592: f402 1280 and.w r2, r2, #1048576 @ 0x100000
8004596: 615a str r2, [r3, #20]
}
/* Handle Incomplete ISO OUT Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
8004598: 687b ldr r3, [r7, #4]
800459a: 681b ldr r3, [r3, #0]
800459c: 4618 mov r0, r3
800459e: f004 fe59 bl 8009254 <USB_ReadInterrupts>
80045a2: 4603 mov r3, r0
80045a4: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80045a8: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
80045ac: d156 bne.n 800465c <HAL_PCD_IRQHandler+0x8ba>
{
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
80045ae: 2301 movs r3, #1
80045b0: 627b str r3, [r7, #36] @ 0x24
80045b2: e045 b.n 8004640 <HAL_PCD_IRQHandler+0x89e>
{
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
80045b4: 6a7b ldr r3, [r7, #36] @ 0x24
80045b6: 015a lsls r2, r3, #5
80045b8: 69fb ldr r3, [r7, #28]
80045ba: 4413 add r3, r2
80045bc: f503 6330 add.w r3, r3, #2816 @ 0xb00
80045c0: 681b ldr r3, [r3, #0]
80045c2: 61bb str r3, [r7, #24]
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
80045c4: 6879 ldr r1, [r7, #4]
80045c6: 6a7a ldr r2, [r7, #36] @ 0x24
80045c8: 4613 mov r3, r2
80045ca: 00db lsls r3, r3, #3
80045cc: 4413 add r3, r2
80045ce: 009b lsls r3, r3, #2
80045d0: 440b add r3, r1
80045d2: f503 7316 add.w r3, r3, #600 @ 0x258
80045d6: 781b ldrb r3, [r3, #0]
80045d8: 2b01 cmp r3, #1
80045da: d12e bne.n 800463a <HAL_PCD_IRQHandler+0x898>
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
80045dc: 69bb ldr r3, [r7, #24]
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
80045de: 2b00 cmp r3, #0
80045e0: da2b bge.n 800463a <HAL_PCD_IRQHandler+0x898>
((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U)))
80045e2: 69bb ldr r3, [r7, #24]
80045e4: f403 3280 and.w r2, r3, #65536 @ 0x10000
80045e8: 687b ldr r3, [r7, #4]
80045ea: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4
80045ee: f003 0301 and.w r3, r3, #1
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
80045f2: 429a cmp r2, r3
80045f4: d121 bne.n 800463a <HAL_PCD_IRQHandler+0x898>
{
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
80045f6: 6879 ldr r1, [r7, #4]
80045f8: 6a7a ldr r2, [r7, #36] @ 0x24
80045fa: 4613 mov r3, r2
80045fc: 00db lsls r3, r3, #3
80045fe: 4413 add r3, r2
8004600: 009b lsls r3, r3, #2
8004602: 440b add r3, r1
8004604: f203 2357 addw r3, r3, #599 @ 0x257
8004608: 2201 movs r2, #1
800460a: 701a strb r2, [r3, #0]
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
800460c: 6a3b ldr r3, [r7, #32]
800460e: 699b ldr r3, [r3, #24]
8004610: f043 0280 orr.w r2, r3, #128 @ 0x80
8004614: 6a3b ldr r3, [r7, #32]
8004616: 619a str r2, [r3, #24]
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
8004618: 6a3b ldr r3, [r7, #32]
800461a: 695b ldr r3, [r3, #20]
800461c: f003 0380 and.w r3, r3, #128 @ 0x80
8004620: 2b00 cmp r3, #0
8004622: d10a bne.n 800463a <HAL_PCD_IRQHandler+0x898>
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
8004624: 69fb ldr r3, [r7, #28]
8004626: f503 6300 add.w r3, r3, #2048 @ 0x800
800462a: 685b ldr r3, [r3, #4]
800462c: 69fa ldr r2, [r7, #28]
800462e: f502 6200 add.w r2, r2, #2048 @ 0x800
8004632: f443 7300 orr.w r3, r3, #512 @ 0x200
8004636: 6053 str r3, [r2, #4]
break;
8004638: e008 b.n 800464c <HAL_PCD_IRQHandler+0x8aa>
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
800463a: 6a7b ldr r3, [r7, #36] @ 0x24
800463c: 3301 adds r3, #1
800463e: 627b str r3, [r7, #36] @ 0x24
8004640: 687b ldr r3, [r7, #4]
8004642: 791b ldrb r3, [r3, #4]
8004644: 461a mov r2, r3
8004646: 6a7b ldr r3, [r7, #36] @ 0x24
8004648: 4293 cmp r3, r2
800464a: d3b3 bcc.n 80045b4 <HAL_PCD_IRQHandler+0x812>
}
}
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
800464c: 687b ldr r3, [r7, #4]
800464e: 681b ldr r3, [r3, #0]
8004650: 695a ldr r2, [r3, #20]
8004652: 687b ldr r3, [r7, #4]
8004654: 681b ldr r3, [r3, #0]
8004656: f402 1200 and.w r2, r2, #2097152 @ 0x200000
800465a: 615a str r2, [r3, #20]
}
/* Handle Connection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
800465c: 687b ldr r3, [r7, #4]
800465e: 681b ldr r3, [r3, #0]
8004660: 4618 mov r0, r3
8004662: f004 fdf7 bl 8009254 <USB_ReadInterrupts>
8004666: 4603 mov r3, r0
8004668: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
800466c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004670: d10a bne.n 8004688 <HAL_PCD_IRQHandler+0x8e6>
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ConnectCallback(hpcd);
#else
HAL_PCD_ConnectCallback(hpcd);
8004672: 6878 ldr r0, [r7, #4]
8004674: f006 fe38 bl 800b2e8 <HAL_PCD_ConnectCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
8004678: 687b ldr r3, [r7, #4]
800467a: 681b ldr r3, [r3, #0]
800467c: 695a ldr r2, [r3, #20]
800467e: 687b ldr r3, [r7, #4]
8004680: 681b ldr r3, [r3, #0]
8004682: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
8004686: 615a str r2, [r3, #20]
}
/* Handle Disconnection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
8004688: 687b ldr r3, [r7, #4]
800468a: 681b ldr r3, [r3, #0]
800468c: 4618 mov r0, r3
800468e: f004 fde1 bl 8009254 <USB_ReadInterrupts>
8004692: 4603 mov r3, r0
8004694: f003 0304 and.w r3, r3, #4
8004698: 2b04 cmp r3, #4
800469a: d115 bne.n 80046c8 <HAL_PCD_IRQHandler+0x926>
{
RegVal = hpcd->Instance->GOTGINT;
800469c: 687b ldr r3, [r7, #4]
800469e: 681b ldr r3, [r3, #0]
80046a0: 685b ldr r3, [r3, #4]
80046a2: 61bb str r3, [r7, #24]
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
80046a4: 69bb ldr r3, [r7, #24]
80046a6: f003 0304 and.w r3, r3, #4
80046aa: 2b00 cmp r3, #0
80046ac: d002 beq.n 80046b4 <HAL_PCD_IRQHandler+0x912>
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DisconnectCallback(hpcd);
#else
HAL_PCD_DisconnectCallback(hpcd);
80046ae: 6878 ldr r0, [r7, #4]
80046b0: f006 fe28 bl 800b304 <HAL_PCD_DisconnectCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
hpcd->Instance->GOTGINT |= RegVal;
80046b4: 687b ldr r3, [r7, #4]
80046b6: 681b ldr r3, [r3, #0]
80046b8: 6859 ldr r1, [r3, #4]
80046ba: 687b ldr r3, [r7, #4]
80046bc: 681b ldr r3, [r3, #0]
80046be: 69ba ldr r2, [r7, #24]
80046c0: 430a orrs r2, r1
80046c2: 605a str r2, [r3, #4]
80046c4: e000 b.n 80046c8 <HAL_PCD_IRQHandler+0x926>
return;
80046c6: bf00 nop
}
}
}
80046c8: 3734 adds r7, #52 @ 0x34
80046ca: 46bd mov sp, r7
80046cc: bd90 pop {r4, r7, pc}
080046ce <HAL_PCD_SetAddress>:
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
80046ce: b580 push {r7, lr}
80046d0: b082 sub sp, #8
80046d2: af00 add r7, sp, #0
80046d4: 6078 str r0, [r7, #4]
80046d6: 460b mov r3, r1
80046d8: 70fb strb r3, [r7, #3]
__HAL_LOCK(hpcd);
80046da: 687b ldr r3, [r7, #4]
80046dc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
80046e0: 2b01 cmp r3, #1
80046e2: d101 bne.n 80046e8 <HAL_PCD_SetAddress+0x1a>
80046e4: 2302 movs r3, #2
80046e6: e012 b.n 800470e <HAL_PCD_SetAddress+0x40>
80046e8: 687b ldr r3, [r7, #4]
80046ea: 2201 movs r2, #1
80046ec: f883 2494 strb.w r2, [r3, #1172] @ 0x494
hpcd->USB_Address = address;
80046f0: 687b ldr r3, [r7, #4]
80046f2: 78fa ldrb r2, [r7, #3]
80046f4: 745a strb r2, [r3, #17]
(void)USB_SetDevAddress(hpcd->Instance, address);
80046f6: 687b ldr r3, [r7, #4]
80046f8: 681b ldr r3, [r3, #0]
80046fa: 78fa ldrb r2, [r7, #3]
80046fc: 4611 mov r1, r2
80046fe: 4618 mov r0, r3
8004700: f004 fd40 bl 8009184 <USB_SetDevAddress>
__HAL_UNLOCK(hpcd);
8004704: 687b ldr r3, [r7, #4]
8004706: 2200 movs r2, #0
8004708: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
800470c: 2300 movs r3, #0
}
800470e: 4618 mov r0, r3
8004710: 3708 adds r7, #8
8004712: 46bd mov sp, r7
8004714: bd80 pop {r7, pc}
08004716 <HAL_PCD_EP_Open>:
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
8004716: b580 push {r7, lr}
8004718: b084 sub sp, #16
800471a: af00 add r7, sp, #0
800471c: 6078 str r0, [r7, #4]
800471e: 4608 mov r0, r1
8004720: 4611 mov r1, r2
8004722: 461a mov r2, r3
8004724: 4603 mov r3, r0
8004726: 70fb strb r3, [r7, #3]
8004728: 460b mov r3, r1
800472a: 803b strh r3, [r7, #0]
800472c: 4613 mov r3, r2
800472e: 70bb strb r3, [r7, #2]
HAL_StatusTypeDef ret = HAL_OK;
8004730: 2300 movs r3, #0
8004732: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8004734: f997 3003 ldrsb.w r3, [r7, #3]
8004738: 2b00 cmp r3, #0
800473a: da0f bge.n 800475c <HAL_PCD_EP_Open+0x46>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800473c: 78fb ldrb r3, [r7, #3]
800473e: f003 020f and.w r2, r3, #15
8004742: 4613 mov r3, r2
8004744: 00db lsls r3, r3, #3
8004746: 4413 add r3, r2
8004748: 009b lsls r3, r3, #2
800474a: 3310 adds r3, #16
800474c: 687a ldr r2, [r7, #4]
800474e: 4413 add r3, r2
8004750: 3304 adds r3, #4
8004752: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8004754: 68fb ldr r3, [r7, #12]
8004756: 2201 movs r2, #1
8004758: 705a strb r2, [r3, #1]
800475a: e00f b.n 800477c <HAL_PCD_EP_Open+0x66>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
800475c: 78fb ldrb r3, [r7, #3]
800475e: f003 020f and.w r2, r3, #15
8004762: 4613 mov r3, r2
8004764: 00db lsls r3, r3, #3
8004766: 4413 add r3, r2
8004768: 009b lsls r3, r3, #2
800476a: f503 7314 add.w r3, r3, #592 @ 0x250
800476e: 687a ldr r2, [r7, #4]
8004770: 4413 add r3, r2
8004772: 3304 adds r3, #4
8004774: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8004776: 68fb ldr r3, [r7, #12]
8004778: 2200 movs r2, #0
800477a: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
800477c: 78fb ldrb r3, [r7, #3]
800477e: f003 030f and.w r3, r3, #15
8004782: b2da uxtb r2, r3
8004784: 68fb ldr r3, [r7, #12]
8004786: 701a strb r2, [r3, #0]
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
8004788: 883b ldrh r3, [r7, #0]
800478a: f3c3 020a ubfx r2, r3, #0, #11
800478e: 68fb ldr r3, [r7, #12]
8004790: 609a str r2, [r3, #8]
ep->type = ep_type;
8004792: 68fb ldr r3, [r7, #12]
8004794: 78ba ldrb r2, [r7, #2]
8004796: 711a strb r2, [r3, #4]
#if defined (USB_OTG_FS)
if (ep->is_in != 0U)
8004798: 68fb ldr r3, [r7, #12]
800479a: 785b ldrb r3, [r3, #1]
800479c: 2b00 cmp r3, #0
800479e: d004 beq.n 80047aa <HAL_PCD_EP_Open+0x94>
{
/* Assign a Tx FIFO */
ep->tx_fifo_num = ep->num;
80047a0: 68fb ldr r3, [r7, #12]
80047a2: 781b ldrb r3, [r3, #0]
80047a4: 461a mov r2, r3
80047a6: 68fb ldr r3, [r7, #12]
80047a8: 835a strh r2, [r3, #26]
}
#endif /* defined (USB_OTG_FS) */
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
80047aa: 78bb ldrb r3, [r7, #2]
80047ac: 2b02 cmp r3, #2
80047ae: d102 bne.n 80047b6 <HAL_PCD_EP_Open+0xa0>
{
ep->data_pid_start = 0U;
80047b0: 68fb ldr r3, [r7, #12]
80047b2: 2200 movs r2, #0
80047b4: 715a strb r2, [r3, #5]
}
__HAL_LOCK(hpcd);
80047b6: 687b ldr r3, [r7, #4]
80047b8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
80047bc: 2b01 cmp r3, #1
80047be: d101 bne.n 80047c4 <HAL_PCD_EP_Open+0xae>
80047c0: 2302 movs r3, #2
80047c2: e00e b.n 80047e2 <HAL_PCD_EP_Open+0xcc>
80047c4: 687b ldr r3, [r7, #4]
80047c6: 2201 movs r2, #1
80047c8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
80047cc: 687b ldr r3, [r7, #4]
80047ce: 681b ldr r3, [r3, #0]
80047d0: 68f9 ldr r1, [r7, #12]
80047d2: 4618 mov r0, r3
80047d4: f003 ff2a bl 800862c <USB_ActivateEndpoint>
__HAL_UNLOCK(hpcd);
80047d8: 687b ldr r3, [r7, #4]
80047da: 2200 movs r2, #0
80047dc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return ret;
80047e0: 7afb ldrb r3, [r7, #11]
}
80047e2: 4618 mov r0, r3
80047e4: 3710 adds r7, #16
80047e6: 46bd mov sp, r7
80047e8: bd80 pop {r7, pc}
080047ea <HAL_PCD_EP_Close>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
80047ea: b580 push {r7, lr}
80047ec: b084 sub sp, #16
80047ee: af00 add r7, sp, #0
80047f0: 6078 str r0, [r7, #4]
80047f2: 460b mov r3, r1
80047f4: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
80047f6: f997 3003 ldrsb.w r3, [r7, #3]
80047fa: 2b00 cmp r3, #0
80047fc: da0f bge.n 800481e <HAL_PCD_EP_Close+0x34>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
80047fe: 78fb ldrb r3, [r7, #3]
8004800: f003 020f and.w r2, r3, #15
8004804: 4613 mov r3, r2
8004806: 00db lsls r3, r3, #3
8004808: 4413 add r3, r2
800480a: 009b lsls r3, r3, #2
800480c: 3310 adds r3, #16
800480e: 687a ldr r2, [r7, #4]
8004810: 4413 add r3, r2
8004812: 3304 adds r3, #4
8004814: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8004816: 68fb ldr r3, [r7, #12]
8004818: 2201 movs r2, #1
800481a: 705a strb r2, [r3, #1]
800481c: e00f b.n 800483e <HAL_PCD_EP_Close+0x54>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
800481e: 78fb ldrb r3, [r7, #3]
8004820: f003 020f and.w r2, r3, #15
8004824: 4613 mov r3, r2
8004826: 00db lsls r3, r3, #3
8004828: 4413 add r3, r2
800482a: 009b lsls r3, r3, #2
800482c: f503 7314 add.w r3, r3, #592 @ 0x250
8004830: 687a ldr r2, [r7, #4]
8004832: 4413 add r3, r2
8004834: 3304 adds r3, #4
8004836: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8004838: 68fb ldr r3, [r7, #12]
800483a: 2200 movs r2, #0
800483c: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
800483e: 78fb ldrb r3, [r7, #3]
8004840: f003 030f and.w r3, r3, #15
8004844: b2da uxtb r2, r3
8004846: 68fb ldr r3, [r7, #12]
8004848: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
800484a: 687b ldr r3, [r7, #4]
800484c: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
8004850: 2b01 cmp r3, #1
8004852: d101 bne.n 8004858 <HAL_PCD_EP_Close+0x6e>
8004854: 2302 movs r3, #2
8004856: e00e b.n 8004876 <HAL_PCD_EP_Close+0x8c>
8004858: 687b ldr r3, [r7, #4]
800485a: 2201 movs r2, #1
800485c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
8004860: 687b ldr r3, [r7, #4]
8004862: 681b ldr r3, [r3, #0]
8004864: 68f9 ldr r1, [r7, #12]
8004866: 4618 mov r0, r3
8004868: f003 ff68 bl 800873c <USB_DeactivateEndpoint>
__HAL_UNLOCK(hpcd);
800486c: 687b ldr r3, [r7, #4]
800486e: 2200 movs r2, #0
8004870: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
8004874: 2300 movs r3, #0
}
8004876: 4618 mov r0, r3
8004878: 3710 adds r7, #16
800487a: 46bd mov sp, r7
800487c: bd80 pop {r7, pc}
0800487e <HAL_PCD_EP_Receive>:
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
800487e: b580 push {r7, lr}
8004880: b086 sub sp, #24
8004882: af00 add r7, sp, #0
8004884: 60f8 str r0, [r7, #12]
8004886: 607a str r2, [r7, #4]
8004888: 603b str r3, [r7, #0]
800488a: 460b mov r3, r1
800488c: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
800488e: 7afb ldrb r3, [r7, #11]
8004890: f003 020f and.w r2, r3, #15
8004894: 4613 mov r3, r2
8004896: 00db lsls r3, r3, #3
8004898: 4413 add r3, r2
800489a: 009b lsls r3, r3, #2
800489c: f503 7314 add.w r3, r3, #592 @ 0x250
80048a0: 68fa ldr r2, [r7, #12]
80048a2: 4413 add r3, r2
80048a4: 3304 adds r3, #4
80048a6: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
80048a8: 697b ldr r3, [r7, #20]
80048aa: 687a ldr r2, [r7, #4]
80048ac: 60da str r2, [r3, #12]
ep->xfer_len = len;
80048ae: 697b ldr r3, [r7, #20]
80048b0: 683a ldr r2, [r7, #0]
80048b2: 611a str r2, [r3, #16]
ep->xfer_count = 0U;
80048b4: 697b ldr r3, [r7, #20]
80048b6: 2200 movs r2, #0
80048b8: 615a str r2, [r3, #20]
ep->is_in = 0U;
80048ba: 697b ldr r3, [r7, #20]
80048bc: 2200 movs r2, #0
80048be: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
80048c0: 7afb ldrb r3, [r7, #11]
80048c2: f003 030f and.w r3, r3, #15
80048c6: b2da uxtb r2, r3
80048c8: 697b ldr r3, [r7, #20]
80048ca: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
80048cc: 68fb ldr r3, [r7, #12]
80048ce: 681b ldr r3, [r3, #0]
80048d0: 6979 ldr r1, [r7, #20]
80048d2: 4618 mov r0, r3
80048d4: f004 f80e bl 80088f4 <USB_EPStartXfer>
return HAL_OK;
80048d8: 2300 movs r3, #0
}
80048da: 4618 mov r0, r3
80048dc: 3718 adds r7, #24
80048de: 46bd mov sp, r7
80048e0: bd80 pop {r7, pc}
080048e2 <HAL_PCD_EP_Transmit>:
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
80048e2: b580 push {r7, lr}
80048e4: b086 sub sp, #24
80048e6: af00 add r7, sp, #0
80048e8: 60f8 str r0, [r7, #12]
80048ea: 607a str r2, [r7, #4]
80048ec: 603b str r3, [r7, #0]
80048ee: 460b mov r3, r1
80048f0: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
80048f2: 7afb ldrb r3, [r7, #11]
80048f4: f003 020f and.w r2, r3, #15
80048f8: 4613 mov r3, r2
80048fa: 00db lsls r3, r3, #3
80048fc: 4413 add r3, r2
80048fe: 009b lsls r3, r3, #2
8004900: 3310 adds r3, #16
8004902: 68fa ldr r2, [r7, #12]
8004904: 4413 add r3, r2
8004906: 3304 adds r3, #4
8004908: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
800490a: 697b ldr r3, [r7, #20]
800490c: 687a ldr r2, [r7, #4]
800490e: 60da str r2, [r3, #12]
ep->xfer_len = len;
8004910: 697b ldr r3, [r7, #20]
8004912: 683a ldr r2, [r7, #0]
8004914: 611a str r2, [r3, #16]
#if defined (USB)
ep->xfer_fill_db = 1U;
ep->xfer_len_db = len;
#endif /* defined (USB) */
ep->xfer_count = 0U;
8004916: 697b ldr r3, [r7, #20]
8004918: 2200 movs r2, #0
800491a: 615a str r2, [r3, #20]
ep->is_in = 1U;
800491c: 697b ldr r3, [r7, #20]
800491e: 2201 movs r2, #1
8004920: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8004922: 7afb ldrb r3, [r7, #11]
8004924: f003 030f and.w r3, r3, #15
8004928: b2da uxtb r2, r3
800492a: 697b ldr r3, [r7, #20]
800492c: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
800492e: 68fb ldr r3, [r7, #12]
8004930: 681b ldr r3, [r3, #0]
8004932: 6979 ldr r1, [r7, #20]
8004934: 4618 mov r0, r3
8004936: f003 ffdd bl 80088f4 <USB_EPStartXfer>
return HAL_OK;
800493a: 2300 movs r3, #0
}
800493c: 4618 mov r0, r3
800493e: 3718 adds r7, #24
8004940: 46bd mov sp, r7
8004942: bd80 pop {r7, pc}
08004944 <HAL_PCD_EP_SetStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8004944: b580 push {r7, lr}
8004946: b084 sub sp, #16
8004948: af00 add r7, sp, #0
800494a: 6078 str r0, [r7, #4]
800494c: 460b mov r3, r1
800494e: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
8004950: 78fb ldrb r3, [r7, #3]
8004952: f003 030f and.w r3, r3, #15
8004956: 687a ldr r2, [r7, #4]
8004958: 7912 ldrb r2, [r2, #4]
800495a: 4293 cmp r3, r2
800495c: d901 bls.n 8004962 <HAL_PCD_EP_SetStall+0x1e>
{
return HAL_ERROR;
800495e: 2301 movs r3, #1
8004960: e04e b.n 8004a00 <HAL_PCD_EP_SetStall+0xbc>
}
if ((0x80U & ep_addr) == 0x80U)
8004962: f997 3003 ldrsb.w r3, [r7, #3]
8004966: 2b00 cmp r3, #0
8004968: da0f bge.n 800498a <HAL_PCD_EP_SetStall+0x46>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800496a: 78fb ldrb r3, [r7, #3]
800496c: f003 020f and.w r2, r3, #15
8004970: 4613 mov r3, r2
8004972: 00db lsls r3, r3, #3
8004974: 4413 add r3, r2
8004976: 009b lsls r3, r3, #2
8004978: 3310 adds r3, #16
800497a: 687a ldr r2, [r7, #4]
800497c: 4413 add r3, r2
800497e: 3304 adds r3, #4
8004980: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8004982: 68fb ldr r3, [r7, #12]
8004984: 2201 movs r2, #1
8004986: 705a strb r2, [r3, #1]
8004988: e00d b.n 80049a6 <HAL_PCD_EP_SetStall+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
800498a: 78fa ldrb r2, [r7, #3]
800498c: 4613 mov r3, r2
800498e: 00db lsls r3, r3, #3
8004990: 4413 add r3, r2
8004992: 009b lsls r3, r3, #2
8004994: f503 7314 add.w r3, r3, #592 @ 0x250
8004998: 687a ldr r2, [r7, #4]
800499a: 4413 add r3, r2
800499c: 3304 adds r3, #4
800499e: 60fb str r3, [r7, #12]
ep->is_in = 0U;
80049a0: 68fb ldr r3, [r7, #12]
80049a2: 2200 movs r2, #0
80049a4: 705a strb r2, [r3, #1]
}
ep->is_stall = 1U;
80049a6: 68fb ldr r3, [r7, #12]
80049a8: 2201 movs r2, #1
80049aa: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
80049ac: 78fb ldrb r3, [r7, #3]
80049ae: f003 030f and.w r3, r3, #15
80049b2: b2da uxtb r2, r3
80049b4: 68fb ldr r3, [r7, #12]
80049b6: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
80049b8: 687b ldr r3, [r7, #4]
80049ba: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
80049be: 2b01 cmp r3, #1
80049c0: d101 bne.n 80049c6 <HAL_PCD_EP_SetStall+0x82>
80049c2: 2302 movs r3, #2
80049c4: e01c b.n 8004a00 <HAL_PCD_EP_SetStall+0xbc>
80049c6: 687b ldr r3, [r7, #4]
80049c8: 2201 movs r2, #1
80049ca: f883 2494 strb.w r2, [r3, #1172] @ 0x494
(void)USB_EPSetStall(hpcd->Instance, ep);
80049ce: 687b ldr r3, [r7, #4]
80049d0: 681b ldr r3, [r3, #0]
80049d2: 68f9 ldr r1, [r7, #12]
80049d4: 4618 mov r0, r3
80049d6: f004 fb01 bl 8008fdc <USB_EPSetStall>
if ((ep_addr & EP_ADDR_MSK) == 0U)
80049da: 78fb ldrb r3, [r7, #3]
80049dc: f003 030f and.w r3, r3, #15
80049e0: 2b00 cmp r3, #0
80049e2: d108 bne.n 80049f6 <HAL_PCD_EP_SetStall+0xb2>
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
80049e4: 687b ldr r3, [r7, #4]
80049e6: 681a ldr r2, [r3, #0]
80049e8: 687b ldr r3, [r7, #4]
80049ea: f203 439c addw r3, r3, #1180 @ 0x49c
80049ee: 4619 mov r1, r3
80049f0: 4610 mov r0, r2
80049f2: f004 fcf3 bl 80093dc <USB_EP0_OutStart>
}
__HAL_UNLOCK(hpcd);
80049f6: 687b ldr r3, [r7, #4]
80049f8: 2200 movs r2, #0
80049fa: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
80049fe: 2300 movs r3, #0
}
8004a00: 4618 mov r0, r3
8004a02: 3710 adds r7, #16
8004a04: 46bd mov sp, r7
8004a06: bd80 pop {r7, pc}
08004a08 <HAL_PCD_EP_ClrStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8004a08: b580 push {r7, lr}
8004a0a: b084 sub sp, #16
8004a0c: af00 add r7, sp, #0
8004a0e: 6078 str r0, [r7, #4]
8004a10: 460b mov r3, r1
8004a12: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
8004a14: 78fb ldrb r3, [r7, #3]
8004a16: f003 030f and.w r3, r3, #15
8004a1a: 687a ldr r2, [r7, #4]
8004a1c: 7912 ldrb r2, [r2, #4]
8004a1e: 4293 cmp r3, r2
8004a20: d901 bls.n 8004a26 <HAL_PCD_EP_ClrStall+0x1e>
{
return HAL_ERROR;
8004a22: 2301 movs r3, #1
8004a24: e042 b.n 8004aac <HAL_PCD_EP_ClrStall+0xa4>
}
if ((0x80U & ep_addr) == 0x80U)
8004a26: f997 3003 ldrsb.w r3, [r7, #3]
8004a2a: 2b00 cmp r3, #0
8004a2c: da0f bge.n 8004a4e <HAL_PCD_EP_ClrStall+0x46>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8004a2e: 78fb ldrb r3, [r7, #3]
8004a30: f003 020f and.w r2, r3, #15
8004a34: 4613 mov r3, r2
8004a36: 00db lsls r3, r3, #3
8004a38: 4413 add r3, r2
8004a3a: 009b lsls r3, r3, #2
8004a3c: 3310 adds r3, #16
8004a3e: 687a ldr r2, [r7, #4]
8004a40: 4413 add r3, r2
8004a42: 3304 adds r3, #4
8004a44: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8004a46: 68fb ldr r3, [r7, #12]
8004a48: 2201 movs r2, #1
8004a4a: 705a strb r2, [r3, #1]
8004a4c: e00f b.n 8004a6e <HAL_PCD_EP_ClrStall+0x66>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8004a4e: 78fb ldrb r3, [r7, #3]
8004a50: f003 020f and.w r2, r3, #15
8004a54: 4613 mov r3, r2
8004a56: 00db lsls r3, r3, #3
8004a58: 4413 add r3, r2
8004a5a: 009b lsls r3, r3, #2
8004a5c: f503 7314 add.w r3, r3, #592 @ 0x250
8004a60: 687a ldr r2, [r7, #4]
8004a62: 4413 add r3, r2
8004a64: 3304 adds r3, #4
8004a66: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8004a68: 68fb ldr r3, [r7, #12]
8004a6a: 2200 movs r2, #0
8004a6c: 705a strb r2, [r3, #1]
}
ep->is_stall = 0U;
8004a6e: 68fb ldr r3, [r7, #12]
8004a70: 2200 movs r2, #0
8004a72: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8004a74: 78fb ldrb r3, [r7, #3]
8004a76: f003 030f and.w r3, r3, #15
8004a7a: b2da uxtb r2, r3
8004a7c: 68fb ldr r3, [r7, #12]
8004a7e: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8004a80: 687b ldr r3, [r7, #4]
8004a82: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
8004a86: 2b01 cmp r3, #1
8004a88: d101 bne.n 8004a8e <HAL_PCD_EP_ClrStall+0x86>
8004a8a: 2302 movs r3, #2
8004a8c: e00e b.n 8004aac <HAL_PCD_EP_ClrStall+0xa4>
8004a8e: 687b ldr r3, [r7, #4]
8004a90: 2201 movs r2, #1
8004a92: f883 2494 strb.w r2, [r3, #1172] @ 0x494
(void)USB_EPClearStall(hpcd->Instance, ep);
8004a96: 687b ldr r3, [r7, #4]
8004a98: 681b ldr r3, [r3, #0]
8004a9a: 68f9 ldr r1, [r7, #12]
8004a9c: 4618 mov r0, r3
8004a9e: f004 fb0b bl 80090b8 <USB_EPClearStall>
__HAL_UNLOCK(hpcd);
8004aa2: 687b ldr r3, [r7, #4]
8004aa4: 2200 movs r2, #0
8004aa6: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
8004aaa: 2300 movs r3, #0
}
8004aac: 4618 mov r0, r3
8004aae: 3710 adds r7, #16
8004ab0: 46bd mov sp, r7
8004ab2: bd80 pop {r7, pc}
08004ab4 <HAL_PCD_EP_Abort>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8004ab4: b580 push {r7, lr}
8004ab6: b084 sub sp, #16
8004ab8: af00 add r7, sp, #0
8004aba: 6078 str r0, [r7, #4]
8004abc: 460b mov r3, r1
8004abe: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef ret;
PCD_EPTypeDef *ep;
if ((0x80U & ep_addr) == 0x80U)
8004ac0: f997 3003 ldrsb.w r3, [r7, #3]
8004ac4: 2b00 cmp r3, #0
8004ac6: da0c bge.n 8004ae2 <HAL_PCD_EP_Abort+0x2e>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8004ac8: 78fb ldrb r3, [r7, #3]
8004aca: f003 020f and.w r2, r3, #15
8004ace: 4613 mov r3, r2
8004ad0: 00db lsls r3, r3, #3
8004ad2: 4413 add r3, r2
8004ad4: 009b lsls r3, r3, #2
8004ad6: 3310 adds r3, #16
8004ad8: 687a ldr r2, [r7, #4]
8004ada: 4413 add r3, r2
8004adc: 3304 adds r3, #4
8004ade: 60fb str r3, [r7, #12]
8004ae0: e00c b.n 8004afc <HAL_PCD_EP_Abort+0x48>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8004ae2: 78fb ldrb r3, [r7, #3]
8004ae4: f003 020f and.w r2, r3, #15
8004ae8: 4613 mov r3, r2
8004aea: 00db lsls r3, r3, #3
8004aec: 4413 add r3, r2
8004aee: 009b lsls r3, r3, #2
8004af0: f503 7314 add.w r3, r3, #592 @ 0x250
8004af4: 687a ldr r2, [r7, #4]
8004af6: 4413 add r3, r2
8004af8: 3304 adds r3, #4
8004afa: 60fb str r3, [r7, #12]
}
/* Stop Xfer */
ret = USB_EPStopXfer(hpcd->Instance, ep);
8004afc: 687b ldr r3, [r7, #4]
8004afe: 681b ldr r3, [r3, #0]
8004b00: 68f9 ldr r1, [r7, #12]
8004b02: 4618 mov r0, r3
8004b04: f004 f92e bl 8008d64 <USB_EPStopXfer>
8004b08: 4603 mov r3, r0
8004b0a: 72fb strb r3, [r7, #11]
return ret;
8004b0c: 7afb ldrb r3, [r7, #11]
}
8004b0e: 4618 mov r0, r3
8004b10: 3710 adds r7, #16
8004b12: 46bd mov sp, r7
8004b14: bd80 pop {r7, pc}
08004b16 <PCD_WriteEmptyTxFifo>:
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
8004b16: b580 push {r7, lr}
8004b18: b088 sub sp, #32
8004b1a: af00 add r7, sp, #0
8004b1c: 6078 str r0, [r7, #4]
8004b1e: 6039 str r1, [r7, #0]
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8004b20: 687b ldr r3, [r7, #4]
8004b22: 681b ldr r3, [r3, #0]
8004b24: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
8004b26: 697b ldr r3, [r7, #20]
8004b28: 613b str r3, [r7, #16]
USB_OTG_EPTypeDef *ep;
uint32_t len;
uint32_t len32b;
uint32_t fifoemptymsk;
ep = &hpcd->IN_ep[epnum];
8004b2a: 683a ldr r2, [r7, #0]
8004b2c: 4613 mov r3, r2
8004b2e: 00db lsls r3, r3, #3
8004b30: 4413 add r3, r2
8004b32: 009b lsls r3, r3, #2
8004b34: 3310 adds r3, #16
8004b36: 687a ldr r2, [r7, #4]
8004b38: 4413 add r3, r2
8004b3a: 3304 adds r3, #4
8004b3c: 60fb str r3, [r7, #12]
if (ep->xfer_count > ep->xfer_len)
8004b3e: 68fb ldr r3, [r7, #12]
8004b40: 695a ldr r2, [r3, #20]
8004b42: 68fb ldr r3, [r7, #12]
8004b44: 691b ldr r3, [r3, #16]
8004b46: 429a cmp r2, r3
8004b48: d901 bls.n 8004b4e <PCD_WriteEmptyTxFifo+0x38>
{
return HAL_ERROR;
8004b4a: 2301 movs r3, #1
8004b4c: e067 b.n 8004c1e <PCD_WriteEmptyTxFifo+0x108>
}
len = ep->xfer_len - ep->xfer_count;
8004b4e: 68fb ldr r3, [r7, #12]
8004b50: 691a ldr r2, [r3, #16]
8004b52: 68fb ldr r3, [r7, #12]
8004b54: 695b ldr r3, [r3, #20]
8004b56: 1ad3 subs r3, r2, r3
8004b58: 61fb str r3, [r7, #28]
if (len > ep->maxpacket)
8004b5a: 68fb ldr r3, [r7, #12]
8004b5c: 689b ldr r3, [r3, #8]
8004b5e: 69fa ldr r2, [r7, #28]
8004b60: 429a cmp r2, r3
8004b62: d902 bls.n 8004b6a <PCD_WriteEmptyTxFifo+0x54>
{
len = ep->maxpacket;
8004b64: 68fb ldr r3, [r7, #12]
8004b66: 689b ldr r3, [r3, #8]
8004b68: 61fb str r3, [r7, #28]
}
len32b = (len + 3U) / 4U;
8004b6a: 69fb ldr r3, [r7, #28]
8004b6c: 3303 adds r3, #3
8004b6e: 089b lsrs r3, r3, #2
8004b70: 61bb str r3, [r7, #24]
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
8004b72: e026 b.n 8004bc2 <PCD_WriteEmptyTxFifo+0xac>
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
8004b74: 68fb ldr r3, [r7, #12]
8004b76: 691a ldr r2, [r3, #16]
8004b78: 68fb ldr r3, [r7, #12]
8004b7a: 695b ldr r3, [r3, #20]
8004b7c: 1ad3 subs r3, r2, r3
8004b7e: 61fb str r3, [r7, #28]
if (len > ep->maxpacket)
8004b80: 68fb ldr r3, [r7, #12]
8004b82: 689b ldr r3, [r3, #8]
8004b84: 69fa ldr r2, [r7, #28]
8004b86: 429a cmp r2, r3
8004b88: d902 bls.n 8004b90 <PCD_WriteEmptyTxFifo+0x7a>
{
len = ep->maxpacket;
8004b8a: 68fb ldr r3, [r7, #12]
8004b8c: 689b ldr r3, [r3, #8]
8004b8e: 61fb str r3, [r7, #28]
}
len32b = (len + 3U) / 4U;
8004b90: 69fb ldr r3, [r7, #28]
8004b92: 3303 adds r3, #3
8004b94: 089b lsrs r3, r3, #2
8004b96: 61bb str r3, [r7, #24]
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len);
8004b98: 68fb ldr r3, [r7, #12]
8004b9a: 68d9 ldr r1, [r3, #12]
8004b9c: 683b ldr r3, [r7, #0]
8004b9e: b2da uxtb r2, r3
8004ba0: 69fb ldr r3, [r7, #28]
8004ba2: b29b uxth r3, r3
8004ba4: 6978 ldr r0, [r7, #20]
8004ba6: f004 f987 bl 8008eb8 <USB_WritePacket>
ep->xfer_buff += len;
8004baa: 68fb ldr r3, [r7, #12]
8004bac: 68da ldr r2, [r3, #12]
8004bae: 69fb ldr r3, [r7, #28]
8004bb0: 441a add r2, r3
8004bb2: 68fb ldr r3, [r7, #12]
8004bb4: 60da str r2, [r3, #12]
ep->xfer_count += len;
8004bb6: 68fb ldr r3, [r7, #12]
8004bb8: 695a ldr r2, [r3, #20]
8004bba: 69fb ldr r3, [r7, #28]
8004bbc: 441a add r2, r3
8004bbe: 68fb ldr r3, [r7, #12]
8004bc0: 615a str r2, [r3, #20]
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
8004bc2: 683b ldr r3, [r7, #0]
8004bc4: 015a lsls r2, r3, #5
8004bc6: 693b ldr r3, [r7, #16]
8004bc8: 4413 add r3, r2
8004bca: f503 6310 add.w r3, r3, #2304 @ 0x900
8004bce: 699b ldr r3, [r3, #24]
8004bd0: b29b uxth r3, r3
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
8004bd2: 69ba ldr r2, [r7, #24]
8004bd4: 429a cmp r2, r3
8004bd6: d809 bhi.n 8004bec <PCD_WriteEmptyTxFifo+0xd6>
8004bd8: 68fb ldr r3, [r7, #12]
8004bda: 695a ldr r2, [r3, #20]
8004bdc: 68fb ldr r3, [r7, #12]
8004bde: 691b ldr r3, [r3, #16]
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
8004be0: 429a cmp r2, r3
8004be2: d203 bcs.n 8004bec <PCD_WriteEmptyTxFifo+0xd6>
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
8004be4: 68fb ldr r3, [r7, #12]
8004be6: 691b ldr r3, [r3, #16]
8004be8: 2b00 cmp r3, #0
8004bea: d1c3 bne.n 8004b74 <PCD_WriteEmptyTxFifo+0x5e>
}
if (ep->xfer_len <= ep->xfer_count)
8004bec: 68fb ldr r3, [r7, #12]
8004bee: 691a ldr r2, [r3, #16]
8004bf0: 68fb ldr r3, [r7, #12]
8004bf2: 695b ldr r3, [r3, #20]
8004bf4: 429a cmp r2, r3
8004bf6: d811 bhi.n 8004c1c <PCD_WriteEmptyTxFifo+0x106>
{
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
8004bf8: 683b ldr r3, [r7, #0]
8004bfa: f003 030f and.w r3, r3, #15
8004bfe: 2201 movs r2, #1
8004c00: fa02 f303 lsl.w r3, r2, r3
8004c04: 60bb str r3, [r7, #8]
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
8004c06: 693b ldr r3, [r7, #16]
8004c08: f503 6300 add.w r3, r3, #2048 @ 0x800
8004c0c: 6b5a ldr r2, [r3, #52] @ 0x34
8004c0e: 68bb ldr r3, [r7, #8]
8004c10: 43db mvns r3, r3
8004c12: 6939 ldr r1, [r7, #16]
8004c14: f501 6100 add.w r1, r1, #2048 @ 0x800
8004c18: 4013 ands r3, r2
8004c1a: 634b str r3, [r1, #52] @ 0x34
}
return HAL_OK;
8004c1c: 2300 movs r3, #0
}
8004c1e: 4618 mov r0, r3
8004c20: 3720 adds r7, #32
8004c22: 46bd mov sp, r7
8004c24: bd80 pop {r7, pc}
...
08004c28 <PCD_EP_OutXfrComplete_int>:
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
8004c28: b580 push {r7, lr}
8004c2a: b086 sub sp, #24
8004c2c: af00 add r7, sp, #0
8004c2e: 6078 str r0, [r7, #4]
8004c30: 6039 str r1, [r7, #0]
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8004c32: 687b ldr r3, [r7, #4]
8004c34: 681b ldr r3, [r3, #0]
8004c36: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
8004c38: 697b ldr r3, [r7, #20]
8004c3a: 613b str r3, [r7, #16]
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
8004c3c: 697b ldr r3, [r7, #20]
8004c3e: 333c adds r3, #60 @ 0x3c
8004c40: 3304 adds r3, #4
8004c42: 681b ldr r3, [r3, #0]
8004c44: 60fb str r3, [r7, #12]
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
8004c46: 683b ldr r3, [r7, #0]
8004c48: 015a lsls r2, r3, #5
8004c4a: 693b ldr r3, [r7, #16]
8004c4c: 4413 add r3, r2
8004c4e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004c52: 689b ldr r3, [r3, #8]
8004c54: 60bb str r3, [r7, #8]
if (gSNPSiD == USB_OTG_CORE_ID_310A)
8004c56: 68fb ldr r3, [r7, #12]
8004c58: 4a19 ldr r2, [pc, #100] @ (8004cc0 <PCD_EP_OutXfrComplete_int+0x98>)
8004c5a: 4293 cmp r3, r2
8004c5c: d124 bne.n 8004ca8 <PCD_EP_OutXfrComplete_int+0x80>
{
/* StupPktRcvd = 1 this is a setup packet */
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
8004c5e: 68bb ldr r3, [r7, #8]
8004c60: f403 4300 and.w r3, r3, #32768 @ 0x8000
8004c64: 2b00 cmp r3, #0
8004c66: d00a beq.n 8004c7e <PCD_EP_OutXfrComplete_int+0x56>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
8004c68: 683b ldr r3, [r7, #0]
8004c6a: 015a lsls r2, r3, #5
8004c6c: 693b ldr r3, [r7, #16]
8004c6e: 4413 add r3, r2
8004c70: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004c74: 461a mov r2, r3
8004c76: f44f 4300 mov.w r3, #32768 @ 0x8000
8004c7a: 6093 str r3, [r2, #8]
8004c7c: e01a b.n 8004cb4 <PCD_EP_OutXfrComplete_int+0x8c>
}
else
{
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
8004c7e: 68bb ldr r3, [r7, #8]
8004c80: f003 0320 and.w r3, r3, #32
8004c84: 2b00 cmp r3, #0
8004c86: d008 beq.n 8004c9a <PCD_EP_OutXfrComplete_int+0x72>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
8004c88: 683b ldr r3, [r7, #0]
8004c8a: 015a lsls r2, r3, #5
8004c8c: 693b ldr r3, [r7, #16]
8004c8e: 4413 add r3, r2
8004c90: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004c94: 461a mov r2, r3
8004c96: 2320 movs r3, #32
8004c98: 6093 str r3, [r2, #8]
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
8004c9a: 683b ldr r3, [r7, #0]
8004c9c: b2db uxtb r3, r3
8004c9e: 4619 mov r1, r3
8004ca0: 6878 ldr r0, [r7, #4]
8004ca2: f006 fa4d bl 800b140 <HAL_PCD_DataOutStageCallback>
8004ca6: e005 b.n 8004cb4 <PCD_EP_OutXfrComplete_int+0x8c>
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
8004ca8: 683b ldr r3, [r7, #0]
8004caa: b2db uxtb r3, r3
8004cac: 4619 mov r1, r3
8004cae: 6878 ldr r0, [r7, #4]
8004cb0: f006 fa46 bl 800b140 <HAL_PCD_DataOutStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
return HAL_OK;
8004cb4: 2300 movs r3, #0
}
8004cb6: 4618 mov r0, r3
8004cb8: 3718 adds r7, #24
8004cba: 46bd mov sp, r7
8004cbc: bd80 pop {r7, pc}
8004cbe: bf00 nop
8004cc0: 4f54310a .word 0x4f54310a
08004cc4 <PCD_EP_OutSetupPacket_int>:
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
8004cc4: b580 push {r7, lr}
8004cc6: b086 sub sp, #24
8004cc8: af00 add r7, sp, #0
8004cca: 6078 str r0, [r7, #4]
8004ccc: 6039 str r1, [r7, #0]
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8004cce: 687b ldr r3, [r7, #4]
8004cd0: 681b ldr r3, [r3, #0]
8004cd2: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
8004cd4: 697b ldr r3, [r7, #20]
8004cd6: 613b str r3, [r7, #16]
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
8004cd8: 697b ldr r3, [r7, #20]
8004cda: 333c adds r3, #60 @ 0x3c
8004cdc: 3304 adds r3, #4
8004cde: 681b ldr r3, [r3, #0]
8004ce0: 60fb str r3, [r7, #12]
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
8004ce2: 683b ldr r3, [r7, #0]
8004ce4: 015a lsls r2, r3, #5
8004ce6: 693b ldr r3, [r7, #16]
8004ce8: 4413 add r3, r2
8004cea: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004cee: 689b ldr r3, [r3, #8]
8004cf0: 60bb str r3, [r7, #8]
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
8004cf2: 68fb ldr r3, [r7, #12]
8004cf4: 4a0c ldr r2, [pc, #48] @ (8004d28 <PCD_EP_OutSetupPacket_int+0x64>)
8004cf6: 4293 cmp r3, r2
8004cf8: d90e bls.n 8004d18 <PCD_EP_OutSetupPacket_int+0x54>
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
8004cfa: 68bb ldr r3, [r7, #8]
8004cfc: f403 4300 and.w r3, r3, #32768 @ 0x8000
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
8004d00: 2b00 cmp r3, #0
8004d02: d009 beq.n 8004d18 <PCD_EP_OutSetupPacket_int+0x54>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
8004d04: 683b ldr r3, [r7, #0]
8004d06: 015a lsls r2, r3, #5
8004d08: 693b ldr r3, [r7, #16]
8004d0a: 4413 add r3, r2
8004d0c: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004d10: 461a mov r2, r3
8004d12: f44f 4300 mov.w r3, #32768 @ 0x8000
8004d16: 6093 str r3, [r2, #8]
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
8004d18: 6878 ldr r0, [r7, #4]
8004d1a: f006 f9ff bl 800b11c <HAL_PCD_SetupStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return HAL_OK;
8004d1e: 2300 movs r3, #0
}
8004d20: 4618 mov r0, r3
8004d22: 3718 adds r7, #24
8004d24: 46bd mov sp, r7
8004d26: bd80 pop {r7, pc}
8004d28: 4f54300a .word 0x4f54300a
08004d2c <HAL_PCDEx_SetTxFiFo>:
* @param fifo The number of Tx fifo
* @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
8004d2c: b480 push {r7}
8004d2e: b085 sub sp, #20
8004d30: af00 add r7, sp, #0
8004d32: 6078 str r0, [r7, #4]
8004d34: 460b mov r3, r1
8004d36: 70fb strb r3, [r7, #3]
8004d38: 4613 mov r3, r2
8004d3a: 803b strh r3, [r7, #0]
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
8004d3c: 687b ldr r3, [r7, #4]
8004d3e: 681b ldr r3, [r3, #0]
8004d40: 6a5b ldr r3, [r3, #36] @ 0x24
8004d42: 60bb str r3, [r7, #8]
if (fifo == 0U)
8004d44: 78fb ldrb r3, [r7, #3]
8004d46: 2b00 cmp r3, #0
8004d48: d107 bne.n 8004d5a <HAL_PCDEx_SetTxFiFo+0x2e>
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
8004d4a: 883b ldrh r3, [r7, #0]
8004d4c: 0419 lsls r1, r3, #16
8004d4e: 687b ldr r3, [r7, #4]
8004d50: 681b ldr r3, [r3, #0]
8004d52: 68ba ldr r2, [r7, #8]
8004d54: 430a orrs r2, r1
8004d56: 629a str r2, [r3, #40] @ 0x28
8004d58: e028 b.n 8004dac <HAL_PCDEx_SetTxFiFo+0x80>
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
8004d5a: 687b ldr r3, [r7, #4]
8004d5c: 681b ldr r3, [r3, #0]
8004d5e: 6a9b ldr r3, [r3, #40] @ 0x28
8004d60: 0c1b lsrs r3, r3, #16
8004d62: 68ba ldr r2, [r7, #8]
8004d64: 4413 add r3, r2
8004d66: 60bb str r3, [r7, #8]
for (i = 0U; i < (fifo - 1U); i++)
8004d68: 2300 movs r3, #0
8004d6a: 73fb strb r3, [r7, #15]
8004d6c: e00d b.n 8004d8a <HAL_PCDEx_SetTxFiFo+0x5e>
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
8004d6e: 687b ldr r3, [r7, #4]
8004d70: 681a ldr r2, [r3, #0]
8004d72: 7bfb ldrb r3, [r7, #15]
8004d74: 3340 adds r3, #64 @ 0x40
8004d76: 009b lsls r3, r3, #2
8004d78: 4413 add r3, r2
8004d7a: 685b ldr r3, [r3, #4]
8004d7c: 0c1b lsrs r3, r3, #16
8004d7e: 68ba ldr r2, [r7, #8]
8004d80: 4413 add r3, r2
8004d82: 60bb str r3, [r7, #8]
for (i = 0U; i < (fifo - 1U); i++)
8004d84: 7bfb ldrb r3, [r7, #15]
8004d86: 3301 adds r3, #1
8004d88: 73fb strb r3, [r7, #15]
8004d8a: 7bfa ldrb r2, [r7, #15]
8004d8c: 78fb ldrb r3, [r7, #3]
8004d8e: 3b01 subs r3, #1
8004d90: 429a cmp r2, r3
8004d92: d3ec bcc.n 8004d6e <HAL_PCDEx_SetTxFiFo+0x42>
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
8004d94: 883b ldrh r3, [r7, #0]
8004d96: 0418 lsls r0, r3, #16
8004d98: 687b ldr r3, [r7, #4]
8004d9a: 6819 ldr r1, [r3, #0]
8004d9c: 78fb ldrb r3, [r7, #3]
8004d9e: 3b01 subs r3, #1
8004da0: 68ba ldr r2, [r7, #8]
8004da2: 4302 orrs r2, r0
8004da4: 3340 adds r3, #64 @ 0x40
8004da6: 009b lsls r3, r3, #2
8004da8: 440b add r3, r1
8004daa: 605a str r2, [r3, #4]
}
return HAL_OK;
8004dac: 2300 movs r3, #0
}
8004dae: 4618 mov r0, r3
8004db0: 3714 adds r7, #20
8004db2: 46bd mov sp, r7
8004db4: f85d 7b04 ldr.w r7, [sp], #4
8004db8: 4770 bx lr
08004dba <HAL_PCDEx_SetRxFiFo>:
* @param hpcd PCD handle
* @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
8004dba: b480 push {r7}
8004dbc: b083 sub sp, #12
8004dbe: af00 add r7, sp, #0
8004dc0: 6078 str r0, [r7, #4]
8004dc2: 460b mov r3, r1
8004dc4: 807b strh r3, [r7, #2]
hpcd->Instance->GRXFSIZ = size;
8004dc6: 687b ldr r3, [r7, #4]
8004dc8: 681b ldr r3, [r3, #0]
8004dca: 887a ldrh r2, [r7, #2]
8004dcc: 625a str r2, [r3, #36] @ 0x24
return HAL_OK;
8004dce: 2300 movs r3, #0
}
8004dd0: 4618 mov r0, r3
8004dd2: 370c adds r7, #12
8004dd4: 46bd mov sp, r7
8004dd6: f85d 7b04 ldr.w r7, [sp], #4
8004dda: 4770 bx lr
08004ddc <HAL_PCDEx_ActivateLPM>:
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
8004ddc: b480 push {r7}
8004dde: b085 sub sp, #20
8004de0: af00 add r7, sp, #0
8004de2: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8004de4: 687b ldr r3, [r7, #4]
8004de6: 681b ldr r3, [r3, #0]
8004de8: 60fb str r3, [r7, #12]
hpcd->lpm_active = 1U;
8004dea: 687b ldr r3, [r7, #4]
8004dec: 2201 movs r2, #1
8004dee: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
hpcd->LPM_State = LPM_L0;
8004df2: 687b ldr r3, [r7, #4]
8004df4: 2200 movs r2, #0
8004df6: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
8004dfa: 68fb ldr r3, [r7, #12]
8004dfc: 699b ldr r3, [r3, #24]
8004dfe: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
8004e02: 68fb ldr r3, [r7, #12]
8004e04: 619a str r2, [r3, #24]
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
8004e06: 68fb ldr r3, [r7, #12]
8004e08: 6d5b ldr r3, [r3, #84] @ 0x54
8004e0a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004e0e: f043 0303 orr.w r3, r3, #3
8004e12: 68fa ldr r2, [r7, #12]
8004e14: 6553 str r3, [r2, #84] @ 0x54
return HAL_OK;
8004e16: 2300 movs r3, #0
}
8004e18: 4618 mov r0, r3
8004e1a: 3714 adds r7, #20
8004e1c: 46bd mov sp, r7
8004e1e: f85d 7b04 ldr.w r7, [sp], #4
8004e22: 4770 bx lr
08004e24 <HAL_PWR_EnableBkUpAccess>:
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
* back-up domain.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
8004e24: b480 push {r7}
8004e26: af00 add r7, sp, #0
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8004e28: 4b05 ldr r3, [pc, #20] @ (8004e40 <HAL_PWR_EnableBkUpAccess+0x1c>)
8004e2a: 681b ldr r3, [r3, #0]
8004e2c: 4a04 ldr r2, [pc, #16] @ (8004e40 <HAL_PWR_EnableBkUpAccess+0x1c>)
8004e2e: f443 7380 orr.w r3, r3, #256 @ 0x100
8004e32: 6013 str r3, [r2, #0]
}
8004e34: bf00 nop
8004e36: 46bd mov sp, r7
8004e38: f85d 7b04 ldr.w r7, [sp], #4
8004e3c: 4770 bx lr
8004e3e: bf00 nop
8004e40: 40007000 .word 0x40007000
08004e44 <HAL_PWREx_GetVoltageRange>:
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
8004e44: b480 push {r7}
8004e46: af00 add r7, sp, #0
else
{
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
}
#else
return (PWR->CR1 & PWR_CR1_VOS);
8004e48: 4b04 ldr r3, [pc, #16] @ (8004e5c <HAL_PWREx_GetVoltageRange+0x18>)
8004e4a: 681b ldr r3, [r3, #0]
8004e4c: f403 63c0 and.w r3, r3, #1536 @ 0x600
#endif
}
8004e50: 4618 mov r0, r3
8004e52: 46bd mov sp, r7
8004e54: f85d 7b04 ldr.w r7, [sp], #4
8004e58: 4770 bx lr
8004e5a: bf00 nop
8004e5c: 40007000 .word 0x40007000
08004e60 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8004e60: b480 push {r7}
8004e62: b085 sub sp, #20
8004e64: af00 add r7, sp, #0
8004e66: 6078 str r0, [r7, #4]
}
#else
/* If Set Range 1 */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8004e68: 687b ldr r3, [r7, #4]
8004e6a: f5b3 7f00 cmp.w r3, #512 @ 0x200
8004e6e: d130 bne.n 8004ed2 <HAL_PWREx_ControlVoltageScaling+0x72>
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
8004e70: 4b23 ldr r3, [pc, #140] @ (8004f00 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8004e72: 681b ldr r3, [r3, #0]
8004e74: f403 63c0 and.w r3, r3, #1536 @ 0x600
8004e78: f5b3 7f00 cmp.w r3, #512 @ 0x200
8004e7c: d038 beq.n 8004ef0 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8004e7e: 4b20 ldr r3, [pc, #128] @ (8004f00 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8004e80: 681b ldr r3, [r3, #0]
8004e82: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8004e86: 4a1e ldr r2, [pc, #120] @ (8004f00 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8004e88: f443 7300 orr.w r3, r3, #512 @ 0x200
8004e8c: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8004e8e: 4b1d ldr r3, [pc, #116] @ (8004f04 <HAL_PWREx_ControlVoltageScaling+0xa4>)
8004e90: 681b ldr r3, [r3, #0]
8004e92: 2232 movs r2, #50 @ 0x32
8004e94: fb02 f303 mul.w r3, r2, r3
8004e98: 4a1b ldr r2, [pc, #108] @ (8004f08 <HAL_PWREx_ControlVoltageScaling+0xa8>)
8004e9a: fba2 2303 umull r2, r3, r2, r3
8004e9e: 0c9b lsrs r3, r3, #18
8004ea0: 3301 adds r3, #1
8004ea2: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8004ea4: e002 b.n 8004eac <HAL_PWREx_ControlVoltageScaling+0x4c>
{
wait_loop_index--;
8004ea6: 68fb ldr r3, [r7, #12]
8004ea8: 3b01 subs r3, #1
8004eaa: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8004eac: 4b14 ldr r3, [pc, #80] @ (8004f00 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8004eae: 695b ldr r3, [r3, #20]
8004eb0: f403 6380 and.w r3, r3, #1024 @ 0x400
8004eb4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004eb8: d102 bne.n 8004ec0 <HAL_PWREx_ControlVoltageScaling+0x60>
8004eba: 68fb ldr r3, [r7, #12]
8004ebc: 2b00 cmp r3, #0
8004ebe: d1f2 bne.n 8004ea6 <HAL_PWREx_ControlVoltageScaling+0x46>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8004ec0: 4b0f ldr r3, [pc, #60] @ (8004f00 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8004ec2: 695b ldr r3, [r3, #20]
8004ec4: f403 6380 and.w r3, r3, #1024 @ 0x400
8004ec8: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004ecc: d110 bne.n 8004ef0 <HAL_PWREx_ControlVoltageScaling+0x90>
{
return HAL_TIMEOUT;
8004ece: 2303 movs r3, #3
8004ed0: e00f b.n 8004ef2 <HAL_PWREx_ControlVoltageScaling+0x92>
}
}
}
else
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
8004ed2: 4b0b ldr r3, [pc, #44] @ (8004f00 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8004ed4: 681b ldr r3, [r3, #0]
8004ed6: f403 63c0 and.w r3, r3, #1536 @ 0x600
8004eda: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004ede: d007 beq.n 8004ef0 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
8004ee0: 4b07 ldr r3, [pc, #28] @ (8004f00 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8004ee2: 681b ldr r3, [r3, #0]
8004ee4: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8004ee8: 4a05 ldr r2, [pc, #20] @ (8004f00 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8004eea: f443 6380 orr.w r3, r3, #1024 @ 0x400
8004eee: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
}
}
#endif
return HAL_OK;
8004ef0: 2300 movs r3, #0
}
8004ef2: 4618 mov r0, r3
8004ef4: 3714 adds r7, #20
8004ef6: 46bd mov sp, r7
8004ef8: f85d 7b04 ldr.w r7, [sp], #4
8004efc: 4770 bx lr
8004efe: bf00 nop
8004f00: 40007000 .word 0x40007000
8004f04: 20000000 .word 0x20000000
8004f08: 431bde83 .word 0x431bde83
08004f0c <HAL_PWREx_EnableVddUSB>:
* @brief Enable VDDUSB supply.
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
* @retval None
*/
void HAL_PWREx_EnableVddUSB(void)
{
8004f0c: b480 push {r7}
8004f0e: af00 add r7, sp, #0
SET_BIT(PWR->CR2, PWR_CR2_USV);
8004f10: 4b05 ldr r3, [pc, #20] @ (8004f28 <HAL_PWREx_EnableVddUSB+0x1c>)
8004f12: 685b ldr r3, [r3, #4]
8004f14: 4a04 ldr r2, [pc, #16] @ (8004f28 <HAL_PWREx_EnableVddUSB+0x1c>)
8004f16: f443 6380 orr.w r3, r3, #1024 @ 0x400
8004f1a: 6053 str r3, [r2, #4]
}
8004f1c: bf00 nop
8004f1e: 46bd mov sp, r7
8004f20: f85d 7b04 ldr.w r7, [sp], #4
8004f24: 4770 bx lr
8004f26: bf00 nop
8004f28: 40007000 .word 0x40007000
08004f2c <HAL_QSPI_Init>:
* in the QSPI_InitTypeDef and initialize the associated handle.
* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
{
8004f2c: b580 push {r7, lr}
8004f2e: b086 sub sp, #24
8004f30: af02 add r7, sp, #8
8004f32: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
8004f34: f7fd f8ee bl 8002114 <HAL_GetTick>
8004f38: 60f8 str r0, [r7, #12]
/* Check the QSPI handle allocation */
if(hqspi == NULL)
8004f3a: 687b ldr r3, [r7, #4]
8004f3c: 2b00 cmp r3, #0
8004f3e: d101 bne.n 8004f44 <HAL_QSPI_Init+0x18>
{
return HAL_ERROR;
8004f40: 2301 movs r3, #1
8004f42: e063 b.n 800500c <HAL_QSPI_Init+0xe0>
{
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
}
#endif
if(hqspi->State == HAL_QSPI_STATE_RESET)
8004f44: 687b ldr r3, [r7, #4]
8004f46: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8004f4a: b2db uxtb r3, r3
8004f4c: 2b00 cmp r3, #0
8004f4e: d10b bne.n 8004f68 <HAL_QSPI_Init+0x3c>
{
/* Allocate lock resource and initialize it */
hqspi->Lock = HAL_UNLOCKED;
8004f50: 687b ldr r3, [r7, #4]
8004f52: 2200 movs r2, #0
8004f54: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* Init the low level hardware */
hqspi->MspInitCallback(hqspi);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_QSPI_MspInit(hqspi);
8004f58: 6878 ldr r0, [r7, #4]
8004f5a: f7fc fd61 bl 8001a20 <HAL_QSPI_MspInit>
#endif
/* Configure the default timeout for the QSPI memory access */
HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
8004f5e: f241 3188 movw r1, #5000 @ 0x1388
8004f62: 6878 ldr r0, [r7, #4]
8004f64: f000 f858 bl 8005018 <HAL_QSPI_SetTimeout>
}
/* Configure QSPI FIFO Threshold */
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
8004f68: 687b ldr r3, [r7, #4]
8004f6a: 681b ldr r3, [r3, #0]
8004f6c: 681b ldr r3, [r3, #0]
8004f6e: f423 6170 bic.w r1, r3, #3840 @ 0xf00
8004f72: 687b ldr r3, [r7, #4]
8004f74: 689b ldr r3, [r3, #8]
8004f76: 3b01 subs r3, #1
8004f78: 021a lsls r2, r3, #8
8004f7a: 687b ldr r3, [r7, #4]
8004f7c: 681b ldr r3, [r3, #0]
8004f7e: 430a orrs r2, r1
8004f80: 601a str r2, [r3, #0]
((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
8004f82: 687b ldr r3, [r7, #4]
8004f84: 6c1b ldr r3, [r3, #64] @ 0x40
8004f86: 9300 str r3, [sp, #0]
8004f88: 68fb ldr r3, [r7, #12]
8004f8a: 2200 movs r2, #0
8004f8c: 2120 movs r1, #32
8004f8e: 6878 ldr r0, [r7, #4]
8004f90: f000 f850 bl 8005034 <QSPI_WaitFlagStateUntilTimeout>
8004f94: 4603 mov r3, r0
8004f96: 72fb strb r3, [r7, #11]
if(status == HAL_OK)
8004f98: 7afb ldrb r3, [r7, #11]
8004f9a: 2b00 cmp r3, #0
8004f9c: d131 bne.n 8005002 <HAL_QSPI_Init+0xd6>
#if defined(QUADSPI_CR_DFM)
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
#else
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
8004f9e: 687b ldr r3, [r7, #4]
8004fa0: 681b ldr r3, [r3, #0]
8004fa2: 681b ldr r3, [r3, #0]
8004fa4: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000
8004fa8: f023 0310 bic.w r3, r3, #16
8004fac: 687a ldr r2, [r7, #4]
8004fae: 6852 ldr r2, [r2, #4]
8004fb0: 0611 lsls r1, r2, #24
8004fb2: 687a ldr r2, [r7, #4]
8004fb4: 68d2 ldr r2, [r2, #12]
8004fb6: 4311 orrs r1, r2
8004fb8: 687a ldr r2, [r7, #4]
8004fba: 6812 ldr r2, [r2, #0]
8004fbc: 430b orrs r3, r1
8004fbe: 6013 str r3, [r2, #0]
((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
hqspi->Init.SampleShifting));
#endif
/* Configure QSPI Flash Size, CS High Time and Clock Mode */
MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
8004fc0: 687b ldr r3, [r7, #4]
8004fc2: 681b ldr r3, [r3, #0]
8004fc4: 685a ldr r2, [r3, #4]
8004fc6: 4b13 ldr r3, [pc, #76] @ (8005014 <HAL_QSPI_Init+0xe8>)
8004fc8: 4013 ands r3, r2
8004fca: 687a ldr r2, [r7, #4]
8004fcc: 6912 ldr r2, [r2, #16]
8004fce: 0411 lsls r1, r2, #16
8004fd0: 687a ldr r2, [r7, #4]
8004fd2: 6952 ldr r2, [r2, #20]
8004fd4: 4311 orrs r1, r2
8004fd6: 687a ldr r2, [r7, #4]
8004fd8: 6992 ldr r2, [r2, #24]
8004fda: 4311 orrs r1, r2
8004fdc: 687a ldr r2, [r7, #4]
8004fde: 6812 ldr r2, [r2, #0]
8004fe0: 430b orrs r3, r1
8004fe2: 6053 str r3, [r2, #4]
((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
/* Enable the QSPI peripheral */
__HAL_QSPI_ENABLE(hqspi);
8004fe4: 687b ldr r3, [r7, #4]
8004fe6: 681b ldr r3, [r3, #0]
8004fe8: 681a ldr r2, [r3, #0]
8004fea: 687b ldr r3, [r7, #4]
8004fec: 681b ldr r3, [r3, #0]
8004fee: f042 0201 orr.w r2, r2, #1
8004ff2: 601a str r2, [r3, #0]
/* Set QSPI error code to none */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
8004ff4: 687b ldr r3, [r7, #4]
8004ff6: 2200 movs r2, #0
8004ff8: 63da str r2, [r3, #60] @ 0x3c
/* Initialize the QSPI state */
hqspi->State = HAL_QSPI_STATE_READY;
8004ffa: 687b ldr r3, [r7, #4]
8004ffc: 2201 movs r2, #1
8004ffe: f883 2039 strb.w r2, [r3, #57] @ 0x39
}
/* Release Lock */
__HAL_UNLOCK(hqspi);
8005002: 687b ldr r3, [r7, #4]
8005004: 2200 movs r2, #0
8005006: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* Return function status */
return status;
800500a: 7afb ldrb r3, [r7, #11]
}
800500c: 4618 mov r0, r3
800500e: 3710 adds r7, #16
8005010: 46bd mov sp, r7
8005012: bd80 pop {r7, pc}
8005014: ffe0f8fe .word 0xffe0f8fe
08005018 <HAL_QSPI_SetTimeout>:
* @param hqspi QSPI handle.
* @param Timeout Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
{
8005018: b480 push {r7}
800501a: b083 sub sp, #12
800501c: af00 add r7, sp, #0
800501e: 6078 str r0, [r7, #4]
8005020: 6039 str r1, [r7, #0]
hqspi->Timeout = Timeout;
8005022: 687b ldr r3, [r7, #4]
8005024: 683a ldr r2, [r7, #0]
8005026: 641a str r2, [r3, #64] @ 0x40
}
8005028: bf00 nop
800502a: 370c adds r7, #12
800502c: 46bd mov sp, r7
800502e: f85d 7b04 ldr.w r7, [sp], #4
8005032: 4770 bx lr
08005034 <QSPI_WaitFlagStateUntilTimeout>:
* @param Timeout Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
8005034: b580 push {r7, lr}
8005036: b084 sub sp, #16
8005038: af00 add r7, sp, #0
800503a: 60f8 str r0, [r7, #12]
800503c: 60b9 str r1, [r7, #8]
800503e: 603b str r3, [r7, #0]
8005040: 4613 mov r3, r2
8005042: 71fb strb r3, [r7, #7]
/* Wait until flag is in expected state */
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
8005044: e01a b.n 800507c <QSPI_WaitFlagStateUntilTimeout+0x48>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8005046: 69bb ldr r3, [r7, #24]
8005048: f1b3 3fff cmp.w r3, #4294967295
800504c: d016 beq.n 800507c <QSPI_WaitFlagStateUntilTimeout+0x48>
{
if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800504e: f7fd f861 bl 8002114 <HAL_GetTick>
8005052: 4602 mov r2, r0
8005054: 683b ldr r3, [r7, #0]
8005056: 1ad3 subs r3, r2, r3
8005058: 69ba ldr r2, [r7, #24]
800505a: 429a cmp r2, r3
800505c: d302 bcc.n 8005064 <QSPI_WaitFlagStateUntilTimeout+0x30>
800505e: 69bb ldr r3, [r7, #24]
8005060: 2b00 cmp r3, #0
8005062: d10b bne.n 800507c <QSPI_WaitFlagStateUntilTimeout+0x48>
{
hqspi->State = HAL_QSPI_STATE_ERROR;
8005064: 68fb ldr r3, [r7, #12]
8005066: 2204 movs r2, #4
8005068: f883 2039 strb.w r2, [r3, #57] @ 0x39
hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
800506c: 68fb ldr r3, [r7, #12]
800506e: 6bdb ldr r3, [r3, #60] @ 0x3c
8005070: f043 0201 orr.w r2, r3, #1
8005074: 68fb ldr r3, [r7, #12]
8005076: 63da str r2, [r3, #60] @ 0x3c
return HAL_ERROR;
8005078: 2301 movs r3, #1
800507a: e00e b.n 800509a <QSPI_WaitFlagStateUntilTimeout+0x66>
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
800507c: 68fb ldr r3, [r7, #12]
800507e: 681b ldr r3, [r3, #0]
8005080: 689a ldr r2, [r3, #8]
8005082: 68bb ldr r3, [r7, #8]
8005084: 4013 ands r3, r2
8005086: 2b00 cmp r3, #0
8005088: bf14 ite ne
800508a: 2301 movne r3, #1
800508c: 2300 moveq r3, #0
800508e: b2db uxtb r3, r3
8005090: 461a mov r2, r3
8005092: 79fb ldrb r3, [r7, #7]
8005094: 429a cmp r2, r3
8005096: d1d6 bne.n 8005046 <QSPI_WaitFlagStateUntilTimeout+0x12>
}
}
}
return HAL_OK;
8005098: 2300 movs r3, #0
}
800509a: 4618 mov r0, r3
800509c: 3710 adds r7, #16
800509e: 46bd mov sp, r7
80050a0: bd80 pop {r7, pc}
...
080050a4 <HAL_RCC_OscConfig>:
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80050a4: b580 push {r7, lr}
80050a6: b088 sub sp, #32
80050a8: af00 add r7, sp, #0
80050aa: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
80050ac: 687b ldr r3, [r7, #4]
80050ae: 2b00 cmp r3, #0
80050b0: d101 bne.n 80050b6 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80050b2: 2301 movs r3, #1
80050b4: e3ca b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
80050b6: 4b97 ldr r3, [pc, #604] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80050b8: 689b ldr r3, [r3, #8]
80050ba: f003 030c and.w r3, r3, #12
80050be: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
80050c0: 4b94 ldr r3, [pc, #592] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80050c2: 68db ldr r3, [r3, #12]
80050c4: f003 0303 and.w r3, r3, #3
80050c8: 617b str r3, [r7, #20]
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
80050ca: 687b ldr r3, [r7, #4]
80050cc: 681b ldr r3, [r3, #0]
80050ce: f003 0310 and.w r3, r3, #16
80050d2: 2b00 cmp r3, #0
80050d4: f000 80e4 beq.w 80052a0 <HAL_RCC_OscConfig+0x1fc>
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
80050d8: 69bb ldr r3, [r7, #24]
80050da: 2b00 cmp r3, #0
80050dc: d007 beq.n 80050ee <HAL_RCC_OscConfig+0x4a>
80050de: 69bb ldr r3, [r7, #24]
80050e0: 2b0c cmp r3, #12
80050e2: f040 808b bne.w 80051fc <HAL_RCC_OscConfig+0x158>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
80050e6: 697b ldr r3, [r7, #20]
80050e8: 2b01 cmp r3, #1
80050ea: f040 8087 bne.w 80051fc <HAL_RCC_OscConfig+0x158>
{
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
80050ee: 4b89 ldr r3, [pc, #548] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80050f0: 681b ldr r3, [r3, #0]
80050f2: f003 0302 and.w r3, r3, #2
80050f6: 2b00 cmp r3, #0
80050f8: d005 beq.n 8005106 <HAL_RCC_OscConfig+0x62>
80050fa: 687b ldr r3, [r7, #4]
80050fc: 699b ldr r3, [r3, #24]
80050fe: 2b00 cmp r3, #0
8005100: d101 bne.n 8005106 <HAL_RCC_OscConfig+0x62>
{
return HAL_ERROR;
8005102: 2301 movs r3, #1
8005104: e3a2 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
else
{
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
8005106: 687b ldr r3, [r7, #4]
8005108: 6a1a ldr r2, [r3, #32]
800510a: 4b82 ldr r3, [pc, #520] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800510c: 681b ldr r3, [r3, #0]
800510e: f003 0308 and.w r3, r3, #8
8005112: 2b00 cmp r3, #0
8005114: d004 beq.n 8005120 <HAL_RCC_OscConfig+0x7c>
8005116: 4b7f ldr r3, [pc, #508] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005118: 681b ldr r3, [r3, #0]
800511a: f003 03f0 and.w r3, r3, #240 @ 0xf0
800511e: e005 b.n 800512c <HAL_RCC_OscConfig+0x88>
8005120: 4b7c ldr r3, [pc, #496] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005122: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8005126: 091b lsrs r3, r3, #4
8005128: f003 03f0 and.w r3, r3, #240 @ 0xf0
800512c: 4293 cmp r3, r2
800512e: d223 bcs.n 8005178 <HAL_RCC_OscConfig+0xd4>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8005130: 687b ldr r3, [r7, #4]
8005132: 6a1b ldr r3, [r3, #32]
8005134: 4618 mov r0, r3
8005136: f000 fd55 bl 8005be4 <RCC_SetFlashLatencyFromMSIRange>
800513a: 4603 mov r3, r0
800513c: 2b00 cmp r3, #0
800513e: d001 beq.n 8005144 <HAL_RCC_OscConfig+0xa0>
{
return HAL_ERROR;
8005140: 2301 movs r3, #1
8005142: e383 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8005144: 4b73 ldr r3, [pc, #460] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005146: 681b ldr r3, [r3, #0]
8005148: 4a72 ldr r2, [pc, #456] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800514a: f043 0308 orr.w r3, r3, #8
800514e: 6013 str r3, [r2, #0]
8005150: 4b70 ldr r3, [pc, #448] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005152: 681b ldr r3, [r3, #0]
8005154: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8005158: 687b ldr r3, [r7, #4]
800515a: 6a1b ldr r3, [r3, #32]
800515c: 496d ldr r1, [pc, #436] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800515e: 4313 orrs r3, r2
8005160: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8005162: 4b6c ldr r3, [pc, #432] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005164: 685b ldr r3, [r3, #4]
8005166: f423 427f bic.w r2, r3, #65280 @ 0xff00
800516a: 687b ldr r3, [r7, #4]
800516c: 69db ldr r3, [r3, #28]
800516e: 021b lsls r3, r3, #8
8005170: 4968 ldr r1, [pc, #416] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005172: 4313 orrs r3, r2
8005174: 604b str r3, [r1, #4]
8005176: e025 b.n 80051c4 <HAL_RCC_OscConfig+0x120>
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8005178: 4b66 ldr r3, [pc, #408] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800517a: 681b ldr r3, [r3, #0]
800517c: 4a65 ldr r2, [pc, #404] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800517e: f043 0308 orr.w r3, r3, #8
8005182: 6013 str r3, [r2, #0]
8005184: 4b63 ldr r3, [pc, #396] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005186: 681b ldr r3, [r3, #0]
8005188: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800518c: 687b ldr r3, [r7, #4]
800518e: 6a1b ldr r3, [r3, #32]
8005190: 4960 ldr r1, [pc, #384] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005192: 4313 orrs r3, r2
8005194: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8005196: 4b5f ldr r3, [pc, #380] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005198: 685b ldr r3, [r3, #4]
800519a: f423 427f bic.w r2, r3, #65280 @ 0xff00
800519e: 687b ldr r3, [r7, #4]
80051a0: 69db ldr r3, [r3, #28]
80051a2: 021b lsls r3, r3, #8
80051a4: 495b ldr r1, [pc, #364] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80051a6: 4313 orrs r3, r2
80051a8: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
/* Only possible when MSI is the System clock source */
if(sysclk_source == RCC_CFGR_SWS_MSI)
80051aa: 69bb ldr r3, [r7, #24]
80051ac: 2b00 cmp r3, #0
80051ae: d109 bne.n 80051c4 <HAL_RCC_OscConfig+0x120>
{
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
80051b0: 687b ldr r3, [r7, #4]
80051b2: 6a1b ldr r3, [r3, #32]
80051b4: 4618 mov r0, r3
80051b6: f000 fd15 bl 8005be4 <RCC_SetFlashLatencyFromMSIRange>
80051ba: 4603 mov r3, r0
80051bc: 2b00 cmp r3, #0
80051be: d001 beq.n 80051c4 <HAL_RCC_OscConfig+0x120>
{
return HAL_ERROR;
80051c0: 2301 movs r3, #1
80051c2: e343 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
80051c4: f000 fc4a bl 8005a5c <HAL_RCC_GetSysClockFreq>
80051c8: 4602 mov r2, r0
80051ca: 4b52 ldr r3, [pc, #328] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80051cc: 689b ldr r3, [r3, #8]
80051ce: 091b lsrs r3, r3, #4
80051d0: f003 030f and.w r3, r3, #15
80051d4: 4950 ldr r1, [pc, #320] @ (8005318 <HAL_RCC_OscConfig+0x274>)
80051d6: 5ccb ldrb r3, [r1, r3]
80051d8: f003 031f and.w r3, r3, #31
80051dc: fa22 f303 lsr.w r3, r2, r3
80051e0: 4a4e ldr r2, [pc, #312] @ (800531c <HAL_RCC_OscConfig+0x278>)
80051e2: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
80051e4: 4b4e ldr r3, [pc, #312] @ (8005320 <HAL_RCC_OscConfig+0x27c>)
80051e6: 681b ldr r3, [r3, #0]
80051e8: 4618 mov r0, r3
80051ea: f7fc ff43 bl 8002074 <HAL_InitTick>
80051ee: 4603 mov r3, r0
80051f0: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
80051f2: 7bfb ldrb r3, [r7, #15]
80051f4: 2b00 cmp r3, #0
80051f6: d052 beq.n 800529e <HAL_RCC_OscConfig+0x1fa>
{
return status;
80051f8: 7bfb ldrb r3, [r7, #15]
80051fa: e327 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
}
else
{
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
80051fc: 687b ldr r3, [r7, #4]
80051fe: 699b ldr r3, [r3, #24]
8005200: 2b00 cmp r3, #0
8005202: d032 beq.n 800526a <HAL_RCC_OscConfig+0x1c6>
{
/* Enable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
8005204: 4b43 ldr r3, [pc, #268] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005206: 681b ldr r3, [r3, #0]
8005208: 4a42 ldr r2, [pc, #264] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800520a: f043 0301 orr.w r3, r3, #1
800520e: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8005210: f7fc ff80 bl 8002114 <HAL_GetTick>
8005214: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8005216: e008 b.n 800522a <HAL_RCC_OscConfig+0x186>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8005218: f7fc ff7c bl 8002114 <HAL_GetTick>
800521c: 4602 mov r2, r0
800521e: 693b ldr r3, [r7, #16]
8005220: 1ad3 subs r3, r2, r3
8005222: 2b02 cmp r3, #2
8005224: d901 bls.n 800522a <HAL_RCC_OscConfig+0x186>
{
return HAL_TIMEOUT;
8005226: 2303 movs r3, #3
8005228: e310 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
800522a: 4b3a ldr r3, [pc, #232] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800522c: 681b ldr r3, [r3, #0]
800522e: f003 0302 and.w r3, r3, #2
8005232: 2b00 cmp r3, #0
8005234: d0f0 beq.n 8005218 <HAL_RCC_OscConfig+0x174>
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8005236: 4b37 ldr r3, [pc, #220] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005238: 681b ldr r3, [r3, #0]
800523a: 4a36 ldr r2, [pc, #216] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800523c: f043 0308 orr.w r3, r3, #8
8005240: 6013 str r3, [r2, #0]
8005242: 4b34 ldr r3, [pc, #208] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005244: 681b ldr r3, [r3, #0]
8005246: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800524a: 687b ldr r3, [r7, #4]
800524c: 6a1b ldr r3, [r3, #32]
800524e: 4931 ldr r1, [pc, #196] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005250: 4313 orrs r3, r2
8005252: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8005254: 4b2f ldr r3, [pc, #188] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005256: 685b ldr r3, [r3, #4]
8005258: f423 427f bic.w r2, r3, #65280 @ 0xff00
800525c: 687b ldr r3, [r7, #4]
800525e: 69db ldr r3, [r3, #28]
8005260: 021b lsls r3, r3, #8
8005262: 492c ldr r1, [pc, #176] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005264: 4313 orrs r3, r2
8005266: 604b str r3, [r1, #4]
8005268: e01a b.n 80052a0 <HAL_RCC_OscConfig+0x1fc>
}
else
{
/* Disable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
800526a: 4b2a ldr r3, [pc, #168] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800526c: 681b ldr r3, [r3, #0]
800526e: 4a29 ldr r2, [pc, #164] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005270: f023 0301 bic.w r3, r3, #1
8005274: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8005276: f7fc ff4d bl 8002114 <HAL_GetTick>
800527a: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
800527c: e008 b.n 8005290 <HAL_RCC_OscConfig+0x1ec>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
800527e: f7fc ff49 bl 8002114 <HAL_GetTick>
8005282: 4602 mov r2, r0
8005284: 693b ldr r3, [r7, #16]
8005286: 1ad3 subs r3, r2, r3
8005288: 2b02 cmp r3, #2
800528a: d901 bls.n 8005290 <HAL_RCC_OscConfig+0x1ec>
{
return HAL_TIMEOUT;
800528c: 2303 movs r3, #3
800528e: e2dd b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
8005290: 4b20 ldr r3, [pc, #128] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005292: 681b ldr r3, [r3, #0]
8005294: f003 0302 and.w r3, r3, #2
8005298: 2b00 cmp r3, #0
800529a: d1f0 bne.n 800527e <HAL_RCC_OscConfig+0x1da>
800529c: e000 b.n 80052a0 <HAL_RCC_OscConfig+0x1fc>
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
800529e: bf00 nop
}
}
}
}
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80052a0: 687b ldr r3, [r7, #4]
80052a2: 681b ldr r3, [r3, #0]
80052a4: f003 0301 and.w r3, r3, #1
80052a8: 2b00 cmp r3, #0
80052aa: d074 beq.n 8005396 <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
80052ac: 69bb ldr r3, [r7, #24]
80052ae: 2b08 cmp r3, #8
80052b0: d005 beq.n 80052be <HAL_RCC_OscConfig+0x21a>
80052b2: 69bb ldr r3, [r7, #24]
80052b4: 2b0c cmp r3, #12
80052b6: d10e bne.n 80052d6 <HAL_RCC_OscConfig+0x232>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
80052b8: 697b ldr r3, [r7, #20]
80052ba: 2b03 cmp r3, #3
80052bc: d10b bne.n 80052d6 <HAL_RCC_OscConfig+0x232>
{
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80052be: 4b15 ldr r3, [pc, #84] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80052c0: 681b ldr r3, [r3, #0]
80052c2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80052c6: 2b00 cmp r3, #0
80052c8: d064 beq.n 8005394 <HAL_RCC_OscConfig+0x2f0>
80052ca: 687b ldr r3, [r7, #4]
80052cc: 685b ldr r3, [r3, #4]
80052ce: 2b00 cmp r3, #0
80052d0: d160 bne.n 8005394 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_ERROR;
80052d2: 2301 movs r3, #1
80052d4: e2ba b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80052d6: 687b ldr r3, [r7, #4]
80052d8: 685b ldr r3, [r3, #4]
80052da: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80052de: d106 bne.n 80052ee <HAL_RCC_OscConfig+0x24a>
80052e0: 4b0c ldr r3, [pc, #48] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80052e2: 681b ldr r3, [r3, #0]
80052e4: 4a0b ldr r2, [pc, #44] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80052e6: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80052ea: 6013 str r3, [r2, #0]
80052ec: e026 b.n 800533c <HAL_RCC_OscConfig+0x298>
80052ee: 687b ldr r3, [r7, #4]
80052f0: 685b ldr r3, [r3, #4]
80052f2: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
80052f6: d115 bne.n 8005324 <HAL_RCC_OscConfig+0x280>
80052f8: 4b06 ldr r3, [pc, #24] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80052fa: 681b ldr r3, [r3, #0]
80052fc: 4a05 ldr r2, [pc, #20] @ (8005314 <HAL_RCC_OscConfig+0x270>)
80052fe: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8005302: 6013 str r3, [r2, #0]
8005304: 4b03 ldr r3, [pc, #12] @ (8005314 <HAL_RCC_OscConfig+0x270>)
8005306: 681b ldr r3, [r3, #0]
8005308: 4a02 ldr r2, [pc, #8] @ (8005314 <HAL_RCC_OscConfig+0x270>)
800530a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800530e: 6013 str r3, [r2, #0]
8005310: e014 b.n 800533c <HAL_RCC_OscConfig+0x298>
8005312: bf00 nop
8005314: 40021000 .word 0x40021000
8005318: 0800e1c0 .word 0x0800e1c0
800531c: 20000000 .word 0x20000000
8005320: 20000004 .word 0x20000004
8005324: 4ba0 ldr r3, [pc, #640] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005326: 681b ldr r3, [r3, #0]
8005328: 4a9f ldr r2, [pc, #636] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800532a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800532e: 6013 str r3, [r2, #0]
8005330: 4b9d ldr r3, [pc, #628] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005332: 681b ldr r3, [r3, #0]
8005334: 4a9c ldr r2, [pc, #624] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005336: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800533a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800533c: 687b ldr r3, [r7, #4]
800533e: 685b ldr r3, [r3, #4]
8005340: 2b00 cmp r3, #0
8005342: d013 beq.n 800536c <HAL_RCC_OscConfig+0x2c8>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005344: f7fc fee6 bl 8002114 <HAL_GetTick>
8005348: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800534a: e008 b.n 800535e <HAL_RCC_OscConfig+0x2ba>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800534c: f7fc fee2 bl 8002114 <HAL_GetTick>
8005350: 4602 mov r2, r0
8005352: 693b ldr r3, [r7, #16]
8005354: 1ad3 subs r3, r2, r3
8005356: 2b64 cmp r3, #100 @ 0x64
8005358: d901 bls.n 800535e <HAL_RCC_OscConfig+0x2ba>
{
return HAL_TIMEOUT;
800535a: 2303 movs r3, #3
800535c: e276 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800535e: 4b92 ldr r3, [pc, #584] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005360: 681b ldr r3, [r3, #0]
8005362: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005366: 2b00 cmp r3, #0
8005368: d0f0 beq.n 800534c <HAL_RCC_OscConfig+0x2a8>
800536a: e014 b.n 8005396 <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800536c: f7fc fed2 bl 8002114 <HAL_GetTick>
8005370: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8005372: e008 b.n 8005386 <HAL_RCC_OscConfig+0x2e2>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8005374: f7fc fece bl 8002114 <HAL_GetTick>
8005378: 4602 mov r2, r0
800537a: 693b ldr r3, [r7, #16]
800537c: 1ad3 subs r3, r2, r3
800537e: 2b64 cmp r3, #100 @ 0x64
8005380: d901 bls.n 8005386 <HAL_RCC_OscConfig+0x2e2>
{
return HAL_TIMEOUT;
8005382: 2303 movs r3, #3
8005384: e262 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8005386: 4b88 ldr r3, [pc, #544] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005388: 681b ldr r3, [r3, #0]
800538a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800538e: 2b00 cmp r3, #0
8005390: d1f0 bne.n 8005374 <HAL_RCC_OscConfig+0x2d0>
8005392: e000 b.n 8005396 <HAL_RCC_OscConfig+0x2f2>
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8005394: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8005396: 687b ldr r3, [r7, #4]
8005398: 681b ldr r3, [r3, #0]
800539a: f003 0302 and.w r3, r3, #2
800539e: 2b00 cmp r3, #0
80053a0: d060 beq.n 8005464 <HAL_RCC_OscConfig+0x3c0>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
80053a2: 69bb ldr r3, [r7, #24]
80053a4: 2b04 cmp r3, #4
80053a6: d005 beq.n 80053b4 <HAL_RCC_OscConfig+0x310>
80053a8: 69bb ldr r3, [r7, #24]
80053aa: 2b0c cmp r3, #12
80053ac: d119 bne.n 80053e2 <HAL_RCC_OscConfig+0x33e>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
80053ae: 697b ldr r3, [r7, #20]
80053b0: 2b02 cmp r3, #2
80053b2: d116 bne.n 80053e2 <HAL_RCC_OscConfig+0x33e>
{
/* When HSI is used as system clock it will not be disabled */
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80053b4: 4b7c ldr r3, [pc, #496] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80053b6: 681b ldr r3, [r3, #0]
80053b8: f403 6380 and.w r3, r3, #1024 @ 0x400
80053bc: 2b00 cmp r3, #0
80053be: d005 beq.n 80053cc <HAL_RCC_OscConfig+0x328>
80053c0: 687b ldr r3, [r7, #4]
80053c2: 68db ldr r3, [r3, #12]
80053c4: 2b00 cmp r3, #0
80053c6: d101 bne.n 80053cc <HAL_RCC_OscConfig+0x328>
{
return HAL_ERROR;
80053c8: 2301 movs r3, #1
80053ca: e23f b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80053cc: 4b76 ldr r3, [pc, #472] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80053ce: 685b ldr r3, [r3, #4]
80053d0: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
80053d4: 687b ldr r3, [r7, #4]
80053d6: 691b ldr r3, [r3, #16]
80053d8: 061b lsls r3, r3, #24
80053da: 4973 ldr r1, [pc, #460] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80053dc: 4313 orrs r3, r2
80053de: 604b str r3, [r1, #4]
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80053e0: e040 b.n 8005464 <HAL_RCC_OscConfig+0x3c0>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80053e2: 687b ldr r3, [r7, #4]
80053e4: 68db ldr r3, [r3, #12]
80053e6: 2b00 cmp r3, #0
80053e8: d023 beq.n 8005432 <HAL_RCC_OscConfig+0x38e>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80053ea: 4b6f ldr r3, [pc, #444] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80053ec: 681b ldr r3, [r3, #0]
80053ee: 4a6e ldr r2, [pc, #440] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80053f0: f443 7380 orr.w r3, r3, #256 @ 0x100
80053f4: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80053f6: f7fc fe8d bl 8002114 <HAL_GetTick>
80053fa: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
80053fc: e008 b.n 8005410 <HAL_RCC_OscConfig+0x36c>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80053fe: f7fc fe89 bl 8002114 <HAL_GetTick>
8005402: 4602 mov r2, r0
8005404: 693b ldr r3, [r7, #16]
8005406: 1ad3 subs r3, r2, r3
8005408: 2b02 cmp r3, #2
800540a: d901 bls.n 8005410 <HAL_RCC_OscConfig+0x36c>
{
return HAL_TIMEOUT;
800540c: 2303 movs r3, #3
800540e: e21d b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8005410: 4b65 ldr r3, [pc, #404] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005412: 681b ldr r3, [r3, #0]
8005414: f403 6380 and.w r3, r3, #1024 @ 0x400
8005418: 2b00 cmp r3, #0
800541a: d0f0 beq.n 80053fe <HAL_RCC_OscConfig+0x35a>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800541c: 4b62 ldr r3, [pc, #392] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800541e: 685b ldr r3, [r3, #4]
8005420: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
8005424: 687b ldr r3, [r7, #4]
8005426: 691b ldr r3, [r3, #16]
8005428: 061b lsls r3, r3, #24
800542a: 495f ldr r1, [pc, #380] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800542c: 4313 orrs r3, r2
800542e: 604b str r3, [r1, #4]
8005430: e018 b.n 8005464 <HAL_RCC_OscConfig+0x3c0>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8005432: 4b5d ldr r3, [pc, #372] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005434: 681b ldr r3, [r3, #0]
8005436: 4a5c ldr r2, [pc, #368] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005438: f423 7380 bic.w r3, r3, #256 @ 0x100
800543c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800543e: f7fc fe69 bl 8002114 <HAL_GetTick>
8005442: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8005444: e008 b.n 8005458 <HAL_RCC_OscConfig+0x3b4>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8005446: f7fc fe65 bl 8002114 <HAL_GetTick>
800544a: 4602 mov r2, r0
800544c: 693b ldr r3, [r7, #16]
800544e: 1ad3 subs r3, r2, r3
8005450: 2b02 cmp r3, #2
8005452: d901 bls.n 8005458 <HAL_RCC_OscConfig+0x3b4>
{
return HAL_TIMEOUT;
8005454: 2303 movs r3, #3
8005456: e1f9 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8005458: 4b53 ldr r3, [pc, #332] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800545a: 681b ldr r3, [r3, #0]
800545c: f403 6380 and.w r3, r3, #1024 @ 0x400
8005460: 2b00 cmp r3, #0
8005462: d1f0 bne.n 8005446 <HAL_RCC_OscConfig+0x3a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8005464: 687b ldr r3, [r7, #4]
8005466: 681b ldr r3, [r3, #0]
8005468: f003 0308 and.w r3, r3, #8
800546c: 2b00 cmp r3, #0
800546e: d03c beq.n 80054ea <HAL_RCC_OscConfig+0x446>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8005470: 687b ldr r3, [r7, #4]
8005472: 695b ldr r3, [r3, #20]
8005474: 2b00 cmp r3, #0
8005476: d01c beq.n 80054b2 <HAL_RCC_OscConfig+0x40e>
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
}
#endif /* RCC_CSR_LSIPREDIV */
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8005478: 4b4b ldr r3, [pc, #300] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800547a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800547e: 4a4a ldr r2, [pc, #296] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005480: f043 0301 orr.w r3, r3, #1
8005484: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005488: f7fc fe44 bl 8002114 <HAL_GetTick>
800548c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
800548e: e008 b.n 80054a2 <HAL_RCC_OscConfig+0x3fe>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8005490: f7fc fe40 bl 8002114 <HAL_GetTick>
8005494: 4602 mov r2, r0
8005496: 693b ldr r3, [r7, #16]
8005498: 1ad3 subs r3, r2, r3
800549a: 2b02 cmp r3, #2
800549c: d901 bls.n 80054a2 <HAL_RCC_OscConfig+0x3fe>
{
return HAL_TIMEOUT;
800549e: 2303 movs r3, #3
80054a0: e1d4 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80054a2: 4b41 ldr r3, [pc, #260] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80054a4: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80054a8: f003 0302 and.w r3, r3, #2
80054ac: 2b00 cmp r3, #0
80054ae: d0ef beq.n 8005490 <HAL_RCC_OscConfig+0x3ec>
80054b0: e01b b.n 80054ea <HAL_RCC_OscConfig+0x446>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80054b2: 4b3d ldr r3, [pc, #244] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80054b4: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80054b8: 4a3b ldr r2, [pc, #236] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80054ba: f023 0301 bic.w r3, r3, #1
80054be: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
80054c2: f7fc fe27 bl 8002114 <HAL_GetTick>
80054c6: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80054c8: e008 b.n 80054dc <HAL_RCC_OscConfig+0x438>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80054ca: f7fc fe23 bl 8002114 <HAL_GetTick>
80054ce: 4602 mov r2, r0
80054d0: 693b ldr r3, [r7, #16]
80054d2: 1ad3 subs r3, r2, r3
80054d4: 2b02 cmp r3, #2
80054d6: d901 bls.n 80054dc <HAL_RCC_OscConfig+0x438>
{
return HAL_TIMEOUT;
80054d8: 2303 movs r3, #3
80054da: e1b7 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80054dc: 4b32 ldr r3, [pc, #200] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80054de: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80054e2: f003 0302 and.w r3, r3, #2
80054e6: 2b00 cmp r3, #0
80054e8: d1ef bne.n 80054ca <HAL_RCC_OscConfig+0x426>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80054ea: 687b ldr r3, [r7, #4]
80054ec: 681b ldr r3, [r3, #0]
80054ee: f003 0304 and.w r3, r3, #4
80054f2: 2b00 cmp r3, #0
80054f4: f000 80a6 beq.w 8005644 <HAL_RCC_OscConfig+0x5a0>
{
FlagStatus pwrclkchanged = RESET;
80054f8: 2300 movs r3, #0
80054fa: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
80054fc: 4b2a ldr r3, [pc, #168] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
80054fe: 6d9b ldr r3, [r3, #88] @ 0x58
8005500: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005504: 2b00 cmp r3, #0
8005506: d10d bne.n 8005524 <HAL_RCC_OscConfig+0x480>
{
__HAL_RCC_PWR_CLK_ENABLE();
8005508: 4b27 ldr r3, [pc, #156] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800550a: 6d9b ldr r3, [r3, #88] @ 0x58
800550c: 4a26 ldr r2, [pc, #152] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800550e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005512: 6593 str r3, [r2, #88] @ 0x58
8005514: 4b24 ldr r3, [pc, #144] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005516: 6d9b ldr r3, [r3, #88] @ 0x58
8005518: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800551c: 60bb str r3, [r7, #8]
800551e: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8005520: 2301 movs r3, #1
8005522: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8005524: 4b21 ldr r3, [pc, #132] @ (80055ac <HAL_RCC_OscConfig+0x508>)
8005526: 681b ldr r3, [r3, #0]
8005528: f403 7380 and.w r3, r3, #256 @ 0x100
800552c: 2b00 cmp r3, #0
800552e: d118 bne.n 8005562 <HAL_RCC_OscConfig+0x4be>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8005530: 4b1e ldr r3, [pc, #120] @ (80055ac <HAL_RCC_OscConfig+0x508>)
8005532: 681b ldr r3, [r3, #0]
8005534: 4a1d ldr r2, [pc, #116] @ (80055ac <HAL_RCC_OscConfig+0x508>)
8005536: f443 7380 orr.w r3, r3, #256 @ 0x100
800553a: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800553c: f7fc fdea bl 8002114 <HAL_GetTick>
8005540: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8005542: e008 b.n 8005556 <HAL_RCC_OscConfig+0x4b2>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8005544: f7fc fde6 bl 8002114 <HAL_GetTick>
8005548: 4602 mov r2, r0
800554a: 693b ldr r3, [r7, #16]
800554c: 1ad3 subs r3, r2, r3
800554e: 2b02 cmp r3, #2
8005550: d901 bls.n 8005556 <HAL_RCC_OscConfig+0x4b2>
{
return HAL_TIMEOUT;
8005552: 2303 movs r3, #3
8005554: e17a b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8005556: 4b15 ldr r3, [pc, #84] @ (80055ac <HAL_RCC_OscConfig+0x508>)
8005558: 681b ldr r3, [r3, #0]
800555a: f403 7380 and.w r3, r3, #256 @ 0x100
800555e: 2b00 cmp r3, #0
8005560: d0f0 beq.n 8005544 <HAL_RCC_OscConfig+0x4a0>
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
#else
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8005562: 687b ldr r3, [r7, #4]
8005564: 689b ldr r3, [r3, #8]
8005566: 2b01 cmp r3, #1
8005568: d108 bne.n 800557c <HAL_RCC_OscConfig+0x4d8>
800556a: 4b0f ldr r3, [pc, #60] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800556c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8005570: 4a0d ldr r2, [pc, #52] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005572: f043 0301 orr.w r3, r3, #1
8005576: f8c2 3090 str.w r3, [r2, #144] @ 0x90
800557a: e029 b.n 80055d0 <HAL_RCC_OscConfig+0x52c>
800557c: 687b ldr r3, [r7, #4]
800557e: 689b ldr r3, [r3, #8]
8005580: 2b05 cmp r3, #5
8005582: d115 bne.n 80055b0 <HAL_RCC_OscConfig+0x50c>
8005584: 4b08 ldr r3, [pc, #32] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005586: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800558a: 4a07 ldr r2, [pc, #28] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800558c: f043 0304 orr.w r3, r3, #4
8005590: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8005594: 4b04 ldr r3, [pc, #16] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
8005596: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800559a: 4a03 ldr r2, [pc, #12] @ (80055a8 <HAL_RCC_OscConfig+0x504>)
800559c: f043 0301 orr.w r3, r3, #1
80055a0: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80055a4: e014 b.n 80055d0 <HAL_RCC_OscConfig+0x52c>
80055a6: bf00 nop
80055a8: 40021000 .word 0x40021000
80055ac: 40007000 .word 0x40007000
80055b0: 4b9c ldr r3, [pc, #624] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80055b2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80055b6: 4a9b ldr r2, [pc, #620] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80055b8: f023 0301 bic.w r3, r3, #1
80055bc: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80055c0: 4b98 ldr r3, [pc, #608] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80055c2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80055c6: 4a97 ldr r2, [pc, #604] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80055c8: f023 0304 bic.w r3, r3, #4
80055cc: f8c2 3090 str.w r3, [r2, #144] @ 0x90
#endif /* RCC_BDCR_LSESYSDIS */
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80055d0: 687b ldr r3, [r7, #4]
80055d2: 689b ldr r3, [r3, #8]
80055d4: 2b00 cmp r3, #0
80055d6: d016 beq.n 8005606 <HAL_RCC_OscConfig+0x562>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80055d8: f7fc fd9c bl 8002114 <HAL_GetTick>
80055dc: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80055de: e00a b.n 80055f6 <HAL_RCC_OscConfig+0x552>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80055e0: f7fc fd98 bl 8002114 <HAL_GetTick>
80055e4: 4602 mov r2, r0
80055e6: 693b ldr r3, [r7, #16]
80055e8: 1ad3 subs r3, r2, r3
80055ea: f241 3288 movw r2, #5000 @ 0x1388
80055ee: 4293 cmp r3, r2
80055f0: d901 bls.n 80055f6 <HAL_RCC_OscConfig+0x552>
{
return HAL_TIMEOUT;
80055f2: 2303 movs r3, #3
80055f4: e12a b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80055f6: 4b8b ldr r3, [pc, #556] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80055f8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80055fc: f003 0302 and.w r3, r3, #2
8005600: 2b00 cmp r3, #0
8005602: d0ed beq.n 80055e0 <HAL_RCC_OscConfig+0x53c>
8005604: e015 b.n 8005632 <HAL_RCC_OscConfig+0x58e>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005606: f7fc fd85 bl 8002114 <HAL_GetTick>
800560a: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
800560c: e00a b.n 8005624 <HAL_RCC_OscConfig+0x580>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800560e: f7fc fd81 bl 8002114 <HAL_GetTick>
8005612: 4602 mov r2, r0
8005614: 693b ldr r3, [r7, #16]
8005616: 1ad3 subs r3, r2, r3
8005618: f241 3288 movw r2, #5000 @ 0x1388
800561c: 4293 cmp r3, r2
800561e: d901 bls.n 8005624 <HAL_RCC_OscConfig+0x580>
{
return HAL_TIMEOUT;
8005620: 2303 movs r3, #3
8005622: e113 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8005624: 4b7f ldr r3, [pc, #508] @ (8005824 <HAL_RCC_OscConfig+0x780>)
8005626: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800562a: f003 0302 and.w r3, r3, #2
800562e: 2b00 cmp r3, #0
8005630: d1ed bne.n 800560e <HAL_RCC_OscConfig+0x56a>
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8005632: 7ffb ldrb r3, [r7, #31]
8005634: 2b01 cmp r3, #1
8005636: d105 bne.n 8005644 <HAL_RCC_OscConfig+0x5a0>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005638: 4b7a ldr r3, [pc, #488] @ (8005824 <HAL_RCC_OscConfig+0x780>)
800563a: 6d9b ldr r3, [r3, #88] @ 0x58
800563c: 4a79 ldr r2, [pc, #484] @ (8005824 <HAL_RCC_OscConfig+0x780>)
800563e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005642: 6593 str r3, [r2, #88] @ 0x58
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8005644: 687b ldr r3, [r7, #4]
8005646: 6a9b ldr r3, [r3, #40] @ 0x28
8005648: 2b00 cmp r3, #0
800564a: f000 80fe beq.w 800584a <HAL_RCC_OscConfig+0x7a6>
{
/* PLL On ? */
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
800564e: 687b ldr r3, [r7, #4]
8005650: 6a9b ldr r3, [r3, #40] @ 0x28
8005652: 2b02 cmp r3, #2
8005654: f040 80d0 bne.w 80057f8 <HAL_RCC_OscConfig+0x754>
#endif /* RCC_PLLP_SUPPORT */
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Do nothing if PLL configuration is the unchanged */
pll_config = RCC->PLLCFGR;
8005658: 4b72 ldr r3, [pc, #456] @ (8005824 <HAL_RCC_OscConfig+0x780>)
800565a: 68db ldr r3, [r3, #12]
800565c: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800565e: 697b ldr r3, [r7, #20]
8005660: f003 0203 and.w r2, r3, #3
8005664: 687b ldr r3, [r7, #4]
8005666: 6adb ldr r3, [r3, #44] @ 0x2c
8005668: 429a cmp r2, r3
800566a: d130 bne.n 80056ce <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
800566c: 697b ldr r3, [r7, #20]
800566e: f003 0270 and.w r2, r3, #112 @ 0x70
8005672: 687b ldr r3, [r7, #4]
8005674: 6b1b ldr r3, [r3, #48] @ 0x30
8005676: 3b01 subs r3, #1
8005678: 011b lsls r3, r3, #4
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800567a: 429a cmp r2, r3
800567c: d127 bne.n 80056ce <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
800567e: 697b ldr r3, [r7, #20]
8005680: f403 42fe and.w r2, r3, #32512 @ 0x7f00
8005684: 687b ldr r3, [r7, #4]
8005686: 6b5b ldr r3, [r3, #52] @ 0x34
8005688: 021b lsls r3, r3, #8
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
800568a: 429a cmp r2, r3
800568c: d11f bne.n 80056ce <HAL_RCC_OscConfig+0x62a>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
#else
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
800568e: 697b ldr r3, [r7, #20]
8005690: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005694: 687a ldr r2, [r7, #4]
8005696: 6b92 ldr r2, [r2, #56] @ 0x38
8005698: 2a07 cmp r2, #7
800569a: bf14 ite ne
800569c: 2201 movne r2, #1
800569e: 2200 moveq r2, #0
80056a0: b2d2 uxtb r2, r2
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80056a2: 4293 cmp r3, r2
80056a4: d113 bne.n 80056ce <HAL_RCC_OscConfig+0x62a>
#endif
#endif
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
80056a6: 697b ldr r3, [r7, #20]
80056a8: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
80056ac: 687b ldr r3, [r7, #4]
80056ae: 6bdb ldr r3, [r3, #60] @ 0x3c
80056b0: 085b lsrs r3, r3, #1
80056b2: 3b01 subs r3, #1
80056b4: 055b lsls r3, r3, #21
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
80056b6: 429a cmp r2, r3
80056b8: d109 bne.n 80056ce <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
80056ba: 697b ldr r3, [r7, #20]
80056bc: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
80056c0: 687b ldr r3, [r7, #4]
80056c2: 6c1b ldr r3, [r3, #64] @ 0x40
80056c4: 085b lsrs r3, r3, #1
80056c6: 3b01 subs r3, #1
80056c8: 065b lsls r3, r3, #25
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
80056ca: 429a cmp r2, r3
80056cc: d06e beq.n 80057ac <HAL_RCC_OscConfig+0x708>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
80056ce: 69bb ldr r3, [r7, #24]
80056d0: 2b0c cmp r3, #12
80056d2: d069 beq.n 80057a8 <HAL_RCC_OscConfig+0x704>
{
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
/* Check if main PLL can be updated */
/* Not possible if the source is shared by other enabled PLLSAIx */
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
80056d4: 4b53 ldr r3, [pc, #332] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80056d6: 681b ldr r3, [r3, #0]
80056d8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
80056dc: 2b00 cmp r3, #0
80056de: d105 bne.n 80056ec <HAL_RCC_OscConfig+0x648>
#if defined(RCC_PLLSAI2_SUPPORT)
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
80056e0: 4b50 ldr r3, [pc, #320] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80056e2: 681b ldr r3, [r3, #0]
80056e4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80056e8: 2b00 cmp r3, #0
80056ea: d001 beq.n 80056f0 <HAL_RCC_OscConfig+0x64c>
#endif
)
{
return HAL_ERROR;
80056ec: 2301 movs r3, #1
80056ee: e0ad b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80056f0: 4b4c ldr r3, [pc, #304] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80056f2: 681b ldr r3, [r3, #0]
80056f4: 4a4b ldr r2, [pc, #300] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80056f6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80056fa: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80056fc: f7fc fd0a bl 8002114 <HAL_GetTick>
8005700: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8005702: e008 b.n 8005716 <HAL_RCC_OscConfig+0x672>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005704: f7fc fd06 bl 8002114 <HAL_GetTick>
8005708: 4602 mov r2, r0
800570a: 693b ldr r3, [r7, #16]
800570c: 1ad3 subs r3, r2, r3
800570e: 2b02 cmp r3, #2
8005710: d901 bls.n 8005716 <HAL_RCC_OscConfig+0x672>
{
return HAL_TIMEOUT;
8005712: 2303 movs r3, #3
8005714: e09a b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8005716: 4b43 ldr r3, [pc, #268] @ (8005824 <HAL_RCC_OscConfig+0x780>)
8005718: 681b ldr r3, [r3, #0]
800571a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800571e: 2b00 cmp r3, #0
8005720: d1f0 bne.n 8005704 <HAL_RCC_OscConfig+0x660>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8005722: 4b40 ldr r3, [pc, #256] @ (8005824 <HAL_RCC_OscConfig+0x780>)
8005724: 68da ldr r2, [r3, #12]
8005726: 4b40 ldr r3, [pc, #256] @ (8005828 <HAL_RCC_OscConfig+0x784>)
8005728: 4013 ands r3, r2
800572a: 687a ldr r2, [r7, #4]
800572c: 6ad1 ldr r1, [r2, #44] @ 0x2c
800572e: 687a ldr r2, [r7, #4]
8005730: 6b12 ldr r2, [r2, #48] @ 0x30
8005732: 3a01 subs r2, #1
8005734: 0112 lsls r2, r2, #4
8005736: 4311 orrs r1, r2
8005738: 687a ldr r2, [r7, #4]
800573a: 6b52 ldr r2, [r2, #52] @ 0x34
800573c: 0212 lsls r2, r2, #8
800573e: 4311 orrs r1, r2
8005740: 687a ldr r2, [r7, #4]
8005742: 6bd2 ldr r2, [r2, #60] @ 0x3c
8005744: 0852 lsrs r2, r2, #1
8005746: 3a01 subs r2, #1
8005748: 0552 lsls r2, r2, #21
800574a: 4311 orrs r1, r2
800574c: 687a ldr r2, [r7, #4]
800574e: 6c12 ldr r2, [r2, #64] @ 0x40
8005750: 0852 lsrs r2, r2, #1
8005752: 3a01 subs r2, #1
8005754: 0652 lsls r2, r2, #25
8005756: 4311 orrs r1, r2
8005758: 687a ldr r2, [r7, #4]
800575a: 6b92 ldr r2, [r2, #56] @ 0x38
800575c: 0912 lsrs r2, r2, #4
800575e: 0452 lsls r2, r2, #17
8005760: 430a orrs r2, r1
8005762: 4930 ldr r1, [pc, #192] @ (8005824 <HAL_RCC_OscConfig+0x780>)
8005764: 4313 orrs r3, r2
8005766: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8005768: 4b2e ldr r3, [pc, #184] @ (8005824 <HAL_RCC_OscConfig+0x780>)
800576a: 681b ldr r3, [r3, #0]
800576c: 4a2d ldr r2, [pc, #180] @ (8005824 <HAL_RCC_OscConfig+0x780>)
800576e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8005772: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8005774: 4b2b ldr r3, [pc, #172] @ (8005824 <HAL_RCC_OscConfig+0x780>)
8005776: 68db ldr r3, [r3, #12]
8005778: 4a2a ldr r2, [pc, #168] @ (8005824 <HAL_RCC_OscConfig+0x780>)
800577a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800577e: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005780: f7fc fcc8 bl 8002114 <HAL_GetTick>
8005784: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8005786: e008 b.n 800579a <HAL_RCC_OscConfig+0x6f6>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005788: f7fc fcc4 bl 8002114 <HAL_GetTick>
800578c: 4602 mov r2, r0
800578e: 693b ldr r3, [r7, #16]
8005790: 1ad3 subs r3, r2, r3
8005792: 2b02 cmp r3, #2
8005794: d901 bls.n 800579a <HAL_RCC_OscConfig+0x6f6>
{
return HAL_TIMEOUT;
8005796: 2303 movs r3, #3
8005798: e058 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800579a: 4b22 ldr r3, [pc, #136] @ (8005824 <HAL_RCC_OscConfig+0x780>)
800579c: 681b ldr r3, [r3, #0]
800579e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80057a2: 2b00 cmp r3, #0
80057a4: d0f0 beq.n 8005788 <HAL_RCC_OscConfig+0x6e4>
if(sysclk_source != RCC_CFGR_SWS_PLL)
80057a6: e050 b.n 800584a <HAL_RCC_OscConfig+0x7a6>
}
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
80057a8: 2301 movs r3, #1
80057aa: e04f b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
else
{
/* PLL configuration is unchanged */
/* Re-enable PLL if it was disabled (ie. low power mode) */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80057ac: 4b1d ldr r3, [pc, #116] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80057ae: 681b ldr r3, [r3, #0]
80057b0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80057b4: 2b00 cmp r3, #0
80057b6: d148 bne.n 800584a <HAL_RCC_OscConfig+0x7a6>
{
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80057b8: 4b1a ldr r3, [pc, #104] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80057ba: 681b ldr r3, [r3, #0]
80057bc: 4a19 ldr r2, [pc, #100] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80057be: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80057c2: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
80057c4: 4b17 ldr r3, [pc, #92] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80057c6: 68db ldr r3, [r3, #12]
80057c8: 4a16 ldr r2, [pc, #88] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80057ca: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80057ce: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80057d0: f7fc fca0 bl 8002114 <HAL_GetTick>
80057d4: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80057d6: e008 b.n 80057ea <HAL_RCC_OscConfig+0x746>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80057d8: f7fc fc9c bl 8002114 <HAL_GetTick>
80057dc: 4602 mov r2, r0
80057de: 693b ldr r3, [r7, #16]
80057e0: 1ad3 subs r3, r2, r3
80057e2: 2b02 cmp r3, #2
80057e4: d901 bls.n 80057ea <HAL_RCC_OscConfig+0x746>
{
return HAL_TIMEOUT;
80057e6: 2303 movs r3, #3
80057e8: e030 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80057ea: 4b0e ldr r3, [pc, #56] @ (8005824 <HAL_RCC_OscConfig+0x780>)
80057ec: 681b ldr r3, [r3, #0]
80057ee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80057f2: 2b00 cmp r3, #0
80057f4: d0f0 beq.n 80057d8 <HAL_RCC_OscConfig+0x734>
80057f6: e028 b.n 800584a <HAL_RCC_OscConfig+0x7a6>
}
}
else
{
/* Check that PLL is not used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
80057f8: 69bb ldr r3, [r7, #24]
80057fa: 2b0c cmp r3, #12
80057fc: d023 beq.n 8005846 <HAL_RCC_OscConfig+0x7a2>
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80057fe: 4b09 ldr r3, [pc, #36] @ (8005824 <HAL_RCC_OscConfig+0x780>)
8005800: 681b ldr r3, [r3, #0]
8005802: 4a08 ldr r2, [pc, #32] @ (8005824 <HAL_RCC_OscConfig+0x780>)
8005804: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8005808: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800580a: f7fc fc83 bl 8002114 <HAL_GetTick>
800580e: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8005810: e00c b.n 800582c <HAL_RCC_OscConfig+0x788>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005812: f7fc fc7f bl 8002114 <HAL_GetTick>
8005816: 4602 mov r2, r0
8005818: 693b ldr r3, [r7, #16]
800581a: 1ad3 subs r3, r2, r3
800581c: 2b02 cmp r3, #2
800581e: d905 bls.n 800582c <HAL_RCC_OscConfig+0x788>
{
return HAL_TIMEOUT;
8005820: 2303 movs r3, #3
8005822: e013 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
8005824: 40021000 .word 0x40021000
8005828: f99d808c .word 0xf99d808c
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
800582c: 4b09 ldr r3, [pc, #36] @ (8005854 <HAL_RCC_OscConfig+0x7b0>)
800582e: 681b ldr r3, [r3, #0]
8005830: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005834: 2b00 cmp r3, #0
8005836: d1ec bne.n 8005812 <HAL_RCC_OscConfig+0x76e>
}
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
8005838: 4b06 ldr r3, [pc, #24] @ (8005854 <HAL_RCC_OscConfig+0x7b0>)
800583a: 68da ldr r2, [r3, #12]
800583c: 4905 ldr r1, [pc, #20] @ (8005854 <HAL_RCC_OscConfig+0x7b0>)
800583e: 4b06 ldr r3, [pc, #24] @ (8005858 <HAL_RCC_OscConfig+0x7b4>)
8005840: 4013 ands r3, r2
8005842: 60cb str r3, [r1, #12]
8005844: e001 b.n 800584a <HAL_RCC_OscConfig+0x7a6>
#endif /* RCC_PLLSAI2_SUPPORT */
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
8005846: 2301 movs r3, #1
8005848: e000 b.n 800584c <HAL_RCC_OscConfig+0x7a8>
}
}
}
return HAL_OK;
800584a: 2300 movs r3, #0
}
800584c: 4618 mov r0, r3
800584e: 3720 adds r7, #32
8005850: 46bd mov sp, r7
8005852: bd80 pop {r7, pc}
8005854: 40021000 .word 0x40021000
8005858: feeefffc .word 0xfeeefffc
0800585c <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
800585c: b580 push {r7, lr}
800585e: b084 sub sp, #16
8005860: af00 add r7, sp, #0
8005862: 6078 str r0, [r7, #4]
8005864: 6039 str r1, [r7, #0]
uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
HAL_StatusTypeDef status;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8005866: 687b ldr r3, [r7, #4]
8005868: 2b00 cmp r3, #0
800586a: d101 bne.n 8005870 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
800586c: 2301 movs r3, #1
800586e: e0e7 b.n 8005a40 <HAL_RCC_ClockConfig+0x1e4>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8005870: 4b75 ldr r3, [pc, #468] @ (8005a48 <HAL_RCC_ClockConfig+0x1ec>)
8005872: 681b ldr r3, [r3, #0]
8005874: f003 0307 and.w r3, r3, #7
8005878: 683a ldr r2, [r7, #0]
800587a: 429a cmp r2, r3
800587c: d910 bls.n 80058a0 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800587e: 4b72 ldr r3, [pc, #456] @ (8005a48 <HAL_RCC_ClockConfig+0x1ec>)
8005880: 681b ldr r3, [r3, #0]
8005882: f023 0207 bic.w r2, r3, #7
8005886: 4970 ldr r1, [pc, #448] @ (8005a48 <HAL_RCC_ClockConfig+0x1ec>)
8005888: 683b ldr r3, [r7, #0]
800588a: 4313 orrs r3, r2
800588c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800588e: 4b6e ldr r3, [pc, #440] @ (8005a48 <HAL_RCC_ClockConfig+0x1ec>)
8005890: 681b ldr r3, [r3, #0]
8005892: f003 0307 and.w r3, r3, #7
8005896: 683a ldr r2, [r7, #0]
8005898: 429a cmp r2, r3
800589a: d001 beq.n 80058a0 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
800589c: 2301 movs r3, #1
800589e: e0cf b.n 8005a40 <HAL_RCC_ClockConfig+0x1e4>
}
}
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80058a0: 687b ldr r3, [r7, #4]
80058a2: 681b ldr r3, [r3, #0]
80058a4: f003 0302 and.w r3, r3, #2
80058a8: 2b00 cmp r3, #0
80058aa: d010 beq.n 80058ce <HAL_RCC_ClockConfig+0x72>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
80058ac: 687b ldr r3, [r7, #4]
80058ae: 689a ldr r2, [r3, #8]
80058b0: 4b66 ldr r3, [pc, #408] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
80058b2: 689b ldr r3, [r3, #8]
80058b4: f003 03f0 and.w r3, r3, #240 @ 0xf0
80058b8: 429a cmp r2, r3
80058ba: d908 bls.n 80058ce <HAL_RCC_ClockConfig+0x72>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80058bc: 4b63 ldr r3, [pc, #396] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
80058be: 689b ldr r3, [r3, #8]
80058c0: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80058c4: 687b ldr r3, [r7, #4]
80058c6: 689b ldr r3, [r3, #8]
80058c8: 4960 ldr r1, [pc, #384] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
80058ca: 4313 orrs r3, r2
80058cc: 608b str r3, [r1, #8]
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80058ce: 687b ldr r3, [r7, #4]
80058d0: 681b ldr r3, [r3, #0]
80058d2: f003 0301 and.w r3, r3, #1
80058d6: 2b00 cmp r3, #0
80058d8: d04c beq.n 8005974 <HAL_RCC_ClockConfig+0x118>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80058da: 687b ldr r3, [r7, #4]
80058dc: 685b ldr r3, [r3, #4]
80058de: 2b03 cmp r3, #3
80058e0: d107 bne.n 80058f2 <HAL_RCC_ClockConfig+0x96>
{
/* Check the PLL ready flag */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80058e2: 4b5a ldr r3, [pc, #360] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
80058e4: 681b ldr r3, [r3, #0]
80058e6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80058ea: 2b00 cmp r3, #0
80058ec: d121 bne.n 8005932 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
80058ee: 2301 movs r3, #1
80058f0: e0a6 b.n 8005a40 <HAL_RCC_ClockConfig+0x1e4>
#endif
}
else
{
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80058f2: 687b ldr r3, [r7, #4]
80058f4: 685b ldr r3, [r3, #4]
80058f6: 2b02 cmp r3, #2
80058f8: d107 bne.n 800590a <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80058fa: 4b54 ldr r3, [pc, #336] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
80058fc: 681b ldr r3, [r3, #0]
80058fe: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005902: 2b00 cmp r3, #0
8005904: d115 bne.n 8005932 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
8005906: 2301 movs r3, #1
8005908: e09a b.n 8005a40 <HAL_RCC_ClockConfig+0x1e4>
}
}
/* MSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
800590a: 687b ldr r3, [r7, #4]
800590c: 685b ldr r3, [r3, #4]
800590e: 2b00 cmp r3, #0
8005910: d107 bne.n 8005922 <HAL_RCC_ClockConfig+0xc6>
{
/* Check the MSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8005912: 4b4e ldr r3, [pc, #312] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005914: 681b ldr r3, [r3, #0]
8005916: f003 0302 and.w r3, r3, #2
800591a: 2b00 cmp r3, #0
800591c: d109 bne.n 8005932 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800591e: 2301 movs r3, #1
8005920: e08e b.n 8005a40 <HAL_RCC_ClockConfig+0x1e4>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8005922: 4b4a ldr r3, [pc, #296] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005924: 681b ldr r3, [r3, #0]
8005926: f403 6380 and.w r3, r3, #1024 @ 0x400
800592a: 2b00 cmp r3, #0
800592c: d101 bne.n 8005932 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800592e: 2301 movs r3, #1
8005930: e086 b.n 8005a40 <HAL_RCC_ClockConfig+0x1e4>
}
#endif
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8005932: 4b46 ldr r3, [pc, #280] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005934: 689b ldr r3, [r3, #8]
8005936: f023 0203 bic.w r2, r3, #3
800593a: 687b ldr r3, [r7, #4]
800593c: 685b ldr r3, [r3, #4]
800593e: 4943 ldr r1, [pc, #268] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005940: 4313 orrs r3, r2
8005942: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005944: f7fc fbe6 bl 8002114 <HAL_GetTick>
8005948: 60f8 str r0, [r7, #12]
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800594a: e00a b.n 8005962 <HAL_RCC_ClockConfig+0x106>
{
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800594c: f7fc fbe2 bl 8002114 <HAL_GetTick>
8005950: 4602 mov r2, r0
8005952: 68fb ldr r3, [r7, #12]
8005954: 1ad3 subs r3, r2, r3
8005956: f241 3288 movw r2, #5000 @ 0x1388
800595a: 4293 cmp r3, r2
800595c: d901 bls.n 8005962 <HAL_RCC_ClockConfig+0x106>
{
return HAL_TIMEOUT;
800595e: 2303 movs r3, #3
8005960: e06e b.n 8005a40 <HAL_RCC_ClockConfig+0x1e4>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8005962: 4b3a ldr r3, [pc, #232] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005964: 689b ldr r3, [r3, #8]
8005966: f003 020c and.w r2, r3, #12
800596a: 687b ldr r3, [r7, #4]
800596c: 685b ldr r3, [r3, #4]
800596e: 009b lsls r3, r3, #2
8005970: 429a cmp r2, r3
8005972: d1eb bne.n 800594c <HAL_RCC_ClockConfig+0xf0>
}
#endif
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8005974: 687b ldr r3, [r7, #4]
8005976: 681b ldr r3, [r3, #0]
8005978: f003 0302 and.w r3, r3, #2
800597c: 2b00 cmp r3, #0
800597e: d010 beq.n 80059a2 <HAL_RCC_ClockConfig+0x146>
{
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
8005980: 687b ldr r3, [r7, #4]
8005982: 689a ldr r2, [r3, #8]
8005984: 4b31 ldr r3, [pc, #196] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005986: 689b ldr r3, [r3, #8]
8005988: f003 03f0 and.w r3, r3, #240 @ 0xf0
800598c: 429a cmp r2, r3
800598e: d208 bcs.n 80059a2 <HAL_RCC_ClockConfig+0x146>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8005990: 4b2e ldr r3, [pc, #184] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005992: 689b ldr r3, [r3, #8]
8005994: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8005998: 687b ldr r3, [r7, #4]
800599a: 689b ldr r3, [r3, #8]
800599c: 492b ldr r1, [pc, #172] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
800599e: 4313 orrs r3, r2
80059a0: 608b str r3, [r1, #8]
}
}
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80059a2: 4b29 ldr r3, [pc, #164] @ (8005a48 <HAL_RCC_ClockConfig+0x1ec>)
80059a4: 681b ldr r3, [r3, #0]
80059a6: f003 0307 and.w r3, r3, #7
80059aa: 683a ldr r2, [r7, #0]
80059ac: 429a cmp r2, r3
80059ae: d210 bcs.n 80059d2 <HAL_RCC_ClockConfig+0x176>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80059b0: 4b25 ldr r3, [pc, #148] @ (8005a48 <HAL_RCC_ClockConfig+0x1ec>)
80059b2: 681b ldr r3, [r3, #0]
80059b4: f023 0207 bic.w r2, r3, #7
80059b8: 4923 ldr r1, [pc, #140] @ (8005a48 <HAL_RCC_ClockConfig+0x1ec>)
80059ba: 683b ldr r3, [r7, #0]
80059bc: 4313 orrs r3, r2
80059be: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80059c0: 4b21 ldr r3, [pc, #132] @ (8005a48 <HAL_RCC_ClockConfig+0x1ec>)
80059c2: 681b ldr r3, [r3, #0]
80059c4: f003 0307 and.w r3, r3, #7
80059c8: 683a ldr r2, [r7, #0]
80059ca: 429a cmp r2, r3
80059cc: d001 beq.n 80059d2 <HAL_RCC_ClockConfig+0x176>
{
return HAL_ERROR;
80059ce: 2301 movs r3, #1
80059d0: e036 b.n 8005a40 <HAL_RCC_ClockConfig+0x1e4>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80059d2: 687b ldr r3, [r7, #4]
80059d4: 681b ldr r3, [r3, #0]
80059d6: f003 0304 and.w r3, r3, #4
80059da: 2b00 cmp r3, #0
80059dc: d008 beq.n 80059f0 <HAL_RCC_ClockConfig+0x194>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80059de: 4b1b ldr r3, [pc, #108] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
80059e0: 689b ldr r3, [r3, #8]
80059e2: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80059e6: 687b ldr r3, [r7, #4]
80059e8: 68db ldr r3, [r3, #12]
80059ea: 4918 ldr r1, [pc, #96] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
80059ec: 4313 orrs r3, r2
80059ee: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80059f0: 687b ldr r3, [r7, #4]
80059f2: 681b ldr r3, [r3, #0]
80059f4: f003 0308 and.w r3, r3, #8
80059f8: 2b00 cmp r3, #0
80059fa: d009 beq.n 8005a10 <HAL_RCC_ClockConfig+0x1b4>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80059fc: 4b13 ldr r3, [pc, #76] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
80059fe: 689b ldr r3, [r3, #8]
8005a00: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8005a04: 687b ldr r3, [r7, #4]
8005a06: 691b ldr r3, [r3, #16]
8005a08: 00db lsls r3, r3, #3
8005a0a: 4910 ldr r1, [pc, #64] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005a0c: 4313 orrs r3, r2
8005a0e: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8005a10: f000 f824 bl 8005a5c <HAL_RCC_GetSysClockFreq>
8005a14: 4602 mov r2, r0
8005a16: 4b0d ldr r3, [pc, #52] @ (8005a4c <HAL_RCC_ClockConfig+0x1f0>)
8005a18: 689b ldr r3, [r3, #8]
8005a1a: 091b lsrs r3, r3, #4
8005a1c: f003 030f and.w r3, r3, #15
8005a20: 490b ldr r1, [pc, #44] @ (8005a50 <HAL_RCC_ClockConfig+0x1f4>)
8005a22: 5ccb ldrb r3, [r1, r3]
8005a24: f003 031f and.w r3, r3, #31
8005a28: fa22 f303 lsr.w r3, r2, r3
8005a2c: 4a09 ldr r2, [pc, #36] @ (8005a54 <HAL_RCC_ClockConfig+0x1f8>)
8005a2e: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8005a30: 4b09 ldr r3, [pc, #36] @ (8005a58 <HAL_RCC_ClockConfig+0x1fc>)
8005a32: 681b ldr r3, [r3, #0]
8005a34: 4618 mov r0, r3
8005a36: f7fc fb1d bl 8002074 <HAL_InitTick>
8005a3a: 4603 mov r3, r0
8005a3c: 72fb strb r3, [r7, #11]
return status;
8005a3e: 7afb ldrb r3, [r7, #11]
}
8005a40: 4618 mov r0, r3
8005a42: 3710 adds r7, #16
8005a44: 46bd mov sp, r7
8005a46: bd80 pop {r7, pc}
8005a48: 40022000 .word 0x40022000
8005a4c: 40021000 .word 0x40021000
8005a50: 0800e1c0 .word 0x0800e1c0
8005a54: 20000000 .word 0x20000000
8005a58: 20000004 .word 0x20000004
08005a5c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8005a5c: b480 push {r7}
8005a5e: b089 sub sp, #36 @ 0x24
8005a60: af00 add r7, sp, #0
uint32_t msirange = 0U, sysclockfreq = 0U;
8005a62: 2300 movs r3, #0
8005a64: 61fb str r3, [r7, #28]
8005a66: 2300 movs r3, #0
8005a68: 61bb str r3, [r7, #24]
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
uint32_t sysclk_source, pll_oscsource;
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8005a6a: 4b3e ldr r3, [pc, #248] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005a6c: 689b ldr r3, [r3, #8]
8005a6e: f003 030c and.w r3, r3, #12
8005a72: 613b str r3, [r7, #16]
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
8005a74: 4b3b ldr r3, [pc, #236] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005a76: 68db ldr r3, [r3, #12]
8005a78: f003 0303 and.w r3, r3, #3
8005a7c: 60fb str r3, [r7, #12]
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
8005a7e: 693b ldr r3, [r7, #16]
8005a80: 2b00 cmp r3, #0
8005a82: d005 beq.n 8005a90 <HAL_RCC_GetSysClockFreq+0x34>
8005a84: 693b ldr r3, [r7, #16]
8005a86: 2b0c cmp r3, #12
8005a88: d121 bne.n 8005ace <HAL_RCC_GetSysClockFreq+0x72>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
8005a8a: 68fb ldr r3, [r7, #12]
8005a8c: 2b01 cmp r3, #1
8005a8e: d11e bne.n 8005ace <HAL_RCC_GetSysClockFreq+0x72>
{
/* MSI or PLL with MSI source used as system clock source */
/* Get SYSCLK source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
8005a90: 4b34 ldr r3, [pc, #208] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005a92: 681b ldr r3, [r3, #0]
8005a94: f003 0308 and.w r3, r3, #8
8005a98: 2b00 cmp r3, #0
8005a9a: d107 bne.n 8005aac <HAL_RCC_GetSysClockFreq+0x50>
{ /* MSISRANGE from RCC_CSR applies */
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
8005a9c: 4b31 ldr r3, [pc, #196] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005a9e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8005aa2: 0a1b lsrs r3, r3, #8
8005aa4: f003 030f and.w r3, r3, #15
8005aa8: 61fb str r3, [r7, #28]
8005aaa: e005 b.n 8005ab8 <HAL_RCC_GetSysClockFreq+0x5c>
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
8005aac: 4b2d ldr r3, [pc, #180] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005aae: 681b ldr r3, [r3, #0]
8005ab0: 091b lsrs r3, r3, #4
8005ab2: f003 030f and.w r3, r3, #15
8005ab6: 61fb str r3, [r7, #28]
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
8005ab8: 4a2b ldr r2, [pc, #172] @ (8005b68 <HAL_RCC_GetSysClockFreq+0x10c>)
8005aba: 69fb ldr r3, [r7, #28]
8005abc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8005ac0: 61fb str r3, [r7, #28]
if(sysclk_source == RCC_CFGR_SWS_MSI)
8005ac2: 693b ldr r3, [r7, #16]
8005ac4: 2b00 cmp r3, #0
8005ac6: d10d bne.n 8005ae4 <HAL_RCC_GetSysClockFreq+0x88>
{
/* MSI used as system clock source */
sysclockfreq = msirange;
8005ac8: 69fb ldr r3, [r7, #28]
8005aca: 61bb str r3, [r7, #24]
if(sysclk_source == RCC_CFGR_SWS_MSI)
8005acc: e00a b.n 8005ae4 <HAL_RCC_GetSysClockFreq+0x88>
}
}
else if(sysclk_source == RCC_CFGR_SWS_HSI)
8005ace: 693b ldr r3, [r7, #16]
8005ad0: 2b04 cmp r3, #4
8005ad2: d102 bne.n 8005ada <HAL_RCC_GetSysClockFreq+0x7e>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
8005ad4: 4b25 ldr r3, [pc, #148] @ (8005b6c <HAL_RCC_GetSysClockFreq+0x110>)
8005ad6: 61bb str r3, [r7, #24]
8005ad8: e004 b.n 8005ae4 <HAL_RCC_GetSysClockFreq+0x88>
}
else if(sysclk_source == RCC_CFGR_SWS_HSE)
8005ada: 693b ldr r3, [r7, #16]
8005adc: 2b08 cmp r3, #8
8005ade: d101 bne.n 8005ae4 <HAL_RCC_GetSysClockFreq+0x88>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8005ae0: 4b23 ldr r3, [pc, #140] @ (8005b70 <HAL_RCC_GetSysClockFreq+0x114>)
8005ae2: 61bb str r3, [r7, #24]
else
{
/* unexpected case: sysclockfreq at 0 */
}
if(sysclk_source == RCC_CFGR_SWS_PLL)
8005ae4: 693b ldr r3, [r7, #16]
8005ae6: 2b0c cmp r3, #12
8005ae8: d134 bne.n 8005b54 <HAL_RCC_GetSysClockFreq+0xf8>
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8005aea: 4b1e ldr r3, [pc, #120] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005aec: 68db ldr r3, [r3, #12]
8005aee: f003 0303 and.w r3, r3, #3
8005af2: 60bb str r3, [r7, #8]
switch (pllsource)
8005af4: 68bb ldr r3, [r7, #8]
8005af6: 2b02 cmp r3, #2
8005af8: d003 beq.n 8005b02 <HAL_RCC_GetSysClockFreq+0xa6>
8005afa: 68bb ldr r3, [r7, #8]
8005afc: 2b03 cmp r3, #3
8005afe: d003 beq.n 8005b08 <HAL_RCC_GetSysClockFreq+0xac>
8005b00: e005 b.n 8005b0e <HAL_RCC_GetSysClockFreq+0xb2>
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllvco = HSI_VALUE;
8005b02: 4b1a ldr r3, [pc, #104] @ (8005b6c <HAL_RCC_GetSysClockFreq+0x110>)
8005b04: 617b str r3, [r7, #20]
break;
8005b06: e005 b.n 8005b14 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = HSE_VALUE;
8005b08: 4b19 ldr r3, [pc, #100] @ (8005b70 <HAL_RCC_GetSysClockFreq+0x114>)
8005b0a: 617b str r3, [r7, #20]
break;
8005b0c: e002 b.n 8005b14 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default:
pllvco = msirange;
8005b0e: 69fb ldr r3, [r7, #28]
8005b10: 617b str r3, [r7, #20]
break;
8005b12: bf00 nop
}
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8005b14: 4b13 ldr r3, [pc, #76] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005b16: 68db ldr r3, [r3, #12]
8005b18: 091b lsrs r3, r3, #4
8005b1a: f003 0307 and.w r3, r3, #7
8005b1e: 3301 adds r3, #1
8005b20: 607b str r3, [r7, #4]
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
8005b22: 4b10 ldr r3, [pc, #64] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005b24: 68db ldr r3, [r3, #12]
8005b26: 0a1b lsrs r3, r3, #8
8005b28: f003 037f and.w r3, r3, #127 @ 0x7f
8005b2c: 697a ldr r2, [r7, #20]
8005b2e: fb03 f202 mul.w r2, r3, r2
8005b32: 687b ldr r3, [r7, #4]
8005b34: fbb2 f3f3 udiv r3, r2, r3
8005b38: 617b str r3, [r7, #20]
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8005b3a: 4b0a ldr r3, [pc, #40] @ (8005b64 <HAL_RCC_GetSysClockFreq+0x108>)
8005b3c: 68db ldr r3, [r3, #12]
8005b3e: 0e5b lsrs r3, r3, #25
8005b40: f003 0303 and.w r3, r3, #3
8005b44: 3301 adds r3, #1
8005b46: 005b lsls r3, r3, #1
8005b48: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllr;
8005b4a: 697a ldr r2, [r7, #20]
8005b4c: 683b ldr r3, [r7, #0]
8005b4e: fbb2 f3f3 udiv r3, r2, r3
8005b52: 61bb str r3, [r7, #24]
}
return sysclockfreq;
8005b54: 69bb ldr r3, [r7, #24]
}
8005b56: 4618 mov r0, r3
8005b58: 3724 adds r7, #36 @ 0x24
8005b5a: 46bd mov sp, r7
8005b5c: f85d 7b04 ldr.w r7, [sp], #4
8005b60: 4770 bx lr
8005b62: bf00 nop
8005b64: 40021000 .word 0x40021000
8005b68: 0800e1d8 .word 0x0800e1d8
8005b6c: 00f42400 .word 0x00f42400
8005b70: 007a1200 .word 0x007a1200
08005b74 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8005b74: b480 push {r7}
8005b76: af00 add r7, sp, #0
return SystemCoreClock;
8005b78: 4b03 ldr r3, [pc, #12] @ (8005b88 <HAL_RCC_GetHCLKFreq+0x14>)
8005b7a: 681b ldr r3, [r3, #0]
}
8005b7c: 4618 mov r0, r3
8005b7e: 46bd mov sp, r7
8005b80: f85d 7b04 ldr.w r7, [sp], #4
8005b84: 4770 bx lr
8005b86: bf00 nop
8005b88: 20000000 .word 0x20000000
08005b8c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8005b8c: b580 push {r7, lr}
8005b8e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
8005b90: f7ff fff0 bl 8005b74 <HAL_RCC_GetHCLKFreq>
8005b94: 4602 mov r2, r0
8005b96: 4b06 ldr r3, [pc, #24] @ (8005bb0 <HAL_RCC_GetPCLK1Freq+0x24>)
8005b98: 689b ldr r3, [r3, #8]
8005b9a: 0a1b lsrs r3, r3, #8
8005b9c: f003 0307 and.w r3, r3, #7
8005ba0: 4904 ldr r1, [pc, #16] @ (8005bb4 <HAL_RCC_GetPCLK1Freq+0x28>)
8005ba2: 5ccb ldrb r3, [r1, r3]
8005ba4: f003 031f and.w r3, r3, #31
8005ba8: fa22 f303 lsr.w r3, r2, r3
}
8005bac: 4618 mov r0, r3
8005bae: bd80 pop {r7, pc}
8005bb0: 40021000 .word 0x40021000
8005bb4: 0800e1d0 .word 0x0800e1d0
08005bb8 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8005bb8: b580 push {r7, lr}
8005bba: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
8005bbc: f7ff ffda bl 8005b74 <HAL_RCC_GetHCLKFreq>
8005bc0: 4602 mov r2, r0
8005bc2: 4b06 ldr r3, [pc, #24] @ (8005bdc <HAL_RCC_GetPCLK2Freq+0x24>)
8005bc4: 689b ldr r3, [r3, #8]
8005bc6: 0adb lsrs r3, r3, #11
8005bc8: f003 0307 and.w r3, r3, #7
8005bcc: 4904 ldr r1, [pc, #16] @ (8005be0 <HAL_RCC_GetPCLK2Freq+0x28>)
8005bce: 5ccb ldrb r3, [r1, r3]
8005bd0: f003 031f and.w r3, r3, #31
8005bd4: fa22 f303 lsr.w r3, r2, r3
}
8005bd8: 4618 mov r0, r3
8005bda: bd80 pop {r7, pc}
8005bdc: 40021000 .word 0x40021000
8005be0: 0800e1d0 .word 0x0800e1d0
08005be4 <RCC_SetFlashLatencyFromMSIRange>:
voltage range.
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
8005be4: b580 push {r7, lr}
8005be6: b086 sub sp, #24
8005be8: af00 add r7, sp, #0
8005bea: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
8005bec: 2300 movs r3, #0
8005bee: 613b str r3, [r7, #16]
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
8005bf0: 4b2a ldr r3, [pc, #168] @ (8005c9c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8005bf2: 6d9b ldr r3, [r3, #88] @ 0x58
8005bf4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005bf8: 2b00 cmp r3, #0
8005bfa: d003 beq.n 8005c04 <RCC_SetFlashLatencyFromMSIRange+0x20>
{
vos = HAL_PWREx_GetVoltageRange();
8005bfc: f7ff f922 bl 8004e44 <HAL_PWREx_GetVoltageRange>
8005c00: 6178 str r0, [r7, #20]
8005c02: e014 b.n 8005c2e <RCC_SetFlashLatencyFromMSIRange+0x4a>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
8005c04: 4b25 ldr r3, [pc, #148] @ (8005c9c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8005c06: 6d9b ldr r3, [r3, #88] @ 0x58
8005c08: 4a24 ldr r2, [pc, #144] @ (8005c9c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8005c0a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005c0e: 6593 str r3, [r2, #88] @ 0x58
8005c10: 4b22 ldr r3, [pc, #136] @ (8005c9c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8005c12: 6d9b ldr r3, [r3, #88] @ 0x58
8005c14: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005c18: 60fb str r3, [r7, #12]
8005c1a: 68fb ldr r3, [r7, #12]
vos = HAL_PWREx_GetVoltageRange();
8005c1c: f7ff f912 bl 8004e44 <HAL_PWREx_GetVoltageRange>
8005c20: 6178 str r0, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
8005c22: 4b1e ldr r3, [pc, #120] @ (8005c9c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8005c24: 6d9b ldr r3, [r3, #88] @ 0x58
8005c26: 4a1d ldr r2, [pc, #116] @ (8005c9c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8005c28: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005c2c: 6593 str r3, [r2, #88] @ 0x58
}
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
8005c2e: 697b ldr r3, [r7, #20]
8005c30: f5b3 7f00 cmp.w r3, #512 @ 0x200
8005c34: d10b bne.n 8005c4e <RCC_SetFlashLatencyFromMSIRange+0x6a>
{
if(msirange > RCC_MSIRANGE_8)
8005c36: 687b ldr r3, [r7, #4]
8005c38: 2b80 cmp r3, #128 @ 0x80
8005c3a: d919 bls.n 8005c70 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI > 16Mhz */
if(msirange > RCC_MSIRANGE_10)
8005c3c: 687b ldr r3, [r7, #4]
8005c3e: 2ba0 cmp r3, #160 @ 0xa0
8005c40: d902 bls.n 8005c48 <RCC_SetFlashLatencyFromMSIRange+0x64>
{
/* MSI 48Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
8005c42: 2302 movs r3, #2
8005c44: 613b str r3, [r7, #16]
8005c46: e013 b.n 8005c70 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
/* MSI 24Mhz or 32Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
8005c48: 2301 movs r3, #1
8005c4a: 613b str r3, [r7, #16]
8005c4c: e010 b.n 8005c70 <RCC_SetFlashLatencyFromMSIRange+0x8c>
latency = FLASH_LATENCY_1; /* 1WS */
}
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
}
#else
if(msirange > RCC_MSIRANGE_8)
8005c4e: 687b ldr r3, [r7, #4]
8005c50: 2b80 cmp r3, #128 @ 0x80
8005c52: d902 bls.n 8005c5a <RCC_SetFlashLatencyFromMSIRange+0x76>
{
/* MSI > 16Mhz */
latency = FLASH_LATENCY_3; /* 3WS */
8005c54: 2303 movs r3, #3
8005c56: 613b str r3, [r7, #16]
8005c58: e00a b.n 8005c70 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
if(msirange == RCC_MSIRANGE_8)
8005c5a: 687b ldr r3, [r7, #4]
8005c5c: 2b80 cmp r3, #128 @ 0x80
8005c5e: d102 bne.n 8005c66 <RCC_SetFlashLatencyFromMSIRange+0x82>
{
/* MSI 16Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
8005c60: 2302 movs r3, #2
8005c62: 613b str r3, [r7, #16]
8005c64: e004 b.n 8005c70 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else if(msirange == RCC_MSIRANGE_7)
8005c66: 687b ldr r3, [r7, #4]
8005c68: 2b70 cmp r3, #112 @ 0x70
8005c6a: d101 bne.n 8005c70 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
8005c6c: 2301 movs r3, #1
8005c6e: 613b str r3, [r7, #16]
}
}
#endif
}
__HAL_FLASH_SET_LATENCY(latency);
8005c70: 4b0b ldr r3, [pc, #44] @ (8005ca0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8005c72: 681b ldr r3, [r3, #0]
8005c74: f023 0207 bic.w r2, r3, #7
8005c78: 4909 ldr r1, [pc, #36] @ (8005ca0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8005c7a: 693b ldr r3, [r7, #16]
8005c7c: 4313 orrs r3, r2
8005c7e: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
8005c80: 4b07 ldr r3, [pc, #28] @ (8005ca0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8005c82: 681b ldr r3, [r3, #0]
8005c84: f003 0307 and.w r3, r3, #7
8005c88: 693a ldr r2, [r7, #16]
8005c8a: 429a cmp r2, r3
8005c8c: d001 beq.n 8005c92 <RCC_SetFlashLatencyFromMSIRange+0xae>
{
return HAL_ERROR;
8005c8e: 2301 movs r3, #1
8005c90: e000 b.n 8005c94 <RCC_SetFlashLatencyFromMSIRange+0xb0>
}
return HAL_OK;
8005c92: 2300 movs r3, #0
}
8005c94: 4618 mov r0, r3
8005c96: 3718 adds r7, #24
8005c98: 46bd mov sp, r7
8005c9a: bd80 pop {r7, pc}
8005c9c: 40021000 .word 0x40021000
8005ca0: 40022000 .word 0x40022000
08005ca4 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8005ca4: b580 push {r7, lr}
8005ca6: b086 sub sp, #24
8005ca8: af00 add r7, sp, #0
8005caa: 6078 str r0, [r7, #4]
uint32_t tmpregister, tickstart; /* no init needed */
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8005cac: 2300 movs r3, #0
8005cae: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8005cb0: 2300 movs r3, #0
8005cb2: 74bb strb r3, [r7, #18]
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
8005cb4: 687b ldr r3, [r7, #4]
8005cb6: 681b ldr r3, [r3, #0]
8005cb8: f403 6300 and.w r3, r3, #2048 @ 0x800
8005cbc: 2b00 cmp r3, #0
8005cbe: d041 beq.n 8005d44 <HAL_RCCEx_PeriphCLKConfig+0xa0>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
switch(PeriphClkInit->Sai1ClockSelection)
8005cc0: 687b ldr r3, [r7, #4]
8005cc2: 6e5b ldr r3, [r3, #100] @ 0x64
8005cc4: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
8005cc8: d02a beq.n 8005d20 <HAL_RCCEx_PeriphCLKConfig+0x7c>
8005cca: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
8005cce: d824 bhi.n 8005d1a <HAL_RCCEx_PeriphCLKConfig+0x76>
8005cd0: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
8005cd4: d008 beq.n 8005ce8 <HAL_RCCEx_PeriphCLKConfig+0x44>
8005cd6: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
8005cda: d81e bhi.n 8005d1a <HAL_RCCEx_PeriphCLKConfig+0x76>
8005cdc: 2b00 cmp r3, #0
8005cde: d00a beq.n 8005cf6 <HAL_RCCEx_PeriphCLKConfig+0x52>
8005ce0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8005ce4: d010 beq.n 8005d08 <HAL_RCCEx_PeriphCLKConfig+0x64>
8005ce6: e018 b.n 8005d1a <HAL_RCCEx_PeriphCLKConfig+0x76>
{
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
/* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
8005ce8: 4b86 ldr r3, [pc, #536] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005cea: 68db ldr r3, [r3, #12]
8005cec: 4a85 ldr r2, [pc, #532] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005cee: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8005cf2: 60d3 str r3, [r2, #12]
#else
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
/* SAI1 clock source config set later after clock selection check */
break;
8005cf4: e015 b.n 8005d22 <HAL_RCCEx_PeriphCLKConfig+0x7e>
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
8005cf6: 687b ldr r3, [r7, #4]
8005cf8: 3304 adds r3, #4
8005cfa: 2100 movs r1, #0
8005cfc: 4618 mov r0, r3
8005cfe: f000 facb bl 8006298 <RCCEx_PLLSAI1_Config>
8005d02: 4603 mov r3, r0
8005d04: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
8005d06: e00c b.n 8005d22 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#if defined(RCC_PLLSAI2_SUPPORT)
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
8005d08: 687b ldr r3, [r7, #4]
8005d0a: 3320 adds r3, #32
8005d0c: 2100 movs r1, #0
8005d0e: 4618 mov r0, r3
8005d10: f000 fbb6 bl 8006480 <RCCEx_PLLSAI2_Config>
8005d14: 4603 mov r3, r0
8005d16: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
8005d18: e003 b.n 8005d22 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI1 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
8005d1a: 2301 movs r3, #1
8005d1c: 74fb strb r3, [r7, #19]
break;
8005d1e: e000 b.n 8005d22 <HAL_RCCEx_PeriphCLKConfig+0x7e>
break;
8005d20: bf00 nop
}
if(ret == HAL_OK)
8005d22: 7cfb ldrb r3, [r7, #19]
8005d24: 2b00 cmp r3, #0
8005d26: d10b bne.n 8005d40 <HAL_RCCEx_PeriphCLKConfig+0x9c>
{
/* Set the source of SAI1 clock*/
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8005d28: 4b76 ldr r3, [pc, #472] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005d2a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005d2e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8005d32: 687b ldr r3, [r7, #4]
8005d34: 6e5b ldr r3, [r3, #100] @ 0x64
8005d36: 4973 ldr r1, [pc, #460] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005d38: 4313 orrs r3, r2
8005d3a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
8005d3e: e001 b.n 8005d44 <HAL_RCCEx_PeriphCLKConfig+0xa0>
}
else
{
/* set overall return value */
status = ret;
8005d40: 7cfb ldrb r3, [r7, #19]
8005d42: 74bb strb r3, [r7, #18]
#endif /* SAI1 */
#if defined(SAI2)
/*-------------------------- SAI2 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
8005d44: 687b ldr r3, [r7, #4]
8005d46: 681b ldr r3, [r3, #0]
8005d48: f403 5380 and.w r3, r3, #4096 @ 0x1000
8005d4c: 2b00 cmp r3, #0
8005d4e: d041 beq.n 8005dd4 <HAL_RCCEx_PeriphCLKConfig+0x130>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
switch(PeriphClkInit->Sai2ClockSelection)
8005d50: 687b ldr r3, [r7, #4]
8005d52: 6e9b ldr r3, [r3, #104] @ 0x68
8005d54: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
8005d58: d02a beq.n 8005db0 <HAL_RCCEx_PeriphCLKConfig+0x10c>
8005d5a: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
8005d5e: d824 bhi.n 8005daa <HAL_RCCEx_PeriphCLKConfig+0x106>
8005d60: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8005d64: d008 beq.n 8005d78 <HAL_RCCEx_PeriphCLKConfig+0xd4>
8005d66: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8005d6a: d81e bhi.n 8005daa <HAL_RCCEx_PeriphCLKConfig+0x106>
8005d6c: 2b00 cmp r3, #0
8005d6e: d00a beq.n 8005d86 <HAL_RCCEx_PeriphCLKConfig+0xe2>
8005d70: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8005d74: d010 beq.n 8005d98 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8005d76: e018 b.n 8005daa <HAL_RCCEx_PeriphCLKConfig+0x106>
{
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
/* Enable SAI Clock output generated from System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
8005d78: 4b62 ldr r3, [pc, #392] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005d7a: 68db ldr r3, [r3, #12]
8005d7c: 4a61 ldr r2, [pc, #388] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005d7e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8005d82: 60d3 str r3, [r2, #12]
/* SAI2 clock source config set later after clock selection check */
break;
8005d84: e015 b.n 8005db2 <HAL_RCCEx_PeriphCLKConfig+0x10e>
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
8005d86: 687b ldr r3, [r7, #4]
8005d88: 3304 adds r3, #4
8005d8a: 2100 movs r1, #0
8005d8c: 4618 mov r0, r3
8005d8e: f000 fa83 bl 8006298 <RCCEx_PLLSAI1_Config>
8005d92: 4603 mov r3, r0
8005d94: 74fb strb r3, [r7, #19]
/* SAI2 clock source config set later after clock selection check */
break;
8005d96: e00c b.n 8005db2 <HAL_RCCEx_PeriphCLKConfig+0x10e>
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
8005d98: 687b ldr r3, [r7, #4]
8005d9a: 3320 adds r3, #32
8005d9c: 2100 movs r1, #0
8005d9e: 4618 mov r0, r3
8005da0: f000 fb6e bl 8006480 <RCCEx_PLLSAI2_Config>
8005da4: 4603 mov r3, r0
8005da6: 74fb strb r3, [r7, #19]
/* SAI2 clock source config set later after clock selection check */
break;
8005da8: e003 b.n 8005db2 <HAL_RCCEx_PeriphCLKConfig+0x10e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI2 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
8005daa: 2301 movs r3, #1
8005dac: 74fb strb r3, [r7, #19]
break;
8005dae: e000 b.n 8005db2 <HAL_RCCEx_PeriphCLKConfig+0x10e>
break;
8005db0: bf00 nop
}
if(ret == HAL_OK)
8005db2: 7cfb ldrb r3, [r7, #19]
8005db4: 2b00 cmp r3, #0
8005db6: d10b bne.n 8005dd0 <HAL_RCCEx_PeriphCLKConfig+0x12c>
{
/* Set the source of SAI2 clock*/
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
8005db8: 4b52 ldr r3, [pc, #328] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005dba: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005dbe: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
8005dc2: 687b ldr r3, [r7, #4]
8005dc4: 6e9b ldr r3, [r3, #104] @ 0x68
8005dc6: 494f ldr r1, [pc, #316] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005dc8: 4313 orrs r3, r2
8005dca: f8c1 3088 str.w r3, [r1, #136] @ 0x88
8005dce: e001 b.n 8005dd4 <HAL_RCCEx_PeriphCLKConfig+0x130>
}
else
{
/* set overall return value */
status = ret;
8005dd0: 7cfb ldrb r3, [r7, #19]
8005dd2: 74bb strb r3, [r7, #18]
}
}
#endif /* SAI2 */
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8005dd4: 687b ldr r3, [r7, #4]
8005dd6: 681b ldr r3, [r3, #0]
8005dd8: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005ddc: 2b00 cmp r3, #0
8005dde: f000 80a0 beq.w 8005f22 <HAL_RCCEx_PeriphCLKConfig+0x27e>
{
FlagStatus pwrclkchanged = RESET;
8005de2: 2300 movs r3, #0
8005de4: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8005de6: 4b47 ldr r3, [pc, #284] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005de8: 6d9b ldr r3, [r3, #88] @ 0x58
8005dea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005dee: 2b00 cmp r3, #0
8005df0: d101 bne.n 8005df6 <HAL_RCCEx_PeriphCLKConfig+0x152>
8005df2: 2301 movs r3, #1
8005df4: e000 b.n 8005df8 <HAL_RCCEx_PeriphCLKConfig+0x154>
8005df6: 2300 movs r3, #0
8005df8: 2b00 cmp r3, #0
8005dfa: d00d beq.n 8005e18 <HAL_RCCEx_PeriphCLKConfig+0x174>
{
__HAL_RCC_PWR_CLK_ENABLE();
8005dfc: 4b41 ldr r3, [pc, #260] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005dfe: 6d9b ldr r3, [r3, #88] @ 0x58
8005e00: 4a40 ldr r2, [pc, #256] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e02: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005e06: 6593 str r3, [r2, #88] @ 0x58
8005e08: 4b3e ldr r3, [pc, #248] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e0a: 6d9b ldr r3, [r3, #88] @ 0x58
8005e0c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005e10: 60bb str r3, [r7, #8]
8005e12: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8005e14: 2301 movs r3, #1
8005e16: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8005e18: 4b3b ldr r3, [pc, #236] @ (8005f08 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8005e1a: 681b ldr r3, [r3, #0]
8005e1c: 4a3a ldr r2, [pc, #232] @ (8005f08 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8005e1e: f443 7380 orr.w r3, r3, #256 @ 0x100
8005e22: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8005e24: f7fc f976 bl 8002114 <HAL_GetTick>
8005e28: 60f8 str r0, [r7, #12]
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8005e2a: e009 b.n 8005e40 <HAL_RCCEx_PeriphCLKConfig+0x19c>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8005e2c: f7fc f972 bl 8002114 <HAL_GetTick>
8005e30: 4602 mov r2, r0
8005e32: 68fb ldr r3, [r7, #12]
8005e34: 1ad3 subs r3, r2, r3
8005e36: 2b02 cmp r3, #2
8005e38: d902 bls.n 8005e40 <HAL_RCCEx_PeriphCLKConfig+0x19c>
{
ret = HAL_TIMEOUT;
8005e3a: 2303 movs r3, #3
8005e3c: 74fb strb r3, [r7, #19]
break;
8005e3e: e005 b.n 8005e4c <HAL_RCCEx_PeriphCLKConfig+0x1a8>
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8005e40: 4b31 ldr r3, [pc, #196] @ (8005f08 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8005e42: 681b ldr r3, [r3, #0]
8005e44: f403 7380 and.w r3, r3, #256 @ 0x100
8005e48: 2b00 cmp r3, #0
8005e4a: d0ef beq.n 8005e2c <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
if(ret == HAL_OK)
8005e4c: 7cfb ldrb r3, [r7, #19]
8005e4e: 2b00 cmp r3, #0
8005e50: d15c bne.n 8005f0c <HAL_RCCEx_PeriphCLKConfig+0x268>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8005e52: 4b2c ldr r3, [pc, #176] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e54: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8005e58: f403 7340 and.w r3, r3, #768 @ 0x300
8005e5c: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8005e5e: 697b ldr r3, [r7, #20]
8005e60: 2b00 cmp r3, #0
8005e62: d01f beq.n 8005ea4 <HAL_RCCEx_PeriphCLKConfig+0x200>
8005e64: 687b ldr r3, [r7, #4]
8005e66: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8005e6a: 697a ldr r2, [r7, #20]
8005e6c: 429a cmp r2, r3
8005e6e: d019 beq.n 8005ea4 <HAL_RCCEx_PeriphCLKConfig+0x200>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8005e70: 4b24 ldr r3, [pc, #144] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e72: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8005e76: f423 7340 bic.w r3, r3, #768 @ 0x300
8005e7a: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8005e7c: 4b21 ldr r3, [pc, #132] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e7e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8005e82: 4a20 ldr r2, [pc, #128] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e84: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8005e88: f8c2 3090 str.w r3, [r2, #144] @ 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
8005e8c: 4b1d ldr r3, [pc, #116] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e8e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8005e92: 4a1c ldr r2, [pc, #112] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e94: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005e98: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8005e9c: 4a19 ldr r2, [pc, #100] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005e9e: 697b ldr r3, [r7, #20]
8005ea0: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8005ea4: 697b ldr r3, [r7, #20]
8005ea6: f003 0301 and.w r3, r3, #1
8005eaa: 2b00 cmp r3, #0
8005eac: d016 beq.n 8005edc <HAL_RCCEx_PeriphCLKConfig+0x238>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005eae: f7fc f931 bl 8002114 <HAL_GetTick>
8005eb2: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8005eb4: e00b b.n 8005ece <HAL_RCCEx_PeriphCLKConfig+0x22a>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005eb6: f7fc f92d bl 8002114 <HAL_GetTick>
8005eba: 4602 mov r2, r0
8005ebc: 68fb ldr r3, [r7, #12]
8005ebe: 1ad3 subs r3, r2, r3
8005ec0: f241 3288 movw r2, #5000 @ 0x1388
8005ec4: 4293 cmp r3, r2
8005ec6: d902 bls.n 8005ece <HAL_RCCEx_PeriphCLKConfig+0x22a>
{
ret = HAL_TIMEOUT;
8005ec8: 2303 movs r3, #3
8005eca: 74fb strb r3, [r7, #19]
break;
8005ecc: e006 b.n 8005edc <HAL_RCCEx_PeriphCLKConfig+0x238>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8005ece: 4b0d ldr r3, [pc, #52] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005ed0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8005ed4: f003 0302 and.w r3, r3, #2
8005ed8: 2b00 cmp r3, #0
8005eda: d0ec beq.n 8005eb6 <HAL_RCCEx_PeriphCLKConfig+0x212>
}
}
}
if(ret == HAL_OK)
8005edc: 7cfb ldrb r3, [r7, #19]
8005ede: 2b00 cmp r3, #0
8005ee0: d10c bne.n 8005efc <HAL_RCCEx_PeriphCLKConfig+0x258>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8005ee2: 4b08 ldr r3, [pc, #32] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005ee4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8005ee8: f423 7240 bic.w r2, r3, #768 @ 0x300
8005eec: 687b ldr r3, [r7, #4]
8005eee: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8005ef2: 4904 ldr r1, [pc, #16] @ (8005f04 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8005ef4: 4313 orrs r3, r2
8005ef6: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8005efa: e009 b.n 8005f10 <HAL_RCCEx_PeriphCLKConfig+0x26c>
}
else
{
/* set overall return value */
status = ret;
8005efc: 7cfb ldrb r3, [r7, #19]
8005efe: 74bb strb r3, [r7, #18]
8005f00: e006 b.n 8005f10 <HAL_RCCEx_PeriphCLKConfig+0x26c>
8005f02: bf00 nop
8005f04: 40021000 .word 0x40021000
8005f08: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8005f0c: 7cfb ldrb r3, [r7, #19]
8005f0e: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8005f10: 7c7b ldrb r3, [r7, #17]
8005f12: 2b01 cmp r3, #1
8005f14: d105 bne.n 8005f22 <HAL_RCCEx_PeriphCLKConfig+0x27e>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005f16: 4b9e ldr r3, [pc, #632] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f18: 6d9b ldr r3, [r3, #88] @ 0x58
8005f1a: 4a9d ldr r2, [pc, #628] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f1c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005f20: 6593 str r3, [r2, #88] @ 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8005f22: 687b ldr r3, [r7, #4]
8005f24: 681b ldr r3, [r3, #0]
8005f26: f003 0301 and.w r3, r3, #1
8005f2a: 2b00 cmp r3, #0
8005f2c: d00a beq.n 8005f44 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8005f2e: 4b98 ldr r3, [pc, #608] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f30: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005f34: f023 0203 bic.w r2, r3, #3
8005f38: 687b ldr r3, [r7, #4]
8005f3a: 6b9b ldr r3, [r3, #56] @ 0x38
8005f3c: 4994 ldr r1, [pc, #592] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f3e: 4313 orrs r3, r2
8005f40: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8005f44: 687b ldr r3, [r7, #4]
8005f46: 681b ldr r3, [r3, #0]
8005f48: f003 0302 and.w r3, r3, #2
8005f4c: 2b00 cmp r3, #0
8005f4e: d00a beq.n 8005f66 <HAL_RCCEx_PeriphCLKConfig+0x2c2>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8005f50: 4b8f ldr r3, [pc, #572] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f52: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005f56: f023 020c bic.w r2, r3, #12
8005f5a: 687b ldr r3, [r7, #4]
8005f5c: 6bdb ldr r3, [r3, #60] @ 0x3c
8005f5e: 498c ldr r1, [pc, #560] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f60: 4313 orrs r3, r2
8005f62: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8005f66: 687b ldr r3, [r7, #4]
8005f68: 681b ldr r3, [r3, #0]
8005f6a: f003 0304 and.w r3, r3, #4
8005f6e: 2b00 cmp r3, #0
8005f70: d00a beq.n 8005f88 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8005f72: 4b87 ldr r3, [pc, #540] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f74: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005f78: f023 0230 bic.w r2, r3, #48 @ 0x30
8005f7c: 687b ldr r3, [r7, #4]
8005f7e: 6c1b ldr r3, [r3, #64] @ 0x40
8005f80: 4983 ldr r1, [pc, #524] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f82: 4313 orrs r3, r2
8005f84: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* USART3 */
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8005f88: 687b ldr r3, [r7, #4]
8005f8a: 681b ldr r3, [r3, #0]
8005f8c: f003 0308 and.w r3, r3, #8
8005f90: 2b00 cmp r3, #0
8005f92: d00a beq.n 8005faa <HAL_RCCEx_PeriphCLKConfig+0x306>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8005f94: 4b7e ldr r3, [pc, #504] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005f96: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005f9a: f023 02c0 bic.w r2, r3, #192 @ 0xc0
8005f9e: 687b ldr r3, [r7, #4]
8005fa0: 6c5b ldr r3, [r3, #68] @ 0x44
8005fa2: 497b ldr r1, [pc, #492] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005fa4: 4313 orrs r3, r2
8005fa6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* UART4 */
#if defined(UART5)
/*-------------------------- UART5 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8005faa: 687b ldr r3, [r7, #4]
8005fac: 681b ldr r3, [r3, #0]
8005fae: f003 0310 and.w r3, r3, #16
8005fb2: 2b00 cmp r3, #0
8005fb4: d00a beq.n 8005fcc <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
8005fb6: 4b76 ldr r3, [pc, #472] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005fb8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005fbc: f423 7240 bic.w r2, r3, #768 @ 0x300
8005fc0: 687b ldr r3, [r7, #4]
8005fc2: 6c9b ldr r3, [r3, #72] @ 0x48
8005fc4: 4972 ldr r1, [pc, #456] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005fc6: 4313 orrs r3, r2
8005fc8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8005fcc: 687b ldr r3, [r7, #4]
8005fce: 681b ldr r3, [r3, #0]
8005fd0: f003 0320 and.w r3, r3, #32
8005fd4: 2b00 cmp r3, #0
8005fd6: d00a beq.n 8005fee <HAL_RCCEx_PeriphCLKConfig+0x34a>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUART1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8005fd8: 4b6d ldr r3, [pc, #436] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005fda: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005fde: f423 6240 bic.w r2, r3, #3072 @ 0xc00
8005fe2: 687b ldr r3, [r7, #4]
8005fe4: 6cdb ldr r3, [r3, #76] @ 0x4c
8005fe6: 496a ldr r1, [pc, #424] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005fe8: 4313 orrs r3, r2
8005fea: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
8005fee: 687b ldr r3, [r7, #4]
8005ff0: 681b ldr r3, [r3, #0]
8005ff2: f403 7300 and.w r3, r3, #512 @ 0x200
8005ff6: 2b00 cmp r3, #0
8005ff8: d00a beq.n 8006010 <HAL_RCCEx_PeriphCLKConfig+0x36c>
{
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8005ffa: 4b65 ldr r3, [pc, #404] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8005ffc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006000: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
8006004: 687b ldr r3, [r7, #4]
8006006: 6ddb ldr r3, [r3, #92] @ 0x5c
8006008: 4961 ldr r1, [pc, #388] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800600a: 4313 orrs r3, r2
800600c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
8006010: 687b ldr r3, [r7, #4]
8006012: 681b ldr r3, [r3, #0]
8006014: f403 6380 and.w r3, r3, #1024 @ 0x400
8006018: 2b00 cmp r3, #0
800601a: d00a beq.n 8006032 <HAL_RCCEx_PeriphCLKConfig+0x38e>
{
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
800601c: 4b5c ldr r3, [pc, #368] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800601e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006022: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8006026: 687b ldr r3, [r7, #4]
8006028: 6e1b ldr r3, [r3, #96] @ 0x60
800602a: 4959 ldr r1, [pc, #356] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800602c: 4313 orrs r3, r2
800602e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8006032: 687b ldr r3, [r7, #4]
8006034: 681b ldr r3, [r3, #0]
8006036: f003 0340 and.w r3, r3, #64 @ 0x40
800603a: 2b00 cmp r3, #0
800603c: d00a beq.n 8006054 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
800603e: 4b54 ldr r3, [pc, #336] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006040: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006044: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8006048: 687b ldr r3, [r7, #4]
800604a: 6d1b ldr r3, [r3, #80] @ 0x50
800604c: 4950 ldr r1, [pc, #320] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800604e: 4313 orrs r3, r2
8006050: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(I2C2)
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8006054: 687b ldr r3, [r7, #4]
8006056: 681b ldr r3, [r3, #0]
8006058: f003 0380 and.w r3, r3, #128 @ 0x80
800605c: 2b00 cmp r3, #0
800605e: d00a beq.n 8006076 <HAL_RCCEx_PeriphCLKConfig+0x3d2>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8006060: 4b4b ldr r3, [pc, #300] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006062: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006066: f423 4240 bic.w r2, r3, #49152 @ 0xc000
800606a: 687b ldr r3, [r7, #4]
800606c: 6d5b ldr r3, [r3, #84] @ 0x54
800606e: 4948 ldr r1, [pc, #288] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006070: 4313 orrs r3, r2
8006072: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* I2C2 */
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8006076: 687b ldr r3, [r7, #4]
8006078: 681b ldr r3, [r3, #0]
800607a: f403 7380 and.w r3, r3, #256 @ 0x100
800607e: 2b00 cmp r3, #0
8006080: d00a beq.n 8006098 <HAL_RCCEx_PeriphCLKConfig+0x3f4>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8006082: 4b43 ldr r3, [pc, #268] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006084: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006088: f423 3240 bic.w r2, r3, #196608 @ 0x30000
800608c: 687b ldr r3, [r7, #4]
800608e: 6d9b ldr r3, [r3, #88] @ 0x58
8006090: 493f ldr r1, [pc, #252] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006092: 4313 orrs r3, r2
8006094: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* I2C4 */
#if defined(USB_OTG_FS) || defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
8006098: 687b ldr r3, [r7, #4]
800609a: 681b ldr r3, [r3, #0]
800609c: f403 5300 and.w r3, r3, #8192 @ 0x2000
80060a0: 2b00 cmp r3, #0
80060a2: d028 beq.n 80060f6 <HAL_RCCEx_PeriphCLKConfig+0x452>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
80060a4: 4b3a ldr r3, [pc, #232] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80060a6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80060aa: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
80060ae: 687b ldr r3, [r7, #4]
80060b0: 6edb ldr r3, [r3, #108] @ 0x6c
80060b2: 4937 ldr r1, [pc, #220] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80060b4: 4313 orrs r3, r2
80060b6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
80060ba: 687b ldr r3, [r7, #4]
80060bc: 6edb ldr r3, [r3, #108] @ 0x6c
80060be: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80060c2: d106 bne.n 80060d2 <HAL_RCCEx_PeriphCLKConfig+0x42e>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80060c4: 4b32 ldr r3, [pc, #200] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80060c6: 68db ldr r3, [r3, #12]
80060c8: 4a31 ldr r2, [pc, #196] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80060ca: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80060ce: 60d3 str r3, [r2, #12]
80060d0: e011 b.n 80060f6 <HAL_RCCEx_PeriphCLKConfig+0x452>
}
else
{
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
80060d2: 687b ldr r3, [r7, #4]
80060d4: 6edb ldr r3, [r3, #108] @ 0x6c
80060d6: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
80060da: d10c bne.n 80060f6 <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
80060dc: 687b ldr r3, [r7, #4]
80060de: 3304 adds r3, #4
80060e0: 2101 movs r1, #1
80060e2: 4618 mov r0, r3
80060e4: f000 f8d8 bl 8006298 <RCCEx_PLLSAI1_Config>
80060e8: 4603 mov r3, r0
80060ea: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
80060ec: 7cfb ldrb r3, [r7, #19]
80060ee: 2b00 cmp r3, #0
80060f0: d001 beq.n 80060f6 <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* set overall return value */
status = ret;
80060f2: 7cfb ldrb r3, [r7, #19]
80060f4: 74bb strb r3, [r7, #18]
#endif /* USB_OTG_FS || USB */
#if defined(SDMMC1)
/*-------------------------- SDMMC1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
80060f6: 687b ldr r3, [r7, #4]
80060f8: 681b ldr r3, [r3, #0]
80060fa: f403 2300 and.w r3, r3, #524288 @ 0x80000
80060fe: 2b00 cmp r3, #0
8006100: d028 beq.n 8006154 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
8006102: 4b23 ldr r3, [pc, #140] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006104: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006108: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
800610c: 687b ldr r3, [r7, #4]
800610e: 6f1b ldr r3, [r3, #112] @ 0x70
8006110: 491f ldr r1, [pc, #124] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006112: 4313 orrs r3, r2
8006114: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
8006118: 687b ldr r3, [r7, #4]
800611a: 6f1b ldr r3, [r3, #112] @ 0x70
800611c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8006120: d106 bne.n 8006130 <HAL_RCCEx_PeriphCLKConfig+0x48c>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8006122: 4b1b ldr r3, [pc, #108] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006124: 68db ldr r3, [r3, #12]
8006126: 4a1a ldr r2, [pc, #104] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006128: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800612c: 60d3 str r3, [r2, #12]
800612e: e011 b.n 8006154 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* Enable PLLSAI3CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
}
#endif
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
8006130: 687b ldr r3, [r7, #4]
8006132: 6f1b ldr r3, [r3, #112] @ 0x70
8006134: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
8006138: d10c bne.n 8006154 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
800613a: 687b ldr r3, [r7, #4]
800613c: 3304 adds r3, #4
800613e: 2101 movs r1, #1
8006140: 4618 mov r0, r3
8006142: f000 f8a9 bl 8006298 <RCCEx_PLLSAI1_Config>
8006146: 4603 mov r3, r0
8006148: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
800614a: 7cfb ldrb r3, [r7, #19]
800614c: 2b00 cmp r3, #0
800614e: d001 beq.n 8006154 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* set overall return value */
status = ret;
8006150: 7cfb ldrb r3, [r7, #19]
8006152: 74bb strb r3, [r7, #18]
}
#endif /* SDMMC1 */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
8006154: 687b ldr r3, [r7, #4]
8006156: 681b ldr r3, [r3, #0]
8006158: f403 2380 and.w r3, r3, #262144 @ 0x40000
800615c: 2b00 cmp r3, #0
800615e: d02b beq.n 80061b8 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
8006160: 4b0b ldr r3, [pc, #44] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006162: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006166: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
800616a: 687b ldr r3, [r7, #4]
800616c: 6f5b ldr r3, [r3, #116] @ 0x74
800616e: 4908 ldr r1, [pc, #32] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006170: 4313 orrs r3, r2
8006172: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
8006176: 687b ldr r3, [r7, #4]
8006178: 6f5b ldr r3, [r3, #116] @ 0x74
800617a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
800617e: d109 bne.n 8006194 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8006180: 4b03 ldr r3, [pc, #12] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006182: 68db ldr r3, [r3, #12]
8006184: 4a02 ldr r2, [pc, #8] @ (8006190 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8006186: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800618a: 60d3 str r3, [r2, #12]
800618c: e014 b.n 80061b8 <HAL_RCCEx_PeriphCLKConfig+0x514>
800618e: bf00 nop
8006190: 40021000 .word 0x40021000
}
#if defined(RCC_PLLSAI1_SUPPORT)
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
8006194: 687b ldr r3, [r7, #4]
8006196: 6f5b ldr r3, [r3, #116] @ 0x74
8006198: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
800619c: d10c bne.n 80061b8 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
800619e: 687b ldr r3, [r7, #4]
80061a0: 3304 adds r3, #4
80061a2: 2101 movs r1, #1
80061a4: 4618 mov r0, r3
80061a6: f000 f877 bl 8006298 <RCCEx_PLLSAI1_Config>
80061aa: 4603 mov r3, r0
80061ac: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
80061ae: 7cfb ldrb r3, [r7, #19]
80061b0: 2b00 cmp r3, #0
80061b2: d001 beq.n 80061b8 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* set overall return value */
status = ret;
80061b4: 7cfb ldrb r3, [r7, #19]
80061b6: 74bb strb r3, [r7, #18]
}
}
/*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
80061b8: 687b ldr r3, [r7, #4]
80061ba: 681b ldr r3, [r3, #0]
80061bc: f403 4380 and.w r3, r3, #16384 @ 0x4000
80061c0: 2b00 cmp r3, #0
80061c2: d02f beq.n 8006224 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
80061c4: 4b2b ldr r3, [pc, #172] @ (8006274 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
80061c6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80061ca: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
80061ce: 687b ldr r3, [r7, #4]
80061d0: 6f9b ldr r3, [r3, #120] @ 0x78
80061d2: 4928 ldr r1, [pc, #160] @ (8006274 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
80061d4: 4313 orrs r3, r2
80061d6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
80061da: 687b ldr r3, [r7, #4]
80061dc: 6f9b ldr r3, [r3, #120] @ 0x78
80061de: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
80061e2: d10d bne.n 8006200 <HAL_RCCEx_PeriphCLKConfig+0x55c>
{
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
80061e4: 687b ldr r3, [r7, #4]
80061e6: 3304 adds r3, #4
80061e8: 2102 movs r1, #2
80061ea: 4618 mov r0, r3
80061ec: f000 f854 bl 8006298 <RCCEx_PLLSAI1_Config>
80061f0: 4603 mov r3, r0
80061f2: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
80061f4: 7cfb ldrb r3, [r7, #19]
80061f6: 2b00 cmp r3, #0
80061f8: d014 beq.n 8006224 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* set overall return value */
status = ret;
80061fa: 7cfb ldrb r3, [r7, #19]
80061fc: 74bb strb r3, [r7, #18]
80061fe: e011 b.n 8006224 <HAL_RCCEx_PeriphCLKConfig+0x580>
}
#endif /* RCC_PLLSAI1_SUPPORT */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
8006200: 687b ldr r3, [r7, #4]
8006202: 6f9b ldr r3, [r3, #120] @ 0x78
8006204: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8006208: d10c bne.n 8006224 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
800620a: 687b ldr r3, [r7, #4]
800620c: 3320 adds r3, #32
800620e: 2102 movs r1, #2
8006210: 4618 mov r0, r3
8006212: f000 f935 bl 8006480 <RCCEx_PLLSAI2_Config>
8006216: 4603 mov r3, r0
8006218: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
800621a: 7cfb ldrb r3, [r7, #19]
800621c: 2b00 cmp r3, #0
800621e: d001 beq.n 8006224 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* set overall return value */
status = ret;
8006220: 7cfb ldrb r3, [r7, #19]
8006222: 74bb strb r3, [r7, #18]
#endif /* !STM32L412xx && !STM32L422xx */
#if defined(SWPMI1)
/*-------------------------- SWPMI1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
8006224: 687b ldr r3, [r7, #4]
8006226: 681b ldr r3, [r3, #0]
8006228: f403 4300 and.w r3, r3, #32768 @ 0x8000
800622c: 2b00 cmp r3, #0
800622e: d00a beq.n 8006246 <HAL_RCCEx_PeriphCLKConfig+0x5a2>
{
/* Check the parameters */
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
/* Configure the SWPMI1 clock source */
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
8006230: 4b10 ldr r3, [pc, #64] @ (8006274 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8006232: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006236: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000
800623a: 687b ldr r3, [r7, #4]
800623c: 6fdb ldr r3, [r3, #124] @ 0x7c
800623e: 490d ldr r1, [pc, #52] @ (8006274 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8006240: 4313 orrs r3, r2
8006242: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* SWPMI1 */
#if defined(DFSDM1_Filter0)
/*-------------------------- DFSDM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
8006246: 687b ldr r3, [r7, #4]
8006248: 681b ldr r3, [r3, #0]
800624a: f403 3380 and.w r3, r3, #65536 @ 0x10000
800624e: 2b00 cmp r3, #0
8006250: d00b beq.n 800626a <HAL_RCCEx_PeriphCLKConfig+0x5c6>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
/* Configure the DFSDM1 interface clock source */
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
8006252: 4b08 ldr r3, [pc, #32] @ (8006274 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8006254: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006258: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
800625c: 687b ldr r3, [r7, #4]
800625e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006262: 4904 ldr r1, [pc, #16] @ (8006274 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8006264: 4313 orrs r3, r2
8006266: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
}
#endif /* OCTOSPI1 || OCTOSPI2 */
return status;
800626a: 7cbb ldrb r3, [r7, #18]
}
800626c: 4618 mov r0, r3
800626e: 3718 adds r7, #24
8006270: 46bd mov sp, r7
8006272: bd80 pop {r7, pc}
8006274: 40021000 .word 0x40021000
08006278 <HAL_RCCEx_EnableMSIPLLMode>:
* @note Prior to enable the PLL-mode of the MSI for automatic hardware
* calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
* @retval None
*/
void HAL_RCCEx_EnableMSIPLLMode(void)
{
8006278: b480 push {r7}
800627a: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
800627c: 4b05 ldr r3, [pc, #20] @ (8006294 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
800627e: 681b ldr r3, [r3, #0]
8006280: 4a04 ldr r2, [pc, #16] @ (8006294 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
8006282: f043 0304 orr.w r3, r3, #4
8006286: 6013 str r3, [r2, #0]
}
8006288: bf00 nop
800628a: 46bd mov sp, r7
800628c: f85d 7b04 ldr.w r7, [sp], #4
8006290: 4770 bx lr
8006292: bf00 nop
8006294: 40021000 .word 0x40021000
08006298 <RCCEx_PLLSAI1_Config>:
* @note PLLSAI1 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
8006298: b580 push {r7, lr}
800629a: b084 sub sp, #16
800629c: af00 add r7, sp, #0
800629e: 6078 str r0, [r7, #4]
80062a0: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
80062a2: 2300 movs r3, #0
80062a4: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
/* Check that PLLSAI1 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
80062a6: 4b75 ldr r3, [pc, #468] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
80062a8: 68db ldr r3, [r3, #12]
80062aa: f003 0303 and.w r3, r3, #3
80062ae: 2b00 cmp r3, #0
80062b0: d018 beq.n 80062e4 <RCCEx_PLLSAI1_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
80062b2: 4b72 ldr r3, [pc, #456] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
80062b4: 68db ldr r3, [r3, #12]
80062b6: f003 0203 and.w r2, r3, #3
80062ba: 687b ldr r3, [r7, #4]
80062bc: 681b ldr r3, [r3, #0]
80062be: 429a cmp r2, r3
80062c0: d10d bne.n 80062de <RCCEx_PLLSAI1_Config+0x46>
||
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
80062c2: 687b ldr r3, [r7, #4]
80062c4: 681b ldr r3, [r3, #0]
||
80062c6: 2b00 cmp r3, #0
80062c8: d009 beq.n 80062de <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
80062ca: 4b6c ldr r3, [pc, #432] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
80062cc: 68db ldr r3, [r3, #12]
80062ce: 091b lsrs r3, r3, #4
80062d0: f003 0307 and.w r3, r3, #7
80062d4: 1c5a adds r2, r3, #1
80062d6: 687b ldr r3, [r7, #4]
80062d8: 685b ldr r3, [r3, #4]
||
80062da: 429a cmp r2, r3
80062dc: d047 beq.n 800636e <RCCEx_PLLSAI1_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
80062de: 2301 movs r3, #1
80062e0: 73fb strb r3, [r7, #15]
80062e2: e044 b.n 800636e <RCCEx_PLLSAI1_Config+0xd6>
}
}
else
{
/* Check PLLSAI1 clock source availability */
switch(PllSai1->PLLSAI1Source)
80062e4: 687b ldr r3, [r7, #4]
80062e6: 681b ldr r3, [r3, #0]
80062e8: 2b03 cmp r3, #3
80062ea: d018 beq.n 800631e <RCCEx_PLLSAI1_Config+0x86>
80062ec: 2b03 cmp r3, #3
80062ee: d825 bhi.n 800633c <RCCEx_PLLSAI1_Config+0xa4>
80062f0: 2b01 cmp r3, #1
80062f2: d002 beq.n 80062fa <RCCEx_PLLSAI1_Config+0x62>
80062f4: 2b02 cmp r3, #2
80062f6: d009 beq.n 800630c <RCCEx_PLLSAI1_Config+0x74>
80062f8: e020 b.n 800633c <RCCEx_PLLSAI1_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
80062fa: 4b60 ldr r3, [pc, #384] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
80062fc: 681b ldr r3, [r3, #0]
80062fe: f003 0302 and.w r3, r3, #2
8006302: 2b00 cmp r3, #0
8006304: d11d bne.n 8006342 <RCCEx_PLLSAI1_Config+0xaa>
{
status = HAL_ERROR;
8006306: 2301 movs r3, #1
8006308: 73fb strb r3, [r7, #15]
}
break;
800630a: e01a b.n 8006342 <RCCEx_PLLSAI1_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
800630c: 4b5b ldr r3, [pc, #364] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
800630e: 681b ldr r3, [r3, #0]
8006310: f403 6380 and.w r3, r3, #1024 @ 0x400
8006314: 2b00 cmp r3, #0
8006316: d116 bne.n 8006346 <RCCEx_PLLSAI1_Config+0xae>
{
status = HAL_ERROR;
8006318: 2301 movs r3, #1
800631a: 73fb strb r3, [r7, #15]
}
break;
800631c: e013 b.n 8006346 <RCCEx_PLLSAI1_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
800631e: 4b57 ldr r3, [pc, #348] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
8006320: 681b ldr r3, [r3, #0]
8006322: f403 3300 and.w r3, r3, #131072 @ 0x20000
8006326: 2b00 cmp r3, #0
8006328: d10f bne.n 800634a <RCCEx_PLLSAI1_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
800632a: 4b54 ldr r3, [pc, #336] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
800632c: 681b ldr r3, [r3, #0]
800632e: f403 2380 and.w r3, r3, #262144 @ 0x40000
8006332: 2b00 cmp r3, #0
8006334: d109 bne.n 800634a <RCCEx_PLLSAI1_Config+0xb2>
{
status = HAL_ERROR;
8006336: 2301 movs r3, #1
8006338: 73fb strb r3, [r7, #15]
}
}
break;
800633a: e006 b.n 800634a <RCCEx_PLLSAI1_Config+0xb2>
default:
status = HAL_ERROR;
800633c: 2301 movs r3, #1
800633e: 73fb strb r3, [r7, #15]
break;
8006340: e004 b.n 800634c <RCCEx_PLLSAI1_Config+0xb4>
break;
8006342: bf00 nop
8006344: e002 b.n 800634c <RCCEx_PLLSAI1_Config+0xb4>
break;
8006346: bf00 nop
8006348: e000 b.n 800634c <RCCEx_PLLSAI1_Config+0xb4>
break;
800634a: bf00 nop
}
if(status == HAL_OK)
800634c: 7bfb ldrb r3, [r7, #15]
800634e: 2b00 cmp r3, #0
8006350: d10d bne.n 800636e <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
/* Set PLLSAI1 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
/* Set PLLSAI1 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
8006352: 4b4a ldr r3, [pc, #296] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
8006354: 68db ldr r3, [r3, #12]
8006356: f023 0273 bic.w r2, r3, #115 @ 0x73
800635a: 687b ldr r3, [r7, #4]
800635c: 6819 ldr r1, [r3, #0]
800635e: 687b ldr r3, [r7, #4]
8006360: 685b ldr r3, [r3, #4]
8006362: 3b01 subs r3, #1
8006364: 011b lsls r3, r3, #4
8006366: 430b orrs r3, r1
8006368: 4944 ldr r1, [pc, #272] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
800636a: 4313 orrs r3, r2
800636c: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
800636e: 7bfb ldrb r3, [r7, #15]
8006370: 2b00 cmp r3, #0
8006372: d17d bne.n 8006470 <RCCEx_PLLSAI1_Config+0x1d8>
{
/* Disable the PLLSAI1 */
__HAL_RCC_PLLSAI1_DISABLE();
8006374: 4b41 ldr r3, [pc, #260] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
8006376: 681b ldr r3, [r3, #0]
8006378: 4a40 ldr r2, [pc, #256] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
800637a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
800637e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006380: f7fb fec8 bl 8002114 <HAL_GetTick>
8006384: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
8006386: e009 b.n 800639c <RCCEx_PLLSAI1_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
8006388: f7fb fec4 bl 8002114 <HAL_GetTick>
800638c: 4602 mov r2, r0
800638e: 68bb ldr r3, [r7, #8]
8006390: 1ad3 subs r3, r2, r3
8006392: 2b02 cmp r3, #2
8006394: d902 bls.n 800639c <RCCEx_PLLSAI1_Config+0x104>
{
status = HAL_TIMEOUT;
8006396: 2303 movs r3, #3
8006398: 73fb strb r3, [r7, #15]
break;
800639a: e005 b.n 80063a8 <RCCEx_PLLSAI1_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
800639c: 4b37 ldr r3, [pc, #220] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
800639e: 681b ldr r3, [r3, #0]
80063a0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
80063a4: 2b00 cmp r3, #0
80063a6: d1ef bne.n 8006388 <RCCEx_PLLSAI1_Config+0xf0>
}
}
if(status == HAL_OK)
80063a8: 7bfb ldrb r3, [r7, #15]
80063aa: 2b00 cmp r3, #0
80063ac: d160 bne.n 8006470 <RCCEx_PLLSAI1_Config+0x1d8>
{
if(Divider == DIVIDER_P_UPDATE)
80063ae: 683b ldr r3, [r7, #0]
80063b0: 2b00 cmp r3, #0
80063b2: d111 bne.n 80063d8 <RCCEx_PLLSAI1_Config+0x140>
MODIFY_REG(RCC->PLLSAI1CFGR,
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI1CFGR,
80063b4: 4b31 ldr r3, [pc, #196] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
80063b6: 691b ldr r3, [r3, #16]
80063b8: f423 331f bic.w r3, r3, #162816 @ 0x27c00
80063bc: f423 7340 bic.w r3, r3, #768 @ 0x300
80063c0: 687a ldr r2, [r7, #4]
80063c2: 6892 ldr r2, [r2, #8]
80063c4: 0211 lsls r1, r2, #8
80063c6: 687a ldr r2, [r7, #4]
80063c8: 68d2 ldr r2, [r2, #12]
80063ca: 0912 lsrs r2, r2, #4
80063cc: 0452 lsls r2, r2, #17
80063ce: 430a orrs r2, r1
80063d0: 492a ldr r1, [pc, #168] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
80063d2: 4313 orrs r3, r2
80063d4: 610b str r3, [r1, #16]
80063d6: e027 b.n 8006428 <RCCEx_PLLSAI1_Config+0x190>
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
else if(Divider == DIVIDER_Q_UPDATE)
80063d8: 683b ldr r3, [r7, #0]
80063da: 2b01 cmp r3, #1
80063dc: d112 bne.n 8006404 <RCCEx_PLLSAI1_Config+0x16c>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
80063de: 4b27 ldr r3, [pc, #156] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
80063e0: 691b ldr r3, [r3, #16]
80063e2: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000
80063e6: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
80063ea: 687a ldr r2, [r7, #4]
80063ec: 6892 ldr r2, [r2, #8]
80063ee: 0211 lsls r1, r2, #8
80063f0: 687a ldr r2, [r7, #4]
80063f2: 6912 ldr r2, [r2, #16]
80063f4: 0852 lsrs r2, r2, #1
80063f6: 3a01 subs r2, #1
80063f8: 0552 lsls r2, r2, #21
80063fa: 430a orrs r2, r1
80063fc: 491f ldr r1, [pc, #124] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
80063fe: 4313 orrs r3, r2
8006400: 610b str r3, [r1, #16]
8006402: e011 b.n 8006428 <RCCEx_PLLSAI1_Config+0x190>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
8006404: 4b1d ldr r3, [pc, #116] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
8006406: 691b ldr r3, [r3, #16]
8006408: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
800640c: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
8006410: 687a ldr r2, [r7, #4]
8006412: 6892 ldr r2, [r2, #8]
8006414: 0211 lsls r1, r2, #8
8006416: 687a ldr r2, [r7, #4]
8006418: 6952 ldr r2, [r2, #20]
800641a: 0852 lsrs r2, r2, #1
800641c: 3a01 subs r2, #1
800641e: 0652 lsls r2, r2, #25
8006420: 430a orrs r2, r1
8006422: 4916 ldr r1, [pc, #88] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
8006424: 4313 orrs r3, r2
8006426: 610b str r3, [r1, #16]
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
__HAL_RCC_PLLSAI1_ENABLE();
8006428: 4b14 ldr r3, [pc, #80] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
800642a: 681b ldr r3, [r3, #0]
800642c: 4a13 ldr r2, [pc, #76] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
800642e: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8006432: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006434: f7fb fe6e bl 8002114 <HAL_GetTick>
8006438: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
800643a: e009 b.n 8006450 <RCCEx_PLLSAI1_Config+0x1b8>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
800643c: f7fb fe6a bl 8002114 <HAL_GetTick>
8006440: 4602 mov r2, r0
8006442: 68bb ldr r3, [r7, #8]
8006444: 1ad3 subs r3, r2, r3
8006446: 2b02 cmp r3, #2
8006448: d902 bls.n 8006450 <RCCEx_PLLSAI1_Config+0x1b8>
{
status = HAL_TIMEOUT;
800644a: 2303 movs r3, #3
800644c: 73fb strb r3, [r7, #15]
break;
800644e: e005 b.n 800645c <RCCEx_PLLSAI1_Config+0x1c4>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
8006450: 4b0a ldr r3, [pc, #40] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
8006452: 681b ldr r3, [r3, #0]
8006454: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8006458: 2b00 cmp r3, #0
800645a: d0ef beq.n 800643c <RCCEx_PLLSAI1_Config+0x1a4>
}
}
if(status == HAL_OK)
800645c: 7bfb ldrb r3, [r7, #15]
800645e: 2b00 cmp r3, #0
8006460: d106 bne.n 8006470 <RCCEx_PLLSAI1_Config+0x1d8>
{
/* Configure the PLLSAI1 Clock output(s) */
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
8006462: 4b06 ldr r3, [pc, #24] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
8006464: 691a ldr r2, [r3, #16]
8006466: 687b ldr r3, [r7, #4]
8006468: 699b ldr r3, [r3, #24]
800646a: 4904 ldr r1, [pc, #16] @ (800647c <RCCEx_PLLSAI1_Config+0x1e4>)
800646c: 4313 orrs r3, r2
800646e: 610b str r3, [r1, #16]
}
}
}
return status;
8006470: 7bfb ldrb r3, [r7, #15]
}
8006472: 4618 mov r0, r3
8006474: 3710 adds r7, #16
8006476: 46bd mov sp, r7
8006478: bd80 pop {r7, pc}
800647a: bf00 nop
800647c: 40021000 .word 0x40021000
08006480 <RCCEx_PLLSAI2_Config>:
* @note PLLSAI2 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
{
8006480: b580 push {r7, lr}
8006482: b084 sub sp, #16
8006484: af00 add r7, sp, #0
8006486: 6078 str r0, [r7, #4]
8006488: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
800648a: 2300 movs r3, #0
800648c: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
/* Check that PLLSAI2 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
800648e: 4b6a ldr r3, [pc, #424] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
8006490: 68db ldr r3, [r3, #12]
8006492: f003 0303 and.w r3, r3, #3
8006496: 2b00 cmp r3, #0
8006498: d018 beq.n 80064cc <RCCEx_PLLSAI2_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
800649a: 4b67 ldr r3, [pc, #412] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
800649c: 68db ldr r3, [r3, #12]
800649e: f003 0203 and.w r2, r3, #3
80064a2: 687b ldr r3, [r7, #4]
80064a4: 681b ldr r3, [r3, #0]
80064a6: 429a cmp r2, r3
80064a8: d10d bne.n 80064c6 <RCCEx_PLLSAI2_Config+0x46>
||
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
80064aa: 687b ldr r3, [r7, #4]
80064ac: 681b ldr r3, [r3, #0]
||
80064ae: 2b00 cmp r3, #0
80064b0: d009 beq.n 80064c6 <RCCEx_PLLSAI2_Config+0x46>
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
80064b2: 4b61 ldr r3, [pc, #388] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
80064b4: 68db ldr r3, [r3, #12]
80064b6: 091b lsrs r3, r3, #4
80064b8: f003 0307 and.w r3, r3, #7
80064bc: 1c5a adds r2, r3, #1
80064be: 687b ldr r3, [r7, #4]
80064c0: 685b ldr r3, [r3, #4]
||
80064c2: 429a cmp r2, r3
80064c4: d047 beq.n 8006556 <RCCEx_PLLSAI2_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
80064c6: 2301 movs r3, #1
80064c8: 73fb strb r3, [r7, #15]
80064ca: e044 b.n 8006556 <RCCEx_PLLSAI2_Config+0xd6>
}
}
else
{
/* Check PLLSAI2 clock source availability */
switch(PllSai2->PLLSAI2Source)
80064cc: 687b ldr r3, [r7, #4]
80064ce: 681b ldr r3, [r3, #0]
80064d0: 2b03 cmp r3, #3
80064d2: d018 beq.n 8006506 <RCCEx_PLLSAI2_Config+0x86>
80064d4: 2b03 cmp r3, #3
80064d6: d825 bhi.n 8006524 <RCCEx_PLLSAI2_Config+0xa4>
80064d8: 2b01 cmp r3, #1
80064da: d002 beq.n 80064e2 <RCCEx_PLLSAI2_Config+0x62>
80064dc: 2b02 cmp r3, #2
80064de: d009 beq.n 80064f4 <RCCEx_PLLSAI2_Config+0x74>
80064e0: e020 b.n 8006524 <RCCEx_PLLSAI2_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
80064e2: 4b55 ldr r3, [pc, #340] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
80064e4: 681b ldr r3, [r3, #0]
80064e6: f003 0302 and.w r3, r3, #2
80064ea: 2b00 cmp r3, #0
80064ec: d11d bne.n 800652a <RCCEx_PLLSAI2_Config+0xaa>
{
status = HAL_ERROR;
80064ee: 2301 movs r3, #1
80064f0: 73fb strb r3, [r7, #15]
}
break;
80064f2: e01a b.n 800652a <RCCEx_PLLSAI2_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
80064f4: 4b50 ldr r3, [pc, #320] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
80064f6: 681b ldr r3, [r3, #0]
80064f8: f403 6380 and.w r3, r3, #1024 @ 0x400
80064fc: 2b00 cmp r3, #0
80064fe: d116 bne.n 800652e <RCCEx_PLLSAI2_Config+0xae>
{
status = HAL_ERROR;
8006500: 2301 movs r3, #1
8006502: 73fb strb r3, [r7, #15]
}
break;
8006504: e013 b.n 800652e <RCCEx_PLLSAI2_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
8006506: 4b4c ldr r3, [pc, #304] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
8006508: 681b ldr r3, [r3, #0]
800650a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800650e: 2b00 cmp r3, #0
8006510: d10f bne.n 8006532 <RCCEx_PLLSAI2_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
8006512: 4b49 ldr r3, [pc, #292] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
8006514: 681b ldr r3, [r3, #0]
8006516: f403 2380 and.w r3, r3, #262144 @ 0x40000
800651a: 2b00 cmp r3, #0
800651c: d109 bne.n 8006532 <RCCEx_PLLSAI2_Config+0xb2>
{
status = HAL_ERROR;
800651e: 2301 movs r3, #1
8006520: 73fb strb r3, [r7, #15]
}
}
break;
8006522: e006 b.n 8006532 <RCCEx_PLLSAI2_Config+0xb2>
default:
status = HAL_ERROR;
8006524: 2301 movs r3, #1
8006526: 73fb strb r3, [r7, #15]
break;
8006528: e004 b.n 8006534 <RCCEx_PLLSAI2_Config+0xb4>
break;
800652a: bf00 nop
800652c: e002 b.n 8006534 <RCCEx_PLLSAI2_Config+0xb4>
break;
800652e: bf00 nop
8006530: e000 b.n 8006534 <RCCEx_PLLSAI2_Config+0xb4>
break;
8006532: bf00 nop
}
if(status == HAL_OK)
8006534: 7bfb ldrb r3, [r7, #15]
8006536: 2b00 cmp r3, #0
8006538: d10d bne.n 8006556 <RCCEx_PLLSAI2_Config+0xd6>
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
/* Set PLLSAI2 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
#else
/* Set PLLSAI2 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
800653a: 4b3f ldr r3, [pc, #252] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
800653c: 68db ldr r3, [r3, #12]
800653e: f023 0273 bic.w r2, r3, #115 @ 0x73
8006542: 687b ldr r3, [r7, #4]
8006544: 6819 ldr r1, [r3, #0]
8006546: 687b ldr r3, [r7, #4]
8006548: 685b ldr r3, [r3, #4]
800654a: 3b01 subs r3, #1
800654c: 011b lsls r3, r3, #4
800654e: 430b orrs r3, r1
8006550: 4939 ldr r1, [pc, #228] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
8006552: 4313 orrs r3, r2
8006554: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
8006556: 7bfb ldrb r3, [r7, #15]
8006558: 2b00 cmp r3, #0
800655a: d167 bne.n 800662c <RCCEx_PLLSAI2_Config+0x1ac>
{
/* Disable the PLLSAI2 */
__HAL_RCC_PLLSAI2_DISABLE();
800655c: 4b36 ldr r3, [pc, #216] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
800655e: 681b ldr r3, [r3, #0]
8006560: 4a35 ldr r2, [pc, #212] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
8006562: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8006566: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006568: f7fb fdd4 bl 8002114 <HAL_GetTick>
800656c: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI2 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
800656e: e009 b.n 8006584 <RCCEx_PLLSAI2_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
8006570: f7fb fdd0 bl 8002114 <HAL_GetTick>
8006574: 4602 mov r2, r0
8006576: 68bb ldr r3, [r7, #8]
8006578: 1ad3 subs r3, r2, r3
800657a: 2b02 cmp r3, #2
800657c: d902 bls.n 8006584 <RCCEx_PLLSAI2_Config+0x104>
{
status = HAL_TIMEOUT;
800657e: 2303 movs r3, #3
8006580: 73fb strb r3, [r7, #15]
break;
8006582: e005 b.n 8006590 <RCCEx_PLLSAI2_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
8006584: 4b2c ldr r3, [pc, #176] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
8006586: 681b ldr r3, [r3, #0]
8006588: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
800658c: 2b00 cmp r3, #0
800658e: d1ef bne.n 8006570 <RCCEx_PLLSAI2_Config+0xf0>
}
}
if(status == HAL_OK)
8006590: 7bfb ldrb r3, [r7, #15]
8006592: 2b00 cmp r3, #0
8006594: d14a bne.n 800662c <RCCEx_PLLSAI2_Config+0x1ac>
{
if(Divider == DIVIDER_P_UPDATE)
8006596: 683b ldr r3, [r7, #0]
8006598: 2b00 cmp r3, #0
800659a: d111 bne.n 80065c0 <RCCEx_PLLSAI2_Config+0x140>
MODIFY_REG(RCC->PLLSAI2CFGR,
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI2CFGR,
800659c: 4b26 ldr r3, [pc, #152] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
800659e: 695b ldr r3, [r3, #20]
80065a0: f423 331f bic.w r3, r3, #162816 @ 0x27c00
80065a4: f423 7340 bic.w r3, r3, #768 @ 0x300
80065a8: 687a ldr r2, [r7, #4]
80065aa: 6892 ldr r2, [r2, #8]
80065ac: 0211 lsls r1, r2, #8
80065ae: 687a ldr r2, [r7, #4]
80065b0: 68d2 ldr r2, [r2, #12]
80065b2: 0912 lsrs r2, r2, #4
80065b4: 0452 lsls r2, r2, #17
80065b6: 430a orrs r2, r1
80065b8: 491f ldr r1, [pc, #124] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
80065ba: 4313 orrs r3, r2
80065bc: 614b str r3, [r1, #20]
80065be: e011 b.n 80065e4 <RCCEx_PLLSAI2_Config+0x164>
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
#else
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI2CFGR,
80065c0: 4b1d ldr r3, [pc, #116] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
80065c2: 695b ldr r3, [r3, #20]
80065c4: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
80065c8: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
80065cc: 687a ldr r2, [r7, #4]
80065ce: 6892 ldr r2, [r2, #8]
80065d0: 0211 lsls r1, r2, #8
80065d2: 687a ldr r2, [r7, #4]
80065d4: 6912 ldr r2, [r2, #16]
80065d6: 0852 lsrs r2, r2, #1
80065d8: 3a01 subs r2, #1
80065da: 0652 lsls r2, r2, #25
80065dc: 430a orrs r2, r1
80065de: 4916 ldr r1, [pc, #88] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
80065e0: 4313 orrs r3, r2
80065e2: 614b str r3, [r1, #20]
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
__HAL_RCC_PLLSAI2_ENABLE();
80065e4: 4b14 ldr r3, [pc, #80] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
80065e6: 681b ldr r3, [r3, #0]
80065e8: 4a13 ldr r2, [pc, #76] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
80065ea: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80065ee: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80065f0: f7fb fd90 bl 8002114 <HAL_GetTick>
80065f4: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI2 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
80065f6: e009 b.n 800660c <RCCEx_PLLSAI2_Config+0x18c>
{
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
80065f8: f7fb fd8c bl 8002114 <HAL_GetTick>
80065fc: 4602 mov r2, r0
80065fe: 68bb ldr r3, [r7, #8]
8006600: 1ad3 subs r3, r2, r3
8006602: 2b02 cmp r3, #2
8006604: d902 bls.n 800660c <RCCEx_PLLSAI2_Config+0x18c>
{
status = HAL_TIMEOUT;
8006606: 2303 movs r3, #3
8006608: 73fb strb r3, [r7, #15]
break;
800660a: e005 b.n 8006618 <RCCEx_PLLSAI2_Config+0x198>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
800660c: 4b0a ldr r3, [pc, #40] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
800660e: 681b ldr r3, [r3, #0]
8006610: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8006614: 2b00 cmp r3, #0
8006616: d0ef beq.n 80065f8 <RCCEx_PLLSAI2_Config+0x178>
}
}
if(status == HAL_OK)
8006618: 7bfb ldrb r3, [r7, #15]
800661a: 2b00 cmp r3, #0
800661c: d106 bne.n 800662c <RCCEx_PLLSAI2_Config+0x1ac>
{
/* Configure the PLLSAI2 Clock output(s) */
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
800661e: 4b06 ldr r3, [pc, #24] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
8006620: 695a ldr r2, [r3, #20]
8006622: 687b ldr r3, [r7, #4]
8006624: 695b ldr r3, [r3, #20]
8006626: 4904 ldr r1, [pc, #16] @ (8006638 <RCCEx_PLLSAI2_Config+0x1b8>)
8006628: 4313 orrs r3, r2
800662a: 614b str r3, [r1, #20]
}
}
}
return status;
800662c: 7bfb ldrb r3, [r7, #15]
}
800662e: 4618 mov r0, r3
8006630: 3710 adds r7, #16
8006632: 46bd mov sp, r7
8006634: bd80 pop {r7, pc}
8006636: bf00 nop
8006638: 40021000 .word 0x40021000
0800663c <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
800663c: b580 push {r7, lr}
800663e: b084 sub sp, #16
8006640: af00 add r7, sp, #0
8006642: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
8006644: 687b ldr r3, [r7, #4]
8006646: 2b00 cmp r3, #0
8006648: d101 bne.n 800664e <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
800664a: 2301 movs r3, #1
800664c: e095 b.n 800677a <HAL_SPI_Init+0x13e>
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
800664e: 687b ldr r3, [r7, #4]
8006650: 6a5b ldr r3, [r3, #36] @ 0x24
8006652: 2b00 cmp r3, #0
8006654: d108 bne.n 8006668 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8006656: 687b ldr r3, [r7, #4]
8006658: 685b ldr r3, [r3, #4]
800665a: f5b3 7f82 cmp.w r3, #260 @ 0x104
800665e: d009 beq.n 8006674 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8006660: 687b ldr r3, [r7, #4]
8006662: 2200 movs r2, #0
8006664: 61da str r2, [r3, #28]
8006666: e005 b.n 8006674 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8006668: 687b ldr r3, [r7, #4]
800666a: 2200 movs r2, #0
800666c: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
800666e: 687b ldr r3, [r7, #4]
8006670: 2200 movs r2, #0
8006672: 615a str r2, [r3, #20]
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8006674: 687b ldr r3, [r7, #4]
8006676: 2200 movs r2, #0
8006678: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
800667a: 687b ldr r3, [r7, #4]
800667c: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
8006680: b2db uxtb r3, r3
8006682: 2b00 cmp r3, #0
8006684: d106 bne.n 8006694 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8006686: 687b ldr r3, [r7, #4]
8006688: 2200 movs r2, #0
800668a: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
800668e: 6878 ldr r0, [r7, #4]
8006690: f7fb fa0a bl 8001aa8 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8006694: 687b ldr r3, [r7, #4]
8006696: 2202 movs r2, #2
8006698: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
800669c: 687b ldr r3, [r7, #4]
800669e: 681b ldr r3, [r3, #0]
80066a0: 681a ldr r2, [r3, #0]
80066a2: 687b ldr r3, [r7, #4]
80066a4: 681b ldr r3, [r3, #0]
80066a6: f022 0240 bic.w r2, r2, #64 @ 0x40
80066aa: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
80066ac: 687b ldr r3, [r7, #4]
80066ae: 68db ldr r3, [r3, #12]
80066b0: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
80066b4: d902 bls.n 80066bc <HAL_SPI_Init+0x80>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
80066b6: 2300 movs r3, #0
80066b8: 60fb str r3, [r7, #12]
80066ba: e002 b.n 80066c2 <HAL_SPI_Init+0x86>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
80066bc: f44f 5380 mov.w r3, #4096 @ 0x1000
80066c0: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
80066c2: 687b ldr r3, [r7, #4]
80066c4: 68db ldr r3, [r3, #12]
80066c6: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
80066ca: d007 beq.n 80066dc <HAL_SPI_Init+0xa0>
80066cc: 687b ldr r3, [r7, #4]
80066ce: 68db ldr r3, [r3, #12]
80066d0: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
80066d4: d002 beq.n 80066dc <HAL_SPI_Init+0xa0>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80066d6: 687b ldr r3, [r7, #4]
80066d8: 2200 movs r2, #0
80066da: 629a str r2, [r3, #40] @ 0x28
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
80066dc: 687b ldr r3, [r7, #4]
80066de: 685b ldr r3, [r3, #4]
80066e0: f403 7282 and.w r2, r3, #260 @ 0x104
80066e4: 687b ldr r3, [r7, #4]
80066e6: 689b ldr r3, [r3, #8]
80066e8: f403 4304 and.w r3, r3, #33792 @ 0x8400
80066ec: 431a orrs r2, r3
80066ee: 687b ldr r3, [r7, #4]
80066f0: 691b ldr r3, [r3, #16]
80066f2: f003 0302 and.w r3, r3, #2
80066f6: 431a orrs r2, r3
80066f8: 687b ldr r3, [r7, #4]
80066fa: 695b ldr r3, [r3, #20]
80066fc: f003 0301 and.w r3, r3, #1
8006700: 431a orrs r2, r3
8006702: 687b ldr r3, [r7, #4]
8006704: 699b ldr r3, [r3, #24]
8006706: f403 7300 and.w r3, r3, #512 @ 0x200
800670a: 431a orrs r2, r3
800670c: 687b ldr r3, [r7, #4]
800670e: 69db ldr r3, [r3, #28]
8006710: f003 0338 and.w r3, r3, #56 @ 0x38
8006714: 431a orrs r2, r3
8006716: 687b ldr r3, [r7, #4]
8006718: 6a1b ldr r3, [r3, #32]
800671a: f003 0380 and.w r3, r3, #128 @ 0x80
800671e: ea42 0103 orr.w r1, r2, r3
8006722: 687b ldr r3, [r7, #4]
8006724: 6a9b ldr r3, [r3, #40] @ 0x28
8006726: f403 5200 and.w r2, r3, #8192 @ 0x2000
800672a: 687b ldr r3, [r7, #4]
800672c: 681b ldr r3, [r3, #0]
800672e: 430a orrs r2, r1
8006730: 601a str r2, [r3, #0]
}
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
8006732: 687b ldr r3, [r7, #4]
8006734: 699b ldr r3, [r3, #24]
8006736: 0c1b lsrs r3, r3, #16
8006738: f003 0204 and.w r2, r3, #4
800673c: 687b ldr r3, [r7, #4]
800673e: 6a5b ldr r3, [r3, #36] @ 0x24
8006740: f003 0310 and.w r3, r3, #16
8006744: 431a orrs r2, r3
8006746: 687b ldr r3, [r7, #4]
8006748: 6b5b ldr r3, [r3, #52] @ 0x34
800674a: f003 0308 and.w r3, r3, #8
800674e: 431a orrs r2, r3
8006750: 687b ldr r3, [r7, #4]
8006752: 68db ldr r3, [r3, #12]
8006754: f403 6370 and.w r3, r3, #3840 @ 0xf00
8006758: ea42 0103 orr.w r1, r2, r3
800675c: 68fb ldr r3, [r7, #12]
800675e: f403 5280 and.w r2, r3, #4096 @ 0x1000
8006762: 687b ldr r3, [r7, #4]
8006764: 681b ldr r3, [r3, #0]
8006766: 430a orrs r2, r1
8006768: 605a str r2, [r3, #4]
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800676a: 687b ldr r3, [r7, #4]
800676c: 2200 movs r2, #0
800676e: 661a str r2, [r3, #96] @ 0x60
hspi->State = HAL_SPI_STATE_READY;
8006770: 687b ldr r3, [r7, #4]
8006772: 2201 movs r2, #1
8006774: f883 205d strb.w r2, [r3, #93] @ 0x5d
return HAL_OK;
8006778: 2300 movs r3, #0
}
800677a: 4618 mov r0, r3
800677c: 3710 adds r7, #16
800677e: 46bd mov sp, r7
8006780: bd80 pop {r7, pc}
08006782 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8006782: b580 push {r7, lr}
8006784: b082 sub sp, #8
8006786: af00 add r7, sp, #0
8006788: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800678a: 687b ldr r3, [r7, #4]
800678c: 2b00 cmp r3, #0
800678e: d101 bne.n 8006794 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8006790: 2301 movs r3, #1
8006792: e049 b.n 8006828 <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8006794: 687b ldr r3, [r7, #4]
8006796: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
800679a: b2db uxtb r3, r3
800679c: 2b00 cmp r3, #0
800679e: d106 bne.n 80067ae <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80067a0: 687b ldr r3, [r7, #4]
80067a2: 2200 movs r2, #0
80067a4: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80067a8: 6878 ldr r0, [r7, #4]
80067aa: f7fb f9df bl 8001b6c <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80067ae: 687b ldr r3, [r7, #4]
80067b0: 2202 movs r2, #2
80067b2: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80067b6: 687b ldr r3, [r7, #4]
80067b8: 681a ldr r2, [r3, #0]
80067ba: 687b ldr r3, [r7, #4]
80067bc: 3304 adds r3, #4
80067be: 4619 mov r1, r3
80067c0: 4610 mov r0, r2
80067c2: f000 fad9 bl 8006d78 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80067c6: 687b ldr r3, [r7, #4]
80067c8: 2201 movs r2, #1
80067ca: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80067ce: 687b ldr r3, [r7, #4]
80067d0: 2201 movs r2, #1
80067d2: f883 203e strb.w r2, [r3, #62] @ 0x3e
80067d6: 687b ldr r3, [r7, #4]
80067d8: 2201 movs r2, #1
80067da: f883 203f strb.w r2, [r3, #63] @ 0x3f
80067de: 687b ldr r3, [r7, #4]
80067e0: 2201 movs r2, #1
80067e2: f883 2040 strb.w r2, [r3, #64] @ 0x40
80067e6: 687b ldr r3, [r7, #4]
80067e8: 2201 movs r2, #1
80067ea: f883 2041 strb.w r2, [r3, #65] @ 0x41
80067ee: 687b ldr r3, [r7, #4]
80067f0: 2201 movs r2, #1
80067f2: f883 2042 strb.w r2, [r3, #66] @ 0x42
80067f6: 687b ldr r3, [r7, #4]
80067f8: 2201 movs r2, #1
80067fa: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80067fe: 687b ldr r3, [r7, #4]
8006800: 2201 movs r2, #1
8006802: f883 2044 strb.w r2, [r3, #68] @ 0x44
8006806: 687b ldr r3, [r7, #4]
8006808: 2201 movs r2, #1
800680a: f883 2045 strb.w r2, [r3, #69] @ 0x45
800680e: 687b ldr r3, [r7, #4]
8006810: 2201 movs r2, #1
8006812: f883 2046 strb.w r2, [r3, #70] @ 0x46
8006816: 687b ldr r3, [r7, #4]
8006818: 2201 movs r2, #1
800681a: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
800681e: 687b ldr r3, [r7, #4]
8006820: 2201 movs r2, #1
8006822: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8006826: 2300 movs r3, #0
}
8006828: 4618 mov r0, r3
800682a: 3708 adds r7, #8
800682c: 46bd mov sp, r7
800682e: bd80 pop {r7, pc}
08006830 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8006830: b580 push {r7, lr}
8006832: b082 sub sp, #8
8006834: af00 add r7, sp, #0
8006836: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8006838: 687b ldr r3, [r7, #4]
800683a: 2b00 cmp r3, #0
800683c: d101 bne.n 8006842 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
800683e: 2301 movs r3, #1
8006840: e049 b.n 80068d6 <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8006842: 687b ldr r3, [r7, #4]
8006844: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8006848: b2db uxtb r3, r3
800684a: 2b00 cmp r3, #0
800684c: d106 bne.n 800685c <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
800684e: 687b ldr r3, [r7, #4]
8006850: 2200 movs r2, #0
8006852: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8006856: 6878 ldr r0, [r7, #4]
8006858: f7fb f96a bl 8001b30 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800685c: 687b ldr r3, [r7, #4]
800685e: 2202 movs r2, #2
8006860: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8006864: 687b ldr r3, [r7, #4]
8006866: 681a ldr r2, [r3, #0]
8006868: 687b ldr r3, [r7, #4]
800686a: 3304 adds r3, #4
800686c: 4619 mov r1, r3
800686e: 4610 mov r0, r2
8006870: f000 fa82 bl 8006d78 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8006874: 687b ldr r3, [r7, #4]
8006876: 2201 movs r2, #1
8006878: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800687c: 687b ldr r3, [r7, #4]
800687e: 2201 movs r2, #1
8006880: f883 203e strb.w r2, [r3, #62] @ 0x3e
8006884: 687b ldr r3, [r7, #4]
8006886: 2201 movs r2, #1
8006888: f883 203f strb.w r2, [r3, #63] @ 0x3f
800688c: 687b ldr r3, [r7, #4]
800688e: 2201 movs r2, #1
8006890: f883 2040 strb.w r2, [r3, #64] @ 0x40
8006894: 687b ldr r3, [r7, #4]
8006896: 2201 movs r2, #1
8006898: f883 2041 strb.w r2, [r3, #65] @ 0x41
800689c: 687b ldr r3, [r7, #4]
800689e: 2201 movs r2, #1
80068a0: f883 2042 strb.w r2, [r3, #66] @ 0x42
80068a4: 687b ldr r3, [r7, #4]
80068a6: 2201 movs r2, #1
80068a8: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80068ac: 687b ldr r3, [r7, #4]
80068ae: 2201 movs r2, #1
80068b0: f883 2044 strb.w r2, [r3, #68] @ 0x44
80068b4: 687b ldr r3, [r7, #4]
80068b6: 2201 movs r2, #1
80068b8: f883 2045 strb.w r2, [r3, #69] @ 0x45
80068bc: 687b ldr r3, [r7, #4]
80068be: 2201 movs r2, #1
80068c0: f883 2046 strb.w r2, [r3, #70] @ 0x46
80068c4: 687b ldr r3, [r7, #4]
80068c6: 2201 movs r2, #1
80068c8: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80068cc: 687b ldr r3, [r7, #4]
80068ce: 2201 movs r2, #1
80068d0: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
80068d4: 2300 movs r3, #0
}
80068d6: 4618 mov r0, r3
80068d8: 3708 adds r7, #8
80068da: 46bd mov sp, r7
80068dc: bd80 pop {r7, pc}
080068de <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
80068de: b580 push {r7, lr}
80068e0: b084 sub sp, #16
80068e2: af00 add r7, sp, #0
80068e4: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
80068e6: 687b ldr r3, [r7, #4]
80068e8: 681b ldr r3, [r3, #0]
80068ea: 68db ldr r3, [r3, #12]
80068ec: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
80068ee: 687b ldr r3, [r7, #4]
80068f0: 681b ldr r3, [r3, #0]
80068f2: 691b ldr r3, [r3, #16]
80068f4: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
80068f6: 68bb ldr r3, [r7, #8]
80068f8: f003 0302 and.w r3, r3, #2
80068fc: 2b00 cmp r3, #0
80068fe: d020 beq.n 8006942 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
8006900: 68fb ldr r3, [r7, #12]
8006902: f003 0302 and.w r3, r3, #2
8006906: 2b00 cmp r3, #0
8006908: d01b beq.n 8006942 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
800690a: 687b ldr r3, [r7, #4]
800690c: 681b ldr r3, [r3, #0]
800690e: f06f 0202 mvn.w r2, #2
8006912: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8006914: 687b ldr r3, [r7, #4]
8006916: 2201 movs r2, #1
8006918: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
800691a: 687b ldr r3, [r7, #4]
800691c: 681b ldr r3, [r3, #0]
800691e: 699b ldr r3, [r3, #24]
8006920: f003 0303 and.w r3, r3, #3
8006924: 2b00 cmp r3, #0
8006926: d003 beq.n 8006930 <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8006928: 6878 ldr r0, [r7, #4]
800692a: f000 fa07 bl 8006d3c <HAL_TIM_IC_CaptureCallback>
800692e: e005 b.n 800693c <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8006930: 6878 ldr r0, [r7, #4]
8006932: f000 f9f9 bl 8006d28 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8006936: 6878 ldr r0, [r7, #4]
8006938: f000 fa0a bl 8006d50 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800693c: 687b ldr r3, [r7, #4]
800693e: 2200 movs r2, #0
8006940: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8006942: 68bb ldr r3, [r7, #8]
8006944: f003 0304 and.w r3, r3, #4
8006948: 2b00 cmp r3, #0
800694a: d020 beq.n 800698e <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
800694c: 68fb ldr r3, [r7, #12]
800694e: f003 0304 and.w r3, r3, #4
8006952: 2b00 cmp r3, #0
8006954: d01b beq.n 800698e <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8006956: 687b ldr r3, [r7, #4]
8006958: 681b ldr r3, [r3, #0]
800695a: f06f 0204 mvn.w r2, #4
800695e: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8006960: 687b ldr r3, [r7, #4]
8006962: 2202 movs r2, #2
8006964: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8006966: 687b ldr r3, [r7, #4]
8006968: 681b ldr r3, [r3, #0]
800696a: 699b ldr r3, [r3, #24]
800696c: f403 7340 and.w r3, r3, #768 @ 0x300
8006970: 2b00 cmp r3, #0
8006972: d003 beq.n 800697c <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8006974: 6878 ldr r0, [r7, #4]
8006976: f000 f9e1 bl 8006d3c <HAL_TIM_IC_CaptureCallback>
800697a: e005 b.n 8006988 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800697c: 6878 ldr r0, [r7, #4]
800697e: f000 f9d3 bl 8006d28 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8006982: 6878 ldr r0, [r7, #4]
8006984: f000 f9e4 bl 8006d50 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8006988: 687b ldr r3, [r7, #4]
800698a: 2200 movs r2, #0
800698c: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
800698e: 68bb ldr r3, [r7, #8]
8006990: f003 0308 and.w r3, r3, #8
8006994: 2b00 cmp r3, #0
8006996: d020 beq.n 80069da <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
8006998: 68fb ldr r3, [r7, #12]
800699a: f003 0308 and.w r3, r3, #8
800699e: 2b00 cmp r3, #0
80069a0: d01b beq.n 80069da <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
80069a2: 687b ldr r3, [r7, #4]
80069a4: 681b ldr r3, [r3, #0]
80069a6: f06f 0208 mvn.w r2, #8
80069aa: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
80069ac: 687b ldr r3, [r7, #4]
80069ae: 2204 movs r2, #4
80069b0: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
80069b2: 687b ldr r3, [r7, #4]
80069b4: 681b ldr r3, [r3, #0]
80069b6: 69db ldr r3, [r3, #28]
80069b8: f003 0303 and.w r3, r3, #3
80069bc: 2b00 cmp r3, #0
80069be: d003 beq.n 80069c8 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80069c0: 6878 ldr r0, [r7, #4]
80069c2: f000 f9bb bl 8006d3c <HAL_TIM_IC_CaptureCallback>
80069c6: e005 b.n 80069d4 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80069c8: 6878 ldr r0, [r7, #4]
80069ca: f000 f9ad bl 8006d28 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80069ce: 6878 ldr r0, [r7, #4]
80069d0: f000 f9be bl 8006d50 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80069d4: 687b ldr r3, [r7, #4]
80069d6: 2200 movs r2, #0
80069d8: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
80069da: 68bb ldr r3, [r7, #8]
80069dc: f003 0310 and.w r3, r3, #16
80069e0: 2b00 cmp r3, #0
80069e2: d020 beq.n 8006a26 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
80069e4: 68fb ldr r3, [r7, #12]
80069e6: f003 0310 and.w r3, r3, #16
80069ea: 2b00 cmp r3, #0
80069ec: d01b beq.n 8006a26 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
80069ee: 687b ldr r3, [r7, #4]
80069f0: 681b ldr r3, [r3, #0]
80069f2: f06f 0210 mvn.w r2, #16
80069f6: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
80069f8: 687b ldr r3, [r7, #4]
80069fa: 2208 movs r2, #8
80069fc: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
80069fe: 687b ldr r3, [r7, #4]
8006a00: 681b ldr r3, [r3, #0]
8006a02: 69db ldr r3, [r3, #28]
8006a04: f403 7340 and.w r3, r3, #768 @ 0x300
8006a08: 2b00 cmp r3, #0
8006a0a: d003 beq.n 8006a14 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8006a0c: 6878 ldr r0, [r7, #4]
8006a0e: f000 f995 bl 8006d3c <HAL_TIM_IC_CaptureCallback>
8006a12: e005 b.n 8006a20 <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8006a14: 6878 ldr r0, [r7, #4]
8006a16: f000 f987 bl 8006d28 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8006a1a: 6878 ldr r0, [r7, #4]
8006a1c: f000 f998 bl 8006d50 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8006a20: 687b ldr r3, [r7, #4]
8006a22: 2200 movs r2, #0
8006a24: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8006a26: 68bb ldr r3, [r7, #8]
8006a28: f003 0301 and.w r3, r3, #1
8006a2c: 2b00 cmp r3, #0
8006a2e: d00c beq.n 8006a4a <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
8006a30: 68fb ldr r3, [r7, #12]
8006a32: f003 0301 and.w r3, r3, #1
8006a36: 2b00 cmp r3, #0
8006a38: d007 beq.n 8006a4a <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8006a3a: 687b ldr r3, [r7, #4]
8006a3c: 681b ldr r3, [r3, #0]
8006a3e: f06f 0201 mvn.w r2, #1
8006a42: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8006a44: 6878 ldr r0, [r7, #4]
8006a46: f000 f965 bl 8006d14 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8006a4a: 68bb ldr r3, [r7, #8]
8006a4c: f003 0380 and.w r3, r3, #128 @ 0x80
8006a50: 2b00 cmp r3, #0
8006a52: d104 bne.n 8006a5e <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
8006a54: 68bb ldr r3, [r7, #8]
8006a56: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8006a5a: 2b00 cmp r3, #0
8006a5c: d00c beq.n 8006a78 <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8006a5e: 68fb ldr r3, [r7, #12]
8006a60: f003 0380 and.w r3, r3, #128 @ 0x80
8006a64: 2b00 cmp r3, #0
8006a66: d007 beq.n 8006a78 <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8006a68: 687b ldr r3, [r7, #4]
8006a6a: 681b ldr r3, [r3, #0]
8006a6c: f46f 5202 mvn.w r2, #8320 @ 0x2080
8006a70: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8006a72: 6878 ldr r0, [r7, #4]
8006a74: f000 fd8e bl 8007594 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8006a78: 68bb ldr r3, [r7, #8]
8006a7a: f403 7380 and.w r3, r3, #256 @ 0x100
8006a7e: 2b00 cmp r3, #0
8006a80: d00c beq.n 8006a9c <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8006a82: 68fb ldr r3, [r7, #12]
8006a84: f003 0380 and.w r3, r3, #128 @ 0x80
8006a88: 2b00 cmp r3, #0
8006a8a: d007 beq.n 8006a9c <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8006a8c: 687b ldr r3, [r7, #4]
8006a8e: 681b ldr r3, [r3, #0]
8006a90: f46f 7280 mvn.w r2, #256 @ 0x100
8006a94: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8006a96: 6878 ldr r0, [r7, #4]
8006a98: f000 fd86 bl 80075a8 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
8006a9c: 68bb ldr r3, [r7, #8]
8006a9e: f003 0340 and.w r3, r3, #64 @ 0x40
8006aa2: 2b00 cmp r3, #0
8006aa4: d00c beq.n 8006ac0 <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8006aa6: 68fb ldr r3, [r7, #12]
8006aa8: f003 0340 and.w r3, r3, #64 @ 0x40
8006aac: 2b00 cmp r3, #0
8006aae: d007 beq.n 8006ac0 <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8006ab0: 687b ldr r3, [r7, #4]
8006ab2: 681b ldr r3, [r3, #0]
8006ab4: f06f 0240 mvn.w r2, #64 @ 0x40
8006ab8: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8006aba: 6878 ldr r0, [r7, #4]
8006abc: f000 f952 bl 8006d64 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
8006ac0: 68bb ldr r3, [r7, #8]
8006ac2: f003 0320 and.w r3, r3, #32
8006ac6: 2b00 cmp r3, #0
8006ac8: d00c beq.n 8006ae4 <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
8006aca: 68fb ldr r3, [r7, #12]
8006acc: f003 0320 and.w r3, r3, #32
8006ad0: 2b00 cmp r3, #0
8006ad2: d007 beq.n 8006ae4 <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8006ad4: 687b ldr r3, [r7, #4]
8006ad6: 681b ldr r3, [r3, #0]
8006ad8: f06f 0220 mvn.w r2, #32
8006adc: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8006ade: 6878 ldr r0, [r7, #4]
8006ae0: f000 fd4e bl 8007580 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8006ae4: bf00 nop
8006ae6: 3710 adds r7, #16
8006ae8: 46bd mov sp, r7
8006aea: bd80 pop {r7, pc}
08006aec <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8006aec: b580 push {r7, lr}
8006aee: b086 sub sp, #24
8006af0: af00 add r7, sp, #0
8006af2: 60f8 str r0, [r7, #12]
8006af4: 60b9 str r1, [r7, #8]
8006af6: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8006af8: 2300 movs r3, #0
8006afa: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8006afc: 68fb ldr r3, [r7, #12]
8006afe: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8006b02: 2b01 cmp r3, #1
8006b04: d101 bne.n 8006b0a <HAL_TIM_PWM_ConfigChannel+0x1e>
8006b06: 2302 movs r3, #2
8006b08: e0ff b.n 8006d0a <HAL_TIM_PWM_ConfigChannel+0x21e>
8006b0a: 68fb ldr r3, [r7, #12]
8006b0c: 2201 movs r2, #1
8006b0e: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8006b12: 687b ldr r3, [r7, #4]
8006b14: 2b14 cmp r3, #20
8006b16: f200 80f0 bhi.w 8006cfa <HAL_TIM_PWM_ConfigChannel+0x20e>
8006b1a: a201 add r2, pc, #4 @ (adr r2, 8006b20 <HAL_TIM_PWM_ConfigChannel+0x34>)
8006b1c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006b20: 08006b75 .word 0x08006b75
8006b24: 08006cfb .word 0x08006cfb
8006b28: 08006cfb .word 0x08006cfb
8006b2c: 08006cfb .word 0x08006cfb
8006b30: 08006bb5 .word 0x08006bb5
8006b34: 08006cfb .word 0x08006cfb
8006b38: 08006cfb .word 0x08006cfb
8006b3c: 08006cfb .word 0x08006cfb
8006b40: 08006bf7 .word 0x08006bf7
8006b44: 08006cfb .word 0x08006cfb
8006b48: 08006cfb .word 0x08006cfb
8006b4c: 08006cfb .word 0x08006cfb
8006b50: 08006c37 .word 0x08006c37
8006b54: 08006cfb .word 0x08006cfb
8006b58: 08006cfb .word 0x08006cfb
8006b5c: 08006cfb .word 0x08006cfb
8006b60: 08006c79 .word 0x08006c79
8006b64: 08006cfb .word 0x08006cfb
8006b68: 08006cfb .word 0x08006cfb
8006b6c: 08006cfb .word 0x08006cfb
8006b70: 08006cb9 .word 0x08006cb9
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8006b74: 68fb ldr r3, [r7, #12]
8006b76: 681b ldr r3, [r3, #0]
8006b78: 68b9 ldr r1, [r7, #8]
8006b7a: 4618 mov r0, r3
8006b7c: f000 f9a2 bl 8006ec4 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8006b80: 68fb ldr r3, [r7, #12]
8006b82: 681b ldr r3, [r3, #0]
8006b84: 699a ldr r2, [r3, #24]
8006b86: 68fb ldr r3, [r7, #12]
8006b88: 681b ldr r3, [r3, #0]
8006b8a: f042 0208 orr.w r2, r2, #8
8006b8e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8006b90: 68fb ldr r3, [r7, #12]
8006b92: 681b ldr r3, [r3, #0]
8006b94: 699a ldr r2, [r3, #24]
8006b96: 68fb ldr r3, [r7, #12]
8006b98: 681b ldr r3, [r3, #0]
8006b9a: f022 0204 bic.w r2, r2, #4
8006b9e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8006ba0: 68fb ldr r3, [r7, #12]
8006ba2: 681b ldr r3, [r3, #0]
8006ba4: 6999 ldr r1, [r3, #24]
8006ba6: 68bb ldr r3, [r7, #8]
8006ba8: 691a ldr r2, [r3, #16]
8006baa: 68fb ldr r3, [r7, #12]
8006bac: 681b ldr r3, [r3, #0]
8006bae: 430a orrs r2, r1
8006bb0: 619a str r2, [r3, #24]
break;
8006bb2: e0a5 b.n 8006d00 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8006bb4: 68fb ldr r3, [r7, #12]
8006bb6: 681b ldr r3, [r3, #0]
8006bb8: 68b9 ldr r1, [r7, #8]
8006bba: 4618 mov r0, r3
8006bbc: f000 fa12 bl 8006fe4 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8006bc0: 68fb ldr r3, [r7, #12]
8006bc2: 681b ldr r3, [r3, #0]
8006bc4: 699a ldr r2, [r3, #24]
8006bc6: 68fb ldr r3, [r7, #12]
8006bc8: 681b ldr r3, [r3, #0]
8006bca: f442 6200 orr.w r2, r2, #2048 @ 0x800
8006bce: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8006bd0: 68fb ldr r3, [r7, #12]
8006bd2: 681b ldr r3, [r3, #0]
8006bd4: 699a ldr r2, [r3, #24]
8006bd6: 68fb ldr r3, [r7, #12]
8006bd8: 681b ldr r3, [r3, #0]
8006bda: f422 6280 bic.w r2, r2, #1024 @ 0x400
8006bde: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8006be0: 68fb ldr r3, [r7, #12]
8006be2: 681b ldr r3, [r3, #0]
8006be4: 6999 ldr r1, [r3, #24]
8006be6: 68bb ldr r3, [r7, #8]
8006be8: 691b ldr r3, [r3, #16]
8006bea: 021a lsls r2, r3, #8
8006bec: 68fb ldr r3, [r7, #12]
8006bee: 681b ldr r3, [r3, #0]
8006bf0: 430a orrs r2, r1
8006bf2: 619a str r2, [r3, #24]
break;
8006bf4: e084 b.n 8006d00 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8006bf6: 68fb ldr r3, [r7, #12]
8006bf8: 681b ldr r3, [r3, #0]
8006bfa: 68b9 ldr r1, [r7, #8]
8006bfc: 4618 mov r0, r3
8006bfe: f000 fa7b bl 80070f8 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8006c02: 68fb ldr r3, [r7, #12]
8006c04: 681b ldr r3, [r3, #0]
8006c06: 69da ldr r2, [r3, #28]
8006c08: 68fb ldr r3, [r7, #12]
8006c0a: 681b ldr r3, [r3, #0]
8006c0c: f042 0208 orr.w r2, r2, #8
8006c10: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8006c12: 68fb ldr r3, [r7, #12]
8006c14: 681b ldr r3, [r3, #0]
8006c16: 69da ldr r2, [r3, #28]
8006c18: 68fb ldr r3, [r7, #12]
8006c1a: 681b ldr r3, [r3, #0]
8006c1c: f022 0204 bic.w r2, r2, #4
8006c20: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8006c22: 68fb ldr r3, [r7, #12]
8006c24: 681b ldr r3, [r3, #0]
8006c26: 69d9 ldr r1, [r3, #28]
8006c28: 68bb ldr r3, [r7, #8]
8006c2a: 691a ldr r2, [r3, #16]
8006c2c: 68fb ldr r3, [r7, #12]
8006c2e: 681b ldr r3, [r3, #0]
8006c30: 430a orrs r2, r1
8006c32: 61da str r2, [r3, #28]
break;
8006c34: e064 b.n 8006d00 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8006c36: 68fb ldr r3, [r7, #12]
8006c38: 681b ldr r3, [r3, #0]
8006c3a: 68b9 ldr r1, [r7, #8]
8006c3c: 4618 mov r0, r3
8006c3e: f000 fae3 bl 8007208 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8006c42: 68fb ldr r3, [r7, #12]
8006c44: 681b ldr r3, [r3, #0]
8006c46: 69da ldr r2, [r3, #28]
8006c48: 68fb ldr r3, [r7, #12]
8006c4a: 681b ldr r3, [r3, #0]
8006c4c: f442 6200 orr.w r2, r2, #2048 @ 0x800
8006c50: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8006c52: 68fb ldr r3, [r7, #12]
8006c54: 681b ldr r3, [r3, #0]
8006c56: 69da ldr r2, [r3, #28]
8006c58: 68fb ldr r3, [r7, #12]
8006c5a: 681b ldr r3, [r3, #0]
8006c5c: f422 6280 bic.w r2, r2, #1024 @ 0x400
8006c60: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8006c62: 68fb ldr r3, [r7, #12]
8006c64: 681b ldr r3, [r3, #0]
8006c66: 69d9 ldr r1, [r3, #28]
8006c68: 68bb ldr r3, [r7, #8]
8006c6a: 691b ldr r3, [r3, #16]
8006c6c: 021a lsls r2, r3, #8
8006c6e: 68fb ldr r3, [r7, #12]
8006c70: 681b ldr r3, [r3, #0]
8006c72: 430a orrs r2, r1
8006c74: 61da str r2, [r3, #28]
break;
8006c76: e043 b.n 8006d00 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8006c78: 68fb ldr r3, [r7, #12]
8006c7a: 681b ldr r3, [r3, #0]
8006c7c: 68b9 ldr r1, [r7, #8]
8006c7e: 4618 mov r0, r3
8006c80: f000 fb2c bl 80072dc <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8006c84: 68fb ldr r3, [r7, #12]
8006c86: 681b ldr r3, [r3, #0]
8006c88: 6d5a ldr r2, [r3, #84] @ 0x54
8006c8a: 68fb ldr r3, [r7, #12]
8006c8c: 681b ldr r3, [r3, #0]
8006c8e: f042 0208 orr.w r2, r2, #8
8006c92: 655a str r2, [r3, #84] @ 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8006c94: 68fb ldr r3, [r7, #12]
8006c96: 681b ldr r3, [r3, #0]
8006c98: 6d5a ldr r2, [r3, #84] @ 0x54
8006c9a: 68fb ldr r3, [r7, #12]
8006c9c: 681b ldr r3, [r3, #0]
8006c9e: f022 0204 bic.w r2, r2, #4
8006ca2: 655a str r2, [r3, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8006ca4: 68fb ldr r3, [r7, #12]
8006ca6: 681b ldr r3, [r3, #0]
8006ca8: 6d59 ldr r1, [r3, #84] @ 0x54
8006caa: 68bb ldr r3, [r7, #8]
8006cac: 691a ldr r2, [r3, #16]
8006cae: 68fb ldr r3, [r7, #12]
8006cb0: 681b ldr r3, [r3, #0]
8006cb2: 430a orrs r2, r1
8006cb4: 655a str r2, [r3, #84] @ 0x54
break;
8006cb6: e023 b.n 8006d00 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8006cb8: 68fb ldr r3, [r7, #12]
8006cba: 681b ldr r3, [r3, #0]
8006cbc: 68b9 ldr r1, [r7, #8]
8006cbe: 4618 mov r0, r3
8006cc0: f000 fb70 bl 80073a4 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8006cc4: 68fb ldr r3, [r7, #12]
8006cc6: 681b ldr r3, [r3, #0]
8006cc8: 6d5a ldr r2, [r3, #84] @ 0x54
8006cca: 68fb ldr r3, [r7, #12]
8006ccc: 681b ldr r3, [r3, #0]
8006cce: f442 6200 orr.w r2, r2, #2048 @ 0x800
8006cd2: 655a str r2, [r3, #84] @ 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8006cd4: 68fb ldr r3, [r7, #12]
8006cd6: 681b ldr r3, [r3, #0]
8006cd8: 6d5a ldr r2, [r3, #84] @ 0x54
8006cda: 68fb ldr r3, [r7, #12]
8006cdc: 681b ldr r3, [r3, #0]
8006cde: f422 6280 bic.w r2, r2, #1024 @ 0x400
8006ce2: 655a str r2, [r3, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8006ce4: 68fb ldr r3, [r7, #12]
8006ce6: 681b ldr r3, [r3, #0]
8006ce8: 6d59 ldr r1, [r3, #84] @ 0x54
8006cea: 68bb ldr r3, [r7, #8]
8006cec: 691b ldr r3, [r3, #16]
8006cee: 021a lsls r2, r3, #8
8006cf0: 68fb ldr r3, [r7, #12]
8006cf2: 681b ldr r3, [r3, #0]
8006cf4: 430a orrs r2, r1
8006cf6: 655a str r2, [r3, #84] @ 0x54
break;
8006cf8: e002 b.n 8006d00 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
status = HAL_ERROR;
8006cfa: 2301 movs r3, #1
8006cfc: 75fb strb r3, [r7, #23]
break;
8006cfe: bf00 nop
}
__HAL_UNLOCK(htim);
8006d00: 68fb ldr r3, [r7, #12]
8006d02: 2200 movs r2, #0
8006d04: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8006d08: 7dfb ldrb r3, [r7, #23]
}
8006d0a: 4618 mov r0, r3
8006d0c: 3718 adds r7, #24
8006d0e: 46bd mov sp, r7
8006d10: bd80 pop {r7, pc}
8006d12: bf00 nop
08006d14 <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8006d14: b480 push {r7}
8006d16: b083 sub sp, #12
8006d18: af00 add r7, sp, #0
8006d1a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
8006d1c: bf00 nop
8006d1e: 370c adds r7, #12
8006d20: 46bd mov sp, r7
8006d22: f85d 7b04 ldr.w r7, [sp], #4
8006d26: 4770 bx lr
08006d28 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8006d28: b480 push {r7}
8006d2a: b083 sub sp, #12
8006d2c: af00 add r7, sp, #0
8006d2e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8006d30: bf00 nop
8006d32: 370c adds r7, #12
8006d34: 46bd mov sp, r7
8006d36: f85d 7b04 ldr.w r7, [sp], #4
8006d3a: 4770 bx lr
08006d3c <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8006d3c: b480 push {r7}
8006d3e: b083 sub sp, #12
8006d40: af00 add r7, sp, #0
8006d42: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8006d44: bf00 nop
8006d46: 370c adds r7, #12
8006d48: 46bd mov sp, r7
8006d4a: f85d 7b04 ldr.w r7, [sp], #4
8006d4e: 4770 bx lr
08006d50 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8006d50: b480 push {r7}
8006d52: b083 sub sp, #12
8006d54: af00 add r7, sp, #0
8006d56: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8006d58: bf00 nop
8006d5a: 370c adds r7, #12
8006d5c: 46bd mov sp, r7
8006d5e: f85d 7b04 ldr.w r7, [sp], #4
8006d62: 4770 bx lr
08006d64 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8006d64: b480 push {r7}
8006d66: b083 sub sp, #12
8006d68: af00 add r7, sp, #0
8006d6a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8006d6c: bf00 nop
8006d6e: 370c adds r7, #12
8006d70: 46bd mov sp, r7
8006d72: f85d 7b04 ldr.w r7, [sp], #4
8006d76: 4770 bx lr
08006d78 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8006d78: b480 push {r7}
8006d7a: b085 sub sp, #20
8006d7c: af00 add r7, sp, #0
8006d7e: 6078 str r0, [r7, #4]
8006d80: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8006d82: 687b ldr r3, [r7, #4]
8006d84: 681b ldr r3, [r3, #0]
8006d86: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8006d88: 687b ldr r3, [r7, #4]
8006d8a: 4a46 ldr r2, [pc, #280] @ (8006ea4 <TIM_Base_SetConfig+0x12c>)
8006d8c: 4293 cmp r3, r2
8006d8e: d013 beq.n 8006db8 <TIM_Base_SetConfig+0x40>
8006d90: 687b ldr r3, [r7, #4]
8006d92: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8006d96: d00f beq.n 8006db8 <TIM_Base_SetConfig+0x40>
8006d98: 687b ldr r3, [r7, #4]
8006d9a: 4a43 ldr r2, [pc, #268] @ (8006ea8 <TIM_Base_SetConfig+0x130>)
8006d9c: 4293 cmp r3, r2
8006d9e: d00b beq.n 8006db8 <TIM_Base_SetConfig+0x40>
8006da0: 687b ldr r3, [r7, #4]
8006da2: 4a42 ldr r2, [pc, #264] @ (8006eac <TIM_Base_SetConfig+0x134>)
8006da4: 4293 cmp r3, r2
8006da6: d007 beq.n 8006db8 <TIM_Base_SetConfig+0x40>
8006da8: 687b ldr r3, [r7, #4]
8006daa: 4a41 ldr r2, [pc, #260] @ (8006eb0 <TIM_Base_SetConfig+0x138>)
8006dac: 4293 cmp r3, r2
8006dae: d003 beq.n 8006db8 <TIM_Base_SetConfig+0x40>
8006db0: 687b ldr r3, [r7, #4]
8006db2: 4a40 ldr r2, [pc, #256] @ (8006eb4 <TIM_Base_SetConfig+0x13c>)
8006db4: 4293 cmp r3, r2
8006db6: d108 bne.n 8006dca <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8006db8: 68fb ldr r3, [r7, #12]
8006dba: f023 0370 bic.w r3, r3, #112 @ 0x70
8006dbe: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8006dc0: 683b ldr r3, [r7, #0]
8006dc2: 685b ldr r3, [r3, #4]
8006dc4: 68fa ldr r2, [r7, #12]
8006dc6: 4313 orrs r3, r2
8006dc8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8006dca: 687b ldr r3, [r7, #4]
8006dcc: 4a35 ldr r2, [pc, #212] @ (8006ea4 <TIM_Base_SetConfig+0x12c>)
8006dce: 4293 cmp r3, r2
8006dd0: d01f beq.n 8006e12 <TIM_Base_SetConfig+0x9a>
8006dd2: 687b ldr r3, [r7, #4]
8006dd4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8006dd8: d01b beq.n 8006e12 <TIM_Base_SetConfig+0x9a>
8006dda: 687b ldr r3, [r7, #4]
8006ddc: 4a32 ldr r2, [pc, #200] @ (8006ea8 <TIM_Base_SetConfig+0x130>)
8006dde: 4293 cmp r3, r2
8006de0: d017 beq.n 8006e12 <TIM_Base_SetConfig+0x9a>
8006de2: 687b ldr r3, [r7, #4]
8006de4: 4a31 ldr r2, [pc, #196] @ (8006eac <TIM_Base_SetConfig+0x134>)
8006de6: 4293 cmp r3, r2
8006de8: d013 beq.n 8006e12 <TIM_Base_SetConfig+0x9a>
8006dea: 687b ldr r3, [r7, #4]
8006dec: 4a30 ldr r2, [pc, #192] @ (8006eb0 <TIM_Base_SetConfig+0x138>)
8006dee: 4293 cmp r3, r2
8006df0: d00f beq.n 8006e12 <TIM_Base_SetConfig+0x9a>
8006df2: 687b ldr r3, [r7, #4]
8006df4: 4a2f ldr r2, [pc, #188] @ (8006eb4 <TIM_Base_SetConfig+0x13c>)
8006df6: 4293 cmp r3, r2
8006df8: d00b beq.n 8006e12 <TIM_Base_SetConfig+0x9a>
8006dfa: 687b ldr r3, [r7, #4]
8006dfc: 4a2e ldr r2, [pc, #184] @ (8006eb8 <TIM_Base_SetConfig+0x140>)
8006dfe: 4293 cmp r3, r2
8006e00: d007 beq.n 8006e12 <TIM_Base_SetConfig+0x9a>
8006e02: 687b ldr r3, [r7, #4]
8006e04: 4a2d ldr r2, [pc, #180] @ (8006ebc <TIM_Base_SetConfig+0x144>)
8006e06: 4293 cmp r3, r2
8006e08: d003 beq.n 8006e12 <TIM_Base_SetConfig+0x9a>
8006e0a: 687b ldr r3, [r7, #4]
8006e0c: 4a2c ldr r2, [pc, #176] @ (8006ec0 <TIM_Base_SetConfig+0x148>)
8006e0e: 4293 cmp r3, r2
8006e10: d108 bne.n 8006e24 <TIM_Base_SetConfig+0xac>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8006e12: 68fb ldr r3, [r7, #12]
8006e14: f423 7340 bic.w r3, r3, #768 @ 0x300
8006e18: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8006e1a: 683b ldr r3, [r7, #0]
8006e1c: 68db ldr r3, [r3, #12]
8006e1e: 68fa ldr r2, [r7, #12]
8006e20: 4313 orrs r3, r2
8006e22: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8006e24: 68fb ldr r3, [r7, #12]
8006e26: f023 0280 bic.w r2, r3, #128 @ 0x80
8006e2a: 683b ldr r3, [r7, #0]
8006e2c: 695b ldr r3, [r3, #20]
8006e2e: 4313 orrs r3, r2
8006e30: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8006e32: 687b ldr r3, [r7, #4]
8006e34: 68fa ldr r2, [r7, #12]
8006e36: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8006e38: 683b ldr r3, [r7, #0]
8006e3a: 689a ldr r2, [r3, #8]
8006e3c: 687b ldr r3, [r7, #4]
8006e3e: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8006e40: 683b ldr r3, [r7, #0]
8006e42: 681a ldr r2, [r3, #0]
8006e44: 687b ldr r3, [r7, #4]
8006e46: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8006e48: 687b ldr r3, [r7, #4]
8006e4a: 4a16 ldr r2, [pc, #88] @ (8006ea4 <TIM_Base_SetConfig+0x12c>)
8006e4c: 4293 cmp r3, r2
8006e4e: d00f beq.n 8006e70 <TIM_Base_SetConfig+0xf8>
8006e50: 687b ldr r3, [r7, #4]
8006e52: 4a18 ldr r2, [pc, #96] @ (8006eb4 <TIM_Base_SetConfig+0x13c>)
8006e54: 4293 cmp r3, r2
8006e56: d00b beq.n 8006e70 <TIM_Base_SetConfig+0xf8>
8006e58: 687b ldr r3, [r7, #4]
8006e5a: 4a17 ldr r2, [pc, #92] @ (8006eb8 <TIM_Base_SetConfig+0x140>)
8006e5c: 4293 cmp r3, r2
8006e5e: d007 beq.n 8006e70 <TIM_Base_SetConfig+0xf8>
8006e60: 687b ldr r3, [r7, #4]
8006e62: 4a16 ldr r2, [pc, #88] @ (8006ebc <TIM_Base_SetConfig+0x144>)
8006e64: 4293 cmp r3, r2
8006e66: d003 beq.n 8006e70 <TIM_Base_SetConfig+0xf8>
8006e68: 687b ldr r3, [r7, #4]
8006e6a: 4a15 ldr r2, [pc, #84] @ (8006ec0 <TIM_Base_SetConfig+0x148>)
8006e6c: 4293 cmp r3, r2
8006e6e: d103 bne.n 8006e78 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8006e70: 683b ldr r3, [r7, #0]
8006e72: 691a ldr r2, [r3, #16]
8006e74: 687b ldr r3, [r7, #4]
8006e76: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8006e78: 687b ldr r3, [r7, #4]
8006e7a: 2201 movs r2, #1
8006e7c: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8006e7e: 687b ldr r3, [r7, #4]
8006e80: 691b ldr r3, [r3, #16]
8006e82: f003 0301 and.w r3, r3, #1
8006e86: 2b01 cmp r3, #1
8006e88: d105 bne.n 8006e96 <TIM_Base_SetConfig+0x11e>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8006e8a: 687b ldr r3, [r7, #4]
8006e8c: 691b ldr r3, [r3, #16]
8006e8e: f023 0201 bic.w r2, r3, #1
8006e92: 687b ldr r3, [r7, #4]
8006e94: 611a str r2, [r3, #16]
}
}
8006e96: bf00 nop
8006e98: 3714 adds r7, #20
8006e9a: 46bd mov sp, r7
8006e9c: f85d 7b04 ldr.w r7, [sp], #4
8006ea0: 4770 bx lr
8006ea2: bf00 nop
8006ea4: 40012c00 .word 0x40012c00
8006ea8: 40000400 .word 0x40000400
8006eac: 40000800 .word 0x40000800
8006eb0: 40000c00 .word 0x40000c00
8006eb4: 40013400 .word 0x40013400
8006eb8: 40014000 .word 0x40014000
8006ebc: 40014400 .word 0x40014400
8006ec0: 40014800 .word 0x40014800
08006ec4 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8006ec4: b480 push {r7}
8006ec6: b087 sub sp, #28
8006ec8: af00 add r7, sp, #0
8006eca: 6078 str r0, [r7, #4]
8006ecc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8006ece: 687b ldr r3, [r7, #4]
8006ed0: 6a1b ldr r3, [r3, #32]
8006ed2: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8006ed4: 687b ldr r3, [r7, #4]
8006ed6: 6a1b ldr r3, [r3, #32]
8006ed8: f023 0201 bic.w r2, r3, #1
8006edc: 687b ldr r3, [r7, #4]
8006ede: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8006ee0: 687b ldr r3, [r7, #4]
8006ee2: 685b ldr r3, [r3, #4]
8006ee4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8006ee6: 687b ldr r3, [r7, #4]
8006ee8: 699b ldr r3, [r3, #24]
8006eea: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8006eec: 68fb ldr r3, [r7, #12]
8006eee: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8006ef2: f023 0370 bic.w r3, r3, #112 @ 0x70
8006ef6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8006ef8: 68fb ldr r3, [r7, #12]
8006efa: f023 0303 bic.w r3, r3, #3
8006efe: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8006f00: 683b ldr r3, [r7, #0]
8006f02: 681b ldr r3, [r3, #0]
8006f04: 68fa ldr r2, [r7, #12]
8006f06: 4313 orrs r3, r2
8006f08: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8006f0a: 697b ldr r3, [r7, #20]
8006f0c: f023 0302 bic.w r3, r3, #2
8006f10: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8006f12: 683b ldr r3, [r7, #0]
8006f14: 689b ldr r3, [r3, #8]
8006f16: 697a ldr r2, [r7, #20]
8006f18: 4313 orrs r3, r2
8006f1a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8006f1c: 687b ldr r3, [r7, #4]
8006f1e: 4a2c ldr r2, [pc, #176] @ (8006fd0 <TIM_OC1_SetConfig+0x10c>)
8006f20: 4293 cmp r3, r2
8006f22: d00f beq.n 8006f44 <TIM_OC1_SetConfig+0x80>
8006f24: 687b ldr r3, [r7, #4]
8006f26: 4a2b ldr r2, [pc, #172] @ (8006fd4 <TIM_OC1_SetConfig+0x110>)
8006f28: 4293 cmp r3, r2
8006f2a: d00b beq.n 8006f44 <TIM_OC1_SetConfig+0x80>
8006f2c: 687b ldr r3, [r7, #4]
8006f2e: 4a2a ldr r2, [pc, #168] @ (8006fd8 <TIM_OC1_SetConfig+0x114>)
8006f30: 4293 cmp r3, r2
8006f32: d007 beq.n 8006f44 <TIM_OC1_SetConfig+0x80>
8006f34: 687b ldr r3, [r7, #4]
8006f36: 4a29 ldr r2, [pc, #164] @ (8006fdc <TIM_OC1_SetConfig+0x118>)
8006f38: 4293 cmp r3, r2
8006f3a: d003 beq.n 8006f44 <TIM_OC1_SetConfig+0x80>
8006f3c: 687b ldr r3, [r7, #4]
8006f3e: 4a28 ldr r2, [pc, #160] @ (8006fe0 <TIM_OC1_SetConfig+0x11c>)
8006f40: 4293 cmp r3, r2
8006f42: d10c bne.n 8006f5e <TIM_OC1_SetConfig+0x9a>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8006f44: 697b ldr r3, [r7, #20]
8006f46: f023 0308 bic.w r3, r3, #8
8006f4a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8006f4c: 683b ldr r3, [r7, #0]
8006f4e: 68db ldr r3, [r3, #12]
8006f50: 697a ldr r2, [r7, #20]
8006f52: 4313 orrs r3, r2
8006f54: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8006f56: 697b ldr r3, [r7, #20]
8006f58: f023 0304 bic.w r3, r3, #4
8006f5c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8006f5e: 687b ldr r3, [r7, #4]
8006f60: 4a1b ldr r2, [pc, #108] @ (8006fd0 <TIM_OC1_SetConfig+0x10c>)
8006f62: 4293 cmp r3, r2
8006f64: d00f beq.n 8006f86 <TIM_OC1_SetConfig+0xc2>
8006f66: 687b ldr r3, [r7, #4]
8006f68: 4a1a ldr r2, [pc, #104] @ (8006fd4 <TIM_OC1_SetConfig+0x110>)
8006f6a: 4293 cmp r3, r2
8006f6c: d00b beq.n 8006f86 <TIM_OC1_SetConfig+0xc2>
8006f6e: 687b ldr r3, [r7, #4]
8006f70: 4a19 ldr r2, [pc, #100] @ (8006fd8 <TIM_OC1_SetConfig+0x114>)
8006f72: 4293 cmp r3, r2
8006f74: d007 beq.n 8006f86 <TIM_OC1_SetConfig+0xc2>
8006f76: 687b ldr r3, [r7, #4]
8006f78: 4a18 ldr r2, [pc, #96] @ (8006fdc <TIM_OC1_SetConfig+0x118>)
8006f7a: 4293 cmp r3, r2
8006f7c: d003 beq.n 8006f86 <TIM_OC1_SetConfig+0xc2>
8006f7e: 687b ldr r3, [r7, #4]
8006f80: 4a17 ldr r2, [pc, #92] @ (8006fe0 <TIM_OC1_SetConfig+0x11c>)
8006f82: 4293 cmp r3, r2
8006f84: d111 bne.n 8006faa <TIM_OC1_SetConfig+0xe6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8006f86: 693b ldr r3, [r7, #16]
8006f88: f423 7380 bic.w r3, r3, #256 @ 0x100
8006f8c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8006f8e: 693b ldr r3, [r7, #16]
8006f90: f423 7300 bic.w r3, r3, #512 @ 0x200
8006f94: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8006f96: 683b ldr r3, [r7, #0]
8006f98: 695b ldr r3, [r3, #20]
8006f9a: 693a ldr r2, [r7, #16]
8006f9c: 4313 orrs r3, r2
8006f9e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8006fa0: 683b ldr r3, [r7, #0]
8006fa2: 699b ldr r3, [r3, #24]
8006fa4: 693a ldr r2, [r7, #16]
8006fa6: 4313 orrs r3, r2
8006fa8: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8006faa: 687b ldr r3, [r7, #4]
8006fac: 693a ldr r2, [r7, #16]
8006fae: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8006fb0: 687b ldr r3, [r7, #4]
8006fb2: 68fa ldr r2, [r7, #12]
8006fb4: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8006fb6: 683b ldr r3, [r7, #0]
8006fb8: 685a ldr r2, [r3, #4]
8006fba: 687b ldr r3, [r7, #4]
8006fbc: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8006fbe: 687b ldr r3, [r7, #4]
8006fc0: 697a ldr r2, [r7, #20]
8006fc2: 621a str r2, [r3, #32]
}
8006fc4: bf00 nop
8006fc6: 371c adds r7, #28
8006fc8: 46bd mov sp, r7
8006fca: f85d 7b04 ldr.w r7, [sp], #4
8006fce: 4770 bx lr
8006fd0: 40012c00 .word 0x40012c00
8006fd4: 40013400 .word 0x40013400
8006fd8: 40014000 .word 0x40014000
8006fdc: 40014400 .word 0x40014400
8006fe0: 40014800 .word 0x40014800
08006fe4 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8006fe4: b480 push {r7}
8006fe6: b087 sub sp, #28
8006fe8: af00 add r7, sp, #0
8006fea: 6078 str r0, [r7, #4]
8006fec: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8006fee: 687b ldr r3, [r7, #4]
8006ff0: 6a1b ldr r3, [r3, #32]
8006ff2: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8006ff4: 687b ldr r3, [r7, #4]
8006ff6: 6a1b ldr r3, [r3, #32]
8006ff8: f023 0210 bic.w r2, r3, #16
8006ffc: 687b ldr r3, [r7, #4]
8006ffe: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007000: 687b ldr r3, [r7, #4]
8007002: 685b ldr r3, [r3, #4]
8007004: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8007006: 687b ldr r3, [r7, #4]
8007008: 699b ldr r3, [r3, #24]
800700a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
800700c: 68fb ldr r3, [r7, #12]
800700e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8007012: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007016: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8007018: 68fb ldr r3, [r7, #12]
800701a: f423 7340 bic.w r3, r3, #768 @ 0x300
800701e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8007020: 683b ldr r3, [r7, #0]
8007022: 681b ldr r3, [r3, #0]
8007024: 021b lsls r3, r3, #8
8007026: 68fa ldr r2, [r7, #12]
8007028: 4313 orrs r3, r2
800702a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
800702c: 697b ldr r3, [r7, #20]
800702e: f023 0320 bic.w r3, r3, #32
8007032: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8007034: 683b ldr r3, [r7, #0]
8007036: 689b ldr r3, [r3, #8]
8007038: 011b lsls r3, r3, #4
800703a: 697a ldr r2, [r7, #20]
800703c: 4313 orrs r3, r2
800703e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8007040: 687b ldr r3, [r7, #4]
8007042: 4a28 ldr r2, [pc, #160] @ (80070e4 <TIM_OC2_SetConfig+0x100>)
8007044: 4293 cmp r3, r2
8007046: d003 beq.n 8007050 <TIM_OC2_SetConfig+0x6c>
8007048: 687b ldr r3, [r7, #4]
800704a: 4a27 ldr r2, [pc, #156] @ (80070e8 <TIM_OC2_SetConfig+0x104>)
800704c: 4293 cmp r3, r2
800704e: d10d bne.n 800706c <TIM_OC2_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8007050: 697b ldr r3, [r7, #20]
8007052: f023 0380 bic.w r3, r3, #128 @ 0x80
8007056: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8007058: 683b ldr r3, [r7, #0]
800705a: 68db ldr r3, [r3, #12]
800705c: 011b lsls r3, r3, #4
800705e: 697a ldr r2, [r7, #20]
8007060: 4313 orrs r3, r2
8007062: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8007064: 697b ldr r3, [r7, #20]
8007066: f023 0340 bic.w r3, r3, #64 @ 0x40
800706a: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800706c: 687b ldr r3, [r7, #4]
800706e: 4a1d ldr r2, [pc, #116] @ (80070e4 <TIM_OC2_SetConfig+0x100>)
8007070: 4293 cmp r3, r2
8007072: d00f beq.n 8007094 <TIM_OC2_SetConfig+0xb0>
8007074: 687b ldr r3, [r7, #4]
8007076: 4a1c ldr r2, [pc, #112] @ (80070e8 <TIM_OC2_SetConfig+0x104>)
8007078: 4293 cmp r3, r2
800707a: d00b beq.n 8007094 <TIM_OC2_SetConfig+0xb0>
800707c: 687b ldr r3, [r7, #4]
800707e: 4a1b ldr r2, [pc, #108] @ (80070ec <TIM_OC2_SetConfig+0x108>)
8007080: 4293 cmp r3, r2
8007082: d007 beq.n 8007094 <TIM_OC2_SetConfig+0xb0>
8007084: 687b ldr r3, [r7, #4]
8007086: 4a1a ldr r2, [pc, #104] @ (80070f0 <TIM_OC2_SetConfig+0x10c>)
8007088: 4293 cmp r3, r2
800708a: d003 beq.n 8007094 <TIM_OC2_SetConfig+0xb0>
800708c: 687b ldr r3, [r7, #4]
800708e: 4a19 ldr r2, [pc, #100] @ (80070f4 <TIM_OC2_SetConfig+0x110>)
8007090: 4293 cmp r3, r2
8007092: d113 bne.n 80070bc <TIM_OC2_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8007094: 693b ldr r3, [r7, #16]
8007096: f423 6380 bic.w r3, r3, #1024 @ 0x400
800709a: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
800709c: 693b ldr r3, [r7, #16]
800709e: f423 6300 bic.w r3, r3, #2048 @ 0x800
80070a2: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
80070a4: 683b ldr r3, [r7, #0]
80070a6: 695b ldr r3, [r3, #20]
80070a8: 009b lsls r3, r3, #2
80070aa: 693a ldr r2, [r7, #16]
80070ac: 4313 orrs r3, r2
80070ae: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
80070b0: 683b ldr r3, [r7, #0]
80070b2: 699b ldr r3, [r3, #24]
80070b4: 009b lsls r3, r3, #2
80070b6: 693a ldr r2, [r7, #16]
80070b8: 4313 orrs r3, r2
80070ba: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80070bc: 687b ldr r3, [r7, #4]
80070be: 693a ldr r2, [r7, #16]
80070c0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80070c2: 687b ldr r3, [r7, #4]
80070c4: 68fa ldr r2, [r7, #12]
80070c6: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
80070c8: 683b ldr r3, [r7, #0]
80070ca: 685a ldr r2, [r3, #4]
80070cc: 687b ldr r3, [r7, #4]
80070ce: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80070d0: 687b ldr r3, [r7, #4]
80070d2: 697a ldr r2, [r7, #20]
80070d4: 621a str r2, [r3, #32]
}
80070d6: bf00 nop
80070d8: 371c adds r7, #28
80070da: 46bd mov sp, r7
80070dc: f85d 7b04 ldr.w r7, [sp], #4
80070e0: 4770 bx lr
80070e2: bf00 nop
80070e4: 40012c00 .word 0x40012c00
80070e8: 40013400 .word 0x40013400
80070ec: 40014000 .word 0x40014000
80070f0: 40014400 .word 0x40014400
80070f4: 40014800 .word 0x40014800
080070f8 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80070f8: b480 push {r7}
80070fa: b087 sub sp, #28
80070fc: af00 add r7, sp, #0
80070fe: 6078 str r0, [r7, #4]
8007100: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8007102: 687b ldr r3, [r7, #4]
8007104: 6a1b ldr r3, [r3, #32]
8007106: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8007108: 687b ldr r3, [r7, #4]
800710a: 6a1b ldr r3, [r3, #32]
800710c: f423 7280 bic.w r2, r3, #256 @ 0x100
8007110: 687b ldr r3, [r7, #4]
8007112: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007114: 687b ldr r3, [r7, #4]
8007116: 685b ldr r3, [r3, #4]
8007118: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800711a: 687b ldr r3, [r7, #4]
800711c: 69db ldr r3, [r3, #28]
800711e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8007120: 68fb ldr r3, [r7, #12]
8007122: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8007126: f023 0370 bic.w r3, r3, #112 @ 0x70
800712a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
800712c: 68fb ldr r3, [r7, #12]
800712e: f023 0303 bic.w r3, r3, #3
8007132: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8007134: 683b ldr r3, [r7, #0]
8007136: 681b ldr r3, [r3, #0]
8007138: 68fa ldr r2, [r7, #12]
800713a: 4313 orrs r3, r2
800713c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800713e: 697b ldr r3, [r7, #20]
8007140: f423 7300 bic.w r3, r3, #512 @ 0x200
8007144: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8007146: 683b ldr r3, [r7, #0]
8007148: 689b ldr r3, [r3, #8]
800714a: 021b lsls r3, r3, #8
800714c: 697a ldr r2, [r7, #20]
800714e: 4313 orrs r3, r2
8007150: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8007152: 687b ldr r3, [r7, #4]
8007154: 4a27 ldr r2, [pc, #156] @ (80071f4 <TIM_OC3_SetConfig+0xfc>)
8007156: 4293 cmp r3, r2
8007158: d003 beq.n 8007162 <TIM_OC3_SetConfig+0x6a>
800715a: 687b ldr r3, [r7, #4]
800715c: 4a26 ldr r2, [pc, #152] @ (80071f8 <TIM_OC3_SetConfig+0x100>)
800715e: 4293 cmp r3, r2
8007160: d10d bne.n 800717e <TIM_OC3_SetConfig+0x86>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8007162: 697b ldr r3, [r7, #20]
8007164: f423 6300 bic.w r3, r3, #2048 @ 0x800
8007168: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
800716a: 683b ldr r3, [r7, #0]
800716c: 68db ldr r3, [r3, #12]
800716e: 021b lsls r3, r3, #8
8007170: 697a ldr r2, [r7, #20]
8007172: 4313 orrs r3, r2
8007174: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8007176: 697b ldr r3, [r7, #20]
8007178: f423 6380 bic.w r3, r3, #1024 @ 0x400
800717c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800717e: 687b ldr r3, [r7, #4]
8007180: 4a1c ldr r2, [pc, #112] @ (80071f4 <TIM_OC3_SetConfig+0xfc>)
8007182: 4293 cmp r3, r2
8007184: d00f beq.n 80071a6 <TIM_OC3_SetConfig+0xae>
8007186: 687b ldr r3, [r7, #4]
8007188: 4a1b ldr r2, [pc, #108] @ (80071f8 <TIM_OC3_SetConfig+0x100>)
800718a: 4293 cmp r3, r2
800718c: d00b beq.n 80071a6 <TIM_OC3_SetConfig+0xae>
800718e: 687b ldr r3, [r7, #4]
8007190: 4a1a ldr r2, [pc, #104] @ (80071fc <TIM_OC3_SetConfig+0x104>)
8007192: 4293 cmp r3, r2
8007194: d007 beq.n 80071a6 <TIM_OC3_SetConfig+0xae>
8007196: 687b ldr r3, [r7, #4]
8007198: 4a19 ldr r2, [pc, #100] @ (8007200 <TIM_OC3_SetConfig+0x108>)
800719a: 4293 cmp r3, r2
800719c: d003 beq.n 80071a6 <TIM_OC3_SetConfig+0xae>
800719e: 687b ldr r3, [r7, #4]
80071a0: 4a18 ldr r2, [pc, #96] @ (8007204 <TIM_OC3_SetConfig+0x10c>)
80071a2: 4293 cmp r3, r2
80071a4: d113 bne.n 80071ce <TIM_OC3_SetConfig+0xd6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
80071a6: 693b ldr r3, [r7, #16]
80071a8: f423 5380 bic.w r3, r3, #4096 @ 0x1000
80071ac: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
80071ae: 693b ldr r3, [r7, #16]
80071b0: f423 5300 bic.w r3, r3, #8192 @ 0x2000
80071b4: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
80071b6: 683b ldr r3, [r7, #0]
80071b8: 695b ldr r3, [r3, #20]
80071ba: 011b lsls r3, r3, #4
80071bc: 693a ldr r2, [r7, #16]
80071be: 4313 orrs r3, r2
80071c0: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
80071c2: 683b ldr r3, [r7, #0]
80071c4: 699b ldr r3, [r3, #24]
80071c6: 011b lsls r3, r3, #4
80071c8: 693a ldr r2, [r7, #16]
80071ca: 4313 orrs r3, r2
80071cc: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80071ce: 687b ldr r3, [r7, #4]
80071d0: 693a ldr r2, [r7, #16]
80071d2: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80071d4: 687b ldr r3, [r7, #4]
80071d6: 68fa ldr r2, [r7, #12]
80071d8: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
80071da: 683b ldr r3, [r7, #0]
80071dc: 685a ldr r2, [r3, #4]
80071de: 687b ldr r3, [r7, #4]
80071e0: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80071e2: 687b ldr r3, [r7, #4]
80071e4: 697a ldr r2, [r7, #20]
80071e6: 621a str r2, [r3, #32]
}
80071e8: bf00 nop
80071ea: 371c adds r7, #28
80071ec: 46bd mov sp, r7
80071ee: f85d 7b04 ldr.w r7, [sp], #4
80071f2: 4770 bx lr
80071f4: 40012c00 .word 0x40012c00
80071f8: 40013400 .word 0x40013400
80071fc: 40014000 .word 0x40014000
8007200: 40014400 .word 0x40014400
8007204: 40014800 .word 0x40014800
08007208 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8007208: b480 push {r7}
800720a: b087 sub sp, #28
800720c: af00 add r7, sp, #0
800720e: 6078 str r0, [r7, #4]
8007210: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8007212: 687b ldr r3, [r7, #4]
8007214: 6a1b ldr r3, [r3, #32]
8007216: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8007218: 687b ldr r3, [r7, #4]
800721a: 6a1b ldr r3, [r3, #32]
800721c: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8007220: 687b ldr r3, [r7, #4]
8007222: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007224: 687b ldr r3, [r7, #4]
8007226: 685b ldr r3, [r3, #4]
8007228: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800722a: 687b ldr r3, [r7, #4]
800722c: 69db ldr r3, [r3, #28]
800722e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8007230: 68fb ldr r3, [r7, #12]
8007232: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8007236: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800723a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
800723c: 68fb ldr r3, [r7, #12]
800723e: f423 7340 bic.w r3, r3, #768 @ 0x300
8007242: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8007244: 683b ldr r3, [r7, #0]
8007246: 681b ldr r3, [r3, #0]
8007248: 021b lsls r3, r3, #8
800724a: 68fa ldr r2, [r7, #12]
800724c: 4313 orrs r3, r2
800724e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8007250: 693b ldr r3, [r7, #16]
8007252: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8007256: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8007258: 683b ldr r3, [r7, #0]
800725a: 689b ldr r3, [r3, #8]
800725c: 031b lsls r3, r3, #12
800725e: 693a ldr r2, [r7, #16]
8007260: 4313 orrs r3, r2
8007262: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8007264: 687b ldr r3, [r7, #4]
8007266: 4a18 ldr r2, [pc, #96] @ (80072c8 <TIM_OC4_SetConfig+0xc0>)
8007268: 4293 cmp r3, r2
800726a: d00f beq.n 800728c <TIM_OC4_SetConfig+0x84>
800726c: 687b ldr r3, [r7, #4]
800726e: 4a17 ldr r2, [pc, #92] @ (80072cc <TIM_OC4_SetConfig+0xc4>)
8007270: 4293 cmp r3, r2
8007272: d00b beq.n 800728c <TIM_OC4_SetConfig+0x84>
8007274: 687b ldr r3, [r7, #4]
8007276: 4a16 ldr r2, [pc, #88] @ (80072d0 <TIM_OC4_SetConfig+0xc8>)
8007278: 4293 cmp r3, r2
800727a: d007 beq.n 800728c <TIM_OC4_SetConfig+0x84>
800727c: 687b ldr r3, [r7, #4]
800727e: 4a15 ldr r2, [pc, #84] @ (80072d4 <TIM_OC4_SetConfig+0xcc>)
8007280: 4293 cmp r3, r2
8007282: d003 beq.n 800728c <TIM_OC4_SetConfig+0x84>
8007284: 687b ldr r3, [r7, #4]
8007286: 4a14 ldr r2, [pc, #80] @ (80072d8 <TIM_OC4_SetConfig+0xd0>)
8007288: 4293 cmp r3, r2
800728a: d109 bne.n 80072a0 <TIM_OC4_SetConfig+0x98>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
800728c: 697b ldr r3, [r7, #20]
800728e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8007292: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8007294: 683b ldr r3, [r7, #0]
8007296: 695b ldr r3, [r3, #20]
8007298: 019b lsls r3, r3, #6
800729a: 697a ldr r2, [r7, #20]
800729c: 4313 orrs r3, r2
800729e: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80072a0: 687b ldr r3, [r7, #4]
80072a2: 697a ldr r2, [r7, #20]
80072a4: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80072a6: 687b ldr r3, [r7, #4]
80072a8: 68fa ldr r2, [r7, #12]
80072aa: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80072ac: 683b ldr r3, [r7, #0]
80072ae: 685a ldr r2, [r3, #4]
80072b0: 687b ldr r3, [r7, #4]
80072b2: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80072b4: 687b ldr r3, [r7, #4]
80072b6: 693a ldr r2, [r7, #16]
80072b8: 621a str r2, [r3, #32]
}
80072ba: bf00 nop
80072bc: 371c adds r7, #28
80072be: 46bd mov sp, r7
80072c0: f85d 7b04 ldr.w r7, [sp], #4
80072c4: 4770 bx lr
80072c6: bf00 nop
80072c8: 40012c00 .word 0x40012c00
80072cc: 40013400 .word 0x40013400
80072d0: 40014000 .word 0x40014000
80072d4: 40014400 .word 0x40014400
80072d8: 40014800 .word 0x40014800
080072dc <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80072dc: b480 push {r7}
80072de: b087 sub sp, #28
80072e0: af00 add r7, sp, #0
80072e2: 6078 str r0, [r7, #4]
80072e4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80072e6: 687b ldr r3, [r7, #4]
80072e8: 6a1b ldr r3, [r3, #32]
80072ea: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
80072ec: 687b ldr r3, [r7, #4]
80072ee: 6a1b ldr r3, [r3, #32]
80072f0: f423 3280 bic.w r2, r3, #65536 @ 0x10000
80072f4: 687b ldr r3, [r7, #4]
80072f6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80072f8: 687b ldr r3, [r7, #4]
80072fa: 685b ldr r3, [r3, #4]
80072fc: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
80072fe: 687b ldr r3, [r7, #4]
8007300: 6d5b ldr r3, [r3, #84] @ 0x54
8007302: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8007304: 68fb ldr r3, [r7, #12]
8007306: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800730a: f023 0370 bic.w r3, r3, #112 @ 0x70
800730e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8007310: 683b ldr r3, [r7, #0]
8007312: 681b ldr r3, [r3, #0]
8007314: 68fa ldr r2, [r7, #12]
8007316: 4313 orrs r3, r2
8007318: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
800731a: 693b ldr r3, [r7, #16]
800731c: f423 3300 bic.w r3, r3, #131072 @ 0x20000
8007320: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
8007322: 683b ldr r3, [r7, #0]
8007324: 689b ldr r3, [r3, #8]
8007326: 041b lsls r3, r3, #16
8007328: 693a ldr r2, [r7, #16]
800732a: 4313 orrs r3, r2
800732c: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800732e: 687b ldr r3, [r7, #4]
8007330: 4a17 ldr r2, [pc, #92] @ (8007390 <TIM_OC5_SetConfig+0xb4>)
8007332: 4293 cmp r3, r2
8007334: d00f beq.n 8007356 <TIM_OC5_SetConfig+0x7a>
8007336: 687b ldr r3, [r7, #4]
8007338: 4a16 ldr r2, [pc, #88] @ (8007394 <TIM_OC5_SetConfig+0xb8>)
800733a: 4293 cmp r3, r2
800733c: d00b beq.n 8007356 <TIM_OC5_SetConfig+0x7a>
800733e: 687b ldr r3, [r7, #4]
8007340: 4a15 ldr r2, [pc, #84] @ (8007398 <TIM_OC5_SetConfig+0xbc>)
8007342: 4293 cmp r3, r2
8007344: d007 beq.n 8007356 <TIM_OC5_SetConfig+0x7a>
8007346: 687b ldr r3, [r7, #4]
8007348: 4a14 ldr r2, [pc, #80] @ (800739c <TIM_OC5_SetConfig+0xc0>)
800734a: 4293 cmp r3, r2
800734c: d003 beq.n 8007356 <TIM_OC5_SetConfig+0x7a>
800734e: 687b ldr r3, [r7, #4]
8007350: 4a13 ldr r2, [pc, #76] @ (80073a0 <TIM_OC5_SetConfig+0xc4>)
8007352: 4293 cmp r3, r2
8007354: d109 bne.n 800736a <TIM_OC5_SetConfig+0x8e>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
8007356: 697b ldr r3, [r7, #20]
8007358: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800735c: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
800735e: 683b ldr r3, [r7, #0]
8007360: 695b ldr r3, [r3, #20]
8007362: 021b lsls r3, r3, #8
8007364: 697a ldr r2, [r7, #20]
8007366: 4313 orrs r3, r2
8007368: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800736a: 687b ldr r3, [r7, #4]
800736c: 697a ldr r2, [r7, #20]
800736e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8007370: 687b ldr r3, [r7, #4]
8007372: 68fa ldr r2, [r7, #12]
8007374: 655a str r2, [r3, #84] @ 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
8007376: 683b ldr r3, [r7, #0]
8007378: 685a ldr r2, [r3, #4]
800737a: 687b ldr r3, [r7, #4]
800737c: 659a str r2, [r3, #88] @ 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800737e: 687b ldr r3, [r7, #4]
8007380: 693a ldr r2, [r7, #16]
8007382: 621a str r2, [r3, #32]
}
8007384: bf00 nop
8007386: 371c adds r7, #28
8007388: 46bd mov sp, r7
800738a: f85d 7b04 ldr.w r7, [sp], #4
800738e: 4770 bx lr
8007390: 40012c00 .word 0x40012c00
8007394: 40013400 .word 0x40013400
8007398: 40014000 .word 0x40014000
800739c: 40014400 .word 0x40014400
80073a0: 40014800 .word 0x40014800
080073a4 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80073a4: b480 push {r7}
80073a6: b087 sub sp, #28
80073a8: af00 add r7, sp, #0
80073aa: 6078 str r0, [r7, #4]
80073ac: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80073ae: 687b ldr r3, [r7, #4]
80073b0: 6a1b ldr r3, [r3, #32]
80073b2: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
80073b4: 687b ldr r3, [r7, #4]
80073b6: 6a1b ldr r3, [r3, #32]
80073b8: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
80073bc: 687b ldr r3, [r7, #4]
80073be: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80073c0: 687b ldr r3, [r7, #4]
80073c2: 685b ldr r3, [r3, #4]
80073c4: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
80073c6: 687b ldr r3, [r7, #4]
80073c8: 6d5b ldr r3, [r3, #84] @ 0x54
80073ca: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
80073cc: 68fb ldr r3, [r7, #12]
80073ce: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80073d2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80073d6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80073d8: 683b ldr r3, [r7, #0]
80073da: 681b ldr r3, [r3, #0]
80073dc: 021b lsls r3, r3, #8
80073de: 68fa ldr r2, [r7, #12]
80073e0: 4313 orrs r3, r2
80073e2: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
80073e4: 693b ldr r3, [r7, #16]
80073e6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
80073ea: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
80073ec: 683b ldr r3, [r7, #0]
80073ee: 689b ldr r3, [r3, #8]
80073f0: 051b lsls r3, r3, #20
80073f2: 693a ldr r2, [r7, #16]
80073f4: 4313 orrs r3, r2
80073f6: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80073f8: 687b ldr r3, [r7, #4]
80073fa: 4a18 ldr r2, [pc, #96] @ (800745c <TIM_OC6_SetConfig+0xb8>)
80073fc: 4293 cmp r3, r2
80073fe: d00f beq.n 8007420 <TIM_OC6_SetConfig+0x7c>
8007400: 687b ldr r3, [r7, #4]
8007402: 4a17 ldr r2, [pc, #92] @ (8007460 <TIM_OC6_SetConfig+0xbc>)
8007404: 4293 cmp r3, r2
8007406: d00b beq.n 8007420 <TIM_OC6_SetConfig+0x7c>
8007408: 687b ldr r3, [r7, #4]
800740a: 4a16 ldr r2, [pc, #88] @ (8007464 <TIM_OC6_SetConfig+0xc0>)
800740c: 4293 cmp r3, r2
800740e: d007 beq.n 8007420 <TIM_OC6_SetConfig+0x7c>
8007410: 687b ldr r3, [r7, #4]
8007412: 4a15 ldr r2, [pc, #84] @ (8007468 <TIM_OC6_SetConfig+0xc4>)
8007414: 4293 cmp r3, r2
8007416: d003 beq.n 8007420 <TIM_OC6_SetConfig+0x7c>
8007418: 687b ldr r3, [r7, #4]
800741a: 4a14 ldr r2, [pc, #80] @ (800746c <TIM_OC6_SetConfig+0xc8>)
800741c: 4293 cmp r3, r2
800741e: d109 bne.n 8007434 <TIM_OC6_SetConfig+0x90>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8007420: 697b ldr r3, [r7, #20]
8007422: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8007426: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8007428: 683b ldr r3, [r7, #0]
800742a: 695b ldr r3, [r3, #20]
800742c: 029b lsls r3, r3, #10
800742e: 697a ldr r2, [r7, #20]
8007430: 4313 orrs r3, r2
8007432: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8007434: 687b ldr r3, [r7, #4]
8007436: 697a ldr r2, [r7, #20]
8007438: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800743a: 687b ldr r3, [r7, #4]
800743c: 68fa ldr r2, [r7, #12]
800743e: 655a str r2, [r3, #84] @ 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8007440: 683b ldr r3, [r7, #0]
8007442: 685a ldr r2, [r3, #4]
8007444: 687b ldr r3, [r7, #4]
8007446: 65da str r2, [r3, #92] @ 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8007448: 687b ldr r3, [r7, #4]
800744a: 693a ldr r2, [r7, #16]
800744c: 621a str r2, [r3, #32]
}
800744e: bf00 nop
8007450: 371c adds r7, #28
8007452: 46bd mov sp, r7
8007454: f85d 7b04 ldr.w r7, [sp], #4
8007458: 4770 bx lr
800745a: bf00 nop
800745c: 40012c00 .word 0x40012c00
8007460: 40013400 .word 0x40013400
8007464: 40014000 .word 0x40014000
8007468: 40014400 .word 0x40014400
800746c: 40014800 .word 0x40014800
08007470 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8007470: b480 push {r7}
8007472: b085 sub sp, #20
8007474: af00 add r7, sp, #0
8007476: 6078 str r0, [r7, #4]
8007478: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
800747a: 687b ldr r3, [r7, #4]
800747c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8007480: 2b01 cmp r3, #1
8007482: d101 bne.n 8007488 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8007484: 2302 movs r3, #2
8007486: e068 b.n 800755a <HAL_TIMEx_MasterConfigSynchronization+0xea>
8007488: 687b ldr r3, [r7, #4]
800748a: 2201 movs r2, #1
800748c: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8007490: 687b ldr r3, [r7, #4]
8007492: 2202 movs r2, #2
8007494: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8007498: 687b ldr r3, [r7, #4]
800749a: 681b ldr r3, [r3, #0]
800749c: 685b ldr r3, [r3, #4]
800749e: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80074a0: 687b ldr r3, [r7, #4]
80074a2: 681b ldr r3, [r3, #0]
80074a4: 689b ldr r3, [r3, #8]
80074a6: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80074a8: 687b ldr r3, [r7, #4]
80074aa: 681b ldr r3, [r3, #0]
80074ac: 4a2e ldr r2, [pc, #184] @ (8007568 <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
80074ae: 4293 cmp r3, r2
80074b0: d004 beq.n 80074bc <HAL_TIMEx_MasterConfigSynchronization+0x4c>
80074b2: 687b ldr r3, [r7, #4]
80074b4: 681b ldr r3, [r3, #0]
80074b6: 4a2d ldr r2, [pc, #180] @ (800756c <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
80074b8: 4293 cmp r3, r2
80074ba: d108 bne.n 80074ce <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
80074bc: 68fb ldr r3, [r7, #12]
80074be: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
80074c2: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
80074c4: 683b ldr r3, [r7, #0]
80074c6: 685b ldr r3, [r3, #4]
80074c8: 68fa ldr r2, [r7, #12]
80074ca: 4313 orrs r3, r2
80074cc: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80074ce: 68fb ldr r3, [r7, #12]
80074d0: f023 0370 bic.w r3, r3, #112 @ 0x70
80074d4: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80074d6: 683b ldr r3, [r7, #0]
80074d8: 681b ldr r3, [r3, #0]
80074da: 68fa ldr r2, [r7, #12]
80074dc: 4313 orrs r3, r2
80074de: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80074e0: 687b ldr r3, [r7, #4]
80074e2: 681b ldr r3, [r3, #0]
80074e4: 68fa ldr r2, [r7, #12]
80074e6: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80074e8: 687b ldr r3, [r7, #4]
80074ea: 681b ldr r3, [r3, #0]
80074ec: 4a1e ldr r2, [pc, #120] @ (8007568 <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
80074ee: 4293 cmp r3, r2
80074f0: d01d beq.n 800752e <HAL_TIMEx_MasterConfigSynchronization+0xbe>
80074f2: 687b ldr r3, [r7, #4]
80074f4: 681b ldr r3, [r3, #0]
80074f6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80074fa: d018 beq.n 800752e <HAL_TIMEx_MasterConfigSynchronization+0xbe>
80074fc: 687b ldr r3, [r7, #4]
80074fe: 681b ldr r3, [r3, #0]
8007500: 4a1b ldr r2, [pc, #108] @ (8007570 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
8007502: 4293 cmp r3, r2
8007504: d013 beq.n 800752e <HAL_TIMEx_MasterConfigSynchronization+0xbe>
8007506: 687b ldr r3, [r7, #4]
8007508: 681b ldr r3, [r3, #0]
800750a: 4a1a ldr r2, [pc, #104] @ (8007574 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
800750c: 4293 cmp r3, r2
800750e: d00e beq.n 800752e <HAL_TIMEx_MasterConfigSynchronization+0xbe>
8007510: 687b ldr r3, [r7, #4]
8007512: 681b ldr r3, [r3, #0]
8007514: 4a18 ldr r2, [pc, #96] @ (8007578 <HAL_TIMEx_MasterConfigSynchronization+0x108>)
8007516: 4293 cmp r3, r2
8007518: d009 beq.n 800752e <HAL_TIMEx_MasterConfigSynchronization+0xbe>
800751a: 687b ldr r3, [r7, #4]
800751c: 681b ldr r3, [r3, #0]
800751e: 4a13 ldr r2, [pc, #76] @ (800756c <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
8007520: 4293 cmp r3, r2
8007522: d004 beq.n 800752e <HAL_TIMEx_MasterConfigSynchronization+0xbe>
8007524: 687b ldr r3, [r7, #4]
8007526: 681b ldr r3, [r3, #0]
8007528: 4a14 ldr r2, [pc, #80] @ (800757c <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
800752a: 4293 cmp r3, r2
800752c: d10c bne.n 8007548 <HAL_TIMEx_MasterConfigSynchronization+0xd8>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800752e: 68bb ldr r3, [r7, #8]
8007530: f023 0380 bic.w r3, r3, #128 @ 0x80
8007534: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8007536: 683b ldr r3, [r7, #0]
8007538: 689b ldr r3, [r3, #8]
800753a: 68ba ldr r2, [r7, #8]
800753c: 4313 orrs r3, r2
800753e: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8007540: 687b ldr r3, [r7, #4]
8007542: 681b ldr r3, [r3, #0]
8007544: 68ba ldr r2, [r7, #8]
8007546: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8007548: 687b ldr r3, [r7, #4]
800754a: 2201 movs r2, #1
800754c: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8007550: 687b ldr r3, [r7, #4]
8007552: 2200 movs r2, #0
8007554: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8007558: 2300 movs r3, #0
}
800755a: 4618 mov r0, r3
800755c: 3714 adds r7, #20
800755e: 46bd mov sp, r7
8007560: f85d 7b04 ldr.w r7, [sp], #4
8007564: 4770 bx lr
8007566: bf00 nop
8007568: 40012c00 .word 0x40012c00
800756c: 40013400 .word 0x40013400
8007570: 40000400 .word 0x40000400
8007574: 40000800 .word 0x40000800
8007578: 40000c00 .word 0x40000c00
800757c: 40014000 .word 0x40014000
08007580 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8007580: b480 push {r7}
8007582: b083 sub sp, #12
8007584: af00 add r7, sp, #0
8007586: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8007588: bf00 nop
800758a: 370c adds r7, #12
800758c: 46bd mov sp, r7
800758e: f85d 7b04 ldr.w r7, [sp], #4
8007592: 4770 bx lr
08007594 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8007594: b480 push {r7}
8007596: b083 sub sp, #12
8007598: af00 add r7, sp, #0
800759a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
800759c: bf00 nop
800759e: 370c adds r7, #12
80075a0: 46bd mov sp, r7
80075a2: f85d 7b04 ldr.w r7, [sp], #4
80075a6: 4770 bx lr
080075a8 <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
80075a8: b480 push {r7}
80075aa: b083 sub sp, #12
80075ac: af00 add r7, sp, #0
80075ae: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
80075b0: bf00 nop
80075b2: 370c adds r7, #12
80075b4: 46bd mov sp, r7
80075b6: f85d 7b04 ldr.w r7, [sp], #4
80075ba: 4770 bx lr
080075bc <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80075bc: b580 push {r7, lr}
80075be: b082 sub sp, #8
80075c0: af00 add r7, sp, #0
80075c2: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80075c4: 687b ldr r3, [r7, #4]
80075c6: 2b00 cmp r3, #0
80075c8: d101 bne.n 80075ce <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80075ca: 2301 movs r3, #1
80075cc: e040 b.n 8007650 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
80075ce: 687b ldr r3, [r7, #4]
80075d0: 6fdb ldr r3, [r3, #124] @ 0x7c
80075d2: 2b00 cmp r3, #0
80075d4: d106 bne.n 80075e4 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80075d6: 687b ldr r3, [r7, #4]
80075d8: 2200 movs r2, #0
80075da: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80075de: 6878 ldr r0, [r7, #4]
80075e0: f7fa fb1e bl 8001c20 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80075e4: 687b ldr r3, [r7, #4]
80075e6: 2224 movs r2, #36 @ 0x24
80075e8: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
80075ea: 687b ldr r3, [r7, #4]
80075ec: 681b ldr r3, [r3, #0]
80075ee: 681a ldr r2, [r3, #0]
80075f0: 687b ldr r3, [r7, #4]
80075f2: 681b ldr r3, [r3, #0]
80075f4: f022 0201 bic.w r2, r2, #1
80075f8: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80075fa: 687b ldr r3, [r7, #4]
80075fc: 6a5b ldr r3, [r3, #36] @ 0x24
80075fe: 2b00 cmp r3, #0
8007600: d002 beq.n 8007608 <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
8007602: 6878 ldr r0, [r7, #4]
8007604: f000 fae0 bl 8007bc8 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8007608: 6878 ldr r0, [r7, #4]
800760a: f000 f825 bl 8007658 <UART_SetConfig>
800760e: 4603 mov r3, r0
8007610: 2b01 cmp r3, #1
8007612: d101 bne.n 8007618 <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
8007614: 2301 movs r3, #1
8007616: e01b b.n 8007650 <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8007618: 687b ldr r3, [r7, #4]
800761a: 681b ldr r3, [r3, #0]
800761c: 685a ldr r2, [r3, #4]
800761e: 687b ldr r3, [r7, #4]
8007620: 681b ldr r3, [r3, #0]
8007622: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8007626: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8007628: 687b ldr r3, [r7, #4]
800762a: 681b ldr r3, [r3, #0]
800762c: 689a ldr r2, [r3, #8]
800762e: 687b ldr r3, [r7, #4]
8007630: 681b ldr r3, [r3, #0]
8007632: f022 022a bic.w r2, r2, #42 @ 0x2a
8007636: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8007638: 687b ldr r3, [r7, #4]
800763a: 681b ldr r3, [r3, #0]
800763c: 681a ldr r2, [r3, #0]
800763e: 687b ldr r3, [r7, #4]
8007640: 681b ldr r3, [r3, #0]
8007642: f042 0201 orr.w r2, r2, #1
8007646: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8007648: 6878 ldr r0, [r7, #4]
800764a: f000 fb5f bl 8007d0c <UART_CheckIdleState>
800764e: 4603 mov r3, r0
}
8007650: 4618 mov r0, r3
8007652: 3708 adds r7, #8
8007654: 46bd mov sp, r7
8007656: bd80 pop {r7, pc}
08007658 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8007658: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
800765c: b08a sub sp, #40 @ 0x28
800765e: af00 add r7, sp, #0
8007660: 60f8 str r0, [r7, #12]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8007662: 2300 movs r3, #0
8007664: f887 3022 strb.w r3, [r7, #34] @ 0x22
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8007668: 68fb ldr r3, [r7, #12]
800766a: 689a ldr r2, [r3, #8]
800766c: 68fb ldr r3, [r7, #12]
800766e: 691b ldr r3, [r3, #16]
8007670: 431a orrs r2, r3
8007672: 68fb ldr r3, [r7, #12]
8007674: 695b ldr r3, [r3, #20]
8007676: 431a orrs r2, r3
8007678: 68fb ldr r3, [r7, #12]
800767a: 69db ldr r3, [r3, #28]
800767c: 4313 orrs r3, r2
800767e: 627b str r3, [r7, #36] @ 0x24
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8007680: 68fb ldr r3, [r7, #12]
8007682: 681b ldr r3, [r3, #0]
8007684: 681a ldr r2, [r3, #0]
8007686: 4ba4 ldr r3, [pc, #656] @ (8007918 <UART_SetConfig+0x2c0>)
8007688: 4013 ands r3, r2
800768a: 68fa ldr r2, [r7, #12]
800768c: 6812 ldr r2, [r2, #0]
800768e: 6a79 ldr r1, [r7, #36] @ 0x24
8007690: 430b orrs r3, r1
8007692: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8007694: 68fb ldr r3, [r7, #12]
8007696: 681b ldr r3, [r3, #0]
8007698: 685b ldr r3, [r3, #4]
800769a: f423 5140 bic.w r1, r3, #12288 @ 0x3000
800769e: 68fb ldr r3, [r7, #12]
80076a0: 68da ldr r2, [r3, #12]
80076a2: 68fb ldr r3, [r7, #12]
80076a4: 681b ldr r3, [r3, #0]
80076a6: 430a orrs r2, r1
80076a8: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
80076aa: 68fb ldr r3, [r7, #12]
80076ac: 699b ldr r3, [r3, #24]
80076ae: 627b str r3, [r7, #36] @ 0x24
if (!(UART_INSTANCE_LOWPOWER(huart)))
80076b0: 68fb ldr r3, [r7, #12]
80076b2: 681b ldr r3, [r3, #0]
80076b4: 4a99 ldr r2, [pc, #612] @ (800791c <UART_SetConfig+0x2c4>)
80076b6: 4293 cmp r3, r2
80076b8: d004 beq.n 80076c4 <UART_SetConfig+0x6c>
{
tmpreg |= huart->Init.OneBitSampling;
80076ba: 68fb ldr r3, [r7, #12]
80076bc: 6a1b ldr r3, [r3, #32]
80076be: 6a7a ldr r2, [r7, #36] @ 0x24
80076c0: 4313 orrs r3, r2
80076c2: 627b str r3, [r7, #36] @ 0x24
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
80076c4: 68fb ldr r3, [r7, #12]
80076c6: 681b ldr r3, [r3, #0]
80076c8: 689b ldr r3, [r3, #8]
80076ca: f423 6130 bic.w r1, r3, #2816 @ 0xb00
80076ce: 68fb ldr r3, [r7, #12]
80076d0: 681b ldr r3, [r3, #0]
80076d2: 6a7a ldr r2, [r7, #36] @ 0x24
80076d4: 430a orrs r2, r1
80076d6: 609a str r2, [r3, #8]
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
#endif /* USART_PRESC_PRESCALER */
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
80076d8: 68fb ldr r3, [r7, #12]
80076da: 681b ldr r3, [r3, #0]
80076dc: 4a90 ldr r2, [pc, #576] @ (8007920 <UART_SetConfig+0x2c8>)
80076de: 4293 cmp r3, r2
80076e0: d126 bne.n 8007730 <UART_SetConfig+0xd8>
80076e2: 4b90 ldr r3, [pc, #576] @ (8007924 <UART_SetConfig+0x2cc>)
80076e4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80076e8: f003 0303 and.w r3, r3, #3
80076ec: 2b03 cmp r3, #3
80076ee: d81b bhi.n 8007728 <UART_SetConfig+0xd0>
80076f0: a201 add r2, pc, #4 @ (adr r2, 80076f8 <UART_SetConfig+0xa0>)
80076f2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80076f6: bf00 nop
80076f8: 08007709 .word 0x08007709
80076fc: 08007719 .word 0x08007719
8007700: 08007711 .word 0x08007711
8007704: 08007721 .word 0x08007721
8007708: 2301 movs r3, #1
800770a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800770e: e116 b.n 800793e <UART_SetConfig+0x2e6>
8007710: 2302 movs r3, #2
8007712: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007716: e112 b.n 800793e <UART_SetConfig+0x2e6>
8007718: 2304 movs r3, #4
800771a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800771e: e10e b.n 800793e <UART_SetConfig+0x2e6>
8007720: 2308 movs r3, #8
8007722: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007726: e10a b.n 800793e <UART_SetConfig+0x2e6>
8007728: 2310 movs r3, #16
800772a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800772e: e106 b.n 800793e <UART_SetConfig+0x2e6>
8007730: 68fb ldr r3, [r7, #12]
8007732: 681b ldr r3, [r3, #0]
8007734: 4a7c ldr r2, [pc, #496] @ (8007928 <UART_SetConfig+0x2d0>)
8007736: 4293 cmp r3, r2
8007738: d138 bne.n 80077ac <UART_SetConfig+0x154>
800773a: 4b7a ldr r3, [pc, #488] @ (8007924 <UART_SetConfig+0x2cc>)
800773c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007740: f003 030c and.w r3, r3, #12
8007744: 2b0c cmp r3, #12
8007746: d82d bhi.n 80077a4 <UART_SetConfig+0x14c>
8007748: a201 add r2, pc, #4 @ (adr r2, 8007750 <UART_SetConfig+0xf8>)
800774a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800774e: bf00 nop
8007750: 08007785 .word 0x08007785
8007754: 080077a5 .word 0x080077a5
8007758: 080077a5 .word 0x080077a5
800775c: 080077a5 .word 0x080077a5
8007760: 08007795 .word 0x08007795
8007764: 080077a5 .word 0x080077a5
8007768: 080077a5 .word 0x080077a5
800776c: 080077a5 .word 0x080077a5
8007770: 0800778d .word 0x0800778d
8007774: 080077a5 .word 0x080077a5
8007778: 080077a5 .word 0x080077a5
800777c: 080077a5 .word 0x080077a5
8007780: 0800779d .word 0x0800779d
8007784: 2300 movs r3, #0
8007786: f887 3023 strb.w r3, [r7, #35] @ 0x23
800778a: e0d8 b.n 800793e <UART_SetConfig+0x2e6>
800778c: 2302 movs r3, #2
800778e: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007792: e0d4 b.n 800793e <UART_SetConfig+0x2e6>
8007794: 2304 movs r3, #4
8007796: f887 3023 strb.w r3, [r7, #35] @ 0x23
800779a: e0d0 b.n 800793e <UART_SetConfig+0x2e6>
800779c: 2308 movs r3, #8
800779e: f887 3023 strb.w r3, [r7, #35] @ 0x23
80077a2: e0cc b.n 800793e <UART_SetConfig+0x2e6>
80077a4: 2310 movs r3, #16
80077a6: f887 3023 strb.w r3, [r7, #35] @ 0x23
80077aa: e0c8 b.n 800793e <UART_SetConfig+0x2e6>
80077ac: 68fb ldr r3, [r7, #12]
80077ae: 681b ldr r3, [r3, #0]
80077b0: 4a5e ldr r2, [pc, #376] @ (800792c <UART_SetConfig+0x2d4>)
80077b2: 4293 cmp r3, r2
80077b4: d125 bne.n 8007802 <UART_SetConfig+0x1aa>
80077b6: 4b5b ldr r3, [pc, #364] @ (8007924 <UART_SetConfig+0x2cc>)
80077b8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80077bc: f003 0330 and.w r3, r3, #48 @ 0x30
80077c0: 2b30 cmp r3, #48 @ 0x30
80077c2: d016 beq.n 80077f2 <UART_SetConfig+0x19a>
80077c4: 2b30 cmp r3, #48 @ 0x30
80077c6: d818 bhi.n 80077fa <UART_SetConfig+0x1a2>
80077c8: 2b20 cmp r3, #32
80077ca: d00a beq.n 80077e2 <UART_SetConfig+0x18a>
80077cc: 2b20 cmp r3, #32
80077ce: d814 bhi.n 80077fa <UART_SetConfig+0x1a2>
80077d0: 2b00 cmp r3, #0
80077d2: d002 beq.n 80077da <UART_SetConfig+0x182>
80077d4: 2b10 cmp r3, #16
80077d6: d008 beq.n 80077ea <UART_SetConfig+0x192>
80077d8: e00f b.n 80077fa <UART_SetConfig+0x1a2>
80077da: 2300 movs r3, #0
80077dc: f887 3023 strb.w r3, [r7, #35] @ 0x23
80077e0: e0ad b.n 800793e <UART_SetConfig+0x2e6>
80077e2: 2302 movs r3, #2
80077e4: f887 3023 strb.w r3, [r7, #35] @ 0x23
80077e8: e0a9 b.n 800793e <UART_SetConfig+0x2e6>
80077ea: 2304 movs r3, #4
80077ec: f887 3023 strb.w r3, [r7, #35] @ 0x23
80077f0: e0a5 b.n 800793e <UART_SetConfig+0x2e6>
80077f2: 2308 movs r3, #8
80077f4: f887 3023 strb.w r3, [r7, #35] @ 0x23
80077f8: e0a1 b.n 800793e <UART_SetConfig+0x2e6>
80077fa: 2310 movs r3, #16
80077fc: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007800: e09d b.n 800793e <UART_SetConfig+0x2e6>
8007802: 68fb ldr r3, [r7, #12]
8007804: 681b ldr r3, [r3, #0]
8007806: 4a4a ldr r2, [pc, #296] @ (8007930 <UART_SetConfig+0x2d8>)
8007808: 4293 cmp r3, r2
800780a: d125 bne.n 8007858 <UART_SetConfig+0x200>
800780c: 4b45 ldr r3, [pc, #276] @ (8007924 <UART_SetConfig+0x2cc>)
800780e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007812: f003 03c0 and.w r3, r3, #192 @ 0xc0
8007816: 2bc0 cmp r3, #192 @ 0xc0
8007818: d016 beq.n 8007848 <UART_SetConfig+0x1f0>
800781a: 2bc0 cmp r3, #192 @ 0xc0
800781c: d818 bhi.n 8007850 <UART_SetConfig+0x1f8>
800781e: 2b80 cmp r3, #128 @ 0x80
8007820: d00a beq.n 8007838 <UART_SetConfig+0x1e0>
8007822: 2b80 cmp r3, #128 @ 0x80
8007824: d814 bhi.n 8007850 <UART_SetConfig+0x1f8>
8007826: 2b00 cmp r3, #0
8007828: d002 beq.n 8007830 <UART_SetConfig+0x1d8>
800782a: 2b40 cmp r3, #64 @ 0x40
800782c: d008 beq.n 8007840 <UART_SetConfig+0x1e8>
800782e: e00f b.n 8007850 <UART_SetConfig+0x1f8>
8007830: 2300 movs r3, #0
8007832: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007836: e082 b.n 800793e <UART_SetConfig+0x2e6>
8007838: 2302 movs r3, #2
800783a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800783e: e07e b.n 800793e <UART_SetConfig+0x2e6>
8007840: 2304 movs r3, #4
8007842: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007846: e07a b.n 800793e <UART_SetConfig+0x2e6>
8007848: 2308 movs r3, #8
800784a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800784e: e076 b.n 800793e <UART_SetConfig+0x2e6>
8007850: 2310 movs r3, #16
8007852: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007856: e072 b.n 800793e <UART_SetConfig+0x2e6>
8007858: 68fb ldr r3, [r7, #12]
800785a: 681b ldr r3, [r3, #0]
800785c: 4a35 ldr r2, [pc, #212] @ (8007934 <UART_SetConfig+0x2dc>)
800785e: 4293 cmp r3, r2
8007860: d12a bne.n 80078b8 <UART_SetConfig+0x260>
8007862: 4b30 ldr r3, [pc, #192] @ (8007924 <UART_SetConfig+0x2cc>)
8007864: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007868: f403 7340 and.w r3, r3, #768 @ 0x300
800786c: f5b3 7f40 cmp.w r3, #768 @ 0x300
8007870: d01a beq.n 80078a8 <UART_SetConfig+0x250>
8007872: f5b3 7f40 cmp.w r3, #768 @ 0x300
8007876: d81b bhi.n 80078b0 <UART_SetConfig+0x258>
8007878: f5b3 7f00 cmp.w r3, #512 @ 0x200
800787c: d00c beq.n 8007898 <UART_SetConfig+0x240>
800787e: f5b3 7f00 cmp.w r3, #512 @ 0x200
8007882: d815 bhi.n 80078b0 <UART_SetConfig+0x258>
8007884: 2b00 cmp r3, #0
8007886: d003 beq.n 8007890 <UART_SetConfig+0x238>
8007888: f5b3 7f80 cmp.w r3, #256 @ 0x100
800788c: d008 beq.n 80078a0 <UART_SetConfig+0x248>
800788e: e00f b.n 80078b0 <UART_SetConfig+0x258>
8007890: 2300 movs r3, #0
8007892: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007896: e052 b.n 800793e <UART_SetConfig+0x2e6>
8007898: 2302 movs r3, #2
800789a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800789e: e04e b.n 800793e <UART_SetConfig+0x2e6>
80078a0: 2304 movs r3, #4
80078a2: f887 3023 strb.w r3, [r7, #35] @ 0x23
80078a6: e04a b.n 800793e <UART_SetConfig+0x2e6>
80078a8: 2308 movs r3, #8
80078aa: f887 3023 strb.w r3, [r7, #35] @ 0x23
80078ae: e046 b.n 800793e <UART_SetConfig+0x2e6>
80078b0: 2310 movs r3, #16
80078b2: f887 3023 strb.w r3, [r7, #35] @ 0x23
80078b6: e042 b.n 800793e <UART_SetConfig+0x2e6>
80078b8: 68fb ldr r3, [r7, #12]
80078ba: 681b ldr r3, [r3, #0]
80078bc: 4a17 ldr r2, [pc, #92] @ (800791c <UART_SetConfig+0x2c4>)
80078be: 4293 cmp r3, r2
80078c0: d13a bne.n 8007938 <UART_SetConfig+0x2e0>
80078c2: 4b18 ldr r3, [pc, #96] @ (8007924 <UART_SetConfig+0x2cc>)
80078c4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80078c8: f403 6340 and.w r3, r3, #3072 @ 0xc00
80078cc: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80078d0: d01a beq.n 8007908 <UART_SetConfig+0x2b0>
80078d2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80078d6: d81b bhi.n 8007910 <UART_SetConfig+0x2b8>
80078d8: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80078dc: d00c beq.n 80078f8 <UART_SetConfig+0x2a0>
80078de: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80078e2: d815 bhi.n 8007910 <UART_SetConfig+0x2b8>
80078e4: 2b00 cmp r3, #0
80078e6: d003 beq.n 80078f0 <UART_SetConfig+0x298>
80078e8: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80078ec: d008 beq.n 8007900 <UART_SetConfig+0x2a8>
80078ee: e00f b.n 8007910 <UART_SetConfig+0x2b8>
80078f0: 2300 movs r3, #0
80078f2: f887 3023 strb.w r3, [r7, #35] @ 0x23
80078f6: e022 b.n 800793e <UART_SetConfig+0x2e6>
80078f8: 2302 movs r3, #2
80078fa: f887 3023 strb.w r3, [r7, #35] @ 0x23
80078fe: e01e b.n 800793e <UART_SetConfig+0x2e6>
8007900: 2304 movs r3, #4
8007902: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007906: e01a b.n 800793e <UART_SetConfig+0x2e6>
8007908: 2308 movs r3, #8
800790a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800790e: e016 b.n 800793e <UART_SetConfig+0x2e6>
8007910: 2310 movs r3, #16
8007912: f887 3023 strb.w r3, [r7, #35] @ 0x23
8007916: e012 b.n 800793e <UART_SetConfig+0x2e6>
8007918: efff69f3 .word 0xefff69f3
800791c: 40008000 .word 0x40008000
8007920: 40013800 .word 0x40013800
8007924: 40021000 .word 0x40021000
8007928: 40004400 .word 0x40004400
800792c: 40004800 .word 0x40004800
8007930: 40004c00 .word 0x40004c00
8007934: 40005000 .word 0x40005000
8007938: 2310 movs r3, #16
800793a: f887 3023 strb.w r3, [r7, #35] @ 0x23
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
800793e: 68fb ldr r3, [r7, #12]
8007940: 681b ldr r3, [r3, #0]
8007942: 4a9f ldr r2, [pc, #636] @ (8007bc0 <UART_SetConfig+0x568>)
8007944: 4293 cmp r3, r2
8007946: d17a bne.n 8007a3e <UART_SetConfig+0x3e6>
{
/* Retrieve frequency clock */
switch (clocksource)
8007948: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
800794c: 2b08 cmp r3, #8
800794e: d824 bhi.n 800799a <UART_SetConfig+0x342>
8007950: a201 add r2, pc, #4 @ (adr r2, 8007958 <UART_SetConfig+0x300>)
8007952: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007956: bf00 nop
8007958: 0800797d .word 0x0800797d
800795c: 0800799b .word 0x0800799b
8007960: 08007985 .word 0x08007985
8007964: 0800799b .word 0x0800799b
8007968: 0800798b .word 0x0800798b
800796c: 0800799b .word 0x0800799b
8007970: 0800799b .word 0x0800799b
8007974: 0800799b .word 0x0800799b
8007978: 08007993 .word 0x08007993
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800797c: f7fe f906 bl 8005b8c <HAL_RCC_GetPCLK1Freq>
8007980: 61f8 str r0, [r7, #28]
break;
8007982: e010 b.n 80079a6 <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8007984: 4b8f ldr r3, [pc, #572] @ (8007bc4 <UART_SetConfig+0x56c>)
8007986: 61fb str r3, [r7, #28]
break;
8007988: e00d b.n 80079a6 <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800798a: f7fe f867 bl 8005a5c <HAL_RCC_GetSysClockFreq>
800798e: 61f8 str r0, [r7, #28]
break;
8007990: e009 b.n 80079a6 <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8007992: f44f 4300 mov.w r3, #32768 @ 0x8000
8007996: 61fb str r3, [r7, #28]
break;
8007998: e005 b.n 80079a6 <UART_SetConfig+0x34e>
default:
pclk = 0U;
800799a: 2300 movs r3, #0
800799c: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
800799e: 2301 movs r3, #1
80079a0: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
80079a4: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
80079a6: 69fb ldr r3, [r7, #28]
80079a8: 2b00 cmp r3, #0
80079aa: f000 80fb beq.w 8007ba4 <UART_SetConfig+0x54c>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
#else
/* No Prescaler applicable */
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((pclk < (3U * huart->Init.BaudRate)) ||
80079ae: 68fb ldr r3, [r7, #12]
80079b0: 685a ldr r2, [r3, #4]
80079b2: 4613 mov r3, r2
80079b4: 005b lsls r3, r3, #1
80079b6: 4413 add r3, r2
80079b8: 69fa ldr r2, [r7, #28]
80079ba: 429a cmp r2, r3
80079bc: d305 bcc.n 80079ca <UART_SetConfig+0x372>
(pclk > (4096U * huart->Init.BaudRate)))
80079be: 68fb ldr r3, [r7, #12]
80079c0: 685b ldr r3, [r3, #4]
80079c2: 031b lsls r3, r3, #12
if ((pclk < (3U * huart->Init.BaudRate)) ||
80079c4: 69fa ldr r2, [r7, #28]
80079c6: 429a cmp r2, r3
80079c8: d903 bls.n 80079d2 <UART_SetConfig+0x37a>
{
ret = HAL_ERROR;
80079ca: 2301 movs r3, #1
80079cc: f887 3022 strb.w r3, [r7, #34] @ 0x22
80079d0: e0e8 b.n 8007ba4 <UART_SetConfig+0x54c>
}
else
{
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
80079d2: 69fb ldr r3, [r7, #28]
80079d4: 2200 movs r2, #0
80079d6: 461c mov r4, r3
80079d8: 4615 mov r5, r2
80079da: f04f 0200 mov.w r2, #0
80079de: f04f 0300 mov.w r3, #0
80079e2: 022b lsls r3, r5, #8
80079e4: ea43 6314 orr.w r3, r3, r4, lsr #24
80079e8: 0222 lsls r2, r4, #8
80079ea: 68f9 ldr r1, [r7, #12]
80079ec: 6849 ldr r1, [r1, #4]
80079ee: 0849 lsrs r1, r1, #1
80079f0: 2000 movs r0, #0
80079f2: 4688 mov r8, r1
80079f4: 4681 mov r9, r0
80079f6: eb12 0a08 adds.w sl, r2, r8
80079fa: eb43 0b09 adc.w fp, r3, r9
80079fe: 68fb ldr r3, [r7, #12]
8007a00: 685b ldr r3, [r3, #4]
8007a02: 2200 movs r2, #0
8007a04: 603b str r3, [r7, #0]
8007a06: 607a str r2, [r7, #4]
8007a08: e9d7 2300 ldrd r2, r3, [r7]
8007a0c: 4650 mov r0, sl
8007a0e: 4659 mov r1, fp
8007a10: f7f9 f8ca bl 8000ba8 <__aeabi_uldivmod>
8007a14: 4602 mov r2, r0
8007a16: 460b mov r3, r1
8007a18: 4613 mov r3, r2
8007a1a: 61bb str r3, [r7, #24]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
8007a1c: 69bb ldr r3, [r7, #24]
8007a1e: f5b3 7f40 cmp.w r3, #768 @ 0x300
8007a22: d308 bcc.n 8007a36 <UART_SetConfig+0x3de>
8007a24: 69bb ldr r3, [r7, #24]
8007a26: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8007a2a: d204 bcs.n 8007a36 <UART_SetConfig+0x3de>
{
huart->Instance->BRR = usartdiv;
8007a2c: 68fb ldr r3, [r7, #12]
8007a2e: 681b ldr r3, [r3, #0]
8007a30: 69ba ldr r2, [r7, #24]
8007a32: 60da str r2, [r3, #12]
8007a34: e0b6 b.n 8007ba4 <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
8007a36: 2301 movs r3, #1
8007a38: f887 3022 strb.w r3, [r7, #34] @ 0x22
8007a3c: e0b2 b.n 8007ba4 <UART_SetConfig+0x54c>
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
#endif /* USART_PRESC_PRESCALER */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8007a3e: 68fb ldr r3, [r7, #12]
8007a40: 69db ldr r3, [r3, #28]
8007a42: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8007a46: d15e bne.n 8007b06 <UART_SetConfig+0x4ae>
{
switch (clocksource)
8007a48: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
8007a4c: 2b08 cmp r3, #8
8007a4e: d828 bhi.n 8007aa2 <UART_SetConfig+0x44a>
8007a50: a201 add r2, pc, #4 @ (adr r2, 8007a58 <UART_SetConfig+0x400>)
8007a52: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007a56: bf00 nop
8007a58: 08007a7d .word 0x08007a7d
8007a5c: 08007a85 .word 0x08007a85
8007a60: 08007a8d .word 0x08007a8d
8007a64: 08007aa3 .word 0x08007aa3
8007a68: 08007a93 .word 0x08007a93
8007a6c: 08007aa3 .word 0x08007aa3
8007a70: 08007aa3 .word 0x08007aa3
8007a74: 08007aa3 .word 0x08007aa3
8007a78: 08007a9b .word 0x08007a9b
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8007a7c: f7fe f886 bl 8005b8c <HAL_RCC_GetPCLK1Freq>
8007a80: 61f8 str r0, [r7, #28]
break;
8007a82: e014 b.n 8007aae <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8007a84: f7fe f898 bl 8005bb8 <HAL_RCC_GetPCLK2Freq>
8007a88: 61f8 str r0, [r7, #28]
break;
8007a8a: e010 b.n 8007aae <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8007a8c: 4b4d ldr r3, [pc, #308] @ (8007bc4 <UART_SetConfig+0x56c>)
8007a8e: 61fb str r3, [r7, #28]
break;
8007a90: e00d b.n 8007aae <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8007a92: f7fd ffe3 bl 8005a5c <HAL_RCC_GetSysClockFreq>
8007a96: 61f8 str r0, [r7, #28]
break;
8007a98: e009 b.n 8007aae <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8007a9a: f44f 4300 mov.w r3, #32768 @ 0x8000
8007a9e: 61fb str r3, [r7, #28]
break;
8007aa0: e005 b.n 8007aae <UART_SetConfig+0x456>
default:
pclk = 0U;
8007aa2: 2300 movs r3, #0
8007aa4: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
8007aa6: 2301 movs r3, #1
8007aa8: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
8007aac: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8007aae: 69fb ldr r3, [r7, #28]
8007ab0: 2b00 cmp r3, #0
8007ab2: d077 beq.n 8007ba4 <UART_SetConfig+0x54c>
{
#if defined(USART_PRESC_PRESCALER)
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
8007ab4: 69fb ldr r3, [r7, #28]
8007ab6: 005a lsls r2, r3, #1
8007ab8: 68fb ldr r3, [r7, #12]
8007aba: 685b ldr r3, [r3, #4]
8007abc: 085b lsrs r3, r3, #1
8007abe: 441a add r2, r3
8007ac0: 68fb ldr r3, [r7, #12]
8007ac2: 685b ldr r3, [r3, #4]
8007ac4: fbb2 f3f3 udiv r3, r2, r3
8007ac8: 61bb str r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8007aca: 69bb ldr r3, [r7, #24]
8007acc: 2b0f cmp r3, #15
8007ace: d916 bls.n 8007afe <UART_SetConfig+0x4a6>
8007ad0: 69bb ldr r3, [r7, #24]
8007ad2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8007ad6: d212 bcs.n 8007afe <UART_SetConfig+0x4a6>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8007ad8: 69bb ldr r3, [r7, #24]
8007ada: b29b uxth r3, r3
8007adc: f023 030f bic.w r3, r3, #15
8007ae0: 82fb strh r3, [r7, #22]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8007ae2: 69bb ldr r3, [r7, #24]
8007ae4: 085b lsrs r3, r3, #1
8007ae6: b29b uxth r3, r3
8007ae8: f003 0307 and.w r3, r3, #7
8007aec: b29a uxth r2, r3
8007aee: 8afb ldrh r3, [r7, #22]
8007af0: 4313 orrs r3, r2
8007af2: 82fb strh r3, [r7, #22]
huart->Instance->BRR = brrtemp;
8007af4: 68fb ldr r3, [r7, #12]
8007af6: 681b ldr r3, [r3, #0]
8007af8: 8afa ldrh r2, [r7, #22]
8007afa: 60da str r2, [r3, #12]
8007afc: e052 b.n 8007ba4 <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
8007afe: 2301 movs r3, #1
8007b00: f887 3022 strb.w r3, [r7, #34] @ 0x22
8007b04: e04e b.n 8007ba4 <UART_SetConfig+0x54c>
}
}
}
else
{
switch (clocksource)
8007b06: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
8007b0a: 2b08 cmp r3, #8
8007b0c: d827 bhi.n 8007b5e <UART_SetConfig+0x506>
8007b0e: a201 add r2, pc, #4 @ (adr r2, 8007b14 <UART_SetConfig+0x4bc>)
8007b10: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007b14: 08007b39 .word 0x08007b39
8007b18: 08007b41 .word 0x08007b41
8007b1c: 08007b49 .word 0x08007b49
8007b20: 08007b5f .word 0x08007b5f
8007b24: 08007b4f .word 0x08007b4f
8007b28: 08007b5f .word 0x08007b5f
8007b2c: 08007b5f .word 0x08007b5f
8007b30: 08007b5f .word 0x08007b5f
8007b34: 08007b57 .word 0x08007b57
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8007b38: f7fe f828 bl 8005b8c <HAL_RCC_GetPCLK1Freq>
8007b3c: 61f8 str r0, [r7, #28]
break;
8007b3e: e014 b.n 8007b6a <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8007b40: f7fe f83a bl 8005bb8 <HAL_RCC_GetPCLK2Freq>
8007b44: 61f8 str r0, [r7, #28]
break;
8007b46: e010 b.n 8007b6a <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8007b48: 4b1e ldr r3, [pc, #120] @ (8007bc4 <UART_SetConfig+0x56c>)
8007b4a: 61fb str r3, [r7, #28]
break;
8007b4c: e00d b.n 8007b6a <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8007b4e: f7fd ff85 bl 8005a5c <HAL_RCC_GetSysClockFreq>
8007b52: 61f8 str r0, [r7, #28]
break;
8007b54: e009 b.n 8007b6a <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8007b56: f44f 4300 mov.w r3, #32768 @ 0x8000
8007b5a: 61fb str r3, [r7, #28]
break;
8007b5c: e005 b.n 8007b6a <UART_SetConfig+0x512>
default:
pclk = 0U;
8007b5e: 2300 movs r3, #0
8007b60: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
8007b62: 2301 movs r3, #1
8007b64: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
8007b68: bf00 nop
}
if (pclk != 0U)
8007b6a: 69fb ldr r3, [r7, #28]
8007b6c: 2b00 cmp r3, #0
8007b6e: d019 beq.n 8007ba4 <UART_SetConfig+0x54c>
{
/* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
8007b70: 68fb ldr r3, [r7, #12]
8007b72: 685b ldr r3, [r3, #4]
8007b74: 085a lsrs r2, r3, #1
8007b76: 69fb ldr r3, [r7, #28]
8007b78: 441a add r2, r3
8007b7a: 68fb ldr r3, [r7, #12]
8007b7c: 685b ldr r3, [r3, #4]
8007b7e: fbb2 f3f3 udiv r3, r2, r3
8007b82: 61bb str r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8007b84: 69bb ldr r3, [r7, #24]
8007b86: 2b0f cmp r3, #15
8007b88: d909 bls.n 8007b9e <UART_SetConfig+0x546>
8007b8a: 69bb ldr r3, [r7, #24]
8007b8c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8007b90: d205 bcs.n 8007b9e <UART_SetConfig+0x546>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8007b92: 69bb ldr r3, [r7, #24]
8007b94: b29a uxth r2, r3
8007b96: 68fb ldr r3, [r7, #12]
8007b98: 681b ldr r3, [r3, #0]
8007b9a: 60da str r2, [r3, #12]
8007b9c: e002 b.n 8007ba4 <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
8007b9e: 2301 movs r3, #1
8007ba0: f887 3022 strb.w r3, [r7, #34] @ 0x22
huart->NbTxDataToProcess = 1;
huart->NbRxDataToProcess = 1;
#endif /* USART_CR1_FIFOEN */
/* Clear ISR function pointers */
huart->RxISR = NULL;
8007ba4: 68fb ldr r3, [r7, #12]
8007ba6: 2200 movs r2, #0
8007ba8: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
8007baa: 68fb ldr r3, [r7, #12]
8007bac: 2200 movs r2, #0
8007bae: 66da str r2, [r3, #108] @ 0x6c
return ret;
8007bb0: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
}
8007bb4: 4618 mov r0, r3
8007bb6: 3728 adds r7, #40 @ 0x28
8007bb8: 46bd mov sp, r7
8007bba: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8007bbe: bf00 nop
8007bc0: 40008000 .word 0x40008000
8007bc4: 00f42400 .word 0x00f42400
08007bc8 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8007bc8: b480 push {r7}
8007bca: b083 sub sp, #12
8007bcc: af00 add r7, sp, #0
8007bce: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8007bd0: 687b ldr r3, [r7, #4]
8007bd2: 6a5b ldr r3, [r3, #36] @ 0x24
8007bd4: f003 0308 and.w r3, r3, #8
8007bd8: 2b00 cmp r3, #0
8007bda: d00a beq.n 8007bf2 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8007bdc: 687b ldr r3, [r7, #4]
8007bde: 681b ldr r3, [r3, #0]
8007be0: 685b ldr r3, [r3, #4]
8007be2: f423 4100 bic.w r1, r3, #32768 @ 0x8000
8007be6: 687b ldr r3, [r7, #4]
8007be8: 6b5a ldr r2, [r3, #52] @ 0x34
8007bea: 687b ldr r3, [r7, #4]
8007bec: 681b ldr r3, [r3, #0]
8007bee: 430a orrs r2, r1
8007bf0: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8007bf2: 687b ldr r3, [r7, #4]
8007bf4: 6a5b ldr r3, [r3, #36] @ 0x24
8007bf6: f003 0301 and.w r3, r3, #1
8007bfa: 2b00 cmp r3, #0
8007bfc: d00a beq.n 8007c14 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8007bfe: 687b ldr r3, [r7, #4]
8007c00: 681b ldr r3, [r3, #0]
8007c02: 685b ldr r3, [r3, #4]
8007c04: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8007c08: 687b ldr r3, [r7, #4]
8007c0a: 6a9a ldr r2, [r3, #40] @ 0x28
8007c0c: 687b ldr r3, [r7, #4]
8007c0e: 681b ldr r3, [r3, #0]
8007c10: 430a orrs r2, r1
8007c12: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8007c14: 687b ldr r3, [r7, #4]
8007c16: 6a5b ldr r3, [r3, #36] @ 0x24
8007c18: f003 0302 and.w r3, r3, #2
8007c1c: 2b00 cmp r3, #0
8007c1e: d00a beq.n 8007c36 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8007c20: 687b ldr r3, [r7, #4]
8007c22: 681b ldr r3, [r3, #0]
8007c24: 685b ldr r3, [r3, #4]
8007c26: f423 3180 bic.w r1, r3, #65536 @ 0x10000
8007c2a: 687b ldr r3, [r7, #4]
8007c2c: 6ada ldr r2, [r3, #44] @ 0x2c
8007c2e: 687b ldr r3, [r7, #4]
8007c30: 681b ldr r3, [r3, #0]
8007c32: 430a orrs r2, r1
8007c34: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8007c36: 687b ldr r3, [r7, #4]
8007c38: 6a5b ldr r3, [r3, #36] @ 0x24
8007c3a: f003 0304 and.w r3, r3, #4
8007c3e: 2b00 cmp r3, #0
8007c40: d00a beq.n 8007c58 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8007c42: 687b ldr r3, [r7, #4]
8007c44: 681b ldr r3, [r3, #0]
8007c46: 685b ldr r3, [r3, #4]
8007c48: f423 2180 bic.w r1, r3, #262144 @ 0x40000
8007c4c: 687b ldr r3, [r7, #4]
8007c4e: 6b1a ldr r2, [r3, #48] @ 0x30
8007c50: 687b ldr r3, [r7, #4]
8007c52: 681b ldr r3, [r3, #0]
8007c54: 430a orrs r2, r1
8007c56: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8007c58: 687b ldr r3, [r7, #4]
8007c5a: 6a5b ldr r3, [r3, #36] @ 0x24
8007c5c: f003 0310 and.w r3, r3, #16
8007c60: 2b00 cmp r3, #0
8007c62: d00a beq.n 8007c7a <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8007c64: 687b ldr r3, [r7, #4]
8007c66: 681b ldr r3, [r3, #0]
8007c68: 689b ldr r3, [r3, #8]
8007c6a: f423 5180 bic.w r1, r3, #4096 @ 0x1000
8007c6e: 687b ldr r3, [r7, #4]
8007c70: 6b9a ldr r2, [r3, #56] @ 0x38
8007c72: 687b ldr r3, [r7, #4]
8007c74: 681b ldr r3, [r3, #0]
8007c76: 430a orrs r2, r1
8007c78: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8007c7a: 687b ldr r3, [r7, #4]
8007c7c: 6a5b ldr r3, [r3, #36] @ 0x24
8007c7e: f003 0320 and.w r3, r3, #32
8007c82: 2b00 cmp r3, #0
8007c84: d00a beq.n 8007c9c <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8007c86: 687b ldr r3, [r7, #4]
8007c88: 681b ldr r3, [r3, #0]
8007c8a: 689b ldr r3, [r3, #8]
8007c8c: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8007c90: 687b ldr r3, [r7, #4]
8007c92: 6bda ldr r2, [r3, #60] @ 0x3c
8007c94: 687b ldr r3, [r7, #4]
8007c96: 681b ldr r3, [r3, #0]
8007c98: 430a orrs r2, r1
8007c9a: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8007c9c: 687b ldr r3, [r7, #4]
8007c9e: 6a5b ldr r3, [r3, #36] @ 0x24
8007ca0: f003 0340 and.w r3, r3, #64 @ 0x40
8007ca4: 2b00 cmp r3, #0
8007ca6: d01a beq.n 8007cde <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8007ca8: 687b ldr r3, [r7, #4]
8007caa: 681b ldr r3, [r3, #0]
8007cac: 685b ldr r3, [r3, #4]
8007cae: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
8007cb2: 687b ldr r3, [r7, #4]
8007cb4: 6c1a ldr r2, [r3, #64] @ 0x40
8007cb6: 687b ldr r3, [r7, #4]
8007cb8: 681b ldr r3, [r3, #0]
8007cba: 430a orrs r2, r1
8007cbc: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8007cbe: 687b ldr r3, [r7, #4]
8007cc0: 6c1b ldr r3, [r3, #64] @ 0x40
8007cc2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8007cc6: d10a bne.n 8007cde <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8007cc8: 687b ldr r3, [r7, #4]
8007cca: 681b ldr r3, [r3, #0]
8007ccc: 685b ldr r3, [r3, #4]
8007cce: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8007cd2: 687b ldr r3, [r7, #4]
8007cd4: 6c5a ldr r2, [r3, #68] @ 0x44
8007cd6: 687b ldr r3, [r7, #4]
8007cd8: 681b ldr r3, [r3, #0]
8007cda: 430a orrs r2, r1
8007cdc: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8007cde: 687b ldr r3, [r7, #4]
8007ce0: 6a5b ldr r3, [r3, #36] @ 0x24
8007ce2: f003 0380 and.w r3, r3, #128 @ 0x80
8007ce6: 2b00 cmp r3, #0
8007ce8: d00a beq.n 8007d00 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8007cea: 687b ldr r3, [r7, #4]
8007cec: 681b ldr r3, [r3, #0]
8007cee: 685b ldr r3, [r3, #4]
8007cf0: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8007cf4: 687b ldr r3, [r7, #4]
8007cf6: 6c9a ldr r2, [r3, #72] @ 0x48
8007cf8: 687b ldr r3, [r7, #4]
8007cfa: 681b ldr r3, [r3, #0]
8007cfc: 430a orrs r2, r1
8007cfe: 605a str r2, [r3, #4]
}
}
8007d00: bf00 nop
8007d02: 370c adds r7, #12
8007d04: 46bd mov sp, r7
8007d06: f85d 7b04 ldr.w r7, [sp], #4
8007d0a: 4770 bx lr
08007d0c <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8007d0c: b580 push {r7, lr}
8007d0e: b098 sub sp, #96 @ 0x60
8007d10: af02 add r7, sp, #8
8007d12: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007d14: 687b ldr r3, [r7, #4]
8007d16: 2200 movs r2, #0
8007d18: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8007d1c: f7fa f9fa bl 8002114 <HAL_GetTick>
8007d20: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8007d22: 687b ldr r3, [r7, #4]
8007d24: 681b ldr r3, [r3, #0]
8007d26: 681b ldr r3, [r3, #0]
8007d28: f003 0308 and.w r3, r3, #8
8007d2c: 2b08 cmp r3, #8
8007d2e: d12e bne.n 8007d8e <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8007d30: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8007d34: 9300 str r3, [sp, #0]
8007d36: 6d7b ldr r3, [r7, #84] @ 0x54
8007d38: 2200 movs r2, #0
8007d3a: f44f 1100 mov.w r1, #2097152 @ 0x200000
8007d3e: 6878 ldr r0, [r7, #4]
8007d40: f000 f88c bl 8007e5c <UART_WaitOnFlagUntilTimeout>
8007d44: 4603 mov r3, r0
8007d46: 2b00 cmp r3, #0
8007d48: d021 beq.n 8007d8e <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
8007d4a: 687b ldr r3, [r7, #4]
8007d4c: 681b ldr r3, [r3, #0]
8007d4e: 63bb str r3, [r7, #56] @ 0x38
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007d50: 6bbb ldr r3, [r7, #56] @ 0x38
8007d52: e853 3f00 ldrex r3, [r3]
8007d56: 637b str r3, [r7, #52] @ 0x34
return(result);
8007d58: 6b7b ldr r3, [r7, #52] @ 0x34
8007d5a: f023 0380 bic.w r3, r3, #128 @ 0x80
8007d5e: 653b str r3, [r7, #80] @ 0x50
8007d60: 687b ldr r3, [r7, #4]
8007d62: 681b ldr r3, [r3, #0]
8007d64: 461a mov r2, r3
8007d66: 6d3b ldr r3, [r7, #80] @ 0x50
8007d68: 647b str r3, [r7, #68] @ 0x44
8007d6a: 643a str r2, [r7, #64] @ 0x40
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007d6c: 6c39 ldr r1, [r7, #64] @ 0x40
8007d6e: 6c7a ldr r2, [r7, #68] @ 0x44
8007d70: e841 2300 strex r3, r2, [r1]
8007d74: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8007d76: 6bfb ldr r3, [r7, #60] @ 0x3c
8007d78: 2b00 cmp r3, #0
8007d7a: d1e6 bne.n 8007d4a <UART_CheckIdleState+0x3e>
#endif /* USART_CR1_FIFOEN */
huart->gState = HAL_UART_STATE_READY;
8007d7c: 687b ldr r3, [r7, #4]
8007d7e: 2220 movs r2, #32
8007d80: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
8007d82: 687b ldr r3, [r7, #4]
8007d84: 2200 movs r2, #0
8007d86: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8007d8a: 2303 movs r3, #3
8007d8c: e062 b.n 8007e54 <UART_CheckIdleState+0x148>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8007d8e: 687b ldr r3, [r7, #4]
8007d90: 681b ldr r3, [r3, #0]
8007d92: 681b ldr r3, [r3, #0]
8007d94: f003 0304 and.w r3, r3, #4
8007d98: 2b04 cmp r3, #4
8007d9a: d149 bne.n 8007e30 <UART_CheckIdleState+0x124>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8007d9c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8007da0: 9300 str r3, [sp, #0]
8007da2: 6d7b ldr r3, [r7, #84] @ 0x54
8007da4: 2200 movs r2, #0
8007da6: f44f 0180 mov.w r1, #4194304 @ 0x400000
8007daa: 6878 ldr r0, [r7, #4]
8007dac: f000 f856 bl 8007e5c <UART_WaitOnFlagUntilTimeout>
8007db0: 4603 mov r3, r0
8007db2: 2b00 cmp r3, #0
8007db4: d03c beq.n 8007e30 <UART_CheckIdleState+0x124>
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8007db6: 687b ldr r3, [r7, #4]
8007db8: 681b ldr r3, [r3, #0]
8007dba: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007dbc: 6a7b ldr r3, [r7, #36] @ 0x24
8007dbe: e853 3f00 ldrex r3, [r3]
8007dc2: 623b str r3, [r7, #32]
return(result);
8007dc4: 6a3b ldr r3, [r7, #32]
8007dc6: f423 7390 bic.w r3, r3, #288 @ 0x120
8007dca: 64fb str r3, [r7, #76] @ 0x4c
8007dcc: 687b ldr r3, [r7, #4]
8007dce: 681b ldr r3, [r3, #0]
8007dd0: 461a mov r2, r3
8007dd2: 6cfb ldr r3, [r7, #76] @ 0x4c
8007dd4: 633b str r3, [r7, #48] @ 0x30
8007dd6: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007dd8: 6af9 ldr r1, [r7, #44] @ 0x2c
8007dda: 6b3a ldr r2, [r7, #48] @ 0x30
8007ddc: e841 2300 strex r3, r2, [r1]
8007de0: 62bb str r3, [r7, #40] @ 0x28
return(result);
8007de2: 6abb ldr r3, [r7, #40] @ 0x28
8007de4: 2b00 cmp r3, #0
8007de6: d1e6 bne.n 8007db6 <UART_CheckIdleState+0xaa>
#endif /* USART_CR1_FIFOEN */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8007de8: 687b ldr r3, [r7, #4]
8007dea: 681b ldr r3, [r3, #0]
8007dec: 3308 adds r3, #8
8007dee: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007df0: 693b ldr r3, [r7, #16]
8007df2: e853 3f00 ldrex r3, [r3]
8007df6: 60fb str r3, [r7, #12]
return(result);
8007df8: 68fb ldr r3, [r7, #12]
8007dfa: f023 0301 bic.w r3, r3, #1
8007dfe: 64bb str r3, [r7, #72] @ 0x48
8007e00: 687b ldr r3, [r7, #4]
8007e02: 681b ldr r3, [r3, #0]
8007e04: 3308 adds r3, #8
8007e06: 6cba ldr r2, [r7, #72] @ 0x48
8007e08: 61fa str r2, [r7, #28]
8007e0a: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007e0c: 69b9 ldr r1, [r7, #24]
8007e0e: 69fa ldr r2, [r7, #28]
8007e10: e841 2300 strex r3, r2, [r1]
8007e14: 617b str r3, [r7, #20]
return(result);
8007e16: 697b ldr r3, [r7, #20]
8007e18: 2b00 cmp r3, #0
8007e1a: d1e5 bne.n 8007de8 <UART_CheckIdleState+0xdc>
huart->RxState = HAL_UART_STATE_READY;
8007e1c: 687b ldr r3, [r7, #4]
8007e1e: 2220 movs r2, #32
8007e20: f8c3 2080 str.w r2, [r3, #128] @ 0x80
__HAL_UNLOCK(huart);
8007e24: 687b ldr r3, [r7, #4]
8007e26: 2200 movs r2, #0
8007e28: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8007e2c: 2303 movs r3, #3
8007e2e: e011 b.n 8007e54 <UART_CheckIdleState+0x148>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8007e30: 687b ldr r3, [r7, #4]
8007e32: 2220 movs r2, #32
8007e34: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
8007e36: 687b ldr r3, [r7, #4]
8007e38: 2220 movs r2, #32
8007e3a: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007e3e: 687b ldr r3, [r7, #4]
8007e40: 2200 movs r2, #0
8007e42: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007e44: 687b ldr r3, [r7, #4]
8007e46: 2200 movs r2, #0
8007e48: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
8007e4a: 687b ldr r3, [r7, #4]
8007e4c: 2200 movs r2, #0
8007e4e: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
8007e52: 2300 movs r3, #0
}
8007e54: 4618 mov r0, r3
8007e56: 3758 adds r7, #88 @ 0x58
8007e58: 46bd mov sp, r7
8007e5a: bd80 pop {r7, pc}
08007e5c <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8007e5c: b580 push {r7, lr}
8007e5e: b084 sub sp, #16
8007e60: af00 add r7, sp, #0
8007e62: 60f8 str r0, [r7, #12]
8007e64: 60b9 str r1, [r7, #8]
8007e66: 603b str r3, [r7, #0]
8007e68: 4613 mov r3, r2
8007e6a: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8007e6c: e04f b.n 8007f0e <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007e6e: 69bb ldr r3, [r7, #24]
8007e70: f1b3 3fff cmp.w r3, #4294967295
8007e74: d04b beq.n 8007f0e <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007e76: f7fa f94d bl 8002114 <HAL_GetTick>
8007e7a: 4602 mov r2, r0
8007e7c: 683b ldr r3, [r7, #0]
8007e7e: 1ad3 subs r3, r2, r3
8007e80: 69ba ldr r2, [r7, #24]
8007e82: 429a cmp r2, r3
8007e84: d302 bcc.n 8007e8c <UART_WaitOnFlagUntilTimeout+0x30>
8007e86: 69bb ldr r3, [r7, #24]
8007e88: 2b00 cmp r3, #0
8007e8a: d101 bne.n 8007e90 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8007e8c: 2303 movs r3, #3
8007e8e: e04e b.n 8007f2e <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8007e90: 68fb ldr r3, [r7, #12]
8007e92: 681b ldr r3, [r3, #0]
8007e94: 681b ldr r3, [r3, #0]
8007e96: f003 0304 and.w r3, r3, #4
8007e9a: 2b00 cmp r3, #0
8007e9c: d037 beq.n 8007f0e <UART_WaitOnFlagUntilTimeout+0xb2>
8007e9e: 68bb ldr r3, [r7, #8]
8007ea0: 2b80 cmp r3, #128 @ 0x80
8007ea2: d034 beq.n 8007f0e <UART_WaitOnFlagUntilTimeout+0xb2>
8007ea4: 68bb ldr r3, [r7, #8]
8007ea6: 2b40 cmp r3, #64 @ 0x40
8007ea8: d031 beq.n 8007f0e <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8007eaa: 68fb ldr r3, [r7, #12]
8007eac: 681b ldr r3, [r3, #0]
8007eae: 69db ldr r3, [r3, #28]
8007eb0: f003 0308 and.w r3, r3, #8
8007eb4: 2b08 cmp r3, #8
8007eb6: d110 bne.n 8007eda <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8007eb8: 68fb ldr r3, [r7, #12]
8007eba: 681b ldr r3, [r3, #0]
8007ebc: 2208 movs r2, #8
8007ebe: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8007ec0: 68f8 ldr r0, [r7, #12]
8007ec2: f000 f838 bl 8007f36 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8007ec6: 68fb ldr r3, [r7, #12]
8007ec8: 2208 movs r2, #8
8007eca: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8007ece: 68fb ldr r3, [r7, #12]
8007ed0: 2200 movs r2, #0
8007ed2: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
8007ed6: 2301 movs r3, #1
8007ed8: e029 b.n 8007f2e <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8007eda: 68fb ldr r3, [r7, #12]
8007edc: 681b ldr r3, [r3, #0]
8007ede: 69db ldr r3, [r3, #28]
8007ee0: f403 6300 and.w r3, r3, #2048 @ 0x800
8007ee4: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8007ee8: d111 bne.n 8007f0e <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8007eea: 68fb ldr r3, [r7, #12]
8007eec: 681b ldr r3, [r3, #0]
8007eee: f44f 6200 mov.w r2, #2048 @ 0x800
8007ef2: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8007ef4: 68f8 ldr r0, [r7, #12]
8007ef6: f000 f81e bl 8007f36 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8007efa: 68fb ldr r3, [r7, #12]
8007efc: 2220 movs r2, #32
8007efe: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8007f02: 68fb ldr r3, [r7, #12]
8007f04: 2200 movs r2, #0
8007f06: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
8007f0a: 2303 movs r3, #3
8007f0c: e00f b.n 8007f2e <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8007f0e: 68fb ldr r3, [r7, #12]
8007f10: 681b ldr r3, [r3, #0]
8007f12: 69da ldr r2, [r3, #28]
8007f14: 68bb ldr r3, [r7, #8]
8007f16: 4013 ands r3, r2
8007f18: 68ba ldr r2, [r7, #8]
8007f1a: 429a cmp r2, r3
8007f1c: bf0c ite eq
8007f1e: 2301 moveq r3, #1
8007f20: 2300 movne r3, #0
8007f22: b2db uxtb r3, r3
8007f24: 461a mov r2, r3
8007f26: 79fb ldrb r3, [r7, #7]
8007f28: 429a cmp r2, r3
8007f2a: d0a0 beq.n 8007e6e <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8007f2c: 2300 movs r3, #0
}
8007f2e: 4618 mov r0, r3
8007f30: 3710 adds r7, #16
8007f32: 46bd mov sp, r7
8007f34: bd80 pop {r7, pc}
08007f36 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8007f36: b480 push {r7}
8007f38: b095 sub sp, #84 @ 0x54
8007f3a: af00 add r7, sp, #0
8007f3c: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8007f3e: 687b ldr r3, [r7, #4]
8007f40: 681b ldr r3, [r3, #0]
8007f42: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007f44: 6b7b ldr r3, [r7, #52] @ 0x34
8007f46: e853 3f00 ldrex r3, [r3]
8007f4a: 633b str r3, [r7, #48] @ 0x30
return(result);
8007f4c: 6b3b ldr r3, [r7, #48] @ 0x30
8007f4e: f423 7390 bic.w r3, r3, #288 @ 0x120
8007f52: 64fb str r3, [r7, #76] @ 0x4c
8007f54: 687b ldr r3, [r7, #4]
8007f56: 681b ldr r3, [r3, #0]
8007f58: 461a mov r2, r3
8007f5a: 6cfb ldr r3, [r7, #76] @ 0x4c
8007f5c: 643b str r3, [r7, #64] @ 0x40
8007f5e: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007f60: 6bf9 ldr r1, [r7, #60] @ 0x3c
8007f62: 6c3a ldr r2, [r7, #64] @ 0x40
8007f64: e841 2300 strex r3, r2, [r1]
8007f68: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007f6a: 6bbb ldr r3, [r7, #56] @ 0x38
8007f6c: 2b00 cmp r3, #0
8007f6e: d1e6 bne.n 8007f3e <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8007f70: 687b ldr r3, [r7, #4]
8007f72: 681b ldr r3, [r3, #0]
8007f74: 3308 adds r3, #8
8007f76: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007f78: 6a3b ldr r3, [r7, #32]
8007f7a: e853 3f00 ldrex r3, [r3]
8007f7e: 61fb str r3, [r7, #28]
return(result);
8007f80: 69fb ldr r3, [r7, #28]
8007f82: f023 0301 bic.w r3, r3, #1
8007f86: 64bb str r3, [r7, #72] @ 0x48
8007f88: 687b ldr r3, [r7, #4]
8007f8a: 681b ldr r3, [r3, #0]
8007f8c: 3308 adds r3, #8
8007f8e: 6cba ldr r2, [r7, #72] @ 0x48
8007f90: 62fa str r2, [r7, #44] @ 0x2c
8007f92: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007f94: 6ab9 ldr r1, [r7, #40] @ 0x28
8007f96: 6afa ldr r2, [r7, #44] @ 0x2c
8007f98: e841 2300 strex r3, r2, [r1]
8007f9c: 627b str r3, [r7, #36] @ 0x24
return(result);
8007f9e: 6a7b ldr r3, [r7, #36] @ 0x24
8007fa0: 2b00 cmp r3, #0
8007fa2: d1e5 bne.n 8007f70 <UART_EndRxTransfer+0x3a>
#endif /* USART_CR1_FIFOEN */
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007fa4: 687b ldr r3, [r7, #4]
8007fa6: 6e1b ldr r3, [r3, #96] @ 0x60
8007fa8: 2b01 cmp r3, #1
8007faa: d118 bne.n 8007fde <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007fac: 687b ldr r3, [r7, #4]
8007fae: 681b ldr r3, [r3, #0]
8007fb0: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007fb2: 68fb ldr r3, [r7, #12]
8007fb4: e853 3f00 ldrex r3, [r3]
8007fb8: 60bb str r3, [r7, #8]
return(result);
8007fba: 68bb ldr r3, [r7, #8]
8007fbc: f023 0310 bic.w r3, r3, #16
8007fc0: 647b str r3, [r7, #68] @ 0x44
8007fc2: 687b ldr r3, [r7, #4]
8007fc4: 681b ldr r3, [r3, #0]
8007fc6: 461a mov r2, r3
8007fc8: 6c7b ldr r3, [r7, #68] @ 0x44
8007fca: 61bb str r3, [r7, #24]
8007fcc: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007fce: 6979 ldr r1, [r7, #20]
8007fd0: 69ba ldr r2, [r7, #24]
8007fd2: e841 2300 strex r3, r2, [r1]
8007fd6: 613b str r3, [r7, #16]
return(result);
8007fd8: 693b ldr r3, [r7, #16]
8007fda: 2b00 cmp r3, #0
8007fdc: d1e6 bne.n 8007fac <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007fde: 687b ldr r3, [r7, #4]
8007fe0: 2220 movs r2, #32
8007fe2: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007fe6: 687b ldr r3, [r7, #4]
8007fe8: 2200 movs r2, #0
8007fea: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8007fec: 687b ldr r3, [r7, #4]
8007fee: 2200 movs r2, #0
8007ff0: 669a str r2, [r3, #104] @ 0x68
}
8007ff2: bf00 nop
8007ff4: 3754 adds r7, #84 @ 0x54
8007ff6: 46bd mov sp, r7
8007ff8: f85d 7b04 ldr.w r7, [sp], #4
8007ffc: 4770 bx lr
08007ffe <USB_CoreInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
8007ffe: b084 sub sp, #16
8008000: b580 push {r7, lr}
8008002: b084 sub sp, #16
8008004: af00 add r7, sp, #0
8008006: 6078 str r0, [r7, #4]
8008008: f107 001c add.w r0, r7, #28
800800c: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret;
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
8008010: 687b ldr r3, [r7, #4]
8008012: 68db ldr r3, [r3, #12]
8008014: f043 0240 orr.w r2, r3, #64 @ 0x40
8008018: 687b ldr r3, [r7, #4]
800801a: 60da str r2, [r3, #12]
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
800801c: 6878 ldr r0, [r7, #4]
800801e: f001 fa25 bl 800946c <USB_CoreReset>
8008022: 4603 mov r3, r0
8008024: 73fb strb r3, [r7, #15]
if (cfg.battery_charging_enable == 0U)
8008026: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
800802a: 2b00 cmp r3, #0
800802c: d106 bne.n 800803c <USB_CoreInit+0x3e>
{
/* Activate the USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
800802e: 687b ldr r3, [r7, #4]
8008030: 6b9b ldr r3, [r3, #56] @ 0x38
8008032: f443 3280 orr.w r2, r3, #65536 @ 0x10000
8008036: 687b ldr r3, [r7, #4]
8008038: 639a str r2, [r3, #56] @ 0x38
800803a: e005 b.n 8008048 <USB_CoreInit+0x4a>
}
else
{
/* Deactivate the USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
800803c: 687b ldr r3, [r7, #4]
800803e: 6b9b ldr r3, [r3, #56] @ 0x38
8008040: f423 3280 bic.w r2, r3, #65536 @ 0x10000
8008044: 687b ldr r3, [r7, #4]
8008046: 639a str r2, [r3, #56] @ 0x38
}
return ret;
8008048: 7bfb ldrb r3, [r7, #15]
}
800804a: 4618 mov r0, r3
800804c: 3710 adds r7, #16
800804e: 46bd mov sp, r7
8008050: e8bd 4080 ldmia.w sp!, {r7, lr}
8008054: b004 add sp, #16
8008056: 4770 bx lr
08008058 <USB_SetTurnaroundTime>:
* @param hclk: AHB clock frequency
* @retval USB turnaround time In PHY Clocks number
*/
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
uint32_t hclk, uint8_t speed)
{
8008058: b480 push {r7}
800805a: b087 sub sp, #28
800805c: af00 add r7, sp, #0
800805e: 60f8 str r0, [r7, #12]
8008060: 60b9 str r1, [r7, #8]
8008062: 4613 mov r3, r2
8008064: 71fb strb r3, [r7, #7]
/* The USBTRD is configured according to the tables below, depending on AHB frequency
used by application. In the low AHB frequency range it is used to stretch enough the USB response
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
latency to the Data FIFO */
if (speed == USBD_FS_SPEED)
8008066: 79fb ldrb r3, [r7, #7]
8008068: 2b02 cmp r3, #2
800806a: d165 bne.n 8008138 <USB_SetTurnaroundTime+0xe0>
{
if ((hclk >= 14200000U) && (hclk < 15000000U))
800806c: 68bb ldr r3, [r7, #8]
800806e: 4a3e ldr r2, [pc, #248] @ (8008168 <USB_SetTurnaroundTime+0x110>)
8008070: 4293 cmp r3, r2
8008072: d906 bls.n 8008082 <USB_SetTurnaroundTime+0x2a>
8008074: 68bb ldr r3, [r7, #8]
8008076: 4a3d ldr r2, [pc, #244] @ (800816c <USB_SetTurnaroundTime+0x114>)
8008078: 4293 cmp r3, r2
800807a: d202 bcs.n 8008082 <USB_SetTurnaroundTime+0x2a>
{
/* hclk Clock Range between 14.2-15 MHz */
UsbTrd = 0xFU;
800807c: 230f movs r3, #15
800807e: 617b str r3, [r7, #20]
8008080: e05c b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 15000000U) && (hclk < 16000000U))
8008082: 68bb ldr r3, [r7, #8]
8008084: 4a39 ldr r2, [pc, #228] @ (800816c <USB_SetTurnaroundTime+0x114>)
8008086: 4293 cmp r3, r2
8008088: d306 bcc.n 8008098 <USB_SetTurnaroundTime+0x40>
800808a: 68bb ldr r3, [r7, #8]
800808c: 4a38 ldr r2, [pc, #224] @ (8008170 <USB_SetTurnaroundTime+0x118>)
800808e: 4293 cmp r3, r2
8008090: d202 bcs.n 8008098 <USB_SetTurnaroundTime+0x40>
{
/* hclk Clock Range between 15-16 MHz */
UsbTrd = 0xEU;
8008092: 230e movs r3, #14
8008094: 617b str r3, [r7, #20]
8008096: e051 b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 16000000U) && (hclk < 17200000U))
8008098: 68bb ldr r3, [r7, #8]
800809a: 4a35 ldr r2, [pc, #212] @ (8008170 <USB_SetTurnaroundTime+0x118>)
800809c: 4293 cmp r3, r2
800809e: d306 bcc.n 80080ae <USB_SetTurnaroundTime+0x56>
80080a0: 68bb ldr r3, [r7, #8]
80080a2: 4a34 ldr r2, [pc, #208] @ (8008174 <USB_SetTurnaroundTime+0x11c>)
80080a4: 4293 cmp r3, r2
80080a6: d202 bcs.n 80080ae <USB_SetTurnaroundTime+0x56>
{
/* hclk Clock Range between 16-17.2 MHz */
UsbTrd = 0xDU;
80080a8: 230d movs r3, #13
80080aa: 617b str r3, [r7, #20]
80080ac: e046 b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 17200000U) && (hclk < 18500000U))
80080ae: 68bb ldr r3, [r7, #8]
80080b0: 4a30 ldr r2, [pc, #192] @ (8008174 <USB_SetTurnaroundTime+0x11c>)
80080b2: 4293 cmp r3, r2
80080b4: d306 bcc.n 80080c4 <USB_SetTurnaroundTime+0x6c>
80080b6: 68bb ldr r3, [r7, #8]
80080b8: 4a2f ldr r2, [pc, #188] @ (8008178 <USB_SetTurnaroundTime+0x120>)
80080ba: 4293 cmp r3, r2
80080bc: d802 bhi.n 80080c4 <USB_SetTurnaroundTime+0x6c>
{
/* hclk Clock Range between 17.2-18.5 MHz */
UsbTrd = 0xCU;
80080be: 230c movs r3, #12
80080c0: 617b str r3, [r7, #20]
80080c2: e03b b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 18500000U) && (hclk < 20000000U))
80080c4: 68bb ldr r3, [r7, #8]
80080c6: 4a2c ldr r2, [pc, #176] @ (8008178 <USB_SetTurnaroundTime+0x120>)
80080c8: 4293 cmp r3, r2
80080ca: d906 bls.n 80080da <USB_SetTurnaroundTime+0x82>
80080cc: 68bb ldr r3, [r7, #8]
80080ce: 4a2b ldr r2, [pc, #172] @ (800817c <USB_SetTurnaroundTime+0x124>)
80080d0: 4293 cmp r3, r2
80080d2: d802 bhi.n 80080da <USB_SetTurnaroundTime+0x82>
{
/* hclk Clock Range between 18.5-20 MHz */
UsbTrd = 0xBU;
80080d4: 230b movs r3, #11
80080d6: 617b str r3, [r7, #20]
80080d8: e030 b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 20000000U) && (hclk < 21800000U))
80080da: 68bb ldr r3, [r7, #8]
80080dc: 4a27 ldr r2, [pc, #156] @ (800817c <USB_SetTurnaroundTime+0x124>)
80080de: 4293 cmp r3, r2
80080e0: d906 bls.n 80080f0 <USB_SetTurnaroundTime+0x98>
80080e2: 68bb ldr r3, [r7, #8]
80080e4: 4a26 ldr r2, [pc, #152] @ (8008180 <USB_SetTurnaroundTime+0x128>)
80080e6: 4293 cmp r3, r2
80080e8: d802 bhi.n 80080f0 <USB_SetTurnaroundTime+0x98>
{
/* hclk Clock Range between 20-21.8 MHz */
UsbTrd = 0xAU;
80080ea: 230a movs r3, #10
80080ec: 617b str r3, [r7, #20]
80080ee: e025 b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 21800000U) && (hclk < 24000000U))
80080f0: 68bb ldr r3, [r7, #8]
80080f2: 4a23 ldr r2, [pc, #140] @ (8008180 <USB_SetTurnaroundTime+0x128>)
80080f4: 4293 cmp r3, r2
80080f6: d906 bls.n 8008106 <USB_SetTurnaroundTime+0xae>
80080f8: 68bb ldr r3, [r7, #8]
80080fa: 4a22 ldr r2, [pc, #136] @ (8008184 <USB_SetTurnaroundTime+0x12c>)
80080fc: 4293 cmp r3, r2
80080fe: d202 bcs.n 8008106 <USB_SetTurnaroundTime+0xae>
{
/* hclk Clock Range between 21.8-24 MHz */
UsbTrd = 0x9U;
8008100: 2309 movs r3, #9
8008102: 617b str r3, [r7, #20]
8008104: e01a b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 24000000U) && (hclk < 27700000U))
8008106: 68bb ldr r3, [r7, #8]
8008108: 4a1e ldr r2, [pc, #120] @ (8008184 <USB_SetTurnaroundTime+0x12c>)
800810a: 4293 cmp r3, r2
800810c: d306 bcc.n 800811c <USB_SetTurnaroundTime+0xc4>
800810e: 68bb ldr r3, [r7, #8]
8008110: 4a1d ldr r2, [pc, #116] @ (8008188 <USB_SetTurnaroundTime+0x130>)
8008112: 4293 cmp r3, r2
8008114: d802 bhi.n 800811c <USB_SetTurnaroundTime+0xc4>
{
/* hclk Clock Range between 24-27.7 MHz */
UsbTrd = 0x8U;
8008116: 2308 movs r3, #8
8008118: 617b str r3, [r7, #20]
800811a: e00f b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 27700000U) && (hclk < 32000000U))
800811c: 68bb ldr r3, [r7, #8]
800811e: 4a1a ldr r2, [pc, #104] @ (8008188 <USB_SetTurnaroundTime+0x130>)
8008120: 4293 cmp r3, r2
8008122: d906 bls.n 8008132 <USB_SetTurnaroundTime+0xda>
8008124: 68bb ldr r3, [r7, #8]
8008126: 4a19 ldr r2, [pc, #100] @ (800818c <USB_SetTurnaroundTime+0x134>)
8008128: 4293 cmp r3, r2
800812a: d202 bcs.n 8008132 <USB_SetTurnaroundTime+0xda>
{
/* hclk Clock Range between 27.7-32 MHz */
UsbTrd = 0x7U;
800812c: 2307 movs r3, #7
800812e: 617b str r3, [r7, #20]
8008130: e004 b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
else /* if(hclk >= 32000000) */
{
/* hclk Clock Range between 32-200 MHz */
UsbTrd = 0x6U;
8008132: 2306 movs r3, #6
8008134: 617b str r3, [r7, #20]
8008136: e001 b.n 800813c <USB_SetTurnaroundTime+0xe4>
}
}
else
{
UsbTrd = USBD_DEFAULT_TRDT_VALUE;
8008138: 2309 movs r3, #9
800813a: 617b str r3, [r7, #20]
}
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
800813c: 68fb ldr r3, [r7, #12]
800813e: 68db ldr r3, [r3, #12]
8008140: f423 5270 bic.w r2, r3, #15360 @ 0x3c00
8008144: 68fb ldr r3, [r7, #12]
8008146: 60da str r2, [r3, #12]
USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
8008148: 68fb ldr r3, [r7, #12]
800814a: 68da ldr r2, [r3, #12]
800814c: 697b ldr r3, [r7, #20]
800814e: 029b lsls r3, r3, #10
8008150: f403 5370 and.w r3, r3, #15360 @ 0x3c00
8008154: 431a orrs r2, r3
8008156: 68fb ldr r3, [r7, #12]
8008158: 60da str r2, [r3, #12]
return HAL_OK;
800815a: 2300 movs r3, #0
}
800815c: 4618 mov r0, r3
800815e: 371c adds r7, #28
8008160: 46bd mov sp, r7
8008162: f85d 7b04 ldr.w r7, [sp], #4
8008166: 4770 bx lr
8008168: 00d8acbf .word 0x00d8acbf
800816c: 00e4e1c0 .word 0x00e4e1c0
8008170: 00f42400 .word 0x00f42400
8008174: 01067380 .word 0x01067380
8008178: 011a499f .word 0x011a499f
800817c: 01312cff .word 0x01312cff
8008180: 014ca43f .word 0x014ca43f
8008184: 016e3600 .word 0x016e3600
8008188: 01a6ab1f .word 0x01a6ab1f
800818c: 01e84800 .word 0x01e84800
08008190 <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
8008190: b480 push {r7}
8008192: b083 sub sp, #12
8008194: af00 add r7, sp, #0
8008196: 6078 str r0, [r7, #4]
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
8008198: 687b ldr r3, [r7, #4]
800819a: 689b ldr r3, [r3, #8]
800819c: f043 0201 orr.w r2, r3, #1
80081a0: 687b ldr r3, [r7, #4]
80081a2: 609a str r2, [r3, #8]
return HAL_OK;
80081a4: 2300 movs r3, #0
}
80081a6: 4618 mov r0, r3
80081a8: 370c adds r7, #12
80081aa: 46bd mov sp, r7
80081ac: f85d 7b04 ldr.w r7, [sp], #4
80081b0: 4770 bx lr
080081b2 <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
80081b2: b480 push {r7}
80081b4: b083 sub sp, #12
80081b6: af00 add r7, sp, #0
80081b8: 6078 str r0, [r7, #4]
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
80081ba: 687b ldr r3, [r7, #4]
80081bc: 689b ldr r3, [r3, #8]
80081be: f023 0201 bic.w r2, r3, #1
80081c2: 687b ldr r3, [r7, #4]
80081c4: 609a str r2, [r3, #8]
return HAL_OK;
80081c6: 2300 movs r3, #0
}
80081c8: 4618 mov r0, r3
80081ca: 370c adds r7, #12
80081cc: 46bd mov sp, r7
80081ce: f85d 7b04 ldr.w r7, [sp], #4
80081d2: 4770 bx lr
080081d4 <USB_SetCurrentMode>:
* @arg USB_DEVICE_MODE Peripheral mode
* @arg USB_HOST_MODE Host mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
{
80081d4: b580 push {r7, lr}
80081d6: b084 sub sp, #16
80081d8: af00 add r7, sp, #0
80081da: 6078 str r0, [r7, #4]
80081dc: 460b mov r3, r1
80081de: 70fb strb r3, [r7, #3]
uint32_t ms = 0U;
80081e0: 2300 movs r3, #0
80081e2: 60fb str r3, [r7, #12]
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
80081e4: 687b ldr r3, [r7, #4]
80081e6: 68db ldr r3, [r3, #12]
80081e8: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
80081ec: 687b ldr r3, [r7, #4]
80081ee: 60da str r2, [r3, #12]
if (mode == USB_HOST_MODE)
80081f0: 78fb ldrb r3, [r7, #3]
80081f2: 2b01 cmp r3, #1
80081f4: d115 bne.n 8008222 <USB_SetCurrentMode+0x4e>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
80081f6: 687b ldr r3, [r7, #4]
80081f8: 68db ldr r3, [r3, #12]
80081fa: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
80081fe: 687b ldr r3, [r7, #4]
8008200: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
8008202: 200a movs r0, #10
8008204: f7f9 ff92 bl 800212c <HAL_Delay>
ms += 10U;
8008208: 68fb ldr r3, [r7, #12]
800820a: 330a adds r3, #10
800820c: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
800820e: 6878 ldr r0, [r7, #4]
8008210: f001 f8b3 bl 800937a <USB_GetMode>
8008214: 4603 mov r3, r0
8008216: 2b01 cmp r3, #1
8008218: d01e beq.n 8008258 <USB_SetCurrentMode+0x84>
800821a: 68fb ldr r3, [r7, #12]
800821c: 2bc7 cmp r3, #199 @ 0xc7
800821e: d9f0 bls.n 8008202 <USB_SetCurrentMode+0x2e>
8008220: e01a b.n 8008258 <USB_SetCurrentMode+0x84>
}
else if (mode == USB_DEVICE_MODE)
8008222: 78fb ldrb r3, [r7, #3]
8008224: 2b00 cmp r3, #0
8008226: d115 bne.n 8008254 <USB_SetCurrentMode+0x80>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
8008228: 687b ldr r3, [r7, #4]
800822a: 68db ldr r3, [r3, #12]
800822c: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
8008230: 687b ldr r3, [r7, #4]
8008232: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
8008234: 200a movs r0, #10
8008236: f7f9 ff79 bl 800212c <HAL_Delay>
ms += 10U;
800823a: 68fb ldr r3, [r7, #12]
800823c: 330a adds r3, #10
800823e: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
8008240: 6878 ldr r0, [r7, #4]
8008242: f001 f89a bl 800937a <USB_GetMode>
8008246: 4603 mov r3, r0
8008248: 2b00 cmp r3, #0
800824a: d005 beq.n 8008258 <USB_SetCurrentMode+0x84>
800824c: 68fb ldr r3, [r7, #12]
800824e: 2bc7 cmp r3, #199 @ 0xc7
8008250: d9f0 bls.n 8008234 <USB_SetCurrentMode+0x60>
8008252: e001 b.n 8008258 <USB_SetCurrentMode+0x84>
}
else
{
return HAL_ERROR;
8008254: 2301 movs r3, #1
8008256: e005 b.n 8008264 <USB_SetCurrentMode+0x90>
}
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
8008258: 68fb ldr r3, [r7, #12]
800825a: 2bc8 cmp r3, #200 @ 0xc8
800825c: d101 bne.n 8008262 <USB_SetCurrentMode+0x8e>
{
return HAL_ERROR;
800825e: 2301 movs r3, #1
8008260: e000 b.n 8008264 <USB_SetCurrentMode+0x90>
}
return HAL_OK;
8008262: 2300 movs r3, #0
}
8008264: 4618 mov r0, r3
8008266: 3710 adds r7, #16
8008268: 46bd mov sp, r7
800826a: bd80 pop {r7, pc}
0800826c <USB_DevInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
800826c: b084 sub sp, #16
800826e: b580 push {r7, lr}
8008270: b086 sub sp, #24
8008272: af00 add r7, sp, #0
8008274: 6078 str r0, [r7, #4]
8008276: f107 0024 add.w r0, r7, #36 @ 0x24
800827a: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret = HAL_OK;
800827e: 2300 movs r3, #0
8008280: 75fb strb r3, [r7, #23]
uint32_t USBx_BASE = (uint32_t)USBx;
8008282: 687b ldr r3, [r7, #4]
8008284: 60fb str r3, [r7, #12]
uint32_t i;
for (i = 0U; i < 15U; i++)
8008286: 2300 movs r3, #0
8008288: 613b str r3, [r7, #16]
800828a: e009 b.n 80082a0 <USB_DevInit+0x34>
{
USBx->DIEPTXF[i] = 0U;
800828c: 687a ldr r2, [r7, #4]
800828e: 693b ldr r3, [r7, #16]
8008290: 3340 adds r3, #64 @ 0x40
8008292: 009b lsls r3, r3, #2
8008294: 4413 add r3, r2
8008296: 2200 movs r2, #0
8008298: 605a str r2, [r3, #4]
for (i = 0U; i < 15U; i++)
800829a: 693b ldr r3, [r7, #16]
800829c: 3301 adds r3, #1
800829e: 613b str r3, [r7, #16]
80082a0: 693b ldr r3, [r7, #16]
80082a2: 2b0e cmp r3, #14
80082a4: d9f2 bls.n 800828c <USB_DevInit+0x20>
}
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
80082a6: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
80082aa: 2b00 cmp r3, #0
80082ac: d11c bne.n 80082e8 <USB_DevInit+0x7c>
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
80082ae: 68fb ldr r3, [r7, #12]
80082b0: f503 6300 add.w r3, r3, #2048 @ 0x800
80082b4: 685b ldr r3, [r3, #4]
80082b6: 68fa ldr r2, [r7, #12]
80082b8: f502 6200 add.w r2, r2, #2048 @ 0x800
80082bc: f043 0302 orr.w r3, r3, #2
80082c0: 6053 str r3, [r2, #4]
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
80082c2: 687b ldr r3, [r7, #4]
80082c4: 6b9b ldr r3, [r3, #56] @ 0x38
80082c6: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
80082ca: 687b ldr r3, [r7, #4]
80082cc: 639a str r2, [r3, #56] @ 0x38
/* B-peripheral session valid override enable */
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
80082ce: 687b ldr r3, [r7, #4]
80082d0: 681b ldr r3, [r3, #0]
80082d2: f043 0240 orr.w r2, r3, #64 @ 0x40
80082d6: 687b ldr r3, [r7, #4]
80082d8: 601a str r2, [r3, #0]
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
80082da: 687b ldr r3, [r7, #4]
80082dc: 681b ldr r3, [r3, #0]
80082de: f043 0280 orr.w r2, r3, #128 @ 0x80
80082e2: 687b ldr r3, [r7, #4]
80082e4: 601a str r2, [r3, #0]
80082e6: e005 b.n 80082f4 <USB_DevInit+0x88>
}
else
{
/* Enable HW VBUS sensing */
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
80082e8: 687b ldr r3, [r7, #4]
80082ea: 6b9b ldr r3, [r3, #56] @ 0x38
80082ec: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80082f0: 687b ldr r3, [r7, #4]
80082f2: 639a str r2, [r3, #56] @ 0x38
}
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
80082f4: 68fb ldr r3, [r7, #12]
80082f6: f503 6360 add.w r3, r3, #3584 @ 0xe00
80082fa: 461a mov r2, r3
80082fc: 2300 movs r3, #0
80082fe: 6013 str r3, [r2, #0]
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
8008300: 2103 movs r1, #3
8008302: 6878 ldr r0, [r7, #4]
8008304: f000 f95a bl 80085bc <USB_SetDevSpeed>
/* Flush the FIFOs */
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
8008308: 2110 movs r1, #16
800830a: 6878 ldr r0, [r7, #4]
800830c: f000 f8f6 bl 80084fc <USB_FlushTxFifo>
8008310: 4603 mov r3, r0
8008312: 2b00 cmp r3, #0
8008314: d001 beq.n 800831a <USB_DevInit+0xae>
{
ret = HAL_ERROR;
8008316: 2301 movs r3, #1
8008318: 75fb strb r3, [r7, #23]
}
if (USB_FlushRxFifo(USBx) != HAL_OK)
800831a: 6878 ldr r0, [r7, #4]
800831c: f000 f920 bl 8008560 <USB_FlushRxFifo>
8008320: 4603 mov r3, r0
8008322: 2b00 cmp r3, #0
8008324: d001 beq.n 800832a <USB_DevInit+0xbe>
{
ret = HAL_ERROR;
8008326: 2301 movs r3, #1
8008328: 75fb strb r3, [r7, #23]
}
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0U;
800832a: 68fb ldr r3, [r7, #12]
800832c: f503 6300 add.w r3, r3, #2048 @ 0x800
8008330: 461a mov r2, r3
8008332: 2300 movs r3, #0
8008334: 6113 str r3, [r2, #16]
USBx_DEVICE->DOEPMSK = 0U;
8008336: 68fb ldr r3, [r7, #12]
8008338: f503 6300 add.w r3, r3, #2048 @ 0x800
800833c: 461a mov r2, r3
800833e: 2300 movs r3, #0
8008340: 6153 str r3, [r2, #20]
USBx_DEVICE->DAINTMSK = 0U;
8008342: 68fb ldr r3, [r7, #12]
8008344: f503 6300 add.w r3, r3, #2048 @ 0x800
8008348: 461a mov r2, r3
800834a: 2300 movs r3, #0
800834c: 61d3 str r3, [r2, #28]
for (i = 0U; i < cfg.dev_endpoints; i++)
800834e: 2300 movs r3, #0
8008350: 613b str r3, [r7, #16]
8008352: e043 b.n 80083dc <USB_DevInit+0x170>
{
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
8008354: 693b ldr r3, [r7, #16]
8008356: 015a lsls r2, r3, #5
8008358: 68fb ldr r3, [r7, #12]
800835a: 4413 add r3, r2
800835c: f503 6310 add.w r3, r3, #2304 @ 0x900
8008360: 681b ldr r3, [r3, #0]
8008362: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8008366: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
800836a: d118 bne.n 800839e <USB_DevInit+0x132>
{
if (i == 0U)
800836c: 693b ldr r3, [r7, #16]
800836e: 2b00 cmp r3, #0
8008370: d10a bne.n 8008388 <USB_DevInit+0x11c>
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
8008372: 693b ldr r3, [r7, #16]
8008374: 015a lsls r2, r3, #5
8008376: 68fb ldr r3, [r7, #12]
8008378: 4413 add r3, r2
800837a: f503 6310 add.w r3, r3, #2304 @ 0x900
800837e: 461a mov r2, r3
8008380: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8008384: 6013 str r3, [r2, #0]
8008386: e013 b.n 80083b0 <USB_DevInit+0x144>
}
else
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
8008388: 693b ldr r3, [r7, #16]
800838a: 015a lsls r2, r3, #5
800838c: 68fb ldr r3, [r7, #12]
800838e: 4413 add r3, r2
8008390: f503 6310 add.w r3, r3, #2304 @ 0x900
8008394: 461a mov r2, r3
8008396: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
800839a: 6013 str r3, [r2, #0]
800839c: e008 b.n 80083b0 <USB_DevInit+0x144>
}
}
else
{
USBx_INEP(i)->DIEPCTL = 0U;
800839e: 693b ldr r3, [r7, #16]
80083a0: 015a lsls r2, r3, #5
80083a2: 68fb ldr r3, [r7, #12]
80083a4: 4413 add r3, r2
80083a6: f503 6310 add.w r3, r3, #2304 @ 0x900
80083aa: 461a mov r2, r3
80083ac: 2300 movs r3, #0
80083ae: 6013 str r3, [r2, #0]
}
USBx_INEP(i)->DIEPTSIZ = 0U;
80083b0: 693b ldr r3, [r7, #16]
80083b2: 015a lsls r2, r3, #5
80083b4: 68fb ldr r3, [r7, #12]
80083b6: 4413 add r3, r2
80083b8: f503 6310 add.w r3, r3, #2304 @ 0x900
80083bc: 461a mov r2, r3
80083be: 2300 movs r3, #0
80083c0: 6113 str r3, [r2, #16]
USBx_INEP(i)->DIEPINT = 0xFB7FU;
80083c2: 693b ldr r3, [r7, #16]
80083c4: 015a lsls r2, r3, #5
80083c6: 68fb ldr r3, [r7, #12]
80083c8: 4413 add r3, r2
80083ca: f503 6310 add.w r3, r3, #2304 @ 0x900
80083ce: 461a mov r2, r3
80083d0: f64f 337f movw r3, #64383 @ 0xfb7f
80083d4: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
80083d6: 693b ldr r3, [r7, #16]
80083d8: 3301 adds r3, #1
80083da: 613b str r3, [r7, #16]
80083dc: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
80083e0: 461a mov r2, r3
80083e2: 693b ldr r3, [r7, #16]
80083e4: 4293 cmp r3, r2
80083e6: d3b5 bcc.n 8008354 <USB_DevInit+0xe8>
}
for (i = 0U; i < cfg.dev_endpoints; i++)
80083e8: 2300 movs r3, #0
80083ea: 613b str r3, [r7, #16]
80083ec: e043 b.n 8008476 <USB_DevInit+0x20a>
{
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
80083ee: 693b ldr r3, [r7, #16]
80083f0: 015a lsls r2, r3, #5
80083f2: 68fb ldr r3, [r7, #12]
80083f4: 4413 add r3, r2
80083f6: f503 6330 add.w r3, r3, #2816 @ 0xb00
80083fa: 681b ldr r3, [r3, #0]
80083fc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8008400: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8008404: d118 bne.n 8008438 <USB_DevInit+0x1cc>
{
if (i == 0U)
8008406: 693b ldr r3, [r7, #16]
8008408: 2b00 cmp r3, #0
800840a: d10a bne.n 8008422 <USB_DevInit+0x1b6>
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
800840c: 693b ldr r3, [r7, #16]
800840e: 015a lsls r2, r3, #5
8008410: 68fb ldr r3, [r7, #12]
8008412: 4413 add r3, r2
8008414: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008418: 461a mov r2, r3
800841a: f04f 6300 mov.w r3, #134217728 @ 0x8000000
800841e: 6013 str r3, [r2, #0]
8008420: e013 b.n 800844a <USB_DevInit+0x1de>
}
else
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
8008422: 693b ldr r3, [r7, #16]
8008424: 015a lsls r2, r3, #5
8008426: 68fb ldr r3, [r7, #12]
8008428: 4413 add r3, r2
800842a: f503 6330 add.w r3, r3, #2816 @ 0xb00
800842e: 461a mov r2, r3
8008430: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
8008434: 6013 str r3, [r2, #0]
8008436: e008 b.n 800844a <USB_DevInit+0x1de>
}
}
else
{
USBx_OUTEP(i)->DOEPCTL = 0U;
8008438: 693b ldr r3, [r7, #16]
800843a: 015a lsls r2, r3, #5
800843c: 68fb ldr r3, [r7, #12]
800843e: 4413 add r3, r2
8008440: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008444: 461a mov r2, r3
8008446: 2300 movs r3, #0
8008448: 6013 str r3, [r2, #0]
}
USBx_OUTEP(i)->DOEPTSIZ = 0U;
800844a: 693b ldr r3, [r7, #16]
800844c: 015a lsls r2, r3, #5
800844e: 68fb ldr r3, [r7, #12]
8008450: 4413 add r3, r2
8008452: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008456: 461a mov r2, r3
8008458: 2300 movs r3, #0
800845a: 6113 str r3, [r2, #16]
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
800845c: 693b ldr r3, [r7, #16]
800845e: 015a lsls r2, r3, #5
8008460: 68fb ldr r3, [r7, #12]
8008462: 4413 add r3, r2
8008464: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008468: 461a mov r2, r3
800846a: f64f 337f movw r3, #64383 @ 0xfb7f
800846e: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
8008470: 693b ldr r3, [r7, #16]
8008472: 3301 adds r3, #1
8008474: 613b str r3, [r7, #16]
8008476: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
800847a: 461a mov r2, r3
800847c: 693b ldr r3, [r7, #16]
800847e: 4293 cmp r3, r2
8008480: d3b5 bcc.n 80083ee <USB_DevInit+0x182>
}
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
8008482: 68fb ldr r3, [r7, #12]
8008484: f503 6300 add.w r3, r3, #2048 @ 0x800
8008488: 691b ldr r3, [r3, #16]
800848a: 68fa ldr r2, [r7, #12]
800848c: f502 6200 add.w r2, r2, #2048 @ 0x800
8008490: f423 7380 bic.w r3, r3, #256 @ 0x100
8008494: 6113 str r3, [r2, #16]
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
8008496: 687b ldr r3, [r7, #4]
8008498: 2200 movs r2, #0
800849a: 619a str r2, [r3, #24]
/* Clear any pending interrupts */
USBx->GINTSTS = 0xBFFFFFFFU;
800849c: 687b ldr r3, [r7, #4]
800849e: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
80084a2: 615a str r2, [r3, #20]
/* Enable the common interrupts */
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
80084a4: 687b ldr r3, [r7, #4]
80084a6: 699b ldr r3, [r3, #24]
80084a8: f043 0210 orr.w r2, r3, #16
80084ac: 687b ldr r3, [r7, #4]
80084ae: 619a str r2, [r3, #24]
/* Enable interrupts matching to the Device mode ONLY */
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
80084b0: 687b ldr r3, [r7, #4]
80084b2: 699a ldr r2, [r3, #24]
80084b4: 4b10 ldr r3, [pc, #64] @ (80084f8 <USB_DevInit+0x28c>)
80084b6: 4313 orrs r3, r2
80084b8: 687a ldr r2, [r7, #4]
80084ba: 6193 str r3, [r2, #24]
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
if (cfg.Sof_enable != 0U)
80084bc: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
80084c0: 2b00 cmp r3, #0
80084c2: d005 beq.n 80084d0 <USB_DevInit+0x264>
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
80084c4: 687b ldr r3, [r7, #4]
80084c6: 699b ldr r3, [r3, #24]
80084c8: f043 0208 orr.w r2, r3, #8
80084cc: 687b ldr r3, [r7, #4]
80084ce: 619a str r2, [r3, #24]
}
if (cfg.vbus_sensing_enable == 1U)
80084d0: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
80084d4: 2b01 cmp r3, #1
80084d6: d107 bne.n 80084e8 <USB_DevInit+0x27c>
{
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
80084d8: 687b ldr r3, [r7, #4]
80084da: 699b ldr r3, [r3, #24]
80084dc: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
80084e0: f043 0304 orr.w r3, r3, #4
80084e4: 687a ldr r2, [r7, #4]
80084e6: 6193 str r3, [r2, #24]
}
return ret;
80084e8: 7dfb ldrb r3, [r7, #23]
}
80084ea: 4618 mov r0, r3
80084ec: 3718 adds r7, #24
80084ee: 46bd mov sp, r7
80084f0: e8bd 4080 ldmia.w sp!, {r7, lr}
80084f4: b004 add sp, #16
80084f6: 4770 bx lr
80084f8: 803c3800 .word 0x803c3800
080084fc <USB_FlushTxFifo>:
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
80084fc: b480 push {r7}
80084fe: b085 sub sp, #20
8008500: af00 add r7, sp, #0
8008502: 6078 str r0, [r7, #4]
8008504: 6039 str r1, [r7, #0]
__IO uint32_t count = 0U;
8008506: 2300 movs r3, #0
8008508: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
800850a: 68fb ldr r3, [r7, #12]
800850c: 3301 adds r3, #1
800850e: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8008510: 68fb ldr r3, [r7, #12]
8008512: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8008516: d901 bls.n 800851c <USB_FlushTxFifo+0x20>
{
return HAL_TIMEOUT;
8008518: 2303 movs r3, #3
800851a: e01b b.n 8008554 <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
800851c: 687b ldr r3, [r7, #4]
800851e: 691b ldr r3, [r3, #16]
8008520: 2b00 cmp r3, #0
8008522: daf2 bge.n 800850a <USB_FlushTxFifo+0xe>
/* Flush TX Fifo */
count = 0U;
8008524: 2300 movs r3, #0
8008526: 60fb str r3, [r7, #12]
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
8008528: 683b ldr r3, [r7, #0]
800852a: 019b lsls r3, r3, #6
800852c: f043 0220 orr.w r2, r3, #32
8008530: 687b ldr r3, [r7, #4]
8008532: 611a str r2, [r3, #16]
do
{
count++;
8008534: 68fb ldr r3, [r7, #12]
8008536: 3301 adds r3, #1
8008538: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
800853a: 68fb ldr r3, [r7, #12]
800853c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8008540: d901 bls.n 8008546 <USB_FlushTxFifo+0x4a>
{
return HAL_TIMEOUT;
8008542: 2303 movs r3, #3
8008544: e006 b.n 8008554 <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
8008546: 687b ldr r3, [r7, #4]
8008548: 691b ldr r3, [r3, #16]
800854a: f003 0320 and.w r3, r3, #32
800854e: 2b20 cmp r3, #32
8008550: d0f0 beq.n 8008534 <USB_FlushTxFifo+0x38>
return HAL_OK;
8008552: 2300 movs r3, #0
}
8008554: 4618 mov r0, r3
8008556: 3714 adds r7, #20
8008558: 46bd mov sp, r7
800855a: f85d 7b04 ldr.w r7, [sp], #4
800855e: 4770 bx lr
08008560 <USB_FlushRxFifo>:
* @brief USB_FlushRxFifo Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
8008560: b480 push {r7}
8008562: b085 sub sp, #20
8008564: af00 add r7, sp, #0
8008566: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8008568: 2300 movs r3, #0
800856a: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
800856c: 68fb ldr r3, [r7, #12]
800856e: 3301 adds r3, #1
8008570: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8008572: 68fb ldr r3, [r7, #12]
8008574: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8008578: d901 bls.n 800857e <USB_FlushRxFifo+0x1e>
{
return HAL_TIMEOUT;
800857a: 2303 movs r3, #3
800857c: e018 b.n 80085b0 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
800857e: 687b ldr r3, [r7, #4]
8008580: 691b ldr r3, [r3, #16]
8008582: 2b00 cmp r3, #0
8008584: daf2 bge.n 800856c <USB_FlushRxFifo+0xc>
/* Flush RX Fifo */
count = 0U;
8008586: 2300 movs r3, #0
8008588: 60fb str r3, [r7, #12]
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
800858a: 687b ldr r3, [r7, #4]
800858c: 2210 movs r2, #16
800858e: 611a str r2, [r3, #16]
do
{
count++;
8008590: 68fb ldr r3, [r7, #12]
8008592: 3301 adds r3, #1
8008594: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8008596: 68fb ldr r3, [r7, #12]
8008598: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
800859c: d901 bls.n 80085a2 <USB_FlushRxFifo+0x42>
{
return HAL_TIMEOUT;
800859e: 2303 movs r3, #3
80085a0: e006 b.n 80085b0 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
80085a2: 687b ldr r3, [r7, #4]
80085a4: 691b ldr r3, [r3, #16]
80085a6: f003 0310 and.w r3, r3, #16
80085aa: 2b10 cmp r3, #16
80085ac: d0f0 beq.n 8008590 <USB_FlushRxFifo+0x30>
return HAL_OK;
80085ae: 2300 movs r3, #0
}
80085b0: 4618 mov r0, r3
80085b2: 3714 adds r7, #20
80085b4: 46bd mov sp, r7
80085b6: f85d 7b04 ldr.w r7, [sp], #4
80085ba: 4770 bx lr
080085bc <USB_SetDevSpeed>:
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
80085bc: b480 push {r7}
80085be: b085 sub sp, #20
80085c0: af00 add r7, sp, #0
80085c2: 6078 str r0, [r7, #4]
80085c4: 460b mov r3, r1
80085c6: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
80085c8: 687b ldr r3, [r7, #4]
80085ca: 60fb str r3, [r7, #12]
USBx_DEVICE->DCFG |= speed;
80085cc: 68fb ldr r3, [r7, #12]
80085ce: f503 6300 add.w r3, r3, #2048 @ 0x800
80085d2: 681a ldr r2, [r3, #0]
80085d4: 78fb ldrb r3, [r7, #3]
80085d6: 68f9 ldr r1, [r7, #12]
80085d8: f501 6100 add.w r1, r1, #2048 @ 0x800
80085dc: 4313 orrs r3, r2
80085de: 600b str r3, [r1, #0]
return HAL_OK;
80085e0: 2300 movs r3, #0
}
80085e2: 4618 mov r0, r3
80085e4: 3714 adds r7, #20
80085e6: 46bd mov sp, r7
80085e8: f85d 7b04 ldr.w r7, [sp], #4
80085ec: 4770 bx lr
080085ee <USB_GetDevSpeed>:
* @retval speed device speed
* This parameter can be one of these values:
* @arg USBD_FS_SPEED: Full speed mode
*/
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
{
80085ee: b480 push {r7}
80085f0: b087 sub sp, #28
80085f2: af00 add r7, sp, #0
80085f4: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
80085f6: 687b ldr r3, [r7, #4]
80085f8: 613b str r3, [r7, #16]
uint8_t speed;
uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
80085fa: 693b ldr r3, [r7, #16]
80085fc: f503 6300 add.w r3, r3, #2048 @ 0x800
8008600: 689b ldr r3, [r3, #8]
8008602: f003 0306 and.w r3, r3, #6
8008606: 60fb str r3, [r7, #12]
if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
8008608: 68fb ldr r3, [r7, #12]
800860a: 2b02 cmp r3, #2
800860c: d002 beq.n 8008614 <USB_GetDevSpeed+0x26>
800860e: 68fb ldr r3, [r7, #12]
8008610: 2b06 cmp r3, #6
8008612: d102 bne.n 800861a <USB_GetDevSpeed+0x2c>
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
{
speed = USBD_FS_SPEED;
8008614: 2302 movs r3, #2
8008616: 75fb strb r3, [r7, #23]
8008618: e001 b.n 800861e <USB_GetDevSpeed+0x30>
}
else
{
speed = 0xFU;
800861a: 230f movs r3, #15
800861c: 75fb strb r3, [r7, #23]
}
return speed;
800861e: 7dfb ldrb r3, [r7, #23]
}
8008620: 4618 mov r0, r3
8008622: 371c adds r7, #28
8008624: 46bd mov sp, r7
8008626: f85d 7b04 ldr.w r7, [sp], #4
800862a: 4770 bx lr
0800862c <USB_ActivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
800862c: b480 push {r7}
800862e: b085 sub sp, #20
8008630: af00 add r7, sp, #0
8008632: 6078 str r0, [r7, #4]
8008634: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
8008636: 687b ldr r3, [r7, #4]
8008638: 60fb str r3, [r7, #12]
uint32_t epnum = (uint32_t)ep->num;
800863a: 683b ldr r3, [r7, #0]
800863c: 781b ldrb r3, [r3, #0]
800863e: 60bb str r3, [r7, #8]
if (ep->is_in == 1U)
8008640: 683b ldr r3, [r7, #0]
8008642: 785b ldrb r3, [r3, #1]
8008644: 2b01 cmp r3, #1
8008646: d13a bne.n 80086be <USB_ActivateEndpoint+0x92>
{
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
8008648: 68fb ldr r3, [r7, #12]
800864a: f503 6300 add.w r3, r3, #2048 @ 0x800
800864e: 69da ldr r2, [r3, #28]
8008650: 683b ldr r3, [r7, #0]
8008652: 781b ldrb r3, [r3, #0]
8008654: f003 030f and.w r3, r3, #15
8008658: 2101 movs r1, #1
800865a: fa01 f303 lsl.w r3, r1, r3
800865e: b29b uxth r3, r3
8008660: 68f9 ldr r1, [r7, #12]
8008662: f501 6100 add.w r1, r1, #2048 @ 0x800
8008666: 4313 orrs r3, r2
8008668: 61cb str r3, [r1, #28]
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
800866a: 68bb ldr r3, [r7, #8]
800866c: 015a lsls r2, r3, #5
800866e: 68fb ldr r3, [r7, #12]
8008670: 4413 add r3, r2
8008672: f503 6310 add.w r3, r3, #2304 @ 0x900
8008676: 681b ldr r3, [r3, #0]
8008678: f403 4300 and.w r3, r3, #32768 @ 0x8000
800867c: 2b00 cmp r3, #0
800867e: d155 bne.n 800872c <USB_ActivateEndpoint+0x100>
{
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
8008680: 68bb ldr r3, [r7, #8]
8008682: 015a lsls r2, r3, #5
8008684: 68fb ldr r3, [r7, #12]
8008686: 4413 add r3, r2
8008688: f503 6310 add.w r3, r3, #2304 @ 0x900
800868c: 681a ldr r2, [r3, #0]
800868e: 683b ldr r3, [r7, #0]
8008690: 689b ldr r3, [r3, #8]
8008692: f3c3 010a ubfx r1, r3, #0, #11
((uint32_t)ep->type << 18) | (epnum << 22) |
8008696: 683b ldr r3, [r7, #0]
8008698: 791b ldrb r3, [r3, #4]
800869a: 049b lsls r3, r3, #18
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
800869c: 4319 orrs r1, r3
((uint32_t)ep->type << 18) | (epnum << 22) |
800869e: 68bb ldr r3, [r7, #8]
80086a0: 059b lsls r3, r3, #22
80086a2: 430b orrs r3, r1
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
80086a4: 4313 orrs r3, r2
80086a6: 68ba ldr r2, [r7, #8]
80086a8: 0151 lsls r1, r2, #5
80086aa: 68fa ldr r2, [r7, #12]
80086ac: 440a add r2, r1
80086ae: f502 6210 add.w r2, r2, #2304 @ 0x900
80086b2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80086b6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80086ba: 6013 str r3, [r2, #0]
80086bc: e036 b.n 800872c <USB_ActivateEndpoint+0x100>
USB_OTG_DIEPCTL_USBAEP;
}
}
else
{
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
80086be: 68fb ldr r3, [r7, #12]
80086c0: f503 6300 add.w r3, r3, #2048 @ 0x800
80086c4: 69da ldr r2, [r3, #28]
80086c6: 683b ldr r3, [r7, #0]
80086c8: 781b ldrb r3, [r3, #0]
80086ca: f003 030f and.w r3, r3, #15
80086ce: 2101 movs r1, #1
80086d0: fa01 f303 lsl.w r3, r1, r3
80086d4: 041b lsls r3, r3, #16
80086d6: 68f9 ldr r1, [r7, #12]
80086d8: f501 6100 add.w r1, r1, #2048 @ 0x800
80086dc: 4313 orrs r3, r2
80086de: 61cb str r3, [r1, #28]
if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
80086e0: 68bb ldr r3, [r7, #8]
80086e2: 015a lsls r2, r3, #5
80086e4: 68fb ldr r3, [r7, #12]
80086e6: 4413 add r3, r2
80086e8: f503 6330 add.w r3, r3, #2816 @ 0xb00
80086ec: 681b ldr r3, [r3, #0]
80086ee: f403 4300 and.w r3, r3, #32768 @ 0x8000
80086f2: 2b00 cmp r3, #0
80086f4: d11a bne.n 800872c <USB_ActivateEndpoint+0x100>
{
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
80086f6: 68bb ldr r3, [r7, #8]
80086f8: 015a lsls r2, r3, #5
80086fa: 68fb ldr r3, [r7, #12]
80086fc: 4413 add r3, r2
80086fe: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008702: 681a ldr r2, [r3, #0]
8008704: 683b ldr r3, [r7, #0]
8008706: 689b ldr r3, [r3, #8]
8008708: f3c3 010a ubfx r1, r3, #0, #11
((uint32_t)ep->type << 18) |
800870c: 683b ldr r3, [r7, #0]
800870e: 791b ldrb r3, [r3, #4]
8008710: 049b lsls r3, r3, #18
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
8008712: 430b orrs r3, r1
8008714: 4313 orrs r3, r2
8008716: 68ba ldr r2, [r7, #8]
8008718: 0151 lsls r1, r2, #5
800871a: 68fa ldr r2, [r7, #12]
800871c: 440a add r2, r1
800871e: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008722: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8008726: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800872a: 6013 str r3, [r2, #0]
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DOEPCTL_USBAEP;
}
}
return HAL_OK;
800872c: 2300 movs r3, #0
}
800872e: 4618 mov r0, r3
8008730: 3714 adds r7, #20
8008732: 46bd mov sp, r7
8008734: f85d 7b04 ldr.w r7, [sp], #4
8008738: 4770 bx lr
...
0800873c <USB_DeactivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
800873c: b480 push {r7}
800873e: b085 sub sp, #20
8008740: af00 add r7, sp, #0
8008742: 6078 str r0, [r7, #4]
8008744: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
8008746: 687b ldr r3, [r7, #4]
8008748: 60fb str r3, [r7, #12]
uint32_t epnum = (uint32_t)ep->num;
800874a: 683b ldr r3, [r7, #0]
800874c: 781b ldrb r3, [r3, #0]
800874e: 60bb str r3, [r7, #8]
/* Read DEPCTLn register */
if (ep->is_in == 1U)
8008750: 683b ldr r3, [r7, #0]
8008752: 785b ldrb r3, [r3, #1]
8008754: 2b01 cmp r3, #1
8008756: d161 bne.n 800881c <USB_DeactivateEndpoint+0xe0>
{
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
8008758: 68bb ldr r3, [r7, #8]
800875a: 015a lsls r2, r3, #5
800875c: 68fb ldr r3, [r7, #12]
800875e: 4413 add r3, r2
8008760: f503 6310 add.w r3, r3, #2304 @ 0x900
8008764: 681b ldr r3, [r3, #0]
8008766: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800876a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
800876e: d11f bne.n 80087b0 <USB_DeactivateEndpoint+0x74>
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
8008770: 68bb ldr r3, [r7, #8]
8008772: 015a lsls r2, r3, #5
8008774: 68fb ldr r3, [r7, #12]
8008776: 4413 add r3, r2
8008778: f503 6310 add.w r3, r3, #2304 @ 0x900
800877c: 681b ldr r3, [r3, #0]
800877e: 68ba ldr r2, [r7, #8]
8008780: 0151 lsls r1, r2, #5
8008782: 68fa ldr r2, [r7, #12]
8008784: 440a add r2, r1
8008786: f502 6210 add.w r2, r2, #2304 @ 0x900
800878a: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
800878e: 6013 str r3, [r2, #0]
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
8008790: 68bb ldr r3, [r7, #8]
8008792: 015a lsls r2, r3, #5
8008794: 68fb ldr r3, [r7, #12]
8008796: 4413 add r3, r2
8008798: f503 6310 add.w r3, r3, #2304 @ 0x900
800879c: 681b ldr r3, [r3, #0]
800879e: 68ba ldr r2, [r7, #8]
80087a0: 0151 lsls r1, r2, #5
80087a2: 68fa ldr r2, [r7, #12]
80087a4: 440a add r2, r1
80087a6: f502 6210 add.w r2, r2, #2304 @ 0x900
80087aa: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
80087ae: 6013 str r3, [r2, #0]
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
80087b0: 68fb ldr r3, [r7, #12]
80087b2: f503 6300 add.w r3, r3, #2048 @ 0x800
80087b6: 6bda ldr r2, [r3, #60] @ 0x3c
80087b8: 683b ldr r3, [r7, #0]
80087ba: 781b ldrb r3, [r3, #0]
80087bc: f003 030f and.w r3, r3, #15
80087c0: 2101 movs r1, #1
80087c2: fa01 f303 lsl.w r3, r1, r3
80087c6: b29b uxth r3, r3
80087c8: 43db mvns r3, r3
80087ca: 68f9 ldr r1, [r7, #12]
80087cc: f501 6100 add.w r1, r1, #2048 @ 0x800
80087d0: 4013 ands r3, r2
80087d2: 63cb str r3, [r1, #60] @ 0x3c
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
80087d4: 68fb ldr r3, [r7, #12]
80087d6: f503 6300 add.w r3, r3, #2048 @ 0x800
80087da: 69da ldr r2, [r3, #28]
80087dc: 683b ldr r3, [r7, #0]
80087de: 781b ldrb r3, [r3, #0]
80087e0: f003 030f and.w r3, r3, #15
80087e4: 2101 movs r1, #1
80087e6: fa01 f303 lsl.w r3, r1, r3
80087ea: b29b uxth r3, r3
80087ec: 43db mvns r3, r3
80087ee: 68f9 ldr r1, [r7, #12]
80087f0: f501 6100 add.w r1, r1, #2048 @ 0x800
80087f4: 4013 ands r3, r2
80087f6: 61cb str r3, [r1, #28]
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
80087f8: 68bb ldr r3, [r7, #8]
80087fa: 015a lsls r2, r3, #5
80087fc: 68fb ldr r3, [r7, #12]
80087fe: 4413 add r3, r2
8008800: f503 6310 add.w r3, r3, #2304 @ 0x900
8008804: 681a ldr r2, [r3, #0]
8008806: 68bb ldr r3, [r7, #8]
8008808: 0159 lsls r1, r3, #5
800880a: 68fb ldr r3, [r7, #12]
800880c: 440b add r3, r1
800880e: f503 6310 add.w r3, r3, #2304 @ 0x900
8008812: 4619 mov r1, r3
8008814: 4b35 ldr r3, [pc, #212] @ (80088ec <USB_DeactivateEndpoint+0x1b0>)
8008816: 4013 ands r3, r2
8008818: 600b str r3, [r1, #0]
800881a: e060 b.n 80088de <USB_DeactivateEndpoint+0x1a2>
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DIEPCTL_EPTYP);
}
else
{
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
800881c: 68bb ldr r3, [r7, #8]
800881e: 015a lsls r2, r3, #5
8008820: 68fb ldr r3, [r7, #12]
8008822: 4413 add r3, r2
8008824: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008828: 681b ldr r3, [r3, #0]
800882a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800882e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8008832: d11f bne.n 8008874 <USB_DeactivateEndpoint+0x138>
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
8008834: 68bb ldr r3, [r7, #8]
8008836: 015a lsls r2, r3, #5
8008838: 68fb ldr r3, [r7, #12]
800883a: 4413 add r3, r2
800883c: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008840: 681b ldr r3, [r3, #0]
8008842: 68ba ldr r2, [r7, #8]
8008844: 0151 lsls r1, r2, #5
8008846: 68fa ldr r2, [r7, #12]
8008848: 440a add r2, r1
800884a: f502 6230 add.w r2, r2, #2816 @ 0xb00
800884e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
8008852: 6013 str r3, [r2, #0]
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
8008854: 68bb ldr r3, [r7, #8]
8008856: 015a lsls r2, r3, #5
8008858: 68fb ldr r3, [r7, #12]
800885a: 4413 add r3, r2
800885c: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008860: 681b ldr r3, [r3, #0]
8008862: 68ba ldr r2, [r7, #8]
8008864: 0151 lsls r1, r2, #5
8008866: 68fa ldr r2, [r7, #12]
8008868: 440a add r2, r1
800886a: f502 6230 add.w r2, r2, #2816 @ 0xb00
800886e: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8008872: 6013 str r3, [r2, #0]
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
8008874: 68fb ldr r3, [r7, #12]
8008876: f503 6300 add.w r3, r3, #2048 @ 0x800
800887a: 6bda ldr r2, [r3, #60] @ 0x3c
800887c: 683b ldr r3, [r7, #0]
800887e: 781b ldrb r3, [r3, #0]
8008880: f003 030f and.w r3, r3, #15
8008884: 2101 movs r1, #1
8008886: fa01 f303 lsl.w r3, r1, r3
800888a: 041b lsls r3, r3, #16
800888c: 43db mvns r3, r3
800888e: 68f9 ldr r1, [r7, #12]
8008890: f501 6100 add.w r1, r1, #2048 @ 0x800
8008894: 4013 ands r3, r2
8008896: 63cb str r3, [r1, #60] @ 0x3c
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
8008898: 68fb ldr r3, [r7, #12]
800889a: f503 6300 add.w r3, r3, #2048 @ 0x800
800889e: 69da ldr r2, [r3, #28]
80088a0: 683b ldr r3, [r7, #0]
80088a2: 781b ldrb r3, [r3, #0]
80088a4: f003 030f and.w r3, r3, #15
80088a8: 2101 movs r1, #1
80088aa: fa01 f303 lsl.w r3, r1, r3
80088ae: 041b lsls r3, r3, #16
80088b0: 43db mvns r3, r3
80088b2: 68f9 ldr r1, [r7, #12]
80088b4: f501 6100 add.w r1, r1, #2048 @ 0x800
80088b8: 4013 ands r3, r2
80088ba: 61cb str r3, [r1, #28]
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
80088bc: 68bb ldr r3, [r7, #8]
80088be: 015a lsls r2, r3, #5
80088c0: 68fb ldr r3, [r7, #12]
80088c2: 4413 add r3, r2
80088c4: f503 6330 add.w r3, r3, #2816 @ 0xb00
80088c8: 681a ldr r2, [r3, #0]
80088ca: 68bb ldr r3, [r7, #8]
80088cc: 0159 lsls r1, r3, #5
80088ce: 68fb ldr r3, [r7, #12]
80088d0: 440b add r3, r1
80088d2: f503 6330 add.w r3, r3, #2816 @ 0xb00
80088d6: 4619 mov r1, r3
80088d8: 4b05 ldr r3, [pc, #20] @ (80088f0 <USB_DeactivateEndpoint+0x1b4>)
80088da: 4013 ands r3, r2
80088dc: 600b str r3, [r1, #0]
USB_OTG_DOEPCTL_MPSIZ |
USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
USB_OTG_DOEPCTL_EPTYP);
}
return HAL_OK;
80088de: 2300 movs r3, #0
}
80088e0: 4618 mov r0, r3
80088e2: 3714 adds r7, #20
80088e4: 46bd mov sp, r7
80088e6: f85d 7b04 ldr.w r7, [sp], #4
80088ea: 4770 bx lr
80088ec: ec337800 .word 0xec337800
80088f0: eff37800 .word 0xeff37800
080088f4 <USB_EPStartXfer>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
80088f4: b580 push {r7, lr}
80088f6: b086 sub sp, #24
80088f8: af00 add r7, sp, #0
80088fa: 6078 str r0, [r7, #4]
80088fc: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
80088fe: 687b ldr r3, [r7, #4]
8008900: 617b str r3, [r7, #20]
uint32_t epnum = (uint32_t)ep->num;
8008902: 683b ldr r3, [r7, #0]
8008904: 781b ldrb r3, [r3, #0]
8008906: 613b str r3, [r7, #16]
uint16_t pktcnt;
/* IN endpoint */
if (ep->is_in == 1U)
8008908: 683b ldr r3, [r7, #0]
800890a: 785b ldrb r3, [r3, #1]
800890c: 2b01 cmp r3, #1
800890e: f040 812d bne.w 8008b6c <USB_EPStartXfer+0x278>
{
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
8008912: 683b ldr r3, [r7, #0]
8008914: 691b ldr r3, [r3, #16]
8008916: 2b00 cmp r3, #0
8008918: d132 bne.n 8008980 <USB_EPStartXfer+0x8c>
{
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
800891a: 693b ldr r3, [r7, #16]
800891c: 015a lsls r2, r3, #5
800891e: 697b ldr r3, [r7, #20]
8008920: 4413 add r3, r2
8008922: f503 6310 add.w r3, r3, #2304 @ 0x900
8008926: 691b ldr r3, [r3, #16]
8008928: 693a ldr r2, [r7, #16]
800892a: 0151 lsls r1, r2, #5
800892c: 697a ldr r2, [r7, #20]
800892e: 440a add r2, r1
8008930: f502 6210 add.w r2, r2, #2304 @ 0x900
8008934: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
8008938: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
800893c: 6113 str r3, [r2, #16]
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
800893e: 693b ldr r3, [r7, #16]
8008940: 015a lsls r2, r3, #5
8008942: 697b ldr r3, [r7, #20]
8008944: 4413 add r3, r2
8008946: f503 6310 add.w r3, r3, #2304 @ 0x900
800894a: 691b ldr r3, [r3, #16]
800894c: 693a ldr r2, [r7, #16]
800894e: 0151 lsls r1, r2, #5
8008950: 697a ldr r2, [r7, #20]
8008952: 440a add r2, r1
8008954: f502 6210 add.w r2, r2, #2304 @ 0x900
8008958: f443 2300 orr.w r3, r3, #524288 @ 0x80000
800895c: 6113 str r3, [r2, #16]
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
800895e: 693b ldr r3, [r7, #16]
8008960: 015a lsls r2, r3, #5
8008962: 697b ldr r3, [r7, #20]
8008964: 4413 add r3, r2
8008966: f503 6310 add.w r3, r3, #2304 @ 0x900
800896a: 691b ldr r3, [r3, #16]
800896c: 693a ldr r2, [r7, #16]
800896e: 0151 lsls r1, r2, #5
8008970: 697a ldr r2, [r7, #20]
8008972: 440a add r2, r1
8008974: f502 6210 add.w r2, r2, #2304 @ 0x900
8008978: 0cdb lsrs r3, r3, #19
800897a: 04db lsls r3, r3, #19
800897c: 6113 str r3, [r2, #16]
800897e: e097 b.n 8008ab0 <USB_EPStartXfer+0x1bc>
/* Program the transfer size and packet count
* as follows: xfersize = N * maxpacket +
* short_packet pktcnt = N + (short_packet
* exist ? 1 : 0)
*/
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
8008980: 693b ldr r3, [r7, #16]
8008982: 015a lsls r2, r3, #5
8008984: 697b ldr r3, [r7, #20]
8008986: 4413 add r3, r2
8008988: f503 6310 add.w r3, r3, #2304 @ 0x900
800898c: 691b ldr r3, [r3, #16]
800898e: 693a ldr r2, [r7, #16]
8008990: 0151 lsls r1, r2, #5
8008992: 697a ldr r2, [r7, #20]
8008994: 440a add r2, r1
8008996: f502 6210 add.w r2, r2, #2304 @ 0x900
800899a: 0cdb lsrs r3, r3, #19
800899c: 04db lsls r3, r3, #19
800899e: 6113 str r3, [r2, #16]
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
80089a0: 693b ldr r3, [r7, #16]
80089a2: 015a lsls r2, r3, #5
80089a4: 697b ldr r3, [r7, #20]
80089a6: 4413 add r3, r2
80089a8: f503 6310 add.w r3, r3, #2304 @ 0x900
80089ac: 691b ldr r3, [r3, #16]
80089ae: 693a ldr r2, [r7, #16]
80089b0: 0151 lsls r1, r2, #5
80089b2: 697a ldr r2, [r7, #20]
80089b4: 440a add r2, r1
80089b6: f502 6210 add.w r2, r2, #2304 @ 0x900
80089ba: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
80089be: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
80089c2: 6113 str r3, [r2, #16]
if (epnum == 0U)
80089c4: 693b ldr r3, [r7, #16]
80089c6: 2b00 cmp r3, #0
80089c8: d11a bne.n 8008a00 <USB_EPStartXfer+0x10c>
{
if (ep->xfer_len > ep->maxpacket)
80089ca: 683b ldr r3, [r7, #0]
80089cc: 691a ldr r2, [r3, #16]
80089ce: 683b ldr r3, [r7, #0]
80089d0: 689b ldr r3, [r3, #8]
80089d2: 429a cmp r2, r3
80089d4: d903 bls.n 80089de <USB_EPStartXfer+0xea>
{
ep->xfer_len = ep->maxpacket;
80089d6: 683b ldr r3, [r7, #0]
80089d8: 689a ldr r2, [r3, #8]
80089da: 683b ldr r3, [r7, #0]
80089dc: 611a str r2, [r3, #16]
}
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
80089de: 693b ldr r3, [r7, #16]
80089e0: 015a lsls r2, r3, #5
80089e2: 697b ldr r3, [r7, #20]
80089e4: 4413 add r3, r2
80089e6: f503 6310 add.w r3, r3, #2304 @ 0x900
80089ea: 691b ldr r3, [r3, #16]
80089ec: 693a ldr r2, [r7, #16]
80089ee: 0151 lsls r1, r2, #5
80089f0: 697a ldr r2, [r7, #20]
80089f2: 440a add r2, r1
80089f4: f502 6210 add.w r2, r2, #2304 @ 0x900
80089f8: f443 2300 orr.w r3, r3, #524288 @ 0x80000
80089fc: 6113 str r3, [r2, #16]
80089fe: e044 b.n 8008a8a <USB_EPStartXfer+0x196>
}
else
{
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
8008a00: 683b ldr r3, [r7, #0]
8008a02: 691a ldr r2, [r3, #16]
8008a04: 683b ldr r3, [r7, #0]
8008a06: 689b ldr r3, [r3, #8]
8008a08: 4413 add r3, r2
8008a0a: 1e5a subs r2, r3, #1
8008a0c: 683b ldr r3, [r7, #0]
8008a0e: 689b ldr r3, [r3, #8]
8008a10: fbb2 f3f3 udiv r3, r2, r3
8008a14: 81fb strh r3, [r7, #14]
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19));
8008a16: 693b ldr r3, [r7, #16]
8008a18: 015a lsls r2, r3, #5
8008a1a: 697b ldr r3, [r7, #20]
8008a1c: 4413 add r3, r2
8008a1e: f503 6310 add.w r3, r3, #2304 @ 0x900
8008a22: 691a ldr r2, [r3, #16]
8008a24: 89fb ldrh r3, [r7, #14]
8008a26: 04d9 lsls r1, r3, #19
8008a28: 4b8f ldr r3, [pc, #572] @ (8008c68 <USB_EPStartXfer+0x374>)
8008a2a: 400b ands r3, r1
8008a2c: 6939 ldr r1, [r7, #16]
8008a2e: 0148 lsls r0, r1, #5
8008a30: 6979 ldr r1, [r7, #20]
8008a32: 4401 add r1, r0
8008a34: f501 6110 add.w r1, r1, #2304 @ 0x900
8008a38: 4313 orrs r3, r2
8008a3a: 610b str r3, [r1, #16]
if (ep->type == EP_TYPE_ISOC)
8008a3c: 683b ldr r3, [r7, #0]
8008a3e: 791b ldrb r3, [r3, #4]
8008a40: 2b01 cmp r3, #1
8008a42: d122 bne.n 8008a8a <USB_EPStartXfer+0x196>
{
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
8008a44: 693b ldr r3, [r7, #16]
8008a46: 015a lsls r2, r3, #5
8008a48: 697b ldr r3, [r7, #20]
8008a4a: 4413 add r3, r2
8008a4c: f503 6310 add.w r3, r3, #2304 @ 0x900
8008a50: 691b ldr r3, [r3, #16]
8008a52: 693a ldr r2, [r7, #16]
8008a54: 0151 lsls r1, r2, #5
8008a56: 697a ldr r2, [r7, #20]
8008a58: 440a add r2, r1
8008a5a: f502 6210 add.w r2, r2, #2304 @ 0x900
8008a5e: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000
8008a62: 6113 str r3, [r2, #16]
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (pktcnt << 29));
8008a64: 693b ldr r3, [r7, #16]
8008a66: 015a lsls r2, r3, #5
8008a68: 697b ldr r3, [r7, #20]
8008a6a: 4413 add r3, r2
8008a6c: f503 6310 add.w r3, r3, #2304 @ 0x900
8008a70: 691a ldr r2, [r3, #16]
8008a72: 89fb ldrh r3, [r7, #14]
8008a74: 075b lsls r3, r3, #29
8008a76: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000
8008a7a: 6939 ldr r1, [r7, #16]
8008a7c: 0148 lsls r0, r1, #5
8008a7e: 6979 ldr r1, [r7, #20]
8008a80: 4401 add r1, r0
8008a82: f501 6110 add.w r1, r1, #2304 @ 0x900
8008a86: 4313 orrs r3, r2
8008a88: 610b str r3, [r1, #16]
}
}
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
8008a8a: 693b ldr r3, [r7, #16]
8008a8c: 015a lsls r2, r3, #5
8008a8e: 697b ldr r3, [r7, #20]
8008a90: 4413 add r3, r2
8008a92: f503 6310 add.w r3, r3, #2304 @ 0x900
8008a96: 691a ldr r2, [r3, #16]
8008a98: 683b ldr r3, [r7, #0]
8008a9a: 691b ldr r3, [r3, #16]
8008a9c: f3c3 0312 ubfx r3, r3, #0, #19
8008aa0: 6939 ldr r1, [r7, #16]
8008aa2: 0148 lsls r0, r1, #5
8008aa4: 6979 ldr r1, [r7, #20]
8008aa6: 4401 add r1, r0
8008aa8: f501 6110 add.w r1, r1, #2304 @ 0x900
8008aac: 4313 orrs r3, r2
8008aae: 610b str r3, [r1, #16]
}
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
8008ab0: 693b ldr r3, [r7, #16]
8008ab2: 015a lsls r2, r3, #5
8008ab4: 697b ldr r3, [r7, #20]
8008ab6: 4413 add r3, r2
8008ab8: f503 6310 add.w r3, r3, #2304 @ 0x900
8008abc: 681b ldr r3, [r3, #0]
8008abe: 693a ldr r2, [r7, #16]
8008ac0: 0151 lsls r1, r2, #5
8008ac2: 697a ldr r2, [r7, #20]
8008ac4: 440a add r2, r1
8008ac6: f502 6210 add.w r2, r2, #2304 @ 0x900
8008aca: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
8008ace: 6013 str r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8008ad0: 683b ldr r3, [r7, #0]
8008ad2: 791b ldrb r3, [r3, #4]
8008ad4: 2b01 cmp r3, #1
8008ad6: d015 beq.n 8008b04 <USB_EPStartXfer+0x210>
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
8008ad8: 683b ldr r3, [r7, #0]
8008ada: 691b ldr r3, [r3, #16]
8008adc: 2b00 cmp r3, #0
8008ade: f000 813a beq.w 8008d56 <USB_EPStartXfer+0x462>
{
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
8008ae2: 697b ldr r3, [r7, #20]
8008ae4: f503 6300 add.w r3, r3, #2048 @ 0x800
8008ae8: 6b5a ldr r2, [r3, #52] @ 0x34
8008aea: 683b ldr r3, [r7, #0]
8008aec: 781b ldrb r3, [r3, #0]
8008aee: f003 030f and.w r3, r3, #15
8008af2: 2101 movs r1, #1
8008af4: fa01 f303 lsl.w r3, r1, r3
8008af8: 6979 ldr r1, [r7, #20]
8008afa: f501 6100 add.w r1, r1, #2048 @ 0x800
8008afe: 4313 orrs r3, r2
8008b00: 634b str r3, [r1, #52] @ 0x34
8008b02: e128 b.n 8008d56 <USB_EPStartXfer+0x462>
}
}
else
{
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
8008b04: 697b ldr r3, [r7, #20]
8008b06: f503 6300 add.w r3, r3, #2048 @ 0x800
8008b0a: 689b ldr r3, [r3, #8]
8008b0c: f403 7380 and.w r3, r3, #256 @ 0x100
8008b10: 2b00 cmp r3, #0
8008b12: d110 bne.n 8008b36 <USB_EPStartXfer+0x242>
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
8008b14: 693b ldr r3, [r7, #16]
8008b16: 015a lsls r2, r3, #5
8008b18: 697b ldr r3, [r7, #20]
8008b1a: 4413 add r3, r2
8008b1c: f503 6310 add.w r3, r3, #2304 @ 0x900
8008b20: 681b ldr r3, [r3, #0]
8008b22: 693a ldr r2, [r7, #16]
8008b24: 0151 lsls r1, r2, #5
8008b26: 697a ldr r2, [r7, #20]
8008b28: 440a add r2, r1
8008b2a: f502 6210 add.w r2, r2, #2304 @ 0x900
8008b2e: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
8008b32: 6013 str r3, [r2, #0]
8008b34: e00f b.n 8008b56 <USB_EPStartXfer+0x262>
}
else
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
8008b36: 693b ldr r3, [r7, #16]
8008b38: 015a lsls r2, r3, #5
8008b3a: 697b ldr r3, [r7, #20]
8008b3c: 4413 add r3, r2
8008b3e: f503 6310 add.w r3, r3, #2304 @ 0x900
8008b42: 681b ldr r3, [r3, #0]
8008b44: 693a ldr r2, [r7, #16]
8008b46: 0151 lsls r1, r2, #5
8008b48: 697a ldr r2, [r7, #20]
8008b4a: 440a add r2, r1
8008b4c: f502 6210 add.w r2, r2, #2304 @ 0x900
8008b50: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8008b54: 6013 str r3, [r2, #0]
}
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len);
8008b56: 683b ldr r3, [r7, #0]
8008b58: 68d9 ldr r1, [r3, #12]
8008b5a: 683b ldr r3, [r7, #0]
8008b5c: 781a ldrb r2, [r3, #0]
8008b5e: 683b ldr r3, [r7, #0]
8008b60: 691b ldr r3, [r3, #16]
8008b62: b29b uxth r3, r3
8008b64: 6878 ldr r0, [r7, #4]
8008b66: f000 f9a7 bl 8008eb8 <USB_WritePacket>
8008b6a: e0f4 b.n 8008d56 <USB_EPStartXfer+0x462>
{
/* Program the transfer size and packet count as follows:
* pktcnt = N
* xfersize = N * maxpacket
*/
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
8008b6c: 693b ldr r3, [r7, #16]
8008b6e: 015a lsls r2, r3, #5
8008b70: 697b ldr r3, [r7, #20]
8008b72: 4413 add r3, r2
8008b74: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008b78: 691b ldr r3, [r3, #16]
8008b7a: 693a ldr r2, [r7, #16]
8008b7c: 0151 lsls r1, r2, #5
8008b7e: 697a ldr r2, [r7, #20]
8008b80: 440a add r2, r1
8008b82: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008b86: 0cdb lsrs r3, r3, #19
8008b88: 04db lsls r3, r3, #19
8008b8a: 6113 str r3, [r2, #16]
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
8008b8c: 693b ldr r3, [r7, #16]
8008b8e: 015a lsls r2, r3, #5
8008b90: 697b ldr r3, [r7, #20]
8008b92: 4413 add r3, r2
8008b94: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008b98: 691b ldr r3, [r3, #16]
8008b9a: 693a ldr r2, [r7, #16]
8008b9c: 0151 lsls r1, r2, #5
8008b9e: 697a ldr r2, [r7, #20]
8008ba0: 440a add r2, r1
8008ba2: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008ba6: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
8008baa: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
8008bae: 6113 str r3, [r2, #16]
if (epnum == 0U)
8008bb0: 693b ldr r3, [r7, #16]
8008bb2: 2b00 cmp r3, #0
8008bb4: d12f bne.n 8008c16 <USB_EPStartXfer+0x322>
{
if (ep->xfer_len > 0U)
8008bb6: 683b ldr r3, [r7, #0]
8008bb8: 691b ldr r3, [r3, #16]
8008bba: 2b00 cmp r3, #0
8008bbc: d003 beq.n 8008bc6 <USB_EPStartXfer+0x2d2>
{
ep->xfer_len = ep->maxpacket;
8008bbe: 683b ldr r3, [r7, #0]
8008bc0: 689a ldr r2, [r3, #8]
8008bc2: 683b ldr r3, [r7, #0]
8008bc4: 611a str r2, [r3, #16]
}
/* Store transfer size, for EP0 this is equal to endpoint max packet size */
ep->xfer_size = ep->maxpacket;
8008bc6: 683b ldr r3, [r7, #0]
8008bc8: 689a ldr r2, [r3, #8]
8008bca: 683b ldr r3, [r7, #0]
8008bcc: 621a str r2, [r3, #32]
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
8008bce: 693b ldr r3, [r7, #16]
8008bd0: 015a lsls r2, r3, #5
8008bd2: 697b ldr r3, [r7, #20]
8008bd4: 4413 add r3, r2
8008bd6: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008bda: 691a ldr r2, [r3, #16]
8008bdc: 683b ldr r3, [r7, #0]
8008bde: 6a1b ldr r3, [r3, #32]
8008be0: f3c3 0312 ubfx r3, r3, #0, #19
8008be4: 6939 ldr r1, [r7, #16]
8008be6: 0148 lsls r0, r1, #5
8008be8: 6979 ldr r1, [r7, #20]
8008bea: 4401 add r1, r0
8008bec: f501 6130 add.w r1, r1, #2816 @ 0xb00
8008bf0: 4313 orrs r3, r2
8008bf2: 610b str r3, [r1, #16]
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
8008bf4: 693b ldr r3, [r7, #16]
8008bf6: 015a lsls r2, r3, #5
8008bf8: 697b ldr r3, [r7, #20]
8008bfa: 4413 add r3, r2
8008bfc: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008c00: 691b ldr r3, [r3, #16]
8008c02: 693a ldr r2, [r7, #16]
8008c04: 0151 lsls r1, r2, #5
8008c06: 697a ldr r2, [r7, #20]
8008c08: 440a add r2, r1
8008c0a: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008c0e: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8008c12: 6113 str r3, [r2, #16]
8008c14: e062 b.n 8008cdc <USB_EPStartXfer+0x3e8>
}
else
{
if (ep->xfer_len == 0U)
8008c16: 683b ldr r3, [r7, #0]
8008c18: 691b ldr r3, [r3, #16]
8008c1a: 2b00 cmp r3, #0
8008c1c: d126 bne.n 8008c6c <USB_EPStartXfer+0x378>
{
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
8008c1e: 693b ldr r3, [r7, #16]
8008c20: 015a lsls r2, r3, #5
8008c22: 697b ldr r3, [r7, #20]
8008c24: 4413 add r3, r2
8008c26: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008c2a: 691a ldr r2, [r3, #16]
8008c2c: 683b ldr r3, [r7, #0]
8008c2e: 689b ldr r3, [r3, #8]
8008c30: f3c3 0312 ubfx r3, r3, #0, #19
8008c34: 6939 ldr r1, [r7, #16]
8008c36: 0148 lsls r0, r1, #5
8008c38: 6979 ldr r1, [r7, #20]
8008c3a: 4401 add r1, r0
8008c3c: f501 6130 add.w r1, r1, #2816 @ 0xb00
8008c40: 4313 orrs r3, r2
8008c42: 610b str r3, [r1, #16]
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
8008c44: 693b ldr r3, [r7, #16]
8008c46: 015a lsls r2, r3, #5
8008c48: 697b ldr r3, [r7, #20]
8008c4a: 4413 add r3, r2
8008c4c: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008c50: 691b ldr r3, [r3, #16]
8008c52: 693a ldr r2, [r7, #16]
8008c54: 0151 lsls r1, r2, #5
8008c56: 697a ldr r2, [r7, #20]
8008c58: 440a add r2, r1
8008c5a: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008c5e: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8008c62: 6113 str r3, [r2, #16]
8008c64: e03a b.n 8008cdc <USB_EPStartXfer+0x3e8>
8008c66: bf00 nop
8008c68: 1ff80000 .word 0x1ff80000
}
else
{
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
8008c6c: 683b ldr r3, [r7, #0]
8008c6e: 691a ldr r2, [r3, #16]
8008c70: 683b ldr r3, [r7, #0]
8008c72: 689b ldr r3, [r3, #8]
8008c74: 4413 add r3, r2
8008c76: 1e5a subs r2, r3, #1
8008c78: 683b ldr r3, [r7, #0]
8008c7a: 689b ldr r3, [r3, #8]
8008c7c: fbb2 f3f3 udiv r3, r2, r3
8008c80: 81fb strh r3, [r7, #14]
ep->xfer_size = ep->maxpacket * pktcnt;
8008c82: 683b ldr r3, [r7, #0]
8008c84: 689b ldr r3, [r3, #8]
8008c86: 89fa ldrh r2, [r7, #14]
8008c88: fb03 f202 mul.w r2, r3, r2
8008c8c: 683b ldr r3, [r7, #0]
8008c8e: 621a str r2, [r3, #32]
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
8008c90: 693b ldr r3, [r7, #16]
8008c92: 015a lsls r2, r3, #5
8008c94: 697b ldr r3, [r7, #20]
8008c96: 4413 add r3, r2
8008c98: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008c9c: 691a ldr r2, [r3, #16]
8008c9e: 89fb ldrh r3, [r7, #14]
8008ca0: 04d9 lsls r1, r3, #19
8008ca2: 4b2f ldr r3, [pc, #188] @ (8008d60 <USB_EPStartXfer+0x46c>)
8008ca4: 400b ands r3, r1
8008ca6: 6939 ldr r1, [r7, #16]
8008ca8: 0148 lsls r0, r1, #5
8008caa: 6979 ldr r1, [r7, #20]
8008cac: 4401 add r1, r0
8008cae: f501 6130 add.w r1, r1, #2816 @ 0xb00
8008cb2: 4313 orrs r3, r2
8008cb4: 610b str r3, [r1, #16]
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
8008cb6: 693b ldr r3, [r7, #16]
8008cb8: 015a lsls r2, r3, #5
8008cba: 697b ldr r3, [r7, #20]
8008cbc: 4413 add r3, r2
8008cbe: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008cc2: 691a ldr r2, [r3, #16]
8008cc4: 683b ldr r3, [r7, #0]
8008cc6: 6a1b ldr r3, [r3, #32]
8008cc8: f3c3 0312 ubfx r3, r3, #0, #19
8008ccc: 6939 ldr r1, [r7, #16]
8008cce: 0148 lsls r0, r1, #5
8008cd0: 6979 ldr r1, [r7, #20]
8008cd2: 4401 add r1, r0
8008cd4: f501 6130 add.w r1, r1, #2816 @ 0xb00
8008cd8: 4313 orrs r3, r2
8008cda: 610b str r3, [r1, #16]
}
}
if (ep->type == EP_TYPE_ISOC)
8008cdc: 683b ldr r3, [r7, #0]
8008cde: 791b ldrb r3, [r3, #4]
8008ce0: 2b01 cmp r3, #1
8008ce2: d128 bne.n 8008d36 <USB_EPStartXfer+0x442>
{
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
8008ce4: 697b ldr r3, [r7, #20]
8008ce6: f503 6300 add.w r3, r3, #2048 @ 0x800
8008cea: 689b ldr r3, [r3, #8]
8008cec: f403 7380 and.w r3, r3, #256 @ 0x100
8008cf0: 2b00 cmp r3, #0
8008cf2: d110 bne.n 8008d16 <USB_EPStartXfer+0x422>
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
8008cf4: 693b ldr r3, [r7, #16]
8008cf6: 015a lsls r2, r3, #5
8008cf8: 697b ldr r3, [r7, #20]
8008cfa: 4413 add r3, r2
8008cfc: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008d00: 681b ldr r3, [r3, #0]
8008d02: 693a ldr r2, [r7, #16]
8008d04: 0151 lsls r1, r2, #5
8008d06: 697a ldr r2, [r7, #20]
8008d08: 440a add r2, r1
8008d0a: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008d0e: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
8008d12: 6013 str r3, [r2, #0]
8008d14: e00f b.n 8008d36 <USB_EPStartXfer+0x442>
}
else
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
8008d16: 693b ldr r3, [r7, #16]
8008d18: 015a lsls r2, r3, #5
8008d1a: 697b ldr r3, [r7, #20]
8008d1c: 4413 add r3, r2
8008d1e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008d22: 681b ldr r3, [r3, #0]
8008d24: 693a ldr r2, [r7, #16]
8008d26: 0151 lsls r1, r2, #5
8008d28: 697a ldr r2, [r7, #20]
8008d2a: 440a add r2, r1
8008d2c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008d30: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8008d34: 6013 str r3, [r2, #0]
}
}
/* EP enable */
USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
8008d36: 693b ldr r3, [r7, #16]
8008d38: 015a lsls r2, r3, #5
8008d3a: 697b ldr r3, [r7, #20]
8008d3c: 4413 add r3, r2
8008d3e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008d42: 681b ldr r3, [r3, #0]
8008d44: 693a ldr r2, [r7, #16]
8008d46: 0151 lsls r1, r2, #5
8008d48: 697a ldr r2, [r7, #20]
8008d4a: 440a add r2, r1
8008d4c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008d50: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
8008d54: 6013 str r3, [r2, #0]
}
return HAL_OK;
8008d56: 2300 movs r3, #0
}
8008d58: 4618 mov r0, r3
8008d5a: 3718 adds r7, #24
8008d5c: 46bd mov sp, r7
8008d5e: bd80 pop {r7, pc}
8008d60: 1ff80000 .word 0x1ff80000
08008d64 <USB_EPStopXfer>:
* @param USBx usb device instance
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
8008d64: b480 push {r7}
8008d66: b087 sub sp, #28
8008d68: af00 add r7, sp, #0
8008d6a: 6078 str r0, [r7, #4]
8008d6c: 6039 str r1, [r7, #0]
__IO uint32_t count = 0U;
8008d6e: 2300 movs r3, #0
8008d70: 60fb str r3, [r7, #12]
HAL_StatusTypeDef ret = HAL_OK;
8008d72: 2300 movs r3, #0
8008d74: 75fb strb r3, [r7, #23]
uint32_t USBx_BASE = (uint32_t)USBx;
8008d76: 687b ldr r3, [r7, #4]
8008d78: 613b str r3, [r7, #16]
/* IN endpoint */
if (ep->is_in == 1U)
8008d7a: 683b ldr r3, [r7, #0]
8008d7c: 785b ldrb r3, [r3, #1]
8008d7e: 2b01 cmp r3, #1
8008d80: d14a bne.n 8008e18 <USB_EPStopXfer+0xb4>
{
/* EP enable, IN data in FIFO */
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
8008d82: 683b ldr r3, [r7, #0]
8008d84: 781b ldrb r3, [r3, #0]
8008d86: 015a lsls r2, r3, #5
8008d88: 693b ldr r3, [r7, #16]
8008d8a: 4413 add r3, r2
8008d8c: f503 6310 add.w r3, r3, #2304 @ 0x900
8008d90: 681b ldr r3, [r3, #0]
8008d92: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8008d96: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8008d9a: f040 8086 bne.w 8008eaa <USB_EPStopXfer+0x146>
{
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
8008d9e: 683b ldr r3, [r7, #0]
8008da0: 781b ldrb r3, [r3, #0]
8008da2: 015a lsls r2, r3, #5
8008da4: 693b ldr r3, [r7, #16]
8008da6: 4413 add r3, r2
8008da8: f503 6310 add.w r3, r3, #2304 @ 0x900
8008dac: 681b ldr r3, [r3, #0]
8008dae: 683a ldr r2, [r7, #0]
8008db0: 7812 ldrb r2, [r2, #0]
8008db2: 0151 lsls r1, r2, #5
8008db4: 693a ldr r2, [r7, #16]
8008db6: 440a add r2, r1
8008db8: f502 6210 add.w r2, r2, #2304 @ 0x900
8008dbc: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
8008dc0: 6013 str r3, [r2, #0]
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
8008dc2: 683b ldr r3, [r7, #0]
8008dc4: 781b ldrb r3, [r3, #0]
8008dc6: 015a lsls r2, r3, #5
8008dc8: 693b ldr r3, [r7, #16]
8008dca: 4413 add r3, r2
8008dcc: f503 6310 add.w r3, r3, #2304 @ 0x900
8008dd0: 681b ldr r3, [r3, #0]
8008dd2: 683a ldr r2, [r7, #0]
8008dd4: 7812 ldrb r2, [r2, #0]
8008dd6: 0151 lsls r1, r2, #5
8008dd8: 693a ldr r2, [r7, #16]
8008dda: 440a add r2, r1
8008ddc: f502 6210 add.w r2, r2, #2304 @ 0x900
8008de0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8008de4: 6013 str r3, [r2, #0]
do
{
count++;
8008de6: 68fb ldr r3, [r7, #12]
8008de8: 3301 adds r3, #1
8008dea: 60fb str r3, [r7, #12]
if (count > 10000U)
8008dec: 68fb ldr r3, [r7, #12]
8008dee: f242 7210 movw r2, #10000 @ 0x2710
8008df2: 4293 cmp r3, r2
8008df4: d902 bls.n 8008dfc <USB_EPStopXfer+0x98>
{
ret = HAL_ERROR;
8008df6: 2301 movs r3, #1
8008df8: 75fb strb r3, [r7, #23]
break;
8008dfa: e056 b.n 8008eaa <USB_EPStopXfer+0x146>
}
} while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
8008dfc: 683b ldr r3, [r7, #0]
8008dfe: 781b ldrb r3, [r3, #0]
8008e00: 015a lsls r2, r3, #5
8008e02: 693b ldr r3, [r7, #16]
8008e04: 4413 add r3, r2
8008e06: f503 6310 add.w r3, r3, #2304 @ 0x900
8008e0a: 681b ldr r3, [r3, #0]
8008e0c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8008e10: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8008e14: d0e7 beq.n 8008de6 <USB_EPStopXfer+0x82>
8008e16: e048 b.n 8008eaa <USB_EPStopXfer+0x146>
}
}
else /* OUT endpoint */
{
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
8008e18: 683b ldr r3, [r7, #0]
8008e1a: 781b ldrb r3, [r3, #0]
8008e1c: 015a lsls r2, r3, #5
8008e1e: 693b ldr r3, [r7, #16]
8008e20: 4413 add r3, r2
8008e22: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008e26: 681b ldr r3, [r3, #0]
8008e28: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8008e2c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8008e30: d13b bne.n 8008eaa <USB_EPStopXfer+0x146>
{
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
8008e32: 683b ldr r3, [r7, #0]
8008e34: 781b ldrb r3, [r3, #0]
8008e36: 015a lsls r2, r3, #5
8008e38: 693b ldr r3, [r7, #16]
8008e3a: 4413 add r3, r2
8008e3c: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008e40: 681b ldr r3, [r3, #0]
8008e42: 683a ldr r2, [r7, #0]
8008e44: 7812 ldrb r2, [r2, #0]
8008e46: 0151 lsls r1, r2, #5
8008e48: 693a ldr r2, [r7, #16]
8008e4a: 440a add r2, r1
8008e4c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008e50: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
8008e54: 6013 str r3, [r2, #0]
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
8008e56: 683b ldr r3, [r7, #0]
8008e58: 781b ldrb r3, [r3, #0]
8008e5a: 015a lsls r2, r3, #5
8008e5c: 693b ldr r3, [r7, #16]
8008e5e: 4413 add r3, r2
8008e60: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008e64: 681b ldr r3, [r3, #0]
8008e66: 683a ldr r2, [r7, #0]
8008e68: 7812 ldrb r2, [r2, #0]
8008e6a: 0151 lsls r1, r2, #5
8008e6c: 693a ldr r2, [r7, #16]
8008e6e: 440a add r2, r1
8008e70: f502 6230 add.w r2, r2, #2816 @ 0xb00
8008e74: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8008e78: 6013 str r3, [r2, #0]
do
{
count++;
8008e7a: 68fb ldr r3, [r7, #12]
8008e7c: 3301 adds r3, #1
8008e7e: 60fb str r3, [r7, #12]
if (count > 10000U)
8008e80: 68fb ldr r3, [r7, #12]
8008e82: f242 7210 movw r2, #10000 @ 0x2710
8008e86: 4293 cmp r3, r2
8008e88: d902 bls.n 8008e90 <USB_EPStopXfer+0x12c>
{
ret = HAL_ERROR;
8008e8a: 2301 movs r3, #1
8008e8c: 75fb strb r3, [r7, #23]
break;
8008e8e: e00c b.n 8008eaa <USB_EPStopXfer+0x146>
}
} while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
8008e90: 683b ldr r3, [r7, #0]
8008e92: 781b ldrb r3, [r3, #0]
8008e94: 015a lsls r2, r3, #5
8008e96: 693b ldr r3, [r7, #16]
8008e98: 4413 add r3, r2
8008e9a: f503 6330 add.w r3, r3, #2816 @ 0xb00
8008e9e: 681b ldr r3, [r3, #0]
8008ea0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8008ea4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8008ea8: d0e7 beq.n 8008e7a <USB_EPStopXfer+0x116>
}
}
return ret;
8008eaa: 7dfb ldrb r3, [r7, #23]
}
8008eac: 4618 mov r0, r3
8008eae: 371c adds r7, #28
8008eb0: 46bd mov sp, r7
8008eb2: f85d 7b04 ldr.w r7, [sp], #4
8008eb6: 4770 bx lr
08008eb8 <USB_WritePacket>:
* @param len Number of bytes to write
* @retval HAL status
*/
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len)
{
8008eb8: b480 push {r7}
8008eba: b089 sub sp, #36 @ 0x24
8008ebc: af00 add r7, sp, #0
8008ebe: 60f8 str r0, [r7, #12]
8008ec0: 60b9 str r1, [r7, #8]
8008ec2: 4611 mov r1, r2
8008ec4: 461a mov r2, r3
8008ec6: 460b mov r3, r1
8008ec8: 71fb strb r3, [r7, #7]
8008eca: 4613 mov r3, r2
8008ecc: 80bb strh r3, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
8008ece: 68fb ldr r3, [r7, #12]
8008ed0: 617b str r3, [r7, #20]
uint8_t *pSrc = src;
8008ed2: 68bb ldr r3, [r7, #8]
8008ed4: 61fb str r3, [r7, #28]
uint32_t count32b;
uint32_t i;
count32b = ((uint32_t)len + 3U) / 4U;
8008ed6: 88bb ldrh r3, [r7, #4]
8008ed8: 3303 adds r3, #3
8008eda: 089b lsrs r3, r3, #2
8008edc: 613b str r3, [r7, #16]
for (i = 0U; i < count32b; i++)
8008ede: 2300 movs r3, #0
8008ee0: 61bb str r3, [r7, #24]
8008ee2: e018 b.n 8008f16 <USB_WritePacket+0x5e>
{
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
8008ee4: 79fb ldrb r3, [r7, #7]
8008ee6: 031a lsls r2, r3, #12
8008ee8: 697b ldr r3, [r7, #20]
8008eea: 4413 add r3, r2
8008eec: f503 5380 add.w r3, r3, #4096 @ 0x1000
8008ef0: 461a mov r2, r3
8008ef2: 69fb ldr r3, [r7, #28]
8008ef4: 681b ldr r3, [r3, #0]
8008ef6: 6013 str r3, [r2, #0]
pSrc++;
8008ef8: 69fb ldr r3, [r7, #28]
8008efa: 3301 adds r3, #1
8008efc: 61fb str r3, [r7, #28]
pSrc++;
8008efe: 69fb ldr r3, [r7, #28]
8008f00: 3301 adds r3, #1
8008f02: 61fb str r3, [r7, #28]
pSrc++;
8008f04: 69fb ldr r3, [r7, #28]
8008f06: 3301 adds r3, #1
8008f08: 61fb str r3, [r7, #28]
pSrc++;
8008f0a: 69fb ldr r3, [r7, #28]
8008f0c: 3301 adds r3, #1
8008f0e: 61fb str r3, [r7, #28]
for (i = 0U; i < count32b; i++)
8008f10: 69bb ldr r3, [r7, #24]
8008f12: 3301 adds r3, #1
8008f14: 61bb str r3, [r7, #24]
8008f16: 69ba ldr r2, [r7, #24]
8008f18: 693b ldr r3, [r7, #16]
8008f1a: 429a cmp r2, r3
8008f1c: d3e2 bcc.n 8008ee4 <USB_WritePacket+0x2c>
}
return HAL_OK;
8008f1e: 2300 movs r3, #0
}
8008f20: 4618 mov r0, r3
8008f22: 3724 adds r7, #36 @ 0x24
8008f24: 46bd mov sp, r7
8008f26: f85d 7b04 ldr.w r7, [sp], #4
8008f2a: 4770 bx lr
08008f2c <USB_ReadPacket>:
* @param dest source pointer
* @param len Number of bytes to read
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
8008f2c: b480 push {r7}
8008f2e: b08b sub sp, #44 @ 0x2c
8008f30: af00 add r7, sp, #0
8008f32: 60f8 str r0, [r7, #12]
8008f34: 60b9 str r1, [r7, #8]
8008f36: 4613 mov r3, r2
8008f38: 80fb strh r3, [r7, #6]
uint32_t USBx_BASE = (uint32_t)USBx;
8008f3a: 68fb ldr r3, [r7, #12]
8008f3c: 61bb str r3, [r7, #24]
uint8_t *pDest = dest;
8008f3e: 68bb ldr r3, [r7, #8]
8008f40: 627b str r3, [r7, #36] @ 0x24
uint32_t pData;
uint32_t i;
uint32_t count32b = (uint32_t)len >> 2U;
8008f42: 88fb ldrh r3, [r7, #6]
8008f44: 089b lsrs r3, r3, #2
8008f46: b29b uxth r3, r3
8008f48: 617b str r3, [r7, #20]
uint16_t remaining_bytes = len % 4U;
8008f4a: 88fb ldrh r3, [r7, #6]
8008f4c: f003 0303 and.w r3, r3, #3
8008f50: 83fb strh r3, [r7, #30]
for (i = 0U; i < count32b; i++)
8008f52: 2300 movs r3, #0
8008f54: 623b str r3, [r7, #32]
8008f56: e014 b.n 8008f82 <USB_ReadPacket+0x56>
{
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
8008f58: 69bb ldr r3, [r7, #24]
8008f5a: f503 5380 add.w r3, r3, #4096 @ 0x1000
8008f5e: 681a ldr r2, [r3, #0]
8008f60: 6a7b ldr r3, [r7, #36] @ 0x24
8008f62: 601a str r2, [r3, #0]
pDest++;
8008f64: 6a7b ldr r3, [r7, #36] @ 0x24
8008f66: 3301 adds r3, #1
8008f68: 627b str r3, [r7, #36] @ 0x24
pDest++;
8008f6a: 6a7b ldr r3, [r7, #36] @ 0x24
8008f6c: 3301 adds r3, #1
8008f6e: 627b str r3, [r7, #36] @ 0x24
pDest++;
8008f70: 6a7b ldr r3, [r7, #36] @ 0x24
8008f72: 3301 adds r3, #1
8008f74: 627b str r3, [r7, #36] @ 0x24
pDest++;
8008f76: 6a7b ldr r3, [r7, #36] @ 0x24
8008f78: 3301 adds r3, #1
8008f7a: 627b str r3, [r7, #36] @ 0x24
for (i = 0U; i < count32b; i++)
8008f7c: 6a3b ldr r3, [r7, #32]
8008f7e: 3301 adds r3, #1
8008f80: 623b str r3, [r7, #32]
8008f82: 6a3a ldr r2, [r7, #32]
8008f84: 697b ldr r3, [r7, #20]
8008f86: 429a cmp r2, r3
8008f88: d3e6 bcc.n 8008f58 <USB_ReadPacket+0x2c>
}
/* When Number of data is not word aligned, read the remaining byte */
if (remaining_bytes != 0U)
8008f8a: 8bfb ldrh r3, [r7, #30]
8008f8c: 2b00 cmp r3, #0
8008f8e: d01e beq.n 8008fce <USB_ReadPacket+0xa2>
{
i = 0U;
8008f90: 2300 movs r3, #0
8008f92: 623b str r3, [r7, #32]
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
8008f94: 69bb ldr r3, [r7, #24]
8008f96: f503 5380 add.w r3, r3, #4096 @ 0x1000
8008f9a: 461a mov r2, r3
8008f9c: f107 0310 add.w r3, r7, #16
8008fa0: 6812 ldr r2, [r2, #0]
8008fa2: 601a str r2, [r3, #0]
do
{
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
8008fa4: 693a ldr r2, [r7, #16]
8008fa6: 6a3b ldr r3, [r7, #32]
8008fa8: b2db uxtb r3, r3
8008faa: 00db lsls r3, r3, #3
8008fac: fa22 f303 lsr.w r3, r2, r3
8008fb0: b2da uxtb r2, r3
8008fb2: 6a7b ldr r3, [r7, #36] @ 0x24
8008fb4: 701a strb r2, [r3, #0]
i++;
8008fb6: 6a3b ldr r3, [r7, #32]
8008fb8: 3301 adds r3, #1
8008fba: 623b str r3, [r7, #32]
pDest++;
8008fbc: 6a7b ldr r3, [r7, #36] @ 0x24
8008fbe: 3301 adds r3, #1
8008fc0: 627b str r3, [r7, #36] @ 0x24
remaining_bytes--;
8008fc2: 8bfb ldrh r3, [r7, #30]
8008fc4: 3b01 subs r3, #1
8008fc6: 83fb strh r3, [r7, #30]
} while (remaining_bytes != 0U);
8008fc8: 8bfb ldrh r3, [r7, #30]
8008fca: 2b00 cmp r3, #0
8008fcc: d1ea bne.n 8008fa4 <USB_ReadPacket+0x78>
}
return ((void *)pDest);
8008fce: 6a7b ldr r3, [r7, #36] @ 0x24
}
8008fd0: 4618 mov r0, r3
8008fd2: 372c adds r7, #44 @ 0x2c
8008fd4: 46bd mov sp, r7
8008fd6: f85d 7b04 ldr.w r7, [sp], #4
8008fda: 4770 bx lr
08008fdc <USB_EPSetStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
8008fdc: b480 push {r7}
8008fde: b085 sub sp, #20
8008fe0: af00 add r7, sp, #0
8008fe2: 6078 str r0, [r7, #4]
8008fe4: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
8008fe6: 687b ldr r3, [r7, #4]
8008fe8: 60fb str r3, [r7, #12]
uint32_t epnum = (uint32_t)ep->num;
8008fea: 683b ldr r3, [r7, #0]
8008fec: 781b ldrb r3, [r3, #0]
8008fee: 60bb str r3, [r7, #8]
if (ep->is_in == 1U)
8008ff0: 683b ldr r3, [r7, #0]
8008ff2: 785b ldrb r3, [r3, #1]
8008ff4: 2b01 cmp r3, #1
8008ff6: d12c bne.n 8009052 <USB_EPSetStall+0x76>
{
if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
8008ff8: 68bb ldr r3, [r7, #8]
8008ffa: 015a lsls r2, r3, #5
8008ffc: 68fb ldr r3, [r7, #12]
8008ffe: 4413 add r3, r2
8009000: f503 6310 add.w r3, r3, #2304 @ 0x900
8009004: 681b ldr r3, [r3, #0]
8009006: 2b00 cmp r3, #0
8009008: db12 blt.n 8009030 <USB_EPSetStall+0x54>
800900a: 68bb ldr r3, [r7, #8]
800900c: 2b00 cmp r3, #0
800900e: d00f beq.n 8009030 <USB_EPSetStall+0x54>
{
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
8009010: 68bb ldr r3, [r7, #8]
8009012: 015a lsls r2, r3, #5
8009014: 68fb ldr r3, [r7, #12]
8009016: 4413 add r3, r2
8009018: f503 6310 add.w r3, r3, #2304 @ 0x900
800901c: 681b ldr r3, [r3, #0]
800901e: 68ba ldr r2, [r7, #8]
8009020: 0151 lsls r1, r2, #5
8009022: 68fa ldr r2, [r7, #12]
8009024: 440a add r2, r1
8009026: f502 6210 add.w r2, r2, #2304 @ 0x900
800902a: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
800902e: 6013 str r3, [r2, #0]
}
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
8009030: 68bb ldr r3, [r7, #8]
8009032: 015a lsls r2, r3, #5
8009034: 68fb ldr r3, [r7, #12]
8009036: 4413 add r3, r2
8009038: f503 6310 add.w r3, r3, #2304 @ 0x900
800903c: 681b ldr r3, [r3, #0]
800903e: 68ba ldr r2, [r7, #8]
8009040: 0151 lsls r1, r2, #5
8009042: 68fa ldr r2, [r7, #12]
8009044: 440a add r2, r1
8009046: f502 6210 add.w r2, r2, #2304 @ 0x900
800904a: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
800904e: 6013 str r3, [r2, #0]
8009050: e02b b.n 80090aa <USB_EPSetStall+0xce>
}
else
{
if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
8009052: 68bb ldr r3, [r7, #8]
8009054: 015a lsls r2, r3, #5
8009056: 68fb ldr r3, [r7, #12]
8009058: 4413 add r3, r2
800905a: f503 6330 add.w r3, r3, #2816 @ 0xb00
800905e: 681b ldr r3, [r3, #0]
8009060: 2b00 cmp r3, #0
8009062: db12 blt.n 800908a <USB_EPSetStall+0xae>
8009064: 68bb ldr r3, [r7, #8]
8009066: 2b00 cmp r3, #0
8009068: d00f beq.n 800908a <USB_EPSetStall+0xae>
{
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
800906a: 68bb ldr r3, [r7, #8]
800906c: 015a lsls r2, r3, #5
800906e: 68fb ldr r3, [r7, #12]
8009070: 4413 add r3, r2
8009072: f503 6330 add.w r3, r3, #2816 @ 0xb00
8009076: 681b ldr r3, [r3, #0]
8009078: 68ba ldr r2, [r7, #8]
800907a: 0151 lsls r1, r2, #5
800907c: 68fa ldr r2, [r7, #12]
800907e: 440a add r2, r1
8009080: f502 6230 add.w r2, r2, #2816 @ 0xb00
8009084: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
8009088: 6013 str r3, [r2, #0]
}
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
800908a: 68bb ldr r3, [r7, #8]
800908c: 015a lsls r2, r3, #5
800908e: 68fb ldr r3, [r7, #12]
8009090: 4413 add r3, r2
8009092: f503 6330 add.w r3, r3, #2816 @ 0xb00
8009096: 681b ldr r3, [r3, #0]
8009098: 68ba ldr r2, [r7, #8]
800909a: 0151 lsls r1, r2, #5
800909c: 68fa ldr r2, [r7, #12]
800909e: 440a add r2, r1
80090a0: f502 6230 add.w r2, r2, #2816 @ 0xb00
80090a4: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
80090a8: 6013 str r3, [r2, #0]
}
return HAL_OK;
80090aa: 2300 movs r3, #0
}
80090ac: 4618 mov r0, r3
80090ae: 3714 adds r7, #20
80090b0: 46bd mov sp, r7
80090b2: f85d 7b04 ldr.w r7, [sp], #4
80090b6: 4770 bx lr
080090b8 <USB_EPClearStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
80090b8: b480 push {r7}
80090ba: b085 sub sp, #20
80090bc: af00 add r7, sp, #0
80090be: 6078 str r0, [r7, #4]
80090c0: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
80090c2: 687b ldr r3, [r7, #4]
80090c4: 60fb str r3, [r7, #12]
uint32_t epnum = (uint32_t)ep->num;
80090c6: 683b ldr r3, [r7, #0]
80090c8: 781b ldrb r3, [r3, #0]
80090ca: 60bb str r3, [r7, #8]
if (ep->is_in == 1U)
80090cc: 683b ldr r3, [r7, #0]
80090ce: 785b ldrb r3, [r3, #1]
80090d0: 2b01 cmp r3, #1
80090d2: d128 bne.n 8009126 <USB_EPClearStall+0x6e>
{
USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
80090d4: 68bb ldr r3, [r7, #8]
80090d6: 015a lsls r2, r3, #5
80090d8: 68fb ldr r3, [r7, #12]
80090da: 4413 add r3, r2
80090dc: f503 6310 add.w r3, r3, #2304 @ 0x900
80090e0: 681b ldr r3, [r3, #0]
80090e2: 68ba ldr r2, [r7, #8]
80090e4: 0151 lsls r1, r2, #5
80090e6: 68fa ldr r2, [r7, #12]
80090e8: 440a add r2, r1
80090ea: f502 6210 add.w r2, r2, #2304 @ 0x900
80090ee: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
80090f2: 6013 str r3, [r2, #0]
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
80090f4: 683b ldr r3, [r7, #0]
80090f6: 791b ldrb r3, [r3, #4]
80090f8: 2b03 cmp r3, #3
80090fa: d003 beq.n 8009104 <USB_EPClearStall+0x4c>
80090fc: 683b ldr r3, [r7, #0]
80090fe: 791b ldrb r3, [r3, #4]
8009100: 2b02 cmp r3, #2
8009102: d138 bne.n 8009176 <USB_EPClearStall+0xbe>
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
8009104: 68bb ldr r3, [r7, #8]
8009106: 015a lsls r2, r3, #5
8009108: 68fb ldr r3, [r7, #12]
800910a: 4413 add r3, r2
800910c: f503 6310 add.w r3, r3, #2304 @ 0x900
8009110: 681b ldr r3, [r3, #0]
8009112: 68ba ldr r2, [r7, #8]
8009114: 0151 lsls r1, r2, #5
8009116: 68fa ldr r2, [r7, #12]
8009118: 440a add r2, r1
800911a: f502 6210 add.w r2, r2, #2304 @ 0x900
800911e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8009122: 6013 str r3, [r2, #0]
8009124: e027 b.n 8009176 <USB_EPClearStall+0xbe>
}
}
else
{
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
8009126: 68bb ldr r3, [r7, #8]
8009128: 015a lsls r2, r3, #5
800912a: 68fb ldr r3, [r7, #12]
800912c: 4413 add r3, r2
800912e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8009132: 681b ldr r3, [r3, #0]
8009134: 68ba ldr r2, [r7, #8]
8009136: 0151 lsls r1, r2, #5
8009138: 68fa ldr r2, [r7, #12]
800913a: 440a add r2, r1
800913c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8009140: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8009144: 6013 str r3, [r2, #0]
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
8009146: 683b ldr r3, [r7, #0]
8009148: 791b ldrb r3, [r3, #4]
800914a: 2b03 cmp r3, #3
800914c: d003 beq.n 8009156 <USB_EPClearStall+0x9e>
800914e: 683b ldr r3, [r7, #0]
8009150: 791b ldrb r3, [r3, #4]
8009152: 2b02 cmp r3, #2
8009154: d10f bne.n 8009176 <USB_EPClearStall+0xbe>
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
8009156: 68bb ldr r3, [r7, #8]
8009158: 015a lsls r2, r3, #5
800915a: 68fb ldr r3, [r7, #12]
800915c: 4413 add r3, r2
800915e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8009162: 681b ldr r3, [r3, #0]
8009164: 68ba ldr r2, [r7, #8]
8009166: 0151 lsls r1, r2, #5
8009168: 68fa ldr r2, [r7, #12]
800916a: 440a add r2, r1
800916c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8009170: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8009174: 6013 str r3, [r2, #0]
}
}
return HAL_OK;
8009176: 2300 movs r3, #0
}
8009178: 4618 mov r0, r3
800917a: 3714 adds r7, #20
800917c: 46bd mov sp, r7
800917e: f85d 7b04 ldr.w r7, [sp], #4
8009182: 4770 bx lr
08009184 <USB_SetDevAddress>:
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
8009184: b480 push {r7}
8009186: b085 sub sp, #20
8009188: af00 add r7, sp, #0
800918a: 6078 str r0, [r7, #4]
800918c: 460b mov r3, r1
800918e: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
8009190: 687b ldr r3, [r7, #4]
8009192: 60fb str r3, [r7, #12]
USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
8009194: 68fb ldr r3, [r7, #12]
8009196: f503 6300 add.w r3, r3, #2048 @ 0x800
800919a: 681b ldr r3, [r3, #0]
800919c: 68fa ldr r2, [r7, #12]
800919e: f502 6200 add.w r2, r2, #2048 @ 0x800
80091a2: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
80091a6: 6013 str r3, [r2, #0]
USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
80091a8: 68fb ldr r3, [r7, #12]
80091aa: f503 6300 add.w r3, r3, #2048 @ 0x800
80091ae: 681a ldr r2, [r3, #0]
80091b0: 78fb ldrb r3, [r7, #3]
80091b2: 011b lsls r3, r3, #4
80091b4: f403 63fe and.w r3, r3, #2032 @ 0x7f0
80091b8: 68f9 ldr r1, [r7, #12]
80091ba: f501 6100 add.w r1, r1, #2048 @ 0x800
80091be: 4313 orrs r3, r2
80091c0: 600b str r3, [r1, #0]
return HAL_OK;
80091c2: 2300 movs r3, #0
}
80091c4: 4618 mov r0, r3
80091c6: 3714 adds r7, #20
80091c8: 46bd mov sp, r7
80091ca: f85d 7b04 ldr.w r7, [sp], #4
80091ce: 4770 bx lr
080091d0 <USB_DevConnect>:
* @brief USB_DevConnect : Connect the USB device by enabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
{
80091d0: b480 push {r7}
80091d2: b085 sub sp, #20
80091d4: af00 add r7, sp, #0
80091d6: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
80091d8: 687b ldr r3, [r7, #4]
80091da: 60fb str r3, [r7, #12]
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
80091dc: 68fb ldr r3, [r7, #12]
80091de: f503 6360 add.w r3, r3, #3584 @ 0xe00
80091e2: 681b ldr r3, [r3, #0]
80091e4: 68fa ldr r2, [r7, #12]
80091e6: f502 6260 add.w r2, r2, #3584 @ 0xe00
80091ea: f023 0303 bic.w r3, r3, #3
80091ee: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
80091f0: 68fb ldr r3, [r7, #12]
80091f2: f503 6300 add.w r3, r3, #2048 @ 0x800
80091f6: 685b ldr r3, [r3, #4]
80091f8: 68fa ldr r2, [r7, #12]
80091fa: f502 6200 add.w r2, r2, #2048 @ 0x800
80091fe: f023 0302 bic.w r3, r3, #2
8009202: 6053 str r3, [r2, #4]
return HAL_OK;
8009204: 2300 movs r3, #0
}
8009206: 4618 mov r0, r3
8009208: 3714 adds r7, #20
800920a: 46bd mov sp, r7
800920c: f85d 7b04 ldr.w r7, [sp], #4
8009210: 4770 bx lr
08009212 <USB_DevDisconnect>:
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
8009212: b480 push {r7}
8009214: b085 sub sp, #20
8009216: af00 add r7, sp, #0
8009218: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
800921a: 687b ldr r3, [r7, #4]
800921c: 60fb str r3, [r7, #12]
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
800921e: 68fb ldr r3, [r7, #12]
8009220: f503 6360 add.w r3, r3, #3584 @ 0xe00
8009224: 681b ldr r3, [r3, #0]
8009226: 68fa ldr r2, [r7, #12]
8009228: f502 6260 add.w r2, r2, #3584 @ 0xe00
800922c: f023 0303 bic.w r3, r3, #3
8009230: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
8009232: 68fb ldr r3, [r7, #12]
8009234: f503 6300 add.w r3, r3, #2048 @ 0x800
8009238: 685b ldr r3, [r3, #4]
800923a: 68fa ldr r2, [r7, #12]
800923c: f502 6200 add.w r2, r2, #2048 @ 0x800
8009240: f043 0302 orr.w r3, r3, #2
8009244: 6053 str r3, [r2, #4]
return HAL_OK;
8009246: 2300 movs r3, #0
}
8009248: 4618 mov r0, r3
800924a: 3714 adds r7, #20
800924c: 46bd mov sp, r7
800924e: f85d 7b04 ldr.w r7, [sp], #4
8009252: 4770 bx lr
08009254 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts: return the global USB interrupt status
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
{
8009254: b480 push {r7}
8009256: b085 sub sp, #20
8009258: af00 add r7, sp, #0
800925a: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->GINTSTS;
800925c: 687b ldr r3, [r7, #4]
800925e: 695b ldr r3, [r3, #20]
8009260: 60fb str r3, [r7, #12]
tmpreg &= USBx->GINTMSK;
8009262: 687b ldr r3, [r7, #4]
8009264: 699b ldr r3, [r3, #24]
8009266: 68fa ldr r2, [r7, #12]
8009268: 4013 ands r3, r2
800926a: 60fb str r3, [r7, #12]
return tmpreg;
800926c: 68fb ldr r3, [r7, #12]
}
800926e: 4618 mov r0, r3
8009270: 3714 adds r7, #20
8009272: 46bd mov sp, r7
8009274: f85d 7b04 ldr.w r7, [sp], #4
8009278: 4770 bx lr
0800927a <USB_ReadDevAllOutEpInterrupt>:
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
* @param USBx Selected device
* @retval USB Device OUT EP interrupt status
*/
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
800927a: b480 push {r7}
800927c: b085 sub sp, #20
800927e: af00 add r7, sp, #0
8009280: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
8009282: 687b ldr r3, [r7, #4]
8009284: 60fb str r3, [r7, #12]
uint32_t tmpreg;
tmpreg = USBx_DEVICE->DAINT;
8009286: 68fb ldr r3, [r7, #12]
8009288: f503 6300 add.w r3, r3, #2048 @ 0x800
800928c: 699b ldr r3, [r3, #24]
800928e: 60bb str r3, [r7, #8]
tmpreg &= USBx_DEVICE->DAINTMSK;
8009290: 68fb ldr r3, [r7, #12]
8009292: f503 6300 add.w r3, r3, #2048 @ 0x800
8009296: 69db ldr r3, [r3, #28]
8009298: 68ba ldr r2, [r7, #8]
800929a: 4013 ands r3, r2
800929c: 60bb str r3, [r7, #8]
return ((tmpreg & 0xffff0000U) >> 16);
800929e: 68bb ldr r3, [r7, #8]
80092a0: 0c1b lsrs r3, r3, #16
}
80092a2: 4618 mov r0, r3
80092a4: 3714 adds r7, #20
80092a6: 46bd mov sp, r7
80092a8: f85d 7b04 ldr.w r7, [sp], #4
80092ac: 4770 bx lr
080092ae <USB_ReadDevAllInEpInterrupt>:
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
* @param USBx Selected device
* @retval USB Device IN EP interrupt status
*/
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
80092ae: b480 push {r7}
80092b0: b085 sub sp, #20
80092b2: af00 add r7, sp, #0
80092b4: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
80092b6: 687b ldr r3, [r7, #4]
80092b8: 60fb str r3, [r7, #12]
uint32_t tmpreg;
tmpreg = USBx_DEVICE->DAINT;
80092ba: 68fb ldr r3, [r7, #12]
80092bc: f503 6300 add.w r3, r3, #2048 @ 0x800
80092c0: 699b ldr r3, [r3, #24]
80092c2: 60bb str r3, [r7, #8]
tmpreg &= USBx_DEVICE->DAINTMSK;
80092c4: 68fb ldr r3, [r7, #12]
80092c6: f503 6300 add.w r3, r3, #2048 @ 0x800
80092ca: 69db ldr r3, [r3, #28]
80092cc: 68ba ldr r2, [r7, #8]
80092ce: 4013 ands r3, r2
80092d0: 60bb str r3, [r7, #8]
return ((tmpreg & 0xFFFFU));
80092d2: 68bb ldr r3, [r7, #8]
80092d4: b29b uxth r3, r3
}
80092d6: 4618 mov r0, r3
80092d8: 3714 adds r7, #20
80092da: 46bd mov sp, r7
80092dc: f85d 7b04 ldr.w r7, [sp], #4
80092e0: 4770 bx lr
080092e2 <USB_ReadDevOutEPInterrupt>:
* @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
80092e2: b480 push {r7}
80092e4: b085 sub sp, #20
80092e6: af00 add r7, sp, #0
80092e8: 6078 str r0, [r7, #4]
80092ea: 460b mov r3, r1
80092ec: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
80092ee: 687b ldr r3, [r7, #4]
80092f0: 60fb str r3, [r7, #12]
uint32_t tmpreg;
tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
80092f2: 78fb ldrb r3, [r7, #3]
80092f4: 015a lsls r2, r3, #5
80092f6: 68fb ldr r3, [r7, #12]
80092f8: 4413 add r3, r2
80092fa: f503 6330 add.w r3, r3, #2816 @ 0xb00
80092fe: 689b ldr r3, [r3, #8]
8009300: 60bb str r3, [r7, #8]
tmpreg &= USBx_DEVICE->DOEPMSK;
8009302: 68fb ldr r3, [r7, #12]
8009304: f503 6300 add.w r3, r3, #2048 @ 0x800
8009308: 695b ldr r3, [r3, #20]
800930a: 68ba ldr r2, [r7, #8]
800930c: 4013 ands r3, r2
800930e: 60bb str r3, [r7, #8]
return tmpreg;
8009310: 68bb ldr r3, [r7, #8]
}
8009312: 4618 mov r0, r3
8009314: 3714 adds r7, #20
8009316: 46bd mov sp, r7
8009318: f85d 7b04 ldr.w r7, [sp], #4
800931c: 4770 bx lr
0800931e <USB_ReadDevInEPInterrupt>:
* @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
800931e: b480 push {r7}
8009320: b087 sub sp, #28
8009322: af00 add r7, sp, #0
8009324: 6078 str r0, [r7, #4]
8009326: 460b mov r3, r1
8009328: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
800932a: 687b ldr r3, [r7, #4]
800932c: 617b str r3, [r7, #20]
uint32_t tmpreg;
uint32_t msk;
uint32_t emp;
msk = USBx_DEVICE->DIEPMSK;
800932e: 697b ldr r3, [r7, #20]
8009330: f503 6300 add.w r3, r3, #2048 @ 0x800
8009334: 691b ldr r3, [r3, #16]
8009336: 613b str r3, [r7, #16]
emp = USBx_DEVICE->DIEPEMPMSK;
8009338: 697b ldr r3, [r7, #20]
800933a: f503 6300 add.w r3, r3, #2048 @ 0x800
800933e: 6b5b ldr r3, [r3, #52] @ 0x34
8009340: 60fb str r3, [r7, #12]
msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
8009342: 78fb ldrb r3, [r7, #3]
8009344: f003 030f and.w r3, r3, #15
8009348: 68fa ldr r2, [r7, #12]
800934a: fa22 f303 lsr.w r3, r2, r3
800934e: 01db lsls r3, r3, #7
8009350: b2db uxtb r3, r3
8009352: 693a ldr r2, [r7, #16]
8009354: 4313 orrs r3, r2
8009356: 613b str r3, [r7, #16]
tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
8009358: 78fb ldrb r3, [r7, #3]
800935a: 015a lsls r2, r3, #5
800935c: 697b ldr r3, [r7, #20]
800935e: 4413 add r3, r2
8009360: f503 6310 add.w r3, r3, #2304 @ 0x900
8009364: 689b ldr r3, [r3, #8]
8009366: 693a ldr r2, [r7, #16]
8009368: 4013 ands r3, r2
800936a: 60bb str r3, [r7, #8]
return tmpreg;
800936c: 68bb ldr r3, [r7, #8]
}
800936e: 4618 mov r0, r3
8009370: 371c adds r7, #28
8009372: 46bd mov sp, r7
8009374: f85d 7b04 ldr.w r7, [sp], #4
8009378: 4770 bx lr
0800937a <USB_GetMode>:
* This parameter can be one of these values:
* 0 : Host
* 1 : Device
*/
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
800937a: b480 push {r7}
800937c: b083 sub sp, #12
800937e: af00 add r7, sp, #0
8009380: 6078 str r0, [r7, #4]
return ((USBx->GINTSTS) & 0x1U);
8009382: 687b ldr r3, [r7, #4]
8009384: 695b ldr r3, [r3, #20]
8009386: f003 0301 and.w r3, r3, #1
}
800938a: 4618 mov r0, r3
800938c: 370c adds r7, #12
800938e: 46bd mov sp, r7
8009390: f85d 7b04 ldr.w r7, [sp], #4
8009394: 4770 bx lr
08009396 <USB_ActivateSetup>:
* @brief Activate EP0 for Setup transactions
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
{
8009396: b480 push {r7}
8009398: b085 sub sp, #20
800939a: af00 add r7, sp, #0
800939c: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
800939e: 687b ldr r3, [r7, #4]
80093a0: 60fb str r3, [r7, #12]
/* Set the MPS of the IN EP0 to 64 bytes */
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
80093a2: 68fb ldr r3, [r7, #12]
80093a4: f503 6310 add.w r3, r3, #2304 @ 0x900
80093a8: 681b ldr r3, [r3, #0]
80093aa: 68fa ldr r2, [r7, #12]
80093ac: f502 6210 add.w r2, r2, #2304 @ 0x900
80093b0: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
80093b4: f023 0307 bic.w r3, r3, #7
80093b8: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
80093ba: 68fb ldr r3, [r7, #12]
80093bc: f503 6300 add.w r3, r3, #2048 @ 0x800
80093c0: 685b ldr r3, [r3, #4]
80093c2: 68fa ldr r2, [r7, #12]
80093c4: f502 6200 add.w r2, r2, #2048 @ 0x800
80093c8: f443 7380 orr.w r3, r3, #256 @ 0x100
80093cc: 6053 str r3, [r2, #4]
return HAL_OK;
80093ce: 2300 movs r3, #0
}
80093d0: 4618 mov r0, r3
80093d2: 3714 adds r7, #20
80093d4: 46bd mov sp, r7
80093d6: f85d 7b04 ldr.w r7, [sp], #4
80093da: 4770 bx lr
080093dc <USB_EP0_OutStart>:
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup)
{
80093dc: b480 push {r7}
80093de: b085 sub sp, #20
80093e0: af00 add r7, sp, #0
80093e2: 6078 str r0, [r7, #4]
80093e4: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
80093e6: 687b ldr r3, [r7, #4]
80093e8: 60fb str r3, [r7, #12]
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
80093ea: 687b ldr r3, [r7, #4]
80093ec: 333c adds r3, #60 @ 0x3c
80093ee: 3304 adds r3, #4
80093f0: 681b ldr r3, [r3, #0]
80093f2: 60bb str r3, [r7, #8]
UNUSED(psetup);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
80093f4: 68bb ldr r3, [r7, #8]
80093f6: 4a1c ldr r2, [pc, #112] @ (8009468 <USB_EP0_OutStart+0x8c>)
80093f8: 4293 cmp r3, r2
80093fa: d90a bls.n 8009412 <USB_EP0_OutStart+0x36>
{
if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
80093fc: 68fb ldr r3, [r7, #12]
80093fe: f503 6330 add.w r3, r3, #2816 @ 0xb00
8009402: 681b ldr r3, [r3, #0]
8009404: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8009408: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
800940c: d101 bne.n 8009412 <USB_EP0_OutStart+0x36>
{
return HAL_OK;
800940e: 2300 movs r3, #0
8009410: e024 b.n 800945c <USB_EP0_OutStart+0x80>
}
}
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
8009412: 68fb ldr r3, [r7, #12]
8009414: f503 6330 add.w r3, r3, #2816 @ 0xb00
8009418: 461a mov r2, r3
800941a: 2300 movs r3, #0
800941c: 6113 str r3, [r2, #16]
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
800941e: 68fb ldr r3, [r7, #12]
8009420: f503 6330 add.w r3, r3, #2816 @ 0xb00
8009424: 691b ldr r3, [r3, #16]
8009426: 68fa ldr r2, [r7, #12]
8009428: f502 6230 add.w r2, r2, #2816 @ 0xb00
800942c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8009430: 6113 str r3, [r2, #16]
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
8009432: 68fb ldr r3, [r7, #12]
8009434: f503 6330 add.w r3, r3, #2816 @ 0xb00
8009438: 691b ldr r3, [r3, #16]
800943a: 68fa ldr r2, [r7, #12]
800943c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8009440: f043 0318 orr.w r3, r3, #24
8009444: 6113 str r3, [r2, #16]
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
8009446: 68fb ldr r3, [r7, #12]
8009448: f503 6330 add.w r3, r3, #2816 @ 0xb00
800944c: 691b ldr r3, [r3, #16]
800944e: 68fa ldr r2, [r7, #12]
8009450: f502 6230 add.w r2, r2, #2816 @ 0xb00
8009454: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000
8009458: 6113 str r3, [r2, #16]
return HAL_OK;
800945a: 2300 movs r3, #0
}
800945c: 4618 mov r0, r3
800945e: 3714 adds r7, #20
8009460: 46bd mov sp, r7
8009462: f85d 7b04 ldr.w r7, [sp], #4
8009466: 4770 bx lr
8009468: 4f54300a .word 0x4f54300a
0800946c <USB_CoreReset>:
* @brief Reset the USB Core (needed after USB clock settings change)
* @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
800946c: b480 push {r7}
800946e: b085 sub sp, #20
8009470: af00 add r7, sp, #0
8009472: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8009474: 2300 movs r3, #0
8009476: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8009478: 68fb ldr r3, [r7, #12]
800947a: 3301 adds r3, #1
800947c: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
800947e: 68fb ldr r3, [r7, #12]
8009480: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8009484: d901 bls.n 800948a <USB_CoreReset+0x1e>
{
return HAL_TIMEOUT;
8009486: 2303 movs r3, #3
8009488: e01b b.n 80094c2 <USB_CoreReset+0x56>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
800948a: 687b ldr r3, [r7, #4]
800948c: 691b ldr r3, [r3, #16]
800948e: 2b00 cmp r3, #0
8009490: daf2 bge.n 8009478 <USB_CoreReset+0xc>
/* Core Soft Reset */
count = 0U;
8009492: 2300 movs r3, #0
8009494: 60fb str r3, [r7, #12]
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
8009496: 687b ldr r3, [r7, #4]
8009498: 691b ldr r3, [r3, #16]
800949a: f043 0201 orr.w r2, r3, #1
800949e: 687b ldr r3, [r7, #4]
80094a0: 611a str r2, [r3, #16]
do
{
count++;
80094a2: 68fb ldr r3, [r7, #12]
80094a4: 3301 adds r3, #1
80094a6: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
80094a8: 68fb ldr r3, [r7, #12]
80094aa: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
80094ae: d901 bls.n 80094b4 <USB_CoreReset+0x48>
{
return HAL_TIMEOUT;
80094b0: 2303 movs r3, #3
80094b2: e006 b.n 80094c2 <USB_CoreReset+0x56>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
80094b4: 687b ldr r3, [r7, #4]
80094b6: 691b ldr r3, [r3, #16]
80094b8: f003 0301 and.w r3, r3, #1
80094bc: 2b01 cmp r3, #1
80094be: d0f0 beq.n 80094a2 <USB_CoreReset+0x36>
return HAL_OK;
80094c0: 2300 movs r3, #0
}
80094c2: 4618 mov r0, r3
80094c4: 3714 adds r7, #20
80094c6: 46bd mov sp, r7
80094c8: f85d 7b04 ldr.w r7, [sp], #4
80094cc: 4770 bx lr
...
080094d0 <USBD_CUSTOM_HID_ReceivePacket>:
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CUSTOM_HID_ReceivePacket(USBD_HandleTypeDef *pdev)
{
80094d0: b580 push {r7, lr}
80094d2: b084 sub sp, #16
80094d4: af00 add r7, sp, #0
80094d6: 6078 str r0, [r7, #4]
USBD_CUSTOM_HID_HandleTypeDef *hhid;
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
80094d8: 687b ldr r3, [r7, #4]
80094da: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
80094de: 687b ldr r3, [r7, #4]
80094e0: 32b0 adds r2, #176 @ 0xb0
80094e2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80094e6: 2b00 cmp r3, #0
80094e8: d101 bne.n 80094ee <USBD_CUSTOM_HID_ReceivePacket+0x1e>
{
return (uint8_t)USBD_FAIL;
80094ea: 2303 movs r3, #3
80094ec: e00f b.n 800950e <USBD_CUSTOM_HID_ReceivePacket+0x3e>
#ifdef USE_USBD_COMPOSITE
/* Get OUT Endpoint address allocated for this class instance */
CUSTOMHIDOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
#endif /* USE_USBD_COMPOSITE */
hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
80094ee: 687b ldr r3, [r7, #4]
80094f0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
80094f4: 687b ldr r3, [r7, #4]
80094f6: 32b0 adds r2, #176 @ 0xb0
80094f8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80094fc: 60fb str r3, [r7, #12]
/* Resume USB Out process */
(void)USBD_LL_PrepareReceive(pdev, CUSTOMHIDOutEpAdd, hhid->Report_buf,
80094fe: 4b06 ldr r3, [pc, #24] @ (8009518 <USBD_CUSTOM_HID_ReceivePacket+0x48>)
8009500: 7819 ldrb r1, [r3, #0]
8009502: 68fa ldr r2, [r7, #12]
8009504: 2302 movs r3, #2
8009506: 6878 ldr r0, [r7, #4]
8009508: f002 f902 bl 800b710 <USBD_LL_PrepareReceive>
USBD_CUSTOMHID_OUTREPORT_BUF_SIZE);
return (uint8_t)USBD_OK;
800950c: 2300 movs r3, #0
}
800950e: 4618 mov r0, r3
8009510: 3710 adds r7, #16
8009512: 46bd mov sp, r7
8009514: bd80 pop {r7, pc}
8009516: bf00 nop
8009518: 20000009 .word 0x20000009
0800951c <USBD_CUSTOM_HID_RegisterInterface>:
* @param fops: CUSTOMHID Interface callback
* @retval status
*/
uint8_t USBD_CUSTOM_HID_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CUSTOM_HID_ItfTypeDef *fops)
{
800951c: b480 push {r7}
800951e: b083 sub sp, #12
8009520: af00 add r7, sp, #0
8009522: 6078 str r0, [r7, #4]
8009524: 6039 str r1, [r7, #0]
if (fops == NULL)
8009526: 683b ldr r3, [r7, #0]
8009528: 2b00 cmp r3, #0
800952a: d101 bne.n 8009530 <USBD_CUSTOM_HID_RegisterInterface+0x14>
{
return (uint8_t)USBD_FAIL;
800952c: 2303 movs r3, #3
800952e: e009 b.n 8009544 <USBD_CUSTOM_HID_RegisterInterface+0x28>
}
pdev->pUserData[pdev->classId] = fops;
8009530: 687b ldr r3, [r7, #4]
8009532: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8009536: 687a ldr r2, [r7, #4]
8009538: 33b0 adds r3, #176 @ 0xb0
800953a: 009b lsls r3, r3, #2
800953c: 4413 add r3, r2
800953e: 683a ldr r2, [r7, #0]
8009540: 605a str r2, [r3, #4]
return (uint8_t)USBD_OK;
8009542: 2300 movs r3, #0
}
8009544: 4618 mov r0, r3
8009546: 370c adds r7, #12
8009548: 46bd mov sp, r7
800954a: f85d 7b04 ldr.w r7, [sp], #4
800954e: 4770 bx lr
08009550 <USBD_MIDI_Init>:
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_MIDI_Init (USBD_HandleTypeDef *pdev,
uint8_t cfgidx)
{
8009550: b580 push {r7, lr}
8009552: b084 sub sp, #16
8009554: af00 add r7, sp, #0
8009556: 6078 str r0, [r7, #4]
8009558: 460b mov r3, r1
800955a: 70fb strb r3, [r7, #3]
uint8_t ret = 0;
800955c: 2300 movs r3, #0
800955e: 73fb strb r3, [r7, #15]
USBD_LL_OpenEP(pdev,
8009560: 2340 movs r3, #64 @ 0x40
8009562: 2202 movs r2, #2
8009564: 2181 movs r1, #129 @ 0x81
8009566: 6878 ldr r0, [r7, #4]
8009568: f001 ff58 bl 800b41c <USBD_LL_OpenEP>
MIDI_EPIN_ADDR,
USBD_EP_TYPE_BULK,
MIDI_EPIN_SIZE);
USBD_LL_OpenEP(pdev,
800956c: 2340 movs r3, #64 @ 0x40
800956e: 2202 movs r2, #2
8009570: 2101 movs r1, #1
8009572: 6878 ldr r0, [r7, #4]
8009574: f001 ff52 bl 800b41c <USBD_LL_OpenEP>
MIDI_EPOUT_ADDR,
USBD_EP_TYPE_BULK,
MIDI_EPOUT_SIZE);
USBD_LL_PrepareReceive(pdev,
8009578: 2340 movs r3, #64 @ 0x40
800957a: 4a0f ldr r2, [pc, #60] @ (80095b8 <USBD_MIDI_Init+0x68>)
800957c: 2101 movs r1, #1
800957e: 6878 ldr r0, [r7, #4]
8009580: f002 f8c6 bl 800b710 <USBD_LL_PrepareReceive>
MIDI_EPOUT_ADDR,
usb_rx_buffer,
MIDI_EPOUT_SIZE);
pdev->pClassData = USBD_malloc(sizeof (USBD_MIDI_HandleTypeDef));
8009584: 2010 movs r0, #16
8009586: f002 f949 bl 800b81c <USBD_static_malloc>
800958a: 4602 mov r2, r0
800958c: 687b ldr r3, [r7, #4]
800958e: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
if(pdev->pClassData == NULL)
8009592: 687b ldr r3, [r7, #4]
8009594: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8009598: 2b00 cmp r3, #0
800959a: d102 bne.n 80095a2 <USBD_MIDI_Init+0x52>
{
ret = 1;
800959c: 2301 movs r3, #1
800959e: 73fb strb r3, [r7, #15]
80095a0: e004 b.n 80095ac <USBD_MIDI_Init+0x5c>
}
else
{
((USBD_MIDI_HandleTypeDef *)pdev->pClassData)->state = MIDI_IDLE;
80095a2: 687b ldr r3, [r7, #4]
80095a4: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80095a8: 2200 movs r2, #0
80095aa: 731a strb r2, [r3, #12]
}
return ret;
80095ac: 7bfb ldrb r3, [r7, #15]
}
80095ae: 4618 mov r0, r3
80095b0: 3710 adds r7, #16
80095b2: 46bd mov sp, r7
80095b4: bd80 pop {r7, pc}
80095b6: bf00 nop
80095b8: 2000068c .word 0x2000068c
080095bc <USBD_MIDI_DeInit>:
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_MIDI_DeInit (USBD_HandleTypeDef *pdev,
uint8_t cfgidx)
{
80095bc: b580 push {r7, lr}
80095be: b082 sub sp, #8
80095c0: af00 add r7, sp, #0
80095c2: 6078 str r0, [r7, #4]
80095c4: 460b mov r3, r1
80095c6: 70fb strb r3, [r7, #3]
/* Close MIDI EPs */
USBD_LL_CloseEP(pdev, MIDI_EPIN_SIZE);
80095c8: 2140 movs r1, #64 @ 0x40
80095ca: 6878 ldr r0, [r7, #4]
80095cc: f001 ff64 bl 800b498 <USBD_LL_CloseEP>
/* FRee allocated memory */
if(pdev->pClassData != NULL)
80095d0: 687b ldr r3, [r7, #4]
80095d2: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80095d6: 2b00 cmp r3, #0
80095d8: d009 beq.n 80095ee <USBD_MIDI_DeInit+0x32>
{
USBD_free(pdev->pClassData);
80095da: 687b ldr r3, [r7, #4]
80095dc: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80095e0: 4618 mov r0, r3
80095e2: f002 f929 bl 800b838 <USBD_static_free>
pdev->pClassData = NULL;
80095e6: 687b ldr r3, [r7, #4]
80095e8: 2200 movs r2, #0
80095ea: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
}
return USBD_OK;
80095ee: 2300 movs r3, #0
}
80095f0: 4618 mov r0, r3
80095f2: 3708 adds r7, #8
80095f4: 46bd mov sp, r7
80095f6: bd80 pop {r7, pc}
080095f8 <USBD_MIDI_Setup>:
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_MIDI_Setup (USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
80095f8: b580 push {r7, lr}
80095fa: b086 sub sp, #24
80095fc: af00 add r7, sp, #0
80095fe: 6078 str r0, [r7, #4]
8009600: 6039 str r1, [r7, #0]
uint16_t len = 0;
8009602: 2300 movs r3, #0
8009604: 82fb strh r3, [r7, #22]
uint8_t *pbuf = NULL;
8009606: 2300 movs r3, #0
8009608: 613b str r3, [r7, #16]
USBD_MIDI_HandleTypeDef *hmidi = pdev->pClassData;
800960a: 687b ldr r3, [r7, #4]
800960c: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8009610: 60fb str r3, [r7, #12]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009612: 683b ldr r3, [r7, #0]
8009614: 781b ldrb r3, [r3, #0]
8009616: f003 0360 and.w r3, r3, #96 @ 0x60
800961a: 2b00 cmp r3, #0
800961c: d044 beq.n 80096a8 <USBD_MIDI_Setup+0xb0>
800961e: 2b20 cmp r3, #32
8009620: d171 bne.n 8009706 <USBD_MIDI_Setup+0x10e>
{
case USB_REQ_TYPE_CLASS :
switch (req->bRequest)
8009622: 683b ldr r3, [r7, #0]
8009624: 785b ldrb r3, [r3, #1]
8009626: 3b02 subs r3, #2
8009628: 2b09 cmp r3, #9
800962a: d836 bhi.n 800969a <USBD_MIDI_Setup+0xa2>
800962c: a201 add r2, pc, #4 @ (adr r2, 8009634 <USBD_MIDI_Setup+0x3c>)
800962e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8009632: bf00 nop
8009634: 0800968b .word 0x0800968b
8009638: 0800966b .word 0x0800966b
800963c: 0800969b .word 0x0800969b
8009640: 0800969b .word 0x0800969b
8009644: 0800969b .word 0x0800969b
8009648: 0800969b .word 0x0800969b
800964c: 0800969b .word 0x0800969b
8009650: 0800969b .word 0x0800969b
8009654: 08009679 .word 0x08009679
8009658: 0800965d .word 0x0800965d
{
case MIDI_REQ_SET_PROTOCOL:
hmidi->Protocol = (uint8_t)(req->wValue);
800965c: 683b ldr r3, [r7, #0]
800965e: 885b ldrh r3, [r3, #2]
8009660: b2db uxtb r3, r3
8009662: 461a mov r2, r3
8009664: 68fb ldr r3, [r7, #12]
8009666: 601a str r2, [r3, #0]
break;
8009668: e01d b.n 80096a6 <USBD_MIDI_Setup+0xae>
case MIDI_REQ_GET_PROTOCOL:
USBD_CtlSendData (pdev,
(uint8_t *)&hmidi->Protocol,
800966a: 68fb ldr r3, [r7, #12]
USBD_CtlSendData (pdev,
800966c: 2201 movs r2, #1
800966e: 4619 mov r1, r3
8009670: 6878 ldr r0, [r7, #4]
8009672: f001 fb07 bl 800ac84 <USBD_CtlSendData>
1);
break;
8009676: e016 b.n 80096a6 <USBD_MIDI_Setup+0xae>
case MIDI_REQ_SET_IDLE:
hmidi->IdleState = (uint8_t)(req->wValue >> 8);
8009678: 683b ldr r3, [r7, #0]
800967a: 885b ldrh r3, [r3, #2]
800967c: 0a1b lsrs r3, r3, #8
800967e: b29b uxth r3, r3
8009680: b2db uxtb r3, r3
8009682: 461a mov r2, r3
8009684: 68fb ldr r3, [r7, #12]
8009686: 605a str r2, [r3, #4]
break;
8009688: e00d b.n 80096a6 <USBD_MIDI_Setup+0xae>
case MIDI_REQ_GET_IDLE:
USBD_CtlSendData (pdev,
(uint8_t *)&hmidi->IdleState,
800968a: 68fb ldr r3, [r7, #12]
800968c: 3304 adds r3, #4
USBD_CtlSendData (pdev,
800968e: 2201 movs r2, #1
8009690: 4619 mov r1, r3
8009692: 6878 ldr r0, [r7, #4]
8009694: f001 faf6 bl 800ac84 <USBD_CtlSendData>
1);
break;
8009698: e005 b.n 80096a6 <USBD_MIDI_Setup+0xae>
default:
USBD_CtlError (pdev, req);
800969a: 6839 ldr r1, [r7, #0]
800969c: 6878 ldr r0, [r7, #4]
800969e: f001 fa74 bl 800ab8a <USBD_CtlError>
return USBD_FAIL;
80096a2: 2303 movs r3, #3
80096a4: e030 b.n 8009708 <USBD_MIDI_Setup+0x110>
}
break;
80096a6: e02e b.n 8009706 <USBD_MIDI_Setup+0x10e>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
80096a8: 683b ldr r3, [r7, #0]
80096aa: 785b ldrb r3, [r3, #1]
80096ac: 2b0b cmp r3, #11
80096ae: d023 beq.n 80096f8 <USBD_MIDI_Setup+0x100>
80096b0: 2b0b cmp r3, #11
80096b2: dc28 bgt.n 8009706 <USBD_MIDI_Setup+0x10e>
80096b4: 2b06 cmp r3, #6
80096b6: d002 beq.n 80096be <USBD_MIDI_Setup+0xc6>
80096b8: 2b0a cmp r3, #10
80096ba: d015 beq.n 80096e8 <USBD_MIDI_Setup+0xf0>
80096bc: e023 b.n 8009706 <USBD_MIDI_Setup+0x10e>
{
case USB_REQ_GET_DESCRIPTOR:
if( req->wValue >> 8 == MIDI_DESCRIPTOR_TYPE)
80096be: 683b ldr r3, [r7, #0]
80096c0: 885b ldrh r3, [r3, #2]
80096c2: 0a1b lsrs r3, r3, #8
80096c4: b29b uxth r3, r3
80096c6: 2b21 cmp r3, #33 @ 0x21
80096c8: d107 bne.n 80096da <USBD_MIDI_Setup+0xe2>
{
pbuf = USBD_MIDI_CfgDesc + USB_MIDI_CLASS_DESC_SHIFT;
80096ca: 4b11 ldr r3, [pc, #68] @ (8009710 <USBD_MIDI_Setup+0x118>)
80096cc: 613b str r3, [r7, #16]
len = MIN(USB_MIDI_DESC_SIZE , req->wLength);
80096ce: 683b ldr r3, [r7, #0]
80096d0: 88db ldrh r3, [r3, #6]
80096d2: 2b07 cmp r3, #7
80096d4: bf28 it cs
80096d6: 2307 movcs r3, #7
80096d8: 82fb strh r3, [r7, #22]
}
USBD_CtlSendData (pdev, pbuf, len);
80096da: 8afb ldrh r3, [r7, #22]
80096dc: 461a mov r2, r3
80096de: 6939 ldr r1, [r7, #16]
80096e0: 6878 ldr r0, [r7, #4]
80096e2: f001 facf bl 800ac84 <USBD_CtlSendData>
break;
80096e6: e00e b.n 8009706 <USBD_MIDI_Setup+0x10e>
case USB_REQ_GET_INTERFACE :
USBD_CtlSendData (pdev,
(uint8_t *)&hmidi->AltSetting,
80096e8: 68fb ldr r3, [r7, #12]
80096ea: 3308 adds r3, #8
USBD_CtlSendData (pdev,
80096ec: 2201 movs r2, #1
80096ee: 4619 mov r1, r3
80096f0: 6878 ldr r0, [r7, #4]
80096f2: f001 fac7 bl 800ac84 <USBD_CtlSendData>
1);
break;
80096f6: e006 b.n 8009706 <USBD_MIDI_Setup+0x10e>
case USB_REQ_SET_INTERFACE :
hmidi->AltSetting = (uint8_t)(req->wValue);
80096f8: 683b ldr r3, [r7, #0]
80096fa: 885b ldrh r3, [r3, #2]
80096fc: b2db uxtb r3, r3
80096fe: 461a mov r2, r3
8009700: 68fb ldr r3, [r7, #12]
8009702: 609a str r2, [r3, #8]
break;
8009704: bf00 nop
}
}
return USBD_OK;
8009706: 2300 movs r3, #0
}
8009708: 4618 mov r0, r3
800970a: 3718 adds r7, #24
800970c: 46bd mov sp, r7
800970e: bd80 pop {r7, pc}
8009710: 20000056 .word 0x20000056
08009714 <USBD_MIDI_GetCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_MIDI_GetCfgDesc (uint16_t *length)
{
8009714: b480 push {r7}
8009716: b083 sub sp, #12
8009718: af00 add r7, sp, #0
800971a: 6078 str r0, [r7, #4]
*length = sizeof (USBD_MIDI_CfgDesc);
800971c: 687b ldr r3, [r7, #4]
800971e: 2273 movs r2, #115 @ 0x73
8009720: 801a strh r2, [r3, #0]
return USBD_MIDI_CfgDesc;
8009722: 4b03 ldr r3, [pc, #12] @ (8009730 <USBD_MIDI_GetCfgDesc+0x1c>)
}
8009724: 4618 mov r0, r3
8009726: 370c adds r7, #12
8009728: 46bd mov sp, r7
800972a: f85d 7b04 ldr.w r7, [sp], #4
800972e: 4770 bx lr
8009730: 20000044 .word 0x20000044
08009734 <USBD_MIDI_DataIn>:
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_MIDI_DataIn (USBD_HandleTypeDef *pdev,
uint8_t epnum)
{
8009734: b480 push {r7}
8009736: b083 sub sp, #12
8009738: af00 add r7, sp, #0
800973a: 6078 str r0, [r7, #4]
800973c: 460b mov r3, r1
800973e: 70fb strb r3, [r7, #3]
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
((USBD_MIDI_HandleTypeDef *)pdev->pClassData)->state = MIDI_IDLE;
8009740: 687b ldr r3, [r7, #4]
8009742: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8009746: 2200 movs r2, #0
8009748: 731a strb r2, [r3, #12]
return USBD_OK;
800974a: 2300 movs r3, #0
}
800974c: 4618 mov r0, r3
800974e: 370c adds r7, #12
8009750: 46bd mov sp, r7
8009752: f85d 7b04 ldr.w r7, [sp], #4
8009756: 4770 bx lr
08009758 <USBD_MIDI_DataOut>:
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_MIDI_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)
{
8009758: b580 push {r7, lr}
800975a: b082 sub sp, #8
800975c: af00 add r7, sp, #0
800975e: 6078 str r0, [r7, #4]
8009760: 460b mov r3, r1
8009762: 70fb strb r3, [r7, #3]
if (epnum != (MIDI_EPOUT_ADDR & 0x0F)) return USBD_FAIL;
8009764: 78fb ldrb r3, [r7, #3]
8009766: 2b01 cmp r3, #1
8009768: d001 beq.n 800976e <USBD_MIDI_DataOut+0x16>
800976a: 2303 movs r3, #3
800976c: e00f b.n 800978e <USBD_MIDI_DataOut+0x36>
USBD_MIDI_DataInHandler(usb_rx_buffer, MIDI_EPOUT_SIZE);
800976e: 2140 movs r1, #64 @ 0x40
8009770: 4809 ldr r0, [pc, #36] @ (8009798 <USBD_MIDI_DataOut+0x40>)
8009772: f000 f813 bl 800979c <USBD_MIDI_DataInHandler>
memset(usb_rx_buffer, 0, MIDI_EPOUT_SIZE);
8009776: 2240 movs r2, #64 @ 0x40
8009778: 2100 movs r1, #0
800977a: 4807 ldr r0, [pc, #28] @ (8009798 <USBD_MIDI_DataOut+0x40>)
800977c: f002 fdc7 bl 800c30e <memset>
USBD_LL_PrepareReceive(pdev, MIDI_EPOUT_ADDR, usb_rx_buffer, MIDI_EPOUT_SIZE);
8009780: 2340 movs r3, #64 @ 0x40
8009782: 4a05 ldr r2, [pc, #20] @ (8009798 <USBD_MIDI_DataOut+0x40>)
8009784: 2101 movs r1, #1
8009786: 6878 ldr r0, [r7, #4]
8009788: f001 ffc2 bl 800b710 <USBD_LL_PrepareReceive>
return USBD_OK;
800978c: 2300 movs r3, #0
}
800978e: 4618 mov r0, r3
8009790: 3708 adds r7, #8
8009792: 46bd mov sp, r7
8009794: bd80 pop {r7, pc}
8009796: bf00 nop
8009798: 2000068c .word 0x2000068c
0800979c <USBD_MIDI_DataInHandler>:
* @brief USBD_MIDI_DataInHandler
* @param usb_rx_buffer: midi messages buffer
* @param usb_rx_buffer_length: midi messages buffer length
*/
__weak extern void USBD_MIDI_DataInHandler(uint8_t * usb_rx_buffer, uint8_t usb_rx_buffer_length)
{
800979c: b480 push {r7}
800979e: b083 sub sp, #12
80097a0: af00 add r7, sp, #0
80097a2: 6078 str r0, [r7, #4]
80097a4: 460b mov r3, r1
80097a6: 70fb strb r3, [r7, #3]
// For user implementation.
}
80097a8: bf00 nop
80097aa: 370c adds r7, #12
80097ac: 46bd mov sp, r7
80097ae: f85d 7b04 ldr.w r7, [sp], #4
80097b2: 4770 bx lr
080097b4 <USBD_MIDI_GetDeviceQualifierDesc>:
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_MIDI_GetDeviceQualifierDesc (uint16_t *length)
{
80097b4: b480 push {r7}
80097b6: b083 sub sp, #12
80097b8: af00 add r7, sp, #0
80097ba: 6078 str r0, [r7, #4]
*length = sizeof (USBD_MIDI_DeviceQualifierDesc);
80097bc: 687b ldr r3, [r7, #4]
80097be: 220a movs r2, #10
80097c0: 801a strh r2, [r3, #0]
return USBD_MIDI_DeviceQualifierDesc;
80097c2: 4b03 ldr r3, [pc, #12] @ (80097d0 <USBD_MIDI_GetDeviceQualifierDesc+0x1c>)
}
80097c4: 4618 mov r0, r3
80097c6: 370c adds r7, #12
80097c8: 46bd mov sp, r7
80097ca: f85d 7b04 ldr.w r7, [sp], #4
80097ce: 4770 bx lr
80097d0: 200000b8 .word 0x200000b8
080097d4 <USBD_Init>:
* @param id: Low level core index
* @retval status: USBD Status
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
80097d4: b580 push {r7, lr}
80097d6: b086 sub sp, #24
80097d8: af00 add r7, sp, #0
80097da: 60f8 str r0, [r7, #12]
80097dc: 60b9 str r1, [r7, #8]
80097de: 4613 mov r3, r2
80097e0: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef ret;
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
80097e2: 68fb ldr r3, [r7, #12]
80097e4: 2b00 cmp r3, #0
80097e6: d101 bne.n 80097ec <USBD_Init+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle");
#endif /* (USBD_DEBUG_LEVEL > 1U) */
return USBD_FAIL;
80097e8: 2303 movs r3, #3
80097ea: e01f b.n 800982c <USBD_Init+0x58>
pdev->NumClasses = 0;
pdev->classId = 0;
}
#else
/* Unlink previous class*/
pdev->pClass[0] = NULL;
80097ec: 68fb ldr r3, [r7, #12]
80097ee: 2200 movs r2, #0
80097f0: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
pdev->pUserData[0] = NULL;
80097f4: 68fb ldr r3, [r7, #12]
80097f6: 2200 movs r2, #0
80097f8: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
#endif /* USE_USBD_COMPOSITE */
pdev->pConfDesc = NULL;
80097fc: 68fb ldr r3, [r7, #12]
80097fe: 2200 movs r2, #0
8009800: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
/* Assign USBD Descriptors */
if (pdesc != NULL)
8009804: 68bb ldr r3, [r7, #8]
8009806: 2b00 cmp r3, #0
8009808: d003 beq.n 8009812 <USBD_Init+0x3e>
{
pdev->pDesc = pdesc;
800980a: 68fb ldr r3, [r7, #12]
800980c: 68ba ldr r2, [r7, #8]
800980e: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
}
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
8009812: 68fb ldr r3, [r7, #12]
8009814: 2201 movs r2, #1
8009816: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->id = id;
800981a: 68fb ldr r3, [r7, #12]
800981c: 79fa ldrb r2, [r7, #7]
800981e: 701a strb r2, [r3, #0]
/* Initialize low level driver */
ret = USBD_LL_Init(pdev);
8009820: 68f8 ldr r0, [r7, #12]
8009822: f001 fd7d bl 800b320 <USBD_LL_Init>
8009826: 4603 mov r3, r0
8009828: 75fb strb r3, [r7, #23]
return ret;
800982a: 7dfb ldrb r3, [r7, #23]
}
800982c: 4618 mov r0, r3
800982e: 3718 adds r7, #24
8009830: 46bd mov sp, r7
8009832: bd80 pop {r7, pc}
08009834 <USBD_RegisterClass>:
* @param pdev: Device Handle
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
8009834: b580 push {r7, lr}
8009836: b084 sub sp, #16
8009838: af00 add r7, sp, #0
800983a: 6078 str r0, [r7, #4]
800983c: 6039 str r1, [r7, #0]
uint16_t len = 0U;
800983e: 2300 movs r3, #0
8009840: 81fb strh r3, [r7, #14]
if (pclass == NULL)
8009842: 683b ldr r3, [r7, #0]
8009844: 2b00 cmp r3, #0
8009846: d101 bne.n 800984c <USBD_RegisterClass+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif /* (USBD_DEBUG_LEVEL > 1U) */
return USBD_FAIL;
8009848: 2303 movs r3, #3
800984a: e025 b.n 8009898 <USBD_RegisterClass+0x64>
}
/* link the class to the USB Device handle */
pdev->pClass[0] = pclass;
800984c: 687b ldr r3, [r7, #4]
800984e: 683a ldr r2, [r7, #0]
8009850: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
{
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
}
#else /* Default USE_USB_FS */
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
8009854: 687b ldr r3, [r7, #4]
8009856: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800985a: 687b ldr r3, [r7, #4]
800985c: 32ae adds r2, #174 @ 0xae
800985e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009862: 6adb ldr r3, [r3, #44] @ 0x2c
8009864: 2b00 cmp r3, #0
8009866: d00f beq.n 8009888 <USBD_RegisterClass+0x54>
{
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
8009868: 687b ldr r3, [r7, #4]
800986a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800986e: 687b ldr r3, [r7, #4]
8009870: 32ae adds r2, #174 @ 0xae
8009872: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009876: 6adb ldr r3, [r3, #44] @ 0x2c
8009878: f107 020e add.w r2, r7, #14
800987c: 4610 mov r0, r2
800987e: 4798 blx r3
8009880: 4602 mov r2, r0
8009882: 687b ldr r3, [r7, #4]
8009884: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
}
#endif /* USE_USB_FS */
/* Increment the NumClasses */
pdev->NumClasses++;
8009888: 687b ldr r3, [r7, #4]
800988a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
800988e: 1c5a adds r2, r3, #1
8009890: 687b ldr r3, [r7, #4]
8009892: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
return USBD_OK;
8009896: 2300 movs r3, #0
}
8009898: 4618 mov r0, r3
800989a: 3710 adds r7, #16
800989c: 46bd mov sp, r7
800989e: bd80 pop {r7, pc}
080098a0 <USBD_Start>:
* Start the USB Device Core.
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
80098a0: b580 push {r7, lr}
80098a2: b082 sub sp, #8
80098a4: af00 add r7, sp, #0
80098a6: 6078 str r0, [r7, #4]
#ifdef USE_USBD_COMPOSITE
pdev->classId = 0U;
#endif /* USE_USBD_COMPOSITE */
/* Start the low level driver */
return USBD_LL_Start(pdev);
80098a8: 6878 ldr r0, [r7, #4]
80098aa: f001 fd85 bl 800b3b8 <USBD_LL_Start>
80098ae: 4603 mov r3, r0
}
80098b0: 4618 mov r0, r3
80098b2: 3708 adds r7, #8
80098b4: 46bd mov sp, r7
80098b6: bd80 pop {r7, pc}
080098b8 <USBD_RunTestMode>:
* Launch test mode process
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
80098b8: b480 push {r7}
80098ba: b083 sub sp, #12
80098bc: af00 add r7, sp, #0
80098be: 6078 str r0, [r7, #4]
return ret;
#else
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
80098c0: 2300 movs r3, #0
#endif /* USBD_HS_TESTMODE_ENABLE */
}
80098c2: 4618 mov r0, r3
80098c4: 370c adds r7, #12
80098c6: 46bd mov sp, r7
80098c8: f85d 7b04 ldr.w r7, [sp], #4
80098cc: 4770 bx lr
080098ce <USBD_SetClassConfig>:
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
80098ce: b580 push {r7, lr}
80098d0: b084 sub sp, #16
80098d2: af00 add r7, sp, #0
80098d4: 6078 str r0, [r7, #4]
80098d6: 460b mov r3, r1
80098d8: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_OK;
80098da: 2300 movs r3, #0
80098dc: 73fb strb r3, [r7, #15]
}
}
}
}
#else
if (pdev->pClass[0] != NULL)
80098de: 687b ldr r3, [r7, #4]
80098e0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80098e4: 2b00 cmp r3, #0
80098e6: d009 beq.n 80098fc <USBD_SetClassConfig+0x2e>
{
/* Set configuration and Start the Class */
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
80098e8: 687b ldr r3, [r7, #4]
80098ea: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80098ee: 681b ldr r3, [r3, #0]
80098f0: 78fa ldrb r2, [r7, #3]
80098f2: 4611 mov r1, r2
80098f4: 6878 ldr r0, [r7, #4]
80098f6: 4798 blx r3
80098f8: 4603 mov r3, r0
80098fa: 73fb strb r3, [r7, #15]
}
#endif /* USE_USBD_COMPOSITE */
return ret;
80098fc: 7bfb ldrb r3, [r7, #15]
}
80098fe: 4618 mov r0, r3
8009900: 3710 adds r7, #16
8009902: 46bd mov sp, r7
8009904: bd80 pop {r7, pc}
08009906 <USBD_ClrClassConfig>:
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8009906: b580 push {r7, lr}
8009908: b084 sub sp, #16
800990a: af00 add r7, sp, #0
800990c: 6078 str r0, [r7, #4]
800990e: 460b mov r3, r1
8009910: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_OK;
8009912: 2300 movs r3, #0
8009914: 73fb strb r3, [r7, #15]
}
}
}
#else
/* Clear configuration and De-initialize the Class process */
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
8009916: 687b ldr r3, [r7, #4]
8009918: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800991c: 685b ldr r3, [r3, #4]
800991e: 78fa ldrb r2, [r7, #3]
8009920: 4611 mov r1, r2
8009922: 6878 ldr r0, [r7, #4]
8009924: 4798 blx r3
8009926: 4603 mov r3, r0
8009928: 2b00 cmp r3, #0
800992a: d001 beq.n 8009930 <USBD_ClrClassConfig+0x2a>
{
ret = USBD_FAIL;
800992c: 2303 movs r3, #3
800992e: 73fb strb r3, [r7, #15]
}
#endif /* USE_USBD_COMPOSITE */
return ret;
8009930: 7bfb ldrb r3, [r7, #15]
}
8009932: 4618 mov r0, r3
8009934: 3710 adds r7, #16
8009936: 46bd mov sp, r7
8009938: bd80 pop {r7, pc}
0800993a <USBD_LL_SetupStage>:
* @param pdev: device instance
* @param psetup: setup packet buffer pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
800993a: b580 push {r7, lr}
800993c: b084 sub sp, #16
800993e: af00 add r7, sp, #0
8009940: 6078 str r0, [r7, #4]
8009942: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret;
USBD_ParseSetupRequest(&pdev->request, psetup);
8009944: 687b ldr r3, [r7, #4]
8009946: f203 23aa addw r3, r3, #682 @ 0x2aa
800994a: 6839 ldr r1, [r7, #0]
800994c: 4618 mov r0, r3
800994e: f001 f8e2 bl 800ab16 <USBD_ParseSetupRequest>
pdev->ep0_state = USBD_EP0_SETUP;
8009952: 687b ldr r3, [r7, #4]
8009954: 2201 movs r2, #1
8009956: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep0_data_len = pdev->request.wLength;
800995a: 687b ldr r3, [r7, #4]
800995c: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
8009960: 461a mov r2, r3
8009962: 687b ldr r3, [r7, #4]
8009964: f8c3 2298 str.w r2, [r3, #664] @ 0x298
switch (pdev->request.bmRequest & 0x1FU)
8009968: 687b ldr r3, [r7, #4]
800996a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
800996e: f003 031f and.w r3, r3, #31
8009972: 2b02 cmp r3, #2
8009974: d01a beq.n 80099ac <USBD_LL_SetupStage+0x72>
8009976: 2b02 cmp r3, #2
8009978: d822 bhi.n 80099c0 <USBD_LL_SetupStage+0x86>
800997a: 2b00 cmp r3, #0
800997c: d002 beq.n 8009984 <USBD_LL_SetupStage+0x4a>
800997e: 2b01 cmp r3, #1
8009980: d00a beq.n 8009998 <USBD_LL_SetupStage+0x5e>
8009982: e01d b.n 80099c0 <USBD_LL_SetupStage+0x86>
{
case USB_REQ_RECIPIENT_DEVICE:
ret = USBD_StdDevReq(pdev, &pdev->request);
8009984: 687b ldr r3, [r7, #4]
8009986: f203 23aa addw r3, r3, #682 @ 0x2aa
800998a: 4619 mov r1, r3
800998c: 6878 ldr r0, [r7, #4]
800998e: f000 fb0f bl 8009fb0 <USBD_StdDevReq>
8009992: 4603 mov r3, r0
8009994: 73fb strb r3, [r7, #15]
break;
8009996: e020 b.n 80099da <USBD_LL_SetupStage+0xa0>
case USB_REQ_RECIPIENT_INTERFACE:
ret = USBD_StdItfReq(pdev, &pdev->request);
8009998: 687b ldr r3, [r7, #4]
800999a: f203 23aa addw r3, r3, #682 @ 0x2aa
800999e: 4619 mov r1, r3
80099a0: 6878 ldr r0, [r7, #4]
80099a2: f000 fb77 bl 800a094 <USBD_StdItfReq>
80099a6: 4603 mov r3, r0
80099a8: 73fb strb r3, [r7, #15]
break;
80099aa: e016 b.n 80099da <USBD_LL_SetupStage+0xa0>
case USB_REQ_RECIPIENT_ENDPOINT:
ret = USBD_StdEPReq(pdev, &pdev->request);
80099ac: 687b ldr r3, [r7, #4]
80099ae: f203 23aa addw r3, r3, #682 @ 0x2aa
80099b2: 4619 mov r1, r3
80099b4: 6878 ldr r0, [r7, #4]
80099b6: f000 fbd9 bl 800a16c <USBD_StdEPReq>
80099ba: 4603 mov r3, r0
80099bc: 73fb strb r3, [r7, #15]
break;
80099be: e00c b.n 80099da <USBD_LL_SetupStage+0xa0>
default:
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
80099c0: 687b ldr r3, [r7, #4]
80099c2: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
80099c6: f023 037f bic.w r3, r3, #127 @ 0x7f
80099ca: b2db uxtb r3, r3
80099cc: 4619 mov r1, r3
80099ce: 6878 ldr r0, [r7, #4]
80099d0: f001 fd98 bl 800b504 <USBD_LL_StallEP>
80099d4: 4603 mov r3, r0
80099d6: 73fb strb r3, [r7, #15]
break;
80099d8: bf00 nop
}
return ret;
80099da: 7bfb ldrb r3, [r7, #15]
}
80099dc: 4618 mov r0, r3
80099de: 3710 adds r7, #16
80099e0: 46bd mov sp, r7
80099e2: bd80 pop {r7, pc}
080099e4 <USBD_LL_DataOutStage>:
* @param pdata: data pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
80099e4: b580 push {r7, lr}
80099e6: b086 sub sp, #24
80099e8: af00 add r7, sp, #0
80099ea: 60f8 str r0, [r7, #12]
80099ec: 460b mov r3, r1
80099ee: 607a str r2, [r7, #4]
80099f0: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
USBD_StatusTypeDef ret = USBD_OK;
80099f2: 2300 movs r3, #0
80099f4: 75fb strb r3, [r7, #23]
uint8_t idx;
if (epnum == 0U)
80099f6: 7afb ldrb r3, [r7, #11]
80099f8: 2b00 cmp r3, #0
80099fa: d16e bne.n 8009ada <USBD_LL_DataOutStage+0xf6>
{
pep = &pdev->ep_out[0];
80099fc: 68fb ldr r3, [r7, #12]
80099fe: f503 73aa add.w r3, r3, #340 @ 0x154
8009a02: 613b str r3, [r7, #16]
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
8009a04: 68fb ldr r3, [r7, #12]
8009a06: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8009a0a: 2b03 cmp r3, #3
8009a0c: f040 8098 bne.w 8009b40 <USBD_LL_DataOutStage+0x15c>
{
if (pep->rem_length > pep->maxpacket)
8009a10: 693b ldr r3, [r7, #16]
8009a12: 689a ldr r2, [r3, #8]
8009a14: 693b ldr r3, [r7, #16]
8009a16: 68db ldr r3, [r3, #12]
8009a18: 429a cmp r2, r3
8009a1a: d913 bls.n 8009a44 <USBD_LL_DataOutStage+0x60>
{
pep->rem_length -= pep->maxpacket;
8009a1c: 693b ldr r3, [r7, #16]
8009a1e: 689a ldr r2, [r3, #8]
8009a20: 693b ldr r3, [r7, #16]
8009a22: 68db ldr r3, [r3, #12]
8009a24: 1ad2 subs r2, r2, r3
8009a26: 693b ldr r3, [r7, #16]
8009a28: 609a str r2, [r3, #8]
(void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket));
8009a2a: 693b ldr r3, [r7, #16]
8009a2c: 68da ldr r2, [r3, #12]
8009a2e: 693b ldr r3, [r7, #16]
8009a30: 689b ldr r3, [r3, #8]
8009a32: 4293 cmp r3, r2
8009a34: bf28 it cs
8009a36: 4613 movcs r3, r2
8009a38: 461a mov r2, r3
8009a3a: 6879 ldr r1, [r7, #4]
8009a3c: 68f8 ldr r0, [r7, #12]
8009a3e: f001 f94d bl 800acdc <USBD_CtlContinueRx>
8009a42: e07d b.n 8009b40 <USBD_LL_DataOutStage+0x15c>
}
else
{
/* Find the class ID relative to the current request */
switch (pdev->request.bmRequest & 0x1FU)
8009a44: 68fb ldr r3, [r7, #12]
8009a46: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
8009a4a: f003 031f and.w r3, r3, #31
8009a4e: 2b02 cmp r3, #2
8009a50: d014 beq.n 8009a7c <USBD_LL_DataOutStage+0x98>
8009a52: 2b02 cmp r3, #2
8009a54: d81d bhi.n 8009a92 <USBD_LL_DataOutStage+0xae>
8009a56: 2b00 cmp r3, #0
8009a58: d002 beq.n 8009a60 <USBD_LL_DataOutStage+0x7c>
8009a5a: 2b01 cmp r3, #1
8009a5c: d003 beq.n 8009a66 <USBD_LL_DataOutStage+0x82>
8009a5e: e018 b.n 8009a92 <USBD_LL_DataOutStage+0xae>
{
case USB_REQ_RECIPIENT_DEVICE:
/* Device requests must be managed by the first instantiated class
(or duplicated by all classes for simplicity) */
idx = 0U;
8009a60: 2300 movs r3, #0
8009a62: 75bb strb r3, [r7, #22]
break;
8009a64: e018 b.n 8009a98 <USBD_LL_DataOutStage+0xb4>
case USB_REQ_RECIPIENT_INTERFACE:
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
8009a66: 68fb ldr r3, [r7, #12]
8009a68: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
8009a6c: b2db uxtb r3, r3
8009a6e: 4619 mov r1, r3
8009a70: 68f8 ldr r0, [r7, #12]
8009a72: f000 fa64 bl 8009f3e <USBD_CoreFindIF>
8009a76: 4603 mov r3, r0
8009a78: 75bb strb r3, [r7, #22]
break;
8009a7a: e00d b.n 8009a98 <USBD_LL_DataOutStage+0xb4>
case USB_REQ_RECIPIENT_ENDPOINT:
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
8009a7c: 68fb ldr r3, [r7, #12]
8009a7e: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
8009a82: b2db uxtb r3, r3
8009a84: 4619 mov r1, r3
8009a86: 68f8 ldr r0, [r7, #12]
8009a88: f000 fa66 bl 8009f58 <USBD_CoreFindEP>
8009a8c: 4603 mov r3, r0
8009a8e: 75bb strb r3, [r7, #22]
break;
8009a90: e002 b.n 8009a98 <USBD_LL_DataOutStage+0xb4>
default:
/* Back to the first class in case of doubt */
idx = 0U;
8009a92: 2300 movs r3, #0
8009a94: 75bb strb r3, [r7, #22]
break;
8009a96: bf00 nop
}
if (idx < USBD_MAX_SUPPORTED_CLASS)
8009a98: 7dbb ldrb r3, [r7, #22]
8009a9a: 2b00 cmp r3, #0
8009a9c: d119 bne.n 8009ad2 <USBD_LL_DataOutStage+0xee>
{
/* Setup the class ID and route the request to the relative class function */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009a9e: 68fb ldr r3, [r7, #12]
8009aa0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009aa4: b2db uxtb r3, r3
8009aa6: 2b03 cmp r3, #3
8009aa8: d113 bne.n 8009ad2 <USBD_LL_DataOutStage+0xee>
{
if (pdev->pClass[idx]->EP0_RxReady != NULL)
8009aaa: 7dba ldrb r2, [r7, #22]
8009aac: 68fb ldr r3, [r7, #12]
8009aae: 32ae adds r2, #174 @ 0xae
8009ab0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009ab4: 691b ldr r3, [r3, #16]
8009ab6: 2b00 cmp r3, #0
8009ab8: d00b beq.n 8009ad2 <USBD_LL_DataOutStage+0xee>
{
pdev->classId = idx;
8009aba: 7dba ldrb r2, [r7, #22]
8009abc: 68fb ldr r3, [r7, #12]
8009abe: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
pdev->pClass[idx]->EP0_RxReady(pdev);
8009ac2: 7dba ldrb r2, [r7, #22]
8009ac4: 68fb ldr r3, [r7, #12]
8009ac6: 32ae adds r2, #174 @ 0xae
8009ac8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009acc: 691b ldr r3, [r3, #16]
8009ace: 68f8 ldr r0, [r7, #12]
8009ad0: 4798 blx r3
}
}
}
(void)USBD_CtlSendStatus(pdev);
8009ad2: 68f8 ldr r0, [r7, #12]
8009ad4: f001 f913 bl 800acfe <USBD_CtlSendStatus>
8009ad8: e032 b.n 8009b40 <USBD_LL_DataOutStage+0x15c>
}
}
else
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
8009ada: 7afb ldrb r3, [r7, #11]
8009adc: f003 037f and.w r3, r3, #127 @ 0x7f
8009ae0: b2db uxtb r3, r3
8009ae2: 4619 mov r1, r3
8009ae4: 68f8 ldr r0, [r7, #12]
8009ae6: f000 fa37 bl 8009f58 <USBD_CoreFindEP>
8009aea: 4603 mov r3, r0
8009aec: 75bb strb r3, [r7, #22]
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
8009aee: 7dbb ldrb r3, [r7, #22]
8009af0: 2bff cmp r3, #255 @ 0xff
8009af2: d025 beq.n 8009b40 <USBD_LL_DataOutStage+0x15c>
8009af4: 7dbb ldrb r3, [r7, #22]
8009af6: 2b00 cmp r3, #0
8009af8: d122 bne.n 8009b40 <USBD_LL_DataOutStage+0x15c>
{
/* Call the class data out function to manage the request */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009afa: 68fb ldr r3, [r7, #12]
8009afc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009b00: b2db uxtb r3, r3
8009b02: 2b03 cmp r3, #3
8009b04: d117 bne.n 8009b36 <USBD_LL_DataOutStage+0x152>
{
if (pdev->pClass[idx]->DataOut != NULL)
8009b06: 7dba ldrb r2, [r7, #22]
8009b08: 68fb ldr r3, [r7, #12]
8009b0a: 32ae adds r2, #174 @ 0xae
8009b0c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009b10: 699b ldr r3, [r3, #24]
8009b12: 2b00 cmp r3, #0
8009b14: d00f beq.n 8009b36 <USBD_LL_DataOutStage+0x152>
{
pdev->classId = idx;
8009b16: 7dba ldrb r2, [r7, #22]
8009b18: 68fb ldr r3, [r7, #12]
8009b1a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
8009b1e: 7dba ldrb r2, [r7, #22]
8009b20: 68fb ldr r3, [r7, #12]
8009b22: 32ae adds r2, #174 @ 0xae
8009b24: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009b28: 699b ldr r3, [r3, #24]
8009b2a: 7afa ldrb r2, [r7, #11]
8009b2c: 4611 mov r1, r2
8009b2e: 68f8 ldr r0, [r7, #12]
8009b30: 4798 blx r3
8009b32: 4603 mov r3, r0
8009b34: 75fb strb r3, [r7, #23]
}
}
if (ret != USBD_OK)
8009b36: 7dfb ldrb r3, [r7, #23]
8009b38: 2b00 cmp r3, #0
8009b3a: d001 beq.n 8009b40 <USBD_LL_DataOutStage+0x15c>
{
return ret;
8009b3c: 7dfb ldrb r3, [r7, #23]
8009b3e: e000 b.n 8009b42 <USBD_LL_DataOutStage+0x15e>
}
}
}
return USBD_OK;
8009b40: 2300 movs r3, #0
}
8009b42: 4618 mov r0, r3
8009b44: 3718 adds r7, #24
8009b46: 46bd mov sp, r7
8009b48: bd80 pop {r7, pc}
08009b4a <USBD_LL_DataInStage>:
* @param pdata: data pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
8009b4a: b580 push {r7, lr}
8009b4c: b086 sub sp, #24
8009b4e: af00 add r7, sp, #0
8009b50: 60f8 str r0, [r7, #12]
8009b52: 460b mov r3, r1
8009b54: 607a str r2, [r7, #4]
8009b56: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
USBD_StatusTypeDef ret;
uint8_t idx;
if (epnum == 0U)
8009b58: 7afb ldrb r3, [r7, #11]
8009b5a: 2b00 cmp r3, #0
8009b5c: d16f bne.n 8009c3e <USBD_LL_DataInStage+0xf4>
{
pep = &pdev->ep_in[0];
8009b5e: 68fb ldr r3, [r7, #12]
8009b60: 3314 adds r3, #20
8009b62: 613b str r3, [r7, #16]
if (pdev->ep0_state == USBD_EP0_DATA_IN)
8009b64: 68fb ldr r3, [r7, #12]
8009b66: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8009b6a: 2b02 cmp r3, #2
8009b6c: d15a bne.n 8009c24 <USBD_LL_DataInStage+0xda>
{
if (pep->rem_length > pep->maxpacket)
8009b6e: 693b ldr r3, [r7, #16]
8009b70: 689a ldr r2, [r3, #8]
8009b72: 693b ldr r3, [r7, #16]
8009b74: 68db ldr r3, [r3, #12]
8009b76: 429a cmp r2, r3
8009b78: d914 bls.n 8009ba4 <USBD_LL_DataInStage+0x5a>
{
pep->rem_length -= pep->maxpacket;
8009b7a: 693b ldr r3, [r7, #16]
8009b7c: 689a ldr r2, [r3, #8]
8009b7e: 693b ldr r3, [r7, #16]
8009b80: 68db ldr r3, [r3, #12]
8009b82: 1ad2 subs r2, r2, r3
8009b84: 693b ldr r3, [r7, #16]
8009b86: 609a str r2, [r3, #8]
(void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length);
8009b88: 693b ldr r3, [r7, #16]
8009b8a: 689b ldr r3, [r3, #8]
8009b8c: 461a mov r2, r3
8009b8e: 6879 ldr r1, [r7, #4]
8009b90: 68f8 ldr r0, [r7, #12]
8009b92: f001 f892 bl 800acba <USBD_CtlContinueSendData>
/* Prepare endpoint for premature end of transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8009b96: 2300 movs r3, #0
8009b98: 2200 movs r2, #0
8009b9a: 2100 movs r1, #0
8009b9c: 68f8 ldr r0, [r7, #12]
8009b9e: f001 fdb7 bl 800b710 <USBD_LL_PrepareReceive>
8009ba2: e03f b.n 8009c24 <USBD_LL_DataInStage+0xda>
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->maxpacket == pep->rem_length) &&
8009ba4: 693b ldr r3, [r7, #16]
8009ba6: 68da ldr r2, [r3, #12]
8009ba8: 693b ldr r3, [r7, #16]
8009baa: 689b ldr r3, [r3, #8]
8009bac: 429a cmp r2, r3
8009bae: d11c bne.n 8009bea <USBD_LL_DataInStage+0xa0>
(pep->total_length >= pep->maxpacket) &&
8009bb0: 693b ldr r3, [r7, #16]
8009bb2: 685a ldr r2, [r3, #4]
8009bb4: 693b ldr r3, [r7, #16]
8009bb6: 68db ldr r3, [r3, #12]
if ((pep->maxpacket == pep->rem_length) &&
8009bb8: 429a cmp r2, r3
8009bba: d316 bcc.n 8009bea <USBD_LL_DataInStage+0xa0>
(pep->total_length < pdev->ep0_data_len))
8009bbc: 693b ldr r3, [r7, #16]
8009bbe: 685a ldr r2, [r3, #4]
8009bc0: 68fb ldr r3, [r7, #12]
8009bc2: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
(pep->total_length >= pep->maxpacket) &&
8009bc6: 429a cmp r2, r3
8009bc8: d20f bcs.n 8009bea <USBD_LL_DataInStage+0xa0>
{
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
8009bca: 2200 movs r2, #0
8009bcc: 2100 movs r1, #0
8009bce: 68f8 ldr r0, [r7, #12]
8009bd0: f001 f873 bl 800acba <USBD_CtlContinueSendData>
pdev->ep0_data_len = 0U;
8009bd4: 68fb ldr r3, [r7, #12]
8009bd6: 2200 movs r2, #0
8009bd8: f8c3 2298 str.w r2, [r3, #664] @ 0x298
/* Prepare endpoint for premature end of transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8009bdc: 2300 movs r3, #0
8009bde: 2200 movs r2, #0
8009be0: 2100 movs r1, #0
8009be2: 68f8 ldr r0, [r7, #12]
8009be4: f001 fd94 bl 800b710 <USBD_LL_PrepareReceive>
8009be8: e01c b.n 8009c24 <USBD_LL_DataInStage+0xda>
}
else
{
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009bea: 68fb ldr r3, [r7, #12]
8009bec: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009bf0: b2db uxtb r3, r3
8009bf2: 2b03 cmp r3, #3
8009bf4: d10f bne.n 8009c16 <USBD_LL_DataInStage+0xcc>
{
if (pdev->pClass[0]->EP0_TxSent != NULL)
8009bf6: 68fb ldr r3, [r7, #12]
8009bf8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009bfc: 68db ldr r3, [r3, #12]
8009bfe: 2b00 cmp r3, #0
8009c00: d009 beq.n 8009c16 <USBD_LL_DataInStage+0xcc>
{
pdev->classId = 0U;
8009c02: 68fb ldr r3, [r7, #12]
8009c04: 2200 movs r2, #0
8009c06: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
pdev->pClass[0]->EP0_TxSent(pdev);
8009c0a: 68fb ldr r3, [r7, #12]
8009c0c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009c10: 68db ldr r3, [r3, #12]
8009c12: 68f8 ldr r0, [r7, #12]
8009c14: 4798 blx r3
}
}
(void)USBD_LL_StallEP(pdev, 0x80U);
8009c16: 2180 movs r1, #128 @ 0x80
8009c18: 68f8 ldr r0, [r7, #12]
8009c1a: f001 fc73 bl 800b504 <USBD_LL_StallEP>
(void)USBD_CtlReceiveStatus(pdev);
8009c1e: 68f8 ldr r0, [r7, #12]
8009c20: f001 f880 bl 800ad24 <USBD_CtlReceiveStatus>
}
}
}
if (pdev->dev_test_mode != 0U)
8009c24: 68fb ldr r3, [r7, #12]
8009c26: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
8009c2a: 2b00 cmp r3, #0
8009c2c: d03a beq.n 8009ca4 <USBD_LL_DataInStage+0x15a>
{
(void)USBD_RunTestMode(pdev);
8009c2e: 68f8 ldr r0, [r7, #12]
8009c30: f7ff fe42 bl 80098b8 <USBD_RunTestMode>
pdev->dev_test_mode = 0U;
8009c34: 68fb ldr r3, [r7, #12]
8009c36: 2200 movs r2, #0
8009c38: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
8009c3c: e032 b.n 8009ca4 <USBD_LL_DataInStage+0x15a>
}
}
else
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
8009c3e: 7afb ldrb r3, [r7, #11]
8009c40: f063 037f orn r3, r3, #127 @ 0x7f
8009c44: b2db uxtb r3, r3
8009c46: 4619 mov r1, r3
8009c48: 68f8 ldr r0, [r7, #12]
8009c4a: f000 f985 bl 8009f58 <USBD_CoreFindEP>
8009c4e: 4603 mov r3, r0
8009c50: 75fb strb r3, [r7, #23]
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
8009c52: 7dfb ldrb r3, [r7, #23]
8009c54: 2bff cmp r3, #255 @ 0xff
8009c56: d025 beq.n 8009ca4 <USBD_LL_DataInStage+0x15a>
8009c58: 7dfb ldrb r3, [r7, #23]
8009c5a: 2b00 cmp r3, #0
8009c5c: d122 bne.n 8009ca4 <USBD_LL_DataInStage+0x15a>
{
/* Call the class data out function to manage the request */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009c5e: 68fb ldr r3, [r7, #12]
8009c60: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009c64: b2db uxtb r3, r3
8009c66: 2b03 cmp r3, #3
8009c68: d11c bne.n 8009ca4 <USBD_LL_DataInStage+0x15a>
{
if (pdev->pClass[idx]->DataIn != NULL)
8009c6a: 7dfa ldrb r2, [r7, #23]
8009c6c: 68fb ldr r3, [r7, #12]
8009c6e: 32ae adds r2, #174 @ 0xae
8009c70: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009c74: 695b ldr r3, [r3, #20]
8009c76: 2b00 cmp r3, #0
8009c78: d014 beq.n 8009ca4 <USBD_LL_DataInStage+0x15a>
{
pdev->classId = idx;
8009c7a: 7dfa ldrb r2, [r7, #23]
8009c7c: 68fb ldr r3, [r7, #12]
8009c7e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
8009c82: 7dfa ldrb r2, [r7, #23]
8009c84: 68fb ldr r3, [r7, #12]
8009c86: 32ae adds r2, #174 @ 0xae
8009c88: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009c8c: 695b ldr r3, [r3, #20]
8009c8e: 7afa ldrb r2, [r7, #11]
8009c90: 4611 mov r1, r2
8009c92: 68f8 ldr r0, [r7, #12]
8009c94: 4798 blx r3
8009c96: 4603 mov r3, r0
8009c98: 75bb strb r3, [r7, #22]
if (ret != USBD_OK)
8009c9a: 7dbb ldrb r3, [r7, #22]
8009c9c: 2b00 cmp r3, #0
8009c9e: d001 beq.n 8009ca4 <USBD_LL_DataInStage+0x15a>
{
return ret;
8009ca0: 7dbb ldrb r3, [r7, #22]
8009ca2: e000 b.n 8009ca6 <USBD_LL_DataInStage+0x15c>
}
}
}
}
return USBD_OK;
8009ca4: 2300 movs r3, #0
}
8009ca6: 4618 mov r0, r3
8009ca8: 3718 adds r7, #24
8009caa: 46bd mov sp, r7
8009cac: bd80 pop {r7, pc}
08009cae <USBD_LL_Reset>:
* Handle Reset event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
8009cae: b580 push {r7, lr}
8009cb0: b084 sub sp, #16
8009cb2: af00 add r7, sp, #0
8009cb4: 6078 str r0, [r7, #4]
USBD_StatusTypeDef ret = USBD_OK;
8009cb6: 2300 movs r3, #0
8009cb8: 73fb strb r3, [r7, #15]
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
8009cba: 687b ldr r3, [r7, #4]
8009cbc: 2201 movs r2, #1
8009cbe: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->ep0_state = USBD_EP0_IDLE;
8009cc2: 687b ldr r3, [r7, #4]
8009cc4: 2200 movs r2, #0
8009cc6: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->dev_config = 0U;
8009cca: 687b ldr r3, [r7, #4]
8009ccc: 2200 movs r2, #0
8009cce: 605a str r2, [r3, #4]
pdev->dev_remote_wakeup = 0U;
8009cd0: 687b ldr r3, [r7, #4]
8009cd2: 2200 movs r2, #0
8009cd4: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
pdev->dev_test_mode = 0U;
8009cd8: 687b ldr r3, [r7, #4]
8009cda: 2200 movs r2, #0
8009cdc: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
}
}
}
#else
if (pdev->pClass[0] != NULL)
8009ce0: 687b ldr r3, [r7, #4]
8009ce2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009ce6: 2b00 cmp r3, #0
8009ce8: d014 beq.n 8009d14 <USBD_LL_Reset+0x66>
{
if (pdev->pClass[0]->DeInit != NULL)
8009cea: 687b ldr r3, [r7, #4]
8009cec: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009cf0: 685b ldr r3, [r3, #4]
8009cf2: 2b00 cmp r3, #0
8009cf4: d00e beq.n 8009d14 <USBD_LL_Reset+0x66>
{
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
8009cf6: 687b ldr r3, [r7, #4]
8009cf8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009cfc: 685b ldr r3, [r3, #4]
8009cfe: 687a ldr r2, [r7, #4]
8009d00: 6852 ldr r2, [r2, #4]
8009d02: b2d2 uxtb r2, r2
8009d04: 4611 mov r1, r2
8009d06: 6878 ldr r0, [r7, #4]
8009d08: 4798 blx r3
8009d0a: 4603 mov r3, r0
8009d0c: 2b00 cmp r3, #0
8009d0e: d001 beq.n 8009d14 <USBD_LL_Reset+0x66>
{
ret = USBD_FAIL;
8009d10: 2303 movs r3, #3
8009d12: 73fb strb r3, [r7, #15]
}
}
#endif /* USE_USBD_COMPOSITE */
/* Open EP0 OUT */
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8009d14: 2340 movs r3, #64 @ 0x40
8009d16: 2200 movs r2, #0
8009d18: 2100 movs r1, #0
8009d1a: 6878 ldr r0, [r7, #4]
8009d1c: f001 fb7e bl 800b41c <USBD_LL_OpenEP>
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
8009d20: 687b ldr r3, [r7, #4]
8009d22: 2201 movs r2, #1
8009d24: f8a3 2164 strh.w r2, [r3, #356] @ 0x164
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
8009d28: 687b ldr r3, [r7, #4]
8009d2a: 2240 movs r2, #64 @ 0x40
8009d2c: f8c3 2160 str.w r2, [r3, #352] @ 0x160
/* Open EP0 IN */
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8009d30: 2340 movs r3, #64 @ 0x40
8009d32: 2200 movs r2, #0
8009d34: 2180 movs r1, #128 @ 0x80
8009d36: 6878 ldr r0, [r7, #4]
8009d38: f001 fb70 bl 800b41c <USBD_LL_OpenEP>
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
8009d3c: 687b ldr r3, [r7, #4]
8009d3e: 2201 movs r2, #1
8009d40: 849a strh r2, [r3, #36] @ 0x24
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
8009d42: 687b ldr r3, [r7, #4]
8009d44: 2240 movs r2, #64 @ 0x40
8009d46: 621a str r2, [r3, #32]
return ret;
8009d48: 7bfb ldrb r3, [r7, #15]
}
8009d4a: 4618 mov r0, r3
8009d4c: 3710 adds r7, #16
8009d4e: 46bd mov sp, r7
8009d50: bd80 pop {r7, pc}
08009d52 <USBD_LL_SetSpeed>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{
8009d52: b480 push {r7}
8009d54: b083 sub sp, #12
8009d56: af00 add r7, sp, #0
8009d58: 6078 str r0, [r7, #4]
8009d5a: 460b mov r3, r1
8009d5c: 70fb strb r3, [r7, #3]
pdev->dev_speed = speed;
8009d5e: 687b ldr r3, [r7, #4]
8009d60: 78fa ldrb r2, [r7, #3]
8009d62: 741a strb r2, [r3, #16]
return USBD_OK;
8009d64: 2300 movs r3, #0
}
8009d66: 4618 mov r0, r3
8009d68: 370c adds r7, #12
8009d6a: 46bd mov sp, r7
8009d6c: f85d 7b04 ldr.w r7, [sp], #4
8009d70: 4770 bx lr
08009d72 <USBD_LL_Suspend>:
* Handle Suspend event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
8009d72: b480 push {r7}
8009d74: b083 sub sp, #12
8009d76: af00 add r7, sp, #0
8009d78: 6078 str r0, [r7, #4]
if (pdev->dev_state != USBD_STATE_SUSPENDED)
8009d7a: 687b ldr r3, [r7, #4]
8009d7c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009d80: b2db uxtb r3, r3
8009d82: 2b04 cmp r3, #4
8009d84: d006 beq.n 8009d94 <USBD_LL_Suspend+0x22>
{
pdev->dev_old_state = pdev->dev_state;
8009d86: 687b ldr r3, [r7, #4]
8009d88: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009d8c: b2da uxtb r2, r3
8009d8e: 687b ldr r3, [r7, #4]
8009d90: f883 229d strb.w r2, [r3, #669] @ 0x29d
}
pdev->dev_state = USBD_STATE_SUSPENDED;
8009d94: 687b ldr r3, [r7, #4]
8009d96: 2204 movs r2, #4
8009d98: f883 229c strb.w r2, [r3, #668] @ 0x29c
return USBD_OK;
8009d9c: 2300 movs r3, #0
}
8009d9e: 4618 mov r0, r3
8009da0: 370c adds r7, #12
8009da2: 46bd mov sp, r7
8009da4: f85d 7b04 ldr.w r7, [sp], #4
8009da8: 4770 bx lr
08009daa <USBD_LL_Resume>:
* Handle Resume event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{
8009daa: b480 push {r7}
8009dac: b083 sub sp, #12
8009dae: af00 add r7, sp, #0
8009db0: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_SUSPENDED)
8009db2: 687b ldr r3, [r7, #4]
8009db4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009db8: b2db uxtb r3, r3
8009dba: 2b04 cmp r3, #4
8009dbc: d106 bne.n 8009dcc <USBD_LL_Resume+0x22>
{
pdev->dev_state = pdev->dev_old_state;
8009dbe: 687b ldr r3, [r7, #4]
8009dc0: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
8009dc4: b2da uxtb r2, r3
8009dc6: 687b ldr r3, [r7, #4]
8009dc8: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
return USBD_OK;
8009dcc: 2300 movs r3, #0
}
8009dce: 4618 mov r0, r3
8009dd0: 370c adds r7, #12
8009dd2: 46bd mov sp, r7
8009dd4: f85d 7b04 ldr.w r7, [sp], #4
8009dd8: 4770 bx lr
08009dda <USBD_LL_SOF>:
* Handle SOF event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{
8009dda: b580 push {r7, lr}
8009ddc: b082 sub sp, #8
8009dde: af00 add r7, sp, #0
8009de0: 6078 str r0, [r7, #4]
/* The SOF event can be distributed for all classes that support it */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009de2: 687b ldr r3, [r7, #4]
8009de4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009de8: b2db uxtb r3, r3
8009dea: 2b03 cmp r3, #3
8009dec: d110 bne.n 8009e10 <USBD_LL_SOF+0x36>
}
}
}
}
#else
if (pdev->pClass[0] != NULL)
8009dee: 687b ldr r3, [r7, #4]
8009df0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009df4: 2b00 cmp r3, #0
8009df6: d00b beq.n 8009e10 <USBD_LL_SOF+0x36>
{
if (pdev->pClass[0]->SOF != NULL)
8009df8: 687b ldr r3, [r7, #4]
8009dfa: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009dfe: 69db ldr r3, [r3, #28]
8009e00: 2b00 cmp r3, #0
8009e02: d005 beq.n 8009e10 <USBD_LL_SOF+0x36>
{
(void)pdev->pClass[0]->SOF(pdev);
8009e04: 687b ldr r3, [r7, #4]
8009e06: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009e0a: 69db ldr r3, [r3, #28]
8009e0c: 6878 ldr r0, [r7, #4]
8009e0e: 4798 blx r3
}
}
#endif /* USE_USBD_COMPOSITE */
}
return USBD_OK;
8009e10: 2300 movs r3, #0
}
8009e12: 4618 mov r0, r3
8009e14: 3708 adds r7, #8
8009e16: 46bd mov sp, r7
8009e18: bd80 pop {r7, pc}
08009e1a <USBD_LL_IsoINIncomplete>:
* @param epnum: Endpoint number
* @retval status
*/
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
uint8_t epnum)
{
8009e1a: b580 push {r7, lr}
8009e1c: b082 sub sp, #8
8009e1e: af00 add r7, sp, #0
8009e20: 6078 str r0, [r7, #4]
8009e22: 460b mov r3, r1
8009e24: 70fb strb r3, [r7, #3]
if (pdev->pClass[pdev->classId] == NULL)
8009e26: 687b ldr r3, [r7, #4]
8009e28: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8009e2c: 687b ldr r3, [r7, #4]
8009e2e: 32ae adds r2, #174 @ 0xae
8009e30: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009e34: 2b00 cmp r3, #0
8009e36: d101 bne.n 8009e3c <USBD_LL_IsoINIncomplete+0x22>
{
return USBD_FAIL;
8009e38: 2303 movs r3, #3
8009e3a: e01c b.n 8009e76 <USBD_LL_IsoINIncomplete+0x5c>
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009e3c: 687b ldr r3, [r7, #4]
8009e3e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009e42: b2db uxtb r3, r3
8009e44: 2b03 cmp r3, #3
8009e46: d115 bne.n 8009e74 <USBD_LL_IsoINIncomplete+0x5a>
{
if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL)
8009e48: 687b ldr r3, [r7, #4]
8009e4a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8009e4e: 687b ldr r3, [r7, #4]
8009e50: 32ae adds r2, #174 @ 0xae
8009e52: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009e56: 6a1b ldr r3, [r3, #32]
8009e58: 2b00 cmp r3, #0
8009e5a: d00b beq.n 8009e74 <USBD_LL_IsoINIncomplete+0x5a>
{
(void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum);
8009e5c: 687b ldr r3, [r7, #4]
8009e5e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8009e62: 687b ldr r3, [r7, #4]
8009e64: 32ae adds r2, #174 @ 0xae
8009e66: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009e6a: 6a1b ldr r3, [r3, #32]
8009e6c: 78fa ldrb r2, [r7, #3]
8009e6e: 4611 mov r1, r2
8009e70: 6878 ldr r0, [r7, #4]
8009e72: 4798 blx r3
}
}
return USBD_OK;
8009e74: 2300 movs r3, #0
}
8009e76: 4618 mov r0, r3
8009e78: 3708 adds r7, #8
8009e7a: 46bd mov sp, r7
8009e7c: bd80 pop {r7, pc}
08009e7e <USBD_LL_IsoOUTIncomplete>:
* @param epnum: Endpoint number
* @retval status
*/
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
uint8_t epnum)
{
8009e7e: b580 push {r7, lr}
8009e80: b082 sub sp, #8
8009e82: af00 add r7, sp, #0
8009e84: 6078 str r0, [r7, #4]
8009e86: 460b mov r3, r1
8009e88: 70fb strb r3, [r7, #3]
if (pdev->pClass[pdev->classId] == NULL)
8009e8a: 687b ldr r3, [r7, #4]
8009e8c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8009e90: 687b ldr r3, [r7, #4]
8009e92: 32ae adds r2, #174 @ 0xae
8009e94: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009e98: 2b00 cmp r3, #0
8009e9a: d101 bne.n 8009ea0 <USBD_LL_IsoOUTIncomplete+0x22>
{
return USBD_FAIL;
8009e9c: 2303 movs r3, #3
8009e9e: e01c b.n 8009eda <USBD_LL_IsoOUTIncomplete+0x5c>
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009ea0: 687b ldr r3, [r7, #4]
8009ea2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009ea6: b2db uxtb r3, r3
8009ea8: 2b03 cmp r3, #3
8009eaa: d115 bne.n 8009ed8 <USBD_LL_IsoOUTIncomplete+0x5a>
{
if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL)
8009eac: 687b ldr r3, [r7, #4]
8009eae: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8009eb2: 687b ldr r3, [r7, #4]
8009eb4: 32ae adds r2, #174 @ 0xae
8009eb6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009eba: 6a5b ldr r3, [r3, #36] @ 0x24
8009ebc: 2b00 cmp r3, #0
8009ebe: d00b beq.n 8009ed8 <USBD_LL_IsoOUTIncomplete+0x5a>
{
(void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum);
8009ec0: 687b ldr r3, [r7, #4]
8009ec2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8009ec6: 687b ldr r3, [r7, #4]
8009ec8: 32ae adds r2, #174 @ 0xae
8009eca: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009ece: 6a5b ldr r3, [r3, #36] @ 0x24
8009ed0: 78fa ldrb r2, [r7, #3]
8009ed2: 4611 mov r1, r2
8009ed4: 6878 ldr r0, [r7, #4]
8009ed6: 4798 blx r3
}
}
return USBD_OK;
8009ed8: 2300 movs r3, #0
}
8009eda: 4618 mov r0, r3
8009edc: 3708 adds r7, #8
8009ede: 46bd mov sp, r7
8009ee0: bd80 pop {r7, pc}
08009ee2 <USBD_LL_DevConnected>:
* Handle device connection event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
{
8009ee2: b480 push {r7}
8009ee4: b083 sub sp, #12
8009ee6: af00 add r7, sp, #0
8009ee8: 6078 str r0, [r7, #4]
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
8009eea: 2300 movs r3, #0
}
8009eec: 4618 mov r0, r3
8009eee: 370c adds r7, #12
8009ef0: 46bd mov sp, r7
8009ef2: f85d 7b04 ldr.w r7, [sp], #4
8009ef6: 4770 bx lr
08009ef8 <USBD_LL_DevDisconnected>:
* Handle device disconnection event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
{
8009ef8: b580 push {r7, lr}
8009efa: b084 sub sp, #16
8009efc: af00 add r7, sp, #0
8009efe: 6078 str r0, [r7, #4]
USBD_StatusTypeDef ret = USBD_OK;
8009f00: 2300 movs r3, #0
8009f02: 73fb strb r3, [r7, #15]
/* Free Class Resources */
pdev->dev_state = USBD_STATE_DEFAULT;
8009f04: 687b ldr r3, [r7, #4]
8009f06: 2201 movs r2, #1
8009f08: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
}
}
}
#else
if (pdev->pClass[0] != NULL)
8009f0c: 687b ldr r3, [r7, #4]
8009f0e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009f12: 2b00 cmp r3, #0
8009f14: d00e beq.n 8009f34 <USBD_LL_DevDisconnected+0x3c>
{
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U)
8009f16: 687b ldr r3, [r7, #4]
8009f18: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009f1c: 685b ldr r3, [r3, #4]
8009f1e: 687a ldr r2, [r7, #4]
8009f20: 6852 ldr r2, [r2, #4]
8009f22: b2d2 uxtb r2, r2
8009f24: 4611 mov r1, r2
8009f26: 6878 ldr r0, [r7, #4]
8009f28: 4798 blx r3
8009f2a: 4603 mov r3, r0
8009f2c: 2b00 cmp r3, #0
8009f2e: d001 beq.n 8009f34 <USBD_LL_DevDisconnected+0x3c>
{
ret = USBD_FAIL;
8009f30: 2303 movs r3, #3
8009f32: 73fb strb r3, [r7, #15]
}
}
#endif /* USE_USBD_COMPOSITE */
return ret;
8009f34: 7bfb ldrb r3, [r7, #15]
}
8009f36: 4618 mov r0, r3
8009f38: 3710 adds r7, #16
8009f3a: 46bd mov sp, r7
8009f3c: bd80 pop {r7, pc}
08009f3e <USBD_CoreFindIF>:
* @param pdev: device instance
* @param index : selected interface number
* @retval index of the class using the selected interface number. OxFF if no class found.
*/
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
{
8009f3e: b480 push {r7}
8009f40: b083 sub sp, #12
8009f42: af00 add r7, sp, #0
8009f44: 6078 str r0, [r7, #4]
8009f46: 460b mov r3, r1
8009f48: 70fb strb r3, [r7, #3]
return 0xFFU;
#else
UNUSED(pdev);
UNUSED(index);
return 0x00U;
8009f4a: 2300 movs r3, #0
#endif /* USE_USBD_COMPOSITE */
}
8009f4c: 4618 mov r0, r3
8009f4e: 370c adds r7, #12
8009f50: 46bd mov sp, r7
8009f52: f85d 7b04 ldr.w r7, [sp], #4
8009f56: 4770 bx lr
08009f58 <USBD_CoreFindEP>:
* @param pdev: device instance
* @param index : selected endpoint number
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
*/
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
{
8009f58: b480 push {r7}
8009f5a: b083 sub sp, #12
8009f5c: af00 add r7, sp, #0
8009f5e: 6078 str r0, [r7, #4]
8009f60: 460b mov r3, r1
8009f62: 70fb strb r3, [r7, #3]
return 0xFFU;
#else
UNUSED(pdev);
UNUSED(index);
return 0x00U;
8009f64: 2300 movs r3, #0
#endif /* USE_USBD_COMPOSITE */
}
8009f66: 4618 mov r0, r3
8009f68: 370c adds r7, #12
8009f6a: 46bd mov sp, r7
8009f6c: f85d 7b04 ldr.w r7, [sp], #4
8009f70: 4770 bx lr
08009f72 <SWAPBYTE>:
/** @defgroup USBD_DEF_Exported_Macros
* @{
*/
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
{
8009f72: b480 push {r7}
8009f74: b087 sub sp, #28
8009f76: af00 add r7, sp, #0
8009f78: 6078 str r0, [r7, #4]
uint16_t _SwapVal;
uint16_t _Byte1;
uint16_t _Byte2;
uint8_t *_pbuff = addr;
8009f7a: 687b ldr r3, [r7, #4]
8009f7c: 617b str r3, [r7, #20]
_Byte1 = *(uint8_t *)_pbuff;
8009f7e: 697b ldr r3, [r7, #20]
8009f80: 781b ldrb r3, [r3, #0]
8009f82: 827b strh r3, [r7, #18]
_pbuff++;
8009f84: 697b ldr r3, [r7, #20]
8009f86: 3301 adds r3, #1
8009f88: 617b str r3, [r7, #20]
_Byte2 = *(uint8_t *)_pbuff;
8009f8a: 697b ldr r3, [r7, #20]
8009f8c: 781b ldrb r3, [r3, #0]
8009f8e: 823b strh r3, [r7, #16]
_SwapVal = (_Byte2 << 8) | _Byte1;
8009f90: f9b7 3010 ldrsh.w r3, [r7, #16]
8009f94: 021b lsls r3, r3, #8
8009f96: b21a sxth r2, r3
8009f98: f9b7 3012 ldrsh.w r3, [r7, #18]
8009f9c: 4313 orrs r3, r2
8009f9e: b21b sxth r3, r3
8009fa0: 81fb strh r3, [r7, #14]
return _SwapVal;
8009fa2: 89fb ldrh r3, [r7, #14]
}
8009fa4: 4618 mov r0, r3
8009fa6: 371c adds r7, #28
8009fa8: 46bd mov sp, r7
8009faa: f85d 7b04 ldr.w r7, [sp], #4
8009fae: 4770 bx lr
08009fb0 <USBD_StdDevReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8009fb0: b580 push {r7, lr}
8009fb2: b084 sub sp, #16
8009fb4: af00 add r7, sp, #0
8009fb6: 6078 str r0, [r7, #4]
8009fb8: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8009fba: 2300 movs r3, #0
8009fbc: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009fbe: 683b ldr r3, [r7, #0]
8009fc0: 781b ldrb r3, [r3, #0]
8009fc2: f003 0360 and.w r3, r3, #96 @ 0x60
8009fc6: 2b40 cmp r3, #64 @ 0x40
8009fc8: d005 beq.n 8009fd6 <USBD_StdDevReq+0x26>
8009fca: 2b40 cmp r3, #64 @ 0x40
8009fcc: d857 bhi.n 800a07e <USBD_StdDevReq+0xce>
8009fce: 2b00 cmp r3, #0
8009fd0: d00f beq.n 8009ff2 <USBD_StdDevReq+0x42>
8009fd2: 2b20 cmp r3, #32
8009fd4: d153 bne.n 800a07e <USBD_StdDevReq+0xce>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
8009fd6: 687b ldr r3, [r7, #4]
8009fd8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8009fdc: 687b ldr r3, [r7, #4]
8009fde: 32ae adds r2, #174 @ 0xae
8009fe0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8009fe4: 689b ldr r3, [r3, #8]
8009fe6: 6839 ldr r1, [r7, #0]
8009fe8: 6878 ldr r0, [r7, #4]
8009fea: 4798 blx r3
8009fec: 4603 mov r3, r0
8009fee: 73fb strb r3, [r7, #15]
break;
8009ff0: e04a b.n 800a088 <USBD_StdDevReq+0xd8>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8009ff2: 683b ldr r3, [r7, #0]
8009ff4: 785b ldrb r3, [r3, #1]
8009ff6: 2b09 cmp r3, #9
8009ff8: d83b bhi.n 800a072 <USBD_StdDevReq+0xc2>
8009ffa: a201 add r2, pc, #4 @ (adr r2, 800a000 <USBD_StdDevReq+0x50>)
8009ffc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a000: 0800a055 .word 0x0800a055
800a004: 0800a069 .word 0x0800a069
800a008: 0800a073 .word 0x0800a073
800a00c: 0800a05f .word 0x0800a05f
800a010: 0800a073 .word 0x0800a073
800a014: 0800a033 .word 0x0800a033
800a018: 0800a029 .word 0x0800a029
800a01c: 0800a073 .word 0x0800a073
800a020: 0800a04b .word 0x0800a04b
800a024: 0800a03d .word 0x0800a03d
{
case USB_REQ_GET_DESCRIPTOR:
USBD_GetDescriptor(pdev, req);
800a028: 6839 ldr r1, [r7, #0]
800a02a: 6878 ldr r0, [r7, #4]
800a02c: f000 fa3c bl 800a4a8 <USBD_GetDescriptor>
break;
800a030: e024 b.n 800a07c <USBD_StdDevReq+0xcc>
case USB_REQ_SET_ADDRESS:
USBD_SetAddress(pdev, req);
800a032: 6839 ldr r1, [r7, #0]
800a034: 6878 ldr r0, [r7, #4]
800a036: f000 fbcb bl 800a7d0 <USBD_SetAddress>
break;
800a03a: e01f b.n 800a07c <USBD_StdDevReq+0xcc>
case USB_REQ_SET_CONFIGURATION:
ret = USBD_SetConfig(pdev, req);
800a03c: 6839 ldr r1, [r7, #0]
800a03e: 6878 ldr r0, [r7, #4]
800a040: f000 fc0a bl 800a858 <USBD_SetConfig>
800a044: 4603 mov r3, r0
800a046: 73fb strb r3, [r7, #15]
break;
800a048: e018 b.n 800a07c <USBD_StdDevReq+0xcc>
case USB_REQ_GET_CONFIGURATION:
USBD_GetConfig(pdev, req);
800a04a: 6839 ldr r1, [r7, #0]
800a04c: 6878 ldr r0, [r7, #4]
800a04e: f000 fcad bl 800a9ac <USBD_GetConfig>
break;
800a052: e013 b.n 800a07c <USBD_StdDevReq+0xcc>
case USB_REQ_GET_STATUS:
USBD_GetStatus(pdev, req);
800a054: 6839 ldr r1, [r7, #0]
800a056: 6878 ldr r0, [r7, #4]
800a058: f000 fcde bl 800aa18 <USBD_GetStatus>
break;
800a05c: e00e b.n 800a07c <USBD_StdDevReq+0xcc>
case USB_REQ_SET_FEATURE:
USBD_SetFeature(pdev, req);
800a05e: 6839 ldr r1, [r7, #0]
800a060: 6878 ldr r0, [r7, #4]
800a062: f000 fd0d bl 800aa80 <USBD_SetFeature>
break;
800a066: e009 b.n 800a07c <USBD_StdDevReq+0xcc>
case USB_REQ_CLEAR_FEATURE:
USBD_ClrFeature(pdev, req);
800a068: 6839 ldr r1, [r7, #0]
800a06a: 6878 ldr r0, [r7, #4]
800a06c: f000 fd31 bl 800aad2 <USBD_ClrFeature>
break;
800a070: e004 b.n 800a07c <USBD_StdDevReq+0xcc>
default:
USBD_CtlError(pdev, req);
800a072: 6839 ldr r1, [r7, #0]
800a074: 6878 ldr r0, [r7, #4]
800a076: f000 fd88 bl 800ab8a <USBD_CtlError>
break;
800a07a: bf00 nop
}
break;
800a07c: e004 b.n 800a088 <USBD_StdDevReq+0xd8>
default:
USBD_CtlError(pdev, req);
800a07e: 6839 ldr r1, [r7, #0]
800a080: 6878 ldr r0, [r7, #4]
800a082: f000 fd82 bl 800ab8a <USBD_CtlError>
break;
800a086: bf00 nop
}
return ret;
800a088: 7bfb ldrb r3, [r7, #15]
}
800a08a: 4618 mov r0, r3
800a08c: 3710 adds r7, #16
800a08e: 46bd mov sp, r7
800a090: bd80 pop {r7, pc}
800a092: bf00 nop
0800a094 <USBD_StdItfReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a094: b580 push {r7, lr}
800a096: b084 sub sp, #16
800a098: af00 add r7, sp, #0
800a09a: 6078 str r0, [r7, #4]
800a09c: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
800a09e: 2300 movs r3, #0
800a0a0: 73fb strb r3, [r7, #15]
uint8_t idx;
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800a0a2: 683b ldr r3, [r7, #0]
800a0a4: 781b ldrb r3, [r3, #0]
800a0a6: f003 0360 and.w r3, r3, #96 @ 0x60
800a0aa: 2b40 cmp r3, #64 @ 0x40
800a0ac: d005 beq.n 800a0ba <USBD_StdItfReq+0x26>
800a0ae: 2b40 cmp r3, #64 @ 0x40
800a0b0: d852 bhi.n 800a158 <USBD_StdItfReq+0xc4>
800a0b2: 2b00 cmp r3, #0
800a0b4: d001 beq.n 800a0ba <USBD_StdItfReq+0x26>
800a0b6: 2b20 cmp r3, #32
800a0b8: d14e bne.n 800a158 <USBD_StdItfReq+0xc4>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
case USB_REQ_TYPE_STANDARD:
switch (pdev->dev_state)
800a0ba: 687b ldr r3, [r7, #4]
800a0bc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a0c0: b2db uxtb r3, r3
800a0c2: 3b01 subs r3, #1
800a0c4: 2b02 cmp r3, #2
800a0c6: d840 bhi.n 800a14a <USBD_StdItfReq+0xb6>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
800a0c8: 683b ldr r3, [r7, #0]
800a0ca: 889b ldrh r3, [r3, #4]
800a0cc: b2db uxtb r3, r3
800a0ce: 2b01 cmp r3, #1
800a0d0: d836 bhi.n 800a140 <USBD_StdItfReq+0xac>
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
800a0d2: 683b ldr r3, [r7, #0]
800a0d4: 889b ldrh r3, [r3, #4]
800a0d6: b2db uxtb r3, r3
800a0d8: 4619 mov r1, r3
800a0da: 6878 ldr r0, [r7, #4]
800a0dc: f7ff ff2f bl 8009f3e <USBD_CoreFindIF>
800a0e0: 4603 mov r3, r0
800a0e2: 73bb strb r3, [r7, #14]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
800a0e4: 7bbb ldrb r3, [r7, #14]
800a0e6: 2bff cmp r3, #255 @ 0xff
800a0e8: d01d beq.n 800a126 <USBD_StdItfReq+0x92>
800a0ea: 7bbb ldrb r3, [r7, #14]
800a0ec: 2b00 cmp r3, #0
800a0ee: d11a bne.n 800a126 <USBD_StdItfReq+0x92>
{
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
800a0f0: 7bba ldrb r2, [r7, #14]
800a0f2: 687b ldr r3, [r7, #4]
800a0f4: 32ae adds r2, #174 @ 0xae
800a0f6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800a0fa: 689b ldr r3, [r3, #8]
800a0fc: 2b00 cmp r3, #0
800a0fe: d00f beq.n 800a120 <USBD_StdItfReq+0x8c>
{
pdev->classId = idx;
800a100: 7bba ldrb r2, [r7, #14]
800a102: 687b ldr r3, [r7, #4]
800a104: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
800a108: 7bba ldrb r2, [r7, #14]
800a10a: 687b ldr r3, [r7, #4]
800a10c: 32ae adds r2, #174 @ 0xae
800a10e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800a112: 689b ldr r3, [r3, #8]
800a114: 6839 ldr r1, [r7, #0]
800a116: 6878 ldr r0, [r7, #4]
800a118: 4798 blx r3
800a11a: 4603 mov r3, r0
800a11c: 73fb strb r3, [r7, #15]
if (pdev->pClass[idx]->Setup != NULL)
800a11e: e004 b.n 800a12a <USBD_StdItfReq+0x96>
}
else
{
/* should never reach this condition */
ret = USBD_FAIL;
800a120: 2303 movs r3, #3
800a122: 73fb strb r3, [r7, #15]
if (pdev->pClass[idx]->Setup != NULL)
800a124: e001 b.n 800a12a <USBD_StdItfReq+0x96>
}
}
else
{
/* No relative interface found */
ret = USBD_FAIL;
800a126: 2303 movs r3, #3
800a128: 73fb strb r3, [r7, #15]
}
if ((req->wLength == 0U) && (ret == USBD_OK))
800a12a: 683b ldr r3, [r7, #0]
800a12c: 88db ldrh r3, [r3, #6]
800a12e: 2b00 cmp r3, #0
800a130: d110 bne.n 800a154 <USBD_StdItfReq+0xc0>
800a132: 7bfb ldrb r3, [r7, #15]
800a134: 2b00 cmp r3, #0
800a136: d10d bne.n 800a154 <USBD_StdItfReq+0xc0>
{
(void)USBD_CtlSendStatus(pdev);
800a138: 6878 ldr r0, [r7, #4]
800a13a: f000 fde0 bl 800acfe <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
break;
800a13e: e009 b.n 800a154 <USBD_StdItfReq+0xc0>
USBD_CtlError(pdev, req);
800a140: 6839 ldr r1, [r7, #0]
800a142: 6878 ldr r0, [r7, #4]
800a144: f000 fd21 bl 800ab8a <USBD_CtlError>
break;
800a148: e004 b.n 800a154 <USBD_StdItfReq+0xc0>
default:
USBD_CtlError(pdev, req);
800a14a: 6839 ldr r1, [r7, #0]
800a14c: 6878 ldr r0, [r7, #4]
800a14e: f000 fd1c bl 800ab8a <USBD_CtlError>
break;
800a152: e000 b.n 800a156 <USBD_StdItfReq+0xc2>
break;
800a154: bf00 nop
}
break;
800a156: e004 b.n 800a162 <USBD_StdItfReq+0xce>
default:
USBD_CtlError(pdev, req);
800a158: 6839 ldr r1, [r7, #0]
800a15a: 6878 ldr r0, [r7, #4]
800a15c: f000 fd15 bl 800ab8a <USBD_CtlError>
break;
800a160: bf00 nop
}
return ret;
800a162: 7bfb ldrb r3, [r7, #15]
}
800a164: 4618 mov r0, r3
800a166: 3710 adds r7, #16
800a168: 46bd mov sp, r7
800a16a: bd80 pop {r7, pc}
0800a16c <USBD_StdEPReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a16c: b580 push {r7, lr}
800a16e: b084 sub sp, #16
800a170: af00 add r7, sp, #0
800a172: 6078 str r0, [r7, #4]
800a174: 6039 str r1, [r7, #0]
USBD_EndpointTypeDef *pep;
uint8_t ep_addr;
uint8_t idx;
USBD_StatusTypeDef ret = USBD_OK;
800a176: 2300 movs r3, #0
800a178: 73fb strb r3, [r7, #15]
ep_addr = LOBYTE(req->wIndex);
800a17a: 683b ldr r3, [r7, #0]
800a17c: 889b ldrh r3, [r3, #4]
800a17e: 73bb strb r3, [r7, #14]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800a180: 683b ldr r3, [r7, #0]
800a182: 781b ldrb r3, [r3, #0]
800a184: f003 0360 and.w r3, r3, #96 @ 0x60
800a188: 2b40 cmp r3, #64 @ 0x40
800a18a: d007 beq.n 800a19c <USBD_StdEPReq+0x30>
800a18c: 2b40 cmp r3, #64 @ 0x40
800a18e: f200 817f bhi.w 800a490 <USBD_StdEPReq+0x324>
800a192: 2b00 cmp r3, #0
800a194: d02a beq.n 800a1ec <USBD_StdEPReq+0x80>
800a196: 2b20 cmp r3, #32
800a198: f040 817a bne.w 800a490 <USBD_StdEPReq+0x324>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
/* Get the class index relative to this endpoint */
idx = USBD_CoreFindEP(pdev, ep_addr);
800a19c: 7bbb ldrb r3, [r7, #14]
800a19e: 4619 mov r1, r3
800a1a0: 6878 ldr r0, [r7, #4]
800a1a2: f7ff fed9 bl 8009f58 <USBD_CoreFindEP>
800a1a6: 4603 mov r3, r0
800a1a8: 737b strb r3, [r7, #13]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
800a1aa: 7b7b ldrb r3, [r7, #13]
800a1ac: 2bff cmp r3, #255 @ 0xff
800a1ae: f000 8174 beq.w 800a49a <USBD_StdEPReq+0x32e>
800a1b2: 7b7b ldrb r3, [r7, #13]
800a1b4: 2b00 cmp r3, #0
800a1b6: f040 8170 bne.w 800a49a <USBD_StdEPReq+0x32e>
{
pdev->classId = idx;
800a1ba: 7b7a ldrb r2, [r7, #13]
800a1bc: 687b ldr r3, [r7, #4]
800a1be: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
800a1c2: 7b7a ldrb r2, [r7, #13]
800a1c4: 687b ldr r3, [r7, #4]
800a1c6: 32ae adds r2, #174 @ 0xae
800a1c8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800a1cc: 689b ldr r3, [r3, #8]
800a1ce: 2b00 cmp r3, #0
800a1d0: f000 8163 beq.w 800a49a <USBD_StdEPReq+0x32e>
{
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
800a1d4: 7b7a ldrb r2, [r7, #13]
800a1d6: 687b ldr r3, [r7, #4]
800a1d8: 32ae adds r2, #174 @ 0xae
800a1da: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800a1de: 689b ldr r3, [r3, #8]
800a1e0: 6839 ldr r1, [r7, #0]
800a1e2: 6878 ldr r0, [r7, #4]
800a1e4: 4798 blx r3
800a1e6: 4603 mov r3, r0
800a1e8: 73fb strb r3, [r7, #15]
}
}
break;
800a1ea: e156 b.n 800a49a <USBD_StdEPReq+0x32e>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
800a1ec: 683b ldr r3, [r7, #0]
800a1ee: 785b ldrb r3, [r3, #1]
800a1f0: 2b03 cmp r3, #3
800a1f2: d008 beq.n 800a206 <USBD_StdEPReq+0x9a>
800a1f4: 2b03 cmp r3, #3
800a1f6: f300 8145 bgt.w 800a484 <USBD_StdEPReq+0x318>
800a1fa: 2b00 cmp r3, #0
800a1fc: f000 809b beq.w 800a336 <USBD_StdEPReq+0x1ca>
800a200: 2b01 cmp r3, #1
800a202: d03c beq.n 800a27e <USBD_StdEPReq+0x112>
800a204: e13e b.n 800a484 <USBD_StdEPReq+0x318>
{
case USB_REQ_SET_FEATURE:
switch (pdev->dev_state)
800a206: 687b ldr r3, [r7, #4]
800a208: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a20c: b2db uxtb r3, r3
800a20e: 2b02 cmp r3, #2
800a210: d002 beq.n 800a218 <USBD_StdEPReq+0xac>
800a212: 2b03 cmp r3, #3
800a214: d016 beq.n 800a244 <USBD_StdEPReq+0xd8>
800a216: e02c b.n 800a272 <USBD_StdEPReq+0x106>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
800a218: 7bbb ldrb r3, [r7, #14]
800a21a: 2b00 cmp r3, #0
800a21c: d00d beq.n 800a23a <USBD_StdEPReq+0xce>
800a21e: 7bbb ldrb r3, [r7, #14]
800a220: 2b80 cmp r3, #128 @ 0x80
800a222: d00a beq.n 800a23a <USBD_StdEPReq+0xce>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
800a224: 7bbb ldrb r3, [r7, #14]
800a226: 4619 mov r1, r3
800a228: 6878 ldr r0, [r7, #4]
800a22a: f001 f96b bl 800b504 <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0x80U);
800a22e: 2180 movs r1, #128 @ 0x80
800a230: 6878 ldr r0, [r7, #4]
800a232: f001 f967 bl 800b504 <USBD_LL_StallEP>
800a236: bf00 nop
}
else
{
USBD_CtlError(pdev, req);
}
break;
800a238: e020 b.n 800a27c <USBD_StdEPReq+0x110>
USBD_CtlError(pdev, req);
800a23a: 6839 ldr r1, [r7, #0]
800a23c: 6878 ldr r0, [r7, #4]
800a23e: f000 fca4 bl 800ab8a <USBD_CtlError>
break;
800a242: e01b b.n 800a27c <USBD_StdEPReq+0x110>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
800a244: 683b ldr r3, [r7, #0]
800a246: 885b ldrh r3, [r3, #2]
800a248: 2b00 cmp r3, #0
800a24a: d10e bne.n 800a26a <USBD_StdEPReq+0xfe>
{
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
800a24c: 7bbb ldrb r3, [r7, #14]
800a24e: 2b00 cmp r3, #0
800a250: d00b beq.n 800a26a <USBD_StdEPReq+0xfe>
800a252: 7bbb ldrb r3, [r7, #14]
800a254: 2b80 cmp r3, #128 @ 0x80
800a256: d008 beq.n 800a26a <USBD_StdEPReq+0xfe>
800a258: 683b ldr r3, [r7, #0]
800a25a: 88db ldrh r3, [r3, #6]
800a25c: 2b00 cmp r3, #0
800a25e: d104 bne.n 800a26a <USBD_StdEPReq+0xfe>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
800a260: 7bbb ldrb r3, [r7, #14]
800a262: 4619 mov r1, r3
800a264: 6878 ldr r0, [r7, #4]
800a266: f001 f94d bl 800b504 <USBD_LL_StallEP>
}
}
(void)USBD_CtlSendStatus(pdev);
800a26a: 6878 ldr r0, [r7, #4]
800a26c: f000 fd47 bl 800acfe <USBD_CtlSendStatus>
break;
800a270: e004 b.n 800a27c <USBD_StdEPReq+0x110>
default:
USBD_CtlError(pdev, req);
800a272: 6839 ldr r1, [r7, #0]
800a274: 6878 ldr r0, [r7, #4]
800a276: f000 fc88 bl 800ab8a <USBD_CtlError>
break;
800a27a: bf00 nop
}
break;
800a27c: e107 b.n 800a48e <USBD_StdEPReq+0x322>
case USB_REQ_CLEAR_FEATURE:
switch (pdev->dev_state)
800a27e: 687b ldr r3, [r7, #4]
800a280: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a284: b2db uxtb r3, r3
800a286: 2b02 cmp r3, #2
800a288: d002 beq.n 800a290 <USBD_StdEPReq+0x124>
800a28a: 2b03 cmp r3, #3
800a28c: d016 beq.n 800a2bc <USBD_StdEPReq+0x150>
800a28e: e04b b.n 800a328 <USBD_StdEPReq+0x1bc>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
800a290: 7bbb ldrb r3, [r7, #14]
800a292: 2b00 cmp r3, #0
800a294: d00d beq.n 800a2b2 <USBD_StdEPReq+0x146>
800a296: 7bbb ldrb r3, [r7, #14]
800a298: 2b80 cmp r3, #128 @ 0x80
800a29a: d00a beq.n 800a2b2 <USBD_StdEPReq+0x146>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
800a29c: 7bbb ldrb r3, [r7, #14]
800a29e: 4619 mov r1, r3
800a2a0: 6878 ldr r0, [r7, #4]
800a2a2: f001 f92f bl 800b504 <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0x80U);
800a2a6: 2180 movs r1, #128 @ 0x80
800a2a8: 6878 ldr r0, [r7, #4]
800a2aa: f001 f92b bl 800b504 <USBD_LL_StallEP>
800a2ae: bf00 nop
}
else
{
USBD_CtlError(pdev, req);
}
break;
800a2b0: e040 b.n 800a334 <USBD_StdEPReq+0x1c8>
USBD_CtlError(pdev, req);
800a2b2: 6839 ldr r1, [r7, #0]
800a2b4: 6878 ldr r0, [r7, #4]
800a2b6: f000 fc68 bl 800ab8a <USBD_CtlError>
break;
800a2ba: e03b b.n 800a334 <USBD_StdEPReq+0x1c8>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
800a2bc: 683b ldr r3, [r7, #0]
800a2be: 885b ldrh r3, [r3, #2]
800a2c0: 2b00 cmp r3, #0
800a2c2: d136 bne.n 800a332 <USBD_StdEPReq+0x1c6>
{
if ((ep_addr & 0x7FU) != 0x00U)
800a2c4: 7bbb ldrb r3, [r7, #14]
800a2c6: f003 037f and.w r3, r3, #127 @ 0x7f
800a2ca: 2b00 cmp r3, #0
800a2cc: d004 beq.n 800a2d8 <USBD_StdEPReq+0x16c>
{
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
800a2ce: 7bbb ldrb r3, [r7, #14]
800a2d0: 4619 mov r1, r3
800a2d2: 6878 ldr r0, [r7, #4]
800a2d4: f001 f94c bl 800b570 <USBD_LL_ClearStallEP>
}
(void)USBD_CtlSendStatus(pdev);
800a2d8: 6878 ldr r0, [r7, #4]
800a2da: f000 fd10 bl 800acfe <USBD_CtlSendStatus>
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, ep_addr);
800a2de: 7bbb ldrb r3, [r7, #14]
800a2e0: 4619 mov r1, r3
800a2e2: 6878 ldr r0, [r7, #4]
800a2e4: f7ff fe38 bl 8009f58 <USBD_CoreFindEP>
800a2e8: 4603 mov r3, r0
800a2ea: 737b strb r3, [r7, #13]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
800a2ec: 7b7b ldrb r3, [r7, #13]
800a2ee: 2bff cmp r3, #255 @ 0xff
800a2f0: d01f beq.n 800a332 <USBD_StdEPReq+0x1c6>
800a2f2: 7b7b ldrb r3, [r7, #13]
800a2f4: 2b00 cmp r3, #0
800a2f6: d11c bne.n 800a332 <USBD_StdEPReq+0x1c6>
{
pdev->classId = idx;
800a2f8: 7b7a ldrb r2, [r7, #13]
800a2fa: 687b ldr r3, [r7, #4]
800a2fc: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
800a300: 7b7a ldrb r2, [r7, #13]
800a302: 687b ldr r3, [r7, #4]
800a304: 32ae adds r2, #174 @ 0xae
800a306: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800a30a: 689b ldr r3, [r3, #8]
800a30c: 2b00 cmp r3, #0
800a30e: d010 beq.n 800a332 <USBD_StdEPReq+0x1c6>
{
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
800a310: 7b7a ldrb r2, [r7, #13]
800a312: 687b ldr r3, [r7, #4]
800a314: 32ae adds r2, #174 @ 0xae
800a316: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800a31a: 689b ldr r3, [r3, #8]
800a31c: 6839 ldr r1, [r7, #0]
800a31e: 6878 ldr r0, [r7, #4]
800a320: 4798 blx r3
800a322: 4603 mov r3, r0
800a324: 73fb strb r3, [r7, #15]
}
}
}
break;
800a326: e004 b.n 800a332 <USBD_StdEPReq+0x1c6>
default:
USBD_CtlError(pdev, req);
800a328: 6839 ldr r1, [r7, #0]
800a32a: 6878 ldr r0, [r7, #4]
800a32c: f000 fc2d bl 800ab8a <USBD_CtlError>
break;
800a330: e000 b.n 800a334 <USBD_StdEPReq+0x1c8>
break;
800a332: bf00 nop
}
break;
800a334: e0ab b.n 800a48e <USBD_StdEPReq+0x322>
case USB_REQ_GET_STATUS:
switch (pdev->dev_state)
800a336: 687b ldr r3, [r7, #4]
800a338: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a33c: b2db uxtb r3, r3
800a33e: 2b02 cmp r3, #2
800a340: d002 beq.n 800a348 <USBD_StdEPReq+0x1dc>
800a342: 2b03 cmp r3, #3
800a344: d032 beq.n 800a3ac <USBD_StdEPReq+0x240>
800a346: e097 b.n 800a478 <USBD_StdEPReq+0x30c>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
800a348: 7bbb ldrb r3, [r7, #14]
800a34a: 2b00 cmp r3, #0
800a34c: d007 beq.n 800a35e <USBD_StdEPReq+0x1f2>
800a34e: 7bbb ldrb r3, [r7, #14]
800a350: 2b80 cmp r3, #128 @ 0x80
800a352: d004 beq.n 800a35e <USBD_StdEPReq+0x1f2>
{
USBD_CtlError(pdev, req);
800a354: 6839 ldr r1, [r7, #0]
800a356: 6878 ldr r0, [r7, #4]
800a358: f000 fc17 bl 800ab8a <USBD_CtlError>
break;
800a35c: e091 b.n 800a482 <USBD_StdEPReq+0x316>
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
800a35e: f997 300e ldrsb.w r3, [r7, #14]
800a362: 2b00 cmp r3, #0
800a364: da0b bge.n 800a37e <USBD_StdEPReq+0x212>
800a366: 7bbb ldrb r3, [r7, #14]
800a368: f003 027f and.w r2, r3, #127 @ 0x7f
800a36c: 4613 mov r3, r2
800a36e: 009b lsls r3, r3, #2
800a370: 4413 add r3, r2
800a372: 009b lsls r3, r3, #2
800a374: 3310 adds r3, #16
800a376: 687a ldr r2, [r7, #4]
800a378: 4413 add r3, r2
800a37a: 3304 adds r3, #4
800a37c: e00b b.n 800a396 <USBD_StdEPReq+0x22a>
&pdev->ep_out[ep_addr & 0x7FU];
800a37e: 7bbb ldrb r3, [r7, #14]
800a380: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
800a384: 4613 mov r3, r2
800a386: 009b lsls r3, r3, #2
800a388: 4413 add r3, r2
800a38a: 009b lsls r3, r3, #2
800a38c: f503 73a8 add.w r3, r3, #336 @ 0x150
800a390: 687a ldr r2, [r7, #4]
800a392: 4413 add r3, r2
800a394: 3304 adds r3, #4
800a396: 60bb str r3, [r7, #8]
pep->status = 0x0000U;
800a398: 68bb ldr r3, [r7, #8]
800a39a: 2200 movs r2, #0
800a39c: 601a str r2, [r3, #0]
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
800a39e: 68bb ldr r3, [r7, #8]
800a3a0: 2202 movs r2, #2
800a3a2: 4619 mov r1, r3
800a3a4: 6878 ldr r0, [r7, #4]
800a3a6: f000 fc6d bl 800ac84 <USBD_CtlSendData>
break;
800a3aa: e06a b.n 800a482 <USBD_StdEPReq+0x316>
case USBD_STATE_CONFIGURED:
if ((ep_addr & 0x80U) == 0x80U)
800a3ac: f997 300e ldrsb.w r3, [r7, #14]
800a3b0: 2b00 cmp r3, #0
800a3b2: da11 bge.n 800a3d8 <USBD_StdEPReq+0x26c>
{
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
800a3b4: 7bbb ldrb r3, [r7, #14]
800a3b6: f003 020f and.w r2, r3, #15
800a3ba: 6879 ldr r1, [r7, #4]
800a3bc: 4613 mov r3, r2
800a3be: 009b lsls r3, r3, #2
800a3c0: 4413 add r3, r2
800a3c2: 009b lsls r3, r3, #2
800a3c4: 440b add r3, r1
800a3c6: 3324 adds r3, #36 @ 0x24
800a3c8: 881b ldrh r3, [r3, #0]
800a3ca: 2b00 cmp r3, #0
800a3cc: d117 bne.n 800a3fe <USBD_StdEPReq+0x292>
{
USBD_CtlError(pdev, req);
800a3ce: 6839 ldr r1, [r7, #0]
800a3d0: 6878 ldr r0, [r7, #4]
800a3d2: f000 fbda bl 800ab8a <USBD_CtlError>
break;
800a3d6: e054 b.n 800a482 <USBD_StdEPReq+0x316>
}
}
else
{
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
800a3d8: 7bbb ldrb r3, [r7, #14]
800a3da: f003 020f and.w r2, r3, #15
800a3de: 6879 ldr r1, [r7, #4]
800a3e0: 4613 mov r3, r2
800a3e2: 009b lsls r3, r3, #2
800a3e4: 4413 add r3, r2
800a3e6: 009b lsls r3, r3, #2
800a3e8: 440b add r3, r1
800a3ea: f503 73b2 add.w r3, r3, #356 @ 0x164
800a3ee: 881b ldrh r3, [r3, #0]
800a3f0: 2b00 cmp r3, #0
800a3f2: d104 bne.n 800a3fe <USBD_StdEPReq+0x292>
{
USBD_CtlError(pdev, req);
800a3f4: 6839 ldr r1, [r7, #0]
800a3f6: 6878 ldr r0, [r7, #4]
800a3f8: f000 fbc7 bl 800ab8a <USBD_CtlError>
break;
800a3fc: e041 b.n 800a482 <USBD_StdEPReq+0x316>
}
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
800a3fe: f997 300e ldrsb.w r3, [r7, #14]
800a402: 2b00 cmp r3, #0
800a404: da0b bge.n 800a41e <USBD_StdEPReq+0x2b2>
800a406: 7bbb ldrb r3, [r7, #14]
800a408: f003 027f and.w r2, r3, #127 @ 0x7f
800a40c: 4613 mov r3, r2
800a40e: 009b lsls r3, r3, #2
800a410: 4413 add r3, r2
800a412: 009b lsls r3, r3, #2
800a414: 3310 adds r3, #16
800a416: 687a ldr r2, [r7, #4]
800a418: 4413 add r3, r2
800a41a: 3304 adds r3, #4
800a41c: e00b b.n 800a436 <USBD_StdEPReq+0x2ca>
&pdev->ep_out[ep_addr & 0x7FU];
800a41e: 7bbb ldrb r3, [r7, #14]
800a420: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
800a424: 4613 mov r3, r2
800a426: 009b lsls r3, r3, #2
800a428: 4413 add r3, r2
800a42a: 009b lsls r3, r3, #2
800a42c: f503 73a8 add.w r3, r3, #336 @ 0x150
800a430: 687a ldr r2, [r7, #4]
800a432: 4413 add r3, r2
800a434: 3304 adds r3, #4
800a436: 60bb str r3, [r7, #8]
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
800a438: 7bbb ldrb r3, [r7, #14]
800a43a: 2b00 cmp r3, #0
800a43c: d002 beq.n 800a444 <USBD_StdEPReq+0x2d8>
800a43e: 7bbb ldrb r3, [r7, #14]
800a440: 2b80 cmp r3, #128 @ 0x80
800a442: d103 bne.n 800a44c <USBD_StdEPReq+0x2e0>
{
pep->status = 0x0000U;
800a444: 68bb ldr r3, [r7, #8]
800a446: 2200 movs r2, #0
800a448: 601a str r2, [r3, #0]
800a44a: e00e b.n 800a46a <USBD_StdEPReq+0x2fe>
}
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
800a44c: 7bbb ldrb r3, [r7, #14]
800a44e: 4619 mov r1, r3
800a450: 6878 ldr r0, [r7, #4]
800a452: f001 f8c3 bl 800b5dc <USBD_LL_IsStallEP>
800a456: 4603 mov r3, r0
800a458: 2b00 cmp r3, #0
800a45a: d003 beq.n 800a464 <USBD_StdEPReq+0x2f8>
{
pep->status = 0x0001U;
800a45c: 68bb ldr r3, [r7, #8]
800a45e: 2201 movs r2, #1
800a460: 601a str r2, [r3, #0]
800a462: e002 b.n 800a46a <USBD_StdEPReq+0x2fe>
}
else
{
pep->status = 0x0000U;
800a464: 68bb ldr r3, [r7, #8]
800a466: 2200 movs r2, #0
800a468: 601a str r2, [r3, #0]
}
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
800a46a: 68bb ldr r3, [r7, #8]
800a46c: 2202 movs r2, #2
800a46e: 4619 mov r1, r3
800a470: 6878 ldr r0, [r7, #4]
800a472: f000 fc07 bl 800ac84 <USBD_CtlSendData>
break;
800a476: e004 b.n 800a482 <USBD_StdEPReq+0x316>
default:
USBD_CtlError(pdev, req);
800a478: 6839 ldr r1, [r7, #0]
800a47a: 6878 ldr r0, [r7, #4]
800a47c: f000 fb85 bl 800ab8a <USBD_CtlError>
break;
800a480: bf00 nop
}
break;
800a482: e004 b.n 800a48e <USBD_StdEPReq+0x322>
default:
USBD_CtlError(pdev, req);
800a484: 6839 ldr r1, [r7, #0]
800a486: 6878 ldr r0, [r7, #4]
800a488: f000 fb7f bl 800ab8a <USBD_CtlError>
break;
800a48c: bf00 nop
}
break;
800a48e: e005 b.n 800a49c <USBD_StdEPReq+0x330>
default:
USBD_CtlError(pdev, req);
800a490: 6839 ldr r1, [r7, #0]
800a492: 6878 ldr r0, [r7, #4]
800a494: f000 fb79 bl 800ab8a <USBD_CtlError>
break;
800a498: e000 b.n 800a49c <USBD_StdEPReq+0x330>
break;
800a49a: bf00 nop
}
return ret;
800a49c: 7bfb ldrb r3, [r7, #15]
}
800a49e: 4618 mov r0, r3
800a4a0: 3710 adds r7, #16
800a4a2: 46bd mov sp, r7
800a4a4: bd80 pop {r7, pc}
...
0800a4a8 <USBD_GetDescriptor>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a4a8: b580 push {r7, lr}
800a4aa: b084 sub sp, #16
800a4ac: af00 add r7, sp, #0
800a4ae: 6078 str r0, [r7, #4]
800a4b0: 6039 str r1, [r7, #0]
uint16_t len = 0U;
800a4b2: 2300 movs r3, #0
800a4b4: 813b strh r3, [r7, #8]
uint8_t *pbuf = NULL;
800a4b6: 2300 movs r3, #0
800a4b8: 60fb str r3, [r7, #12]
uint8_t err = 0U;
800a4ba: 2300 movs r3, #0
800a4bc: 72fb strb r3, [r7, #11]
switch (req->wValue >> 8)
800a4be: 683b ldr r3, [r7, #0]
800a4c0: 885b ldrh r3, [r3, #2]
800a4c2: 0a1b lsrs r3, r3, #8
800a4c4: b29b uxth r3, r3
800a4c6: 3b01 subs r3, #1
800a4c8: 2b0e cmp r3, #14
800a4ca: f200 8152 bhi.w 800a772 <USBD_GetDescriptor+0x2ca>
800a4ce: a201 add r2, pc, #4 @ (adr r2, 800a4d4 <USBD_GetDescriptor+0x2c>)
800a4d0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a4d4: 0800a545 .word 0x0800a545
800a4d8: 0800a55d .word 0x0800a55d
800a4dc: 0800a59d .word 0x0800a59d
800a4e0: 0800a773 .word 0x0800a773
800a4e4: 0800a773 .word 0x0800a773
800a4e8: 0800a713 .word 0x0800a713
800a4ec: 0800a73f .word 0x0800a73f
800a4f0: 0800a773 .word 0x0800a773
800a4f4: 0800a773 .word 0x0800a773
800a4f8: 0800a773 .word 0x0800a773
800a4fc: 0800a773 .word 0x0800a773
800a500: 0800a773 .word 0x0800a773
800a504: 0800a773 .word 0x0800a773
800a508: 0800a773 .word 0x0800a773
800a50c: 0800a511 .word 0x0800a511
{
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
case USB_DESC_TYPE_BOS:
if (pdev->pDesc->GetBOSDescriptor != NULL)
800a510: 687b ldr r3, [r7, #4]
800a512: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a516: 69db ldr r3, [r3, #28]
800a518: 2b00 cmp r3, #0
800a51a: d00b beq.n 800a534 <USBD_GetDescriptor+0x8c>
{
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
800a51c: 687b ldr r3, [r7, #4]
800a51e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a522: 69db ldr r3, [r3, #28]
800a524: 687a ldr r2, [r7, #4]
800a526: 7c12 ldrb r2, [r2, #16]
800a528: f107 0108 add.w r1, r7, #8
800a52c: 4610 mov r0, r2
800a52e: 4798 blx r3
800a530: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a532: e126 b.n 800a782 <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
800a534: 6839 ldr r1, [r7, #0]
800a536: 6878 ldr r0, [r7, #4]
800a538: f000 fb27 bl 800ab8a <USBD_CtlError>
err++;
800a53c: 7afb ldrb r3, [r7, #11]
800a53e: 3301 adds r3, #1
800a540: 72fb strb r3, [r7, #11]
break;
800a542: e11e b.n 800a782 <USBD_GetDescriptor+0x2da>
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
case USB_DESC_TYPE_DEVICE:
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
800a544: 687b ldr r3, [r7, #4]
800a546: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a54a: 681b ldr r3, [r3, #0]
800a54c: 687a ldr r2, [r7, #4]
800a54e: 7c12 ldrb r2, [r2, #16]
800a550: f107 0108 add.w r1, r7, #8
800a554: 4610 mov r0, r2
800a556: 4798 blx r3
800a558: 60f8 str r0, [r7, #12]
break;
800a55a: e112 b.n 800a782 <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a55c: 687b ldr r3, [r7, #4]
800a55e: 7c1b ldrb r3, [r3, #16]
800a560: 2b00 cmp r3, #0
800a562: d10d bne.n 800a580 <USBD_GetDescriptor+0xd8>
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
800a564: 687b ldr r3, [r7, #4]
800a566: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a56a: 6a9b ldr r3, [r3, #40] @ 0x28
800a56c: f107 0208 add.w r2, r7, #8
800a570: 4610 mov r0, r2
800a572: 4798 blx r3
800a574: 60f8 str r0, [r7, #12]
}
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800a576: 68fb ldr r3, [r7, #12]
800a578: 3301 adds r3, #1
800a57a: 2202 movs r2, #2
800a57c: 701a strb r2, [r3, #0]
{
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
}
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
}
break;
800a57e: e100 b.n 800a782 <USBD_GetDescriptor+0x2da>
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
800a580: 687b ldr r3, [r7, #4]
800a582: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a586: 6adb ldr r3, [r3, #44] @ 0x2c
800a588: f107 0208 add.w r2, r7, #8
800a58c: 4610 mov r0, r2
800a58e: 4798 blx r3
800a590: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800a592: 68fb ldr r3, [r7, #12]
800a594: 3301 adds r3, #1
800a596: 2202 movs r2, #2
800a598: 701a strb r2, [r3, #0]
break;
800a59a: e0f2 b.n 800a782 <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_STRING:
switch ((uint8_t)(req->wValue))
800a59c: 683b ldr r3, [r7, #0]
800a59e: 885b ldrh r3, [r3, #2]
800a5a0: b2db uxtb r3, r3
800a5a2: 2b05 cmp r3, #5
800a5a4: f200 80ac bhi.w 800a700 <USBD_GetDescriptor+0x258>
800a5a8: a201 add r2, pc, #4 @ (adr r2, 800a5b0 <USBD_GetDescriptor+0x108>)
800a5aa: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a5ae: bf00 nop
800a5b0: 0800a5c9 .word 0x0800a5c9
800a5b4: 0800a5fd .word 0x0800a5fd
800a5b8: 0800a631 .word 0x0800a631
800a5bc: 0800a665 .word 0x0800a665
800a5c0: 0800a699 .word 0x0800a699
800a5c4: 0800a6cd .word 0x0800a6cd
{
case USBD_IDX_LANGID_STR:
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
800a5c8: 687b ldr r3, [r7, #4]
800a5ca: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a5ce: 685b ldr r3, [r3, #4]
800a5d0: 2b00 cmp r3, #0
800a5d2: d00b beq.n 800a5ec <USBD_GetDescriptor+0x144>
{
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
800a5d4: 687b ldr r3, [r7, #4]
800a5d6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a5da: 685b ldr r3, [r3, #4]
800a5dc: 687a ldr r2, [r7, #4]
800a5de: 7c12 ldrb r2, [r2, #16]
800a5e0: f107 0108 add.w r1, r7, #8
800a5e4: 4610 mov r0, r2
800a5e6: 4798 blx r3
800a5e8: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a5ea: e091 b.n 800a710 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
800a5ec: 6839 ldr r1, [r7, #0]
800a5ee: 6878 ldr r0, [r7, #4]
800a5f0: f000 facb bl 800ab8a <USBD_CtlError>
err++;
800a5f4: 7afb ldrb r3, [r7, #11]
800a5f6: 3301 adds r3, #1
800a5f8: 72fb strb r3, [r7, #11]
break;
800a5fa: e089 b.n 800a710 <USBD_GetDescriptor+0x268>
case USBD_IDX_MFC_STR:
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
800a5fc: 687b ldr r3, [r7, #4]
800a5fe: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a602: 689b ldr r3, [r3, #8]
800a604: 2b00 cmp r3, #0
800a606: d00b beq.n 800a620 <USBD_GetDescriptor+0x178>
{
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
800a608: 687b ldr r3, [r7, #4]
800a60a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a60e: 689b ldr r3, [r3, #8]
800a610: 687a ldr r2, [r7, #4]
800a612: 7c12 ldrb r2, [r2, #16]
800a614: f107 0108 add.w r1, r7, #8
800a618: 4610 mov r0, r2
800a61a: 4798 blx r3
800a61c: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a61e: e077 b.n 800a710 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
800a620: 6839 ldr r1, [r7, #0]
800a622: 6878 ldr r0, [r7, #4]
800a624: f000 fab1 bl 800ab8a <USBD_CtlError>
err++;
800a628: 7afb ldrb r3, [r7, #11]
800a62a: 3301 adds r3, #1
800a62c: 72fb strb r3, [r7, #11]
break;
800a62e: e06f b.n 800a710 <USBD_GetDescriptor+0x268>
case USBD_IDX_PRODUCT_STR:
if (pdev->pDesc->GetProductStrDescriptor != NULL)
800a630: 687b ldr r3, [r7, #4]
800a632: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a636: 68db ldr r3, [r3, #12]
800a638: 2b00 cmp r3, #0
800a63a: d00b beq.n 800a654 <USBD_GetDescriptor+0x1ac>
{
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
800a63c: 687b ldr r3, [r7, #4]
800a63e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a642: 68db ldr r3, [r3, #12]
800a644: 687a ldr r2, [r7, #4]
800a646: 7c12 ldrb r2, [r2, #16]
800a648: f107 0108 add.w r1, r7, #8
800a64c: 4610 mov r0, r2
800a64e: 4798 blx r3
800a650: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a652: e05d b.n 800a710 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
800a654: 6839 ldr r1, [r7, #0]
800a656: 6878 ldr r0, [r7, #4]
800a658: f000 fa97 bl 800ab8a <USBD_CtlError>
err++;
800a65c: 7afb ldrb r3, [r7, #11]
800a65e: 3301 adds r3, #1
800a660: 72fb strb r3, [r7, #11]
break;
800a662: e055 b.n 800a710 <USBD_GetDescriptor+0x268>
case USBD_IDX_SERIAL_STR:
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
800a664: 687b ldr r3, [r7, #4]
800a666: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a66a: 691b ldr r3, [r3, #16]
800a66c: 2b00 cmp r3, #0
800a66e: d00b beq.n 800a688 <USBD_GetDescriptor+0x1e0>
{
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
800a670: 687b ldr r3, [r7, #4]
800a672: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a676: 691b ldr r3, [r3, #16]
800a678: 687a ldr r2, [r7, #4]
800a67a: 7c12 ldrb r2, [r2, #16]
800a67c: f107 0108 add.w r1, r7, #8
800a680: 4610 mov r0, r2
800a682: 4798 blx r3
800a684: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a686: e043 b.n 800a710 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
800a688: 6839 ldr r1, [r7, #0]
800a68a: 6878 ldr r0, [r7, #4]
800a68c: f000 fa7d bl 800ab8a <USBD_CtlError>
err++;
800a690: 7afb ldrb r3, [r7, #11]
800a692: 3301 adds r3, #1
800a694: 72fb strb r3, [r7, #11]
break;
800a696: e03b b.n 800a710 <USBD_GetDescriptor+0x268>
case USBD_IDX_CONFIG_STR:
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
800a698: 687b ldr r3, [r7, #4]
800a69a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a69e: 695b ldr r3, [r3, #20]
800a6a0: 2b00 cmp r3, #0
800a6a2: d00b beq.n 800a6bc <USBD_GetDescriptor+0x214>
{
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
800a6a4: 687b ldr r3, [r7, #4]
800a6a6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a6aa: 695b ldr r3, [r3, #20]
800a6ac: 687a ldr r2, [r7, #4]
800a6ae: 7c12 ldrb r2, [r2, #16]
800a6b0: f107 0108 add.w r1, r7, #8
800a6b4: 4610 mov r0, r2
800a6b6: 4798 blx r3
800a6b8: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a6ba: e029 b.n 800a710 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
800a6bc: 6839 ldr r1, [r7, #0]
800a6be: 6878 ldr r0, [r7, #4]
800a6c0: f000 fa63 bl 800ab8a <USBD_CtlError>
err++;
800a6c4: 7afb ldrb r3, [r7, #11]
800a6c6: 3301 adds r3, #1
800a6c8: 72fb strb r3, [r7, #11]
break;
800a6ca: e021 b.n 800a710 <USBD_GetDescriptor+0x268>
case USBD_IDX_INTERFACE_STR:
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
800a6cc: 687b ldr r3, [r7, #4]
800a6ce: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a6d2: 699b ldr r3, [r3, #24]
800a6d4: 2b00 cmp r3, #0
800a6d6: d00b beq.n 800a6f0 <USBD_GetDescriptor+0x248>
{
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
800a6d8: 687b ldr r3, [r7, #4]
800a6da: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a6de: 699b ldr r3, [r3, #24]
800a6e0: 687a ldr r2, [r7, #4]
800a6e2: 7c12 ldrb r2, [r2, #16]
800a6e4: f107 0108 add.w r1, r7, #8
800a6e8: 4610 mov r0, r2
800a6ea: 4798 blx r3
800a6ec: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a6ee: e00f b.n 800a710 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
800a6f0: 6839 ldr r1, [r7, #0]
800a6f2: 6878 ldr r0, [r7, #4]
800a6f4: f000 fa49 bl 800ab8a <USBD_CtlError>
err++;
800a6f8: 7afb ldrb r3, [r7, #11]
800a6fa: 3301 adds r3, #1
800a6fc: 72fb strb r3, [r7, #11]
break;
800a6fe: e007 b.n 800a710 <USBD_GetDescriptor+0x268>
err++;
}
#endif /* USBD_SUPPORT_USER_STRING_DESC */
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
USBD_CtlError(pdev, req);
800a700: 6839 ldr r1, [r7, #0]
800a702: 6878 ldr r0, [r7, #4]
800a704: f000 fa41 bl 800ab8a <USBD_CtlError>
err++;
800a708: 7afb ldrb r3, [r7, #11]
800a70a: 3301 adds r3, #1
800a70c: 72fb strb r3, [r7, #11]
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
break;
800a70e: bf00 nop
}
break;
800a710: e037 b.n 800a782 <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_DEVICE_QUALIFIER:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a712: 687b ldr r3, [r7, #4]
800a714: 7c1b ldrb r3, [r3, #16]
800a716: 2b00 cmp r3, #0
800a718: d109 bne.n 800a72e <USBD_GetDescriptor+0x286>
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
800a71a: 687b ldr r3, [r7, #4]
800a71c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a720: 6b5b ldr r3, [r3, #52] @ 0x34
800a722: f107 0208 add.w r2, r7, #8
800a726: 4610 mov r0, r2
800a728: 4798 blx r3
800a72a: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a72c: e029 b.n 800a782 <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
800a72e: 6839 ldr r1, [r7, #0]
800a730: 6878 ldr r0, [r7, #4]
800a732: f000 fa2a bl 800ab8a <USBD_CtlError>
err++;
800a736: 7afb ldrb r3, [r7, #11]
800a738: 3301 adds r3, #1
800a73a: 72fb strb r3, [r7, #11]
break;
800a73c: e021 b.n 800a782 <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a73e: 687b ldr r3, [r7, #4]
800a740: 7c1b ldrb r3, [r3, #16]
800a742: 2b00 cmp r3, #0
800a744: d10d bne.n 800a762 <USBD_GetDescriptor+0x2ba>
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
800a746: 687b ldr r3, [r7, #4]
800a748: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a74c: 6b1b ldr r3, [r3, #48] @ 0x30
800a74e: f107 0208 add.w r2, r7, #8
800a752: 4610 mov r0, r2
800a754: 4798 blx r3
800a756: 60f8 str r0, [r7, #12]
}
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
800a758: 68fb ldr r3, [r7, #12]
800a75a: 3301 adds r3, #1
800a75c: 2207 movs r2, #7
800a75e: 701a strb r2, [r3, #0]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a760: e00f b.n 800a782 <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
800a762: 6839 ldr r1, [r7, #0]
800a764: 6878 ldr r0, [r7, #4]
800a766: f000 fa10 bl 800ab8a <USBD_CtlError>
err++;
800a76a: 7afb ldrb r3, [r7, #11]
800a76c: 3301 adds r3, #1
800a76e: 72fb strb r3, [r7, #11]
break;
800a770: e007 b.n 800a782 <USBD_GetDescriptor+0x2da>
default:
USBD_CtlError(pdev, req);
800a772: 6839 ldr r1, [r7, #0]
800a774: 6878 ldr r0, [r7, #4]
800a776: f000 fa08 bl 800ab8a <USBD_CtlError>
err++;
800a77a: 7afb ldrb r3, [r7, #11]
800a77c: 3301 adds r3, #1
800a77e: 72fb strb r3, [r7, #11]
break;
800a780: bf00 nop
}
if (err != 0U)
800a782: 7afb ldrb r3, [r7, #11]
800a784: 2b00 cmp r3, #0
800a786: d11e bne.n 800a7c6 <USBD_GetDescriptor+0x31e>
{
return;
}
if (req->wLength != 0U)
800a788: 683b ldr r3, [r7, #0]
800a78a: 88db ldrh r3, [r3, #6]
800a78c: 2b00 cmp r3, #0
800a78e: d016 beq.n 800a7be <USBD_GetDescriptor+0x316>
{
if (len != 0U)
800a790: 893b ldrh r3, [r7, #8]
800a792: 2b00 cmp r3, #0
800a794: d00e beq.n 800a7b4 <USBD_GetDescriptor+0x30c>
{
len = MIN(len, req->wLength);
800a796: 683b ldr r3, [r7, #0]
800a798: 88da ldrh r2, [r3, #6]
800a79a: 893b ldrh r3, [r7, #8]
800a79c: 4293 cmp r3, r2
800a79e: bf28 it cs
800a7a0: 4613 movcs r3, r2
800a7a2: b29b uxth r3, r3
800a7a4: 813b strh r3, [r7, #8]
(void)USBD_CtlSendData(pdev, pbuf, len);
800a7a6: 893b ldrh r3, [r7, #8]
800a7a8: 461a mov r2, r3
800a7aa: 68f9 ldr r1, [r7, #12]
800a7ac: 6878 ldr r0, [r7, #4]
800a7ae: f000 fa69 bl 800ac84 <USBD_CtlSendData>
800a7b2: e009 b.n 800a7c8 <USBD_GetDescriptor+0x320>
}
else
{
USBD_CtlError(pdev, req);
800a7b4: 6839 ldr r1, [r7, #0]
800a7b6: 6878 ldr r0, [r7, #4]
800a7b8: f000 f9e7 bl 800ab8a <USBD_CtlError>
800a7bc: e004 b.n 800a7c8 <USBD_GetDescriptor+0x320>
}
}
else
{
(void)USBD_CtlSendStatus(pdev);
800a7be: 6878 ldr r0, [r7, #4]
800a7c0: f000 fa9d bl 800acfe <USBD_CtlSendStatus>
800a7c4: e000 b.n 800a7c8 <USBD_GetDescriptor+0x320>
return;
800a7c6: bf00 nop
}
}
800a7c8: 3710 adds r7, #16
800a7ca: 46bd mov sp, r7
800a7cc: bd80 pop {r7, pc}
800a7ce: bf00 nop
0800a7d0 <USBD_SetAddress>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a7d0: b580 push {r7, lr}
800a7d2: b084 sub sp, #16
800a7d4: af00 add r7, sp, #0
800a7d6: 6078 str r0, [r7, #4]
800a7d8: 6039 str r1, [r7, #0]
uint8_t dev_addr;
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
800a7da: 683b ldr r3, [r7, #0]
800a7dc: 889b ldrh r3, [r3, #4]
800a7de: 2b00 cmp r3, #0
800a7e0: d131 bne.n 800a846 <USBD_SetAddress+0x76>
800a7e2: 683b ldr r3, [r7, #0]
800a7e4: 88db ldrh r3, [r3, #6]
800a7e6: 2b00 cmp r3, #0
800a7e8: d12d bne.n 800a846 <USBD_SetAddress+0x76>
800a7ea: 683b ldr r3, [r7, #0]
800a7ec: 885b ldrh r3, [r3, #2]
800a7ee: 2b7f cmp r3, #127 @ 0x7f
800a7f0: d829 bhi.n 800a846 <USBD_SetAddress+0x76>
{
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
800a7f2: 683b ldr r3, [r7, #0]
800a7f4: 885b ldrh r3, [r3, #2]
800a7f6: b2db uxtb r3, r3
800a7f8: f003 037f and.w r3, r3, #127 @ 0x7f
800a7fc: 73fb strb r3, [r7, #15]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a7fe: 687b ldr r3, [r7, #4]
800a800: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a804: b2db uxtb r3, r3
800a806: 2b03 cmp r3, #3
800a808: d104 bne.n 800a814 <USBD_SetAddress+0x44>
{
USBD_CtlError(pdev, req);
800a80a: 6839 ldr r1, [r7, #0]
800a80c: 6878 ldr r0, [r7, #4]
800a80e: f000 f9bc bl 800ab8a <USBD_CtlError>
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a812: e01d b.n 800a850 <USBD_SetAddress+0x80>
}
else
{
pdev->dev_address = dev_addr;
800a814: 687b ldr r3, [r7, #4]
800a816: 7bfa ldrb r2, [r7, #15]
800a818: f883 229e strb.w r2, [r3, #670] @ 0x29e
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
800a81c: 7bfb ldrb r3, [r7, #15]
800a81e: 4619 mov r1, r3
800a820: 6878 ldr r0, [r7, #4]
800a822: f000 ff07 bl 800b634 <USBD_LL_SetUSBAddress>
(void)USBD_CtlSendStatus(pdev);
800a826: 6878 ldr r0, [r7, #4]
800a828: f000 fa69 bl 800acfe <USBD_CtlSendStatus>
if (dev_addr != 0U)
800a82c: 7bfb ldrb r3, [r7, #15]
800a82e: 2b00 cmp r3, #0
800a830: d004 beq.n 800a83c <USBD_SetAddress+0x6c>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
800a832: 687b ldr r3, [r7, #4]
800a834: 2202 movs r2, #2
800a836: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a83a: e009 b.n 800a850 <USBD_SetAddress+0x80>
}
else
{
pdev->dev_state = USBD_STATE_DEFAULT;
800a83c: 687b ldr r3, [r7, #4]
800a83e: 2201 movs r2, #1
800a840: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a844: e004 b.n 800a850 <USBD_SetAddress+0x80>
}
}
}
else
{
USBD_CtlError(pdev, req);
800a846: 6839 ldr r1, [r7, #0]
800a848: 6878 ldr r0, [r7, #4]
800a84a: f000 f99e bl 800ab8a <USBD_CtlError>
}
}
800a84e: bf00 nop
800a850: bf00 nop
800a852: 3710 adds r7, #16
800a854: 46bd mov sp, r7
800a856: bd80 pop {r7, pc}
0800a858 <USBD_SetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a858: b580 push {r7, lr}
800a85a: b084 sub sp, #16
800a85c: af00 add r7, sp, #0
800a85e: 6078 str r0, [r7, #4]
800a860: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
800a862: 2300 movs r3, #0
800a864: 73fb strb r3, [r7, #15]
static uint8_t cfgidx;
cfgidx = (uint8_t)(req->wValue);
800a866: 683b ldr r3, [r7, #0]
800a868: 885b ldrh r3, [r3, #2]
800a86a: b2da uxtb r2, r3
800a86c: 4b4e ldr r3, [pc, #312] @ (800a9a8 <USBD_SetConfig+0x150>)
800a86e: 701a strb r2, [r3, #0]
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
800a870: 4b4d ldr r3, [pc, #308] @ (800a9a8 <USBD_SetConfig+0x150>)
800a872: 781b ldrb r3, [r3, #0]
800a874: 2b01 cmp r3, #1
800a876: d905 bls.n 800a884 <USBD_SetConfig+0x2c>
{
USBD_CtlError(pdev, req);
800a878: 6839 ldr r1, [r7, #0]
800a87a: 6878 ldr r0, [r7, #4]
800a87c: f000 f985 bl 800ab8a <USBD_CtlError>
return USBD_FAIL;
800a880: 2303 movs r3, #3
800a882: e08c b.n 800a99e <USBD_SetConfig+0x146>
}
switch (pdev->dev_state)
800a884: 687b ldr r3, [r7, #4]
800a886: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a88a: b2db uxtb r3, r3
800a88c: 2b02 cmp r3, #2
800a88e: d002 beq.n 800a896 <USBD_SetConfig+0x3e>
800a890: 2b03 cmp r3, #3
800a892: d029 beq.n 800a8e8 <USBD_SetConfig+0x90>
800a894: e075 b.n 800a982 <USBD_SetConfig+0x12a>
{
case USBD_STATE_ADDRESSED:
if (cfgidx != 0U)
800a896: 4b44 ldr r3, [pc, #272] @ (800a9a8 <USBD_SetConfig+0x150>)
800a898: 781b ldrb r3, [r3, #0]
800a89a: 2b00 cmp r3, #0
800a89c: d020 beq.n 800a8e0 <USBD_SetConfig+0x88>
{
pdev->dev_config = cfgidx;
800a89e: 4b42 ldr r3, [pc, #264] @ (800a9a8 <USBD_SetConfig+0x150>)
800a8a0: 781b ldrb r3, [r3, #0]
800a8a2: 461a mov r2, r3
800a8a4: 687b ldr r3, [r7, #4]
800a8a6: 605a str r2, [r3, #4]
ret = USBD_SetClassConfig(pdev, cfgidx);
800a8a8: 4b3f ldr r3, [pc, #252] @ (800a9a8 <USBD_SetConfig+0x150>)
800a8aa: 781b ldrb r3, [r3, #0]
800a8ac: 4619 mov r1, r3
800a8ae: 6878 ldr r0, [r7, #4]
800a8b0: f7ff f80d bl 80098ce <USBD_SetClassConfig>
800a8b4: 4603 mov r3, r0
800a8b6: 73fb strb r3, [r7, #15]
if (ret != USBD_OK)
800a8b8: 7bfb ldrb r3, [r7, #15]
800a8ba: 2b00 cmp r3, #0
800a8bc: d008 beq.n 800a8d0 <USBD_SetConfig+0x78>
{
USBD_CtlError(pdev, req);
800a8be: 6839 ldr r1, [r7, #0]
800a8c0: 6878 ldr r0, [r7, #4]
800a8c2: f000 f962 bl 800ab8a <USBD_CtlError>
pdev->dev_state = USBD_STATE_ADDRESSED;
800a8c6: 687b ldr r3, [r7, #4]
800a8c8: 2202 movs r2, #2
800a8ca: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
else
{
(void)USBD_CtlSendStatus(pdev);
}
break;
800a8ce: e065 b.n 800a99c <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
800a8d0: 6878 ldr r0, [r7, #4]
800a8d2: f000 fa14 bl 800acfe <USBD_CtlSendStatus>
pdev->dev_state = USBD_STATE_CONFIGURED;
800a8d6: 687b ldr r3, [r7, #4]
800a8d8: 2203 movs r2, #3
800a8da: f883 229c strb.w r2, [r3, #668] @ 0x29c
break;
800a8de: e05d b.n 800a99c <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
800a8e0: 6878 ldr r0, [r7, #4]
800a8e2: f000 fa0c bl 800acfe <USBD_CtlSendStatus>
break;
800a8e6: e059 b.n 800a99c <USBD_SetConfig+0x144>
case USBD_STATE_CONFIGURED:
if (cfgidx == 0U)
800a8e8: 4b2f ldr r3, [pc, #188] @ (800a9a8 <USBD_SetConfig+0x150>)
800a8ea: 781b ldrb r3, [r3, #0]
800a8ec: 2b00 cmp r3, #0
800a8ee: d112 bne.n 800a916 <USBD_SetConfig+0xbe>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
800a8f0: 687b ldr r3, [r7, #4]
800a8f2: 2202 movs r2, #2
800a8f4: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->dev_config = cfgidx;
800a8f8: 4b2b ldr r3, [pc, #172] @ (800a9a8 <USBD_SetConfig+0x150>)
800a8fa: 781b ldrb r3, [r3, #0]
800a8fc: 461a mov r2, r3
800a8fe: 687b ldr r3, [r7, #4]
800a900: 605a str r2, [r3, #4]
(void)USBD_ClrClassConfig(pdev, cfgidx);
800a902: 4b29 ldr r3, [pc, #164] @ (800a9a8 <USBD_SetConfig+0x150>)
800a904: 781b ldrb r3, [r3, #0]
800a906: 4619 mov r1, r3
800a908: 6878 ldr r0, [r7, #4]
800a90a: f7fe fffc bl 8009906 <USBD_ClrClassConfig>
(void)USBD_CtlSendStatus(pdev);
800a90e: 6878 ldr r0, [r7, #4]
800a910: f000 f9f5 bl 800acfe <USBD_CtlSendStatus>
}
else
{
(void)USBD_CtlSendStatus(pdev);
}
break;
800a914: e042 b.n 800a99c <USBD_SetConfig+0x144>
else if (cfgidx != pdev->dev_config)
800a916: 4b24 ldr r3, [pc, #144] @ (800a9a8 <USBD_SetConfig+0x150>)
800a918: 781b ldrb r3, [r3, #0]
800a91a: 461a mov r2, r3
800a91c: 687b ldr r3, [r7, #4]
800a91e: 685b ldr r3, [r3, #4]
800a920: 429a cmp r2, r3
800a922: d02a beq.n 800a97a <USBD_SetConfig+0x122>
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
800a924: 687b ldr r3, [r7, #4]
800a926: 685b ldr r3, [r3, #4]
800a928: b2db uxtb r3, r3
800a92a: 4619 mov r1, r3
800a92c: 6878 ldr r0, [r7, #4]
800a92e: f7fe ffea bl 8009906 <USBD_ClrClassConfig>
pdev->dev_config = cfgidx;
800a932: 4b1d ldr r3, [pc, #116] @ (800a9a8 <USBD_SetConfig+0x150>)
800a934: 781b ldrb r3, [r3, #0]
800a936: 461a mov r2, r3
800a938: 687b ldr r3, [r7, #4]
800a93a: 605a str r2, [r3, #4]
ret = USBD_SetClassConfig(pdev, cfgidx);
800a93c: 4b1a ldr r3, [pc, #104] @ (800a9a8 <USBD_SetConfig+0x150>)
800a93e: 781b ldrb r3, [r3, #0]
800a940: 4619 mov r1, r3
800a942: 6878 ldr r0, [r7, #4]
800a944: f7fe ffc3 bl 80098ce <USBD_SetClassConfig>
800a948: 4603 mov r3, r0
800a94a: 73fb strb r3, [r7, #15]
if (ret != USBD_OK)
800a94c: 7bfb ldrb r3, [r7, #15]
800a94e: 2b00 cmp r3, #0
800a950: d00f beq.n 800a972 <USBD_SetConfig+0x11a>
USBD_CtlError(pdev, req);
800a952: 6839 ldr r1, [r7, #0]
800a954: 6878 ldr r0, [r7, #4]
800a956: f000 f918 bl 800ab8a <USBD_CtlError>
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
800a95a: 687b ldr r3, [r7, #4]
800a95c: 685b ldr r3, [r3, #4]
800a95e: b2db uxtb r3, r3
800a960: 4619 mov r1, r3
800a962: 6878 ldr r0, [r7, #4]
800a964: f7fe ffcf bl 8009906 <USBD_ClrClassConfig>
pdev->dev_state = USBD_STATE_ADDRESSED;
800a968: 687b ldr r3, [r7, #4]
800a96a: 2202 movs r2, #2
800a96c: f883 229c strb.w r2, [r3, #668] @ 0x29c
break;
800a970: e014 b.n 800a99c <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
800a972: 6878 ldr r0, [r7, #4]
800a974: f000 f9c3 bl 800acfe <USBD_CtlSendStatus>
break;
800a978: e010 b.n 800a99c <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
800a97a: 6878 ldr r0, [r7, #4]
800a97c: f000 f9bf bl 800acfe <USBD_CtlSendStatus>
break;
800a980: e00c b.n 800a99c <USBD_SetConfig+0x144>
default:
USBD_CtlError(pdev, req);
800a982: 6839 ldr r1, [r7, #0]
800a984: 6878 ldr r0, [r7, #4]
800a986: f000 f900 bl 800ab8a <USBD_CtlError>
(void)USBD_ClrClassConfig(pdev, cfgidx);
800a98a: 4b07 ldr r3, [pc, #28] @ (800a9a8 <USBD_SetConfig+0x150>)
800a98c: 781b ldrb r3, [r3, #0]
800a98e: 4619 mov r1, r3
800a990: 6878 ldr r0, [r7, #4]
800a992: f7fe ffb8 bl 8009906 <USBD_ClrClassConfig>
ret = USBD_FAIL;
800a996: 2303 movs r3, #3
800a998: 73fb strb r3, [r7, #15]
break;
800a99a: bf00 nop
}
return ret;
800a99c: 7bfb ldrb r3, [r7, #15]
}
800a99e: 4618 mov r0, r3
800a9a0: 3710 adds r7, #16
800a9a2: 46bd mov sp, r7
800a9a4: bd80 pop {r7, pc}
800a9a6: bf00 nop
800a9a8: 200006cc .word 0x200006cc
0800a9ac <USBD_GetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a9ac: b580 push {r7, lr}
800a9ae: b082 sub sp, #8
800a9b0: af00 add r7, sp, #0
800a9b2: 6078 str r0, [r7, #4]
800a9b4: 6039 str r1, [r7, #0]
if (req->wLength != 1U)
800a9b6: 683b ldr r3, [r7, #0]
800a9b8: 88db ldrh r3, [r3, #6]
800a9ba: 2b01 cmp r3, #1
800a9bc: d004 beq.n 800a9c8 <USBD_GetConfig+0x1c>
{
USBD_CtlError(pdev, req);
800a9be: 6839 ldr r1, [r7, #0]
800a9c0: 6878 ldr r0, [r7, #4]
800a9c2: f000 f8e2 bl 800ab8a <USBD_CtlError>
default:
USBD_CtlError(pdev, req);
break;
}
}
}
800a9c6: e023 b.n 800aa10 <USBD_GetConfig+0x64>
switch (pdev->dev_state)
800a9c8: 687b ldr r3, [r7, #4]
800a9ca: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a9ce: b2db uxtb r3, r3
800a9d0: 2b02 cmp r3, #2
800a9d2: dc02 bgt.n 800a9da <USBD_GetConfig+0x2e>
800a9d4: 2b00 cmp r3, #0
800a9d6: dc03 bgt.n 800a9e0 <USBD_GetConfig+0x34>
800a9d8: e015 b.n 800aa06 <USBD_GetConfig+0x5a>
800a9da: 2b03 cmp r3, #3
800a9dc: d00b beq.n 800a9f6 <USBD_GetConfig+0x4a>
800a9de: e012 b.n 800aa06 <USBD_GetConfig+0x5a>
pdev->dev_default_config = 0U;
800a9e0: 687b ldr r3, [r7, #4]
800a9e2: 2200 movs r2, #0
800a9e4: 609a str r2, [r3, #8]
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
800a9e6: 687b ldr r3, [r7, #4]
800a9e8: 3308 adds r3, #8
800a9ea: 2201 movs r2, #1
800a9ec: 4619 mov r1, r3
800a9ee: 6878 ldr r0, [r7, #4]
800a9f0: f000 f948 bl 800ac84 <USBD_CtlSendData>
break;
800a9f4: e00c b.n 800aa10 <USBD_GetConfig+0x64>
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
800a9f6: 687b ldr r3, [r7, #4]
800a9f8: 3304 adds r3, #4
800a9fa: 2201 movs r2, #1
800a9fc: 4619 mov r1, r3
800a9fe: 6878 ldr r0, [r7, #4]
800aa00: f000 f940 bl 800ac84 <USBD_CtlSendData>
break;
800aa04: e004 b.n 800aa10 <USBD_GetConfig+0x64>
USBD_CtlError(pdev, req);
800aa06: 6839 ldr r1, [r7, #0]
800aa08: 6878 ldr r0, [r7, #4]
800aa0a: f000 f8be bl 800ab8a <USBD_CtlError>
break;
800aa0e: bf00 nop
}
800aa10: bf00 nop
800aa12: 3708 adds r7, #8
800aa14: 46bd mov sp, r7
800aa16: bd80 pop {r7, pc}
0800aa18 <USBD_GetStatus>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800aa18: b580 push {r7, lr}
800aa1a: b082 sub sp, #8
800aa1c: af00 add r7, sp, #0
800aa1e: 6078 str r0, [r7, #4]
800aa20: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800aa22: 687b ldr r3, [r7, #4]
800aa24: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800aa28: b2db uxtb r3, r3
800aa2a: 3b01 subs r3, #1
800aa2c: 2b02 cmp r3, #2
800aa2e: d81e bhi.n 800aa6e <USBD_GetStatus+0x56>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wLength != 0x2U)
800aa30: 683b ldr r3, [r7, #0]
800aa32: 88db ldrh r3, [r3, #6]
800aa34: 2b02 cmp r3, #2
800aa36: d004 beq.n 800aa42 <USBD_GetStatus+0x2a>
{
USBD_CtlError(pdev, req);
800aa38: 6839 ldr r1, [r7, #0]
800aa3a: 6878 ldr r0, [r7, #4]
800aa3c: f000 f8a5 bl 800ab8a <USBD_CtlError>
break;
800aa40: e01a b.n 800aa78 <USBD_GetStatus+0x60>
}
#if (USBD_SELF_POWERED == 1U)
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
800aa42: 687b ldr r3, [r7, #4]
800aa44: 2201 movs r2, #1
800aa46: 60da str r2, [r3, #12]
#else
pdev->dev_config_status = 0U;
#endif /* USBD_SELF_POWERED */
if (pdev->dev_remote_wakeup != 0U)
800aa48: 687b ldr r3, [r7, #4]
800aa4a: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
800aa4e: 2b00 cmp r3, #0
800aa50: d005 beq.n 800aa5e <USBD_GetStatus+0x46>
{
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
800aa52: 687b ldr r3, [r7, #4]
800aa54: 68db ldr r3, [r3, #12]
800aa56: f043 0202 orr.w r2, r3, #2
800aa5a: 687b ldr r3, [r7, #4]
800aa5c: 60da str r2, [r3, #12]
}
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
800aa5e: 687b ldr r3, [r7, #4]
800aa60: 330c adds r3, #12
800aa62: 2202 movs r2, #2
800aa64: 4619 mov r1, r3
800aa66: 6878 ldr r0, [r7, #4]
800aa68: f000 f90c bl 800ac84 <USBD_CtlSendData>
break;
800aa6c: e004 b.n 800aa78 <USBD_GetStatus+0x60>
default:
USBD_CtlError(pdev, req);
800aa6e: 6839 ldr r1, [r7, #0]
800aa70: 6878 ldr r0, [r7, #4]
800aa72: f000 f88a bl 800ab8a <USBD_CtlError>
break;
800aa76: bf00 nop
}
}
800aa78: bf00 nop
800aa7a: 3708 adds r7, #8
800aa7c: 46bd mov sp, r7
800aa7e: bd80 pop {r7, pc}
0800aa80 <USBD_SetFeature>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800aa80: b580 push {r7, lr}
800aa82: b082 sub sp, #8
800aa84: af00 add r7, sp, #0
800aa86: 6078 str r0, [r7, #4]
800aa88: 6039 str r1, [r7, #0]
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800aa8a: 683b ldr r3, [r7, #0]
800aa8c: 885b ldrh r3, [r3, #2]
800aa8e: 2b01 cmp r3, #1
800aa90: d107 bne.n 800aaa2 <USBD_SetFeature+0x22>
{
pdev->dev_remote_wakeup = 1U;
800aa92: 687b ldr r3, [r7, #4]
800aa94: 2201 movs r2, #1
800aa96: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
(void)USBD_CtlSendStatus(pdev);
800aa9a: 6878 ldr r0, [r7, #4]
800aa9c: f000 f92f bl 800acfe <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
}
800aaa0: e013 b.n 800aaca <USBD_SetFeature+0x4a>
else if (req->wValue == USB_FEATURE_TEST_MODE)
800aaa2: 683b ldr r3, [r7, #0]
800aaa4: 885b ldrh r3, [r3, #2]
800aaa6: 2b02 cmp r3, #2
800aaa8: d10b bne.n 800aac2 <USBD_SetFeature+0x42>
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
800aaaa: 683b ldr r3, [r7, #0]
800aaac: 889b ldrh r3, [r3, #4]
800aaae: 0a1b lsrs r3, r3, #8
800aab0: b29b uxth r3, r3
800aab2: b2da uxtb r2, r3
800aab4: 687b ldr r3, [r7, #4]
800aab6: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
(void)USBD_CtlSendStatus(pdev);
800aaba: 6878 ldr r0, [r7, #4]
800aabc: f000 f91f bl 800acfe <USBD_CtlSendStatus>
}
800aac0: e003 b.n 800aaca <USBD_SetFeature+0x4a>
USBD_CtlError(pdev, req);
800aac2: 6839 ldr r1, [r7, #0]
800aac4: 6878 ldr r0, [r7, #4]
800aac6: f000 f860 bl 800ab8a <USBD_CtlError>
}
800aaca: bf00 nop
800aacc: 3708 adds r7, #8
800aace: 46bd mov sp, r7
800aad0: bd80 pop {r7, pc}
0800aad2 <USBD_ClrFeature>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800aad2: b580 push {r7, lr}
800aad4: b082 sub sp, #8
800aad6: af00 add r7, sp, #0
800aad8: 6078 str r0, [r7, #4]
800aada: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800aadc: 687b ldr r3, [r7, #4]
800aade: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800aae2: b2db uxtb r3, r3
800aae4: 3b01 subs r3, #1
800aae6: 2b02 cmp r3, #2
800aae8: d80b bhi.n 800ab02 <USBD_ClrFeature+0x30>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800aaea: 683b ldr r3, [r7, #0]
800aaec: 885b ldrh r3, [r3, #2]
800aaee: 2b01 cmp r3, #1
800aaf0: d10c bne.n 800ab0c <USBD_ClrFeature+0x3a>
{
pdev->dev_remote_wakeup = 0U;
800aaf2: 687b ldr r3, [r7, #4]
800aaf4: 2200 movs r2, #0
800aaf6: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
(void)USBD_CtlSendStatus(pdev);
800aafa: 6878 ldr r0, [r7, #4]
800aafc: f000 f8ff bl 800acfe <USBD_CtlSendStatus>
}
break;
800ab00: e004 b.n 800ab0c <USBD_ClrFeature+0x3a>
default:
USBD_CtlError(pdev, req);
800ab02: 6839 ldr r1, [r7, #0]
800ab04: 6878 ldr r0, [r7, #4]
800ab06: f000 f840 bl 800ab8a <USBD_CtlError>
break;
800ab0a: e000 b.n 800ab0e <USBD_ClrFeature+0x3c>
break;
800ab0c: bf00 nop
}
}
800ab0e: bf00 nop
800ab10: 3708 adds r7, #8
800ab12: 46bd mov sp, r7
800ab14: bd80 pop {r7, pc}
0800ab16 <USBD_ParseSetupRequest>:
* @param req: usb request
* @param pdata: setup data pointer
* @retval None
*/
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
{
800ab16: b580 push {r7, lr}
800ab18: b084 sub sp, #16
800ab1a: af00 add r7, sp, #0
800ab1c: 6078 str r0, [r7, #4]
800ab1e: 6039 str r1, [r7, #0]
uint8_t *pbuff = pdata;
800ab20: 683b ldr r3, [r7, #0]
800ab22: 60fb str r3, [r7, #12]
req->bmRequest = *(uint8_t *)(pbuff);
800ab24: 68fb ldr r3, [r7, #12]
800ab26: 781a ldrb r2, [r3, #0]
800ab28: 687b ldr r3, [r7, #4]
800ab2a: 701a strb r2, [r3, #0]
pbuff++;
800ab2c: 68fb ldr r3, [r7, #12]
800ab2e: 3301 adds r3, #1
800ab30: 60fb str r3, [r7, #12]
req->bRequest = *(uint8_t *)(pbuff);
800ab32: 68fb ldr r3, [r7, #12]
800ab34: 781a ldrb r2, [r3, #0]
800ab36: 687b ldr r3, [r7, #4]
800ab38: 705a strb r2, [r3, #1]
pbuff++;
800ab3a: 68fb ldr r3, [r7, #12]
800ab3c: 3301 adds r3, #1
800ab3e: 60fb str r3, [r7, #12]
req->wValue = SWAPBYTE(pbuff);
800ab40: 68f8 ldr r0, [r7, #12]
800ab42: f7ff fa16 bl 8009f72 <SWAPBYTE>
800ab46: 4603 mov r3, r0
800ab48: 461a mov r2, r3
800ab4a: 687b ldr r3, [r7, #4]
800ab4c: 805a strh r2, [r3, #2]
pbuff++;
800ab4e: 68fb ldr r3, [r7, #12]
800ab50: 3301 adds r3, #1
800ab52: 60fb str r3, [r7, #12]
pbuff++;
800ab54: 68fb ldr r3, [r7, #12]
800ab56: 3301 adds r3, #1
800ab58: 60fb str r3, [r7, #12]
req->wIndex = SWAPBYTE(pbuff);
800ab5a: 68f8 ldr r0, [r7, #12]
800ab5c: f7ff fa09 bl 8009f72 <SWAPBYTE>
800ab60: 4603 mov r3, r0
800ab62: 461a mov r2, r3
800ab64: 687b ldr r3, [r7, #4]
800ab66: 809a strh r2, [r3, #4]
pbuff++;
800ab68: 68fb ldr r3, [r7, #12]
800ab6a: 3301 adds r3, #1
800ab6c: 60fb str r3, [r7, #12]
pbuff++;
800ab6e: 68fb ldr r3, [r7, #12]
800ab70: 3301 adds r3, #1
800ab72: 60fb str r3, [r7, #12]
req->wLength = SWAPBYTE(pbuff);
800ab74: 68f8 ldr r0, [r7, #12]
800ab76: f7ff f9fc bl 8009f72 <SWAPBYTE>
800ab7a: 4603 mov r3, r0
800ab7c: 461a mov r2, r3
800ab7e: 687b ldr r3, [r7, #4]
800ab80: 80da strh r2, [r3, #6]
}
800ab82: bf00 nop
800ab84: 3710 adds r7, #16
800ab86: 46bd mov sp, r7
800ab88: bd80 pop {r7, pc}
0800ab8a <USBD_CtlError>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800ab8a: b580 push {r7, lr}
800ab8c: b082 sub sp, #8
800ab8e: af00 add r7, sp, #0
800ab90: 6078 str r0, [r7, #4]
800ab92: 6039 str r1, [r7, #0]
UNUSED(req);
(void)USBD_LL_StallEP(pdev, 0x80U);
800ab94: 2180 movs r1, #128 @ 0x80
800ab96: 6878 ldr r0, [r7, #4]
800ab98: f000 fcb4 bl 800b504 <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0U);
800ab9c: 2100 movs r1, #0
800ab9e: 6878 ldr r0, [r7, #4]
800aba0: f000 fcb0 bl 800b504 <USBD_LL_StallEP>
}
800aba4: bf00 nop
800aba6: 3708 adds r7, #8
800aba8: 46bd mov sp, r7
800abaa: bd80 pop {r7, pc}
0800abac <USBD_GetString>:
* @param unicode : Formatted string buffer (unicode)
* @param len : descriptor length
* @retval None
*/
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
{
800abac: b580 push {r7, lr}
800abae: b086 sub sp, #24
800abb0: af00 add r7, sp, #0
800abb2: 60f8 str r0, [r7, #12]
800abb4: 60b9 str r1, [r7, #8]
800abb6: 607a str r2, [r7, #4]
uint8_t idx = 0U;
800abb8: 2300 movs r3, #0
800abba: 75fb strb r3, [r7, #23]
uint8_t *pdesc;
if (desc == NULL)
800abbc: 68fb ldr r3, [r7, #12]
800abbe: 2b00 cmp r3, #0
800abc0: d042 beq.n 800ac48 <USBD_GetString+0x9c>
{
return;
}
pdesc = desc;
800abc2: 68fb ldr r3, [r7, #12]
800abc4: 613b str r3, [r7, #16]
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
800abc6: 6938 ldr r0, [r7, #16]
800abc8: f000 f842 bl 800ac50 <USBD_GetLen>
800abcc: 4603 mov r3, r0
800abce: 3301 adds r3, #1
800abd0: 005b lsls r3, r3, #1
800abd2: f5b3 7f00 cmp.w r3, #512 @ 0x200
800abd6: d808 bhi.n 800abea <USBD_GetString+0x3e>
800abd8: 6938 ldr r0, [r7, #16]
800abda: f000 f839 bl 800ac50 <USBD_GetLen>
800abde: 4603 mov r3, r0
800abe0: 3301 adds r3, #1
800abe2: b29b uxth r3, r3
800abe4: 005b lsls r3, r3, #1
800abe6: b29a uxth r2, r3
800abe8: e001 b.n 800abee <USBD_GetString+0x42>
800abea: f44f 7200 mov.w r2, #512 @ 0x200
800abee: 687b ldr r3, [r7, #4]
800abf0: 801a strh r2, [r3, #0]
unicode[idx] = *(uint8_t *)len;
800abf2: 7dfb ldrb r3, [r7, #23]
800abf4: 68ba ldr r2, [r7, #8]
800abf6: 4413 add r3, r2
800abf8: 687a ldr r2, [r7, #4]
800abfa: 7812 ldrb r2, [r2, #0]
800abfc: 701a strb r2, [r3, #0]
idx++;
800abfe: 7dfb ldrb r3, [r7, #23]
800ac00: 3301 adds r3, #1
800ac02: 75fb strb r3, [r7, #23]
unicode[idx] = USB_DESC_TYPE_STRING;
800ac04: 7dfb ldrb r3, [r7, #23]
800ac06: 68ba ldr r2, [r7, #8]
800ac08: 4413 add r3, r2
800ac0a: 2203 movs r2, #3
800ac0c: 701a strb r2, [r3, #0]
idx++;
800ac0e: 7dfb ldrb r3, [r7, #23]
800ac10: 3301 adds r3, #1
800ac12: 75fb strb r3, [r7, #23]
while (*pdesc != (uint8_t)'\0')
800ac14: e013 b.n 800ac3e <USBD_GetString+0x92>
{
unicode[idx] = *pdesc;
800ac16: 7dfb ldrb r3, [r7, #23]
800ac18: 68ba ldr r2, [r7, #8]
800ac1a: 4413 add r3, r2
800ac1c: 693a ldr r2, [r7, #16]
800ac1e: 7812 ldrb r2, [r2, #0]
800ac20: 701a strb r2, [r3, #0]
pdesc++;
800ac22: 693b ldr r3, [r7, #16]
800ac24: 3301 adds r3, #1
800ac26: 613b str r3, [r7, #16]
idx++;
800ac28: 7dfb ldrb r3, [r7, #23]
800ac2a: 3301 adds r3, #1
800ac2c: 75fb strb r3, [r7, #23]
unicode[idx] = 0U;
800ac2e: 7dfb ldrb r3, [r7, #23]
800ac30: 68ba ldr r2, [r7, #8]
800ac32: 4413 add r3, r2
800ac34: 2200 movs r2, #0
800ac36: 701a strb r2, [r3, #0]
idx++;
800ac38: 7dfb ldrb r3, [r7, #23]
800ac3a: 3301 adds r3, #1
800ac3c: 75fb strb r3, [r7, #23]
while (*pdesc != (uint8_t)'\0')
800ac3e: 693b ldr r3, [r7, #16]
800ac40: 781b ldrb r3, [r3, #0]
800ac42: 2b00 cmp r3, #0
800ac44: d1e7 bne.n 800ac16 <USBD_GetString+0x6a>
800ac46: e000 b.n 800ac4a <USBD_GetString+0x9e>
return;
800ac48: bf00 nop
}
}
800ac4a: 3718 adds r7, #24
800ac4c: 46bd mov sp, r7
800ac4e: bd80 pop {r7, pc}
0800ac50 <USBD_GetLen>:
* return the string length
* @param buf : pointer to the ascii string buffer
* @retval string length
*/
static uint8_t USBD_GetLen(uint8_t *buf)
{
800ac50: b480 push {r7}
800ac52: b085 sub sp, #20
800ac54: af00 add r7, sp, #0
800ac56: 6078 str r0, [r7, #4]
uint8_t len = 0U;
800ac58: 2300 movs r3, #0
800ac5a: 73fb strb r3, [r7, #15]
uint8_t *pbuff = buf;
800ac5c: 687b ldr r3, [r7, #4]
800ac5e: 60bb str r3, [r7, #8]
while (*pbuff != (uint8_t)'\0')
800ac60: e005 b.n 800ac6e <USBD_GetLen+0x1e>
{
len++;
800ac62: 7bfb ldrb r3, [r7, #15]
800ac64: 3301 adds r3, #1
800ac66: 73fb strb r3, [r7, #15]
pbuff++;
800ac68: 68bb ldr r3, [r7, #8]
800ac6a: 3301 adds r3, #1
800ac6c: 60bb str r3, [r7, #8]
while (*pbuff != (uint8_t)'\0')
800ac6e: 68bb ldr r3, [r7, #8]
800ac70: 781b ldrb r3, [r3, #0]
800ac72: 2b00 cmp r3, #0
800ac74: d1f5 bne.n 800ac62 <USBD_GetLen+0x12>
}
return len;
800ac76: 7bfb ldrb r3, [r7, #15]
}
800ac78: 4618 mov r0, r3
800ac7a: 3714 adds r7, #20
800ac7c: 46bd mov sp, r7
800ac7e: f85d 7b04 ldr.w r7, [sp], #4
800ac82: 4770 bx lr
0800ac84 <USBD_CtlSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
800ac84: b580 push {r7, lr}
800ac86: b084 sub sp, #16
800ac88: af00 add r7, sp, #0
800ac8a: 60f8 str r0, [r7, #12]
800ac8c: 60b9 str r1, [r7, #8]
800ac8e: 607a str r2, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
800ac90: 68fb ldr r3, [r7, #12]
800ac92: 2202 movs r2, #2
800ac94: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_in[0].total_length = len;
800ac98: 68fb ldr r3, [r7, #12]
800ac9a: 687a ldr r2, [r7, #4]
800ac9c: 619a str r2, [r3, #24]
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
pdev->ep_in[0].rem_length = 0U;
#else
pdev->ep_in[0].rem_length = len;
800ac9e: 68fb ldr r3, [r7, #12]
800aca0: 687a ldr r2, [r7, #4]
800aca2: 61da str r2, [r3, #28]
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
/* Start the transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800aca4: 687b ldr r3, [r7, #4]
800aca6: 68ba ldr r2, [r7, #8]
800aca8: 2100 movs r1, #0
800acaa: 68f8 ldr r0, [r7, #12]
800acac: f000 fcf8 bl 800b6a0 <USBD_LL_Transmit>
return USBD_OK;
800acb0: 2300 movs r3, #0
}
800acb2: 4618 mov r0, r3
800acb4: 3710 adds r7, #16
800acb6: 46bd mov sp, r7
800acb8: bd80 pop {r7, pc}
0800acba <USBD_CtlContinueSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
800acba: b580 push {r7, lr}
800acbc: b084 sub sp, #16
800acbe: af00 add r7, sp, #0
800acc0: 60f8 str r0, [r7, #12]
800acc2: 60b9 str r1, [r7, #8]
800acc4: 607a str r2, [r7, #4]
/* Start the next transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800acc6: 687b ldr r3, [r7, #4]
800acc8: 68ba ldr r2, [r7, #8]
800acca: 2100 movs r1, #0
800accc: 68f8 ldr r0, [r7, #12]
800acce: f000 fce7 bl 800b6a0 <USBD_LL_Transmit>
return USBD_OK;
800acd2: 2300 movs r3, #0
}
800acd4: 4618 mov r0, r3
800acd6: 3710 adds r7, #16
800acd8: 46bd mov sp, r7
800acda: bd80 pop {r7, pc}
0800acdc <USBD_CtlContinueRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
800acdc: b580 push {r7, lr}
800acde: b084 sub sp, #16
800ace0: af00 add r7, sp, #0
800ace2: 60f8 str r0, [r7, #12]
800ace4: 60b9 str r1, [r7, #8]
800ace6: 607a str r2, [r7, #4]
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
800ace8: 687b ldr r3, [r7, #4]
800acea: 68ba ldr r2, [r7, #8]
800acec: 2100 movs r1, #0
800acee: 68f8 ldr r0, [r7, #12]
800acf0: f000 fd0e bl 800b710 <USBD_LL_PrepareReceive>
return USBD_OK;
800acf4: 2300 movs r3, #0
}
800acf6: 4618 mov r0, r3
800acf8: 3710 adds r7, #16
800acfa: 46bd mov sp, r7
800acfc: bd80 pop {r7, pc}
0800acfe <USBD_CtlSendStatus>:
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
800acfe: b580 push {r7, lr}
800ad00: b082 sub sp, #8
800ad02: af00 add r7, sp, #0
800ad04: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
800ad06: 687b ldr r3, [r7, #4]
800ad08: 2204 movs r2, #4
800ad0a: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
800ad0e: 2300 movs r3, #0
800ad10: 2200 movs r2, #0
800ad12: 2100 movs r1, #0
800ad14: 6878 ldr r0, [r7, #4]
800ad16: f000 fcc3 bl 800b6a0 <USBD_LL_Transmit>
return USBD_OK;
800ad1a: 2300 movs r3, #0
}
800ad1c: 4618 mov r0, r3
800ad1e: 3708 adds r7, #8
800ad20: 46bd mov sp, r7
800ad22: bd80 pop {r7, pc}
0800ad24 <USBD_CtlReceiveStatus>:
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
800ad24: b580 push {r7, lr}
800ad26: b082 sub sp, #8
800ad28: af00 add r7, sp, #0
800ad2a: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
800ad2c: 687b ldr r3, [r7, #4]
800ad2e: 2205 movs r2, #5
800ad30: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
800ad34: 2300 movs r3, #0
800ad36: 2200 movs r2, #0
800ad38: 2100 movs r1, #0
800ad3a: 6878 ldr r0, [r7, #4]
800ad3c: f000 fce8 bl 800b710 <USBD_LL_PrepareReceive>
return USBD_OK;
800ad40: 2300 movs r3, #0
}
800ad42: 4618 mov r0, r3
800ad44: 3708 adds r7, #8
800ad46: 46bd mov sp, r7
800ad48: bd80 pop {r7, pc}
...
0800ad4c <MX_USB_DEVICE_Init>:
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void MX_USB_DEVICE_Init(void)
{
800ad4c: b580 push {r7, lr}
800ad4e: af00 add r7, sp, #0
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
/* USER CODE END USB_DEVICE_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
800ad50: 2200 movs r2, #0
800ad52: 4912 ldr r1, [pc, #72] @ (800ad9c <MX_USB_DEVICE_Init+0x50>)
800ad54: 4812 ldr r0, [pc, #72] @ (800ada0 <MX_USB_DEVICE_Init+0x54>)
800ad56: f7fe fd3d bl 80097d4 <USBD_Init>
800ad5a: 4603 mov r3, r0
800ad5c: 2b00 cmp r3, #0
800ad5e: d001 beq.n 800ad64 <MX_USB_DEVICE_Init+0x18>
{
Error_Handler();
800ad60: f7f6 fd32 bl 80017c8 <Error_Handler>
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_MIDI) != USBD_OK)
800ad64: 490f ldr r1, [pc, #60] @ (800ada4 <MX_USB_DEVICE_Init+0x58>)
800ad66: 480e ldr r0, [pc, #56] @ (800ada0 <MX_USB_DEVICE_Init+0x54>)
800ad68: f7fe fd64 bl 8009834 <USBD_RegisterClass>
800ad6c: 4603 mov r3, r0
800ad6e: 2b00 cmp r3, #0
800ad70: d001 beq.n 800ad76 <MX_USB_DEVICE_Init+0x2a>
{
Error_Handler();
800ad72: f7f6 fd29 bl 80017c8 <Error_Handler>
}
if (USBD_CUSTOM_HID_RegisterInterface(&hUsbDeviceFS, &USBD_CustomHID_fops_FS) != USBD_OK)
800ad76: 490c ldr r1, [pc, #48] @ (800ada8 <MX_USB_DEVICE_Init+0x5c>)
800ad78: 4809 ldr r0, [pc, #36] @ (800ada0 <MX_USB_DEVICE_Init+0x54>)
800ad7a: f7fe fbcf bl 800951c <USBD_CUSTOM_HID_RegisterInterface>
800ad7e: 4603 mov r3, r0
800ad80: 2b00 cmp r3, #0
800ad82: d001 beq.n 800ad88 <MX_USB_DEVICE_Init+0x3c>
{
Error_Handler();
800ad84: f7f6 fd20 bl 80017c8 <Error_Handler>
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
800ad88: 4805 ldr r0, [pc, #20] @ (800ada0 <MX_USB_DEVICE_Init+0x54>)
800ad8a: f7fe fd89 bl 80098a0 <USBD_Start>
800ad8e: 4603 mov r3, r0
800ad90: 2b00 cmp r3, #0
800ad92: d001 beq.n 800ad98 <MX_USB_DEVICE_Init+0x4c>
{
Error_Handler();
800ad94: f7f6 fd18 bl 80017c8 <Error_Handler>
}
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
/* USER CODE END USB_DEVICE_Init_PostTreatment */
}
800ad98: bf00 nop
800ad9a: bd80 pop {r7, pc}
800ad9c: 200000d8 .word 0x200000d8
800ada0: 200006d0 .word 0x200006d0
800ada4: 2000000c .word 0x2000000c
800ada8: 200000c8 .word 0x200000c8
0800adac <CUSTOM_HID_Init_FS>:
/**
* @brief Initializes the CUSTOM HID media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CUSTOM_HID_Init_FS(void)
{
800adac: b480 push {r7}
800adae: af00 add r7, sp, #0
/* USER CODE BEGIN 4 */
return (USBD_OK);
800adb0: 2300 movs r3, #0
/* USER CODE END 4 */
}
800adb2: 4618 mov r0, r3
800adb4: 46bd mov sp, r7
800adb6: f85d 7b04 ldr.w r7, [sp], #4
800adba: 4770 bx lr
0800adbc <CUSTOM_HID_DeInit_FS>:
/**
* @brief DeInitializes the CUSTOM HID media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CUSTOM_HID_DeInit_FS(void)
{
800adbc: b480 push {r7}
800adbe: af00 add r7, sp, #0
/* USER CODE BEGIN 5 */
return (USBD_OK);
800adc0: 2300 movs r3, #0
/* USER CODE END 5 */
}
800adc2: 4618 mov r0, r3
800adc4: 46bd mov sp, r7
800adc6: f85d 7b04 ldr.w r7, [sp], #4
800adca: 4770 bx lr
0800adcc <CUSTOM_HID_OutEvent_FS>:
* @param event_idx: Event index
* @param state: Event state
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CUSTOM_HID_OutEvent_FS(uint8_t event_idx, uint8_t state)
{
800adcc: b580 push {r7, lr}
800adce: b082 sub sp, #8
800add0: af00 add r7, sp, #0
800add2: 4603 mov r3, r0
800add4: 460a mov r2, r1
800add6: 71fb strb r3, [r7, #7]
800add8: 4613 mov r3, r2
800adda: 71bb strb r3, [r7, #6]
/* USER CODE BEGIN 6 */
UNUSED(event_idx);
UNUSED(state);
/* Start next USB packet transfer once data processing is completed */
USBD_CUSTOM_HID_ReceivePacket(&hUsbDeviceFS);
800addc: 4803 ldr r0, [pc, #12] @ (800adec <CUSTOM_HID_OutEvent_FS+0x20>)
800adde: f7fe fb77 bl 80094d0 <USBD_CUSTOM_HID_ReceivePacket>
return (USBD_OK);
800ade2: 2300 movs r3, #0
/* USER CODE END 6 */
}
800ade4: 4618 mov r0, r3
800ade6: 3708 adds r7, #8
800ade8: 46bd mov sp, r7
800adea: bd80 pop {r7, pc}
800adec: 200006d0 .word 0x200006d0
0800adf0 <USBD_FS_DeviceDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800adf0: b480 push {r7}
800adf2: b083 sub sp, #12
800adf4: af00 add r7, sp, #0
800adf6: 4603 mov r3, r0
800adf8: 6039 str r1, [r7, #0]
800adfa: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc);
800adfc: 683b ldr r3, [r7, #0]
800adfe: 2212 movs r2, #18
800ae00: 801a strh r2, [r3, #0]
return USBD_FS_DeviceDesc;
800ae02: 4b03 ldr r3, [pc, #12] @ (800ae10 <USBD_FS_DeviceDescriptor+0x20>)
}
800ae04: 4618 mov r0, r3
800ae06: 370c adds r7, #12
800ae08: 46bd mov sp, r7
800ae0a: f85d 7b04 ldr.w r7, [sp], #4
800ae0e: 4770 bx lr
800ae10: 200000f8 .word 0x200000f8
0800ae14 <USBD_FS_LangIDStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ae14: b480 push {r7}
800ae16: b083 sub sp, #12
800ae18: af00 add r7, sp, #0
800ae1a: 4603 mov r3, r0
800ae1c: 6039 str r1, [r7, #0]
800ae1e: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
800ae20: 683b ldr r3, [r7, #0]
800ae22: 2204 movs r2, #4
800ae24: 801a strh r2, [r3, #0]
return USBD_LangIDDesc;
800ae26: 4b03 ldr r3, [pc, #12] @ (800ae34 <USBD_FS_LangIDStrDescriptor+0x20>)
}
800ae28: 4618 mov r0, r3
800ae2a: 370c adds r7, #12
800ae2c: 46bd mov sp, r7
800ae2e: f85d 7b04 ldr.w r7, [sp], #4
800ae32: 4770 bx lr
800ae34: 20000118 .word 0x20000118
0800ae38 <USBD_FS_ProductStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ae38: b580 push {r7, lr}
800ae3a: b082 sub sp, #8
800ae3c: af00 add r7, sp, #0
800ae3e: 4603 mov r3, r0
800ae40: 6039 str r1, [r7, #0]
800ae42: 71fb strb r3, [r7, #7]
if(speed == 0)
800ae44: 79fb ldrb r3, [r7, #7]
800ae46: 2b00 cmp r3, #0
800ae48: d105 bne.n 800ae56 <USBD_FS_ProductStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800ae4a: 683a ldr r2, [r7, #0]
800ae4c: 4907 ldr r1, [pc, #28] @ (800ae6c <USBD_FS_ProductStrDescriptor+0x34>)
800ae4e: 4808 ldr r0, [pc, #32] @ (800ae70 <USBD_FS_ProductStrDescriptor+0x38>)
800ae50: f7ff feac bl 800abac <USBD_GetString>
800ae54: e004 b.n 800ae60 <USBD_FS_ProductStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800ae56: 683a ldr r2, [r7, #0]
800ae58: 4904 ldr r1, [pc, #16] @ (800ae6c <USBD_FS_ProductStrDescriptor+0x34>)
800ae5a: 4805 ldr r0, [pc, #20] @ (800ae70 <USBD_FS_ProductStrDescriptor+0x38>)
800ae5c: f7ff fea6 bl 800abac <USBD_GetString>
}
return USBD_StrDesc;
800ae60: 4b02 ldr r3, [pc, #8] @ (800ae6c <USBD_FS_ProductStrDescriptor+0x34>)
}
800ae62: 4618 mov r0, r3
800ae64: 3708 adds r7, #8
800ae66: 46bd mov sp, r7
800ae68: bd80 pop {r7, pc}
800ae6a: bf00 nop
800ae6c: 200009ac .word 0x200009ac
800ae70: 0800e178 .word 0x0800e178
0800ae74 <USBD_FS_ManufacturerStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ae74: b580 push {r7, lr}
800ae76: b082 sub sp, #8
800ae78: af00 add r7, sp, #0
800ae7a: 4603 mov r3, r0
800ae7c: 6039 str r1, [r7, #0]
800ae7e: 71fb strb r3, [r7, #7]
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
800ae80: 683a ldr r2, [r7, #0]
800ae82: 4904 ldr r1, [pc, #16] @ (800ae94 <USBD_FS_ManufacturerStrDescriptor+0x20>)
800ae84: 4804 ldr r0, [pc, #16] @ (800ae98 <USBD_FS_ManufacturerStrDescriptor+0x24>)
800ae86: f7ff fe91 bl 800abac <USBD_GetString>
return USBD_StrDesc;
800ae8a: 4b02 ldr r3, [pc, #8] @ (800ae94 <USBD_FS_ManufacturerStrDescriptor+0x20>)
}
800ae8c: 4618 mov r0, r3
800ae8e: 3708 adds r7, #8
800ae90: 46bd mov sp, r7
800ae92: bd80 pop {r7, pc}
800ae94: 200009ac .word 0x200009ac
800ae98: 0800e184 .word 0x0800e184
0800ae9c <USBD_FS_SerialStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ae9c: b580 push {r7, lr}
800ae9e: b082 sub sp, #8
800aea0: af00 add r7, sp, #0
800aea2: 4603 mov r3, r0
800aea4: 6039 str r1, [r7, #0]
800aea6: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
800aea8: 683b ldr r3, [r7, #0]
800aeaa: 221a movs r2, #26
800aeac: 801a strh r2, [r3, #0]
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
800aeae: f000 f855 bl 800af5c <Get_SerialNum>
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
/* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
800aeb2: 4b02 ldr r3, [pc, #8] @ (800aebc <USBD_FS_SerialStrDescriptor+0x20>)
}
800aeb4: 4618 mov r0, r3
800aeb6: 3708 adds r7, #8
800aeb8: 46bd mov sp, r7
800aeba: bd80 pop {r7, pc}
800aebc: 2000011c .word 0x2000011c
0800aec0 <USBD_FS_ConfigStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800aec0: b580 push {r7, lr}
800aec2: b082 sub sp, #8
800aec4: af00 add r7, sp, #0
800aec6: 4603 mov r3, r0
800aec8: 6039 str r1, [r7, #0]
800aeca: 71fb strb r3, [r7, #7]
if(speed == USBD_SPEED_HIGH)
800aecc: 79fb ldrb r3, [r7, #7]
800aece: 2b00 cmp r3, #0
800aed0: d105 bne.n 800aede <USBD_FS_ConfigStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
800aed2: 683a ldr r2, [r7, #0]
800aed4: 4907 ldr r1, [pc, #28] @ (800aef4 <USBD_FS_ConfigStrDescriptor+0x34>)
800aed6: 4808 ldr r0, [pc, #32] @ (800aef8 <USBD_FS_ConfigStrDescriptor+0x38>)
800aed8: f7ff fe68 bl 800abac <USBD_GetString>
800aedc: e004 b.n 800aee8 <USBD_FS_ConfigStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
800aede: 683a ldr r2, [r7, #0]
800aee0: 4904 ldr r1, [pc, #16] @ (800aef4 <USBD_FS_ConfigStrDescriptor+0x34>)
800aee2: 4805 ldr r0, [pc, #20] @ (800aef8 <USBD_FS_ConfigStrDescriptor+0x38>)
800aee4: f7ff fe62 bl 800abac <USBD_GetString>
}
return USBD_StrDesc;
800aee8: 4b02 ldr r3, [pc, #8] @ (800aef4 <USBD_FS_ConfigStrDescriptor+0x34>)
}
800aeea: 4618 mov r0, r3
800aeec: 3708 adds r7, #8
800aeee: 46bd mov sp, r7
800aef0: bd80 pop {r7, pc}
800aef2: bf00 nop
800aef4: 200009ac .word 0x200009ac
800aef8: 0800e198 .word 0x0800e198
0800aefc <USBD_FS_InterfaceStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800aefc: b580 push {r7, lr}
800aefe: b082 sub sp, #8
800af00: af00 add r7, sp, #0
800af02: 4603 mov r3, r0
800af04: 6039 str r1, [r7, #0]
800af06: 71fb strb r3, [r7, #7]
if(speed == 0)
800af08: 79fb ldrb r3, [r7, #7]
800af0a: 2b00 cmp r3, #0
800af0c: d105 bne.n 800af1a <USBD_FS_InterfaceStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
800af0e: 683a ldr r2, [r7, #0]
800af10: 4907 ldr r1, [pc, #28] @ (800af30 <USBD_FS_InterfaceStrDescriptor+0x34>)
800af12: 4808 ldr r0, [pc, #32] @ (800af34 <USBD_FS_InterfaceStrDescriptor+0x38>)
800af14: f7ff fe4a bl 800abac <USBD_GetString>
800af18: e004 b.n 800af24 <USBD_FS_InterfaceStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
800af1a: 683a ldr r2, [r7, #0]
800af1c: 4904 ldr r1, [pc, #16] @ (800af30 <USBD_FS_InterfaceStrDescriptor+0x34>)
800af1e: 4805 ldr r0, [pc, #20] @ (800af34 <USBD_FS_InterfaceStrDescriptor+0x38>)
800af20: f7ff fe44 bl 800abac <USBD_GetString>
}
return USBD_StrDesc;
800af24: 4b02 ldr r3, [pc, #8] @ (800af30 <USBD_FS_InterfaceStrDescriptor+0x34>)
}
800af26: 4618 mov r0, r3
800af28: 3708 adds r7, #8
800af2a: 46bd mov sp, r7
800af2c: bd80 pop {r7, pc}
800af2e: bf00 nop
800af30: 200009ac .word 0x200009ac
800af34: 0800e1ac .word 0x0800e1ac
0800af38 <USBD_FS_USR_BOSDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800af38: b480 push {r7}
800af3a: b083 sub sp, #12
800af3c: af00 add r7, sp, #0
800af3e: 4603 mov r3, r0
800af40: 6039 str r1, [r7, #0]
800af42: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_BOSDesc);
800af44: 683b ldr r3, [r7, #0]
800af46: 220c movs r2, #12
800af48: 801a strh r2, [r3, #0]
return (uint8_t*)USBD_FS_BOSDesc;
800af4a: 4b03 ldr r3, [pc, #12] @ (800af58 <USBD_FS_USR_BOSDescriptor+0x20>)
}
800af4c: 4618 mov r0, r3
800af4e: 370c adds r7, #12
800af50: 46bd mov sp, r7
800af52: f85d 7b04 ldr.w r7, [sp], #4
800af56: 4770 bx lr
800af58: 2000010c .word 0x2000010c
0800af5c <Get_SerialNum>:
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
800af5c: b580 push {r7, lr}
800af5e: b084 sub sp, #16
800af60: af00 add r7, sp, #0
uint32_t deviceserial0;
uint32_t deviceserial1;
uint32_t deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
800af62: 4b0f ldr r3, [pc, #60] @ (800afa0 <Get_SerialNum+0x44>)
800af64: 681b ldr r3, [r3, #0]
800af66: 60fb str r3, [r7, #12]
deviceserial1 = *(uint32_t *) DEVICE_ID2;
800af68: 4b0e ldr r3, [pc, #56] @ (800afa4 <Get_SerialNum+0x48>)
800af6a: 681b ldr r3, [r3, #0]
800af6c: 60bb str r3, [r7, #8]
deviceserial2 = *(uint32_t *) DEVICE_ID3;
800af6e: 4b0e ldr r3, [pc, #56] @ (800afa8 <Get_SerialNum+0x4c>)
800af70: 681b ldr r3, [r3, #0]
800af72: 607b str r3, [r7, #4]
deviceserial0 += deviceserial2;
800af74: 68fa ldr r2, [r7, #12]
800af76: 687b ldr r3, [r7, #4]
800af78: 4413 add r3, r2
800af7a: 60fb str r3, [r7, #12]
if (deviceserial0 != 0)
800af7c: 68fb ldr r3, [r7, #12]
800af7e: 2b00 cmp r3, #0
800af80: d009 beq.n 800af96 <Get_SerialNum+0x3a>
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
800af82: 2208 movs r2, #8
800af84: 4909 ldr r1, [pc, #36] @ (800afac <Get_SerialNum+0x50>)
800af86: 68f8 ldr r0, [r7, #12]
800af88: f000 f814 bl 800afb4 <IntToUnicode>
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
800af8c: 2204 movs r2, #4
800af8e: 4908 ldr r1, [pc, #32] @ (800afb0 <Get_SerialNum+0x54>)
800af90: 68b8 ldr r0, [r7, #8]
800af92: f000 f80f bl 800afb4 <IntToUnicode>
}
}
800af96: bf00 nop
800af98: 3710 adds r7, #16
800af9a: 46bd mov sp, r7
800af9c: bd80 pop {r7, pc}
800af9e: bf00 nop
800afa0: 1fff7590 .word 0x1fff7590
800afa4: 1fff7594 .word 0x1fff7594
800afa8: 1fff7598 .word 0x1fff7598
800afac: 2000011e .word 0x2000011e
800afb0: 2000012e .word 0x2000012e
0800afb4 <IntToUnicode>:
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
800afb4: b480 push {r7}
800afb6: b087 sub sp, #28
800afb8: af00 add r7, sp, #0
800afba: 60f8 str r0, [r7, #12]
800afbc: 60b9 str r1, [r7, #8]
800afbe: 4613 mov r3, r2
800afc0: 71fb strb r3, [r7, #7]
uint8_t idx = 0;
800afc2: 2300 movs r3, #0
800afc4: 75fb strb r3, [r7, #23]
for (idx = 0; idx < len; idx++)
800afc6: 2300 movs r3, #0
800afc8: 75fb strb r3, [r7, #23]
800afca: e027 b.n 800b01c <IntToUnicode+0x68>
{
if (((value >> 28)) < 0xA)
800afcc: 68fb ldr r3, [r7, #12]
800afce: 0f1b lsrs r3, r3, #28
800afd0: 2b09 cmp r3, #9
800afd2: d80b bhi.n 800afec <IntToUnicode+0x38>
{
pbuf[2 * idx] = (value >> 28) + '0';
800afd4: 68fb ldr r3, [r7, #12]
800afd6: 0f1b lsrs r3, r3, #28
800afd8: b2da uxtb r2, r3
800afda: 7dfb ldrb r3, [r7, #23]
800afdc: 005b lsls r3, r3, #1
800afde: 4619 mov r1, r3
800afe0: 68bb ldr r3, [r7, #8]
800afe2: 440b add r3, r1
800afe4: 3230 adds r2, #48 @ 0x30
800afe6: b2d2 uxtb r2, r2
800afe8: 701a strb r2, [r3, #0]
800afea: e00a b.n 800b002 <IntToUnicode+0x4e>
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
800afec: 68fb ldr r3, [r7, #12]
800afee: 0f1b lsrs r3, r3, #28
800aff0: b2da uxtb r2, r3
800aff2: 7dfb ldrb r3, [r7, #23]
800aff4: 005b lsls r3, r3, #1
800aff6: 4619 mov r1, r3
800aff8: 68bb ldr r3, [r7, #8]
800affa: 440b add r3, r1
800affc: 3237 adds r2, #55 @ 0x37
800affe: b2d2 uxtb r2, r2
800b000: 701a strb r2, [r3, #0]
}
value = value << 4;
800b002: 68fb ldr r3, [r7, #12]
800b004: 011b lsls r3, r3, #4
800b006: 60fb str r3, [r7, #12]
pbuf[2 * idx + 1] = 0;
800b008: 7dfb ldrb r3, [r7, #23]
800b00a: 005b lsls r3, r3, #1
800b00c: 3301 adds r3, #1
800b00e: 68ba ldr r2, [r7, #8]
800b010: 4413 add r3, r2
800b012: 2200 movs r2, #0
800b014: 701a strb r2, [r3, #0]
for (idx = 0; idx < len; idx++)
800b016: 7dfb ldrb r3, [r7, #23]
800b018: 3301 adds r3, #1
800b01a: 75fb strb r3, [r7, #23]
800b01c: 7dfa ldrb r2, [r7, #23]
800b01e: 79fb ldrb r3, [r7, #7]
800b020: 429a cmp r2, r3
800b022: d3d3 bcc.n 800afcc <IntToUnicode+0x18>
}
}
800b024: bf00 nop
800b026: bf00 nop
800b028: 371c adds r7, #28
800b02a: 46bd mov sp, r7
800b02c: f85d 7b04 ldr.w r7, [sp], #4
800b030: 4770 bx lr
...
0800b034 <HAL_PCD_MspInit>:
LL Driver Callbacks (PCD -> USB Device Library)
*******************************************************************************/
/* MSP Init */
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
800b034: b580 push {r7, lr}
800b036: b08a sub sp, #40 @ 0x28
800b038: af00 add r7, sp, #0
800b03a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800b03c: f107 0314 add.w r3, r7, #20
800b040: 2200 movs r2, #0
800b042: 601a str r2, [r3, #0]
800b044: 605a str r2, [r3, #4]
800b046: 609a str r2, [r3, #8]
800b048: 60da str r2, [r3, #12]
800b04a: 611a str r2, [r3, #16]
if(pcdHandle->Instance==USB_OTG_FS)
800b04c: 687b ldr r3, [r7, #4]
800b04e: 681b ldr r3, [r3, #0]
800b050: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
800b054: d15c bne.n 800b110 <HAL_PCD_MspInit+0xdc>
{
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
/* USER CODE END USB_OTG_FS_MspInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
800b056: 4b30 ldr r3, [pc, #192] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b058: 6cdb ldr r3, [r3, #76] @ 0x4c
800b05a: 4a2f ldr r2, [pc, #188] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b05c: f043 0301 orr.w r3, r3, #1
800b060: 64d3 str r3, [r2, #76] @ 0x4c
800b062: 4b2d ldr r3, [pc, #180] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b064: 6cdb ldr r3, [r3, #76] @ 0x4c
800b066: f003 0301 and.w r3, r3, #1
800b06a: 613b str r3, [r7, #16]
800b06c: 693b ldr r3, [r7, #16]
PA9 ------> USB_OTG_FS_VBUS
PA10 ------> USB_OTG_FS_ID
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
GPIO_InitStruct.Pin = USB_OTG_FS_VBUS_Pin;
800b06e: f44f 7300 mov.w r3, #512 @ 0x200
800b072: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800b074: 2300 movs r3, #0
800b076: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b078: 2300 movs r3, #0
800b07a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(USB_OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
800b07c: f107 0314 add.w r3, r7, #20
800b080: 4619 mov r1, r3
800b082: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800b086: f7f8 fa37 bl 80034f8 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = USB_OTG_FS_ID_Pin|USB_OTG_FS_DM_Pin|USB_OTG_FS_DP_Pin;
800b08a: f44f 53e0 mov.w r3, #7168 @ 0x1c00
800b08e: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b090: 2302 movs r3, #2
800b092: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b094: 2300 movs r3, #0
800b096: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b098: 2303 movs r3, #3
800b09a: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
800b09c: 230a movs r3, #10
800b09e: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800b0a0: f107 0314 add.w r3, r7, #20
800b0a4: 4619 mov r1, r3
800b0a6: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800b0aa: f7f8 fa25 bl 80034f8 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
800b0ae: 4b1a ldr r3, [pc, #104] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0b0: 6cdb ldr r3, [r3, #76] @ 0x4c
800b0b2: 4a19 ldr r2, [pc, #100] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0b4: f443 5380 orr.w r3, r3, #4096 @ 0x1000
800b0b8: 64d3 str r3, [r2, #76] @ 0x4c
800b0ba: 4b17 ldr r3, [pc, #92] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0bc: 6cdb ldr r3, [r3, #76] @ 0x4c
800b0be: f403 5380 and.w r3, r3, #4096 @ 0x1000
800b0c2: 60fb str r3, [r7, #12]
800b0c4: 68fb ldr r3, [r7, #12]
/* Enable VDDUSB */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800b0c6: 4b14 ldr r3, [pc, #80] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0c8: 6d9b ldr r3, [r3, #88] @ 0x58
800b0ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800b0ce: 2b00 cmp r3, #0
800b0d0: d114 bne.n 800b0fc <HAL_PCD_MspInit+0xc8>
{
__HAL_RCC_PWR_CLK_ENABLE();
800b0d2: 4b11 ldr r3, [pc, #68] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0d4: 6d9b ldr r3, [r3, #88] @ 0x58
800b0d6: 4a10 ldr r2, [pc, #64] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0d8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800b0dc: 6593 str r3, [r2, #88] @ 0x58
800b0de: 4b0e ldr r3, [pc, #56] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0e0: 6d9b ldr r3, [r3, #88] @ 0x58
800b0e2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800b0e6: 60bb str r3, [r7, #8]
800b0e8: 68bb ldr r3, [r7, #8]
HAL_PWREx_EnableVddUSB();
800b0ea: f7f9 ff0f bl 8004f0c <HAL_PWREx_EnableVddUSB>
__HAL_RCC_PWR_CLK_DISABLE();
800b0ee: 4b0a ldr r3, [pc, #40] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0f0: 6d9b ldr r3, [r3, #88] @ 0x58
800b0f2: 4a09 ldr r2, [pc, #36] @ (800b118 <HAL_PCD_MspInit+0xe4>)
800b0f4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800b0f8: 6593 str r3, [r2, #88] @ 0x58
800b0fa: e001 b.n 800b100 <HAL_PCD_MspInit+0xcc>
}
else
{
HAL_PWREx_EnableVddUSB();
800b0fc: f7f9 ff06 bl 8004f0c <HAL_PWREx_EnableVddUSB>
}
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
800b100: 2200 movs r2, #0
800b102: 2100 movs r1, #0
800b104: 2043 movs r0, #67 @ 0x43
800b106: f7f8 f8b4 bl 8003272 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
800b10a: 2043 movs r0, #67 @ 0x43
800b10c: f7f8 f8cd bl 80032aa <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
800b110: bf00 nop
800b112: 3728 adds r7, #40 @ 0x28
800b114: 46bd mov sp, r7
800b116: bd80 pop {r7, pc}
800b118: 40021000 .word 0x40021000
0800b11c <HAL_PCD_SetupStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b11c: b580 push {r7, lr}
800b11e: b082 sub sp, #8
800b120: af00 add r7, sp, #0
800b122: 6078 str r0, [r7, #4]
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
800b124: 687b ldr r3, [r7, #4]
800b126: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0
800b12a: 687b ldr r3, [r7, #4]
800b12c: f203 439c addw r3, r3, #1180 @ 0x49c
800b130: 4619 mov r1, r3
800b132: 4610 mov r0, r2
800b134: f7fe fc01 bl 800993a <USBD_LL_SetupStage>
}
800b138: bf00 nop
800b13a: 3708 adds r7, #8
800b13c: 46bd mov sp, r7
800b13e: bd80 pop {r7, pc}
0800b140 <HAL_PCD_DataOutStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b140: b580 push {r7, lr}
800b142: b082 sub sp, #8
800b144: af00 add r7, sp, #0
800b146: 6078 str r0, [r7, #4]
800b148: 460b mov r3, r1
800b14a: 70fb strb r3, [r7, #3]
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
800b14c: 687b ldr r3, [r7, #4]
800b14e: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
800b152: 78fa ldrb r2, [r7, #3]
800b154: 6879 ldr r1, [r7, #4]
800b156: 4613 mov r3, r2
800b158: 00db lsls r3, r3, #3
800b15a: 4413 add r3, r2
800b15c: 009b lsls r3, r3, #2
800b15e: 440b add r3, r1
800b160: f503 7318 add.w r3, r3, #608 @ 0x260
800b164: 681a ldr r2, [r3, #0]
800b166: 78fb ldrb r3, [r7, #3]
800b168: 4619 mov r1, r3
800b16a: f7fe fc3b bl 80099e4 <USBD_LL_DataOutStage>
}
800b16e: bf00 nop
800b170: 3708 adds r7, #8
800b172: 46bd mov sp, r7
800b174: bd80 pop {r7, pc}
0800b176 <HAL_PCD_DataInStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b176: b580 push {r7, lr}
800b178: b082 sub sp, #8
800b17a: af00 add r7, sp, #0
800b17c: 6078 str r0, [r7, #4]
800b17e: 460b mov r3, r1
800b180: 70fb strb r3, [r7, #3]
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
800b182: 687b ldr r3, [r7, #4]
800b184: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
800b188: 78fa ldrb r2, [r7, #3]
800b18a: 6879 ldr r1, [r7, #4]
800b18c: 4613 mov r3, r2
800b18e: 00db lsls r3, r3, #3
800b190: 4413 add r3, r2
800b192: 009b lsls r3, r3, #2
800b194: 440b add r3, r1
800b196: 3320 adds r3, #32
800b198: 681a ldr r2, [r3, #0]
800b19a: 78fb ldrb r3, [r7, #3]
800b19c: 4619 mov r1, r3
800b19e: f7fe fcd4 bl 8009b4a <USBD_LL_DataInStage>
}
800b1a2: bf00 nop
800b1a4: 3708 adds r7, #8
800b1a6: 46bd mov sp, r7
800b1a8: bd80 pop {r7, pc}
0800b1aa <HAL_PCD_SOFCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b1aa: b580 push {r7, lr}
800b1ac: b082 sub sp, #8
800b1ae: af00 add r7, sp, #0
800b1b0: 6078 str r0, [r7, #4]
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
800b1b2: 687b ldr r3, [r7, #4]
800b1b4: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b1b8: 4618 mov r0, r3
800b1ba: f7fe fe0e bl 8009dda <USBD_LL_SOF>
}
800b1be: bf00 nop
800b1c0: 3708 adds r7, #8
800b1c2: 46bd mov sp, r7
800b1c4: bd80 pop {r7, pc}
0800b1c6 <HAL_PCD_ResetCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b1c6: b580 push {r7, lr}
800b1c8: b084 sub sp, #16
800b1ca: af00 add r7, sp, #0
800b1cc: 6078 str r0, [r7, #4]
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
800b1ce: 2301 movs r3, #1
800b1d0: 73fb strb r3, [r7, #15]
if ( hpcd->Init.speed != PCD_SPEED_FULL)
800b1d2: 687b ldr r3, [r7, #4]
800b1d4: 79db ldrb r3, [r3, #7]
800b1d6: 2b02 cmp r3, #2
800b1d8: d001 beq.n 800b1de <HAL_PCD_ResetCallback+0x18>
{
Error_Handler();
800b1da: f7f6 faf5 bl 80017c8 <Error_Handler>
}
/* Set Speed. */
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
800b1de: 687b ldr r3, [r7, #4]
800b1e0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b1e4: 7bfa ldrb r2, [r7, #15]
800b1e6: 4611 mov r1, r2
800b1e8: 4618 mov r0, r3
800b1ea: f7fe fdb2 bl 8009d52 <USBD_LL_SetSpeed>
/* Reset Device. */
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
800b1ee: 687b ldr r3, [r7, #4]
800b1f0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b1f4: 4618 mov r0, r3
800b1f6: f7fe fd5a bl 8009cae <USBD_LL_Reset>
}
800b1fa: bf00 nop
800b1fc: 3710 adds r7, #16
800b1fe: 46bd mov sp, r7
800b200: bd80 pop {r7, pc}
...
0800b204 <HAL_PCD_SuspendCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b204: b580 push {r7, lr}
800b206: b082 sub sp, #8
800b208: af00 add r7, sp, #0
800b20a: 6078 str r0, [r7, #4]
__HAL_PCD_GATE_PHYCLOCK(hpcd);
800b20c: 687b ldr r3, [r7, #4]
800b20e: 681b ldr r3, [r3, #0]
800b210: f503 6360 add.w r3, r3, #3584 @ 0xe00
800b214: 681b ldr r3, [r3, #0]
800b216: 687a ldr r2, [r7, #4]
800b218: 6812 ldr r2, [r2, #0]
800b21a: f502 6260 add.w r2, r2, #3584 @ 0xe00
800b21e: f043 0301 orr.w r3, r3, #1
800b222: 6013 str r3, [r2, #0]
/* Inform USB library that core enters in suspend Mode. */
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
800b224: 687b ldr r3, [r7, #4]
800b226: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b22a: 4618 mov r0, r3
800b22c: f7fe fda1 bl 8009d72 <USBD_LL_Suspend>
/* Enter in STOP mode. */
/* USER CODE BEGIN 2 */
if (hpcd->Init.low_power_enable)
800b230: 687b ldr r3, [r7, #4]
800b232: 7adb ldrb r3, [r3, #11]
800b234: 2b00 cmp r3, #0
800b236: d005 beq.n 800b244 <HAL_PCD_SuspendCallback+0x40>
{
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
800b238: 4b04 ldr r3, [pc, #16] @ (800b24c <HAL_PCD_SuspendCallback+0x48>)
800b23a: 691b ldr r3, [r3, #16]
800b23c: 4a03 ldr r2, [pc, #12] @ (800b24c <HAL_PCD_SuspendCallback+0x48>)
800b23e: f043 0306 orr.w r3, r3, #6
800b242: 6113 str r3, [r2, #16]
}
/* USER CODE END 2 */
}
800b244: bf00 nop
800b246: 3708 adds r7, #8
800b248: 46bd mov sp, r7
800b24a: bd80 pop {r7, pc}
800b24c: e000ed00 .word 0xe000ed00
0800b250 <HAL_PCD_ResumeCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b250: b580 push {r7, lr}
800b252: b082 sub sp, #8
800b254: af00 add r7, sp, #0
800b256: 6078 str r0, [r7, #4]
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
800b258: 687b ldr r3, [r7, #4]
800b25a: 681b ldr r3, [r3, #0]
800b25c: f503 6360 add.w r3, r3, #3584 @ 0xe00
800b260: 681b ldr r3, [r3, #0]
800b262: 687a ldr r2, [r7, #4]
800b264: 6812 ldr r2, [r2, #0]
800b266: f502 6260 add.w r2, r2, #3584 @ 0xe00
800b26a: f023 0301 bic.w r3, r3, #1
800b26e: 6013 str r3, [r2, #0]
/* USER CODE BEGIN 3 */
if (hpcd->Init.low_power_enable)
800b270: 687b ldr r3, [r7, #4]
800b272: 7adb ldrb r3, [r3, #11]
800b274: 2b00 cmp r3, #0
800b276: d007 beq.n 800b288 <HAL_PCD_ResumeCallback+0x38>
{
/* Reset SLEEPDEEP bit of Cortex System Control Register. */
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
800b278: 4b08 ldr r3, [pc, #32] @ (800b29c <HAL_PCD_ResumeCallback+0x4c>)
800b27a: 691b ldr r3, [r3, #16]
800b27c: 4a07 ldr r2, [pc, #28] @ (800b29c <HAL_PCD_ResumeCallback+0x4c>)
800b27e: f023 0306 bic.w r3, r3, #6
800b282: 6113 str r3, [r2, #16]
SystemClockConfig_Resume();
800b284: f000 fae2 bl 800b84c <SystemClockConfig_Resume>
}
/* USER CODE END 3 */
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
800b288: 687b ldr r3, [r7, #4]
800b28a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b28e: 4618 mov r0, r3
800b290: f7fe fd8b bl 8009daa <USBD_LL_Resume>
}
800b294: bf00 nop
800b296: 3708 adds r7, #8
800b298: 46bd mov sp, r7
800b29a: bd80 pop {r7, pc}
800b29c: e000ed00 .word 0xe000ed00
0800b2a0 <HAL_PCD_ISOOUTIncompleteCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b2a0: b580 push {r7, lr}
800b2a2: b082 sub sp, #8
800b2a4: af00 add r7, sp, #0
800b2a6: 6078 str r0, [r7, #4]
800b2a8: 460b mov r3, r1
800b2aa: 70fb strb r3, [r7, #3]
USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
800b2ac: 687b ldr r3, [r7, #4]
800b2ae: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b2b2: 78fa ldrb r2, [r7, #3]
800b2b4: 4611 mov r1, r2
800b2b6: 4618 mov r0, r3
800b2b8: f7fe fde1 bl 8009e7e <USBD_LL_IsoOUTIncomplete>
}
800b2bc: bf00 nop
800b2be: 3708 adds r7, #8
800b2c0: 46bd mov sp, r7
800b2c2: bd80 pop {r7, pc}
0800b2c4 <HAL_PCD_ISOINIncompleteCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b2c4: b580 push {r7, lr}
800b2c6: b082 sub sp, #8
800b2c8: af00 add r7, sp, #0
800b2ca: 6078 str r0, [r7, #4]
800b2cc: 460b mov r3, r1
800b2ce: 70fb strb r3, [r7, #3]
USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
800b2d0: 687b ldr r3, [r7, #4]
800b2d2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b2d6: 78fa ldrb r2, [r7, #3]
800b2d8: 4611 mov r1, r2
800b2da: 4618 mov r0, r3
800b2dc: f7fe fd9d bl 8009e1a <USBD_LL_IsoINIncomplete>
}
800b2e0: bf00 nop
800b2e2: 3708 adds r7, #8
800b2e4: 46bd mov sp, r7
800b2e6: bd80 pop {r7, pc}
0800b2e8 <HAL_PCD_ConnectCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b2e8: b580 push {r7, lr}
800b2ea: b082 sub sp, #8
800b2ec: af00 add r7, sp, #0
800b2ee: 6078 str r0, [r7, #4]
USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
800b2f0: 687b ldr r3, [r7, #4]
800b2f2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b2f6: 4618 mov r0, r3
800b2f8: f7fe fdf3 bl 8009ee2 <USBD_LL_DevConnected>
}
800b2fc: bf00 nop
800b2fe: 3708 adds r7, #8
800b300: 46bd mov sp, r7
800b302: bd80 pop {r7, pc}
0800b304 <HAL_PCD_DisconnectCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b304: b580 push {r7, lr}
800b306: b082 sub sp, #8
800b308: af00 add r7, sp, #0
800b30a: 6078 str r0, [r7, #4]
USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
800b30c: 687b ldr r3, [r7, #4]
800b30e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b312: 4618 mov r0, r3
800b314: f7fe fdf0 bl 8009ef8 <USBD_LL_DevDisconnected>
}
800b318: bf00 nop
800b31a: 3708 adds r7, #8
800b31c: 46bd mov sp, r7
800b31e: bd80 pop {r7, pc}
0800b320 <USBD_LL_Init>:
* @brief Initializes the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
{
800b320: b580 push {r7, lr}
800b322: b082 sub sp, #8
800b324: af00 add r7, sp, #0
800b326: 6078 str r0, [r7, #4]
/* Init USB Ip. */
if (pdev->id == DEVICE_FS) {
800b328: 687b ldr r3, [r7, #4]
800b32a: 781b ldrb r3, [r3, #0]
800b32c: 2b00 cmp r3, #0
800b32e: d13c bne.n 800b3aa <USBD_LL_Init+0x8a>
/* Enable USB power on Pwrctrl CR2 register. */
/* Link the driver to the stack. */
hpcd_USB_OTG_FS.pData = pdev;
800b330: 4a20 ldr r2, [pc, #128] @ (800b3b4 <USBD_LL_Init+0x94>)
800b332: 687b ldr r3, [r7, #4]
800b334: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0
pdev->pData = &hpcd_USB_OTG_FS;
800b338: 687b ldr r3, [r7, #4]
800b33a: 4a1e ldr r2, [pc, #120] @ (800b3b4 <USBD_LL_Init+0x94>)
800b33c: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
800b340: 4b1c ldr r3, [pc, #112] @ (800b3b4 <USBD_LL_Init+0x94>)
800b342: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
800b346: 601a str r2, [r3, #0]
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
800b348: 4b1a ldr r3, [pc, #104] @ (800b3b4 <USBD_LL_Init+0x94>)
800b34a: 2206 movs r2, #6
800b34c: 711a strb r2, [r3, #4]
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
800b34e: 4b19 ldr r3, [pc, #100] @ (800b3b4 <USBD_LL_Init+0x94>)
800b350: 2202 movs r2, #2
800b352: 71da strb r2, [r3, #7]
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
800b354: 4b17 ldr r3, [pc, #92] @ (800b3b4 <USBD_LL_Init+0x94>)
800b356: 2202 movs r2, #2
800b358: 725a strb r2, [r3, #9]
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
800b35a: 4b16 ldr r3, [pc, #88] @ (800b3b4 <USBD_LL_Init+0x94>)
800b35c: 2200 movs r2, #0
800b35e: 729a strb r2, [r3, #10]
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
800b360: 4b14 ldr r3, [pc, #80] @ (800b3b4 <USBD_LL_Init+0x94>)
800b362: 2200 movs r2, #0
800b364: 72da strb r2, [r3, #11]
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
800b366: 4b13 ldr r3, [pc, #76] @ (800b3b4 <USBD_LL_Init+0x94>)
800b368: 2200 movs r2, #0
800b36a: 731a strb r2, [r3, #12]
hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
800b36c: 4b11 ldr r3, [pc, #68] @ (800b3b4 <USBD_LL_Init+0x94>)
800b36e: 2200 movs r2, #0
800b370: 735a strb r2, [r3, #13]
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
800b372: 4b10 ldr r3, [pc, #64] @ (800b3b4 <USBD_LL_Init+0x94>)
800b374: 2200 movs r2, #0
800b376: 73da strb r2, [r3, #15]
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
800b378: 4b0e ldr r3, [pc, #56] @ (800b3b4 <USBD_LL_Init+0x94>)
800b37a: 2200 movs r2, #0
800b37c: 739a strb r2, [r3, #14]
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
800b37e: 480d ldr r0, [pc, #52] @ (800b3b4 <USBD_LL_Init+0x94>)
800b380: f7f8 fbd1 bl 8003b26 <HAL_PCD_Init>
800b384: 4603 mov r3, r0
800b386: 2b00 cmp r3, #0
800b388: d001 beq.n 800b38e <USBD_LL_Init+0x6e>
{
Error_Handler( );
800b38a: f7f6 fa1d bl 80017c8 <Error_Handler>
HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
800b38e: 2180 movs r1, #128 @ 0x80
800b390: 4808 ldr r0, [pc, #32] @ (800b3b4 <USBD_LL_Init+0x94>)
800b392: f7f9 fd12 bl 8004dba <HAL_PCDEx_SetRxFiFo>
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
800b396: 2240 movs r2, #64 @ 0x40
800b398: 2100 movs r1, #0
800b39a: 4806 ldr r0, [pc, #24] @ (800b3b4 <USBD_LL_Init+0x94>)
800b39c: f7f9 fcc6 bl 8004d2c <HAL_PCDEx_SetTxFiFo>
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
800b3a0: 2280 movs r2, #128 @ 0x80
800b3a2: 2101 movs r1, #1
800b3a4: 4803 ldr r0, [pc, #12] @ (800b3b4 <USBD_LL_Init+0x94>)
800b3a6: f7f9 fcc1 bl 8004d2c <HAL_PCDEx_SetTxFiFo>
}
return USBD_OK;
800b3aa: 2300 movs r3, #0
}
800b3ac: 4618 mov r0, r3
800b3ae: 3708 adds r7, #8
800b3b0: 46bd mov sp, r7
800b3b2: bd80 pop {r7, pc}
800b3b4: 20000bac .word 0x20000bac
0800b3b8 <USBD_LL_Start>:
* @brief Starts the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
800b3b8: b580 push {r7, lr}
800b3ba: b084 sub sp, #16
800b3bc: af00 add r7, sp, #0
800b3be: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
800b3c0: 2300 movs r3, #0
800b3c2: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
800b3c4: 2300 movs r3, #0
800b3c6: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_Start(pdev->pData);
800b3c8: 687b ldr r3, [r7, #4]
800b3ca: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
800b3ce: 4618 mov r0, r3
800b3d0: f7f8 fcb8 bl 8003d44 <HAL_PCD_Start>
800b3d4: 4603 mov r3, r0
800b3d6: 73bb strb r3, [r7, #14]
switch (hal_status) {
800b3d8: 7bbb ldrb r3, [r7, #14]
800b3da: 2b03 cmp r3, #3
800b3dc: d816 bhi.n 800b40c <USBD_LL_Start+0x54>
800b3de: a201 add r2, pc, #4 @ (adr r2, 800b3e4 <USBD_LL_Start+0x2c>)
800b3e0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b3e4: 0800b3f5 .word 0x0800b3f5
800b3e8: 0800b3fb .word 0x0800b3fb
800b3ec: 0800b401 .word 0x0800b401
800b3f0: 0800b407 .word 0x0800b407
case HAL_OK :
usb_status = USBD_OK;
800b3f4: 2300 movs r3, #0
800b3f6: 73fb strb r3, [r7, #15]
break;
800b3f8: e00b b.n 800b412 <USBD_LL_Start+0x5a>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b3fa: 2303 movs r3, #3
800b3fc: 73fb strb r3, [r7, #15]
break;
800b3fe: e008 b.n 800b412 <USBD_LL_Start+0x5a>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b400: 2301 movs r3, #1
800b402: 73fb strb r3, [r7, #15]
break;
800b404: e005 b.n 800b412 <USBD_LL_Start+0x5a>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b406: 2303 movs r3, #3
800b408: 73fb strb r3, [r7, #15]
break;
800b40a: e002 b.n 800b412 <USBD_LL_Start+0x5a>
default :
usb_status = USBD_FAIL;
800b40c: 2303 movs r3, #3
800b40e: 73fb strb r3, [r7, #15]
break;
800b410: bf00 nop
}
return usb_status;
800b412: 7bfb ldrb r3, [r7, #15]
}
800b414: 4618 mov r0, r3
800b416: 3710 adds r7, #16
800b418: 46bd mov sp, r7
800b41a: bd80 pop {r7, pc}
0800b41c <USBD_LL_OpenEP>:
* @param ep_type: Endpoint type
* @param ep_mps: Endpoint max packet size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
{
800b41c: b580 push {r7, lr}
800b41e: b084 sub sp, #16
800b420: af00 add r7, sp, #0
800b422: 6078 str r0, [r7, #4]
800b424: 4608 mov r0, r1
800b426: 4611 mov r1, r2
800b428: 461a mov r2, r3
800b42a: 4603 mov r3, r0
800b42c: 70fb strb r3, [r7, #3]
800b42e: 460b mov r3, r1
800b430: 70bb strb r3, [r7, #2]
800b432: 4613 mov r3, r2
800b434: 803b strh r3, [r7, #0]
HAL_StatusTypeDef hal_status = HAL_OK;
800b436: 2300 movs r3, #0
800b438: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
800b43a: 2300 movs r3, #0
800b43c: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
800b43e: 687b ldr r3, [r7, #4]
800b440: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
800b444: 78bb ldrb r3, [r7, #2]
800b446: 883a ldrh r2, [r7, #0]
800b448: 78f9 ldrb r1, [r7, #3]
800b44a: f7f9 f964 bl 8004716 <HAL_PCD_EP_Open>
800b44e: 4603 mov r3, r0
800b450: 73bb strb r3, [r7, #14]
switch (hal_status) {
800b452: 7bbb ldrb r3, [r7, #14]
800b454: 2b03 cmp r3, #3
800b456: d817 bhi.n 800b488 <USBD_LL_OpenEP+0x6c>
800b458: a201 add r2, pc, #4 @ (adr r2, 800b460 <USBD_LL_OpenEP+0x44>)
800b45a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b45e: bf00 nop
800b460: 0800b471 .word 0x0800b471
800b464: 0800b477 .word 0x0800b477
800b468: 0800b47d .word 0x0800b47d
800b46c: 0800b483 .word 0x0800b483
case HAL_OK :
usb_status = USBD_OK;
800b470: 2300 movs r3, #0
800b472: 73fb strb r3, [r7, #15]
break;
800b474: e00b b.n 800b48e <USBD_LL_OpenEP+0x72>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b476: 2303 movs r3, #3
800b478: 73fb strb r3, [r7, #15]
break;
800b47a: e008 b.n 800b48e <USBD_LL_OpenEP+0x72>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b47c: 2301 movs r3, #1
800b47e: 73fb strb r3, [r7, #15]
break;
800b480: e005 b.n 800b48e <USBD_LL_OpenEP+0x72>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b482: 2303 movs r3, #3
800b484: 73fb strb r3, [r7, #15]
break;
800b486: e002 b.n 800b48e <USBD_LL_OpenEP+0x72>
default :
usb_status = USBD_FAIL;
800b488: 2303 movs r3, #3
800b48a: 73fb strb r3, [r7, #15]
break;
800b48c: bf00 nop
}
return usb_status;
800b48e: 7bfb ldrb r3, [r7, #15]
}
800b490: 4618 mov r0, r3
800b492: 3710 adds r7, #16
800b494: 46bd mov sp, r7
800b496: bd80 pop {r7, pc}
0800b498 <USBD_LL_CloseEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b498: b580 push {r7, lr}
800b49a: b084 sub sp, #16
800b49c: af00 add r7, sp, #0
800b49e: 6078 str r0, [r7, #4]
800b4a0: 460b mov r3, r1
800b4a2: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800b4a4: 2300 movs r3, #0
800b4a6: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
800b4a8: 2300 movs r3, #0
800b4aa: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
800b4ac: 687b ldr r3, [r7, #4]
800b4ae: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
800b4b2: 78fa ldrb r2, [r7, #3]
800b4b4: 4611 mov r1, r2
800b4b6: 4618 mov r0, r3
800b4b8: f7f9 f997 bl 80047ea <HAL_PCD_EP_Close>
800b4bc: 4603 mov r3, r0
800b4be: 73bb strb r3, [r7, #14]
switch (hal_status) {
800b4c0: 7bbb ldrb r3, [r7, #14]
800b4c2: 2b03 cmp r3, #3
800b4c4: d816 bhi.n 800b4f4 <USBD_LL_CloseEP+0x5c>
800b4c6: a201 add r2, pc, #4 @ (adr r2, 800b4cc <USBD_LL_CloseEP+0x34>)
800b4c8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b4cc: 0800b4dd .word 0x0800b4dd
800b4d0: 0800b4e3 .word 0x0800b4e3
800b4d4: 0800b4e9 .word 0x0800b4e9
800b4d8: 0800b4ef .word 0x0800b4ef
case HAL_OK :
usb_status = USBD_OK;
800b4dc: 2300 movs r3, #0
800b4de: 73fb strb r3, [r7, #15]
break;
800b4e0: e00b b.n 800b4fa <USBD_LL_CloseEP+0x62>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b4e2: 2303 movs r3, #3
800b4e4: 73fb strb r3, [r7, #15]
break;
800b4e6: e008 b.n 800b4fa <USBD_LL_CloseEP+0x62>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b4e8: 2301 movs r3, #1
800b4ea: 73fb strb r3, [r7, #15]
break;
800b4ec: e005 b.n 800b4fa <USBD_LL_CloseEP+0x62>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b4ee: 2303 movs r3, #3
800b4f0: 73fb strb r3, [r7, #15]
break;
800b4f2: e002 b.n 800b4fa <USBD_LL_CloseEP+0x62>
default :
usb_status = USBD_FAIL;
800b4f4: 2303 movs r3, #3
800b4f6: 73fb strb r3, [r7, #15]
break;
800b4f8: bf00 nop
}
return usb_status;
800b4fa: 7bfb ldrb r3, [r7, #15]
}
800b4fc: 4618 mov r0, r3
800b4fe: 3710 adds r7, #16
800b500: 46bd mov sp, r7
800b502: bd80 pop {r7, pc}
0800b504 <USBD_LL_StallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b504: b580 push {r7, lr}
800b506: b084 sub sp, #16
800b508: af00 add r7, sp, #0
800b50a: 6078 str r0, [r7, #4]
800b50c: 460b mov r3, r1
800b50e: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800b510: 2300 movs r3, #0
800b512: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
800b514: 2300 movs r3, #0
800b516: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
800b518: 687b ldr r3, [r7, #4]
800b51a: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
800b51e: 78fa ldrb r2, [r7, #3]
800b520: 4611 mov r1, r2
800b522: 4618 mov r0, r3
800b524: f7f9 fa0e bl 8004944 <HAL_PCD_EP_SetStall>
800b528: 4603 mov r3, r0
800b52a: 73bb strb r3, [r7, #14]
switch (hal_status) {
800b52c: 7bbb ldrb r3, [r7, #14]
800b52e: 2b03 cmp r3, #3
800b530: d816 bhi.n 800b560 <USBD_LL_StallEP+0x5c>
800b532: a201 add r2, pc, #4 @ (adr r2, 800b538 <USBD_LL_StallEP+0x34>)
800b534: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b538: 0800b549 .word 0x0800b549
800b53c: 0800b54f .word 0x0800b54f
800b540: 0800b555 .word 0x0800b555
800b544: 0800b55b .word 0x0800b55b
case HAL_OK :
usb_status = USBD_OK;
800b548: 2300 movs r3, #0
800b54a: 73fb strb r3, [r7, #15]
break;
800b54c: e00b b.n 800b566 <USBD_LL_StallEP+0x62>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b54e: 2303 movs r3, #3
800b550: 73fb strb r3, [r7, #15]
break;
800b552: e008 b.n 800b566 <USBD_LL_StallEP+0x62>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b554: 2301 movs r3, #1
800b556: 73fb strb r3, [r7, #15]
break;
800b558: e005 b.n 800b566 <USBD_LL_StallEP+0x62>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b55a: 2303 movs r3, #3
800b55c: 73fb strb r3, [r7, #15]
break;
800b55e: e002 b.n 800b566 <USBD_LL_StallEP+0x62>
default :
usb_status = USBD_FAIL;
800b560: 2303 movs r3, #3
800b562: 73fb strb r3, [r7, #15]
break;
800b564: bf00 nop
}
return usb_status;
800b566: 7bfb ldrb r3, [r7, #15]
}
800b568: 4618 mov r0, r3
800b56a: 3710 adds r7, #16
800b56c: 46bd mov sp, r7
800b56e: bd80 pop {r7, pc}
0800b570 <USBD_LL_ClearStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b570: b580 push {r7, lr}
800b572: b084 sub sp, #16
800b574: af00 add r7, sp, #0
800b576: 6078 str r0, [r7, #4]
800b578: 460b mov r3, r1
800b57a: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800b57c: 2300 movs r3, #0
800b57e: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
800b580: 2300 movs r3, #0
800b582: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
800b584: 687b ldr r3, [r7, #4]
800b586: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
800b58a: 78fa ldrb r2, [r7, #3]
800b58c: 4611 mov r1, r2
800b58e: 4618 mov r0, r3
800b590: f7f9 fa3a bl 8004a08 <HAL_PCD_EP_ClrStall>
800b594: 4603 mov r3, r0
800b596: 73bb strb r3, [r7, #14]
switch (hal_status) {
800b598: 7bbb ldrb r3, [r7, #14]
800b59a: 2b03 cmp r3, #3
800b59c: d816 bhi.n 800b5cc <USBD_LL_ClearStallEP+0x5c>
800b59e: a201 add r2, pc, #4 @ (adr r2, 800b5a4 <USBD_LL_ClearStallEP+0x34>)
800b5a0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b5a4: 0800b5b5 .word 0x0800b5b5
800b5a8: 0800b5bb .word 0x0800b5bb
800b5ac: 0800b5c1 .word 0x0800b5c1
800b5b0: 0800b5c7 .word 0x0800b5c7
case HAL_OK :
usb_status = USBD_OK;
800b5b4: 2300 movs r3, #0
800b5b6: 73fb strb r3, [r7, #15]
break;
800b5b8: e00b b.n 800b5d2 <USBD_LL_ClearStallEP+0x62>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b5ba: 2303 movs r3, #3
800b5bc: 73fb strb r3, [r7, #15]
break;
800b5be: e008 b.n 800b5d2 <USBD_LL_ClearStallEP+0x62>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b5c0: 2301 movs r3, #1
800b5c2: 73fb strb r3, [r7, #15]
break;
800b5c4: e005 b.n 800b5d2 <USBD_LL_ClearStallEP+0x62>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b5c6: 2303 movs r3, #3
800b5c8: 73fb strb r3, [r7, #15]
break;
800b5ca: e002 b.n 800b5d2 <USBD_LL_ClearStallEP+0x62>
default :
usb_status = USBD_FAIL;
800b5cc: 2303 movs r3, #3
800b5ce: 73fb strb r3, [r7, #15]
break;
800b5d0: bf00 nop
}
return usb_status;
800b5d2: 7bfb ldrb r3, [r7, #15]
}
800b5d4: 4618 mov r0, r3
800b5d6: 3710 adds r7, #16
800b5d8: 46bd mov sp, r7
800b5da: bd80 pop {r7, pc}
0800b5dc <USBD_LL_IsStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Stall (1: Yes, 0: No)
*/
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b5dc: b480 push {r7}
800b5de: b085 sub sp, #20
800b5e0: af00 add r7, sp, #0
800b5e2: 6078 str r0, [r7, #4]
800b5e4: 460b mov r3, r1
800b5e6: 70fb strb r3, [r7, #3]
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
800b5e8: 687b ldr r3, [r7, #4]
800b5ea: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
800b5ee: 60fb str r3, [r7, #12]
if((ep_addr & 0x80) == 0x80)
800b5f0: f997 3003 ldrsb.w r3, [r7, #3]
800b5f4: 2b00 cmp r3, #0
800b5f6: da0b bge.n 800b610 <USBD_LL_IsStallEP+0x34>
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
800b5f8: 78fb ldrb r3, [r7, #3]
800b5fa: f003 027f and.w r2, r3, #127 @ 0x7f
800b5fe: 68f9 ldr r1, [r7, #12]
800b600: 4613 mov r3, r2
800b602: 00db lsls r3, r3, #3
800b604: 4413 add r3, r2
800b606: 009b lsls r3, r3, #2
800b608: 440b add r3, r1
800b60a: 3316 adds r3, #22
800b60c: 781b ldrb r3, [r3, #0]
800b60e: e00b b.n 800b628 <USBD_LL_IsStallEP+0x4c>
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
800b610: 78fb ldrb r3, [r7, #3]
800b612: f003 027f and.w r2, r3, #127 @ 0x7f
800b616: 68f9 ldr r1, [r7, #12]
800b618: 4613 mov r3, r2
800b61a: 00db lsls r3, r3, #3
800b61c: 4413 add r3, r2
800b61e: 009b lsls r3, r3, #2
800b620: 440b add r3, r1
800b622: f203 2356 addw r3, r3, #598 @ 0x256
800b626: 781b ldrb r3, [r3, #0]
}
}
800b628: 4618 mov r0, r3
800b62a: 3714 adds r7, #20
800b62c: 46bd mov sp, r7
800b62e: f85d 7b04 ldr.w r7, [sp], #4
800b632: 4770 bx lr
0800b634 <USBD_LL_SetUSBAddress>:
* @param pdev: Device handle
* @param dev_addr: Device address
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
{
800b634: b580 push {r7, lr}
800b636: b084 sub sp, #16
800b638: af00 add r7, sp, #0
800b63a: 6078 str r0, [r7, #4]
800b63c: 460b mov r3, r1
800b63e: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800b640: 2300 movs r3, #0
800b642: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
800b644: 2300 movs r3, #0
800b646: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
800b648: 687b ldr r3, [r7, #4]
800b64a: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
800b64e: 78fa ldrb r2, [r7, #3]
800b650: 4611 mov r1, r2
800b652: 4618 mov r0, r3
800b654: f7f9 f83b bl 80046ce <HAL_PCD_SetAddress>
800b658: 4603 mov r3, r0
800b65a: 73bb strb r3, [r7, #14]
switch (hal_status) {
800b65c: 7bbb ldrb r3, [r7, #14]
800b65e: 2b03 cmp r3, #3
800b660: d816 bhi.n 800b690 <USBD_LL_SetUSBAddress+0x5c>
800b662: a201 add r2, pc, #4 @ (adr r2, 800b668 <USBD_LL_SetUSBAddress+0x34>)
800b664: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b668: 0800b679 .word 0x0800b679
800b66c: 0800b67f .word 0x0800b67f
800b670: 0800b685 .word 0x0800b685
800b674: 0800b68b .word 0x0800b68b
case HAL_OK :
usb_status = USBD_OK;
800b678: 2300 movs r3, #0
800b67a: 73fb strb r3, [r7, #15]
break;
800b67c: e00b b.n 800b696 <USBD_LL_SetUSBAddress+0x62>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b67e: 2303 movs r3, #3
800b680: 73fb strb r3, [r7, #15]
break;
800b682: e008 b.n 800b696 <USBD_LL_SetUSBAddress+0x62>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b684: 2301 movs r3, #1
800b686: 73fb strb r3, [r7, #15]
break;
800b688: e005 b.n 800b696 <USBD_LL_SetUSBAddress+0x62>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b68a: 2303 movs r3, #3
800b68c: 73fb strb r3, [r7, #15]
break;
800b68e: e002 b.n 800b696 <USBD_LL_SetUSBAddress+0x62>
default :
usb_status = USBD_FAIL;
800b690: 2303 movs r3, #3
800b692: 73fb strb r3, [r7, #15]
break;
800b694: bf00 nop
}
return usb_status;
800b696: 7bfb ldrb r3, [r7, #15]
}
800b698: 4618 mov r0, r3
800b69a: 3710 adds r7, #16
800b69c: 46bd mov sp, r7
800b69e: bd80 pop {r7, pc}
0800b6a0 <USBD_LL_Transmit>:
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
{
800b6a0: b580 push {r7, lr}
800b6a2: b086 sub sp, #24
800b6a4: af00 add r7, sp, #0
800b6a6: 60f8 str r0, [r7, #12]
800b6a8: 607a str r2, [r7, #4]
800b6aa: 603b str r3, [r7, #0]
800b6ac: 460b mov r3, r1
800b6ae: 72fb strb r3, [r7, #11]
HAL_StatusTypeDef hal_status = HAL_OK;
800b6b0: 2300 movs r3, #0
800b6b2: 75bb strb r3, [r7, #22]
USBD_StatusTypeDef usb_status = USBD_OK;
800b6b4: 2300 movs r3, #0
800b6b6: 75fb strb r3, [r7, #23]
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
800b6b8: 68fb ldr r3, [r7, #12]
800b6ba: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
800b6be: 7af9 ldrb r1, [r7, #11]
800b6c0: 683b ldr r3, [r7, #0]
800b6c2: 687a ldr r2, [r7, #4]
800b6c4: f7f9 f90d bl 80048e2 <HAL_PCD_EP_Transmit>
800b6c8: 4603 mov r3, r0
800b6ca: 75bb strb r3, [r7, #22]
switch (hal_status) {
800b6cc: 7dbb ldrb r3, [r7, #22]
800b6ce: 2b03 cmp r3, #3
800b6d0: d816 bhi.n 800b700 <USBD_LL_Transmit+0x60>
800b6d2: a201 add r2, pc, #4 @ (adr r2, 800b6d8 <USBD_LL_Transmit+0x38>)
800b6d4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b6d8: 0800b6e9 .word 0x0800b6e9
800b6dc: 0800b6ef .word 0x0800b6ef
800b6e0: 0800b6f5 .word 0x0800b6f5
800b6e4: 0800b6fb .word 0x0800b6fb
case HAL_OK :
usb_status = USBD_OK;
800b6e8: 2300 movs r3, #0
800b6ea: 75fb strb r3, [r7, #23]
break;
800b6ec: e00b b.n 800b706 <USBD_LL_Transmit+0x66>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b6ee: 2303 movs r3, #3
800b6f0: 75fb strb r3, [r7, #23]
break;
800b6f2: e008 b.n 800b706 <USBD_LL_Transmit+0x66>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b6f4: 2301 movs r3, #1
800b6f6: 75fb strb r3, [r7, #23]
break;
800b6f8: e005 b.n 800b706 <USBD_LL_Transmit+0x66>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b6fa: 2303 movs r3, #3
800b6fc: 75fb strb r3, [r7, #23]
break;
800b6fe: e002 b.n 800b706 <USBD_LL_Transmit+0x66>
default :
usb_status = USBD_FAIL;
800b700: 2303 movs r3, #3
800b702: 75fb strb r3, [r7, #23]
break;
800b704: bf00 nop
}
return usb_status;
800b706: 7dfb ldrb r3, [r7, #23]
}
800b708: 4618 mov r0, r3
800b70a: 3718 adds r7, #24
800b70c: 46bd mov sp, r7
800b70e: bd80 pop {r7, pc}
0800b710 <USBD_LL_PrepareReceive>:
* @param pbuf: Pointer to data to be received
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
{
800b710: b580 push {r7, lr}
800b712: b086 sub sp, #24
800b714: af00 add r7, sp, #0
800b716: 60f8 str r0, [r7, #12]
800b718: 607a str r2, [r7, #4]
800b71a: 603b str r3, [r7, #0]
800b71c: 460b mov r3, r1
800b71e: 72fb strb r3, [r7, #11]
HAL_StatusTypeDef hal_status = HAL_OK;
800b720: 2300 movs r3, #0
800b722: 75bb strb r3, [r7, #22]
USBD_StatusTypeDef usb_status = USBD_OK;
800b724: 2300 movs r3, #0
800b726: 75fb strb r3, [r7, #23]
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
800b728: 68fb ldr r3, [r7, #12]
800b72a: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
800b72e: 7af9 ldrb r1, [r7, #11]
800b730: 683b ldr r3, [r7, #0]
800b732: 687a ldr r2, [r7, #4]
800b734: f7f9 f8a3 bl 800487e <HAL_PCD_EP_Receive>
800b738: 4603 mov r3, r0
800b73a: 75bb strb r3, [r7, #22]
switch (hal_status) {
800b73c: 7dbb ldrb r3, [r7, #22]
800b73e: 2b03 cmp r3, #3
800b740: d816 bhi.n 800b770 <USBD_LL_PrepareReceive+0x60>
800b742: a201 add r2, pc, #4 @ (adr r2, 800b748 <USBD_LL_PrepareReceive+0x38>)
800b744: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b748: 0800b759 .word 0x0800b759
800b74c: 0800b75f .word 0x0800b75f
800b750: 0800b765 .word 0x0800b765
800b754: 0800b76b .word 0x0800b76b
case HAL_OK :
usb_status = USBD_OK;
800b758: 2300 movs r3, #0
800b75a: 75fb strb r3, [r7, #23]
break;
800b75c: e00b b.n 800b776 <USBD_LL_PrepareReceive+0x66>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b75e: 2303 movs r3, #3
800b760: 75fb strb r3, [r7, #23]
break;
800b762: e008 b.n 800b776 <USBD_LL_PrepareReceive+0x66>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b764: 2301 movs r3, #1
800b766: 75fb strb r3, [r7, #23]
break;
800b768: e005 b.n 800b776 <USBD_LL_PrepareReceive+0x66>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b76a: 2303 movs r3, #3
800b76c: 75fb strb r3, [r7, #23]
break;
800b76e: e002 b.n 800b776 <USBD_LL_PrepareReceive+0x66>
default :
usb_status = USBD_FAIL;
800b770: 2303 movs r3, #3
800b772: 75fb strb r3, [r7, #23]
break;
800b774: bf00 nop
}
return usb_status;
800b776: 7dfb ldrb r3, [r7, #23]
}
800b778: 4618 mov r0, r3
800b77a: 3718 adds r7, #24
800b77c: 46bd mov sp, r7
800b77e: bd80 pop {r7, pc}
0800b780 <HAL_PCDEx_LPM_Callback>:
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval None
*/
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
800b780: b580 push {r7, lr}
800b782: b082 sub sp, #8
800b784: af00 add r7, sp, #0
800b786: 6078 str r0, [r7, #4]
800b788: 460b mov r3, r1
800b78a: 70fb strb r3, [r7, #3]
switch (msg)
800b78c: 78fb ldrb r3, [r7, #3]
800b78e: 2b00 cmp r3, #0
800b790: d002 beq.n 800b798 <HAL_PCDEx_LPM_Callback+0x18>
800b792: 2b01 cmp r3, #1
800b794: d01f beq.n 800b7d6 <HAL_PCDEx_LPM_Callback+0x56>
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
}
break;
}
}
800b796: e03b b.n 800b810 <HAL_PCDEx_LPM_Callback+0x90>
if (hpcd->Init.low_power_enable)
800b798: 687b ldr r3, [r7, #4]
800b79a: 7adb ldrb r3, [r3, #11]
800b79c: 2b00 cmp r3, #0
800b79e: d007 beq.n 800b7b0 <HAL_PCDEx_LPM_Callback+0x30>
SystemClockConfig_Resume();
800b7a0: f000 f854 bl 800b84c <SystemClockConfig_Resume>
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
800b7a4: 4b1c ldr r3, [pc, #112] @ (800b818 <HAL_PCDEx_LPM_Callback+0x98>)
800b7a6: 691b ldr r3, [r3, #16]
800b7a8: 4a1b ldr r2, [pc, #108] @ (800b818 <HAL_PCDEx_LPM_Callback+0x98>)
800b7aa: f023 0306 bic.w r3, r3, #6
800b7ae: 6113 str r3, [r2, #16]
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
800b7b0: 687b ldr r3, [r7, #4]
800b7b2: 681b ldr r3, [r3, #0]
800b7b4: f503 6360 add.w r3, r3, #3584 @ 0xe00
800b7b8: 681b ldr r3, [r3, #0]
800b7ba: 687a ldr r2, [r7, #4]
800b7bc: 6812 ldr r2, [r2, #0]
800b7be: f502 6260 add.w r2, r2, #3584 @ 0xe00
800b7c2: f023 0301 bic.w r3, r3, #1
800b7c6: 6013 str r3, [r2, #0]
USBD_LL_Resume(hpcd->pData);
800b7c8: 687b ldr r3, [r7, #4]
800b7ca: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b7ce: 4618 mov r0, r3
800b7d0: f7fe faeb bl 8009daa <USBD_LL_Resume>
break;
800b7d4: e01c b.n 800b810 <HAL_PCDEx_LPM_Callback+0x90>
__HAL_PCD_GATE_PHYCLOCK(hpcd);
800b7d6: 687b ldr r3, [r7, #4]
800b7d8: 681b ldr r3, [r3, #0]
800b7da: f503 6360 add.w r3, r3, #3584 @ 0xe00
800b7de: 681b ldr r3, [r3, #0]
800b7e0: 687a ldr r2, [r7, #4]
800b7e2: 6812 ldr r2, [r2, #0]
800b7e4: f502 6260 add.w r2, r2, #3584 @ 0xe00
800b7e8: f043 0301 orr.w r3, r3, #1
800b7ec: 6013 str r3, [r2, #0]
USBD_LL_Suspend(hpcd->pData);
800b7ee: 687b ldr r3, [r7, #4]
800b7f0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
800b7f4: 4618 mov r0, r3
800b7f6: f7fe fabc bl 8009d72 <USBD_LL_Suspend>
if (hpcd->Init.low_power_enable)
800b7fa: 687b ldr r3, [r7, #4]
800b7fc: 7adb ldrb r3, [r3, #11]
800b7fe: 2b00 cmp r3, #0
800b800: d005 beq.n 800b80e <HAL_PCDEx_LPM_Callback+0x8e>
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
800b802: 4b05 ldr r3, [pc, #20] @ (800b818 <HAL_PCDEx_LPM_Callback+0x98>)
800b804: 691b ldr r3, [r3, #16]
800b806: 4a04 ldr r2, [pc, #16] @ (800b818 <HAL_PCDEx_LPM_Callback+0x98>)
800b808: f043 0306 orr.w r3, r3, #6
800b80c: 6113 str r3, [r2, #16]
break;
800b80e: bf00 nop
}
800b810: bf00 nop
800b812: 3708 adds r7, #8
800b814: 46bd mov sp, r7
800b816: bd80 pop {r7, pc}
800b818: e000ed00 .word 0xe000ed00
0800b81c <USBD_static_malloc>:
* @brief Static single allocation.
* @param size: Size of allocated memory
* @retval None
*/
void *USBD_static_malloc(uint32_t size)
{
800b81c: b480 push {r7}
800b81e: b083 sub sp, #12
800b820: af00 add r7, sp, #0
800b822: 6078 str r0, [r7, #4]
static uint32_t mem[(sizeof(USBD_MIDI_HandleTypeDef)/4+1)];/* On 32-bit boundary */
return mem;
800b824: 4b03 ldr r3, [pc, #12] @ (800b834 <USBD_static_malloc+0x18>)
}
800b826: 4618 mov r0, r3
800b828: 370c adds r7, #12
800b82a: 46bd mov sp, r7
800b82c: f85d 7b04 ldr.w r7, [sp], #4
800b830: 4770 bx lr
800b832: bf00 nop
800b834: 20001090 .word 0x20001090
0800b838 <USBD_static_free>:
* @brief Dummy memory free
* @param p: Pointer to allocated memory address
* @retval None
*/
void USBD_static_free(void *p)
{
800b838: b480 push {r7}
800b83a: b083 sub sp, #12
800b83c: af00 add r7, sp, #0
800b83e: 6078 str r0, [r7, #4]
}
800b840: bf00 nop
800b842: 370c adds r7, #12
800b844: 46bd mov sp, r7
800b846: f85d 7b04 ldr.w r7, [sp], #4
800b84a: 4770 bx lr
0800b84c <SystemClockConfig_Resume>:
* @brief Configures system clock after wake-up from USB resume callBack:
* enable HSI, PLL and select PLL as system clock source.
* @retval None
*/
static void SystemClockConfig_Resume(void)
{
800b84c: b580 push {r7, lr}
800b84e: af00 add r7, sp, #0
SystemClock_Config();
800b850: f7f5 fb70 bl 8000f34 <SystemClock_Config>
}
800b854: bf00 nop
800b856: bd80 pop {r7, pc}
0800b858 <__cvt>:
800b858: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
800b85c: ec57 6b10 vmov r6, r7, d0
800b860: 2f00 cmp r7, #0
800b862: 460c mov r4, r1
800b864: 4619 mov r1, r3
800b866: 463b mov r3, r7
800b868: bfbb ittet lt
800b86a: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000
800b86e: 461f movlt r7, r3
800b870: 2300 movge r3, #0
800b872: 232d movlt r3, #45 @ 0x2d
800b874: 700b strb r3, [r1, #0]
800b876: 9b0d ldr r3, [sp, #52] @ 0x34
800b878: f8dd a030 ldr.w sl, [sp, #48] @ 0x30
800b87c: 4691 mov r9, r2
800b87e: f023 0820 bic.w r8, r3, #32
800b882: bfbc itt lt
800b884: 4632 movlt r2, r6
800b886: 4616 movlt r6, r2
800b888: f1b8 0f46 cmp.w r8, #70 @ 0x46
800b88c: d005 beq.n 800b89a <__cvt+0x42>
800b88e: f1b8 0f45 cmp.w r8, #69 @ 0x45
800b892: d100 bne.n 800b896 <__cvt+0x3e>
800b894: 3401 adds r4, #1
800b896: 2102 movs r1, #2
800b898: e000 b.n 800b89c <__cvt+0x44>
800b89a: 2103 movs r1, #3
800b89c: ab03 add r3, sp, #12
800b89e: 9301 str r3, [sp, #4]
800b8a0: ab02 add r3, sp, #8
800b8a2: 9300 str r3, [sp, #0]
800b8a4: ec47 6b10 vmov d0, r6, r7
800b8a8: 4653 mov r3, sl
800b8aa: 4622 mov r2, r4
800b8ac: f000 fe38 bl 800c520 <_dtoa_r>
800b8b0: f1b8 0f47 cmp.w r8, #71 @ 0x47
800b8b4: 4605 mov r5, r0
800b8b6: d119 bne.n 800b8ec <__cvt+0x94>
800b8b8: f019 0f01 tst.w r9, #1
800b8bc: d00e beq.n 800b8dc <__cvt+0x84>
800b8be: eb00 0904 add.w r9, r0, r4
800b8c2: 2200 movs r2, #0
800b8c4: 2300 movs r3, #0
800b8c6: 4630 mov r0, r6
800b8c8: 4639 mov r1, r7
800b8ca: f7f5 f8fd bl 8000ac8 <__aeabi_dcmpeq>
800b8ce: b108 cbz r0, 800b8d4 <__cvt+0x7c>
800b8d0: f8cd 900c str.w r9, [sp, #12]
800b8d4: 2230 movs r2, #48 @ 0x30
800b8d6: 9b03 ldr r3, [sp, #12]
800b8d8: 454b cmp r3, r9
800b8da: d31e bcc.n 800b91a <__cvt+0xc2>
800b8dc: 9b03 ldr r3, [sp, #12]
800b8de: 9a0e ldr r2, [sp, #56] @ 0x38
800b8e0: 1b5b subs r3, r3, r5
800b8e2: 4628 mov r0, r5
800b8e4: 6013 str r3, [r2, #0]
800b8e6: b004 add sp, #16
800b8e8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800b8ec: f1b8 0f46 cmp.w r8, #70 @ 0x46
800b8f0: eb00 0904 add.w r9, r0, r4
800b8f4: d1e5 bne.n 800b8c2 <__cvt+0x6a>
800b8f6: 7803 ldrb r3, [r0, #0]
800b8f8: 2b30 cmp r3, #48 @ 0x30
800b8fa: d10a bne.n 800b912 <__cvt+0xba>
800b8fc: 2200 movs r2, #0
800b8fe: 2300 movs r3, #0
800b900: 4630 mov r0, r6
800b902: 4639 mov r1, r7
800b904: f7f5 f8e0 bl 8000ac8 <__aeabi_dcmpeq>
800b908: b918 cbnz r0, 800b912 <__cvt+0xba>
800b90a: f1c4 0401 rsb r4, r4, #1
800b90e: f8ca 4000 str.w r4, [sl]
800b912: f8da 3000 ldr.w r3, [sl]
800b916: 4499 add r9, r3
800b918: e7d3 b.n 800b8c2 <__cvt+0x6a>
800b91a: 1c59 adds r1, r3, #1
800b91c: 9103 str r1, [sp, #12]
800b91e: 701a strb r2, [r3, #0]
800b920: e7d9 b.n 800b8d6 <__cvt+0x7e>
0800b922 <__exponent>:
800b922: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
800b924: 2900 cmp r1, #0
800b926: bfba itte lt
800b928: 4249 neglt r1, r1
800b92a: 232d movlt r3, #45 @ 0x2d
800b92c: 232b movge r3, #43 @ 0x2b
800b92e: 2909 cmp r1, #9
800b930: 7002 strb r2, [r0, #0]
800b932: 7043 strb r3, [r0, #1]
800b934: dd29 ble.n 800b98a <__exponent+0x68>
800b936: f10d 0307 add.w r3, sp, #7
800b93a: 461d mov r5, r3
800b93c: 270a movs r7, #10
800b93e: 461a mov r2, r3
800b940: fbb1 f6f7 udiv r6, r1, r7
800b944: fb07 1416 mls r4, r7, r6, r1
800b948: 3430 adds r4, #48 @ 0x30
800b94a: f802 4c01 strb.w r4, [r2, #-1]
800b94e: 460c mov r4, r1
800b950: 2c63 cmp r4, #99 @ 0x63
800b952: f103 33ff add.w r3, r3, #4294967295
800b956: 4631 mov r1, r6
800b958: dcf1 bgt.n 800b93e <__exponent+0x1c>
800b95a: 3130 adds r1, #48 @ 0x30
800b95c: 1e94 subs r4, r2, #2
800b95e: f803 1c01 strb.w r1, [r3, #-1]
800b962: 1c41 adds r1, r0, #1
800b964: 4623 mov r3, r4
800b966: 42ab cmp r3, r5
800b968: d30a bcc.n 800b980 <__exponent+0x5e>
800b96a: f10d 0309 add.w r3, sp, #9
800b96e: 1a9b subs r3, r3, r2
800b970: 42ac cmp r4, r5
800b972: bf88 it hi
800b974: 2300 movhi r3, #0
800b976: 3302 adds r3, #2
800b978: 4403 add r3, r0
800b97a: 1a18 subs r0, r3, r0
800b97c: b003 add sp, #12
800b97e: bdf0 pop {r4, r5, r6, r7, pc}
800b980: f813 6b01 ldrb.w r6, [r3], #1
800b984: f801 6f01 strb.w r6, [r1, #1]!
800b988: e7ed b.n 800b966 <__exponent+0x44>
800b98a: 2330 movs r3, #48 @ 0x30
800b98c: 3130 adds r1, #48 @ 0x30
800b98e: 7083 strb r3, [r0, #2]
800b990: 70c1 strb r1, [r0, #3]
800b992: 1d03 adds r3, r0, #4
800b994: e7f1 b.n 800b97a <__exponent+0x58>
...
0800b998 <_printf_float>:
800b998: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800b99c: b08d sub sp, #52 @ 0x34
800b99e: 460c mov r4, r1
800b9a0: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
800b9a4: 4616 mov r6, r2
800b9a6: 461f mov r7, r3
800b9a8: 4605 mov r5, r0
800b9aa: f000 fcb9 bl 800c320 <_localeconv_r>
800b9ae: 6803 ldr r3, [r0, #0]
800b9b0: 9304 str r3, [sp, #16]
800b9b2: 4618 mov r0, r3
800b9b4: f7f4 fc5c bl 8000270 <strlen>
800b9b8: 2300 movs r3, #0
800b9ba: 930a str r3, [sp, #40] @ 0x28
800b9bc: f8d8 3000 ldr.w r3, [r8]
800b9c0: 9005 str r0, [sp, #20]
800b9c2: 3307 adds r3, #7
800b9c4: f023 0307 bic.w r3, r3, #7
800b9c8: f103 0208 add.w r2, r3, #8
800b9cc: f894 a018 ldrb.w sl, [r4, #24]
800b9d0: f8d4 b000 ldr.w fp, [r4]
800b9d4: f8c8 2000 str.w r2, [r8]
800b9d8: e9d3 8900 ldrd r8, r9, [r3]
800b9dc: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
800b9e0: 9307 str r3, [sp, #28]
800b9e2: f8cd 8018 str.w r8, [sp, #24]
800b9e6: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48
800b9ea: e9dd 0106 ldrd r0, r1, [sp, #24]
800b9ee: 4b9c ldr r3, [pc, #624] @ (800bc60 <_printf_float+0x2c8>)
800b9f0: f04f 32ff mov.w r2, #4294967295
800b9f4: f7f5 f89a bl 8000b2c <__aeabi_dcmpun>
800b9f8: bb70 cbnz r0, 800ba58 <_printf_float+0xc0>
800b9fa: e9dd 0106 ldrd r0, r1, [sp, #24]
800b9fe: 4b98 ldr r3, [pc, #608] @ (800bc60 <_printf_float+0x2c8>)
800ba00: f04f 32ff mov.w r2, #4294967295
800ba04: f7f5 f874 bl 8000af0 <__aeabi_dcmple>
800ba08: bb30 cbnz r0, 800ba58 <_printf_float+0xc0>
800ba0a: 2200 movs r2, #0
800ba0c: 2300 movs r3, #0
800ba0e: 4640 mov r0, r8
800ba10: 4649 mov r1, r9
800ba12: f7f5 f863 bl 8000adc <__aeabi_dcmplt>
800ba16: b110 cbz r0, 800ba1e <_printf_float+0x86>
800ba18: 232d movs r3, #45 @ 0x2d
800ba1a: f884 3043 strb.w r3, [r4, #67] @ 0x43
800ba1e: 4a91 ldr r2, [pc, #580] @ (800bc64 <_printf_float+0x2cc>)
800ba20: 4b91 ldr r3, [pc, #580] @ (800bc68 <_printf_float+0x2d0>)
800ba22: f1ba 0f47 cmp.w sl, #71 @ 0x47
800ba26: bf8c ite hi
800ba28: 4690 movhi r8, r2
800ba2a: 4698 movls r8, r3
800ba2c: 2303 movs r3, #3
800ba2e: 6123 str r3, [r4, #16]
800ba30: f02b 0304 bic.w r3, fp, #4
800ba34: 6023 str r3, [r4, #0]
800ba36: f04f 0900 mov.w r9, #0
800ba3a: 9700 str r7, [sp, #0]
800ba3c: 4633 mov r3, r6
800ba3e: aa0b add r2, sp, #44 @ 0x2c
800ba40: 4621 mov r1, r4
800ba42: 4628 mov r0, r5
800ba44: f000 f9d2 bl 800bdec <_printf_common>
800ba48: 3001 adds r0, #1
800ba4a: f040 808d bne.w 800bb68 <_printf_float+0x1d0>
800ba4e: f04f 30ff mov.w r0, #4294967295
800ba52: b00d add sp, #52 @ 0x34
800ba54: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800ba58: 4642 mov r2, r8
800ba5a: 464b mov r3, r9
800ba5c: 4640 mov r0, r8
800ba5e: 4649 mov r1, r9
800ba60: f7f5 f864 bl 8000b2c <__aeabi_dcmpun>
800ba64: b140 cbz r0, 800ba78 <_printf_float+0xe0>
800ba66: 464b mov r3, r9
800ba68: 2b00 cmp r3, #0
800ba6a: bfbc itt lt
800ba6c: 232d movlt r3, #45 @ 0x2d
800ba6e: f884 3043 strblt.w r3, [r4, #67] @ 0x43
800ba72: 4a7e ldr r2, [pc, #504] @ (800bc6c <_printf_float+0x2d4>)
800ba74: 4b7e ldr r3, [pc, #504] @ (800bc70 <_printf_float+0x2d8>)
800ba76: e7d4 b.n 800ba22 <_printf_float+0x8a>
800ba78: 6863 ldr r3, [r4, #4]
800ba7a: f00a 02df and.w r2, sl, #223 @ 0xdf
800ba7e: 9206 str r2, [sp, #24]
800ba80: 1c5a adds r2, r3, #1
800ba82: d13b bne.n 800bafc <_printf_float+0x164>
800ba84: 2306 movs r3, #6
800ba86: 6063 str r3, [r4, #4]
800ba88: f44b 6280 orr.w r2, fp, #1024 @ 0x400
800ba8c: 2300 movs r3, #0
800ba8e: 6022 str r2, [r4, #0]
800ba90: 9303 str r3, [sp, #12]
800ba92: ab0a add r3, sp, #40 @ 0x28
800ba94: e9cd a301 strd sl, r3, [sp, #4]
800ba98: ab09 add r3, sp, #36 @ 0x24
800ba9a: 9300 str r3, [sp, #0]
800ba9c: 6861 ldr r1, [r4, #4]
800ba9e: ec49 8b10 vmov d0, r8, r9
800baa2: f10d 0323 add.w r3, sp, #35 @ 0x23
800baa6: 4628 mov r0, r5
800baa8: f7ff fed6 bl 800b858 <__cvt>
800baac: 9b06 ldr r3, [sp, #24]
800baae: 9909 ldr r1, [sp, #36] @ 0x24
800bab0: 2b47 cmp r3, #71 @ 0x47
800bab2: 4680 mov r8, r0
800bab4: d129 bne.n 800bb0a <_printf_float+0x172>
800bab6: 1cc8 adds r0, r1, #3
800bab8: db02 blt.n 800bac0 <_printf_float+0x128>
800baba: 6863 ldr r3, [r4, #4]
800babc: 4299 cmp r1, r3
800babe: dd41 ble.n 800bb44 <_printf_float+0x1ac>
800bac0: f1aa 0a02 sub.w sl, sl, #2
800bac4: fa5f fa8a uxtb.w sl, sl
800bac8: 3901 subs r1, #1
800baca: 4652 mov r2, sl
800bacc: f104 0050 add.w r0, r4, #80 @ 0x50
800bad0: 9109 str r1, [sp, #36] @ 0x24
800bad2: f7ff ff26 bl 800b922 <__exponent>
800bad6: 9a0a ldr r2, [sp, #40] @ 0x28
800bad8: 1813 adds r3, r2, r0
800bada: 2a01 cmp r2, #1
800badc: 4681 mov r9, r0
800bade: 6123 str r3, [r4, #16]
800bae0: dc02 bgt.n 800bae8 <_printf_float+0x150>
800bae2: 6822 ldr r2, [r4, #0]
800bae4: 07d2 lsls r2, r2, #31
800bae6: d501 bpl.n 800baec <_printf_float+0x154>
800bae8: 3301 adds r3, #1
800baea: 6123 str r3, [r4, #16]
800baec: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
800baf0: 2b00 cmp r3, #0
800baf2: d0a2 beq.n 800ba3a <_printf_float+0xa2>
800baf4: 232d movs r3, #45 @ 0x2d
800baf6: f884 3043 strb.w r3, [r4, #67] @ 0x43
800bafa: e79e b.n 800ba3a <_printf_float+0xa2>
800bafc: 9a06 ldr r2, [sp, #24]
800bafe: 2a47 cmp r2, #71 @ 0x47
800bb00: d1c2 bne.n 800ba88 <_printf_float+0xf0>
800bb02: 2b00 cmp r3, #0
800bb04: d1c0 bne.n 800ba88 <_printf_float+0xf0>
800bb06: 2301 movs r3, #1
800bb08: e7bd b.n 800ba86 <_printf_float+0xee>
800bb0a: f1ba 0f65 cmp.w sl, #101 @ 0x65
800bb0e: d9db bls.n 800bac8 <_printf_float+0x130>
800bb10: f1ba 0f66 cmp.w sl, #102 @ 0x66
800bb14: d118 bne.n 800bb48 <_printf_float+0x1b0>
800bb16: 2900 cmp r1, #0
800bb18: 6863 ldr r3, [r4, #4]
800bb1a: dd0b ble.n 800bb34 <_printf_float+0x19c>
800bb1c: 6121 str r1, [r4, #16]
800bb1e: b913 cbnz r3, 800bb26 <_printf_float+0x18e>
800bb20: 6822 ldr r2, [r4, #0]
800bb22: 07d0 lsls r0, r2, #31
800bb24: d502 bpl.n 800bb2c <_printf_float+0x194>
800bb26: 3301 adds r3, #1
800bb28: 440b add r3, r1
800bb2a: 6123 str r3, [r4, #16]
800bb2c: 65a1 str r1, [r4, #88] @ 0x58
800bb2e: f04f 0900 mov.w r9, #0
800bb32: e7db b.n 800baec <_printf_float+0x154>
800bb34: b913 cbnz r3, 800bb3c <_printf_float+0x1a4>
800bb36: 6822 ldr r2, [r4, #0]
800bb38: 07d2 lsls r2, r2, #31
800bb3a: d501 bpl.n 800bb40 <_printf_float+0x1a8>
800bb3c: 3302 adds r3, #2
800bb3e: e7f4 b.n 800bb2a <_printf_float+0x192>
800bb40: 2301 movs r3, #1
800bb42: e7f2 b.n 800bb2a <_printf_float+0x192>
800bb44: f04f 0a67 mov.w sl, #103 @ 0x67
800bb48: 9b0a ldr r3, [sp, #40] @ 0x28
800bb4a: 4299 cmp r1, r3
800bb4c: db05 blt.n 800bb5a <_printf_float+0x1c2>
800bb4e: 6823 ldr r3, [r4, #0]
800bb50: 6121 str r1, [r4, #16]
800bb52: 07d8 lsls r0, r3, #31
800bb54: d5ea bpl.n 800bb2c <_printf_float+0x194>
800bb56: 1c4b adds r3, r1, #1
800bb58: e7e7 b.n 800bb2a <_printf_float+0x192>
800bb5a: 2900 cmp r1, #0
800bb5c: bfd4 ite le
800bb5e: f1c1 0202 rsble r2, r1, #2
800bb62: 2201 movgt r2, #1
800bb64: 4413 add r3, r2
800bb66: e7e0 b.n 800bb2a <_printf_float+0x192>
800bb68: 6823 ldr r3, [r4, #0]
800bb6a: 055a lsls r2, r3, #21
800bb6c: d407 bmi.n 800bb7e <_printf_float+0x1e6>
800bb6e: 6923 ldr r3, [r4, #16]
800bb70: 4642 mov r2, r8
800bb72: 4631 mov r1, r6
800bb74: 4628 mov r0, r5
800bb76: 47b8 blx r7
800bb78: 3001 adds r0, #1
800bb7a: d12b bne.n 800bbd4 <_printf_float+0x23c>
800bb7c: e767 b.n 800ba4e <_printf_float+0xb6>
800bb7e: f1ba 0f65 cmp.w sl, #101 @ 0x65
800bb82: f240 80dd bls.w 800bd40 <_printf_float+0x3a8>
800bb86: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
800bb8a: 2200 movs r2, #0
800bb8c: 2300 movs r3, #0
800bb8e: f7f4 ff9b bl 8000ac8 <__aeabi_dcmpeq>
800bb92: 2800 cmp r0, #0
800bb94: d033 beq.n 800bbfe <_printf_float+0x266>
800bb96: 4a37 ldr r2, [pc, #220] @ (800bc74 <_printf_float+0x2dc>)
800bb98: 2301 movs r3, #1
800bb9a: 4631 mov r1, r6
800bb9c: 4628 mov r0, r5
800bb9e: 47b8 blx r7
800bba0: 3001 adds r0, #1
800bba2: f43f af54 beq.w 800ba4e <_printf_float+0xb6>
800bba6: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
800bbaa: 4543 cmp r3, r8
800bbac: db02 blt.n 800bbb4 <_printf_float+0x21c>
800bbae: 6823 ldr r3, [r4, #0]
800bbb0: 07d8 lsls r0, r3, #31
800bbb2: d50f bpl.n 800bbd4 <_printf_float+0x23c>
800bbb4: e9dd 2304 ldrd r2, r3, [sp, #16]
800bbb8: 4631 mov r1, r6
800bbba: 4628 mov r0, r5
800bbbc: 47b8 blx r7
800bbbe: 3001 adds r0, #1
800bbc0: f43f af45 beq.w 800ba4e <_printf_float+0xb6>
800bbc4: f04f 0900 mov.w r9, #0
800bbc8: f108 38ff add.w r8, r8, #4294967295
800bbcc: f104 0a1a add.w sl, r4, #26
800bbd0: 45c8 cmp r8, r9
800bbd2: dc09 bgt.n 800bbe8 <_printf_float+0x250>
800bbd4: 6823 ldr r3, [r4, #0]
800bbd6: 079b lsls r3, r3, #30
800bbd8: f100 8103 bmi.w 800bde2 <_printf_float+0x44a>
800bbdc: 68e0 ldr r0, [r4, #12]
800bbde: 9b0b ldr r3, [sp, #44] @ 0x2c
800bbe0: 4298 cmp r0, r3
800bbe2: bfb8 it lt
800bbe4: 4618 movlt r0, r3
800bbe6: e734 b.n 800ba52 <_printf_float+0xba>
800bbe8: 2301 movs r3, #1
800bbea: 4652 mov r2, sl
800bbec: 4631 mov r1, r6
800bbee: 4628 mov r0, r5
800bbf0: 47b8 blx r7
800bbf2: 3001 adds r0, #1
800bbf4: f43f af2b beq.w 800ba4e <_printf_float+0xb6>
800bbf8: f109 0901 add.w r9, r9, #1
800bbfc: e7e8 b.n 800bbd0 <_printf_float+0x238>
800bbfe: 9b09 ldr r3, [sp, #36] @ 0x24
800bc00: 2b00 cmp r3, #0
800bc02: dc39 bgt.n 800bc78 <_printf_float+0x2e0>
800bc04: 4a1b ldr r2, [pc, #108] @ (800bc74 <_printf_float+0x2dc>)
800bc06: 2301 movs r3, #1
800bc08: 4631 mov r1, r6
800bc0a: 4628 mov r0, r5
800bc0c: 47b8 blx r7
800bc0e: 3001 adds r0, #1
800bc10: f43f af1d beq.w 800ba4e <_printf_float+0xb6>
800bc14: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
800bc18: ea59 0303 orrs.w r3, r9, r3
800bc1c: d102 bne.n 800bc24 <_printf_float+0x28c>
800bc1e: 6823 ldr r3, [r4, #0]
800bc20: 07d9 lsls r1, r3, #31
800bc22: d5d7 bpl.n 800bbd4 <_printf_float+0x23c>
800bc24: e9dd 2304 ldrd r2, r3, [sp, #16]
800bc28: 4631 mov r1, r6
800bc2a: 4628 mov r0, r5
800bc2c: 47b8 blx r7
800bc2e: 3001 adds r0, #1
800bc30: f43f af0d beq.w 800ba4e <_printf_float+0xb6>
800bc34: f04f 0a00 mov.w sl, #0
800bc38: f104 0b1a add.w fp, r4, #26
800bc3c: 9b09 ldr r3, [sp, #36] @ 0x24
800bc3e: 425b negs r3, r3
800bc40: 4553 cmp r3, sl
800bc42: dc01 bgt.n 800bc48 <_printf_float+0x2b0>
800bc44: 464b mov r3, r9
800bc46: e793 b.n 800bb70 <_printf_float+0x1d8>
800bc48: 2301 movs r3, #1
800bc4a: 465a mov r2, fp
800bc4c: 4631 mov r1, r6
800bc4e: 4628 mov r0, r5
800bc50: 47b8 blx r7
800bc52: 3001 adds r0, #1
800bc54: f43f aefb beq.w 800ba4e <_printf_float+0xb6>
800bc58: f10a 0a01 add.w sl, sl, #1
800bc5c: e7ee b.n 800bc3c <_printf_float+0x2a4>
800bc5e: bf00 nop
800bc60: 7fefffff .word 0x7fefffff
800bc64: 0800e20c .word 0x0800e20c
800bc68: 0800e208 .word 0x0800e208
800bc6c: 0800e214 .word 0x0800e214
800bc70: 0800e210 .word 0x0800e210
800bc74: 0800e218 .word 0x0800e218
800bc78: 6da3 ldr r3, [r4, #88] @ 0x58
800bc7a: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
800bc7e: 4553 cmp r3, sl
800bc80: bfa8 it ge
800bc82: 4653 movge r3, sl
800bc84: 2b00 cmp r3, #0
800bc86: 4699 mov r9, r3
800bc88: dc36 bgt.n 800bcf8 <_printf_float+0x360>
800bc8a: f04f 0b00 mov.w fp, #0
800bc8e: ea29 79e9 bic.w r9, r9, r9, asr #31
800bc92: f104 021a add.w r2, r4, #26
800bc96: 6da3 ldr r3, [r4, #88] @ 0x58
800bc98: 9306 str r3, [sp, #24]
800bc9a: eba3 0309 sub.w r3, r3, r9
800bc9e: 455b cmp r3, fp
800bca0: dc31 bgt.n 800bd06 <_printf_float+0x36e>
800bca2: 9b09 ldr r3, [sp, #36] @ 0x24
800bca4: 459a cmp sl, r3
800bca6: dc3a bgt.n 800bd1e <_printf_float+0x386>
800bca8: 6823 ldr r3, [r4, #0]
800bcaa: 07da lsls r2, r3, #31
800bcac: d437 bmi.n 800bd1e <_printf_float+0x386>
800bcae: 9b09 ldr r3, [sp, #36] @ 0x24
800bcb0: ebaa 0903 sub.w r9, sl, r3
800bcb4: 9b06 ldr r3, [sp, #24]
800bcb6: ebaa 0303 sub.w r3, sl, r3
800bcba: 4599 cmp r9, r3
800bcbc: bfa8 it ge
800bcbe: 4699 movge r9, r3
800bcc0: f1b9 0f00 cmp.w r9, #0
800bcc4: dc33 bgt.n 800bd2e <_printf_float+0x396>
800bcc6: f04f 0800 mov.w r8, #0
800bcca: ea29 79e9 bic.w r9, r9, r9, asr #31
800bcce: f104 0b1a add.w fp, r4, #26
800bcd2: 9b09 ldr r3, [sp, #36] @ 0x24
800bcd4: ebaa 0303 sub.w r3, sl, r3
800bcd8: eba3 0309 sub.w r3, r3, r9
800bcdc: 4543 cmp r3, r8
800bcde: f77f af79 ble.w 800bbd4 <_printf_float+0x23c>
800bce2: 2301 movs r3, #1
800bce4: 465a mov r2, fp
800bce6: 4631 mov r1, r6
800bce8: 4628 mov r0, r5
800bcea: 47b8 blx r7
800bcec: 3001 adds r0, #1
800bcee: f43f aeae beq.w 800ba4e <_printf_float+0xb6>
800bcf2: f108 0801 add.w r8, r8, #1
800bcf6: e7ec b.n 800bcd2 <_printf_float+0x33a>
800bcf8: 4642 mov r2, r8
800bcfa: 4631 mov r1, r6
800bcfc: 4628 mov r0, r5
800bcfe: 47b8 blx r7
800bd00: 3001 adds r0, #1
800bd02: d1c2 bne.n 800bc8a <_printf_float+0x2f2>
800bd04: e6a3 b.n 800ba4e <_printf_float+0xb6>
800bd06: 2301 movs r3, #1
800bd08: 4631 mov r1, r6
800bd0a: 4628 mov r0, r5
800bd0c: 9206 str r2, [sp, #24]
800bd0e: 47b8 blx r7
800bd10: 3001 adds r0, #1
800bd12: f43f ae9c beq.w 800ba4e <_printf_float+0xb6>
800bd16: 9a06 ldr r2, [sp, #24]
800bd18: f10b 0b01 add.w fp, fp, #1
800bd1c: e7bb b.n 800bc96 <_printf_float+0x2fe>
800bd1e: e9dd 2304 ldrd r2, r3, [sp, #16]
800bd22: 4631 mov r1, r6
800bd24: 4628 mov r0, r5
800bd26: 47b8 blx r7
800bd28: 3001 adds r0, #1
800bd2a: d1c0 bne.n 800bcae <_printf_float+0x316>
800bd2c: e68f b.n 800ba4e <_printf_float+0xb6>
800bd2e: 9a06 ldr r2, [sp, #24]
800bd30: 464b mov r3, r9
800bd32: 4442 add r2, r8
800bd34: 4631 mov r1, r6
800bd36: 4628 mov r0, r5
800bd38: 47b8 blx r7
800bd3a: 3001 adds r0, #1
800bd3c: d1c3 bne.n 800bcc6 <_printf_float+0x32e>
800bd3e: e686 b.n 800ba4e <_printf_float+0xb6>
800bd40: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
800bd44: f1ba 0f01 cmp.w sl, #1
800bd48: dc01 bgt.n 800bd4e <_printf_float+0x3b6>
800bd4a: 07db lsls r3, r3, #31
800bd4c: d536 bpl.n 800bdbc <_printf_float+0x424>
800bd4e: 2301 movs r3, #1
800bd50: 4642 mov r2, r8
800bd52: 4631 mov r1, r6
800bd54: 4628 mov r0, r5
800bd56: 47b8 blx r7
800bd58: 3001 adds r0, #1
800bd5a: f43f ae78 beq.w 800ba4e <_printf_float+0xb6>
800bd5e: e9dd 2304 ldrd r2, r3, [sp, #16]
800bd62: 4631 mov r1, r6
800bd64: 4628 mov r0, r5
800bd66: 47b8 blx r7
800bd68: 3001 adds r0, #1
800bd6a: f43f ae70 beq.w 800ba4e <_printf_float+0xb6>
800bd6e: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
800bd72: 2200 movs r2, #0
800bd74: 2300 movs r3, #0
800bd76: f10a 3aff add.w sl, sl, #4294967295
800bd7a: f7f4 fea5 bl 8000ac8 <__aeabi_dcmpeq>
800bd7e: b9c0 cbnz r0, 800bdb2 <_printf_float+0x41a>
800bd80: 4653 mov r3, sl
800bd82: f108 0201 add.w r2, r8, #1
800bd86: 4631 mov r1, r6
800bd88: 4628 mov r0, r5
800bd8a: 47b8 blx r7
800bd8c: 3001 adds r0, #1
800bd8e: d10c bne.n 800bdaa <_printf_float+0x412>
800bd90: e65d b.n 800ba4e <_printf_float+0xb6>
800bd92: 2301 movs r3, #1
800bd94: 465a mov r2, fp
800bd96: 4631 mov r1, r6
800bd98: 4628 mov r0, r5
800bd9a: 47b8 blx r7
800bd9c: 3001 adds r0, #1
800bd9e: f43f ae56 beq.w 800ba4e <_printf_float+0xb6>
800bda2: f108 0801 add.w r8, r8, #1
800bda6: 45d0 cmp r8, sl
800bda8: dbf3 blt.n 800bd92 <_printf_float+0x3fa>
800bdaa: 464b mov r3, r9
800bdac: f104 0250 add.w r2, r4, #80 @ 0x50
800bdb0: e6df b.n 800bb72 <_printf_float+0x1da>
800bdb2: f04f 0800 mov.w r8, #0
800bdb6: f104 0b1a add.w fp, r4, #26
800bdba: e7f4 b.n 800bda6 <_printf_float+0x40e>
800bdbc: 2301 movs r3, #1
800bdbe: 4642 mov r2, r8
800bdc0: e7e1 b.n 800bd86 <_printf_float+0x3ee>
800bdc2: 2301 movs r3, #1
800bdc4: 464a mov r2, r9
800bdc6: 4631 mov r1, r6
800bdc8: 4628 mov r0, r5
800bdca: 47b8 blx r7
800bdcc: 3001 adds r0, #1
800bdce: f43f ae3e beq.w 800ba4e <_printf_float+0xb6>
800bdd2: f108 0801 add.w r8, r8, #1
800bdd6: 68e3 ldr r3, [r4, #12]
800bdd8: 990b ldr r1, [sp, #44] @ 0x2c
800bdda: 1a5b subs r3, r3, r1
800bddc: 4543 cmp r3, r8
800bdde: dcf0 bgt.n 800bdc2 <_printf_float+0x42a>
800bde0: e6fc b.n 800bbdc <_printf_float+0x244>
800bde2: f04f 0800 mov.w r8, #0
800bde6: f104 0919 add.w r9, r4, #25
800bdea: e7f4 b.n 800bdd6 <_printf_float+0x43e>
0800bdec <_printf_common>:
800bdec: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800bdf0: 4616 mov r6, r2
800bdf2: 4698 mov r8, r3
800bdf4: 688a ldr r2, [r1, #8]
800bdf6: 690b ldr r3, [r1, #16]
800bdf8: f8dd 9020 ldr.w r9, [sp, #32]
800bdfc: 4293 cmp r3, r2
800bdfe: bfb8 it lt
800be00: 4613 movlt r3, r2
800be02: 6033 str r3, [r6, #0]
800be04: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
800be08: 4607 mov r7, r0
800be0a: 460c mov r4, r1
800be0c: b10a cbz r2, 800be12 <_printf_common+0x26>
800be0e: 3301 adds r3, #1
800be10: 6033 str r3, [r6, #0]
800be12: 6823 ldr r3, [r4, #0]
800be14: 0699 lsls r1, r3, #26
800be16: bf42 ittt mi
800be18: 6833 ldrmi r3, [r6, #0]
800be1a: 3302 addmi r3, #2
800be1c: 6033 strmi r3, [r6, #0]
800be1e: 6825 ldr r5, [r4, #0]
800be20: f015 0506 ands.w r5, r5, #6
800be24: d106 bne.n 800be34 <_printf_common+0x48>
800be26: f104 0a19 add.w sl, r4, #25
800be2a: 68e3 ldr r3, [r4, #12]
800be2c: 6832 ldr r2, [r6, #0]
800be2e: 1a9b subs r3, r3, r2
800be30: 42ab cmp r3, r5
800be32: dc26 bgt.n 800be82 <_printf_common+0x96>
800be34: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
800be38: 6822 ldr r2, [r4, #0]
800be3a: 3b00 subs r3, #0
800be3c: bf18 it ne
800be3e: 2301 movne r3, #1
800be40: 0692 lsls r2, r2, #26
800be42: d42b bmi.n 800be9c <_printf_common+0xb0>
800be44: f104 0243 add.w r2, r4, #67 @ 0x43
800be48: 4641 mov r1, r8
800be4a: 4638 mov r0, r7
800be4c: 47c8 blx r9
800be4e: 3001 adds r0, #1
800be50: d01e beq.n 800be90 <_printf_common+0xa4>
800be52: 6823 ldr r3, [r4, #0]
800be54: 6922 ldr r2, [r4, #16]
800be56: f003 0306 and.w r3, r3, #6
800be5a: 2b04 cmp r3, #4
800be5c: bf02 ittt eq
800be5e: 68e5 ldreq r5, [r4, #12]
800be60: 6833 ldreq r3, [r6, #0]
800be62: 1aed subeq r5, r5, r3
800be64: 68a3 ldr r3, [r4, #8]
800be66: bf0c ite eq
800be68: ea25 75e5 biceq.w r5, r5, r5, asr #31
800be6c: 2500 movne r5, #0
800be6e: 4293 cmp r3, r2
800be70: bfc4 itt gt
800be72: 1a9b subgt r3, r3, r2
800be74: 18ed addgt r5, r5, r3
800be76: 2600 movs r6, #0
800be78: 341a adds r4, #26
800be7a: 42b5 cmp r5, r6
800be7c: d11a bne.n 800beb4 <_printf_common+0xc8>
800be7e: 2000 movs r0, #0
800be80: e008 b.n 800be94 <_printf_common+0xa8>
800be82: 2301 movs r3, #1
800be84: 4652 mov r2, sl
800be86: 4641 mov r1, r8
800be88: 4638 mov r0, r7
800be8a: 47c8 blx r9
800be8c: 3001 adds r0, #1
800be8e: d103 bne.n 800be98 <_printf_common+0xac>
800be90: f04f 30ff mov.w r0, #4294967295
800be94: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800be98: 3501 adds r5, #1
800be9a: e7c6 b.n 800be2a <_printf_common+0x3e>
800be9c: 18e1 adds r1, r4, r3
800be9e: 1c5a adds r2, r3, #1
800bea0: 2030 movs r0, #48 @ 0x30
800bea2: f881 0043 strb.w r0, [r1, #67] @ 0x43
800bea6: 4422 add r2, r4
800bea8: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
800beac: f882 1043 strb.w r1, [r2, #67] @ 0x43
800beb0: 3302 adds r3, #2
800beb2: e7c7 b.n 800be44 <_printf_common+0x58>
800beb4: 2301 movs r3, #1
800beb6: 4622 mov r2, r4
800beb8: 4641 mov r1, r8
800beba: 4638 mov r0, r7
800bebc: 47c8 blx r9
800bebe: 3001 adds r0, #1
800bec0: d0e6 beq.n 800be90 <_printf_common+0xa4>
800bec2: 3601 adds r6, #1
800bec4: e7d9 b.n 800be7a <_printf_common+0x8e>
...
0800bec8 <_printf_i>:
800bec8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
800becc: 7e0f ldrb r7, [r1, #24]
800bece: 9e0c ldr r6, [sp, #48] @ 0x30
800bed0: 2f78 cmp r7, #120 @ 0x78
800bed2: 4691 mov r9, r2
800bed4: 4680 mov r8, r0
800bed6: 460c mov r4, r1
800bed8: 469a mov sl, r3
800beda: f101 0243 add.w r2, r1, #67 @ 0x43
800bede: d807 bhi.n 800bef0 <_printf_i+0x28>
800bee0: 2f62 cmp r7, #98 @ 0x62
800bee2: d80a bhi.n 800befa <_printf_i+0x32>
800bee4: 2f00 cmp r7, #0
800bee6: f000 80d1 beq.w 800c08c <_printf_i+0x1c4>
800beea: 2f58 cmp r7, #88 @ 0x58
800beec: f000 80b8 beq.w 800c060 <_printf_i+0x198>
800bef0: f104 0642 add.w r6, r4, #66 @ 0x42
800bef4: f884 7042 strb.w r7, [r4, #66] @ 0x42
800bef8: e03a b.n 800bf70 <_printf_i+0xa8>
800befa: f1a7 0363 sub.w r3, r7, #99 @ 0x63
800befe: 2b15 cmp r3, #21
800bf00: d8f6 bhi.n 800bef0 <_printf_i+0x28>
800bf02: a101 add r1, pc, #4 @ (adr r1, 800bf08 <_printf_i+0x40>)
800bf04: f851 f023 ldr.w pc, [r1, r3, lsl #2]
800bf08: 0800bf61 .word 0x0800bf61
800bf0c: 0800bf75 .word 0x0800bf75
800bf10: 0800bef1 .word 0x0800bef1
800bf14: 0800bef1 .word 0x0800bef1
800bf18: 0800bef1 .word 0x0800bef1
800bf1c: 0800bef1 .word 0x0800bef1
800bf20: 0800bf75 .word 0x0800bf75
800bf24: 0800bef1 .word 0x0800bef1
800bf28: 0800bef1 .word 0x0800bef1
800bf2c: 0800bef1 .word 0x0800bef1
800bf30: 0800bef1 .word 0x0800bef1
800bf34: 0800c073 .word 0x0800c073
800bf38: 0800bf9f .word 0x0800bf9f
800bf3c: 0800c02d .word 0x0800c02d
800bf40: 0800bef1 .word 0x0800bef1
800bf44: 0800bef1 .word 0x0800bef1
800bf48: 0800c095 .word 0x0800c095
800bf4c: 0800bef1 .word 0x0800bef1
800bf50: 0800bf9f .word 0x0800bf9f
800bf54: 0800bef1 .word 0x0800bef1
800bf58: 0800bef1 .word 0x0800bef1
800bf5c: 0800c035 .word 0x0800c035
800bf60: 6833 ldr r3, [r6, #0]
800bf62: 1d1a adds r2, r3, #4
800bf64: 681b ldr r3, [r3, #0]
800bf66: 6032 str r2, [r6, #0]
800bf68: f104 0642 add.w r6, r4, #66 @ 0x42
800bf6c: f884 3042 strb.w r3, [r4, #66] @ 0x42
800bf70: 2301 movs r3, #1
800bf72: e09c b.n 800c0ae <_printf_i+0x1e6>
800bf74: 6833 ldr r3, [r6, #0]
800bf76: 6820 ldr r0, [r4, #0]
800bf78: 1d19 adds r1, r3, #4
800bf7a: 6031 str r1, [r6, #0]
800bf7c: 0606 lsls r6, r0, #24
800bf7e: d501 bpl.n 800bf84 <_printf_i+0xbc>
800bf80: 681d ldr r5, [r3, #0]
800bf82: e003 b.n 800bf8c <_printf_i+0xc4>
800bf84: 0645 lsls r5, r0, #25
800bf86: d5fb bpl.n 800bf80 <_printf_i+0xb8>
800bf88: f9b3 5000 ldrsh.w r5, [r3]
800bf8c: 2d00 cmp r5, #0
800bf8e: da03 bge.n 800bf98 <_printf_i+0xd0>
800bf90: 232d movs r3, #45 @ 0x2d
800bf92: 426d negs r5, r5
800bf94: f884 3043 strb.w r3, [r4, #67] @ 0x43
800bf98: 4858 ldr r0, [pc, #352] @ (800c0fc <_printf_i+0x234>)
800bf9a: 230a movs r3, #10
800bf9c: e011 b.n 800bfc2 <_printf_i+0xfa>
800bf9e: 6821 ldr r1, [r4, #0]
800bfa0: 6833 ldr r3, [r6, #0]
800bfa2: 0608 lsls r0, r1, #24
800bfa4: f853 5b04 ldr.w r5, [r3], #4
800bfa8: d402 bmi.n 800bfb0 <_printf_i+0xe8>
800bfaa: 0649 lsls r1, r1, #25
800bfac: bf48 it mi
800bfae: b2ad uxthmi r5, r5
800bfb0: 2f6f cmp r7, #111 @ 0x6f
800bfb2: 4852 ldr r0, [pc, #328] @ (800c0fc <_printf_i+0x234>)
800bfb4: 6033 str r3, [r6, #0]
800bfb6: bf14 ite ne
800bfb8: 230a movne r3, #10
800bfba: 2308 moveq r3, #8
800bfbc: 2100 movs r1, #0
800bfbe: f884 1043 strb.w r1, [r4, #67] @ 0x43
800bfc2: 6866 ldr r6, [r4, #4]
800bfc4: 60a6 str r6, [r4, #8]
800bfc6: 2e00 cmp r6, #0
800bfc8: db05 blt.n 800bfd6 <_printf_i+0x10e>
800bfca: 6821 ldr r1, [r4, #0]
800bfcc: 432e orrs r6, r5
800bfce: f021 0104 bic.w r1, r1, #4
800bfd2: 6021 str r1, [r4, #0]
800bfd4: d04b beq.n 800c06e <_printf_i+0x1a6>
800bfd6: 4616 mov r6, r2
800bfd8: fbb5 f1f3 udiv r1, r5, r3
800bfdc: fb03 5711 mls r7, r3, r1, r5
800bfe0: 5dc7 ldrb r7, [r0, r7]
800bfe2: f806 7d01 strb.w r7, [r6, #-1]!
800bfe6: 462f mov r7, r5
800bfe8: 42bb cmp r3, r7
800bfea: 460d mov r5, r1
800bfec: d9f4 bls.n 800bfd8 <_printf_i+0x110>
800bfee: 2b08 cmp r3, #8
800bff0: d10b bne.n 800c00a <_printf_i+0x142>
800bff2: 6823 ldr r3, [r4, #0]
800bff4: 07df lsls r7, r3, #31
800bff6: d508 bpl.n 800c00a <_printf_i+0x142>
800bff8: 6923 ldr r3, [r4, #16]
800bffa: 6861 ldr r1, [r4, #4]
800bffc: 4299 cmp r1, r3
800bffe: bfde ittt le
800c000: 2330 movle r3, #48 @ 0x30
800c002: f806 3c01 strble.w r3, [r6, #-1]
800c006: f106 36ff addle.w r6, r6, #4294967295
800c00a: 1b92 subs r2, r2, r6
800c00c: 6122 str r2, [r4, #16]
800c00e: f8cd a000 str.w sl, [sp]
800c012: 464b mov r3, r9
800c014: aa03 add r2, sp, #12
800c016: 4621 mov r1, r4
800c018: 4640 mov r0, r8
800c01a: f7ff fee7 bl 800bdec <_printf_common>
800c01e: 3001 adds r0, #1
800c020: d14a bne.n 800c0b8 <_printf_i+0x1f0>
800c022: f04f 30ff mov.w r0, #4294967295
800c026: b004 add sp, #16
800c028: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800c02c: 6823 ldr r3, [r4, #0]
800c02e: f043 0320 orr.w r3, r3, #32
800c032: 6023 str r3, [r4, #0]
800c034: 4832 ldr r0, [pc, #200] @ (800c100 <_printf_i+0x238>)
800c036: 2778 movs r7, #120 @ 0x78
800c038: f884 7045 strb.w r7, [r4, #69] @ 0x45
800c03c: 6823 ldr r3, [r4, #0]
800c03e: 6831 ldr r1, [r6, #0]
800c040: 061f lsls r7, r3, #24
800c042: f851 5b04 ldr.w r5, [r1], #4
800c046: d402 bmi.n 800c04e <_printf_i+0x186>
800c048: 065f lsls r7, r3, #25
800c04a: bf48 it mi
800c04c: b2ad uxthmi r5, r5
800c04e: 6031 str r1, [r6, #0]
800c050: 07d9 lsls r1, r3, #31
800c052: bf44 itt mi
800c054: f043 0320 orrmi.w r3, r3, #32
800c058: 6023 strmi r3, [r4, #0]
800c05a: b11d cbz r5, 800c064 <_printf_i+0x19c>
800c05c: 2310 movs r3, #16
800c05e: e7ad b.n 800bfbc <_printf_i+0xf4>
800c060: 4826 ldr r0, [pc, #152] @ (800c0fc <_printf_i+0x234>)
800c062: e7e9 b.n 800c038 <_printf_i+0x170>
800c064: 6823 ldr r3, [r4, #0]
800c066: f023 0320 bic.w r3, r3, #32
800c06a: 6023 str r3, [r4, #0]
800c06c: e7f6 b.n 800c05c <_printf_i+0x194>
800c06e: 4616 mov r6, r2
800c070: e7bd b.n 800bfee <_printf_i+0x126>
800c072: 6833 ldr r3, [r6, #0]
800c074: 6825 ldr r5, [r4, #0]
800c076: 6961 ldr r1, [r4, #20]
800c078: 1d18 adds r0, r3, #4
800c07a: 6030 str r0, [r6, #0]
800c07c: 062e lsls r6, r5, #24
800c07e: 681b ldr r3, [r3, #0]
800c080: d501 bpl.n 800c086 <_printf_i+0x1be>
800c082: 6019 str r1, [r3, #0]
800c084: e002 b.n 800c08c <_printf_i+0x1c4>
800c086: 0668 lsls r0, r5, #25
800c088: d5fb bpl.n 800c082 <_printf_i+0x1ba>
800c08a: 8019 strh r1, [r3, #0]
800c08c: 2300 movs r3, #0
800c08e: 6123 str r3, [r4, #16]
800c090: 4616 mov r6, r2
800c092: e7bc b.n 800c00e <_printf_i+0x146>
800c094: 6833 ldr r3, [r6, #0]
800c096: 1d1a adds r2, r3, #4
800c098: 6032 str r2, [r6, #0]
800c09a: 681e ldr r6, [r3, #0]
800c09c: 6862 ldr r2, [r4, #4]
800c09e: 2100 movs r1, #0
800c0a0: 4630 mov r0, r6
800c0a2: f7f4 f895 bl 80001d0 <memchr>
800c0a6: b108 cbz r0, 800c0ac <_printf_i+0x1e4>
800c0a8: 1b80 subs r0, r0, r6
800c0aa: 6060 str r0, [r4, #4]
800c0ac: 6863 ldr r3, [r4, #4]
800c0ae: 6123 str r3, [r4, #16]
800c0b0: 2300 movs r3, #0
800c0b2: f884 3043 strb.w r3, [r4, #67] @ 0x43
800c0b6: e7aa b.n 800c00e <_printf_i+0x146>
800c0b8: 6923 ldr r3, [r4, #16]
800c0ba: 4632 mov r2, r6
800c0bc: 4649 mov r1, r9
800c0be: 4640 mov r0, r8
800c0c0: 47d0 blx sl
800c0c2: 3001 adds r0, #1
800c0c4: d0ad beq.n 800c022 <_printf_i+0x15a>
800c0c6: 6823 ldr r3, [r4, #0]
800c0c8: 079b lsls r3, r3, #30
800c0ca: d413 bmi.n 800c0f4 <_printf_i+0x22c>
800c0cc: 68e0 ldr r0, [r4, #12]
800c0ce: 9b03 ldr r3, [sp, #12]
800c0d0: 4298 cmp r0, r3
800c0d2: bfb8 it lt
800c0d4: 4618 movlt r0, r3
800c0d6: e7a6 b.n 800c026 <_printf_i+0x15e>
800c0d8: 2301 movs r3, #1
800c0da: 4632 mov r2, r6
800c0dc: 4649 mov r1, r9
800c0de: 4640 mov r0, r8
800c0e0: 47d0 blx sl
800c0e2: 3001 adds r0, #1
800c0e4: d09d beq.n 800c022 <_printf_i+0x15a>
800c0e6: 3501 adds r5, #1
800c0e8: 68e3 ldr r3, [r4, #12]
800c0ea: 9903 ldr r1, [sp, #12]
800c0ec: 1a5b subs r3, r3, r1
800c0ee: 42ab cmp r3, r5
800c0f0: dcf2 bgt.n 800c0d8 <_printf_i+0x210>
800c0f2: e7eb b.n 800c0cc <_printf_i+0x204>
800c0f4: 2500 movs r5, #0
800c0f6: f104 0619 add.w r6, r4, #25
800c0fa: e7f5 b.n 800c0e8 <_printf_i+0x220>
800c0fc: 0800e21a .word 0x0800e21a
800c100: 0800e22b .word 0x0800e22b
0800c104 <std>:
800c104: 2300 movs r3, #0
800c106: b510 push {r4, lr}
800c108: 4604 mov r4, r0
800c10a: e9c0 3300 strd r3, r3, [r0]
800c10e: e9c0 3304 strd r3, r3, [r0, #16]
800c112: 6083 str r3, [r0, #8]
800c114: 8181 strh r1, [r0, #12]
800c116: 6643 str r3, [r0, #100] @ 0x64
800c118: 81c2 strh r2, [r0, #14]
800c11a: 6183 str r3, [r0, #24]
800c11c: 4619 mov r1, r3
800c11e: 2208 movs r2, #8
800c120: 305c adds r0, #92 @ 0x5c
800c122: f000 f8f4 bl 800c30e <memset>
800c126: 4b0d ldr r3, [pc, #52] @ (800c15c <std+0x58>)
800c128: 6263 str r3, [r4, #36] @ 0x24
800c12a: 4b0d ldr r3, [pc, #52] @ (800c160 <std+0x5c>)
800c12c: 62a3 str r3, [r4, #40] @ 0x28
800c12e: 4b0d ldr r3, [pc, #52] @ (800c164 <std+0x60>)
800c130: 62e3 str r3, [r4, #44] @ 0x2c
800c132: 4b0d ldr r3, [pc, #52] @ (800c168 <std+0x64>)
800c134: 6323 str r3, [r4, #48] @ 0x30
800c136: 4b0d ldr r3, [pc, #52] @ (800c16c <std+0x68>)
800c138: 6224 str r4, [r4, #32]
800c13a: 429c cmp r4, r3
800c13c: d006 beq.n 800c14c <std+0x48>
800c13e: f103 0268 add.w r2, r3, #104 @ 0x68
800c142: 4294 cmp r4, r2
800c144: d002 beq.n 800c14c <std+0x48>
800c146: 33d0 adds r3, #208 @ 0xd0
800c148: 429c cmp r4, r3
800c14a: d105 bne.n 800c158 <std+0x54>
800c14c: f104 0058 add.w r0, r4, #88 @ 0x58
800c150: e8bd 4010 ldmia.w sp!, {r4, lr}
800c154: f000 b958 b.w 800c408 <__retarget_lock_init_recursive>
800c158: bd10 pop {r4, pc}
800c15a: bf00 nop
800c15c: 0800c289 .word 0x0800c289
800c160: 0800c2ab .word 0x0800c2ab
800c164: 0800c2e3 .word 0x0800c2e3
800c168: 0800c307 .word 0x0800c307
800c16c: 200010a4 .word 0x200010a4
0800c170 <stdio_exit_handler>:
800c170: 4a02 ldr r2, [pc, #8] @ (800c17c <stdio_exit_handler+0xc>)
800c172: 4903 ldr r1, [pc, #12] @ (800c180 <stdio_exit_handler+0x10>)
800c174: 4803 ldr r0, [pc, #12] @ (800c184 <stdio_exit_handler+0x14>)
800c176: f000 b869 b.w 800c24c <_fwalk_sglue>
800c17a: bf00 nop
800c17c: 20000138 .word 0x20000138
800c180: 0800dabd .word 0x0800dabd
800c184: 20000148 .word 0x20000148
0800c188 <cleanup_stdio>:
800c188: 6841 ldr r1, [r0, #4]
800c18a: 4b0c ldr r3, [pc, #48] @ (800c1bc <cleanup_stdio+0x34>)
800c18c: 4299 cmp r1, r3
800c18e: b510 push {r4, lr}
800c190: 4604 mov r4, r0
800c192: d001 beq.n 800c198 <cleanup_stdio+0x10>
800c194: f001 fc92 bl 800dabc <_fflush_r>
800c198: 68a1 ldr r1, [r4, #8]
800c19a: 4b09 ldr r3, [pc, #36] @ (800c1c0 <cleanup_stdio+0x38>)
800c19c: 4299 cmp r1, r3
800c19e: d002 beq.n 800c1a6 <cleanup_stdio+0x1e>
800c1a0: 4620 mov r0, r4
800c1a2: f001 fc8b bl 800dabc <_fflush_r>
800c1a6: 68e1 ldr r1, [r4, #12]
800c1a8: 4b06 ldr r3, [pc, #24] @ (800c1c4 <cleanup_stdio+0x3c>)
800c1aa: 4299 cmp r1, r3
800c1ac: d004 beq.n 800c1b8 <cleanup_stdio+0x30>
800c1ae: 4620 mov r0, r4
800c1b0: e8bd 4010 ldmia.w sp!, {r4, lr}
800c1b4: f001 bc82 b.w 800dabc <_fflush_r>
800c1b8: bd10 pop {r4, pc}
800c1ba: bf00 nop
800c1bc: 200010a4 .word 0x200010a4
800c1c0: 2000110c .word 0x2000110c
800c1c4: 20001174 .word 0x20001174
0800c1c8 <global_stdio_init.part.0>:
800c1c8: b510 push {r4, lr}
800c1ca: 4b0b ldr r3, [pc, #44] @ (800c1f8 <global_stdio_init.part.0+0x30>)
800c1cc: 4c0b ldr r4, [pc, #44] @ (800c1fc <global_stdio_init.part.0+0x34>)
800c1ce: 4a0c ldr r2, [pc, #48] @ (800c200 <global_stdio_init.part.0+0x38>)
800c1d0: 601a str r2, [r3, #0]
800c1d2: 4620 mov r0, r4
800c1d4: 2200 movs r2, #0
800c1d6: 2104 movs r1, #4
800c1d8: f7ff ff94 bl 800c104 <std>
800c1dc: f104 0068 add.w r0, r4, #104 @ 0x68
800c1e0: 2201 movs r2, #1
800c1e2: 2109 movs r1, #9
800c1e4: f7ff ff8e bl 800c104 <std>
800c1e8: f104 00d0 add.w r0, r4, #208 @ 0xd0
800c1ec: 2202 movs r2, #2
800c1ee: e8bd 4010 ldmia.w sp!, {r4, lr}
800c1f2: 2112 movs r1, #18
800c1f4: f7ff bf86 b.w 800c104 <std>
800c1f8: 200011dc .word 0x200011dc
800c1fc: 200010a4 .word 0x200010a4
800c200: 0800c171 .word 0x0800c171
0800c204 <__sfp_lock_acquire>:
800c204: 4801 ldr r0, [pc, #4] @ (800c20c <__sfp_lock_acquire+0x8>)
800c206: f000 b900 b.w 800c40a <__retarget_lock_acquire_recursive>
800c20a: bf00 nop
800c20c: 200011e5 .word 0x200011e5
0800c210 <__sfp_lock_release>:
800c210: 4801 ldr r0, [pc, #4] @ (800c218 <__sfp_lock_release+0x8>)
800c212: f000 b8fb b.w 800c40c <__retarget_lock_release_recursive>
800c216: bf00 nop
800c218: 200011e5 .word 0x200011e5
0800c21c <__sinit>:
800c21c: b510 push {r4, lr}
800c21e: 4604 mov r4, r0
800c220: f7ff fff0 bl 800c204 <__sfp_lock_acquire>
800c224: 6a23 ldr r3, [r4, #32]
800c226: b11b cbz r3, 800c230 <__sinit+0x14>
800c228: e8bd 4010 ldmia.w sp!, {r4, lr}
800c22c: f7ff bff0 b.w 800c210 <__sfp_lock_release>
800c230: 4b04 ldr r3, [pc, #16] @ (800c244 <__sinit+0x28>)
800c232: 6223 str r3, [r4, #32]
800c234: 4b04 ldr r3, [pc, #16] @ (800c248 <__sinit+0x2c>)
800c236: 681b ldr r3, [r3, #0]
800c238: 2b00 cmp r3, #0
800c23a: d1f5 bne.n 800c228 <__sinit+0xc>
800c23c: f7ff ffc4 bl 800c1c8 <global_stdio_init.part.0>
800c240: e7f2 b.n 800c228 <__sinit+0xc>
800c242: bf00 nop
800c244: 0800c189 .word 0x0800c189
800c248: 200011dc .word 0x200011dc
0800c24c <_fwalk_sglue>:
800c24c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
800c250: 4607 mov r7, r0
800c252: 4688 mov r8, r1
800c254: 4614 mov r4, r2
800c256: 2600 movs r6, #0
800c258: e9d4 9501 ldrd r9, r5, [r4, #4]
800c25c: f1b9 0901 subs.w r9, r9, #1
800c260: d505 bpl.n 800c26e <_fwalk_sglue+0x22>
800c262: 6824 ldr r4, [r4, #0]
800c264: 2c00 cmp r4, #0
800c266: d1f7 bne.n 800c258 <_fwalk_sglue+0xc>
800c268: 4630 mov r0, r6
800c26a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
800c26e: 89ab ldrh r3, [r5, #12]
800c270: 2b01 cmp r3, #1
800c272: d907 bls.n 800c284 <_fwalk_sglue+0x38>
800c274: f9b5 300e ldrsh.w r3, [r5, #14]
800c278: 3301 adds r3, #1
800c27a: d003 beq.n 800c284 <_fwalk_sglue+0x38>
800c27c: 4629 mov r1, r5
800c27e: 4638 mov r0, r7
800c280: 47c0 blx r8
800c282: 4306 orrs r6, r0
800c284: 3568 adds r5, #104 @ 0x68
800c286: e7e9 b.n 800c25c <_fwalk_sglue+0x10>
0800c288 <__sread>:
800c288: b510 push {r4, lr}
800c28a: 460c mov r4, r1
800c28c: f9b1 100e ldrsh.w r1, [r1, #14]
800c290: f000 f86c bl 800c36c <_read_r>
800c294: 2800 cmp r0, #0
800c296: bfab itete ge
800c298: 6d63 ldrge r3, [r4, #84] @ 0x54
800c29a: 89a3 ldrhlt r3, [r4, #12]
800c29c: 181b addge r3, r3, r0
800c29e: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
800c2a2: bfac ite ge
800c2a4: 6563 strge r3, [r4, #84] @ 0x54
800c2a6: 81a3 strhlt r3, [r4, #12]
800c2a8: bd10 pop {r4, pc}
0800c2aa <__swrite>:
800c2aa: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
800c2ae: 461f mov r7, r3
800c2b0: 898b ldrh r3, [r1, #12]
800c2b2: 05db lsls r3, r3, #23
800c2b4: 4605 mov r5, r0
800c2b6: 460c mov r4, r1
800c2b8: 4616 mov r6, r2
800c2ba: d505 bpl.n 800c2c8 <__swrite+0x1e>
800c2bc: f9b1 100e ldrsh.w r1, [r1, #14]
800c2c0: 2302 movs r3, #2
800c2c2: 2200 movs r2, #0
800c2c4: f000 f840 bl 800c348 <_lseek_r>
800c2c8: 89a3 ldrh r3, [r4, #12]
800c2ca: f9b4 100e ldrsh.w r1, [r4, #14]
800c2ce: f423 5380 bic.w r3, r3, #4096 @ 0x1000
800c2d2: 81a3 strh r3, [r4, #12]
800c2d4: 4632 mov r2, r6
800c2d6: 463b mov r3, r7
800c2d8: 4628 mov r0, r5
800c2da: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
800c2de: f000 b857 b.w 800c390 <_write_r>
0800c2e2 <__sseek>:
800c2e2: b510 push {r4, lr}
800c2e4: 460c mov r4, r1
800c2e6: f9b1 100e ldrsh.w r1, [r1, #14]
800c2ea: f000 f82d bl 800c348 <_lseek_r>
800c2ee: 1c43 adds r3, r0, #1
800c2f0: 89a3 ldrh r3, [r4, #12]
800c2f2: bf15 itete ne
800c2f4: 6560 strne r0, [r4, #84] @ 0x54
800c2f6: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
800c2fa: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
800c2fe: 81a3 strheq r3, [r4, #12]
800c300: bf18 it ne
800c302: 81a3 strhne r3, [r4, #12]
800c304: bd10 pop {r4, pc}
0800c306 <__sclose>:
800c306: f9b1 100e ldrsh.w r1, [r1, #14]
800c30a: f000 b80d b.w 800c328 <_close_r>
0800c30e <memset>:
800c30e: 4402 add r2, r0
800c310: 4603 mov r3, r0
800c312: 4293 cmp r3, r2
800c314: d100 bne.n 800c318 <memset+0xa>
800c316: 4770 bx lr
800c318: f803 1b01 strb.w r1, [r3], #1
800c31c: e7f9 b.n 800c312 <memset+0x4>
...
0800c320 <_localeconv_r>:
800c320: 4800 ldr r0, [pc, #0] @ (800c324 <_localeconv_r+0x4>)
800c322: 4770 bx lr
800c324: 20000284 .word 0x20000284
0800c328 <_close_r>:
800c328: b538 push {r3, r4, r5, lr}
800c32a: 4d06 ldr r5, [pc, #24] @ (800c344 <_close_r+0x1c>)
800c32c: 2300 movs r3, #0
800c32e: 4604 mov r4, r0
800c330: 4608 mov r0, r1
800c332: 602b str r3, [r5, #0]
800c334: f7f5 fde0 bl 8001ef8 <_close>
800c338: 1c43 adds r3, r0, #1
800c33a: d102 bne.n 800c342 <_close_r+0x1a>
800c33c: 682b ldr r3, [r5, #0]
800c33e: b103 cbz r3, 800c342 <_close_r+0x1a>
800c340: 6023 str r3, [r4, #0]
800c342: bd38 pop {r3, r4, r5, pc}
800c344: 200011e0 .word 0x200011e0
0800c348 <_lseek_r>:
800c348: b538 push {r3, r4, r5, lr}
800c34a: 4d07 ldr r5, [pc, #28] @ (800c368 <_lseek_r+0x20>)
800c34c: 4604 mov r4, r0
800c34e: 4608 mov r0, r1
800c350: 4611 mov r1, r2
800c352: 2200 movs r2, #0
800c354: 602a str r2, [r5, #0]
800c356: 461a mov r2, r3
800c358: f7f5 fdf5 bl 8001f46 <_lseek>
800c35c: 1c43 adds r3, r0, #1
800c35e: d102 bne.n 800c366 <_lseek_r+0x1e>
800c360: 682b ldr r3, [r5, #0]
800c362: b103 cbz r3, 800c366 <_lseek_r+0x1e>
800c364: 6023 str r3, [r4, #0]
800c366: bd38 pop {r3, r4, r5, pc}
800c368: 200011e0 .word 0x200011e0
0800c36c <_read_r>:
800c36c: b538 push {r3, r4, r5, lr}
800c36e: 4d07 ldr r5, [pc, #28] @ (800c38c <_read_r+0x20>)
800c370: 4604 mov r4, r0
800c372: 4608 mov r0, r1
800c374: 4611 mov r1, r2
800c376: 2200 movs r2, #0
800c378: 602a str r2, [r5, #0]
800c37a: 461a mov r2, r3
800c37c: f7f5 fd83 bl 8001e86 <_read>
800c380: 1c43 adds r3, r0, #1
800c382: d102 bne.n 800c38a <_read_r+0x1e>
800c384: 682b ldr r3, [r5, #0]
800c386: b103 cbz r3, 800c38a <_read_r+0x1e>
800c388: 6023 str r3, [r4, #0]
800c38a: bd38 pop {r3, r4, r5, pc}
800c38c: 200011e0 .word 0x200011e0
0800c390 <_write_r>:
800c390: b538 push {r3, r4, r5, lr}
800c392: 4d07 ldr r5, [pc, #28] @ (800c3b0 <_write_r+0x20>)
800c394: 4604 mov r4, r0
800c396: 4608 mov r0, r1
800c398: 4611 mov r1, r2
800c39a: 2200 movs r2, #0
800c39c: 602a str r2, [r5, #0]
800c39e: 461a mov r2, r3
800c3a0: f7f5 fd8e bl 8001ec0 <_write>
800c3a4: 1c43 adds r3, r0, #1
800c3a6: d102 bne.n 800c3ae <_write_r+0x1e>
800c3a8: 682b ldr r3, [r5, #0]
800c3aa: b103 cbz r3, 800c3ae <_write_r+0x1e>
800c3ac: 6023 str r3, [r4, #0]
800c3ae: bd38 pop {r3, r4, r5, pc}
800c3b0: 200011e0 .word 0x200011e0
0800c3b4 <__errno>:
800c3b4: 4b01 ldr r3, [pc, #4] @ (800c3bc <__errno+0x8>)
800c3b6: 6818 ldr r0, [r3, #0]
800c3b8: 4770 bx lr
800c3ba: bf00 nop
800c3bc: 20000144 .word 0x20000144
0800c3c0 <__libc_init_array>:
800c3c0: b570 push {r4, r5, r6, lr}
800c3c2: 4d0d ldr r5, [pc, #52] @ (800c3f8 <__libc_init_array+0x38>)
800c3c4: 4c0d ldr r4, [pc, #52] @ (800c3fc <__libc_init_array+0x3c>)
800c3c6: 1b64 subs r4, r4, r5
800c3c8: 10a4 asrs r4, r4, #2
800c3ca: 2600 movs r6, #0
800c3cc: 42a6 cmp r6, r4
800c3ce: d109 bne.n 800c3e4 <__libc_init_array+0x24>
800c3d0: 4d0b ldr r5, [pc, #44] @ (800c400 <__libc_init_array+0x40>)
800c3d2: 4c0c ldr r4, [pc, #48] @ (800c404 <__libc_init_array+0x44>)
800c3d4: f001 fec0 bl 800e158 <_init>
800c3d8: 1b64 subs r4, r4, r5
800c3da: 10a4 asrs r4, r4, #2
800c3dc: 2600 movs r6, #0
800c3de: 42a6 cmp r6, r4
800c3e0: d105 bne.n 800c3ee <__libc_init_array+0x2e>
800c3e2: bd70 pop {r4, r5, r6, pc}
800c3e4: f855 3b04 ldr.w r3, [r5], #4
800c3e8: 4798 blx r3
800c3ea: 3601 adds r6, #1
800c3ec: e7ee b.n 800c3cc <__libc_init_array+0xc>
800c3ee: f855 3b04 ldr.w r3, [r5], #4
800c3f2: 4798 blx r3
800c3f4: 3601 adds r6, #1
800c3f6: e7f2 b.n 800c3de <__libc_init_array+0x1e>
800c3f8: 0800e584 .word 0x0800e584
800c3fc: 0800e584 .word 0x0800e584
800c400: 0800e584 .word 0x0800e584
800c404: 0800e588 .word 0x0800e588
0800c408 <__retarget_lock_init_recursive>:
800c408: 4770 bx lr
0800c40a <__retarget_lock_acquire_recursive>:
800c40a: 4770 bx lr
0800c40c <__retarget_lock_release_recursive>:
800c40c: 4770 bx lr
0800c40e <quorem>:
800c40e: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
800c412: 6903 ldr r3, [r0, #16]
800c414: 690c ldr r4, [r1, #16]
800c416: 42a3 cmp r3, r4
800c418: 4607 mov r7, r0
800c41a: db7e blt.n 800c51a <quorem+0x10c>
800c41c: 3c01 subs r4, #1
800c41e: f101 0814 add.w r8, r1, #20
800c422: 00a3 lsls r3, r4, #2
800c424: f100 0514 add.w r5, r0, #20
800c428: 9300 str r3, [sp, #0]
800c42a: eb05 0384 add.w r3, r5, r4, lsl #2
800c42e: 9301 str r3, [sp, #4]
800c430: f858 3024 ldr.w r3, [r8, r4, lsl #2]
800c434: f855 2024 ldr.w r2, [r5, r4, lsl #2]
800c438: 3301 adds r3, #1
800c43a: 429a cmp r2, r3
800c43c: eb08 0984 add.w r9, r8, r4, lsl #2
800c440: fbb2 f6f3 udiv r6, r2, r3
800c444: d32e bcc.n 800c4a4 <quorem+0x96>
800c446: f04f 0a00 mov.w sl, #0
800c44a: 46c4 mov ip, r8
800c44c: 46ae mov lr, r5
800c44e: 46d3 mov fp, sl
800c450: f85c 3b04 ldr.w r3, [ip], #4
800c454: b298 uxth r0, r3
800c456: fb06 a000 mla r0, r6, r0, sl
800c45a: 0c02 lsrs r2, r0, #16
800c45c: 0c1b lsrs r3, r3, #16
800c45e: fb06 2303 mla r3, r6, r3, r2
800c462: f8de 2000 ldr.w r2, [lr]
800c466: b280 uxth r0, r0
800c468: b292 uxth r2, r2
800c46a: 1a12 subs r2, r2, r0
800c46c: 445a add r2, fp
800c46e: f8de 0000 ldr.w r0, [lr]
800c472: ea4f 4a13 mov.w sl, r3, lsr #16
800c476: b29b uxth r3, r3
800c478: ebc3 4322 rsb r3, r3, r2, asr #16
800c47c: eb03 4310 add.w r3, r3, r0, lsr #16
800c480: b292 uxth r2, r2
800c482: ea42 4203 orr.w r2, r2, r3, lsl #16
800c486: 45e1 cmp r9, ip
800c488: f84e 2b04 str.w r2, [lr], #4
800c48c: ea4f 4b23 mov.w fp, r3, asr #16
800c490: d2de bcs.n 800c450 <quorem+0x42>
800c492: 9b00 ldr r3, [sp, #0]
800c494: 58eb ldr r3, [r5, r3]
800c496: b92b cbnz r3, 800c4a4 <quorem+0x96>
800c498: 9b01 ldr r3, [sp, #4]
800c49a: 3b04 subs r3, #4
800c49c: 429d cmp r5, r3
800c49e: 461a mov r2, r3
800c4a0: d32f bcc.n 800c502 <quorem+0xf4>
800c4a2: 613c str r4, [r7, #16]
800c4a4: 4638 mov r0, r7
800c4a6: f001 f97d bl 800d7a4 <__mcmp>
800c4aa: 2800 cmp r0, #0
800c4ac: db25 blt.n 800c4fa <quorem+0xec>
800c4ae: 4629 mov r1, r5
800c4b0: 2000 movs r0, #0
800c4b2: f858 2b04 ldr.w r2, [r8], #4
800c4b6: f8d1 c000 ldr.w ip, [r1]
800c4ba: fa1f fe82 uxth.w lr, r2
800c4be: fa1f f38c uxth.w r3, ip
800c4c2: eba3 030e sub.w r3, r3, lr
800c4c6: 4403 add r3, r0
800c4c8: 0c12 lsrs r2, r2, #16
800c4ca: ebc2 4223 rsb r2, r2, r3, asr #16
800c4ce: eb02 421c add.w r2, r2, ip, lsr #16
800c4d2: b29b uxth r3, r3
800c4d4: ea43 4302 orr.w r3, r3, r2, lsl #16
800c4d8: 45c1 cmp r9, r8
800c4da: f841 3b04 str.w r3, [r1], #4
800c4de: ea4f 4022 mov.w r0, r2, asr #16
800c4e2: d2e6 bcs.n 800c4b2 <quorem+0xa4>
800c4e4: f855 2024 ldr.w r2, [r5, r4, lsl #2]
800c4e8: eb05 0384 add.w r3, r5, r4, lsl #2
800c4ec: b922 cbnz r2, 800c4f8 <quorem+0xea>
800c4ee: 3b04 subs r3, #4
800c4f0: 429d cmp r5, r3
800c4f2: 461a mov r2, r3
800c4f4: d30b bcc.n 800c50e <quorem+0x100>
800c4f6: 613c str r4, [r7, #16]
800c4f8: 3601 adds r6, #1
800c4fa: 4630 mov r0, r6
800c4fc: b003 add sp, #12
800c4fe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800c502: 6812 ldr r2, [r2, #0]
800c504: 3b04 subs r3, #4
800c506: 2a00 cmp r2, #0
800c508: d1cb bne.n 800c4a2 <quorem+0x94>
800c50a: 3c01 subs r4, #1
800c50c: e7c6 b.n 800c49c <quorem+0x8e>
800c50e: 6812 ldr r2, [r2, #0]
800c510: 3b04 subs r3, #4
800c512: 2a00 cmp r2, #0
800c514: d1ef bne.n 800c4f6 <quorem+0xe8>
800c516: 3c01 subs r4, #1
800c518: e7ea b.n 800c4f0 <quorem+0xe2>
800c51a: 2000 movs r0, #0
800c51c: e7ee b.n 800c4fc <quorem+0xee>
...
0800c520 <_dtoa_r>:
800c520: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800c524: 69c7 ldr r7, [r0, #28]
800c526: b097 sub sp, #92 @ 0x5c
800c528: ed8d 0b04 vstr d0, [sp, #16]
800c52c: ec55 4b10 vmov r4, r5, d0
800c530: 9e20 ldr r6, [sp, #128] @ 0x80
800c532: 9107 str r1, [sp, #28]
800c534: 4681 mov r9, r0
800c536: 920c str r2, [sp, #48] @ 0x30
800c538: 9311 str r3, [sp, #68] @ 0x44
800c53a: b97f cbnz r7, 800c55c <_dtoa_r+0x3c>
800c53c: 2010 movs r0, #16
800c53e: f000 fe09 bl 800d154 <malloc>
800c542: 4602 mov r2, r0
800c544: f8c9 001c str.w r0, [r9, #28]
800c548: b920 cbnz r0, 800c554 <_dtoa_r+0x34>
800c54a: 4ba9 ldr r3, [pc, #676] @ (800c7f0 <_dtoa_r+0x2d0>)
800c54c: 21ef movs r1, #239 @ 0xef
800c54e: 48a9 ldr r0, [pc, #676] @ (800c7f4 <_dtoa_r+0x2d4>)
800c550: f001 fafa bl 800db48 <__assert_func>
800c554: e9c0 7701 strd r7, r7, [r0, #4]
800c558: 6007 str r7, [r0, #0]
800c55a: 60c7 str r7, [r0, #12]
800c55c: f8d9 301c ldr.w r3, [r9, #28]
800c560: 6819 ldr r1, [r3, #0]
800c562: b159 cbz r1, 800c57c <_dtoa_r+0x5c>
800c564: 685a ldr r2, [r3, #4]
800c566: 604a str r2, [r1, #4]
800c568: 2301 movs r3, #1
800c56a: 4093 lsls r3, r2
800c56c: 608b str r3, [r1, #8]
800c56e: 4648 mov r0, r9
800c570: f000 fee6 bl 800d340 <_Bfree>
800c574: f8d9 301c ldr.w r3, [r9, #28]
800c578: 2200 movs r2, #0
800c57a: 601a str r2, [r3, #0]
800c57c: 1e2b subs r3, r5, #0
800c57e: bfb9 ittee lt
800c580: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000
800c584: 9305 strlt r3, [sp, #20]
800c586: 2300 movge r3, #0
800c588: 6033 strge r3, [r6, #0]
800c58a: 9f05 ldr r7, [sp, #20]
800c58c: 4b9a ldr r3, [pc, #616] @ (800c7f8 <_dtoa_r+0x2d8>)
800c58e: bfbc itt lt
800c590: 2201 movlt r2, #1
800c592: 6032 strlt r2, [r6, #0]
800c594: 43bb bics r3, r7
800c596: d112 bne.n 800c5be <_dtoa_r+0x9e>
800c598: 9a11 ldr r2, [sp, #68] @ 0x44
800c59a: f242 730f movw r3, #9999 @ 0x270f
800c59e: 6013 str r3, [r2, #0]
800c5a0: f3c7 0313 ubfx r3, r7, #0, #20
800c5a4: 4323 orrs r3, r4
800c5a6: f000 855a beq.w 800d05e <_dtoa_r+0xb3e>
800c5aa: 9b21 ldr r3, [sp, #132] @ 0x84
800c5ac: f8df a25c ldr.w sl, [pc, #604] @ 800c80c <_dtoa_r+0x2ec>
800c5b0: 2b00 cmp r3, #0
800c5b2: f000 855c beq.w 800d06e <_dtoa_r+0xb4e>
800c5b6: f10a 0303 add.w r3, sl, #3
800c5ba: f000 bd56 b.w 800d06a <_dtoa_r+0xb4a>
800c5be: ed9d 7b04 vldr d7, [sp, #16]
800c5c2: 2200 movs r2, #0
800c5c4: ec51 0b17 vmov r0, r1, d7
800c5c8: 2300 movs r3, #0
800c5ca: ed8d 7b0a vstr d7, [sp, #40] @ 0x28
800c5ce: f7f4 fa7b bl 8000ac8 <__aeabi_dcmpeq>
800c5d2: 4680 mov r8, r0
800c5d4: b158 cbz r0, 800c5ee <_dtoa_r+0xce>
800c5d6: 9a11 ldr r2, [sp, #68] @ 0x44
800c5d8: 2301 movs r3, #1
800c5da: 6013 str r3, [r2, #0]
800c5dc: 9b21 ldr r3, [sp, #132] @ 0x84
800c5de: b113 cbz r3, 800c5e6 <_dtoa_r+0xc6>
800c5e0: 9a21 ldr r2, [sp, #132] @ 0x84
800c5e2: 4b86 ldr r3, [pc, #536] @ (800c7fc <_dtoa_r+0x2dc>)
800c5e4: 6013 str r3, [r2, #0]
800c5e6: f8df a228 ldr.w sl, [pc, #552] @ 800c810 <_dtoa_r+0x2f0>
800c5ea: f000 bd40 b.w 800d06e <_dtoa_r+0xb4e>
800c5ee: ed9d 0b0a vldr d0, [sp, #40] @ 0x28
800c5f2: aa14 add r2, sp, #80 @ 0x50
800c5f4: a915 add r1, sp, #84 @ 0x54
800c5f6: 4648 mov r0, r9
800c5f8: f001 f984 bl 800d904 <__d2b>
800c5fc: f3c7 560a ubfx r6, r7, #20, #11
800c600: 9002 str r0, [sp, #8]
800c602: 2e00 cmp r6, #0
800c604: d078 beq.n 800c6f8 <_dtoa_r+0x1d8>
800c606: 9b0b ldr r3, [sp, #44] @ 0x2c
800c608: f8cd 8048 str.w r8, [sp, #72] @ 0x48
800c60c: f3c3 0313 ubfx r3, r3, #0, #20
800c610: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
800c614: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000
800c618: f443 1340 orr.w r3, r3, #3145728 @ 0x300000
800c61c: f2a6 36ff subw r6, r6, #1023 @ 0x3ff
800c620: 4619 mov r1, r3
800c622: 2200 movs r2, #0
800c624: 4b76 ldr r3, [pc, #472] @ (800c800 <_dtoa_r+0x2e0>)
800c626: f7f3 fe2f bl 8000288 <__aeabi_dsub>
800c62a: a36b add r3, pc, #428 @ (adr r3, 800c7d8 <_dtoa_r+0x2b8>)
800c62c: e9d3 2300 ldrd r2, r3, [r3]
800c630: f7f3 ffe2 bl 80005f8 <__aeabi_dmul>
800c634: a36a add r3, pc, #424 @ (adr r3, 800c7e0 <_dtoa_r+0x2c0>)
800c636: e9d3 2300 ldrd r2, r3, [r3]
800c63a: f7f3 fe27 bl 800028c <__adddf3>
800c63e: 4604 mov r4, r0
800c640: 4630 mov r0, r6
800c642: 460d mov r5, r1
800c644: f7f3 ff6e bl 8000524 <__aeabi_i2d>
800c648: a367 add r3, pc, #412 @ (adr r3, 800c7e8 <_dtoa_r+0x2c8>)
800c64a: e9d3 2300 ldrd r2, r3, [r3]
800c64e: f7f3 ffd3 bl 80005f8 <__aeabi_dmul>
800c652: 4602 mov r2, r0
800c654: 460b mov r3, r1
800c656: 4620 mov r0, r4
800c658: 4629 mov r1, r5
800c65a: f7f3 fe17 bl 800028c <__adddf3>
800c65e: 4604 mov r4, r0
800c660: 460d mov r5, r1
800c662: f7f4 fa79 bl 8000b58 <__aeabi_d2iz>
800c666: 2200 movs r2, #0
800c668: 4607 mov r7, r0
800c66a: 2300 movs r3, #0
800c66c: 4620 mov r0, r4
800c66e: 4629 mov r1, r5
800c670: f7f4 fa34 bl 8000adc <__aeabi_dcmplt>
800c674: b140 cbz r0, 800c688 <_dtoa_r+0x168>
800c676: 4638 mov r0, r7
800c678: f7f3 ff54 bl 8000524 <__aeabi_i2d>
800c67c: 4622 mov r2, r4
800c67e: 462b mov r3, r5
800c680: f7f4 fa22 bl 8000ac8 <__aeabi_dcmpeq>
800c684: b900 cbnz r0, 800c688 <_dtoa_r+0x168>
800c686: 3f01 subs r7, #1
800c688: 2f16 cmp r7, #22
800c68a: d852 bhi.n 800c732 <_dtoa_r+0x212>
800c68c: 4b5d ldr r3, [pc, #372] @ (800c804 <_dtoa_r+0x2e4>)
800c68e: eb03 03c7 add.w r3, r3, r7, lsl #3
800c692: e9d3 2300 ldrd r2, r3, [r3]
800c696: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
800c69a: f7f4 fa1f bl 8000adc <__aeabi_dcmplt>
800c69e: 2800 cmp r0, #0
800c6a0: d049 beq.n 800c736 <_dtoa_r+0x216>
800c6a2: 3f01 subs r7, #1
800c6a4: 2300 movs r3, #0
800c6a6: 9310 str r3, [sp, #64] @ 0x40
800c6a8: 9b14 ldr r3, [sp, #80] @ 0x50
800c6aa: 1b9b subs r3, r3, r6
800c6ac: 1e5a subs r2, r3, #1
800c6ae: bf45 ittet mi
800c6b0: f1c3 0301 rsbmi r3, r3, #1
800c6b4: 9300 strmi r3, [sp, #0]
800c6b6: 2300 movpl r3, #0
800c6b8: 2300 movmi r3, #0
800c6ba: 9206 str r2, [sp, #24]
800c6bc: bf54 ite pl
800c6be: 9300 strpl r3, [sp, #0]
800c6c0: 9306 strmi r3, [sp, #24]
800c6c2: 2f00 cmp r7, #0
800c6c4: db39 blt.n 800c73a <_dtoa_r+0x21a>
800c6c6: 9b06 ldr r3, [sp, #24]
800c6c8: 970d str r7, [sp, #52] @ 0x34
800c6ca: 443b add r3, r7
800c6cc: 9306 str r3, [sp, #24]
800c6ce: 2300 movs r3, #0
800c6d0: 9308 str r3, [sp, #32]
800c6d2: 9b07 ldr r3, [sp, #28]
800c6d4: 2b09 cmp r3, #9
800c6d6: d863 bhi.n 800c7a0 <_dtoa_r+0x280>
800c6d8: 2b05 cmp r3, #5
800c6da: bfc4 itt gt
800c6dc: 3b04 subgt r3, #4
800c6de: 9307 strgt r3, [sp, #28]
800c6e0: 9b07 ldr r3, [sp, #28]
800c6e2: f1a3 0302 sub.w r3, r3, #2
800c6e6: bfcc ite gt
800c6e8: 2400 movgt r4, #0
800c6ea: 2401 movle r4, #1
800c6ec: 2b03 cmp r3, #3
800c6ee: d863 bhi.n 800c7b8 <_dtoa_r+0x298>
800c6f0: e8df f003 tbb [pc, r3]
800c6f4: 2b375452 .word 0x2b375452
800c6f8: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50
800c6fc: 441e add r6, r3
800c6fe: f206 4332 addw r3, r6, #1074 @ 0x432
800c702: 2b20 cmp r3, #32
800c704: bfc1 itttt gt
800c706: f1c3 0340 rsbgt r3, r3, #64 @ 0x40
800c70a: 409f lslgt r7, r3
800c70c: f206 4312 addwgt r3, r6, #1042 @ 0x412
800c710: fa24 f303 lsrgt.w r3, r4, r3
800c714: bfd6 itet le
800c716: f1c3 0320 rsble r3, r3, #32
800c71a: ea47 0003 orrgt.w r0, r7, r3
800c71e: fa04 f003 lslle.w r0, r4, r3
800c722: f7f3 feef bl 8000504 <__aeabi_ui2d>
800c726: 2201 movs r2, #1
800c728: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000
800c72c: 3e01 subs r6, #1
800c72e: 9212 str r2, [sp, #72] @ 0x48
800c730: e776 b.n 800c620 <_dtoa_r+0x100>
800c732: 2301 movs r3, #1
800c734: e7b7 b.n 800c6a6 <_dtoa_r+0x186>
800c736: 9010 str r0, [sp, #64] @ 0x40
800c738: e7b6 b.n 800c6a8 <_dtoa_r+0x188>
800c73a: 9b00 ldr r3, [sp, #0]
800c73c: 1bdb subs r3, r3, r7
800c73e: 9300 str r3, [sp, #0]
800c740: 427b negs r3, r7
800c742: 9308 str r3, [sp, #32]
800c744: 2300 movs r3, #0
800c746: 930d str r3, [sp, #52] @ 0x34
800c748: e7c3 b.n 800c6d2 <_dtoa_r+0x1b2>
800c74a: 2301 movs r3, #1
800c74c: 9309 str r3, [sp, #36] @ 0x24
800c74e: 9b0c ldr r3, [sp, #48] @ 0x30
800c750: eb07 0b03 add.w fp, r7, r3
800c754: f10b 0301 add.w r3, fp, #1
800c758: 2b01 cmp r3, #1
800c75a: 9303 str r3, [sp, #12]
800c75c: bfb8 it lt
800c75e: 2301 movlt r3, #1
800c760: e006 b.n 800c770 <_dtoa_r+0x250>
800c762: 2301 movs r3, #1
800c764: 9309 str r3, [sp, #36] @ 0x24
800c766: 9b0c ldr r3, [sp, #48] @ 0x30
800c768: 2b00 cmp r3, #0
800c76a: dd28 ble.n 800c7be <_dtoa_r+0x29e>
800c76c: 469b mov fp, r3
800c76e: 9303 str r3, [sp, #12]
800c770: f8d9 001c ldr.w r0, [r9, #28]
800c774: 2100 movs r1, #0
800c776: 2204 movs r2, #4
800c778: f102 0514 add.w r5, r2, #20
800c77c: 429d cmp r5, r3
800c77e: d926 bls.n 800c7ce <_dtoa_r+0x2ae>
800c780: 6041 str r1, [r0, #4]
800c782: 4648 mov r0, r9
800c784: f000 fd9c bl 800d2c0 <_Balloc>
800c788: 4682 mov sl, r0
800c78a: 2800 cmp r0, #0
800c78c: d142 bne.n 800c814 <_dtoa_r+0x2f4>
800c78e: 4b1e ldr r3, [pc, #120] @ (800c808 <_dtoa_r+0x2e8>)
800c790: 4602 mov r2, r0
800c792: f240 11af movw r1, #431 @ 0x1af
800c796: e6da b.n 800c54e <_dtoa_r+0x2e>
800c798: 2300 movs r3, #0
800c79a: e7e3 b.n 800c764 <_dtoa_r+0x244>
800c79c: 2300 movs r3, #0
800c79e: e7d5 b.n 800c74c <_dtoa_r+0x22c>
800c7a0: 2401 movs r4, #1
800c7a2: 2300 movs r3, #0
800c7a4: 9307 str r3, [sp, #28]
800c7a6: 9409 str r4, [sp, #36] @ 0x24
800c7a8: f04f 3bff mov.w fp, #4294967295
800c7ac: 2200 movs r2, #0
800c7ae: f8cd b00c str.w fp, [sp, #12]
800c7b2: 2312 movs r3, #18
800c7b4: 920c str r2, [sp, #48] @ 0x30
800c7b6: e7db b.n 800c770 <_dtoa_r+0x250>
800c7b8: 2301 movs r3, #1
800c7ba: 9309 str r3, [sp, #36] @ 0x24
800c7bc: e7f4 b.n 800c7a8 <_dtoa_r+0x288>
800c7be: f04f 0b01 mov.w fp, #1
800c7c2: f8cd b00c str.w fp, [sp, #12]
800c7c6: 465b mov r3, fp
800c7c8: f8cd b030 str.w fp, [sp, #48] @ 0x30
800c7cc: e7d0 b.n 800c770 <_dtoa_r+0x250>
800c7ce: 3101 adds r1, #1
800c7d0: 0052 lsls r2, r2, #1
800c7d2: e7d1 b.n 800c778 <_dtoa_r+0x258>
800c7d4: f3af 8000 nop.w
800c7d8: 636f4361 .word 0x636f4361
800c7dc: 3fd287a7 .word 0x3fd287a7
800c7e0: 8b60c8b3 .word 0x8b60c8b3
800c7e4: 3fc68a28 .word 0x3fc68a28
800c7e8: 509f79fb .word 0x509f79fb
800c7ec: 3fd34413 .word 0x3fd34413
800c7f0: 0800e249 .word 0x0800e249
800c7f4: 0800e260 .word 0x0800e260
800c7f8: 7ff00000 .word 0x7ff00000
800c7fc: 0800e219 .word 0x0800e219
800c800: 3ff80000 .word 0x3ff80000
800c804: 0800e3b0 .word 0x0800e3b0
800c808: 0800e2b8 .word 0x0800e2b8
800c80c: 0800e245 .word 0x0800e245
800c810: 0800e218 .word 0x0800e218
800c814: f8d9 301c ldr.w r3, [r9, #28]
800c818: 6018 str r0, [r3, #0]
800c81a: 9b03 ldr r3, [sp, #12]
800c81c: 2b0e cmp r3, #14
800c81e: f200 80a1 bhi.w 800c964 <_dtoa_r+0x444>
800c822: 2c00 cmp r4, #0
800c824: f000 809e beq.w 800c964 <_dtoa_r+0x444>
800c828: 2f00 cmp r7, #0
800c82a: dd33 ble.n 800c894 <_dtoa_r+0x374>
800c82c: 4b9c ldr r3, [pc, #624] @ (800caa0 <_dtoa_r+0x580>)
800c82e: f007 020f and.w r2, r7, #15
800c832: eb03 03c2 add.w r3, r3, r2, lsl #3
800c836: ed93 7b00 vldr d7, [r3]
800c83a: 05f8 lsls r0, r7, #23
800c83c: ed8d 7b0e vstr d7, [sp, #56] @ 0x38
800c840: ea4f 1427 mov.w r4, r7, asr #4
800c844: d516 bpl.n 800c874 <_dtoa_r+0x354>
800c846: 4b97 ldr r3, [pc, #604] @ (800caa4 <_dtoa_r+0x584>)
800c848: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
800c84c: e9d3 2308 ldrd r2, r3, [r3, #32]
800c850: f7f3 fffc bl 800084c <__aeabi_ddiv>
800c854: e9cd 0104 strd r0, r1, [sp, #16]
800c858: f004 040f and.w r4, r4, #15
800c85c: 2603 movs r6, #3
800c85e: 4d91 ldr r5, [pc, #580] @ (800caa4 <_dtoa_r+0x584>)
800c860: b954 cbnz r4, 800c878 <_dtoa_r+0x358>
800c862: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
800c866: e9dd 0104 ldrd r0, r1, [sp, #16]
800c86a: f7f3 ffef bl 800084c <__aeabi_ddiv>
800c86e: e9cd 0104 strd r0, r1, [sp, #16]
800c872: e028 b.n 800c8c6 <_dtoa_r+0x3a6>
800c874: 2602 movs r6, #2
800c876: e7f2 b.n 800c85e <_dtoa_r+0x33e>
800c878: 07e1 lsls r1, r4, #31
800c87a: d508 bpl.n 800c88e <_dtoa_r+0x36e>
800c87c: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
800c880: e9d5 2300 ldrd r2, r3, [r5]
800c884: f7f3 feb8 bl 80005f8 <__aeabi_dmul>
800c888: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
800c88c: 3601 adds r6, #1
800c88e: 1064 asrs r4, r4, #1
800c890: 3508 adds r5, #8
800c892: e7e5 b.n 800c860 <_dtoa_r+0x340>
800c894: f000 80af beq.w 800c9f6 <_dtoa_r+0x4d6>
800c898: 427c negs r4, r7
800c89a: 4b81 ldr r3, [pc, #516] @ (800caa0 <_dtoa_r+0x580>)
800c89c: 4d81 ldr r5, [pc, #516] @ (800caa4 <_dtoa_r+0x584>)
800c89e: f004 020f and.w r2, r4, #15
800c8a2: eb03 03c2 add.w r3, r3, r2, lsl #3
800c8a6: e9d3 2300 ldrd r2, r3, [r3]
800c8aa: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
800c8ae: f7f3 fea3 bl 80005f8 <__aeabi_dmul>
800c8b2: e9cd 0104 strd r0, r1, [sp, #16]
800c8b6: 1124 asrs r4, r4, #4
800c8b8: 2300 movs r3, #0
800c8ba: 2602 movs r6, #2
800c8bc: 2c00 cmp r4, #0
800c8be: f040 808f bne.w 800c9e0 <_dtoa_r+0x4c0>
800c8c2: 2b00 cmp r3, #0
800c8c4: d1d3 bne.n 800c86e <_dtoa_r+0x34e>
800c8c6: 9b10 ldr r3, [sp, #64] @ 0x40
800c8c8: e9dd 4504 ldrd r4, r5, [sp, #16]
800c8cc: 2b00 cmp r3, #0
800c8ce: f000 8094 beq.w 800c9fa <_dtoa_r+0x4da>
800c8d2: 4b75 ldr r3, [pc, #468] @ (800caa8 <_dtoa_r+0x588>)
800c8d4: 2200 movs r2, #0
800c8d6: 4620 mov r0, r4
800c8d8: 4629 mov r1, r5
800c8da: f7f4 f8ff bl 8000adc <__aeabi_dcmplt>
800c8de: 2800 cmp r0, #0
800c8e0: f000 808b beq.w 800c9fa <_dtoa_r+0x4da>
800c8e4: 9b03 ldr r3, [sp, #12]
800c8e6: 2b00 cmp r3, #0
800c8e8: f000 8087 beq.w 800c9fa <_dtoa_r+0x4da>
800c8ec: f1bb 0f00 cmp.w fp, #0
800c8f0: dd34 ble.n 800c95c <_dtoa_r+0x43c>
800c8f2: 4620 mov r0, r4
800c8f4: 4b6d ldr r3, [pc, #436] @ (800caac <_dtoa_r+0x58c>)
800c8f6: 2200 movs r2, #0
800c8f8: 4629 mov r1, r5
800c8fa: f7f3 fe7d bl 80005f8 <__aeabi_dmul>
800c8fe: e9cd 0104 strd r0, r1, [sp, #16]
800c902: f107 38ff add.w r8, r7, #4294967295
800c906: 3601 adds r6, #1
800c908: 465c mov r4, fp
800c90a: 4630 mov r0, r6
800c90c: f7f3 fe0a bl 8000524 <__aeabi_i2d>
800c910: e9dd 2304 ldrd r2, r3, [sp, #16]
800c914: f7f3 fe70 bl 80005f8 <__aeabi_dmul>
800c918: 4b65 ldr r3, [pc, #404] @ (800cab0 <_dtoa_r+0x590>)
800c91a: 2200 movs r2, #0
800c91c: f7f3 fcb6 bl 800028c <__adddf3>
800c920: 4605 mov r5, r0
800c922: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000
800c926: 2c00 cmp r4, #0
800c928: d16a bne.n 800ca00 <_dtoa_r+0x4e0>
800c92a: e9dd 0104 ldrd r0, r1, [sp, #16]
800c92e: 4b61 ldr r3, [pc, #388] @ (800cab4 <_dtoa_r+0x594>)
800c930: 2200 movs r2, #0
800c932: f7f3 fca9 bl 8000288 <__aeabi_dsub>
800c936: 4602 mov r2, r0
800c938: 460b mov r3, r1
800c93a: e9cd 2304 strd r2, r3, [sp, #16]
800c93e: 462a mov r2, r5
800c940: 4633 mov r3, r6
800c942: f7f4 f8e9 bl 8000b18 <__aeabi_dcmpgt>
800c946: 2800 cmp r0, #0
800c948: f040 8298 bne.w 800ce7c <_dtoa_r+0x95c>
800c94c: e9dd 0104 ldrd r0, r1, [sp, #16]
800c950: 462a mov r2, r5
800c952: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000
800c956: f7f4 f8c1 bl 8000adc <__aeabi_dcmplt>
800c95a: bb38 cbnz r0, 800c9ac <_dtoa_r+0x48c>
800c95c: e9dd 340a ldrd r3, r4, [sp, #40] @ 0x28
800c960: e9cd 3404 strd r3, r4, [sp, #16]
800c964: 9b15 ldr r3, [sp, #84] @ 0x54
800c966: 2b00 cmp r3, #0
800c968: f2c0 8157 blt.w 800cc1a <_dtoa_r+0x6fa>
800c96c: 2f0e cmp r7, #14
800c96e: f300 8154 bgt.w 800cc1a <_dtoa_r+0x6fa>
800c972: 4b4b ldr r3, [pc, #300] @ (800caa0 <_dtoa_r+0x580>)
800c974: eb03 03c7 add.w r3, r3, r7, lsl #3
800c978: ed93 7b00 vldr d7, [r3]
800c97c: 9b0c ldr r3, [sp, #48] @ 0x30
800c97e: 2b00 cmp r3, #0
800c980: ed8d 7b00 vstr d7, [sp]
800c984: f280 80e5 bge.w 800cb52 <_dtoa_r+0x632>
800c988: 9b03 ldr r3, [sp, #12]
800c98a: 2b00 cmp r3, #0
800c98c: f300 80e1 bgt.w 800cb52 <_dtoa_r+0x632>
800c990: d10c bne.n 800c9ac <_dtoa_r+0x48c>
800c992: 4b48 ldr r3, [pc, #288] @ (800cab4 <_dtoa_r+0x594>)
800c994: 2200 movs r2, #0
800c996: ec51 0b17 vmov r0, r1, d7
800c99a: f7f3 fe2d bl 80005f8 <__aeabi_dmul>
800c99e: e9dd 2304 ldrd r2, r3, [sp, #16]
800c9a2: f7f4 f8af bl 8000b04 <__aeabi_dcmpge>
800c9a6: 2800 cmp r0, #0
800c9a8: f000 8266 beq.w 800ce78 <_dtoa_r+0x958>
800c9ac: 2400 movs r4, #0
800c9ae: 4625 mov r5, r4
800c9b0: 9b0c ldr r3, [sp, #48] @ 0x30
800c9b2: 4656 mov r6, sl
800c9b4: ea6f 0803 mvn.w r8, r3
800c9b8: 2700 movs r7, #0
800c9ba: 4621 mov r1, r4
800c9bc: 4648 mov r0, r9
800c9be: f000 fcbf bl 800d340 <_Bfree>
800c9c2: 2d00 cmp r5, #0
800c9c4: f000 80bd beq.w 800cb42 <_dtoa_r+0x622>
800c9c8: b12f cbz r7, 800c9d6 <_dtoa_r+0x4b6>
800c9ca: 42af cmp r7, r5
800c9cc: d003 beq.n 800c9d6 <_dtoa_r+0x4b6>
800c9ce: 4639 mov r1, r7
800c9d0: 4648 mov r0, r9
800c9d2: f000 fcb5 bl 800d340 <_Bfree>
800c9d6: 4629 mov r1, r5
800c9d8: 4648 mov r0, r9
800c9da: f000 fcb1 bl 800d340 <_Bfree>
800c9de: e0b0 b.n 800cb42 <_dtoa_r+0x622>
800c9e0: 07e2 lsls r2, r4, #31
800c9e2: d505 bpl.n 800c9f0 <_dtoa_r+0x4d0>
800c9e4: e9d5 2300 ldrd r2, r3, [r5]
800c9e8: f7f3 fe06 bl 80005f8 <__aeabi_dmul>
800c9ec: 3601 adds r6, #1
800c9ee: 2301 movs r3, #1
800c9f0: 1064 asrs r4, r4, #1
800c9f2: 3508 adds r5, #8
800c9f4: e762 b.n 800c8bc <_dtoa_r+0x39c>
800c9f6: 2602 movs r6, #2
800c9f8: e765 b.n 800c8c6 <_dtoa_r+0x3a6>
800c9fa: 9c03 ldr r4, [sp, #12]
800c9fc: 46b8 mov r8, r7
800c9fe: e784 b.n 800c90a <_dtoa_r+0x3ea>
800ca00: 4b27 ldr r3, [pc, #156] @ (800caa0 <_dtoa_r+0x580>)
800ca02: 9909 ldr r1, [sp, #36] @ 0x24
800ca04: eb03 03c4 add.w r3, r3, r4, lsl #3
800ca08: e953 2302 ldrd r2, r3, [r3, #-8]
800ca0c: 4454 add r4, sl
800ca0e: 2900 cmp r1, #0
800ca10: d054 beq.n 800cabc <_dtoa_r+0x59c>
800ca12: 4929 ldr r1, [pc, #164] @ (800cab8 <_dtoa_r+0x598>)
800ca14: 2000 movs r0, #0
800ca16: f7f3 ff19 bl 800084c <__aeabi_ddiv>
800ca1a: 4633 mov r3, r6
800ca1c: 462a mov r2, r5
800ca1e: f7f3 fc33 bl 8000288 <__aeabi_dsub>
800ca22: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
800ca26: 4656 mov r6, sl
800ca28: e9dd 0104 ldrd r0, r1, [sp, #16]
800ca2c: f7f4 f894 bl 8000b58 <__aeabi_d2iz>
800ca30: 4605 mov r5, r0
800ca32: f7f3 fd77 bl 8000524 <__aeabi_i2d>
800ca36: 4602 mov r2, r0
800ca38: 460b mov r3, r1
800ca3a: e9dd 0104 ldrd r0, r1, [sp, #16]
800ca3e: f7f3 fc23 bl 8000288 <__aeabi_dsub>
800ca42: 3530 adds r5, #48 @ 0x30
800ca44: 4602 mov r2, r0
800ca46: 460b mov r3, r1
800ca48: e9cd 2304 strd r2, r3, [sp, #16]
800ca4c: f806 5b01 strb.w r5, [r6], #1
800ca50: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
800ca54: f7f4 f842 bl 8000adc <__aeabi_dcmplt>
800ca58: 2800 cmp r0, #0
800ca5a: d172 bne.n 800cb42 <_dtoa_r+0x622>
800ca5c: e9dd 2304 ldrd r2, r3, [sp, #16]
800ca60: 4911 ldr r1, [pc, #68] @ (800caa8 <_dtoa_r+0x588>)
800ca62: 2000 movs r0, #0
800ca64: f7f3 fc10 bl 8000288 <__aeabi_dsub>
800ca68: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
800ca6c: f7f4 f836 bl 8000adc <__aeabi_dcmplt>
800ca70: 2800 cmp r0, #0
800ca72: f040 80b4 bne.w 800cbde <_dtoa_r+0x6be>
800ca76: 42a6 cmp r6, r4
800ca78: f43f af70 beq.w 800c95c <_dtoa_r+0x43c>
800ca7c: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
800ca80: 4b0a ldr r3, [pc, #40] @ (800caac <_dtoa_r+0x58c>)
800ca82: 2200 movs r2, #0
800ca84: f7f3 fdb8 bl 80005f8 <__aeabi_dmul>
800ca88: 4b08 ldr r3, [pc, #32] @ (800caac <_dtoa_r+0x58c>)
800ca8a: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
800ca8e: 2200 movs r2, #0
800ca90: e9dd 0104 ldrd r0, r1, [sp, #16]
800ca94: f7f3 fdb0 bl 80005f8 <__aeabi_dmul>
800ca98: e9cd 0104 strd r0, r1, [sp, #16]
800ca9c: e7c4 b.n 800ca28 <_dtoa_r+0x508>
800ca9e: bf00 nop
800caa0: 0800e3b0 .word 0x0800e3b0
800caa4: 0800e388 .word 0x0800e388
800caa8: 3ff00000 .word 0x3ff00000
800caac: 40240000 .word 0x40240000
800cab0: 401c0000 .word 0x401c0000
800cab4: 40140000 .word 0x40140000
800cab8: 3fe00000 .word 0x3fe00000
800cabc: 4631 mov r1, r6
800cabe: 4628 mov r0, r5
800cac0: f7f3 fd9a bl 80005f8 <__aeabi_dmul>
800cac4: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
800cac8: 9413 str r4, [sp, #76] @ 0x4c
800caca: 4656 mov r6, sl
800cacc: e9dd 0104 ldrd r0, r1, [sp, #16]
800cad0: f7f4 f842 bl 8000b58 <__aeabi_d2iz>
800cad4: 4605 mov r5, r0
800cad6: f7f3 fd25 bl 8000524 <__aeabi_i2d>
800cada: 4602 mov r2, r0
800cadc: 460b mov r3, r1
800cade: e9dd 0104 ldrd r0, r1, [sp, #16]
800cae2: f7f3 fbd1 bl 8000288 <__aeabi_dsub>
800cae6: 3530 adds r5, #48 @ 0x30
800cae8: f806 5b01 strb.w r5, [r6], #1
800caec: 4602 mov r2, r0
800caee: 460b mov r3, r1
800caf0: 42a6 cmp r6, r4
800caf2: e9cd 2304 strd r2, r3, [sp, #16]
800caf6: f04f 0200 mov.w r2, #0
800cafa: d124 bne.n 800cb46 <_dtoa_r+0x626>
800cafc: 4baf ldr r3, [pc, #700] @ (800cdbc <_dtoa_r+0x89c>)
800cafe: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
800cb02: f7f3 fbc3 bl 800028c <__adddf3>
800cb06: 4602 mov r2, r0
800cb08: 460b mov r3, r1
800cb0a: e9dd 0104 ldrd r0, r1, [sp, #16]
800cb0e: f7f4 f803 bl 8000b18 <__aeabi_dcmpgt>
800cb12: 2800 cmp r0, #0
800cb14: d163 bne.n 800cbde <_dtoa_r+0x6be>
800cb16: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
800cb1a: 49a8 ldr r1, [pc, #672] @ (800cdbc <_dtoa_r+0x89c>)
800cb1c: 2000 movs r0, #0
800cb1e: f7f3 fbb3 bl 8000288 <__aeabi_dsub>
800cb22: 4602 mov r2, r0
800cb24: 460b mov r3, r1
800cb26: e9dd 0104 ldrd r0, r1, [sp, #16]
800cb2a: f7f3 ffd7 bl 8000adc <__aeabi_dcmplt>
800cb2e: 2800 cmp r0, #0
800cb30: f43f af14 beq.w 800c95c <_dtoa_r+0x43c>
800cb34: 9e13 ldr r6, [sp, #76] @ 0x4c
800cb36: 1e73 subs r3, r6, #1
800cb38: 9313 str r3, [sp, #76] @ 0x4c
800cb3a: f816 3c01 ldrb.w r3, [r6, #-1]
800cb3e: 2b30 cmp r3, #48 @ 0x30
800cb40: d0f8 beq.n 800cb34 <_dtoa_r+0x614>
800cb42: 4647 mov r7, r8
800cb44: e03b b.n 800cbbe <_dtoa_r+0x69e>
800cb46: 4b9e ldr r3, [pc, #632] @ (800cdc0 <_dtoa_r+0x8a0>)
800cb48: f7f3 fd56 bl 80005f8 <__aeabi_dmul>
800cb4c: e9cd 0104 strd r0, r1, [sp, #16]
800cb50: e7bc b.n 800cacc <_dtoa_r+0x5ac>
800cb52: e9dd 4504 ldrd r4, r5, [sp, #16]
800cb56: 4656 mov r6, sl
800cb58: e9dd 2300 ldrd r2, r3, [sp]
800cb5c: 4620 mov r0, r4
800cb5e: 4629 mov r1, r5
800cb60: f7f3 fe74 bl 800084c <__aeabi_ddiv>
800cb64: f7f3 fff8 bl 8000b58 <__aeabi_d2iz>
800cb68: 4680 mov r8, r0
800cb6a: f7f3 fcdb bl 8000524 <__aeabi_i2d>
800cb6e: e9dd 2300 ldrd r2, r3, [sp]
800cb72: f7f3 fd41 bl 80005f8 <__aeabi_dmul>
800cb76: 4602 mov r2, r0
800cb78: 460b mov r3, r1
800cb7a: 4620 mov r0, r4
800cb7c: 4629 mov r1, r5
800cb7e: f108 0430 add.w r4, r8, #48 @ 0x30
800cb82: f7f3 fb81 bl 8000288 <__aeabi_dsub>
800cb86: f806 4b01 strb.w r4, [r6], #1
800cb8a: 9d03 ldr r5, [sp, #12]
800cb8c: eba6 040a sub.w r4, r6, sl
800cb90: 42a5 cmp r5, r4
800cb92: 4602 mov r2, r0
800cb94: 460b mov r3, r1
800cb96: d133 bne.n 800cc00 <_dtoa_r+0x6e0>
800cb98: f7f3 fb78 bl 800028c <__adddf3>
800cb9c: e9dd 2300 ldrd r2, r3, [sp]
800cba0: 4604 mov r4, r0
800cba2: 460d mov r5, r1
800cba4: f7f3 ffb8 bl 8000b18 <__aeabi_dcmpgt>
800cba8: b9c0 cbnz r0, 800cbdc <_dtoa_r+0x6bc>
800cbaa: e9dd 2300 ldrd r2, r3, [sp]
800cbae: 4620 mov r0, r4
800cbb0: 4629 mov r1, r5
800cbb2: f7f3 ff89 bl 8000ac8 <__aeabi_dcmpeq>
800cbb6: b110 cbz r0, 800cbbe <_dtoa_r+0x69e>
800cbb8: f018 0f01 tst.w r8, #1
800cbbc: d10e bne.n 800cbdc <_dtoa_r+0x6bc>
800cbbe: 9902 ldr r1, [sp, #8]
800cbc0: 4648 mov r0, r9
800cbc2: f000 fbbd bl 800d340 <_Bfree>
800cbc6: 2300 movs r3, #0
800cbc8: 7033 strb r3, [r6, #0]
800cbca: 9b11 ldr r3, [sp, #68] @ 0x44
800cbcc: 3701 adds r7, #1
800cbce: 601f str r7, [r3, #0]
800cbd0: 9b21 ldr r3, [sp, #132] @ 0x84
800cbd2: 2b00 cmp r3, #0
800cbd4: f000 824b beq.w 800d06e <_dtoa_r+0xb4e>
800cbd8: 601e str r6, [r3, #0]
800cbda: e248 b.n 800d06e <_dtoa_r+0xb4e>
800cbdc: 46b8 mov r8, r7
800cbde: 4633 mov r3, r6
800cbe0: 461e mov r6, r3
800cbe2: f813 2d01 ldrb.w r2, [r3, #-1]!
800cbe6: 2a39 cmp r2, #57 @ 0x39
800cbe8: d106 bne.n 800cbf8 <_dtoa_r+0x6d8>
800cbea: 459a cmp sl, r3
800cbec: d1f8 bne.n 800cbe0 <_dtoa_r+0x6c0>
800cbee: 2230 movs r2, #48 @ 0x30
800cbf0: f108 0801 add.w r8, r8, #1
800cbf4: f88a 2000 strb.w r2, [sl]
800cbf8: 781a ldrb r2, [r3, #0]
800cbfa: 3201 adds r2, #1
800cbfc: 701a strb r2, [r3, #0]
800cbfe: e7a0 b.n 800cb42 <_dtoa_r+0x622>
800cc00: 4b6f ldr r3, [pc, #444] @ (800cdc0 <_dtoa_r+0x8a0>)
800cc02: 2200 movs r2, #0
800cc04: f7f3 fcf8 bl 80005f8 <__aeabi_dmul>
800cc08: 2200 movs r2, #0
800cc0a: 2300 movs r3, #0
800cc0c: 4604 mov r4, r0
800cc0e: 460d mov r5, r1
800cc10: f7f3 ff5a bl 8000ac8 <__aeabi_dcmpeq>
800cc14: 2800 cmp r0, #0
800cc16: d09f beq.n 800cb58 <_dtoa_r+0x638>
800cc18: e7d1 b.n 800cbbe <_dtoa_r+0x69e>
800cc1a: 9a09 ldr r2, [sp, #36] @ 0x24
800cc1c: 2a00 cmp r2, #0
800cc1e: f000 80ea beq.w 800cdf6 <_dtoa_r+0x8d6>
800cc22: 9a07 ldr r2, [sp, #28]
800cc24: 2a01 cmp r2, #1
800cc26: f300 80cd bgt.w 800cdc4 <_dtoa_r+0x8a4>
800cc2a: 9a12 ldr r2, [sp, #72] @ 0x48
800cc2c: 2a00 cmp r2, #0
800cc2e: f000 80c1 beq.w 800cdb4 <_dtoa_r+0x894>
800cc32: f203 4333 addw r3, r3, #1075 @ 0x433
800cc36: 9c08 ldr r4, [sp, #32]
800cc38: 9e00 ldr r6, [sp, #0]
800cc3a: 9a00 ldr r2, [sp, #0]
800cc3c: 441a add r2, r3
800cc3e: 9200 str r2, [sp, #0]
800cc40: 9a06 ldr r2, [sp, #24]
800cc42: 2101 movs r1, #1
800cc44: 441a add r2, r3
800cc46: 4648 mov r0, r9
800cc48: 9206 str r2, [sp, #24]
800cc4a: f000 fc2d bl 800d4a8 <__i2b>
800cc4e: 4605 mov r5, r0
800cc50: b166 cbz r6, 800cc6c <_dtoa_r+0x74c>
800cc52: 9b06 ldr r3, [sp, #24]
800cc54: 2b00 cmp r3, #0
800cc56: dd09 ble.n 800cc6c <_dtoa_r+0x74c>
800cc58: 42b3 cmp r3, r6
800cc5a: 9a00 ldr r2, [sp, #0]
800cc5c: bfa8 it ge
800cc5e: 4633 movge r3, r6
800cc60: 1ad2 subs r2, r2, r3
800cc62: 9200 str r2, [sp, #0]
800cc64: 9a06 ldr r2, [sp, #24]
800cc66: 1af6 subs r6, r6, r3
800cc68: 1ad3 subs r3, r2, r3
800cc6a: 9306 str r3, [sp, #24]
800cc6c: 9b08 ldr r3, [sp, #32]
800cc6e: b30b cbz r3, 800ccb4 <_dtoa_r+0x794>
800cc70: 9b09 ldr r3, [sp, #36] @ 0x24
800cc72: 2b00 cmp r3, #0
800cc74: f000 80c6 beq.w 800ce04 <_dtoa_r+0x8e4>
800cc78: 2c00 cmp r4, #0
800cc7a: f000 80c0 beq.w 800cdfe <_dtoa_r+0x8de>
800cc7e: 4629 mov r1, r5
800cc80: 4622 mov r2, r4
800cc82: 4648 mov r0, r9
800cc84: f000 fcc8 bl 800d618 <__pow5mult>
800cc88: 9a02 ldr r2, [sp, #8]
800cc8a: 4601 mov r1, r0
800cc8c: 4605 mov r5, r0
800cc8e: 4648 mov r0, r9
800cc90: f000 fc20 bl 800d4d4 <__multiply>
800cc94: 9902 ldr r1, [sp, #8]
800cc96: 4680 mov r8, r0
800cc98: 4648 mov r0, r9
800cc9a: f000 fb51 bl 800d340 <_Bfree>
800cc9e: 9b08 ldr r3, [sp, #32]
800cca0: 1b1b subs r3, r3, r4
800cca2: 9308 str r3, [sp, #32]
800cca4: f000 80b1 beq.w 800ce0a <_dtoa_r+0x8ea>
800cca8: 9a08 ldr r2, [sp, #32]
800ccaa: 4641 mov r1, r8
800ccac: 4648 mov r0, r9
800ccae: f000 fcb3 bl 800d618 <__pow5mult>
800ccb2: 9002 str r0, [sp, #8]
800ccb4: 2101 movs r1, #1
800ccb6: 4648 mov r0, r9
800ccb8: f000 fbf6 bl 800d4a8 <__i2b>
800ccbc: 9b0d ldr r3, [sp, #52] @ 0x34
800ccbe: 4604 mov r4, r0
800ccc0: 2b00 cmp r3, #0
800ccc2: f000 81d8 beq.w 800d076 <_dtoa_r+0xb56>
800ccc6: 461a mov r2, r3
800ccc8: 4601 mov r1, r0
800ccca: 4648 mov r0, r9
800cccc: f000 fca4 bl 800d618 <__pow5mult>
800ccd0: 9b07 ldr r3, [sp, #28]
800ccd2: 2b01 cmp r3, #1
800ccd4: 4604 mov r4, r0
800ccd6: f300 809f bgt.w 800ce18 <_dtoa_r+0x8f8>
800ccda: 9b04 ldr r3, [sp, #16]
800ccdc: 2b00 cmp r3, #0
800ccde: f040 8097 bne.w 800ce10 <_dtoa_r+0x8f0>
800cce2: 9b05 ldr r3, [sp, #20]
800cce4: f3c3 0313 ubfx r3, r3, #0, #20
800cce8: 2b00 cmp r3, #0
800ccea: f040 8093 bne.w 800ce14 <_dtoa_r+0x8f4>
800ccee: 9b05 ldr r3, [sp, #20]
800ccf0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
800ccf4: 0d1b lsrs r3, r3, #20
800ccf6: 051b lsls r3, r3, #20
800ccf8: b133 cbz r3, 800cd08 <_dtoa_r+0x7e8>
800ccfa: 9b00 ldr r3, [sp, #0]
800ccfc: 3301 adds r3, #1
800ccfe: 9300 str r3, [sp, #0]
800cd00: 9b06 ldr r3, [sp, #24]
800cd02: 3301 adds r3, #1
800cd04: 9306 str r3, [sp, #24]
800cd06: 2301 movs r3, #1
800cd08: 9308 str r3, [sp, #32]
800cd0a: 9b0d ldr r3, [sp, #52] @ 0x34
800cd0c: 2b00 cmp r3, #0
800cd0e: f000 81b8 beq.w 800d082 <_dtoa_r+0xb62>
800cd12: 6923 ldr r3, [r4, #16]
800cd14: eb04 0383 add.w r3, r4, r3, lsl #2
800cd18: 6918 ldr r0, [r3, #16]
800cd1a: f000 fb79 bl 800d410 <__hi0bits>
800cd1e: f1c0 0020 rsb r0, r0, #32
800cd22: 9b06 ldr r3, [sp, #24]
800cd24: 4418 add r0, r3
800cd26: f010 001f ands.w r0, r0, #31
800cd2a: f000 8082 beq.w 800ce32 <_dtoa_r+0x912>
800cd2e: f1c0 0320 rsb r3, r0, #32
800cd32: 2b04 cmp r3, #4
800cd34: dd73 ble.n 800ce1e <_dtoa_r+0x8fe>
800cd36: 9b00 ldr r3, [sp, #0]
800cd38: f1c0 001c rsb r0, r0, #28
800cd3c: 4403 add r3, r0
800cd3e: 9300 str r3, [sp, #0]
800cd40: 9b06 ldr r3, [sp, #24]
800cd42: 4403 add r3, r0
800cd44: 4406 add r6, r0
800cd46: 9306 str r3, [sp, #24]
800cd48: 9b00 ldr r3, [sp, #0]
800cd4a: 2b00 cmp r3, #0
800cd4c: dd05 ble.n 800cd5a <_dtoa_r+0x83a>
800cd4e: 9902 ldr r1, [sp, #8]
800cd50: 461a mov r2, r3
800cd52: 4648 mov r0, r9
800cd54: f000 fcba bl 800d6cc <__lshift>
800cd58: 9002 str r0, [sp, #8]
800cd5a: 9b06 ldr r3, [sp, #24]
800cd5c: 2b00 cmp r3, #0
800cd5e: dd05 ble.n 800cd6c <_dtoa_r+0x84c>
800cd60: 4621 mov r1, r4
800cd62: 461a mov r2, r3
800cd64: 4648 mov r0, r9
800cd66: f000 fcb1 bl 800d6cc <__lshift>
800cd6a: 4604 mov r4, r0
800cd6c: 9b10 ldr r3, [sp, #64] @ 0x40
800cd6e: 2b00 cmp r3, #0
800cd70: d061 beq.n 800ce36 <_dtoa_r+0x916>
800cd72: 9802 ldr r0, [sp, #8]
800cd74: 4621 mov r1, r4
800cd76: f000 fd15 bl 800d7a4 <__mcmp>
800cd7a: 2800 cmp r0, #0
800cd7c: da5b bge.n 800ce36 <_dtoa_r+0x916>
800cd7e: 2300 movs r3, #0
800cd80: 9902 ldr r1, [sp, #8]
800cd82: 220a movs r2, #10
800cd84: 4648 mov r0, r9
800cd86: f000 fafd bl 800d384 <__multadd>
800cd8a: 9b09 ldr r3, [sp, #36] @ 0x24
800cd8c: 9002 str r0, [sp, #8]
800cd8e: f107 38ff add.w r8, r7, #4294967295
800cd92: 2b00 cmp r3, #0
800cd94: f000 8177 beq.w 800d086 <_dtoa_r+0xb66>
800cd98: 4629 mov r1, r5
800cd9a: 2300 movs r3, #0
800cd9c: 220a movs r2, #10
800cd9e: 4648 mov r0, r9
800cda0: f000 faf0 bl 800d384 <__multadd>
800cda4: f1bb 0f00 cmp.w fp, #0
800cda8: 4605 mov r5, r0
800cdaa: dc6f bgt.n 800ce8c <_dtoa_r+0x96c>
800cdac: 9b07 ldr r3, [sp, #28]
800cdae: 2b02 cmp r3, #2
800cdb0: dc49 bgt.n 800ce46 <_dtoa_r+0x926>
800cdb2: e06b b.n 800ce8c <_dtoa_r+0x96c>
800cdb4: 9b14 ldr r3, [sp, #80] @ 0x50
800cdb6: f1c3 0336 rsb r3, r3, #54 @ 0x36
800cdba: e73c b.n 800cc36 <_dtoa_r+0x716>
800cdbc: 3fe00000 .word 0x3fe00000
800cdc0: 40240000 .word 0x40240000
800cdc4: 9b03 ldr r3, [sp, #12]
800cdc6: 1e5c subs r4, r3, #1
800cdc8: 9b08 ldr r3, [sp, #32]
800cdca: 42a3 cmp r3, r4
800cdcc: db09 blt.n 800cde2 <_dtoa_r+0x8c2>
800cdce: 1b1c subs r4, r3, r4
800cdd0: 9b03 ldr r3, [sp, #12]
800cdd2: 2b00 cmp r3, #0
800cdd4: f6bf af30 bge.w 800cc38 <_dtoa_r+0x718>
800cdd8: 9b00 ldr r3, [sp, #0]
800cdda: 9a03 ldr r2, [sp, #12]
800cddc: 1a9e subs r6, r3, r2
800cdde: 2300 movs r3, #0
800cde0: e72b b.n 800cc3a <_dtoa_r+0x71a>
800cde2: 9b08 ldr r3, [sp, #32]
800cde4: 9a0d ldr r2, [sp, #52] @ 0x34
800cde6: 9408 str r4, [sp, #32]
800cde8: 1ae3 subs r3, r4, r3
800cdea: 441a add r2, r3
800cdec: 9e00 ldr r6, [sp, #0]
800cdee: 9b03 ldr r3, [sp, #12]
800cdf0: 920d str r2, [sp, #52] @ 0x34
800cdf2: 2400 movs r4, #0
800cdf4: e721 b.n 800cc3a <_dtoa_r+0x71a>
800cdf6: 9c08 ldr r4, [sp, #32]
800cdf8: 9e00 ldr r6, [sp, #0]
800cdfa: 9d09 ldr r5, [sp, #36] @ 0x24
800cdfc: e728 b.n 800cc50 <_dtoa_r+0x730>
800cdfe: f8dd 8008 ldr.w r8, [sp, #8]
800ce02: e751 b.n 800cca8 <_dtoa_r+0x788>
800ce04: 9a08 ldr r2, [sp, #32]
800ce06: 9902 ldr r1, [sp, #8]
800ce08: e750 b.n 800ccac <_dtoa_r+0x78c>
800ce0a: f8cd 8008 str.w r8, [sp, #8]
800ce0e: e751 b.n 800ccb4 <_dtoa_r+0x794>
800ce10: 2300 movs r3, #0
800ce12: e779 b.n 800cd08 <_dtoa_r+0x7e8>
800ce14: 9b04 ldr r3, [sp, #16]
800ce16: e777 b.n 800cd08 <_dtoa_r+0x7e8>
800ce18: 2300 movs r3, #0
800ce1a: 9308 str r3, [sp, #32]
800ce1c: e779 b.n 800cd12 <_dtoa_r+0x7f2>
800ce1e: d093 beq.n 800cd48 <_dtoa_r+0x828>
800ce20: 9a00 ldr r2, [sp, #0]
800ce22: 331c adds r3, #28
800ce24: 441a add r2, r3
800ce26: 9200 str r2, [sp, #0]
800ce28: 9a06 ldr r2, [sp, #24]
800ce2a: 441a add r2, r3
800ce2c: 441e add r6, r3
800ce2e: 9206 str r2, [sp, #24]
800ce30: e78a b.n 800cd48 <_dtoa_r+0x828>
800ce32: 4603 mov r3, r0
800ce34: e7f4 b.n 800ce20 <_dtoa_r+0x900>
800ce36: 9b03 ldr r3, [sp, #12]
800ce38: 2b00 cmp r3, #0
800ce3a: 46b8 mov r8, r7
800ce3c: dc20 bgt.n 800ce80 <_dtoa_r+0x960>
800ce3e: 469b mov fp, r3
800ce40: 9b07 ldr r3, [sp, #28]
800ce42: 2b02 cmp r3, #2
800ce44: dd1e ble.n 800ce84 <_dtoa_r+0x964>
800ce46: f1bb 0f00 cmp.w fp, #0
800ce4a: f47f adb1 bne.w 800c9b0 <_dtoa_r+0x490>
800ce4e: 4621 mov r1, r4
800ce50: 465b mov r3, fp
800ce52: 2205 movs r2, #5
800ce54: 4648 mov r0, r9
800ce56: f000 fa95 bl 800d384 <__multadd>
800ce5a: 4601 mov r1, r0
800ce5c: 4604 mov r4, r0
800ce5e: 9802 ldr r0, [sp, #8]
800ce60: f000 fca0 bl 800d7a4 <__mcmp>
800ce64: 2800 cmp r0, #0
800ce66: f77f ada3 ble.w 800c9b0 <_dtoa_r+0x490>
800ce6a: 4656 mov r6, sl
800ce6c: 2331 movs r3, #49 @ 0x31
800ce6e: f806 3b01 strb.w r3, [r6], #1
800ce72: f108 0801 add.w r8, r8, #1
800ce76: e59f b.n 800c9b8 <_dtoa_r+0x498>
800ce78: 9c03 ldr r4, [sp, #12]
800ce7a: 46b8 mov r8, r7
800ce7c: 4625 mov r5, r4
800ce7e: e7f4 b.n 800ce6a <_dtoa_r+0x94a>
800ce80: f8dd b00c ldr.w fp, [sp, #12]
800ce84: 9b09 ldr r3, [sp, #36] @ 0x24
800ce86: 2b00 cmp r3, #0
800ce88: f000 8101 beq.w 800d08e <_dtoa_r+0xb6e>
800ce8c: 2e00 cmp r6, #0
800ce8e: dd05 ble.n 800ce9c <_dtoa_r+0x97c>
800ce90: 4629 mov r1, r5
800ce92: 4632 mov r2, r6
800ce94: 4648 mov r0, r9
800ce96: f000 fc19 bl 800d6cc <__lshift>
800ce9a: 4605 mov r5, r0
800ce9c: 9b08 ldr r3, [sp, #32]
800ce9e: 2b00 cmp r3, #0
800cea0: d05c beq.n 800cf5c <_dtoa_r+0xa3c>
800cea2: 6869 ldr r1, [r5, #4]
800cea4: 4648 mov r0, r9
800cea6: f000 fa0b bl 800d2c0 <_Balloc>
800ceaa: 4606 mov r6, r0
800ceac: b928 cbnz r0, 800ceba <_dtoa_r+0x99a>
800ceae: 4b82 ldr r3, [pc, #520] @ (800d0b8 <_dtoa_r+0xb98>)
800ceb0: 4602 mov r2, r0
800ceb2: f240 21ef movw r1, #751 @ 0x2ef
800ceb6: f7ff bb4a b.w 800c54e <_dtoa_r+0x2e>
800ceba: 692a ldr r2, [r5, #16]
800cebc: 3202 adds r2, #2
800cebe: 0092 lsls r2, r2, #2
800cec0: f105 010c add.w r1, r5, #12
800cec4: 300c adds r0, #12
800cec6: f000 fe31 bl 800db2c <memcpy>
800ceca: 2201 movs r2, #1
800cecc: 4631 mov r1, r6
800cece: 4648 mov r0, r9
800ced0: f000 fbfc bl 800d6cc <__lshift>
800ced4: f10a 0301 add.w r3, sl, #1
800ced8: 9300 str r3, [sp, #0]
800ceda: eb0a 030b add.w r3, sl, fp
800cede: 9308 str r3, [sp, #32]
800cee0: 9b04 ldr r3, [sp, #16]
800cee2: f003 0301 and.w r3, r3, #1
800cee6: 462f mov r7, r5
800cee8: 9306 str r3, [sp, #24]
800ceea: 4605 mov r5, r0
800ceec: 9b00 ldr r3, [sp, #0]
800ceee: 9802 ldr r0, [sp, #8]
800cef0: 4621 mov r1, r4
800cef2: f103 3bff add.w fp, r3, #4294967295
800cef6: f7ff fa8a bl 800c40e <quorem>
800cefa: 4603 mov r3, r0
800cefc: 3330 adds r3, #48 @ 0x30
800cefe: 9003 str r0, [sp, #12]
800cf00: 4639 mov r1, r7
800cf02: 9802 ldr r0, [sp, #8]
800cf04: 9309 str r3, [sp, #36] @ 0x24
800cf06: f000 fc4d bl 800d7a4 <__mcmp>
800cf0a: 462a mov r2, r5
800cf0c: 9004 str r0, [sp, #16]
800cf0e: 4621 mov r1, r4
800cf10: 4648 mov r0, r9
800cf12: f000 fc63 bl 800d7dc <__mdiff>
800cf16: 68c2 ldr r2, [r0, #12]
800cf18: 9b09 ldr r3, [sp, #36] @ 0x24
800cf1a: 4606 mov r6, r0
800cf1c: bb02 cbnz r2, 800cf60 <_dtoa_r+0xa40>
800cf1e: 4601 mov r1, r0
800cf20: 9802 ldr r0, [sp, #8]
800cf22: f000 fc3f bl 800d7a4 <__mcmp>
800cf26: 9b09 ldr r3, [sp, #36] @ 0x24
800cf28: 4602 mov r2, r0
800cf2a: 4631 mov r1, r6
800cf2c: 4648 mov r0, r9
800cf2e: 920c str r2, [sp, #48] @ 0x30
800cf30: 9309 str r3, [sp, #36] @ 0x24
800cf32: f000 fa05 bl 800d340 <_Bfree>
800cf36: 9b07 ldr r3, [sp, #28]
800cf38: 9a0c ldr r2, [sp, #48] @ 0x30
800cf3a: 9e00 ldr r6, [sp, #0]
800cf3c: ea42 0103 orr.w r1, r2, r3
800cf40: 9b06 ldr r3, [sp, #24]
800cf42: 4319 orrs r1, r3
800cf44: 9b09 ldr r3, [sp, #36] @ 0x24
800cf46: d10d bne.n 800cf64 <_dtoa_r+0xa44>
800cf48: 2b39 cmp r3, #57 @ 0x39
800cf4a: d027 beq.n 800cf9c <_dtoa_r+0xa7c>
800cf4c: 9a04 ldr r2, [sp, #16]
800cf4e: 2a00 cmp r2, #0
800cf50: dd01 ble.n 800cf56 <_dtoa_r+0xa36>
800cf52: 9b03 ldr r3, [sp, #12]
800cf54: 3331 adds r3, #49 @ 0x31
800cf56: f88b 3000 strb.w r3, [fp]
800cf5a: e52e b.n 800c9ba <_dtoa_r+0x49a>
800cf5c: 4628 mov r0, r5
800cf5e: e7b9 b.n 800ced4 <_dtoa_r+0x9b4>
800cf60: 2201 movs r2, #1
800cf62: e7e2 b.n 800cf2a <_dtoa_r+0xa0a>
800cf64: 9904 ldr r1, [sp, #16]
800cf66: 2900 cmp r1, #0
800cf68: db04 blt.n 800cf74 <_dtoa_r+0xa54>
800cf6a: 9807 ldr r0, [sp, #28]
800cf6c: 4301 orrs r1, r0
800cf6e: 9806 ldr r0, [sp, #24]
800cf70: 4301 orrs r1, r0
800cf72: d120 bne.n 800cfb6 <_dtoa_r+0xa96>
800cf74: 2a00 cmp r2, #0
800cf76: ddee ble.n 800cf56 <_dtoa_r+0xa36>
800cf78: 9902 ldr r1, [sp, #8]
800cf7a: 9300 str r3, [sp, #0]
800cf7c: 2201 movs r2, #1
800cf7e: 4648 mov r0, r9
800cf80: f000 fba4 bl 800d6cc <__lshift>
800cf84: 4621 mov r1, r4
800cf86: 9002 str r0, [sp, #8]
800cf88: f000 fc0c bl 800d7a4 <__mcmp>
800cf8c: 2800 cmp r0, #0
800cf8e: 9b00 ldr r3, [sp, #0]
800cf90: dc02 bgt.n 800cf98 <_dtoa_r+0xa78>
800cf92: d1e0 bne.n 800cf56 <_dtoa_r+0xa36>
800cf94: 07da lsls r2, r3, #31
800cf96: d5de bpl.n 800cf56 <_dtoa_r+0xa36>
800cf98: 2b39 cmp r3, #57 @ 0x39
800cf9a: d1da bne.n 800cf52 <_dtoa_r+0xa32>
800cf9c: 2339 movs r3, #57 @ 0x39
800cf9e: f88b 3000 strb.w r3, [fp]
800cfa2: 4633 mov r3, r6
800cfa4: 461e mov r6, r3
800cfa6: 3b01 subs r3, #1
800cfa8: f816 2c01 ldrb.w r2, [r6, #-1]
800cfac: 2a39 cmp r2, #57 @ 0x39
800cfae: d04e beq.n 800d04e <_dtoa_r+0xb2e>
800cfb0: 3201 adds r2, #1
800cfb2: 701a strb r2, [r3, #0]
800cfb4: e501 b.n 800c9ba <_dtoa_r+0x49a>
800cfb6: 2a00 cmp r2, #0
800cfb8: dd03 ble.n 800cfc2 <_dtoa_r+0xaa2>
800cfba: 2b39 cmp r3, #57 @ 0x39
800cfbc: d0ee beq.n 800cf9c <_dtoa_r+0xa7c>
800cfbe: 3301 adds r3, #1
800cfc0: e7c9 b.n 800cf56 <_dtoa_r+0xa36>
800cfc2: 9a00 ldr r2, [sp, #0]
800cfc4: 9908 ldr r1, [sp, #32]
800cfc6: f802 3c01 strb.w r3, [r2, #-1]
800cfca: 428a cmp r2, r1
800cfcc: d028 beq.n 800d020 <_dtoa_r+0xb00>
800cfce: 9902 ldr r1, [sp, #8]
800cfd0: 2300 movs r3, #0
800cfd2: 220a movs r2, #10
800cfd4: 4648 mov r0, r9
800cfd6: f000 f9d5 bl 800d384 <__multadd>
800cfda: 42af cmp r7, r5
800cfdc: 9002 str r0, [sp, #8]
800cfde: f04f 0300 mov.w r3, #0
800cfe2: f04f 020a mov.w r2, #10
800cfe6: 4639 mov r1, r7
800cfe8: 4648 mov r0, r9
800cfea: d107 bne.n 800cffc <_dtoa_r+0xadc>
800cfec: f000 f9ca bl 800d384 <__multadd>
800cff0: 4607 mov r7, r0
800cff2: 4605 mov r5, r0
800cff4: 9b00 ldr r3, [sp, #0]
800cff6: 3301 adds r3, #1
800cff8: 9300 str r3, [sp, #0]
800cffa: e777 b.n 800ceec <_dtoa_r+0x9cc>
800cffc: f000 f9c2 bl 800d384 <__multadd>
800d000: 4629 mov r1, r5
800d002: 4607 mov r7, r0
800d004: 2300 movs r3, #0
800d006: 220a movs r2, #10
800d008: 4648 mov r0, r9
800d00a: f000 f9bb bl 800d384 <__multadd>
800d00e: 4605 mov r5, r0
800d010: e7f0 b.n 800cff4 <_dtoa_r+0xad4>
800d012: f1bb 0f00 cmp.w fp, #0
800d016: bfcc ite gt
800d018: 465e movgt r6, fp
800d01a: 2601 movle r6, #1
800d01c: 4456 add r6, sl
800d01e: 2700 movs r7, #0
800d020: 9902 ldr r1, [sp, #8]
800d022: 9300 str r3, [sp, #0]
800d024: 2201 movs r2, #1
800d026: 4648 mov r0, r9
800d028: f000 fb50 bl 800d6cc <__lshift>
800d02c: 4621 mov r1, r4
800d02e: 9002 str r0, [sp, #8]
800d030: f000 fbb8 bl 800d7a4 <__mcmp>
800d034: 2800 cmp r0, #0
800d036: dcb4 bgt.n 800cfa2 <_dtoa_r+0xa82>
800d038: d102 bne.n 800d040 <_dtoa_r+0xb20>
800d03a: 9b00 ldr r3, [sp, #0]
800d03c: 07db lsls r3, r3, #31
800d03e: d4b0 bmi.n 800cfa2 <_dtoa_r+0xa82>
800d040: 4633 mov r3, r6
800d042: 461e mov r6, r3
800d044: f813 2d01 ldrb.w r2, [r3, #-1]!
800d048: 2a30 cmp r2, #48 @ 0x30
800d04a: d0fa beq.n 800d042 <_dtoa_r+0xb22>
800d04c: e4b5 b.n 800c9ba <_dtoa_r+0x49a>
800d04e: 459a cmp sl, r3
800d050: d1a8 bne.n 800cfa4 <_dtoa_r+0xa84>
800d052: 2331 movs r3, #49 @ 0x31
800d054: f108 0801 add.w r8, r8, #1
800d058: f88a 3000 strb.w r3, [sl]
800d05c: e4ad b.n 800c9ba <_dtoa_r+0x49a>
800d05e: 9b21 ldr r3, [sp, #132] @ 0x84
800d060: f8df a058 ldr.w sl, [pc, #88] @ 800d0bc <_dtoa_r+0xb9c>
800d064: b11b cbz r3, 800d06e <_dtoa_r+0xb4e>
800d066: f10a 0308 add.w r3, sl, #8
800d06a: 9a21 ldr r2, [sp, #132] @ 0x84
800d06c: 6013 str r3, [r2, #0]
800d06e: 4650 mov r0, sl
800d070: b017 add sp, #92 @ 0x5c
800d072: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800d076: 9b07 ldr r3, [sp, #28]
800d078: 2b01 cmp r3, #1
800d07a: f77f ae2e ble.w 800ccda <_dtoa_r+0x7ba>
800d07e: 9b0d ldr r3, [sp, #52] @ 0x34
800d080: 9308 str r3, [sp, #32]
800d082: 2001 movs r0, #1
800d084: e64d b.n 800cd22 <_dtoa_r+0x802>
800d086: f1bb 0f00 cmp.w fp, #0
800d08a: f77f aed9 ble.w 800ce40 <_dtoa_r+0x920>
800d08e: 4656 mov r6, sl
800d090: 9802 ldr r0, [sp, #8]
800d092: 4621 mov r1, r4
800d094: f7ff f9bb bl 800c40e <quorem>
800d098: f100 0330 add.w r3, r0, #48 @ 0x30
800d09c: f806 3b01 strb.w r3, [r6], #1
800d0a0: eba6 020a sub.w r2, r6, sl
800d0a4: 4593 cmp fp, r2
800d0a6: ddb4 ble.n 800d012 <_dtoa_r+0xaf2>
800d0a8: 9902 ldr r1, [sp, #8]
800d0aa: 2300 movs r3, #0
800d0ac: 220a movs r2, #10
800d0ae: 4648 mov r0, r9
800d0b0: f000 f968 bl 800d384 <__multadd>
800d0b4: 9002 str r0, [sp, #8]
800d0b6: e7eb b.n 800d090 <_dtoa_r+0xb70>
800d0b8: 0800e2b8 .word 0x0800e2b8
800d0bc: 0800e23c .word 0x0800e23c
0800d0c0 <_free_r>:
800d0c0: b538 push {r3, r4, r5, lr}
800d0c2: 4605 mov r5, r0
800d0c4: 2900 cmp r1, #0
800d0c6: d041 beq.n 800d14c <_free_r+0x8c>
800d0c8: f851 3c04 ldr.w r3, [r1, #-4]
800d0cc: 1f0c subs r4, r1, #4
800d0ce: 2b00 cmp r3, #0
800d0d0: bfb8 it lt
800d0d2: 18e4 addlt r4, r4, r3
800d0d4: f000 f8e8 bl 800d2a8 <__malloc_lock>
800d0d8: 4a1d ldr r2, [pc, #116] @ (800d150 <_free_r+0x90>)
800d0da: 6813 ldr r3, [r2, #0]
800d0dc: b933 cbnz r3, 800d0ec <_free_r+0x2c>
800d0de: 6063 str r3, [r4, #4]
800d0e0: 6014 str r4, [r2, #0]
800d0e2: 4628 mov r0, r5
800d0e4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
800d0e8: f000 b8e4 b.w 800d2b4 <__malloc_unlock>
800d0ec: 42a3 cmp r3, r4
800d0ee: d908 bls.n 800d102 <_free_r+0x42>
800d0f0: 6820 ldr r0, [r4, #0]
800d0f2: 1821 adds r1, r4, r0
800d0f4: 428b cmp r3, r1
800d0f6: bf01 itttt eq
800d0f8: 6819 ldreq r1, [r3, #0]
800d0fa: 685b ldreq r3, [r3, #4]
800d0fc: 1809 addeq r1, r1, r0
800d0fe: 6021 streq r1, [r4, #0]
800d100: e7ed b.n 800d0de <_free_r+0x1e>
800d102: 461a mov r2, r3
800d104: 685b ldr r3, [r3, #4]
800d106: b10b cbz r3, 800d10c <_free_r+0x4c>
800d108: 42a3 cmp r3, r4
800d10a: d9fa bls.n 800d102 <_free_r+0x42>
800d10c: 6811 ldr r1, [r2, #0]
800d10e: 1850 adds r0, r2, r1
800d110: 42a0 cmp r0, r4
800d112: d10b bne.n 800d12c <_free_r+0x6c>
800d114: 6820 ldr r0, [r4, #0]
800d116: 4401 add r1, r0
800d118: 1850 adds r0, r2, r1
800d11a: 4283 cmp r3, r0
800d11c: 6011 str r1, [r2, #0]
800d11e: d1e0 bne.n 800d0e2 <_free_r+0x22>
800d120: 6818 ldr r0, [r3, #0]
800d122: 685b ldr r3, [r3, #4]
800d124: 6053 str r3, [r2, #4]
800d126: 4408 add r0, r1
800d128: 6010 str r0, [r2, #0]
800d12a: e7da b.n 800d0e2 <_free_r+0x22>
800d12c: d902 bls.n 800d134 <_free_r+0x74>
800d12e: 230c movs r3, #12
800d130: 602b str r3, [r5, #0]
800d132: e7d6 b.n 800d0e2 <_free_r+0x22>
800d134: 6820 ldr r0, [r4, #0]
800d136: 1821 adds r1, r4, r0
800d138: 428b cmp r3, r1
800d13a: bf04 itt eq
800d13c: 6819 ldreq r1, [r3, #0]
800d13e: 685b ldreq r3, [r3, #4]
800d140: 6063 str r3, [r4, #4]
800d142: bf04 itt eq
800d144: 1809 addeq r1, r1, r0
800d146: 6021 streq r1, [r4, #0]
800d148: 6054 str r4, [r2, #4]
800d14a: e7ca b.n 800d0e2 <_free_r+0x22>
800d14c: bd38 pop {r3, r4, r5, pc}
800d14e: bf00 nop
800d150: 200011ec .word 0x200011ec
0800d154 <malloc>:
800d154: 4b02 ldr r3, [pc, #8] @ (800d160 <malloc+0xc>)
800d156: 4601 mov r1, r0
800d158: 6818 ldr r0, [r3, #0]
800d15a: f000 b825 b.w 800d1a8 <_malloc_r>
800d15e: bf00 nop
800d160: 20000144 .word 0x20000144
0800d164 <sbrk_aligned>:
800d164: b570 push {r4, r5, r6, lr}
800d166: 4e0f ldr r6, [pc, #60] @ (800d1a4 <sbrk_aligned+0x40>)
800d168: 460c mov r4, r1
800d16a: 6831 ldr r1, [r6, #0]
800d16c: 4605 mov r5, r0
800d16e: b911 cbnz r1, 800d176 <sbrk_aligned+0x12>
800d170: f000 fccc bl 800db0c <_sbrk_r>
800d174: 6030 str r0, [r6, #0]
800d176: 4621 mov r1, r4
800d178: 4628 mov r0, r5
800d17a: f000 fcc7 bl 800db0c <_sbrk_r>
800d17e: 1c43 adds r3, r0, #1
800d180: d103 bne.n 800d18a <sbrk_aligned+0x26>
800d182: f04f 34ff mov.w r4, #4294967295
800d186: 4620 mov r0, r4
800d188: bd70 pop {r4, r5, r6, pc}
800d18a: 1cc4 adds r4, r0, #3
800d18c: f024 0403 bic.w r4, r4, #3
800d190: 42a0 cmp r0, r4
800d192: d0f8 beq.n 800d186 <sbrk_aligned+0x22>
800d194: 1a21 subs r1, r4, r0
800d196: 4628 mov r0, r5
800d198: f000 fcb8 bl 800db0c <_sbrk_r>
800d19c: 3001 adds r0, #1
800d19e: d1f2 bne.n 800d186 <sbrk_aligned+0x22>
800d1a0: e7ef b.n 800d182 <sbrk_aligned+0x1e>
800d1a2: bf00 nop
800d1a4: 200011e8 .word 0x200011e8
0800d1a8 <_malloc_r>:
800d1a8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
800d1ac: 1ccd adds r5, r1, #3
800d1ae: f025 0503 bic.w r5, r5, #3
800d1b2: 3508 adds r5, #8
800d1b4: 2d0c cmp r5, #12
800d1b6: bf38 it cc
800d1b8: 250c movcc r5, #12
800d1ba: 2d00 cmp r5, #0
800d1bc: 4606 mov r6, r0
800d1be: db01 blt.n 800d1c4 <_malloc_r+0x1c>
800d1c0: 42a9 cmp r1, r5
800d1c2: d904 bls.n 800d1ce <_malloc_r+0x26>
800d1c4: 230c movs r3, #12
800d1c6: 6033 str r3, [r6, #0]
800d1c8: 2000 movs r0, #0
800d1ca: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
800d1ce: f8df 80d4 ldr.w r8, [pc, #212] @ 800d2a4 <_malloc_r+0xfc>
800d1d2: f000 f869 bl 800d2a8 <__malloc_lock>
800d1d6: f8d8 3000 ldr.w r3, [r8]
800d1da: 461c mov r4, r3
800d1dc: bb44 cbnz r4, 800d230 <_malloc_r+0x88>
800d1de: 4629 mov r1, r5
800d1e0: 4630 mov r0, r6
800d1e2: f7ff ffbf bl 800d164 <sbrk_aligned>
800d1e6: 1c43 adds r3, r0, #1
800d1e8: 4604 mov r4, r0
800d1ea: d158 bne.n 800d29e <_malloc_r+0xf6>
800d1ec: f8d8 4000 ldr.w r4, [r8]
800d1f0: 4627 mov r7, r4
800d1f2: 2f00 cmp r7, #0
800d1f4: d143 bne.n 800d27e <_malloc_r+0xd6>
800d1f6: 2c00 cmp r4, #0
800d1f8: d04b beq.n 800d292 <_malloc_r+0xea>
800d1fa: 6823 ldr r3, [r4, #0]
800d1fc: 4639 mov r1, r7
800d1fe: 4630 mov r0, r6
800d200: eb04 0903 add.w r9, r4, r3
800d204: f000 fc82 bl 800db0c <_sbrk_r>
800d208: 4581 cmp r9, r0
800d20a: d142 bne.n 800d292 <_malloc_r+0xea>
800d20c: 6821 ldr r1, [r4, #0]
800d20e: 1a6d subs r5, r5, r1
800d210: 4629 mov r1, r5
800d212: 4630 mov r0, r6
800d214: f7ff ffa6 bl 800d164 <sbrk_aligned>
800d218: 3001 adds r0, #1
800d21a: d03a beq.n 800d292 <_malloc_r+0xea>
800d21c: 6823 ldr r3, [r4, #0]
800d21e: 442b add r3, r5
800d220: 6023 str r3, [r4, #0]
800d222: f8d8 3000 ldr.w r3, [r8]
800d226: 685a ldr r2, [r3, #4]
800d228: bb62 cbnz r2, 800d284 <_malloc_r+0xdc>
800d22a: f8c8 7000 str.w r7, [r8]
800d22e: e00f b.n 800d250 <_malloc_r+0xa8>
800d230: 6822 ldr r2, [r4, #0]
800d232: 1b52 subs r2, r2, r5
800d234: d420 bmi.n 800d278 <_malloc_r+0xd0>
800d236: 2a0b cmp r2, #11
800d238: d917 bls.n 800d26a <_malloc_r+0xc2>
800d23a: 1961 adds r1, r4, r5
800d23c: 42a3 cmp r3, r4
800d23e: 6025 str r5, [r4, #0]
800d240: bf18 it ne
800d242: 6059 strne r1, [r3, #4]
800d244: 6863 ldr r3, [r4, #4]
800d246: bf08 it eq
800d248: f8c8 1000 streq.w r1, [r8]
800d24c: 5162 str r2, [r4, r5]
800d24e: 604b str r3, [r1, #4]
800d250: 4630 mov r0, r6
800d252: f000 f82f bl 800d2b4 <__malloc_unlock>
800d256: f104 000b add.w r0, r4, #11
800d25a: 1d23 adds r3, r4, #4
800d25c: f020 0007 bic.w r0, r0, #7
800d260: 1ac2 subs r2, r0, r3
800d262: bf1c itt ne
800d264: 1a1b subne r3, r3, r0
800d266: 50a3 strne r3, [r4, r2]
800d268: e7af b.n 800d1ca <_malloc_r+0x22>
800d26a: 6862 ldr r2, [r4, #4]
800d26c: 42a3 cmp r3, r4
800d26e: bf0c ite eq
800d270: f8c8 2000 streq.w r2, [r8]
800d274: 605a strne r2, [r3, #4]
800d276: e7eb b.n 800d250 <_malloc_r+0xa8>
800d278: 4623 mov r3, r4
800d27a: 6864 ldr r4, [r4, #4]
800d27c: e7ae b.n 800d1dc <_malloc_r+0x34>
800d27e: 463c mov r4, r7
800d280: 687f ldr r7, [r7, #4]
800d282: e7b6 b.n 800d1f2 <_malloc_r+0x4a>
800d284: 461a mov r2, r3
800d286: 685b ldr r3, [r3, #4]
800d288: 42a3 cmp r3, r4
800d28a: d1fb bne.n 800d284 <_malloc_r+0xdc>
800d28c: 2300 movs r3, #0
800d28e: 6053 str r3, [r2, #4]
800d290: e7de b.n 800d250 <_malloc_r+0xa8>
800d292: 230c movs r3, #12
800d294: 6033 str r3, [r6, #0]
800d296: 4630 mov r0, r6
800d298: f000 f80c bl 800d2b4 <__malloc_unlock>
800d29c: e794 b.n 800d1c8 <_malloc_r+0x20>
800d29e: 6005 str r5, [r0, #0]
800d2a0: e7d6 b.n 800d250 <_malloc_r+0xa8>
800d2a2: bf00 nop
800d2a4: 200011ec .word 0x200011ec
0800d2a8 <__malloc_lock>:
800d2a8: 4801 ldr r0, [pc, #4] @ (800d2b0 <__malloc_lock+0x8>)
800d2aa: f7ff b8ae b.w 800c40a <__retarget_lock_acquire_recursive>
800d2ae: bf00 nop
800d2b0: 200011e4 .word 0x200011e4
0800d2b4 <__malloc_unlock>:
800d2b4: 4801 ldr r0, [pc, #4] @ (800d2bc <__malloc_unlock+0x8>)
800d2b6: f7ff b8a9 b.w 800c40c <__retarget_lock_release_recursive>
800d2ba: bf00 nop
800d2bc: 200011e4 .word 0x200011e4
0800d2c0 <_Balloc>:
800d2c0: b570 push {r4, r5, r6, lr}
800d2c2: 69c6 ldr r6, [r0, #28]
800d2c4: 4604 mov r4, r0
800d2c6: 460d mov r5, r1
800d2c8: b976 cbnz r6, 800d2e8 <_Balloc+0x28>
800d2ca: 2010 movs r0, #16
800d2cc: f7ff ff42 bl 800d154 <malloc>
800d2d0: 4602 mov r2, r0
800d2d2: 61e0 str r0, [r4, #28]
800d2d4: b920 cbnz r0, 800d2e0 <_Balloc+0x20>
800d2d6: 4b18 ldr r3, [pc, #96] @ (800d338 <_Balloc+0x78>)
800d2d8: 4818 ldr r0, [pc, #96] @ (800d33c <_Balloc+0x7c>)
800d2da: 216b movs r1, #107 @ 0x6b
800d2dc: f000 fc34 bl 800db48 <__assert_func>
800d2e0: e9c0 6601 strd r6, r6, [r0, #4]
800d2e4: 6006 str r6, [r0, #0]
800d2e6: 60c6 str r6, [r0, #12]
800d2e8: 69e6 ldr r6, [r4, #28]
800d2ea: 68f3 ldr r3, [r6, #12]
800d2ec: b183 cbz r3, 800d310 <_Balloc+0x50>
800d2ee: 69e3 ldr r3, [r4, #28]
800d2f0: 68db ldr r3, [r3, #12]
800d2f2: f853 0025 ldr.w r0, [r3, r5, lsl #2]
800d2f6: b9b8 cbnz r0, 800d328 <_Balloc+0x68>
800d2f8: 2101 movs r1, #1
800d2fa: fa01 f605 lsl.w r6, r1, r5
800d2fe: 1d72 adds r2, r6, #5
800d300: 0092 lsls r2, r2, #2
800d302: 4620 mov r0, r4
800d304: f000 fc3e bl 800db84 <_calloc_r>
800d308: b160 cbz r0, 800d324 <_Balloc+0x64>
800d30a: e9c0 5601 strd r5, r6, [r0, #4]
800d30e: e00e b.n 800d32e <_Balloc+0x6e>
800d310: 2221 movs r2, #33 @ 0x21
800d312: 2104 movs r1, #4
800d314: 4620 mov r0, r4
800d316: f000 fc35 bl 800db84 <_calloc_r>
800d31a: 69e3 ldr r3, [r4, #28]
800d31c: 60f0 str r0, [r6, #12]
800d31e: 68db ldr r3, [r3, #12]
800d320: 2b00 cmp r3, #0
800d322: d1e4 bne.n 800d2ee <_Balloc+0x2e>
800d324: 2000 movs r0, #0
800d326: bd70 pop {r4, r5, r6, pc}
800d328: 6802 ldr r2, [r0, #0]
800d32a: f843 2025 str.w r2, [r3, r5, lsl #2]
800d32e: 2300 movs r3, #0
800d330: e9c0 3303 strd r3, r3, [r0, #12]
800d334: e7f7 b.n 800d326 <_Balloc+0x66>
800d336: bf00 nop
800d338: 0800e249 .word 0x0800e249
800d33c: 0800e2c9 .word 0x0800e2c9
0800d340 <_Bfree>:
800d340: b570 push {r4, r5, r6, lr}
800d342: 69c6 ldr r6, [r0, #28]
800d344: 4605 mov r5, r0
800d346: 460c mov r4, r1
800d348: b976 cbnz r6, 800d368 <_Bfree+0x28>
800d34a: 2010 movs r0, #16
800d34c: f7ff ff02 bl 800d154 <malloc>
800d350: 4602 mov r2, r0
800d352: 61e8 str r0, [r5, #28]
800d354: b920 cbnz r0, 800d360 <_Bfree+0x20>
800d356: 4b09 ldr r3, [pc, #36] @ (800d37c <_Bfree+0x3c>)
800d358: 4809 ldr r0, [pc, #36] @ (800d380 <_Bfree+0x40>)
800d35a: 218f movs r1, #143 @ 0x8f
800d35c: f000 fbf4 bl 800db48 <__assert_func>
800d360: e9c0 6601 strd r6, r6, [r0, #4]
800d364: 6006 str r6, [r0, #0]
800d366: 60c6 str r6, [r0, #12]
800d368: b13c cbz r4, 800d37a <_Bfree+0x3a>
800d36a: 69eb ldr r3, [r5, #28]
800d36c: 6862 ldr r2, [r4, #4]
800d36e: 68db ldr r3, [r3, #12]
800d370: f853 1022 ldr.w r1, [r3, r2, lsl #2]
800d374: 6021 str r1, [r4, #0]
800d376: f843 4022 str.w r4, [r3, r2, lsl #2]
800d37a: bd70 pop {r4, r5, r6, pc}
800d37c: 0800e249 .word 0x0800e249
800d380: 0800e2c9 .word 0x0800e2c9
0800d384 <__multadd>:
800d384: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
800d388: 690d ldr r5, [r1, #16]
800d38a: 4607 mov r7, r0
800d38c: 460c mov r4, r1
800d38e: 461e mov r6, r3
800d390: f101 0c14 add.w ip, r1, #20
800d394: 2000 movs r0, #0
800d396: f8dc 3000 ldr.w r3, [ip]
800d39a: b299 uxth r1, r3
800d39c: fb02 6101 mla r1, r2, r1, r6
800d3a0: 0c1e lsrs r6, r3, #16
800d3a2: 0c0b lsrs r3, r1, #16
800d3a4: fb02 3306 mla r3, r2, r6, r3
800d3a8: b289 uxth r1, r1
800d3aa: 3001 adds r0, #1
800d3ac: eb01 4103 add.w r1, r1, r3, lsl #16
800d3b0: 4285 cmp r5, r0
800d3b2: f84c 1b04 str.w r1, [ip], #4
800d3b6: ea4f 4613 mov.w r6, r3, lsr #16
800d3ba: dcec bgt.n 800d396 <__multadd+0x12>
800d3bc: b30e cbz r6, 800d402 <__multadd+0x7e>
800d3be: 68a3 ldr r3, [r4, #8]
800d3c0: 42ab cmp r3, r5
800d3c2: dc19 bgt.n 800d3f8 <__multadd+0x74>
800d3c4: 6861 ldr r1, [r4, #4]
800d3c6: 4638 mov r0, r7
800d3c8: 3101 adds r1, #1
800d3ca: f7ff ff79 bl 800d2c0 <_Balloc>
800d3ce: 4680 mov r8, r0
800d3d0: b928 cbnz r0, 800d3de <__multadd+0x5a>
800d3d2: 4602 mov r2, r0
800d3d4: 4b0c ldr r3, [pc, #48] @ (800d408 <__multadd+0x84>)
800d3d6: 480d ldr r0, [pc, #52] @ (800d40c <__multadd+0x88>)
800d3d8: 21ba movs r1, #186 @ 0xba
800d3da: f000 fbb5 bl 800db48 <__assert_func>
800d3de: 6922 ldr r2, [r4, #16]
800d3e0: 3202 adds r2, #2
800d3e2: f104 010c add.w r1, r4, #12
800d3e6: 0092 lsls r2, r2, #2
800d3e8: 300c adds r0, #12
800d3ea: f000 fb9f bl 800db2c <memcpy>
800d3ee: 4621 mov r1, r4
800d3f0: 4638 mov r0, r7
800d3f2: f7ff ffa5 bl 800d340 <_Bfree>
800d3f6: 4644 mov r4, r8
800d3f8: eb04 0385 add.w r3, r4, r5, lsl #2
800d3fc: 3501 adds r5, #1
800d3fe: 615e str r6, [r3, #20]
800d400: 6125 str r5, [r4, #16]
800d402: 4620 mov r0, r4
800d404: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
800d408: 0800e2b8 .word 0x0800e2b8
800d40c: 0800e2c9 .word 0x0800e2c9
0800d410 <__hi0bits>:
800d410: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
800d414: 4603 mov r3, r0
800d416: bf36 itet cc
800d418: 0403 lslcc r3, r0, #16
800d41a: 2000 movcs r0, #0
800d41c: 2010 movcc r0, #16
800d41e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
800d422: bf3c itt cc
800d424: 021b lslcc r3, r3, #8
800d426: 3008 addcc r0, #8
800d428: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800d42c: bf3c itt cc
800d42e: 011b lslcc r3, r3, #4
800d430: 3004 addcc r0, #4
800d432: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800d436: bf3c itt cc
800d438: 009b lslcc r3, r3, #2
800d43a: 3002 addcc r0, #2
800d43c: 2b00 cmp r3, #0
800d43e: db05 blt.n 800d44c <__hi0bits+0x3c>
800d440: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
800d444: f100 0001 add.w r0, r0, #1
800d448: bf08 it eq
800d44a: 2020 moveq r0, #32
800d44c: 4770 bx lr
0800d44e <__lo0bits>:
800d44e: 6803 ldr r3, [r0, #0]
800d450: 4602 mov r2, r0
800d452: f013 0007 ands.w r0, r3, #7
800d456: d00b beq.n 800d470 <__lo0bits+0x22>
800d458: 07d9 lsls r1, r3, #31
800d45a: d421 bmi.n 800d4a0 <__lo0bits+0x52>
800d45c: 0798 lsls r0, r3, #30
800d45e: bf49 itett mi
800d460: 085b lsrmi r3, r3, #1
800d462: 089b lsrpl r3, r3, #2
800d464: 2001 movmi r0, #1
800d466: 6013 strmi r3, [r2, #0]
800d468: bf5c itt pl
800d46a: 6013 strpl r3, [r2, #0]
800d46c: 2002 movpl r0, #2
800d46e: 4770 bx lr
800d470: b299 uxth r1, r3
800d472: b909 cbnz r1, 800d478 <__lo0bits+0x2a>
800d474: 0c1b lsrs r3, r3, #16
800d476: 2010 movs r0, #16
800d478: b2d9 uxtb r1, r3
800d47a: b909 cbnz r1, 800d480 <__lo0bits+0x32>
800d47c: 3008 adds r0, #8
800d47e: 0a1b lsrs r3, r3, #8
800d480: 0719 lsls r1, r3, #28
800d482: bf04 itt eq
800d484: 091b lsreq r3, r3, #4
800d486: 3004 addeq r0, #4
800d488: 0799 lsls r1, r3, #30
800d48a: bf04 itt eq
800d48c: 089b lsreq r3, r3, #2
800d48e: 3002 addeq r0, #2
800d490: 07d9 lsls r1, r3, #31
800d492: d403 bmi.n 800d49c <__lo0bits+0x4e>
800d494: 085b lsrs r3, r3, #1
800d496: f100 0001 add.w r0, r0, #1
800d49a: d003 beq.n 800d4a4 <__lo0bits+0x56>
800d49c: 6013 str r3, [r2, #0]
800d49e: 4770 bx lr
800d4a0: 2000 movs r0, #0
800d4a2: 4770 bx lr
800d4a4: 2020 movs r0, #32
800d4a6: 4770 bx lr
0800d4a8 <__i2b>:
800d4a8: b510 push {r4, lr}
800d4aa: 460c mov r4, r1
800d4ac: 2101 movs r1, #1
800d4ae: f7ff ff07 bl 800d2c0 <_Balloc>
800d4b2: 4602 mov r2, r0
800d4b4: b928 cbnz r0, 800d4c2 <__i2b+0x1a>
800d4b6: 4b05 ldr r3, [pc, #20] @ (800d4cc <__i2b+0x24>)
800d4b8: 4805 ldr r0, [pc, #20] @ (800d4d0 <__i2b+0x28>)
800d4ba: f240 1145 movw r1, #325 @ 0x145
800d4be: f000 fb43 bl 800db48 <__assert_func>
800d4c2: 2301 movs r3, #1
800d4c4: 6144 str r4, [r0, #20]
800d4c6: 6103 str r3, [r0, #16]
800d4c8: bd10 pop {r4, pc}
800d4ca: bf00 nop
800d4cc: 0800e2b8 .word 0x0800e2b8
800d4d0: 0800e2c9 .word 0x0800e2c9
0800d4d4 <__multiply>:
800d4d4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800d4d8: 4617 mov r7, r2
800d4da: 690a ldr r2, [r1, #16]
800d4dc: 693b ldr r3, [r7, #16]
800d4de: 429a cmp r2, r3
800d4e0: bfa8 it ge
800d4e2: 463b movge r3, r7
800d4e4: 4689 mov r9, r1
800d4e6: bfa4 itt ge
800d4e8: 460f movge r7, r1
800d4ea: 4699 movge r9, r3
800d4ec: 693d ldr r5, [r7, #16]
800d4ee: f8d9 a010 ldr.w sl, [r9, #16]
800d4f2: 68bb ldr r3, [r7, #8]
800d4f4: 6879 ldr r1, [r7, #4]
800d4f6: eb05 060a add.w r6, r5, sl
800d4fa: 42b3 cmp r3, r6
800d4fc: b085 sub sp, #20
800d4fe: bfb8 it lt
800d500: 3101 addlt r1, #1
800d502: f7ff fedd bl 800d2c0 <_Balloc>
800d506: b930 cbnz r0, 800d516 <__multiply+0x42>
800d508: 4602 mov r2, r0
800d50a: 4b41 ldr r3, [pc, #260] @ (800d610 <__multiply+0x13c>)
800d50c: 4841 ldr r0, [pc, #260] @ (800d614 <__multiply+0x140>)
800d50e: f44f 71b1 mov.w r1, #354 @ 0x162
800d512: f000 fb19 bl 800db48 <__assert_func>
800d516: f100 0414 add.w r4, r0, #20
800d51a: eb04 0e86 add.w lr, r4, r6, lsl #2
800d51e: 4623 mov r3, r4
800d520: 2200 movs r2, #0
800d522: 4573 cmp r3, lr
800d524: d320 bcc.n 800d568 <__multiply+0x94>
800d526: f107 0814 add.w r8, r7, #20
800d52a: f109 0114 add.w r1, r9, #20
800d52e: eb08 0585 add.w r5, r8, r5, lsl #2
800d532: eb01 038a add.w r3, r1, sl, lsl #2
800d536: 9302 str r3, [sp, #8]
800d538: 1beb subs r3, r5, r7
800d53a: 3b15 subs r3, #21
800d53c: f023 0303 bic.w r3, r3, #3
800d540: 3304 adds r3, #4
800d542: 3715 adds r7, #21
800d544: 42bd cmp r5, r7
800d546: bf38 it cc
800d548: 2304 movcc r3, #4
800d54a: 9301 str r3, [sp, #4]
800d54c: 9b02 ldr r3, [sp, #8]
800d54e: 9103 str r1, [sp, #12]
800d550: 428b cmp r3, r1
800d552: d80c bhi.n 800d56e <__multiply+0x9a>
800d554: 2e00 cmp r6, #0
800d556: dd03 ble.n 800d560 <__multiply+0x8c>
800d558: f85e 3d04 ldr.w r3, [lr, #-4]!
800d55c: 2b00 cmp r3, #0
800d55e: d055 beq.n 800d60c <__multiply+0x138>
800d560: 6106 str r6, [r0, #16]
800d562: b005 add sp, #20
800d564: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800d568: f843 2b04 str.w r2, [r3], #4
800d56c: e7d9 b.n 800d522 <__multiply+0x4e>
800d56e: f8b1 a000 ldrh.w sl, [r1]
800d572: f1ba 0f00 cmp.w sl, #0
800d576: d01f beq.n 800d5b8 <__multiply+0xe4>
800d578: 46c4 mov ip, r8
800d57a: 46a1 mov r9, r4
800d57c: 2700 movs r7, #0
800d57e: f85c 2b04 ldr.w r2, [ip], #4
800d582: f8d9 3000 ldr.w r3, [r9]
800d586: fa1f fb82 uxth.w fp, r2
800d58a: b29b uxth r3, r3
800d58c: fb0a 330b mla r3, sl, fp, r3
800d590: 443b add r3, r7
800d592: f8d9 7000 ldr.w r7, [r9]
800d596: 0c12 lsrs r2, r2, #16
800d598: 0c3f lsrs r7, r7, #16
800d59a: fb0a 7202 mla r2, sl, r2, r7
800d59e: eb02 4213 add.w r2, r2, r3, lsr #16
800d5a2: b29b uxth r3, r3
800d5a4: ea43 4302 orr.w r3, r3, r2, lsl #16
800d5a8: 4565 cmp r5, ip
800d5aa: f849 3b04 str.w r3, [r9], #4
800d5ae: ea4f 4712 mov.w r7, r2, lsr #16
800d5b2: d8e4 bhi.n 800d57e <__multiply+0xaa>
800d5b4: 9b01 ldr r3, [sp, #4]
800d5b6: 50e7 str r7, [r4, r3]
800d5b8: 9b03 ldr r3, [sp, #12]
800d5ba: f8b3 9002 ldrh.w r9, [r3, #2]
800d5be: 3104 adds r1, #4
800d5c0: f1b9 0f00 cmp.w r9, #0
800d5c4: d020 beq.n 800d608 <__multiply+0x134>
800d5c6: 6823 ldr r3, [r4, #0]
800d5c8: 4647 mov r7, r8
800d5ca: 46a4 mov ip, r4
800d5cc: f04f 0a00 mov.w sl, #0
800d5d0: f8b7 b000 ldrh.w fp, [r7]
800d5d4: f8bc 2002 ldrh.w r2, [ip, #2]
800d5d8: fb09 220b mla r2, r9, fp, r2
800d5dc: 4452 add r2, sl
800d5de: b29b uxth r3, r3
800d5e0: ea43 4302 orr.w r3, r3, r2, lsl #16
800d5e4: f84c 3b04 str.w r3, [ip], #4
800d5e8: f857 3b04 ldr.w r3, [r7], #4
800d5ec: ea4f 4a13 mov.w sl, r3, lsr #16
800d5f0: f8bc 3000 ldrh.w r3, [ip]
800d5f4: fb09 330a mla r3, r9, sl, r3
800d5f8: eb03 4312 add.w r3, r3, r2, lsr #16
800d5fc: 42bd cmp r5, r7
800d5fe: ea4f 4a13 mov.w sl, r3, lsr #16
800d602: d8e5 bhi.n 800d5d0 <__multiply+0xfc>
800d604: 9a01 ldr r2, [sp, #4]
800d606: 50a3 str r3, [r4, r2]
800d608: 3404 adds r4, #4
800d60a: e79f b.n 800d54c <__multiply+0x78>
800d60c: 3e01 subs r6, #1
800d60e: e7a1 b.n 800d554 <__multiply+0x80>
800d610: 0800e2b8 .word 0x0800e2b8
800d614: 0800e2c9 .word 0x0800e2c9
0800d618 <__pow5mult>:
800d618: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
800d61c: 4615 mov r5, r2
800d61e: f012 0203 ands.w r2, r2, #3
800d622: 4607 mov r7, r0
800d624: 460e mov r6, r1
800d626: d007 beq.n 800d638 <__pow5mult+0x20>
800d628: 4c25 ldr r4, [pc, #148] @ (800d6c0 <__pow5mult+0xa8>)
800d62a: 3a01 subs r2, #1
800d62c: 2300 movs r3, #0
800d62e: f854 2022 ldr.w r2, [r4, r2, lsl #2]
800d632: f7ff fea7 bl 800d384 <__multadd>
800d636: 4606 mov r6, r0
800d638: 10ad asrs r5, r5, #2
800d63a: d03d beq.n 800d6b8 <__pow5mult+0xa0>
800d63c: 69fc ldr r4, [r7, #28]
800d63e: b97c cbnz r4, 800d660 <__pow5mult+0x48>
800d640: 2010 movs r0, #16
800d642: f7ff fd87 bl 800d154 <malloc>
800d646: 4602 mov r2, r0
800d648: 61f8 str r0, [r7, #28]
800d64a: b928 cbnz r0, 800d658 <__pow5mult+0x40>
800d64c: 4b1d ldr r3, [pc, #116] @ (800d6c4 <__pow5mult+0xac>)
800d64e: 481e ldr r0, [pc, #120] @ (800d6c8 <__pow5mult+0xb0>)
800d650: f240 11b3 movw r1, #435 @ 0x1b3
800d654: f000 fa78 bl 800db48 <__assert_func>
800d658: e9c0 4401 strd r4, r4, [r0, #4]
800d65c: 6004 str r4, [r0, #0]
800d65e: 60c4 str r4, [r0, #12]
800d660: f8d7 801c ldr.w r8, [r7, #28]
800d664: f8d8 4008 ldr.w r4, [r8, #8]
800d668: b94c cbnz r4, 800d67e <__pow5mult+0x66>
800d66a: f240 2171 movw r1, #625 @ 0x271
800d66e: 4638 mov r0, r7
800d670: f7ff ff1a bl 800d4a8 <__i2b>
800d674: 2300 movs r3, #0
800d676: f8c8 0008 str.w r0, [r8, #8]
800d67a: 4604 mov r4, r0
800d67c: 6003 str r3, [r0, #0]
800d67e: f04f 0900 mov.w r9, #0
800d682: 07eb lsls r3, r5, #31
800d684: d50a bpl.n 800d69c <__pow5mult+0x84>
800d686: 4631 mov r1, r6
800d688: 4622 mov r2, r4
800d68a: 4638 mov r0, r7
800d68c: f7ff ff22 bl 800d4d4 <__multiply>
800d690: 4631 mov r1, r6
800d692: 4680 mov r8, r0
800d694: 4638 mov r0, r7
800d696: f7ff fe53 bl 800d340 <_Bfree>
800d69a: 4646 mov r6, r8
800d69c: 106d asrs r5, r5, #1
800d69e: d00b beq.n 800d6b8 <__pow5mult+0xa0>
800d6a0: 6820 ldr r0, [r4, #0]
800d6a2: b938 cbnz r0, 800d6b4 <__pow5mult+0x9c>
800d6a4: 4622 mov r2, r4
800d6a6: 4621 mov r1, r4
800d6a8: 4638 mov r0, r7
800d6aa: f7ff ff13 bl 800d4d4 <__multiply>
800d6ae: 6020 str r0, [r4, #0]
800d6b0: f8c0 9000 str.w r9, [r0]
800d6b4: 4604 mov r4, r0
800d6b6: e7e4 b.n 800d682 <__pow5mult+0x6a>
800d6b8: 4630 mov r0, r6
800d6ba: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
800d6be: bf00 nop
800d6c0: 0800e37c .word 0x0800e37c
800d6c4: 0800e249 .word 0x0800e249
800d6c8: 0800e2c9 .word 0x0800e2c9
0800d6cc <__lshift>:
800d6cc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800d6d0: 460c mov r4, r1
800d6d2: 6849 ldr r1, [r1, #4]
800d6d4: 6923 ldr r3, [r4, #16]
800d6d6: eb03 1862 add.w r8, r3, r2, asr #5
800d6da: 68a3 ldr r3, [r4, #8]
800d6dc: 4607 mov r7, r0
800d6de: 4691 mov r9, r2
800d6e0: ea4f 1a62 mov.w sl, r2, asr #5
800d6e4: f108 0601 add.w r6, r8, #1
800d6e8: 42b3 cmp r3, r6
800d6ea: db0b blt.n 800d704 <__lshift+0x38>
800d6ec: 4638 mov r0, r7
800d6ee: f7ff fde7 bl 800d2c0 <_Balloc>
800d6f2: 4605 mov r5, r0
800d6f4: b948 cbnz r0, 800d70a <__lshift+0x3e>
800d6f6: 4602 mov r2, r0
800d6f8: 4b28 ldr r3, [pc, #160] @ (800d79c <__lshift+0xd0>)
800d6fa: 4829 ldr r0, [pc, #164] @ (800d7a0 <__lshift+0xd4>)
800d6fc: f44f 71ef mov.w r1, #478 @ 0x1de
800d700: f000 fa22 bl 800db48 <__assert_func>
800d704: 3101 adds r1, #1
800d706: 005b lsls r3, r3, #1
800d708: e7ee b.n 800d6e8 <__lshift+0x1c>
800d70a: 2300 movs r3, #0
800d70c: f100 0114 add.w r1, r0, #20
800d710: f100 0210 add.w r2, r0, #16
800d714: 4618 mov r0, r3
800d716: 4553 cmp r3, sl
800d718: db33 blt.n 800d782 <__lshift+0xb6>
800d71a: 6920 ldr r0, [r4, #16]
800d71c: ea2a 7aea bic.w sl, sl, sl, asr #31
800d720: f104 0314 add.w r3, r4, #20
800d724: f019 091f ands.w r9, r9, #31
800d728: eb01 018a add.w r1, r1, sl, lsl #2
800d72c: eb03 0c80 add.w ip, r3, r0, lsl #2
800d730: d02b beq.n 800d78a <__lshift+0xbe>
800d732: f1c9 0e20 rsb lr, r9, #32
800d736: 468a mov sl, r1
800d738: 2200 movs r2, #0
800d73a: 6818 ldr r0, [r3, #0]
800d73c: fa00 f009 lsl.w r0, r0, r9
800d740: 4310 orrs r0, r2
800d742: f84a 0b04 str.w r0, [sl], #4
800d746: f853 2b04 ldr.w r2, [r3], #4
800d74a: 459c cmp ip, r3
800d74c: fa22 f20e lsr.w r2, r2, lr
800d750: d8f3 bhi.n 800d73a <__lshift+0x6e>
800d752: ebac 0304 sub.w r3, ip, r4
800d756: 3b15 subs r3, #21
800d758: f023 0303 bic.w r3, r3, #3
800d75c: 3304 adds r3, #4
800d75e: f104 0015 add.w r0, r4, #21
800d762: 4560 cmp r0, ip
800d764: bf88 it hi
800d766: 2304 movhi r3, #4
800d768: 50ca str r2, [r1, r3]
800d76a: b10a cbz r2, 800d770 <__lshift+0xa4>
800d76c: f108 0602 add.w r6, r8, #2
800d770: 3e01 subs r6, #1
800d772: 4638 mov r0, r7
800d774: 612e str r6, [r5, #16]
800d776: 4621 mov r1, r4
800d778: f7ff fde2 bl 800d340 <_Bfree>
800d77c: 4628 mov r0, r5
800d77e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800d782: f842 0f04 str.w r0, [r2, #4]!
800d786: 3301 adds r3, #1
800d788: e7c5 b.n 800d716 <__lshift+0x4a>
800d78a: 3904 subs r1, #4
800d78c: f853 2b04 ldr.w r2, [r3], #4
800d790: f841 2f04 str.w r2, [r1, #4]!
800d794: 459c cmp ip, r3
800d796: d8f9 bhi.n 800d78c <__lshift+0xc0>
800d798: e7ea b.n 800d770 <__lshift+0xa4>
800d79a: bf00 nop
800d79c: 0800e2b8 .word 0x0800e2b8
800d7a0: 0800e2c9 .word 0x0800e2c9
0800d7a4 <__mcmp>:
800d7a4: 690a ldr r2, [r1, #16]
800d7a6: 4603 mov r3, r0
800d7a8: 6900 ldr r0, [r0, #16]
800d7aa: 1a80 subs r0, r0, r2
800d7ac: b530 push {r4, r5, lr}
800d7ae: d10e bne.n 800d7ce <__mcmp+0x2a>
800d7b0: 3314 adds r3, #20
800d7b2: 3114 adds r1, #20
800d7b4: eb03 0482 add.w r4, r3, r2, lsl #2
800d7b8: eb01 0182 add.w r1, r1, r2, lsl #2
800d7bc: f854 5d04 ldr.w r5, [r4, #-4]!
800d7c0: f851 2d04 ldr.w r2, [r1, #-4]!
800d7c4: 4295 cmp r5, r2
800d7c6: d003 beq.n 800d7d0 <__mcmp+0x2c>
800d7c8: d205 bcs.n 800d7d6 <__mcmp+0x32>
800d7ca: f04f 30ff mov.w r0, #4294967295
800d7ce: bd30 pop {r4, r5, pc}
800d7d0: 42a3 cmp r3, r4
800d7d2: d3f3 bcc.n 800d7bc <__mcmp+0x18>
800d7d4: e7fb b.n 800d7ce <__mcmp+0x2a>
800d7d6: 2001 movs r0, #1
800d7d8: e7f9 b.n 800d7ce <__mcmp+0x2a>
...
0800d7dc <__mdiff>:
800d7dc: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
800d7e0: 4689 mov r9, r1
800d7e2: 4606 mov r6, r0
800d7e4: 4611 mov r1, r2
800d7e6: 4648 mov r0, r9
800d7e8: 4614 mov r4, r2
800d7ea: f7ff ffdb bl 800d7a4 <__mcmp>
800d7ee: 1e05 subs r5, r0, #0
800d7f0: d112 bne.n 800d818 <__mdiff+0x3c>
800d7f2: 4629 mov r1, r5
800d7f4: 4630 mov r0, r6
800d7f6: f7ff fd63 bl 800d2c0 <_Balloc>
800d7fa: 4602 mov r2, r0
800d7fc: b928 cbnz r0, 800d80a <__mdiff+0x2e>
800d7fe: 4b3f ldr r3, [pc, #252] @ (800d8fc <__mdiff+0x120>)
800d800: f240 2137 movw r1, #567 @ 0x237
800d804: 483e ldr r0, [pc, #248] @ (800d900 <__mdiff+0x124>)
800d806: f000 f99f bl 800db48 <__assert_func>
800d80a: 2301 movs r3, #1
800d80c: e9c0 3504 strd r3, r5, [r0, #16]
800d810: 4610 mov r0, r2
800d812: b003 add sp, #12
800d814: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800d818: bfbc itt lt
800d81a: 464b movlt r3, r9
800d81c: 46a1 movlt r9, r4
800d81e: 4630 mov r0, r6
800d820: f8d9 1004 ldr.w r1, [r9, #4]
800d824: bfba itte lt
800d826: 461c movlt r4, r3
800d828: 2501 movlt r5, #1
800d82a: 2500 movge r5, #0
800d82c: f7ff fd48 bl 800d2c0 <_Balloc>
800d830: 4602 mov r2, r0
800d832: b918 cbnz r0, 800d83c <__mdiff+0x60>
800d834: 4b31 ldr r3, [pc, #196] @ (800d8fc <__mdiff+0x120>)
800d836: f240 2145 movw r1, #581 @ 0x245
800d83a: e7e3 b.n 800d804 <__mdiff+0x28>
800d83c: f8d9 7010 ldr.w r7, [r9, #16]
800d840: 6926 ldr r6, [r4, #16]
800d842: 60c5 str r5, [r0, #12]
800d844: f109 0310 add.w r3, r9, #16
800d848: f109 0514 add.w r5, r9, #20
800d84c: f104 0e14 add.w lr, r4, #20
800d850: f100 0b14 add.w fp, r0, #20
800d854: eb05 0887 add.w r8, r5, r7, lsl #2
800d858: eb0e 0686 add.w r6, lr, r6, lsl #2
800d85c: 9301 str r3, [sp, #4]
800d85e: 46d9 mov r9, fp
800d860: f04f 0c00 mov.w ip, #0
800d864: 9b01 ldr r3, [sp, #4]
800d866: f85e 0b04 ldr.w r0, [lr], #4
800d86a: f853 af04 ldr.w sl, [r3, #4]!
800d86e: 9301 str r3, [sp, #4]
800d870: fa1f f38a uxth.w r3, sl
800d874: 4619 mov r1, r3
800d876: b283 uxth r3, r0
800d878: 1acb subs r3, r1, r3
800d87a: 0c00 lsrs r0, r0, #16
800d87c: 4463 add r3, ip
800d87e: ebc0 401a rsb r0, r0, sl, lsr #16
800d882: eb00 4023 add.w r0, r0, r3, asr #16
800d886: b29b uxth r3, r3
800d888: ea43 4300 orr.w r3, r3, r0, lsl #16
800d88c: 4576 cmp r6, lr
800d88e: f849 3b04 str.w r3, [r9], #4
800d892: ea4f 4c20 mov.w ip, r0, asr #16
800d896: d8e5 bhi.n 800d864 <__mdiff+0x88>
800d898: 1b33 subs r3, r6, r4
800d89a: 3b15 subs r3, #21
800d89c: f023 0303 bic.w r3, r3, #3
800d8a0: 3415 adds r4, #21
800d8a2: 3304 adds r3, #4
800d8a4: 42a6 cmp r6, r4
800d8a6: bf38 it cc
800d8a8: 2304 movcc r3, #4
800d8aa: 441d add r5, r3
800d8ac: 445b add r3, fp
800d8ae: 461e mov r6, r3
800d8b0: 462c mov r4, r5
800d8b2: 4544 cmp r4, r8
800d8b4: d30e bcc.n 800d8d4 <__mdiff+0xf8>
800d8b6: f108 0103 add.w r1, r8, #3
800d8ba: 1b49 subs r1, r1, r5
800d8bc: f021 0103 bic.w r1, r1, #3
800d8c0: 3d03 subs r5, #3
800d8c2: 45a8 cmp r8, r5
800d8c4: bf38 it cc
800d8c6: 2100 movcc r1, #0
800d8c8: 440b add r3, r1
800d8ca: f853 1d04 ldr.w r1, [r3, #-4]!
800d8ce: b191 cbz r1, 800d8f6 <__mdiff+0x11a>
800d8d0: 6117 str r7, [r2, #16]
800d8d2: e79d b.n 800d810 <__mdiff+0x34>
800d8d4: f854 1b04 ldr.w r1, [r4], #4
800d8d8: 46e6 mov lr, ip
800d8da: 0c08 lsrs r0, r1, #16
800d8dc: fa1c fc81 uxtah ip, ip, r1
800d8e0: 4471 add r1, lr
800d8e2: eb00 402c add.w r0, r0, ip, asr #16
800d8e6: b289 uxth r1, r1
800d8e8: ea41 4100 orr.w r1, r1, r0, lsl #16
800d8ec: f846 1b04 str.w r1, [r6], #4
800d8f0: ea4f 4c20 mov.w ip, r0, asr #16
800d8f4: e7dd b.n 800d8b2 <__mdiff+0xd6>
800d8f6: 3f01 subs r7, #1
800d8f8: e7e7 b.n 800d8ca <__mdiff+0xee>
800d8fa: bf00 nop
800d8fc: 0800e2b8 .word 0x0800e2b8
800d900: 0800e2c9 .word 0x0800e2c9
0800d904 <__d2b>:
800d904: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
800d908: 460f mov r7, r1
800d90a: 2101 movs r1, #1
800d90c: ec59 8b10 vmov r8, r9, d0
800d910: 4616 mov r6, r2
800d912: f7ff fcd5 bl 800d2c0 <_Balloc>
800d916: 4604 mov r4, r0
800d918: b930 cbnz r0, 800d928 <__d2b+0x24>
800d91a: 4602 mov r2, r0
800d91c: 4b23 ldr r3, [pc, #140] @ (800d9ac <__d2b+0xa8>)
800d91e: 4824 ldr r0, [pc, #144] @ (800d9b0 <__d2b+0xac>)
800d920: f240 310f movw r1, #783 @ 0x30f
800d924: f000 f910 bl 800db48 <__assert_func>
800d928: f3c9 550a ubfx r5, r9, #20, #11
800d92c: f3c9 0313 ubfx r3, r9, #0, #20
800d930: b10d cbz r5, 800d936 <__d2b+0x32>
800d932: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800d936: 9301 str r3, [sp, #4]
800d938: f1b8 0300 subs.w r3, r8, #0
800d93c: d023 beq.n 800d986 <__d2b+0x82>
800d93e: 4668 mov r0, sp
800d940: 9300 str r3, [sp, #0]
800d942: f7ff fd84 bl 800d44e <__lo0bits>
800d946: e9dd 1200 ldrd r1, r2, [sp]
800d94a: b1d0 cbz r0, 800d982 <__d2b+0x7e>
800d94c: f1c0 0320 rsb r3, r0, #32
800d950: fa02 f303 lsl.w r3, r2, r3
800d954: 430b orrs r3, r1
800d956: 40c2 lsrs r2, r0
800d958: 6163 str r3, [r4, #20]
800d95a: 9201 str r2, [sp, #4]
800d95c: 9b01 ldr r3, [sp, #4]
800d95e: 61a3 str r3, [r4, #24]
800d960: 2b00 cmp r3, #0
800d962: bf0c ite eq
800d964: 2201 moveq r2, #1
800d966: 2202 movne r2, #2
800d968: 6122 str r2, [r4, #16]
800d96a: b1a5 cbz r5, 800d996 <__d2b+0x92>
800d96c: f2a5 4533 subw r5, r5, #1075 @ 0x433
800d970: 4405 add r5, r0
800d972: 603d str r5, [r7, #0]
800d974: f1c0 0035 rsb r0, r0, #53 @ 0x35
800d978: 6030 str r0, [r6, #0]
800d97a: 4620 mov r0, r4
800d97c: b003 add sp, #12
800d97e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
800d982: 6161 str r1, [r4, #20]
800d984: e7ea b.n 800d95c <__d2b+0x58>
800d986: a801 add r0, sp, #4
800d988: f7ff fd61 bl 800d44e <__lo0bits>
800d98c: 9b01 ldr r3, [sp, #4]
800d98e: 6163 str r3, [r4, #20]
800d990: 3020 adds r0, #32
800d992: 2201 movs r2, #1
800d994: e7e8 b.n 800d968 <__d2b+0x64>
800d996: eb04 0382 add.w r3, r4, r2, lsl #2
800d99a: f2a0 4032 subw r0, r0, #1074 @ 0x432
800d99e: 6038 str r0, [r7, #0]
800d9a0: 6918 ldr r0, [r3, #16]
800d9a2: f7ff fd35 bl 800d410 <__hi0bits>
800d9a6: ebc0 1042 rsb r0, r0, r2, lsl #5
800d9aa: e7e5 b.n 800d978 <__d2b+0x74>
800d9ac: 0800e2b8 .word 0x0800e2b8
800d9b0: 0800e2c9 .word 0x0800e2c9
0800d9b4 <__sflush_r>:
800d9b4: f9b1 200c ldrsh.w r2, [r1, #12]
800d9b8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
800d9bc: 0716 lsls r6, r2, #28
800d9be: 4605 mov r5, r0
800d9c0: 460c mov r4, r1
800d9c2: d454 bmi.n 800da6e <__sflush_r+0xba>
800d9c4: 684b ldr r3, [r1, #4]
800d9c6: 2b00 cmp r3, #0
800d9c8: dc02 bgt.n 800d9d0 <__sflush_r+0x1c>
800d9ca: 6c0b ldr r3, [r1, #64] @ 0x40
800d9cc: 2b00 cmp r3, #0
800d9ce: dd48 ble.n 800da62 <__sflush_r+0xae>
800d9d0: 6ae6 ldr r6, [r4, #44] @ 0x2c
800d9d2: 2e00 cmp r6, #0
800d9d4: d045 beq.n 800da62 <__sflush_r+0xae>
800d9d6: 2300 movs r3, #0
800d9d8: f412 5280 ands.w r2, r2, #4096 @ 0x1000
800d9dc: 682f ldr r7, [r5, #0]
800d9de: 6a21 ldr r1, [r4, #32]
800d9e0: 602b str r3, [r5, #0]
800d9e2: d030 beq.n 800da46 <__sflush_r+0x92>
800d9e4: 6d62 ldr r2, [r4, #84] @ 0x54
800d9e6: 89a3 ldrh r3, [r4, #12]
800d9e8: 0759 lsls r1, r3, #29
800d9ea: d505 bpl.n 800d9f8 <__sflush_r+0x44>
800d9ec: 6863 ldr r3, [r4, #4]
800d9ee: 1ad2 subs r2, r2, r3
800d9f0: 6b63 ldr r3, [r4, #52] @ 0x34
800d9f2: b10b cbz r3, 800d9f8 <__sflush_r+0x44>
800d9f4: 6c23 ldr r3, [r4, #64] @ 0x40
800d9f6: 1ad2 subs r2, r2, r3
800d9f8: 2300 movs r3, #0
800d9fa: 6ae6 ldr r6, [r4, #44] @ 0x2c
800d9fc: 6a21 ldr r1, [r4, #32]
800d9fe: 4628 mov r0, r5
800da00: 47b0 blx r6
800da02: 1c43 adds r3, r0, #1
800da04: 89a3 ldrh r3, [r4, #12]
800da06: d106 bne.n 800da16 <__sflush_r+0x62>
800da08: 6829 ldr r1, [r5, #0]
800da0a: 291d cmp r1, #29
800da0c: d82b bhi.n 800da66 <__sflush_r+0xb2>
800da0e: 4a2a ldr r2, [pc, #168] @ (800dab8 <__sflush_r+0x104>)
800da10: 40ca lsrs r2, r1
800da12: 07d6 lsls r6, r2, #31
800da14: d527 bpl.n 800da66 <__sflush_r+0xb2>
800da16: 2200 movs r2, #0
800da18: 6062 str r2, [r4, #4]
800da1a: 04d9 lsls r1, r3, #19
800da1c: 6922 ldr r2, [r4, #16]
800da1e: 6022 str r2, [r4, #0]
800da20: d504 bpl.n 800da2c <__sflush_r+0x78>
800da22: 1c42 adds r2, r0, #1
800da24: d101 bne.n 800da2a <__sflush_r+0x76>
800da26: 682b ldr r3, [r5, #0]
800da28: b903 cbnz r3, 800da2c <__sflush_r+0x78>
800da2a: 6560 str r0, [r4, #84] @ 0x54
800da2c: 6b61 ldr r1, [r4, #52] @ 0x34
800da2e: 602f str r7, [r5, #0]
800da30: b1b9 cbz r1, 800da62 <__sflush_r+0xae>
800da32: f104 0344 add.w r3, r4, #68 @ 0x44
800da36: 4299 cmp r1, r3
800da38: d002 beq.n 800da40 <__sflush_r+0x8c>
800da3a: 4628 mov r0, r5
800da3c: f7ff fb40 bl 800d0c0 <_free_r>
800da40: 2300 movs r3, #0
800da42: 6363 str r3, [r4, #52] @ 0x34
800da44: e00d b.n 800da62 <__sflush_r+0xae>
800da46: 2301 movs r3, #1
800da48: 4628 mov r0, r5
800da4a: 47b0 blx r6
800da4c: 4602 mov r2, r0
800da4e: 1c50 adds r0, r2, #1
800da50: d1c9 bne.n 800d9e6 <__sflush_r+0x32>
800da52: 682b ldr r3, [r5, #0]
800da54: 2b00 cmp r3, #0
800da56: d0c6 beq.n 800d9e6 <__sflush_r+0x32>
800da58: 2b1d cmp r3, #29
800da5a: d001 beq.n 800da60 <__sflush_r+0xac>
800da5c: 2b16 cmp r3, #22
800da5e: d11e bne.n 800da9e <__sflush_r+0xea>
800da60: 602f str r7, [r5, #0]
800da62: 2000 movs r0, #0
800da64: e022 b.n 800daac <__sflush_r+0xf8>
800da66: f043 0340 orr.w r3, r3, #64 @ 0x40
800da6a: b21b sxth r3, r3
800da6c: e01b b.n 800daa6 <__sflush_r+0xf2>
800da6e: 690f ldr r7, [r1, #16]
800da70: 2f00 cmp r7, #0
800da72: d0f6 beq.n 800da62 <__sflush_r+0xae>
800da74: 0793 lsls r3, r2, #30
800da76: 680e ldr r6, [r1, #0]
800da78: bf08 it eq
800da7a: 694b ldreq r3, [r1, #20]
800da7c: 600f str r7, [r1, #0]
800da7e: bf18 it ne
800da80: 2300 movne r3, #0
800da82: eba6 0807 sub.w r8, r6, r7
800da86: 608b str r3, [r1, #8]
800da88: f1b8 0f00 cmp.w r8, #0
800da8c: dde9 ble.n 800da62 <__sflush_r+0xae>
800da8e: 6a21 ldr r1, [r4, #32]
800da90: 6aa6 ldr r6, [r4, #40] @ 0x28
800da92: 4643 mov r3, r8
800da94: 463a mov r2, r7
800da96: 4628 mov r0, r5
800da98: 47b0 blx r6
800da9a: 2800 cmp r0, #0
800da9c: dc08 bgt.n 800dab0 <__sflush_r+0xfc>
800da9e: f9b4 300c ldrsh.w r3, [r4, #12]
800daa2: f043 0340 orr.w r3, r3, #64 @ 0x40
800daa6: 81a3 strh r3, [r4, #12]
800daa8: f04f 30ff mov.w r0, #4294967295
800daac: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
800dab0: 4407 add r7, r0
800dab2: eba8 0800 sub.w r8, r8, r0
800dab6: e7e7 b.n 800da88 <__sflush_r+0xd4>
800dab8: 20400001 .word 0x20400001
0800dabc <_fflush_r>:
800dabc: b538 push {r3, r4, r5, lr}
800dabe: 690b ldr r3, [r1, #16]
800dac0: 4605 mov r5, r0
800dac2: 460c mov r4, r1
800dac4: b913 cbnz r3, 800dacc <_fflush_r+0x10>
800dac6: 2500 movs r5, #0
800dac8: 4628 mov r0, r5
800daca: bd38 pop {r3, r4, r5, pc}
800dacc: b118 cbz r0, 800dad6 <_fflush_r+0x1a>
800dace: 6a03 ldr r3, [r0, #32]
800dad0: b90b cbnz r3, 800dad6 <_fflush_r+0x1a>
800dad2: f7fe fba3 bl 800c21c <__sinit>
800dad6: f9b4 300c ldrsh.w r3, [r4, #12]
800dada: 2b00 cmp r3, #0
800dadc: d0f3 beq.n 800dac6 <_fflush_r+0xa>
800dade: 6e62 ldr r2, [r4, #100] @ 0x64
800dae0: 07d0 lsls r0, r2, #31
800dae2: d404 bmi.n 800daee <_fflush_r+0x32>
800dae4: 0599 lsls r1, r3, #22
800dae6: d402 bmi.n 800daee <_fflush_r+0x32>
800dae8: 6da0 ldr r0, [r4, #88] @ 0x58
800daea: f7fe fc8e bl 800c40a <__retarget_lock_acquire_recursive>
800daee: 4628 mov r0, r5
800daf0: 4621 mov r1, r4
800daf2: f7ff ff5f bl 800d9b4 <__sflush_r>
800daf6: 6e63 ldr r3, [r4, #100] @ 0x64
800daf8: 07da lsls r2, r3, #31
800dafa: 4605 mov r5, r0
800dafc: d4e4 bmi.n 800dac8 <_fflush_r+0xc>
800dafe: 89a3 ldrh r3, [r4, #12]
800db00: 059b lsls r3, r3, #22
800db02: d4e1 bmi.n 800dac8 <_fflush_r+0xc>
800db04: 6da0 ldr r0, [r4, #88] @ 0x58
800db06: f7fe fc81 bl 800c40c <__retarget_lock_release_recursive>
800db0a: e7dd b.n 800dac8 <_fflush_r+0xc>
0800db0c <_sbrk_r>:
800db0c: b538 push {r3, r4, r5, lr}
800db0e: 4d06 ldr r5, [pc, #24] @ (800db28 <_sbrk_r+0x1c>)
800db10: 2300 movs r3, #0
800db12: 4604 mov r4, r0
800db14: 4608 mov r0, r1
800db16: 602b str r3, [r5, #0]
800db18: f7f4 fa22 bl 8001f60 <_sbrk>
800db1c: 1c43 adds r3, r0, #1
800db1e: d102 bne.n 800db26 <_sbrk_r+0x1a>
800db20: 682b ldr r3, [r5, #0]
800db22: b103 cbz r3, 800db26 <_sbrk_r+0x1a>
800db24: 6023 str r3, [r4, #0]
800db26: bd38 pop {r3, r4, r5, pc}
800db28: 200011e0 .word 0x200011e0
0800db2c <memcpy>:
800db2c: 440a add r2, r1
800db2e: 4291 cmp r1, r2
800db30: f100 33ff add.w r3, r0, #4294967295
800db34: d100 bne.n 800db38 <memcpy+0xc>
800db36: 4770 bx lr
800db38: b510 push {r4, lr}
800db3a: f811 4b01 ldrb.w r4, [r1], #1
800db3e: f803 4f01 strb.w r4, [r3, #1]!
800db42: 4291 cmp r1, r2
800db44: d1f9 bne.n 800db3a <memcpy+0xe>
800db46: bd10 pop {r4, pc}
0800db48 <__assert_func>:
800db48: b51f push {r0, r1, r2, r3, r4, lr}
800db4a: 4614 mov r4, r2
800db4c: 461a mov r2, r3
800db4e: 4b09 ldr r3, [pc, #36] @ (800db74 <__assert_func+0x2c>)
800db50: 681b ldr r3, [r3, #0]
800db52: 4605 mov r5, r0
800db54: 68d8 ldr r0, [r3, #12]
800db56: b14c cbz r4, 800db6c <__assert_func+0x24>
800db58: 4b07 ldr r3, [pc, #28] @ (800db78 <__assert_func+0x30>)
800db5a: 9100 str r1, [sp, #0]
800db5c: e9cd 3401 strd r3, r4, [sp, #4]
800db60: 4906 ldr r1, [pc, #24] @ (800db7c <__assert_func+0x34>)
800db62: 462b mov r3, r5
800db64: f000 f842 bl 800dbec <fiprintf>
800db68: f000 f852 bl 800dc10 <abort>
800db6c: 4b04 ldr r3, [pc, #16] @ (800db80 <__assert_func+0x38>)
800db6e: 461c mov r4, r3
800db70: e7f3 b.n 800db5a <__assert_func+0x12>
800db72: bf00 nop
800db74: 20000144 .word 0x20000144
800db78: 0800e32c .word 0x0800e32c
800db7c: 0800e339 .word 0x0800e339
800db80: 0800e367 .word 0x0800e367
0800db84 <_calloc_r>:
800db84: b570 push {r4, r5, r6, lr}
800db86: fba1 5402 umull r5, r4, r1, r2
800db8a: b934 cbnz r4, 800db9a <_calloc_r+0x16>
800db8c: 4629 mov r1, r5
800db8e: f7ff fb0b bl 800d1a8 <_malloc_r>
800db92: 4606 mov r6, r0
800db94: b928 cbnz r0, 800dba2 <_calloc_r+0x1e>
800db96: 4630 mov r0, r6
800db98: bd70 pop {r4, r5, r6, pc}
800db9a: 220c movs r2, #12
800db9c: 6002 str r2, [r0, #0]
800db9e: 2600 movs r6, #0
800dba0: e7f9 b.n 800db96 <_calloc_r+0x12>
800dba2: 462a mov r2, r5
800dba4: 4621 mov r1, r4
800dba6: f7fe fbb2 bl 800c30e <memset>
800dbaa: e7f4 b.n 800db96 <_calloc_r+0x12>
0800dbac <__ascii_mbtowc>:
800dbac: b082 sub sp, #8
800dbae: b901 cbnz r1, 800dbb2 <__ascii_mbtowc+0x6>
800dbb0: a901 add r1, sp, #4
800dbb2: b142 cbz r2, 800dbc6 <__ascii_mbtowc+0x1a>
800dbb4: b14b cbz r3, 800dbca <__ascii_mbtowc+0x1e>
800dbb6: 7813 ldrb r3, [r2, #0]
800dbb8: 600b str r3, [r1, #0]
800dbba: 7812 ldrb r2, [r2, #0]
800dbbc: 1e10 subs r0, r2, #0
800dbbe: bf18 it ne
800dbc0: 2001 movne r0, #1
800dbc2: b002 add sp, #8
800dbc4: 4770 bx lr
800dbc6: 4610 mov r0, r2
800dbc8: e7fb b.n 800dbc2 <__ascii_mbtowc+0x16>
800dbca: f06f 0001 mvn.w r0, #1
800dbce: e7f8 b.n 800dbc2 <__ascii_mbtowc+0x16>
0800dbd0 <__ascii_wctomb>:
800dbd0: 4603 mov r3, r0
800dbd2: 4608 mov r0, r1
800dbd4: b141 cbz r1, 800dbe8 <__ascii_wctomb+0x18>
800dbd6: 2aff cmp r2, #255 @ 0xff
800dbd8: d904 bls.n 800dbe4 <__ascii_wctomb+0x14>
800dbda: 228a movs r2, #138 @ 0x8a
800dbdc: 601a str r2, [r3, #0]
800dbde: f04f 30ff mov.w r0, #4294967295
800dbe2: 4770 bx lr
800dbe4: 700a strb r2, [r1, #0]
800dbe6: 2001 movs r0, #1
800dbe8: 4770 bx lr
...
0800dbec <fiprintf>:
800dbec: b40e push {r1, r2, r3}
800dbee: b503 push {r0, r1, lr}
800dbf0: 4601 mov r1, r0
800dbf2: ab03 add r3, sp, #12
800dbf4: 4805 ldr r0, [pc, #20] @ (800dc0c <fiprintf+0x20>)
800dbf6: f853 2b04 ldr.w r2, [r3], #4
800dbfa: 6800 ldr r0, [r0, #0]
800dbfc: 9301 str r3, [sp, #4]
800dbfe: f000 f837 bl 800dc70 <_vfiprintf_r>
800dc02: b002 add sp, #8
800dc04: f85d eb04 ldr.w lr, [sp], #4
800dc08: b003 add sp, #12
800dc0a: 4770 bx lr
800dc0c: 20000144 .word 0x20000144
0800dc10 <abort>:
800dc10: b508 push {r3, lr}
800dc12: 2006 movs r0, #6
800dc14: f000 fa00 bl 800e018 <raise>
800dc18: 2001 movs r0, #1
800dc1a: f7f4 f929 bl 8001e70 <_exit>
0800dc1e <__sfputc_r>:
800dc1e: 6893 ldr r3, [r2, #8]
800dc20: 3b01 subs r3, #1
800dc22: 2b00 cmp r3, #0
800dc24: b410 push {r4}
800dc26: 6093 str r3, [r2, #8]
800dc28: da08 bge.n 800dc3c <__sfputc_r+0x1e>
800dc2a: 6994 ldr r4, [r2, #24]
800dc2c: 42a3 cmp r3, r4
800dc2e: db01 blt.n 800dc34 <__sfputc_r+0x16>
800dc30: 290a cmp r1, #10
800dc32: d103 bne.n 800dc3c <__sfputc_r+0x1e>
800dc34: f85d 4b04 ldr.w r4, [sp], #4
800dc38: f000 b932 b.w 800dea0 <__swbuf_r>
800dc3c: 6813 ldr r3, [r2, #0]
800dc3e: 1c58 adds r0, r3, #1
800dc40: 6010 str r0, [r2, #0]
800dc42: 7019 strb r1, [r3, #0]
800dc44: 4608 mov r0, r1
800dc46: f85d 4b04 ldr.w r4, [sp], #4
800dc4a: 4770 bx lr
0800dc4c <__sfputs_r>:
800dc4c: b5f8 push {r3, r4, r5, r6, r7, lr}
800dc4e: 4606 mov r6, r0
800dc50: 460f mov r7, r1
800dc52: 4614 mov r4, r2
800dc54: 18d5 adds r5, r2, r3
800dc56: 42ac cmp r4, r5
800dc58: d101 bne.n 800dc5e <__sfputs_r+0x12>
800dc5a: 2000 movs r0, #0
800dc5c: e007 b.n 800dc6e <__sfputs_r+0x22>
800dc5e: f814 1b01 ldrb.w r1, [r4], #1
800dc62: 463a mov r2, r7
800dc64: 4630 mov r0, r6
800dc66: f7ff ffda bl 800dc1e <__sfputc_r>
800dc6a: 1c43 adds r3, r0, #1
800dc6c: d1f3 bne.n 800dc56 <__sfputs_r+0xa>
800dc6e: bdf8 pop {r3, r4, r5, r6, r7, pc}
0800dc70 <_vfiprintf_r>:
800dc70: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800dc74: 460d mov r5, r1
800dc76: b09d sub sp, #116 @ 0x74
800dc78: 4614 mov r4, r2
800dc7a: 4698 mov r8, r3
800dc7c: 4606 mov r6, r0
800dc7e: b118 cbz r0, 800dc88 <_vfiprintf_r+0x18>
800dc80: 6a03 ldr r3, [r0, #32]
800dc82: b90b cbnz r3, 800dc88 <_vfiprintf_r+0x18>
800dc84: f7fe faca bl 800c21c <__sinit>
800dc88: 6e6b ldr r3, [r5, #100] @ 0x64
800dc8a: 07d9 lsls r1, r3, #31
800dc8c: d405 bmi.n 800dc9a <_vfiprintf_r+0x2a>
800dc8e: 89ab ldrh r3, [r5, #12]
800dc90: 059a lsls r2, r3, #22
800dc92: d402 bmi.n 800dc9a <_vfiprintf_r+0x2a>
800dc94: 6da8 ldr r0, [r5, #88] @ 0x58
800dc96: f7fe fbb8 bl 800c40a <__retarget_lock_acquire_recursive>
800dc9a: 89ab ldrh r3, [r5, #12]
800dc9c: 071b lsls r3, r3, #28
800dc9e: d501 bpl.n 800dca4 <_vfiprintf_r+0x34>
800dca0: 692b ldr r3, [r5, #16]
800dca2: b99b cbnz r3, 800dccc <_vfiprintf_r+0x5c>
800dca4: 4629 mov r1, r5
800dca6: 4630 mov r0, r6
800dca8: f000 f938 bl 800df1c <__swsetup_r>
800dcac: b170 cbz r0, 800dccc <_vfiprintf_r+0x5c>
800dcae: 6e6b ldr r3, [r5, #100] @ 0x64
800dcb0: 07dc lsls r4, r3, #31
800dcb2: d504 bpl.n 800dcbe <_vfiprintf_r+0x4e>
800dcb4: f04f 30ff mov.w r0, #4294967295
800dcb8: b01d add sp, #116 @ 0x74
800dcba: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800dcbe: 89ab ldrh r3, [r5, #12]
800dcc0: 0598 lsls r0, r3, #22
800dcc2: d4f7 bmi.n 800dcb4 <_vfiprintf_r+0x44>
800dcc4: 6da8 ldr r0, [r5, #88] @ 0x58
800dcc6: f7fe fba1 bl 800c40c <__retarget_lock_release_recursive>
800dcca: e7f3 b.n 800dcb4 <_vfiprintf_r+0x44>
800dccc: 2300 movs r3, #0
800dcce: 9309 str r3, [sp, #36] @ 0x24
800dcd0: 2320 movs r3, #32
800dcd2: f88d 3029 strb.w r3, [sp, #41] @ 0x29
800dcd6: f8cd 800c str.w r8, [sp, #12]
800dcda: 2330 movs r3, #48 @ 0x30
800dcdc: f8df 81ac ldr.w r8, [pc, #428] @ 800de8c <_vfiprintf_r+0x21c>
800dce0: f88d 302a strb.w r3, [sp, #42] @ 0x2a
800dce4: f04f 0901 mov.w r9, #1
800dce8: 4623 mov r3, r4
800dcea: 469a mov sl, r3
800dcec: f813 2b01 ldrb.w r2, [r3], #1
800dcf0: b10a cbz r2, 800dcf6 <_vfiprintf_r+0x86>
800dcf2: 2a25 cmp r2, #37 @ 0x25
800dcf4: d1f9 bne.n 800dcea <_vfiprintf_r+0x7a>
800dcf6: ebba 0b04 subs.w fp, sl, r4
800dcfa: d00b beq.n 800dd14 <_vfiprintf_r+0xa4>
800dcfc: 465b mov r3, fp
800dcfe: 4622 mov r2, r4
800dd00: 4629 mov r1, r5
800dd02: 4630 mov r0, r6
800dd04: f7ff ffa2 bl 800dc4c <__sfputs_r>
800dd08: 3001 adds r0, #1
800dd0a: f000 80a7 beq.w 800de5c <_vfiprintf_r+0x1ec>
800dd0e: 9a09 ldr r2, [sp, #36] @ 0x24
800dd10: 445a add r2, fp
800dd12: 9209 str r2, [sp, #36] @ 0x24
800dd14: f89a 3000 ldrb.w r3, [sl]
800dd18: 2b00 cmp r3, #0
800dd1a: f000 809f beq.w 800de5c <_vfiprintf_r+0x1ec>
800dd1e: 2300 movs r3, #0
800dd20: f04f 32ff mov.w r2, #4294967295
800dd24: e9cd 2305 strd r2, r3, [sp, #20]
800dd28: f10a 0a01 add.w sl, sl, #1
800dd2c: 9304 str r3, [sp, #16]
800dd2e: 9307 str r3, [sp, #28]
800dd30: f88d 3053 strb.w r3, [sp, #83] @ 0x53
800dd34: 931a str r3, [sp, #104] @ 0x68
800dd36: 4654 mov r4, sl
800dd38: 2205 movs r2, #5
800dd3a: f814 1b01 ldrb.w r1, [r4], #1
800dd3e: 4853 ldr r0, [pc, #332] @ (800de8c <_vfiprintf_r+0x21c>)
800dd40: f7f2 fa46 bl 80001d0 <memchr>
800dd44: 9a04 ldr r2, [sp, #16]
800dd46: b9d8 cbnz r0, 800dd80 <_vfiprintf_r+0x110>
800dd48: 06d1 lsls r1, r2, #27
800dd4a: bf44 itt mi
800dd4c: 2320 movmi r3, #32
800dd4e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800dd52: 0713 lsls r3, r2, #28
800dd54: bf44 itt mi
800dd56: 232b movmi r3, #43 @ 0x2b
800dd58: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800dd5c: f89a 3000 ldrb.w r3, [sl]
800dd60: 2b2a cmp r3, #42 @ 0x2a
800dd62: d015 beq.n 800dd90 <_vfiprintf_r+0x120>
800dd64: 9a07 ldr r2, [sp, #28]
800dd66: 4654 mov r4, sl
800dd68: 2000 movs r0, #0
800dd6a: f04f 0c0a mov.w ip, #10
800dd6e: 4621 mov r1, r4
800dd70: f811 3b01 ldrb.w r3, [r1], #1
800dd74: 3b30 subs r3, #48 @ 0x30
800dd76: 2b09 cmp r3, #9
800dd78: d94b bls.n 800de12 <_vfiprintf_r+0x1a2>
800dd7a: b1b0 cbz r0, 800ddaa <_vfiprintf_r+0x13a>
800dd7c: 9207 str r2, [sp, #28]
800dd7e: e014 b.n 800ddaa <_vfiprintf_r+0x13a>
800dd80: eba0 0308 sub.w r3, r0, r8
800dd84: fa09 f303 lsl.w r3, r9, r3
800dd88: 4313 orrs r3, r2
800dd8a: 9304 str r3, [sp, #16]
800dd8c: 46a2 mov sl, r4
800dd8e: e7d2 b.n 800dd36 <_vfiprintf_r+0xc6>
800dd90: 9b03 ldr r3, [sp, #12]
800dd92: 1d19 adds r1, r3, #4
800dd94: 681b ldr r3, [r3, #0]
800dd96: 9103 str r1, [sp, #12]
800dd98: 2b00 cmp r3, #0
800dd9a: bfbb ittet lt
800dd9c: 425b neglt r3, r3
800dd9e: f042 0202 orrlt.w r2, r2, #2
800dda2: 9307 strge r3, [sp, #28]
800dda4: 9307 strlt r3, [sp, #28]
800dda6: bfb8 it lt
800dda8: 9204 strlt r2, [sp, #16]
800ddaa: 7823 ldrb r3, [r4, #0]
800ddac: 2b2e cmp r3, #46 @ 0x2e
800ddae: d10a bne.n 800ddc6 <_vfiprintf_r+0x156>
800ddb0: 7863 ldrb r3, [r4, #1]
800ddb2: 2b2a cmp r3, #42 @ 0x2a
800ddb4: d132 bne.n 800de1c <_vfiprintf_r+0x1ac>
800ddb6: 9b03 ldr r3, [sp, #12]
800ddb8: 1d1a adds r2, r3, #4
800ddba: 681b ldr r3, [r3, #0]
800ddbc: 9203 str r2, [sp, #12]
800ddbe: ea43 73e3 orr.w r3, r3, r3, asr #31
800ddc2: 3402 adds r4, #2
800ddc4: 9305 str r3, [sp, #20]
800ddc6: f8df a0d4 ldr.w sl, [pc, #212] @ 800de9c <_vfiprintf_r+0x22c>
800ddca: 7821 ldrb r1, [r4, #0]
800ddcc: 2203 movs r2, #3
800ddce: 4650 mov r0, sl
800ddd0: f7f2 f9fe bl 80001d0 <memchr>
800ddd4: b138 cbz r0, 800dde6 <_vfiprintf_r+0x176>
800ddd6: 9b04 ldr r3, [sp, #16]
800ddd8: eba0 000a sub.w r0, r0, sl
800dddc: 2240 movs r2, #64 @ 0x40
800ddde: 4082 lsls r2, r0
800dde0: 4313 orrs r3, r2
800dde2: 3401 adds r4, #1
800dde4: 9304 str r3, [sp, #16]
800dde6: f814 1b01 ldrb.w r1, [r4], #1
800ddea: 4829 ldr r0, [pc, #164] @ (800de90 <_vfiprintf_r+0x220>)
800ddec: f88d 1028 strb.w r1, [sp, #40] @ 0x28
800ddf0: 2206 movs r2, #6
800ddf2: f7f2 f9ed bl 80001d0 <memchr>
800ddf6: 2800 cmp r0, #0
800ddf8: d03f beq.n 800de7a <_vfiprintf_r+0x20a>
800ddfa: 4b26 ldr r3, [pc, #152] @ (800de94 <_vfiprintf_r+0x224>)
800ddfc: bb1b cbnz r3, 800de46 <_vfiprintf_r+0x1d6>
800ddfe: 9b03 ldr r3, [sp, #12]
800de00: 3307 adds r3, #7
800de02: f023 0307 bic.w r3, r3, #7
800de06: 3308 adds r3, #8
800de08: 9303 str r3, [sp, #12]
800de0a: 9b09 ldr r3, [sp, #36] @ 0x24
800de0c: 443b add r3, r7
800de0e: 9309 str r3, [sp, #36] @ 0x24
800de10: e76a b.n 800dce8 <_vfiprintf_r+0x78>
800de12: fb0c 3202 mla r2, ip, r2, r3
800de16: 460c mov r4, r1
800de18: 2001 movs r0, #1
800de1a: e7a8 b.n 800dd6e <_vfiprintf_r+0xfe>
800de1c: 2300 movs r3, #0
800de1e: 3401 adds r4, #1
800de20: 9305 str r3, [sp, #20]
800de22: 4619 mov r1, r3
800de24: f04f 0c0a mov.w ip, #10
800de28: 4620 mov r0, r4
800de2a: f810 2b01 ldrb.w r2, [r0], #1
800de2e: 3a30 subs r2, #48 @ 0x30
800de30: 2a09 cmp r2, #9
800de32: d903 bls.n 800de3c <_vfiprintf_r+0x1cc>
800de34: 2b00 cmp r3, #0
800de36: d0c6 beq.n 800ddc6 <_vfiprintf_r+0x156>
800de38: 9105 str r1, [sp, #20]
800de3a: e7c4 b.n 800ddc6 <_vfiprintf_r+0x156>
800de3c: fb0c 2101 mla r1, ip, r1, r2
800de40: 4604 mov r4, r0
800de42: 2301 movs r3, #1
800de44: e7f0 b.n 800de28 <_vfiprintf_r+0x1b8>
800de46: ab03 add r3, sp, #12
800de48: 9300 str r3, [sp, #0]
800de4a: 462a mov r2, r5
800de4c: 4b12 ldr r3, [pc, #72] @ (800de98 <_vfiprintf_r+0x228>)
800de4e: a904 add r1, sp, #16
800de50: 4630 mov r0, r6
800de52: f7fd fda1 bl 800b998 <_printf_float>
800de56: 4607 mov r7, r0
800de58: 1c78 adds r0, r7, #1
800de5a: d1d6 bne.n 800de0a <_vfiprintf_r+0x19a>
800de5c: 6e6b ldr r3, [r5, #100] @ 0x64
800de5e: 07d9 lsls r1, r3, #31
800de60: d405 bmi.n 800de6e <_vfiprintf_r+0x1fe>
800de62: 89ab ldrh r3, [r5, #12]
800de64: 059a lsls r2, r3, #22
800de66: d402 bmi.n 800de6e <_vfiprintf_r+0x1fe>
800de68: 6da8 ldr r0, [r5, #88] @ 0x58
800de6a: f7fe facf bl 800c40c <__retarget_lock_release_recursive>
800de6e: 89ab ldrh r3, [r5, #12]
800de70: 065b lsls r3, r3, #25
800de72: f53f af1f bmi.w 800dcb4 <_vfiprintf_r+0x44>
800de76: 9809 ldr r0, [sp, #36] @ 0x24
800de78: e71e b.n 800dcb8 <_vfiprintf_r+0x48>
800de7a: ab03 add r3, sp, #12
800de7c: 9300 str r3, [sp, #0]
800de7e: 462a mov r2, r5
800de80: 4b05 ldr r3, [pc, #20] @ (800de98 <_vfiprintf_r+0x228>)
800de82: a904 add r1, sp, #16
800de84: 4630 mov r0, r6
800de86: f7fe f81f bl 800bec8 <_printf_i>
800de8a: e7e4 b.n 800de56 <_vfiprintf_r+0x1e6>
800de8c: 0800e368 .word 0x0800e368
800de90: 0800e372 .word 0x0800e372
800de94: 0800b999 .word 0x0800b999
800de98: 0800dc4d .word 0x0800dc4d
800de9c: 0800e36e .word 0x0800e36e
0800dea0 <__swbuf_r>:
800dea0: b5f8 push {r3, r4, r5, r6, r7, lr}
800dea2: 460e mov r6, r1
800dea4: 4614 mov r4, r2
800dea6: 4605 mov r5, r0
800dea8: b118 cbz r0, 800deb2 <__swbuf_r+0x12>
800deaa: 6a03 ldr r3, [r0, #32]
800deac: b90b cbnz r3, 800deb2 <__swbuf_r+0x12>
800deae: f7fe f9b5 bl 800c21c <__sinit>
800deb2: 69a3 ldr r3, [r4, #24]
800deb4: 60a3 str r3, [r4, #8]
800deb6: 89a3 ldrh r3, [r4, #12]
800deb8: 071a lsls r2, r3, #28
800deba: d501 bpl.n 800dec0 <__swbuf_r+0x20>
800debc: 6923 ldr r3, [r4, #16]
800debe: b943 cbnz r3, 800ded2 <__swbuf_r+0x32>
800dec0: 4621 mov r1, r4
800dec2: 4628 mov r0, r5
800dec4: f000 f82a bl 800df1c <__swsetup_r>
800dec8: b118 cbz r0, 800ded2 <__swbuf_r+0x32>
800deca: f04f 37ff mov.w r7, #4294967295
800dece: 4638 mov r0, r7
800ded0: bdf8 pop {r3, r4, r5, r6, r7, pc}
800ded2: 6823 ldr r3, [r4, #0]
800ded4: 6922 ldr r2, [r4, #16]
800ded6: 1a98 subs r0, r3, r2
800ded8: 6963 ldr r3, [r4, #20]
800deda: b2f6 uxtb r6, r6
800dedc: 4283 cmp r3, r0
800dede: 4637 mov r7, r6
800dee0: dc05 bgt.n 800deee <__swbuf_r+0x4e>
800dee2: 4621 mov r1, r4
800dee4: 4628 mov r0, r5
800dee6: f7ff fde9 bl 800dabc <_fflush_r>
800deea: 2800 cmp r0, #0
800deec: d1ed bne.n 800deca <__swbuf_r+0x2a>
800deee: 68a3 ldr r3, [r4, #8]
800def0: 3b01 subs r3, #1
800def2: 60a3 str r3, [r4, #8]
800def4: 6823 ldr r3, [r4, #0]
800def6: 1c5a adds r2, r3, #1
800def8: 6022 str r2, [r4, #0]
800defa: 701e strb r6, [r3, #0]
800defc: 6962 ldr r2, [r4, #20]
800defe: 1c43 adds r3, r0, #1
800df00: 429a cmp r2, r3
800df02: d004 beq.n 800df0e <__swbuf_r+0x6e>
800df04: 89a3 ldrh r3, [r4, #12]
800df06: 07db lsls r3, r3, #31
800df08: d5e1 bpl.n 800dece <__swbuf_r+0x2e>
800df0a: 2e0a cmp r6, #10
800df0c: d1df bne.n 800dece <__swbuf_r+0x2e>
800df0e: 4621 mov r1, r4
800df10: 4628 mov r0, r5
800df12: f7ff fdd3 bl 800dabc <_fflush_r>
800df16: 2800 cmp r0, #0
800df18: d0d9 beq.n 800dece <__swbuf_r+0x2e>
800df1a: e7d6 b.n 800deca <__swbuf_r+0x2a>
0800df1c <__swsetup_r>:
800df1c: b538 push {r3, r4, r5, lr}
800df1e: 4b29 ldr r3, [pc, #164] @ (800dfc4 <__swsetup_r+0xa8>)
800df20: 4605 mov r5, r0
800df22: 6818 ldr r0, [r3, #0]
800df24: 460c mov r4, r1
800df26: b118 cbz r0, 800df30 <__swsetup_r+0x14>
800df28: 6a03 ldr r3, [r0, #32]
800df2a: b90b cbnz r3, 800df30 <__swsetup_r+0x14>
800df2c: f7fe f976 bl 800c21c <__sinit>
800df30: f9b4 300c ldrsh.w r3, [r4, #12]
800df34: 0719 lsls r1, r3, #28
800df36: d422 bmi.n 800df7e <__swsetup_r+0x62>
800df38: 06da lsls r2, r3, #27
800df3a: d407 bmi.n 800df4c <__swsetup_r+0x30>
800df3c: 2209 movs r2, #9
800df3e: 602a str r2, [r5, #0]
800df40: f043 0340 orr.w r3, r3, #64 @ 0x40
800df44: 81a3 strh r3, [r4, #12]
800df46: f04f 30ff mov.w r0, #4294967295
800df4a: e033 b.n 800dfb4 <__swsetup_r+0x98>
800df4c: 0758 lsls r0, r3, #29
800df4e: d512 bpl.n 800df76 <__swsetup_r+0x5a>
800df50: 6b61 ldr r1, [r4, #52] @ 0x34
800df52: b141 cbz r1, 800df66 <__swsetup_r+0x4a>
800df54: f104 0344 add.w r3, r4, #68 @ 0x44
800df58: 4299 cmp r1, r3
800df5a: d002 beq.n 800df62 <__swsetup_r+0x46>
800df5c: 4628 mov r0, r5
800df5e: f7ff f8af bl 800d0c0 <_free_r>
800df62: 2300 movs r3, #0
800df64: 6363 str r3, [r4, #52] @ 0x34
800df66: 89a3 ldrh r3, [r4, #12]
800df68: f023 0324 bic.w r3, r3, #36 @ 0x24
800df6c: 81a3 strh r3, [r4, #12]
800df6e: 2300 movs r3, #0
800df70: 6063 str r3, [r4, #4]
800df72: 6923 ldr r3, [r4, #16]
800df74: 6023 str r3, [r4, #0]
800df76: 89a3 ldrh r3, [r4, #12]
800df78: f043 0308 orr.w r3, r3, #8
800df7c: 81a3 strh r3, [r4, #12]
800df7e: 6923 ldr r3, [r4, #16]
800df80: b94b cbnz r3, 800df96 <__swsetup_r+0x7a>
800df82: 89a3 ldrh r3, [r4, #12]
800df84: f403 7320 and.w r3, r3, #640 @ 0x280
800df88: f5b3 7f00 cmp.w r3, #512 @ 0x200
800df8c: d003 beq.n 800df96 <__swsetup_r+0x7a>
800df8e: 4621 mov r1, r4
800df90: 4628 mov r0, r5
800df92: f000 f883 bl 800e09c <__smakebuf_r>
800df96: f9b4 300c ldrsh.w r3, [r4, #12]
800df9a: f013 0201 ands.w r2, r3, #1
800df9e: d00a beq.n 800dfb6 <__swsetup_r+0x9a>
800dfa0: 2200 movs r2, #0
800dfa2: 60a2 str r2, [r4, #8]
800dfa4: 6962 ldr r2, [r4, #20]
800dfa6: 4252 negs r2, r2
800dfa8: 61a2 str r2, [r4, #24]
800dfaa: 6922 ldr r2, [r4, #16]
800dfac: b942 cbnz r2, 800dfc0 <__swsetup_r+0xa4>
800dfae: f013 0080 ands.w r0, r3, #128 @ 0x80
800dfb2: d1c5 bne.n 800df40 <__swsetup_r+0x24>
800dfb4: bd38 pop {r3, r4, r5, pc}
800dfb6: 0799 lsls r1, r3, #30
800dfb8: bf58 it pl
800dfba: 6962 ldrpl r2, [r4, #20]
800dfbc: 60a2 str r2, [r4, #8]
800dfbe: e7f4 b.n 800dfaa <__swsetup_r+0x8e>
800dfc0: 2000 movs r0, #0
800dfc2: e7f7 b.n 800dfb4 <__swsetup_r+0x98>
800dfc4: 20000144 .word 0x20000144
0800dfc8 <_raise_r>:
800dfc8: 291f cmp r1, #31
800dfca: b538 push {r3, r4, r5, lr}
800dfcc: 4605 mov r5, r0
800dfce: 460c mov r4, r1
800dfd0: d904 bls.n 800dfdc <_raise_r+0x14>
800dfd2: 2316 movs r3, #22
800dfd4: 6003 str r3, [r0, #0]
800dfd6: f04f 30ff mov.w r0, #4294967295
800dfda: bd38 pop {r3, r4, r5, pc}
800dfdc: 6bc2 ldr r2, [r0, #60] @ 0x3c
800dfde: b112 cbz r2, 800dfe6 <_raise_r+0x1e>
800dfe0: f852 3021 ldr.w r3, [r2, r1, lsl #2]
800dfe4: b94b cbnz r3, 800dffa <_raise_r+0x32>
800dfe6: 4628 mov r0, r5
800dfe8: f000 f830 bl 800e04c <_getpid_r>
800dfec: 4622 mov r2, r4
800dfee: 4601 mov r1, r0
800dff0: 4628 mov r0, r5
800dff2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
800dff6: f000 b817 b.w 800e028 <_kill_r>
800dffa: 2b01 cmp r3, #1
800dffc: d00a beq.n 800e014 <_raise_r+0x4c>
800dffe: 1c59 adds r1, r3, #1
800e000: d103 bne.n 800e00a <_raise_r+0x42>
800e002: 2316 movs r3, #22
800e004: 6003 str r3, [r0, #0]
800e006: 2001 movs r0, #1
800e008: e7e7 b.n 800dfda <_raise_r+0x12>
800e00a: 2100 movs r1, #0
800e00c: f842 1024 str.w r1, [r2, r4, lsl #2]
800e010: 4620 mov r0, r4
800e012: 4798 blx r3
800e014: 2000 movs r0, #0
800e016: e7e0 b.n 800dfda <_raise_r+0x12>
0800e018 <raise>:
800e018: 4b02 ldr r3, [pc, #8] @ (800e024 <raise+0xc>)
800e01a: 4601 mov r1, r0
800e01c: 6818 ldr r0, [r3, #0]
800e01e: f7ff bfd3 b.w 800dfc8 <_raise_r>
800e022: bf00 nop
800e024: 20000144 .word 0x20000144
0800e028 <_kill_r>:
800e028: b538 push {r3, r4, r5, lr}
800e02a: 4d07 ldr r5, [pc, #28] @ (800e048 <_kill_r+0x20>)
800e02c: 2300 movs r3, #0
800e02e: 4604 mov r4, r0
800e030: 4608 mov r0, r1
800e032: 4611 mov r1, r2
800e034: 602b str r3, [r5, #0]
800e036: f7f3 ff0b bl 8001e50 <_kill>
800e03a: 1c43 adds r3, r0, #1
800e03c: d102 bne.n 800e044 <_kill_r+0x1c>
800e03e: 682b ldr r3, [r5, #0]
800e040: b103 cbz r3, 800e044 <_kill_r+0x1c>
800e042: 6023 str r3, [r4, #0]
800e044: bd38 pop {r3, r4, r5, pc}
800e046: bf00 nop
800e048: 200011e0 .word 0x200011e0
0800e04c <_getpid_r>:
800e04c: f7f3 bef8 b.w 8001e40 <_getpid>
0800e050 <__swhatbuf_r>:
800e050: b570 push {r4, r5, r6, lr}
800e052: 460c mov r4, r1
800e054: f9b1 100e ldrsh.w r1, [r1, #14]
800e058: 2900 cmp r1, #0
800e05a: b096 sub sp, #88 @ 0x58
800e05c: 4615 mov r5, r2
800e05e: 461e mov r6, r3
800e060: da0d bge.n 800e07e <__swhatbuf_r+0x2e>
800e062: 89a3 ldrh r3, [r4, #12]
800e064: f013 0f80 tst.w r3, #128 @ 0x80
800e068: f04f 0100 mov.w r1, #0
800e06c: bf14 ite ne
800e06e: 2340 movne r3, #64 @ 0x40
800e070: f44f 6380 moveq.w r3, #1024 @ 0x400
800e074: 2000 movs r0, #0
800e076: 6031 str r1, [r6, #0]
800e078: 602b str r3, [r5, #0]
800e07a: b016 add sp, #88 @ 0x58
800e07c: bd70 pop {r4, r5, r6, pc}
800e07e: 466a mov r2, sp
800e080: f000 f848 bl 800e114 <_fstat_r>
800e084: 2800 cmp r0, #0
800e086: dbec blt.n 800e062 <__swhatbuf_r+0x12>
800e088: 9901 ldr r1, [sp, #4]
800e08a: f401 4170 and.w r1, r1, #61440 @ 0xf000
800e08e: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
800e092: 4259 negs r1, r3
800e094: 4159 adcs r1, r3
800e096: f44f 6380 mov.w r3, #1024 @ 0x400
800e09a: e7eb b.n 800e074 <__swhatbuf_r+0x24>
0800e09c <__smakebuf_r>:
800e09c: 898b ldrh r3, [r1, #12]
800e09e: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
800e0a0: 079d lsls r5, r3, #30
800e0a2: 4606 mov r6, r0
800e0a4: 460c mov r4, r1
800e0a6: d507 bpl.n 800e0b8 <__smakebuf_r+0x1c>
800e0a8: f104 0347 add.w r3, r4, #71 @ 0x47
800e0ac: 6023 str r3, [r4, #0]
800e0ae: 6123 str r3, [r4, #16]
800e0b0: 2301 movs r3, #1
800e0b2: 6163 str r3, [r4, #20]
800e0b4: b003 add sp, #12
800e0b6: bdf0 pop {r4, r5, r6, r7, pc}
800e0b8: ab01 add r3, sp, #4
800e0ba: 466a mov r2, sp
800e0bc: f7ff ffc8 bl 800e050 <__swhatbuf_r>
800e0c0: 9f00 ldr r7, [sp, #0]
800e0c2: 4605 mov r5, r0
800e0c4: 4639 mov r1, r7
800e0c6: 4630 mov r0, r6
800e0c8: f7ff f86e bl 800d1a8 <_malloc_r>
800e0cc: b948 cbnz r0, 800e0e2 <__smakebuf_r+0x46>
800e0ce: f9b4 300c ldrsh.w r3, [r4, #12]
800e0d2: 059a lsls r2, r3, #22
800e0d4: d4ee bmi.n 800e0b4 <__smakebuf_r+0x18>
800e0d6: f023 0303 bic.w r3, r3, #3
800e0da: f043 0302 orr.w r3, r3, #2
800e0de: 81a3 strh r3, [r4, #12]
800e0e0: e7e2 b.n 800e0a8 <__smakebuf_r+0xc>
800e0e2: 89a3 ldrh r3, [r4, #12]
800e0e4: 6020 str r0, [r4, #0]
800e0e6: f043 0380 orr.w r3, r3, #128 @ 0x80
800e0ea: 81a3 strh r3, [r4, #12]
800e0ec: 9b01 ldr r3, [sp, #4]
800e0ee: e9c4 0704 strd r0, r7, [r4, #16]
800e0f2: b15b cbz r3, 800e10c <__smakebuf_r+0x70>
800e0f4: f9b4 100e ldrsh.w r1, [r4, #14]
800e0f8: 4630 mov r0, r6
800e0fa: f000 f81d bl 800e138 <_isatty_r>
800e0fe: b128 cbz r0, 800e10c <__smakebuf_r+0x70>
800e100: 89a3 ldrh r3, [r4, #12]
800e102: f023 0303 bic.w r3, r3, #3
800e106: f043 0301 orr.w r3, r3, #1
800e10a: 81a3 strh r3, [r4, #12]
800e10c: 89a3 ldrh r3, [r4, #12]
800e10e: 431d orrs r5, r3
800e110: 81a5 strh r5, [r4, #12]
800e112: e7cf b.n 800e0b4 <__smakebuf_r+0x18>
0800e114 <_fstat_r>:
800e114: b538 push {r3, r4, r5, lr}
800e116: 4d07 ldr r5, [pc, #28] @ (800e134 <_fstat_r+0x20>)
800e118: 2300 movs r3, #0
800e11a: 4604 mov r4, r0
800e11c: 4608 mov r0, r1
800e11e: 4611 mov r1, r2
800e120: 602b str r3, [r5, #0]
800e122: f7f3 fef5 bl 8001f10 <_fstat>
800e126: 1c43 adds r3, r0, #1
800e128: d102 bne.n 800e130 <_fstat_r+0x1c>
800e12a: 682b ldr r3, [r5, #0]
800e12c: b103 cbz r3, 800e130 <_fstat_r+0x1c>
800e12e: 6023 str r3, [r4, #0]
800e130: bd38 pop {r3, r4, r5, pc}
800e132: bf00 nop
800e134: 200011e0 .word 0x200011e0
0800e138 <_isatty_r>:
800e138: b538 push {r3, r4, r5, lr}
800e13a: 4d06 ldr r5, [pc, #24] @ (800e154 <_isatty_r+0x1c>)
800e13c: 2300 movs r3, #0
800e13e: 4604 mov r4, r0
800e140: 4608 mov r0, r1
800e142: 602b str r3, [r5, #0]
800e144: f7f3 fef4 bl 8001f30 <_isatty>
800e148: 1c43 adds r3, r0, #1
800e14a: d102 bne.n 800e152 <_isatty_r+0x1a>
800e14c: 682b ldr r3, [r5, #0]
800e14e: b103 cbz r3, 800e152 <_isatty_r+0x1a>
800e150: 6023 str r3, [r4, #0]
800e152: bd38 pop {r3, r4, r5, pc}
800e154: 200011e0 .word 0x200011e0
0800e158 <_init>:
800e158: b5f8 push {r3, r4, r5, r6, r7, lr}
800e15a: bf00 nop
800e15c: bcf8 pop {r3, r4, r5, r6, r7}
800e15e: bc08 pop {r3}
800e160: 469e mov lr, r3
800e162: 4770 bx lr
0800e164 <_fini>:
800e164: b5f8 push {r3, r4, r5, r6, r7, lr}
800e166: bf00 nop
800e168: bcf8 pop {r3, r4, r5, r6, r7}
800e16a: bc08 pop {r3}
800e16c: 469e mov lr, r3
800e16e: 4770 bx lr
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