16444 lines
626 KiB
Plaintext
Executable File
16444 lines
626 KiB
Plaintext
Executable File
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P5_SETR1.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00007364 08000190 08000190 00001190 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 000003d4 080074f8 080074f8 000084f8 2**3
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 080078cc 080078cc 000091d4 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 080078cc 080078cc 000088cc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 080078d4 080078d4 000091d4 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 080078d4 080078d4 000088d4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 080078d8 080078d8 000088d8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 000001d4 20000000 080078dc 00009000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 0000024c 200001d4 08007ab0 000091d4 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000420 08007ab0 00009420 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 000091d4 2**0
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CONTENTS, READONLY
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12 .debug_info 0000e10d 00000000 00000000 00009204 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00002068 00000000 00000000 00017311 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000c98 00000000 00000000 00019380 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 000009b9 00000000 00000000 0001a018 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00026db1 00000000 00000000 0001a9d1 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0000f146 00000000 00000000 00041782 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000eb055 00000000 00000000 000508c8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 0013b91d 2**0
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CONTENTS, READONLY
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20 .debug_frame 00004408 00000000 00000000 0013b960 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000061 00000000 00000000 0013fd68 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000190 <__do_global_dtors_aux>:
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8000190: b510 push {r4, lr}
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8000192: 4c05 ldr r4, [pc, #20] @ (80001a8 <__do_global_dtors_aux+0x18>)
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8000194: 7823 ldrb r3, [r4, #0]
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8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16>
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8000198: 4b04 ldr r3, [pc, #16] @ (80001ac <__do_global_dtors_aux+0x1c>)
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800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12>
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800019c: 4804 ldr r0, [pc, #16] @ (80001b0 <__do_global_dtors_aux+0x20>)
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800019e: f3af 8000 nop.w
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80001a2: 2301 movs r3, #1
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80001a4: 7023 strb r3, [r4, #0]
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80001a6: bd10 pop {r4, pc}
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80001a8: 200001d4 .word 0x200001d4
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80001ac: 00000000 .word 0x00000000
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80001b0: 080074dc .word 0x080074dc
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080001b4 <frame_dummy>:
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80001b4: b508 push {r3, lr}
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80001b6: 4b03 ldr r3, [pc, #12] @ (80001c4 <frame_dummy+0x10>)
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80001b8: b11b cbz r3, 80001c2 <frame_dummy+0xe>
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80001ba: 4903 ldr r1, [pc, #12] @ (80001c8 <frame_dummy+0x14>)
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80001bc: 4803 ldr r0, [pc, #12] @ (80001cc <frame_dummy+0x18>)
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80001be: f3af 8000 nop.w
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80001c2: bd08 pop {r3, pc}
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80001c4: 00000000 .word 0x00000000
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80001c8: 200001d8 .word 0x200001d8
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80001cc: 080074dc .word 0x080074dc
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080001d0 <memchr>:
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80001d0: f001 01ff and.w r1, r1, #255 @ 0xff
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80001d4: 2a10 cmp r2, #16
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80001d6: db2b blt.n 8000230 <memchr+0x60>
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80001d8: f010 0f07 tst.w r0, #7
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80001dc: d008 beq.n 80001f0 <memchr+0x20>
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80001de: f810 3b01 ldrb.w r3, [r0], #1
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80001e2: 3a01 subs r2, #1
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80001e4: 428b cmp r3, r1
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80001e6: d02d beq.n 8000244 <memchr+0x74>
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80001e8: f010 0f07 tst.w r0, #7
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80001ec: b342 cbz r2, 8000240 <memchr+0x70>
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80001ee: d1f6 bne.n 80001de <memchr+0xe>
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80001f0: b4f0 push {r4, r5, r6, r7}
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80001f2: ea41 2101 orr.w r1, r1, r1, lsl #8
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80001f6: ea41 4101 orr.w r1, r1, r1, lsl #16
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80001fa: f022 0407 bic.w r4, r2, #7
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80001fe: f07f 0700 mvns.w r7, #0
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8000202: 2300 movs r3, #0
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8000204: e8f0 5602 ldrd r5, r6, [r0], #8
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8000208: 3c08 subs r4, #8
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800020a: ea85 0501 eor.w r5, r5, r1
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800020e: ea86 0601 eor.w r6, r6, r1
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8000212: fa85 f547 uadd8 r5, r5, r7
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8000216: faa3 f587 sel r5, r3, r7
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800021a: fa86 f647 uadd8 r6, r6, r7
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800021e: faa5 f687 sel r6, r5, r7
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8000222: b98e cbnz r6, 8000248 <memchr+0x78>
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8000224: d1ee bne.n 8000204 <memchr+0x34>
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8000226: bcf0 pop {r4, r5, r6, r7}
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8000228: f001 01ff and.w r1, r1, #255 @ 0xff
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800022c: f002 0207 and.w r2, r2, #7
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8000230: b132 cbz r2, 8000240 <memchr+0x70>
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8000232: f810 3b01 ldrb.w r3, [r0], #1
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8000236: 3a01 subs r2, #1
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8000238: ea83 0301 eor.w r3, r3, r1
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800023c: b113 cbz r3, 8000244 <memchr+0x74>
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800023e: d1f8 bne.n 8000232 <memchr+0x62>
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8000240: 2000 movs r0, #0
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8000242: 4770 bx lr
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8000244: 3801 subs r0, #1
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8000246: 4770 bx lr
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8000248: 2d00 cmp r5, #0
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800024a: bf06 itte eq
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800024c: 4635 moveq r5, r6
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800024e: 3803 subeq r0, #3
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8000250: 3807 subne r0, #7
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8000252: f015 0f01 tst.w r5, #1
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8000256: d107 bne.n 8000268 <memchr+0x98>
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8000258: 3001 adds r0, #1
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800025a: f415 7f80 tst.w r5, #256 @ 0x100
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800025e: bf02 ittt eq
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8000260: 3001 addeq r0, #1
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8000262: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
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8000266: 3001 addeq r0, #1
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8000268: bcf0 pop {r4, r5, r6, r7}
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800026a: 3801 subs r0, #1
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800026c: 4770 bx lr
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800026e: bf00 nop
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08000270 <strlen>:
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8000270: 4603 mov r3, r0
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8000272: f813 2b01 ldrb.w r2, [r3], #1
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8000276: 2a00 cmp r2, #0
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8000278: d1fb bne.n 8000272 <strlen+0x2>
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800027a: 1a18 subs r0, r3, r0
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800027c: 3801 subs r0, #1
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800027e: 4770 bx lr
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08000280 <__aeabi_drsub>:
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8000280: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
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8000284: e002 b.n 800028c <__adddf3>
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8000286: bf00 nop
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08000288 <__aeabi_dsub>:
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8000288: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
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0800028c <__adddf3>:
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800028c: b530 push {r4, r5, lr}
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800028e: ea4f 0441 mov.w r4, r1, lsl #1
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8000292: ea4f 0543 mov.w r5, r3, lsl #1
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8000296: ea94 0f05 teq r4, r5
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800029a: bf08 it eq
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800029c: ea90 0f02 teqeq r0, r2
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80002a0: bf1f itttt ne
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80002a2: ea54 0c00 orrsne.w ip, r4, r0
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80002a6: ea55 0c02 orrsne.w ip, r5, r2
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80002aa: ea7f 5c64 mvnsne.w ip, r4, asr #21
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80002ae: ea7f 5c65 mvnsne.w ip, r5, asr #21
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80002b2: f000 80e2 beq.w 800047a <__adddf3+0x1ee>
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80002b6: ea4f 5454 mov.w r4, r4, lsr #21
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80002ba: ebd4 5555 rsbs r5, r4, r5, lsr #21
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80002be: bfb8 it lt
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80002c0: 426d neglt r5, r5
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80002c2: dd0c ble.n 80002de <__adddf3+0x52>
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80002c4: 442c add r4, r5
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80002c6: ea80 0202 eor.w r2, r0, r2
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80002ca: ea81 0303 eor.w r3, r1, r3
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80002ce: ea82 0000 eor.w r0, r2, r0
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80002d2: ea83 0101 eor.w r1, r3, r1
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80002d6: ea80 0202 eor.w r2, r0, r2
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80002da: ea81 0303 eor.w r3, r1, r3
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80002de: 2d36 cmp r5, #54 @ 0x36
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80002e0: bf88 it hi
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80002e2: bd30 pophi {r4, r5, pc}
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80002e4: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
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80002e8: ea4f 3101 mov.w r1, r1, lsl #12
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80002ec: f44f 1c80 mov.w ip, #1048576 @ 0x100000
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80002f0: ea4c 3111 orr.w r1, ip, r1, lsr #12
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80002f4: d002 beq.n 80002fc <__adddf3+0x70>
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80002f6: 4240 negs r0, r0
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80002f8: eb61 0141 sbc.w r1, r1, r1, lsl #1
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80002fc: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
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8000300: ea4f 3303 mov.w r3, r3, lsl #12
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8000304: ea4c 3313 orr.w r3, ip, r3, lsr #12
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8000308: d002 beq.n 8000310 <__adddf3+0x84>
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800030a: 4252 negs r2, r2
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800030c: eb63 0343 sbc.w r3, r3, r3, lsl #1
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8000310: ea94 0f05 teq r4, r5
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8000314: f000 80a7 beq.w 8000466 <__adddf3+0x1da>
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8000318: f1a4 0401 sub.w r4, r4, #1
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800031c: f1d5 0e20 rsbs lr, r5, #32
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8000320: db0d blt.n 800033e <__adddf3+0xb2>
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8000322: fa02 fc0e lsl.w ip, r2, lr
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8000326: fa22 f205 lsr.w r2, r2, r5
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800032a: 1880 adds r0, r0, r2
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800032c: f141 0100 adc.w r1, r1, #0
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8000330: fa03 f20e lsl.w r2, r3, lr
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8000334: 1880 adds r0, r0, r2
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8000336: fa43 f305 asr.w r3, r3, r5
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800033a: 4159 adcs r1, r3
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800033c: e00e b.n 800035c <__adddf3+0xd0>
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800033e: f1a5 0520 sub.w r5, r5, #32
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8000342: f10e 0e20 add.w lr, lr, #32
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8000346: 2a01 cmp r2, #1
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8000348: fa03 fc0e lsl.w ip, r3, lr
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800034c: bf28 it cs
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800034e: f04c 0c02 orrcs.w ip, ip, #2
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8000352: fa43 f305 asr.w r3, r3, r5
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8000356: 18c0 adds r0, r0, r3
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8000358: eb51 71e3 adcs.w r1, r1, r3, asr #31
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800035c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
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8000360: d507 bpl.n 8000372 <__adddf3+0xe6>
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8000362: f04f 0e00 mov.w lr, #0
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8000366: f1dc 0c00 rsbs ip, ip, #0
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800036a: eb7e 0000 sbcs.w r0, lr, r0
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800036e: eb6e 0101 sbc.w r1, lr, r1
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8000372: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
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8000376: d31b bcc.n 80003b0 <__adddf3+0x124>
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8000378: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
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800037c: d30c bcc.n 8000398 <__adddf3+0x10c>
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800037e: 0849 lsrs r1, r1, #1
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8000380: ea5f 0030 movs.w r0, r0, rrx
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8000384: ea4f 0c3c mov.w ip, ip, rrx
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8000388: f104 0401 add.w r4, r4, #1
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800038c: ea4f 5244 mov.w r2, r4, lsl #21
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8000390: f512 0f80 cmn.w r2, #4194304 @ 0x400000
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8000394: f080 809a bcs.w 80004cc <__adddf3+0x240>
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8000398: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
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800039c: bf08 it eq
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800039e: ea5f 0c50 movseq.w ip, r0, lsr #1
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80003a2: f150 0000 adcs.w r0, r0, #0
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80003a6: eb41 5104 adc.w r1, r1, r4, lsl #20
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80003aa: ea41 0105 orr.w r1, r1, r5
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80003ae: bd30 pop {r4, r5, pc}
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80003b0: ea5f 0c4c movs.w ip, ip, lsl #1
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80003b4: 4140 adcs r0, r0
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80003b6: eb41 0101 adc.w r1, r1, r1
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80003ba: 3c01 subs r4, #1
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80003bc: bf28 it cs
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80003be: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
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80003c2: d2e9 bcs.n 8000398 <__adddf3+0x10c>
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80003c4: f091 0f00 teq r1, #0
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80003c8: bf04 itt eq
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80003ca: 4601 moveq r1, r0
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80003cc: 2000 moveq r0, #0
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80003ce: fab1 f381 clz r3, r1
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80003d2: bf08 it eq
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80003d4: 3320 addeq r3, #32
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80003d6: f1a3 030b sub.w r3, r3, #11
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80003da: f1b3 0220 subs.w r2, r3, #32
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80003de: da0c bge.n 80003fa <__adddf3+0x16e>
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80003e0: 320c adds r2, #12
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80003e2: dd08 ble.n 80003f6 <__adddf3+0x16a>
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80003e4: f102 0c14 add.w ip, r2, #20
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80003e8: f1c2 020c rsb r2, r2, #12
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80003ec: fa01 f00c lsl.w r0, r1, ip
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80003f0: fa21 f102 lsr.w r1, r1, r2
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80003f4: e00c b.n 8000410 <__adddf3+0x184>
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80003f6: f102 0214 add.w r2, r2, #20
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80003fa: bfd8 it le
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80003fc: f1c2 0c20 rsble ip, r2, #32
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8000400: fa01 f102 lsl.w r1, r1, r2
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8000404: fa20 fc0c lsr.w ip, r0, ip
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8000408: bfdc itt le
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800040a: ea41 010c orrle.w r1, r1, ip
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800040e: 4090 lslle r0, r2
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8000410: 1ae4 subs r4, r4, r3
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8000412: bfa2 ittt ge
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8000414: eb01 5104 addge.w r1, r1, r4, lsl #20
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8000418: 4329 orrge r1, r5
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800041a: bd30 popge {r4, r5, pc}
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800041c: ea6f 0404 mvn.w r4, r4
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8000420: 3c1f subs r4, #31
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8000422: da1c bge.n 800045e <__adddf3+0x1d2>
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8000424: 340c adds r4, #12
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8000426: dc0e bgt.n 8000446 <__adddf3+0x1ba>
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8000428: f104 0414 add.w r4, r4, #20
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800042c: f1c4 0220 rsb r2, r4, #32
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8000430: fa20 f004 lsr.w r0, r0, r4
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8000434: fa01 f302 lsl.w r3, r1, r2
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8000438: ea40 0003 orr.w r0, r0, r3
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800043c: fa21 f304 lsr.w r3, r1, r4
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8000440: ea45 0103 orr.w r1, r5, r3
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8000444: bd30 pop {r4, r5, pc}
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8000446: f1c4 040c rsb r4, r4, #12
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800044a: f1c4 0220 rsb r2, r4, #32
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800044e: fa20 f002 lsr.w r0, r0, r2
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8000452: fa01 f304 lsl.w r3, r1, r4
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8000456: ea40 0003 orr.w r0, r0, r3
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800045a: 4629 mov r1, r5
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800045c: bd30 pop {r4, r5, pc}
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800045e: fa21 f004 lsr.w r0, r1, r4
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8000462: 4629 mov r1, r5
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8000464: bd30 pop {r4, r5, pc}
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8000466: f094 0f00 teq r4, #0
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800046a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
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800046e: bf06 itte eq
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8000470: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
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8000474: 3401 addeq r4, #1
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8000476: 3d01 subne r5, #1
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8000478: e74e b.n 8000318 <__adddf3+0x8c>
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800047a: ea7f 5c64 mvns.w ip, r4, asr #21
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800047e: bf18 it ne
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8000480: ea7f 5c65 mvnsne.w ip, r5, asr #21
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8000484: d029 beq.n 80004da <__adddf3+0x24e>
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8000486: ea94 0f05 teq r4, r5
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800048a: bf08 it eq
|
|
800048c: ea90 0f02 teqeq r0, r2
|
|
8000490: d005 beq.n 800049e <__adddf3+0x212>
|
|
8000492: ea54 0c00 orrs.w ip, r4, r0
|
|
8000496: bf04 itt eq
|
|
8000498: 4619 moveq r1, r3
|
|
800049a: 4610 moveq r0, r2
|
|
800049c: bd30 pop {r4, r5, pc}
|
|
800049e: ea91 0f03 teq r1, r3
|
|
80004a2: bf1e ittt ne
|
|
80004a4: 2100 movne r1, #0
|
|
80004a6: 2000 movne r0, #0
|
|
80004a8: bd30 popne {r4, r5, pc}
|
|
80004aa: ea5f 5c54 movs.w ip, r4, lsr #21
|
|
80004ae: d105 bne.n 80004bc <__adddf3+0x230>
|
|
80004b0: 0040 lsls r0, r0, #1
|
|
80004b2: 4149 adcs r1, r1
|
|
80004b4: bf28 it cs
|
|
80004b6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
|
|
80004ba: bd30 pop {r4, r5, pc}
|
|
80004bc: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
|
|
80004c0: bf3c itt cc
|
|
80004c2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
|
|
80004c6: bd30 popcc {r4, r5, pc}
|
|
80004c8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
80004cc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
|
|
80004d0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
80004d4: f04f 0000 mov.w r0, #0
|
|
80004d8: bd30 pop {r4, r5, pc}
|
|
80004da: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
80004de: bf1a itte ne
|
|
80004e0: 4619 movne r1, r3
|
|
80004e2: 4610 movne r0, r2
|
|
80004e4: ea7f 5c65 mvnseq.w ip, r5, asr #21
|
|
80004e8: bf1c itt ne
|
|
80004ea: 460b movne r3, r1
|
|
80004ec: 4602 movne r2, r0
|
|
80004ee: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80004f2: bf06 itte eq
|
|
80004f4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
|
|
80004f8: ea91 0f03 teqeq r1, r3
|
|
80004fc: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
|
|
8000500: bd30 pop {r4, r5, pc}
|
|
8000502: bf00 nop
|
|
|
|
08000504 <__aeabi_ui2d>:
|
|
8000504: f090 0f00 teq r0, #0
|
|
8000508: bf04 itt eq
|
|
800050a: 2100 moveq r1, #0
|
|
800050c: 4770 bxeq lr
|
|
800050e: b530 push {r4, r5, lr}
|
|
8000510: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000514: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000518: f04f 0500 mov.w r5, #0
|
|
800051c: f04f 0100 mov.w r1, #0
|
|
8000520: e750 b.n 80003c4 <__adddf3+0x138>
|
|
8000522: bf00 nop
|
|
|
|
08000524 <__aeabi_i2d>:
|
|
8000524: f090 0f00 teq r0, #0
|
|
8000528: bf04 itt eq
|
|
800052a: 2100 moveq r1, #0
|
|
800052c: 4770 bxeq lr
|
|
800052e: b530 push {r4, r5, lr}
|
|
8000530: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000534: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000538: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
|
|
800053c: bf48 it mi
|
|
800053e: 4240 negmi r0, r0
|
|
8000540: f04f 0100 mov.w r1, #0
|
|
8000544: e73e b.n 80003c4 <__adddf3+0x138>
|
|
8000546: bf00 nop
|
|
|
|
08000548 <__aeabi_f2d>:
|
|
8000548: 0042 lsls r2, r0, #1
|
|
800054a: ea4f 01e2 mov.w r1, r2, asr #3
|
|
800054e: ea4f 0131 mov.w r1, r1, rrx
|
|
8000552: ea4f 7002 mov.w r0, r2, lsl #28
|
|
8000556: bf1f itttt ne
|
|
8000558: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
|
|
800055c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
|
|
8000560: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
|
|
8000564: 4770 bxne lr
|
|
8000566: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
|
|
800056a: bf08 it eq
|
|
800056c: 4770 bxeq lr
|
|
800056e: f093 4f7f teq r3, #4278190080 @ 0xff000000
|
|
8000572: bf04 itt eq
|
|
8000574: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
|
|
8000578: 4770 bxeq lr
|
|
800057a: b530 push {r4, r5, lr}
|
|
800057c: f44f 7460 mov.w r4, #896 @ 0x380
|
|
8000580: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
8000584: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000588: e71c b.n 80003c4 <__adddf3+0x138>
|
|
800058a: bf00 nop
|
|
|
|
0800058c <__aeabi_ul2d>:
|
|
800058c: ea50 0201 orrs.w r2, r0, r1
|
|
8000590: bf08 it eq
|
|
8000592: 4770 bxeq lr
|
|
8000594: b530 push {r4, r5, lr}
|
|
8000596: f04f 0500 mov.w r5, #0
|
|
800059a: e00a b.n 80005b2 <__aeabi_l2d+0x16>
|
|
|
|
0800059c <__aeabi_l2d>:
|
|
800059c: ea50 0201 orrs.w r2, r0, r1
|
|
80005a0: bf08 it eq
|
|
80005a2: 4770 bxeq lr
|
|
80005a4: b530 push {r4, r5, lr}
|
|
80005a6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
|
|
80005aa: d502 bpl.n 80005b2 <__aeabi_l2d+0x16>
|
|
80005ac: 4240 negs r0, r0
|
|
80005ae: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
80005b2: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80005b6: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80005ba: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
80005be: f43f aed8 beq.w 8000372 <__adddf3+0xe6>
|
|
80005c2: f04f 0203 mov.w r2, #3
|
|
80005c6: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005ca: bf18 it ne
|
|
80005cc: 3203 addne r2, #3
|
|
80005ce: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005d2: bf18 it ne
|
|
80005d4: 3203 addne r2, #3
|
|
80005d6: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
80005da: f1c2 0320 rsb r3, r2, #32
|
|
80005de: fa00 fc03 lsl.w ip, r0, r3
|
|
80005e2: fa20 f002 lsr.w r0, r0, r2
|
|
80005e6: fa01 fe03 lsl.w lr, r1, r3
|
|
80005ea: ea40 000e orr.w r0, r0, lr
|
|
80005ee: fa21 f102 lsr.w r1, r1, r2
|
|
80005f2: 4414 add r4, r2
|
|
80005f4: e6bd b.n 8000372 <__adddf3+0xe6>
|
|
80005f6: bf00 nop
|
|
|
|
080005f8 <__aeabi_dmul>:
|
|
80005f8: b570 push {r4, r5, r6, lr}
|
|
80005fa: f04f 0cff mov.w ip, #255 @ 0xff
|
|
80005fe: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000602: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
8000606: bf1d ittte ne
|
|
8000608: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
800060c: ea94 0f0c teqne r4, ip
|
|
8000610: ea95 0f0c teqne r5, ip
|
|
8000614: f000 f8de bleq 80007d4 <__aeabi_dmul+0x1dc>
|
|
8000618: 442c add r4, r5
|
|
800061a: ea81 0603 eor.w r6, r1, r3
|
|
800061e: ea21 514c bic.w r1, r1, ip, lsl #21
|
|
8000622: ea23 534c bic.w r3, r3, ip, lsl #21
|
|
8000626: ea50 3501 orrs.w r5, r0, r1, lsl #12
|
|
800062a: bf18 it ne
|
|
800062c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
|
|
8000630: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
8000634: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8000638: d038 beq.n 80006ac <__aeabi_dmul+0xb4>
|
|
800063a: fba0 ce02 umull ip, lr, r0, r2
|
|
800063e: f04f 0500 mov.w r5, #0
|
|
8000642: fbe1 e502 umlal lr, r5, r1, r2
|
|
8000646: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
|
|
800064a: fbe0 e503 umlal lr, r5, r0, r3
|
|
800064e: f04f 0600 mov.w r6, #0
|
|
8000652: fbe1 5603 umlal r5, r6, r1, r3
|
|
8000656: f09c 0f00 teq ip, #0
|
|
800065a: bf18 it ne
|
|
800065c: f04e 0e01 orrne.w lr, lr, #1
|
|
8000660: f1a4 04ff sub.w r4, r4, #255 @ 0xff
|
|
8000664: f5b6 7f00 cmp.w r6, #512 @ 0x200
|
|
8000668: f564 7440 sbc.w r4, r4, #768 @ 0x300
|
|
800066c: d204 bcs.n 8000678 <__aeabi_dmul+0x80>
|
|
800066e: ea5f 0e4e movs.w lr, lr, lsl #1
|
|
8000672: 416d adcs r5, r5
|
|
8000674: eb46 0606 adc.w r6, r6, r6
|
|
8000678: ea42 21c6 orr.w r1, r2, r6, lsl #11
|
|
800067c: ea41 5155 orr.w r1, r1, r5, lsr #21
|
|
8000680: ea4f 20c5 mov.w r0, r5, lsl #11
|
|
8000684: ea40 505e orr.w r0, r0, lr, lsr #21
|
|
8000688: ea4f 2ece mov.w lr, lr, lsl #11
|
|
800068c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
8000690: bf88 it hi
|
|
8000692: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000696: d81e bhi.n 80006d6 <__aeabi_dmul+0xde>
|
|
8000698: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
|
|
800069c: bf08 it eq
|
|
800069e: ea5f 0e50 movseq.w lr, r0, lsr #1
|
|
80006a2: f150 0000 adcs.w r0, r0, #0
|
|
80006a6: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
80006aa: bd70 pop {r4, r5, r6, pc}
|
|
80006ac: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
|
|
80006b0: ea46 0101 orr.w r1, r6, r1
|
|
80006b4: ea40 0002 orr.w r0, r0, r2
|
|
80006b8: ea81 0103 eor.w r1, r1, r3
|
|
80006bc: ebb4 045c subs.w r4, r4, ip, lsr #1
|
|
80006c0: bfc2 ittt gt
|
|
80006c2: ebd4 050c rsbsgt r5, r4, ip
|
|
80006c6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80006ca: bd70 popgt {r4, r5, r6, pc}
|
|
80006cc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80006d0: f04f 0e00 mov.w lr, #0
|
|
80006d4: 3c01 subs r4, #1
|
|
80006d6: f300 80ab bgt.w 8000830 <__aeabi_dmul+0x238>
|
|
80006da: f114 0f36 cmn.w r4, #54 @ 0x36
|
|
80006de: bfde ittt le
|
|
80006e0: 2000 movle r0, #0
|
|
80006e2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
|
|
80006e6: bd70 pople {r4, r5, r6, pc}
|
|
80006e8: f1c4 0400 rsb r4, r4, #0
|
|
80006ec: 3c20 subs r4, #32
|
|
80006ee: da35 bge.n 800075c <__aeabi_dmul+0x164>
|
|
80006f0: 340c adds r4, #12
|
|
80006f2: dc1b bgt.n 800072c <__aeabi_dmul+0x134>
|
|
80006f4: f104 0414 add.w r4, r4, #20
|
|
80006f8: f1c4 0520 rsb r5, r4, #32
|
|
80006fc: fa00 f305 lsl.w r3, r0, r5
|
|
8000700: fa20 f004 lsr.w r0, r0, r4
|
|
8000704: fa01 f205 lsl.w r2, r1, r5
|
|
8000708: ea40 0002 orr.w r0, r0, r2
|
|
800070c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
|
|
8000710: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
8000718: fa21 f604 lsr.w r6, r1, r4
|
|
800071c: eb42 0106 adc.w r1, r2, r6
|
|
8000720: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000724: bf08 it eq
|
|
8000726: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800072a: bd70 pop {r4, r5, r6, pc}
|
|
800072c: f1c4 040c rsb r4, r4, #12
|
|
8000730: f1c4 0520 rsb r5, r4, #32
|
|
8000734: fa00 f304 lsl.w r3, r0, r4
|
|
8000738: fa20 f005 lsr.w r0, r0, r5
|
|
800073c: fa01 f204 lsl.w r2, r1, r4
|
|
8000740: ea40 0002 orr.w r0, r0, r2
|
|
8000744: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
8000748: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
800074c: f141 0100 adc.w r1, r1, #0
|
|
8000750: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000754: bf08 it eq
|
|
8000756: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800075a: bd70 pop {r4, r5, r6, pc}
|
|
800075c: f1c4 0520 rsb r5, r4, #32
|
|
8000760: fa00 f205 lsl.w r2, r0, r5
|
|
8000764: ea4e 0e02 orr.w lr, lr, r2
|
|
8000768: fa20 f304 lsr.w r3, r0, r4
|
|
800076c: fa01 f205 lsl.w r2, r1, r5
|
|
8000770: ea43 0302 orr.w r3, r3, r2
|
|
8000774: fa21 f004 lsr.w r0, r1, r4
|
|
8000778: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
800077c: fa21 f204 lsr.w r2, r1, r4
|
|
8000780: ea20 0002 bic.w r0, r0, r2
|
|
8000784: eb00 70d3 add.w r0, r0, r3, lsr #31
|
|
8000788: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
800078c: bf08 it eq
|
|
800078e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
8000792: bd70 pop {r4, r5, r6, pc}
|
|
8000794: f094 0f00 teq r4, #0
|
|
8000798: d10f bne.n 80007ba <__aeabi_dmul+0x1c2>
|
|
800079a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
|
|
800079e: 0040 lsls r0, r0, #1
|
|
80007a0: eb41 0101 adc.w r1, r1, r1
|
|
80007a4: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
80007a8: bf08 it eq
|
|
80007aa: 3c01 subeq r4, #1
|
|
80007ac: d0f7 beq.n 800079e <__aeabi_dmul+0x1a6>
|
|
80007ae: ea41 0106 orr.w r1, r1, r6
|
|
80007b2: f095 0f00 teq r5, #0
|
|
80007b6: bf18 it ne
|
|
80007b8: 4770 bxne lr
|
|
80007ba: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
|
|
80007be: 0052 lsls r2, r2, #1
|
|
80007c0: eb43 0303 adc.w r3, r3, r3
|
|
80007c4: f413 1f80 tst.w r3, #1048576 @ 0x100000
|
|
80007c8: bf08 it eq
|
|
80007ca: 3d01 subeq r5, #1
|
|
80007cc: d0f7 beq.n 80007be <__aeabi_dmul+0x1c6>
|
|
80007ce: ea43 0306 orr.w r3, r3, r6
|
|
80007d2: 4770 bx lr
|
|
80007d4: ea94 0f0c teq r4, ip
|
|
80007d8: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80007dc: bf18 it ne
|
|
80007de: ea95 0f0c teqne r5, ip
|
|
80007e2: d00c beq.n 80007fe <__aeabi_dmul+0x206>
|
|
80007e4: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
80007e8: bf18 it ne
|
|
80007ea: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
80007ee: d1d1 bne.n 8000794 <__aeabi_dmul+0x19c>
|
|
80007f0: ea81 0103 eor.w r1, r1, r3
|
|
80007f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
80007f8: f04f 0000 mov.w r0, #0
|
|
80007fc: bd70 pop {r4, r5, r6, pc}
|
|
80007fe: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000802: bf06 itte eq
|
|
8000804: 4610 moveq r0, r2
|
|
8000806: 4619 moveq r1, r3
|
|
8000808: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
800080c: d019 beq.n 8000842 <__aeabi_dmul+0x24a>
|
|
800080e: ea94 0f0c teq r4, ip
|
|
8000812: d102 bne.n 800081a <__aeabi_dmul+0x222>
|
|
8000814: ea50 3601 orrs.w r6, r0, r1, lsl #12
|
|
8000818: d113 bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800081a: ea95 0f0c teq r5, ip
|
|
800081e: d105 bne.n 800082c <__aeabi_dmul+0x234>
|
|
8000820: ea52 3603 orrs.w r6, r2, r3, lsl #12
|
|
8000824: bf1c itt ne
|
|
8000826: 4610 movne r0, r2
|
|
8000828: 4619 movne r1, r3
|
|
800082a: d10a bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800082c: ea81 0103 eor.w r1, r1, r3
|
|
8000830: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
8000834: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
8000838: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
800083c: f04f 0000 mov.w r0, #0
|
|
8000840: bd70 pop {r4, r5, r6, pc}
|
|
8000842: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
8000846: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
|
|
800084a: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0800084c <__aeabi_ddiv>:
|
|
800084c: b570 push {r4, r5, r6, lr}
|
|
800084e: f04f 0cff mov.w ip, #255 @ 0xff
|
|
8000852: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000856: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
800085a: bf1d ittte ne
|
|
800085c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
8000860: ea94 0f0c teqne r4, ip
|
|
8000864: ea95 0f0c teqne r5, ip
|
|
8000868: f000 f8a7 bleq 80009ba <__aeabi_ddiv+0x16e>
|
|
800086c: eba4 0405 sub.w r4, r4, r5
|
|
8000870: ea81 0e03 eor.w lr, r1, r3
|
|
8000874: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
8000878: ea4f 3101 mov.w r1, r1, lsl #12
|
|
800087c: f000 8088 beq.w 8000990 <__aeabi_ddiv+0x144>
|
|
8000880: ea4f 3303 mov.w r3, r3, lsl #12
|
|
8000884: f04f 5580 mov.w r5, #268435456 @ 0x10000000
|
|
8000888: ea45 1313 orr.w r3, r5, r3, lsr #4
|
|
800088c: ea43 6312 orr.w r3, r3, r2, lsr #24
|
|
8000890: ea4f 2202 mov.w r2, r2, lsl #8
|
|
8000894: ea45 1511 orr.w r5, r5, r1, lsr #4
|
|
8000898: ea45 6510 orr.w r5, r5, r0, lsr #24
|
|
800089c: ea4f 2600 mov.w r6, r0, lsl #8
|
|
80008a0: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
|
|
80008a4: 429d cmp r5, r3
|
|
80008a6: bf08 it eq
|
|
80008a8: 4296 cmpeq r6, r2
|
|
80008aa: f144 04fd adc.w r4, r4, #253 @ 0xfd
|
|
80008ae: f504 7440 add.w r4, r4, #768 @ 0x300
|
|
80008b2: d202 bcs.n 80008ba <__aeabi_ddiv+0x6e>
|
|
80008b4: 085b lsrs r3, r3, #1
|
|
80008b6: ea4f 0232 mov.w r2, r2, rrx
|
|
80008ba: 1ab6 subs r6, r6, r2
|
|
80008bc: eb65 0503 sbc.w r5, r5, r3
|
|
80008c0: 085b lsrs r3, r3, #1
|
|
80008c2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008c6: f44f 1080 mov.w r0, #1048576 @ 0x100000
|
|
80008ca: f44f 2c00 mov.w ip, #524288 @ 0x80000
|
|
80008ce: ebb6 0e02 subs.w lr, r6, r2
|
|
80008d2: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008d6: bf22 ittt cs
|
|
80008d8: 1ab6 subcs r6, r6, r2
|
|
80008da: 4675 movcs r5, lr
|
|
80008dc: ea40 000c orrcs.w r0, r0, ip
|
|
80008e0: 085b lsrs r3, r3, #1
|
|
80008e2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008e6: ebb6 0e02 subs.w lr, r6, r2
|
|
80008ea: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008ee: bf22 ittt cs
|
|
80008f0: 1ab6 subcs r6, r6, r2
|
|
80008f2: 4675 movcs r5, lr
|
|
80008f4: ea40 005c orrcs.w r0, r0, ip, lsr #1
|
|
80008f8: 085b lsrs r3, r3, #1
|
|
80008fa: ea4f 0232 mov.w r2, r2, rrx
|
|
80008fe: ebb6 0e02 subs.w lr, r6, r2
|
|
8000902: eb75 0e03 sbcs.w lr, r5, r3
|
|
8000906: bf22 ittt cs
|
|
8000908: 1ab6 subcs r6, r6, r2
|
|
800090a: 4675 movcs r5, lr
|
|
800090c: ea40 009c orrcs.w r0, r0, ip, lsr #2
|
|
8000910: 085b lsrs r3, r3, #1
|
|
8000912: ea4f 0232 mov.w r2, r2, rrx
|
|
8000916: ebb6 0e02 subs.w lr, r6, r2
|
|
800091a: eb75 0e03 sbcs.w lr, r5, r3
|
|
800091e: bf22 ittt cs
|
|
8000920: 1ab6 subcs r6, r6, r2
|
|
8000922: 4675 movcs r5, lr
|
|
8000924: ea40 00dc orrcs.w r0, r0, ip, lsr #3
|
|
8000928: ea55 0e06 orrs.w lr, r5, r6
|
|
800092c: d018 beq.n 8000960 <__aeabi_ddiv+0x114>
|
|
800092e: ea4f 1505 mov.w r5, r5, lsl #4
|
|
8000932: ea45 7516 orr.w r5, r5, r6, lsr #28
|
|
8000936: ea4f 1606 mov.w r6, r6, lsl #4
|
|
800093a: ea4f 03c3 mov.w r3, r3, lsl #3
|
|
800093e: ea43 7352 orr.w r3, r3, r2, lsr #29
|
|
8000942: ea4f 02c2 mov.w r2, r2, lsl #3
|
|
8000946: ea5f 1c1c movs.w ip, ip, lsr #4
|
|
800094a: d1c0 bne.n 80008ce <__aeabi_ddiv+0x82>
|
|
800094c: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000950: d10b bne.n 800096a <__aeabi_ddiv+0x11e>
|
|
8000952: ea41 0100 orr.w r1, r1, r0
|
|
8000956: f04f 0000 mov.w r0, #0
|
|
800095a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
|
|
800095e: e7b6 b.n 80008ce <__aeabi_ddiv+0x82>
|
|
8000960: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000964: bf04 itt eq
|
|
8000966: 4301 orreq r1, r0
|
|
8000968: 2000 moveq r0, #0
|
|
800096a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
800096e: bf88 it hi
|
|
8000970: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000974: f63f aeaf bhi.w 80006d6 <__aeabi_dmul+0xde>
|
|
8000978: ebb5 0c03 subs.w ip, r5, r3
|
|
800097c: bf04 itt eq
|
|
800097e: ebb6 0c02 subseq.w ip, r6, r2
|
|
8000982: ea5f 0c50 movseq.w ip, r0, lsr #1
|
|
8000986: f150 0000 adcs.w r0, r0, #0
|
|
800098a: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
800098e: bd70 pop {r4, r5, r6, pc}
|
|
8000990: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
|
|
8000994: ea4e 3111 orr.w r1, lr, r1, lsr #12
|
|
8000998: eb14 045c adds.w r4, r4, ip, lsr #1
|
|
800099c: bfc2 ittt gt
|
|
800099e: ebd4 050c rsbsgt r5, r4, ip
|
|
80009a2: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80009a6: bd70 popgt {r4, r5, r6, pc}
|
|
80009a8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80009ac: f04f 0e00 mov.w lr, #0
|
|
80009b0: 3c01 subs r4, #1
|
|
80009b2: e690 b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009b4: ea45 0e06 orr.w lr, r5, r6
|
|
80009b8: e68d b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009ba: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80009be: ea94 0f0c teq r4, ip
|
|
80009c2: bf08 it eq
|
|
80009c4: ea95 0f0c teqeq r5, ip
|
|
80009c8: f43f af3b beq.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009cc: ea94 0f0c teq r4, ip
|
|
80009d0: d10a bne.n 80009e8 <__aeabi_ddiv+0x19c>
|
|
80009d2: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80009d6: f47f af34 bne.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009da: ea95 0f0c teq r5, ip
|
|
80009de: f47f af25 bne.w 800082c <__aeabi_dmul+0x234>
|
|
80009e2: 4610 mov r0, r2
|
|
80009e4: 4619 mov r1, r3
|
|
80009e6: e72c b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009e8: ea95 0f0c teq r5, ip
|
|
80009ec: d106 bne.n 80009fc <__aeabi_ddiv+0x1b0>
|
|
80009ee: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
80009f2: f43f aefd beq.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
80009f6: 4610 mov r0, r2
|
|
80009f8: 4619 mov r1, r3
|
|
80009fa: e722 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009fc: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000a00: bf18 it ne
|
|
8000a02: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
8000a06: f47f aec5 bne.w 8000794 <__aeabi_dmul+0x19c>
|
|
8000a0a: ea50 0441 orrs.w r4, r0, r1, lsl #1
|
|
8000a0e: f47f af0d bne.w 800082c <__aeabi_dmul+0x234>
|
|
8000a12: ea52 0543 orrs.w r5, r2, r3, lsl #1
|
|
8000a16: f47f aeeb bne.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
8000a1a: e712 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
|
|
08000a1c <__gedf2>:
|
|
8000a1c: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff
|
|
8000a20: e006 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a22: bf00 nop
|
|
|
|
08000a24 <__ledf2>:
|
|
8000a24: f04f 0c01 mov.w ip, #1
|
|
8000a28: e002 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a2a: bf00 nop
|
|
|
|
08000a2c <__cmpdf2>:
|
|
8000a2c: f04f 0c01 mov.w ip, #1
|
|
8000a30: f84d cd04 str.w ip, [sp, #-4]!
|
|
8000a34: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a38: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a40: bf18 it ne
|
|
8000a42: ea7f 5c6c mvnsne.w ip, ip, asr #21
|
|
8000a46: d01b beq.n 8000a80 <__cmpdf2+0x54>
|
|
8000a48: b001 add sp, #4
|
|
8000a4a: ea50 0c41 orrs.w ip, r0, r1, lsl #1
|
|
8000a4e: bf0c ite eq
|
|
8000a50: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
|
|
8000a54: ea91 0f03 teqne r1, r3
|
|
8000a58: bf02 ittt eq
|
|
8000a5a: ea90 0f02 teqeq r0, r2
|
|
8000a5e: 2000 moveq r0, #0
|
|
8000a60: 4770 bxeq lr
|
|
8000a62: f110 0f00 cmn.w r0, #0
|
|
8000a66: ea91 0f03 teq r1, r3
|
|
8000a6a: bf58 it pl
|
|
8000a6c: 4299 cmppl r1, r3
|
|
8000a6e: bf08 it eq
|
|
8000a70: 4290 cmpeq r0, r2
|
|
8000a72: bf2c ite cs
|
|
8000a74: 17d8 asrcs r0, r3, #31
|
|
8000a76: ea6f 70e3 mvncc.w r0, r3, asr #31
|
|
8000a7a: f040 0001 orr.w r0, r0, #1
|
|
8000a7e: 4770 bx lr
|
|
8000a80: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a84: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a88: d102 bne.n 8000a90 <__cmpdf2+0x64>
|
|
8000a8a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000a8e: d107 bne.n 8000aa0 <__cmpdf2+0x74>
|
|
8000a90: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a94: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a98: d1d6 bne.n 8000a48 <__cmpdf2+0x1c>
|
|
8000a9a: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000a9e: d0d3 beq.n 8000a48 <__cmpdf2+0x1c>
|
|
8000aa0: f85d 0b04 ldr.w r0, [sp], #4
|
|
8000aa4: 4770 bx lr
|
|
8000aa6: bf00 nop
|
|
|
|
08000aa8 <__aeabi_cdrcmple>:
|
|
8000aa8: 4684 mov ip, r0
|
|
8000aaa: 4610 mov r0, r2
|
|
8000aac: 4662 mov r2, ip
|
|
8000aae: 468c mov ip, r1
|
|
8000ab0: 4619 mov r1, r3
|
|
8000ab2: 4663 mov r3, ip
|
|
8000ab4: e000 b.n 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ab6: bf00 nop
|
|
|
|
08000ab8 <__aeabi_cdcmpeq>:
|
|
8000ab8: b501 push {r0, lr}
|
|
8000aba: f7ff ffb7 bl 8000a2c <__cmpdf2>
|
|
8000abe: 2800 cmp r0, #0
|
|
8000ac0: bf48 it mi
|
|
8000ac2: f110 0f00 cmnmi.w r0, #0
|
|
8000ac6: bd01 pop {r0, pc}
|
|
|
|
08000ac8 <__aeabi_dcmpeq>:
|
|
8000ac8: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000acc: f7ff fff4 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ad0: bf0c ite eq
|
|
8000ad2: 2001 moveq r0, #1
|
|
8000ad4: 2000 movne r0, #0
|
|
8000ad6: f85d fb08 ldr.w pc, [sp], #8
|
|
8000ada: bf00 nop
|
|
|
|
08000adc <__aeabi_dcmplt>:
|
|
8000adc: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000ae0: f7ff ffea bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ae4: bf34 ite cc
|
|
8000ae6: 2001 movcc r0, #1
|
|
8000ae8: 2000 movcs r0, #0
|
|
8000aea: f85d fb08 ldr.w pc, [sp], #8
|
|
8000aee: bf00 nop
|
|
|
|
08000af0 <__aeabi_dcmple>:
|
|
8000af0: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000af4: f7ff ffe0 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000af8: bf94 ite ls
|
|
8000afa: 2001 movls r0, #1
|
|
8000afc: 2000 movhi r0, #0
|
|
8000afe: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b02: bf00 nop
|
|
|
|
08000b04 <__aeabi_dcmpge>:
|
|
8000b04: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b08: f7ff ffce bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b0c: bf94 ite ls
|
|
8000b0e: 2001 movls r0, #1
|
|
8000b10: 2000 movhi r0, #0
|
|
8000b12: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b16: bf00 nop
|
|
|
|
08000b18 <__aeabi_dcmpgt>:
|
|
8000b18: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b1c: f7ff ffc4 bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b20: bf34 ite cc
|
|
8000b22: 2001 movcc r0, #1
|
|
8000b24: 2000 movcs r0, #0
|
|
8000b26: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b2a: bf00 nop
|
|
|
|
08000b2c <__aeabi_dcmpun>:
|
|
8000b2c: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000b30: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b34: d102 bne.n 8000b3c <__aeabi_dcmpun+0x10>
|
|
8000b36: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000b3a: d10a bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000b40: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x20>
|
|
8000b46: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000b4a: d102 bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b4c: f04f 0000 mov.w r0, #0
|
|
8000b50: 4770 bx lr
|
|
8000b52: f04f 0001 mov.w r0, #1
|
|
8000b56: 4770 bx lr
|
|
|
|
08000b58 <__aeabi_d2iz>:
|
|
8000b58: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
8000b60: d215 bcs.n 8000b8e <__aeabi_d2iz+0x36>
|
|
8000b62: d511 bpl.n 8000b88 <__aeabi_d2iz+0x30>
|
|
8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
8000b6c: d912 bls.n 8000b94 <__aeabi_d2iz+0x3c>
|
|
8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
8000b7a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
|
|
8000b7e: fa23 f002 lsr.w r0, r3, r2
|
|
8000b82: bf18 it ne
|
|
8000b84: 4240 negne r0, r0
|
|
8000b86: 4770 bx lr
|
|
8000b88: f04f 0000 mov.w r0, #0
|
|
8000b8c: 4770 bx lr
|
|
8000b8e: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000b92: d105 bne.n 8000ba0 <__aeabi_d2iz+0x48>
|
|
8000b94: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
|
|
8000b98: bf08 it eq
|
|
8000b9a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
|
|
8000b9e: 4770 bx lr
|
|
8000ba0: f04f 0000 mov.w r0, #0
|
|
8000ba4: 4770 bx lr
|
|
8000ba6: bf00 nop
|
|
|
|
08000ba8 <__aeabi_uldivmod>:
|
|
8000ba8: b953 cbnz r3, 8000bc0 <__aeabi_uldivmod+0x18>
|
|
8000baa: b94a cbnz r2, 8000bc0 <__aeabi_uldivmod+0x18>
|
|
8000bac: 2900 cmp r1, #0
|
|
8000bae: bf08 it eq
|
|
8000bb0: 2800 cmpeq r0, #0
|
|
8000bb2: bf1c itt ne
|
|
8000bb4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
|
|
8000bb8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
|
|
8000bbc: f000 b988 b.w 8000ed0 <__aeabi_idiv0>
|
|
8000bc0: f1ad 0c08 sub.w ip, sp, #8
|
|
8000bc4: e96d ce04 strd ip, lr, [sp, #-16]!
|
|
8000bc8: f000 f806 bl 8000bd8 <__udivmoddi4>
|
|
8000bcc: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000bd0: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000bd4: b004 add sp, #16
|
|
8000bd6: 4770 bx lr
|
|
|
|
08000bd8 <__udivmoddi4>:
|
|
8000bd8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8000bdc: 9d08 ldr r5, [sp, #32]
|
|
8000bde: 468e mov lr, r1
|
|
8000be0: 4604 mov r4, r0
|
|
8000be2: 4688 mov r8, r1
|
|
8000be4: 2b00 cmp r3, #0
|
|
8000be6: d14a bne.n 8000c7e <__udivmoddi4+0xa6>
|
|
8000be8: 428a cmp r2, r1
|
|
8000bea: 4617 mov r7, r2
|
|
8000bec: d962 bls.n 8000cb4 <__udivmoddi4+0xdc>
|
|
8000bee: fab2 f682 clz r6, r2
|
|
8000bf2: b14e cbz r6, 8000c08 <__udivmoddi4+0x30>
|
|
8000bf4: f1c6 0320 rsb r3, r6, #32
|
|
8000bf8: fa01 f806 lsl.w r8, r1, r6
|
|
8000bfc: fa20 f303 lsr.w r3, r0, r3
|
|
8000c00: 40b7 lsls r7, r6
|
|
8000c02: ea43 0808 orr.w r8, r3, r8
|
|
8000c06: 40b4 lsls r4, r6
|
|
8000c08: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000c0c: fa1f fc87 uxth.w ip, r7
|
|
8000c10: fbb8 f1fe udiv r1, r8, lr
|
|
8000c14: 0c23 lsrs r3, r4, #16
|
|
8000c16: fb0e 8811 mls r8, lr, r1, r8
|
|
8000c1a: ea43 4308 orr.w r3, r3, r8, lsl #16
|
|
8000c1e: fb01 f20c mul.w r2, r1, ip
|
|
8000c22: 429a cmp r2, r3
|
|
8000c24: d909 bls.n 8000c3a <__udivmoddi4+0x62>
|
|
8000c26: 18fb adds r3, r7, r3
|
|
8000c28: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
|
|
8000c2c: f080 80ea bcs.w 8000e04 <__udivmoddi4+0x22c>
|
|
8000c30: 429a cmp r2, r3
|
|
8000c32: f240 80e7 bls.w 8000e04 <__udivmoddi4+0x22c>
|
|
8000c36: 3902 subs r1, #2
|
|
8000c38: 443b add r3, r7
|
|
8000c3a: 1a9a subs r2, r3, r2
|
|
8000c3c: b2a3 uxth r3, r4
|
|
8000c3e: fbb2 f0fe udiv r0, r2, lr
|
|
8000c42: fb0e 2210 mls r2, lr, r0, r2
|
|
8000c46: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8000c4a: fb00 fc0c mul.w ip, r0, ip
|
|
8000c4e: 459c cmp ip, r3
|
|
8000c50: d909 bls.n 8000c66 <__udivmoddi4+0x8e>
|
|
8000c52: 18fb adds r3, r7, r3
|
|
8000c54: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
|
|
8000c58: f080 80d6 bcs.w 8000e08 <__udivmoddi4+0x230>
|
|
8000c5c: 459c cmp ip, r3
|
|
8000c5e: f240 80d3 bls.w 8000e08 <__udivmoddi4+0x230>
|
|
8000c62: 443b add r3, r7
|
|
8000c64: 3802 subs r0, #2
|
|
8000c66: ea40 4001 orr.w r0, r0, r1, lsl #16
|
|
8000c6a: eba3 030c sub.w r3, r3, ip
|
|
8000c6e: 2100 movs r1, #0
|
|
8000c70: b11d cbz r5, 8000c7a <__udivmoddi4+0xa2>
|
|
8000c72: 40f3 lsrs r3, r6
|
|
8000c74: 2200 movs r2, #0
|
|
8000c76: e9c5 3200 strd r3, r2, [r5]
|
|
8000c7a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8000c7e: 428b cmp r3, r1
|
|
8000c80: d905 bls.n 8000c8e <__udivmoddi4+0xb6>
|
|
8000c82: b10d cbz r5, 8000c88 <__udivmoddi4+0xb0>
|
|
8000c84: e9c5 0100 strd r0, r1, [r5]
|
|
8000c88: 2100 movs r1, #0
|
|
8000c8a: 4608 mov r0, r1
|
|
8000c8c: e7f5 b.n 8000c7a <__udivmoddi4+0xa2>
|
|
8000c8e: fab3 f183 clz r1, r3
|
|
8000c92: 2900 cmp r1, #0
|
|
8000c94: d146 bne.n 8000d24 <__udivmoddi4+0x14c>
|
|
8000c96: 4573 cmp r3, lr
|
|
8000c98: d302 bcc.n 8000ca0 <__udivmoddi4+0xc8>
|
|
8000c9a: 4282 cmp r2, r0
|
|
8000c9c: f200 8105 bhi.w 8000eaa <__udivmoddi4+0x2d2>
|
|
8000ca0: 1a84 subs r4, r0, r2
|
|
8000ca2: eb6e 0203 sbc.w r2, lr, r3
|
|
8000ca6: 2001 movs r0, #1
|
|
8000ca8: 4690 mov r8, r2
|
|
8000caa: 2d00 cmp r5, #0
|
|
8000cac: d0e5 beq.n 8000c7a <__udivmoddi4+0xa2>
|
|
8000cae: e9c5 4800 strd r4, r8, [r5]
|
|
8000cb2: e7e2 b.n 8000c7a <__udivmoddi4+0xa2>
|
|
8000cb4: 2a00 cmp r2, #0
|
|
8000cb6: f000 8090 beq.w 8000dda <__udivmoddi4+0x202>
|
|
8000cba: fab2 f682 clz r6, r2
|
|
8000cbe: 2e00 cmp r6, #0
|
|
8000cc0: f040 80a4 bne.w 8000e0c <__udivmoddi4+0x234>
|
|
8000cc4: 1a8a subs r2, r1, r2
|
|
8000cc6: 0c03 lsrs r3, r0, #16
|
|
8000cc8: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000ccc: b280 uxth r0, r0
|
|
8000cce: b2bc uxth r4, r7
|
|
8000cd0: 2101 movs r1, #1
|
|
8000cd2: fbb2 fcfe udiv ip, r2, lr
|
|
8000cd6: fb0e 221c mls r2, lr, ip, r2
|
|
8000cda: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8000cde: fb04 f20c mul.w r2, r4, ip
|
|
8000ce2: 429a cmp r2, r3
|
|
8000ce4: d907 bls.n 8000cf6 <__udivmoddi4+0x11e>
|
|
8000ce6: 18fb adds r3, r7, r3
|
|
8000ce8: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
|
|
8000cec: d202 bcs.n 8000cf4 <__udivmoddi4+0x11c>
|
|
8000cee: 429a cmp r2, r3
|
|
8000cf0: f200 80e0 bhi.w 8000eb4 <__udivmoddi4+0x2dc>
|
|
8000cf4: 46c4 mov ip, r8
|
|
8000cf6: 1a9b subs r3, r3, r2
|
|
8000cf8: fbb3 f2fe udiv r2, r3, lr
|
|
8000cfc: fb0e 3312 mls r3, lr, r2, r3
|
|
8000d00: ea40 4303 orr.w r3, r0, r3, lsl #16
|
|
8000d04: fb02 f404 mul.w r4, r2, r4
|
|
8000d08: 429c cmp r4, r3
|
|
8000d0a: d907 bls.n 8000d1c <__udivmoddi4+0x144>
|
|
8000d0c: 18fb adds r3, r7, r3
|
|
8000d0e: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
|
|
8000d12: d202 bcs.n 8000d1a <__udivmoddi4+0x142>
|
|
8000d14: 429c cmp r4, r3
|
|
8000d16: f200 80ca bhi.w 8000eae <__udivmoddi4+0x2d6>
|
|
8000d1a: 4602 mov r2, r0
|
|
8000d1c: 1b1b subs r3, r3, r4
|
|
8000d1e: ea42 400c orr.w r0, r2, ip, lsl #16
|
|
8000d22: e7a5 b.n 8000c70 <__udivmoddi4+0x98>
|
|
8000d24: f1c1 0620 rsb r6, r1, #32
|
|
8000d28: 408b lsls r3, r1
|
|
8000d2a: fa22 f706 lsr.w r7, r2, r6
|
|
8000d2e: 431f orrs r7, r3
|
|
8000d30: fa0e f401 lsl.w r4, lr, r1
|
|
8000d34: fa20 f306 lsr.w r3, r0, r6
|
|
8000d38: fa2e fe06 lsr.w lr, lr, r6
|
|
8000d3c: ea4f 4917 mov.w r9, r7, lsr #16
|
|
8000d40: 4323 orrs r3, r4
|
|
8000d42: fa00 f801 lsl.w r8, r0, r1
|
|
8000d46: fa1f fc87 uxth.w ip, r7
|
|
8000d4a: fbbe f0f9 udiv r0, lr, r9
|
|
8000d4e: 0c1c lsrs r4, r3, #16
|
|
8000d50: fb09 ee10 mls lr, r9, r0, lr
|
|
8000d54: ea44 440e orr.w r4, r4, lr, lsl #16
|
|
8000d58: fb00 fe0c mul.w lr, r0, ip
|
|
8000d5c: 45a6 cmp lr, r4
|
|
8000d5e: fa02 f201 lsl.w r2, r2, r1
|
|
8000d62: d909 bls.n 8000d78 <__udivmoddi4+0x1a0>
|
|
8000d64: 193c adds r4, r7, r4
|
|
8000d66: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
|
|
8000d6a: f080 809c bcs.w 8000ea6 <__udivmoddi4+0x2ce>
|
|
8000d6e: 45a6 cmp lr, r4
|
|
8000d70: f240 8099 bls.w 8000ea6 <__udivmoddi4+0x2ce>
|
|
8000d74: 3802 subs r0, #2
|
|
8000d76: 443c add r4, r7
|
|
8000d78: eba4 040e sub.w r4, r4, lr
|
|
8000d7c: fa1f fe83 uxth.w lr, r3
|
|
8000d80: fbb4 f3f9 udiv r3, r4, r9
|
|
8000d84: fb09 4413 mls r4, r9, r3, r4
|
|
8000d88: ea4e 4404 orr.w r4, lr, r4, lsl #16
|
|
8000d8c: fb03 fc0c mul.w ip, r3, ip
|
|
8000d90: 45a4 cmp ip, r4
|
|
8000d92: d908 bls.n 8000da6 <__udivmoddi4+0x1ce>
|
|
8000d94: 193c adds r4, r7, r4
|
|
8000d96: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
|
|
8000d9a: f080 8082 bcs.w 8000ea2 <__udivmoddi4+0x2ca>
|
|
8000d9e: 45a4 cmp ip, r4
|
|
8000da0: d97f bls.n 8000ea2 <__udivmoddi4+0x2ca>
|
|
8000da2: 3b02 subs r3, #2
|
|
8000da4: 443c add r4, r7
|
|
8000da6: ea43 4000 orr.w r0, r3, r0, lsl #16
|
|
8000daa: eba4 040c sub.w r4, r4, ip
|
|
8000dae: fba0 ec02 umull lr, ip, r0, r2
|
|
8000db2: 4564 cmp r4, ip
|
|
8000db4: 4673 mov r3, lr
|
|
8000db6: 46e1 mov r9, ip
|
|
8000db8: d362 bcc.n 8000e80 <__udivmoddi4+0x2a8>
|
|
8000dba: d05f beq.n 8000e7c <__udivmoddi4+0x2a4>
|
|
8000dbc: b15d cbz r5, 8000dd6 <__udivmoddi4+0x1fe>
|
|
8000dbe: ebb8 0203 subs.w r2, r8, r3
|
|
8000dc2: eb64 0409 sbc.w r4, r4, r9
|
|
8000dc6: fa04 f606 lsl.w r6, r4, r6
|
|
8000dca: fa22 f301 lsr.w r3, r2, r1
|
|
8000dce: 431e orrs r6, r3
|
|
8000dd0: 40cc lsrs r4, r1
|
|
8000dd2: e9c5 6400 strd r6, r4, [r5]
|
|
8000dd6: 2100 movs r1, #0
|
|
8000dd8: e74f b.n 8000c7a <__udivmoddi4+0xa2>
|
|
8000dda: fbb1 fcf2 udiv ip, r1, r2
|
|
8000dde: 0c01 lsrs r1, r0, #16
|
|
8000de0: ea41 410e orr.w r1, r1, lr, lsl #16
|
|
8000de4: b280 uxth r0, r0
|
|
8000de6: ea40 4201 orr.w r2, r0, r1, lsl #16
|
|
8000dea: 463b mov r3, r7
|
|
8000dec: 4638 mov r0, r7
|
|
8000dee: 463c mov r4, r7
|
|
8000df0: 46b8 mov r8, r7
|
|
8000df2: 46be mov lr, r7
|
|
8000df4: 2620 movs r6, #32
|
|
8000df6: fbb1 f1f7 udiv r1, r1, r7
|
|
8000dfa: eba2 0208 sub.w r2, r2, r8
|
|
8000dfe: ea41 410c orr.w r1, r1, ip, lsl #16
|
|
8000e02: e766 b.n 8000cd2 <__udivmoddi4+0xfa>
|
|
8000e04: 4601 mov r1, r0
|
|
8000e06: e718 b.n 8000c3a <__udivmoddi4+0x62>
|
|
8000e08: 4610 mov r0, r2
|
|
8000e0a: e72c b.n 8000c66 <__udivmoddi4+0x8e>
|
|
8000e0c: f1c6 0220 rsb r2, r6, #32
|
|
8000e10: fa2e f302 lsr.w r3, lr, r2
|
|
8000e14: 40b7 lsls r7, r6
|
|
8000e16: 40b1 lsls r1, r6
|
|
8000e18: fa20 f202 lsr.w r2, r0, r2
|
|
8000e1c: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000e20: 430a orrs r2, r1
|
|
8000e22: fbb3 f8fe udiv r8, r3, lr
|
|
8000e26: b2bc uxth r4, r7
|
|
8000e28: fb0e 3318 mls r3, lr, r8, r3
|
|
8000e2c: 0c11 lsrs r1, r2, #16
|
|
8000e2e: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
8000e32: fb08 f904 mul.w r9, r8, r4
|
|
8000e36: 40b0 lsls r0, r6
|
|
8000e38: 4589 cmp r9, r1
|
|
8000e3a: ea4f 4310 mov.w r3, r0, lsr #16
|
|
8000e3e: b280 uxth r0, r0
|
|
8000e40: d93e bls.n 8000ec0 <__udivmoddi4+0x2e8>
|
|
8000e42: 1879 adds r1, r7, r1
|
|
8000e44: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
8000e48: d201 bcs.n 8000e4e <__udivmoddi4+0x276>
|
|
8000e4a: 4589 cmp r9, r1
|
|
8000e4c: d81f bhi.n 8000e8e <__udivmoddi4+0x2b6>
|
|
8000e4e: eba1 0109 sub.w r1, r1, r9
|
|
8000e52: fbb1 f9fe udiv r9, r1, lr
|
|
8000e56: fb09 f804 mul.w r8, r9, r4
|
|
8000e5a: fb0e 1119 mls r1, lr, r9, r1
|
|
8000e5e: b292 uxth r2, r2
|
|
8000e60: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
8000e64: 4542 cmp r2, r8
|
|
8000e66: d229 bcs.n 8000ebc <__udivmoddi4+0x2e4>
|
|
8000e68: 18ba adds r2, r7, r2
|
|
8000e6a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
8000e6e: d2c4 bcs.n 8000dfa <__udivmoddi4+0x222>
|
|
8000e70: 4542 cmp r2, r8
|
|
8000e72: d2c2 bcs.n 8000dfa <__udivmoddi4+0x222>
|
|
8000e74: f1a9 0102 sub.w r1, r9, #2
|
|
8000e78: 443a add r2, r7
|
|
8000e7a: e7be b.n 8000dfa <__udivmoddi4+0x222>
|
|
8000e7c: 45f0 cmp r8, lr
|
|
8000e7e: d29d bcs.n 8000dbc <__udivmoddi4+0x1e4>
|
|
8000e80: ebbe 0302 subs.w r3, lr, r2
|
|
8000e84: eb6c 0c07 sbc.w ip, ip, r7
|
|
8000e88: 3801 subs r0, #1
|
|
8000e8a: 46e1 mov r9, ip
|
|
8000e8c: e796 b.n 8000dbc <__udivmoddi4+0x1e4>
|
|
8000e8e: eba7 0909 sub.w r9, r7, r9
|
|
8000e92: 4449 add r1, r9
|
|
8000e94: f1a8 0c02 sub.w ip, r8, #2
|
|
8000e98: fbb1 f9fe udiv r9, r1, lr
|
|
8000e9c: fb09 f804 mul.w r8, r9, r4
|
|
8000ea0: e7db b.n 8000e5a <__udivmoddi4+0x282>
|
|
8000ea2: 4673 mov r3, lr
|
|
8000ea4: e77f b.n 8000da6 <__udivmoddi4+0x1ce>
|
|
8000ea6: 4650 mov r0, sl
|
|
8000ea8: e766 b.n 8000d78 <__udivmoddi4+0x1a0>
|
|
8000eaa: 4608 mov r0, r1
|
|
8000eac: e6fd b.n 8000caa <__udivmoddi4+0xd2>
|
|
8000eae: 443b add r3, r7
|
|
8000eb0: 3a02 subs r2, #2
|
|
8000eb2: e733 b.n 8000d1c <__udivmoddi4+0x144>
|
|
8000eb4: f1ac 0c02 sub.w ip, ip, #2
|
|
8000eb8: 443b add r3, r7
|
|
8000eba: e71c b.n 8000cf6 <__udivmoddi4+0x11e>
|
|
8000ebc: 4649 mov r1, r9
|
|
8000ebe: e79c b.n 8000dfa <__udivmoddi4+0x222>
|
|
8000ec0: eba1 0109 sub.w r1, r1, r9
|
|
8000ec4: 46c4 mov ip, r8
|
|
8000ec6: fbb1 f9fe udiv r9, r1, lr
|
|
8000eca: fb09 f804 mul.w r8, r9, r4
|
|
8000ece: e7c4 b.n 8000e5a <__udivmoddi4+0x282>
|
|
|
|
08000ed0 <__aeabi_idiv0>:
|
|
8000ed0: 4770 bx lr
|
|
8000ed2: bf00 nop
|
|
|
|
08000ed4 <LSM6DSL_Init>:
|
|
#include "stm32l4xx_hal.h"
|
|
#include "LSM6DSL.h"
|
|
|
|
extern I2C_HandleTypeDef hi2c2;
|
|
|
|
void LSM6DSL_Init(){
|
|
8000ed4: b580 push {r7, lr}
|
|
8000ed6: b086 sub sp, #24
|
|
8000ed8: af04 add r7, sp, #16
|
|
|
|
uint8_t buffer[1];
|
|
buffer[0] = ODR_XL_104Hz;
|
|
8000eda: 2340 movs r3, #64 @ 0x40
|
|
8000edc: 713b strb r3, [r7, #4]
|
|
HAL_I2C_Mem_Write(&hi2c2, LSM6DSL_ADDR, REG_CTRL1_XL, I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000);
|
|
8000ede: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8000ee2: 9302 str r3, [sp, #8]
|
|
8000ee4: 2301 movs r3, #1
|
|
8000ee6: 9301 str r3, [sp, #4]
|
|
8000ee8: 1d3b adds r3, r7, #4
|
|
8000eea: 9300 str r3, [sp, #0]
|
|
8000eec: 2301 movs r3, #1
|
|
8000eee: 2210 movs r2, #16
|
|
8000ef0: 21d4 movs r1, #212 @ 0xd4
|
|
8000ef2: 4803 ldr r0, [pc, #12] @ (8000f00 <LSM6DSL_Init+0x2c>)
|
|
8000ef4: f000 ffac bl 8001e50 <HAL_I2C_Mem_Write>
|
|
|
|
}
|
|
8000ef8: bf00 nop
|
|
8000efa: 3708 adds r7, #8
|
|
8000efc: 46bd mov sp, r7
|
|
8000efe: bd80 pop {r7, pc}
|
|
8000f00: 200001f0 .word 0x200001f0
|
|
|
|
08000f04 <LSM6DSL_DataReady>:
|
|
|
|
uint8_t LSM6DSL_DataReady(){
|
|
8000f04: b580 push {r7, lr}
|
|
8000f06: b086 sub sp, #24
|
|
8000f08: af04 add r7, sp, #16
|
|
|
|
uint8_t buffer[1];
|
|
HAL_I2C_Mem_Read(&hi2c2, LSM6DSL_ADDR, REG_STATUS, I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000);
|
|
8000f0a: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8000f0e: 9302 str r3, [sp, #8]
|
|
8000f10: 2301 movs r3, #1
|
|
8000f12: 9301 str r3, [sp, #4]
|
|
8000f14: 1d3b adds r3, r7, #4
|
|
8000f16: 9300 str r3, [sp, #0]
|
|
8000f18: 2301 movs r3, #1
|
|
8000f1a: 221e movs r2, #30
|
|
8000f1c: 21d4 movs r1, #212 @ 0xd4
|
|
8000f1e: 4807 ldr r0, [pc, #28] @ (8000f3c <LSM6DSL_DataReady+0x38>)
|
|
8000f20: f001 f8aa bl 8002078 <HAL_I2C_Mem_Read>
|
|
return ((buffer[0] & 0x01) != 0);
|
|
8000f24: 793b ldrb r3, [r7, #4]
|
|
8000f26: f003 0301 and.w r3, r3, #1
|
|
8000f2a: 2b00 cmp r3, #0
|
|
8000f2c: bf14 ite ne
|
|
8000f2e: 2301 movne r3, #1
|
|
8000f30: 2300 moveq r3, #0
|
|
8000f32: b2db uxtb r3, r3
|
|
|
|
}
|
|
8000f34: 4618 mov r0, r3
|
|
8000f36: 3708 adds r7, #8
|
|
8000f38: 46bd mov sp, r7
|
|
8000f3a: bd80 pop {r7, pc}
|
|
8000f3c: 200001f0 .word 0x200001f0
|
|
|
|
08000f40 <LSM6DSL_ReadAccel>:
|
|
|
|
void LSM6DSL_ReadAccel(float accel[]){
|
|
8000f40: b580 push {r7, lr}
|
|
8000f42: b088 sub sp, #32
|
|
8000f44: af04 add r7, sp, #16
|
|
8000f46: 6078 str r0, [r7, #4]
|
|
|
|
uint8_t buffer[6];
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, LSM6DSL_ADDR, REG_OUTX_L_XL, I2C_MEMADD_SIZE_8BIT, buffer, 6, 1000);
|
|
8000f48: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8000f4c: 9302 str r3, [sp, #8]
|
|
8000f4e: 2306 movs r3, #6
|
|
8000f50: 9301 str r3, [sp, #4]
|
|
8000f52: f107 0308 add.w r3, r7, #8
|
|
8000f56: 9300 str r3, [sp, #0]
|
|
8000f58: 2301 movs r3, #1
|
|
8000f5a: 2228 movs r2, #40 @ 0x28
|
|
8000f5c: 21d4 movs r1, #212 @ 0xd4
|
|
8000f5e: 4818 ldr r0, [pc, #96] @ (8000fc0 <LSM6DSL_ReadAccel+0x80>)
|
|
8000f60: f001 f88a bl 8002078 <HAL_I2C_Mem_Read>
|
|
|
|
for(uint8_t i = 0; i < 3; i++){
|
|
8000f64: 2300 movs r3, #0
|
|
8000f66: 73fb strb r3, [r7, #15]
|
|
8000f68: e022 b.n 8000fb0 <LSM6DSL_ReadAccel+0x70>
|
|
accel[i] = ((int16_t)(buffer[2*i+1]<<8) | buffer[2*i])*0.061f;
|
|
8000f6a: 7bfb ldrb r3, [r7, #15]
|
|
8000f6c: 005b lsls r3, r3, #1
|
|
8000f6e: 3301 adds r3, #1
|
|
8000f70: 3310 adds r3, #16
|
|
8000f72: 443b add r3, r7
|
|
8000f74: f813 3c08 ldrb.w r3, [r3, #-8]
|
|
8000f78: b21b sxth r3, r3
|
|
8000f7a: 021b lsls r3, r3, #8
|
|
8000f7c: b21b sxth r3, r3
|
|
8000f7e: 461a mov r2, r3
|
|
8000f80: 7bfb ldrb r3, [r7, #15]
|
|
8000f82: 005b lsls r3, r3, #1
|
|
8000f84: 3310 adds r3, #16
|
|
8000f86: 443b add r3, r7
|
|
8000f88: f813 3c08 ldrb.w r3, [r3, #-8]
|
|
8000f8c: 4313 orrs r3, r2
|
|
8000f8e: ee07 3a90 vmov s15, r3
|
|
8000f92: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8000f96: 7bfb ldrb r3, [r7, #15]
|
|
8000f98: 009b lsls r3, r3, #2
|
|
8000f9a: 687a ldr r2, [r7, #4]
|
|
8000f9c: 4413 add r3, r2
|
|
8000f9e: ed9f 7a09 vldr s14, [pc, #36] @ 8000fc4 <LSM6DSL_ReadAccel+0x84>
|
|
8000fa2: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000fa6: edc3 7a00 vstr s15, [r3]
|
|
for(uint8_t i = 0; i < 3; i++){
|
|
8000faa: 7bfb ldrb r3, [r7, #15]
|
|
8000fac: 3301 adds r3, #1
|
|
8000fae: 73fb strb r3, [r7, #15]
|
|
8000fb0: 7bfb ldrb r3, [r7, #15]
|
|
8000fb2: 2b02 cmp r3, #2
|
|
8000fb4: d9d9 bls.n 8000f6a <LSM6DSL_ReadAccel+0x2a>
|
|
}
|
|
|
|
}
|
|
8000fb6: bf00 nop
|
|
8000fb8: bf00 nop
|
|
8000fba: 3710 adds r7, #16
|
|
8000fbc: 46bd mov sp, r7
|
|
8000fbe: bd80 pop {r7, pc}
|
|
8000fc0: 200001f0 .word 0x200001f0
|
|
8000fc4: 3d79db23 .word 0x3d79db23
|
|
|
|
08000fc8 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000fc8: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr}
|
|
8000fcc: b088 sub sp, #32
|
|
8000fce: af04 add r7, sp, #16
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000fd0: f000 fb85 bl 80016de <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8000fd4: f000 f83e bl 8001054 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000fd8: f000 f8fe bl 80011d8 <MX_GPIO_Init>
|
|
MX_I2C2_Init();
|
|
8000fdc: f000 f88c bl 80010f8 <MX_I2C2_Init>
|
|
MX_USART1_UART_Init();
|
|
8000fe0: f000 f8ca bl 8001178 <MX_USART1_UART_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
LSM6DSL_Init();
|
|
8000fe4: f7ff ff76 bl 8000ed4 <LSM6DSL_Init>
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
float accel[3];
|
|
|
|
for(uint16_t i = 0; i < N_SAMPLE; i++)
|
|
8000fe8: 2300 movs r3, #0
|
|
8000fea: 81fb strh r3, [r7, #14]
|
|
8000fec: e027 b.n 800103e <main+0x76>
|
|
{
|
|
while(!LSM6DSL_DataReady());
|
|
8000fee: bf00 nop
|
|
8000ff0: f7ff ff88 bl 8000f04 <LSM6DSL_DataReady>
|
|
8000ff4: 4603 mov r3, r0
|
|
8000ff6: 2b00 cmp r3, #0
|
|
8000ff8: d0fa beq.n 8000ff0 <main+0x28>
|
|
LSM6DSL_ReadAccel(accel);
|
|
8000ffa: 463b mov r3, r7
|
|
8000ffc: 4618 mov r0, r3
|
|
8000ffe: f7ff ff9f bl 8000f40 <LSM6DSL_ReadAccel>
|
|
printf("%.3f %.3f %.3f ", accel[0], accel[1], accel[2]);
|
|
8001002: 683b ldr r3, [r7, #0]
|
|
8001004: 4618 mov r0, r3
|
|
8001006: f7ff fa9f bl 8000548 <__aeabi_f2d>
|
|
800100a: 4680 mov r8, r0
|
|
800100c: 4689 mov r9, r1
|
|
800100e: 687b ldr r3, [r7, #4]
|
|
8001010: 4618 mov r0, r3
|
|
8001012: f7ff fa99 bl 8000548 <__aeabi_f2d>
|
|
8001016: 4604 mov r4, r0
|
|
8001018: 460d mov r5, r1
|
|
800101a: 68bb ldr r3, [r7, #8]
|
|
800101c: 4618 mov r0, r3
|
|
800101e: f7ff fa93 bl 8000548 <__aeabi_f2d>
|
|
8001022: 4602 mov r2, r0
|
|
8001024: 460b mov r3, r1
|
|
8001026: e9cd 2302 strd r2, r3, [sp, #8]
|
|
800102a: e9cd 4500 strd r4, r5, [sp]
|
|
800102e: 4642 mov r2, r8
|
|
8001030: 464b mov r3, r9
|
|
8001032: 4806 ldr r0, [pc, #24] @ (800104c <main+0x84>)
|
|
8001034: f004 fa76 bl 8005524 <iprintf>
|
|
for(uint16_t i = 0; i < N_SAMPLE; i++)
|
|
8001038: 89fb ldrh r3, [r7, #14]
|
|
800103a: 3301 adds r3, #1
|
|
800103c: 81fb strh r3, [r7, #14]
|
|
800103e: 89fb ldrh r3, [r7, #14]
|
|
8001040: 2b3f cmp r3, #63 @ 0x3f
|
|
8001042: d9d4 bls.n 8000fee <main+0x26>
|
|
}
|
|
|
|
printf("\r\n");
|
|
8001044: 4802 ldr r0, [pc, #8] @ (8001050 <main+0x88>)
|
|
8001046: f004 fad5 bl 80055f4 <puts>
|
|
{
|
|
800104a: e7cd b.n 8000fe8 <main+0x20>
|
|
800104c: 080074f8 .word 0x080074f8
|
|
8001050: 08007508 .word 0x08007508
|
|
|
|
08001054 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8001054: b580 push {r7, lr}
|
|
8001056: b096 sub sp, #88 @ 0x58
|
|
8001058: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
800105a: f107 0314 add.w r3, r7, #20
|
|
800105e: 2244 movs r2, #68 @ 0x44
|
|
8001060: 2100 movs r1, #0
|
|
8001062: 4618 mov r0, r3
|
|
8001064: f004 fba6 bl 80057b4 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8001068: 463b mov r3, r7
|
|
800106a: 2200 movs r2, #0
|
|
800106c: 601a str r2, [r3, #0]
|
|
800106e: 605a str r2, [r3, #4]
|
|
8001070: 609a str r2, [r3, #8]
|
|
8001072: 60da str r2, [r3, #12]
|
|
8001074: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
|
|
8001076: f44f 7000 mov.w r0, #512 @ 0x200
|
|
800107a: f001 fc7f bl 800297c <HAL_PWREx_ControlVoltageScaling>
|
|
800107e: 4603 mov r3, r0
|
|
8001080: 2b00 cmp r3, #0
|
|
8001082: d001 beq.n 8001088 <SystemClock_Config+0x34>
|
|
{
|
|
Error_Handler();
|
|
8001084: f000 f914 bl 80012b0 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
|
8001088: 2310 movs r3, #16
|
|
800108a: 617b str r3, [r7, #20]
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
|
800108c: 2301 movs r3, #1
|
|
800108e: 62fb str r3, [r7, #44] @ 0x2c
|
|
RCC_OscInitStruct.MSICalibrationValue = 0;
|
|
8001090: 2300 movs r3, #0
|
|
8001092: 633b str r3, [r7, #48] @ 0x30
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
|
8001094: 2360 movs r3, #96 @ 0x60
|
|
8001096: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8001098: 2302 movs r3, #2
|
|
800109a: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
|
800109c: 2301 movs r3, #1
|
|
800109e: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLM = 1;
|
|
80010a0: 2301 movs r3, #1
|
|
80010a2: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLN = 40;
|
|
80010a4: 2328 movs r3, #40 @ 0x28
|
|
80010a6: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
|
80010a8: 2307 movs r3, #7
|
|
80010aa: 64fb str r3, [r7, #76] @ 0x4c
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
80010ac: 2302 movs r3, #2
|
|
80010ae: 653b str r3, [r7, #80] @ 0x50
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
80010b0: 2302 movs r3, #2
|
|
80010b2: 657b str r3, [r7, #84] @ 0x54
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
80010b4: f107 0314 add.w r3, r7, #20
|
|
80010b8: 4618 mov r0, r3
|
|
80010ba: f001 fcb5 bl 8002a28 <HAL_RCC_OscConfig>
|
|
80010be: 4603 mov r3, r0
|
|
80010c0: 2b00 cmp r3, #0
|
|
80010c2: d001 beq.n 80010c8 <SystemClock_Config+0x74>
|
|
{
|
|
Error_Handler();
|
|
80010c4: f000 f8f4 bl 80012b0 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
80010c8: 230f movs r3, #15
|
|
80010ca: 603b str r3, [r7, #0]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
80010cc: 2303 movs r3, #3
|
|
80010ce: 607b str r3, [r7, #4]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
80010d0: 2300 movs r3, #0
|
|
80010d2: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
80010d4: 2300 movs r3, #0
|
|
80010d6: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
80010d8: 2300 movs r3, #0
|
|
80010da: 613b str r3, [r7, #16]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
|
80010dc: 463b mov r3, r7
|
|
80010de: 2104 movs r1, #4
|
|
80010e0: 4618 mov r0, r3
|
|
80010e2: f002 f87d bl 80031e0 <HAL_RCC_ClockConfig>
|
|
80010e6: 4603 mov r3, r0
|
|
80010e8: 2b00 cmp r3, #0
|
|
80010ea: d001 beq.n 80010f0 <SystemClock_Config+0x9c>
|
|
{
|
|
Error_Handler();
|
|
80010ec: f000 f8e0 bl 80012b0 <Error_Handler>
|
|
}
|
|
}
|
|
80010f0: bf00 nop
|
|
80010f2: 3758 adds r7, #88 @ 0x58
|
|
80010f4: 46bd mov sp, r7
|
|
80010f6: bd80 pop {r7, pc}
|
|
|
|
080010f8 <MX_I2C2_Init>:
|
|
* @brief I2C2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C2_Init(void)
|
|
{
|
|
80010f8: b580 push {r7, lr}
|
|
80010fa: af00 add r7, sp, #0
|
|
/* USER CODE END I2C2_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C2_Init 1 */
|
|
|
|
/* USER CODE END I2C2_Init 1 */
|
|
hi2c2.Instance = I2C2;
|
|
80010fc: 4b1b ldr r3, [pc, #108] @ (800116c <MX_I2C2_Init+0x74>)
|
|
80010fe: 4a1c ldr r2, [pc, #112] @ (8001170 <MX_I2C2_Init+0x78>)
|
|
8001100: 601a str r2, [r3, #0]
|
|
hi2c2.Init.Timing = 0x10D19CE4;
|
|
8001102: 4b1a ldr r3, [pc, #104] @ (800116c <MX_I2C2_Init+0x74>)
|
|
8001104: 4a1b ldr r2, [pc, #108] @ (8001174 <MX_I2C2_Init+0x7c>)
|
|
8001106: 605a str r2, [r3, #4]
|
|
hi2c2.Init.OwnAddress1 = 0;
|
|
8001108: 4b18 ldr r3, [pc, #96] @ (800116c <MX_I2C2_Init+0x74>)
|
|
800110a: 2200 movs r2, #0
|
|
800110c: 609a str r2, [r3, #8]
|
|
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
800110e: 4b17 ldr r3, [pc, #92] @ (800116c <MX_I2C2_Init+0x74>)
|
|
8001110: 2201 movs r2, #1
|
|
8001112: 60da str r2, [r3, #12]
|
|
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8001114: 4b15 ldr r3, [pc, #84] @ (800116c <MX_I2C2_Init+0x74>)
|
|
8001116: 2200 movs r2, #0
|
|
8001118: 611a str r2, [r3, #16]
|
|
hi2c2.Init.OwnAddress2 = 0;
|
|
800111a: 4b14 ldr r3, [pc, #80] @ (800116c <MX_I2C2_Init+0x74>)
|
|
800111c: 2200 movs r2, #0
|
|
800111e: 615a str r2, [r3, #20]
|
|
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
8001120: 4b12 ldr r3, [pc, #72] @ (800116c <MX_I2C2_Init+0x74>)
|
|
8001122: 2200 movs r2, #0
|
|
8001124: 619a str r2, [r3, #24]
|
|
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8001126: 4b11 ldr r3, [pc, #68] @ (800116c <MX_I2C2_Init+0x74>)
|
|
8001128: 2200 movs r2, #0
|
|
800112a: 61da str r2, [r3, #28]
|
|
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
800112c: 4b0f ldr r3, [pc, #60] @ (800116c <MX_I2C2_Init+0x74>)
|
|
800112e: 2200 movs r2, #0
|
|
8001130: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
|
|
8001132: 480e ldr r0, [pc, #56] @ (800116c <MX_I2C2_Init+0x74>)
|
|
8001134: f000 fdf0 bl 8001d18 <HAL_I2C_Init>
|
|
8001138: 4603 mov r3, r0
|
|
800113a: 2b00 cmp r3, #0
|
|
800113c: d001 beq.n 8001142 <MX_I2C2_Init+0x4a>
|
|
{
|
|
Error_Handler();
|
|
800113e: f000 f8b7 bl 80012b0 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
8001142: 2100 movs r1, #0
|
|
8001144: 4809 ldr r0, [pc, #36] @ (800116c <MX_I2C2_Init+0x74>)
|
|
8001146: f001 fb73 bl 8002830 <HAL_I2CEx_ConfigAnalogFilter>
|
|
800114a: 4603 mov r3, r0
|
|
800114c: 2b00 cmp r3, #0
|
|
800114e: d001 beq.n 8001154 <MX_I2C2_Init+0x5c>
|
|
{
|
|
Error_Handler();
|
|
8001150: f000 f8ae bl 80012b0 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
|
|
8001154: 2100 movs r1, #0
|
|
8001156: 4805 ldr r0, [pc, #20] @ (800116c <MX_I2C2_Init+0x74>)
|
|
8001158: f001 fbb5 bl 80028c6 <HAL_I2CEx_ConfigDigitalFilter>
|
|
800115c: 4603 mov r3, r0
|
|
800115e: 2b00 cmp r3, #0
|
|
8001160: d001 beq.n 8001166 <MX_I2C2_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
8001162: f000 f8a5 bl 80012b0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C2_Init 2 */
|
|
|
|
/* USER CODE END I2C2_Init 2 */
|
|
|
|
}
|
|
8001166: bf00 nop
|
|
8001168: bd80 pop {r7, pc}
|
|
800116a: bf00 nop
|
|
800116c: 200001f0 .word 0x200001f0
|
|
8001170: 40005800 .word 0x40005800
|
|
8001174: 10d19ce4 .word 0x10d19ce4
|
|
|
|
08001178 <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
8001178: b580 push {r7, lr}
|
|
800117a: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
800117c: 4b14 ldr r3, [pc, #80] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
800117e: 4a15 ldr r2, [pc, #84] @ (80011d4 <MX_USART1_UART_Init+0x5c>)
|
|
8001180: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8001182: 4b13 ldr r3, [pc, #76] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
8001184: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8001188: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800118a: 4b11 ldr r3, [pc, #68] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
800118c: 2200 movs r2, #0
|
|
800118e: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8001190: 4b0f ldr r3, [pc, #60] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
8001192: 2200 movs r2, #0
|
|
8001194: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8001196: 4b0e ldr r3, [pc, #56] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
8001198: 2200 movs r2, #0
|
|
800119a: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
800119c: 4b0c ldr r3, [pc, #48] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
800119e: 220c movs r2, #12
|
|
80011a0: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80011a2: 4b0b ldr r3, [pc, #44] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
80011a4: 2200 movs r2, #0
|
|
80011a6: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80011a8: 4b09 ldr r3, [pc, #36] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
80011aa: 2200 movs r2, #0
|
|
80011ac: 61da str r2, [r3, #28]
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
80011ae: 4b08 ldr r3, [pc, #32] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
80011b0: 2200 movs r2, #0
|
|
80011b2: 621a str r2, [r3, #32]
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
80011b4: 4b06 ldr r3, [pc, #24] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
80011b6: 2200 movs r2, #0
|
|
80011b8: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
80011ba: 4805 ldr r0, [pc, #20] @ (80011d0 <MX_USART1_UART_Init+0x58>)
|
|
80011bc: f002 fef0 bl 8003fa0 <HAL_UART_Init>
|
|
80011c0: 4603 mov r3, r0
|
|
80011c2: 2b00 cmp r3, #0
|
|
80011c4: d001 beq.n 80011ca <MX_USART1_UART_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
80011c6: f000 f873 bl 80012b0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
80011ca: bf00 nop
|
|
80011cc: bd80 pop {r7, pc}
|
|
80011ce: bf00 nop
|
|
80011d0: 20000244 .word 0x20000244
|
|
80011d4: 40013800 .word 0x40013800
|
|
|
|
080011d8 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
80011d8: b580 push {r7, lr}
|
|
80011da: b088 sub sp, #32
|
|
80011dc: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80011de: f107 030c add.w r3, r7, #12
|
|
80011e2: 2200 movs r2, #0
|
|
80011e4: 601a str r2, [r3, #0]
|
|
80011e6: 605a str r2, [r3, #4]
|
|
80011e8: 609a str r2, [r3, #8]
|
|
80011ea: 60da str r2, [r3, #12]
|
|
80011ec: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80011ee: 4b23 ldr r3, [pc, #140] @ (800127c <MX_GPIO_Init+0xa4>)
|
|
80011f0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80011f2: 4a22 ldr r2, [pc, #136] @ (800127c <MX_GPIO_Init+0xa4>)
|
|
80011f4: f043 0301 orr.w r3, r3, #1
|
|
80011f8: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80011fa: 4b20 ldr r3, [pc, #128] @ (800127c <MX_GPIO_Init+0xa4>)
|
|
80011fc: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80011fe: f003 0301 and.w r3, r3, #1
|
|
8001202: 60bb str r3, [r7, #8]
|
|
8001204: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001206: 4b1d ldr r3, [pc, #116] @ (800127c <MX_GPIO_Init+0xa4>)
|
|
8001208: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800120a: 4a1c ldr r2, [pc, #112] @ (800127c <MX_GPIO_Init+0xa4>)
|
|
800120c: f043 0302 orr.w r3, r3, #2
|
|
8001210: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001212: 4b1a ldr r3, [pc, #104] @ (800127c <MX_GPIO_Init+0xa4>)
|
|
8001214: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001216: f003 0302 and.w r3, r3, #2
|
|
800121a: 607b str r3, [r7, #4]
|
|
800121c: 687b ldr r3, [r7, #4]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
|
|
800121e: 2200 movs r2, #0
|
|
8001220: 2120 movs r1, #32
|
|
8001222: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001226: f000 fd5f bl 8001ce8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
|
|
800122a: 2200 movs r2, #0
|
|
800122c: f44f 4180 mov.w r1, #16384 @ 0x4000
|
|
8001230: 4813 ldr r0, [pc, #76] @ (8001280 <MX_GPIO_Init+0xa8>)
|
|
8001232: f000 fd59 bl 8001ce8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin : LED1_Pin */
|
|
GPIO_InitStruct.Pin = LED1_Pin;
|
|
8001236: 2320 movs r3, #32
|
|
8001238: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
800123a: 2301 movs r3, #1
|
|
800123c: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800123e: 2300 movs r3, #0
|
|
8001240: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001242: 2300 movs r3, #0
|
|
8001244: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(LED1_GPIO_Port, &GPIO_InitStruct);
|
|
8001246: f107 030c add.w r3, r7, #12
|
|
800124a: 4619 mov r1, r3
|
|
800124c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001250: f000 fba0 bl 8001994 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : LED2_Pin */
|
|
GPIO_InitStruct.Pin = LED2_Pin;
|
|
8001254: f44f 4380 mov.w r3, #16384 @ 0x4000
|
|
8001258: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
800125a: 2301 movs r3, #1
|
|
800125c: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800125e: 2300 movs r3, #0
|
|
8001260: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001262: 2300 movs r3, #0
|
|
8001264: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
|
|
8001266: f107 030c add.w r3, r7, #12
|
|
800126a: 4619 mov r1, r3
|
|
800126c: 4804 ldr r0, [pc, #16] @ (8001280 <MX_GPIO_Init+0xa8>)
|
|
800126e: f000 fb91 bl 8001994 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8001272: bf00 nop
|
|
8001274: 3720 adds r7, #32
|
|
8001276: 46bd mov sp, r7
|
|
8001278: bd80 pop {r7, pc}
|
|
800127a: bf00 nop
|
|
800127c: 40021000 .word 0x40021000
|
|
8001280: 48000400 .word 0x48000400
|
|
|
|
08001284 <__io_putchar>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
int __io_putchar(int ch)
|
|
{
|
|
8001284: b580 push {r7, lr}
|
|
8001286: b084 sub sp, #16
|
|
8001288: af00 add r7, sp, #0
|
|
800128a: 6078 str r0, [r7, #4]
|
|
uint8_t c[1];
|
|
c[0] = ch & 0x00FF;
|
|
800128c: 687b ldr r3, [r7, #4]
|
|
800128e: b2db uxtb r3, r3
|
|
8001290: 733b strb r3, [r7, #12]
|
|
HAL_UART_Transmit(&huart1, &*c, 1, 10);
|
|
8001292: f107 010c add.w r1, r7, #12
|
|
8001296: 230a movs r3, #10
|
|
8001298: 2201 movs r2, #1
|
|
800129a: 4804 ldr r0, [pc, #16] @ (80012ac <__io_putchar+0x28>)
|
|
800129c: f002 fece bl 800403c <HAL_UART_Transmit>
|
|
return ch;
|
|
80012a0: 687b ldr r3, [r7, #4]
|
|
}
|
|
80012a2: 4618 mov r0, r3
|
|
80012a4: 3710 adds r7, #16
|
|
80012a6: 46bd mov sp, r7
|
|
80012a8: bd80 pop {r7, pc}
|
|
80012aa: bf00 nop
|
|
80012ac: 20000244 .word 0x20000244
|
|
|
|
080012b0 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
80012b0: b480 push {r7}
|
|
80012b2: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80012b4: b672 cpsid i
|
|
}
|
|
80012b6: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
80012b8: bf00 nop
|
|
80012ba: e7fd b.n 80012b8 <Error_Handler+0x8>
|
|
|
|
080012bc <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
80012bc: b480 push {r7}
|
|
80012be: b083 sub sp, #12
|
|
80012c0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80012c2: 4b0f ldr r3, [pc, #60] @ (8001300 <HAL_MspInit+0x44>)
|
|
80012c4: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80012c6: 4a0e ldr r2, [pc, #56] @ (8001300 <HAL_MspInit+0x44>)
|
|
80012c8: f043 0301 orr.w r3, r3, #1
|
|
80012cc: 6613 str r3, [r2, #96] @ 0x60
|
|
80012ce: 4b0c ldr r3, [pc, #48] @ (8001300 <HAL_MspInit+0x44>)
|
|
80012d0: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80012d2: f003 0301 and.w r3, r3, #1
|
|
80012d6: 607b str r3, [r7, #4]
|
|
80012d8: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80012da: 4b09 ldr r3, [pc, #36] @ (8001300 <HAL_MspInit+0x44>)
|
|
80012dc: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80012de: 4a08 ldr r2, [pc, #32] @ (8001300 <HAL_MspInit+0x44>)
|
|
80012e0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80012e4: 6593 str r3, [r2, #88] @ 0x58
|
|
80012e6: 4b06 ldr r3, [pc, #24] @ (8001300 <HAL_MspInit+0x44>)
|
|
80012e8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80012ea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80012ee: 603b str r3, [r7, #0]
|
|
80012f0: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
80012f2: bf00 nop
|
|
80012f4: 370c adds r7, #12
|
|
80012f6: 46bd mov sp, r7
|
|
80012f8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80012fc: 4770 bx lr
|
|
80012fe: bf00 nop
|
|
8001300: 40021000 .word 0x40021000
|
|
|
|
08001304 <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8001304: b580 push {r7, lr}
|
|
8001306: b0ac sub sp, #176 @ 0xb0
|
|
8001308: af00 add r7, sp, #0
|
|
800130a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800130c: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8001310: 2200 movs r2, #0
|
|
8001312: 601a str r2, [r3, #0]
|
|
8001314: 605a str r2, [r3, #4]
|
|
8001316: 609a str r2, [r3, #8]
|
|
8001318: 60da str r2, [r3, #12]
|
|
800131a: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
800131c: f107 0314 add.w r3, r7, #20
|
|
8001320: 2288 movs r2, #136 @ 0x88
|
|
8001322: 2100 movs r1, #0
|
|
8001324: 4618 mov r0, r3
|
|
8001326: f004 fa45 bl 80057b4 <memset>
|
|
if(hi2c->Instance==I2C2)
|
|
800132a: 687b ldr r3, [r7, #4]
|
|
800132c: 681b ldr r3, [r3, #0]
|
|
800132e: 4a21 ldr r2, [pc, #132] @ (80013b4 <HAL_I2C_MspInit+0xb0>)
|
|
8001330: 4293 cmp r3, r2
|
|
8001332: d13b bne.n 80013ac <HAL_I2C_MspInit+0xa8>
|
|
|
|
/* USER CODE END I2C2_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
|
|
8001334: 2380 movs r3, #128 @ 0x80
|
|
8001336: 617b str r3, [r7, #20]
|
|
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
|
|
8001338: 2300 movs r3, #0
|
|
800133a: 66bb str r3, [r7, #104] @ 0x68
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
800133c: f107 0314 add.w r3, r7, #20
|
|
8001340: 4618 mov r0, r3
|
|
8001342: f002 f971 bl 8003628 <HAL_RCCEx_PeriphCLKConfig>
|
|
8001346: 4603 mov r3, r0
|
|
8001348: 2b00 cmp r3, #0
|
|
800134a: d001 beq.n 8001350 <HAL_I2C_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
800134c: f7ff ffb0 bl 80012b0 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001350: 4b19 ldr r3, [pc, #100] @ (80013b8 <HAL_I2C_MspInit+0xb4>)
|
|
8001352: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001354: 4a18 ldr r2, [pc, #96] @ (80013b8 <HAL_I2C_MspInit+0xb4>)
|
|
8001356: f043 0302 orr.w r3, r3, #2
|
|
800135a: 64d3 str r3, [r2, #76] @ 0x4c
|
|
800135c: 4b16 ldr r3, [pc, #88] @ (80013b8 <HAL_I2C_MspInit+0xb4>)
|
|
800135e: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001360: f003 0302 and.w r3, r3, #2
|
|
8001364: 613b str r3, [r7, #16]
|
|
8001366: 693b ldr r3, [r7, #16]
|
|
/**I2C2 GPIO Configuration
|
|
PB10 ------> I2C2_SCL
|
|
PB11 ------> I2C2_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
|
|
8001368: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
800136c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8001370: 2312 movs r3, #18
|
|
8001372: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001376: 2300 movs r3, #0
|
|
8001378: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800137c: 2303 movs r3, #3
|
|
800137e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
|
|
8001382: 2304 movs r3, #4
|
|
8001384: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001388: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
800138c: 4619 mov r1, r3
|
|
800138e: 480b ldr r0, [pc, #44] @ (80013bc <HAL_I2C_MspInit+0xb8>)
|
|
8001390: f000 fb00 bl 8001994 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C2_CLK_ENABLE();
|
|
8001394: 4b08 ldr r3, [pc, #32] @ (80013b8 <HAL_I2C_MspInit+0xb4>)
|
|
8001396: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001398: 4a07 ldr r2, [pc, #28] @ (80013b8 <HAL_I2C_MspInit+0xb4>)
|
|
800139a: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
800139e: 6593 str r3, [r2, #88] @ 0x58
|
|
80013a0: 4b05 ldr r3, [pc, #20] @ (80013b8 <HAL_I2C_MspInit+0xb4>)
|
|
80013a2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80013a4: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80013a8: 60fb str r3, [r7, #12]
|
|
80013aa: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END I2C2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80013ac: bf00 nop
|
|
80013ae: 37b0 adds r7, #176 @ 0xb0
|
|
80013b0: 46bd mov sp, r7
|
|
80013b2: bd80 pop {r7, pc}
|
|
80013b4: 40005800 .word 0x40005800
|
|
80013b8: 40021000 .word 0x40021000
|
|
80013bc: 48000400 .word 0x48000400
|
|
|
|
080013c0 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
80013c0: b580 push {r7, lr}
|
|
80013c2: b0ac sub sp, #176 @ 0xb0
|
|
80013c4: af00 add r7, sp, #0
|
|
80013c6: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80013c8: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
80013cc: 2200 movs r2, #0
|
|
80013ce: 601a str r2, [r3, #0]
|
|
80013d0: 605a str r2, [r3, #4]
|
|
80013d2: 609a str r2, [r3, #8]
|
|
80013d4: 60da str r2, [r3, #12]
|
|
80013d6: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
80013d8: f107 0314 add.w r3, r7, #20
|
|
80013dc: 2288 movs r2, #136 @ 0x88
|
|
80013de: 2100 movs r1, #0
|
|
80013e0: 4618 mov r0, r3
|
|
80013e2: f004 f9e7 bl 80057b4 <memset>
|
|
if(huart->Instance==USART1)
|
|
80013e6: 687b ldr r3, [r7, #4]
|
|
80013e8: 681b ldr r3, [r3, #0]
|
|
80013ea: 4a21 ldr r2, [pc, #132] @ (8001470 <HAL_UART_MspInit+0xb0>)
|
|
80013ec: 4293 cmp r3, r2
|
|
80013ee: d13a bne.n 8001466 <HAL_UART_MspInit+0xa6>
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|
80013f0: 2301 movs r3, #1
|
|
80013f2: 617b str r3, [r7, #20]
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|
80013f4: 2300 movs r3, #0
|
|
80013f6: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
80013f8: f107 0314 add.w r3, r7, #20
|
|
80013fc: 4618 mov r0, r3
|
|
80013fe: f002 f913 bl 8003628 <HAL_RCCEx_PeriphCLKConfig>
|
|
8001402: 4603 mov r3, r0
|
|
8001404: 2b00 cmp r3, #0
|
|
8001406: d001 beq.n 800140c <HAL_UART_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8001408: f7ff ff52 bl 80012b0 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
800140c: 4b19 ldr r3, [pc, #100] @ (8001474 <HAL_UART_MspInit+0xb4>)
|
|
800140e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001410: 4a18 ldr r2, [pc, #96] @ (8001474 <HAL_UART_MspInit+0xb4>)
|
|
8001412: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8001416: 6613 str r3, [r2, #96] @ 0x60
|
|
8001418: 4b16 ldr r3, [pc, #88] @ (8001474 <HAL_UART_MspInit+0xb4>)
|
|
800141a: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800141c: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8001420: 613b str r3, [r7, #16]
|
|
8001422: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001424: 4b13 ldr r3, [pc, #76] @ (8001474 <HAL_UART_MspInit+0xb4>)
|
|
8001426: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001428: 4a12 ldr r2, [pc, #72] @ (8001474 <HAL_UART_MspInit+0xb4>)
|
|
800142a: f043 0302 orr.w r3, r3, #2
|
|
800142e: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001430: 4b10 ldr r3, [pc, #64] @ (8001474 <HAL_UART_MspInit+0xb4>)
|
|
8001432: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001434: f003 0302 and.w r3, r3, #2
|
|
8001438: 60fb str r3, [r7, #12]
|
|
800143a: 68fb ldr r3, [r7, #12]
|
|
/**USART1 GPIO Configuration
|
|
PB6 ------> USART1_TX
|
|
PB7 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
800143c: 23c0 movs r3, #192 @ 0xc0
|
|
800143e: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001442: 2302 movs r3, #2
|
|
8001444: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001448: 2300 movs r3, #0
|
|
800144a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800144e: 2303 movs r3, #3
|
|
8001450: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
8001454: 2307 movs r3, #7
|
|
8001456: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
800145a: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
800145e: 4619 mov r1, r3
|
|
8001460: 4805 ldr r0, [pc, #20] @ (8001478 <HAL_UART_MspInit+0xb8>)
|
|
8001462: f000 fa97 bl 8001994 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END USART1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8001466: bf00 nop
|
|
8001468: 37b0 adds r7, #176 @ 0xb0
|
|
800146a: 46bd mov sp, r7
|
|
800146c: bd80 pop {r7, pc}
|
|
800146e: bf00 nop
|
|
8001470: 40013800 .word 0x40013800
|
|
8001474: 40021000 .word 0x40021000
|
|
8001478: 48000400 .word 0x48000400
|
|
|
|
0800147c <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
800147c: b480 push {r7}
|
|
800147e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8001480: bf00 nop
|
|
8001482: e7fd b.n 8001480 <NMI_Handler+0x4>
|
|
|
|
08001484 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8001484: b480 push {r7}
|
|
8001486: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8001488: bf00 nop
|
|
800148a: e7fd b.n 8001488 <HardFault_Handler+0x4>
|
|
|
|
0800148c <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
800148c: b480 push {r7}
|
|
800148e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8001490: bf00 nop
|
|
8001492: e7fd b.n 8001490 <MemManage_Handler+0x4>
|
|
|
|
08001494 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8001494: b480 push {r7}
|
|
8001496: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8001498: bf00 nop
|
|
800149a: e7fd b.n 8001498 <BusFault_Handler+0x4>
|
|
|
|
0800149c <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
800149c: b480 push {r7}
|
|
800149e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
80014a0: bf00 nop
|
|
80014a2: e7fd b.n 80014a0 <UsageFault_Handler+0x4>
|
|
|
|
080014a4 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
80014a4: b480 push {r7}
|
|
80014a6: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
80014a8: bf00 nop
|
|
80014aa: 46bd mov sp, r7
|
|
80014ac: f85d 7b04 ldr.w r7, [sp], #4
|
|
80014b0: 4770 bx lr
|
|
|
|
080014b2 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
80014b2: b480 push {r7}
|
|
80014b4: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
80014b6: bf00 nop
|
|
80014b8: 46bd mov sp, r7
|
|
80014ba: f85d 7b04 ldr.w r7, [sp], #4
|
|
80014be: 4770 bx lr
|
|
|
|
080014c0 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
80014c0: b480 push {r7}
|
|
80014c2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
80014c4: bf00 nop
|
|
80014c6: 46bd mov sp, r7
|
|
80014c8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80014cc: 4770 bx lr
|
|
|
|
080014ce <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
80014ce: b580 push {r7, lr}
|
|
80014d0: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
80014d2: f000 f959 bl 8001788 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
80014d6: bf00 nop
|
|
80014d8: bd80 pop {r7, pc}
|
|
|
|
080014da <_getpid>:
|
|
void initialise_monitor_handles()
|
|
{
|
|
}
|
|
|
|
int _getpid(void)
|
|
{
|
|
80014da: b480 push {r7}
|
|
80014dc: af00 add r7, sp, #0
|
|
return 1;
|
|
80014de: 2301 movs r3, #1
|
|
}
|
|
80014e0: 4618 mov r0, r3
|
|
80014e2: 46bd mov sp, r7
|
|
80014e4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80014e8: 4770 bx lr
|
|
|
|
080014ea <_kill>:
|
|
|
|
int _kill(int pid, int sig)
|
|
{
|
|
80014ea: b580 push {r7, lr}
|
|
80014ec: b082 sub sp, #8
|
|
80014ee: af00 add r7, sp, #0
|
|
80014f0: 6078 str r0, [r7, #4]
|
|
80014f2: 6039 str r1, [r7, #0]
|
|
(void)pid;
|
|
(void)sig;
|
|
errno = EINVAL;
|
|
80014f4: f004 f9b0 bl 8005858 <__errno>
|
|
80014f8: 4603 mov r3, r0
|
|
80014fa: 2216 movs r2, #22
|
|
80014fc: 601a str r2, [r3, #0]
|
|
return -1;
|
|
80014fe: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
8001502: 4618 mov r0, r3
|
|
8001504: 3708 adds r7, #8
|
|
8001506: 46bd mov sp, r7
|
|
8001508: bd80 pop {r7, pc}
|
|
|
|
0800150a <_exit>:
|
|
|
|
void _exit (int status)
|
|
{
|
|
800150a: b580 push {r7, lr}
|
|
800150c: b082 sub sp, #8
|
|
800150e: af00 add r7, sp, #0
|
|
8001510: 6078 str r0, [r7, #4]
|
|
_kill(status, -1);
|
|
8001512: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8001516: 6878 ldr r0, [r7, #4]
|
|
8001518: f7ff ffe7 bl 80014ea <_kill>
|
|
while (1) {} /* Make sure we hang here */
|
|
800151c: bf00 nop
|
|
800151e: e7fd b.n 800151c <_exit+0x12>
|
|
|
|
08001520 <_read>:
|
|
}
|
|
|
|
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
|
{
|
|
8001520: b580 push {r7, lr}
|
|
8001522: b086 sub sp, #24
|
|
8001524: af00 add r7, sp, #0
|
|
8001526: 60f8 str r0, [r7, #12]
|
|
8001528: 60b9 str r1, [r7, #8]
|
|
800152a: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
800152c: 2300 movs r3, #0
|
|
800152e: 617b str r3, [r7, #20]
|
|
8001530: e00a b.n 8001548 <_read+0x28>
|
|
{
|
|
*ptr++ = __io_getchar();
|
|
8001532: f3af 8000 nop.w
|
|
8001536: 4601 mov r1, r0
|
|
8001538: 68bb ldr r3, [r7, #8]
|
|
800153a: 1c5a adds r2, r3, #1
|
|
800153c: 60ba str r2, [r7, #8]
|
|
800153e: b2ca uxtb r2, r1
|
|
8001540: 701a strb r2, [r3, #0]
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8001542: 697b ldr r3, [r7, #20]
|
|
8001544: 3301 adds r3, #1
|
|
8001546: 617b str r3, [r7, #20]
|
|
8001548: 697a ldr r2, [r7, #20]
|
|
800154a: 687b ldr r3, [r7, #4]
|
|
800154c: 429a cmp r2, r3
|
|
800154e: dbf0 blt.n 8001532 <_read+0x12>
|
|
}
|
|
|
|
return len;
|
|
8001550: 687b ldr r3, [r7, #4]
|
|
}
|
|
8001552: 4618 mov r0, r3
|
|
8001554: 3718 adds r7, #24
|
|
8001556: 46bd mov sp, r7
|
|
8001558: bd80 pop {r7, pc}
|
|
|
|
0800155a <_write>:
|
|
|
|
__attribute__((weak)) int _write(int file, char *ptr, int len)
|
|
{
|
|
800155a: b580 push {r7, lr}
|
|
800155c: b086 sub sp, #24
|
|
800155e: af00 add r7, sp, #0
|
|
8001560: 60f8 str r0, [r7, #12]
|
|
8001562: 60b9 str r1, [r7, #8]
|
|
8001564: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8001566: 2300 movs r3, #0
|
|
8001568: 617b str r3, [r7, #20]
|
|
800156a: e009 b.n 8001580 <_write+0x26>
|
|
{
|
|
__io_putchar(*ptr++);
|
|
800156c: 68bb ldr r3, [r7, #8]
|
|
800156e: 1c5a adds r2, r3, #1
|
|
8001570: 60ba str r2, [r7, #8]
|
|
8001572: 781b ldrb r3, [r3, #0]
|
|
8001574: 4618 mov r0, r3
|
|
8001576: f7ff fe85 bl 8001284 <__io_putchar>
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
800157a: 697b ldr r3, [r7, #20]
|
|
800157c: 3301 adds r3, #1
|
|
800157e: 617b str r3, [r7, #20]
|
|
8001580: 697a ldr r2, [r7, #20]
|
|
8001582: 687b ldr r3, [r7, #4]
|
|
8001584: 429a cmp r2, r3
|
|
8001586: dbf1 blt.n 800156c <_write+0x12>
|
|
}
|
|
return len;
|
|
8001588: 687b ldr r3, [r7, #4]
|
|
}
|
|
800158a: 4618 mov r0, r3
|
|
800158c: 3718 adds r7, #24
|
|
800158e: 46bd mov sp, r7
|
|
8001590: bd80 pop {r7, pc}
|
|
|
|
08001592 <_close>:
|
|
|
|
int _close(int file)
|
|
{
|
|
8001592: b480 push {r7}
|
|
8001594: b083 sub sp, #12
|
|
8001596: af00 add r7, sp, #0
|
|
8001598: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return -1;
|
|
800159a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
800159e: 4618 mov r0, r3
|
|
80015a0: 370c adds r7, #12
|
|
80015a2: 46bd mov sp, r7
|
|
80015a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015a8: 4770 bx lr
|
|
|
|
080015aa <_fstat>:
|
|
|
|
|
|
int _fstat(int file, struct stat *st)
|
|
{
|
|
80015aa: b480 push {r7}
|
|
80015ac: b083 sub sp, #12
|
|
80015ae: af00 add r7, sp, #0
|
|
80015b0: 6078 str r0, [r7, #4]
|
|
80015b2: 6039 str r1, [r7, #0]
|
|
(void)file;
|
|
st->st_mode = S_IFCHR;
|
|
80015b4: 683b ldr r3, [r7, #0]
|
|
80015b6: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
80015ba: 605a str r2, [r3, #4]
|
|
return 0;
|
|
80015bc: 2300 movs r3, #0
|
|
}
|
|
80015be: 4618 mov r0, r3
|
|
80015c0: 370c adds r7, #12
|
|
80015c2: 46bd mov sp, r7
|
|
80015c4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015c8: 4770 bx lr
|
|
|
|
080015ca <_isatty>:
|
|
|
|
int _isatty(int file)
|
|
{
|
|
80015ca: b480 push {r7}
|
|
80015cc: b083 sub sp, #12
|
|
80015ce: af00 add r7, sp, #0
|
|
80015d0: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return 1;
|
|
80015d2: 2301 movs r3, #1
|
|
}
|
|
80015d4: 4618 mov r0, r3
|
|
80015d6: 370c adds r7, #12
|
|
80015d8: 46bd mov sp, r7
|
|
80015da: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015de: 4770 bx lr
|
|
|
|
080015e0 <_lseek>:
|
|
|
|
int _lseek(int file, int ptr, int dir)
|
|
{
|
|
80015e0: b480 push {r7}
|
|
80015e2: b085 sub sp, #20
|
|
80015e4: af00 add r7, sp, #0
|
|
80015e6: 60f8 str r0, [r7, #12]
|
|
80015e8: 60b9 str r1, [r7, #8]
|
|
80015ea: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
(void)ptr;
|
|
(void)dir;
|
|
return 0;
|
|
80015ec: 2300 movs r3, #0
|
|
}
|
|
80015ee: 4618 mov r0, r3
|
|
80015f0: 3714 adds r7, #20
|
|
80015f2: 46bd mov sp, r7
|
|
80015f4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015f8: 4770 bx lr
|
|
...
|
|
|
|
080015fc <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
80015fc: b580 push {r7, lr}
|
|
80015fe: b086 sub sp, #24
|
|
8001600: af00 add r7, sp, #0
|
|
8001602: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
8001604: 4a14 ldr r2, [pc, #80] @ (8001658 <_sbrk+0x5c>)
|
|
8001606: 4b15 ldr r3, [pc, #84] @ (800165c <_sbrk+0x60>)
|
|
8001608: 1ad3 subs r3, r2, r3
|
|
800160a: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
800160c: 697b ldr r3, [r7, #20]
|
|
800160e: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
8001610: 4b13 ldr r3, [pc, #76] @ (8001660 <_sbrk+0x64>)
|
|
8001612: 681b ldr r3, [r3, #0]
|
|
8001614: 2b00 cmp r3, #0
|
|
8001616: d102 bne.n 800161e <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
8001618: 4b11 ldr r3, [pc, #68] @ (8001660 <_sbrk+0x64>)
|
|
800161a: 4a12 ldr r2, [pc, #72] @ (8001664 <_sbrk+0x68>)
|
|
800161c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
800161e: 4b10 ldr r3, [pc, #64] @ (8001660 <_sbrk+0x64>)
|
|
8001620: 681a ldr r2, [r3, #0]
|
|
8001622: 687b ldr r3, [r7, #4]
|
|
8001624: 4413 add r3, r2
|
|
8001626: 693a ldr r2, [r7, #16]
|
|
8001628: 429a cmp r2, r3
|
|
800162a: d207 bcs.n 800163c <_sbrk+0x40>
|
|
{
|
|
errno = ENOMEM;
|
|
800162c: f004 f914 bl 8005858 <__errno>
|
|
8001630: 4603 mov r3, r0
|
|
8001632: 220c movs r2, #12
|
|
8001634: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
8001636: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800163a: e009 b.n 8001650 <_sbrk+0x54>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
800163c: 4b08 ldr r3, [pc, #32] @ (8001660 <_sbrk+0x64>)
|
|
800163e: 681b ldr r3, [r3, #0]
|
|
8001640: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
8001642: 4b07 ldr r3, [pc, #28] @ (8001660 <_sbrk+0x64>)
|
|
8001644: 681a ldr r2, [r3, #0]
|
|
8001646: 687b ldr r3, [r7, #4]
|
|
8001648: 4413 add r3, r2
|
|
800164a: 4a05 ldr r2, [pc, #20] @ (8001660 <_sbrk+0x64>)
|
|
800164c: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
800164e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8001650: 4618 mov r0, r3
|
|
8001652: 3718 adds r7, #24
|
|
8001654: 46bd mov sp, r7
|
|
8001656: bd80 pop {r7, pc}
|
|
8001658: 20018000 .word 0x20018000
|
|
800165c: 00000400 .word 0x00000400
|
|
8001660: 200002cc .word 0x200002cc
|
|
8001664: 20000420 .word 0x20000420
|
|
|
|
08001668 <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
8001668: b480 push {r7}
|
|
800166a: af00 add r7, sp, #0
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
|
#endif
|
|
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
|
800166c: 4b06 ldr r3, [pc, #24] @ (8001688 <SystemInit+0x20>)
|
|
800166e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8001672: 4a05 ldr r2, [pc, #20] @ (8001688 <SystemInit+0x20>)
|
|
8001674: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8001678: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
#endif
|
|
}
|
|
800167c: bf00 nop
|
|
800167e: 46bd mov sp, r7
|
|
8001680: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001684: 4770 bx lr
|
|
8001686: bf00 nop
|
|
8001688: e000ed00 .word 0xe000ed00
|
|
|
|
0800168c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
800168c: f8df d034 ldr.w sp, [pc, #52] @ 80016c4 <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001690: f7ff ffea bl 8001668 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001694: 480c ldr r0, [pc, #48] @ (80016c8 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
8001696: 490d ldr r1, [pc, #52] @ (80016cc <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8001698: 4a0d ldr r2, [pc, #52] @ (80016d0 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
800169a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800169c: e002 b.n 80016a4 <LoopCopyDataInit>
|
|
|
|
0800169e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800169e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
80016a0: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
80016a2: 3304 adds r3, #4
|
|
|
|
080016a4 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
80016a4: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
80016a6: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
80016a8: d3f9 bcc.n 800169e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
80016aa: 4a0a ldr r2, [pc, #40] @ (80016d4 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
80016ac: 4c0a ldr r4, [pc, #40] @ (80016d8 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
80016ae: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
80016b0: e001 b.n 80016b6 <LoopFillZerobss>
|
|
|
|
080016b2 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
80016b2: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
80016b4: 3204 adds r2, #4
|
|
|
|
080016b6 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
80016b6: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
80016b8: d3fb bcc.n 80016b2 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
80016ba: f004 f8d3 bl 8005864 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
80016be: f7ff fc83 bl 8000fc8 <main>
|
|
|
|
080016c2 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
80016c2: e7fe b.n 80016c2 <LoopForever>
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
80016c4: 20018000 .word 0x20018000
|
|
ldr r0, =_sdata
|
|
80016c8: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
80016cc: 200001d4 .word 0x200001d4
|
|
ldr r2, =_sidata
|
|
80016d0: 080078dc .word 0x080078dc
|
|
ldr r2, =_sbss
|
|
80016d4: 200001d4 .word 0x200001d4
|
|
ldr r4, =_ebss
|
|
80016d8: 20000420 .word 0x20000420
|
|
|
|
080016dc <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80016dc: e7fe b.n 80016dc <ADC1_2_IRQHandler>
|
|
|
|
080016de <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
80016de: b580 push {r7, lr}
|
|
80016e0: b082 sub sp, #8
|
|
80016e2: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80016e4: 2300 movs r3, #0
|
|
80016e6: 71fb strb r3, [r7, #7]
|
|
#if (PREFETCH_ENABLE != 0)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
80016e8: 2003 movs r0, #3
|
|
80016ea: f000 f91f bl 800192c <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
80016ee: 200f movs r0, #15
|
|
80016f0: f000 f80e bl 8001710 <HAL_InitTick>
|
|
80016f4: 4603 mov r3, r0
|
|
80016f6: 2b00 cmp r3, #0
|
|
80016f8: d002 beq.n 8001700 <HAL_Init+0x22>
|
|
{
|
|
status = HAL_ERROR;
|
|
80016fa: 2301 movs r3, #1
|
|
80016fc: 71fb strb r3, [r7, #7]
|
|
80016fe: e001 b.n 8001704 <HAL_Init+0x26>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8001700: f7ff fddc bl 80012bc <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8001704: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8001706: 4618 mov r0, r3
|
|
8001708: 3708 adds r7, #8
|
|
800170a: 46bd mov sp, r7
|
|
800170c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001710 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8001710: b580 push {r7, lr}
|
|
8001712: b084 sub sp, #16
|
|
8001714: af00 add r7, sp, #0
|
|
8001716: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001718: 2300 movs r3, #0
|
|
800171a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
800171c: 4b17 ldr r3, [pc, #92] @ (800177c <HAL_InitTick+0x6c>)
|
|
800171e: 781b ldrb r3, [r3, #0]
|
|
8001720: 2b00 cmp r3, #0
|
|
8001722: d023 beq.n 800176c <HAL_InitTick+0x5c>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
|
|
8001724: 4b16 ldr r3, [pc, #88] @ (8001780 <HAL_InitTick+0x70>)
|
|
8001726: 681a ldr r2, [r3, #0]
|
|
8001728: 4b14 ldr r3, [pc, #80] @ (800177c <HAL_InitTick+0x6c>)
|
|
800172a: 781b ldrb r3, [r3, #0]
|
|
800172c: 4619 mov r1, r3
|
|
800172e: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001732: fbb3 f3f1 udiv r3, r3, r1
|
|
8001736: fbb2 f3f3 udiv r3, r2, r3
|
|
800173a: 4618 mov r0, r3
|
|
800173c: f000 f91d bl 800197a <HAL_SYSTICK_Config>
|
|
8001740: 4603 mov r3, r0
|
|
8001742: 2b00 cmp r3, #0
|
|
8001744: d10f bne.n 8001766 <HAL_InitTick+0x56>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8001746: 687b ldr r3, [r7, #4]
|
|
8001748: 2b0f cmp r3, #15
|
|
800174a: d809 bhi.n 8001760 <HAL_InitTick+0x50>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
800174c: 2200 movs r2, #0
|
|
800174e: 6879 ldr r1, [r7, #4]
|
|
8001750: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8001754: f000 f8f5 bl 8001942 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8001758: 4a0a ldr r2, [pc, #40] @ (8001784 <HAL_InitTick+0x74>)
|
|
800175a: 687b ldr r3, [r7, #4]
|
|
800175c: 6013 str r3, [r2, #0]
|
|
800175e: e007 b.n 8001770 <HAL_InitTick+0x60>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8001760: 2301 movs r3, #1
|
|
8001762: 73fb strb r3, [r7, #15]
|
|
8001764: e004 b.n 8001770 <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8001766: 2301 movs r3, #1
|
|
8001768: 73fb strb r3, [r7, #15]
|
|
800176a: e001 b.n 8001770 <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800176c: 2301 movs r3, #1
|
|
800176e: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8001770: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001772: 4618 mov r0, r3
|
|
8001774: 3710 adds r7, #16
|
|
8001776: 46bd mov sp, r7
|
|
8001778: bd80 pop {r7, pc}
|
|
800177a: bf00 nop
|
|
800177c: 20000008 .word 0x20000008
|
|
8001780: 20000000 .word 0x20000000
|
|
8001784: 20000004 .word 0x20000004
|
|
|
|
08001788 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8001788: b480 push {r7}
|
|
800178a: af00 add r7, sp, #0
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
800178c: 4b06 ldr r3, [pc, #24] @ (80017a8 <HAL_IncTick+0x20>)
|
|
800178e: 781b ldrb r3, [r3, #0]
|
|
8001790: 461a mov r2, r3
|
|
8001792: 4b06 ldr r3, [pc, #24] @ (80017ac <HAL_IncTick+0x24>)
|
|
8001794: 681b ldr r3, [r3, #0]
|
|
8001796: 4413 add r3, r2
|
|
8001798: 4a04 ldr r2, [pc, #16] @ (80017ac <HAL_IncTick+0x24>)
|
|
800179a: 6013 str r3, [r2, #0]
|
|
}
|
|
800179c: bf00 nop
|
|
800179e: 46bd mov sp, r7
|
|
80017a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80017a4: 4770 bx lr
|
|
80017a6: bf00 nop
|
|
80017a8: 20000008 .word 0x20000008
|
|
80017ac: 200002d0 .word 0x200002d0
|
|
|
|
080017b0 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80017b0: b480 push {r7}
|
|
80017b2: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80017b4: 4b03 ldr r3, [pc, #12] @ (80017c4 <HAL_GetTick+0x14>)
|
|
80017b6: 681b ldr r3, [r3, #0]
|
|
}
|
|
80017b8: 4618 mov r0, r3
|
|
80017ba: 46bd mov sp, r7
|
|
80017bc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80017c0: 4770 bx lr
|
|
80017c2: bf00 nop
|
|
80017c4: 200002d0 .word 0x200002d0
|
|
|
|
080017c8 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80017c8: b480 push {r7}
|
|
80017ca: b085 sub sp, #20
|
|
80017cc: af00 add r7, sp, #0
|
|
80017ce: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80017d0: 687b ldr r3, [r7, #4]
|
|
80017d2: f003 0307 and.w r3, r3, #7
|
|
80017d6: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80017d8: 4b0c ldr r3, [pc, #48] @ (800180c <__NVIC_SetPriorityGrouping+0x44>)
|
|
80017da: 68db ldr r3, [r3, #12]
|
|
80017dc: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80017de: 68ba ldr r2, [r7, #8]
|
|
80017e0: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80017e4: 4013 ands r3, r2
|
|
80017e6: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80017e8: 68fb ldr r3, [r7, #12]
|
|
80017ea: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80017ec: 68bb ldr r3, [r7, #8]
|
|
80017ee: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80017f0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80017f4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80017f8: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80017fa: 4a04 ldr r2, [pc, #16] @ (800180c <__NVIC_SetPriorityGrouping+0x44>)
|
|
80017fc: 68bb ldr r3, [r7, #8]
|
|
80017fe: 60d3 str r3, [r2, #12]
|
|
}
|
|
8001800: bf00 nop
|
|
8001802: 3714 adds r7, #20
|
|
8001804: 46bd mov sp, r7
|
|
8001806: f85d 7b04 ldr.w r7, [sp], #4
|
|
800180a: 4770 bx lr
|
|
800180c: e000ed00 .word 0xe000ed00
|
|
|
|
08001810 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8001810: b480 push {r7}
|
|
8001812: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8001814: 4b04 ldr r3, [pc, #16] @ (8001828 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8001816: 68db ldr r3, [r3, #12]
|
|
8001818: 0a1b lsrs r3, r3, #8
|
|
800181a: f003 0307 and.w r3, r3, #7
|
|
}
|
|
800181e: 4618 mov r0, r3
|
|
8001820: 46bd mov sp, r7
|
|
8001822: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001826: 4770 bx lr
|
|
8001828: e000ed00 .word 0xe000ed00
|
|
|
|
0800182c <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
800182c: b480 push {r7}
|
|
800182e: b083 sub sp, #12
|
|
8001830: af00 add r7, sp, #0
|
|
8001832: 4603 mov r3, r0
|
|
8001834: 6039 str r1, [r7, #0]
|
|
8001836: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001838: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800183c: 2b00 cmp r3, #0
|
|
800183e: db0a blt.n 8001856 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001840: 683b ldr r3, [r7, #0]
|
|
8001842: b2da uxtb r2, r3
|
|
8001844: 490c ldr r1, [pc, #48] @ (8001878 <__NVIC_SetPriority+0x4c>)
|
|
8001846: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800184a: 0112 lsls r2, r2, #4
|
|
800184c: b2d2 uxtb r2, r2
|
|
800184e: 440b add r3, r1
|
|
8001850: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001854: e00a b.n 800186c <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001856: 683b ldr r3, [r7, #0]
|
|
8001858: b2da uxtb r2, r3
|
|
800185a: 4908 ldr r1, [pc, #32] @ (800187c <__NVIC_SetPriority+0x50>)
|
|
800185c: 79fb ldrb r3, [r7, #7]
|
|
800185e: f003 030f and.w r3, r3, #15
|
|
8001862: 3b04 subs r3, #4
|
|
8001864: 0112 lsls r2, r2, #4
|
|
8001866: b2d2 uxtb r2, r2
|
|
8001868: 440b add r3, r1
|
|
800186a: 761a strb r2, [r3, #24]
|
|
}
|
|
800186c: bf00 nop
|
|
800186e: 370c adds r7, #12
|
|
8001870: 46bd mov sp, r7
|
|
8001872: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001876: 4770 bx lr
|
|
8001878: e000e100 .word 0xe000e100
|
|
800187c: e000ed00 .word 0xe000ed00
|
|
|
|
08001880 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001880: b480 push {r7}
|
|
8001882: b089 sub sp, #36 @ 0x24
|
|
8001884: af00 add r7, sp, #0
|
|
8001886: 60f8 str r0, [r7, #12]
|
|
8001888: 60b9 str r1, [r7, #8]
|
|
800188a: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
800188c: 68fb ldr r3, [r7, #12]
|
|
800188e: f003 0307 and.w r3, r3, #7
|
|
8001892: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8001894: 69fb ldr r3, [r7, #28]
|
|
8001896: f1c3 0307 rsb r3, r3, #7
|
|
800189a: 2b04 cmp r3, #4
|
|
800189c: bf28 it cs
|
|
800189e: 2304 movcs r3, #4
|
|
80018a0: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80018a2: 69fb ldr r3, [r7, #28]
|
|
80018a4: 3304 adds r3, #4
|
|
80018a6: 2b06 cmp r3, #6
|
|
80018a8: d902 bls.n 80018b0 <NVIC_EncodePriority+0x30>
|
|
80018aa: 69fb ldr r3, [r7, #28]
|
|
80018ac: 3b03 subs r3, #3
|
|
80018ae: e000 b.n 80018b2 <NVIC_EncodePriority+0x32>
|
|
80018b0: 2300 movs r3, #0
|
|
80018b2: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80018b4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80018b8: 69bb ldr r3, [r7, #24]
|
|
80018ba: fa02 f303 lsl.w r3, r2, r3
|
|
80018be: 43da mvns r2, r3
|
|
80018c0: 68bb ldr r3, [r7, #8]
|
|
80018c2: 401a ands r2, r3
|
|
80018c4: 697b ldr r3, [r7, #20]
|
|
80018c6: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80018c8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80018cc: 697b ldr r3, [r7, #20]
|
|
80018ce: fa01 f303 lsl.w r3, r1, r3
|
|
80018d2: 43d9 mvns r1, r3
|
|
80018d4: 687b ldr r3, [r7, #4]
|
|
80018d6: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80018d8: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80018da: 4618 mov r0, r3
|
|
80018dc: 3724 adds r7, #36 @ 0x24
|
|
80018de: 46bd mov sp, r7
|
|
80018e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80018e4: 4770 bx lr
|
|
...
|
|
|
|
080018e8 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80018e8: b580 push {r7, lr}
|
|
80018ea: b082 sub sp, #8
|
|
80018ec: af00 add r7, sp, #0
|
|
80018ee: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80018f0: 687b ldr r3, [r7, #4]
|
|
80018f2: 3b01 subs r3, #1
|
|
80018f4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80018f8: d301 bcc.n 80018fe <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
80018fa: 2301 movs r3, #1
|
|
80018fc: e00f b.n 800191e <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
80018fe: 4a0a ldr r2, [pc, #40] @ (8001928 <SysTick_Config+0x40>)
|
|
8001900: 687b ldr r3, [r7, #4]
|
|
8001902: 3b01 subs r3, #1
|
|
8001904: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8001906: 210f movs r1, #15
|
|
8001908: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800190c: f7ff ff8e bl 800182c <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8001910: 4b05 ldr r3, [pc, #20] @ (8001928 <SysTick_Config+0x40>)
|
|
8001912: 2200 movs r2, #0
|
|
8001914: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8001916: 4b04 ldr r3, [pc, #16] @ (8001928 <SysTick_Config+0x40>)
|
|
8001918: 2207 movs r2, #7
|
|
800191a: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
800191c: 2300 movs r3, #0
|
|
}
|
|
800191e: 4618 mov r0, r3
|
|
8001920: 3708 adds r7, #8
|
|
8001922: 46bd mov sp, r7
|
|
8001924: bd80 pop {r7, pc}
|
|
8001926: bf00 nop
|
|
8001928: e000e010 .word 0xe000e010
|
|
|
|
0800192c <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800192c: b580 push {r7, lr}
|
|
800192e: b082 sub sp, #8
|
|
8001930: af00 add r7, sp, #0
|
|
8001932: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8001934: 6878 ldr r0, [r7, #4]
|
|
8001936: f7ff ff47 bl 80017c8 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
800193a: bf00 nop
|
|
800193c: 3708 adds r7, #8
|
|
800193e: 46bd mov sp, r7
|
|
8001940: bd80 pop {r7, pc}
|
|
|
|
08001942 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001942: b580 push {r7, lr}
|
|
8001944: b086 sub sp, #24
|
|
8001946: af00 add r7, sp, #0
|
|
8001948: 4603 mov r3, r0
|
|
800194a: 60b9 str r1, [r7, #8]
|
|
800194c: 607a str r2, [r7, #4]
|
|
800194e: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8001950: 2300 movs r3, #0
|
|
8001952: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8001954: f7ff ff5c bl 8001810 <__NVIC_GetPriorityGrouping>
|
|
8001958: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
800195a: 687a ldr r2, [r7, #4]
|
|
800195c: 68b9 ldr r1, [r7, #8]
|
|
800195e: 6978 ldr r0, [r7, #20]
|
|
8001960: f7ff ff8e bl 8001880 <NVIC_EncodePriority>
|
|
8001964: 4602 mov r2, r0
|
|
8001966: f997 300f ldrsb.w r3, [r7, #15]
|
|
800196a: 4611 mov r1, r2
|
|
800196c: 4618 mov r0, r3
|
|
800196e: f7ff ff5d bl 800182c <__NVIC_SetPriority>
|
|
}
|
|
8001972: bf00 nop
|
|
8001974: 3718 adds r7, #24
|
|
8001976: 46bd mov sp, r7
|
|
8001978: bd80 pop {r7, pc}
|
|
|
|
0800197a <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
800197a: b580 push {r7, lr}
|
|
800197c: b082 sub sp, #8
|
|
800197e: af00 add r7, sp, #0
|
|
8001980: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8001982: 6878 ldr r0, [r7, #4]
|
|
8001984: f7ff ffb0 bl 80018e8 <SysTick_Config>
|
|
8001988: 4603 mov r3, r0
|
|
}
|
|
800198a: 4618 mov r0, r3
|
|
800198c: 3708 adds r7, #8
|
|
800198e: 46bd mov sp, r7
|
|
8001990: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001994 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8001994: b480 push {r7}
|
|
8001996: b087 sub sp, #28
|
|
8001998: af00 add r7, sp, #0
|
|
800199a: 6078 str r0, [r7, #4]
|
|
800199c: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
800199e: 2300 movs r3, #0
|
|
80019a0: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80019a2: e17f b.n 8001ca4 <HAL_GPIO_Init+0x310>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
80019a4: 683b ldr r3, [r7, #0]
|
|
80019a6: 681a ldr r2, [r3, #0]
|
|
80019a8: 2101 movs r1, #1
|
|
80019aa: 697b ldr r3, [r7, #20]
|
|
80019ac: fa01 f303 lsl.w r3, r1, r3
|
|
80019b0: 4013 ands r3, r2
|
|
80019b2: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
80019b4: 68fb ldr r3, [r7, #12]
|
|
80019b6: 2b00 cmp r3, #0
|
|
80019b8: f000 8171 beq.w 8001c9e <HAL_GPIO_Init+0x30a>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
80019bc: 683b ldr r3, [r7, #0]
|
|
80019be: 685b ldr r3, [r3, #4]
|
|
80019c0: f003 0303 and.w r3, r3, #3
|
|
80019c4: 2b01 cmp r3, #1
|
|
80019c6: d005 beq.n 80019d4 <HAL_GPIO_Init+0x40>
|
|
80019c8: 683b ldr r3, [r7, #0]
|
|
80019ca: 685b ldr r3, [r3, #4]
|
|
80019cc: f003 0303 and.w r3, r3, #3
|
|
80019d0: 2b02 cmp r3, #2
|
|
80019d2: d130 bne.n 8001a36 <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
80019d4: 687b ldr r3, [r7, #4]
|
|
80019d6: 689b ldr r3, [r3, #8]
|
|
80019d8: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
80019da: 697b ldr r3, [r7, #20]
|
|
80019dc: 005b lsls r3, r3, #1
|
|
80019de: 2203 movs r2, #3
|
|
80019e0: fa02 f303 lsl.w r3, r2, r3
|
|
80019e4: 43db mvns r3, r3
|
|
80019e6: 693a ldr r2, [r7, #16]
|
|
80019e8: 4013 ands r3, r2
|
|
80019ea: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
80019ec: 683b ldr r3, [r7, #0]
|
|
80019ee: 68da ldr r2, [r3, #12]
|
|
80019f0: 697b ldr r3, [r7, #20]
|
|
80019f2: 005b lsls r3, r3, #1
|
|
80019f4: fa02 f303 lsl.w r3, r2, r3
|
|
80019f8: 693a ldr r2, [r7, #16]
|
|
80019fa: 4313 orrs r3, r2
|
|
80019fc: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
80019fe: 687b ldr r3, [r7, #4]
|
|
8001a00: 693a ldr r2, [r7, #16]
|
|
8001a02: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8001a04: 687b ldr r3, [r7, #4]
|
|
8001a06: 685b ldr r3, [r3, #4]
|
|
8001a08: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8001a0a: 2201 movs r2, #1
|
|
8001a0c: 697b ldr r3, [r7, #20]
|
|
8001a0e: fa02 f303 lsl.w r3, r2, r3
|
|
8001a12: 43db mvns r3, r3
|
|
8001a14: 693a ldr r2, [r7, #16]
|
|
8001a16: 4013 ands r3, r2
|
|
8001a18: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8001a1a: 683b ldr r3, [r7, #0]
|
|
8001a1c: 685b ldr r3, [r3, #4]
|
|
8001a1e: 091b lsrs r3, r3, #4
|
|
8001a20: f003 0201 and.w r2, r3, #1
|
|
8001a24: 697b ldr r3, [r7, #20]
|
|
8001a26: fa02 f303 lsl.w r3, r2, r3
|
|
8001a2a: 693a ldr r2, [r7, #16]
|
|
8001a2c: 4313 orrs r3, r2
|
|
8001a2e: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8001a30: 687b ldr r3, [r7, #4]
|
|
8001a32: 693a ldr r2, [r7, #16]
|
|
8001a34: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
|
/* In case of Analog mode, check if ADC control mode is selected */
|
|
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
|
|
8001a36: 683b ldr r3, [r7, #0]
|
|
8001a38: 685b ldr r3, [r3, #4]
|
|
8001a3a: f003 0303 and.w r3, r3, #3
|
|
8001a3e: 2b03 cmp r3, #3
|
|
8001a40: d118 bne.n 8001a74 <HAL_GPIO_Init+0xe0>
|
|
{
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->ASCR;
|
|
8001a42: 687b ldr r3, [r7, #4]
|
|
8001a44: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8001a46: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_ASCR_ASC0 << position) ;
|
|
8001a48: 2201 movs r2, #1
|
|
8001a4a: 697b ldr r3, [r7, #20]
|
|
8001a4c: fa02 f303 lsl.w r3, r2, r3
|
|
8001a50: 43db mvns r3, r3
|
|
8001a52: 693a ldr r2, [r7, #16]
|
|
8001a54: 4013 ands r3, r2
|
|
8001a56: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
|
|
8001a58: 683b ldr r3, [r7, #0]
|
|
8001a5a: 685b ldr r3, [r3, #4]
|
|
8001a5c: 08db lsrs r3, r3, #3
|
|
8001a5e: f003 0201 and.w r2, r3, #1
|
|
8001a62: 697b ldr r3, [r7, #20]
|
|
8001a64: fa02 f303 lsl.w r3, r2, r3
|
|
8001a68: 693a ldr r2, [r7, #16]
|
|
8001a6a: 4313 orrs r3, r2
|
|
8001a6c: 613b str r3, [r7, #16]
|
|
GPIOx->ASCR = temp;
|
|
8001a6e: 687b ldr r3, [r7, #4]
|
|
8001a70: 693a ldr r2, [r7, #16]
|
|
8001a72: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
8001a74: 683b ldr r3, [r7, #0]
|
|
8001a76: 685b ldr r3, [r3, #4]
|
|
8001a78: f003 0303 and.w r3, r3, #3
|
|
8001a7c: 2b03 cmp r3, #3
|
|
8001a7e: d017 beq.n 8001ab0 <HAL_GPIO_Init+0x11c>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
temp = GPIOx->PUPDR;
|
|
8001a80: 687b ldr r3, [r7, #4]
|
|
8001a82: 68db ldr r3, [r3, #12]
|
|
8001a84: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
8001a86: 697b ldr r3, [r7, #20]
|
|
8001a88: 005b lsls r3, r3, #1
|
|
8001a8a: 2203 movs r2, #3
|
|
8001a8c: fa02 f303 lsl.w r3, r2, r3
|
|
8001a90: 43db mvns r3, r3
|
|
8001a92: 693a ldr r2, [r7, #16]
|
|
8001a94: 4013 ands r3, r2
|
|
8001a96: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8001a98: 683b ldr r3, [r7, #0]
|
|
8001a9a: 689a ldr r2, [r3, #8]
|
|
8001a9c: 697b ldr r3, [r7, #20]
|
|
8001a9e: 005b lsls r3, r3, #1
|
|
8001aa0: fa02 f303 lsl.w r3, r2, r3
|
|
8001aa4: 693a ldr r2, [r7, #16]
|
|
8001aa6: 4313 orrs r3, r2
|
|
8001aa8: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8001aaa: 687b ldr r3, [r7, #4]
|
|
8001aac: 693a ldr r2, [r7, #16]
|
|
8001aae: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8001ab0: 683b ldr r3, [r7, #0]
|
|
8001ab2: 685b ldr r3, [r3, #4]
|
|
8001ab4: f003 0303 and.w r3, r3, #3
|
|
8001ab8: 2b02 cmp r3, #2
|
|
8001aba: d123 bne.n 8001b04 <HAL_GPIO_Init+0x170>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
8001abc: 697b ldr r3, [r7, #20]
|
|
8001abe: 08da lsrs r2, r3, #3
|
|
8001ac0: 687b ldr r3, [r7, #4]
|
|
8001ac2: 3208 adds r2, #8
|
|
8001ac4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8001ac8: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8001aca: 697b ldr r3, [r7, #20]
|
|
8001acc: f003 0307 and.w r3, r3, #7
|
|
8001ad0: 009b lsls r3, r3, #2
|
|
8001ad2: 220f movs r2, #15
|
|
8001ad4: fa02 f303 lsl.w r3, r2, r3
|
|
8001ad8: 43db mvns r3, r3
|
|
8001ada: 693a ldr r2, [r7, #16]
|
|
8001adc: 4013 ands r3, r2
|
|
8001ade: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
8001ae0: 683b ldr r3, [r7, #0]
|
|
8001ae2: 691a ldr r2, [r3, #16]
|
|
8001ae4: 697b ldr r3, [r7, #20]
|
|
8001ae6: f003 0307 and.w r3, r3, #7
|
|
8001aea: 009b lsls r3, r3, #2
|
|
8001aec: fa02 f303 lsl.w r3, r2, r3
|
|
8001af0: 693a ldr r2, [r7, #16]
|
|
8001af2: 4313 orrs r3, r2
|
|
8001af4: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
8001af6: 697b ldr r3, [r7, #20]
|
|
8001af8: 08da lsrs r2, r3, #3
|
|
8001afa: 687b ldr r3, [r7, #4]
|
|
8001afc: 3208 adds r2, #8
|
|
8001afe: 6939 ldr r1, [r7, #16]
|
|
8001b00: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8001b04: 687b ldr r3, [r7, #4]
|
|
8001b06: 681b ldr r3, [r3, #0]
|
|
8001b08: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
8001b0a: 697b ldr r3, [r7, #20]
|
|
8001b0c: 005b lsls r3, r3, #1
|
|
8001b0e: 2203 movs r2, #3
|
|
8001b10: fa02 f303 lsl.w r3, r2, r3
|
|
8001b14: 43db mvns r3, r3
|
|
8001b16: 693a ldr r2, [r7, #16]
|
|
8001b18: 4013 ands r3, r2
|
|
8001b1a: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
8001b1c: 683b ldr r3, [r7, #0]
|
|
8001b1e: 685b ldr r3, [r3, #4]
|
|
8001b20: f003 0203 and.w r2, r3, #3
|
|
8001b24: 697b ldr r3, [r7, #20]
|
|
8001b26: 005b lsls r3, r3, #1
|
|
8001b28: fa02 f303 lsl.w r3, r2, r3
|
|
8001b2c: 693a ldr r2, [r7, #16]
|
|
8001b2e: 4313 orrs r3, r2
|
|
8001b30: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
8001b32: 687b ldr r3, [r7, #4]
|
|
8001b34: 693a ldr r2, [r7, #16]
|
|
8001b36: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
8001b38: 683b ldr r3, [r7, #0]
|
|
8001b3a: 685b ldr r3, [r3, #4]
|
|
8001b3c: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8001b40: 2b00 cmp r3, #0
|
|
8001b42: f000 80ac beq.w 8001c9e <HAL_GPIO_Init+0x30a>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8001b46: 4b5f ldr r3, [pc, #380] @ (8001cc4 <HAL_GPIO_Init+0x330>)
|
|
8001b48: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001b4a: 4a5e ldr r2, [pc, #376] @ (8001cc4 <HAL_GPIO_Init+0x330>)
|
|
8001b4c: f043 0301 orr.w r3, r3, #1
|
|
8001b50: 6613 str r3, [r2, #96] @ 0x60
|
|
8001b52: 4b5c ldr r3, [pc, #368] @ (8001cc4 <HAL_GPIO_Init+0x330>)
|
|
8001b54: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001b56: f003 0301 and.w r3, r3, #1
|
|
8001b5a: 60bb str r3, [r7, #8]
|
|
8001b5c: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
8001b5e: 4a5a ldr r2, [pc, #360] @ (8001cc8 <HAL_GPIO_Init+0x334>)
|
|
8001b60: 697b ldr r3, [r7, #20]
|
|
8001b62: 089b lsrs r3, r3, #2
|
|
8001b64: 3302 adds r3, #2
|
|
8001b66: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001b6a: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
8001b6c: 697b ldr r3, [r7, #20]
|
|
8001b6e: f003 0303 and.w r3, r3, #3
|
|
8001b72: 009b lsls r3, r3, #2
|
|
8001b74: 220f movs r2, #15
|
|
8001b76: fa02 f303 lsl.w r3, r2, r3
|
|
8001b7a: 43db mvns r3, r3
|
|
8001b7c: 693a ldr r2, [r7, #16]
|
|
8001b7e: 4013 ands r3, r2
|
|
8001b80: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
8001b82: 687b ldr r3, [r7, #4]
|
|
8001b84: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
8001b88: d025 beq.n 8001bd6 <HAL_GPIO_Init+0x242>
|
|
8001b8a: 687b ldr r3, [r7, #4]
|
|
8001b8c: 4a4f ldr r2, [pc, #316] @ (8001ccc <HAL_GPIO_Init+0x338>)
|
|
8001b8e: 4293 cmp r3, r2
|
|
8001b90: d01f beq.n 8001bd2 <HAL_GPIO_Init+0x23e>
|
|
8001b92: 687b ldr r3, [r7, #4]
|
|
8001b94: 4a4e ldr r2, [pc, #312] @ (8001cd0 <HAL_GPIO_Init+0x33c>)
|
|
8001b96: 4293 cmp r3, r2
|
|
8001b98: d019 beq.n 8001bce <HAL_GPIO_Init+0x23a>
|
|
8001b9a: 687b ldr r3, [r7, #4]
|
|
8001b9c: 4a4d ldr r2, [pc, #308] @ (8001cd4 <HAL_GPIO_Init+0x340>)
|
|
8001b9e: 4293 cmp r3, r2
|
|
8001ba0: d013 beq.n 8001bca <HAL_GPIO_Init+0x236>
|
|
8001ba2: 687b ldr r3, [r7, #4]
|
|
8001ba4: 4a4c ldr r2, [pc, #304] @ (8001cd8 <HAL_GPIO_Init+0x344>)
|
|
8001ba6: 4293 cmp r3, r2
|
|
8001ba8: d00d beq.n 8001bc6 <HAL_GPIO_Init+0x232>
|
|
8001baa: 687b ldr r3, [r7, #4]
|
|
8001bac: 4a4b ldr r2, [pc, #300] @ (8001cdc <HAL_GPIO_Init+0x348>)
|
|
8001bae: 4293 cmp r3, r2
|
|
8001bb0: d007 beq.n 8001bc2 <HAL_GPIO_Init+0x22e>
|
|
8001bb2: 687b ldr r3, [r7, #4]
|
|
8001bb4: 4a4a ldr r2, [pc, #296] @ (8001ce0 <HAL_GPIO_Init+0x34c>)
|
|
8001bb6: 4293 cmp r3, r2
|
|
8001bb8: d101 bne.n 8001bbe <HAL_GPIO_Init+0x22a>
|
|
8001bba: 2306 movs r3, #6
|
|
8001bbc: e00c b.n 8001bd8 <HAL_GPIO_Init+0x244>
|
|
8001bbe: 2307 movs r3, #7
|
|
8001bc0: e00a b.n 8001bd8 <HAL_GPIO_Init+0x244>
|
|
8001bc2: 2305 movs r3, #5
|
|
8001bc4: e008 b.n 8001bd8 <HAL_GPIO_Init+0x244>
|
|
8001bc6: 2304 movs r3, #4
|
|
8001bc8: e006 b.n 8001bd8 <HAL_GPIO_Init+0x244>
|
|
8001bca: 2303 movs r3, #3
|
|
8001bcc: e004 b.n 8001bd8 <HAL_GPIO_Init+0x244>
|
|
8001bce: 2302 movs r3, #2
|
|
8001bd0: e002 b.n 8001bd8 <HAL_GPIO_Init+0x244>
|
|
8001bd2: 2301 movs r3, #1
|
|
8001bd4: e000 b.n 8001bd8 <HAL_GPIO_Init+0x244>
|
|
8001bd6: 2300 movs r3, #0
|
|
8001bd8: 697a ldr r2, [r7, #20]
|
|
8001bda: f002 0203 and.w r2, r2, #3
|
|
8001bde: 0092 lsls r2, r2, #2
|
|
8001be0: 4093 lsls r3, r2
|
|
8001be2: 693a ldr r2, [r7, #16]
|
|
8001be4: 4313 orrs r3, r2
|
|
8001be6: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
8001be8: 4937 ldr r1, [pc, #220] @ (8001cc8 <HAL_GPIO_Init+0x334>)
|
|
8001bea: 697b ldr r3, [r7, #20]
|
|
8001bec: 089b lsrs r3, r3, #2
|
|
8001bee: 3302 adds r3, #2
|
|
8001bf0: 693a ldr r2, [r7, #16]
|
|
8001bf2: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
8001bf6: 4b3b ldr r3, [pc, #236] @ (8001ce4 <HAL_GPIO_Init+0x350>)
|
|
8001bf8: 689b ldr r3, [r3, #8]
|
|
8001bfa: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8001bfc: 68fb ldr r3, [r7, #12]
|
|
8001bfe: 43db mvns r3, r3
|
|
8001c00: 693a ldr r2, [r7, #16]
|
|
8001c02: 4013 ands r3, r2
|
|
8001c04: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
8001c06: 683b ldr r3, [r7, #0]
|
|
8001c08: 685b ldr r3, [r3, #4]
|
|
8001c0a: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001c0e: 2b00 cmp r3, #0
|
|
8001c10: d003 beq.n 8001c1a <HAL_GPIO_Init+0x286>
|
|
{
|
|
temp |= iocurrent;
|
|
8001c12: 693a ldr r2, [r7, #16]
|
|
8001c14: 68fb ldr r3, [r7, #12]
|
|
8001c16: 4313 orrs r3, r2
|
|
8001c18: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
8001c1a: 4a32 ldr r2, [pc, #200] @ (8001ce4 <HAL_GPIO_Init+0x350>)
|
|
8001c1c: 693b ldr r3, [r7, #16]
|
|
8001c1e: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR1;
|
|
8001c20: 4b30 ldr r3, [pc, #192] @ (8001ce4 <HAL_GPIO_Init+0x350>)
|
|
8001c22: 68db ldr r3, [r3, #12]
|
|
8001c24: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8001c26: 68fb ldr r3, [r7, #12]
|
|
8001c28: 43db mvns r3, r3
|
|
8001c2a: 693a ldr r2, [r7, #16]
|
|
8001c2c: 4013 ands r3, r2
|
|
8001c2e: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
8001c30: 683b ldr r3, [r7, #0]
|
|
8001c32: 685b ldr r3, [r3, #4]
|
|
8001c34: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8001c38: 2b00 cmp r3, #0
|
|
8001c3a: d003 beq.n 8001c44 <HAL_GPIO_Init+0x2b0>
|
|
{
|
|
temp |= iocurrent;
|
|
8001c3c: 693a ldr r2, [r7, #16]
|
|
8001c3e: 68fb ldr r3, [r7, #12]
|
|
8001c40: 4313 orrs r3, r2
|
|
8001c42: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
8001c44: 4a27 ldr r2, [pc, #156] @ (8001ce4 <HAL_GPIO_Init+0x350>)
|
|
8001c46: 693b ldr r3, [r7, #16]
|
|
8001c48: 60d3 str r3, [r2, #12]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->EMR1;
|
|
8001c4a: 4b26 ldr r3, [pc, #152] @ (8001ce4 <HAL_GPIO_Init+0x350>)
|
|
8001c4c: 685b ldr r3, [r3, #4]
|
|
8001c4e: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8001c50: 68fb ldr r3, [r7, #12]
|
|
8001c52: 43db mvns r3, r3
|
|
8001c54: 693a ldr r2, [r7, #16]
|
|
8001c56: 4013 ands r3, r2
|
|
8001c58: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
8001c5a: 683b ldr r3, [r7, #0]
|
|
8001c5c: 685b ldr r3, [r3, #4]
|
|
8001c5e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001c62: 2b00 cmp r3, #0
|
|
8001c64: d003 beq.n 8001c6e <HAL_GPIO_Init+0x2da>
|
|
{
|
|
temp |= iocurrent;
|
|
8001c66: 693a ldr r2, [r7, #16]
|
|
8001c68: 68fb ldr r3, [r7, #12]
|
|
8001c6a: 4313 orrs r3, r2
|
|
8001c6c: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
8001c6e: 4a1d ldr r2, [pc, #116] @ (8001ce4 <HAL_GPIO_Init+0x350>)
|
|
8001c70: 693b ldr r3, [r7, #16]
|
|
8001c72: 6053 str r3, [r2, #4]
|
|
|
|
temp = EXTI->IMR1;
|
|
8001c74: 4b1b ldr r3, [pc, #108] @ (8001ce4 <HAL_GPIO_Init+0x350>)
|
|
8001c76: 681b ldr r3, [r3, #0]
|
|
8001c78: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8001c7a: 68fb ldr r3, [r7, #12]
|
|
8001c7c: 43db mvns r3, r3
|
|
8001c7e: 693a ldr r2, [r7, #16]
|
|
8001c80: 4013 ands r3, r2
|
|
8001c82: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
8001c84: 683b ldr r3, [r7, #0]
|
|
8001c86: 685b ldr r3, [r3, #4]
|
|
8001c88: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001c8c: 2b00 cmp r3, #0
|
|
8001c8e: d003 beq.n 8001c98 <HAL_GPIO_Init+0x304>
|
|
{
|
|
temp |= iocurrent;
|
|
8001c90: 693a ldr r2, [r7, #16]
|
|
8001c92: 68fb ldr r3, [r7, #12]
|
|
8001c94: 4313 orrs r3, r2
|
|
8001c96: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
8001c98: 4a12 ldr r2, [pc, #72] @ (8001ce4 <HAL_GPIO_Init+0x350>)
|
|
8001c9a: 693b ldr r3, [r7, #16]
|
|
8001c9c: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8001c9e: 697b ldr r3, [r7, #20]
|
|
8001ca0: 3301 adds r3, #1
|
|
8001ca2: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8001ca4: 683b ldr r3, [r7, #0]
|
|
8001ca6: 681a ldr r2, [r3, #0]
|
|
8001ca8: 697b ldr r3, [r7, #20]
|
|
8001caa: fa22 f303 lsr.w r3, r2, r3
|
|
8001cae: 2b00 cmp r3, #0
|
|
8001cb0: f47f ae78 bne.w 80019a4 <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8001cb4: bf00 nop
|
|
8001cb6: bf00 nop
|
|
8001cb8: 371c adds r7, #28
|
|
8001cba: 46bd mov sp, r7
|
|
8001cbc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001cc0: 4770 bx lr
|
|
8001cc2: bf00 nop
|
|
8001cc4: 40021000 .word 0x40021000
|
|
8001cc8: 40010000 .word 0x40010000
|
|
8001ccc: 48000400 .word 0x48000400
|
|
8001cd0: 48000800 .word 0x48000800
|
|
8001cd4: 48000c00 .word 0x48000c00
|
|
8001cd8: 48001000 .word 0x48001000
|
|
8001cdc: 48001400 .word 0x48001400
|
|
8001ce0: 48001800 .word 0x48001800
|
|
8001ce4: 40010400 .word 0x40010400
|
|
|
|
08001ce8 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8001ce8: b480 push {r7}
|
|
8001cea: b083 sub sp, #12
|
|
8001cec: af00 add r7, sp, #0
|
|
8001cee: 6078 str r0, [r7, #4]
|
|
8001cf0: 460b mov r3, r1
|
|
8001cf2: 807b strh r3, [r7, #2]
|
|
8001cf4: 4613 mov r3, r2
|
|
8001cf6: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8001cf8: 787b ldrb r3, [r7, #1]
|
|
8001cfa: 2b00 cmp r3, #0
|
|
8001cfc: d003 beq.n 8001d06 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8001cfe: 887a ldrh r2, [r7, #2]
|
|
8001d00: 687b ldr r3, [r7, #4]
|
|
8001d02: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8001d04: e002 b.n 8001d0c <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8001d06: 887a ldrh r2, [r7, #2]
|
|
8001d08: 687b ldr r3, [r7, #4]
|
|
8001d0a: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
8001d0c: bf00 nop
|
|
8001d0e: 370c adds r7, #12
|
|
8001d10: 46bd mov sp, r7
|
|
8001d12: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001d16: 4770 bx lr
|
|
|
|
08001d18 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8001d18: b580 push {r7, lr}
|
|
8001d1a: b082 sub sp, #8
|
|
8001d1c: af00 add r7, sp, #0
|
|
8001d1e: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8001d20: 687b ldr r3, [r7, #4]
|
|
8001d22: 2b00 cmp r3, #0
|
|
8001d24: d101 bne.n 8001d2a <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001d26: 2301 movs r3, #1
|
|
8001d28: e08d b.n 8001e46 <HAL_I2C_Init+0x12e>
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8001d2a: 687b ldr r3, [r7, #4]
|
|
8001d2c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8001d30: b2db uxtb r3, r3
|
|
8001d32: 2b00 cmp r3, #0
|
|
8001d34: d106 bne.n 8001d44 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8001d36: 687b ldr r3, [r7, #4]
|
|
8001d38: 2200 movs r2, #0
|
|
8001d3a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8001d3e: 6878 ldr r0, [r7, #4]
|
|
8001d40: f7ff fae0 bl 8001304 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8001d44: 687b ldr r3, [r7, #4]
|
|
8001d46: 2224 movs r2, #36 @ 0x24
|
|
8001d48: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8001d4c: 687b ldr r3, [r7, #4]
|
|
8001d4e: 681b ldr r3, [r3, #0]
|
|
8001d50: 681a ldr r2, [r3, #0]
|
|
8001d52: 687b ldr r3, [r7, #4]
|
|
8001d54: 681b ldr r3, [r3, #0]
|
|
8001d56: f022 0201 bic.w r2, r2, #1
|
|
8001d5a: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
|
|
8001d5c: 687b ldr r3, [r7, #4]
|
|
8001d5e: 685a ldr r2, [r3, #4]
|
|
8001d60: 687b ldr r3, [r7, #4]
|
|
8001d62: 681b ldr r3, [r3, #0]
|
|
8001d64: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
|
|
8001d68: 611a str r2, [r3, #16]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Disable Own Address1 before set the Own Address1 configuration */
|
|
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
|
|
8001d6a: 687b ldr r3, [r7, #4]
|
|
8001d6c: 681b ldr r3, [r3, #0]
|
|
8001d6e: 689a ldr r2, [r3, #8]
|
|
8001d70: 687b ldr r3, [r7, #4]
|
|
8001d72: 681b ldr r3, [r3, #0]
|
|
8001d74: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8001d78: 609a str r2, [r3, #8]
|
|
|
|
/* Configure I2Cx: Own Address1 and ack own address1 mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
8001d7a: 687b ldr r3, [r7, #4]
|
|
8001d7c: 68db ldr r3, [r3, #12]
|
|
8001d7e: 2b01 cmp r3, #1
|
|
8001d80: d107 bne.n 8001d92 <HAL_I2C_Init+0x7a>
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
|
|
8001d82: 687b ldr r3, [r7, #4]
|
|
8001d84: 689a ldr r2, [r3, #8]
|
|
8001d86: 687b ldr r3, [r7, #4]
|
|
8001d88: 681b ldr r3, [r3, #0]
|
|
8001d8a: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8001d8e: 609a str r2, [r3, #8]
|
|
8001d90: e006 b.n 8001da0 <HAL_I2C_Init+0x88>
|
|
}
|
|
else /* I2C_ADDRESSINGMODE_10BIT */
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
|
|
8001d92: 687b ldr r3, [r7, #4]
|
|
8001d94: 689a ldr r2, [r3, #8]
|
|
8001d96: 687b ldr r3, [r7, #4]
|
|
8001d98: 681b ldr r3, [r3, #0]
|
|
8001d9a: f442 4204 orr.w r2, r2, #33792 @ 0x8400
|
|
8001d9e: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Addressing Master mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
8001da0: 687b ldr r3, [r7, #4]
|
|
8001da2: 68db ldr r3, [r3, #12]
|
|
8001da4: 2b02 cmp r3, #2
|
|
8001da6: d108 bne.n 8001dba <HAL_I2C_Init+0xa2>
|
|
{
|
|
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
8001da8: 687b ldr r3, [r7, #4]
|
|
8001daa: 681b ldr r3, [r3, #0]
|
|
8001dac: 685a ldr r2, [r3, #4]
|
|
8001dae: 687b ldr r3, [r7, #4]
|
|
8001db0: 681b ldr r3, [r3, #0]
|
|
8001db2: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8001db6: 605a str r2, [r3, #4]
|
|
8001db8: e007 b.n 8001dca <HAL_I2C_Init+0xb2>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the I2C ADD10 bit */
|
|
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
8001dba: 687b ldr r3, [r7, #4]
|
|
8001dbc: 681b ldr r3, [r3, #0]
|
|
8001dbe: 685a ldr r2, [r3, #4]
|
|
8001dc0: 687b ldr r3, [r7, #4]
|
|
8001dc2: 681b ldr r3, [r3, #0]
|
|
8001dc4: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8001dc8: 605a str r2, [r3, #4]
|
|
}
|
|
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
|
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
|
8001dca: 687b ldr r3, [r7, #4]
|
|
8001dcc: 681b ldr r3, [r3, #0]
|
|
8001dce: 685b ldr r3, [r3, #4]
|
|
8001dd0: 687a ldr r2, [r7, #4]
|
|
8001dd2: 6812 ldr r2, [r2, #0]
|
|
8001dd4: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
8001dd8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8001ddc: 6053 str r3, [r2, #4]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Disable Own Address2 before set the Own Address2 configuration */
|
|
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
|
|
8001dde: 687b ldr r3, [r7, #4]
|
|
8001de0: 681b ldr r3, [r3, #0]
|
|
8001de2: 68da ldr r2, [r3, #12]
|
|
8001de4: 687b ldr r3, [r7, #4]
|
|
8001de6: 681b ldr r3, [r3, #0]
|
|
8001de8: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8001dec: 60da str r2, [r3, #12]
|
|
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8001dee: 687b ldr r3, [r7, #4]
|
|
8001df0: 691a ldr r2, [r3, #16]
|
|
8001df2: 687b ldr r3, [r7, #4]
|
|
8001df4: 695b ldr r3, [r3, #20]
|
|
8001df6: ea42 0103 orr.w r1, r2, r3
|
|
(hi2c->Init.OwnAddress2Masks << 8));
|
|
8001dfa: 687b ldr r3, [r7, #4]
|
|
8001dfc: 699b ldr r3, [r3, #24]
|
|
8001dfe: 021a lsls r2, r3, #8
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8001e00: 687b ldr r3, [r7, #4]
|
|
8001e02: 681b ldr r3, [r3, #0]
|
|
8001e04: 430a orrs r2, r1
|
|
8001e06: 60da str r2, [r3, #12]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
|
|
8001e08: 687b ldr r3, [r7, #4]
|
|
8001e0a: 69d9 ldr r1, [r3, #28]
|
|
8001e0c: 687b ldr r3, [r7, #4]
|
|
8001e0e: 6a1a ldr r2, [r3, #32]
|
|
8001e10: 687b ldr r3, [r7, #4]
|
|
8001e12: 681b ldr r3, [r3, #0]
|
|
8001e14: 430a orrs r2, r1
|
|
8001e16: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8001e18: 687b ldr r3, [r7, #4]
|
|
8001e1a: 681b ldr r3, [r3, #0]
|
|
8001e1c: 681a ldr r2, [r3, #0]
|
|
8001e1e: 687b ldr r3, [r7, #4]
|
|
8001e20: 681b ldr r3, [r3, #0]
|
|
8001e22: f042 0201 orr.w r2, r2, #1
|
|
8001e26: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8001e28: 687b ldr r3, [r7, #4]
|
|
8001e2a: 2200 movs r2, #0
|
|
8001e2c: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8001e2e: 687b ldr r3, [r7, #4]
|
|
8001e30: 2220 movs r2, #32
|
|
8001e32: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8001e36: 687b ldr r3, [r7, #4]
|
|
8001e38: 2200 movs r2, #0
|
|
8001e3a: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8001e3c: 687b ldr r3, [r7, #4]
|
|
8001e3e: 2200 movs r2, #0
|
|
8001e40: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_OK;
|
|
8001e44: 2300 movs r3, #0
|
|
}
|
|
8001e46: 4618 mov r0, r3
|
|
8001e48: 3708 adds r7, #8
|
|
8001e4a: 46bd mov sp, r7
|
|
8001e4c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001e50 <HAL_I2C_Mem_Write>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8001e50: b580 push {r7, lr}
|
|
8001e52: b088 sub sp, #32
|
|
8001e54: af02 add r7, sp, #8
|
|
8001e56: 60f8 str r0, [r7, #12]
|
|
8001e58: 4608 mov r0, r1
|
|
8001e5a: 4611 mov r1, r2
|
|
8001e5c: 461a mov r2, r3
|
|
8001e5e: 4603 mov r3, r0
|
|
8001e60: 817b strh r3, [r7, #10]
|
|
8001e62: 460b mov r3, r1
|
|
8001e64: 813b strh r3, [r7, #8]
|
|
8001e66: 4613 mov r3, r2
|
|
8001e68: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8001e6a: 68fb ldr r3, [r7, #12]
|
|
8001e6c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8001e70: b2db uxtb r3, r3
|
|
8001e72: 2b20 cmp r3, #32
|
|
8001e74: f040 80f9 bne.w 800206a <HAL_I2C_Mem_Write+0x21a>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8001e78: 6a3b ldr r3, [r7, #32]
|
|
8001e7a: 2b00 cmp r3, #0
|
|
8001e7c: d002 beq.n 8001e84 <HAL_I2C_Mem_Write+0x34>
|
|
8001e7e: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
8001e80: 2b00 cmp r3, #0
|
|
8001e82: d105 bne.n 8001e90 <HAL_I2C_Mem_Write+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8001e84: 68fb ldr r3, [r7, #12]
|
|
8001e86: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8001e8a: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
8001e8c: 2301 movs r3, #1
|
|
8001e8e: e0ed b.n 800206c <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8001e90: 68fb ldr r3, [r7, #12]
|
|
8001e92: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8001e96: 2b01 cmp r3, #1
|
|
8001e98: d101 bne.n 8001e9e <HAL_I2C_Mem_Write+0x4e>
|
|
8001e9a: 2302 movs r3, #2
|
|
8001e9c: e0e6 b.n 800206c <HAL_I2C_Mem_Write+0x21c>
|
|
8001e9e: 68fb ldr r3, [r7, #12]
|
|
8001ea0: 2201 movs r2, #1
|
|
8001ea2: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8001ea6: f7ff fc83 bl 80017b0 <HAL_GetTick>
|
|
8001eaa: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8001eac: 697b ldr r3, [r7, #20]
|
|
8001eae: 9300 str r3, [sp, #0]
|
|
8001eb0: 2319 movs r3, #25
|
|
8001eb2: 2201 movs r2, #1
|
|
8001eb4: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
8001eb8: 68f8 ldr r0, [r7, #12]
|
|
8001eba: f000 fac3 bl 8002444 <I2C_WaitOnFlagUntilTimeout>
|
|
8001ebe: 4603 mov r3, r0
|
|
8001ec0: 2b00 cmp r3, #0
|
|
8001ec2: d001 beq.n 8001ec8 <HAL_I2C_Mem_Write+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8001ec4: 2301 movs r3, #1
|
|
8001ec6: e0d1 b.n 800206c <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
8001ec8: 68fb ldr r3, [r7, #12]
|
|
8001eca: 2221 movs r2, #33 @ 0x21
|
|
8001ecc: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8001ed0: 68fb ldr r3, [r7, #12]
|
|
8001ed2: 2240 movs r2, #64 @ 0x40
|
|
8001ed4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8001ed8: 68fb ldr r3, [r7, #12]
|
|
8001eda: 2200 movs r2, #0
|
|
8001edc: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8001ede: 68fb ldr r3, [r7, #12]
|
|
8001ee0: 6a3a ldr r2, [r7, #32]
|
|
8001ee2: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8001ee4: 68fb ldr r3, [r7, #12]
|
|
8001ee6: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
8001ee8: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8001eea: 68fb ldr r3, [r7, #12]
|
|
8001eec: 2200 movs r2, #0
|
|
8001eee: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8001ef0: 88f8 ldrh r0, [r7, #6]
|
|
8001ef2: 893a ldrh r2, [r7, #8]
|
|
8001ef4: 8979 ldrh r1, [r7, #10]
|
|
8001ef6: 697b ldr r3, [r7, #20]
|
|
8001ef8: 9301 str r3, [sp, #4]
|
|
8001efa: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001efc: 9300 str r3, [sp, #0]
|
|
8001efe: 4603 mov r3, r0
|
|
8001f00: 68f8 ldr r0, [r7, #12]
|
|
8001f02: f000 f9d3 bl 80022ac <I2C_RequestMemoryWrite>
|
|
8001f06: 4603 mov r3, r0
|
|
8001f08: 2b00 cmp r3, #0
|
|
8001f0a: d005 beq.n 8001f18 <HAL_I2C_Mem_Write+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8001f0c: 68fb ldr r3, [r7, #12]
|
|
8001f0e: 2200 movs r2, #0
|
|
8001f10: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8001f14: 2301 movs r3, #1
|
|
8001f16: e0a9 b.n 800206c <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8001f18: 68fb ldr r3, [r7, #12]
|
|
8001f1a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8001f1c: b29b uxth r3, r3
|
|
8001f1e: 2bff cmp r3, #255 @ 0xff
|
|
8001f20: d90e bls.n 8001f40 <HAL_I2C_Mem_Write+0xf0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8001f22: 68fb ldr r3, [r7, #12]
|
|
8001f24: 22ff movs r2, #255 @ 0xff
|
|
8001f26: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
8001f28: 68fb ldr r3, [r7, #12]
|
|
8001f2a: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8001f2c: b2da uxtb r2, r3
|
|
8001f2e: 8979 ldrh r1, [r7, #10]
|
|
8001f30: 2300 movs r3, #0
|
|
8001f32: 9300 str r3, [sp, #0]
|
|
8001f34: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8001f38: 68f8 ldr r0, [r7, #12]
|
|
8001f3a: f000 fc47 bl 80027cc <I2C_TransferConfig>
|
|
8001f3e: e00f b.n 8001f60 <HAL_I2C_Mem_Write+0x110>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8001f40: 68fb ldr r3, [r7, #12]
|
|
8001f42: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8001f44: b29a uxth r2, r3
|
|
8001f46: 68fb ldr r3, [r7, #12]
|
|
8001f48: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
8001f4a: 68fb ldr r3, [r7, #12]
|
|
8001f4c: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8001f4e: b2da uxtb r2, r3
|
|
8001f50: 8979 ldrh r1, [r7, #10]
|
|
8001f52: 2300 movs r3, #0
|
|
8001f54: 9300 str r3, [sp, #0]
|
|
8001f56: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8001f5a: 68f8 ldr r0, [r7, #12]
|
|
8001f5c: f000 fc36 bl 80027cc <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8001f60: 697a ldr r2, [r7, #20]
|
|
8001f62: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8001f64: 68f8 ldr r0, [r7, #12]
|
|
8001f66: f000 fac6 bl 80024f6 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8001f6a: 4603 mov r3, r0
|
|
8001f6c: 2b00 cmp r3, #0
|
|
8001f6e: d001 beq.n 8001f74 <HAL_I2C_Mem_Write+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
8001f70: 2301 movs r3, #1
|
|
8001f72: e07b b.n 800206c <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Write data to TXDR */
|
|
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
|
8001f74: 68fb ldr r3, [r7, #12]
|
|
8001f76: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001f78: 781a ldrb r2, [r3, #0]
|
|
8001f7a: 68fb ldr r3, [r7, #12]
|
|
8001f7c: 681b ldr r3, [r3, #0]
|
|
8001f7e: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8001f80: 68fb ldr r3, [r7, #12]
|
|
8001f82: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001f84: 1c5a adds r2, r3, #1
|
|
8001f86: 68fb ldr r3, [r7, #12]
|
|
8001f88: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferCount--;
|
|
8001f8a: 68fb ldr r3, [r7, #12]
|
|
8001f8c: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8001f8e: b29b uxth r3, r3
|
|
8001f90: 3b01 subs r3, #1
|
|
8001f92: b29a uxth r2, r3
|
|
8001f94: 68fb ldr r3, [r7, #12]
|
|
8001f96: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize--;
|
|
8001f98: 68fb ldr r3, [r7, #12]
|
|
8001f9a: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8001f9c: 3b01 subs r3, #1
|
|
8001f9e: b29a uxth r2, r3
|
|
8001fa0: 68fb ldr r3, [r7, #12]
|
|
8001fa2: 851a strh r2, [r3, #40] @ 0x28
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8001fa4: 68fb ldr r3, [r7, #12]
|
|
8001fa6: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8001fa8: b29b uxth r3, r3
|
|
8001faa: 2b00 cmp r3, #0
|
|
8001fac: d034 beq.n 8002018 <HAL_I2C_Mem_Write+0x1c8>
|
|
8001fae: 68fb ldr r3, [r7, #12]
|
|
8001fb0: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8001fb2: 2b00 cmp r3, #0
|
|
8001fb4: d130 bne.n 8002018 <HAL_I2C_Mem_Write+0x1c8>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8001fb6: 697b ldr r3, [r7, #20]
|
|
8001fb8: 9300 str r3, [sp, #0]
|
|
8001fba: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001fbc: 2200 movs r2, #0
|
|
8001fbe: 2180 movs r1, #128 @ 0x80
|
|
8001fc0: 68f8 ldr r0, [r7, #12]
|
|
8001fc2: f000 fa3f bl 8002444 <I2C_WaitOnFlagUntilTimeout>
|
|
8001fc6: 4603 mov r3, r0
|
|
8001fc8: 2b00 cmp r3, #0
|
|
8001fca: d001 beq.n 8001fd0 <HAL_I2C_Mem_Write+0x180>
|
|
{
|
|
return HAL_ERROR;
|
|
8001fcc: 2301 movs r3, #1
|
|
8001fce: e04d b.n 800206c <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8001fd0: 68fb ldr r3, [r7, #12]
|
|
8001fd2: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8001fd4: b29b uxth r3, r3
|
|
8001fd6: 2bff cmp r3, #255 @ 0xff
|
|
8001fd8: d90e bls.n 8001ff8 <HAL_I2C_Mem_Write+0x1a8>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8001fda: 68fb ldr r3, [r7, #12]
|
|
8001fdc: 22ff movs r2, #255 @ 0xff
|
|
8001fde: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8001fe0: 68fb ldr r3, [r7, #12]
|
|
8001fe2: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8001fe4: b2da uxtb r2, r3
|
|
8001fe6: 8979 ldrh r1, [r7, #10]
|
|
8001fe8: 2300 movs r3, #0
|
|
8001fea: 9300 str r3, [sp, #0]
|
|
8001fec: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8001ff0: 68f8 ldr r0, [r7, #12]
|
|
8001ff2: f000 fbeb bl 80027cc <I2C_TransferConfig>
|
|
8001ff6: e00f b.n 8002018 <HAL_I2C_Mem_Write+0x1c8>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8001ff8: 68fb ldr r3, [r7, #12]
|
|
8001ffa: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8001ffc: b29a uxth r2, r3
|
|
8001ffe: 68fb ldr r3, [r7, #12]
|
|
8002000: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8002002: 68fb ldr r3, [r7, #12]
|
|
8002004: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002006: b2da uxtb r2, r3
|
|
8002008: 8979 ldrh r1, [r7, #10]
|
|
800200a: 2300 movs r3, #0
|
|
800200c: 9300 str r3, [sp, #0]
|
|
800200e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8002012: 68f8 ldr r0, [r7, #12]
|
|
8002014: f000 fbda bl 80027cc <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
|
|
} while (hi2c->XferCount > 0U);
|
|
8002018: 68fb ldr r3, [r7, #12]
|
|
800201a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800201c: b29b uxth r3, r3
|
|
800201e: 2b00 cmp r3, #0
|
|
8002020: d19e bne.n 8001f60 <HAL_I2C_Mem_Write+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8002022: 697a ldr r2, [r7, #20]
|
|
8002024: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8002026: 68f8 ldr r0, [r7, #12]
|
|
8002028: f000 faac bl 8002584 <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
800202c: 4603 mov r3, r0
|
|
800202e: 2b00 cmp r3, #0
|
|
8002030: d001 beq.n 8002036 <HAL_I2C_Mem_Write+0x1e6>
|
|
{
|
|
return HAL_ERROR;
|
|
8002032: 2301 movs r3, #1
|
|
8002034: e01a b.n 800206c <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8002036: 68fb ldr r3, [r7, #12]
|
|
8002038: 681b ldr r3, [r3, #0]
|
|
800203a: 2220 movs r2, #32
|
|
800203c: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
800203e: 68fb ldr r3, [r7, #12]
|
|
8002040: 681b ldr r3, [r3, #0]
|
|
8002042: 6859 ldr r1, [r3, #4]
|
|
8002044: 68fb ldr r3, [r7, #12]
|
|
8002046: 681a ldr r2, [r3, #0]
|
|
8002048: 4b0a ldr r3, [pc, #40] @ (8002074 <HAL_I2C_Mem_Write+0x224>)
|
|
800204a: 400b ands r3, r1
|
|
800204c: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800204e: 68fb ldr r3, [r7, #12]
|
|
8002050: 2220 movs r2, #32
|
|
8002052: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002056: 68fb ldr r3, [r7, #12]
|
|
8002058: 2200 movs r2, #0
|
|
800205a: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800205e: 68fb ldr r3, [r7, #12]
|
|
8002060: 2200 movs r2, #0
|
|
8002062: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8002066: 2300 movs r3, #0
|
|
8002068: e000 b.n 800206c <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800206a: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800206c: 4618 mov r0, r3
|
|
800206e: 3718 adds r7, #24
|
|
8002070: 46bd mov sp, r7
|
|
8002072: bd80 pop {r7, pc}
|
|
8002074: fe00e800 .word 0xfe00e800
|
|
|
|
08002078 <HAL_I2C_Mem_Read>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8002078: b580 push {r7, lr}
|
|
800207a: b088 sub sp, #32
|
|
800207c: af02 add r7, sp, #8
|
|
800207e: 60f8 str r0, [r7, #12]
|
|
8002080: 4608 mov r0, r1
|
|
8002082: 4611 mov r1, r2
|
|
8002084: 461a mov r2, r3
|
|
8002086: 4603 mov r3, r0
|
|
8002088: 817b strh r3, [r7, #10]
|
|
800208a: 460b mov r3, r1
|
|
800208c: 813b strh r3, [r7, #8]
|
|
800208e: 4613 mov r3, r2
|
|
8002090: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8002092: 68fb ldr r3, [r7, #12]
|
|
8002094: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8002098: b2db uxtb r3, r3
|
|
800209a: 2b20 cmp r3, #32
|
|
800209c: f040 80fd bne.w 800229a <HAL_I2C_Mem_Read+0x222>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80020a0: 6a3b ldr r3, [r7, #32]
|
|
80020a2: 2b00 cmp r3, #0
|
|
80020a4: d002 beq.n 80020ac <HAL_I2C_Mem_Read+0x34>
|
|
80020a6: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
80020a8: 2b00 cmp r3, #0
|
|
80020aa: d105 bne.n 80020b8 <HAL_I2C_Mem_Read+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
80020ac: 68fb ldr r3, [r7, #12]
|
|
80020ae: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80020b2: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
80020b4: 2301 movs r3, #1
|
|
80020b6: e0f1 b.n 800229c <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80020b8: 68fb ldr r3, [r7, #12]
|
|
80020ba: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
80020be: 2b01 cmp r3, #1
|
|
80020c0: d101 bne.n 80020c6 <HAL_I2C_Mem_Read+0x4e>
|
|
80020c2: 2302 movs r3, #2
|
|
80020c4: e0ea b.n 800229c <HAL_I2C_Mem_Read+0x224>
|
|
80020c6: 68fb ldr r3, [r7, #12]
|
|
80020c8: 2201 movs r2, #1
|
|
80020ca: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
80020ce: f7ff fb6f bl 80017b0 <HAL_GetTick>
|
|
80020d2: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
80020d4: 697b ldr r3, [r7, #20]
|
|
80020d6: 9300 str r3, [sp, #0]
|
|
80020d8: 2319 movs r3, #25
|
|
80020da: 2201 movs r2, #1
|
|
80020dc: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
80020e0: 68f8 ldr r0, [r7, #12]
|
|
80020e2: f000 f9af bl 8002444 <I2C_WaitOnFlagUntilTimeout>
|
|
80020e6: 4603 mov r3, r0
|
|
80020e8: 2b00 cmp r3, #0
|
|
80020ea: d001 beq.n 80020f0 <HAL_I2C_Mem_Read+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
80020ec: 2301 movs r3, #1
|
|
80020ee: e0d5 b.n 800229c <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
80020f0: 68fb ldr r3, [r7, #12]
|
|
80020f2: 2222 movs r2, #34 @ 0x22
|
|
80020f4: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
80020f8: 68fb ldr r3, [r7, #12]
|
|
80020fa: 2240 movs r2, #64 @ 0x40
|
|
80020fc: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002100: 68fb ldr r3, [r7, #12]
|
|
8002102: 2200 movs r2, #0
|
|
8002104: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8002106: 68fb ldr r3, [r7, #12]
|
|
8002108: 6a3a ldr r2, [r7, #32]
|
|
800210a: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
800210c: 68fb ldr r3, [r7, #12]
|
|
800210e: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
8002110: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8002112: 68fb ldr r3, [r7, #12]
|
|
8002114: 2200 movs r2, #0
|
|
8002116: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8002118: 88f8 ldrh r0, [r7, #6]
|
|
800211a: 893a ldrh r2, [r7, #8]
|
|
800211c: 8979 ldrh r1, [r7, #10]
|
|
800211e: 697b ldr r3, [r7, #20]
|
|
8002120: 9301 str r3, [sp, #4]
|
|
8002122: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002124: 9300 str r3, [sp, #0]
|
|
8002126: 4603 mov r3, r0
|
|
8002128: 68f8 ldr r0, [r7, #12]
|
|
800212a: f000 f913 bl 8002354 <I2C_RequestMemoryRead>
|
|
800212e: 4603 mov r3, r0
|
|
8002130: 2b00 cmp r3, #0
|
|
8002132: d005 beq.n 8002140 <HAL_I2C_Mem_Read+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002134: 68fb ldr r3, [r7, #12]
|
|
8002136: 2200 movs r2, #0
|
|
8002138: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
800213c: 2301 movs r3, #1
|
|
800213e: e0ad b.n 800229c <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Send Slave Address */
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002140: 68fb ldr r3, [r7, #12]
|
|
8002142: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002144: b29b uxth r3, r3
|
|
8002146: 2bff cmp r3, #255 @ 0xff
|
|
8002148: d90e bls.n 8002168 <HAL_I2C_Mem_Read+0xf0>
|
|
{
|
|
hi2c->XferSize = 1U;
|
|
800214a: 68fb ldr r3, [r7, #12]
|
|
800214c: 2201 movs r2, #1
|
|
800214e: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8002150: 68fb ldr r3, [r7, #12]
|
|
8002152: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002154: b2da uxtb r2, r3
|
|
8002156: 8979 ldrh r1, [r7, #10]
|
|
8002158: 4b52 ldr r3, [pc, #328] @ (80022a4 <HAL_I2C_Mem_Read+0x22c>)
|
|
800215a: 9300 str r3, [sp, #0]
|
|
800215c: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8002160: 68f8 ldr r0, [r7, #12]
|
|
8002162: f000 fb33 bl 80027cc <I2C_TransferConfig>
|
|
8002166: e00f b.n 8002188 <HAL_I2C_Mem_Read+0x110>
|
|
I2C_GENERATE_START_READ);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002168: 68fb ldr r3, [r7, #12]
|
|
800216a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800216c: b29a uxth r2, r3
|
|
800216e: 68fb ldr r3, [r7, #12]
|
|
8002170: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8002172: 68fb ldr r3, [r7, #12]
|
|
8002174: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002176: b2da uxtb r2, r3
|
|
8002178: 8979 ldrh r1, [r7, #10]
|
|
800217a: 4b4a ldr r3, [pc, #296] @ (80022a4 <HAL_I2C_Mem_Read+0x22c>)
|
|
800217c: 9300 str r3, [sp, #0]
|
|
800217e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8002182: 68f8 ldr r0, [r7, #12]
|
|
8002184: f000 fb22 bl 80027cc <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
|
|
8002188: 697b ldr r3, [r7, #20]
|
|
800218a: 9300 str r3, [sp, #0]
|
|
800218c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800218e: 2200 movs r2, #0
|
|
8002190: 2104 movs r1, #4
|
|
8002192: 68f8 ldr r0, [r7, #12]
|
|
8002194: f000 f956 bl 8002444 <I2C_WaitOnFlagUntilTimeout>
|
|
8002198: 4603 mov r3, r0
|
|
800219a: 2b00 cmp r3, #0
|
|
800219c: d001 beq.n 80021a2 <HAL_I2C_Mem_Read+0x12a>
|
|
{
|
|
return HAL_ERROR;
|
|
800219e: 2301 movs r3, #1
|
|
80021a0: e07c b.n 800229c <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
80021a2: 68fb ldr r3, [r7, #12]
|
|
80021a4: 681b ldr r3, [r3, #0]
|
|
80021a6: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
80021a8: 68fb ldr r3, [r7, #12]
|
|
80021aa: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80021ac: b2d2 uxtb r2, r2
|
|
80021ae: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
80021b0: 68fb ldr r3, [r7, #12]
|
|
80021b2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80021b4: 1c5a adds r2, r3, #1
|
|
80021b6: 68fb ldr r3, [r7, #12]
|
|
80021b8: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferSize--;
|
|
80021ba: 68fb ldr r3, [r7, #12]
|
|
80021bc: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80021be: 3b01 subs r3, #1
|
|
80021c0: b29a uxth r2, r3
|
|
80021c2: 68fb ldr r3, [r7, #12]
|
|
80021c4: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
80021c6: 68fb ldr r3, [r7, #12]
|
|
80021c8: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80021ca: b29b uxth r3, r3
|
|
80021cc: 3b01 subs r3, #1
|
|
80021ce: b29a uxth r2, r3
|
|
80021d0: 68fb ldr r3, [r7, #12]
|
|
80021d2: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
80021d4: 68fb ldr r3, [r7, #12]
|
|
80021d6: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80021d8: b29b uxth r3, r3
|
|
80021da: 2b00 cmp r3, #0
|
|
80021dc: d034 beq.n 8002248 <HAL_I2C_Mem_Read+0x1d0>
|
|
80021de: 68fb ldr r3, [r7, #12]
|
|
80021e0: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80021e2: 2b00 cmp r3, #0
|
|
80021e4: d130 bne.n 8002248 <HAL_I2C_Mem_Read+0x1d0>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
80021e6: 697b ldr r3, [r7, #20]
|
|
80021e8: 9300 str r3, [sp, #0]
|
|
80021ea: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80021ec: 2200 movs r2, #0
|
|
80021ee: 2180 movs r1, #128 @ 0x80
|
|
80021f0: 68f8 ldr r0, [r7, #12]
|
|
80021f2: f000 f927 bl 8002444 <I2C_WaitOnFlagUntilTimeout>
|
|
80021f6: 4603 mov r3, r0
|
|
80021f8: 2b00 cmp r3, #0
|
|
80021fa: d001 beq.n 8002200 <HAL_I2C_Mem_Read+0x188>
|
|
{
|
|
return HAL_ERROR;
|
|
80021fc: 2301 movs r3, #1
|
|
80021fe: e04d b.n 800229c <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002200: 68fb ldr r3, [r7, #12]
|
|
8002202: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002204: b29b uxth r3, r3
|
|
8002206: 2bff cmp r3, #255 @ 0xff
|
|
8002208: d90e bls.n 8002228 <HAL_I2C_Mem_Read+0x1b0>
|
|
{
|
|
hi2c->XferSize = 1U;
|
|
800220a: 68fb ldr r3, [r7, #12]
|
|
800220c: 2201 movs r2, #1
|
|
800220e: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8002210: 68fb ldr r3, [r7, #12]
|
|
8002212: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002214: b2da uxtb r2, r3
|
|
8002216: 8979 ldrh r1, [r7, #10]
|
|
8002218: 2300 movs r3, #0
|
|
800221a: 9300 str r3, [sp, #0]
|
|
800221c: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8002220: 68f8 ldr r0, [r7, #12]
|
|
8002222: f000 fad3 bl 80027cc <I2C_TransferConfig>
|
|
8002226: e00f b.n 8002248 <HAL_I2C_Mem_Read+0x1d0>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002228: 68fb ldr r3, [r7, #12]
|
|
800222a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800222c: b29a uxth r2, r3
|
|
800222e: 68fb ldr r3, [r7, #12]
|
|
8002230: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8002232: 68fb ldr r3, [r7, #12]
|
|
8002234: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002236: b2da uxtb r2, r3
|
|
8002238: 8979 ldrh r1, [r7, #10]
|
|
800223a: 2300 movs r3, #0
|
|
800223c: 9300 str r3, [sp, #0]
|
|
800223e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8002242: 68f8 ldr r0, [r7, #12]
|
|
8002244: f000 fac2 bl 80027cc <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
} while (hi2c->XferCount > 0U);
|
|
8002248: 68fb ldr r3, [r7, #12]
|
|
800224a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800224c: b29b uxth r3, r3
|
|
800224e: 2b00 cmp r3, #0
|
|
8002250: d19a bne.n 8002188 <HAL_I2C_Mem_Read+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8002252: 697a ldr r2, [r7, #20]
|
|
8002254: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8002256: 68f8 ldr r0, [r7, #12]
|
|
8002258: f000 f994 bl 8002584 <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
800225c: 4603 mov r3, r0
|
|
800225e: 2b00 cmp r3, #0
|
|
8002260: d001 beq.n 8002266 <HAL_I2C_Mem_Read+0x1ee>
|
|
{
|
|
return HAL_ERROR;
|
|
8002262: 2301 movs r3, #1
|
|
8002264: e01a b.n 800229c <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8002266: 68fb ldr r3, [r7, #12]
|
|
8002268: 681b ldr r3, [r3, #0]
|
|
800226a: 2220 movs r2, #32
|
|
800226c: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
800226e: 68fb ldr r3, [r7, #12]
|
|
8002270: 681b ldr r3, [r3, #0]
|
|
8002272: 6859 ldr r1, [r3, #4]
|
|
8002274: 68fb ldr r3, [r7, #12]
|
|
8002276: 681a ldr r2, [r3, #0]
|
|
8002278: 4b0b ldr r3, [pc, #44] @ (80022a8 <HAL_I2C_Mem_Read+0x230>)
|
|
800227a: 400b ands r3, r1
|
|
800227c: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800227e: 68fb ldr r3, [r7, #12]
|
|
8002280: 2220 movs r2, #32
|
|
8002282: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002286: 68fb ldr r3, [r7, #12]
|
|
8002288: 2200 movs r2, #0
|
|
800228a: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800228e: 68fb ldr r3, [r7, #12]
|
|
8002290: 2200 movs r2, #0
|
|
8002292: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8002296: 2300 movs r3, #0
|
|
8002298: e000 b.n 800229c <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800229a: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800229c: 4618 mov r0, r3
|
|
800229e: 3718 adds r7, #24
|
|
80022a0: 46bd mov sp, r7
|
|
80022a2: bd80 pop {r7, pc}
|
|
80022a4: 80002400 .word 0x80002400
|
|
80022a8: fe00e800 .word 0xfe00e800
|
|
|
|
080022ac <I2C_RequestMemoryWrite>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
80022ac: b580 push {r7, lr}
|
|
80022ae: b086 sub sp, #24
|
|
80022b0: af02 add r7, sp, #8
|
|
80022b2: 60f8 str r0, [r7, #12]
|
|
80022b4: 4608 mov r0, r1
|
|
80022b6: 4611 mov r1, r2
|
|
80022b8: 461a mov r2, r3
|
|
80022ba: 4603 mov r3, r0
|
|
80022bc: 817b strh r3, [r7, #10]
|
|
80022be: 460b mov r3, r1
|
|
80022c0: 813b strh r3, [r7, #8]
|
|
80022c2: 4613 mov r3, r2
|
|
80022c4: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
|
80022c6: 88fb ldrh r3, [r7, #6]
|
|
80022c8: b2da uxtb r2, r3
|
|
80022ca: 8979 ldrh r1, [r7, #10]
|
|
80022cc: 4b20 ldr r3, [pc, #128] @ (8002350 <I2C_RequestMemoryWrite+0xa4>)
|
|
80022ce: 9300 str r3, [sp, #0]
|
|
80022d0: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
80022d4: 68f8 ldr r0, [r7, #12]
|
|
80022d6: f000 fa79 bl 80027cc <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80022da: 69fa ldr r2, [r7, #28]
|
|
80022dc: 69b9 ldr r1, [r7, #24]
|
|
80022de: 68f8 ldr r0, [r7, #12]
|
|
80022e0: f000 f909 bl 80024f6 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80022e4: 4603 mov r3, r0
|
|
80022e6: 2b00 cmp r3, #0
|
|
80022e8: d001 beq.n 80022ee <I2C_RequestMemoryWrite+0x42>
|
|
{
|
|
return HAL_ERROR;
|
|
80022ea: 2301 movs r3, #1
|
|
80022ec: e02c b.n 8002348 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
80022ee: 88fb ldrh r3, [r7, #6]
|
|
80022f0: 2b01 cmp r3, #1
|
|
80022f2: d105 bne.n 8002300 <I2C_RequestMemoryWrite+0x54>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80022f4: 893b ldrh r3, [r7, #8]
|
|
80022f6: b2da uxtb r2, r3
|
|
80022f8: 68fb ldr r3, [r7, #12]
|
|
80022fa: 681b ldr r3, [r3, #0]
|
|
80022fc: 629a str r2, [r3, #40] @ 0x28
|
|
80022fe: e015 b.n 800232c <I2C_RequestMemoryWrite+0x80>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
8002300: 893b ldrh r3, [r7, #8]
|
|
8002302: 0a1b lsrs r3, r3, #8
|
|
8002304: b29b uxth r3, r3
|
|
8002306: b2da uxtb r2, r3
|
|
8002308: 68fb ldr r3, [r7, #12]
|
|
800230a: 681b ldr r3, [r3, #0]
|
|
800230c: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
800230e: 69fa ldr r2, [r7, #28]
|
|
8002310: 69b9 ldr r1, [r7, #24]
|
|
8002312: 68f8 ldr r0, [r7, #12]
|
|
8002314: f000 f8ef bl 80024f6 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8002318: 4603 mov r3, r0
|
|
800231a: 2b00 cmp r3, #0
|
|
800231c: d001 beq.n 8002322 <I2C_RequestMemoryWrite+0x76>
|
|
{
|
|
return HAL_ERROR;
|
|
800231e: 2301 movs r3, #1
|
|
8002320: e012 b.n 8002348 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8002322: 893b ldrh r3, [r7, #8]
|
|
8002324: b2da uxtb r2, r3
|
|
8002326: 68fb ldr r3, [r7, #12]
|
|
8002328: 681b ldr r3, [r3, #0]
|
|
800232a: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
|
|
800232c: 69fb ldr r3, [r7, #28]
|
|
800232e: 9300 str r3, [sp, #0]
|
|
8002330: 69bb ldr r3, [r7, #24]
|
|
8002332: 2200 movs r2, #0
|
|
8002334: 2180 movs r1, #128 @ 0x80
|
|
8002336: 68f8 ldr r0, [r7, #12]
|
|
8002338: f000 f884 bl 8002444 <I2C_WaitOnFlagUntilTimeout>
|
|
800233c: 4603 mov r3, r0
|
|
800233e: 2b00 cmp r3, #0
|
|
8002340: d001 beq.n 8002346 <I2C_RequestMemoryWrite+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8002342: 2301 movs r3, #1
|
|
8002344: e000 b.n 8002348 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002346: 2300 movs r3, #0
|
|
}
|
|
8002348: 4618 mov r0, r3
|
|
800234a: 3710 adds r7, #16
|
|
800234c: 46bd mov sp, r7
|
|
800234e: bd80 pop {r7, pc}
|
|
8002350: 80002000 .word 0x80002000
|
|
|
|
08002354 <I2C_RequestMemoryRead>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8002354: b580 push {r7, lr}
|
|
8002356: b086 sub sp, #24
|
|
8002358: af02 add r7, sp, #8
|
|
800235a: 60f8 str r0, [r7, #12]
|
|
800235c: 4608 mov r0, r1
|
|
800235e: 4611 mov r1, r2
|
|
8002360: 461a mov r2, r3
|
|
8002362: 4603 mov r3, r0
|
|
8002364: 817b strh r3, [r7, #10]
|
|
8002366: 460b mov r3, r1
|
|
8002368: 813b strh r3, [r7, #8]
|
|
800236a: 4613 mov r3, r2
|
|
800236c: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
|
800236e: 88fb ldrh r3, [r7, #6]
|
|
8002370: b2da uxtb r2, r3
|
|
8002372: 8979 ldrh r1, [r7, #10]
|
|
8002374: 4b20 ldr r3, [pc, #128] @ (80023f8 <I2C_RequestMemoryRead+0xa4>)
|
|
8002376: 9300 str r3, [sp, #0]
|
|
8002378: 2300 movs r3, #0
|
|
800237a: 68f8 ldr r0, [r7, #12]
|
|
800237c: f000 fa26 bl 80027cc <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8002380: 69fa ldr r2, [r7, #28]
|
|
8002382: 69b9 ldr r1, [r7, #24]
|
|
8002384: 68f8 ldr r0, [r7, #12]
|
|
8002386: f000 f8b6 bl 80024f6 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
800238a: 4603 mov r3, r0
|
|
800238c: 2b00 cmp r3, #0
|
|
800238e: d001 beq.n 8002394 <I2C_RequestMemoryRead+0x40>
|
|
{
|
|
return HAL_ERROR;
|
|
8002390: 2301 movs r3, #1
|
|
8002392: e02c b.n 80023ee <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
8002394: 88fb ldrh r3, [r7, #6]
|
|
8002396: 2b01 cmp r3, #1
|
|
8002398: d105 bne.n 80023a6 <I2C_RequestMemoryRead+0x52>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
800239a: 893b ldrh r3, [r7, #8]
|
|
800239c: b2da uxtb r2, r3
|
|
800239e: 68fb ldr r3, [r7, #12]
|
|
80023a0: 681b ldr r3, [r3, #0]
|
|
80023a2: 629a str r2, [r3, #40] @ 0x28
|
|
80023a4: e015 b.n 80023d2 <I2C_RequestMemoryRead+0x7e>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
80023a6: 893b ldrh r3, [r7, #8]
|
|
80023a8: 0a1b lsrs r3, r3, #8
|
|
80023aa: b29b uxth r3, r3
|
|
80023ac: b2da uxtb r2, r3
|
|
80023ae: 68fb ldr r3, [r7, #12]
|
|
80023b0: 681b ldr r3, [r3, #0]
|
|
80023b2: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80023b4: 69fa ldr r2, [r7, #28]
|
|
80023b6: 69b9 ldr r1, [r7, #24]
|
|
80023b8: 68f8 ldr r0, [r7, #12]
|
|
80023ba: f000 f89c bl 80024f6 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80023be: 4603 mov r3, r0
|
|
80023c0: 2b00 cmp r3, #0
|
|
80023c2: d001 beq.n 80023c8 <I2C_RequestMemoryRead+0x74>
|
|
{
|
|
return HAL_ERROR;
|
|
80023c4: 2301 movs r3, #1
|
|
80023c6: e012 b.n 80023ee <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80023c8: 893b ldrh r3, [r7, #8]
|
|
80023ca: b2da uxtb r2, r3
|
|
80023cc: 68fb ldr r3, [r7, #12]
|
|
80023ce: 681b ldr r3, [r3, #0]
|
|
80023d0: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until TC flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
|
|
80023d2: 69fb ldr r3, [r7, #28]
|
|
80023d4: 9300 str r3, [sp, #0]
|
|
80023d6: 69bb ldr r3, [r7, #24]
|
|
80023d8: 2200 movs r2, #0
|
|
80023da: 2140 movs r1, #64 @ 0x40
|
|
80023dc: 68f8 ldr r0, [r7, #12]
|
|
80023de: f000 f831 bl 8002444 <I2C_WaitOnFlagUntilTimeout>
|
|
80023e2: 4603 mov r3, r0
|
|
80023e4: 2b00 cmp r3, #0
|
|
80023e6: d001 beq.n 80023ec <I2C_RequestMemoryRead+0x98>
|
|
{
|
|
return HAL_ERROR;
|
|
80023e8: 2301 movs r3, #1
|
|
80023ea: e000 b.n 80023ee <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80023ec: 2300 movs r3, #0
|
|
}
|
|
80023ee: 4618 mov r0, r3
|
|
80023f0: 3710 adds r7, #16
|
|
80023f2: 46bd mov sp, r7
|
|
80023f4: bd80 pop {r7, pc}
|
|
80023f6: bf00 nop
|
|
80023f8: 80002000 .word 0x80002000
|
|
|
|
080023fc <I2C_Flush_TXDR>:
|
|
* @brief I2C Tx data register flush process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
80023fc: b480 push {r7}
|
|
80023fe: b083 sub sp, #12
|
|
8002400: af00 add r7, sp, #0
|
|
8002402: 6078 str r0, [r7, #4]
|
|
/* If a pending TXIS flag is set */
|
|
/* Write a dummy data in TXDR to clear it */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
|
|
8002404: 687b ldr r3, [r7, #4]
|
|
8002406: 681b ldr r3, [r3, #0]
|
|
8002408: 699b ldr r3, [r3, #24]
|
|
800240a: f003 0302 and.w r3, r3, #2
|
|
800240e: 2b02 cmp r3, #2
|
|
8002410: d103 bne.n 800241a <I2C_Flush_TXDR+0x1e>
|
|
{
|
|
hi2c->Instance->TXDR = 0x00U;
|
|
8002412: 687b ldr r3, [r7, #4]
|
|
8002414: 681b ldr r3, [r3, #0]
|
|
8002416: 2200 movs r2, #0
|
|
8002418: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Flush TX register if not empty */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
800241a: 687b ldr r3, [r7, #4]
|
|
800241c: 681b ldr r3, [r3, #0]
|
|
800241e: 699b ldr r3, [r3, #24]
|
|
8002420: f003 0301 and.w r3, r3, #1
|
|
8002424: 2b01 cmp r3, #1
|
|
8002426: d007 beq.n 8002438 <I2C_Flush_TXDR+0x3c>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
|
|
8002428: 687b ldr r3, [r7, #4]
|
|
800242a: 681b ldr r3, [r3, #0]
|
|
800242c: 699a ldr r2, [r3, #24]
|
|
800242e: 687b ldr r3, [r7, #4]
|
|
8002430: 681b ldr r3, [r3, #0]
|
|
8002432: f042 0201 orr.w r2, r2, #1
|
|
8002436: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
8002438: bf00 nop
|
|
800243a: 370c adds r7, #12
|
|
800243c: 46bd mov sp, r7
|
|
800243e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002442: 4770 bx lr
|
|
|
|
08002444 <I2C_WaitOnFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8002444: b580 push {r7, lr}
|
|
8002446: b084 sub sp, #16
|
|
8002448: af00 add r7, sp, #0
|
|
800244a: 60f8 str r0, [r7, #12]
|
|
800244c: 60b9 str r1, [r7, #8]
|
|
800244e: 603b str r3, [r7, #0]
|
|
8002450: 4613 mov r3, r2
|
|
8002452: 71fb strb r3, [r7, #7]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
8002454: e03b b.n 80024ce <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8002456: 69ba ldr r2, [r7, #24]
|
|
8002458: 6839 ldr r1, [r7, #0]
|
|
800245a: 68f8 ldr r0, [r7, #12]
|
|
800245c: f000 f8d6 bl 800260c <I2C_IsErrorOccurred>
|
|
8002460: 4603 mov r3, r0
|
|
8002462: 2b00 cmp r3, #0
|
|
8002464: d001 beq.n 800246a <I2C_WaitOnFlagUntilTimeout+0x26>
|
|
{
|
|
return HAL_ERROR;
|
|
8002466: 2301 movs r3, #1
|
|
8002468: e041 b.n 80024ee <I2C_WaitOnFlagUntilTimeout+0xaa>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800246a: 683b ldr r3, [r7, #0]
|
|
800246c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8002470: d02d beq.n 80024ce <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8002472: f7ff f99d bl 80017b0 <HAL_GetTick>
|
|
8002476: 4602 mov r2, r0
|
|
8002478: 69bb ldr r3, [r7, #24]
|
|
800247a: 1ad3 subs r3, r2, r3
|
|
800247c: 683a ldr r2, [r7, #0]
|
|
800247e: 429a cmp r2, r3
|
|
8002480: d302 bcc.n 8002488 <I2C_WaitOnFlagUntilTimeout+0x44>
|
|
8002482: 683b ldr r3, [r7, #0]
|
|
8002484: 2b00 cmp r3, #0
|
|
8002486: d122 bne.n 80024ce <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
|
|
8002488: 68fb ldr r3, [r7, #12]
|
|
800248a: 681b ldr r3, [r3, #0]
|
|
800248c: 699a ldr r2, [r3, #24]
|
|
800248e: 68bb ldr r3, [r7, #8]
|
|
8002490: 4013 ands r3, r2
|
|
8002492: 68ba ldr r2, [r7, #8]
|
|
8002494: 429a cmp r2, r3
|
|
8002496: bf0c ite eq
|
|
8002498: 2301 moveq r3, #1
|
|
800249a: 2300 movne r3, #0
|
|
800249c: b2db uxtb r3, r3
|
|
800249e: 461a mov r2, r3
|
|
80024a0: 79fb ldrb r3, [r7, #7]
|
|
80024a2: 429a cmp r2, r3
|
|
80024a4: d113 bne.n 80024ce <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80024a6: 68fb ldr r3, [r7, #12]
|
|
80024a8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80024aa: f043 0220 orr.w r2, r3, #32
|
|
80024ae: 68fb ldr r3, [r7, #12]
|
|
80024b0: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80024b2: 68fb ldr r3, [r7, #12]
|
|
80024b4: 2220 movs r2, #32
|
|
80024b6: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80024ba: 68fb ldr r3, [r7, #12]
|
|
80024bc: 2200 movs r2, #0
|
|
80024be: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80024c2: 68fb ldr r3, [r7, #12]
|
|
80024c4: 2200 movs r2, #0
|
|
80024c6: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
80024ca: 2301 movs r3, #1
|
|
80024cc: e00f b.n 80024ee <I2C_WaitOnFlagUntilTimeout+0xaa>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
80024ce: 68fb ldr r3, [r7, #12]
|
|
80024d0: 681b ldr r3, [r3, #0]
|
|
80024d2: 699a ldr r2, [r3, #24]
|
|
80024d4: 68bb ldr r3, [r7, #8]
|
|
80024d6: 4013 ands r3, r2
|
|
80024d8: 68ba ldr r2, [r7, #8]
|
|
80024da: 429a cmp r2, r3
|
|
80024dc: bf0c ite eq
|
|
80024de: 2301 moveq r3, #1
|
|
80024e0: 2300 movne r3, #0
|
|
80024e2: b2db uxtb r3, r3
|
|
80024e4: 461a mov r2, r3
|
|
80024e6: 79fb ldrb r3, [r7, #7]
|
|
80024e8: 429a cmp r2, r3
|
|
80024ea: d0b4 beq.n 8002456 <I2C_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80024ec: 2300 movs r3, #0
|
|
}
|
|
80024ee: 4618 mov r0, r3
|
|
80024f0: 3710 adds r7, #16
|
|
80024f2: 46bd mov sp, r7
|
|
80024f4: bd80 pop {r7, pc}
|
|
|
|
080024f6 <I2C_WaitOnTXISFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
80024f6: b580 push {r7, lr}
|
|
80024f8: b084 sub sp, #16
|
|
80024fa: af00 add r7, sp, #0
|
|
80024fc: 60f8 str r0, [r7, #12]
|
|
80024fe: 60b9 str r1, [r7, #8]
|
|
8002500: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
8002502: e033 b.n 800256c <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8002504: 687a ldr r2, [r7, #4]
|
|
8002506: 68b9 ldr r1, [r7, #8]
|
|
8002508: 68f8 ldr r0, [r7, #12]
|
|
800250a: f000 f87f bl 800260c <I2C_IsErrorOccurred>
|
|
800250e: 4603 mov r3, r0
|
|
8002510: 2b00 cmp r3, #0
|
|
8002512: d001 beq.n 8002518 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
8002514: 2301 movs r3, #1
|
|
8002516: e031 b.n 800257c <I2C_WaitOnTXISFlagUntilTimeout+0x86>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8002518: 68bb ldr r3, [r7, #8]
|
|
800251a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800251e: d025 beq.n 800256c <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8002520: f7ff f946 bl 80017b0 <HAL_GetTick>
|
|
8002524: 4602 mov r2, r0
|
|
8002526: 687b ldr r3, [r7, #4]
|
|
8002528: 1ad3 subs r3, r2, r3
|
|
800252a: 68ba ldr r2, [r7, #8]
|
|
800252c: 429a cmp r2, r3
|
|
800252e: d302 bcc.n 8002536 <I2C_WaitOnTXISFlagUntilTimeout+0x40>
|
|
8002530: 68bb ldr r3, [r7, #8]
|
|
8002532: 2b00 cmp r3, #0
|
|
8002534: d11a bne.n 800256c <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
|
|
8002536: 68fb ldr r3, [r7, #12]
|
|
8002538: 681b ldr r3, [r3, #0]
|
|
800253a: 699b ldr r3, [r3, #24]
|
|
800253c: f003 0302 and.w r3, r3, #2
|
|
8002540: 2b02 cmp r3, #2
|
|
8002542: d013 beq.n 800256c <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8002544: 68fb ldr r3, [r7, #12]
|
|
8002546: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002548: f043 0220 orr.w r2, r3, #32
|
|
800254c: 68fb ldr r3, [r7, #12]
|
|
800254e: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8002550: 68fb ldr r3, [r7, #12]
|
|
8002552: 2220 movs r2, #32
|
|
8002554: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002558: 68fb ldr r3, [r7, #12]
|
|
800255a: 2200 movs r2, #0
|
|
800255c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002560: 68fb ldr r3, [r7, #12]
|
|
8002562: 2200 movs r2, #0
|
|
8002564: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
8002568: 2301 movs r3, #1
|
|
800256a: e007 b.n 800257c <I2C_WaitOnTXISFlagUntilTimeout+0x86>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
800256c: 68fb ldr r3, [r7, #12]
|
|
800256e: 681b ldr r3, [r3, #0]
|
|
8002570: 699b ldr r3, [r3, #24]
|
|
8002572: f003 0302 and.w r3, r3, #2
|
|
8002576: 2b02 cmp r3, #2
|
|
8002578: d1c4 bne.n 8002504 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800257a: 2300 movs r3, #0
|
|
}
|
|
800257c: 4618 mov r0, r3
|
|
800257e: 3710 adds r7, #16
|
|
8002580: 46bd mov sp, r7
|
|
8002582: bd80 pop {r7, pc}
|
|
|
|
08002584 <I2C_WaitOnSTOPFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
8002584: b580 push {r7, lr}
|
|
8002586: b084 sub sp, #16
|
|
8002588: af00 add r7, sp, #0
|
|
800258a: 60f8 str r0, [r7, #12]
|
|
800258c: 60b9 str r1, [r7, #8]
|
|
800258e: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8002590: e02f b.n 80025f2 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8002592: 687a ldr r2, [r7, #4]
|
|
8002594: 68b9 ldr r1, [r7, #8]
|
|
8002596: 68f8 ldr r0, [r7, #12]
|
|
8002598: f000 f838 bl 800260c <I2C_IsErrorOccurred>
|
|
800259c: 4603 mov r3, r0
|
|
800259e: 2b00 cmp r3, #0
|
|
80025a0: d001 beq.n 80025a6 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
80025a2: 2301 movs r3, #1
|
|
80025a4: e02d b.n 8002602 <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80025a6: f7ff f903 bl 80017b0 <HAL_GetTick>
|
|
80025aa: 4602 mov r2, r0
|
|
80025ac: 687b ldr r3, [r7, #4]
|
|
80025ae: 1ad3 subs r3, r2, r3
|
|
80025b0: 68ba ldr r2, [r7, #8]
|
|
80025b2: 429a cmp r2, r3
|
|
80025b4: d302 bcc.n 80025bc <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
|
|
80025b6: 68bb ldr r3, [r7, #8]
|
|
80025b8: 2b00 cmp r3, #0
|
|
80025ba: d11a bne.n 80025f2 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
|
|
80025bc: 68fb ldr r3, [r7, #12]
|
|
80025be: 681b ldr r3, [r3, #0]
|
|
80025c0: 699b ldr r3, [r3, #24]
|
|
80025c2: f003 0320 and.w r3, r3, #32
|
|
80025c6: 2b20 cmp r3, #32
|
|
80025c8: d013 beq.n 80025f2 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80025ca: 68fb ldr r3, [r7, #12]
|
|
80025cc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80025ce: f043 0220 orr.w r2, r3, #32
|
|
80025d2: 68fb ldr r3, [r7, #12]
|
|
80025d4: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80025d6: 68fb ldr r3, [r7, #12]
|
|
80025d8: 2220 movs r2, #32
|
|
80025da: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80025de: 68fb ldr r3, [r7, #12]
|
|
80025e0: 2200 movs r2, #0
|
|
80025e2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80025e6: 68fb ldr r3, [r7, #12]
|
|
80025e8: 2200 movs r2, #0
|
|
80025ea: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
80025ee: 2301 movs r3, #1
|
|
80025f0: e007 b.n 8002602 <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80025f2: 68fb ldr r3, [r7, #12]
|
|
80025f4: 681b ldr r3, [r3, #0]
|
|
80025f6: 699b ldr r3, [r3, #24]
|
|
80025f8: f003 0320 and.w r3, r3, #32
|
|
80025fc: 2b20 cmp r3, #32
|
|
80025fe: d1c8 bne.n 8002592 <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8002600: 2300 movs r3, #0
|
|
}
|
|
8002602: 4618 mov r0, r3
|
|
8002604: 3710 adds r7, #16
|
|
8002606: 46bd mov sp, r7
|
|
8002608: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800260c <I2C_IsErrorOccurred>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800260c: b580 push {r7, lr}
|
|
800260e: b08a sub sp, #40 @ 0x28
|
|
8002610: af00 add r7, sp, #0
|
|
8002612: 60f8 str r0, [r7, #12]
|
|
8002614: 60b9 str r1, [r7, #8]
|
|
8002616: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8002618: 2300 movs r3, #0
|
|
800261a: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
uint32_t itflag = hi2c->Instance->ISR;
|
|
800261e: 68fb ldr r3, [r7, #12]
|
|
8002620: 681b ldr r3, [r3, #0]
|
|
8002622: 699b ldr r3, [r3, #24]
|
|
8002624: 61bb str r3, [r7, #24]
|
|
uint32_t error_code = 0;
|
|
8002626: 2300 movs r3, #0
|
|
8002628: 623b str r3, [r7, #32]
|
|
uint32_t tickstart = Tickstart;
|
|
800262a: 687b ldr r3, [r7, #4]
|
|
800262c: 61fb str r3, [r7, #28]
|
|
uint32_t tmp1;
|
|
HAL_I2C_ModeTypeDef tmp2;
|
|
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
|
|
800262e: 69bb ldr r3, [r7, #24]
|
|
8002630: f003 0310 and.w r3, r3, #16
|
|
8002634: 2b00 cmp r3, #0
|
|
8002636: d068 beq.n 800270a <I2C_IsErrorOccurred+0xfe>
|
|
{
|
|
/* Clear NACKF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8002638: 68fb ldr r3, [r7, #12]
|
|
800263a: 681b ldr r3, [r3, #0]
|
|
800263c: 2210 movs r2, #16
|
|
800263e: 61da str r2, [r3, #28]
|
|
|
|
/* Wait until STOP Flag is set or timeout occurred */
|
|
/* AutoEnd should be initiate after AF */
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
8002640: e049 b.n 80026d6 <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8002642: 68bb ldr r3, [r7, #8]
|
|
8002644: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8002648: d045 beq.n 80026d6 <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
|
800264a: f7ff f8b1 bl 80017b0 <HAL_GetTick>
|
|
800264e: 4602 mov r2, r0
|
|
8002650: 69fb ldr r3, [r7, #28]
|
|
8002652: 1ad3 subs r3, r2, r3
|
|
8002654: 68ba ldr r2, [r7, #8]
|
|
8002656: 429a cmp r2, r3
|
|
8002658: d302 bcc.n 8002660 <I2C_IsErrorOccurred+0x54>
|
|
800265a: 68bb ldr r3, [r7, #8]
|
|
800265c: 2b00 cmp r3, #0
|
|
800265e: d13a bne.n 80026d6 <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
|
|
8002660: 68fb ldr r3, [r7, #12]
|
|
8002662: 681b ldr r3, [r3, #0]
|
|
8002664: 685b ldr r3, [r3, #4]
|
|
8002666: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800266a: 617b str r3, [r7, #20]
|
|
tmp2 = hi2c->Mode;
|
|
800266c: 68fb ldr r3, [r7, #12]
|
|
800266e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8002672: 74fb strb r3, [r7, #19]
|
|
|
|
/* In case of I2C still busy, try to regenerate a STOP manually */
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
|
|
8002674: 68fb ldr r3, [r7, #12]
|
|
8002676: 681b ldr r3, [r3, #0]
|
|
8002678: 699b ldr r3, [r3, #24]
|
|
800267a: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
800267e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8002682: d121 bne.n 80026c8 <I2C_IsErrorOccurred+0xbc>
|
|
8002684: 697b ldr r3, [r7, #20]
|
|
8002686: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
800268a: d01d beq.n 80026c8 <I2C_IsErrorOccurred+0xbc>
|
|
(tmp1 != I2C_CR2_STOP) && \
|
|
800268c: 7cfb ldrb r3, [r7, #19]
|
|
800268e: 2b20 cmp r3, #32
|
|
8002690: d01a beq.n 80026c8 <I2C_IsErrorOccurred+0xbc>
|
|
(tmp2 != HAL_I2C_MODE_SLAVE))
|
|
{
|
|
/* Generate Stop */
|
|
hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
|
8002692: 68fb ldr r3, [r7, #12]
|
|
8002694: 681b ldr r3, [r3, #0]
|
|
8002696: 685a ldr r2, [r3, #4]
|
|
8002698: 68fb ldr r3, [r7, #12]
|
|
800269a: 681b ldr r3, [r3, #0]
|
|
800269c: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
80026a0: 605a str r2, [r3, #4]
|
|
|
|
/* Update Tick with new reference */
|
|
tickstart = HAL_GetTick();
|
|
80026a2: f7ff f885 bl 80017b0 <HAL_GetTick>
|
|
80026a6: 61f8 str r0, [r7, #28]
|
|
}
|
|
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80026a8: e00e b.n 80026c8 <I2C_IsErrorOccurred+0xbc>
|
|
{
|
|
/* Check for the Timeout */
|
|
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
|
|
80026aa: f7ff f881 bl 80017b0 <HAL_GetTick>
|
|
80026ae: 4602 mov r2, r0
|
|
80026b0: 69fb ldr r3, [r7, #28]
|
|
80026b2: 1ad3 subs r3, r2, r3
|
|
80026b4: 2b19 cmp r3, #25
|
|
80026b6: d907 bls.n 80026c8 <I2C_IsErrorOccurred+0xbc>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_TIMEOUT;
|
|
80026b8: 6a3b ldr r3, [r7, #32]
|
|
80026ba: f043 0320 orr.w r3, r3, #32
|
|
80026be: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
80026c0: 2301 movs r3, #1
|
|
80026c2: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
|
|
break;
|
|
80026c6: e006 b.n 80026d6 <I2C_IsErrorOccurred+0xca>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80026c8: 68fb ldr r3, [r7, #12]
|
|
80026ca: 681b ldr r3, [r3, #0]
|
|
80026cc: 699b ldr r3, [r3, #24]
|
|
80026ce: f003 0320 and.w r3, r3, #32
|
|
80026d2: 2b20 cmp r3, #32
|
|
80026d4: d1e9 bne.n 80026aa <I2C_IsErrorOccurred+0x9e>
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
80026d6: 68fb ldr r3, [r7, #12]
|
|
80026d8: 681b ldr r3, [r3, #0]
|
|
80026da: 699b ldr r3, [r3, #24]
|
|
80026dc: f003 0320 and.w r3, r3, #32
|
|
80026e0: 2b20 cmp r3, #32
|
|
80026e2: d003 beq.n 80026ec <I2C_IsErrorOccurred+0xe0>
|
|
80026e4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80026e8: 2b00 cmp r3, #0
|
|
80026ea: d0aa beq.n 8002642 <I2C_IsErrorOccurred+0x36>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* In case STOP Flag is detected, clear it */
|
|
if (status == HAL_OK)
|
|
80026ec: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80026f0: 2b00 cmp r3, #0
|
|
80026f2: d103 bne.n 80026fc <I2C_IsErrorOccurred+0xf0>
|
|
{
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
80026f4: 68fb ldr r3, [r7, #12]
|
|
80026f6: 681b ldr r3, [r3, #0]
|
|
80026f8: 2220 movs r2, #32
|
|
80026fa: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
error_code |= HAL_I2C_ERROR_AF;
|
|
80026fc: 6a3b ldr r3, [r7, #32]
|
|
80026fe: f043 0304 orr.w r3, r3, #4
|
|
8002702: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
8002704: 2301 movs r3, #1
|
|
8002706: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Refresh Content of Status register */
|
|
itflag = hi2c->Instance->ISR;
|
|
800270a: 68fb ldr r3, [r7, #12]
|
|
800270c: 681b ldr r3, [r3, #0]
|
|
800270e: 699b ldr r3, [r3, #24]
|
|
8002710: 61bb str r3, [r7, #24]
|
|
|
|
/* Then verify if an additional errors occurs */
|
|
/* Check if a Bus error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
|
|
8002712: 69bb ldr r3, [r7, #24]
|
|
8002714: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002718: 2b00 cmp r3, #0
|
|
800271a: d00b beq.n 8002734 <I2C_IsErrorOccurred+0x128>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_BERR;
|
|
800271c: 6a3b ldr r3, [r7, #32]
|
|
800271e: f043 0301 orr.w r3, r3, #1
|
|
8002722: 623b str r3, [r7, #32]
|
|
|
|
/* Clear BERR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
|
|
8002724: 68fb ldr r3, [r7, #12]
|
|
8002726: 681b ldr r3, [r3, #0]
|
|
8002728: f44f 7280 mov.w r2, #256 @ 0x100
|
|
800272c: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
800272e: 2301 movs r3, #1
|
|
8002730: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Check if an Over-Run/Under-Run error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
|
|
8002734: 69bb ldr r3, [r7, #24]
|
|
8002736: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800273a: 2b00 cmp r3, #0
|
|
800273c: d00b beq.n 8002756 <I2C_IsErrorOccurred+0x14a>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_OVR;
|
|
800273e: 6a3b ldr r3, [r7, #32]
|
|
8002740: f043 0308 orr.w r3, r3, #8
|
|
8002744: 623b str r3, [r7, #32]
|
|
|
|
/* Clear OVR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
|
|
8002746: 68fb ldr r3, [r7, #12]
|
|
8002748: 681b ldr r3, [r3, #0]
|
|
800274a: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
800274e: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
8002750: 2301 movs r3, #1
|
|
8002752: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Check if an Arbitration Loss error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
|
|
8002756: 69bb ldr r3, [r7, #24]
|
|
8002758: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800275c: 2b00 cmp r3, #0
|
|
800275e: d00b beq.n 8002778 <I2C_IsErrorOccurred+0x16c>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_ARLO;
|
|
8002760: 6a3b ldr r3, [r7, #32]
|
|
8002762: f043 0302 orr.w r3, r3, #2
|
|
8002766: 623b str r3, [r7, #32]
|
|
|
|
/* Clear ARLO flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
|
|
8002768: 68fb ldr r3, [r7, #12]
|
|
800276a: 681b ldr r3, [r3, #0]
|
|
800276c: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8002770: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
8002772: 2301 movs r3, #1
|
|
8002774: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
if (status != HAL_OK)
|
|
8002778: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800277c: 2b00 cmp r3, #0
|
|
800277e: d01c beq.n 80027ba <I2C_IsErrorOccurred+0x1ae>
|
|
{
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8002780: 68f8 ldr r0, [r7, #12]
|
|
8002782: f7ff fe3b bl 80023fc <I2C_Flush_TXDR>
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8002786: 68fb ldr r3, [r7, #12]
|
|
8002788: 681b ldr r3, [r3, #0]
|
|
800278a: 6859 ldr r1, [r3, #4]
|
|
800278c: 68fb ldr r3, [r7, #12]
|
|
800278e: 681a ldr r2, [r3, #0]
|
|
8002790: 4b0d ldr r3, [pc, #52] @ (80027c8 <I2C_IsErrorOccurred+0x1bc>)
|
|
8002792: 400b ands r3, r1
|
|
8002794: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->ErrorCode |= error_code;
|
|
8002796: 68fb ldr r3, [r7, #12]
|
|
8002798: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
800279a: 6a3b ldr r3, [r7, #32]
|
|
800279c: 431a orrs r2, r3
|
|
800279e: 68fb ldr r3, [r7, #12]
|
|
80027a0: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80027a2: 68fb ldr r3, [r7, #12]
|
|
80027a4: 2220 movs r2, #32
|
|
80027a6: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80027aa: 68fb ldr r3, [r7, #12]
|
|
80027ac: 2200 movs r2, #0
|
|
80027ae: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80027b2: 68fb ldr r3, [r7, #12]
|
|
80027b4: 2200 movs r2, #0
|
|
80027b6: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
}
|
|
|
|
return status;
|
|
80027ba: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
80027be: 4618 mov r0, r3
|
|
80027c0: 3728 adds r7, #40 @ 0x28
|
|
80027c2: 46bd mov sp, r7
|
|
80027c4: bd80 pop {r7, pc}
|
|
80027c6: bf00 nop
|
|
80027c8: fe00e800 .word 0xfe00e800
|
|
|
|
080027cc <I2C_TransferConfig>:
|
|
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
|
uint32_t Request)
|
|
{
|
|
80027cc: b480 push {r7}
|
|
80027ce: b087 sub sp, #28
|
|
80027d0: af00 add r7, sp, #0
|
|
80027d2: 60f8 str r0, [r7, #12]
|
|
80027d4: 607b str r3, [r7, #4]
|
|
80027d6: 460b mov r3, r1
|
|
80027d8: 817b strh r3, [r7, #10]
|
|
80027da: 4613 mov r3, r2
|
|
80027dc: 727b strb r3, [r7, #9]
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_TRANSFER_MODE(Mode));
|
|
assert_param(IS_TRANSFER_REQUEST(Request));
|
|
|
|
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
80027de: 897b ldrh r3, [r7, #10]
|
|
80027e0: f3c3 0209 ubfx r2, r3, #0, #10
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
80027e4: 7a7b ldrb r3, [r7, #9]
|
|
80027e6: 041b lsls r3, r3, #16
|
|
80027e8: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
80027ec: 431a orrs r2, r3
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
80027ee: 687b ldr r3, [r7, #4]
|
|
80027f0: 431a orrs r2, r3
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
80027f2: 6a3b ldr r3, [r7, #32]
|
|
80027f4: 4313 orrs r3, r2
|
|
80027f6: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
80027fa: 617b str r3, [r7, #20]
|
|
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
|
|
|
|
/* update CR2 register */
|
|
MODIFY_REG(hi2c->Instance->CR2, \
|
|
80027fc: 68fb ldr r3, [r7, #12]
|
|
80027fe: 681b ldr r3, [r3, #0]
|
|
8002800: 685a ldr r2, [r3, #4]
|
|
8002802: 6a3b ldr r3, [r7, #32]
|
|
8002804: 0d5b lsrs r3, r3, #21
|
|
8002806: f403 6180 and.w r1, r3, #1024 @ 0x400
|
|
800280a: 4b08 ldr r3, [pc, #32] @ (800282c <I2C_TransferConfig+0x60>)
|
|
800280c: 430b orrs r3, r1
|
|
800280e: 43db mvns r3, r3
|
|
8002810: ea02 0103 and.w r1, r2, r3
|
|
8002814: 68fb ldr r3, [r7, #12]
|
|
8002816: 681b ldr r3, [r3, #0]
|
|
8002818: 697a ldr r2, [r7, #20]
|
|
800281a: 430a orrs r2, r1
|
|
800281c: 605a str r2, [r3, #4]
|
|
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
|
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
|
|
I2C_CR2_START | I2C_CR2_STOP)), tmp);
|
|
}
|
|
800281e: bf00 nop
|
|
8002820: 371c adds r7, #28
|
|
8002822: 46bd mov sp, r7
|
|
8002824: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002828: 4770 bx lr
|
|
800282a: bf00 nop
|
|
800282c: 03ff63ff .word 0x03ff63ff
|
|
|
|
08002830 <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter New state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8002830: b480 push {r7}
|
|
8002832: b083 sub sp, #12
|
|
8002834: af00 add r7, sp, #0
|
|
8002836: 6078 str r0, [r7, #4]
|
|
8002838: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
800283a: 687b ldr r3, [r7, #4]
|
|
800283c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8002840: b2db uxtb r3, r3
|
|
8002842: 2b20 cmp r3, #32
|
|
8002844: d138 bne.n 80028b8 <HAL_I2CEx_ConfigAnalogFilter+0x88>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8002846: 687b ldr r3, [r7, #4]
|
|
8002848: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
800284c: 2b01 cmp r3, #1
|
|
800284e: d101 bne.n 8002854 <HAL_I2CEx_ConfigAnalogFilter+0x24>
|
|
8002850: 2302 movs r3, #2
|
|
8002852: e032 b.n 80028ba <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
8002854: 687b ldr r3, [r7, #4]
|
|
8002856: 2201 movs r2, #1
|
|
8002858: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
800285c: 687b ldr r3, [r7, #4]
|
|
800285e: 2224 movs r2, #36 @ 0x24
|
|
8002860: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8002864: 687b ldr r3, [r7, #4]
|
|
8002866: 681b ldr r3, [r3, #0]
|
|
8002868: 681a ldr r2, [r3, #0]
|
|
800286a: 687b ldr r3, [r7, #4]
|
|
800286c: 681b ldr r3, [r3, #0]
|
|
800286e: f022 0201 bic.w r2, r2, #1
|
|
8002872: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
|
8002874: 687b ldr r3, [r7, #4]
|
|
8002876: 681b ldr r3, [r3, #0]
|
|
8002878: 681a ldr r2, [r3, #0]
|
|
800287a: 687b ldr r3, [r7, #4]
|
|
800287c: 681b ldr r3, [r3, #0]
|
|
800287e: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
8002882: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog filter bit*/
|
|
hi2c->Instance->CR1 |= AnalogFilter;
|
|
8002884: 687b ldr r3, [r7, #4]
|
|
8002886: 681b ldr r3, [r3, #0]
|
|
8002888: 6819 ldr r1, [r3, #0]
|
|
800288a: 687b ldr r3, [r7, #4]
|
|
800288c: 681b ldr r3, [r3, #0]
|
|
800288e: 683a ldr r2, [r7, #0]
|
|
8002890: 430a orrs r2, r1
|
|
8002892: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8002894: 687b ldr r3, [r7, #4]
|
|
8002896: 681b ldr r3, [r3, #0]
|
|
8002898: 681a ldr r2, [r3, #0]
|
|
800289a: 687b ldr r3, [r7, #4]
|
|
800289c: 681b ldr r3, [r3, #0]
|
|
800289e: f042 0201 orr.w r2, r2, #1
|
|
80028a2: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80028a4: 687b ldr r3, [r7, #4]
|
|
80028a6: 2220 movs r2, #32
|
|
80028a8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80028ac: 687b ldr r3, [r7, #4]
|
|
80028ae: 2200 movs r2, #0
|
|
80028b0: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
80028b4: 2300 movs r3, #0
|
|
80028b6: e000 b.n 80028ba <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80028b8: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80028ba: 4618 mov r0, r3
|
|
80028bc: 370c adds r7, #12
|
|
80028be: 46bd mov sp, r7
|
|
80028c0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80028c4: 4770 bx lr
|
|
|
|
080028c6 <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
80028c6: b480 push {r7}
|
|
80028c8: b085 sub sp, #20
|
|
80028ca: af00 add r7, sp, #0
|
|
80028cc: 6078 str r0, [r7, #4]
|
|
80028ce: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
80028d0: 687b ldr r3, [r7, #4]
|
|
80028d2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80028d6: b2db uxtb r3, r3
|
|
80028d8: 2b20 cmp r3, #32
|
|
80028da: d139 bne.n 8002950 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80028dc: 687b ldr r3, [r7, #4]
|
|
80028de: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
80028e2: 2b01 cmp r3, #1
|
|
80028e4: d101 bne.n 80028ea <HAL_I2CEx_ConfigDigitalFilter+0x24>
|
|
80028e6: 2302 movs r3, #2
|
|
80028e8: e033 b.n 8002952 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
80028ea: 687b ldr r3, [r7, #4]
|
|
80028ec: 2201 movs r2, #1
|
|
80028ee: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80028f2: 687b ldr r3, [r7, #4]
|
|
80028f4: 2224 movs r2, #36 @ 0x24
|
|
80028f6: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80028fa: 687b ldr r3, [r7, #4]
|
|
80028fc: 681b ldr r3, [r3, #0]
|
|
80028fe: 681a ldr r2, [r3, #0]
|
|
8002900: 687b ldr r3, [r7, #4]
|
|
8002902: 681b ldr r3, [r3, #0]
|
|
8002904: f022 0201 bic.w r2, r2, #1
|
|
8002908: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->CR1;
|
|
800290a: 687b ldr r3, [r7, #4]
|
|
800290c: 681b ldr r3, [r3, #0]
|
|
800290e: 681b ldr r3, [r3, #0]
|
|
8002910: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2Cx DNF bits [11:8] */
|
|
tmpreg &= ~(I2C_CR1_DNF);
|
|
8002912: 68fb ldr r3, [r7, #12]
|
|
8002914: f423 6370 bic.w r3, r3, #3840 @ 0xf00
|
|
8002918: 60fb str r3, [r7, #12]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter << 8U;
|
|
800291a: 683b ldr r3, [r7, #0]
|
|
800291c: 021b lsls r3, r3, #8
|
|
800291e: 68fa ldr r2, [r7, #12]
|
|
8002920: 4313 orrs r3, r2
|
|
8002922: 60fb str r3, [r7, #12]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->CR1 = tmpreg;
|
|
8002924: 687b ldr r3, [r7, #4]
|
|
8002926: 681b ldr r3, [r3, #0]
|
|
8002928: 68fa ldr r2, [r7, #12]
|
|
800292a: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
800292c: 687b ldr r3, [r7, #4]
|
|
800292e: 681b ldr r3, [r3, #0]
|
|
8002930: 681a ldr r2, [r3, #0]
|
|
8002932: 687b ldr r3, [r7, #4]
|
|
8002934: 681b ldr r3, [r3, #0]
|
|
8002936: f042 0201 orr.w r2, r2, #1
|
|
800293a: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800293c: 687b ldr r3, [r7, #4]
|
|
800293e: 2220 movs r2, #32
|
|
8002940: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002944: 687b ldr r3, [r7, #4]
|
|
8002946: 2200 movs r2, #0
|
|
8002948: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
800294c: 2300 movs r3, #0
|
|
800294e: e000 b.n 8002952 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8002950: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8002952: 4618 mov r0, r3
|
|
8002954: 3714 adds r7, #20
|
|
8002956: 46bd mov sp, r7
|
|
8002958: f85d 7b04 ldr.w r7, [sp], #4
|
|
800295c: 4770 bx lr
|
|
...
|
|
|
|
08002960 <HAL_PWREx_GetVoltageRange>:
|
|
* @brief Return Voltage Scaling Range.
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
|
|
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
|
|
*/
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
|
{
|
|
8002960: b480 push {r7}
|
|
8002962: af00 add r7, sp, #0
|
|
else
|
|
{
|
|
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
|
|
}
|
|
#else
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
|
8002964: 4b04 ldr r3, [pc, #16] @ (8002978 <HAL_PWREx_GetVoltageRange+0x18>)
|
|
8002966: 681b ldr r3, [r3, #0]
|
|
8002968: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
#endif
|
|
}
|
|
800296c: 4618 mov r0, r3
|
|
800296e: 46bd mov sp, r7
|
|
8002970: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002974: 4770 bx lr
|
|
8002976: bf00 nop
|
|
8002978: 40007000 .word 0x40007000
|
|
|
|
0800297c <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
800297c: b480 push {r7}
|
|
800297e: b085 sub sp, #20
|
|
8002980: af00 add r7, sp, #0
|
|
8002982: 6078 str r0, [r7, #4]
|
|
}
|
|
|
|
#else
|
|
|
|
/* If Set Range 1 */
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8002984: 687b ldr r3, [r7, #4]
|
|
8002986: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
800298a: d130 bne.n 80029ee <HAL_PWREx_ControlVoltageScaling+0x72>
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
800298c: 4b23 ldr r3, [pc, #140] @ (8002a1c <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
800298e: 681b ldr r3, [r3, #0]
|
|
8002990: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8002994: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8002998: d038 beq.n 8002a0c <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
800299a: 4b20 ldr r3, [pc, #128] @ (8002a1c <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
800299c: 681b ldr r3, [r3, #0]
|
|
800299e: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
80029a2: 4a1e ldr r2, [pc, #120] @ (8002a1c <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80029a4: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
80029a8: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
80029aa: 4b1d ldr r3, [pc, #116] @ (8002a20 <HAL_PWREx_ControlVoltageScaling+0xa4>)
|
|
80029ac: 681b ldr r3, [r3, #0]
|
|
80029ae: 2232 movs r2, #50 @ 0x32
|
|
80029b0: fb02 f303 mul.w r3, r2, r3
|
|
80029b4: 4a1b ldr r2, [pc, #108] @ (8002a24 <HAL_PWREx_ControlVoltageScaling+0xa8>)
|
|
80029b6: fba2 2303 umull r2, r3, r2, r3
|
|
80029ba: 0c9b lsrs r3, r3, #18
|
|
80029bc: 3301 adds r3, #1
|
|
80029be: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
80029c0: e002 b.n 80029c8 <HAL_PWREx_ControlVoltageScaling+0x4c>
|
|
{
|
|
wait_loop_index--;
|
|
80029c2: 68fb ldr r3, [r7, #12]
|
|
80029c4: 3b01 subs r3, #1
|
|
80029c6: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
80029c8: 4b14 ldr r3, [pc, #80] @ (8002a1c <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80029ca: 695b ldr r3, [r3, #20]
|
|
80029cc: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80029d0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80029d4: d102 bne.n 80029dc <HAL_PWREx_ControlVoltageScaling+0x60>
|
|
80029d6: 68fb ldr r3, [r7, #12]
|
|
80029d8: 2b00 cmp r3, #0
|
|
80029da: d1f2 bne.n 80029c2 <HAL_PWREx_ControlVoltageScaling+0x46>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
80029dc: 4b0f ldr r3, [pc, #60] @ (8002a1c <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80029de: 695b ldr r3, [r3, #20]
|
|
80029e0: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80029e4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80029e8: d110 bne.n 8002a0c <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80029ea: 2303 movs r3, #3
|
|
80029ec: e00f b.n 8002a0e <HAL_PWREx_ControlVoltageScaling+0x92>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
80029ee: 4b0b ldr r3, [pc, #44] @ (8002a1c <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80029f0: 681b ldr r3, [r3, #0]
|
|
80029f2: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
80029f6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80029fa: d007 beq.n 8002a0c <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
/* Set Range 2 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
|
80029fc: 4b07 ldr r3, [pc, #28] @ (8002a1c <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80029fe: 681b ldr r3, [r3, #0]
|
|
8002a00: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8002a04: 4a05 ldr r2, [pc, #20] @ (8002a1c <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8002a06: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8002a0a: 6013 str r3, [r2, #0]
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return HAL_OK;
|
|
8002a0c: 2300 movs r3, #0
|
|
}
|
|
8002a0e: 4618 mov r0, r3
|
|
8002a10: 3714 adds r7, #20
|
|
8002a12: 46bd mov sp, r7
|
|
8002a14: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002a18: 4770 bx lr
|
|
8002a1a: bf00 nop
|
|
8002a1c: 40007000 .word 0x40007000
|
|
8002a20: 20000000 .word 0x20000000
|
|
8002a24: 431bde83 .word 0x431bde83
|
|
|
|
08002a28 <HAL_RCC_OscConfig>:
|
|
* @note If HSE failed to start, HSE should be disabled before recalling
|
|
HAL_RCC_OscConfig().
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8002a28: b580 push {r7, lr}
|
|
8002a2a: b088 sub sp, #32
|
|
8002a2c: af00 add r7, sp, #0
|
|
8002a2e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status;
|
|
uint32_t sysclk_source, pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8002a30: 687b ldr r3, [r7, #4]
|
|
8002a32: 2b00 cmp r3, #0
|
|
8002a34: d101 bne.n 8002a3a <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002a36: 2301 movs r3, #1
|
|
8002a38: e3ca b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8002a3a: 4b97 ldr r3, [pc, #604] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002a3c: 689b ldr r3, [r3, #8]
|
|
8002a3e: f003 030c and.w r3, r3, #12
|
|
8002a42: 61bb str r3, [r7, #24]
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8002a44: 4b94 ldr r3, [pc, #592] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002a46: 68db ldr r3, [r3, #12]
|
|
8002a48: f003 0303 and.w r3, r3, #3
|
|
8002a4c: 617b str r3, [r7, #20]
|
|
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
8002a4e: 687b ldr r3, [r7, #4]
|
|
8002a50: 681b ldr r3, [r3, #0]
|
|
8002a52: f003 0310 and.w r3, r3, #16
|
|
8002a56: 2b00 cmp r3, #0
|
|
8002a58: f000 80e4 beq.w 8002c24 <HAL_RCC_OscConfig+0x1fc>
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
8002a5c: 69bb ldr r3, [r7, #24]
|
|
8002a5e: 2b00 cmp r3, #0
|
|
8002a60: d007 beq.n 8002a72 <HAL_RCC_OscConfig+0x4a>
|
|
8002a62: 69bb ldr r3, [r7, #24]
|
|
8002a64: 2b0c cmp r3, #12
|
|
8002a66: f040 808b bne.w 8002b80 <HAL_RCC_OscConfig+0x158>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
|
|
8002a6a: 697b ldr r3, [r7, #20]
|
|
8002a6c: 2b01 cmp r3, #1
|
|
8002a6e: f040 8087 bne.w 8002b80 <HAL_RCC_OscConfig+0x158>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8002a72: 4b89 ldr r3, [pc, #548] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002a74: 681b ldr r3, [r3, #0]
|
|
8002a76: f003 0302 and.w r3, r3, #2
|
|
8002a7a: 2b00 cmp r3, #0
|
|
8002a7c: d005 beq.n 8002a8a <HAL_RCC_OscConfig+0x62>
|
|
8002a7e: 687b ldr r3, [r7, #4]
|
|
8002a80: 699b ldr r3, [r3, #24]
|
|
8002a82: 2b00 cmp r3, #0
|
|
8002a84: d101 bne.n 8002a8a <HAL_RCC_OscConfig+0x62>
|
|
{
|
|
return HAL_ERROR;
|
|
8002a86: 2301 movs r3, #1
|
|
8002a88: e3a2 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
else
|
|
{
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
8002a8a: 687b ldr r3, [r7, #4]
|
|
8002a8c: 6a1a ldr r2, [r3, #32]
|
|
8002a8e: 4b82 ldr r3, [pc, #520] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002a90: 681b ldr r3, [r3, #0]
|
|
8002a92: f003 0308 and.w r3, r3, #8
|
|
8002a96: 2b00 cmp r3, #0
|
|
8002a98: d004 beq.n 8002aa4 <HAL_RCC_OscConfig+0x7c>
|
|
8002a9a: 4b7f ldr r3, [pc, #508] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002a9c: 681b ldr r3, [r3, #0]
|
|
8002a9e: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8002aa2: e005 b.n 8002ab0 <HAL_RCC_OscConfig+0x88>
|
|
8002aa4: 4b7c ldr r3, [pc, #496] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002aa6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002aaa: 091b lsrs r3, r3, #4
|
|
8002aac: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8002ab0: 4293 cmp r3, r2
|
|
8002ab2: d223 bcs.n 8002afc <HAL_RCC_OscConfig+0xd4>
|
|
{
|
|
/* First increase number of wait states update if necessary */
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8002ab4: 687b ldr r3, [r7, #4]
|
|
8002ab6: 6a1b ldr r3, [r3, #32]
|
|
8002ab8: 4618 mov r0, r3
|
|
8002aba: f000 fd55 bl 8003568 <RCC_SetFlashLatencyFromMSIRange>
|
|
8002abe: 4603 mov r3, r0
|
|
8002ac0: 2b00 cmp r3, #0
|
|
8002ac2: d001 beq.n 8002ac8 <HAL_RCC_OscConfig+0xa0>
|
|
{
|
|
return HAL_ERROR;
|
|
8002ac4: 2301 movs r3, #1
|
|
8002ac6: e383 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8002ac8: 4b73 ldr r3, [pc, #460] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002aca: 681b ldr r3, [r3, #0]
|
|
8002acc: 4a72 ldr r2, [pc, #456] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002ace: f043 0308 orr.w r3, r3, #8
|
|
8002ad2: 6013 str r3, [r2, #0]
|
|
8002ad4: 4b70 ldr r3, [pc, #448] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002ad6: 681b ldr r3, [r3, #0]
|
|
8002ad8: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002adc: 687b ldr r3, [r7, #4]
|
|
8002ade: 6a1b ldr r3, [r3, #32]
|
|
8002ae0: 496d ldr r1, [pc, #436] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002ae2: 4313 orrs r3, r2
|
|
8002ae4: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8002ae6: 4b6c ldr r3, [pc, #432] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002ae8: 685b ldr r3, [r3, #4]
|
|
8002aea: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8002aee: 687b ldr r3, [r7, #4]
|
|
8002af0: 69db ldr r3, [r3, #28]
|
|
8002af2: 021b lsls r3, r3, #8
|
|
8002af4: 4968 ldr r1, [pc, #416] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002af6: 4313 orrs r3, r2
|
|
8002af8: 604b str r3, [r1, #4]
|
|
8002afa: e025 b.n 8002b48 <HAL_RCC_OscConfig+0x120>
|
|
}
|
|
else
|
|
{
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8002afc: 4b66 ldr r3, [pc, #408] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002afe: 681b ldr r3, [r3, #0]
|
|
8002b00: 4a65 ldr r2, [pc, #404] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002b02: f043 0308 orr.w r3, r3, #8
|
|
8002b06: 6013 str r3, [r2, #0]
|
|
8002b08: 4b63 ldr r3, [pc, #396] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002b0a: 681b ldr r3, [r3, #0]
|
|
8002b0c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002b10: 687b ldr r3, [r7, #4]
|
|
8002b12: 6a1b ldr r3, [r3, #32]
|
|
8002b14: 4960 ldr r1, [pc, #384] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002b16: 4313 orrs r3, r2
|
|
8002b18: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8002b1a: 4b5f ldr r3, [pc, #380] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002b1c: 685b ldr r3, [r3, #4]
|
|
8002b1e: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8002b22: 687b ldr r3, [r7, #4]
|
|
8002b24: 69db ldr r3, [r3, #28]
|
|
8002b26: 021b lsls r3, r3, #8
|
|
8002b28: 495b ldr r1, [pc, #364] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002b2a: 4313 orrs r3, r2
|
|
8002b2c: 604b str r3, [r1, #4]
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
/* Only possible when MSI is the System clock source */
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8002b2e: 69bb ldr r3, [r7, #24]
|
|
8002b30: 2b00 cmp r3, #0
|
|
8002b32: d109 bne.n 8002b48 <HAL_RCC_OscConfig+0x120>
|
|
{
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8002b34: 687b ldr r3, [r7, #4]
|
|
8002b36: 6a1b ldr r3, [r3, #32]
|
|
8002b38: 4618 mov r0, r3
|
|
8002b3a: f000 fd15 bl 8003568 <RCC_SetFlashLatencyFromMSIRange>
|
|
8002b3e: 4603 mov r3, r0
|
|
8002b40: 2b00 cmp r3, #0
|
|
8002b42: d001 beq.n 8002b48 <HAL_RCC_OscConfig+0x120>
|
|
{
|
|
return HAL_ERROR;
|
|
8002b44: 2301 movs r3, #1
|
|
8002b46: e343 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8002b48: f000 fc4a bl 80033e0 <HAL_RCC_GetSysClockFreq>
|
|
8002b4c: 4602 mov r2, r0
|
|
8002b4e: 4b52 ldr r3, [pc, #328] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002b50: 689b ldr r3, [r3, #8]
|
|
8002b52: 091b lsrs r3, r3, #4
|
|
8002b54: f003 030f and.w r3, r3, #15
|
|
8002b58: 4950 ldr r1, [pc, #320] @ (8002c9c <HAL_RCC_OscConfig+0x274>)
|
|
8002b5a: 5ccb ldrb r3, [r1, r3]
|
|
8002b5c: f003 031f and.w r3, r3, #31
|
|
8002b60: fa22 f303 lsr.w r3, r2, r3
|
|
8002b64: 4a4e ldr r2, [pc, #312] @ (8002ca0 <HAL_RCC_OscConfig+0x278>)
|
|
8002b66: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
8002b68: 4b4e ldr r3, [pc, #312] @ (8002ca4 <HAL_RCC_OscConfig+0x27c>)
|
|
8002b6a: 681b ldr r3, [r3, #0]
|
|
8002b6c: 4618 mov r0, r3
|
|
8002b6e: f7fe fdcf bl 8001710 <HAL_InitTick>
|
|
8002b72: 4603 mov r3, r0
|
|
8002b74: 73fb strb r3, [r7, #15]
|
|
if(status != HAL_OK)
|
|
8002b76: 7bfb ldrb r3, [r7, #15]
|
|
8002b78: 2b00 cmp r3, #0
|
|
8002b7a: d052 beq.n 8002c22 <HAL_RCC_OscConfig+0x1fa>
|
|
{
|
|
return status;
|
|
8002b7c: 7bfb ldrb r3, [r7, #15]
|
|
8002b7e: e327 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the MSI State */
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
8002b80: 687b ldr r3, [r7, #4]
|
|
8002b82: 699b ldr r3, [r3, #24]
|
|
8002b84: 2b00 cmp r3, #0
|
|
8002b86: d032 beq.n 8002bee <HAL_RCC_OscConfig+0x1c6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_ENABLE();
|
|
8002b88: 4b43 ldr r3, [pc, #268] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002b8a: 681b ldr r3, [r3, #0]
|
|
8002b8c: 4a42 ldr r2, [pc, #264] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002b8e: f043 0301 orr.w r3, r3, #1
|
|
8002b92: 6013 str r3, [r2, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8002b94: f7fe fe0c bl 80017b0 <HAL_GetTick>
|
|
8002b98: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8002b9a: e008 b.n 8002bae <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8002b9c: f7fe fe08 bl 80017b0 <HAL_GetTick>
|
|
8002ba0: 4602 mov r2, r0
|
|
8002ba2: 693b ldr r3, [r7, #16]
|
|
8002ba4: 1ad3 subs r3, r2, r3
|
|
8002ba6: 2b02 cmp r3, #2
|
|
8002ba8: d901 bls.n 8002bae <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002baa: 2303 movs r3, #3
|
|
8002bac: e310 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8002bae: 4b3a ldr r3, [pc, #232] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002bb0: 681b ldr r3, [r3, #0]
|
|
8002bb2: f003 0302 and.w r3, r3, #2
|
|
8002bb6: 2b00 cmp r3, #0
|
|
8002bb8: d0f0 beq.n 8002b9c <HAL_RCC_OscConfig+0x174>
|
|
}
|
|
}
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8002bba: 4b37 ldr r3, [pc, #220] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002bbc: 681b ldr r3, [r3, #0]
|
|
8002bbe: 4a36 ldr r2, [pc, #216] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002bc0: f043 0308 orr.w r3, r3, #8
|
|
8002bc4: 6013 str r3, [r2, #0]
|
|
8002bc6: 4b34 ldr r3, [pc, #208] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002bc8: 681b ldr r3, [r3, #0]
|
|
8002bca: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002bce: 687b ldr r3, [r7, #4]
|
|
8002bd0: 6a1b ldr r3, [r3, #32]
|
|
8002bd2: 4931 ldr r1, [pc, #196] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002bd4: 4313 orrs r3, r2
|
|
8002bd6: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8002bd8: 4b2f ldr r3, [pc, #188] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002bda: 685b ldr r3, [r3, #4]
|
|
8002bdc: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8002be0: 687b ldr r3, [r7, #4]
|
|
8002be2: 69db ldr r3, [r3, #28]
|
|
8002be4: 021b lsls r3, r3, #8
|
|
8002be6: 492c ldr r1, [pc, #176] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002be8: 4313 orrs r3, r2
|
|
8002bea: 604b str r3, [r1, #4]
|
|
8002bec: e01a b.n 8002c24 <HAL_RCC_OscConfig+0x1fc>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_DISABLE();
|
|
8002bee: 4b2a ldr r3, [pc, #168] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002bf0: 681b ldr r3, [r3, #0]
|
|
8002bf2: 4a29 ldr r2, [pc, #164] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002bf4: f023 0301 bic.w r3, r3, #1
|
|
8002bf8: 6013 str r3, [r2, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8002bfa: f7fe fdd9 bl 80017b0 <HAL_GetTick>
|
|
8002bfe: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
8002c00: e008 b.n 8002c14 <HAL_RCC_OscConfig+0x1ec>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8002c02: f7fe fdd5 bl 80017b0 <HAL_GetTick>
|
|
8002c06: 4602 mov r2, r0
|
|
8002c08: 693b ldr r3, [r7, #16]
|
|
8002c0a: 1ad3 subs r3, r2, r3
|
|
8002c0c: 2b02 cmp r3, #2
|
|
8002c0e: d901 bls.n 8002c14 <HAL_RCC_OscConfig+0x1ec>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002c10: 2303 movs r3, #3
|
|
8002c12: e2dd b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
8002c14: 4b20 ldr r3, [pc, #128] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002c16: 681b ldr r3, [r3, #0]
|
|
8002c18: f003 0302 and.w r3, r3, #2
|
|
8002c1c: 2b00 cmp r3, #0
|
|
8002c1e: d1f0 bne.n 8002c02 <HAL_RCC_OscConfig+0x1da>
|
|
8002c20: e000 b.n 8002c24 <HAL_RCC_OscConfig+0x1fc>
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8002c22: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8002c24: 687b ldr r3, [r7, #4]
|
|
8002c26: 681b ldr r3, [r3, #0]
|
|
8002c28: f003 0301 and.w r3, r3, #1
|
|
8002c2c: 2b00 cmp r3, #0
|
|
8002c2e: d074 beq.n 8002d1a <HAL_RCC_OscConfig+0x2f2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
|
|
8002c30: 69bb ldr r3, [r7, #24]
|
|
8002c32: 2b08 cmp r3, #8
|
|
8002c34: d005 beq.n 8002c42 <HAL_RCC_OscConfig+0x21a>
|
|
8002c36: 69bb ldr r3, [r7, #24]
|
|
8002c38: 2b0c cmp r3, #12
|
|
8002c3a: d10e bne.n 8002c5a <HAL_RCC_OscConfig+0x232>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
8002c3c: 697b ldr r3, [r7, #20]
|
|
8002c3e: 2b03 cmp r3, #3
|
|
8002c40: d10b bne.n 8002c5a <HAL_RCC_OscConfig+0x232>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8002c42: 4b15 ldr r3, [pc, #84] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002c44: 681b ldr r3, [r3, #0]
|
|
8002c46: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002c4a: 2b00 cmp r3, #0
|
|
8002c4c: d064 beq.n 8002d18 <HAL_RCC_OscConfig+0x2f0>
|
|
8002c4e: 687b ldr r3, [r7, #4]
|
|
8002c50: 685b ldr r3, [r3, #4]
|
|
8002c52: 2b00 cmp r3, #0
|
|
8002c54: d160 bne.n 8002d18 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_ERROR;
|
|
8002c56: 2301 movs r3, #1
|
|
8002c58: e2ba b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8002c5a: 687b ldr r3, [r7, #4]
|
|
8002c5c: 685b ldr r3, [r3, #4]
|
|
8002c5e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8002c62: d106 bne.n 8002c72 <HAL_RCC_OscConfig+0x24a>
|
|
8002c64: 4b0c ldr r3, [pc, #48] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002c66: 681b ldr r3, [r3, #0]
|
|
8002c68: 4a0b ldr r2, [pc, #44] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002c6a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8002c6e: 6013 str r3, [r2, #0]
|
|
8002c70: e026 b.n 8002cc0 <HAL_RCC_OscConfig+0x298>
|
|
8002c72: 687b ldr r3, [r7, #4]
|
|
8002c74: 685b ldr r3, [r3, #4]
|
|
8002c76: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8002c7a: d115 bne.n 8002ca8 <HAL_RCC_OscConfig+0x280>
|
|
8002c7c: 4b06 ldr r3, [pc, #24] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002c7e: 681b ldr r3, [r3, #0]
|
|
8002c80: 4a05 ldr r2, [pc, #20] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002c82: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8002c86: 6013 str r3, [r2, #0]
|
|
8002c88: 4b03 ldr r3, [pc, #12] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002c8a: 681b ldr r3, [r3, #0]
|
|
8002c8c: 4a02 ldr r2, [pc, #8] @ (8002c98 <HAL_RCC_OscConfig+0x270>)
|
|
8002c8e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8002c92: 6013 str r3, [r2, #0]
|
|
8002c94: e014 b.n 8002cc0 <HAL_RCC_OscConfig+0x298>
|
|
8002c96: bf00 nop
|
|
8002c98: 40021000 .word 0x40021000
|
|
8002c9c: 0800750c .word 0x0800750c
|
|
8002ca0: 20000000 .word 0x20000000
|
|
8002ca4: 20000004 .word 0x20000004
|
|
8002ca8: 4ba0 ldr r3, [pc, #640] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002caa: 681b ldr r3, [r3, #0]
|
|
8002cac: 4a9f ldr r2, [pc, #636] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002cae: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8002cb2: 6013 str r3, [r2, #0]
|
|
8002cb4: 4b9d ldr r3, [pc, #628] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002cb6: 681b ldr r3, [r3, #0]
|
|
8002cb8: 4a9c ldr r2, [pc, #624] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002cba: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8002cbe: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8002cc0: 687b ldr r3, [r7, #4]
|
|
8002cc2: 685b ldr r3, [r3, #4]
|
|
8002cc4: 2b00 cmp r3, #0
|
|
8002cc6: d013 beq.n 8002cf0 <HAL_RCC_OscConfig+0x2c8>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002cc8: f7fe fd72 bl 80017b0 <HAL_GetTick>
|
|
8002ccc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8002cce: e008 b.n 8002ce2 <HAL_RCC_OscConfig+0x2ba>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8002cd0: f7fe fd6e bl 80017b0 <HAL_GetTick>
|
|
8002cd4: 4602 mov r2, r0
|
|
8002cd6: 693b ldr r3, [r7, #16]
|
|
8002cd8: 1ad3 subs r3, r2, r3
|
|
8002cda: 2b64 cmp r3, #100 @ 0x64
|
|
8002cdc: d901 bls.n 8002ce2 <HAL_RCC_OscConfig+0x2ba>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002cde: 2303 movs r3, #3
|
|
8002ce0: e276 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8002ce2: 4b92 ldr r3, [pc, #584] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002ce4: 681b ldr r3, [r3, #0]
|
|
8002ce6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002cea: 2b00 cmp r3, #0
|
|
8002cec: d0f0 beq.n 8002cd0 <HAL_RCC_OscConfig+0x2a8>
|
|
8002cee: e014 b.n 8002d1a <HAL_RCC_OscConfig+0x2f2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002cf0: f7fe fd5e bl 80017b0 <HAL_GetTick>
|
|
8002cf4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8002cf6: e008 b.n 8002d0a <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8002cf8: f7fe fd5a bl 80017b0 <HAL_GetTick>
|
|
8002cfc: 4602 mov r2, r0
|
|
8002cfe: 693b ldr r3, [r7, #16]
|
|
8002d00: 1ad3 subs r3, r2, r3
|
|
8002d02: 2b64 cmp r3, #100 @ 0x64
|
|
8002d04: d901 bls.n 8002d0a <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002d06: 2303 movs r3, #3
|
|
8002d08: e262 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8002d0a: 4b88 ldr r3, [pc, #544] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002d0c: 681b ldr r3, [r3, #0]
|
|
8002d0e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002d12: 2b00 cmp r3, #0
|
|
8002d14: d1f0 bne.n 8002cf8 <HAL_RCC_OscConfig+0x2d0>
|
|
8002d16: e000 b.n 8002d1a <HAL_RCC_OscConfig+0x2f2>
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8002d18: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8002d1a: 687b ldr r3, [r7, #4]
|
|
8002d1c: 681b ldr r3, [r3, #0]
|
|
8002d1e: f003 0302 and.w r3, r3, #2
|
|
8002d22: 2b00 cmp r3, #0
|
|
8002d24: d060 beq.n 8002de8 <HAL_RCC_OscConfig+0x3c0>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
|
|
8002d26: 69bb ldr r3, [r7, #24]
|
|
8002d28: 2b04 cmp r3, #4
|
|
8002d2a: d005 beq.n 8002d38 <HAL_RCC_OscConfig+0x310>
|
|
8002d2c: 69bb ldr r3, [r7, #24]
|
|
8002d2e: 2b0c cmp r3, #12
|
|
8002d30: d119 bne.n 8002d66 <HAL_RCC_OscConfig+0x33e>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
8002d32: 697b ldr r3, [r7, #20]
|
|
8002d34: 2b02 cmp r3, #2
|
|
8002d36: d116 bne.n 8002d66 <HAL_RCC_OscConfig+0x33e>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8002d38: 4b7c ldr r3, [pc, #496] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002d3a: 681b ldr r3, [r3, #0]
|
|
8002d3c: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002d40: 2b00 cmp r3, #0
|
|
8002d42: d005 beq.n 8002d50 <HAL_RCC_OscConfig+0x328>
|
|
8002d44: 687b ldr r3, [r7, #4]
|
|
8002d46: 68db ldr r3, [r3, #12]
|
|
8002d48: 2b00 cmp r3, #0
|
|
8002d4a: d101 bne.n 8002d50 <HAL_RCC_OscConfig+0x328>
|
|
{
|
|
return HAL_ERROR;
|
|
8002d4c: 2301 movs r3, #1
|
|
8002d4e: e23f b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8002d50: 4b76 ldr r3, [pc, #472] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002d52: 685b ldr r3, [r3, #4]
|
|
8002d54: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
|
|
8002d58: 687b ldr r3, [r7, #4]
|
|
8002d5a: 691b ldr r3, [r3, #16]
|
|
8002d5c: 061b lsls r3, r3, #24
|
|
8002d5e: 4973 ldr r1, [pc, #460] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002d60: 4313 orrs r3, r2
|
|
8002d62: 604b str r3, [r1, #4]
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8002d64: e040 b.n 8002de8 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8002d66: 687b ldr r3, [r7, #4]
|
|
8002d68: 68db ldr r3, [r3, #12]
|
|
8002d6a: 2b00 cmp r3, #0
|
|
8002d6c: d023 beq.n 8002db6 <HAL_RCC_OscConfig+0x38e>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8002d6e: 4b6f ldr r3, [pc, #444] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002d70: 681b ldr r3, [r3, #0]
|
|
8002d72: 4a6e ldr r2, [pc, #440] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002d74: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8002d78: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002d7a: f7fe fd19 bl 80017b0 <HAL_GetTick>
|
|
8002d7e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8002d80: e008 b.n 8002d94 <HAL_RCC_OscConfig+0x36c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8002d82: f7fe fd15 bl 80017b0 <HAL_GetTick>
|
|
8002d86: 4602 mov r2, r0
|
|
8002d88: 693b ldr r3, [r7, #16]
|
|
8002d8a: 1ad3 subs r3, r2, r3
|
|
8002d8c: 2b02 cmp r3, #2
|
|
8002d8e: d901 bls.n 8002d94 <HAL_RCC_OscConfig+0x36c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002d90: 2303 movs r3, #3
|
|
8002d92: e21d b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8002d94: 4b65 ldr r3, [pc, #404] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002d96: 681b ldr r3, [r3, #0]
|
|
8002d98: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002d9c: 2b00 cmp r3, #0
|
|
8002d9e: d0f0 beq.n 8002d82 <HAL_RCC_OscConfig+0x35a>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8002da0: 4b62 ldr r3, [pc, #392] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002da2: 685b ldr r3, [r3, #4]
|
|
8002da4: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
|
|
8002da8: 687b ldr r3, [r7, #4]
|
|
8002daa: 691b ldr r3, [r3, #16]
|
|
8002dac: 061b lsls r3, r3, #24
|
|
8002dae: 495f ldr r1, [pc, #380] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002db0: 4313 orrs r3, r2
|
|
8002db2: 604b str r3, [r1, #4]
|
|
8002db4: e018 b.n 8002de8 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8002db6: 4b5d ldr r3, [pc, #372] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002db8: 681b ldr r3, [r3, #0]
|
|
8002dba: 4a5c ldr r2, [pc, #368] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002dbc: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8002dc0: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002dc2: f7fe fcf5 bl 80017b0 <HAL_GetTick>
|
|
8002dc6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8002dc8: e008 b.n 8002ddc <HAL_RCC_OscConfig+0x3b4>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8002dca: f7fe fcf1 bl 80017b0 <HAL_GetTick>
|
|
8002dce: 4602 mov r2, r0
|
|
8002dd0: 693b ldr r3, [r7, #16]
|
|
8002dd2: 1ad3 subs r3, r2, r3
|
|
8002dd4: 2b02 cmp r3, #2
|
|
8002dd6: d901 bls.n 8002ddc <HAL_RCC_OscConfig+0x3b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002dd8: 2303 movs r3, #3
|
|
8002dda: e1f9 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8002ddc: 4b53 ldr r3, [pc, #332] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002dde: 681b ldr r3, [r3, #0]
|
|
8002de0: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002de4: 2b00 cmp r3, #0
|
|
8002de6: d1f0 bne.n 8002dca <HAL_RCC_OscConfig+0x3a2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8002de8: 687b ldr r3, [r7, #4]
|
|
8002dea: 681b ldr r3, [r3, #0]
|
|
8002dec: f003 0308 and.w r3, r3, #8
|
|
8002df0: 2b00 cmp r3, #0
|
|
8002df2: d03c beq.n 8002e6e <HAL_RCC_OscConfig+0x446>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8002df4: 687b ldr r3, [r7, #4]
|
|
8002df6: 695b ldr r3, [r3, #20]
|
|
8002df8: 2b00 cmp r3, #0
|
|
8002dfa: d01c beq.n 8002e36 <HAL_RCC_OscConfig+0x40e>
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
|
|
}
|
|
#endif /* RCC_CSR_LSIPREDIV */
|
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8002dfc: 4b4b ldr r3, [pc, #300] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002dfe: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002e02: 4a4a ldr r2, [pc, #296] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e04: f043 0301 orr.w r3, r3, #1
|
|
8002e08: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002e0c: f7fe fcd0 bl 80017b0 <HAL_GetTick>
|
|
8002e10: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8002e12: e008 b.n 8002e26 <HAL_RCC_OscConfig+0x3fe>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8002e14: f7fe fccc bl 80017b0 <HAL_GetTick>
|
|
8002e18: 4602 mov r2, r0
|
|
8002e1a: 693b ldr r3, [r7, #16]
|
|
8002e1c: 1ad3 subs r3, r2, r3
|
|
8002e1e: 2b02 cmp r3, #2
|
|
8002e20: d901 bls.n 8002e26 <HAL_RCC_OscConfig+0x3fe>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002e22: 2303 movs r3, #3
|
|
8002e24: e1d4 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8002e26: 4b41 ldr r3, [pc, #260] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e28: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002e2c: f003 0302 and.w r3, r3, #2
|
|
8002e30: 2b00 cmp r3, #0
|
|
8002e32: d0ef beq.n 8002e14 <HAL_RCC_OscConfig+0x3ec>
|
|
8002e34: e01b b.n 8002e6e <HAL_RCC_OscConfig+0x446>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8002e36: 4b3d ldr r3, [pc, #244] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e38: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002e3c: 4a3b ldr r2, [pc, #236] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e3e: f023 0301 bic.w r3, r3, #1
|
|
8002e42: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002e46: f7fe fcb3 bl 80017b0 <HAL_GetTick>
|
|
8002e4a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8002e4c: e008 b.n 8002e60 <HAL_RCC_OscConfig+0x438>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8002e4e: f7fe fcaf bl 80017b0 <HAL_GetTick>
|
|
8002e52: 4602 mov r2, r0
|
|
8002e54: 693b ldr r3, [r7, #16]
|
|
8002e56: 1ad3 subs r3, r2, r3
|
|
8002e58: 2b02 cmp r3, #2
|
|
8002e5a: d901 bls.n 8002e60 <HAL_RCC_OscConfig+0x438>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002e5c: 2303 movs r3, #3
|
|
8002e5e: e1b7 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8002e60: 4b32 ldr r3, [pc, #200] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e62: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002e66: f003 0302 and.w r3, r3, #2
|
|
8002e6a: 2b00 cmp r3, #0
|
|
8002e6c: d1ef bne.n 8002e4e <HAL_RCC_OscConfig+0x426>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8002e6e: 687b ldr r3, [r7, #4]
|
|
8002e70: 681b ldr r3, [r3, #0]
|
|
8002e72: f003 0304 and.w r3, r3, #4
|
|
8002e76: 2b00 cmp r3, #0
|
|
8002e78: f000 80a6 beq.w 8002fc8 <HAL_RCC_OscConfig+0x5a0>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8002e7c: 2300 movs r3, #0
|
|
8002e7e: 77fb strb r3, [r7, #31]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
|
|
8002e80: 4b2a ldr r3, [pc, #168] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e82: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002e84: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8002e88: 2b00 cmp r3, #0
|
|
8002e8a: d10d bne.n 8002ea8 <HAL_RCC_OscConfig+0x480>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8002e8c: 4b27 ldr r3, [pc, #156] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e8e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002e90: 4a26 ldr r2, [pc, #152] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e92: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8002e96: 6593 str r3, [r2, #88] @ 0x58
|
|
8002e98: 4b24 ldr r3, [pc, #144] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002e9a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002e9c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8002ea0: 60bb str r3, [r7, #8]
|
|
8002ea2: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8002ea4: 2301 movs r3, #1
|
|
8002ea6: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8002ea8: 4b21 ldr r3, [pc, #132] @ (8002f30 <HAL_RCC_OscConfig+0x508>)
|
|
8002eaa: 681b ldr r3, [r3, #0]
|
|
8002eac: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002eb0: 2b00 cmp r3, #0
|
|
8002eb2: d118 bne.n 8002ee6 <HAL_RCC_OscConfig+0x4be>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8002eb4: 4b1e ldr r3, [pc, #120] @ (8002f30 <HAL_RCC_OscConfig+0x508>)
|
|
8002eb6: 681b ldr r3, [r3, #0]
|
|
8002eb8: 4a1d ldr r2, [pc, #116] @ (8002f30 <HAL_RCC_OscConfig+0x508>)
|
|
8002eba: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8002ebe: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8002ec0: f7fe fc76 bl 80017b0 <HAL_GetTick>
|
|
8002ec4: 6138 str r0, [r7, #16]
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8002ec6: e008 b.n 8002eda <HAL_RCC_OscConfig+0x4b2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8002ec8: f7fe fc72 bl 80017b0 <HAL_GetTick>
|
|
8002ecc: 4602 mov r2, r0
|
|
8002ece: 693b ldr r3, [r7, #16]
|
|
8002ed0: 1ad3 subs r3, r2, r3
|
|
8002ed2: 2b02 cmp r3, #2
|
|
8002ed4: d901 bls.n 8002eda <HAL_RCC_OscConfig+0x4b2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002ed6: 2303 movs r3, #3
|
|
8002ed8: e17a b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8002eda: 4b15 ldr r3, [pc, #84] @ (8002f30 <HAL_RCC_OscConfig+0x508>)
|
|
8002edc: 681b ldr r3, [r3, #0]
|
|
8002ede: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002ee2: 2b00 cmp r3, #0
|
|
8002ee4: d0f0 beq.n 8002ec8 <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
}
|
|
#else
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8002ee6: 687b ldr r3, [r7, #4]
|
|
8002ee8: 689b ldr r3, [r3, #8]
|
|
8002eea: 2b01 cmp r3, #1
|
|
8002eec: d108 bne.n 8002f00 <HAL_RCC_OscConfig+0x4d8>
|
|
8002eee: 4b0f ldr r3, [pc, #60] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002ef0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002ef4: 4a0d ldr r2, [pc, #52] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002ef6: f043 0301 orr.w r3, r3, #1
|
|
8002efa: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8002efe: e029 b.n 8002f54 <HAL_RCC_OscConfig+0x52c>
|
|
8002f00: 687b ldr r3, [r7, #4]
|
|
8002f02: 689b ldr r3, [r3, #8]
|
|
8002f04: 2b05 cmp r3, #5
|
|
8002f06: d115 bne.n 8002f34 <HAL_RCC_OscConfig+0x50c>
|
|
8002f08: 4b08 ldr r3, [pc, #32] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002f0a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002f0e: 4a07 ldr r2, [pc, #28] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002f10: f043 0304 orr.w r3, r3, #4
|
|
8002f14: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8002f18: 4b04 ldr r3, [pc, #16] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002f1a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002f1e: 4a03 ldr r2, [pc, #12] @ (8002f2c <HAL_RCC_OscConfig+0x504>)
|
|
8002f20: f043 0301 orr.w r3, r3, #1
|
|
8002f24: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8002f28: e014 b.n 8002f54 <HAL_RCC_OscConfig+0x52c>
|
|
8002f2a: bf00 nop
|
|
8002f2c: 40021000 .word 0x40021000
|
|
8002f30: 40007000 .word 0x40007000
|
|
8002f34: 4b9c ldr r3, [pc, #624] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002f36: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002f3a: 4a9b ldr r2, [pc, #620] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002f3c: f023 0301 bic.w r3, r3, #1
|
|
8002f40: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8002f44: 4b98 ldr r3, [pc, #608] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002f46: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002f4a: 4a97 ldr r2, [pc, #604] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002f4c: f023 0304 bic.w r3, r3, #4
|
|
8002f50: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8002f54: 687b ldr r3, [r7, #4]
|
|
8002f56: 689b ldr r3, [r3, #8]
|
|
8002f58: 2b00 cmp r3, #0
|
|
8002f5a: d016 beq.n 8002f8a <HAL_RCC_OscConfig+0x562>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002f5c: f7fe fc28 bl 80017b0 <HAL_GetTick>
|
|
8002f60: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8002f62: e00a b.n 8002f7a <HAL_RCC_OscConfig+0x552>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8002f64: f7fe fc24 bl 80017b0 <HAL_GetTick>
|
|
8002f68: 4602 mov r2, r0
|
|
8002f6a: 693b ldr r3, [r7, #16]
|
|
8002f6c: 1ad3 subs r3, r2, r3
|
|
8002f6e: f241 3288 movw r2, #5000 @ 0x1388
|
|
8002f72: 4293 cmp r3, r2
|
|
8002f74: d901 bls.n 8002f7a <HAL_RCC_OscConfig+0x552>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002f76: 2303 movs r3, #3
|
|
8002f78: e12a b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8002f7a: 4b8b ldr r3, [pc, #556] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002f7c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002f80: f003 0302 and.w r3, r3, #2
|
|
8002f84: 2b00 cmp r3, #0
|
|
8002f86: d0ed beq.n 8002f64 <HAL_RCC_OscConfig+0x53c>
|
|
8002f88: e015 b.n 8002fb6 <HAL_RCC_OscConfig+0x58e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002f8a: f7fe fc11 bl 80017b0 <HAL_GetTick>
|
|
8002f8e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8002f90: e00a b.n 8002fa8 <HAL_RCC_OscConfig+0x580>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8002f92: f7fe fc0d bl 80017b0 <HAL_GetTick>
|
|
8002f96: 4602 mov r2, r0
|
|
8002f98: 693b ldr r3, [r7, #16]
|
|
8002f9a: 1ad3 subs r3, r2, r3
|
|
8002f9c: f241 3288 movw r2, #5000 @ 0x1388
|
|
8002fa0: 4293 cmp r3, r2
|
|
8002fa2: d901 bls.n 8002fa8 <HAL_RCC_OscConfig+0x580>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002fa4: 2303 movs r3, #3
|
|
8002fa6: e113 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8002fa8: 4b7f ldr r3, [pc, #508] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002faa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002fae: f003 0302 and.w r3, r3, #2
|
|
8002fb2: 2b00 cmp r3, #0
|
|
8002fb4: d1ed bne.n 8002f92 <HAL_RCC_OscConfig+0x56a>
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
8002fb6: 7ffb ldrb r3, [r7, #31]
|
|
8002fb8: 2b01 cmp r3, #1
|
|
8002fba: d105 bne.n 8002fc8 <HAL_RCC_OscConfig+0x5a0>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8002fbc: 4b7a ldr r3, [pc, #488] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002fbe: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002fc0: 4a79 ldr r2, [pc, #484] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002fc2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8002fc6: 6593 str r3, [r2, #88] @ 0x58
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
8002fc8: 687b ldr r3, [r7, #4]
|
|
8002fca: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002fcc: 2b00 cmp r3, #0
|
|
8002fce: f000 80fe beq.w 80031ce <HAL_RCC_OscConfig+0x7a6>
|
|
{
|
|
/* PLL On ? */
|
|
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8002fd2: 687b ldr r3, [r7, #4]
|
|
8002fd4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002fd6: 2b02 cmp r3, #2
|
|
8002fd8: f040 80d0 bne.w 800317c <HAL_RCC_OscConfig+0x754>
|
|
#endif /* RCC_PLLP_SUPPORT */
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Do nothing if PLL configuration is the unchanged */
|
|
pll_config = RCC->PLLCFGR;
|
|
8002fdc: 4b72 ldr r3, [pc, #456] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8002fde: 68db ldr r3, [r3, #12]
|
|
8002fe0: 617b str r3, [r7, #20]
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8002fe2: 697b ldr r3, [r7, #20]
|
|
8002fe4: f003 0203 and.w r2, r3, #3
|
|
8002fe8: 687b ldr r3, [r7, #4]
|
|
8002fea: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002fec: 429a cmp r2, r3
|
|
8002fee: d130 bne.n 8003052 <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8002ff0: 697b ldr r3, [r7, #20]
|
|
8002ff2: f003 0270 and.w r2, r3, #112 @ 0x70
|
|
8002ff6: 687b ldr r3, [r7, #4]
|
|
8002ff8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8002ffa: 3b01 subs r3, #1
|
|
8002ffc: 011b lsls r3, r3, #4
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8002ffe: 429a cmp r2, r3
|
|
8003000: d127 bne.n 8003052 <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8003002: 697b ldr r3, [r7, #20]
|
|
8003004: f403 42fe and.w r2, r3, #32512 @ 0x7f00
|
|
8003008: 687b ldr r3, [r7, #4]
|
|
800300a: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800300c: 021b lsls r3, r3, #8
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
800300e: 429a cmp r2, r3
|
|
8003010: d11f bne.n 8003052 <HAL_RCC_OscConfig+0x62a>
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
#else
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
8003012: 697b ldr r3, [r7, #20]
|
|
8003014: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003018: 687a ldr r2, [r7, #4]
|
|
800301a: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
800301c: 2a07 cmp r2, #7
|
|
800301e: bf14 ite ne
|
|
8003020: 2201 movne r2, #1
|
|
8003022: 2200 moveq r2, #0
|
|
8003024: b2d2 uxtb r2, r2
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8003026: 4293 cmp r3, r2
|
|
8003028: d113 bne.n 8003052 <HAL_RCC_OscConfig+0x62a>
|
|
#endif
|
|
#endif
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
800302a: 697b ldr r3, [r7, #20]
|
|
800302c: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
|
|
8003030: 687b ldr r3, [r7, #4]
|
|
8003032: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8003034: 085b lsrs r3, r3, #1
|
|
8003036: 3b01 subs r3, #1
|
|
8003038: 055b lsls r3, r3, #21
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
800303a: 429a cmp r2, r3
|
|
800303c: d109 bne.n 8003052 <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
|
800303e: 697b ldr r3, [r7, #20]
|
|
8003040: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
|
|
8003044: 687b ldr r3, [r7, #4]
|
|
8003046: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003048: 085b lsrs r3, r3, #1
|
|
800304a: 3b01 subs r3, #1
|
|
800304c: 065b lsls r3, r3, #25
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
800304e: 429a cmp r2, r3
|
|
8003050: d06e beq.n 8003130 <HAL_RCC_OscConfig+0x708>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
8003052: 69bb ldr r3, [r7, #24]
|
|
8003054: 2b0c cmp r3, #12
|
|
8003056: d069 beq.n 800312c <HAL_RCC_OscConfig+0x704>
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
|
|
/* Check if main PLL can be updated */
|
|
/* Not possible if the source is shared by other enabled PLLSAIx */
|
|
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
|
|
8003058: 4b53 ldr r3, [pc, #332] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
800305a: 681b ldr r3, [r3, #0]
|
|
800305c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8003060: 2b00 cmp r3, #0
|
|
8003062: d105 bne.n 8003070 <HAL_RCC_OscConfig+0x648>
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
|
|
8003064: 4b50 ldr r3, [pc, #320] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8003066: 681b ldr r3, [r3, #0]
|
|
8003068: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800306c: 2b00 cmp r3, #0
|
|
800306e: d001 beq.n 8003074 <HAL_RCC_OscConfig+0x64c>
|
|
#endif
|
|
)
|
|
{
|
|
return HAL_ERROR;
|
|
8003070: 2301 movs r3, #1
|
|
8003072: e0ad b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
else
|
|
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003074: 4b4c ldr r3, [pc, #304] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8003076: 681b ldr r3, [r3, #0]
|
|
8003078: 4a4b ldr r2, [pc, #300] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
800307a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800307e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003080: f7fe fb96 bl 80017b0 <HAL_GetTick>
|
|
8003084: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003086: e008 b.n 800309a <HAL_RCC_OscConfig+0x672>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003088: f7fe fb92 bl 80017b0 <HAL_GetTick>
|
|
800308c: 4602 mov r2, r0
|
|
800308e: 693b ldr r3, [r7, #16]
|
|
8003090: 1ad3 subs r3, r2, r3
|
|
8003092: 2b02 cmp r3, #2
|
|
8003094: d901 bls.n 800309a <HAL_RCC_OscConfig+0x672>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003096: 2303 movs r3, #3
|
|
8003098: e09a b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800309a: 4b43 ldr r3, [pc, #268] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
800309c: 681b ldr r3, [r3, #0]
|
|
800309e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80030a2: 2b00 cmp r3, #0
|
|
80030a4: d1f0 bne.n 8003088 <HAL_RCC_OscConfig+0x660>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
80030a6: 4b40 ldr r3, [pc, #256] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
80030a8: 68da ldr r2, [r3, #12]
|
|
80030aa: 4b40 ldr r3, [pc, #256] @ (80031ac <HAL_RCC_OscConfig+0x784>)
|
|
80030ac: 4013 ands r3, r2
|
|
80030ae: 687a ldr r2, [r7, #4]
|
|
80030b0: 6ad1 ldr r1, [r2, #44] @ 0x2c
|
|
80030b2: 687a ldr r2, [r7, #4]
|
|
80030b4: 6b12 ldr r2, [r2, #48] @ 0x30
|
|
80030b6: 3a01 subs r2, #1
|
|
80030b8: 0112 lsls r2, r2, #4
|
|
80030ba: 4311 orrs r1, r2
|
|
80030bc: 687a ldr r2, [r7, #4]
|
|
80030be: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
80030c0: 0212 lsls r2, r2, #8
|
|
80030c2: 4311 orrs r1, r2
|
|
80030c4: 687a ldr r2, [r7, #4]
|
|
80030c6: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
80030c8: 0852 lsrs r2, r2, #1
|
|
80030ca: 3a01 subs r2, #1
|
|
80030cc: 0552 lsls r2, r2, #21
|
|
80030ce: 4311 orrs r1, r2
|
|
80030d0: 687a ldr r2, [r7, #4]
|
|
80030d2: 6c12 ldr r2, [r2, #64] @ 0x40
|
|
80030d4: 0852 lsrs r2, r2, #1
|
|
80030d6: 3a01 subs r2, #1
|
|
80030d8: 0652 lsls r2, r2, #25
|
|
80030da: 4311 orrs r1, r2
|
|
80030dc: 687a ldr r2, [r7, #4]
|
|
80030de: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
80030e0: 0912 lsrs r2, r2, #4
|
|
80030e2: 0452 lsls r2, r2, #17
|
|
80030e4: 430a orrs r2, r1
|
|
80030e6: 4930 ldr r1, [pc, #192] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
80030e8: 4313 orrs r3, r2
|
|
80030ea: 60cb str r3, [r1, #12]
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
#endif
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80030ec: 4b2e ldr r3, [pc, #184] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
80030ee: 681b ldr r3, [r3, #0]
|
|
80030f0: 4a2d ldr r2, [pc, #180] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
80030f2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
80030f6: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
80030f8: 4b2b ldr r3, [pc, #172] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
80030fa: 68db ldr r3, [r3, #12]
|
|
80030fc: 4a2a ldr r2, [pc, #168] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
80030fe: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003102: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003104: f7fe fb54 bl 80017b0 <HAL_GetTick>
|
|
8003108: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800310a: e008 b.n 800311e <HAL_RCC_OscConfig+0x6f6>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800310c: f7fe fb50 bl 80017b0 <HAL_GetTick>
|
|
8003110: 4602 mov r2, r0
|
|
8003112: 693b ldr r3, [r7, #16]
|
|
8003114: 1ad3 subs r3, r2, r3
|
|
8003116: 2b02 cmp r3, #2
|
|
8003118: d901 bls.n 800311e <HAL_RCC_OscConfig+0x6f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800311a: 2303 movs r3, #3
|
|
800311c: e058 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800311e: 4b22 ldr r3, [pc, #136] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8003120: 681b ldr r3, [r3, #0]
|
|
8003122: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003126: 2b00 cmp r3, #0
|
|
8003128: d0f0 beq.n 800310c <HAL_RCC_OscConfig+0x6e4>
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
800312a: e050 b.n 80031ce <HAL_RCC_OscConfig+0x7a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
800312c: 2301 movs r3, #1
|
|
800312e: e04f b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
else
|
|
{
|
|
/* PLL configuration is unchanged */
|
|
/* Re-enable PLL if it was disabled (ie. low power mode) */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003130: 4b1d ldr r3, [pc, #116] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8003132: 681b ldr r3, [r3, #0]
|
|
8003134: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003138: 2b00 cmp r3, #0
|
|
800313a: d148 bne.n 80031ce <HAL_RCC_OscConfig+0x7a6>
|
|
{
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
800313c: 4b1a ldr r3, [pc, #104] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
800313e: 681b ldr r3, [r3, #0]
|
|
8003140: 4a19 ldr r2, [pc, #100] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8003142: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003146: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
8003148: 4b17 ldr r3, [pc, #92] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
800314a: 68db ldr r3, [r3, #12]
|
|
800314c: 4a16 ldr r2, [pc, #88] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
800314e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003152: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003154: f7fe fb2c bl 80017b0 <HAL_GetTick>
|
|
8003158: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800315a: e008 b.n 800316e <HAL_RCC_OscConfig+0x746>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800315c: f7fe fb28 bl 80017b0 <HAL_GetTick>
|
|
8003160: 4602 mov r2, r0
|
|
8003162: 693b ldr r3, [r7, #16]
|
|
8003164: 1ad3 subs r3, r2, r3
|
|
8003166: 2b02 cmp r3, #2
|
|
8003168: d901 bls.n 800316e <HAL_RCC_OscConfig+0x746>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800316a: 2303 movs r3, #3
|
|
800316c: e030 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800316e: 4b0e ldr r3, [pc, #56] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8003170: 681b ldr r3, [r3, #0]
|
|
8003172: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003176: 2b00 cmp r3, #0
|
|
8003178: d0f0 beq.n 800315c <HAL_RCC_OscConfig+0x734>
|
|
800317a: e028 b.n 80031ce <HAL_RCC_OscConfig+0x7a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check that PLL is not used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
800317c: 69bb ldr r3, [r7, #24]
|
|
800317e: 2b0c cmp r3, #12
|
|
8003180: d023 beq.n 80031ca <HAL_RCC_OscConfig+0x7a2>
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003182: 4b09 ldr r3, [pc, #36] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8003184: 681b ldr r3, [r3, #0]
|
|
8003186: 4a08 ldr r2, [pc, #32] @ (80031a8 <HAL_RCC_OscConfig+0x780>)
|
|
8003188: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800318c: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800318e: f7fe fb0f bl 80017b0 <HAL_GetTick>
|
|
8003192: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003194: e00c b.n 80031b0 <HAL_RCC_OscConfig+0x788>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003196: f7fe fb0b bl 80017b0 <HAL_GetTick>
|
|
800319a: 4602 mov r2, r0
|
|
800319c: 693b ldr r3, [r7, #16]
|
|
800319e: 1ad3 subs r3, r2, r3
|
|
80031a0: 2b02 cmp r3, #2
|
|
80031a2: d905 bls.n 80031b0 <HAL_RCC_OscConfig+0x788>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80031a4: 2303 movs r3, #3
|
|
80031a6: e013 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
80031a8: 40021000 .word 0x40021000
|
|
80031ac: f99d808c .word 0xf99d808c
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
80031b0: 4b09 ldr r3, [pc, #36] @ (80031d8 <HAL_RCC_OscConfig+0x7b0>)
|
|
80031b2: 681b ldr r3, [r3, #0]
|
|
80031b4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80031b8: 2b00 cmp r3, #0
|
|
80031ba: d1ec bne.n 8003196 <HAL_RCC_OscConfig+0x76e>
|
|
}
|
|
}
|
|
/* Unselect main PLL clock source and disable main PLL outputs to save power */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
|
|
80031bc: 4b06 ldr r3, [pc, #24] @ (80031d8 <HAL_RCC_OscConfig+0x7b0>)
|
|
80031be: 68da ldr r2, [r3, #12]
|
|
80031c0: 4905 ldr r1, [pc, #20] @ (80031d8 <HAL_RCC_OscConfig+0x7b0>)
|
|
80031c2: 4b06 ldr r3, [pc, #24] @ (80031dc <HAL_RCC_OscConfig+0x7b4>)
|
|
80031c4: 4013 ands r3, r2
|
|
80031c6: 60cb str r3, [r1, #12]
|
|
80031c8: e001 b.n 80031ce <HAL_RCC_OscConfig+0x7a6>
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
80031ca: 2301 movs r3, #1
|
|
80031cc: e000 b.n 80031d0 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80031ce: 2300 movs r3, #0
|
|
}
|
|
80031d0: 4618 mov r0, r3
|
|
80031d2: 3720 adds r7, #32
|
|
80031d4: 46bd mov sp, r7
|
|
80031d6: bd80 pop {r7, pc}
|
|
80031d8: 40021000 .word 0x40021000
|
|
80031dc: feeefffc .word 0xfeeefffc
|
|
|
|
080031e0 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
80031e0: b580 push {r7, lr}
|
|
80031e2: b084 sub sp, #16
|
|
80031e4: af00 add r7, sp, #0
|
|
80031e6: 6078 str r0, [r7, #4]
|
|
80031e8: 6039 str r1, [r7, #0]
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
|
#endif
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
80031ea: 687b ldr r3, [r7, #4]
|
|
80031ec: 2b00 cmp r3, #0
|
|
80031ee: d101 bne.n 80031f4 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80031f0: 2301 movs r3, #1
|
|
80031f2: e0e7 b.n 80033c4 <HAL_RCC_ClockConfig+0x1e4>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80031f4: 4b75 ldr r3, [pc, #468] @ (80033cc <HAL_RCC_ClockConfig+0x1ec>)
|
|
80031f6: 681b ldr r3, [r3, #0]
|
|
80031f8: f003 0307 and.w r3, r3, #7
|
|
80031fc: 683a ldr r2, [r7, #0]
|
|
80031fe: 429a cmp r2, r3
|
|
8003200: d910 bls.n 8003224 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003202: 4b72 ldr r3, [pc, #456] @ (80033cc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8003204: 681b ldr r3, [r3, #0]
|
|
8003206: f023 0207 bic.w r2, r3, #7
|
|
800320a: 4970 ldr r1, [pc, #448] @ (80033cc <HAL_RCC_ClockConfig+0x1ec>)
|
|
800320c: 683b ldr r3, [r7, #0]
|
|
800320e: 4313 orrs r3, r2
|
|
8003210: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8003212: 4b6e ldr r3, [pc, #440] @ (80033cc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8003214: 681b ldr r3, [r3, #0]
|
|
8003216: f003 0307 and.w r3, r3, #7
|
|
800321a: 683a ldr r2, [r7, #0]
|
|
800321c: 429a cmp r2, r3
|
|
800321e: d001 beq.n 8003224 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8003220: 2301 movs r3, #1
|
|
8003222: e0cf b.n 80033c4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
|
|
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
|
|
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8003224: 687b ldr r3, [r7, #4]
|
|
8003226: 681b ldr r3, [r3, #0]
|
|
8003228: f003 0302 and.w r3, r3, #2
|
|
800322c: 2b00 cmp r3, #0
|
|
800322e: d010 beq.n 8003252 <HAL_RCC_ClockConfig+0x72>
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
|
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
8003230: 687b ldr r3, [r7, #4]
|
|
8003232: 689a ldr r2, [r3, #8]
|
|
8003234: 4b66 ldr r3, [pc, #408] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003236: 689b ldr r3, [r3, #8]
|
|
8003238: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
800323c: 429a cmp r2, r3
|
|
800323e: d908 bls.n 8003252 <HAL_RCC_ClockConfig+0x72>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8003240: 4b63 ldr r3, [pc, #396] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003242: 689b ldr r3, [r3, #8]
|
|
8003244: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8003248: 687b ldr r3, [r7, #4]
|
|
800324a: 689b ldr r3, [r3, #8]
|
|
800324c: 4960 ldr r1, [pc, #384] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800324e: 4313 orrs r3, r2
|
|
8003250: 608b str r3, [r1, #8]
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8003252: 687b ldr r3, [r7, #4]
|
|
8003254: 681b ldr r3, [r3, #0]
|
|
8003256: f003 0301 and.w r3, r3, #1
|
|
800325a: 2b00 cmp r3, #0
|
|
800325c: d04c beq.n 80032f8 <HAL_RCC_ClockConfig+0x118>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
800325e: 687b ldr r3, [r7, #4]
|
|
8003260: 685b ldr r3, [r3, #4]
|
|
8003262: 2b03 cmp r3, #3
|
|
8003264: d107 bne.n 8003276 <HAL_RCC_ClockConfig+0x96>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003266: 4b5a ldr r3, [pc, #360] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003268: 681b ldr r3, [r3, #0]
|
|
800326a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800326e: 2b00 cmp r3, #0
|
|
8003270: d121 bne.n 80032b6 <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
8003272: 2301 movs r3, #1
|
|
8003274: e0a6 b.n 80033c4 <HAL_RCC_ClockConfig+0x1e4>
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8003276: 687b ldr r3, [r7, #4]
|
|
8003278: 685b ldr r3, [r3, #4]
|
|
800327a: 2b02 cmp r3, #2
|
|
800327c: d107 bne.n 800328e <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
800327e: 4b54 ldr r3, [pc, #336] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003280: 681b ldr r3, [r3, #0]
|
|
8003282: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003286: 2b00 cmp r3, #0
|
|
8003288: d115 bne.n 80032b6 <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
800328a: 2301 movs r3, #1
|
|
800328c: e09a b.n 80033c4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
800328e: 687b ldr r3, [r7, #4]
|
|
8003290: 685b ldr r3, [r3, #4]
|
|
8003292: 2b00 cmp r3, #0
|
|
8003294: d107 bne.n 80032a6 <HAL_RCC_ClockConfig+0xc6>
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8003296: 4b4e ldr r3, [pc, #312] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003298: 681b ldr r3, [r3, #0]
|
|
800329a: f003 0302 and.w r3, r3, #2
|
|
800329e: 2b00 cmp r3, #0
|
|
80032a0: d109 bne.n 80032b6 <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80032a2: 2301 movs r3, #1
|
|
80032a4: e08e b.n 80033c4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
80032a6: 4b4a ldr r3, [pc, #296] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80032a8: 681b ldr r3, [r3, #0]
|
|
80032aa: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80032ae: 2b00 cmp r3, #0
|
|
80032b0: d101 bne.n 80032b6 <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80032b2: 2301 movs r3, #1
|
|
80032b4: e086 b.n 80033c4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
80032b6: 4b46 ldr r3, [pc, #280] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80032b8: 689b ldr r3, [r3, #8]
|
|
80032ba: f023 0203 bic.w r2, r3, #3
|
|
80032be: 687b ldr r3, [r7, #4]
|
|
80032c0: 685b ldr r3, [r3, #4]
|
|
80032c2: 4943 ldr r1, [pc, #268] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80032c4: 4313 orrs r3, r2
|
|
80032c6: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80032c8: f7fe fa72 bl 80017b0 <HAL_GetTick>
|
|
80032cc: 60f8 str r0, [r7, #12]
|
|
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80032ce: e00a b.n 80032e6 <HAL_RCC_ClockConfig+0x106>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80032d0: f7fe fa6e bl 80017b0 <HAL_GetTick>
|
|
80032d4: 4602 mov r2, r0
|
|
80032d6: 68fb ldr r3, [r7, #12]
|
|
80032d8: 1ad3 subs r3, r2, r3
|
|
80032da: f241 3288 movw r2, #5000 @ 0x1388
|
|
80032de: 4293 cmp r3, r2
|
|
80032e0: d901 bls.n 80032e6 <HAL_RCC_ClockConfig+0x106>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80032e2: 2303 movs r3, #3
|
|
80032e4: e06e b.n 80033c4 <HAL_RCC_ClockConfig+0x1e4>
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80032e6: 4b3a ldr r3, [pc, #232] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80032e8: 689b ldr r3, [r3, #8]
|
|
80032ea: f003 020c and.w r2, r3, #12
|
|
80032ee: 687b ldr r3, [r7, #4]
|
|
80032f0: 685b ldr r3, [r3, #4]
|
|
80032f2: 009b lsls r3, r3, #2
|
|
80032f4: 429a cmp r2, r3
|
|
80032f6: d1eb bne.n 80032d0 <HAL_RCC_ClockConfig+0xf0>
|
|
}
|
|
#endif
|
|
|
|
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
|
|
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
80032f8: 687b ldr r3, [r7, #4]
|
|
80032fa: 681b ldr r3, [r3, #0]
|
|
80032fc: f003 0302 and.w r3, r3, #2
|
|
8003300: 2b00 cmp r3, #0
|
|
8003302: d010 beq.n 8003326 <HAL_RCC_ClockConfig+0x146>
|
|
{
|
|
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
8003304: 687b ldr r3, [r7, #4]
|
|
8003306: 689a ldr r2, [r3, #8]
|
|
8003308: 4b31 ldr r3, [pc, #196] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800330a: 689b ldr r3, [r3, #8]
|
|
800330c: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8003310: 429a cmp r2, r3
|
|
8003312: d208 bcs.n 8003326 <HAL_RCC_ClockConfig+0x146>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8003314: 4b2e ldr r3, [pc, #184] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003316: 689b ldr r3, [r3, #8]
|
|
8003318: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
800331c: 687b ldr r3, [r7, #4]
|
|
800331e: 689b ldr r3, [r3, #8]
|
|
8003320: 492b ldr r1, [pc, #172] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003322: 4313 orrs r3, r2
|
|
8003324: 608b str r3, [r1, #8]
|
|
}
|
|
}
|
|
|
|
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8003326: 4b29 ldr r3, [pc, #164] @ (80033cc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8003328: 681b ldr r3, [r3, #0]
|
|
800332a: f003 0307 and.w r3, r3, #7
|
|
800332e: 683a ldr r2, [r7, #0]
|
|
8003330: 429a cmp r2, r3
|
|
8003332: d210 bcs.n 8003356 <HAL_RCC_ClockConfig+0x176>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003334: 4b25 ldr r3, [pc, #148] @ (80033cc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8003336: 681b ldr r3, [r3, #0]
|
|
8003338: f023 0207 bic.w r2, r3, #7
|
|
800333c: 4923 ldr r1, [pc, #140] @ (80033cc <HAL_RCC_ClockConfig+0x1ec>)
|
|
800333e: 683b ldr r3, [r7, #0]
|
|
8003340: 4313 orrs r3, r2
|
|
8003342: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8003344: 4b21 ldr r3, [pc, #132] @ (80033cc <HAL_RCC_ClockConfig+0x1ec>)
|
|
8003346: 681b ldr r3, [r3, #0]
|
|
8003348: f003 0307 and.w r3, r3, #7
|
|
800334c: 683a ldr r2, [r7, #0]
|
|
800334e: 429a cmp r2, r3
|
|
8003350: d001 beq.n 8003356 <HAL_RCC_ClockConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
8003352: 2301 movs r3, #1
|
|
8003354: e036 b.n 80033c4 <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003356: 687b ldr r3, [r7, #4]
|
|
8003358: 681b ldr r3, [r3, #0]
|
|
800335a: f003 0304 and.w r3, r3, #4
|
|
800335e: 2b00 cmp r3, #0
|
|
8003360: d008 beq.n 8003374 <HAL_RCC_ClockConfig+0x194>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8003362: 4b1b ldr r3, [pc, #108] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003364: 689b ldr r3, [r3, #8]
|
|
8003366: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
800336a: 687b ldr r3, [r7, #4]
|
|
800336c: 68db ldr r3, [r3, #12]
|
|
800336e: 4918 ldr r1, [pc, #96] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003370: 4313 orrs r3, r2
|
|
8003372: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8003374: 687b ldr r3, [r7, #4]
|
|
8003376: 681b ldr r3, [r3, #0]
|
|
8003378: f003 0308 and.w r3, r3, #8
|
|
800337c: 2b00 cmp r3, #0
|
|
800337e: d009 beq.n 8003394 <HAL_RCC_ClockConfig+0x1b4>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8003380: 4b13 ldr r3, [pc, #76] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003382: 689b ldr r3, [r3, #8]
|
|
8003384: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
8003388: 687b ldr r3, [r7, #4]
|
|
800338a: 691b ldr r3, [r3, #16]
|
|
800338c: 00db lsls r3, r3, #3
|
|
800338e: 4910 ldr r1, [pc, #64] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8003390: 4313 orrs r3, r2
|
|
8003392: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8003394: f000 f824 bl 80033e0 <HAL_RCC_GetSysClockFreq>
|
|
8003398: 4602 mov r2, r0
|
|
800339a: 4b0d ldr r3, [pc, #52] @ (80033d0 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800339c: 689b ldr r3, [r3, #8]
|
|
800339e: 091b lsrs r3, r3, #4
|
|
80033a0: f003 030f and.w r3, r3, #15
|
|
80033a4: 490b ldr r1, [pc, #44] @ (80033d4 <HAL_RCC_ClockConfig+0x1f4>)
|
|
80033a6: 5ccb ldrb r3, [r1, r3]
|
|
80033a8: f003 031f and.w r3, r3, #31
|
|
80033ac: fa22 f303 lsr.w r3, r2, r3
|
|
80033b0: 4a09 ldr r2, [pc, #36] @ (80033d8 <HAL_RCC_ClockConfig+0x1f8>)
|
|
80033b2: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
80033b4: 4b09 ldr r3, [pc, #36] @ (80033dc <HAL_RCC_ClockConfig+0x1fc>)
|
|
80033b6: 681b ldr r3, [r3, #0]
|
|
80033b8: 4618 mov r0, r3
|
|
80033ba: f7fe f9a9 bl 8001710 <HAL_InitTick>
|
|
80033be: 4603 mov r3, r0
|
|
80033c0: 72fb strb r3, [r7, #11]
|
|
|
|
return status;
|
|
80033c2: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
80033c4: 4618 mov r0, r3
|
|
80033c6: 3710 adds r7, #16
|
|
80033c8: 46bd mov sp, r7
|
|
80033ca: bd80 pop {r7, pc}
|
|
80033cc: 40022000 .word 0x40022000
|
|
80033d0: 40021000 .word 0x40021000
|
|
80033d4: 0800750c .word 0x0800750c
|
|
80033d8: 20000000 .word 0x20000000
|
|
80033dc: 20000004 .word 0x20000004
|
|
|
|
080033e0 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80033e0: b480 push {r7}
|
|
80033e2: b089 sub sp, #36 @ 0x24
|
|
80033e4: af00 add r7, sp, #0
|
|
uint32_t msirange = 0U, sysclockfreq = 0U;
|
|
80033e6: 2300 movs r3, #0
|
|
80033e8: 61fb str r3, [r7, #28]
|
|
80033ea: 2300 movs r3, #0
|
|
80033ec: 61bb str r3, [r7, #24]
|
|
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
|
|
uint32_t sysclk_source, pll_oscsource;
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
80033ee: 4b3e ldr r3, [pc, #248] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80033f0: 689b ldr r3, [r3, #8]
|
|
80033f2: f003 030c and.w r3, r3, #12
|
|
80033f6: 613b str r3, [r7, #16]
|
|
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
80033f8: 4b3b ldr r3, [pc, #236] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80033fa: 68db ldr r3, [r3, #12]
|
|
80033fc: f003 0303 and.w r3, r3, #3
|
|
8003400: 60fb str r3, [r7, #12]
|
|
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
8003402: 693b ldr r3, [r7, #16]
|
|
8003404: 2b00 cmp r3, #0
|
|
8003406: d005 beq.n 8003414 <HAL_RCC_GetSysClockFreq+0x34>
|
|
8003408: 693b ldr r3, [r7, #16]
|
|
800340a: 2b0c cmp r3, #12
|
|
800340c: d121 bne.n 8003452 <HAL_RCC_GetSysClockFreq+0x72>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
|
|
800340e: 68fb ldr r3, [r7, #12]
|
|
8003410: 2b01 cmp r3, #1
|
|
8003412: d11e bne.n 8003452 <HAL_RCC_GetSysClockFreq+0x72>
|
|
{
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
|
|
/* Get SYSCLK source */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
|
|
8003414: 4b34 ldr r3, [pc, #208] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8003416: 681b ldr r3, [r3, #0]
|
|
8003418: f003 0308 and.w r3, r3, #8
|
|
800341c: 2b00 cmp r3, #0
|
|
800341e: d107 bne.n 8003430 <HAL_RCC_GetSysClockFreq+0x50>
|
|
{ /* MSISRANGE from RCC_CSR applies */
|
|
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
|
|
8003420: 4b31 ldr r3, [pc, #196] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8003422: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003426: 0a1b lsrs r3, r3, #8
|
|
8003428: f003 030f and.w r3, r3, #15
|
|
800342c: 61fb str r3, [r7, #28]
|
|
800342e: e005 b.n 800343c <HAL_RCC_GetSysClockFreq+0x5c>
|
|
}
|
|
else
|
|
{ /* MSIRANGE from RCC_CR applies */
|
|
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
|
|
8003430: 4b2d ldr r3, [pc, #180] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8003432: 681b ldr r3, [r3, #0]
|
|
8003434: 091b lsrs r3, r3, #4
|
|
8003436: f003 030f and.w r3, r3, #15
|
|
800343a: 61fb str r3, [r7, #28]
|
|
}
|
|
/*MSI frequency range in HZ*/
|
|
msirange = MSIRangeTable[msirange];
|
|
800343c: 4a2b ldr r2, [pc, #172] @ (80034ec <HAL_RCC_GetSysClockFreq+0x10c>)
|
|
800343e: 69fb ldr r3, [r7, #28]
|
|
8003440: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8003444: 61fb str r3, [r7, #28]
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8003446: 693b ldr r3, [r7, #16]
|
|
8003448: 2b00 cmp r3, #0
|
|
800344a: d10d bne.n 8003468 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = msirange;
|
|
800344c: 69fb ldr r3, [r7, #28]
|
|
800344e: 61bb str r3, [r7, #24]
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8003450: e00a b.n 8003468 <HAL_RCC_GetSysClockFreq+0x88>
|
|
}
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSI)
|
|
8003452: 693b ldr r3, [r7, #16]
|
|
8003454: 2b04 cmp r3, #4
|
|
8003456: d102 bne.n 800345e <HAL_RCC_GetSysClockFreq+0x7e>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
8003458: 4b25 ldr r3, [pc, #148] @ (80034f0 <HAL_RCC_GetSysClockFreq+0x110>)
|
|
800345a: 61bb str r3, [r7, #24]
|
|
800345c: e004 b.n 8003468 <HAL_RCC_GetSysClockFreq+0x88>
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSE)
|
|
800345e: 693b ldr r3, [r7, #16]
|
|
8003460: 2b08 cmp r3, #8
|
|
8003462: d101 bne.n 8003468 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
8003464: 4b23 ldr r3, [pc, #140] @ (80034f4 <HAL_RCC_GetSysClockFreq+0x114>)
|
|
8003466: 61bb str r3, [r7, #24]
|
|
else
|
|
{
|
|
/* unexpected case: sysclockfreq at 0 */
|
|
}
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_PLL)
|
|
8003468: 693b ldr r3, [r7, #16]
|
|
800346a: 2b0c cmp r3, #12
|
|
800346c: d134 bne.n 80034d8 <HAL_RCC_GetSysClockFreq+0xf8>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
800346e: 4b1e ldr r3, [pc, #120] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8003470: 68db ldr r3, [r3, #12]
|
|
8003472: f003 0303 and.w r3, r3, #3
|
|
8003476: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
8003478: 68bb ldr r3, [r7, #8]
|
|
800347a: 2b02 cmp r3, #2
|
|
800347c: d003 beq.n 8003486 <HAL_RCC_GetSysClockFreq+0xa6>
|
|
800347e: 68bb ldr r3, [r7, #8]
|
|
8003480: 2b03 cmp r3, #3
|
|
8003482: d003 beq.n 800348c <HAL_RCC_GetSysClockFreq+0xac>
|
|
8003484: e005 b.n 8003492 <HAL_RCC_GetSysClockFreq+0xb2>
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllvco = HSI_VALUE;
|
|
8003486: 4b1a ldr r3, [pc, #104] @ (80034f0 <HAL_RCC_GetSysClockFreq+0x110>)
|
|
8003488: 617b str r3, [r7, #20]
|
|
break;
|
|
800348a: e005 b.n 8003498 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = HSE_VALUE;
|
|
800348c: 4b19 ldr r3, [pc, #100] @ (80034f4 <HAL_RCC_GetSysClockFreq+0x114>)
|
|
800348e: 617b str r3, [r7, #20]
|
|
break;
|
|
8003490: e002 b.n 8003498 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllvco = msirange;
|
|
8003492: 69fb ldr r3, [r7, #28]
|
|
8003494: 617b str r3, [r7, #20]
|
|
break;
|
|
8003496: bf00 nop
|
|
}
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8003498: 4b13 ldr r3, [pc, #76] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
800349a: 68db ldr r3, [r3, #12]
|
|
800349c: 091b lsrs r3, r3, #4
|
|
800349e: f003 0307 and.w r3, r3, #7
|
|
80034a2: 3301 adds r3, #1
|
|
80034a4: 607b str r3, [r7, #4]
|
|
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
|
|
80034a6: 4b10 ldr r3, [pc, #64] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80034a8: 68db ldr r3, [r3, #12]
|
|
80034aa: 0a1b lsrs r3, r3, #8
|
|
80034ac: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80034b0: 697a ldr r2, [r7, #20]
|
|
80034b2: fb03 f202 mul.w r2, r3, r2
|
|
80034b6: 687b ldr r3, [r7, #4]
|
|
80034b8: fbb2 f3f3 udiv r3, r2, r3
|
|
80034bc: 617b str r3, [r7, #20]
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
80034be: 4b0a ldr r3, [pc, #40] @ (80034e8 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80034c0: 68db ldr r3, [r3, #12]
|
|
80034c2: 0e5b lsrs r3, r3, #25
|
|
80034c4: f003 0303 and.w r3, r3, #3
|
|
80034c8: 3301 adds r3, #1
|
|
80034ca: 005b lsls r3, r3, #1
|
|
80034cc: 603b str r3, [r7, #0]
|
|
sysclockfreq = pllvco / pllr;
|
|
80034ce: 697a ldr r2, [r7, #20]
|
|
80034d0: 683b ldr r3, [r7, #0]
|
|
80034d2: fbb2 f3f3 udiv r3, r2, r3
|
|
80034d6: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
80034d8: 69bb ldr r3, [r7, #24]
|
|
}
|
|
80034da: 4618 mov r0, r3
|
|
80034dc: 3724 adds r7, #36 @ 0x24
|
|
80034de: 46bd mov sp, r7
|
|
80034e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80034e4: 4770 bx lr
|
|
80034e6: bf00 nop
|
|
80034e8: 40021000 .word 0x40021000
|
|
80034ec: 08007524 .word 0x08007524
|
|
80034f0: 00f42400 .word 0x00f42400
|
|
80034f4: 007a1200 .word 0x007a1200
|
|
|
|
080034f8 <HAL_RCC_GetHCLKFreq>:
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
80034f8: b480 push {r7}
|
|
80034fa: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
80034fc: 4b03 ldr r3, [pc, #12] @ (800350c <HAL_RCC_GetHCLKFreq+0x14>)
|
|
80034fe: 681b ldr r3, [r3, #0]
|
|
}
|
|
8003500: 4618 mov r0, r3
|
|
8003502: 46bd mov sp, r7
|
|
8003504: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003508: 4770 bx lr
|
|
800350a: bf00 nop
|
|
800350c: 20000000 .word 0x20000000
|
|
|
|
08003510 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8003510: b580 push {r7, lr}
|
|
8003512: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
|
8003514: f7ff fff0 bl 80034f8 <HAL_RCC_GetHCLKFreq>
|
|
8003518: 4602 mov r2, r0
|
|
800351a: 4b06 ldr r3, [pc, #24] @ (8003534 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
800351c: 689b ldr r3, [r3, #8]
|
|
800351e: 0a1b lsrs r3, r3, #8
|
|
8003520: f003 0307 and.w r3, r3, #7
|
|
8003524: 4904 ldr r1, [pc, #16] @ (8003538 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|
8003526: 5ccb ldrb r3, [r1, r3]
|
|
8003528: f003 031f and.w r3, r3, #31
|
|
800352c: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8003530: 4618 mov r0, r3
|
|
8003532: bd80 pop {r7, pc}
|
|
8003534: 40021000 .word 0x40021000
|
|
8003538: 0800751c .word 0x0800751c
|
|
|
|
0800353c <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
800353c: b580 push {r7, lr}
|
|
800353e: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
|
8003540: f7ff ffda bl 80034f8 <HAL_RCC_GetHCLKFreq>
|
|
8003544: 4602 mov r2, r0
|
|
8003546: 4b06 ldr r3, [pc, #24] @ (8003560 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
8003548: 689b ldr r3, [r3, #8]
|
|
800354a: 0adb lsrs r3, r3, #11
|
|
800354c: f003 0307 and.w r3, r3, #7
|
|
8003550: 4904 ldr r1, [pc, #16] @ (8003564 <HAL_RCC_GetPCLK2Freq+0x28>)
|
|
8003552: 5ccb ldrb r3, [r1, r3]
|
|
8003554: f003 031f and.w r3, r3, #31
|
|
8003558: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
800355c: 4618 mov r0, r3
|
|
800355e: bd80 pop {r7, pc}
|
|
8003560: 40021000 .word 0x40021000
|
|
8003564: 0800751c .word 0x0800751c
|
|
|
|
08003568 <RCC_SetFlashLatencyFromMSIRange>:
|
|
voltage range.
|
|
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
|
{
|
|
8003568: b580 push {r7, lr}
|
|
800356a: b086 sub sp, #24
|
|
800356c: af00 add r7, sp, #0
|
|
800356e: 6078 str r0, [r7, #4]
|
|
uint32_t vos;
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
8003570: 2300 movs r3, #0
|
|
8003572: 613b str r3, [r7, #16]
|
|
|
|
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
|
8003574: 4b2a ldr r3, [pc, #168] @ (8003620 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8003576: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003578: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800357c: 2b00 cmp r3, #0
|
|
800357e: d003 beq.n 8003588 <RCC_SetFlashLatencyFromMSIRange+0x20>
|
|
{
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
8003580: f7ff f9ee bl 8002960 <HAL_PWREx_GetVoltageRange>
|
|
8003584: 6178 str r0, [r7, #20]
|
|
8003586: e014 b.n 80035b2 <RCC_SetFlashLatencyFromMSIRange+0x4a>
|
|
}
|
|
else
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8003588: 4b25 ldr r3, [pc, #148] @ (8003620 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
800358a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800358c: 4a24 ldr r2, [pc, #144] @ (8003620 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
800358e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003592: 6593 str r3, [r2, #88] @ 0x58
|
|
8003594: 4b22 ldr r3, [pc, #136] @ (8003620 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8003596: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003598: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800359c: 60fb str r3, [r7, #12]
|
|
800359e: 68fb ldr r3, [r7, #12]
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
80035a0: f7ff f9de bl 8002960 <HAL_PWREx_GetVoltageRange>
|
|
80035a4: 6178 str r0, [r7, #20]
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80035a6: 4b1e ldr r3, [pc, #120] @ (8003620 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
80035a8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80035aa: 4a1d ldr r2, [pc, #116] @ (8003620 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
80035ac: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80035b0: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
|
|
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
80035b2: 697b ldr r3, [r7, #20]
|
|
80035b4: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80035b8: d10b bne.n 80035d2 <RCC_SetFlashLatencyFromMSIRange+0x6a>
|
|
{
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
80035ba: 687b ldr r3, [r7, #4]
|
|
80035bc: 2b80 cmp r3, #128 @ 0x80
|
|
80035be: d919 bls.n 80035f4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
if(msirange > RCC_MSIRANGE_10)
|
|
80035c0: 687b ldr r3, [r7, #4]
|
|
80035c2: 2ba0 cmp r3, #160 @ 0xa0
|
|
80035c4: d902 bls.n 80035cc <RCC_SetFlashLatencyFromMSIRange+0x64>
|
|
{
|
|
/* MSI 48Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
80035c6: 2302 movs r3, #2
|
|
80035c8: 613b str r3, [r7, #16]
|
|
80035ca: e013 b.n 80035f4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else
|
|
{
|
|
/* MSI 24Mhz or 32Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
80035cc: 2301 movs r3, #1
|
|
80035ce: 613b str r3, [r7, #16]
|
|
80035d0: e010 b.n 80035f4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
}
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
}
|
|
#else
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
80035d2: 687b ldr r3, [r7, #4]
|
|
80035d4: 2b80 cmp r3, #128 @ 0x80
|
|
80035d6: d902 bls.n 80035de <RCC_SetFlashLatencyFromMSIRange+0x76>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
latency = FLASH_LATENCY_3; /* 3WS */
|
|
80035d8: 2303 movs r3, #3
|
|
80035da: 613b str r3, [r7, #16]
|
|
80035dc: e00a b.n 80035f4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else
|
|
{
|
|
if(msirange == RCC_MSIRANGE_8)
|
|
80035de: 687b ldr r3, [r7, #4]
|
|
80035e0: 2b80 cmp r3, #128 @ 0x80
|
|
80035e2: d102 bne.n 80035ea <RCC_SetFlashLatencyFromMSIRange+0x82>
|
|
{
|
|
/* MSI 16Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
80035e4: 2302 movs r3, #2
|
|
80035e6: 613b str r3, [r7, #16]
|
|
80035e8: e004 b.n 80035f4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else if(msirange == RCC_MSIRANGE_7)
|
|
80035ea: 687b ldr r3, [r7, #4]
|
|
80035ec: 2b70 cmp r3, #112 @ 0x70
|
|
80035ee: d101 bne.n 80035f4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
{
|
|
/* MSI 8Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
80035f0: 2301 movs r3, #1
|
|
80035f2: 613b str r3, [r7, #16]
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
80035f4: 4b0b ldr r3, [pc, #44] @ (8003624 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
80035f6: 681b ldr r3, [r3, #0]
|
|
80035f8: f023 0207 bic.w r2, r3, #7
|
|
80035fc: 4909 ldr r1, [pc, #36] @ (8003624 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
80035fe: 693b ldr r3, [r7, #16]
|
|
8003600: 4313 orrs r3, r2
|
|
8003602: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != latency)
|
|
8003604: 4b07 ldr r3, [pc, #28] @ (8003624 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
8003606: 681b ldr r3, [r3, #0]
|
|
8003608: f003 0307 and.w r3, r3, #7
|
|
800360c: 693a ldr r2, [r7, #16]
|
|
800360e: 429a cmp r2, r3
|
|
8003610: d001 beq.n 8003616 <RCC_SetFlashLatencyFromMSIRange+0xae>
|
|
{
|
|
return HAL_ERROR;
|
|
8003612: 2301 movs r3, #1
|
|
8003614: e000 b.n 8003618 <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003616: 2300 movs r3, #0
|
|
}
|
|
8003618: 4618 mov r0, r3
|
|
800361a: 3718 adds r7, #24
|
|
800361c: 46bd mov sp, r7
|
|
800361e: bd80 pop {r7, pc}
|
|
8003620: 40021000 .word 0x40021000
|
|
8003624: 40022000 .word 0x40022000
|
|
|
|
08003628 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8003628: b580 push {r7, lr}
|
|
800362a: b086 sub sp, #24
|
|
800362c: af00 add r7, sp, #0
|
|
800362e: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister, tickstart; /* no init needed */
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
8003630: 2300 movs r3, #0
|
|
8003632: 74fb strb r3, [r7, #19]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
8003634: 2300 movs r3, #0
|
|
8003636: 74bb strb r3, [r7, #18]
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
#if defined(SAI1)
|
|
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
|
|
8003638: 687b ldr r3, [r7, #4]
|
|
800363a: 681b ldr r3, [r3, #0]
|
|
800363c: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8003640: 2b00 cmp r3, #0
|
|
8003642: d041 beq.n 80036c8 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai1ClockSelection)
|
|
8003644: 687b ldr r3, [r7, #4]
|
|
8003646: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8003648: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
800364c: d02a beq.n 80036a4 <HAL_RCCEx_PeriphCLKConfig+0x7c>
|
|
800364e: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
8003652: d824 bhi.n 800369e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
8003654: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
8003658: d008 beq.n 800366c <HAL_RCCEx_PeriphCLKConfig+0x44>
|
|
800365a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
800365e: d81e bhi.n 800369e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
8003660: 2b00 cmp r3, #0
|
|
8003662: d00a beq.n 800367a <HAL_RCCEx_PeriphCLKConfig+0x52>
|
|
8003664: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8003668: d010 beq.n 800368c <HAL_RCCEx_PeriphCLKConfig+0x64>
|
|
800366a: e018 b.n 800369e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
{
|
|
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
800366c: 4b86 ldr r3, [pc, #536] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800366e: 68db ldr r3, [r3, #12]
|
|
8003670: 4a85 ldr r2, [pc, #532] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003672: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003676: 60d3 str r3, [r2, #12]
|
|
#else
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8003678: e015 b.n 80036a6 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
800367a: 687b ldr r3, [r7, #4]
|
|
800367c: 3304 adds r3, #4
|
|
800367e: 2100 movs r1, #0
|
|
8003680: 4618 mov r0, r3
|
|
8003682: f000 fabb bl 8003bfc <RCCEx_PLLSAI1_Config>
|
|
8003686: 4603 mov r3, r0
|
|
8003688: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
800368a: e00c b.n 80036a6 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
800368c: 687b ldr r3, [r7, #4]
|
|
800368e: 3320 adds r3, #32
|
|
8003690: 2100 movs r1, #0
|
|
8003692: 4618 mov r0, r3
|
|
8003694: f000 fba6 bl 8003de4 <RCCEx_PLLSAI2_Config>
|
|
8003698: 4603 mov r3, r0
|
|
800369a: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
800369c: e003 b.n 80036a6 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
800369e: 2301 movs r3, #1
|
|
80036a0: 74fb strb r3, [r7, #19]
|
|
break;
|
|
80036a2: e000 b.n 80036a6 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
break;
|
|
80036a4: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
80036a6: 7cfb ldrb r3, [r7, #19]
|
|
80036a8: 2b00 cmp r3, #0
|
|
80036aa: d10b bne.n 80036c4 <HAL_RCCEx_PeriphCLKConfig+0x9c>
|
|
{
|
|
/* Set the source of SAI1 clock*/
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
80036ac: 4b76 ldr r3, [pc, #472] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80036ae: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80036b2: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
80036b6: 687b ldr r3, [r7, #4]
|
|
80036b8: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
80036ba: 4973 ldr r1, [pc, #460] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80036bc: 4313 orrs r3, r2
|
|
80036be: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
80036c2: e001 b.n 80036c8 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80036c4: 7cfb ldrb r3, [r7, #19]
|
|
80036c6: 74bb strb r3, [r7, #18]
|
|
#endif /* SAI1 */
|
|
|
|
#if defined(SAI2)
|
|
|
|
/*-------------------------- SAI2 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
|
|
80036c8: 687b ldr r3, [r7, #4]
|
|
80036ca: 681b ldr r3, [r3, #0]
|
|
80036cc: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80036d0: 2b00 cmp r3, #0
|
|
80036d2: d041 beq.n 8003758 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai2ClockSelection)
|
|
80036d4: 687b ldr r3, [r7, #4]
|
|
80036d6: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
80036d8: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
|
|
80036dc: d02a beq.n 8003734 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
80036de: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
|
|
80036e2: d824 bhi.n 800372e <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
80036e4: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
80036e8: d008 beq.n 80036fc <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
|
80036ea: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
80036ee: d81e bhi.n 800372e <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
80036f0: 2b00 cmp r3, #0
|
|
80036f2: d00a beq.n 800370a <HAL_RCCEx_PeriphCLKConfig+0xe2>
|
|
80036f4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80036f8: d010 beq.n 800371c <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
80036fa: e018 b.n 800372e <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
{
|
|
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
80036fc: 4b62 ldr r3, [pc, #392] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80036fe: 68db ldr r3, [r3, #12]
|
|
8003700: 4a61 ldr r2, [pc, #388] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003702: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003706: 60d3 str r3, [r2, #12]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8003708: e015 b.n 8003736 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
800370a: 687b ldr r3, [r7, #4]
|
|
800370c: 3304 adds r3, #4
|
|
800370e: 2100 movs r1, #0
|
|
8003710: 4618 mov r0, r3
|
|
8003712: f000 fa73 bl 8003bfc <RCCEx_PLLSAI1_Config>
|
|
8003716: 4603 mov r3, r0
|
|
8003718: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
800371a: e00c b.n 8003736 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
800371c: 687b ldr r3, [r7, #4]
|
|
800371e: 3320 adds r3, #32
|
|
8003720: 2100 movs r1, #0
|
|
8003722: 4618 mov r0, r3
|
|
8003724: f000 fb5e bl 8003de4 <RCCEx_PLLSAI2_Config>
|
|
8003728: 4603 mov r3, r0
|
|
800372a: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
800372c: e003 b.n 8003736 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
800372e: 2301 movs r3, #1
|
|
8003730: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8003732: e000 b.n 8003736 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
break;
|
|
8003734: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8003736: 7cfb ldrb r3, [r7, #19]
|
|
8003738: 2b00 cmp r3, #0
|
|
800373a: d10b bne.n 8003754 <HAL_RCCEx_PeriphCLKConfig+0x12c>
|
|
{
|
|
/* Set the source of SAI2 clock*/
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
800373c: 4b52 ldr r3, [pc, #328] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800373e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003742: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
|
|
8003746: 687b ldr r3, [r7, #4]
|
|
8003748: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
800374a: 494f ldr r1, [pc, #316] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800374c: 4313 orrs r3, r2
|
|
800374e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
8003752: e001 b.n 8003758 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003754: 7cfb ldrb r3, [r7, #19]
|
|
8003756: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
#endif /* SAI2 */
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
8003758: 687b ldr r3, [r7, #4]
|
|
800375a: 681b ldr r3, [r3, #0]
|
|
800375c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003760: 2b00 cmp r3, #0
|
|
8003762: f000 80a0 beq.w 80038a6 <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8003766: 2300 movs r3, #0
|
|
8003768: 747b strb r3, [r7, #17]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
800376a: 4b47 ldr r3, [pc, #284] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800376c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800376e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003772: 2b00 cmp r3, #0
|
|
8003774: d101 bne.n 800377a <HAL_RCCEx_PeriphCLKConfig+0x152>
|
|
8003776: 2301 movs r3, #1
|
|
8003778: e000 b.n 800377c <HAL_RCCEx_PeriphCLKConfig+0x154>
|
|
800377a: 2300 movs r3, #0
|
|
800377c: 2b00 cmp r3, #0
|
|
800377e: d00d beq.n 800379c <HAL_RCCEx_PeriphCLKConfig+0x174>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8003780: 4b41 ldr r3, [pc, #260] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003782: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003784: 4a40 ldr r2, [pc, #256] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003786: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800378a: 6593 str r3, [r2, #88] @ 0x58
|
|
800378c: 4b3e ldr r3, [pc, #248] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800378e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003790: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003794: 60bb str r3, [r7, #8]
|
|
8003796: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8003798: 2301 movs r3, #1
|
|
800379a: 747b strb r3, [r7, #17]
|
|
}
|
|
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
800379c: 4b3b ldr r3, [pc, #236] @ (800388c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
800379e: 681b ldr r3, [r3, #0]
|
|
80037a0: 4a3a ldr r2, [pc, #232] @ (800388c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
80037a2: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80037a6: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80037a8: f7fe f802 bl 80017b0 <HAL_GetTick>
|
|
80037ac: 60f8 str r0, [r7, #12]
|
|
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
80037ae: e009 b.n 80037c4 <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80037b0: f7fd fffe bl 80017b0 <HAL_GetTick>
|
|
80037b4: 4602 mov r2, r0
|
|
80037b6: 68fb ldr r3, [r7, #12]
|
|
80037b8: 1ad3 subs r3, r2, r3
|
|
80037ba: 2b02 cmp r3, #2
|
|
80037bc: d902 bls.n 80037c4 <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
80037be: 2303 movs r3, #3
|
|
80037c0: 74fb strb r3, [r7, #19]
|
|
break;
|
|
80037c2: e005 b.n 80037d0 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
80037c4: 4b31 ldr r3, [pc, #196] @ (800388c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
80037c6: 681b ldr r3, [r3, #0]
|
|
80037c8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80037cc: 2b00 cmp r3, #0
|
|
80037ce: d0ef beq.n 80037b0 <HAL_RCCEx_PeriphCLKConfig+0x188>
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
80037d0: 7cfb ldrb r3, [r7, #19]
|
|
80037d2: 2b00 cmp r3, #0
|
|
80037d4: d15c bne.n 8003890 <HAL_RCCEx_PeriphCLKConfig+0x268>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
80037d6: 4b2c ldr r3, [pc, #176] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80037d8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80037dc: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80037e0: 617b str r3, [r7, #20]
|
|
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
80037e2: 697b ldr r3, [r7, #20]
|
|
80037e4: 2b00 cmp r3, #0
|
|
80037e6: d01f beq.n 8003828 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
|
80037e8: 687b ldr r3, [r7, #4]
|
|
80037ea: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80037ee: 697a ldr r2, [r7, #20]
|
|
80037f0: 429a cmp r2, r3
|
|
80037f2: d019 beq.n 8003828 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
80037f4: 4b24 ldr r3, [pc, #144] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80037f6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80037fa: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80037fe: 617b str r3, [r7, #20]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8003800: 4b21 ldr r3, [pc, #132] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003802: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003806: 4a20 ldr r2, [pc, #128] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003808: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800380c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8003810: 4b1d ldr r3, [pc, #116] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003812: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003816: 4a1c ldr r2, [pc, #112] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003818: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800381c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
8003820: 4a19 ldr r2, [pc, #100] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003822: 697b ldr r3, [r7, #20]
|
|
8003824: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
8003828: 697b ldr r3, [r7, #20]
|
|
800382a: f003 0301 and.w r3, r3, #1
|
|
800382e: 2b00 cmp r3, #0
|
|
8003830: d016 beq.n 8003860 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003832: f7fd ffbd bl 80017b0 <HAL_GetTick>
|
|
8003836: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003838: e00b b.n 8003852 <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800383a: f7fd ffb9 bl 80017b0 <HAL_GetTick>
|
|
800383e: 4602 mov r2, r0
|
|
8003840: 68fb ldr r3, [r7, #12]
|
|
8003842: 1ad3 subs r3, r2, r3
|
|
8003844: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003848: 4293 cmp r3, r2
|
|
800384a: d902 bls.n 8003852 <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
800384c: 2303 movs r3, #3
|
|
800384e: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8003850: e006 b.n 8003860 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003852: 4b0d ldr r3, [pc, #52] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003854: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003858: f003 0302 and.w r3, r3, #2
|
|
800385c: 2b00 cmp r3, #0
|
|
800385e: d0ec beq.n 800383a <HAL_RCCEx_PeriphCLKConfig+0x212>
|
|
}
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8003860: 7cfb ldrb r3, [r7, #19]
|
|
8003862: 2b00 cmp r3, #0
|
|
8003864: d10c bne.n 8003880 <HAL_RCCEx_PeriphCLKConfig+0x258>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8003866: 4b08 ldr r3, [pc, #32] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003868: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800386c: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8003870: 687b ldr r3, [r7, #4]
|
|
8003872: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003876: 4904 ldr r1, [pc, #16] @ (8003888 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8003878: 4313 orrs r3, r2
|
|
800387a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
800387e: e009 b.n 8003894 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003880: 7cfb ldrb r3, [r7, #19]
|
|
8003882: 74bb strb r3, [r7, #18]
|
|
8003884: e006 b.n 8003894 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
8003886: bf00 nop
|
|
8003888: 40021000 .word 0x40021000
|
|
800388c: 40007000 .word 0x40007000
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003890: 7cfb ldrb r3, [r7, #19]
|
|
8003892: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
8003894: 7c7b ldrb r3, [r7, #17]
|
|
8003896: 2b01 cmp r3, #1
|
|
8003898: d105 bne.n 80038a6 <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
800389a: 4b9e ldr r3, [pc, #632] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800389c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800389e: 4a9d ldr r2, [pc, #628] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80038a0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80038a4: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
80038a6: 687b ldr r3, [r7, #4]
|
|
80038a8: 681b ldr r3, [r3, #0]
|
|
80038aa: f003 0301 and.w r3, r3, #1
|
|
80038ae: 2b00 cmp r3, #0
|
|
80038b0: d00a beq.n 80038c8 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
80038b2: 4b98 ldr r3, [pc, #608] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80038b4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80038b8: f023 0203 bic.w r2, r3, #3
|
|
80038bc: 687b ldr r3, [r7, #4]
|
|
80038be: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80038c0: 4994 ldr r1, [pc, #592] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80038c2: 4313 orrs r3, r2
|
|
80038c4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
80038c8: 687b ldr r3, [r7, #4]
|
|
80038ca: 681b ldr r3, [r3, #0]
|
|
80038cc: f003 0302 and.w r3, r3, #2
|
|
80038d0: 2b00 cmp r3, #0
|
|
80038d2: d00a beq.n 80038ea <HAL_RCCEx_PeriphCLKConfig+0x2c2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
80038d4: 4b8f ldr r3, [pc, #572] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80038d6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80038da: f023 020c bic.w r2, r3, #12
|
|
80038de: 687b ldr r3, [r7, #4]
|
|
80038e0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80038e2: 498c ldr r1, [pc, #560] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80038e4: 4313 orrs r3, r2
|
|
80038e6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(USART3)
|
|
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
80038ea: 687b ldr r3, [r7, #4]
|
|
80038ec: 681b ldr r3, [r3, #0]
|
|
80038ee: f003 0304 and.w r3, r3, #4
|
|
80038f2: 2b00 cmp r3, #0
|
|
80038f4: d00a beq.n 800390c <HAL_RCCEx_PeriphCLKConfig+0x2e4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
80038f6: 4b87 ldr r3, [pc, #540] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80038f8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80038fc: f023 0230 bic.w r2, r3, #48 @ 0x30
|
|
8003900: 687b ldr r3, [r7, #4]
|
|
8003902: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003904: 4983 ldr r1, [pc, #524] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003906: 4313 orrs r3, r2
|
|
8003908: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* USART3 */
|
|
|
|
#if defined(UART4)
|
|
|
|
/*-------------------------- UART4 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
800390c: 687b ldr r3, [r7, #4]
|
|
800390e: 681b ldr r3, [r3, #0]
|
|
8003910: f003 0308 and.w r3, r3, #8
|
|
8003914: 2b00 cmp r3, #0
|
|
8003916: d00a beq.n 800392e <HAL_RCCEx_PeriphCLKConfig+0x306>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
8003918: 4b7e ldr r3, [pc, #504] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800391a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800391e: f023 02c0 bic.w r2, r3, #192 @ 0xc0
|
|
8003922: 687b ldr r3, [r7, #4]
|
|
8003924: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8003926: 497b ldr r1, [pc, #492] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003928: 4313 orrs r3, r2
|
|
800392a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* UART4 */
|
|
|
|
#if defined(UART5)
|
|
|
|
/*-------------------------- UART5 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
|
800392e: 687b ldr r3, [r7, #4]
|
|
8003930: 681b ldr r3, [r3, #0]
|
|
8003932: f003 0310 and.w r3, r3, #16
|
|
8003936: 2b00 cmp r3, #0
|
|
8003938: d00a beq.n 8003950 <HAL_RCCEx_PeriphCLKConfig+0x328>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
|
|
|
/* Configure the UART5 clock source */
|
|
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
|
800393a: 4b76 ldr r3, [pc, #472] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800393c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003940: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8003944: 687b ldr r3, [r7, #4]
|
|
8003946: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8003948: 4972 ldr r1, [pc, #456] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800394a: 4313 orrs r3, r2
|
|
800394c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* UART5 */
|
|
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
8003950: 687b ldr r3, [r7, #4]
|
|
8003952: 681b ldr r3, [r3, #0]
|
|
8003954: f003 0320 and.w r3, r3, #32
|
|
8003958: 2b00 cmp r3, #0
|
|
800395a: d00a beq.n 8003972 <HAL_RCCEx_PeriphCLKConfig+0x34a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUART1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
800395c: 4b6d ldr r3, [pc, #436] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800395e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003962: f423 6240 bic.w r2, r3, #3072 @ 0xc00
|
|
8003966: 687b ldr r3, [r7, #4]
|
|
8003968: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800396a: 496a ldr r1, [pc, #424] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800396c: 4313 orrs r3, r2
|
|
800396e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
8003972: 687b ldr r3, [r7, #4]
|
|
8003974: 681b ldr r3, [r3, #0]
|
|
8003976: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800397a: 2b00 cmp r3, #0
|
|
800397c: d00a beq.n 8003994 <HAL_RCCEx_PeriphCLKConfig+0x36c>
|
|
{
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
800397e: 4b65 ldr r3, [pc, #404] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003980: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003984: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
|
|
8003988: 687b ldr r3, [r7, #4]
|
|
800398a: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800398c: 4961 ldr r1, [pc, #388] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800398e: 4313 orrs r3, r2
|
|
8003990: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
8003994: 687b ldr r3, [r7, #4]
|
|
8003996: 681b ldr r3, [r3, #0]
|
|
8003998: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800399c: 2b00 cmp r3, #0
|
|
800399e: d00a beq.n 80039b6 <HAL_RCCEx_PeriphCLKConfig+0x38e>
|
|
{
|
|
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
80039a0: 4b5c ldr r3, [pc, #368] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80039a2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80039a6: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
80039aa: 687b ldr r3, [r7, #4]
|
|
80039ac: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80039ae: 4959 ldr r1, [pc, #356] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80039b0: 4313 orrs r3, r2
|
|
80039b2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
80039b6: 687b ldr r3, [r7, #4]
|
|
80039b8: 681b ldr r3, [r3, #0]
|
|
80039ba: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80039be: 2b00 cmp r3, #0
|
|
80039c0: d00a beq.n 80039d8 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
80039c2: 4b54 ldr r3, [pc, #336] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80039c4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80039c8: f423 5240 bic.w r2, r3, #12288 @ 0x3000
|
|
80039cc: 687b ldr r3, [r7, #4]
|
|
80039ce: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80039d0: 4950 ldr r1, [pc, #320] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80039d2: 4313 orrs r3, r2
|
|
80039d4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(I2C2)
|
|
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
80039d8: 687b ldr r3, [r7, #4]
|
|
80039da: 681b ldr r3, [r3, #0]
|
|
80039dc: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80039e0: 2b00 cmp r3, #0
|
|
80039e2: d00a beq.n 80039fa <HAL_RCCEx_PeriphCLKConfig+0x3d2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
80039e4: 4b4b ldr r3, [pc, #300] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80039e6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80039ea: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
80039ee: 687b ldr r3, [r7, #4]
|
|
80039f0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80039f2: 4948 ldr r1, [pc, #288] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80039f4: 4313 orrs r3, r2
|
|
80039f6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* I2C2 */
|
|
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
80039fa: 687b ldr r3, [r7, #4]
|
|
80039fc: 681b ldr r3, [r3, #0]
|
|
80039fe: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003a02: 2b00 cmp r3, #0
|
|
8003a04: d00a beq.n 8003a1c <HAL_RCCEx_PeriphCLKConfig+0x3f4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
8003a06: 4b43 ldr r3, [pc, #268] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003a08: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003a0c: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
8003a10: 687b ldr r3, [r7, #4]
|
|
8003a12: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003a14: 493f ldr r1, [pc, #252] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003a16: 4313 orrs r3, r2
|
|
8003a18: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* I2C4 */
|
|
|
|
#if defined(USB_OTG_FS) || defined(USB)
|
|
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|
8003a1c: 687b ldr r3, [r7, #4]
|
|
8003a1e: 681b ldr r3, [r3, #0]
|
|
8003a20: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8003a24: 2b00 cmp r3, #0
|
|
8003a26: d028 beq.n 8003a7a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
8003a28: 4b3a ldr r3, [pc, #232] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003a2a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003a2e: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8003a32: 687b ldr r3, [r7, #4]
|
|
8003a34: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8003a36: 4937 ldr r1, [pc, #220] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003a38: 4313 orrs r3, r2
|
|
8003a3a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
|
8003a3e: 687b ldr r3, [r7, #4]
|
|
8003a40: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8003a42: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8003a46: d106 bne.n 8003a56 <HAL_RCCEx_PeriphCLKConfig+0x42e>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8003a48: 4b32 ldr r3, [pc, #200] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003a4a: 68db ldr r3, [r3, #12]
|
|
8003a4c: 4a31 ldr r2, [pc, #196] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003a4e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8003a52: 60d3 str r3, [r2, #12]
|
|
8003a54: e011 b.n 8003a7a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
}
|
|
else
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
|
|
8003a56: 687b ldr r3, [r7, #4]
|
|
8003a58: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8003a5a: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8003a5e: d10c bne.n 8003a7a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8003a60: 687b ldr r3, [r7, #4]
|
|
8003a62: 3304 adds r3, #4
|
|
8003a64: 2101 movs r1, #1
|
|
8003a66: 4618 mov r0, r3
|
|
8003a68: f000 f8c8 bl 8003bfc <RCCEx_PLLSAI1_Config>
|
|
8003a6c: 4603 mov r3, r0
|
|
8003a6e: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8003a70: 7cfb ldrb r3, [r7, #19]
|
|
8003a72: 2b00 cmp r3, #0
|
|
8003a74: d001 beq.n 8003a7a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003a76: 7cfb ldrb r3, [r7, #19]
|
|
8003a78: 74bb strb r3, [r7, #18]
|
|
#endif /* USB_OTG_FS || USB */
|
|
|
|
#if defined(SDMMC1)
|
|
|
|
/*-------------------------- SDMMC1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
|
|
8003a7a: 687b ldr r3, [r7, #4]
|
|
8003a7c: 681b ldr r3, [r3, #0]
|
|
8003a7e: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8003a82: 2b00 cmp r3, #0
|
|
8003a84: d028 beq.n 8003ad8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
|
|
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
|
|
8003a86: 4b23 ldr r3, [pc, #140] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003a88: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003a8c: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8003a90: 687b ldr r3, [r7, #4]
|
|
8003a92: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003a94: 491f ldr r1, [pc, #124] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003a96: 4313 orrs r3, r2
|
|
8003a98: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
|
|
8003a9c: 687b ldr r3, [r7, #4]
|
|
8003a9e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003aa0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8003aa4: d106 bne.n 8003ab4 <HAL_RCCEx_PeriphCLKConfig+0x48c>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8003aa6: 4b1b ldr r3, [pc, #108] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003aa8: 68db ldr r3, [r3, #12]
|
|
8003aaa: 4a1a ldr r2, [pc, #104] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003aac: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8003ab0: 60d3 str r3, [r2, #12]
|
|
8003ab2: e011 b.n 8003ad8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* Enable PLLSAI3CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
}
|
|
#endif
|
|
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
|
|
8003ab4: 687b ldr r3, [r7, #4]
|
|
8003ab6: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003ab8: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8003abc: d10c bne.n 8003ad8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8003abe: 687b ldr r3, [r7, #4]
|
|
8003ac0: 3304 adds r3, #4
|
|
8003ac2: 2101 movs r1, #1
|
|
8003ac4: 4618 mov r0, r3
|
|
8003ac6: f000 f899 bl 8003bfc <RCCEx_PLLSAI1_Config>
|
|
8003aca: 4603 mov r3, r0
|
|
8003acc: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8003ace: 7cfb ldrb r3, [r7, #19]
|
|
8003ad0: 2b00 cmp r3, #0
|
|
8003ad2: d001 beq.n 8003ad8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003ad4: 7cfb ldrb r3, [r7, #19]
|
|
8003ad6: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
#endif /* SDMMC1 */
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
8003ad8: 687b ldr r3, [r7, #4]
|
|
8003ada: 681b ldr r3, [r3, #0]
|
|
8003adc: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8003ae0: 2b00 cmp r3, #0
|
|
8003ae2: d02b beq.n 8003b3c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
8003ae4: 4b0b ldr r3, [pc, #44] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003ae6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003aea: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8003aee: 687b ldr r3, [r7, #4]
|
|
8003af0: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8003af2: 4908 ldr r1, [pc, #32] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003af4: 4313 orrs r3, r2
|
|
8003af6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
8003afa: 687b ldr r3, [r7, #4]
|
|
8003afc: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8003afe: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8003b02: d109 bne.n 8003b18 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8003b04: 4b03 ldr r3, [pc, #12] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003b06: 68db ldr r3, [r3, #12]
|
|
8003b08: 4a02 ldr r2, [pc, #8] @ (8003b14 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8003b0a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8003b0e: 60d3 str r3, [r2, #12]
|
|
8003b10: e014 b.n 8003b3c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
8003b12: bf00 nop
|
|
8003b14: 40021000 .word 0x40021000
|
|
}
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
|
|
8003b18: 687b ldr r3, [r7, #4]
|
|
8003b1a: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8003b1c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8003b20: d10c bne.n 8003b3c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8003b22: 687b ldr r3, [r7, #4]
|
|
8003b24: 3304 adds r3, #4
|
|
8003b26: 2101 movs r1, #1
|
|
8003b28: 4618 mov r0, r3
|
|
8003b2a: f000 f867 bl 8003bfc <RCCEx_PLLSAI1_Config>
|
|
8003b2e: 4603 mov r3, r0
|
|
8003b30: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8003b32: 7cfb ldrb r3, [r7, #19]
|
|
8003b34: 2b00 cmp r3, #0
|
|
8003b36: d001 beq.n 8003b3c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003b38: 7cfb ldrb r3, [r7, #19]
|
|
8003b3a: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
#if !defined(STM32L412xx) && !defined(STM32L422xx)
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8003b3c: 687b ldr r3, [r7, #4]
|
|
8003b3e: 681b ldr r3, [r3, #0]
|
|
8003b40: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8003b44: 2b00 cmp r3, #0
|
|
8003b46: d02f beq.n 8003ba8 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
8003b48: 4b2b ldr r3, [pc, #172] @ (8003bf8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8003b4a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003b4e: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
|
|
8003b52: 687b ldr r3, [r7, #4]
|
|
8003b54: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8003b56: 4928 ldr r1, [pc, #160] @ (8003bf8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8003b58: 4313 orrs r3, r2
|
|
8003b5a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
|
|
8003b5e: 687b ldr r3, [r7, #4]
|
|
8003b60: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8003b62: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8003b66: d10d bne.n 8003b84 <HAL_RCCEx_PeriphCLKConfig+0x55c>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
|
|
8003b68: 687b ldr r3, [r7, #4]
|
|
8003b6a: 3304 adds r3, #4
|
|
8003b6c: 2102 movs r1, #2
|
|
8003b6e: 4618 mov r0, r3
|
|
8003b70: f000 f844 bl 8003bfc <RCCEx_PLLSAI1_Config>
|
|
8003b74: 4603 mov r3, r0
|
|
8003b76: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8003b78: 7cfb ldrb r3, [r7, #19]
|
|
8003b7a: 2b00 cmp r3, #0
|
|
8003b7c: d014 beq.n 8003ba8 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003b7e: 7cfb ldrb r3, [r7, #19]
|
|
8003b80: 74bb strb r3, [r7, #18]
|
|
8003b82: e011 b.n 8003ba8 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
}
|
|
#endif /* RCC_PLLSAI1_SUPPORT */
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
|
|
|
|
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
|
|
8003b84: 687b ldr r3, [r7, #4]
|
|
8003b86: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8003b88: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003b8c: d10c bne.n 8003ba8 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
|
|
8003b8e: 687b ldr r3, [r7, #4]
|
|
8003b90: 3320 adds r3, #32
|
|
8003b92: 2102 movs r1, #2
|
|
8003b94: 4618 mov r0, r3
|
|
8003b96: f000 f925 bl 8003de4 <RCCEx_PLLSAI2_Config>
|
|
8003b9a: 4603 mov r3, r0
|
|
8003b9c: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8003b9e: 7cfb ldrb r3, [r7, #19]
|
|
8003ba0: 2b00 cmp r3, #0
|
|
8003ba2: d001 beq.n 8003ba8 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8003ba4: 7cfb ldrb r3, [r7, #19]
|
|
8003ba6: 74bb strb r3, [r7, #18]
|
|
#endif /* !STM32L412xx && !STM32L422xx */
|
|
|
|
#if defined(SWPMI1)
|
|
|
|
/*-------------------------- SWPMI1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
|
|
8003ba8: 687b ldr r3, [r7, #4]
|
|
8003baa: 681b ldr r3, [r3, #0]
|
|
8003bac: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8003bb0: 2b00 cmp r3, #0
|
|
8003bb2: d00a beq.n 8003bca <HAL_RCCEx_PeriphCLKConfig+0x5a2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
|
|
|
|
/* Configure the SWPMI1 clock source */
|
|
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
|
|
8003bb4: 4b10 ldr r3, [pc, #64] @ (8003bf8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8003bb6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003bba: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000
|
|
8003bbe: 687b ldr r3, [r7, #4]
|
|
8003bc0: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8003bc2: 490d ldr r1, [pc, #52] @ (8003bf8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8003bc4: 4313 orrs r3, r2
|
|
8003bc6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* SWPMI1 */
|
|
|
|
#if defined(DFSDM1_Filter0)
|
|
|
|
/*-------------------------- DFSDM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
|
|
8003bca: 687b ldr r3, [r7, #4]
|
|
8003bcc: 681b ldr r3, [r3, #0]
|
|
8003bce: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8003bd2: 2b00 cmp r3, #0
|
|
8003bd4: d00b beq.n 8003bee <HAL_RCCEx_PeriphCLKConfig+0x5c6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
|
|
|
|
/* Configure the DFSDM1 interface clock source */
|
|
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
|
|
8003bd6: 4b08 ldr r3, [pc, #32] @ (8003bf8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8003bd8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003bdc: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
|
|
8003be0: 687b ldr r3, [r7, #4]
|
|
8003be2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8003be6: 4904 ldr r1, [pc, #16] @ (8003bf8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8003be8: 4313 orrs r3, r2
|
|
8003bea: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
}
|
|
|
|
#endif /* OCTOSPI1 || OCTOSPI2 */
|
|
|
|
return status;
|
|
8003bee: 7cbb ldrb r3, [r7, #18]
|
|
}
|
|
8003bf0: 4618 mov r0, r3
|
|
8003bf2: 3718 adds r7, #24
|
|
8003bf4: 46bd mov sp, r7
|
|
8003bf6: bd80 pop {r7, pc}
|
|
8003bf8: 40021000 .word 0x40021000
|
|
|
|
08003bfc <RCCEx_PLLSAI1_Config>:
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
|
|
{
|
|
8003bfc: b580 push {r7, lr}
|
|
8003bfe: b084 sub sp, #16
|
|
8003c00: af00 add r7, sp, #0
|
|
8003c02: 6078 str r0, [r7, #4]
|
|
8003c04: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003c06: 2300 movs r3, #0
|
|
8003c08: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
|
|
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
|
|
|
|
/* Check that PLLSAI1 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
8003c0a: 4b75 ldr r3, [pc, #468] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003c0c: 68db ldr r3, [r3, #12]
|
|
8003c0e: f003 0303 and.w r3, r3, #3
|
|
8003c12: 2b00 cmp r3, #0
|
|
8003c14: d018 beq.n 8003c48 <RCCEx_PLLSAI1_Config+0x4c>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
|
|
8003c16: 4b72 ldr r3, [pc, #456] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003c18: 68db ldr r3, [r3, #12]
|
|
8003c1a: f003 0203 and.w r2, r3, #3
|
|
8003c1e: 687b ldr r3, [r7, #4]
|
|
8003c20: 681b ldr r3, [r3, #0]
|
|
8003c22: 429a cmp r2, r3
|
|
8003c24: d10d bne.n 8003c42 <RCCEx_PLLSAI1_Config+0x46>
|
|
||
|
|
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
|
|
8003c26: 687b ldr r3, [r7, #4]
|
|
8003c28: 681b ldr r3, [r3, #0]
|
|
||
|
|
8003c2a: 2b00 cmp r3, #0
|
|
8003c2c: d009 beq.n 8003c42 <RCCEx_PLLSAI1_Config+0x46>
|
|
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
|
|
8003c2e: 4b6c ldr r3, [pc, #432] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003c30: 68db ldr r3, [r3, #12]
|
|
8003c32: 091b lsrs r3, r3, #4
|
|
8003c34: f003 0307 and.w r3, r3, #7
|
|
8003c38: 1c5a adds r2, r3, #1
|
|
8003c3a: 687b ldr r3, [r7, #4]
|
|
8003c3c: 685b ldr r3, [r3, #4]
|
|
||
|
|
8003c3e: 429a cmp r2, r3
|
|
8003c40: d047 beq.n 8003cd2 <RCCEx_PLLSAI1_Config+0xd6>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
8003c42: 2301 movs r3, #1
|
|
8003c44: 73fb strb r3, [r7, #15]
|
|
8003c46: e044 b.n 8003cd2 <RCCEx_PLLSAI1_Config+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI1 clock source availability */
|
|
switch(PllSai1->PLLSAI1Source)
|
|
8003c48: 687b ldr r3, [r7, #4]
|
|
8003c4a: 681b ldr r3, [r3, #0]
|
|
8003c4c: 2b03 cmp r3, #3
|
|
8003c4e: d018 beq.n 8003c82 <RCCEx_PLLSAI1_Config+0x86>
|
|
8003c50: 2b03 cmp r3, #3
|
|
8003c52: d825 bhi.n 8003ca0 <RCCEx_PLLSAI1_Config+0xa4>
|
|
8003c54: 2b01 cmp r3, #1
|
|
8003c56: d002 beq.n 8003c5e <RCCEx_PLLSAI1_Config+0x62>
|
|
8003c58: 2b02 cmp r3, #2
|
|
8003c5a: d009 beq.n 8003c70 <RCCEx_PLLSAI1_Config+0x74>
|
|
8003c5c: e020 b.n 8003ca0 <RCCEx_PLLSAI1_Config+0xa4>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
8003c5e: 4b60 ldr r3, [pc, #384] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003c60: 681b ldr r3, [r3, #0]
|
|
8003c62: f003 0302 and.w r3, r3, #2
|
|
8003c66: 2b00 cmp r3, #0
|
|
8003c68: d11d bne.n 8003ca6 <RCCEx_PLLSAI1_Config+0xaa>
|
|
{
|
|
status = HAL_ERROR;
|
|
8003c6a: 2301 movs r3, #1
|
|
8003c6c: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8003c6e: e01a b.n 8003ca6 <RCCEx_PLLSAI1_Config+0xaa>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8003c70: 4b5b ldr r3, [pc, #364] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003c72: 681b ldr r3, [r3, #0]
|
|
8003c74: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003c78: 2b00 cmp r3, #0
|
|
8003c7a: d116 bne.n 8003caa <RCCEx_PLLSAI1_Config+0xae>
|
|
{
|
|
status = HAL_ERROR;
|
|
8003c7c: 2301 movs r3, #1
|
|
8003c7e: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8003c80: e013 b.n 8003caa <RCCEx_PLLSAI1_Config+0xae>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8003c82: 4b57 ldr r3, [pc, #348] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003c84: 681b ldr r3, [r3, #0]
|
|
8003c86: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003c8a: 2b00 cmp r3, #0
|
|
8003c8c: d10f bne.n 8003cae <RCCEx_PLLSAI1_Config+0xb2>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
8003c8e: 4b54 ldr r3, [pc, #336] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003c90: 681b ldr r3, [r3, #0]
|
|
8003c92: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8003c96: 2b00 cmp r3, #0
|
|
8003c98: d109 bne.n 8003cae <RCCEx_PLLSAI1_Config+0xb2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8003c9a: 2301 movs r3, #1
|
|
8003c9c: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8003c9e: e006 b.n 8003cae <RCCEx_PLLSAI1_Config+0xb2>
|
|
default:
|
|
status = HAL_ERROR;
|
|
8003ca0: 2301 movs r3, #1
|
|
8003ca2: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8003ca4: e004 b.n 8003cb0 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8003ca6: bf00 nop
|
|
8003ca8: e002 b.n 8003cb0 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8003caa: bf00 nop
|
|
8003cac: e000 b.n 8003cb0 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8003cae: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8003cb0: 7bfb ldrb r3, [r7, #15]
|
|
8003cb2: 2b00 cmp r3, #0
|
|
8003cb4: d10d bne.n 8003cd2 <RCCEx_PLLSAI1_Config+0xd6>
|
|
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI1 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
|
|
#else
|
|
/* Set PLLSAI1 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
8003cb6: 4b4a ldr r3, [pc, #296] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003cb8: 68db ldr r3, [r3, #12]
|
|
8003cba: f023 0273 bic.w r2, r3, #115 @ 0x73
|
|
8003cbe: 687b ldr r3, [r7, #4]
|
|
8003cc0: 6819 ldr r1, [r3, #0]
|
|
8003cc2: 687b ldr r3, [r7, #4]
|
|
8003cc4: 685b ldr r3, [r3, #4]
|
|
8003cc6: 3b01 subs r3, #1
|
|
8003cc8: 011b lsls r3, r3, #4
|
|
8003cca: 430b orrs r3, r1
|
|
8003ccc: 4944 ldr r1, [pc, #272] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003cce: 4313 orrs r3, r2
|
|
8003cd0: 60cb str r3, [r1, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8003cd2: 7bfb ldrb r3, [r7, #15]
|
|
8003cd4: 2b00 cmp r3, #0
|
|
8003cd6: d17d bne.n 8003dd4 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
/* Disable the PLLSAI1 */
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
8003cd8: 4b41 ldr r3, [pc, #260] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003cda: 681b ldr r3, [r3, #0]
|
|
8003cdc: 4a40 ldr r2, [pc, #256] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003cde: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8003ce2: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003ce4: f7fd fd64 bl 80017b0 <HAL_GetTick>
|
|
8003ce8: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
8003cea: e009 b.n 8003d00 <RCCEx_PLLSAI1_Config+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
8003cec: f7fd fd60 bl 80017b0 <HAL_GetTick>
|
|
8003cf0: 4602 mov r2, r0
|
|
8003cf2: 68bb ldr r3, [r7, #8]
|
|
8003cf4: 1ad3 subs r3, r2, r3
|
|
8003cf6: 2b02 cmp r3, #2
|
|
8003cf8: d902 bls.n 8003d00 <RCCEx_PLLSAI1_Config+0x104>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8003cfa: 2303 movs r3, #3
|
|
8003cfc: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8003cfe: e005 b.n 8003d0c <RCCEx_PLLSAI1_Config+0x110>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
8003d00: 4b37 ldr r3, [pc, #220] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d02: 681b ldr r3, [r3, #0]
|
|
8003d04: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8003d08: 2b00 cmp r3, #0
|
|
8003d0a: d1ef bne.n 8003cec <RCCEx_PLLSAI1_Config+0xf0>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8003d0c: 7bfb ldrb r3, [r7, #15]
|
|
8003d0e: 2b00 cmp r3, #0
|
|
8003d10: d160 bne.n 8003dd4 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
8003d12: 683b ldr r3, [r7, #0]
|
|
8003d14: 2b00 cmp r3, #0
|
|
8003d16: d111 bne.n 8003d3c <RCCEx_PLLSAI1_Config+0x140>
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8003d18: 4b31 ldr r3, [pc, #196] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d1a: 691b ldr r3, [r3, #16]
|
|
8003d1c: f423 331f bic.w r3, r3, #162816 @ 0x27c00
|
|
8003d20: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8003d24: 687a ldr r2, [r7, #4]
|
|
8003d26: 6892 ldr r2, [r2, #8]
|
|
8003d28: 0211 lsls r1, r2, #8
|
|
8003d2a: 687a ldr r2, [r7, #4]
|
|
8003d2c: 68d2 ldr r2, [r2, #12]
|
|
8003d2e: 0912 lsrs r2, r2, #4
|
|
8003d30: 0452 lsls r2, r2, #17
|
|
8003d32: 430a orrs r2, r1
|
|
8003d34: 492a ldr r1, [pc, #168] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d36: 4313 orrs r3, r2
|
|
8003d38: 610b str r3, [r1, #16]
|
|
8003d3a: e027 b.n 8003d8c <RCCEx_PLLSAI1_Config+0x190>
|
|
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
|
|
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
else if(Divider == DIVIDER_Q_UPDATE)
|
|
8003d3c: 683b ldr r3, [r7, #0]
|
|
8003d3e: 2b01 cmp r3, #1
|
|
8003d40: d112 bne.n 8003d68 <RCCEx_PLLSAI1_Config+0x16c>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8003d42: 4b27 ldr r3, [pc, #156] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d44: 691b ldr r3, [r3, #16]
|
|
8003d46: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000
|
|
8003d4a: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8003d4e: 687a ldr r2, [r7, #4]
|
|
8003d50: 6892 ldr r2, [r2, #8]
|
|
8003d52: 0211 lsls r1, r2, #8
|
|
8003d54: 687a ldr r2, [r7, #4]
|
|
8003d56: 6912 ldr r2, [r2, #16]
|
|
8003d58: 0852 lsrs r2, r2, #1
|
|
8003d5a: 3a01 subs r2, #1
|
|
8003d5c: 0552 lsls r2, r2, #21
|
|
8003d5e: 430a orrs r2, r1
|
|
8003d60: 491f ldr r1, [pc, #124] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d62: 4313 orrs r3, r2
|
|
8003d64: 610b str r3, [r1, #16]
|
|
8003d66: e011 b.n 8003d8c <RCCEx_PLLSAI1_Config+0x190>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8003d68: 4b1d ldr r3, [pc, #116] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d6a: 691b ldr r3, [r3, #16]
|
|
8003d6c: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
|
|
8003d70: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8003d74: 687a ldr r2, [r7, #4]
|
|
8003d76: 6892 ldr r2, [r2, #8]
|
|
8003d78: 0211 lsls r1, r2, #8
|
|
8003d7a: 687a ldr r2, [r7, #4]
|
|
8003d7c: 6952 ldr r2, [r2, #20]
|
|
8003d7e: 0852 lsrs r2, r2, #1
|
|
8003d80: 3a01 subs r2, #1
|
|
8003d82: 0652 lsls r2, r2, #25
|
|
8003d84: 430a orrs r2, r1
|
|
8003d86: 4916 ldr r1, [pc, #88] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d88: 4313 orrs r3, r2
|
|
8003d8a: 610b str r3, [r1, #16]
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
8003d8c: 4b14 ldr r3, [pc, #80] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d8e: 681b ldr r3, [r3, #0]
|
|
8003d90: 4a13 ldr r2, [pc, #76] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003d92: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
8003d96: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003d98: f7fd fd0a bl 80017b0 <HAL_GetTick>
|
|
8003d9c: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
8003d9e: e009 b.n 8003db4 <RCCEx_PLLSAI1_Config+0x1b8>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
8003da0: f7fd fd06 bl 80017b0 <HAL_GetTick>
|
|
8003da4: 4602 mov r2, r0
|
|
8003da6: 68bb ldr r3, [r7, #8]
|
|
8003da8: 1ad3 subs r3, r2, r3
|
|
8003daa: 2b02 cmp r3, #2
|
|
8003dac: d902 bls.n 8003db4 <RCCEx_PLLSAI1_Config+0x1b8>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8003dae: 2303 movs r3, #3
|
|
8003db0: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8003db2: e005 b.n 8003dc0 <RCCEx_PLLSAI1_Config+0x1c4>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
8003db4: 4b0a ldr r3, [pc, #40] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003db6: 681b ldr r3, [r3, #0]
|
|
8003db8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8003dbc: 2b00 cmp r3, #0
|
|
8003dbe: d0ef beq.n 8003da0 <RCCEx_PLLSAI1_Config+0x1a4>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8003dc0: 7bfb ldrb r3, [r7, #15]
|
|
8003dc2: 2b00 cmp r3, #0
|
|
8003dc4: d106 bne.n 8003dd4 <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
|
|
8003dc6: 4b06 ldr r3, [pc, #24] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003dc8: 691a ldr r2, [r3, #16]
|
|
8003dca: 687b ldr r3, [r7, #4]
|
|
8003dcc: 699b ldr r3, [r3, #24]
|
|
8003dce: 4904 ldr r1, [pc, #16] @ (8003de0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8003dd0: 4313 orrs r3, r2
|
|
8003dd2: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8003dd4: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8003dd6: 4618 mov r0, r3
|
|
8003dd8: 3710 adds r7, #16
|
|
8003dda: 46bd mov sp, r7
|
|
8003ddc: bd80 pop {r7, pc}
|
|
8003dde: bf00 nop
|
|
8003de0: 40021000 .word 0x40021000
|
|
|
|
08003de4 <RCCEx_PLLSAI2_Config>:
|
|
* @note PLLSAI2 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
|
|
{
|
|
8003de4: b580 push {r7, lr}
|
|
8003de6: b084 sub sp, #16
|
|
8003de8: af00 add r7, sp, #0
|
|
8003dea: 6078 str r0, [r7, #4]
|
|
8003dec: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003dee: 2300 movs r3, #0
|
|
8003df0: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
|
|
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
|
|
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
|
|
|
|
/* Check that PLLSAI2 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
8003df2: 4b6a ldr r3, [pc, #424] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003df4: 68db ldr r3, [r3, #12]
|
|
8003df6: f003 0303 and.w r3, r3, #3
|
|
8003dfa: 2b00 cmp r3, #0
|
|
8003dfc: d018 beq.n 8003e30 <RCCEx_PLLSAI2_Config+0x4c>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
|
|
8003dfe: 4b67 ldr r3, [pc, #412] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003e00: 68db ldr r3, [r3, #12]
|
|
8003e02: f003 0203 and.w r2, r3, #3
|
|
8003e06: 687b ldr r3, [r7, #4]
|
|
8003e08: 681b ldr r3, [r3, #0]
|
|
8003e0a: 429a cmp r2, r3
|
|
8003e0c: d10d bne.n 8003e2a <RCCEx_PLLSAI2_Config+0x46>
|
|
||
|
|
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
|
|
8003e0e: 687b ldr r3, [r7, #4]
|
|
8003e10: 681b ldr r3, [r3, #0]
|
|
||
|
|
8003e12: 2b00 cmp r3, #0
|
|
8003e14: d009 beq.n 8003e2a <RCCEx_PLLSAI2_Config+0x46>
|
|
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
|
|
8003e16: 4b61 ldr r3, [pc, #388] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003e18: 68db ldr r3, [r3, #12]
|
|
8003e1a: 091b lsrs r3, r3, #4
|
|
8003e1c: f003 0307 and.w r3, r3, #7
|
|
8003e20: 1c5a adds r2, r3, #1
|
|
8003e22: 687b ldr r3, [r7, #4]
|
|
8003e24: 685b ldr r3, [r3, #4]
|
|
||
|
|
8003e26: 429a cmp r2, r3
|
|
8003e28: d047 beq.n 8003eba <RCCEx_PLLSAI2_Config+0xd6>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
8003e2a: 2301 movs r3, #1
|
|
8003e2c: 73fb strb r3, [r7, #15]
|
|
8003e2e: e044 b.n 8003eba <RCCEx_PLLSAI2_Config+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI2 clock source availability */
|
|
switch(PllSai2->PLLSAI2Source)
|
|
8003e30: 687b ldr r3, [r7, #4]
|
|
8003e32: 681b ldr r3, [r3, #0]
|
|
8003e34: 2b03 cmp r3, #3
|
|
8003e36: d018 beq.n 8003e6a <RCCEx_PLLSAI2_Config+0x86>
|
|
8003e38: 2b03 cmp r3, #3
|
|
8003e3a: d825 bhi.n 8003e88 <RCCEx_PLLSAI2_Config+0xa4>
|
|
8003e3c: 2b01 cmp r3, #1
|
|
8003e3e: d002 beq.n 8003e46 <RCCEx_PLLSAI2_Config+0x62>
|
|
8003e40: 2b02 cmp r3, #2
|
|
8003e42: d009 beq.n 8003e58 <RCCEx_PLLSAI2_Config+0x74>
|
|
8003e44: e020 b.n 8003e88 <RCCEx_PLLSAI2_Config+0xa4>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
8003e46: 4b55 ldr r3, [pc, #340] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003e48: 681b ldr r3, [r3, #0]
|
|
8003e4a: f003 0302 and.w r3, r3, #2
|
|
8003e4e: 2b00 cmp r3, #0
|
|
8003e50: d11d bne.n 8003e8e <RCCEx_PLLSAI2_Config+0xaa>
|
|
{
|
|
status = HAL_ERROR;
|
|
8003e52: 2301 movs r3, #1
|
|
8003e54: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8003e56: e01a b.n 8003e8e <RCCEx_PLLSAI2_Config+0xaa>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8003e58: 4b50 ldr r3, [pc, #320] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003e5a: 681b ldr r3, [r3, #0]
|
|
8003e5c: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003e60: 2b00 cmp r3, #0
|
|
8003e62: d116 bne.n 8003e92 <RCCEx_PLLSAI2_Config+0xae>
|
|
{
|
|
status = HAL_ERROR;
|
|
8003e64: 2301 movs r3, #1
|
|
8003e66: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8003e68: e013 b.n 8003e92 <RCCEx_PLLSAI2_Config+0xae>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8003e6a: 4b4c ldr r3, [pc, #304] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003e6c: 681b ldr r3, [r3, #0]
|
|
8003e6e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003e72: 2b00 cmp r3, #0
|
|
8003e74: d10f bne.n 8003e96 <RCCEx_PLLSAI2_Config+0xb2>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
8003e76: 4b49 ldr r3, [pc, #292] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003e78: 681b ldr r3, [r3, #0]
|
|
8003e7a: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8003e7e: 2b00 cmp r3, #0
|
|
8003e80: d109 bne.n 8003e96 <RCCEx_PLLSAI2_Config+0xb2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8003e82: 2301 movs r3, #1
|
|
8003e84: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8003e86: e006 b.n 8003e96 <RCCEx_PLLSAI2_Config+0xb2>
|
|
default:
|
|
status = HAL_ERROR;
|
|
8003e88: 2301 movs r3, #1
|
|
8003e8a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8003e8c: e004 b.n 8003e98 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8003e8e: bf00 nop
|
|
8003e90: e002 b.n 8003e98 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8003e92: bf00 nop
|
|
8003e94: e000 b.n 8003e98 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8003e96: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8003e98: 7bfb ldrb r3, [r7, #15]
|
|
8003e9a: 2b00 cmp r3, #0
|
|
8003e9c: d10d bne.n 8003eba <RCCEx_PLLSAI2_Config+0xd6>
|
|
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI2 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
|
|
#else
|
|
/* Set PLLSAI2 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
8003e9e: 4b3f ldr r3, [pc, #252] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003ea0: 68db ldr r3, [r3, #12]
|
|
8003ea2: f023 0273 bic.w r2, r3, #115 @ 0x73
|
|
8003ea6: 687b ldr r3, [r7, #4]
|
|
8003ea8: 6819 ldr r1, [r3, #0]
|
|
8003eaa: 687b ldr r3, [r7, #4]
|
|
8003eac: 685b ldr r3, [r3, #4]
|
|
8003eae: 3b01 subs r3, #1
|
|
8003eb0: 011b lsls r3, r3, #4
|
|
8003eb2: 430b orrs r3, r1
|
|
8003eb4: 4939 ldr r1, [pc, #228] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003eb6: 4313 orrs r3, r2
|
|
8003eb8: 60cb str r3, [r1, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8003eba: 7bfb ldrb r3, [r7, #15]
|
|
8003ebc: 2b00 cmp r3, #0
|
|
8003ebe: d167 bne.n 8003f90 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
/* Disable the PLLSAI2 */
|
|
__HAL_RCC_PLLSAI2_DISABLE();
|
|
8003ec0: 4b36 ldr r3, [pc, #216] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003ec2: 681b ldr r3, [r3, #0]
|
|
8003ec4: 4a35 ldr r2, [pc, #212] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003ec6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8003eca: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003ecc: f7fd fc70 bl 80017b0 <HAL_GetTick>
|
|
8003ed0: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
8003ed2: e009 b.n 8003ee8 <RCCEx_PLLSAI2_Config+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
8003ed4: f7fd fc6c bl 80017b0 <HAL_GetTick>
|
|
8003ed8: 4602 mov r2, r0
|
|
8003eda: 68bb ldr r3, [r7, #8]
|
|
8003edc: 1ad3 subs r3, r2, r3
|
|
8003ede: 2b02 cmp r3, #2
|
|
8003ee0: d902 bls.n 8003ee8 <RCCEx_PLLSAI2_Config+0x104>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8003ee2: 2303 movs r3, #3
|
|
8003ee4: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8003ee6: e005 b.n 8003ef4 <RCCEx_PLLSAI2_Config+0x110>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
8003ee8: 4b2c ldr r3, [pc, #176] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003eea: 681b ldr r3, [r3, #0]
|
|
8003eec: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8003ef0: 2b00 cmp r3, #0
|
|
8003ef2: d1ef bne.n 8003ed4 <RCCEx_PLLSAI2_Config+0xf0>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8003ef4: 7bfb ldrb r3, [r7, #15]
|
|
8003ef6: 2b00 cmp r3, #0
|
|
8003ef8: d14a bne.n 8003f90 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
8003efa: 683b ldr r3, [r7, #0]
|
|
8003efc: 2b00 cmp r3, #0
|
|
8003efe: d111 bne.n 8003f24 <RCCEx_PLLSAI2_Config+0x140>
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
8003f00: 4b26 ldr r3, [pc, #152] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f02: 695b ldr r3, [r3, #20]
|
|
8003f04: f423 331f bic.w r3, r3, #162816 @ 0x27c00
|
|
8003f08: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8003f0c: 687a ldr r2, [r7, #4]
|
|
8003f0e: 6892 ldr r2, [r2, #8]
|
|
8003f10: 0211 lsls r1, r2, #8
|
|
8003f12: 687a ldr r2, [r7, #4]
|
|
8003f14: 68d2 ldr r2, [r2, #12]
|
|
8003f16: 0912 lsrs r2, r2, #4
|
|
8003f18: 0452 lsls r2, r2, #17
|
|
8003f1a: 430a orrs r2, r1
|
|
8003f1c: 491f ldr r1, [pc, #124] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f1e: 4313 orrs r3, r2
|
|
8003f20: 614b str r3, [r1, #20]
|
|
8003f22: e011 b.n 8003f48 <RCCEx_PLLSAI2_Config+0x164>
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
|
|
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
8003f24: 4b1d ldr r3, [pc, #116] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f26: 695b ldr r3, [r3, #20]
|
|
8003f28: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
|
|
8003f2c: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8003f30: 687a ldr r2, [r7, #4]
|
|
8003f32: 6892 ldr r2, [r2, #8]
|
|
8003f34: 0211 lsls r1, r2, #8
|
|
8003f36: 687a ldr r2, [r7, #4]
|
|
8003f38: 6912 ldr r2, [r2, #16]
|
|
8003f3a: 0852 lsrs r2, r2, #1
|
|
8003f3c: 3a01 subs r2, #1
|
|
8003f3e: 0652 lsls r2, r2, #25
|
|
8003f40: 430a orrs r2, r1
|
|
8003f42: 4916 ldr r1, [pc, #88] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f44: 4313 orrs r3, r2
|
|
8003f46: 614b str r3, [r1, #20]
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
|
|
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
|
|
__HAL_RCC_PLLSAI2_ENABLE();
|
|
8003f48: 4b14 ldr r3, [pc, #80] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f4a: 681b ldr r3, [r3, #0]
|
|
8003f4c: 4a13 ldr r2, [pc, #76] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f4e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003f52: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003f54: f7fd fc2c bl 80017b0 <HAL_GetTick>
|
|
8003f58: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
8003f5a: e009 b.n 8003f70 <RCCEx_PLLSAI2_Config+0x18c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
8003f5c: f7fd fc28 bl 80017b0 <HAL_GetTick>
|
|
8003f60: 4602 mov r2, r0
|
|
8003f62: 68bb ldr r3, [r7, #8]
|
|
8003f64: 1ad3 subs r3, r2, r3
|
|
8003f66: 2b02 cmp r3, #2
|
|
8003f68: d902 bls.n 8003f70 <RCCEx_PLLSAI2_Config+0x18c>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8003f6a: 2303 movs r3, #3
|
|
8003f6c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8003f6e: e005 b.n 8003f7c <RCCEx_PLLSAI2_Config+0x198>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
8003f70: 4b0a ldr r3, [pc, #40] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f72: 681b ldr r3, [r3, #0]
|
|
8003f74: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8003f78: 2b00 cmp r3, #0
|
|
8003f7a: d0ef beq.n 8003f5c <RCCEx_PLLSAI2_Config+0x178>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8003f7c: 7bfb ldrb r3, [r7, #15]
|
|
8003f7e: 2b00 cmp r3, #0
|
|
8003f80: d106 bne.n 8003f90 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
/* Configure the PLLSAI2 Clock output(s) */
|
|
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
|
|
8003f82: 4b06 ldr r3, [pc, #24] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f84: 695a ldr r2, [r3, #20]
|
|
8003f86: 687b ldr r3, [r7, #4]
|
|
8003f88: 695b ldr r3, [r3, #20]
|
|
8003f8a: 4904 ldr r1, [pc, #16] @ (8003f9c <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8003f8c: 4313 orrs r3, r2
|
|
8003f8e: 614b str r3, [r1, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8003f90: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8003f92: 4618 mov r0, r3
|
|
8003f94: 3710 adds r7, #16
|
|
8003f96: 46bd mov sp, r7
|
|
8003f98: bd80 pop {r7, pc}
|
|
8003f9a: bf00 nop
|
|
8003f9c: 40021000 .word 0x40021000
|
|
|
|
08003fa0 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8003fa0: b580 push {r7, lr}
|
|
8003fa2: b082 sub sp, #8
|
|
8003fa4: af00 add r7, sp, #0
|
|
8003fa6: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8003fa8: 687b ldr r3, [r7, #4]
|
|
8003faa: 2b00 cmp r3, #0
|
|
8003fac: d101 bne.n 8003fb2 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003fae: 2301 movs r3, #1
|
|
8003fb0: e040 b.n 8004034 <HAL_UART_Init+0x94>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8003fb2: 687b ldr r3, [r7, #4]
|
|
8003fb4: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8003fb6: 2b00 cmp r3, #0
|
|
8003fb8: d106 bne.n 8003fc8 <HAL_UART_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8003fba: 687b ldr r3, [r7, #4]
|
|
8003fbc: 2200 movs r2, #0
|
|
8003fbe: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8003fc2: 6878 ldr r0, [r7, #4]
|
|
8003fc4: f7fd f9fc bl 80013c0 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8003fc8: 687b ldr r3, [r7, #4]
|
|
8003fca: 2224 movs r2, #36 @ 0x24
|
|
8003fcc: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
8003fce: 687b ldr r3, [r7, #4]
|
|
8003fd0: 681b ldr r3, [r3, #0]
|
|
8003fd2: 681a ldr r2, [r3, #0]
|
|
8003fd4: 687b ldr r3, [r7, #4]
|
|
8003fd6: 681b ldr r3, [r3, #0]
|
|
8003fd8: f022 0201 bic.w r2, r2, #1
|
|
8003fdc: 601a str r2, [r3, #0]
|
|
|
|
/* Perform advanced settings configuration */
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
8003fde: 687b ldr r3, [r7, #4]
|
|
8003fe0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003fe2: 2b00 cmp r3, #0
|
|
8003fe4: d002 beq.n 8003fec <HAL_UART_Init+0x4c>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
8003fe6: 6878 ldr r0, [r7, #4]
|
|
8003fe8: f000 fb6a bl 80046c0 <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
8003fec: 6878 ldr r0, [r7, #4]
|
|
8003fee: f000 f8af bl 8004150 <UART_SetConfig>
|
|
8003ff2: 4603 mov r3, r0
|
|
8003ff4: 2b01 cmp r3, #1
|
|
8003ff6: d101 bne.n 8003ffc <HAL_UART_Init+0x5c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ff8: 2301 movs r3, #1
|
|
8003ffa: e01b b.n 8004034 <HAL_UART_Init+0x94>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8003ffc: 687b ldr r3, [r7, #4]
|
|
8003ffe: 681b ldr r3, [r3, #0]
|
|
8004000: 685a ldr r2, [r3, #4]
|
|
8004002: 687b ldr r3, [r7, #4]
|
|
8004004: 681b ldr r3, [r3, #0]
|
|
8004006: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
800400a: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
800400c: 687b ldr r3, [r7, #4]
|
|
800400e: 681b ldr r3, [r3, #0]
|
|
8004010: 689a ldr r2, [r3, #8]
|
|
8004012: 687b ldr r3, [r7, #4]
|
|
8004014: 681b ldr r3, [r3, #0]
|
|
8004016: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
800401a: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
800401c: 687b ldr r3, [r7, #4]
|
|
800401e: 681b ldr r3, [r3, #0]
|
|
8004020: 681a ldr r2, [r3, #0]
|
|
8004022: 687b ldr r3, [r7, #4]
|
|
8004024: 681b ldr r3, [r3, #0]
|
|
8004026: f042 0201 orr.w r2, r2, #1
|
|
800402a: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
800402c: 6878 ldr r0, [r7, #4]
|
|
800402e: f000 fbe9 bl 8004804 <UART_CheckIdleState>
|
|
8004032: 4603 mov r3, r0
|
|
}
|
|
8004034: 4618 mov r0, r3
|
|
8004036: 3708 adds r7, #8
|
|
8004038: 46bd mov sp, r7
|
|
800403a: bd80 pop {r7, pc}
|
|
|
|
0800403c <HAL_UART_Transmit>:
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
* @param Timeout Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
800403c: b580 push {r7, lr}
|
|
800403e: b08a sub sp, #40 @ 0x28
|
|
8004040: af02 add r7, sp, #8
|
|
8004042: 60f8 str r0, [r7, #12]
|
|
8004044: 60b9 str r1, [r7, #8]
|
|
8004046: 603b str r3, [r7, #0]
|
|
8004048: 4613 mov r3, r2
|
|
800404a: 80fb strh r3, [r7, #6]
|
|
const uint8_t *pdata8bits;
|
|
const uint16_t *pdata16bits;
|
|
uint32_t tickstart;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
800404c: 68fb ldr r3, [r7, #12]
|
|
800404e: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8004050: 2b20 cmp r3, #32
|
|
8004052: d177 bne.n 8004144 <HAL_UART_Transmit+0x108>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004054: 68bb ldr r3, [r7, #8]
|
|
8004056: 2b00 cmp r3, #0
|
|
8004058: d002 beq.n 8004060 <HAL_UART_Transmit+0x24>
|
|
800405a: 88fb ldrh r3, [r7, #6]
|
|
800405c: 2b00 cmp r3, #0
|
|
800405e: d101 bne.n 8004064 <HAL_UART_Transmit+0x28>
|
|
{
|
|
return HAL_ERROR;
|
|
8004060: 2301 movs r3, #1
|
|
8004062: e070 b.n 8004146 <HAL_UART_Transmit+0x10a>
|
|
}
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004064: 68fb ldr r3, [r7, #12]
|
|
8004066: 2200 movs r2, #0
|
|
8004068: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
800406c: 68fb ldr r3, [r7, #12]
|
|
800406e: 2221 movs r2, #33 @ 0x21
|
|
8004070: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8004072: f7fd fb9d bl 80017b0 <HAL_GetTick>
|
|
8004076: 6178 str r0, [r7, #20]
|
|
|
|
huart->TxXferSize = Size;
|
|
8004078: 68fb ldr r3, [r7, #12]
|
|
800407a: 88fa ldrh r2, [r7, #6]
|
|
800407c: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
|
|
huart->TxXferCount = Size;
|
|
8004080: 68fb ldr r3, [r7, #12]
|
|
8004082: 88fa ldrh r2, [r7, #6]
|
|
8004084: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8004088: 68fb ldr r3, [r7, #12]
|
|
800408a: 689b ldr r3, [r3, #8]
|
|
800408c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8004090: d108 bne.n 80040a4 <HAL_UART_Transmit+0x68>
|
|
8004092: 68fb ldr r3, [r7, #12]
|
|
8004094: 691b ldr r3, [r3, #16]
|
|
8004096: 2b00 cmp r3, #0
|
|
8004098: d104 bne.n 80040a4 <HAL_UART_Transmit+0x68>
|
|
{
|
|
pdata8bits = NULL;
|
|
800409a: 2300 movs r3, #0
|
|
800409c: 61fb str r3, [r7, #28]
|
|
pdata16bits = (const uint16_t *) pData;
|
|
800409e: 68bb ldr r3, [r7, #8]
|
|
80040a0: 61bb str r3, [r7, #24]
|
|
80040a2: e003 b.n 80040ac <HAL_UART_Transmit+0x70>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
80040a4: 68bb ldr r3, [r7, #8]
|
|
80040a6: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
80040a8: 2300 movs r3, #0
|
|
80040aa: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
80040ac: e02f b.n 800410e <HAL_UART_Transmit+0xd2>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
80040ae: 683b ldr r3, [r7, #0]
|
|
80040b0: 9300 str r3, [sp, #0]
|
|
80040b2: 697b ldr r3, [r7, #20]
|
|
80040b4: 2200 movs r2, #0
|
|
80040b6: 2180 movs r1, #128 @ 0x80
|
|
80040b8: 68f8 ldr r0, [r7, #12]
|
|
80040ba: f000 fc4b bl 8004954 <UART_WaitOnFlagUntilTimeout>
|
|
80040be: 4603 mov r3, r0
|
|
80040c0: 2b00 cmp r3, #0
|
|
80040c2: d004 beq.n 80040ce <HAL_UART_Transmit+0x92>
|
|
{
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80040c4: 68fb ldr r3, [r7, #12]
|
|
80040c6: 2220 movs r2, #32
|
|
80040c8: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_TIMEOUT;
|
|
80040ca: 2303 movs r3, #3
|
|
80040cc: e03b b.n 8004146 <HAL_UART_Transmit+0x10a>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
80040ce: 69fb ldr r3, [r7, #28]
|
|
80040d0: 2b00 cmp r3, #0
|
|
80040d2: d10b bne.n 80040ec <HAL_UART_Transmit+0xb0>
|
|
{
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
80040d4: 69bb ldr r3, [r7, #24]
|
|
80040d6: 881a ldrh r2, [r3, #0]
|
|
80040d8: 68fb ldr r3, [r7, #12]
|
|
80040da: 681b ldr r3, [r3, #0]
|
|
80040dc: f3c2 0208 ubfx r2, r2, #0, #9
|
|
80040e0: b292 uxth r2, r2
|
|
80040e2: 851a strh r2, [r3, #40] @ 0x28
|
|
pdata16bits++;
|
|
80040e4: 69bb ldr r3, [r7, #24]
|
|
80040e6: 3302 adds r3, #2
|
|
80040e8: 61bb str r3, [r7, #24]
|
|
80040ea: e007 b.n 80040fc <HAL_UART_Transmit+0xc0>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
80040ec: 69fb ldr r3, [r7, #28]
|
|
80040ee: 781a ldrb r2, [r3, #0]
|
|
80040f0: 68fb ldr r3, [r7, #12]
|
|
80040f2: 681b ldr r3, [r3, #0]
|
|
80040f4: 851a strh r2, [r3, #40] @ 0x28
|
|
pdata8bits++;
|
|
80040f6: 69fb ldr r3, [r7, #28]
|
|
80040f8: 3301 adds r3, #1
|
|
80040fa: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->TxXferCount--;
|
|
80040fc: 68fb ldr r3, [r7, #12]
|
|
80040fe: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8004102: b29b uxth r3, r3
|
|
8004104: 3b01 subs r3, #1
|
|
8004106: b29a uxth r2, r3
|
|
8004108: 68fb ldr r3, [r7, #12]
|
|
800410a: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
while (huart->TxXferCount > 0U)
|
|
800410e: 68fb ldr r3, [r7, #12]
|
|
8004110: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8004114: b29b uxth r3, r3
|
|
8004116: 2b00 cmp r3, #0
|
|
8004118: d1c9 bne.n 80040ae <HAL_UART_Transmit+0x72>
|
|
}
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
800411a: 683b ldr r3, [r7, #0]
|
|
800411c: 9300 str r3, [sp, #0]
|
|
800411e: 697b ldr r3, [r7, #20]
|
|
8004120: 2200 movs r2, #0
|
|
8004122: 2140 movs r1, #64 @ 0x40
|
|
8004124: 68f8 ldr r0, [r7, #12]
|
|
8004126: f000 fc15 bl 8004954 <UART_WaitOnFlagUntilTimeout>
|
|
800412a: 4603 mov r3, r0
|
|
800412c: 2b00 cmp r3, #0
|
|
800412e: d004 beq.n 800413a <HAL_UART_Transmit+0xfe>
|
|
{
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004130: 68fb ldr r3, [r7, #12]
|
|
8004132: 2220 movs r2, #32
|
|
8004134: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_TIMEOUT;
|
|
8004136: 2303 movs r3, #3
|
|
8004138: e005 b.n 8004146 <HAL_UART_Transmit+0x10a>
|
|
}
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800413a: 68fb ldr r3, [r7, #12]
|
|
800413c: 2220 movs r2, #32
|
|
800413e: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_OK;
|
|
8004140: 2300 movs r3, #0
|
|
8004142: e000 b.n 8004146 <HAL_UART_Transmit+0x10a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004144: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004146: 4618 mov r0, r3
|
|
8004148: 3720 adds r7, #32
|
|
800414a: 46bd mov sp, r7
|
|
800414c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08004150 <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8004150: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8004154: b08a sub sp, #40 @ 0x28
|
|
8004156: af00 add r7, sp, #0
|
|
8004158: 60f8 str r0, [r7, #12]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800415a: 2300 movs r3, #0
|
|
800415c: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
8004160: 68fb ldr r3, [r7, #12]
|
|
8004162: 689a ldr r2, [r3, #8]
|
|
8004164: 68fb ldr r3, [r7, #12]
|
|
8004166: 691b ldr r3, [r3, #16]
|
|
8004168: 431a orrs r2, r3
|
|
800416a: 68fb ldr r3, [r7, #12]
|
|
800416c: 695b ldr r3, [r3, #20]
|
|
800416e: 431a orrs r2, r3
|
|
8004170: 68fb ldr r3, [r7, #12]
|
|
8004172: 69db ldr r3, [r3, #28]
|
|
8004174: 4313 orrs r3, r2
|
|
8004176: 627b str r3, [r7, #36] @ 0x24
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
8004178: 68fb ldr r3, [r7, #12]
|
|
800417a: 681b ldr r3, [r3, #0]
|
|
800417c: 681a ldr r2, [r3, #0]
|
|
800417e: 4ba4 ldr r3, [pc, #656] @ (8004410 <UART_SetConfig+0x2c0>)
|
|
8004180: 4013 ands r3, r2
|
|
8004182: 68fa ldr r2, [r7, #12]
|
|
8004184: 6812 ldr r2, [r2, #0]
|
|
8004186: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8004188: 430b orrs r3, r1
|
|
800418a: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
800418c: 68fb ldr r3, [r7, #12]
|
|
800418e: 681b ldr r3, [r3, #0]
|
|
8004190: 685b ldr r3, [r3, #4]
|
|
8004192: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
8004196: 68fb ldr r3, [r7, #12]
|
|
8004198: 68da ldr r2, [r3, #12]
|
|
800419a: 68fb ldr r3, [r7, #12]
|
|
800419c: 681b ldr r3, [r3, #0]
|
|
800419e: 430a orrs r2, r1
|
|
80041a0: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
80041a2: 68fb ldr r3, [r7, #12]
|
|
80041a4: 699b ldr r3, [r3, #24]
|
|
80041a6: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
80041a8: 68fb ldr r3, [r7, #12]
|
|
80041aa: 681b ldr r3, [r3, #0]
|
|
80041ac: 4a99 ldr r2, [pc, #612] @ (8004414 <UART_SetConfig+0x2c4>)
|
|
80041ae: 4293 cmp r3, r2
|
|
80041b0: d004 beq.n 80041bc <UART_SetConfig+0x6c>
|
|
{
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
80041b2: 68fb ldr r3, [r7, #12]
|
|
80041b4: 6a1b ldr r3, [r3, #32]
|
|
80041b6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80041b8: 4313 orrs r3, r2
|
|
80041ba: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
80041bc: 68fb ldr r3, [r7, #12]
|
|
80041be: 681b ldr r3, [r3, #0]
|
|
80041c0: 689b ldr r3, [r3, #8]
|
|
80041c2: f423 6130 bic.w r1, r3, #2816 @ 0xb00
|
|
80041c6: 68fb ldr r3, [r7, #12]
|
|
80041c8: 681b ldr r3, [r3, #0]
|
|
80041ca: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80041cc: 430a orrs r2, r1
|
|
80041ce: 609a str r2, [r3, #8]
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
80041d0: 68fb ldr r3, [r7, #12]
|
|
80041d2: 681b ldr r3, [r3, #0]
|
|
80041d4: 4a90 ldr r2, [pc, #576] @ (8004418 <UART_SetConfig+0x2c8>)
|
|
80041d6: 4293 cmp r3, r2
|
|
80041d8: d126 bne.n 8004228 <UART_SetConfig+0xd8>
|
|
80041da: 4b90 ldr r3, [pc, #576] @ (800441c <UART_SetConfig+0x2cc>)
|
|
80041dc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80041e0: f003 0303 and.w r3, r3, #3
|
|
80041e4: 2b03 cmp r3, #3
|
|
80041e6: d81b bhi.n 8004220 <UART_SetConfig+0xd0>
|
|
80041e8: a201 add r2, pc, #4 @ (adr r2, 80041f0 <UART_SetConfig+0xa0>)
|
|
80041ea: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80041ee: bf00 nop
|
|
80041f0: 08004201 .word 0x08004201
|
|
80041f4: 08004211 .word 0x08004211
|
|
80041f8: 08004209 .word 0x08004209
|
|
80041fc: 08004219 .word 0x08004219
|
|
8004200: 2301 movs r3, #1
|
|
8004202: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004206: e116 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004208: 2302 movs r3, #2
|
|
800420a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800420e: e112 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004210: 2304 movs r3, #4
|
|
8004212: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004216: e10e b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004218: 2308 movs r3, #8
|
|
800421a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800421e: e10a b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004220: 2310 movs r3, #16
|
|
8004222: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004226: e106 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004228: 68fb ldr r3, [r7, #12]
|
|
800422a: 681b ldr r3, [r3, #0]
|
|
800422c: 4a7c ldr r2, [pc, #496] @ (8004420 <UART_SetConfig+0x2d0>)
|
|
800422e: 4293 cmp r3, r2
|
|
8004230: d138 bne.n 80042a4 <UART_SetConfig+0x154>
|
|
8004232: 4b7a ldr r3, [pc, #488] @ (800441c <UART_SetConfig+0x2cc>)
|
|
8004234: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004238: f003 030c and.w r3, r3, #12
|
|
800423c: 2b0c cmp r3, #12
|
|
800423e: d82d bhi.n 800429c <UART_SetConfig+0x14c>
|
|
8004240: a201 add r2, pc, #4 @ (adr r2, 8004248 <UART_SetConfig+0xf8>)
|
|
8004242: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8004246: bf00 nop
|
|
8004248: 0800427d .word 0x0800427d
|
|
800424c: 0800429d .word 0x0800429d
|
|
8004250: 0800429d .word 0x0800429d
|
|
8004254: 0800429d .word 0x0800429d
|
|
8004258: 0800428d .word 0x0800428d
|
|
800425c: 0800429d .word 0x0800429d
|
|
8004260: 0800429d .word 0x0800429d
|
|
8004264: 0800429d .word 0x0800429d
|
|
8004268: 08004285 .word 0x08004285
|
|
800426c: 0800429d .word 0x0800429d
|
|
8004270: 0800429d .word 0x0800429d
|
|
8004274: 0800429d .word 0x0800429d
|
|
8004278: 08004295 .word 0x08004295
|
|
800427c: 2300 movs r3, #0
|
|
800427e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004282: e0d8 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004284: 2302 movs r3, #2
|
|
8004286: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800428a: e0d4 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
800428c: 2304 movs r3, #4
|
|
800428e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004292: e0d0 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004294: 2308 movs r3, #8
|
|
8004296: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800429a: e0cc b.n 8004436 <UART_SetConfig+0x2e6>
|
|
800429c: 2310 movs r3, #16
|
|
800429e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80042a2: e0c8 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80042a4: 68fb ldr r3, [r7, #12]
|
|
80042a6: 681b ldr r3, [r3, #0]
|
|
80042a8: 4a5e ldr r2, [pc, #376] @ (8004424 <UART_SetConfig+0x2d4>)
|
|
80042aa: 4293 cmp r3, r2
|
|
80042ac: d125 bne.n 80042fa <UART_SetConfig+0x1aa>
|
|
80042ae: 4b5b ldr r3, [pc, #364] @ (800441c <UART_SetConfig+0x2cc>)
|
|
80042b0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80042b4: f003 0330 and.w r3, r3, #48 @ 0x30
|
|
80042b8: 2b30 cmp r3, #48 @ 0x30
|
|
80042ba: d016 beq.n 80042ea <UART_SetConfig+0x19a>
|
|
80042bc: 2b30 cmp r3, #48 @ 0x30
|
|
80042be: d818 bhi.n 80042f2 <UART_SetConfig+0x1a2>
|
|
80042c0: 2b20 cmp r3, #32
|
|
80042c2: d00a beq.n 80042da <UART_SetConfig+0x18a>
|
|
80042c4: 2b20 cmp r3, #32
|
|
80042c6: d814 bhi.n 80042f2 <UART_SetConfig+0x1a2>
|
|
80042c8: 2b00 cmp r3, #0
|
|
80042ca: d002 beq.n 80042d2 <UART_SetConfig+0x182>
|
|
80042cc: 2b10 cmp r3, #16
|
|
80042ce: d008 beq.n 80042e2 <UART_SetConfig+0x192>
|
|
80042d0: e00f b.n 80042f2 <UART_SetConfig+0x1a2>
|
|
80042d2: 2300 movs r3, #0
|
|
80042d4: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80042d8: e0ad b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80042da: 2302 movs r3, #2
|
|
80042dc: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80042e0: e0a9 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80042e2: 2304 movs r3, #4
|
|
80042e4: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80042e8: e0a5 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80042ea: 2308 movs r3, #8
|
|
80042ec: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80042f0: e0a1 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80042f2: 2310 movs r3, #16
|
|
80042f4: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80042f8: e09d b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80042fa: 68fb ldr r3, [r7, #12]
|
|
80042fc: 681b ldr r3, [r3, #0]
|
|
80042fe: 4a4a ldr r2, [pc, #296] @ (8004428 <UART_SetConfig+0x2d8>)
|
|
8004300: 4293 cmp r3, r2
|
|
8004302: d125 bne.n 8004350 <UART_SetConfig+0x200>
|
|
8004304: 4b45 ldr r3, [pc, #276] @ (800441c <UART_SetConfig+0x2cc>)
|
|
8004306: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800430a: f003 03c0 and.w r3, r3, #192 @ 0xc0
|
|
800430e: 2bc0 cmp r3, #192 @ 0xc0
|
|
8004310: d016 beq.n 8004340 <UART_SetConfig+0x1f0>
|
|
8004312: 2bc0 cmp r3, #192 @ 0xc0
|
|
8004314: d818 bhi.n 8004348 <UART_SetConfig+0x1f8>
|
|
8004316: 2b80 cmp r3, #128 @ 0x80
|
|
8004318: d00a beq.n 8004330 <UART_SetConfig+0x1e0>
|
|
800431a: 2b80 cmp r3, #128 @ 0x80
|
|
800431c: d814 bhi.n 8004348 <UART_SetConfig+0x1f8>
|
|
800431e: 2b00 cmp r3, #0
|
|
8004320: d002 beq.n 8004328 <UART_SetConfig+0x1d8>
|
|
8004322: 2b40 cmp r3, #64 @ 0x40
|
|
8004324: d008 beq.n 8004338 <UART_SetConfig+0x1e8>
|
|
8004326: e00f b.n 8004348 <UART_SetConfig+0x1f8>
|
|
8004328: 2300 movs r3, #0
|
|
800432a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800432e: e082 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004330: 2302 movs r3, #2
|
|
8004332: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004336: e07e b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004338: 2304 movs r3, #4
|
|
800433a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800433e: e07a b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004340: 2308 movs r3, #8
|
|
8004342: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004346: e076 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004348: 2310 movs r3, #16
|
|
800434a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800434e: e072 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004350: 68fb ldr r3, [r7, #12]
|
|
8004352: 681b ldr r3, [r3, #0]
|
|
8004354: 4a35 ldr r2, [pc, #212] @ (800442c <UART_SetConfig+0x2dc>)
|
|
8004356: 4293 cmp r3, r2
|
|
8004358: d12a bne.n 80043b0 <UART_SetConfig+0x260>
|
|
800435a: 4b30 ldr r3, [pc, #192] @ (800441c <UART_SetConfig+0x2cc>)
|
|
800435c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004360: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8004364: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8004368: d01a beq.n 80043a0 <UART_SetConfig+0x250>
|
|
800436a: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
800436e: d81b bhi.n 80043a8 <UART_SetConfig+0x258>
|
|
8004370: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8004374: d00c beq.n 8004390 <UART_SetConfig+0x240>
|
|
8004376: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
800437a: d815 bhi.n 80043a8 <UART_SetConfig+0x258>
|
|
800437c: 2b00 cmp r3, #0
|
|
800437e: d003 beq.n 8004388 <UART_SetConfig+0x238>
|
|
8004380: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8004384: d008 beq.n 8004398 <UART_SetConfig+0x248>
|
|
8004386: e00f b.n 80043a8 <UART_SetConfig+0x258>
|
|
8004388: 2300 movs r3, #0
|
|
800438a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800438e: e052 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004390: 2302 movs r3, #2
|
|
8004392: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004396: e04e b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004398: 2304 movs r3, #4
|
|
800439a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800439e: e04a b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80043a0: 2308 movs r3, #8
|
|
80043a2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80043a6: e046 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80043a8: 2310 movs r3, #16
|
|
80043aa: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80043ae: e042 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80043b0: 68fb ldr r3, [r7, #12]
|
|
80043b2: 681b ldr r3, [r3, #0]
|
|
80043b4: 4a17 ldr r2, [pc, #92] @ (8004414 <UART_SetConfig+0x2c4>)
|
|
80043b6: 4293 cmp r3, r2
|
|
80043b8: d13a bne.n 8004430 <UART_SetConfig+0x2e0>
|
|
80043ba: 4b18 ldr r3, [pc, #96] @ (800441c <UART_SetConfig+0x2cc>)
|
|
80043bc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80043c0: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
80043c4: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
80043c8: d01a beq.n 8004400 <UART_SetConfig+0x2b0>
|
|
80043ca: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
80043ce: d81b bhi.n 8004408 <UART_SetConfig+0x2b8>
|
|
80043d0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80043d4: d00c beq.n 80043f0 <UART_SetConfig+0x2a0>
|
|
80043d6: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80043da: d815 bhi.n 8004408 <UART_SetConfig+0x2b8>
|
|
80043dc: 2b00 cmp r3, #0
|
|
80043de: d003 beq.n 80043e8 <UART_SetConfig+0x298>
|
|
80043e0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80043e4: d008 beq.n 80043f8 <UART_SetConfig+0x2a8>
|
|
80043e6: e00f b.n 8004408 <UART_SetConfig+0x2b8>
|
|
80043e8: 2300 movs r3, #0
|
|
80043ea: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80043ee: e022 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80043f0: 2302 movs r3, #2
|
|
80043f2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80043f6: e01e b.n 8004436 <UART_SetConfig+0x2e6>
|
|
80043f8: 2304 movs r3, #4
|
|
80043fa: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80043fe: e01a b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004400: 2308 movs r3, #8
|
|
8004402: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8004406: e016 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004408: 2310 movs r3, #16
|
|
800440a: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800440e: e012 b.n 8004436 <UART_SetConfig+0x2e6>
|
|
8004410: efff69f3 .word 0xefff69f3
|
|
8004414: 40008000 .word 0x40008000
|
|
8004418: 40013800 .word 0x40013800
|
|
800441c: 40021000 .word 0x40021000
|
|
8004420: 40004400 .word 0x40004400
|
|
8004424: 40004800 .word 0x40004800
|
|
8004428: 40004c00 .word 0x40004c00
|
|
800442c: 40005000 .word 0x40005000
|
|
8004430: 2310 movs r3, #16
|
|
8004432: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
|
|
/* Check LPUART instance */
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
8004436: 68fb ldr r3, [r7, #12]
|
|
8004438: 681b ldr r3, [r3, #0]
|
|
800443a: 4a9f ldr r2, [pc, #636] @ (80046b8 <UART_SetConfig+0x568>)
|
|
800443c: 4293 cmp r3, r2
|
|
800443e: d17a bne.n 8004536 <UART_SetConfig+0x3e6>
|
|
{
|
|
/* Retrieve frequency clock */
|
|
switch (clocksource)
|
|
8004440: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8004444: 2b08 cmp r3, #8
|
|
8004446: d824 bhi.n 8004492 <UART_SetConfig+0x342>
|
|
8004448: a201 add r2, pc, #4 @ (adr r2, 8004450 <UART_SetConfig+0x300>)
|
|
800444a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800444e: bf00 nop
|
|
8004450: 08004475 .word 0x08004475
|
|
8004454: 08004493 .word 0x08004493
|
|
8004458: 0800447d .word 0x0800447d
|
|
800445c: 08004493 .word 0x08004493
|
|
8004460: 08004483 .word 0x08004483
|
|
8004464: 08004493 .word 0x08004493
|
|
8004468: 08004493 .word 0x08004493
|
|
800446c: 08004493 .word 0x08004493
|
|
8004470: 0800448b .word 0x0800448b
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8004474: f7ff f84c bl 8003510 <HAL_RCC_GetPCLK1Freq>
|
|
8004478: 61f8 str r0, [r7, #28]
|
|
break;
|
|
800447a: e010 b.n 800449e <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
800447c: 4b8f ldr r3, [pc, #572] @ (80046bc <UART_SetConfig+0x56c>)
|
|
800447e: 61fb str r3, [r7, #28]
|
|
break;
|
|
8004480: e00d b.n 800449e <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8004482: f7fe ffad bl 80033e0 <HAL_RCC_GetSysClockFreq>
|
|
8004486: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8004488: e009 b.n 800449e <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
800448a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
800448e: 61fb str r3, [r7, #28]
|
|
break;
|
|
8004490: e005 b.n 800449e <UART_SetConfig+0x34e>
|
|
default:
|
|
pclk = 0U;
|
|
8004492: 2300 movs r3, #0
|
|
8004494: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
8004496: 2301 movs r3, #1
|
|
8004498: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
800449c: bf00 nop
|
|
}
|
|
|
|
/* If proper clock source reported */
|
|
if (pclk != 0U)
|
|
800449e: 69fb ldr r3, [r7, #28]
|
|
80044a0: 2b00 cmp r3, #0
|
|
80044a2: f000 80fb beq.w 800469c <UART_SetConfig+0x54c>
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
#else
|
|
/* No Prescaler applicable */
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
80044a6: 68fb ldr r3, [r7, #12]
|
|
80044a8: 685a ldr r2, [r3, #4]
|
|
80044aa: 4613 mov r3, r2
|
|
80044ac: 005b lsls r3, r3, #1
|
|
80044ae: 4413 add r3, r2
|
|
80044b0: 69fa ldr r2, [r7, #28]
|
|
80044b2: 429a cmp r2, r3
|
|
80044b4: d305 bcc.n 80044c2 <UART_SetConfig+0x372>
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
|
80044b6: 68fb ldr r3, [r7, #12]
|
|
80044b8: 685b ldr r3, [r3, #4]
|
|
80044ba: 031b lsls r3, r3, #12
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
80044bc: 69fa ldr r2, [r7, #28]
|
|
80044be: 429a cmp r2, r3
|
|
80044c0: d903 bls.n 80044ca <UART_SetConfig+0x37a>
|
|
{
|
|
ret = HAL_ERROR;
|
|
80044c2: 2301 movs r3, #1
|
|
80044c4: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
80044c8: e0e8 b.n 800469c <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
|
80044ca: 69fb ldr r3, [r7, #28]
|
|
80044cc: 2200 movs r2, #0
|
|
80044ce: 461c mov r4, r3
|
|
80044d0: 4615 mov r5, r2
|
|
80044d2: f04f 0200 mov.w r2, #0
|
|
80044d6: f04f 0300 mov.w r3, #0
|
|
80044da: 022b lsls r3, r5, #8
|
|
80044dc: ea43 6314 orr.w r3, r3, r4, lsr #24
|
|
80044e0: 0222 lsls r2, r4, #8
|
|
80044e2: 68f9 ldr r1, [r7, #12]
|
|
80044e4: 6849 ldr r1, [r1, #4]
|
|
80044e6: 0849 lsrs r1, r1, #1
|
|
80044e8: 2000 movs r0, #0
|
|
80044ea: 4688 mov r8, r1
|
|
80044ec: 4681 mov r9, r0
|
|
80044ee: eb12 0a08 adds.w sl, r2, r8
|
|
80044f2: eb43 0b09 adc.w fp, r3, r9
|
|
80044f6: 68fb ldr r3, [r7, #12]
|
|
80044f8: 685b ldr r3, [r3, #4]
|
|
80044fa: 2200 movs r2, #0
|
|
80044fc: 603b str r3, [r7, #0]
|
|
80044fe: 607a str r2, [r7, #4]
|
|
8004500: e9d7 2300 ldrd r2, r3, [r7]
|
|
8004504: 4650 mov r0, sl
|
|
8004506: 4659 mov r1, fp
|
|
8004508: f7fc fb4e bl 8000ba8 <__aeabi_uldivmod>
|
|
800450c: 4602 mov r2, r0
|
|
800450e: 460b mov r3, r1
|
|
8004510: 4613 mov r3, r2
|
|
8004512: 61bb str r3, [r7, #24]
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
8004514: 69bb ldr r3, [r7, #24]
|
|
8004516: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
800451a: d308 bcc.n 800452e <UART_SetConfig+0x3de>
|
|
800451c: 69bb ldr r3, [r7, #24]
|
|
800451e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8004522: d204 bcs.n 800452e <UART_SetConfig+0x3de>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
8004524: 68fb ldr r3, [r7, #12]
|
|
8004526: 681b ldr r3, [r3, #0]
|
|
8004528: 69ba ldr r2, [r7, #24]
|
|
800452a: 60da str r2, [r3, #12]
|
|
800452c: e0b6 b.n 800469c <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800452e: 2301 movs r3, #1
|
|
8004530: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
8004534: e0b2 b.n 800469c <UART_SetConfig+0x54c>
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
} /* if (pclk != 0) */
|
|
}
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8004536: 68fb ldr r3, [r7, #12]
|
|
8004538: 69db ldr r3, [r3, #28]
|
|
800453a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800453e: d15e bne.n 80045fe <UART_SetConfig+0x4ae>
|
|
{
|
|
switch (clocksource)
|
|
8004540: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8004544: 2b08 cmp r3, #8
|
|
8004546: d828 bhi.n 800459a <UART_SetConfig+0x44a>
|
|
8004548: a201 add r2, pc, #4 @ (adr r2, 8004550 <UART_SetConfig+0x400>)
|
|
800454a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800454e: bf00 nop
|
|
8004550: 08004575 .word 0x08004575
|
|
8004554: 0800457d .word 0x0800457d
|
|
8004558: 08004585 .word 0x08004585
|
|
800455c: 0800459b .word 0x0800459b
|
|
8004560: 0800458b .word 0x0800458b
|
|
8004564: 0800459b .word 0x0800459b
|
|
8004568: 0800459b .word 0x0800459b
|
|
800456c: 0800459b .word 0x0800459b
|
|
8004570: 08004593 .word 0x08004593
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8004574: f7fe ffcc bl 8003510 <HAL_RCC_GetPCLK1Freq>
|
|
8004578: 61f8 str r0, [r7, #28]
|
|
break;
|
|
800457a: e014 b.n 80045a6 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
800457c: f7fe ffde bl 800353c <HAL_RCC_GetPCLK2Freq>
|
|
8004580: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8004582: e010 b.n 80045a6 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8004584: 4b4d ldr r3, [pc, #308] @ (80046bc <UART_SetConfig+0x56c>)
|
|
8004586: 61fb str r3, [r7, #28]
|
|
break;
|
|
8004588: e00d b.n 80045a6 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800458a: f7fe ff29 bl 80033e0 <HAL_RCC_GetSysClockFreq>
|
|
800458e: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8004590: e009 b.n 80045a6 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8004592: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8004596: 61fb str r3, [r7, #28]
|
|
break;
|
|
8004598: e005 b.n 80045a6 <UART_SetConfig+0x456>
|
|
default:
|
|
pclk = 0U;
|
|
800459a: 2300 movs r3, #0
|
|
800459c: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
800459e: 2301 movs r3, #1
|
|
80045a0: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
80045a4: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
80045a6: 69fb ldr r3, [r7, #28]
|
|
80045a8: 2b00 cmp r3, #0
|
|
80045aa: d077 beq.n 800469c <UART_SetConfig+0x54c>
|
|
{
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
80045ac: 69fb ldr r3, [r7, #28]
|
|
80045ae: 005a lsls r2, r3, #1
|
|
80045b0: 68fb ldr r3, [r7, #12]
|
|
80045b2: 685b ldr r3, [r3, #4]
|
|
80045b4: 085b lsrs r3, r3, #1
|
|
80045b6: 441a add r2, r3
|
|
80045b8: 68fb ldr r3, [r7, #12]
|
|
80045ba: 685b ldr r3, [r3, #4]
|
|
80045bc: fbb2 f3f3 udiv r3, r2, r3
|
|
80045c0: 61bb str r3, [r7, #24]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
80045c2: 69bb ldr r3, [r7, #24]
|
|
80045c4: 2b0f cmp r3, #15
|
|
80045c6: d916 bls.n 80045f6 <UART_SetConfig+0x4a6>
|
|
80045c8: 69bb ldr r3, [r7, #24]
|
|
80045ca: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
80045ce: d212 bcs.n 80045f6 <UART_SetConfig+0x4a6>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
80045d0: 69bb ldr r3, [r7, #24]
|
|
80045d2: b29b uxth r3, r3
|
|
80045d4: f023 030f bic.w r3, r3, #15
|
|
80045d8: 82fb strh r3, [r7, #22]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
80045da: 69bb ldr r3, [r7, #24]
|
|
80045dc: 085b lsrs r3, r3, #1
|
|
80045de: b29b uxth r3, r3
|
|
80045e0: f003 0307 and.w r3, r3, #7
|
|
80045e4: b29a uxth r2, r3
|
|
80045e6: 8afb ldrh r3, [r7, #22]
|
|
80045e8: 4313 orrs r3, r2
|
|
80045ea: 82fb strh r3, [r7, #22]
|
|
huart->Instance->BRR = brrtemp;
|
|
80045ec: 68fb ldr r3, [r7, #12]
|
|
80045ee: 681b ldr r3, [r3, #0]
|
|
80045f0: 8afa ldrh r2, [r7, #22]
|
|
80045f2: 60da str r2, [r3, #12]
|
|
80045f4: e052 b.n 800469c <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
80045f6: 2301 movs r3, #1
|
|
80045f8: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
80045fc: e04e b.n 800469c <UART_SetConfig+0x54c>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
80045fe: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8004602: 2b08 cmp r3, #8
|
|
8004604: d827 bhi.n 8004656 <UART_SetConfig+0x506>
|
|
8004606: a201 add r2, pc, #4 @ (adr r2, 800460c <UART_SetConfig+0x4bc>)
|
|
8004608: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800460c: 08004631 .word 0x08004631
|
|
8004610: 08004639 .word 0x08004639
|
|
8004614: 08004641 .word 0x08004641
|
|
8004618: 08004657 .word 0x08004657
|
|
800461c: 08004647 .word 0x08004647
|
|
8004620: 08004657 .word 0x08004657
|
|
8004624: 08004657 .word 0x08004657
|
|
8004628: 08004657 .word 0x08004657
|
|
800462c: 0800464f .word 0x0800464f
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8004630: f7fe ff6e bl 8003510 <HAL_RCC_GetPCLK1Freq>
|
|
8004634: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8004636: e014 b.n 8004662 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8004638: f7fe ff80 bl 800353c <HAL_RCC_GetPCLK2Freq>
|
|
800463c: 61f8 str r0, [r7, #28]
|
|
break;
|
|
800463e: e010 b.n 8004662 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8004640: 4b1e ldr r3, [pc, #120] @ (80046bc <UART_SetConfig+0x56c>)
|
|
8004642: 61fb str r3, [r7, #28]
|
|
break;
|
|
8004644: e00d b.n 8004662 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8004646: f7fe fecb bl 80033e0 <HAL_RCC_GetSysClockFreq>
|
|
800464a: 61f8 str r0, [r7, #28]
|
|
break;
|
|
800464c: e009 b.n 8004662 <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
800464e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8004652: 61fb str r3, [r7, #28]
|
|
break;
|
|
8004654: e005 b.n 8004662 <UART_SetConfig+0x512>
|
|
default:
|
|
pclk = 0U;
|
|
8004656: 2300 movs r3, #0
|
|
8004658: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
800465a: 2301 movs r3, #1
|
|
800465c: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
8004660: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
8004662: 69fb ldr r3, [r7, #28]
|
|
8004664: 2b00 cmp r3, #0
|
|
8004666: d019 beq.n 800469c <UART_SetConfig+0x54c>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
8004668: 68fb ldr r3, [r7, #12]
|
|
800466a: 685b ldr r3, [r3, #4]
|
|
800466c: 085a lsrs r2, r3, #1
|
|
800466e: 69fb ldr r3, [r7, #28]
|
|
8004670: 441a add r2, r3
|
|
8004672: 68fb ldr r3, [r7, #12]
|
|
8004674: 685b ldr r3, [r3, #4]
|
|
8004676: fbb2 f3f3 udiv r3, r2, r3
|
|
800467a: 61bb str r3, [r7, #24]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
800467c: 69bb ldr r3, [r7, #24]
|
|
800467e: 2b0f cmp r3, #15
|
|
8004680: d909 bls.n 8004696 <UART_SetConfig+0x546>
|
|
8004682: 69bb ldr r3, [r7, #24]
|
|
8004684: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004688: d205 bcs.n 8004696 <UART_SetConfig+0x546>
|
|
{
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
800468a: 69bb ldr r3, [r7, #24]
|
|
800468c: b29a uxth r2, r3
|
|
800468e: 68fb ldr r3, [r7, #12]
|
|
8004690: 681b ldr r3, [r3, #0]
|
|
8004692: 60da str r2, [r3, #12]
|
|
8004694: e002 b.n 800469c <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8004696: 2301 movs r3, #1
|
|
8004698: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
huart->NbTxDataToProcess = 1;
|
|
huart->NbRxDataToProcess = 1;
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
800469c: 68fb ldr r3, [r7, #12]
|
|
800469e: 2200 movs r2, #0
|
|
80046a0: 669a str r2, [r3, #104] @ 0x68
|
|
huart->TxISR = NULL;
|
|
80046a2: 68fb ldr r3, [r7, #12]
|
|
80046a4: 2200 movs r2, #0
|
|
80046a6: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
return ret;
|
|
80046a8: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
|
|
}
|
|
80046ac: 4618 mov r0, r3
|
|
80046ae: 3728 adds r7, #40 @ 0x28
|
|
80046b0: 46bd mov sp, r7
|
|
80046b2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
80046b6: bf00 nop
|
|
80046b8: 40008000 .word 0x40008000
|
|
80046bc: 00f42400 .word 0x00f42400
|
|
|
|
080046c0 <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
80046c0: b480 push {r7}
|
|
80046c2: b083 sub sp, #12
|
|
80046c4: af00 add r7, sp, #0
|
|
80046c6: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
80046c8: 687b ldr r3, [r7, #4]
|
|
80046ca: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80046cc: f003 0308 and.w r3, r3, #8
|
|
80046d0: 2b00 cmp r3, #0
|
|
80046d2: d00a beq.n 80046ea <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
80046d4: 687b ldr r3, [r7, #4]
|
|
80046d6: 681b ldr r3, [r3, #0]
|
|
80046d8: 685b ldr r3, [r3, #4]
|
|
80046da: f423 4100 bic.w r1, r3, #32768 @ 0x8000
|
|
80046de: 687b ldr r3, [r7, #4]
|
|
80046e0: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80046e2: 687b ldr r3, [r7, #4]
|
|
80046e4: 681b ldr r3, [r3, #0]
|
|
80046e6: 430a orrs r2, r1
|
|
80046e8: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
80046ea: 687b ldr r3, [r7, #4]
|
|
80046ec: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80046ee: f003 0301 and.w r3, r3, #1
|
|
80046f2: 2b00 cmp r3, #0
|
|
80046f4: d00a beq.n 800470c <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
80046f6: 687b ldr r3, [r7, #4]
|
|
80046f8: 681b ldr r3, [r3, #0]
|
|
80046fa: 685b ldr r3, [r3, #4]
|
|
80046fc: f423 3100 bic.w r1, r3, #131072 @ 0x20000
|
|
8004700: 687b ldr r3, [r7, #4]
|
|
8004702: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
8004704: 687b ldr r3, [r7, #4]
|
|
8004706: 681b ldr r3, [r3, #0]
|
|
8004708: 430a orrs r2, r1
|
|
800470a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
800470c: 687b ldr r3, [r7, #4]
|
|
800470e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004710: f003 0302 and.w r3, r3, #2
|
|
8004714: 2b00 cmp r3, #0
|
|
8004716: d00a beq.n 800472e <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
8004718: 687b ldr r3, [r7, #4]
|
|
800471a: 681b ldr r3, [r3, #0]
|
|
800471c: 685b ldr r3, [r3, #4]
|
|
800471e: f423 3180 bic.w r1, r3, #65536 @ 0x10000
|
|
8004722: 687b ldr r3, [r7, #4]
|
|
8004724: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8004726: 687b ldr r3, [r7, #4]
|
|
8004728: 681b ldr r3, [r3, #0]
|
|
800472a: 430a orrs r2, r1
|
|
800472c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
800472e: 687b ldr r3, [r7, #4]
|
|
8004730: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004732: f003 0304 and.w r3, r3, #4
|
|
8004736: 2b00 cmp r3, #0
|
|
8004738: d00a beq.n 8004750 <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
800473a: 687b ldr r3, [r7, #4]
|
|
800473c: 681b ldr r3, [r3, #0]
|
|
800473e: 685b ldr r3, [r3, #4]
|
|
8004740: f423 2180 bic.w r1, r3, #262144 @ 0x40000
|
|
8004744: 687b ldr r3, [r7, #4]
|
|
8004746: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8004748: 687b ldr r3, [r7, #4]
|
|
800474a: 681b ldr r3, [r3, #0]
|
|
800474c: 430a orrs r2, r1
|
|
800474e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8004750: 687b ldr r3, [r7, #4]
|
|
8004752: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004754: f003 0310 and.w r3, r3, #16
|
|
8004758: 2b00 cmp r3, #0
|
|
800475a: d00a beq.n 8004772 <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
800475c: 687b ldr r3, [r7, #4]
|
|
800475e: 681b ldr r3, [r3, #0]
|
|
8004760: 689b ldr r3, [r3, #8]
|
|
8004762: f423 5180 bic.w r1, r3, #4096 @ 0x1000
|
|
8004766: 687b ldr r3, [r7, #4]
|
|
8004768: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800476a: 687b ldr r3, [r7, #4]
|
|
800476c: 681b ldr r3, [r3, #0]
|
|
800476e: 430a orrs r2, r1
|
|
8004770: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8004772: 687b ldr r3, [r7, #4]
|
|
8004774: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004776: f003 0320 and.w r3, r3, #32
|
|
800477a: 2b00 cmp r3, #0
|
|
800477c: d00a beq.n 8004794 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
800477e: 687b ldr r3, [r7, #4]
|
|
8004780: 681b ldr r3, [r3, #0]
|
|
8004782: 689b ldr r3, [r3, #8]
|
|
8004784: f423 5100 bic.w r1, r3, #8192 @ 0x2000
|
|
8004788: 687b ldr r3, [r7, #4]
|
|
800478a: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
800478c: 687b ldr r3, [r7, #4]
|
|
800478e: 681b ldr r3, [r3, #0]
|
|
8004790: 430a orrs r2, r1
|
|
8004792: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
8004794: 687b ldr r3, [r7, #4]
|
|
8004796: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004798: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800479c: 2b00 cmp r3, #0
|
|
800479e: d01a beq.n 80047d6 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
80047a0: 687b ldr r3, [r7, #4]
|
|
80047a2: 681b ldr r3, [r3, #0]
|
|
80047a4: 685b ldr r3, [r3, #4]
|
|
80047a6: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
|
|
80047aa: 687b ldr r3, [r7, #4]
|
|
80047ac: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
80047ae: 687b ldr r3, [r7, #4]
|
|
80047b0: 681b ldr r3, [r3, #0]
|
|
80047b2: 430a orrs r2, r1
|
|
80047b4: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
80047b6: 687b ldr r3, [r7, #4]
|
|
80047b8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80047ba: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80047be: d10a bne.n 80047d6 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
80047c0: 687b ldr r3, [r7, #4]
|
|
80047c2: 681b ldr r3, [r3, #0]
|
|
80047c4: 685b ldr r3, [r3, #4]
|
|
80047c6: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
|
|
80047ca: 687b ldr r3, [r7, #4]
|
|
80047cc: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
80047ce: 687b ldr r3, [r7, #4]
|
|
80047d0: 681b ldr r3, [r3, #0]
|
|
80047d2: 430a orrs r2, r1
|
|
80047d4: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
80047d6: 687b ldr r3, [r7, #4]
|
|
80047d8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80047da: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80047de: 2b00 cmp r3, #0
|
|
80047e0: d00a beq.n 80047f8 <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
80047e2: 687b ldr r3, [r7, #4]
|
|
80047e4: 681b ldr r3, [r3, #0]
|
|
80047e6: 685b ldr r3, [r3, #4]
|
|
80047e8: f423 2100 bic.w r1, r3, #524288 @ 0x80000
|
|
80047ec: 687b ldr r3, [r7, #4]
|
|
80047ee: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
80047f0: 687b ldr r3, [r7, #4]
|
|
80047f2: 681b ldr r3, [r3, #0]
|
|
80047f4: 430a orrs r2, r1
|
|
80047f6: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
80047f8: bf00 nop
|
|
80047fa: 370c adds r7, #12
|
|
80047fc: 46bd mov sp, r7
|
|
80047fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004802: 4770 bx lr
|
|
|
|
08004804 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8004804: b580 push {r7, lr}
|
|
8004806: b098 sub sp, #96 @ 0x60
|
|
8004808: af02 add r7, sp, #8
|
|
800480a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800480c: 687b ldr r3, [r7, #4]
|
|
800480e: 2200 movs r2, #0
|
|
8004810: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8004814: f7fc ffcc bl 80017b0 <HAL_GetTick>
|
|
8004818: 6578 str r0, [r7, #84] @ 0x54
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
800481a: 687b ldr r3, [r7, #4]
|
|
800481c: 681b ldr r3, [r3, #0]
|
|
800481e: 681b ldr r3, [r3, #0]
|
|
8004820: f003 0308 and.w r3, r3, #8
|
|
8004824: 2b08 cmp r3, #8
|
|
8004826: d12e bne.n 8004886 <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8004828: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
800482c: 9300 str r3, [sp, #0]
|
|
800482e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8004830: 2200 movs r2, #0
|
|
8004832: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
8004836: 6878 ldr r0, [r7, #4]
|
|
8004838: f000 f88c bl 8004954 <UART_WaitOnFlagUntilTimeout>
|
|
800483c: 4603 mov r3, r0
|
|
800483e: 2b00 cmp r3, #0
|
|
8004840: d021 beq.n 8004886 <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
|
|
8004842: 687b ldr r3, [r7, #4]
|
|
8004844: 681b ldr r3, [r3, #0]
|
|
8004846: 63bb str r3, [r7, #56] @ 0x38
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004848: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800484a: e853 3f00 ldrex r3, [r3]
|
|
800484e: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8004850: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8004852: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8004856: 653b str r3, [r7, #80] @ 0x50
|
|
8004858: 687b ldr r3, [r7, #4]
|
|
800485a: 681b ldr r3, [r3, #0]
|
|
800485c: 461a mov r2, r3
|
|
800485e: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8004860: 647b str r3, [r7, #68] @ 0x44
|
|
8004862: 643a str r2, [r7, #64] @ 0x40
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004864: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8004866: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8004868: e841 2300 strex r3, r2, [r1]
|
|
800486c: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
800486e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8004870: 2b00 cmp r3, #0
|
|
8004872: d1e6 bne.n 8004842 <UART_CheckIdleState+0x3e>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004874: 687b ldr r3, [r7, #4]
|
|
8004876: 2220 movs r2, #32
|
|
8004878: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800487a: 687b ldr r3, [r7, #4]
|
|
800487c: 2200 movs r2, #0
|
|
800487e: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8004882: 2303 movs r3, #3
|
|
8004884: e062 b.n 800494c <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
8004886: 687b ldr r3, [r7, #4]
|
|
8004888: 681b ldr r3, [r3, #0]
|
|
800488a: 681b ldr r3, [r3, #0]
|
|
800488c: f003 0304 and.w r3, r3, #4
|
|
8004890: 2b04 cmp r3, #4
|
|
8004892: d149 bne.n 8004928 <UART_CheckIdleState+0x124>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8004894: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8004898: 9300 str r3, [sp, #0]
|
|
800489a: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800489c: 2200 movs r2, #0
|
|
800489e: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
80048a2: 6878 ldr r0, [r7, #4]
|
|
80048a4: f000 f856 bl 8004954 <UART_WaitOnFlagUntilTimeout>
|
|
80048a8: 4603 mov r3, r0
|
|
80048aa: 2b00 cmp r3, #0
|
|
80048ac: d03c beq.n 8004928 <UART_CheckIdleState+0x124>
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
80048ae: 687b ldr r3, [r7, #4]
|
|
80048b0: 681b ldr r3, [r3, #0]
|
|
80048b2: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80048b4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80048b6: e853 3f00 ldrex r3, [r3]
|
|
80048ba: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80048bc: 6a3b ldr r3, [r7, #32]
|
|
80048be: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80048c2: 64fb str r3, [r7, #76] @ 0x4c
|
|
80048c4: 687b ldr r3, [r7, #4]
|
|
80048c6: 681b ldr r3, [r3, #0]
|
|
80048c8: 461a mov r2, r3
|
|
80048ca: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80048cc: 633b str r3, [r7, #48] @ 0x30
|
|
80048ce: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80048d0: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80048d2: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80048d4: e841 2300 strex r3, r2, [r1]
|
|
80048d8: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80048da: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80048dc: 2b00 cmp r3, #0
|
|
80048de: d1e6 bne.n 80048ae <UART_CheckIdleState+0xaa>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80048e0: 687b ldr r3, [r7, #4]
|
|
80048e2: 681b ldr r3, [r3, #0]
|
|
80048e4: 3308 adds r3, #8
|
|
80048e6: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80048e8: 693b ldr r3, [r7, #16]
|
|
80048ea: e853 3f00 ldrex r3, [r3]
|
|
80048ee: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80048f0: 68fb ldr r3, [r7, #12]
|
|
80048f2: f023 0301 bic.w r3, r3, #1
|
|
80048f6: 64bb str r3, [r7, #72] @ 0x48
|
|
80048f8: 687b ldr r3, [r7, #4]
|
|
80048fa: 681b ldr r3, [r3, #0]
|
|
80048fc: 3308 adds r3, #8
|
|
80048fe: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8004900: 61fa str r2, [r7, #28]
|
|
8004902: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004904: 69b9 ldr r1, [r7, #24]
|
|
8004906: 69fa ldr r2, [r7, #28]
|
|
8004908: e841 2300 strex r3, r2, [r1]
|
|
800490c: 617b str r3, [r7, #20]
|
|
return(result);
|
|
800490e: 697b ldr r3, [r7, #20]
|
|
8004910: 2b00 cmp r3, #0
|
|
8004912: d1e5 bne.n 80048e0 <UART_CheckIdleState+0xdc>
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004914: 687b ldr r3, [r7, #4]
|
|
8004916: 2220 movs r2, #32
|
|
8004918: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800491c: 687b ldr r3, [r7, #4]
|
|
800491e: 2200 movs r2, #0
|
|
8004920: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8004924: 2303 movs r3, #3
|
|
8004926: e011 b.n 800494c <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004928: 687b ldr r3, [r7, #4]
|
|
800492a: 2220 movs r2, #32
|
|
800492c: 67da str r2, [r3, #124] @ 0x7c
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800492e: 687b ldr r3, [r7, #4]
|
|
8004930: 2220 movs r2, #32
|
|
8004932: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004936: 687b ldr r3, [r7, #4]
|
|
8004938: 2200 movs r2, #0
|
|
800493a: 661a str r2, [r3, #96] @ 0x60
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
800493c: 687b ldr r3, [r7, #4]
|
|
800493e: 2200 movs r2, #0
|
|
8004940: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8004942: 687b ldr r3, [r7, #4]
|
|
8004944: 2200 movs r2, #0
|
|
8004946: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_OK;
|
|
800494a: 2300 movs r3, #0
|
|
}
|
|
800494c: 4618 mov r0, r3
|
|
800494e: 3758 adds r7, #88 @ 0x58
|
|
8004950: 46bd mov sp, r7
|
|
8004952: bd80 pop {r7, pc}
|
|
|
|
08004954 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8004954: b580 push {r7, lr}
|
|
8004956: b084 sub sp, #16
|
|
8004958: af00 add r7, sp, #0
|
|
800495a: 60f8 str r0, [r7, #12]
|
|
800495c: 60b9 str r1, [r7, #8]
|
|
800495e: 603b str r3, [r7, #0]
|
|
8004960: 4613 mov r3, r2
|
|
8004962: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8004964: e04f b.n 8004a06 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8004966: 69bb ldr r3, [r7, #24]
|
|
8004968: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800496c: d04b beq.n 8004a06 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
800496e: f7fc ff1f bl 80017b0 <HAL_GetTick>
|
|
8004972: 4602 mov r2, r0
|
|
8004974: 683b ldr r3, [r7, #0]
|
|
8004976: 1ad3 subs r3, r2, r3
|
|
8004978: 69ba ldr r2, [r7, #24]
|
|
800497a: 429a cmp r2, r3
|
|
800497c: d302 bcc.n 8004984 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
800497e: 69bb ldr r3, [r7, #24]
|
|
8004980: 2b00 cmp r3, #0
|
|
8004982: d101 bne.n 8004988 <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
8004984: 2303 movs r3, #3
|
|
8004986: e04e b.n 8004a26 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
8004988: 68fb ldr r3, [r7, #12]
|
|
800498a: 681b ldr r3, [r3, #0]
|
|
800498c: 681b ldr r3, [r3, #0]
|
|
800498e: f003 0304 and.w r3, r3, #4
|
|
8004992: 2b00 cmp r3, #0
|
|
8004994: d037 beq.n 8004a06 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8004996: 68bb ldr r3, [r7, #8]
|
|
8004998: 2b80 cmp r3, #128 @ 0x80
|
|
800499a: d034 beq.n 8004a06 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
800499c: 68bb ldr r3, [r7, #8]
|
|
800499e: 2b40 cmp r3, #64 @ 0x40
|
|
80049a0: d031 beq.n 8004a06 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
80049a2: 68fb ldr r3, [r7, #12]
|
|
80049a4: 681b ldr r3, [r3, #0]
|
|
80049a6: 69db ldr r3, [r3, #28]
|
|
80049a8: f003 0308 and.w r3, r3, #8
|
|
80049ac: 2b08 cmp r3, #8
|
|
80049ae: d110 bne.n 80049d2 <UART_WaitOnFlagUntilTimeout+0x7e>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
80049b0: 68fb ldr r3, [r7, #12]
|
|
80049b2: 681b ldr r3, [r3, #0]
|
|
80049b4: 2208 movs r2, #8
|
|
80049b6: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
80049b8: 68f8 ldr r0, [r7, #12]
|
|
80049ba: f000 f838 bl 8004a2e <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
80049be: 68fb ldr r3, [r7, #12]
|
|
80049c0: 2208 movs r2, #8
|
|
80049c2: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80049c6: 68fb ldr r3, [r7, #12]
|
|
80049c8: 2200 movs r2, #0
|
|
80049ca: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_ERROR;
|
|
80049ce: 2301 movs r3, #1
|
|
80049d0: e029 b.n 8004a26 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
80049d2: 68fb ldr r3, [r7, #12]
|
|
80049d4: 681b ldr r3, [r3, #0]
|
|
80049d6: 69db ldr r3, [r3, #28]
|
|
80049d8: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80049dc: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80049e0: d111 bne.n 8004a06 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
80049e2: 68fb ldr r3, [r7, #12]
|
|
80049e4: 681b ldr r3, [r3, #0]
|
|
80049e6: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
80049ea: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
80049ec: 68f8 ldr r0, [r7, #12]
|
|
80049ee: f000 f81e bl 8004a2e <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
80049f2: 68fb ldr r3, [r7, #12]
|
|
80049f4: 2220 movs r2, #32
|
|
80049f6: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80049fa: 68fb ldr r3, [r7, #12]
|
|
80049fc: 2200 movs r2, #0
|
|
80049fe: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_TIMEOUT;
|
|
8004a02: 2303 movs r3, #3
|
|
8004a04: e00f b.n 8004a26 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8004a06: 68fb ldr r3, [r7, #12]
|
|
8004a08: 681b ldr r3, [r3, #0]
|
|
8004a0a: 69da ldr r2, [r3, #28]
|
|
8004a0c: 68bb ldr r3, [r7, #8]
|
|
8004a0e: 4013 ands r3, r2
|
|
8004a10: 68ba ldr r2, [r7, #8]
|
|
8004a12: 429a cmp r2, r3
|
|
8004a14: bf0c ite eq
|
|
8004a16: 2301 moveq r3, #1
|
|
8004a18: 2300 movne r3, #0
|
|
8004a1a: b2db uxtb r3, r3
|
|
8004a1c: 461a mov r2, r3
|
|
8004a1e: 79fb ldrb r3, [r7, #7]
|
|
8004a20: 429a cmp r2, r3
|
|
8004a22: d0a0 beq.n 8004966 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8004a24: 2300 movs r3, #0
|
|
}
|
|
8004a26: 4618 mov r0, r3
|
|
8004a28: 3710 adds r7, #16
|
|
8004a2a: 46bd mov sp, r7
|
|
8004a2c: bd80 pop {r7, pc}
|
|
|
|
08004a2e <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
8004a2e: b480 push {r7}
|
|
8004a30: b095 sub sp, #84 @ 0x54
|
|
8004a32: af00 add r7, sp, #0
|
|
8004a34: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8004a36: 687b ldr r3, [r7, #4]
|
|
8004a38: 681b ldr r3, [r3, #0]
|
|
8004a3a: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004a3c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8004a3e: e853 3f00 ldrex r3, [r3]
|
|
8004a42: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8004a44: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8004a46: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8004a4a: 64fb str r3, [r7, #76] @ 0x4c
|
|
8004a4c: 687b ldr r3, [r7, #4]
|
|
8004a4e: 681b ldr r3, [r3, #0]
|
|
8004a50: 461a mov r2, r3
|
|
8004a52: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8004a54: 643b str r3, [r7, #64] @ 0x40
|
|
8004a56: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004a58: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8004a5a: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8004a5c: e841 2300 strex r3, r2, [r1]
|
|
8004a60: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8004a62: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8004a64: 2b00 cmp r3, #0
|
|
8004a66: d1e6 bne.n 8004a36 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8004a68: 687b ldr r3, [r7, #4]
|
|
8004a6a: 681b ldr r3, [r3, #0]
|
|
8004a6c: 3308 adds r3, #8
|
|
8004a6e: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004a70: 6a3b ldr r3, [r7, #32]
|
|
8004a72: e853 3f00 ldrex r3, [r3]
|
|
8004a76: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8004a78: 69fb ldr r3, [r7, #28]
|
|
8004a7a: f023 0301 bic.w r3, r3, #1
|
|
8004a7e: 64bb str r3, [r7, #72] @ 0x48
|
|
8004a80: 687b ldr r3, [r7, #4]
|
|
8004a82: 681b ldr r3, [r3, #0]
|
|
8004a84: 3308 adds r3, #8
|
|
8004a86: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8004a88: 62fa str r2, [r7, #44] @ 0x2c
|
|
8004a8a: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004a8c: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8004a8e: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8004a90: e841 2300 strex r3, r2, [r1]
|
|
8004a94: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8004a96: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004a98: 2b00 cmp r3, #0
|
|
8004a9a: d1e5 bne.n 8004a68 <UART_EndRxTransfer+0x3a>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8004a9c: 687b ldr r3, [r7, #4]
|
|
8004a9e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8004aa0: 2b01 cmp r3, #1
|
|
8004aa2: d118 bne.n 8004ad6 <UART_EndRxTransfer+0xa8>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8004aa4: 687b ldr r3, [r7, #4]
|
|
8004aa6: 681b ldr r3, [r3, #0]
|
|
8004aa8: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004aaa: 68fb ldr r3, [r7, #12]
|
|
8004aac: e853 3f00 ldrex r3, [r3]
|
|
8004ab0: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8004ab2: 68bb ldr r3, [r7, #8]
|
|
8004ab4: f023 0310 bic.w r3, r3, #16
|
|
8004ab8: 647b str r3, [r7, #68] @ 0x44
|
|
8004aba: 687b ldr r3, [r7, #4]
|
|
8004abc: 681b ldr r3, [r3, #0]
|
|
8004abe: 461a mov r2, r3
|
|
8004ac0: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8004ac2: 61bb str r3, [r7, #24]
|
|
8004ac4: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004ac6: 6979 ldr r1, [r7, #20]
|
|
8004ac8: 69ba ldr r2, [r7, #24]
|
|
8004aca: e841 2300 strex r3, r2, [r1]
|
|
8004ace: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8004ad0: 693b ldr r3, [r7, #16]
|
|
8004ad2: 2b00 cmp r3, #0
|
|
8004ad4: d1e6 bne.n 8004aa4 <UART_EndRxTransfer+0x76>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004ad6: 687b ldr r3, [r7, #4]
|
|
8004ad8: 2220 movs r2, #32
|
|
8004ada: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004ade: 687b ldr r3, [r7, #4]
|
|
8004ae0: 2200 movs r2, #0
|
|
8004ae2: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
8004ae4: 687b ldr r3, [r7, #4]
|
|
8004ae6: 2200 movs r2, #0
|
|
8004ae8: 669a str r2, [r3, #104] @ 0x68
|
|
}
|
|
8004aea: bf00 nop
|
|
8004aec: 3754 adds r7, #84 @ 0x54
|
|
8004aee: 46bd mov sp, r7
|
|
8004af0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004af4: 4770 bx lr
|
|
|
|
08004af6 <__cvt>:
|
|
8004af6: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8004afa: ec57 6b10 vmov r6, r7, d0
|
|
8004afe: 2f00 cmp r7, #0
|
|
8004b00: 460c mov r4, r1
|
|
8004b02: 4619 mov r1, r3
|
|
8004b04: 463b mov r3, r7
|
|
8004b06: bfbb ittet lt
|
|
8004b08: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000
|
|
8004b0c: 461f movlt r7, r3
|
|
8004b0e: 2300 movge r3, #0
|
|
8004b10: 232d movlt r3, #45 @ 0x2d
|
|
8004b12: 700b strb r3, [r1, #0]
|
|
8004b14: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8004b16: f8dd a030 ldr.w sl, [sp, #48] @ 0x30
|
|
8004b1a: 4691 mov r9, r2
|
|
8004b1c: f023 0820 bic.w r8, r3, #32
|
|
8004b20: bfbc itt lt
|
|
8004b22: 4632 movlt r2, r6
|
|
8004b24: 4616 movlt r6, r2
|
|
8004b26: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
8004b2a: d005 beq.n 8004b38 <__cvt+0x42>
|
|
8004b2c: f1b8 0f45 cmp.w r8, #69 @ 0x45
|
|
8004b30: d100 bne.n 8004b34 <__cvt+0x3e>
|
|
8004b32: 3401 adds r4, #1
|
|
8004b34: 2102 movs r1, #2
|
|
8004b36: e000 b.n 8004b3a <__cvt+0x44>
|
|
8004b38: 2103 movs r1, #3
|
|
8004b3a: ab03 add r3, sp, #12
|
|
8004b3c: 9301 str r3, [sp, #4]
|
|
8004b3e: ab02 add r3, sp, #8
|
|
8004b40: 9300 str r3, [sp, #0]
|
|
8004b42: ec47 6b10 vmov d0, r6, r7
|
|
8004b46: 4653 mov r3, sl
|
|
8004b48: 4622 mov r2, r4
|
|
8004b4a: f000 ff3d bl 80059c8 <_dtoa_r>
|
|
8004b4e: f1b8 0f47 cmp.w r8, #71 @ 0x47
|
|
8004b52: 4605 mov r5, r0
|
|
8004b54: d119 bne.n 8004b8a <__cvt+0x94>
|
|
8004b56: f019 0f01 tst.w r9, #1
|
|
8004b5a: d00e beq.n 8004b7a <__cvt+0x84>
|
|
8004b5c: eb00 0904 add.w r9, r0, r4
|
|
8004b60: 2200 movs r2, #0
|
|
8004b62: 2300 movs r3, #0
|
|
8004b64: 4630 mov r0, r6
|
|
8004b66: 4639 mov r1, r7
|
|
8004b68: f7fb ffae bl 8000ac8 <__aeabi_dcmpeq>
|
|
8004b6c: b108 cbz r0, 8004b72 <__cvt+0x7c>
|
|
8004b6e: f8cd 900c str.w r9, [sp, #12]
|
|
8004b72: 2230 movs r2, #48 @ 0x30
|
|
8004b74: 9b03 ldr r3, [sp, #12]
|
|
8004b76: 454b cmp r3, r9
|
|
8004b78: d31e bcc.n 8004bb8 <__cvt+0xc2>
|
|
8004b7a: 9b03 ldr r3, [sp, #12]
|
|
8004b7c: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
8004b7e: 1b5b subs r3, r3, r5
|
|
8004b80: 4628 mov r0, r5
|
|
8004b82: 6013 str r3, [r2, #0]
|
|
8004b84: b004 add sp, #16
|
|
8004b86: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8004b8a: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
8004b8e: eb00 0904 add.w r9, r0, r4
|
|
8004b92: d1e5 bne.n 8004b60 <__cvt+0x6a>
|
|
8004b94: 7803 ldrb r3, [r0, #0]
|
|
8004b96: 2b30 cmp r3, #48 @ 0x30
|
|
8004b98: d10a bne.n 8004bb0 <__cvt+0xba>
|
|
8004b9a: 2200 movs r2, #0
|
|
8004b9c: 2300 movs r3, #0
|
|
8004b9e: 4630 mov r0, r6
|
|
8004ba0: 4639 mov r1, r7
|
|
8004ba2: f7fb ff91 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8004ba6: b918 cbnz r0, 8004bb0 <__cvt+0xba>
|
|
8004ba8: f1c4 0401 rsb r4, r4, #1
|
|
8004bac: f8ca 4000 str.w r4, [sl]
|
|
8004bb0: f8da 3000 ldr.w r3, [sl]
|
|
8004bb4: 4499 add r9, r3
|
|
8004bb6: e7d3 b.n 8004b60 <__cvt+0x6a>
|
|
8004bb8: 1c59 adds r1, r3, #1
|
|
8004bba: 9103 str r1, [sp, #12]
|
|
8004bbc: 701a strb r2, [r3, #0]
|
|
8004bbe: e7d9 b.n 8004b74 <__cvt+0x7e>
|
|
|
|
08004bc0 <__exponent>:
|
|
8004bc0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
8004bc2: 2900 cmp r1, #0
|
|
8004bc4: bfba itte lt
|
|
8004bc6: 4249 neglt r1, r1
|
|
8004bc8: 232d movlt r3, #45 @ 0x2d
|
|
8004bca: 232b movge r3, #43 @ 0x2b
|
|
8004bcc: 2909 cmp r1, #9
|
|
8004bce: 7002 strb r2, [r0, #0]
|
|
8004bd0: 7043 strb r3, [r0, #1]
|
|
8004bd2: dd29 ble.n 8004c28 <__exponent+0x68>
|
|
8004bd4: f10d 0307 add.w r3, sp, #7
|
|
8004bd8: 461d mov r5, r3
|
|
8004bda: 270a movs r7, #10
|
|
8004bdc: 461a mov r2, r3
|
|
8004bde: fbb1 f6f7 udiv r6, r1, r7
|
|
8004be2: fb07 1416 mls r4, r7, r6, r1
|
|
8004be6: 3430 adds r4, #48 @ 0x30
|
|
8004be8: f802 4c01 strb.w r4, [r2, #-1]
|
|
8004bec: 460c mov r4, r1
|
|
8004bee: 2c63 cmp r4, #99 @ 0x63
|
|
8004bf0: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff
|
|
8004bf4: 4631 mov r1, r6
|
|
8004bf6: dcf1 bgt.n 8004bdc <__exponent+0x1c>
|
|
8004bf8: 3130 adds r1, #48 @ 0x30
|
|
8004bfa: 1e94 subs r4, r2, #2
|
|
8004bfc: f803 1c01 strb.w r1, [r3, #-1]
|
|
8004c00: 1c41 adds r1, r0, #1
|
|
8004c02: 4623 mov r3, r4
|
|
8004c04: 42ab cmp r3, r5
|
|
8004c06: d30a bcc.n 8004c1e <__exponent+0x5e>
|
|
8004c08: f10d 0309 add.w r3, sp, #9
|
|
8004c0c: 1a9b subs r3, r3, r2
|
|
8004c0e: 42ac cmp r4, r5
|
|
8004c10: bf88 it hi
|
|
8004c12: 2300 movhi r3, #0
|
|
8004c14: 3302 adds r3, #2
|
|
8004c16: 4403 add r3, r0
|
|
8004c18: 1a18 subs r0, r3, r0
|
|
8004c1a: b003 add sp, #12
|
|
8004c1c: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8004c1e: f813 6b01 ldrb.w r6, [r3], #1
|
|
8004c22: f801 6f01 strb.w r6, [r1, #1]!
|
|
8004c26: e7ed b.n 8004c04 <__exponent+0x44>
|
|
8004c28: 2330 movs r3, #48 @ 0x30
|
|
8004c2a: 3130 adds r1, #48 @ 0x30
|
|
8004c2c: 7083 strb r3, [r0, #2]
|
|
8004c2e: 70c1 strb r1, [r0, #3]
|
|
8004c30: 1d03 adds r3, r0, #4
|
|
8004c32: e7f1 b.n 8004c18 <__exponent+0x58>
|
|
|
|
08004c34 <_printf_float>:
|
|
8004c34: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8004c38: b08d sub sp, #52 @ 0x34
|
|
8004c3a: 460c mov r4, r1
|
|
8004c3c: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
|
|
8004c40: 4616 mov r6, r2
|
|
8004c42: 461f mov r7, r3
|
|
8004c44: 4605 mov r5, r0
|
|
8004c46: f000 fdbd bl 80057c4 <_localeconv_r>
|
|
8004c4a: 6803 ldr r3, [r0, #0]
|
|
8004c4c: 9304 str r3, [sp, #16]
|
|
8004c4e: 4618 mov r0, r3
|
|
8004c50: f7fb fb0e bl 8000270 <strlen>
|
|
8004c54: 2300 movs r3, #0
|
|
8004c56: 930a str r3, [sp, #40] @ 0x28
|
|
8004c58: f8d8 3000 ldr.w r3, [r8]
|
|
8004c5c: 9005 str r0, [sp, #20]
|
|
8004c5e: 3307 adds r3, #7
|
|
8004c60: f023 0307 bic.w r3, r3, #7
|
|
8004c64: f103 0208 add.w r2, r3, #8
|
|
8004c68: f894 a018 ldrb.w sl, [r4, #24]
|
|
8004c6c: f8d4 b000 ldr.w fp, [r4]
|
|
8004c70: f8c8 2000 str.w r2, [r8]
|
|
8004c74: e9d3 8900 ldrd r8, r9, [r3]
|
|
8004c78: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
|
|
8004c7c: 9307 str r3, [sp, #28]
|
|
8004c7e: f8cd 8018 str.w r8, [sp, #24]
|
|
8004c82: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48
|
|
8004c86: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
8004c8a: 4b9c ldr r3, [pc, #624] @ (8004efc <_printf_float+0x2c8>)
|
|
8004c8c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8004c90: f7fb ff4c bl 8000b2c <__aeabi_dcmpun>
|
|
8004c94: bb70 cbnz r0, 8004cf4 <_printf_float+0xc0>
|
|
8004c96: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
8004c9a: 4b98 ldr r3, [pc, #608] @ (8004efc <_printf_float+0x2c8>)
|
|
8004c9c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8004ca0: f7fb ff26 bl 8000af0 <__aeabi_dcmple>
|
|
8004ca4: bb30 cbnz r0, 8004cf4 <_printf_float+0xc0>
|
|
8004ca6: 2200 movs r2, #0
|
|
8004ca8: 2300 movs r3, #0
|
|
8004caa: 4640 mov r0, r8
|
|
8004cac: 4649 mov r1, r9
|
|
8004cae: f7fb ff15 bl 8000adc <__aeabi_dcmplt>
|
|
8004cb2: b110 cbz r0, 8004cba <_printf_float+0x86>
|
|
8004cb4: 232d movs r3, #45 @ 0x2d
|
|
8004cb6: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8004cba: 4a91 ldr r2, [pc, #580] @ (8004f00 <_printf_float+0x2cc>)
|
|
8004cbc: 4b91 ldr r3, [pc, #580] @ (8004f04 <_printf_float+0x2d0>)
|
|
8004cbe: f1ba 0f47 cmp.w sl, #71 @ 0x47
|
|
8004cc2: bf8c ite hi
|
|
8004cc4: 4690 movhi r8, r2
|
|
8004cc6: 4698 movls r8, r3
|
|
8004cc8: 2303 movs r3, #3
|
|
8004cca: 6123 str r3, [r4, #16]
|
|
8004ccc: f02b 0304 bic.w r3, fp, #4
|
|
8004cd0: 6023 str r3, [r4, #0]
|
|
8004cd2: f04f 0900 mov.w r9, #0
|
|
8004cd6: 9700 str r7, [sp, #0]
|
|
8004cd8: 4633 mov r3, r6
|
|
8004cda: aa0b add r2, sp, #44 @ 0x2c
|
|
8004cdc: 4621 mov r1, r4
|
|
8004cde: 4628 mov r0, r5
|
|
8004ce0: f000 f9d2 bl 8005088 <_printf_common>
|
|
8004ce4: 3001 adds r0, #1
|
|
8004ce6: f040 808d bne.w 8004e04 <_printf_float+0x1d0>
|
|
8004cea: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8004cee: b00d add sp, #52 @ 0x34
|
|
8004cf0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8004cf4: 4642 mov r2, r8
|
|
8004cf6: 464b mov r3, r9
|
|
8004cf8: 4640 mov r0, r8
|
|
8004cfa: 4649 mov r1, r9
|
|
8004cfc: f7fb ff16 bl 8000b2c <__aeabi_dcmpun>
|
|
8004d00: b140 cbz r0, 8004d14 <_printf_float+0xe0>
|
|
8004d02: 464b mov r3, r9
|
|
8004d04: 2b00 cmp r3, #0
|
|
8004d06: bfbc itt lt
|
|
8004d08: 232d movlt r3, #45 @ 0x2d
|
|
8004d0a: f884 3043 strblt.w r3, [r4, #67] @ 0x43
|
|
8004d0e: 4a7e ldr r2, [pc, #504] @ (8004f08 <_printf_float+0x2d4>)
|
|
8004d10: 4b7e ldr r3, [pc, #504] @ (8004f0c <_printf_float+0x2d8>)
|
|
8004d12: e7d4 b.n 8004cbe <_printf_float+0x8a>
|
|
8004d14: 6863 ldr r3, [r4, #4]
|
|
8004d16: f00a 02df and.w r2, sl, #223 @ 0xdf
|
|
8004d1a: 9206 str r2, [sp, #24]
|
|
8004d1c: 1c5a adds r2, r3, #1
|
|
8004d1e: d13b bne.n 8004d98 <_printf_float+0x164>
|
|
8004d20: 2306 movs r3, #6
|
|
8004d22: 6063 str r3, [r4, #4]
|
|
8004d24: f44b 6280 orr.w r2, fp, #1024 @ 0x400
|
|
8004d28: 2300 movs r3, #0
|
|
8004d2a: 6022 str r2, [r4, #0]
|
|
8004d2c: 9303 str r3, [sp, #12]
|
|
8004d2e: ab0a add r3, sp, #40 @ 0x28
|
|
8004d30: e9cd a301 strd sl, r3, [sp, #4]
|
|
8004d34: ab09 add r3, sp, #36 @ 0x24
|
|
8004d36: 9300 str r3, [sp, #0]
|
|
8004d38: 6861 ldr r1, [r4, #4]
|
|
8004d3a: ec49 8b10 vmov d0, r8, r9
|
|
8004d3e: f10d 0323 add.w r3, sp, #35 @ 0x23
|
|
8004d42: 4628 mov r0, r5
|
|
8004d44: f7ff fed7 bl 8004af6 <__cvt>
|
|
8004d48: 9b06 ldr r3, [sp, #24]
|
|
8004d4a: 9909 ldr r1, [sp, #36] @ 0x24
|
|
8004d4c: 2b47 cmp r3, #71 @ 0x47
|
|
8004d4e: 4680 mov r8, r0
|
|
8004d50: d129 bne.n 8004da6 <_printf_float+0x172>
|
|
8004d52: 1cc8 adds r0, r1, #3
|
|
8004d54: db02 blt.n 8004d5c <_printf_float+0x128>
|
|
8004d56: 6863 ldr r3, [r4, #4]
|
|
8004d58: 4299 cmp r1, r3
|
|
8004d5a: dd41 ble.n 8004de0 <_printf_float+0x1ac>
|
|
8004d5c: f1aa 0a02 sub.w sl, sl, #2
|
|
8004d60: fa5f fa8a uxtb.w sl, sl
|
|
8004d64: 3901 subs r1, #1
|
|
8004d66: 4652 mov r2, sl
|
|
8004d68: f104 0050 add.w r0, r4, #80 @ 0x50
|
|
8004d6c: 9109 str r1, [sp, #36] @ 0x24
|
|
8004d6e: f7ff ff27 bl 8004bc0 <__exponent>
|
|
8004d72: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
8004d74: 1813 adds r3, r2, r0
|
|
8004d76: 2a01 cmp r2, #1
|
|
8004d78: 4681 mov r9, r0
|
|
8004d7a: 6123 str r3, [r4, #16]
|
|
8004d7c: dc02 bgt.n 8004d84 <_printf_float+0x150>
|
|
8004d7e: 6822 ldr r2, [r4, #0]
|
|
8004d80: 07d2 lsls r2, r2, #31
|
|
8004d82: d501 bpl.n 8004d88 <_printf_float+0x154>
|
|
8004d84: 3301 adds r3, #1
|
|
8004d86: 6123 str r3, [r4, #16]
|
|
8004d88: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
|
|
8004d8c: 2b00 cmp r3, #0
|
|
8004d8e: d0a2 beq.n 8004cd6 <_printf_float+0xa2>
|
|
8004d90: 232d movs r3, #45 @ 0x2d
|
|
8004d92: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8004d96: e79e b.n 8004cd6 <_printf_float+0xa2>
|
|
8004d98: 9a06 ldr r2, [sp, #24]
|
|
8004d9a: 2a47 cmp r2, #71 @ 0x47
|
|
8004d9c: d1c2 bne.n 8004d24 <_printf_float+0xf0>
|
|
8004d9e: 2b00 cmp r3, #0
|
|
8004da0: d1c0 bne.n 8004d24 <_printf_float+0xf0>
|
|
8004da2: 2301 movs r3, #1
|
|
8004da4: e7bd b.n 8004d22 <_printf_float+0xee>
|
|
8004da6: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
8004daa: d9db bls.n 8004d64 <_printf_float+0x130>
|
|
8004dac: f1ba 0f66 cmp.w sl, #102 @ 0x66
|
|
8004db0: d118 bne.n 8004de4 <_printf_float+0x1b0>
|
|
8004db2: 2900 cmp r1, #0
|
|
8004db4: 6863 ldr r3, [r4, #4]
|
|
8004db6: dd0b ble.n 8004dd0 <_printf_float+0x19c>
|
|
8004db8: 6121 str r1, [r4, #16]
|
|
8004dba: b913 cbnz r3, 8004dc2 <_printf_float+0x18e>
|
|
8004dbc: 6822 ldr r2, [r4, #0]
|
|
8004dbe: 07d0 lsls r0, r2, #31
|
|
8004dc0: d502 bpl.n 8004dc8 <_printf_float+0x194>
|
|
8004dc2: 3301 adds r3, #1
|
|
8004dc4: 440b add r3, r1
|
|
8004dc6: 6123 str r3, [r4, #16]
|
|
8004dc8: 65a1 str r1, [r4, #88] @ 0x58
|
|
8004dca: f04f 0900 mov.w r9, #0
|
|
8004dce: e7db b.n 8004d88 <_printf_float+0x154>
|
|
8004dd0: b913 cbnz r3, 8004dd8 <_printf_float+0x1a4>
|
|
8004dd2: 6822 ldr r2, [r4, #0]
|
|
8004dd4: 07d2 lsls r2, r2, #31
|
|
8004dd6: d501 bpl.n 8004ddc <_printf_float+0x1a8>
|
|
8004dd8: 3302 adds r3, #2
|
|
8004dda: e7f4 b.n 8004dc6 <_printf_float+0x192>
|
|
8004ddc: 2301 movs r3, #1
|
|
8004dde: e7f2 b.n 8004dc6 <_printf_float+0x192>
|
|
8004de0: f04f 0a67 mov.w sl, #103 @ 0x67
|
|
8004de4: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
8004de6: 4299 cmp r1, r3
|
|
8004de8: db05 blt.n 8004df6 <_printf_float+0x1c2>
|
|
8004dea: 6823 ldr r3, [r4, #0]
|
|
8004dec: 6121 str r1, [r4, #16]
|
|
8004dee: 07d8 lsls r0, r3, #31
|
|
8004df0: d5ea bpl.n 8004dc8 <_printf_float+0x194>
|
|
8004df2: 1c4b adds r3, r1, #1
|
|
8004df4: e7e7 b.n 8004dc6 <_printf_float+0x192>
|
|
8004df6: 2900 cmp r1, #0
|
|
8004df8: bfd4 ite le
|
|
8004dfa: f1c1 0202 rsble r2, r1, #2
|
|
8004dfe: 2201 movgt r2, #1
|
|
8004e00: 4413 add r3, r2
|
|
8004e02: e7e0 b.n 8004dc6 <_printf_float+0x192>
|
|
8004e04: 6823 ldr r3, [r4, #0]
|
|
8004e06: 055a lsls r2, r3, #21
|
|
8004e08: d407 bmi.n 8004e1a <_printf_float+0x1e6>
|
|
8004e0a: 6923 ldr r3, [r4, #16]
|
|
8004e0c: 4642 mov r2, r8
|
|
8004e0e: 4631 mov r1, r6
|
|
8004e10: 4628 mov r0, r5
|
|
8004e12: 47b8 blx r7
|
|
8004e14: 3001 adds r0, #1
|
|
8004e16: d12b bne.n 8004e70 <_printf_float+0x23c>
|
|
8004e18: e767 b.n 8004cea <_printf_float+0xb6>
|
|
8004e1a: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
8004e1e: f240 80dd bls.w 8004fdc <_printf_float+0x3a8>
|
|
8004e22: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
8004e26: 2200 movs r2, #0
|
|
8004e28: 2300 movs r3, #0
|
|
8004e2a: f7fb fe4d bl 8000ac8 <__aeabi_dcmpeq>
|
|
8004e2e: 2800 cmp r0, #0
|
|
8004e30: d033 beq.n 8004e9a <_printf_float+0x266>
|
|
8004e32: 4a37 ldr r2, [pc, #220] @ (8004f10 <_printf_float+0x2dc>)
|
|
8004e34: 2301 movs r3, #1
|
|
8004e36: 4631 mov r1, r6
|
|
8004e38: 4628 mov r0, r5
|
|
8004e3a: 47b8 blx r7
|
|
8004e3c: 3001 adds r0, #1
|
|
8004e3e: f43f af54 beq.w 8004cea <_printf_float+0xb6>
|
|
8004e42: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
|
|
8004e46: 4543 cmp r3, r8
|
|
8004e48: db02 blt.n 8004e50 <_printf_float+0x21c>
|
|
8004e4a: 6823 ldr r3, [r4, #0]
|
|
8004e4c: 07d8 lsls r0, r3, #31
|
|
8004e4e: d50f bpl.n 8004e70 <_printf_float+0x23c>
|
|
8004e50: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8004e54: 4631 mov r1, r6
|
|
8004e56: 4628 mov r0, r5
|
|
8004e58: 47b8 blx r7
|
|
8004e5a: 3001 adds r0, #1
|
|
8004e5c: f43f af45 beq.w 8004cea <_printf_float+0xb6>
|
|
8004e60: f04f 0900 mov.w r9, #0
|
|
8004e64: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
|
|
8004e68: f104 0a1a add.w sl, r4, #26
|
|
8004e6c: 45c8 cmp r8, r9
|
|
8004e6e: dc09 bgt.n 8004e84 <_printf_float+0x250>
|
|
8004e70: 6823 ldr r3, [r4, #0]
|
|
8004e72: 079b lsls r3, r3, #30
|
|
8004e74: f100 8103 bmi.w 800507e <_printf_float+0x44a>
|
|
8004e78: 68e0 ldr r0, [r4, #12]
|
|
8004e7a: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8004e7c: 4298 cmp r0, r3
|
|
8004e7e: bfb8 it lt
|
|
8004e80: 4618 movlt r0, r3
|
|
8004e82: e734 b.n 8004cee <_printf_float+0xba>
|
|
8004e84: 2301 movs r3, #1
|
|
8004e86: 4652 mov r2, sl
|
|
8004e88: 4631 mov r1, r6
|
|
8004e8a: 4628 mov r0, r5
|
|
8004e8c: 47b8 blx r7
|
|
8004e8e: 3001 adds r0, #1
|
|
8004e90: f43f af2b beq.w 8004cea <_printf_float+0xb6>
|
|
8004e94: f109 0901 add.w r9, r9, #1
|
|
8004e98: e7e8 b.n 8004e6c <_printf_float+0x238>
|
|
8004e9a: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8004e9c: 2b00 cmp r3, #0
|
|
8004e9e: dc39 bgt.n 8004f14 <_printf_float+0x2e0>
|
|
8004ea0: 4a1b ldr r2, [pc, #108] @ (8004f10 <_printf_float+0x2dc>)
|
|
8004ea2: 2301 movs r3, #1
|
|
8004ea4: 4631 mov r1, r6
|
|
8004ea6: 4628 mov r0, r5
|
|
8004ea8: 47b8 blx r7
|
|
8004eaa: 3001 adds r0, #1
|
|
8004eac: f43f af1d beq.w 8004cea <_printf_float+0xb6>
|
|
8004eb0: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
|
|
8004eb4: ea59 0303 orrs.w r3, r9, r3
|
|
8004eb8: d102 bne.n 8004ec0 <_printf_float+0x28c>
|
|
8004eba: 6823 ldr r3, [r4, #0]
|
|
8004ebc: 07d9 lsls r1, r3, #31
|
|
8004ebe: d5d7 bpl.n 8004e70 <_printf_float+0x23c>
|
|
8004ec0: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8004ec4: 4631 mov r1, r6
|
|
8004ec6: 4628 mov r0, r5
|
|
8004ec8: 47b8 blx r7
|
|
8004eca: 3001 adds r0, #1
|
|
8004ecc: f43f af0d beq.w 8004cea <_printf_float+0xb6>
|
|
8004ed0: f04f 0a00 mov.w sl, #0
|
|
8004ed4: f104 0b1a add.w fp, r4, #26
|
|
8004ed8: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8004eda: 425b negs r3, r3
|
|
8004edc: 4553 cmp r3, sl
|
|
8004ede: dc01 bgt.n 8004ee4 <_printf_float+0x2b0>
|
|
8004ee0: 464b mov r3, r9
|
|
8004ee2: e793 b.n 8004e0c <_printf_float+0x1d8>
|
|
8004ee4: 2301 movs r3, #1
|
|
8004ee6: 465a mov r2, fp
|
|
8004ee8: 4631 mov r1, r6
|
|
8004eea: 4628 mov r0, r5
|
|
8004eec: 47b8 blx r7
|
|
8004eee: 3001 adds r0, #1
|
|
8004ef0: f43f aefb beq.w 8004cea <_printf_float+0xb6>
|
|
8004ef4: f10a 0a01 add.w sl, sl, #1
|
|
8004ef8: e7ee b.n 8004ed8 <_printf_float+0x2a4>
|
|
8004efa: bf00 nop
|
|
8004efc: 7fefffff .word 0x7fefffff
|
|
8004f00: 08007558 .word 0x08007558
|
|
8004f04: 08007554 .word 0x08007554
|
|
8004f08: 08007560 .word 0x08007560
|
|
8004f0c: 0800755c .word 0x0800755c
|
|
8004f10: 08007564 .word 0x08007564
|
|
8004f14: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
8004f16: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
8004f1a: 4553 cmp r3, sl
|
|
8004f1c: bfa8 it ge
|
|
8004f1e: 4653 movge r3, sl
|
|
8004f20: 2b00 cmp r3, #0
|
|
8004f22: 4699 mov r9, r3
|
|
8004f24: dc36 bgt.n 8004f94 <_printf_float+0x360>
|
|
8004f26: f04f 0b00 mov.w fp, #0
|
|
8004f2a: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
8004f2e: f104 021a add.w r2, r4, #26
|
|
8004f32: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
8004f34: 9306 str r3, [sp, #24]
|
|
8004f36: eba3 0309 sub.w r3, r3, r9
|
|
8004f3a: 455b cmp r3, fp
|
|
8004f3c: dc31 bgt.n 8004fa2 <_printf_float+0x36e>
|
|
8004f3e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8004f40: 459a cmp sl, r3
|
|
8004f42: dc3a bgt.n 8004fba <_printf_float+0x386>
|
|
8004f44: 6823 ldr r3, [r4, #0]
|
|
8004f46: 07da lsls r2, r3, #31
|
|
8004f48: d437 bmi.n 8004fba <_printf_float+0x386>
|
|
8004f4a: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8004f4c: ebaa 0903 sub.w r9, sl, r3
|
|
8004f50: 9b06 ldr r3, [sp, #24]
|
|
8004f52: ebaa 0303 sub.w r3, sl, r3
|
|
8004f56: 4599 cmp r9, r3
|
|
8004f58: bfa8 it ge
|
|
8004f5a: 4699 movge r9, r3
|
|
8004f5c: f1b9 0f00 cmp.w r9, #0
|
|
8004f60: dc33 bgt.n 8004fca <_printf_float+0x396>
|
|
8004f62: f04f 0800 mov.w r8, #0
|
|
8004f66: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
8004f6a: f104 0b1a add.w fp, r4, #26
|
|
8004f6e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8004f70: ebaa 0303 sub.w r3, sl, r3
|
|
8004f74: eba3 0309 sub.w r3, r3, r9
|
|
8004f78: 4543 cmp r3, r8
|
|
8004f7a: f77f af79 ble.w 8004e70 <_printf_float+0x23c>
|
|
8004f7e: 2301 movs r3, #1
|
|
8004f80: 465a mov r2, fp
|
|
8004f82: 4631 mov r1, r6
|
|
8004f84: 4628 mov r0, r5
|
|
8004f86: 47b8 blx r7
|
|
8004f88: 3001 adds r0, #1
|
|
8004f8a: f43f aeae beq.w 8004cea <_printf_float+0xb6>
|
|
8004f8e: f108 0801 add.w r8, r8, #1
|
|
8004f92: e7ec b.n 8004f6e <_printf_float+0x33a>
|
|
8004f94: 4642 mov r2, r8
|
|
8004f96: 4631 mov r1, r6
|
|
8004f98: 4628 mov r0, r5
|
|
8004f9a: 47b8 blx r7
|
|
8004f9c: 3001 adds r0, #1
|
|
8004f9e: d1c2 bne.n 8004f26 <_printf_float+0x2f2>
|
|
8004fa0: e6a3 b.n 8004cea <_printf_float+0xb6>
|
|
8004fa2: 2301 movs r3, #1
|
|
8004fa4: 4631 mov r1, r6
|
|
8004fa6: 4628 mov r0, r5
|
|
8004fa8: 9206 str r2, [sp, #24]
|
|
8004faa: 47b8 blx r7
|
|
8004fac: 3001 adds r0, #1
|
|
8004fae: f43f ae9c beq.w 8004cea <_printf_float+0xb6>
|
|
8004fb2: 9a06 ldr r2, [sp, #24]
|
|
8004fb4: f10b 0b01 add.w fp, fp, #1
|
|
8004fb8: e7bb b.n 8004f32 <_printf_float+0x2fe>
|
|
8004fba: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8004fbe: 4631 mov r1, r6
|
|
8004fc0: 4628 mov r0, r5
|
|
8004fc2: 47b8 blx r7
|
|
8004fc4: 3001 adds r0, #1
|
|
8004fc6: d1c0 bne.n 8004f4a <_printf_float+0x316>
|
|
8004fc8: e68f b.n 8004cea <_printf_float+0xb6>
|
|
8004fca: 9a06 ldr r2, [sp, #24]
|
|
8004fcc: 464b mov r3, r9
|
|
8004fce: 4442 add r2, r8
|
|
8004fd0: 4631 mov r1, r6
|
|
8004fd2: 4628 mov r0, r5
|
|
8004fd4: 47b8 blx r7
|
|
8004fd6: 3001 adds r0, #1
|
|
8004fd8: d1c3 bne.n 8004f62 <_printf_float+0x32e>
|
|
8004fda: e686 b.n 8004cea <_printf_float+0xb6>
|
|
8004fdc: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
8004fe0: f1ba 0f01 cmp.w sl, #1
|
|
8004fe4: dc01 bgt.n 8004fea <_printf_float+0x3b6>
|
|
8004fe6: 07db lsls r3, r3, #31
|
|
8004fe8: d536 bpl.n 8005058 <_printf_float+0x424>
|
|
8004fea: 2301 movs r3, #1
|
|
8004fec: 4642 mov r2, r8
|
|
8004fee: 4631 mov r1, r6
|
|
8004ff0: 4628 mov r0, r5
|
|
8004ff2: 47b8 blx r7
|
|
8004ff4: 3001 adds r0, #1
|
|
8004ff6: f43f ae78 beq.w 8004cea <_printf_float+0xb6>
|
|
8004ffa: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8004ffe: 4631 mov r1, r6
|
|
8005000: 4628 mov r0, r5
|
|
8005002: 47b8 blx r7
|
|
8005004: 3001 adds r0, #1
|
|
8005006: f43f ae70 beq.w 8004cea <_printf_float+0xb6>
|
|
800500a: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
800500e: 2200 movs r2, #0
|
|
8005010: 2300 movs r3, #0
|
|
8005012: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
8005016: f7fb fd57 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800501a: b9c0 cbnz r0, 800504e <_printf_float+0x41a>
|
|
800501c: 4653 mov r3, sl
|
|
800501e: f108 0201 add.w r2, r8, #1
|
|
8005022: 4631 mov r1, r6
|
|
8005024: 4628 mov r0, r5
|
|
8005026: 47b8 blx r7
|
|
8005028: 3001 adds r0, #1
|
|
800502a: d10c bne.n 8005046 <_printf_float+0x412>
|
|
800502c: e65d b.n 8004cea <_printf_float+0xb6>
|
|
800502e: 2301 movs r3, #1
|
|
8005030: 465a mov r2, fp
|
|
8005032: 4631 mov r1, r6
|
|
8005034: 4628 mov r0, r5
|
|
8005036: 47b8 blx r7
|
|
8005038: 3001 adds r0, #1
|
|
800503a: f43f ae56 beq.w 8004cea <_printf_float+0xb6>
|
|
800503e: f108 0801 add.w r8, r8, #1
|
|
8005042: 45d0 cmp r8, sl
|
|
8005044: dbf3 blt.n 800502e <_printf_float+0x3fa>
|
|
8005046: 464b mov r3, r9
|
|
8005048: f104 0250 add.w r2, r4, #80 @ 0x50
|
|
800504c: e6df b.n 8004e0e <_printf_float+0x1da>
|
|
800504e: f04f 0800 mov.w r8, #0
|
|
8005052: f104 0b1a add.w fp, r4, #26
|
|
8005056: e7f4 b.n 8005042 <_printf_float+0x40e>
|
|
8005058: 2301 movs r3, #1
|
|
800505a: 4642 mov r2, r8
|
|
800505c: e7e1 b.n 8005022 <_printf_float+0x3ee>
|
|
800505e: 2301 movs r3, #1
|
|
8005060: 464a mov r2, r9
|
|
8005062: 4631 mov r1, r6
|
|
8005064: 4628 mov r0, r5
|
|
8005066: 47b8 blx r7
|
|
8005068: 3001 adds r0, #1
|
|
800506a: f43f ae3e beq.w 8004cea <_printf_float+0xb6>
|
|
800506e: f108 0801 add.w r8, r8, #1
|
|
8005072: 68e3 ldr r3, [r4, #12]
|
|
8005074: 990b ldr r1, [sp, #44] @ 0x2c
|
|
8005076: 1a5b subs r3, r3, r1
|
|
8005078: 4543 cmp r3, r8
|
|
800507a: dcf0 bgt.n 800505e <_printf_float+0x42a>
|
|
800507c: e6fc b.n 8004e78 <_printf_float+0x244>
|
|
800507e: f04f 0800 mov.w r8, #0
|
|
8005082: f104 0919 add.w r9, r4, #25
|
|
8005086: e7f4 b.n 8005072 <_printf_float+0x43e>
|
|
|
|
08005088 <_printf_common>:
|
|
8005088: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800508c: 4616 mov r6, r2
|
|
800508e: 4698 mov r8, r3
|
|
8005090: 688a ldr r2, [r1, #8]
|
|
8005092: 690b ldr r3, [r1, #16]
|
|
8005094: f8dd 9020 ldr.w r9, [sp, #32]
|
|
8005098: 4293 cmp r3, r2
|
|
800509a: bfb8 it lt
|
|
800509c: 4613 movlt r3, r2
|
|
800509e: 6033 str r3, [r6, #0]
|
|
80050a0: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
|
|
80050a4: 4607 mov r7, r0
|
|
80050a6: 460c mov r4, r1
|
|
80050a8: b10a cbz r2, 80050ae <_printf_common+0x26>
|
|
80050aa: 3301 adds r3, #1
|
|
80050ac: 6033 str r3, [r6, #0]
|
|
80050ae: 6823 ldr r3, [r4, #0]
|
|
80050b0: 0699 lsls r1, r3, #26
|
|
80050b2: bf42 ittt mi
|
|
80050b4: 6833 ldrmi r3, [r6, #0]
|
|
80050b6: 3302 addmi r3, #2
|
|
80050b8: 6033 strmi r3, [r6, #0]
|
|
80050ba: 6825 ldr r5, [r4, #0]
|
|
80050bc: f015 0506 ands.w r5, r5, #6
|
|
80050c0: d106 bne.n 80050d0 <_printf_common+0x48>
|
|
80050c2: f104 0a19 add.w sl, r4, #25
|
|
80050c6: 68e3 ldr r3, [r4, #12]
|
|
80050c8: 6832 ldr r2, [r6, #0]
|
|
80050ca: 1a9b subs r3, r3, r2
|
|
80050cc: 42ab cmp r3, r5
|
|
80050ce: dc26 bgt.n 800511e <_printf_common+0x96>
|
|
80050d0: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
|
|
80050d4: 6822 ldr r2, [r4, #0]
|
|
80050d6: 3b00 subs r3, #0
|
|
80050d8: bf18 it ne
|
|
80050da: 2301 movne r3, #1
|
|
80050dc: 0692 lsls r2, r2, #26
|
|
80050de: d42b bmi.n 8005138 <_printf_common+0xb0>
|
|
80050e0: f104 0243 add.w r2, r4, #67 @ 0x43
|
|
80050e4: 4641 mov r1, r8
|
|
80050e6: 4638 mov r0, r7
|
|
80050e8: 47c8 blx r9
|
|
80050ea: 3001 adds r0, #1
|
|
80050ec: d01e beq.n 800512c <_printf_common+0xa4>
|
|
80050ee: 6823 ldr r3, [r4, #0]
|
|
80050f0: 6922 ldr r2, [r4, #16]
|
|
80050f2: f003 0306 and.w r3, r3, #6
|
|
80050f6: 2b04 cmp r3, #4
|
|
80050f8: bf02 ittt eq
|
|
80050fa: 68e5 ldreq r5, [r4, #12]
|
|
80050fc: 6833 ldreq r3, [r6, #0]
|
|
80050fe: 1aed subeq r5, r5, r3
|
|
8005100: 68a3 ldr r3, [r4, #8]
|
|
8005102: bf0c ite eq
|
|
8005104: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
8005108: 2500 movne r5, #0
|
|
800510a: 4293 cmp r3, r2
|
|
800510c: bfc4 itt gt
|
|
800510e: 1a9b subgt r3, r3, r2
|
|
8005110: 18ed addgt r5, r5, r3
|
|
8005112: 2600 movs r6, #0
|
|
8005114: 341a adds r4, #26
|
|
8005116: 42b5 cmp r5, r6
|
|
8005118: d11a bne.n 8005150 <_printf_common+0xc8>
|
|
800511a: 2000 movs r0, #0
|
|
800511c: e008 b.n 8005130 <_printf_common+0xa8>
|
|
800511e: 2301 movs r3, #1
|
|
8005120: 4652 mov r2, sl
|
|
8005122: 4641 mov r1, r8
|
|
8005124: 4638 mov r0, r7
|
|
8005126: 47c8 blx r9
|
|
8005128: 3001 adds r0, #1
|
|
800512a: d103 bne.n 8005134 <_printf_common+0xac>
|
|
800512c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8005130: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8005134: 3501 adds r5, #1
|
|
8005136: e7c6 b.n 80050c6 <_printf_common+0x3e>
|
|
8005138: 18e1 adds r1, r4, r3
|
|
800513a: 1c5a adds r2, r3, #1
|
|
800513c: 2030 movs r0, #48 @ 0x30
|
|
800513e: f881 0043 strb.w r0, [r1, #67] @ 0x43
|
|
8005142: 4422 add r2, r4
|
|
8005144: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
|
|
8005148: f882 1043 strb.w r1, [r2, #67] @ 0x43
|
|
800514c: 3302 adds r3, #2
|
|
800514e: e7c7 b.n 80050e0 <_printf_common+0x58>
|
|
8005150: 2301 movs r3, #1
|
|
8005152: 4622 mov r2, r4
|
|
8005154: 4641 mov r1, r8
|
|
8005156: 4638 mov r0, r7
|
|
8005158: 47c8 blx r9
|
|
800515a: 3001 adds r0, #1
|
|
800515c: d0e6 beq.n 800512c <_printf_common+0xa4>
|
|
800515e: 3601 adds r6, #1
|
|
8005160: e7d9 b.n 8005116 <_printf_common+0x8e>
|
|
...
|
|
|
|
08005164 <_printf_i>:
|
|
8005164: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8005168: 7e0f ldrb r7, [r1, #24]
|
|
800516a: 9e0c ldr r6, [sp, #48] @ 0x30
|
|
800516c: 2f78 cmp r7, #120 @ 0x78
|
|
800516e: 4691 mov r9, r2
|
|
8005170: 4680 mov r8, r0
|
|
8005172: 460c mov r4, r1
|
|
8005174: 469a mov sl, r3
|
|
8005176: f101 0243 add.w r2, r1, #67 @ 0x43
|
|
800517a: d807 bhi.n 800518c <_printf_i+0x28>
|
|
800517c: 2f62 cmp r7, #98 @ 0x62
|
|
800517e: d80a bhi.n 8005196 <_printf_i+0x32>
|
|
8005180: 2f00 cmp r7, #0
|
|
8005182: f000 80d1 beq.w 8005328 <_printf_i+0x1c4>
|
|
8005186: 2f58 cmp r7, #88 @ 0x58
|
|
8005188: f000 80b8 beq.w 80052fc <_printf_i+0x198>
|
|
800518c: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8005190: f884 7042 strb.w r7, [r4, #66] @ 0x42
|
|
8005194: e03a b.n 800520c <_printf_i+0xa8>
|
|
8005196: f1a7 0363 sub.w r3, r7, #99 @ 0x63
|
|
800519a: 2b15 cmp r3, #21
|
|
800519c: d8f6 bhi.n 800518c <_printf_i+0x28>
|
|
800519e: a101 add r1, pc, #4 @ (adr r1, 80051a4 <_printf_i+0x40>)
|
|
80051a0: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
80051a4: 080051fd .word 0x080051fd
|
|
80051a8: 08005211 .word 0x08005211
|
|
80051ac: 0800518d .word 0x0800518d
|
|
80051b0: 0800518d .word 0x0800518d
|
|
80051b4: 0800518d .word 0x0800518d
|
|
80051b8: 0800518d .word 0x0800518d
|
|
80051bc: 08005211 .word 0x08005211
|
|
80051c0: 0800518d .word 0x0800518d
|
|
80051c4: 0800518d .word 0x0800518d
|
|
80051c8: 0800518d .word 0x0800518d
|
|
80051cc: 0800518d .word 0x0800518d
|
|
80051d0: 0800530f .word 0x0800530f
|
|
80051d4: 0800523b .word 0x0800523b
|
|
80051d8: 080052c9 .word 0x080052c9
|
|
80051dc: 0800518d .word 0x0800518d
|
|
80051e0: 0800518d .word 0x0800518d
|
|
80051e4: 08005331 .word 0x08005331
|
|
80051e8: 0800518d .word 0x0800518d
|
|
80051ec: 0800523b .word 0x0800523b
|
|
80051f0: 0800518d .word 0x0800518d
|
|
80051f4: 0800518d .word 0x0800518d
|
|
80051f8: 080052d1 .word 0x080052d1
|
|
80051fc: 6833 ldr r3, [r6, #0]
|
|
80051fe: 1d1a adds r2, r3, #4
|
|
8005200: 681b ldr r3, [r3, #0]
|
|
8005202: 6032 str r2, [r6, #0]
|
|
8005204: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8005208: f884 3042 strb.w r3, [r4, #66] @ 0x42
|
|
800520c: 2301 movs r3, #1
|
|
800520e: e09c b.n 800534a <_printf_i+0x1e6>
|
|
8005210: 6833 ldr r3, [r6, #0]
|
|
8005212: 6820 ldr r0, [r4, #0]
|
|
8005214: 1d19 adds r1, r3, #4
|
|
8005216: 6031 str r1, [r6, #0]
|
|
8005218: 0606 lsls r6, r0, #24
|
|
800521a: d501 bpl.n 8005220 <_printf_i+0xbc>
|
|
800521c: 681d ldr r5, [r3, #0]
|
|
800521e: e003 b.n 8005228 <_printf_i+0xc4>
|
|
8005220: 0645 lsls r5, r0, #25
|
|
8005222: d5fb bpl.n 800521c <_printf_i+0xb8>
|
|
8005224: f9b3 5000 ldrsh.w r5, [r3]
|
|
8005228: 2d00 cmp r5, #0
|
|
800522a: da03 bge.n 8005234 <_printf_i+0xd0>
|
|
800522c: 232d movs r3, #45 @ 0x2d
|
|
800522e: 426d negs r5, r5
|
|
8005230: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8005234: 4858 ldr r0, [pc, #352] @ (8005398 <_printf_i+0x234>)
|
|
8005236: 230a movs r3, #10
|
|
8005238: e011 b.n 800525e <_printf_i+0xfa>
|
|
800523a: 6821 ldr r1, [r4, #0]
|
|
800523c: 6833 ldr r3, [r6, #0]
|
|
800523e: 0608 lsls r0, r1, #24
|
|
8005240: f853 5b04 ldr.w r5, [r3], #4
|
|
8005244: d402 bmi.n 800524c <_printf_i+0xe8>
|
|
8005246: 0649 lsls r1, r1, #25
|
|
8005248: bf48 it mi
|
|
800524a: b2ad uxthmi r5, r5
|
|
800524c: 2f6f cmp r7, #111 @ 0x6f
|
|
800524e: 4852 ldr r0, [pc, #328] @ (8005398 <_printf_i+0x234>)
|
|
8005250: 6033 str r3, [r6, #0]
|
|
8005252: bf14 ite ne
|
|
8005254: 230a movne r3, #10
|
|
8005256: 2308 moveq r3, #8
|
|
8005258: 2100 movs r1, #0
|
|
800525a: f884 1043 strb.w r1, [r4, #67] @ 0x43
|
|
800525e: 6866 ldr r6, [r4, #4]
|
|
8005260: 60a6 str r6, [r4, #8]
|
|
8005262: 2e00 cmp r6, #0
|
|
8005264: db05 blt.n 8005272 <_printf_i+0x10e>
|
|
8005266: 6821 ldr r1, [r4, #0]
|
|
8005268: 432e orrs r6, r5
|
|
800526a: f021 0104 bic.w r1, r1, #4
|
|
800526e: 6021 str r1, [r4, #0]
|
|
8005270: d04b beq.n 800530a <_printf_i+0x1a6>
|
|
8005272: 4616 mov r6, r2
|
|
8005274: fbb5 f1f3 udiv r1, r5, r3
|
|
8005278: fb03 5711 mls r7, r3, r1, r5
|
|
800527c: 5dc7 ldrb r7, [r0, r7]
|
|
800527e: f806 7d01 strb.w r7, [r6, #-1]!
|
|
8005282: 462f mov r7, r5
|
|
8005284: 42bb cmp r3, r7
|
|
8005286: 460d mov r5, r1
|
|
8005288: d9f4 bls.n 8005274 <_printf_i+0x110>
|
|
800528a: 2b08 cmp r3, #8
|
|
800528c: d10b bne.n 80052a6 <_printf_i+0x142>
|
|
800528e: 6823 ldr r3, [r4, #0]
|
|
8005290: 07df lsls r7, r3, #31
|
|
8005292: d508 bpl.n 80052a6 <_printf_i+0x142>
|
|
8005294: 6923 ldr r3, [r4, #16]
|
|
8005296: 6861 ldr r1, [r4, #4]
|
|
8005298: 4299 cmp r1, r3
|
|
800529a: bfde ittt le
|
|
800529c: 2330 movle r3, #48 @ 0x30
|
|
800529e: f806 3c01 strble.w r3, [r6, #-1]
|
|
80052a2: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
|
|
80052a6: 1b92 subs r2, r2, r6
|
|
80052a8: 6122 str r2, [r4, #16]
|
|
80052aa: f8cd a000 str.w sl, [sp]
|
|
80052ae: 464b mov r3, r9
|
|
80052b0: aa03 add r2, sp, #12
|
|
80052b2: 4621 mov r1, r4
|
|
80052b4: 4640 mov r0, r8
|
|
80052b6: f7ff fee7 bl 8005088 <_printf_common>
|
|
80052ba: 3001 adds r0, #1
|
|
80052bc: d14a bne.n 8005354 <_printf_i+0x1f0>
|
|
80052be: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80052c2: b004 add sp, #16
|
|
80052c4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
80052c8: 6823 ldr r3, [r4, #0]
|
|
80052ca: f043 0320 orr.w r3, r3, #32
|
|
80052ce: 6023 str r3, [r4, #0]
|
|
80052d0: 4832 ldr r0, [pc, #200] @ (800539c <_printf_i+0x238>)
|
|
80052d2: 2778 movs r7, #120 @ 0x78
|
|
80052d4: f884 7045 strb.w r7, [r4, #69] @ 0x45
|
|
80052d8: 6823 ldr r3, [r4, #0]
|
|
80052da: 6831 ldr r1, [r6, #0]
|
|
80052dc: 061f lsls r7, r3, #24
|
|
80052de: f851 5b04 ldr.w r5, [r1], #4
|
|
80052e2: d402 bmi.n 80052ea <_printf_i+0x186>
|
|
80052e4: 065f lsls r7, r3, #25
|
|
80052e6: bf48 it mi
|
|
80052e8: b2ad uxthmi r5, r5
|
|
80052ea: 6031 str r1, [r6, #0]
|
|
80052ec: 07d9 lsls r1, r3, #31
|
|
80052ee: bf44 itt mi
|
|
80052f0: f043 0320 orrmi.w r3, r3, #32
|
|
80052f4: 6023 strmi r3, [r4, #0]
|
|
80052f6: b11d cbz r5, 8005300 <_printf_i+0x19c>
|
|
80052f8: 2310 movs r3, #16
|
|
80052fa: e7ad b.n 8005258 <_printf_i+0xf4>
|
|
80052fc: 4826 ldr r0, [pc, #152] @ (8005398 <_printf_i+0x234>)
|
|
80052fe: e7e9 b.n 80052d4 <_printf_i+0x170>
|
|
8005300: 6823 ldr r3, [r4, #0]
|
|
8005302: f023 0320 bic.w r3, r3, #32
|
|
8005306: 6023 str r3, [r4, #0]
|
|
8005308: e7f6 b.n 80052f8 <_printf_i+0x194>
|
|
800530a: 4616 mov r6, r2
|
|
800530c: e7bd b.n 800528a <_printf_i+0x126>
|
|
800530e: 6833 ldr r3, [r6, #0]
|
|
8005310: 6825 ldr r5, [r4, #0]
|
|
8005312: 6961 ldr r1, [r4, #20]
|
|
8005314: 1d18 adds r0, r3, #4
|
|
8005316: 6030 str r0, [r6, #0]
|
|
8005318: 062e lsls r6, r5, #24
|
|
800531a: 681b ldr r3, [r3, #0]
|
|
800531c: d501 bpl.n 8005322 <_printf_i+0x1be>
|
|
800531e: 6019 str r1, [r3, #0]
|
|
8005320: e002 b.n 8005328 <_printf_i+0x1c4>
|
|
8005322: 0668 lsls r0, r5, #25
|
|
8005324: d5fb bpl.n 800531e <_printf_i+0x1ba>
|
|
8005326: 8019 strh r1, [r3, #0]
|
|
8005328: 2300 movs r3, #0
|
|
800532a: 6123 str r3, [r4, #16]
|
|
800532c: 4616 mov r6, r2
|
|
800532e: e7bc b.n 80052aa <_printf_i+0x146>
|
|
8005330: 6833 ldr r3, [r6, #0]
|
|
8005332: 1d1a adds r2, r3, #4
|
|
8005334: 6032 str r2, [r6, #0]
|
|
8005336: 681e ldr r6, [r3, #0]
|
|
8005338: 6862 ldr r2, [r4, #4]
|
|
800533a: 2100 movs r1, #0
|
|
800533c: 4630 mov r0, r6
|
|
800533e: f7fa ff47 bl 80001d0 <memchr>
|
|
8005342: b108 cbz r0, 8005348 <_printf_i+0x1e4>
|
|
8005344: 1b80 subs r0, r0, r6
|
|
8005346: 6060 str r0, [r4, #4]
|
|
8005348: 6863 ldr r3, [r4, #4]
|
|
800534a: 6123 str r3, [r4, #16]
|
|
800534c: 2300 movs r3, #0
|
|
800534e: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8005352: e7aa b.n 80052aa <_printf_i+0x146>
|
|
8005354: 6923 ldr r3, [r4, #16]
|
|
8005356: 4632 mov r2, r6
|
|
8005358: 4649 mov r1, r9
|
|
800535a: 4640 mov r0, r8
|
|
800535c: 47d0 blx sl
|
|
800535e: 3001 adds r0, #1
|
|
8005360: d0ad beq.n 80052be <_printf_i+0x15a>
|
|
8005362: 6823 ldr r3, [r4, #0]
|
|
8005364: 079b lsls r3, r3, #30
|
|
8005366: d413 bmi.n 8005390 <_printf_i+0x22c>
|
|
8005368: 68e0 ldr r0, [r4, #12]
|
|
800536a: 9b03 ldr r3, [sp, #12]
|
|
800536c: 4298 cmp r0, r3
|
|
800536e: bfb8 it lt
|
|
8005370: 4618 movlt r0, r3
|
|
8005372: e7a6 b.n 80052c2 <_printf_i+0x15e>
|
|
8005374: 2301 movs r3, #1
|
|
8005376: 4632 mov r2, r6
|
|
8005378: 4649 mov r1, r9
|
|
800537a: 4640 mov r0, r8
|
|
800537c: 47d0 blx sl
|
|
800537e: 3001 adds r0, #1
|
|
8005380: d09d beq.n 80052be <_printf_i+0x15a>
|
|
8005382: 3501 adds r5, #1
|
|
8005384: 68e3 ldr r3, [r4, #12]
|
|
8005386: 9903 ldr r1, [sp, #12]
|
|
8005388: 1a5b subs r3, r3, r1
|
|
800538a: 42ab cmp r3, r5
|
|
800538c: dcf2 bgt.n 8005374 <_printf_i+0x210>
|
|
800538e: e7eb b.n 8005368 <_printf_i+0x204>
|
|
8005390: 2500 movs r5, #0
|
|
8005392: f104 0619 add.w r6, r4, #25
|
|
8005396: e7f5 b.n 8005384 <_printf_i+0x220>
|
|
8005398: 08007566 .word 0x08007566
|
|
800539c: 08007577 .word 0x08007577
|
|
|
|
080053a0 <std>:
|
|
80053a0: 2300 movs r3, #0
|
|
80053a2: b510 push {r4, lr}
|
|
80053a4: 4604 mov r4, r0
|
|
80053a6: e9c0 3300 strd r3, r3, [r0]
|
|
80053aa: e9c0 3304 strd r3, r3, [r0, #16]
|
|
80053ae: 6083 str r3, [r0, #8]
|
|
80053b0: 8181 strh r1, [r0, #12]
|
|
80053b2: 6643 str r3, [r0, #100] @ 0x64
|
|
80053b4: 81c2 strh r2, [r0, #14]
|
|
80053b6: 6183 str r3, [r0, #24]
|
|
80053b8: 4619 mov r1, r3
|
|
80053ba: 2208 movs r2, #8
|
|
80053bc: 305c adds r0, #92 @ 0x5c
|
|
80053be: f000 f9f9 bl 80057b4 <memset>
|
|
80053c2: 4b0d ldr r3, [pc, #52] @ (80053f8 <std+0x58>)
|
|
80053c4: 6263 str r3, [r4, #36] @ 0x24
|
|
80053c6: 4b0d ldr r3, [pc, #52] @ (80053fc <std+0x5c>)
|
|
80053c8: 62a3 str r3, [r4, #40] @ 0x28
|
|
80053ca: 4b0d ldr r3, [pc, #52] @ (8005400 <std+0x60>)
|
|
80053cc: 62e3 str r3, [r4, #44] @ 0x2c
|
|
80053ce: 4b0d ldr r3, [pc, #52] @ (8005404 <std+0x64>)
|
|
80053d0: 6323 str r3, [r4, #48] @ 0x30
|
|
80053d2: 4b0d ldr r3, [pc, #52] @ (8005408 <std+0x68>)
|
|
80053d4: 6224 str r4, [r4, #32]
|
|
80053d6: 429c cmp r4, r3
|
|
80053d8: d006 beq.n 80053e8 <std+0x48>
|
|
80053da: f103 0268 add.w r2, r3, #104 @ 0x68
|
|
80053de: 4294 cmp r4, r2
|
|
80053e0: d002 beq.n 80053e8 <std+0x48>
|
|
80053e2: 33d0 adds r3, #208 @ 0xd0
|
|
80053e4: 429c cmp r4, r3
|
|
80053e6: d105 bne.n 80053f4 <std+0x54>
|
|
80053e8: f104 0058 add.w r0, r4, #88 @ 0x58
|
|
80053ec: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
80053f0: f000 ba5c b.w 80058ac <__retarget_lock_init_recursive>
|
|
80053f4: bd10 pop {r4, pc}
|
|
80053f6: bf00 nop
|
|
80053f8: 08005605 .word 0x08005605
|
|
80053fc: 08005627 .word 0x08005627
|
|
8005400: 0800565f .word 0x0800565f
|
|
8005404: 08005683 .word 0x08005683
|
|
8005408: 200002d4 .word 0x200002d4
|
|
|
|
0800540c <stdio_exit_handler>:
|
|
800540c: 4a02 ldr r2, [pc, #8] @ (8005418 <stdio_exit_handler+0xc>)
|
|
800540e: 4903 ldr r1, [pc, #12] @ (800541c <stdio_exit_handler+0x10>)
|
|
8005410: 4803 ldr r0, [pc, #12] @ (8005420 <stdio_exit_handler+0x14>)
|
|
8005412: f000 b869 b.w 80054e8 <_fwalk_sglue>
|
|
8005416: bf00 nop
|
|
8005418: 2000000c .word 0x2000000c
|
|
800541c: 080071e9 .word 0x080071e9
|
|
8005420: 2000001c .word 0x2000001c
|
|
|
|
08005424 <cleanup_stdio>:
|
|
8005424: 6841 ldr r1, [r0, #4]
|
|
8005426: 4b0c ldr r3, [pc, #48] @ (8005458 <cleanup_stdio+0x34>)
|
|
8005428: 4299 cmp r1, r3
|
|
800542a: b510 push {r4, lr}
|
|
800542c: 4604 mov r4, r0
|
|
800542e: d001 beq.n 8005434 <cleanup_stdio+0x10>
|
|
8005430: f001 feda bl 80071e8 <_fflush_r>
|
|
8005434: 68a1 ldr r1, [r4, #8]
|
|
8005436: 4b09 ldr r3, [pc, #36] @ (800545c <cleanup_stdio+0x38>)
|
|
8005438: 4299 cmp r1, r3
|
|
800543a: d002 beq.n 8005442 <cleanup_stdio+0x1e>
|
|
800543c: 4620 mov r0, r4
|
|
800543e: f001 fed3 bl 80071e8 <_fflush_r>
|
|
8005442: 68e1 ldr r1, [r4, #12]
|
|
8005444: 4b06 ldr r3, [pc, #24] @ (8005460 <cleanup_stdio+0x3c>)
|
|
8005446: 4299 cmp r1, r3
|
|
8005448: d004 beq.n 8005454 <cleanup_stdio+0x30>
|
|
800544a: 4620 mov r0, r4
|
|
800544c: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8005450: f001 beca b.w 80071e8 <_fflush_r>
|
|
8005454: bd10 pop {r4, pc}
|
|
8005456: bf00 nop
|
|
8005458: 200002d4 .word 0x200002d4
|
|
800545c: 2000033c .word 0x2000033c
|
|
8005460: 200003a4 .word 0x200003a4
|
|
|
|
08005464 <global_stdio_init.part.0>:
|
|
8005464: b510 push {r4, lr}
|
|
8005466: 4b0b ldr r3, [pc, #44] @ (8005494 <global_stdio_init.part.0+0x30>)
|
|
8005468: 4c0b ldr r4, [pc, #44] @ (8005498 <global_stdio_init.part.0+0x34>)
|
|
800546a: 4a0c ldr r2, [pc, #48] @ (800549c <global_stdio_init.part.0+0x38>)
|
|
800546c: 601a str r2, [r3, #0]
|
|
800546e: 4620 mov r0, r4
|
|
8005470: 2200 movs r2, #0
|
|
8005472: 2104 movs r1, #4
|
|
8005474: f7ff ff94 bl 80053a0 <std>
|
|
8005478: f104 0068 add.w r0, r4, #104 @ 0x68
|
|
800547c: 2201 movs r2, #1
|
|
800547e: 2109 movs r1, #9
|
|
8005480: f7ff ff8e bl 80053a0 <std>
|
|
8005484: f104 00d0 add.w r0, r4, #208 @ 0xd0
|
|
8005488: 2202 movs r2, #2
|
|
800548a: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
800548e: 2112 movs r1, #18
|
|
8005490: f7ff bf86 b.w 80053a0 <std>
|
|
8005494: 2000040c .word 0x2000040c
|
|
8005498: 200002d4 .word 0x200002d4
|
|
800549c: 0800540d .word 0x0800540d
|
|
|
|
080054a0 <__sfp_lock_acquire>:
|
|
80054a0: 4801 ldr r0, [pc, #4] @ (80054a8 <__sfp_lock_acquire+0x8>)
|
|
80054a2: f000 ba04 b.w 80058ae <__retarget_lock_acquire_recursive>
|
|
80054a6: bf00 nop
|
|
80054a8: 20000415 .word 0x20000415
|
|
|
|
080054ac <__sfp_lock_release>:
|
|
80054ac: 4801 ldr r0, [pc, #4] @ (80054b4 <__sfp_lock_release+0x8>)
|
|
80054ae: f000 b9ff b.w 80058b0 <__retarget_lock_release_recursive>
|
|
80054b2: bf00 nop
|
|
80054b4: 20000415 .word 0x20000415
|
|
|
|
080054b8 <__sinit>:
|
|
80054b8: b510 push {r4, lr}
|
|
80054ba: 4604 mov r4, r0
|
|
80054bc: f7ff fff0 bl 80054a0 <__sfp_lock_acquire>
|
|
80054c0: 6a23 ldr r3, [r4, #32]
|
|
80054c2: b11b cbz r3, 80054cc <__sinit+0x14>
|
|
80054c4: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
80054c8: f7ff bff0 b.w 80054ac <__sfp_lock_release>
|
|
80054cc: 4b04 ldr r3, [pc, #16] @ (80054e0 <__sinit+0x28>)
|
|
80054ce: 6223 str r3, [r4, #32]
|
|
80054d0: 4b04 ldr r3, [pc, #16] @ (80054e4 <__sinit+0x2c>)
|
|
80054d2: 681b ldr r3, [r3, #0]
|
|
80054d4: 2b00 cmp r3, #0
|
|
80054d6: d1f5 bne.n 80054c4 <__sinit+0xc>
|
|
80054d8: f7ff ffc4 bl 8005464 <global_stdio_init.part.0>
|
|
80054dc: e7f2 b.n 80054c4 <__sinit+0xc>
|
|
80054de: bf00 nop
|
|
80054e0: 08005425 .word 0x08005425
|
|
80054e4: 2000040c .word 0x2000040c
|
|
|
|
080054e8 <_fwalk_sglue>:
|
|
80054e8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
80054ec: 4607 mov r7, r0
|
|
80054ee: 4688 mov r8, r1
|
|
80054f0: 4614 mov r4, r2
|
|
80054f2: 2600 movs r6, #0
|
|
80054f4: e9d4 9501 ldrd r9, r5, [r4, #4]
|
|
80054f8: f1b9 0901 subs.w r9, r9, #1
|
|
80054fc: d505 bpl.n 800550a <_fwalk_sglue+0x22>
|
|
80054fe: 6824 ldr r4, [r4, #0]
|
|
8005500: 2c00 cmp r4, #0
|
|
8005502: d1f7 bne.n 80054f4 <_fwalk_sglue+0xc>
|
|
8005504: 4630 mov r0, r6
|
|
8005506: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
800550a: 89ab ldrh r3, [r5, #12]
|
|
800550c: 2b01 cmp r3, #1
|
|
800550e: d907 bls.n 8005520 <_fwalk_sglue+0x38>
|
|
8005510: f9b5 300e ldrsh.w r3, [r5, #14]
|
|
8005514: 3301 adds r3, #1
|
|
8005516: d003 beq.n 8005520 <_fwalk_sglue+0x38>
|
|
8005518: 4629 mov r1, r5
|
|
800551a: 4638 mov r0, r7
|
|
800551c: 47c0 blx r8
|
|
800551e: 4306 orrs r6, r0
|
|
8005520: 3568 adds r5, #104 @ 0x68
|
|
8005522: e7e9 b.n 80054f8 <_fwalk_sglue+0x10>
|
|
|
|
08005524 <iprintf>:
|
|
8005524: b40f push {r0, r1, r2, r3}
|
|
8005526: b507 push {r0, r1, r2, lr}
|
|
8005528: 4906 ldr r1, [pc, #24] @ (8005544 <iprintf+0x20>)
|
|
800552a: ab04 add r3, sp, #16
|
|
800552c: 6808 ldr r0, [r1, #0]
|
|
800552e: f853 2b04 ldr.w r2, [r3], #4
|
|
8005532: 6881 ldr r1, [r0, #8]
|
|
8005534: 9301 str r3, [sp, #4]
|
|
8005536: f001 fcbb bl 8006eb0 <_vfiprintf_r>
|
|
800553a: b003 add sp, #12
|
|
800553c: f85d eb04 ldr.w lr, [sp], #4
|
|
8005540: b004 add sp, #16
|
|
8005542: 4770 bx lr
|
|
8005544: 20000018 .word 0x20000018
|
|
|
|
08005548 <_puts_r>:
|
|
8005548: 6a03 ldr r3, [r0, #32]
|
|
800554a: b570 push {r4, r5, r6, lr}
|
|
800554c: 6884 ldr r4, [r0, #8]
|
|
800554e: 4605 mov r5, r0
|
|
8005550: 460e mov r6, r1
|
|
8005552: b90b cbnz r3, 8005558 <_puts_r+0x10>
|
|
8005554: f7ff ffb0 bl 80054b8 <__sinit>
|
|
8005558: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
800555a: 07db lsls r3, r3, #31
|
|
800555c: d405 bmi.n 800556a <_puts_r+0x22>
|
|
800555e: 89a3 ldrh r3, [r4, #12]
|
|
8005560: 0598 lsls r0, r3, #22
|
|
8005562: d402 bmi.n 800556a <_puts_r+0x22>
|
|
8005564: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8005566: f000 f9a2 bl 80058ae <__retarget_lock_acquire_recursive>
|
|
800556a: 89a3 ldrh r3, [r4, #12]
|
|
800556c: 0719 lsls r1, r3, #28
|
|
800556e: d502 bpl.n 8005576 <_puts_r+0x2e>
|
|
8005570: 6923 ldr r3, [r4, #16]
|
|
8005572: 2b00 cmp r3, #0
|
|
8005574: d135 bne.n 80055e2 <_puts_r+0x9a>
|
|
8005576: 4621 mov r1, r4
|
|
8005578: 4628 mov r0, r5
|
|
800557a: f000 f8c5 bl 8005708 <__swsetup_r>
|
|
800557e: b380 cbz r0, 80055e2 <_puts_r+0x9a>
|
|
8005580: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff
|
|
8005584: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
8005586: 07da lsls r2, r3, #31
|
|
8005588: d405 bmi.n 8005596 <_puts_r+0x4e>
|
|
800558a: 89a3 ldrh r3, [r4, #12]
|
|
800558c: 059b lsls r3, r3, #22
|
|
800558e: d402 bmi.n 8005596 <_puts_r+0x4e>
|
|
8005590: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8005592: f000 f98d bl 80058b0 <__retarget_lock_release_recursive>
|
|
8005596: 4628 mov r0, r5
|
|
8005598: bd70 pop {r4, r5, r6, pc}
|
|
800559a: 2b00 cmp r3, #0
|
|
800559c: da04 bge.n 80055a8 <_puts_r+0x60>
|
|
800559e: 69a2 ldr r2, [r4, #24]
|
|
80055a0: 429a cmp r2, r3
|
|
80055a2: dc17 bgt.n 80055d4 <_puts_r+0x8c>
|
|
80055a4: 290a cmp r1, #10
|
|
80055a6: d015 beq.n 80055d4 <_puts_r+0x8c>
|
|
80055a8: 6823 ldr r3, [r4, #0]
|
|
80055aa: 1c5a adds r2, r3, #1
|
|
80055ac: 6022 str r2, [r4, #0]
|
|
80055ae: 7019 strb r1, [r3, #0]
|
|
80055b0: 68a3 ldr r3, [r4, #8]
|
|
80055b2: f816 1f01 ldrb.w r1, [r6, #1]!
|
|
80055b6: 3b01 subs r3, #1
|
|
80055b8: 60a3 str r3, [r4, #8]
|
|
80055ba: 2900 cmp r1, #0
|
|
80055bc: d1ed bne.n 800559a <_puts_r+0x52>
|
|
80055be: 2b00 cmp r3, #0
|
|
80055c0: da11 bge.n 80055e6 <_puts_r+0x9e>
|
|
80055c2: 4622 mov r2, r4
|
|
80055c4: 210a movs r1, #10
|
|
80055c6: 4628 mov r0, r5
|
|
80055c8: f000 f85f bl 800568a <__swbuf_r>
|
|
80055cc: 3001 adds r0, #1
|
|
80055ce: d0d7 beq.n 8005580 <_puts_r+0x38>
|
|
80055d0: 250a movs r5, #10
|
|
80055d2: e7d7 b.n 8005584 <_puts_r+0x3c>
|
|
80055d4: 4622 mov r2, r4
|
|
80055d6: 4628 mov r0, r5
|
|
80055d8: f000 f857 bl 800568a <__swbuf_r>
|
|
80055dc: 3001 adds r0, #1
|
|
80055de: d1e7 bne.n 80055b0 <_puts_r+0x68>
|
|
80055e0: e7ce b.n 8005580 <_puts_r+0x38>
|
|
80055e2: 3e01 subs r6, #1
|
|
80055e4: e7e4 b.n 80055b0 <_puts_r+0x68>
|
|
80055e6: 6823 ldr r3, [r4, #0]
|
|
80055e8: 1c5a adds r2, r3, #1
|
|
80055ea: 6022 str r2, [r4, #0]
|
|
80055ec: 220a movs r2, #10
|
|
80055ee: 701a strb r2, [r3, #0]
|
|
80055f0: e7ee b.n 80055d0 <_puts_r+0x88>
|
|
...
|
|
|
|
080055f4 <puts>:
|
|
80055f4: 4b02 ldr r3, [pc, #8] @ (8005600 <puts+0xc>)
|
|
80055f6: 4601 mov r1, r0
|
|
80055f8: 6818 ldr r0, [r3, #0]
|
|
80055fa: f7ff bfa5 b.w 8005548 <_puts_r>
|
|
80055fe: bf00 nop
|
|
8005600: 20000018 .word 0x20000018
|
|
|
|
08005604 <__sread>:
|
|
8005604: b510 push {r4, lr}
|
|
8005606: 460c mov r4, r1
|
|
8005608: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800560c: f000 f900 bl 8005810 <_read_r>
|
|
8005610: 2800 cmp r0, #0
|
|
8005612: bfab itete ge
|
|
8005614: 6d63 ldrge r3, [r4, #84] @ 0x54
|
|
8005616: 89a3 ldrhlt r3, [r4, #12]
|
|
8005618: 181b addge r3, r3, r0
|
|
800561a: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
|
|
800561e: bfac ite ge
|
|
8005620: 6563 strge r3, [r4, #84] @ 0x54
|
|
8005622: 81a3 strhlt r3, [r4, #12]
|
|
8005624: bd10 pop {r4, pc}
|
|
|
|
08005626 <__swrite>:
|
|
8005626: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
800562a: 461f mov r7, r3
|
|
800562c: 898b ldrh r3, [r1, #12]
|
|
800562e: 05db lsls r3, r3, #23
|
|
8005630: 4605 mov r5, r0
|
|
8005632: 460c mov r4, r1
|
|
8005634: 4616 mov r6, r2
|
|
8005636: d505 bpl.n 8005644 <__swrite+0x1e>
|
|
8005638: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800563c: 2302 movs r3, #2
|
|
800563e: 2200 movs r2, #0
|
|
8005640: f000 f8d4 bl 80057ec <_lseek_r>
|
|
8005644: 89a3 ldrh r3, [r4, #12]
|
|
8005646: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
800564a: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
800564e: 81a3 strh r3, [r4, #12]
|
|
8005650: 4632 mov r2, r6
|
|
8005652: 463b mov r3, r7
|
|
8005654: 4628 mov r0, r5
|
|
8005656: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
800565a: f000 b8eb b.w 8005834 <_write_r>
|
|
|
|
0800565e <__sseek>:
|
|
800565e: b510 push {r4, lr}
|
|
8005660: 460c mov r4, r1
|
|
8005662: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
8005666: f000 f8c1 bl 80057ec <_lseek_r>
|
|
800566a: 1c43 adds r3, r0, #1
|
|
800566c: 89a3 ldrh r3, [r4, #12]
|
|
800566e: bf15 itete ne
|
|
8005670: 6560 strne r0, [r4, #84] @ 0x54
|
|
8005672: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
|
|
8005676: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
|
|
800567a: 81a3 strheq r3, [r4, #12]
|
|
800567c: bf18 it ne
|
|
800567e: 81a3 strhne r3, [r4, #12]
|
|
8005680: bd10 pop {r4, pc}
|
|
|
|
08005682 <__sclose>:
|
|
8005682: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
8005686: f000 b8a1 b.w 80057cc <_close_r>
|
|
|
|
0800568a <__swbuf_r>:
|
|
800568a: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800568c: 460e mov r6, r1
|
|
800568e: 4614 mov r4, r2
|
|
8005690: 4605 mov r5, r0
|
|
8005692: b118 cbz r0, 800569c <__swbuf_r+0x12>
|
|
8005694: 6a03 ldr r3, [r0, #32]
|
|
8005696: b90b cbnz r3, 800569c <__swbuf_r+0x12>
|
|
8005698: f7ff ff0e bl 80054b8 <__sinit>
|
|
800569c: 69a3 ldr r3, [r4, #24]
|
|
800569e: 60a3 str r3, [r4, #8]
|
|
80056a0: 89a3 ldrh r3, [r4, #12]
|
|
80056a2: 071a lsls r2, r3, #28
|
|
80056a4: d501 bpl.n 80056aa <__swbuf_r+0x20>
|
|
80056a6: 6923 ldr r3, [r4, #16]
|
|
80056a8: b943 cbnz r3, 80056bc <__swbuf_r+0x32>
|
|
80056aa: 4621 mov r1, r4
|
|
80056ac: 4628 mov r0, r5
|
|
80056ae: f000 f82b bl 8005708 <__swsetup_r>
|
|
80056b2: b118 cbz r0, 80056bc <__swbuf_r+0x32>
|
|
80056b4: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
|
|
80056b8: 4638 mov r0, r7
|
|
80056ba: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
80056bc: 6823 ldr r3, [r4, #0]
|
|
80056be: 6922 ldr r2, [r4, #16]
|
|
80056c0: 1a98 subs r0, r3, r2
|
|
80056c2: 6963 ldr r3, [r4, #20]
|
|
80056c4: b2f6 uxtb r6, r6
|
|
80056c6: 4283 cmp r3, r0
|
|
80056c8: 4637 mov r7, r6
|
|
80056ca: dc05 bgt.n 80056d8 <__swbuf_r+0x4e>
|
|
80056cc: 4621 mov r1, r4
|
|
80056ce: 4628 mov r0, r5
|
|
80056d0: f001 fd8a bl 80071e8 <_fflush_r>
|
|
80056d4: 2800 cmp r0, #0
|
|
80056d6: d1ed bne.n 80056b4 <__swbuf_r+0x2a>
|
|
80056d8: 68a3 ldr r3, [r4, #8]
|
|
80056da: 3b01 subs r3, #1
|
|
80056dc: 60a3 str r3, [r4, #8]
|
|
80056de: 6823 ldr r3, [r4, #0]
|
|
80056e0: 1c5a adds r2, r3, #1
|
|
80056e2: 6022 str r2, [r4, #0]
|
|
80056e4: 701e strb r6, [r3, #0]
|
|
80056e6: 6962 ldr r2, [r4, #20]
|
|
80056e8: 1c43 adds r3, r0, #1
|
|
80056ea: 429a cmp r2, r3
|
|
80056ec: d004 beq.n 80056f8 <__swbuf_r+0x6e>
|
|
80056ee: 89a3 ldrh r3, [r4, #12]
|
|
80056f0: 07db lsls r3, r3, #31
|
|
80056f2: d5e1 bpl.n 80056b8 <__swbuf_r+0x2e>
|
|
80056f4: 2e0a cmp r6, #10
|
|
80056f6: d1df bne.n 80056b8 <__swbuf_r+0x2e>
|
|
80056f8: 4621 mov r1, r4
|
|
80056fa: 4628 mov r0, r5
|
|
80056fc: f001 fd74 bl 80071e8 <_fflush_r>
|
|
8005700: 2800 cmp r0, #0
|
|
8005702: d0d9 beq.n 80056b8 <__swbuf_r+0x2e>
|
|
8005704: e7d6 b.n 80056b4 <__swbuf_r+0x2a>
|
|
...
|
|
|
|
08005708 <__swsetup_r>:
|
|
8005708: b538 push {r3, r4, r5, lr}
|
|
800570a: 4b29 ldr r3, [pc, #164] @ (80057b0 <__swsetup_r+0xa8>)
|
|
800570c: 4605 mov r5, r0
|
|
800570e: 6818 ldr r0, [r3, #0]
|
|
8005710: 460c mov r4, r1
|
|
8005712: b118 cbz r0, 800571c <__swsetup_r+0x14>
|
|
8005714: 6a03 ldr r3, [r0, #32]
|
|
8005716: b90b cbnz r3, 800571c <__swsetup_r+0x14>
|
|
8005718: f7ff fece bl 80054b8 <__sinit>
|
|
800571c: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8005720: 0719 lsls r1, r3, #28
|
|
8005722: d422 bmi.n 800576a <__swsetup_r+0x62>
|
|
8005724: 06da lsls r2, r3, #27
|
|
8005726: d407 bmi.n 8005738 <__swsetup_r+0x30>
|
|
8005728: 2209 movs r2, #9
|
|
800572a: 602a str r2, [r5, #0]
|
|
800572c: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8005730: 81a3 strh r3, [r4, #12]
|
|
8005732: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8005736: e033 b.n 80057a0 <__swsetup_r+0x98>
|
|
8005738: 0758 lsls r0, r3, #29
|
|
800573a: d512 bpl.n 8005762 <__swsetup_r+0x5a>
|
|
800573c: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
800573e: b141 cbz r1, 8005752 <__swsetup_r+0x4a>
|
|
8005740: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
8005744: 4299 cmp r1, r3
|
|
8005746: d002 beq.n 800574e <__swsetup_r+0x46>
|
|
8005748: 4628 mov r0, r5
|
|
800574a: f000 ff0d bl 8006568 <_free_r>
|
|
800574e: 2300 movs r3, #0
|
|
8005750: 6363 str r3, [r4, #52] @ 0x34
|
|
8005752: 89a3 ldrh r3, [r4, #12]
|
|
8005754: f023 0324 bic.w r3, r3, #36 @ 0x24
|
|
8005758: 81a3 strh r3, [r4, #12]
|
|
800575a: 2300 movs r3, #0
|
|
800575c: 6063 str r3, [r4, #4]
|
|
800575e: 6923 ldr r3, [r4, #16]
|
|
8005760: 6023 str r3, [r4, #0]
|
|
8005762: 89a3 ldrh r3, [r4, #12]
|
|
8005764: f043 0308 orr.w r3, r3, #8
|
|
8005768: 81a3 strh r3, [r4, #12]
|
|
800576a: 6923 ldr r3, [r4, #16]
|
|
800576c: b94b cbnz r3, 8005782 <__swsetup_r+0x7a>
|
|
800576e: 89a3 ldrh r3, [r4, #12]
|
|
8005770: f403 7320 and.w r3, r3, #640 @ 0x280
|
|
8005774: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8005778: d003 beq.n 8005782 <__swsetup_r+0x7a>
|
|
800577a: 4621 mov r1, r4
|
|
800577c: 4628 mov r0, r5
|
|
800577e: f001 fd81 bl 8007284 <__smakebuf_r>
|
|
8005782: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8005786: f013 0201 ands.w r2, r3, #1
|
|
800578a: d00a beq.n 80057a2 <__swsetup_r+0x9a>
|
|
800578c: 2200 movs r2, #0
|
|
800578e: 60a2 str r2, [r4, #8]
|
|
8005790: 6962 ldr r2, [r4, #20]
|
|
8005792: 4252 negs r2, r2
|
|
8005794: 61a2 str r2, [r4, #24]
|
|
8005796: 6922 ldr r2, [r4, #16]
|
|
8005798: b942 cbnz r2, 80057ac <__swsetup_r+0xa4>
|
|
800579a: f013 0080 ands.w r0, r3, #128 @ 0x80
|
|
800579e: d1c5 bne.n 800572c <__swsetup_r+0x24>
|
|
80057a0: bd38 pop {r3, r4, r5, pc}
|
|
80057a2: 0799 lsls r1, r3, #30
|
|
80057a4: bf58 it pl
|
|
80057a6: 6962 ldrpl r2, [r4, #20]
|
|
80057a8: 60a2 str r2, [r4, #8]
|
|
80057aa: e7f4 b.n 8005796 <__swsetup_r+0x8e>
|
|
80057ac: 2000 movs r0, #0
|
|
80057ae: e7f7 b.n 80057a0 <__swsetup_r+0x98>
|
|
80057b0: 20000018 .word 0x20000018
|
|
|
|
080057b4 <memset>:
|
|
80057b4: 4402 add r2, r0
|
|
80057b6: 4603 mov r3, r0
|
|
80057b8: 4293 cmp r3, r2
|
|
80057ba: d100 bne.n 80057be <memset+0xa>
|
|
80057bc: 4770 bx lr
|
|
80057be: f803 1b01 strb.w r1, [r3], #1
|
|
80057c2: e7f9 b.n 80057b8 <memset+0x4>
|
|
|
|
080057c4 <_localeconv_r>:
|
|
80057c4: 4800 ldr r0, [pc, #0] @ (80057c8 <_localeconv_r+0x4>)
|
|
80057c6: 4770 bx lr
|
|
80057c8: 20000158 .word 0x20000158
|
|
|
|
080057cc <_close_r>:
|
|
80057cc: b538 push {r3, r4, r5, lr}
|
|
80057ce: 4d06 ldr r5, [pc, #24] @ (80057e8 <_close_r+0x1c>)
|
|
80057d0: 2300 movs r3, #0
|
|
80057d2: 4604 mov r4, r0
|
|
80057d4: 4608 mov r0, r1
|
|
80057d6: 602b str r3, [r5, #0]
|
|
80057d8: f7fb fedb bl 8001592 <_close>
|
|
80057dc: 1c43 adds r3, r0, #1
|
|
80057de: d102 bne.n 80057e6 <_close_r+0x1a>
|
|
80057e0: 682b ldr r3, [r5, #0]
|
|
80057e2: b103 cbz r3, 80057e6 <_close_r+0x1a>
|
|
80057e4: 6023 str r3, [r4, #0]
|
|
80057e6: bd38 pop {r3, r4, r5, pc}
|
|
80057e8: 20000410 .word 0x20000410
|
|
|
|
080057ec <_lseek_r>:
|
|
80057ec: b538 push {r3, r4, r5, lr}
|
|
80057ee: 4d07 ldr r5, [pc, #28] @ (800580c <_lseek_r+0x20>)
|
|
80057f0: 4604 mov r4, r0
|
|
80057f2: 4608 mov r0, r1
|
|
80057f4: 4611 mov r1, r2
|
|
80057f6: 2200 movs r2, #0
|
|
80057f8: 602a str r2, [r5, #0]
|
|
80057fa: 461a mov r2, r3
|
|
80057fc: f7fb fef0 bl 80015e0 <_lseek>
|
|
8005800: 1c43 adds r3, r0, #1
|
|
8005802: d102 bne.n 800580a <_lseek_r+0x1e>
|
|
8005804: 682b ldr r3, [r5, #0]
|
|
8005806: b103 cbz r3, 800580a <_lseek_r+0x1e>
|
|
8005808: 6023 str r3, [r4, #0]
|
|
800580a: bd38 pop {r3, r4, r5, pc}
|
|
800580c: 20000410 .word 0x20000410
|
|
|
|
08005810 <_read_r>:
|
|
8005810: b538 push {r3, r4, r5, lr}
|
|
8005812: 4d07 ldr r5, [pc, #28] @ (8005830 <_read_r+0x20>)
|
|
8005814: 4604 mov r4, r0
|
|
8005816: 4608 mov r0, r1
|
|
8005818: 4611 mov r1, r2
|
|
800581a: 2200 movs r2, #0
|
|
800581c: 602a str r2, [r5, #0]
|
|
800581e: 461a mov r2, r3
|
|
8005820: f7fb fe7e bl 8001520 <_read>
|
|
8005824: 1c43 adds r3, r0, #1
|
|
8005826: d102 bne.n 800582e <_read_r+0x1e>
|
|
8005828: 682b ldr r3, [r5, #0]
|
|
800582a: b103 cbz r3, 800582e <_read_r+0x1e>
|
|
800582c: 6023 str r3, [r4, #0]
|
|
800582e: bd38 pop {r3, r4, r5, pc}
|
|
8005830: 20000410 .word 0x20000410
|
|
|
|
08005834 <_write_r>:
|
|
8005834: b538 push {r3, r4, r5, lr}
|
|
8005836: 4d07 ldr r5, [pc, #28] @ (8005854 <_write_r+0x20>)
|
|
8005838: 4604 mov r4, r0
|
|
800583a: 4608 mov r0, r1
|
|
800583c: 4611 mov r1, r2
|
|
800583e: 2200 movs r2, #0
|
|
8005840: 602a str r2, [r5, #0]
|
|
8005842: 461a mov r2, r3
|
|
8005844: f7fb fe89 bl 800155a <_write>
|
|
8005848: 1c43 adds r3, r0, #1
|
|
800584a: d102 bne.n 8005852 <_write_r+0x1e>
|
|
800584c: 682b ldr r3, [r5, #0]
|
|
800584e: b103 cbz r3, 8005852 <_write_r+0x1e>
|
|
8005850: 6023 str r3, [r4, #0]
|
|
8005852: bd38 pop {r3, r4, r5, pc}
|
|
8005854: 20000410 .word 0x20000410
|
|
|
|
08005858 <__errno>:
|
|
8005858: 4b01 ldr r3, [pc, #4] @ (8005860 <__errno+0x8>)
|
|
800585a: 6818 ldr r0, [r3, #0]
|
|
800585c: 4770 bx lr
|
|
800585e: bf00 nop
|
|
8005860: 20000018 .word 0x20000018
|
|
|
|
08005864 <__libc_init_array>:
|
|
8005864: b570 push {r4, r5, r6, lr}
|
|
8005866: 4d0d ldr r5, [pc, #52] @ (800589c <__libc_init_array+0x38>)
|
|
8005868: 4c0d ldr r4, [pc, #52] @ (80058a0 <__libc_init_array+0x3c>)
|
|
800586a: 1b64 subs r4, r4, r5
|
|
800586c: 10a4 asrs r4, r4, #2
|
|
800586e: 2600 movs r6, #0
|
|
8005870: 42a6 cmp r6, r4
|
|
8005872: d109 bne.n 8005888 <__libc_init_array+0x24>
|
|
8005874: 4d0b ldr r5, [pc, #44] @ (80058a4 <__libc_init_array+0x40>)
|
|
8005876: 4c0c ldr r4, [pc, #48] @ (80058a8 <__libc_init_array+0x44>)
|
|
8005878: f001 fe30 bl 80074dc <_init>
|
|
800587c: 1b64 subs r4, r4, r5
|
|
800587e: 10a4 asrs r4, r4, #2
|
|
8005880: 2600 movs r6, #0
|
|
8005882: 42a6 cmp r6, r4
|
|
8005884: d105 bne.n 8005892 <__libc_init_array+0x2e>
|
|
8005886: bd70 pop {r4, r5, r6, pc}
|
|
8005888: f855 3b04 ldr.w r3, [r5], #4
|
|
800588c: 4798 blx r3
|
|
800588e: 3601 adds r6, #1
|
|
8005890: e7ee b.n 8005870 <__libc_init_array+0xc>
|
|
8005892: f855 3b04 ldr.w r3, [r5], #4
|
|
8005896: 4798 blx r3
|
|
8005898: 3601 adds r6, #1
|
|
800589a: e7f2 b.n 8005882 <__libc_init_array+0x1e>
|
|
800589c: 080078d4 .word 0x080078d4
|
|
80058a0: 080078d4 .word 0x080078d4
|
|
80058a4: 080078d4 .word 0x080078d4
|
|
80058a8: 080078d8 .word 0x080078d8
|
|
|
|
080058ac <__retarget_lock_init_recursive>:
|
|
80058ac: 4770 bx lr
|
|
|
|
080058ae <__retarget_lock_acquire_recursive>:
|
|
80058ae: 4770 bx lr
|
|
|
|
080058b0 <__retarget_lock_release_recursive>:
|
|
80058b0: 4770 bx lr
|
|
|
|
080058b2 <quorem>:
|
|
80058b2: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80058b6: 6903 ldr r3, [r0, #16]
|
|
80058b8: 690c ldr r4, [r1, #16]
|
|
80058ba: 42a3 cmp r3, r4
|
|
80058bc: 4607 mov r7, r0
|
|
80058be: db7e blt.n 80059be <quorem+0x10c>
|
|
80058c0: 3c01 subs r4, #1
|
|
80058c2: f101 0814 add.w r8, r1, #20
|
|
80058c6: 00a3 lsls r3, r4, #2
|
|
80058c8: f100 0514 add.w r5, r0, #20
|
|
80058cc: 9300 str r3, [sp, #0]
|
|
80058ce: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
80058d2: 9301 str r3, [sp, #4]
|
|
80058d4: f858 3024 ldr.w r3, [r8, r4, lsl #2]
|
|
80058d8: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
80058dc: 3301 adds r3, #1
|
|
80058de: 429a cmp r2, r3
|
|
80058e0: eb08 0984 add.w r9, r8, r4, lsl #2
|
|
80058e4: fbb2 f6f3 udiv r6, r2, r3
|
|
80058e8: d32e bcc.n 8005948 <quorem+0x96>
|
|
80058ea: f04f 0a00 mov.w sl, #0
|
|
80058ee: 46c4 mov ip, r8
|
|
80058f0: 46ae mov lr, r5
|
|
80058f2: 46d3 mov fp, sl
|
|
80058f4: f85c 3b04 ldr.w r3, [ip], #4
|
|
80058f8: b298 uxth r0, r3
|
|
80058fa: fb06 a000 mla r0, r6, r0, sl
|
|
80058fe: 0c02 lsrs r2, r0, #16
|
|
8005900: 0c1b lsrs r3, r3, #16
|
|
8005902: fb06 2303 mla r3, r6, r3, r2
|
|
8005906: f8de 2000 ldr.w r2, [lr]
|
|
800590a: b280 uxth r0, r0
|
|
800590c: b292 uxth r2, r2
|
|
800590e: 1a12 subs r2, r2, r0
|
|
8005910: 445a add r2, fp
|
|
8005912: f8de 0000 ldr.w r0, [lr]
|
|
8005916: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
800591a: b29b uxth r3, r3
|
|
800591c: ebc3 4322 rsb r3, r3, r2, asr #16
|
|
8005920: eb03 4310 add.w r3, r3, r0, lsr #16
|
|
8005924: b292 uxth r2, r2
|
|
8005926: ea42 4203 orr.w r2, r2, r3, lsl #16
|
|
800592a: 45e1 cmp r9, ip
|
|
800592c: f84e 2b04 str.w r2, [lr], #4
|
|
8005930: ea4f 4b23 mov.w fp, r3, asr #16
|
|
8005934: d2de bcs.n 80058f4 <quorem+0x42>
|
|
8005936: 9b00 ldr r3, [sp, #0]
|
|
8005938: 58eb ldr r3, [r5, r3]
|
|
800593a: b92b cbnz r3, 8005948 <quorem+0x96>
|
|
800593c: 9b01 ldr r3, [sp, #4]
|
|
800593e: 3b04 subs r3, #4
|
|
8005940: 429d cmp r5, r3
|
|
8005942: 461a mov r2, r3
|
|
8005944: d32f bcc.n 80059a6 <quorem+0xf4>
|
|
8005946: 613c str r4, [r7, #16]
|
|
8005948: 4638 mov r0, r7
|
|
800594a: f001 f97f bl 8006c4c <__mcmp>
|
|
800594e: 2800 cmp r0, #0
|
|
8005950: db25 blt.n 800599e <quorem+0xec>
|
|
8005952: 4629 mov r1, r5
|
|
8005954: 2000 movs r0, #0
|
|
8005956: f858 2b04 ldr.w r2, [r8], #4
|
|
800595a: f8d1 c000 ldr.w ip, [r1]
|
|
800595e: fa1f fe82 uxth.w lr, r2
|
|
8005962: fa1f f38c uxth.w r3, ip
|
|
8005966: eba3 030e sub.w r3, r3, lr
|
|
800596a: 4403 add r3, r0
|
|
800596c: 0c12 lsrs r2, r2, #16
|
|
800596e: ebc2 4223 rsb r2, r2, r3, asr #16
|
|
8005972: eb02 421c add.w r2, r2, ip, lsr #16
|
|
8005976: b29b uxth r3, r3
|
|
8005978: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
800597c: 45c1 cmp r9, r8
|
|
800597e: f841 3b04 str.w r3, [r1], #4
|
|
8005982: ea4f 4022 mov.w r0, r2, asr #16
|
|
8005986: d2e6 bcs.n 8005956 <quorem+0xa4>
|
|
8005988: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
800598c: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
8005990: b922 cbnz r2, 800599c <quorem+0xea>
|
|
8005992: 3b04 subs r3, #4
|
|
8005994: 429d cmp r5, r3
|
|
8005996: 461a mov r2, r3
|
|
8005998: d30b bcc.n 80059b2 <quorem+0x100>
|
|
800599a: 613c str r4, [r7, #16]
|
|
800599c: 3601 adds r6, #1
|
|
800599e: 4630 mov r0, r6
|
|
80059a0: b003 add sp, #12
|
|
80059a2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80059a6: 6812 ldr r2, [r2, #0]
|
|
80059a8: 3b04 subs r3, #4
|
|
80059aa: 2a00 cmp r2, #0
|
|
80059ac: d1cb bne.n 8005946 <quorem+0x94>
|
|
80059ae: 3c01 subs r4, #1
|
|
80059b0: e7c6 b.n 8005940 <quorem+0x8e>
|
|
80059b2: 6812 ldr r2, [r2, #0]
|
|
80059b4: 3b04 subs r3, #4
|
|
80059b6: 2a00 cmp r2, #0
|
|
80059b8: d1ef bne.n 800599a <quorem+0xe8>
|
|
80059ba: 3c01 subs r4, #1
|
|
80059bc: e7ea b.n 8005994 <quorem+0xe2>
|
|
80059be: 2000 movs r0, #0
|
|
80059c0: e7ee b.n 80059a0 <quorem+0xee>
|
|
80059c2: 0000 movs r0, r0
|
|
80059c4: 0000 movs r0, r0
|
|
...
|
|
|
|
080059c8 <_dtoa_r>:
|
|
80059c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80059cc: 69c7 ldr r7, [r0, #28]
|
|
80059ce: b097 sub sp, #92 @ 0x5c
|
|
80059d0: ed8d 0b04 vstr d0, [sp, #16]
|
|
80059d4: ec55 4b10 vmov r4, r5, d0
|
|
80059d8: 9e20 ldr r6, [sp, #128] @ 0x80
|
|
80059da: 9107 str r1, [sp, #28]
|
|
80059dc: 4681 mov r9, r0
|
|
80059de: 920c str r2, [sp, #48] @ 0x30
|
|
80059e0: 9311 str r3, [sp, #68] @ 0x44
|
|
80059e2: b97f cbnz r7, 8005a04 <_dtoa_r+0x3c>
|
|
80059e4: 2010 movs r0, #16
|
|
80059e6: f000 fe09 bl 80065fc <malloc>
|
|
80059ea: 4602 mov r2, r0
|
|
80059ec: f8c9 001c str.w r0, [r9, #28]
|
|
80059f0: b920 cbnz r0, 80059fc <_dtoa_r+0x34>
|
|
80059f2: 4ba9 ldr r3, [pc, #676] @ (8005c98 <_dtoa_r+0x2d0>)
|
|
80059f4: 21ef movs r1, #239 @ 0xef
|
|
80059f6: 48a9 ldr r0, [pc, #676] @ (8005c9c <_dtoa_r+0x2d4>)
|
|
80059f8: f001 fcc0 bl 800737c <__assert_func>
|
|
80059fc: e9c0 7701 strd r7, r7, [r0, #4]
|
|
8005a00: 6007 str r7, [r0, #0]
|
|
8005a02: 60c7 str r7, [r0, #12]
|
|
8005a04: f8d9 301c ldr.w r3, [r9, #28]
|
|
8005a08: 6819 ldr r1, [r3, #0]
|
|
8005a0a: b159 cbz r1, 8005a24 <_dtoa_r+0x5c>
|
|
8005a0c: 685a ldr r2, [r3, #4]
|
|
8005a0e: 604a str r2, [r1, #4]
|
|
8005a10: 2301 movs r3, #1
|
|
8005a12: 4093 lsls r3, r2
|
|
8005a14: 608b str r3, [r1, #8]
|
|
8005a16: 4648 mov r0, r9
|
|
8005a18: f000 fee6 bl 80067e8 <_Bfree>
|
|
8005a1c: f8d9 301c ldr.w r3, [r9, #28]
|
|
8005a20: 2200 movs r2, #0
|
|
8005a22: 601a str r2, [r3, #0]
|
|
8005a24: 1e2b subs r3, r5, #0
|
|
8005a26: bfb9 ittee lt
|
|
8005a28: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000
|
|
8005a2c: 9305 strlt r3, [sp, #20]
|
|
8005a2e: 2300 movge r3, #0
|
|
8005a30: 6033 strge r3, [r6, #0]
|
|
8005a32: 9f05 ldr r7, [sp, #20]
|
|
8005a34: 4b9a ldr r3, [pc, #616] @ (8005ca0 <_dtoa_r+0x2d8>)
|
|
8005a36: bfbc itt lt
|
|
8005a38: 2201 movlt r2, #1
|
|
8005a3a: 6032 strlt r2, [r6, #0]
|
|
8005a3c: 43bb bics r3, r7
|
|
8005a3e: d112 bne.n 8005a66 <_dtoa_r+0x9e>
|
|
8005a40: 9a11 ldr r2, [sp, #68] @ 0x44
|
|
8005a42: f242 730f movw r3, #9999 @ 0x270f
|
|
8005a46: 6013 str r3, [r2, #0]
|
|
8005a48: f3c7 0313 ubfx r3, r7, #0, #20
|
|
8005a4c: 4323 orrs r3, r4
|
|
8005a4e: f000 855a beq.w 8006506 <_dtoa_r+0xb3e>
|
|
8005a52: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8005a54: f8df a25c ldr.w sl, [pc, #604] @ 8005cb4 <_dtoa_r+0x2ec>
|
|
8005a58: 2b00 cmp r3, #0
|
|
8005a5a: f000 855c beq.w 8006516 <_dtoa_r+0xb4e>
|
|
8005a5e: f10a 0303 add.w r3, sl, #3
|
|
8005a62: f000 bd56 b.w 8006512 <_dtoa_r+0xb4a>
|
|
8005a66: ed9d 7b04 vldr d7, [sp, #16]
|
|
8005a6a: 2200 movs r2, #0
|
|
8005a6c: ec51 0b17 vmov r0, r1, d7
|
|
8005a70: 2300 movs r3, #0
|
|
8005a72: ed8d 7b0a vstr d7, [sp, #40] @ 0x28
|
|
8005a76: f7fb f827 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8005a7a: 4680 mov r8, r0
|
|
8005a7c: b158 cbz r0, 8005a96 <_dtoa_r+0xce>
|
|
8005a7e: 9a11 ldr r2, [sp, #68] @ 0x44
|
|
8005a80: 2301 movs r3, #1
|
|
8005a82: 6013 str r3, [r2, #0]
|
|
8005a84: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8005a86: b113 cbz r3, 8005a8e <_dtoa_r+0xc6>
|
|
8005a88: 9a21 ldr r2, [sp, #132] @ 0x84
|
|
8005a8a: 4b86 ldr r3, [pc, #536] @ (8005ca4 <_dtoa_r+0x2dc>)
|
|
8005a8c: 6013 str r3, [r2, #0]
|
|
8005a8e: f8df a228 ldr.w sl, [pc, #552] @ 8005cb8 <_dtoa_r+0x2f0>
|
|
8005a92: f000 bd40 b.w 8006516 <_dtoa_r+0xb4e>
|
|
8005a96: ed9d 0b0a vldr d0, [sp, #40] @ 0x28
|
|
8005a9a: aa14 add r2, sp, #80 @ 0x50
|
|
8005a9c: a915 add r1, sp, #84 @ 0x54
|
|
8005a9e: 4648 mov r0, r9
|
|
8005aa0: f001 f984 bl 8006dac <__d2b>
|
|
8005aa4: f3c7 560a ubfx r6, r7, #20, #11
|
|
8005aa8: 9002 str r0, [sp, #8]
|
|
8005aaa: 2e00 cmp r6, #0
|
|
8005aac: d078 beq.n 8005ba0 <_dtoa_r+0x1d8>
|
|
8005aae: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8005ab0: f8cd 8048 str.w r8, [sp, #72] @ 0x48
|
|
8005ab4: f3c3 0313 ubfx r3, r3, #0, #20
|
|
8005ab8: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
8005abc: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000
|
|
8005ac0: f443 1340 orr.w r3, r3, #3145728 @ 0x300000
|
|
8005ac4: f2a6 36ff subw r6, r6, #1023 @ 0x3ff
|
|
8005ac8: 4619 mov r1, r3
|
|
8005aca: 2200 movs r2, #0
|
|
8005acc: 4b76 ldr r3, [pc, #472] @ (8005ca8 <_dtoa_r+0x2e0>)
|
|
8005ace: f7fa fbdb bl 8000288 <__aeabi_dsub>
|
|
8005ad2: a36b add r3, pc, #428 @ (adr r3, 8005c80 <_dtoa_r+0x2b8>)
|
|
8005ad4: e9d3 2300 ldrd r2, r3, [r3]
|
|
8005ad8: f7fa fd8e bl 80005f8 <__aeabi_dmul>
|
|
8005adc: a36a add r3, pc, #424 @ (adr r3, 8005c88 <_dtoa_r+0x2c0>)
|
|
8005ade: e9d3 2300 ldrd r2, r3, [r3]
|
|
8005ae2: f7fa fbd3 bl 800028c <__adddf3>
|
|
8005ae6: 4604 mov r4, r0
|
|
8005ae8: 4630 mov r0, r6
|
|
8005aea: 460d mov r5, r1
|
|
8005aec: f7fa fd1a bl 8000524 <__aeabi_i2d>
|
|
8005af0: a367 add r3, pc, #412 @ (adr r3, 8005c90 <_dtoa_r+0x2c8>)
|
|
8005af2: e9d3 2300 ldrd r2, r3, [r3]
|
|
8005af6: f7fa fd7f bl 80005f8 <__aeabi_dmul>
|
|
8005afa: 4602 mov r2, r0
|
|
8005afc: 460b mov r3, r1
|
|
8005afe: 4620 mov r0, r4
|
|
8005b00: 4629 mov r1, r5
|
|
8005b02: f7fa fbc3 bl 800028c <__adddf3>
|
|
8005b06: 4604 mov r4, r0
|
|
8005b08: 460d mov r5, r1
|
|
8005b0a: f7fb f825 bl 8000b58 <__aeabi_d2iz>
|
|
8005b0e: 2200 movs r2, #0
|
|
8005b10: 4607 mov r7, r0
|
|
8005b12: 2300 movs r3, #0
|
|
8005b14: 4620 mov r0, r4
|
|
8005b16: 4629 mov r1, r5
|
|
8005b18: f7fa ffe0 bl 8000adc <__aeabi_dcmplt>
|
|
8005b1c: b140 cbz r0, 8005b30 <_dtoa_r+0x168>
|
|
8005b1e: 4638 mov r0, r7
|
|
8005b20: f7fa fd00 bl 8000524 <__aeabi_i2d>
|
|
8005b24: 4622 mov r2, r4
|
|
8005b26: 462b mov r3, r5
|
|
8005b28: f7fa ffce bl 8000ac8 <__aeabi_dcmpeq>
|
|
8005b2c: b900 cbnz r0, 8005b30 <_dtoa_r+0x168>
|
|
8005b2e: 3f01 subs r7, #1
|
|
8005b30: 2f16 cmp r7, #22
|
|
8005b32: d852 bhi.n 8005bda <_dtoa_r+0x212>
|
|
8005b34: 4b5d ldr r3, [pc, #372] @ (8005cac <_dtoa_r+0x2e4>)
|
|
8005b36: eb03 03c7 add.w r3, r3, r7, lsl #3
|
|
8005b3a: e9d3 2300 ldrd r2, r3, [r3]
|
|
8005b3e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
8005b42: f7fa ffcb bl 8000adc <__aeabi_dcmplt>
|
|
8005b46: 2800 cmp r0, #0
|
|
8005b48: d049 beq.n 8005bde <_dtoa_r+0x216>
|
|
8005b4a: 3f01 subs r7, #1
|
|
8005b4c: 2300 movs r3, #0
|
|
8005b4e: 9310 str r3, [sp, #64] @ 0x40
|
|
8005b50: 9b14 ldr r3, [sp, #80] @ 0x50
|
|
8005b52: 1b9b subs r3, r3, r6
|
|
8005b54: 1e5a subs r2, r3, #1
|
|
8005b56: bf45 ittet mi
|
|
8005b58: f1c3 0301 rsbmi r3, r3, #1
|
|
8005b5c: 9300 strmi r3, [sp, #0]
|
|
8005b5e: 2300 movpl r3, #0
|
|
8005b60: 2300 movmi r3, #0
|
|
8005b62: 9206 str r2, [sp, #24]
|
|
8005b64: bf54 ite pl
|
|
8005b66: 9300 strpl r3, [sp, #0]
|
|
8005b68: 9306 strmi r3, [sp, #24]
|
|
8005b6a: 2f00 cmp r7, #0
|
|
8005b6c: db39 blt.n 8005be2 <_dtoa_r+0x21a>
|
|
8005b6e: 9b06 ldr r3, [sp, #24]
|
|
8005b70: 970d str r7, [sp, #52] @ 0x34
|
|
8005b72: 443b add r3, r7
|
|
8005b74: 9306 str r3, [sp, #24]
|
|
8005b76: 2300 movs r3, #0
|
|
8005b78: 9308 str r3, [sp, #32]
|
|
8005b7a: 9b07 ldr r3, [sp, #28]
|
|
8005b7c: 2b09 cmp r3, #9
|
|
8005b7e: d863 bhi.n 8005c48 <_dtoa_r+0x280>
|
|
8005b80: 2b05 cmp r3, #5
|
|
8005b82: bfc4 itt gt
|
|
8005b84: 3b04 subgt r3, #4
|
|
8005b86: 9307 strgt r3, [sp, #28]
|
|
8005b88: 9b07 ldr r3, [sp, #28]
|
|
8005b8a: f1a3 0302 sub.w r3, r3, #2
|
|
8005b8e: bfcc ite gt
|
|
8005b90: 2400 movgt r4, #0
|
|
8005b92: 2401 movle r4, #1
|
|
8005b94: 2b03 cmp r3, #3
|
|
8005b96: d863 bhi.n 8005c60 <_dtoa_r+0x298>
|
|
8005b98: e8df f003 tbb [pc, r3]
|
|
8005b9c: 2b375452 .word 0x2b375452
|
|
8005ba0: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50
|
|
8005ba4: 441e add r6, r3
|
|
8005ba6: f206 4332 addw r3, r6, #1074 @ 0x432
|
|
8005baa: 2b20 cmp r3, #32
|
|
8005bac: bfc1 itttt gt
|
|
8005bae: f1c3 0340 rsbgt r3, r3, #64 @ 0x40
|
|
8005bb2: 409f lslgt r7, r3
|
|
8005bb4: f206 4312 addwgt r3, r6, #1042 @ 0x412
|
|
8005bb8: fa24 f303 lsrgt.w r3, r4, r3
|
|
8005bbc: bfd6 itet le
|
|
8005bbe: f1c3 0320 rsble r3, r3, #32
|
|
8005bc2: ea47 0003 orrgt.w r0, r7, r3
|
|
8005bc6: fa04 f003 lslle.w r0, r4, r3
|
|
8005bca: f7fa fc9b bl 8000504 <__aeabi_ui2d>
|
|
8005bce: 2201 movs r2, #1
|
|
8005bd0: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000
|
|
8005bd4: 3e01 subs r6, #1
|
|
8005bd6: 9212 str r2, [sp, #72] @ 0x48
|
|
8005bd8: e776 b.n 8005ac8 <_dtoa_r+0x100>
|
|
8005bda: 2301 movs r3, #1
|
|
8005bdc: e7b7 b.n 8005b4e <_dtoa_r+0x186>
|
|
8005bde: 9010 str r0, [sp, #64] @ 0x40
|
|
8005be0: e7b6 b.n 8005b50 <_dtoa_r+0x188>
|
|
8005be2: 9b00 ldr r3, [sp, #0]
|
|
8005be4: 1bdb subs r3, r3, r7
|
|
8005be6: 9300 str r3, [sp, #0]
|
|
8005be8: 427b negs r3, r7
|
|
8005bea: 9308 str r3, [sp, #32]
|
|
8005bec: 2300 movs r3, #0
|
|
8005bee: 930d str r3, [sp, #52] @ 0x34
|
|
8005bf0: e7c3 b.n 8005b7a <_dtoa_r+0x1b2>
|
|
8005bf2: 2301 movs r3, #1
|
|
8005bf4: 9309 str r3, [sp, #36] @ 0x24
|
|
8005bf6: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8005bf8: eb07 0b03 add.w fp, r7, r3
|
|
8005bfc: f10b 0301 add.w r3, fp, #1
|
|
8005c00: 2b01 cmp r3, #1
|
|
8005c02: 9303 str r3, [sp, #12]
|
|
8005c04: bfb8 it lt
|
|
8005c06: 2301 movlt r3, #1
|
|
8005c08: e006 b.n 8005c18 <_dtoa_r+0x250>
|
|
8005c0a: 2301 movs r3, #1
|
|
8005c0c: 9309 str r3, [sp, #36] @ 0x24
|
|
8005c0e: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8005c10: 2b00 cmp r3, #0
|
|
8005c12: dd28 ble.n 8005c66 <_dtoa_r+0x29e>
|
|
8005c14: 469b mov fp, r3
|
|
8005c16: 9303 str r3, [sp, #12]
|
|
8005c18: f8d9 001c ldr.w r0, [r9, #28]
|
|
8005c1c: 2100 movs r1, #0
|
|
8005c1e: 2204 movs r2, #4
|
|
8005c20: f102 0514 add.w r5, r2, #20
|
|
8005c24: 429d cmp r5, r3
|
|
8005c26: d926 bls.n 8005c76 <_dtoa_r+0x2ae>
|
|
8005c28: 6041 str r1, [r0, #4]
|
|
8005c2a: 4648 mov r0, r9
|
|
8005c2c: f000 fd9c bl 8006768 <_Balloc>
|
|
8005c30: 4682 mov sl, r0
|
|
8005c32: 2800 cmp r0, #0
|
|
8005c34: d142 bne.n 8005cbc <_dtoa_r+0x2f4>
|
|
8005c36: 4b1e ldr r3, [pc, #120] @ (8005cb0 <_dtoa_r+0x2e8>)
|
|
8005c38: 4602 mov r2, r0
|
|
8005c3a: f240 11af movw r1, #431 @ 0x1af
|
|
8005c3e: e6da b.n 80059f6 <_dtoa_r+0x2e>
|
|
8005c40: 2300 movs r3, #0
|
|
8005c42: e7e3 b.n 8005c0c <_dtoa_r+0x244>
|
|
8005c44: 2300 movs r3, #0
|
|
8005c46: e7d5 b.n 8005bf4 <_dtoa_r+0x22c>
|
|
8005c48: 2401 movs r4, #1
|
|
8005c4a: 2300 movs r3, #0
|
|
8005c4c: 9307 str r3, [sp, #28]
|
|
8005c4e: 9409 str r4, [sp, #36] @ 0x24
|
|
8005c50: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff
|
|
8005c54: 2200 movs r2, #0
|
|
8005c56: f8cd b00c str.w fp, [sp, #12]
|
|
8005c5a: 2312 movs r3, #18
|
|
8005c5c: 920c str r2, [sp, #48] @ 0x30
|
|
8005c5e: e7db b.n 8005c18 <_dtoa_r+0x250>
|
|
8005c60: 2301 movs r3, #1
|
|
8005c62: 9309 str r3, [sp, #36] @ 0x24
|
|
8005c64: e7f4 b.n 8005c50 <_dtoa_r+0x288>
|
|
8005c66: f04f 0b01 mov.w fp, #1
|
|
8005c6a: f8cd b00c str.w fp, [sp, #12]
|
|
8005c6e: 465b mov r3, fp
|
|
8005c70: f8cd b030 str.w fp, [sp, #48] @ 0x30
|
|
8005c74: e7d0 b.n 8005c18 <_dtoa_r+0x250>
|
|
8005c76: 3101 adds r1, #1
|
|
8005c78: 0052 lsls r2, r2, #1
|
|
8005c7a: e7d1 b.n 8005c20 <_dtoa_r+0x258>
|
|
8005c7c: f3af 8000 nop.w
|
|
8005c80: 636f4361 .word 0x636f4361
|
|
8005c84: 3fd287a7 .word 0x3fd287a7
|
|
8005c88: 8b60c8b3 .word 0x8b60c8b3
|
|
8005c8c: 3fc68a28 .word 0x3fc68a28
|
|
8005c90: 509f79fb .word 0x509f79fb
|
|
8005c94: 3fd34413 .word 0x3fd34413
|
|
8005c98: 08007595 .word 0x08007595
|
|
8005c9c: 080075ac .word 0x080075ac
|
|
8005ca0: 7ff00000 .word 0x7ff00000
|
|
8005ca4: 08007565 .word 0x08007565
|
|
8005ca8: 3ff80000 .word 0x3ff80000
|
|
8005cac: 08007700 .word 0x08007700
|
|
8005cb0: 08007604 .word 0x08007604
|
|
8005cb4: 08007591 .word 0x08007591
|
|
8005cb8: 08007564 .word 0x08007564
|
|
8005cbc: f8d9 301c ldr.w r3, [r9, #28]
|
|
8005cc0: 6018 str r0, [r3, #0]
|
|
8005cc2: 9b03 ldr r3, [sp, #12]
|
|
8005cc4: 2b0e cmp r3, #14
|
|
8005cc6: f200 80a1 bhi.w 8005e0c <_dtoa_r+0x444>
|
|
8005cca: 2c00 cmp r4, #0
|
|
8005ccc: f000 809e beq.w 8005e0c <_dtoa_r+0x444>
|
|
8005cd0: 2f00 cmp r7, #0
|
|
8005cd2: dd33 ble.n 8005d3c <_dtoa_r+0x374>
|
|
8005cd4: 4b9c ldr r3, [pc, #624] @ (8005f48 <_dtoa_r+0x580>)
|
|
8005cd6: f007 020f and.w r2, r7, #15
|
|
8005cda: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
8005cde: ed93 7b00 vldr d7, [r3]
|
|
8005ce2: 05f8 lsls r0, r7, #23
|
|
8005ce4: ed8d 7b0e vstr d7, [sp, #56] @ 0x38
|
|
8005ce8: ea4f 1427 mov.w r4, r7, asr #4
|
|
8005cec: d516 bpl.n 8005d1c <_dtoa_r+0x354>
|
|
8005cee: 4b97 ldr r3, [pc, #604] @ (8005f4c <_dtoa_r+0x584>)
|
|
8005cf0: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
8005cf4: e9d3 2308 ldrd r2, r3, [r3, #32]
|
|
8005cf8: f7fa fda8 bl 800084c <__aeabi_ddiv>
|
|
8005cfc: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8005d00: f004 040f and.w r4, r4, #15
|
|
8005d04: 2603 movs r6, #3
|
|
8005d06: 4d91 ldr r5, [pc, #580] @ (8005f4c <_dtoa_r+0x584>)
|
|
8005d08: b954 cbnz r4, 8005d20 <_dtoa_r+0x358>
|
|
8005d0a: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8005d0e: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005d12: f7fa fd9b bl 800084c <__aeabi_ddiv>
|
|
8005d16: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8005d1a: e028 b.n 8005d6e <_dtoa_r+0x3a6>
|
|
8005d1c: 2602 movs r6, #2
|
|
8005d1e: e7f2 b.n 8005d06 <_dtoa_r+0x33e>
|
|
8005d20: 07e1 lsls r1, r4, #31
|
|
8005d22: d508 bpl.n 8005d36 <_dtoa_r+0x36e>
|
|
8005d24: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8005d28: e9d5 2300 ldrd r2, r3, [r5]
|
|
8005d2c: f7fa fc64 bl 80005f8 <__aeabi_dmul>
|
|
8005d30: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8005d34: 3601 adds r6, #1
|
|
8005d36: 1064 asrs r4, r4, #1
|
|
8005d38: 3508 adds r5, #8
|
|
8005d3a: e7e5 b.n 8005d08 <_dtoa_r+0x340>
|
|
8005d3c: f000 80af beq.w 8005e9e <_dtoa_r+0x4d6>
|
|
8005d40: 427c negs r4, r7
|
|
8005d42: 4b81 ldr r3, [pc, #516] @ (8005f48 <_dtoa_r+0x580>)
|
|
8005d44: 4d81 ldr r5, [pc, #516] @ (8005f4c <_dtoa_r+0x584>)
|
|
8005d46: f004 020f and.w r2, r4, #15
|
|
8005d4a: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
8005d4e: e9d3 2300 ldrd r2, r3, [r3]
|
|
8005d52: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
8005d56: f7fa fc4f bl 80005f8 <__aeabi_dmul>
|
|
8005d5a: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8005d5e: 1124 asrs r4, r4, #4
|
|
8005d60: 2300 movs r3, #0
|
|
8005d62: 2602 movs r6, #2
|
|
8005d64: 2c00 cmp r4, #0
|
|
8005d66: f040 808f bne.w 8005e88 <_dtoa_r+0x4c0>
|
|
8005d6a: 2b00 cmp r3, #0
|
|
8005d6c: d1d3 bne.n 8005d16 <_dtoa_r+0x34e>
|
|
8005d6e: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
8005d70: e9dd 4504 ldrd r4, r5, [sp, #16]
|
|
8005d74: 2b00 cmp r3, #0
|
|
8005d76: f000 8094 beq.w 8005ea2 <_dtoa_r+0x4da>
|
|
8005d7a: 4b75 ldr r3, [pc, #468] @ (8005f50 <_dtoa_r+0x588>)
|
|
8005d7c: 2200 movs r2, #0
|
|
8005d7e: 4620 mov r0, r4
|
|
8005d80: 4629 mov r1, r5
|
|
8005d82: f7fa feab bl 8000adc <__aeabi_dcmplt>
|
|
8005d86: 2800 cmp r0, #0
|
|
8005d88: f000 808b beq.w 8005ea2 <_dtoa_r+0x4da>
|
|
8005d8c: 9b03 ldr r3, [sp, #12]
|
|
8005d8e: 2b00 cmp r3, #0
|
|
8005d90: f000 8087 beq.w 8005ea2 <_dtoa_r+0x4da>
|
|
8005d94: f1bb 0f00 cmp.w fp, #0
|
|
8005d98: dd34 ble.n 8005e04 <_dtoa_r+0x43c>
|
|
8005d9a: 4620 mov r0, r4
|
|
8005d9c: 4b6d ldr r3, [pc, #436] @ (8005f54 <_dtoa_r+0x58c>)
|
|
8005d9e: 2200 movs r2, #0
|
|
8005da0: 4629 mov r1, r5
|
|
8005da2: f7fa fc29 bl 80005f8 <__aeabi_dmul>
|
|
8005da6: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8005daa: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
|
|
8005dae: 3601 adds r6, #1
|
|
8005db0: 465c mov r4, fp
|
|
8005db2: 4630 mov r0, r6
|
|
8005db4: f7fa fbb6 bl 8000524 <__aeabi_i2d>
|
|
8005db8: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8005dbc: f7fa fc1c bl 80005f8 <__aeabi_dmul>
|
|
8005dc0: 4b65 ldr r3, [pc, #404] @ (8005f58 <_dtoa_r+0x590>)
|
|
8005dc2: 2200 movs r2, #0
|
|
8005dc4: f7fa fa62 bl 800028c <__adddf3>
|
|
8005dc8: 4605 mov r5, r0
|
|
8005dca: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000
|
|
8005dce: 2c00 cmp r4, #0
|
|
8005dd0: d16a bne.n 8005ea8 <_dtoa_r+0x4e0>
|
|
8005dd2: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005dd6: 4b61 ldr r3, [pc, #388] @ (8005f5c <_dtoa_r+0x594>)
|
|
8005dd8: 2200 movs r2, #0
|
|
8005dda: f7fa fa55 bl 8000288 <__aeabi_dsub>
|
|
8005dde: 4602 mov r2, r0
|
|
8005de0: 460b mov r3, r1
|
|
8005de2: e9cd 2304 strd r2, r3, [sp, #16]
|
|
8005de6: 462a mov r2, r5
|
|
8005de8: 4633 mov r3, r6
|
|
8005dea: f7fa fe95 bl 8000b18 <__aeabi_dcmpgt>
|
|
8005dee: 2800 cmp r0, #0
|
|
8005df0: f040 8298 bne.w 8006324 <_dtoa_r+0x95c>
|
|
8005df4: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005df8: 462a mov r2, r5
|
|
8005dfa: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000
|
|
8005dfe: f7fa fe6d bl 8000adc <__aeabi_dcmplt>
|
|
8005e02: bb38 cbnz r0, 8005e54 <_dtoa_r+0x48c>
|
|
8005e04: e9dd 340a ldrd r3, r4, [sp, #40] @ 0x28
|
|
8005e08: e9cd 3404 strd r3, r4, [sp, #16]
|
|
8005e0c: 9b15 ldr r3, [sp, #84] @ 0x54
|
|
8005e0e: 2b00 cmp r3, #0
|
|
8005e10: f2c0 8157 blt.w 80060c2 <_dtoa_r+0x6fa>
|
|
8005e14: 2f0e cmp r7, #14
|
|
8005e16: f300 8154 bgt.w 80060c2 <_dtoa_r+0x6fa>
|
|
8005e1a: 4b4b ldr r3, [pc, #300] @ (8005f48 <_dtoa_r+0x580>)
|
|
8005e1c: eb03 03c7 add.w r3, r3, r7, lsl #3
|
|
8005e20: ed93 7b00 vldr d7, [r3]
|
|
8005e24: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8005e26: 2b00 cmp r3, #0
|
|
8005e28: ed8d 7b00 vstr d7, [sp]
|
|
8005e2c: f280 80e5 bge.w 8005ffa <_dtoa_r+0x632>
|
|
8005e30: 9b03 ldr r3, [sp, #12]
|
|
8005e32: 2b00 cmp r3, #0
|
|
8005e34: f300 80e1 bgt.w 8005ffa <_dtoa_r+0x632>
|
|
8005e38: d10c bne.n 8005e54 <_dtoa_r+0x48c>
|
|
8005e3a: 4b48 ldr r3, [pc, #288] @ (8005f5c <_dtoa_r+0x594>)
|
|
8005e3c: 2200 movs r2, #0
|
|
8005e3e: ec51 0b17 vmov r0, r1, d7
|
|
8005e42: f7fa fbd9 bl 80005f8 <__aeabi_dmul>
|
|
8005e46: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8005e4a: f7fa fe5b bl 8000b04 <__aeabi_dcmpge>
|
|
8005e4e: 2800 cmp r0, #0
|
|
8005e50: f000 8266 beq.w 8006320 <_dtoa_r+0x958>
|
|
8005e54: 2400 movs r4, #0
|
|
8005e56: 4625 mov r5, r4
|
|
8005e58: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8005e5a: 4656 mov r6, sl
|
|
8005e5c: ea6f 0803 mvn.w r8, r3
|
|
8005e60: 2700 movs r7, #0
|
|
8005e62: 4621 mov r1, r4
|
|
8005e64: 4648 mov r0, r9
|
|
8005e66: f000 fcbf bl 80067e8 <_Bfree>
|
|
8005e6a: 2d00 cmp r5, #0
|
|
8005e6c: f000 80bd beq.w 8005fea <_dtoa_r+0x622>
|
|
8005e70: b12f cbz r7, 8005e7e <_dtoa_r+0x4b6>
|
|
8005e72: 42af cmp r7, r5
|
|
8005e74: d003 beq.n 8005e7e <_dtoa_r+0x4b6>
|
|
8005e76: 4639 mov r1, r7
|
|
8005e78: 4648 mov r0, r9
|
|
8005e7a: f000 fcb5 bl 80067e8 <_Bfree>
|
|
8005e7e: 4629 mov r1, r5
|
|
8005e80: 4648 mov r0, r9
|
|
8005e82: f000 fcb1 bl 80067e8 <_Bfree>
|
|
8005e86: e0b0 b.n 8005fea <_dtoa_r+0x622>
|
|
8005e88: 07e2 lsls r2, r4, #31
|
|
8005e8a: d505 bpl.n 8005e98 <_dtoa_r+0x4d0>
|
|
8005e8c: e9d5 2300 ldrd r2, r3, [r5]
|
|
8005e90: f7fa fbb2 bl 80005f8 <__aeabi_dmul>
|
|
8005e94: 3601 adds r6, #1
|
|
8005e96: 2301 movs r3, #1
|
|
8005e98: 1064 asrs r4, r4, #1
|
|
8005e9a: 3508 adds r5, #8
|
|
8005e9c: e762 b.n 8005d64 <_dtoa_r+0x39c>
|
|
8005e9e: 2602 movs r6, #2
|
|
8005ea0: e765 b.n 8005d6e <_dtoa_r+0x3a6>
|
|
8005ea2: 9c03 ldr r4, [sp, #12]
|
|
8005ea4: 46b8 mov r8, r7
|
|
8005ea6: e784 b.n 8005db2 <_dtoa_r+0x3ea>
|
|
8005ea8: 4b27 ldr r3, [pc, #156] @ (8005f48 <_dtoa_r+0x580>)
|
|
8005eaa: 9909 ldr r1, [sp, #36] @ 0x24
|
|
8005eac: eb03 03c4 add.w r3, r3, r4, lsl #3
|
|
8005eb0: e953 2302 ldrd r2, r3, [r3, #-8]
|
|
8005eb4: 4454 add r4, sl
|
|
8005eb6: 2900 cmp r1, #0
|
|
8005eb8: d054 beq.n 8005f64 <_dtoa_r+0x59c>
|
|
8005eba: 4929 ldr r1, [pc, #164] @ (8005f60 <_dtoa_r+0x598>)
|
|
8005ebc: 2000 movs r0, #0
|
|
8005ebe: f7fa fcc5 bl 800084c <__aeabi_ddiv>
|
|
8005ec2: 4633 mov r3, r6
|
|
8005ec4: 462a mov r2, r5
|
|
8005ec6: f7fa f9df bl 8000288 <__aeabi_dsub>
|
|
8005eca: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8005ece: 4656 mov r6, sl
|
|
8005ed0: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005ed4: f7fa fe40 bl 8000b58 <__aeabi_d2iz>
|
|
8005ed8: 4605 mov r5, r0
|
|
8005eda: f7fa fb23 bl 8000524 <__aeabi_i2d>
|
|
8005ede: 4602 mov r2, r0
|
|
8005ee0: 460b mov r3, r1
|
|
8005ee2: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005ee6: f7fa f9cf bl 8000288 <__aeabi_dsub>
|
|
8005eea: 3530 adds r5, #48 @ 0x30
|
|
8005eec: 4602 mov r2, r0
|
|
8005eee: 460b mov r3, r1
|
|
8005ef0: e9cd 2304 strd r2, r3, [sp, #16]
|
|
8005ef4: f806 5b01 strb.w r5, [r6], #1
|
|
8005ef8: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8005efc: f7fa fdee bl 8000adc <__aeabi_dcmplt>
|
|
8005f00: 2800 cmp r0, #0
|
|
8005f02: d172 bne.n 8005fea <_dtoa_r+0x622>
|
|
8005f04: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8005f08: 4911 ldr r1, [pc, #68] @ (8005f50 <_dtoa_r+0x588>)
|
|
8005f0a: 2000 movs r0, #0
|
|
8005f0c: f7fa f9bc bl 8000288 <__aeabi_dsub>
|
|
8005f10: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8005f14: f7fa fde2 bl 8000adc <__aeabi_dcmplt>
|
|
8005f18: 2800 cmp r0, #0
|
|
8005f1a: f040 80b4 bne.w 8006086 <_dtoa_r+0x6be>
|
|
8005f1e: 42a6 cmp r6, r4
|
|
8005f20: f43f af70 beq.w 8005e04 <_dtoa_r+0x43c>
|
|
8005f24: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8005f28: 4b0a ldr r3, [pc, #40] @ (8005f54 <_dtoa_r+0x58c>)
|
|
8005f2a: 2200 movs r2, #0
|
|
8005f2c: f7fa fb64 bl 80005f8 <__aeabi_dmul>
|
|
8005f30: 4b08 ldr r3, [pc, #32] @ (8005f54 <_dtoa_r+0x58c>)
|
|
8005f32: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8005f36: 2200 movs r2, #0
|
|
8005f38: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005f3c: f7fa fb5c bl 80005f8 <__aeabi_dmul>
|
|
8005f40: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8005f44: e7c4 b.n 8005ed0 <_dtoa_r+0x508>
|
|
8005f46: bf00 nop
|
|
8005f48: 08007700 .word 0x08007700
|
|
8005f4c: 080076d8 .word 0x080076d8
|
|
8005f50: 3ff00000 .word 0x3ff00000
|
|
8005f54: 40240000 .word 0x40240000
|
|
8005f58: 401c0000 .word 0x401c0000
|
|
8005f5c: 40140000 .word 0x40140000
|
|
8005f60: 3fe00000 .word 0x3fe00000
|
|
8005f64: 4631 mov r1, r6
|
|
8005f66: 4628 mov r0, r5
|
|
8005f68: f7fa fb46 bl 80005f8 <__aeabi_dmul>
|
|
8005f6c: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8005f70: 9413 str r4, [sp, #76] @ 0x4c
|
|
8005f72: 4656 mov r6, sl
|
|
8005f74: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005f78: f7fa fdee bl 8000b58 <__aeabi_d2iz>
|
|
8005f7c: 4605 mov r5, r0
|
|
8005f7e: f7fa fad1 bl 8000524 <__aeabi_i2d>
|
|
8005f82: 4602 mov r2, r0
|
|
8005f84: 460b mov r3, r1
|
|
8005f86: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005f8a: f7fa f97d bl 8000288 <__aeabi_dsub>
|
|
8005f8e: 3530 adds r5, #48 @ 0x30
|
|
8005f90: f806 5b01 strb.w r5, [r6], #1
|
|
8005f94: 4602 mov r2, r0
|
|
8005f96: 460b mov r3, r1
|
|
8005f98: 42a6 cmp r6, r4
|
|
8005f9a: e9cd 2304 strd r2, r3, [sp, #16]
|
|
8005f9e: f04f 0200 mov.w r2, #0
|
|
8005fa2: d124 bne.n 8005fee <_dtoa_r+0x626>
|
|
8005fa4: 4baf ldr r3, [pc, #700] @ (8006264 <_dtoa_r+0x89c>)
|
|
8005fa6: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8005faa: f7fa f96f bl 800028c <__adddf3>
|
|
8005fae: 4602 mov r2, r0
|
|
8005fb0: 460b mov r3, r1
|
|
8005fb2: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005fb6: f7fa fdaf bl 8000b18 <__aeabi_dcmpgt>
|
|
8005fba: 2800 cmp r0, #0
|
|
8005fbc: d163 bne.n 8006086 <_dtoa_r+0x6be>
|
|
8005fbe: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8005fc2: 49a8 ldr r1, [pc, #672] @ (8006264 <_dtoa_r+0x89c>)
|
|
8005fc4: 2000 movs r0, #0
|
|
8005fc6: f7fa f95f bl 8000288 <__aeabi_dsub>
|
|
8005fca: 4602 mov r2, r0
|
|
8005fcc: 460b mov r3, r1
|
|
8005fce: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8005fd2: f7fa fd83 bl 8000adc <__aeabi_dcmplt>
|
|
8005fd6: 2800 cmp r0, #0
|
|
8005fd8: f43f af14 beq.w 8005e04 <_dtoa_r+0x43c>
|
|
8005fdc: 9e13 ldr r6, [sp, #76] @ 0x4c
|
|
8005fde: 1e73 subs r3, r6, #1
|
|
8005fe0: 9313 str r3, [sp, #76] @ 0x4c
|
|
8005fe2: f816 3c01 ldrb.w r3, [r6, #-1]
|
|
8005fe6: 2b30 cmp r3, #48 @ 0x30
|
|
8005fe8: d0f8 beq.n 8005fdc <_dtoa_r+0x614>
|
|
8005fea: 4647 mov r7, r8
|
|
8005fec: e03b b.n 8006066 <_dtoa_r+0x69e>
|
|
8005fee: 4b9e ldr r3, [pc, #632] @ (8006268 <_dtoa_r+0x8a0>)
|
|
8005ff0: f7fa fb02 bl 80005f8 <__aeabi_dmul>
|
|
8005ff4: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8005ff8: e7bc b.n 8005f74 <_dtoa_r+0x5ac>
|
|
8005ffa: e9dd 4504 ldrd r4, r5, [sp, #16]
|
|
8005ffe: 4656 mov r6, sl
|
|
8006000: e9dd 2300 ldrd r2, r3, [sp]
|
|
8006004: 4620 mov r0, r4
|
|
8006006: 4629 mov r1, r5
|
|
8006008: f7fa fc20 bl 800084c <__aeabi_ddiv>
|
|
800600c: f7fa fda4 bl 8000b58 <__aeabi_d2iz>
|
|
8006010: 4680 mov r8, r0
|
|
8006012: f7fa fa87 bl 8000524 <__aeabi_i2d>
|
|
8006016: e9dd 2300 ldrd r2, r3, [sp]
|
|
800601a: f7fa faed bl 80005f8 <__aeabi_dmul>
|
|
800601e: 4602 mov r2, r0
|
|
8006020: 460b mov r3, r1
|
|
8006022: 4620 mov r0, r4
|
|
8006024: 4629 mov r1, r5
|
|
8006026: f108 0430 add.w r4, r8, #48 @ 0x30
|
|
800602a: f7fa f92d bl 8000288 <__aeabi_dsub>
|
|
800602e: f806 4b01 strb.w r4, [r6], #1
|
|
8006032: 9d03 ldr r5, [sp, #12]
|
|
8006034: eba6 040a sub.w r4, r6, sl
|
|
8006038: 42a5 cmp r5, r4
|
|
800603a: 4602 mov r2, r0
|
|
800603c: 460b mov r3, r1
|
|
800603e: d133 bne.n 80060a8 <_dtoa_r+0x6e0>
|
|
8006040: f7fa f924 bl 800028c <__adddf3>
|
|
8006044: e9dd 2300 ldrd r2, r3, [sp]
|
|
8006048: 4604 mov r4, r0
|
|
800604a: 460d mov r5, r1
|
|
800604c: f7fa fd64 bl 8000b18 <__aeabi_dcmpgt>
|
|
8006050: b9c0 cbnz r0, 8006084 <_dtoa_r+0x6bc>
|
|
8006052: e9dd 2300 ldrd r2, r3, [sp]
|
|
8006056: 4620 mov r0, r4
|
|
8006058: 4629 mov r1, r5
|
|
800605a: f7fa fd35 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800605e: b110 cbz r0, 8006066 <_dtoa_r+0x69e>
|
|
8006060: f018 0f01 tst.w r8, #1
|
|
8006064: d10e bne.n 8006084 <_dtoa_r+0x6bc>
|
|
8006066: 9902 ldr r1, [sp, #8]
|
|
8006068: 4648 mov r0, r9
|
|
800606a: f000 fbbd bl 80067e8 <_Bfree>
|
|
800606e: 2300 movs r3, #0
|
|
8006070: 7033 strb r3, [r6, #0]
|
|
8006072: 9b11 ldr r3, [sp, #68] @ 0x44
|
|
8006074: 3701 adds r7, #1
|
|
8006076: 601f str r7, [r3, #0]
|
|
8006078: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
800607a: 2b00 cmp r3, #0
|
|
800607c: f000 824b beq.w 8006516 <_dtoa_r+0xb4e>
|
|
8006080: 601e str r6, [r3, #0]
|
|
8006082: e248 b.n 8006516 <_dtoa_r+0xb4e>
|
|
8006084: 46b8 mov r8, r7
|
|
8006086: 4633 mov r3, r6
|
|
8006088: 461e mov r6, r3
|
|
800608a: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
800608e: 2a39 cmp r2, #57 @ 0x39
|
|
8006090: d106 bne.n 80060a0 <_dtoa_r+0x6d8>
|
|
8006092: 459a cmp sl, r3
|
|
8006094: d1f8 bne.n 8006088 <_dtoa_r+0x6c0>
|
|
8006096: 2230 movs r2, #48 @ 0x30
|
|
8006098: f108 0801 add.w r8, r8, #1
|
|
800609c: f88a 2000 strb.w r2, [sl]
|
|
80060a0: 781a ldrb r2, [r3, #0]
|
|
80060a2: 3201 adds r2, #1
|
|
80060a4: 701a strb r2, [r3, #0]
|
|
80060a6: e7a0 b.n 8005fea <_dtoa_r+0x622>
|
|
80060a8: 4b6f ldr r3, [pc, #444] @ (8006268 <_dtoa_r+0x8a0>)
|
|
80060aa: 2200 movs r2, #0
|
|
80060ac: f7fa faa4 bl 80005f8 <__aeabi_dmul>
|
|
80060b0: 2200 movs r2, #0
|
|
80060b2: 2300 movs r3, #0
|
|
80060b4: 4604 mov r4, r0
|
|
80060b6: 460d mov r5, r1
|
|
80060b8: f7fa fd06 bl 8000ac8 <__aeabi_dcmpeq>
|
|
80060bc: 2800 cmp r0, #0
|
|
80060be: d09f beq.n 8006000 <_dtoa_r+0x638>
|
|
80060c0: e7d1 b.n 8006066 <_dtoa_r+0x69e>
|
|
80060c2: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
80060c4: 2a00 cmp r2, #0
|
|
80060c6: f000 80ea beq.w 800629e <_dtoa_r+0x8d6>
|
|
80060ca: 9a07 ldr r2, [sp, #28]
|
|
80060cc: 2a01 cmp r2, #1
|
|
80060ce: f300 80cd bgt.w 800626c <_dtoa_r+0x8a4>
|
|
80060d2: 9a12 ldr r2, [sp, #72] @ 0x48
|
|
80060d4: 2a00 cmp r2, #0
|
|
80060d6: f000 80c1 beq.w 800625c <_dtoa_r+0x894>
|
|
80060da: f203 4333 addw r3, r3, #1075 @ 0x433
|
|
80060de: 9c08 ldr r4, [sp, #32]
|
|
80060e0: 9e00 ldr r6, [sp, #0]
|
|
80060e2: 9a00 ldr r2, [sp, #0]
|
|
80060e4: 441a add r2, r3
|
|
80060e6: 9200 str r2, [sp, #0]
|
|
80060e8: 9a06 ldr r2, [sp, #24]
|
|
80060ea: 2101 movs r1, #1
|
|
80060ec: 441a add r2, r3
|
|
80060ee: 4648 mov r0, r9
|
|
80060f0: 9206 str r2, [sp, #24]
|
|
80060f2: f000 fc2d bl 8006950 <__i2b>
|
|
80060f6: 4605 mov r5, r0
|
|
80060f8: b166 cbz r6, 8006114 <_dtoa_r+0x74c>
|
|
80060fa: 9b06 ldr r3, [sp, #24]
|
|
80060fc: 2b00 cmp r3, #0
|
|
80060fe: dd09 ble.n 8006114 <_dtoa_r+0x74c>
|
|
8006100: 42b3 cmp r3, r6
|
|
8006102: 9a00 ldr r2, [sp, #0]
|
|
8006104: bfa8 it ge
|
|
8006106: 4633 movge r3, r6
|
|
8006108: 1ad2 subs r2, r2, r3
|
|
800610a: 9200 str r2, [sp, #0]
|
|
800610c: 9a06 ldr r2, [sp, #24]
|
|
800610e: 1af6 subs r6, r6, r3
|
|
8006110: 1ad3 subs r3, r2, r3
|
|
8006112: 9306 str r3, [sp, #24]
|
|
8006114: 9b08 ldr r3, [sp, #32]
|
|
8006116: b30b cbz r3, 800615c <_dtoa_r+0x794>
|
|
8006118: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
800611a: 2b00 cmp r3, #0
|
|
800611c: f000 80c6 beq.w 80062ac <_dtoa_r+0x8e4>
|
|
8006120: 2c00 cmp r4, #0
|
|
8006122: f000 80c0 beq.w 80062a6 <_dtoa_r+0x8de>
|
|
8006126: 4629 mov r1, r5
|
|
8006128: 4622 mov r2, r4
|
|
800612a: 4648 mov r0, r9
|
|
800612c: f000 fcc8 bl 8006ac0 <__pow5mult>
|
|
8006130: 9a02 ldr r2, [sp, #8]
|
|
8006132: 4601 mov r1, r0
|
|
8006134: 4605 mov r5, r0
|
|
8006136: 4648 mov r0, r9
|
|
8006138: f000 fc20 bl 800697c <__multiply>
|
|
800613c: 9902 ldr r1, [sp, #8]
|
|
800613e: 4680 mov r8, r0
|
|
8006140: 4648 mov r0, r9
|
|
8006142: f000 fb51 bl 80067e8 <_Bfree>
|
|
8006146: 9b08 ldr r3, [sp, #32]
|
|
8006148: 1b1b subs r3, r3, r4
|
|
800614a: 9308 str r3, [sp, #32]
|
|
800614c: f000 80b1 beq.w 80062b2 <_dtoa_r+0x8ea>
|
|
8006150: 9a08 ldr r2, [sp, #32]
|
|
8006152: 4641 mov r1, r8
|
|
8006154: 4648 mov r0, r9
|
|
8006156: f000 fcb3 bl 8006ac0 <__pow5mult>
|
|
800615a: 9002 str r0, [sp, #8]
|
|
800615c: 2101 movs r1, #1
|
|
800615e: 4648 mov r0, r9
|
|
8006160: f000 fbf6 bl 8006950 <__i2b>
|
|
8006164: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8006166: 4604 mov r4, r0
|
|
8006168: 2b00 cmp r3, #0
|
|
800616a: f000 81d8 beq.w 800651e <_dtoa_r+0xb56>
|
|
800616e: 461a mov r2, r3
|
|
8006170: 4601 mov r1, r0
|
|
8006172: 4648 mov r0, r9
|
|
8006174: f000 fca4 bl 8006ac0 <__pow5mult>
|
|
8006178: 9b07 ldr r3, [sp, #28]
|
|
800617a: 2b01 cmp r3, #1
|
|
800617c: 4604 mov r4, r0
|
|
800617e: f300 809f bgt.w 80062c0 <_dtoa_r+0x8f8>
|
|
8006182: 9b04 ldr r3, [sp, #16]
|
|
8006184: 2b00 cmp r3, #0
|
|
8006186: f040 8097 bne.w 80062b8 <_dtoa_r+0x8f0>
|
|
800618a: 9b05 ldr r3, [sp, #20]
|
|
800618c: f3c3 0313 ubfx r3, r3, #0, #20
|
|
8006190: 2b00 cmp r3, #0
|
|
8006192: f040 8093 bne.w 80062bc <_dtoa_r+0x8f4>
|
|
8006196: 9b05 ldr r3, [sp, #20]
|
|
8006198: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
800619c: 0d1b lsrs r3, r3, #20
|
|
800619e: 051b lsls r3, r3, #20
|
|
80061a0: b133 cbz r3, 80061b0 <_dtoa_r+0x7e8>
|
|
80061a2: 9b00 ldr r3, [sp, #0]
|
|
80061a4: 3301 adds r3, #1
|
|
80061a6: 9300 str r3, [sp, #0]
|
|
80061a8: 9b06 ldr r3, [sp, #24]
|
|
80061aa: 3301 adds r3, #1
|
|
80061ac: 9306 str r3, [sp, #24]
|
|
80061ae: 2301 movs r3, #1
|
|
80061b0: 9308 str r3, [sp, #32]
|
|
80061b2: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
80061b4: 2b00 cmp r3, #0
|
|
80061b6: f000 81b8 beq.w 800652a <_dtoa_r+0xb62>
|
|
80061ba: 6923 ldr r3, [r4, #16]
|
|
80061bc: eb04 0383 add.w r3, r4, r3, lsl #2
|
|
80061c0: 6918 ldr r0, [r3, #16]
|
|
80061c2: f000 fb79 bl 80068b8 <__hi0bits>
|
|
80061c6: f1c0 0020 rsb r0, r0, #32
|
|
80061ca: 9b06 ldr r3, [sp, #24]
|
|
80061cc: 4418 add r0, r3
|
|
80061ce: f010 001f ands.w r0, r0, #31
|
|
80061d2: f000 8082 beq.w 80062da <_dtoa_r+0x912>
|
|
80061d6: f1c0 0320 rsb r3, r0, #32
|
|
80061da: 2b04 cmp r3, #4
|
|
80061dc: dd73 ble.n 80062c6 <_dtoa_r+0x8fe>
|
|
80061de: 9b00 ldr r3, [sp, #0]
|
|
80061e0: f1c0 001c rsb r0, r0, #28
|
|
80061e4: 4403 add r3, r0
|
|
80061e6: 9300 str r3, [sp, #0]
|
|
80061e8: 9b06 ldr r3, [sp, #24]
|
|
80061ea: 4403 add r3, r0
|
|
80061ec: 4406 add r6, r0
|
|
80061ee: 9306 str r3, [sp, #24]
|
|
80061f0: 9b00 ldr r3, [sp, #0]
|
|
80061f2: 2b00 cmp r3, #0
|
|
80061f4: dd05 ble.n 8006202 <_dtoa_r+0x83a>
|
|
80061f6: 9902 ldr r1, [sp, #8]
|
|
80061f8: 461a mov r2, r3
|
|
80061fa: 4648 mov r0, r9
|
|
80061fc: f000 fcba bl 8006b74 <__lshift>
|
|
8006200: 9002 str r0, [sp, #8]
|
|
8006202: 9b06 ldr r3, [sp, #24]
|
|
8006204: 2b00 cmp r3, #0
|
|
8006206: dd05 ble.n 8006214 <_dtoa_r+0x84c>
|
|
8006208: 4621 mov r1, r4
|
|
800620a: 461a mov r2, r3
|
|
800620c: 4648 mov r0, r9
|
|
800620e: f000 fcb1 bl 8006b74 <__lshift>
|
|
8006212: 4604 mov r4, r0
|
|
8006214: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
8006216: 2b00 cmp r3, #0
|
|
8006218: d061 beq.n 80062de <_dtoa_r+0x916>
|
|
800621a: 9802 ldr r0, [sp, #8]
|
|
800621c: 4621 mov r1, r4
|
|
800621e: f000 fd15 bl 8006c4c <__mcmp>
|
|
8006222: 2800 cmp r0, #0
|
|
8006224: da5b bge.n 80062de <_dtoa_r+0x916>
|
|
8006226: 2300 movs r3, #0
|
|
8006228: 9902 ldr r1, [sp, #8]
|
|
800622a: 220a movs r2, #10
|
|
800622c: 4648 mov r0, r9
|
|
800622e: f000 fafd bl 800682c <__multadd>
|
|
8006232: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8006234: 9002 str r0, [sp, #8]
|
|
8006236: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
|
|
800623a: 2b00 cmp r3, #0
|
|
800623c: f000 8177 beq.w 800652e <_dtoa_r+0xb66>
|
|
8006240: 4629 mov r1, r5
|
|
8006242: 2300 movs r3, #0
|
|
8006244: 220a movs r2, #10
|
|
8006246: 4648 mov r0, r9
|
|
8006248: f000 faf0 bl 800682c <__multadd>
|
|
800624c: f1bb 0f00 cmp.w fp, #0
|
|
8006250: 4605 mov r5, r0
|
|
8006252: dc6f bgt.n 8006334 <_dtoa_r+0x96c>
|
|
8006254: 9b07 ldr r3, [sp, #28]
|
|
8006256: 2b02 cmp r3, #2
|
|
8006258: dc49 bgt.n 80062ee <_dtoa_r+0x926>
|
|
800625a: e06b b.n 8006334 <_dtoa_r+0x96c>
|
|
800625c: 9b14 ldr r3, [sp, #80] @ 0x50
|
|
800625e: f1c3 0336 rsb r3, r3, #54 @ 0x36
|
|
8006262: e73c b.n 80060de <_dtoa_r+0x716>
|
|
8006264: 3fe00000 .word 0x3fe00000
|
|
8006268: 40240000 .word 0x40240000
|
|
800626c: 9b03 ldr r3, [sp, #12]
|
|
800626e: 1e5c subs r4, r3, #1
|
|
8006270: 9b08 ldr r3, [sp, #32]
|
|
8006272: 42a3 cmp r3, r4
|
|
8006274: db09 blt.n 800628a <_dtoa_r+0x8c2>
|
|
8006276: 1b1c subs r4, r3, r4
|
|
8006278: 9b03 ldr r3, [sp, #12]
|
|
800627a: 2b00 cmp r3, #0
|
|
800627c: f6bf af30 bge.w 80060e0 <_dtoa_r+0x718>
|
|
8006280: 9b00 ldr r3, [sp, #0]
|
|
8006282: 9a03 ldr r2, [sp, #12]
|
|
8006284: 1a9e subs r6, r3, r2
|
|
8006286: 2300 movs r3, #0
|
|
8006288: e72b b.n 80060e2 <_dtoa_r+0x71a>
|
|
800628a: 9b08 ldr r3, [sp, #32]
|
|
800628c: 9a0d ldr r2, [sp, #52] @ 0x34
|
|
800628e: 9408 str r4, [sp, #32]
|
|
8006290: 1ae3 subs r3, r4, r3
|
|
8006292: 441a add r2, r3
|
|
8006294: 9e00 ldr r6, [sp, #0]
|
|
8006296: 9b03 ldr r3, [sp, #12]
|
|
8006298: 920d str r2, [sp, #52] @ 0x34
|
|
800629a: 2400 movs r4, #0
|
|
800629c: e721 b.n 80060e2 <_dtoa_r+0x71a>
|
|
800629e: 9c08 ldr r4, [sp, #32]
|
|
80062a0: 9e00 ldr r6, [sp, #0]
|
|
80062a2: 9d09 ldr r5, [sp, #36] @ 0x24
|
|
80062a4: e728 b.n 80060f8 <_dtoa_r+0x730>
|
|
80062a6: f8dd 8008 ldr.w r8, [sp, #8]
|
|
80062aa: e751 b.n 8006150 <_dtoa_r+0x788>
|
|
80062ac: 9a08 ldr r2, [sp, #32]
|
|
80062ae: 9902 ldr r1, [sp, #8]
|
|
80062b0: e750 b.n 8006154 <_dtoa_r+0x78c>
|
|
80062b2: f8cd 8008 str.w r8, [sp, #8]
|
|
80062b6: e751 b.n 800615c <_dtoa_r+0x794>
|
|
80062b8: 2300 movs r3, #0
|
|
80062ba: e779 b.n 80061b0 <_dtoa_r+0x7e8>
|
|
80062bc: 9b04 ldr r3, [sp, #16]
|
|
80062be: e777 b.n 80061b0 <_dtoa_r+0x7e8>
|
|
80062c0: 2300 movs r3, #0
|
|
80062c2: 9308 str r3, [sp, #32]
|
|
80062c4: e779 b.n 80061ba <_dtoa_r+0x7f2>
|
|
80062c6: d093 beq.n 80061f0 <_dtoa_r+0x828>
|
|
80062c8: 9a00 ldr r2, [sp, #0]
|
|
80062ca: 331c adds r3, #28
|
|
80062cc: 441a add r2, r3
|
|
80062ce: 9200 str r2, [sp, #0]
|
|
80062d0: 9a06 ldr r2, [sp, #24]
|
|
80062d2: 441a add r2, r3
|
|
80062d4: 441e add r6, r3
|
|
80062d6: 9206 str r2, [sp, #24]
|
|
80062d8: e78a b.n 80061f0 <_dtoa_r+0x828>
|
|
80062da: 4603 mov r3, r0
|
|
80062dc: e7f4 b.n 80062c8 <_dtoa_r+0x900>
|
|
80062de: 9b03 ldr r3, [sp, #12]
|
|
80062e0: 2b00 cmp r3, #0
|
|
80062e2: 46b8 mov r8, r7
|
|
80062e4: dc20 bgt.n 8006328 <_dtoa_r+0x960>
|
|
80062e6: 469b mov fp, r3
|
|
80062e8: 9b07 ldr r3, [sp, #28]
|
|
80062ea: 2b02 cmp r3, #2
|
|
80062ec: dd1e ble.n 800632c <_dtoa_r+0x964>
|
|
80062ee: f1bb 0f00 cmp.w fp, #0
|
|
80062f2: f47f adb1 bne.w 8005e58 <_dtoa_r+0x490>
|
|
80062f6: 4621 mov r1, r4
|
|
80062f8: 465b mov r3, fp
|
|
80062fa: 2205 movs r2, #5
|
|
80062fc: 4648 mov r0, r9
|
|
80062fe: f000 fa95 bl 800682c <__multadd>
|
|
8006302: 4601 mov r1, r0
|
|
8006304: 4604 mov r4, r0
|
|
8006306: 9802 ldr r0, [sp, #8]
|
|
8006308: f000 fca0 bl 8006c4c <__mcmp>
|
|
800630c: 2800 cmp r0, #0
|
|
800630e: f77f ada3 ble.w 8005e58 <_dtoa_r+0x490>
|
|
8006312: 4656 mov r6, sl
|
|
8006314: 2331 movs r3, #49 @ 0x31
|
|
8006316: f806 3b01 strb.w r3, [r6], #1
|
|
800631a: f108 0801 add.w r8, r8, #1
|
|
800631e: e59f b.n 8005e60 <_dtoa_r+0x498>
|
|
8006320: 9c03 ldr r4, [sp, #12]
|
|
8006322: 46b8 mov r8, r7
|
|
8006324: 4625 mov r5, r4
|
|
8006326: e7f4 b.n 8006312 <_dtoa_r+0x94a>
|
|
8006328: f8dd b00c ldr.w fp, [sp, #12]
|
|
800632c: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
800632e: 2b00 cmp r3, #0
|
|
8006330: f000 8101 beq.w 8006536 <_dtoa_r+0xb6e>
|
|
8006334: 2e00 cmp r6, #0
|
|
8006336: dd05 ble.n 8006344 <_dtoa_r+0x97c>
|
|
8006338: 4629 mov r1, r5
|
|
800633a: 4632 mov r2, r6
|
|
800633c: 4648 mov r0, r9
|
|
800633e: f000 fc19 bl 8006b74 <__lshift>
|
|
8006342: 4605 mov r5, r0
|
|
8006344: 9b08 ldr r3, [sp, #32]
|
|
8006346: 2b00 cmp r3, #0
|
|
8006348: d05c beq.n 8006404 <_dtoa_r+0xa3c>
|
|
800634a: 6869 ldr r1, [r5, #4]
|
|
800634c: 4648 mov r0, r9
|
|
800634e: f000 fa0b bl 8006768 <_Balloc>
|
|
8006352: 4606 mov r6, r0
|
|
8006354: b928 cbnz r0, 8006362 <_dtoa_r+0x99a>
|
|
8006356: 4b82 ldr r3, [pc, #520] @ (8006560 <_dtoa_r+0xb98>)
|
|
8006358: 4602 mov r2, r0
|
|
800635a: f240 21ef movw r1, #751 @ 0x2ef
|
|
800635e: f7ff bb4a b.w 80059f6 <_dtoa_r+0x2e>
|
|
8006362: 692a ldr r2, [r5, #16]
|
|
8006364: 3202 adds r2, #2
|
|
8006366: 0092 lsls r2, r2, #2
|
|
8006368: f105 010c add.w r1, r5, #12
|
|
800636c: 300c adds r0, #12
|
|
800636e: f000 fff7 bl 8007360 <memcpy>
|
|
8006372: 2201 movs r2, #1
|
|
8006374: 4631 mov r1, r6
|
|
8006376: 4648 mov r0, r9
|
|
8006378: f000 fbfc bl 8006b74 <__lshift>
|
|
800637c: f10a 0301 add.w r3, sl, #1
|
|
8006380: 9300 str r3, [sp, #0]
|
|
8006382: eb0a 030b add.w r3, sl, fp
|
|
8006386: 9308 str r3, [sp, #32]
|
|
8006388: 9b04 ldr r3, [sp, #16]
|
|
800638a: f003 0301 and.w r3, r3, #1
|
|
800638e: 462f mov r7, r5
|
|
8006390: 9306 str r3, [sp, #24]
|
|
8006392: 4605 mov r5, r0
|
|
8006394: 9b00 ldr r3, [sp, #0]
|
|
8006396: 9802 ldr r0, [sp, #8]
|
|
8006398: 4621 mov r1, r4
|
|
800639a: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff
|
|
800639e: f7ff fa88 bl 80058b2 <quorem>
|
|
80063a2: 4603 mov r3, r0
|
|
80063a4: 3330 adds r3, #48 @ 0x30
|
|
80063a6: 9003 str r0, [sp, #12]
|
|
80063a8: 4639 mov r1, r7
|
|
80063aa: 9802 ldr r0, [sp, #8]
|
|
80063ac: 9309 str r3, [sp, #36] @ 0x24
|
|
80063ae: f000 fc4d bl 8006c4c <__mcmp>
|
|
80063b2: 462a mov r2, r5
|
|
80063b4: 9004 str r0, [sp, #16]
|
|
80063b6: 4621 mov r1, r4
|
|
80063b8: 4648 mov r0, r9
|
|
80063ba: f000 fc63 bl 8006c84 <__mdiff>
|
|
80063be: 68c2 ldr r2, [r0, #12]
|
|
80063c0: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80063c2: 4606 mov r6, r0
|
|
80063c4: bb02 cbnz r2, 8006408 <_dtoa_r+0xa40>
|
|
80063c6: 4601 mov r1, r0
|
|
80063c8: 9802 ldr r0, [sp, #8]
|
|
80063ca: f000 fc3f bl 8006c4c <__mcmp>
|
|
80063ce: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80063d0: 4602 mov r2, r0
|
|
80063d2: 4631 mov r1, r6
|
|
80063d4: 4648 mov r0, r9
|
|
80063d6: 920c str r2, [sp, #48] @ 0x30
|
|
80063d8: 9309 str r3, [sp, #36] @ 0x24
|
|
80063da: f000 fa05 bl 80067e8 <_Bfree>
|
|
80063de: 9b07 ldr r3, [sp, #28]
|
|
80063e0: 9a0c ldr r2, [sp, #48] @ 0x30
|
|
80063e2: 9e00 ldr r6, [sp, #0]
|
|
80063e4: ea42 0103 orr.w r1, r2, r3
|
|
80063e8: 9b06 ldr r3, [sp, #24]
|
|
80063ea: 4319 orrs r1, r3
|
|
80063ec: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80063ee: d10d bne.n 800640c <_dtoa_r+0xa44>
|
|
80063f0: 2b39 cmp r3, #57 @ 0x39
|
|
80063f2: d027 beq.n 8006444 <_dtoa_r+0xa7c>
|
|
80063f4: 9a04 ldr r2, [sp, #16]
|
|
80063f6: 2a00 cmp r2, #0
|
|
80063f8: dd01 ble.n 80063fe <_dtoa_r+0xa36>
|
|
80063fa: 9b03 ldr r3, [sp, #12]
|
|
80063fc: 3331 adds r3, #49 @ 0x31
|
|
80063fe: f88b 3000 strb.w r3, [fp]
|
|
8006402: e52e b.n 8005e62 <_dtoa_r+0x49a>
|
|
8006404: 4628 mov r0, r5
|
|
8006406: e7b9 b.n 800637c <_dtoa_r+0x9b4>
|
|
8006408: 2201 movs r2, #1
|
|
800640a: e7e2 b.n 80063d2 <_dtoa_r+0xa0a>
|
|
800640c: 9904 ldr r1, [sp, #16]
|
|
800640e: 2900 cmp r1, #0
|
|
8006410: db04 blt.n 800641c <_dtoa_r+0xa54>
|
|
8006412: 9807 ldr r0, [sp, #28]
|
|
8006414: 4301 orrs r1, r0
|
|
8006416: 9806 ldr r0, [sp, #24]
|
|
8006418: 4301 orrs r1, r0
|
|
800641a: d120 bne.n 800645e <_dtoa_r+0xa96>
|
|
800641c: 2a00 cmp r2, #0
|
|
800641e: ddee ble.n 80063fe <_dtoa_r+0xa36>
|
|
8006420: 9902 ldr r1, [sp, #8]
|
|
8006422: 9300 str r3, [sp, #0]
|
|
8006424: 2201 movs r2, #1
|
|
8006426: 4648 mov r0, r9
|
|
8006428: f000 fba4 bl 8006b74 <__lshift>
|
|
800642c: 4621 mov r1, r4
|
|
800642e: 9002 str r0, [sp, #8]
|
|
8006430: f000 fc0c bl 8006c4c <__mcmp>
|
|
8006434: 2800 cmp r0, #0
|
|
8006436: 9b00 ldr r3, [sp, #0]
|
|
8006438: dc02 bgt.n 8006440 <_dtoa_r+0xa78>
|
|
800643a: d1e0 bne.n 80063fe <_dtoa_r+0xa36>
|
|
800643c: 07da lsls r2, r3, #31
|
|
800643e: d5de bpl.n 80063fe <_dtoa_r+0xa36>
|
|
8006440: 2b39 cmp r3, #57 @ 0x39
|
|
8006442: d1da bne.n 80063fa <_dtoa_r+0xa32>
|
|
8006444: 2339 movs r3, #57 @ 0x39
|
|
8006446: f88b 3000 strb.w r3, [fp]
|
|
800644a: 4633 mov r3, r6
|
|
800644c: 461e mov r6, r3
|
|
800644e: 3b01 subs r3, #1
|
|
8006450: f816 2c01 ldrb.w r2, [r6, #-1]
|
|
8006454: 2a39 cmp r2, #57 @ 0x39
|
|
8006456: d04e beq.n 80064f6 <_dtoa_r+0xb2e>
|
|
8006458: 3201 adds r2, #1
|
|
800645a: 701a strb r2, [r3, #0]
|
|
800645c: e501 b.n 8005e62 <_dtoa_r+0x49a>
|
|
800645e: 2a00 cmp r2, #0
|
|
8006460: dd03 ble.n 800646a <_dtoa_r+0xaa2>
|
|
8006462: 2b39 cmp r3, #57 @ 0x39
|
|
8006464: d0ee beq.n 8006444 <_dtoa_r+0xa7c>
|
|
8006466: 3301 adds r3, #1
|
|
8006468: e7c9 b.n 80063fe <_dtoa_r+0xa36>
|
|
800646a: 9a00 ldr r2, [sp, #0]
|
|
800646c: 9908 ldr r1, [sp, #32]
|
|
800646e: f802 3c01 strb.w r3, [r2, #-1]
|
|
8006472: 428a cmp r2, r1
|
|
8006474: d028 beq.n 80064c8 <_dtoa_r+0xb00>
|
|
8006476: 9902 ldr r1, [sp, #8]
|
|
8006478: 2300 movs r3, #0
|
|
800647a: 220a movs r2, #10
|
|
800647c: 4648 mov r0, r9
|
|
800647e: f000 f9d5 bl 800682c <__multadd>
|
|
8006482: 42af cmp r7, r5
|
|
8006484: 9002 str r0, [sp, #8]
|
|
8006486: f04f 0300 mov.w r3, #0
|
|
800648a: f04f 020a mov.w r2, #10
|
|
800648e: 4639 mov r1, r7
|
|
8006490: 4648 mov r0, r9
|
|
8006492: d107 bne.n 80064a4 <_dtoa_r+0xadc>
|
|
8006494: f000 f9ca bl 800682c <__multadd>
|
|
8006498: 4607 mov r7, r0
|
|
800649a: 4605 mov r5, r0
|
|
800649c: 9b00 ldr r3, [sp, #0]
|
|
800649e: 3301 adds r3, #1
|
|
80064a0: 9300 str r3, [sp, #0]
|
|
80064a2: e777 b.n 8006394 <_dtoa_r+0x9cc>
|
|
80064a4: f000 f9c2 bl 800682c <__multadd>
|
|
80064a8: 4629 mov r1, r5
|
|
80064aa: 4607 mov r7, r0
|
|
80064ac: 2300 movs r3, #0
|
|
80064ae: 220a movs r2, #10
|
|
80064b0: 4648 mov r0, r9
|
|
80064b2: f000 f9bb bl 800682c <__multadd>
|
|
80064b6: 4605 mov r5, r0
|
|
80064b8: e7f0 b.n 800649c <_dtoa_r+0xad4>
|
|
80064ba: f1bb 0f00 cmp.w fp, #0
|
|
80064be: bfcc ite gt
|
|
80064c0: 465e movgt r6, fp
|
|
80064c2: 2601 movle r6, #1
|
|
80064c4: 4456 add r6, sl
|
|
80064c6: 2700 movs r7, #0
|
|
80064c8: 9902 ldr r1, [sp, #8]
|
|
80064ca: 9300 str r3, [sp, #0]
|
|
80064cc: 2201 movs r2, #1
|
|
80064ce: 4648 mov r0, r9
|
|
80064d0: f000 fb50 bl 8006b74 <__lshift>
|
|
80064d4: 4621 mov r1, r4
|
|
80064d6: 9002 str r0, [sp, #8]
|
|
80064d8: f000 fbb8 bl 8006c4c <__mcmp>
|
|
80064dc: 2800 cmp r0, #0
|
|
80064de: dcb4 bgt.n 800644a <_dtoa_r+0xa82>
|
|
80064e0: d102 bne.n 80064e8 <_dtoa_r+0xb20>
|
|
80064e2: 9b00 ldr r3, [sp, #0]
|
|
80064e4: 07db lsls r3, r3, #31
|
|
80064e6: d4b0 bmi.n 800644a <_dtoa_r+0xa82>
|
|
80064e8: 4633 mov r3, r6
|
|
80064ea: 461e mov r6, r3
|
|
80064ec: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
80064f0: 2a30 cmp r2, #48 @ 0x30
|
|
80064f2: d0fa beq.n 80064ea <_dtoa_r+0xb22>
|
|
80064f4: e4b5 b.n 8005e62 <_dtoa_r+0x49a>
|
|
80064f6: 459a cmp sl, r3
|
|
80064f8: d1a8 bne.n 800644c <_dtoa_r+0xa84>
|
|
80064fa: 2331 movs r3, #49 @ 0x31
|
|
80064fc: f108 0801 add.w r8, r8, #1
|
|
8006500: f88a 3000 strb.w r3, [sl]
|
|
8006504: e4ad b.n 8005e62 <_dtoa_r+0x49a>
|
|
8006506: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8006508: f8df a058 ldr.w sl, [pc, #88] @ 8006564 <_dtoa_r+0xb9c>
|
|
800650c: b11b cbz r3, 8006516 <_dtoa_r+0xb4e>
|
|
800650e: f10a 0308 add.w r3, sl, #8
|
|
8006512: 9a21 ldr r2, [sp, #132] @ 0x84
|
|
8006514: 6013 str r3, [r2, #0]
|
|
8006516: 4650 mov r0, sl
|
|
8006518: b017 add sp, #92 @ 0x5c
|
|
800651a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800651e: 9b07 ldr r3, [sp, #28]
|
|
8006520: 2b01 cmp r3, #1
|
|
8006522: f77f ae2e ble.w 8006182 <_dtoa_r+0x7ba>
|
|
8006526: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8006528: 9308 str r3, [sp, #32]
|
|
800652a: 2001 movs r0, #1
|
|
800652c: e64d b.n 80061ca <_dtoa_r+0x802>
|
|
800652e: f1bb 0f00 cmp.w fp, #0
|
|
8006532: f77f aed9 ble.w 80062e8 <_dtoa_r+0x920>
|
|
8006536: 4656 mov r6, sl
|
|
8006538: 9802 ldr r0, [sp, #8]
|
|
800653a: 4621 mov r1, r4
|
|
800653c: f7ff f9b9 bl 80058b2 <quorem>
|
|
8006540: f100 0330 add.w r3, r0, #48 @ 0x30
|
|
8006544: f806 3b01 strb.w r3, [r6], #1
|
|
8006548: eba6 020a sub.w r2, r6, sl
|
|
800654c: 4593 cmp fp, r2
|
|
800654e: ddb4 ble.n 80064ba <_dtoa_r+0xaf2>
|
|
8006550: 9902 ldr r1, [sp, #8]
|
|
8006552: 2300 movs r3, #0
|
|
8006554: 220a movs r2, #10
|
|
8006556: 4648 mov r0, r9
|
|
8006558: f000 f968 bl 800682c <__multadd>
|
|
800655c: 9002 str r0, [sp, #8]
|
|
800655e: e7eb b.n 8006538 <_dtoa_r+0xb70>
|
|
8006560: 08007604 .word 0x08007604
|
|
8006564: 08007588 .word 0x08007588
|
|
|
|
08006568 <_free_r>:
|
|
8006568: b538 push {r3, r4, r5, lr}
|
|
800656a: 4605 mov r5, r0
|
|
800656c: 2900 cmp r1, #0
|
|
800656e: d041 beq.n 80065f4 <_free_r+0x8c>
|
|
8006570: f851 3c04 ldr.w r3, [r1, #-4]
|
|
8006574: 1f0c subs r4, r1, #4
|
|
8006576: 2b00 cmp r3, #0
|
|
8006578: bfb8 it lt
|
|
800657a: 18e4 addlt r4, r4, r3
|
|
800657c: f000 f8e8 bl 8006750 <__malloc_lock>
|
|
8006580: 4a1d ldr r2, [pc, #116] @ (80065f8 <_free_r+0x90>)
|
|
8006582: 6813 ldr r3, [r2, #0]
|
|
8006584: b933 cbnz r3, 8006594 <_free_r+0x2c>
|
|
8006586: 6063 str r3, [r4, #4]
|
|
8006588: 6014 str r4, [r2, #0]
|
|
800658a: 4628 mov r0, r5
|
|
800658c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8006590: f000 b8e4 b.w 800675c <__malloc_unlock>
|
|
8006594: 42a3 cmp r3, r4
|
|
8006596: d908 bls.n 80065aa <_free_r+0x42>
|
|
8006598: 6820 ldr r0, [r4, #0]
|
|
800659a: 1821 adds r1, r4, r0
|
|
800659c: 428b cmp r3, r1
|
|
800659e: bf01 itttt eq
|
|
80065a0: 6819 ldreq r1, [r3, #0]
|
|
80065a2: 685b ldreq r3, [r3, #4]
|
|
80065a4: 1809 addeq r1, r1, r0
|
|
80065a6: 6021 streq r1, [r4, #0]
|
|
80065a8: e7ed b.n 8006586 <_free_r+0x1e>
|
|
80065aa: 461a mov r2, r3
|
|
80065ac: 685b ldr r3, [r3, #4]
|
|
80065ae: b10b cbz r3, 80065b4 <_free_r+0x4c>
|
|
80065b0: 42a3 cmp r3, r4
|
|
80065b2: d9fa bls.n 80065aa <_free_r+0x42>
|
|
80065b4: 6811 ldr r1, [r2, #0]
|
|
80065b6: 1850 adds r0, r2, r1
|
|
80065b8: 42a0 cmp r0, r4
|
|
80065ba: d10b bne.n 80065d4 <_free_r+0x6c>
|
|
80065bc: 6820 ldr r0, [r4, #0]
|
|
80065be: 4401 add r1, r0
|
|
80065c0: 1850 adds r0, r2, r1
|
|
80065c2: 4283 cmp r3, r0
|
|
80065c4: 6011 str r1, [r2, #0]
|
|
80065c6: d1e0 bne.n 800658a <_free_r+0x22>
|
|
80065c8: 6818 ldr r0, [r3, #0]
|
|
80065ca: 685b ldr r3, [r3, #4]
|
|
80065cc: 6053 str r3, [r2, #4]
|
|
80065ce: 4408 add r0, r1
|
|
80065d0: 6010 str r0, [r2, #0]
|
|
80065d2: e7da b.n 800658a <_free_r+0x22>
|
|
80065d4: d902 bls.n 80065dc <_free_r+0x74>
|
|
80065d6: 230c movs r3, #12
|
|
80065d8: 602b str r3, [r5, #0]
|
|
80065da: e7d6 b.n 800658a <_free_r+0x22>
|
|
80065dc: 6820 ldr r0, [r4, #0]
|
|
80065de: 1821 adds r1, r4, r0
|
|
80065e0: 428b cmp r3, r1
|
|
80065e2: bf04 itt eq
|
|
80065e4: 6819 ldreq r1, [r3, #0]
|
|
80065e6: 685b ldreq r3, [r3, #4]
|
|
80065e8: 6063 str r3, [r4, #4]
|
|
80065ea: bf04 itt eq
|
|
80065ec: 1809 addeq r1, r1, r0
|
|
80065ee: 6021 streq r1, [r4, #0]
|
|
80065f0: 6054 str r4, [r2, #4]
|
|
80065f2: e7ca b.n 800658a <_free_r+0x22>
|
|
80065f4: bd38 pop {r3, r4, r5, pc}
|
|
80065f6: bf00 nop
|
|
80065f8: 2000041c .word 0x2000041c
|
|
|
|
080065fc <malloc>:
|
|
80065fc: 4b02 ldr r3, [pc, #8] @ (8006608 <malloc+0xc>)
|
|
80065fe: 4601 mov r1, r0
|
|
8006600: 6818 ldr r0, [r3, #0]
|
|
8006602: f000 b825 b.w 8006650 <_malloc_r>
|
|
8006606: bf00 nop
|
|
8006608: 20000018 .word 0x20000018
|
|
|
|
0800660c <sbrk_aligned>:
|
|
800660c: b570 push {r4, r5, r6, lr}
|
|
800660e: 4e0f ldr r6, [pc, #60] @ (800664c <sbrk_aligned+0x40>)
|
|
8006610: 460c mov r4, r1
|
|
8006612: 6831 ldr r1, [r6, #0]
|
|
8006614: 4605 mov r5, r0
|
|
8006616: b911 cbnz r1, 800661e <sbrk_aligned+0x12>
|
|
8006618: f000 fe92 bl 8007340 <_sbrk_r>
|
|
800661c: 6030 str r0, [r6, #0]
|
|
800661e: 4621 mov r1, r4
|
|
8006620: 4628 mov r0, r5
|
|
8006622: f000 fe8d bl 8007340 <_sbrk_r>
|
|
8006626: 1c43 adds r3, r0, #1
|
|
8006628: d103 bne.n 8006632 <sbrk_aligned+0x26>
|
|
800662a: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
|
|
800662e: 4620 mov r0, r4
|
|
8006630: bd70 pop {r4, r5, r6, pc}
|
|
8006632: 1cc4 adds r4, r0, #3
|
|
8006634: f024 0403 bic.w r4, r4, #3
|
|
8006638: 42a0 cmp r0, r4
|
|
800663a: d0f8 beq.n 800662e <sbrk_aligned+0x22>
|
|
800663c: 1a21 subs r1, r4, r0
|
|
800663e: 4628 mov r0, r5
|
|
8006640: f000 fe7e bl 8007340 <_sbrk_r>
|
|
8006644: 3001 adds r0, #1
|
|
8006646: d1f2 bne.n 800662e <sbrk_aligned+0x22>
|
|
8006648: e7ef b.n 800662a <sbrk_aligned+0x1e>
|
|
800664a: bf00 nop
|
|
800664c: 20000418 .word 0x20000418
|
|
|
|
08006650 <_malloc_r>:
|
|
8006650: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
8006654: 1ccd adds r5, r1, #3
|
|
8006656: f025 0503 bic.w r5, r5, #3
|
|
800665a: 3508 adds r5, #8
|
|
800665c: 2d0c cmp r5, #12
|
|
800665e: bf38 it cc
|
|
8006660: 250c movcc r5, #12
|
|
8006662: 2d00 cmp r5, #0
|
|
8006664: 4606 mov r6, r0
|
|
8006666: db01 blt.n 800666c <_malloc_r+0x1c>
|
|
8006668: 42a9 cmp r1, r5
|
|
800666a: d904 bls.n 8006676 <_malloc_r+0x26>
|
|
800666c: 230c movs r3, #12
|
|
800666e: 6033 str r3, [r6, #0]
|
|
8006670: 2000 movs r0, #0
|
|
8006672: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
8006676: f8df 80d4 ldr.w r8, [pc, #212] @ 800674c <_malloc_r+0xfc>
|
|
800667a: f000 f869 bl 8006750 <__malloc_lock>
|
|
800667e: f8d8 3000 ldr.w r3, [r8]
|
|
8006682: 461c mov r4, r3
|
|
8006684: bb44 cbnz r4, 80066d8 <_malloc_r+0x88>
|
|
8006686: 4629 mov r1, r5
|
|
8006688: 4630 mov r0, r6
|
|
800668a: f7ff ffbf bl 800660c <sbrk_aligned>
|
|
800668e: 1c43 adds r3, r0, #1
|
|
8006690: 4604 mov r4, r0
|
|
8006692: d158 bne.n 8006746 <_malloc_r+0xf6>
|
|
8006694: f8d8 4000 ldr.w r4, [r8]
|
|
8006698: 4627 mov r7, r4
|
|
800669a: 2f00 cmp r7, #0
|
|
800669c: d143 bne.n 8006726 <_malloc_r+0xd6>
|
|
800669e: 2c00 cmp r4, #0
|
|
80066a0: d04b beq.n 800673a <_malloc_r+0xea>
|
|
80066a2: 6823 ldr r3, [r4, #0]
|
|
80066a4: 4639 mov r1, r7
|
|
80066a6: 4630 mov r0, r6
|
|
80066a8: eb04 0903 add.w r9, r4, r3
|
|
80066ac: f000 fe48 bl 8007340 <_sbrk_r>
|
|
80066b0: 4581 cmp r9, r0
|
|
80066b2: d142 bne.n 800673a <_malloc_r+0xea>
|
|
80066b4: 6821 ldr r1, [r4, #0]
|
|
80066b6: 1a6d subs r5, r5, r1
|
|
80066b8: 4629 mov r1, r5
|
|
80066ba: 4630 mov r0, r6
|
|
80066bc: f7ff ffa6 bl 800660c <sbrk_aligned>
|
|
80066c0: 3001 adds r0, #1
|
|
80066c2: d03a beq.n 800673a <_malloc_r+0xea>
|
|
80066c4: 6823 ldr r3, [r4, #0]
|
|
80066c6: 442b add r3, r5
|
|
80066c8: 6023 str r3, [r4, #0]
|
|
80066ca: f8d8 3000 ldr.w r3, [r8]
|
|
80066ce: 685a ldr r2, [r3, #4]
|
|
80066d0: bb62 cbnz r2, 800672c <_malloc_r+0xdc>
|
|
80066d2: f8c8 7000 str.w r7, [r8]
|
|
80066d6: e00f b.n 80066f8 <_malloc_r+0xa8>
|
|
80066d8: 6822 ldr r2, [r4, #0]
|
|
80066da: 1b52 subs r2, r2, r5
|
|
80066dc: d420 bmi.n 8006720 <_malloc_r+0xd0>
|
|
80066de: 2a0b cmp r2, #11
|
|
80066e0: d917 bls.n 8006712 <_malloc_r+0xc2>
|
|
80066e2: 1961 adds r1, r4, r5
|
|
80066e4: 42a3 cmp r3, r4
|
|
80066e6: 6025 str r5, [r4, #0]
|
|
80066e8: bf18 it ne
|
|
80066ea: 6059 strne r1, [r3, #4]
|
|
80066ec: 6863 ldr r3, [r4, #4]
|
|
80066ee: bf08 it eq
|
|
80066f0: f8c8 1000 streq.w r1, [r8]
|
|
80066f4: 5162 str r2, [r4, r5]
|
|
80066f6: 604b str r3, [r1, #4]
|
|
80066f8: 4630 mov r0, r6
|
|
80066fa: f000 f82f bl 800675c <__malloc_unlock>
|
|
80066fe: f104 000b add.w r0, r4, #11
|
|
8006702: 1d23 adds r3, r4, #4
|
|
8006704: f020 0007 bic.w r0, r0, #7
|
|
8006708: 1ac2 subs r2, r0, r3
|
|
800670a: bf1c itt ne
|
|
800670c: 1a1b subne r3, r3, r0
|
|
800670e: 50a3 strne r3, [r4, r2]
|
|
8006710: e7af b.n 8006672 <_malloc_r+0x22>
|
|
8006712: 6862 ldr r2, [r4, #4]
|
|
8006714: 42a3 cmp r3, r4
|
|
8006716: bf0c ite eq
|
|
8006718: f8c8 2000 streq.w r2, [r8]
|
|
800671c: 605a strne r2, [r3, #4]
|
|
800671e: e7eb b.n 80066f8 <_malloc_r+0xa8>
|
|
8006720: 4623 mov r3, r4
|
|
8006722: 6864 ldr r4, [r4, #4]
|
|
8006724: e7ae b.n 8006684 <_malloc_r+0x34>
|
|
8006726: 463c mov r4, r7
|
|
8006728: 687f ldr r7, [r7, #4]
|
|
800672a: e7b6 b.n 800669a <_malloc_r+0x4a>
|
|
800672c: 461a mov r2, r3
|
|
800672e: 685b ldr r3, [r3, #4]
|
|
8006730: 42a3 cmp r3, r4
|
|
8006732: d1fb bne.n 800672c <_malloc_r+0xdc>
|
|
8006734: 2300 movs r3, #0
|
|
8006736: 6053 str r3, [r2, #4]
|
|
8006738: e7de b.n 80066f8 <_malloc_r+0xa8>
|
|
800673a: 230c movs r3, #12
|
|
800673c: 6033 str r3, [r6, #0]
|
|
800673e: 4630 mov r0, r6
|
|
8006740: f000 f80c bl 800675c <__malloc_unlock>
|
|
8006744: e794 b.n 8006670 <_malloc_r+0x20>
|
|
8006746: 6005 str r5, [r0, #0]
|
|
8006748: e7d6 b.n 80066f8 <_malloc_r+0xa8>
|
|
800674a: bf00 nop
|
|
800674c: 2000041c .word 0x2000041c
|
|
|
|
08006750 <__malloc_lock>:
|
|
8006750: 4801 ldr r0, [pc, #4] @ (8006758 <__malloc_lock+0x8>)
|
|
8006752: f7ff b8ac b.w 80058ae <__retarget_lock_acquire_recursive>
|
|
8006756: bf00 nop
|
|
8006758: 20000414 .word 0x20000414
|
|
|
|
0800675c <__malloc_unlock>:
|
|
800675c: 4801 ldr r0, [pc, #4] @ (8006764 <__malloc_unlock+0x8>)
|
|
800675e: f7ff b8a7 b.w 80058b0 <__retarget_lock_release_recursive>
|
|
8006762: bf00 nop
|
|
8006764: 20000414 .word 0x20000414
|
|
|
|
08006768 <_Balloc>:
|
|
8006768: b570 push {r4, r5, r6, lr}
|
|
800676a: 69c6 ldr r6, [r0, #28]
|
|
800676c: 4604 mov r4, r0
|
|
800676e: 460d mov r5, r1
|
|
8006770: b976 cbnz r6, 8006790 <_Balloc+0x28>
|
|
8006772: 2010 movs r0, #16
|
|
8006774: f7ff ff42 bl 80065fc <malloc>
|
|
8006778: 4602 mov r2, r0
|
|
800677a: 61e0 str r0, [r4, #28]
|
|
800677c: b920 cbnz r0, 8006788 <_Balloc+0x20>
|
|
800677e: 4b18 ldr r3, [pc, #96] @ (80067e0 <_Balloc+0x78>)
|
|
8006780: 4818 ldr r0, [pc, #96] @ (80067e4 <_Balloc+0x7c>)
|
|
8006782: 216b movs r1, #107 @ 0x6b
|
|
8006784: f000 fdfa bl 800737c <__assert_func>
|
|
8006788: e9c0 6601 strd r6, r6, [r0, #4]
|
|
800678c: 6006 str r6, [r0, #0]
|
|
800678e: 60c6 str r6, [r0, #12]
|
|
8006790: 69e6 ldr r6, [r4, #28]
|
|
8006792: 68f3 ldr r3, [r6, #12]
|
|
8006794: b183 cbz r3, 80067b8 <_Balloc+0x50>
|
|
8006796: 69e3 ldr r3, [r4, #28]
|
|
8006798: 68db ldr r3, [r3, #12]
|
|
800679a: f853 0025 ldr.w r0, [r3, r5, lsl #2]
|
|
800679e: b9b8 cbnz r0, 80067d0 <_Balloc+0x68>
|
|
80067a0: 2101 movs r1, #1
|
|
80067a2: fa01 f605 lsl.w r6, r1, r5
|
|
80067a6: 1d72 adds r2, r6, #5
|
|
80067a8: 0092 lsls r2, r2, #2
|
|
80067aa: 4620 mov r0, r4
|
|
80067ac: f000 fe04 bl 80073b8 <_calloc_r>
|
|
80067b0: b160 cbz r0, 80067cc <_Balloc+0x64>
|
|
80067b2: e9c0 5601 strd r5, r6, [r0, #4]
|
|
80067b6: e00e b.n 80067d6 <_Balloc+0x6e>
|
|
80067b8: 2221 movs r2, #33 @ 0x21
|
|
80067ba: 2104 movs r1, #4
|
|
80067bc: 4620 mov r0, r4
|
|
80067be: f000 fdfb bl 80073b8 <_calloc_r>
|
|
80067c2: 69e3 ldr r3, [r4, #28]
|
|
80067c4: 60f0 str r0, [r6, #12]
|
|
80067c6: 68db ldr r3, [r3, #12]
|
|
80067c8: 2b00 cmp r3, #0
|
|
80067ca: d1e4 bne.n 8006796 <_Balloc+0x2e>
|
|
80067cc: 2000 movs r0, #0
|
|
80067ce: bd70 pop {r4, r5, r6, pc}
|
|
80067d0: 6802 ldr r2, [r0, #0]
|
|
80067d2: f843 2025 str.w r2, [r3, r5, lsl #2]
|
|
80067d6: 2300 movs r3, #0
|
|
80067d8: e9c0 3303 strd r3, r3, [r0, #12]
|
|
80067dc: e7f7 b.n 80067ce <_Balloc+0x66>
|
|
80067de: bf00 nop
|
|
80067e0: 08007595 .word 0x08007595
|
|
80067e4: 08007615 .word 0x08007615
|
|
|
|
080067e8 <_Bfree>:
|
|
80067e8: b570 push {r4, r5, r6, lr}
|
|
80067ea: 69c6 ldr r6, [r0, #28]
|
|
80067ec: 4605 mov r5, r0
|
|
80067ee: 460c mov r4, r1
|
|
80067f0: b976 cbnz r6, 8006810 <_Bfree+0x28>
|
|
80067f2: 2010 movs r0, #16
|
|
80067f4: f7ff ff02 bl 80065fc <malloc>
|
|
80067f8: 4602 mov r2, r0
|
|
80067fa: 61e8 str r0, [r5, #28]
|
|
80067fc: b920 cbnz r0, 8006808 <_Bfree+0x20>
|
|
80067fe: 4b09 ldr r3, [pc, #36] @ (8006824 <_Bfree+0x3c>)
|
|
8006800: 4809 ldr r0, [pc, #36] @ (8006828 <_Bfree+0x40>)
|
|
8006802: 218f movs r1, #143 @ 0x8f
|
|
8006804: f000 fdba bl 800737c <__assert_func>
|
|
8006808: e9c0 6601 strd r6, r6, [r0, #4]
|
|
800680c: 6006 str r6, [r0, #0]
|
|
800680e: 60c6 str r6, [r0, #12]
|
|
8006810: b13c cbz r4, 8006822 <_Bfree+0x3a>
|
|
8006812: 69eb ldr r3, [r5, #28]
|
|
8006814: 6862 ldr r2, [r4, #4]
|
|
8006816: 68db ldr r3, [r3, #12]
|
|
8006818: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
800681c: 6021 str r1, [r4, #0]
|
|
800681e: f843 4022 str.w r4, [r3, r2, lsl #2]
|
|
8006822: bd70 pop {r4, r5, r6, pc}
|
|
8006824: 08007595 .word 0x08007595
|
|
8006828: 08007615 .word 0x08007615
|
|
|
|
0800682c <__multadd>:
|
|
800682c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8006830: 690d ldr r5, [r1, #16]
|
|
8006832: 4607 mov r7, r0
|
|
8006834: 460c mov r4, r1
|
|
8006836: 461e mov r6, r3
|
|
8006838: f101 0c14 add.w ip, r1, #20
|
|
800683c: 2000 movs r0, #0
|
|
800683e: f8dc 3000 ldr.w r3, [ip]
|
|
8006842: b299 uxth r1, r3
|
|
8006844: fb02 6101 mla r1, r2, r1, r6
|
|
8006848: 0c1e lsrs r6, r3, #16
|
|
800684a: 0c0b lsrs r3, r1, #16
|
|
800684c: fb02 3306 mla r3, r2, r6, r3
|
|
8006850: b289 uxth r1, r1
|
|
8006852: 3001 adds r0, #1
|
|
8006854: eb01 4103 add.w r1, r1, r3, lsl #16
|
|
8006858: 4285 cmp r5, r0
|
|
800685a: f84c 1b04 str.w r1, [ip], #4
|
|
800685e: ea4f 4613 mov.w r6, r3, lsr #16
|
|
8006862: dcec bgt.n 800683e <__multadd+0x12>
|
|
8006864: b30e cbz r6, 80068aa <__multadd+0x7e>
|
|
8006866: 68a3 ldr r3, [r4, #8]
|
|
8006868: 42ab cmp r3, r5
|
|
800686a: dc19 bgt.n 80068a0 <__multadd+0x74>
|
|
800686c: 6861 ldr r1, [r4, #4]
|
|
800686e: 4638 mov r0, r7
|
|
8006870: 3101 adds r1, #1
|
|
8006872: f7ff ff79 bl 8006768 <_Balloc>
|
|
8006876: 4680 mov r8, r0
|
|
8006878: b928 cbnz r0, 8006886 <__multadd+0x5a>
|
|
800687a: 4602 mov r2, r0
|
|
800687c: 4b0c ldr r3, [pc, #48] @ (80068b0 <__multadd+0x84>)
|
|
800687e: 480d ldr r0, [pc, #52] @ (80068b4 <__multadd+0x88>)
|
|
8006880: 21ba movs r1, #186 @ 0xba
|
|
8006882: f000 fd7b bl 800737c <__assert_func>
|
|
8006886: 6922 ldr r2, [r4, #16]
|
|
8006888: 3202 adds r2, #2
|
|
800688a: f104 010c add.w r1, r4, #12
|
|
800688e: 0092 lsls r2, r2, #2
|
|
8006890: 300c adds r0, #12
|
|
8006892: f000 fd65 bl 8007360 <memcpy>
|
|
8006896: 4621 mov r1, r4
|
|
8006898: 4638 mov r0, r7
|
|
800689a: f7ff ffa5 bl 80067e8 <_Bfree>
|
|
800689e: 4644 mov r4, r8
|
|
80068a0: eb04 0385 add.w r3, r4, r5, lsl #2
|
|
80068a4: 3501 adds r5, #1
|
|
80068a6: 615e str r6, [r3, #20]
|
|
80068a8: 6125 str r5, [r4, #16]
|
|
80068aa: 4620 mov r0, r4
|
|
80068ac: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
80068b0: 08007604 .word 0x08007604
|
|
80068b4: 08007615 .word 0x08007615
|
|
|
|
080068b8 <__hi0bits>:
|
|
80068b8: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
|
|
80068bc: 4603 mov r3, r0
|
|
80068be: bf36 itet cc
|
|
80068c0: 0403 lslcc r3, r0, #16
|
|
80068c2: 2000 movcs r0, #0
|
|
80068c4: 2010 movcc r0, #16
|
|
80068c6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80068ca: bf3c itt cc
|
|
80068cc: 021b lslcc r3, r3, #8
|
|
80068ce: 3008 addcc r0, #8
|
|
80068d0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
80068d4: bf3c itt cc
|
|
80068d6: 011b lslcc r3, r3, #4
|
|
80068d8: 3004 addcc r0, #4
|
|
80068da: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80068de: bf3c itt cc
|
|
80068e0: 009b lslcc r3, r3, #2
|
|
80068e2: 3002 addcc r0, #2
|
|
80068e4: 2b00 cmp r3, #0
|
|
80068e6: db05 blt.n 80068f4 <__hi0bits+0x3c>
|
|
80068e8: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
|
|
80068ec: f100 0001 add.w r0, r0, #1
|
|
80068f0: bf08 it eq
|
|
80068f2: 2020 moveq r0, #32
|
|
80068f4: 4770 bx lr
|
|
|
|
080068f6 <__lo0bits>:
|
|
80068f6: 6803 ldr r3, [r0, #0]
|
|
80068f8: 4602 mov r2, r0
|
|
80068fa: f013 0007 ands.w r0, r3, #7
|
|
80068fe: d00b beq.n 8006918 <__lo0bits+0x22>
|
|
8006900: 07d9 lsls r1, r3, #31
|
|
8006902: d421 bmi.n 8006948 <__lo0bits+0x52>
|
|
8006904: 0798 lsls r0, r3, #30
|
|
8006906: bf49 itett mi
|
|
8006908: 085b lsrmi r3, r3, #1
|
|
800690a: 089b lsrpl r3, r3, #2
|
|
800690c: 2001 movmi r0, #1
|
|
800690e: 6013 strmi r3, [r2, #0]
|
|
8006910: bf5c itt pl
|
|
8006912: 6013 strpl r3, [r2, #0]
|
|
8006914: 2002 movpl r0, #2
|
|
8006916: 4770 bx lr
|
|
8006918: b299 uxth r1, r3
|
|
800691a: b909 cbnz r1, 8006920 <__lo0bits+0x2a>
|
|
800691c: 0c1b lsrs r3, r3, #16
|
|
800691e: 2010 movs r0, #16
|
|
8006920: b2d9 uxtb r1, r3
|
|
8006922: b909 cbnz r1, 8006928 <__lo0bits+0x32>
|
|
8006924: 3008 adds r0, #8
|
|
8006926: 0a1b lsrs r3, r3, #8
|
|
8006928: 0719 lsls r1, r3, #28
|
|
800692a: bf04 itt eq
|
|
800692c: 091b lsreq r3, r3, #4
|
|
800692e: 3004 addeq r0, #4
|
|
8006930: 0799 lsls r1, r3, #30
|
|
8006932: bf04 itt eq
|
|
8006934: 089b lsreq r3, r3, #2
|
|
8006936: 3002 addeq r0, #2
|
|
8006938: 07d9 lsls r1, r3, #31
|
|
800693a: d403 bmi.n 8006944 <__lo0bits+0x4e>
|
|
800693c: 085b lsrs r3, r3, #1
|
|
800693e: f100 0001 add.w r0, r0, #1
|
|
8006942: d003 beq.n 800694c <__lo0bits+0x56>
|
|
8006944: 6013 str r3, [r2, #0]
|
|
8006946: 4770 bx lr
|
|
8006948: 2000 movs r0, #0
|
|
800694a: 4770 bx lr
|
|
800694c: 2020 movs r0, #32
|
|
800694e: 4770 bx lr
|
|
|
|
08006950 <__i2b>:
|
|
8006950: b510 push {r4, lr}
|
|
8006952: 460c mov r4, r1
|
|
8006954: 2101 movs r1, #1
|
|
8006956: f7ff ff07 bl 8006768 <_Balloc>
|
|
800695a: 4602 mov r2, r0
|
|
800695c: b928 cbnz r0, 800696a <__i2b+0x1a>
|
|
800695e: 4b05 ldr r3, [pc, #20] @ (8006974 <__i2b+0x24>)
|
|
8006960: 4805 ldr r0, [pc, #20] @ (8006978 <__i2b+0x28>)
|
|
8006962: f240 1145 movw r1, #325 @ 0x145
|
|
8006966: f000 fd09 bl 800737c <__assert_func>
|
|
800696a: 2301 movs r3, #1
|
|
800696c: 6144 str r4, [r0, #20]
|
|
800696e: 6103 str r3, [r0, #16]
|
|
8006970: bd10 pop {r4, pc}
|
|
8006972: bf00 nop
|
|
8006974: 08007604 .word 0x08007604
|
|
8006978: 08007615 .word 0x08007615
|
|
|
|
0800697c <__multiply>:
|
|
800697c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8006980: 4617 mov r7, r2
|
|
8006982: 690a ldr r2, [r1, #16]
|
|
8006984: 693b ldr r3, [r7, #16]
|
|
8006986: 429a cmp r2, r3
|
|
8006988: bfa8 it ge
|
|
800698a: 463b movge r3, r7
|
|
800698c: 4689 mov r9, r1
|
|
800698e: bfa4 itt ge
|
|
8006990: 460f movge r7, r1
|
|
8006992: 4699 movge r9, r3
|
|
8006994: 693d ldr r5, [r7, #16]
|
|
8006996: f8d9 a010 ldr.w sl, [r9, #16]
|
|
800699a: 68bb ldr r3, [r7, #8]
|
|
800699c: 6879 ldr r1, [r7, #4]
|
|
800699e: eb05 060a add.w r6, r5, sl
|
|
80069a2: 42b3 cmp r3, r6
|
|
80069a4: b085 sub sp, #20
|
|
80069a6: bfb8 it lt
|
|
80069a8: 3101 addlt r1, #1
|
|
80069aa: f7ff fedd bl 8006768 <_Balloc>
|
|
80069ae: b930 cbnz r0, 80069be <__multiply+0x42>
|
|
80069b0: 4602 mov r2, r0
|
|
80069b2: 4b41 ldr r3, [pc, #260] @ (8006ab8 <__multiply+0x13c>)
|
|
80069b4: 4841 ldr r0, [pc, #260] @ (8006abc <__multiply+0x140>)
|
|
80069b6: f44f 71b1 mov.w r1, #354 @ 0x162
|
|
80069ba: f000 fcdf bl 800737c <__assert_func>
|
|
80069be: f100 0414 add.w r4, r0, #20
|
|
80069c2: eb04 0e86 add.w lr, r4, r6, lsl #2
|
|
80069c6: 4623 mov r3, r4
|
|
80069c8: 2200 movs r2, #0
|
|
80069ca: 4573 cmp r3, lr
|
|
80069cc: d320 bcc.n 8006a10 <__multiply+0x94>
|
|
80069ce: f107 0814 add.w r8, r7, #20
|
|
80069d2: f109 0114 add.w r1, r9, #20
|
|
80069d6: eb08 0585 add.w r5, r8, r5, lsl #2
|
|
80069da: eb01 038a add.w r3, r1, sl, lsl #2
|
|
80069de: 9302 str r3, [sp, #8]
|
|
80069e0: 1beb subs r3, r5, r7
|
|
80069e2: 3b15 subs r3, #21
|
|
80069e4: f023 0303 bic.w r3, r3, #3
|
|
80069e8: 3304 adds r3, #4
|
|
80069ea: 3715 adds r7, #21
|
|
80069ec: 42bd cmp r5, r7
|
|
80069ee: bf38 it cc
|
|
80069f0: 2304 movcc r3, #4
|
|
80069f2: 9301 str r3, [sp, #4]
|
|
80069f4: 9b02 ldr r3, [sp, #8]
|
|
80069f6: 9103 str r1, [sp, #12]
|
|
80069f8: 428b cmp r3, r1
|
|
80069fa: d80c bhi.n 8006a16 <__multiply+0x9a>
|
|
80069fc: 2e00 cmp r6, #0
|
|
80069fe: dd03 ble.n 8006a08 <__multiply+0x8c>
|
|
8006a00: f85e 3d04 ldr.w r3, [lr, #-4]!
|
|
8006a04: 2b00 cmp r3, #0
|
|
8006a06: d055 beq.n 8006ab4 <__multiply+0x138>
|
|
8006a08: 6106 str r6, [r0, #16]
|
|
8006a0a: b005 add sp, #20
|
|
8006a0c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8006a10: f843 2b04 str.w r2, [r3], #4
|
|
8006a14: e7d9 b.n 80069ca <__multiply+0x4e>
|
|
8006a16: f8b1 a000 ldrh.w sl, [r1]
|
|
8006a1a: f1ba 0f00 cmp.w sl, #0
|
|
8006a1e: d01f beq.n 8006a60 <__multiply+0xe4>
|
|
8006a20: 46c4 mov ip, r8
|
|
8006a22: 46a1 mov r9, r4
|
|
8006a24: 2700 movs r7, #0
|
|
8006a26: f85c 2b04 ldr.w r2, [ip], #4
|
|
8006a2a: f8d9 3000 ldr.w r3, [r9]
|
|
8006a2e: fa1f fb82 uxth.w fp, r2
|
|
8006a32: b29b uxth r3, r3
|
|
8006a34: fb0a 330b mla r3, sl, fp, r3
|
|
8006a38: 443b add r3, r7
|
|
8006a3a: f8d9 7000 ldr.w r7, [r9]
|
|
8006a3e: 0c12 lsrs r2, r2, #16
|
|
8006a40: 0c3f lsrs r7, r7, #16
|
|
8006a42: fb0a 7202 mla r2, sl, r2, r7
|
|
8006a46: eb02 4213 add.w r2, r2, r3, lsr #16
|
|
8006a4a: b29b uxth r3, r3
|
|
8006a4c: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8006a50: 4565 cmp r5, ip
|
|
8006a52: f849 3b04 str.w r3, [r9], #4
|
|
8006a56: ea4f 4712 mov.w r7, r2, lsr #16
|
|
8006a5a: d8e4 bhi.n 8006a26 <__multiply+0xaa>
|
|
8006a5c: 9b01 ldr r3, [sp, #4]
|
|
8006a5e: 50e7 str r7, [r4, r3]
|
|
8006a60: 9b03 ldr r3, [sp, #12]
|
|
8006a62: f8b3 9002 ldrh.w r9, [r3, #2]
|
|
8006a66: 3104 adds r1, #4
|
|
8006a68: f1b9 0f00 cmp.w r9, #0
|
|
8006a6c: d020 beq.n 8006ab0 <__multiply+0x134>
|
|
8006a6e: 6823 ldr r3, [r4, #0]
|
|
8006a70: 4647 mov r7, r8
|
|
8006a72: 46a4 mov ip, r4
|
|
8006a74: f04f 0a00 mov.w sl, #0
|
|
8006a78: f8b7 b000 ldrh.w fp, [r7]
|
|
8006a7c: f8bc 2002 ldrh.w r2, [ip, #2]
|
|
8006a80: fb09 220b mla r2, r9, fp, r2
|
|
8006a84: 4452 add r2, sl
|
|
8006a86: b29b uxth r3, r3
|
|
8006a88: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8006a8c: f84c 3b04 str.w r3, [ip], #4
|
|
8006a90: f857 3b04 ldr.w r3, [r7], #4
|
|
8006a94: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
8006a98: f8bc 3000 ldrh.w r3, [ip]
|
|
8006a9c: fb09 330a mla r3, r9, sl, r3
|
|
8006aa0: eb03 4312 add.w r3, r3, r2, lsr #16
|
|
8006aa4: 42bd cmp r5, r7
|
|
8006aa6: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
8006aaa: d8e5 bhi.n 8006a78 <__multiply+0xfc>
|
|
8006aac: 9a01 ldr r2, [sp, #4]
|
|
8006aae: 50a3 str r3, [r4, r2]
|
|
8006ab0: 3404 adds r4, #4
|
|
8006ab2: e79f b.n 80069f4 <__multiply+0x78>
|
|
8006ab4: 3e01 subs r6, #1
|
|
8006ab6: e7a1 b.n 80069fc <__multiply+0x80>
|
|
8006ab8: 08007604 .word 0x08007604
|
|
8006abc: 08007615 .word 0x08007615
|
|
|
|
08006ac0 <__pow5mult>:
|
|
8006ac0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
8006ac4: 4615 mov r5, r2
|
|
8006ac6: f012 0203 ands.w r2, r2, #3
|
|
8006aca: 4607 mov r7, r0
|
|
8006acc: 460e mov r6, r1
|
|
8006ace: d007 beq.n 8006ae0 <__pow5mult+0x20>
|
|
8006ad0: 4c25 ldr r4, [pc, #148] @ (8006b68 <__pow5mult+0xa8>)
|
|
8006ad2: 3a01 subs r2, #1
|
|
8006ad4: 2300 movs r3, #0
|
|
8006ad6: f854 2022 ldr.w r2, [r4, r2, lsl #2]
|
|
8006ada: f7ff fea7 bl 800682c <__multadd>
|
|
8006ade: 4606 mov r6, r0
|
|
8006ae0: 10ad asrs r5, r5, #2
|
|
8006ae2: d03d beq.n 8006b60 <__pow5mult+0xa0>
|
|
8006ae4: 69fc ldr r4, [r7, #28]
|
|
8006ae6: b97c cbnz r4, 8006b08 <__pow5mult+0x48>
|
|
8006ae8: 2010 movs r0, #16
|
|
8006aea: f7ff fd87 bl 80065fc <malloc>
|
|
8006aee: 4602 mov r2, r0
|
|
8006af0: 61f8 str r0, [r7, #28]
|
|
8006af2: b928 cbnz r0, 8006b00 <__pow5mult+0x40>
|
|
8006af4: 4b1d ldr r3, [pc, #116] @ (8006b6c <__pow5mult+0xac>)
|
|
8006af6: 481e ldr r0, [pc, #120] @ (8006b70 <__pow5mult+0xb0>)
|
|
8006af8: f240 11b3 movw r1, #435 @ 0x1b3
|
|
8006afc: f000 fc3e bl 800737c <__assert_func>
|
|
8006b00: e9c0 4401 strd r4, r4, [r0, #4]
|
|
8006b04: 6004 str r4, [r0, #0]
|
|
8006b06: 60c4 str r4, [r0, #12]
|
|
8006b08: f8d7 801c ldr.w r8, [r7, #28]
|
|
8006b0c: f8d8 4008 ldr.w r4, [r8, #8]
|
|
8006b10: b94c cbnz r4, 8006b26 <__pow5mult+0x66>
|
|
8006b12: f240 2171 movw r1, #625 @ 0x271
|
|
8006b16: 4638 mov r0, r7
|
|
8006b18: f7ff ff1a bl 8006950 <__i2b>
|
|
8006b1c: 2300 movs r3, #0
|
|
8006b1e: f8c8 0008 str.w r0, [r8, #8]
|
|
8006b22: 4604 mov r4, r0
|
|
8006b24: 6003 str r3, [r0, #0]
|
|
8006b26: f04f 0900 mov.w r9, #0
|
|
8006b2a: 07eb lsls r3, r5, #31
|
|
8006b2c: d50a bpl.n 8006b44 <__pow5mult+0x84>
|
|
8006b2e: 4631 mov r1, r6
|
|
8006b30: 4622 mov r2, r4
|
|
8006b32: 4638 mov r0, r7
|
|
8006b34: f7ff ff22 bl 800697c <__multiply>
|
|
8006b38: 4631 mov r1, r6
|
|
8006b3a: 4680 mov r8, r0
|
|
8006b3c: 4638 mov r0, r7
|
|
8006b3e: f7ff fe53 bl 80067e8 <_Bfree>
|
|
8006b42: 4646 mov r6, r8
|
|
8006b44: 106d asrs r5, r5, #1
|
|
8006b46: d00b beq.n 8006b60 <__pow5mult+0xa0>
|
|
8006b48: 6820 ldr r0, [r4, #0]
|
|
8006b4a: b938 cbnz r0, 8006b5c <__pow5mult+0x9c>
|
|
8006b4c: 4622 mov r2, r4
|
|
8006b4e: 4621 mov r1, r4
|
|
8006b50: 4638 mov r0, r7
|
|
8006b52: f7ff ff13 bl 800697c <__multiply>
|
|
8006b56: 6020 str r0, [r4, #0]
|
|
8006b58: f8c0 9000 str.w r9, [r0]
|
|
8006b5c: 4604 mov r4, r0
|
|
8006b5e: e7e4 b.n 8006b2a <__pow5mult+0x6a>
|
|
8006b60: 4630 mov r0, r6
|
|
8006b62: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
8006b66: bf00 nop
|
|
8006b68: 080076c8 .word 0x080076c8
|
|
8006b6c: 08007595 .word 0x08007595
|
|
8006b70: 08007615 .word 0x08007615
|
|
|
|
08006b74 <__lshift>:
|
|
8006b74: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8006b78: 460c mov r4, r1
|
|
8006b7a: 6849 ldr r1, [r1, #4]
|
|
8006b7c: 6923 ldr r3, [r4, #16]
|
|
8006b7e: eb03 1862 add.w r8, r3, r2, asr #5
|
|
8006b82: 68a3 ldr r3, [r4, #8]
|
|
8006b84: 4607 mov r7, r0
|
|
8006b86: 4691 mov r9, r2
|
|
8006b88: ea4f 1a62 mov.w sl, r2, asr #5
|
|
8006b8c: f108 0601 add.w r6, r8, #1
|
|
8006b90: 42b3 cmp r3, r6
|
|
8006b92: db0b blt.n 8006bac <__lshift+0x38>
|
|
8006b94: 4638 mov r0, r7
|
|
8006b96: f7ff fde7 bl 8006768 <_Balloc>
|
|
8006b9a: 4605 mov r5, r0
|
|
8006b9c: b948 cbnz r0, 8006bb2 <__lshift+0x3e>
|
|
8006b9e: 4602 mov r2, r0
|
|
8006ba0: 4b28 ldr r3, [pc, #160] @ (8006c44 <__lshift+0xd0>)
|
|
8006ba2: 4829 ldr r0, [pc, #164] @ (8006c48 <__lshift+0xd4>)
|
|
8006ba4: f44f 71ef mov.w r1, #478 @ 0x1de
|
|
8006ba8: f000 fbe8 bl 800737c <__assert_func>
|
|
8006bac: 3101 adds r1, #1
|
|
8006bae: 005b lsls r3, r3, #1
|
|
8006bb0: e7ee b.n 8006b90 <__lshift+0x1c>
|
|
8006bb2: 2300 movs r3, #0
|
|
8006bb4: f100 0114 add.w r1, r0, #20
|
|
8006bb8: f100 0210 add.w r2, r0, #16
|
|
8006bbc: 4618 mov r0, r3
|
|
8006bbe: 4553 cmp r3, sl
|
|
8006bc0: db33 blt.n 8006c2a <__lshift+0xb6>
|
|
8006bc2: 6920 ldr r0, [r4, #16]
|
|
8006bc4: ea2a 7aea bic.w sl, sl, sl, asr #31
|
|
8006bc8: f104 0314 add.w r3, r4, #20
|
|
8006bcc: f019 091f ands.w r9, r9, #31
|
|
8006bd0: eb01 018a add.w r1, r1, sl, lsl #2
|
|
8006bd4: eb03 0c80 add.w ip, r3, r0, lsl #2
|
|
8006bd8: d02b beq.n 8006c32 <__lshift+0xbe>
|
|
8006bda: f1c9 0e20 rsb lr, r9, #32
|
|
8006bde: 468a mov sl, r1
|
|
8006be0: 2200 movs r2, #0
|
|
8006be2: 6818 ldr r0, [r3, #0]
|
|
8006be4: fa00 f009 lsl.w r0, r0, r9
|
|
8006be8: 4310 orrs r0, r2
|
|
8006bea: f84a 0b04 str.w r0, [sl], #4
|
|
8006bee: f853 2b04 ldr.w r2, [r3], #4
|
|
8006bf2: 459c cmp ip, r3
|
|
8006bf4: fa22 f20e lsr.w r2, r2, lr
|
|
8006bf8: d8f3 bhi.n 8006be2 <__lshift+0x6e>
|
|
8006bfa: ebac 0304 sub.w r3, ip, r4
|
|
8006bfe: 3b15 subs r3, #21
|
|
8006c00: f023 0303 bic.w r3, r3, #3
|
|
8006c04: 3304 adds r3, #4
|
|
8006c06: f104 0015 add.w r0, r4, #21
|
|
8006c0a: 4560 cmp r0, ip
|
|
8006c0c: bf88 it hi
|
|
8006c0e: 2304 movhi r3, #4
|
|
8006c10: 50ca str r2, [r1, r3]
|
|
8006c12: b10a cbz r2, 8006c18 <__lshift+0xa4>
|
|
8006c14: f108 0602 add.w r6, r8, #2
|
|
8006c18: 3e01 subs r6, #1
|
|
8006c1a: 4638 mov r0, r7
|
|
8006c1c: 612e str r6, [r5, #16]
|
|
8006c1e: 4621 mov r1, r4
|
|
8006c20: f7ff fde2 bl 80067e8 <_Bfree>
|
|
8006c24: 4628 mov r0, r5
|
|
8006c26: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8006c2a: f842 0f04 str.w r0, [r2, #4]!
|
|
8006c2e: 3301 adds r3, #1
|
|
8006c30: e7c5 b.n 8006bbe <__lshift+0x4a>
|
|
8006c32: 3904 subs r1, #4
|
|
8006c34: f853 2b04 ldr.w r2, [r3], #4
|
|
8006c38: f841 2f04 str.w r2, [r1, #4]!
|
|
8006c3c: 459c cmp ip, r3
|
|
8006c3e: d8f9 bhi.n 8006c34 <__lshift+0xc0>
|
|
8006c40: e7ea b.n 8006c18 <__lshift+0xa4>
|
|
8006c42: bf00 nop
|
|
8006c44: 08007604 .word 0x08007604
|
|
8006c48: 08007615 .word 0x08007615
|
|
|
|
08006c4c <__mcmp>:
|
|
8006c4c: 690a ldr r2, [r1, #16]
|
|
8006c4e: 4603 mov r3, r0
|
|
8006c50: 6900 ldr r0, [r0, #16]
|
|
8006c52: 1a80 subs r0, r0, r2
|
|
8006c54: b530 push {r4, r5, lr}
|
|
8006c56: d10e bne.n 8006c76 <__mcmp+0x2a>
|
|
8006c58: 3314 adds r3, #20
|
|
8006c5a: 3114 adds r1, #20
|
|
8006c5c: eb03 0482 add.w r4, r3, r2, lsl #2
|
|
8006c60: eb01 0182 add.w r1, r1, r2, lsl #2
|
|
8006c64: f854 5d04 ldr.w r5, [r4, #-4]!
|
|
8006c68: f851 2d04 ldr.w r2, [r1, #-4]!
|
|
8006c6c: 4295 cmp r5, r2
|
|
8006c6e: d003 beq.n 8006c78 <__mcmp+0x2c>
|
|
8006c70: d205 bcs.n 8006c7e <__mcmp+0x32>
|
|
8006c72: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8006c76: bd30 pop {r4, r5, pc}
|
|
8006c78: 42a3 cmp r3, r4
|
|
8006c7a: d3f3 bcc.n 8006c64 <__mcmp+0x18>
|
|
8006c7c: e7fb b.n 8006c76 <__mcmp+0x2a>
|
|
8006c7e: 2001 movs r0, #1
|
|
8006c80: e7f9 b.n 8006c76 <__mcmp+0x2a>
|
|
...
|
|
|
|
08006c84 <__mdiff>:
|
|
8006c84: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8006c88: 4689 mov r9, r1
|
|
8006c8a: 4606 mov r6, r0
|
|
8006c8c: 4611 mov r1, r2
|
|
8006c8e: 4648 mov r0, r9
|
|
8006c90: 4614 mov r4, r2
|
|
8006c92: f7ff ffdb bl 8006c4c <__mcmp>
|
|
8006c96: 1e05 subs r5, r0, #0
|
|
8006c98: d112 bne.n 8006cc0 <__mdiff+0x3c>
|
|
8006c9a: 4629 mov r1, r5
|
|
8006c9c: 4630 mov r0, r6
|
|
8006c9e: f7ff fd63 bl 8006768 <_Balloc>
|
|
8006ca2: 4602 mov r2, r0
|
|
8006ca4: b928 cbnz r0, 8006cb2 <__mdiff+0x2e>
|
|
8006ca6: 4b3f ldr r3, [pc, #252] @ (8006da4 <__mdiff+0x120>)
|
|
8006ca8: f240 2137 movw r1, #567 @ 0x237
|
|
8006cac: 483e ldr r0, [pc, #248] @ (8006da8 <__mdiff+0x124>)
|
|
8006cae: f000 fb65 bl 800737c <__assert_func>
|
|
8006cb2: 2301 movs r3, #1
|
|
8006cb4: e9c0 3504 strd r3, r5, [r0, #16]
|
|
8006cb8: 4610 mov r0, r2
|
|
8006cba: b003 add sp, #12
|
|
8006cbc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8006cc0: bfbc itt lt
|
|
8006cc2: 464b movlt r3, r9
|
|
8006cc4: 46a1 movlt r9, r4
|
|
8006cc6: 4630 mov r0, r6
|
|
8006cc8: f8d9 1004 ldr.w r1, [r9, #4]
|
|
8006ccc: bfba itte lt
|
|
8006cce: 461c movlt r4, r3
|
|
8006cd0: 2501 movlt r5, #1
|
|
8006cd2: 2500 movge r5, #0
|
|
8006cd4: f7ff fd48 bl 8006768 <_Balloc>
|
|
8006cd8: 4602 mov r2, r0
|
|
8006cda: b918 cbnz r0, 8006ce4 <__mdiff+0x60>
|
|
8006cdc: 4b31 ldr r3, [pc, #196] @ (8006da4 <__mdiff+0x120>)
|
|
8006cde: f240 2145 movw r1, #581 @ 0x245
|
|
8006ce2: e7e3 b.n 8006cac <__mdiff+0x28>
|
|
8006ce4: f8d9 7010 ldr.w r7, [r9, #16]
|
|
8006ce8: 6926 ldr r6, [r4, #16]
|
|
8006cea: 60c5 str r5, [r0, #12]
|
|
8006cec: f109 0310 add.w r3, r9, #16
|
|
8006cf0: f109 0514 add.w r5, r9, #20
|
|
8006cf4: f104 0e14 add.w lr, r4, #20
|
|
8006cf8: f100 0b14 add.w fp, r0, #20
|
|
8006cfc: eb05 0887 add.w r8, r5, r7, lsl #2
|
|
8006d00: eb0e 0686 add.w r6, lr, r6, lsl #2
|
|
8006d04: 9301 str r3, [sp, #4]
|
|
8006d06: 46d9 mov r9, fp
|
|
8006d08: f04f 0c00 mov.w ip, #0
|
|
8006d0c: 9b01 ldr r3, [sp, #4]
|
|
8006d0e: f85e 0b04 ldr.w r0, [lr], #4
|
|
8006d12: f853 af04 ldr.w sl, [r3, #4]!
|
|
8006d16: 9301 str r3, [sp, #4]
|
|
8006d18: fa1f f38a uxth.w r3, sl
|
|
8006d1c: 4619 mov r1, r3
|
|
8006d1e: b283 uxth r3, r0
|
|
8006d20: 1acb subs r3, r1, r3
|
|
8006d22: 0c00 lsrs r0, r0, #16
|
|
8006d24: 4463 add r3, ip
|
|
8006d26: ebc0 401a rsb r0, r0, sl, lsr #16
|
|
8006d2a: eb00 4023 add.w r0, r0, r3, asr #16
|
|
8006d2e: b29b uxth r3, r3
|
|
8006d30: ea43 4300 orr.w r3, r3, r0, lsl #16
|
|
8006d34: 4576 cmp r6, lr
|
|
8006d36: f849 3b04 str.w r3, [r9], #4
|
|
8006d3a: ea4f 4c20 mov.w ip, r0, asr #16
|
|
8006d3e: d8e5 bhi.n 8006d0c <__mdiff+0x88>
|
|
8006d40: 1b33 subs r3, r6, r4
|
|
8006d42: 3b15 subs r3, #21
|
|
8006d44: f023 0303 bic.w r3, r3, #3
|
|
8006d48: 3415 adds r4, #21
|
|
8006d4a: 3304 adds r3, #4
|
|
8006d4c: 42a6 cmp r6, r4
|
|
8006d4e: bf38 it cc
|
|
8006d50: 2304 movcc r3, #4
|
|
8006d52: 441d add r5, r3
|
|
8006d54: 445b add r3, fp
|
|
8006d56: 461e mov r6, r3
|
|
8006d58: 462c mov r4, r5
|
|
8006d5a: 4544 cmp r4, r8
|
|
8006d5c: d30e bcc.n 8006d7c <__mdiff+0xf8>
|
|
8006d5e: f108 0103 add.w r1, r8, #3
|
|
8006d62: 1b49 subs r1, r1, r5
|
|
8006d64: f021 0103 bic.w r1, r1, #3
|
|
8006d68: 3d03 subs r5, #3
|
|
8006d6a: 45a8 cmp r8, r5
|
|
8006d6c: bf38 it cc
|
|
8006d6e: 2100 movcc r1, #0
|
|
8006d70: 440b add r3, r1
|
|
8006d72: f853 1d04 ldr.w r1, [r3, #-4]!
|
|
8006d76: b191 cbz r1, 8006d9e <__mdiff+0x11a>
|
|
8006d78: 6117 str r7, [r2, #16]
|
|
8006d7a: e79d b.n 8006cb8 <__mdiff+0x34>
|
|
8006d7c: f854 1b04 ldr.w r1, [r4], #4
|
|
8006d80: 46e6 mov lr, ip
|
|
8006d82: 0c08 lsrs r0, r1, #16
|
|
8006d84: fa1c fc81 uxtah ip, ip, r1
|
|
8006d88: 4471 add r1, lr
|
|
8006d8a: eb00 402c add.w r0, r0, ip, asr #16
|
|
8006d8e: b289 uxth r1, r1
|
|
8006d90: ea41 4100 orr.w r1, r1, r0, lsl #16
|
|
8006d94: f846 1b04 str.w r1, [r6], #4
|
|
8006d98: ea4f 4c20 mov.w ip, r0, asr #16
|
|
8006d9c: e7dd b.n 8006d5a <__mdiff+0xd6>
|
|
8006d9e: 3f01 subs r7, #1
|
|
8006da0: e7e7 b.n 8006d72 <__mdiff+0xee>
|
|
8006da2: bf00 nop
|
|
8006da4: 08007604 .word 0x08007604
|
|
8006da8: 08007615 .word 0x08007615
|
|
|
|
08006dac <__d2b>:
|
|
8006dac: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
|
|
8006db0: 460f mov r7, r1
|
|
8006db2: 2101 movs r1, #1
|
|
8006db4: ec59 8b10 vmov r8, r9, d0
|
|
8006db8: 4616 mov r6, r2
|
|
8006dba: f7ff fcd5 bl 8006768 <_Balloc>
|
|
8006dbe: 4604 mov r4, r0
|
|
8006dc0: b930 cbnz r0, 8006dd0 <__d2b+0x24>
|
|
8006dc2: 4602 mov r2, r0
|
|
8006dc4: 4b23 ldr r3, [pc, #140] @ (8006e54 <__d2b+0xa8>)
|
|
8006dc6: 4824 ldr r0, [pc, #144] @ (8006e58 <__d2b+0xac>)
|
|
8006dc8: f240 310f movw r1, #783 @ 0x30f
|
|
8006dcc: f000 fad6 bl 800737c <__assert_func>
|
|
8006dd0: f3c9 550a ubfx r5, r9, #20, #11
|
|
8006dd4: f3c9 0313 ubfx r3, r9, #0, #20
|
|
8006dd8: b10d cbz r5, 8006dde <__d2b+0x32>
|
|
8006dda: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8006dde: 9301 str r3, [sp, #4]
|
|
8006de0: f1b8 0300 subs.w r3, r8, #0
|
|
8006de4: d023 beq.n 8006e2e <__d2b+0x82>
|
|
8006de6: 4668 mov r0, sp
|
|
8006de8: 9300 str r3, [sp, #0]
|
|
8006dea: f7ff fd84 bl 80068f6 <__lo0bits>
|
|
8006dee: e9dd 1200 ldrd r1, r2, [sp]
|
|
8006df2: b1d0 cbz r0, 8006e2a <__d2b+0x7e>
|
|
8006df4: f1c0 0320 rsb r3, r0, #32
|
|
8006df8: fa02 f303 lsl.w r3, r2, r3
|
|
8006dfc: 430b orrs r3, r1
|
|
8006dfe: 40c2 lsrs r2, r0
|
|
8006e00: 6163 str r3, [r4, #20]
|
|
8006e02: 9201 str r2, [sp, #4]
|
|
8006e04: 9b01 ldr r3, [sp, #4]
|
|
8006e06: 61a3 str r3, [r4, #24]
|
|
8006e08: 2b00 cmp r3, #0
|
|
8006e0a: bf0c ite eq
|
|
8006e0c: 2201 moveq r2, #1
|
|
8006e0e: 2202 movne r2, #2
|
|
8006e10: 6122 str r2, [r4, #16]
|
|
8006e12: b1a5 cbz r5, 8006e3e <__d2b+0x92>
|
|
8006e14: f2a5 4533 subw r5, r5, #1075 @ 0x433
|
|
8006e18: 4405 add r5, r0
|
|
8006e1a: 603d str r5, [r7, #0]
|
|
8006e1c: f1c0 0035 rsb r0, r0, #53 @ 0x35
|
|
8006e20: 6030 str r0, [r6, #0]
|
|
8006e22: 4620 mov r0, r4
|
|
8006e24: b003 add sp, #12
|
|
8006e26: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
8006e2a: 6161 str r1, [r4, #20]
|
|
8006e2c: e7ea b.n 8006e04 <__d2b+0x58>
|
|
8006e2e: a801 add r0, sp, #4
|
|
8006e30: f7ff fd61 bl 80068f6 <__lo0bits>
|
|
8006e34: 9b01 ldr r3, [sp, #4]
|
|
8006e36: 6163 str r3, [r4, #20]
|
|
8006e38: 3020 adds r0, #32
|
|
8006e3a: 2201 movs r2, #1
|
|
8006e3c: e7e8 b.n 8006e10 <__d2b+0x64>
|
|
8006e3e: eb04 0382 add.w r3, r4, r2, lsl #2
|
|
8006e42: f2a0 4032 subw r0, r0, #1074 @ 0x432
|
|
8006e46: 6038 str r0, [r7, #0]
|
|
8006e48: 6918 ldr r0, [r3, #16]
|
|
8006e4a: f7ff fd35 bl 80068b8 <__hi0bits>
|
|
8006e4e: ebc0 1042 rsb r0, r0, r2, lsl #5
|
|
8006e52: e7e5 b.n 8006e20 <__d2b+0x74>
|
|
8006e54: 08007604 .word 0x08007604
|
|
8006e58: 08007615 .word 0x08007615
|
|
|
|
08006e5c <__sfputc_r>:
|
|
8006e5c: 6893 ldr r3, [r2, #8]
|
|
8006e5e: 3b01 subs r3, #1
|
|
8006e60: 2b00 cmp r3, #0
|
|
8006e62: b410 push {r4}
|
|
8006e64: 6093 str r3, [r2, #8]
|
|
8006e66: da08 bge.n 8006e7a <__sfputc_r+0x1e>
|
|
8006e68: 6994 ldr r4, [r2, #24]
|
|
8006e6a: 42a3 cmp r3, r4
|
|
8006e6c: db01 blt.n 8006e72 <__sfputc_r+0x16>
|
|
8006e6e: 290a cmp r1, #10
|
|
8006e70: d103 bne.n 8006e7a <__sfputc_r+0x1e>
|
|
8006e72: f85d 4b04 ldr.w r4, [sp], #4
|
|
8006e76: f7fe bc08 b.w 800568a <__swbuf_r>
|
|
8006e7a: 6813 ldr r3, [r2, #0]
|
|
8006e7c: 1c58 adds r0, r3, #1
|
|
8006e7e: 6010 str r0, [r2, #0]
|
|
8006e80: 7019 strb r1, [r3, #0]
|
|
8006e82: 4608 mov r0, r1
|
|
8006e84: f85d 4b04 ldr.w r4, [sp], #4
|
|
8006e88: 4770 bx lr
|
|
|
|
08006e8a <__sfputs_r>:
|
|
8006e8a: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8006e8c: 4606 mov r6, r0
|
|
8006e8e: 460f mov r7, r1
|
|
8006e90: 4614 mov r4, r2
|
|
8006e92: 18d5 adds r5, r2, r3
|
|
8006e94: 42ac cmp r4, r5
|
|
8006e96: d101 bne.n 8006e9c <__sfputs_r+0x12>
|
|
8006e98: 2000 movs r0, #0
|
|
8006e9a: e007 b.n 8006eac <__sfputs_r+0x22>
|
|
8006e9c: f814 1b01 ldrb.w r1, [r4], #1
|
|
8006ea0: 463a mov r2, r7
|
|
8006ea2: 4630 mov r0, r6
|
|
8006ea4: f7ff ffda bl 8006e5c <__sfputc_r>
|
|
8006ea8: 1c43 adds r3, r0, #1
|
|
8006eaa: d1f3 bne.n 8006e94 <__sfputs_r+0xa>
|
|
8006eac: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
...
|
|
|
|
08006eb0 <_vfiprintf_r>:
|
|
8006eb0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8006eb4: 460d mov r5, r1
|
|
8006eb6: b09d sub sp, #116 @ 0x74
|
|
8006eb8: 4614 mov r4, r2
|
|
8006eba: 4698 mov r8, r3
|
|
8006ebc: 4606 mov r6, r0
|
|
8006ebe: b118 cbz r0, 8006ec8 <_vfiprintf_r+0x18>
|
|
8006ec0: 6a03 ldr r3, [r0, #32]
|
|
8006ec2: b90b cbnz r3, 8006ec8 <_vfiprintf_r+0x18>
|
|
8006ec4: f7fe faf8 bl 80054b8 <__sinit>
|
|
8006ec8: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8006eca: 07d9 lsls r1, r3, #31
|
|
8006ecc: d405 bmi.n 8006eda <_vfiprintf_r+0x2a>
|
|
8006ece: 89ab ldrh r3, [r5, #12]
|
|
8006ed0: 059a lsls r2, r3, #22
|
|
8006ed2: d402 bmi.n 8006eda <_vfiprintf_r+0x2a>
|
|
8006ed4: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8006ed6: f7fe fcea bl 80058ae <__retarget_lock_acquire_recursive>
|
|
8006eda: 89ab ldrh r3, [r5, #12]
|
|
8006edc: 071b lsls r3, r3, #28
|
|
8006ede: d501 bpl.n 8006ee4 <_vfiprintf_r+0x34>
|
|
8006ee0: 692b ldr r3, [r5, #16]
|
|
8006ee2: b99b cbnz r3, 8006f0c <_vfiprintf_r+0x5c>
|
|
8006ee4: 4629 mov r1, r5
|
|
8006ee6: 4630 mov r0, r6
|
|
8006ee8: f7fe fc0e bl 8005708 <__swsetup_r>
|
|
8006eec: b170 cbz r0, 8006f0c <_vfiprintf_r+0x5c>
|
|
8006eee: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8006ef0: 07dc lsls r4, r3, #31
|
|
8006ef2: d504 bpl.n 8006efe <_vfiprintf_r+0x4e>
|
|
8006ef4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8006ef8: b01d add sp, #116 @ 0x74
|
|
8006efa: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8006efe: 89ab ldrh r3, [r5, #12]
|
|
8006f00: 0598 lsls r0, r3, #22
|
|
8006f02: d4f7 bmi.n 8006ef4 <_vfiprintf_r+0x44>
|
|
8006f04: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8006f06: f7fe fcd3 bl 80058b0 <__retarget_lock_release_recursive>
|
|
8006f0a: e7f3 b.n 8006ef4 <_vfiprintf_r+0x44>
|
|
8006f0c: 2300 movs r3, #0
|
|
8006f0e: 9309 str r3, [sp, #36] @ 0x24
|
|
8006f10: 2320 movs r3, #32
|
|
8006f12: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
8006f16: f8cd 800c str.w r8, [sp, #12]
|
|
8006f1a: 2330 movs r3, #48 @ 0x30
|
|
8006f1c: f8df 81ac ldr.w r8, [pc, #428] @ 80070cc <_vfiprintf_r+0x21c>
|
|
8006f20: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
8006f24: f04f 0901 mov.w r9, #1
|
|
8006f28: 4623 mov r3, r4
|
|
8006f2a: 469a mov sl, r3
|
|
8006f2c: f813 2b01 ldrb.w r2, [r3], #1
|
|
8006f30: b10a cbz r2, 8006f36 <_vfiprintf_r+0x86>
|
|
8006f32: 2a25 cmp r2, #37 @ 0x25
|
|
8006f34: d1f9 bne.n 8006f2a <_vfiprintf_r+0x7a>
|
|
8006f36: ebba 0b04 subs.w fp, sl, r4
|
|
8006f3a: d00b beq.n 8006f54 <_vfiprintf_r+0xa4>
|
|
8006f3c: 465b mov r3, fp
|
|
8006f3e: 4622 mov r2, r4
|
|
8006f40: 4629 mov r1, r5
|
|
8006f42: 4630 mov r0, r6
|
|
8006f44: f7ff ffa1 bl 8006e8a <__sfputs_r>
|
|
8006f48: 3001 adds r0, #1
|
|
8006f4a: f000 80a7 beq.w 800709c <_vfiprintf_r+0x1ec>
|
|
8006f4e: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8006f50: 445a add r2, fp
|
|
8006f52: 9209 str r2, [sp, #36] @ 0x24
|
|
8006f54: f89a 3000 ldrb.w r3, [sl]
|
|
8006f58: 2b00 cmp r3, #0
|
|
8006f5a: f000 809f beq.w 800709c <_vfiprintf_r+0x1ec>
|
|
8006f5e: 2300 movs r3, #0
|
|
8006f60: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8006f64: e9cd 2305 strd r2, r3, [sp, #20]
|
|
8006f68: f10a 0a01 add.w sl, sl, #1
|
|
8006f6c: 9304 str r3, [sp, #16]
|
|
8006f6e: 9307 str r3, [sp, #28]
|
|
8006f70: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
8006f74: 931a str r3, [sp, #104] @ 0x68
|
|
8006f76: 4654 mov r4, sl
|
|
8006f78: 2205 movs r2, #5
|
|
8006f7a: f814 1b01 ldrb.w r1, [r4], #1
|
|
8006f7e: 4853 ldr r0, [pc, #332] @ (80070cc <_vfiprintf_r+0x21c>)
|
|
8006f80: f7f9 f926 bl 80001d0 <memchr>
|
|
8006f84: 9a04 ldr r2, [sp, #16]
|
|
8006f86: b9d8 cbnz r0, 8006fc0 <_vfiprintf_r+0x110>
|
|
8006f88: 06d1 lsls r1, r2, #27
|
|
8006f8a: bf44 itt mi
|
|
8006f8c: 2320 movmi r3, #32
|
|
8006f8e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8006f92: 0713 lsls r3, r2, #28
|
|
8006f94: bf44 itt mi
|
|
8006f96: 232b movmi r3, #43 @ 0x2b
|
|
8006f98: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8006f9c: f89a 3000 ldrb.w r3, [sl]
|
|
8006fa0: 2b2a cmp r3, #42 @ 0x2a
|
|
8006fa2: d015 beq.n 8006fd0 <_vfiprintf_r+0x120>
|
|
8006fa4: 9a07 ldr r2, [sp, #28]
|
|
8006fa6: 4654 mov r4, sl
|
|
8006fa8: 2000 movs r0, #0
|
|
8006faa: f04f 0c0a mov.w ip, #10
|
|
8006fae: 4621 mov r1, r4
|
|
8006fb0: f811 3b01 ldrb.w r3, [r1], #1
|
|
8006fb4: 3b30 subs r3, #48 @ 0x30
|
|
8006fb6: 2b09 cmp r3, #9
|
|
8006fb8: d94b bls.n 8007052 <_vfiprintf_r+0x1a2>
|
|
8006fba: b1b0 cbz r0, 8006fea <_vfiprintf_r+0x13a>
|
|
8006fbc: 9207 str r2, [sp, #28]
|
|
8006fbe: e014 b.n 8006fea <_vfiprintf_r+0x13a>
|
|
8006fc0: eba0 0308 sub.w r3, r0, r8
|
|
8006fc4: fa09 f303 lsl.w r3, r9, r3
|
|
8006fc8: 4313 orrs r3, r2
|
|
8006fca: 9304 str r3, [sp, #16]
|
|
8006fcc: 46a2 mov sl, r4
|
|
8006fce: e7d2 b.n 8006f76 <_vfiprintf_r+0xc6>
|
|
8006fd0: 9b03 ldr r3, [sp, #12]
|
|
8006fd2: 1d19 adds r1, r3, #4
|
|
8006fd4: 681b ldr r3, [r3, #0]
|
|
8006fd6: 9103 str r1, [sp, #12]
|
|
8006fd8: 2b00 cmp r3, #0
|
|
8006fda: bfbb ittet lt
|
|
8006fdc: 425b neglt r3, r3
|
|
8006fde: f042 0202 orrlt.w r2, r2, #2
|
|
8006fe2: 9307 strge r3, [sp, #28]
|
|
8006fe4: 9307 strlt r3, [sp, #28]
|
|
8006fe6: bfb8 it lt
|
|
8006fe8: 9204 strlt r2, [sp, #16]
|
|
8006fea: 7823 ldrb r3, [r4, #0]
|
|
8006fec: 2b2e cmp r3, #46 @ 0x2e
|
|
8006fee: d10a bne.n 8007006 <_vfiprintf_r+0x156>
|
|
8006ff0: 7863 ldrb r3, [r4, #1]
|
|
8006ff2: 2b2a cmp r3, #42 @ 0x2a
|
|
8006ff4: d132 bne.n 800705c <_vfiprintf_r+0x1ac>
|
|
8006ff6: 9b03 ldr r3, [sp, #12]
|
|
8006ff8: 1d1a adds r2, r3, #4
|
|
8006ffa: 681b ldr r3, [r3, #0]
|
|
8006ffc: 9203 str r2, [sp, #12]
|
|
8006ffe: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
8007002: 3402 adds r4, #2
|
|
8007004: 9305 str r3, [sp, #20]
|
|
8007006: f8df a0d4 ldr.w sl, [pc, #212] @ 80070dc <_vfiprintf_r+0x22c>
|
|
800700a: 7821 ldrb r1, [r4, #0]
|
|
800700c: 2203 movs r2, #3
|
|
800700e: 4650 mov r0, sl
|
|
8007010: f7f9 f8de bl 80001d0 <memchr>
|
|
8007014: b138 cbz r0, 8007026 <_vfiprintf_r+0x176>
|
|
8007016: 9b04 ldr r3, [sp, #16]
|
|
8007018: eba0 000a sub.w r0, r0, sl
|
|
800701c: 2240 movs r2, #64 @ 0x40
|
|
800701e: 4082 lsls r2, r0
|
|
8007020: 4313 orrs r3, r2
|
|
8007022: 3401 adds r4, #1
|
|
8007024: 9304 str r3, [sp, #16]
|
|
8007026: f814 1b01 ldrb.w r1, [r4], #1
|
|
800702a: 4829 ldr r0, [pc, #164] @ (80070d0 <_vfiprintf_r+0x220>)
|
|
800702c: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
8007030: 2206 movs r2, #6
|
|
8007032: f7f9 f8cd bl 80001d0 <memchr>
|
|
8007036: 2800 cmp r0, #0
|
|
8007038: d03f beq.n 80070ba <_vfiprintf_r+0x20a>
|
|
800703a: 4b26 ldr r3, [pc, #152] @ (80070d4 <_vfiprintf_r+0x224>)
|
|
800703c: bb1b cbnz r3, 8007086 <_vfiprintf_r+0x1d6>
|
|
800703e: 9b03 ldr r3, [sp, #12]
|
|
8007040: 3307 adds r3, #7
|
|
8007042: f023 0307 bic.w r3, r3, #7
|
|
8007046: 3308 adds r3, #8
|
|
8007048: 9303 str r3, [sp, #12]
|
|
800704a: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
800704c: 443b add r3, r7
|
|
800704e: 9309 str r3, [sp, #36] @ 0x24
|
|
8007050: e76a b.n 8006f28 <_vfiprintf_r+0x78>
|
|
8007052: fb0c 3202 mla r2, ip, r2, r3
|
|
8007056: 460c mov r4, r1
|
|
8007058: 2001 movs r0, #1
|
|
800705a: e7a8 b.n 8006fae <_vfiprintf_r+0xfe>
|
|
800705c: 2300 movs r3, #0
|
|
800705e: 3401 adds r4, #1
|
|
8007060: 9305 str r3, [sp, #20]
|
|
8007062: 4619 mov r1, r3
|
|
8007064: f04f 0c0a mov.w ip, #10
|
|
8007068: 4620 mov r0, r4
|
|
800706a: f810 2b01 ldrb.w r2, [r0], #1
|
|
800706e: 3a30 subs r2, #48 @ 0x30
|
|
8007070: 2a09 cmp r2, #9
|
|
8007072: d903 bls.n 800707c <_vfiprintf_r+0x1cc>
|
|
8007074: 2b00 cmp r3, #0
|
|
8007076: d0c6 beq.n 8007006 <_vfiprintf_r+0x156>
|
|
8007078: 9105 str r1, [sp, #20]
|
|
800707a: e7c4 b.n 8007006 <_vfiprintf_r+0x156>
|
|
800707c: fb0c 2101 mla r1, ip, r1, r2
|
|
8007080: 4604 mov r4, r0
|
|
8007082: 2301 movs r3, #1
|
|
8007084: e7f0 b.n 8007068 <_vfiprintf_r+0x1b8>
|
|
8007086: ab03 add r3, sp, #12
|
|
8007088: 9300 str r3, [sp, #0]
|
|
800708a: 462a mov r2, r5
|
|
800708c: 4b12 ldr r3, [pc, #72] @ (80070d8 <_vfiprintf_r+0x228>)
|
|
800708e: a904 add r1, sp, #16
|
|
8007090: 4630 mov r0, r6
|
|
8007092: f7fd fdcf bl 8004c34 <_printf_float>
|
|
8007096: 4607 mov r7, r0
|
|
8007098: 1c78 adds r0, r7, #1
|
|
800709a: d1d6 bne.n 800704a <_vfiprintf_r+0x19a>
|
|
800709c: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
800709e: 07d9 lsls r1, r3, #31
|
|
80070a0: d405 bmi.n 80070ae <_vfiprintf_r+0x1fe>
|
|
80070a2: 89ab ldrh r3, [r5, #12]
|
|
80070a4: 059a lsls r2, r3, #22
|
|
80070a6: d402 bmi.n 80070ae <_vfiprintf_r+0x1fe>
|
|
80070a8: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
80070aa: f7fe fc01 bl 80058b0 <__retarget_lock_release_recursive>
|
|
80070ae: 89ab ldrh r3, [r5, #12]
|
|
80070b0: 065b lsls r3, r3, #25
|
|
80070b2: f53f af1f bmi.w 8006ef4 <_vfiprintf_r+0x44>
|
|
80070b6: 9809 ldr r0, [sp, #36] @ 0x24
|
|
80070b8: e71e b.n 8006ef8 <_vfiprintf_r+0x48>
|
|
80070ba: ab03 add r3, sp, #12
|
|
80070bc: 9300 str r3, [sp, #0]
|
|
80070be: 462a mov r2, r5
|
|
80070c0: 4b05 ldr r3, [pc, #20] @ (80070d8 <_vfiprintf_r+0x228>)
|
|
80070c2: a904 add r1, sp, #16
|
|
80070c4: 4630 mov r0, r6
|
|
80070c6: f7fe f84d bl 8005164 <_printf_i>
|
|
80070ca: e7e4 b.n 8007096 <_vfiprintf_r+0x1e6>
|
|
80070cc: 0800766e .word 0x0800766e
|
|
80070d0: 08007678 .word 0x08007678
|
|
80070d4: 08004c35 .word 0x08004c35
|
|
80070d8: 08006e8b .word 0x08006e8b
|
|
80070dc: 08007674 .word 0x08007674
|
|
|
|
080070e0 <__sflush_r>:
|
|
80070e0: f9b1 200c ldrsh.w r2, [r1, #12]
|
|
80070e4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
80070e8: 0716 lsls r6, r2, #28
|
|
80070ea: 4605 mov r5, r0
|
|
80070ec: 460c mov r4, r1
|
|
80070ee: d454 bmi.n 800719a <__sflush_r+0xba>
|
|
80070f0: 684b ldr r3, [r1, #4]
|
|
80070f2: 2b00 cmp r3, #0
|
|
80070f4: dc02 bgt.n 80070fc <__sflush_r+0x1c>
|
|
80070f6: 6c0b ldr r3, [r1, #64] @ 0x40
|
|
80070f8: 2b00 cmp r3, #0
|
|
80070fa: dd48 ble.n 800718e <__sflush_r+0xae>
|
|
80070fc: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
80070fe: 2e00 cmp r6, #0
|
|
8007100: d045 beq.n 800718e <__sflush_r+0xae>
|
|
8007102: 2300 movs r3, #0
|
|
8007104: f412 5280 ands.w r2, r2, #4096 @ 0x1000
|
|
8007108: 682f ldr r7, [r5, #0]
|
|
800710a: 6a21 ldr r1, [r4, #32]
|
|
800710c: 602b str r3, [r5, #0]
|
|
800710e: d030 beq.n 8007172 <__sflush_r+0x92>
|
|
8007110: 6d62 ldr r2, [r4, #84] @ 0x54
|
|
8007112: 89a3 ldrh r3, [r4, #12]
|
|
8007114: 0759 lsls r1, r3, #29
|
|
8007116: d505 bpl.n 8007124 <__sflush_r+0x44>
|
|
8007118: 6863 ldr r3, [r4, #4]
|
|
800711a: 1ad2 subs r2, r2, r3
|
|
800711c: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
800711e: b10b cbz r3, 8007124 <__sflush_r+0x44>
|
|
8007120: 6c23 ldr r3, [r4, #64] @ 0x40
|
|
8007122: 1ad2 subs r2, r2, r3
|
|
8007124: 2300 movs r3, #0
|
|
8007126: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
8007128: 6a21 ldr r1, [r4, #32]
|
|
800712a: 4628 mov r0, r5
|
|
800712c: 47b0 blx r6
|
|
800712e: 1c43 adds r3, r0, #1
|
|
8007130: 89a3 ldrh r3, [r4, #12]
|
|
8007132: d106 bne.n 8007142 <__sflush_r+0x62>
|
|
8007134: 6829 ldr r1, [r5, #0]
|
|
8007136: 291d cmp r1, #29
|
|
8007138: d82b bhi.n 8007192 <__sflush_r+0xb2>
|
|
800713a: 4a2a ldr r2, [pc, #168] @ (80071e4 <__sflush_r+0x104>)
|
|
800713c: 40ca lsrs r2, r1
|
|
800713e: 07d6 lsls r6, r2, #31
|
|
8007140: d527 bpl.n 8007192 <__sflush_r+0xb2>
|
|
8007142: 2200 movs r2, #0
|
|
8007144: 6062 str r2, [r4, #4]
|
|
8007146: 04d9 lsls r1, r3, #19
|
|
8007148: 6922 ldr r2, [r4, #16]
|
|
800714a: 6022 str r2, [r4, #0]
|
|
800714c: d504 bpl.n 8007158 <__sflush_r+0x78>
|
|
800714e: 1c42 adds r2, r0, #1
|
|
8007150: d101 bne.n 8007156 <__sflush_r+0x76>
|
|
8007152: 682b ldr r3, [r5, #0]
|
|
8007154: b903 cbnz r3, 8007158 <__sflush_r+0x78>
|
|
8007156: 6560 str r0, [r4, #84] @ 0x54
|
|
8007158: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
800715a: 602f str r7, [r5, #0]
|
|
800715c: b1b9 cbz r1, 800718e <__sflush_r+0xae>
|
|
800715e: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
8007162: 4299 cmp r1, r3
|
|
8007164: d002 beq.n 800716c <__sflush_r+0x8c>
|
|
8007166: 4628 mov r0, r5
|
|
8007168: f7ff f9fe bl 8006568 <_free_r>
|
|
800716c: 2300 movs r3, #0
|
|
800716e: 6363 str r3, [r4, #52] @ 0x34
|
|
8007170: e00d b.n 800718e <__sflush_r+0xae>
|
|
8007172: 2301 movs r3, #1
|
|
8007174: 4628 mov r0, r5
|
|
8007176: 47b0 blx r6
|
|
8007178: 4602 mov r2, r0
|
|
800717a: 1c50 adds r0, r2, #1
|
|
800717c: d1c9 bne.n 8007112 <__sflush_r+0x32>
|
|
800717e: 682b ldr r3, [r5, #0]
|
|
8007180: 2b00 cmp r3, #0
|
|
8007182: d0c6 beq.n 8007112 <__sflush_r+0x32>
|
|
8007184: 2b1d cmp r3, #29
|
|
8007186: d001 beq.n 800718c <__sflush_r+0xac>
|
|
8007188: 2b16 cmp r3, #22
|
|
800718a: d11e bne.n 80071ca <__sflush_r+0xea>
|
|
800718c: 602f str r7, [r5, #0]
|
|
800718e: 2000 movs r0, #0
|
|
8007190: e022 b.n 80071d8 <__sflush_r+0xf8>
|
|
8007192: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8007196: b21b sxth r3, r3
|
|
8007198: e01b b.n 80071d2 <__sflush_r+0xf2>
|
|
800719a: 690f ldr r7, [r1, #16]
|
|
800719c: 2f00 cmp r7, #0
|
|
800719e: d0f6 beq.n 800718e <__sflush_r+0xae>
|
|
80071a0: 0793 lsls r3, r2, #30
|
|
80071a2: 680e ldr r6, [r1, #0]
|
|
80071a4: bf08 it eq
|
|
80071a6: 694b ldreq r3, [r1, #20]
|
|
80071a8: 600f str r7, [r1, #0]
|
|
80071aa: bf18 it ne
|
|
80071ac: 2300 movne r3, #0
|
|
80071ae: eba6 0807 sub.w r8, r6, r7
|
|
80071b2: 608b str r3, [r1, #8]
|
|
80071b4: f1b8 0f00 cmp.w r8, #0
|
|
80071b8: dde9 ble.n 800718e <__sflush_r+0xae>
|
|
80071ba: 6a21 ldr r1, [r4, #32]
|
|
80071bc: 6aa6 ldr r6, [r4, #40] @ 0x28
|
|
80071be: 4643 mov r3, r8
|
|
80071c0: 463a mov r2, r7
|
|
80071c2: 4628 mov r0, r5
|
|
80071c4: 47b0 blx r6
|
|
80071c6: 2800 cmp r0, #0
|
|
80071c8: dc08 bgt.n 80071dc <__sflush_r+0xfc>
|
|
80071ca: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
80071ce: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
80071d2: 81a3 strh r3, [r4, #12]
|
|
80071d4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80071d8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
80071dc: 4407 add r7, r0
|
|
80071de: eba8 0800 sub.w r8, r8, r0
|
|
80071e2: e7e7 b.n 80071b4 <__sflush_r+0xd4>
|
|
80071e4: 20400001 .word 0x20400001
|
|
|
|
080071e8 <_fflush_r>:
|
|
80071e8: b538 push {r3, r4, r5, lr}
|
|
80071ea: 690b ldr r3, [r1, #16]
|
|
80071ec: 4605 mov r5, r0
|
|
80071ee: 460c mov r4, r1
|
|
80071f0: b913 cbnz r3, 80071f8 <_fflush_r+0x10>
|
|
80071f2: 2500 movs r5, #0
|
|
80071f4: 4628 mov r0, r5
|
|
80071f6: bd38 pop {r3, r4, r5, pc}
|
|
80071f8: b118 cbz r0, 8007202 <_fflush_r+0x1a>
|
|
80071fa: 6a03 ldr r3, [r0, #32]
|
|
80071fc: b90b cbnz r3, 8007202 <_fflush_r+0x1a>
|
|
80071fe: f7fe f95b bl 80054b8 <__sinit>
|
|
8007202: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8007206: 2b00 cmp r3, #0
|
|
8007208: d0f3 beq.n 80071f2 <_fflush_r+0xa>
|
|
800720a: 6e62 ldr r2, [r4, #100] @ 0x64
|
|
800720c: 07d0 lsls r0, r2, #31
|
|
800720e: d404 bmi.n 800721a <_fflush_r+0x32>
|
|
8007210: 0599 lsls r1, r3, #22
|
|
8007212: d402 bmi.n 800721a <_fflush_r+0x32>
|
|
8007214: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8007216: f7fe fb4a bl 80058ae <__retarget_lock_acquire_recursive>
|
|
800721a: 4628 mov r0, r5
|
|
800721c: 4621 mov r1, r4
|
|
800721e: f7ff ff5f bl 80070e0 <__sflush_r>
|
|
8007222: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
8007224: 07da lsls r2, r3, #31
|
|
8007226: 4605 mov r5, r0
|
|
8007228: d4e4 bmi.n 80071f4 <_fflush_r+0xc>
|
|
800722a: 89a3 ldrh r3, [r4, #12]
|
|
800722c: 059b lsls r3, r3, #22
|
|
800722e: d4e1 bmi.n 80071f4 <_fflush_r+0xc>
|
|
8007230: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8007232: f7fe fb3d bl 80058b0 <__retarget_lock_release_recursive>
|
|
8007236: e7dd b.n 80071f4 <_fflush_r+0xc>
|
|
|
|
08007238 <__swhatbuf_r>:
|
|
8007238: b570 push {r4, r5, r6, lr}
|
|
800723a: 460c mov r4, r1
|
|
800723c: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
8007240: 2900 cmp r1, #0
|
|
8007242: b096 sub sp, #88 @ 0x58
|
|
8007244: 4615 mov r5, r2
|
|
8007246: 461e mov r6, r3
|
|
8007248: da0d bge.n 8007266 <__swhatbuf_r+0x2e>
|
|
800724a: 89a3 ldrh r3, [r4, #12]
|
|
800724c: f013 0f80 tst.w r3, #128 @ 0x80
|
|
8007250: f04f 0100 mov.w r1, #0
|
|
8007254: bf14 ite ne
|
|
8007256: 2340 movne r3, #64 @ 0x40
|
|
8007258: f44f 6380 moveq.w r3, #1024 @ 0x400
|
|
800725c: 2000 movs r0, #0
|
|
800725e: 6031 str r1, [r6, #0]
|
|
8007260: 602b str r3, [r5, #0]
|
|
8007262: b016 add sp, #88 @ 0x58
|
|
8007264: bd70 pop {r4, r5, r6, pc}
|
|
8007266: 466a mov r2, sp
|
|
8007268: f000 f848 bl 80072fc <_fstat_r>
|
|
800726c: 2800 cmp r0, #0
|
|
800726e: dbec blt.n 800724a <__swhatbuf_r+0x12>
|
|
8007270: 9901 ldr r1, [sp, #4]
|
|
8007272: f401 4170 and.w r1, r1, #61440 @ 0xf000
|
|
8007276: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
|
|
800727a: 4259 negs r1, r3
|
|
800727c: 4159 adcs r1, r3
|
|
800727e: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8007282: e7eb b.n 800725c <__swhatbuf_r+0x24>
|
|
|
|
08007284 <__smakebuf_r>:
|
|
8007284: 898b ldrh r3, [r1, #12]
|
|
8007286: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
8007288: 079d lsls r5, r3, #30
|
|
800728a: 4606 mov r6, r0
|
|
800728c: 460c mov r4, r1
|
|
800728e: d507 bpl.n 80072a0 <__smakebuf_r+0x1c>
|
|
8007290: f104 0347 add.w r3, r4, #71 @ 0x47
|
|
8007294: 6023 str r3, [r4, #0]
|
|
8007296: 6123 str r3, [r4, #16]
|
|
8007298: 2301 movs r3, #1
|
|
800729a: 6163 str r3, [r4, #20]
|
|
800729c: b003 add sp, #12
|
|
800729e: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80072a0: ab01 add r3, sp, #4
|
|
80072a2: 466a mov r2, sp
|
|
80072a4: f7ff ffc8 bl 8007238 <__swhatbuf_r>
|
|
80072a8: 9f00 ldr r7, [sp, #0]
|
|
80072aa: 4605 mov r5, r0
|
|
80072ac: 4639 mov r1, r7
|
|
80072ae: 4630 mov r0, r6
|
|
80072b0: f7ff f9ce bl 8006650 <_malloc_r>
|
|
80072b4: b948 cbnz r0, 80072ca <__smakebuf_r+0x46>
|
|
80072b6: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
80072ba: 059a lsls r2, r3, #22
|
|
80072bc: d4ee bmi.n 800729c <__smakebuf_r+0x18>
|
|
80072be: f023 0303 bic.w r3, r3, #3
|
|
80072c2: f043 0302 orr.w r3, r3, #2
|
|
80072c6: 81a3 strh r3, [r4, #12]
|
|
80072c8: e7e2 b.n 8007290 <__smakebuf_r+0xc>
|
|
80072ca: 89a3 ldrh r3, [r4, #12]
|
|
80072cc: 6020 str r0, [r4, #0]
|
|
80072ce: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80072d2: 81a3 strh r3, [r4, #12]
|
|
80072d4: 9b01 ldr r3, [sp, #4]
|
|
80072d6: e9c4 0704 strd r0, r7, [r4, #16]
|
|
80072da: b15b cbz r3, 80072f4 <__smakebuf_r+0x70>
|
|
80072dc: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
80072e0: 4630 mov r0, r6
|
|
80072e2: f000 f81d bl 8007320 <_isatty_r>
|
|
80072e6: b128 cbz r0, 80072f4 <__smakebuf_r+0x70>
|
|
80072e8: 89a3 ldrh r3, [r4, #12]
|
|
80072ea: f023 0303 bic.w r3, r3, #3
|
|
80072ee: f043 0301 orr.w r3, r3, #1
|
|
80072f2: 81a3 strh r3, [r4, #12]
|
|
80072f4: 89a3 ldrh r3, [r4, #12]
|
|
80072f6: 431d orrs r5, r3
|
|
80072f8: 81a5 strh r5, [r4, #12]
|
|
80072fa: e7cf b.n 800729c <__smakebuf_r+0x18>
|
|
|
|
080072fc <_fstat_r>:
|
|
80072fc: b538 push {r3, r4, r5, lr}
|
|
80072fe: 4d07 ldr r5, [pc, #28] @ (800731c <_fstat_r+0x20>)
|
|
8007300: 2300 movs r3, #0
|
|
8007302: 4604 mov r4, r0
|
|
8007304: 4608 mov r0, r1
|
|
8007306: 4611 mov r1, r2
|
|
8007308: 602b str r3, [r5, #0]
|
|
800730a: f7fa f94e bl 80015aa <_fstat>
|
|
800730e: 1c43 adds r3, r0, #1
|
|
8007310: d102 bne.n 8007318 <_fstat_r+0x1c>
|
|
8007312: 682b ldr r3, [r5, #0]
|
|
8007314: b103 cbz r3, 8007318 <_fstat_r+0x1c>
|
|
8007316: 6023 str r3, [r4, #0]
|
|
8007318: bd38 pop {r3, r4, r5, pc}
|
|
800731a: bf00 nop
|
|
800731c: 20000410 .word 0x20000410
|
|
|
|
08007320 <_isatty_r>:
|
|
8007320: b538 push {r3, r4, r5, lr}
|
|
8007322: 4d06 ldr r5, [pc, #24] @ (800733c <_isatty_r+0x1c>)
|
|
8007324: 2300 movs r3, #0
|
|
8007326: 4604 mov r4, r0
|
|
8007328: 4608 mov r0, r1
|
|
800732a: 602b str r3, [r5, #0]
|
|
800732c: f7fa f94d bl 80015ca <_isatty>
|
|
8007330: 1c43 adds r3, r0, #1
|
|
8007332: d102 bne.n 800733a <_isatty_r+0x1a>
|
|
8007334: 682b ldr r3, [r5, #0]
|
|
8007336: b103 cbz r3, 800733a <_isatty_r+0x1a>
|
|
8007338: 6023 str r3, [r4, #0]
|
|
800733a: bd38 pop {r3, r4, r5, pc}
|
|
800733c: 20000410 .word 0x20000410
|
|
|
|
08007340 <_sbrk_r>:
|
|
8007340: b538 push {r3, r4, r5, lr}
|
|
8007342: 4d06 ldr r5, [pc, #24] @ (800735c <_sbrk_r+0x1c>)
|
|
8007344: 2300 movs r3, #0
|
|
8007346: 4604 mov r4, r0
|
|
8007348: 4608 mov r0, r1
|
|
800734a: 602b str r3, [r5, #0]
|
|
800734c: f7fa f956 bl 80015fc <_sbrk>
|
|
8007350: 1c43 adds r3, r0, #1
|
|
8007352: d102 bne.n 800735a <_sbrk_r+0x1a>
|
|
8007354: 682b ldr r3, [r5, #0]
|
|
8007356: b103 cbz r3, 800735a <_sbrk_r+0x1a>
|
|
8007358: 6023 str r3, [r4, #0]
|
|
800735a: bd38 pop {r3, r4, r5, pc}
|
|
800735c: 20000410 .word 0x20000410
|
|
|
|
08007360 <memcpy>:
|
|
8007360: 440a add r2, r1
|
|
8007362: 4291 cmp r1, r2
|
|
8007364: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
8007368: d100 bne.n 800736c <memcpy+0xc>
|
|
800736a: 4770 bx lr
|
|
800736c: b510 push {r4, lr}
|
|
800736e: f811 4b01 ldrb.w r4, [r1], #1
|
|
8007372: f803 4f01 strb.w r4, [r3, #1]!
|
|
8007376: 4291 cmp r1, r2
|
|
8007378: d1f9 bne.n 800736e <memcpy+0xe>
|
|
800737a: bd10 pop {r4, pc}
|
|
|
|
0800737c <__assert_func>:
|
|
800737c: b51f push {r0, r1, r2, r3, r4, lr}
|
|
800737e: 4614 mov r4, r2
|
|
8007380: 461a mov r2, r3
|
|
8007382: 4b09 ldr r3, [pc, #36] @ (80073a8 <__assert_func+0x2c>)
|
|
8007384: 681b ldr r3, [r3, #0]
|
|
8007386: 4605 mov r5, r0
|
|
8007388: 68d8 ldr r0, [r3, #12]
|
|
800738a: b14c cbz r4, 80073a0 <__assert_func+0x24>
|
|
800738c: 4b07 ldr r3, [pc, #28] @ (80073ac <__assert_func+0x30>)
|
|
800738e: 9100 str r1, [sp, #0]
|
|
8007390: e9cd 3401 strd r3, r4, [sp, #4]
|
|
8007394: 4906 ldr r1, [pc, #24] @ (80073b0 <__assert_func+0x34>)
|
|
8007396: 462b mov r3, r5
|
|
8007398: f000 f842 bl 8007420 <fiprintf>
|
|
800739c: f000 f852 bl 8007444 <abort>
|
|
80073a0: 4b04 ldr r3, [pc, #16] @ (80073b4 <__assert_func+0x38>)
|
|
80073a2: 461c mov r4, r3
|
|
80073a4: e7f3 b.n 800738e <__assert_func+0x12>
|
|
80073a6: bf00 nop
|
|
80073a8: 20000018 .word 0x20000018
|
|
80073ac: 08007689 .word 0x08007689
|
|
80073b0: 08007696 .word 0x08007696
|
|
80073b4: 080076c4 .word 0x080076c4
|
|
|
|
080073b8 <_calloc_r>:
|
|
80073b8: b570 push {r4, r5, r6, lr}
|
|
80073ba: fba1 5402 umull r5, r4, r1, r2
|
|
80073be: b934 cbnz r4, 80073ce <_calloc_r+0x16>
|
|
80073c0: 4629 mov r1, r5
|
|
80073c2: f7ff f945 bl 8006650 <_malloc_r>
|
|
80073c6: 4606 mov r6, r0
|
|
80073c8: b928 cbnz r0, 80073d6 <_calloc_r+0x1e>
|
|
80073ca: 4630 mov r0, r6
|
|
80073cc: bd70 pop {r4, r5, r6, pc}
|
|
80073ce: 220c movs r2, #12
|
|
80073d0: 6002 str r2, [r0, #0]
|
|
80073d2: 2600 movs r6, #0
|
|
80073d4: e7f9 b.n 80073ca <_calloc_r+0x12>
|
|
80073d6: 462a mov r2, r5
|
|
80073d8: 4621 mov r1, r4
|
|
80073da: f7fe f9eb bl 80057b4 <memset>
|
|
80073de: e7f4 b.n 80073ca <_calloc_r+0x12>
|
|
|
|
080073e0 <__ascii_mbtowc>:
|
|
80073e0: b082 sub sp, #8
|
|
80073e2: b901 cbnz r1, 80073e6 <__ascii_mbtowc+0x6>
|
|
80073e4: a901 add r1, sp, #4
|
|
80073e6: b142 cbz r2, 80073fa <__ascii_mbtowc+0x1a>
|
|
80073e8: b14b cbz r3, 80073fe <__ascii_mbtowc+0x1e>
|
|
80073ea: 7813 ldrb r3, [r2, #0]
|
|
80073ec: 600b str r3, [r1, #0]
|
|
80073ee: 7812 ldrb r2, [r2, #0]
|
|
80073f0: 1e10 subs r0, r2, #0
|
|
80073f2: bf18 it ne
|
|
80073f4: 2001 movne r0, #1
|
|
80073f6: b002 add sp, #8
|
|
80073f8: 4770 bx lr
|
|
80073fa: 4610 mov r0, r2
|
|
80073fc: e7fb b.n 80073f6 <__ascii_mbtowc+0x16>
|
|
80073fe: f06f 0001 mvn.w r0, #1
|
|
8007402: e7f8 b.n 80073f6 <__ascii_mbtowc+0x16>
|
|
|
|
08007404 <__ascii_wctomb>:
|
|
8007404: 4603 mov r3, r0
|
|
8007406: 4608 mov r0, r1
|
|
8007408: b141 cbz r1, 800741c <__ascii_wctomb+0x18>
|
|
800740a: 2aff cmp r2, #255 @ 0xff
|
|
800740c: d904 bls.n 8007418 <__ascii_wctomb+0x14>
|
|
800740e: 228a movs r2, #138 @ 0x8a
|
|
8007410: 601a str r2, [r3, #0]
|
|
8007412: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8007416: 4770 bx lr
|
|
8007418: 700a strb r2, [r1, #0]
|
|
800741a: 2001 movs r0, #1
|
|
800741c: 4770 bx lr
|
|
...
|
|
|
|
08007420 <fiprintf>:
|
|
8007420: b40e push {r1, r2, r3}
|
|
8007422: b503 push {r0, r1, lr}
|
|
8007424: 4601 mov r1, r0
|
|
8007426: ab03 add r3, sp, #12
|
|
8007428: 4805 ldr r0, [pc, #20] @ (8007440 <fiprintf+0x20>)
|
|
800742a: f853 2b04 ldr.w r2, [r3], #4
|
|
800742e: 6800 ldr r0, [r0, #0]
|
|
8007430: 9301 str r3, [sp, #4]
|
|
8007432: f7ff fd3d bl 8006eb0 <_vfiprintf_r>
|
|
8007436: b002 add sp, #8
|
|
8007438: f85d eb04 ldr.w lr, [sp], #4
|
|
800743c: b003 add sp, #12
|
|
800743e: 4770 bx lr
|
|
8007440: 20000018 .word 0x20000018
|
|
|
|
08007444 <abort>:
|
|
8007444: b508 push {r3, lr}
|
|
8007446: 2006 movs r0, #6
|
|
8007448: f000 f82c bl 80074a4 <raise>
|
|
800744c: 2001 movs r0, #1
|
|
800744e: f7fa f85c bl 800150a <_exit>
|
|
|
|
08007452 <_raise_r>:
|
|
8007452: 291f cmp r1, #31
|
|
8007454: b538 push {r3, r4, r5, lr}
|
|
8007456: 4605 mov r5, r0
|
|
8007458: 460c mov r4, r1
|
|
800745a: d904 bls.n 8007466 <_raise_r+0x14>
|
|
800745c: 2316 movs r3, #22
|
|
800745e: 6003 str r3, [r0, #0]
|
|
8007460: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8007464: bd38 pop {r3, r4, r5, pc}
|
|
8007466: 6bc2 ldr r2, [r0, #60] @ 0x3c
|
|
8007468: b112 cbz r2, 8007470 <_raise_r+0x1e>
|
|
800746a: f852 3021 ldr.w r3, [r2, r1, lsl #2]
|
|
800746e: b94b cbnz r3, 8007484 <_raise_r+0x32>
|
|
8007470: 4628 mov r0, r5
|
|
8007472: f000 f831 bl 80074d8 <_getpid_r>
|
|
8007476: 4622 mov r2, r4
|
|
8007478: 4601 mov r1, r0
|
|
800747a: 4628 mov r0, r5
|
|
800747c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8007480: f000 b818 b.w 80074b4 <_kill_r>
|
|
8007484: 2b01 cmp r3, #1
|
|
8007486: d00a beq.n 800749e <_raise_r+0x4c>
|
|
8007488: 1c59 adds r1, r3, #1
|
|
800748a: d103 bne.n 8007494 <_raise_r+0x42>
|
|
800748c: 2316 movs r3, #22
|
|
800748e: 6003 str r3, [r0, #0]
|
|
8007490: 2001 movs r0, #1
|
|
8007492: e7e7 b.n 8007464 <_raise_r+0x12>
|
|
8007494: 2100 movs r1, #0
|
|
8007496: f842 1024 str.w r1, [r2, r4, lsl #2]
|
|
800749a: 4620 mov r0, r4
|
|
800749c: 4798 blx r3
|
|
800749e: 2000 movs r0, #0
|
|
80074a0: e7e0 b.n 8007464 <_raise_r+0x12>
|
|
...
|
|
|
|
080074a4 <raise>:
|
|
80074a4: 4b02 ldr r3, [pc, #8] @ (80074b0 <raise+0xc>)
|
|
80074a6: 4601 mov r1, r0
|
|
80074a8: 6818 ldr r0, [r3, #0]
|
|
80074aa: f7ff bfd2 b.w 8007452 <_raise_r>
|
|
80074ae: bf00 nop
|
|
80074b0: 20000018 .word 0x20000018
|
|
|
|
080074b4 <_kill_r>:
|
|
80074b4: b538 push {r3, r4, r5, lr}
|
|
80074b6: 4d07 ldr r5, [pc, #28] @ (80074d4 <_kill_r+0x20>)
|
|
80074b8: 2300 movs r3, #0
|
|
80074ba: 4604 mov r4, r0
|
|
80074bc: 4608 mov r0, r1
|
|
80074be: 4611 mov r1, r2
|
|
80074c0: 602b str r3, [r5, #0]
|
|
80074c2: f7fa f812 bl 80014ea <_kill>
|
|
80074c6: 1c43 adds r3, r0, #1
|
|
80074c8: d102 bne.n 80074d0 <_kill_r+0x1c>
|
|
80074ca: 682b ldr r3, [r5, #0]
|
|
80074cc: b103 cbz r3, 80074d0 <_kill_r+0x1c>
|
|
80074ce: 6023 str r3, [r4, #0]
|
|
80074d0: bd38 pop {r3, r4, r5, pc}
|
|
80074d2: bf00 nop
|
|
80074d4: 20000410 .word 0x20000410
|
|
|
|
080074d8 <_getpid_r>:
|
|
80074d8: f7f9 bfff b.w 80014da <_getpid>
|
|
|
|
080074dc <_init>:
|
|
80074dc: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80074de: bf00 nop
|
|
80074e0: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80074e2: bc08 pop {r3}
|
|
80074e4: 469e mov lr, r3
|
|
80074e6: 4770 bx lr
|
|
|
|
080074e8 <_fini>:
|
|
80074e8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80074ea: bf00 nop
|
|
80074ec: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80074ee: bc08 pop {r3}
|
|
80074f0: 469e mov lr, r3
|
|
80074f2: 4770 bx lr
|