Gallardo7761/setr1-monorepo
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85e60bcc395d54bac7c45fdfeb66aee5b9aa7fed
setr1-monorepo/P4_SETR1/Debug/P4_SETR1.list
Jose 85e60bcc39 monorepo
2025-10-10 02:20:31 +02:00

13305 lines
503 KiB
Plaintext
Executable File
Raw Blame History

P4_SETR1.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00004d00 08000188 08000188 00001188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000048 08004e88 08004e88 00005e88 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08004ed0 08004ed0 0000600c 2**0
CONTENTS, READONLY
4 .ARM 00000008 08004ed0 08004ed0 00005ed0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08004ed8 08004ed8 0000600c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08004ed8 08004ed8 00005ed8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08004edc 08004edc 00005edc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08004ee0 00006000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000194 2000000c 08004eec 0000600c 2**2
ALLOC
10 ._user_heap_stack 00000600 200001a0 08004eec 000061a0 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000600c 2**0
CONTENTS, READONLY
12 .debug_info 00012249 00000000 00000000 0000603c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000236a 00000000 00000000 00018285 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001160 00000000 00000000 0001a5f0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000db3 00000000 00000000 0001b750 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00026e2f 00000000 00000000 0001c503 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00014111 00000000 00000000 00043332 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000f3a69 00000000 00000000 00057443 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 0014aeac 2**0
CONTENTS, READONLY
20 .debug_frame 00004a4c 00000000 00000000 0014aef0 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000061 00000000 00000000 0014f93c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000000c .word 0x2000000c
80001a4: 00000000 .word 0x00000000
80001a8: 08004e70 .word 0x08004e70
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000010 .word 0x20000010
80001c4: 08004e70 .word 0x08004e70
080001c8 <__aeabi_uldivmod>:
80001c8: b953 cbnz r3, 80001e0 <__aeabi_uldivmod+0x18>
80001ca: b94a cbnz r2, 80001e0 <__aeabi_uldivmod+0x18>
80001cc: 2900 cmp r1, #0
80001ce: bf08 it eq
80001d0: 2800 cmpeq r0, #0
80001d2: bf1c itt ne
80001d4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
80001d8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
80001dc: f000 b988 b.w 80004f0 <__aeabi_idiv0>
80001e0: f1ad 0c08 sub.w ip, sp, #8
80001e4: e96d ce04 strd ip, lr, [sp, #-16]!
80001e8: f000 f806 bl 80001f8 <__udivmoddi4>
80001ec: f8dd e004 ldr.w lr, [sp, #4]
80001f0: e9dd 2302 ldrd r2, r3, [sp, #8]
80001f4: b004 add sp, #16
80001f6: 4770 bx lr
080001f8 <__udivmoddi4>:
80001f8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80001fc: 9d08 ldr r5, [sp, #32]
80001fe: 468e mov lr, r1
8000200: 4604 mov r4, r0
8000202: 4688 mov r8, r1
8000204: 2b00 cmp r3, #0
8000206: d14a bne.n 800029e <__udivmoddi4+0xa6>
8000208: 428a cmp r2, r1
800020a: 4617 mov r7, r2
800020c: d962 bls.n 80002d4 <__udivmoddi4+0xdc>
800020e: fab2 f682 clz r6, r2
8000212: b14e cbz r6, 8000228 <__udivmoddi4+0x30>
8000214: f1c6 0320 rsb r3, r6, #32
8000218: fa01 f806 lsl.w r8, r1, r6
800021c: fa20 f303 lsr.w r3, r0, r3
8000220: 40b7 lsls r7, r6
8000222: ea43 0808 orr.w r8, r3, r8
8000226: 40b4 lsls r4, r6
8000228: ea4f 4e17 mov.w lr, r7, lsr #16
800022c: fa1f fc87 uxth.w ip, r7
8000230: fbb8 f1fe udiv r1, r8, lr
8000234: 0c23 lsrs r3, r4, #16
8000236: fb0e 8811 mls r8, lr, r1, r8
800023a: ea43 4308 orr.w r3, r3, r8, lsl #16
800023e: fb01 f20c mul.w r2, r1, ip
8000242: 429a cmp r2, r3
8000244: d909 bls.n 800025a <__udivmoddi4+0x62>
8000246: 18fb adds r3, r7, r3
8000248: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
800024c: f080 80ea bcs.w 8000424 <__udivmoddi4+0x22c>
8000250: 429a cmp r2, r3
8000252: f240 80e7 bls.w 8000424 <__udivmoddi4+0x22c>
8000256: 3902 subs r1, #2
8000258: 443b add r3, r7
800025a: 1a9a subs r2, r3, r2
800025c: b2a3 uxth r3, r4
800025e: fbb2 f0fe udiv r0, r2, lr
8000262: fb0e 2210 mls r2, lr, r0, r2
8000266: ea43 4302 orr.w r3, r3, r2, lsl #16
800026a: fb00 fc0c mul.w ip, r0, ip
800026e: 459c cmp ip, r3
8000270: d909 bls.n 8000286 <__udivmoddi4+0x8e>
8000272: 18fb adds r3, r7, r3
8000274: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
8000278: f080 80d6 bcs.w 8000428 <__udivmoddi4+0x230>
800027c: 459c cmp ip, r3
800027e: f240 80d3 bls.w 8000428 <__udivmoddi4+0x230>
8000282: 443b add r3, r7
8000284: 3802 subs r0, #2
8000286: ea40 4001 orr.w r0, r0, r1, lsl #16
800028a: eba3 030c sub.w r3, r3, ip
800028e: 2100 movs r1, #0
8000290: b11d cbz r5, 800029a <__udivmoddi4+0xa2>
8000292: 40f3 lsrs r3, r6
8000294: 2200 movs r2, #0
8000296: e9c5 3200 strd r3, r2, [r5]
800029a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800029e: 428b cmp r3, r1
80002a0: d905 bls.n 80002ae <__udivmoddi4+0xb6>
80002a2: b10d cbz r5, 80002a8 <__udivmoddi4+0xb0>
80002a4: e9c5 0100 strd r0, r1, [r5]
80002a8: 2100 movs r1, #0
80002aa: 4608 mov r0, r1
80002ac: e7f5 b.n 800029a <__udivmoddi4+0xa2>
80002ae: fab3 f183 clz r1, r3
80002b2: 2900 cmp r1, #0
80002b4: d146 bne.n 8000344 <__udivmoddi4+0x14c>
80002b6: 4573 cmp r3, lr
80002b8: d302 bcc.n 80002c0 <__udivmoddi4+0xc8>
80002ba: 4282 cmp r2, r0
80002bc: f200 8105 bhi.w 80004ca <__udivmoddi4+0x2d2>
80002c0: 1a84 subs r4, r0, r2
80002c2: eb6e 0203 sbc.w r2, lr, r3
80002c6: 2001 movs r0, #1
80002c8: 4690 mov r8, r2
80002ca: 2d00 cmp r5, #0
80002cc: d0e5 beq.n 800029a <__udivmoddi4+0xa2>
80002ce: e9c5 4800 strd r4, r8, [r5]
80002d2: e7e2 b.n 800029a <__udivmoddi4+0xa2>
80002d4: 2a00 cmp r2, #0
80002d6: f000 8090 beq.w 80003fa <__udivmoddi4+0x202>
80002da: fab2 f682 clz r6, r2
80002de: 2e00 cmp r6, #0
80002e0: f040 80a4 bne.w 800042c <__udivmoddi4+0x234>
80002e4: 1a8a subs r2, r1, r2
80002e6: 0c03 lsrs r3, r0, #16
80002e8: ea4f 4e17 mov.w lr, r7, lsr #16
80002ec: b280 uxth r0, r0
80002ee: b2bc uxth r4, r7
80002f0: 2101 movs r1, #1
80002f2: fbb2 fcfe udiv ip, r2, lr
80002f6: fb0e 221c mls r2, lr, ip, r2
80002fa: ea43 4302 orr.w r3, r3, r2, lsl #16
80002fe: fb04 f20c mul.w r2, r4, ip
8000302: 429a cmp r2, r3
8000304: d907 bls.n 8000316 <__udivmoddi4+0x11e>
8000306: 18fb adds r3, r7, r3
8000308: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
800030c: d202 bcs.n 8000314 <__udivmoddi4+0x11c>
800030e: 429a cmp r2, r3
8000310: f200 80e0 bhi.w 80004d4 <__udivmoddi4+0x2dc>
8000314: 46c4 mov ip, r8
8000316: 1a9b subs r3, r3, r2
8000318: fbb3 f2fe udiv r2, r3, lr
800031c: fb0e 3312 mls r3, lr, r2, r3
8000320: ea40 4303 orr.w r3, r0, r3, lsl #16
8000324: fb02 f404 mul.w r4, r2, r4
8000328: 429c cmp r4, r3
800032a: d907 bls.n 800033c <__udivmoddi4+0x144>
800032c: 18fb adds r3, r7, r3
800032e: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
8000332: d202 bcs.n 800033a <__udivmoddi4+0x142>
8000334: 429c cmp r4, r3
8000336: f200 80ca bhi.w 80004ce <__udivmoddi4+0x2d6>
800033a: 4602 mov r2, r0
800033c: 1b1b subs r3, r3, r4
800033e: ea42 400c orr.w r0, r2, ip, lsl #16
8000342: e7a5 b.n 8000290 <__udivmoddi4+0x98>
8000344: f1c1 0620 rsb r6, r1, #32
8000348: 408b lsls r3, r1
800034a: fa22 f706 lsr.w r7, r2, r6
800034e: 431f orrs r7, r3
8000350: fa0e f401 lsl.w r4, lr, r1
8000354: fa20 f306 lsr.w r3, r0, r6
8000358: fa2e fe06 lsr.w lr, lr, r6
800035c: ea4f 4917 mov.w r9, r7, lsr #16
8000360: 4323 orrs r3, r4
8000362: fa00 f801 lsl.w r8, r0, r1
8000366: fa1f fc87 uxth.w ip, r7
800036a: fbbe f0f9 udiv r0, lr, r9
800036e: 0c1c lsrs r4, r3, #16
8000370: fb09 ee10 mls lr, r9, r0, lr
8000374: ea44 440e orr.w r4, r4, lr, lsl #16
8000378: fb00 fe0c mul.w lr, r0, ip
800037c: 45a6 cmp lr, r4
800037e: fa02 f201 lsl.w r2, r2, r1
8000382: d909 bls.n 8000398 <__udivmoddi4+0x1a0>
8000384: 193c adds r4, r7, r4
8000386: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
800038a: f080 809c bcs.w 80004c6 <__udivmoddi4+0x2ce>
800038e: 45a6 cmp lr, r4
8000390: f240 8099 bls.w 80004c6 <__udivmoddi4+0x2ce>
8000394: 3802 subs r0, #2
8000396: 443c add r4, r7
8000398: eba4 040e sub.w r4, r4, lr
800039c: fa1f fe83 uxth.w lr, r3
80003a0: fbb4 f3f9 udiv r3, r4, r9
80003a4: fb09 4413 mls r4, r9, r3, r4
80003a8: ea4e 4404 orr.w r4, lr, r4, lsl #16
80003ac: fb03 fc0c mul.w ip, r3, ip
80003b0: 45a4 cmp ip, r4
80003b2: d908 bls.n 80003c6 <__udivmoddi4+0x1ce>
80003b4: 193c adds r4, r7, r4
80003b6: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
80003ba: f080 8082 bcs.w 80004c2 <__udivmoddi4+0x2ca>
80003be: 45a4 cmp ip, r4
80003c0: d97f bls.n 80004c2 <__udivmoddi4+0x2ca>
80003c2: 3b02 subs r3, #2
80003c4: 443c add r4, r7
80003c6: ea43 4000 orr.w r0, r3, r0, lsl #16
80003ca: eba4 040c sub.w r4, r4, ip
80003ce: fba0 ec02 umull lr, ip, r0, r2
80003d2: 4564 cmp r4, ip
80003d4: 4673 mov r3, lr
80003d6: 46e1 mov r9, ip
80003d8: d362 bcc.n 80004a0 <__udivmoddi4+0x2a8>
80003da: d05f beq.n 800049c <__udivmoddi4+0x2a4>
80003dc: b15d cbz r5, 80003f6 <__udivmoddi4+0x1fe>
80003de: ebb8 0203 subs.w r2, r8, r3
80003e2: eb64 0409 sbc.w r4, r4, r9
80003e6: fa04 f606 lsl.w r6, r4, r6
80003ea: fa22 f301 lsr.w r3, r2, r1
80003ee: 431e orrs r6, r3
80003f0: 40cc lsrs r4, r1
80003f2: e9c5 6400 strd r6, r4, [r5]
80003f6: 2100 movs r1, #0
80003f8: e74f b.n 800029a <__udivmoddi4+0xa2>
80003fa: fbb1 fcf2 udiv ip, r1, r2
80003fe: 0c01 lsrs r1, r0, #16
8000400: ea41 410e orr.w r1, r1, lr, lsl #16
8000404: b280 uxth r0, r0
8000406: ea40 4201 orr.w r2, r0, r1, lsl #16
800040a: 463b mov r3, r7
800040c: 4638 mov r0, r7
800040e: 463c mov r4, r7
8000410: 46b8 mov r8, r7
8000412: 46be mov lr, r7
8000414: 2620 movs r6, #32
8000416: fbb1 f1f7 udiv r1, r1, r7
800041a: eba2 0208 sub.w r2, r2, r8
800041e: ea41 410c orr.w r1, r1, ip, lsl #16
8000422: e766 b.n 80002f2 <__udivmoddi4+0xfa>
8000424: 4601 mov r1, r0
8000426: e718 b.n 800025a <__udivmoddi4+0x62>
8000428: 4610 mov r0, r2
800042a: e72c b.n 8000286 <__udivmoddi4+0x8e>
800042c: f1c6 0220 rsb r2, r6, #32
8000430: fa2e f302 lsr.w r3, lr, r2
8000434: 40b7 lsls r7, r6
8000436: 40b1 lsls r1, r6
8000438: fa20 f202 lsr.w r2, r0, r2
800043c: ea4f 4e17 mov.w lr, r7, lsr #16
8000440: 430a orrs r2, r1
8000442: fbb3 f8fe udiv r8, r3, lr
8000446: b2bc uxth r4, r7
8000448: fb0e 3318 mls r3, lr, r8, r3
800044c: 0c11 lsrs r1, r2, #16
800044e: ea41 4103 orr.w r1, r1, r3, lsl #16
8000452: fb08 f904 mul.w r9, r8, r4
8000456: 40b0 lsls r0, r6
8000458: 4589 cmp r9, r1
800045a: ea4f 4310 mov.w r3, r0, lsr #16
800045e: b280 uxth r0, r0
8000460: d93e bls.n 80004e0 <__udivmoddi4+0x2e8>
8000462: 1879 adds r1, r7, r1
8000464: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000468: d201 bcs.n 800046e <__udivmoddi4+0x276>
800046a: 4589 cmp r9, r1
800046c: d81f bhi.n 80004ae <__udivmoddi4+0x2b6>
800046e: eba1 0109 sub.w r1, r1, r9
8000472: fbb1 f9fe udiv r9, r1, lr
8000476: fb09 f804 mul.w r8, r9, r4
800047a: fb0e 1119 mls r1, lr, r9, r1
800047e: b292 uxth r2, r2
8000480: ea42 4201 orr.w r2, r2, r1, lsl #16
8000484: 4542 cmp r2, r8
8000486: d229 bcs.n 80004dc <__udivmoddi4+0x2e4>
8000488: 18ba adds r2, r7, r2
800048a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
800048e: d2c4 bcs.n 800041a <__udivmoddi4+0x222>
8000490: 4542 cmp r2, r8
8000492: d2c2 bcs.n 800041a <__udivmoddi4+0x222>
8000494: f1a9 0102 sub.w r1, r9, #2
8000498: 443a add r2, r7
800049a: e7be b.n 800041a <__udivmoddi4+0x222>
800049c: 45f0 cmp r8, lr
800049e: d29d bcs.n 80003dc <__udivmoddi4+0x1e4>
80004a0: ebbe 0302 subs.w r3, lr, r2
80004a4: eb6c 0c07 sbc.w ip, ip, r7
80004a8: 3801 subs r0, #1
80004aa: 46e1 mov r9, ip
80004ac: e796 b.n 80003dc <__udivmoddi4+0x1e4>
80004ae: eba7 0909 sub.w r9, r7, r9
80004b2: 4449 add r1, r9
80004b4: f1a8 0c02 sub.w ip, r8, #2
80004b8: fbb1 f9fe udiv r9, r1, lr
80004bc: fb09 f804 mul.w r8, r9, r4
80004c0: e7db b.n 800047a <__udivmoddi4+0x282>
80004c2: 4673 mov r3, lr
80004c4: e77f b.n 80003c6 <__udivmoddi4+0x1ce>
80004c6: 4650 mov r0, sl
80004c8: e766 b.n 8000398 <__udivmoddi4+0x1a0>
80004ca: 4608 mov r0, r1
80004cc: e6fd b.n 80002ca <__udivmoddi4+0xd2>
80004ce: 443b add r3, r7
80004d0: 3a02 subs r2, #2
80004d2: e733 b.n 800033c <__udivmoddi4+0x144>
80004d4: f1ac 0c02 sub.w ip, ip, #2
80004d8: 443b add r3, r7
80004da: e71c b.n 8000316 <__udivmoddi4+0x11e>
80004dc: 4649 mov r1, r9
80004de: e79c b.n 800041a <__udivmoddi4+0x222>
80004e0: eba1 0109 sub.w r1, r1, r9
80004e4: 46c4 mov ip, r8
80004e6: fbb1 f9fe udiv r9, r1, lr
80004ea: fb09 f804 mul.w r8, r9, r4
80004ee: e7c4 b.n 800047a <__udivmoddi4+0x282>
080004f0 <__aeabi_idiv0>:
80004f0: 4770 bx lr
80004f2: bf00 nop
080004f4 <LSM6DSL_Init>:
#include "LSM6DSL.h"
extern I2C_HandleTypeDef hi2c2;
void LSM6DSL_Init(void)
{
80004f4: b580 push {r7, lr}
80004f6: b086 sub sp, #24
80004f8: af04 add r7, sp, #16
uint8_t buffer[1];
buffer[0] = 0x40;
80004fa: 2340 movs r3, #64 @ 0x40
80004fc: 713b strb r3, [r7, #4]
HAL_I2C_Mem_Write(&hi2c2, 0xD4, 0x10,
80004fe: f44f 737a mov.w r3, #1000 @ 0x3e8
8000502: 9302 str r3, [sp, #8]
8000504: 2301 movs r3, #1
8000506: 9301 str r3, [sp, #4]
8000508: 1d3b adds r3, r7, #4
800050a: 9300 str r3, [sp, #0]
800050c: 2301 movs r3, #1
800050e: 2210 movs r2, #16
8000510: 21d4 movs r1, #212 @ 0xd4
8000512: 4803 ldr r0, [pc, #12] @ (8000520 <LSM6DSL_Init+0x2c>)
8000514: f001 f81a bl 800154c <HAL_I2C_Mem_Write>
I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000);
}
8000518: bf00 nop
800051a: 3708 adds r7, #8
800051c: 46bd mov sp, r7
800051e: bd80 pop {r7, pc}
8000520: 20000028 .word 0x20000028
08000524 <LSM6DSL_ReadAccel>:
int16_t LSM6DSL_ReadAccel(uint8_t axis)
{
8000524: b580 push {r7, lr}
8000526: b088 sub sp, #32
8000528: af04 add r7, sp, #16
800052a: 4603 mov r3, r0
800052c: 71fb strb r3, [r7, #7]
uint8_t buffer[2];
HAL_I2C_Mem_Read(&hi2c2, 0xD4, 0x28+2*axis,
800052e: 79fb ldrb r3, [r7, #7]
8000530: 3314 adds r3, #20
8000532: b29b uxth r3, r3
8000534: 005b lsls r3, r3, #1
8000536: b29a uxth r2, r3
8000538: f44f 737a mov.w r3, #1000 @ 0x3e8
800053c: 9302 str r3, [sp, #8]
800053e: 2302 movs r3, #2
8000540: 9301 str r3, [sp, #4]
8000542: f107 030c add.w r3, r7, #12
8000546: 9300 str r3, [sp, #0]
8000548: 2301 movs r3, #1
800054a: 21d4 movs r1, #212 @ 0xd4
800054c: 480d ldr r0, [pc, #52] @ (8000584 <LSM6DSL_ReadAccel+0x60>)
800054e: f001 f911 bl 8001774 <HAL_I2C_Mem_Read>
I2C_MEMADD_SIZE_8BIT, buffer, 2, 1000);
return ((int16_t)(buffer[1]<<8) | buffer[0]) * 0.061f;
8000552: 7b7b ldrb r3, [r7, #13]
8000554: b21b sxth r3, r3
8000556: 021b lsls r3, r3, #8
8000558: b21b sxth r3, r3
800055a: 461a mov r2, r3
800055c: 7b3b ldrb r3, [r7, #12]
800055e: 4313 orrs r3, r2
8000560: ee07 3a90 vmov s15, r3
8000564: eef8 7ae7 vcvt.f32.s32 s15, s15
8000568: ed9f 7a07 vldr s14, [pc, #28] @ 8000588 <LSM6DSL_ReadAccel+0x64>
800056c: ee67 7a87 vmul.f32 s15, s15, s14
8000570: eefd 7ae7 vcvt.s32.f32 s15, s15
8000574: ee17 3a90 vmov r3, s15
8000578: b21b sxth r3, r3
}
800057a: 4618 mov r0, r3
800057c: 3710 adds r7, #16
800057e: 46bd mov sp, r7
8000580: bd80 pop {r7, pc}
8000582: bf00 nop
8000584: 20000028 .word 0x20000028
8000588: 3d79db23 .word 0x3d79db23
0800058c <set_motor_speed>:
return ch;
}
void set_motor_speed(int16_t speed)
{
800058c: b480 push {r7}
800058e: b083 sub sp, #12
8000590: af00 add r7, sp, #0
8000592: 4603 mov r3, r0
8000594: 80fb strh r3, [r7, #6]
if(speed >= 0)
8000596: f9b7 3006 ldrsh.w r3, [r7, #6]
800059a: 2b00 cmp r3, #0
800059c: db09 blt.n 80005b2 <set_motor_speed+0x26>
{
__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, speed);
800059e: 4b0d ldr r3, [pc, #52] @ (80005d4 <set_motor_speed+0x48>)
80005a0: 681b ldr r3, [r3, #0]
80005a2: f9b7 2006 ldrsh.w r2, [r7, #6]
80005a6: 635a str r2, [r3, #52] @ 0x34
__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_3, 0);
80005a8: 4b0a ldr r3, [pc, #40] @ (80005d4 <set_motor_speed+0x48>)
80005aa: 681b ldr r3, [r3, #0]
80005ac: 2200 movs r2, #0
80005ae: 63da str r2, [r3, #60] @ 0x3c
else
{
__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_3, -speed);
__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, 0);
}
}
80005b0: e009 b.n 80005c6 <set_motor_speed+0x3a>
__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_3, -speed);
80005b2: f9b7 3006 ldrsh.w r3, [r7, #6]
80005b6: 425a negs r2, r3
80005b8: 4b06 ldr r3, [pc, #24] @ (80005d4 <set_motor_speed+0x48>)
80005ba: 681b ldr r3, [r3, #0]
80005bc: 63da str r2, [r3, #60] @ 0x3c
__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, 0);
80005be: 4b05 ldr r3, [pc, #20] @ (80005d4 <set_motor_speed+0x48>)
80005c0: 681b ldr r3, [r3, #0]
80005c2: 2200 movs r2, #0
80005c4: 635a str r2, [r3, #52] @ 0x34
}
80005c6: bf00 nop
80005c8: 370c adds r7, #12
80005ca: 46bd mov sp, r7
80005cc: f85d 7b04 ldr.w r7, [sp], #4
80005d0: 4770 bx lr
80005d2: bf00 nop
80005d4: 2000007c .word 0x2000007c
080005d8 <set_servo_pos>:
void set_servo_pos(float angle)
{
80005d8: b480 push {r7}
80005da: b083 sub sp, #12
80005dc: af00 add r7, sp, #0
80005de: ed87 0a01 vstr s0, [r7, #4]
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_4, angle*2500/180);
80005e2: edd7 7a01 vldr s15, [r7, #4]
80005e6: ed9f 7a0a vldr s14, [pc, #40] @ 8000610 <set_servo_pos+0x38>
80005ea: ee27 7a87 vmul.f32 s14, s15, s14
80005ee: eddf 6a09 vldr s13, [pc, #36] @ 8000614 <set_servo_pos+0x3c>
80005f2: eec7 7a26 vdiv.f32 s15, s14, s13
80005f6: 4b08 ldr r3, [pc, #32] @ (8000618 <set_servo_pos+0x40>)
80005f8: 681b ldr r3, [r3, #0]
80005fa: eefc 7ae7 vcvt.u32.f32 s15, s15
80005fe: ee17 2a90 vmov r2, s15
8000602: 641a str r2, [r3, #64] @ 0x40
}
8000604: bf00 nop
8000606: 370c adds r7, #12
8000608: 46bd mov sp, r7
800060a: f85d 7b04 ldr.w r7, [sp], #4
800060e: 4770 bx lr
8000610: 451c4000 .word 0x451c4000
8000614: 43340000 .word 0x43340000
8000618: 200000c8 .word 0x200000c8
0800061c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800061c: b580 push {r7, lr}
800061e: b082 sub sp, #8
8000620: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000622: f000 fbce bl 8000dc2 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000626: f000 f849 bl 80006bc <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800062a: f000 f9c7 bl 80009bc <MX_GPIO_Init>
MX_TIM2_Init();
800062e: f000 f8d7 bl 80007e0 <MX_TIM2_Init>
MX_USART1_UART_Init();
8000632: f000 f993 bl 800095c <MX_USART1_UART_Init>
MX_I2C2_Init();
8000636: f000 f893 bl 8000760 <MX_I2C2_Init>
MX_TIM3_Init();
800063a: f000 f935 bl 80008a8 <MX_TIM3_Init>
/* USER CODE BEGIN 2 */
LSM6DSL_Init();
800063e: f7ff ff59 bl 80004f4 <LSM6DSL_Init>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3);
8000642: 2108 movs r1, #8
8000644: 481a ldr r0, [pc, #104] @ (80006b0 <main+0x94>)
8000646: f003 f881 bl 800374c <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
800064a: 2100 movs r1, #0
800064c: 4818 ldr r0, [pc, #96] @ (80006b0 <main+0x94>)
800064e: f003 f87d bl 800374c <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_4);
8000652: 210c movs r1, #12
8000654: 4817 ldr r0, [pc, #92] @ (80006b4 <main+0x98>)
8000656: f003 f879 bl 800374c <HAL_TIM_PWM_Start>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
int16_t yValue = LSM6DSL_ReadAccel(Y_AXIS);
800065a: 2001 movs r0, #1
800065c: f7ff ff62 bl 8000524 <LSM6DSL_ReadAccel>
8000660: 4603 mov r3, r0
8000662: 80fb strh r3, [r7, #6]
set_motor_speed(4*yValue);
8000664: 88fb ldrh r3, [r7, #6]
8000666: 009b lsls r3, r3, #2
8000668: b29b uxth r3, r3
800066a: b21b sxth r3, r3
800066c: 4618 mov r0, r3
800066e: f7ff ff8d bl 800058c <set_motor_speed>
int16_t xValue = LSM6DSL_ReadAccel(X_AXIS);
8000672: 2000 movs r0, #0
8000674: f7ff ff56 bl 8000524 <LSM6DSL_ReadAccel>
8000678: 4603 mov r3, r0
800067a: 80bb strh r3, [r7, #4]
set_servo_pos((1000+xValue)*180/2000);
800067c: f9b7 3004 ldrsh.w r3, [r7, #4]
8000680: f503 737a add.w r3, r3, #1000 @ 0x3e8
8000684: 22b4 movs r2, #180 @ 0xb4
8000686: fb02 f303 mul.w r3, r2, r3
800068a: 4a0b ldr r2, [pc, #44] @ (80006b8 <main+0x9c>)
800068c: fb82 1203 smull r1, r2, r2, r3
8000690: 11d2 asrs r2, r2, #7
8000692: 17db asrs r3, r3, #31
8000694: 1ad3 subs r3, r2, r3
8000696: ee07 3a90 vmov s15, r3
800069a: eef8 7ae7 vcvt.f32.s32 s15, s15
800069e: eeb0 0a67 vmov.f32 s0, s15
80006a2: f7ff ff99 bl 80005d8 <set_servo_pos>
HAL_Delay(50);
80006a6: 2032 movs r0, #50 @ 0x32
80006a8: f000 fc00 bl 8000eac <HAL_Delay>
{
80006ac: bf00 nop
80006ae: e7d4 b.n 800065a <main+0x3e>
80006b0: 2000007c .word 0x2000007c
80006b4: 200000c8 .word 0x200000c8
80006b8: 10624dd3 .word 0x10624dd3
080006bc <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80006bc: b580 push {r7, lr}
80006be: b096 sub sp, #88 @ 0x58
80006c0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80006c2: f107 0314 add.w r3, r7, #20
80006c6: 2244 movs r2, #68 @ 0x44
80006c8: 2100 movs r1, #0
80006ca: 4618 mov r0, r3
80006cc: f004 fba3 bl 8004e16 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80006d0: 463b mov r3, r7
80006d2: 2200 movs r2, #0
80006d4: 601a str r2, [r3, #0]
80006d6: 605a str r2, [r3, #4]
80006d8: 609a str r2, [r3, #8]
80006da: 60da str r2, [r3, #12]
80006dc: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
80006de: f44f 7000 mov.w r0, #512 @ 0x200
80006e2: f001 fcc9 bl 8002078 <HAL_PWREx_ControlVoltageScaling>
80006e6: 4603 mov r3, r0
80006e8: 2b00 cmp r3, #0
80006ea: d001 beq.n 80006f0 <SystemClock_Config+0x34>
{
Error_Handler();
80006ec: f000 f98a bl 8000a04 <Error_Handler>
}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
80006f0: 2310 movs r3, #16
80006f2: 617b str r3, [r7, #20]
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
80006f4: 2301 movs r3, #1
80006f6: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.MSICalibrationValue = 0;
80006f8: 2300 movs r3, #0
80006fa: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
80006fc: 2360 movs r3, #96 @ 0x60
80006fe: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000700: 2302 movs r3, #2
8000702: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
8000704: 2301 movs r3, #1
8000706: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLM = 1;
8000708: 2301 movs r3, #1
800070a: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLN = 40;
800070c: 2328 movs r3, #40 @ 0x28
800070e: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
8000710: 2307 movs r3, #7
8000712: 64fb str r3, [r7, #76] @ 0x4c
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
8000714: 2302 movs r3, #2
8000716: 653b str r3, [r7, #80] @ 0x50
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
8000718: 2302 movs r3, #2
800071a: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800071c: f107 0314 add.w r3, r7, #20
8000720: 4618 mov r0, r3
8000722: f001 fcff bl 8002124 <HAL_RCC_OscConfig>
8000726: 4603 mov r3, r0
8000728: 2b00 cmp r3, #0
800072a: d001 beq.n 8000730 <SystemClock_Config+0x74>
{
Error_Handler();
800072c: f000 f96a bl 8000a04 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000730: 230f movs r3, #15
8000732: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000734: 2303 movs r3, #3
8000736: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000738: 2300 movs r3, #0
800073a: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800073c: 2300 movs r3, #0
800073e: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000740: 2300 movs r3, #0
8000742: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
8000744: 463b mov r3, r7
8000746: 2104 movs r1, #4
8000748: 4618 mov r0, r3
800074a: f002 f8c7 bl 80028dc <HAL_RCC_ClockConfig>
800074e: 4603 mov r3, r0
8000750: 2b00 cmp r3, #0
8000752: d001 beq.n 8000758 <SystemClock_Config+0x9c>
{
Error_Handler();
8000754: f000 f956 bl 8000a04 <Error_Handler>
}
}
8000758: bf00 nop
800075a: 3758 adds r7, #88 @ 0x58
800075c: 46bd mov sp, r7
800075e: bd80 pop {r7, pc}
08000760 <MX_I2C2_Init>:
* @brief I2C2 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C2_Init(void)
{
8000760: b580 push {r7, lr}
8000762: af00 add r7, sp, #0
/* USER CODE END I2C2_Init 0 */
/* USER CODE BEGIN I2C2_Init 1 */
/* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2;
8000764: 4b1b ldr r3, [pc, #108] @ (80007d4 <MX_I2C2_Init+0x74>)
8000766: 4a1c ldr r2, [pc, #112] @ (80007d8 <MX_I2C2_Init+0x78>)
8000768: 601a str r2, [r3, #0]
hi2c2.Init.Timing = 0x10D19CE4;
800076a: 4b1a ldr r3, [pc, #104] @ (80007d4 <MX_I2C2_Init+0x74>)
800076c: 4a1b ldr r2, [pc, #108] @ (80007dc <MX_I2C2_Init+0x7c>)
800076e: 605a str r2, [r3, #4]
hi2c2.Init.OwnAddress1 = 0;
8000770: 4b18 ldr r3, [pc, #96] @ (80007d4 <MX_I2C2_Init+0x74>)
8000772: 2200 movs r2, #0
8000774: 609a str r2, [r3, #8]
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8000776: 4b17 ldr r3, [pc, #92] @ (80007d4 <MX_I2C2_Init+0x74>)
8000778: 2201 movs r2, #1
800077a: 60da str r2, [r3, #12]
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
800077c: 4b15 ldr r3, [pc, #84] @ (80007d4 <MX_I2C2_Init+0x74>)
800077e: 2200 movs r2, #0
8000780: 611a str r2, [r3, #16]
hi2c2.Init.OwnAddress2 = 0;
8000782: 4b14 ldr r3, [pc, #80] @ (80007d4 <MX_I2C2_Init+0x74>)
8000784: 2200 movs r2, #0
8000786: 615a str r2, [r3, #20]
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
8000788: 4b12 ldr r3, [pc, #72] @ (80007d4 <MX_I2C2_Init+0x74>)
800078a: 2200 movs r2, #0
800078c: 619a str r2, [r3, #24]
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
800078e: 4b11 ldr r3, [pc, #68] @ (80007d4 <MX_I2C2_Init+0x74>)
8000790: 2200 movs r2, #0
8000792: 61da str r2, [r3, #28]
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8000794: 4b0f ldr r3, [pc, #60] @ (80007d4 <MX_I2C2_Init+0x74>)
8000796: 2200 movs r2, #0
8000798: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
800079a: 480e ldr r0, [pc, #56] @ (80007d4 <MX_I2C2_Init+0x74>)
800079c: f000 fe3a bl 8001414 <HAL_I2C_Init>
80007a0: 4603 mov r3, r0
80007a2: 2b00 cmp r3, #0
80007a4: d001 beq.n 80007aa <MX_I2C2_Init+0x4a>
{
Error_Handler();
80007a6: f000 f92d bl 8000a04 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
80007aa: 2100 movs r1, #0
80007ac: 4809 ldr r0, [pc, #36] @ (80007d4 <MX_I2C2_Init+0x74>)
80007ae: f001 fbbd bl 8001f2c <HAL_I2CEx_ConfigAnalogFilter>
80007b2: 4603 mov r3, r0
80007b4: 2b00 cmp r3, #0
80007b6: d001 beq.n 80007bc <MX_I2C2_Init+0x5c>
{
Error_Handler();
80007b8: f000 f924 bl 8000a04 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
80007bc: 2100 movs r1, #0
80007be: 4805 ldr r0, [pc, #20] @ (80007d4 <MX_I2C2_Init+0x74>)
80007c0: f001 fbff bl 8001fc2 <HAL_I2CEx_ConfigDigitalFilter>
80007c4: 4603 mov r3, r0
80007c6: 2b00 cmp r3, #0
80007c8: d001 beq.n 80007ce <MX_I2C2_Init+0x6e>
{
Error_Handler();
80007ca: f000 f91b bl 8000a04 <Error_Handler>
}
/* USER CODE BEGIN I2C2_Init 2 */
/* USER CODE END I2C2_Init 2 */
}
80007ce: bf00 nop
80007d0: bd80 pop {r7, pc}
80007d2: bf00 nop
80007d4: 20000028 .word 0x20000028
80007d8: 40005800 .word 0x40005800
80007dc: 10d19ce4 .word 0x10d19ce4
080007e0 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
80007e0: b580 push {r7, lr}
80007e2: b08a sub sp, #40 @ 0x28
80007e4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
80007e6: f107 031c add.w r3, r7, #28
80007ea: 2200 movs r2, #0
80007ec: 601a str r2, [r3, #0]
80007ee: 605a str r2, [r3, #4]
80007f0: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
80007f2: 463b mov r3, r7
80007f4: 2200 movs r2, #0
80007f6: 601a str r2, [r3, #0]
80007f8: 605a str r2, [r3, #4]
80007fa: 609a str r2, [r3, #8]
80007fc: 60da str r2, [r3, #12]
80007fe: 611a str r2, [r3, #16]
8000800: 615a str r2, [r3, #20]
8000802: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8000804: 4b27 ldr r3, [pc, #156] @ (80008a4 <MX_TIM2_Init+0xc4>)
8000806: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
800080a: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
800080c: 4b25 ldr r3, [pc, #148] @ (80008a4 <MX_TIM2_Init+0xc4>)
800080e: 2200 movs r2, #0
8000810: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000812: 4b24 ldr r3, [pc, #144] @ (80008a4 <MX_TIM2_Init+0xc4>)
8000814: 2200 movs r2, #0
8000816: 609a str r2, [r3, #8]
htim2.Init.Period = 4000;
8000818: 4b22 ldr r3, [pc, #136] @ (80008a4 <MX_TIM2_Init+0xc4>)
800081a: f44f 627a mov.w r2, #4000 @ 0xfa0
800081e: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000820: 4b20 ldr r3, [pc, #128] @ (80008a4 <MX_TIM2_Init+0xc4>)
8000822: 2200 movs r2, #0
8000824: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000826: 4b1f ldr r3, [pc, #124] @ (80008a4 <MX_TIM2_Init+0xc4>)
8000828: 2200 movs r2, #0
800082a: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
800082c: 481d ldr r0, [pc, #116] @ (80008a4 <MX_TIM2_Init+0xc4>)
800082e: f002 ff35 bl 800369c <HAL_TIM_PWM_Init>
8000832: 4603 mov r3, r0
8000834: 2b00 cmp r3, #0
8000836: d001 beq.n 800083c <MX_TIM2_Init+0x5c>
{
Error_Handler();
8000838: f000 f8e4 bl 8000a04 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800083c: 2300 movs r3, #0
800083e: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000840: 2300 movs r3, #0
8000842: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000844: f107 031c add.w r3, r7, #28
8000848: 4619 mov r1, r3
800084a: 4816 ldr r0, [pc, #88] @ (80008a4 <MX_TIM2_Init+0xc4>)
800084c: f003 fd3a bl 80042c4 <HAL_TIMEx_MasterConfigSynchronization>
8000850: 4603 mov r3, r0
8000852: 2b00 cmp r3, #0
8000854: d001 beq.n 800085a <MX_TIM2_Init+0x7a>
{
Error_Handler();
8000856: f000 f8d5 bl 8000a04 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800085a: 2360 movs r3, #96 @ 0x60
800085c: 603b str r3, [r7, #0]
sConfigOC.Pulse = 0;
800085e: 2300 movs r3, #0
8000860: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000862: 2300 movs r3, #0
8000864: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000866: 2300 movs r3, #0
8000868: 613b str r3, [r7, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800086a: 463b mov r3, r7
800086c: 2200 movs r2, #0
800086e: 4619 mov r1, r3
8000870: 480c ldr r0, [pc, #48] @ (80008a4 <MX_TIM2_Init+0xc4>)
8000872: f003 f871 bl 8003958 <HAL_TIM_PWM_ConfigChannel>
8000876: 4603 mov r3, r0
8000878: 2b00 cmp r3, #0
800087a: d001 beq.n 8000880 <MX_TIM2_Init+0xa0>
{
Error_Handler();
800087c: f000 f8c2 bl 8000a04 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8000880: 463b mov r3, r7
8000882: 2208 movs r2, #8
8000884: 4619 mov r1, r3
8000886: 4807 ldr r0, [pc, #28] @ (80008a4 <MX_TIM2_Init+0xc4>)
8000888: f003 f866 bl 8003958 <HAL_TIM_PWM_ConfigChannel>
800088c: 4603 mov r3, r0
800088e: 2b00 cmp r3, #0
8000890: d001 beq.n 8000896 <MX_TIM2_Init+0xb6>
{
Error_Handler();
8000892: f000 f8b7 bl 8000a04 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
8000896: 4803 ldr r0, [pc, #12] @ (80008a4 <MX_TIM2_Init+0xc4>)
8000898: f000 f96e bl 8000b78 <HAL_TIM_MspPostInit>
}
800089c: bf00 nop
800089e: 3728 adds r7, #40 @ 0x28
80008a0: 46bd mov sp, r7
80008a2: bd80 pop {r7, pc}
80008a4: 2000007c .word 0x2000007c
080008a8 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
80008a8: b580 push {r7, lr}
80008aa: b08a sub sp, #40 @ 0x28
80008ac: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
80008ae: f107 031c add.w r3, r7, #28
80008b2: 2200 movs r2, #0
80008b4: 601a str r2, [r3, #0]
80008b6: 605a str r2, [r3, #4]
80008b8: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
80008ba: 463b mov r3, r7
80008bc: 2200 movs r2, #0
80008be: 601a str r2, [r3, #0]
80008c0: 605a str r2, [r3, #4]
80008c2: 609a str r2, [r3, #8]
80008c4: 60da str r2, [r3, #12]
80008c6: 611a str r2, [r3, #16]
80008c8: 615a str r2, [r3, #20]
80008ca: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80008cc: 4b21 ldr r3, [pc, #132] @ (8000954 <MX_TIM3_Init+0xac>)
80008ce: 4a22 ldr r2, [pc, #136] @ (8000958 <MX_TIM3_Init+0xb0>)
80008d0: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 79;
80008d2: 4b20 ldr r3, [pc, #128] @ (8000954 <MX_TIM3_Init+0xac>)
80008d4: 224f movs r2, #79 @ 0x4f
80008d6: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80008d8: 4b1e ldr r3, [pc, #120] @ (8000954 <MX_TIM3_Init+0xac>)
80008da: 2200 movs r2, #0
80008dc: 609a str r2, [r3, #8]
htim3.Init.Period = 20000;
80008de: 4b1d ldr r3, [pc, #116] @ (8000954 <MX_TIM3_Init+0xac>)
80008e0: f644 6220 movw r2, #20000 @ 0x4e20
80008e4: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80008e6: 4b1b ldr r3, [pc, #108] @ (8000954 <MX_TIM3_Init+0xac>)
80008e8: 2200 movs r2, #0
80008ea: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80008ec: 4b19 ldr r3, [pc, #100] @ (8000954 <MX_TIM3_Init+0xac>)
80008ee: 2200 movs r2, #0
80008f0: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
80008f2: 4818 ldr r0, [pc, #96] @ (8000954 <MX_TIM3_Init+0xac>)
80008f4: f002 fed2 bl 800369c <HAL_TIM_PWM_Init>
80008f8: 4603 mov r3, r0
80008fa: 2b00 cmp r3, #0
80008fc: d001 beq.n 8000902 <MX_TIM3_Init+0x5a>
{
Error_Handler();
80008fe: f000 f881 bl 8000a04 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000902: 2300 movs r3, #0
8000904: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000906: 2300 movs r3, #0
8000908: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
800090a: f107 031c add.w r3, r7, #28
800090e: 4619 mov r1, r3
8000910: 4810 ldr r0, [pc, #64] @ (8000954 <MX_TIM3_Init+0xac>)
8000912: f003 fcd7 bl 80042c4 <HAL_TIMEx_MasterConfigSynchronization>
8000916: 4603 mov r3, r0
8000918: 2b00 cmp r3, #0
800091a: d001 beq.n 8000920 <MX_TIM3_Init+0x78>
{
Error_Handler();
800091c: f000 f872 bl 8000a04 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000920: 2360 movs r3, #96 @ 0x60
8000922: 603b str r3, [r7, #0]
sConfigOC.Pulse = 0;
8000924: 2300 movs r3, #0
8000926: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000928: 2300 movs r3, #0
800092a: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
800092c: 2300 movs r3, #0
800092e: 613b str r3, [r7, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8000930: 463b mov r3, r7
8000932: 220c movs r2, #12
8000934: 4619 mov r1, r3
8000936: 4807 ldr r0, [pc, #28] @ (8000954 <MX_TIM3_Init+0xac>)
8000938: f003 f80e bl 8003958 <HAL_TIM_PWM_ConfigChannel>
800093c: 4603 mov r3, r0
800093e: 2b00 cmp r3, #0
8000940: d001 beq.n 8000946 <MX_TIM3_Init+0x9e>
{
Error_Handler();
8000942: f000 f85f bl 8000a04 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
8000946: 4803 ldr r0, [pc, #12] @ (8000954 <MX_TIM3_Init+0xac>)
8000948: f000 f916 bl 8000b78 <HAL_TIM_MspPostInit>
}
800094c: bf00 nop
800094e: 3728 adds r7, #40 @ 0x28
8000950: 46bd mov sp, r7
8000952: bd80 pop {r7, pc}
8000954: 200000c8 .word 0x200000c8
8000958: 40000400 .word 0x40000400
0800095c <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
800095c: b580 push {r7, lr}
800095e: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8000960: 4b14 ldr r3, [pc, #80] @ (80009b4 <MX_USART1_UART_Init+0x58>)
8000962: 4a15 ldr r2, [pc, #84] @ (80009b8 <MX_USART1_UART_Init+0x5c>)
8000964: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8000966: 4b13 ldr r3, [pc, #76] @ (80009b4 <MX_USART1_UART_Init+0x58>)
8000968: f44f 32e1 mov.w r2, #115200 @ 0x1c200
800096c: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
800096e: 4b11 ldr r3, [pc, #68] @ (80009b4 <MX_USART1_UART_Init+0x58>)
8000970: 2200 movs r2, #0
8000972: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8000974: 4b0f ldr r3, [pc, #60] @ (80009b4 <MX_USART1_UART_Init+0x58>)
8000976: 2200 movs r2, #0
8000978: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
800097a: 4b0e ldr r3, [pc, #56] @ (80009b4 <MX_USART1_UART_Init+0x58>)
800097c: 2200 movs r2, #0
800097e: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8000980: 4b0c ldr r3, [pc, #48] @ (80009b4 <MX_USART1_UART_Init+0x58>)
8000982: 220c movs r2, #12
8000984: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000986: 4b0b ldr r3, [pc, #44] @ (80009b4 <MX_USART1_UART_Init+0x58>)
8000988: 2200 movs r2, #0
800098a: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
800098c: 4b09 ldr r3, [pc, #36] @ (80009b4 <MX_USART1_UART_Init+0x58>)
800098e: 2200 movs r2, #0
8000990: 61da str r2, [r3, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000992: 4b08 ldr r3, [pc, #32] @ (80009b4 <MX_USART1_UART_Init+0x58>)
8000994: 2200 movs r2, #0
8000996: 621a str r2, [r3, #32]
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000998: 4b06 ldr r3, [pc, #24] @ (80009b4 <MX_USART1_UART_Init+0x58>)
800099a: 2200 movs r2, #0
800099c: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart1) != HAL_OK)
800099e: 4805 ldr r0, [pc, #20] @ (80009b4 <MX_USART1_UART_Init+0x58>)
80009a0: f003 fd18 bl 80043d4 <HAL_UART_Init>
80009a4: 4603 mov r3, r0
80009a6: 2b00 cmp r3, #0
80009a8: d001 beq.n 80009ae <MX_USART1_UART_Init+0x52>
{
Error_Handler();
80009aa: f000 f82b bl 8000a04 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
80009ae: bf00 nop
80009b0: bd80 pop {r7, pc}
80009b2: bf00 nop
80009b4: 20000114 .word 0x20000114
80009b8: 40013800 .word 0x40013800
080009bc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80009bc: b480 push {r7}
80009be: b083 sub sp, #12
80009c0: af00 add r7, sp, #0
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
80009c2: 4b0f ldr r3, [pc, #60] @ (8000a00 <MX_GPIO_Init+0x44>)
80009c4: 6cdb ldr r3, [r3, #76] @ 0x4c
80009c6: 4a0e ldr r2, [pc, #56] @ (8000a00 <MX_GPIO_Init+0x44>)
80009c8: f043 0301 orr.w r3, r3, #1
80009cc: 64d3 str r3, [r2, #76] @ 0x4c
80009ce: 4b0c ldr r3, [pc, #48] @ (8000a00 <MX_GPIO_Init+0x44>)
80009d0: 6cdb ldr r3, [r3, #76] @ 0x4c
80009d2: f003 0301 and.w r3, r3, #1
80009d6: 607b str r3, [r7, #4]
80009d8: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
80009da: 4b09 ldr r3, [pc, #36] @ (8000a00 <MX_GPIO_Init+0x44>)
80009dc: 6cdb ldr r3, [r3, #76] @ 0x4c
80009de: 4a08 ldr r2, [pc, #32] @ (8000a00 <MX_GPIO_Init+0x44>)
80009e0: f043 0302 orr.w r3, r3, #2
80009e4: 64d3 str r3, [r2, #76] @ 0x4c
80009e6: 4b06 ldr r3, [pc, #24] @ (8000a00 <MX_GPIO_Init+0x44>)
80009e8: 6cdb ldr r3, [r3, #76] @ 0x4c
80009ea: f003 0302 and.w r3, r3, #2
80009ee: 603b str r3, [r7, #0]
80009f0: 683b ldr r3, [r7, #0]
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80009f2: bf00 nop
80009f4: 370c adds r7, #12
80009f6: 46bd mov sp, r7
80009f8: f85d 7b04 ldr.w r7, [sp], #4
80009fc: 4770 bx lr
80009fe: bf00 nop
8000a00: 40021000 .word 0x40021000
08000a04 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000a04: b480 push {r7}
8000a06: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000a08: b672 cpsid i
}
8000a0a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000a0c: bf00 nop
8000a0e: e7fd b.n 8000a0c <Error_Handler+0x8>
08000a10 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000a10: b480 push {r7}
8000a12: b083 sub sp, #12
8000a14: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000a16: 4b0f ldr r3, [pc, #60] @ (8000a54 <HAL_MspInit+0x44>)
8000a18: 6e1b ldr r3, [r3, #96] @ 0x60
8000a1a: 4a0e ldr r2, [pc, #56] @ (8000a54 <HAL_MspInit+0x44>)
8000a1c: f043 0301 orr.w r3, r3, #1
8000a20: 6613 str r3, [r2, #96] @ 0x60
8000a22: 4b0c ldr r3, [pc, #48] @ (8000a54 <HAL_MspInit+0x44>)
8000a24: 6e1b ldr r3, [r3, #96] @ 0x60
8000a26: f003 0301 and.w r3, r3, #1
8000a2a: 607b str r3, [r7, #4]
8000a2c: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000a2e: 4b09 ldr r3, [pc, #36] @ (8000a54 <HAL_MspInit+0x44>)
8000a30: 6d9b ldr r3, [r3, #88] @ 0x58
8000a32: 4a08 ldr r2, [pc, #32] @ (8000a54 <HAL_MspInit+0x44>)
8000a34: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000a38: 6593 str r3, [r2, #88] @ 0x58
8000a3a: 4b06 ldr r3, [pc, #24] @ (8000a54 <HAL_MspInit+0x44>)
8000a3c: 6d9b ldr r3, [r3, #88] @ 0x58
8000a3e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000a42: 603b str r3, [r7, #0]
8000a44: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000a46: bf00 nop
8000a48: 370c adds r7, #12
8000a4a: 46bd mov sp, r7
8000a4c: f85d 7b04 ldr.w r7, [sp], #4
8000a50: 4770 bx lr
8000a52: bf00 nop
8000a54: 40021000 .word 0x40021000
08000a58 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8000a58: b580 push {r7, lr}
8000a5a: b0ac sub sp, #176 @ 0xb0
8000a5c: af00 add r7, sp, #0
8000a5e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000a60: f107 039c add.w r3, r7, #156 @ 0x9c
8000a64: 2200 movs r2, #0
8000a66: 601a str r2, [r3, #0]
8000a68: 605a str r2, [r3, #4]
8000a6a: 609a str r2, [r3, #8]
8000a6c: 60da str r2, [r3, #12]
8000a6e: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000a70: f107 0314 add.w r3, r7, #20
8000a74: 2288 movs r2, #136 @ 0x88
8000a76: 2100 movs r1, #0
8000a78: 4618 mov r0, r3
8000a7a: f004 f9cc bl 8004e16 <memset>
if(hi2c->Instance==I2C2)
8000a7e: 687b ldr r3, [r7, #4]
8000a80: 681b ldr r3, [r3, #0]
8000a82: 4a21 ldr r2, [pc, #132] @ (8000b08 <HAL_I2C_MspInit+0xb0>)
8000a84: 4293 cmp r3, r2
8000a86: d13b bne.n 8000b00 <HAL_I2C_MspInit+0xa8>
/* USER CODE END I2C2_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
8000a88: 2380 movs r3, #128 @ 0x80
8000a8a: 617b str r3, [r7, #20]
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
8000a8c: 2300 movs r3, #0
8000a8e: 66bb str r3, [r7, #104] @ 0x68
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000a90: f107 0314 add.w r3, r7, #20
8000a94: 4618 mov r0, r3
8000a96: f002 f945 bl 8002d24 <HAL_RCCEx_PeriphCLKConfig>
8000a9a: 4603 mov r3, r0
8000a9c: 2b00 cmp r3, #0
8000a9e: d001 beq.n 8000aa4 <HAL_I2C_MspInit+0x4c>
{
Error_Handler();
8000aa0: f7ff ffb0 bl 8000a04 <Error_Handler>
}
__HAL_RCC_GPIOB_CLK_ENABLE();
8000aa4: 4b19 ldr r3, [pc, #100] @ (8000b0c <HAL_I2C_MspInit+0xb4>)
8000aa6: 6cdb ldr r3, [r3, #76] @ 0x4c
8000aa8: 4a18 ldr r2, [pc, #96] @ (8000b0c <HAL_I2C_MspInit+0xb4>)
8000aaa: f043 0302 orr.w r3, r3, #2
8000aae: 64d3 str r3, [r2, #76] @ 0x4c
8000ab0: 4b16 ldr r3, [pc, #88] @ (8000b0c <HAL_I2C_MspInit+0xb4>)
8000ab2: 6cdb ldr r3, [r3, #76] @ 0x4c
8000ab4: f003 0302 and.w r3, r3, #2
8000ab8: 613b str r3, [r7, #16]
8000aba: 693b ldr r3, [r7, #16]
/**I2C2 GPIO Configuration
PB10 ------> I2C2_SCL
PB11 ------> I2C2_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
8000abc: f44f 6340 mov.w r3, #3072 @ 0xc00
8000ac0: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000ac4: 2312 movs r3, #18
8000ac6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000aca: 2300 movs r3, #0
8000acc: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000ad0: 2303 movs r3, #3
8000ad2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
8000ad6: 2304 movs r3, #4
8000ad8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000adc: f107 039c add.w r3, r7, #156 @ 0x9c
8000ae0: 4619 mov r1, r3
8000ae2: 480b ldr r0, [pc, #44] @ (8000b10 <HAL_I2C_MspInit+0xb8>)
8000ae4: f000 faec bl 80010c0 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C2_CLK_ENABLE();
8000ae8: 4b08 ldr r3, [pc, #32] @ (8000b0c <HAL_I2C_MspInit+0xb4>)
8000aea: 6d9b ldr r3, [r3, #88] @ 0x58
8000aec: 4a07 ldr r2, [pc, #28] @ (8000b0c <HAL_I2C_MspInit+0xb4>)
8000aee: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8000af2: 6593 str r3, [r2, #88] @ 0x58
8000af4: 4b05 ldr r3, [pc, #20] @ (8000b0c <HAL_I2C_MspInit+0xb4>)
8000af6: 6d9b ldr r3, [r3, #88] @ 0x58
8000af8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8000afc: 60fb str r3, [r7, #12]
8000afe: 68fb ldr r3, [r7, #12]
/* USER CODE END I2C2_MspInit 1 */
}
}
8000b00: bf00 nop
8000b02: 37b0 adds r7, #176 @ 0xb0
8000b04: 46bd mov sp, r7
8000b06: bd80 pop {r7, pc}
8000b08: 40005800 .word 0x40005800
8000b0c: 40021000 .word 0x40021000
8000b10: 48000400 .word 0x48000400
08000b14 <HAL_TIM_PWM_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{
8000b14: b480 push {r7}
8000b16: b085 sub sp, #20
8000b18: af00 add r7, sp, #0
8000b1a: 6078 str r0, [r7, #4]
if(htim_pwm->Instance==TIM2)
8000b1c: 687b ldr r3, [r7, #4]
8000b1e: 681b ldr r3, [r3, #0]
8000b20: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8000b24: d10c bne.n 8000b40 <HAL_TIM_PWM_MspInit+0x2c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8000b26: 4b12 ldr r3, [pc, #72] @ (8000b70 <HAL_TIM_PWM_MspInit+0x5c>)
8000b28: 6d9b ldr r3, [r3, #88] @ 0x58
8000b2a: 4a11 ldr r2, [pc, #68] @ (8000b70 <HAL_TIM_PWM_MspInit+0x5c>)
8000b2c: f043 0301 orr.w r3, r3, #1
8000b30: 6593 str r3, [r2, #88] @ 0x58
8000b32: 4b0f ldr r3, [pc, #60] @ (8000b70 <HAL_TIM_PWM_MspInit+0x5c>)
8000b34: 6d9b ldr r3, [r3, #88] @ 0x58
8000b36: f003 0301 and.w r3, r3, #1
8000b3a: 60fb str r3, [r7, #12]
8000b3c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
8000b3e: e010 b.n 8000b62 <HAL_TIM_PWM_MspInit+0x4e>
else if(htim_pwm->Instance==TIM3)
8000b40: 687b ldr r3, [r7, #4]
8000b42: 681b ldr r3, [r3, #0]
8000b44: 4a0b ldr r2, [pc, #44] @ (8000b74 <HAL_TIM_PWM_MspInit+0x60>)
8000b46: 4293 cmp r3, r2
8000b48: d10b bne.n 8000b62 <HAL_TIM_PWM_MspInit+0x4e>
__HAL_RCC_TIM3_CLK_ENABLE();
8000b4a: 4b09 ldr r3, [pc, #36] @ (8000b70 <HAL_TIM_PWM_MspInit+0x5c>)
8000b4c: 6d9b ldr r3, [r3, #88] @ 0x58
8000b4e: 4a08 ldr r2, [pc, #32] @ (8000b70 <HAL_TIM_PWM_MspInit+0x5c>)
8000b50: f043 0302 orr.w r3, r3, #2
8000b54: 6593 str r3, [r2, #88] @ 0x58
8000b56: 4b06 ldr r3, [pc, #24] @ (8000b70 <HAL_TIM_PWM_MspInit+0x5c>)
8000b58: 6d9b ldr r3, [r3, #88] @ 0x58
8000b5a: f003 0302 and.w r3, r3, #2
8000b5e: 60bb str r3, [r7, #8]
8000b60: 68bb ldr r3, [r7, #8]
}
8000b62: bf00 nop
8000b64: 3714 adds r7, #20
8000b66: 46bd mov sp, r7
8000b68: f85d 7b04 ldr.w r7, [sp], #4
8000b6c: 4770 bx lr
8000b6e: bf00 nop
8000b70: 40021000 .word 0x40021000
8000b74: 40000400 .word 0x40000400
08000b78 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000b78: b580 push {r7, lr}
8000b7a: b08a sub sp, #40 @ 0x28
8000b7c: af00 add r7, sp, #0
8000b7e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000b80: f107 0314 add.w r3, r7, #20
8000b84: 2200 movs r2, #0
8000b86: 601a str r2, [r3, #0]
8000b88: 605a str r2, [r3, #4]
8000b8a: 609a str r2, [r3, #8]
8000b8c: 60da str r2, [r3, #12]
8000b8e: 611a str r2, [r3, #16]
if(htim->Instance==TIM2)
8000b90: 687b ldr r3, [r7, #4]
8000b92: 681b ldr r3, [r3, #0]
8000b94: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8000b98: d11e bne.n 8000bd8 <HAL_TIM_MspPostInit+0x60>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000b9a: 4b22 ldr r3, [pc, #136] @ (8000c24 <HAL_TIM_MspPostInit+0xac>)
8000b9c: 6cdb ldr r3, [r3, #76] @ 0x4c
8000b9e: 4a21 ldr r2, [pc, #132] @ (8000c24 <HAL_TIM_MspPostInit+0xac>)
8000ba0: f043 0301 orr.w r3, r3, #1
8000ba4: 64d3 str r3, [r2, #76] @ 0x4c
8000ba6: 4b1f ldr r3, [pc, #124] @ (8000c24 <HAL_TIM_MspPostInit+0xac>)
8000ba8: 6cdb ldr r3, [r3, #76] @ 0x4c
8000baa: f003 0301 and.w r3, r3, #1
8000bae: 613b str r3, [r7, #16]
8000bb0: 693b ldr r3, [r7, #16]
/**TIM2 GPIO Configuration
PA2 ------> TIM2_CH3
PA15 (JTDI) ------> TIM2_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_15;
8000bb2: f248 0304 movw r3, #32772 @ 0x8004
8000bb6: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bb8: 2302 movs r3, #2
8000bba: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bbc: 2300 movs r3, #0
8000bbe: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bc0: 2300 movs r3, #0
8000bc2: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8000bc4: 2301 movs r3, #1
8000bc6: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000bc8: f107 0314 add.w r3, r7, #20
8000bcc: 4619 mov r1, r3
8000bce: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000bd2: f000 fa75 bl 80010c0 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
8000bd6: e020 b.n 8000c1a <HAL_TIM_MspPostInit+0xa2>
else if(htim->Instance==TIM3)
8000bd8: 687b ldr r3, [r7, #4]
8000bda: 681b ldr r3, [r3, #0]
8000bdc: 4a12 ldr r2, [pc, #72] @ (8000c28 <HAL_TIM_MspPostInit+0xb0>)
8000bde: 4293 cmp r3, r2
8000be0: d11b bne.n 8000c1a <HAL_TIM_MspPostInit+0xa2>
__HAL_RCC_GPIOB_CLK_ENABLE();
8000be2: 4b10 ldr r3, [pc, #64] @ (8000c24 <HAL_TIM_MspPostInit+0xac>)
8000be4: 6cdb ldr r3, [r3, #76] @ 0x4c
8000be6: 4a0f ldr r2, [pc, #60] @ (8000c24 <HAL_TIM_MspPostInit+0xac>)
8000be8: f043 0302 orr.w r3, r3, #2
8000bec: 64d3 str r3, [r2, #76] @ 0x4c
8000bee: 4b0d ldr r3, [pc, #52] @ (8000c24 <HAL_TIM_MspPostInit+0xac>)
8000bf0: 6cdb ldr r3, [r3, #76] @ 0x4c
8000bf2: f003 0302 and.w r3, r3, #2
8000bf6: 60fb str r3, [r7, #12]
8000bf8: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_1;
8000bfa: 2302 movs r3, #2
8000bfc: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bfe: 2302 movs r3, #2
8000c00: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c02: 2300 movs r3, #0
8000c04: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c06: 2300 movs r3, #0
8000c08: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
8000c0a: 2302 movs r3, #2
8000c0c: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000c0e: f107 0314 add.w r3, r7, #20
8000c12: 4619 mov r1, r3
8000c14: 4805 ldr r0, [pc, #20] @ (8000c2c <HAL_TIM_MspPostInit+0xb4>)
8000c16: f000 fa53 bl 80010c0 <HAL_GPIO_Init>
}
8000c1a: bf00 nop
8000c1c: 3728 adds r7, #40 @ 0x28
8000c1e: 46bd mov sp, r7
8000c20: bd80 pop {r7, pc}
8000c22: bf00 nop
8000c24: 40021000 .word 0x40021000
8000c28: 40000400 .word 0x40000400
8000c2c: 48000400 .word 0x48000400
08000c30 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8000c30: b580 push {r7, lr}
8000c32: b0ac sub sp, #176 @ 0xb0
8000c34: af00 add r7, sp, #0
8000c36: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000c38: f107 039c add.w r3, r7, #156 @ 0x9c
8000c3c: 2200 movs r2, #0
8000c3e: 601a str r2, [r3, #0]
8000c40: 605a str r2, [r3, #4]
8000c42: 609a str r2, [r3, #8]
8000c44: 60da str r2, [r3, #12]
8000c46: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000c48: f107 0314 add.w r3, r7, #20
8000c4c: 2288 movs r2, #136 @ 0x88
8000c4e: 2100 movs r1, #0
8000c50: 4618 mov r0, r3
8000c52: f004 f8e0 bl 8004e16 <memset>
if(huart->Instance==USART1)
8000c56: 687b ldr r3, [r7, #4]
8000c58: 681b ldr r3, [r3, #0]
8000c5a: 4a21 ldr r2, [pc, #132] @ (8000ce0 <HAL_UART_MspInit+0xb0>)
8000c5c: 4293 cmp r3, r2
8000c5e: d13a bne.n 8000cd6 <HAL_UART_MspInit+0xa6>
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
8000c60: 2301 movs r3, #1
8000c62: 617b str r3, [r7, #20]
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
8000c64: 2300 movs r3, #0
8000c66: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000c68: f107 0314 add.w r3, r7, #20
8000c6c: 4618 mov r0, r3
8000c6e: f002 f859 bl 8002d24 <HAL_RCCEx_PeriphCLKConfig>
8000c72: 4603 mov r3, r0
8000c74: 2b00 cmp r3, #0
8000c76: d001 beq.n 8000c7c <HAL_UART_MspInit+0x4c>
{
Error_Handler();
8000c78: f7ff fec4 bl 8000a04 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8000c7c: 4b19 ldr r3, [pc, #100] @ (8000ce4 <HAL_UART_MspInit+0xb4>)
8000c7e: 6e1b ldr r3, [r3, #96] @ 0x60
8000c80: 4a18 ldr r2, [pc, #96] @ (8000ce4 <HAL_UART_MspInit+0xb4>)
8000c82: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8000c86: 6613 str r3, [r2, #96] @ 0x60
8000c88: 4b16 ldr r3, [pc, #88] @ (8000ce4 <HAL_UART_MspInit+0xb4>)
8000c8a: 6e1b ldr r3, [r3, #96] @ 0x60
8000c8c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8000c90: 613b str r3, [r7, #16]
8000c92: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000c94: 4b13 ldr r3, [pc, #76] @ (8000ce4 <HAL_UART_MspInit+0xb4>)
8000c96: 6cdb ldr r3, [r3, #76] @ 0x4c
8000c98: 4a12 ldr r2, [pc, #72] @ (8000ce4 <HAL_UART_MspInit+0xb4>)
8000c9a: f043 0302 orr.w r3, r3, #2
8000c9e: 64d3 str r3, [r2, #76] @ 0x4c
8000ca0: 4b10 ldr r3, [pc, #64] @ (8000ce4 <HAL_UART_MspInit+0xb4>)
8000ca2: 6cdb ldr r3, [r3, #76] @ 0x4c
8000ca4: f003 0302 and.w r3, r3, #2
8000ca8: 60fb str r3, [r7, #12]
8000caa: 68fb ldr r3, [r7, #12]
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8000cac: 23c0 movs r3, #192 @ 0xc0
8000cae: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cb2: 2302 movs r3, #2
8000cb4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cb8: 2300 movs r3, #0
8000cba: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000cbe: 2303 movs r3, #3
8000cc0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8000cc4: 2307 movs r3, #7
8000cc6: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000cca: f107 039c add.w r3, r7, #156 @ 0x9c
8000cce: 4619 mov r1, r3
8000cd0: 4805 ldr r0, [pc, #20] @ (8000ce8 <HAL_UART_MspInit+0xb8>)
8000cd2: f000 f9f5 bl 80010c0 <HAL_GPIO_Init>
/* USER CODE END USART1_MspInit 1 */
}
}
8000cd6: bf00 nop
8000cd8: 37b0 adds r7, #176 @ 0xb0
8000cda: 46bd mov sp, r7
8000cdc: bd80 pop {r7, pc}
8000cde: bf00 nop
8000ce0: 40013800 .word 0x40013800
8000ce4: 40021000 .word 0x40021000
8000ce8: 48000400 .word 0x48000400
08000cec <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000cec: b480 push {r7}
8000cee: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000cf0: bf00 nop
8000cf2: e7fd b.n 8000cf0 <NMI_Handler+0x4>
08000cf4 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000cf4: b480 push {r7}
8000cf6: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000cf8: bf00 nop
8000cfa: e7fd b.n 8000cf8 <HardFault_Handler+0x4>
08000cfc <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000cfc: b480 push {r7}
8000cfe: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000d00: bf00 nop
8000d02: e7fd b.n 8000d00 <MemManage_Handler+0x4>
08000d04 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000d04: b480 push {r7}
8000d06: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000d08: bf00 nop
8000d0a: e7fd b.n 8000d08 <BusFault_Handler+0x4>
08000d0c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000d0c: b480 push {r7}
8000d0e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000d10: bf00 nop
8000d12: e7fd b.n 8000d10 <UsageFault_Handler+0x4>
08000d14 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000d14: b480 push {r7}
8000d16: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000d18: bf00 nop
8000d1a: 46bd mov sp, r7
8000d1c: f85d 7b04 ldr.w r7, [sp], #4
8000d20: 4770 bx lr
08000d22 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000d22: b480 push {r7}
8000d24: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000d26: bf00 nop
8000d28: 46bd mov sp, r7
8000d2a: f85d 7b04 ldr.w r7, [sp], #4
8000d2e: 4770 bx lr
08000d30 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000d30: b480 push {r7}
8000d32: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000d34: bf00 nop
8000d36: 46bd mov sp, r7
8000d38: f85d 7b04 ldr.w r7, [sp], #4
8000d3c: 4770 bx lr
08000d3e <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000d3e: b580 push {r7, lr}
8000d40: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000d42: f000 f893 bl 8000e6c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000d46: bf00 nop
8000d48: bd80 pop {r7, pc}
...
08000d4c <SystemInit>:
* @brief Setup the microcontroller system.
* @retval None
*/
void SystemInit(void)
{
8000d4c: b480 push {r7}
8000d4e: af00 add r7, sp, #0
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
8000d50: 4b06 ldr r3, [pc, #24] @ (8000d6c <SystemInit+0x20>)
8000d52: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8000d56: 4a05 ldr r2, [pc, #20] @ (8000d6c <SystemInit+0x20>)
8000d58: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8000d5c: f8c2 3088 str.w r3, [r2, #136] @ 0x88
#endif
}
8000d60: bf00 nop
8000d62: 46bd mov sp, r7
8000d64: f85d 7b04 ldr.w r7, [sp], #4
8000d68: 4770 bx lr
8000d6a: bf00 nop
8000d6c: e000ed00 .word 0xe000ed00
08000d70 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
8000d70: f8df d034 ldr.w sp, [pc, #52] @ 8000da8 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
8000d74: f7ff ffea bl 8000d4c <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000d78: 480c ldr r0, [pc, #48] @ (8000dac <LoopForever+0x6>)
ldr r1, =_edata
8000d7a: 490d ldr r1, [pc, #52] @ (8000db0 <LoopForever+0xa>)
ldr r2, =_sidata
8000d7c: 4a0d ldr r2, [pc, #52] @ (8000db4 <LoopForever+0xe>)
movs r3, #0
8000d7e: 2300 movs r3, #0
b LoopCopyDataInit
8000d80: e002 b.n 8000d88 <LoopCopyDataInit>
08000d82 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000d82: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000d84: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000d86: 3304 adds r3, #4
08000d88 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000d88: 18c4 adds r4, r0, r3
cmp r4, r1
8000d8a: 428c cmp r4, r1
bcc CopyDataInit
8000d8c: d3f9 bcc.n 8000d82 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000d8e: 4a0a ldr r2, [pc, #40] @ (8000db8 <LoopForever+0x12>)
ldr r4, =_ebss
8000d90: 4c0a ldr r4, [pc, #40] @ (8000dbc <LoopForever+0x16>)
movs r3, #0
8000d92: 2300 movs r3, #0
b LoopFillZerobss
8000d94: e001 b.n 8000d9a <LoopFillZerobss>
08000d96 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000d96: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000d98: 3204 adds r2, #4
08000d9a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000d9a: 42a2 cmp r2, r4
bcc FillZerobss
8000d9c: d3fb bcc.n 8000d96 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000d9e: f004 f843 bl 8004e28 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000da2: f7ff fc3b bl 800061c <main>
08000da6 <LoopForever>:
LoopForever:
b LoopForever
8000da6: e7fe b.n 8000da6 <LoopForever>
ldr sp, =_estack /* Set stack pointer */
8000da8: 20018000 .word 0x20018000
ldr r0, =_sdata
8000dac: 20000000 .word 0x20000000
ldr r1, =_edata
8000db0: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000db4: 08004ee0 .word 0x08004ee0
ldr r2, =_sbss
8000db8: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000dbc: 200001a0 .word 0x200001a0
08000dc0 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000dc0: e7fe b.n 8000dc0 <ADC1_2_IRQHandler>
08000dc2 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000dc2: b580 push {r7, lr}
8000dc4: b082 sub sp, #8
8000dc6: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8000dc8: 2300 movs r3, #0
8000dca: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000dcc: 2003 movs r0, #3
8000dce: f000 f943 bl 8001058 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8000dd2: 200f movs r0, #15
8000dd4: f000 f80e bl 8000df4 <HAL_InitTick>
8000dd8: 4603 mov r3, r0
8000dda: 2b00 cmp r3, #0
8000ddc: d002 beq.n 8000de4 <HAL_Init+0x22>
{
status = HAL_ERROR;
8000dde: 2301 movs r3, #1
8000de0: 71fb strb r3, [r7, #7]
8000de2: e001 b.n 8000de8 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8000de4: f7ff fe14 bl 8000a10 <HAL_MspInit>
}
/* Return function status */
return status;
8000de8: 79fb ldrb r3, [r7, #7]
}
8000dea: 4618 mov r0, r3
8000dec: 3708 adds r7, #8
8000dee: 46bd mov sp, r7
8000df0: bd80 pop {r7, pc}
...
08000df4 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000df4: b580 push {r7, lr}
8000df6: b084 sub sp, #16
8000df8: af00 add r7, sp, #0
8000dfa: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000dfc: 2300 movs r3, #0
8000dfe: 73fb strb r3, [r7, #15]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8000e00: 4b17 ldr r3, [pc, #92] @ (8000e60 <HAL_InitTick+0x6c>)
8000e02: 781b ldrb r3, [r3, #0]
8000e04: 2b00 cmp r3, #0
8000e06: d023 beq.n 8000e50 <HAL_InitTick+0x5c>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
8000e08: 4b16 ldr r3, [pc, #88] @ (8000e64 <HAL_InitTick+0x70>)
8000e0a: 681a ldr r2, [r3, #0]
8000e0c: 4b14 ldr r3, [pc, #80] @ (8000e60 <HAL_InitTick+0x6c>)
8000e0e: 781b ldrb r3, [r3, #0]
8000e10: 4619 mov r1, r3
8000e12: f44f 737a mov.w r3, #1000 @ 0x3e8
8000e16: fbb3 f3f1 udiv r3, r3, r1
8000e1a: fbb2 f3f3 udiv r3, r2, r3
8000e1e: 4618 mov r0, r3
8000e20: f000 f941 bl 80010a6 <HAL_SYSTICK_Config>
8000e24: 4603 mov r3, r0
8000e26: 2b00 cmp r3, #0
8000e28: d10f bne.n 8000e4a <HAL_InitTick+0x56>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000e2a: 687b ldr r3, [r7, #4]
8000e2c: 2b0f cmp r3, #15
8000e2e: d809 bhi.n 8000e44 <HAL_InitTick+0x50>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000e30: 2200 movs r2, #0
8000e32: 6879 ldr r1, [r7, #4]
8000e34: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000e38: f000 f919 bl 800106e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000e3c: 4a0a ldr r2, [pc, #40] @ (8000e68 <HAL_InitTick+0x74>)
8000e3e: 687b ldr r3, [r7, #4]
8000e40: 6013 str r3, [r2, #0]
8000e42: e007 b.n 8000e54 <HAL_InitTick+0x60>
}
else
{
status = HAL_ERROR;
8000e44: 2301 movs r3, #1
8000e46: 73fb strb r3, [r7, #15]
8000e48: e004 b.n 8000e54 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
8000e4a: 2301 movs r3, #1
8000e4c: 73fb strb r3, [r7, #15]
8000e4e: e001 b.n 8000e54 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
8000e50: 2301 movs r3, #1
8000e52: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8000e54: 7bfb ldrb r3, [r7, #15]
}
8000e56: 4618 mov r0, r3
8000e58: 3710 adds r7, #16
8000e5a: 46bd mov sp, r7
8000e5c: bd80 pop {r7, pc}
8000e5e: bf00 nop
8000e60: 20000008 .word 0x20000008
8000e64: 20000000 .word 0x20000000
8000e68: 20000004 .word 0x20000004
08000e6c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000e6c: b480 push {r7}
8000e6e: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
8000e70: 4b06 ldr r3, [pc, #24] @ (8000e8c <HAL_IncTick+0x20>)
8000e72: 781b ldrb r3, [r3, #0]
8000e74: 461a mov r2, r3
8000e76: 4b06 ldr r3, [pc, #24] @ (8000e90 <HAL_IncTick+0x24>)
8000e78: 681b ldr r3, [r3, #0]
8000e7a: 4413 add r3, r2
8000e7c: 4a04 ldr r2, [pc, #16] @ (8000e90 <HAL_IncTick+0x24>)
8000e7e: 6013 str r3, [r2, #0]
}
8000e80: bf00 nop
8000e82: 46bd mov sp, r7
8000e84: f85d 7b04 ldr.w r7, [sp], #4
8000e88: 4770 bx lr
8000e8a: bf00 nop
8000e8c: 20000008 .word 0x20000008
8000e90: 2000019c .word 0x2000019c
08000e94 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000e94: b480 push {r7}
8000e96: af00 add r7, sp, #0
return uwTick;
8000e98: 4b03 ldr r3, [pc, #12] @ (8000ea8 <HAL_GetTick+0x14>)
8000e9a: 681b ldr r3, [r3, #0]
}
8000e9c: 4618 mov r0, r3
8000e9e: 46bd mov sp, r7
8000ea0: f85d 7b04 ldr.w r7, [sp], #4
8000ea4: 4770 bx lr
8000ea6: bf00 nop
8000ea8: 2000019c .word 0x2000019c
08000eac <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000eac: b580 push {r7, lr}
8000eae: b084 sub sp, #16
8000eb0: af00 add r7, sp, #0
8000eb2: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000eb4: f7ff ffee bl 8000e94 <HAL_GetTick>
8000eb8: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000eba: 687b ldr r3, [r7, #4]
8000ebc: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
8000ebe: 68fb ldr r3, [r7, #12]
8000ec0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8000ec4: d005 beq.n 8000ed2 <HAL_Delay+0x26>
{
wait += (uint32_t)uwTickFreq;
8000ec6: 4b0a ldr r3, [pc, #40] @ (8000ef0 <HAL_Delay+0x44>)
8000ec8: 781b ldrb r3, [r3, #0]
8000eca: 461a mov r2, r3
8000ecc: 68fb ldr r3, [r7, #12]
8000ece: 4413 add r3, r2
8000ed0: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8000ed2: bf00 nop
8000ed4: f7ff ffde bl 8000e94 <HAL_GetTick>
8000ed8: 4602 mov r2, r0
8000eda: 68bb ldr r3, [r7, #8]
8000edc: 1ad3 subs r3, r2, r3
8000ede: 68fa ldr r2, [r7, #12]
8000ee0: 429a cmp r2, r3
8000ee2: d8f7 bhi.n 8000ed4 <HAL_Delay+0x28>
{
}
}
8000ee4: bf00 nop
8000ee6: bf00 nop
8000ee8: 3710 adds r7, #16
8000eea: 46bd mov sp, r7
8000eec: bd80 pop {r7, pc}
8000eee: bf00 nop
8000ef0: 20000008 .word 0x20000008
08000ef4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000ef4: b480 push {r7}
8000ef6: b085 sub sp, #20
8000ef8: af00 add r7, sp, #0
8000efa: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000efc: 687b ldr r3, [r7, #4]
8000efe: f003 0307 and.w r3, r3, #7
8000f02: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000f04: 4b0c ldr r3, [pc, #48] @ (8000f38 <__NVIC_SetPriorityGrouping+0x44>)
8000f06: 68db ldr r3, [r3, #12]
8000f08: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000f0a: 68ba ldr r2, [r7, #8]
8000f0c: f64f 03ff movw r3, #63743 @ 0xf8ff
8000f10: 4013 ands r3, r2
8000f12: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000f14: 68fb ldr r3, [r7, #12]
8000f16: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000f18: 68bb ldr r3, [r7, #8]
8000f1a: 4313 orrs r3, r2
reg_value = (reg_value |
8000f1c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8000f20: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000f24: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000f26: 4a04 ldr r2, [pc, #16] @ (8000f38 <__NVIC_SetPriorityGrouping+0x44>)
8000f28: 68bb ldr r3, [r7, #8]
8000f2a: 60d3 str r3, [r2, #12]
}
8000f2c: bf00 nop
8000f2e: 3714 adds r7, #20
8000f30: 46bd mov sp, r7
8000f32: f85d 7b04 ldr.w r7, [sp], #4
8000f36: 4770 bx lr
8000f38: e000ed00 .word 0xe000ed00
08000f3c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000f3c: b480 push {r7}
8000f3e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000f40: 4b04 ldr r3, [pc, #16] @ (8000f54 <__NVIC_GetPriorityGrouping+0x18>)
8000f42: 68db ldr r3, [r3, #12]
8000f44: 0a1b lsrs r3, r3, #8
8000f46: f003 0307 and.w r3, r3, #7
}
8000f4a: 4618 mov r0, r3
8000f4c: 46bd mov sp, r7
8000f4e: f85d 7b04 ldr.w r7, [sp], #4
8000f52: 4770 bx lr
8000f54: e000ed00 .word 0xe000ed00
08000f58 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000f58: b480 push {r7}
8000f5a: b083 sub sp, #12
8000f5c: af00 add r7, sp, #0
8000f5e: 4603 mov r3, r0
8000f60: 6039 str r1, [r7, #0]
8000f62: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000f64: f997 3007 ldrsb.w r3, [r7, #7]
8000f68: 2b00 cmp r3, #0
8000f6a: db0a blt.n 8000f82 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000f6c: 683b ldr r3, [r7, #0]
8000f6e: b2da uxtb r2, r3
8000f70: 490c ldr r1, [pc, #48] @ (8000fa4 <__NVIC_SetPriority+0x4c>)
8000f72: f997 3007 ldrsb.w r3, [r7, #7]
8000f76: 0112 lsls r2, r2, #4
8000f78: b2d2 uxtb r2, r2
8000f7a: 440b add r3, r1
8000f7c: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000f80: e00a b.n 8000f98 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000f82: 683b ldr r3, [r7, #0]
8000f84: b2da uxtb r2, r3
8000f86: 4908 ldr r1, [pc, #32] @ (8000fa8 <__NVIC_SetPriority+0x50>)
8000f88: 79fb ldrb r3, [r7, #7]
8000f8a: f003 030f and.w r3, r3, #15
8000f8e: 3b04 subs r3, #4
8000f90: 0112 lsls r2, r2, #4
8000f92: b2d2 uxtb r2, r2
8000f94: 440b add r3, r1
8000f96: 761a strb r2, [r3, #24]
}
8000f98: bf00 nop
8000f9a: 370c adds r7, #12
8000f9c: 46bd mov sp, r7
8000f9e: f85d 7b04 ldr.w r7, [sp], #4
8000fa2: 4770 bx lr
8000fa4: e000e100 .word 0xe000e100
8000fa8: e000ed00 .word 0xe000ed00
08000fac <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000fac: b480 push {r7}
8000fae: b089 sub sp, #36 @ 0x24
8000fb0: af00 add r7, sp, #0
8000fb2: 60f8 str r0, [r7, #12]
8000fb4: 60b9 str r1, [r7, #8]
8000fb6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000fb8: 68fb ldr r3, [r7, #12]
8000fba: f003 0307 and.w r3, r3, #7
8000fbe: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000fc0: 69fb ldr r3, [r7, #28]
8000fc2: f1c3 0307 rsb r3, r3, #7
8000fc6: 2b04 cmp r3, #4
8000fc8: bf28 it cs
8000fca: 2304 movcs r3, #4
8000fcc: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000fce: 69fb ldr r3, [r7, #28]
8000fd0: 3304 adds r3, #4
8000fd2: 2b06 cmp r3, #6
8000fd4: d902 bls.n 8000fdc <NVIC_EncodePriority+0x30>
8000fd6: 69fb ldr r3, [r7, #28]
8000fd8: 3b03 subs r3, #3
8000fda: e000 b.n 8000fde <NVIC_EncodePriority+0x32>
8000fdc: 2300 movs r3, #0
8000fde: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000fe0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8000fe4: 69bb ldr r3, [r7, #24]
8000fe6: fa02 f303 lsl.w r3, r2, r3
8000fea: 43da mvns r2, r3
8000fec: 68bb ldr r3, [r7, #8]
8000fee: 401a ands r2, r3
8000ff0: 697b ldr r3, [r7, #20]
8000ff2: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000ff4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8000ff8: 697b ldr r3, [r7, #20]
8000ffa: fa01 f303 lsl.w r3, r1, r3
8000ffe: 43d9 mvns r1, r3
8001000: 687b ldr r3, [r7, #4]
8001002: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001004: 4313 orrs r3, r2
);
}
8001006: 4618 mov r0, r3
8001008: 3724 adds r7, #36 @ 0x24
800100a: 46bd mov sp, r7
800100c: f85d 7b04 ldr.w r7, [sp], #4
8001010: 4770 bx lr
...
08001014 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001014: b580 push {r7, lr}
8001016: b082 sub sp, #8
8001018: af00 add r7, sp, #0
800101a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
800101c: 687b ldr r3, [r7, #4]
800101e: 3b01 subs r3, #1
8001020: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8001024: d301 bcc.n 800102a <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8001026: 2301 movs r3, #1
8001028: e00f b.n 800104a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800102a: 4a0a ldr r2, [pc, #40] @ (8001054 <SysTick_Config+0x40>)
800102c: 687b ldr r3, [r7, #4]
800102e: 3b01 subs r3, #1
8001030: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001032: 210f movs r1, #15
8001034: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8001038: f7ff ff8e bl 8000f58 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
800103c: 4b05 ldr r3, [pc, #20] @ (8001054 <SysTick_Config+0x40>)
800103e: 2200 movs r2, #0
8001040: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001042: 4b04 ldr r3, [pc, #16] @ (8001054 <SysTick_Config+0x40>)
8001044: 2207 movs r2, #7
8001046: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001048: 2300 movs r3, #0
}
800104a: 4618 mov r0, r3
800104c: 3708 adds r7, #8
800104e: 46bd mov sp, r7
8001050: bd80 pop {r7, pc}
8001052: bf00 nop
8001054: e000e010 .word 0xe000e010
08001058 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001058: b580 push {r7, lr}
800105a: b082 sub sp, #8
800105c: af00 add r7, sp, #0
800105e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001060: 6878 ldr r0, [r7, #4]
8001062: f7ff ff47 bl 8000ef4 <__NVIC_SetPriorityGrouping>
}
8001066: bf00 nop
8001068: 3708 adds r7, #8
800106a: 46bd mov sp, r7
800106c: bd80 pop {r7, pc}
0800106e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800106e: b580 push {r7, lr}
8001070: b086 sub sp, #24
8001072: af00 add r7, sp, #0
8001074: 4603 mov r3, r0
8001076: 60b9 str r1, [r7, #8]
8001078: 607a str r2, [r7, #4]
800107a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
800107c: 2300 movs r3, #0
800107e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001080: f7ff ff5c bl 8000f3c <__NVIC_GetPriorityGrouping>
8001084: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001086: 687a ldr r2, [r7, #4]
8001088: 68b9 ldr r1, [r7, #8]
800108a: 6978 ldr r0, [r7, #20]
800108c: f7ff ff8e bl 8000fac <NVIC_EncodePriority>
8001090: 4602 mov r2, r0
8001092: f997 300f ldrsb.w r3, [r7, #15]
8001096: 4611 mov r1, r2
8001098: 4618 mov r0, r3
800109a: f7ff ff5d bl 8000f58 <__NVIC_SetPriority>
}
800109e: bf00 nop
80010a0: 3718 adds r7, #24
80010a2: 46bd mov sp, r7
80010a4: bd80 pop {r7, pc}
080010a6 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80010a6: b580 push {r7, lr}
80010a8: b082 sub sp, #8
80010aa: af00 add r7, sp, #0
80010ac: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80010ae: 6878 ldr r0, [r7, #4]
80010b0: f7ff ffb0 bl 8001014 <SysTick_Config>
80010b4: 4603 mov r3, r0
}
80010b6: 4618 mov r0, r3
80010b8: 3708 adds r7, #8
80010ba: 46bd mov sp, r7
80010bc: bd80 pop {r7, pc}
...
080010c0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80010c0: b480 push {r7}
80010c2: b087 sub sp, #28
80010c4: af00 add r7, sp, #0
80010c6: 6078 str r0, [r7, #4]
80010c8: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80010ca: 2300 movs r3, #0
80010cc: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80010ce: e17f b.n 80013d0 <HAL_GPIO_Init+0x310>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
80010d0: 683b ldr r3, [r7, #0]
80010d2: 681a ldr r2, [r3, #0]
80010d4: 2101 movs r1, #1
80010d6: 697b ldr r3, [r7, #20]
80010d8: fa01 f303 lsl.w r3, r1, r3
80010dc: 4013 ands r3, r2
80010de: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
80010e0: 68fb ldr r3, [r7, #12]
80010e2: 2b00 cmp r3, #0
80010e4: f000 8171 beq.w 80013ca <HAL_GPIO_Init+0x30a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80010e8: 683b ldr r3, [r7, #0]
80010ea: 685b ldr r3, [r3, #4]
80010ec: f003 0303 and.w r3, r3, #3
80010f0: 2b01 cmp r3, #1
80010f2: d005 beq.n 8001100 <HAL_GPIO_Init+0x40>
80010f4: 683b ldr r3, [r7, #0]
80010f6: 685b ldr r3, [r3, #4]
80010f8: f003 0303 and.w r3, r3, #3
80010fc: 2b02 cmp r3, #2
80010fe: d130 bne.n 8001162 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001100: 687b ldr r3, [r7, #4]
8001102: 689b ldr r3, [r3, #8]
8001104: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
8001106: 697b ldr r3, [r7, #20]
8001108: 005b lsls r3, r3, #1
800110a: 2203 movs r2, #3
800110c: fa02 f303 lsl.w r3, r2, r3
8001110: 43db mvns r3, r3
8001112: 693a ldr r2, [r7, #16]
8001114: 4013 ands r3, r2
8001116: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001118: 683b ldr r3, [r7, #0]
800111a: 68da ldr r2, [r3, #12]
800111c: 697b ldr r3, [r7, #20]
800111e: 005b lsls r3, r3, #1
8001120: fa02 f303 lsl.w r3, r2, r3
8001124: 693a ldr r2, [r7, #16]
8001126: 4313 orrs r3, r2
8001128: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800112a: 687b ldr r3, [r7, #4]
800112c: 693a ldr r2, [r7, #16]
800112e: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001130: 687b ldr r3, [r7, #4]
8001132: 685b ldr r3, [r3, #4]
8001134: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8001136: 2201 movs r2, #1
8001138: 697b ldr r3, [r7, #20]
800113a: fa02 f303 lsl.w r3, r2, r3
800113e: 43db mvns r3, r3
8001140: 693a ldr r2, [r7, #16]
8001142: 4013 ands r3, r2
8001144: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001146: 683b ldr r3, [r7, #0]
8001148: 685b ldr r3, [r3, #4]
800114a: 091b lsrs r3, r3, #4
800114c: f003 0201 and.w r2, r3, #1
8001150: 697b ldr r3, [r7, #20]
8001152: fa02 f303 lsl.w r3, r2, r3
8001156: 693a ldr r2, [r7, #16]
8001158: 4313 orrs r3, r2
800115a: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
800115c: 687b ldr r3, [r7, #4]
800115e: 693a ldr r2, [r7, #16]
8001160: 605a str r2, [r3, #4]
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* In case of Analog mode, check if ADC control mode is selected */
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
8001162: 683b ldr r3, [r7, #0]
8001164: 685b ldr r3, [r3, #4]
8001166: f003 0303 and.w r3, r3, #3
800116a: 2b03 cmp r3, #3
800116c: d118 bne.n 80011a0 <HAL_GPIO_Init+0xe0>
{
/* Configure the IO Output Type */
temp = GPIOx->ASCR;
800116e: 687b ldr r3, [r7, #4]
8001170: 6adb ldr r3, [r3, #44] @ 0x2c
8001172: 613b str r3, [r7, #16]
temp &= ~(GPIO_ASCR_ASC0 << position) ;
8001174: 2201 movs r2, #1
8001176: 697b ldr r3, [r7, #20]
8001178: fa02 f303 lsl.w r3, r2, r3
800117c: 43db mvns r3, r3
800117e: 693a ldr r2, [r7, #16]
8001180: 4013 ands r3, r2
8001182: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
8001184: 683b ldr r3, [r7, #0]
8001186: 685b ldr r3, [r3, #4]
8001188: 08db lsrs r3, r3, #3
800118a: f003 0201 and.w r2, r3, #1
800118e: 697b ldr r3, [r7, #20]
8001190: fa02 f303 lsl.w r3, r2, r3
8001194: 693a ldr r2, [r7, #16]
8001196: 4313 orrs r3, r2
8001198: 613b str r3, [r7, #16]
GPIOx->ASCR = temp;
800119a: 687b ldr r3, [r7, #4]
800119c: 693a ldr r2, [r7, #16]
800119e: 62da str r2, [r3, #44] @ 0x2c
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80011a0: 683b ldr r3, [r7, #0]
80011a2: 685b ldr r3, [r3, #4]
80011a4: f003 0303 and.w r3, r3, #3
80011a8: 2b03 cmp r3, #3
80011aa: d017 beq.n 80011dc <HAL_GPIO_Init+0x11c>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
temp = GPIOx->PUPDR;
80011ac: 687b ldr r3, [r7, #4]
80011ae: 68db ldr r3, [r3, #12]
80011b0: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
80011b2: 697b ldr r3, [r7, #20]
80011b4: 005b lsls r3, r3, #1
80011b6: 2203 movs r2, #3
80011b8: fa02 f303 lsl.w r3, r2, r3
80011bc: 43db mvns r3, r3
80011be: 693a ldr r2, [r7, #16]
80011c0: 4013 ands r3, r2
80011c2: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80011c4: 683b ldr r3, [r7, #0]
80011c6: 689a ldr r2, [r3, #8]
80011c8: 697b ldr r3, [r7, #20]
80011ca: 005b lsls r3, r3, #1
80011cc: fa02 f303 lsl.w r3, r2, r3
80011d0: 693a ldr r2, [r7, #16]
80011d2: 4313 orrs r3, r2
80011d4: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80011d6: 687b ldr r3, [r7, #4]
80011d8: 693a ldr r2, [r7, #16]
80011da: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80011dc: 683b ldr r3, [r7, #0]
80011de: 685b ldr r3, [r3, #4]
80011e0: f003 0303 and.w r3, r3, #3
80011e4: 2b02 cmp r3, #2
80011e6: d123 bne.n 8001230 <HAL_GPIO_Init+0x170>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
80011e8: 697b ldr r3, [r7, #20]
80011ea: 08da lsrs r2, r3, #3
80011ec: 687b ldr r3, [r7, #4]
80011ee: 3208 adds r2, #8
80011f0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80011f4: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
80011f6: 697b ldr r3, [r7, #20]
80011f8: f003 0307 and.w r3, r3, #7
80011fc: 009b lsls r3, r3, #2
80011fe: 220f movs r2, #15
8001200: fa02 f303 lsl.w r3, r2, r3
8001204: 43db mvns r3, r3
8001206: 693a ldr r2, [r7, #16]
8001208: 4013 ands r3, r2
800120a: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
800120c: 683b ldr r3, [r7, #0]
800120e: 691a ldr r2, [r3, #16]
8001210: 697b ldr r3, [r7, #20]
8001212: f003 0307 and.w r3, r3, #7
8001216: 009b lsls r3, r3, #2
8001218: fa02 f303 lsl.w r3, r2, r3
800121c: 693a ldr r2, [r7, #16]
800121e: 4313 orrs r3, r2
8001220: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001222: 697b ldr r3, [r7, #20]
8001224: 08da lsrs r2, r3, #3
8001226: 687b ldr r3, [r7, #4]
8001228: 3208 adds r2, #8
800122a: 6939 ldr r1, [r7, #16]
800122c: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001230: 687b ldr r3, [r7, #4]
8001232: 681b ldr r3, [r3, #0]
8001234: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8001236: 697b ldr r3, [r7, #20]
8001238: 005b lsls r3, r3, #1
800123a: 2203 movs r2, #3
800123c: fa02 f303 lsl.w r3, r2, r3
8001240: 43db mvns r3, r3
8001242: 693a ldr r2, [r7, #16]
8001244: 4013 ands r3, r2
8001246: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001248: 683b ldr r3, [r7, #0]
800124a: 685b ldr r3, [r3, #4]
800124c: f003 0203 and.w r2, r3, #3
8001250: 697b ldr r3, [r7, #20]
8001252: 005b lsls r3, r3, #1
8001254: fa02 f303 lsl.w r3, r2, r3
8001258: 693a ldr r2, [r7, #16]
800125a: 4313 orrs r3, r2
800125c: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
800125e: 687b ldr r3, [r7, #4]
8001260: 693a ldr r2, [r7, #16]
8001262: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001264: 683b ldr r3, [r7, #0]
8001266: 685b ldr r3, [r3, #4]
8001268: f403 3340 and.w r3, r3, #196608 @ 0x30000
800126c: 2b00 cmp r3, #0
800126e: f000 80ac beq.w 80013ca <HAL_GPIO_Init+0x30a>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001272: 4b5f ldr r3, [pc, #380] @ (80013f0 <HAL_GPIO_Init+0x330>)
8001274: 6e1b ldr r3, [r3, #96] @ 0x60
8001276: 4a5e ldr r2, [pc, #376] @ (80013f0 <HAL_GPIO_Init+0x330>)
8001278: f043 0301 orr.w r3, r3, #1
800127c: 6613 str r3, [r2, #96] @ 0x60
800127e: 4b5c ldr r3, [pc, #368] @ (80013f0 <HAL_GPIO_Init+0x330>)
8001280: 6e1b ldr r3, [r3, #96] @ 0x60
8001282: f003 0301 and.w r3, r3, #1
8001286: 60bb str r3, [r7, #8]
8001288: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
800128a: 4a5a ldr r2, [pc, #360] @ (80013f4 <HAL_GPIO_Init+0x334>)
800128c: 697b ldr r3, [r7, #20]
800128e: 089b lsrs r3, r3, #2
8001290: 3302 adds r3, #2
8001292: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001296: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8001298: 697b ldr r3, [r7, #20]
800129a: f003 0303 and.w r3, r3, #3
800129e: 009b lsls r3, r3, #2
80012a0: 220f movs r2, #15
80012a2: fa02 f303 lsl.w r3, r2, r3
80012a6: 43db mvns r3, r3
80012a8: 693a ldr r2, [r7, #16]
80012aa: 4013 ands r3, r2
80012ac: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
80012ae: 687b ldr r3, [r7, #4]
80012b0: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
80012b4: d025 beq.n 8001302 <HAL_GPIO_Init+0x242>
80012b6: 687b ldr r3, [r7, #4]
80012b8: 4a4f ldr r2, [pc, #316] @ (80013f8 <HAL_GPIO_Init+0x338>)
80012ba: 4293 cmp r3, r2
80012bc: d01f beq.n 80012fe <HAL_GPIO_Init+0x23e>
80012be: 687b ldr r3, [r7, #4]
80012c0: 4a4e ldr r2, [pc, #312] @ (80013fc <HAL_GPIO_Init+0x33c>)
80012c2: 4293 cmp r3, r2
80012c4: d019 beq.n 80012fa <HAL_GPIO_Init+0x23a>
80012c6: 687b ldr r3, [r7, #4]
80012c8: 4a4d ldr r2, [pc, #308] @ (8001400 <HAL_GPIO_Init+0x340>)
80012ca: 4293 cmp r3, r2
80012cc: d013 beq.n 80012f6 <HAL_GPIO_Init+0x236>
80012ce: 687b ldr r3, [r7, #4]
80012d0: 4a4c ldr r2, [pc, #304] @ (8001404 <HAL_GPIO_Init+0x344>)
80012d2: 4293 cmp r3, r2
80012d4: d00d beq.n 80012f2 <HAL_GPIO_Init+0x232>
80012d6: 687b ldr r3, [r7, #4]
80012d8: 4a4b ldr r2, [pc, #300] @ (8001408 <HAL_GPIO_Init+0x348>)
80012da: 4293 cmp r3, r2
80012dc: d007 beq.n 80012ee <HAL_GPIO_Init+0x22e>
80012de: 687b ldr r3, [r7, #4]
80012e0: 4a4a ldr r2, [pc, #296] @ (800140c <HAL_GPIO_Init+0x34c>)
80012e2: 4293 cmp r3, r2
80012e4: d101 bne.n 80012ea <HAL_GPIO_Init+0x22a>
80012e6: 2306 movs r3, #6
80012e8: e00c b.n 8001304 <HAL_GPIO_Init+0x244>
80012ea: 2307 movs r3, #7
80012ec: e00a b.n 8001304 <HAL_GPIO_Init+0x244>
80012ee: 2305 movs r3, #5
80012f0: e008 b.n 8001304 <HAL_GPIO_Init+0x244>
80012f2: 2304 movs r3, #4
80012f4: e006 b.n 8001304 <HAL_GPIO_Init+0x244>
80012f6: 2303 movs r3, #3
80012f8: e004 b.n 8001304 <HAL_GPIO_Init+0x244>
80012fa: 2302 movs r3, #2
80012fc: e002 b.n 8001304 <HAL_GPIO_Init+0x244>
80012fe: 2301 movs r3, #1
8001300: e000 b.n 8001304 <HAL_GPIO_Init+0x244>
8001302: 2300 movs r3, #0
8001304: 697a ldr r2, [r7, #20]
8001306: f002 0203 and.w r2, r2, #3
800130a: 0092 lsls r2, r2, #2
800130c: 4093 lsls r3, r2
800130e: 693a ldr r2, [r7, #16]
8001310: 4313 orrs r3, r2
8001312: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8001314: 4937 ldr r1, [pc, #220] @ (80013f4 <HAL_GPIO_Init+0x334>)
8001316: 697b ldr r3, [r7, #20]
8001318: 089b lsrs r3, r3, #2
800131a: 3302 adds r3, #2
800131c: 693a ldr r2, [r7, #16]
800131e: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8001322: 4b3b ldr r3, [pc, #236] @ (8001410 <HAL_GPIO_Init+0x350>)
8001324: 689b ldr r3, [r3, #8]
8001326: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001328: 68fb ldr r3, [r7, #12]
800132a: 43db mvns r3, r3
800132c: 693a ldr r2, [r7, #16]
800132e: 4013 ands r3, r2
8001330: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001332: 683b ldr r3, [r7, #0]
8001334: 685b ldr r3, [r3, #4]
8001336: f403 1380 and.w r3, r3, #1048576 @ 0x100000
800133a: 2b00 cmp r3, #0
800133c: d003 beq.n 8001346 <HAL_GPIO_Init+0x286>
{
temp |= iocurrent;
800133e: 693a ldr r2, [r7, #16]
8001340: 68fb ldr r3, [r7, #12]
8001342: 4313 orrs r3, r2
8001344: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8001346: 4a32 ldr r2, [pc, #200] @ (8001410 <HAL_GPIO_Init+0x350>)
8001348: 693b ldr r3, [r7, #16]
800134a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
800134c: 4b30 ldr r3, [pc, #192] @ (8001410 <HAL_GPIO_Init+0x350>)
800134e: 68db ldr r3, [r3, #12]
8001350: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001352: 68fb ldr r3, [r7, #12]
8001354: 43db mvns r3, r3
8001356: 693a ldr r2, [r7, #16]
8001358: 4013 ands r3, r2
800135a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
800135c: 683b ldr r3, [r7, #0]
800135e: 685b ldr r3, [r3, #4]
8001360: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001364: 2b00 cmp r3, #0
8001366: d003 beq.n 8001370 <HAL_GPIO_Init+0x2b0>
{
temp |= iocurrent;
8001368: 693a ldr r2, [r7, #16]
800136a: 68fb ldr r3, [r7, #12]
800136c: 4313 orrs r3, r2
800136e: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8001370: 4a27 ldr r2, [pc, #156] @ (8001410 <HAL_GPIO_Init+0x350>)
8001372: 693b ldr r3, [r7, #16]
8001374: 60d3 str r3, [r2, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8001376: 4b26 ldr r3, [pc, #152] @ (8001410 <HAL_GPIO_Init+0x350>)
8001378: 685b ldr r3, [r3, #4]
800137a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800137c: 68fb ldr r3, [r7, #12]
800137e: 43db mvns r3, r3
8001380: 693a ldr r2, [r7, #16]
8001382: 4013 ands r3, r2
8001384: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001386: 683b ldr r3, [r7, #0]
8001388: 685b ldr r3, [r3, #4]
800138a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800138e: 2b00 cmp r3, #0
8001390: d003 beq.n 800139a <HAL_GPIO_Init+0x2da>
{
temp |= iocurrent;
8001392: 693a ldr r2, [r7, #16]
8001394: 68fb ldr r3, [r7, #12]
8001396: 4313 orrs r3, r2
8001398: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
800139a: 4a1d ldr r2, [pc, #116] @ (8001410 <HAL_GPIO_Init+0x350>)
800139c: 693b ldr r3, [r7, #16]
800139e: 6053 str r3, [r2, #4]
temp = EXTI->IMR1;
80013a0: 4b1b ldr r3, [pc, #108] @ (8001410 <HAL_GPIO_Init+0x350>)
80013a2: 681b ldr r3, [r3, #0]
80013a4: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80013a6: 68fb ldr r3, [r7, #12]
80013a8: 43db mvns r3, r3
80013aa: 693a ldr r2, [r7, #16]
80013ac: 4013 ands r3, r2
80013ae: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
80013b0: 683b ldr r3, [r7, #0]
80013b2: 685b ldr r3, [r3, #4]
80013b4: f403 3380 and.w r3, r3, #65536 @ 0x10000
80013b8: 2b00 cmp r3, #0
80013ba: d003 beq.n 80013c4 <HAL_GPIO_Init+0x304>
{
temp |= iocurrent;
80013bc: 693a ldr r2, [r7, #16]
80013be: 68fb ldr r3, [r7, #12]
80013c0: 4313 orrs r3, r2
80013c2: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
80013c4: 4a12 ldr r2, [pc, #72] @ (8001410 <HAL_GPIO_Init+0x350>)
80013c6: 693b ldr r3, [r7, #16]
80013c8: 6013 str r3, [r2, #0]
}
}
position++;
80013ca: 697b ldr r3, [r7, #20]
80013cc: 3301 adds r3, #1
80013ce: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80013d0: 683b ldr r3, [r7, #0]
80013d2: 681a ldr r2, [r3, #0]
80013d4: 697b ldr r3, [r7, #20]
80013d6: fa22 f303 lsr.w r3, r2, r3
80013da: 2b00 cmp r3, #0
80013dc: f47f ae78 bne.w 80010d0 <HAL_GPIO_Init+0x10>
}
}
80013e0: bf00 nop
80013e2: bf00 nop
80013e4: 371c adds r7, #28
80013e6: 46bd mov sp, r7
80013e8: f85d 7b04 ldr.w r7, [sp], #4
80013ec: 4770 bx lr
80013ee: bf00 nop
80013f0: 40021000 .word 0x40021000
80013f4: 40010000 .word 0x40010000
80013f8: 48000400 .word 0x48000400
80013fc: 48000800 .word 0x48000800
8001400: 48000c00 .word 0x48000c00
8001404: 48001000 .word 0x48001000
8001408: 48001400 .word 0x48001400
800140c: 48001800 .word 0x48001800
8001410: 40010400 .word 0x40010400
08001414 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8001414: b580 push {r7, lr}
8001416: b082 sub sp, #8
8001418: af00 add r7, sp, #0
800141a: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
800141c: 687b ldr r3, [r7, #4]
800141e: 2b00 cmp r3, #0
8001420: d101 bne.n 8001426 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8001422: 2301 movs r3, #1
8001424: e08d b.n 8001542 <HAL_I2C_Init+0x12e>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8001426: 687b ldr r3, [r7, #4]
8001428: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800142c: b2db uxtb r3, r3
800142e: 2b00 cmp r3, #0
8001430: d106 bne.n 8001440 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8001432: 687b ldr r3, [r7, #4]
8001434: 2200 movs r2, #0
8001436: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
800143a: 6878 ldr r0, [r7, #4]
800143c: f7ff fb0c bl 8000a58 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8001440: 687b ldr r3, [r7, #4]
8001442: 2224 movs r2, #36 @ 0x24
8001444: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001448: 687b ldr r3, [r7, #4]
800144a: 681b ldr r3, [r3, #0]
800144c: 681a ldr r2, [r3, #0]
800144e: 687b ldr r3, [r7, #4]
8001450: 681b ldr r3, [r3, #0]
8001452: f022 0201 bic.w r2, r2, #1
8001456: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8001458: 687b ldr r3, [r7, #4]
800145a: 685a ldr r2, [r3, #4]
800145c: 687b ldr r3, [r7, #4]
800145e: 681b ldr r3, [r3, #0]
8001460: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
8001464: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8001466: 687b ldr r3, [r7, #4]
8001468: 681b ldr r3, [r3, #0]
800146a: 689a ldr r2, [r3, #8]
800146c: 687b ldr r3, [r7, #4]
800146e: 681b ldr r3, [r3, #0]
8001470: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8001474: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8001476: 687b ldr r3, [r7, #4]
8001478: 68db ldr r3, [r3, #12]
800147a: 2b01 cmp r3, #1
800147c: d107 bne.n 800148e <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
800147e: 687b ldr r3, [r7, #4]
8001480: 689a ldr r2, [r3, #8]
8001482: 687b ldr r3, [r7, #4]
8001484: 681b ldr r3, [r3, #0]
8001486: f442 4200 orr.w r2, r2, #32768 @ 0x8000
800148a: 609a str r2, [r3, #8]
800148c: e006 b.n 800149c <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
800148e: 687b ldr r3, [r7, #4]
8001490: 689a ldr r2, [r3, #8]
8001492: 687b ldr r3, [r7, #4]
8001494: 681b ldr r3, [r3, #0]
8001496: f442 4204 orr.w r2, r2, #33792 @ 0x8400
800149a: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
800149c: 687b ldr r3, [r7, #4]
800149e: 68db ldr r3, [r3, #12]
80014a0: 2b02 cmp r3, #2
80014a2: d108 bne.n 80014b6 <HAL_I2C_Init+0xa2>
{
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
80014a4: 687b ldr r3, [r7, #4]
80014a6: 681b ldr r3, [r3, #0]
80014a8: 685a ldr r2, [r3, #4]
80014aa: 687b ldr r3, [r7, #4]
80014ac: 681b ldr r3, [r3, #0]
80014ae: f442 6200 orr.w r2, r2, #2048 @ 0x800
80014b2: 605a str r2, [r3, #4]
80014b4: e007 b.n 80014c6 <HAL_I2C_Init+0xb2>
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
80014b6: 687b ldr r3, [r7, #4]
80014b8: 681b ldr r3, [r3, #0]
80014ba: 685a ldr r2, [r3, #4]
80014bc: 687b ldr r3, [r7, #4]
80014be: 681b ldr r3, [r3, #0]
80014c0: f422 6200 bic.w r2, r2, #2048 @ 0x800
80014c4: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
80014c6: 687b ldr r3, [r7, #4]
80014c8: 681b ldr r3, [r3, #0]
80014ca: 685b ldr r3, [r3, #4]
80014cc: 687a ldr r2, [r7, #4]
80014ce: 6812 ldr r2, [r2, #0]
80014d0: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
80014d4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80014d8: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
80014da: 687b ldr r3, [r7, #4]
80014dc: 681b ldr r3, [r3, #0]
80014de: 68da ldr r2, [r3, #12]
80014e0: 687b ldr r3, [r7, #4]
80014e2: 681b ldr r3, [r3, #0]
80014e4: f422 4200 bic.w r2, r2, #32768 @ 0x8000
80014e8: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
80014ea: 687b ldr r3, [r7, #4]
80014ec: 691a ldr r2, [r3, #16]
80014ee: 687b ldr r3, [r7, #4]
80014f0: 695b ldr r3, [r3, #20]
80014f2: ea42 0103 orr.w r1, r2, r3
(hi2c->Init.OwnAddress2Masks << 8));
80014f6: 687b ldr r3, [r7, #4]
80014f8: 699b ldr r3, [r3, #24]
80014fa: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
80014fc: 687b ldr r3, [r7, #4]
80014fe: 681b ldr r3, [r3, #0]
8001500: 430a orrs r2, r1
8001502: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8001504: 687b ldr r3, [r7, #4]
8001506: 69d9 ldr r1, [r3, #28]
8001508: 687b ldr r3, [r7, #4]
800150a: 6a1a ldr r2, [r3, #32]
800150c: 687b ldr r3, [r7, #4]
800150e: 681b ldr r3, [r3, #0]
8001510: 430a orrs r2, r1
8001512: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8001514: 687b ldr r3, [r7, #4]
8001516: 681b ldr r3, [r3, #0]
8001518: 681a ldr r2, [r3, #0]
800151a: 687b ldr r3, [r7, #4]
800151c: 681b ldr r3, [r3, #0]
800151e: f042 0201 orr.w r2, r2, #1
8001522: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001524: 687b ldr r3, [r7, #4]
8001526: 2200 movs r2, #0
8001528: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
800152a: 687b ldr r3, [r7, #4]
800152c: 2220 movs r2, #32
800152e: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8001532: 687b ldr r3, [r7, #4]
8001534: 2200 movs r2, #0
8001536: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8001538: 687b ldr r3, [r7, #4]
800153a: 2200 movs r2, #0
800153c: f883 2042 strb.w r2, [r3, #66] @ 0x42
return HAL_OK;
8001540: 2300 movs r3, #0
}
8001542: 4618 mov r0, r3
8001544: 3708 adds r7, #8
8001546: 46bd mov sp, r7
8001548: bd80 pop {r7, pc}
...
0800154c <HAL_I2C_Mem_Write>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800154c: b580 push {r7, lr}
800154e: b088 sub sp, #32
8001550: af02 add r7, sp, #8
8001552: 60f8 str r0, [r7, #12]
8001554: 4608 mov r0, r1
8001556: 4611 mov r1, r2
8001558: 461a mov r2, r3
800155a: 4603 mov r3, r0
800155c: 817b strh r3, [r7, #10]
800155e: 460b mov r3, r1
8001560: 813b strh r3, [r7, #8]
8001562: 4613 mov r3, r2
8001564: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
8001566: 68fb ldr r3, [r7, #12]
8001568: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800156c: b2db uxtb r3, r3
800156e: 2b20 cmp r3, #32
8001570: f040 80f9 bne.w 8001766 <HAL_I2C_Mem_Write+0x21a>
{
if ((pData == NULL) || (Size == 0U))
8001574: 6a3b ldr r3, [r7, #32]
8001576: 2b00 cmp r3, #0
8001578: d002 beq.n 8001580 <HAL_I2C_Mem_Write+0x34>
800157a: 8cbb ldrh r3, [r7, #36] @ 0x24
800157c: 2b00 cmp r3, #0
800157e: d105 bne.n 800158c <HAL_I2C_Mem_Write+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8001580: 68fb ldr r3, [r7, #12]
8001582: f44f 7200 mov.w r2, #512 @ 0x200
8001586: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
8001588: 2301 movs r3, #1
800158a: e0ed b.n 8001768 <HAL_I2C_Mem_Write+0x21c>
}
/* Process Locked */
__HAL_LOCK(hi2c);
800158c: 68fb ldr r3, [r7, #12]
800158e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8001592: 2b01 cmp r3, #1
8001594: d101 bne.n 800159a <HAL_I2C_Mem_Write+0x4e>
8001596: 2302 movs r3, #2
8001598: e0e6 b.n 8001768 <HAL_I2C_Mem_Write+0x21c>
800159a: 68fb ldr r3, [r7, #12]
800159c: 2201 movs r2, #1
800159e: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
80015a2: f7ff fc77 bl 8000e94 <HAL_GetTick>
80015a6: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
80015a8: 697b ldr r3, [r7, #20]
80015aa: 9300 str r3, [sp, #0]
80015ac: 2319 movs r3, #25
80015ae: 2201 movs r2, #1
80015b0: f44f 4100 mov.w r1, #32768 @ 0x8000
80015b4: 68f8 ldr r0, [r7, #12]
80015b6: f000 fac3 bl 8001b40 <I2C_WaitOnFlagUntilTimeout>
80015ba: 4603 mov r3, r0
80015bc: 2b00 cmp r3, #0
80015be: d001 beq.n 80015c4 <HAL_I2C_Mem_Write+0x78>
{
return HAL_ERROR;
80015c0: 2301 movs r3, #1
80015c2: e0d1 b.n 8001768 <HAL_I2C_Mem_Write+0x21c>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
80015c4: 68fb ldr r3, [r7, #12]
80015c6: 2221 movs r2, #33 @ 0x21
80015c8: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
80015cc: 68fb ldr r3, [r7, #12]
80015ce: 2240 movs r2, #64 @ 0x40
80015d0: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80015d4: 68fb ldr r3, [r7, #12]
80015d6: 2200 movs r2, #0
80015d8: 645a str r2, [r3, #68] @ 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80015da: 68fb ldr r3, [r7, #12]
80015dc: 6a3a ldr r2, [r7, #32]
80015de: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
80015e0: 68fb ldr r3, [r7, #12]
80015e2: 8cba ldrh r2, [r7, #36] @ 0x24
80015e4: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferISR = NULL;
80015e6: 68fb ldr r3, [r7, #12]
80015e8: 2200 movs r2, #0
80015ea: 635a str r2, [r3, #52] @ 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
80015ec: 88f8 ldrh r0, [r7, #6]
80015ee: 893a ldrh r2, [r7, #8]
80015f0: 8979 ldrh r1, [r7, #10]
80015f2: 697b ldr r3, [r7, #20]
80015f4: 9301 str r3, [sp, #4]
80015f6: 6abb ldr r3, [r7, #40] @ 0x28
80015f8: 9300 str r3, [sp, #0]
80015fa: 4603 mov r3, r0
80015fc: 68f8 ldr r0, [r7, #12]
80015fe: f000 f9d3 bl 80019a8 <I2C_RequestMemoryWrite>
8001602: 4603 mov r3, r0
8001604: 2b00 cmp r3, #0
8001606: d005 beq.n 8001614 <HAL_I2C_Mem_Write+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001608: 68fb ldr r3, [r7, #12]
800160a: 2200 movs r2, #0
800160c: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8001610: 2301 movs r3, #1
8001612: e0a9 b.n 8001768 <HAL_I2C_Mem_Write+0x21c>
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8001614: 68fb ldr r3, [r7, #12]
8001616: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001618: b29b uxth r3, r3
800161a: 2bff cmp r3, #255 @ 0xff
800161c: d90e bls.n 800163c <HAL_I2C_Mem_Write+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
800161e: 68fb ldr r3, [r7, #12]
8001620: 22ff movs r2, #255 @ 0xff
8001622: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
8001624: 68fb ldr r3, [r7, #12]
8001626: 8d1b ldrh r3, [r3, #40] @ 0x28
8001628: b2da uxtb r2, r3
800162a: 8979 ldrh r1, [r7, #10]
800162c: 2300 movs r3, #0
800162e: 9300 str r3, [sp, #0]
8001630: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8001634: 68f8 ldr r0, [r7, #12]
8001636: f000 fc47 bl 8001ec8 <I2C_TransferConfig>
800163a: e00f b.n 800165c <HAL_I2C_Mem_Write+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
800163c: 68fb ldr r3, [r7, #12]
800163e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001640: b29a uxth r2, r3
8001642: 68fb ldr r3, [r7, #12]
8001644: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
8001646: 68fb ldr r3, [r7, #12]
8001648: 8d1b ldrh r3, [r3, #40] @ 0x28
800164a: b2da uxtb r2, r3
800164c: 8979 ldrh r1, [r7, #10]
800164e: 2300 movs r3, #0
8001650: 9300 str r3, [sp, #0]
8001652: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8001656: 68f8 ldr r0, [r7, #12]
8001658: f000 fc36 bl 8001ec8 <I2C_TransferConfig>
}
do
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800165c: 697a ldr r2, [r7, #20]
800165e: 6ab9 ldr r1, [r7, #40] @ 0x28
8001660: 68f8 ldr r0, [r7, #12]
8001662: f000 fac6 bl 8001bf2 <I2C_WaitOnTXISFlagUntilTimeout>
8001666: 4603 mov r3, r0
8001668: 2b00 cmp r3, #0
800166a: d001 beq.n 8001670 <HAL_I2C_Mem_Write+0x124>
{
return HAL_ERROR;
800166c: 2301 movs r3, #1
800166e: e07b b.n 8001768 <HAL_I2C_Mem_Write+0x21c>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8001670: 68fb ldr r3, [r7, #12]
8001672: 6a5b ldr r3, [r3, #36] @ 0x24
8001674: 781a ldrb r2, [r3, #0]
8001676: 68fb ldr r3, [r7, #12]
8001678: 681b ldr r3, [r3, #0]
800167a: 629a str r2, [r3, #40] @ 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800167c: 68fb ldr r3, [r7, #12]
800167e: 6a5b ldr r3, [r3, #36] @ 0x24
8001680: 1c5a adds r2, r3, #1
8001682: 68fb ldr r3, [r7, #12]
8001684: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount--;
8001686: 68fb ldr r3, [r7, #12]
8001688: 8d5b ldrh r3, [r3, #42] @ 0x2a
800168a: b29b uxth r3, r3
800168c: 3b01 subs r3, #1
800168e: b29a uxth r2, r3
8001690: 68fb ldr r3, [r7, #12]
8001692: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8001694: 68fb ldr r3, [r7, #12]
8001696: 8d1b ldrh r3, [r3, #40] @ 0x28
8001698: 3b01 subs r3, #1
800169a: b29a uxth r2, r3
800169c: 68fb ldr r3, [r7, #12]
800169e: 851a strh r2, [r3, #40] @ 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
80016a0: 68fb ldr r3, [r7, #12]
80016a2: 8d5b ldrh r3, [r3, #42] @ 0x2a
80016a4: b29b uxth r3, r3
80016a6: 2b00 cmp r3, #0
80016a8: d034 beq.n 8001714 <HAL_I2C_Mem_Write+0x1c8>
80016aa: 68fb ldr r3, [r7, #12]
80016ac: 8d1b ldrh r3, [r3, #40] @ 0x28
80016ae: 2b00 cmp r3, #0
80016b0: d130 bne.n 8001714 <HAL_I2C_Mem_Write+0x1c8>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
80016b2: 697b ldr r3, [r7, #20]
80016b4: 9300 str r3, [sp, #0]
80016b6: 6abb ldr r3, [r7, #40] @ 0x28
80016b8: 2200 movs r2, #0
80016ba: 2180 movs r1, #128 @ 0x80
80016bc: 68f8 ldr r0, [r7, #12]
80016be: f000 fa3f bl 8001b40 <I2C_WaitOnFlagUntilTimeout>
80016c2: 4603 mov r3, r0
80016c4: 2b00 cmp r3, #0
80016c6: d001 beq.n 80016cc <HAL_I2C_Mem_Write+0x180>
{
return HAL_ERROR;
80016c8: 2301 movs r3, #1
80016ca: e04d b.n 8001768 <HAL_I2C_Mem_Write+0x21c>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80016cc: 68fb ldr r3, [r7, #12]
80016ce: 8d5b ldrh r3, [r3, #42] @ 0x2a
80016d0: b29b uxth r3, r3
80016d2: 2bff cmp r3, #255 @ 0xff
80016d4: d90e bls.n 80016f4 <HAL_I2C_Mem_Write+0x1a8>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80016d6: 68fb ldr r3, [r7, #12]
80016d8: 22ff movs r2, #255 @ 0xff
80016da: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
80016dc: 68fb ldr r3, [r7, #12]
80016de: 8d1b ldrh r3, [r3, #40] @ 0x28
80016e0: b2da uxtb r2, r3
80016e2: 8979 ldrh r1, [r7, #10]
80016e4: 2300 movs r3, #0
80016e6: 9300 str r3, [sp, #0]
80016e8: f04f 7380 mov.w r3, #16777216 @ 0x1000000
80016ec: 68f8 ldr r0, [r7, #12]
80016ee: f000 fbeb bl 8001ec8 <I2C_TransferConfig>
80016f2: e00f b.n 8001714 <HAL_I2C_Mem_Write+0x1c8>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
80016f4: 68fb ldr r3, [r7, #12]
80016f6: 8d5b ldrh r3, [r3, #42] @ 0x2a
80016f8: b29a uxth r2, r3
80016fa: 68fb ldr r3, [r7, #12]
80016fc: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
80016fe: 68fb ldr r3, [r7, #12]
8001700: 8d1b ldrh r3, [r3, #40] @ 0x28
8001702: b2da uxtb r2, r3
8001704: 8979 ldrh r1, [r7, #10]
8001706: 2300 movs r3, #0
8001708: 9300 str r3, [sp, #0]
800170a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
800170e: 68f8 ldr r0, [r7, #12]
8001710: f000 fbda bl 8001ec8 <I2C_TransferConfig>
I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
8001714: 68fb ldr r3, [r7, #12]
8001716: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001718: b29b uxth r3, r3
800171a: 2b00 cmp r3, #0
800171c: d19e bne.n 800165c <HAL_I2C_Mem_Write+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800171e: 697a ldr r2, [r7, #20]
8001720: 6ab9 ldr r1, [r7, #40] @ 0x28
8001722: 68f8 ldr r0, [r7, #12]
8001724: f000 faac bl 8001c80 <I2C_WaitOnSTOPFlagUntilTimeout>
8001728: 4603 mov r3, r0
800172a: 2b00 cmp r3, #0
800172c: d001 beq.n 8001732 <HAL_I2C_Mem_Write+0x1e6>
{
return HAL_ERROR;
800172e: 2301 movs r3, #1
8001730: e01a b.n 8001768 <HAL_I2C_Mem_Write+0x21c>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8001732: 68fb ldr r3, [r7, #12]
8001734: 681b ldr r3, [r3, #0]
8001736: 2220 movs r2, #32
8001738: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
800173a: 68fb ldr r3, [r7, #12]
800173c: 681b ldr r3, [r3, #0]
800173e: 6859 ldr r1, [r3, #4]
8001740: 68fb ldr r3, [r7, #12]
8001742: 681a ldr r2, [r3, #0]
8001744: 4b0a ldr r3, [pc, #40] @ (8001770 <HAL_I2C_Mem_Write+0x224>)
8001746: 400b ands r3, r1
8001748: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
800174a: 68fb ldr r3, [r7, #12]
800174c: 2220 movs r2, #32
800174e: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001752: 68fb ldr r3, [r7, #12]
8001754: 2200 movs r2, #0
8001756: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800175a: 68fb ldr r3, [r7, #12]
800175c: 2200 movs r2, #0
800175e: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8001762: 2300 movs r3, #0
8001764: e000 b.n 8001768 <HAL_I2C_Mem_Write+0x21c>
}
else
{
return HAL_BUSY;
8001766: 2302 movs r3, #2
}
}
8001768: 4618 mov r0, r3
800176a: 3718 adds r7, #24
800176c: 46bd mov sp, r7
800176e: bd80 pop {r7, pc}
8001770: fe00e800 .word 0xfe00e800
08001774 <HAL_I2C_Mem_Read>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8001774: b580 push {r7, lr}
8001776: b088 sub sp, #32
8001778: af02 add r7, sp, #8
800177a: 60f8 str r0, [r7, #12]
800177c: 4608 mov r0, r1
800177e: 4611 mov r1, r2
8001780: 461a mov r2, r3
8001782: 4603 mov r3, r0
8001784: 817b strh r3, [r7, #10]
8001786: 460b mov r3, r1
8001788: 813b strh r3, [r7, #8]
800178a: 4613 mov r3, r2
800178c: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
800178e: 68fb ldr r3, [r7, #12]
8001790: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8001794: b2db uxtb r3, r3
8001796: 2b20 cmp r3, #32
8001798: f040 80fd bne.w 8001996 <HAL_I2C_Mem_Read+0x222>
{
if ((pData == NULL) || (Size == 0U))
800179c: 6a3b ldr r3, [r7, #32]
800179e: 2b00 cmp r3, #0
80017a0: d002 beq.n 80017a8 <HAL_I2C_Mem_Read+0x34>
80017a2: 8cbb ldrh r3, [r7, #36] @ 0x24
80017a4: 2b00 cmp r3, #0
80017a6: d105 bne.n 80017b4 <HAL_I2C_Mem_Read+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
80017a8: 68fb ldr r3, [r7, #12]
80017aa: f44f 7200 mov.w r2, #512 @ 0x200
80017ae: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
80017b0: 2301 movs r3, #1
80017b2: e0f1 b.n 8001998 <HAL_I2C_Mem_Read+0x224>
}
/* Process Locked */
__HAL_LOCK(hi2c);
80017b4: 68fb ldr r3, [r7, #12]
80017b6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80017ba: 2b01 cmp r3, #1
80017bc: d101 bne.n 80017c2 <HAL_I2C_Mem_Read+0x4e>
80017be: 2302 movs r3, #2
80017c0: e0ea b.n 8001998 <HAL_I2C_Mem_Read+0x224>
80017c2: 68fb ldr r3, [r7, #12]
80017c4: 2201 movs r2, #1
80017c6: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
80017ca: f7ff fb63 bl 8000e94 <HAL_GetTick>
80017ce: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
80017d0: 697b ldr r3, [r7, #20]
80017d2: 9300 str r3, [sp, #0]
80017d4: 2319 movs r3, #25
80017d6: 2201 movs r2, #1
80017d8: f44f 4100 mov.w r1, #32768 @ 0x8000
80017dc: 68f8 ldr r0, [r7, #12]
80017de: f000 f9af bl 8001b40 <I2C_WaitOnFlagUntilTimeout>
80017e2: 4603 mov r3, r0
80017e4: 2b00 cmp r3, #0
80017e6: d001 beq.n 80017ec <HAL_I2C_Mem_Read+0x78>
{
return HAL_ERROR;
80017e8: 2301 movs r3, #1
80017ea: e0d5 b.n 8001998 <HAL_I2C_Mem_Read+0x224>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
80017ec: 68fb ldr r3, [r7, #12]
80017ee: 2222 movs r2, #34 @ 0x22
80017f0: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
80017f4: 68fb ldr r3, [r7, #12]
80017f6: 2240 movs r2, #64 @ 0x40
80017f8: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80017fc: 68fb ldr r3, [r7, #12]
80017fe: 2200 movs r2, #0
8001800: 645a str r2, [r3, #68] @ 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8001802: 68fb ldr r3, [r7, #12]
8001804: 6a3a ldr r2, [r7, #32]
8001806: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8001808: 68fb ldr r3, [r7, #12]
800180a: 8cba ldrh r2, [r7, #36] @ 0x24
800180c: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferISR = NULL;
800180e: 68fb ldr r3, [r7, #12]
8001810: 2200 movs r2, #0
8001812: 635a str r2, [r3, #52] @ 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
8001814: 88f8 ldrh r0, [r7, #6]
8001816: 893a ldrh r2, [r7, #8]
8001818: 8979 ldrh r1, [r7, #10]
800181a: 697b ldr r3, [r7, #20]
800181c: 9301 str r3, [sp, #4]
800181e: 6abb ldr r3, [r7, #40] @ 0x28
8001820: 9300 str r3, [sp, #0]
8001822: 4603 mov r3, r0
8001824: 68f8 ldr r0, [r7, #12]
8001826: f000 f913 bl 8001a50 <I2C_RequestMemoryRead>
800182a: 4603 mov r3, r0
800182c: 2b00 cmp r3, #0
800182e: d005 beq.n 800183c <HAL_I2C_Mem_Read+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001830: 68fb ldr r3, [r7, #12]
8001832: 2200 movs r2, #0
8001834: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8001838: 2301 movs r3, #1
800183a: e0ad b.n 8001998 <HAL_I2C_Mem_Read+0x224>
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
800183c: 68fb ldr r3, [r7, #12]
800183e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001840: b29b uxth r3, r3
8001842: 2bff cmp r3, #255 @ 0xff
8001844: d90e bls.n 8001864 <HAL_I2C_Mem_Read+0xf0>
{
hi2c->XferSize = 1U;
8001846: 68fb ldr r3, [r7, #12]
8001848: 2201 movs r2, #1
800184a: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
800184c: 68fb ldr r3, [r7, #12]
800184e: 8d1b ldrh r3, [r3, #40] @ 0x28
8001850: b2da uxtb r2, r3
8001852: 8979 ldrh r1, [r7, #10]
8001854: 4b52 ldr r3, [pc, #328] @ (80019a0 <HAL_I2C_Mem_Read+0x22c>)
8001856: 9300 str r3, [sp, #0]
8001858: f04f 7380 mov.w r3, #16777216 @ 0x1000000
800185c: 68f8 ldr r0, [r7, #12]
800185e: f000 fb33 bl 8001ec8 <I2C_TransferConfig>
8001862: e00f b.n 8001884 <HAL_I2C_Mem_Read+0x110>
I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8001864: 68fb ldr r3, [r7, #12]
8001866: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001868: b29a uxth r2, r3
800186a: 68fb ldr r3, [r7, #12]
800186c: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
800186e: 68fb ldr r3, [r7, #12]
8001870: 8d1b ldrh r3, [r3, #40] @ 0x28
8001872: b2da uxtb r2, r3
8001874: 8979 ldrh r1, [r7, #10]
8001876: 4b4a ldr r3, [pc, #296] @ (80019a0 <HAL_I2C_Mem_Read+0x22c>)
8001878: 9300 str r3, [sp, #0]
800187a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
800187e: 68f8 ldr r0, [r7, #12]
8001880: f000 fb22 bl 8001ec8 <I2C_TransferConfig>
}
do
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
8001884: 697b ldr r3, [r7, #20]
8001886: 9300 str r3, [sp, #0]
8001888: 6abb ldr r3, [r7, #40] @ 0x28
800188a: 2200 movs r2, #0
800188c: 2104 movs r1, #4
800188e: 68f8 ldr r0, [r7, #12]
8001890: f000 f956 bl 8001b40 <I2C_WaitOnFlagUntilTimeout>
8001894: 4603 mov r3, r0
8001896: 2b00 cmp r3, #0
8001898: d001 beq.n 800189e <HAL_I2C_Mem_Read+0x12a>
{
return HAL_ERROR;
800189a: 2301 movs r3, #1
800189c: e07c b.n 8001998 <HAL_I2C_Mem_Read+0x224>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
800189e: 68fb ldr r3, [r7, #12]
80018a0: 681b ldr r3, [r3, #0]
80018a2: 6a5a ldr r2, [r3, #36] @ 0x24
80018a4: 68fb ldr r3, [r7, #12]
80018a6: 6a5b ldr r3, [r3, #36] @ 0x24
80018a8: b2d2 uxtb r2, r2
80018aa: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80018ac: 68fb ldr r3, [r7, #12]
80018ae: 6a5b ldr r3, [r3, #36] @ 0x24
80018b0: 1c5a adds r2, r3, #1
80018b2: 68fb ldr r3, [r7, #12]
80018b4: 625a str r2, [r3, #36] @ 0x24
hi2c->XferSize--;
80018b6: 68fb ldr r3, [r7, #12]
80018b8: 8d1b ldrh r3, [r3, #40] @ 0x28
80018ba: 3b01 subs r3, #1
80018bc: b29a uxth r2, r3
80018be: 68fb ldr r3, [r7, #12]
80018c0: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80018c2: 68fb ldr r3, [r7, #12]
80018c4: 8d5b ldrh r3, [r3, #42] @ 0x2a
80018c6: b29b uxth r3, r3
80018c8: 3b01 subs r3, #1
80018ca: b29a uxth r2, r3
80018cc: 68fb ldr r3, [r7, #12]
80018ce: 855a strh r2, [r3, #42] @ 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
80018d0: 68fb ldr r3, [r7, #12]
80018d2: 8d5b ldrh r3, [r3, #42] @ 0x2a
80018d4: b29b uxth r3, r3
80018d6: 2b00 cmp r3, #0
80018d8: d034 beq.n 8001944 <HAL_I2C_Mem_Read+0x1d0>
80018da: 68fb ldr r3, [r7, #12]
80018dc: 8d1b ldrh r3, [r3, #40] @ 0x28
80018de: 2b00 cmp r3, #0
80018e0: d130 bne.n 8001944 <HAL_I2C_Mem_Read+0x1d0>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
80018e2: 697b ldr r3, [r7, #20]
80018e4: 9300 str r3, [sp, #0]
80018e6: 6abb ldr r3, [r7, #40] @ 0x28
80018e8: 2200 movs r2, #0
80018ea: 2180 movs r1, #128 @ 0x80
80018ec: 68f8 ldr r0, [r7, #12]
80018ee: f000 f927 bl 8001b40 <I2C_WaitOnFlagUntilTimeout>
80018f2: 4603 mov r3, r0
80018f4: 2b00 cmp r3, #0
80018f6: d001 beq.n 80018fc <HAL_I2C_Mem_Read+0x188>
{
return HAL_ERROR;
80018f8: 2301 movs r3, #1
80018fa: e04d b.n 8001998 <HAL_I2C_Mem_Read+0x224>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80018fc: 68fb ldr r3, [r7, #12]
80018fe: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001900: b29b uxth r3, r3
8001902: 2bff cmp r3, #255 @ 0xff
8001904: d90e bls.n 8001924 <HAL_I2C_Mem_Read+0x1b0>
{
hi2c->XferSize = 1U;
8001906: 68fb ldr r3, [r7, #12]
8001908: 2201 movs r2, #1
800190a: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
800190c: 68fb ldr r3, [r7, #12]
800190e: 8d1b ldrh r3, [r3, #40] @ 0x28
8001910: b2da uxtb r2, r3
8001912: 8979 ldrh r1, [r7, #10]
8001914: 2300 movs r3, #0
8001916: 9300 str r3, [sp, #0]
8001918: f04f 7380 mov.w r3, #16777216 @ 0x1000000
800191c: 68f8 ldr r0, [r7, #12]
800191e: f000 fad3 bl 8001ec8 <I2C_TransferConfig>
8001922: e00f b.n 8001944 <HAL_I2C_Mem_Read+0x1d0>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8001924: 68fb ldr r3, [r7, #12]
8001926: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001928: b29a uxth r2, r3
800192a: 68fb ldr r3, [r7, #12]
800192c: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
800192e: 68fb ldr r3, [r7, #12]
8001930: 8d1b ldrh r3, [r3, #40] @ 0x28
8001932: b2da uxtb r2, r3
8001934: 8979 ldrh r1, [r7, #10]
8001936: 2300 movs r3, #0
8001938: 9300 str r3, [sp, #0]
800193a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
800193e: 68f8 ldr r0, [r7, #12]
8001940: f000 fac2 bl 8001ec8 <I2C_TransferConfig>
I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
8001944: 68fb ldr r3, [r7, #12]
8001946: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001948: b29b uxth r3, r3
800194a: 2b00 cmp r3, #0
800194c: d19a bne.n 8001884 <HAL_I2C_Mem_Read+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800194e: 697a ldr r2, [r7, #20]
8001950: 6ab9 ldr r1, [r7, #40] @ 0x28
8001952: 68f8 ldr r0, [r7, #12]
8001954: f000 f994 bl 8001c80 <I2C_WaitOnSTOPFlagUntilTimeout>
8001958: 4603 mov r3, r0
800195a: 2b00 cmp r3, #0
800195c: d001 beq.n 8001962 <HAL_I2C_Mem_Read+0x1ee>
{
return HAL_ERROR;
800195e: 2301 movs r3, #1
8001960: e01a b.n 8001998 <HAL_I2C_Mem_Read+0x224>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8001962: 68fb ldr r3, [r7, #12]
8001964: 681b ldr r3, [r3, #0]
8001966: 2220 movs r2, #32
8001968: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
800196a: 68fb ldr r3, [r7, #12]
800196c: 681b ldr r3, [r3, #0]
800196e: 6859 ldr r1, [r3, #4]
8001970: 68fb ldr r3, [r7, #12]
8001972: 681a ldr r2, [r3, #0]
8001974: 4b0b ldr r3, [pc, #44] @ (80019a4 <HAL_I2C_Mem_Read+0x230>)
8001976: 400b ands r3, r1
8001978: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
800197a: 68fb ldr r3, [r7, #12]
800197c: 2220 movs r2, #32
800197e: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001982: 68fb ldr r3, [r7, #12]
8001984: 2200 movs r2, #0
8001986: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800198a: 68fb ldr r3, [r7, #12]
800198c: 2200 movs r2, #0
800198e: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8001992: 2300 movs r3, #0
8001994: e000 b.n 8001998 <HAL_I2C_Mem_Read+0x224>
}
else
{
return HAL_BUSY;
8001996: 2302 movs r3, #2
}
}
8001998: 4618 mov r0, r3
800199a: 3718 adds r7, #24
800199c: 46bd mov sp, r7
800199e: bd80 pop {r7, pc}
80019a0: 80002400 .word 0x80002400
80019a4: fe00e800 .word 0xfe00e800
080019a8 <I2C_RequestMemoryWrite>:
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
80019a8: b580 push {r7, lr}
80019aa: b086 sub sp, #24
80019ac: af02 add r7, sp, #8
80019ae: 60f8 str r0, [r7, #12]
80019b0: 4608 mov r0, r1
80019b2: 4611 mov r1, r2
80019b4: 461a mov r2, r3
80019b6: 4603 mov r3, r0
80019b8: 817b strh r3, [r7, #10]
80019ba: 460b mov r3, r1
80019bc: 813b strh r3, [r7, #8]
80019be: 4613 mov r3, r2
80019c0: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
80019c2: 88fb ldrh r3, [r7, #6]
80019c4: b2da uxtb r2, r3
80019c6: 8979 ldrh r1, [r7, #10]
80019c8: 4b20 ldr r3, [pc, #128] @ (8001a4c <I2C_RequestMemoryWrite+0xa4>)
80019ca: 9300 str r3, [sp, #0]
80019cc: f04f 7380 mov.w r3, #16777216 @ 0x1000000
80019d0: 68f8 ldr r0, [r7, #12]
80019d2: f000 fa79 bl 8001ec8 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
80019d6: 69fa ldr r2, [r7, #28]
80019d8: 69b9 ldr r1, [r7, #24]
80019da: 68f8 ldr r0, [r7, #12]
80019dc: f000 f909 bl 8001bf2 <I2C_WaitOnTXISFlagUntilTimeout>
80019e0: 4603 mov r3, r0
80019e2: 2b00 cmp r3, #0
80019e4: d001 beq.n 80019ea <I2C_RequestMemoryWrite+0x42>
{
return HAL_ERROR;
80019e6: 2301 movs r3, #1
80019e8: e02c b.n 8001a44 <I2C_RequestMemoryWrite+0x9c>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
80019ea: 88fb ldrh r3, [r7, #6]
80019ec: 2b01 cmp r3, #1
80019ee: d105 bne.n 80019fc <I2C_RequestMemoryWrite+0x54>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
80019f0: 893b ldrh r3, [r7, #8]
80019f2: b2da uxtb r2, r3
80019f4: 68fb ldr r3, [r7, #12]
80019f6: 681b ldr r3, [r3, #0]
80019f8: 629a str r2, [r3, #40] @ 0x28
80019fa: e015 b.n 8001a28 <I2C_RequestMemoryWrite+0x80>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
80019fc: 893b ldrh r3, [r7, #8]
80019fe: 0a1b lsrs r3, r3, #8
8001a00: b29b uxth r3, r3
8001a02: b2da uxtb r2, r3
8001a04: 68fb ldr r3, [r7, #12]
8001a06: 681b ldr r3, [r3, #0]
8001a08: 629a str r2, [r3, #40] @ 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8001a0a: 69fa ldr r2, [r7, #28]
8001a0c: 69b9 ldr r1, [r7, #24]
8001a0e: 68f8 ldr r0, [r7, #12]
8001a10: f000 f8ef bl 8001bf2 <I2C_WaitOnTXISFlagUntilTimeout>
8001a14: 4603 mov r3, r0
8001a16: 2b00 cmp r3, #0
8001a18: d001 beq.n 8001a1e <I2C_RequestMemoryWrite+0x76>
{
return HAL_ERROR;
8001a1a: 2301 movs r3, #1
8001a1c: e012 b.n 8001a44 <I2C_RequestMemoryWrite+0x9c>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8001a1e: 893b ldrh r3, [r7, #8]
8001a20: b2da uxtb r2, r3
8001a22: 68fb ldr r3, [r7, #12]
8001a24: 681b ldr r3, [r3, #0]
8001a26: 629a str r2, [r3, #40] @ 0x28
}
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
8001a28: 69fb ldr r3, [r7, #28]
8001a2a: 9300 str r3, [sp, #0]
8001a2c: 69bb ldr r3, [r7, #24]
8001a2e: 2200 movs r2, #0
8001a30: 2180 movs r1, #128 @ 0x80
8001a32: 68f8 ldr r0, [r7, #12]
8001a34: f000 f884 bl 8001b40 <I2C_WaitOnFlagUntilTimeout>
8001a38: 4603 mov r3, r0
8001a3a: 2b00 cmp r3, #0
8001a3c: d001 beq.n 8001a42 <I2C_RequestMemoryWrite+0x9a>
{
return HAL_ERROR;
8001a3e: 2301 movs r3, #1
8001a40: e000 b.n 8001a44 <I2C_RequestMemoryWrite+0x9c>
}
return HAL_OK;
8001a42: 2300 movs r3, #0
}
8001a44: 4618 mov r0, r3
8001a46: 3710 adds r7, #16
8001a48: 46bd mov sp, r7
8001a4a: bd80 pop {r7, pc}
8001a4c: 80002000 .word 0x80002000
08001a50 <I2C_RequestMemoryRead>:
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
8001a50: b580 push {r7, lr}
8001a52: b086 sub sp, #24
8001a54: af02 add r7, sp, #8
8001a56: 60f8 str r0, [r7, #12]
8001a58: 4608 mov r0, r1
8001a5a: 4611 mov r1, r2
8001a5c: 461a mov r2, r3
8001a5e: 4603 mov r3, r0
8001a60: 817b strh r3, [r7, #10]
8001a62: 460b mov r3, r1
8001a64: 813b strh r3, [r7, #8]
8001a66: 4613 mov r3, r2
8001a68: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
8001a6a: 88fb ldrh r3, [r7, #6]
8001a6c: b2da uxtb r2, r3
8001a6e: 8979 ldrh r1, [r7, #10]
8001a70: 4b20 ldr r3, [pc, #128] @ (8001af4 <I2C_RequestMemoryRead+0xa4>)
8001a72: 9300 str r3, [sp, #0]
8001a74: 2300 movs r3, #0
8001a76: 68f8 ldr r0, [r7, #12]
8001a78: f000 fa26 bl 8001ec8 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8001a7c: 69fa ldr r2, [r7, #28]
8001a7e: 69b9 ldr r1, [r7, #24]
8001a80: 68f8 ldr r0, [r7, #12]
8001a82: f000 f8b6 bl 8001bf2 <I2C_WaitOnTXISFlagUntilTimeout>
8001a86: 4603 mov r3, r0
8001a88: 2b00 cmp r3, #0
8001a8a: d001 beq.n 8001a90 <I2C_RequestMemoryRead+0x40>
{
return HAL_ERROR;
8001a8c: 2301 movs r3, #1
8001a8e: e02c b.n 8001aea <I2C_RequestMemoryRead+0x9a>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8001a90: 88fb ldrh r3, [r7, #6]
8001a92: 2b01 cmp r3, #1
8001a94: d105 bne.n 8001aa2 <I2C_RequestMemoryRead+0x52>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8001a96: 893b ldrh r3, [r7, #8]
8001a98: b2da uxtb r2, r3
8001a9a: 68fb ldr r3, [r7, #12]
8001a9c: 681b ldr r3, [r3, #0]
8001a9e: 629a str r2, [r3, #40] @ 0x28
8001aa0: e015 b.n 8001ace <I2C_RequestMemoryRead+0x7e>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8001aa2: 893b ldrh r3, [r7, #8]
8001aa4: 0a1b lsrs r3, r3, #8
8001aa6: b29b uxth r3, r3
8001aa8: b2da uxtb r2, r3
8001aaa: 68fb ldr r3, [r7, #12]
8001aac: 681b ldr r3, [r3, #0]
8001aae: 629a str r2, [r3, #40] @ 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8001ab0: 69fa ldr r2, [r7, #28]
8001ab2: 69b9 ldr r1, [r7, #24]
8001ab4: 68f8 ldr r0, [r7, #12]
8001ab6: f000 f89c bl 8001bf2 <I2C_WaitOnTXISFlagUntilTimeout>
8001aba: 4603 mov r3, r0
8001abc: 2b00 cmp r3, #0
8001abe: d001 beq.n 8001ac4 <I2C_RequestMemoryRead+0x74>
{
return HAL_ERROR;
8001ac0: 2301 movs r3, #1
8001ac2: e012 b.n 8001aea <I2C_RequestMemoryRead+0x9a>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8001ac4: 893b ldrh r3, [r7, #8]
8001ac6: b2da uxtb r2, r3
8001ac8: 68fb ldr r3, [r7, #12]
8001aca: 681b ldr r3, [r3, #0]
8001acc: 629a str r2, [r3, #40] @ 0x28
}
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
8001ace: 69fb ldr r3, [r7, #28]
8001ad0: 9300 str r3, [sp, #0]
8001ad2: 69bb ldr r3, [r7, #24]
8001ad4: 2200 movs r2, #0
8001ad6: 2140 movs r1, #64 @ 0x40
8001ad8: 68f8 ldr r0, [r7, #12]
8001ada: f000 f831 bl 8001b40 <I2C_WaitOnFlagUntilTimeout>
8001ade: 4603 mov r3, r0
8001ae0: 2b00 cmp r3, #0
8001ae2: d001 beq.n 8001ae8 <I2C_RequestMemoryRead+0x98>
{
return HAL_ERROR;
8001ae4: 2301 movs r3, #1
8001ae6: e000 b.n 8001aea <I2C_RequestMemoryRead+0x9a>
}
return HAL_OK;
8001ae8: 2300 movs r3, #0
}
8001aea: 4618 mov r0, r3
8001aec: 3710 adds r7, #16
8001aee: 46bd mov sp, r7
8001af0: bd80 pop {r7, pc}
8001af2: bf00 nop
8001af4: 80002000 .word 0x80002000
08001af8 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
8001af8: b480 push {r7}
8001afa: b083 sub sp, #12
8001afc: af00 add r7, sp, #0
8001afe: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
8001b00: 687b ldr r3, [r7, #4]
8001b02: 681b ldr r3, [r3, #0]
8001b04: 699b ldr r3, [r3, #24]
8001b06: f003 0302 and.w r3, r3, #2
8001b0a: 2b02 cmp r3, #2
8001b0c: d103 bne.n 8001b16 <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
8001b0e: 687b ldr r3, [r7, #4]
8001b10: 681b ldr r3, [r3, #0]
8001b12: 2200 movs r2, #0
8001b14: 629a str r2, [r3, #40] @ 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8001b16: 687b ldr r3, [r7, #4]
8001b18: 681b ldr r3, [r3, #0]
8001b1a: 699b ldr r3, [r3, #24]
8001b1c: f003 0301 and.w r3, r3, #1
8001b20: 2b01 cmp r3, #1
8001b22: d007 beq.n 8001b34 <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
8001b24: 687b ldr r3, [r7, #4]
8001b26: 681b ldr r3, [r3, #0]
8001b28: 699a ldr r2, [r3, #24]
8001b2a: 687b ldr r3, [r7, #4]
8001b2c: 681b ldr r3, [r3, #0]
8001b2e: f042 0201 orr.w r2, r2, #1
8001b32: 619a str r2, [r3, #24]
}
}
8001b34: bf00 nop
8001b36: 370c adds r7, #12
8001b38: 46bd mov sp, r7
8001b3a: f85d 7b04 ldr.w r7, [sp], #4
8001b3e: 4770 bx lr
08001b40 <I2C_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
8001b40: b580 push {r7, lr}
8001b42: b084 sub sp, #16
8001b44: af00 add r7, sp, #0
8001b46: 60f8 str r0, [r7, #12]
8001b48: 60b9 str r1, [r7, #8]
8001b4a: 603b str r3, [r7, #0]
8001b4c: 4613 mov r3, r2
8001b4e: 71fb strb r3, [r7, #7]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8001b50: e03b b.n 8001bca <I2C_WaitOnFlagUntilTimeout+0x8a>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
8001b52: 69ba ldr r2, [r7, #24]
8001b54: 6839 ldr r1, [r7, #0]
8001b56: 68f8 ldr r0, [r7, #12]
8001b58: f000 f8d6 bl 8001d08 <I2C_IsErrorOccurred>
8001b5c: 4603 mov r3, r0
8001b5e: 2b00 cmp r3, #0
8001b60: d001 beq.n 8001b66 <I2C_WaitOnFlagUntilTimeout+0x26>
{
return HAL_ERROR;
8001b62: 2301 movs r3, #1
8001b64: e041 b.n 8001bea <I2C_WaitOnFlagUntilTimeout+0xaa>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8001b66: 683b ldr r3, [r7, #0]
8001b68: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8001b6c: d02d beq.n 8001bca <I2C_WaitOnFlagUntilTimeout+0x8a>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8001b6e: f7ff f991 bl 8000e94 <HAL_GetTick>
8001b72: 4602 mov r2, r0
8001b74: 69bb ldr r3, [r7, #24]
8001b76: 1ad3 subs r3, r2, r3
8001b78: 683a ldr r2, [r7, #0]
8001b7a: 429a cmp r2, r3
8001b7c: d302 bcc.n 8001b84 <I2C_WaitOnFlagUntilTimeout+0x44>
8001b7e: 683b ldr r3, [r7, #0]
8001b80: 2b00 cmp r3, #0
8001b82: d122 bne.n 8001bca <I2C_WaitOnFlagUntilTimeout+0x8a>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
8001b84: 68fb ldr r3, [r7, #12]
8001b86: 681b ldr r3, [r3, #0]
8001b88: 699a ldr r2, [r3, #24]
8001b8a: 68bb ldr r3, [r7, #8]
8001b8c: 4013 ands r3, r2
8001b8e: 68ba ldr r2, [r7, #8]
8001b90: 429a cmp r2, r3
8001b92: bf0c ite eq
8001b94: 2301 moveq r3, #1
8001b96: 2300 movne r3, #0
8001b98: b2db uxtb r3, r3
8001b9a: 461a mov r2, r3
8001b9c: 79fb ldrb r3, [r7, #7]
8001b9e: 429a cmp r2, r3
8001ba0: d113 bne.n 8001bca <I2C_WaitOnFlagUntilTimeout+0x8a>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8001ba2: 68fb ldr r3, [r7, #12]
8001ba4: 6c5b ldr r3, [r3, #68] @ 0x44
8001ba6: f043 0220 orr.w r2, r3, #32
8001baa: 68fb ldr r3, [r7, #12]
8001bac: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
8001bae: 68fb ldr r3, [r7, #12]
8001bb0: 2220 movs r2, #32
8001bb2: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001bb6: 68fb ldr r3, [r7, #12]
8001bb8: 2200 movs r2, #0
8001bba: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001bbe: 68fb ldr r3, [r7, #12]
8001bc0: 2200 movs r2, #0
8001bc2: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8001bc6: 2301 movs r3, #1
8001bc8: e00f b.n 8001bea <I2C_WaitOnFlagUntilTimeout+0xaa>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8001bca: 68fb ldr r3, [r7, #12]
8001bcc: 681b ldr r3, [r3, #0]
8001bce: 699a ldr r2, [r3, #24]
8001bd0: 68bb ldr r3, [r7, #8]
8001bd2: 4013 ands r3, r2
8001bd4: 68ba ldr r2, [r7, #8]
8001bd6: 429a cmp r2, r3
8001bd8: bf0c ite eq
8001bda: 2301 moveq r3, #1
8001bdc: 2300 movne r3, #0
8001bde: b2db uxtb r3, r3
8001be0: 461a mov r2, r3
8001be2: 79fb ldrb r3, [r7, #7]
8001be4: 429a cmp r2, r3
8001be6: d0b4 beq.n 8001b52 <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8001be8: 2300 movs r3, #0
}
8001bea: 4618 mov r0, r3
8001bec: 3710 adds r7, #16
8001bee: 46bd mov sp, r7
8001bf0: bd80 pop {r7, pc}
08001bf2 <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
8001bf2: b580 push {r7, lr}
8001bf4: b084 sub sp, #16
8001bf6: af00 add r7, sp, #0
8001bf8: 60f8 str r0, [r7, #12]
8001bfa: 60b9 str r1, [r7, #8]
8001bfc: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8001bfe: e033 b.n 8001c68 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
8001c00: 687a ldr r2, [r7, #4]
8001c02: 68b9 ldr r1, [r7, #8]
8001c04: 68f8 ldr r0, [r7, #12]
8001c06: f000 f87f bl 8001d08 <I2C_IsErrorOccurred>
8001c0a: 4603 mov r3, r0
8001c0c: 2b00 cmp r3, #0
8001c0e: d001 beq.n 8001c14 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8001c10: 2301 movs r3, #1
8001c12: e031 b.n 8001c78 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8001c14: 68bb ldr r3, [r7, #8]
8001c16: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8001c1a: d025 beq.n 8001c68 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8001c1c: f7ff f93a bl 8000e94 <HAL_GetTick>
8001c20: 4602 mov r2, r0
8001c22: 687b ldr r3, [r7, #4]
8001c24: 1ad3 subs r3, r2, r3
8001c26: 68ba ldr r2, [r7, #8]
8001c28: 429a cmp r2, r3
8001c2a: d302 bcc.n 8001c32 <I2C_WaitOnTXISFlagUntilTimeout+0x40>
8001c2c: 68bb ldr r3, [r7, #8]
8001c2e: 2b00 cmp r3, #0
8001c30: d11a bne.n 8001c68 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
8001c32: 68fb ldr r3, [r7, #12]
8001c34: 681b ldr r3, [r3, #0]
8001c36: 699b ldr r3, [r3, #24]
8001c38: f003 0302 and.w r3, r3, #2
8001c3c: 2b02 cmp r3, #2
8001c3e: d013 beq.n 8001c68 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8001c40: 68fb ldr r3, [r7, #12]
8001c42: 6c5b ldr r3, [r3, #68] @ 0x44
8001c44: f043 0220 orr.w r2, r3, #32
8001c48: 68fb ldr r3, [r7, #12]
8001c4a: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
8001c4c: 68fb ldr r3, [r7, #12]
8001c4e: 2220 movs r2, #32
8001c50: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001c54: 68fb ldr r3, [r7, #12]
8001c56: 2200 movs r2, #0
8001c58: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001c5c: 68fb ldr r3, [r7, #12]
8001c5e: 2200 movs r2, #0
8001c60: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8001c64: 2301 movs r3, #1
8001c66: e007 b.n 8001c78 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8001c68: 68fb ldr r3, [r7, #12]
8001c6a: 681b ldr r3, [r3, #0]
8001c6c: 699b ldr r3, [r3, #24]
8001c6e: f003 0302 and.w r3, r3, #2
8001c72: 2b02 cmp r3, #2
8001c74: d1c4 bne.n 8001c00 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8001c76: 2300 movs r3, #0
}
8001c78: 4618 mov r0, r3
8001c7a: 3710 adds r7, #16
8001c7c: 46bd mov sp, r7
8001c7e: bd80 pop {r7, pc}
08001c80 <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
8001c80: b580 push {r7, lr}
8001c82: b084 sub sp, #16
8001c84: af00 add r7, sp, #0
8001c86: 60f8 str r0, [r7, #12]
8001c88: 60b9 str r1, [r7, #8]
8001c8a: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8001c8c: e02f b.n 8001cee <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
8001c8e: 687a ldr r2, [r7, #4]
8001c90: 68b9 ldr r1, [r7, #8]
8001c92: 68f8 ldr r0, [r7, #12]
8001c94: f000 f838 bl 8001d08 <I2C_IsErrorOccurred>
8001c98: 4603 mov r3, r0
8001c9a: 2b00 cmp r3, #0
8001c9c: d001 beq.n 8001ca2 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8001c9e: 2301 movs r3, #1
8001ca0: e02d b.n 8001cfe <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8001ca2: f7ff f8f7 bl 8000e94 <HAL_GetTick>
8001ca6: 4602 mov r2, r0
8001ca8: 687b ldr r3, [r7, #4]
8001caa: 1ad3 subs r3, r2, r3
8001cac: 68ba ldr r2, [r7, #8]
8001cae: 429a cmp r2, r3
8001cb0: d302 bcc.n 8001cb8 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
8001cb2: 68bb ldr r3, [r7, #8]
8001cb4: 2b00 cmp r3, #0
8001cb6: d11a bne.n 8001cee <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
8001cb8: 68fb ldr r3, [r7, #12]
8001cba: 681b ldr r3, [r3, #0]
8001cbc: 699b ldr r3, [r3, #24]
8001cbe: f003 0320 and.w r3, r3, #32
8001cc2: 2b20 cmp r3, #32
8001cc4: d013 beq.n 8001cee <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8001cc6: 68fb ldr r3, [r7, #12]
8001cc8: 6c5b ldr r3, [r3, #68] @ 0x44
8001cca: f043 0220 orr.w r2, r3, #32
8001cce: 68fb ldr r3, [r7, #12]
8001cd0: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
8001cd2: 68fb ldr r3, [r7, #12]
8001cd4: 2220 movs r2, #32
8001cd6: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001cda: 68fb ldr r3, [r7, #12]
8001cdc: 2200 movs r2, #0
8001cde: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001ce2: 68fb ldr r3, [r7, #12]
8001ce4: 2200 movs r2, #0
8001ce6: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8001cea: 2301 movs r3, #1
8001cec: e007 b.n 8001cfe <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8001cee: 68fb ldr r3, [r7, #12]
8001cf0: 681b ldr r3, [r3, #0]
8001cf2: 699b ldr r3, [r3, #24]
8001cf4: f003 0320 and.w r3, r3, #32
8001cf8: 2b20 cmp r3, #32
8001cfa: d1c8 bne.n 8001c8e <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8001cfc: 2300 movs r3, #0
}
8001cfe: 4618 mov r0, r3
8001d00: 3710 adds r7, #16
8001d02: 46bd mov sp, r7
8001d04: bd80 pop {r7, pc}
...
08001d08 <I2C_IsErrorOccurred>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8001d08: b580 push {r7, lr}
8001d0a: b08a sub sp, #40 @ 0x28
8001d0c: af00 add r7, sp, #0
8001d0e: 60f8 str r0, [r7, #12]
8001d10: 60b9 str r1, [r7, #8]
8001d12: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001d14: 2300 movs r3, #0
8001d16: f887 3027 strb.w r3, [r7, #39] @ 0x27
uint32_t itflag = hi2c->Instance->ISR;
8001d1a: 68fb ldr r3, [r7, #12]
8001d1c: 681b ldr r3, [r3, #0]
8001d1e: 699b ldr r3, [r3, #24]
8001d20: 61bb str r3, [r7, #24]
uint32_t error_code = 0;
8001d22: 2300 movs r3, #0
8001d24: 623b str r3, [r7, #32]
uint32_t tickstart = Tickstart;
8001d26: 687b ldr r3, [r7, #4]
8001d28: 61fb str r3, [r7, #28]
uint32_t tmp1;
HAL_I2C_ModeTypeDef tmp2;
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
8001d2a: 69bb ldr r3, [r7, #24]
8001d2c: f003 0310 and.w r3, r3, #16
8001d30: 2b00 cmp r3, #0
8001d32: d068 beq.n 8001e06 <I2C_IsErrorOccurred+0xfe>
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8001d34: 68fb ldr r3, [r7, #12]
8001d36: 681b ldr r3, [r3, #0]
8001d38: 2210 movs r2, #16
8001d3a: 61da str r2, [r3, #28]
/* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
8001d3c: e049 b.n 8001dd2 <I2C_IsErrorOccurred+0xca>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8001d3e: 68bb ldr r3, [r7, #8]
8001d40: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8001d44: d045 beq.n 8001dd2 <I2C_IsErrorOccurred+0xca>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
8001d46: f7ff f8a5 bl 8000e94 <HAL_GetTick>
8001d4a: 4602 mov r2, r0
8001d4c: 69fb ldr r3, [r7, #28]
8001d4e: 1ad3 subs r3, r2, r3
8001d50: 68ba ldr r2, [r7, #8]
8001d52: 429a cmp r2, r3
8001d54: d302 bcc.n 8001d5c <I2C_IsErrorOccurred+0x54>
8001d56: 68bb ldr r3, [r7, #8]
8001d58: 2b00 cmp r3, #0
8001d5a: d13a bne.n 8001dd2 <I2C_IsErrorOccurred+0xca>
{
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
8001d5c: 68fb ldr r3, [r7, #12]
8001d5e: 681b ldr r3, [r3, #0]
8001d60: 685b ldr r3, [r3, #4]
8001d62: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001d66: 617b str r3, [r7, #20]
tmp2 = hi2c->Mode;
8001d68: 68fb ldr r3, [r7, #12]
8001d6a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
8001d6e: 74fb strb r3, [r7, #19]
/* In case of I2C still busy, try to regenerate a STOP manually */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
8001d70: 68fb ldr r3, [r7, #12]
8001d72: 681b ldr r3, [r3, #0]
8001d74: 699b ldr r3, [r3, #24]
8001d76: f403 4300 and.w r3, r3, #32768 @ 0x8000
8001d7a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8001d7e: d121 bne.n 8001dc4 <I2C_IsErrorOccurred+0xbc>
8001d80: 697b ldr r3, [r7, #20]
8001d82: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8001d86: d01d beq.n 8001dc4 <I2C_IsErrorOccurred+0xbc>
(tmp1 != I2C_CR2_STOP) && \
8001d88: 7cfb ldrb r3, [r7, #19]
8001d8a: 2b20 cmp r3, #32
8001d8c: d01a beq.n 8001dc4 <I2C_IsErrorOccurred+0xbc>
(tmp2 != HAL_I2C_MODE_SLAVE))
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
8001d8e: 68fb ldr r3, [r7, #12]
8001d90: 681b ldr r3, [r3, #0]
8001d92: 685a ldr r2, [r3, #4]
8001d94: 68fb ldr r3, [r7, #12]
8001d96: 681b ldr r3, [r3, #0]
8001d98: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8001d9c: 605a str r2, [r3, #4]
/* Update Tick with new reference */
tickstart = HAL_GetTick();
8001d9e: f7ff f879 bl 8000e94 <HAL_GetTick>
8001da2: 61f8 str r0, [r7, #28]
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8001da4: e00e b.n 8001dc4 <I2C_IsErrorOccurred+0xbc>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
8001da6: f7ff f875 bl 8000e94 <HAL_GetTick>
8001daa: 4602 mov r2, r0
8001dac: 69fb ldr r3, [r7, #28]
8001dae: 1ad3 subs r3, r2, r3
8001db0: 2b19 cmp r3, #25
8001db2: d907 bls.n 8001dc4 <I2C_IsErrorOccurred+0xbc>
{
error_code |= HAL_I2C_ERROR_TIMEOUT;
8001db4: 6a3b ldr r3, [r7, #32]
8001db6: f043 0320 orr.w r3, r3, #32
8001dba: 623b str r3, [r7, #32]
status = HAL_ERROR;
8001dbc: 2301 movs r3, #1
8001dbe: f887 3027 strb.w r3, [r7, #39] @ 0x27
break;
8001dc2: e006 b.n 8001dd2 <I2C_IsErrorOccurred+0xca>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8001dc4: 68fb ldr r3, [r7, #12]
8001dc6: 681b ldr r3, [r3, #0]
8001dc8: 699b ldr r3, [r3, #24]
8001dca: f003 0320 and.w r3, r3, #32
8001dce: 2b20 cmp r3, #32
8001dd0: d1e9 bne.n 8001da6 <I2C_IsErrorOccurred+0x9e>
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
8001dd2: 68fb ldr r3, [r7, #12]
8001dd4: 681b ldr r3, [r3, #0]
8001dd6: 699b ldr r3, [r3, #24]
8001dd8: f003 0320 and.w r3, r3, #32
8001ddc: 2b20 cmp r3, #32
8001dde: d003 beq.n 8001de8 <I2C_IsErrorOccurred+0xe0>
8001de0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
8001de4: 2b00 cmp r3, #0
8001de6: d0aa beq.n 8001d3e <I2C_IsErrorOccurred+0x36>
}
}
}
/* In case STOP Flag is detected, clear it */
if (status == HAL_OK)
8001de8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
8001dec: 2b00 cmp r3, #0
8001dee: d103 bne.n 8001df8 <I2C_IsErrorOccurred+0xf0>
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8001df0: 68fb ldr r3, [r7, #12]
8001df2: 681b ldr r3, [r3, #0]
8001df4: 2220 movs r2, #32
8001df6: 61da str r2, [r3, #28]
}
error_code |= HAL_I2C_ERROR_AF;
8001df8: 6a3b ldr r3, [r7, #32]
8001dfa: f043 0304 orr.w r3, r3, #4
8001dfe: 623b str r3, [r7, #32]
status = HAL_ERROR;
8001e00: 2301 movs r3, #1
8001e02: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
/* Refresh Content of Status register */
itflag = hi2c->Instance->ISR;
8001e06: 68fb ldr r3, [r7, #12]
8001e08: 681b ldr r3, [r3, #0]
8001e0a: 699b ldr r3, [r3, #24]
8001e0c: 61bb str r3, [r7, #24]
/* Then verify if an additional errors occurs */
/* Check if a Bus error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
8001e0e: 69bb ldr r3, [r7, #24]
8001e10: f403 7380 and.w r3, r3, #256 @ 0x100
8001e14: 2b00 cmp r3, #0
8001e16: d00b beq.n 8001e30 <I2C_IsErrorOccurred+0x128>
{
error_code |= HAL_I2C_ERROR_BERR;
8001e18: 6a3b ldr r3, [r7, #32]
8001e1a: f043 0301 orr.w r3, r3, #1
8001e1e: 623b str r3, [r7, #32]
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
8001e20: 68fb ldr r3, [r7, #12]
8001e22: 681b ldr r3, [r3, #0]
8001e24: f44f 7280 mov.w r2, #256 @ 0x100
8001e28: 61da str r2, [r3, #28]
status = HAL_ERROR;
8001e2a: 2301 movs r3, #1
8001e2c: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
/* Check if an Over-Run/Under-Run error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
8001e30: 69bb ldr r3, [r7, #24]
8001e32: f403 6380 and.w r3, r3, #1024 @ 0x400
8001e36: 2b00 cmp r3, #0
8001e38: d00b beq.n 8001e52 <I2C_IsErrorOccurred+0x14a>
{
error_code |= HAL_I2C_ERROR_OVR;
8001e3a: 6a3b ldr r3, [r7, #32]
8001e3c: f043 0308 orr.w r3, r3, #8
8001e40: 623b str r3, [r7, #32]
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
8001e42: 68fb ldr r3, [r7, #12]
8001e44: 681b ldr r3, [r3, #0]
8001e46: f44f 6280 mov.w r2, #1024 @ 0x400
8001e4a: 61da str r2, [r3, #28]
status = HAL_ERROR;
8001e4c: 2301 movs r3, #1
8001e4e: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
/* Check if an Arbitration Loss error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
8001e52: 69bb ldr r3, [r7, #24]
8001e54: f403 7300 and.w r3, r3, #512 @ 0x200
8001e58: 2b00 cmp r3, #0
8001e5a: d00b beq.n 8001e74 <I2C_IsErrorOccurred+0x16c>
{
error_code |= HAL_I2C_ERROR_ARLO;
8001e5c: 6a3b ldr r3, [r7, #32]
8001e5e: f043 0302 orr.w r3, r3, #2
8001e62: 623b str r3, [r7, #32]
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
8001e64: 68fb ldr r3, [r7, #12]
8001e66: 681b ldr r3, [r3, #0]
8001e68: f44f 7200 mov.w r2, #512 @ 0x200
8001e6c: 61da str r2, [r3, #28]
status = HAL_ERROR;
8001e6e: 2301 movs r3, #1
8001e70: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
if (status != HAL_OK)
8001e74: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
8001e78: 2b00 cmp r3, #0
8001e7a: d01c beq.n 8001eb6 <I2C_IsErrorOccurred+0x1ae>
{
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8001e7c: 68f8 ldr r0, [r7, #12]
8001e7e: f7ff fe3b bl 8001af8 <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8001e82: 68fb ldr r3, [r7, #12]
8001e84: 681b ldr r3, [r3, #0]
8001e86: 6859 ldr r1, [r3, #4]
8001e88: 68fb ldr r3, [r7, #12]
8001e8a: 681a ldr r2, [r3, #0]
8001e8c: 4b0d ldr r3, [pc, #52] @ (8001ec4 <I2C_IsErrorOccurred+0x1bc>)
8001e8e: 400b ands r3, r1
8001e90: 6053 str r3, [r2, #4]
hi2c->ErrorCode |= error_code;
8001e92: 68fb ldr r3, [r7, #12]
8001e94: 6c5a ldr r2, [r3, #68] @ 0x44
8001e96: 6a3b ldr r3, [r7, #32]
8001e98: 431a orrs r2, r3
8001e9a: 68fb ldr r3, [r7, #12]
8001e9c: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
8001e9e: 68fb ldr r3, [r7, #12]
8001ea0: 2220 movs r2, #32
8001ea2: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001ea6: 68fb ldr r3, [r7, #12]
8001ea8: 2200 movs r2, #0
8001eaa: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001eae: 68fb ldr r3, [r7, #12]
8001eb0: 2200 movs r2, #0
8001eb2: f883 2040 strb.w r2, [r3, #64] @ 0x40
}
return status;
8001eb6: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
}
8001eba: 4618 mov r0, r3
8001ebc: 3728 adds r7, #40 @ 0x28
8001ebe: 46bd mov sp, r7
8001ec0: bd80 pop {r7, pc}
8001ec2: bf00 nop
8001ec4: fe00e800 .word 0xfe00e800
08001ec8 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
8001ec8: b480 push {r7}
8001eca: b087 sub sp, #28
8001ecc: af00 add r7, sp, #0
8001ece: 60f8 str r0, [r7, #12]
8001ed0: 607b str r3, [r7, #4]
8001ed2: 460b mov r3, r1
8001ed4: 817b strh r3, [r7, #10]
8001ed6: 4613 mov r3, r2
8001ed8: 727b strb r3, [r7, #9]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8001eda: 897b ldrh r3, [r7, #10]
8001edc: f3c3 0209 ubfx r2, r3, #0, #10
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
8001ee0: 7a7b ldrb r3, [r7, #9]
8001ee2: 041b lsls r3, r3, #16
8001ee4: f403 037f and.w r3, r3, #16711680 @ 0xff0000
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8001ee8: 431a orrs r2, r3
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
8001eea: 687b ldr r3, [r7, #4]
8001eec: 431a orrs r2, r3
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8001eee: 6a3b ldr r3, [r7, #32]
8001ef0: 4313 orrs r3, r2
8001ef2: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8001ef6: 617b str r3, [r7, #20]
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
8001ef8: 68fb ldr r3, [r7, #12]
8001efa: 681b ldr r3, [r3, #0]
8001efc: 685a ldr r2, [r3, #4]
8001efe: 6a3b ldr r3, [r7, #32]
8001f00: 0d5b lsrs r3, r3, #21
8001f02: f403 6180 and.w r1, r3, #1024 @ 0x400
8001f06: 4b08 ldr r3, [pc, #32] @ (8001f28 <I2C_TransferConfig+0x60>)
8001f08: 430b orrs r3, r1
8001f0a: 43db mvns r3, r3
8001f0c: ea02 0103 and.w r1, r2, r3
8001f10: 68fb ldr r3, [r7, #12]
8001f12: 681b ldr r3, [r3, #0]
8001f14: 697a ldr r2, [r7, #20]
8001f16: 430a orrs r2, r1
8001f18: 605a str r2, [r3, #4]
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
8001f1a: bf00 nop
8001f1c: 371c adds r7, #28
8001f1e: 46bd mov sp, r7
8001f20: f85d 7b04 ldr.w r7, [sp], #4
8001f24: 4770 bx lr
8001f26: bf00 nop
8001f28: 03ff63ff .word 0x03ff63ff
08001f2c <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
8001f2c: b480 push {r7}
8001f2e: b083 sub sp, #12
8001f30: af00 add r7, sp, #0
8001f32: 6078 str r0, [r7, #4]
8001f34: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8001f36: 687b ldr r3, [r7, #4]
8001f38: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8001f3c: b2db uxtb r3, r3
8001f3e: 2b20 cmp r3, #32
8001f40: d138 bne.n 8001fb4 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8001f42: 687b ldr r3, [r7, #4]
8001f44: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8001f48: 2b01 cmp r3, #1
8001f4a: d101 bne.n 8001f50 <HAL_I2CEx_ConfigAnalogFilter+0x24>
8001f4c: 2302 movs r3, #2
8001f4e: e032 b.n 8001fb6 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
8001f50: 687b ldr r3, [r7, #4]
8001f52: 2201 movs r2, #1
8001f54: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8001f58: 687b ldr r3, [r7, #4]
8001f5a: 2224 movs r2, #36 @ 0x24
8001f5c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001f60: 687b ldr r3, [r7, #4]
8001f62: 681b ldr r3, [r3, #0]
8001f64: 681a ldr r2, [r3, #0]
8001f66: 687b ldr r3, [r7, #4]
8001f68: 681b ldr r3, [r3, #0]
8001f6a: f022 0201 bic.w r2, r2, #1
8001f6e: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8001f70: 687b ldr r3, [r7, #4]
8001f72: 681b ldr r3, [r3, #0]
8001f74: 681a ldr r2, [r3, #0]
8001f76: 687b ldr r3, [r7, #4]
8001f78: 681b ldr r3, [r3, #0]
8001f7a: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8001f7e: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
8001f80: 687b ldr r3, [r7, #4]
8001f82: 681b ldr r3, [r3, #0]
8001f84: 6819 ldr r1, [r3, #0]
8001f86: 687b ldr r3, [r7, #4]
8001f88: 681b ldr r3, [r3, #0]
8001f8a: 683a ldr r2, [r7, #0]
8001f8c: 430a orrs r2, r1
8001f8e: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8001f90: 687b ldr r3, [r7, #4]
8001f92: 681b ldr r3, [r3, #0]
8001f94: 681a ldr r2, [r3, #0]
8001f96: 687b ldr r3, [r7, #4]
8001f98: 681b ldr r3, [r3, #0]
8001f9a: f042 0201 orr.w r2, r2, #1
8001f9e: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8001fa0: 687b ldr r3, [r7, #4]
8001fa2: 2220 movs r2, #32
8001fa4: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001fa8: 687b ldr r3, [r7, #4]
8001faa: 2200 movs r2, #0
8001fac: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8001fb0: 2300 movs r3, #0
8001fb2: e000 b.n 8001fb6 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8001fb4: 2302 movs r3, #2
}
}
8001fb6: 4618 mov r0, r3
8001fb8: 370c adds r7, #12
8001fba: 46bd mov sp, r7
8001fbc: f85d 7b04 ldr.w r7, [sp], #4
8001fc0: 4770 bx lr
08001fc2 <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
8001fc2: b480 push {r7}
8001fc4: b085 sub sp, #20
8001fc6: af00 add r7, sp, #0
8001fc8: 6078 str r0, [r7, #4]
8001fca: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8001fcc: 687b ldr r3, [r7, #4]
8001fce: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8001fd2: b2db uxtb r3, r3
8001fd4: 2b20 cmp r3, #32
8001fd6: d139 bne.n 800204c <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8001fd8: 687b ldr r3, [r7, #4]
8001fda: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8001fde: 2b01 cmp r3, #1
8001fe0: d101 bne.n 8001fe6 <HAL_I2CEx_ConfigDigitalFilter+0x24>
8001fe2: 2302 movs r3, #2
8001fe4: e033 b.n 800204e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
8001fe6: 687b ldr r3, [r7, #4]
8001fe8: 2201 movs r2, #1
8001fea: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8001fee: 687b ldr r3, [r7, #4]
8001ff0: 2224 movs r2, #36 @ 0x24
8001ff2: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001ff6: 687b ldr r3, [r7, #4]
8001ff8: 681b ldr r3, [r3, #0]
8001ffa: 681a ldr r2, [r3, #0]
8001ffc: 687b ldr r3, [r7, #4]
8001ffe: 681b ldr r3, [r3, #0]
8002000: f022 0201 bic.w r2, r2, #1
8002004: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
8002006: 687b ldr r3, [r7, #4]
8002008: 681b ldr r3, [r3, #0]
800200a: 681b ldr r3, [r3, #0]
800200c: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
800200e: 68fb ldr r3, [r7, #12]
8002010: f423 6370 bic.w r3, r3, #3840 @ 0xf00
8002014: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
8002016: 683b ldr r3, [r7, #0]
8002018: 021b lsls r3, r3, #8
800201a: 68fa ldr r2, [r7, #12]
800201c: 4313 orrs r3, r2
800201e: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
8002020: 687b ldr r3, [r7, #4]
8002022: 681b ldr r3, [r3, #0]
8002024: 68fa ldr r2, [r7, #12]
8002026: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8002028: 687b ldr r3, [r7, #4]
800202a: 681b ldr r3, [r3, #0]
800202c: 681a ldr r2, [r3, #0]
800202e: 687b ldr r3, [r7, #4]
8002030: 681b ldr r3, [r3, #0]
8002032: f042 0201 orr.w r2, r2, #1
8002036: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8002038: 687b ldr r3, [r7, #4]
800203a: 2220 movs r2, #32
800203c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002040: 687b ldr r3, [r7, #4]
8002042: 2200 movs r2, #0
8002044: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8002048: 2300 movs r3, #0
800204a: e000 b.n 800204e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
800204c: 2302 movs r3, #2
}
}
800204e: 4618 mov r0, r3
8002050: 3714 adds r7, #20
8002052: 46bd mov sp, r7
8002054: f85d 7b04 ldr.w r7, [sp], #4
8002058: 4770 bx lr
...
0800205c <HAL_PWREx_GetVoltageRange>:
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
800205c: b480 push {r7}
800205e: af00 add r7, sp, #0
else
{
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
}
#else
return (PWR->CR1 & PWR_CR1_VOS);
8002060: 4b04 ldr r3, [pc, #16] @ (8002074 <HAL_PWREx_GetVoltageRange+0x18>)
8002062: 681b ldr r3, [r3, #0]
8002064: f403 63c0 and.w r3, r3, #1536 @ 0x600
#endif
}
8002068: 4618 mov r0, r3
800206a: 46bd mov sp, r7
800206c: f85d 7b04 ldr.w r7, [sp], #4
8002070: 4770 bx lr
8002072: bf00 nop
8002074: 40007000 .word 0x40007000
08002078 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8002078: b480 push {r7}
800207a: b085 sub sp, #20
800207c: af00 add r7, sp, #0
800207e: 6078 str r0, [r7, #4]
}
#else
/* If Set Range 1 */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8002080: 687b ldr r3, [r7, #4]
8002082: f5b3 7f00 cmp.w r3, #512 @ 0x200
8002086: d130 bne.n 80020ea <HAL_PWREx_ControlVoltageScaling+0x72>
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
8002088: 4b23 ldr r3, [pc, #140] @ (8002118 <HAL_PWREx_ControlVoltageScaling+0xa0>)
800208a: 681b ldr r3, [r3, #0]
800208c: f403 63c0 and.w r3, r3, #1536 @ 0x600
8002090: f5b3 7f00 cmp.w r3, #512 @ 0x200
8002094: d038 beq.n 8002108 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8002096: 4b20 ldr r3, [pc, #128] @ (8002118 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002098: 681b ldr r3, [r3, #0]
800209a: f423 63c0 bic.w r3, r3, #1536 @ 0x600
800209e: 4a1e ldr r2, [pc, #120] @ (8002118 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80020a0: f443 7300 orr.w r3, r3, #512 @ 0x200
80020a4: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
80020a6: 4b1d ldr r3, [pc, #116] @ (800211c <HAL_PWREx_ControlVoltageScaling+0xa4>)
80020a8: 681b ldr r3, [r3, #0]
80020aa: 2232 movs r2, #50 @ 0x32
80020ac: fb02 f303 mul.w r3, r2, r3
80020b0: 4a1b ldr r2, [pc, #108] @ (8002120 <HAL_PWREx_ControlVoltageScaling+0xa8>)
80020b2: fba2 2303 umull r2, r3, r2, r3
80020b6: 0c9b lsrs r3, r3, #18
80020b8: 3301 adds r3, #1
80020ba: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80020bc: e002 b.n 80020c4 <HAL_PWREx_ControlVoltageScaling+0x4c>
{
wait_loop_index--;
80020be: 68fb ldr r3, [r7, #12]
80020c0: 3b01 subs r3, #1
80020c2: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80020c4: 4b14 ldr r3, [pc, #80] @ (8002118 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80020c6: 695b ldr r3, [r3, #20]
80020c8: f403 6380 and.w r3, r3, #1024 @ 0x400
80020cc: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80020d0: d102 bne.n 80020d8 <HAL_PWREx_ControlVoltageScaling+0x60>
80020d2: 68fb ldr r3, [r7, #12]
80020d4: 2b00 cmp r3, #0
80020d6: d1f2 bne.n 80020be <HAL_PWREx_ControlVoltageScaling+0x46>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
80020d8: 4b0f ldr r3, [pc, #60] @ (8002118 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80020da: 695b ldr r3, [r3, #20]
80020dc: f403 6380 and.w r3, r3, #1024 @ 0x400
80020e0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80020e4: d110 bne.n 8002108 <HAL_PWREx_ControlVoltageScaling+0x90>
{
return HAL_TIMEOUT;
80020e6: 2303 movs r3, #3
80020e8: e00f b.n 800210a <HAL_PWREx_ControlVoltageScaling+0x92>
}
}
}
else
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
80020ea: 4b0b ldr r3, [pc, #44] @ (8002118 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80020ec: 681b ldr r3, [r3, #0]
80020ee: f403 63c0 and.w r3, r3, #1536 @ 0x600
80020f2: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80020f6: d007 beq.n 8002108 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
80020f8: 4b07 ldr r3, [pc, #28] @ (8002118 <HAL_PWREx_ControlVoltageScaling+0xa0>)
80020fa: 681b ldr r3, [r3, #0]
80020fc: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8002100: 4a05 ldr r2, [pc, #20] @ (8002118 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002102: f443 6380 orr.w r3, r3, #1024 @ 0x400
8002106: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
}
}
#endif
return HAL_OK;
8002108: 2300 movs r3, #0
}
800210a: 4618 mov r0, r3
800210c: 3714 adds r7, #20
800210e: 46bd mov sp, r7
8002110: f85d 7b04 ldr.w r7, [sp], #4
8002114: 4770 bx lr
8002116: bf00 nop
8002118: 40007000 .word 0x40007000
800211c: 20000000 .word 0x20000000
8002120: 431bde83 .word 0x431bde83
08002124 <HAL_RCC_OscConfig>:
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8002124: b580 push {r7, lr}
8002126: b088 sub sp, #32
8002128: af00 add r7, sp, #0
800212a: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
800212c: 687b ldr r3, [r7, #4]
800212e: 2b00 cmp r3, #0
8002130: d101 bne.n 8002136 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8002132: 2301 movs r3, #1
8002134: e3ca b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8002136: 4b97 ldr r3, [pc, #604] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002138: 689b ldr r3, [r3, #8]
800213a: f003 030c and.w r3, r3, #12
800213e: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
8002140: 4b94 ldr r3, [pc, #592] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002142: 68db ldr r3, [r3, #12]
8002144: f003 0303 and.w r3, r3, #3
8002148: 617b str r3, [r7, #20]
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
800214a: 687b ldr r3, [r7, #4]
800214c: 681b ldr r3, [r3, #0]
800214e: f003 0310 and.w r3, r3, #16
8002152: 2b00 cmp r3, #0
8002154: f000 80e4 beq.w 8002320 <HAL_RCC_OscConfig+0x1fc>
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
8002158: 69bb ldr r3, [r7, #24]
800215a: 2b00 cmp r3, #0
800215c: d007 beq.n 800216e <HAL_RCC_OscConfig+0x4a>
800215e: 69bb ldr r3, [r7, #24]
8002160: 2b0c cmp r3, #12
8002162: f040 808b bne.w 800227c <HAL_RCC_OscConfig+0x158>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
8002166: 697b ldr r3, [r7, #20]
8002168: 2b01 cmp r3, #1
800216a: f040 8087 bne.w 800227c <HAL_RCC_OscConfig+0x158>
{
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
800216e: 4b89 ldr r3, [pc, #548] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002170: 681b ldr r3, [r3, #0]
8002172: f003 0302 and.w r3, r3, #2
8002176: 2b00 cmp r3, #0
8002178: d005 beq.n 8002186 <HAL_RCC_OscConfig+0x62>
800217a: 687b ldr r3, [r7, #4]
800217c: 699b ldr r3, [r3, #24]
800217e: 2b00 cmp r3, #0
8002180: d101 bne.n 8002186 <HAL_RCC_OscConfig+0x62>
{
return HAL_ERROR;
8002182: 2301 movs r3, #1
8002184: e3a2 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
else
{
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
8002186: 687b ldr r3, [r7, #4]
8002188: 6a1a ldr r2, [r3, #32]
800218a: 4b82 ldr r3, [pc, #520] @ (8002394 <HAL_RCC_OscConfig+0x270>)
800218c: 681b ldr r3, [r3, #0]
800218e: f003 0308 and.w r3, r3, #8
8002192: 2b00 cmp r3, #0
8002194: d004 beq.n 80021a0 <HAL_RCC_OscConfig+0x7c>
8002196: 4b7f ldr r3, [pc, #508] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002198: 681b ldr r3, [r3, #0]
800219a: f003 03f0 and.w r3, r3, #240 @ 0xf0
800219e: e005 b.n 80021ac <HAL_RCC_OscConfig+0x88>
80021a0: 4b7c ldr r3, [pc, #496] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021a2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80021a6: 091b lsrs r3, r3, #4
80021a8: f003 03f0 and.w r3, r3, #240 @ 0xf0
80021ac: 4293 cmp r3, r2
80021ae: d223 bcs.n 80021f8 <HAL_RCC_OscConfig+0xd4>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
80021b0: 687b ldr r3, [r7, #4]
80021b2: 6a1b ldr r3, [r3, #32]
80021b4: 4618 mov r0, r3
80021b6: f000 fd55 bl 8002c64 <RCC_SetFlashLatencyFromMSIRange>
80021ba: 4603 mov r3, r0
80021bc: 2b00 cmp r3, #0
80021be: d001 beq.n 80021c4 <HAL_RCC_OscConfig+0xa0>
{
return HAL_ERROR;
80021c0: 2301 movs r3, #1
80021c2: e383 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80021c4: 4b73 ldr r3, [pc, #460] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021c6: 681b ldr r3, [r3, #0]
80021c8: 4a72 ldr r2, [pc, #456] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021ca: f043 0308 orr.w r3, r3, #8
80021ce: 6013 str r3, [r2, #0]
80021d0: 4b70 ldr r3, [pc, #448] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021d2: 681b ldr r3, [r3, #0]
80021d4: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80021d8: 687b ldr r3, [r7, #4]
80021da: 6a1b ldr r3, [r3, #32]
80021dc: 496d ldr r1, [pc, #436] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021de: 4313 orrs r3, r2
80021e0: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80021e2: 4b6c ldr r3, [pc, #432] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021e4: 685b ldr r3, [r3, #4]
80021e6: f423 427f bic.w r2, r3, #65280 @ 0xff00
80021ea: 687b ldr r3, [r7, #4]
80021ec: 69db ldr r3, [r3, #28]
80021ee: 021b lsls r3, r3, #8
80021f0: 4968 ldr r1, [pc, #416] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021f2: 4313 orrs r3, r2
80021f4: 604b str r3, [r1, #4]
80021f6: e025 b.n 8002244 <HAL_RCC_OscConfig+0x120>
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80021f8: 4b66 ldr r3, [pc, #408] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021fa: 681b ldr r3, [r3, #0]
80021fc: 4a65 ldr r2, [pc, #404] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80021fe: f043 0308 orr.w r3, r3, #8
8002202: 6013 str r3, [r2, #0]
8002204: 4b63 ldr r3, [pc, #396] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002206: 681b ldr r3, [r3, #0]
8002208: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800220c: 687b ldr r3, [r7, #4]
800220e: 6a1b ldr r3, [r3, #32]
8002210: 4960 ldr r1, [pc, #384] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002212: 4313 orrs r3, r2
8002214: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8002216: 4b5f ldr r3, [pc, #380] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002218: 685b ldr r3, [r3, #4]
800221a: f423 427f bic.w r2, r3, #65280 @ 0xff00
800221e: 687b ldr r3, [r7, #4]
8002220: 69db ldr r3, [r3, #28]
8002222: 021b lsls r3, r3, #8
8002224: 495b ldr r1, [pc, #364] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002226: 4313 orrs r3, r2
8002228: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
/* Only possible when MSI is the System clock source */
if(sysclk_source == RCC_CFGR_SWS_MSI)
800222a: 69bb ldr r3, [r7, #24]
800222c: 2b00 cmp r3, #0
800222e: d109 bne.n 8002244 <HAL_RCC_OscConfig+0x120>
{
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8002230: 687b ldr r3, [r7, #4]
8002232: 6a1b ldr r3, [r3, #32]
8002234: 4618 mov r0, r3
8002236: f000 fd15 bl 8002c64 <RCC_SetFlashLatencyFromMSIRange>
800223a: 4603 mov r3, r0
800223c: 2b00 cmp r3, #0
800223e: d001 beq.n 8002244 <HAL_RCC_OscConfig+0x120>
{
return HAL_ERROR;
8002240: 2301 movs r3, #1
8002242: e343 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8002244: f000 fc4a bl 8002adc <HAL_RCC_GetSysClockFreq>
8002248: 4602 mov r2, r0
800224a: 4b52 ldr r3, [pc, #328] @ (8002394 <HAL_RCC_OscConfig+0x270>)
800224c: 689b ldr r3, [r3, #8]
800224e: 091b lsrs r3, r3, #4
8002250: f003 030f and.w r3, r3, #15
8002254: 4950 ldr r1, [pc, #320] @ (8002398 <HAL_RCC_OscConfig+0x274>)
8002256: 5ccb ldrb r3, [r1, r3]
8002258: f003 031f and.w r3, r3, #31
800225c: fa22 f303 lsr.w r3, r2, r3
8002260: 4a4e ldr r2, [pc, #312] @ (800239c <HAL_RCC_OscConfig+0x278>)
8002262: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8002264: 4b4e ldr r3, [pc, #312] @ (80023a0 <HAL_RCC_OscConfig+0x27c>)
8002266: 681b ldr r3, [r3, #0]
8002268: 4618 mov r0, r3
800226a: f7fe fdc3 bl 8000df4 <HAL_InitTick>
800226e: 4603 mov r3, r0
8002270: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
8002272: 7bfb ldrb r3, [r7, #15]
8002274: 2b00 cmp r3, #0
8002276: d052 beq.n 800231e <HAL_RCC_OscConfig+0x1fa>
{
return status;
8002278: 7bfb ldrb r3, [r7, #15]
800227a: e327 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
}
else
{
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
800227c: 687b ldr r3, [r7, #4]
800227e: 699b ldr r3, [r3, #24]
8002280: 2b00 cmp r3, #0
8002282: d032 beq.n 80022ea <HAL_RCC_OscConfig+0x1c6>
{
/* Enable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
8002284: 4b43 ldr r3, [pc, #268] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002286: 681b ldr r3, [r3, #0]
8002288: 4a42 ldr r2, [pc, #264] @ (8002394 <HAL_RCC_OscConfig+0x270>)
800228a: f043 0301 orr.w r3, r3, #1
800228e: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8002290: f7fe fe00 bl 8000e94 <HAL_GetTick>
8002294: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8002296: e008 b.n 80022aa <HAL_RCC_OscConfig+0x186>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8002298: f7fe fdfc bl 8000e94 <HAL_GetTick>
800229c: 4602 mov r2, r0
800229e: 693b ldr r3, [r7, #16]
80022a0: 1ad3 subs r3, r2, r3
80022a2: 2b02 cmp r3, #2
80022a4: d901 bls.n 80022aa <HAL_RCC_OscConfig+0x186>
{
return HAL_TIMEOUT;
80022a6: 2303 movs r3, #3
80022a8: e310 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
80022aa: 4b3a ldr r3, [pc, #232] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022ac: 681b ldr r3, [r3, #0]
80022ae: f003 0302 and.w r3, r3, #2
80022b2: 2b00 cmp r3, #0
80022b4: d0f0 beq.n 8002298 <HAL_RCC_OscConfig+0x174>
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80022b6: 4b37 ldr r3, [pc, #220] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022b8: 681b ldr r3, [r3, #0]
80022ba: 4a36 ldr r2, [pc, #216] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022bc: f043 0308 orr.w r3, r3, #8
80022c0: 6013 str r3, [r2, #0]
80022c2: 4b34 ldr r3, [pc, #208] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022c4: 681b ldr r3, [r3, #0]
80022c6: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80022ca: 687b ldr r3, [r7, #4]
80022cc: 6a1b ldr r3, [r3, #32]
80022ce: 4931 ldr r1, [pc, #196] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022d0: 4313 orrs r3, r2
80022d2: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80022d4: 4b2f ldr r3, [pc, #188] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022d6: 685b ldr r3, [r3, #4]
80022d8: f423 427f bic.w r2, r3, #65280 @ 0xff00
80022dc: 687b ldr r3, [r7, #4]
80022de: 69db ldr r3, [r3, #28]
80022e0: 021b lsls r3, r3, #8
80022e2: 492c ldr r1, [pc, #176] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022e4: 4313 orrs r3, r2
80022e6: 604b str r3, [r1, #4]
80022e8: e01a b.n 8002320 <HAL_RCC_OscConfig+0x1fc>
}
else
{
/* Disable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
80022ea: 4b2a ldr r3, [pc, #168] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022ec: 681b ldr r3, [r3, #0]
80022ee: 4a29 ldr r2, [pc, #164] @ (8002394 <HAL_RCC_OscConfig+0x270>)
80022f0: f023 0301 bic.w r3, r3, #1
80022f4: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
80022f6: f7fe fdcd bl 8000e94 <HAL_GetTick>
80022fa: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
80022fc: e008 b.n 8002310 <HAL_RCC_OscConfig+0x1ec>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
80022fe: f7fe fdc9 bl 8000e94 <HAL_GetTick>
8002302: 4602 mov r2, r0
8002304: 693b ldr r3, [r7, #16]
8002306: 1ad3 subs r3, r2, r3
8002308: 2b02 cmp r3, #2
800230a: d901 bls.n 8002310 <HAL_RCC_OscConfig+0x1ec>
{
return HAL_TIMEOUT;
800230c: 2303 movs r3, #3
800230e: e2dd b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
8002310: 4b20 ldr r3, [pc, #128] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002312: 681b ldr r3, [r3, #0]
8002314: f003 0302 and.w r3, r3, #2
8002318: 2b00 cmp r3, #0
800231a: d1f0 bne.n 80022fe <HAL_RCC_OscConfig+0x1da>
800231c: e000 b.n 8002320 <HAL_RCC_OscConfig+0x1fc>
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
800231e: bf00 nop
}
}
}
}
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002320: 687b ldr r3, [r7, #4]
8002322: 681b ldr r3, [r3, #0]
8002324: f003 0301 and.w r3, r3, #1
8002328: 2b00 cmp r3, #0
800232a: d074 beq.n 8002416 <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
800232c: 69bb ldr r3, [r7, #24]
800232e: 2b08 cmp r3, #8
8002330: d005 beq.n 800233e <HAL_RCC_OscConfig+0x21a>
8002332: 69bb ldr r3, [r7, #24]
8002334: 2b0c cmp r3, #12
8002336: d10e bne.n 8002356 <HAL_RCC_OscConfig+0x232>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
8002338: 697b ldr r3, [r7, #20]
800233a: 2b03 cmp r3, #3
800233c: d10b bne.n 8002356 <HAL_RCC_OscConfig+0x232>
{
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800233e: 4b15 ldr r3, [pc, #84] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002340: 681b ldr r3, [r3, #0]
8002342: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002346: 2b00 cmp r3, #0
8002348: d064 beq.n 8002414 <HAL_RCC_OscConfig+0x2f0>
800234a: 687b ldr r3, [r7, #4]
800234c: 685b ldr r3, [r3, #4]
800234e: 2b00 cmp r3, #0
8002350: d160 bne.n 8002414 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_ERROR;
8002352: 2301 movs r3, #1
8002354: e2ba b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002356: 687b ldr r3, [r7, #4]
8002358: 685b ldr r3, [r3, #4]
800235a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800235e: d106 bne.n 800236e <HAL_RCC_OscConfig+0x24a>
8002360: 4b0c ldr r3, [pc, #48] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002362: 681b ldr r3, [r3, #0]
8002364: 4a0b ldr r2, [pc, #44] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002366: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800236a: 6013 str r3, [r2, #0]
800236c: e026 b.n 80023bc <HAL_RCC_OscConfig+0x298>
800236e: 687b ldr r3, [r7, #4]
8002370: 685b ldr r3, [r3, #4]
8002372: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8002376: d115 bne.n 80023a4 <HAL_RCC_OscConfig+0x280>
8002378: 4b06 ldr r3, [pc, #24] @ (8002394 <HAL_RCC_OscConfig+0x270>)
800237a: 681b ldr r3, [r3, #0]
800237c: 4a05 ldr r2, [pc, #20] @ (8002394 <HAL_RCC_OscConfig+0x270>)
800237e: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8002382: 6013 str r3, [r2, #0]
8002384: 4b03 ldr r3, [pc, #12] @ (8002394 <HAL_RCC_OscConfig+0x270>)
8002386: 681b ldr r3, [r3, #0]
8002388: 4a02 ldr r2, [pc, #8] @ (8002394 <HAL_RCC_OscConfig+0x270>)
800238a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800238e: 6013 str r3, [r2, #0]
8002390: e014 b.n 80023bc <HAL_RCC_OscConfig+0x298>
8002392: bf00 nop
8002394: 40021000 .word 0x40021000
8002398: 08004e88 .word 0x08004e88
800239c: 20000000 .word 0x20000000
80023a0: 20000004 .word 0x20000004
80023a4: 4ba0 ldr r3, [pc, #640] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80023a6: 681b ldr r3, [r3, #0]
80023a8: 4a9f ldr r2, [pc, #636] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80023aa: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80023ae: 6013 str r3, [r2, #0]
80023b0: 4b9d ldr r3, [pc, #628] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80023b2: 681b ldr r3, [r3, #0]
80023b4: 4a9c ldr r2, [pc, #624] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80023b6: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80023ba: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80023bc: 687b ldr r3, [r7, #4]
80023be: 685b ldr r3, [r3, #4]
80023c0: 2b00 cmp r3, #0
80023c2: d013 beq.n 80023ec <HAL_RCC_OscConfig+0x2c8>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80023c4: f7fe fd66 bl 8000e94 <HAL_GetTick>
80023c8: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80023ca: e008 b.n 80023de <HAL_RCC_OscConfig+0x2ba>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80023cc: f7fe fd62 bl 8000e94 <HAL_GetTick>
80023d0: 4602 mov r2, r0
80023d2: 693b ldr r3, [r7, #16]
80023d4: 1ad3 subs r3, r2, r3
80023d6: 2b64 cmp r3, #100 @ 0x64
80023d8: d901 bls.n 80023de <HAL_RCC_OscConfig+0x2ba>
{
return HAL_TIMEOUT;
80023da: 2303 movs r3, #3
80023dc: e276 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80023de: 4b92 ldr r3, [pc, #584] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80023e0: 681b ldr r3, [r3, #0]
80023e2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80023e6: 2b00 cmp r3, #0
80023e8: d0f0 beq.n 80023cc <HAL_RCC_OscConfig+0x2a8>
80023ea: e014 b.n 8002416 <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80023ec: f7fe fd52 bl 8000e94 <HAL_GetTick>
80023f0: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80023f2: e008 b.n 8002406 <HAL_RCC_OscConfig+0x2e2>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80023f4: f7fe fd4e bl 8000e94 <HAL_GetTick>
80023f8: 4602 mov r2, r0
80023fa: 693b ldr r3, [r7, #16]
80023fc: 1ad3 subs r3, r2, r3
80023fe: 2b64 cmp r3, #100 @ 0x64
8002400: d901 bls.n 8002406 <HAL_RCC_OscConfig+0x2e2>
{
return HAL_TIMEOUT;
8002402: 2303 movs r3, #3
8002404: e262 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8002406: 4b88 ldr r3, [pc, #544] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002408: 681b ldr r3, [r3, #0]
800240a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800240e: 2b00 cmp r3, #0
8002410: d1f0 bne.n 80023f4 <HAL_RCC_OscConfig+0x2d0>
8002412: e000 b.n 8002416 <HAL_RCC_OscConfig+0x2f2>
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002414: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002416: 687b ldr r3, [r7, #4]
8002418: 681b ldr r3, [r3, #0]
800241a: f003 0302 and.w r3, r3, #2
800241e: 2b00 cmp r3, #0
8002420: d060 beq.n 80024e4 <HAL_RCC_OscConfig+0x3c0>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
8002422: 69bb ldr r3, [r7, #24]
8002424: 2b04 cmp r3, #4
8002426: d005 beq.n 8002434 <HAL_RCC_OscConfig+0x310>
8002428: 69bb ldr r3, [r7, #24]
800242a: 2b0c cmp r3, #12
800242c: d119 bne.n 8002462 <HAL_RCC_OscConfig+0x33e>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
800242e: 697b ldr r3, [r7, #20]
8002430: 2b02 cmp r3, #2
8002432: d116 bne.n 8002462 <HAL_RCC_OscConfig+0x33e>
{
/* When HSI is used as system clock it will not be disabled */
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8002434: 4b7c ldr r3, [pc, #496] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002436: 681b ldr r3, [r3, #0]
8002438: f403 6380 and.w r3, r3, #1024 @ 0x400
800243c: 2b00 cmp r3, #0
800243e: d005 beq.n 800244c <HAL_RCC_OscConfig+0x328>
8002440: 687b ldr r3, [r7, #4]
8002442: 68db ldr r3, [r3, #12]
8002444: 2b00 cmp r3, #0
8002446: d101 bne.n 800244c <HAL_RCC_OscConfig+0x328>
{
return HAL_ERROR;
8002448: 2301 movs r3, #1
800244a: e23f b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800244c: 4b76 ldr r3, [pc, #472] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800244e: 685b ldr r3, [r3, #4]
8002450: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
8002454: 687b ldr r3, [r7, #4]
8002456: 691b ldr r3, [r3, #16]
8002458: 061b lsls r3, r3, #24
800245a: 4973 ldr r1, [pc, #460] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800245c: 4313 orrs r3, r2
800245e: 604b str r3, [r1, #4]
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8002460: e040 b.n 80024e4 <HAL_RCC_OscConfig+0x3c0>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8002462: 687b ldr r3, [r7, #4]
8002464: 68db ldr r3, [r3, #12]
8002466: 2b00 cmp r3, #0
8002468: d023 beq.n 80024b2 <HAL_RCC_OscConfig+0x38e>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800246a: 4b6f ldr r3, [pc, #444] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800246c: 681b ldr r3, [r3, #0]
800246e: 4a6e ldr r2, [pc, #440] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002470: f443 7380 orr.w r3, r3, #256 @ 0x100
8002474: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002476: f7fe fd0d bl 8000e94 <HAL_GetTick>
800247a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800247c: e008 b.n 8002490 <HAL_RCC_OscConfig+0x36c>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800247e: f7fe fd09 bl 8000e94 <HAL_GetTick>
8002482: 4602 mov r2, r0
8002484: 693b ldr r3, [r7, #16]
8002486: 1ad3 subs r3, r2, r3
8002488: 2b02 cmp r3, #2
800248a: d901 bls.n 8002490 <HAL_RCC_OscConfig+0x36c>
{
return HAL_TIMEOUT;
800248c: 2303 movs r3, #3
800248e: e21d b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8002490: 4b65 ldr r3, [pc, #404] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002492: 681b ldr r3, [r3, #0]
8002494: f403 6380 and.w r3, r3, #1024 @ 0x400
8002498: 2b00 cmp r3, #0
800249a: d0f0 beq.n 800247e <HAL_RCC_OscConfig+0x35a>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800249c: 4b62 ldr r3, [pc, #392] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800249e: 685b ldr r3, [r3, #4]
80024a0: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
80024a4: 687b ldr r3, [r7, #4]
80024a6: 691b ldr r3, [r3, #16]
80024a8: 061b lsls r3, r3, #24
80024aa: 495f ldr r1, [pc, #380] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80024ac: 4313 orrs r3, r2
80024ae: 604b str r3, [r1, #4]
80024b0: e018 b.n 80024e4 <HAL_RCC_OscConfig+0x3c0>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80024b2: 4b5d ldr r3, [pc, #372] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80024b4: 681b ldr r3, [r3, #0]
80024b6: 4a5c ldr r2, [pc, #368] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80024b8: f423 7380 bic.w r3, r3, #256 @ 0x100
80024bc: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80024be: f7fe fce9 bl 8000e94 <HAL_GetTick>
80024c2: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
80024c4: e008 b.n 80024d8 <HAL_RCC_OscConfig+0x3b4>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80024c6: f7fe fce5 bl 8000e94 <HAL_GetTick>
80024ca: 4602 mov r2, r0
80024cc: 693b ldr r3, [r7, #16]
80024ce: 1ad3 subs r3, r2, r3
80024d0: 2b02 cmp r3, #2
80024d2: d901 bls.n 80024d8 <HAL_RCC_OscConfig+0x3b4>
{
return HAL_TIMEOUT;
80024d4: 2303 movs r3, #3
80024d6: e1f9 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
80024d8: 4b53 ldr r3, [pc, #332] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80024da: 681b ldr r3, [r3, #0]
80024dc: f403 6380 and.w r3, r3, #1024 @ 0x400
80024e0: 2b00 cmp r3, #0
80024e2: d1f0 bne.n 80024c6 <HAL_RCC_OscConfig+0x3a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80024e4: 687b ldr r3, [r7, #4]
80024e6: 681b ldr r3, [r3, #0]
80024e8: f003 0308 and.w r3, r3, #8
80024ec: 2b00 cmp r3, #0
80024ee: d03c beq.n 800256a <HAL_RCC_OscConfig+0x446>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80024f0: 687b ldr r3, [r7, #4]
80024f2: 695b ldr r3, [r3, #20]
80024f4: 2b00 cmp r3, #0
80024f6: d01c beq.n 8002532 <HAL_RCC_OscConfig+0x40e>
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
}
#endif /* RCC_CSR_LSIPREDIV */
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80024f8: 4b4b ldr r3, [pc, #300] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80024fa: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80024fe: 4a4a ldr r2, [pc, #296] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002500: f043 0301 orr.w r3, r3, #1
8002504: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002508: f7fe fcc4 bl 8000e94 <HAL_GetTick>
800250c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
800250e: e008 b.n 8002522 <HAL_RCC_OscConfig+0x3fe>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002510: f7fe fcc0 bl 8000e94 <HAL_GetTick>
8002514: 4602 mov r2, r0
8002516: 693b ldr r3, [r7, #16]
8002518: 1ad3 subs r3, r2, r3
800251a: 2b02 cmp r3, #2
800251c: d901 bls.n 8002522 <HAL_RCC_OscConfig+0x3fe>
{
return HAL_TIMEOUT;
800251e: 2303 movs r3, #3
8002520: e1d4 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8002522: 4b41 ldr r3, [pc, #260] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002524: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8002528: f003 0302 and.w r3, r3, #2
800252c: 2b00 cmp r3, #0
800252e: d0ef beq.n 8002510 <HAL_RCC_OscConfig+0x3ec>
8002530: e01b b.n 800256a <HAL_RCC_OscConfig+0x446>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002532: 4b3d ldr r3, [pc, #244] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002534: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8002538: 4a3b ldr r2, [pc, #236] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800253a: f023 0301 bic.w r3, r3, #1
800253e: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002542: f7fe fca7 bl 8000e94 <HAL_GetTick>
8002546: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8002548: e008 b.n 800255c <HAL_RCC_OscConfig+0x438>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800254a: f7fe fca3 bl 8000e94 <HAL_GetTick>
800254e: 4602 mov r2, r0
8002550: 693b ldr r3, [r7, #16]
8002552: 1ad3 subs r3, r2, r3
8002554: 2b02 cmp r3, #2
8002556: d901 bls.n 800255c <HAL_RCC_OscConfig+0x438>
{
return HAL_TIMEOUT;
8002558: 2303 movs r3, #3
800255a: e1b7 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
800255c: 4b32 ldr r3, [pc, #200] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800255e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8002562: f003 0302 and.w r3, r3, #2
8002566: 2b00 cmp r3, #0
8002568: d1ef bne.n 800254a <HAL_RCC_OscConfig+0x426>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800256a: 687b ldr r3, [r7, #4]
800256c: 681b ldr r3, [r3, #0]
800256e: f003 0304 and.w r3, r3, #4
8002572: 2b00 cmp r3, #0
8002574: f000 80a6 beq.w 80026c4 <HAL_RCC_OscConfig+0x5a0>
{
FlagStatus pwrclkchanged = RESET;
8002578: 2300 movs r3, #0
800257a: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
800257c: 4b2a ldr r3, [pc, #168] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800257e: 6d9b ldr r3, [r3, #88] @ 0x58
8002580: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002584: 2b00 cmp r3, #0
8002586: d10d bne.n 80025a4 <HAL_RCC_OscConfig+0x480>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002588: 4b27 ldr r3, [pc, #156] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800258a: 6d9b ldr r3, [r3, #88] @ 0x58
800258c: 4a26 ldr r2, [pc, #152] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800258e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002592: 6593 str r3, [r2, #88] @ 0x58
8002594: 4b24 ldr r3, [pc, #144] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002596: 6d9b ldr r3, [r3, #88] @ 0x58
8002598: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800259c: 60bb str r3, [r7, #8]
800259e: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80025a0: 2301 movs r3, #1
80025a2: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80025a4: 4b21 ldr r3, [pc, #132] @ (800262c <HAL_RCC_OscConfig+0x508>)
80025a6: 681b ldr r3, [r3, #0]
80025a8: f403 7380 and.w r3, r3, #256 @ 0x100
80025ac: 2b00 cmp r3, #0
80025ae: d118 bne.n 80025e2 <HAL_RCC_OscConfig+0x4be>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80025b0: 4b1e ldr r3, [pc, #120] @ (800262c <HAL_RCC_OscConfig+0x508>)
80025b2: 681b ldr r3, [r3, #0]
80025b4: 4a1d ldr r2, [pc, #116] @ (800262c <HAL_RCC_OscConfig+0x508>)
80025b6: f443 7380 orr.w r3, r3, #256 @ 0x100
80025ba: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80025bc: f7fe fc6a bl 8000e94 <HAL_GetTick>
80025c0: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80025c2: e008 b.n 80025d6 <HAL_RCC_OscConfig+0x4b2>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80025c4: f7fe fc66 bl 8000e94 <HAL_GetTick>
80025c8: 4602 mov r2, r0
80025ca: 693b ldr r3, [r7, #16]
80025cc: 1ad3 subs r3, r2, r3
80025ce: 2b02 cmp r3, #2
80025d0: d901 bls.n 80025d6 <HAL_RCC_OscConfig+0x4b2>
{
return HAL_TIMEOUT;
80025d2: 2303 movs r3, #3
80025d4: e17a b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80025d6: 4b15 ldr r3, [pc, #84] @ (800262c <HAL_RCC_OscConfig+0x508>)
80025d8: 681b ldr r3, [r3, #0]
80025da: f403 7380 and.w r3, r3, #256 @ 0x100
80025de: 2b00 cmp r3, #0
80025e0: d0f0 beq.n 80025c4 <HAL_RCC_OscConfig+0x4a0>
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
#else
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80025e2: 687b ldr r3, [r7, #4]
80025e4: 689b ldr r3, [r3, #8]
80025e6: 2b01 cmp r3, #1
80025e8: d108 bne.n 80025fc <HAL_RCC_OscConfig+0x4d8>
80025ea: 4b0f ldr r3, [pc, #60] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80025ec: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80025f0: 4a0d ldr r2, [pc, #52] @ (8002628 <HAL_RCC_OscConfig+0x504>)
80025f2: f043 0301 orr.w r3, r3, #1
80025f6: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80025fa: e029 b.n 8002650 <HAL_RCC_OscConfig+0x52c>
80025fc: 687b ldr r3, [r7, #4]
80025fe: 689b ldr r3, [r3, #8]
8002600: 2b05 cmp r3, #5
8002602: d115 bne.n 8002630 <HAL_RCC_OscConfig+0x50c>
8002604: 4b08 ldr r3, [pc, #32] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002606: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800260a: 4a07 ldr r2, [pc, #28] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800260c: f043 0304 orr.w r3, r3, #4
8002610: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8002614: 4b04 ldr r3, [pc, #16] @ (8002628 <HAL_RCC_OscConfig+0x504>)
8002616: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800261a: 4a03 ldr r2, [pc, #12] @ (8002628 <HAL_RCC_OscConfig+0x504>)
800261c: f043 0301 orr.w r3, r3, #1
8002620: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8002624: e014 b.n 8002650 <HAL_RCC_OscConfig+0x52c>
8002626: bf00 nop
8002628: 40021000 .word 0x40021000
800262c: 40007000 .word 0x40007000
8002630: 4b9c ldr r3, [pc, #624] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002632: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002636: 4a9b ldr r2, [pc, #620] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002638: f023 0301 bic.w r3, r3, #1
800263c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8002640: 4b98 ldr r3, [pc, #608] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002642: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002646: 4a97 ldr r2, [pc, #604] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002648: f023 0304 bic.w r3, r3, #4
800264c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
#endif /* RCC_BDCR_LSESYSDIS */
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8002650: 687b ldr r3, [r7, #4]
8002652: 689b ldr r3, [r3, #8]
8002654: 2b00 cmp r3, #0
8002656: d016 beq.n 8002686 <HAL_RCC_OscConfig+0x562>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002658: f7fe fc1c bl 8000e94 <HAL_GetTick>
800265c: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
800265e: e00a b.n 8002676 <HAL_RCC_OscConfig+0x552>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002660: f7fe fc18 bl 8000e94 <HAL_GetTick>
8002664: 4602 mov r2, r0
8002666: 693b ldr r3, [r7, #16]
8002668: 1ad3 subs r3, r2, r3
800266a: f241 3288 movw r2, #5000 @ 0x1388
800266e: 4293 cmp r3, r2
8002670: d901 bls.n 8002676 <HAL_RCC_OscConfig+0x552>
{
return HAL_TIMEOUT;
8002672: 2303 movs r3, #3
8002674: e12a b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8002676: 4b8b ldr r3, [pc, #556] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002678: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800267c: f003 0302 and.w r3, r3, #2
8002680: 2b00 cmp r3, #0
8002682: d0ed beq.n 8002660 <HAL_RCC_OscConfig+0x53c>
8002684: e015 b.n 80026b2 <HAL_RCC_OscConfig+0x58e>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002686: f7fe fc05 bl 8000e94 <HAL_GetTick>
800268a: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
800268c: e00a b.n 80026a4 <HAL_RCC_OscConfig+0x580>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800268e: f7fe fc01 bl 8000e94 <HAL_GetTick>
8002692: 4602 mov r2, r0
8002694: 693b ldr r3, [r7, #16]
8002696: 1ad3 subs r3, r2, r3
8002698: f241 3288 movw r2, #5000 @ 0x1388
800269c: 4293 cmp r3, r2
800269e: d901 bls.n 80026a4 <HAL_RCC_OscConfig+0x580>
{
return HAL_TIMEOUT;
80026a0: 2303 movs r3, #3
80026a2: e113 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
80026a4: 4b7f ldr r3, [pc, #508] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80026a6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80026aa: f003 0302 and.w r3, r3, #2
80026ae: 2b00 cmp r3, #0
80026b0: d1ed bne.n 800268e <HAL_RCC_OscConfig+0x56a>
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
80026b2: 7ffb ldrb r3, [r7, #31]
80026b4: 2b01 cmp r3, #1
80026b6: d105 bne.n 80026c4 <HAL_RCC_OscConfig+0x5a0>
{
__HAL_RCC_PWR_CLK_DISABLE();
80026b8: 4b7a ldr r3, [pc, #488] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80026ba: 6d9b ldr r3, [r3, #88] @ 0x58
80026bc: 4a79 ldr r2, [pc, #484] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80026be: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80026c2: 6593 str r3, [r2, #88] @ 0x58
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
80026c4: 687b ldr r3, [r7, #4]
80026c6: 6a9b ldr r3, [r3, #40] @ 0x28
80026c8: 2b00 cmp r3, #0
80026ca: f000 80fe beq.w 80028ca <HAL_RCC_OscConfig+0x7a6>
{
/* PLL On ? */
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
80026ce: 687b ldr r3, [r7, #4]
80026d0: 6a9b ldr r3, [r3, #40] @ 0x28
80026d2: 2b02 cmp r3, #2
80026d4: f040 80d0 bne.w 8002878 <HAL_RCC_OscConfig+0x754>
#endif /* RCC_PLLP_SUPPORT */
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Do nothing if PLL configuration is the unchanged */
pll_config = RCC->PLLCFGR;
80026d8: 4b72 ldr r3, [pc, #456] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80026da: 68db ldr r3, [r3, #12]
80026dc: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80026de: 697b ldr r3, [r7, #20]
80026e0: f003 0203 and.w r2, r3, #3
80026e4: 687b ldr r3, [r7, #4]
80026e6: 6adb ldr r3, [r3, #44] @ 0x2c
80026e8: 429a cmp r2, r3
80026ea: d130 bne.n 800274e <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
80026ec: 697b ldr r3, [r7, #20]
80026ee: f003 0270 and.w r2, r3, #112 @ 0x70
80026f2: 687b ldr r3, [r7, #4]
80026f4: 6b1b ldr r3, [r3, #48] @ 0x30
80026f6: 3b01 subs r3, #1
80026f8: 011b lsls r3, r3, #4
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80026fa: 429a cmp r2, r3
80026fc: d127 bne.n 800274e <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80026fe: 697b ldr r3, [r7, #20]
8002700: f403 42fe and.w r2, r3, #32512 @ 0x7f00
8002704: 687b ldr r3, [r7, #4]
8002706: 6b5b ldr r3, [r3, #52] @ 0x34
8002708: 021b lsls r3, r3, #8
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
800270a: 429a cmp r2, r3
800270c: d11f bne.n 800274e <HAL_RCC_OscConfig+0x62a>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
#else
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
800270e: 697b ldr r3, [r7, #20]
8002710: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002714: 687a ldr r2, [r7, #4]
8002716: 6b92 ldr r2, [r2, #56] @ 0x38
8002718: 2a07 cmp r2, #7
800271a: bf14 ite ne
800271c: 2201 movne r2, #1
800271e: 2200 moveq r2, #0
8002720: b2d2 uxtb r2, r2
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8002722: 4293 cmp r3, r2
8002724: d113 bne.n 800274e <HAL_RCC_OscConfig+0x62a>
#endif
#endif
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8002726: 697b ldr r3, [r7, #20]
8002728: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
800272c: 687b ldr r3, [r7, #4]
800272e: 6bdb ldr r3, [r3, #60] @ 0x3c
8002730: 085b lsrs r3, r3, #1
8002732: 3b01 subs r3, #1
8002734: 055b lsls r3, r3, #21
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
8002736: 429a cmp r2, r3
8002738: d109 bne.n 800274e <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
800273a: 697b ldr r3, [r7, #20]
800273c: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
8002740: 687b ldr r3, [r7, #4]
8002742: 6c1b ldr r3, [r3, #64] @ 0x40
8002744: 085b lsrs r3, r3, #1
8002746: 3b01 subs r3, #1
8002748: 065b lsls r3, r3, #25
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
800274a: 429a cmp r2, r3
800274c: d06e beq.n 800282c <HAL_RCC_OscConfig+0x708>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
800274e: 69bb ldr r3, [r7, #24]
8002750: 2b0c cmp r3, #12
8002752: d069 beq.n 8002828 <HAL_RCC_OscConfig+0x704>
{
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
/* Check if main PLL can be updated */
/* Not possible if the source is shared by other enabled PLLSAIx */
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
8002754: 4b53 ldr r3, [pc, #332] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002756: 681b ldr r3, [r3, #0]
8002758: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
800275c: 2b00 cmp r3, #0
800275e: d105 bne.n 800276c <HAL_RCC_OscConfig+0x648>
#if defined(RCC_PLLSAI2_SUPPORT)
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
8002760: 4b50 ldr r3, [pc, #320] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002762: 681b ldr r3, [r3, #0]
8002764: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002768: 2b00 cmp r3, #0
800276a: d001 beq.n 8002770 <HAL_RCC_OscConfig+0x64c>
#endif
)
{
return HAL_ERROR;
800276c: 2301 movs r3, #1
800276e: e0ad b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002770: 4b4c ldr r3, [pc, #304] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002772: 681b ldr r3, [r3, #0]
8002774: 4a4b ldr r2, [pc, #300] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002776: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800277a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800277c: f7fe fb8a bl 8000e94 <HAL_GetTick>
8002780: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002782: e008 b.n 8002796 <HAL_RCC_OscConfig+0x672>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002784: f7fe fb86 bl 8000e94 <HAL_GetTick>
8002788: 4602 mov r2, r0
800278a: 693b ldr r3, [r7, #16]
800278c: 1ad3 subs r3, r2, r3
800278e: 2b02 cmp r3, #2
8002790: d901 bls.n 8002796 <HAL_RCC_OscConfig+0x672>
{
return HAL_TIMEOUT;
8002792: 2303 movs r3, #3
8002794: e09a b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002796: 4b43 ldr r3, [pc, #268] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002798: 681b ldr r3, [r3, #0]
800279a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800279e: 2b00 cmp r3, #0
80027a0: d1f0 bne.n 8002784 <HAL_RCC_OscConfig+0x660>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80027a2: 4b40 ldr r3, [pc, #256] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80027a4: 68da ldr r2, [r3, #12]
80027a6: 4b40 ldr r3, [pc, #256] @ (80028a8 <HAL_RCC_OscConfig+0x784>)
80027a8: 4013 ands r3, r2
80027aa: 687a ldr r2, [r7, #4]
80027ac: 6ad1 ldr r1, [r2, #44] @ 0x2c
80027ae: 687a ldr r2, [r7, #4]
80027b0: 6b12 ldr r2, [r2, #48] @ 0x30
80027b2: 3a01 subs r2, #1
80027b4: 0112 lsls r2, r2, #4
80027b6: 4311 orrs r1, r2
80027b8: 687a ldr r2, [r7, #4]
80027ba: 6b52 ldr r2, [r2, #52] @ 0x34
80027bc: 0212 lsls r2, r2, #8
80027be: 4311 orrs r1, r2
80027c0: 687a ldr r2, [r7, #4]
80027c2: 6bd2 ldr r2, [r2, #60] @ 0x3c
80027c4: 0852 lsrs r2, r2, #1
80027c6: 3a01 subs r2, #1
80027c8: 0552 lsls r2, r2, #21
80027ca: 4311 orrs r1, r2
80027cc: 687a ldr r2, [r7, #4]
80027ce: 6c12 ldr r2, [r2, #64] @ 0x40
80027d0: 0852 lsrs r2, r2, #1
80027d2: 3a01 subs r2, #1
80027d4: 0652 lsls r2, r2, #25
80027d6: 4311 orrs r1, r2
80027d8: 687a ldr r2, [r7, #4]
80027da: 6b92 ldr r2, [r2, #56] @ 0x38
80027dc: 0912 lsrs r2, r2, #4
80027de: 0452 lsls r2, r2, #17
80027e0: 430a orrs r2, r1
80027e2: 4930 ldr r1, [pc, #192] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80027e4: 4313 orrs r3, r2
80027e6: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80027e8: 4b2e ldr r3, [pc, #184] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80027ea: 681b ldr r3, [r3, #0]
80027ec: 4a2d ldr r2, [pc, #180] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80027ee: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80027f2: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
80027f4: 4b2b ldr r3, [pc, #172] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80027f6: 68db ldr r3, [r3, #12]
80027f8: 4a2a ldr r2, [pc, #168] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
80027fa: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80027fe: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002800: f7fe fb48 bl 8000e94 <HAL_GetTick>
8002804: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002806: e008 b.n 800281a <HAL_RCC_OscConfig+0x6f6>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002808: f7fe fb44 bl 8000e94 <HAL_GetTick>
800280c: 4602 mov r2, r0
800280e: 693b ldr r3, [r7, #16]
8002810: 1ad3 subs r3, r2, r3
8002812: 2b02 cmp r3, #2
8002814: d901 bls.n 800281a <HAL_RCC_OscConfig+0x6f6>
{
return HAL_TIMEOUT;
8002816: 2303 movs r3, #3
8002818: e058 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800281a: 4b22 ldr r3, [pc, #136] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
800281c: 681b ldr r3, [r3, #0]
800281e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002822: 2b00 cmp r3, #0
8002824: d0f0 beq.n 8002808 <HAL_RCC_OscConfig+0x6e4>
if(sysclk_source != RCC_CFGR_SWS_PLL)
8002826: e050 b.n 80028ca <HAL_RCC_OscConfig+0x7a6>
}
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
8002828: 2301 movs r3, #1
800282a: e04f b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
else
{
/* PLL configuration is unchanged */
/* Re-enable PLL if it was disabled (ie. low power mode) */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800282c: 4b1d ldr r3, [pc, #116] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
800282e: 681b ldr r3, [r3, #0]
8002830: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002834: 2b00 cmp r3, #0
8002836: d148 bne.n 80028ca <HAL_RCC_OscConfig+0x7a6>
{
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002838: 4b1a ldr r3, [pc, #104] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
800283a: 681b ldr r3, [r3, #0]
800283c: 4a19 ldr r2, [pc, #100] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
800283e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002842: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8002844: 4b17 ldr r3, [pc, #92] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002846: 68db ldr r3, [r3, #12]
8002848: 4a16 ldr r2, [pc, #88] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
800284a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800284e: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002850: f7fe fb20 bl 8000e94 <HAL_GetTick>
8002854: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002856: e008 b.n 800286a <HAL_RCC_OscConfig+0x746>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002858: f7fe fb1c bl 8000e94 <HAL_GetTick>
800285c: 4602 mov r2, r0
800285e: 693b ldr r3, [r7, #16]
8002860: 1ad3 subs r3, r2, r3
8002862: 2b02 cmp r3, #2
8002864: d901 bls.n 800286a <HAL_RCC_OscConfig+0x746>
{
return HAL_TIMEOUT;
8002866: 2303 movs r3, #3
8002868: e030 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800286a: 4b0e ldr r3, [pc, #56] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
800286c: 681b ldr r3, [r3, #0]
800286e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002872: 2b00 cmp r3, #0
8002874: d0f0 beq.n 8002858 <HAL_RCC_OscConfig+0x734>
8002876: e028 b.n 80028ca <HAL_RCC_OscConfig+0x7a6>
}
}
else
{
/* Check that PLL is not used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
8002878: 69bb ldr r3, [r7, #24]
800287a: 2b0c cmp r3, #12
800287c: d023 beq.n 80028c6 <HAL_RCC_OscConfig+0x7a2>
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800287e: 4b09 ldr r3, [pc, #36] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002880: 681b ldr r3, [r3, #0]
8002882: 4a08 ldr r2, [pc, #32] @ (80028a4 <HAL_RCC_OscConfig+0x780>)
8002884: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8002888: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800288a: f7fe fb03 bl 8000e94 <HAL_GetTick>
800288e: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002890: e00c b.n 80028ac <HAL_RCC_OscConfig+0x788>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002892: f7fe faff bl 8000e94 <HAL_GetTick>
8002896: 4602 mov r2, r0
8002898: 693b ldr r3, [r7, #16]
800289a: 1ad3 subs r3, r2, r3
800289c: 2b02 cmp r3, #2
800289e: d905 bls.n 80028ac <HAL_RCC_OscConfig+0x788>
{
return HAL_TIMEOUT;
80028a0: 2303 movs r3, #3
80028a2: e013 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
80028a4: 40021000 .word 0x40021000
80028a8: f99d808c .word 0xf99d808c
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80028ac: 4b09 ldr r3, [pc, #36] @ (80028d4 <HAL_RCC_OscConfig+0x7b0>)
80028ae: 681b ldr r3, [r3, #0]
80028b0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80028b4: 2b00 cmp r3, #0
80028b6: d1ec bne.n 8002892 <HAL_RCC_OscConfig+0x76e>
}
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
80028b8: 4b06 ldr r3, [pc, #24] @ (80028d4 <HAL_RCC_OscConfig+0x7b0>)
80028ba: 68da ldr r2, [r3, #12]
80028bc: 4905 ldr r1, [pc, #20] @ (80028d4 <HAL_RCC_OscConfig+0x7b0>)
80028be: 4b06 ldr r3, [pc, #24] @ (80028d8 <HAL_RCC_OscConfig+0x7b4>)
80028c0: 4013 ands r3, r2
80028c2: 60cb str r3, [r1, #12]
80028c4: e001 b.n 80028ca <HAL_RCC_OscConfig+0x7a6>
#endif /* RCC_PLLSAI2_SUPPORT */
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
80028c6: 2301 movs r3, #1
80028c8: e000 b.n 80028cc <HAL_RCC_OscConfig+0x7a8>
}
}
}
return HAL_OK;
80028ca: 2300 movs r3, #0
}
80028cc: 4618 mov r0, r3
80028ce: 3720 adds r7, #32
80028d0: 46bd mov sp, r7
80028d2: bd80 pop {r7, pc}
80028d4: 40021000 .word 0x40021000
80028d8: feeefffc .word 0xfeeefffc
080028dc <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80028dc: b580 push {r7, lr}
80028de: b084 sub sp, #16
80028e0: af00 add r7, sp, #0
80028e2: 6078 str r0, [r7, #4]
80028e4: 6039 str r1, [r7, #0]
uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
HAL_StatusTypeDef status;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
80028e6: 687b ldr r3, [r7, #4]
80028e8: 2b00 cmp r3, #0
80028ea: d101 bne.n 80028f0 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80028ec: 2301 movs r3, #1
80028ee: e0e7 b.n 8002ac0 <HAL_RCC_ClockConfig+0x1e4>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80028f0: 4b75 ldr r3, [pc, #468] @ (8002ac8 <HAL_RCC_ClockConfig+0x1ec>)
80028f2: 681b ldr r3, [r3, #0]
80028f4: f003 0307 and.w r3, r3, #7
80028f8: 683a ldr r2, [r7, #0]
80028fa: 429a cmp r2, r3
80028fc: d910 bls.n 8002920 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80028fe: 4b72 ldr r3, [pc, #456] @ (8002ac8 <HAL_RCC_ClockConfig+0x1ec>)
8002900: 681b ldr r3, [r3, #0]
8002902: f023 0207 bic.w r2, r3, #7
8002906: 4970 ldr r1, [pc, #448] @ (8002ac8 <HAL_RCC_ClockConfig+0x1ec>)
8002908: 683b ldr r3, [r7, #0]
800290a: 4313 orrs r3, r2
800290c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800290e: 4b6e ldr r3, [pc, #440] @ (8002ac8 <HAL_RCC_ClockConfig+0x1ec>)
8002910: 681b ldr r3, [r3, #0]
8002912: f003 0307 and.w r3, r3, #7
8002916: 683a ldr r2, [r7, #0]
8002918: 429a cmp r2, r3
800291a: d001 beq.n 8002920 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
800291c: 2301 movs r3, #1
800291e: e0cf b.n 8002ac0 <HAL_RCC_ClockConfig+0x1e4>
}
}
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002920: 687b ldr r3, [r7, #4]
8002922: 681b ldr r3, [r3, #0]
8002924: f003 0302 and.w r3, r3, #2
8002928: 2b00 cmp r3, #0
800292a: d010 beq.n 800294e <HAL_RCC_ClockConfig+0x72>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
800292c: 687b ldr r3, [r7, #4]
800292e: 689a ldr r2, [r3, #8]
8002930: 4b66 ldr r3, [pc, #408] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002932: 689b ldr r3, [r3, #8]
8002934: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002938: 429a cmp r2, r3
800293a: d908 bls.n 800294e <HAL_RCC_ClockConfig+0x72>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
800293c: 4b63 ldr r3, [pc, #396] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
800293e: 689b ldr r3, [r3, #8]
8002940: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002944: 687b ldr r3, [r7, #4]
8002946: 689b ldr r3, [r3, #8]
8002948: 4960 ldr r1, [pc, #384] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
800294a: 4313 orrs r3, r2
800294c: 608b str r3, [r1, #8]
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800294e: 687b ldr r3, [r7, #4]
8002950: 681b ldr r3, [r3, #0]
8002952: f003 0301 and.w r3, r3, #1
8002956: 2b00 cmp r3, #0
8002958: d04c beq.n 80029f4 <HAL_RCC_ClockConfig+0x118>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800295a: 687b ldr r3, [r7, #4]
800295c: 685b ldr r3, [r3, #4]
800295e: 2b03 cmp r3, #3
8002960: d107 bne.n 8002972 <HAL_RCC_ClockConfig+0x96>
{
/* Check the PLL ready flag */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002962: 4b5a ldr r3, [pc, #360] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002964: 681b ldr r3, [r3, #0]
8002966: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800296a: 2b00 cmp r3, #0
800296c: d121 bne.n 80029b2 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800296e: 2301 movs r3, #1
8002970: e0a6 b.n 8002ac0 <HAL_RCC_ClockConfig+0x1e4>
#endif
}
else
{
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002972: 687b ldr r3, [r7, #4]
8002974: 685b ldr r3, [r3, #4]
8002976: 2b02 cmp r3, #2
8002978: d107 bne.n 800298a <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800297a: 4b54 ldr r3, [pc, #336] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
800297c: 681b ldr r3, [r3, #0]
800297e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002982: 2b00 cmp r3, #0
8002984: d115 bne.n 80029b2 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
8002986: 2301 movs r3, #1
8002988: e09a b.n 8002ac0 <HAL_RCC_ClockConfig+0x1e4>
}
}
/* MSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
800298a: 687b ldr r3, [r7, #4]
800298c: 685b ldr r3, [r3, #4]
800298e: 2b00 cmp r3, #0
8002990: d107 bne.n 80029a2 <HAL_RCC_ClockConfig+0xc6>
{
/* Check the MSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8002992: 4b4e ldr r3, [pc, #312] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002994: 681b ldr r3, [r3, #0]
8002996: f003 0302 and.w r3, r3, #2
800299a: 2b00 cmp r3, #0
800299c: d109 bne.n 80029b2 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800299e: 2301 movs r3, #1
80029a0: e08e b.n 8002ac0 <HAL_RCC_ClockConfig+0x1e4>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
80029a2: 4b4a ldr r3, [pc, #296] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
80029a4: 681b ldr r3, [r3, #0]
80029a6: f403 6380 and.w r3, r3, #1024 @ 0x400
80029aa: 2b00 cmp r3, #0
80029ac: d101 bne.n 80029b2 <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
80029ae: 2301 movs r3, #1
80029b0: e086 b.n 8002ac0 <HAL_RCC_ClockConfig+0x1e4>
}
#endif
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
80029b2: 4b46 ldr r3, [pc, #280] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
80029b4: 689b ldr r3, [r3, #8]
80029b6: f023 0203 bic.w r2, r3, #3
80029ba: 687b ldr r3, [r7, #4]
80029bc: 685b ldr r3, [r3, #4]
80029be: 4943 ldr r1, [pc, #268] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
80029c0: 4313 orrs r3, r2
80029c2: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80029c4: f7fe fa66 bl 8000e94 <HAL_GetTick>
80029c8: 60f8 str r0, [r7, #12]
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80029ca: e00a b.n 80029e2 <HAL_RCC_ClockConfig+0x106>
{
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80029cc: f7fe fa62 bl 8000e94 <HAL_GetTick>
80029d0: 4602 mov r2, r0
80029d2: 68fb ldr r3, [r7, #12]
80029d4: 1ad3 subs r3, r2, r3
80029d6: f241 3288 movw r2, #5000 @ 0x1388
80029da: 4293 cmp r3, r2
80029dc: d901 bls.n 80029e2 <HAL_RCC_ClockConfig+0x106>
{
return HAL_TIMEOUT;
80029de: 2303 movs r3, #3
80029e0: e06e b.n 8002ac0 <HAL_RCC_ClockConfig+0x1e4>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80029e2: 4b3a ldr r3, [pc, #232] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
80029e4: 689b ldr r3, [r3, #8]
80029e6: f003 020c and.w r2, r3, #12
80029ea: 687b ldr r3, [r7, #4]
80029ec: 685b ldr r3, [r3, #4]
80029ee: 009b lsls r3, r3, #2
80029f0: 429a cmp r2, r3
80029f2: d1eb bne.n 80029cc <HAL_RCC_ClockConfig+0xf0>
}
#endif
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80029f4: 687b ldr r3, [r7, #4]
80029f6: 681b ldr r3, [r3, #0]
80029f8: f003 0302 and.w r3, r3, #2
80029fc: 2b00 cmp r3, #0
80029fe: d010 beq.n 8002a22 <HAL_RCC_ClockConfig+0x146>
{
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
8002a00: 687b ldr r3, [r7, #4]
8002a02: 689a ldr r2, [r3, #8]
8002a04: 4b31 ldr r3, [pc, #196] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002a06: 689b ldr r3, [r3, #8]
8002a08: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002a0c: 429a cmp r2, r3
8002a0e: d208 bcs.n 8002a22 <HAL_RCC_ClockConfig+0x146>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002a10: 4b2e ldr r3, [pc, #184] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002a12: 689b ldr r3, [r3, #8]
8002a14: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002a18: 687b ldr r3, [r7, #4]
8002a1a: 689b ldr r3, [r3, #8]
8002a1c: 492b ldr r1, [pc, #172] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002a1e: 4313 orrs r3, r2
8002a20: 608b str r3, [r1, #8]
}
}
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8002a22: 4b29 ldr r3, [pc, #164] @ (8002ac8 <HAL_RCC_ClockConfig+0x1ec>)
8002a24: 681b ldr r3, [r3, #0]
8002a26: f003 0307 and.w r3, r3, #7
8002a2a: 683a ldr r2, [r7, #0]
8002a2c: 429a cmp r2, r3
8002a2e: d210 bcs.n 8002a52 <HAL_RCC_ClockConfig+0x176>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002a30: 4b25 ldr r3, [pc, #148] @ (8002ac8 <HAL_RCC_ClockConfig+0x1ec>)
8002a32: 681b ldr r3, [r3, #0]
8002a34: f023 0207 bic.w r2, r3, #7
8002a38: 4923 ldr r1, [pc, #140] @ (8002ac8 <HAL_RCC_ClockConfig+0x1ec>)
8002a3a: 683b ldr r3, [r7, #0]
8002a3c: 4313 orrs r3, r2
8002a3e: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002a40: 4b21 ldr r3, [pc, #132] @ (8002ac8 <HAL_RCC_ClockConfig+0x1ec>)
8002a42: 681b ldr r3, [r3, #0]
8002a44: f003 0307 and.w r3, r3, #7
8002a48: 683a ldr r2, [r7, #0]
8002a4a: 429a cmp r2, r3
8002a4c: d001 beq.n 8002a52 <HAL_RCC_ClockConfig+0x176>
{
return HAL_ERROR;
8002a4e: 2301 movs r3, #1
8002a50: e036 b.n 8002ac0 <HAL_RCC_ClockConfig+0x1e4>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002a52: 687b ldr r3, [r7, #4]
8002a54: 681b ldr r3, [r3, #0]
8002a56: f003 0304 and.w r3, r3, #4
8002a5a: 2b00 cmp r3, #0
8002a5c: d008 beq.n 8002a70 <HAL_RCC_ClockConfig+0x194>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8002a5e: 4b1b ldr r3, [pc, #108] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002a60: 689b ldr r3, [r3, #8]
8002a62: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8002a66: 687b ldr r3, [r7, #4]
8002a68: 68db ldr r3, [r3, #12]
8002a6a: 4918 ldr r1, [pc, #96] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002a6c: 4313 orrs r3, r2
8002a6e: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002a70: 687b ldr r3, [r7, #4]
8002a72: 681b ldr r3, [r3, #0]
8002a74: f003 0308 and.w r3, r3, #8
8002a78: 2b00 cmp r3, #0
8002a7a: d009 beq.n 8002a90 <HAL_RCC_ClockConfig+0x1b4>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8002a7c: 4b13 ldr r3, [pc, #76] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002a7e: 689b ldr r3, [r3, #8]
8002a80: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8002a84: 687b ldr r3, [r7, #4]
8002a86: 691b ldr r3, [r3, #16]
8002a88: 00db lsls r3, r3, #3
8002a8a: 4910 ldr r1, [pc, #64] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002a8c: 4313 orrs r3, r2
8002a8e: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8002a90: f000 f824 bl 8002adc <HAL_RCC_GetSysClockFreq>
8002a94: 4602 mov r2, r0
8002a96: 4b0d ldr r3, [pc, #52] @ (8002acc <HAL_RCC_ClockConfig+0x1f0>)
8002a98: 689b ldr r3, [r3, #8]
8002a9a: 091b lsrs r3, r3, #4
8002a9c: f003 030f and.w r3, r3, #15
8002aa0: 490b ldr r1, [pc, #44] @ (8002ad0 <HAL_RCC_ClockConfig+0x1f4>)
8002aa2: 5ccb ldrb r3, [r1, r3]
8002aa4: f003 031f and.w r3, r3, #31
8002aa8: fa22 f303 lsr.w r3, r2, r3
8002aac: 4a09 ldr r2, [pc, #36] @ (8002ad4 <HAL_RCC_ClockConfig+0x1f8>)
8002aae: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8002ab0: 4b09 ldr r3, [pc, #36] @ (8002ad8 <HAL_RCC_ClockConfig+0x1fc>)
8002ab2: 681b ldr r3, [r3, #0]
8002ab4: 4618 mov r0, r3
8002ab6: f7fe f99d bl 8000df4 <HAL_InitTick>
8002aba: 4603 mov r3, r0
8002abc: 72fb strb r3, [r7, #11]
return status;
8002abe: 7afb ldrb r3, [r7, #11]
}
8002ac0: 4618 mov r0, r3
8002ac2: 3710 adds r7, #16
8002ac4: 46bd mov sp, r7
8002ac6: bd80 pop {r7, pc}
8002ac8: 40022000 .word 0x40022000
8002acc: 40021000 .word 0x40021000
8002ad0: 08004e88 .word 0x08004e88
8002ad4: 20000000 .word 0x20000000
8002ad8: 20000004 .word 0x20000004
08002adc <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002adc: b480 push {r7}
8002ade: b089 sub sp, #36 @ 0x24
8002ae0: af00 add r7, sp, #0
uint32_t msirange = 0U, sysclockfreq = 0U;
8002ae2: 2300 movs r3, #0
8002ae4: 61fb str r3, [r7, #28]
8002ae6: 2300 movs r3, #0
8002ae8: 61bb str r3, [r7, #24]
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
uint32_t sysclk_source, pll_oscsource;
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8002aea: 4b3e ldr r3, [pc, #248] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002aec: 689b ldr r3, [r3, #8]
8002aee: f003 030c and.w r3, r3, #12
8002af2: 613b str r3, [r7, #16]
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
8002af4: 4b3b ldr r3, [pc, #236] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002af6: 68db ldr r3, [r3, #12]
8002af8: f003 0303 and.w r3, r3, #3
8002afc: 60fb str r3, [r7, #12]
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
8002afe: 693b ldr r3, [r7, #16]
8002b00: 2b00 cmp r3, #0
8002b02: d005 beq.n 8002b10 <HAL_RCC_GetSysClockFreq+0x34>
8002b04: 693b ldr r3, [r7, #16]
8002b06: 2b0c cmp r3, #12
8002b08: d121 bne.n 8002b4e <HAL_RCC_GetSysClockFreq+0x72>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
8002b0a: 68fb ldr r3, [r7, #12]
8002b0c: 2b01 cmp r3, #1
8002b0e: d11e bne.n 8002b4e <HAL_RCC_GetSysClockFreq+0x72>
{
/* MSI or PLL with MSI source used as system clock source */
/* Get SYSCLK source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
8002b10: 4b34 ldr r3, [pc, #208] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002b12: 681b ldr r3, [r3, #0]
8002b14: f003 0308 and.w r3, r3, #8
8002b18: 2b00 cmp r3, #0
8002b1a: d107 bne.n 8002b2c <HAL_RCC_GetSysClockFreq+0x50>
{ /* MSISRANGE from RCC_CSR applies */
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
8002b1c: 4b31 ldr r3, [pc, #196] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002b1e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8002b22: 0a1b lsrs r3, r3, #8
8002b24: f003 030f and.w r3, r3, #15
8002b28: 61fb str r3, [r7, #28]
8002b2a: e005 b.n 8002b38 <HAL_RCC_GetSysClockFreq+0x5c>
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
8002b2c: 4b2d ldr r3, [pc, #180] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002b2e: 681b ldr r3, [r3, #0]
8002b30: 091b lsrs r3, r3, #4
8002b32: f003 030f and.w r3, r3, #15
8002b36: 61fb str r3, [r7, #28]
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
8002b38: 4a2b ldr r2, [pc, #172] @ (8002be8 <HAL_RCC_GetSysClockFreq+0x10c>)
8002b3a: 69fb ldr r3, [r7, #28]
8002b3c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8002b40: 61fb str r3, [r7, #28]
if(sysclk_source == RCC_CFGR_SWS_MSI)
8002b42: 693b ldr r3, [r7, #16]
8002b44: 2b00 cmp r3, #0
8002b46: d10d bne.n 8002b64 <HAL_RCC_GetSysClockFreq+0x88>
{
/* MSI used as system clock source */
sysclockfreq = msirange;
8002b48: 69fb ldr r3, [r7, #28]
8002b4a: 61bb str r3, [r7, #24]
if(sysclk_source == RCC_CFGR_SWS_MSI)
8002b4c: e00a b.n 8002b64 <HAL_RCC_GetSysClockFreq+0x88>
}
}
else if(sysclk_source == RCC_CFGR_SWS_HSI)
8002b4e: 693b ldr r3, [r7, #16]
8002b50: 2b04 cmp r3, #4
8002b52: d102 bne.n 8002b5a <HAL_RCC_GetSysClockFreq+0x7e>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
8002b54: 4b25 ldr r3, [pc, #148] @ (8002bec <HAL_RCC_GetSysClockFreq+0x110>)
8002b56: 61bb str r3, [r7, #24]
8002b58: e004 b.n 8002b64 <HAL_RCC_GetSysClockFreq+0x88>
}
else if(sysclk_source == RCC_CFGR_SWS_HSE)
8002b5a: 693b ldr r3, [r7, #16]
8002b5c: 2b08 cmp r3, #8
8002b5e: d101 bne.n 8002b64 <HAL_RCC_GetSysClockFreq+0x88>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8002b60: 4b23 ldr r3, [pc, #140] @ (8002bf0 <HAL_RCC_GetSysClockFreq+0x114>)
8002b62: 61bb str r3, [r7, #24]
else
{
/* unexpected case: sysclockfreq at 0 */
}
if(sysclk_source == RCC_CFGR_SWS_PLL)
8002b64: 693b ldr r3, [r7, #16]
8002b66: 2b0c cmp r3, #12
8002b68: d134 bne.n 8002bd4 <HAL_RCC_GetSysClockFreq+0xf8>
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8002b6a: 4b1e ldr r3, [pc, #120] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002b6c: 68db ldr r3, [r3, #12]
8002b6e: f003 0303 and.w r3, r3, #3
8002b72: 60bb str r3, [r7, #8]
switch (pllsource)
8002b74: 68bb ldr r3, [r7, #8]
8002b76: 2b02 cmp r3, #2
8002b78: d003 beq.n 8002b82 <HAL_RCC_GetSysClockFreq+0xa6>
8002b7a: 68bb ldr r3, [r7, #8]
8002b7c: 2b03 cmp r3, #3
8002b7e: d003 beq.n 8002b88 <HAL_RCC_GetSysClockFreq+0xac>
8002b80: e005 b.n 8002b8e <HAL_RCC_GetSysClockFreq+0xb2>
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllvco = HSI_VALUE;
8002b82: 4b1a ldr r3, [pc, #104] @ (8002bec <HAL_RCC_GetSysClockFreq+0x110>)
8002b84: 617b str r3, [r7, #20]
break;
8002b86: e005 b.n 8002b94 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = HSE_VALUE;
8002b88: 4b19 ldr r3, [pc, #100] @ (8002bf0 <HAL_RCC_GetSysClockFreq+0x114>)
8002b8a: 617b str r3, [r7, #20]
break;
8002b8c: e002 b.n 8002b94 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default:
pllvco = msirange;
8002b8e: 69fb ldr r3, [r7, #28]
8002b90: 617b str r3, [r7, #20]
break;
8002b92: bf00 nop
}
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8002b94: 4b13 ldr r3, [pc, #76] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002b96: 68db ldr r3, [r3, #12]
8002b98: 091b lsrs r3, r3, #4
8002b9a: f003 0307 and.w r3, r3, #7
8002b9e: 3301 adds r3, #1
8002ba0: 607b str r3, [r7, #4]
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
8002ba2: 4b10 ldr r3, [pc, #64] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002ba4: 68db ldr r3, [r3, #12]
8002ba6: 0a1b lsrs r3, r3, #8
8002ba8: f003 037f and.w r3, r3, #127 @ 0x7f
8002bac: 697a ldr r2, [r7, #20]
8002bae: fb03 f202 mul.w r2, r3, r2
8002bb2: 687b ldr r3, [r7, #4]
8002bb4: fbb2 f3f3 udiv r3, r2, r3
8002bb8: 617b str r3, [r7, #20]
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8002bba: 4b0a ldr r3, [pc, #40] @ (8002be4 <HAL_RCC_GetSysClockFreq+0x108>)
8002bbc: 68db ldr r3, [r3, #12]
8002bbe: 0e5b lsrs r3, r3, #25
8002bc0: f003 0303 and.w r3, r3, #3
8002bc4: 3301 adds r3, #1
8002bc6: 005b lsls r3, r3, #1
8002bc8: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllr;
8002bca: 697a ldr r2, [r7, #20]
8002bcc: 683b ldr r3, [r7, #0]
8002bce: fbb2 f3f3 udiv r3, r2, r3
8002bd2: 61bb str r3, [r7, #24]
}
return sysclockfreq;
8002bd4: 69bb ldr r3, [r7, #24]
}
8002bd6: 4618 mov r0, r3
8002bd8: 3724 adds r7, #36 @ 0x24
8002bda: 46bd mov sp, r7
8002bdc: f85d 7b04 ldr.w r7, [sp], #4
8002be0: 4770 bx lr
8002be2: bf00 nop
8002be4: 40021000 .word 0x40021000
8002be8: 08004ea0 .word 0x08004ea0
8002bec: 00f42400 .word 0x00f42400
8002bf0: 007a1200 .word 0x007a1200
08002bf4 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002bf4: b480 push {r7}
8002bf6: af00 add r7, sp, #0
return SystemCoreClock;
8002bf8: 4b03 ldr r3, [pc, #12] @ (8002c08 <HAL_RCC_GetHCLKFreq+0x14>)
8002bfa: 681b ldr r3, [r3, #0]
}
8002bfc: 4618 mov r0, r3
8002bfe: 46bd mov sp, r7
8002c00: f85d 7b04 ldr.w r7, [sp], #4
8002c04: 4770 bx lr
8002c06: bf00 nop
8002c08: 20000000 .word 0x20000000
08002c0c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002c0c: b580 push {r7, lr}
8002c0e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
8002c10: f7ff fff0 bl 8002bf4 <HAL_RCC_GetHCLKFreq>
8002c14: 4602 mov r2, r0
8002c16: 4b06 ldr r3, [pc, #24] @ (8002c30 <HAL_RCC_GetPCLK1Freq+0x24>)
8002c18: 689b ldr r3, [r3, #8]
8002c1a: 0a1b lsrs r3, r3, #8
8002c1c: f003 0307 and.w r3, r3, #7
8002c20: 4904 ldr r1, [pc, #16] @ (8002c34 <HAL_RCC_GetPCLK1Freq+0x28>)
8002c22: 5ccb ldrb r3, [r1, r3]
8002c24: f003 031f and.w r3, r3, #31
8002c28: fa22 f303 lsr.w r3, r2, r3
}
8002c2c: 4618 mov r0, r3
8002c2e: bd80 pop {r7, pc}
8002c30: 40021000 .word 0x40021000
8002c34: 08004e98 .word 0x08004e98
08002c38 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002c38: b580 push {r7, lr}
8002c3a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
8002c3c: f7ff ffda bl 8002bf4 <HAL_RCC_GetHCLKFreq>
8002c40: 4602 mov r2, r0
8002c42: 4b06 ldr r3, [pc, #24] @ (8002c5c <HAL_RCC_GetPCLK2Freq+0x24>)
8002c44: 689b ldr r3, [r3, #8]
8002c46: 0adb lsrs r3, r3, #11
8002c48: f003 0307 and.w r3, r3, #7
8002c4c: 4904 ldr r1, [pc, #16] @ (8002c60 <HAL_RCC_GetPCLK2Freq+0x28>)
8002c4e: 5ccb ldrb r3, [r1, r3]
8002c50: f003 031f and.w r3, r3, #31
8002c54: fa22 f303 lsr.w r3, r2, r3
}
8002c58: 4618 mov r0, r3
8002c5a: bd80 pop {r7, pc}
8002c5c: 40021000 .word 0x40021000
8002c60: 08004e98 .word 0x08004e98
08002c64 <RCC_SetFlashLatencyFromMSIRange>:
voltage range.
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
8002c64: b580 push {r7, lr}
8002c66: b086 sub sp, #24
8002c68: af00 add r7, sp, #0
8002c6a: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
8002c6c: 2300 movs r3, #0
8002c6e: 613b str r3, [r7, #16]
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
8002c70: 4b2a ldr r3, [pc, #168] @ (8002d1c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002c72: 6d9b ldr r3, [r3, #88] @ 0x58
8002c74: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002c78: 2b00 cmp r3, #0
8002c7a: d003 beq.n 8002c84 <RCC_SetFlashLatencyFromMSIRange+0x20>
{
vos = HAL_PWREx_GetVoltageRange();
8002c7c: f7ff f9ee bl 800205c <HAL_PWREx_GetVoltageRange>
8002c80: 6178 str r0, [r7, #20]
8002c82: e014 b.n 8002cae <RCC_SetFlashLatencyFromMSIRange+0x4a>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
8002c84: 4b25 ldr r3, [pc, #148] @ (8002d1c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002c86: 6d9b ldr r3, [r3, #88] @ 0x58
8002c88: 4a24 ldr r2, [pc, #144] @ (8002d1c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002c8a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002c8e: 6593 str r3, [r2, #88] @ 0x58
8002c90: 4b22 ldr r3, [pc, #136] @ (8002d1c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002c92: 6d9b ldr r3, [r3, #88] @ 0x58
8002c94: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002c98: 60fb str r3, [r7, #12]
8002c9a: 68fb ldr r3, [r7, #12]
vos = HAL_PWREx_GetVoltageRange();
8002c9c: f7ff f9de bl 800205c <HAL_PWREx_GetVoltageRange>
8002ca0: 6178 str r0, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
8002ca2: 4b1e ldr r3, [pc, #120] @ (8002d1c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002ca4: 6d9b ldr r3, [r3, #88] @ 0x58
8002ca6: 4a1d ldr r2, [pc, #116] @ (8002d1c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002ca8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002cac: 6593 str r3, [r2, #88] @ 0x58
}
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
8002cae: 697b ldr r3, [r7, #20]
8002cb0: f5b3 7f00 cmp.w r3, #512 @ 0x200
8002cb4: d10b bne.n 8002cce <RCC_SetFlashLatencyFromMSIRange+0x6a>
{
if(msirange > RCC_MSIRANGE_8)
8002cb6: 687b ldr r3, [r7, #4]
8002cb8: 2b80 cmp r3, #128 @ 0x80
8002cba: d919 bls.n 8002cf0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI > 16Mhz */
if(msirange > RCC_MSIRANGE_10)
8002cbc: 687b ldr r3, [r7, #4]
8002cbe: 2ba0 cmp r3, #160 @ 0xa0
8002cc0: d902 bls.n 8002cc8 <RCC_SetFlashLatencyFromMSIRange+0x64>
{
/* MSI 48Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
8002cc2: 2302 movs r3, #2
8002cc4: 613b str r3, [r7, #16]
8002cc6: e013 b.n 8002cf0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
/* MSI 24Mhz or 32Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
8002cc8: 2301 movs r3, #1
8002cca: 613b str r3, [r7, #16]
8002ccc: e010 b.n 8002cf0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
latency = FLASH_LATENCY_1; /* 1WS */
}
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
}
#else
if(msirange > RCC_MSIRANGE_8)
8002cce: 687b ldr r3, [r7, #4]
8002cd0: 2b80 cmp r3, #128 @ 0x80
8002cd2: d902 bls.n 8002cda <RCC_SetFlashLatencyFromMSIRange+0x76>
{
/* MSI > 16Mhz */
latency = FLASH_LATENCY_3; /* 3WS */
8002cd4: 2303 movs r3, #3
8002cd6: 613b str r3, [r7, #16]
8002cd8: e00a b.n 8002cf0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
if(msirange == RCC_MSIRANGE_8)
8002cda: 687b ldr r3, [r7, #4]
8002cdc: 2b80 cmp r3, #128 @ 0x80
8002cde: d102 bne.n 8002ce6 <RCC_SetFlashLatencyFromMSIRange+0x82>
{
/* MSI 16Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
8002ce0: 2302 movs r3, #2
8002ce2: 613b str r3, [r7, #16]
8002ce4: e004 b.n 8002cf0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else if(msirange == RCC_MSIRANGE_7)
8002ce6: 687b ldr r3, [r7, #4]
8002ce8: 2b70 cmp r3, #112 @ 0x70
8002cea: d101 bne.n 8002cf0 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
8002cec: 2301 movs r3, #1
8002cee: 613b str r3, [r7, #16]
}
}
#endif
}
__HAL_FLASH_SET_LATENCY(latency);
8002cf0: 4b0b ldr r3, [pc, #44] @ (8002d20 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002cf2: 681b ldr r3, [r3, #0]
8002cf4: f023 0207 bic.w r2, r3, #7
8002cf8: 4909 ldr r1, [pc, #36] @ (8002d20 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002cfa: 693b ldr r3, [r7, #16]
8002cfc: 4313 orrs r3, r2
8002cfe: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
8002d00: 4b07 ldr r3, [pc, #28] @ (8002d20 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002d02: 681b ldr r3, [r3, #0]
8002d04: f003 0307 and.w r3, r3, #7
8002d08: 693a ldr r2, [r7, #16]
8002d0a: 429a cmp r2, r3
8002d0c: d001 beq.n 8002d12 <RCC_SetFlashLatencyFromMSIRange+0xae>
{
return HAL_ERROR;
8002d0e: 2301 movs r3, #1
8002d10: e000 b.n 8002d14 <RCC_SetFlashLatencyFromMSIRange+0xb0>
}
return HAL_OK;
8002d12: 2300 movs r3, #0
}
8002d14: 4618 mov r0, r3
8002d16: 3718 adds r7, #24
8002d18: 46bd mov sp, r7
8002d1a: bd80 pop {r7, pc}
8002d1c: 40021000 .word 0x40021000
8002d20: 40022000 .word 0x40022000
08002d24 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8002d24: b580 push {r7, lr}
8002d26: b086 sub sp, #24
8002d28: af00 add r7, sp, #0
8002d2a: 6078 str r0, [r7, #4]
uint32_t tmpregister, tickstart; /* no init needed */
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8002d2c: 2300 movs r3, #0
8002d2e: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8002d30: 2300 movs r3, #0
8002d32: 74bb strb r3, [r7, #18]
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
8002d34: 687b ldr r3, [r7, #4]
8002d36: 681b ldr r3, [r3, #0]
8002d38: f403 6300 and.w r3, r3, #2048 @ 0x800
8002d3c: 2b00 cmp r3, #0
8002d3e: d041 beq.n 8002dc4 <HAL_RCCEx_PeriphCLKConfig+0xa0>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
switch(PeriphClkInit->Sai1ClockSelection)
8002d40: 687b ldr r3, [r7, #4]
8002d42: 6e5b ldr r3, [r3, #100] @ 0x64
8002d44: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
8002d48: d02a beq.n 8002da0 <HAL_RCCEx_PeriphCLKConfig+0x7c>
8002d4a: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
8002d4e: d824 bhi.n 8002d9a <HAL_RCCEx_PeriphCLKConfig+0x76>
8002d50: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
8002d54: d008 beq.n 8002d68 <HAL_RCCEx_PeriphCLKConfig+0x44>
8002d56: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
8002d5a: d81e bhi.n 8002d9a <HAL_RCCEx_PeriphCLKConfig+0x76>
8002d5c: 2b00 cmp r3, #0
8002d5e: d00a beq.n 8002d76 <HAL_RCCEx_PeriphCLKConfig+0x52>
8002d60: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8002d64: d010 beq.n 8002d88 <HAL_RCCEx_PeriphCLKConfig+0x64>
8002d66: e018 b.n 8002d9a <HAL_RCCEx_PeriphCLKConfig+0x76>
{
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
/* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
8002d68: 4b86 ldr r3, [pc, #536] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002d6a: 68db ldr r3, [r3, #12]
8002d6c: 4a85 ldr r2, [pc, #532] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002d6e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002d72: 60d3 str r3, [r2, #12]
#else
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
/* SAI1 clock source config set later after clock selection check */
break;
8002d74: e015 b.n 8002da2 <HAL_RCCEx_PeriphCLKConfig+0x7e>
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
8002d76: 687b ldr r3, [r7, #4]
8002d78: 3304 adds r3, #4
8002d7a: 2100 movs r1, #0
8002d7c: 4618 mov r0, r3
8002d7e: f000 fabb bl 80032f8 <RCCEx_PLLSAI1_Config>
8002d82: 4603 mov r3, r0
8002d84: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
8002d86: e00c b.n 8002da2 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#if defined(RCC_PLLSAI2_SUPPORT)
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
8002d88: 687b ldr r3, [r7, #4]
8002d8a: 3320 adds r3, #32
8002d8c: 2100 movs r1, #0
8002d8e: 4618 mov r0, r3
8002d90: f000 fba6 bl 80034e0 <RCCEx_PLLSAI2_Config>
8002d94: 4603 mov r3, r0
8002d96: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
8002d98: e003 b.n 8002da2 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI1 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
8002d9a: 2301 movs r3, #1
8002d9c: 74fb strb r3, [r7, #19]
break;
8002d9e: e000 b.n 8002da2 <HAL_RCCEx_PeriphCLKConfig+0x7e>
break;
8002da0: bf00 nop
}
if(ret == HAL_OK)
8002da2: 7cfb ldrb r3, [r7, #19]
8002da4: 2b00 cmp r3, #0
8002da6: d10b bne.n 8002dc0 <HAL_RCCEx_PeriphCLKConfig+0x9c>
{
/* Set the source of SAI1 clock*/
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8002da8: 4b76 ldr r3, [pc, #472] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002daa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002dae: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8002db2: 687b ldr r3, [r7, #4]
8002db4: 6e5b ldr r3, [r3, #100] @ 0x64
8002db6: 4973 ldr r1, [pc, #460] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002db8: 4313 orrs r3, r2
8002dba: f8c1 3088 str.w r3, [r1, #136] @ 0x88
8002dbe: e001 b.n 8002dc4 <HAL_RCCEx_PeriphCLKConfig+0xa0>
}
else
{
/* set overall return value */
status = ret;
8002dc0: 7cfb ldrb r3, [r7, #19]
8002dc2: 74bb strb r3, [r7, #18]
#endif /* SAI1 */
#if defined(SAI2)
/*-------------------------- SAI2 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
8002dc4: 687b ldr r3, [r7, #4]
8002dc6: 681b ldr r3, [r3, #0]
8002dc8: f403 5380 and.w r3, r3, #4096 @ 0x1000
8002dcc: 2b00 cmp r3, #0
8002dce: d041 beq.n 8002e54 <HAL_RCCEx_PeriphCLKConfig+0x130>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
switch(PeriphClkInit->Sai2ClockSelection)
8002dd0: 687b ldr r3, [r7, #4]
8002dd2: 6e9b ldr r3, [r3, #104] @ 0x68
8002dd4: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
8002dd8: d02a beq.n 8002e30 <HAL_RCCEx_PeriphCLKConfig+0x10c>
8002dda: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
8002dde: d824 bhi.n 8002e2a <HAL_RCCEx_PeriphCLKConfig+0x106>
8002de0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8002de4: d008 beq.n 8002df8 <HAL_RCCEx_PeriphCLKConfig+0xd4>
8002de6: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8002dea: d81e bhi.n 8002e2a <HAL_RCCEx_PeriphCLKConfig+0x106>
8002dec: 2b00 cmp r3, #0
8002dee: d00a beq.n 8002e06 <HAL_RCCEx_PeriphCLKConfig+0xe2>
8002df0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8002df4: d010 beq.n 8002e18 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8002df6: e018 b.n 8002e2a <HAL_RCCEx_PeriphCLKConfig+0x106>
{
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
/* Enable SAI Clock output generated from System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
8002df8: 4b62 ldr r3, [pc, #392] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002dfa: 68db ldr r3, [r3, #12]
8002dfc: 4a61 ldr r2, [pc, #388] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002dfe: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002e02: 60d3 str r3, [r2, #12]
/* SAI2 clock source config set later after clock selection check */
break;
8002e04: e015 b.n 8002e32 <HAL_RCCEx_PeriphCLKConfig+0x10e>
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
8002e06: 687b ldr r3, [r7, #4]
8002e08: 3304 adds r3, #4
8002e0a: 2100 movs r1, #0
8002e0c: 4618 mov r0, r3
8002e0e: f000 fa73 bl 80032f8 <RCCEx_PLLSAI1_Config>
8002e12: 4603 mov r3, r0
8002e14: 74fb strb r3, [r7, #19]
/* SAI2 clock source config set later after clock selection check */
break;
8002e16: e00c b.n 8002e32 <HAL_RCCEx_PeriphCLKConfig+0x10e>
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
8002e18: 687b ldr r3, [r7, #4]
8002e1a: 3320 adds r3, #32
8002e1c: 2100 movs r1, #0
8002e1e: 4618 mov r0, r3
8002e20: f000 fb5e bl 80034e0 <RCCEx_PLLSAI2_Config>
8002e24: 4603 mov r3, r0
8002e26: 74fb strb r3, [r7, #19]
/* SAI2 clock source config set later after clock selection check */
break;
8002e28: e003 b.n 8002e32 <HAL_RCCEx_PeriphCLKConfig+0x10e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI2 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
8002e2a: 2301 movs r3, #1
8002e2c: 74fb strb r3, [r7, #19]
break;
8002e2e: e000 b.n 8002e32 <HAL_RCCEx_PeriphCLKConfig+0x10e>
break;
8002e30: bf00 nop
}
if(ret == HAL_OK)
8002e32: 7cfb ldrb r3, [r7, #19]
8002e34: 2b00 cmp r3, #0
8002e36: d10b bne.n 8002e50 <HAL_RCCEx_PeriphCLKConfig+0x12c>
{
/* Set the source of SAI2 clock*/
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
8002e38: 4b52 ldr r3, [pc, #328] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002e3a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002e3e: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
8002e42: 687b ldr r3, [r7, #4]
8002e44: 6e9b ldr r3, [r3, #104] @ 0x68
8002e46: 494f ldr r1, [pc, #316] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002e48: 4313 orrs r3, r2
8002e4a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
8002e4e: e001 b.n 8002e54 <HAL_RCCEx_PeriphCLKConfig+0x130>
}
else
{
/* set overall return value */
status = ret;
8002e50: 7cfb ldrb r3, [r7, #19]
8002e52: 74bb strb r3, [r7, #18]
}
}
#endif /* SAI2 */
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8002e54: 687b ldr r3, [r7, #4]
8002e56: 681b ldr r3, [r3, #0]
8002e58: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002e5c: 2b00 cmp r3, #0
8002e5e: f000 80a0 beq.w 8002fa2 <HAL_RCCEx_PeriphCLKConfig+0x27e>
{
FlagStatus pwrclkchanged = RESET;
8002e62: 2300 movs r3, #0
8002e64: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8002e66: 4b47 ldr r3, [pc, #284] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002e68: 6d9b ldr r3, [r3, #88] @ 0x58
8002e6a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002e6e: 2b00 cmp r3, #0
8002e70: d101 bne.n 8002e76 <HAL_RCCEx_PeriphCLKConfig+0x152>
8002e72: 2301 movs r3, #1
8002e74: e000 b.n 8002e78 <HAL_RCCEx_PeriphCLKConfig+0x154>
8002e76: 2300 movs r3, #0
8002e78: 2b00 cmp r3, #0
8002e7a: d00d beq.n 8002e98 <HAL_RCCEx_PeriphCLKConfig+0x174>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002e7c: 4b41 ldr r3, [pc, #260] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002e7e: 6d9b ldr r3, [r3, #88] @ 0x58
8002e80: 4a40 ldr r2, [pc, #256] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002e82: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002e86: 6593 str r3, [r2, #88] @ 0x58
8002e88: 4b3e ldr r3, [pc, #248] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002e8a: 6d9b ldr r3, [r3, #88] @ 0x58
8002e8c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002e90: 60bb str r3, [r7, #8]
8002e92: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002e94: 2301 movs r3, #1
8002e96: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8002e98: 4b3b ldr r3, [pc, #236] @ (8002f88 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8002e9a: 681b ldr r3, [r3, #0]
8002e9c: 4a3a ldr r2, [pc, #232] @ (8002f88 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8002e9e: f443 7380 orr.w r3, r3, #256 @ 0x100
8002ea2: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002ea4: f7fd fff6 bl 8000e94 <HAL_GetTick>
8002ea8: 60f8 str r0, [r7, #12]
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8002eaa: e009 b.n 8002ec0 <HAL_RCCEx_PeriphCLKConfig+0x19c>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002eac: f7fd fff2 bl 8000e94 <HAL_GetTick>
8002eb0: 4602 mov r2, r0
8002eb2: 68fb ldr r3, [r7, #12]
8002eb4: 1ad3 subs r3, r2, r3
8002eb6: 2b02 cmp r3, #2
8002eb8: d902 bls.n 8002ec0 <HAL_RCCEx_PeriphCLKConfig+0x19c>
{
ret = HAL_TIMEOUT;
8002eba: 2303 movs r3, #3
8002ebc: 74fb strb r3, [r7, #19]
break;
8002ebe: e005 b.n 8002ecc <HAL_RCCEx_PeriphCLKConfig+0x1a8>
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8002ec0: 4b31 ldr r3, [pc, #196] @ (8002f88 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8002ec2: 681b ldr r3, [r3, #0]
8002ec4: f403 7380 and.w r3, r3, #256 @ 0x100
8002ec8: 2b00 cmp r3, #0
8002eca: d0ef beq.n 8002eac <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
if(ret == HAL_OK)
8002ecc: 7cfb ldrb r3, [r7, #19]
8002ece: 2b00 cmp r3, #0
8002ed0: d15c bne.n 8002f8c <HAL_RCCEx_PeriphCLKConfig+0x268>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8002ed2: 4b2c ldr r3, [pc, #176] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002ed4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002ed8: f403 7340 and.w r3, r3, #768 @ 0x300
8002edc: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8002ede: 697b ldr r3, [r7, #20]
8002ee0: 2b00 cmp r3, #0
8002ee2: d01f beq.n 8002f24 <HAL_RCCEx_PeriphCLKConfig+0x200>
8002ee4: 687b ldr r3, [r7, #4]
8002ee6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002eea: 697a ldr r2, [r7, #20]
8002eec: 429a cmp r2, r3
8002eee: d019 beq.n 8002f24 <HAL_RCCEx_PeriphCLKConfig+0x200>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8002ef0: 4b24 ldr r3, [pc, #144] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002ef2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002ef6: f423 7340 bic.w r3, r3, #768 @ 0x300
8002efa: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8002efc: 4b21 ldr r3, [pc, #132] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002efe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002f02: 4a20 ldr r2, [pc, #128] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002f04: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002f08: f8c2 3090 str.w r3, [r2, #144] @ 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
8002f0c: 4b1d ldr r3, [pc, #116] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002f0e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002f12: 4a1c ldr r2, [pc, #112] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002f14: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002f18: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8002f1c: 4a19 ldr r2, [pc, #100] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002f1e: 697b ldr r3, [r7, #20]
8002f20: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8002f24: 697b ldr r3, [r7, #20]
8002f26: f003 0301 and.w r3, r3, #1
8002f2a: 2b00 cmp r3, #0
8002f2c: d016 beq.n 8002f5c <HAL_RCCEx_PeriphCLKConfig+0x238>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002f2e: f7fd ffb1 bl 8000e94 <HAL_GetTick>
8002f32: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8002f34: e00b b.n 8002f4e <HAL_RCCEx_PeriphCLKConfig+0x22a>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002f36: f7fd ffad bl 8000e94 <HAL_GetTick>
8002f3a: 4602 mov r2, r0
8002f3c: 68fb ldr r3, [r7, #12]
8002f3e: 1ad3 subs r3, r2, r3
8002f40: f241 3288 movw r2, #5000 @ 0x1388
8002f44: 4293 cmp r3, r2
8002f46: d902 bls.n 8002f4e <HAL_RCCEx_PeriphCLKConfig+0x22a>
{
ret = HAL_TIMEOUT;
8002f48: 2303 movs r3, #3
8002f4a: 74fb strb r3, [r7, #19]
break;
8002f4c: e006 b.n 8002f5c <HAL_RCCEx_PeriphCLKConfig+0x238>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8002f4e: 4b0d ldr r3, [pc, #52] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002f50: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002f54: f003 0302 and.w r3, r3, #2
8002f58: 2b00 cmp r3, #0
8002f5a: d0ec beq.n 8002f36 <HAL_RCCEx_PeriphCLKConfig+0x212>
}
}
}
if(ret == HAL_OK)
8002f5c: 7cfb ldrb r3, [r7, #19]
8002f5e: 2b00 cmp r3, #0
8002f60: d10c bne.n 8002f7c <HAL_RCCEx_PeriphCLKConfig+0x258>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8002f62: 4b08 ldr r3, [pc, #32] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002f64: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002f68: f423 7240 bic.w r2, r3, #768 @ 0x300
8002f6c: 687b ldr r3, [r7, #4]
8002f6e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002f72: 4904 ldr r1, [pc, #16] @ (8002f84 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8002f74: 4313 orrs r3, r2
8002f76: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8002f7a: e009 b.n 8002f90 <HAL_RCCEx_PeriphCLKConfig+0x26c>
}
else
{
/* set overall return value */
status = ret;
8002f7c: 7cfb ldrb r3, [r7, #19]
8002f7e: 74bb strb r3, [r7, #18]
8002f80: e006 b.n 8002f90 <HAL_RCCEx_PeriphCLKConfig+0x26c>
8002f82: bf00 nop
8002f84: 40021000 .word 0x40021000
8002f88: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8002f8c: 7cfb ldrb r3, [r7, #19]
8002f8e: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8002f90: 7c7b ldrb r3, [r7, #17]
8002f92: 2b01 cmp r3, #1
8002f94: d105 bne.n 8002fa2 <HAL_RCCEx_PeriphCLKConfig+0x27e>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002f96: 4b9e ldr r3, [pc, #632] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8002f98: 6d9b ldr r3, [r3, #88] @ 0x58
8002f9a: 4a9d ldr r2, [pc, #628] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8002f9c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002fa0: 6593 str r3, [r2, #88] @ 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8002fa2: 687b ldr r3, [r7, #4]
8002fa4: 681b ldr r3, [r3, #0]
8002fa6: f003 0301 and.w r3, r3, #1
8002faa: 2b00 cmp r3, #0
8002fac: d00a beq.n 8002fc4 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8002fae: 4b98 ldr r3, [pc, #608] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8002fb0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002fb4: f023 0203 bic.w r2, r3, #3
8002fb8: 687b ldr r3, [r7, #4]
8002fba: 6b9b ldr r3, [r3, #56] @ 0x38
8002fbc: 4994 ldr r1, [pc, #592] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8002fbe: 4313 orrs r3, r2
8002fc0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8002fc4: 687b ldr r3, [r7, #4]
8002fc6: 681b ldr r3, [r3, #0]
8002fc8: f003 0302 and.w r3, r3, #2
8002fcc: 2b00 cmp r3, #0
8002fce: d00a beq.n 8002fe6 <HAL_RCCEx_PeriphCLKConfig+0x2c2>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8002fd0: 4b8f ldr r3, [pc, #572] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8002fd2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002fd6: f023 020c bic.w r2, r3, #12
8002fda: 687b ldr r3, [r7, #4]
8002fdc: 6bdb ldr r3, [r3, #60] @ 0x3c
8002fde: 498c ldr r1, [pc, #560] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8002fe0: 4313 orrs r3, r2
8002fe2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8002fe6: 687b ldr r3, [r7, #4]
8002fe8: 681b ldr r3, [r3, #0]
8002fea: f003 0304 and.w r3, r3, #4
8002fee: 2b00 cmp r3, #0
8002ff0: d00a beq.n 8003008 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8002ff2: 4b87 ldr r3, [pc, #540] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8002ff4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002ff8: f023 0230 bic.w r2, r3, #48 @ 0x30
8002ffc: 687b ldr r3, [r7, #4]
8002ffe: 6c1b ldr r3, [r3, #64] @ 0x40
8003000: 4983 ldr r1, [pc, #524] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003002: 4313 orrs r3, r2
8003004: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* USART3 */
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8003008: 687b ldr r3, [r7, #4]
800300a: 681b ldr r3, [r3, #0]
800300c: f003 0308 and.w r3, r3, #8
8003010: 2b00 cmp r3, #0
8003012: d00a beq.n 800302a <HAL_RCCEx_PeriphCLKConfig+0x306>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8003014: 4b7e ldr r3, [pc, #504] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003016: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800301a: f023 02c0 bic.w r2, r3, #192 @ 0xc0
800301e: 687b ldr r3, [r7, #4]
8003020: 6c5b ldr r3, [r3, #68] @ 0x44
8003022: 497b ldr r1, [pc, #492] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003024: 4313 orrs r3, r2
8003026: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* UART4 */
#if defined(UART5)
/*-------------------------- UART5 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
800302a: 687b ldr r3, [r7, #4]
800302c: 681b ldr r3, [r3, #0]
800302e: f003 0310 and.w r3, r3, #16
8003032: 2b00 cmp r3, #0
8003034: d00a beq.n 800304c <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
8003036: 4b76 ldr r3, [pc, #472] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003038: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800303c: f423 7240 bic.w r2, r3, #768 @ 0x300
8003040: 687b ldr r3, [r7, #4]
8003042: 6c9b ldr r3, [r3, #72] @ 0x48
8003044: 4972 ldr r1, [pc, #456] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003046: 4313 orrs r3, r2
8003048: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
800304c: 687b ldr r3, [r7, #4]
800304e: 681b ldr r3, [r3, #0]
8003050: f003 0320 and.w r3, r3, #32
8003054: 2b00 cmp r3, #0
8003056: d00a beq.n 800306e <HAL_RCCEx_PeriphCLKConfig+0x34a>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUART1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8003058: 4b6d ldr r3, [pc, #436] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800305a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800305e: f423 6240 bic.w r2, r3, #3072 @ 0xc00
8003062: 687b ldr r3, [r7, #4]
8003064: 6cdb ldr r3, [r3, #76] @ 0x4c
8003066: 496a ldr r1, [pc, #424] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003068: 4313 orrs r3, r2
800306a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
800306e: 687b ldr r3, [r7, #4]
8003070: 681b ldr r3, [r3, #0]
8003072: f403 7300 and.w r3, r3, #512 @ 0x200
8003076: 2b00 cmp r3, #0
8003078: d00a beq.n 8003090 <HAL_RCCEx_PeriphCLKConfig+0x36c>
{
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
800307a: 4b65 ldr r3, [pc, #404] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800307c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003080: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
8003084: 687b ldr r3, [r7, #4]
8003086: 6ddb ldr r3, [r3, #92] @ 0x5c
8003088: 4961 ldr r1, [pc, #388] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800308a: 4313 orrs r3, r2
800308c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
8003090: 687b ldr r3, [r7, #4]
8003092: 681b ldr r3, [r3, #0]
8003094: f403 6380 and.w r3, r3, #1024 @ 0x400
8003098: 2b00 cmp r3, #0
800309a: d00a beq.n 80030b2 <HAL_RCCEx_PeriphCLKConfig+0x38e>
{
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
800309c: 4b5c ldr r3, [pc, #368] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800309e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80030a2: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
80030a6: 687b ldr r3, [r7, #4]
80030a8: 6e1b ldr r3, [r3, #96] @ 0x60
80030aa: 4959 ldr r1, [pc, #356] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80030ac: 4313 orrs r3, r2
80030ae: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80030b2: 687b ldr r3, [r7, #4]
80030b4: 681b ldr r3, [r3, #0]
80030b6: f003 0340 and.w r3, r3, #64 @ 0x40
80030ba: 2b00 cmp r3, #0
80030bc: d00a beq.n 80030d4 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80030be: 4b54 ldr r3, [pc, #336] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80030c0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80030c4: f423 5240 bic.w r2, r3, #12288 @ 0x3000
80030c8: 687b ldr r3, [r7, #4]
80030ca: 6d1b ldr r3, [r3, #80] @ 0x50
80030cc: 4950 ldr r1, [pc, #320] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80030ce: 4313 orrs r3, r2
80030d0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(I2C2)
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
80030d4: 687b ldr r3, [r7, #4]
80030d6: 681b ldr r3, [r3, #0]
80030d8: f003 0380 and.w r3, r3, #128 @ 0x80
80030dc: 2b00 cmp r3, #0
80030de: d00a beq.n 80030f6 <HAL_RCCEx_PeriphCLKConfig+0x3d2>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
80030e0: 4b4b ldr r3, [pc, #300] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80030e2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80030e6: f423 4240 bic.w r2, r3, #49152 @ 0xc000
80030ea: 687b ldr r3, [r7, #4]
80030ec: 6d5b ldr r3, [r3, #84] @ 0x54
80030ee: 4948 ldr r1, [pc, #288] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80030f0: 4313 orrs r3, r2
80030f2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* I2C2 */
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
80030f6: 687b ldr r3, [r7, #4]
80030f8: 681b ldr r3, [r3, #0]
80030fa: f403 7380 and.w r3, r3, #256 @ 0x100
80030fe: 2b00 cmp r3, #0
8003100: d00a beq.n 8003118 <HAL_RCCEx_PeriphCLKConfig+0x3f4>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8003102: 4b43 ldr r3, [pc, #268] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003104: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003108: f423 3240 bic.w r2, r3, #196608 @ 0x30000
800310c: 687b ldr r3, [r7, #4]
800310e: 6d9b ldr r3, [r3, #88] @ 0x58
8003110: 493f ldr r1, [pc, #252] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003112: 4313 orrs r3, r2
8003114: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* I2C4 */
#if defined(USB_OTG_FS) || defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
8003118: 687b ldr r3, [r7, #4]
800311a: 681b ldr r3, [r3, #0]
800311c: f403 5300 and.w r3, r3, #8192 @ 0x2000
8003120: 2b00 cmp r3, #0
8003122: d028 beq.n 8003176 <HAL_RCCEx_PeriphCLKConfig+0x452>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8003124: 4b3a ldr r3, [pc, #232] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003126: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800312a: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
800312e: 687b ldr r3, [r7, #4]
8003130: 6edb ldr r3, [r3, #108] @ 0x6c
8003132: 4937 ldr r1, [pc, #220] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003134: 4313 orrs r3, r2
8003136: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
800313a: 687b ldr r3, [r7, #4]
800313c: 6edb ldr r3, [r3, #108] @ 0x6c
800313e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8003142: d106 bne.n 8003152 <HAL_RCCEx_PeriphCLKConfig+0x42e>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8003144: 4b32 ldr r3, [pc, #200] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003146: 68db ldr r3, [r3, #12]
8003148: 4a31 ldr r2, [pc, #196] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
800314a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800314e: 60d3 str r3, [r2, #12]
8003150: e011 b.n 8003176 <HAL_RCCEx_PeriphCLKConfig+0x452>
}
else
{
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
8003152: 687b ldr r3, [r7, #4]
8003154: 6edb ldr r3, [r3, #108] @ 0x6c
8003156: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
800315a: d10c bne.n 8003176 <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
800315c: 687b ldr r3, [r7, #4]
800315e: 3304 adds r3, #4
8003160: 2101 movs r1, #1
8003162: 4618 mov r0, r3
8003164: f000 f8c8 bl 80032f8 <RCCEx_PLLSAI1_Config>
8003168: 4603 mov r3, r0
800316a: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
800316c: 7cfb ldrb r3, [r7, #19]
800316e: 2b00 cmp r3, #0
8003170: d001 beq.n 8003176 <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* set overall return value */
status = ret;
8003172: 7cfb ldrb r3, [r7, #19]
8003174: 74bb strb r3, [r7, #18]
#endif /* USB_OTG_FS || USB */
#if defined(SDMMC1)
/*-------------------------- SDMMC1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
8003176: 687b ldr r3, [r7, #4]
8003178: 681b ldr r3, [r3, #0]
800317a: f403 2300 and.w r3, r3, #524288 @ 0x80000
800317e: 2b00 cmp r3, #0
8003180: d028 beq.n 80031d4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
8003182: 4b23 ldr r3, [pc, #140] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003184: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003188: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
800318c: 687b ldr r3, [r7, #4]
800318e: 6f1b ldr r3, [r3, #112] @ 0x70
8003190: 491f ldr r1, [pc, #124] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003192: 4313 orrs r3, r2
8003194: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
8003198: 687b ldr r3, [r7, #4]
800319a: 6f1b ldr r3, [r3, #112] @ 0x70
800319c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80031a0: d106 bne.n 80031b0 <HAL_RCCEx_PeriphCLKConfig+0x48c>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80031a2: 4b1b ldr r3, [pc, #108] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80031a4: 68db ldr r3, [r3, #12]
80031a6: 4a1a ldr r2, [pc, #104] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80031a8: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80031ac: 60d3 str r3, [r2, #12]
80031ae: e011 b.n 80031d4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* Enable PLLSAI3CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
}
#endif
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
80031b0: 687b ldr r3, [r7, #4]
80031b2: 6f1b ldr r3, [r3, #112] @ 0x70
80031b4: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
80031b8: d10c bne.n 80031d4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
80031ba: 687b ldr r3, [r7, #4]
80031bc: 3304 adds r3, #4
80031be: 2101 movs r1, #1
80031c0: 4618 mov r0, r3
80031c2: f000 f899 bl 80032f8 <RCCEx_PLLSAI1_Config>
80031c6: 4603 mov r3, r0
80031c8: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
80031ca: 7cfb ldrb r3, [r7, #19]
80031cc: 2b00 cmp r3, #0
80031ce: d001 beq.n 80031d4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* set overall return value */
status = ret;
80031d0: 7cfb ldrb r3, [r7, #19]
80031d2: 74bb strb r3, [r7, #18]
}
#endif /* SDMMC1 */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
80031d4: 687b ldr r3, [r7, #4]
80031d6: 681b ldr r3, [r3, #0]
80031d8: f403 2380 and.w r3, r3, #262144 @ 0x40000
80031dc: 2b00 cmp r3, #0
80031de: d02b beq.n 8003238 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
80031e0: 4b0b ldr r3, [pc, #44] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80031e2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80031e6: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
80031ea: 687b ldr r3, [r7, #4]
80031ec: 6f5b ldr r3, [r3, #116] @ 0x74
80031ee: 4908 ldr r1, [pc, #32] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
80031f0: 4313 orrs r3, r2
80031f2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
80031f6: 687b ldr r3, [r7, #4]
80031f8: 6f5b ldr r3, [r3, #116] @ 0x74
80031fa: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80031fe: d109 bne.n 8003214 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8003200: 4b03 ldr r3, [pc, #12] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003202: 68db ldr r3, [r3, #12]
8003204: 4a02 ldr r2, [pc, #8] @ (8003210 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003206: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800320a: 60d3 str r3, [r2, #12]
800320c: e014 b.n 8003238 <HAL_RCCEx_PeriphCLKConfig+0x514>
800320e: bf00 nop
8003210: 40021000 .word 0x40021000
}
#if defined(RCC_PLLSAI1_SUPPORT)
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
8003214: 687b ldr r3, [r7, #4]
8003216: 6f5b ldr r3, [r3, #116] @ 0x74
8003218: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
800321c: d10c bne.n 8003238 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
800321e: 687b ldr r3, [r7, #4]
8003220: 3304 adds r3, #4
8003222: 2101 movs r1, #1
8003224: 4618 mov r0, r3
8003226: f000 f867 bl 80032f8 <RCCEx_PLLSAI1_Config>
800322a: 4603 mov r3, r0
800322c: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
800322e: 7cfb ldrb r3, [r7, #19]
8003230: 2b00 cmp r3, #0
8003232: d001 beq.n 8003238 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* set overall return value */
status = ret;
8003234: 7cfb ldrb r3, [r7, #19]
8003236: 74bb strb r3, [r7, #18]
}
}
/*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003238: 687b ldr r3, [r7, #4]
800323a: 681b ldr r3, [r3, #0]
800323c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8003240: 2b00 cmp r3, #0
8003242: d02f beq.n 80032a4 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8003244: 4b2b ldr r3, [pc, #172] @ (80032f4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003246: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800324a: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
800324e: 687b ldr r3, [r7, #4]
8003250: 6f9b ldr r3, [r3, #120] @ 0x78
8003252: 4928 ldr r1, [pc, #160] @ (80032f4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003254: 4313 orrs r3, r2
8003256: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
800325a: 687b ldr r3, [r7, #4]
800325c: 6f9b ldr r3, [r3, #120] @ 0x78
800325e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8003262: d10d bne.n 8003280 <HAL_RCCEx_PeriphCLKConfig+0x55c>
{
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
8003264: 687b ldr r3, [r7, #4]
8003266: 3304 adds r3, #4
8003268: 2102 movs r1, #2
800326a: 4618 mov r0, r3
800326c: f000 f844 bl 80032f8 <RCCEx_PLLSAI1_Config>
8003270: 4603 mov r3, r0
8003272: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003274: 7cfb ldrb r3, [r7, #19]
8003276: 2b00 cmp r3, #0
8003278: d014 beq.n 80032a4 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* set overall return value */
status = ret;
800327a: 7cfb ldrb r3, [r7, #19]
800327c: 74bb strb r3, [r7, #18]
800327e: e011 b.n 80032a4 <HAL_RCCEx_PeriphCLKConfig+0x580>
}
#endif /* RCC_PLLSAI1_SUPPORT */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
8003280: 687b ldr r3, [r7, #4]
8003282: 6f9b ldr r3, [r3, #120] @ 0x78
8003284: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8003288: d10c bne.n 80032a4 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
800328a: 687b ldr r3, [r7, #4]
800328c: 3320 adds r3, #32
800328e: 2102 movs r1, #2
8003290: 4618 mov r0, r3
8003292: f000 f925 bl 80034e0 <RCCEx_PLLSAI2_Config>
8003296: 4603 mov r3, r0
8003298: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
800329a: 7cfb ldrb r3, [r7, #19]
800329c: 2b00 cmp r3, #0
800329e: d001 beq.n 80032a4 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* set overall return value */
status = ret;
80032a0: 7cfb ldrb r3, [r7, #19]
80032a2: 74bb strb r3, [r7, #18]
#endif /* !STM32L412xx && !STM32L422xx */
#if defined(SWPMI1)
/*-------------------------- SWPMI1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
80032a4: 687b ldr r3, [r7, #4]
80032a6: 681b ldr r3, [r3, #0]
80032a8: f403 4300 and.w r3, r3, #32768 @ 0x8000
80032ac: 2b00 cmp r3, #0
80032ae: d00a beq.n 80032c6 <HAL_RCCEx_PeriphCLKConfig+0x5a2>
{
/* Check the parameters */
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
/* Configure the SWPMI1 clock source */
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
80032b0: 4b10 ldr r3, [pc, #64] @ (80032f4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
80032b2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80032b6: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000
80032ba: 687b ldr r3, [r7, #4]
80032bc: 6fdb ldr r3, [r3, #124] @ 0x7c
80032be: 490d ldr r1, [pc, #52] @ (80032f4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
80032c0: 4313 orrs r3, r2
80032c2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* SWPMI1 */
#if defined(DFSDM1_Filter0)
/*-------------------------- DFSDM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
80032c6: 687b ldr r3, [r7, #4]
80032c8: 681b ldr r3, [r3, #0]
80032ca: f403 3380 and.w r3, r3, #65536 @ 0x10000
80032ce: 2b00 cmp r3, #0
80032d0: d00b beq.n 80032ea <HAL_RCCEx_PeriphCLKConfig+0x5c6>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
/* Configure the DFSDM1 interface clock source */
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
80032d2: 4b08 ldr r3, [pc, #32] @ (80032f4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
80032d4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80032d8: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
80032dc: 687b ldr r3, [r7, #4]
80032de: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80032e2: 4904 ldr r1, [pc, #16] @ (80032f4 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
80032e4: 4313 orrs r3, r2
80032e6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
}
#endif /* OCTOSPI1 || OCTOSPI2 */
return status;
80032ea: 7cbb ldrb r3, [r7, #18]
}
80032ec: 4618 mov r0, r3
80032ee: 3718 adds r7, #24
80032f0: 46bd mov sp, r7
80032f2: bd80 pop {r7, pc}
80032f4: 40021000 .word 0x40021000
080032f8 <RCCEx_PLLSAI1_Config>:
* @note PLLSAI1 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
80032f8: b580 push {r7, lr}
80032fa: b084 sub sp, #16
80032fc: af00 add r7, sp, #0
80032fe: 6078 str r0, [r7, #4]
8003300: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
8003302: 2300 movs r3, #0
8003304: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
/* Check that PLLSAI1 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
8003306: 4b75 ldr r3, [pc, #468] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
8003308: 68db ldr r3, [r3, #12]
800330a: f003 0303 and.w r3, r3, #3
800330e: 2b00 cmp r3, #0
8003310: d018 beq.n 8003344 <RCCEx_PLLSAI1_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
8003312: 4b72 ldr r3, [pc, #456] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
8003314: 68db ldr r3, [r3, #12]
8003316: f003 0203 and.w r2, r3, #3
800331a: 687b ldr r3, [r7, #4]
800331c: 681b ldr r3, [r3, #0]
800331e: 429a cmp r2, r3
8003320: d10d bne.n 800333e <RCCEx_PLLSAI1_Config+0x46>
||
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
8003322: 687b ldr r3, [r7, #4]
8003324: 681b ldr r3, [r3, #0]
||
8003326: 2b00 cmp r3, #0
8003328: d009 beq.n 800333e <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
800332a: 4b6c ldr r3, [pc, #432] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
800332c: 68db ldr r3, [r3, #12]
800332e: 091b lsrs r3, r3, #4
8003330: f003 0307 and.w r3, r3, #7
8003334: 1c5a adds r2, r3, #1
8003336: 687b ldr r3, [r7, #4]
8003338: 685b ldr r3, [r3, #4]
||
800333a: 429a cmp r2, r3
800333c: d047 beq.n 80033ce <RCCEx_PLLSAI1_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
800333e: 2301 movs r3, #1
8003340: 73fb strb r3, [r7, #15]
8003342: e044 b.n 80033ce <RCCEx_PLLSAI1_Config+0xd6>
}
}
else
{
/* Check PLLSAI1 clock source availability */
switch(PllSai1->PLLSAI1Source)
8003344: 687b ldr r3, [r7, #4]
8003346: 681b ldr r3, [r3, #0]
8003348: 2b03 cmp r3, #3
800334a: d018 beq.n 800337e <RCCEx_PLLSAI1_Config+0x86>
800334c: 2b03 cmp r3, #3
800334e: d825 bhi.n 800339c <RCCEx_PLLSAI1_Config+0xa4>
8003350: 2b01 cmp r3, #1
8003352: d002 beq.n 800335a <RCCEx_PLLSAI1_Config+0x62>
8003354: 2b02 cmp r3, #2
8003356: d009 beq.n 800336c <RCCEx_PLLSAI1_Config+0x74>
8003358: e020 b.n 800339c <RCCEx_PLLSAI1_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
800335a: 4b60 ldr r3, [pc, #384] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
800335c: 681b ldr r3, [r3, #0]
800335e: f003 0302 and.w r3, r3, #2
8003362: 2b00 cmp r3, #0
8003364: d11d bne.n 80033a2 <RCCEx_PLLSAI1_Config+0xaa>
{
status = HAL_ERROR;
8003366: 2301 movs r3, #1
8003368: 73fb strb r3, [r7, #15]
}
break;
800336a: e01a b.n 80033a2 <RCCEx_PLLSAI1_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
800336c: 4b5b ldr r3, [pc, #364] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
800336e: 681b ldr r3, [r3, #0]
8003370: f403 6380 and.w r3, r3, #1024 @ 0x400
8003374: 2b00 cmp r3, #0
8003376: d116 bne.n 80033a6 <RCCEx_PLLSAI1_Config+0xae>
{
status = HAL_ERROR;
8003378: 2301 movs r3, #1
800337a: 73fb strb r3, [r7, #15]
}
break;
800337c: e013 b.n 80033a6 <RCCEx_PLLSAI1_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
800337e: 4b57 ldr r3, [pc, #348] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
8003380: 681b ldr r3, [r3, #0]
8003382: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003386: 2b00 cmp r3, #0
8003388: d10f bne.n 80033aa <RCCEx_PLLSAI1_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
800338a: 4b54 ldr r3, [pc, #336] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
800338c: 681b ldr r3, [r3, #0]
800338e: f403 2380 and.w r3, r3, #262144 @ 0x40000
8003392: 2b00 cmp r3, #0
8003394: d109 bne.n 80033aa <RCCEx_PLLSAI1_Config+0xb2>
{
status = HAL_ERROR;
8003396: 2301 movs r3, #1
8003398: 73fb strb r3, [r7, #15]
}
}
break;
800339a: e006 b.n 80033aa <RCCEx_PLLSAI1_Config+0xb2>
default:
status = HAL_ERROR;
800339c: 2301 movs r3, #1
800339e: 73fb strb r3, [r7, #15]
break;
80033a0: e004 b.n 80033ac <RCCEx_PLLSAI1_Config+0xb4>
break;
80033a2: bf00 nop
80033a4: e002 b.n 80033ac <RCCEx_PLLSAI1_Config+0xb4>
break;
80033a6: bf00 nop
80033a8: e000 b.n 80033ac <RCCEx_PLLSAI1_Config+0xb4>
break;
80033aa: bf00 nop
}
if(status == HAL_OK)
80033ac: 7bfb ldrb r3, [r7, #15]
80033ae: 2b00 cmp r3, #0
80033b0: d10d bne.n 80033ce <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
/* Set PLLSAI1 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
/* Set PLLSAI1 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
80033b2: 4b4a ldr r3, [pc, #296] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
80033b4: 68db ldr r3, [r3, #12]
80033b6: f023 0273 bic.w r2, r3, #115 @ 0x73
80033ba: 687b ldr r3, [r7, #4]
80033bc: 6819 ldr r1, [r3, #0]
80033be: 687b ldr r3, [r7, #4]
80033c0: 685b ldr r3, [r3, #4]
80033c2: 3b01 subs r3, #1
80033c4: 011b lsls r3, r3, #4
80033c6: 430b orrs r3, r1
80033c8: 4944 ldr r1, [pc, #272] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
80033ca: 4313 orrs r3, r2
80033cc: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
80033ce: 7bfb ldrb r3, [r7, #15]
80033d0: 2b00 cmp r3, #0
80033d2: d17d bne.n 80034d0 <RCCEx_PLLSAI1_Config+0x1d8>
{
/* Disable the PLLSAI1 */
__HAL_RCC_PLLSAI1_DISABLE();
80033d4: 4b41 ldr r3, [pc, #260] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
80033d6: 681b ldr r3, [r3, #0]
80033d8: 4a40 ldr r2, [pc, #256] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
80033da: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
80033de: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80033e0: f7fd fd58 bl 8000e94 <HAL_GetTick>
80033e4: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
80033e6: e009 b.n 80033fc <RCCEx_PLLSAI1_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
80033e8: f7fd fd54 bl 8000e94 <HAL_GetTick>
80033ec: 4602 mov r2, r0
80033ee: 68bb ldr r3, [r7, #8]
80033f0: 1ad3 subs r3, r2, r3
80033f2: 2b02 cmp r3, #2
80033f4: d902 bls.n 80033fc <RCCEx_PLLSAI1_Config+0x104>
{
status = HAL_TIMEOUT;
80033f6: 2303 movs r3, #3
80033f8: 73fb strb r3, [r7, #15]
break;
80033fa: e005 b.n 8003408 <RCCEx_PLLSAI1_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
80033fc: 4b37 ldr r3, [pc, #220] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
80033fe: 681b ldr r3, [r3, #0]
8003400: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8003404: 2b00 cmp r3, #0
8003406: d1ef bne.n 80033e8 <RCCEx_PLLSAI1_Config+0xf0>
}
}
if(status == HAL_OK)
8003408: 7bfb ldrb r3, [r7, #15]
800340a: 2b00 cmp r3, #0
800340c: d160 bne.n 80034d0 <RCCEx_PLLSAI1_Config+0x1d8>
{
if(Divider == DIVIDER_P_UPDATE)
800340e: 683b ldr r3, [r7, #0]
8003410: 2b00 cmp r3, #0
8003412: d111 bne.n 8003438 <RCCEx_PLLSAI1_Config+0x140>
MODIFY_REG(RCC->PLLSAI1CFGR,
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI1CFGR,
8003414: 4b31 ldr r3, [pc, #196] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
8003416: 691b ldr r3, [r3, #16]
8003418: f423 331f bic.w r3, r3, #162816 @ 0x27c00
800341c: f423 7340 bic.w r3, r3, #768 @ 0x300
8003420: 687a ldr r2, [r7, #4]
8003422: 6892 ldr r2, [r2, #8]
8003424: 0211 lsls r1, r2, #8
8003426: 687a ldr r2, [r7, #4]
8003428: 68d2 ldr r2, [r2, #12]
800342a: 0912 lsrs r2, r2, #4
800342c: 0452 lsls r2, r2, #17
800342e: 430a orrs r2, r1
8003430: 492a ldr r1, [pc, #168] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
8003432: 4313 orrs r3, r2
8003434: 610b str r3, [r1, #16]
8003436: e027 b.n 8003488 <RCCEx_PLLSAI1_Config+0x190>
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
else if(Divider == DIVIDER_Q_UPDATE)
8003438: 683b ldr r3, [r7, #0]
800343a: 2b01 cmp r3, #1
800343c: d112 bne.n 8003464 <RCCEx_PLLSAI1_Config+0x16c>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
800343e: 4b27 ldr r3, [pc, #156] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
8003440: 691b ldr r3, [r3, #16]
8003442: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000
8003446: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
800344a: 687a ldr r2, [r7, #4]
800344c: 6892 ldr r2, [r2, #8]
800344e: 0211 lsls r1, r2, #8
8003450: 687a ldr r2, [r7, #4]
8003452: 6912 ldr r2, [r2, #16]
8003454: 0852 lsrs r2, r2, #1
8003456: 3a01 subs r2, #1
8003458: 0552 lsls r2, r2, #21
800345a: 430a orrs r2, r1
800345c: 491f ldr r1, [pc, #124] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
800345e: 4313 orrs r3, r2
8003460: 610b str r3, [r1, #16]
8003462: e011 b.n 8003488 <RCCEx_PLLSAI1_Config+0x190>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
8003464: 4b1d ldr r3, [pc, #116] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
8003466: 691b ldr r3, [r3, #16]
8003468: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
800346c: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
8003470: 687a ldr r2, [r7, #4]
8003472: 6892 ldr r2, [r2, #8]
8003474: 0211 lsls r1, r2, #8
8003476: 687a ldr r2, [r7, #4]
8003478: 6952 ldr r2, [r2, #20]
800347a: 0852 lsrs r2, r2, #1
800347c: 3a01 subs r2, #1
800347e: 0652 lsls r2, r2, #25
8003480: 430a orrs r2, r1
8003482: 4916 ldr r1, [pc, #88] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
8003484: 4313 orrs r3, r2
8003486: 610b str r3, [r1, #16]
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
__HAL_RCC_PLLSAI1_ENABLE();
8003488: 4b14 ldr r3, [pc, #80] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
800348a: 681b ldr r3, [r3, #0]
800348c: 4a13 ldr r2, [pc, #76] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
800348e: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8003492: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003494: f7fd fcfe bl 8000e94 <HAL_GetTick>
8003498: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
800349a: e009 b.n 80034b0 <RCCEx_PLLSAI1_Config+0x1b8>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
800349c: f7fd fcfa bl 8000e94 <HAL_GetTick>
80034a0: 4602 mov r2, r0
80034a2: 68bb ldr r3, [r7, #8]
80034a4: 1ad3 subs r3, r2, r3
80034a6: 2b02 cmp r3, #2
80034a8: d902 bls.n 80034b0 <RCCEx_PLLSAI1_Config+0x1b8>
{
status = HAL_TIMEOUT;
80034aa: 2303 movs r3, #3
80034ac: 73fb strb r3, [r7, #15]
break;
80034ae: e005 b.n 80034bc <RCCEx_PLLSAI1_Config+0x1c4>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
80034b0: 4b0a ldr r3, [pc, #40] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
80034b2: 681b ldr r3, [r3, #0]
80034b4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
80034b8: 2b00 cmp r3, #0
80034ba: d0ef beq.n 800349c <RCCEx_PLLSAI1_Config+0x1a4>
}
}
if(status == HAL_OK)
80034bc: 7bfb ldrb r3, [r7, #15]
80034be: 2b00 cmp r3, #0
80034c0: d106 bne.n 80034d0 <RCCEx_PLLSAI1_Config+0x1d8>
{
/* Configure the PLLSAI1 Clock output(s) */
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
80034c2: 4b06 ldr r3, [pc, #24] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
80034c4: 691a ldr r2, [r3, #16]
80034c6: 687b ldr r3, [r7, #4]
80034c8: 699b ldr r3, [r3, #24]
80034ca: 4904 ldr r1, [pc, #16] @ (80034dc <RCCEx_PLLSAI1_Config+0x1e4>)
80034cc: 4313 orrs r3, r2
80034ce: 610b str r3, [r1, #16]
}
}
}
return status;
80034d0: 7bfb ldrb r3, [r7, #15]
}
80034d2: 4618 mov r0, r3
80034d4: 3710 adds r7, #16
80034d6: 46bd mov sp, r7
80034d8: bd80 pop {r7, pc}
80034da: bf00 nop
80034dc: 40021000 .word 0x40021000
080034e0 <RCCEx_PLLSAI2_Config>:
* @note PLLSAI2 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
{
80034e0: b580 push {r7, lr}
80034e2: b084 sub sp, #16
80034e4: af00 add r7, sp, #0
80034e6: 6078 str r0, [r7, #4]
80034e8: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
80034ea: 2300 movs r3, #0
80034ec: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
/* Check that PLLSAI2 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
80034ee: 4b6a ldr r3, [pc, #424] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
80034f0: 68db ldr r3, [r3, #12]
80034f2: f003 0303 and.w r3, r3, #3
80034f6: 2b00 cmp r3, #0
80034f8: d018 beq.n 800352c <RCCEx_PLLSAI2_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
80034fa: 4b67 ldr r3, [pc, #412] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
80034fc: 68db ldr r3, [r3, #12]
80034fe: f003 0203 and.w r2, r3, #3
8003502: 687b ldr r3, [r7, #4]
8003504: 681b ldr r3, [r3, #0]
8003506: 429a cmp r2, r3
8003508: d10d bne.n 8003526 <RCCEx_PLLSAI2_Config+0x46>
||
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
800350a: 687b ldr r3, [r7, #4]
800350c: 681b ldr r3, [r3, #0]
||
800350e: 2b00 cmp r3, #0
8003510: d009 beq.n 8003526 <RCCEx_PLLSAI2_Config+0x46>
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
8003512: 4b61 ldr r3, [pc, #388] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003514: 68db ldr r3, [r3, #12]
8003516: 091b lsrs r3, r3, #4
8003518: f003 0307 and.w r3, r3, #7
800351c: 1c5a adds r2, r3, #1
800351e: 687b ldr r3, [r7, #4]
8003520: 685b ldr r3, [r3, #4]
||
8003522: 429a cmp r2, r3
8003524: d047 beq.n 80035b6 <RCCEx_PLLSAI2_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
8003526: 2301 movs r3, #1
8003528: 73fb strb r3, [r7, #15]
800352a: e044 b.n 80035b6 <RCCEx_PLLSAI2_Config+0xd6>
}
}
else
{
/* Check PLLSAI2 clock source availability */
switch(PllSai2->PLLSAI2Source)
800352c: 687b ldr r3, [r7, #4]
800352e: 681b ldr r3, [r3, #0]
8003530: 2b03 cmp r3, #3
8003532: d018 beq.n 8003566 <RCCEx_PLLSAI2_Config+0x86>
8003534: 2b03 cmp r3, #3
8003536: d825 bhi.n 8003584 <RCCEx_PLLSAI2_Config+0xa4>
8003538: 2b01 cmp r3, #1
800353a: d002 beq.n 8003542 <RCCEx_PLLSAI2_Config+0x62>
800353c: 2b02 cmp r3, #2
800353e: d009 beq.n 8003554 <RCCEx_PLLSAI2_Config+0x74>
8003540: e020 b.n 8003584 <RCCEx_PLLSAI2_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
8003542: 4b55 ldr r3, [pc, #340] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003544: 681b ldr r3, [r3, #0]
8003546: f003 0302 and.w r3, r3, #2
800354a: 2b00 cmp r3, #0
800354c: d11d bne.n 800358a <RCCEx_PLLSAI2_Config+0xaa>
{
status = HAL_ERROR;
800354e: 2301 movs r3, #1
8003550: 73fb strb r3, [r7, #15]
}
break;
8003552: e01a b.n 800358a <RCCEx_PLLSAI2_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
8003554: 4b50 ldr r3, [pc, #320] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003556: 681b ldr r3, [r3, #0]
8003558: f403 6380 and.w r3, r3, #1024 @ 0x400
800355c: 2b00 cmp r3, #0
800355e: d116 bne.n 800358e <RCCEx_PLLSAI2_Config+0xae>
{
status = HAL_ERROR;
8003560: 2301 movs r3, #1
8003562: 73fb strb r3, [r7, #15]
}
break;
8003564: e013 b.n 800358e <RCCEx_PLLSAI2_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
8003566: 4b4c ldr r3, [pc, #304] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003568: 681b ldr r3, [r3, #0]
800356a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800356e: 2b00 cmp r3, #0
8003570: d10f bne.n 8003592 <RCCEx_PLLSAI2_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
8003572: 4b49 ldr r3, [pc, #292] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003574: 681b ldr r3, [r3, #0]
8003576: f403 2380 and.w r3, r3, #262144 @ 0x40000
800357a: 2b00 cmp r3, #0
800357c: d109 bne.n 8003592 <RCCEx_PLLSAI2_Config+0xb2>
{
status = HAL_ERROR;
800357e: 2301 movs r3, #1
8003580: 73fb strb r3, [r7, #15]
}
}
break;
8003582: e006 b.n 8003592 <RCCEx_PLLSAI2_Config+0xb2>
default:
status = HAL_ERROR;
8003584: 2301 movs r3, #1
8003586: 73fb strb r3, [r7, #15]
break;
8003588: e004 b.n 8003594 <RCCEx_PLLSAI2_Config+0xb4>
break;
800358a: bf00 nop
800358c: e002 b.n 8003594 <RCCEx_PLLSAI2_Config+0xb4>
break;
800358e: bf00 nop
8003590: e000 b.n 8003594 <RCCEx_PLLSAI2_Config+0xb4>
break;
8003592: bf00 nop
}
if(status == HAL_OK)
8003594: 7bfb ldrb r3, [r7, #15]
8003596: 2b00 cmp r3, #0
8003598: d10d bne.n 80035b6 <RCCEx_PLLSAI2_Config+0xd6>
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
/* Set PLLSAI2 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
#else
/* Set PLLSAI2 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
800359a: 4b3f ldr r3, [pc, #252] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
800359c: 68db ldr r3, [r3, #12]
800359e: f023 0273 bic.w r2, r3, #115 @ 0x73
80035a2: 687b ldr r3, [r7, #4]
80035a4: 6819 ldr r1, [r3, #0]
80035a6: 687b ldr r3, [r7, #4]
80035a8: 685b ldr r3, [r3, #4]
80035aa: 3b01 subs r3, #1
80035ac: 011b lsls r3, r3, #4
80035ae: 430b orrs r3, r1
80035b0: 4939 ldr r1, [pc, #228] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
80035b2: 4313 orrs r3, r2
80035b4: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
80035b6: 7bfb ldrb r3, [r7, #15]
80035b8: 2b00 cmp r3, #0
80035ba: d167 bne.n 800368c <RCCEx_PLLSAI2_Config+0x1ac>
{
/* Disable the PLLSAI2 */
__HAL_RCC_PLLSAI2_DISABLE();
80035bc: 4b36 ldr r3, [pc, #216] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
80035be: 681b ldr r3, [r3, #0]
80035c0: 4a35 ldr r2, [pc, #212] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
80035c2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80035c6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80035c8: f7fd fc64 bl 8000e94 <HAL_GetTick>
80035cc: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI2 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
80035ce: e009 b.n 80035e4 <RCCEx_PLLSAI2_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
80035d0: f7fd fc60 bl 8000e94 <HAL_GetTick>
80035d4: 4602 mov r2, r0
80035d6: 68bb ldr r3, [r7, #8]
80035d8: 1ad3 subs r3, r2, r3
80035da: 2b02 cmp r3, #2
80035dc: d902 bls.n 80035e4 <RCCEx_PLLSAI2_Config+0x104>
{
status = HAL_TIMEOUT;
80035de: 2303 movs r3, #3
80035e0: 73fb strb r3, [r7, #15]
break;
80035e2: e005 b.n 80035f0 <RCCEx_PLLSAI2_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
80035e4: 4b2c ldr r3, [pc, #176] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
80035e6: 681b ldr r3, [r3, #0]
80035e8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80035ec: 2b00 cmp r3, #0
80035ee: d1ef bne.n 80035d0 <RCCEx_PLLSAI2_Config+0xf0>
}
}
if(status == HAL_OK)
80035f0: 7bfb ldrb r3, [r7, #15]
80035f2: 2b00 cmp r3, #0
80035f4: d14a bne.n 800368c <RCCEx_PLLSAI2_Config+0x1ac>
{
if(Divider == DIVIDER_P_UPDATE)
80035f6: 683b ldr r3, [r7, #0]
80035f8: 2b00 cmp r3, #0
80035fa: d111 bne.n 8003620 <RCCEx_PLLSAI2_Config+0x140>
MODIFY_REG(RCC->PLLSAI2CFGR,
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI2CFGR,
80035fc: 4b26 ldr r3, [pc, #152] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
80035fe: 695b ldr r3, [r3, #20]
8003600: f423 331f bic.w r3, r3, #162816 @ 0x27c00
8003604: f423 7340 bic.w r3, r3, #768 @ 0x300
8003608: 687a ldr r2, [r7, #4]
800360a: 6892 ldr r2, [r2, #8]
800360c: 0211 lsls r1, r2, #8
800360e: 687a ldr r2, [r7, #4]
8003610: 68d2 ldr r2, [r2, #12]
8003612: 0912 lsrs r2, r2, #4
8003614: 0452 lsls r2, r2, #17
8003616: 430a orrs r2, r1
8003618: 491f ldr r1, [pc, #124] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
800361a: 4313 orrs r3, r2
800361c: 614b str r3, [r1, #20]
800361e: e011 b.n 8003644 <RCCEx_PLLSAI2_Config+0x164>
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
#else
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI2CFGR,
8003620: 4b1d ldr r3, [pc, #116] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003622: 695b ldr r3, [r3, #20]
8003624: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
8003628: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
800362c: 687a ldr r2, [r7, #4]
800362e: 6892 ldr r2, [r2, #8]
8003630: 0211 lsls r1, r2, #8
8003632: 687a ldr r2, [r7, #4]
8003634: 6912 ldr r2, [r2, #16]
8003636: 0852 lsrs r2, r2, #1
8003638: 3a01 subs r2, #1
800363a: 0652 lsls r2, r2, #25
800363c: 430a orrs r2, r1
800363e: 4916 ldr r1, [pc, #88] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003640: 4313 orrs r3, r2
8003642: 614b str r3, [r1, #20]
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
__HAL_RCC_PLLSAI2_ENABLE();
8003644: 4b14 ldr r3, [pc, #80] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003646: 681b ldr r3, [r3, #0]
8003648: 4a13 ldr r2, [pc, #76] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
800364a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800364e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003650: f7fd fc20 bl 8000e94 <HAL_GetTick>
8003654: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI2 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
8003656: e009 b.n 800366c <RCCEx_PLLSAI2_Config+0x18c>
{
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
8003658: f7fd fc1c bl 8000e94 <HAL_GetTick>
800365c: 4602 mov r2, r0
800365e: 68bb ldr r3, [r7, #8]
8003660: 1ad3 subs r3, r2, r3
8003662: 2b02 cmp r3, #2
8003664: d902 bls.n 800366c <RCCEx_PLLSAI2_Config+0x18c>
{
status = HAL_TIMEOUT;
8003666: 2303 movs r3, #3
8003668: 73fb strb r3, [r7, #15]
break;
800366a: e005 b.n 8003678 <RCCEx_PLLSAI2_Config+0x198>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
800366c: 4b0a ldr r3, [pc, #40] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
800366e: 681b ldr r3, [r3, #0]
8003670: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8003674: 2b00 cmp r3, #0
8003676: d0ef beq.n 8003658 <RCCEx_PLLSAI2_Config+0x178>
}
}
if(status == HAL_OK)
8003678: 7bfb ldrb r3, [r7, #15]
800367a: 2b00 cmp r3, #0
800367c: d106 bne.n 800368c <RCCEx_PLLSAI2_Config+0x1ac>
{
/* Configure the PLLSAI2 Clock output(s) */
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
800367e: 4b06 ldr r3, [pc, #24] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003680: 695a ldr r2, [r3, #20]
8003682: 687b ldr r3, [r7, #4]
8003684: 695b ldr r3, [r3, #20]
8003686: 4904 ldr r1, [pc, #16] @ (8003698 <RCCEx_PLLSAI2_Config+0x1b8>)
8003688: 4313 orrs r3, r2
800368a: 614b str r3, [r1, #20]
}
}
}
return status;
800368c: 7bfb ldrb r3, [r7, #15]
}
800368e: 4618 mov r0, r3
8003690: 3710 adds r7, #16
8003692: 46bd mov sp, r7
8003694: bd80 pop {r7, pc}
8003696: bf00 nop
8003698: 40021000 .word 0x40021000
0800369c <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
800369c: b580 push {r7, lr}
800369e: b082 sub sp, #8
80036a0: af00 add r7, sp, #0
80036a2: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80036a4: 687b ldr r3, [r7, #4]
80036a6: 2b00 cmp r3, #0
80036a8: d101 bne.n 80036ae <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
80036aa: 2301 movs r3, #1
80036ac: e049 b.n 8003742 <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80036ae: 687b ldr r3, [r7, #4]
80036b0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80036b4: b2db uxtb r3, r3
80036b6: 2b00 cmp r3, #0
80036b8: d106 bne.n 80036c8 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80036ba: 687b ldr r3, [r7, #4]
80036bc: 2200 movs r2, #0
80036be: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
80036c2: 6878 ldr r0, [r7, #4]
80036c4: f7fd fa26 bl 8000b14 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80036c8: 687b ldr r3, [r7, #4]
80036ca: 2202 movs r2, #2
80036cc: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80036d0: 687b ldr r3, [r7, #4]
80036d2: 681a ldr r2, [r3, #0]
80036d4: 687b ldr r3, [r7, #4]
80036d6: 3304 adds r3, #4
80036d8: 4619 mov r1, r3
80036da: 4610 mov r0, r2
80036dc: f000 fa50 bl 8003b80 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80036e0: 687b ldr r3, [r7, #4]
80036e2: 2201 movs r2, #1
80036e4: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80036e8: 687b ldr r3, [r7, #4]
80036ea: 2201 movs r2, #1
80036ec: f883 203e strb.w r2, [r3, #62] @ 0x3e
80036f0: 687b ldr r3, [r7, #4]
80036f2: 2201 movs r2, #1
80036f4: f883 203f strb.w r2, [r3, #63] @ 0x3f
80036f8: 687b ldr r3, [r7, #4]
80036fa: 2201 movs r2, #1
80036fc: f883 2040 strb.w r2, [r3, #64] @ 0x40
8003700: 687b ldr r3, [r7, #4]
8003702: 2201 movs r2, #1
8003704: f883 2041 strb.w r2, [r3, #65] @ 0x41
8003708: 687b ldr r3, [r7, #4]
800370a: 2201 movs r2, #1
800370c: f883 2042 strb.w r2, [r3, #66] @ 0x42
8003710: 687b ldr r3, [r7, #4]
8003712: 2201 movs r2, #1
8003714: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003718: 687b ldr r3, [r7, #4]
800371a: 2201 movs r2, #1
800371c: f883 2044 strb.w r2, [r3, #68] @ 0x44
8003720: 687b ldr r3, [r7, #4]
8003722: 2201 movs r2, #1
8003724: f883 2045 strb.w r2, [r3, #69] @ 0x45
8003728: 687b ldr r3, [r7, #4]
800372a: 2201 movs r2, #1
800372c: f883 2046 strb.w r2, [r3, #70] @ 0x46
8003730: 687b ldr r3, [r7, #4]
8003732: 2201 movs r2, #1
8003734: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003738: 687b ldr r3, [r7, #4]
800373a: 2201 movs r2, #1
800373c: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8003740: 2300 movs r3, #0
}
8003742: 4618 mov r0, r3
8003744: 3708 adds r7, #8
8003746: 46bd mov sp, r7
8003748: bd80 pop {r7, pc}
...
0800374c <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
800374c: b580 push {r7, lr}
800374e: b084 sub sp, #16
8003750: af00 add r7, sp, #0
8003752: 6078 str r0, [r7, #4]
8003754: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8003756: 683b ldr r3, [r7, #0]
8003758: 2b00 cmp r3, #0
800375a: d109 bne.n 8003770 <HAL_TIM_PWM_Start+0x24>
800375c: 687b ldr r3, [r7, #4]
800375e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
8003762: b2db uxtb r3, r3
8003764: 2b01 cmp r3, #1
8003766: bf14 ite ne
8003768: 2301 movne r3, #1
800376a: 2300 moveq r3, #0
800376c: b2db uxtb r3, r3
800376e: e03c b.n 80037ea <HAL_TIM_PWM_Start+0x9e>
8003770: 683b ldr r3, [r7, #0]
8003772: 2b04 cmp r3, #4
8003774: d109 bne.n 800378a <HAL_TIM_PWM_Start+0x3e>
8003776: 687b ldr r3, [r7, #4]
8003778: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
800377c: b2db uxtb r3, r3
800377e: 2b01 cmp r3, #1
8003780: bf14 ite ne
8003782: 2301 movne r3, #1
8003784: 2300 moveq r3, #0
8003786: b2db uxtb r3, r3
8003788: e02f b.n 80037ea <HAL_TIM_PWM_Start+0x9e>
800378a: 683b ldr r3, [r7, #0]
800378c: 2b08 cmp r3, #8
800378e: d109 bne.n 80037a4 <HAL_TIM_PWM_Start+0x58>
8003790: 687b ldr r3, [r7, #4]
8003792: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8003796: b2db uxtb r3, r3
8003798: 2b01 cmp r3, #1
800379a: bf14 ite ne
800379c: 2301 movne r3, #1
800379e: 2300 moveq r3, #0
80037a0: b2db uxtb r3, r3
80037a2: e022 b.n 80037ea <HAL_TIM_PWM_Start+0x9e>
80037a4: 683b ldr r3, [r7, #0]
80037a6: 2b0c cmp r3, #12
80037a8: d109 bne.n 80037be <HAL_TIM_PWM_Start+0x72>
80037aa: 687b ldr r3, [r7, #4]
80037ac: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80037b0: b2db uxtb r3, r3
80037b2: 2b01 cmp r3, #1
80037b4: bf14 ite ne
80037b6: 2301 movne r3, #1
80037b8: 2300 moveq r3, #0
80037ba: b2db uxtb r3, r3
80037bc: e015 b.n 80037ea <HAL_TIM_PWM_Start+0x9e>
80037be: 683b ldr r3, [r7, #0]
80037c0: 2b10 cmp r3, #16
80037c2: d109 bne.n 80037d8 <HAL_TIM_PWM_Start+0x8c>
80037c4: 687b ldr r3, [r7, #4]
80037c6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
80037ca: b2db uxtb r3, r3
80037cc: 2b01 cmp r3, #1
80037ce: bf14 ite ne
80037d0: 2301 movne r3, #1
80037d2: 2300 moveq r3, #0
80037d4: b2db uxtb r3, r3
80037d6: e008 b.n 80037ea <HAL_TIM_PWM_Start+0x9e>
80037d8: 687b ldr r3, [r7, #4]
80037da: f893 3043 ldrb.w r3, [r3, #67] @ 0x43
80037de: b2db uxtb r3, r3
80037e0: 2b01 cmp r3, #1
80037e2: bf14 ite ne
80037e4: 2301 movne r3, #1
80037e6: 2300 moveq r3, #0
80037e8: b2db uxtb r3, r3
80037ea: 2b00 cmp r3, #0
80037ec: d001 beq.n 80037f2 <HAL_TIM_PWM_Start+0xa6>
{
return HAL_ERROR;
80037ee: 2301 movs r3, #1
80037f0: e09c b.n 800392c <HAL_TIM_PWM_Start+0x1e0>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
80037f2: 683b ldr r3, [r7, #0]
80037f4: 2b00 cmp r3, #0
80037f6: d104 bne.n 8003802 <HAL_TIM_PWM_Start+0xb6>
80037f8: 687b ldr r3, [r7, #4]
80037fa: 2202 movs r2, #2
80037fc: f883 203e strb.w r2, [r3, #62] @ 0x3e
8003800: e023 b.n 800384a <HAL_TIM_PWM_Start+0xfe>
8003802: 683b ldr r3, [r7, #0]
8003804: 2b04 cmp r3, #4
8003806: d104 bne.n 8003812 <HAL_TIM_PWM_Start+0xc6>
8003808: 687b ldr r3, [r7, #4]
800380a: 2202 movs r2, #2
800380c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8003810: e01b b.n 800384a <HAL_TIM_PWM_Start+0xfe>
8003812: 683b ldr r3, [r7, #0]
8003814: 2b08 cmp r3, #8
8003816: d104 bne.n 8003822 <HAL_TIM_PWM_Start+0xd6>
8003818: 687b ldr r3, [r7, #4]
800381a: 2202 movs r2, #2
800381c: f883 2040 strb.w r2, [r3, #64] @ 0x40
8003820: e013 b.n 800384a <HAL_TIM_PWM_Start+0xfe>
8003822: 683b ldr r3, [r7, #0]
8003824: 2b0c cmp r3, #12
8003826: d104 bne.n 8003832 <HAL_TIM_PWM_Start+0xe6>
8003828: 687b ldr r3, [r7, #4]
800382a: 2202 movs r2, #2
800382c: f883 2041 strb.w r2, [r3, #65] @ 0x41
8003830: e00b b.n 800384a <HAL_TIM_PWM_Start+0xfe>
8003832: 683b ldr r3, [r7, #0]
8003834: 2b10 cmp r3, #16
8003836: d104 bne.n 8003842 <HAL_TIM_PWM_Start+0xf6>
8003838: 687b ldr r3, [r7, #4]
800383a: 2202 movs r2, #2
800383c: f883 2042 strb.w r2, [r3, #66] @ 0x42
8003840: e003 b.n 800384a <HAL_TIM_PWM_Start+0xfe>
8003842: 687b ldr r3, [r7, #4]
8003844: 2202 movs r2, #2
8003846: f883 2043 strb.w r2, [r3, #67] @ 0x43
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
800384a: 687b ldr r3, [r7, #4]
800384c: 681b ldr r3, [r3, #0]
800384e: 2201 movs r2, #1
8003850: 6839 ldr r1, [r7, #0]
8003852: 4618 mov r0, r3
8003854: f000 fd10 bl 8004278 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8003858: 687b ldr r3, [r7, #4]
800385a: 681b ldr r3, [r3, #0]
800385c: 4a35 ldr r2, [pc, #212] @ (8003934 <HAL_TIM_PWM_Start+0x1e8>)
800385e: 4293 cmp r3, r2
8003860: d013 beq.n 800388a <HAL_TIM_PWM_Start+0x13e>
8003862: 687b ldr r3, [r7, #4]
8003864: 681b ldr r3, [r3, #0]
8003866: 4a34 ldr r2, [pc, #208] @ (8003938 <HAL_TIM_PWM_Start+0x1ec>)
8003868: 4293 cmp r3, r2
800386a: d00e beq.n 800388a <HAL_TIM_PWM_Start+0x13e>
800386c: 687b ldr r3, [r7, #4]
800386e: 681b ldr r3, [r3, #0]
8003870: 4a32 ldr r2, [pc, #200] @ (800393c <HAL_TIM_PWM_Start+0x1f0>)
8003872: 4293 cmp r3, r2
8003874: d009 beq.n 800388a <HAL_TIM_PWM_Start+0x13e>
8003876: 687b ldr r3, [r7, #4]
8003878: 681b ldr r3, [r3, #0]
800387a: 4a31 ldr r2, [pc, #196] @ (8003940 <HAL_TIM_PWM_Start+0x1f4>)
800387c: 4293 cmp r3, r2
800387e: d004 beq.n 800388a <HAL_TIM_PWM_Start+0x13e>
8003880: 687b ldr r3, [r7, #4]
8003882: 681b ldr r3, [r3, #0]
8003884: 4a2f ldr r2, [pc, #188] @ (8003944 <HAL_TIM_PWM_Start+0x1f8>)
8003886: 4293 cmp r3, r2
8003888: d101 bne.n 800388e <HAL_TIM_PWM_Start+0x142>
800388a: 2301 movs r3, #1
800388c: e000 b.n 8003890 <HAL_TIM_PWM_Start+0x144>
800388e: 2300 movs r3, #0
8003890: 2b00 cmp r3, #0
8003892: d007 beq.n 80038a4 <HAL_TIM_PWM_Start+0x158>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8003894: 687b ldr r3, [r7, #4]
8003896: 681b ldr r3, [r3, #0]
8003898: 6c5a ldr r2, [r3, #68] @ 0x44
800389a: 687b ldr r3, [r7, #4]
800389c: 681b ldr r3, [r3, #0]
800389e: f442 4200 orr.w r2, r2, #32768 @ 0x8000
80038a2: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80038a4: 687b ldr r3, [r7, #4]
80038a6: 681b ldr r3, [r3, #0]
80038a8: 4a22 ldr r2, [pc, #136] @ (8003934 <HAL_TIM_PWM_Start+0x1e8>)
80038aa: 4293 cmp r3, r2
80038ac: d01d beq.n 80038ea <HAL_TIM_PWM_Start+0x19e>
80038ae: 687b ldr r3, [r7, #4]
80038b0: 681b ldr r3, [r3, #0]
80038b2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80038b6: d018 beq.n 80038ea <HAL_TIM_PWM_Start+0x19e>
80038b8: 687b ldr r3, [r7, #4]
80038ba: 681b ldr r3, [r3, #0]
80038bc: 4a22 ldr r2, [pc, #136] @ (8003948 <HAL_TIM_PWM_Start+0x1fc>)
80038be: 4293 cmp r3, r2
80038c0: d013 beq.n 80038ea <HAL_TIM_PWM_Start+0x19e>
80038c2: 687b ldr r3, [r7, #4]
80038c4: 681b ldr r3, [r3, #0]
80038c6: 4a21 ldr r2, [pc, #132] @ (800394c <HAL_TIM_PWM_Start+0x200>)
80038c8: 4293 cmp r3, r2
80038ca: d00e beq.n 80038ea <HAL_TIM_PWM_Start+0x19e>
80038cc: 687b ldr r3, [r7, #4]
80038ce: 681b ldr r3, [r3, #0]
80038d0: 4a1f ldr r2, [pc, #124] @ (8003950 <HAL_TIM_PWM_Start+0x204>)
80038d2: 4293 cmp r3, r2
80038d4: d009 beq.n 80038ea <HAL_TIM_PWM_Start+0x19e>
80038d6: 687b ldr r3, [r7, #4]
80038d8: 681b ldr r3, [r3, #0]
80038da: 4a17 ldr r2, [pc, #92] @ (8003938 <HAL_TIM_PWM_Start+0x1ec>)
80038dc: 4293 cmp r3, r2
80038de: d004 beq.n 80038ea <HAL_TIM_PWM_Start+0x19e>
80038e0: 687b ldr r3, [r7, #4]
80038e2: 681b ldr r3, [r3, #0]
80038e4: 4a15 ldr r2, [pc, #84] @ (800393c <HAL_TIM_PWM_Start+0x1f0>)
80038e6: 4293 cmp r3, r2
80038e8: d115 bne.n 8003916 <HAL_TIM_PWM_Start+0x1ca>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80038ea: 687b ldr r3, [r7, #4]
80038ec: 681b ldr r3, [r3, #0]
80038ee: 689a ldr r2, [r3, #8]
80038f0: 4b18 ldr r3, [pc, #96] @ (8003954 <HAL_TIM_PWM_Start+0x208>)
80038f2: 4013 ands r3, r2
80038f4: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80038f6: 68fb ldr r3, [r7, #12]
80038f8: 2b06 cmp r3, #6
80038fa: d015 beq.n 8003928 <HAL_TIM_PWM_Start+0x1dc>
80038fc: 68fb ldr r3, [r7, #12]
80038fe: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003902: d011 beq.n 8003928 <HAL_TIM_PWM_Start+0x1dc>
{
__HAL_TIM_ENABLE(htim);
8003904: 687b ldr r3, [r7, #4]
8003906: 681b ldr r3, [r3, #0]
8003908: 681a ldr r2, [r3, #0]
800390a: 687b ldr r3, [r7, #4]
800390c: 681b ldr r3, [r3, #0]
800390e: f042 0201 orr.w r2, r2, #1
8003912: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003914: e008 b.n 8003928 <HAL_TIM_PWM_Start+0x1dc>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8003916: 687b ldr r3, [r7, #4]
8003918: 681b ldr r3, [r3, #0]
800391a: 681a ldr r2, [r3, #0]
800391c: 687b ldr r3, [r7, #4]
800391e: 681b ldr r3, [r3, #0]
8003920: f042 0201 orr.w r2, r2, #1
8003924: 601a str r2, [r3, #0]
8003926: e000 b.n 800392a <HAL_TIM_PWM_Start+0x1de>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003928: bf00 nop
}
/* Return function status */
return HAL_OK;
800392a: 2300 movs r3, #0
}
800392c: 4618 mov r0, r3
800392e: 3710 adds r7, #16
8003930: 46bd mov sp, r7
8003932: bd80 pop {r7, pc}
8003934: 40012c00 .word 0x40012c00
8003938: 40013400 .word 0x40013400
800393c: 40014000 .word 0x40014000
8003940: 40014400 .word 0x40014400
8003944: 40014800 .word 0x40014800
8003948: 40000400 .word 0x40000400
800394c: 40000800 .word 0x40000800
8003950: 40000c00 .word 0x40000c00
8003954: 00010007 .word 0x00010007
08003958 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8003958: b580 push {r7, lr}
800395a: b086 sub sp, #24
800395c: af00 add r7, sp, #0
800395e: 60f8 str r0, [r7, #12]
8003960: 60b9 str r1, [r7, #8]
8003962: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003964: 2300 movs r3, #0
8003966: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8003968: 68fb ldr r3, [r7, #12]
800396a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800396e: 2b01 cmp r3, #1
8003970: d101 bne.n 8003976 <HAL_TIM_PWM_ConfigChannel+0x1e>
8003972: 2302 movs r3, #2
8003974: e0ff b.n 8003b76 <HAL_TIM_PWM_ConfigChannel+0x21e>
8003976: 68fb ldr r3, [r7, #12]
8003978: 2201 movs r2, #1
800397a: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
800397e: 687b ldr r3, [r7, #4]
8003980: 2b14 cmp r3, #20
8003982: f200 80f0 bhi.w 8003b66 <HAL_TIM_PWM_ConfigChannel+0x20e>
8003986: a201 add r2, pc, #4 @ (adr r2, 800398c <HAL_TIM_PWM_ConfigChannel+0x34>)
8003988: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800398c: 080039e1 .word 0x080039e1
8003990: 08003b67 .word 0x08003b67
8003994: 08003b67 .word 0x08003b67
8003998: 08003b67 .word 0x08003b67
800399c: 08003a21 .word 0x08003a21
80039a0: 08003b67 .word 0x08003b67
80039a4: 08003b67 .word 0x08003b67
80039a8: 08003b67 .word 0x08003b67
80039ac: 08003a63 .word 0x08003a63
80039b0: 08003b67 .word 0x08003b67
80039b4: 08003b67 .word 0x08003b67
80039b8: 08003b67 .word 0x08003b67
80039bc: 08003aa3 .word 0x08003aa3
80039c0: 08003b67 .word 0x08003b67
80039c4: 08003b67 .word 0x08003b67
80039c8: 08003b67 .word 0x08003b67
80039cc: 08003ae5 .word 0x08003ae5
80039d0: 08003b67 .word 0x08003b67
80039d4: 08003b67 .word 0x08003b67
80039d8: 08003b67 .word 0x08003b67
80039dc: 08003b25 .word 0x08003b25
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
80039e0: 68fb ldr r3, [r7, #12]
80039e2: 681b ldr r3, [r3, #0]
80039e4: 68b9 ldr r1, [r7, #8]
80039e6: 4618 mov r0, r3
80039e8: f000 f970 bl 8003ccc <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
80039ec: 68fb ldr r3, [r7, #12]
80039ee: 681b ldr r3, [r3, #0]
80039f0: 699a ldr r2, [r3, #24]
80039f2: 68fb ldr r3, [r7, #12]
80039f4: 681b ldr r3, [r3, #0]
80039f6: f042 0208 orr.w r2, r2, #8
80039fa: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
80039fc: 68fb ldr r3, [r7, #12]
80039fe: 681b ldr r3, [r3, #0]
8003a00: 699a ldr r2, [r3, #24]
8003a02: 68fb ldr r3, [r7, #12]
8003a04: 681b ldr r3, [r3, #0]
8003a06: f022 0204 bic.w r2, r2, #4
8003a0a: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8003a0c: 68fb ldr r3, [r7, #12]
8003a0e: 681b ldr r3, [r3, #0]
8003a10: 6999 ldr r1, [r3, #24]
8003a12: 68bb ldr r3, [r7, #8]
8003a14: 691a ldr r2, [r3, #16]
8003a16: 68fb ldr r3, [r7, #12]
8003a18: 681b ldr r3, [r3, #0]
8003a1a: 430a orrs r2, r1
8003a1c: 619a str r2, [r3, #24]
break;
8003a1e: e0a5 b.n 8003b6c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8003a20: 68fb ldr r3, [r7, #12]
8003a22: 681b ldr r3, [r3, #0]
8003a24: 68b9 ldr r1, [r7, #8]
8003a26: 4618 mov r0, r3
8003a28: f000 f9e0 bl 8003dec <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8003a2c: 68fb ldr r3, [r7, #12]
8003a2e: 681b ldr r3, [r3, #0]
8003a30: 699a ldr r2, [r3, #24]
8003a32: 68fb ldr r3, [r7, #12]
8003a34: 681b ldr r3, [r3, #0]
8003a36: f442 6200 orr.w r2, r2, #2048 @ 0x800
8003a3a: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8003a3c: 68fb ldr r3, [r7, #12]
8003a3e: 681b ldr r3, [r3, #0]
8003a40: 699a ldr r2, [r3, #24]
8003a42: 68fb ldr r3, [r7, #12]
8003a44: 681b ldr r3, [r3, #0]
8003a46: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003a4a: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8003a4c: 68fb ldr r3, [r7, #12]
8003a4e: 681b ldr r3, [r3, #0]
8003a50: 6999 ldr r1, [r3, #24]
8003a52: 68bb ldr r3, [r7, #8]
8003a54: 691b ldr r3, [r3, #16]
8003a56: 021a lsls r2, r3, #8
8003a58: 68fb ldr r3, [r7, #12]
8003a5a: 681b ldr r3, [r3, #0]
8003a5c: 430a orrs r2, r1
8003a5e: 619a str r2, [r3, #24]
break;
8003a60: e084 b.n 8003b6c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8003a62: 68fb ldr r3, [r7, #12]
8003a64: 681b ldr r3, [r3, #0]
8003a66: 68b9 ldr r1, [r7, #8]
8003a68: 4618 mov r0, r3
8003a6a: f000 fa49 bl 8003f00 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8003a6e: 68fb ldr r3, [r7, #12]
8003a70: 681b ldr r3, [r3, #0]
8003a72: 69da ldr r2, [r3, #28]
8003a74: 68fb ldr r3, [r7, #12]
8003a76: 681b ldr r3, [r3, #0]
8003a78: f042 0208 orr.w r2, r2, #8
8003a7c: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8003a7e: 68fb ldr r3, [r7, #12]
8003a80: 681b ldr r3, [r3, #0]
8003a82: 69da ldr r2, [r3, #28]
8003a84: 68fb ldr r3, [r7, #12]
8003a86: 681b ldr r3, [r3, #0]
8003a88: f022 0204 bic.w r2, r2, #4
8003a8c: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8003a8e: 68fb ldr r3, [r7, #12]
8003a90: 681b ldr r3, [r3, #0]
8003a92: 69d9 ldr r1, [r3, #28]
8003a94: 68bb ldr r3, [r7, #8]
8003a96: 691a ldr r2, [r3, #16]
8003a98: 68fb ldr r3, [r7, #12]
8003a9a: 681b ldr r3, [r3, #0]
8003a9c: 430a orrs r2, r1
8003a9e: 61da str r2, [r3, #28]
break;
8003aa0: e064 b.n 8003b6c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8003aa2: 68fb ldr r3, [r7, #12]
8003aa4: 681b ldr r3, [r3, #0]
8003aa6: 68b9 ldr r1, [r7, #8]
8003aa8: 4618 mov r0, r3
8003aaa: f000 fab1 bl 8004010 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8003aae: 68fb ldr r3, [r7, #12]
8003ab0: 681b ldr r3, [r3, #0]
8003ab2: 69da ldr r2, [r3, #28]
8003ab4: 68fb ldr r3, [r7, #12]
8003ab6: 681b ldr r3, [r3, #0]
8003ab8: f442 6200 orr.w r2, r2, #2048 @ 0x800
8003abc: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8003abe: 68fb ldr r3, [r7, #12]
8003ac0: 681b ldr r3, [r3, #0]
8003ac2: 69da ldr r2, [r3, #28]
8003ac4: 68fb ldr r3, [r7, #12]
8003ac6: 681b ldr r3, [r3, #0]
8003ac8: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003acc: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8003ace: 68fb ldr r3, [r7, #12]
8003ad0: 681b ldr r3, [r3, #0]
8003ad2: 69d9 ldr r1, [r3, #28]
8003ad4: 68bb ldr r3, [r7, #8]
8003ad6: 691b ldr r3, [r3, #16]
8003ad8: 021a lsls r2, r3, #8
8003ada: 68fb ldr r3, [r7, #12]
8003adc: 681b ldr r3, [r3, #0]
8003ade: 430a orrs r2, r1
8003ae0: 61da str r2, [r3, #28]
break;
8003ae2: e043 b.n 8003b6c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8003ae4: 68fb ldr r3, [r7, #12]
8003ae6: 681b ldr r3, [r3, #0]
8003ae8: 68b9 ldr r1, [r7, #8]
8003aea: 4618 mov r0, r3
8003aec: f000 fafa bl 80040e4 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8003af0: 68fb ldr r3, [r7, #12]
8003af2: 681b ldr r3, [r3, #0]
8003af4: 6d5a ldr r2, [r3, #84] @ 0x54
8003af6: 68fb ldr r3, [r7, #12]
8003af8: 681b ldr r3, [r3, #0]
8003afa: f042 0208 orr.w r2, r2, #8
8003afe: 655a str r2, [r3, #84] @ 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8003b00: 68fb ldr r3, [r7, #12]
8003b02: 681b ldr r3, [r3, #0]
8003b04: 6d5a ldr r2, [r3, #84] @ 0x54
8003b06: 68fb ldr r3, [r7, #12]
8003b08: 681b ldr r3, [r3, #0]
8003b0a: f022 0204 bic.w r2, r2, #4
8003b0e: 655a str r2, [r3, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8003b10: 68fb ldr r3, [r7, #12]
8003b12: 681b ldr r3, [r3, #0]
8003b14: 6d59 ldr r1, [r3, #84] @ 0x54
8003b16: 68bb ldr r3, [r7, #8]
8003b18: 691a ldr r2, [r3, #16]
8003b1a: 68fb ldr r3, [r7, #12]
8003b1c: 681b ldr r3, [r3, #0]
8003b1e: 430a orrs r2, r1
8003b20: 655a str r2, [r3, #84] @ 0x54
break;
8003b22: e023 b.n 8003b6c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8003b24: 68fb ldr r3, [r7, #12]
8003b26: 681b ldr r3, [r3, #0]
8003b28: 68b9 ldr r1, [r7, #8]
8003b2a: 4618 mov r0, r3
8003b2c: f000 fb3e bl 80041ac <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8003b30: 68fb ldr r3, [r7, #12]
8003b32: 681b ldr r3, [r3, #0]
8003b34: 6d5a ldr r2, [r3, #84] @ 0x54
8003b36: 68fb ldr r3, [r7, #12]
8003b38: 681b ldr r3, [r3, #0]
8003b3a: f442 6200 orr.w r2, r2, #2048 @ 0x800
8003b3e: 655a str r2, [r3, #84] @ 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8003b40: 68fb ldr r3, [r7, #12]
8003b42: 681b ldr r3, [r3, #0]
8003b44: 6d5a ldr r2, [r3, #84] @ 0x54
8003b46: 68fb ldr r3, [r7, #12]
8003b48: 681b ldr r3, [r3, #0]
8003b4a: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003b4e: 655a str r2, [r3, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8003b50: 68fb ldr r3, [r7, #12]
8003b52: 681b ldr r3, [r3, #0]
8003b54: 6d59 ldr r1, [r3, #84] @ 0x54
8003b56: 68bb ldr r3, [r7, #8]
8003b58: 691b ldr r3, [r3, #16]
8003b5a: 021a lsls r2, r3, #8
8003b5c: 68fb ldr r3, [r7, #12]
8003b5e: 681b ldr r3, [r3, #0]
8003b60: 430a orrs r2, r1
8003b62: 655a str r2, [r3, #84] @ 0x54
break;
8003b64: e002 b.n 8003b6c <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
status = HAL_ERROR;
8003b66: 2301 movs r3, #1
8003b68: 75fb strb r3, [r7, #23]
break;
8003b6a: bf00 nop
}
__HAL_UNLOCK(htim);
8003b6c: 68fb ldr r3, [r7, #12]
8003b6e: 2200 movs r2, #0
8003b70: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8003b74: 7dfb ldrb r3, [r7, #23]
}
8003b76: 4618 mov r0, r3
8003b78: 3718 adds r7, #24
8003b7a: 46bd mov sp, r7
8003b7c: bd80 pop {r7, pc}
8003b7e: bf00 nop
08003b80 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8003b80: b480 push {r7}
8003b82: b085 sub sp, #20
8003b84: af00 add r7, sp, #0
8003b86: 6078 str r0, [r7, #4]
8003b88: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8003b8a: 687b ldr r3, [r7, #4]
8003b8c: 681b ldr r3, [r3, #0]
8003b8e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8003b90: 687b ldr r3, [r7, #4]
8003b92: 4a46 ldr r2, [pc, #280] @ (8003cac <TIM_Base_SetConfig+0x12c>)
8003b94: 4293 cmp r3, r2
8003b96: d013 beq.n 8003bc0 <TIM_Base_SetConfig+0x40>
8003b98: 687b ldr r3, [r7, #4]
8003b9a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8003b9e: d00f beq.n 8003bc0 <TIM_Base_SetConfig+0x40>
8003ba0: 687b ldr r3, [r7, #4]
8003ba2: 4a43 ldr r2, [pc, #268] @ (8003cb0 <TIM_Base_SetConfig+0x130>)
8003ba4: 4293 cmp r3, r2
8003ba6: d00b beq.n 8003bc0 <TIM_Base_SetConfig+0x40>
8003ba8: 687b ldr r3, [r7, #4]
8003baa: 4a42 ldr r2, [pc, #264] @ (8003cb4 <TIM_Base_SetConfig+0x134>)
8003bac: 4293 cmp r3, r2
8003bae: d007 beq.n 8003bc0 <TIM_Base_SetConfig+0x40>
8003bb0: 687b ldr r3, [r7, #4]
8003bb2: 4a41 ldr r2, [pc, #260] @ (8003cb8 <TIM_Base_SetConfig+0x138>)
8003bb4: 4293 cmp r3, r2
8003bb6: d003 beq.n 8003bc0 <TIM_Base_SetConfig+0x40>
8003bb8: 687b ldr r3, [r7, #4]
8003bba: 4a40 ldr r2, [pc, #256] @ (8003cbc <TIM_Base_SetConfig+0x13c>)
8003bbc: 4293 cmp r3, r2
8003bbe: d108 bne.n 8003bd2 <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8003bc0: 68fb ldr r3, [r7, #12]
8003bc2: f023 0370 bic.w r3, r3, #112 @ 0x70
8003bc6: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8003bc8: 683b ldr r3, [r7, #0]
8003bca: 685b ldr r3, [r3, #4]
8003bcc: 68fa ldr r2, [r7, #12]
8003bce: 4313 orrs r3, r2
8003bd0: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8003bd2: 687b ldr r3, [r7, #4]
8003bd4: 4a35 ldr r2, [pc, #212] @ (8003cac <TIM_Base_SetConfig+0x12c>)
8003bd6: 4293 cmp r3, r2
8003bd8: d01f beq.n 8003c1a <TIM_Base_SetConfig+0x9a>
8003bda: 687b ldr r3, [r7, #4]
8003bdc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8003be0: d01b beq.n 8003c1a <TIM_Base_SetConfig+0x9a>
8003be2: 687b ldr r3, [r7, #4]
8003be4: 4a32 ldr r2, [pc, #200] @ (8003cb0 <TIM_Base_SetConfig+0x130>)
8003be6: 4293 cmp r3, r2
8003be8: d017 beq.n 8003c1a <TIM_Base_SetConfig+0x9a>
8003bea: 687b ldr r3, [r7, #4]
8003bec: 4a31 ldr r2, [pc, #196] @ (8003cb4 <TIM_Base_SetConfig+0x134>)
8003bee: 4293 cmp r3, r2
8003bf0: d013 beq.n 8003c1a <TIM_Base_SetConfig+0x9a>
8003bf2: 687b ldr r3, [r7, #4]
8003bf4: 4a30 ldr r2, [pc, #192] @ (8003cb8 <TIM_Base_SetConfig+0x138>)
8003bf6: 4293 cmp r3, r2
8003bf8: d00f beq.n 8003c1a <TIM_Base_SetConfig+0x9a>
8003bfa: 687b ldr r3, [r7, #4]
8003bfc: 4a2f ldr r2, [pc, #188] @ (8003cbc <TIM_Base_SetConfig+0x13c>)
8003bfe: 4293 cmp r3, r2
8003c00: d00b beq.n 8003c1a <TIM_Base_SetConfig+0x9a>
8003c02: 687b ldr r3, [r7, #4]
8003c04: 4a2e ldr r2, [pc, #184] @ (8003cc0 <TIM_Base_SetConfig+0x140>)
8003c06: 4293 cmp r3, r2
8003c08: d007 beq.n 8003c1a <TIM_Base_SetConfig+0x9a>
8003c0a: 687b ldr r3, [r7, #4]
8003c0c: 4a2d ldr r2, [pc, #180] @ (8003cc4 <TIM_Base_SetConfig+0x144>)
8003c0e: 4293 cmp r3, r2
8003c10: d003 beq.n 8003c1a <TIM_Base_SetConfig+0x9a>
8003c12: 687b ldr r3, [r7, #4]
8003c14: 4a2c ldr r2, [pc, #176] @ (8003cc8 <TIM_Base_SetConfig+0x148>)
8003c16: 4293 cmp r3, r2
8003c18: d108 bne.n 8003c2c <TIM_Base_SetConfig+0xac>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8003c1a: 68fb ldr r3, [r7, #12]
8003c1c: f423 7340 bic.w r3, r3, #768 @ 0x300
8003c20: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8003c22: 683b ldr r3, [r7, #0]
8003c24: 68db ldr r3, [r3, #12]
8003c26: 68fa ldr r2, [r7, #12]
8003c28: 4313 orrs r3, r2
8003c2a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003c2c: 68fb ldr r3, [r7, #12]
8003c2e: f023 0280 bic.w r2, r3, #128 @ 0x80
8003c32: 683b ldr r3, [r7, #0]
8003c34: 695b ldr r3, [r3, #20]
8003c36: 4313 orrs r3, r2
8003c38: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8003c3a: 687b ldr r3, [r7, #4]
8003c3c: 68fa ldr r2, [r7, #12]
8003c3e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8003c40: 683b ldr r3, [r7, #0]
8003c42: 689a ldr r2, [r3, #8]
8003c44: 687b ldr r3, [r7, #4]
8003c46: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8003c48: 683b ldr r3, [r7, #0]
8003c4a: 681a ldr r2, [r3, #0]
8003c4c: 687b ldr r3, [r7, #4]
8003c4e: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8003c50: 687b ldr r3, [r7, #4]
8003c52: 4a16 ldr r2, [pc, #88] @ (8003cac <TIM_Base_SetConfig+0x12c>)
8003c54: 4293 cmp r3, r2
8003c56: d00f beq.n 8003c78 <TIM_Base_SetConfig+0xf8>
8003c58: 687b ldr r3, [r7, #4]
8003c5a: 4a18 ldr r2, [pc, #96] @ (8003cbc <TIM_Base_SetConfig+0x13c>)
8003c5c: 4293 cmp r3, r2
8003c5e: d00b beq.n 8003c78 <TIM_Base_SetConfig+0xf8>
8003c60: 687b ldr r3, [r7, #4]
8003c62: 4a17 ldr r2, [pc, #92] @ (8003cc0 <TIM_Base_SetConfig+0x140>)
8003c64: 4293 cmp r3, r2
8003c66: d007 beq.n 8003c78 <TIM_Base_SetConfig+0xf8>
8003c68: 687b ldr r3, [r7, #4]
8003c6a: 4a16 ldr r2, [pc, #88] @ (8003cc4 <TIM_Base_SetConfig+0x144>)
8003c6c: 4293 cmp r3, r2
8003c6e: d003 beq.n 8003c78 <TIM_Base_SetConfig+0xf8>
8003c70: 687b ldr r3, [r7, #4]
8003c72: 4a15 ldr r2, [pc, #84] @ (8003cc8 <TIM_Base_SetConfig+0x148>)
8003c74: 4293 cmp r3, r2
8003c76: d103 bne.n 8003c80 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8003c78: 683b ldr r3, [r7, #0]
8003c7a: 691a ldr r2, [r3, #16]
8003c7c: 687b ldr r3, [r7, #4]
8003c7e: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8003c80: 687b ldr r3, [r7, #4]
8003c82: 2201 movs r2, #1
8003c84: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8003c86: 687b ldr r3, [r7, #4]
8003c88: 691b ldr r3, [r3, #16]
8003c8a: f003 0301 and.w r3, r3, #1
8003c8e: 2b01 cmp r3, #1
8003c90: d105 bne.n 8003c9e <TIM_Base_SetConfig+0x11e>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8003c92: 687b ldr r3, [r7, #4]
8003c94: 691b ldr r3, [r3, #16]
8003c96: f023 0201 bic.w r2, r3, #1
8003c9a: 687b ldr r3, [r7, #4]
8003c9c: 611a str r2, [r3, #16]
}
}
8003c9e: bf00 nop
8003ca0: 3714 adds r7, #20
8003ca2: 46bd mov sp, r7
8003ca4: f85d 7b04 ldr.w r7, [sp], #4
8003ca8: 4770 bx lr
8003caa: bf00 nop
8003cac: 40012c00 .word 0x40012c00
8003cb0: 40000400 .word 0x40000400
8003cb4: 40000800 .word 0x40000800
8003cb8: 40000c00 .word 0x40000c00
8003cbc: 40013400 .word 0x40013400
8003cc0: 40014000 .word 0x40014000
8003cc4: 40014400 .word 0x40014400
8003cc8: 40014800 .word 0x40014800
08003ccc <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8003ccc: b480 push {r7}
8003cce: b087 sub sp, #28
8003cd0: af00 add r7, sp, #0
8003cd2: 6078 str r0, [r7, #4]
8003cd4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003cd6: 687b ldr r3, [r7, #4]
8003cd8: 6a1b ldr r3, [r3, #32]
8003cda: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8003cdc: 687b ldr r3, [r7, #4]
8003cde: 6a1b ldr r3, [r3, #32]
8003ce0: f023 0201 bic.w r2, r3, #1
8003ce4: 687b ldr r3, [r7, #4]
8003ce6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003ce8: 687b ldr r3, [r7, #4]
8003cea: 685b ldr r3, [r3, #4]
8003cec: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8003cee: 687b ldr r3, [r7, #4]
8003cf0: 699b ldr r3, [r3, #24]
8003cf2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8003cf4: 68fb ldr r3, [r7, #12]
8003cf6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003cfa: f023 0370 bic.w r3, r3, #112 @ 0x70
8003cfe: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8003d00: 68fb ldr r3, [r7, #12]
8003d02: f023 0303 bic.w r3, r3, #3
8003d06: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8003d08: 683b ldr r3, [r7, #0]
8003d0a: 681b ldr r3, [r3, #0]
8003d0c: 68fa ldr r2, [r7, #12]
8003d0e: 4313 orrs r3, r2
8003d10: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8003d12: 697b ldr r3, [r7, #20]
8003d14: f023 0302 bic.w r3, r3, #2
8003d18: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8003d1a: 683b ldr r3, [r7, #0]
8003d1c: 689b ldr r3, [r3, #8]
8003d1e: 697a ldr r2, [r7, #20]
8003d20: 4313 orrs r3, r2
8003d22: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8003d24: 687b ldr r3, [r7, #4]
8003d26: 4a2c ldr r2, [pc, #176] @ (8003dd8 <TIM_OC1_SetConfig+0x10c>)
8003d28: 4293 cmp r3, r2
8003d2a: d00f beq.n 8003d4c <TIM_OC1_SetConfig+0x80>
8003d2c: 687b ldr r3, [r7, #4]
8003d2e: 4a2b ldr r2, [pc, #172] @ (8003ddc <TIM_OC1_SetConfig+0x110>)
8003d30: 4293 cmp r3, r2
8003d32: d00b beq.n 8003d4c <TIM_OC1_SetConfig+0x80>
8003d34: 687b ldr r3, [r7, #4]
8003d36: 4a2a ldr r2, [pc, #168] @ (8003de0 <TIM_OC1_SetConfig+0x114>)
8003d38: 4293 cmp r3, r2
8003d3a: d007 beq.n 8003d4c <TIM_OC1_SetConfig+0x80>
8003d3c: 687b ldr r3, [r7, #4]
8003d3e: 4a29 ldr r2, [pc, #164] @ (8003de4 <TIM_OC1_SetConfig+0x118>)
8003d40: 4293 cmp r3, r2
8003d42: d003 beq.n 8003d4c <TIM_OC1_SetConfig+0x80>
8003d44: 687b ldr r3, [r7, #4]
8003d46: 4a28 ldr r2, [pc, #160] @ (8003de8 <TIM_OC1_SetConfig+0x11c>)
8003d48: 4293 cmp r3, r2
8003d4a: d10c bne.n 8003d66 <TIM_OC1_SetConfig+0x9a>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8003d4c: 697b ldr r3, [r7, #20]
8003d4e: f023 0308 bic.w r3, r3, #8
8003d52: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8003d54: 683b ldr r3, [r7, #0]
8003d56: 68db ldr r3, [r3, #12]
8003d58: 697a ldr r2, [r7, #20]
8003d5a: 4313 orrs r3, r2
8003d5c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8003d5e: 697b ldr r3, [r7, #20]
8003d60: f023 0304 bic.w r3, r3, #4
8003d64: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003d66: 687b ldr r3, [r7, #4]
8003d68: 4a1b ldr r2, [pc, #108] @ (8003dd8 <TIM_OC1_SetConfig+0x10c>)
8003d6a: 4293 cmp r3, r2
8003d6c: d00f beq.n 8003d8e <TIM_OC1_SetConfig+0xc2>
8003d6e: 687b ldr r3, [r7, #4]
8003d70: 4a1a ldr r2, [pc, #104] @ (8003ddc <TIM_OC1_SetConfig+0x110>)
8003d72: 4293 cmp r3, r2
8003d74: d00b beq.n 8003d8e <TIM_OC1_SetConfig+0xc2>
8003d76: 687b ldr r3, [r7, #4]
8003d78: 4a19 ldr r2, [pc, #100] @ (8003de0 <TIM_OC1_SetConfig+0x114>)
8003d7a: 4293 cmp r3, r2
8003d7c: d007 beq.n 8003d8e <TIM_OC1_SetConfig+0xc2>
8003d7e: 687b ldr r3, [r7, #4]
8003d80: 4a18 ldr r2, [pc, #96] @ (8003de4 <TIM_OC1_SetConfig+0x118>)
8003d82: 4293 cmp r3, r2
8003d84: d003 beq.n 8003d8e <TIM_OC1_SetConfig+0xc2>
8003d86: 687b ldr r3, [r7, #4]
8003d88: 4a17 ldr r2, [pc, #92] @ (8003de8 <TIM_OC1_SetConfig+0x11c>)
8003d8a: 4293 cmp r3, r2
8003d8c: d111 bne.n 8003db2 <TIM_OC1_SetConfig+0xe6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8003d8e: 693b ldr r3, [r7, #16]
8003d90: f423 7380 bic.w r3, r3, #256 @ 0x100
8003d94: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8003d96: 693b ldr r3, [r7, #16]
8003d98: f423 7300 bic.w r3, r3, #512 @ 0x200
8003d9c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8003d9e: 683b ldr r3, [r7, #0]
8003da0: 695b ldr r3, [r3, #20]
8003da2: 693a ldr r2, [r7, #16]
8003da4: 4313 orrs r3, r2
8003da6: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8003da8: 683b ldr r3, [r7, #0]
8003daa: 699b ldr r3, [r3, #24]
8003dac: 693a ldr r2, [r7, #16]
8003dae: 4313 orrs r3, r2
8003db0: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003db2: 687b ldr r3, [r7, #4]
8003db4: 693a ldr r2, [r7, #16]
8003db6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8003db8: 687b ldr r3, [r7, #4]
8003dba: 68fa ldr r2, [r7, #12]
8003dbc: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8003dbe: 683b ldr r3, [r7, #0]
8003dc0: 685a ldr r2, [r3, #4]
8003dc2: 687b ldr r3, [r7, #4]
8003dc4: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003dc6: 687b ldr r3, [r7, #4]
8003dc8: 697a ldr r2, [r7, #20]
8003dca: 621a str r2, [r3, #32]
}
8003dcc: bf00 nop
8003dce: 371c adds r7, #28
8003dd0: 46bd mov sp, r7
8003dd2: f85d 7b04 ldr.w r7, [sp], #4
8003dd6: 4770 bx lr
8003dd8: 40012c00 .word 0x40012c00
8003ddc: 40013400 .word 0x40013400
8003de0: 40014000 .word 0x40014000
8003de4: 40014400 .word 0x40014400
8003de8: 40014800 .word 0x40014800
08003dec <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8003dec: b480 push {r7}
8003dee: b087 sub sp, #28
8003df0: af00 add r7, sp, #0
8003df2: 6078 str r0, [r7, #4]
8003df4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003df6: 687b ldr r3, [r7, #4]
8003df8: 6a1b ldr r3, [r3, #32]
8003dfa: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8003dfc: 687b ldr r3, [r7, #4]
8003dfe: 6a1b ldr r3, [r3, #32]
8003e00: f023 0210 bic.w r2, r3, #16
8003e04: 687b ldr r3, [r7, #4]
8003e06: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003e08: 687b ldr r3, [r7, #4]
8003e0a: 685b ldr r3, [r3, #4]
8003e0c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8003e0e: 687b ldr r3, [r7, #4]
8003e10: 699b ldr r3, [r3, #24]
8003e12: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8003e14: 68fb ldr r3, [r7, #12]
8003e16: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8003e1a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8003e1e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8003e20: 68fb ldr r3, [r7, #12]
8003e22: f423 7340 bic.w r3, r3, #768 @ 0x300
8003e26: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8003e28: 683b ldr r3, [r7, #0]
8003e2a: 681b ldr r3, [r3, #0]
8003e2c: 021b lsls r3, r3, #8
8003e2e: 68fa ldr r2, [r7, #12]
8003e30: 4313 orrs r3, r2
8003e32: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8003e34: 697b ldr r3, [r7, #20]
8003e36: f023 0320 bic.w r3, r3, #32
8003e3a: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8003e3c: 683b ldr r3, [r7, #0]
8003e3e: 689b ldr r3, [r3, #8]
8003e40: 011b lsls r3, r3, #4
8003e42: 697a ldr r2, [r7, #20]
8003e44: 4313 orrs r3, r2
8003e46: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8003e48: 687b ldr r3, [r7, #4]
8003e4a: 4a28 ldr r2, [pc, #160] @ (8003eec <TIM_OC2_SetConfig+0x100>)
8003e4c: 4293 cmp r3, r2
8003e4e: d003 beq.n 8003e58 <TIM_OC2_SetConfig+0x6c>
8003e50: 687b ldr r3, [r7, #4]
8003e52: 4a27 ldr r2, [pc, #156] @ (8003ef0 <TIM_OC2_SetConfig+0x104>)
8003e54: 4293 cmp r3, r2
8003e56: d10d bne.n 8003e74 <TIM_OC2_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8003e58: 697b ldr r3, [r7, #20]
8003e5a: f023 0380 bic.w r3, r3, #128 @ 0x80
8003e5e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8003e60: 683b ldr r3, [r7, #0]
8003e62: 68db ldr r3, [r3, #12]
8003e64: 011b lsls r3, r3, #4
8003e66: 697a ldr r2, [r7, #20]
8003e68: 4313 orrs r3, r2
8003e6a: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8003e6c: 697b ldr r3, [r7, #20]
8003e6e: f023 0340 bic.w r3, r3, #64 @ 0x40
8003e72: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003e74: 687b ldr r3, [r7, #4]
8003e76: 4a1d ldr r2, [pc, #116] @ (8003eec <TIM_OC2_SetConfig+0x100>)
8003e78: 4293 cmp r3, r2
8003e7a: d00f beq.n 8003e9c <TIM_OC2_SetConfig+0xb0>
8003e7c: 687b ldr r3, [r7, #4]
8003e7e: 4a1c ldr r2, [pc, #112] @ (8003ef0 <TIM_OC2_SetConfig+0x104>)
8003e80: 4293 cmp r3, r2
8003e82: d00b beq.n 8003e9c <TIM_OC2_SetConfig+0xb0>
8003e84: 687b ldr r3, [r7, #4]
8003e86: 4a1b ldr r2, [pc, #108] @ (8003ef4 <TIM_OC2_SetConfig+0x108>)
8003e88: 4293 cmp r3, r2
8003e8a: d007 beq.n 8003e9c <TIM_OC2_SetConfig+0xb0>
8003e8c: 687b ldr r3, [r7, #4]
8003e8e: 4a1a ldr r2, [pc, #104] @ (8003ef8 <TIM_OC2_SetConfig+0x10c>)
8003e90: 4293 cmp r3, r2
8003e92: d003 beq.n 8003e9c <TIM_OC2_SetConfig+0xb0>
8003e94: 687b ldr r3, [r7, #4]
8003e96: 4a19 ldr r2, [pc, #100] @ (8003efc <TIM_OC2_SetConfig+0x110>)
8003e98: 4293 cmp r3, r2
8003e9a: d113 bne.n 8003ec4 <TIM_OC2_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8003e9c: 693b ldr r3, [r7, #16]
8003e9e: f423 6380 bic.w r3, r3, #1024 @ 0x400
8003ea2: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8003ea4: 693b ldr r3, [r7, #16]
8003ea6: f423 6300 bic.w r3, r3, #2048 @ 0x800
8003eaa: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8003eac: 683b ldr r3, [r7, #0]
8003eae: 695b ldr r3, [r3, #20]
8003eb0: 009b lsls r3, r3, #2
8003eb2: 693a ldr r2, [r7, #16]
8003eb4: 4313 orrs r3, r2
8003eb6: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8003eb8: 683b ldr r3, [r7, #0]
8003eba: 699b ldr r3, [r3, #24]
8003ebc: 009b lsls r3, r3, #2
8003ebe: 693a ldr r2, [r7, #16]
8003ec0: 4313 orrs r3, r2
8003ec2: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003ec4: 687b ldr r3, [r7, #4]
8003ec6: 693a ldr r2, [r7, #16]
8003ec8: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 68fa ldr r2, [r7, #12]
8003ece: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8003ed0: 683b ldr r3, [r7, #0]
8003ed2: 685a ldr r2, [r3, #4]
8003ed4: 687b ldr r3, [r7, #4]
8003ed6: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003ed8: 687b ldr r3, [r7, #4]
8003eda: 697a ldr r2, [r7, #20]
8003edc: 621a str r2, [r3, #32]
}
8003ede: bf00 nop
8003ee0: 371c adds r7, #28
8003ee2: 46bd mov sp, r7
8003ee4: f85d 7b04 ldr.w r7, [sp], #4
8003ee8: 4770 bx lr
8003eea: bf00 nop
8003eec: 40012c00 .word 0x40012c00
8003ef0: 40013400 .word 0x40013400
8003ef4: 40014000 .word 0x40014000
8003ef8: 40014400 .word 0x40014400
8003efc: 40014800 .word 0x40014800
08003f00 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8003f00: b480 push {r7}
8003f02: b087 sub sp, #28
8003f04: af00 add r7, sp, #0
8003f06: 6078 str r0, [r7, #4]
8003f08: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003f0a: 687b ldr r3, [r7, #4]
8003f0c: 6a1b ldr r3, [r3, #32]
8003f0e: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8003f10: 687b ldr r3, [r7, #4]
8003f12: 6a1b ldr r3, [r3, #32]
8003f14: f423 7280 bic.w r2, r3, #256 @ 0x100
8003f18: 687b ldr r3, [r7, #4]
8003f1a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003f1c: 687b ldr r3, [r7, #4]
8003f1e: 685b ldr r3, [r3, #4]
8003f20: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8003f22: 687b ldr r3, [r7, #4]
8003f24: 69db ldr r3, [r3, #28]
8003f26: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8003f28: 68fb ldr r3, [r7, #12]
8003f2a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003f2e: f023 0370 bic.w r3, r3, #112 @ 0x70
8003f32: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8003f34: 68fb ldr r3, [r7, #12]
8003f36: f023 0303 bic.w r3, r3, #3
8003f3a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8003f3c: 683b ldr r3, [r7, #0]
8003f3e: 681b ldr r3, [r3, #0]
8003f40: 68fa ldr r2, [r7, #12]
8003f42: 4313 orrs r3, r2
8003f44: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8003f46: 697b ldr r3, [r7, #20]
8003f48: f423 7300 bic.w r3, r3, #512 @ 0x200
8003f4c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8003f4e: 683b ldr r3, [r7, #0]
8003f50: 689b ldr r3, [r3, #8]
8003f52: 021b lsls r3, r3, #8
8003f54: 697a ldr r2, [r7, #20]
8003f56: 4313 orrs r3, r2
8003f58: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8003f5a: 687b ldr r3, [r7, #4]
8003f5c: 4a27 ldr r2, [pc, #156] @ (8003ffc <TIM_OC3_SetConfig+0xfc>)
8003f5e: 4293 cmp r3, r2
8003f60: d003 beq.n 8003f6a <TIM_OC3_SetConfig+0x6a>
8003f62: 687b ldr r3, [r7, #4]
8003f64: 4a26 ldr r2, [pc, #152] @ (8004000 <TIM_OC3_SetConfig+0x100>)
8003f66: 4293 cmp r3, r2
8003f68: d10d bne.n 8003f86 <TIM_OC3_SetConfig+0x86>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8003f6a: 697b ldr r3, [r7, #20]
8003f6c: f423 6300 bic.w r3, r3, #2048 @ 0x800
8003f70: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8003f72: 683b ldr r3, [r7, #0]
8003f74: 68db ldr r3, [r3, #12]
8003f76: 021b lsls r3, r3, #8
8003f78: 697a ldr r2, [r7, #20]
8003f7a: 4313 orrs r3, r2
8003f7c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8003f7e: 697b ldr r3, [r7, #20]
8003f80: f423 6380 bic.w r3, r3, #1024 @ 0x400
8003f84: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003f86: 687b ldr r3, [r7, #4]
8003f88: 4a1c ldr r2, [pc, #112] @ (8003ffc <TIM_OC3_SetConfig+0xfc>)
8003f8a: 4293 cmp r3, r2
8003f8c: d00f beq.n 8003fae <TIM_OC3_SetConfig+0xae>
8003f8e: 687b ldr r3, [r7, #4]
8003f90: 4a1b ldr r2, [pc, #108] @ (8004000 <TIM_OC3_SetConfig+0x100>)
8003f92: 4293 cmp r3, r2
8003f94: d00b beq.n 8003fae <TIM_OC3_SetConfig+0xae>
8003f96: 687b ldr r3, [r7, #4]
8003f98: 4a1a ldr r2, [pc, #104] @ (8004004 <TIM_OC3_SetConfig+0x104>)
8003f9a: 4293 cmp r3, r2
8003f9c: d007 beq.n 8003fae <TIM_OC3_SetConfig+0xae>
8003f9e: 687b ldr r3, [r7, #4]
8003fa0: 4a19 ldr r2, [pc, #100] @ (8004008 <TIM_OC3_SetConfig+0x108>)
8003fa2: 4293 cmp r3, r2
8003fa4: d003 beq.n 8003fae <TIM_OC3_SetConfig+0xae>
8003fa6: 687b ldr r3, [r7, #4]
8003fa8: 4a18 ldr r2, [pc, #96] @ (800400c <TIM_OC3_SetConfig+0x10c>)
8003faa: 4293 cmp r3, r2
8003fac: d113 bne.n 8003fd6 <TIM_OC3_SetConfig+0xd6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8003fae: 693b ldr r3, [r7, #16]
8003fb0: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8003fb4: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8003fb6: 693b ldr r3, [r7, #16]
8003fb8: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8003fbc: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8003fbe: 683b ldr r3, [r7, #0]
8003fc0: 695b ldr r3, [r3, #20]
8003fc2: 011b lsls r3, r3, #4
8003fc4: 693a ldr r2, [r7, #16]
8003fc6: 4313 orrs r3, r2
8003fc8: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8003fca: 683b ldr r3, [r7, #0]
8003fcc: 699b ldr r3, [r3, #24]
8003fce: 011b lsls r3, r3, #4
8003fd0: 693a ldr r2, [r7, #16]
8003fd2: 4313 orrs r3, r2
8003fd4: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003fd6: 687b ldr r3, [r7, #4]
8003fd8: 693a ldr r2, [r7, #16]
8003fda: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8003fdc: 687b ldr r3, [r7, #4]
8003fde: 68fa ldr r2, [r7, #12]
8003fe0: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8003fe2: 683b ldr r3, [r7, #0]
8003fe4: 685a ldr r2, [r3, #4]
8003fe6: 687b ldr r3, [r7, #4]
8003fe8: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003fea: 687b ldr r3, [r7, #4]
8003fec: 697a ldr r2, [r7, #20]
8003fee: 621a str r2, [r3, #32]
}
8003ff0: bf00 nop
8003ff2: 371c adds r7, #28
8003ff4: 46bd mov sp, r7
8003ff6: f85d 7b04 ldr.w r7, [sp], #4
8003ffa: 4770 bx lr
8003ffc: 40012c00 .word 0x40012c00
8004000: 40013400 .word 0x40013400
8004004: 40014000 .word 0x40014000
8004008: 40014400 .word 0x40014400
800400c: 40014800 .word 0x40014800
08004010 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004010: b480 push {r7}
8004012: b087 sub sp, #28
8004014: af00 add r7, sp, #0
8004016: 6078 str r0, [r7, #4]
8004018: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800401a: 687b ldr r3, [r7, #4]
800401c: 6a1b ldr r3, [r3, #32]
800401e: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8004020: 687b ldr r3, [r7, #4]
8004022: 6a1b ldr r3, [r3, #32]
8004024: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8004028: 687b ldr r3, [r7, #4]
800402a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800402c: 687b ldr r3, [r7, #4]
800402e: 685b ldr r3, [r3, #4]
8004030: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8004032: 687b ldr r3, [r7, #4]
8004034: 69db ldr r3, [r3, #28]
8004036: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8004038: 68fb ldr r3, [r7, #12]
800403a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800403e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004042: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8004044: 68fb ldr r3, [r7, #12]
8004046: f423 7340 bic.w r3, r3, #768 @ 0x300
800404a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800404c: 683b ldr r3, [r7, #0]
800404e: 681b ldr r3, [r3, #0]
8004050: 021b lsls r3, r3, #8
8004052: 68fa ldr r2, [r7, #12]
8004054: 4313 orrs r3, r2
8004056: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8004058: 693b ldr r3, [r7, #16]
800405a: f423 5300 bic.w r3, r3, #8192 @ 0x2000
800405e: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8004060: 683b ldr r3, [r7, #0]
8004062: 689b ldr r3, [r3, #8]
8004064: 031b lsls r3, r3, #12
8004066: 693a ldr r2, [r7, #16]
8004068: 4313 orrs r3, r2
800406a: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800406c: 687b ldr r3, [r7, #4]
800406e: 4a18 ldr r2, [pc, #96] @ (80040d0 <TIM_OC4_SetConfig+0xc0>)
8004070: 4293 cmp r3, r2
8004072: d00f beq.n 8004094 <TIM_OC4_SetConfig+0x84>
8004074: 687b ldr r3, [r7, #4]
8004076: 4a17 ldr r2, [pc, #92] @ (80040d4 <TIM_OC4_SetConfig+0xc4>)
8004078: 4293 cmp r3, r2
800407a: d00b beq.n 8004094 <TIM_OC4_SetConfig+0x84>
800407c: 687b ldr r3, [r7, #4]
800407e: 4a16 ldr r2, [pc, #88] @ (80040d8 <TIM_OC4_SetConfig+0xc8>)
8004080: 4293 cmp r3, r2
8004082: d007 beq.n 8004094 <TIM_OC4_SetConfig+0x84>
8004084: 687b ldr r3, [r7, #4]
8004086: 4a15 ldr r2, [pc, #84] @ (80040dc <TIM_OC4_SetConfig+0xcc>)
8004088: 4293 cmp r3, r2
800408a: d003 beq.n 8004094 <TIM_OC4_SetConfig+0x84>
800408c: 687b ldr r3, [r7, #4]
800408e: 4a14 ldr r2, [pc, #80] @ (80040e0 <TIM_OC4_SetConfig+0xd0>)
8004090: 4293 cmp r3, r2
8004092: d109 bne.n 80040a8 <TIM_OC4_SetConfig+0x98>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8004094: 697b ldr r3, [r7, #20]
8004096: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800409a: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
800409c: 683b ldr r3, [r7, #0]
800409e: 695b ldr r3, [r3, #20]
80040a0: 019b lsls r3, r3, #6
80040a2: 697a ldr r2, [r7, #20]
80040a4: 4313 orrs r3, r2
80040a6: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80040a8: 687b ldr r3, [r7, #4]
80040aa: 697a ldr r2, [r7, #20]
80040ac: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80040ae: 687b ldr r3, [r7, #4]
80040b0: 68fa ldr r2, [r7, #12]
80040b2: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80040b4: 683b ldr r3, [r7, #0]
80040b6: 685a ldr r2, [r3, #4]
80040b8: 687b ldr r3, [r7, #4]
80040ba: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80040bc: 687b ldr r3, [r7, #4]
80040be: 693a ldr r2, [r7, #16]
80040c0: 621a str r2, [r3, #32]
}
80040c2: bf00 nop
80040c4: 371c adds r7, #28
80040c6: 46bd mov sp, r7
80040c8: f85d 7b04 ldr.w r7, [sp], #4
80040cc: 4770 bx lr
80040ce: bf00 nop
80040d0: 40012c00 .word 0x40012c00
80040d4: 40013400 .word 0x40013400
80040d8: 40014000 .word 0x40014000
80040dc: 40014400 .word 0x40014400
80040e0: 40014800 .word 0x40014800
080040e4 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80040e4: b480 push {r7}
80040e6: b087 sub sp, #28
80040e8: af00 add r7, sp, #0
80040ea: 6078 str r0, [r7, #4]
80040ec: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80040ee: 687b ldr r3, [r7, #4]
80040f0: 6a1b ldr r3, [r3, #32]
80040f2: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
80040f4: 687b ldr r3, [r7, #4]
80040f6: 6a1b ldr r3, [r3, #32]
80040f8: f423 3280 bic.w r2, r3, #65536 @ 0x10000
80040fc: 687b ldr r3, [r7, #4]
80040fe: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004100: 687b ldr r3, [r7, #4]
8004102: 685b ldr r3, [r3, #4]
8004104: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8004106: 687b ldr r3, [r7, #4]
8004108: 6d5b ldr r3, [r3, #84] @ 0x54
800410a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
800410c: 68fb ldr r3, [r7, #12]
800410e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004112: f023 0370 bic.w r3, r3, #112 @ 0x70
8004116: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8004118: 683b ldr r3, [r7, #0]
800411a: 681b ldr r3, [r3, #0]
800411c: 68fa ldr r2, [r7, #12]
800411e: 4313 orrs r3, r2
8004120: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
8004122: 693b ldr r3, [r7, #16]
8004124: f423 3300 bic.w r3, r3, #131072 @ 0x20000
8004128: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
800412a: 683b ldr r3, [r7, #0]
800412c: 689b ldr r3, [r3, #8]
800412e: 041b lsls r3, r3, #16
8004130: 693a ldr r2, [r7, #16]
8004132: 4313 orrs r3, r2
8004134: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004136: 687b ldr r3, [r7, #4]
8004138: 4a17 ldr r2, [pc, #92] @ (8004198 <TIM_OC5_SetConfig+0xb4>)
800413a: 4293 cmp r3, r2
800413c: d00f beq.n 800415e <TIM_OC5_SetConfig+0x7a>
800413e: 687b ldr r3, [r7, #4]
8004140: 4a16 ldr r2, [pc, #88] @ (800419c <TIM_OC5_SetConfig+0xb8>)
8004142: 4293 cmp r3, r2
8004144: d00b beq.n 800415e <TIM_OC5_SetConfig+0x7a>
8004146: 687b ldr r3, [r7, #4]
8004148: 4a15 ldr r2, [pc, #84] @ (80041a0 <TIM_OC5_SetConfig+0xbc>)
800414a: 4293 cmp r3, r2
800414c: d007 beq.n 800415e <TIM_OC5_SetConfig+0x7a>
800414e: 687b ldr r3, [r7, #4]
8004150: 4a14 ldr r2, [pc, #80] @ (80041a4 <TIM_OC5_SetConfig+0xc0>)
8004152: 4293 cmp r3, r2
8004154: d003 beq.n 800415e <TIM_OC5_SetConfig+0x7a>
8004156: 687b ldr r3, [r7, #4]
8004158: 4a13 ldr r2, [pc, #76] @ (80041a8 <TIM_OC5_SetConfig+0xc4>)
800415a: 4293 cmp r3, r2
800415c: d109 bne.n 8004172 <TIM_OC5_SetConfig+0x8e>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
800415e: 697b ldr r3, [r7, #20]
8004160: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004164: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
8004166: 683b ldr r3, [r7, #0]
8004168: 695b ldr r3, [r3, #20]
800416a: 021b lsls r3, r3, #8
800416c: 697a ldr r2, [r7, #20]
800416e: 4313 orrs r3, r2
8004170: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004172: 687b ldr r3, [r7, #4]
8004174: 697a ldr r2, [r7, #20]
8004176: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8004178: 687b ldr r3, [r7, #4]
800417a: 68fa ldr r2, [r7, #12]
800417c: 655a str r2, [r3, #84] @ 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
800417e: 683b ldr r3, [r7, #0]
8004180: 685a ldr r2, [r3, #4]
8004182: 687b ldr r3, [r7, #4]
8004184: 659a str r2, [r3, #88] @ 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004186: 687b ldr r3, [r7, #4]
8004188: 693a ldr r2, [r7, #16]
800418a: 621a str r2, [r3, #32]
}
800418c: bf00 nop
800418e: 371c adds r7, #28
8004190: 46bd mov sp, r7
8004192: f85d 7b04 ldr.w r7, [sp], #4
8004196: 4770 bx lr
8004198: 40012c00 .word 0x40012c00
800419c: 40013400 .word 0x40013400
80041a0: 40014000 .word 0x40014000
80041a4: 40014400 .word 0x40014400
80041a8: 40014800 .word 0x40014800
080041ac <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80041ac: b480 push {r7}
80041ae: b087 sub sp, #28
80041b0: af00 add r7, sp, #0
80041b2: 6078 str r0, [r7, #4]
80041b4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80041b6: 687b ldr r3, [r7, #4]
80041b8: 6a1b ldr r3, [r3, #32]
80041ba: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
80041bc: 687b ldr r3, [r7, #4]
80041be: 6a1b ldr r3, [r3, #32]
80041c0: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
80041c4: 687b ldr r3, [r7, #4]
80041c6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80041c8: 687b ldr r3, [r7, #4]
80041ca: 685b ldr r3, [r3, #4]
80041cc: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
80041ce: 687b ldr r3, [r7, #4]
80041d0: 6d5b ldr r3, [r3, #84] @ 0x54
80041d2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
80041d4: 68fb ldr r3, [r7, #12]
80041d6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80041da: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80041de: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80041e0: 683b ldr r3, [r7, #0]
80041e2: 681b ldr r3, [r3, #0]
80041e4: 021b lsls r3, r3, #8
80041e6: 68fa ldr r2, [r7, #12]
80041e8: 4313 orrs r3, r2
80041ea: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
80041ec: 693b ldr r3, [r7, #16]
80041ee: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
80041f2: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
80041f4: 683b ldr r3, [r7, #0]
80041f6: 689b ldr r3, [r3, #8]
80041f8: 051b lsls r3, r3, #20
80041fa: 693a ldr r2, [r7, #16]
80041fc: 4313 orrs r3, r2
80041fe: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004200: 687b ldr r3, [r7, #4]
8004202: 4a18 ldr r2, [pc, #96] @ (8004264 <TIM_OC6_SetConfig+0xb8>)
8004204: 4293 cmp r3, r2
8004206: d00f beq.n 8004228 <TIM_OC6_SetConfig+0x7c>
8004208: 687b ldr r3, [r7, #4]
800420a: 4a17 ldr r2, [pc, #92] @ (8004268 <TIM_OC6_SetConfig+0xbc>)
800420c: 4293 cmp r3, r2
800420e: d00b beq.n 8004228 <TIM_OC6_SetConfig+0x7c>
8004210: 687b ldr r3, [r7, #4]
8004212: 4a16 ldr r2, [pc, #88] @ (800426c <TIM_OC6_SetConfig+0xc0>)
8004214: 4293 cmp r3, r2
8004216: d007 beq.n 8004228 <TIM_OC6_SetConfig+0x7c>
8004218: 687b ldr r3, [r7, #4]
800421a: 4a15 ldr r2, [pc, #84] @ (8004270 <TIM_OC6_SetConfig+0xc4>)
800421c: 4293 cmp r3, r2
800421e: d003 beq.n 8004228 <TIM_OC6_SetConfig+0x7c>
8004220: 687b ldr r3, [r7, #4]
8004222: 4a14 ldr r2, [pc, #80] @ (8004274 <TIM_OC6_SetConfig+0xc8>)
8004224: 4293 cmp r3, r2
8004226: d109 bne.n 800423c <TIM_OC6_SetConfig+0x90>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8004228: 697b ldr r3, [r7, #20]
800422a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800422e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8004230: 683b ldr r3, [r7, #0]
8004232: 695b ldr r3, [r3, #20]
8004234: 029b lsls r3, r3, #10
8004236: 697a ldr r2, [r7, #20]
8004238: 4313 orrs r3, r2
800423a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800423c: 687b ldr r3, [r7, #4]
800423e: 697a ldr r2, [r7, #20]
8004240: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8004242: 687b ldr r3, [r7, #4]
8004244: 68fa ldr r2, [r7, #12]
8004246: 655a str r2, [r3, #84] @ 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8004248: 683b ldr r3, [r7, #0]
800424a: 685a ldr r2, [r3, #4]
800424c: 687b ldr r3, [r7, #4]
800424e: 65da str r2, [r3, #92] @ 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004250: 687b ldr r3, [r7, #4]
8004252: 693a ldr r2, [r7, #16]
8004254: 621a str r2, [r3, #32]
}
8004256: bf00 nop
8004258: 371c adds r7, #28
800425a: 46bd mov sp, r7
800425c: f85d 7b04 ldr.w r7, [sp], #4
8004260: 4770 bx lr
8004262: bf00 nop
8004264: 40012c00 .word 0x40012c00
8004268: 40013400 .word 0x40013400
800426c: 40014000 .word 0x40014000
8004270: 40014400 .word 0x40014400
8004274: 40014800 .word 0x40014800
08004278 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8004278: b480 push {r7}
800427a: b087 sub sp, #28
800427c: af00 add r7, sp, #0
800427e: 60f8 str r0, [r7, #12]
8004280: 60b9 str r1, [r7, #8]
8004282: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8004284: 68bb ldr r3, [r7, #8]
8004286: f003 031f and.w r3, r3, #31
800428a: 2201 movs r2, #1
800428c: fa02 f303 lsl.w r3, r2, r3
8004290: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8004292: 68fb ldr r3, [r7, #12]
8004294: 6a1a ldr r2, [r3, #32]
8004296: 697b ldr r3, [r7, #20]
8004298: 43db mvns r3, r3
800429a: 401a ands r2, r3
800429c: 68fb ldr r3, [r7, #12]
800429e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
80042a0: 68fb ldr r3, [r7, #12]
80042a2: 6a1a ldr r2, [r3, #32]
80042a4: 68bb ldr r3, [r7, #8]
80042a6: f003 031f and.w r3, r3, #31
80042aa: 6879 ldr r1, [r7, #4]
80042ac: fa01 f303 lsl.w r3, r1, r3
80042b0: 431a orrs r2, r3
80042b2: 68fb ldr r3, [r7, #12]
80042b4: 621a str r2, [r3, #32]
}
80042b6: bf00 nop
80042b8: 371c adds r7, #28
80042ba: 46bd mov sp, r7
80042bc: f85d 7b04 ldr.w r7, [sp], #4
80042c0: 4770 bx lr
...
080042c4 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
80042c4: b480 push {r7}
80042c6: b085 sub sp, #20
80042c8: af00 add r7, sp, #0
80042ca: 6078 str r0, [r7, #4]
80042cc: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80042ce: 687b ldr r3, [r7, #4]
80042d0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80042d4: 2b01 cmp r3, #1
80042d6: d101 bne.n 80042dc <HAL_TIMEx_MasterConfigSynchronization+0x18>
80042d8: 2302 movs r3, #2
80042da: e068 b.n 80043ae <HAL_TIMEx_MasterConfigSynchronization+0xea>
80042dc: 687b ldr r3, [r7, #4]
80042de: 2201 movs r2, #1
80042e0: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80042e4: 687b ldr r3, [r7, #4]
80042e6: 2202 movs r2, #2
80042e8: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80042ec: 687b ldr r3, [r7, #4]
80042ee: 681b ldr r3, [r3, #0]
80042f0: 685b ldr r3, [r3, #4]
80042f2: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80042f4: 687b ldr r3, [r7, #4]
80042f6: 681b ldr r3, [r3, #0]
80042f8: 689b ldr r3, [r3, #8]
80042fa: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80042fc: 687b ldr r3, [r7, #4]
80042fe: 681b ldr r3, [r3, #0]
8004300: 4a2e ldr r2, [pc, #184] @ (80043bc <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
8004302: 4293 cmp r3, r2
8004304: d004 beq.n 8004310 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
8004306: 687b ldr r3, [r7, #4]
8004308: 681b ldr r3, [r3, #0]
800430a: 4a2d ldr r2, [pc, #180] @ (80043c0 <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
800430c: 4293 cmp r3, r2
800430e: d108 bne.n 8004322 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8004310: 68fb ldr r3, [r7, #12]
8004312: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
8004316: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8004318: 683b ldr r3, [r7, #0]
800431a: 685b ldr r3, [r3, #4]
800431c: 68fa ldr r2, [r7, #12]
800431e: 4313 orrs r3, r2
8004320: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8004322: 68fb ldr r3, [r7, #12]
8004324: f023 0370 bic.w r3, r3, #112 @ 0x70
8004328: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800432a: 683b ldr r3, [r7, #0]
800432c: 681b ldr r3, [r3, #0]
800432e: 68fa ldr r2, [r7, #12]
8004330: 4313 orrs r3, r2
8004332: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8004334: 687b ldr r3, [r7, #4]
8004336: 681b ldr r3, [r3, #0]
8004338: 68fa ldr r2, [r7, #12]
800433a: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800433c: 687b ldr r3, [r7, #4]
800433e: 681b ldr r3, [r3, #0]
8004340: 4a1e ldr r2, [pc, #120] @ (80043bc <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
8004342: 4293 cmp r3, r2
8004344: d01d beq.n 8004382 <HAL_TIMEx_MasterConfigSynchronization+0xbe>
8004346: 687b ldr r3, [r7, #4]
8004348: 681b ldr r3, [r3, #0]
800434a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800434e: d018 beq.n 8004382 <HAL_TIMEx_MasterConfigSynchronization+0xbe>
8004350: 687b ldr r3, [r7, #4]
8004352: 681b ldr r3, [r3, #0]
8004354: 4a1b ldr r2, [pc, #108] @ (80043c4 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
8004356: 4293 cmp r3, r2
8004358: d013 beq.n 8004382 <HAL_TIMEx_MasterConfigSynchronization+0xbe>
800435a: 687b ldr r3, [r7, #4]
800435c: 681b ldr r3, [r3, #0]
800435e: 4a1a ldr r2, [pc, #104] @ (80043c8 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
8004360: 4293 cmp r3, r2
8004362: d00e beq.n 8004382 <HAL_TIMEx_MasterConfigSynchronization+0xbe>
8004364: 687b ldr r3, [r7, #4]
8004366: 681b ldr r3, [r3, #0]
8004368: 4a18 ldr r2, [pc, #96] @ (80043cc <HAL_TIMEx_MasterConfigSynchronization+0x108>)
800436a: 4293 cmp r3, r2
800436c: d009 beq.n 8004382 <HAL_TIMEx_MasterConfigSynchronization+0xbe>
800436e: 687b ldr r3, [r7, #4]
8004370: 681b ldr r3, [r3, #0]
8004372: 4a13 ldr r2, [pc, #76] @ (80043c0 <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
8004374: 4293 cmp r3, r2
8004376: d004 beq.n 8004382 <HAL_TIMEx_MasterConfigSynchronization+0xbe>
8004378: 687b ldr r3, [r7, #4]
800437a: 681b ldr r3, [r3, #0]
800437c: 4a14 ldr r2, [pc, #80] @ (80043d0 <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
800437e: 4293 cmp r3, r2
8004380: d10c bne.n 800439c <HAL_TIMEx_MasterConfigSynchronization+0xd8>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8004382: 68bb ldr r3, [r7, #8]
8004384: f023 0380 bic.w r3, r3, #128 @ 0x80
8004388: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800438a: 683b ldr r3, [r7, #0]
800438c: 689b ldr r3, [r3, #8]
800438e: 68ba ldr r2, [r7, #8]
8004390: 4313 orrs r3, r2
8004392: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8004394: 687b ldr r3, [r7, #4]
8004396: 681b ldr r3, [r3, #0]
8004398: 68ba ldr r2, [r7, #8]
800439a: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
800439c: 687b ldr r3, [r7, #4]
800439e: 2201 movs r2, #1
80043a0: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
80043a4: 687b ldr r3, [r7, #4]
80043a6: 2200 movs r2, #0
80043a8: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80043ac: 2300 movs r3, #0
}
80043ae: 4618 mov r0, r3
80043b0: 3714 adds r7, #20
80043b2: 46bd mov sp, r7
80043b4: f85d 7b04 ldr.w r7, [sp], #4
80043b8: 4770 bx lr
80043ba: bf00 nop
80043bc: 40012c00 .word 0x40012c00
80043c0: 40013400 .word 0x40013400
80043c4: 40000400 .word 0x40000400
80043c8: 40000800 .word 0x40000800
80043cc: 40000c00 .word 0x40000c00
80043d0: 40014000 .word 0x40014000
080043d4 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80043d4: b580 push {r7, lr}
80043d6: b082 sub sp, #8
80043d8: af00 add r7, sp, #0
80043da: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80043dc: 687b ldr r3, [r7, #4]
80043de: 2b00 cmp r3, #0
80043e0: d101 bne.n 80043e6 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80043e2: 2301 movs r3, #1
80043e4: e040 b.n 8004468 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
80043e6: 687b ldr r3, [r7, #4]
80043e8: 6fdb ldr r3, [r3, #124] @ 0x7c
80043ea: 2b00 cmp r3, #0
80043ec: d106 bne.n 80043fc <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80043ee: 687b ldr r3, [r7, #4]
80043f0: 2200 movs r2, #0
80043f2: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80043f6: 6878 ldr r0, [r7, #4]
80043f8: f7fc fc1a bl 8000c30 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80043fc: 687b ldr r3, [r7, #4]
80043fe: 2224 movs r2, #36 @ 0x24
8004400: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
8004402: 687b ldr r3, [r7, #4]
8004404: 681b ldr r3, [r3, #0]
8004406: 681a ldr r2, [r3, #0]
8004408: 687b ldr r3, [r7, #4]
800440a: 681b ldr r3, [r3, #0]
800440c: f022 0201 bic.w r2, r2, #1
8004410: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8004412: 687b ldr r3, [r7, #4]
8004414: 6a5b ldr r3, [r3, #36] @ 0x24
8004416: 2b00 cmp r3, #0
8004418: d002 beq.n 8004420 <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
800441a: 6878 ldr r0, [r7, #4]
800441c: f000 fae0 bl 80049e0 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8004420: 6878 ldr r0, [r7, #4]
8004422: f000 f825 bl 8004470 <UART_SetConfig>
8004426: 4603 mov r3, r0
8004428: 2b01 cmp r3, #1
800442a: d101 bne.n 8004430 <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
800442c: 2301 movs r3, #1
800442e: e01b b.n 8004468 <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8004430: 687b ldr r3, [r7, #4]
8004432: 681b ldr r3, [r3, #0]
8004434: 685a ldr r2, [r3, #4]
8004436: 687b ldr r3, [r7, #4]
8004438: 681b ldr r3, [r3, #0]
800443a: f422 4290 bic.w r2, r2, #18432 @ 0x4800
800443e: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8004440: 687b ldr r3, [r7, #4]
8004442: 681b ldr r3, [r3, #0]
8004444: 689a ldr r2, [r3, #8]
8004446: 687b ldr r3, [r7, #4]
8004448: 681b ldr r3, [r3, #0]
800444a: f022 022a bic.w r2, r2, #42 @ 0x2a
800444e: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8004450: 687b ldr r3, [r7, #4]
8004452: 681b ldr r3, [r3, #0]
8004454: 681a ldr r2, [r3, #0]
8004456: 687b ldr r3, [r7, #4]
8004458: 681b ldr r3, [r3, #0]
800445a: f042 0201 orr.w r2, r2, #1
800445e: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8004460: 6878 ldr r0, [r7, #4]
8004462: f000 fb5f bl 8004b24 <UART_CheckIdleState>
8004466: 4603 mov r3, r0
}
8004468: 4618 mov r0, r3
800446a: 3708 adds r7, #8
800446c: 46bd mov sp, r7
800446e: bd80 pop {r7, pc}
08004470 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8004470: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8004474: b08a sub sp, #40 @ 0x28
8004476: af00 add r7, sp, #0
8004478: 60f8 str r0, [r7, #12]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
800447a: 2300 movs r3, #0
800447c: f887 3022 strb.w r3, [r7, #34] @ 0x22
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8004480: 68fb ldr r3, [r7, #12]
8004482: 689a ldr r2, [r3, #8]
8004484: 68fb ldr r3, [r7, #12]
8004486: 691b ldr r3, [r3, #16]
8004488: 431a orrs r2, r3
800448a: 68fb ldr r3, [r7, #12]
800448c: 695b ldr r3, [r3, #20]
800448e: 431a orrs r2, r3
8004490: 68fb ldr r3, [r7, #12]
8004492: 69db ldr r3, [r3, #28]
8004494: 4313 orrs r3, r2
8004496: 627b str r3, [r7, #36] @ 0x24
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8004498: 68fb ldr r3, [r7, #12]
800449a: 681b ldr r3, [r3, #0]
800449c: 681a ldr r2, [r3, #0]
800449e: 4ba4 ldr r3, [pc, #656] @ (8004730 <UART_SetConfig+0x2c0>)
80044a0: 4013 ands r3, r2
80044a2: 68fa ldr r2, [r7, #12]
80044a4: 6812 ldr r2, [r2, #0]
80044a6: 6a79 ldr r1, [r7, #36] @ 0x24
80044a8: 430b orrs r3, r1
80044aa: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80044ac: 68fb ldr r3, [r7, #12]
80044ae: 681b ldr r3, [r3, #0]
80044b0: 685b ldr r3, [r3, #4]
80044b2: f423 5140 bic.w r1, r3, #12288 @ 0x3000
80044b6: 68fb ldr r3, [r7, #12]
80044b8: 68da ldr r2, [r3, #12]
80044ba: 68fb ldr r3, [r7, #12]
80044bc: 681b ldr r3, [r3, #0]
80044be: 430a orrs r2, r1
80044c0: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
80044c2: 68fb ldr r3, [r7, #12]
80044c4: 699b ldr r3, [r3, #24]
80044c6: 627b str r3, [r7, #36] @ 0x24
if (!(UART_INSTANCE_LOWPOWER(huart)))
80044c8: 68fb ldr r3, [r7, #12]
80044ca: 681b ldr r3, [r3, #0]
80044cc: 4a99 ldr r2, [pc, #612] @ (8004734 <UART_SetConfig+0x2c4>)
80044ce: 4293 cmp r3, r2
80044d0: d004 beq.n 80044dc <UART_SetConfig+0x6c>
{
tmpreg |= huart->Init.OneBitSampling;
80044d2: 68fb ldr r3, [r7, #12]
80044d4: 6a1b ldr r3, [r3, #32]
80044d6: 6a7a ldr r2, [r7, #36] @ 0x24
80044d8: 4313 orrs r3, r2
80044da: 627b str r3, [r7, #36] @ 0x24
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
80044dc: 68fb ldr r3, [r7, #12]
80044de: 681b ldr r3, [r3, #0]
80044e0: 689b ldr r3, [r3, #8]
80044e2: f423 6130 bic.w r1, r3, #2816 @ 0xb00
80044e6: 68fb ldr r3, [r7, #12]
80044e8: 681b ldr r3, [r3, #0]
80044ea: 6a7a ldr r2, [r7, #36] @ 0x24
80044ec: 430a orrs r2, r1
80044ee: 609a str r2, [r3, #8]
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
#endif /* USART_PRESC_PRESCALER */
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
80044f0: 68fb ldr r3, [r7, #12]
80044f2: 681b ldr r3, [r3, #0]
80044f4: 4a90 ldr r2, [pc, #576] @ (8004738 <UART_SetConfig+0x2c8>)
80044f6: 4293 cmp r3, r2
80044f8: d126 bne.n 8004548 <UART_SetConfig+0xd8>
80044fa: 4b90 ldr r3, [pc, #576] @ (800473c <UART_SetConfig+0x2cc>)
80044fc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004500: f003 0303 and.w r3, r3, #3
8004504: 2b03 cmp r3, #3
8004506: d81b bhi.n 8004540 <UART_SetConfig+0xd0>
8004508: a201 add r2, pc, #4 @ (adr r2, 8004510 <UART_SetConfig+0xa0>)
800450a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800450e: bf00 nop
8004510: 08004521 .word 0x08004521
8004514: 08004531 .word 0x08004531
8004518: 08004529 .word 0x08004529
800451c: 08004539 .word 0x08004539
8004520: 2301 movs r3, #1
8004522: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004526: e116 b.n 8004756 <UART_SetConfig+0x2e6>
8004528: 2302 movs r3, #2
800452a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800452e: e112 b.n 8004756 <UART_SetConfig+0x2e6>
8004530: 2304 movs r3, #4
8004532: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004536: e10e b.n 8004756 <UART_SetConfig+0x2e6>
8004538: 2308 movs r3, #8
800453a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800453e: e10a b.n 8004756 <UART_SetConfig+0x2e6>
8004540: 2310 movs r3, #16
8004542: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004546: e106 b.n 8004756 <UART_SetConfig+0x2e6>
8004548: 68fb ldr r3, [r7, #12]
800454a: 681b ldr r3, [r3, #0]
800454c: 4a7c ldr r2, [pc, #496] @ (8004740 <UART_SetConfig+0x2d0>)
800454e: 4293 cmp r3, r2
8004550: d138 bne.n 80045c4 <UART_SetConfig+0x154>
8004552: 4b7a ldr r3, [pc, #488] @ (800473c <UART_SetConfig+0x2cc>)
8004554: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004558: f003 030c and.w r3, r3, #12
800455c: 2b0c cmp r3, #12
800455e: d82d bhi.n 80045bc <UART_SetConfig+0x14c>
8004560: a201 add r2, pc, #4 @ (adr r2, 8004568 <UART_SetConfig+0xf8>)
8004562: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004566: bf00 nop
8004568: 0800459d .word 0x0800459d
800456c: 080045bd .word 0x080045bd
8004570: 080045bd .word 0x080045bd
8004574: 080045bd .word 0x080045bd
8004578: 080045ad .word 0x080045ad
800457c: 080045bd .word 0x080045bd
8004580: 080045bd .word 0x080045bd
8004584: 080045bd .word 0x080045bd
8004588: 080045a5 .word 0x080045a5
800458c: 080045bd .word 0x080045bd
8004590: 080045bd .word 0x080045bd
8004594: 080045bd .word 0x080045bd
8004598: 080045b5 .word 0x080045b5
800459c: 2300 movs r3, #0
800459e: f887 3023 strb.w r3, [r7, #35] @ 0x23
80045a2: e0d8 b.n 8004756 <UART_SetConfig+0x2e6>
80045a4: 2302 movs r3, #2
80045a6: f887 3023 strb.w r3, [r7, #35] @ 0x23
80045aa: e0d4 b.n 8004756 <UART_SetConfig+0x2e6>
80045ac: 2304 movs r3, #4
80045ae: f887 3023 strb.w r3, [r7, #35] @ 0x23
80045b2: e0d0 b.n 8004756 <UART_SetConfig+0x2e6>
80045b4: 2308 movs r3, #8
80045b6: f887 3023 strb.w r3, [r7, #35] @ 0x23
80045ba: e0cc b.n 8004756 <UART_SetConfig+0x2e6>
80045bc: 2310 movs r3, #16
80045be: f887 3023 strb.w r3, [r7, #35] @ 0x23
80045c2: e0c8 b.n 8004756 <UART_SetConfig+0x2e6>
80045c4: 68fb ldr r3, [r7, #12]
80045c6: 681b ldr r3, [r3, #0]
80045c8: 4a5e ldr r2, [pc, #376] @ (8004744 <UART_SetConfig+0x2d4>)
80045ca: 4293 cmp r3, r2
80045cc: d125 bne.n 800461a <UART_SetConfig+0x1aa>
80045ce: 4b5b ldr r3, [pc, #364] @ (800473c <UART_SetConfig+0x2cc>)
80045d0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80045d4: f003 0330 and.w r3, r3, #48 @ 0x30
80045d8: 2b30 cmp r3, #48 @ 0x30
80045da: d016 beq.n 800460a <UART_SetConfig+0x19a>
80045dc: 2b30 cmp r3, #48 @ 0x30
80045de: d818 bhi.n 8004612 <UART_SetConfig+0x1a2>
80045e0: 2b20 cmp r3, #32
80045e2: d00a beq.n 80045fa <UART_SetConfig+0x18a>
80045e4: 2b20 cmp r3, #32
80045e6: d814 bhi.n 8004612 <UART_SetConfig+0x1a2>
80045e8: 2b00 cmp r3, #0
80045ea: d002 beq.n 80045f2 <UART_SetConfig+0x182>
80045ec: 2b10 cmp r3, #16
80045ee: d008 beq.n 8004602 <UART_SetConfig+0x192>
80045f0: e00f b.n 8004612 <UART_SetConfig+0x1a2>
80045f2: 2300 movs r3, #0
80045f4: f887 3023 strb.w r3, [r7, #35] @ 0x23
80045f8: e0ad b.n 8004756 <UART_SetConfig+0x2e6>
80045fa: 2302 movs r3, #2
80045fc: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004600: e0a9 b.n 8004756 <UART_SetConfig+0x2e6>
8004602: 2304 movs r3, #4
8004604: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004608: e0a5 b.n 8004756 <UART_SetConfig+0x2e6>
800460a: 2308 movs r3, #8
800460c: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004610: e0a1 b.n 8004756 <UART_SetConfig+0x2e6>
8004612: 2310 movs r3, #16
8004614: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004618: e09d b.n 8004756 <UART_SetConfig+0x2e6>
800461a: 68fb ldr r3, [r7, #12]
800461c: 681b ldr r3, [r3, #0]
800461e: 4a4a ldr r2, [pc, #296] @ (8004748 <UART_SetConfig+0x2d8>)
8004620: 4293 cmp r3, r2
8004622: d125 bne.n 8004670 <UART_SetConfig+0x200>
8004624: 4b45 ldr r3, [pc, #276] @ (800473c <UART_SetConfig+0x2cc>)
8004626: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800462a: f003 03c0 and.w r3, r3, #192 @ 0xc0
800462e: 2bc0 cmp r3, #192 @ 0xc0
8004630: d016 beq.n 8004660 <UART_SetConfig+0x1f0>
8004632: 2bc0 cmp r3, #192 @ 0xc0
8004634: d818 bhi.n 8004668 <UART_SetConfig+0x1f8>
8004636: 2b80 cmp r3, #128 @ 0x80
8004638: d00a beq.n 8004650 <UART_SetConfig+0x1e0>
800463a: 2b80 cmp r3, #128 @ 0x80
800463c: d814 bhi.n 8004668 <UART_SetConfig+0x1f8>
800463e: 2b00 cmp r3, #0
8004640: d002 beq.n 8004648 <UART_SetConfig+0x1d8>
8004642: 2b40 cmp r3, #64 @ 0x40
8004644: d008 beq.n 8004658 <UART_SetConfig+0x1e8>
8004646: e00f b.n 8004668 <UART_SetConfig+0x1f8>
8004648: 2300 movs r3, #0
800464a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800464e: e082 b.n 8004756 <UART_SetConfig+0x2e6>
8004650: 2302 movs r3, #2
8004652: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004656: e07e b.n 8004756 <UART_SetConfig+0x2e6>
8004658: 2304 movs r3, #4
800465a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800465e: e07a b.n 8004756 <UART_SetConfig+0x2e6>
8004660: 2308 movs r3, #8
8004662: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004666: e076 b.n 8004756 <UART_SetConfig+0x2e6>
8004668: 2310 movs r3, #16
800466a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800466e: e072 b.n 8004756 <UART_SetConfig+0x2e6>
8004670: 68fb ldr r3, [r7, #12]
8004672: 681b ldr r3, [r3, #0]
8004674: 4a35 ldr r2, [pc, #212] @ (800474c <UART_SetConfig+0x2dc>)
8004676: 4293 cmp r3, r2
8004678: d12a bne.n 80046d0 <UART_SetConfig+0x260>
800467a: 4b30 ldr r3, [pc, #192] @ (800473c <UART_SetConfig+0x2cc>)
800467c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004680: f403 7340 and.w r3, r3, #768 @ 0x300
8004684: f5b3 7f40 cmp.w r3, #768 @ 0x300
8004688: d01a beq.n 80046c0 <UART_SetConfig+0x250>
800468a: f5b3 7f40 cmp.w r3, #768 @ 0x300
800468e: d81b bhi.n 80046c8 <UART_SetConfig+0x258>
8004690: f5b3 7f00 cmp.w r3, #512 @ 0x200
8004694: d00c beq.n 80046b0 <UART_SetConfig+0x240>
8004696: f5b3 7f00 cmp.w r3, #512 @ 0x200
800469a: d815 bhi.n 80046c8 <UART_SetConfig+0x258>
800469c: 2b00 cmp r3, #0
800469e: d003 beq.n 80046a8 <UART_SetConfig+0x238>
80046a0: f5b3 7f80 cmp.w r3, #256 @ 0x100
80046a4: d008 beq.n 80046b8 <UART_SetConfig+0x248>
80046a6: e00f b.n 80046c8 <UART_SetConfig+0x258>
80046a8: 2300 movs r3, #0
80046aa: f887 3023 strb.w r3, [r7, #35] @ 0x23
80046ae: e052 b.n 8004756 <UART_SetConfig+0x2e6>
80046b0: 2302 movs r3, #2
80046b2: f887 3023 strb.w r3, [r7, #35] @ 0x23
80046b6: e04e b.n 8004756 <UART_SetConfig+0x2e6>
80046b8: 2304 movs r3, #4
80046ba: f887 3023 strb.w r3, [r7, #35] @ 0x23
80046be: e04a b.n 8004756 <UART_SetConfig+0x2e6>
80046c0: 2308 movs r3, #8
80046c2: f887 3023 strb.w r3, [r7, #35] @ 0x23
80046c6: e046 b.n 8004756 <UART_SetConfig+0x2e6>
80046c8: 2310 movs r3, #16
80046ca: f887 3023 strb.w r3, [r7, #35] @ 0x23
80046ce: e042 b.n 8004756 <UART_SetConfig+0x2e6>
80046d0: 68fb ldr r3, [r7, #12]
80046d2: 681b ldr r3, [r3, #0]
80046d4: 4a17 ldr r2, [pc, #92] @ (8004734 <UART_SetConfig+0x2c4>)
80046d6: 4293 cmp r3, r2
80046d8: d13a bne.n 8004750 <UART_SetConfig+0x2e0>
80046da: 4b18 ldr r3, [pc, #96] @ (800473c <UART_SetConfig+0x2cc>)
80046dc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80046e0: f403 6340 and.w r3, r3, #3072 @ 0xc00
80046e4: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80046e8: d01a beq.n 8004720 <UART_SetConfig+0x2b0>
80046ea: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80046ee: d81b bhi.n 8004728 <UART_SetConfig+0x2b8>
80046f0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80046f4: d00c beq.n 8004710 <UART_SetConfig+0x2a0>
80046f6: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80046fa: d815 bhi.n 8004728 <UART_SetConfig+0x2b8>
80046fc: 2b00 cmp r3, #0
80046fe: d003 beq.n 8004708 <UART_SetConfig+0x298>
8004700: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8004704: d008 beq.n 8004718 <UART_SetConfig+0x2a8>
8004706: e00f b.n 8004728 <UART_SetConfig+0x2b8>
8004708: 2300 movs r3, #0
800470a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800470e: e022 b.n 8004756 <UART_SetConfig+0x2e6>
8004710: 2302 movs r3, #2
8004712: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004716: e01e b.n 8004756 <UART_SetConfig+0x2e6>
8004718: 2304 movs r3, #4
800471a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800471e: e01a b.n 8004756 <UART_SetConfig+0x2e6>
8004720: 2308 movs r3, #8
8004722: f887 3023 strb.w r3, [r7, #35] @ 0x23
8004726: e016 b.n 8004756 <UART_SetConfig+0x2e6>
8004728: 2310 movs r3, #16
800472a: f887 3023 strb.w r3, [r7, #35] @ 0x23
800472e: e012 b.n 8004756 <UART_SetConfig+0x2e6>
8004730: efff69f3 .word 0xefff69f3
8004734: 40008000 .word 0x40008000
8004738: 40013800 .word 0x40013800
800473c: 40021000 .word 0x40021000
8004740: 40004400 .word 0x40004400
8004744: 40004800 .word 0x40004800
8004748: 40004c00 .word 0x40004c00
800474c: 40005000 .word 0x40005000
8004750: 2310 movs r3, #16
8004752: f887 3023 strb.w r3, [r7, #35] @ 0x23
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
8004756: 68fb ldr r3, [r7, #12]
8004758: 681b ldr r3, [r3, #0]
800475a: 4a9f ldr r2, [pc, #636] @ (80049d8 <UART_SetConfig+0x568>)
800475c: 4293 cmp r3, r2
800475e: d17a bne.n 8004856 <UART_SetConfig+0x3e6>
{
/* Retrieve frequency clock */
switch (clocksource)
8004760: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
8004764: 2b08 cmp r3, #8
8004766: d824 bhi.n 80047b2 <UART_SetConfig+0x342>
8004768: a201 add r2, pc, #4 @ (adr r2, 8004770 <UART_SetConfig+0x300>)
800476a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800476e: bf00 nop
8004770: 08004795 .word 0x08004795
8004774: 080047b3 .word 0x080047b3
8004778: 0800479d .word 0x0800479d
800477c: 080047b3 .word 0x080047b3
8004780: 080047a3 .word 0x080047a3
8004784: 080047b3 .word 0x080047b3
8004788: 080047b3 .word 0x080047b3
800478c: 080047b3 .word 0x080047b3
8004790: 080047ab .word 0x080047ab
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004794: f7fe fa3a bl 8002c0c <HAL_RCC_GetPCLK1Freq>
8004798: 61f8 str r0, [r7, #28]
break;
800479a: e010 b.n 80047be <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
800479c: 4b8f ldr r3, [pc, #572] @ (80049dc <UART_SetConfig+0x56c>)
800479e: 61fb str r3, [r7, #28]
break;
80047a0: e00d b.n 80047be <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80047a2: f7fe f99b bl 8002adc <HAL_RCC_GetSysClockFreq>
80047a6: 61f8 str r0, [r7, #28]
break;
80047a8: e009 b.n 80047be <UART_SetConfig+0x34e>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80047aa: f44f 4300 mov.w r3, #32768 @ 0x8000
80047ae: 61fb str r3, [r7, #28]
break;
80047b0: e005 b.n 80047be <UART_SetConfig+0x34e>
default:
pclk = 0U;
80047b2: 2300 movs r3, #0
80047b4: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
80047b6: 2301 movs r3, #1
80047b8: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
80047bc: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
80047be: 69fb ldr r3, [r7, #28]
80047c0: 2b00 cmp r3, #0
80047c2: f000 80fb beq.w 80049bc <UART_SetConfig+0x54c>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
#else
/* No Prescaler applicable */
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((pclk < (3U * huart->Init.BaudRate)) ||
80047c6: 68fb ldr r3, [r7, #12]
80047c8: 685a ldr r2, [r3, #4]
80047ca: 4613 mov r3, r2
80047cc: 005b lsls r3, r3, #1
80047ce: 4413 add r3, r2
80047d0: 69fa ldr r2, [r7, #28]
80047d2: 429a cmp r2, r3
80047d4: d305 bcc.n 80047e2 <UART_SetConfig+0x372>
(pclk > (4096U * huart->Init.BaudRate)))
80047d6: 68fb ldr r3, [r7, #12]
80047d8: 685b ldr r3, [r3, #4]
80047da: 031b lsls r3, r3, #12
if ((pclk < (3U * huart->Init.BaudRate)) ||
80047dc: 69fa ldr r2, [r7, #28]
80047de: 429a cmp r2, r3
80047e0: d903 bls.n 80047ea <UART_SetConfig+0x37a>
{
ret = HAL_ERROR;
80047e2: 2301 movs r3, #1
80047e4: f887 3022 strb.w r3, [r7, #34] @ 0x22
80047e8: e0e8 b.n 80049bc <UART_SetConfig+0x54c>
}
else
{
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
80047ea: 69fb ldr r3, [r7, #28]
80047ec: 2200 movs r2, #0
80047ee: 461c mov r4, r3
80047f0: 4615 mov r5, r2
80047f2: f04f 0200 mov.w r2, #0
80047f6: f04f 0300 mov.w r3, #0
80047fa: 022b lsls r3, r5, #8
80047fc: ea43 6314 orr.w r3, r3, r4, lsr #24
8004800: 0222 lsls r2, r4, #8
8004802: 68f9 ldr r1, [r7, #12]
8004804: 6849 ldr r1, [r1, #4]
8004806: 0849 lsrs r1, r1, #1
8004808: 2000 movs r0, #0
800480a: 4688 mov r8, r1
800480c: 4681 mov r9, r0
800480e: eb12 0a08 adds.w sl, r2, r8
8004812: eb43 0b09 adc.w fp, r3, r9
8004816: 68fb ldr r3, [r7, #12]
8004818: 685b ldr r3, [r3, #4]
800481a: 2200 movs r2, #0
800481c: 603b str r3, [r7, #0]
800481e: 607a str r2, [r7, #4]
8004820: e9d7 2300 ldrd r2, r3, [r7]
8004824: 4650 mov r0, sl
8004826: 4659 mov r1, fp
8004828: f7fb fcce bl 80001c8 <__aeabi_uldivmod>
800482c: 4602 mov r2, r0
800482e: 460b mov r3, r1
8004830: 4613 mov r3, r2
8004832: 61bb str r3, [r7, #24]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
8004834: 69bb ldr r3, [r7, #24]
8004836: f5b3 7f40 cmp.w r3, #768 @ 0x300
800483a: d308 bcc.n 800484e <UART_SetConfig+0x3de>
800483c: 69bb ldr r3, [r7, #24]
800483e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8004842: d204 bcs.n 800484e <UART_SetConfig+0x3de>
{
huart->Instance->BRR = usartdiv;
8004844: 68fb ldr r3, [r7, #12]
8004846: 681b ldr r3, [r3, #0]
8004848: 69ba ldr r2, [r7, #24]
800484a: 60da str r2, [r3, #12]
800484c: e0b6 b.n 80049bc <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
800484e: 2301 movs r3, #1
8004850: f887 3022 strb.w r3, [r7, #34] @ 0x22
8004854: e0b2 b.n 80049bc <UART_SetConfig+0x54c>
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
#endif /* USART_PRESC_PRESCALER */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004856: 68fb ldr r3, [r7, #12]
8004858: 69db ldr r3, [r3, #28]
800485a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800485e: d15e bne.n 800491e <UART_SetConfig+0x4ae>
{
switch (clocksource)
8004860: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
8004864: 2b08 cmp r3, #8
8004866: d828 bhi.n 80048ba <UART_SetConfig+0x44a>
8004868: a201 add r2, pc, #4 @ (adr r2, 8004870 <UART_SetConfig+0x400>)
800486a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800486e: bf00 nop
8004870: 08004895 .word 0x08004895
8004874: 0800489d .word 0x0800489d
8004878: 080048a5 .word 0x080048a5
800487c: 080048bb .word 0x080048bb
8004880: 080048ab .word 0x080048ab
8004884: 080048bb .word 0x080048bb
8004888: 080048bb .word 0x080048bb
800488c: 080048bb .word 0x080048bb
8004890: 080048b3 .word 0x080048b3
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004894: f7fe f9ba bl 8002c0c <HAL_RCC_GetPCLK1Freq>
8004898: 61f8 str r0, [r7, #28]
break;
800489a: e014 b.n 80048c6 <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
800489c: f7fe f9cc bl 8002c38 <HAL_RCC_GetPCLK2Freq>
80048a0: 61f8 str r0, [r7, #28]
break;
80048a2: e010 b.n 80048c6 <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80048a4: 4b4d ldr r3, [pc, #308] @ (80049dc <UART_SetConfig+0x56c>)
80048a6: 61fb str r3, [r7, #28]
break;
80048a8: e00d b.n 80048c6 <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80048aa: f7fe f917 bl 8002adc <HAL_RCC_GetSysClockFreq>
80048ae: 61f8 str r0, [r7, #28]
break;
80048b0: e009 b.n 80048c6 <UART_SetConfig+0x456>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80048b2: f44f 4300 mov.w r3, #32768 @ 0x8000
80048b6: 61fb str r3, [r7, #28]
break;
80048b8: e005 b.n 80048c6 <UART_SetConfig+0x456>
default:
pclk = 0U;
80048ba: 2300 movs r3, #0
80048bc: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
80048be: 2301 movs r3, #1
80048c0: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
80048c4: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
80048c6: 69fb ldr r3, [r7, #28]
80048c8: 2b00 cmp r3, #0
80048ca: d077 beq.n 80049bc <UART_SetConfig+0x54c>
{
#if defined(USART_PRESC_PRESCALER)
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
80048cc: 69fb ldr r3, [r7, #28]
80048ce: 005a lsls r2, r3, #1
80048d0: 68fb ldr r3, [r7, #12]
80048d2: 685b ldr r3, [r3, #4]
80048d4: 085b lsrs r3, r3, #1
80048d6: 441a add r2, r3
80048d8: 68fb ldr r3, [r7, #12]
80048da: 685b ldr r3, [r3, #4]
80048dc: fbb2 f3f3 udiv r3, r2, r3
80048e0: 61bb str r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80048e2: 69bb ldr r3, [r7, #24]
80048e4: 2b0f cmp r3, #15
80048e6: d916 bls.n 8004916 <UART_SetConfig+0x4a6>
80048e8: 69bb ldr r3, [r7, #24]
80048ea: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80048ee: d212 bcs.n 8004916 <UART_SetConfig+0x4a6>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
80048f0: 69bb ldr r3, [r7, #24]
80048f2: b29b uxth r3, r3
80048f4: f023 030f bic.w r3, r3, #15
80048f8: 82fb strh r3, [r7, #22]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
80048fa: 69bb ldr r3, [r7, #24]
80048fc: 085b lsrs r3, r3, #1
80048fe: b29b uxth r3, r3
8004900: f003 0307 and.w r3, r3, #7
8004904: b29a uxth r2, r3
8004906: 8afb ldrh r3, [r7, #22]
8004908: 4313 orrs r3, r2
800490a: 82fb strh r3, [r7, #22]
huart->Instance->BRR = brrtemp;
800490c: 68fb ldr r3, [r7, #12]
800490e: 681b ldr r3, [r3, #0]
8004910: 8afa ldrh r2, [r7, #22]
8004912: 60da str r2, [r3, #12]
8004914: e052 b.n 80049bc <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
8004916: 2301 movs r3, #1
8004918: f887 3022 strb.w r3, [r7, #34] @ 0x22
800491c: e04e b.n 80049bc <UART_SetConfig+0x54c>
}
}
}
else
{
switch (clocksource)
800491e: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
8004922: 2b08 cmp r3, #8
8004924: d827 bhi.n 8004976 <UART_SetConfig+0x506>
8004926: a201 add r2, pc, #4 @ (adr r2, 800492c <UART_SetConfig+0x4bc>)
8004928: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800492c: 08004951 .word 0x08004951
8004930: 08004959 .word 0x08004959
8004934: 08004961 .word 0x08004961
8004938: 08004977 .word 0x08004977
800493c: 08004967 .word 0x08004967
8004940: 08004977 .word 0x08004977
8004944: 08004977 .word 0x08004977
8004948: 08004977 .word 0x08004977
800494c: 0800496f .word 0x0800496f
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004950: f7fe f95c bl 8002c0c <HAL_RCC_GetPCLK1Freq>
8004954: 61f8 str r0, [r7, #28]
break;
8004956: e014 b.n 8004982 <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8004958: f7fe f96e bl 8002c38 <HAL_RCC_GetPCLK2Freq>
800495c: 61f8 str r0, [r7, #28]
break;
800495e: e010 b.n 8004982 <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8004960: 4b1e ldr r3, [pc, #120] @ (80049dc <UART_SetConfig+0x56c>)
8004962: 61fb str r3, [r7, #28]
break;
8004964: e00d b.n 8004982 <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8004966: f7fe f8b9 bl 8002adc <HAL_RCC_GetSysClockFreq>
800496a: 61f8 str r0, [r7, #28]
break;
800496c: e009 b.n 8004982 <UART_SetConfig+0x512>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
800496e: f44f 4300 mov.w r3, #32768 @ 0x8000
8004972: 61fb str r3, [r7, #28]
break;
8004974: e005 b.n 8004982 <UART_SetConfig+0x512>
default:
pclk = 0U;
8004976: 2300 movs r3, #0
8004978: 61fb str r3, [r7, #28]
ret = HAL_ERROR;
800497a: 2301 movs r3, #1
800497c: f887 3022 strb.w r3, [r7, #34] @ 0x22
break;
8004980: bf00 nop
}
if (pclk != 0U)
8004982: 69fb ldr r3, [r7, #28]
8004984: 2b00 cmp r3, #0
8004986: d019 beq.n 80049bc <UART_SetConfig+0x54c>
{
/* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
8004988: 68fb ldr r3, [r7, #12]
800498a: 685b ldr r3, [r3, #4]
800498c: 085a lsrs r2, r3, #1
800498e: 69fb ldr r3, [r7, #28]
8004990: 441a add r2, r3
8004992: 68fb ldr r3, [r7, #12]
8004994: 685b ldr r3, [r3, #4]
8004996: fbb2 f3f3 udiv r3, r2, r3
800499a: 61bb str r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800499c: 69bb ldr r3, [r7, #24]
800499e: 2b0f cmp r3, #15
80049a0: d909 bls.n 80049b6 <UART_SetConfig+0x546>
80049a2: 69bb ldr r3, [r7, #24]
80049a4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80049a8: d205 bcs.n 80049b6 <UART_SetConfig+0x546>
{
huart->Instance->BRR = (uint16_t)usartdiv;
80049aa: 69bb ldr r3, [r7, #24]
80049ac: b29a uxth r2, r3
80049ae: 68fb ldr r3, [r7, #12]
80049b0: 681b ldr r3, [r3, #0]
80049b2: 60da str r2, [r3, #12]
80049b4: e002 b.n 80049bc <UART_SetConfig+0x54c>
}
else
{
ret = HAL_ERROR;
80049b6: 2301 movs r3, #1
80049b8: f887 3022 strb.w r3, [r7, #34] @ 0x22
huart->NbTxDataToProcess = 1;
huart->NbRxDataToProcess = 1;
#endif /* USART_CR1_FIFOEN */
/* Clear ISR function pointers */
huart->RxISR = NULL;
80049bc: 68fb ldr r3, [r7, #12]
80049be: 2200 movs r2, #0
80049c0: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
80049c2: 68fb ldr r3, [r7, #12]
80049c4: 2200 movs r2, #0
80049c6: 66da str r2, [r3, #108] @ 0x6c
return ret;
80049c8: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
}
80049cc: 4618 mov r0, r3
80049ce: 3728 adds r7, #40 @ 0x28
80049d0: 46bd mov sp, r7
80049d2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80049d6: bf00 nop
80049d8: 40008000 .word 0x40008000
80049dc: 00f42400 .word 0x00f42400
080049e0 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
80049e0: b480 push {r7}
80049e2: b083 sub sp, #12
80049e4: af00 add r7, sp, #0
80049e6: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80049e8: 687b ldr r3, [r7, #4]
80049ea: 6a5b ldr r3, [r3, #36] @ 0x24
80049ec: f003 0308 and.w r3, r3, #8
80049f0: 2b00 cmp r3, #0
80049f2: d00a beq.n 8004a0a <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
80049f4: 687b ldr r3, [r7, #4]
80049f6: 681b ldr r3, [r3, #0]
80049f8: 685b ldr r3, [r3, #4]
80049fa: f423 4100 bic.w r1, r3, #32768 @ 0x8000
80049fe: 687b ldr r3, [r7, #4]
8004a00: 6b5a ldr r2, [r3, #52] @ 0x34
8004a02: 687b ldr r3, [r7, #4]
8004a04: 681b ldr r3, [r3, #0]
8004a06: 430a orrs r2, r1
8004a08: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8004a0a: 687b ldr r3, [r7, #4]
8004a0c: 6a5b ldr r3, [r3, #36] @ 0x24
8004a0e: f003 0301 and.w r3, r3, #1
8004a12: 2b00 cmp r3, #0
8004a14: d00a beq.n 8004a2c <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8004a16: 687b ldr r3, [r7, #4]
8004a18: 681b ldr r3, [r3, #0]
8004a1a: 685b ldr r3, [r3, #4]
8004a1c: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8004a20: 687b ldr r3, [r7, #4]
8004a22: 6a9a ldr r2, [r3, #40] @ 0x28
8004a24: 687b ldr r3, [r7, #4]
8004a26: 681b ldr r3, [r3, #0]
8004a28: 430a orrs r2, r1
8004a2a: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8004a2c: 687b ldr r3, [r7, #4]
8004a2e: 6a5b ldr r3, [r3, #36] @ 0x24
8004a30: f003 0302 and.w r3, r3, #2
8004a34: 2b00 cmp r3, #0
8004a36: d00a beq.n 8004a4e <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8004a38: 687b ldr r3, [r7, #4]
8004a3a: 681b ldr r3, [r3, #0]
8004a3c: 685b ldr r3, [r3, #4]
8004a3e: f423 3180 bic.w r1, r3, #65536 @ 0x10000
8004a42: 687b ldr r3, [r7, #4]
8004a44: 6ada ldr r2, [r3, #44] @ 0x2c
8004a46: 687b ldr r3, [r7, #4]
8004a48: 681b ldr r3, [r3, #0]
8004a4a: 430a orrs r2, r1
8004a4c: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8004a4e: 687b ldr r3, [r7, #4]
8004a50: 6a5b ldr r3, [r3, #36] @ 0x24
8004a52: f003 0304 and.w r3, r3, #4
8004a56: 2b00 cmp r3, #0
8004a58: d00a beq.n 8004a70 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8004a5a: 687b ldr r3, [r7, #4]
8004a5c: 681b ldr r3, [r3, #0]
8004a5e: 685b ldr r3, [r3, #4]
8004a60: f423 2180 bic.w r1, r3, #262144 @ 0x40000
8004a64: 687b ldr r3, [r7, #4]
8004a66: 6b1a ldr r2, [r3, #48] @ 0x30
8004a68: 687b ldr r3, [r7, #4]
8004a6a: 681b ldr r3, [r3, #0]
8004a6c: 430a orrs r2, r1
8004a6e: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8004a70: 687b ldr r3, [r7, #4]
8004a72: 6a5b ldr r3, [r3, #36] @ 0x24
8004a74: f003 0310 and.w r3, r3, #16
8004a78: 2b00 cmp r3, #0
8004a7a: d00a beq.n 8004a92 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8004a7c: 687b ldr r3, [r7, #4]
8004a7e: 681b ldr r3, [r3, #0]
8004a80: 689b ldr r3, [r3, #8]
8004a82: f423 5180 bic.w r1, r3, #4096 @ 0x1000
8004a86: 687b ldr r3, [r7, #4]
8004a88: 6b9a ldr r2, [r3, #56] @ 0x38
8004a8a: 687b ldr r3, [r7, #4]
8004a8c: 681b ldr r3, [r3, #0]
8004a8e: 430a orrs r2, r1
8004a90: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8004a92: 687b ldr r3, [r7, #4]
8004a94: 6a5b ldr r3, [r3, #36] @ 0x24
8004a96: f003 0320 and.w r3, r3, #32
8004a9a: 2b00 cmp r3, #0
8004a9c: d00a beq.n 8004ab4 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8004a9e: 687b ldr r3, [r7, #4]
8004aa0: 681b ldr r3, [r3, #0]
8004aa2: 689b ldr r3, [r3, #8]
8004aa4: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8004aa8: 687b ldr r3, [r7, #4]
8004aaa: 6bda ldr r2, [r3, #60] @ 0x3c
8004aac: 687b ldr r3, [r7, #4]
8004aae: 681b ldr r3, [r3, #0]
8004ab0: 430a orrs r2, r1
8004ab2: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8004ab4: 687b ldr r3, [r7, #4]
8004ab6: 6a5b ldr r3, [r3, #36] @ 0x24
8004ab8: f003 0340 and.w r3, r3, #64 @ 0x40
8004abc: 2b00 cmp r3, #0
8004abe: d01a beq.n 8004af6 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8004ac0: 687b ldr r3, [r7, #4]
8004ac2: 681b ldr r3, [r3, #0]
8004ac4: 685b ldr r3, [r3, #4]
8004ac6: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
8004aca: 687b ldr r3, [r7, #4]
8004acc: 6c1a ldr r2, [r3, #64] @ 0x40
8004ace: 687b ldr r3, [r7, #4]
8004ad0: 681b ldr r3, [r3, #0]
8004ad2: 430a orrs r2, r1
8004ad4: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8004ad6: 687b ldr r3, [r7, #4]
8004ad8: 6c1b ldr r3, [r3, #64] @ 0x40
8004ada: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8004ade: d10a bne.n 8004af6 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8004ae0: 687b ldr r3, [r7, #4]
8004ae2: 681b ldr r3, [r3, #0]
8004ae4: 685b ldr r3, [r3, #4]
8004ae6: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8004aea: 687b ldr r3, [r7, #4]
8004aec: 6c5a ldr r2, [r3, #68] @ 0x44
8004aee: 687b ldr r3, [r7, #4]
8004af0: 681b ldr r3, [r3, #0]
8004af2: 430a orrs r2, r1
8004af4: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8004af6: 687b ldr r3, [r7, #4]
8004af8: 6a5b ldr r3, [r3, #36] @ 0x24
8004afa: f003 0380 and.w r3, r3, #128 @ 0x80
8004afe: 2b00 cmp r3, #0
8004b00: d00a beq.n 8004b18 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8004b02: 687b ldr r3, [r7, #4]
8004b04: 681b ldr r3, [r3, #0]
8004b06: 685b ldr r3, [r3, #4]
8004b08: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8004b0c: 687b ldr r3, [r7, #4]
8004b0e: 6c9a ldr r2, [r3, #72] @ 0x48
8004b10: 687b ldr r3, [r7, #4]
8004b12: 681b ldr r3, [r3, #0]
8004b14: 430a orrs r2, r1
8004b16: 605a str r2, [r3, #4]
}
}
8004b18: bf00 nop
8004b1a: 370c adds r7, #12
8004b1c: 46bd mov sp, r7
8004b1e: f85d 7b04 ldr.w r7, [sp], #4
8004b22: 4770 bx lr
08004b24 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8004b24: b580 push {r7, lr}
8004b26: b098 sub sp, #96 @ 0x60
8004b28: af02 add r7, sp, #8
8004b2a: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004b2c: 687b ldr r3, [r7, #4]
8004b2e: 2200 movs r2, #0
8004b30: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8004b34: f7fc f9ae bl 8000e94 <HAL_GetTick>
8004b38: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8004b3a: 687b ldr r3, [r7, #4]
8004b3c: 681b ldr r3, [r3, #0]
8004b3e: 681b ldr r3, [r3, #0]
8004b40: f003 0308 and.w r3, r3, #8
8004b44: 2b08 cmp r3, #8
8004b46: d12e bne.n 8004ba6 <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8004b48: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8004b4c: 9300 str r3, [sp, #0]
8004b4e: 6d7b ldr r3, [r7, #84] @ 0x54
8004b50: 2200 movs r2, #0
8004b52: f44f 1100 mov.w r1, #2097152 @ 0x200000
8004b56: 6878 ldr r0, [r7, #4]
8004b58: f000 f88c bl 8004c74 <UART_WaitOnFlagUntilTimeout>
8004b5c: 4603 mov r3, r0
8004b5e: 2b00 cmp r3, #0
8004b60: d021 beq.n 8004ba6 <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
8004b62: 687b ldr r3, [r7, #4]
8004b64: 681b ldr r3, [r3, #0]
8004b66: 63bb str r3, [r7, #56] @ 0x38
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004b68: 6bbb ldr r3, [r7, #56] @ 0x38
8004b6a: e853 3f00 ldrex r3, [r3]
8004b6e: 637b str r3, [r7, #52] @ 0x34
return(result);
8004b70: 6b7b ldr r3, [r7, #52] @ 0x34
8004b72: f023 0380 bic.w r3, r3, #128 @ 0x80
8004b76: 653b str r3, [r7, #80] @ 0x50
8004b78: 687b ldr r3, [r7, #4]
8004b7a: 681b ldr r3, [r3, #0]
8004b7c: 461a mov r2, r3
8004b7e: 6d3b ldr r3, [r7, #80] @ 0x50
8004b80: 647b str r3, [r7, #68] @ 0x44
8004b82: 643a str r2, [r7, #64] @ 0x40
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004b84: 6c39 ldr r1, [r7, #64] @ 0x40
8004b86: 6c7a ldr r2, [r7, #68] @ 0x44
8004b88: e841 2300 strex r3, r2, [r1]
8004b8c: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8004b8e: 6bfb ldr r3, [r7, #60] @ 0x3c
8004b90: 2b00 cmp r3, #0
8004b92: d1e6 bne.n 8004b62 <UART_CheckIdleState+0x3e>
#endif /* USART_CR1_FIFOEN */
huart->gState = HAL_UART_STATE_READY;
8004b94: 687b ldr r3, [r7, #4]
8004b96: 2220 movs r2, #32
8004b98: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
8004b9a: 687b ldr r3, [r7, #4]
8004b9c: 2200 movs r2, #0
8004b9e: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8004ba2: 2303 movs r3, #3
8004ba4: e062 b.n 8004c6c <UART_CheckIdleState+0x148>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8004ba6: 687b ldr r3, [r7, #4]
8004ba8: 681b ldr r3, [r3, #0]
8004baa: 681b ldr r3, [r3, #0]
8004bac: f003 0304 and.w r3, r3, #4
8004bb0: 2b04 cmp r3, #4
8004bb2: d149 bne.n 8004c48 <UART_CheckIdleState+0x124>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8004bb4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8004bb8: 9300 str r3, [sp, #0]
8004bba: 6d7b ldr r3, [r7, #84] @ 0x54
8004bbc: 2200 movs r2, #0
8004bbe: f44f 0180 mov.w r1, #4194304 @ 0x400000
8004bc2: 6878 ldr r0, [r7, #4]
8004bc4: f000 f856 bl 8004c74 <UART_WaitOnFlagUntilTimeout>
8004bc8: 4603 mov r3, r0
8004bca: 2b00 cmp r3, #0
8004bcc: d03c beq.n 8004c48 <UART_CheckIdleState+0x124>
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004bce: 687b ldr r3, [r7, #4]
8004bd0: 681b ldr r3, [r3, #0]
8004bd2: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004bd4: 6a7b ldr r3, [r7, #36] @ 0x24
8004bd6: e853 3f00 ldrex r3, [r3]
8004bda: 623b str r3, [r7, #32]
return(result);
8004bdc: 6a3b ldr r3, [r7, #32]
8004bde: f423 7390 bic.w r3, r3, #288 @ 0x120
8004be2: 64fb str r3, [r7, #76] @ 0x4c
8004be4: 687b ldr r3, [r7, #4]
8004be6: 681b ldr r3, [r3, #0]
8004be8: 461a mov r2, r3
8004bea: 6cfb ldr r3, [r7, #76] @ 0x4c
8004bec: 633b str r3, [r7, #48] @ 0x30
8004bee: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004bf0: 6af9 ldr r1, [r7, #44] @ 0x2c
8004bf2: 6b3a ldr r2, [r7, #48] @ 0x30
8004bf4: e841 2300 strex r3, r2, [r1]
8004bf8: 62bb str r3, [r7, #40] @ 0x28
return(result);
8004bfa: 6abb ldr r3, [r7, #40] @ 0x28
8004bfc: 2b00 cmp r3, #0
8004bfe: d1e6 bne.n 8004bce <UART_CheckIdleState+0xaa>
#endif /* USART_CR1_FIFOEN */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004c00: 687b ldr r3, [r7, #4]
8004c02: 681b ldr r3, [r3, #0]
8004c04: 3308 adds r3, #8
8004c06: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004c08: 693b ldr r3, [r7, #16]
8004c0a: e853 3f00 ldrex r3, [r3]
8004c0e: 60fb str r3, [r7, #12]
return(result);
8004c10: 68fb ldr r3, [r7, #12]
8004c12: f023 0301 bic.w r3, r3, #1
8004c16: 64bb str r3, [r7, #72] @ 0x48
8004c18: 687b ldr r3, [r7, #4]
8004c1a: 681b ldr r3, [r3, #0]
8004c1c: 3308 adds r3, #8
8004c1e: 6cba ldr r2, [r7, #72] @ 0x48
8004c20: 61fa str r2, [r7, #28]
8004c22: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004c24: 69b9 ldr r1, [r7, #24]
8004c26: 69fa ldr r2, [r7, #28]
8004c28: e841 2300 strex r3, r2, [r1]
8004c2c: 617b str r3, [r7, #20]
return(result);
8004c2e: 697b ldr r3, [r7, #20]
8004c30: 2b00 cmp r3, #0
8004c32: d1e5 bne.n 8004c00 <UART_CheckIdleState+0xdc>
huart->RxState = HAL_UART_STATE_READY;
8004c34: 687b ldr r3, [r7, #4]
8004c36: 2220 movs r2, #32
8004c38: f8c3 2080 str.w r2, [r3, #128] @ 0x80
__HAL_UNLOCK(huart);
8004c3c: 687b ldr r3, [r7, #4]
8004c3e: 2200 movs r2, #0
8004c40: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8004c44: 2303 movs r3, #3
8004c46: e011 b.n 8004c6c <UART_CheckIdleState+0x148>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8004c48: 687b ldr r3, [r7, #4]
8004c4a: 2220 movs r2, #32
8004c4c: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
8004c4e: 687b ldr r3, [r7, #4]
8004c50: 2220 movs r2, #32
8004c52: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004c56: 687b ldr r3, [r7, #4]
8004c58: 2200 movs r2, #0
8004c5a: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8004c5c: 687b ldr r3, [r7, #4]
8004c5e: 2200 movs r2, #0
8004c60: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
8004c62: 687b ldr r3, [r7, #4]
8004c64: 2200 movs r2, #0
8004c66: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
8004c6a: 2300 movs r3, #0
}
8004c6c: 4618 mov r0, r3
8004c6e: 3758 adds r7, #88 @ 0x58
8004c70: 46bd mov sp, r7
8004c72: bd80 pop {r7, pc}
08004c74 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8004c74: b580 push {r7, lr}
8004c76: b084 sub sp, #16
8004c78: af00 add r7, sp, #0
8004c7a: 60f8 str r0, [r7, #12]
8004c7c: 60b9 str r1, [r7, #8]
8004c7e: 603b str r3, [r7, #0]
8004c80: 4613 mov r3, r2
8004c82: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004c84: e04f b.n 8004d26 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004c86: 69bb ldr r3, [r7, #24]
8004c88: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8004c8c: d04b beq.n 8004d26 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004c8e: f7fc f901 bl 8000e94 <HAL_GetTick>
8004c92: 4602 mov r2, r0
8004c94: 683b ldr r3, [r7, #0]
8004c96: 1ad3 subs r3, r2, r3
8004c98: 69ba ldr r2, [r7, #24]
8004c9a: 429a cmp r2, r3
8004c9c: d302 bcc.n 8004ca4 <UART_WaitOnFlagUntilTimeout+0x30>
8004c9e: 69bb ldr r3, [r7, #24]
8004ca0: 2b00 cmp r3, #0
8004ca2: d101 bne.n 8004ca8 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8004ca4: 2303 movs r3, #3
8004ca6: e04e b.n 8004d46 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8004ca8: 68fb ldr r3, [r7, #12]
8004caa: 681b ldr r3, [r3, #0]
8004cac: 681b ldr r3, [r3, #0]
8004cae: f003 0304 and.w r3, r3, #4
8004cb2: 2b00 cmp r3, #0
8004cb4: d037 beq.n 8004d26 <UART_WaitOnFlagUntilTimeout+0xb2>
8004cb6: 68bb ldr r3, [r7, #8]
8004cb8: 2b80 cmp r3, #128 @ 0x80
8004cba: d034 beq.n 8004d26 <UART_WaitOnFlagUntilTimeout+0xb2>
8004cbc: 68bb ldr r3, [r7, #8]
8004cbe: 2b40 cmp r3, #64 @ 0x40
8004cc0: d031 beq.n 8004d26 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8004cc2: 68fb ldr r3, [r7, #12]
8004cc4: 681b ldr r3, [r3, #0]
8004cc6: 69db ldr r3, [r3, #28]
8004cc8: f003 0308 and.w r3, r3, #8
8004ccc: 2b08 cmp r3, #8
8004cce: d110 bne.n 8004cf2 <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8004cd0: 68fb ldr r3, [r7, #12]
8004cd2: 681b ldr r3, [r3, #0]
8004cd4: 2208 movs r2, #8
8004cd6: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8004cd8: 68f8 ldr r0, [r7, #12]
8004cda: f000 f838 bl 8004d4e <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8004cde: 68fb ldr r3, [r7, #12]
8004ce0: 2208 movs r2, #8
8004ce2: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004ce6: 68fb ldr r3, [r7, #12]
8004ce8: 2200 movs r2, #0
8004cea: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
8004cee: 2301 movs r3, #1
8004cf0: e029 b.n 8004d46 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8004cf2: 68fb ldr r3, [r7, #12]
8004cf4: 681b ldr r3, [r3, #0]
8004cf6: 69db ldr r3, [r3, #28]
8004cf8: f403 6300 and.w r3, r3, #2048 @ 0x800
8004cfc: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8004d00: d111 bne.n 8004d26 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8004d02: 68fb ldr r3, [r7, #12]
8004d04: 681b ldr r3, [r3, #0]
8004d06: f44f 6200 mov.w r2, #2048 @ 0x800
8004d0a: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8004d0c: 68f8 ldr r0, [r7, #12]
8004d0e: f000 f81e bl 8004d4e <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8004d12: 68fb ldr r3, [r7, #12]
8004d14: 2220 movs r2, #32
8004d16: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004d1a: 68fb ldr r3, [r7, #12]
8004d1c: 2200 movs r2, #0
8004d1e: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
8004d22: 2303 movs r3, #3
8004d24: e00f b.n 8004d46 <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004d26: 68fb ldr r3, [r7, #12]
8004d28: 681b ldr r3, [r3, #0]
8004d2a: 69da ldr r2, [r3, #28]
8004d2c: 68bb ldr r3, [r7, #8]
8004d2e: 4013 ands r3, r2
8004d30: 68ba ldr r2, [r7, #8]
8004d32: 429a cmp r2, r3
8004d34: bf0c ite eq
8004d36: 2301 moveq r3, #1
8004d38: 2300 movne r3, #0
8004d3a: b2db uxtb r3, r3
8004d3c: 461a mov r2, r3
8004d3e: 79fb ldrb r3, [r7, #7]
8004d40: 429a cmp r2, r3
8004d42: d0a0 beq.n 8004c86 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8004d44: 2300 movs r3, #0
}
8004d46: 4618 mov r0, r3
8004d48: 3710 adds r7, #16
8004d4a: 46bd mov sp, r7
8004d4c: bd80 pop {r7, pc}
08004d4e <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004d4e: b480 push {r7}
8004d50: b095 sub sp, #84 @ 0x54
8004d52: af00 add r7, sp, #0
8004d54: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004d56: 687b ldr r3, [r7, #4]
8004d58: 681b ldr r3, [r3, #0]
8004d5a: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004d5c: 6b7b ldr r3, [r7, #52] @ 0x34
8004d5e: e853 3f00 ldrex r3, [r3]
8004d62: 633b str r3, [r7, #48] @ 0x30
return(result);
8004d64: 6b3b ldr r3, [r7, #48] @ 0x30
8004d66: f423 7390 bic.w r3, r3, #288 @ 0x120
8004d6a: 64fb str r3, [r7, #76] @ 0x4c
8004d6c: 687b ldr r3, [r7, #4]
8004d6e: 681b ldr r3, [r3, #0]
8004d70: 461a mov r2, r3
8004d72: 6cfb ldr r3, [r7, #76] @ 0x4c
8004d74: 643b str r3, [r7, #64] @ 0x40
8004d76: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004d78: 6bf9 ldr r1, [r7, #60] @ 0x3c
8004d7a: 6c3a ldr r2, [r7, #64] @ 0x40
8004d7c: e841 2300 strex r3, r2, [r1]
8004d80: 63bb str r3, [r7, #56] @ 0x38
return(result);
8004d82: 6bbb ldr r3, [r7, #56] @ 0x38
8004d84: 2b00 cmp r3, #0
8004d86: d1e6 bne.n 8004d56 <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004d88: 687b ldr r3, [r7, #4]
8004d8a: 681b ldr r3, [r3, #0]
8004d8c: 3308 adds r3, #8
8004d8e: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004d90: 6a3b ldr r3, [r7, #32]
8004d92: e853 3f00 ldrex r3, [r3]
8004d96: 61fb str r3, [r7, #28]
return(result);
8004d98: 69fb ldr r3, [r7, #28]
8004d9a: f023 0301 bic.w r3, r3, #1
8004d9e: 64bb str r3, [r7, #72] @ 0x48
8004da0: 687b ldr r3, [r7, #4]
8004da2: 681b ldr r3, [r3, #0]
8004da4: 3308 adds r3, #8
8004da6: 6cba ldr r2, [r7, #72] @ 0x48
8004da8: 62fa str r2, [r7, #44] @ 0x2c
8004daa: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004dac: 6ab9 ldr r1, [r7, #40] @ 0x28
8004dae: 6afa ldr r2, [r7, #44] @ 0x2c
8004db0: e841 2300 strex r3, r2, [r1]
8004db4: 627b str r3, [r7, #36] @ 0x24
return(result);
8004db6: 6a7b ldr r3, [r7, #36] @ 0x24
8004db8: 2b00 cmp r3, #0
8004dba: d1e5 bne.n 8004d88 <UART_EndRxTransfer+0x3a>
#endif /* USART_CR1_FIFOEN */
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004dbc: 687b ldr r3, [r7, #4]
8004dbe: 6e1b ldr r3, [r3, #96] @ 0x60
8004dc0: 2b01 cmp r3, #1
8004dc2: d118 bne.n 8004df6 <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004dc4: 687b ldr r3, [r7, #4]
8004dc6: 681b ldr r3, [r3, #0]
8004dc8: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004dca: 68fb ldr r3, [r7, #12]
8004dcc: e853 3f00 ldrex r3, [r3]
8004dd0: 60bb str r3, [r7, #8]
return(result);
8004dd2: 68bb ldr r3, [r7, #8]
8004dd4: f023 0310 bic.w r3, r3, #16
8004dd8: 647b str r3, [r7, #68] @ 0x44
8004dda: 687b ldr r3, [r7, #4]
8004ddc: 681b ldr r3, [r3, #0]
8004dde: 461a mov r2, r3
8004de0: 6c7b ldr r3, [r7, #68] @ 0x44
8004de2: 61bb str r3, [r7, #24]
8004de4: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004de6: 6979 ldr r1, [r7, #20]
8004de8: 69ba ldr r2, [r7, #24]
8004dea: e841 2300 strex r3, r2, [r1]
8004dee: 613b str r3, [r7, #16]
return(result);
8004df0: 693b ldr r3, [r7, #16]
8004df2: 2b00 cmp r3, #0
8004df4: d1e6 bne.n 8004dc4 <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004df6: 687b ldr r3, [r7, #4]
8004df8: 2220 movs r2, #32
8004dfa: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004dfe: 687b ldr r3, [r7, #4]
8004e00: 2200 movs r2, #0
8004e02: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8004e04: 687b ldr r3, [r7, #4]
8004e06: 2200 movs r2, #0
8004e08: 669a str r2, [r3, #104] @ 0x68
}
8004e0a: bf00 nop
8004e0c: 3754 adds r7, #84 @ 0x54
8004e0e: 46bd mov sp, r7
8004e10: f85d 7b04 ldr.w r7, [sp], #4
8004e14: 4770 bx lr
08004e16 <memset>:
8004e16: 4402 add r2, r0
8004e18: 4603 mov r3, r0
8004e1a: 4293 cmp r3, r2
8004e1c: d100 bne.n 8004e20 <memset+0xa>
8004e1e: 4770 bx lr
8004e20: f803 1b01 strb.w r1, [r3], #1
8004e24: e7f9 b.n 8004e1a <memset+0x4>
...
08004e28 <__libc_init_array>:
8004e28: b570 push {r4, r5, r6, lr}
8004e2a: 4d0d ldr r5, [pc, #52] @ (8004e60 <__libc_init_array+0x38>)
8004e2c: 4c0d ldr r4, [pc, #52] @ (8004e64 <__libc_init_array+0x3c>)
8004e2e: 1b64 subs r4, r4, r5
8004e30: 10a4 asrs r4, r4, #2
8004e32: 2600 movs r6, #0
8004e34: 42a6 cmp r6, r4
8004e36: d109 bne.n 8004e4c <__libc_init_array+0x24>
8004e38: 4d0b ldr r5, [pc, #44] @ (8004e68 <__libc_init_array+0x40>)
8004e3a: 4c0c ldr r4, [pc, #48] @ (8004e6c <__libc_init_array+0x44>)
8004e3c: f000 f818 bl 8004e70 <_init>
8004e40: 1b64 subs r4, r4, r5
8004e42: 10a4 asrs r4, r4, #2
8004e44: 2600 movs r6, #0
8004e46: 42a6 cmp r6, r4
8004e48: d105 bne.n 8004e56 <__libc_init_array+0x2e>
8004e4a: bd70 pop {r4, r5, r6, pc}
8004e4c: f855 3b04 ldr.w r3, [r5], #4
8004e50: 4798 blx r3
8004e52: 3601 adds r6, #1
8004e54: e7ee b.n 8004e34 <__libc_init_array+0xc>
8004e56: f855 3b04 ldr.w r3, [r5], #4
8004e5a: 4798 blx r3
8004e5c: 3601 adds r6, #1
8004e5e: e7f2 b.n 8004e46 <__libc_init_array+0x1e>
8004e60: 08004ed8 .word 0x08004ed8
8004e64: 08004ed8 .word 0x08004ed8
8004e68: 08004ed8 .word 0x08004ed8
8004e6c: 08004edc .word 0x08004edc
08004e70 <_init>:
8004e70: b5f8 push {r3, r4, r5, r6, r7, lr}
8004e72: bf00 nop
8004e74: bcf8 pop {r3, r4, r5, r6, r7}
8004e76: bc08 pop {r3}
8004e78: 469e mov lr, r3
8004e7a: 4770 bx lr
08004e7c <_fini>:
8004e7c: b5f8 push {r3, r4, r5, r6, r7, lr}
8004e7e: bf00 nop
8004e80: bcf8 pop {r3, r4, r5, r6, r7}
8004e82: bc08 pop {r3}
8004e84: 469e mov lr, r3
8004e86: 4770 bx lr
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