Gallardo7761/setr1-monorepo
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85e60bcc395d54bac7c45fdfeb66aee5b9aa7fed
setr1-monorepo/P1_SETR1/Debug/SETR_P1.list
Jose 85e60bcc39 monorepo
2025-10-10 02:20:31 +02:00

3888 lines
146 KiB
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Executable File
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SETR_P1.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000014cc 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000002c 080015d8 080015d8 000025d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08001604 08001604 0000300c 2**0
CONTENTS
4 .ARM 00000000 08001604 08001604 0000300c 2**0
CONTENTS
5 .preinit_array 00000000 08001604 08001604 0000300c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08001604 08001604 00002604 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08001608 08001608 00002608 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 0800160c 00003000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000006c 2000000c 08001618 0000300c 2**2
ALLOC
10 ._user_heap_stack 00000600 20000078 08001618 00003078 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000300c 2**0
CONTENTS, READONLY
12 .debug_info 000065e4 00000000 00000000 00003035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000131c 00000000 00000000 00009619 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000600 00000000 00000000 0000a938 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000493 00000000 00000000 0000af38 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00015e0d 00000000 00000000 0000b3cb 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000734a 00000000 00000000 000211d8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0007e3dc 00000000 00000000 00028522 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000a68fe 2**0
CONTENTS, READONLY
20 .debug_frame 00001714 00000000 00000000 000a6944 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000004a 00000000 00000000 000a8058 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 2000000c .word 0x2000000c
8000128: 00000000 .word 0x00000000
800012c: 080015c0 .word 0x080015c0
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000010 .word 0x20000010
8000148: 080015c0 .word 0x080015c0
0800014c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800014c: b580 push {r7, lr}
800014e: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000150: f000 f9f8 bl 8000544 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000154: f000 f80a bl 800016c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000158: f000 f874 bl 8000244 <MX_GPIO_Init>
MX_USART2_UART_Init();
800015c: f000 f848 bl 80001f0 <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
HAL_SYSTICK_Config(0xffffff);
8000160: f06f 407f mvn.w r0, #4278190080 @ 0xff000000
8000164: f000 fb51 bl 800080a <HAL_SYSTICK_Config>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000168: bf00 nop
800016a: e7fd b.n 8000168 <main+0x1c>
0800016c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800016c: b580 push {r7, lr}
800016e: b090 sub sp, #64 @ 0x40
8000170: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000172: f107 0318 add.w r3, r7, #24
8000176: 2228 movs r2, #40 @ 0x28
8000178: 2100 movs r1, #0
800017a: 4618 mov r0, r3
800017c: f001 f9f4 bl 8001568 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000180: 1d3b adds r3, r7, #4
8000182: 2200 movs r2, #0
8000184: 601a str r2, [r3, #0]
8000186: 605a str r2, [r3, #4]
8000188: 609a str r2, [r3, #8]
800018a: 60da str r2, [r3, #12]
800018c: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800018e: 2302 movs r3, #2
8000190: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000192: 2301 movs r3, #1
8000194: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000196: 2310 movs r3, #16
8000198: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
800019a: 2302 movs r3, #2
800019c: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
800019e: 2300 movs r3, #0
80001a0: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
80001a2: f44f 1360 mov.w r3, #3670016 @ 0x380000
80001a6: 63fb str r3, [r7, #60] @ 0x3c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80001a8: f107 0318 add.w r3, r7, #24
80001ac: 4618 mov r0, r3
80001ae: f000 fced bl 8000b8c <HAL_RCC_OscConfig>
80001b2: 4603 mov r3, r0
80001b4: 2b00 cmp r3, #0
80001b6: d001 beq.n 80001bc <SystemClock_Config+0x50>
{
Error_Handler();
80001b8: f000 f8d4 bl 8000364 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80001bc: 230f movs r3, #15
80001be: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80001c0: 2302 movs r3, #2
80001c2: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV16;
80001c4: 23b0 movs r3, #176 @ 0xb0
80001c6: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
80001c8: f44f 6380 mov.w r3, #1024 @ 0x400
80001cc: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80001ce: 2300 movs r3, #0
80001d0: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
80001d2: 1d3b adds r3, r7, #4
80001d4: 2102 movs r1, #2
80001d6: 4618 mov r0, r3
80001d8: f000 ff5a bl 8001090 <HAL_RCC_ClockConfig>
80001dc: 4603 mov r3, r0
80001de: 2b00 cmp r3, #0
80001e0: d001 beq.n 80001e6 <SystemClock_Config+0x7a>
{
Error_Handler();
80001e2: f000 f8bf bl 8000364 <Error_Handler>
}
}
80001e6: bf00 nop
80001e8: 3740 adds r7, #64 @ 0x40
80001ea: 46bd mov sp, r7
80001ec: bd80 pop {r7, pc}
...
080001f0 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
80001f0: b580 push {r7, lr}
80001f2: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
80001f4: 4b11 ldr r3, [pc, #68] @ (800023c <MX_USART2_UART_Init+0x4c>)
80001f6: 4a12 ldr r2, [pc, #72] @ (8000240 <MX_USART2_UART_Init+0x50>)
80001f8: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
80001fa: 4b10 ldr r3, [pc, #64] @ (800023c <MX_USART2_UART_Init+0x4c>)
80001fc: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000200: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
8000202: 4b0e ldr r3, [pc, #56] @ (800023c <MX_USART2_UART_Init+0x4c>)
8000204: 2200 movs r2, #0
8000206: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8000208: 4b0c ldr r3, [pc, #48] @ (800023c <MX_USART2_UART_Init+0x4c>)
800020a: 2200 movs r2, #0
800020c: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
800020e: 4b0b ldr r3, [pc, #44] @ (800023c <MX_USART2_UART_Init+0x4c>)
8000210: 2200 movs r2, #0
8000212: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
8000214: 4b09 ldr r3, [pc, #36] @ (800023c <MX_USART2_UART_Init+0x4c>)
8000216: 220c movs r2, #12
8000218: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800021a: 4b08 ldr r3, [pc, #32] @ (800023c <MX_USART2_UART_Init+0x4c>)
800021c: 2200 movs r2, #0
800021e: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8000220: 4b06 ldr r3, [pc, #24] @ (800023c <MX_USART2_UART_Init+0x4c>)
8000222: 2200 movs r2, #0
8000224: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
8000226: 4805 ldr r0, [pc, #20] @ (800023c <MX_USART2_UART_Init+0x4c>)
8000228: f001 f8c0 bl 80013ac <HAL_UART_Init>
800022c: 4603 mov r3, r0
800022e: 2b00 cmp r3, #0
8000230: d001 beq.n 8000236 <MX_USART2_UART_Init+0x46>
{
Error_Handler();
8000232: f000 f897 bl 8000364 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
8000236: bf00 nop
8000238: bd80 pop {r7, pc}
800023a: bf00 nop
800023c: 20000028 .word 0x20000028
8000240: 40004400 .word 0x40004400
08000244 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000244: b580 push {r7, lr}
8000246: b088 sub sp, #32
8000248: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800024a: f107 0310 add.w r3, r7, #16
800024e: 2200 movs r2, #0
8000250: 601a str r2, [r3, #0]
8000252: 605a str r2, [r3, #4]
8000254: 609a str r2, [r3, #8]
8000256: 60da str r2, [r3, #12]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000258: 4b2d ldr r3, [pc, #180] @ (8000310 <MX_GPIO_Init+0xcc>)
800025a: 699b ldr r3, [r3, #24]
800025c: 4a2c ldr r2, [pc, #176] @ (8000310 <MX_GPIO_Init+0xcc>)
800025e: f043 0310 orr.w r3, r3, #16
8000262: 6193 str r3, [r2, #24]
8000264: 4b2a ldr r3, [pc, #168] @ (8000310 <MX_GPIO_Init+0xcc>)
8000266: 699b ldr r3, [r3, #24]
8000268: f003 0310 and.w r3, r3, #16
800026c: 60fb str r3, [r7, #12]
800026e: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000270: 4b27 ldr r3, [pc, #156] @ (8000310 <MX_GPIO_Init+0xcc>)
8000272: 699b ldr r3, [r3, #24]
8000274: 4a26 ldr r2, [pc, #152] @ (8000310 <MX_GPIO_Init+0xcc>)
8000276: f043 0320 orr.w r3, r3, #32
800027a: 6193 str r3, [r2, #24]
800027c: 4b24 ldr r3, [pc, #144] @ (8000310 <MX_GPIO_Init+0xcc>)
800027e: 699b ldr r3, [r3, #24]
8000280: f003 0320 and.w r3, r3, #32
8000284: 60bb str r3, [r7, #8]
8000286: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000288: 4b21 ldr r3, [pc, #132] @ (8000310 <MX_GPIO_Init+0xcc>)
800028a: 699b ldr r3, [r3, #24]
800028c: 4a20 ldr r2, [pc, #128] @ (8000310 <MX_GPIO_Init+0xcc>)
800028e: f043 0304 orr.w r3, r3, #4
8000292: 6193 str r3, [r2, #24]
8000294: 4b1e ldr r3, [pc, #120] @ (8000310 <MX_GPIO_Init+0xcc>)
8000296: 699b ldr r3, [r3, #24]
8000298: f003 0304 and.w r3, r3, #4
800029c: 607b str r3, [r7, #4]
800029e: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
80002a0: 4b1b ldr r3, [pc, #108] @ (8000310 <MX_GPIO_Init+0xcc>)
80002a2: 699b ldr r3, [r3, #24]
80002a4: 4a1a ldr r2, [pc, #104] @ (8000310 <MX_GPIO_Init+0xcc>)
80002a6: f043 0308 orr.w r3, r3, #8
80002aa: 6193 str r3, [r2, #24]
80002ac: 4b18 ldr r3, [pc, #96] @ (8000310 <MX_GPIO_Init+0xcc>)
80002ae: 699b ldr r3, [r3, #24]
80002b0: f003 0308 and.w r3, r3, #8
80002b4: 603b str r3, [r7, #0]
80002b6: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
80002b8: 2200 movs r2, #0
80002ba: 2120 movs r1, #32
80002bc: 4815 ldr r0, [pc, #84] @ (8000314 <MX_GPIO_Init+0xd0>)
80002be: f000 fc35 bl 8000b2c <HAL_GPIO_WritePin>
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
80002c2: f44f 5300 mov.w r3, #8192 @ 0x2000
80002c6: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
80002c8: 4b13 ldr r3, [pc, #76] @ (8000318 <MX_GPIO_Init+0xd4>)
80002ca: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80002cc: 2300 movs r3, #0
80002ce: 61bb str r3, [r7, #24]
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
80002d0: f107 0310 add.w r3, r7, #16
80002d4: 4619 mov r1, r3
80002d6: 4811 ldr r0, [pc, #68] @ (800031c <MX_GPIO_Init+0xd8>)
80002d8: f000 faa4 bl 8000824 <HAL_GPIO_Init>
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
80002dc: 2320 movs r3, #32
80002de: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80002e0: 2301 movs r3, #1
80002e2: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80002e4: 2300 movs r3, #0
80002e6: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80002e8: 2302 movs r3, #2
80002ea: 61fb str r3, [r7, #28]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
80002ec: f107 0310 add.w r3, r7, #16
80002f0: 4619 mov r1, r3
80002f2: 4808 ldr r0, [pc, #32] @ (8000314 <MX_GPIO_Init+0xd0>)
80002f4: f000 fa96 bl 8000824 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
80002f8: 2200 movs r2, #0
80002fa: 2100 movs r1, #0
80002fc: 2028 movs r0, #40 @ 0x28
80002fe: f000 fa5a bl 80007b6 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
8000302: 2028 movs r0, #40 @ 0x28
8000304: f000 fa73 bl 80007ee <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000308: bf00 nop
800030a: 3720 adds r7, #32
800030c: 46bd mov sp, r7
800030e: bd80 pop {r7, pc}
8000310: 40021000 .word 0x40021000
8000314: 40010800 .word 0x40010800
8000318: 10310000 .word 0x10310000
800031c: 40011000 .word 0x40011000
08000320 <HAL_GPIO_EXTI_Callback>:
/* USER CODE BEGIN 4 */
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8000320: b580 push {r7, lr}
8000322: b082 sub sp, #8
8000324: af00 add r7, sp, #0
8000326: 4603 mov r3, r0
8000328: 80fb strh r3, [r7, #6]
static char state = 0;if (state == 1){HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET);state = 0;}else{HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);state = 1;}
800032a: 4b0c ldr r3, [pc, #48] @ (800035c <HAL_GPIO_EXTI_Callback+0x3c>)
800032c: 781b ldrb r3, [r3, #0]
800032e: 2b01 cmp r3, #1
8000330: d108 bne.n 8000344 <HAL_GPIO_EXTI_Callback+0x24>
8000332: 2201 movs r2, #1
8000334: 2120 movs r1, #32
8000336: 480a ldr r0, [pc, #40] @ (8000360 <HAL_GPIO_EXTI_Callback+0x40>)
8000338: f000 fbf8 bl 8000b2c <HAL_GPIO_WritePin>
800033c: 4b07 ldr r3, [pc, #28] @ (800035c <HAL_GPIO_EXTI_Callback+0x3c>)
800033e: 2200 movs r2, #0
8000340: 701a strb r2, [r3, #0]
}
8000342: e007 b.n 8000354 <HAL_GPIO_EXTI_Callback+0x34>
static char state = 0;if (state == 1){HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET);state = 0;}else{HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);state = 1;}
8000344: 2200 movs r2, #0
8000346: 2120 movs r1, #32
8000348: 4805 ldr r0, [pc, #20] @ (8000360 <HAL_GPIO_EXTI_Callback+0x40>)
800034a: f000 fbef bl 8000b2c <HAL_GPIO_WritePin>
800034e: 4b03 ldr r3, [pc, #12] @ (800035c <HAL_GPIO_EXTI_Callback+0x3c>)
8000350: 2201 movs r2, #1
8000352: 701a strb r2, [r3, #0]
}
8000354: bf00 nop
8000356: 3708 adds r7, #8
8000358: 46bd mov sp, r7
800035a: bd80 pop {r7, pc}
800035c: 20000070 .word 0x20000070
8000360: 40010800 .word 0x40010800
08000364 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000364: b480 push {r7}
8000366: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000368: b672 cpsid i
}
800036a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800036c: bf00 nop
800036e: e7fd b.n 800036c <Error_Handler+0x8>
08000370 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000370: b480 push {r7}
8000372: b085 sub sp, #20
8000374: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8000376: 4b15 ldr r3, [pc, #84] @ (80003cc <HAL_MspInit+0x5c>)
8000378: 699b ldr r3, [r3, #24]
800037a: 4a14 ldr r2, [pc, #80] @ (80003cc <HAL_MspInit+0x5c>)
800037c: f043 0301 orr.w r3, r3, #1
8000380: 6193 str r3, [r2, #24]
8000382: 4b12 ldr r3, [pc, #72] @ (80003cc <HAL_MspInit+0x5c>)
8000384: 699b ldr r3, [r3, #24]
8000386: f003 0301 and.w r3, r3, #1
800038a: 60bb str r3, [r7, #8]
800038c: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
800038e: 4b0f ldr r3, [pc, #60] @ (80003cc <HAL_MspInit+0x5c>)
8000390: 69db ldr r3, [r3, #28]
8000392: 4a0e ldr r2, [pc, #56] @ (80003cc <HAL_MspInit+0x5c>)
8000394: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000398: 61d3 str r3, [r2, #28]
800039a: 4b0c ldr r3, [pc, #48] @ (80003cc <HAL_MspInit+0x5c>)
800039c: 69db ldr r3, [r3, #28]
800039e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80003a2: 607b str r3, [r7, #4]
80003a4: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
80003a6: 4b0a ldr r3, [pc, #40] @ (80003d0 <HAL_MspInit+0x60>)
80003a8: 685b ldr r3, [r3, #4]
80003aa: 60fb str r3, [r7, #12]
80003ac: 68fb ldr r3, [r7, #12]
80003ae: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
80003b2: 60fb str r3, [r7, #12]
80003b4: 68fb ldr r3, [r7, #12]
80003b6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
80003ba: 60fb str r3, [r7, #12]
80003bc: 4a04 ldr r2, [pc, #16] @ (80003d0 <HAL_MspInit+0x60>)
80003be: 68fb ldr r3, [r7, #12]
80003c0: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80003c2: bf00 nop
80003c4: 3714 adds r7, #20
80003c6: 46bd mov sp, r7
80003c8: bc80 pop {r7}
80003ca: 4770 bx lr
80003cc: 40021000 .word 0x40021000
80003d0: 40010000 .word 0x40010000
080003d4 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
80003d4: b580 push {r7, lr}
80003d6: b088 sub sp, #32
80003d8: af00 add r7, sp, #0
80003da: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80003dc: f107 0310 add.w r3, r7, #16
80003e0: 2200 movs r2, #0
80003e2: 601a str r2, [r3, #0]
80003e4: 605a str r2, [r3, #4]
80003e6: 609a str r2, [r3, #8]
80003e8: 60da str r2, [r3, #12]
if(huart->Instance==USART2)
80003ea: 687b ldr r3, [r7, #4]
80003ec: 681b ldr r3, [r3, #0]
80003ee: 4a15 ldr r2, [pc, #84] @ (8000444 <HAL_UART_MspInit+0x70>)
80003f0: 4293 cmp r3, r2
80003f2: d123 bne.n 800043c <HAL_UART_MspInit+0x68>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
80003f4: 4b14 ldr r3, [pc, #80] @ (8000448 <HAL_UART_MspInit+0x74>)
80003f6: 69db ldr r3, [r3, #28]
80003f8: 4a13 ldr r2, [pc, #76] @ (8000448 <HAL_UART_MspInit+0x74>)
80003fa: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80003fe: 61d3 str r3, [r2, #28]
8000400: 4b11 ldr r3, [pc, #68] @ (8000448 <HAL_UART_MspInit+0x74>)
8000402: 69db ldr r3, [r3, #28]
8000404: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000408: 60fb str r3, [r7, #12]
800040a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800040c: 4b0e ldr r3, [pc, #56] @ (8000448 <HAL_UART_MspInit+0x74>)
800040e: 699b ldr r3, [r3, #24]
8000410: 4a0d ldr r2, [pc, #52] @ (8000448 <HAL_UART_MspInit+0x74>)
8000412: f043 0304 orr.w r3, r3, #4
8000416: 6193 str r3, [r2, #24]
8000418: 4b0b ldr r3, [pc, #44] @ (8000448 <HAL_UART_MspInit+0x74>)
800041a: 699b ldr r3, [r3, #24]
800041c: f003 0304 and.w r3, r3, #4
8000420: 60bb str r3, [r7, #8]
8000422: 68bb ldr r3, [r7, #8]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
8000424: 230c movs r3, #12
8000426: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000428: 2302 movs r3, #2
800042a: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800042c: 2302 movs r3, #2
800042e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000430: f107 0310 add.w r3, r7, #16
8000434: 4619 mov r1, r3
8000436: 4805 ldr r0, [pc, #20] @ (800044c <HAL_UART_MspInit+0x78>)
8000438: f000 f9f4 bl 8000824 <HAL_GPIO_Init>
/* USER CODE END USART2_MspInit 1 */
}
}
800043c: bf00 nop
800043e: 3720 adds r7, #32
8000440: 46bd mov sp, r7
8000442: bd80 pop {r7, pc}
8000444: 40004400 .word 0x40004400
8000448: 40021000 .word 0x40021000
800044c: 40010800 .word 0x40010800
08000450 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000450: b480 push {r7}
8000452: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000454: bf00 nop
8000456: e7fd b.n 8000454 <NMI_Handler+0x4>
08000458 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000458: b480 push {r7}
800045a: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800045c: bf00 nop
800045e: e7fd b.n 800045c <HardFault_Handler+0x4>
08000460 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000460: b480 push {r7}
8000462: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000464: bf00 nop
8000466: e7fd b.n 8000464 <MemManage_Handler+0x4>
08000468 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000468: b480 push {r7}
800046a: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800046c: bf00 nop
800046e: e7fd b.n 800046c <BusFault_Handler+0x4>
08000470 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000470: b480 push {r7}
8000472: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000474: bf00 nop
8000476: e7fd b.n 8000474 <UsageFault_Handler+0x4>
08000478 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000478: b480 push {r7}
800047a: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800047c: bf00 nop
800047e: 46bd mov sp, r7
8000480: bc80 pop {r7}
8000482: 4770 bx lr
08000484 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000484: b480 push {r7}
8000486: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000488: bf00 nop
800048a: 46bd mov sp, r7
800048c: bc80 pop {r7}
800048e: 4770 bx lr
08000490 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000490: b480 push {r7}
8000492: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000494: bf00 nop
8000496: 46bd mov sp, r7
8000498: bc80 pop {r7}
800049a: 4770 bx lr
0800049c <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
800049c: b580 push {r7, lr}
800049e: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
static char state = 0;if (state == 1){HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET);state = 0;}else{HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);state = 1;}
80004a0: 4b0c ldr r3, [pc, #48] @ (80004d4 <SysTick_Handler+0x38>)
80004a2: 781b ldrb r3, [r3, #0]
80004a4: 2b01 cmp r3, #1
80004a6: d108 bne.n 80004ba <SysTick_Handler+0x1e>
80004a8: 2201 movs r2, #1
80004aa: 2120 movs r1, #32
80004ac: 480a ldr r0, [pc, #40] @ (80004d8 <SysTick_Handler+0x3c>)
80004ae: f000 fb3d bl 8000b2c <HAL_GPIO_WritePin>
80004b2: 4b08 ldr r3, [pc, #32] @ (80004d4 <SysTick_Handler+0x38>)
80004b4: 2200 movs r2, #0
80004b6: 701a strb r2, [r3, #0]
80004b8: e007 b.n 80004ca <SysTick_Handler+0x2e>
80004ba: 2200 movs r2, #0
80004bc: 2120 movs r1, #32
80004be: 4806 ldr r0, [pc, #24] @ (80004d8 <SysTick_Handler+0x3c>)
80004c0: f000 fb34 bl 8000b2c <HAL_GPIO_WritePin>
80004c4: 4b03 ldr r3, [pc, #12] @ (80004d4 <SysTick_Handler+0x38>)
80004c6: 2201 movs r2, #1
80004c8: 701a strb r2, [r3, #0]
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80004ca: f000 f881 bl 80005d0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80004ce: bf00 nop
80004d0: bd80 pop {r7, pc}
80004d2: bf00 nop
80004d4: 20000071 .word 0x20000071
80004d8: 40010800 .word 0x40010800
080004dc <EXTI15_10_IRQHandler>:
/**
* @brief This function handles EXTI line[15:10] interrupts.
*/
void EXTI15_10_IRQHandler(void)
{
80004dc: b580 push {r7, lr}
80004de: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(B1_Pin);
80004e0: f44f 5000 mov.w r0, #8192 @ 0x2000
80004e4: f000 fb3a bl 8000b5c <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 1 */
}
80004e8: bf00 nop
80004ea: bd80 pop {r7, pc}
080004ec <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
80004ec: b480 push {r7}
80004ee: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80004f0: bf00 nop
80004f2: 46bd mov sp, r7
80004f4: bc80 pop {r7}
80004f6: 4770 bx lr
080004f8 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
80004f8: f7ff fff8 bl 80004ec <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80004fc: 480b ldr r0, [pc, #44] @ (800052c <LoopFillZerobss+0xe>)
ldr r1, =_edata
80004fe: 490c ldr r1, [pc, #48] @ (8000530 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8000500: 4a0c ldr r2, [pc, #48] @ (8000534 <LoopFillZerobss+0x16>)
movs r3, #0
8000502: 2300 movs r3, #0
b LoopCopyDataInit
8000504: e002 b.n 800050c <LoopCopyDataInit>
08000506 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000506: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000508: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800050a: 3304 adds r3, #4
0800050c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800050c: 18c4 adds r4, r0, r3
cmp r4, r1
800050e: 428c cmp r4, r1
bcc CopyDataInit
8000510: d3f9 bcc.n 8000506 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000512: 4a09 ldr r2, [pc, #36] @ (8000538 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8000514: 4c09 ldr r4, [pc, #36] @ (800053c <LoopFillZerobss+0x1e>)
movs r3, #0
8000516: 2300 movs r3, #0
b LoopFillZerobss
8000518: e001 b.n 800051e <LoopFillZerobss>
0800051a <FillZerobss>:
FillZerobss:
str r3, [r2]
800051a: 6013 str r3, [r2, #0]
adds r2, r2, #4
800051c: 3204 adds r2, #4
0800051e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800051e: 42a2 cmp r2, r4
bcc FillZerobss
8000520: d3fb bcc.n 800051a <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000522: f001 f829 bl 8001578 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000526: f7ff fe11 bl 800014c <main>
bx lr
800052a: 4770 bx lr
ldr r0, =_sdata
800052c: 20000000 .word 0x20000000
ldr r1, =_edata
8000530: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000534: 0800160c .word 0x0800160c
ldr r2, =_sbss
8000538: 2000000c .word 0x2000000c
ldr r4, =_ebss
800053c: 20000078 .word 0x20000078
08000540 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000540: e7fe b.n 8000540 <ADC1_2_IRQHandler>
...
08000544 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000544: b580 push {r7, lr}
8000546: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000548: 4b08 ldr r3, [pc, #32] @ (800056c <HAL_Init+0x28>)
800054a: 681b ldr r3, [r3, #0]
800054c: 4a07 ldr r2, [pc, #28] @ (800056c <HAL_Init+0x28>)
800054e: f043 0310 orr.w r3, r3, #16
8000552: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000554: 2003 movs r0, #3
8000556: f000 f923 bl 80007a0 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
800055a: 2000 movs r0, #0
800055c: f000 f808 bl 8000570 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000560: f7ff ff06 bl 8000370 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000564: 2300 movs r3, #0
}
8000566: 4618 mov r0, r3
8000568: bd80 pop {r7, pc}
800056a: bf00 nop
800056c: 40022000 .word 0x40022000
08000570 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000570: b580 push {r7, lr}
8000572: b082 sub sp, #8
8000574: af00 add r7, sp, #0
8000576: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000578: 4b12 ldr r3, [pc, #72] @ (80005c4 <HAL_InitTick+0x54>)
800057a: 681a ldr r2, [r3, #0]
800057c: 4b12 ldr r3, [pc, #72] @ (80005c8 <HAL_InitTick+0x58>)
800057e: 781b ldrb r3, [r3, #0]
8000580: 4619 mov r1, r3
8000582: f44f 737a mov.w r3, #1000 @ 0x3e8
8000586: fbb3 f3f1 udiv r3, r3, r1
800058a: fbb2 f3f3 udiv r3, r2, r3
800058e: 4618 mov r0, r3
8000590: f000 f93b bl 800080a <HAL_SYSTICK_Config>
8000594: 4603 mov r3, r0
8000596: 2b00 cmp r3, #0
8000598: d001 beq.n 800059e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800059a: 2301 movs r3, #1
800059c: e00e b.n 80005bc <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800059e: 687b ldr r3, [r7, #4]
80005a0: 2b0f cmp r3, #15
80005a2: d80a bhi.n 80005ba <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80005a4: 2200 movs r2, #0
80005a6: 6879 ldr r1, [r7, #4]
80005a8: f04f 30ff mov.w r0, #4294967295
80005ac: f000 f903 bl 80007b6 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80005b0: 4a06 ldr r2, [pc, #24] @ (80005cc <HAL_InitTick+0x5c>)
80005b2: 687b ldr r3, [r7, #4]
80005b4: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80005b6: 2300 movs r3, #0
80005b8: e000 b.n 80005bc <HAL_InitTick+0x4c>
return HAL_ERROR;
80005ba: 2301 movs r3, #1
}
80005bc: 4618 mov r0, r3
80005be: 3708 adds r7, #8
80005c0: 46bd mov sp, r7
80005c2: bd80 pop {r7, pc}
80005c4: 20000000 .word 0x20000000
80005c8: 20000008 .word 0x20000008
80005cc: 20000004 .word 0x20000004
080005d0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80005d0: b480 push {r7}
80005d2: af00 add r7, sp, #0
uwTick += uwTickFreq;
80005d4: 4b05 ldr r3, [pc, #20] @ (80005ec <HAL_IncTick+0x1c>)
80005d6: 781b ldrb r3, [r3, #0]
80005d8: 461a mov r2, r3
80005da: 4b05 ldr r3, [pc, #20] @ (80005f0 <HAL_IncTick+0x20>)
80005dc: 681b ldr r3, [r3, #0]
80005de: 4413 add r3, r2
80005e0: 4a03 ldr r2, [pc, #12] @ (80005f0 <HAL_IncTick+0x20>)
80005e2: 6013 str r3, [r2, #0]
}
80005e4: bf00 nop
80005e6: 46bd mov sp, r7
80005e8: bc80 pop {r7}
80005ea: 4770 bx lr
80005ec: 20000008 .word 0x20000008
80005f0: 20000074 .word 0x20000074
080005f4 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80005f4: b480 push {r7}
80005f6: af00 add r7, sp, #0
return uwTick;
80005f8: 4b02 ldr r3, [pc, #8] @ (8000604 <HAL_GetTick+0x10>)
80005fa: 681b ldr r3, [r3, #0]
}
80005fc: 4618 mov r0, r3
80005fe: 46bd mov sp, r7
8000600: bc80 pop {r7}
8000602: 4770 bx lr
8000604: 20000074 .word 0x20000074
08000608 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000608: b480 push {r7}
800060a: b085 sub sp, #20
800060c: af00 add r7, sp, #0
800060e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000610: 687b ldr r3, [r7, #4]
8000612: f003 0307 and.w r3, r3, #7
8000616: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000618: 4b0c ldr r3, [pc, #48] @ (800064c <__NVIC_SetPriorityGrouping+0x44>)
800061a: 68db ldr r3, [r3, #12]
800061c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800061e: 68ba ldr r2, [r7, #8]
8000620: f64f 03ff movw r3, #63743 @ 0xf8ff
8000624: 4013 ands r3, r2
8000626: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000628: 68fb ldr r3, [r7, #12]
800062a: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
800062c: 68bb ldr r3, [r7, #8]
800062e: 4313 orrs r3, r2
reg_value = (reg_value |
8000630: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8000634: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000638: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800063a: 4a04 ldr r2, [pc, #16] @ (800064c <__NVIC_SetPriorityGrouping+0x44>)
800063c: 68bb ldr r3, [r7, #8]
800063e: 60d3 str r3, [r2, #12]
}
8000640: bf00 nop
8000642: 3714 adds r7, #20
8000644: 46bd mov sp, r7
8000646: bc80 pop {r7}
8000648: 4770 bx lr
800064a: bf00 nop
800064c: e000ed00 .word 0xe000ed00
08000650 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000650: b480 push {r7}
8000652: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000654: 4b04 ldr r3, [pc, #16] @ (8000668 <__NVIC_GetPriorityGrouping+0x18>)
8000656: 68db ldr r3, [r3, #12]
8000658: 0a1b lsrs r3, r3, #8
800065a: f003 0307 and.w r3, r3, #7
}
800065e: 4618 mov r0, r3
8000660: 46bd mov sp, r7
8000662: bc80 pop {r7}
8000664: 4770 bx lr
8000666: bf00 nop
8000668: e000ed00 .word 0xe000ed00
0800066c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
800066c: b480 push {r7}
800066e: b083 sub sp, #12
8000670: af00 add r7, sp, #0
8000672: 4603 mov r3, r0
8000674: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000676: f997 3007 ldrsb.w r3, [r7, #7]
800067a: 2b00 cmp r3, #0
800067c: db0b blt.n 8000696 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800067e: 79fb ldrb r3, [r7, #7]
8000680: f003 021f and.w r2, r3, #31
8000684: 4906 ldr r1, [pc, #24] @ (80006a0 <__NVIC_EnableIRQ+0x34>)
8000686: f997 3007 ldrsb.w r3, [r7, #7]
800068a: 095b lsrs r3, r3, #5
800068c: 2001 movs r0, #1
800068e: fa00 f202 lsl.w r2, r0, r2
8000692: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8000696: bf00 nop
8000698: 370c adds r7, #12
800069a: 46bd mov sp, r7
800069c: bc80 pop {r7}
800069e: 4770 bx lr
80006a0: e000e100 .word 0xe000e100
080006a4 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80006a4: b480 push {r7}
80006a6: b083 sub sp, #12
80006a8: af00 add r7, sp, #0
80006aa: 4603 mov r3, r0
80006ac: 6039 str r1, [r7, #0]
80006ae: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80006b0: f997 3007 ldrsb.w r3, [r7, #7]
80006b4: 2b00 cmp r3, #0
80006b6: db0a blt.n 80006ce <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80006b8: 683b ldr r3, [r7, #0]
80006ba: b2da uxtb r2, r3
80006bc: 490c ldr r1, [pc, #48] @ (80006f0 <__NVIC_SetPriority+0x4c>)
80006be: f997 3007 ldrsb.w r3, [r7, #7]
80006c2: 0112 lsls r2, r2, #4
80006c4: b2d2 uxtb r2, r2
80006c6: 440b add r3, r1
80006c8: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80006cc: e00a b.n 80006e4 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80006ce: 683b ldr r3, [r7, #0]
80006d0: b2da uxtb r2, r3
80006d2: 4908 ldr r1, [pc, #32] @ (80006f4 <__NVIC_SetPriority+0x50>)
80006d4: 79fb ldrb r3, [r7, #7]
80006d6: f003 030f and.w r3, r3, #15
80006da: 3b04 subs r3, #4
80006dc: 0112 lsls r2, r2, #4
80006de: b2d2 uxtb r2, r2
80006e0: 440b add r3, r1
80006e2: 761a strb r2, [r3, #24]
}
80006e4: bf00 nop
80006e6: 370c adds r7, #12
80006e8: 46bd mov sp, r7
80006ea: bc80 pop {r7}
80006ec: 4770 bx lr
80006ee: bf00 nop
80006f0: e000e100 .word 0xe000e100
80006f4: e000ed00 .word 0xe000ed00
080006f8 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80006f8: b480 push {r7}
80006fa: b089 sub sp, #36 @ 0x24
80006fc: af00 add r7, sp, #0
80006fe: 60f8 str r0, [r7, #12]
8000700: 60b9 str r1, [r7, #8]
8000702: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000704: 68fb ldr r3, [r7, #12]
8000706: f003 0307 and.w r3, r3, #7
800070a: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
800070c: 69fb ldr r3, [r7, #28]
800070e: f1c3 0307 rsb r3, r3, #7
8000712: 2b04 cmp r3, #4
8000714: bf28 it cs
8000716: 2304 movcs r3, #4
8000718: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800071a: 69fb ldr r3, [r7, #28]
800071c: 3304 adds r3, #4
800071e: 2b06 cmp r3, #6
8000720: d902 bls.n 8000728 <NVIC_EncodePriority+0x30>
8000722: 69fb ldr r3, [r7, #28]
8000724: 3b03 subs r3, #3
8000726: e000 b.n 800072a <NVIC_EncodePriority+0x32>
8000728: 2300 movs r3, #0
800072a: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800072c: f04f 32ff mov.w r2, #4294967295
8000730: 69bb ldr r3, [r7, #24]
8000732: fa02 f303 lsl.w r3, r2, r3
8000736: 43da mvns r2, r3
8000738: 68bb ldr r3, [r7, #8]
800073a: 401a ands r2, r3
800073c: 697b ldr r3, [r7, #20]
800073e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000740: f04f 31ff mov.w r1, #4294967295
8000744: 697b ldr r3, [r7, #20]
8000746: fa01 f303 lsl.w r3, r1, r3
800074a: 43d9 mvns r1, r3
800074c: 687b ldr r3, [r7, #4]
800074e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000750: 4313 orrs r3, r2
);
}
8000752: 4618 mov r0, r3
8000754: 3724 adds r7, #36 @ 0x24
8000756: 46bd mov sp, r7
8000758: bc80 pop {r7}
800075a: 4770 bx lr
0800075c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
800075c: b580 push {r7, lr}
800075e: b082 sub sp, #8
8000760: af00 add r7, sp, #0
8000762: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000764: 687b ldr r3, [r7, #4]
8000766: 3b01 subs r3, #1
8000768: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
800076c: d301 bcc.n 8000772 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800076e: 2301 movs r3, #1
8000770: e00f b.n 8000792 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000772: 4a0a ldr r2, [pc, #40] @ (800079c <SysTick_Config+0x40>)
8000774: 687b ldr r3, [r7, #4]
8000776: 3b01 subs r3, #1
8000778: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800077a: 210f movs r1, #15
800077c: f04f 30ff mov.w r0, #4294967295
8000780: f7ff ff90 bl 80006a4 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000784: 4b05 ldr r3, [pc, #20] @ (800079c <SysTick_Config+0x40>)
8000786: 2200 movs r2, #0
8000788: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800078a: 4b04 ldr r3, [pc, #16] @ (800079c <SysTick_Config+0x40>)
800078c: 2207 movs r2, #7
800078e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000790: 2300 movs r3, #0
}
8000792: 4618 mov r0, r3
8000794: 3708 adds r7, #8
8000796: 46bd mov sp, r7
8000798: bd80 pop {r7, pc}
800079a: bf00 nop
800079c: e000e010 .word 0xe000e010
080007a0 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80007a0: b580 push {r7, lr}
80007a2: b082 sub sp, #8
80007a4: af00 add r7, sp, #0
80007a6: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
80007a8: 6878 ldr r0, [r7, #4]
80007aa: f7ff ff2d bl 8000608 <__NVIC_SetPriorityGrouping>
}
80007ae: bf00 nop
80007b0: 3708 adds r7, #8
80007b2: 46bd mov sp, r7
80007b4: bd80 pop {r7, pc}
080007b6 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80007b6: b580 push {r7, lr}
80007b8: b086 sub sp, #24
80007ba: af00 add r7, sp, #0
80007bc: 4603 mov r3, r0
80007be: 60b9 str r1, [r7, #8]
80007c0: 607a str r2, [r7, #4]
80007c2: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80007c4: 2300 movs r3, #0
80007c6: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80007c8: f7ff ff42 bl 8000650 <__NVIC_GetPriorityGrouping>
80007cc: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80007ce: 687a ldr r2, [r7, #4]
80007d0: 68b9 ldr r1, [r7, #8]
80007d2: 6978 ldr r0, [r7, #20]
80007d4: f7ff ff90 bl 80006f8 <NVIC_EncodePriority>
80007d8: 4602 mov r2, r0
80007da: f997 300f ldrsb.w r3, [r7, #15]
80007de: 4611 mov r1, r2
80007e0: 4618 mov r0, r3
80007e2: f7ff ff5f bl 80006a4 <__NVIC_SetPriority>
}
80007e6: bf00 nop
80007e8: 3718 adds r7, #24
80007ea: 46bd mov sp, r7
80007ec: bd80 pop {r7, pc}
080007ee <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80007ee: b580 push {r7, lr}
80007f0: b082 sub sp, #8
80007f2: af00 add r7, sp, #0
80007f4: 4603 mov r3, r0
80007f6: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80007f8: f997 3007 ldrsb.w r3, [r7, #7]
80007fc: 4618 mov r0, r3
80007fe: f7ff ff35 bl 800066c <__NVIC_EnableIRQ>
}
8000802: bf00 nop
8000804: 3708 adds r7, #8
8000806: 46bd mov sp, r7
8000808: bd80 pop {r7, pc}
0800080a <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800080a: b580 push {r7, lr}
800080c: b082 sub sp, #8
800080e: af00 add r7, sp, #0
8000810: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000812: 6878 ldr r0, [r7, #4]
8000814: f7ff ffa2 bl 800075c <SysTick_Config>
8000818: 4603 mov r3, r0
}
800081a: 4618 mov r0, r3
800081c: 3708 adds r7, #8
800081e: 46bd mov sp, r7
8000820: bd80 pop {r7, pc}
...
08000824 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000824: b480 push {r7}
8000826: b08b sub sp, #44 @ 0x2c
8000828: af00 add r7, sp, #0
800082a: 6078 str r0, [r7, #4]
800082c: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
800082e: 2300 movs r3, #0
8000830: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
8000832: 2300 movs r3, #0
8000834: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000836: e169 b.n 8000b0c <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8000838: 2201 movs r2, #1
800083a: 6a7b ldr r3, [r7, #36] @ 0x24
800083c: fa02 f303 lsl.w r3, r2, r3
8000840: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8000842: 683b ldr r3, [r7, #0]
8000844: 681b ldr r3, [r3, #0]
8000846: 69fa ldr r2, [r7, #28]
8000848: 4013 ands r3, r2
800084a: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
800084c: 69ba ldr r2, [r7, #24]
800084e: 69fb ldr r3, [r7, #28]
8000850: 429a cmp r2, r3
8000852: f040 8158 bne.w 8000b06 <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
8000856: 683b ldr r3, [r7, #0]
8000858: 685b ldr r3, [r3, #4]
800085a: 4a9a ldr r2, [pc, #616] @ (8000ac4 <HAL_GPIO_Init+0x2a0>)
800085c: 4293 cmp r3, r2
800085e: d05e beq.n 800091e <HAL_GPIO_Init+0xfa>
8000860: 4a98 ldr r2, [pc, #608] @ (8000ac4 <HAL_GPIO_Init+0x2a0>)
8000862: 4293 cmp r3, r2
8000864: d875 bhi.n 8000952 <HAL_GPIO_Init+0x12e>
8000866: 4a98 ldr r2, [pc, #608] @ (8000ac8 <HAL_GPIO_Init+0x2a4>)
8000868: 4293 cmp r3, r2
800086a: d058 beq.n 800091e <HAL_GPIO_Init+0xfa>
800086c: 4a96 ldr r2, [pc, #600] @ (8000ac8 <HAL_GPIO_Init+0x2a4>)
800086e: 4293 cmp r3, r2
8000870: d86f bhi.n 8000952 <HAL_GPIO_Init+0x12e>
8000872: 4a96 ldr r2, [pc, #600] @ (8000acc <HAL_GPIO_Init+0x2a8>)
8000874: 4293 cmp r3, r2
8000876: d052 beq.n 800091e <HAL_GPIO_Init+0xfa>
8000878: 4a94 ldr r2, [pc, #592] @ (8000acc <HAL_GPIO_Init+0x2a8>)
800087a: 4293 cmp r3, r2
800087c: d869 bhi.n 8000952 <HAL_GPIO_Init+0x12e>
800087e: 4a94 ldr r2, [pc, #592] @ (8000ad0 <HAL_GPIO_Init+0x2ac>)
8000880: 4293 cmp r3, r2
8000882: d04c beq.n 800091e <HAL_GPIO_Init+0xfa>
8000884: 4a92 ldr r2, [pc, #584] @ (8000ad0 <HAL_GPIO_Init+0x2ac>)
8000886: 4293 cmp r3, r2
8000888: d863 bhi.n 8000952 <HAL_GPIO_Init+0x12e>
800088a: 4a92 ldr r2, [pc, #584] @ (8000ad4 <HAL_GPIO_Init+0x2b0>)
800088c: 4293 cmp r3, r2
800088e: d046 beq.n 800091e <HAL_GPIO_Init+0xfa>
8000890: 4a90 ldr r2, [pc, #576] @ (8000ad4 <HAL_GPIO_Init+0x2b0>)
8000892: 4293 cmp r3, r2
8000894: d85d bhi.n 8000952 <HAL_GPIO_Init+0x12e>
8000896: 2b12 cmp r3, #18
8000898: d82a bhi.n 80008f0 <HAL_GPIO_Init+0xcc>
800089a: 2b12 cmp r3, #18
800089c: d859 bhi.n 8000952 <HAL_GPIO_Init+0x12e>
800089e: a201 add r2, pc, #4 @ (adr r2, 80008a4 <HAL_GPIO_Init+0x80>)
80008a0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80008a4: 0800091f .word 0x0800091f
80008a8: 080008f9 .word 0x080008f9
80008ac: 0800090b .word 0x0800090b
80008b0: 0800094d .word 0x0800094d
80008b4: 08000953 .word 0x08000953
80008b8: 08000953 .word 0x08000953
80008bc: 08000953 .word 0x08000953
80008c0: 08000953 .word 0x08000953
80008c4: 08000953 .word 0x08000953
80008c8: 08000953 .word 0x08000953
80008cc: 08000953 .word 0x08000953
80008d0: 08000953 .word 0x08000953
80008d4: 08000953 .word 0x08000953
80008d8: 08000953 .word 0x08000953
80008dc: 08000953 .word 0x08000953
80008e0: 08000953 .word 0x08000953
80008e4: 08000953 .word 0x08000953
80008e8: 08000901 .word 0x08000901
80008ec: 08000915 .word 0x08000915
80008f0: 4a79 ldr r2, [pc, #484] @ (8000ad8 <HAL_GPIO_Init+0x2b4>)
80008f2: 4293 cmp r3, r2
80008f4: d013 beq.n 800091e <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
80008f6: e02c b.n 8000952 <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
80008f8: 683b ldr r3, [r7, #0]
80008fa: 68db ldr r3, [r3, #12]
80008fc: 623b str r3, [r7, #32]
break;
80008fe: e029 b.n 8000954 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8000900: 683b ldr r3, [r7, #0]
8000902: 68db ldr r3, [r3, #12]
8000904: 3304 adds r3, #4
8000906: 623b str r3, [r7, #32]
break;
8000908: e024 b.n 8000954 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
800090a: 683b ldr r3, [r7, #0]
800090c: 68db ldr r3, [r3, #12]
800090e: 3308 adds r3, #8
8000910: 623b str r3, [r7, #32]
break;
8000912: e01f b.n 8000954 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8000914: 683b ldr r3, [r7, #0]
8000916: 68db ldr r3, [r3, #12]
8000918: 330c adds r3, #12
800091a: 623b str r3, [r7, #32]
break;
800091c: e01a b.n 8000954 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
800091e: 683b ldr r3, [r7, #0]
8000920: 689b ldr r3, [r3, #8]
8000922: 2b00 cmp r3, #0
8000924: d102 bne.n 800092c <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
8000926: 2304 movs r3, #4
8000928: 623b str r3, [r7, #32]
break;
800092a: e013 b.n 8000954 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
800092c: 683b ldr r3, [r7, #0]
800092e: 689b ldr r3, [r3, #8]
8000930: 2b01 cmp r3, #1
8000932: d105 bne.n 8000940 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000934: 2308 movs r3, #8
8000936: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8000938: 687b ldr r3, [r7, #4]
800093a: 69fa ldr r2, [r7, #28]
800093c: 611a str r2, [r3, #16]
break;
800093e: e009 b.n 8000954 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000940: 2308 movs r3, #8
8000942: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
8000944: 687b ldr r3, [r7, #4]
8000946: 69fa ldr r2, [r7, #28]
8000948: 615a str r2, [r3, #20]
break;
800094a: e003 b.n 8000954 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
800094c: 2300 movs r3, #0
800094e: 623b str r3, [r7, #32]
break;
8000950: e000 b.n 8000954 <HAL_GPIO_Init+0x130>
break;
8000952: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
8000954: 69bb ldr r3, [r7, #24]
8000956: 2bff cmp r3, #255 @ 0xff
8000958: d801 bhi.n 800095e <HAL_GPIO_Init+0x13a>
800095a: 687b ldr r3, [r7, #4]
800095c: e001 b.n 8000962 <HAL_GPIO_Init+0x13e>
800095e: 687b ldr r3, [r7, #4]
8000960: 3304 adds r3, #4
8000962: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
8000964: 69bb ldr r3, [r7, #24]
8000966: 2bff cmp r3, #255 @ 0xff
8000968: d802 bhi.n 8000970 <HAL_GPIO_Init+0x14c>
800096a: 6a7b ldr r3, [r7, #36] @ 0x24
800096c: 009b lsls r3, r3, #2
800096e: e002 b.n 8000976 <HAL_GPIO_Init+0x152>
8000970: 6a7b ldr r3, [r7, #36] @ 0x24
8000972: 3b08 subs r3, #8
8000974: 009b lsls r3, r3, #2
8000976: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
8000978: 697b ldr r3, [r7, #20]
800097a: 681a ldr r2, [r3, #0]
800097c: 210f movs r1, #15
800097e: 693b ldr r3, [r7, #16]
8000980: fa01 f303 lsl.w r3, r1, r3
8000984: 43db mvns r3, r3
8000986: 401a ands r2, r3
8000988: 6a39 ldr r1, [r7, #32]
800098a: 693b ldr r3, [r7, #16]
800098c: fa01 f303 lsl.w r3, r1, r3
8000990: 431a orrs r2, r3
8000992: 697b ldr r3, [r7, #20]
8000994: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8000996: 683b ldr r3, [r7, #0]
8000998: 685b ldr r3, [r3, #4]
800099a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800099e: 2b00 cmp r3, #0
80009a0: f000 80b1 beq.w 8000b06 <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
80009a4: 4b4d ldr r3, [pc, #308] @ (8000adc <HAL_GPIO_Init+0x2b8>)
80009a6: 699b ldr r3, [r3, #24]
80009a8: 4a4c ldr r2, [pc, #304] @ (8000adc <HAL_GPIO_Init+0x2b8>)
80009aa: f043 0301 orr.w r3, r3, #1
80009ae: 6193 str r3, [r2, #24]
80009b0: 4b4a ldr r3, [pc, #296] @ (8000adc <HAL_GPIO_Init+0x2b8>)
80009b2: 699b ldr r3, [r3, #24]
80009b4: f003 0301 and.w r3, r3, #1
80009b8: 60bb str r3, [r7, #8]
80009ba: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
80009bc: 4a48 ldr r2, [pc, #288] @ (8000ae0 <HAL_GPIO_Init+0x2bc>)
80009be: 6a7b ldr r3, [r7, #36] @ 0x24
80009c0: 089b lsrs r3, r3, #2
80009c2: 3302 adds r3, #2
80009c4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80009c8: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
80009ca: 6a7b ldr r3, [r7, #36] @ 0x24
80009cc: f003 0303 and.w r3, r3, #3
80009d0: 009b lsls r3, r3, #2
80009d2: 220f movs r2, #15
80009d4: fa02 f303 lsl.w r3, r2, r3
80009d8: 43db mvns r3, r3
80009da: 68fa ldr r2, [r7, #12]
80009dc: 4013 ands r3, r2
80009de: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
80009e0: 687b ldr r3, [r7, #4]
80009e2: 4a40 ldr r2, [pc, #256] @ (8000ae4 <HAL_GPIO_Init+0x2c0>)
80009e4: 4293 cmp r3, r2
80009e6: d013 beq.n 8000a10 <HAL_GPIO_Init+0x1ec>
80009e8: 687b ldr r3, [r7, #4]
80009ea: 4a3f ldr r2, [pc, #252] @ (8000ae8 <HAL_GPIO_Init+0x2c4>)
80009ec: 4293 cmp r3, r2
80009ee: d00d beq.n 8000a0c <HAL_GPIO_Init+0x1e8>
80009f0: 687b ldr r3, [r7, #4]
80009f2: 4a3e ldr r2, [pc, #248] @ (8000aec <HAL_GPIO_Init+0x2c8>)
80009f4: 4293 cmp r3, r2
80009f6: d007 beq.n 8000a08 <HAL_GPIO_Init+0x1e4>
80009f8: 687b ldr r3, [r7, #4]
80009fa: 4a3d ldr r2, [pc, #244] @ (8000af0 <HAL_GPIO_Init+0x2cc>)
80009fc: 4293 cmp r3, r2
80009fe: d101 bne.n 8000a04 <HAL_GPIO_Init+0x1e0>
8000a00: 2303 movs r3, #3
8000a02: e006 b.n 8000a12 <HAL_GPIO_Init+0x1ee>
8000a04: 2304 movs r3, #4
8000a06: e004 b.n 8000a12 <HAL_GPIO_Init+0x1ee>
8000a08: 2302 movs r3, #2
8000a0a: e002 b.n 8000a12 <HAL_GPIO_Init+0x1ee>
8000a0c: 2301 movs r3, #1
8000a0e: e000 b.n 8000a12 <HAL_GPIO_Init+0x1ee>
8000a10: 2300 movs r3, #0
8000a12: 6a7a ldr r2, [r7, #36] @ 0x24
8000a14: f002 0203 and.w r2, r2, #3
8000a18: 0092 lsls r2, r2, #2
8000a1a: 4093 lsls r3, r2
8000a1c: 68fa ldr r2, [r7, #12]
8000a1e: 4313 orrs r3, r2
8000a20: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8000a22: 492f ldr r1, [pc, #188] @ (8000ae0 <HAL_GPIO_Init+0x2bc>)
8000a24: 6a7b ldr r3, [r7, #36] @ 0x24
8000a26: 089b lsrs r3, r3, #2
8000a28: 3302 adds r3, #2
8000a2a: 68fa ldr r2, [r7, #12]
8000a2c: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8000a30: 683b ldr r3, [r7, #0]
8000a32: 685b ldr r3, [r3, #4]
8000a34: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8000a38: 2b00 cmp r3, #0
8000a3a: d006 beq.n 8000a4a <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
8000a3c: 4b2d ldr r3, [pc, #180] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a3e: 689a ldr r2, [r3, #8]
8000a40: 492c ldr r1, [pc, #176] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a42: 69bb ldr r3, [r7, #24]
8000a44: 4313 orrs r3, r2
8000a46: 608b str r3, [r1, #8]
8000a48: e006 b.n 8000a58 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8000a4a: 4b2a ldr r3, [pc, #168] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a4c: 689a ldr r2, [r3, #8]
8000a4e: 69bb ldr r3, [r7, #24]
8000a50: 43db mvns r3, r3
8000a52: 4928 ldr r1, [pc, #160] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a54: 4013 ands r3, r2
8000a56: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8000a58: 683b ldr r3, [r7, #0]
8000a5a: 685b ldr r3, [r3, #4]
8000a5c: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8000a60: 2b00 cmp r3, #0
8000a62: d006 beq.n 8000a72 <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
8000a64: 4b23 ldr r3, [pc, #140] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a66: 68da ldr r2, [r3, #12]
8000a68: 4922 ldr r1, [pc, #136] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a6a: 69bb ldr r3, [r7, #24]
8000a6c: 4313 orrs r3, r2
8000a6e: 60cb str r3, [r1, #12]
8000a70: e006 b.n 8000a80 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8000a72: 4b20 ldr r3, [pc, #128] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a74: 68da ldr r2, [r3, #12]
8000a76: 69bb ldr r3, [r7, #24]
8000a78: 43db mvns r3, r3
8000a7a: 491e ldr r1, [pc, #120] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a7c: 4013 ands r3, r2
8000a7e: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8000a80: 683b ldr r3, [r7, #0]
8000a82: 685b ldr r3, [r3, #4]
8000a84: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000a88: 2b00 cmp r3, #0
8000a8a: d006 beq.n 8000a9a <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
8000a8c: 4b19 ldr r3, [pc, #100] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a8e: 685a ldr r2, [r3, #4]
8000a90: 4918 ldr r1, [pc, #96] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a92: 69bb ldr r3, [r7, #24]
8000a94: 4313 orrs r3, r2
8000a96: 604b str r3, [r1, #4]
8000a98: e006 b.n 8000aa8 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8000a9a: 4b16 ldr r3, [pc, #88] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000a9c: 685a ldr r2, [r3, #4]
8000a9e: 69bb ldr r3, [r7, #24]
8000aa0: 43db mvns r3, r3
8000aa2: 4914 ldr r1, [pc, #80] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000aa4: 4013 ands r3, r2
8000aa6: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8000aa8: 683b ldr r3, [r7, #0]
8000aaa: 685b ldr r3, [r3, #4]
8000aac: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000ab0: 2b00 cmp r3, #0
8000ab2: d021 beq.n 8000af8 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
8000ab4: 4b0f ldr r3, [pc, #60] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000ab6: 681a ldr r2, [r3, #0]
8000ab8: 490e ldr r1, [pc, #56] @ (8000af4 <HAL_GPIO_Init+0x2d0>)
8000aba: 69bb ldr r3, [r7, #24]
8000abc: 4313 orrs r3, r2
8000abe: 600b str r3, [r1, #0]
8000ac0: e021 b.n 8000b06 <HAL_GPIO_Init+0x2e2>
8000ac2: bf00 nop
8000ac4: 10320000 .word 0x10320000
8000ac8: 10310000 .word 0x10310000
8000acc: 10220000 .word 0x10220000
8000ad0: 10210000 .word 0x10210000
8000ad4: 10120000 .word 0x10120000
8000ad8: 10110000 .word 0x10110000
8000adc: 40021000 .word 0x40021000
8000ae0: 40010000 .word 0x40010000
8000ae4: 40010800 .word 0x40010800
8000ae8: 40010c00 .word 0x40010c00
8000aec: 40011000 .word 0x40011000
8000af0: 40011400 .word 0x40011400
8000af4: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8000af8: 4b0b ldr r3, [pc, #44] @ (8000b28 <HAL_GPIO_Init+0x304>)
8000afa: 681a ldr r2, [r3, #0]
8000afc: 69bb ldr r3, [r7, #24]
8000afe: 43db mvns r3, r3
8000b00: 4909 ldr r1, [pc, #36] @ (8000b28 <HAL_GPIO_Init+0x304>)
8000b02: 4013 ands r3, r2
8000b04: 600b str r3, [r1, #0]
}
}
}
position++;
8000b06: 6a7b ldr r3, [r7, #36] @ 0x24
8000b08: 3301 adds r3, #1
8000b0a: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000b0c: 683b ldr r3, [r7, #0]
8000b0e: 681a ldr r2, [r3, #0]
8000b10: 6a7b ldr r3, [r7, #36] @ 0x24
8000b12: fa22 f303 lsr.w r3, r2, r3
8000b16: 2b00 cmp r3, #0
8000b18: f47f ae8e bne.w 8000838 <HAL_GPIO_Init+0x14>
}
}
8000b1c: bf00 nop
8000b1e: bf00 nop
8000b20: 372c adds r7, #44 @ 0x2c
8000b22: 46bd mov sp, r7
8000b24: bc80 pop {r7}
8000b26: 4770 bx lr
8000b28: 40010400 .word 0x40010400
08000b2c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000b2c: b480 push {r7}
8000b2e: b083 sub sp, #12
8000b30: af00 add r7, sp, #0
8000b32: 6078 str r0, [r7, #4]
8000b34: 460b mov r3, r1
8000b36: 807b strh r3, [r7, #2]
8000b38: 4613 mov r3, r2
8000b3a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8000b3c: 787b ldrb r3, [r7, #1]
8000b3e: 2b00 cmp r3, #0
8000b40: d003 beq.n 8000b4a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8000b42: 887a ldrh r2, [r7, #2]
8000b44: 687b ldr r3, [r7, #4]
8000b46: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
8000b48: e003 b.n 8000b52 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
8000b4a: 887b ldrh r3, [r7, #2]
8000b4c: 041a lsls r2, r3, #16
8000b4e: 687b ldr r3, [r7, #4]
8000b50: 611a str r2, [r3, #16]
}
8000b52: bf00 nop
8000b54: 370c adds r7, #12
8000b56: 46bd mov sp, r7
8000b58: bc80 pop {r7}
8000b5a: 4770 bx lr
08000b5c <HAL_GPIO_EXTI_IRQHandler>:
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin: Specifies the pins connected EXTI line
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
8000b5c: b580 push {r7, lr}
8000b5e: b082 sub sp, #8
8000b60: af00 add r7, sp, #0
8000b62: 4603 mov r3, r0
8000b64: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
8000b66: 4b08 ldr r3, [pc, #32] @ (8000b88 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8000b68: 695a ldr r2, [r3, #20]
8000b6a: 88fb ldrh r3, [r7, #6]
8000b6c: 4013 ands r3, r2
8000b6e: 2b00 cmp r3, #0
8000b70: d006 beq.n 8000b80 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8000b72: 4a05 ldr r2, [pc, #20] @ (8000b88 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8000b74: 88fb ldrh r3, [r7, #6]
8000b76: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
8000b78: 88fb ldrh r3, [r7, #6]
8000b7a: 4618 mov r0, r3
8000b7c: f7ff fbd0 bl 8000320 <HAL_GPIO_EXTI_Callback>
}
}
8000b80: bf00 nop
8000b82: 3708 adds r7, #8
8000b84: 46bd mov sp, r7
8000b86: bd80 pop {r7, pc}
8000b88: 40010400 .word 0x40010400
08000b8c <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000b8c: b580 push {r7, lr}
8000b8e: b086 sub sp, #24
8000b90: af00 add r7, sp, #0
8000b92: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8000b94: 687b ldr r3, [r7, #4]
8000b96: 2b00 cmp r3, #0
8000b98: d101 bne.n 8000b9e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000b9a: 2301 movs r3, #1
8000b9c: e272 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000b9e: 687b ldr r3, [r7, #4]
8000ba0: 681b ldr r3, [r3, #0]
8000ba2: f003 0301 and.w r3, r3, #1
8000ba6: 2b00 cmp r3, #0
8000ba8: f000 8087 beq.w 8000cba <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000bac: 4b92 ldr r3, [pc, #584] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000bae: 685b ldr r3, [r3, #4]
8000bb0: f003 030c and.w r3, r3, #12
8000bb4: 2b04 cmp r3, #4
8000bb6: d00c beq.n 8000bd2 <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000bb8: 4b8f ldr r3, [pc, #572] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000bba: 685b ldr r3, [r3, #4]
8000bbc: f003 030c and.w r3, r3, #12
8000bc0: 2b08 cmp r3, #8
8000bc2: d112 bne.n 8000bea <HAL_RCC_OscConfig+0x5e>
8000bc4: 4b8c ldr r3, [pc, #560] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000bc6: 685b ldr r3, [r3, #4]
8000bc8: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000bcc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8000bd0: d10b bne.n 8000bea <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000bd2: 4b89 ldr r3, [pc, #548] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000bd4: 681b ldr r3, [r3, #0]
8000bd6: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000bda: 2b00 cmp r3, #0
8000bdc: d06c beq.n 8000cb8 <HAL_RCC_OscConfig+0x12c>
8000bde: 687b ldr r3, [r7, #4]
8000be0: 685b ldr r3, [r3, #4]
8000be2: 2b00 cmp r3, #0
8000be4: d168 bne.n 8000cb8 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8000be6: 2301 movs r3, #1
8000be8: e24c b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000bea: 687b ldr r3, [r7, #4]
8000bec: 685b ldr r3, [r3, #4]
8000bee: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8000bf2: d106 bne.n 8000c02 <HAL_RCC_OscConfig+0x76>
8000bf4: 4b80 ldr r3, [pc, #512] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000bf6: 681b ldr r3, [r3, #0]
8000bf8: 4a7f ldr r2, [pc, #508] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000bfa: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000bfe: 6013 str r3, [r2, #0]
8000c00: e02e b.n 8000c60 <HAL_RCC_OscConfig+0xd4>
8000c02: 687b ldr r3, [r7, #4]
8000c04: 685b ldr r3, [r3, #4]
8000c06: 2b00 cmp r3, #0
8000c08: d10c bne.n 8000c24 <HAL_RCC_OscConfig+0x98>
8000c0a: 4b7b ldr r3, [pc, #492] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c0c: 681b ldr r3, [r3, #0]
8000c0e: 4a7a ldr r2, [pc, #488] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c10: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8000c14: 6013 str r3, [r2, #0]
8000c16: 4b78 ldr r3, [pc, #480] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c18: 681b ldr r3, [r3, #0]
8000c1a: 4a77 ldr r2, [pc, #476] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c1c: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8000c20: 6013 str r3, [r2, #0]
8000c22: e01d b.n 8000c60 <HAL_RCC_OscConfig+0xd4>
8000c24: 687b ldr r3, [r7, #4]
8000c26: 685b ldr r3, [r3, #4]
8000c28: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8000c2c: d10c bne.n 8000c48 <HAL_RCC_OscConfig+0xbc>
8000c2e: 4b72 ldr r3, [pc, #456] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c30: 681b ldr r3, [r3, #0]
8000c32: 4a71 ldr r2, [pc, #452] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c34: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8000c38: 6013 str r3, [r2, #0]
8000c3a: 4b6f ldr r3, [pc, #444] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c3c: 681b ldr r3, [r3, #0]
8000c3e: 4a6e ldr r2, [pc, #440] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c40: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000c44: 6013 str r3, [r2, #0]
8000c46: e00b b.n 8000c60 <HAL_RCC_OscConfig+0xd4>
8000c48: 4b6b ldr r3, [pc, #428] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c4a: 681b ldr r3, [r3, #0]
8000c4c: 4a6a ldr r2, [pc, #424] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c4e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8000c52: 6013 str r3, [r2, #0]
8000c54: 4b68 ldr r3, [pc, #416] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c56: 681b ldr r3, [r3, #0]
8000c58: 4a67 ldr r2, [pc, #412] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c5a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8000c5e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000c60: 687b ldr r3, [r7, #4]
8000c62: 685b ldr r3, [r3, #4]
8000c64: 2b00 cmp r3, #0
8000c66: d013 beq.n 8000c90 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000c68: f7ff fcc4 bl 80005f4 <HAL_GetTick>
8000c6c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000c6e: e008 b.n 8000c82 <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000c70: f7ff fcc0 bl 80005f4 <HAL_GetTick>
8000c74: 4602 mov r2, r0
8000c76: 693b ldr r3, [r7, #16]
8000c78: 1ad3 subs r3, r2, r3
8000c7a: 2b64 cmp r3, #100 @ 0x64
8000c7c: d901 bls.n 8000c82 <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8000c7e: 2303 movs r3, #3
8000c80: e200 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000c82: 4b5d ldr r3, [pc, #372] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000c84: 681b ldr r3, [r3, #0]
8000c86: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000c8a: 2b00 cmp r3, #0
8000c8c: d0f0 beq.n 8000c70 <HAL_RCC_OscConfig+0xe4>
8000c8e: e014 b.n 8000cba <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000c90: f7ff fcb0 bl 80005f4 <HAL_GetTick>
8000c94: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000c96: e008 b.n 8000caa <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000c98: f7ff fcac bl 80005f4 <HAL_GetTick>
8000c9c: 4602 mov r2, r0
8000c9e: 693b ldr r3, [r7, #16]
8000ca0: 1ad3 subs r3, r2, r3
8000ca2: 2b64 cmp r3, #100 @ 0x64
8000ca4: d901 bls.n 8000caa <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8000ca6: 2303 movs r3, #3
8000ca8: e1ec b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000caa: 4b53 ldr r3, [pc, #332] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000cac: 681b ldr r3, [r3, #0]
8000cae: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000cb2: 2b00 cmp r3, #0
8000cb4: d1f0 bne.n 8000c98 <HAL_RCC_OscConfig+0x10c>
8000cb6: e000 b.n 8000cba <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000cb8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000cba: 687b ldr r3, [r7, #4]
8000cbc: 681b ldr r3, [r3, #0]
8000cbe: f003 0302 and.w r3, r3, #2
8000cc2: 2b00 cmp r3, #0
8000cc4: d063 beq.n 8000d8e <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000cc6: 4b4c ldr r3, [pc, #304] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000cc8: 685b ldr r3, [r3, #4]
8000cca: f003 030c and.w r3, r3, #12
8000cce: 2b00 cmp r3, #0
8000cd0: d00b beq.n 8000cea <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8000cd2: 4b49 ldr r3, [pc, #292] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000cd4: 685b ldr r3, [r3, #4]
8000cd6: f003 030c and.w r3, r3, #12
8000cda: 2b08 cmp r3, #8
8000cdc: d11c bne.n 8000d18 <HAL_RCC_OscConfig+0x18c>
8000cde: 4b46 ldr r3, [pc, #280] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000ce0: 685b ldr r3, [r3, #4]
8000ce2: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000ce6: 2b00 cmp r3, #0
8000ce8: d116 bne.n 8000d18 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000cea: 4b43 ldr r3, [pc, #268] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000cec: 681b ldr r3, [r3, #0]
8000cee: f003 0302 and.w r3, r3, #2
8000cf2: 2b00 cmp r3, #0
8000cf4: d005 beq.n 8000d02 <HAL_RCC_OscConfig+0x176>
8000cf6: 687b ldr r3, [r7, #4]
8000cf8: 691b ldr r3, [r3, #16]
8000cfa: 2b01 cmp r3, #1
8000cfc: d001 beq.n 8000d02 <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8000cfe: 2301 movs r3, #1
8000d00: e1c0 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000d02: 4b3d ldr r3, [pc, #244] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000d04: 681b ldr r3, [r3, #0]
8000d06: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8000d0a: 687b ldr r3, [r7, #4]
8000d0c: 695b ldr r3, [r3, #20]
8000d0e: 00db lsls r3, r3, #3
8000d10: 4939 ldr r1, [pc, #228] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000d12: 4313 orrs r3, r2
8000d14: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000d16: e03a b.n 8000d8e <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000d18: 687b ldr r3, [r7, #4]
8000d1a: 691b ldr r3, [r3, #16]
8000d1c: 2b00 cmp r3, #0
8000d1e: d020 beq.n 8000d62 <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000d20: 4b36 ldr r3, [pc, #216] @ (8000dfc <HAL_RCC_OscConfig+0x270>)
8000d22: 2201 movs r2, #1
8000d24: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d26: f7ff fc65 bl 80005f4 <HAL_GetTick>
8000d2a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000d2c: e008 b.n 8000d40 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000d2e: f7ff fc61 bl 80005f4 <HAL_GetTick>
8000d32: 4602 mov r2, r0
8000d34: 693b ldr r3, [r7, #16]
8000d36: 1ad3 subs r3, r2, r3
8000d38: 2b02 cmp r3, #2
8000d3a: d901 bls.n 8000d40 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8000d3c: 2303 movs r3, #3
8000d3e: e1a1 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000d40: 4b2d ldr r3, [pc, #180] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000d42: 681b ldr r3, [r3, #0]
8000d44: f003 0302 and.w r3, r3, #2
8000d48: 2b00 cmp r3, #0
8000d4a: d0f0 beq.n 8000d2e <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000d4c: 4b2a ldr r3, [pc, #168] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000d4e: 681b ldr r3, [r3, #0]
8000d50: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8000d54: 687b ldr r3, [r7, #4]
8000d56: 695b ldr r3, [r3, #20]
8000d58: 00db lsls r3, r3, #3
8000d5a: 4927 ldr r1, [pc, #156] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000d5c: 4313 orrs r3, r2
8000d5e: 600b str r3, [r1, #0]
8000d60: e015 b.n 8000d8e <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000d62: 4b26 ldr r3, [pc, #152] @ (8000dfc <HAL_RCC_OscConfig+0x270>)
8000d64: 2200 movs r2, #0
8000d66: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d68: f7ff fc44 bl 80005f4 <HAL_GetTick>
8000d6c: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000d6e: e008 b.n 8000d82 <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000d70: f7ff fc40 bl 80005f4 <HAL_GetTick>
8000d74: 4602 mov r2, r0
8000d76: 693b ldr r3, [r7, #16]
8000d78: 1ad3 subs r3, r2, r3
8000d7a: 2b02 cmp r3, #2
8000d7c: d901 bls.n 8000d82 <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8000d7e: 2303 movs r3, #3
8000d80: e180 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000d82: 4b1d ldr r3, [pc, #116] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000d84: 681b ldr r3, [r3, #0]
8000d86: f003 0302 and.w r3, r3, #2
8000d8a: 2b00 cmp r3, #0
8000d8c: d1f0 bne.n 8000d70 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000d8e: 687b ldr r3, [r7, #4]
8000d90: 681b ldr r3, [r3, #0]
8000d92: f003 0308 and.w r3, r3, #8
8000d96: 2b00 cmp r3, #0
8000d98: d03a beq.n 8000e10 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000d9a: 687b ldr r3, [r7, #4]
8000d9c: 699b ldr r3, [r3, #24]
8000d9e: 2b00 cmp r3, #0
8000da0: d019 beq.n 8000dd6 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000da2: 4b17 ldr r3, [pc, #92] @ (8000e00 <HAL_RCC_OscConfig+0x274>)
8000da4: 2201 movs r2, #1
8000da6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000da8: f7ff fc24 bl 80005f4 <HAL_GetTick>
8000dac: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000dae: e008 b.n 8000dc2 <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000db0: f7ff fc20 bl 80005f4 <HAL_GetTick>
8000db4: 4602 mov r2, r0
8000db6: 693b ldr r3, [r7, #16]
8000db8: 1ad3 subs r3, r2, r3
8000dba: 2b02 cmp r3, #2
8000dbc: d901 bls.n 8000dc2 <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8000dbe: 2303 movs r3, #3
8000dc0: e160 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000dc2: 4b0d ldr r3, [pc, #52] @ (8000df8 <HAL_RCC_OscConfig+0x26c>)
8000dc4: 6a5b ldr r3, [r3, #36] @ 0x24
8000dc6: f003 0302 and.w r3, r3, #2
8000dca: 2b00 cmp r3, #0
8000dcc: d0f0 beq.n 8000db0 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8000dce: 2001 movs r0, #1
8000dd0: f000 face bl 8001370 <RCC_Delay>
8000dd4: e01c b.n 8000e10 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000dd6: 4b0a ldr r3, [pc, #40] @ (8000e00 <HAL_RCC_OscConfig+0x274>)
8000dd8: 2200 movs r2, #0
8000dda: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ddc: f7ff fc0a bl 80005f4 <HAL_GetTick>
8000de0: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000de2: e00f b.n 8000e04 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000de4: f7ff fc06 bl 80005f4 <HAL_GetTick>
8000de8: 4602 mov r2, r0
8000dea: 693b ldr r3, [r7, #16]
8000dec: 1ad3 subs r3, r2, r3
8000dee: 2b02 cmp r3, #2
8000df0: d908 bls.n 8000e04 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
8000df2: 2303 movs r3, #3
8000df4: e146 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
8000df6: bf00 nop
8000df8: 40021000 .word 0x40021000
8000dfc: 42420000 .word 0x42420000
8000e00: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000e04: 4b92 ldr r3, [pc, #584] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000e06: 6a5b ldr r3, [r3, #36] @ 0x24
8000e08: f003 0302 and.w r3, r3, #2
8000e0c: 2b00 cmp r3, #0
8000e0e: d1e9 bne.n 8000de4 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8000e10: 687b ldr r3, [r7, #4]
8000e12: 681b ldr r3, [r3, #0]
8000e14: f003 0304 and.w r3, r3, #4
8000e18: 2b00 cmp r3, #0
8000e1a: f000 80a6 beq.w 8000f6a <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8000e1e: 2300 movs r3, #0
8000e20: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8000e22: 4b8b ldr r3, [pc, #556] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000e24: 69db ldr r3, [r3, #28]
8000e26: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000e2a: 2b00 cmp r3, #0
8000e2c: d10d bne.n 8000e4a <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8000e2e: 4b88 ldr r3, [pc, #544] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000e30: 69db ldr r3, [r3, #28]
8000e32: 4a87 ldr r2, [pc, #540] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000e34: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000e38: 61d3 str r3, [r2, #28]
8000e3a: 4b85 ldr r3, [pc, #532] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000e3c: 69db ldr r3, [r3, #28]
8000e3e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000e42: 60bb str r3, [r7, #8]
8000e44: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8000e46: 2301 movs r3, #1
8000e48: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000e4a: 4b82 ldr r3, [pc, #520] @ (8001054 <HAL_RCC_OscConfig+0x4c8>)
8000e4c: 681b ldr r3, [r3, #0]
8000e4e: f403 7380 and.w r3, r3, #256 @ 0x100
8000e52: 2b00 cmp r3, #0
8000e54: d118 bne.n 8000e88 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8000e56: 4b7f ldr r3, [pc, #508] @ (8001054 <HAL_RCC_OscConfig+0x4c8>)
8000e58: 681b ldr r3, [r3, #0]
8000e5a: 4a7e ldr r2, [pc, #504] @ (8001054 <HAL_RCC_OscConfig+0x4c8>)
8000e5c: f443 7380 orr.w r3, r3, #256 @ 0x100
8000e60: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8000e62: f7ff fbc7 bl 80005f4 <HAL_GetTick>
8000e66: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000e68: e008 b.n 8000e7c <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8000e6a: f7ff fbc3 bl 80005f4 <HAL_GetTick>
8000e6e: 4602 mov r2, r0
8000e70: 693b ldr r3, [r7, #16]
8000e72: 1ad3 subs r3, r2, r3
8000e74: 2b64 cmp r3, #100 @ 0x64
8000e76: d901 bls.n 8000e7c <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8000e78: 2303 movs r3, #3
8000e7a: e103 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000e7c: 4b75 ldr r3, [pc, #468] @ (8001054 <HAL_RCC_OscConfig+0x4c8>)
8000e7e: 681b ldr r3, [r3, #0]
8000e80: f403 7380 and.w r3, r3, #256 @ 0x100
8000e84: 2b00 cmp r3, #0
8000e86: d0f0 beq.n 8000e6a <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8000e88: 687b ldr r3, [r7, #4]
8000e8a: 68db ldr r3, [r3, #12]
8000e8c: 2b01 cmp r3, #1
8000e8e: d106 bne.n 8000e9e <HAL_RCC_OscConfig+0x312>
8000e90: 4b6f ldr r3, [pc, #444] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000e92: 6a1b ldr r3, [r3, #32]
8000e94: 4a6e ldr r2, [pc, #440] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000e96: f043 0301 orr.w r3, r3, #1
8000e9a: 6213 str r3, [r2, #32]
8000e9c: e02d b.n 8000efa <HAL_RCC_OscConfig+0x36e>
8000e9e: 687b ldr r3, [r7, #4]
8000ea0: 68db ldr r3, [r3, #12]
8000ea2: 2b00 cmp r3, #0
8000ea4: d10c bne.n 8000ec0 <HAL_RCC_OscConfig+0x334>
8000ea6: 4b6a ldr r3, [pc, #424] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000ea8: 6a1b ldr r3, [r3, #32]
8000eaa: 4a69 ldr r2, [pc, #420] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000eac: f023 0301 bic.w r3, r3, #1
8000eb0: 6213 str r3, [r2, #32]
8000eb2: 4b67 ldr r3, [pc, #412] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000eb4: 6a1b ldr r3, [r3, #32]
8000eb6: 4a66 ldr r2, [pc, #408] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000eb8: f023 0304 bic.w r3, r3, #4
8000ebc: 6213 str r3, [r2, #32]
8000ebe: e01c b.n 8000efa <HAL_RCC_OscConfig+0x36e>
8000ec0: 687b ldr r3, [r7, #4]
8000ec2: 68db ldr r3, [r3, #12]
8000ec4: 2b05 cmp r3, #5
8000ec6: d10c bne.n 8000ee2 <HAL_RCC_OscConfig+0x356>
8000ec8: 4b61 ldr r3, [pc, #388] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000eca: 6a1b ldr r3, [r3, #32]
8000ecc: 4a60 ldr r2, [pc, #384] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000ece: f043 0304 orr.w r3, r3, #4
8000ed2: 6213 str r3, [r2, #32]
8000ed4: 4b5e ldr r3, [pc, #376] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000ed6: 6a1b ldr r3, [r3, #32]
8000ed8: 4a5d ldr r2, [pc, #372] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000eda: f043 0301 orr.w r3, r3, #1
8000ede: 6213 str r3, [r2, #32]
8000ee0: e00b b.n 8000efa <HAL_RCC_OscConfig+0x36e>
8000ee2: 4b5b ldr r3, [pc, #364] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000ee4: 6a1b ldr r3, [r3, #32]
8000ee6: 4a5a ldr r2, [pc, #360] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000ee8: f023 0301 bic.w r3, r3, #1
8000eec: 6213 str r3, [r2, #32]
8000eee: 4b58 ldr r3, [pc, #352] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000ef0: 6a1b ldr r3, [r3, #32]
8000ef2: 4a57 ldr r2, [pc, #348] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000ef4: f023 0304 bic.w r3, r3, #4
8000ef8: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8000efa: 687b ldr r3, [r7, #4]
8000efc: 68db ldr r3, [r3, #12]
8000efe: 2b00 cmp r3, #0
8000f00: d015 beq.n 8000f2e <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f02: f7ff fb77 bl 80005f4 <HAL_GetTick>
8000f06: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000f08: e00a b.n 8000f20 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000f0a: f7ff fb73 bl 80005f4 <HAL_GetTick>
8000f0e: 4602 mov r2, r0
8000f10: 693b ldr r3, [r7, #16]
8000f12: 1ad3 subs r3, r2, r3
8000f14: f241 3288 movw r2, #5000 @ 0x1388
8000f18: 4293 cmp r3, r2
8000f1a: d901 bls.n 8000f20 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8000f1c: 2303 movs r3, #3
8000f1e: e0b1 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000f20: 4b4b ldr r3, [pc, #300] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000f22: 6a1b ldr r3, [r3, #32]
8000f24: f003 0302 and.w r3, r3, #2
8000f28: 2b00 cmp r3, #0
8000f2a: d0ee beq.n 8000f0a <HAL_RCC_OscConfig+0x37e>
8000f2c: e014 b.n 8000f58 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f2e: f7ff fb61 bl 80005f4 <HAL_GetTick>
8000f32: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000f34: e00a b.n 8000f4c <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000f36: f7ff fb5d bl 80005f4 <HAL_GetTick>
8000f3a: 4602 mov r2, r0
8000f3c: 693b ldr r3, [r7, #16]
8000f3e: 1ad3 subs r3, r2, r3
8000f40: f241 3288 movw r2, #5000 @ 0x1388
8000f44: 4293 cmp r3, r2
8000f46: d901 bls.n 8000f4c <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8000f48: 2303 movs r3, #3
8000f4a: e09b b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000f4c: 4b40 ldr r3, [pc, #256] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000f4e: 6a1b ldr r3, [r3, #32]
8000f50: f003 0302 and.w r3, r3, #2
8000f54: 2b00 cmp r3, #0
8000f56: d1ee bne.n 8000f36 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8000f58: 7dfb ldrb r3, [r7, #23]
8000f5a: 2b01 cmp r3, #1
8000f5c: d105 bne.n 8000f6a <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000f5e: 4b3c ldr r3, [pc, #240] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000f60: 69db ldr r3, [r3, #28]
8000f62: 4a3b ldr r2, [pc, #236] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000f64: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8000f68: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8000f6a: 687b ldr r3, [r7, #4]
8000f6c: 69db ldr r3, [r3, #28]
8000f6e: 2b00 cmp r3, #0
8000f70: f000 8087 beq.w 8001082 <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8000f74: 4b36 ldr r3, [pc, #216] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000f76: 685b ldr r3, [r3, #4]
8000f78: f003 030c and.w r3, r3, #12
8000f7c: 2b08 cmp r3, #8
8000f7e: d061 beq.n 8001044 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8000f80: 687b ldr r3, [r7, #4]
8000f82: 69db ldr r3, [r3, #28]
8000f84: 2b02 cmp r3, #2
8000f86: d146 bne.n 8001016 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000f88: 4b33 ldr r3, [pc, #204] @ (8001058 <HAL_RCC_OscConfig+0x4cc>)
8000f8a: 2200 movs r2, #0
8000f8c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f8e: f7ff fb31 bl 80005f4 <HAL_GetTick>
8000f92: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000f94: e008 b.n 8000fa8 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000f96: f7ff fb2d bl 80005f4 <HAL_GetTick>
8000f9a: 4602 mov r2, r0
8000f9c: 693b ldr r3, [r7, #16]
8000f9e: 1ad3 subs r3, r2, r3
8000fa0: 2b02 cmp r3, #2
8000fa2: d901 bls.n 8000fa8 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8000fa4: 2303 movs r3, #3
8000fa6: e06d b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000fa8: 4b29 ldr r3, [pc, #164] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000faa: 681b ldr r3, [r3, #0]
8000fac: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8000fb0: 2b00 cmp r3, #0
8000fb2: d1f0 bne.n 8000f96 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8000fb4: 687b ldr r3, [r7, #4]
8000fb6: 6a1b ldr r3, [r3, #32]
8000fb8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8000fbc: d108 bne.n 8000fd0 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8000fbe: 4b24 ldr r3, [pc, #144] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000fc0: 685b ldr r3, [r3, #4]
8000fc2: f423 3200 bic.w r2, r3, #131072 @ 0x20000
8000fc6: 687b ldr r3, [r7, #4]
8000fc8: 689b ldr r3, [r3, #8]
8000fca: 4921 ldr r1, [pc, #132] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000fcc: 4313 orrs r3, r2
8000fce: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8000fd0: 4b1f ldr r3, [pc, #124] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000fd2: 685b ldr r3, [r3, #4]
8000fd4: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8000fd8: 687b ldr r3, [r7, #4]
8000fda: 6a19 ldr r1, [r3, #32]
8000fdc: 687b ldr r3, [r7, #4]
8000fde: 6a5b ldr r3, [r3, #36] @ 0x24
8000fe0: 430b orrs r3, r1
8000fe2: 491b ldr r1, [pc, #108] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8000fe4: 4313 orrs r3, r2
8000fe6: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8000fe8: 4b1b ldr r3, [pc, #108] @ (8001058 <HAL_RCC_OscConfig+0x4cc>)
8000fea: 2201 movs r2, #1
8000fec: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fee: f7ff fb01 bl 80005f4 <HAL_GetTick>
8000ff2: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000ff4: e008 b.n 8001008 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000ff6: f7ff fafd bl 80005f4 <HAL_GetTick>
8000ffa: 4602 mov r2, r0
8000ffc: 693b ldr r3, [r7, #16]
8000ffe: 1ad3 subs r3, r2, r3
8001000: 2b02 cmp r3, #2
8001002: d901 bls.n 8001008 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8001004: 2303 movs r3, #3
8001006: e03d b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001008: 4b11 ldr r3, [pc, #68] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
800100a: 681b ldr r3, [r3, #0]
800100c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001010: 2b00 cmp r3, #0
8001012: d0f0 beq.n 8000ff6 <HAL_RCC_OscConfig+0x46a>
8001014: e035 b.n 8001082 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001016: 4b10 ldr r3, [pc, #64] @ (8001058 <HAL_RCC_OscConfig+0x4cc>)
8001018: 2200 movs r2, #0
800101a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800101c: f7ff faea bl 80005f4 <HAL_GetTick>
8001020: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001022: e008 b.n 8001036 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001024: f7ff fae6 bl 80005f4 <HAL_GetTick>
8001028: 4602 mov r2, r0
800102a: 693b ldr r3, [r7, #16]
800102c: 1ad3 subs r3, r2, r3
800102e: 2b02 cmp r3, #2
8001030: d901 bls.n 8001036 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8001032: 2303 movs r3, #3
8001034: e026 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001036: 4b06 ldr r3, [pc, #24] @ (8001050 <HAL_RCC_OscConfig+0x4c4>)
8001038: 681b ldr r3, [r3, #0]
800103a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800103e: 2b00 cmp r3, #0
8001040: d1f0 bne.n 8001024 <HAL_RCC_OscConfig+0x498>
8001042: e01e b.n 8001082 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001044: 687b ldr r3, [r7, #4]
8001046: 69db ldr r3, [r3, #28]
8001048: 2b01 cmp r3, #1
800104a: d107 bne.n 800105c <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
800104c: 2301 movs r3, #1
800104e: e019 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
8001050: 40021000 .word 0x40021000
8001054: 40007000 .word 0x40007000
8001058: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800105c: 4b0b ldr r3, [pc, #44] @ (800108c <HAL_RCC_OscConfig+0x500>)
800105e: 685b ldr r3, [r3, #4]
8001060: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001062: 68fb ldr r3, [r7, #12]
8001064: f403 3280 and.w r2, r3, #65536 @ 0x10000
8001068: 687b ldr r3, [r7, #4]
800106a: 6a1b ldr r3, [r3, #32]
800106c: 429a cmp r2, r3
800106e: d106 bne.n 800107e <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8001070: 68fb ldr r3, [r7, #12]
8001072: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8001076: 687b ldr r3, [r7, #4]
8001078: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800107a: 429a cmp r2, r3
800107c: d001 beq.n 8001082 <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
800107e: 2301 movs r3, #1
8001080: e000 b.n 8001084 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
8001082: 2300 movs r3, #0
}
8001084: 4618 mov r0, r3
8001086: 3718 adds r7, #24
8001088: 46bd mov sp, r7
800108a: bd80 pop {r7, pc}
800108c: 40021000 .word 0x40021000
08001090 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001090: b580 push {r7, lr}
8001092: b084 sub sp, #16
8001094: af00 add r7, sp, #0
8001096: 6078 str r0, [r7, #4]
8001098: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
800109a: 687b ldr r3, [r7, #4]
800109c: 2b00 cmp r3, #0
800109e: d101 bne.n 80010a4 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80010a0: 2301 movs r3, #1
80010a2: e0d0 b.n 8001246 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
80010a4: 4b6a ldr r3, [pc, #424] @ (8001250 <HAL_RCC_ClockConfig+0x1c0>)
80010a6: 681b ldr r3, [r3, #0]
80010a8: f003 0307 and.w r3, r3, #7
80010ac: 683a ldr r2, [r7, #0]
80010ae: 429a cmp r2, r3
80010b0: d910 bls.n 80010d4 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80010b2: 4b67 ldr r3, [pc, #412] @ (8001250 <HAL_RCC_ClockConfig+0x1c0>)
80010b4: 681b ldr r3, [r3, #0]
80010b6: f023 0207 bic.w r2, r3, #7
80010ba: 4965 ldr r1, [pc, #404] @ (8001250 <HAL_RCC_ClockConfig+0x1c0>)
80010bc: 683b ldr r3, [r7, #0]
80010be: 4313 orrs r3, r2
80010c0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80010c2: 4b63 ldr r3, [pc, #396] @ (8001250 <HAL_RCC_ClockConfig+0x1c0>)
80010c4: 681b ldr r3, [r3, #0]
80010c6: f003 0307 and.w r3, r3, #7
80010ca: 683a ldr r2, [r7, #0]
80010cc: 429a cmp r2, r3
80010ce: d001 beq.n 80010d4 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
80010d0: 2301 movs r3, #1
80010d2: e0b8 b.n 8001246 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80010d4: 687b ldr r3, [r7, #4]
80010d6: 681b ldr r3, [r3, #0]
80010d8: f003 0302 and.w r3, r3, #2
80010dc: 2b00 cmp r3, #0
80010de: d020 beq.n 8001122 <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80010e0: 687b ldr r3, [r7, #4]
80010e2: 681b ldr r3, [r3, #0]
80010e4: f003 0304 and.w r3, r3, #4
80010e8: 2b00 cmp r3, #0
80010ea: d005 beq.n 80010f8 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80010ec: 4b59 ldr r3, [pc, #356] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
80010ee: 685b ldr r3, [r3, #4]
80010f0: 4a58 ldr r2, [pc, #352] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
80010f2: f443 63e0 orr.w r3, r3, #1792 @ 0x700
80010f6: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80010f8: 687b ldr r3, [r7, #4]
80010fa: 681b ldr r3, [r3, #0]
80010fc: f003 0308 and.w r3, r3, #8
8001100: 2b00 cmp r3, #0
8001102: d005 beq.n 8001110 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8001104: 4b53 ldr r3, [pc, #332] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
8001106: 685b ldr r3, [r3, #4]
8001108: 4a52 ldr r2, [pc, #328] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
800110a: f443 5360 orr.w r3, r3, #14336 @ 0x3800
800110e: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001110: 4b50 ldr r3, [pc, #320] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
8001112: 685b ldr r3, [r3, #4]
8001114: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8001118: 687b ldr r3, [r7, #4]
800111a: 689b ldr r3, [r3, #8]
800111c: 494d ldr r1, [pc, #308] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
800111e: 4313 orrs r3, r2
8001120: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001122: 687b ldr r3, [r7, #4]
8001124: 681b ldr r3, [r3, #0]
8001126: f003 0301 and.w r3, r3, #1
800112a: 2b00 cmp r3, #0
800112c: d040 beq.n 80011b0 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800112e: 687b ldr r3, [r7, #4]
8001130: 685b ldr r3, [r3, #4]
8001132: 2b01 cmp r3, #1
8001134: d107 bne.n 8001146 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001136: 4b47 ldr r3, [pc, #284] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
8001138: 681b ldr r3, [r3, #0]
800113a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800113e: 2b00 cmp r3, #0
8001140: d115 bne.n 800116e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001142: 2301 movs r3, #1
8001144: e07f b.n 8001246 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001146: 687b ldr r3, [r7, #4]
8001148: 685b ldr r3, [r3, #4]
800114a: 2b02 cmp r3, #2
800114c: d107 bne.n 800115e <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800114e: 4b41 ldr r3, [pc, #260] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
8001150: 681b ldr r3, [r3, #0]
8001152: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001156: 2b00 cmp r3, #0
8001158: d109 bne.n 800116e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800115a: 2301 movs r3, #1
800115c: e073 b.n 8001246 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800115e: 4b3d ldr r3, [pc, #244] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
8001160: 681b ldr r3, [r3, #0]
8001162: f003 0302 and.w r3, r3, #2
8001166: 2b00 cmp r3, #0
8001168: d101 bne.n 800116e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800116a: 2301 movs r3, #1
800116c: e06b b.n 8001246 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800116e: 4b39 ldr r3, [pc, #228] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
8001170: 685b ldr r3, [r3, #4]
8001172: f023 0203 bic.w r2, r3, #3
8001176: 687b ldr r3, [r7, #4]
8001178: 685b ldr r3, [r3, #4]
800117a: 4936 ldr r1, [pc, #216] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
800117c: 4313 orrs r3, r2
800117e: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001180: f7ff fa38 bl 80005f4 <HAL_GetTick>
8001184: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001186: e00a b.n 800119e <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001188: f7ff fa34 bl 80005f4 <HAL_GetTick>
800118c: 4602 mov r2, r0
800118e: 68fb ldr r3, [r7, #12]
8001190: 1ad3 subs r3, r2, r3
8001192: f241 3288 movw r2, #5000 @ 0x1388
8001196: 4293 cmp r3, r2
8001198: d901 bls.n 800119e <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
800119a: 2303 movs r3, #3
800119c: e053 b.n 8001246 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800119e: 4b2d ldr r3, [pc, #180] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
80011a0: 685b ldr r3, [r3, #4]
80011a2: f003 020c and.w r2, r3, #12
80011a6: 687b ldr r3, [r7, #4]
80011a8: 685b ldr r3, [r3, #4]
80011aa: 009b lsls r3, r3, #2
80011ac: 429a cmp r2, r3
80011ae: d1eb bne.n 8001188 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
80011b0: 4b27 ldr r3, [pc, #156] @ (8001250 <HAL_RCC_ClockConfig+0x1c0>)
80011b2: 681b ldr r3, [r3, #0]
80011b4: f003 0307 and.w r3, r3, #7
80011b8: 683a ldr r2, [r7, #0]
80011ba: 429a cmp r2, r3
80011bc: d210 bcs.n 80011e0 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80011be: 4b24 ldr r3, [pc, #144] @ (8001250 <HAL_RCC_ClockConfig+0x1c0>)
80011c0: 681b ldr r3, [r3, #0]
80011c2: f023 0207 bic.w r2, r3, #7
80011c6: 4922 ldr r1, [pc, #136] @ (8001250 <HAL_RCC_ClockConfig+0x1c0>)
80011c8: 683b ldr r3, [r7, #0]
80011ca: 4313 orrs r3, r2
80011cc: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80011ce: 4b20 ldr r3, [pc, #128] @ (8001250 <HAL_RCC_ClockConfig+0x1c0>)
80011d0: 681b ldr r3, [r3, #0]
80011d2: f003 0307 and.w r3, r3, #7
80011d6: 683a ldr r2, [r7, #0]
80011d8: 429a cmp r2, r3
80011da: d001 beq.n 80011e0 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
80011dc: 2301 movs r3, #1
80011de: e032 b.n 8001246 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80011e0: 687b ldr r3, [r7, #4]
80011e2: 681b ldr r3, [r3, #0]
80011e4: f003 0304 and.w r3, r3, #4
80011e8: 2b00 cmp r3, #0
80011ea: d008 beq.n 80011fe <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80011ec: 4b19 ldr r3, [pc, #100] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
80011ee: 685b ldr r3, [r3, #4]
80011f0: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80011f4: 687b ldr r3, [r7, #4]
80011f6: 68db ldr r3, [r3, #12]
80011f8: 4916 ldr r1, [pc, #88] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
80011fa: 4313 orrs r3, r2
80011fc: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80011fe: 687b ldr r3, [r7, #4]
8001200: 681b ldr r3, [r3, #0]
8001202: f003 0308 and.w r3, r3, #8
8001206: 2b00 cmp r3, #0
8001208: d009 beq.n 800121e <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
800120a: 4b12 ldr r3, [pc, #72] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
800120c: 685b ldr r3, [r3, #4]
800120e: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8001212: 687b ldr r3, [r7, #4]
8001214: 691b ldr r3, [r3, #16]
8001216: 00db lsls r3, r3, #3
8001218: 490e ldr r1, [pc, #56] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
800121a: 4313 orrs r3, r2
800121c: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
800121e: f000 f821 bl 8001264 <HAL_RCC_GetSysClockFreq>
8001222: 4602 mov r2, r0
8001224: 4b0b ldr r3, [pc, #44] @ (8001254 <HAL_RCC_ClockConfig+0x1c4>)
8001226: 685b ldr r3, [r3, #4]
8001228: 091b lsrs r3, r3, #4
800122a: f003 030f and.w r3, r3, #15
800122e: 490a ldr r1, [pc, #40] @ (8001258 <HAL_RCC_ClockConfig+0x1c8>)
8001230: 5ccb ldrb r3, [r1, r3]
8001232: fa22 f303 lsr.w r3, r2, r3
8001236: 4a09 ldr r2, [pc, #36] @ (800125c <HAL_RCC_ClockConfig+0x1cc>)
8001238: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
800123a: 4b09 ldr r3, [pc, #36] @ (8001260 <HAL_RCC_ClockConfig+0x1d0>)
800123c: 681b ldr r3, [r3, #0]
800123e: 4618 mov r0, r3
8001240: f7ff f996 bl 8000570 <HAL_InitTick>
return HAL_OK;
8001244: 2300 movs r3, #0
}
8001246: 4618 mov r0, r3
8001248: 3710 adds r7, #16
800124a: 46bd mov sp, r7
800124c: bd80 pop {r7, pc}
800124e: bf00 nop
8001250: 40022000 .word 0x40022000
8001254: 40021000 .word 0x40021000
8001258: 080015d8 .word 0x080015d8
800125c: 20000000 .word 0x20000000
8001260: 20000004 .word 0x20000004
08001264 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001264: b480 push {r7}
8001266: b087 sub sp, #28
8001268: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
800126a: 2300 movs r3, #0
800126c: 60fb str r3, [r7, #12]
800126e: 2300 movs r3, #0
8001270: 60bb str r3, [r7, #8]
8001272: 2300 movs r3, #0
8001274: 617b str r3, [r7, #20]
8001276: 2300 movs r3, #0
8001278: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
800127a: 2300 movs r3, #0
800127c: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
800127e: 4b1e ldr r3, [pc, #120] @ (80012f8 <HAL_RCC_GetSysClockFreq+0x94>)
8001280: 685b ldr r3, [r3, #4]
8001282: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8001284: 68fb ldr r3, [r7, #12]
8001286: f003 030c and.w r3, r3, #12
800128a: 2b04 cmp r3, #4
800128c: d002 beq.n 8001294 <HAL_RCC_GetSysClockFreq+0x30>
800128e: 2b08 cmp r3, #8
8001290: d003 beq.n 800129a <HAL_RCC_GetSysClockFreq+0x36>
8001292: e027 b.n 80012e4 <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8001294: 4b19 ldr r3, [pc, #100] @ (80012fc <HAL_RCC_GetSysClockFreq+0x98>)
8001296: 613b str r3, [r7, #16]
break;
8001298: e027 b.n 80012ea <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
800129a: 68fb ldr r3, [r7, #12]
800129c: 0c9b lsrs r3, r3, #18
800129e: f003 030f and.w r3, r3, #15
80012a2: 4a17 ldr r2, [pc, #92] @ (8001300 <HAL_RCC_GetSysClockFreq+0x9c>)
80012a4: 5cd3 ldrb r3, [r2, r3]
80012a6: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
80012a8: 68fb ldr r3, [r7, #12]
80012aa: f403 3380 and.w r3, r3, #65536 @ 0x10000
80012ae: 2b00 cmp r3, #0
80012b0: d010 beq.n 80012d4 <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
80012b2: 4b11 ldr r3, [pc, #68] @ (80012f8 <HAL_RCC_GetSysClockFreq+0x94>)
80012b4: 685b ldr r3, [r3, #4]
80012b6: 0c5b lsrs r3, r3, #17
80012b8: f003 0301 and.w r3, r3, #1
80012bc: 4a11 ldr r2, [pc, #68] @ (8001304 <HAL_RCC_GetSysClockFreq+0xa0>)
80012be: 5cd3 ldrb r3, [r2, r3]
80012c0: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
80012c2: 687b ldr r3, [r7, #4]
80012c4: 4a0d ldr r2, [pc, #52] @ (80012fc <HAL_RCC_GetSysClockFreq+0x98>)
80012c6: fb03 f202 mul.w r2, r3, r2
80012ca: 68bb ldr r3, [r7, #8]
80012cc: fbb2 f3f3 udiv r3, r2, r3
80012d0: 617b str r3, [r7, #20]
80012d2: e004 b.n 80012de <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
80012d4: 687b ldr r3, [r7, #4]
80012d6: 4a0c ldr r2, [pc, #48] @ (8001308 <HAL_RCC_GetSysClockFreq+0xa4>)
80012d8: fb02 f303 mul.w r3, r2, r3
80012dc: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
80012de: 697b ldr r3, [r7, #20]
80012e0: 613b str r3, [r7, #16]
break;
80012e2: e002 b.n 80012ea <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
80012e4: 4b05 ldr r3, [pc, #20] @ (80012fc <HAL_RCC_GetSysClockFreq+0x98>)
80012e6: 613b str r3, [r7, #16]
break;
80012e8: bf00 nop
}
}
return sysclockfreq;
80012ea: 693b ldr r3, [r7, #16]
}
80012ec: 4618 mov r0, r3
80012ee: 371c adds r7, #28
80012f0: 46bd mov sp, r7
80012f2: bc80 pop {r7}
80012f4: 4770 bx lr
80012f6: bf00 nop
80012f8: 40021000 .word 0x40021000
80012fc: 007a1200 .word 0x007a1200
8001300: 080015f0 .word 0x080015f0
8001304: 08001600 .word 0x08001600
8001308: 003d0900 .word 0x003d0900
0800130c <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
800130c: b480 push {r7}
800130e: af00 add r7, sp, #0
return SystemCoreClock;
8001310: 4b02 ldr r3, [pc, #8] @ (800131c <HAL_RCC_GetHCLKFreq+0x10>)
8001312: 681b ldr r3, [r3, #0]
}
8001314: 4618 mov r0, r3
8001316: 46bd mov sp, r7
8001318: bc80 pop {r7}
800131a: 4770 bx lr
800131c: 20000000 .word 0x20000000
08001320 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001320: b580 push {r7, lr}
8001322: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8001324: f7ff fff2 bl 800130c <HAL_RCC_GetHCLKFreq>
8001328: 4602 mov r2, r0
800132a: 4b05 ldr r3, [pc, #20] @ (8001340 <HAL_RCC_GetPCLK1Freq+0x20>)
800132c: 685b ldr r3, [r3, #4]
800132e: 0a1b lsrs r3, r3, #8
8001330: f003 0307 and.w r3, r3, #7
8001334: 4903 ldr r1, [pc, #12] @ (8001344 <HAL_RCC_GetPCLK1Freq+0x24>)
8001336: 5ccb ldrb r3, [r1, r3]
8001338: fa22 f303 lsr.w r3, r2, r3
}
800133c: 4618 mov r0, r3
800133e: bd80 pop {r7, pc}
8001340: 40021000 .word 0x40021000
8001344: 080015e8 .word 0x080015e8
08001348 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8001348: b580 push {r7, lr}
800134a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
800134c: f7ff ffde bl 800130c <HAL_RCC_GetHCLKFreq>
8001350: 4602 mov r2, r0
8001352: 4b05 ldr r3, [pc, #20] @ (8001368 <HAL_RCC_GetPCLK2Freq+0x20>)
8001354: 685b ldr r3, [r3, #4]
8001356: 0adb lsrs r3, r3, #11
8001358: f003 0307 and.w r3, r3, #7
800135c: 4903 ldr r1, [pc, #12] @ (800136c <HAL_RCC_GetPCLK2Freq+0x24>)
800135e: 5ccb ldrb r3, [r1, r3]
8001360: fa22 f303 lsr.w r3, r2, r3
}
8001364: 4618 mov r0, r3
8001366: bd80 pop {r7, pc}
8001368: 40021000 .word 0x40021000
800136c: 080015e8 .word 0x080015e8
08001370 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8001370: b480 push {r7}
8001372: b085 sub sp, #20
8001374: af00 add r7, sp, #0
8001376: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8001378: 4b0a ldr r3, [pc, #40] @ (80013a4 <RCC_Delay+0x34>)
800137a: 681b ldr r3, [r3, #0]
800137c: 4a0a ldr r2, [pc, #40] @ (80013a8 <RCC_Delay+0x38>)
800137e: fba2 2303 umull r2, r3, r2, r3
8001382: 0a5b lsrs r3, r3, #9
8001384: 687a ldr r2, [r7, #4]
8001386: fb02 f303 mul.w r3, r2, r3
800138a: 60fb str r3, [r7, #12]
do
{
__NOP();
800138c: bf00 nop
}
while (Delay --);
800138e: 68fb ldr r3, [r7, #12]
8001390: 1e5a subs r2, r3, #1
8001392: 60fa str r2, [r7, #12]
8001394: 2b00 cmp r3, #0
8001396: d1f9 bne.n 800138c <RCC_Delay+0x1c>
}
8001398: bf00 nop
800139a: bf00 nop
800139c: 3714 adds r7, #20
800139e: 46bd mov sp, r7
80013a0: bc80 pop {r7}
80013a2: 4770 bx lr
80013a4: 20000000 .word 0x20000000
80013a8: 10624dd3 .word 0x10624dd3
080013ac <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80013ac: b580 push {r7, lr}
80013ae: b082 sub sp, #8
80013b0: af00 add r7, sp, #0
80013b2: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80013b4: 687b ldr r3, [r7, #4]
80013b6: 2b00 cmp r3, #0
80013b8: d101 bne.n 80013be <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80013ba: 2301 movs r3, #1
80013bc: e042 b.n 8001444 <HAL_UART_Init+0x98>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
80013be: 687b ldr r3, [r7, #4]
80013c0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80013c4: b2db uxtb r3, r3
80013c6: 2b00 cmp r3, #0
80013c8: d106 bne.n 80013d8 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80013ca: 687b ldr r3, [r7, #4]
80013cc: 2200 movs r2, #0
80013ce: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80013d2: 6878 ldr r0, [r7, #4]
80013d4: f7fe fffe bl 80003d4 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80013d8: 687b ldr r3, [r7, #4]
80013da: 2224 movs r2, #36 @ 0x24
80013dc: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
80013e0: 687b ldr r3, [r7, #4]
80013e2: 681b ldr r3, [r3, #0]
80013e4: 68da ldr r2, [r3, #12]
80013e6: 687b ldr r3, [r7, #4]
80013e8: 681b ldr r3, [r3, #0]
80013ea: f422 5200 bic.w r2, r2, #8192 @ 0x2000
80013ee: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
80013f0: 6878 ldr r0, [r7, #4]
80013f2: f000 f82b bl 800144c <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80013f6: 687b ldr r3, [r7, #4]
80013f8: 681b ldr r3, [r3, #0]
80013fa: 691a ldr r2, [r3, #16]
80013fc: 687b ldr r3, [r7, #4]
80013fe: 681b ldr r3, [r3, #0]
8001400: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8001404: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8001406: 687b ldr r3, [r7, #4]
8001408: 681b ldr r3, [r3, #0]
800140a: 695a ldr r2, [r3, #20]
800140c: 687b ldr r3, [r7, #4]
800140e: 681b ldr r3, [r3, #0]
8001410: f022 022a bic.w r2, r2, #42 @ 0x2a
8001414: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8001416: 687b ldr r3, [r7, #4]
8001418: 681b ldr r3, [r3, #0]
800141a: 68da ldr r2, [r3, #12]
800141c: 687b ldr r3, [r7, #4]
800141e: 681b ldr r3, [r3, #0]
8001420: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8001424: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8001426: 687b ldr r3, [r7, #4]
8001428: 2200 movs r2, #0
800142a: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
800142c: 687b ldr r3, [r7, #4]
800142e: 2220 movs r2, #32
8001430: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
8001434: 687b ldr r3, [r7, #4]
8001436: 2220 movs r2, #32
8001438: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
800143c: 687b ldr r3, [r7, #4]
800143e: 2200 movs r2, #0
8001440: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
8001442: 2300 movs r3, #0
}
8001444: 4618 mov r0, r3
8001446: 3708 adds r7, #8
8001448: 46bd mov sp, r7
800144a: bd80 pop {r7, pc}
0800144c <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
800144c: b580 push {r7, lr}
800144e: b084 sub sp, #16
8001450: af00 add r7, sp, #0
8001452: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8001454: 687b ldr r3, [r7, #4]
8001456: 681b ldr r3, [r3, #0]
8001458: 691b ldr r3, [r3, #16]
800145a: f423 5140 bic.w r1, r3, #12288 @ 0x3000
800145e: 687b ldr r3, [r7, #4]
8001460: 68da ldr r2, [r3, #12]
8001462: 687b ldr r3, [r7, #4]
8001464: 681b ldr r3, [r3, #0]
8001466: 430a orrs r2, r1
8001468: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
800146a: 687b ldr r3, [r7, #4]
800146c: 689a ldr r2, [r3, #8]
800146e: 687b ldr r3, [r7, #4]
8001470: 691b ldr r3, [r3, #16]
8001472: 431a orrs r2, r3
8001474: 687b ldr r3, [r7, #4]
8001476: 695b ldr r3, [r3, #20]
8001478: 4313 orrs r3, r2
800147a: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
800147c: 687b ldr r3, [r7, #4]
800147e: 681b ldr r3, [r3, #0]
8001480: 68db ldr r3, [r3, #12]
8001482: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
8001486: f023 030c bic.w r3, r3, #12
800148a: 687a ldr r2, [r7, #4]
800148c: 6812 ldr r2, [r2, #0]
800148e: 68b9 ldr r1, [r7, #8]
8001490: 430b orrs r3, r1
8001492: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8001494: 687b ldr r3, [r7, #4]
8001496: 681b ldr r3, [r3, #0]
8001498: 695b ldr r3, [r3, #20]
800149a: f423 7140 bic.w r1, r3, #768 @ 0x300
800149e: 687b ldr r3, [r7, #4]
80014a0: 699a ldr r2, [r3, #24]
80014a2: 687b ldr r3, [r7, #4]
80014a4: 681b ldr r3, [r3, #0]
80014a6: 430a orrs r2, r1
80014a8: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
80014aa: 687b ldr r3, [r7, #4]
80014ac: 681b ldr r3, [r3, #0]
80014ae: 4a2c ldr r2, [pc, #176] @ (8001560 <UART_SetConfig+0x114>)
80014b0: 4293 cmp r3, r2
80014b2: d103 bne.n 80014bc <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
80014b4: f7ff ff48 bl 8001348 <HAL_RCC_GetPCLK2Freq>
80014b8: 60f8 str r0, [r7, #12]
80014ba: e002 b.n 80014c2 <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
80014bc: f7ff ff30 bl 8001320 <HAL_RCC_GetPCLK1Freq>
80014c0: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
80014c2: 68fa ldr r2, [r7, #12]
80014c4: 4613 mov r3, r2
80014c6: 009b lsls r3, r3, #2
80014c8: 4413 add r3, r2
80014ca: 009a lsls r2, r3, #2
80014cc: 441a add r2, r3
80014ce: 687b ldr r3, [r7, #4]
80014d0: 685b ldr r3, [r3, #4]
80014d2: 009b lsls r3, r3, #2
80014d4: fbb2 f3f3 udiv r3, r2, r3
80014d8: 4a22 ldr r2, [pc, #136] @ (8001564 <UART_SetConfig+0x118>)
80014da: fba2 2303 umull r2, r3, r2, r3
80014de: 095b lsrs r3, r3, #5
80014e0: 0119 lsls r1, r3, #4
80014e2: 68fa ldr r2, [r7, #12]
80014e4: 4613 mov r3, r2
80014e6: 009b lsls r3, r3, #2
80014e8: 4413 add r3, r2
80014ea: 009a lsls r2, r3, #2
80014ec: 441a add r2, r3
80014ee: 687b ldr r3, [r7, #4]
80014f0: 685b ldr r3, [r3, #4]
80014f2: 009b lsls r3, r3, #2
80014f4: fbb2 f2f3 udiv r2, r2, r3
80014f8: 4b1a ldr r3, [pc, #104] @ (8001564 <UART_SetConfig+0x118>)
80014fa: fba3 0302 umull r0, r3, r3, r2
80014fe: 095b lsrs r3, r3, #5
8001500: 2064 movs r0, #100 @ 0x64
8001502: fb00 f303 mul.w r3, r0, r3
8001506: 1ad3 subs r3, r2, r3
8001508: 011b lsls r3, r3, #4
800150a: 3332 adds r3, #50 @ 0x32
800150c: 4a15 ldr r2, [pc, #84] @ (8001564 <UART_SetConfig+0x118>)
800150e: fba2 2303 umull r2, r3, r2, r3
8001512: 095b lsrs r3, r3, #5
8001514: f003 03f0 and.w r3, r3, #240 @ 0xf0
8001518: 4419 add r1, r3
800151a: 68fa ldr r2, [r7, #12]
800151c: 4613 mov r3, r2
800151e: 009b lsls r3, r3, #2
8001520: 4413 add r3, r2
8001522: 009a lsls r2, r3, #2
8001524: 441a add r2, r3
8001526: 687b ldr r3, [r7, #4]
8001528: 685b ldr r3, [r3, #4]
800152a: 009b lsls r3, r3, #2
800152c: fbb2 f2f3 udiv r2, r2, r3
8001530: 4b0c ldr r3, [pc, #48] @ (8001564 <UART_SetConfig+0x118>)
8001532: fba3 0302 umull r0, r3, r3, r2
8001536: 095b lsrs r3, r3, #5
8001538: 2064 movs r0, #100 @ 0x64
800153a: fb00 f303 mul.w r3, r0, r3
800153e: 1ad3 subs r3, r2, r3
8001540: 011b lsls r3, r3, #4
8001542: 3332 adds r3, #50 @ 0x32
8001544: 4a07 ldr r2, [pc, #28] @ (8001564 <UART_SetConfig+0x118>)
8001546: fba2 2303 umull r2, r3, r2, r3
800154a: 095b lsrs r3, r3, #5
800154c: f003 020f and.w r2, r3, #15
8001550: 687b ldr r3, [r7, #4]
8001552: 681b ldr r3, [r3, #0]
8001554: 440a add r2, r1
8001556: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
8001558: bf00 nop
800155a: 3710 adds r7, #16
800155c: 46bd mov sp, r7
800155e: bd80 pop {r7, pc}
8001560: 40013800 .word 0x40013800
8001564: 51eb851f .word 0x51eb851f
08001568 <memset>:
8001568: 4603 mov r3, r0
800156a: 4402 add r2, r0
800156c: 4293 cmp r3, r2
800156e: d100 bne.n 8001572 <memset+0xa>
8001570: 4770 bx lr
8001572: f803 1b01 strb.w r1, [r3], #1
8001576: e7f9 b.n 800156c <memset+0x4>
08001578 <__libc_init_array>:
8001578: b570 push {r4, r5, r6, lr}
800157a: 2600 movs r6, #0
800157c: 4d0c ldr r5, [pc, #48] @ (80015b0 <__libc_init_array+0x38>)
800157e: 4c0d ldr r4, [pc, #52] @ (80015b4 <__libc_init_array+0x3c>)
8001580: 1b64 subs r4, r4, r5
8001582: 10a4 asrs r4, r4, #2
8001584: 42a6 cmp r6, r4
8001586: d109 bne.n 800159c <__libc_init_array+0x24>
8001588: f000 f81a bl 80015c0 <_init>
800158c: 2600 movs r6, #0
800158e: 4d0a ldr r5, [pc, #40] @ (80015b8 <__libc_init_array+0x40>)
8001590: 4c0a ldr r4, [pc, #40] @ (80015bc <__libc_init_array+0x44>)
8001592: 1b64 subs r4, r4, r5
8001594: 10a4 asrs r4, r4, #2
8001596: 42a6 cmp r6, r4
8001598: d105 bne.n 80015a6 <__libc_init_array+0x2e>
800159a: bd70 pop {r4, r5, r6, pc}
800159c: f855 3b04 ldr.w r3, [r5], #4
80015a0: 4798 blx r3
80015a2: 3601 adds r6, #1
80015a4: e7ee b.n 8001584 <__libc_init_array+0xc>
80015a6: f855 3b04 ldr.w r3, [r5], #4
80015aa: 4798 blx r3
80015ac: 3601 adds r6, #1
80015ae: e7f2 b.n 8001596 <__libc_init_array+0x1e>
80015b0: 08001604 .word 0x08001604
80015b4: 08001604 .word 0x08001604
80015b8: 08001604 .word 0x08001604
80015bc: 08001608 .word 0x08001608
080015c0 <_init>:
80015c0: b5f8 push {r3, r4, r5, r6, r7, lr}
80015c2: bf00 nop
80015c4: bcf8 pop {r3, r4, r5, r6, r7}
80015c6: bc08 pop {r3}
80015c8: 469e mov lr, r3
80015ca: 4770 bx lr
080015cc <_fini>:
80015cc: b5f8 push {r3, r4, r5, r6, r7, lr}
80015ce: bf00 nop
80015d0: bcf8 pop {r3, r4, r5, r6, r7}
80015d2: bc08 pop {r3}
80015d4: 469e mov lr, r3
80015d6: 4770 bx lr
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