Gallardo7761/setr1-monorepo
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setr1-monorepo/P6_SETR1/Debug/P6_SETR1.list
Jose 85e60bcc39 monorepo
2025-10-10 02:20:31 +02:00

22540 lines
806 KiB
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P6_SETR1.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00007f64 08000188 08000188 00001188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000a0 080080ec 080080ec 000090ec 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800818c 0800818c 0000a12c 2**0
CONTENTS, READONLY
4 .ARM 00000000 0800818c 0800818c 0000a12c 2**0
CONTENTS, READONLY
5 .preinit_array 00000000 0800818c 0800818c 0000a12c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800818c 0800818c 0000918c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08008190 08008190 00009190 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000012c 20000000 08008194 0000a000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000a54 2000012c 080082c0 0000a12c 2**2
ALLOC
10 ._user_heap_stack 00000600 20000b80 080082c0 0000ab80 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000a12c 2**0
CONTENTS, READONLY
12 .debug_info 00012fd8 00000000 00000000 0000a15c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003580 00000000 00000000 0001d134 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000010d0 00000000 00000000 000206b8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000ca4 00000000 00000000 00021788 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00028215 00000000 00000000 0002242c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00015067 00000000 00000000 0004a641 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000e7c77 00000000 00000000 0005f6a8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 0014731f 2**0
CONTENTS, READONLY
20 .debug_frame 000043f4 00000000 00000000 00147364 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000061 00000000 00000000 0014b758 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000012c .word 0x2000012c
80001a4: 00000000 .word 0x00000000
80001a8: 080080d4 .word 0x080080d4
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000130 .word 0x20000130
80001c4: 080080d4 .word 0x080080d4
080001c8 <LSM6DSL_Init>:
#include "LSM6DSL.h"
extern I2C_HandleTypeDef hi2c2;
void LSM6DSL_Init(void)
{
80001c8: b580 push {r7, lr}
80001ca: b086 sub sp, #24
80001cc: af04 add r7, sp, #16
uint8_t buffer[1];
buffer[0] = 0x40;
80001ce: 2340 movs r3, #64 @ 0x40
80001d0: 713b strb r3, [r7, #4]
HAL_I2C_Mem_Write(&hi2c2, 0xD4, 0x10,
80001d2: f44f 737a mov.w r3, #1000 @ 0x3e8
80001d6: 9302 str r3, [sp, #8]
80001d8: 2301 movs r3, #1
80001da: 9301 str r3, [sp, #4]
80001dc: 1d3b adds r3, r7, #4
80001de: 9300 str r3, [sp, #0]
80001e0: 2301 movs r3, #1
80001e2: 2210 movs r2, #16
80001e4: 21d4 movs r1, #212 @ 0xd4
80001e6: 4803 ldr r0, [pc, #12] @ (80001f4 <LSM6DSL_Init+0x2c>)
80001e8: f000 fe20 bl 8000e2c <HAL_I2C_Mem_Write>
I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000);
}
80001ec: bf00 nop
80001ee: 3708 adds r7, #8
80001f0: 46bd mov sp, r7
80001f2: bd80 pop {r7, pc}
80001f4: 20000148 .word 0x20000148
080001f8 <LSM6DSL_ReadAccel>:
int16_t LSM6DSL_ReadAccel(uint8_t axis)
{
80001f8: b580 push {r7, lr}
80001fa: b088 sub sp, #32
80001fc: af04 add r7, sp, #16
80001fe: 4603 mov r3, r0
8000200: 71fb strb r3, [r7, #7]
uint8_t buffer[2];
HAL_I2C_Mem_Read(&hi2c2, 0xD4, 0x28+2*axis,
8000202: 79fb ldrb r3, [r7, #7]
8000204: 3314 adds r3, #20
8000206: b29b uxth r3, r3
8000208: 005b lsls r3, r3, #1
800020a: b29a uxth r2, r3
800020c: f44f 737a mov.w r3, #1000 @ 0x3e8
8000210: 9302 str r3, [sp, #8]
8000212: 2302 movs r3, #2
8000214: 9301 str r3, [sp, #4]
8000216: f107 030c add.w r3, r7, #12
800021a: 9300 str r3, [sp, #0]
800021c: 2301 movs r3, #1
800021e: 21d4 movs r1, #212 @ 0xd4
8000220: 480d ldr r0, [pc, #52] @ (8000258 <LSM6DSL_ReadAccel+0x60>)
8000222: f000 ff17 bl 8001054 <HAL_I2C_Mem_Read>
I2C_MEMADD_SIZE_8BIT, buffer, 2, 1000);
return ((int16_t)(buffer[1]<<8) | buffer[0]) * 0.061f;
8000226: 7b7b ldrb r3, [r7, #13]
8000228: b21b sxth r3, r3
800022a: 021b lsls r3, r3, #8
800022c: b21b sxth r3, r3
800022e: 461a mov r2, r3
8000230: 7b3b ldrb r3, [r7, #12]
8000232: 4313 orrs r3, r2
8000234: ee07 3a90 vmov s15, r3
8000238: eef8 7ae7 vcvt.f32.s32 s15, s15
800023c: ed9f 7a07 vldr s14, [pc, #28] @ 800025c <LSM6DSL_ReadAccel+0x64>
8000240: ee67 7a87 vmul.f32 s15, s15, s14
8000244: eefd 7ae7 vcvt.s32.f32 s15, s15
8000248: ee17 3a90 vmov r3, s15
800024c: b21b sxth r3, r3
}
800024e: 4618 mov r0, r3
8000250: 3710 adds r7, #16
8000252: 46bd mov sp, r7
8000254: bd80 pop {r7, pc}
8000256: bf00 nop
8000258: 20000148 .word 0x20000148
800025c: 3d79db23 .word 0x3d79db23
08000260 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000260: b580 push {r7, lr}
8000262: b084 sub sp, #16
8000264: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000266: f000 f9f0 bl 800064a <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800026a: f000 f83b bl 80002e4 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800026e: f000 f8cb bl 8000408 <MX_GPIO_Init>
MX_USB_DEVICE_Init();
8000272: f007 f94b bl 800750c <MX_USB_DEVICE_Init>
MX_I2C2_Init();
8000276: f000 f887 bl 8000388 <MX_I2C2_Init>
/* USER CODE BEGIN 2 */
LSM6DSL_Init();
800027a: f7ff ffa5 bl 80001c8 <LSM6DSL_Init>
HAL_Delay(5000);
800027e: f241 3088 movw r0, #5000 @ 0x1388
8000282: f000 fa57 bl 8000734 <HAL_Delay>
data[0] = 0;
8000286: 2300 movs r3, #0
8000288: 713b strb r3, [r7, #4]
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
int16_t yValue = LSM6DSL_ReadAccel(Y_AXIS);
800028a: 2001 movs r0, #1
800028c: f7ff ffb4 bl 80001f8 <LSM6DSL_ReadAccel>
8000290: 4603 mov r3, r0
8000292: 81fb strh r3, [r7, #14]
int16_t xValue = LSM6DSL_ReadAccel(X_AXIS);
8000294: 2000 movs r0, #0
8000296: f7ff ffaf bl 80001f8 <LSM6DSL_ReadAccel>
800029a: 4603 mov r3, r0
800029c: 81bb strh r3, [r7, #12]
data[1] = xValue/100; // X
800029e: f9b7 300c ldrsh.w r3, [r7, #12]
80002a2: 4a0f ldr r2, [pc, #60] @ (80002e0 <main+0x80>)
80002a4: fb82 1203 smull r1, r2, r2, r3
80002a8: 1152 asrs r2, r2, #5
80002aa: 17db asrs r3, r3, #31
80002ac: 1ad3 subs r3, r2, r3
80002ae: b21b sxth r3, r3
80002b0: b2db uxtb r3, r3
80002b2: 717b strb r3, [r7, #5]
data[2] = yValue/100; // Y
80002b4: f9b7 300e ldrsh.w r3, [r7, #14]
80002b8: 4a09 ldr r2, [pc, #36] @ (80002e0 <main+0x80>)
80002ba: fb82 1203 smull r1, r2, r2, r3
80002be: 1152 asrs r2, r2, #5
80002c0: 17db asrs r3, r3, #31
80002c2: 1ad3 subs r3, r2, r3
80002c4: b21b sxth r3, r3
80002c6: b2db uxtb r3, r3
80002c8: 71bb strb r3, [r7, #6]
USBD_CUSTOM_HID_SendReport_FS(data, 3);
80002ca: 1d3b adds r3, r7, #4
80002cc: 2103 movs r1, #3
80002ce: 4618 mov r0, r3
80002d0: f007 f96e bl 80075b0 <USBD_CUSTOM_HID_SendReport_FS>
HAL_Delay(10);
80002d4: 200a movs r0, #10
80002d6: f000 fa2d bl 8000734 <HAL_Delay>
{
80002da: bf00 nop
80002dc: e7d5 b.n 800028a <main+0x2a>
80002de: bf00 nop
80002e0: 51eb851f .word 0x51eb851f
080002e4 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80002e4: b580 push {r7, lr}
80002e6: b096 sub sp, #88 @ 0x58
80002e8: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80002ea: f107 0314 add.w r3, r7, #20
80002ee: 2244 movs r2, #68 @ 0x44
80002f0: 2100 movs r1, #0
80002f2: 4618 mov r0, r3
80002f4: f007 fec2 bl 800807c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80002f8: 463b mov r3, r7
80002fa: 2200 movs r2, #0
80002fc: 601a str r2, [r3, #0]
80002fe: 605a str r2, [r3, #4]
8000300: 609a str r2, [r3, #8]
8000302: 60da str r2, [r3, #12]
8000304: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
8000306: f44f 7000 mov.w r0, #512 @ 0x200
800030a: f002 fca3 bl 8002c54 <HAL_PWREx_ControlVoltageScaling>
800030e: 4603 mov r3, r0
8000310: 2b00 cmp r3, #0
8000312: d001 beq.n 8000318 <SystemClock_Config+0x34>
{
Error_Handler();
8000314: f000 f89c bl 8000450 <Error_Handler>
}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
8000318: 2310 movs r3, #16
800031a: 617b str r3, [r7, #20]
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
800031c: 2301 movs r3, #1
800031e: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.MSICalibrationValue = 0;
8000320: 2300 movs r3, #0
8000322: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
8000324: 2360 movs r3, #96 @ 0x60
8000326: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000328: 2302 movs r3, #2
800032a: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
800032c: 2301 movs r3, #1
800032e: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLM = 1;
8000330: 2301 movs r3, #1
8000332: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLN = 40;
8000334: 2328 movs r3, #40 @ 0x28
8000336: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
8000338: 2307 movs r3, #7
800033a: 64fb str r3, [r7, #76] @ 0x4c
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
800033c: 2302 movs r3, #2
800033e: 653b str r3, [r7, #80] @ 0x50
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
8000340: 2302 movs r3, #2
8000342: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000344: f107 0314 add.w r3, r7, #20
8000348: 4618 mov r0, r3
800034a: f002 fce9 bl 8002d20 <HAL_RCC_OscConfig>
800034e: 4603 mov r3, r0
8000350: 2b00 cmp r3, #0
8000352: d001 beq.n 8000358 <SystemClock_Config+0x74>
{
Error_Handler();
8000354: f000 f87c bl 8000450 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000358: 230f movs r3, #15
800035a: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
800035c: 2303 movs r3, #3
800035e: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000360: 2300 movs r3, #0
8000362: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000364: 2300 movs r3, #0
8000366: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000368: 2300 movs r3, #0
800036a: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
800036c: 463b mov r3, r7
800036e: 2104 movs r1, #4
8000370: 4618 mov r0, r3
8000372: f003 f8b1 bl 80034d8 <HAL_RCC_ClockConfig>
8000376: 4603 mov r3, r0
8000378: 2b00 cmp r3, #0
800037a: d001 beq.n 8000380 <SystemClock_Config+0x9c>
{
Error_Handler();
800037c: f000 f868 bl 8000450 <Error_Handler>
}
}
8000380: bf00 nop
8000382: 3758 adds r7, #88 @ 0x58
8000384: 46bd mov sp, r7
8000386: bd80 pop {r7, pc}
08000388 <MX_I2C2_Init>:
* @brief I2C2 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C2_Init(void)
{
8000388: b580 push {r7, lr}
800038a: af00 add r7, sp, #0
/* USER CODE END I2C2_Init 0 */
/* USER CODE BEGIN I2C2_Init 1 */
/* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2;
800038c: 4b1b ldr r3, [pc, #108] @ (80003fc <MX_I2C2_Init+0x74>)
800038e: 4a1c ldr r2, [pc, #112] @ (8000400 <MX_I2C2_Init+0x78>)
8000390: 601a str r2, [r3, #0]
hi2c2.Init.Timing = 0x10D19CE4;
8000392: 4b1a ldr r3, [pc, #104] @ (80003fc <MX_I2C2_Init+0x74>)
8000394: 4a1b ldr r2, [pc, #108] @ (8000404 <MX_I2C2_Init+0x7c>)
8000396: 605a str r2, [r3, #4]
hi2c2.Init.OwnAddress1 = 0;
8000398: 4b18 ldr r3, [pc, #96] @ (80003fc <MX_I2C2_Init+0x74>)
800039a: 2200 movs r2, #0
800039c: 609a str r2, [r3, #8]
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
800039e: 4b17 ldr r3, [pc, #92] @ (80003fc <MX_I2C2_Init+0x74>)
80003a0: 2201 movs r2, #1
80003a2: 60da str r2, [r3, #12]
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80003a4: 4b15 ldr r3, [pc, #84] @ (80003fc <MX_I2C2_Init+0x74>)
80003a6: 2200 movs r2, #0
80003a8: 611a str r2, [r3, #16]
hi2c2.Init.OwnAddress2 = 0;
80003aa: 4b14 ldr r3, [pc, #80] @ (80003fc <MX_I2C2_Init+0x74>)
80003ac: 2200 movs r2, #0
80003ae: 615a str r2, [r3, #20]
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
80003b0: 4b12 ldr r3, [pc, #72] @ (80003fc <MX_I2C2_Init+0x74>)
80003b2: 2200 movs r2, #0
80003b4: 619a str r2, [r3, #24]
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
80003b6: 4b11 ldr r3, [pc, #68] @ (80003fc <MX_I2C2_Init+0x74>)
80003b8: 2200 movs r2, #0
80003ba: 61da str r2, [r3, #28]
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80003bc: 4b0f ldr r3, [pc, #60] @ (80003fc <MX_I2C2_Init+0x74>)
80003be: 2200 movs r2, #0
80003c0: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
80003c2: 480e ldr r0, [pc, #56] @ (80003fc <MX_I2C2_Init+0x74>)
80003c4: f000 fc96 bl 8000cf4 <HAL_I2C_Init>
80003c8: 4603 mov r3, r0
80003ca: 2b00 cmp r3, #0
80003cc: d001 beq.n 80003d2 <MX_I2C2_Init+0x4a>
{
Error_Handler();
80003ce: f000 f83f bl 8000450 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
80003d2: 2100 movs r1, #0
80003d4: 4809 ldr r0, [pc, #36] @ (80003fc <MX_I2C2_Init+0x74>)
80003d6: f001 fa19 bl 800180c <HAL_I2CEx_ConfigAnalogFilter>
80003da: 4603 mov r3, r0
80003dc: 2b00 cmp r3, #0
80003de: d001 beq.n 80003e4 <MX_I2C2_Init+0x5c>
{
Error_Handler();
80003e0: f000 f836 bl 8000450 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
80003e4: 2100 movs r1, #0
80003e6: 4805 ldr r0, [pc, #20] @ (80003fc <MX_I2C2_Init+0x74>)
80003e8: f001 fa5b bl 80018a2 <HAL_I2CEx_ConfigDigitalFilter>
80003ec: 4603 mov r3, r0
80003ee: 2b00 cmp r3, #0
80003f0: d001 beq.n 80003f6 <MX_I2C2_Init+0x6e>
{
Error_Handler();
80003f2: f000 f82d bl 8000450 <Error_Handler>
}
/* USER CODE BEGIN I2C2_Init 2 */
/* USER CODE END I2C2_Init 2 */
}
80003f6: bf00 nop
80003f8: bd80 pop {r7, pc}
80003fa: bf00 nop
80003fc: 20000148 .word 0x20000148
8000400: 40005800 .word 0x40005800
8000404: 10d19ce4 .word 0x10d19ce4
08000408 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000408: b480 push {r7}
800040a: b083 sub sp, #12
800040c: af00 add r7, sp, #0
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOB_CLK_ENABLE();
800040e: 4b0f ldr r3, [pc, #60] @ (800044c <MX_GPIO_Init+0x44>)
8000410: 6cdb ldr r3, [r3, #76] @ 0x4c
8000412: 4a0e ldr r2, [pc, #56] @ (800044c <MX_GPIO_Init+0x44>)
8000414: f043 0302 orr.w r3, r3, #2
8000418: 64d3 str r3, [r2, #76] @ 0x4c
800041a: 4b0c ldr r3, [pc, #48] @ (800044c <MX_GPIO_Init+0x44>)
800041c: 6cdb ldr r3, [r3, #76] @ 0x4c
800041e: f003 0302 and.w r3, r3, #2
8000422: 607b str r3, [r7, #4]
8000424: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000426: 4b09 ldr r3, [pc, #36] @ (800044c <MX_GPIO_Init+0x44>)
8000428: 6cdb ldr r3, [r3, #76] @ 0x4c
800042a: 4a08 ldr r2, [pc, #32] @ (800044c <MX_GPIO_Init+0x44>)
800042c: f043 0301 orr.w r3, r3, #1
8000430: 64d3 str r3, [r2, #76] @ 0x4c
8000432: 4b06 ldr r3, [pc, #24] @ (800044c <MX_GPIO_Init+0x44>)
8000434: 6cdb ldr r3, [r3, #76] @ 0x4c
8000436: f003 0301 and.w r3, r3, #1
800043a: 603b str r3, [r7, #0]
800043c: 683b ldr r3, [r7, #0]
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
800043e: bf00 nop
8000440: 370c adds r7, #12
8000442: 46bd mov sp, r7
8000444: f85d 7b04 ldr.w r7, [sp], #4
8000448: 4770 bx lr
800044a: bf00 nop
800044c: 40021000 .word 0x40021000
08000450 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000450: b480 push {r7}
8000452: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000454: b672 cpsid i
}
8000456: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000458: bf00 nop
800045a: e7fd b.n 8000458 <Error_Handler+0x8>
0800045c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800045c: b480 push {r7}
800045e: b083 sub sp, #12
8000460: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000462: 4b0f ldr r3, [pc, #60] @ (80004a0 <HAL_MspInit+0x44>)
8000464: 6e1b ldr r3, [r3, #96] @ 0x60
8000466: 4a0e ldr r2, [pc, #56] @ (80004a0 <HAL_MspInit+0x44>)
8000468: f043 0301 orr.w r3, r3, #1
800046c: 6613 str r3, [r2, #96] @ 0x60
800046e: 4b0c ldr r3, [pc, #48] @ (80004a0 <HAL_MspInit+0x44>)
8000470: 6e1b ldr r3, [r3, #96] @ 0x60
8000472: f003 0301 and.w r3, r3, #1
8000476: 607b str r3, [r7, #4]
8000478: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800047a: 4b09 ldr r3, [pc, #36] @ (80004a0 <HAL_MspInit+0x44>)
800047c: 6d9b ldr r3, [r3, #88] @ 0x58
800047e: 4a08 ldr r2, [pc, #32] @ (80004a0 <HAL_MspInit+0x44>)
8000480: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000484: 6593 str r3, [r2, #88] @ 0x58
8000486: 4b06 ldr r3, [pc, #24] @ (80004a0 <HAL_MspInit+0x44>)
8000488: 6d9b ldr r3, [r3, #88] @ 0x58
800048a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800048e: 603b str r3, [r7, #0]
8000490: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000492: bf00 nop
8000494: 370c adds r7, #12
8000496: 46bd mov sp, r7
8000498: f85d 7b04 ldr.w r7, [sp], #4
800049c: 4770 bx lr
800049e: bf00 nop
80004a0: 40021000 .word 0x40021000
080004a4 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
80004a4: b580 push {r7, lr}
80004a6: b0ac sub sp, #176 @ 0xb0
80004a8: af00 add r7, sp, #0
80004aa: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80004ac: f107 039c add.w r3, r7, #156 @ 0x9c
80004b0: 2200 movs r2, #0
80004b2: 601a str r2, [r3, #0]
80004b4: 605a str r2, [r3, #4]
80004b6: 609a str r2, [r3, #8]
80004b8: 60da str r2, [r3, #12]
80004ba: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
80004bc: f107 0314 add.w r3, r7, #20
80004c0: 2288 movs r2, #136 @ 0x88
80004c2: 2100 movs r1, #0
80004c4: 4618 mov r0, r3
80004c6: f007 fdd9 bl 800807c <memset>
if(hi2c->Instance==I2C2)
80004ca: 687b ldr r3, [r7, #4]
80004cc: 681b ldr r3, [r3, #0]
80004ce: 4a21 ldr r2, [pc, #132] @ (8000554 <HAL_I2C_MspInit+0xb0>)
80004d0: 4293 cmp r3, r2
80004d2: d13b bne.n 800054c <HAL_I2C_MspInit+0xa8>
/* USER CODE END I2C2_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
80004d4: 2380 movs r3, #128 @ 0x80
80004d6: 617b str r3, [r7, #20]
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
80004d8: 2300 movs r3, #0
80004da: 66bb str r3, [r7, #104] @ 0x68
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80004dc: f107 0314 add.w r3, r7, #20
80004e0: 4618 mov r0, r3
80004e2: f003 f9f1 bl 80038c8 <HAL_RCCEx_PeriphCLKConfig>
80004e6: 4603 mov r3, r0
80004e8: 2b00 cmp r3, #0
80004ea: d001 beq.n 80004f0 <HAL_I2C_MspInit+0x4c>
{
Error_Handler();
80004ec: f7ff ffb0 bl 8000450 <Error_Handler>
}
__HAL_RCC_GPIOB_CLK_ENABLE();
80004f0: 4b19 ldr r3, [pc, #100] @ (8000558 <HAL_I2C_MspInit+0xb4>)
80004f2: 6cdb ldr r3, [r3, #76] @ 0x4c
80004f4: 4a18 ldr r2, [pc, #96] @ (8000558 <HAL_I2C_MspInit+0xb4>)
80004f6: f043 0302 orr.w r3, r3, #2
80004fa: 64d3 str r3, [r2, #76] @ 0x4c
80004fc: 4b16 ldr r3, [pc, #88] @ (8000558 <HAL_I2C_MspInit+0xb4>)
80004fe: 6cdb ldr r3, [r3, #76] @ 0x4c
8000500: f003 0302 and.w r3, r3, #2
8000504: 613b str r3, [r7, #16]
8000506: 693b ldr r3, [r7, #16]
/**I2C2 GPIO Configuration
PB10 ------> I2C2_SCL
PB11 ------> I2C2_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
8000508: f44f 6340 mov.w r3, #3072 @ 0xc00
800050c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000510: 2312 movs r3, #18
8000512: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000516: 2300 movs r3, #0
8000518: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800051c: 2303 movs r3, #3
800051e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
8000522: 2304 movs r3, #4
8000524: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000528: f107 039c add.w r3, r7, #156 @ 0x9c
800052c: 4619 mov r1, r3
800052e: 480b ldr r0, [pc, #44] @ (800055c <HAL_I2C_MspInit+0xb8>)
8000530: f000 fa36 bl 80009a0 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C2_CLK_ENABLE();
8000534: 4b08 ldr r3, [pc, #32] @ (8000558 <HAL_I2C_MspInit+0xb4>)
8000536: 6d9b ldr r3, [r3, #88] @ 0x58
8000538: 4a07 ldr r2, [pc, #28] @ (8000558 <HAL_I2C_MspInit+0xb4>)
800053a: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
800053e: 6593 str r3, [r2, #88] @ 0x58
8000540: 4b05 ldr r3, [pc, #20] @ (8000558 <HAL_I2C_MspInit+0xb4>)
8000542: 6d9b ldr r3, [r3, #88] @ 0x58
8000544: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8000548: 60fb str r3, [r7, #12]
800054a: 68fb ldr r3, [r7, #12]
/* USER CODE END I2C2_MspInit 1 */
}
}
800054c: bf00 nop
800054e: 37b0 adds r7, #176 @ 0xb0
8000550: 46bd mov sp, r7
8000552: bd80 pop {r7, pc}
8000554: 40005800 .word 0x40005800
8000558: 40021000 .word 0x40021000
800055c: 48000400 .word 0x48000400
08000560 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000560: b480 push {r7}
8000562: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000564: bf00 nop
8000566: e7fd b.n 8000564 <NMI_Handler+0x4>
08000568 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000568: b480 push {r7}
800056a: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800056c: bf00 nop
800056e: e7fd b.n 800056c <HardFault_Handler+0x4>
08000570 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000570: b480 push {r7}
8000572: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000574: bf00 nop
8000576: e7fd b.n 8000574 <MemManage_Handler+0x4>
08000578 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000578: b480 push {r7}
800057a: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800057c: bf00 nop
800057e: e7fd b.n 800057c <BusFault_Handler+0x4>
08000580 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000580: b480 push {r7}
8000582: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000584: bf00 nop
8000586: e7fd b.n 8000584 <UsageFault_Handler+0x4>
08000588 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000588: b480 push {r7}
800058a: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800058c: bf00 nop
800058e: 46bd mov sp, r7
8000590: f85d 7b04 ldr.w r7, [sp], #4
8000594: 4770 bx lr
08000596 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000596: b480 push {r7}
8000598: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800059a: bf00 nop
800059c: 46bd mov sp, r7
800059e: f85d 7b04 ldr.w r7, [sp], #4
80005a2: 4770 bx lr
080005a4 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80005a4: b480 push {r7}
80005a6: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80005a8: bf00 nop
80005aa: 46bd mov sp, r7
80005ac: f85d 7b04 ldr.w r7, [sp], #4
80005b0: 4770 bx lr
080005b2 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80005b2: b580 push {r7, lr}
80005b4: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80005b6: f000 f89d bl 80006f4 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80005ba: bf00 nop
80005bc: bd80 pop {r7, pc}
...
080005c0 <OTG_FS_IRQHandler>:
/**
* @brief This function handles USB OTG FS global interrupt.
*/
void OTG_FS_IRQHandler(void)
{
80005c0: b580 push {r7, lr}
80005c2: af00 add r7, sp, #0
/* USER CODE BEGIN OTG_FS_IRQn 0 */
/* USER CODE END OTG_FS_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
80005c4: 4802 ldr r0, [pc, #8] @ (80005d0 <OTG_FS_IRQHandler+0x10>)
80005c6: f001 faf6 bl 8001bb6 <HAL_PCD_IRQHandler>
/* USER CODE BEGIN OTG_FS_IRQn 1 */
/* USER CODE END OTG_FS_IRQn 1 */
}
80005ca: bf00 nop
80005cc: bd80 pop {r7, pc}
80005ce: bf00 nop
80005d0: 20000680 .word 0x20000680
080005d4 <SystemInit>:
* @brief Setup the microcontroller system.
* @retval None
*/
void SystemInit(void)
{
80005d4: b480 push {r7}
80005d6: af00 add r7, sp, #0
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
80005d8: 4b06 ldr r3, [pc, #24] @ (80005f4 <SystemInit+0x20>)
80005da: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80005de: 4a05 ldr r2, [pc, #20] @ (80005f4 <SystemInit+0x20>)
80005e0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80005e4: f8c2 3088 str.w r3, [r2, #136] @ 0x88
#endif
}
80005e8: bf00 nop
80005ea: 46bd mov sp, r7
80005ec: f85d 7b04 ldr.w r7, [sp], #4
80005f0: 4770 bx lr
80005f2: bf00 nop
80005f4: e000ed00 .word 0xe000ed00
080005f8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
80005f8: f8df d034 ldr.w sp, [pc, #52] @ 8000630 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
80005fc: f7ff ffea bl 80005d4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000600: 480c ldr r0, [pc, #48] @ (8000634 <LoopForever+0x6>)
ldr r1, =_edata
8000602: 490d ldr r1, [pc, #52] @ (8000638 <LoopForever+0xa>)
ldr r2, =_sidata
8000604: 4a0d ldr r2, [pc, #52] @ (800063c <LoopForever+0xe>)
movs r3, #0
8000606: 2300 movs r3, #0
b LoopCopyDataInit
8000608: e002 b.n 8000610 <LoopCopyDataInit>
0800060a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800060a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
800060c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800060e: 3304 adds r3, #4
08000610 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000610: 18c4 adds r4, r0, r3
cmp r4, r1
8000612: 428c cmp r4, r1
bcc CopyDataInit
8000614: d3f9 bcc.n 800060a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000616: 4a0a ldr r2, [pc, #40] @ (8000640 <LoopForever+0x12>)
ldr r4, =_ebss
8000618: 4c0a ldr r4, [pc, #40] @ (8000644 <LoopForever+0x16>)
movs r3, #0
800061a: 2300 movs r3, #0
b LoopFillZerobss
800061c: e001 b.n 8000622 <LoopFillZerobss>
0800061e <FillZerobss>:
FillZerobss:
str r3, [r2]
800061e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000620: 3204 adds r2, #4
08000622 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000622: 42a2 cmp r2, r4
bcc FillZerobss
8000624: d3fb bcc.n 800061e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000626: f007 fd31 bl 800808c <__libc_init_array>
/* Call the application's entry point.*/
bl main
800062a: f7ff fe19 bl 8000260 <main>
0800062e <LoopForever>:
LoopForever:
b LoopForever
800062e: e7fe b.n 800062e <LoopForever>
ldr sp, =_estack /* Set stack pointer */
8000630: 20018000 .word 0x20018000
ldr r0, =_sdata
8000634: 20000000 .word 0x20000000
ldr r1, =_edata
8000638: 2000012c .word 0x2000012c
ldr r2, =_sidata
800063c: 08008194 .word 0x08008194
ldr r2, =_sbss
8000640: 2000012c .word 0x2000012c
ldr r4, =_ebss
8000644: 20000b80 .word 0x20000b80
08000648 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000648: e7fe b.n 8000648 <ADC1_2_IRQHandler>
0800064a <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800064a: b580 push {r7, lr}
800064c: b082 sub sp, #8
800064e: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8000650: 2300 movs r3, #0
8000652: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000654: 2003 movs r0, #3
8000656: f000 f961 bl 800091c <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
800065a: 200f movs r0, #15
800065c: f000 f80e bl 800067c <HAL_InitTick>
8000660: 4603 mov r3, r0
8000662: 2b00 cmp r3, #0
8000664: d002 beq.n 800066c <HAL_Init+0x22>
{
status = HAL_ERROR;
8000666: 2301 movs r3, #1
8000668: 71fb strb r3, [r7, #7]
800066a: e001 b.n 8000670 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
800066c: f7ff fef6 bl 800045c <HAL_MspInit>
}
/* Return function status */
return status;
8000670: 79fb ldrb r3, [r7, #7]
}
8000672: 4618 mov r0, r3
8000674: 3708 adds r7, #8
8000676: 46bd mov sp, r7
8000678: bd80 pop {r7, pc}
...
0800067c <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
800067c: b580 push {r7, lr}
800067e: b084 sub sp, #16
8000680: af00 add r7, sp, #0
8000682: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000684: 2300 movs r3, #0
8000686: 73fb strb r3, [r7, #15]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8000688: 4b17 ldr r3, [pc, #92] @ (80006e8 <HAL_InitTick+0x6c>)
800068a: 781b ldrb r3, [r3, #0]
800068c: 2b00 cmp r3, #0
800068e: d023 beq.n 80006d8 <HAL_InitTick+0x5c>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
8000690: 4b16 ldr r3, [pc, #88] @ (80006ec <HAL_InitTick+0x70>)
8000692: 681a ldr r2, [r3, #0]
8000694: 4b14 ldr r3, [pc, #80] @ (80006e8 <HAL_InitTick+0x6c>)
8000696: 781b ldrb r3, [r3, #0]
8000698: 4619 mov r1, r3
800069a: f44f 737a mov.w r3, #1000 @ 0x3e8
800069e: fbb3 f3f1 udiv r3, r3, r1
80006a2: fbb2 f3f3 udiv r3, r2, r3
80006a6: 4618 mov r0, r3
80006a8: f000 f96d bl 8000986 <HAL_SYSTICK_Config>
80006ac: 4603 mov r3, r0
80006ae: 2b00 cmp r3, #0
80006b0: d10f bne.n 80006d2 <HAL_InitTick+0x56>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80006b2: 687b ldr r3, [r7, #4]
80006b4: 2b0f cmp r3, #15
80006b6: d809 bhi.n 80006cc <HAL_InitTick+0x50>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80006b8: 2200 movs r2, #0
80006ba: 6879 ldr r1, [r7, #4]
80006bc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80006c0: f000 f937 bl 8000932 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80006c4: 4a0a ldr r2, [pc, #40] @ (80006f0 <HAL_InitTick+0x74>)
80006c6: 687b ldr r3, [r7, #4]
80006c8: 6013 str r3, [r2, #0]
80006ca: e007 b.n 80006dc <HAL_InitTick+0x60>
}
else
{
status = HAL_ERROR;
80006cc: 2301 movs r3, #1
80006ce: 73fb strb r3, [r7, #15]
80006d0: e004 b.n 80006dc <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
80006d2: 2301 movs r3, #1
80006d4: 73fb strb r3, [r7, #15]
80006d6: e001 b.n 80006dc <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
80006d8: 2301 movs r3, #1
80006da: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
80006dc: 7bfb ldrb r3, [r7, #15]
}
80006de: 4618 mov r0, r3
80006e0: 3710 adds r7, #16
80006e2: 46bd mov sp, r7
80006e4: bd80 pop {r7, pc}
80006e6: bf00 nop
80006e8: 20000008 .word 0x20000008
80006ec: 20000000 .word 0x20000000
80006f0: 20000004 .word 0x20000004
080006f4 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80006f4: b480 push {r7}
80006f6: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
80006f8: 4b06 ldr r3, [pc, #24] @ (8000714 <HAL_IncTick+0x20>)
80006fa: 781b ldrb r3, [r3, #0]
80006fc: 461a mov r2, r3
80006fe: 4b06 ldr r3, [pc, #24] @ (8000718 <HAL_IncTick+0x24>)
8000700: 681b ldr r3, [r3, #0]
8000702: 4413 add r3, r2
8000704: 4a04 ldr r2, [pc, #16] @ (8000718 <HAL_IncTick+0x24>)
8000706: 6013 str r3, [r2, #0]
}
8000708: bf00 nop
800070a: 46bd mov sp, r7
800070c: f85d 7b04 ldr.w r7, [sp], #4
8000710: 4770 bx lr
8000712: bf00 nop
8000714: 20000008 .word 0x20000008
8000718: 2000019c .word 0x2000019c
0800071c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800071c: b480 push {r7}
800071e: af00 add r7, sp, #0
return uwTick;
8000720: 4b03 ldr r3, [pc, #12] @ (8000730 <HAL_GetTick+0x14>)
8000722: 681b ldr r3, [r3, #0]
}
8000724: 4618 mov r0, r3
8000726: 46bd mov sp, r7
8000728: f85d 7b04 ldr.w r7, [sp], #4
800072c: 4770 bx lr
800072e: bf00 nop
8000730: 2000019c .word 0x2000019c
08000734 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000734: b580 push {r7, lr}
8000736: b084 sub sp, #16
8000738: af00 add r7, sp, #0
800073a: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
800073c: f7ff ffee bl 800071c <HAL_GetTick>
8000740: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000742: 687b ldr r3, [r7, #4]
8000744: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
8000746: 68fb ldr r3, [r7, #12]
8000748: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800074c: d005 beq.n 800075a <HAL_Delay+0x26>
{
wait += (uint32_t)uwTickFreq;
800074e: 4b0a ldr r3, [pc, #40] @ (8000778 <HAL_Delay+0x44>)
8000750: 781b ldrb r3, [r3, #0]
8000752: 461a mov r2, r3
8000754: 68fb ldr r3, [r7, #12]
8000756: 4413 add r3, r2
8000758: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
800075a: bf00 nop
800075c: f7ff ffde bl 800071c <HAL_GetTick>
8000760: 4602 mov r2, r0
8000762: 68bb ldr r3, [r7, #8]
8000764: 1ad3 subs r3, r2, r3
8000766: 68fa ldr r2, [r7, #12]
8000768: 429a cmp r2, r3
800076a: d8f7 bhi.n 800075c <HAL_Delay+0x28>
{
}
}
800076c: bf00 nop
800076e: bf00 nop
8000770: 3710 adds r7, #16
8000772: 46bd mov sp, r7
8000774: bd80 pop {r7, pc}
8000776: bf00 nop
8000778: 20000008 .word 0x20000008
0800077c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800077c: b480 push {r7}
800077e: b085 sub sp, #20
8000780: af00 add r7, sp, #0
8000782: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000784: 687b ldr r3, [r7, #4]
8000786: f003 0307 and.w r3, r3, #7
800078a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
800078c: 4b0c ldr r3, [pc, #48] @ (80007c0 <__NVIC_SetPriorityGrouping+0x44>)
800078e: 68db ldr r3, [r3, #12]
8000790: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000792: 68ba ldr r2, [r7, #8]
8000794: f64f 03ff movw r3, #63743 @ 0xf8ff
8000798: 4013 ands r3, r2
800079a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800079c: 68fb ldr r3, [r7, #12]
800079e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80007a0: 68bb ldr r3, [r7, #8]
80007a2: 4313 orrs r3, r2
reg_value = (reg_value |
80007a4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
80007a8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80007ac: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80007ae: 4a04 ldr r2, [pc, #16] @ (80007c0 <__NVIC_SetPriorityGrouping+0x44>)
80007b0: 68bb ldr r3, [r7, #8]
80007b2: 60d3 str r3, [r2, #12]
}
80007b4: bf00 nop
80007b6: 3714 adds r7, #20
80007b8: 46bd mov sp, r7
80007ba: f85d 7b04 ldr.w r7, [sp], #4
80007be: 4770 bx lr
80007c0: e000ed00 .word 0xe000ed00
080007c4 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80007c4: b480 push {r7}
80007c6: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80007c8: 4b04 ldr r3, [pc, #16] @ (80007dc <__NVIC_GetPriorityGrouping+0x18>)
80007ca: 68db ldr r3, [r3, #12]
80007cc: 0a1b lsrs r3, r3, #8
80007ce: f003 0307 and.w r3, r3, #7
}
80007d2: 4618 mov r0, r3
80007d4: 46bd mov sp, r7
80007d6: f85d 7b04 ldr.w r7, [sp], #4
80007da: 4770 bx lr
80007dc: e000ed00 .word 0xe000ed00
080007e0 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80007e0: b480 push {r7}
80007e2: b083 sub sp, #12
80007e4: af00 add r7, sp, #0
80007e6: 4603 mov r3, r0
80007e8: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80007ea: f997 3007 ldrsb.w r3, [r7, #7]
80007ee: 2b00 cmp r3, #0
80007f0: db0b blt.n 800080a <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80007f2: 79fb ldrb r3, [r7, #7]
80007f4: f003 021f and.w r2, r3, #31
80007f8: 4907 ldr r1, [pc, #28] @ (8000818 <__NVIC_EnableIRQ+0x38>)
80007fa: f997 3007 ldrsb.w r3, [r7, #7]
80007fe: 095b lsrs r3, r3, #5
8000800: 2001 movs r0, #1
8000802: fa00 f202 lsl.w r2, r0, r2
8000806: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
800080a: bf00 nop
800080c: 370c adds r7, #12
800080e: 46bd mov sp, r7
8000810: f85d 7b04 ldr.w r7, [sp], #4
8000814: 4770 bx lr
8000816: bf00 nop
8000818: e000e100 .word 0xe000e100
0800081c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
800081c: b480 push {r7}
800081e: b083 sub sp, #12
8000820: af00 add r7, sp, #0
8000822: 4603 mov r3, r0
8000824: 6039 str r1, [r7, #0]
8000826: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000828: f997 3007 ldrsb.w r3, [r7, #7]
800082c: 2b00 cmp r3, #0
800082e: db0a blt.n 8000846 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000830: 683b ldr r3, [r7, #0]
8000832: b2da uxtb r2, r3
8000834: 490c ldr r1, [pc, #48] @ (8000868 <__NVIC_SetPriority+0x4c>)
8000836: f997 3007 ldrsb.w r3, [r7, #7]
800083a: 0112 lsls r2, r2, #4
800083c: b2d2 uxtb r2, r2
800083e: 440b add r3, r1
8000840: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000844: e00a b.n 800085c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000846: 683b ldr r3, [r7, #0]
8000848: b2da uxtb r2, r3
800084a: 4908 ldr r1, [pc, #32] @ (800086c <__NVIC_SetPriority+0x50>)
800084c: 79fb ldrb r3, [r7, #7]
800084e: f003 030f and.w r3, r3, #15
8000852: 3b04 subs r3, #4
8000854: 0112 lsls r2, r2, #4
8000856: b2d2 uxtb r2, r2
8000858: 440b add r3, r1
800085a: 761a strb r2, [r3, #24]
}
800085c: bf00 nop
800085e: 370c adds r7, #12
8000860: 46bd mov sp, r7
8000862: f85d 7b04 ldr.w r7, [sp], #4
8000866: 4770 bx lr
8000868: e000e100 .word 0xe000e100
800086c: e000ed00 .word 0xe000ed00
08000870 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000870: b480 push {r7}
8000872: b089 sub sp, #36 @ 0x24
8000874: af00 add r7, sp, #0
8000876: 60f8 str r0, [r7, #12]
8000878: 60b9 str r1, [r7, #8]
800087a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800087c: 68fb ldr r3, [r7, #12]
800087e: f003 0307 and.w r3, r3, #7
8000882: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000884: 69fb ldr r3, [r7, #28]
8000886: f1c3 0307 rsb r3, r3, #7
800088a: 2b04 cmp r3, #4
800088c: bf28 it cs
800088e: 2304 movcs r3, #4
8000890: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000892: 69fb ldr r3, [r7, #28]
8000894: 3304 adds r3, #4
8000896: 2b06 cmp r3, #6
8000898: d902 bls.n 80008a0 <NVIC_EncodePriority+0x30>
800089a: 69fb ldr r3, [r7, #28]
800089c: 3b03 subs r3, #3
800089e: e000 b.n 80008a2 <NVIC_EncodePriority+0x32>
80008a0: 2300 movs r3, #0
80008a2: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80008a4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80008a8: 69bb ldr r3, [r7, #24]
80008aa: fa02 f303 lsl.w r3, r2, r3
80008ae: 43da mvns r2, r3
80008b0: 68bb ldr r3, [r7, #8]
80008b2: 401a ands r2, r3
80008b4: 697b ldr r3, [r7, #20]
80008b6: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80008b8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
80008bc: 697b ldr r3, [r7, #20]
80008be: fa01 f303 lsl.w r3, r1, r3
80008c2: 43d9 mvns r1, r3
80008c4: 687b ldr r3, [r7, #4]
80008c6: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80008c8: 4313 orrs r3, r2
);
}
80008ca: 4618 mov r0, r3
80008cc: 3724 adds r7, #36 @ 0x24
80008ce: 46bd mov sp, r7
80008d0: f85d 7b04 ldr.w r7, [sp], #4
80008d4: 4770 bx lr
...
080008d8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80008d8: b580 push {r7, lr}
80008da: b082 sub sp, #8
80008dc: af00 add r7, sp, #0
80008de: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80008e0: 687b ldr r3, [r7, #4]
80008e2: 3b01 subs r3, #1
80008e4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80008e8: d301 bcc.n 80008ee <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80008ea: 2301 movs r3, #1
80008ec: e00f b.n 800090e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80008ee: 4a0a ldr r2, [pc, #40] @ (8000918 <SysTick_Config+0x40>)
80008f0: 687b ldr r3, [r7, #4]
80008f2: 3b01 subs r3, #1
80008f4: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80008f6: 210f movs r1, #15
80008f8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80008fc: f7ff ff8e bl 800081c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000900: 4b05 ldr r3, [pc, #20] @ (8000918 <SysTick_Config+0x40>)
8000902: 2200 movs r2, #0
8000904: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000906: 4b04 ldr r3, [pc, #16] @ (8000918 <SysTick_Config+0x40>)
8000908: 2207 movs r2, #7
800090a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
800090c: 2300 movs r3, #0
}
800090e: 4618 mov r0, r3
8000910: 3708 adds r7, #8
8000912: 46bd mov sp, r7
8000914: bd80 pop {r7, pc}
8000916: bf00 nop
8000918: e000e010 .word 0xe000e010
0800091c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800091c: b580 push {r7, lr}
800091e: b082 sub sp, #8
8000920: af00 add r7, sp, #0
8000922: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000924: 6878 ldr r0, [r7, #4]
8000926: f7ff ff29 bl 800077c <__NVIC_SetPriorityGrouping>
}
800092a: bf00 nop
800092c: 3708 adds r7, #8
800092e: 46bd mov sp, r7
8000930: bd80 pop {r7, pc}
08000932 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000932: b580 push {r7, lr}
8000934: b086 sub sp, #24
8000936: af00 add r7, sp, #0
8000938: 4603 mov r3, r0
800093a: 60b9 str r1, [r7, #8]
800093c: 607a str r2, [r7, #4]
800093e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8000940: 2300 movs r3, #0
8000942: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000944: f7ff ff3e bl 80007c4 <__NVIC_GetPriorityGrouping>
8000948: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800094a: 687a ldr r2, [r7, #4]
800094c: 68b9 ldr r1, [r7, #8]
800094e: 6978 ldr r0, [r7, #20]
8000950: f7ff ff8e bl 8000870 <NVIC_EncodePriority>
8000954: 4602 mov r2, r0
8000956: f997 300f ldrsb.w r3, [r7, #15]
800095a: 4611 mov r1, r2
800095c: 4618 mov r0, r3
800095e: f7ff ff5d bl 800081c <__NVIC_SetPriority>
}
8000962: bf00 nop
8000964: 3718 adds r7, #24
8000966: 46bd mov sp, r7
8000968: bd80 pop {r7, pc}
0800096a <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800096a: b580 push {r7, lr}
800096c: b082 sub sp, #8
800096e: af00 add r7, sp, #0
8000970: 4603 mov r3, r0
8000972: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8000974: f997 3007 ldrsb.w r3, [r7, #7]
8000978: 4618 mov r0, r3
800097a: f7ff ff31 bl 80007e0 <__NVIC_EnableIRQ>
}
800097e: bf00 nop
8000980: 3708 adds r7, #8
8000982: 46bd mov sp, r7
8000984: bd80 pop {r7, pc}
08000986 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000986: b580 push {r7, lr}
8000988: b082 sub sp, #8
800098a: af00 add r7, sp, #0
800098c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
800098e: 6878 ldr r0, [r7, #4]
8000990: f7ff ffa2 bl 80008d8 <SysTick_Config>
8000994: 4603 mov r3, r0
}
8000996: 4618 mov r0, r3
8000998: 3708 adds r7, #8
800099a: 46bd mov sp, r7
800099c: bd80 pop {r7, pc}
...
080009a0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80009a0: b480 push {r7}
80009a2: b087 sub sp, #28
80009a4: af00 add r7, sp, #0
80009a6: 6078 str r0, [r7, #4]
80009a8: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80009aa: 2300 movs r3, #0
80009ac: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80009ae: e17f b.n 8000cb0 <HAL_GPIO_Init+0x310>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
80009b0: 683b ldr r3, [r7, #0]
80009b2: 681a ldr r2, [r3, #0]
80009b4: 2101 movs r1, #1
80009b6: 697b ldr r3, [r7, #20]
80009b8: fa01 f303 lsl.w r3, r1, r3
80009bc: 4013 ands r3, r2
80009be: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
80009c0: 68fb ldr r3, [r7, #12]
80009c2: 2b00 cmp r3, #0
80009c4: f000 8171 beq.w 8000caa <HAL_GPIO_Init+0x30a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80009c8: 683b ldr r3, [r7, #0]
80009ca: 685b ldr r3, [r3, #4]
80009cc: f003 0303 and.w r3, r3, #3
80009d0: 2b01 cmp r3, #1
80009d2: d005 beq.n 80009e0 <HAL_GPIO_Init+0x40>
80009d4: 683b ldr r3, [r7, #0]
80009d6: 685b ldr r3, [r3, #4]
80009d8: f003 0303 and.w r3, r3, #3
80009dc: 2b02 cmp r3, #2
80009de: d130 bne.n 8000a42 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80009e0: 687b ldr r3, [r7, #4]
80009e2: 689b ldr r3, [r3, #8]
80009e4: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
80009e6: 697b ldr r3, [r7, #20]
80009e8: 005b lsls r3, r3, #1
80009ea: 2203 movs r2, #3
80009ec: fa02 f303 lsl.w r3, r2, r3
80009f0: 43db mvns r3, r3
80009f2: 693a ldr r2, [r7, #16]
80009f4: 4013 ands r3, r2
80009f6: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
80009f8: 683b ldr r3, [r7, #0]
80009fa: 68da ldr r2, [r3, #12]
80009fc: 697b ldr r3, [r7, #20]
80009fe: 005b lsls r3, r3, #1
8000a00: fa02 f303 lsl.w r3, r2, r3
8000a04: 693a ldr r2, [r7, #16]
8000a06: 4313 orrs r3, r2
8000a08: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8000a0a: 687b ldr r3, [r7, #4]
8000a0c: 693a ldr r2, [r7, #16]
8000a0e: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000a10: 687b ldr r3, [r7, #4]
8000a12: 685b ldr r3, [r3, #4]
8000a14: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8000a16: 2201 movs r2, #1
8000a18: 697b ldr r3, [r7, #20]
8000a1a: fa02 f303 lsl.w r3, r2, r3
8000a1e: 43db mvns r3, r3
8000a20: 693a ldr r2, [r7, #16]
8000a22: 4013 ands r3, r2
8000a24: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000a26: 683b ldr r3, [r7, #0]
8000a28: 685b ldr r3, [r3, #4]
8000a2a: 091b lsrs r3, r3, #4
8000a2c: f003 0201 and.w r2, r3, #1
8000a30: 697b ldr r3, [r7, #20]
8000a32: fa02 f303 lsl.w r3, r2, r3
8000a36: 693a ldr r2, [r7, #16]
8000a38: 4313 orrs r3, r2
8000a3a: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8000a3c: 687b ldr r3, [r7, #4]
8000a3e: 693a ldr r2, [r7, #16]
8000a40: 605a str r2, [r3, #4]
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* In case of Analog mode, check if ADC control mode is selected */
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
8000a42: 683b ldr r3, [r7, #0]
8000a44: 685b ldr r3, [r3, #4]
8000a46: f003 0303 and.w r3, r3, #3
8000a4a: 2b03 cmp r3, #3
8000a4c: d118 bne.n 8000a80 <HAL_GPIO_Init+0xe0>
{
/* Configure the IO Output Type */
temp = GPIOx->ASCR;
8000a4e: 687b ldr r3, [r7, #4]
8000a50: 6adb ldr r3, [r3, #44] @ 0x2c
8000a52: 613b str r3, [r7, #16]
temp &= ~(GPIO_ASCR_ASC0 << position) ;
8000a54: 2201 movs r2, #1
8000a56: 697b ldr r3, [r7, #20]
8000a58: fa02 f303 lsl.w r3, r2, r3
8000a5c: 43db mvns r3, r3
8000a5e: 693a ldr r2, [r7, #16]
8000a60: 4013 ands r3, r2
8000a62: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
8000a64: 683b ldr r3, [r7, #0]
8000a66: 685b ldr r3, [r3, #4]
8000a68: 08db lsrs r3, r3, #3
8000a6a: f003 0201 and.w r2, r3, #1
8000a6e: 697b ldr r3, [r7, #20]
8000a70: fa02 f303 lsl.w r3, r2, r3
8000a74: 693a ldr r2, [r7, #16]
8000a76: 4313 orrs r3, r2
8000a78: 613b str r3, [r7, #16]
GPIOx->ASCR = temp;
8000a7a: 687b ldr r3, [r7, #4]
8000a7c: 693a ldr r2, [r7, #16]
8000a7e: 62da str r2, [r3, #44] @ 0x2c
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000a80: 683b ldr r3, [r7, #0]
8000a82: 685b ldr r3, [r3, #4]
8000a84: f003 0303 and.w r3, r3, #3
8000a88: 2b03 cmp r3, #3
8000a8a: d017 beq.n 8000abc <HAL_GPIO_Init+0x11c>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
temp = GPIOx->PUPDR;
8000a8c: 687b ldr r3, [r7, #4]
8000a8e: 68db ldr r3, [r3, #12]
8000a90: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8000a92: 697b ldr r3, [r7, #20]
8000a94: 005b lsls r3, r3, #1
8000a96: 2203 movs r2, #3
8000a98: fa02 f303 lsl.w r3, r2, r3
8000a9c: 43db mvns r3, r3
8000a9e: 693a ldr r2, [r7, #16]
8000aa0: 4013 ands r3, r2
8000aa2: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8000aa4: 683b ldr r3, [r7, #0]
8000aa6: 689a ldr r2, [r3, #8]
8000aa8: 697b ldr r3, [r7, #20]
8000aaa: 005b lsls r3, r3, #1
8000aac: fa02 f303 lsl.w r3, r2, r3
8000ab0: 693a ldr r2, [r7, #16]
8000ab2: 4313 orrs r3, r2
8000ab4: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000ab6: 687b ldr r3, [r7, #4]
8000ab8: 693a ldr r2, [r7, #16]
8000aba: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000abc: 683b ldr r3, [r7, #0]
8000abe: 685b ldr r3, [r3, #4]
8000ac0: f003 0303 and.w r3, r3, #3
8000ac4: 2b02 cmp r3, #2
8000ac6: d123 bne.n 8000b10 <HAL_GPIO_Init+0x170>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8000ac8: 697b ldr r3, [r7, #20]
8000aca: 08da lsrs r2, r3, #3
8000acc: 687b ldr r3, [r7, #4]
8000ace: 3208 adds r2, #8
8000ad0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8000ad4: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8000ad6: 697b ldr r3, [r7, #20]
8000ad8: f003 0307 and.w r3, r3, #7
8000adc: 009b lsls r3, r3, #2
8000ade: 220f movs r2, #15
8000ae0: fa02 f303 lsl.w r3, r2, r3
8000ae4: 43db mvns r3, r3
8000ae6: 693a ldr r2, [r7, #16]
8000ae8: 4013 ands r3, r2
8000aea: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8000aec: 683b ldr r3, [r7, #0]
8000aee: 691a ldr r2, [r3, #16]
8000af0: 697b ldr r3, [r7, #20]
8000af2: f003 0307 and.w r3, r3, #7
8000af6: 009b lsls r3, r3, #2
8000af8: fa02 f303 lsl.w r3, r2, r3
8000afc: 693a ldr r2, [r7, #16]
8000afe: 4313 orrs r3, r2
8000b00: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8000b02: 697b ldr r3, [r7, #20]
8000b04: 08da lsrs r2, r3, #3
8000b06: 687b ldr r3, [r7, #4]
8000b08: 3208 adds r2, #8
8000b0a: 6939 ldr r1, [r7, #16]
8000b0c: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000b10: 687b ldr r3, [r7, #4]
8000b12: 681b ldr r3, [r3, #0]
8000b14: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8000b16: 697b ldr r3, [r7, #20]
8000b18: 005b lsls r3, r3, #1
8000b1a: 2203 movs r2, #3
8000b1c: fa02 f303 lsl.w r3, r2, r3
8000b20: 43db mvns r3, r3
8000b22: 693a ldr r2, [r7, #16]
8000b24: 4013 ands r3, r2
8000b26: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8000b28: 683b ldr r3, [r7, #0]
8000b2a: 685b ldr r3, [r3, #4]
8000b2c: f003 0203 and.w r2, r3, #3
8000b30: 697b ldr r3, [r7, #20]
8000b32: 005b lsls r3, r3, #1
8000b34: fa02 f303 lsl.w r3, r2, r3
8000b38: 693a ldr r2, [r7, #16]
8000b3a: 4313 orrs r3, r2
8000b3c: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8000b3e: 687b ldr r3, [r7, #4]
8000b40: 693a ldr r2, [r7, #16]
8000b42: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8000b44: 683b ldr r3, [r7, #0]
8000b46: 685b ldr r3, [r3, #4]
8000b48: f403 3340 and.w r3, r3, #196608 @ 0x30000
8000b4c: 2b00 cmp r3, #0
8000b4e: f000 80ac beq.w 8000caa <HAL_GPIO_Init+0x30a>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000b52: 4b5f ldr r3, [pc, #380] @ (8000cd0 <HAL_GPIO_Init+0x330>)
8000b54: 6e1b ldr r3, [r3, #96] @ 0x60
8000b56: 4a5e ldr r2, [pc, #376] @ (8000cd0 <HAL_GPIO_Init+0x330>)
8000b58: f043 0301 orr.w r3, r3, #1
8000b5c: 6613 str r3, [r2, #96] @ 0x60
8000b5e: 4b5c ldr r3, [pc, #368] @ (8000cd0 <HAL_GPIO_Init+0x330>)
8000b60: 6e1b ldr r3, [r3, #96] @ 0x60
8000b62: f003 0301 and.w r3, r3, #1
8000b66: 60bb str r3, [r7, #8]
8000b68: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8000b6a: 4a5a ldr r2, [pc, #360] @ (8000cd4 <HAL_GPIO_Init+0x334>)
8000b6c: 697b ldr r3, [r7, #20]
8000b6e: 089b lsrs r3, r3, #2
8000b70: 3302 adds r3, #2
8000b72: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000b76: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8000b78: 697b ldr r3, [r7, #20]
8000b7a: f003 0303 and.w r3, r3, #3
8000b7e: 009b lsls r3, r3, #2
8000b80: 220f movs r2, #15
8000b82: fa02 f303 lsl.w r3, r2, r3
8000b86: 43db mvns r3, r3
8000b88: 693a ldr r2, [r7, #16]
8000b8a: 4013 ands r3, r2
8000b8c: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8000b8e: 687b ldr r3, [r7, #4]
8000b90: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8000b94: d025 beq.n 8000be2 <HAL_GPIO_Init+0x242>
8000b96: 687b ldr r3, [r7, #4]
8000b98: 4a4f ldr r2, [pc, #316] @ (8000cd8 <HAL_GPIO_Init+0x338>)
8000b9a: 4293 cmp r3, r2
8000b9c: d01f beq.n 8000bde <HAL_GPIO_Init+0x23e>
8000b9e: 687b ldr r3, [r7, #4]
8000ba0: 4a4e ldr r2, [pc, #312] @ (8000cdc <HAL_GPIO_Init+0x33c>)
8000ba2: 4293 cmp r3, r2
8000ba4: d019 beq.n 8000bda <HAL_GPIO_Init+0x23a>
8000ba6: 687b ldr r3, [r7, #4]
8000ba8: 4a4d ldr r2, [pc, #308] @ (8000ce0 <HAL_GPIO_Init+0x340>)
8000baa: 4293 cmp r3, r2
8000bac: d013 beq.n 8000bd6 <HAL_GPIO_Init+0x236>
8000bae: 687b ldr r3, [r7, #4]
8000bb0: 4a4c ldr r2, [pc, #304] @ (8000ce4 <HAL_GPIO_Init+0x344>)
8000bb2: 4293 cmp r3, r2
8000bb4: d00d beq.n 8000bd2 <HAL_GPIO_Init+0x232>
8000bb6: 687b ldr r3, [r7, #4]
8000bb8: 4a4b ldr r2, [pc, #300] @ (8000ce8 <HAL_GPIO_Init+0x348>)
8000bba: 4293 cmp r3, r2
8000bbc: d007 beq.n 8000bce <HAL_GPIO_Init+0x22e>
8000bbe: 687b ldr r3, [r7, #4]
8000bc0: 4a4a ldr r2, [pc, #296] @ (8000cec <HAL_GPIO_Init+0x34c>)
8000bc2: 4293 cmp r3, r2
8000bc4: d101 bne.n 8000bca <HAL_GPIO_Init+0x22a>
8000bc6: 2306 movs r3, #6
8000bc8: e00c b.n 8000be4 <HAL_GPIO_Init+0x244>
8000bca: 2307 movs r3, #7
8000bcc: e00a b.n 8000be4 <HAL_GPIO_Init+0x244>
8000bce: 2305 movs r3, #5
8000bd0: e008 b.n 8000be4 <HAL_GPIO_Init+0x244>
8000bd2: 2304 movs r3, #4
8000bd4: e006 b.n 8000be4 <HAL_GPIO_Init+0x244>
8000bd6: 2303 movs r3, #3
8000bd8: e004 b.n 8000be4 <HAL_GPIO_Init+0x244>
8000bda: 2302 movs r3, #2
8000bdc: e002 b.n 8000be4 <HAL_GPIO_Init+0x244>
8000bde: 2301 movs r3, #1
8000be0: e000 b.n 8000be4 <HAL_GPIO_Init+0x244>
8000be2: 2300 movs r3, #0
8000be4: 697a ldr r2, [r7, #20]
8000be6: f002 0203 and.w r2, r2, #3
8000bea: 0092 lsls r2, r2, #2
8000bec: 4093 lsls r3, r2
8000bee: 693a ldr r2, [r7, #16]
8000bf0: 4313 orrs r3, r2
8000bf2: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8000bf4: 4937 ldr r1, [pc, #220] @ (8000cd4 <HAL_GPIO_Init+0x334>)
8000bf6: 697b ldr r3, [r7, #20]
8000bf8: 089b lsrs r3, r3, #2
8000bfa: 3302 adds r3, #2
8000bfc: 693a ldr r2, [r7, #16]
8000bfe: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8000c02: 4b3b ldr r3, [pc, #236] @ (8000cf0 <HAL_GPIO_Init+0x350>)
8000c04: 689b ldr r3, [r3, #8]
8000c06: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000c08: 68fb ldr r3, [r7, #12]
8000c0a: 43db mvns r3, r3
8000c0c: 693a ldr r2, [r7, #16]
8000c0e: 4013 ands r3, r2
8000c10: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8000c12: 683b ldr r3, [r7, #0]
8000c14: 685b ldr r3, [r3, #4]
8000c16: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8000c1a: 2b00 cmp r3, #0
8000c1c: d003 beq.n 8000c26 <HAL_GPIO_Init+0x286>
{
temp |= iocurrent;
8000c1e: 693a ldr r2, [r7, #16]
8000c20: 68fb ldr r3, [r7, #12]
8000c22: 4313 orrs r3, r2
8000c24: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8000c26: 4a32 ldr r2, [pc, #200] @ (8000cf0 <HAL_GPIO_Init+0x350>)
8000c28: 693b ldr r3, [r7, #16]
8000c2a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8000c2c: 4b30 ldr r3, [pc, #192] @ (8000cf0 <HAL_GPIO_Init+0x350>)
8000c2e: 68db ldr r3, [r3, #12]
8000c30: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000c32: 68fb ldr r3, [r7, #12]
8000c34: 43db mvns r3, r3
8000c36: 693a ldr r2, [r7, #16]
8000c38: 4013 ands r3, r2
8000c3a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8000c3c: 683b ldr r3, [r7, #0]
8000c3e: 685b ldr r3, [r3, #4]
8000c40: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8000c44: 2b00 cmp r3, #0
8000c46: d003 beq.n 8000c50 <HAL_GPIO_Init+0x2b0>
{
temp |= iocurrent;
8000c48: 693a ldr r2, [r7, #16]
8000c4a: 68fb ldr r3, [r7, #12]
8000c4c: 4313 orrs r3, r2
8000c4e: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8000c50: 4a27 ldr r2, [pc, #156] @ (8000cf0 <HAL_GPIO_Init+0x350>)
8000c52: 693b ldr r3, [r7, #16]
8000c54: 60d3 str r3, [r2, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8000c56: 4b26 ldr r3, [pc, #152] @ (8000cf0 <HAL_GPIO_Init+0x350>)
8000c58: 685b ldr r3, [r3, #4]
8000c5a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000c5c: 68fb ldr r3, [r7, #12]
8000c5e: 43db mvns r3, r3
8000c60: 693a ldr r2, [r7, #16]
8000c62: 4013 ands r3, r2
8000c64: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8000c66: 683b ldr r3, [r7, #0]
8000c68: 685b ldr r3, [r3, #4]
8000c6a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000c6e: 2b00 cmp r3, #0
8000c70: d003 beq.n 8000c7a <HAL_GPIO_Init+0x2da>
{
temp |= iocurrent;
8000c72: 693a ldr r2, [r7, #16]
8000c74: 68fb ldr r3, [r7, #12]
8000c76: 4313 orrs r3, r2
8000c78: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8000c7a: 4a1d ldr r2, [pc, #116] @ (8000cf0 <HAL_GPIO_Init+0x350>)
8000c7c: 693b ldr r3, [r7, #16]
8000c7e: 6053 str r3, [r2, #4]
temp = EXTI->IMR1;
8000c80: 4b1b ldr r3, [pc, #108] @ (8000cf0 <HAL_GPIO_Init+0x350>)
8000c82: 681b ldr r3, [r3, #0]
8000c84: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000c86: 68fb ldr r3, [r7, #12]
8000c88: 43db mvns r3, r3
8000c8a: 693a ldr r2, [r7, #16]
8000c8c: 4013 ands r3, r2
8000c8e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8000c90: 683b ldr r3, [r7, #0]
8000c92: 685b ldr r3, [r3, #4]
8000c94: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000c98: 2b00 cmp r3, #0
8000c9a: d003 beq.n 8000ca4 <HAL_GPIO_Init+0x304>
{
temp |= iocurrent;
8000c9c: 693a ldr r2, [r7, #16]
8000c9e: 68fb ldr r3, [r7, #12]
8000ca0: 4313 orrs r3, r2
8000ca2: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8000ca4: 4a12 ldr r2, [pc, #72] @ (8000cf0 <HAL_GPIO_Init+0x350>)
8000ca6: 693b ldr r3, [r7, #16]
8000ca8: 6013 str r3, [r2, #0]
}
}
position++;
8000caa: 697b ldr r3, [r7, #20]
8000cac: 3301 adds r3, #1
8000cae: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000cb0: 683b ldr r3, [r7, #0]
8000cb2: 681a ldr r2, [r3, #0]
8000cb4: 697b ldr r3, [r7, #20]
8000cb6: fa22 f303 lsr.w r3, r2, r3
8000cba: 2b00 cmp r3, #0
8000cbc: f47f ae78 bne.w 80009b0 <HAL_GPIO_Init+0x10>
}
}
8000cc0: bf00 nop
8000cc2: bf00 nop
8000cc4: 371c adds r7, #28
8000cc6: 46bd mov sp, r7
8000cc8: f85d 7b04 ldr.w r7, [sp], #4
8000ccc: 4770 bx lr
8000cce: bf00 nop
8000cd0: 40021000 .word 0x40021000
8000cd4: 40010000 .word 0x40010000
8000cd8: 48000400 .word 0x48000400
8000cdc: 48000800 .word 0x48000800
8000ce0: 48000c00 .word 0x48000c00
8000ce4: 48001000 .word 0x48001000
8000ce8: 48001400 .word 0x48001400
8000cec: 48001800 .word 0x48001800
8000cf0: 40010400 .word 0x40010400
08000cf4 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8000cf4: b580 push {r7, lr}
8000cf6: b082 sub sp, #8
8000cf8: af00 add r7, sp, #0
8000cfa: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8000cfc: 687b ldr r3, [r7, #4]
8000cfe: 2b00 cmp r3, #0
8000d00: d101 bne.n 8000d06 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8000d02: 2301 movs r3, #1
8000d04: e08d b.n 8000e22 <HAL_I2C_Init+0x12e>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8000d06: 687b ldr r3, [r7, #4]
8000d08: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8000d0c: b2db uxtb r3, r3
8000d0e: 2b00 cmp r3, #0
8000d10: d106 bne.n 8000d20 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8000d12: 687b ldr r3, [r7, #4]
8000d14: 2200 movs r2, #0
8000d16: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
8000d1a: 6878 ldr r0, [r7, #4]
8000d1c: f7ff fbc2 bl 80004a4 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8000d20: 687b ldr r3, [r7, #4]
8000d22: 2224 movs r2, #36 @ 0x24
8000d24: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8000d28: 687b ldr r3, [r7, #4]
8000d2a: 681b ldr r3, [r3, #0]
8000d2c: 681a ldr r2, [r3, #0]
8000d2e: 687b ldr r3, [r7, #4]
8000d30: 681b ldr r3, [r3, #0]
8000d32: f022 0201 bic.w r2, r2, #1
8000d36: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8000d38: 687b ldr r3, [r7, #4]
8000d3a: 685a ldr r2, [r3, #4]
8000d3c: 687b ldr r3, [r7, #4]
8000d3e: 681b ldr r3, [r3, #0]
8000d40: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
8000d44: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8000d46: 687b ldr r3, [r7, #4]
8000d48: 681b ldr r3, [r3, #0]
8000d4a: 689a ldr r2, [r3, #8]
8000d4c: 687b ldr r3, [r7, #4]
8000d4e: 681b ldr r3, [r3, #0]
8000d50: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8000d54: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8000d56: 687b ldr r3, [r7, #4]
8000d58: 68db ldr r3, [r3, #12]
8000d5a: 2b01 cmp r3, #1
8000d5c: d107 bne.n 8000d6e <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
8000d5e: 687b ldr r3, [r7, #4]
8000d60: 689a ldr r2, [r3, #8]
8000d62: 687b ldr r3, [r7, #4]
8000d64: 681b ldr r3, [r3, #0]
8000d66: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8000d6a: 609a str r2, [r3, #8]
8000d6c: e006 b.n 8000d7c <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
8000d6e: 687b ldr r3, [r7, #4]
8000d70: 689a ldr r2, [r3, #8]
8000d72: 687b ldr r3, [r7, #4]
8000d74: 681b ldr r3, [r3, #0]
8000d76: f442 4204 orr.w r2, r2, #33792 @ 0x8400
8000d7a: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
8000d7c: 687b ldr r3, [r7, #4]
8000d7e: 68db ldr r3, [r3, #12]
8000d80: 2b02 cmp r3, #2
8000d82: d108 bne.n 8000d96 <HAL_I2C_Init+0xa2>
{
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8000d84: 687b ldr r3, [r7, #4]
8000d86: 681b ldr r3, [r3, #0]
8000d88: 685a ldr r2, [r3, #4]
8000d8a: 687b ldr r3, [r7, #4]
8000d8c: 681b ldr r3, [r3, #0]
8000d8e: f442 6200 orr.w r2, r2, #2048 @ 0x800
8000d92: 605a str r2, [r3, #4]
8000d94: e007 b.n 8000da6 <HAL_I2C_Init+0xb2>
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8000d96: 687b ldr r3, [r7, #4]
8000d98: 681b ldr r3, [r3, #0]
8000d9a: 685a ldr r2, [r3, #4]
8000d9c: 687b ldr r3, [r7, #4]
8000d9e: 681b ldr r3, [r3, #0]
8000da0: f422 6200 bic.w r2, r2, #2048 @ 0x800
8000da4: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8000da6: 687b ldr r3, [r7, #4]
8000da8: 681b ldr r3, [r3, #0]
8000daa: 685b ldr r3, [r3, #4]
8000dac: 687a ldr r2, [r7, #4]
8000dae: 6812 ldr r2, [r2, #0]
8000db0: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8000db4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8000db8: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8000dba: 687b ldr r3, [r7, #4]
8000dbc: 681b ldr r3, [r3, #0]
8000dbe: 68da ldr r2, [r3, #12]
8000dc0: 687b ldr r3, [r7, #4]
8000dc2: 681b ldr r3, [r3, #0]
8000dc4: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8000dc8: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8000dca: 687b ldr r3, [r7, #4]
8000dcc: 691a ldr r2, [r3, #16]
8000dce: 687b ldr r3, [r7, #4]
8000dd0: 695b ldr r3, [r3, #20]
8000dd2: ea42 0103 orr.w r1, r2, r3
(hi2c->Init.OwnAddress2Masks << 8));
8000dd6: 687b ldr r3, [r7, #4]
8000dd8: 699b ldr r3, [r3, #24]
8000dda: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8000ddc: 687b ldr r3, [r7, #4]
8000dde: 681b ldr r3, [r3, #0]
8000de0: 430a orrs r2, r1
8000de2: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8000de4: 687b ldr r3, [r7, #4]
8000de6: 69d9 ldr r1, [r3, #28]
8000de8: 687b ldr r3, [r7, #4]
8000dea: 6a1a ldr r2, [r3, #32]
8000dec: 687b ldr r3, [r7, #4]
8000dee: 681b ldr r3, [r3, #0]
8000df0: 430a orrs r2, r1
8000df2: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8000df4: 687b ldr r3, [r7, #4]
8000df6: 681b ldr r3, [r3, #0]
8000df8: 681a ldr r2, [r3, #0]
8000dfa: 687b ldr r3, [r7, #4]
8000dfc: 681b ldr r3, [r3, #0]
8000dfe: f042 0201 orr.w r2, r2, #1
8000e02: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8000e04: 687b ldr r3, [r7, #4]
8000e06: 2200 movs r2, #0
8000e08: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
8000e0a: 687b ldr r3, [r7, #4]
8000e0c: 2220 movs r2, #32
8000e0e: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8000e12: 687b ldr r3, [r7, #4]
8000e14: 2200 movs r2, #0
8000e16: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8000e18: 687b ldr r3, [r7, #4]
8000e1a: 2200 movs r2, #0
8000e1c: f883 2042 strb.w r2, [r3, #66] @ 0x42
return HAL_OK;
8000e20: 2300 movs r3, #0
}
8000e22: 4618 mov r0, r3
8000e24: 3708 adds r7, #8
8000e26: 46bd mov sp, r7
8000e28: bd80 pop {r7, pc}
...
08000e2c <HAL_I2C_Mem_Write>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8000e2c: b580 push {r7, lr}
8000e2e: b088 sub sp, #32
8000e30: af02 add r7, sp, #8
8000e32: 60f8 str r0, [r7, #12]
8000e34: 4608 mov r0, r1
8000e36: 4611 mov r1, r2
8000e38: 461a mov r2, r3
8000e3a: 4603 mov r3, r0
8000e3c: 817b strh r3, [r7, #10]
8000e3e: 460b mov r3, r1
8000e40: 813b strh r3, [r7, #8]
8000e42: 4613 mov r3, r2
8000e44: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
8000e46: 68fb ldr r3, [r7, #12]
8000e48: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8000e4c: b2db uxtb r3, r3
8000e4e: 2b20 cmp r3, #32
8000e50: f040 80f9 bne.w 8001046 <HAL_I2C_Mem_Write+0x21a>
{
if ((pData == NULL) || (Size == 0U))
8000e54: 6a3b ldr r3, [r7, #32]
8000e56: 2b00 cmp r3, #0
8000e58: d002 beq.n 8000e60 <HAL_I2C_Mem_Write+0x34>
8000e5a: 8cbb ldrh r3, [r7, #36] @ 0x24
8000e5c: 2b00 cmp r3, #0
8000e5e: d105 bne.n 8000e6c <HAL_I2C_Mem_Write+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8000e60: 68fb ldr r3, [r7, #12]
8000e62: f44f 7200 mov.w r2, #512 @ 0x200
8000e66: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
8000e68: 2301 movs r3, #1
8000e6a: e0ed b.n 8001048 <HAL_I2C_Mem_Write+0x21c>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8000e6c: 68fb ldr r3, [r7, #12]
8000e6e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8000e72: 2b01 cmp r3, #1
8000e74: d101 bne.n 8000e7a <HAL_I2C_Mem_Write+0x4e>
8000e76: 2302 movs r3, #2
8000e78: e0e6 b.n 8001048 <HAL_I2C_Mem_Write+0x21c>
8000e7a: 68fb ldr r3, [r7, #12]
8000e7c: 2201 movs r2, #1
8000e7e: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8000e82: f7ff fc4b bl 800071c <HAL_GetTick>
8000e86: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8000e88: 697b ldr r3, [r7, #20]
8000e8a: 9300 str r3, [sp, #0]
8000e8c: 2319 movs r3, #25
8000e8e: 2201 movs r2, #1
8000e90: f44f 4100 mov.w r1, #32768 @ 0x8000
8000e94: 68f8 ldr r0, [r7, #12]
8000e96: f000 fac3 bl 8001420 <I2C_WaitOnFlagUntilTimeout>
8000e9a: 4603 mov r3, r0
8000e9c: 2b00 cmp r3, #0
8000e9e: d001 beq.n 8000ea4 <HAL_I2C_Mem_Write+0x78>
{
return HAL_ERROR;
8000ea0: 2301 movs r3, #1
8000ea2: e0d1 b.n 8001048 <HAL_I2C_Mem_Write+0x21c>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
8000ea4: 68fb ldr r3, [r7, #12]
8000ea6: 2221 movs r2, #33 @ 0x21
8000ea8: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
8000eac: 68fb ldr r3, [r7, #12]
8000eae: 2240 movs r2, #64 @ 0x40
8000eb0: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8000eb4: 68fb ldr r3, [r7, #12]
8000eb6: 2200 movs r2, #0
8000eb8: 645a str r2, [r3, #68] @ 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8000eba: 68fb ldr r3, [r7, #12]
8000ebc: 6a3a ldr r2, [r7, #32]
8000ebe: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8000ec0: 68fb ldr r3, [r7, #12]
8000ec2: 8cba ldrh r2, [r7, #36] @ 0x24
8000ec4: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferISR = NULL;
8000ec6: 68fb ldr r3, [r7, #12]
8000ec8: 2200 movs r2, #0
8000eca: 635a str r2, [r3, #52] @ 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
8000ecc: 88f8 ldrh r0, [r7, #6]
8000ece: 893a ldrh r2, [r7, #8]
8000ed0: 8979 ldrh r1, [r7, #10]
8000ed2: 697b ldr r3, [r7, #20]
8000ed4: 9301 str r3, [sp, #4]
8000ed6: 6abb ldr r3, [r7, #40] @ 0x28
8000ed8: 9300 str r3, [sp, #0]
8000eda: 4603 mov r3, r0
8000edc: 68f8 ldr r0, [r7, #12]
8000ede: f000 f9d3 bl 8001288 <I2C_RequestMemoryWrite>
8000ee2: 4603 mov r3, r0
8000ee4: 2b00 cmp r3, #0
8000ee6: d005 beq.n 8000ef4 <HAL_I2C_Mem_Write+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8000ee8: 68fb ldr r3, [r7, #12]
8000eea: 2200 movs r2, #0
8000eec: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8000ef0: 2301 movs r3, #1
8000ef2: e0a9 b.n 8001048 <HAL_I2C_Mem_Write+0x21c>
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8000ef4: 68fb ldr r3, [r7, #12]
8000ef6: 8d5b ldrh r3, [r3, #42] @ 0x2a
8000ef8: b29b uxth r3, r3
8000efa: 2bff cmp r3, #255 @ 0xff
8000efc: d90e bls.n 8000f1c <HAL_I2C_Mem_Write+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8000efe: 68fb ldr r3, [r7, #12]
8000f00: 22ff movs r2, #255 @ 0xff
8000f02: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
8000f04: 68fb ldr r3, [r7, #12]
8000f06: 8d1b ldrh r3, [r3, #40] @ 0x28
8000f08: b2da uxtb r2, r3
8000f0a: 8979 ldrh r1, [r7, #10]
8000f0c: 2300 movs r3, #0
8000f0e: 9300 str r3, [sp, #0]
8000f10: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8000f14: 68f8 ldr r0, [r7, #12]
8000f16: f000 fc47 bl 80017a8 <I2C_TransferConfig>
8000f1a: e00f b.n 8000f3c <HAL_I2C_Mem_Write+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8000f1c: 68fb ldr r3, [r7, #12]
8000f1e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8000f20: b29a uxth r2, r3
8000f22: 68fb ldr r3, [r7, #12]
8000f24: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
8000f26: 68fb ldr r3, [r7, #12]
8000f28: 8d1b ldrh r3, [r3, #40] @ 0x28
8000f2a: b2da uxtb r2, r3
8000f2c: 8979 ldrh r1, [r7, #10]
8000f2e: 2300 movs r3, #0
8000f30: 9300 str r3, [sp, #0]
8000f32: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8000f36: 68f8 ldr r0, [r7, #12]
8000f38: f000 fc36 bl 80017a8 <I2C_TransferConfig>
}
do
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8000f3c: 697a ldr r2, [r7, #20]
8000f3e: 6ab9 ldr r1, [r7, #40] @ 0x28
8000f40: 68f8 ldr r0, [r7, #12]
8000f42: f000 fac6 bl 80014d2 <I2C_WaitOnTXISFlagUntilTimeout>
8000f46: 4603 mov r3, r0
8000f48: 2b00 cmp r3, #0
8000f4a: d001 beq.n 8000f50 <HAL_I2C_Mem_Write+0x124>
{
return HAL_ERROR;
8000f4c: 2301 movs r3, #1
8000f4e: e07b b.n 8001048 <HAL_I2C_Mem_Write+0x21c>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8000f50: 68fb ldr r3, [r7, #12]
8000f52: 6a5b ldr r3, [r3, #36] @ 0x24
8000f54: 781a ldrb r2, [r3, #0]
8000f56: 68fb ldr r3, [r7, #12]
8000f58: 681b ldr r3, [r3, #0]
8000f5a: 629a str r2, [r3, #40] @ 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8000f5c: 68fb ldr r3, [r7, #12]
8000f5e: 6a5b ldr r3, [r3, #36] @ 0x24
8000f60: 1c5a adds r2, r3, #1
8000f62: 68fb ldr r3, [r7, #12]
8000f64: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount--;
8000f66: 68fb ldr r3, [r7, #12]
8000f68: 8d5b ldrh r3, [r3, #42] @ 0x2a
8000f6a: b29b uxth r3, r3
8000f6c: 3b01 subs r3, #1
8000f6e: b29a uxth r2, r3
8000f70: 68fb ldr r3, [r7, #12]
8000f72: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8000f74: 68fb ldr r3, [r7, #12]
8000f76: 8d1b ldrh r3, [r3, #40] @ 0x28
8000f78: 3b01 subs r3, #1
8000f7a: b29a uxth r2, r3
8000f7c: 68fb ldr r3, [r7, #12]
8000f7e: 851a strh r2, [r3, #40] @ 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8000f80: 68fb ldr r3, [r7, #12]
8000f82: 8d5b ldrh r3, [r3, #42] @ 0x2a
8000f84: b29b uxth r3, r3
8000f86: 2b00 cmp r3, #0
8000f88: d034 beq.n 8000ff4 <HAL_I2C_Mem_Write+0x1c8>
8000f8a: 68fb ldr r3, [r7, #12]
8000f8c: 8d1b ldrh r3, [r3, #40] @ 0x28
8000f8e: 2b00 cmp r3, #0
8000f90: d130 bne.n 8000ff4 <HAL_I2C_Mem_Write+0x1c8>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
8000f92: 697b ldr r3, [r7, #20]
8000f94: 9300 str r3, [sp, #0]
8000f96: 6abb ldr r3, [r7, #40] @ 0x28
8000f98: 2200 movs r2, #0
8000f9a: 2180 movs r1, #128 @ 0x80
8000f9c: 68f8 ldr r0, [r7, #12]
8000f9e: f000 fa3f bl 8001420 <I2C_WaitOnFlagUntilTimeout>
8000fa2: 4603 mov r3, r0
8000fa4: 2b00 cmp r3, #0
8000fa6: d001 beq.n 8000fac <HAL_I2C_Mem_Write+0x180>
{
return HAL_ERROR;
8000fa8: 2301 movs r3, #1
8000faa: e04d b.n 8001048 <HAL_I2C_Mem_Write+0x21c>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8000fac: 68fb ldr r3, [r7, #12]
8000fae: 8d5b ldrh r3, [r3, #42] @ 0x2a
8000fb0: b29b uxth r3, r3
8000fb2: 2bff cmp r3, #255 @ 0xff
8000fb4: d90e bls.n 8000fd4 <HAL_I2C_Mem_Write+0x1a8>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8000fb6: 68fb ldr r3, [r7, #12]
8000fb8: 22ff movs r2, #255 @ 0xff
8000fba: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
8000fbc: 68fb ldr r3, [r7, #12]
8000fbe: 8d1b ldrh r3, [r3, #40] @ 0x28
8000fc0: b2da uxtb r2, r3
8000fc2: 8979 ldrh r1, [r7, #10]
8000fc4: 2300 movs r3, #0
8000fc6: 9300 str r3, [sp, #0]
8000fc8: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8000fcc: 68f8 ldr r0, [r7, #12]
8000fce: f000 fbeb bl 80017a8 <I2C_TransferConfig>
8000fd2: e00f b.n 8000ff4 <HAL_I2C_Mem_Write+0x1c8>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8000fd4: 68fb ldr r3, [r7, #12]
8000fd6: 8d5b ldrh r3, [r3, #42] @ 0x2a
8000fd8: b29a uxth r2, r3
8000fda: 68fb ldr r3, [r7, #12]
8000fdc: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
8000fde: 68fb ldr r3, [r7, #12]
8000fe0: 8d1b ldrh r3, [r3, #40] @ 0x28
8000fe2: b2da uxtb r2, r3
8000fe4: 8979 ldrh r1, [r7, #10]
8000fe6: 2300 movs r3, #0
8000fe8: 9300 str r3, [sp, #0]
8000fea: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8000fee: 68f8 ldr r0, [r7, #12]
8000ff0: f000 fbda bl 80017a8 <I2C_TransferConfig>
I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
8000ff4: 68fb ldr r3, [r7, #12]
8000ff6: 8d5b ldrh r3, [r3, #42] @ 0x2a
8000ff8: b29b uxth r3, r3
8000ffa: 2b00 cmp r3, #0
8000ffc: d19e bne.n 8000f3c <HAL_I2C_Mem_Write+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8000ffe: 697a ldr r2, [r7, #20]
8001000: 6ab9 ldr r1, [r7, #40] @ 0x28
8001002: 68f8 ldr r0, [r7, #12]
8001004: f000 faac bl 8001560 <I2C_WaitOnSTOPFlagUntilTimeout>
8001008: 4603 mov r3, r0
800100a: 2b00 cmp r3, #0
800100c: d001 beq.n 8001012 <HAL_I2C_Mem_Write+0x1e6>
{
return HAL_ERROR;
800100e: 2301 movs r3, #1
8001010: e01a b.n 8001048 <HAL_I2C_Mem_Write+0x21c>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8001012: 68fb ldr r3, [r7, #12]
8001014: 681b ldr r3, [r3, #0]
8001016: 2220 movs r2, #32
8001018: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
800101a: 68fb ldr r3, [r7, #12]
800101c: 681b ldr r3, [r3, #0]
800101e: 6859 ldr r1, [r3, #4]
8001020: 68fb ldr r3, [r7, #12]
8001022: 681a ldr r2, [r3, #0]
8001024: 4b0a ldr r3, [pc, #40] @ (8001050 <HAL_I2C_Mem_Write+0x224>)
8001026: 400b ands r3, r1
8001028: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
800102a: 68fb ldr r3, [r7, #12]
800102c: 2220 movs r2, #32
800102e: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001032: 68fb ldr r3, [r7, #12]
8001034: 2200 movs r2, #0
8001036: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800103a: 68fb ldr r3, [r7, #12]
800103c: 2200 movs r2, #0
800103e: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8001042: 2300 movs r3, #0
8001044: e000 b.n 8001048 <HAL_I2C_Mem_Write+0x21c>
}
else
{
return HAL_BUSY;
8001046: 2302 movs r3, #2
}
}
8001048: 4618 mov r0, r3
800104a: 3718 adds r7, #24
800104c: 46bd mov sp, r7
800104e: bd80 pop {r7, pc}
8001050: fe00e800 .word 0xfe00e800
08001054 <HAL_I2C_Mem_Read>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8001054: b580 push {r7, lr}
8001056: b088 sub sp, #32
8001058: af02 add r7, sp, #8
800105a: 60f8 str r0, [r7, #12]
800105c: 4608 mov r0, r1
800105e: 4611 mov r1, r2
8001060: 461a mov r2, r3
8001062: 4603 mov r3, r0
8001064: 817b strh r3, [r7, #10]
8001066: 460b mov r3, r1
8001068: 813b strh r3, [r7, #8]
800106a: 4613 mov r3, r2
800106c: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
800106e: 68fb ldr r3, [r7, #12]
8001070: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8001074: b2db uxtb r3, r3
8001076: 2b20 cmp r3, #32
8001078: f040 80fd bne.w 8001276 <HAL_I2C_Mem_Read+0x222>
{
if ((pData == NULL) || (Size == 0U))
800107c: 6a3b ldr r3, [r7, #32]
800107e: 2b00 cmp r3, #0
8001080: d002 beq.n 8001088 <HAL_I2C_Mem_Read+0x34>
8001082: 8cbb ldrh r3, [r7, #36] @ 0x24
8001084: 2b00 cmp r3, #0
8001086: d105 bne.n 8001094 <HAL_I2C_Mem_Read+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8001088: 68fb ldr r3, [r7, #12]
800108a: f44f 7200 mov.w r2, #512 @ 0x200
800108e: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
8001090: 2301 movs r3, #1
8001092: e0f1 b.n 8001278 <HAL_I2C_Mem_Read+0x224>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8001094: 68fb ldr r3, [r7, #12]
8001096: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
800109a: 2b01 cmp r3, #1
800109c: d101 bne.n 80010a2 <HAL_I2C_Mem_Read+0x4e>
800109e: 2302 movs r3, #2
80010a0: e0ea b.n 8001278 <HAL_I2C_Mem_Read+0x224>
80010a2: 68fb ldr r3, [r7, #12]
80010a4: 2201 movs r2, #1
80010a6: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
80010aa: f7ff fb37 bl 800071c <HAL_GetTick>
80010ae: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
80010b0: 697b ldr r3, [r7, #20]
80010b2: 9300 str r3, [sp, #0]
80010b4: 2319 movs r3, #25
80010b6: 2201 movs r2, #1
80010b8: f44f 4100 mov.w r1, #32768 @ 0x8000
80010bc: 68f8 ldr r0, [r7, #12]
80010be: f000 f9af bl 8001420 <I2C_WaitOnFlagUntilTimeout>
80010c2: 4603 mov r3, r0
80010c4: 2b00 cmp r3, #0
80010c6: d001 beq.n 80010cc <HAL_I2C_Mem_Read+0x78>
{
return HAL_ERROR;
80010c8: 2301 movs r3, #1
80010ca: e0d5 b.n 8001278 <HAL_I2C_Mem_Read+0x224>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
80010cc: 68fb ldr r3, [r7, #12]
80010ce: 2222 movs r2, #34 @ 0x22
80010d0: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
80010d4: 68fb ldr r3, [r7, #12]
80010d6: 2240 movs r2, #64 @ 0x40
80010d8: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80010dc: 68fb ldr r3, [r7, #12]
80010de: 2200 movs r2, #0
80010e0: 645a str r2, [r3, #68] @ 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80010e2: 68fb ldr r3, [r7, #12]
80010e4: 6a3a ldr r2, [r7, #32]
80010e6: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
80010e8: 68fb ldr r3, [r7, #12]
80010ea: 8cba ldrh r2, [r7, #36] @ 0x24
80010ec: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferISR = NULL;
80010ee: 68fb ldr r3, [r7, #12]
80010f0: 2200 movs r2, #0
80010f2: 635a str r2, [r3, #52] @ 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
80010f4: 88f8 ldrh r0, [r7, #6]
80010f6: 893a ldrh r2, [r7, #8]
80010f8: 8979 ldrh r1, [r7, #10]
80010fa: 697b ldr r3, [r7, #20]
80010fc: 9301 str r3, [sp, #4]
80010fe: 6abb ldr r3, [r7, #40] @ 0x28
8001100: 9300 str r3, [sp, #0]
8001102: 4603 mov r3, r0
8001104: 68f8 ldr r0, [r7, #12]
8001106: f000 f913 bl 8001330 <I2C_RequestMemoryRead>
800110a: 4603 mov r3, r0
800110c: 2b00 cmp r3, #0
800110e: d005 beq.n 800111c <HAL_I2C_Mem_Read+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001110: 68fb ldr r3, [r7, #12]
8001112: 2200 movs r2, #0
8001114: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8001118: 2301 movs r3, #1
800111a: e0ad b.n 8001278 <HAL_I2C_Mem_Read+0x224>
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
800111c: 68fb ldr r3, [r7, #12]
800111e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001120: b29b uxth r3, r3
8001122: 2bff cmp r3, #255 @ 0xff
8001124: d90e bls.n 8001144 <HAL_I2C_Mem_Read+0xf0>
{
hi2c->XferSize = 1U;
8001126: 68fb ldr r3, [r7, #12]
8001128: 2201 movs r2, #1
800112a: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
800112c: 68fb ldr r3, [r7, #12]
800112e: 8d1b ldrh r3, [r3, #40] @ 0x28
8001130: b2da uxtb r2, r3
8001132: 8979 ldrh r1, [r7, #10]
8001134: 4b52 ldr r3, [pc, #328] @ (8001280 <HAL_I2C_Mem_Read+0x22c>)
8001136: 9300 str r3, [sp, #0]
8001138: f04f 7380 mov.w r3, #16777216 @ 0x1000000
800113c: 68f8 ldr r0, [r7, #12]
800113e: f000 fb33 bl 80017a8 <I2C_TransferConfig>
8001142: e00f b.n 8001164 <HAL_I2C_Mem_Read+0x110>
I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8001144: 68fb ldr r3, [r7, #12]
8001146: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001148: b29a uxth r2, r3
800114a: 68fb ldr r3, [r7, #12]
800114c: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
800114e: 68fb ldr r3, [r7, #12]
8001150: 8d1b ldrh r3, [r3, #40] @ 0x28
8001152: b2da uxtb r2, r3
8001154: 8979 ldrh r1, [r7, #10]
8001156: 4b4a ldr r3, [pc, #296] @ (8001280 <HAL_I2C_Mem_Read+0x22c>)
8001158: 9300 str r3, [sp, #0]
800115a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
800115e: 68f8 ldr r0, [r7, #12]
8001160: f000 fb22 bl 80017a8 <I2C_TransferConfig>
}
do
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
8001164: 697b ldr r3, [r7, #20]
8001166: 9300 str r3, [sp, #0]
8001168: 6abb ldr r3, [r7, #40] @ 0x28
800116a: 2200 movs r2, #0
800116c: 2104 movs r1, #4
800116e: 68f8 ldr r0, [r7, #12]
8001170: f000 f956 bl 8001420 <I2C_WaitOnFlagUntilTimeout>
8001174: 4603 mov r3, r0
8001176: 2b00 cmp r3, #0
8001178: d001 beq.n 800117e <HAL_I2C_Mem_Read+0x12a>
{
return HAL_ERROR;
800117a: 2301 movs r3, #1
800117c: e07c b.n 8001278 <HAL_I2C_Mem_Read+0x224>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
800117e: 68fb ldr r3, [r7, #12]
8001180: 681b ldr r3, [r3, #0]
8001182: 6a5a ldr r2, [r3, #36] @ 0x24
8001184: 68fb ldr r3, [r7, #12]
8001186: 6a5b ldr r3, [r3, #36] @ 0x24
8001188: b2d2 uxtb r2, r2
800118a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800118c: 68fb ldr r3, [r7, #12]
800118e: 6a5b ldr r3, [r3, #36] @ 0x24
8001190: 1c5a adds r2, r3, #1
8001192: 68fb ldr r3, [r7, #12]
8001194: 625a str r2, [r3, #36] @ 0x24
hi2c->XferSize--;
8001196: 68fb ldr r3, [r7, #12]
8001198: 8d1b ldrh r3, [r3, #40] @ 0x28
800119a: 3b01 subs r3, #1
800119c: b29a uxth r2, r3
800119e: 68fb ldr r3, [r7, #12]
80011a0: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
80011a2: 68fb ldr r3, [r7, #12]
80011a4: 8d5b ldrh r3, [r3, #42] @ 0x2a
80011a6: b29b uxth r3, r3
80011a8: 3b01 subs r3, #1
80011aa: b29a uxth r2, r3
80011ac: 68fb ldr r3, [r7, #12]
80011ae: 855a strh r2, [r3, #42] @ 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
80011b0: 68fb ldr r3, [r7, #12]
80011b2: 8d5b ldrh r3, [r3, #42] @ 0x2a
80011b4: b29b uxth r3, r3
80011b6: 2b00 cmp r3, #0
80011b8: d034 beq.n 8001224 <HAL_I2C_Mem_Read+0x1d0>
80011ba: 68fb ldr r3, [r7, #12]
80011bc: 8d1b ldrh r3, [r3, #40] @ 0x28
80011be: 2b00 cmp r3, #0
80011c0: d130 bne.n 8001224 <HAL_I2C_Mem_Read+0x1d0>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
80011c2: 697b ldr r3, [r7, #20]
80011c4: 9300 str r3, [sp, #0]
80011c6: 6abb ldr r3, [r7, #40] @ 0x28
80011c8: 2200 movs r2, #0
80011ca: 2180 movs r1, #128 @ 0x80
80011cc: 68f8 ldr r0, [r7, #12]
80011ce: f000 f927 bl 8001420 <I2C_WaitOnFlagUntilTimeout>
80011d2: 4603 mov r3, r0
80011d4: 2b00 cmp r3, #0
80011d6: d001 beq.n 80011dc <HAL_I2C_Mem_Read+0x188>
{
return HAL_ERROR;
80011d8: 2301 movs r3, #1
80011da: e04d b.n 8001278 <HAL_I2C_Mem_Read+0x224>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80011dc: 68fb ldr r3, [r7, #12]
80011de: 8d5b ldrh r3, [r3, #42] @ 0x2a
80011e0: b29b uxth r3, r3
80011e2: 2bff cmp r3, #255 @ 0xff
80011e4: d90e bls.n 8001204 <HAL_I2C_Mem_Read+0x1b0>
{
hi2c->XferSize = 1U;
80011e6: 68fb ldr r3, [r7, #12]
80011e8: 2201 movs r2, #1
80011ea: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
80011ec: 68fb ldr r3, [r7, #12]
80011ee: 8d1b ldrh r3, [r3, #40] @ 0x28
80011f0: b2da uxtb r2, r3
80011f2: 8979 ldrh r1, [r7, #10]
80011f4: 2300 movs r3, #0
80011f6: 9300 str r3, [sp, #0]
80011f8: f04f 7380 mov.w r3, #16777216 @ 0x1000000
80011fc: 68f8 ldr r0, [r7, #12]
80011fe: f000 fad3 bl 80017a8 <I2C_TransferConfig>
8001202: e00f b.n 8001224 <HAL_I2C_Mem_Read+0x1d0>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8001204: 68fb ldr r3, [r7, #12]
8001206: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001208: b29a uxth r2, r3
800120a: 68fb ldr r3, [r7, #12]
800120c: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
800120e: 68fb ldr r3, [r7, #12]
8001210: 8d1b ldrh r3, [r3, #40] @ 0x28
8001212: b2da uxtb r2, r3
8001214: 8979 ldrh r1, [r7, #10]
8001216: 2300 movs r3, #0
8001218: 9300 str r3, [sp, #0]
800121a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
800121e: 68f8 ldr r0, [r7, #12]
8001220: f000 fac2 bl 80017a8 <I2C_TransferConfig>
I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
8001224: 68fb ldr r3, [r7, #12]
8001226: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001228: b29b uxth r3, r3
800122a: 2b00 cmp r3, #0
800122c: d19a bne.n 8001164 <HAL_I2C_Mem_Read+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800122e: 697a ldr r2, [r7, #20]
8001230: 6ab9 ldr r1, [r7, #40] @ 0x28
8001232: 68f8 ldr r0, [r7, #12]
8001234: f000 f994 bl 8001560 <I2C_WaitOnSTOPFlagUntilTimeout>
8001238: 4603 mov r3, r0
800123a: 2b00 cmp r3, #0
800123c: d001 beq.n 8001242 <HAL_I2C_Mem_Read+0x1ee>
{
return HAL_ERROR;
800123e: 2301 movs r3, #1
8001240: e01a b.n 8001278 <HAL_I2C_Mem_Read+0x224>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8001242: 68fb ldr r3, [r7, #12]
8001244: 681b ldr r3, [r3, #0]
8001246: 2220 movs r2, #32
8001248: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
800124a: 68fb ldr r3, [r7, #12]
800124c: 681b ldr r3, [r3, #0]
800124e: 6859 ldr r1, [r3, #4]
8001250: 68fb ldr r3, [r7, #12]
8001252: 681a ldr r2, [r3, #0]
8001254: 4b0b ldr r3, [pc, #44] @ (8001284 <HAL_I2C_Mem_Read+0x230>)
8001256: 400b ands r3, r1
8001258: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
800125a: 68fb ldr r3, [r7, #12]
800125c: 2220 movs r2, #32
800125e: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001262: 68fb ldr r3, [r7, #12]
8001264: 2200 movs r2, #0
8001266: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800126a: 68fb ldr r3, [r7, #12]
800126c: 2200 movs r2, #0
800126e: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8001272: 2300 movs r3, #0
8001274: e000 b.n 8001278 <HAL_I2C_Mem_Read+0x224>
}
else
{
return HAL_BUSY;
8001276: 2302 movs r3, #2
}
}
8001278: 4618 mov r0, r3
800127a: 3718 adds r7, #24
800127c: 46bd mov sp, r7
800127e: bd80 pop {r7, pc}
8001280: 80002400 .word 0x80002400
8001284: fe00e800 .word 0xfe00e800
08001288 <I2C_RequestMemoryWrite>:
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
8001288: b580 push {r7, lr}
800128a: b086 sub sp, #24
800128c: af02 add r7, sp, #8
800128e: 60f8 str r0, [r7, #12]
8001290: 4608 mov r0, r1
8001292: 4611 mov r1, r2
8001294: 461a mov r2, r3
8001296: 4603 mov r3, r0
8001298: 817b strh r3, [r7, #10]
800129a: 460b mov r3, r1
800129c: 813b strh r3, [r7, #8]
800129e: 4613 mov r3, r2
80012a0: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
80012a2: 88fb ldrh r3, [r7, #6]
80012a4: b2da uxtb r2, r3
80012a6: 8979 ldrh r1, [r7, #10]
80012a8: 4b20 ldr r3, [pc, #128] @ (800132c <I2C_RequestMemoryWrite+0xa4>)
80012aa: 9300 str r3, [sp, #0]
80012ac: f04f 7380 mov.w r3, #16777216 @ 0x1000000
80012b0: 68f8 ldr r0, [r7, #12]
80012b2: f000 fa79 bl 80017a8 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
80012b6: 69fa ldr r2, [r7, #28]
80012b8: 69b9 ldr r1, [r7, #24]
80012ba: 68f8 ldr r0, [r7, #12]
80012bc: f000 f909 bl 80014d2 <I2C_WaitOnTXISFlagUntilTimeout>
80012c0: 4603 mov r3, r0
80012c2: 2b00 cmp r3, #0
80012c4: d001 beq.n 80012ca <I2C_RequestMemoryWrite+0x42>
{
return HAL_ERROR;
80012c6: 2301 movs r3, #1
80012c8: e02c b.n 8001324 <I2C_RequestMemoryWrite+0x9c>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
80012ca: 88fb ldrh r3, [r7, #6]
80012cc: 2b01 cmp r3, #1
80012ce: d105 bne.n 80012dc <I2C_RequestMemoryWrite+0x54>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
80012d0: 893b ldrh r3, [r7, #8]
80012d2: b2da uxtb r2, r3
80012d4: 68fb ldr r3, [r7, #12]
80012d6: 681b ldr r3, [r3, #0]
80012d8: 629a str r2, [r3, #40] @ 0x28
80012da: e015 b.n 8001308 <I2C_RequestMemoryWrite+0x80>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
80012dc: 893b ldrh r3, [r7, #8]
80012de: 0a1b lsrs r3, r3, #8
80012e0: b29b uxth r3, r3
80012e2: b2da uxtb r2, r3
80012e4: 68fb ldr r3, [r7, #12]
80012e6: 681b ldr r3, [r3, #0]
80012e8: 629a str r2, [r3, #40] @ 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
80012ea: 69fa ldr r2, [r7, #28]
80012ec: 69b9 ldr r1, [r7, #24]
80012ee: 68f8 ldr r0, [r7, #12]
80012f0: f000 f8ef bl 80014d2 <I2C_WaitOnTXISFlagUntilTimeout>
80012f4: 4603 mov r3, r0
80012f6: 2b00 cmp r3, #0
80012f8: d001 beq.n 80012fe <I2C_RequestMemoryWrite+0x76>
{
return HAL_ERROR;
80012fa: 2301 movs r3, #1
80012fc: e012 b.n 8001324 <I2C_RequestMemoryWrite+0x9c>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
80012fe: 893b ldrh r3, [r7, #8]
8001300: b2da uxtb r2, r3
8001302: 68fb ldr r3, [r7, #12]
8001304: 681b ldr r3, [r3, #0]
8001306: 629a str r2, [r3, #40] @ 0x28
}
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
8001308: 69fb ldr r3, [r7, #28]
800130a: 9300 str r3, [sp, #0]
800130c: 69bb ldr r3, [r7, #24]
800130e: 2200 movs r2, #0
8001310: 2180 movs r1, #128 @ 0x80
8001312: 68f8 ldr r0, [r7, #12]
8001314: f000 f884 bl 8001420 <I2C_WaitOnFlagUntilTimeout>
8001318: 4603 mov r3, r0
800131a: 2b00 cmp r3, #0
800131c: d001 beq.n 8001322 <I2C_RequestMemoryWrite+0x9a>
{
return HAL_ERROR;
800131e: 2301 movs r3, #1
8001320: e000 b.n 8001324 <I2C_RequestMemoryWrite+0x9c>
}
return HAL_OK;
8001322: 2300 movs r3, #0
}
8001324: 4618 mov r0, r3
8001326: 3710 adds r7, #16
8001328: 46bd mov sp, r7
800132a: bd80 pop {r7, pc}
800132c: 80002000 .word 0x80002000
08001330 <I2C_RequestMemoryRead>:
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
8001330: b580 push {r7, lr}
8001332: b086 sub sp, #24
8001334: af02 add r7, sp, #8
8001336: 60f8 str r0, [r7, #12]
8001338: 4608 mov r0, r1
800133a: 4611 mov r1, r2
800133c: 461a mov r2, r3
800133e: 4603 mov r3, r0
8001340: 817b strh r3, [r7, #10]
8001342: 460b mov r3, r1
8001344: 813b strh r3, [r7, #8]
8001346: 4613 mov r3, r2
8001348: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
800134a: 88fb ldrh r3, [r7, #6]
800134c: b2da uxtb r2, r3
800134e: 8979 ldrh r1, [r7, #10]
8001350: 4b20 ldr r3, [pc, #128] @ (80013d4 <I2C_RequestMemoryRead+0xa4>)
8001352: 9300 str r3, [sp, #0]
8001354: 2300 movs r3, #0
8001356: 68f8 ldr r0, [r7, #12]
8001358: f000 fa26 bl 80017a8 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
800135c: 69fa ldr r2, [r7, #28]
800135e: 69b9 ldr r1, [r7, #24]
8001360: 68f8 ldr r0, [r7, #12]
8001362: f000 f8b6 bl 80014d2 <I2C_WaitOnTXISFlagUntilTimeout>
8001366: 4603 mov r3, r0
8001368: 2b00 cmp r3, #0
800136a: d001 beq.n 8001370 <I2C_RequestMemoryRead+0x40>
{
return HAL_ERROR;
800136c: 2301 movs r3, #1
800136e: e02c b.n 80013ca <I2C_RequestMemoryRead+0x9a>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8001370: 88fb ldrh r3, [r7, #6]
8001372: 2b01 cmp r3, #1
8001374: d105 bne.n 8001382 <I2C_RequestMemoryRead+0x52>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8001376: 893b ldrh r3, [r7, #8]
8001378: b2da uxtb r2, r3
800137a: 68fb ldr r3, [r7, #12]
800137c: 681b ldr r3, [r3, #0]
800137e: 629a str r2, [r3, #40] @ 0x28
8001380: e015 b.n 80013ae <I2C_RequestMemoryRead+0x7e>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8001382: 893b ldrh r3, [r7, #8]
8001384: 0a1b lsrs r3, r3, #8
8001386: b29b uxth r3, r3
8001388: b2da uxtb r2, r3
800138a: 68fb ldr r3, [r7, #12]
800138c: 681b ldr r3, [r3, #0]
800138e: 629a str r2, [r3, #40] @ 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8001390: 69fa ldr r2, [r7, #28]
8001392: 69b9 ldr r1, [r7, #24]
8001394: 68f8 ldr r0, [r7, #12]
8001396: f000 f89c bl 80014d2 <I2C_WaitOnTXISFlagUntilTimeout>
800139a: 4603 mov r3, r0
800139c: 2b00 cmp r3, #0
800139e: d001 beq.n 80013a4 <I2C_RequestMemoryRead+0x74>
{
return HAL_ERROR;
80013a0: 2301 movs r3, #1
80013a2: e012 b.n 80013ca <I2C_RequestMemoryRead+0x9a>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
80013a4: 893b ldrh r3, [r7, #8]
80013a6: b2da uxtb r2, r3
80013a8: 68fb ldr r3, [r7, #12]
80013aa: 681b ldr r3, [r3, #0]
80013ac: 629a str r2, [r3, #40] @ 0x28
}
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
80013ae: 69fb ldr r3, [r7, #28]
80013b0: 9300 str r3, [sp, #0]
80013b2: 69bb ldr r3, [r7, #24]
80013b4: 2200 movs r2, #0
80013b6: 2140 movs r1, #64 @ 0x40
80013b8: 68f8 ldr r0, [r7, #12]
80013ba: f000 f831 bl 8001420 <I2C_WaitOnFlagUntilTimeout>
80013be: 4603 mov r3, r0
80013c0: 2b00 cmp r3, #0
80013c2: d001 beq.n 80013c8 <I2C_RequestMemoryRead+0x98>
{
return HAL_ERROR;
80013c4: 2301 movs r3, #1
80013c6: e000 b.n 80013ca <I2C_RequestMemoryRead+0x9a>
}
return HAL_OK;
80013c8: 2300 movs r3, #0
}
80013ca: 4618 mov r0, r3
80013cc: 3710 adds r7, #16
80013ce: 46bd mov sp, r7
80013d0: bd80 pop {r7, pc}
80013d2: bf00 nop
80013d4: 80002000 .word 0x80002000
080013d8 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
80013d8: b480 push {r7}
80013da: b083 sub sp, #12
80013dc: af00 add r7, sp, #0
80013de: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
80013e0: 687b ldr r3, [r7, #4]
80013e2: 681b ldr r3, [r3, #0]
80013e4: 699b ldr r3, [r3, #24]
80013e6: f003 0302 and.w r3, r3, #2
80013ea: 2b02 cmp r3, #2
80013ec: d103 bne.n 80013f6 <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
80013ee: 687b ldr r3, [r7, #4]
80013f0: 681b ldr r3, [r3, #0]
80013f2: 2200 movs r2, #0
80013f4: 629a str r2, [r3, #40] @ 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
80013f6: 687b ldr r3, [r7, #4]
80013f8: 681b ldr r3, [r3, #0]
80013fa: 699b ldr r3, [r3, #24]
80013fc: f003 0301 and.w r3, r3, #1
8001400: 2b01 cmp r3, #1
8001402: d007 beq.n 8001414 <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
8001404: 687b ldr r3, [r7, #4]
8001406: 681b ldr r3, [r3, #0]
8001408: 699a ldr r2, [r3, #24]
800140a: 687b ldr r3, [r7, #4]
800140c: 681b ldr r3, [r3, #0]
800140e: f042 0201 orr.w r2, r2, #1
8001412: 619a str r2, [r3, #24]
}
}
8001414: bf00 nop
8001416: 370c adds r7, #12
8001418: 46bd mov sp, r7
800141a: f85d 7b04 ldr.w r7, [sp], #4
800141e: 4770 bx lr
08001420 <I2C_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
8001420: b580 push {r7, lr}
8001422: b084 sub sp, #16
8001424: af00 add r7, sp, #0
8001426: 60f8 str r0, [r7, #12]
8001428: 60b9 str r1, [r7, #8]
800142a: 603b str r3, [r7, #0]
800142c: 4613 mov r3, r2
800142e: 71fb strb r3, [r7, #7]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8001430: e03b b.n 80014aa <I2C_WaitOnFlagUntilTimeout+0x8a>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
8001432: 69ba ldr r2, [r7, #24]
8001434: 6839 ldr r1, [r7, #0]
8001436: 68f8 ldr r0, [r7, #12]
8001438: f000 f8d6 bl 80015e8 <I2C_IsErrorOccurred>
800143c: 4603 mov r3, r0
800143e: 2b00 cmp r3, #0
8001440: d001 beq.n 8001446 <I2C_WaitOnFlagUntilTimeout+0x26>
{
return HAL_ERROR;
8001442: 2301 movs r3, #1
8001444: e041 b.n 80014ca <I2C_WaitOnFlagUntilTimeout+0xaa>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8001446: 683b ldr r3, [r7, #0]
8001448: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800144c: d02d beq.n 80014aa <I2C_WaitOnFlagUntilTimeout+0x8a>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800144e: f7ff f965 bl 800071c <HAL_GetTick>
8001452: 4602 mov r2, r0
8001454: 69bb ldr r3, [r7, #24]
8001456: 1ad3 subs r3, r2, r3
8001458: 683a ldr r2, [r7, #0]
800145a: 429a cmp r2, r3
800145c: d302 bcc.n 8001464 <I2C_WaitOnFlagUntilTimeout+0x44>
800145e: 683b ldr r3, [r7, #0]
8001460: 2b00 cmp r3, #0
8001462: d122 bne.n 80014aa <I2C_WaitOnFlagUntilTimeout+0x8a>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
8001464: 68fb ldr r3, [r7, #12]
8001466: 681b ldr r3, [r3, #0]
8001468: 699a ldr r2, [r3, #24]
800146a: 68bb ldr r3, [r7, #8]
800146c: 4013 ands r3, r2
800146e: 68ba ldr r2, [r7, #8]
8001470: 429a cmp r2, r3
8001472: bf0c ite eq
8001474: 2301 moveq r3, #1
8001476: 2300 movne r3, #0
8001478: b2db uxtb r3, r3
800147a: 461a mov r2, r3
800147c: 79fb ldrb r3, [r7, #7]
800147e: 429a cmp r2, r3
8001480: d113 bne.n 80014aa <I2C_WaitOnFlagUntilTimeout+0x8a>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8001482: 68fb ldr r3, [r7, #12]
8001484: 6c5b ldr r3, [r3, #68] @ 0x44
8001486: f043 0220 orr.w r2, r3, #32
800148a: 68fb ldr r3, [r7, #12]
800148c: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
800148e: 68fb ldr r3, [r7, #12]
8001490: 2220 movs r2, #32
8001492: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001496: 68fb ldr r3, [r7, #12]
8001498: 2200 movs r2, #0
800149a: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800149e: 68fb ldr r3, [r7, #12]
80014a0: 2200 movs r2, #0
80014a2: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
80014a6: 2301 movs r3, #1
80014a8: e00f b.n 80014ca <I2C_WaitOnFlagUntilTimeout+0xaa>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
80014aa: 68fb ldr r3, [r7, #12]
80014ac: 681b ldr r3, [r3, #0]
80014ae: 699a ldr r2, [r3, #24]
80014b0: 68bb ldr r3, [r7, #8]
80014b2: 4013 ands r3, r2
80014b4: 68ba ldr r2, [r7, #8]
80014b6: 429a cmp r2, r3
80014b8: bf0c ite eq
80014ba: 2301 moveq r3, #1
80014bc: 2300 movne r3, #0
80014be: b2db uxtb r3, r3
80014c0: 461a mov r2, r3
80014c2: 79fb ldrb r3, [r7, #7]
80014c4: 429a cmp r2, r3
80014c6: d0b4 beq.n 8001432 <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
80014c8: 2300 movs r3, #0
}
80014ca: 4618 mov r0, r3
80014cc: 3710 adds r7, #16
80014ce: 46bd mov sp, r7
80014d0: bd80 pop {r7, pc}
080014d2 <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
80014d2: b580 push {r7, lr}
80014d4: b084 sub sp, #16
80014d6: af00 add r7, sp, #0
80014d8: 60f8 str r0, [r7, #12]
80014da: 60b9 str r1, [r7, #8]
80014dc: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
80014de: e033 b.n 8001548 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
80014e0: 687a ldr r2, [r7, #4]
80014e2: 68b9 ldr r1, [r7, #8]
80014e4: 68f8 ldr r0, [r7, #12]
80014e6: f000 f87f bl 80015e8 <I2C_IsErrorOccurred>
80014ea: 4603 mov r3, r0
80014ec: 2b00 cmp r3, #0
80014ee: d001 beq.n 80014f4 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
80014f0: 2301 movs r3, #1
80014f2: e031 b.n 8001558 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80014f4: 68bb ldr r3, [r7, #8]
80014f6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80014fa: d025 beq.n 8001548 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80014fc: f7ff f90e bl 800071c <HAL_GetTick>
8001500: 4602 mov r2, r0
8001502: 687b ldr r3, [r7, #4]
8001504: 1ad3 subs r3, r2, r3
8001506: 68ba ldr r2, [r7, #8]
8001508: 429a cmp r2, r3
800150a: d302 bcc.n 8001512 <I2C_WaitOnTXISFlagUntilTimeout+0x40>
800150c: 68bb ldr r3, [r7, #8]
800150e: 2b00 cmp r3, #0
8001510: d11a bne.n 8001548 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
8001512: 68fb ldr r3, [r7, #12]
8001514: 681b ldr r3, [r3, #0]
8001516: 699b ldr r3, [r3, #24]
8001518: f003 0302 and.w r3, r3, #2
800151c: 2b02 cmp r3, #2
800151e: d013 beq.n 8001548 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8001520: 68fb ldr r3, [r7, #12]
8001522: 6c5b ldr r3, [r3, #68] @ 0x44
8001524: f043 0220 orr.w r2, r3, #32
8001528: 68fb ldr r3, [r7, #12]
800152a: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
800152c: 68fb ldr r3, [r7, #12]
800152e: 2220 movs r2, #32
8001530: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001534: 68fb ldr r3, [r7, #12]
8001536: 2200 movs r2, #0
8001538: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800153c: 68fb ldr r3, [r7, #12]
800153e: 2200 movs r2, #0
8001540: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8001544: 2301 movs r3, #1
8001546: e007 b.n 8001558 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8001548: 68fb ldr r3, [r7, #12]
800154a: 681b ldr r3, [r3, #0]
800154c: 699b ldr r3, [r3, #24]
800154e: f003 0302 and.w r3, r3, #2
8001552: 2b02 cmp r3, #2
8001554: d1c4 bne.n 80014e0 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
8001556: 2300 movs r3, #0
}
8001558: 4618 mov r0, r3
800155a: 3710 adds r7, #16
800155c: 46bd mov sp, r7
800155e: bd80 pop {r7, pc}
08001560 <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
8001560: b580 push {r7, lr}
8001562: b084 sub sp, #16
8001564: af00 add r7, sp, #0
8001566: 60f8 str r0, [r7, #12]
8001568: 60b9 str r1, [r7, #8]
800156a: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
800156c: e02f b.n 80015ce <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
800156e: 687a ldr r2, [r7, #4]
8001570: 68b9 ldr r1, [r7, #8]
8001572: 68f8 ldr r0, [r7, #12]
8001574: f000 f838 bl 80015e8 <I2C_IsErrorOccurred>
8001578: 4603 mov r3, r0
800157a: 2b00 cmp r3, #0
800157c: d001 beq.n 8001582 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
800157e: 2301 movs r3, #1
8001580: e02d b.n 80015de <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8001582: f7ff f8cb bl 800071c <HAL_GetTick>
8001586: 4602 mov r2, r0
8001588: 687b ldr r3, [r7, #4]
800158a: 1ad3 subs r3, r2, r3
800158c: 68ba ldr r2, [r7, #8]
800158e: 429a cmp r2, r3
8001590: d302 bcc.n 8001598 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
8001592: 68bb ldr r3, [r7, #8]
8001594: 2b00 cmp r3, #0
8001596: d11a bne.n 80015ce <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
8001598: 68fb ldr r3, [r7, #12]
800159a: 681b ldr r3, [r3, #0]
800159c: 699b ldr r3, [r3, #24]
800159e: f003 0320 and.w r3, r3, #32
80015a2: 2b20 cmp r3, #32
80015a4: d013 beq.n 80015ce <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80015a6: 68fb ldr r3, [r7, #12]
80015a8: 6c5b ldr r3, [r3, #68] @ 0x44
80015aa: f043 0220 orr.w r2, r3, #32
80015ae: 68fb ldr r3, [r7, #12]
80015b0: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
80015b2: 68fb ldr r3, [r7, #12]
80015b4: 2220 movs r2, #32
80015b6: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
80015ba: 68fb ldr r3, [r7, #12]
80015bc: 2200 movs r2, #0
80015be: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80015c2: 68fb ldr r3, [r7, #12]
80015c4: 2200 movs r2, #0
80015c6: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
80015ca: 2301 movs r3, #1
80015cc: e007 b.n 80015de <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
80015ce: 68fb ldr r3, [r7, #12]
80015d0: 681b ldr r3, [r3, #0]
80015d2: 699b ldr r3, [r3, #24]
80015d4: f003 0320 and.w r3, r3, #32
80015d8: 2b20 cmp r3, #32
80015da: d1c8 bne.n 800156e <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
80015dc: 2300 movs r3, #0
}
80015de: 4618 mov r0, r3
80015e0: 3710 adds r7, #16
80015e2: 46bd mov sp, r7
80015e4: bd80 pop {r7, pc}
...
080015e8 <I2C_IsErrorOccurred>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
80015e8: b580 push {r7, lr}
80015ea: b08a sub sp, #40 @ 0x28
80015ec: af00 add r7, sp, #0
80015ee: 60f8 str r0, [r7, #12]
80015f0: 60b9 str r1, [r7, #8]
80015f2: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80015f4: 2300 movs r3, #0
80015f6: f887 3027 strb.w r3, [r7, #39] @ 0x27
uint32_t itflag = hi2c->Instance->ISR;
80015fa: 68fb ldr r3, [r7, #12]
80015fc: 681b ldr r3, [r3, #0]
80015fe: 699b ldr r3, [r3, #24]
8001600: 61bb str r3, [r7, #24]
uint32_t error_code = 0;
8001602: 2300 movs r3, #0
8001604: 623b str r3, [r7, #32]
uint32_t tickstart = Tickstart;
8001606: 687b ldr r3, [r7, #4]
8001608: 61fb str r3, [r7, #28]
uint32_t tmp1;
HAL_I2C_ModeTypeDef tmp2;
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
800160a: 69bb ldr r3, [r7, #24]
800160c: f003 0310 and.w r3, r3, #16
8001610: 2b00 cmp r3, #0
8001612: d068 beq.n 80016e6 <I2C_IsErrorOccurred+0xfe>
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8001614: 68fb ldr r3, [r7, #12]
8001616: 681b ldr r3, [r3, #0]
8001618: 2210 movs r2, #16
800161a: 61da str r2, [r3, #28]
/* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
800161c: e049 b.n 80016b2 <I2C_IsErrorOccurred+0xca>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800161e: 68bb ldr r3, [r7, #8]
8001620: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8001624: d045 beq.n 80016b2 <I2C_IsErrorOccurred+0xca>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
8001626: f7ff f879 bl 800071c <HAL_GetTick>
800162a: 4602 mov r2, r0
800162c: 69fb ldr r3, [r7, #28]
800162e: 1ad3 subs r3, r2, r3
8001630: 68ba ldr r2, [r7, #8]
8001632: 429a cmp r2, r3
8001634: d302 bcc.n 800163c <I2C_IsErrorOccurred+0x54>
8001636: 68bb ldr r3, [r7, #8]
8001638: 2b00 cmp r3, #0
800163a: d13a bne.n 80016b2 <I2C_IsErrorOccurred+0xca>
{
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
800163c: 68fb ldr r3, [r7, #12]
800163e: 681b ldr r3, [r3, #0]
8001640: 685b ldr r3, [r3, #4]
8001642: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001646: 617b str r3, [r7, #20]
tmp2 = hi2c->Mode;
8001648: 68fb ldr r3, [r7, #12]
800164a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
800164e: 74fb strb r3, [r7, #19]
/* In case of I2C still busy, try to regenerate a STOP manually */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
8001650: 68fb ldr r3, [r7, #12]
8001652: 681b ldr r3, [r3, #0]
8001654: 699b ldr r3, [r3, #24]
8001656: f403 4300 and.w r3, r3, #32768 @ 0x8000
800165a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800165e: d121 bne.n 80016a4 <I2C_IsErrorOccurred+0xbc>
8001660: 697b ldr r3, [r7, #20]
8001662: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8001666: d01d beq.n 80016a4 <I2C_IsErrorOccurred+0xbc>
(tmp1 != I2C_CR2_STOP) && \
8001668: 7cfb ldrb r3, [r7, #19]
800166a: 2b20 cmp r3, #32
800166c: d01a beq.n 80016a4 <I2C_IsErrorOccurred+0xbc>
(tmp2 != HAL_I2C_MODE_SLAVE))
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
800166e: 68fb ldr r3, [r7, #12]
8001670: 681b ldr r3, [r3, #0]
8001672: 685a ldr r2, [r3, #4]
8001674: 68fb ldr r3, [r7, #12]
8001676: 681b ldr r3, [r3, #0]
8001678: f442 4280 orr.w r2, r2, #16384 @ 0x4000
800167c: 605a str r2, [r3, #4]
/* Update Tick with new reference */
tickstart = HAL_GetTick();
800167e: f7ff f84d bl 800071c <HAL_GetTick>
8001682: 61f8 str r0, [r7, #28]
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8001684: e00e b.n 80016a4 <I2C_IsErrorOccurred+0xbc>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
8001686: f7ff f849 bl 800071c <HAL_GetTick>
800168a: 4602 mov r2, r0
800168c: 69fb ldr r3, [r7, #28]
800168e: 1ad3 subs r3, r2, r3
8001690: 2b19 cmp r3, #25
8001692: d907 bls.n 80016a4 <I2C_IsErrorOccurred+0xbc>
{
error_code |= HAL_I2C_ERROR_TIMEOUT;
8001694: 6a3b ldr r3, [r7, #32]
8001696: f043 0320 orr.w r3, r3, #32
800169a: 623b str r3, [r7, #32]
status = HAL_ERROR;
800169c: 2301 movs r3, #1
800169e: f887 3027 strb.w r3, [r7, #39] @ 0x27
break;
80016a2: e006 b.n 80016b2 <I2C_IsErrorOccurred+0xca>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
80016a4: 68fb ldr r3, [r7, #12]
80016a6: 681b ldr r3, [r3, #0]
80016a8: 699b ldr r3, [r3, #24]
80016aa: f003 0320 and.w r3, r3, #32
80016ae: 2b20 cmp r3, #32
80016b0: d1e9 bne.n 8001686 <I2C_IsErrorOccurred+0x9e>
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
80016b2: 68fb ldr r3, [r7, #12]
80016b4: 681b ldr r3, [r3, #0]
80016b6: 699b ldr r3, [r3, #24]
80016b8: f003 0320 and.w r3, r3, #32
80016bc: 2b20 cmp r3, #32
80016be: d003 beq.n 80016c8 <I2C_IsErrorOccurred+0xe0>
80016c0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80016c4: 2b00 cmp r3, #0
80016c6: d0aa beq.n 800161e <I2C_IsErrorOccurred+0x36>
}
}
}
/* In case STOP Flag is detected, clear it */
if (status == HAL_OK)
80016c8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
80016cc: 2b00 cmp r3, #0
80016ce: d103 bne.n 80016d8 <I2C_IsErrorOccurred+0xf0>
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
80016d0: 68fb ldr r3, [r7, #12]
80016d2: 681b ldr r3, [r3, #0]
80016d4: 2220 movs r2, #32
80016d6: 61da str r2, [r3, #28]
}
error_code |= HAL_I2C_ERROR_AF;
80016d8: 6a3b ldr r3, [r7, #32]
80016da: f043 0304 orr.w r3, r3, #4
80016de: 623b str r3, [r7, #32]
status = HAL_ERROR;
80016e0: 2301 movs r3, #1
80016e2: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
/* Refresh Content of Status register */
itflag = hi2c->Instance->ISR;
80016e6: 68fb ldr r3, [r7, #12]
80016e8: 681b ldr r3, [r3, #0]
80016ea: 699b ldr r3, [r3, #24]
80016ec: 61bb str r3, [r7, #24]
/* Then verify if an additional errors occurs */
/* Check if a Bus error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
80016ee: 69bb ldr r3, [r7, #24]
80016f0: f403 7380 and.w r3, r3, #256 @ 0x100
80016f4: 2b00 cmp r3, #0
80016f6: d00b beq.n 8001710 <I2C_IsErrorOccurred+0x128>
{
error_code |= HAL_I2C_ERROR_BERR;
80016f8: 6a3b ldr r3, [r7, #32]
80016fa: f043 0301 orr.w r3, r3, #1
80016fe: 623b str r3, [r7, #32]
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
8001700: 68fb ldr r3, [r7, #12]
8001702: 681b ldr r3, [r3, #0]
8001704: f44f 7280 mov.w r2, #256 @ 0x100
8001708: 61da str r2, [r3, #28]
status = HAL_ERROR;
800170a: 2301 movs r3, #1
800170c: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
/* Check if an Over-Run/Under-Run error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
8001710: 69bb ldr r3, [r7, #24]
8001712: f403 6380 and.w r3, r3, #1024 @ 0x400
8001716: 2b00 cmp r3, #0
8001718: d00b beq.n 8001732 <I2C_IsErrorOccurred+0x14a>
{
error_code |= HAL_I2C_ERROR_OVR;
800171a: 6a3b ldr r3, [r7, #32]
800171c: f043 0308 orr.w r3, r3, #8
8001720: 623b str r3, [r7, #32]
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
8001722: 68fb ldr r3, [r7, #12]
8001724: 681b ldr r3, [r3, #0]
8001726: f44f 6280 mov.w r2, #1024 @ 0x400
800172a: 61da str r2, [r3, #28]
status = HAL_ERROR;
800172c: 2301 movs r3, #1
800172e: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
/* Check if an Arbitration Loss error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
8001732: 69bb ldr r3, [r7, #24]
8001734: f403 7300 and.w r3, r3, #512 @ 0x200
8001738: 2b00 cmp r3, #0
800173a: d00b beq.n 8001754 <I2C_IsErrorOccurred+0x16c>
{
error_code |= HAL_I2C_ERROR_ARLO;
800173c: 6a3b ldr r3, [r7, #32]
800173e: f043 0302 orr.w r3, r3, #2
8001742: 623b str r3, [r7, #32]
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
8001744: 68fb ldr r3, [r7, #12]
8001746: 681b ldr r3, [r3, #0]
8001748: f44f 7200 mov.w r2, #512 @ 0x200
800174c: 61da str r2, [r3, #28]
status = HAL_ERROR;
800174e: 2301 movs r3, #1
8001750: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
if (status != HAL_OK)
8001754: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
8001758: 2b00 cmp r3, #0
800175a: d01c beq.n 8001796 <I2C_IsErrorOccurred+0x1ae>
{
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
800175c: 68f8 ldr r0, [r7, #12]
800175e: f7ff fe3b bl 80013d8 <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8001762: 68fb ldr r3, [r7, #12]
8001764: 681b ldr r3, [r3, #0]
8001766: 6859 ldr r1, [r3, #4]
8001768: 68fb ldr r3, [r7, #12]
800176a: 681a ldr r2, [r3, #0]
800176c: 4b0d ldr r3, [pc, #52] @ (80017a4 <I2C_IsErrorOccurred+0x1bc>)
800176e: 400b ands r3, r1
8001770: 6053 str r3, [r2, #4]
hi2c->ErrorCode |= error_code;
8001772: 68fb ldr r3, [r7, #12]
8001774: 6c5a ldr r2, [r3, #68] @ 0x44
8001776: 6a3b ldr r3, [r7, #32]
8001778: 431a orrs r2, r3
800177a: 68fb ldr r3, [r7, #12]
800177c: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
800177e: 68fb ldr r3, [r7, #12]
8001780: 2220 movs r2, #32
8001782: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8001786: 68fb ldr r3, [r7, #12]
8001788: 2200 movs r2, #0
800178a: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800178e: 68fb ldr r3, [r7, #12]
8001790: 2200 movs r2, #0
8001792: f883 2040 strb.w r2, [r3, #64] @ 0x40
}
return status;
8001796: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
}
800179a: 4618 mov r0, r3
800179c: 3728 adds r7, #40 @ 0x28
800179e: 46bd mov sp, r7
80017a0: bd80 pop {r7, pc}
80017a2: bf00 nop
80017a4: fe00e800 .word 0xfe00e800
080017a8 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
80017a8: b480 push {r7}
80017aa: b087 sub sp, #28
80017ac: af00 add r7, sp, #0
80017ae: 60f8 str r0, [r7, #12]
80017b0: 607b str r3, [r7, #4]
80017b2: 460b mov r3, r1
80017b4: 817b strh r3, [r7, #10]
80017b6: 4613 mov r3, r2
80017b8: 727b strb r3, [r7, #9]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
80017ba: 897b ldrh r3, [r7, #10]
80017bc: f3c3 0209 ubfx r2, r3, #0, #10
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
80017c0: 7a7b ldrb r3, [r7, #9]
80017c2: 041b lsls r3, r3, #16
80017c4: f403 037f and.w r3, r3, #16711680 @ 0xff0000
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
80017c8: 431a orrs r2, r3
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
80017ca: 687b ldr r3, [r7, #4]
80017cc: 431a orrs r2, r3
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
80017ce: 6a3b ldr r3, [r7, #32]
80017d0: 4313 orrs r3, r2
80017d2: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
80017d6: 617b str r3, [r7, #20]
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
80017d8: 68fb ldr r3, [r7, #12]
80017da: 681b ldr r3, [r3, #0]
80017dc: 685a ldr r2, [r3, #4]
80017de: 6a3b ldr r3, [r7, #32]
80017e0: 0d5b lsrs r3, r3, #21
80017e2: f403 6180 and.w r1, r3, #1024 @ 0x400
80017e6: 4b08 ldr r3, [pc, #32] @ (8001808 <I2C_TransferConfig+0x60>)
80017e8: 430b orrs r3, r1
80017ea: 43db mvns r3, r3
80017ec: ea02 0103 and.w r1, r2, r3
80017f0: 68fb ldr r3, [r7, #12]
80017f2: 681b ldr r3, [r3, #0]
80017f4: 697a ldr r2, [r7, #20]
80017f6: 430a orrs r2, r1
80017f8: 605a str r2, [r3, #4]
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
80017fa: bf00 nop
80017fc: 371c adds r7, #28
80017fe: 46bd mov sp, r7
8001800: f85d 7b04 ldr.w r7, [sp], #4
8001804: 4770 bx lr
8001806: bf00 nop
8001808: 03ff63ff .word 0x03ff63ff
0800180c <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
800180c: b480 push {r7}
800180e: b083 sub sp, #12
8001810: af00 add r7, sp, #0
8001812: 6078 str r0, [r7, #4]
8001814: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8001816: 687b ldr r3, [r7, #4]
8001818: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800181c: b2db uxtb r3, r3
800181e: 2b20 cmp r3, #32
8001820: d138 bne.n 8001894 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8001822: 687b ldr r3, [r7, #4]
8001824: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8001828: 2b01 cmp r3, #1
800182a: d101 bne.n 8001830 <HAL_I2CEx_ConfigAnalogFilter+0x24>
800182c: 2302 movs r3, #2
800182e: e032 b.n 8001896 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
8001830: 687b ldr r3, [r7, #4]
8001832: 2201 movs r2, #1
8001834: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8001838: 687b ldr r3, [r7, #4]
800183a: 2224 movs r2, #36 @ 0x24
800183c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001840: 687b ldr r3, [r7, #4]
8001842: 681b ldr r3, [r3, #0]
8001844: 681a ldr r2, [r3, #0]
8001846: 687b ldr r3, [r7, #4]
8001848: 681b ldr r3, [r3, #0]
800184a: f022 0201 bic.w r2, r2, #1
800184e: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8001850: 687b ldr r3, [r7, #4]
8001852: 681b ldr r3, [r3, #0]
8001854: 681a ldr r2, [r3, #0]
8001856: 687b ldr r3, [r7, #4]
8001858: 681b ldr r3, [r3, #0]
800185a: f422 5280 bic.w r2, r2, #4096 @ 0x1000
800185e: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
8001860: 687b ldr r3, [r7, #4]
8001862: 681b ldr r3, [r3, #0]
8001864: 6819 ldr r1, [r3, #0]
8001866: 687b ldr r3, [r7, #4]
8001868: 681b ldr r3, [r3, #0]
800186a: 683a ldr r2, [r7, #0]
800186c: 430a orrs r2, r1
800186e: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8001870: 687b ldr r3, [r7, #4]
8001872: 681b ldr r3, [r3, #0]
8001874: 681a ldr r2, [r3, #0]
8001876: 687b ldr r3, [r7, #4]
8001878: 681b ldr r3, [r3, #0]
800187a: f042 0201 orr.w r2, r2, #1
800187e: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8001880: 687b ldr r3, [r7, #4]
8001882: 2220 movs r2, #32
8001884: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001888: 687b ldr r3, [r7, #4]
800188a: 2200 movs r2, #0
800188c: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8001890: 2300 movs r3, #0
8001892: e000 b.n 8001896 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8001894: 2302 movs r3, #2
}
}
8001896: 4618 mov r0, r3
8001898: 370c adds r7, #12
800189a: 46bd mov sp, r7
800189c: f85d 7b04 ldr.w r7, [sp], #4
80018a0: 4770 bx lr
080018a2 <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
80018a2: b480 push {r7}
80018a4: b085 sub sp, #20
80018a6: af00 add r7, sp, #0
80018a8: 6078 str r0, [r7, #4]
80018aa: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
80018ac: 687b ldr r3, [r7, #4]
80018ae: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80018b2: b2db uxtb r3, r3
80018b4: 2b20 cmp r3, #32
80018b6: d139 bne.n 800192c <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
80018b8: 687b ldr r3, [r7, #4]
80018ba: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80018be: 2b01 cmp r3, #1
80018c0: d101 bne.n 80018c6 <HAL_I2CEx_ConfigDigitalFilter+0x24>
80018c2: 2302 movs r3, #2
80018c4: e033 b.n 800192e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
80018c6: 687b ldr r3, [r7, #4]
80018c8: 2201 movs r2, #1
80018ca: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
80018ce: 687b ldr r3, [r7, #4]
80018d0: 2224 movs r2, #36 @ 0x24
80018d2: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80018d6: 687b ldr r3, [r7, #4]
80018d8: 681b ldr r3, [r3, #0]
80018da: 681a ldr r2, [r3, #0]
80018dc: 687b ldr r3, [r7, #4]
80018de: 681b ldr r3, [r3, #0]
80018e0: f022 0201 bic.w r2, r2, #1
80018e4: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
80018e6: 687b ldr r3, [r7, #4]
80018e8: 681b ldr r3, [r3, #0]
80018ea: 681b ldr r3, [r3, #0]
80018ec: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
80018ee: 68fb ldr r3, [r7, #12]
80018f0: f423 6370 bic.w r3, r3, #3840 @ 0xf00
80018f4: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
80018f6: 683b ldr r3, [r7, #0]
80018f8: 021b lsls r3, r3, #8
80018fa: 68fa ldr r2, [r7, #12]
80018fc: 4313 orrs r3, r2
80018fe: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
8001900: 687b ldr r3, [r7, #4]
8001902: 681b ldr r3, [r3, #0]
8001904: 68fa ldr r2, [r7, #12]
8001906: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8001908: 687b ldr r3, [r7, #4]
800190a: 681b ldr r3, [r3, #0]
800190c: 681a ldr r2, [r3, #0]
800190e: 687b ldr r3, [r7, #4]
8001910: 681b ldr r3, [r3, #0]
8001912: f042 0201 orr.w r2, r2, #1
8001916: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8001918: 687b ldr r3, [r7, #4]
800191a: 2220 movs r2, #32
800191c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001920: 687b ldr r3, [r7, #4]
8001922: 2200 movs r2, #0
8001924: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8001928: 2300 movs r3, #0
800192a: e000 b.n 800192e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
800192c: 2302 movs r3, #2
}
}
800192e: 4618 mov r0, r3
8001930: 3714 adds r7, #20
8001932: 46bd mov sp, r7
8001934: f85d 7b04 ldr.w r7, [sp], #4
8001938: 4770 bx lr
0800193a <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
800193a: b580 push {r7, lr}
800193c: b086 sub sp, #24
800193e: af02 add r7, sp, #8
8001940: 6078 str r0, [r7, #4]
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
8001942: 687b ldr r3, [r7, #4]
8001944: 2b00 cmp r3, #0
8001946: d101 bne.n 800194c <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8001948: 2301 movs r3, #1
800194a: e101 b.n 8001b50 <HAL_PCD_Init+0x216>
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
800194c: 687b ldr r3, [r7, #4]
800194e: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
8001952: b2db uxtb r3, r3
8001954: 2b00 cmp r3, #0
8001956: d106 bne.n 8001966 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8001958: 687b ldr r3, [r7, #4]
800195a: 2200 movs r2, #0
800195c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
8001960: 6878 ldr r0, [r7, #4]
8001962: f005 ff5b bl 800781c <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8001966: 687b ldr r3, [r7, #4]
8001968: 2203 movs r2, #3
800196a: f883 2495 strb.w r2, [r3, #1173] @ 0x495
/* Disable DMA mode for FS instance */
hpcd->Init.dma_enable = 0U;
800196e: 687b ldr r3, [r7, #4]
8001970: 2200 movs r2, #0
8001972: 719a strb r2, [r3, #6]
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
8001974: 687b ldr r3, [r7, #4]
8001976: 681b ldr r3, [r3, #0]
8001978: 4618 mov r0, r3
800197a: f002 fd3c bl 80043f6 <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
800197e: 687b ldr r3, [r7, #4]
8001980: 6818 ldr r0, [r3, #0]
8001982: 687b ldr r3, [r7, #4]
8001984: 7c1a ldrb r2, [r3, #16]
8001986: f88d 2000 strb.w r2, [sp]
800198a: 3304 adds r3, #4
800198c: cb0e ldmia r3, {r1, r2, r3}
800198e: f002 fc57 bl 8004240 <USB_CoreInit>
8001992: 4603 mov r3, r0
8001994: 2b00 cmp r3, #0
8001996: d005 beq.n 80019a4 <HAL_PCD_Init+0x6a>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8001998: 687b ldr r3, [r7, #4]
800199a: 2202 movs r2, #2
800199c: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
80019a0: 2301 movs r3, #1
80019a2: e0d5 b.n 8001b50 <HAL_PCD_Init+0x216>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
80019a4: 687b ldr r3, [r7, #4]
80019a6: 681b ldr r3, [r3, #0]
80019a8: 2100 movs r1, #0
80019aa: 4618 mov r0, r3
80019ac: f002 fd34 bl 8004418 <USB_SetCurrentMode>
80019b0: 4603 mov r3, r0
80019b2: 2b00 cmp r3, #0
80019b4: d005 beq.n 80019c2 <HAL_PCD_Init+0x88>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80019b6: 687b ldr r3, [r7, #4]
80019b8: 2202 movs r2, #2
80019ba: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
80019be: 2301 movs r3, #1
80019c0: e0c6 b.n 8001b50 <HAL_PCD_Init+0x216>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80019c2: 2300 movs r3, #0
80019c4: 73fb strb r3, [r7, #15]
80019c6: e04a b.n 8001a5e <HAL_PCD_Init+0x124>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
80019c8: 7bfa ldrb r2, [r7, #15]
80019ca: 6879 ldr r1, [r7, #4]
80019cc: 4613 mov r3, r2
80019ce: 00db lsls r3, r3, #3
80019d0: 4413 add r3, r2
80019d2: 009b lsls r3, r3, #2
80019d4: 440b add r3, r1
80019d6: 3315 adds r3, #21
80019d8: 2201 movs r2, #1
80019da: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
80019dc: 7bfa ldrb r2, [r7, #15]
80019de: 6879 ldr r1, [r7, #4]
80019e0: 4613 mov r3, r2
80019e2: 00db lsls r3, r3, #3
80019e4: 4413 add r3, r2
80019e6: 009b lsls r3, r3, #2
80019e8: 440b add r3, r1
80019ea: 3314 adds r3, #20
80019ec: 7bfa ldrb r2, [r7, #15]
80019ee: 701a strb r2, [r3, #0]
#if defined (USB_OTG_FS)
hpcd->IN_ep[i].tx_fifo_num = i;
80019f0: 7bfa ldrb r2, [r7, #15]
80019f2: 7bfb ldrb r3, [r7, #15]
80019f4: b298 uxth r0, r3
80019f6: 6879 ldr r1, [r7, #4]
80019f8: 4613 mov r3, r2
80019fa: 00db lsls r3, r3, #3
80019fc: 4413 add r3, r2
80019fe: 009b lsls r3, r3, #2
8001a00: 440b add r3, r1
8001a02: 332e adds r3, #46 @ 0x2e
8001a04: 4602 mov r2, r0
8001a06: 801a strh r2, [r3, #0]
#endif /* defined (USB_OTG_FS) */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8001a08: 7bfa ldrb r2, [r7, #15]
8001a0a: 6879 ldr r1, [r7, #4]
8001a0c: 4613 mov r3, r2
8001a0e: 00db lsls r3, r3, #3
8001a10: 4413 add r3, r2
8001a12: 009b lsls r3, r3, #2
8001a14: 440b add r3, r1
8001a16: 3318 adds r3, #24
8001a18: 2200 movs r2, #0
8001a1a: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
8001a1c: 7bfa ldrb r2, [r7, #15]
8001a1e: 6879 ldr r1, [r7, #4]
8001a20: 4613 mov r3, r2
8001a22: 00db lsls r3, r3, #3
8001a24: 4413 add r3, r2
8001a26: 009b lsls r3, r3, #2
8001a28: 440b add r3, r1
8001a2a: 331c adds r3, #28
8001a2c: 2200 movs r2, #0
8001a2e: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
8001a30: 7bfa ldrb r2, [r7, #15]
8001a32: 6879 ldr r1, [r7, #4]
8001a34: 4613 mov r3, r2
8001a36: 00db lsls r3, r3, #3
8001a38: 4413 add r3, r2
8001a3a: 009b lsls r3, r3, #2
8001a3c: 440b add r3, r1
8001a3e: 3320 adds r3, #32
8001a40: 2200 movs r2, #0
8001a42: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8001a44: 7bfa ldrb r2, [r7, #15]
8001a46: 6879 ldr r1, [r7, #4]
8001a48: 4613 mov r3, r2
8001a4a: 00db lsls r3, r3, #3
8001a4c: 4413 add r3, r2
8001a4e: 009b lsls r3, r3, #2
8001a50: 440b add r3, r1
8001a52: 3324 adds r3, #36 @ 0x24
8001a54: 2200 movs r2, #0
8001a56: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001a58: 7bfb ldrb r3, [r7, #15]
8001a5a: 3301 adds r3, #1
8001a5c: 73fb strb r3, [r7, #15]
8001a5e: 687b ldr r3, [r7, #4]
8001a60: 791b ldrb r3, [r3, #4]
8001a62: 7bfa ldrb r2, [r7, #15]
8001a64: 429a cmp r2, r3
8001a66: d3af bcc.n 80019c8 <HAL_PCD_Init+0x8e>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001a68: 2300 movs r3, #0
8001a6a: 73fb strb r3, [r7, #15]
8001a6c: e044 b.n 8001af8 <HAL_PCD_Init+0x1be>
{
hpcd->OUT_ep[i].is_in = 0U;
8001a6e: 7bfa ldrb r2, [r7, #15]
8001a70: 6879 ldr r1, [r7, #4]
8001a72: 4613 mov r3, r2
8001a74: 00db lsls r3, r3, #3
8001a76: 4413 add r3, r2
8001a78: 009b lsls r3, r3, #2
8001a7a: 440b add r3, r1
8001a7c: f203 2355 addw r3, r3, #597 @ 0x255
8001a80: 2200 movs r2, #0
8001a82: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8001a84: 7bfa ldrb r2, [r7, #15]
8001a86: 6879 ldr r1, [r7, #4]
8001a88: 4613 mov r3, r2
8001a8a: 00db lsls r3, r3, #3
8001a8c: 4413 add r3, r2
8001a8e: 009b lsls r3, r3, #2
8001a90: 440b add r3, r1
8001a92: f503 7315 add.w r3, r3, #596 @ 0x254
8001a96: 7bfa ldrb r2, [r7, #15]
8001a98: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8001a9a: 7bfa ldrb r2, [r7, #15]
8001a9c: 6879 ldr r1, [r7, #4]
8001a9e: 4613 mov r3, r2
8001aa0: 00db lsls r3, r3, #3
8001aa2: 4413 add r3, r2
8001aa4: 009b lsls r3, r3, #2
8001aa6: 440b add r3, r1
8001aa8: f503 7316 add.w r3, r3, #600 @ 0x258
8001aac: 2200 movs r2, #0
8001aae: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
8001ab0: 7bfa ldrb r2, [r7, #15]
8001ab2: 6879 ldr r1, [r7, #4]
8001ab4: 4613 mov r3, r2
8001ab6: 00db lsls r3, r3, #3
8001ab8: 4413 add r3, r2
8001aba: 009b lsls r3, r3, #2
8001abc: 440b add r3, r1
8001abe: f503 7317 add.w r3, r3, #604 @ 0x25c
8001ac2: 2200 movs r2, #0
8001ac4: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8001ac6: 7bfa ldrb r2, [r7, #15]
8001ac8: 6879 ldr r1, [r7, #4]
8001aca: 4613 mov r3, r2
8001acc: 00db lsls r3, r3, #3
8001ace: 4413 add r3, r2
8001ad0: 009b lsls r3, r3, #2
8001ad2: 440b add r3, r1
8001ad4: f503 7318 add.w r3, r3, #608 @ 0x260
8001ad8: 2200 movs r2, #0
8001ada: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8001adc: 7bfa ldrb r2, [r7, #15]
8001ade: 6879 ldr r1, [r7, #4]
8001ae0: 4613 mov r3, r2
8001ae2: 00db lsls r3, r3, #3
8001ae4: 4413 add r3, r2
8001ae6: 009b lsls r3, r3, #2
8001ae8: 440b add r3, r1
8001aea: f503 7319 add.w r3, r3, #612 @ 0x264
8001aee: 2200 movs r2, #0
8001af0: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001af2: 7bfb ldrb r3, [r7, #15]
8001af4: 3301 adds r3, #1
8001af6: 73fb strb r3, [r7, #15]
8001af8: 687b ldr r3, [r7, #4]
8001afa: 791b ldrb r3, [r3, #4]
8001afc: 7bfa ldrb r2, [r7, #15]
8001afe: 429a cmp r2, r3
8001b00: d3b5 bcc.n 8001a6e <HAL_PCD_Init+0x134>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8001b02: 687b ldr r3, [r7, #4]
8001b04: 6818 ldr r0, [r3, #0]
8001b06: 687b ldr r3, [r7, #4]
8001b08: 7c1a ldrb r2, [r3, #16]
8001b0a: f88d 2000 strb.w r2, [sp]
8001b0e: 3304 adds r3, #4
8001b10: cb0e ldmia r3, {r1, r2, r3}
8001b12: f002 fccd bl 80044b0 <USB_DevInit>
8001b16: 4603 mov r3, r0
8001b18: 2b00 cmp r3, #0
8001b1a: d005 beq.n 8001b28 <HAL_PCD_Init+0x1ee>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8001b1c: 687b ldr r3, [r7, #4]
8001b1e: 2202 movs r2, #2
8001b20: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
8001b24: 2301 movs r3, #1
8001b26: e013 b.n 8001b50 <HAL_PCD_Init+0x216>
}
hpcd->USB_Address = 0U;
8001b28: 687b ldr r3, [r7, #4]
8001b2a: 2200 movs r2, #0
8001b2c: 745a strb r2, [r3, #17]
hpcd->State = HAL_PCD_STATE_READY;
8001b2e: 687b ldr r3, [r7, #4]
8001b30: 2201 movs r2, #1
8001b32: f883 2495 strb.w r2, [r3, #1173] @ 0x495
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
8001b36: 687b ldr r3, [r7, #4]
8001b38: 7b1b ldrb r3, [r3, #12]
8001b3a: 2b01 cmp r3, #1
8001b3c: d102 bne.n 8001b44 <HAL_PCD_Init+0x20a>
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
8001b3e: 6878 ldr r0, [r7, #4]
8001b40: f001 f856 bl 8002bf0 <HAL_PCDEx_ActivateLPM>
}
(void)USB_DevDisconnect(hpcd->Instance);
8001b44: 687b ldr r3, [r7, #4]
8001b46: 681b ldr r3, [r3, #0]
8001b48: 4618 mov r0, r3
8001b4a: f003 fc84 bl 8005456 <USB_DevDisconnect>
return HAL_OK;
8001b4e: 2300 movs r3, #0
}
8001b50: 4618 mov r0, r3
8001b52: 3710 adds r7, #16
8001b54: 46bd mov sp, r7
8001b56: bd80 pop {r7, pc}
08001b58 <HAL_PCD_Start>:
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
8001b58: b580 push {r7, lr}
8001b5a: b084 sub sp, #16
8001b5c: af00 add r7, sp, #0
8001b5e: 6078 str r0, [r7, #4]
#if defined (USB_OTG_FS)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8001b60: 687b ldr r3, [r7, #4]
8001b62: 681b ldr r3, [r3, #0]
8001b64: 60fb str r3, [r7, #12]
#endif /* defined (USB_OTG_FS) */
__HAL_LOCK(hpcd);
8001b66: 687b ldr r3, [r7, #4]
8001b68: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
8001b6c: 2b01 cmp r3, #1
8001b6e: d101 bne.n 8001b74 <HAL_PCD_Start+0x1c>
8001b70: 2302 movs r3, #2
8001b72: e01c b.n 8001bae <HAL_PCD_Start+0x56>
8001b74: 687b ldr r3, [r7, #4]
8001b76: 2201 movs r2, #1
8001b78: f883 2494 strb.w r2, [r3, #1172] @ 0x494
#if defined (USB_OTG_FS)
if (hpcd->Init.battery_charging_enable == 1U)
8001b7c: 687b ldr r3, [r7, #4]
8001b7e: 7b5b ldrb r3, [r3, #13]
8001b80: 2b01 cmp r3, #1
8001b82: d105 bne.n 8001b90 <HAL_PCD_Start+0x38>
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
8001b84: 68fb ldr r3, [r7, #12]
8001b86: 6b9b ldr r3, [r3, #56] @ 0x38
8001b88: f443 3280 orr.w r2, r3, #65536 @ 0x10000
8001b8c: 68fb ldr r3, [r7, #12]
8001b8e: 639a str r2, [r3, #56] @ 0x38
}
#endif /* defined (USB_OTG_FS) */
__HAL_PCD_ENABLE(hpcd);
8001b90: 687b ldr r3, [r7, #4]
8001b92: 681b ldr r3, [r3, #0]
8001b94: 4618 mov r0, r3
8001b96: f002 fc1d bl 80043d4 <USB_EnableGlobalInt>
(void)USB_DevConnect(hpcd->Instance);
8001b9a: 687b ldr r3, [r7, #4]
8001b9c: 681b ldr r3, [r3, #0]
8001b9e: 4618 mov r0, r3
8001ba0: f003 fc38 bl 8005414 <USB_DevConnect>
__HAL_UNLOCK(hpcd);
8001ba4: 687b ldr r3, [r7, #4]
8001ba6: 2200 movs r2, #0
8001ba8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
8001bac: 2300 movs r3, #0
}
8001bae: 4618 mov r0, r3
8001bb0: 3710 adds r7, #16
8001bb2: 46bd mov sp, r7
8001bb4: bd80 pop {r7, pc}
08001bb6 <HAL_PCD_IRQHandler>:
* @brief Handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
8001bb6: b590 push {r4, r7, lr}
8001bb8: b08d sub sp, #52 @ 0x34
8001bba: af00 add r7, sp, #0
8001bbc: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8001bbe: 687b ldr r3, [r7, #4]
8001bc0: 681b ldr r3, [r3, #0]
8001bc2: 623b str r3, [r7, #32]
uint32_t USBx_BASE = (uint32_t)USBx;
8001bc4: 6a3b ldr r3, [r7, #32]
8001bc6: 61fb str r3, [r7, #28]
uint32_t epnum;
uint32_t fifoemptymsk;
uint32_t RegVal;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
8001bc8: 687b ldr r3, [r7, #4]
8001bca: 681b ldr r3, [r3, #0]
8001bcc: 4618 mov r0, r3
8001bce: f003 fcf6 bl 80055be <USB_GetMode>
8001bd2: 4603 mov r3, r0
8001bd4: 2b00 cmp r3, #0
8001bd6: f040 8481 bne.w 80024dc <HAL_PCD_IRQHandler+0x926>
{
/* avoid spurious interrupt */
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
8001bda: 687b ldr r3, [r7, #4]
8001bdc: 681b ldr r3, [r3, #0]
8001bde: 4618 mov r0, r3
8001be0: f003 fc5a bl 8005498 <USB_ReadInterrupts>
8001be4: 4603 mov r3, r0
8001be6: 2b00 cmp r3, #0
8001be8: f000 8477 beq.w 80024da <HAL_PCD_IRQHandler+0x924>
{
return;
}
/* store current frame number */
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
8001bec: 69fb ldr r3, [r7, #28]
8001bee: f503 6300 add.w r3, r3, #2048 @ 0x800
8001bf2: 689b ldr r3, [r3, #8]
8001bf4: 0a1b lsrs r3, r3, #8
8001bf6: f3c3 020d ubfx r2, r3, #0, #14
8001bfa: 687b ldr r3, [r7, #4]
8001bfc: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
8001c00: 687b ldr r3, [r7, #4]
8001c02: 681b ldr r3, [r3, #0]
8001c04: 4618 mov r0, r3
8001c06: f003 fc47 bl 8005498 <USB_ReadInterrupts>
8001c0a: 4603 mov r3, r0
8001c0c: f003 0302 and.w r3, r3, #2
8001c10: 2b02 cmp r3, #2
8001c12: d107 bne.n 8001c24 <HAL_PCD_IRQHandler+0x6e>
{
/* incorrect mode, acknowledge the interrupt */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
8001c14: 687b ldr r3, [r7, #4]
8001c16: 681b ldr r3, [r3, #0]
8001c18: 695a ldr r2, [r3, #20]
8001c1a: 687b ldr r3, [r7, #4]
8001c1c: 681b ldr r3, [r3, #0]
8001c1e: f002 0202 and.w r2, r2, #2
8001c22: 615a str r2, [r3, #20]
}
/* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
8001c24: 687b ldr r3, [r7, #4]
8001c26: 681b ldr r3, [r3, #0]
8001c28: 4618 mov r0, r3
8001c2a: f003 fc35 bl 8005498 <USB_ReadInterrupts>
8001c2e: 4603 mov r3, r0
8001c30: f003 0310 and.w r3, r3, #16
8001c34: 2b10 cmp r3, #16
8001c36: d161 bne.n 8001cfc <HAL_PCD_IRQHandler+0x146>
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
8001c38: 687b ldr r3, [r7, #4]
8001c3a: 681b ldr r3, [r3, #0]
8001c3c: 699a ldr r2, [r3, #24]
8001c3e: 687b ldr r3, [r7, #4]
8001c40: 681b ldr r3, [r3, #0]
8001c42: f022 0210 bic.w r2, r2, #16
8001c46: 619a str r2, [r3, #24]
RegVal = USBx->GRXSTSP;
8001c48: 6a3b ldr r3, [r7, #32]
8001c4a: 6a1b ldr r3, [r3, #32]
8001c4c: 61bb str r3, [r7, #24]
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
8001c4e: 69bb ldr r3, [r7, #24]
8001c50: f003 020f and.w r2, r3, #15
8001c54: 4613 mov r3, r2
8001c56: 00db lsls r3, r3, #3
8001c58: 4413 add r3, r2
8001c5a: 009b lsls r3, r3, #2
8001c5c: f503 7314 add.w r3, r3, #592 @ 0x250
8001c60: 687a ldr r2, [r7, #4]
8001c62: 4413 add r3, r2
8001c64: 3304 adds r3, #4
8001c66: 617b str r3, [r7, #20]
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
8001c68: 69bb ldr r3, [r7, #24]
8001c6a: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
8001c6e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8001c72: d124 bne.n 8001cbe <HAL_PCD_IRQHandler+0x108>
{
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
8001c74: 69ba ldr r2, [r7, #24]
8001c76: f647 73f0 movw r3, #32752 @ 0x7ff0
8001c7a: 4013 ands r3, r2
8001c7c: 2b00 cmp r3, #0
8001c7e: d035 beq.n 8001cec <HAL_PCD_IRQHandler+0x136>
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
8001c80: 697b ldr r3, [r7, #20]
8001c82: 68d9 ldr r1, [r3, #12]
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
8001c84: 69bb ldr r3, [r7, #24]
8001c86: 091b lsrs r3, r3, #4
8001c88: b29b uxth r3, r3
(void)USB_ReadPacket(USBx, ep->xfer_buff,
8001c8a: f3c3 030a ubfx r3, r3, #0, #11
8001c8e: b29b uxth r3, r3
8001c90: 461a mov r2, r3
8001c92: 6a38 ldr r0, [r7, #32]
8001c94: f003 fa6c bl 8005170 <USB_ReadPacket>
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
8001c98: 697b ldr r3, [r7, #20]
8001c9a: 68da ldr r2, [r3, #12]
8001c9c: 69bb ldr r3, [r7, #24]
8001c9e: 091b lsrs r3, r3, #4
8001ca0: f3c3 030a ubfx r3, r3, #0, #11
8001ca4: 441a add r2, r3
8001ca6: 697b ldr r3, [r7, #20]
8001ca8: 60da str r2, [r3, #12]
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
8001caa: 697b ldr r3, [r7, #20]
8001cac: 695a ldr r2, [r3, #20]
8001cae: 69bb ldr r3, [r7, #24]
8001cb0: 091b lsrs r3, r3, #4
8001cb2: f3c3 030a ubfx r3, r3, #0, #11
8001cb6: 441a add r2, r3
8001cb8: 697b ldr r3, [r7, #20]
8001cba: 615a str r2, [r3, #20]
8001cbc: e016 b.n 8001cec <HAL_PCD_IRQHandler+0x136>
}
}
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
8001cbe: 69bb ldr r3, [r7, #24]
8001cc0: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
8001cc4: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
8001cc8: d110 bne.n 8001cec <HAL_PCD_IRQHandler+0x136>
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
8001cca: 687b ldr r3, [r7, #4]
8001ccc: f203 439c addw r3, r3, #1180 @ 0x49c
8001cd0: 2208 movs r2, #8
8001cd2: 4619 mov r1, r3
8001cd4: 6a38 ldr r0, [r7, #32]
8001cd6: f003 fa4b bl 8005170 <USB_ReadPacket>
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
8001cda: 697b ldr r3, [r7, #20]
8001cdc: 695a ldr r2, [r3, #20]
8001cde: 69bb ldr r3, [r7, #24]
8001ce0: 091b lsrs r3, r3, #4
8001ce2: f3c3 030a ubfx r3, r3, #0, #11
8001ce6: 441a add r2, r3
8001ce8: 697b ldr r3, [r7, #20]
8001cea: 615a str r2, [r3, #20]
else
{
/* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
8001cec: 687b ldr r3, [r7, #4]
8001cee: 681b ldr r3, [r3, #0]
8001cf0: 699a ldr r2, [r3, #24]
8001cf2: 687b ldr r3, [r7, #4]
8001cf4: 681b ldr r3, [r3, #0]
8001cf6: f042 0210 orr.w r2, r2, #16
8001cfa: 619a str r2, [r3, #24]
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
8001cfc: 687b ldr r3, [r7, #4]
8001cfe: 681b ldr r3, [r3, #0]
8001d00: 4618 mov r0, r3
8001d02: f003 fbc9 bl 8005498 <USB_ReadInterrupts>
8001d06: 4603 mov r3, r0
8001d08: f403 2300 and.w r3, r3, #524288 @ 0x80000
8001d0c: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
8001d10: f040 80a7 bne.w 8001e62 <HAL_PCD_IRQHandler+0x2ac>
{
epnum = 0U;
8001d14: 2300 movs r3, #0
8001d16: 627b str r3, [r7, #36] @ 0x24
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
8001d18: 687b ldr r3, [r7, #4]
8001d1a: 681b ldr r3, [r3, #0]
8001d1c: 4618 mov r0, r3
8001d1e: f003 fbce bl 80054be <USB_ReadDevAllOutEpInterrupt>
8001d22: 62b8 str r0, [r7, #40] @ 0x28
while (ep_intr != 0U)
8001d24: e099 b.n 8001e5a <HAL_PCD_IRQHandler+0x2a4>
{
if ((ep_intr & 0x1U) != 0U)
8001d26: 6abb ldr r3, [r7, #40] @ 0x28
8001d28: f003 0301 and.w r3, r3, #1
8001d2c: 2b00 cmp r3, #0
8001d2e: f000 808e beq.w 8001e4e <HAL_PCD_IRQHandler+0x298>
{
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
8001d32: 687b ldr r3, [r7, #4]
8001d34: 681b ldr r3, [r3, #0]
8001d36: 6a7a ldr r2, [r7, #36] @ 0x24
8001d38: b2d2 uxtb r2, r2
8001d3a: 4611 mov r1, r2
8001d3c: 4618 mov r0, r3
8001d3e: f003 fbf2 bl 8005526 <USB_ReadDevOutEPInterrupt>
8001d42: 6138 str r0, [r7, #16]
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
8001d44: 693b ldr r3, [r7, #16]
8001d46: f003 0301 and.w r3, r3, #1
8001d4a: 2b00 cmp r3, #0
8001d4c: d00c beq.n 8001d68 <HAL_PCD_IRQHandler+0x1b2>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
8001d4e: 6a7b ldr r3, [r7, #36] @ 0x24
8001d50: 015a lsls r2, r3, #5
8001d52: 69fb ldr r3, [r7, #28]
8001d54: 4413 add r3, r2
8001d56: f503 6330 add.w r3, r3, #2816 @ 0xb00
8001d5a: 461a mov r2, r3
8001d5c: 2301 movs r3, #1
8001d5e: 6093 str r3, [r2, #8]
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
8001d60: 6a79 ldr r1, [r7, #36] @ 0x24
8001d62: 6878 ldr r0, [r7, #4]
8001d64: f000 fe6a bl 8002a3c <PCD_EP_OutXfrComplete_int>
}
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
8001d68: 693b ldr r3, [r7, #16]
8001d6a: f003 0308 and.w r3, r3, #8
8001d6e: 2b00 cmp r3, #0
8001d70: d00c beq.n 8001d8c <HAL_PCD_IRQHandler+0x1d6>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
8001d72: 6a7b ldr r3, [r7, #36] @ 0x24
8001d74: 015a lsls r2, r3, #5
8001d76: 69fb ldr r3, [r7, #28]
8001d78: 4413 add r3, r2
8001d7a: f503 6330 add.w r3, r3, #2816 @ 0xb00
8001d7e: 461a mov r2, r3
8001d80: 2308 movs r3, #8
8001d82: 6093 str r3, [r2, #8]
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
8001d84: 6a79 ldr r1, [r7, #36] @ 0x24
8001d86: 6878 ldr r0, [r7, #4]
8001d88: f000 fea6 bl 8002ad8 <PCD_EP_OutSetupPacket_int>
}
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
8001d8c: 693b ldr r3, [r7, #16]
8001d8e: f003 0310 and.w r3, r3, #16
8001d92: 2b00 cmp r3, #0
8001d94: d008 beq.n 8001da8 <HAL_PCD_IRQHandler+0x1f2>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
8001d96: 6a7b ldr r3, [r7, #36] @ 0x24
8001d98: 015a lsls r2, r3, #5
8001d9a: 69fb ldr r3, [r7, #28]
8001d9c: 4413 add r3, r2
8001d9e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8001da2: 461a mov r2, r3
8001da4: 2310 movs r3, #16
8001da6: 6093 str r3, [r2, #8]
}
/* Clear OUT Endpoint disable interrupt */
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
8001da8: 693b ldr r3, [r7, #16]
8001daa: f003 0302 and.w r3, r3, #2
8001dae: 2b00 cmp r3, #0
8001db0: d030 beq.n 8001e14 <HAL_PCD_IRQHandler+0x25e>
{
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
8001db2: 6a3b ldr r3, [r7, #32]
8001db4: 695b ldr r3, [r3, #20]
8001db6: f003 0380 and.w r3, r3, #128 @ 0x80
8001dba: 2b80 cmp r3, #128 @ 0x80
8001dbc: d109 bne.n 8001dd2 <HAL_PCD_IRQHandler+0x21c>
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
8001dbe: 69fb ldr r3, [r7, #28]
8001dc0: f503 6300 add.w r3, r3, #2048 @ 0x800
8001dc4: 685b ldr r3, [r3, #4]
8001dc6: 69fa ldr r2, [r7, #28]
8001dc8: f502 6200 add.w r2, r2, #2048 @ 0x800
8001dcc: f443 6380 orr.w r3, r3, #1024 @ 0x400
8001dd0: 6053 str r3, [r2, #4]
}
ep = &hpcd->OUT_ep[epnum];
8001dd2: 6a7a ldr r2, [r7, #36] @ 0x24
8001dd4: 4613 mov r3, r2
8001dd6: 00db lsls r3, r3, #3
8001dd8: 4413 add r3, r2
8001dda: 009b lsls r3, r3, #2
8001ddc: f503 7314 add.w r3, r3, #592 @ 0x250
8001de0: 687a ldr r2, [r7, #4]
8001de2: 4413 add r3, r2
8001de4: 3304 adds r3, #4
8001de6: 617b str r3, [r7, #20]
if (ep->is_iso_incomplete == 1U)
8001de8: 697b ldr r3, [r7, #20]
8001dea: 78db ldrb r3, [r3, #3]
8001dec: 2b01 cmp r3, #1
8001dee: d108 bne.n 8001e02 <HAL_PCD_IRQHandler+0x24c>
{
ep->is_iso_incomplete = 0U;
8001df0: 697b ldr r3, [r7, #20]
8001df2: 2200 movs r2, #0
8001df4: 70da strb r2, [r3, #3]
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
8001df6: 6a7b ldr r3, [r7, #36] @ 0x24
8001df8: b2db uxtb r3, r3
8001dfa: 4619 mov r1, r3
8001dfc: 6878 ldr r0, [r7, #4]
8001dfe: f005 fe61 bl 8007ac4 <HAL_PCD_ISOOUTIncompleteCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
8001e02: 6a7b ldr r3, [r7, #36] @ 0x24
8001e04: 015a lsls r2, r3, #5
8001e06: 69fb ldr r3, [r7, #28]
8001e08: 4413 add r3, r2
8001e0a: f503 6330 add.w r3, r3, #2816 @ 0xb00
8001e0e: 461a mov r2, r3
8001e10: 2302 movs r3, #2
8001e12: 6093 str r3, [r2, #8]
}
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
8001e14: 693b ldr r3, [r7, #16]
8001e16: f003 0320 and.w r3, r3, #32
8001e1a: 2b00 cmp r3, #0
8001e1c: d008 beq.n 8001e30 <HAL_PCD_IRQHandler+0x27a>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
8001e1e: 6a7b ldr r3, [r7, #36] @ 0x24
8001e20: 015a lsls r2, r3, #5
8001e22: 69fb ldr r3, [r7, #28]
8001e24: 4413 add r3, r2
8001e26: f503 6330 add.w r3, r3, #2816 @ 0xb00
8001e2a: 461a mov r2, r3
8001e2c: 2320 movs r3, #32
8001e2e: 6093 str r3, [r2, #8]
}
/* Clear OUT NAK interrupt */
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
8001e30: 693b ldr r3, [r7, #16]
8001e32: f403 5300 and.w r3, r3, #8192 @ 0x2000
8001e36: 2b00 cmp r3, #0
8001e38: d009 beq.n 8001e4e <HAL_PCD_IRQHandler+0x298>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
8001e3a: 6a7b ldr r3, [r7, #36] @ 0x24
8001e3c: 015a lsls r2, r3, #5
8001e3e: 69fb ldr r3, [r7, #28]
8001e40: 4413 add r3, r2
8001e42: f503 6330 add.w r3, r3, #2816 @ 0xb00
8001e46: 461a mov r2, r3
8001e48: f44f 5300 mov.w r3, #8192 @ 0x2000
8001e4c: 6093 str r3, [r2, #8]
}
}
epnum++;
8001e4e: 6a7b ldr r3, [r7, #36] @ 0x24
8001e50: 3301 adds r3, #1
8001e52: 627b str r3, [r7, #36] @ 0x24
ep_intr >>= 1U;
8001e54: 6abb ldr r3, [r7, #40] @ 0x28
8001e56: 085b lsrs r3, r3, #1
8001e58: 62bb str r3, [r7, #40] @ 0x28
while (ep_intr != 0U)
8001e5a: 6abb ldr r3, [r7, #40] @ 0x28
8001e5c: 2b00 cmp r3, #0
8001e5e: f47f af62 bne.w 8001d26 <HAL_PCD_IRQHandler+0x170>
}
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
8001e62: 687b ldr r3, [r7, #4]
8001e64: 681b ldr r3, [r3, #0]
8001e66: 4618 mov r0, r3
8001e68: f003 fb16 bl 8005498 <USB_ReadInterrupts>
8001e6c: 4603 mov r3, r0
8001e6e: f403 2380 and.w r3, r3, #262144 @ 0x40000
8001e72: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8001e76: f040 80a4 bne.w 8001fc2 <HAL_PCD_IRQHandler+0x40c>
{
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
8001e7a: 687b ldr r3, [r7, #4]
8001e7c: 681b ldr r3, [r3, #0]
8001e7e: 4618 mov r0, r3
8001e80: f003 fb37 bl 80054f2 <USB_ReadDevAllInEpInterrupt>
8001e84: 62b8 str r0, [r7, #40] @ 0x28
epnum = 0U;
8001e86: 2300 movs r3, #0
8001e88: 627b str r3, [r7, #36] @ 0x24
while (ep_intr != 0U)
8001e8a: e096 b.n 8001fba <HAL_PCD_IRQHandler+0x404>
{
if ((ep_intr & 0x1U) != 0U) /* In ITR */
8001e8c: 6abb ldr r3, [r7, #40] @ 0x28
8001e8e: f003 0301 and.w r3, r3, #1
8001e92: 2b00 cmp r3, #0
8001e94: f000 808b beq.w 8001fae <HAL_PCD_IRQHandler+0x3f8>
{
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
8001e98: 687b ldr r3, [r7, #4]
8001e9a: 681b ldr r3, [r3, #0]
8001e9c: 6a7a ldr r2, [r7, #36] @ 0x24
8001e9e: b2d2 uxtb r2, r2
8001ea0: 4611 mov r1, r2
8001ea2: 4618 mov r0, r3
8001ea4: f003 fb5d bl 8005562 <USB_ReadDevInEPInterrupt>
8001ea8: 6138 str r0, [r7, #16]
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
8001eaa: 693b ldr r3, [r7, #16]
8001eac: f003 0301 and.w r3, r3, #1
8001eb0: 2b00 cmp r3, #0
8001eb2: d020 beq.n 8001ef6 <HAL_PCD_IRQHandler+0x340>
{
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
8001eb4: 6a7b ldr r3, [r7, #36] @ 0x24
8001eb6: f003 030f and.w r3, r3, #15
8001eba: 2201 movs r2, #1
8001ebc: fa02 f303 lsl.w r3, r2, r3
8001ec0: 60fb str r3, [r7, #12]
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
8001ec2: 69fb ldr r3, [r7, #28]
8001ec4: f503 6300 add.w r3, r3, #2048 @ 0x800
8001ec8: 6b5a ldr r2, [r3, #52] @ 0x34
8001eca: 68fb ldr r3, [r7, #12]
8001ecc: 43db mvns r3, r3
8001ece: 69f9 ldr r1, [r7, #28]
8001ed0: f501 6100 add.w r1, r1, #2048 @ 0x800
8001ed4: 4013 ands r3, r2
8001ed6: 634b str r3, [r1, #52] @ 0x34
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
8001ed8: 6a7b ldr r3, [r7, #36] @ 0x24
8001eda: 015a lsls r2, r3, #5
8001edc: 69fb ldr r3, [r7, #28]
8001ede: 4413 add r3, r2
8001ee0: f503 6310 add.w r3, r3, #2304 @ 0x900
8001ee4: 461a mov r2, r3
8001ee6: 2301 movs r3, #1
8001ee8: 6093 str r3, [r2, #8]
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
8001eea: 6a7b ldr r3, [r7, #36] @ 0x24
8001eec: b2db uxtb r3, r3
8001eee: 4619 mov r1, r3
8001ef0: 6878 ldr r0, [r7, #4]
8001ef2: f005 fd52 bl 800799a <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
8001ef6: 693b ldr r3, [r7, #16]
8001ef8: f003 0308 and.w r3, r3, #8
8001efc: 2b00 cmp r3, #0
8001efe: d008 beq.n 8001f12 <HAL_PCD_IRQHandler+0x35c>
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
8001f00: 6a7b ldr r3, [r7, #36] @ 0x24
8001f02: 015a lsls r2, r3, #5
8001f04: 69fb ldr r3, [r7, #28]
8001f06: 4413 add r3, r2
8001f08: f503 6310 add.w r3, r3, #2304 @ 0x900
8001f0c: 461a mov r2, r3
8001f0e: 2308 movs r3, #8
8001f10: 6093 str r3, [r2, #8]
}
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
8001f12: 693b ldr r3, [r7, #16]
8001f14: f003 0310 and.w r3, r3, #16
8001f18: 2b00 cmp r3, #0
8001f1a: d008 beq.n 8001f2e <HAL_PCD_IRQHandler+0x378>
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
8001f1c: 6a7b ldr r3, [r7, #36] @ 0x24
8001f1e: 015a lsls r2, r3, #5
8001f20: 69fb ldr r3, [r7, #28]
8001f22: 4413 add r3, r2
8001f24: f503 6310 add.w r3, r3, #2304 @ 0x900
8001f28: 461a mov r2, r3
8001f2a: 2310 movs r3, #16
8001f2c: 6093 str r3, [r2, #8]
}
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
8001f2e: 693b ldr r3, [r7, #16]
8001f30: f003 0340 and.w r3, r3, #64 @ 0x40
8001f34: 2b00 cmp r3, #0
8001f36: d008 beq.n 8001f4a <HAL_PCD_IRQHandler+0x394>
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
8001f38: 6a7b ldr r3, [r7, #36] @ 0x24
8001f3a: 015a lsls r2, r3, #5
8001f3c: 69fb ldr r3, [r7, #28]
8001f3e: 4413 add r3, r2
8001f40: f503 6310 add.w r3, r3, #2304 @ 0x900
8001f44: 461a mov r2, r3
8001f46: 2340 movs r3, #64 @ 0x40
8001f48: 6093 str r3, [r2, #8]
}
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
8001f4a: 693b ldr r3, [r7, #16]
8001f4c: f003 0302 and.w r3, r3, #2
8001f50: 2b00 cmp r3, #0
8001f52: d023 beq.n 8001f9c <HAL_PCD_IRQHandler+0x3e6>
{
(void)USB_FlushTxFifo(USBx, epnum);
8001f54: 6a79 ldr r1, [r7, #36] @ 0x24
8001f56: 6a38 ldr r0, [r7, #32]
8001f58: f002 fbf2 bl 8004740 <USB_FlushTxFifo>
ep = &hpcd->IN_ep[epnum];
8001f5c: 6a7a ldr r2, [r7, #36] @ 0x24
8001f5e: 4613 mov r3, r2
8001f60: 00db lsls r3, r3, #3
8001f62: 4413 add r3, r2
8001f64: 009b lsls r3, r3, #2
8001f66: 3310 adds r3, #16
8001f68: 687a ldr r2, [r7, #4]
8001f6a: 4413 add r3, r2
8001f6c: 3304 adds r3, #4
8001f6e: 617b str r3, [r7, #20]
if (ep->is_iso_incomplete == 1U)
8001f70: 697b ldr r3, [r7, #20]
8001f72: 78db ldrb r3, [r3, #3]
8001f74: 2b01 cmp r3, #1
8001f76: d108 bne.n 8001f8a <HAL_PCD_IRQHandler+0x3d4>
{
ep->is_iso_incomplete = 0U;
8001f78: 697b ldr r3, [r7, #20]
8001f7a: 2200 movs r2, #0
8001f7c: 70da strb r2, [r3, #3]
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
8001f7e: 6a7b ldr r3, [r7, #36] @ 0x24
8001f80: b2db uxtb r3, r3
8001f82: 4619 mov r1, r3
8001f84: 6878 ldr r0, [r7, #4]
8001f86: f005 fdaf bl 8007ae8 <HAL_PCD_ISOINIncompleteCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
8001f8a: 6a7b ldr r3, [r7, #36] @ 0x24
8001f8c: 015a lsls r2, r3, #5
8001f8e: 69fb ldr r3, [r7, #28]
8001f90: 4413 add r3, r2
8001f92: f503 6310 add.w r3, r3, #2304 @ 0x900
8001f96: 461a mov r2, r3
8001f98: 2302 movs r3, #2
8001f9a: 6093 str r3, [r2, #8]
}
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
8001f9c: 693b ldr r3, [r7, #16]
8001f9e: f003 0380 and.w r3, r3, #128 @ 0x80
8001fa2: 2b00 cmp r3, #0
8001fa4: d003 beq.n 8001fae <HAL_PCD_IRQHandler+0x3f8>
{
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
8001fa6: 6a79 ldr r1, [r7, #36] @ 0x24
8001fa8: 6878 ldr r0, [r7, #4]
8001faa: f000 fcbe bl 800292a <PCD_WriteEmptyTxFifo>
}
}
epnum++;
8001fae: 6a7b ldr r3, [r7, #36] @ 0x24
8001fb0: 3301 adds r3, #1
8001fb2: 627b str r3, [r7, #36] @ 0x24
ep_intr >>= 1U;
8001fb4: 6abb ldr r3, [r7, #40] @ 0x28
8001fb6: 085b lsrs r3, r3, #1
8001fb8: 62bb str r3, [r7, #40] @ 0x28
while (ep_intr != 0U)
8001fba: 6abb ldr r3, [r7, #40] @ 0x28
8001fbc: 2b00 cmp r3, #0
8001fbe: f47f af65 bne.w 8001e8c <HAL_PCD_IRQHandler+0x2d6>
}
}
/* Handle Resume Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
8001fc2: 687b ldr r3, [r7, #4]
8001fc4: 681b ldr r3, [r3, #0]
8001fc6: 4618 mov r0, r3
8001fc8: f003 fa66 bl 8005498 <USB_ReadInterrupts>
8001fcc: 4603 mov r3, r0
8001fce: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8001fd2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8001fd6: d122 bne.n 800201e <HAL_PCD_IRQHandler+0x468>
{
/* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
8001fd8: 69fb ldr r3, [r7, #28]
8001fda: f503 6300 add.w r3, r3, #2048 @ 0x800
8001fde: 685b ldr r3, [r3, #4]
8001fe0: 69fa ldr r2, [r7, #28]
8001fe2: f502 6200 add.w r2, r2, #2048 @ 0x800
8001fe6: f023 0301 bic.w r3, r3, #1
8001fea: 6053 str r3, [r2, #4]
if (hpcd->LPM_State == LPM_L1)
8001fec: 687b ldr r3, [r7, #4]
8001fee: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
8001ff2: 2b01 cmp r3, #1
8001ff4: d108 bne.n 8002008 <HAL_PCD_IRQHandler+0x452>
{
hpcd->LPM_State = LPM_L0;
8001ff6: 687b ldr r3, [r7, #4]
8001ff8: 2200 movs r2, #0
8001ffa: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
8001ffe: 2100 movs r1, #0
8002000: 6878 ldr r0, [r7, #4]
8002002: f005 ffcf bl 8007fa4 <HAL_PCDEx_LPM_Callback>
8002006: e002 b.n 800200e <HAL_PCD_IRQHandler+0x458>
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
8002008: 6878 ldr r0, [r7, #4]
800200a: f005 fd33 bl 8007a74 <HAL_PCD_ResumeCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
800200e: 687b ldr r3, [r7, #4]
8002010: 681b ldr r3, [r3, #0]
8002012: 695a ldr r2, [r3, #20]
8002014: 687b ldr r3, [r7, #4]
8002016: 681b ldr r3, [r3, #0]
8002018: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000
800201c: 615a str r2, [r3, #20]
}
/* Handle Suspend Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
800201e: 687b ldr r3, [r7, #4]
8002020: 681b ldr r3, [r3, #0]
8002022: 4618 mov r0, r3
8002024: f003 fa38 bl 8005498 <USB_ReadInterrupts>
8002028: 4603 mov r3, r0
800202a: f403 6300 and.w r3, r3, #2048 @ 0x800
800202e: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8002032: d112 bne.n 800205a <HAL_PCD_IRQHandler+0x4a4>
{
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
8002034: 69fb ldr r3, [r7, #28]
8002036: f503 6300 add.w r3, r3, #2048 @ 0x800
800203a: 689b ldr r3, [r3, #8]
800203c: f003 0301 and.w r3, r3, #1
8002040: 2b01 cmp r3, #1
8002042: d102 bne.n 800204a <HAL_PCD_IRQHandler+0x494>
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
8002044: 6878 ldr r0, [r7, #4]
8002046: f005 fcef bl 8007a28 <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
800204a: 687b ldr r3, [r7, #4]
800204c: 681b ldr r3, [r3, #0]
800204e: 695a ldr r2, [r3, #20]
8002050: 687b ldr r3, [r7, #4]
8002052: 681b ldr r3, [r3, #0]
8002054: f402 6200 and.w r2, r2, #2048 @ 0x800
8002058: 615a str r2, [r3, #20]
}
/* Handle LPM Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
800205a: 687b ldr r3, [r7, #4]
800205c: 681b ldr r3, [r3, #0]
800205e: 4618 mov r0, r3
8002060: f003 fa1a bl 8005498 <USB_ReadInterrupts>
8002064: 4603 mov r3, r0
8002066: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
800206a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
800206e: d121 bne.n 80020b4 <HAL_PCD_IRQHandler+0x4fe>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
8002070: 687b ldr r3, [r7, #4]
8002072: 681b ldr r3, [r3, #0]
8002074: 695a ldr r2, [r3, #20]
8002076: 687b ldr r3, [r7, #4]
8002078: 681b ldr r3, [r3, #0]
800207a: f002 6200 and.w r2, r2, #134217728 @ 0x8000000
800207e: 615a str r2, [r3, #20]
if (hpcd->LPM_State == LPM_L0)
8002080: 687b ldr r3, [r7, #4]
8002082: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
8002086: 2b00 cmp r3, #0
8002088: d111 bne.n 80020ae <HAL_PCD_IRQHandler+0x4f8>
{
hpcd->LPM_State = LPM_L1;
800208a: 687b ldr r3, [r7, #4]
800208c: 2201 movs r2, #1
800208e: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
8002092: 687b ldr r3, [r7, #4]
8002094: 681b ldr r3, [r3, #0]
8002096: 6d5b ldr r3, [r3, #84] @ 0x54
8002098: 089b lsrs r3, r3, #2
800209a: f003 020f and.w r2, r3, #15
800209e: 687b ldr r3, [r7, #4]
80020a0: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
80020a4: 2101 movs r1, #1
80020a6: 6878 ldr r0, [r7, #4]
80020a8: f005 ff7c bl 8007fa4 <HAL_PCDEx_LPM_Callback>
80020ac: e002 b.n 80020b4 <HAL_PCD_IRQHandler+0x4fe>
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
80020ae: 6878 ldr r0, [r7, #4]
80020b0: f005 fcba bl 8007a28 <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Handle Reset Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
80020b4: 687b ldr r3, [r7, #4]
80020b6: 681b ldr r3, [r3, #0]
80020b8: 4618 mov r0, r3
80020ba: f003 f9ed bl 8005498 <USB_ReadInterrupts>
80020be: 4603 mov r3, r0
80020c0: f403 5380 and.w r3, r3, #4096 @ 0x1000
80020c4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80020c8: f040 80b6 bne.w 8002238 <HAL_PCD_IRQHandler+0x682>
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
80020cc: 69fb ldr r3, [r7, #28]
80020ce: f503 6300 add.w r3, r3, #2048 @ 0x800
80020d2: 685b ldr r3, [r3, #4]
80020d4: 69fa ldr r2, [r7, #28]
80020d6: f502 6200 add.w r2, r2, #2048 @ 0x800
80020da: f023 0301 bic.w r3, r3, #1
80020de: 6053 str r3, [r2, #4]
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
80020e0: 687b ldr r3, [r7, #4]
80020e2: 681b ldr r3, [r3, #0]
80020e4: 2110 movs r1, #16
80020e6: 4618 mov r0, r3
80020e8: f002 fb2a bl 8004740 <USB_FlushTxFifo>
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80020ec: 2300 movs r3, #0
80020ee: 62fb str r3, [r7, #44] @ 0x2c
80020f0: e046 b.n 8002180 <HAL_PCD_IRQHandler+0x5ca>
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
80020f2: 6afb ldr r3, [r7, #44] @ 0x2c
80020f4: 015a lsls r2, r3, #5
80020f6: 69fb ldr r3, [r7, #28]
80020f8: 4413 add r3, r2
80020fa: f503 6310 add.w r3, r3, #2304 @ 0x900
80020fe: 461a mov r2, r3
8002100: f64f 337f movw r3, #64383 @ 0xfb7f
8002104: 6093 str r3, [r2, #8]
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
8002106: 6afb ldr r3, [r7, #44] @ 0x2c
8002108: 015a lsls r2, r3, #5
800210a: 69fb ldr r3, [r7, #28]
800210c: 4413 add r3, r2
800210e: f503 6310 add.w r3, r3, #2304 @ 0x900
8002112: 681b ldr r3, [r3, #0]
8002114: 6afa ldr r2, [r7, #44] @ 0x2c
8002116: 0151 lsls r1, r2, #5
8002118: 69fa ldr r2, [r7, #28]
800211a: 440a add r2, r1
800211c: f502 6210 add.w r2, r2, #2304 @ 0x900
8002120: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8002124: 6013 str r3, [r2, #0]
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
8002126: 6afb ldr r3, [r7, #44] @ 0x2c
8002128: 015a lsls r2, r3, #5
800212a: 69fb ldr r3, [r7, #28]
800212c: 4413 add r3, r2
800212e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8002132: 461a mov r2, r3
8002134: f64f 337f movw r3, #64383 @ 0xfb7f
8002138: 6093 str r3, [r2, #8]
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
800213a: 6afb ldr r3, [r7, #44] @ 0x2c
800213c: 015a lsls r2, r3, #5
800213e: 69fb ldr r3, [r7, #28]
8002140: 4413 add r3, r2
8002142: f503 6330 add.w r3, r3, #2816 @ 0xb00
8002146: 681b ldr r3, [r3, #0]
8002148: 6afa ldr r2, [r7, #44] @ 0x2c
800214a: 0151 lsls r1, r2, #5
800214c: 69fa ldr r2, [r7, #28]
800214e: 440a add r2, r1
8002150: f502 6230 add.w r2, r2, #2816 @ 0xb00
8002154: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8002158: 6013 str r3, [r2, #0]
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
800215a: 6afb ldr r3, [r7, #44] @ 0x2c
800215c: 015a lsls r2, r3, #5
800215e: 69fb ldr r3, [r7, #28]
8002160: 4413 add r3, r2
8002162: f503 6330 add.w r3, r3, #2816 @ 0xb00
8002166: 681b ldr r3, [r3, #0]
8002168: 6afa ldr r2, [r7, #44] @ 0x2c
800216a: 0151 lsls r1, r2, #5
800216c: 69fa ldr r2, [r7, #28]
800216e: 440a add r2, r1
8002170: f502 6230 add.w r2, r2, #2816 @ 0xb00
8002174: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
8002178: 6013 str r3, [r2, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
800217a: 6afb ldr r3, [r7, #44] @ 0x2c
800217c: 3301 adds r3, #1
800217e: 62fb str r3, [r7, #44] @ 0x2c
8002180: 687b ldr r3, [r7, #4]
8002182: 791b ldrb r3, [r3, #4]
8002184: 461a mov r2, r3
8002186: 6afb ldr r3, [r7, #44] @ 0x2c
8002188: 4293 cmp r3, r2
800218a: d3b2 bcc.n 80020f2 <HAL_PCD_IRQHandler+0x53c>
}
USBx_DEVICE->DAINTMSK |= 0x10001U;
800218c: 69fb ldr r3, [r7, #28]
800218e: f503 6300 add.w r3, r3, #2048 @ 0x800
8002192: 69db ldr r3, [r3, #28]
8002194: 69fa ldr r2, [r7, #28]
8002196: f502 6200 add.w r2, r2, #2048 @ 0x800
800219a: f043 1301 orr.w r3, r3, #65537 @ 0x10001
800219e: 61d3 str r3, [r2, #28]
if (hpcd->Init.use_dedicated_ep1 != 0U)
80021a0: 687b ldr r3, [r7, #4]
80021a2: 7bdb ldrb r3, [r3, #15]
80021a4: 2b00 cmp r3, #0
80021a6: d016 beq.n 80021d6 <HAL_PCD_IRQHandler+0x620>
{
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
80021a8: 69fb ldr r3, [r7, #28]
80021aa: f503 6300 add.w r3, r3, #2048 @ 0x800
80021ae: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
80021b2: 69fa ldr r2, [r7, #28]
80021b4: f502 6200 add.w r2, r2, #2048 @ 0x800
80021b8: f043 030b orr.w r3, r3, #11
80021bc: f8c2 3084 str.w r3, [r2, #132] @ 0x84
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM;
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
80021c0: 69fb ldr r3, [r7, #28]
80021c2: f503 6300 add.w r3, r3, #2048 @ 0x800
80021c6: 6c5b ldr r3, [r3, #68] @ 0x44
80021c8: 69fa ldr r2, [r7, #28]
80021ca: f502 6200 add.w r2, r2, #2048 @ 0x800
80021ce: f043 030b orr.w r3, r3, #11
80021d2: 6453 str r3, [r2, #68] @ 0x44
80021d4: e015 b.n 8002202 <HAL_PCD_IRQHandler+0x64c>
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
else
{
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
80021d6: 69fb ldr r3, [r7, #28]
80021d8: f503 6300 add.w r3, r3, #2048 @ 0x800
80021dc: 695b ldr r3, [r3, #20]
80021de: 69fa ldr r2, [r7, #28]
80021e0: f502 6200 add.w r2, r2, #2048 @ 0x800
80021e4: f443 5300 orr.w r3, r3, #8192 @ 0x2000
80021e8: f043 032b orr.w r3, r3, #43 @ 0x2b
80021ec: 6153 str r3, [r2, #20]
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM |
USB_OTG_DOEPMSK_OTEPSPRM |
USB_OTG_DOEPMSK_NAKM;
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
80021ee: 69fb ldr r3, [r7, #28]
80021f0: f503 6300 add.w r3, r3, #2048 @ 0x800
80021f4: 691b ldr r3, [r3, #16]
80021f6: 69fa ldr r2, [r7, #28]
80021f8: f502 6200 add.w r2, r2, #2048 @ 0x800
80021fc: f043 030b orr.w r3, r3, #11
8002200: 6113 str r3, [r2, #16]
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
/* Set Default Address to 0 */
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
8002202: 69fb ldr r3, [r7, #28]
8002204: f503 6300 add.w r3, r3, #2048 @ 0x800
8002208: 681b ldr r3, [r3, #0]
800220a: 69fa ldr r2, [r7, #28]
800220c: f502 6200 add.w r2, r2, #2048 @ 0x800
8002210: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
8002214: 6013 str r3, [r2, #0]
/* setup EP0 to receive SETUP packets */
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
8002216: 687b ldr r3, [r7, #4]
8002218: 681a ldr r2, [r3, #0]
800221a: 687b ldr r3, [r7, #4]
800221c: f203 439c addw r3, r3, #1180 @ 0x49c
8002220: 4619 mov r1, r3
8002222: 4610 mov r0, r2
8002224: f003 f9fc bl 8005620 <USB_EP0_OutStart>
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
8002228: 687b ldr r3, [r7, #4]
800222a: 681b ldr r3, [r3, #0]
800222c: 695a ldr r2, [r3, #20]
800222e: 687b ldr r3, [r7, #4]
8002230: 681b ldr r3, [r3, #0]
8002232: f402 5280 and.w r2, r2, #4096 @ 0x1000
8002236: 615a str r2, [r3, #20]
}
/* Handle Enumeration done Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
8002238: 687b ldr r3, [r7, #4]
800223a: 681b ldr r3, [r3, #0]
800223c: 4618 mov r0, r3
800223e: f003 f92b bl 8005498 <USB_ReadInterrupts>
8002242: 4603 mov r3, r0
8002244: f403 5300 and.w r3, r3, #8192 @ 0x2000
8002248: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800224c: d123 bne.n 8002296 <HAL_PCD_IRQHandler+0x6e0>
{
(void)USB_ActivateSetup(hpcd->Instance);
800224e: 687b ldr r3, [r7, #4]
8002250: 681b ldr r3, [r3, #0]
8002252: 4618 mov r0, r3
8002254: f003 f9c1 bl 80055da <USB_ActivateSetup>
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
8002258: 687b ldr r3, [r7, #4]
800225a: 681b ldr r3, [r3, #0]
800225c: 4618 mov r0, r3
800225e: f002 fae8 bl 8004832 <USB_GetDevSpeed>
8002262: 4603 mov r3, r0
8002264: 461a mov r2, r3
8002266: 687b ldr r3, [r7, #4]
8002268: 71da strb r2, [r3, #7]
/* Set USB Turnaround time */
(void)USB_SetTurnaroundTime(hpcd->Instance,
800226a: 687b ldr r3, [r7, #4]
800226c: 681c ldr r4, [r3, #0]
800226e: f001 fabf bl 80037f0 <HAL_RCC_GetHCLKFreq>
8002272: 4601 mov r1, r0
HAL_RCC_GetHCLKFreq(),
(uint8_t)hpcd->Init.speed);
8002274: 687b ldr r3, [r7, #4]
8002276: 79db ldrb r3, [r3, #7]
(void)USB_SetTurnaroundTime(hpcd->Instance,
8002278: 461a mov r2, r3
800227a: 4620 mov r0, r4
800227c: f002 f80e bl 800429c <USB_SetTurnaroundTime>
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
8002280: 6878 ldr r0, [r7, #4]
8002282: f005 fbb2 bl 80079ea <HAL_PCD_ResetCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
8002286: 687b ldr r3, [r7, #4]
8002288: 681b ldr r3, [r3, #0]
800228a: 695a ldr r2, [r3, #20]
800228c: 687b ldr r3, [r7, #4]
800228e: 681b ldr r3, [r3, #0]
8002290: f402 5200 and.w r2, r2, #8192 @ 0x2000
8002294: 615a str r2, [r3, #20]
}
/* Handle SOF Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
8002296: 687b ldr r3, [r7, #4]
8002298: 681b ldr r3, [r3, #0]
800229a: 4618 mov r0, r3
800229c: f003 f8fc bl 8005498 <USB_ReadInterrupts>
80022a0: 4603 mov r3, r0
80022a2: f003 0308 and.w r3, r3, #8
80022a6: 2b08 cmp r3, #8
80022a8: d10a bne.n 80022c0 <HAL_PCD_IRQHandler+0x70a>
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
80022aa: 6878 ldr r0, [r7, #4]
80022ac: f005 fb8f bl 80079ce <HAL_PCD_SOFCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
80022b0: 687b ldr r3, [r7, #4]
80022b2: 681b ldr r3, [r3, #0]
80022b4: 695a ldr r2, [r3, #20]
80022b6: 687b ldr r3, [r7, #4]
80022b8: 681b ldr r3, [r3, #0]
80022ba: f002 0208 and.w r2, r2, #8
80022be: 615a str r2, [r3, #20]
}
/* Handle Global OUT NAK effective Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
80022c0: 687b ldr r3, [r7, #4]
80022c2: 681b ldr r3, [r3, #0]
80022c4: 4618 mov r0, r3
80022c6: f003 f8e7 bl 8005498 <USB_ReadInterrupts>
80022ca: 4603 mov r3, r0
80022cc: f003 0380 and.w r3, r3, #128 @ 0x80
80022d0: 2b80 cmp r3, #128 @ 0x80
80022d2: d123 bne.n 800231c <HAL_PCD_IRQHandler+0x766>
{
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
80022d4: 6a3b ldr r3, [r7, #32]
80022d6: 699b ldr r3, [r3, #24]
80022d8: f023 0280 bic.w r2, r3, #128 @ 0x80
80022dc: 6a3b ldr r3, [r7, #32]
80022de: 619a str r2, [r3, #24]
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
80022e0: 2301 movs r3, #1
80022e2: 627b str r3, [r7, #36] @ 0x24
80022e4: e014 b.n 8002310 <HAL_PCD_IRQHandler+0x75a>
{
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
80022e6: 6879 ldr r1, [r7, #4]
80022e8: 6a7a ldr r2, [r7, #36] @ 0x24
80022ea: 4613 mov r3, r2
80022ec: 00db lsls r3, r3, #3
80022ee: 4413 add r3, r2
80022f0: 009b lsls r3, r3, #2
80022f2: 440b add r3, r1
80022f4: f203 2357 addw r3, r3, #599 @ 0x257
80022f8: 781b ldrb r3, [r3, #0]
80022fa: 2b01 cmp r3, #1
80022fc: d105 bne.n 800230a <HAL_PCD_IRQHandler+0x754>
{
/* Abort current transaction and disable the EP */
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
80022fe: 6a7b ldr r3, [r7, #36] @ 0x24
8002300: b2db uxtb r3, r3
8002302: 4619 mov r1, r3
8002304: 6878 ldr r0, [r7, #4]
8002306: f000 fadf bl 80028c8 <HAL_PCD_EP_Abort>
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
800230a: 6a7b ldr r3, [r7, #36] @ 0x24
800230c: 3301 adds r3, #1
800230e: 627b str r3, [r7, #36] @ 0x24
8002310: 687b ldr r3, [r7, #4]
8002312: 791b ldrb r3, [r3, #4]
8002314: 461a mov r2, r3
8002316: 6a7b ldr r3, [r7, #36] @ 0x24
8002318: 4293 cmp r3, r2
800231a: d3e4 bcc.n 80022e6 <HAL_PCD_IRQHandler+0x730>
}
}
}
/* Handle Incomplete ISO IN Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
800231c: 687b ldr r3, [r7, #4]
800231e: 681b ldr r3, [r3, #0]
8002320: 4618 mov r0, r3
8002322: f003 f8b9 bl 8005498 <USB_ReadInterrupts>
8002326: 4603 mov r3, r0
8002328: f403 1380 and.w r3, r3, #1048576 @ 0x100000
800232c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8002330: d13c bne.n 80023ac <HAL_PCD_IRQHandler+0x7f6>
{
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
8002332: 2301 movs r3, #1
8002334: 627b str r3, [r7, #36] @ 0x24
8002336: e02b b.n 8002390 <HAL_PCD_IRQHandler+0x7da>
{
RegVal = USBx_INEP(epnum)->DIEPCTL;
8002338: 6a7b ldr r3, [r7, #36] @ 0x24
800233a: 015a lsls r2, r3, #5
800233c: 69fb ldr r3, [r7, #28]
800233e: 4413 add r3, r2
8002340: f503 6310 add.w r3, r3, #2304 @ 0x900
8002344: 681b ldr r3, [r3, #0]
8002346: 61bb str r3, [r7, #24]
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
8002348: 6879 ldr r1, [r7, #4]
800234a: 6a7a ldr r2, [r7, #36] @ 0x24
800234c: 4613 mov r3, r2
800234e: 00db lsls r3, r3, #3
8002350: 4413 add r3, r2
8002352: 009b lsls r3, r3, #2
8002354: 440b add r3, r1
8002356: 3318 adds r3, #24
8002358: 781b ldrb r3, [r3, #0]
800235a: 2b01 cmp r3, #1
800235c: d115 bne.n 800238a <HAL_PCD_IRQHandler+0x7d4>
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
800235e: 69bb ldr r3, [r7, #24]
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
8002360: 2b00 cmp r3, #0
8002362: da12 bge.n 800238a <HAL_PCD_IRQHandler+0x7d4>
{
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
8002364: 6879 ldr r1, [r7, #4]
8002366: 6a7a ldr r2, [r7, #36] @ 0x24
8002368: 4613 mov r3, r2
800236a: 00db lsls r3, r3, #3
800236c: 4413 add r3, r2
800236e: 009b lsls r3, r3, #2
8002370: 440b add r3, r1
8002372: 3317 adds r3, #23
8002374: 2201 movs r2, #1
8002376: 701a strb r2, [r3, #0]
/* Abort current transaction and disable the EP */
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
8002378: 6a7b ldr r3, [r7, #36] @ 0x24
800237a: b2db uxtb r3, r3
800237c: f063 037f orn r3, r3, #127 @ 0x7f
8002380: b2db uxtb r3, r3
8002382: 4619 mov r1, r3
8002384: 6878 ldr r0, [r7, #4]
8002386: f000 fa9f bl 80028c8 <HAL_PCD_EP_Abort>
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
800238a: 6a7b ldr r3, [r7, #36] @ 0x24
800238c: 3301 adds r3, #1
800238e: 627b str r3, [r7, #36] @ 0x24
8002390: 687b ldr r3, [r7, #4]
8002392: 791b ldrb r3, [r3, #4]
8002394: 461a mov r2, r3
8002396: 6a7b ldr r3, [r7, #36] @ 0x24
8002398: 4293 cmp r3, r2
800239a: d3cd bcc.n 8002338 <HAL_PCD_IRQHandler+0x782>
}
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
800239c: 687b ldr r3, [r7, #4]
800239e: 681b ldr r3, [r3, #0]
80023a0: 695a ldr r2, [r3, #20]
80023a2: 687b ldr r3, [r7, #4]
80023a4: 681b ldr r3, [r3, #0]
80023a6: f402 1280 and.w r2, r2, #1048576 @ 0x100000
80023aa: 615a str r2, [r3, #20]
}
/* Handle Incomplete ISO OUT Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
80023ac: 687b ldr r3, [r7, #4]
80023ae: 681b ldr r3, [r3, #0]
80023b0: 4618 mov r0, r3
80023b2: f003 f871 bl 8005498 <USB_ReadInterrupts>
80023b6: 4603 mov r3, r0
80023b8: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80023bc: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
80023c0: d156 bne.n 8002470 <HAL_PCD_IRQHandler+0x8ba>
{
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
80023c2: 2301 movs r3, #1
80023c4: 627b str r3, [r7, #36] @ 0x24
80023c6: e045 b.n 8002454 <HAL_PCD_IRQHandler+0x89e>
{
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
80023c8: 6a7b ldr r3, [r7, #36] @ 0x24
80023ca: 015a lsls r2, r3, #5
80023cc: 69fb ldr r3, [r7, #28]
80023ce: 4413 add r3, r2
80023d0: f503 6330 add.w r3, r3, #2816 @ 0xb00
80023d4: 681b ldr r3, [r3, #0]
80023d6: 61bb str r3, [r7, #24]
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
80023d8: 6879 ldr r1, [r7, #4]
80023da: 6a7a ldr r2, [r7, #36] @ 0x24
80023dc: 4613 mov r3, r2
80023de: 00db lsls r3, r3, #3
80023e0: 4413 add r3, r2
80023e2: 009b lsls r3, r3, #2
80023e4: 440b add r3, r1
80023e6: f503 7316 add.w r3, r3, #600 @ 0x258
80023ea: 781b ldrb r3, [r3, #0]
80023ec: 2b01 cmp r3, #1
80023ee: d12e bne.n 800244e <HAL_PCD_IRQHandler+0x898>
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
80023f0: 69bb ldr r3, [r7, #24]
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
80023f2: 2b00 cmp r3, #0
80023f4: da2b bge.n 800244e <HAL_PCD_IRQHandler+0x898>
((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U)))
80023f6: 69bb ldr r3, [r7, #24]
80023f8: f403 3280 and.w r2, r3, #65536 @ 0x10000
80023fc: 687b ldr r3, [r7, #4]
80023fe: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4
8002402: f003 0301 and.w r3, r3, #1
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
8002406: 429a cmp r2, r3
8002408: d121 bne.n 800244e <HAL_PCD_IRQHandler+0x898>
{
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
800240a: 6879 ldr r1, [r7, #4]
800240c: 6a7a ldr r2, [r7, #36] @ 0x24
800240e: 4613 mov r3, r2
8002410: 00db lsls r3, r3, #3
8002412: 4413 add r3, r2
8002414: 009b lsls r3, r3, #2
8002416: 440b add r3, r1
8002418: f203 2357 addw r3, r3, #599 @ 0x257
800241c: 2201 movs r2, #1
800241e: 701a strb r2, [r3, #0]
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
8002420: 6a3b ldr r3, [r7, #32]
8002422: 699b ldr r3, [r3, #24]
8002424: f043 0280 orr.w r2, r3, #128 @ 0x80
8002428: 6a3b ldr r3, [r7, #32]
800242a: 619a str r2, [r3, #24]
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
800242c: 6a3b ldr r3, [r7, #32]
800242e: 695b ldr r3, [r3, #20]
8002430: f003 0380 and.w r3, r3, #128 @ 0x80
8002434: 2b00 cmp r3, #0
8002436: d10a bne.n 800244e <HAL_PCD_IRQHandler+0x898>
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
8002438: 69fb ldr r3, [r7, #28]
800243a: f503 6300 add.w r3, r3, #2048 @ 0x800
800243e: 685b ldr r3, [r3, #4]
8002440: 69fa ldr r2, [r7, #28]
8002442: f502 6200 add.w r2, r2, #2048 @ 0x800
8002446: f443 7300 orr.w r3, r3, #512 @ 0x200
800244a: 6053 str r3, [r2, #4]
break;
800244c: e008 b.n 8002460 <HAL_PCD_IRQHandler+0x8aa>
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
800244e: 6a7b ldr r3, [r7, #36] @ 0x24
8002450: 3301 adds r3, #1
8002452: 627b str r3, [r7, #36] @ 0x24
8002454: 687b ldr r3, [r7, #4]
8002456: 791b ldrb r3, [r3, #4]
8002458: 461a mov r2, r3
800245a: 6a7b ldr r3, [r7, #36] @ 0x24
800245c: 4293 cmp r3, r2
800245e: d3b3 bcc.n 80023c8 <HAL_PCD_IRQHandler+0x812>
}
}
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
8002460: 687b ldr r3, [r7, #4]
8002462: 681b ldr r3, [r3, #0]
8002464: 695a ldr r2, [r3, #20]
8002466: 687b ldr r3, [r7, #4]
8002468: 681b ldr r3, [r3, #0]
800246a: f402 1200 and.w r2, r2, #2097152 @ 0x200000
800246e: 615a str r2, [r3, #20]
}
/* Handle Connection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
8002470: 687b ldr r3, [r7, #4]
8002472: 681b ldr r3, [r3, #0]
8002474: 4618 mov r0, r3
8002476: f003 f80f bl 8005498 <USB_ReadInterrupts>
800247a: 4603 mov r3, r0
800247c: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
8002480: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002484: d10a bne.n 800249c <HAL_PCD_IRQHandler+0x8e6>
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ConnectCallback(hpcd);
#else
HAL_PCD_ConnectCallback(hpcd);
8002486: 6878 ldr r0, [r7, #4]
8002488: f005 fb40 bl 8007b0c <HAL_PCD_ConnectCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
800248c: 687b ldr r3, [r7, #4]
800248e: 681b ldr r3, [r3, #0]
8002490: 695a ldr r2, [r3, #20]
8002492: 687b ldr r3, [r7, #4]
8002494: 681b ldr r3, [r3, #0]
8002496: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
800249a: 615a str r2, [r3, #20]
}
/* Handle Disconnection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
800249c: 687b ldr r3, [r7, #4]
800249e: 681b ldr r3, [r3, #0]
80024a0: 4618 mov r0, r3
80024a2: f002 fff9 bl 8005498 <USB_ReadInterrupts>
80024a6: 4603 mov r3, r0
80024a8: f003 0304 and.w r3, r3, #4
80024ac: 2b04 cmp r3, #4
80024ae: d115 bne.n 80024dc <HAL_PCD_IRQHandler+0x926>
{
RegVal = hpcd->Instance->GOTGINT;
80024b0: 687b ldr r3, [r7, #4]
80024b2: 681b ldr r3, [r3, #0]
80024b4: 685b ldr r3, [r3, #4]
80024b6: 61bb str r3, [r7, #24]
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
80024b8: 69bb ldr r3, [r7, #24]
80024ba: f003 0304 and.w r3, r3, #4
80024be: 2b00 cmp r3, #0
80024c0: d002 beq.n 80024c8 <HAL_PCD_IRQHandler+0x912>
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DisconnectCallback(hpcd);
#else
HAL_PCD_DisconnectCallback(hpcd);
80024c2: 6878 ldr r0, [r7, #4]
80024c4: f005 fb30 bl 8007b28 <HAL_PCD_DisconnectCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
hpcd->Instance->GOTGINT |= RegVal;
80024c8: 687b ldr r3, [r7, #4]
80024ca: 681b ldr r3, [r3, #0]
80024cc: 6859 ldr r1, [r3, #4]
80024ce: 687b ldr r3, [r7, #4]
80024d0: 681b ldr r3, [r3, #0]
80024d2: 69ba ldr r2, [r7, #24]
80024d4: 430a orrs r2, r1
80024d6: 605a str r2, [r3, #4]
80024d8: e000 b.n 80024dc <HAL_PCD_IRQHandler+0x926>
return;
80024da: bf00 nop
}
}
}
80024dc: 3734 adds r7, #52 @ 0x34
80024de: 46bd mov sp, r7
80024e0: bd90 pop {r4, r7, pc}
080024e2 <HAL_PCD_SetAddress>:
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
80024e2: b580 push {r7, lr}
80024e4: b082 sub sp, #8
80024e6: af00 add r7, sp, #0
80024e8: 6078 str r0, [r7, #4]
80024ea: 460b mov r3, r1
80024ec: 70fb strb r3, [r7, #3]
__HAL_LOCK(hpcd);
80024ee: 687b ldr r3, [r7, #4]
80024f0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
80024f4: 2b01 cmp r3, #1
80024f6: d101 bne.n 80024fc <HAL_PCD_SetAddress+0x1a>
80024f8: 2302 movs r3, #2
80024fa: e012 b.n 8002522 <HAL_PCD_SetAddress+0x40>
80024fc: 687b ldr r3, [r7, #4]
80024fe: 2201 movs r2, #1
8002500: f883 2494 strb.w r2, [r3, #1172] @ 0x494
hpcd->USB_Address = address;
8002504: 687b ldr r3, [r7, #4]
8002506: 78fa ldrb r2, [r7, #3]
8002508: 745a strb r2, [r3, #17]
(void)USB_SetDevAddress(hpcd->Instance, address);
800250a: 687b ldr r3, [r7, #4]
800250c: 681b ldr r3, [r3, #0]
800250e: 78fa ldrb r2, [r7, #3]
8002510: 4611 mov r1, r2
8002512: 4618 mov r0, r3
8002514: f002 ff58 bl 80053c8 <USB_SetDevAddress>
__HAL_UNLOCK(hpcd);
8002518: 687b ldr r3, [r7, #4]
800251a: 2200 movs r2, #0
800251c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
8002520: 2300 movs r3, #0
}
8002522: 4618 mov r0, r3
8002524: 3708 adds r7, #8
8002526: 46bd mov sp, r7
8002528: bd80 pop {r7, pc}
0800252a <HAL_PCD_EP_Open>:
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
800252a: b580 push {r7, lr}
800252c: b084 sub sp, #16
800252e: af00 add r7, sp, #0
8002530: 6078 str r0, [r7, #4]
8002532: 4608 mov r0, r1
8002534: 4611 mov r1, r2
8002536: 461a mov r2, r3
8002538: 4603 mov r3, r0
800253a: 70fb strb r3, [r7, #3]
800253c: 460b mov r3, r1
800253e: 803b strh r3, [r7, #0]
8002540: 4613 mov r3, r2
8002542: 70bb strb r3, [r7, #2]
HAL_StatusTypeDef ret = HAL_OK;
8002544: 2300 movs r3, #0
8002546: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8002548: f997 3003 ldrsb.w r3, [r7, #3]
800254c: 2b00 cmp r3, #0
800254e: da0f bge.n 8002570 <HAL_PCD_EP_Open+0x46>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8002550: 78fb ldrb r3, [r7, #3]
8002552: f003 020f and.w r2, r3, #15
8002556: 4613 mov r3, r2
8002558: 00db lsls r3, r3, #3
800255a: 4413 add r3, r2
800255c: 009b lsls r3, r3, #2
800255e: 3310 adds r3, #16
8002560: 687a ldr r2, [r7, #4]
8002562: 4413 add r3, r2
8002564: 3304 adds r3, #4
8002566: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8002568: 68fb ldr r3, [r7, #12]
800256a: 2201 movs r2, #1
800256c: 705a strb r2, [r3, #1]
800256e: e00f b.n 8002590 <HAL_PCD_EP_Open+0x66>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8002570: 78fb ldrb r3, [r7, #3]
8002572: f003 020f and.w r2, r3, #15
8002576: 4613 mov r3, r2
8002578: 00db lsls r3, r3, #3
800257a: 4413 add r3, r2
800257c: 009b lsls r3, r3, #2
800257e: f503 7314 add.w r3, r3, #592 @ 0x250
8002582: 687a ldr r2, [r7, #4]
8002584: 4413 add r3, r2
8002586: 3304 adds r3, #4
8002588: 60fb str r3, [r7, #12]
ep->is_in = 0U;
800258a: 68fb ldr r3, [r7, #12]
800258c: 2200 movs r2, #0
800258e: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8002590: 78fb ldrb r3, [r7, #3]
8002592: f003 030f and.w r3, r3, #15
8002596: b2da uxtb r2, r3
8002598: 68fb ldr r3, [r7, #12]
800259a: 701a strb r2, [r3, #0]
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
800259c: 883b ldrh r3, [r7, #0]
800259e: f3c3 020a ubfx r2, r3, #0, #11
80025a2: 68fb ldr r3, [r7, #12]
80025a4: 609a str r2, [r3, #8]
ep->type = ep_type;
80025a6: 68fb ldr r3, [r7, #12]
80025a8: 78ba ldrb r2, [r7, #2]
80025aa: 711a strb r2, [r3, #4]
#if defined (USB_OTG_FS)
if (ep->is_in != 0U)
80025ac: 68fb ldr r3, [r7, #12]
80025ae: 785b ldrb r3, [r3, #1]
80025b0: 2b00 cmp r3, #0
80025b2: d004 beq.n 80025be <HAL_PCD_EP_Open+0x94>
{
/* Assign a Tx FIFO */
ep->tx_fifo_num = ep->num;
80025b4: 68fb ldr r3, [r7, #12]
80025b6: 781b ldrb r3, [r3, #0]
80025b8: 461a mov r2, r3
80025ba: 68fb ldr r3, [r7, #12]
80025bc: 835a strh r2, [r3, #26]
}
#endif /* defined (USB_OTG_FS) */
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
80025be: 78bb ldrb r3, [r7, #2]
80025c0: 2b02 cmp r3, #2
80025c2: d102 bne.n 80025ca <HAL_PCD_EP_Open+0xa0>
{
ep->data_pid_start = 0U;
80025c4: 68fb ldr r3, [r7, #12]
80025c6: 2200 movs r2, #0
80025c8: 715a strb r2, [r3, #5]
}
__HAL_LOCK(hpcd);
80025ca: 687b ldr r3, [r7, #4]
80025cc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
80025d0: 2b01 cmp r3, #1
80025d2: d101 bne.n 80025d8 <HAL_PCD_EP_Open+0xae>
80025d4: 2302 movs r3, #2
80025d6: e00e b.n 80025f6 <HAL_PCD_EP_Open+0xcc>
80025d8: 687b ldr r3, [r7, #4]
80025da: 2201 movs r2, #1
80025dc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
80025e0: 687b ldr r3, [r7, #4]
80025e2: 681b ldr r3, [r3, #0]
80025e4: 68f9 ldr r1, [r7, #12]
80025e6: 4618 mov r0, r3
80025e8: f002 f942 bl 8004870 <USB_ActivateEndpoint>
__HAL_UNLOCK(hpcd);
80025ec: 687b ldr r3, [r7, #4]
80025ee: 2200 movs r2, #0
80025f0: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return ret;
80025f4: 7afb ldrb r3, [r7, #11]
}
80025f6: 4618 mov r0, r3
80025f8: 3710 adds r7, #16
80025fa: 46bd mov sp, r7
80025fc: bd80 pop {r7, pc}
080025fe <HAL_PCD_EP_Close>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
80025fe: b580 push {r7, lr}
8002600: b084 sub sp, #16
8002602: af00 add r7, sp, #0
8002604: 6078 str r0, [r7, #4]
8002606: 460b mov r3, r1
8002608: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
800260a: f997 3003 ldrsb.w r3, [r7, #3]
800260e: 2b00 cmp r3, #0
8002610: da0f bge.n 8002632 <HAL_PCD_EP_Close+0x34>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8002612: 78fb ldrb r3, [r7, #3]
8002614: f003 020f and.w r2, r3, #15
8002618: 4613 mov r3, r2
800261a: 00db lsls r3, r3, #3
800261c: 4413 add r3, r2
800261e: 009b lsls r3, r3, #2
8002620: 3310 adds r3, #16
8002622: 687a ldr r2, [r7, #4]
8002624: 4413 add r3, r2
8002626: 3304 adds r3, #4
8002628: 60fb str r3, [r7, #12]
ep->is_in = 1U;
800262a: 68fb ldr r3, [r7, #12]
800262c: 2201 movs r2, #1
800262e: 705a strb r2, [r3, #1]
8002630: e00f b.n 8002652 <HAL_PCD_EP_Close+0x54>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8002632: 78fb ldrb r3, [r7, #3]
8002634: f003 020f and.w r2, r3, #15
8002638: 4613 mov r3, r2
800263a: 00db lsls r3, r3, #3
800263c: 4413 add r3, r2
800263e: 009b lsls r3, r3, #2
8002640: f503 7314 add.w r3, r3, #592 @ 0x250
8002644: 687a ldr r2, [r7, #4]
8002646: 4413 add r3, r2
8002648: 3304 adds r3, #4
800264a: 60fb str r3, [r7, #12]
ep->is_in = 0U;
800264c: 68fb ldr r3, [r7, #12]
800264e: 2200 movs r2, #0
8002650: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8002652: 78fb ldrb r3, [r7, #3]
8002654: f003 030f and.w r3, r3, #15
8002658: b2da uxtb r2, r3
800265a: 68fb ldr r3, [r7, #12]
800265c: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
800265e: 687b ldr r3, [r7, #4]
8002660: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
8002664: 2b01 cmp r3, #1
8002666: d101 bne.n 800266c <HAL_PCD_EP_Close+0x6e>
8002668: 2302 movs r3, #2
800266a: e00e b.n 800268a <HAL_PCD_EP_Close+0x8c>
800266c: 687b ldr r3, [r7, #4]
800266e: 2201 movs r2, #1
8002670: f883 2494 strb.w r2, [r3, #1172] @ 0x494
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
8002674: 687b ldr r3, [r7, #4]
8002676: 681b ldr r3, [r3, #0]
8002678: 68f9 ldr r1, [r7, #12]
800267a: 4618 mov r0, r3
800267c: f002 f980 bl 8004980 <USB_DeactivateEndpoint>
__HAL_UNLOCK(hpcd);
8002680: 687b ldr r3, [r7, #4]
8002682: 2200 movs r2, #0
8002684: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
8002688: 2300 movs r3, #0
}
800268a: 4618 mov r0, r3
800268c: 3710 adds r7, #16
800268e: 46bd mov sp, r7
8002690: bd80 pop {r7, pc}
08002692 <HAL_PCD_EP_Receive>:
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8002692: b580 push {r7, lr}
8002694: b086 sub sp, #24
8002696: af00 add r7, sp, #0
8002698: 60f8 str r0, [r7, #12]
800269a: 607a str r2, [r7, #4]
800269c: 603b str r3, [r7, #0]
800269e: 460b mov r3, r1
80026a0: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
80026a2: 7afb ldrb r3, [r7, #11]
80026a4: f003 020f and.w r2, r3, #15
80026a8: 4613 mov r3, r2
80026aa: 00db lsls r3, r3, #3
80026ac: 4413 add r3, r2
80026ae: 009b lsls r3, r3, #2
80026b0: f503 7314 add.w r3, r3, #592 @ 0x250
80026b4: 68fa ldr r2, [r7, #12]
80026b6: 4413 add r3, r2
80026b8: 3304 adds r3, #4
80026ba: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
80026bc: 697b ldr r3, [r7, #20]
80026be: 687a ldr r2, [r7, #4]
80026c0: 60da str r2, [r3, #12]
ep->xfer_len = len;
80026c2: 697b ldr r3, [r7, #20]
80026c4: 683a ldr r2, [r7, #0]
80026c6: 611a str r2, [r3, #16]
ep->xfer_count = 0U;
80026c8: 697b ldr r3, [r7, #20]
80026ca: 2200 movs r2, #0
80026cc: 615a str r2, [r3, #20]
ep->is_in = 0U;
80026ce: 697b ldr r3, [r7, #20]
80026d0: 2200 movs r2, #0
80026d2: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
80026d4: 7afb ldrb r3, [r7, #11]
80026d6: f003 030f and.w r3, r3, #15
80026da: b2da uxtb r2, r3
80026dc: 697b ldr r3, [r7, #20]
80026de: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
80026e0: 68fb ldr r3, [r7, #12]
80026e2: 681b ldr r3, [r3, #0]
80026e4: 6979 ldr r1, [r7, #20]
80026e6: 4618 mov r0, r3
80026e8: f002 fa26 bl 8004b38 <USB_EPStartXfer>
return HAL_OK;
80026ec: 2300 movs r3, #0
}
80026ee: 4618 mov r0, r3
80026f0: 3718 adds r7, #24
80026f2: 46bd mov sp, r7
80026f4: bd80 pop {r7, pc}
080026f6 <HAL_PCD_EP_Transmit>:
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
80026f6: b580 push {r7, lr}
80026f8: b086 sub sp, #24
80026fa: af00 add r7, sp, #0
80026fc: 60f8 str r0, [r7, #12]
80026fe: 607a str r2, [r7, #4]
8002700: 603b str r3, [r7, #0]
8002702: 460b mov r3, r1
8002704: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8002706: 7afb ldrb r3, [r7, #11]
8002708: f003 020f and.w r2, r3, #15
800270c: 4613 mov r3, r2
800270e: 00db lsls r3, r3, #3
8002710: 4413 add r3, r2
8002712: 009b lsls r3, r3, #2
8002714: 3310 adds r3, #16
8002716: 68fa ldr r2, [r7, #12]
8002718: 4413 add r3, r2
800271a: 3304 adds r3, #4
800271c: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
800271e: 697b ldr r3, [r7, #20]
8002720: 687a ldr r2, [r7, #4]
8002722: 60da str r2, [r3, #12]
ep->xfer_len = len;
8002724: 697b ldr r3, [r7, #20]
8002726: 683a ldr r2, [r7, #0]
8002728: 611a str r2, [r3, #16]
#if defined (USB)
ep->xfer_fill_db = 1U;
ep->xfer_len_db = len;
#endif /* defined (USB) */
ep->xfer_count = 0U;
800272a: 697b ldr r3, [r7, #20]
800272c: 2200 movs r2, #0
800272e: 615a str r2, [r3, #20]
ep->is_in = 1U;
8002730: 697b ldr r3, [r7, #20]
8002732: 2201 movs r2, #1
8002734: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8002736: 7afb ldrb r3, [r7, #11]
8002738: f003 030f and.w r3, r3, #15
800273c: b2da uxtb r2, r3
800273e: 697b ldr r3, [r7, #20]
8002740: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8002742: 68fb ldr r3, [r7, #12]
8002744: 681b ldr r3, [r3, #0]
8002746: 6979 ldr r1, [r7, #20]
8002748: 4618 mov r0, r3
800274a: f002 f9f5 bl 8004b38 <USB_EPStartXfer>
return HAL_OK;
800274e: 2300 movs r3, #0
}
8002750: 4618 mov r0, r3
8002752: 3718 adds r7, #24
8002754: 46bd mov sp, r7
8002756: bd80 pop {r7, pc}
08002758 <HAL_PCD_EP_SetStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8002758: b580 push {r7, lr}
800275a: b084 sub sp, #16
800275c: af00 add r7, sp, #0
800275e: 6078 str r0, [r7, #4]
8002760: 460b mov r3, r1
8002762: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
8002764: 78fb ldrb r3, [r7, #3]
8002766: f003 030f and.w r3, r3, #15
800276a: 687a ldr r2, [r7, #4]
800276c: 7912 ldrb r2, [r2, #4]
800276e: 4293 cmp r3, r2
8002770: d901 bls.n 8002776 <HAL_PCD_EP_SetStall+0x1e>
{
return HAL_ERROR;
8002772: 2301 movs r3, #1
8002774: e04e b.n 8002814 <HAL_PCD_EP_SetStall+0xbc>
}
if ((0x80U & ep_addr) == 0x80U)
8002776: f997 3003 ldrsb.w r3, [r7, #3]
800277a: 2b00 cmp r3, #0
800277c: da0f bge.n 800279e <HAL_PCD_EP_SetStall+0x46>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800277e: 78fb ldrb r3, [r7, #3]
8002780: f003 020f and.w r2, r3, #15
8002784: 4613 mov r3, r2
8002786: 00db lsls r3, r3, #3
8002788: 4413 add r3, r2
800278a: 009b lsls r3, r3, #2
800278c: 3310 adds r3, #16
800278e: 687a ldr r2, [r7, #4]
8002790: 4413 add r3, r2
8002792: 3304 adds r3, #4
8002794: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8002796: 68fb ldr r3, [r7, #12]
8002798: 2201 movs r2, #1
800279a: 705a strb r2, [r3, #1]
800279c: e00d b.n 80027ba <HAL_PCD_EP_SetStall+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
800279e: 78fa ldrb r2, [r7, #3]
80027a0: 4613 mov r3, r2
80027a2: 00db lsls r3, r3, #3
80027a4: 4413 add r3, r2
80027a6: 009b lsls r3, r3, #2
80027a8: f503 7314 add.w r3, r3, #592 @ 0x250
80027ac: 687a ldr r2, [r7, #4]
80027ae: 4413 add r3, r2
80027b0: 3304 adds r3, #4
80027b2: 60fb str r3, [r7, #12]
ep->is_in = 0U;
80027b4: 68fb ldr r3, [r7, #12]
80027b6: 2200 movs r2, #0
80027b8: 705a strb r2, [r3, #1]
}
ep->is_stall = 1U;
80027ba: 68fb ldr r3, [r7, #12]
80027bc: 2201 movs r2, #1
80027be: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
80027c0: 78fb ldrb r3, [r7, #3]
80027c2: f003 030f and.w r3, r3, #15
80027c6: b2da uxtb r2, r3
80027c8: 68fb ldr r3, [r7, #12]
80027ca: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
80027cc: 687b ldr r3, [r7, #4]
80027ce: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
80027d2: 2b01 cmp r3, #1
80027d4: d101 bne.n 80027da <HAL_PCD_EP_SetStall+0x82>
80027d6: 2302 movs r3, #2
80027d8: e01c b.n 8002814 <HAL_PCD_EP_SetStall+0xbc>
80027da: 687b ldr r3, [r7, #4]
80027dc: 2201 movs r2, #1
80027de: f883 2494 strb.w r2, [r3, #1172] @ 0x494
(void)USB_EPSetStall(hpcd->Instance, ep);
80027e2: 687b ldr r3, [r7, #4]
80027e4: 681b ldr r3, [r3, #0]
80027e6: 68f9 ldr r1, [r7, #12]
80027e8: 4618 mov r0, r3
80027ea: f002 fd19 bl 8005220 <USB_EPSetStall>
if ((ep_addr & EP_ADDR_MSK) == 0U)
80027ee: 78fb ldrb r3, [r7, #3]
80027f0: f003 030f and.w r3, r3, #15
80027f4: 2b00 cmp r3, #0
80027f6: d108 bne.n 800280a <HAL_PCD_EP_SetStall+0xb2>
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
80027f8: 687b ldr r3, [r7, #4]
80027fa: 681a ldr r2, [r3, #0]
80027fc: 687b ldr r3, [r7, #4]
80027fe: f203 439c addw r3, r3, #1180 @ 0x49c
8002802: 4619 mov r1, r3
8002804: 4610 mov r0, r2
8002806: f002 ff0b bl 8005620 <USB_EP0_OutStart>
}
__HAL_UNLOCK(hpcd);
800280a: 687b ldr r3, [r7, #4]
800280c: 2200 movs r2, #0
800280e: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
8002812: 2300 movs r3, #0
}
8002814: 4618 mov r0, r3
8002816: 3710 adds r7, #16
8002818: 46bd mov sp, r7
800281a: bd80 pop {r7, pc}
0800281c <HAL_PCD_EP_ClrStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
800281c: b580 push {r7, lr}
800281e: b084 sub sp, #16
8002820: af00 add r7, sp, #0
8002822: 6078 str r0, [r7, #4]
8002824: 460b mov r3, r1
8002826: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
8002828: 78fb ldrb r3, [r7, #3]
800282a: f003 030f and.w r3, r3, #15
800282e: 687a ldr r2, [r7, #4]
8002830: 7912 ldrb r2, [r2, #4]
8002832: 4293 cmp r3, r2
8002834: d901 bls.n 800283a <HAL_PCD_EP_ClrStall+0x1e>
{
return HAL_ERROR;
8002836: 2301 movs r3, #1
8002838: e042 b.n 80028c0 <HAL_PCD_EP_ClrStall+0xa4>
}
if ((0x80U & ep_addr) == 0x80U)
800283a: f997 3003 ldrsb.w r3, [r7, #3]
800283e: 2b00 cmp r3, #0
8002840: da0f bge.n 8002862 <HAL_PCD_EP_ClrStall+0x46>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8002842: 78fb ldrb r3, [r7, #3]
8002844: f003 020f and.w r2, r3, #15
8002848: 4613 mov r3, r2
800284a: 00db lsls r3, r3, #3
800284c: 4413 add r3, r2
800284e: 009b lsls r3, r3, #2
8002850: 3310 adds r3, #16
8002852: 687a ldr r2, [r7, #4]
8002854: 4413 add r3, r2
8002856: 3304 adds r3, #4
8002858: 60fb str r3, [r7, #12]
ep->is_in = 1U;
800285a: 68fb ldr r3, [r7, #12]
800285c: 2201 movs r2, #1
800285e: 705a strb r2, [r3, #1]
8002860: e00f b.n 8002882 <HAL_PCD_EP_ClrStall+0x66>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8002862: 78fb ldrb r3, [r7, #3]
8002864: f003 020f and.w r2, r3, #15
8002868: 4613 mov r3, r2
800286a: 00db lsls r3, r3, #3
800286c: 4413 add r3, r2
800286e: 009b lsls r3, r3, #2
8002870: f503 7314 add.w r3, r3, #592 @ 0x250
8002874: 687a ldr r2, [r7, #4]
8002876: 4413 add r3, r2
8002878: 3304 adds r3, #4
800287a: 60fb str r3, [r7, #12]
ep->is_in = 0U;
800287c: 68fb ldr r3, [r7, #12]
800287e: 2200 movs r2, #0
8002880: 705a strb r2, [r3, #1]
}
ep->is_stall = 0U;
8002882: 68fb ldr r3, [r7, #12]
8002884: 2200 movs r2, #0
8002886: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8002888: 78fb ldrb r3, [r7, #3]
800288a: f003 030f and.w r3, r3, #15
800288e: b2da uxtb r2, r3
8002890: 68fb ldr r3, [r7, #12]
8002892: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8002894: 687b ldr r3, [r7, #4]
8002896: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
800289a: 2b01 cmp r3, #1
800289c: d101 bne.n 80028a2 <HAL_PCD_EP_ClrStall+0x86>
800289e: 2302 movs r3, #2
80028a0: e00e b.n 80028c0 <HAL_PCD_EP_ClrStall+0xa4>
80028a2: 687b ldr r3, [r7, #4]
80028a4: 2201 movs r2, #1
80028a6: f883 2494 strb.w r2, [r3, #1172] @ 0x494
(void)USB_EPClearStall(hpcd->Instance, ep);
80028aa: 687b ldr r3, [r7, #4]
80028ac: 681b ldr r3, [r3, #0]
80028ae: 68f9 ldr r1, [r7, #12]
80028b0: 4618 mov r0, r3
80028b2: f002 fd23 bl 80052fc <USB_EPClearStall>
__HAL_UNLOCK(hpcd);
80028b6: 687b ldr r3, [r7, #4]
80028b8: 2200 movs r2, #0
80028ba: f883 2494 strb.w r2, [r3, #1172] @ 0x494
return HAL_OK;
80028be: 2300 movs r3, #0
}
80028c0: 4618 mov r0, r3
80028c2: 3710 adds r7, #16
80028c4: 46bd mov sp, r7
80028c6: bd80 pop {r7, pc}
080028c8 <HAL_PCD_EP_Abort>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
80028c8: b580 push {r7, lr}
80028ca: b084 sub sp, #16
80028cc: af00 add r7, sp, #0
80028ce: 6078 str r0, [r7, #4]
80028d0: 460b mov r3, r1
80028d2: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef ret;
PCD_EPTypeDef *ep;
if ((0x80U & ep_addr) == 0x80U)
80028d4: f997 3003 ldrsb.w r3, [r7, #3]
80028d8: 2b00 cmp r3, #0
80028da: da0c bge.n 80028f6 <HAL_PCD_EP_Abort+0x2e>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
80028dc: 78fb ldrb r3, [r7, #3]
80028de: f003 020f and.w r2, r3, #15
80028e2: 4613 mov r3, r2
80028e4: 00db lsls r3, r3, #3
80028e6: 4413 add r3, r2
80028e8: 009b lsls r3, r3, #2
80028ea: 3310 adds r3, #16
80028ec: 687a ldr r2, [r7, #4]
80028ee: 4413 add r3, r2
80028f0: 3304 adds r3, #4
80028f2: 60fb str r3, [r7, #12]
80028f4: e00c b.n 8002910 <HAL_PCD_EP_Abort+0x48>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
80028f6: 78fb ldrb r3, [r7, #3]
80028f8: f003 020f and.w r2, r3, #15
80028fc: 4613 mov r3, r2
80028fe: 00db lsls r3, r3, #3
8002900: 4413 add r3, r2
8002902: 009b lsls r3, r3, #2
8002904: f503 7314 add.w r3, r3, #592 @ 0x250
8002908: 687a ldr r2, [r7, #4]
800290a: 4413 add r3, r2
800290c: 3304 adds r3, #4
800290e: 60fb str r3, [r7, #12]
}
/* Stop Xfer */
ret = USB_EPStopXfer(hpcd->Instance, ep);
8002910: 687b ldr r3, [r7, #4]
8002912: 681b ldr r3, [r3, #0]
8002914: 68f9 ldr r1, [r7, #12]
8002916: 4618 mov r0, r3
8002918: f002 fb46 bl 8004fa8 <USB_EPStopXfer>
800291c: 4603 mov r3, r0
800291e: 72fb strb r3, [r7, #11]
return ret;
8002920: 7afb ldrb r3, [r7, #11]
}
8002922: 4618 mov r0, r3
8002924: 3710 adds r7, #16
8002926: 46bd mov sp, r7
8002928: bd80 pop {r7, pc}
0800292a <PCD_WriteEmptyTxFifo>:
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
800292a: b580 push {r7, lr}
800292c: b088 sub sp, #32
800292e: af00 add r7, sp, #0
8002930: 6078 str r0, [r7, #4]
8002932: 6039 str r1, [r7, #0]
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8002934: 687b ldr r3, [r7, #4]
8002936: 681b ldr r3, [r3, #0]
8002938: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
800293a: 697b ldr r3, [r7, #20]
800293c: 613b str r3, [r7, #16]
USB_OTG_EPTypeDef *ep;
uint32_t len;
uint32_t len32b;
uint32_t fifoemptymsk;
ep = &hpcd->IN_ep[epnum];
800293e: 683a ldr r2, [r7, #0]
8002940: 4613 mov r3, r2
8002942: 00db lsls r3, r3, #3
8002944: 4413 add r3, r2
8002946: 009b lsls r3, r3, #2
8002948: 3310 adds r3, #16
800294a: 687a ldr r2, [r7, #4]
800294c: 4413 add r3, r2
800294e: 3304 adds r3, #4
8002950: 60fb str r3, [r7, #12]
if (ep->xfer_count > ep->xfer_len)
8002952: 68fb ldr r3, [r7, #12]
8002954: 695a ldr r2, [r3, #20]
8002956: 68fb ldr r3, [r7, #12]
8002958: 691b ldr r3, [r3, #16]
800295a: 429a cmp r2, r3
800295c: d901 bls.n 8002962 <PCD_WriteEmptyTxFifo+0x38>
{
return HAL_ERROR;
800295e: 2301 movs r3, #1
8002960: e067 b.n 8002a32 <PCD_WriteEmptyTxFifo+0x108>
}
len = ep->xfer_len - ep->xfer_count;
8002962: 68fb ldr r3, [r7, #12]
8002964: 691a ldr r2, [r3, #16]
8002966: 68fb ldr r3, [r7, #12]
8002968: 695b ldr r3, [r3, #20]
800296a: 1ad3 subs r3, r2, r3
800296c: 61fb str r3, [r7, #28]
if (len > ep->maxpacket)
800296e: 68fb ldr r3, [r7, #12]
8002970: 689b ldr r3, [r3, #8]
8002972: 69fa ldr r2, [r7, #28]
8002974: 429a cmp r2, r3
8002976: d902 bls.n 800297e <PCD_WriteEmptyTxFifo+0x54>
{
len = ep->maxpacket;
8002978: 68fb ldr r3, [r7, #12]
800297a: 689b ldr r3, [r3, #8]
800297c: 61fb str r3, [r7, #28]
}
len32b = (len + 3U) / 4U;
800297e: 69fb ldr r3, [r7, #28]
8002980: 3303 adds r3, #3
8002982: 089b lsrs r3, r3, #2
8002984: 61bb str r3, [r7, #24]
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
8002986: e026 b.n 80029d6 <PCD_WriteEmptyTxFifo+0xac>
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
8002988: 68fb ldr r3, [r7, #12]
800298a: 691a ldr r2, [r3, #16]
800298c: 68fb ldr r3, [r7, #12]
800298e: 695b ldr r3, [r3, #20]
8002990: 1ad3 subs r3, r2, r3
8002992: 61fb str r3, [r7, #28]
if (len > ep->maxpacket)
8002994: 68fb ldr r3, [r7, #12]
8002996: 689b ldr r3, [r3, #8]
8002998: 69fa ldr r2, [r7, #28]
800299a: 429a cmp r2, r3
800299c: d902 bls.n 80029a4 <PCD_WriteEmptyTxFifo+0x7a>
{
len = ep->maxpacket;
800299e: 68fb ldr r3, [r7, #12]
80029a0: 689b ldr r3, [r3, #8]
80029a2: 61fb str r3, [r7, #28]
}
len32b = (len + 3U) / 4U;
80029a4: 69fb ldr r3, [r7, #28]
80029a6: 3303 adds r3, #3
80029a8: 089b lsrs r3, r3, #2
80029aa: 61bb str r3, [r7, #24]
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len);
80029ac: 68fb ldr r3, [r7, #12]
80029ae: 68d9 ldr r1, [r3, #12]
80029b0: 683b ldr r3, [r7, #0]
80029b2: b2da uxtb r2, r3
80029b4: 69fb ldr r3, [r7, #28]
80029b6: b29b uxth r3, r3
80029b8: 6978 ldr r0, [r7, #20]
80029ba: f002 fb9f bl 80050fc <USB_WritePacket>
ep->xfer_buff += len;
80029be: 68fb ldr r3, [r7, #12]
80029c0: 68da ldr r2, [r3, #12]
80029c2: 69fb ldr r3, [r7, #28]
80029c4: 441a add r2, r3
80029c6: 68fb ldr r3, [r7, #12]
80029c8: 60da str r2, [r3, #12]
ep->xfer_count += len;
80029ca: 68fb ldr r3, [r7, #12]
80029cc: 695a ldr r2, [r3, #20]
80029ce: 69fb ldr r3, [r7, #28]
80029d0: 441a add r2, r3
80029d2: 68fb ldr r3, [r7, #12]
80029d4: 615a str r2, [r3, #20]
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
80029d6: 683b ldr r3, [r7, #0]
80029d8: 015a lsls r2, r3, #5
80029da: 693b ldr r3, [r7, #16]
80029dc: 4413 add r3, r2
80029de: f503 6310 add.w r3, r3, #2304 @ 0x900
80029e2: 699b ldr r3, [r3, #24]
80029e4: b29b uxth r3, r3
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
80029e6: 69ba ldr r2, [r7, #24]
80029e8: 429a cmp r2, r3
80029ea: d809 bhi.n 8002a00 <PCD_WriteEmptyTxFifo+0xd6>
80029ec: 68fb ldr r3, [r7, #12]
80029ee: 695a ldr r2, [r3, #20]
80029f0: 68fb ldr r3, [r7, #12]
80029f2: 691b ldr r3, [r3, #16]
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
80029f4: 429a cmp r2, r3
80029f6: d203 bcs.n 8002a00 <PCD_WriteEmptyTxFifo+0xd6>
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
80029f8: 68fb ldr r3, [r7, #12]
80029fa: 691b ldr r3, [r3, #16]
80029fc: 2b00 cmp r3, #0
80029fe: d1c3 bne.n 8002988 <PCD_WriteEmptyTxFifo+0x5e>
}
if (ep->xfer_len <= ep->xfer_count)
8002a00: 68fb ldr r3, [r7, #12]
8002a02: 691a ldr r2, [r3, #16]
8002a04: 68fb ldr r3, [r7, #12]
8002a06: 695b ldr r3, [r3, #20]
8002a08: 429a cmp r2, r3
8002a0a: d811 bhi.n 8002a30 <PCD_WriteEmptyTxFifo+0x106>
{
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
8002a0c: 683b ldr r3, [r7, #0]
8002a0e: f003 030f and.w r3, r3, #15
8002a12: 2201 movs r2, #1
8002a14: fa02 f303 lsl.w r3, r2, r3
8002a18: 60bb str r3, [r7, #8]
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
8002a1a: 693b ldr r3, [r7, #16]
8002a1c: f503 6300 add.w r3, r3, #2048 @ 0x800
8002a20: 6b5a ldr r2, [r3, #52] @ 0x34
8002a22: 68bb ldr r3, [r7, #8]
8002a24: 43db mvns r3, r3
8002a26: 6939 ldr r1, [r7, #16]
8002a28: f501 6100 add.w r1, r1, #2048 @ 0x800
8002a2c: 4013 ands r3, r2
8002a2e: 634b str r3, [r1, #52] @ 0x34
}
return HAL_OK;
8002a30: 2300 movs r3, #0
}
8002a32: 4618 mov r0, r3
8002a34: 3720 adds r7, #32
8002a36: 46bd mov sp, r7
8002a38: bd80 pop {r7, pc}
...
08002a3c <PCD_EP_OutXfrComplete_int>:
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
8002a3c: b580 push {r7, lr}
8002a3e: b086 sub sp, #24
8002a40: af00 add r7, sp, #0
8002a42: 6078 str r0, [r7, #4]
8002a44: 6039 str r1, [r7, #0]
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8002a46: 687b ldr r3, [r7, #4]
8002a48: 681b ldr r3, [r3, #0]
8002a4a: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
8002a4c: 697b ldr r3, [r7, #20]
8002a4e: 613b str r3, [r7, #16]
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
8002a50: 697b ldr r3, [r7, #20]
8002a52: 333c adds r3, #60 @ 0x3c
8002a54: 3304 adds r3, #4
8002a56: 681b ldr r3, [r3, #0]
8002a58: 60fb str r3, [r7, #12]
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
8002a5a: 683b ldr r3, [r7, #0]
8002a5c: 015a lsls r2, r3, #5
8002a5e: 693b ldr r3, [r7, #16]
8002a60: 4413 add r3, r2
8002a62: f503 6330 add.w r3, r3, #2816 @ 0xb00
8002a66: 689b ldr r3, [r3, #8]
8002a68: 60bb str r3, [r7, #8]
if (gSNPSiD == USB_OTG_CORE_ID_310A)
8002a6a: 68fb ldr r3, [r7, #12]
8002a6c: 4a19 ldr r2, [pc, #100] @ (8002ad4 <PCD_EP_OutXfrComplete_int+0x98>)
8002a6e: 4293 cmp r3, r2
8002a70: d124 bne.n 8002abc <PCD_EP_OutXfrComplete_int+0x80>
{
/* StupPktRcvd = 1 this is a setup packet */
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
8002a72: 68bb ldr r3, [r7, #8]
8002a74: f403 4300 and.w r3, r3, #32768 @ 0x8000
8002a78: 2b00 cmp r3, #0
8002a7a: d00a beq.n 8002a92 <PCD_EP_OutXfrComplete_int+0x56>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
8002a7c: 683b ldr r3, [r7, #0]
8002a7e: 015a lsls r2, r3, #5
8002a80: 693b ldr r3, [r7, #16]
8002a82: 4413 add r3, r2
8002a84: f503 6330 add.w r3, r3, #2816 @ 0xb00
8002a88: 461a mov r2, r3
8002a8a: f44f 4300 mov.w r3, #32768 @ 0x8000
8002a8e: 6093 str r3, [r2, #8]
8002a90: e01a b.n 8002ac8 <PCD_EP_OutXfrComplete_int+0x8c>
}
else
{
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
8002a92: 68bb ldr r3, [r7, #8]
8002a94: f003 0320 and.w r3, r3, #32
8002a98: 2b00 cmp r3, #0
8002a9a: d008 beq.n 8002aae <PCD_EP_OutXfrComplete_int+0x72>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
8002a9c: 683b ldr r3, [r7, #0]
8002a9e: 015a lsls r2, r3, #5
8002aa0: 693b ldr r3, [r7, #16]
8002aa2: 4413 add r3, r2
8002aa4: f503 6330 add.w r3, r3, #2816 @ 0xb00
8002aa8: 461a mov r2, r3
8002aaa: 2320 movs r3, #32
8002aac: 6093 str r3, [r2, #8]
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
8002aae: 683b ldr r3, [r7, #0]
8002ab0: b2db uxtb r3, r3
8002ab2: 4619 mov r1, r3
8002ab4: 6878 ldr r0, [r7, #4]
8002ab6: f004 ff55 bl 8007964 <HAL_PCD_DataOutStageCallback>
8002aba: e005 b.n 8002ac8 <PCD_EP_OutXfrComplete_int+0x8c>
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
8002abc: 683b ldr r3, [r7, #0]
8002abe: b2db uxtb r3, r3
8002ac0: 4619 mov r1, r3
8002ac2: 6878 ldr r0, [r7, #4]
8002ac4: f004 ff4e bl 8007964 <HAL_PCD_DataOutStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
return HAL_OK;
8002ac8: 2300 movs r3, #0
}
8002aca: 4618 mov r0, r3
8002acc: 3718 adds r7, #24
8002ace: 46bd mov sp, r7
8002ad0: bd80 pop {r7, pc}
8002ad2: bf00 nop
8002ad4: 4f54310a .word 0x4f54310a
08002ad8 <PCD_EP_OutSetupPacket_int>:
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
8002ad8: b580 push {r7, lr}
8002ada: b086 sub sp, #24
8002adc: af00 add r7, sp, #0
8002ade: 6078 str r0, [r7, #4]
8002ae0: 6039 str r1, [r7, #0]
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8002ae2: 687b ldr r3, [r7, #4]
8002ae4: 681b ldr r3, [r3, #0]
8002ae6: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
8002ae8: 697b ldr r3, [r7, #20]
8002aea: 613b str r3, [r7, #16]
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
8002aec: 697b ldr r3, [r7, #20]
8002aee: 333c adds r3, #60 @ 0x3c
8002af0: 3304 adds r3, #4
8002af2: 681b ldr r3, [r3, #0]
8002af4: 60fb str r3, [r7, #12]
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
8002af6: 683b ldr r3, [r7, #0]
8002af8: 015a lsls r2, r3, #5
8002afa: 693b ldr r3, [r7, #16]
8002afc: 4413 add r3, r2
8002afe: f503 6330 add.w r3, r3, #2816 @ 0xb00
8002b02: 689b ldr r3, [r3, #8]
8002b04: 60bb str r3, [r7, #8]
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
8002b06: 68fb ldr r3, [r7, #12]
8002b08: 4a0c ldr r2, [pc, #48] @ (8002b3c <PCD_EP_OutSetupPacket_int+0x64>)
8002b0a: 4293 cmp r3, r2
8002b0c: d90e bls.n 8002b2c <PCD_EP_OutSetupPacket_int+0x54>
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
8002b0e: 68bb ldr r3, [r7, #8]
8002b10: f403 4300 and.w r3, r3, #32768 @ 0x8000
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
8002b14: 2b00 cmp r3, #0
8002b16: d009 beq.n 8002b2c <PCD_EP_OutSetupPacket_int+0x54>
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
8002b18: 683b ldr r3, [r7, #0]
8002b1a: 015a lsls r2, r3, #5
8002b1c: 693b ldr r3, [r7, #16]
8002b1e: 4413 add r3, r2
8002b20: f503 6330 add.w r3, r3, #2816 @ 0xb00
8002b24: 461a mov r2, r3
8002b26: f44f 4300 mov.w r3, #32768 @ 0x8000
8002b2a: 6093 str r3, [r2, #8]
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
8002b2c: 6878 ldr r0, [r7, #4]
8002b2e: f004 ff07 bl 8007940 <HAL_PCD_SetupStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return HAL_OK;
8002b32: 2300 movs r3, #0
}
8002b34: 4618 mov r0, r3
8002b36: 3718 adds r7, #24
8002b38: 46bd mov sp, r7
8002b3a: bd80 pop {r7, pc}
8002b3c: 4f54300a .word 0x4f54300a
08002b40 <HAL_PCDEx_SetTxFiFo>:
* @param fifo The number of Tx fifo
* @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
8002b40: b480 push {r7}
8002b42: b085 sub sp, #20
8002b44: af00 add r7, sp, #0
8002b46: 6078 str r0, [r7, #4]
8002b48: 460b mov r3, r1
8002b4a: 70fb strb r3, [r7, #3]
8002b4c: 4613 mov r3, r2
8002b4e: 803b strh r3, [r7, #0]
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
8002b50: 687b ldr r3, [r7, #4]
8002b52: 681b ldr r3, [r3, #0]
8002b54: 6a5b ldr r3, [r3, #36] @ 0x24
8002b56: 60bb str r3, [r7, #8]
if (fifo == 0U)
8002b58: 78fb ldrb r3, [r7, #3]
8002b5a: 2b00 cmp r3, #0
8002b5c: d107 bne.n 8002b6e <HAL_PCDEx_SetTxFiFo+0x2e>
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
8002b5e: 883b ldrh r3, [r7, #0]
8002b60: 0419 lsls r1, r3, #16
8002b62: 687b ldr r3, [r7, #4]
8002b64: 681b ldr r3, [r3, #0]
8002b66: 68ba ldr r2, [r7, #8]
8002b68: 430a orrs r2, r1
8002b6a: 629a str r2, [r3, #40] @ 0x28
8002b6c: e028 b.n 8002bc0 <HAL_PCDEx_SetTxFiFo+0x80>
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
8002b6e: 687b ldr r3, [r7, #4]
8002b70: 681b ldr r3, [r3, #0]
8002b72: 6a9b ldr r3, [r3, #40] @ 0x28
8002b74: 0c1b lsrs r3, r3, #16
8002b76: 68ba ldr r2, [r7, #8]
8002b78: 4413 add r3, r2
8002b7a: 60bb str r3, [r7, #8]
for (i = 0U; i < (fifo - 1U); i++)
8002b7c: 2300 movs r3, #0
8002b7e: 73fb strb r3, [r7, #15]
8002b80: e00d b.n 8002b9e <HAL_PCDEx_SetTxFiFo+0x5e>
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
8002b82: 687b ldr r3, [r7, #4]
8002b84: 681a ldr r2, [r3, #0]
8002b86: 7bfb ldrb r3, [r7, #15]
8002b88: 3340 adds r3, #64 @ 0x40
8002b8a: 009b lsls r3, r3, #2
8002b8c: 4413 add r3, r2
8002b8e: 685b ldr r3, [r3, #4]
8002b90: 0c1b lsrs r3, r3, #16
8002b92: 68ba ldr r2, [r7, #8]
8002b94: 4413 add r3, r2
8002b96: 60bb str r3, [r7, #8]
for (i = 0U; i < (fifo - 1U); i++)
8002b98: 7bfb ldrb r3, [r7, #15]
8002b9a: 3301 adds r3, #1
8002b9c: 73fb strb r3, [r7, #15]
8002b9e: 7bfa ldrb r2, [r7, #15]
8002ba0: 78fb ldrb r3, [r7, #3]
8002ba2: 3b01 subs r3, #1
8002ba4: 429a cmp r2, r3
8002ba6: d3ec bcc.n 8002b82 <HAL_PCDEx_SetTxFiFo+0x42>
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
8002ba8: 883b ldrh r3, [r7, #0]
8002baa: 0418 lsls r0, r3, #16
8002bac: 687b ldr r3, [r7, #4]
8002bae: 6819 ldr r1, [r3, #0]
8002bb0: 78fb ldrb r3, [r7, #3]
8002bb2: 3b01 subs r3, #1
8002bb4: 68ba ldr r2, [r7, #8]
8002bb6: 4302 orrs r2, r0
8002bb8: 3340 adds r3, #64 @ 0x40
8002bba: 009b lsls r3, r3, #2
8002bbc: 440b add r3, r1
8002bbe: 605a str r2, [r3, #4]
}
return HAL_OK;
8002bc0: 2300 movs r3, #0
}
8002bc2: 4618 mov r0, r3
8002bc4: 3714 adds r7, #20
8002bc6: 46bd mov sp, r7
8002bc8: f85d 7b04 ldr.w r7, [sp], #4
8002bcc: 4770 bx lr
08002bce <HAL_PCDEx_SetRxFiFo>:
* @param hpcd PCD handle
* @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
8002bce: b480 push {r7}
8002bd0: b083 sub sp, #12
8002bd2: af00 add r7, sp, #0
8002bd4: 6078 str r0, [r7, #4]
8002bd6: 460b mov r3, r1
8002bd8: 807b strh r3, [r7, #2]
hpcd->Instance->GRXFSIZ = size;
8002bda: 687b ldr r3, [r7, #4]
8002bdc: 681b ldr r3, [r3, #0]
8002bde: 887a ldrh r2, [r7, #2]
8002be0: 625a str r2, [r3, #36] @ 0x24
return HAL_OK;
8002be2: 2300 movs r3, #0
}
8002be4: 4618 mov r0, r3
8002be6: 370c adds r7, #12
8002be8: 46bd mov sp, r7
8002bea: f85d 7b04 ldr.w r7, [sp], #4
8002bee: 4770 bx lr
08002bf0 <HAL_PCDEx_ActivateLPM>:
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
8002bf0: b480 push {r7}
8002bf2: b085 sub sp, #20
8002bf4: af00 add r7, sp, #0
8002bf6: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8002bf8: 687b ldr r3, [r7, #4]
8002bfa: 681b ldr r3, [r3, #0]
8002bfc: 60fb str r3, [r7, #12]
hpcd->lpm_active = 1U;
8002bfe: 687b ldr r3, [r7, #4]
8002c00: 2201 movs r2, #1
8002c02: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
hpcd->LPM_State = LPM_L0;
8002c06: 687b ldr r3, [r7, #4]
8002c08: 2200 movs r2, #0
8002c0a: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
8002c0e: 68fb ldr r3, [r7, #12]
8002c10: 699b ldr r3, [r3, #24]
8002c12: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
8002c16: 68fb ldr r3, [r7, #12]
8002c18: 619a str r2, [r3, #24]
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
8002c1a: 68fb ldr r3, [r7, #12]
8002c1c: 6d5b ldr r3, [r3, #84] @ 0x54
8002c1e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002c22: f043 0303 orr.w r3, r3, #3
8002c26: 68fa ldr r2, [r7, #12]
8002c28: 6553 str r3, [r2, #84] @ 0x54
return HAL_OK;
8002c2a: 2300 movs r3, #0
}
8002c2c: 4618 mov r0, r3
8002c2e: 3714 adds r7, #20
8002c30: 46bd mov sp, r7
8002c32: f85d 7b04 ldr.w r7, [sp], #4
8002c36: 4770 bx lr
08002c38 <HAL_PWREx_GetVoltageRange>:
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
8002c38: b480 push {r7}
8002c3a: af00 add r7, sp, #0
else
{
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
}
#else
return (PWR->CR1 & PWR_CR1_VOS);
8002c3c: 4b04 ldr r3, [pc, #16] @ (8002c50 <HAL_PWREx_GetVoltageRange+0x18>)
8002c3e: 681b ldr r3, [r3, #0]
8002c40: f403 63c0 and.w r3, r3, #1536 @ 0x600
#endif
}
8002c44: 4618 mov r0, r3
8002c46: 46bd mov sp, r7
8002c48: f85d 7b04 ldr.w r7, [sp], #4
8002c4c: 4770 bx lr
8002c4e: bf00 nop
8002c50: 40007000 .word 0x40007000
08002c54 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8002c54: b480 push {r7}
8002c56: b085 sub sp, #20
8002c58: af00 add r7, sp, #0
8002c5a: 6078 str r0, [r7, #4]
}
#else
/* If Set Range 1 */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8002c5c: 687b ldr r3, [r7, #4]
8002c5e: f5b3 7f00 cmp.w r3, #512 @ 0x200
8002c62: d130 bne.n 8002cc6 <HAL_PWREx_ControlVoltageScaling+0x72>
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
8002c64: 4b23 ldr r3, [pc, #140] @ (8002cf4 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002c66: 681b ldr r3, [r3, #0]
8002c68: f403 63c0 and.w r3, r3, #1536 @ 0x600
8002c6c: f5b3 7f00 cmp.w r3, #512 @ 0x200
8002c70: d038 beq.n 8002ce4 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8002c72: 4b20 ldr r3, [pc, #128] @ (8002cf4 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002c74: 681b ldr r3, [r3, #0]
8002c76: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8002c7a: 4a1e ldr r2, [pc, #120] @ (8002cf4 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002c7c: f443 7300 orr.w r3, r3, #512 @ 0x200
8002c80: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8002c82: 4b1d ldr r3, [pc, #116] @ (8002cf8 <HAL_PWREx_ControlVoltageScaling+0xa4>)
8002c84: 681b ldr r3, [r3, #0]
8002c86: 2232 movs r2, #50 @ 0x32
8002c88: fb02 f303 mul.w r3, r2, r3
8002c8c: 4a1b ldr r2, [pc, #108] @ (8002cfc <HAL_PWREx_ControlVoltageScaling+0xa8>)
8002c8e: fba2 2303 umull r2, r3, r2, r3
8002c92: 0c9b lsrs r3, r3, #18
8002c94: 3301 adds r3, #1
8002c96: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8002c98: e002 b.n 8002ca0 <HAL_PWREx_ControlVoltageScaling+0x4c>
{
wait_loop_index--;
8002c9a: 68fb ldr r3, [r7, #12]
8002c9c: 3b01 subs r3, #1
8002c9e: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8002ca0: 4b14 ldr r3, [pc, #80] @ (8002cf4 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002ca2: 695b ldr r3, [r3, #20]
8002ca4: f403 6380 and.w r3, r3, #1024 @ 0x400
8002ca8: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002cac: d102 bne.n 8002cb4 <HAL_PWREx_ControlVoltageScaling+0x60>
8002cae: 68fb ldr r3, [r7, #12]
8002cb0: 2b00 cmp r3, #0
8002cb2: d1f2 bne.n 8002c9a <HAL_PWREx_ControlVoltageScaling+0x46>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8002cb4: 4b0f ldr r3, [pc, #60] @ (8002cf4 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002cb6: 695b ldr r3, [r3, #20]
8002cb8: f403 6380 and.w r3, r3, #1024 @ 0x400
8002cbc: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002cc0: d110 bne.n 8002ce4 <HAL_PWREx_ControlVoltageScaling+0x90>
{
return HAL_TIMEOUT;
8002cc2: 2303 movs r3, #3
8002cc4: e00f b.n 8002ce6 <HAL_PWREx_ControlVoltageScaling+0x92>
}
}
}
else
{
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
8002cc6: 4b0b ldr r3, [pc, #44] @ (8002cf4 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002cc8: 681b ldr r3, [r3, #0]
8002cca: f403 63c0 and.w r3, r3, #1536 @ 0x600
8002cce: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002cd2: d007 beq.n 8002ce4 <HAL_PWREx_ControlVoltageScaling+0x90>
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
8002cd4: 4b07 ldr r3, [pc, #28] @ (8002cf4 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002cd6: 681b ldr r3, [r3, #0]
8002cd8: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8002cdc: 4a05 ldr r2, [pc, #20] @ (8002cf4 <HAL_PWREx_ControlVoltageScaling+0xa0>)
8002cde: f443 6380 orr.w r3, r3, #1024 @ 0x400
8002ce2: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
}
}
#endif
return HAL_OK;
8002ce4: 2300 movs r3, #0
}
8002ce6: 4618 mov r0, r3
8002ce8: 3714 adds r7, #20
8002cea: 46bd mov sp, r7
8002cec: f85d 7b04 ldr.w r7, [sp], #4
8002cf0: 4770 bx lr
8002cf2: bf00 nop
8002cf4: 40007000 .word 0x40007000
8002cf8: 20000000 .word 0x20000000
8002cfc: 431bde83 .word 0x431bde83
08002d00 <HAL_PWREx_EnableVddUSB>:
* @brief Enable VDDUSB supply.
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
* @retval None
*/
void HAL_PWREx_EnableVddUSB(void)
{
8002d00: b480 push {r7}
8002d02: af00 add r7, sp, #0
SET_BIT(PWR->CR2, PWR_CR2_USV);
8002d04: 4b05 ldr r3, [pc, #20] @ (8002d1c <HAL_PWREx_EnableVddUSB+0x1c>)
8002d06: 685b ldr r3, [r3, #4]
8002d08: 4a04 ldr r2, [pc, #16] @ (8002d1c <HAL_PWREx_EnableVddUSB+0x1c>)
8002d0a: f443 6380 orr.w r3, r3, #1024 @ 0x400
8002d0e: 6053 str r3, [r2, #4]
}
8002d10: bf00 nop
8002d12: 46bd mov sp, r7
8002d14: f85d 7b04 ldr.w r7, [sp], #4
8002d18: 4770 bx lr
8002d1a: bf00 nop
8002d1c: 40007000 .word 0x40007000
08002d20 <HAL_RCC_OscConfig>:
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8002d20: b580 push {r7, lr}
8002d22: b088 sub sp, #32
8002d24: af00 add r7, sp, #0
8002d26: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8002d28: 687b ldr r3, [r7, #4]
8002d2a: 2b00 cmp r3, #0
8002d2c: d101 bne.n 8002d32 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8002d2e: 2301 movs r3, #1
8002d30: e3ca b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8002d32: 4b97 ldr r3, [pc, #604] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002d34: 689b ldr r3, [r3, #8]
8002d36: f003 030c and.w r3, r3, #12
8002d3a: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
8002d3c: 4b94 ldr r3, [pc, #592] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002d3e: 68db ldr r3, [r3, #12]
8002d40: f003 0303 and.w r3, r3, #3
8002d44: 617b str r3, [r7, #20]
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8002d46: 687b ldr r3, [r7, #4]
8002d48: 681b ldr r3, [r3, #0]
8002d4a: f003 0310 and.w r3, r3, #16
8002d4e: 2b00 cmp r3, #0
8002d50: f000 80e4 beq.w 8002f1c <HAL_RCC_OscConfig+0x1fc>
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
8002d54: 69bb ldr r3, [r7, #24]
8002d56: 2b00 cmp r3, #0
8002d58: d007 beq.n 8002d6a <HAL_RCC_OscConfig+0x4a>
8002d5a: 69bb ldr r3, [r7, #24]
8002d5c: 2b0c cmp r3, #12
8002d5e: f040 808b bne.w 8002e78 <HAL_RCC_OscConfig+0x158>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
8002d62: 697b ldr r3, [r7, #20]
8002d64: 2b01 cmp r3, #1
8002d66: f040 8087 bne.w 8002e78 <HAL_RCC_OscConfig+0x158>
{
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8002d6a: 4b89 ldr r3, [pc, #548] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002d6c: 681b ldr r3, [r3, #0]
8002d6e: f003 0302 and.w r3, r3, #2
8002d72: 2b00 cmp r3, #0
8002d74: d005 beq.n 8002d82 <HAL_RCC_OscConfig+0x62>
8002d76: 687b ldr r3, [r7, #4]
8002d78: 699b ldr r3, [r3, #24]
8002d7a: 2b00 cmp r3, #0
8002d7c: d101 bne.n 8002d82 <HAL_RCC_OscConfig+0x62>
{
return HAL_ERROR;
8002d7e: 2301 movs r3, #1
8002d80: e3a2 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
else
{
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
8002d82: 687b ldr r3, [r7, #4]
8002d84: 6a1a ldr r2, [r3, #32]
8002d86: 4b82 ldr r3, [pc, #520] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002d88: 681b ldr r3, [r3, #0]
8002d8a: f003 0308 and.w r3, r3, #8
8002d8e: 2b00 cmp r3, #0
8002d90: d004 beq.n 8002d9c <HAL_RCC_OscConfig+0x7c>
8002d92: 4b7f ldr r3, [pc, #508] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002d94: 681b ldr r3, [r3, #0]
8002d96: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002d9a: e005 b.n 8002da8 <HAL_RCC_OscConfig+0x88>
8002d9c: 4b7c ldr r3, [pc, #496] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002d9e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8002da2: 091b lsrs r3, r3, #4
8002da4: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002da8: 4293 cmp r3, r2
8002daa: d223 bcs.n 8002df4 <HAL_RCC_OscConfig+0xd4>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8002dac: 687b ldr r3, [r7, #4]
8002dae: 6a1b ldr r3, [r3, #32]
8002db0: 4618 mov r0, r3
8002db2: f000 fd29 bl 8003808 <RCC_SetFlashLatencyFromMSIRange>
8002db6: 4603 mov r3, r0
8002db8: 2b00 cmp r3, #0
8002dba: d001 beq.n 8002dc0 <HAL_RCC_OscConfig+0xa0>
{
return HAL_ERROR;
8002dbc: 2301 movs r3, #1
8002dbe: e383 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8002dc0: 4b73 ldr r3, [pc, #460] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002dc2: 681b ldr r3, [r3, #0]
8002dc4: 4a72 ldr r2, [pc, #456] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002dc6: f043 0308 orr.w r3, r3, #8
8002dca: 6013 str r3, [r2, #0]
8002dcc: 4b70 ldr r3, [pc, #448] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002dce: 681b ldr r3, [r3, #0]
8002dd0: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002dd4: 687b ldr r3, [r7, #4]
8002dd6: 6a1b ldr r3, [r3, #32]
8002dd8: 496d ldr r1, [pc, #436] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002dda: 4313 orrs r3, r2
8002ddc: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8002dde: 4b6c ldr r3, [pc, #432] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002de0: 685b ldr r3, [r3, #4]
8002de2: f423 427f bic.w r2, r3, #65280 @ 0xff00
8002de6: 687b ldr r3, [r7, #4]
8002de8: 69db ldr r3, [r3, #28]
8002dea: 021b lsls r3, r3, #8
8002dec: 4968 ldr r1, [pc, #416] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002dee: 4313 orrs r3, r2
8002df0: 604b str r3, [r1, #4]
8002df2: e025 b.n 8002e40 <HAL_RCC_OscConfig+0x120>
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8002df4: 4b66 ldr r3, [pc, #408] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002df6: 681b ldr r3, [r3, #0]
8002df8: 4a65 ldr r2, [pc, #404] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002dfa: f043 0308 orr.w r3, r3, #8
8002dfe: 6013 str r3, [r2, #0]
8002e00: 4b63 ldr r3, [pc, #396] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002e02: 681b ldr r3, [r3, #0]
8002e04: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002e08: 687b ldr r3, [r7, #4]
8002e0a: 6a1b ldr r3, [r3, #32]
8002e0c: 4960 ldr r1, [pc, #384] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002e0e: 4313 orrs r3, r2
8002e10: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8002e12: 4b5f ldr r3, [pc, #380] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002e14: 685b ldr r3, [r3, #4]
8002e16: f423 427f bic.w r2, r3, #65280 @ 0xff00
8002e1a: 687b ldr r3, [r7, #4]
8002e1c: 69db ldr r3, [r3, #28]
8002e1e: 021b lsls r3, r3, #8
8002e20: 495b ldr r1, [pc, #364] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002e22: 4313 orrs r3, r2
8002e24: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
/* Only possible when MSI is the System clock source */
if(sysclk_source == RCC_CFGR_SWS_MSI)
8002e26: 69bb ldr r3, [r7, #24]
8002e28: 2b00 cmp r3, #0
8002e2a: d109 bne.n 8002e40 <HAL_RCC_OscConfig+0x120>
{
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8002e2c: 687b ldr r3, [r7, #4]
8002e2e: 6a1b ldr r3, [r3, #32]
8002e30: 4618 mov r0, r3
8002e32: f000 fce9 bl 8003808 <RCC_SetFlashLatencyFromMSIRange>
8002e36: 4603 mov r3, r0
8002e38: 2b00 cmp r3, #0
8002e3a: d001 beq.n 8002e40 <HAL_RCC_OscConfig+0x120>
{
return HAL_ERROR;
8002e3c: 2301 movs r3, #1
8002e3e: e343 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8002e40: f000 fc4a bl 80036d8 <HAL_RCC_GetSysClockFreq>
8002e44: 4602 mov r2, r0
8002e46: 4b52 ldr r3, [pc, #328] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002e48: 689b ldr r3, [r3, #8]
8002e4a: 091b lsrs r3, r3, #4
8002e4c: f003 030f and.w r3, r3, #15
8002e50: 4950 ldr r1, [pc, #320] @ (8002f94 <HAL_RCC_OscConfig+0x274>)
8002e52: 5ccb ldrb r3, [r1, r3]
8002e54: f003 031f and.w r3, r3, #31
8002e58: fa22 f303 lsr.w r3, r2, r3
8002e5c: 4a4e ldr r2, [pc, #312] @ (8002f98 <HAL_RCC_OscConfig+0x278>)
8002e5e: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8002e60: 4b4e ldr r3, [pc, #312] @ (8002f9c <HAL_RCC_OscConfig+0x27c>)
8002e62: 681b ldr r3, [r3, #0]
8002e64: 4618 mov r0, r3
8002e66: f7fd fc09 bl 800067c <HAL_InitTick>
8002e6a: 4603 mov r3, r0
8002e6c: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
8002e6e: 7bfb ldrb r3, [r7, #15]
8002e70: 2b00 cmp r3, #0
8002e72: d052 beq.n 8002f1a <HAL_RCC_OscConfig+0x1fa>
{
return status;
8002e74: 7bfb ldrb r3, [r7, #15]
8002e76: e327 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
}
else
{
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8002e78: 687b ldr r3, [r7, #4]
8002e7a: 699b ldr r3, [r3, #24]
8002e7c: 2b00 cmp r3, #0
8002e7e: d032 beq.n 8002ee6 <HAL_RCC_OscConfig+0x1c6>
{
/* Enable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
8002e80: 4b43 ldr r3, [pc, #268] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002e82: 681b ldr r3, [r3, #0]
8002e84: 4a42 ldr r2, [pc, #264] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002e86: f043 0301 orr.w r3, r3, #1
8002e8a: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8002e8c: f7fd fc46 bl 800071c <HAL_GetTick>
8002e90: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8002e92: e008 b.n 8002ea6 <HAL_RCC_OscConfig+0x186>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8002e94: f7fd fc42 bl 800071c <HAL_GetTick>
8002e98: 4602 mov r2, r0
8002e9a: 693b ldr r3, [r7, #16]
8002e9c: 1ad3 subs r3, r2, r3
8002e9e: 2b02 cmp r3, #2
8002ea0: d901 bls.n 8002ea6 <HAL_RCC_OscConfig+0x186>
{
return HAL_TIMEOUT;
8002ea2: 2303 movs r3, #3
8002ea4: e310 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8002ea6: 4b3a ldr r3, [pc, #232] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002ea8: 681b ldr r3, [r3, #0]
8002eaa: f003 0302 and.w r3, r3, #2
8002eae: 2b00 cmp r3, #0
8002eb0: d0f0 beq.n 8002e94 <HAL_RCC_OscConfig+0x174>
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8002eb2: 4b37 ldr r3, [pc, #220] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002eb4: 681b ldr r3, [r3, #0]
8002eb6: 4a36 ldr r2, [pc, #216] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002eb8: f043 0308 orr.w r3, r3, #8
8002ebc: 6013 str r3, [r2, #0]
8002ebe: 4b34 ldr r3, [pc, #208] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002ec0: 681b ldr r3, [r3, #0]
8002ec2: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002ec6: 687b ldr r3, [r7, #4]
8002ec8: 6a1b ldr r3, [r3, #32]
8002eca: 4931 ldr r1, [pc, #196] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002ecc: 4313 orrs r3, r2
8002ece: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8002ed0: 4b2f ldr r3, [pc, #188] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002ed2: 685b ldr r3, [r3, #4]
8002ed4: f423 427f bic.w r2, r3, #65280 @ 0xff00
8002ed8: 687b ldr r3, [r7, #4]
8002eda: 69db ldr r3, [r3, #28]
8002edc: 021b lsls r3, r3, #8
8002ede: 492c ldr r1, [pc, #176] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002ee0: 4313 orrs r3, r2
8002ee2: 604b str r3, [r1, #4]
8002ee4: e01a b.n 8002f1c <HAL_RCC_OscConfig+0x1fc>
}
else
{
/* Disable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
8002ee6: 4b2a ldr r3, [pc, #168] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002ee8: 681b ldr r3, [r3, #0]
8002eea: 4a29 ldr r2, [pc, #164] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002eec: f023 0301 bic.w r3, r3, #1
8002ef0: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8002ef2: f7fd fc13 bl 800071c <HAL_GetTick>
8002ef6: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
8002ef8: e008 b.n 8002f0c <HAL_RCC_OscConfig+0x1ec>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8002efa: f7fd fc0f bl 800071c <HAL_GetTick>
8002efe: 4602 mov r2, r0
8002f00: 693b ldr r3, [r7, #16]
8002f02: 1ad3 subs r3, r2, r3
8002f04: 2b02 cmp r3, #2
8002f06: d901 bls.n 8002f0c <HAL_RCC_OscConfig+0x1ec>
{
return HAL_TIMEOUT;
8002f08: 2303 movs r3, #3
8002f0a: e2dd b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
8002f0c: 4b20 ldr r3, [pc, #128] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002f0e: 681b ldr r3, [r3, #0]
8002f10: f003 0302 and.w r3, r3, #2
8002f14: 2b00 cmp r3, #0
8002f16: d1f0 bne.n 8002efa <HAL_RCC_OscConfig+0x1da>
8002f18: e000 b.n 8002f1c <HAL_RCC_OscConfig+0x1fc>
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8002f1a: bf00 nop
}
}
}
}
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002f1c: 687b ldr r3, [r7, #4]
8002f1e: 681b ldr r3, [r3, #0]
8002f20: f003 0301 and.w r3, r3, #1
8002f24: 2b00 cmp r3, #0
8002f26: d074 beq.n 8003012 <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
8002f28: 69bb ldr r3, [r7, #24]
8002f2a: 2b08 cmp r3, #8
8002f2c: d005 beq.n 8002f3a <HAL_RCC_OscConfig+0x21a>
8002f2e: 69bb ldr r3, [r7, #24]
8002f30: 2b0c cmp r3, #12
8002f32: d10e bne.n 8002f52 <HAL_RCC_OscConfig+0x232>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
8002f34: 697b ldr r3, [r7, #20]
8002f36: 2b03 cmp r3, #3
8002f38: d10b bne.n 8002f52 <HAL_RCC_OscConfig+0x232>
{
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002f3a: 4b15 ldr r3, [pc, #84] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002f3c: 681b ldr r3, [r3, #0]
8002f3e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002f42: 2b00 cmp r3, #0
8002f44: d064 beq.n 8003010 <HAL_RCC_OscConfig+0x2f0>
8002f46: 687b ldr r3, [r7, #4]
8002f48: 685b ldr r3, [r3, #4]
8002f4a: 2b00 cmp r3, #0
8002f4c: d160 bne.n 8003010 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_ERROR;
8002f4e: 2301 movs r3, #1
8002f50: e2ba b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002f52: 687b ldr r3, [r7, #4]
8002f54: 685b ldr r3, [r3, #4]
8002f56: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002f5a: d106 bne.n 8002f6a <HAL_RCC_OscConfig+0x24a>
8002f5c: 4b0c ldr r3, [pc, #48] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002f5e: 681b ldr r3, [r3, #0]
8002f60: 4a0b ldr r2, [pc, #44] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002f62: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002f66: 6013 str r3, [r2, #0]
8002f68: e026 b.n 8002fb8 <HAL_RCC_OscConfig+0x298>
8002f6a: 687b ldr r3, [r7, #4]
8002f6c: 685b ldr r3, [r3, #4]
8002f6e: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8002f72: d115 bne.n 8002fa0 <HAL_RCC_OscConfig+0x280>
8002f74: 4b06 ldr r3, [pc, #24] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002f76: 681b ldr r3, [r3, #0]
8002f78: 4a05 ldr r2, [pc, #20] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002f7a: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8002f7e: 6013 str r3, [r2, #0]
8002f80: 4b03 ldr r3, [pc, #12] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002f82: 681b ldr r3, [r3, #0]
8002f84: 4a02 ldr r2, [pc, #8] @ (8002f90 <HAL_RCC_OscConfig+0x270>)
8002f86: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002f8a: 6013 str r3, [r2, #0]
8002f8c: e014 b.n 8002fb8 <HAL_RCC_OscConfig+0x298>
8002f8e: bf00 nop
8002f90: 40021000 .word 0x40021000
8002f94: 0800814c .word 0x0800814c
8002f98: 20000000 .word 0x20000000
8002f9c: 20000004 .word 0x20000004
8002fa0: 4ba0 ldr r3, [pc, #640] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8002fa2: 681b ldr r3, [r3, #0]
8002fa4: 4a9f ldr r2, [pc, #636] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8002fa6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002faa: 6013 str r3, [r2, #0]
8002fac: 4b9d ldr r3, [pc, #628] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8002fae: 681b ldr r3, [r3, #0]
8002fb0: 4a9c ldr r2, [pc, #624] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8002fb2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8002fb6: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8002fb8: 687b ldr r3, [r7, #4]
8002fba: 685b ldr r3, [r3, #4]
8002fbc: 2b00 cmp r3, #0
8002fbe: d013 beq.n 8002fe8 <HAL_RCC_OscConfig+0x2c8>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002fc0: f7fd fbac bl 800071c <HAL_GetTick>
8002fc4: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8002fc6: e008 b.n 8002fda <HAL_RCC_OscConfig+0x2ba>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002fc8: f7fd fba8 bl 800071c <HAL_GetTick>
8002fcc: 4602 mov r2, r0
8002fce: 693b ldr r3, [r7, #16]
8002fd0: 1ad3 subs r3, r2, r3
8002fd2: 2b64 cmp r3, #100 @ 0x64
8002fd4: d901 bls.n 8002fda <HAL_RCC_OscConfig+0x2ba>
{
return HAL_TIMEOUT;
8002fd6: 2303 movs r3, #3
8002fd8: e276 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8002fda: 4b92 ldr r3, [pc, #584] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8002fdc: 681b ldr r3, [r3, #0]
8002fde: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002fe2: 2b00 cmp r3, #0
8002fe4: d0f0 beq.n 8002fc8 <HAL_RCC_OscConfig+0x2a8>
8002fe6: e014 b.n 8003012 <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002fe8: f7fd fb98 bl 800071c <HAL_GetTick>
8002fec: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8002fee: e008 b.n 8003002 <HAL_RCC_OscConfig+0x2e2>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002ff0: f7fd fb94 bl 800071c <HAL_GetTick>
8002ff4: 4602 mov r2, r0
8002ff6: 693b ldr r3, [r7, #16]
8002ff8: 1ad3 subs r3, r2, r3
8002ffa: 2b64 cmp r3, #100 @ 0x64
8002ffc: d901 bls.n 8003002 <HAL_RCC_OscConfig+0x2e2>
{
return HAL_TIMEOUT;
8002ffe: 2303 movs r3, #3
8003000: e262 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8003002: 4b88 ldr r3, [pc, #544] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003004: 681b ldr r3, [r3, #0]
8003006: f403 3300 and.w r3, r3, #131072 @ 0x20000
800300a: 2b00 cmp r3, #0
800300c: d1f0 bne.n 8002ff0 <HAL_RCC_OscConfig+0x2d0>
800300e: e000 b.n 8003012 <HAL_RCC_OscConfig+0x2f2>
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003010: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8003012: 687b ldr r3, [r7, #4]
8003014: 681b ldr r3, [r3, #0]
8003016: f003 0302 and.w r3, r3, #2
800301a: 2b00 cmp r3, #0
800301c: d060 beq.n 80030e0 <HAL_RCC_OscConfig+0x3c0>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
800301e: 69bb ldr r3, [r7, #24]
8003020: 2b04 cmp r3, #4
8003022: d005 beq.n 8003030 <HAL_RCC_OscConfig+0x310>
8003024: 69bb ldr r3, [r7, #24]
8003026: 2b0c cmp r3, #12
8003028: d119 bne.n 800305e <HAL_RCC_OscConfig+0x33e>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
800302a: 697b ldr r3, [r7, #20]
800302c: 2b02 cmp r3, #2
800302e: d116 bne.n 800305e <HAL_RCC_OscConfig+0x33e>
{
/* When HSI is used as system clock it will not be disabled */
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003030: 4b7c ldr r3, [pc, #496] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003032: 681b ldr r3, [r3, #0]
8003034: f403 6380 and.w r3, r3, #1024 @ 0x400
8003038: 2b00 cmp r3, #0
800303a: d005 beq.n 8003048 <HAL_RCC_OscConfig+0x328>
800303c: 687b ldr r3, [r7, #4]
800303e: 68db ldr r3, [r3, #12]
8003040: 2b00 cmp r3, #0
8003042: d101 bne.n 8003048 <HAL_RCC_OscConfig+0x328>
{
return HAL_ERROR;
8003044: 2301 movs r3, #1
8003046: e23f b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003048: 4b76 ldr r3, [pc, #472] @ (8003224 <HAL_RCC_OscConfig+0x504>)
800304a: 685b ldr r3, [r3, #4]
800304c: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
8003050: 687b ldr r3, [r7, #4]
8003052: 691b ldr r3, [r3, #16]
8003054: 061b lsls r3, r3, #24
8003056: 4973 ldr r1, [pc, #460] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003058: 4313 orrs r3, r2
800305a: 604b str r3, [r1, #4]
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
800305c: e040 b.n 80030e0 <HAL_RCC_OscConfig+0x3c0>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800305e: 687b ldr r3, [r7, #4]
8003060: 68db ldr r3, [r3, #12]
8003062: 2b00 cmp r3, #0
8003064: d023 beq.n 80030ae <HAL_RCC_OscConfig+0x38e>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8003066: 4b6f ldr r3, [pc, #444] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003068: 681b ldr r3, [r3, #0]
800306a: 4a6e ldr r2, [pc, #440] @ (8003224 <HAL_RCC_OscConfig+0x504>)
800306c: f443 7380 orr.w r3, r3, #256 @ 0x100
8003070: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003072: f7fd fb53 bl 800071c <HAL_GetTick>
8003076: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003078: e008 b.n 800308c <HAL_RCC_OscConfig+0x36c>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800307a: f7fd fb4f bl 800071c <HAL_GetTick>
800307e: 4602 mov r2, r0
8003080: 693b ldr r3, [r7, #16]
8003082: 1ad3 subs r3, r2, r3
8003084: 2b02 cmp r3, #2
8003086: d901 bls.n 800308c <HAL_RCC_OscConfig+0x36c>
{
return HAL_TIMEOUT;
8003088: 2303 movs r3, #3
800308a: e21d b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800308c: 4b65 ldr r3, [pc, #404] @ (8003224 <HAL_RCC_OscConfig+0x504>)
800308e: 681b ldr r3, [r3, #0]
8003090: f403 6380 and.w r3, r3, #1024 @ 0x400
8003094: 2b00 cmp r3, #0
8003096: d0f0 beq.n 800307a <HAL_RCC_OscConfig+0x35a>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003098: 4b62 ldr r3, [pc, #392] @ (8003224 <HAL_RCC_OscConfig+0x504>)
800309a: 685b ldr r3, [r3, #4]
800309c: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
80030a0: 687b ldr r3, [r7, #4]
80030a2: 691b ldr r3, [r3, #16]
80030a4: 061b lsls r3, r3, #24
80030a6: 495f ldr r1, [pc, #380] @ (8003224 <HAL_RCC_OscConfig+0x504>)
80030a8: 4313 orrs r3, r2
80030aa: 604b str r3, [r1, #4]
80030ac: e018 b.n 80030e0 <HAL_RCC_OscConfig+0x3c0>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80030ae: 4b5d ldr r3, [pc, #372] @ (8003224 <HAL_RCC_OscConfig+0x504>)
80030b0: 681b ldr r3, [r3, #0]
80030b2: 4a5c ldr r2, [pc, #368] @ (8003224 <HAL_RCC_OscConfig+0x504>)
80030b4: f423 7380 bic.w r3, r3, #256 @ 0x100
80030b8: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80030ba: f7fd fb2f bl 800071c <HAL_GetTick>
80030be: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
80030c0: e008 b.n 80030d4 <HAL_RCC_OscConfig+0x3b4>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80030c2: f7fd fb2b bl 800071c <HAL_GetTick>
80030c6: 4602 mov r2, r0
80030c8: 693b ldr r3, [r7, #16]
80030ca: 1ad3 subs r3, r2, r3
80030cc: 2b02 cmp r3, #2
80030ce: d901 bls.n 80030d4 <HAL_RCC_OscConfig+0x3b4>
{
return HAL_TIMEOUT;
80030d0: 2303 movs r3, #3
80030d2: e1f9 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
80030d4: 4b53 ldr r3, [pc, #332] @ (8003224 <HAL_RCC_OscConfig+0x504>)
80030d6: 681b ldr r3, [r3, #0]
80030d8: f403 6380 and.w r3, r3, #1024 @ 0x400
80030dc: 2b00 cmp r3, #0
80030de: d1f0 bne.n 80030c2 <HAL_RCC_OscConfig+0x3a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80030e0: 687b ldr r3, [r7, #4]
80030e2: 681b ldr r3, [r3, #0]
80030e4: f003 0308 and.w r3, r3, #8
80030e8: 2b00 cmp r3, #0
80030ea: d03c beq.n 8003166 <HAL_RCC_OscConfig+0x446>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80030ec: 687b ldr r3, [r7, #4]
80030ee: 695b ldr r3, [r3, #20]
80030f0: 2b00 cmp r3, #0
80030f2: d01c beq.n 800312e <HAL_RCC_OscConfig+0x40e>
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
}
#endif /* RCC_CSR_LSIPREDIV */
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80030f4: 4b4b ldr r3, [pc, #300] @ (8003224 <HAL_RCC_OscConfig+0x504>)
80030f6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80030fa: 4a4a ldr r2, [pc, #296] @ (8003224 <HAL_RCC_OscConfig+0x504>)
80030fc: f043 0301 orr.w r3, r3, #1
8003100: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003104: f7fd fb0a bl 800071c <HAL_GetTick>
8003108: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
800310a: e008 b.n 800311e <HAL_RCC_OscConfig+0x3fe>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800310c: f7fd fb06 bl 800071c <HAL_GetTick>
8003110: 4602 mov r2, r0
8003112: 693b ldr r3, [r7, #16]
8003114: 1ad3 subs r3, r2, r3
8003116: 2b02 cmp r3, #2
8003118: d901 bls.n 800311e <HAL_RCC_OscConfig+0x3fe>
{
return HAL_TIMEOUT;
800311a: 2303 movs r3, #3
800311c: e1d4 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
800311e: 4b41 ldr r3, [pc, #260] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003120: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8003124: f003 0302 and.w r3, r3, #2
8003128: 2b00 cmp r3, #0
800312a: d0ef beq.n 800310c <HAL_RCC_OscConfig+0x3ec>
800312c: e01b b.n 8003166 <HAL_RCC_OscConfig+0x446>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
800312e: 4b3d ldr r3, [pc, #244] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003130: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8003134: 4a3b ldr r2, [pc, #236] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003136: f023 0301 bic.w r3, r3, #1
800313a: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
800313e: f7fd faed bl 800071c <HAL_GetTick>
8003142: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003144: e008 b.n 8003158 <HAL_RCC_OscConfig+0x438>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8003146: f7fd fae9 bl 800071c <HAL_GetTick>
800314a: 4602 mov r2, r0
800314c: 693b ldr r3, [r7, #16]
800314e: 1ad3 subs r3, r2, r3
8003150: 2b02 cmp r3, #2
8003152: d901 bls.n 8003158 <HAL_RCC_OscConfig+0x438>
{
return HAL_TIMEOUT;
8003154: 2303 movs r3, #3
8003156: e1b7 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003158: 4b32 ldr r3, [pc, #200] @ (8003224 <HAL_RCC_OscConfig+0x504>)
800315a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800315e: f003 0302 and.w r3, r3, #2
8003162: 2b00 cmp r3, #0
8003164: d1ef bne.n 8003146 <HAL_RCC_OscConfig+0x426>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8003166: 687b ldr r3, [r7, #4]
8003168: 681b ldr r3, [r3, #0]
800316a: f003 0304 and.w r3, r3, #4
800316e: 2b00 cmp r3, #0
8003170: f000 80a6 beq.w 80032c0 <HAL_RCC_OscConfig+0x5a0>
{
FlagStatus pwrclkchanged = RESET;
8003174: 2300 movs r3, #0
8003176: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
8003178: 4b2a ldr r3, [pc, #168] @ (8003224 <HAL_RCC_OscConfig+0x504>)
800317a: 6d9b ldr r3, [r3, #88] @ 0x58
800317c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003180: 2b00 cmp r3, #0
8003182: d10d bne.n 80031a0 <HAL_RCC_OscConfig+0x480>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003184: 4b27 ldr r3, [pc, #156] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003186: 6d9b ldr r3, [r3, #88] @ 0x58
8003188: 4a26 ldr r2, [pc, #152] @ (8003224 <HAL_RCC_OscConfig+0x504>)
800318a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800318e: 6593 str r3, [r2, #88] @ 0x58
8003190: 4b24 ldr r3, [pc, #144] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003192: 6d9b ldr r3, [r3, #88] @ 0x58
8003194: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003198: 60bb str r3, [r7, #8]
800319a: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800319c: 2301 movs r3, #1
800319e: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80031a0: 4b21 ldr r3, [pc, #132] @ (8003228 <HAL_RCC_OscConfig+0x508>)
80031a2: 681b ldr r3, [r3, #0]
80031a4: f403 7380 and.w r3, r3, #256 @ 0x100
80031a8: 2b00 cmp r3, #0
80031aa: d118 bne.n 80031de <HAL_RCC_OscConfig+0x4be>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80031ac: 4b1e ldr r3, [pc, #120] @ (8003228 <HAL_RCC_OscConfig+0x508>)
80031ae: 681b ldr r3, [r3, #0]
80031b0: 4a1d ldr r2, [pc, #116] @ (8003228 <HAL_RCC_OscConfig+0x508>)
80031b2: f443 7380 orr.w r3, r3, #256 @ 0x100
80031b6: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80031b8: f7fd fab0 bl 800071c <HAL_GetTick>
80031bc: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80031be: e008 b.n 80031d2 <HAL_RCC_OscConfig+0x4b2>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80031c0: f7fd faac bl 800071c <HAL_GetTick>
80031c4: 4602 mov r2, r0
80031c6: 693b ldr r3, [r7, #16]
80031c8: 1ad3 subs r3, r2, r3
80031ca: 2b02 cmp r3, #2
80031cc: d901 bls.n 80031d2 <HAL_RCC_OscConfig+0x4b2>
{
return HAL_TIMEOUT;
80031ce: 2303 movs r3, #3
80031d0: e17a b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80031d2: 4b15 ldr r3, [pc, #84] @ (8003228 <HAL_RCC_OscConfig+0x508>)
80031d4: 681b ldr r3, [r3, #0]
80031d6: f403 7380 and.w r3, r3, #256 @ 0x100
80031da: 2b00 cmp r3, #0
80031dc: d0f0 beq.n 80031c0 <HAL_RCC_OscConfig+0x4a0>
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
#else
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80031de: 687b ldr r3, [r7, #4]
80031e0: 689b ldr r3, [r3, #8]
80031e2: 2b01 cmp r3, #1
80031e4: d108 bne.n 80031f8 <HAL_RCC_OscConfig+0x4d8>
80031e6: 4b0f ldr r3, [pc, #60] @ (8003224 <HAL_RCC_OscConfig+0x504>)
80031e8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80031ec: 4a0d ldr r2, [pc, #52] @ (8003224 <HAL_RCC_OscConfig+0x504>)
80031ee: f043 0301 orr.w r3, r3, #1
80031f2: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80031f6: e029 b.n 800324c <HAL_RCC_OscConfig+0x52c>
80031f8: 687b ldr r3, [r7, #4]
80031fa: 689b ldr r3, [r3, #8]
80031fc: 2b05 cmp r3, #5
80031fe: d115 bne.n 800322c <HAL_RCC_OscConfig+0x50c>
8003200: 4b08 ldr r3, [pc, #32] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003202: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003206: 4a07 ldr r2, [pc, #28] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003208: f043 0304 orr.w r3, r3, #4
800320c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8003210: 4b04 ldr r3, [pc, #16] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003212: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003216: 4a03 ldr r2, [pc, #12] @ (8003224 <HAL_RCC_OscConfig+0x504>)
8003218: f043 0301 orr.w r3, r3, #1
800321c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8003220: e014 b.n 800324c <HAL_RCC_OscConfig+0x52c>
8003222: bf00 nop
8003224: 40021000 .word 0x40021000
8003228: 40007000 .word 0x40007000
800322c: 4b9c ldr r3, [pc, #624] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
800322e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003232: 4a9b ldr r2, [pc, #620] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003234: f023 0301 bic.w r3, r3, #1
8003238: f8c2 3090 str.w r3, [r2, #144] @ 0x90
800323c: 4b98 ldr r3, [pc, #608] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
800323e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003242: 4a97 ldr r2, [pc, #604] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003244: f023 0304 bic.w r3, r3, #4
8003248: f8c2 3090 str.w r3, [r2, #144] @ 0x90
#endif /* RCC_BDCR_LSESYSDIS */
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
800324c: 687b ldr r3, [r7, #4]
800324e: 689b ldr r3, [r3, #8]
8003250: 2b00 cmp r3, #0
8003252: d016 beq.n 8003282 <HAL_RCC_OscConfig+0x562>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003254: f7fd fa62 bl 800071c <HAL_GetTick>
8003258: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
800325a: e00a b.n 8003272 <HAL_RCC_OscConfig+0x552>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800325c: f7fd fa5e bl 800071c <HAL_GetTick>
8003260: 4602 mov r2, r0
8003262: 693b ldr r3, [r7, #16]
8003264: 1ad3 subs r3, r2, r3
8003266: f241 3288 movw r2, #5000 @ 0x1388
800326a: 4293 cmp r3, r2
800326c: d901 bls.n 8003272 <HAL_RCC_OscConfig+0x552>
{
return HAL_TIMEOUT;
800326e: 2303 movs r3, #3
8003270: e12a b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003272: 4b8b ldr r3, [pc, #556] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003274: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003278: f003 0302 and.w r3, r3, #2
800327c: 2b00 cmp r3, #0
800327e: d0ed beq.n 800325c <HAL_RCC_OscConfig+0x53c>
8003280: e015 b.n 80032ae <HAL_RCC_OscConfig+0x58e>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003282: f7fd fa4b bl 800071c <HAL_GetTick>
8003286: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003288: e00a b.n 80032a0 <HAL_RCC_OscConfig+0x580>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800328a: f7fd fa47 bl 800071c <HAL_GetTick>
800328e: 4602 mov r2, r0
8003290: 693b ldr r3, [r7, #16]
8003292: 1ad3 subs r3, r2, r3
8003294: f241 3288 movw r2, #5000 @ 0x1388
8003298: 4293 cmp r3, r2
800329a: d901 bls.n 80032a0 <HAL_RCC_OscConfig+0x580>
{
return HAL_TIMEOUT;
800329c: 2303 movs r3, #3
800329e: e113 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
80032a0: 4b7f ldr r3, [pc, #508] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80032a2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80032a6: f003 0302 and.w r3, r3, #2
80032aa: 2b00 cmp r3, #0
80032ac: d1ed bne.n 800328a <HAL_RCC_OscConfig+0x56a>
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
80032ae: 7ffb ldrb r3, [r7, #31]
80032b0: 2b01 cmp r3, #1
80032b2: d105 bne.n 80032c0 <HAL_RCC_OscConfig+0x5a0>
{
__HAL_RCC_PWR_CLK_DISABLE();
80032b4: 4b7a ldr r3, [pc, #488] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80032b6: 6d9b ldr r3, [r3, #88] @ 0x58
80032b8: 4a79 ldr r2, [pc, #484] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80032ba: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80032be: 6593 str r3, [r2, #88] @ 0x58
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
80032c0: 687b ldr r3, [r7, #4]
80032c2: 6a9b ldr r3, [r3, #40] @ 0x28
80032c4: 2b00 cmp r3, #0
80032c6: f000 80fe beq.w 80034c6 <HAL_RCC_OscConfig+0x7a6>
{
/* PLL On ? */
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
80032ca: 687b ldr r3, [r7, #4]
80032cc: 6a9b ldr r3, [r3, #40] @ 0x28
80032ce: 2b02 cmp r3, #2
80032d0: f040 80d0 bne.w 8003474 <HAL_RCC_OscConfig+0x754>
#endif /* RCC_PLLP_SUPPORT */
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Do nothing if PLL configuration is the unchanged */
pll_config = RCC->PLLCFGR;
80032d4: 4b72 ldr r3, [pc, #456] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80032d6: 68db ldr r3, [r3, #12]
80032d8: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80032da: 697b ldr r3, [r7, #20]
80032dc: f003 0203 and.w r2, r3, #3
80032e0: 687b ldr r3, [r7, #4]
80032e2: 6adb ldr r3, [r3, #44] @ 0x2c
80032e4: 429a cmp r2, r3
80032e6: d130 bne.n 800334a <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
80032e8: 697b ldr r3, [r7, #20]
80032ea: f003 0270 and.w r2, r3, #112 @ 0x70
80032ee: 687b ldr r3, [r7, #4]
80032f0: 6b1b ldr r3, [r3, #48] @ 0x30
80032f2: 3b01 subs r3, #1
80032f4: 011b lsls r3, r3, #4
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80032f6: 429a cmp r2, r3
80032f8: d127 bne.n 800334a <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80032fa: 697b ldr r3, [r7, #20]
80032fc: f403 42fe and.w r2, r3, #32512 @ 0x7f00
8003300: 687b ldr r3, [r7, #4]
8003302: 6b5b ldr r3, [r3, #52] @ 0x34
8003304: 021b lsls r3, r3, #8
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8003306: 429a cmp r2, r3
8003308: d11f bne.n 800334a <HAL_RCC_OscConfig+0x62a>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
#else
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
800330a: 697b ldr r3, [r7, #20]
800330c: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003310: 687a ldr r2, [r7, #4]
8003312: 6b92 ldr r2, [r2, #56] @ 0x38
8003314: 2a07 cmp r2, #7
8003316: bf14 ite ne
8003318: 2201 movne r2, #1
800331a: 2200 moveq r2, #0
800331c: b2d2 uxtb r2, r2
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
800331e: 4293 cmp r3, r2
8003320: d113 bne.n 800334a <HAL_RCC_OscConfig+0x62a>
#endif
#endif
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8003322: 697b ldr r3, [r7, #20]
8003324: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
8003328: 687b ldr r3, [r7, #4]
800332a: 6bdb ldr r3, [r3, #60] @ 0x3c
800332c: 085b lsrs r3, r3, #1
800332e: 3b01 subs r3, #1
8003330: 055b lsls r3, r3, #21
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
8003332: 429a cmp r2, r3
8003334: d109 bne.n 800334a <HAL_RCC_OscConfig+0x62a>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
8003336: 697b ldr r3, [r7, #20]
8003338: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
800333c: 687b ldr r3, [r7, #4]
800333e: 6c1b ldr r3, [r3, #64] @ 0x40
8003340: 085b lsrs r3, r3, #1
8003342: 3b01 subs r3, #1
8003344: 065b lsls r3, r3, #25
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8003346: 429a cmp r2, r3
8003348: d06e beq.n 8003428 <HAL_RCC_OscConfig+0x708>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
800334a: 69bb ldr r3, [r7, #24]
800334c: 2b0c cmp r3, #12
800334e: d069 beq.n 8003424 <HAL_RCC_OscConfig+0x704>
{
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
/* Check if main PLL can be updated */
/* Not possible if the source is shared by other enabled PLLSAIx */
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
8003350: 4b53 ldr r3, [pc, #332] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003352: 681b ldr r3, [r3, #0]
8003354: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8003358: 2b00 cmp r3, #0
800335a: d105 bne.n 8003368 <HAL_RCC_OscConfig+0x648>
#if defined(RCC_PLLSAI2_SUPPORT)
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
800335c: 4b50 ldr r3, [pc, #320] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
800335e: 681b ldr r3, [r3, #0]
8003360: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003364: 2b00 cmp r3, #0
8003366: d001 beq.n 800336c <HAL_RCC_OscConfig+0x64c>
#endif
)
{
return HAL_ERROR;
8003368: 2301 movs r3, #1
800336a: e0ad b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800336c: 4b4c ldr r3, [pc, #304] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
800336e: 681b ldr r3, [r3, #0]
8003370: 4a4b ldr r2, [pc, #300] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003372: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8003376: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003378: f7fd f9d0 bl 800071c <HAL_GetTick>
800337c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
800337e: e008 b.n 8003392 <HAL_RCC_OscConfig+0x672>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003380: f7fd f9cc bl 800071c <HAL_GetTick>
8003384: 4602 mov r2, r0
8003386: 693b ldr r3, [r7, #16]
8003388: 1ad3 subs r3, r2, r3
800338a: 2b02 cmp r3, #2
800338c: d901 bls.n 8003392 <HAL_RCC_OscConfig+0x672>
{
return HAL_TIMEOUT;
800338e: 2303 movs r3, #3
8003390: e09a b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003392: 4b43 ldr r3, [pc, #268] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003394: 681b ldr r3, [r3, #0]
8003396: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800339a: 2b00 cmp r3, #0
800339c: d1f0 bne.n 8003380 <HAL_RCC_OscConfig+0x660>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
800339e: 4b40 ldr r3, [pc, #256] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80033a0: 68da ldr r2, [r3, #12]
80033a2: 4b40 ldr r3, [pc, #256] @ (80034a4 <HAL_RCC_OscConfig+0x784>)
80033a4: 4013 ands r3, r2
80033a6: 687a ldr r2, [r7, #4]
80033a8: 6ad1 ldr r1, [r2, #44] @ 0x2c
80033aa: 687a ldr r2, [r7, #4]
80033ac: 6b12 ldr r2, [r2, #48] @ 0x30
80033ae: 3a01 subs r2, #1
80033b0: 0112 lsls r2, r2, #4
80033b2: 4311 orrs r1, r2
80033b4: 687a ldr r2, [r7, #4]
80033b6: 6b52 ldr r2, [r2, #52] @ 0x34
80033b8: 0212 lsls r2, r2, #8
80033ba: 4311 orrs r1, r2
80033bc: 687a ldr r2, [r7, #4]
80033be: 6bd2 ldr r2, [r2, #60] @ 0x3c
80033c0: 0852 lsrs r2, r2, #1
80033c2: 3a01 subs r2, #1
80033c4: 0552 lsls r2, r2, #21
80033c6: 4311 orrs r1, r2
80033c8: 687a ldr r2, [r7, #4]
80033ca: 6c12 ldr r2, [r2, #64] @ 0x40
80033cc: 0852 lsrs r2, r2, #1
80033ce: 3a01 subs r2, #1
80033d0: 0652 lsls r2, r2, #25
80033d2: 4311 orrs r1, r2
80033d4: 687a ldr r2, [r7, #4]
80033d6: 6b92 ldr r2, [r2, #56] @ 0x38
80033d8: 0912 lsrs r2, r2, #4
80033da: 0452 lsls r2, r2, #17
80033dc: 430a orrs r2, r1
80033de: 4930 ldr r1, [pc, #192] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80033e0: 4313 orrs r3, r2
80033e2: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80033e4: 4b2e ldr r3, [pc, #184] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80033e6: 681b ldr r3, [r3, #0]
80033e8: 4a2d ldr r2, [pc, #180] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80033ea: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80033ee: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
80033f0: 4b2b ldr r3, [pc, #172] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80033f2: 68db ldr r3, [r3, #12]
80033f4: 4a2a ldr r2, [pc, #168] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
80033f6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80033fa: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80033fc: f7fd f98e bl 800071c <HAL_GetTick>
8003400: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003402: e008 b.n 8003416 <HAL_RCC_OscConfig+0x6f6>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003404: f7fd f98a bl 800071c <HAL_GetTick>
8003408: 4602 mov r2, r0
800340a: 693b ldr r3, [r7, #16]
800340c: 1ad3 subs r3, r2, r3
800340e: 2b02 cmp r3, #2
8003410: d901 bls.n 8003416 <HAL_RCC_OscConfig+0x6f6>
{
return HAL_TIMEOUT;
8003412: 2303 movs r3, #3
8003414: e058 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003416: 4b22 ldr r3, [pc, #136] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003418: 681b ldr r3, [r3, #0]
800341a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800341e: 2b00 cmp r3, #0
8003420: d0f0 beq.n 8003404 <HAL_RCC_OscConfig+0x6e4>
if(sysclk_source != RCC_CFGR_SWS_PLL)
8003422: e050 b.n 80034c6 <HAL_RCC_OscConfig+0x7a6>
}
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
8003424: 2301 movs r3, #1
8003426: e04f b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
else
{
/* PLL configuration is unchanged */
/* Re-enable PLL if it was disabled (ie. low power mode) */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003428: 4b1d ldr r3, [pc, #116] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
800342a: 681b ldr r3, [r3, #0]
800342c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003430: 2b00 cmp r3, #0
8003432: d148 bne.n 80034c6 <HAL_RCC_OscConfig+0x7a6>
{
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8003434: 4b1a ldr r3, [pc, #104] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003436: 681b ldr r3, [r3, #0]
8003438: 4a19 ldr r2, [pc, #100] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
800343a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800343e: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8003440: 4b17 ldr r3, [pc, #92] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003442: 68db ldr r3, [r3, #12]
8003444: 4a16 ldr r2, [pc, #88] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003446: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800344a: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800344c: f7fd f966 bl 800071c <HAL_GetTick>
8003450: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003452: e008 b.n 8003466 <HAL_RCC_OscConfig+0x746>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003454: f7fd f962 bl 800071c <HAL_GetTick>
8003458: 4602 mov r2, r0
800345a: 693b ldr r3, [r7, #16]
800345c: 1ad3 subs r3, r2, r3
800345e: 2b02 cmp r3, #2
8003460: d901 bls.n 8003466 <HAL_RCC_OscConfig+0x746>
{
return HAL_TIMEOUT;
8003462: 2303 movs r3, #3
8003464: e030 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003466: 4b0e ldr r3, [pc, #56] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003468: 681b ldr r3, [r3, #0]
800346a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800346e: 2b00 cmp r3, #0
8003470: d0f0 beq.n 8003454 <HAL_RCC_OscConfig+0x734>
8003472: e028 b.n 80034c6 <HAL_RCC_OscConfig+0x7a6>
}
}
else
{
/* Check that PLL is not used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
8003474: 69bb ldr r3, [r7, #24]
8003476: 2b0c cmp r3, #12
8003478: d023 beq.n 80034c2 <HAL_RCC_OscConfig+0x7a2>
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800347a: 4b09 ldr r3, [pc, #36] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
800347c: 681b ldr r3, [r3, #0]
800347e: 4a08 ldr r2, [pc, #32] @ (80034a0 <HAL_RCC_OscConfig+0x780>)
8003480: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8003484: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003486: f7fd f949 bl 800071c <HAL_GetTick>
800348a: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
800348c: e00c b.n 80034a8 <HAL_RCC_OscConfig+0x788>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800348e: f7fd f945 bl 800071c <HAL_GetTick>
8003492: 4602 mov r2, r0
8003494: 693b ldr r3, [r7, #16]
8003496: 1ad3 subs r3, r2, r3
8003498: 2b02 cmp r3, #2
800349a: d905 bls.n 80034a8 <HAL_RCC_OscConfig+0x788>
{
return HAL_TIMEOUT;
800349c: 2303 movs r3, #3
800349e: e013 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
80034a0: 40021000 .word 0x40021000
80034a4: f99d808c .word 0xf99d808c
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80034a8: 4b09 ldr r3, [pc, #36] @ (80034d0 <HAL_RCC_OscConfig+0x7b0>)
80034aa: 681b ldr r3, [r3, #0]
80034ac: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80034b0: 2b00 cmp r3, #0
80034b2: d1ec bne.n 800348e <HAL_RCC_OscConfig+0x76e>
}
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
80034b4: 4b06 ldr r3, [pc, #24] @ (80034d0 <HAL_RCC_OscConfig+0x7b0>)
80034b6: 68da ldr r2, [r3, #12]
80034b8: 4905 ldr r1, [pc, #20] @ (80034d0 <HAL_RCC_OscConfig+0x7b0>)
80034ba: 4b06 ldr r3, [pc, #24] @ (80034d4 <HAL_RCC_OscConfig+0x7b4>)
80034bc: 4013 ands r3, r2
80034be: 60cb str r3, [r1, #12]
80034c0: e001 b.n 80034c6 <HAL_RCC_OscConfig+0x7a6>
#endif /* RCC_PLLSAI2_SUPPORT */
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
80034c2: 2301 movs r3, #1
80034c4: e000 b.n 80034c8 <HAL_RCC_OscConfig+0x7a8>
}
}
}
return HAL_OK;
80034c6: 2300 movs r3, #0
}
80034c8: 4618 mov r0, r3
80034ca: 3720 adds r7, #32
80034cc: 46bd mov sp, r7
80034ce: bd80 pop {r7, pc}
80034d0: 40021000 .word 0x40021000
80034d4: feeefffc .word 0xfeeefffc
080034d8 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80034d8: b580 push {r7, lr}
80034da: b084 sub sp, #16
80034dc: af00 add r7, sp, #0
80034de: 6078 str r0, [r7, #4]
80034e0: 6039 str r1, [r7, #0]
uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
HAL_StatusTypeDef status;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
80034e2: 687b ldr r3, [r7, #4]
80034e4: 2b00 cmp r3, #0
80034e6: d101 bne.n 80034ec <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80034e8: 2301 movs r3, #1
80034ea: e0e7 b.n 80036bc <HAL_RCC_ClockConfig+0x1e4>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80034ec: 4b75 ldr r3, [pc, #468] @ (80036c4 <HAL_RCC_ClockConfig+0x1ec>)
80034ee: 681b ldr r3, [r3, #0]
80034f0: f003 0307 and.w r3, r3, #7
80034f4: 683a ldr r2, [r7, #0]
80034f6: 429a cmp r2, r3
80034f8: d910 bls.n 800351c <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80034fa: 4b72 ldr r3, [pc, #456] @ (80036c4 <HAL_RCC_ClockConfig+0x1ec>)
80034fc: 681b ldr r3, [r3, #0]
80034fe: f023 0207 bic.w r2, r3, #7
8003502: 4970 ldr r1, [pc, #448] @ (80036c4 <HAL_RCC_ClockConfig+0x1ec>)
8003504: 683b ldr r3, [r7, #0]
8003506: 4313 orrs r3, r2
8003508: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800350a: 4b6e ldr r3, [pc, #440] @ (80036c4 <HAL_RCC_ClockConfig+0x1ec>)
800350c: 681b ldr r3, [r3, #0]
800350e: f003 0307 and.w r3, r3, #7
8003512: 683a ldr r2, [r7, #0]
8003514: 429a cmp r2, r3
8003516: d001 beq.n 800351c <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8003518: 2301 movs r3, #1
800351a: e0cf b.n 80036bc <HAL_RCC_ClockConfig+0x1e4>
}
}
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800351c: 687b ldr r3, [r7, #4]
800351e: 681b ldr r3, [r3, #0]
8003520: f003 0302 and.w r3, r3, #2
8003524: 2b00 cmp r3, #0
8003526: d010 beq.n 800354a <HAL_RCC_ClockConfig+0x72>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
8003528: 687b ldr r3, [r7, #4]
800352a: 689a ldr r2, [r3, #8]
800352c: 4b66 ldr r3, [pc, #408] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
800352e: 689b ldr r3, [r3, #8]
8003530: f003 03f0 and.w r3, r3, #240 @ 0xf0
8003534: 429a cmp r2, r3
8003536: d908 bls.n 800354a <HAL_RCC_ClockConfig+0x72>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003538: 4b63 ldr r3, [pc, #396] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
800353a: 689b ldr r3, [r3, #8]
800353c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8003540: 687b ldr r3, [r7, #4]
8003542: 689b ldr r3, [r3, #8]
8003544: 4960 ldr r1, [pc, #384] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
8003546: 4313 orrs r3, r2
8003548: 608b str r3, [r1, #8]
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800354a: 687b ldr r3, [r7, #4]
800354c: 681b ldr r3, [r3, #0]
800354e: f003 0301 and.w r3, r3, #1
8003552: 2b00 cmp r3, #0
8003554: d04c beq.n 80035f0 <HAL_RCC_ClockConfig+0x118>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8003556: 687b ldr r3, [r7, #4]
8003558: 685b ldr r3, [r3, #4]
800355a: 2b03 cmp r3, #3
800355c: d107 bne.n 800356e <HAL_RCC_ClockConfig+0x96>
{
/* Check the PLL ready flag */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800355e: 4b5a ldr r3, [pc, #360] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
8003560: 681b ldr r3, [r3, #0]
8003562: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003566: 2b00 cmp r3, #0
8003568: d121 bne.n 80035ae <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800356a: 2301 movs r3, #1
800356c: e0a6 b.n 80036bc <HAL_RCC_ClockConfig+0x1e4>
#endif
}
else
{
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800356e: 687b ldr r3, [r7, #4]
8003570: 685b ldr r3, [r3, #4]
8003572: 2b02 cmp r3, #2
8003574: d107 bne.n 8003586 <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8003576: 4b54 ldr r3, [pc, #336] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
8003578: 681b ldr r3, [r3, #0]
800357a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800357e: 2b00 cmp r3, #0
8003580: d115 bne.n 80035ae <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
8003582: 2301 movs r3, #1
8003584: e09a b.n 80036bc <HAL_RCC_ClockConfig+0x1e4>
}
}
/* MSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
8003586: 687b ldr r3, [r7, #4]
8003588: 685b ldr r3, [r3, #4]
800358a: 2b00 cmp r3, #0
800358c: d107 bne.n 800359e <HAL_RCC_ClockConfig+0xc6>
{
/* Check the MSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
800358e: 4b4e ldr r3, [pc, #312] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
8003590: 681b ldr r3, [r3, #0]
8003592: f003 0302 and.w r3, r3, #2
8003596: 2b00 cmp r3, #0
8003598: d109 bne.n 80035ae <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800359a: 2301 movs r3, #1
800359c: e08e b.n 80036bc <HAL_RCC_ClockConfig+0x1e4>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800359e: 4b4a ldr r3, [pc, #296] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
80035a0: 681b ldr r3, [r3, #0]
80035a2: f403 6380 and.w r3, r3, #1024 @ 0x400
80035a6: 2b00 cmp r3, #0
80035a8: d101 bne.n 80035ae <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
80035aa: 2301 movs r3, #1
80035ac: e086 b.n 80036bc <HAL_RCC_ClockConfig+0x1e4>
}
#endif
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
80035ae: 4b46 ldr r3, [pc, #280] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
80035b0: 689b ldr r3, [r3, #8]
80035b2: f023 0203 bic.w r2, r3, #3
80035b6: 687b ldr r3, [r7, #4]
80035b8: 685b ldr r3, [r3, #4]
80035ba: 4943 ldr r1, [pc, #268] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
80035bc: 4313 orrs r3, r2
80035be: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80035c0: f7fd f8ac bl 800071c <HAL_GetTick>
80035c4: 60f8 str r0, [r7, #12]
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80035c6: e00a b.n 80035de <HAL_RCC_ClockConfig+0x106>
{
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80035c8: f7fd f8a8 bl 800071c <HAL_GetTick>
80035cc: 4602 mov r2, r0
80035ce: 68fb ldr r3, [r7, #12]
80035d0: 1ad3 subs r3, r2, r3
80035d2: f241 3288 movw r2, #5000 @ 0x1388
80035d6: 4293 cmp r3, r2
80035d8: d901 bls.n 80035de <HAL_RCC_ClockConfig+0x106>
{
return HAL_TIMEOUT;
80035da: 2303 movs r3, #3
80035dc: e06e b.n 80036bc <HAL_RCC_ClockConfig+0x1e4>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80035de: 4b3a ldr r3, [pc, #232] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
80035e0: 689b ldr r3, [r3, #8]
80035e2: f003 020c and.w r2, r3, #12
80035e6: 687b ldr r3, [r7, #4]
80035e8: 685b ldr r3, [r3, #4]
80035ea: 009b lsls r3, r3, #2
80035ec: 429a cmp r2, r3
80035ee: d1eb bne.n 80035c8 <HAL_RCC_ClockConfig+0xf0>
}
#endif
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80035f0: 687b ldr r3, [r7, #4]
80035f2: 681b ldr r3, [r3, #0]
80035f4: f003 0302 and.w r3, r3, #2
80035f8: 2b00 cmp r3, #0
80035fa: d010 beq.n 800361e <HAL_RCC_ClockConfig+0x146>
{
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
80035fc: 687b ldr r3, [r7, #4]
80035fe: 689a ldr r2, [r3, #8]
8003600: 4b31 ldr r3, [pc, #196] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
8003602: 689b ldr r3, [r3, #8]
8003604: f003 03f0 and.w r3, r3, #240 @ 0xf0
8003608: 429a cmp r2, r3
800360a: d208 bcs.n 800361e <HAL_RCC_ClockConfig+0x146>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
800360c: 4b2e ldr r3, [pc, #184] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
800360e: 689b ldr r3, [r3, #8]
8003610: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8003614: 687b ldr r3, [r7, #4]
8003616: 689b ldr r3, [r3, #8]
8003618: 492b ldr r1, [pc, #172] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
800361a: 4313 orrs r3, r2
800361c: 608b str r3, [r1, #8]
}
}
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
if(FLatency < __HAL_FLASH_GET_LATENCY())
800361e: 4b29 ldr r3, [pc, #164] @ (80036c4 <HAL_RCC_ClockConfig+0x1ec>)
8003620: 681b ldr r3, [r3, #0]
8003622: f003 0307 and.w r3, r3, #7
8003626: 683a ldr r2, [r7, #0]
8003628: 429a cmp r2, r3
800362a: d210 bcs.n 800364e <HAL_RCC_ClockConfig+0x176>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800362c: 4b25 ldr r3, [pc, #148] @ (80036c4 <HAL_RCC_ClockConfig+0x1ec>)
800362e: 681b ldr r3, [r3, #0]
8003630: f023 0207 bic.w r2, r3, #7
8003634: 4923 ldr r1, [pc, #140] @ (80036c4 <HAL_RCC_ClockConfig+0x1ec>)
8003636: 683b ldr r3, [r7, #0]
8003638: 4313 orrs r3, r2
800363a: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800363c: 4b21 ldr r3, [pc, #132] @ (80036c4 <HAL_RCC_ClockConfig+0x1ec>)
800363e: 681b ldr r3, [r3, #0]
8003640: f003 0307 and.w r3, r3, #7
8003644: 683a ldr r2, [r7, #0]
8003646: 429a cmp r2, r3
8003648: d001 beq.n 800364e <HAL_RCC_ClockConfig+0x176>
{
return HAL_ERROR;
800364a: 2301 movs r3, #1
800364c: e036 b.n 80036bc <HAL_RCC_ClockConfig+0x1e4>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800364e: 687b ldr r3, [r7, #4]
8003650: 681b ldr r3, [r3, #0]
8003652: f003 0304 and.w r3, r3, #4
8003656: 2b00 cmp r3, #0
8003658: d008 beq.n 800366c <HAL_RCC_ClockConfig+0x194>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
800365a: 4b1b ldr r3, [pc, #108] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
800365c: 689b ldr r3, [r3, #8]
800365e: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8003662: 687b ldr r3, [r7, #4]
8003664: 68db ldr r3, [r3, #12]
8003666: 4918 ldr r1, [pc, #96] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
8003668: 4313 orrs r3, r2
800366a: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800366c: 687b ldr r3, [r7, #4]
800366e: 681b ldr r3, [r3, #0]
8003670: f003 0308 and.w r3, r3, #8
8003674: 2b00 cmp r3, #0
8003676: d009 beq.n 800368c <HAL_RCC_ClockConfig+0x1b4>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8003678: 4b13 ldr r3, [pc, #76] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
800367a: 689b ldr r3, [r3, #8]
800367c: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8003680: 687b ldr r3, [r7, #4]
8003682: 691b ldr r3, [r3, #16]
8003684: 00db lsls r3, r3, #3
8003686: 4910 ldr r1, [pc, #64] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
8003688: 4313 orrs r3, r2
800368a: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
800368c: f000 f824 bl 80036d8 <HAL_RCC_GetSysClockFreq>
8003690: 4602 mov r2, r0
8003692: 4b0d ldr r3, [pc, #52] @ (80036c8 <HAL_RCC_ClockConfig+0x1f0>)
8003694: 689b ldr r3, [r3, #8]
8003696: 091b lsrs r3, r3, #4
8003698: f003 030f and.w r3, r3, #15
800369c: 490b ldr r1, [pc, #44] @ (80036cc <HAL_RCC_ClockConfig+0x1f4>)
800369e: 5ccb ldrb r3, [r1, r3]
80036a0: f003 031f and.w r3, r3, #31
80036a4: fa22 f303 lsr.w r3, r2, r3
80036a8: 4a09 ldr r2, [pc, #36] @ (80036d0 <HAL_RCC_ClockConfig+0x1f8>)
80036aa: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
80036ac: 4b09 ldr r3, [pc, #36] @ (80036d4 <HAL_RCC_ClockConfig+0x1fc>)
80036ae: 681b ldr r3, [r3, #0]
80036b0: 4618 mov r0, r3
80036b2: f7fc ffe3 bl 800067c <HAL_InitTick>
80036b6: 4603 mov r3, r0
80036b8: 72fb strb r3, [r7, #11]
return status;
80036ba: 7afb ldrb r3, [r7, #11]
}
80036bc: 4618 mov r0, r3
80036be: 3710 adds r7, #16
80036c0: 46bd mov sp, r7
80036c2: bd80 pop {r7, pc}
80036c4: 40022000 .word 0x40022000
80036c8: 40021000 .word 0x40021000
80036cc: 0800814c .word 0x0800814c
80036d0: 20000000 .word 0x20000000
80036d4: 20000004 .word 0x20000004
080036d8 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80036d8: b480 push {r7}
80036da: b089 sub sp, #36 @ 0x24
80036dc: af00 add r7, sp, #0
uint32_t msirange = 0U, sysclockfreq = 0U;
80036de: 2300 movs r3, #0
80036e0: 61fb str r3, [r7, #28]
80036e2: 2300 movs r3, #0
80036e4: 61bb str r3, [r7, #24]
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
uint32_t sysclk_source, pll_oscsource;
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
80036e6: 4b3e ldr r3, [pc, #248] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
80036e8: 689b ldr r3, [r3, #8]
80036ea: f003 030c and.w r3, r3, #12
80036ee: 613b str r3, [r7, #16]
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
80036f0: 4b3b ldr r3, [pc, #236] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
80036f2: 68db ldr r3, [r3, #12]
80036f4: f003 0303 and.w r3, r3, #3
80036f8: 60fb str r3, [r7, #12]
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
80036fa: 693b ldr r3, [r7, #16]
80036fc: 2b00 cmp r3, #0
80036fe: d005 beq.n 800370c <HAL_RCC_GetSysClockFreq+0x34>
8003700: 693b ldr r3, [r7, #16]
8003702: 2b0c cmp r3, #12
8003704: d121 bne.n 800374a <HAL_RCC_GetSysClockFreq+0x72>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
8003706: 68fb ldr r3, [r7, #12]
8003708: 2b01 cmp r3, #1
800370a: d11e bne.n 800374a <HAL_RCC_GetSysClockFreq+0x72>
{
/* MSI or PLL with MSI source used as system clock source */
/* Get SYSCLK source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
800370c: 4b34 ldr r3, [pc, #208] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
800370e: 681b ldr r3, [r3, #0]
8003710: f003 0308 and.w r3, r3, #8
8003714: 2b00 cmp r3, #0
8003716: d107 bne.n 8003728 <HAL_RCC_GetSysClockFreq+0x50>
{ /* MSISRANGE from RCC_CSR applies */
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
8003718: 4b31 ldr r3, [pc, #196] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
800371a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800371e: 0a1b lsrs r3, r3, #8
8003720: f003 030f and.w r3, r3, #15
8003724: 61fb str r3, [r7, #28]
8003726: e005 b.n 8003734 <HAL_RCC_GetSysClockFreq+0x5c>
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
8003728: 4b2d ldr r3, [pc, #180] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
800372a: 681b ldr r3, [r3, #0]
800372c: 091b lsrs r3, r3, #4
800372e: f003 030f and.w r3, r3, #15
8003732: 61fb str r3, [r7, #28]
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
8003734: 4a2b ldr r2, [pc, #172] @ (80037e4 <HAL_RCC_GetSysClockFreq+0x10c>)
8003736: 69fb ldr r3, [r7, #28]
8003738: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800373c: 61fb str r3, [r7, #28]
if(sysclk_source == RCC_CFGR_SWS_MSI)
800373e: 693b ldr r3, [r7, #16]
8003740: 2b00 cmp r3, #0
8003742: d10d bne.n 8003760 <HAL_RCC_GetSysClockFreq+0x88>
{
/* MSI used as system clock source */
sysclockfreq = msirange;
8003744: 69fb ldr r3, [r7, #28]
8003746: 61bb str r3, [r7, #24]
if(sysclk_source == RCC_CFGR_SWS_MSI)
8003748: e00a b.n 8003760 <HAL_RCC_GetSysClockFreq+0x88>
}
}
else if(sysclk_source == RCC_CFGR_SWS_HSI)
800374a: 693b ldr r3, [r7, #16]
800374c: 2b04 cmp r3, #4
800374e: d102 bne.n 8003756 <HAL_RCC_GetSysClockFreq+0x7e>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
8003750: 4b25 ldr r3, [pc, #148] @ (80037e8 <HAL_RCC_GetSysClockFreq+0x110>)
8003752: 61bb str r3, [r7, #24]
8003754: e004 b.n 8003760 <HAL_RCC_GetSysClockFreq+0x88>
}
else if(sysclk_source == RCC_CFGR_SWS_HSE)
8003756: 693b ldr r3, [r7, #16]
8003758: 2b08 cmp r3, #8
800375a: d101 bne.n 8003760 <HAL_RCC_GetSysClockFreq+0x88>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
800375c: 4b23 ldr r3, [pc, #140] @ (80037ec <HAL_RCC_GetSysClockFreq+0x114>)
800375e: 61bb str r3, [r7, #24]
else
{
/* unexpected case: sysclockfreq at 0 */
}
if(sysclk_source == RCC_CFGR_SWS_PLL)
8003760: 693b ldr r3, [r7, #16]
8003762: 2b0c cmp r3, #12
8003764: d134 bne.n 80037d0 <HAL_RCC_GetSysClockFreq+0xf8>
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8003766: 4b1e ldr r3, [pc, #120] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
8003768: 68db ldr r3, [r3, #12]
800376a: f003 0303 and.w r3, r3, #3
800376e: 60bb str r3, [r7, #8]
switch (pllsource)
8003770: 68bb ldr r3, [r7, #8]
8003772: 2b02 cmp r3, #2
8003774: d003 beq.n 800377e <HAL_RCC_GetSysClockFreq+0xa6>
8003776: 68bb ldr r3, [r7, #8]
8003778: 2b03 cmp r3, #3
800377a: d003 beq.n 8003784 <HAL_RCC_GetSysClockFreq+0xac>
800377c: e005 b.n 800378a <HAL_RCC_GetSysClockFreq+0xb2>
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllvco = HSI_VALUE;
800377e: 4b1a ldr r3, [pc, #104] @ (80037e8 <HAL_RCC_GetSysClockFreq+0x110>)
8003780: 617b str r3, [r7, #20]
break;
8003782: e005 b.n 8003790 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = HSE_VALUE;
8003784: 4b19 ldr r3, [pc, #100] @ (80037ec <HAL_RCC_GetSysClockFreq+0x114>)
8003786: 617b str r3, [r7, #20]
break;
8003788: e002 b.n 8003790 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default:
pllvco = msirange;
800378a: 69fb ldr r3, [r7, #28]
800378c: 617b str r3, [r7, #20]
break;
800378e: bf00 nop
}
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8003790: 4b13 ldr r3, [pc, #76] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
8003792: 68db ldr r3, [r3, #12]
8003794: 091b lsrs r3, r3, #4
8003796: f003 0307 and.w r3, r3, #7
800379a: 3301 adds r3, #1
800379c: 607b str r3, [r7, #4]
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
800379e: 4b10 ldr r3, [pc, #64] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
80037a0: 68db ldr r3, [r3, #12]
80037a2: 0a1b lsrs r3, r3, #8
80037a4: f003 037f and.w r3, r3, #127 @ 0x7f
80037a8: 697a ldr r2, [r7, #20]
80037aa: fb03 f202 mul.w r2, r3, r2
80037ae: 687b ldr r3, [r7, #4]
80037b0: fbb2 f3f3 udiv r3, r2, r3
80037b4: 617b str r3, [r7, #20]
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
80037b6: 4b0a ldr r3, [pc, #40] @ (80037e0 <HAL_RCC_GetSysClockFreq+0x108>)
80037b8: 68db ldr r3, [r3, #12]
80037ba: 0e5b lsrs r3, r3, #25
80037bc: f003 0303 and.w r3, r3, #3
80037c0: 3301 adds r3, #1
80037c2: 005b lsls r3, r3, #1
80037c4: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllr;
80037c6: 697a ldr r2, [r7, #20]
80037c8: 683b ldr r3, [r7, #0]
80037ca: fbb2 f3f3 udiv r3, r2, r3
80037ce: 61bb str r3, [r7, #24]
}
return sysclockfreq;
80037d0: 69bb ldr r3, [r7, #24]
}
80037d2: 4618 mov r0, r3
80037d4: 3724 adds r7, #36 @ 0x24
80037d6: 46bd mov sp, r7
80037d8: f85d 7b04 ldr.w r7, [sp], #4
80037dc: 4770 bx lr
80037de: bf00 nop
80037e0: 40021000 .word 0x40021000
80037e4: 0800815c .word 0x0800815c
80037e8: 00f42400 .word 0x00f42400
80037ec: 007a1200 .word 0x007a1200
080037f0 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80037f0: b480 push {r7}
80037f2: af00 add r7, sp, #0
return SystemCoreClock;
80037f4: 4b03 ldr r3, [pc, #12] @ (8003804 <HAL_RCC_GetHCLKFreq+0x14>)
80037f6: 681b ldr r3, [r3, #0]
}
80037f8: 4618 mov r0, r3
80037fa: 46bd mov sp, r7
80037fc: f85d 7b04 ldr.w r7, [sp], #4
8003800: 4770 bx lr
8003802: bf00 nop
8003804: 20000000 .word 0x20000000
08003808 <RCC_SetFlashLatencyFromMSIRange>:
voltage range.
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
8003808: b580 push {r7, lr}
800380a: b086 sub sp, #24
800380c: af00 add r7, sp, #0
800380e: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
8003810: 2300 movs r3, #0
8003812: 613b str r3, [r7, #16]
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
8003814: 4b2a ldr r3, [pc, #168] @ (80038c0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8003816: 6d9b ldr r3, [r3, #88] @ 0x58
8003818: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800381c: 2b00 cmp r3, #0
800381e: d003 beq.n 8003828 <RCC_SetFlashLatencyFromMSIRange+0x20>
{
vos = HAL_PWREx_GetVoltageRange();
8003820: f7ff fa0a bl 8002c38 <HAL_PWREx_GetVoltageRange>
8003824: 6178 str r0, [r7, #20]
8003826: e014 b.n 8003852 <RCC_SetFlashLatencyFromMSIRange+0x4a>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
8003828: 4b25 ldr r3, [pc, #148] @ (80038c0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800382a: 6d9b ldr r3, [r3, #88] @ 0x58
800382c: 4a24 ldr r2, [pc, #144] @ (80038c0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800382e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003832: 6593 str r3, [r2, #88] @ 0x58
8003834: 4b22 ldr r3, [pc, #136] @ (80038c0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8003836: 6d9b ldr r3, [r3, #88] @ 0x58
8003838: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800383c: 60fb str r3, [r7, #12]
800383e: 68fb ldr r3, [r7, #12]
vos = HAL_PWREx_GetVoltageRange();
8003840: f7ff f9fa bl 8002c38 <HAL_PWREx_GetVoltageRange>
8003844: 6178 str r0, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
8003846: 4b1e ldr r3, [pc, #120] @ (80038c0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8003848: 6d9b ldr r3, [r3, #88] @ 0x58
800384a: 4a1d ldr r2, [pc, #116] @ (80038c0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800384c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8003850: 6593 str r3, [r2, #88] @ 0x58
}
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
8003852: 697b ldr r3, [r7, #20]
8003854: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003858: d10b bne.n 8003872 <RCC_SetFlashLatencyFromMSIRange+0x6a>
{
if(msirange > RCC_MSIRANGE_8)
800385a: 687b ldr r3, [r7, #4]
800385c: 2b80 cmp r3, #128 @ 0x80
800385e: d919 bls.n 8003894 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI > 16Mhz */
if(msirange > RCC_MSIRANGE_10)
8003860: 687b ldr r3, [r7, #4]
8003862: 2ba0 cmp r3, #160 @ 0xa0
8003864: d902 bls.n 800386c <RCC_SetFlashLatencyFromMSIRange+0x64>
{
/* MSI 48Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
8003866: 2302 movs r3, #2
8003868: 613b str r3, [r7, #16]
800386a: e013 b.n 8003894 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
/* MSI 24Mhz or 32Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
800386c: 2301 movs r3, #1
800386e: 613b str r3, [r7, #16]
8003870: e010 b.n 8003894 <RCC_SetFlashLatencyFromMSIRange+0x8c>
latency = FLASH_LATENCY_1; /* 1WS */
}
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
}
#else
if(msirange > RCC_MSIRANGE_8)
8003872: 687b ldr r3, [r7, #4]
8003874: 2b80 cmp r3, #128 @ 0x80
8003876: d902 bls.n 800387e <RCC_SetFlashLatencyFromMSIRange+0x76>
{
/* MSI > 16Mhz */
latency = FLASH_LATENCY_3; /* 3WS */
8003878: 2303 movs r3, #3
800387a: 613b str r3, [r7, #16]
800387c: e00a b.n 8003894 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
if(msirange == RCC_MSIRANGE_8)
800387e: 687b ldr r3, [r7, #4]
8003880: 2b80 cmp r3, #128 @ 0x80
8003882: d102 bne.n 800388a <RCC_SetFlashLatencyFromMSIRange+0x82>
{
/* MSI 16Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
8003884: 2302 movs r3, #2
8003886: 613b str r3, [r7, #16]
8003888: e004 b.n 8003894 <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else if(msirange == RCC_MSIRANGE_7)
800388a: 687b ldr r3, [r7, #4]
800388c: 2b70 cmp r3, #112 @ 0x70
800388e: d101 bne.n 8003894 <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
8003890: 2301 movs r3, #1
8003892: 613b str r3, [r7, #16]
}
}
#endif
}
__HAL_FLASH_SET_LATENCY(latency);
8003894: 4b0b ldr r3, [pc, #44] @ (80038c4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8003896: 681b ldr r3, [r3, #0]
8003898: f023 0207 bic.w r2, r3, #7
800389c: 4909 ldr r1, [pc, #36] @ (80038c4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
800389e: 693b ldr r3, [r7, #16]
80038a0: 4313 orrs r3, r2
80038a2: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
80038a4: 4b07 ldr r3, [pc, #28] @ (80038c4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80038a6: 681b ldr r3, [r3, #0]
80038a8: f003 0307 and.w r3, r3, #7
80038ac: 693a ldr r2, [r7, #16]
80038ae: 429a cmp r2, r3
80038b0: d001 beq.n 80038b6 <RCC_SetFlashLatencyFromMSIRange+0xae>
{
return HAL_ERROR;
80038b2: 2301 movs r3, #1
80038b4: e000 b.n 80038b8 <RCC_SetFlashLatencyFromMSIRange+0xb0>
}
return HAL_OK;
80038b6: 2300 movs r3, #0
}
80038b8: 4618 mov r0, r3
80038ba: 3718 adds r7, #24
80038bc: 46bd mov sp, r7
80038be: bd80 pop {r7, pc}
80038c0: 40021000 .word 0x40021000
80038c4: 40022000 .word 0x40022000
080038c8 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
80038c8: b580 push {r7, lr}
80038ca: b086 sub sp, #24
80038cc: af00 add r7, sp, #0
80038ce: 6078 str r0, [r7, #4]
uint32_t tmpregister, tickstart; /* no init needed */
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
80038d0: 2300 movs r3, #0
80038d2: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
80038d4: 2300 movs r3, #0
80038d6: 74bb strb r3, [r7, #18]
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
80038d8: 687b ldr r3, [r7, #4]
80038da: 681b ldr r3, [r3, #0]
80038dc: f403 6300 and.w r3, r3, #2048 @ 0x800
80038e0: 2b00 cmp r3, #0
80038e2: d041 beq.n 8003968 <HAL_RCCEx_PeriphCLKConfig+0xa0>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
switch(PeriphClkInit->Sai1ClockSelection)
80038e4: 687b ldr r3, [r7, #4]
80038e6: 6e5b ldr r3, [r3, #100] @ 0x64
80038e8: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
80038ec: d02a beq.n 8003944 <HAL_RCCEx_PeriphCLKConfig+0x7c>
80038ee: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
80038f2: d824 bhi.n 800393e <HAL_RCCEx_PeriphCLKConfig+0x76>
80038f4: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
80038f8: d008 beq.n 800390c <HAL_RCCEx_PeriphCLKConfig+0x44>
80038fa: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
80038fe: d81e bhi.n 800393e <HAL_RCCEx_PeriphCLKConfig+0x76>
8003900: 2b00 cmp r3, #0
8003902: d00a beq.n 800391a <HAL_RCCEx_PeriphCLKConfig+0x52>
8003904: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8003908: d010 beq.n 800392c <HAL_RCCEx_PeriphCLKConfig+0x64>
800390a: e018 b.n 800393e <HAL_RCCEx_PeriphCLKConfig+0x76>
{
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
/* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
800390c: 4b86 ldr r3, [pc, #536] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
800390e: 68db ldr r3, [r3, #12]
8003910: 4a85 ldr r2, [pc, #532] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003912: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003916: 60d3 str r3, [r2, #12]
#else
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
/* SAI1 clock source config set later after clock selection check */
break;
8003918: e015 b.n 8003946 <HAL_RCCEx_PeriphCLKConfig+0x7e>
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
800391a: 687b ldr r3, [r7, #4]
800391c: 3304 adds r3, #4
800391e: 2100 movs r1, #0
8003920: 4618 mov r0, r3
8003922: f000 fabb bl 8003e9c <RCCEx_PLLSAI1_Config>
8003926: 4603 mov r3, r0
8003928: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
800392a: e00c b.n 8003946 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#if defined(RCC_PLLSAI2_SUPPORT)
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
800392c: 687b ldr r3, [r7, #4]
800392e: 3320 adds r3, #32
8003930: 2100 movs r1, #0
8003932: 4618 mov r0, r3
8003934: f000 fba6 bl 8004084 <RCCEx_PLLSAI2_Config>
8003938: 4603 mov r3, r0
800393a: 74fb strb r3, [r7, #19]
/* SAI1 clock source config set later after clock selection check */
break;
800393c: e003 b.n 8003946 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI1 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
800393e: 2301 movs r3, #1
8003940: 74fb strb r3, [r7, #19]
break;
8003942: e000 b.n 8003946 <HAL_RCCEx_PeriphCLKConfig+0x7e>
break;
8003944: bf00 nop
}
if(ret == HAL_OK)
8003946: 7cfb ldrb r3, [r7, #19]
8003948: 2b00 cmp r3, #0
800394a: d10b bne.n 8003964 <HAL_RCCEx_PeriphCLKConfig+0x9c>
{
/* Set the source of SAI1 clock*/
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
800394c: 4b76 ldr r3, [pc, #472] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
800394e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003952: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8003956: 687b ldr r3, [r7, #4]
8003958: 6e5b ldr r3, [r3, #100] @ 0x64
800395a: 4973 ldr r1, [pc, #460] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
800395c: 4313 orrs r3, r2
800395e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
8003962: e001 b.n 8003968 <HAL_RCCEx_PeriphCLKConfig+0xa0>
}
else
{
/* set overall return value */
status = ret;
8003964: 7cfb ldrb r3, [r7, #19]
8003966: 74bb strb r3, [r7, #18]
#endif /* SAI1 */
#if defined(SAI2)
/*-------------------------- SAI2 clock source configuration ---------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
8003968: 687b ldr r3, [r7, #4]
800396a: 681b ldr r3, [r3, #0]
800396c: f403 5380 and.w r3, r3, #4096 @ 0x1000
8003970: 2b00 cmp r3, #0
8003972: d041 beq.n 80039f8 <HAL_RCCEx_PeriphCLKConfig+0x130>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
switch(PeriphClkInit->Sai2ClockSelection)
8003974: 687b ldr r3, [r7, #4]
8003976: 6e9b ldr r3, [r3, #104] @ 0x68
8003978: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
800397c: d02a beq.n 80039d4 <HAL_RCCEx_PeriphCLKConfig+0x10c>
800397e: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
8003982: d824 bhi.n 80039ce <HAL_RCCEx_PeriphCLKConfig+0x106>
8003984: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8003988: d008 beq.n 800399c <HAL_RCCEx_PeriphCLKConfig+0xd4>
800398a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
800398e: d81e bhi.n 80039ce <HAL_RCCEx_PeriphCLKConfig+0x106>
8003990: 2b00 cmp r3, #0
8003992: d00a beq.n 80039aa <HAL_RCCEx_PeriphCLKConfig+0xe2>
8003994: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8003998: d010 beq.n 80039bc <HAL_RCCEx_PeriphCLKConfig+0xf4>
800399a: e018 b.n 80039ce <HAL_RCCEx_PeriphCLKConfig+0x106>
{
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
/* Enable SAI Clock output generated from System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
800399c: 4b62 ldr r3, [pc, #392] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
800399e: 68db ldr r3, [r3, #12]
80039a0: 4a61 ldr r2, [pc, #388] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
80039a2: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80039a6: 60d3 str r3, [r2, #12]
/* SAI2 clock source config set later after clock selection check */
break;
80039a8: e015 b.n 80039d6 <HAL_RCCEx_PeriphCLKConfig+0x10e>
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
80039aa: 687b ldr r3, [r7, #4]
80039ac: 3304 adds r3, #4
80039ae: 2100 movs r1, #0
80039b0: 4618 mov r0, r3
80039b2: f000 fa73 bl 8003e9c <RCCEx_PLLSAI1_Config>
80039b6: 4603 mov r3, r0
80039b8: 74fb strb r3, [r7, #19]
/* SAI2 clock source config set later after clock selection check */
break;
80039ba: e00c b.n 80039d6 <HAL_RCCEx_PeriphCLKConfig+0x10e>
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
80039bc: 687b ldr r3, [r7, #4]
80039be: 3320 adds r3, #32
80039c0: 2100 movs r1, #0
80039c2: 4618 mov r0, r3
80039c4: f000 fb5e bl 8004084 <RCCEx_PLLSAI2_Config>
80039c8: 4603 mov r3, r0
80039ca: 74fb strb r3, [r7, #19]
/* SAI2 clock source config set later after clock selection check */
break;
80039cc: e003 b.n 80039d6 <HAL_RCCEx_PeriphCLKConfig+0x10e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* SAI2 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
80039ce: 2301 movs r3, #1
80039d0: 74fb strb r3, [r7, #19]
break;
80039d2: e000 b.n 80039d6 <HAL_RCCEx_PeriphCLKConfig+0x10e>
break;
80039d4: bf00 nop
}
if(ret == HAL_OK)
80039d6: 7cfb ldrb r3, [r7, #19]
80039d8: 2b00 cmp r3, #0
80039da: d10b bne.n 80039f4 <HAL_RCCEx_PeriphCLKConfig+0x12c>
{
/* Set the source of SAI2 clock*/
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
80039dc: 4b52 ldr r3, [pc, #328] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
80039de: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80039e2: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
80039e6: 687b ldr r3, [r7, #4]
80039e8: 6e9b ldr r3, [r3, #104] @ 0x68
80039ea: 494f ldr r1, [pc, #316] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
80039ec: 4313 orrs r3, r2
80039ee: f8c1 3088 str.w r3, [r1, #136] @ 0x88
80039f2: e001 b.n 80039f8 <HAL_RCCEx_PeriphCLKConfig+0x130>
}
else
{
/* set overall return value */
status = ret;
80039f4: 7cfb ldrb r3, [r7, #19]
80039f6: 74bb strb r3, [r7, #18]
}
}
#endif /* SAI2 */
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
80039f8: 687b ldr r3, [r7, #4]
80039fa: 681b ldr r3, [r3, #0]
80039fc: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003a00: 2b00 cmp r3, #0
8003a02: f000 80a0 beq.w 8003b46 <HAL_RCCEx_PeriphCLKConfig+0x27e>
{
FlagStatus pwrclkchanged = RESET;
8003a06: 2300 movs r3, #0
8003a08: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8003a0a: 4b47 ldr r3, [pc, #284] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003a0c: 6d9b ldr r3, [r3, #88] @ 0x58
8003a0e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003a12: 2b00 cmp r3, #0
8003a14: d101 bne.n 8003a1a <HAL_RCCEx_PeriphCLKConfig+0x152>
8003a16: 2301 movs r3, #1
8003a18: e000 b.n 8003a1c <HAL_RCCEx_PeriphCLKConfig+0x154>
8003a1a: 2300 movs r3, #0
8003a1c: 2b00 cmp r3, #0
8003a1e: d00d beq.n 8003a3c <HAL_RCCEx_PeriphCLKConfig+0x174>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003a20: 4b41 ldr r3, [pc, #260] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003a22: 6d9b ldr r3, [r3, #88] @ 0x58
8003a24: 4a40 ldr r2, [pc, #256] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003a26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003a2a: 6593 str r3, [r2, #88] @ 0x58
8003a2c: 4b3e ldr r3, [pc, #248] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003a2e: 6d9b ldr r3, [r3, #88] @ 0x58
8003a30: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003a34: 60bb str r3, [r7, #8]
8003a36: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8003a38: 2301 movs r3, #1
8003a3a: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8003a3c: 4b3b ldr r3, [pc, #236] @ (8003b2c <HAL_RCCEx_PeriphCLKConfig+0x264>)
8003a3e: 681b ldr r3, [r3, #0]
8003a40: 4a3a ldr r2, [pc, #232] @ (8003b2c <HAL_RCCEx_PeriphCLKConfig+0x264>)
8003a42: f443 7380 orr.w r3, r3, #256 @ 0x100
8003a46: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003a48: f7fc fe68 bl 800071c <HAL_GetTick>
8003a4c: 60f8 str r0, [r7, #12]
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8003a4e: e009 b.n 8003a64 <HAL_RCCEx_PeriphCLKConfig+0x19c>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003a50: f7fc fe64 bl 800071c <HAL_GetTick>
8003a54: 4602 mov r2, r0
8003a56: 68fb ldr r3, [r7, #12]
8003a58: 1ad3 subs r3, r2, r3
8003a5a: 2b02 cmp r3, #2
8003a5c: d902 bls.n 8003a64 <HAL_RCCEx_PeriphCLKConfig+0x19c>
{
ret = HAL_TIMEOUT;
8003a5e: 2303 movs r3, #3
8003a60: 74fb strb r3, [r7, #19]
break;
8003a62: e005 b.n 8003a70 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
8003a64: 4b31 ldr r3, [pc, #196] @ (8003b2c <HAL_RCCEx_PeriphCLKConfig+0x264>)
8003a66: 681b ldr r3, [r3, #0]
8003a68: f403 7380 and.w r3, r3, #256 @ 0x100
8003a6c: 2b00 cmp r3, #0
8003a6e: d0ef beq.n 8003a50 <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
if(ret == HAL_OK)
8003a70: 7cfb ldrb r3, [r7, #19]
8003a72: 2b00 cmp r3, #0
8003a74: d15c bne.n 8003b30 <HAL_RCCEx_PeriphCLKConfig+0x268>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8003a76: 4b2c ldr r3, [pc, #176] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003a78: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003a7c: f403 7340 and.w r3, r3, #768 @ 0x300
8003a80: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8003a82: 697b ldr r3, [r7, #20]
8003a84: 2b00 cmp r3, #0
8003a86: d01f beq.n 8003ac8 <HAL_RCCEx_PeriphCLKConfig+0x200>
8003a88: 687b ldr r3, [r7, #4]
8003a8a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8003a8e: 697a ldr r2, [r7, #20]
8003a90: 429a cmp r2, r3
8003a92: d019 beq.n 8003ac8 <HAL_RCCEx_PeriphCLKConfig+0x200>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8003a94: 4b24 ldr r3, [pc, #144] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003a96: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003a9a: f423 7340 bic.w r3, r3, #768 @ 0x300
8003a9e: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8003aa0: 4b21 ldr r3, [pc, #132] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003aa2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003aa6: 4a20 ldr r2, [pc, #128] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003aa8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003aac: f8c2 3090 str.w r3, [r2, #144] @ 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
8003ab0: 4b1d ldr r3, [pc, #116] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003ab2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003ab6: 4a1c ldr r2, [pc, #112] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003ab8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003abc: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8003ac0: 4a19 ldr r2, [pc, #100] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003ac2: 697b ldr r3, [r7, #20]
8003ac4: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8003ac8: 697b ldr r3, [r7, #20]
8003aca: f003 0301 and.w r3, r3, #1
8003ace: 2b00 cmp r3, #0
8003ad0: d016 beq.n 8003b00 <HAL_RCCEx_PeriphCLKConfig+0x238>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003ad2: f7fc fe23 bl 800071c <HAL_GetTick>
8003ad6: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003ad8: e00b b.n 8003af2 <HAL_RCCEx_PeriphCLKConfig+0x22a>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003ada: f7fc fe1f bl 800071c <HAL_GetTick>
8003ade: 4602 mov r2, r0
8003ae0: 68fb ldr r3, [r7, #12]
8003ae2: 1ad3 subs r3, r2, r3
8003ae4: f241 3288 movw r2, #5000 @ 0x1388
8003ae8: 4293 cmp r3, r2
8003aea: d902 bls.n 8003af2 <HAL_RCCEx_PeriphCLKConfig+0x22a>
{
ret = HAL_TIMEOUT;
8003aec: 2303 movs r3, #3
8003aee: 74fb strb r3, [r7, #19]
break;
8003af0: e006 b.n 8003b00 <HAL_RCCEx_PeriphCLKConfig+0x238>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003af2: 4b0d ldr r3, [pc, #52] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003af4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003af8: f003 0302 and.w r3, r3, #2
8003afc: 2b00 cmp r3, #0
8003afe: d0ec beq.n 8003ada <HAL_RCCEx_PeriphCLKConfig+0x212>
}
}
}
if(ret == HAL_OK)
8003b00: 7cfb ldrb r3, [r7, #19]
8003b02: 2b00 cmp r3, #0
8003b04: d10c bne.n 8003b20 <HAL_RCCEx_PeriphCLKConfig+0x258>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003b06: 4b08 ldr r3, [pc, #32] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003b08: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003b0c: f423 7240 bic.w r2, r3, #768 @ 0x300
8003b10: 687b ldr r3, [r7, #4]
8003b12: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8003b16: 4904 ldr r1, [pc, #16] @ (8003b28 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003b18: 4313 orrs r3, r2
8003b1a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8003b1e: e009 b.n 8003b34 <HAL_RCCEx_PeriphCLKConfig+0x26c>
}
else
{
/* set overall return value */
status = ret;
8003b20: 7cfb ldrb r3, [r7, #19]
8003b22: 74bb strb r3, [r7, #18]
8003b24: e006 b.n 8003b34 <HAL_RCCEx_PeriphCLKConfig+0x26c>
8003b26: bf00 nop
8003b28: 40021000 .word 0x40021000
8003b2c: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8003b30: 7cfb ldrb r3, [r7, #19]
8003b32: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8003b34: 7c7b ldrb r3, [r7, #17]
8003b36: 2b01 cmp r3, #1
8003b38: d105 bne.n 8003b46 <HAL_RCCEx_PeriphCLKConfig+0x27e>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003b3a: 4b9e ldr r3, [pc, #632] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003b3c: 6d9b ldr r3, [r3, #88] @ 0x58
8003b3e: 4a9d ldr r2, [pc, #628] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003b40: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8003b44: 6593 str r3, [r2, #88] @ 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8003b46: 687b ldr r3, [r7, #4]
8003b48: 681b ldr r3, [r3, #0]
8003b4a: f003 0301 and.w r3, r3, #1
8003b4e: 2b00 cmp r3, #0
8003b50: d00a beq.n 8003b68 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8003b52: 4b98 ldr r3, [pc, #608] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003b54: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003b58: f023 0203 bic.w r2, r3, #3
8003b5c: 687b ldr r3, [r7, #4]
8003b5e: 6b9b ldr r3, [r3, #56] @ 0x38
8003b60: 4994 ldr r1, [pc, #592] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003b62: 4313 orrs r3, r2
8003b64: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8003b68: 687b ldr r3, [r7, #4]
8003b6a: 681b ldr r3, [r3, #0]
8003b6c: f003 0302 and.w r3, r3, #2
8003b70: 2b00 cmp r3, #0
8003b72: d00a beq.n 8003b8a <HAL_RCCEx_PeriphCLKConfig+0x2c2>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8003b74: 4b8f ldr r3, [pc, #572] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003b76: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003b7a: f023 020c bic.w r2, r3, #12
8003b7e: 687b ldr r3, [r7, #4]
8003b80: 6bdb ldr r3, [r3, #60] @ 0x3c
8003b82: 498c ldr r1, [pc, #560] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003b84: 4313 orrs r3, r2
8003b86: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8003b8a: 687b ldr r3, [r7, #4]
8003b8c: 681b ldr r3, [r3, #0]
8003b8e: f003 0304 and.w r3, r3, #4
8003b92: 2b00 cmp r3, #0
8003b94: d00a beq.n 8003bac <HAL_RCCEx_PeriphCLKConfig+0x2e4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8003b96: 4b87 ldr r3, [pc, #540] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003b98: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003b9c: f023 0230 bic.w r2, r3, #48 @ 0x30
8003ba0: 687b ldr r3, [r7, #4]
8003ba2: 6c1b ldr r3, [r3, #64] @ 0x40
8003ba4: 4983 ldr r1, [pc, #524] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003ba6: 4313 orrs r3, r2
8003ba8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* USART3 */
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8003bac: 687b ldr r3, [r7, #4]
8003bae: 681b ldr r3, [r3, #0]
8003bb0: f003 0308 and.w r3, r3, #8
8003bb4: 2b00 cmp r3, #0
8003bb6: d00a beq.n 8003bce <HAL_RCCEx_PeriphCLKConfig+0x306>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8003bb8: 4b7e ldr r3, [pc, #504] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003bba: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003bbe: f023 02c0 bic.w r2, r3, #192 @ 0xc0
8003bc2: 687b ldr r3, [r7, #4]
8003bc4: 6c5b ldr r3, [r3, #68] @ 0x44
8003bc6: 497b ldr r1, [pc, #492] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003bc8: 4313 orrs r3, r2
8003bca: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* UART4 */
#if defined(UART5)
/*-------------------------- UART5 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8003bce: 687b ldr r3, [r7, #4]
8003bd0: 681b ldr r3, [r3, #0]
8003bd2: f003 0310 and.w r3, r3, #16
8003bd6: 2b00 cmp r3, #0
8003bd8: d00a beq.n 8003bf0 <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
8003bda: 4b76 ldr r3, [pc, #472] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003bdc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003be0: f423 7240 bic.w r2, r3, #768 @ 0x300
8003be4: 687b ldr r3, [r7, #4]
8003be6: 6c9b ldr r3, [r3, #72] @ 0x48
8003be8: 4972 ldr r1, [pc, #456] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003bea: 4313 orrs r3, r2
8003bec: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8003bf0: 687b ldr r3, [r7, #4]
8003bf2: 681b ldr r3, [r3, #0]
8003bf4: f003 0320 and.w r3, r3, #32
8003bf8: 2b00 cmp r3, #0
8003bfa: d00a beq.n 8003c12 <HAL_RCCEx_PeriphCLKConfig+0x34a>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUART1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8003bfc: 4b6d ldr r3, [pc, #436] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003bfe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003c02: f423 6240 bic.w r2, r3, #3072 @ 0xc00
8003c06: 687b ldr r3, [r7, #4]
8003c08: 6cdb ldr r3, [r3, #76] @ 0x4c
8003c0a: 496a ldr r1, [pc, #424] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c0c: 4313 orrs r3, r2
8003c0e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
8003c12: 687b ldr r3, [r7, #4]
8003c14: 681b ldr r3, [r3, #0]
8003c16: f403 7300 and.w r3, r3, #512 @ 0x200
8003c1a: 2b00 cmp r3, #0
8003c1c: d00a beq.n 8003c34 <HAL_RCCEx_PeriphCLKConfig+0x36c>
{
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8003c1e: 4b65 ldr r3, [pc, #404] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c20: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003c24: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
8003c28: 687b ldr r3, [r7, #4]
8003c2a: 6ddb ldr r3, [r3, #92] @ 0x5c
8003c2c: 4961 ldr r1, [pc, #388] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c2e: 4313 orrs r3, r2
8003c30: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
8003c34: 687b ldr r3, [r7, #4]
8003c36: 681b ldr r3, [r3, #0]
8003c38: f403 6380 and.w r3, r3, #1024 @ 0x400
8003c3c: 2b00 cmp r3, #0
8003c3e: d00a beq.n 8003c56 <HAL_RCCEx_PeriphCLKConfig+0x38e>
{
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
8003c40: 4b5c ldr r3, [pc, #368] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c42: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003c46: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8003c4a: 687b ldr r3, [r7, #4]
8003c4c: 6e1b ldr r3, [r3, #96] @ 0x60
8003c4e: 4959 ldr r1, [pc, #356] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c50: 4313 orrs r3, r2
8003c52: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8003c56: 687b ldr r3, [r7, #4]
8003c58: 681b ldr r3, [r3, #0]
8003c5a: f003 0340 and.w r3, r3, #64 @ 0x40
8003c5e: 2b00 cmp r3, #0
8003c60: d00a beq.n 8003c78 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8003c62: 4b54 ldr r3, [pc, #336] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c64: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003c68: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8003c6c: 687b ldr r3, [r7, #4]
8003c6e: 6d1b ldr r3, [r3, #80] @ 0x50
8003c70: 4950 ldr r1, [pc, #320] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c72: 4313 orrs r3, r2
8003c74: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(I2C2)
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8003c78: 687b ldr r3, [r7, #4]
8003c7a: 681b ldr r3, [r3, #0]
8003c7c: f003 0380 and.w r3, r3, #128 @ 0x80
8003c80: 2b00 cmp r3, #0
8003c82: d00a beq.n 8003c9a <HAL_RCCEx_PeriphCLKConfig+0x3d2>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8003c84: 4b4b ldr r3, [pc, #300] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c86: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003c8a: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8003c8e: 687b ldr r3, [r7, #4]
8003c90: 6d5b ldr r3, [r3, #84] @ 0x54
8003c92: 4948 ldr r1, [pc, #288] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003c94: 4313 orrs r3, r2
8003c96: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* I2C2 */
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8003c9a: 687b ldr r3, [r7, #4]
8003c9c: 681b ldr r3, [r3, #0]
8003c9e: f403 7380 and.w r3, r3, #256 @ 0x100
8003ca2: 2b00 cmp r3, #0
8003ca4: d00a beq.n 8003cbc <HAL_RCCEx_PeriphCLKConfig+0x3f4>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8003ca6: 4b43 ldr r3, [pc, #268] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003ca8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003cac: f423 3240 bic.w r2, r3, #196608 @ 0x30000
8003cb0: 687b ldr r3, [r7, #4]
8003cb2: 6d9b ldr r3, [r3, #88] @ 0x58
8003cb4: 493f ldr r1, [pc, #252] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003cb6: 4313 orrs r3, r2
8003cb8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* I2C4 */
#if defined(USB_OTG_FS) || defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
8003cbc: 687b ldr r3, [r7, #4]
8003cbe: 681b ldr r3, [r3, #0]
8003cc0: f403 5300 and.w r3, r3, #8192 @ 0x2000
8003cc4: 2b00 cmp r3, #0
8003cc6: d028 beq.n 8003d1a <HAL_RCCEx_PeriphCLKConfig+0x452>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8003cc8: 4b3a ldr r3, [pc, #232] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003cca: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003cce: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8003cd2: 687b ldr r3, [r7, #4]
8003cd4: 6edb ldr r3, [r3, #108] @ 0x6c
8003cd6: 4937 ldr r1, [pc, #220] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003cd8: 4313 orrs r3, r2
8003cda: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
8003cde: 687b ldr r3, [r7, #4]
8003ce0: 6edb ldr r3, [r3, #108] @ 0x6c
8003ce2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8003ce6: d106 bne.n 8003cf6 <HAL_RCCEx_PeriphCLKConfig+0x42e>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8003ce8: 4b32 ldr r3, [pc, #200] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003cea: 68db ldr r3, [r3, #12]
8003cec: 4a31 ldr r2, [pc, #196] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003cee: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8003cf2: 60d3 str r3, [r2, #12]
8003cf4: e011 b.n 8003d1a <HAL_RCCEx_PeriphCLKConfig+0x452>
}
else
{
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
8003cf6: 687b ldr r3, [r7, #4]
8003cf8: 6edb ldr r3, [r3, #108] @ 0x6c
8003cfa: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
8003cfe: d10c bne.n 8003d1a <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
8003d00: 687b ldr r3, [r7, #4]
8003d02: 3304 adds r3, #4
8003d04: 2101 movs r1, #1
8003d06: 4618 mov r0, r3
8003d08: f000 f8c8 bl 8003e9c <RCCEx_PLLSAI1_Config>
8003d0c: 4603 mov r3, r0
8003d0e: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003d10: 7cfb ldrb r3, [r7, #19]
8003d12: 2b00 cmp r3, #0
8003d14: d001 beq.n 8003d1a <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* set overall return value */
status = ret;
8003d16: 7cfb ldrb r3, [r7, #19]
8003d18: 74bb strb r3, [r7, #18]
#endif /* USB_OTG_FS || USB */
#if defined(SDMMC1)
/*-------------------------- SDMMC1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
8003d1a: 687b ldr r3, [r7, #4]
8003d1c: 681b ldr r3, [r3, #0]
8003d1e: f403 2300 and.w r3, r3, #524288 @ 0x80000
8003d22: 2b00 cmp r3, #0
8003d24: d028 beq.n 8003d78 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
8003d26: 4b23 ldr r3, [pc, #140] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003d28: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003d2c: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8003d30: 687b ldr r3, [r7, #4]
8003d32: 6f1b ldr r3, [r3, #112] @ 0x70
8003d34: 491f ldr r1, [pc, #124] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003d36: 4313 orrs r3, r2
8003d38: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
8003d3c: 687b ldr r3, [r7, #4]
8003d3e: 6f1b ldr r3, [r3, #112] @ 0x70
8003d40: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8003d44: d106 bne.n 8003d54 <HAL_RCCEx_PeriphCLKConfig+0x48c>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8003d46: 4b1b ldr r3, [pc, #108] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003d48: 68db ldr r3, [r3, #12]
8003d4a: 4a1a ldr r2, [pc, #104] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003d4c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8003d50: 60d3 str r3, [r2, #12]
8003d52: e011 b.n 8003d78 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* Enable PLLSAI3CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
}
#endif
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
8003d54: 687b ldr r3, [r7, #4]
8003d56: 6f1b ldr r3, [r3, #112] @ 0x70
8003d58: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
8003d5c: d10c bne.n 8003d78 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
8003d5e: 687b ldr r3, [r7, #4]
8003d60: 3304 adds r3, #4
8003d62: 2101 movs r1, #1
8003d64: 4618 mov r0, r3
8003d66: f000 f899 bl 8003e9c <RCCEx_PLLSAI1_Config>
8003d6a: 4603 mov r3, r0
8003d6c: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003d6e: 7cfb ldrb r3, [r7, #19]
8003d70: 2b00 cmp r3, #0
8003d72: d001 beq.n 8003d78 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
{
/* set overall return value */
status = ret;
8003d74: 7cfb ldrb r3, [r7, #19]
8003d76: 74bb strb r3, [r7, #18]
}
#endif /* SDMMC1 */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
8003d78: 687b ldr r3, [r7, #4]
8003d7a: 681b ldr r3, [r3, #0]
8003d7c: f403 2380 and.w r3, r3, #262144 @ 0x40000
8003d80: 2b00 cmp r3, #0
8003d82: d02b beq.n 8003ddc <HAL_RCCEx_PeriphCLKConfig+0x514>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
8003d84: 4b0b ldr r3, [pc, #44] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003d86: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003d8a: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8003d8e: 687b ldr r3, [r7, #4]
8003d90: 6f5b ldr r3, [r3, #116] @ 0x74
8003d92: 4908 ldr r1, [pc, #32] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003d94: 4313 orrs r3, r2
8003d96: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
8003d9a: 687b ldr r3, [r7, #4]
8003d9c: 6f5b ldr r3, [r3, #116] @ 0x74
8003d9e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8003da2: d109 bne.n 8003db8 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
{
/* Enable PLL48M1CLK output clock */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8003da4: 4b03 ldr r3, [pc, #12] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003da6: 68db ldr r3, [r3, #12]
8003da8: 4a02 ldr r2, [pc, #8] @ (8003db4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
8003daa: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8003dae: 60d3 str r3, [r2, #12]
8003db0: e014 b.n 8003ddc <HAL_RCCEx_PeriphCLKConfig+0x514>
8003db2: bf00 nop
8003db4: 40021000 .word 0x40021000
}
#if defined(RCC_PLLSAI1_SUPPORT)
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
8003db8: 687b ldr r3, [r7, #4]
8003dba: 6f5b ldr r3, [r3, #116] @ 0x74
8003dbc: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
8003dc0: d10c bne.n 8003ddc <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
8003dc2: 687b ldr r3, [r7, #4]
8003dc4: 3304 adds r3, #4
8003dc6: 2101 movs r1, #1
8003dc8: 4618 mov r0, r3
8003dca: f000 f867 bl 8003e9c <RCCEx_PLLSAI1_Config>
8003dce: 4603 mov r3, r0
8003dd0: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003dd2: 7cfb ldrb r3, [r7, #19]
8003dd4: 2b00 cmp r3, #0
8003dd6: d001 beq.n 8003ddc <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* set overall return value */
status = ret;
8003dd8: 7cfb ldrb r3, [r7, #19]
8003dda: 74bb strb r3, [r7, #18]
}
}
/*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003ddc: 687b ldr r3, [r7, #4]
8003dde: 681b ldr r3, [r3, #0]
8003de0: f403 4380 and.w r3, r3, #16384 @ 0x4000
8003de4: 2b00 cmp r3, #0
8003de6: d02f beq.n 8003e48 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8003de8: 4b2b ldr r3, [pc, #172] @ (8003e98 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003dea: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003dee: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
8003df2: 687b ldr r3, [r7, #4]
8003df4: 6f9b ldr r3, [r3, #120] @ 0x78
8003df6: 4928 ldr r1, [pc, #160] @ (8003e98 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003df8: 4313 orrs r3, r2
8003dfa: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#if defined(RCC_PLLSAI1_SUPPORT)
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
8003dfe: 687b ldr r3, [r7, #4]
8003e00: 6f9b ldr r3, [r3, #120] @ 0x78
8003e02: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8003e06: d10d bne.n 8003e24 <HAL_RCCEx_PeriphCLKConfig+0x55c>
{
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
8003e08: 687b ldr r3, [r7, #4]
8003e0a: 3304 adds r3, #4
8003e0c: 2102 movs r1, #2
8003e0e: 4618 mov r0, r3
8003e10: f000 f844 bl 8003e9c <RCCEx_PLLSAI1_Config>
8003e14: 4603 mov r3, r0
8003e16: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003e18: 7cfb ldrb r3, [r7, #19]
8003e1a: 2b00 cmp r3, #0
8003e1c: d014 beq.n 8003e48 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* set overall return value */
status = ret;
8003e1e: 7cfb ldrb r3, [r7, #19]
8003e20: 74bb strb r3, [r7, #18]
8003e22: e011 b.n 8003e48 <HAL_RCCEx_PeriphCLKConfig+0x580>
}
#endif /* RCC_PLLSAI1_SUPPORT */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
8003e24: 687b ldr r3, [r7, #4]
8003e26: 6f9b ldr r3, [r3, #120] @ 0x78
8003e28: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8003e2c: d10c bne.n 8003e48 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
8003e2e: 687b ldr r3, [r7, #4]
8003e30: 3320 adds r3, #32
8003e32: 2102 movs r1, #2
8003e34: 4618 mov r0, r3
8003e36: f000 f925 bl 8004084 <RCCEx_PLLSAI2_Config>
8003e3a: 4603 mov r3, r0
8003e3c: 74fb strb r3, [r7, #19]
if(ret != HAL_OK)
8003e3e: 7cfb ldrb r3, [r7, #19]
8003e40: 2b00 cmp r3, #0
8003e42: d001 beq.n 8003e48 <HAL_RCCEx_PeriphCLKConfig+0x580>
{
/* set overall return value */
status = ret;
8003e44: 7cfb ldrb r3, [r7, #19]
8003e46: 74bb strb r3, [r7, #18]
#endif /* !STM32L412xx && !STM32L422xx */
#if defined(SWPMI1)
/*-------------------------- SWPMI1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
8003e48: 687b ldr r3, [r7, #4]
8003e4a: 681b ldr r3, [r3, #0]
8003e4c: f403 4300 and.w r3, r3, #32768 @ 0x8000
8003e50: 2b00 cmp r3, #0
8003e52: d00a beq.n 8003e6a <HAL_RCCEx_PeriphCLKConfig+0x5a2>
{
/* Check the parameters */
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
/* Configure the SWPMI1 clock source */
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
8003e54: 4b10 ldr r3, [pc, #64] @ (8003e98 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003e56: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003e5a: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000
8003e5e: 687b ldr r3, [r7, #4]
8003e60: 6fdb ldr r3, [r3, #124] @ 0x7c
8003e62: 490d ldr r1, [pc, #52] @ (8003e98 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003e64: 4313 orrs r3, r2
8003e66: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* SWPMI1 */
#if defined(DFSDM1_Filter0)
/*-------------------------- DFSDM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
8003e6a: 687b ldr r3, [r7, #4]
8003e6c: 681b ldr r3, [r3, #0]
8003e6e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003e72: 2b00 cmp r3, #0
8003e74: d00b beq.n 8003e8e <HAL_RCCEx_PeriphCLKConfig+0x5c6>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
/* Configure the DFSDM1 interface clock source */
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
8003e76: 4b08 ldr r3, [pc, #32] @ (8003e98 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003e78: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8003e7c: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8003e80: 687b ldr r3, [r7, #4]
8003e82: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003e86: 4904 ldr r1, [pc, #16] @ (8003e98 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
8003e88: 4313 orrs r3, r2
8003e8a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
}
#endif /* OCTOSPI1 || OCTOSPI2 */
return status;
8003e8e: 7cbb ldrb r3, [r7, #18]
}
8003e90: 4618 mov r0, r3
8003e92: 3718 adds r7, #24
8003e94: 46bd mov sp, r7
8003e96: bd80 pop {r7, pc}
8003e98: 40021000 .word 0x40021000
08003e9c <RCCEx_PLLSAI1_Config>:
* @note PLLSAI1 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
8003e9c: b580 push {r7, lr}
8003e9e: b084 sub sp, #16
8003ea0: af00 add r7, sp, #0
8003ea2: 6078 str r0, [r7, #4]
8003ea4: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
8003ea6: 2300 movs r3, #0
8003ea8: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
/* Check that PLLSAI1 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
8003eaa: 4b75 ldr r3, [pc, #468] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003eac: 68db ldr r3, [r3, #12]
8003eae: f003 0303 and.w r3, r3, #3
8003eb2: 2b00 cmp r3, #0
8003eb4: d018 beq.n 8003ee8 <RCCEx_PLLSAI1_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
8003eb6: 4b72 ldr r3, [pc, #456] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003eb8: 68db ldr r3, [r3, #12]
8003eba: f003 0203 and.w r2, r3, #3
8003ebe: 687b ldr r3, [r7, #4]
8003ec0: 681b ldr r3, [r3, #0]
8003ec2: 429a cmp r2, r3
8003ec4: d10d bne.n 8003ee2 <RCCEx_PLLSAI1_Config+0x46>
||
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
8003ec6: 687b ldr r3, [r7, #4]
8003ec8: 681b ldr r3, [r3, #0]
||
8003eca: 2b00 cmp r3, #0
8003ecc: d009 beq.n 8003ee2 <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
8003ece: 4b6c ldr r3, [pc, #432] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003ed0: 68db ldr r3, [r3, #12]
8003ed2: 091b lsrs r3, r3, #4
8003ed4: f003 0307 and.w r3, r3, #7
8003ed8: 1c5a adds r2, r3, #1
8003eda: 687b ldr r3, [r7, #4]
8003edc: 685b ldr r3, [r3, #4]
||
8003ede: 429a cmp r2, r3
8003ee0: d047 beq.n 8003f72 <RCCEx_PLLSAI1_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
8003ee2: 2301 movs r3, #1
8003ee4: 73fb strb r3, [r7, #15]
8003ee6: e044 b.n 8003f72 <RCCEx_PLLSAI1_Config+0xd6>
}
}
else
{
/* Check PLLSAI1 clock source availability */
switch(PllSai1->PLLSAI1Source)
8003ee8: 687b ldr r3, [r7, #4]
8003eea: 681b ldr r3, [r3, #0]
8003eec: 2b03 cmp r3, #3
8003eee: d018 beq.n 8003f22 <RCCEx_PLLSAI1_Config+0x86>
8003ef0: 2b03 cmp r3, #3
8003ef2: d825 bhi.n 8003f40 <RCCEx_PLLSAI1_Config+0xa4>
8003ef4: 2b01 cmp r3, #1
8003ef6: d002 beq.n 8003efe <RCCEx_PLLSAI1_Config+0x62>
8003ef8: 2b02 cmp r3, #2
8003efa: d009 beq.n 8003f10 <RCCEx_PLLSAI1_Config+0x74>
8003efc: e020 b.n 8003f40 <RCCEx_PLLSAI1_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
8003efe: 4b60 ldr r3, [pc, #384] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003f00: 681b ldr r3, [r3, #0]
8003f02: f003 0302 and.w r3, r3, #2
8003f06: 2b00 cmp r3, #0
8003f08: d11d bne.n 8003f46 <RCCEx_PLLSAI1_Config+0xaa>
{
status = HAL_ERROR;
8003f0a: 2301 movs r3, #1
8003f0c: 73fb strb r3, [r7, #15]
}
break;
8003f0e: e01a b.n 8003f46 <RCCEx_PLLSAI1_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
8003f10: 4b5b ldr r3, [pc, #364] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003f12: 681b ldr r3, [r3, #0]
8003f14: f403 6380 and.w r3, r3, #1024 @ 0x400
8003f18: 2b00 cmp r3, #0
8003f1a: d116 bne.n 8003f4a <RCCEx_PLLSAI1_Config+0xae>
{
status = HAL_ERROR;
8003f1c: 2301 movs r3, #1
8003f1e: 73fb strb r3, [r7, #15]
}
break;
8003f20: e013 b.n 8003f4a <RCCEx_PLLSAI1_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
8003f22: 4b57 ldr r3, [pc, #348] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003f24: 681b ldr r3, [r3, #0]
8003f26: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003f2a: 2b00 cmp r3, #0
8003f2c: d10f bne.n 8003f4e <RCCEx_PLLSAI1_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
8003f2e: 4b54 ldr r3, [pc, #336] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003f30: 681b ldr r3, [r3, #0]
8003f32: f403 2380 and.w r3, r3, #262144 @ 0x40000
8003f36: 2b00 cmp r3, #0
8003f38: d109 bne.n 8003f4e <RCCEx_PLLSAI1_Config+0xb2>
{
status = HAL_ERROR;
8003f3a: 2301 movs r3, #1
8003f3c: 73fb strb r3, [r7, #15]
}
}
break;
8003f3e: e006 b.n 8003f4e <RCCEx_PLLSAI1_Config+0xb2>
default:
status = HAL_ERROR;
8003f40: 2301 movs r3, #1
8003f42: 73fb strb r3, [r7, #15]
break;
8003f44: e004 b.n 8003f50 <RCCEx_PLLSAI1_Config+0xb4>
break;
8003f46: bf00 nop
8003f48: e002 b.n 8003f50 <RCCEx_PLLSAI1_Config+0xb4>
break;
8003f4a: bf00 nop
8003f4c: e000 b.n 8003f50 <RCCEx_PLLSAI1_Config+0xb4>
break;
8003f4e: bf00 nop
}
if(status == HAL_OK)
8003f50: 7bfb ldrb r3, [r7, #15]
8003f52: 2b00 cmp r3, #0
8003f54: d10d bne.n 8003f72 <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
/* Set PLLSAI1 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
/* Set PLLSAI1 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
8003f56: 4b4a ldr r3, [pc, #296] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003f58: 68db ldr r3, [r3, #12]
8003f5a: f023 0273 bic.w r2, r3, #115 @ 0x73
8003f5e: 687b ldr r3, [r7, #4]
8003f60: 6819 ldr r1, [r3, #0]
8003f62: 687b ldr r3, [r7, #4]
8003f64: 685b ldr r3, [r3, #4]
8003f66: 3b01 subs r3, #1
8003f68: 011b lsls r3, r3, #4
8003f6a: 430b orrs r3, r1
8003f6c: 4944 ldr r1, [pc, #272] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003f6e: 4313 orrs r3, r2
8003f70: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
8003f72: 7bfb ldrb r3, [r7, #15]
8003f74: 2b00 cmp r3, #0
8003f76: d17d bne.n 8004074 <RCCEx_PLLSAI1_Config+0x1d8>
{
/* Disable the PLLSAI1 */
__HAL_RCC_PLLSAI1_DISABLE();
8003f78: 4b41 ldr r3, [pc, #260] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003f7a: 681b ldr r3, [r3, #0]
8003f7c: 4a40 ldr r2, [pc, #256] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003f7e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8003f82: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003f84: f7fc fbca bl 800071c <HAL_GetTick>
8003f88: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
8003f8a: e009 b.n 8003fa0 <RCCEx_PLLSAI1_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
8003f8c: f7fc fbc6 bl 800071c <HAL_GetTick>
8003f90: 4602 mov r2, r0
8003f92: 68bb ldr r3, [r7, #8]
8003f94: 1ad3 subs r3, r2, r3
8003f96: 2b02 cmp r3, #2
8003f98: d902 bls.n 8003fa0 <RCCEx_PLLSAI1_Config+0x104>
{
status = HAL_TIMEOUT;
8003f9a: 2303 movs r3, #3
8003f9c: 73fb strb r3, [r7, #15]
break;
8003f9e: e005 b.n 8003fac <RCCEx_PLLSAI1_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
8003fa0: 4b37 ldr r3, [pc, #220] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003fa2: 681b ldr r3, [r3, #0]
8003fa4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8003fa8: 2b00 cmp r3, #0
8003faa: d1ef bne.n 8003f8c <RCCEx_PLLSAI1_Config+0xf0>
}
}
if(status == HAL_OK)
8003fac: 7bfb ldrb r3, [r7, #15]
8003fae: 2b00 cmp r3, #0
8003fb0: d160 bne.n 8004074 <RCCEx_PLLSAI1_Config+0x1d8>
{
if(Divider == DIVIDER_P_UPDATE)
8003fb2: 683b ldr r3, [r7, #0]
8003fb4: 2b00 cmp r3, #0
8003fb6: d111 bne.n 8003fdc <RCCEx_PLLSAI1_Config+0x140>
MODIFY_REG(RCC->PLLSAI1CFGR,
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI1CFGR,
8003fb8: 4b31 ldr r3, [pc, #196] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003fba: 691b ldr r3, [r3, #16]
8003fbc: f423 331f bic.w r3, r3, #162816 @ 0x27c00
8003fc0: f423 7340 bic.w r3, r3, #768 @ 0x300
8003fc4: 687a ldr r2, [r7, #4]
8003fc6: 6892 ldr r2, [r2, #8]
8003fc8: 0211 lsls r1, r2, #8
8003fca: 687a ldr r2, [r7, #4]
8003fcc: 68d2 ldr r2, [r2, #12]
8003fce: 0912 lsrs r2, r2, #4
8003fd0: 0452 lsls r2, r2, #17
8003fd2: 430a orrs r2, r1
8003fd4: 492a ldr r1, [pc, #168] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003fd6: 4313 orrs r3, r2
8003fd8: 610b str r3, [r1, #16]
8003fda: e027 b.n 800402c <RCCEx_PLLSAI1_Config+0x190>
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
else if(Divider == DIVIDER_Q_UPDATE)
8003fdc: 683b ldr r3, [r7, #0]
8003fde: 2b01 cmp r3, #1
8003fe0: d112 bne.n 8004008 <RCCEx_PLLSAI1_Config+0x16c>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
8003fe2: 4b27 ldr r3, [pc, #156] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8003fe4: 691b ldr r3, [r3, #16]
8003fe6: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000
8003fea: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
8003fee: 687a ldr r2, [r7, #4]
8003ff0: 6892 ldr r2, [r2, #8]
8003ff2: 0211 lsls r1, r2, #8
8003ff4: 687a ldr r2, [r7, #4]
8003ff6: 6912 ldr r2, [r2, #16]
8003ff8: 0852 lsrs r2, r2, #1
8003ffa: 3a01 subs r2, #1
8003ffc: 0552 lsls r2, r2, #21
8003ffe: 430a orrs r2, r1
8004000: 491f ldr r1, [pc, #124] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8004002: 4313 orrs r3, r2
8004004: 610b str r3, [r1, #16]
8004006: e011 b.n 800402c <RCCEx_PLLSAI1_Config+0x190>
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
8004008: 4b1d ldr r3, [pc, #116] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
800400a: 691b ldr r3, [r3, #16]
800400c: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
8004010: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
8004014: 687a ldr r2, [r7, #4]
8004016: 6892 ldr r2, [r2, #8]
8004018: 0211 lsls r1, r2, #8
800401a: 687a ldr r2, [r7, #4]
800401c: 6952 ldr r2, [r2, #20]
800401e: 0852 lsrs r2, r2, #1
8004020: 3a01 subs r2, #1
8004022: 0652 lsls r2, r2, #25
8004024: 430a orrs r2, r1
8004026: 4916 ldr r1, [pc, #88] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8004028: 4313 orrs r3, r2
800402a: 610b str r3, [r1, #16]
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
__HAL_RCC_PLLSAI1_ENABLE();
800402c: 4b14 ldr r3, [pc, #80] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
800402e: 681b ldr r3, [r3, #0]
8004030: 4a13 ldr r2, [pc, #76] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8004032: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8004036: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004038: f7fc fb70 bl 800071c <HAL_GetTick>
800403c: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
800403e: e009 b.n 8004054 <RCCEx_PLLSAI1_Config+0x1b8>
{
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
8004040: f7fc fb6c bl 800071c <HAL_GetTick>
8004044: 4602 mov r2, r0
8004046: 68bb ldr r3, [r7, #8]
8004048: 1ad3 subs r3, r2, r3
800404a: 2b02 cmp r3, #2
800404c: d902 bls.n 8004054 <RCCEx_PLLSAI1_Config+0x1b8>
{
status = HAL_TIMEOUT;
800404e: 2303 movs r3, #3
8004050: 73fb strb r3, [r7, #15]
break;
8004052: e005 b.n 8004060 <RCCEx_PLLSAI1_Config+0x1c4>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
8004054: 4b0a ldr r3, [pc, #40] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8004056: 681b ldr r3, [r3, #0]
8004058: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
800405c: 2b00 cmp r3, #0
800405e: d0ef beq.n 8004040 <RCCEx_PLLSAI1_Config+0x1a4>
}
}
if(status == HAL_OK)
8004060: 7bfb ldrb r3, [r7, #15]
8004062: 2b00 cmp r3, #0
8004064: d106 bne.n 8004074 <RCCEx_PLLSAI1_Config+0x1d8>
{
/* Configure the PLLSAI1 Clock output(s) */
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
8004066: 4b06 ldr r3, [pc, #24] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8004068: 691a ldr r2, [r3, #16]
800406a: 687b ldr r3, [r7, #4]
800406c: 699b ldr r3, [r3, #24]
800406e: 4904 ldr r1, [pc, #16] @ (8004080 <RCCEx_PLLSAI1_Config+0x1e4>)
8004070: 4313 orrs r3, r2
8004072: 610b str r3, [r1, #16]
}
}
}
return status;
8004074: 7bfb ldrb r3, [r7, #15]
}
8004076: 4618 mov r0, r3
8004078: 3710 adds r7, #16
800407a: 46bd mov sp, r7
800407c: bd80 pop {r7, pc}
800407e: bf00 nop
8004080: 40021000 .word 0x40021000
08004084 <RCCEx_PLLSAI2_Config>:
* @note PLLSAI2 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
{
8004084: b580 push {r7, lr}
8004086: b084 sub sp, #16
8004088: af00 add r7, sp, #0
800408a: 6078 str r0, [r7, #4]
800408c: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
800408e: 2300 movs r3, #0
8004090: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
/* Check that PLLSAI2 clock source and divider M can be applied */
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
8004092: 4b6a ldr r3, [pc, #424] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
8004094: 68db ldr r3, [r3, #12]
8004096: f003 0303 and.w r3, r3, #3
800409a: 2b00 cmp r3, #0
800409c: d018 beq.n 80040d0 <RCCEx_PLLSAI2_Config+0x4c>
{
/* PLL clock source and divider M already set, check that no request for change */
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
800409e: 4b67 ldr r3, [pc, #412] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80040a0: 68db ldr r3, [r3, #12]
80040a2: f003 0203 and.w r2, r3, #3
80040a6: 687b ldr r3, [r7, #4]
80040a8: 681b ldr r3, [r3, #0]
80040aa: 429a cmp r2, r3
80040ac: d10d bne.n 80040ca <RCCEx_PLLSAI2_Config+0x46>
||
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
80040ae: 687b ldr r3, [r7, #4]
80040b0: 681b ldr r3, [r3, #0]
||
80040b2: 2b00 cmp r3, #0
80040b4: d009 beq.n 80040ca <RCCEx_PLLSAI2_Config+0x46>
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
||
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
80040b6: 4b61 ldr r3, [pc, #388] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80040b8: 68db ldr r3, [r3, #12]
80040ba: 091b lsrs r3, r3, #4
80040bc: f003 0307 and.w r3, r3, #7
80040c0: 1c5a adds r2, r3, #1
80040c2: 687b ldr r3, [r7, #4]
80040c4: 685b ldr r3, [r3, #4]
||
80040c6: 429a cmp r2, r3
80040c8: d047 beq.n 800415a <RCCEx_PLLSAI2_Config+0xd6>
#endif
)
{
status = HAL_ERROR;
80040ca: 2301 movs r3, #1
80040cc: 73fb strb r3, [r7, #15]
80040ce: e044 b.n 800415a <RCCEx_PLLSAI2_Config+0xd6>
}
}
else
{
/* Check PLLSAI2 clock source availability */
switch(PllSai2->PLLSAI2Source)
80040d0: 687b ldr r3, [r7, #4]
80040d2: 681b ldr r3, [r3, #0]
80040d4: 2b03 cmp r3, #3
80040d6: d018 beq.n 800410a <RCCEx_PLLSAI2_Config+0x86>
80040d8: 2b03 cmp r3, #3
80040da: d825 bhi.n 8004128 <RCCEx_PLLSAI2_Config+0xa4>
80040dc: 2b01 cmp r3, #1
80040de: d002 beq.n 80040e6 <RCCEx_PLLSAI2_Config+0x62>
80040e0: 2b02 cmp r3, #2
80040e2: d009 beq.n 80040f8 <RCCEx_PLLSAI2_Config+0x74>
80040e4: e020 b.n 8004128 <RCCEx_PLLSAI2_Config+0xa4>
{
case RCC_PLLSOURCE_MSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
80040e6: 4b55 ldr r3, [pc, #340] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80040e8: 681b ldr r3, [r3, #0]
80040ea: f003 0302 and.w r3, r3, #2
80040ee: 2b00 cmp r3, #0
80040f0: d11d bne.n 800412e <RCCEx_PLLSAI2_Config+0xaa>
{
status = HAL_ERROR;
80040f2: 2301 movs r3, #1
80040f4: 73fb strb r3, [r7, #15]
}
break;
80040f6: e01a b.n 800412e <RCCEx_PLLSAI2_Config+0xaa>
case RCC_PLLSOURCE_HSI:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
80040f8: 4b50 ldr r3, [pc, #320] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80040fa: 681b ldr r3, [r3, #0]
80040fc: f403 6380 and.w r3, r3, #1024 @ 0x400
8004100: 2b00 cmp r3, #0
8004102: d116 bne.n 8004132 <RCCEx_PLLSAI2_Config+0xae>
{
status = HAL_ERROR;
8004104: 2301 movs r3, #1
8004106: 73fb strb r3, [r7, #15]
}
break;
8004108: e013 b.n 8004132 <RCCEx_PLLSAI2_Config+0xae>
case RCC_PLLSOURCE_HSE:
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
800410a: 4b4c ldr r3, [pc, #304] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
800410c: 681b ldr r3, [r3, #0]
800410e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004112: 2b00 cmp r3, #0
8004114: d10f bne.n 8004136 <RCCEx_PLLSAI2_Config+0xb2>
{
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
8004116: 4b49 ldr r3, [pc, #292] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
8004118: 681b ldr r3, [r3, #0]
800411a: f403 2380 and.w r3, r3, #262144 @ 0x40000
800411e: 2b00 cmp r3, #0
8004120: d109 bne.n 8004136 <RCCEx_PLLSAI2_Config+0xb2>
{
status = HAL_ERROR;
8004122: 2301 movs r3, #1
8004124: 73fb strb r3, [r7, #15]
}
}
break;
8004126: e006 b.n 8004136 <RCCEx_PLLSAI2_Config+0xb2>
default:
status = HAL_ERROR;
8004128: 2301 movs r3, #1
800412a: 73fb strb r3, [r7, #15]
break;
800412c: e004 b.n 8004138 <RCCEx_PLLSAI2_Config+0xb4>
break;
800412e: bf00 nop
8004130: e002 b.n 8004138 <RCCEx_PLLSAI2_Config+0xb4>
break;
8004132: bf00 nop
8004134: e000 b.n 8004138 <RCCEx_PLLSAI2_Config+0xb4>
break;
8004136: bf00 nop
}
if(status == HAL_OK)
8004138: 7bfb ldrb r3, [r7, #15]
800413a: 2b00 cmp r3, #0
800413c: d10d bne.n 800415a <RCCEx_PLLSAI2_Config+0xd6>
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
/* Set PLLSAI2 clock source */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
#else
/* Set PLLSAI2 clock source and divider M */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
800413e: 4b3f ldr r3, [pc, #252] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
8004140: 68db ldr r3, [r3, #12]
8004142: f023 0273 bic.w r2, r3, #115 @ 0x73
8004146: 687b ldr r3, [r7, #4]
8004148: 6819 ldr r1, [r3, #0]
800414a: 687b ldr r3, [r7, #4]
800414c: 685b ldr r3, [r3, #4]
800414e: 3b01 subs r3, #1
8004150: 011b lsls r3, r3, #4
8004152: 430b orrs r3, r1
8004154: 4939 ldr r1, [pc, #228] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
8004156: 4313 orrs r3, r2
8004158: 60cb str r3, [r1, #12]
#endif
}
}
if(status == HAL_OK)
800415a: 7bfb ldrb r3, [r7, #15]
800415c: 2b00 cmp r3, #0
800415e: d167 bne.n 8004230 <RCCEx_PLLSAI2_Config+0x1ac>
{
/* Disable the PLLSAI2 */
__HAL_RCC_PLLSAI2_DISABLE();
8004160: 4b36 ldr r3, [pc, #216] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
8004162: 681b ldr r3, [r3, #0]
8004164: 4a35 ldr r2, [pc, #212] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
8004166: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800416a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800416c: f7fc fad6 bl 800071c <HAL_GetTick>
8004170: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI2 is ready to be updated */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
8004172: e009 b.n 8004188 <RCCEx_PLLSAI2_Config+0x104>
{
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
8004174: f7fc fad2 bl 800071c <HAL_GetTick>
8004178: 4602 mov r2, r0
800417a: 68bb ldr r3, [r7, #8]
800417c: 1ad3 subs r3, r2, r3
800417e: 2b02 cmp r3, #2
8004180: d902 bls.n 8004188 <RCCEx_PLLSAI2_Config+0x104>
{
status = HAL_TIMEOUT;
8004182: 2303 movs r3, #3
8004184: 73fb strb r3, [r7, #15]
break;
8004186: e005 b.n 8004194 <RCCEx_PLLSAI2_Config+0x110>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
8004188: 4b2c ldr r3, [pc, #176] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
800418a: 681b ldr r3, [r3, #0]
800418c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8004190: 2b00 cmp r3, #0
8004192: d1ef bne.n 8004174 <RCCEx_PLLSAI2_Config+0xf0>
}
}
if(status == HAL_OK)
8004194: 7bfb ldrb r3, [r7, #15]
8004196: 2b00 cmp r3, #0
8004198: d14a bne.n 8004230 <RCCEx_PLLSAI2_Config+0x1ac>
{
if(Divider == DIVIDER_P_UPDATE)
800419a: 683b ldr r3, [r7, #0]
800419c: 2b00 cmp r3, #0
800419e: d111 bne.n 80041c4 <RCCEx_PLLSAI2_Config+0x140>
MODIFY_REG(RCC->PLLSAI2CFGR,
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI2CFGR,
80041a0: 4b26 ldr r3, [pc, #152] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80041a2: 695b ldr r3, [r3, #20]
80041a4: f423 331f bic.w r3, r3, #162816 @ 0x27c00
80041a8: f423 7340 bic.w r3, r3, #768 @ 0x300
80041ac: 687a ldr r2, [r7, #4]
80041ae: 6892 ldr r2, [r2, #8]
80041b0: 0211 lsls r1, r2, #8
80041b2: 687a ldr r2, [r7, #4]
80041b4: 68d2 ldr r2, [r2, #12]
80041b6: 0912 lsrs r2, r2, #4
80041b8: 0452 lsls r2, r2, #17
80041ba: 430a orrs r2, r1
80041bc: 491f ldr r1, [pc, #124] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80041be: 4313 orrs r3, r2
80041c0: 614b str r3, [r1, #20]
80041c2: e011 b.n 80041e8 <RCCEx_PLLSAI2_Config+0x164>
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
#else
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI2CFGR,
80041c4: 4b1d ldr r3, [pc, #116] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80041c6: 695b ldr r3, [r3, #20]
80041c8: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
80041cc: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
80041d0: 687a ldr r2, [r7, #4]
80041d2: 6892 ldr r2, [r2, #8]
80041d4: 0211 lsls r1, r2, #8
80041d6: 687a ldr r2, [r7, #4]
80041d8: 6912 ldr r2, [r2, #16]
80041da: 0852 lsrs r2, r2, #1
80041dc: 3a01 subs r2, #1
80041de: 0652 lsls r2, r2, #25
80041e0: 430a orrs r2, r1
80041e2: 4916 ldr r1, [pc, #88] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80041e4: 4313 orrs r3, r2
80041e6: 614b str r3, [r1, #20]
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
}
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
__HAL_RCC_PLLSAI2_ENABLE();
80041e8: 4b14 ldr r3, [pc, #80] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80041ea: 681b ldr r3, [r3, #0]
80041ec: 4a13 ldr r2, [pc, #76] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
80041ee: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80041f2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80041f4: f7fc fa92 bl 800071c <HAL_GetTick>
80041f8: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI2 is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
80041fa: e009 b.n 8004210 <RCCEx_PLLSAI2_Config+0x18c>
{
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
80041fc: f7fc fa8e bl 800071c <HAL_GetTick>
8004200: 4602 mov r2, r0
8004202: 68bb ldr r3, [r7, #8]
8004204: 1ad3 subs r3, r2, r3
8004206: 2b02 cmp r3, #2
8004208: d902 bls.n 8004210 <RCCEx_PLLSAI2_Config+0x18c>
{
status = HAL_TIMEOUT;
800420a: 2303 movs r3, #3
800420c: 73fb strb r3, [r7, #15]
break;
800420e: e005 b.n 800421c <RCCEx_PLLSAI2_Config+0x198>
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
8004210: 4b0a ldr r3, [pc, #40] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
8004212: 681b ldr r3, [r3, #0]
8004214: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8004218: 2b00 cmp r3, #0
800421a: d0ef beq.n 80041fc <RCCEx_PLLSAI2_Config+0x178>
}
}
if(status == HAL_OK)
800421c: 7bfb ldrb r3, [r7, #15]
800421e: 2b00 cmp r3, #0
8004220: d106 bne.n 8004230 <RCCEx_PLLSAI2_Config+0x1ac>
{
/* Configure the PLLSAI2 Clock output(s) */
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
8004222: 4b06 ldr r3, [pc, #24] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
8004224: 695a ldr r2, [r3, #20]
8004226: 687b ldr r3, [r7, #4]
8004228: 695b ldr r3, [r3, #20]
800422a: 4904 ldr r1, [pc, #16] @ (800423c <RCCEx_PLLSAI2_Config+0x1b8>)
800422c: 4313 orrs r3, r2
800422e: 614b str r3, [r1, #20]
}
}
}
return status;
8004230: 7bfb ldrb r3, [r7, #15]
}
8004232: 4618 mov r0, r3
8004234: 3710 adds r7, #16
8004236: 46bd mov sp, r7
8004238: bd80 pop {r7, pc}
800423a: bf00 nop
800423c: 40021000 .word 0x40021000
08004240 <USB_CoreInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
8004240: b084 sub sp, #16
8004242: b580 push {r7, lr}
8004244: b084 sub sp, #16
8004246: af00 add r7, sp, #0
8004248: 6078 str r0, [r7, #4]
800424a: f107 001c add.w r0, r7, #28
800424e: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret;
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
8004252: 687b ldr r3, [r7, #4]
8004254: 68db ldr r3, [r3, #12]
8004256: f043 0240 orr.w r2, r3, #64 @ 0x40
800425a: 687b ldr r3, [r7, #4]
800425c: 60da str r2, [r3, #12]
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
800425e: 6878 ldr r0, [r7, #4]
8004260: f001 fa26 bl 80056b0 <USB_CoreReset>
8004264: 4603 mov r3, r0
8004266: 73fb strb r3, [r7, #15]
if (cfg.battery_charging_enable == 0U)
8004268: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
800426c: 2b00 cmp r3, #0
800426e: d106 bne.n 800427e <USB_CoreInit+0x3e>
{
/* Activate the USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
8004270: 687b ldr r3, [r7, #4]
8004272: 6b9b ldr r3, [r3, #56] @ 0x38
8004274: f443 3280 orr.w r2, r3, #65536 @ 0x10000
8004278: 687b ldr r3, [r7, #4]
800427a: 639a str r2, [r3, #56] @ 0x38
800427c: e005 b.n 800428a <USB_CoreInit+0x4a>
}
else
{
/* Deactivate the USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
800427e: 687b ldr r3, [r7, #4]
8004280: 6b9b ldr r3, [r3, #56] @ 0x38
8004282: f423 3280 bic.w r2, r3, #65536 @ 0x10000
8004286: 687b ldr r3, [r7, #4]
8004288: 639a str r2, [r3, #56] @ 0x38
}
return ret;
800428a: 7bfb ldrb r3, [r7, #15]
}
800428c: 4618 mov r0, r3
800428e: 3710 adds r7, #16
8004290: 46bd mov sp, r7
8004292: e8bd 4080 ldmia.w sp!, {r7, lr}
8004296: b004 add sp, #16
8004298: 4770 bx lr
...
0800429c <USB_SetTurnaroundTime>:
* @param hclk: AHB clock frequency
* @retval USB turnaround time In PHY Clocks number
*/
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
uint32_t hclk, uint8_t speed)
{
800429c: b480 push {r7}
800429e: b087 sub sp, #28
80042a0: af00 add r7, sp, #0
80042a2: 60f8 str r0, [r7, #12]
80042a4: 60b9 str r1, [r7, #8]
80042a6: 4613 mov r3, r2
80042a8: 71fb strb r3, [r7, #7]
/* The USBTRD is configured according to the tables below, depending on AHB frequency
used by application. In the low AHB frequency range it is used to stretch enough the USB response
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
latency to the Data FIFO */
if (speed == USBD_FS_SPEED)
80042aa: 79fb ldrb r3, [r7, #7]
80042ac: 2b02 cmp r3, #2
80042ae: d165 bne.n 800437c <USB_SetTurnaroundTime+0xe0>
{
if ((hclk >= 14200000U) && (hclk < 15000000U))
80042b0: 68bb ldr r3, [r7, #8]
80042b2: 4a3e ldr r2, [pc, #248] @ (80043ac <USB_SetTurnaroundTime+0x110>)
80042b4: 4293 cmp r3, r2
80042b6: d906 bls.n 80042c6 <USB_SetTurnaroundTime+0x2a>
80042b8: 68bb ldr r3, [r7, #8]
80042ba: 4a3d ldr r2, [pc, #244] @ (80043b0 <USB_SetTurnaroundTime+0x114>)
80042bc: 4293 cmp r3, r2
80042be: d202 bcs.n 80042c6 <USB_SetTurnaroundTime+0x2a>
{
/* hclk Clock Range between 14.2-15 MHz */
UsbTrd = 0xFU;
80042c0: 230f movs r3, #15
80042c2: 617b str r3, [r7, #20]
80042c4: e05c b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 15000000U) && (hclk < 16000000U))
80042c6: 68bb ldr r3, [r7, #8]
80042c8: 4a39 ldr r2, [pc, #228] @ (80043b0 <USB_SetTurnaroundTime+0x114>)
80042ca: 4293 cmp r3, r2
80042cc: d306 bcc.n 80042dc <USB_SetTurnaroundTime+0x40>
80042ce: 68bb ldr r3, [r7, #8]
80042d0: 4a38 ldr r2, [pc, #224] @ (80043b4 <USB_SetTurnaroundTime+0x118>)
80042d2: 4293 cmp r3, r2
80042d4: d202 bcs.n 80042dc <USB_SetTurnaroundTime+0x40>
{
/* hclk Clock Range between 15-16 MHz */
UsbTrd = 0xEU;
80042d6: 230e movs r3, #14
80042d8: 617b str r3, [r7, #20]
80042da: e051 b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 16000000U) && (hclk < 17200000U))
80042dc: 68bb ldr r3, [r7, #8]
80042de: 4a35 ldr r2, [pc, #212] @ (80043b4 <USB_SetTurnaroundTime+0x118>)
80042e0: 4293 cmp r3, r2
80042e2: d306 bcc.n 80042f2 <USB_SetTurnaroundTime+0x56>
80042e4: 68bb ldr r3, [r7, #8]
80042e6: 4a34 ldr r2, [pc, #208] @ (80043b8 <USB_SetTurnaroundTime+0x11c>)
80042e8: 4293 cmp r3, r2
80042ea: d202 bcs.n 80042f2 <USB_SetTurnaroundTime+0x56>
{
/* hclk Clock Range between 16-17.2 MHz */
UsbTrd = 0xDU;
80042ec: 230d movs r3, #13
80042ee: 617b str r3, [r7, #20]
80042f0: e046 b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 17200000U) && (hclk < 18500000U))
80042f2: 68bb ldr r3, [r7, #8]
80042f4: 4a30 ldr r2, [pc, #192] @ (80043b8 <USB_SetTurnaroundTime+0x11c>)
80042f6: 4293 cmp r3, r2
80042f8: d306 bcc.n 8004308 <USB_SetTurnaroundTime+0x6c>
80042fa: 68bb ldr r3, [r7, #8]
80042fc: 4a2f ldr r2, [pc, #188] @ (80043bc <USB_SetTurnaroundTime+0x120>)
80042fe: 4293 cmp r3, r2
8004300: d802 bhi.n 8004308 <USB_SetTurnaroundTime+0x6c>
{
/* hclk Clock Range between 17.2-18.5 MHz */
UsbTrd = 0xCU;
8004302: 230c movs r3, #12
8004304: 617b str r3, [r7, #20]
8004306: e03b b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 18500000U) && (hclk < 20000000U))
8004308: 68bb ldr r3, [r7, #8]
800430a: 4a2c ldr r2, [pc, #176] @ (80043bc <USB_SetTurnaroundTime+0x120>)
800430c: 4293 cmp r3, r2
800430e: d906 bls.n 800431e <USB_SetTurnaroundTime+0x82>
8004310: 68bb ldr r3, [r7, #8]
8004312: 4a2b ldr r2, [pc, #172] @ (80043c0 <USB_SetTurnaroundTime+0x124>)
8004314: 4293 cmp r3, r2
8004316: d802 bhi.n 800431e <USB_SetTurnaroundTime+0x82>
{
/* hclk Clock Range between 18.5-20 MHz */
UsbTrd = 0xBU;
8004318: 230b movs r3, #11
800431a: 617b str r3, [r7, #20]
800431c: e030 b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 20000000U) && (hclk < 21800000U))
800431e: 68bb ldr r3, [r7, #8]
8004320: 4a27 ldr r2, [pc, #156] @ (80043c0 <USB_SetTurnaroundTime+0x124>)
8004322: 4293 cmp r3, r2
8004324: d906 bls.n 8004334 <USB_SetTurnaroundTime+0x98>
8004326: 68bb ldr r3, [r7, #8]
8004328: 4a26 ldr r2, [pc, #152] @ (80043c4 <USB_SetTurnaroundTime+0x128>)
800432a: 4293 cmp r3, r2
800432c: d802 bhi.n 8004334 <USB_SetTurnaroundTime+0x98>
{
/* hclk Clock Range between 20-21.8 MHz */
UsbTrd = 0xAU;
800432e: 230a movs r3, #10
8004330: 617b str r3, [r7, #20]
8004332: e025 b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 21800000U) && (hclk < 24000000U))
8004334: 68bb ldr r3, [r7, #8]
8004336: 4a23 ldr r2, [pc, #140] @ (80043c4 <USB_SetTurnaroundTime+0x128>)
8004338: 4293 cmp r3, r2
800433a: d906 bls.n 800434a <USB_SetTurnaroundTime+0xae>
800433c: 68bb ldr r3, [r7, #8]
800433e: 4a22 ldr r2, [pc, #136] @ (80043c8 <USB_SetTurnaroundTime+0x12c>)
8004340: 4293 cmp r3, r2
8004342: d202 bcs.n 800434a <USB_SetTurnaroundTime+0xae>
{
/* hclk Clock Range between 21.8-24 MHz */
UsbTrd = 0x9U;
8004344: 2309 movs r3, #9
8004346: 617b str r3, [r7, #20]
8004348: e01a b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 24000000U) && (hclk < 27700000U))
800434a: 68bb ldr r3, [r7, #8]
800434c: 4a1e ldr r2, [pc, #120] @ (80043c8 <USB_SetTurnaroundTime+0x12c>)
800434e: 4293 cmp r3, r2
8004350: d306 bcc.n 8004360 <USB_SetTurnaroundTime+0xc4>
8004352: 68bb ldr r3, [r7, #8]
8004354: 4a1d ldr r2, [pc, #116] @ (80043cc <USB_SetTurnaroundTime+0x130>)
8004356: 4293 cmp r3, r2
8004358: d802 bhi.n 8004360 <USB_SetTurnaroundTime+0xc4>
{
/* hclk Clock Range between 24-27.7 MHz */
UsbTrd = 0x8U;
800435a: 2308 movs r3, #8
800435c: 617b str r3, [r7, #20]
800435e: e00f b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else if ((hclk >= 27700000U) && (hclk < 32000000U))
8004360: 68bb ldr r3, [r7, #8]
8004362: 4a1a ldr r2, [pc, #104] @ (80043cc <USB_SetTurnaroundTime+0x130>)
8004364: 4293 cmp r3, r2
8004366: d906 bls.n 8004376 <USB_SetTurnaroundTime+0xda>
8004368: 68bb ldr r3, [r7, #8]
800436a: 4a19 ldr r2, [pc, #100] @ (80043d0 <USB_SetTurnaroundTime+0x134>)
800436c: 4293 cmp r3, r2
800436e: d202 bcs.n 8004376 <USB_SetTurnaroundTime+0xda>
{
/* hclk Clock Range between 27.7-32 MHz */
UsbTrd = 0x7U;
8004370: 2307 movs r3, #7
8004372: 617b str r3, [r7, #20]
8004374: e004 b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
else /* if(hclk >= 32000000) */
{
/* hclk Clock Range between 32-200 MHz */
UsbTrd = 0x6U;
8004376: 2306 movs r3, #6
8004378: 617b str r3, [r7, #20]
800437a: e001 b.n 8004380 <USB_SetTurnaroundTime+0xe4>
}
}
else
{
UsbTrd = USBD_DEFAULT_TRDT_VALUE;
800437c: 2309 movs r3, #9
800437e: 617b str r3, [r7, #20]
}
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
8004380: 68fb ldr r3, [r7, #12]
8004382: 68db ldr r3, [r3, #12]
8004384: f423 5270 bic.w r2, r3, #15360 @ 0x3c00
8004388: 68fb ldr r3, [r7, #12]
800438a: 60da str r2, [r3, #12]
USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
800438c: 68fb ldr r3, [r7, #12]
800438e: 68da ldr r2, [r3, #12]
8004390: 697b ldr r3, [r7, #20]
8004392: 029b lsls r3, r3, #10
8004394: f403 5370 and.w r3, r3, #15360 @ 0x3c00
8004398: 431a orrs r2, r3
800439a: 68fb ldr r3, [r7, #12]
800439c: 60da str r2, [r3, #12]
return HAL_OK;
800439e: 2300 movs r3, #0
}
80043a0: 4618 mov r0, r3
80043a2: 371c adds r7, #28
80043a4: 46bd mov sp, r7
80043a6: f85d 7b04 ldr.w r7, [sp], #4
80043aa: 4770 bx lr
80043ac: 00d8acbf .word 0x00d8acbf
80043b0: 00e4e1c0 .word 0x00e4e1c0
80043b4: 00f42400 .word 0x00f42400
80043b8: 01067380 .word 0x01067380
80043bc: 011a499f .word 0x011a499f
80043c0: 01312cff .word 0x01312cff
80043c4: 014ca43f .word 0x014ca43f
80043c8: 016e3600 .word 0x016e3600
80043cc: 01a6ab1f .word 0x01a6ab1f
80043d0: 01e84800 .word 0x01e84800
080043d4 <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
80043d4: b480 push {r7}
80043d6: b083 sub sp, #12
80043d8: af00 add r7, sp, #0
80043da: 6078 str r0, [r7, #4]
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
80043dc: 687b ldr r3, [r7, #4]
80043de: 689b ldr r3, [r3, #8]
80043e0: f043 0201 orr.w r2, r3, #1
80043e4: 687b ldr r3, [r7, #4]
80043e6: 609a str r2, [r3, #8]
return HAL_OK;
80043e8: 2300 movs r3, #0
}
80043ea: 4618 mov r0, r3
80043ec: 370c adds r7, #12
80043ee: 46bd mov sp, r7
80043f0: f85d 7b04 ldr.w r7, [sp], #4
80043f4: 4770 bx lr
080043f6 <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
80043f6: b480 push {r7}
80043f8: b083 sub sp, #12
80043fa: af00 add r7, sp, #0
80043fc: 6078 str r0, [r7, #4]
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
80043fe: 687b ldr r3, [r7, #4]
8004400: 689b ldr r3, [r3, #8]
8004402: f023 0201 bic.w r2, r3, #1
8004406: 687b ldr r3, [r7, #4]
8004408: 609a str r2, [r3, #8]
return HAL_OK;
800440a: 2300 movs r3, #0
}
800440c: 4618 mov r0, r3
800440e: 370c adds r7, #12
8004410: 46bd mov sp, r7
8004412: f85d 7b04 ldr.w r7, [sp], #4
8004416: 4770 bx lr
08004418 <USB_SetCurrentMode>:
* @arg USB_DEVICE_MODE Peripheral mode
* @arg USB_HOST_MODE Host mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
{
8004418: b580 push {r7, lr}
800441a: b084 sub sp, #16
800441c: af00 add r7, sp, #0
800441e: 6078 str r0, [r7, #4]
8004420: 460b mov r3, r1
8004422: 70fb strb r3, [r7, #3]
uint32_t ms = 0U;
8004424: 2300 movs r3, #0
8004426: 60fb str r3, [r7, #12]
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
8004428: 687b ldr r3, [r7, #4]
800442a: 68db ldr r3, [r3, #12]
800442c: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
8004430: 687b ldr r3, [r7, #4]
8004432: 60da str r2, [r3, #12]
if (mode == USB_HOST_MODE)
8004434: 78fb ldrb r3, [r7, #3]
8004436: 2b01 cmp r3, #1
8004438: d115 bne.n 8004466 <USB_SetCurrentMode+0x4e>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
800443a: 687b ldr r3, [r7, #4]
800443c: 68db ldr r3, [r3, #12]
800443e: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
8004442: 687b ldr r3, [r7, #4]
8004444: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
8004446: 200a movs r0, #10
8004448: f7fc f974 bl 8000734 <HAL_Delay>
ms += 10U;
800444c: 68fb ldr r3, [r7, #12]
800444e: 330a adds r3, #10
8004450: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
8004452: 6878 ldr r0, [r7, #4]
8004454: f001 f8b3 bl 80055be <USB_GetMode>
8004458: 4603 mov r3, r0
800445a: 2b01 cmp r3, #1
800445c: d01e beq.n 800449c <USB_SetCurrentMode+0x84>
800445e: 68fb ldr r3, [r7, #12]
8004460: 2bc7 cmp r3, #199 @ 0xc7
8004462: d9f0 bls.n 8004446 <USB_SetCurrentMode+0x2e>
8004464: e01a b.n 800449c <USB_SetCurrentMode+0x84>
}
else if (mode == USB_DEVICE_MODE)
8004466: 78fb ldrb r3, [r7, #3]
8004468: 2b00 cmp r3, #0
800446a: d115 bne.n 8004498 <USB_SetCurrentMode+0x80>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
800446c: 687b ldr r3, [r7, #4]
800446e: 68db ldr r3, [r3, #12]
8004470: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
8004474: 687b ldr r3, [r7, #4]
8004476: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
8004478: 200a movs r0, #10
800447a: f7fc f95b bl 8000734 <HAL_Delay>
ms += 10U;
800447e: 68fb ldr r3, [r7, #12]
8004480: 330a adds r3, #10
8004482: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
8004484: 6878 ldr r0, [r7, #4]
8004486: f001 f89a bl 80055be <USB_GetMode>
800448a: 4603 mov r3, r0
800448c: 2b00 cmp r3, #0
800448e: d005 beq.n 800449c <USB_SetCurrentMode+0x84>
8004490: 68fb ldr r3, [r7, #12]
8004492: 2bc7 cmp r3, #199 @ 0xc7
8004494: d9f0 bls.n 8004478 <USB_SetCurrentMode+0x60>
8004496: e001 b.n 800449c <USB_SetCurrentMode+0x84>
}
else
{
return HAL_ERROR;
8004498: 2301 movs r3, #1
800449a: e005 b.n 80044a8 <USB_SetCurrentMode+0x90>
}
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
800449c: 68fb ldr r3, [r7, #12]
800449e: 2bc8 cmp r3, #200 @ 0xc8
80044a0: d101 bne.n 80044a6 <USB_SetCurrentMode+0x8e>
{
return HAL_ERROR;
80044a2: 2301 movs r3, #1
80044a4: e000 b.n 80044a8 <USB_SetCurrentMode+0x90>
}
return HAL_OK;
80044a6: 2300 movs r3, #0
}
80044a8: 4618 mov r0, r3
80044aa: 3710 adds r7, #16
80044ac: 46bd mov sp, r7
80044ae: bd80 pop {r7, pc}
080044b0 <USB_DevInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
80044b0: b084 sub sp, #16
80044b2: b580 push {r7, lr}
80044b4: b086 sub sp, #24
80044b6: af00 add r7, sp, #0
80044b8: 6078 str r0, [r7, #4]
80044ba: f107 0024 add.w r0, r7, #36 @ 0x24
80044be: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret = HAL_OK;
80044c2: 2300 movs r3, #0
80044c4: 75fb strb r3, [r7, #23]
uint32_t USBx_BASE = (uint32_t)USBx;
80044c6: 687b ldr r3, [r7, #4]
80044c8: 60fb str r3, [r7, #12]
uint32_t i;
for (i = 0U; i < 15U; i++)
80044ca: 2300 movs r3, #0
80044cc: 613b str r3, [r7, #16]
80044ce: e009 b.n 80044e4 <USB_DevInit+0x34>
{
USBx->DIEPTXF[i] = 0U;
80044d0: 687a ldr r2, [r7, #4]
80044d2: 693b ldr r3, [r7, #16]
80044d4: 3340 adds r3, #64 @ 0x40
80044d6: 009b lsls r3, r3, #2
80044d8: 4413 add r3, r2
80044da: 2200 movs r2, #0
80044dc: 605a str r2, [r3, #4]
for (i = 0U; i < 15U; i++)
80044de: 693b ldr r3, [r7, #16]
80044e0: 3301 adds r3, #1
80044e2: 613b str r3, [r7, #16]
80044e4: 693b ldr r3, [r7, #16]
80044e6: 2b0e cmp r3, #14
80044e8: d9f2 bls.n 80044d0 <USB_DevInit+0x20>
}
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
80044ea: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
80044ee: 2b00 cmp r3, #0
80044f0: d11c bne.n 800452c <USB_DevInit+0x7c>
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
80044f2: 68fb ldr r3, [r7, #12]
80044f4: f503 6300 add.w r3, r3, #2048 @ 0x800
80044f8: 685b ldr r3, [r3, #4]
80044fa: 68fa ldr r2, [r7, #12]
80044fc: f502 6200 add.w r2, r2, #2048 @ 0x800
8004500: f043 0302 orr.w r3, r3, #2
8004504: 6053 str r3, [r2, #4]
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
8004506: 687b ldr r3, [r7, #4]
8004508: 6b9b ldr r3, [r3, #56] @ 0x38
800450a: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
800450e: 687b ldr r3, [r7, #4]
8004510: 639a str r2, [r3, #56] @ 0x38
/* B-peripheral session valid override enable */
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
8004512: 687b ldr r3, [r7, #4]
8004514: 681b ldr r3, [r3, #0]
8004516: f043 0240 orr.w r2, r3, #64 @ 0x40
800451a: 687b ldr r3, [r7, #4]
800451c: 601a str r2, [r3, #0]
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
800451e: 687b ldr r3, [r7, #4]
8004520: 681b ldr r3, [r3, #0]
8004522: f043 0280 orr.w r2, r3, #128 @ 0x80
8004526: 687b ldr r3, [r7, #4]
8004528: 601a str r2, [r3, #0]
800452a: e005 b.n 8004538 <USB_DevInit+0x88>
}
else
{
/* Enable HW VBUS sensing */
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
800452c: 687b ldr r3, [r7, #4]
800452e: 6b9b ldr r3, [r3, #56] @ 0x38
8004530: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
8004534: 687b ldr r3, [r7, #4]
8004536: 639a str r2, [r3, #56] @ 0x38
}
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
8004538: 68fb ldr r3, [r7, #12]
800453a: f503 6360 add.w r3, r3, #3584 @ 0xe00
800453e: 461a mov r2, r3
8004540: 2300 movs r3, #0
8004542: 6013 str r3, [r2, #0]
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
8004544: 2103 movs r1, #3
8004546: 6878 ldr r0, [r7, #4]
8004548: f000 f95a bl 8004800 <USB_SetDevSpeed>
/* Flush the FIFOs */
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
800454c: 2110 movs r1, #16
800454e: 6878 ldr r0, [r7, #4]
8004550: f000 f8f6 bl 8004740 <USB_FlushTxFifo>
8004554: 4603 mov r3, r0
8004556: 2b00 cmp r3, #0
8004558: d001 beq.n 800455e <USB_DevInit+0xae>
{
ret = HAL_ERROR;
800455a: 2301 movs r3, #1
800455c: 75fb strb r3, [r7, #23]
}
if (USB_FlushRxFifo(USBx) != HAL_OK)
800455e: 6878 ldr r0, [r7, #4]
8004560: f000 f920 bl 80047a4 <USB_FlushRxFifo>
8004564: 4603 mov r3, r0
8004566: 2b00 cmp r3, #0
8004568: d001 beq.n 800456e <USB_DevInit+0xbe>
{
ret = HAL_ERROR;
800456a: 2301 movs r3, #1
800456c: 75fb strb r3, [r7, #23]
}
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0U;
800456e: 68fb ldr r3, [r7, #12]
8004570: f503 6300 add.w r3, r3, #2048 @ 0x800
8004574: 461a mov r2, r3
8004576: 2300 movs r3, #0
8004578: 6113 str r3, [r2, #16]
USBx_DEVICE->DOEPMSK = 0U;
800457a: 68fb ldr r3, [r7, #12]
800457c: f503 6300 add.w r3, r3, #2048 @ 0x800
8004580: 461a mov r2, r3
8004582: 2300 movs r3, #0
8004584: 6153 str r3, [r2, #20]
USBx_DEVICE->DAINTMSK = 0U;
8004586: 68fb ldr r3, [r7, #12]
8004588: f503 6300 add.w r3, r3, #2048 @ 0x800
800458c: 461a mov r2, r3
800458e: 2300 movs r3, #0
8004590: 61d3 str r3, [r2, #28]
for (i = 0U; i < cfg.dev_endpoints; i++)
8004592: 2300 movs r3, #0
8004594: 613b str r3, [r7, #16]
8004596: e043 b.n 8004620 <USB_DevInit+0x170>
{
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
8004598: 693b ldr r3, [r7, #16]
800459a: 015a lsls r2, r3, #5
800459c: 68fb ldr r3, [r7, #12]
800459e: 4413 add r3, r2
80045a0: f503 6310 add.w r3, r3, #2304 @ 0x900
80045a4: 681b ldr r3, [r3, #0]
80045a6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80045aa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80045ae: d118 bne.n 80045e2 <USB_DevInit+0x132>
{
if (i == 0U)
80045b0: 693b ldr r3, [r7, #16]
80045b2: 2b00 cmp r3, #0
80045b4: d10a bne.n 80045cc <USB_DevInit+0x11c>
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
80045b6: 693b ldr r3, [r7, #16]
80045b8: 015a lsls r2, r3, #5
80045ba: 68fb ldr r3, [r7, #12]
80045bc: 4413 add r3, r2
80045be: f503 6310 add.w r3, r3, #2304 @ 0x900
80045c2: 461a mov r2, r3
80045c4: f04f 6300 mov.w r3, #134217728 @ 0x8000000
80045c8: 6013 str r3, [r2, #0]
80045ca: e013 b.n 80045f4 <USB_DevInit+0x144>
}
else
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
80045cc: 693b ldr r3, [r7, #16]
80045ce: 015a lsls r2, r3, #5
80045d0: 68fb ldr r3, [r7, #12]
80045d2: 4413 add r3, r2
80045d4: f503 6310 add.w r3, r3, #2304 @ 0x900
80045d8: 461a mov r2, r3
80045da: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
80045de: 6013 str r3, [r2, #0]
80045e0: e008 b.n 80045f4 <USB_DevInit+0x144>
}
}
else
{
USBx_INEP(i)->DIEPCTL = 0U;
80045e2: 693b ldr r3, [r7, #16]
80045e4: 015a lsls r2, r3, #5
80045e6: 68fb ldr r3, [r7, #12]
80045e8: 4413 add r3, r2
80045ea: f503 6310 add.w r3, r3, #2304 @ 0x900
80045ee: 461a mov r2, r3
80045f0: 2300 movs r3, #0
80045f2: 6013 str r3, [r2, #0]
}
USBx_INEP(i)->DIEPTSIZ = 0U;
80045f4: 693b ldr r3, [r7, #16]
80045f6: 015a lsls r2, r3, #5
80045f8: 68fb ldr r3, [r7, #12]
80045fa: 4413 add r3, r2
80045fc: f503 6310 add.w r3, r3, #2304 @ 0x900
8004600: 461a mov r2, r3
8004602: 2300 movs r3, #0
8004604: 6113 str r3, [r2, #16]
USBx_INEP(i)->DIEPINT = 0xFB7FU;
8004606: 693b ldr r3, [r7, #16]
8004608: 015a lsls r2, r3, #5
800460a: 68fb ldr r3, [r7, #12]
800460c: 4413 add r3, r2
800460e: f503 6310 add.w r3, r3, #2304 @ 0x900
8004612: 461a mov r2, r3
8004614: f64f 337f movw r3, #64383 @ 0xfb7f
8004618: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
800461a: 693b ldr r3, [r7, #16]
800461c: 3301 adds r3, #1
800461e: 613b str r3, [r7, #16]
8004620: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8004624: 461a mov r2, r3
8004626: 693b ldr r3, [r7, #16]
8004628: 4293 cmp r3, r2
800462a: d3b5 bcc.n 8004598 <USB_DevInit+0xe8>
}
for (i = 0U; i < cfg.dev_endpoints; i++)
800462c: 2300 movs r3, #0
800462e: 613b str r3, [r7, #16]
8004630: e043 b.n 80046ba <USB_DevInit+0x20a>
{
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
8004632: 693b ldr r3, [r7, #16]
8004634: 015a lsls r2, r3, #5
8004636: 68fb ldr r3, [r7, #12]
8004638: 4413 add r3, r2
800463a: f503 6330 add.w r3, r3, #2816 @ 0xb00
800463e: 681b ldr r3, [r3, #0]
8004640: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8004644: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8004648: d118 bne.n 800467c <USB_DevInit+0x1cc>
{
if (i == 0U)
800464a: 693b ldr r3, [r7, #16]
800464c: 2b00 cmp r3, #0
800464e: d10a bne.n 8004666 <USB_DevInit+0x1b6>
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
8004650: 693b ldr r3, [r7, #16]
8004652: 015a lsls r2, r3, #5
8004654: 68fb ldr r3, [r7, #12]
8004656: 4413 add r3, r2
8004658: f503 6330 add.w r3, r3, #2816 @ 0xb00
800465c: 461a mov r2, r3
800465e: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8004662: 6013 str r3, [r2, #0]
8004664: e013 b.n 800468e <USB_DevInit+0x1de>
}
else
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
8004666: 693b ldr r3, [r7, #16]
8004668: 015a lsls r2, r3, #5
800466a: 68fb ldr r3, [r7, #12]
800466c: 4413 add r3, r2
800466e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004672: 461a mov r2, r3
8004674: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
8004678: 6013 str r3, [r2, #0]
800467a: e008 b.n 800468e <USB_DevInit+0x1de>
}
}
else
{
USBx_OUTEP(i)->DOEPCTL = 0U;
800467c: 693b ldr r3, [r7, #16]
800467e: 015a lsls r2, r3, #5
8004680: 68fb ldr r3, [r7, #12]
8004682: 4413 add r3, r2
8004684: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004688: 461a mov r2, r3
800468a: 2300 movs r3, #0
800468c: 6013 str r3, [r2, #0]
}
USBx_OUTEP(i)->DOEPTSIZ = 0U;
800468e: 693b ldr r3, [r7, #16]
8004690: 015a lsls r2, r3, #5
8004692: 68fb ldr r3, [r7, #12]
8004694: 4413 add r3, r2
8004696: f503 6330 add.w r3, r3, #2816 @ 0xb00
800469a: 461a mov r2, r3
800469c: 2300 movs r3, #0
800469e: 6113 str r3, [r2, #16]
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
80046a0: 693b ldr r3, [r7, #16]
80046a2: 015a lsls r2, r3, #5
80046a4: 68fb ldr r3, [r7, #12]
80046a6: 4413 add r3, r2
80046a8: f503 6330 add.w r3, r3, #2816 @ 0xb00
80046ac: 461a mov r2, r3
80046ae: f64f 337f movw r3, #64383 @ 0xfb7f
80046b2: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
80046b4: 693b ldr r3, [r7, #16]
80046b6: 3301 adds r3, #1
80046b8: 613b str r3, [r7, #16]
80046ba: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
80046be: 461a mov r2, r3
80046c0: 693b ldr r3, [r7, #16]
80046c2: 4293 cmp r3, r2
80046c4: d3b5 bcc.n 8004632 <USB_DevInit+0x182>
}
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
80046c6: 68fb ldr r3, [r7, #12]
80046c8: f503 6300 add.w r3, r3, #2048 @ 0x800
80046cc: 691b ldr r3, [r3, #16]
80046ce: 68fa ldr r2, [r7, #12]
80046d0: f502 6200 add.w r2, r2, #2048 @ 0x800
80046d4: f423 7380 bic.w r3, r3, #256 @ 0x100
80046d8: 6113 str r3, [r2, #16]
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
80046da: 687b ldr r3, [r7, #4]
80046dc: 2200 movs r2, #0
80046de: 619a str r2, [r3, #24]
/* Clear any pending interrupts */
USBx->GINTSTS = 0xBFFFFFFFU;
80046e0: 687b ldr r3, [r7, #4]
80046e2: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
80046e6: 615a str r2, [r3, #20]
/* Enable the common interrupts */
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
80046e8: 687b ldr r3, [r7, #4]
80046ea: 699b ldr r3, [r3, #24]
80046ec: f043 0210 orr.w r2, r3, #16
80046f0: 687b ldr r3, [r7, #4]
80046f2: 619a str r2, [r3, #24]
/* Enable interrupts matching to the Device mode ONLY */
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
80046f4: 687b ldr r3, [r7, #4]
80046f6: 699a ldr r2, [r3, #24]
80046f8: 4b10 ldr r3, [pc, #64] @ (800473c <USB_DevInit+0x28c>)
80046fa: 4313 orrs r3, r2
80046fc: 687a ldr r2, [r7, #4]
80046fe: 6193 str r3, [r2, #24]
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
if (cfg.Sof_enable != 0U)
8004700: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
8004704: 2b00 cmp r3, #0
8004706: d005 beq.n 8004714 <USB_DevInit+0x264>
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
8004708: 687b ldr r3, [r7, #4]
800470a: 699b ldr r3, [r3, #24]
800470c: f043 0208 orr.w r2, r3, #8
8004710: 687b ldr r3, [r7, #4]
8004712: 619a str r2, [r3, #24]
}
if (cfg.vbus_sensing_enable == 1U)
8004714: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
8004718: 2b01 cmp r3, #1
800471a: d107 bne.n 800472c <USB_DevInit+0x27c>
{
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
800471c: 687b ldr r3, [r7, #4]
800471e: 699b ldr r3, [r3, #24]
8004720: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8004724: f043 0304 orr.w r3, r3, #4
8004728: 687a ldr r2, [r7, #4]
800472a: 6193 str r3, [r2, #24]
}
return ret;
800472c: 7dfb ldrb r3, [r7, #23]
}
800472e: 4618 mov r0, r3
8004730: 3718 adds r7, #24
8004732: 46bd mov sp, r7
8004734: e8bd 4080 ldmia.w sp!, {r7, lr}
8004738: b004 add sp, #16
800473a: 4770 bx lr
800473c: 803c3800 .word 0x803c3800
08004740 <USB_FlushTxFifo>:
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
8004740: b480 push {r7}
8004742: b085 sub sp, #20
8004744: af00 add r7, sp, #0
8004746: 6078 str r0, [r7, #4]
8004748: 6039 str r1, [r7, #0]
__IO uint32_t count = 0U;
800474a: 2300 movs r3, #0
800474c: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
800474e: 68fb ldr r3, [r7, #12]
8004750: 3301 adds r3, #1
8004752: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8004754: 68fb ldr r3, [r7, #12]
8004756: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
800475a: d901 bls.n 8004760 <USB_FlushTxFifo+0x20>
{
return HAL_TIMEOUT;
800475c: 2303 movs r3, #3
800475e: e01b b.n 8004798 <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8004760: 687b ldr r3, [r7, #4]
8004762: 691b ldr r3, [r3, #16]
8004764: 2b00 cmp r3, #0
8004766: daf2 bge.n 800474e <USB_FlushTxFifo+0xe>
/* Flush TX Fifo */
count = 0U;
8004768: 2300 movs r3, #0
800476a: 60fb str r3, [r7, #12]
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
800476c: 683b ldr r3, [r7, #0]
800476e: 019b lsls r3, r3, #6
8004770: f043 0220 orr.w r2, r3, #32
8004774: 687b ldr r3, [r7, #4]
8004776: 611a str r2, [r3, #16]
do
{
count++;
8004778: 68fb ldr r3, [r7, #12]
800477a: 3301 adds r3, #1
800477c: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
800477e: 68fb ldr r3, [r7, #12]
8004780: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8004784: d901 bls.n 800478a <USB_FlushTxFifo+0x4a>
{
return HAL_TIMEOUT;
8004786: 2303 movs r3, #3
8004788: e006 b.n 8004798 <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
800478a: 687b ldr r3, [r7, #4]
800478c: 691b ldr r3, [r3, #16]
800478e: f003 0320 and.w r3, r3, #32
8004792: 2b20 cmp r3, #32
8004794: d0f0 beq.n 8004778 <USB_FlushTxFifo+0x38>
return HAL_OK;
8004796: 2300 movs r3, #0
}
8004798: 4618 mov r0, r3
800479a: 3714 adds r7, #20
800479c: 46bd mov sp, r7
800479e: f85d 7b04 ldr.w r7, [sp], #4
80047a2: 4770 bx lr
080047a4 <USB_FlushRxFifo>:
* @brief USB_FlushRxFifo Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
80047a4: b480 push {r7}
80047a6: b085 sub sp, #20
80047a8: af00 add r7, sp, #0
80047aa: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
80047ac: 2300 movs r3, #0
80047ae: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
80047b0: 68fb ldr r3, [r7, #12]
80047b2: 3301 adds r3, #1
80047b4: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
80047b6: 68fb ldr r3, [r7, #12]
80047b8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
80047bc: d901 bls.n 80047c2 <USB_FlushRxFifo+0x1e>
{
return HAL_TIMEOUT;
80047be: 2303 movs r3, #3
80047c0: e018 b.n 80047f4 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
80047c2: 687b ldr r3, [r7, #4]
80047c4: 691b ldr r3, [r3, #16]
80047c6: 2b00 cmp r3, #0
80047c8: daf2 bge.n 80047b0 <USB_FlushRxFifo+0xc>
/* Flush RX Fifo */
count = 0U;
80047ca: 2300 movs r3, #0
80047cc: 60fb str r3, [r7, #12]
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
80047ce: 687b ldr r3, [r7, #4]
80047d0: 2210 movs r2, #16
80047d2: 611a str r2, [r3, #16]
do
{
count++;
80047d4: 68fb ldr r3, [r7, #12]
80047d6: 3301 adds r3, #1
80047d8: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
80047da: 68fb ldr r3, [r7, #12]
80047dc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
80047e0: d901 bls.n 80047e6 <USB_FlushRxFifo+0x42>
{
return HAL_TIMEOUT;
80047e2: 2303 movs r3, #3
80047e4: e006 b.n 80047f4 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
80047e6: 687b ldr r3, [r7, #4]
80047e8: 691b ldr r3, [r3, #16]
80047ea: f003 0310 and.w r3, r3, #16
80047ee: 2b10 cmp r3, #16
80047f0: d0f0 beq.n 80047d4 <USB_FlushRxFifo+0x30>
return HAL_OK;
80047f2: 2300 movs r3, #0
}
80047f4: 4618 mov r0, r3
80047f6: 3714 adds r7, #20
80047f8: 46bd mov sp, r7
80047fa: f85d 7b04 ldr.w r7, [sp], #4
80047fe: 4770 bx lr
08004800 <USB_SetDevSpeed>:
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
8004800: b480 push {r7}
8004802: b085 sub sp, #20
8004804: af00 add r7, sp, #0
8004806: 6078 str r0, [r7, #4]
8004808: 460b mov r3, r1
800480a: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
800480c: 687b ldr r3, [r7, #4]
800480e: 60fb str r3, [r7, #12]
USBx_DEVICE->DCFG |= speed;
8004810: 68fb ldr r3, [r7, #12]
8004812: f503 6300 add.w r3, r3, #2048 @ 0x800
8004816: 681a ldr r2, [r3, #0]
8004818: 78fb ldrb r3, [r7, #3]
800481a: 68f9 ldr r1, [r7, #12]
800481c: f501 6100 add.w r1, r1, #2048 @ 0x800
8004820: 4313 orrs r3, r2
8004822: 600b str r3, [r1, #0]
return HAL_OK;
8004824: 2300 movs r3, #0
}
8004826: 4618 mov r0, r3
8004828: 3714 adds r7, #20
800482a: 46bd mov sp, r7
800482c: f85d 7b04 ldr.w r7, [sp], #4
8004830: 4770 bx lr
08004832 <USB_GetDevSpeed>:
* @retval speed device speed
* This parameter can be one of these values:
* @arg USBD_FS_SPEED: Full speed mode
*/
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
{
8004832: b480 push {r7}
8004834: b087 sub sp, #28
8004836: af00 add r7, sp, #0
8004838: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
800483a: 687b ldr r3, [r7, #4]
800483c: 613b str r3, [r7, #16]
uint8_t speed;
uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
800483e: 693b ldr r3, [r7, #16]
8004840: f503 6300 add.w r3, r3, #2048 @ 0x800
8004844: 689b ldr r3, [r3, #8]
8004846: f003 0306 and.w r3, r3, #6
800484a: 60fb str r3, [r7, #12]
if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
800484c: 68fb ldr r3, [r7, #12]
800484e: 2b02 cmp r3, #2
8004850: d002 beq.n 8004858 <USB_GetDevSpeed+0x26>
8004852: 68fb ldr r3, [r7, #12]
8004854: 2b06 cmp r3, #6
8004856: d102 bne.n 800485e <USB_GetDevSpeed+0x2c>
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
{
speed = USBD_FS_SPEED;
8004858: 2302 movs r3, #2
800485a: 75fb strb r3, [r7, #23]
800485c: e001 b.n 8004862 <USB_GetDevSpeed+0x30>
}
else
{
speed = 0xFU;
800485e: 230f movs r3, #15
8004860: 75fb strb r3, [r7, #23]
}
return speed;
8004862: 7dfb ldrb r3, [r7, #23]
}
8004864: 4618 mov r0, r3
8004866: 371c adds r7, #28
8004868: 46bd mov sp, r7
800486a: f85d 7b04 ldr.w r7, [sp], #4
800486e: 4770 bx lr
08004870 <USB_ActivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
8004870: b480 push {r7}
8004872: b085 sub sp, #20
8004874: af00 add r7, sp, #0
8004876: 6078 str r0, [r7, #4]
8004878: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
800487a: 687b ldr r3, [r7, #4]
800487c: 60fb str r3, [r7, #12]
uint32_t epnum = (uint32_t)ep->num;
800487e: 683b ldr r3, [r7, #0]
8004880: 781b ldrb r3, [r3, #0]
8004882: 60bb str r3, [r7, #8]
if (ep->is_in == 1U)
8004884: 683b ldr r3, [r7, #0]
8004886: 785b ldrb r3, [r3, #1]
8004888: 2b01 cmp r3, #1
800488a: d13a bne.n 8004902 <USB_ActivateEndpoint+0x92>
{
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
800488c: 68fb ldr r3, [r7, #12]
800488e: f503 6300 add.w r3, r3, #2048 @ 0x800
8004892: 69da ldr r2, [r3, #28]
8004894: 683b ldr r3, [r7, #0]
8004896: 781b ldrb r3, [r3, #0]
8004898: f003 030f and.w r3, r3, #15
800489c: 2101 movs r1, #1
800489e: fa01 f303 lsl.w r3, r1, r3
80048a2: b29b uxth r3, r3
80048a4: 68f9 ldr r1, [r7, #12]
80048a6: f501 6100 add.w r1, r1, #2048 @ 0x800
80048aa: 4313 orrs r3, r2
80048ac: 61cb str r3, [r1, #28]
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
80048ae: 68bb ldr r3, [r7, #8]
80048b0: 015a lsls r2, r3, #5
80048b2: 68fb ldr r3, [r7, #12]
80048b4: 4413 add r3, r2
80048b6: f503 6310 add.w r3, r3, #2304 @ 0x900
80048ba: 681b ldr r3, [r3, #0]
80048bc: f403 4300 and.w r3, r3, #32768 @ 0x8000
80048c0: 2b00 cmp r3, #0
80048c2: d155 bne.n 8004970 <USB_ActivateEndpoint+0x100>
{
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
80048c4: 68bb ldr r3, [r7, #8]
80048c6: 015a lsls r2, r3, #5
80048c8: 68fb ldr r3, [r7, #12]
80048ca: 4413 add r3, r2
80048cc: f503 6310 add.w r3, r3, #2304 @ 0x900
80048d0: 681a ldr r2, [r3, #0]
80048d2: 683b ldr r3, [r7, #0]
80048d4: 689b ldr r3, [r3, #8]
80048d6: f3c3 010a ubfx r1, r3, #0, #11
((uint32_t)ep->type << 18) | (epnum << 22) |
80048da: 683b ldr r3, [r7, #0]
80048dc: 791b ldrb r3, [r3, #4]
80048de: 049b lsls r3, r3, #18
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
80048e0: 4319 orrs r1, r3
((uint32_t)ep->type << 18) | (epnum << 22) |
80048e2: 68bb ldr r3, [r7, #8]
80048e4: 059b lsls r3, r3, #22
80048e6: 430b orrs r3, r1
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
80048e8: 4313 orrs r3, r2
80048ea: 68ba ldr r2, [r7, #8]
80048ec: 0151 lsls r1, r2, #5
80048ee: 68fa ldr r2, [r7, #12]
80048f0: 440a add r2, r1
80048f2: f502 6210 add.w r2, r2, #2304 @ 0x900
80048f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80048fa: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80048fe: 6013 str r3, [r2, #0]
8004900: e036 b.n 8004970 <USB_ActivateEndpoint+0x100>
USB_OTG_DIEPCTL_USBAEP;
}
}
else
{
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
8004902: 68fb ldr r3, [r7, #12]
8004904: f503 6300 add.w r3, r3, #2048 @ 0x800
8004908: 69da ldr r2, [r3, #28]
800490a: 683b ldr r3, [r7, #0]
800490c: 781b ldrb r3, [r3, #0]
800490e: f003 030f and.w r3, r3, #15
8004912: 2101 movs r1, #1
8004914: fa01 f303 lsl.w r3, r1, r3
8004918: 041b lsls r3, r3, #16
800491a: 68f9 ldr r1, [r7, #12]
800491c: f501 6100 add.w r1, r1, #2048 @ 0x800
8004920: 4313 orrs r3, r2
8004922: 61cb str r3, [r1, #28]
if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
8004924: 68bb ldr r3, [r7, #8]
8004926: 015a lsls r2, r3, #5
8004928: 68fb ldr r3, [r7, #12]
800492a: 4413 add r3, r2
800492c: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004930: 681b ldr r3, [r3, #0]
8004932: f403 4300 and.w r3, r3, #32768 @ 0x8000
8004936: 2b00 cmp r3, #0
8004938: d11a bne.n 8004970 <USB_ActivateEndpoint+0x100>
{
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
800493a: 68bb ldr r3, [r7, #8]
800493c: 015a lsls r2, r3, #5
800493e: 68fb ldr r3, [r7, #12]
8004940: 4413 add r3, r2
8004942: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004946: 681a ldr r2, [r3, #0]
8004948: 683b ldr r3, [r7, #0]
800494a: 689b ldr r3, [r3, #8]
800494c: f3c3 010a ubfx r1, r3, #0, #11
((uint32_t)ep->type << 18) |
8004950: 683b ldr r3, [r7, #0]
8004952: 791b ldrb r3, [r3, #4]
8004954: 049b lsls r3, r3, #18
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
8004956: 430b orrs r3, r1
8004958: 4313 orrs r3, r2
800495a: 68ba ldr r2, [r7, #8]
800495c: 0151 lsls r1, r2, #5
800495e: 68fa ldr r2, [r7, #12]
8004960: 440a add r2, r1
8004962: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004966: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800496a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800496e: 6013 str r3, [r2, #0]
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DOEPCTL_USBAEP;
}
}
return HAL_OK;
8004970: 2300 movs r3, #0
}
8004972: 4618 mov r0, r3
8004974: 3714 adds r7, #20
8004976: 46bd mov sp, r7
8004978: f85d 7b04 ldr.w r7, [sp], #4
800497c: 4770 bx lr
...
08004980 <USB_DeactivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
8004980: b480 push {r7}
8004982: b085 sub sp, #20
8004984: af00 add r7, sp, #0
8004986: 6078 str r0, [r7, #4]
8004988: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
800498a: 687b ldr r3, [r7, #4]
800498c: 60fb str r3, [r7, #12]
uint32_t epnum = (uint32_t)ep->num;
800498e: 683b ldr r3, [r7, #0]
8004990: 781b ldrb r3, [r3, #0]
8004992: 60bb str r3, [r7, #8]
/* Read DEPCTLn register */
if (ep->is_in == 1U)
8004994: 683b ldr r3, [r7, #0]
8004996: 785b ldrb r3, [r3, #1]
8004998: 2b01 cmp r3, #1
800499a: d161 bne.n 8004a60 <USB_DeactivateEndpoint+0xe0>
{
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
800499c: 68bb ldr r3, [r7, #8]
800499e: 015a lsls r2, r3, #5
80049a0: 68fb ldr r3, [r7, #12]
80049a2: 4413 add r3, r2
80049a4: f503 6310 add.w r3, r3, #2304 @ 0x900
80049a8: 681b ldr r3, [r3, #0]
80049aa: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80049ae: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80049b2: d11f bne.n 80049f4 <USB_DeactivateEndpoint+0x74>
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
80049b4: 68bb ldr r3, [r7, #8]
80049b6: 015a lsls r2, r3, #5
80049b8: 68fb ldr r3, [r7, #12]
80049ba: 4413 add r3, r2
80049bc: f503 6310 add.w r3, r3, #2304 @ 0x900
80049c0: 681b ldr r3, [r3, #0]
80049c2: 68ba ldr r2, [r7, #8]
80049c4: 0151 lsls r1, r2, #5
80049c6: 68fa ldr r2, [r7, #12]
80049c8: 440a add r2, r1
80049ca: f502 6210 add.w r2, r2, #2304 @ 0x900
80049ce: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
80049d2: 6013 str r3, [r2, #0]
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
80049d4: 68bb ldr r3, [r7, #8]
80049d6: 015a lsls r2, r3, #5
80049d8: 68fb ldr r3, [r7, #12]
80049da: 4413 add r3, r2
80049dc: f503 6310 add.w r3, r3, #2304 @ 0x900
80049e0: 681b ldr r3, [r3, #0]
80049e2: 68ba ldr r2, [r7, #8]
80049e4: 0151 lsls r1, r2, #5
80049e6: 68fa ldr r2, [r7, #12]
80049e8: 440a add r2, r1
80049ea: f502 6210 add.w r2, r2, #2304 @ 0x900
80049ee: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
80049f2: 6013 str r3, [r2, #0]
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
80049f4: 68fb ldr r3, [r7, #12]
80049f6: f503 6300 add.w r3, r3, #2048 @ 0x800
80049fa: 6bda ldr r2, [r3, #60] @ 0x3c
80049fc: 683b ldr r3, [r7, #0]
80049fe: 781b ldrb r3, [r3, #0]
8004a00: f003 030f and.w r3, r3, #15
8004a04: 2101 movs r1, #1
8004a06: fa01 f303 lsl.w r3, r1, r3
8004a0a: b29b uxth r3, r3
8004a0c: 43db mvns r3, r3
8004a0e: 68f9 ldr r1, [r7, #12]
8004a10: f501 6100 add.w r1, r1, #2048 @ 0x800
8004a14: 4013 ands r3, r2
8004a16: 63cb str r3, [r1, #60] @ 0x3c
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
8004a18: 68fb ldr r3, [r7, #12]
8004a1a: f503 6300 add.w r3, r3, #2048 @ 0x800
8004a1e: 69da ldr r2, [r3, #28]
8004a20: 683b ldr r3, [r7, #0]
8004a22: 781b ldrb r3, [r3, #0]
8004a24: f003 030f and.w r3, r3, #15
8004a28: 2101 movs r1, #1
8004a2a: fa01 f303 lsl.w r3, r1, r3
8004a2e: b29b uxth r3, r3
8004a30: 43db mvns r3, r3
8004a32: 68f9 ldr r1, [r7, #12]
8004a34: f501 6100 add.w r1, r1, #2048 @ 0x800
8004a38: 4013 ands r3, r2
8004a3a: 61cb str r3, [r1, #28]
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
8004a3c: 68bb ldr r3, [r7, #8]
8004a3e: 015a lsls r2, r3, #5
8004a40: 68fb ldr r3, [r7, #12]
8004a42: 4413 add r3, r2
8004a44: f503 6310 add.w r3, r3, #2304 @ 0x900
8004a48: 681a ldr r2, [r3, #0]
8004a4a: 68bb ldr r3, [r7, #8]
8004a4c: 0159 lsls r1, r3, #5
8004a4e: 68fb ldr r3, [r7, #12]
8004a50: 440b add r3, r1
8004a52: f503 6310 add.w r3, r3, #2304 @ 0x900
8004a56: 4619 mov r1, r3
8004a58: 4b35 ldr r3, [pc, #212] @ (8004b30 <USB_DeactivateEndpoint+0x1b0>)
8004a5a: 4013 ands r3, r2
8004a5c: 600b str r3, [r1, #0]
8004a5e: e060 b.n 8004b22 <USB_DeactivateEndpoint+0x1a2>
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DIEPCTL_EPTYP);
}
else
{
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
8004a60: 68bb ldr r3, [r7, #8]
8004a62: 015a lsls r2, r3, #5
8004a64: 68fb ldr r3, [r7, #12]
8004a66: 4413 add r3, r2
8004a68: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004a6c: 681b ldr r3, [r3, #0]
8004a6e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8004a72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8004a76: d11f bne.n 8004ab8 <USB_DeactivateEndpoint+0x138>
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
8004a78: 68bb ldr r3, [r7, #8]
8004a7a: 015a lsls r2, r3, #5
8004a7c: 68fb ldr r3, [r7, #12]
8004a7e: 4413 add r3, r2
8004a80: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004a84: 681b ldr r3, [r3, #0]
8004a86: 68ba ldr r2, [r7, #8]
8004a88: 0151 lsls r1, r2, #5
8004a8a: 68fa ldr r2, [r7, #12]
8004a8c: 440a add r2, r1
8004a8e: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004a92: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
8004a96: 6013 str r3, [r2, #0]
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
8004a98: 68bb ldr r3, [r7, #8]
8004a9a: 015a lsls r2, r3, #5
8004a9c: 68fb ldr r3, [r7, #12]
8004a9e: 4413 add r3, r2
8004aa0: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004aa4: 681b ldr r3, [r3, #0]
8004aa6: 68ba ldr r2, [r7, #8]
8004aa8: 0151 lsls r1, r2, #5
8004aaa: 68fa ldr r2, [r7, #12]
8004aac: 440a add r2, r1
8004aae: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004ab2: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8004ab6: 6013 str r3, [r2, #0]
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
8004ab8: 68fb ldr r3, [r7, #12]
8004aba: f503 6300 add.w r3, r3, #2048 @ 0x800
8004abe: 6bda ldr r2, [r3, #60] @ 0x3c
8004ac0: 683b ldr r3, [r7, #0]
8004ac2: 781b ldrb r3, [r3, #0]
8004ac4: f003 030f and.w r3, r3, #15
8004ac8: 2101 movs r1, #1
8004aca: fa01 f303 lsl.w r3, r1, r3
8004ace: 041b lsls r3, r3, #16
8004ad0: 43db mvns r3, r3
8004ad2: 68f9 ldr r1, [r7, #12]
8004ad4: f501 6100 add.w r1, r1, #2048 @ 0x800
8004ad8: 4013 ands r3, r2
8004ada: 63cb str r3, [r1, #60] @ 0x3c
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
8004adc: 68fb ldr r3, [r7, #12]
8004ade: f503 6300 add.w r3, r3, #2048 @ 0x800
8004ae2: 69da ldr r2, [r3, #28]
8004ae4: 683b ldr r3, [r7, #0]
8004ae6: 781b ldrb r3, [r3, #0]
8004ae8: f003 030f and.w r3, r3, #15
8004aec: 2101 movs r1, #1
8004aee: fa01 f303 lsl.w r3, r1, r3
8004af2: 041b lsls r3, r3, #16
8004af4: 43db mvns r3, r3
8004af6: 68f9 ldr r1, [r7, #12]
8004af8: f501 6100 add.w r1, r1, #2048 @ 0x800
8004afc: 4013 ands r3, r2
8004afe: 61cb str r3, [r1, #28]
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
8004b00: 68bb ldr r3, [r7, #8]
8004b02: 015a lsls r2, r3, #5
8004b04: 68fb ldr r3, [r7, #12]
8004b06: 4413 add r3, r2
8004b08: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004b0c: 681a ldr r2, [r3, #0]
8004b0e: 68bb ldr r3, [r7, #8]
8004b10: 0159 lsls r1, r3, #5
8004b12: 68fb ldr r3, [r7, #12]
8004b14: 440b add r3, r1
8004b16: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004b1a: 4619 mov r1, r3
8004b1c: 4b05 ldr r3, [pc, #20] @ (8004b34 <USB_DeactivateEndpoint+0x1b4>)
8004b1e: 4013 ands r3, r2
8004b20: 600b str r3, [r1, #0]
USB_OTG_DOEPCTL_MPSIZ |
USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
USB_OTG_DOEPCTL_EPTYP);
}
return HAL_OK;
8004b22: 2300 movs r3, #0
}
8004b24: 4618 mov r0, r3
8004b26: 3714 adds r7, #20
8004b28: 46bd mov sp, r7
8004b2a: f85d 7b04 ldr.w r7, [sp], #4
8004b2e: 4770 bx lr
8004b30: ec337800 .word 0xec337800
8004b34: eff37800 .word 0xeff37800
08004b38 <USB_EPStartXfer>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
8004b38: b580 push {r7, lr}
8004b3a: b086 sub sp, #24
8004b3c: af00 add r7, sp, #0
8004b3e: 6078 str r0, [r7, #4]
8004b40: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
8004b42: 687b ldr r3, [r7, #4]
8004b44: 617b str r3, [r7, #20]
uint32_t epnum = (uint32_t)ep->num;
8004b46: 683b ldr r3, [r7, #0]
8004b48: 781b ldrb r3, [r3, #0]
8004b4a: 613b str r3, [r7, #16]
uint16_t pktcnt;
/* IN endpoint */
if (ep->is_in == 1U)
8004b4c: 683b ldr r3, [r7, #0]
8004b4e: 785b ldrb r3, [r3, #1]
8004b50: 2b01 cmp r3, #1
8004b52: f040 812d bne.w 8004db0 <USB_EPStartXfer+0x278>
{
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
8004b56: 683b ldr r3, [r7, #0]
8004b58: 691b ldr r3, [r3, #16]
8004b5a: 2b00 cmp r3, #0
8004b5c: d132 bne.n 8004bc4 <USB_EPStartXfer+0x8c>
{
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
8004b5e: 693b ldr r3, [r7, #16]
8004b60: 015a lsls r2, r3, #5
8004b62: 697b ldr r3, [r7, #20]
8004b64: 4413 add r3, r2
8004b66: f503 6310 add.w r3, r3, #2304 @ 0x900
8004b6a: 691b ldr r3, [r3, #16]
8004b6c: 693a ldr r2, [r7, #16]
8004b6e: 0151 lsls r1, r2, #5
8004b70: 697a ldr r2, [r7, #20]
8004b72: 440a add r2, r1
8004b74: f502 6210 add.w r2, r2, #2304 @ 0x900
8004b78: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
8004b7c: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
8004b80: 6113 str r3, [r2, #16]
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
8004b82: 693b ldr r3, [r7, #16]
8004b84: 015a lsls r2, r3, #5
8004b86: 697b ldr r3, [r7, #20]
8004b88: 4413 add r3, r2
8004b8a: f503 6310 add.w r3, r3, #2304 @ 0x900
8004b8e: 691b ldr r3, [r3, #16]
8004b90: 693a ldr r2, [r7, #16]
8004b92: 0151 lsls r1, r2, #5
8004b94: 697a ldr r2, [r7, #20]
8004b96: 440a add r2, r1
8004b98: f502 6210 add.w r2, r2, #2304 @ 0x900
8004b9c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8004ba0: 6113 str r3, [r2, #16]
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
8004ba2: 693b ldr r3, [r7, #16]
8004ba4: 015a lsls r2, r3, #5
8004ba6: 697b ldr r3, [r7, #20]
8004ba8: 4413 add r3, r2
8004baa: f503 6310 add.w r3, r3, #2304 @ 0x900
8004bae: 691b ldr r3, [r3, #16]
8004bb0: 693a ldr r2, [r7, #16]
8004bb2: 0151 lsls r1, r2, #5
8004bb4: 697a ldr r2, [r7, #20]
8004bb6: 440a add r2, r1
8004bb8: f502 6210 add.w r2, r2, #2304 @ 0x900
8004bbc: 0cdb lsrs r3, r3, #19
8004bbe: 04db lsls r3, r3, #19
8004bc0: 6113 str r3, [r2, #16]
8004bc2: e097 b.n 8004cf4 <USB_EPStartXfer+0x1bc>
/* Program the transfer size and packet count
* as follows: xfersize = N * maxpacket +
* short_packet pktcnt = N + (short_packet
* exist ? 1 : 0)
*/
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
8004bc4: 693b ldr r3, [r7, #16]
8004bc6: 015a lsls r2, r3, #5
8004bc8: 697b ldr r3, [r7, #20]
8004bca: 4413 add r3, r2
8004bcc: f503 6310 add.w r3, r3, #2304 @ 0x900
8004bd0: 691b ldr r3, [r3, #16]
8004bd2: 693a ldr r2, [r7, #16]
8004bd4: 0151 lsls r1, r2, #5
8004bd6: 697a ldr r2, [r7, #20]
8004bd8: 440a add r2, r1
8004bda: f502 6210 add.w r2, r2, #2304 @ 0x900
8004bde: 0cdb lsrs r3, r3, #19
8004be0: 04db lsls r3, r3, #19
8004be2: 6113 str r3, [r2, #16]
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
8004be4: 693b ldr r3, [r7, #16]
8004be6: 015a lsls r2, r3, #5
8004be8: 697b ldr r3, [r7, #20]
8004bea: 4413 add r3, r2
8004bec: f503 6310 add.w r3, r3, #2304 @ 0x900
8004bf0: 691b ldr r3, [r3, #16]
8004bf2: 693a ldr r2, [r7, #16]
8004bf4: 0151 lsls r1, r2, #5
8004bf6: 697a ldr r2, [r7, #20]
8004bf8: 440a add r2, r1
8004bfa: f502 6210 add.w r2, r2, #2304 @ 0x900
8004bfe: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
8004c02: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
8004c06: 6113 str r3, [r2, #16]
if (epnum == 0U)
8004c08: 693b ldr r3, [r7, #16]
8004c0a: 2b00 cmp r3, #0
8004c0c: d11a bne.n 8004c44 <USB_EPStartXfer+0x10c>
{
if (ep->xfer_len > ep->maxpacket)
8004c0e: 683b ldr r3, [r7, #0]
8004c10: 691a ldr r2, [r3, #16]
8004c12: 683b ldr r3, [r7, #0]
8004c14: 689b ldr r3, [r3, #8]
8004c16: 429a cmp r2, r3
8004c18: d903 bls.n 8004c22 <USB_EPStartXfer+0xea>
{
ep->xfer_len = ep->maxpacket;
8004c1a: 683b ldr r3, [r7, #0]
8004c1c: 689a ldr r2, [r3, #8]
8004c1e: 683b ldr r3, [r7, #0]
8004c20: 611a str r2, [r3, #16]
}
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
8004c22: 693b ldr r3, [r7, #16]
8004c24: 015a lsls r2, r3, #5
8004c26: 697b ldr r3, [r7, #20]
8004c28: 4413 add r3, r2
8004c2a: f503 6310 add.w r3, r3, #2304 @ 0x900
8004c2e: 691b ldr r3, [r3, #16]
8004c30: 693a ldr r2, [r7, #16]
8004c32: 0151 lsls r1, r2, #5
8004c34: 697a ldr r2, [r7, #20]
8004c36: 440a add r2, r1
8004c38: f502 6210 add.w r2, r2, #2304 @ 0x900
8004c3c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8004c40: 6113 str r3, [r2, #16]
8004c42: e044 b.n 8004cce <USB_EPStartXfer+0x196>
}
else
{
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
8004c44: 683b ldr r3, [r7, #0]
8004c46: 691a ldr r2, [r3, #16]
8004c48: 683b ldr r3, [r7, #0]
8004c4a: 689b ldr r3, [r3, #8]
8004c4c: 4413 add r3, r2
8004c4e: 1e5a subs r2, r3, #1
8004c50: 683b ldr r3, [r7, #0]
8004c52: 689b ldr r3, [r3, #8]
8004c54: fbb2 f3f3 udiv r3, r2, r3
8004c58: 81fb strh r3, [r7, #14]
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19));
8004c5a: 693b ldr r3, [r7, #16]
8004c5c: 015a lsls r2, r3, #5
8004c5e: 697b ldr r3, [r7, #20]
8004c60: 4413 add r3, r2
8004c62: f503 6310 add.w r3, r3, #2304 @ 0x900
8004c66: 691a ldr r2, [r3, #16]
8004c68: 89fb ldrh r3, [r7, #14]
8004c6a: 04d9 lsls r1, r3, #19
8004c6c: 4b8f ldr r3, [pc, #572] @ (8004eac <USB_EPStartXfer+0x374>)
8004c6e: 400b ands r3, r1
8004c70: 6939 ldr r1, [r7, #16]
8004c72: 0148 lsls r0, r1, #5
8004c74: 6979 ldr r1, [r7, #20]
8004c76: 4401 add r1, r0
8004c78: f501 6110 add.w r1, r1, #2304 @ 0x900
8004c7c: 4313 orrs r3, r2
8004c7e: 610b str r3, [r1, #16]
if (ep->type == EP_TYPE_ISOC)
8004c80: 683b ldr r3, [r7, #0]
8004c82: 791b ldrb r3, [r3, #4]
8004c84: 2b01 cmp r3, #1
8004c86: d122 bne.n 8004cce <USB_EPStartXfer+0x196>
{
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
8004c88: 693b ldr r3, [r7, #16]
8004c8a: 015a lsls r2, r3, #5
8004c8c: 697b ldr r3, [r7, #20]
8004c8e: 4413 add r3, r2
8004c90: f503 6310 add.w r3, r3, #2304 @ 0x900
8004c94: 691b ldr r3, [r3, #16]
8004c96: 693a ldr r2, [r7, #16]
8004c98: 0151 lsls r1, r2, #5
8004c9a: 697a ldr r2, [r7, #20]
8004c9c: 440a add r2, r1
8004c9e: f502 6210 add.w r2, r2, #2304 @ 0x900
8004ca2: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000
8004ca6: 6113 str r3, [r2, #16]
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (pktcnt << 29));
8004ca8: 693b ldr r3, [r7, #16]
8004caa: 015a lsls r2, r3, #5
8004cac: 697b ldr r3, [r7, #20]
8004cae: 4413 add r3, r2
8004cb0: f503 6310 add.w r3, r3, #2304 @ 0x900
8004cb4: 691a ldr r2, [r3, #16]
8004cb6: 89fb ldrh r3, [r7, #14]
8004cb8: 075b lsls r3, r3, #29
8004cba: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000
8004cbe: 6939 ldr r1, [r7, #16]
8004cc0: 0148 lsls r0, r1, #5
8004cc2: 6979 ldr r1, [r7, #20]
8004cc4: 4401 add r1, r0
8004cc6: f501 6110 add.w r1, r1, #2304 @ 0x900
8004cca: 4313 orrs r3, r2
8004ccc: 610b str r3, [r1, #16]
}
}
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
8004cce: 693b ldr r3, [r7, #16]
8004cd0: 015a lsls r2, r3, #5
8004cd2: 697b ldr r3, [r7, #20]
8004cd4: 4413 add r3, r2
8004cd6: f503 6310 add.w r3, r3, #2304 @ 0x900
8004cda: 691a ldr r2, [r3, #16]
8004cdc: 683b ldr r3, [r7, #0]
8004cde: 691b ldr r3, [r3, #16]
8004ce0: f3c3 0312 ubfx r3, r3, #0, #19
8004ce4: 6939 ldr r1, [r7, #16]
8004ce6: 0148 lsls r0, r1, #5
8004ce8: 6979 ldr r1, [r7, #20]
8004cea: 4401 add r1, r0
8004cec: f501 6110 add.w r1, r1, #2304 @ 0x900
8004cf0: 4313 orrs r3, r2
8004cf2: 610b str r3, [r1, #16]
}
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
8004cf4: 693b ldr r3, [r7, #16]
8004cf6: 015a lsls r2, r3, #5
8004cf8: 697b ldr r3, [r7, #20]
8004cfa: 4413 add r3, r2
8004cfc: f503 6310 add.w r3, r3, #2304 @ 0x900
8004d00: 681b ldr r3, [r3, #0]
8004d02: 693a ldr r2, [r7, #16]
8004d04: 0151 lsls r1, r2, #5
8004d06: 697a ldr r2, [r7, #20]
8004d08: 440a add r2, r1
8004d0a: f502 6210 add.w r2, r2, #2304 @ 0x900
8004d0e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
8004d12: 6013 str r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8004d14: 683b ldr r3, [r7, #0]
8004d16: 791b ldrb r3, [r3, #4]
8004d18: 2b01 cmp r3, #1
8004d1a: d015 beq.n 8004d48 <USB_EPStartXfer+0x210>
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
8004d1c: 683b ldr r3, [r7, #0]
8004d1e: 691b ldr r3, [r3, #16]
8004d20: 2b00 cmp r3, #0
8004d22: f000 813a beq.w 8004f9a <USB_EPStartXfer+0x462>
{
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
8004d26: 697b ldr r3, [r7, #20]
8004d28: f503 6300 add.w r3, r3, #2048 @ 0x800
8004d2c: 6b5a ldr r2, [r3, #52] @ 0x34
8004d2e: 683b ldr r3, [r7, #0]
8004d30: 781b ldrb r3, [r3, #0]
8004d32: f003 030f and.w r3, r3, #15
8004d36: 2101 movs r1, #1
8004d38: fa01 f303 lsl.w r3, r1, r3
8004d3c: 6979 ldr r1, [r7, #20]
8004d3e: f501 6100 add.w r1, r1, #2048 @ 0x800
8004d42: 4313 orrs r3, r2
8004d44: 634b str r3, [r1, #52] @ 0x34
8004d46: e128 b.n 8004f9a <USB_EPStartXfer+0x462>
}
}
else
{
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
8004d48: 697b ldr r3, [r7, #20]
8004d4a: f503 6300 add.w r3, r3, #2048 @ 0x800
8004d4e: 689b ldr r3, [r3, #8]
8004d50: f403 7380 and.w r3, r3, #256 @ 0x100
8004d54: 2b00 cmp r3, #0
8004d56: d110 bne.n 8004d7a <USB_EPStartXfer+0x242>
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
8004d58: 693b ldr r3, [r7, #16]
8004d5a: 015a lsls r2, r3, #5
8004d5c: 697b ldr r3, [r7, #20]
8004d5e: 4413 add r3, r2
8004d60: f503 6310 add.w r3, r3, #2304 @ 0x900
8004d64: 681b ldr r3, [r3, #0]
8004d66: 693a ldr r2, [r7, #16]
8004d68: 0151 lsls r1, r2, #5
8004d6a: 697a ldr r2, [r7, #20]
8004d6c: 440a add r2, r1
8004d6e: f502 6210 add.w r2, r2, #2304 @ 0x900
8004d72: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
8004d76: 6013 str r3, [r2, #0]
8004d78: e00f b.n 8004d9a <USB_EPStartXfer+0x262>
}
else
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
8004d7a: 693b ldr r3, [r7, #16]
8004d7c: 015a lsls r2, r3, #5
8004d7e: 697b ldr r3, [r7, #20]
8004d80: 4413 add r3, r2
8004d82: f503 6310 add.w r3, r3, #2304 @ 0x900
8004d86: 681b ldr r3, [r3, #0]
8004d88: 693a ldr r2, [r7, #16]
8004d8a: 0151 lsls r1, r2, #5
8004d8c: 697a ldr r2, [r7, #20]
8004d8e: 440a add r2, r1
8004d90: f502 6210 add.w r2, r2, #2304 @ 0x900
8004d94: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004d98: 6013 str r3, [r2, #0]
}
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len);
8004d9a: 683b ldr r3, [r7, #0]
8004d9c: 68d9 ldr r1, [r3, #12]
8004d9e: 683b ldr r3, [r7, #0]
8004da0: 781a ldrb r2, [r3, #0]
8004da2: 683b ldr r3, [r7, #0]
8004da4: 691b ldr r3, [r3, #16]
8004da6: b29b uxth r3, r3
8004da8: 6878 ldr r0, [r7, #4]
8004daa: f000 f9a7 bl 80050fc <USB_WritePacket>
8004dae: e0f4 b.n 8004f9a <USB_EPStartXfer+0x462>
{
/* Program the transfer size and packet count as follows:
* pktcnt = N
* xfersize = N * maxpacket
*/
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
8004db0: 693b ldr r3, [r7, #16]
8004db2: 015a lsls r2, r3, #5
8004db4: 697b ldr r3, [r7, #20]
8004db6: 4413 add r3, r2
8004db8: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004dbc: 691b ldr r3, [r3, #16]
8004dbe: 693a ldr r2, [r7, #16]
8004dc0: 0151 lsls r1, r2, #5
8004dc2: 697a ldr r2, [r7, #20]
8004dc4: 440a add r2, r1
8004dc6: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004dca: 0cdb lsrs r3, r3, #19
8004dcc: 04db lsls r3, r3, #19
8004dce: 6113 str r3, [r2, #16]
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
8004dd0: 693b ldr r3, [r7, #16]
8004dd2: 015a lsls r2, r3, #5
8004dd4: 697b ldr r3, [r7, #20]
8004dd6: 4413 add r3, r2
8004dd8: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004ddc: 691b ldr r3, [r3, #16]
8004dde: 693a ldr r2, [r7, #16]
8004de0: 0151 lsls r1, r2, #5
8004de2: 697a ldr r2, [r7, #20]
8004de4: 440a add r2, r1
8004de6: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004dea: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
8004dee: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
8004df2: 6113 str r3, [r2, #16]
if (epnum == 0U)
8004df4: 693b ldr r3, [r7, #16]
8004df6: 2b00 cmp r3, #0
8004df8: d12f bne.n 8004e5a <USB_EPStartXfer+0x322>
{
if (ep->xfer_len > 0U)
8004dfa: 683b ldr r3, [r7, #0]
8004dfc: 691b ldr r3, [r3, #16]
8004dfe: 2b00 cmp r3, #0
8004e00: d003 beq.n 8004e0a <USB_EPStartXfer+0x2d2>
{
ep->xfer_len = ep->maxpacket;
8004e02: 683b ldr r3, [r7, #0]
8004e04: 689a ldr r2, [r3, #8]
8004e06: 683b ldr r3, [r7, #0]
8004e08: 611a str r2, [r3, #16]
}
/* Store transfer size, for EP0 this is equal to endpoint max packet size */
ep->xfer_size = ep->maxpacket;
8004e0a: 683b ldr r3, [r7, #0]
8004e0c: 689a ldr r2, [r3, #8]
8004e0e: 683b ldr r3, [r7, #0]
8004e10: 621a str r2, [r3, #32]
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
8004e12: 693b ldr r3, [r7, #16]
8004e14: 015a lsls r2, r3, #5
8004e16: 697b ldr r3, [r7, #20]
8004e18: 4413 add r3, r2
8004e1a: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004e1e: 691a ldr r2, [r3, #16]
8004e20: 683b ldr r3, [r7, #0]
8004e22: 6a1b ldr r3, [r3, #32]
8004e24: f3c3 0312 ubfx r3, r3, #0, #19
8004e28: 6939 ldr r1, [r7, #16]
8004e2a: 0148 lsls r0, r1, #5
8004e2c: 6979 ldr r1, [r7, #20]
8004e2e: 4401 add r1, r0
8004e30: f501 6130 add.w r1, r1, #2816 @ 0xb00
8004e34: 4313 orrs r3, r2
8004e36: 610b str r3, [r1, #16]
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
8004e38: 693b ldr r3, [r7, #16]
8004e3a: 015a lsls r2, r3, #5
8004e3c: 697b ldr r3, [r7, #20]
8004e3e: 4413 add r3, r2
8004e40: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004e44: 691b ldr r3, [r3, #16]
8004e46: 693a ldr r2, [r7, #16]
8004e48: 0151 lsls r1, r2, #5
8004e4a: 697a ldr r2, [r7, #20]
8004e4c: 440a add r2, r1
8004e4e: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004e52: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8004e56: 6113 str r3, [r2, #16]
8004e58: e062 b.n 8004f20 <USB_EPStartXfer+0x3e8>
}
else
{
if (ep->xfer_len == 0U)
8004e5a: 683b ldr r3, [r7, #0]
8004e5c: 691b ldr r3, [r3, #16]
8004e5e: 2b00 cmp r3, #0
8004e60: d126 bne.n 8004eb0 <USB_EPStartXfer+0x378>
{
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
8004e62: 693b ldr r3, [r7, #16]
8004e64: 015a lsls r2, r3, #5
8004e66: 697b ldr r3, [r7, #20]
8004e68: 4413 add r3, r2
8004e6a: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004e6e: 691a ldr r2, [r3, #16]
8004e70: 683b ldr r3, [r7, #0]
8004e72: 689b ldr r3, [r3, #8]
8004e74: f3c3 0312 ubfx r3, r3, #0, #19
8004e78: 6939 ldr r1, [r7, #16]
8004e7a: 0148 lsls r0, r1, #5
8004e7c: 6979 ldr r1, [r7, #20]
8004e7e: 4401 add r1, r0
8004e80: f501 6130 add.w r1, r1, #2816 @ 0xb00
8004e84: 4313 orrs r3, r2
8004e86: 610b str r3, [r1, #16]
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
8004e88: 693b ldr r3, [r7, #16]
8004e8a: 015a lsls r2, r3, #5
8004e8c: 697b ldr r3, [r7, #20]
8004e8e: 4413 add r3, r2
8004e90: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004e94: 691b ldr r3, [r3, #16]
8004e96: 693a ldr r2, [r7, #16]
8004e98: 0151 lsls r1, r2, #5
8004e9a: 697a ldr r2, [r7, #20]
8004e9c: 440a add r2, r1
8004e9e: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004ea2: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8004ea6: 6113 str r3, [r2, #16]
8004ea8: e03a b.n 8004f20 <USB_EPStartXfer+0x3e8>
8004eaa: bf00 nop
8004eac: 1ff80000 .word 0x1ff80000
}
else
{
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
8004eb0: 683b ldr r3, [r7, #0]
8004eb2: 691a ldr r2, [r3, #16]
8004eb4: 683b ldr r3, [r7, #0]
8004eb6: 689b ldr r3, [r3, #8]
8004eb8: 4413 add r3, r2
8004eba: 1e5a subs r2, r3, #1
8004ebc: 683b ldr r3, [r7, #0]
8004ebe: 689b ldr r3, [r3, #8]
8004ec0: fbb2 f3f3 udiv r3, r2, r3
8004ec4: 81fb strh r3, [r7, #14]
ep->xfer_size = ep->maxpacket * pktcnt;
8004ec6: 683b ldr r3, [r7, #0]
8004ec8: 689b ldr r3, [r3, #8]
8004eca: 89fa ldrh r2, [r7, #14]
8004ecc: fb03 f202 mul.w r2, r3, r2
8004ed0: 683b ldr r3, [r7, #0]
8004ed2: 621a str r2, [r3, #32]
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
8004ed4: 693b ldr r3, [r7, #16]
8004ed6: 015a lsls r2, r3, #5
8004ed8: 697b ldr r3, [r7, #20]
8004eda: 4413 add r3, r2
8004edc: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004ee0: 691a ldr r2, [r3, #16]
8004ee2: 89fb ldrh r3, [r7, #14]
8004ee4: 04d9 lsls r1, r3, #19
8004ee6: 4b2f ldr r3, [pc, #188] @ (8004fa4 <USB_EPStartXfer+0x46c>)
8004ee8: 400b ands r3, r1
8004eea: 6939 ldr r1, [r7, #16]
8004eec: 0148 lsls r0, r1, #5
8004eee: 6979 ldr r1, [r7, #20]
8004ef0: 4401 add r1, r0
8004ef2: f501 6130 add.w r1, r1, #2816 @ 0xb00
8004ef6: 4313 orrs r3, r2
8004ef8: 610b str r3, [r1, #16]
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
8004efa: 693b ldr r3, [r7, #16]
8004efc: 015a lsls r2, r3, #5
8004efe: 697b ldr r3, [r7, #20]
8004f00: 4413 add r3, r2
8004f02: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004f06: 691a ldr r2, [r3, #16]
8004f08: 683b ldr r3, [r7, #0]
8004f0a: 6a1b ldr r3, [r3, #32]
8004f0c: f3c3 0312 ubfx r3, r3, #0, #19
8004f10: 6939 ldr r1, [r7, #16]
8004f12: 0148 lsls r0, r1, #5
8004f14: 6979 ldr r1, [r7, #20]
8004f16: 4401 add r1, r0
8004f18: f501 6130 add.w r1, r1, #2816 @ 0xb00
8004f1c: 4313 orrs r3, r2
8004f1e: 610b str r3, [r1, #16]
}
}
if (ep->type == EP_TYPE_ISOC)
8004f20: 683b ldr r3, [r7, #0]
8004f22: 791b ldrb r3, [r3, #4]
8004f24: 2b01 cmp r3, #1
8004f26: d128 bne.n 8004f7a <USB_EPStartXfer+0x442>
{
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
8004f28: 697b ldr r3, [r7, #20]
8004f2a: f503 6300 add.w r3, r3, #2048 @ 0x800
8004f2e: 689b ldr r3, [r3, #8]
8004f30: f403 7380 and.w r3, r3, #256 @ 0x100
8004f34: 2b00 cmp r3, #0
8004f36: d110 bne.n 8004f5a <USB_EPStartXfer+0x422>
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
8004f38: 693b ldr r3, [r7, #16]
8004f3a: 015a lsls r2, r3, #5
8004f3c: 697b ldr r3, [r7, #20]
8004f3e: 4413 add r3, r2
8004f40: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004f44: 681b ldr r3, [r3, #0]
8004f46: 693a ldr r2, [r7, #16]
8004f48: 0151 lsls r1, r2, #5
8004f4a: 697a ldr r2, [r7, #20]
8004f4c: 440a add r2, r1
8004f4e: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004f52: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
8004f56: 6013 str r3, [r2, #0]
8004f58: e00f b.n 8004f7a <USB_EPStartXfer+0x442>
}
else
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
8004f5a: 693b ldr r3, [r7, #16]
8004f5c: 015a lsls r2, r3, #5
8004f5e: 697b ldr r3, [r7, #20]
8004f60: 4413 add r3, r2
8004f62: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004f66: 681b ldr r3, [r3, #0]
8004f68: 693a ldr r2, [r7, #16]
8004f6a: 0151 lsls r1, r2, #5
8004f6c: 697a ldr r2, [r7, #20]
8004f6e: 440a add r2, r1
8004f70: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004f74: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004f78: 6013 str r3, [r2, #0]
}
}
/* EP enable */
USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
8004f7a: 693b ldr r3, [r7, #16]
8004f7c: 015a lsls r2, r3, #5
8004f7e: 697b ldr r3, [r7, #20]
8004f80: 4413 add r3, r2
8004f82: f503 6330 add.w r3, r3, #2816 @ 0xb00
8004f86: 681b ldr r3, [r3, #0]
8004f88: 693a ldr r2, [r7, #16]
8004f8a: 0151 lsls r1, r2, #5
8004f8c: 697a ldr r2, [r7, #20]
8004f8e: 440a add r2, r1
8004f90: f502 6230 add.w r2, r2, #2816 @ 0xb00
8004f94: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
8004f98: 6013 str r3, [r2, #0]
}
return HAL_OK;
8004f9a: 2300 movs r3, #0
}
8004f9c: 4618 mov r0, r3
8004f9e: 3718 adds r7, #24
8004fa0: 46bd mov sp, r7
8004fa2: bd80 pop {r7, pc}
8004fa4: 1ff80000 .word 0x1ff80000
08004fa8 <USB_EPStopXfer>:
* @param USBx usb device instance
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
8004fa8: b480 push {r7}
8004faa: b087 sub sp, #28
8004fac: af00 add r7, sp, #0
8004fae: 6078 str r0, [r7, #4]
8004fb0: 6039 str r1, [r7, #0]
__IO uint32_t count = 0U;
8004fb2: 2300 movs r3, #0
8004fb4: 60fb str r3, [r7, #12]
HAL_StatusTypeDef ret = HAL_OK;
8004fb6: 2300 movs r3, #0
8004fb8: 75fb strb r3, [r7, #23]
uint32_t USBx_BASE = (uint32_t)USBx;
8004fba: 687b ldr r3, [r7, #4]
8004fbc: 613b str r3, [r7, #16]
/* IN endpoint */
if (ep->is_in == 1U)
8004fbe: 683b ldr r3, [r7, #0]
8004fc0: 785b ldrb r3, [r3, #1]
8004fc2: 2b01 cmp r3, #1
8004fc4: d14a bne.n 800505c <USB_EPStopXfer+0xb4>
{
/* EP enable, IN data in FIFO */
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
8004fc6: 683b ldr r3, [r7, #0]
8004fc8: 781b ldrb r3, [r3, #0]
8004fca: 015a lsls r2, r3, #5
8004fcc: 693b ldr r3, [r7, #16]
8004fce: 4413 add r3, r2
8004fd0: f503 6310 add.w r3, r3, #2304 @ 0x900
8004fd4: 681b ldr r3, [r3, #0]
8004fd6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8004fda: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8004fde: f040 8086 bne.w 80050ee <USB_EPStopXfer+0x146>
{
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
8004fe2: 683b ldr r3, [r7, #0]
8004fe4: 781b ldrb r3, [r3, #0]
8004fe6: 015a lsls r2, r3, #5
8004fe8: 693b ldr r3, [r7, #16]
8004fea: 4413 add r3, r2
8004fec: f503 6310 add.w r3, r3, #2304 @ 0x900
8004ff0: 681b ldr r3, [r3, #0]
8004ff2: 683a ldr r2, [r7, #0]
8004ff4: 7812 ldrb r2, [r2, #0]
8004ff6: 0151 lsls r1, r2, #5
8004ff8: 693a ldr r2, [r7, #16]
8004ffa: 440a add r2, r1
8004ffc: f502 6210 add.w r2, r2, #2304 @ 0x900
8005000: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
8005004: 6013 str r3, [r2, #0]
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
8005006: 683b ldr r3, [r7, #0]
8005008: 781b ldrb r3, [r3, #0]
800500a: 015a lsls r2, r3, #5
800500c: 693b ldr r3, [r7, #16]
800500e: 4413 add r3, r2
8005010: f503 6310 add.w r3, r3, #2304 @ 0x900
8005014: 681b ldr r3, [r3, #0]
8005016: 683a ldr r2, [r7, #0]
8005018: 7812 ldrb r2, [r2, #0]
800501a: 0151 lsls r1, r2, #5
800501c: 693a ldr r2, [r7, #16]
800501e: 440a add r2, r1
8005020: f502 6210 add.w r2, r2, #2304 @ 0x900
8005024: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8005028: 6013 str r3, [r2, #0]
do
{
count++;
800502a: 68fb ldr r3, [r7, #12]
800502c: 3301 adds r3, #1
800502e: 60fb str r3, [r7, #12]
if (count > 10000U)
8005030: 68fb ldr r3, [r7, #12]
8005032: f242 7210 movw r2, #10000 @ 0x2710
8005036: 4293 cmp r3, r2
8005038: d902 bls.n 8005040 <USB_EPStopXfer+0x98>
{
ret = HAL_ERROR;
800503a: 2301 movs r3, #1
800503c: 75fb strb r3, [r7, #23]
break;
800503e: e056 b.n 80050ee <USB_EPStopXfer+0x146>
}
} while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
8005040: 683b ldr r3, [r7, #0]
8005042: 781b ldrb r3, [r3, #0]
8005044: 015a lsls r2, r3, #5
8005046: 693b ldr r3, [r7, #16]
8005048: 4413 add r3, r2
800504a: f503 6310 add.w r3, r3, #2304 @ 0x900
800504e: 681b ldr r3, [r3, #0]
8005050: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8005054: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8005058: d0e7 beq.n 800502a <USB_EPStopXfer+0x82>
800505a: e048 b.n 80050ee <USB_EPStopXfer+0x146>
}
}
else /* OUT endpoint */
{
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
800505c: 683b ldr r3, [r7, #0]
800505e: 781b ldrb r3, [r3, #0]
8005060: 015a lsls r2, r3, #5
8005062: 693b ldr r3, [r7, #16]
8005064: 4413 add r3, r2
8005066: f503 6330 add.w r3, r3, #2816 @ 0xb00
800506a: 681b ldr r3, [r3, #0]
800506c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8005070: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8005074: d13b bne.n 80050ee <USB_EPStopXfer+0x146>
{
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
8005076: 683b ldr r3, [r7, #0]
8005078: 781b ldrb r3, [r3, #0]
800507a: 015a lsls r2, r3, #5
800507c: 693b ldr r3, [r7, #16]
800507e: 4413 add r3, r2
8005080: f503 6330 add.w r3, r3, #2816 @ 0xb00
8005084: 681b ldr r3, [r3, #0]
8005086: 683a ldr r2, [r7, #0]
8005088: 7812 ldrb r2, [r2, #0]
800508a: 0151 lsls r1, r2, #5
800508c: 693a ldr r2, [r7, #16]
800508e: 440a add r2, r1
8005090: f502 6230 add.w r2, r2, #2816 @ 0xb00
8005094: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
8005098: 6013 str r3, [r2, #0]
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
800509a: 683b ldr r3, [r7, #0]
800509c: 781b ldrb r3, [r3, #0]
800509e: 015a lsls r2, r3, #5
80050a0: 693b ldr r3, [r7, #16]
80050a2: 4413 add r3, r2
80050a4: f503 6330 add.w r3, r3, #2816 @ 0xb00
80050a8: 681b ldr r3, [r3, #0]
80050aa: 683a ldr r2, [r7, #0]
80050ac: 7812 ldrb r2, [r2, #0]
80050ae: 0151 lsls r1, r2, #5
80050b0: 693a ldr r2, [r7, #16]
80050b2: 440a add r2, r1
80050b4: f502 6230 add.w r2, r2, #2816 @ 0xb00
80050b8: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
80050bc: 6013 str r3, [r2, #0]
do
{
count++;
80050be: 68fb ldr r3, [r7, #12]
80050c0: 3301 adds r3, #1
80050c2: 60fb str r3, [r7, #12]
if (count > 10000U)
80050c4: 68fb ldr r3, [r7, #12]
80050c6: f242 7210 movw r2, #10000 @ 0x2710
80050ca: 4293 cmp r3, r2
80050cc: d902 bls.n 80050d4 <USB_EPStopXfer+0x12c>
{
ret = HAL_ERROR;
80050ce: 2301 movs r3, #1
80050d0: 75fb strb r3, [r7, #23]
break;
80050d2: e00c b.n 80050ee <USB_EPStopXfer+0x146>
}
} while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
80050d4: 683b ldr r3, [r7, #0]
80050d6: 781b ldrb r3, [r3, #0]
80050d8: 015a lsls r2, r3, #5
80050da: 693b ldr r3, [r7, #16]
80050dc: 4413 add r3, r2
80050de: f503 6330 add.w r3, r3, #2816 @ 0xb00
80050e2: 681b ldr r3, [r3, #0]
80050e4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80050e8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80050ec: d0e7 beq.n 80050be <USB_EPStopXfer+0x116>
}
}
return ret;
80050ee: 7dfb ldrb r3, [r7, #23]
}
80050f0: 4618 mov r0, r3
80050f2: 371c adds r7, #28
80050f4: 46bd mov sp, r7
80050f6: f85d 7b04 ldr.w r7, [sp], #4
80050fa: 4770 bx lr
080050fc <USB_WritePacket>:
* @param len Number of bytes to write
* @retval HAL status
*/
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len)
{
80050fc: b480 push {r7}
80050fe: b089 sub sp, #36 @ 0x24
8005100: af00 add r7, sp, #0
8005102: 60f8 str r0, [r7, #12]
8005104: 60b9 str r1, [r7, #8]
8005106: 4611 mov r1, r2
8005108: 461a mov r2, r3
800510a: 460b mov r3, r1
800510c: 71fb strb r3, [r7, #7]
800510e: 4613 mov r3, r2
8005110: 80bb strh r3, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
8005112: 68fb ldr r3, [r7, #12]
8005114: 617b str r3, [r7, #20]
uint8_t *pSrc = src;
8005116: 68bb ldr r3, [r7, #8]
8005118: 61fb str r3, [r7, #28]
uint32_t count32b;
uint32_t i;
count32b = ((uint32_t)len + 3U) / 4U;
800511a: 88bb ldrh r3, [r7, #4]
800511c: 3303 adds r3, #3
800511e: 089b lsrs r3, r3, #2
8005120: 613b str r3, [r7, #16]
for (i = 0U; i < count32b; i++)
8005122: 2300 movs r3, #0
8005124: 61bb str r3, [r7, #24]
8005126: e018 b.n 800515a <USB_WritePacket+0x5e>
{
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
8005128: 79fb ldrb r3, [r7, #7]
800512a: 031a lsls r2, r3, #12
800512c: 697b ldr r3, [r7, #20]
800512e: 4413 add r3, r2
8005130: f503 5380 add.w r3, r3, #4096 @ 0x1000
8005134: 461a mov r2, r3
8005136: 69fb ldr r3, [r7, #28]
8005138: 681b ldr r3, [r3, #0]
800513a: 6013 str r3, [r2, #0]
pSrc++;
800513c: 69fb ldr r3, [r7, #28]
800513e: 3301 adds r3, #1
8005140: 61fb str r3, [r7, #28]
pSrc++;
8005142: 69fb ldr r3, [r7, #28]
8005144: 3301 adds r3, #1
8005146: 61fb str r3, [r7, #28]
pSrc++;
8005148: 69fb ldr r3, [r7, #28]
800514a: 3301 adds r3, #1
800514c: 61fb str r3, [r7, #28]
pSrc++;
800514e: 69fb ldr r3, [r7, #28]
8005150: 3301 adds r3, #1
8005152: 61fb str r3, [r7, #28]
for (i = 0U; i < count32b; i++)
8005154: 69bb ldr r3, [r7, #24]
8005156: 3301 adds r3, #1
8005158: 61bb str r3, [r7, #24]
800515a: 69ba ldr r2, [r7, #24]
800515c: 693b ldr r3, [r7, #16]
800515e: 429a cmp r2, r3
8005160: d3e2 bcc.n 8005128 <USB_WritePacket+0x2c>
}
return HAL_OK;
8005162: 2300 movs r3, #0
}
8005164: 4618 mov r0, r3
8005166: 3724 adds r7, #36 @ 0x24
8005168: 46bd mov sp, r7
800516a: f85d 7b04 ldr.w r7, [sp], #4
800516e: 4770 bx lr
08005170 <USB_ReadPacket>:
* @param dest source pointer
* @param len Number of bytes to read
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
8005170: b480 push {r7}
8005172: b08b sub sp, #44 @ 0x2c
8005174: af00 add r7, sp, #0
8005176: 60f8 str r0, [r7, #12]
8005178: 60b9 str r1, [r7, #8]
800517a: 4613 mov r3, r2
800517c: 80fb strh r3, [r7, #6]
uint32_t USBx_BASE = (uint32_t)USBx;
800517e: 68fb ldr r3, [r7, #12]
8005180: 61bb str r3, [r7, #24]
uint8_t *pDest = dest;
8005182: 68bb ldr r3, [r7, #8]
8005184: 627b str r3, [r7, #36] @ 0x24
uint32_t pData;
uint32_t i;
uint32_t count32b = (uint32_t)len >> 2U;
8005186: 88fb ldrh r3, [r7, #6]
8005188: 089b lsrs r3, r3, #2
800518a: b29b uxth r3, r3
800518c: 617b str r3, [r7, #20]
uint16_t remaining_bytes = len % 4U;
800518e: 88fb ldrh r3, [r7, #6]
8005190: f003 0303 and.w r3, r3, #3
8005194: 83fb strh r3, [r7, #30]
for (i = 0U; i < count32b; i++)
8005196: 2300 movs r3, #0
8005198: 623b str r3, [r7, #32]
800519a: e014 b.n 80051c6 <USB_ReadPacket+0x56>
{
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
800519c: 69bb ldr r3, [r7, #24]
800519e: f503 5380 add.w r3, r3, #4096 @ 0x1000
80051a2: 681a ldr r2, [r3, #0]
80051a4: 6a7b ldr r3, [r7, #36] @ 0x24
80051a6: 601a str r2, [r3, #0]
pDest++;
80051a8: 6a7b ldr r3, [r7, #36] @ 0x24
80051aa: 3301 adds r3, #1
80051ac: 627b str r3, [r7, #36] @ 0x24
pDest++;
80051ae: 6a7b ldr r3, [r7, #36] @ 0x24
80051b0: 3301 adds r3, #1
80051b2: 627b str r3, [r7, #36] @ 0x24
pDest++;
80051b4: 6a7b ldr r3, [r7, #36] @ 0x24
80051b6: 3301 adds r3, #1
80051b8: 627b str r3, [r7, #36] @ 0x24
pDest++;
80051ba: 6a7b ldr r3, [r7, #36] @ 0x24
80051bc: 3301 adds r3, #1
80051be: 627b str r3, [r7, #36] @ 0x24
for (i = 0U; i < count32b; i++)
80051c0: 6a3b ldr r3, [r7, #32]
80051c2: 3301 adds r3, #1
80051c4: 623b str r3, [r7, #32]
80051c6: 6a3a ldr r2, [r7, #32]
80051c8: 697b ldr r3, [r7, #20]
80051ca: 429a cmp r2, r3
80051cc: d3e6 bcc.n 800519c <USB_ReadPacket+0x2c>
}
/* When Number of data is not word aligned, read the remaining byte */
if (remaining_bytes != 0U)
80051ce: 8bfb ldrh r3, [r7, #30]
80051d0: 2b00 cmp r3, #0
80051d2: d01e beq.n 8005212 <USB_ReadPacket+0xa2>
{
i = 0U;
80051d4: 2300 movs r3, #0
80051d6: 623b str r3, [r7, #32]
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
80051d8: 69bb ldr r3, [r7, #24]
80051da: f503 5380 add.w r3, r3, #4096 @ 0x1000
80051de: 461a mov r2, r3
80051e0: f107 0310 add.w r3, r7, #16
80051e4: 6812 ldr r2, [r2, #0]
80051e6: 601a str r2, [r3, #0]
do
{
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
80051e8: 693a ldr r2, [r7, #16]
80051ea: 6a3b ldr r3, [r7, #32]
80051ec: b2db uxtb r3, r3
80051ee: 00db lsls r3, r3, #3
80051f0: fa22 f303 lsr.w r3, r2, r3
80051f4: b2da uxtb r2, r3
80051f6: 6a7b ldr r3, [r7, #36] @ 0x24
80051f8: 701a strb r2, [r3, #0]
i++;
80051fa: 6a3b ldr r3, [r7, #32]
80051fc: 3301 adds r3, #1
80051fe: 623b str r3, [r7, #32]
pDest++;
8005200: 6a7b ldr r3, [r7, #36] @ 0x24
8005202: 3301 adds r3, #1
8005204: 627b str r3, [r7, #36] @ 0x24
remaining_bytes--;
8005206: 8bfb ldrh r3, [r7, #30]
8005208: 3b01 subs r3, #1
800520a: 83fb strh r3, [r7, #30]
} while (remaining_bytes != 0U);
800520c: 8bfb ldrh r3, [r7, #30]
800520e: 2b00 cmp r3, #0
8005210: d1ea bne.n 80051e8 <USB_ReadPacket+0x78>
}
return ((void *)pDest);
8005212: 6a7b ldr r3, [r7, #36] @ 0x24
}
8005214: 4618 mov r0, r3
8005216: 372c adds r7, #44 @ 0x2c
8005218: 46bd mov sp, r7
800521a: f85d 7b04 ldr.w r7, [sp], #4
800521e: 4770 bx lr
08005220 <USB_EPSetStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
8005220: b480 push {r7}
8005222: b085 sub sp, #20
8005224: af00 add r7, sp, #0
8005226: 6078 str r0, [r7, #4]
8005228: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
800522a: 687b ldr r3, [r7, #4]
800522c: 60fb str r3, [r7, #12]
uint32_t epnum = (uint32_t)ep->num;
800522e: 683b ldr r3, [r7, #0]
8005230: 781b ldrb r3, [r3, #0]
8005232: 60bb str r3, [r7, #8]
if (ep->is_in == 1U)
8005234: 683b ldr r3, [r7, #0]
8005236: 785b ldrb r3, [r3, #1]
8005238: 2b01 cmp r3, #1
800523a: d12c bne.n 8005296 <USB_EPSetStall+0x76>
{
if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
800523c: 68bb ldr r3, [r7, #8]
800523e: 015a lsls r2, r3, #5
8005240: 68fb ldr r3, [r7, #12]
8005242: 4413 add r3, r2
8005244: f503 6310 add.w r3, r3, #2304 @ 0x900
8005248: 681b ldr r3, [r3, #0]
800524a: 2b00 cmp r3, #0
800524c: db12 blt.n 8005274 <USB_EPSetStall+0x54>
800524e: 68bb ldr r3, [r7, #8]
8005250: 2b00 cmp r3, #0
8005252: d00f beq.n 8005274 <USB_EPSetStall+0x54>
{
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
8005254: 68bb ldr r3, [r7, #8]
8005256: 015a lsls r2, r3, #5
8005258: 68fb ldr r3, [r7, #12]
800525a: 4413 add r3, r2
800525c: f503 6310 add.w r3, r3, #2304 @ 0x900
8005260: 681b ldr r3, [r3, #0]
8005262: 68ba ldr r2, [r7, #8]
8005264: 0151 lsls r1, r2, #5
8005266: 68fa ldr r2, [r7, #12]
8005268: 440a add r2, r1
800526a: f502 6210 add.w r2, r2, #2304 @ 0x900
800526e: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
8005272: 6013 str r3, [r2, #0]
}
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
8005274: 68bb ldr r3, [r7, #8]
8005276: 015a lsls r2, r3, #5
8005278: 68fb ldr r3, [r7, #12]
800527a: 4413 add r3, r2
800527c: f503 6310 add.w r3, r3, #2304 @ 0x900
8005280: 681b ldr r3, [r3, #0]
8005282: 68ba ldr r2, [r7, #8]
8005284: 0151 lsls r1, r2, #5
8005286: 68fa ldr r2, [r7, #12]
8005288: 440a add r2, r1
800528a: f502 6210 add.w r2, r2, #2304 @ 0x900
800528e: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
8005292: 6013 str r3, [r2, #0]
8005294: e02b b.n 80052ee <USB_EPSetStall+0xce>
}
else
{
if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
8005296: 68bb ldr r3, [r7, #8]
8005298: 015a lsls r2, r3, #5
800529a: 68fb ldr r3, [r7, #12]
800529c: 4413 add r3, r2
800529e: f503 6330 add.w r3, r3, #2816 @ 0xb00
80052a2: 681b ldr r3, [r3, #0]
80052a4: 2b00 cmp r3, #0
80052a6: db12 blt.n 80052ce <USB_EPSetStall+0xae>
80052a8: 68bb ldr r3, [r7, #8]
80052aa: 2b00 cmp r3, #0
80052ac: d00f beq.n 80052ce <USB_EPSetStall+0xae>
{
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
80052ae: 68bb ldr r3, [r7, #8]
80052b0: 015a lsls r2, r3, #5
80052b2: 68fb ldr r3, [r7, #12]
80052b4: 4413 add r3, r2
80052b6: f503 6330 add.w r3, r3, #2816 @ 0xb00
80052ba: 681b ldr r3, [r3, #0]
80052bc: 68ba ldr r2, [r7, #8]
80052be: 0151 lsls r1, r2, #5
80052c0: 68fa ldr r2, [r7, #12]
80052c2: 440a add r2, r1
80052c4: f502 6230 add.w r2, r2, #2816 @ 0xb00
80052c8: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
80052cc: 6013 str r3, [r2, #0]
}
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
80052ce: 68bb ldr r3, [r7, #8]
80052d0: 015a lsls r2, r3, #5
80052d2: 68fb ldr r3, [r7, #12]
80052d4: 4413 add r3, r2
80052d6: f503 6330 add.w r3, r3, #2816 @ 0xb00
80052da: 681b ldr r3, [r3, #0]
80052dc: 68ba ldr r2, [r7, #8]
80052de: 0151 lsls r1, r2, #5
80052e0: 68fa ldr r2, [r7, #12]
80052e2: 440a add r2, r1
80052e4: f502 6230 add.w r2, r2, #2816 @ 0xb00
80052e8: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
80052ec: 6013 str r3, [r2, #0]
}
return HAL_OK;
80052ee: 2300 movs r3, #0
}
80052f0: 4618 mov r0, r3
80052f2: 3714 adds r7, #20
80052f4: 46bd mov sp, r7
80052f6: f85d 7b04 ldr.w r7, [sp], #4
80052fa: 4770 bx lr
080052fc <USB_EPClearStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
80052fc: b480 push {r7}
80052fe: b085 sub sp, #20
8005300: af00 add r7, sp, #0
8005302: 6078 str r0, [r7, #4]
8005304: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
8005306: 687b ldr r3, [r7, #4]
8005308: 60fb str r3, [r7, #12]
uint32_t epnum = (uint32_t)ep->num;
800530a: 683b ldr r3, [r7, #0]
800530c: 781b ldrb r3, [r3, #0]
800530e: 60bb str r3, [r7, #8]
if (ep->is_in == 1U)
8005310: 683b ldr r3, [r7, #0]
8005312: 785b ldrb r3, [r3, #1]
8005314: 2b01 cmp r3, #1
8005316: d128 bne.n 800536a <USB_EPClearStall+0x6e>
{
USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
8005318: 68bb ldr r3, [r7, #8]
800531a: 015a lsls r2, r3, #5
800531c: 68fb ldr r3, [r7, #12]
800531e: 4413 add r3, r2
8005320: f503 6310 add.w r3, r3, #2304 @ 0x900
8005324: 681b ldr r3, [r3, #0]
8005326: 68ba ldr r2, [r7, #8]
8005328: 0151 lsls r1, r2, #5
800532a: 68fa ldr r2, [r7, #12]
800532c: 440a add r2, r1
800532e: f502 6210 add.w r2, r2, #2304 @ 0x900
8005332: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8005336: 6013 str r3, [r2, #0]
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
8005338: 683b ldr r3, [r7, #0]
800533a: 791b ldrb r3, [r3, #4]
800533c: 2b03 cmp r3, #3
800533e: d003 beq.n 8005348 <USB_EPClearStall+0x4c>
8005340: 683b ldr r3, [r7, #0]
8005342: 791b ldrb r3, [r3, #4]
8005344: 2b02 cmp r3, #2
8005346: d138 bne.n 80053ba <USB_EPClearStall+0xbe>
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
8005348: 68bb ldr r3, [r7, #8]
800534a: 015a lsls r2, r3, #5
800534c: 68fb ldr r3, [r7, #12]
800534e: 4413 add r3, r2
8005350: f503 6310 add.w r3, r3, #2304 @ 0x900
8005354: 681b ldr r3, [r3, #0]
8005356: 68ba ldr r2, [r7, #8]
8005358: 0151 lsls r1, r2, #5
800535a: 68fa ldr r2, [r7, #12]
800535c: 440a add r2, r1
800535e: f502 6210 add.w r2, r2, #2304 @ 0x900
8005362: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005366: 6013 str r3, [r2, #0]
8005368: e027 b.n 80053ba <USB_EPClearStall+0xbe>
}
}
else
{
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
800536a: 68bb ldr r3, [r7, #8]
800536c: 015a lsls r2, r3, #5
800536e: 68fb ldr r3, [r7, #12]
8005370: 4413 add r3, r2
8005372: f503 6330 add.w r3, r3, #2816 @ 0xb00
8005376: 681b ldr r3, [r3, #0]
8005378: 68ba ldr r2, [r7, #8]
800537a: 0151 lsls r1, r2, #5
800537c: 68fa ldr r2, [r7, #12]
800537e: 440a add r2, r1
8005380: f502 6230 add.w r2, r2, #2816 @ 0xb00
8005384: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8005388: 6013 str r3, [r2, #0]
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
800538a: 683b ldr r3, [r7, #0]
800538c: 791b ldrb r3, [r3, #4]
800538e: 2b03 cmp r3, #3
8005390: d003 beq.n 800539a <USB_EPClearStall+0x9e>
8005392: 683b ldr r3, [r7, #0]
8005394: 791b ldrb r3, [r3, #4]
8005396: 2b02 cmp r3, #2
8005398: d10f bne.n 80053ba <USB_EPClearStall+0xbe>
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
800539a: 68bb ldr r3, [r7, #8]
800539c: 015a lsls r2, r3, #5
800539e: 68fb ldr r3, [r7, #12]
80053a0: 4413 add r3, r2
80053a2: f503 6330 add.w r3, r3, #2816 @ 0xb00
80053a6: 681b ldr r3, [r3, #0]
80053a8: 68ba ldr r2, [r7, #8]
80053aa: 0151 lsls r1, r2, #5
80053ac: 68fa ldr r2, [r7, #12]
80053ae: 440a add r2, r1
80053b0: f502 6230 add.w r2, r2, #2816 @ 0xb00
80053b4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80053b8: 6013 str r3, [r2, #0]
}
}
return HAL_OK;
80053ba: 2300 movs r3, #0
}
80053bc: 4618 mov r0, r3
80053be: 3714 adds r7, #20
80053c0: 46bd mov sp, r7
80053c2: f85d 7b04 ldr.w r7, [sp], #4
80053c6: 4770 bx lr
080053c8 <USB_SetDevAddress>:
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
80053c8: b480 push {r7}
80053ca: b085 sub sp, #20
80053cc: af00 add r7, sp, #0
80053ce: 6078 str r0, [r7, #4]
80053d0: 460b mov r3, r1
80053d2: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
80053d4: 687b ldr r3, [r7, #4]
80053d6: 60fb str r3, [r7, #12]
USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
80053d8: 68fb ldr r3, [r7, #12]
80053da: f503 6300 add.w r3, r3, #2048 @ 0x800
80053de: 681b ldr r3, [r3, #0]
80053e0: 68fa ldr r2, [r7, #12]
80053e2: f502 6200 add.w r2, r2, #2048 @ 0x800
80053e6: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
80053ea: 6013 str r3, [r2, #0]
USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
80053ec: 68fb ldr r3, [r7, #12]
80053ee: f503 6300 add.w r3, r3, #2048 @ 0x800
80053f2: 681a ldr r2, [r3, #0]
80053f4: 78fb ldrb r3, [r7, #3]
80053f6: 011b lsls r3, r3, #4
80053f8: f403 63fe and.w r3, r3, #2032 @ 0x7f0
80053fc: 68f9 ldr r1, [r7, #12]
80053fe: f501 6100 add.w r1, r1, #2048 @ 0x800
8005402: 4313 orrs r3, r2
8005404: 600b str r3, [r1, #0]
return HAL_OK;
8005406: 2300 movs r3, #0
}
8005408: 4618 mov r0, r3
800540a: 3714 adds r7, #20
800540c: 46bd mov sp, r7
800540e: f85d 7b04 ldr.w r7, [sp], #4
8005412: 4770 bx lr
08005414 <USB_DevConnect>:
* @brief USB_DevConnect : Connect the USB device by enabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
{
8005414: b480 push {r7}
8005416: b085 sub sp, #20
8005418: af00 add r7, sp, #0
800541a: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
800541c: 687b ldr r3, [r7, #4]
800541e: 60fb str r3, [r7, #12]
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
8005420: 68fb ldr r3, [r7, #12]
8005422: f503 6360 add.w r3, r3, #3584 @ 0xe00
8005426: 681b ldr r3, [r3, #0]
8005428: 68fa ldr r2, [r7, #12]
800542a: f502 6260 add.w r2, r2, #3584 @ 0xe00
800542e: f023 0303 bic.w r3, r3, #3
8005432: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
8005434: 68fb ldr r3, [r7, #12]
8005436: f503 6300 add.w r3, r3, #2048 @ 0x800
800543a: 685b ldr r3, [r3, #4]
800543c: 68fa ldr r2, [r7, #12]
800543e: f502 6200 add.w r2, r2, #2048 @ 0x800
8005442: f023 0302 bic.w r3, r3, #2
8005446: 6053 str r3, [r2, #4]
return HAL_OK;
8005448: 2300 movs r3, #0
}
800544a: 4618 mov r0, r3
800544c: 3714 adds r7, #20
800544e: 46bd mov sp, r7
8005450: f85d 7b04 ldr.w r7, [sp], #4
8005454: 4770 bx lr
08005456 <USB_DevDisconnect>:
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
8005456: b480 push {r7}
8005458: b085 sub sp, #20
800545a: af00 add r7, sp, #0
800545c: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
800545e: 687b ldr r3, [r7, #4]
8005460: 60fb str r3, [r7, #12]
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
8005462: 68fb ldr r3, [r7, #12]
8005464: f503 6360 add.w r3, r3, #3584 @ 0xe00
8005468: 681b ldr r3, [r3, #0]
800546a: 68fa ldr r2, [r7, #12]
800546c: f502 6260 add.w r2, r2, #3584 @ 0xe00
8005470: f023 0303 bic.w r3, r3, #3
8005474: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
8005476: 68fb ldr r3, [r7, #12]
8005478: f503 6300 add.w r3, r3, #2048 @ 0x800
800547c: 685b ldr r3, [r3, #4]
800547e: 68fa ldr r2, [r7, #12]
8005480: f502 6200 add.w r2, r2, #2048 @ 0x800
8005484: f043 0302 orr.w r3, r3, #2
8005488: 6053 str r3, [r2, #4]
return HAL_OK;
800548a: 2300 movs r3, #0
}
800548c: 4618 mov r0, r3
800548e: 3714 adds r7, #20
8005490: 46bd mov sp, r7
8005492: f85d 7b04 ldr.w r7, [sp], #4
8005496: 4770 bx lr
08005498 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts: return the global USB interrupt status
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
{
8005498: b480 push {r7}
800549a: b085 sub sp, #20
800549c: af00 add r7, sp, #0
800549e: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->GINTSTS;
80054a0: 687b ldr r3, [r7, #4]
80054a2: 695b ldr r3, [r3, #20]
80054a4: 60fb str r3, [r7, #12]
tmpreg &= USBx->GINTMSK;
80054a6: 687b ldr r3, [r7, #4]
80054a8: 699b ldr r3, [r3, #24]
80054aa: 68fa ldr r2, [r7, #12]
80054ac: 4013 ands r3, r2
80054ae: 60fb str r3, [r7, #12]
return tmpreg;
80054b0: 68fb ldr r3, [r7, #12]
}
80054b2: 4618 mov r0, r3
80054b4: 3714 adds r7, #20
80054b6: 46bd mov sp, r7
80054b8: f85d 7b04 ldr.w r7, [sp], #4
80054bc: 4770 bx lr
080054be <USB_ReadDevAllOutEpInterrupt>:
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
* @param USBx Selected device
* @retval USB Device OUT EP interrupt status
*/
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
80054be: b480 push {r7}
80054c0: b085 sub sp, #20
80054c2: af00 add r7, sp, #0
80054c4: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
80054c6: 687b ldr r3, [r7, #4]
80054c8: 60fb str r3, [r7, #12]
uint32_t tmpreg;
tmpreg = USBx_DEVICE->DAINT;
80054ca: 68fb ldr r3, [r7, #12]
80054cc: f503 6300 add.w r3, r3, #2048 @ 0x800
80054d0: 699b ldr r3, [r3, #24]
80054d2: 60bb str r3, [r7, #8]
tmpreg &= USBx_DEVICE->DAINTMSK;
80054d4: 68fb ldr r3, [r7, #12]
80054d6: f503 6300 add.w r3, r3, #2048 @ 0x800
80054da: 69db ldr r3, [r3, #28]
80054dc: 68ba ldr r2, [r7, #8]
80054de: 4013 ands r3, r2
80054e0: 60bb str r3, [r7, #8]
return ((tmpreg & 0xffff0000U) >> 16);
80054e2: 68bb ldr r3, [r7, #8]
80054e4: 0c1b lsrs r3, r3, #16
}
80054e6: 4618 mov r0, r3
80054e8: 3714 adds r7, #20
80054ea: 46bd mov sp, r7
80054ec: f85d 7b04 ldr.w r7, [sp], #4
80054f0: 4770 bx lr
080054f2 <USB_ReadDevAllInEpInterrupt>:
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
* @param USBx Selected device
* @retval USB Device IN EP interrupt status
*/
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
80054f2: b480 push {r7}
80054f4: b085 sub sp, #20
80054f6: af00 add r7, sp, #0
80054f8: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
80054fa: 687b ldr r3, [r7, #4]
80054fc: 60fb str r3, [r7, #12]
uint32_t tmpreg;
tmpreg = USBx_DEVICE->DAINT;
80054fe: 68fb ldr r3, [r7, #12]
8005500: f503 6300 add.w r3, r3, #2048 @ 0x800
8005504: 699b ldr r3, [r3, #24]
8005506: 60bb str r3, [r7, #8]
tmpreg &= USBx_DEVICE->DAINTMSK;
8005508: 68fb ldr r3, [r7, #12]
800550a: f503 6300 add.w r3, r3, #2048 @ 0x800
800550e: 69db ldr r3, [r3, #28]
8005510: 68ba ldr r2, [r7, #8]
8005512: 4013 ands r3, r2
8005514: 60bb str r3, [r7, #8]
return ((tmpreg & 0xFFFFU));
8005516: 68bb ldr r3, [r7, #8]
8005518: b29b uxth r3, r3
}
800551a: 4618 mov r0, r3
800551c: 3714 adds r7, #20
800551e: 46bd mov sp, r7
8005520: f85d 7b04 ldr.w r7, [sp], #4
8005524: 4770 bx lr
08005526 <USB_ReadDevOutEPInterrupt>:
* @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
8005526: b480 push {r7}
8005528: b085 sub sp, #20
800552a: af00 add r7, sp, #0
800552c: 6078 str r0, [r7, #4]
800552e: 460b mov r3, r1
8005530: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
8005532: 687b ldr r3, [r7, #4]
8005534: 60fb str r3, [r7, #12]
uint32_t tmpreg;
tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
8005536: 78fb ldrb r3, [r7, #3]
8005538: 015a lsls r2, r3, #5
800553a: 68fb ldr r3, [r7, #12]
800553c: 4413 add r3, r2
800553e: f503 6330 add.w r3, r3, #2816 @ 0xb00
8005542: 689b ldr r3, [r3, #8]
8005544: 60bb str r3, [r7, #8]
tmpreg &= USBx_DEVICE->DOEPMSK;
8005546: 68fb ldr r3, [r7, #12]
8005548: f503 6300 add.w r3, r3, #2048 @ 0x800
800554c: 695b ldr r3, [r3, #20]
800554e: 68ba ldr r2, [r7, #8]
8005550: 4013 ands r3, r2
8005552: 60bb str r3, [r7, #8]
return tmpreg;
8005554: 68bb ldr r3, [r7, #8]
}
8005556: 4618 mov r0, r3
8005558: 3714 adds r7, #20
800555a: 46bd mov sp, r7
800555c: f85d 7b04 ldr.w r7, [sp], #4
8005560: 4770 bx lr
08005562 <USB_ReadDevInEPInterrupt>:
* @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
8005562: b480 push {r7}
8005564: b087 sub sp, #28
8005566: af00 add r7, sp, #0
8005568: 6078 str r0, [r7, #4]
800556a: 460b mov r3, r1
800556c: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
800556e: 687b ldr r3, [r7, #4]
8005570: 617b str r3, [r7, #20]
uint32_t tmpreg;
uint32_t msk;
uint32_t emp;
msk = USBx_DEVICE->DIEPMSK;
8005572: 697b ldr r3, [r7, #20]
8005574: f503 6300 add.w r3, r3, #2048 @ 0x800
8005578: 691b ldr r3, [r3, #16]
800557a: 613b str r3, [r7, #16]
emp = USBx_DEVICE->DIEPEMPMSK;
800557c: 697b ldr r3, [r7, #20]
800557e: f503 6300 add.w r3, r3, #2048 @ 0x800
8005582: 6b5b ldr r3, [r3, #52] @ 0x34
8005584: 60fb str r3, [r7, #12]
msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
8005586: 78fb ldrb r3, [r7, #3]
8005588: f003 030f and.w r3, r3, #15
800558c: 68fa ldr r2, [r7, #12]
800558e: fa22 f303 lsr.w r3, r2, r3
8005592: 01db lsls r3, r3, #7
8005594: b2db uxtb r3, r3
8005596: 693a ldr r2, [r7, #16]
8005598: 4313 orrs r3, r2
800559a: 613b str r3, [r7, #16]
tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
800559c: 78fb ldrb r3, [r7, #3]
800559e: 015a lsls r2, r3, #5
80055a0: 697b ldr r3, [r7, #20]
80055a2: 4413 add r3, r2
80055a4: f503 6310 add.w r3, r3, #2304 @ 0x900
80055a8: 689b ldr r3, [r3, #8]
80055aa: 693a ldr r2, [r7, #16]
80055ac: 4013 ands r3, r2
80055ae: 60bb str r3, [r7, #8]
return tmpreg;
80055b0: 68bb ldr r3, [r7, #8]
}
80055b2: 4618 mov r0, r3
80055b4: 371c adds r7, #28
80055b6: 46bd mov sp, r7
80055b8: f85d 7b04 ldr.w r7, [sp], #4
80055bc: 4770 bx lr
080055be <USB_GetMode>:
* This parameter can be one of these values:
* 0 : Host
* 1 : Device
*/
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
80055be: b480 push {r7}
80055c0: b083 sub sp, #12
80055c2: af00 add r7, sp, #0
80055c4: 6078 str r0, [r7, #4]
return ((USBx->GINTSTS) & 0x1U);
80055c6: 687b ldr r3, [r7, #4]
80055c8: 695b ldr r3, [r3, #20]
80055ca: f003 0301 and.w r3, r3, #1
}
80055ce: 4618 mov r0, r3
80055d0: 370c adds r7, #12
80055d2: 46bd mov sp, r7
80055d4: f85d 7b04 ldr.w r7, [sp], #4
80055d8: 4770 bx lr
080055da <USB_ActivateSetup>:
* @brief Activate EP0 for Setup transactions
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
{
80055da: b480 push {r7}
80055dc: b085 sub sp, #20
80055de: af00 add r7, sp, #0
80055e0: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
80055e2: 687b ldr r3, [r7, #4]
80055e4: 60fb str r3, [r7, #12]
/* Set the MPS of the IN EP0 to 64 bytes */
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
80055e6: 68fb ldr r3, [r7, #12]
80055e8: f503 6310 add.w r3, r3, #2304 @ 0x900
80055ec: 681b ldr r3, [r3, #0]
80055ee: 68fa ldr r2, [r7, #12]
80055f0: f502 6210 add.w r2, r2, #2304 @ 0x900
80055f4: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
80055f8: f023 0307 bic.w r3, r3, #7
80055fc: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
80055fe: 68fb ldr r3, [r7, #12]
8005600: f503 6300 add.w r3, r3, #2048 @ 0x800
8005604: 685b ldr r3, [r3, #4]
8005606: 68fa ldr r2, [r7, #12]
8005608: f502 6200 add.w r2, r2, #2048 @ 0x800
800560c: f443 7380 orr.w r3, r3, #256 @ 0x100
8005610: 6053 str r3, [r2, #4]
return HAL_OK;
8005612: 2300 movs r3, #0
}
8005614: 4618 mov r0, r3
8005616: 3714 adds r7, #20
8005618: 46bd mov sp, r7
800561a: f85d 7b04 ldr.w r7, [sp], #4
800561e: 4770 bx lr
08005620 <USB_EP0_OutStart>:
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup)
{
8005620: b480 push {r7}
8005622: b085 sub sp, #20
8005624: af00 add r7, sp, #0
8005626: 6078 str r0, [r7, #4]
8005628: 6039 str r1, [r7, #0]
uint32_t USBx_BASE = (uint32_t)USBx;
800562a: 687b ldr r3, [r7, #4]
800562c: 60fb str r3, [r7, #12]
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
800562e: 687b ldr r3, [r7, #4]
8005630: 333c adds r3, #60 @ 0x3c
8005632: 3304 adds r3, #4
8005634: 681b ldr r3, [r3, #0]
8005636: 60bb str r3, [r7, #8]
UNUSED(psetup);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
8005638: 68bb ldr r3, [r7, #8]
800563a: 4a1c ldr r2, [pc, #112] @ (80056ac <USB_EP0_OutStart+0x8c>)
800563c: 4293 cmp r3, r2
800563e: d90a bls.n 8005656 <USB_EP0_OutStart+0x36>
{
if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
8005640: 68fb ldr r3, [r7, #12]
8005642: f503 6330 add.w r3, r3, #2816 @ 0xb00
8005646: 681b ldr r3, [r3, #0]
8005648: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800564c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8005650: d101 bne.n 8005656 <USB_EP0_OutStart+0x36>
{
return HAL_OK;
8005652: 2300 movs r3, #0
8005654: e024 b.n 80056a0 <USB_EP0_OutStart+0x80>
}
}
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
8005656: 68fb ldr r3, [r7, #12]
8005658: f503 6330 add.w r3, r3, #2816 @ 0xb00
800565c: 461a mov r2, r3
800565e: 2300 movs r3, #0
8005660: 6113 str r3, [r2, #16]
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
8005662: 68fb ldr r3, [r7, #12]
8005664: f503 6330 add.w r3, r3, #2816 @ 0xb00
8005668: 691b ldr r3, [r3, #16]
800566a: 68fa ldr r2, [r7, #12]
800566c: f502 6230 add.w r2, r2, #2816 @ 0xb00
8005670: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8005674: 6113 str r3, [r2, #16]
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
8005676: 68fb ldr r3, [r7, #12]
8005678: f503 6330 add.w r3, r3, #2816 @ 0xb00
800567c: 691b ldr r3, [r3, #16]
800567e: 68fa ldr r2, [r7, #12]
8005680: f502 6230 add.w r2, r2, #2816 @ 0xb00
8005684: f043 0318 orr.w r3, r3, #24
8005688: 6113 str r3, [r2, #16]
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
800568a: 68fb ldr r3, [r7, #12]
800568c: f503 6330 add.w r3, r3, #2816 @ 0xb00
8005690: 691b ldr r3, [r3, #16]
8005692: 68fa ldr r2, [r7, #12]
8005694: f502 6230 add.w r2, r2, #2816 @ 0xb00
8005698: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000
800569c: 6113 str r3, [r2, #16]
return HAL_OK;
800569e: 2300 movs r3, #0
}
80056a0: 4618 mov r0, r3
80056a2: 3714 adds r7, #20
80056a4: 46bd mov sp, r7
80056a6: f85d 7b04 ldr.w r7, [sp], #4
80056aa: 4770 bx lr
80056ac: 4f54300a .word 0x4f54300a
080056b0 <USB_CoreReset>:
* @brief Reset the USB Core (needed after USB clock settings change)
* @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
80056b0: b480 push {r7}
80056b2: b085 sub sp, #20
80056b4: af00 add r7, sp, #0
80056b6: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
80056b8: 2300 movs r3, #0
80056ba: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
80056bc: 68fb ldr r3, [r7, #12]
80056be: 3301 adds r3, #1
80056c0: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
80056c2: 68fb ldr r3, [r7, #12]
80056c4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
80056c8: d901 bls.n 80056ce <USB_CoreReset+0x1e>
{
return HAL_TIMEOUT;
80056ca: 2303 movs r3, #3
80056cc: e01b b.n 8005706 <USB_CoreReset+0x56>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
80056ce: 687b ldr r3, [r7, #4]
80056d0: 691b ldr r3, [r3, #16]
80056d2: 2b00 cmp r3, #0
80056d4: daf2 bge.n 80056bc <USB_CoreReset+0xc>
/* Core Soft Reset */
count = 0U;
80056d6: 2300 movs r3, #0
80056d8: 60fb str r3, [r7, #12]
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
80056da: 687b ldr r3, [r7, #4]
80056dc: 691b ldr r3, [r3, #16]
80056de: f043 0201 orr.w r2, r3, #1
80056e2: 687b ldr r3, [r7, #4]
80056e4: 611a str r2, [r3, #16]
do
{
count++;
80056e6: 68fb ldr r3, [r7, #12]
80056e8: 3301 adds r3, #1
80056ea: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
80056ec: 68fb ldr r3, [r7, #12]
80056ee: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
80056f2: d901 bls.n 80056f8 <USB_CoreReset+0x48>
{
return HAL_TIMEOUT;
80056f4: 2303 movs r3, #3
80056f6: e006 b.n 8005706 <USB_CoreReset+0x56>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
80056f8: 687b ldr r3, [r7, #4]
80056fa: 691b ldr r3, [r3, #16]
80056fc: f003 0301 and.w r3, r3, #1
8005700: 2b01 cmp r3, #1
8005702: d0f0 beq.n 80056e6 <USB_CoreReset+0x36>
return HAL_OK;
8005704: 2300 movs r3, #0
}
8005706: 4618 mov r0, r3
8005708: 3714 adds r7, #20
800570a: 46bd mov sp, r7
800570c: f85d 7b04 ldr.w r7, [sp], #4
8005710: 4770 bx lr
...
08005714 <USBD_CUSTOM_HID_Init>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CUSTOM_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8005714: b580 push {r7, lr}
8005716: b084 sub sp, #16
8005718: af00 add r7, sp, #0
800571a: 6078 str r0, [r7, #4]
800571c: 460b mov r3, r1
800571e: 70fb strb r3, [r7, #3]
UNUSED(cfgidx);
USBD_CUSTOM_HID_HandleTypeDef *hhid;
hhid = (USBD_CUSTOM_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_CUSTOM_HID_HandleTypeDef));
8005720: 2018 movs r0, #24
8005722: f002 fc8d bl 8008040 <USBD_static_malloc>
8005726: 60f8 str r0, [r7, #12]
if (hhid == NULL)
8005728: 68fb ldr r3, [r7, #12]
800572a: 2b00 cmp r3, #0
800572c: d109 bne.n 8005742 <USBD_CUSTOM_HID_Init+0x2e>
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
800572e: 687b ldr r3, [r7, #4]
8005730: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005734: 687b ldr r3, [r7, #4]
8005736: 32b0 adds r2, #176 @ 0xb0
8005738: 2100 movs r1, #0
800573a: f843 1022 str.w r1, [r3, r2, lsl #2]
return (uint8_t)USBD_EMEM;
800573e: 2302 movs r3, #2
8005740: e08a b.n 8005858 <USBD_CUSTOM_HID_Init+0x144>
}
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
8005742: 687b ldr r3, [r7, #4]
8005744: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005748: 687b ldr r3, [r7, #4]
800574a: 32b0 adds r2, #176 @ 0xb0
800574c: 68f9 ldr r1, [r7, #12]
800574e: f843 1022 str.w r1, [r3, r2, lsl #2]
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
8005752: 687b ldr r3, [r7, #4]
8005754: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005758: 687b ldr r3, [r7, #4]
800575a: 32b0 adds r2, #176 @ 0xb0
800575c: f853 2022 ldr.w r2, [r3, r2, lsl #2]
8005760: 687b ldr r3, [r7, #4]
8005762: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
/* Get the Endpoints addresses allocated for this class instance */
CUSTOMHIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
CUSTOMHIDOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
8005766: 687b ldr r3, [r7, #4]
8005768: 7c1b ldrb r3, [r3, #16]
800576a: 2b00 cmp r3, #0
800576c: d11b bne.n 80057a6 <USBD_CUSTOM_HID_Init+0x92>
{
pdev->ep_in[CUSTOMHIDInEpAdd & 0xFU].bInterval = CUSTOM_HID_HS_BINTERVAL;
800576e: 4b3c ldr r3, [pc, #240] @ (8005860 <USBD_CUSTOM_HID_Init+0x14c>)
8005770: 781b ldrb r3, [r3, #0]
8005772: f003 020f and.w r2, r3, #15
8005776: 6879 ldr r1, [r7, #4]
8005778: 4613 mov r3, r2
800577a: 009b lsls r3, r3, #2
800577c: 4413 add r3, r2
800577e: 009b lsls r3, r3, #2
8005780: 440b add r3, r1
8005782: 3326 adds r3, #38 @ 0x26
8005784: 2205 movs r2, #5
8005786: 801a strh r2, [r3, #0]
pdev->ep_out[CUSTOMHIDOutEpAdd & 0xFU].bInterval = CUSTOM_HID_HS_BINTERVAL;
8005788: 4b36 ldr r3, [pc, #216] @ (8005864 <USBD_CUSTOM_HID_Init+0x150>)
800578a: 781b ldrb r3, [r3, #0]
800578c: f003 020f and.w r2, r3, #15
8005790: 6879 ldr r1, [r7, #4]
8005792: 4613 mov r3, r2
8005794: 009b lsls r3, r3, #2
8005796: 4413 add r3, r2
8005798: 009b lsls r3, r3, #2
800579a: 440b add r3, r1
800579c: f503 73b3 add.w r3, r3, #358 @ 0x166
80057a0: 2205 movs r2, #5
80057a2: 801a strh r2, [r3, #0]
80057a4: e01a b.n 80057dc <USBD_CUSTOM_HID_Init+0xc8>
}
else /* LOW and FULL-speed endpoints */
{
pdev->ep_in[CUSTOMHIDInEpAdd & 0xFU].bInterval = CUSTOM_HID_FS_BINTERVAL;
80057a6: 4b2e ldr r3, [pc, #184] @ (8005860 <USBD_CUSTOM_HID_Init+0x14c>)
80057a8: 781b ldrb r3, [r3, #0]
80057aa: f003 020f and.w r2, r3, #15
80057ae: 6879 ldr r1, [r7, #4]
80057b0: 4613 mov r3, r2
80057b2: 009b lsls r3, r3, #2
80057b4: 4413 add r3, r2
80057b6: 009b lsls r3, r3, #2
80057b8: 440b add r3, r1
80057ba: 3326 adds r3, #38 @ 0x26
80057bc: 2205 movs r2, #5
80057be: 801a strh r2, [r3, #0]
pdev->ep_out[CUSTOMHIDOutEpAdd & 0xFU].bInterval = CUSTOM_HID_FS_BINTERVAL;
80057c0: 4b28 ldr r3, [pc, #160] @ (8005864 <USBD_CUSTOM_HID_Init+0x150>)
80057c2: 781b ldrb r3, [r3, #0]
80057c4: f003 020f and.w r2, r3, #15
80057c8: 6879 ldr r1, [r7, #4]
80057ca: 4613 mov r3, r2
80057cc: 009b lsls r3, r3, #2
80057ce: 4413 add r3, r2
80057d0: 009b lsls r3, r3, #2
80057d2: 440b add r3, r1
80057d4: f503 73b3 add.w r3, r3, #358 @ 0x166
80057d8: 2205 movs r2, #5
80057da: 801a strh r2, [r3, #0]
}
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, CUSTOMHIDInEpAdd, USBD_EP_TYPE_INTR,
80057dc: 4b20 ldr r3, [pc, #128] @ (8005860 <USBD_CUSTOM_HID_Init+0x14c>)
80057de: 7819 ldrb r1, [r3, #0]
80057e0: 2302 movs r3, #2
80057e2: 2203 movs r2, #3
80057e4: 6878 ldr r0, [r7, #4]
80057e6: f002 fa2b bl 8007c40 <USBD_LL_OpenEP>
CUSTOM_HID_EPIN_SIZE);
pdev->ep_in[CUSTOMHIDInEpAdd & 0xFU].is_used = 1U;
80057ea: 4b1d ldr r3, [pc, #116] @ (8005860 <USBD_CUSTOM_HID_Init+0x14c>)
80057ec: 781b ldrb r3, [r3, #0]
80057ee: f003 020f and.w r2, r3, #15
80057f2: 6879 ldr r1, [r7, #4]
80057f4: 4613 mov r3, r2
80057f6: 009b lsls r3, r3, #2
80057f8: 4413 add r3, r2
80057fa: 009b lsls r3, r3, #2
80057fc: 440b add r3, r1
80057fe: 3324 adds r3, #36 @ 0x24
8005800: 2201 movs r2, #1
8005802: 801a strh r2, [r3, #0]
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, CUSTOMHIDOutEpAdd, USBD_EP_TYPE_INTR,
8005804: 4b17 ldr r3, [pc, #92] @ (8005864 <USBD_CUSTOM_HID_Init+0x150>)
8005806: 7819 ldrb r1, [r3, #0]
8005808: 2302 movs r3, #2
800580a: 2203 movs r2, #3
800580c: 6878 ldr r0, [r7, #4]
800580e: f002 fa17 bl 8007c40 <USBD_LL_OpenEP>
CUSTOM_HID_EPOUT_SIZE);
pdev->ep_out[CUSTOMHIDOutEpAdd & 0xFU].is_used = 1U;
8005812: 4b14 ldr r3, [pc, #80] @ (8005864 <USBD_CUSTOM_HID_Init+0x150>)
8005814: 781b ldrb r3, [r3, #0]
8005816: f003 020f and.w r2, r3, #15
800581a: 6879 ldr r1, [r7, #4]
800581c: 4613 mov r3, r2
800581e: 009b lsls r3, r3, #2
8005820: 4413 add r3, r2
8005822: 009b lsls r3, r3, #2
8005824: 440b add r3, r1
8005826: f503 73b2 add.w r3, r3, #356 @ 0x164
800582a: 2201 movs r2, #1
800582c: 801a strh r2, [r3, #0]
hhid->state = CUSTOM_HID_IDLE;
800582e: 68fb ldr r3, [r7, #12]
8005830: 2200 movs r2, #0
8005832: 751a strb r2, [r3, #20]
((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData[pdev->classId])->Init();
8005834: 687b ldr r3, [r7, #4]
8005836: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800583a: 687a ldr r2, [r7, #4]
800583c: 33b0 adds r3, #176 @ 0xb0
800583e: 009b lsls r3, r3, #2
8005840: 4413 add r3, r2
8005842: 685b ldr r3, [r3, #4]
8005844: 685b ldr r3, [r3, #4]
8005846: 4798 blx r3
#ifndef USBD_CUSTOMHID_OUT_PREPARE_RECEIVE_DISABLED
/* Prepare Out endpoint to receive 1st packet */
(void)USBD_LL_PrepareReceive(pdev, CUSTOMHIDOutEpAdd, hhid->Report_buf,
8005848: 4b06 ldr r3, [pc, #24] @ (8005864 <USBD_CUSTOM_HID_Init+0x150>)
800584a: 7819 ldrb r1, [r3, #0]
800584c: 68fa ldr r2, [r7, #12]
800584e: 2304 movs r3, #4
8005850: 6878 ldr r0, [r7, #4]
8005852: f002 fb6f bl 8007f34 <USBD_LL_PrepareReceive>
USBD_CUSTOMHID_OUTREPORT_BUF_SIZE);
#endif /* USBD_CUSTOMHID_OUT_PREPARE_RECEIVE_DISABLED */
return (uint8_t)USBD_OK;
8005856: 2300 movs r3, #0
}
8005858: 4618 mov r0, r3
800585a: 3710 adds r7, #16
800585c: 46bd mov sp, r7
800585e: bd80 pop {r7, pc}
8005860: 20000086 .word 0x20000086
8005864: 20000087 .word 0x20000087
08005868 <USBD_CUSTOM_HID_DeInit>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CUSTOM_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8005868: b580 push {r7, lr}
800586a: b082 sub sp, #8
800586c: af00 add r7, sp, #0
800586e: 6078 str r0, [r7, #4]
8005870: 460b mov r3, r1
8005872: 70fb strb r3, [r7, #3]
CUSTOMHIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
CUSTOMHIDOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
#endif /* USE_USBD_COMPOSITE */
/* Close CUSTOM_HID EP IN */
(void)USBD_LL_CloseEP(pdev, CUSTOMHIDInEpAdd);
8005874: 4b37 ldr r3, [pc, #220] @ (8005954 <USBD_CUSTOM_HID_DeInit+0xec>)
8005876: 781b ldrb r3, [r3, #0]
8005878: 4619 mov r1, r3
800587a: 6878 ldr r0, [r7, #4]
800587c: f002 fa1e bl 8007cbc <USBD_LL_CloseEP>
pdev->ep_in[CUSTOMHIDInEpAdd & 0xFU].is_used = 0U;
8005880: 4b34 ldr r3, [pc, #208] @ (8005954 <USBD_CUSTOM_HID_DeInit+0xec>)
8005882: 781b ldrb r3, [r3, #0]
8005884: f003 020f and.w r2, r3, #15
8005888: 6879 ldr r1, [r7, #4]
800588a: 4613 mov r3, r2
800588c: 009b lsls r3, r3, #2
800588e: 4413 add r3, r2
8005890: 009b lsls r3, r3, #2
8005892: 440b add r3, r1
8005894: 3324 adds r3, #36 @ 0x24
8005896: 2200 movs r2, #0
8005898: 801a strh r2, [r3, #0]
pdev->ep_in[CUSTOMHIDInEpAdd & 0xFU].bInterval = 0U;
800589a: 4b2e ldr r3, [pc, #184] @ (8005954 <USBD_CUSTOM_HID_DeInit+0xec>)
800589c: 781b ldrb r3, [r3, #0]
800589e: f003 020f and.w r2, r3, #15
80058a2: 6879 ldr r1, [r7, #4]
80058a4: 4613 mov r3, r2
80058a6: 009b lsls r3, r3, #2
80058a8: 4413 add r3, r2
80058aa: 009b lsls r3, r3, #2
80058ac: 440b add r3, r1
80058ae: 3326 adds r3, #38 @ 0x26
80058b0: 2200 movs r2, #0
80058b2: 801a strh r2, [r3, #0]
/* Close CUSTOM_HID EP OUT */
(void)USBD_LL_CloseEP(pdev, CUSTOMHIDOutEpAdd);
80058b4: 4b28 ldr r3, [pc, #160] @ (8005958 <USBD_CUSTOM_HID_DeInit+0xf0>)
80058b6: 781b ldrb r3, [r3, #0]
80058b8: 4619 mov r1, r3
80058ba: 6878 ldr r0, [r7, #4]
80058bc: f002 f9fe bl 8007cbc <USBD_LL_CloseEP>
pdev->ep_out[CUSTOMHIDOutEpAdd & 0xFU].is_used = 0U;
80058c0: 4b25 ldr r3, [pc, #148] @ (8005958 <USBD_CUSTOM_HID_DeInit+0xf0>)
80058c2: 781b ldrb r3, [r3, #0]
80058c4: f003 020f and.w r2, r3, #15
80058c8: 6879 ldr r1, [r7, #4]
80058ca: 4613 mov r3, r2
80058cc: 009b lsls r3, r3, #2
80058ce: 4413 add r3, r2
80058d0: 009b lsls r3, r3, #2
80058d2: 440b add r3, r1
80058d4: f503 73b2 add.w r3, r3, #356 @ 0x164
80058d8: 2200 movs r2, #0
80058da: 801a strh r2, [r3, #0]
pdev->ep_out[CUSTOMHIDOutEpAdd & 0xFU].bInterval = 0U;
80058dc: 4b1e ldr r3, [pc, #120] @ (8005958 <USBD_CUSTOM_HID_DeInit+0xf0>)
80058de: 781b ldrb r3, [r3, #0]
80058e0: f003 020f and.w r2, r3, #15
80058e4: 6879 ldr r1, [r7, #4]
80058e6: 4613 mov r3, r2
80058e8: 009b lsls r3, r3, #2
80058ea: 4413 add r3, r2
80058ec: 009b lsls r3, r3, #2
80058ee: 440b add r3, r1
80058f0: f503 73b3 add.w r3, r3, #358 @ 0x166
80058f4: 2200 movs r2, #0
80058f6: 801a strh r2, [r3, #0]
/* Free allocated memory */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
80058f8: 687b ldr r3, [r7, #4]
80058fa: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
80058fe: 687b ldr r3, [r7, #4]
8005900: 32b0 adds r2, #176 @ 0xb0
8005902: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005906: 2b00 cmp r3, #0
8005908: d01f beq.n 800594a <USBD_CUSTOM_HID_DeInit+0xe2>
{
((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData[pdev->classId])->DeInit();
800590a: 687b ldr r3, [r7, #4]
800590c: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8005910: 687a ldr r2, [r7, #4]
8005912: 33b0 adds r3, #176 @ 0xb0
8005914: 009b lsls r3, r3, #2
8005916: 4413 add r3, r2
8005918: 685b ldr r3, [r3, #4]
800591a: 689b ldr r3, [r3, #8]
800591c: 4798 blx r3
USBD_free(pdev->pClassDataCmsit[pdev->classId]);
800591e: 687b ldr r3, [r7, #4]
8005920: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005924: 687b ldr r3, [r7, #4]
8005926: 32b0 adds r2, #176 @ 0xb0
8005928: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800592c: 4618 mov r0, r3
800592e: f002 fb95 bl 800805c <USBD_static_free>
pdev->pClassDataCmsit[pdev->classId] = NULL;
8005932: 687b ldr r3, [r7, #4]
8005934: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005938: 687b ldr r3, [r7, #4]
800593a: 32b0 adds r2, #176 @ 0xb0
800593c: 2100 movs r1, #0
800593e: f843 1022 str.w r1, [r3, r2, lsl #2]
pdev->pClassData = NULL;
8005942: 687b ldr r3, [r7, #4]
8005944: 2200 movs r2, #0
8005946: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
}
return (uint8_t)USBD_OK;
800594a: 2300 movs r3, #0
}
800594c: 4618 mov r0, r3
800594e: 3708 adds r7, #8
8005950: 46bd mov sp, r7
8005952: bd80 pop {r7, pc}
8005954: 20000086 .word 0x20000086
8005958: 20000087 .word 0x20000087
0800595c <USBD_CUSTOM_HID_Setup>:
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_CUSTOM_HID_Setup(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800595c: b580 push {r7, lr}
800595e: b088 sub sp, #32
8005960: af00 add r7, sp, #0
8005962: 6078 str r0, [r7, #4]
8005964: 6039 str r1, [r7, #0]
USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
8005966: 687b ldr r3, [r7, #4]
8005968: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800596c: 687b ldr r3, [r7, #4]
800596e: 32b0 adds r2, #176 @ 0xb0
8005970: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005974: 613b str r3, [r7, #16]
uint16_t len = 0U;
8005976: 2300 movs r3, #0
8005978: 83fb strh r3, [r7, #30]
#ifdef USBD_CUSTOMHID_CTRL_REQ_GET_REPORT_ENABLED
uint16_t ReportLength = 0U;
#endif /* USBD_CUSTOMHID_CTRL_REQ_GET_REPORT_ENABLED */
uint8_t *pbuf = NULL;
800597a: 2300 movs r3, #0
800597c: 61bb str r3, [r7, #24]
uint16_t status_info = 0U;
800597e: 2300 movs r3, #0
8005980: 81fb strh r3, [r7, #14]
USBD_StatusTypeDef ret = USBD_OK;
8005982: 2300 movs r3, #0
8005984: 75fb strb r3, [r7, #23]
if (hhid == NULL)
8005986: 693b ldr r3, [r7, #16]
8005988: 2b00 cmp r3, #0
800598a: d101 bne.n 8005990 <USBD_CUSTOM_HID_Setup+0x34>
{
return (uint8_t)USBD_FAIL;
800598c: 2303 movs r3, #3
800598e: e102 b.n 8005b96 <USBD_CUSTOM_HID_Setup+0x23a>
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8005990: 683b ldr r3, [r7, #0]
8005992: 781b ldrb r3, [r3, #0]
8005994: f003 0360 and.w r3, r3, #96 @ 0x60
8005998: 2b00 cmp r3, #0
800599a: d056 beq.n 8005a4a <USBD_CUSTOM_HID_Setup+0xee>
800599c: 2b20 cmp r3, #32
800599e: f040 80f2 bne.w 8005b86 <USBD_CUSTOM_HID_Setup+0x22a>
{
case USB_REQ_TYPE_CLASS:
switch (req->bRequest)
80059a2: 683b ldr r3, [r7, #0]
80059a4: 785b ldrb r3, [r3, #1]
80059a6: 3b02 subs r3, #2
80059a8: 2b09 cmp r3, #9
80059aa: d846 bhi.n 8005a3a <USBD_CUSTOM_HID_Setup+0xde>
80059ac: a201 add r2, pc, #4 @ (adr r2, 80059b4 <USBD_CUSTOM_HID_Setup+0x58>)
80059ae: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80059b2: bf00 nop
80059b4: 08005a0d .word 0x08005a0d
80059b8: 080059eb .word 0x080059eb
80059bc: 08005a3b .word 0x08005a3b
80059c0: 08005a3b .word 0x08005a3b
80059c4: 08005a3b .word 0x08005a3b
80059c8: 08005a3b .word 0x08005a3b
80059cc: 08005a3b .word 0x08005a3b
80059d0: 08005a1d .word 0x08005a1d
80059d4: 080059fb .word 0x080059fb
80059d8: 080059dd .word 0x080059dd
{
case CUSTOM_HID_REQ_SET_PROTOCOL:
hhid->Protocol = (uint8_t)(req->wValue);
80059dc: 683b ldr r3, [r7, #0]
80059de: 885b ldrh r3, [r3, #2]
80059e0: b2db uxtb r3, r3
80059e2: 461a mov r2, r3
80059e4: 693b ldr r3, [r7, #16]
80059e6: 605a str r2, [r3, #4]
break;
80059e8: e02e b.n 8005a48 <USBD_CUSTOM_HID_Setup+0xec>
case CUSTOM_HID_REQ_GET_PROTOCOL:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
80059ea: 693b ldr r3, [r7, #16]
80059ec: 3304 adds r3, #4
80059ee: 2201 movs r2, #1
80059f0: 4619 mov r1, r3
80059f2: 6878 ldr r0, [r7, #4]
80059f4: f001 fd0a bl 800740c <USBD_CtlSendData>
break;
80059f8: e026 b.n 8005a48 <USBD_CUSTOM_HID_Setup+0xec>
case CUSTOM_HID_REQ_SET_IDLE:
hhid->IdleState = (uint8_t)(req->wValue >> 8);
80059fa: 683b ldr r3, [r7, #0]
80059fc: 885b ldrh r3, [r3, #2]
80059fe: 0a1b lsrs r3, r3, #8
8005a00: b29b uxth r3, r3
8005a02: b2db uxtb r3, r3
8005a04: 461a mov r2, r3
8005a06: 693b ldr r3, [r7, #16]
8005a08: 609a str r2, [r3, #8]
break;
8005a0a: e01d b.n 8005a48 <USBD_CUSTOM_HID_Setup+0xec>
case CUSTOM_HID_REQ_GET_IDLE:
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
8005a0c: 693b ldr r3, [r7, #16]
8005a0e: 3308 adds r3, #8
8005a10: 2201 movs r2, #1
8005a12: 4619 mov r1, r3
8005a14: 6878 ldr r0, [r7, #4]
8005a16: f001 fcf9 bl 800740c <USBD_CtlSendData>
break;
8005a1a: e015 b.n 8005a48 <USBD_CUSTOM_HID_Setup+0xec>
((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData[pdev->classId])->CtrlReqComplete(req->bRequest,
req->wLength);
}
#endif /* USBD_CUSTOMHID_CTRL_REQ_COMPLETE_CALLBACK_ENABLED */
#ifndef USBD_CUSTOMHID_EP0_OUT_PREPARE_RECEIVE_DISABLED
hhid->IsReportAvailable = 1U;
8005a1c: 693b ldr r3, [r7, #16]
8005a1e: 2201 movs r2, #1
8005a20: 611a str r2, [r3, #16]
(void)USBD_CtlPrepareRx(pdev, hhid->Report_buf,
8005a22: 6939 ldr r1, [r7, #16]
MIN(req->wLength, USBD_CUSTOMHID_OUTREPORT_BUF_SIZE));
8005a24: 683b ldr r3, [r7, #0]
8005a26: 88db ldrh r3, [r3, #6]
8005a28: 2b04 cmp r3, #4
8005a2a: bf28 it cs
8005a2c: 2304 movcs r3, #4
8005a2e: b29b uxth r3, r3
(void)USBD_CtlPrepareRx(pdev, hhid->Report_buf,
8005a30: 461a mov r2, r3
8005a32: 6878 ldr r0, [r7, #4]
8005a34: f001 fd16 bl 8007464 <USBD_CtlPrepareRx>
#endif /* USBD_CUSTOMHID_EP0_OUT_PREPARE_RECEIVE_DISABLED */
break;
8005a38: e006 b.n 8005a48 <USBD_CUSTOM_HID_Setup+0xec>
}
break;
#endif /* USBD_CUSTOMHID_CTRL_REQ_GET_REPORT_ENABLED */
default:
USBD_CtlError(pdev, req);
8005a3a: 6839 ldr r1, [r7, #0]
8005a3c: 6878 ldr r0, [r7, #4]
8005a3e: f001 fc68 bl 8007312 <USBD_CtlError>
ret = USBD_FAIL;
8005a42: 2303 movs r3, #3
8005a44: 75fb strb r3, [r7, #23]
break;
8005a46: bf00 nop
}
break;
8005a48: e0a4 b.n 8005b94 <USBD_CUSTOM_HID_Setup+0x238>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8005a4a: 683b ldr r3, [r7, #0]
8005a4c: 785b ldrb r3, [r3, #1]
8005a4e: 2b0b cmp r3, #11
8005a50: f200 8090 bhi.w 8005b74 <USBD_CUSTOM_HID_Setup+0x218>
8005a54: a201 add r2, pc, #4 @ (adr r2, 8005a5c <USBD_CUSTOM_HID_Setup+0x100>)
8005a56: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005a5a: bf00 nop
8005a5c: 08005a8d .word 0x08005a8d
8005a60: 08005b83 .word 0x08005b83
8005a64: 08005b75 .word 0x08005b75
8005a68: 08005b75 .word 0x08005b75
8005a6c: 08005b75 .word 0x08005b75
8005a70: 08005b75 .word 0x08005b75
8005a74: 08005ab7 .word 0x08005ab7
8005a78: 08005b75 .word 0x08005b75
8005a7c: 08005b75 .word 0x08005b75
8005a80: 08005b75 .word 0x08005b75
8005a84: 08005b23 .word 0x08005b23
8005a88: 08005b4d .word 0x08005b4d
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8005a8c: 687b ldr r3, [r7, #4]
8005a8e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8005a92: b2db uxtb r3, r3
8005a94: 2b03 cmp r3, #3
8005a96: d107 bne.n 8005aa8 <USBD_CUSTOM_HID_Setup+0x14c>
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
8005a98: f107 030e add.w r3, r7, #14
8005a9c: 2202 movs r2, #2
8005a9e: 4619 mov r1, r3
8005aa0: 6878 ldr r0, [r7, #4]
8005aa2: f001 fcb3 bl 800740c <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
8005aa6: e06d b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
USBD_CtlError(pdev, req);
8005aa8: 6839 ldr r1, [r7, #0]
8005aaa: 6878 ldr r0, [r7, #4]
8005aac: f001 fc31 bl 8007312 <USBD_CtlError>
ret = USBD_FAIL;
8005ab0: 2303 movs r3, #3
8005ab2: 75fb strb r3, [r7, #23]
break;
8005ab4: e066 b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
case USB_REQ_GET_DESCRIPTOR:
if ((req->wValue >> 8) == CUSTOM_HID_REPORT_DESC)
8005ab6: 683b ldr r3, [r7, #0]
8005ab8: 885b ldrh r3, [r3, #2]
8005aba: 0a1b lsrs r3, r3, #8
8005abc: b29b uxth r3, r3
8005abe: 2b22 cmp r3, #34 @ 0x22
8005ac0: d110 bne.n 8005ae4 <USBD_CUSTOM_HID_Setup+0x188>
{
len = MIN(USBD_CUSTOM_HID_REPORT_DESC_SIZE, req->wLength);
8005ac2: 683b ldr r3, [r7, #0]
8005ac4: 88db ldrh r3, [r3, #6]
8005ac6: 2b32 cmp r3, #50 @ 0x32
8005ac8: bf28 it cs
8005aca: 2332 movcs r3, #50 @ 0x32
8005acc: 83fb strh r3, [r7, #30]
pbuf = ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData[pdev->classId])->pReport;
8005ace: 687b ldr r3, [r7, #4]
8005ad0: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8005ad4: 687a ldr r2, [r7, #4]
8005ad6: 33b0 adds r3, #176 @ 0xb0
8005ad8: 009b lsls r3, r3, #2
8005ada: 4413 add r3, r2
8005adc: 685b ldr r3, [r3, #4]
8005ade: 681b ldr r3, [r3, #0]
8005ae0: 61bb str r3, [r7, #24]
8005ae2: e00d b.n 8005b00 <USBD_CUSTOM_HID_Setup+0x1a4>
}
else
{
if ((req->wValue >> 8) == CUSTOM_HID_DESCRIPTOR_TYPE)
8005ae4: 683b ldr r3, [r7, #0]
8005ae6: 885b ldrh r3, [r3, #2]
8005ae8: 0a1b lsrs r3, r3, #8
8005aea: b29b uxth r3, r3
8005aec: 2b21 cmp r3, #33 @ 0x21
8005aee: d107 bne.n 8005b00 <USBD_CUSTOM_HID_Setup+0x1a4>
{
pbuf = USBD_CUSTOM_HID_Desc;
8005af0: 4b2b ldr r3, [pc, #172] @ (8005ba0 <USBD_CUSTOM_HID_Setup+0x244>)
8005af2: 61bb str r3, [r7, #24]
len = MIN(USB_CUSTOM_HID_DESC_SIZ, req->wLength);
8005af4: 683b ldr r3, [r7, #0]
8005af6: 88db ldrh r3, [r3, #6]
8005af8: 2b09 cmp r3, #9
8005afa: bf28 it cs
8005afc: 2309 movcs r3, #9
8005afe: 83fb strh r3, [r7, #30]
}
}
if (pbuf != NULL)
8005b00: 69bb ldr r3, [r7, #24]
8005b02: 2b00 cmp r3, #0
8005b04: d006 beq.n 8005b14 <USBD_CUSTOM_HID_Setup+0x1b8>
{
(void)USBD_CtlSendData(pdev, pbuf, len);
8005b06: 8bfb ldrh r3, [r7, #30]
8005b08: 461a mov r2, r3
8005b0a: 69b9 ldr r1, [r7, #24]
8005b0c: 6878 ldr r0, [r7, #4]
8005b0e: f001 fc7d bl 800740c <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
8005b12: e037 b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
USBD_CtlError(pdev, req);
8005b14: 6839 ldr r1, [r7, #0]
8005b16: 6878 ldr r0, [r7, #4]
8005b18: f001 fbfb bl 8007312 <USBD_CtlError>
ret = USBD_FAIL;
8005b1c: 2303 movs r3, #3
8005b1e: 75fb strb r3, [r7, #23]
break;
8005b20: e030 b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8005b22: 687b ldr r3, [r7, #4]
8005b24: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8005b28: b2db uxtb r3, r3
8005b2a: 2b03 cmp r3, #3
8005b2c: d107 bne.n 8005b3e <USBD_CUSTOM_HID_Setup+0x1e2>
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
8005b2e: 693b ldr r3, [r7, #16]
8005b30: 330c adds r3, #12
8005b32: 2201 movs r2, #1
8005b34: 4619 mov r1, r3
8005b36: 6878 ldr r0, [r7, #4]
8005b38: f001 fc68 bl 800740c <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
8005b3c: e022 b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
USBD_CtlError(pdev, req);
8005b3e: 6839 ldr r1, [r7, #0]
8005b40: 6878 ldr r0, [r7, #4]
8005b42: f001 fbe6 bl 8007312 <USBD_CtlError>
ret = USBD_FAIL;
8005b46: 2303 movs r3, #3
8005b48: 75fb strb r3, [r7, #23]
break;
8005b4a: e01b b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8005b4c: 687b ldr r3, [r7, #4]
8005b4e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8005b52: b2db uxtb r3, r3
8005b54: 2b03 cmp r3, #3
8005b56: d106 bne.n 8005b66 <USBD_CUSTOM_HID_Setup+0x20a>
{
hhid->AltSetting = (uint8_t)(req->wValue);
8005b58: 683b ldr r3, [r7, #0]
8005b5a: 885b ldrh r3, [r3, #2]
8005b5c: b2db uxtb r3, r3
8005b5e: 461a mov r2, r3
8005b60: 693b ldr r3, [r7, #16]
8005b62: 60da str r2, [r3, #12]
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
8005b64: e00e b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
USBD_CtlError(pdev, req);
8005b66: 6839 ldr r1, [r7, #0]
8005b68: 6878 ldr r0, [r7, #4]
8005b6a: f001 fbd2 bl 8007312 <USBD_CtlError>
ret = USBD_FAIL;
8005b6e: 2303 movs r3, #3
8005b70: 75fb strb r3, [r7, #23]
break;
8005b72: e007 b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
8005b74: 6839 ldr r1, [r7, #0]
8005b76: 6878 ldr r0, [r7, #4]
8005b78: f001 fbcb bl 8007312 <USBD_CtlError>
ret = USBD_FAIL;
8005b7c: 2303 movs r3, #3
8005b7e: 75fb strb r3, [r7, #23]
break;
8005b80: e000 b.n 8005b84 <USBD_CUSTOM_HID_Setup+0x228>
break;
8005b82: bf00 nop
}
break;
8005b84: e006 b.n 8005b94 <USBD_CUSTOM_HID_Setup+0x238>
default:
USBD_CtlError(pdev, req);
8005b86: 6839 ldr r1, [r7, #0]
8005b88: 6878 ldr r0, [r7, #4]
8005b8a: f001 fbc2 bl 8007312 <USBD_CtlError>
ret = USBD_FAIL;
8005b8e: 2303 movs r3, #3
8005b90: 75fb strb r3, [r7, #23]
break;
8005b92: bf00 nop
}
return (uint8_t)ret;
8005b94: 7dfb ldrb r3, [r7, #23]
}
8005b96: 4618 mov r0, r3
8005b98: 3720 adds r7, #32
8005b9a: 46bd mov sp, r7
8005b9c: bd80 pop {r7, pc}
8005b9e: bf00 nop
8005ba0: 20000070 .word 0x20000070
08005ba4 <USBD_CUSTOM_HID_SendReport>:
{
USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
#else
uint8_t USBD_CUSTOM_HID_SendReport(USBD_HandleTypeDef *pdev,
uint8_t *report, uint16_t len)
{
8005ba4: b580 push {r7, lr}
8005ba6: b086 sub sp, #24
8005ba8: af00 add r7, sp, #0
8005baa: 60f8 str r0, [r7, #12]
8005bac: 60b9 str r1, [r7, #8]
8005bae: 4613 mov r3, r2
8005bb0: 80fb strh r3, [r7, #6]
USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
8005bb2: 68fb ldr r3, [r7, #12]
8005bb4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005bb8: 68fb ldr r3, [r7, #12]
8005bba: 32b0 adds r2, #176 @ 0xb0
8005bbc: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005bc0: 617b str r3, [r7, #20]
#endif /* USE_USBD_COMPOSITE */
if (hhid == NULL)
8005bc2: 697b ldr r3, [r7, #20]
8005bc4: 2b00 cmp r3, #0
8005bc6: d101 bne.n 8005bcc <USBD_CUSTOM_HID_SendReport+0x28>
{
return (uint8_t)USBD_FAIL;
8005bc8: 2303 movs r3, #3
8005bca: e017 b.n 8005bfc <USBD_CUSTOM_HID_SendReport+0x58>
#ifdef USE_USBD_COMPOSITE
/* Get Endpoint IN address allocated for this class instance */
CUSTOMHIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8005bcc: 68fb ldr r3, [r7, #12]
8005bce: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8005bd2: b2db uxtb r3, r3
8005bd4: 2b03 cmp r3, #3
8005bd6: d110 bne.n 8005bfa <USBD_CUSTOM_HID_SendReport+0x56>
{
if (hhid->state == CUSTOM_HID_IDLE)
8005bd8: 697b ldr r3, [r7, #20]
8005bda: 7d1b ldrb r3, [r3, #20]
8005bdc: 2b00 cmp r3, #0
8005bde: d10a bne.n 8005bf6 <USBD_CUSTOM_HID_SendReport+0x52>
{
hhid->state = CUSTOM_HID_BUSY;
8005be0: 697b ldr r3, [r7, #20]
8005be2: 2201 movs r2, #1
8005be4: 751a strb r2, [r3, #20]
(void)USBD_LL_Transmit(pdev, CUSTOMHIDInEpAdd, report, len);
8005be6: 4b07 ldr r3, [pc, #28] @ (8005c04 <USBD_CUSTOM_HID_SendReport+0x60>)
8005be8: 7819 ldrb r1, [r3, #0]
8005bea: 88fb ldrh r3, [r7, #6]
8005bec: 68ba ldr r2, [r7, #8]
8005bee: 68f8 ldr r0, [r7, #12]
8005bf0: f002 f968 bl 8007ec4 <USBD_LL_Transmit>
8005bf4: e001 b.n 8005bfa <USBD_CUSTOM_HID_SendReport+0x56>
}
else
{
return (uint8_t)USBD_BUSY;
8005bf6: 2301 movs r3, #1
8005bf8: e000 b.n 8005bfc <USBD_CUSTOM_HID_SendReport+0x58>
}
}
return (uint8_t)USBD_OK;
8005bfa: 2300 movs r3, #0
}
8005bfc: 4618 mov r0, r3
8005bfe: 3718 adds r7, #24
8005c00: 46bd mov sp, r7
8005c02: bd80 pop {r7, pc}
8005c04: 20000086 .word 0x20000086
08005c08 <USBD_CUSTOM_HID_GetFSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CUSTOM_HID_GetFSCfgDesc(uint16_t *length)
{
8005c08: b580 push {r7, lr}
8005c0a: b084 sub sp, #16
8005c0c: af00 add r7, sp, #0
8005c0e: 6078 str r0, [r7, #4]
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CUSTOM_HID_CfgDesc, CUSTOM_HID_EPIN_ADDR);
8005c10: 2181 movs r1, #129 @ 0x81
8005c12: 4815 ldr r0, [pc, #84] @ (8005c68 <USBD_CUSTOM_HID_GetFSCfgDesc+0x60>)
8005c14: f000 fd1d bl 8006652 <USBD_GetEpDesc>
8005c18: 60f8 str r0, [r7, #12]
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CUSTOM_HID_CfgDesc, CUSTOM_HID_EPOUT_ADDR);
8005c1a: 2101 movs r1, #1
8005c1c: 4812 ldr r0, [pc, #72] @ (8005c68 <USBD_CUSTOM_HID_GetFSCfgDesc+0x60>)
8005c1e: f000 fd18 bl 8006652 <USBD_GetEpDesc>
8005c22: 60b8 str r0, [r7, #8]
if (pEpInDesc != NULL)
8005c24: 68fb ldr r3, [r7, #12]
8005c26: 2b00 cmp r3, #0
8005c28: d009 beq.n 8005c3e <USBD_CUSTOM_HID_GetFSCfgDesc+0x36>
{
pEpInDesc->wMaxPacketSize = CUSTOM_HID_EPIN_SIZE;
8005c2a: 68fb ldr r3, [r7, #12]
8005c2c: 2200 movs r2, #0
8005c2e: f042 0202 orr.w r2, r2, #2
8005c32: 711a strb r2, [r3, #4]
8005c34: 2200 movs r2, #0
8005c36: 715a strb r2, [r3, #5]
pEpInDesc->bInterval = CUSTOM_HID_FS_BINTERVAL;
8005c38: 68fb ldr r3, [r7, #12]
8005c3a: 2205 movs r2, #5
8005c3c: 719a strb r2, [r3, #6]
}
if (pEpOutDesc != NULL)
8005c3e: 68bb ldr r3, [r7, #8]
8005c40: 2b00 cmp r3, #0
8005c42: d009 beq.n 8005c58 <USBD_CUSTOM_HID_GetFSCfgDesc+0x50>
{
pEpOutDesc->wMaxPacketSize = CUSTOM_HID_EPOUT_SIZE;
8005c44: 68bb ldr r3, [r7, #8]
8005c46: 2200 movs r2, #0
8005c48: f042 0202 orr.w r2, r2, #2
8005c4c: 711a strb r2, [r3, #4]
8005c4e: 2200 movs r2, #0
8005c50: 715a strb r2, [r3, #5]
pEpOutDesc->bInterval = CUSTOM_HID_FS_BINTERVAL;
8005c52: 68bb ldr r3, [r7, #8]
8005c54: 2205 movs r2, #5
8005c56: 719a strb r2, [r3, #6]
}
*length = (uint16_t)sizeof(USBD_CUSTOM_HID_CfgDesc);
8005c58: 687b ldr r3, [r7, #4]
8005c5a: 2229 movs r2, #41 @ 0x29
8005c5c: 801a strh r2, [r3, #0]
return USBD_CUSTOM_HID_CfgDesc;
8005c5e: 4b02 ldr r3, [pc, #8] @ (8005c68 <USBD_CUSTOM_HID_GetFSCfgDesc+0x60>)
}
8005c60: 4618 mov r0, r3
8005c62: 3710 adds r7, #16
8005c64: 46bd mov sp, r7
8005c66: bd80 pop {r7, pc}
8005c68: 20000044 .word 0x20000044
08005c6c <USBD_CUSTOM_HID_GetHSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CUSTOM_HID_GetHSCfgDesc(uint16_t *length)
{
8005c6c: b580 push {r7, lr}
8005c6e: b084 sub sp, #16
8005c70: af00 add r7, sp, #0
8005c72: 6078 str r0, [r7, #4]
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CUSTOM_HID_CfgDesc, CUSTOM_HID_EPIN_ADDR);
8005c74: 2181 movs r1, #129 @ 0x81
8005c76: 4815 ldr r0, [pc, #84] @ (8005ccc <USBD_CUSTOM_HID_GetHSCfgDesc+0x60>)
8005c78: f000 fceb bl 8006652 <USBD_GetEpDesc>
8005c7c: 60f8 str r0, [r7, #12]
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CUSTOM_HID_CfgDesc, CUSTOM_HID_EPOUT_ADDR);
8005c7e: 2101 movs r1, #1
8005c80: 4812 ldr r0, [pc, #72] @ (8005ccc <USBD_CUSTOM_HID_GetHSCfgDesc+0x60>)
8005c82: f000 fce6 bl 8006652 <USBD_GetEpDesc>
8005c86: 60b8 str r0, [r7, #8]
if (pEpInDesc != NULL)
8005c88: 68fb ldr r3, [r7, #12]
8005c8a: 2b00 cmp r3, #0
8005c8c: d009 beq.n 8005ca2 <USBD_CUSTOM_HID_GetHSCfgDesc+0x36>
{
pEpInDesc->wMaxPacketSize = CUSTOM_HID_EPIN_SIZE;
8005c8e: 68fb ldr r3, [r7, #12]
8005c90: 2200 movs r2, #0
8005c92: f042 0202 orr.w r2, r2, #2
8005c96: 711a strb r2, [r3, #4]
8005c98: 2200 movs r2, #0
8005c9a: 715a strb r2, [r3, #5]
pEpInDesc->bInterval = CUSTOM_HID_HS_BINTERVAL;
8005c9c: 68fb ldr r3, [r7, #12]
8005c9e: 2205 movs r2, #5
8005ca0: 719a strb r2, [r3, #6]
}
if (pEpOutDesc != NULL)
8005ca2: 68bb ldr r3, [r7, #8]
8005ca4: 2b00 cmp r3, #0
8005ca6: d009 beq.n 8005cbc <USBD_CUSTOM_HID_GetHSCfgDesc+0x50>
{
pEpOutDesc->wMaxPacketSize = CUSTOM_HID_EPOUT_SIZE;
8005ca8: 68bb ldr r3, [r7, #8]
8005caa: 2200 movs r2, #0
8005cac: f042 0202 orr.w r2, r2, #2
8005cb0: 711a strb r2, [r3, #4]
8005cb2: 2200 movs r2, #0
8005cb4: 715a strb r2, [r3, #5]
pEpOutDesc->bInterval = CUSTOM_HID_HS_BINTERVAL;
8005cb6: 68bb ldr r3, [r7, #8]
8005cb8: 2205 movs r2, #5
8005cba: 719a strb r2, [r3, #6]
}
*length = (uint16_t)sizeof(USBD_CUSTOM_HID_CfgDesc);
8005cbc: 687b ldr r3, [r7, #4]
8005cbe: 2229 movs r2, #41 @ 0x29
8005cc0: 801a strh r2, [r3, #0]
return USBD_CUSTOM_HID_CfgDesc;
8005cc2: 4b02 ldr r3, [pc, #8] @ (8005ccc <USBD_CUSTOM_HID_GetHSCfgDesc+0x60>)
}
8005cc4: 4618 mov r0, r3
8005cc6: 3710 adds r7, #16
8005cc8: 46bd mov sp, r7
8005cca: bd80 pop {r7, pc}
8005ccc: 20000044 .word 0x20000044
08005cd0 <USBD_CUSTOM_HID_GetOtherSpeedCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CUSTOM_HID_GetOtherSpeedCfgDesc(uint16_t *length)
{
8005cd0: b580 push {r7, lr}
8005cd2: b084 sub sp, #16
8005cd4: af00 add r7, sp, #0
8005cd6: 6078 str r0, [r7, #4]
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CUSTOM_HID_CfgDesc, CUSTOM_HID_EPIN_ADDR);
8005cd8: 2181 movs r1, #129 @ 0x81
8005cda: 4815 ldr r0, [pc, #84] @ (8005d30 <USBD_CUSTOM_HID_GetOtherSpeedCfgDesc+0x60>)
8005cdc: f000 fcb9 bl 8006652 <USBD_GetEpDesc>
8005ce0: 60f8 str r0, [r7, #12]
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CUSTOM_HID_CfgDesc, CUSTOM_HID_EPOUT_ADDR);
8005ce2: 2101 movs r1, #1
8005ce4: 4812 ldr r0, [pc, #72] @ (8005d30 <USBD_CUSTOM_HID_GetOtherSpeedCfgDesc+0x60>)
8005ce6: f000 fcb4 bl 8006652 <USBD_GetEpDesc>
8005cea: 60b8 str r0, [r7, #8]
if (pEpInDesc != NULL)
8005cec: 68fb ldr r3, [r7, #12]
8005cee: 2b00 cmp r3, #0
8005cf0: d009 beq.n 8005d06 <USBD_CUSTOM_HID_GetOtherSpeedCfgDesc+0x36>
{
pEpInDesc->wMaxPacketSize = CUSTOM_HID_EPIN_SIZE;
8005cf2: 68fb ldr r3, [r7, #12]
8005cf4: 2200 movs r2, #0
8005cf6: f042 0202 orr.w r2, r2, #2
8005cfa: 711a strb r2, [r3, #4]
8005cfc: 2200 movs r2, #0
8005cfe: 715a strb r2, [r3, #5]
pEpInDesc->bInterval = CUSTOM_HID_FS_BINTERVAL;
8005d00: 68fb ldr r3, [r7, #12]
8005d02: 2205 movs r2, #5
8005d04: 719a strb r2, [r3, #6]
}
if (pEpOutDesc != NULL)
8005d06: 68bb ldr r3, [r7, #8]
8005d08: 2b00 cmp r3, #0
8005d0a: d009 beq.n 8005d20 <USBD_CUSTOM_HID_GetOtherSpeedCfgDesc+0x50>
{
pEpOutDesc->wMaxPacketSize = CUSTOM_HID_EPOUT_SIZE;
8005d0c: 68bb ldr r3, [r7, #8]
8005d0e: 2200 movs r2, #0
8005d10: f042 0202 orr.w r2, r2, #2
8005d14: 711a strb r2, [r3, #4]
8005d16: 2200 movs r2, #0
8005d18: 715a strb r2, [r3, #5]
pEpOutDesc->bInterval = CUSTOM_HID_FS_BINTERVAL;
8005d1a: 68bb ldr r3, [r7, #8]
8005d1c: 2205 movs r2, #5
8005d1e: 719a strb r2, [r3, #6]
}
*length = (uint16_t)sizeof(USBD_CUSTOM_HID_CfgDesc);
8005d20: 687b ldr r3, [r7, #4]
8005d22: 2229 movs r2, #41 @ 0x29
8005d24: 801a strh r2, [r3, #0]
return USBD_CUSTOM_HID_CfgDesc;
8005d26: 4b02 ldr r3, [pc, #8] @ (8005d30 <USBD_CUSTOM_HID_GetOtherSpeedCfgDesc+0x60>)
}
8005d28: 4618 mov r0, r3
8005d2a: 3710 adds r7, #16
8005d2c: 46bd mov sp, r7
8005d2e: bd80 pop {r7, pc}
8005d30: 20000044 .word 0x20000044
08005d34 <USBD_CUSTOM_HID_DataIn>:
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_CUSTOM_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
8005d34: b480 push {r7}
8005d36: b083 sub sp, #12
8005d38: af00 add r7, sp, #0
8005d3a: 6078 str r0, [r7, #4]
8005d3c: 460b mov r3, r1
8005d3e: 70fb strb r3, [r7, #3]
UNUSED(epnum);
/* Ensure that the FIFO is empty before a new transfer, this condition could
be caused by a new transfer before the end of the previous transfer */
((USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = CUSTOM_HID_IDLE;
8005d40: 687b ldr r3, [r7, #4]
8005d42: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005d46: 687b ldr r3, [r7, #4]
8005d48: 32b0 adds r2, #176 @ 0xb0
8005d4a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005d4e: 2200 movs r2, #0
8005d50: 751a strb r2, [r3, #20]
return (uint8_t)USBD_OK;
8005d52: 2300 movs r3, #0
}
8005d54: 4618 mov r0, r3
8005d56: 370c adds r7, #12
8005d58: 46bd mov sp, r7
8005d5a: f85d 7b04 ldr.w r7, [sp], #4
8005d5e: 4770 bx lr
08005d60 <USBD_CUSTOM_HID_DataOut>:
* @param pdev: device instance
* @param epnum: endpoint index
* @retval status
*/
static uint8_t USBD_CUSTOM_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
8005d60: b580 push {r7, lr}
8005d62: b084 sub sp, #16
8005d64: af00 add r7, sp, #0
8005d66: 6078 str r0, [r7, #4]
8005d68: 460b mov r3, r1
8005d6a: 70fb strb r3, [r7, #3]
UNUSED(epnum);
USBD_CUSTOM_HID_HandleTypeDef *hhid;
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
8005d6c: 687b ldr r3, [r7, #4]
8005d6e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005d72: 687b ldr r3, [r7, #4]
8005d74: 32b0 adds r2, #176 @ 0xb0
8005d76: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005d7a: 2b00 cmp r3, #0
8005d7c: d101 bne.n 8005d82 <USBD_CUSTOM_HID_DataOut+0x22>
{
return (uint8_t)USBD_FAIL;
8005d7e: 2303 movs r3, #3
8005d80: e017 b.n 8005db2 <USBD_CUSTOM_HID_DataOut+0x52>
}
hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
8005d82: 687b ldr r3, [r7, #4]
8005d84: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005d88: 687b ldr r3, [r7, #4]
8005d8a: 32b0 adds r2, #176 @ 0xb0
8005d8c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005d90: 60fb str r3, [r7, #12]
/* USB data will be immediately processed, this allow next USB traffic being
NAKed till the end of the application processing */
((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData[pdev->classId])->OutEvent(hhid->Report_buf[0],
8005d92: 687b ldr r3, [r7, #4]
8005d94: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8005d98: 687a ldr r2, [r7, #4]
8005d9a: 33b0 adds r3, #176 @ 0xb0
8005d9c: 009b lsls r3, r3, #2
8005d9e: 4413 add r3, r2
8005da0: 685b ldr r3, [r3, #4]
8005da2: 68db ldr r3, [r3, #12]
8005da4: 68fa ldr r2, [r7, #12]
8005da6: 7810 ldrb r0, [r2, #0]
8005da8: 68fa ldr r2, [r7, #12]
8005daa: 7852 ldrb r2, [r2, #1]
8005dac: 4611 mov r1, r2
8005dae: 4798 blx r3
hhid->Report_buf[1]);
return (uint8_t)USBD_OK;
8005db0: 2300 movs r3, #0
}
8005db2: 4618 mov r0, r3
8005db4: 3710 adds r7, #16
8005db6: 46bd mov sp, r7
8005db8: bd80 pop {r7, pc}
...
08005dbc <USBD_CUSTOM_HID_ReceivePacket>:
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CUSTOM_HID_ReceivePacket(USBD_HandleTypeDef *pdev)
{
8005dbc: b580 push {r7, lr}
8005dbe: b084 sub sp, #16
8005dc0: af00 add r7, sp, #0
8005dc2: 6078 str r0, [r7, #4]
USBD_CUSTOM_HID_HandleTypeDef *hhid;
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
8005dc4: 687b ldr r3, [r7, #4]
8005dc6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005dca: 687b ldr r3, [r7, #4]
8005dcc: 32b0 adds r2, #176 @ 0xb0
8005dce: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005dd2: 2b00 cmp r3, #0
8005dd4: d101 bne.n 8005dda <USBD_CUSTOM_HID_ReceivePacket+0x1e>
{
return (uint8_t)USBD_FAIL;
8005dd6: 2303 movs r3, #3
8005dd8: e00f b.n 8005dfa <USBD_CUSTOM_HID_ReceivePacket+0x3e>
#ifdef USE_USBD_COMPOSITE
/* Get OUT Endpoint address allocated for this class instance */
CUSTOMHIDOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
#endif /* USE_USBD_COMPOSITE */
hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
8005dda: 687b ldr r3, [r7, #4]
8005ddc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005de0: 687b ldr r3, [r7, #4]
8005de2: 32b0 adds r2, #176 @ 0xb0
8005de4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005de8: 60fb str r3, [r7, #12]
/* Resume USB Out process */
(void)USBD_LL_PrepareReceive(pdev, CUSTOMHIDOutEpAdd, hhid->Report_buf,
8005dea: 4b06 ldr r3, [pc, #24] @ (8005e04 <USBD_CUSTOM_HID_ReceivePacket+0x48>)
8005dec: 7819 ldrb r1, [r3, #0]
8005dee: 68fa ldr r2, [r7, #12]
8005df0: 2304 movs r3, #4
8005df2: 6878 ldr r0, [r7, #4]
8005df4: f002 f89e bl 8007f34 <USBD_LL_PrepareReceive>
USBD_CUSTOMHID_OUTREPORT_BUF_SIZE);
return (uint8_t)USBD_OK;
8005df8: 2300 movs r3, #0
}
8005dfa: 4618 mov r0, r3
8005dfc: 3710 adds r7, #16
8005dfe: 46bd mov sp, r7
8005e00: bd80 pop {r7, pc}
8005e02: bf00 nop
8005e04: 20000087 .word 0x20000087
08005e08 <USBD_CUSTOM_HID_EP0_RxReady>:
* Handles control request data.
* @param pdev: device instance
* @retval status
*/
static uint8_t USBD_CUSTOM_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
8005e08: b580 push {r7, lr}
8005e0a: b084 sub sp, #16
8005e0c: af00 add r7, sp, #0
8005e0e: 6078 str r0, [r7, #4]
USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
8005e10: 687b ldr r3, [r7, #4]
8005e12: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005e16: 687b ldr r3, [r7, #4]
8005e18: 32b0 adds r2, #176 @ 0xb0
8005e1a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005e1e: 60fb str r3, [r7, #12]
if (hhid == NULL)
8005e20: 68fb ldr r3, [r7, #12]
8005e22: 2b00 cmp r3, #0
8005e24: d101 bne.n 8005e2a <USBD_CUSTOM_HID_EP0_RxReady+0x22>
{
return (uint8_t)USBD_FAIL;
8005e26: 2303 movs r3, #3
8005e28: e016 b.n 8005e58 <USBD_CUSTOM_HID_EP0_RxReady+0x50>
}
if (hhid->IsReportAvailable == 1U)
8005e2a: 68fb ldr r3, [r7, #12]
8005e2c: 691b ldr r3, [r3, #16]
8005e2e: 2b01 cmp r3, #1
8005e30: d111 bne.n 8005e56 <USBD_CUSTOM_HID_EP0_RxReady+0x4e>
{
((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData[pdev->classId])->OutEvent(hhid->Report_buf[0],
8005e32: 687b ldr r3, [r7, #4]
8005e34: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8005e38: 687a ldr r2, [r7, #4]
8005e3a: 33b0 adds r3, #176 @ 0xb0
8005e3c: 009b lsls r3, r3, #2
8005e3e: 4413 add r3, r2
8005e40: 685b ldr r3, [r3, #4]
8005e42: 68db ldr r3, [r3, #12]
8005e44: 68fa ldr r2, [r7, #12]
8005e46: 7810 ldrb r0, [r2, #0]
8005e48: 68fa ldr r2, [r7, #12]
8005e4a: 7852 ldrb r2, [r2, #1]
8005e4c: 4611 mov r1, r2
8005e4e: 4798 blx r3
hhid->Report_buf[1]);
hhid->IsReportAvailable = 0U;
8005e50: 68fb ldr r3, [r7, #12]
8005e52: 2200 movs r2, #0
8005e54: 611a str r2, [r3, #16]
}
return (uint8_t)USBD_OK;
8005e56: 2300 movs r3, #0
}
8005e58: 4618 mov r0, r3
8005e5a: 3710 adds r7, #16
8005e5c: 46bd mov sp, r7
8005e5e: bd80 pop {r7, pc}
08005e60 <USBD_CUSTOM_HID_GetDeviceQualifierDesc>:
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CUSTOM_HID_GetDeviceQualifierDesc(uint16_t *length)
{
8005e60: b480 push {r7}
8005e62: b083 sub sp, #12
8005e64: af00 add r7, sp, #0
8005e66: 6078 str r0, [r7, #4]
*length = (uint16_t)sizeof(USBD_CUSTOM_HID_DeviceQualifierDesc);
8005e68: 687b ldr r3, [r7, #4]
8005e6a: 220a movs r2, #10
8005e6c: 801a strh r2, [r3, #0]
return USBD_CUSTOM_HID_DeviceQualifierDesc;
8005e6e: 4b03 ldr r3, [pc, #12] @ (8005e7c <USBD_CUSTOM_HID_GetDeviceQualifierDesc+0x1c>)
}
8005e70: 4618 mov r0, r3
8005e72: 370c adds r7, #12
8005e74: 46bd mov sp, r7
8005e76: f85d 7b04 ldr.w r7, [sp], #4
8005e7a: 4770 bx lr
8005e7c: 2000007c .word 0x2000007c
08005e80 <USBD_CUSTOM_HID_RegisterInterface>:
* @param fops: CUSTOMHID Interface callback
* @retval status
*/
uint8_t USBD_CUSTOM_HID_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CUSTOM_HID_ItfTypeDef *fops)
{
8005e80: b480 push {r7}
8005e82: b083 sub sp, #12
8005e84: af00 add r7, sp, #0
8005e86: 6078 str r0, [r7, #4]
8005e88: 6039 str r1, [r7, #0]
if (fops == NULL)
8005e8a: 683b ldr r3, [r7, #0]
8005e8c: 2b00 cmp r3, #0
8005e8e: d101 bne.n 8005e94 <USBD_CUSTOM_HID_RegisterInterface+0x14>
{
return (uint8_t)USBD_FAIL;
8005e90: 2303 movs r3, #3
8005e92: e009 b.n 8005ea8 <USBD_CUSTOM_HID_RegisterInterface+0x28>
}
pdev->pUserData[pdev->classId] = fops;
8005e94: 687b ldr r3, [r7, #4]
8005e96: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8005e9a: 687a ldr r2, [r7, #4]
8005e9c: 33b0 adds r3, #176 @ 0xb0
8005e9e: 009b lsls r3, r3, #2
8005ea0: 4413 add r3, r2
8005ea2: 683a ldr r2, [r7, #0]
8005ea4: 605a str r2, [r3, #4]
return (uint8_t)USBD_OK;
8005ea6: 2300 movs r3, #0
}
8005ea8: 4618 mov r0, r3
8005eaa: 370c adds r7, #12
8005eac: 46bd mov sp, r7
8005eae: f85d 7b04 ldr.w r7, [sp], #4
8005eb2: 4770 bx lr
08005eb4 <USBD_Init>:
* @param id: Low level core index
* @retval status: USBD Status
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
8005eb4: b580 push {r7, lr}
8005eb6: b086 sub sp, #24
8005eb8: af00 add r7, sp, #0
8005eba: 60f8 str r0, [r7, #12]
8005ebc: 60b9 str r1, [r7, #8]
8005ebe: 4613 mov r3, r2
8005ec0: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef ret;
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
8005ec2: 68fb ldr r3, [r7, #12]
8005ec4: 2b00 cmp r3, #0
8005ec6: d101 bne.n 8005ecc <USBD_Init+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle");
#endif /* (USBD_DEBUG_LEVEL > 1U) */
return USBD_FAIL;
8005ec8: 2303 movs r3, #3
8005eca: e01f b.n 8005f0c <USBD_Init+0x58>
pdev->NumClasses = 0;
pdev->classId = 0;
}
#else
/* Unlink previous class*/
pdev->pClass[0] = NULL;
8005ecc: 68fb ldr r3, [r7, #12]
8005ece: 2200 movs r2, #0
8005ed0: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
pdev->pUserData[0] = NULL;
8005ed4: 68fb ldr r3, [r7, #12]
8005ed6: 2200 movs r2, #0
8005ed8: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
#endif /* USE_USBD_COMPOSITE */
pdev->pConfDesc = NULL;
8005edc: 68fb ldr r3, [r7, #12]
8005ede: 2200 movs r2, #0
8005ee0: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
/* Assign USBD Descriptors */
if (pdesc != NULL)
8005ee4: 68bb ldr r3, [r7, #8]
8005ee6: 2b00 cmp r3, #0
8005ee8: d003 beq.n 8005ef2 <USBD_Init+0x3e>
{
pdev->pDesc = pdesc;
8005eea: 68fb ldr r3, [r7, #12]
8005eec: 68ba ldr r2, [r7, #8]
8005eee: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
}
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
8005ef2: 68fb ldr r3, [r7, #12]
8005ef4: 2201 movs r2, #1
8005ef6: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->id = id;
8005efa: 68fb ldr r3, [r7, #12]
8005efc: 79fa ldrb r2, [r7, #7]
8005efe: 701a strb r2, [r3, #0]
/* Initialize low level driver */
ret = USBD_LL_Init(pdev);
8005f00: 68f8 ldr r0, [r7, #12]
8005f02: f001 fe1f bl 8007b44 <USBD_LL_Init>
8005f06: 4603 mov r3, r0
8005f08: 75fb strb r3, [r7, #23]
return ret;
8005f0a: 7dfb ldrb r3, [r7, #23]
}
8005f0c: 4618 mov r0, r3
8005f0e: 3718 adds r7, #24
8005f10: 46bd mov sp, r7
8005f12: bd80 pop {r7, pc}
08005f14 <USBD_RegisterClass>:
* @param pdev: Device Handle
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
8005f14: b580 push {r7, lr}
8005f16: b084 sub sp, #16
8005f18: af00 add r7, sp, #0
8005f1a: 6078 str r0, [r7, #4]
8005f1c: 6039 str r1, [r7, #0]
uint16_t len = 0U;
8005f1e: 2300 movs r3, #0
8005f20: 81fb strh r3, [r7, #14]
if (pclass == NULL)
8005f22: 683b ldr r3, [r7, #0]
8005f24: 2b00 cmp r3, #0
8005f26: d101 bne.n 8005f2c <USBD_RegisterClass+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif /* (USBD_DEBUG_LEVEL > 1U) */
return USBD_FAIL;
8005f28: 2303 movs r3, #3
8005f2a: e025 b.n 8005f78 <USBD_RegisterClass+0x64>
}
/* link the class to the USB Device handle */
pdev->pClass[0] = pclass;
8005f2c: 687b ldr r3, [r7, #4]
8005f2e: 683a ldr r2, [r7, #0]
8005f30: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
{
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
}
#else /* Default USE_USB_FS */
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
8005f34: 687b ldr r3, [r7, #4]
8005f36: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005f3a: 687b ldr r3, [r7, #4]
8005f3c: 32ae adds r2, #174 @ 0xae
8005f3e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005f42: 6adb ldr r3, [r3, #44] @ 0x2c
8005f44: 2b00 cmp r3, #0
8005f46: d00f beq.n 8005f68 <USBD_RegisterClass+0x54>
{
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
8005f48: 687b ldr r3, [r7, #4]
8005f4a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8005f4e: 687b ldr r3, [r7, #4]
8005f50: 32ae adds r2, #174 @ 0xae
8005f52: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005f56: 6adb ldr r3, [r3, #44] @ 0x2c
8005f58: f107 020e add.w r2, r7, #14
8005f5c: 4610 mov r0, r2
8005f5e: 4798 blx r3
8005f60: 4602 mov r2, r0
8005f62: 687b ldr r3, [r7, #4]
8005f64: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
}
#endif /* USE_USB_FS */
/* Increment the NumClasses */
pdev->NumClasses++;
8005f68: 687b ldr r3, [r7, #4]
8005f6a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
8005f6e: 1c5a adds r2, r3, #1
8005f70: 687b ldr r3, [r7, #4]
8005f72: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
return USBD_OK;
8005f76: 2300 movs r3, #0
}
8005f78: 4618 mov r0, r3
8005f7a: 3710 adds r7, #16
8005f7c: 46bd mov sp, r7
8005f7e: bd80 pop {r7, pc}
08005f80 <USBD_Start>:
* Start the USB Device Core.
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
8005f80: b580 push {r7, lr}
8005f82: b082 sub sp, #8
8005f84: af00 add r7, sp, #0
8005f86: 6078 str r0, [r7, #4]
#ifdef USE_USBD_COMPOSITE
pdev->classId = 0U;
#endif /* USE_USBD_COMPOSITE */
/* Start the low level driver */
return USBD_LL_Start(pdev);
8005f88: 6878 ldr r0, [r7, #4]
8005f8a: f001 fe27 bl 8007bdc <USBD_LL_Start>
8005f8e: 4603 mov r3, r0
}
8005f90: 4618 mov r0, r3
8005f92: 3708 adds r7, #8
8005f94: 46bd mov sp, r7
8005f96: bd80 pop {r7, pc}
08005f98 <USBD_RunTestMode>:
* Launch test mode process
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
8005f98: b480 push {r7}
8005f9a: b083 sub sp, #12
8005f9c: af00 add r7, sp, #0
8005f9e: 6078 str r0, [r7, #4]
return ret;
#else
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
8005fa0: 2300 movs r3, #0
#endif /* USBD_HS_TESTMODE_ENABLE */
}
8005fa2: 4618 mov r0, r3
8005fa4: 370c adds r7, #12
8005fa6: 46bd mov sp, r7
8005fa8: f85d 7b04 ldr.w r7, [sp], #4
8005fac: 4770 bx lr
08005fae <USBD_SetClassConfig>:
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8005fae: b580 push {r7, lr}
8005fb0: b084 sub sp, #16
8005fb2: af00 add r7, sp, #0
8005fb4: 6078 str r0, [r7, #4]
8005fb6: 460b mov r3, r1
8005fb8: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_OK;
8005fba: 2300 movs r3, #0
8005fbc: 73fb strb r3, [r7, #15]
}
}
}
}
#else
if (pdev->pClass[0] != NULL)
8005fbe: 687b ldr r3, [r7, #4]
8005fc0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8005fc4: 2b00 cmp r3, #0
8005fc6: d009 beq.n 8005fdc <USBD_SetClassConfig+0x2e>
{
/* Set configuration and Start the Class */
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
8005fc8: 687b ldr r3, [r7, #4]
8005fca: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8005fce: 681b ldr r3, [r3, #0]
8005fd0: 78fa ldrb r2, [r7, #3]
8005fd2: 4611 mov r1, r2
8005fd4: 6878 ldr r0, [r7, #4]
8005fd6: 4798 blx r3
8005fd8: 4603 mov r3, r0
8005fda: 73fb strb r3, [r7, #15]
}
#endif /* USE_USBD_COMPOSITE */
return ret;
8005fdc: 7bfb ldrb r3, [r7, #15]
}
8005fde: 4618 mov r0, r3
8005fe0: 3710 adds r7, #16
8005fe2: 46bd mov sp, r7
8005fe4: bd80 pop {r7, pc}
08005fe6 <USBD_ClrClassConfig>:
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8005fe6: b580 push {r7, lr}
8005fe8: b084 sub sp, #16
8005fea: af00 add r7, sp, #0
8005fec: 6078 str r0, [r7, #4]
8005fee: 460b mov r3, r1
8005ff0: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_OK;
8005ff2: 2300 movs r3, #0
8005ff4: 73fb strb r3, [r7, #15]
}
}
}
#else
/* Clear configuration and De-initialize the Class process */
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
8005ff6: 687b ldr r3, [r7, #4]
8005ff8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8005ffc: 685b ldr r3, [r3, #4]
8005ffe: 78fa ldrb r2, [r7, #3]
8006000: 4611 mov r1, r2
8006002: 6878 ldr r0, [r7, #4]
8006004: 4798 blx r3
8006006: 4603 mov r3, r0
8006008: 2b00 cmp r3, #0
800600a: d001 beq.n 8006010 <USBD_ClrClassConfig+0x2a>
{
ret = USBD_FAIL;
800600c: 2303 movs r3, #3
800600e: 73fb strb r3, [r7, #15]
}
#endif /* USE_USBD_COMPOSITE */
return ret;
8006010: 7bfb ldrb r3, [r7, #15]
}
8006012: 4618 mov r0, r3
8006014: 3710 adds r7, #16
8006016: 46bd mov sp, r7
8006018: bd80 pop {r7, pc}
0800601a <USBD_LL_SetupStage>:
* @param pdev: device instance
* @param psetup: setup packet buffer pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
800601a: b580 push {r7, lr}
800601c: b084 sub sp, #16
800601e: af00 add r7, sp, #0
8006020: 6078 str r0, [r7, #4]
8006022: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret;
USBD_ParseSetupRequest(&pdev->request, psetup);
8006024: 687b ldr r3, [r7, #4]
8006026: f203 23aa addw r3, r3, #682 @ 0x2aa
800602a: 6839 ldr r1, [r7, #0]
800602c: 4618 mov r0, r3
800602e: f001 f936 bl 800729e <USBD_ParseSetupRequest>
pdev->ep0_state = USBD_EP0_SETUP;
8006032: 687b ldr r3, [r7, #4]
8006034: 2201 movs r2, #1
8006036: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep0_data_len = pdev->request.wLength;
800603a: 687b ldr r3, [r7, #4]
800603c: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
8006040: 461a mov r2, r3
8006042: 687b ldr r3, [r7, #4]
8006044: f8c3 2298 str.w r2, [r3, #664] @ 0x298
switch (pdev->request.bmRequest & 0x1FU)
8006048: 687b ldr r3, [r7, #4]
800604a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
800604e: f003 031f and.w r3, r3, #31
8006052: 2b02 cmp r3, #2
8006054: d01a beq.n 800608c <USBD_LL_SetupStage+0x72>
8006056: 2b02 cmp r3, #2
8006058: d822 bhi.n 80060a0 <USBD_LL_SetupStage+0x86>
800605a: 2b00 cmp r3, #0
800605c: d002 beq.n 8006064 <USBD_LL_SetupStage+0x4a>
800605e: 2b01 cmp r3, #1
8006060: d00a beq.n 8006078 <USBD_LL_SetupStage+0x5e>
8006062: e01d b.n 80060a0 <USBD_LL_SetupStage+0x86>
{
case USB_REQ_RECIPIENT_DEVICE:
ret = USBD_StdDevReq(pdev, &pdev->request);
8006064: 687b ldr r3, [r7, #4]
8006066: f203 23aa addw r3, r3, #682 @ 0x2aa
800606a: 4619 mov r1, r3
800606c: 6878 ldr r0, [r7, #4]
800606e: f000 fb63 bl 8006738 <USBD_StdDevReq>
8006072: 4603 mov r3, r0
8006074: 73fb strb r3, [r7, #15]
break;
8006076: e020 b.n 80060ba <USBD_LL_SetupStage+0xa0>
case USB_REQ_RECIPIENT_INTERFACE:
ret = USBD_StdItfReq(pdev, &pdev->request);
8006078: 687b ldr r3, [r7, #4]
800607a: f203 23aa addw r3, r3, #682 @ 0x2aa
800607e: 4619 mov r1, r3
8006080: 6878 ldr r0, [r7, #4]
8006082: f000 fbcb bl 800681c <USBD_StdItfReq>
8006086: 4603 mov r3, r0
8006088: 73fb strb r3, [r7, #15]
break;
800608a: e016 b.n 80060ba <USBD_LL_SetupStage+0xa0>
case USB_REQ_RECIPIENT_ENDPOINT:
ret = USBD_StdEPReq(pdev, &pdev->request);
800608c: 687b ldr r3, [r7, #4]
800608e: f203 23aa addw r3, r3, #682 @ 0x2aa
8006092: 4619 mov r1, r3
8006094: 6878 ldr r0, [r7, #4]
8006096: f000 fc2d bl 80068f4 <USBD_StdEPReq>
800609a: 4603 mov r3, r0
800609c: 73fb strb r3, [r7, #15]
break;
800609e: e00c b.n 80060ba <USBD_LL_SetupStage+0xa0>
default:
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
80060a0: 687b ldr r3, [r7, #4]
80060a2: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
80060a6: f023 037f bic.w r3, r3, #127 @ 0x7f
80060aa: b2db uxtb r3, r3
80060ac: 4619 mov r1, r3
80060ae: 6878 ldr r0, [r7, #4]
80060b0: f001 fe3a bl 8007d28 <USBD_LL_StallEP>
80060b4: 4603 mov r3, r0
80060b6: 73fb strb r3, [r7, #15]
break;
80060b8: bf00 nop
}
return ret;
80060ba: 7bfb ldrb r3, [r7, #15]
}
80060bc: 4618 mov r0, r3
80060be: 3710 adds r7, #16
80060c0: 46bd mov sp, r7
80060c2: bd80 pop {r7, pc}
080060c4 <USBD_LL_DataOutStage>:
* @param pdata: data pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
80060c4: b580 push {r7, lr}
80060c6: b086 sub sp, #24
80060c8: af00 add r7, sp, #0
80060ca: 60f8 str r0, [r7, #12]
80060cc: 460b mov r3, r1
80060ce: 607a str r2, [r7, #4]
80060d0: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
USBD_StatusTypeDef ret = USBD_OK;
80060d2: 2300 movs r3, #0
80060d4: 75fb strb r3, [r7, #23]
uint8_t idx;
if (epnum == 0U)
80060d6: 7afb ldrb r3, [r7, #11]
80060d8: 2b00 cmp r3, #0
80060da: d16e bne.n 80061ba <USBD_LL_DataOutStage+0xf6>
{
pep = &pdev->ep_out[0];
80060dc: 68fb ldr r3, [r7, #12]
80060de: f503 73aa add.w r3, r3, #340 @ 0x154
80060e2: 613b str r3, [r7, #16]
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
80060e4: 68fb ldr r3, [r7, #12]
80060e6: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
80060ea: 2b03 cmp r3, #3
80060ec: f040 8098 bne.w 8006220 <USBD_LL_DataOutStage+0x15c>
{
if (pep->rem_length > pep->maxpacket)
80060f0: 693b ldr r3, [r7, #16]
80060f2: 689a ldr r2, [r3, #8]
80060f4: 693b ldr r3, [r7, #16]
80060f6: 68db ldr r3, [r3, #12]
80060f8: 429a cmp r2, r3
80060fa: d913 bls.n 8006124 <USBD_LL_DataOutStage+0x60>
{
pep->rem_length -= pep->maxpacket;
80060fc: 693b ldr r3, [r7, #16]
80060fe: 689a ldr r2, [r3, #8]
8006100: 693b ldr r3, [r7, #16]
8006102: 68db ldr r3, [r3, #12]
8006104: 1ad2 subs r2, r2, r3
8006106: 693b ldr r3, [r7, #16]
8006108: 609a str r2, [r3, #8]
(void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket));
800610a: 693b ldr r3, [r7, #16]
800610c: 68da ldr r2, [r3, #12]
800610e: 693b ldr r3, [r7, #16]
8006110: 689b ldr r3, [r3, #8]
8006112: 4293 cmp r3, r2
8006114: bf28 it cs
8006116: 4613 movcs r3, r2
8006118: 461a mov r2, r3
800611a: 6879 ldr r1, [r7, #4]
800611c: 68f8 ldr r0, [r7, #12]
800611e: f001 f9be bl 800749e <USBD_CtlContinueRx>
8006122: e07d b.n 8006220 <USBD_LL_DataOutStage+0x15c>
}
else
{
/* Find the class ID relative to the current request */
switch (pdev->request.bmRequest & 0x1FU)
8006124: 68fb ldr r3, [r7, #12]
8006126: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
800612a: f003 031f and.w r3, r3, #31
800612e: 2b02 cmp r3, #2
8006130: d014 beq.n 800615c <USBD_LL_DataOutStage+0x98>
8006132: 2b02 cmp r3, #2
8006134: d81d bhi.n 8006172 <USBD_LL_DataOutStage+0xae>
8006136: 2b00 cmp r3, #0
8006138: d002 beq.n 8006140 <USBD_LL_DataOutStage+0x7c>
800613a: 2b01 cmp r3, #1
800613c: d003 beq.n 8006146 <USBD_LL_DataOutStage+0x82>
800613e: e018 b.n 8006172 <USBD_LL_DataOutStage+0xae>
{
case USB_REQ_RECIPIENT_DEVICE:
/* Device requests must be managed by the first instantiated class
(or duplicated by all classes for simplicity) */
idx = 0U;
8006140: 2300 movs r3, #0
8006142: 75bb strb r3, [r7, #22]
break;
8006144: e018 b.n 8006178 <USBD_LL_DataOutStage+0xb4>
case USB_REQ_RECIPIENT_INTERFACE:
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
8006146: 68fb ldr r3, [r7, #12]
8006148: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
800614c: b2db uxtb r3, r3
800614e: 4619 mov r1, r3
8006150: 68f8 ldr r0, [r7, #12]
8006152: f000 fa64 bl 800661e <USBD_CoreFindIF>
8006156: 4603 mov r3, r0
8006158: 75bb strb r3, [r7, #22]
break;
800615a: e00d b.n 8006178 <USBD_LL_DataOutStage+0xb4>
case USB_REQ_RECIPIENT_ENDPOINT:
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
800615c: 68fb ldr r3, [r7, #12]
800615e: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
8006162: b2db uxtb r3, r3
8006164: 4619 mov r1, r3
8006166: 68f8 ldr r0, [r7, #12]
8006168: f000 fa66 bl 8006638 <USBD_CoreFindEP>
800616c: 4603 mov r3, r0
800616e: 75bb strb r3, [r7, #22]
break;
8006170: e002 b.n 8006178 <USBD_LL_DataOutStage+0xb4>
default:
/* Back to the first class in case of doubt */
idx = 0U;
8006172: 2300 movs r3, #0
8006174: 75bb strb r3, [r7, #22]
break;
8006176: bf00 nop
}
if (idx < USBD_MAX_SUPPORTED_CLASS)
8006178: 7dbb ldrb r3, [r7, #22]
800617a: 2b00 cmp r3, #0
800617c: d119 bne.n 80061b2 <USBD_LL_DataOutStage+0xee>
{
/* Setup the class ID and route the request to the relative class function */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800617e: 68fb ldr r3, [r7, #12]
8006180: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006184: b2db uxtb r3, r3
8006186: 2b03 cmp r3, #3
8006188: d113 bne.n 80061b2 <USBD_LL_DataOutStage+0xee>
{
if (pdev->pClass[idx]->EP0_RxReady != NULL)
800618a: 7dba ldrb r2, [r7, #22]
800618c: 68fb ldr r3, [r7, #12]
800618e: 32ae adds r2, #174 @ 0xae
8006190: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006194: 691b ldr r3, [r3, #16]
8006196: 2b00 cmp r3, #0
8006198: d00b beq.n 80061b2 <USBD_LL_DataOutStage+0xee>
{
pdev->classId = idx;
800619a: 7dba ldrb r2, [r7, #22]
800619c: 68fb ldr r3, [r7, #12]
800619e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
pdev->pClass[idx]->EP0_RxReady(pdev);
80061a2: 7dba ldrb r2, [r7, #22]
80061a4: 68fb ldr r3, [r7, #12]
80061a6: 32ae adds r2, #174 @ 0xae
80061a8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80061ac: 691b ldr r3, [r3, #16]
80061ae: 68f8 ldr r0, [r7, #12]
80061b0: 4798 blx r3
}
}
}
(void)USBD_CtlSendStatus(pdev);
80061b2: 68f8 ldr r0, [r7, #12]
80061b4: f001 f984 bl 80074c0 <USBD_CtlSendStatus>
80061b8: e032 b.n 8006220 <USBD_LL_DataOutStage+0x15c>
}
}
else
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
80061ba: 7afb ldrb r3, [r7, #11]
80061bc: f003 037f and.w r3, r3, #127 @ 0x7f
80061c0: b2db uxtb r3, r3
80061c2: 4619 mov r1, r3
80061c4: 68f8 ldr r0, [r7, #12]
80061c6: f000 fa37 bl 8006638 <USBD_CoreFindEP>
80061ca: 4603 mov r3, r0
80061cc: 75bb strb r3, [r7, #22]
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
80061ce: 7dbb ldrb r3, [r7, #22]
80061d0: 2bff cmp r3, #255 @ 0xff
80061d2: d025 beq.n 8006220 <USBD_LL_DataOutStage+0x15c>
80061d4: 7dbb ldrb r3, [r7, #22]
80061d6: 2b00 cmp r3, #0
80061d8: d122 bne.n 8006220 <USBD_LL_DataOutStage+0x15c>
{
/* Call the class data out function to manage the request */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
80061da: 68fb ldr r3, [r7, #12]
80061dc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80061e0: b2db uxtb r3, r3
80061e2: 2b03 cmp r3, #3
80061e4: d117 bne.n 8006216 <USBD_LL_DataOutStage+0x152>
{
if (pdev->pClass[idx]->DataOut != NULL)
80061e6: 7dba ldrb r2, [r7, #22]
80061e8: 68fb ldr r3, [r7, #12]
80061ea: 32ae adds r2, #174 @ 0xae
80061ec: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80061f0: 699b ldr r3, [r3, #24]
80061f2: 2b00 cmp r3, #0
80061f4: d00f beq.n 8006216 <USBD_LL_DataOutStage+0x152>
{
pdev->classId = idx;
80061f6: 7dba ldrb r2, [r7, #22]
80061f8: 68fb ldr r3, [r7, #12]
80061fa: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
80061fe: 7dba ldrb r2, [r7, #22]
8006200: 68fb ldr r3, [r7, #12]
8006202: 32ae adds r2, #174 @ 0xae
8006204: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006208: 699b ldr r3, [r3, #24]
800620a: 7afa ldrb r2, [r7, #11]
800620c: 4611 mov r1, r2
800620e: 68f8 ldr r0, [r7, #12]
8006210: 4798 blx r3
8006212: 4603 mov r3, r0
8006214: 75fb strb r3, [r7, #23]
}
}
if (ret != USBD_OK)
8006216: 7dfb ldrb r3, [r7, #23]
8006218: 2b00 cmp r3, #0
800621a: d001 beq.n 8006220 <USBD_LL_DataOutStage+0x15c>
{
return ret;
800621c: 7dfb ldrb r3, [r7, #23]
800621e: e000 b.n 8006222 <USBD_LL_DataOutStage+0x15e>
}
}
}
return USBD_OK;
8006220: 2300 movs r3, #0
}
8006222: 4618 mov r0, r3
8006224: 3718 adds r7, #24
8006226: 46bd mov sp, r7
8006228: bd80 pop {r7, pc}
0800622a <USBD_LL_DataInStage>:
* @param pdata: data pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
800622a: b580 push {r7, lr}
800622c: b086 sub sp, #24
800622e: af00 add r7, sp, #0
8006230: 60f8 str r0, [r7, #12]
8006232: 460b mov r3, r1
8006234: 607a str r2, [r7, #4]
8006236: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
USBD_StatusTypeDef ret;
uint8_t idx;
if (epnum == 0U)
8006238: 7afb ldrb r3, [r7, #11]
800623a: 2b00 cmp r3, #0
800623c: d16f bne.n 800631e <USBD_LL_DataInStage+0xf4>
{
pep = &pdev->ep_in[0];
800623e: 68fb ldr r3, [r7, #12]
8006240: 3314 adds r3, #20
8006242: 613b str r3, [r7, #16]
if (pdev->ep0_state == USBD_EP0_DATA_IN)
8006244: 68fb ldr r3, [r7, #12]
8006246: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
800624a: 2b02 cmp r3, #2
800624c: d15a bne.n 8006304 <USBD_LL_DataInStage+0xda>
{
if (pep->rem_length > pep->maxpacket)
800624e: 693b ldr r3, [r7, #16]
8006250: 689a ldr r2, [r3, #8]
8006252: 693b ldr r3, [r7, #16]
8006254: 68db ldr r3, [r3, #12]
8006256: 429a cmp r2, r3
8006258: d914 bls.n 8006284 <USBD_LL_DataInStage+0x5a>
{
pep->rem_length -= pep->maxpacket;
800625a: 693b ldr r3, [r7, #16]
800625c: 689a ldr r2, [r3, #8]
800625e: 693b ldr r3, [r7, #16]
8006260: 68db ldr r3, [r3, #12]
8006262: 1ad2 subs r2, r2, r3
8006264: 693b ldr r3, [r7, #16]
8006266: 609a str r2, [r3, #8]
(void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length);
8006268: 693b ldr r3, [r7, #16]
800626a: 689b ldr r3, [r3, #8]
800626c: 461a mov r2, r3
800626e: 6879 ldr r1, [r7, #4]
8006270: 68f8 ldr r0, [r7, #12]
8006272: f001 f8e6 bl 8007442 <USBD_CtlContinueSendData>
/* Prepare endpoint for premature end of transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8006276: 2300 movs r3, #0
8006278: 2200 movs r2, #0
800627a: 2100 movs r1, #0
800627c: 68f8 ldr r0, [r7, #12]
800627e: f001 fe59 bl 8007f34 <USBD_LL_PrepareReceive>
8006282: e03f b.n 8006304 <USBD_LL_DataInStage+0xda>
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->maxpacket == pep->rem_length) &&
8006284: 693b ldr r3, [r7, #16]
8006286: 68da ldr r2, [r3, #12]
8006288: 693b ldr r3, [r7, #16]
800628a: 689b ldr r3, [r3, #8]
800628c: 429a cmp r2, r3
800628e: d11c bne.n 80062ca <USBD_LL_DataInStage+0xa0>
(pep->total_length >= pep->maxpacket) &&
8006290: 693b ldr r3, [r7, #16]
8006292: 685a ldr r2, [r3, #4]
8006294: 693b ldr r3, [r7, #16]
8006296: 68db ldr r3, [r3, #12]
if ((pep->maxpacket == pep->rem_length) &&
8006298: 429a cmp r2, r3
800629a: d316 bcc.n 80062ca <USBD_LL_DataInStage+0xa0>
(pep->total_length < pdev->ep0_data_len))
800629c: 693b ldr r3, [r7, #16]
800629e: 685a ldr r2, [r3, #4]
80062a0: 68fb ldr r3, [r7, #12]
80062a2: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
(pep->total_length >= pep->maxpacket) &&
80062a6: 429a cmp r2, r3
80062a8: d20f bcs.n 80062ca <USBD_LL_DataInStage+0xa0>
{
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
80062aa: 2200 movs r2, #0
80062ac: 2100 movs r1, #0
80062ae: 68f8 ldr r0, [r7, #12]
80062b0: f001 f8c7 bl 8007442 <USBD_CtlContinueSendData>
pdev->ep0_data_len = 0U;
80062b4: 68fb ldr r3, [r7, #12]
80062b6: 2200 movs r2, #0
80062b8: f8c3 2298 str.w r2, [r3, #664] @ 0x298
/* Prepare endpoint for premature end of transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
80062bc: 2300 movs r3, #0
80062be: 2200 movs r2, #0
80062c0: 2100 movs r1, #0
80062c2: 68f8 ldr r0, [r7, #12]
80062c4: f001 fe36 bl 8007f34 <USBD_LL_PrepareReceive>
80062c8: e01c b.n 8006304 <USBD_LL_DataInStage+0xda>
}
else
{
if (pdev->dev_state == USBD_STATE_CONFIGURED)
80062ca: 68fb ldr r3, [r7, #12]
80062cc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80062d0: b2db uxtb r3, r3
80062d2: 2b03 cmp r3, #3
80062d4: d10f bne.n 80062f6 <USBD_LL_DataInStage+0xcc>
{
if (pdev->pClass[0]->EP0_TxSent != NULL)
80062d6: 68fb ldr r3, [r7, #12]
80062d8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80062dc: 68db ldr r3, [r3, #12]
80062de: 2b00 cmp r3, #0
80062e0: d009 beq.n 80062f6 <USBD_LL_DataInStage+0xcc>
{
pdev->classId = 0U;
80062e2: 68fb ldr r3, [r7, #12]
80062e4: 2200 movs r2, #0
80062e6: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
pdev->pClass[0]->EP0_TxSent(pdev);
80062ea: 68fb ldr r3, [r7, #12]
80062ec: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80062f0: 68db ldr r3, [r3, #12]
80062f2: 68f8 ldr r0, [r7, #12]
80062f4: 4798 blx r3
}
}
(void)USBD_LL_StallEP(pdev, 0x80U);
80062f6: 2180 movs r1, #128 @ 0x80
80062f8: 68f8 ldr r0, [r7, #12]
80062fa: f001 fd15 bl 8007d28 <USBD_LL_StallEP>
(void)USBD_CtlReceiveStatus(pdev);
80062fe: 68f8 ldr r0, [r7, #12]
8006300: f001 f8f1 bl 80074e6 <USBD_CtlReceiveStatus>
}
}
}
if (pdev->dev_test_mode != 0U)
8006304: 68fb ldr r3, [r7, #12]
8006306: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
800630a: 2b00 cmp r3, #0
800630c: d03a beq.n 8006384 <USBD_LL_DataInStage+0x15a>
{
(void)USBD_RunTestMode(pdev);
800630e: 68f8 ldr r0, [r7, #12]
8006310: f7ff fe42 bl 8005f98 <USBD_RunTestMode>
pdev->dev_test_mode = 0U;
8006314: 68fb ldr r3, [r7, #12]
8006316: 2200 movs r2, #0
8006318: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
800631c: e032 b.n 8006384 <USBD_LL_DataInStage+0x15a>
}
}
else
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
800631e: 7afb ldrb r3, [r7, #11]
8006320: f063 037f orn r3, r3, #127 @ 0x7f
8006324: b2db uxtb r3, r3
8006326: 4619 mov r1, r3
8006328: 68f8 ldr r0, [r7, #12]
800632a: f000 f985 bl 8006638 <USBD_CoreFindEP>
800632e: 4603 mov r3, r0
8006330: 75fb strb r3, [r7, #23]
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
8006332: 7dfb ldrb r3, [r7, #23]
8006334: 2bff cmp r3, #255 @ 0xff
8006336: d025 beq.n 8006384 <USBD_LL_DataInStage+0x15a>
8006338: 7dfb ldrb r3, [r7, #23]
800633a: 2b00 cmp r3, #0
800633c: d122 bne.n 8006384 <USBD_LL_DataInStage+0x15a>
{
/* Call the class data out function to manage the request */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800633e: 68fb ldr r3, [r7, #12]
8006340: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006344: b2db uxtb r3, r3
8006346: 2b03 cmp r3, #3
8006348: d11c bne.n 8006384 <USBD_LL_DataInStage+0x15a>
{
if (pdev->pClass[idx]->DataIn != NULL)
800634a: 7dfa ldrb r2, [r7, #23]
800634c: 68fb ldr r3, [r7, #12]
800634e: 32ae adds r2, #174 @ 0xae
8006350: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006354: 695b ldr r3, [r3, #20]
8006356: 2b00 cmp r3, #0
8006358: d014 beq.n 8006384 <USBD_LL_DataInStage+0x15a>
{
pdev->classId = idx;
800635a: 7dfa ldrb r2, [r7, #23]
800635c: 68fb ldr r3, [r7, #12]
800635e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
8006362: 7dfa ldrb r2, [r7, #23]
8006364: 68fb ldr r3, [r7, #12]
8006366: 32ae adds r2, #174 @ 0xae
8006368: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800636c: 695b ldr r3, [r3, #20]
800636e: 7afa ldrb r2, [r7, #11]
8006370: 4611 mov r1, r2
8006372: 68f8 ldr r0, [r7, #12]
8006374: 4798 blx r3
8006376: 4603 mov r3, r0
8006378: 75bb strb r3, [r7, #22]
if (ret != USBD_OK)
800637a: 7dbb ldrb r3, [r7, #22]
800637c: 2b00 cmp r3, #0
800637e: d001 beq.n 8006384 <USBD_LL_DataInStage+0x15a>
{
return ret;
8006380: 7dbb ldrb r3, [r7, #22]
8006382: e000 b.n 8006386 <USBD_LL_DataInStage+0x15c>
}
}
}
}
return USBD_OK;
8006384: 2300 movs r3, #0
}
8006386: 4618 mov r0, r3
8006388: 3718 adds r7, #24
800638a: 46bd mov sp, r7
800638c: bd80 pop {r7, pc}
0800638e <USBD_LL_Reset>:
* Handle Reset event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
800638e: b580 push {r7, lr}
8006390: b084 sub sp, #16
8006392: af00 add r7, sp, #0
8006394: 6078 str r0, [r7, #4]
USBD_StatusTypeDef ret = USBD_OK;
8006396: 2300 movs r3, #0
8006398: 73fb strb r3, [r7, #15]
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
800639a: 687b ldr r3, [r7, #4]
800639c: 2201 movs r2, #1
800639e: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->ep0_state = USBD_EP0_IDLE;
80063a2: 687b ldr r3, [r7, #4]
80063a4: 2200 movs r2, #0
80063a6: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->dev_config = 0U;
80063aa: 687b ldr r3, [r7, #4]
80063ac: 2200 movs r2, #0
80063ae: 605a str r2, [r3, #4]
pdev->dev_remote_wakeup = 0U;
80063b0: 687b ldr r3, [r7, #4]
80063b2: 2200 movs r2, #0
80063b4: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
pdev->dev_test_mode = 0U;
80063b8: 687b ldr r3, [r7, #4]
80063ba: 2200 movs r2, #0
80063bc: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
}
}
}
#else
if (pdev->pClass[0] != NULL)
80063c0: 687b ldr r3, [r7, #4]
80063c2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80063c6: 2b00 cmp r3, #0
80063c8: d014 beq.n 80063f4 <USBD_LL_Reset+0x66>
{
if (pdev->pClass[0]->DeInit != NULL)
80063ca: 687b ldr r3, [r7, #4]
80063cc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80063d0: 685b ldr r3, [r3, #4]
80063d2: 2b00 cmp r3, #0
80063d4: d00e beq.n 80063f4 <USBD_LL_Reset+0x66>
{
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
80063d6: 687b ldr r3, [r7, #4]
80063d8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80063dc: 685b ldr r3, [r3, #4]
80063de: 687a ldr r2, [r7, #4]
80063e0: 6852 ldr r2, [r2, #4]
80063e2: b2d2 uxtb r2, r2
80063e4: 4611 mov r1, r2
80063e6: 6878 ldr r0, [r7, #4]
80063e8: 4798 blx r3
80063ea: 4603 mov r3, r0
80063ec: 2b00 cmp r3, #0
80063ee: d001 beq.n 80063f4 <USBD_LL_Reset+0x66>
{
ret = USBD_FAIL;
80063f0: 2303 movs r3, #3
80063f2: 73fb strb r3, [r7, #15]
}
}
#endif /* USE_USBD_COMPOSITE */
/* Open EP0 OUT */
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
80063f4: 2340 movs r3, #64 @ 0x40
80063f6: 2200 movs r2, #0
80063f8: 2100 movs r1, #0
80063fa: 6878 ldr r0, [r7, #4]
80063fc: f001 fc20 bl 8007c40 <USBD_LL_OpenEP>
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
8006400: 687b ldr r3, [r7, #4]
8006402: 2201 movs r2, #1
8006404: f8a3 2164 strh.w r2, [r3, #356] @ 0x164
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
8006408: 687b ldr r3, [r7, #4]
800640a: 2240 movs r2, #64 @ 0x40
800640c: f8c3 2160 str.w r2, [r3, #352] @ 0x160
/* Open EP0 IN */
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8006410: 2340 movs r3, #64 @ 0x40
8006412: 2200 movs r2, #0
8006414: 2180 movs r1, #128 @ 0x80
8006416: 6878 ldr r0, [r7, #4]
8006418: f001 fc12 bl 8007c40 <USBD_LL_OpenEP>
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
800641c: 687b ldr r3, [r7, #4]
800641e: 2201 movs r2, #1
8006420: 849a strh r2, [r3, #36] @ 0x24
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
8006422: 687b ldr r3, [r7, #4]
8006424: 2240 movs r2, #64 @ 0x40
8006426: 621a str r2, [r3, #32]
return ret;
8006428: 7bfb ldrb r3, [r7, #15]
}
800642a: 4618 mov r0, r3
800642c: 3710 adds r7, #16
800642e: 46bd mov sp, r7
8006430: bd80 pop {r7, pc}
08006432 <USBD_LL_SetSpeed>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{
8006432: b480 push {r7}
8006434: b083 sub sp, #12
8006436: af00 add r7, sp, #0
8006438: 6078 str r0, [r7, #4]
800643a: 460b mov r3, r1
800643c: 70fb strb r3, [r7, #3]
pdev->dev_speed = speed;
800643e: 687b ldr r3, [r7, #4]
8006440: 78fa ldrb r2, [r7, #3]
8006442: 741a strb r2, [r3, #16]
return USBD_OK;
8006444: 2300 movs r3, #0
}
8006446: 4618 mov r0, r3
8006448: 370c adds r7, #12
800644a: 46bd mov sp, r7
800644c: f85d 7b04 ldr.w r7, [sp], #4
8006450: 4770 bx lr
08006452 <USBD_LL_Suspend>:
* Handle Suspend event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
8006452: b480 push {r7}
8006454: b083 sub sp, #12
8006456: af00 add r7, sp, #0
8006458: 6078 str r0, [r7, #4]
if (pdev->dev_state != USBD_STATE_SUSPENDED)
800645a: 687b ldr r3, [r7, #4]
800645c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006460: b2db uxtb r3, r3
8006462: 2b04 cmp r3, #4
8006464: d006 beq.n 8006474 <USBD_LL_Suspend+0x22>
{
pdev->dev_old_state = pdev->dev_state;
8006466: 687b ldr r3, [r7, #4]
8006468: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800646c: b2da uxtb r2, r3
800646e: 687b ldr r3, [r7, #4]
8006470: f883 229d strb.w r2, [r3, #669] @ 0x29d
}
pdev->dev_state = USBD_STATE_SUSPENDED;
8006474: 687b ldr r3, [r7, #4]
8006476: 2204 movs r2, #4
8006478: f883 229c strb.w r2, [r3, #668] @ 0x29c
return USBD_OK;
800647c: 2300 movs r3, #0
}
800647e: 4618 mov r0, r3
8006480: 370c adds r7, #12
8006482: 46bd mov sp, r7
8006484: f85d 7b04 ldr.w r7, [sp], #4
8006488: 4770 bx lr
0800648a <USBD_LL_Resume>:
* Handle Resume event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{
800648a: b480 push {r7}
800648c: b083 sub sp, #12
800648e: af00 add r7, sp, #0
8006490: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_SUSPENDED)
8006492: 687b ldr r3, [r7, #4]
8006494: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006498: b2db uxtb r3, r3
800649a: 2b04 cmp r3, #4
800649c: d106 bne.n 80064ac <USBD_LL_Resume+0x22>
{
pdev->dev_state = pdev->dev_old_state;
800649e: 687b ldr r3, [r7, #4]
80064a0: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
80064a4: b2da uxtb r2, r3
80064a6: 687b ldr r3, [r7, #4]
80064a8: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
return USBD_OK;
80064ac: 2300 movs r3, #0
}
80064ae: 4618 mov r0, r3
80064b0: 370c adds r7, #12
80064b2: 46bd mov sp, r7
80064b4: f85d 7b04 ldr.w r7, [sp], #4
80064b8: 4770 bx lr
080064ba <USBD_LL_SOF>:
* Handle SOF event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{
80064ba: b580 push {r7, lr}
80064bc: b082 sub sp, #8
80064be: af00 add r7, sp, #0
80064c0: 6078 str r0, [r7, #4]
/* The SOF event can be distributed for all classes that support it */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
80064c2: 687b ldr r3, [r7, #4]
80064c4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80064c8: b2db uxtb r3, r3
80064ca: 2b03 cmp r3, #3
80064cc: d110 bne.n 80064f0 <USBD_LL_SOF+0x36>
}
}
}
}
#else
if (pdev->pClass[0] != NULL)
80064ce: 687b ldr r3, [r7, #4]
80064d0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80064d4: 2b00 cmp r3, #0
80064d6: d00b beq.n 80064f0 <USBD_LL_SOF+0x36>
{
if (pdev->pClass[0]->SOF != NULL)
80064d8: 687b ldr r3, [r7, #4]
80064da: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80064de: 69db ldr r3, [r3, #28]
80064e0: 2b00 cmp r3, #0
80064e2: d005 beq.n 80064f0 <USBD_LL_SOF+0x36>
{
(void)pdev->pClass[0]->SOF(pdev);
80064e4: 687b ldr r3, [r7, #4]
80064e6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80064ea: 69db ldr r3, [r3, #28]
80064ec: 6878 ldr r0, [r7, #4]
80064ee: 4798 blx r3
}
}
#endif /* USE_USBD_COMPOSITE */
}
return USBD_OK;
80064f0: 2300 movs r3, #0
}
80064f2: 4618 mov r0, r3
80064f4: 3708 adds r7, #8
80064f6: 46bd mov sp, r7
80064f8: bd80 pop {r7, pc}
080064fa <USBD_LL_IsoINIncomplete>:
* @param epnum: Endpoint number
* @retval status
*/
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
uint8_t epnum)
{
80064fa: b580 push {r7, lr}
80064fc: b082 sub sp, #8
80064fe: af00 add r7, sp, #0
8006500: 6078 str r0, [r7, #4]
8006502: 460b mov r3, r1
8006504: 70fb strb r3, [r7, #3]
if (pdev->pClass[pdev->classId] == NULL)
8006506: 687b ldr r3, [r7, #4]
8006508: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800650c: 687b ldr r3, [r7, #4]
800650e: 32ae adds r2, #174 @ 0xae
8006510: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006514: 2b00 cmp r3, #0
8006516: d101 bne.n 800651c <USBD_LL_IsoINIncomplete+0x22>
{
return USBD_FAIL;
8006518: 2303 movs r3, #3
800651a: e01c b.n 8006556 <USBD_LL_IsoINIncomplete+0x5c>
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800651c: 687b ldr r3, [r7, #4]
800651e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006522: b2db uxtb r3, r3
8006524: 2b03 cmp r3, #3
8006526: d115 bne.n 8006554 <USBD_LL_IsoINIncomplete+0x5a>
{
if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL)
8006528: 687b ldr r3, [r7, #4]
800652a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800652e: 687b ldr r3, [r7, #4]
8006530: 32ae adds r2, #174 @ 0xae
8006532: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006536: 6a1b ldr r3, [r3, #32]
8006538: 2b00 cmp r3, #0
800653a: d00b beq.n 8006554 <USBD_LL_IsoINIncomplete+0x5a>
{
(void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum);
800653c: 687b ldr r3, [r7, #4]
800653e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8006542: 687b ldr r3, [r7, #4]
8006544: 32ae adds r2, #174 @ 0xae
8006546: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800654a: 6a1b ldr r3, [r3, #32]
800654c: 78fa ldrb r2, [r7, #3]
800654e: 4611 mov r1, r2
8006550: 6878 ldr r0, [r7, #4]
8006552: 4798 blx r3
}
}
return USBD_OK;
8006554: 2300 movs r3, #0
}
8006556: 4618 mov r0, r3
8006558: 3708 adds r7, #8
800655a: 46bd mov sp, r7
800655c: bd80 pop {r7, pc}
0800655e <USBD_LL_IsoOUTIncomplete>:
* @param epnum: Endpoint number
* @retval status
*/
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
uint8_t epnum)
{
800655e: b580 push {r7, lr}
8006560: b082 sub sp, #8
8006562: af00 add r7, sp, #0
8006564: 6078 str r0, [r7, #4]
8006566: 460b mov r3, r1
8006568: 70fb strb r3, [r7, #3]
if (pdev->pClass[pdev->classId] == NULL)
800656a: 687b ldr r3, [r7, #4]
800656c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8006570: 687b ldr r3, [r7, #4]
8006572: 32ae adds r2, #174 @ 0xae
8006574: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006578: 2b00 cmp r3, #0
800657a: d101 bne.n 8006580 <USBD_LL_IsoOUTIncomplete+0x22>
{
return USBD_FAIL;
800657c: 2303 movs r3, #3
800657e: e01c b.n 80065ba <USBD_LL_IsoOUTIncomplete+0x5c>
}
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8006580: 687b ldr r3, [r7, #4]
8006582: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006586: b2db uxtb r3, r3
8006588: 2b03 cmp r3, #3
800658a: d115 bne.n 80065b8 <USBD_LL_IsoOUTIncomplete+0x5a>
{
if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL)
800658c: 687b ldr r3, [r7, #4]
800658e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8006592: 687b ldr r3, [r7, #4]
8006594: 32ae adds r2, #174 @ 0xae
8006596: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800659a: 6a5b ldr r3, [r3, #36] @ 0x24
800659c: 2b00 cmp r3, #0
800659e: d00b beq.n 80065b8 <USBD_LL_IsoOUTIncomplete+0x5a>
{
(void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum);
80065a0: 687b ldr r3, [r7, #4]
80065a2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
80065a6: 687b ldr r3, [r7, #4]
80065a8: 32ae adds r2, #174 @ 0xae
80065aa: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80065ae: 6a5b ldr r3, [r3, #36] @ 0x24
80065b0: 78fa ldrb r2, [r7, #3]
80065b2: 4611 mov r1, r2
80065b4: 6878 ldr r0, [r7, #4]
80065b6: 4798 blx r3
}
}
return USBD_OK;
80065b8: 2300 movs r3, #0
}
80065ba: 4618 mov r0, r3
80065bc: 3708 adds r7, #8
80065be: 46bd mov sp, r7
80065c0: bd80 pop {r7, pc}
080065c2 <USBD_LL_DevConnected>:
* Handle device connection event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
{
80065c2: b480 push {r7}
80065c4: b083 sub sp, #12
80065c6: af00 add r7, sp, #0
80065c8: 6078 str r0, [r7, #4]
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
80065ca: 2300 movs r3, #0
}
80065cc: 4618 mov r0, r3
80065ce: 370c adds r7, #12
80065d0: 46bd mov sp, r7
80065d2: f85d 7b04 ldr.w r7, [sp], #4
80065d6: 4770 bx lr
080065d8 <USBD_LL_DevDisconnected>:
* Handle device disconnection event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
{
80065d8: b580 push {r7, lr}
80065da: b084 sub sp, #16
80065dc: af00 add r7, sp, #0
80065de: 6078 str r0, [r7, #4]
USBD_StatusTypeDef ret = USBD_OK;
80065e0: 2300 movs r3, #0
80065e2: 73fb strb r3, [r7, #15]
/* Free Class Resources */
pdev->dev_state = USBD_STATE_DEFAULT;
80065e4: 687b ldr r3, [r7, #4]
80065e6: 2201 movs r2, #1
80065e8: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
}
}
}
#else
if (pdev->pClass[0] != NULL)
80065ec: 687b ldr r3, [r7, #4]
80065ee: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80065f2: 2b00 cmp r3, #0
80065f4: d00e beq.n 8006614 <USBD_LL_DevDisconnected+0x3c>
{
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U)
80065f6: 687b ldr r3, [r7, #4]
80065f8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80065fc: 685b ldr r3, [r3, #4]
80065fe: 687a ldr r2, [r7, #4]
8006600: 6852 ldr r2, [r2, #4]
8006602: b2d2 uxtb r2, r2
8006604: 4611 mov r1, r2
8006606: 6878 ldr r0, [r7, #4]
8006608: 4798 blx r3
800660a: 4603 mov r3, r0
800660c: 2b00 cmp r3, #0
800660e: d001 beq.n 8006614 <USBD_LL_DevDisconnected+0x3c>
{
ret = USBD_FAIL;
8006610: 2303 movs r3, #3
8006612: 73fb strb r3, [r7, #15]
}
}
#endif /* USE_USBD_COMPOSITE */
return ret;
8006614: 7bfb ldrb r3, [r7, #15]
}
8006616: 4618 mov r0, r3
8006618: 3710 adds r7, #16
800661a: 46bd mov sp, r7
800661c: bd80 pop {r7, pc}
0800661e <USBD_CoreFindIF>:
* @param pdev: device instance
* @param index : selected interface number
* @retval index of the class using the selected interface number. OxFF if no class found.
*/
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
{
800661e: b480 push {r7}
8006620: b083 sub sp, #12
8006622: af00 add r7, sp, #0
8006624: 6078 str r0, [r7, #4]
8006626: 460b mov r3, r1
8006628: 70fb strb r3, [r7, #3]
return 0xFFU;
#else
UNUSED(pdev);
UNUSED(index);
return 0x00U;
800662a: 2300 movs r3, #0
#endif /* USE_USBD_COMPOSITE */
}
800662c: 4618 mov r0, r3
800662e: 370c adds r7, #12
8006630: 46bd mov sp, r7
8006632: f85d 7b04 ldr.w r7, [sp], #4
8006636: 4770 bx lr
08006638 <USBD_CoreFindEP>:
* @param pdev: device instance
* @param index : selected endpoint number
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
*/
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
{
8006638: b480 push {r7}
800663a: b083 sub sp, #12
800663c: af00 add r7, sp, #0
800663e: 6078 str r0, [r7, #4]
8006640: 460b mov r3, r1
8006642: 70fb strb r3, [r7, #3]
return 0xFFU;
#else
UNUSED(pdev);
UNUSED(index);
return 0x00U;
8006644: 2300 movs r3, #0
#endif /* USE_USBD_COMPOSITE */
}
8006646: 4618 mov r0, r3
8006648: 370c adds r7, #12
800664a: 46bd mov sp, r7
800664c: f85d 7b04 ldr.w r7, [sp], #4
8006650: 4770 bx lr
08006652 <USBD_GetEpDesc>:
* @param pConfDesc: pointer to Bos descriptor
* @param EpAddr: endpoint address
* @retval pointer to video endpoint descriptor
*/
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr)
{
8006652: b580 push {r7, lr}
8006654: b086 sub sp, #24
8006656: af00 add r7, sp, #0
8006658: 6078 str r0, [r7, #4]
800665a: 460b mov r3, r1
800665c: 70fb strb r3, [r7, #3]
USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc;
800665e: 687b ldr r3, [r7, #4]
8006660: 617b str r3, [r7, #20]
USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc;
8006662: 687b ldr r3, [r7, #4]
8006664: 60fb str r3, [r7, #12]
USBD_EpDescTypeDef *pEpDesc = NULL;
8006666: 2300 movs r3, #0
8006668: 613b str r3, [r7, #16]
uint16_t ptr;
if (desc->wTotalLength > desc->bLength)
800666a: 68fb ldr r3, [r7, #12]
800666c: 885b ldrh r3, [r3, #2]
800666e: b29b uxth r3, r3
8006670: 68fa ldr r2, [r7, #12]
8006672: 7812 ldrb r2, [r2, #0]
8006674: 4293 cmp r3, r2
8006676: d91f bls.n 80066b8 <USBD_GetEpDesc+0x66>
{
ptr = desc->bLength;
8006678: 68fb ldr r3, [r7, #12]
800667a: 781b ldrb r3, [r3, #0]
800667c: 817b strh r3, [r7, #10]
while (ptr < desc->wTotalLength)
800667e: e013 b.n 80066a8 <USBD_GetEpDesc+0x56>
{
pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr);
8006680: f107 030a add.w r3, r7, #10
8006684: 4619 mov r1, r3
8006686: 6978 ldr r0, [r7, #20]
8006688: f000 f81b bl 80066c2 <USBD_GetNextDesc>
800668c: 6178 str r0, [r7, #20]
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
800668e: 697b ldr r3, [r7, #20]
8006690: 785b ldrb r3, [r3, #1]
8006692: 2b05 cmp r3, #5
8006694: d108 bne.n 80066a8 <USBD_GetEpDesc+0x56>
{
pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc;
8006696: 697b ldr r3, [r7, #20]
8006698: 613b str r3, [r7, #16]
if (pEpDesc->bEndpointAddress == EpAddr)
800669a: 693b ldr r3, [r7, #16]
800669c: 789b ldrb r3, [r3, #2]
800669e: 78fa ldrb r2, [r7, #3]
80066a0: 429a cmp r2, r3
80066a2: d008 beq.n 80066b6 <USBD_GetEpDesc+0x64>
{
break;
}
else
{
pEpDesc = NULL;
80066a4: 2300 movs r3, #0
80066a6: 613b str r3, [r7, #16]
while (ptr < desc->wTotalLength)
80066a8: 68fb ldr r3, [r7, #12]
80066aa: 885b ldrh r3, [r3, #2]
80066ac: b29a uxth r2, r3
80066ae: 897b ldrh r3, [r7, #10]
80066b0: 429a cmp r2, r3
80066b2: d8e5 bhi.n 8006680 <USBD_GetEpDesc+0x2e>
80066b4: e000 b.n 80066b8 <USBD_GetEpDesc+0x66>
break;
80066b6: bf00 nop
}
}
}
}
return (void *)pEpDesc;
80066b8: 693b ldr r3, [r7, #16]
}
80066ba: 4618 mov r0, r3
80066bc: 3718 adds r7, #24
80066be: 46bd mov sp, r7
80066c0: bd80 pop {r7, pc}
080066c2 <USBD_GetNextDesc>:
* @param buf: Buffer where the descriptor is available
* @param ptr: data pointer inside the descriptor
* @retval next header
*/
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
{
80066c2: b480 push {r7}
80066c4: b085 sub sp, #20
80066c6: af00 add r7, sp, #0
80066c8: 6078 str r0, [r7, #4]
80066ca: 6039 str r1, [r7, #0]
USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf;
80066cc: 687b ldr r3, [r7, #4]
80066ce: 60fb str r3, [r7, #12]
*ptr += pnext->bLength;
80066d0: 683b ldr r3, [r7, #0]
80066d2: 881b ldrh r3, [r3, #0]
80066d4: 68fa ldr r2, [r7, #12]
80066d6: 7812 ldrb r2, [r2, #0]
80066d8: 4413 add r3, r2
80066da: b29a uxth r2, r3
80066dc: 683b ldr r3, [r7, #0]
80066de: 801a strh r2, [r3, #0]
pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength);
80066e0: 68fb ldr r3, [r7, #12]
80066e2: 781b ldrb r3, [r3, #0]
80066e4: 461a mov r2, r3
80066e6: 687b ldr r3, [r7, #4]
80066e8: 4413 add r3, r2
80066ea: 60fb str r3, [r7, #12]
return (pnext);
80066ec: 68fb ldr r3, [r7, #12]
}
80066ee: 4618 mov r0, r3
80066f0: 3714 adds r7, #20
80066f2: 46bd mov sp, r7
80066f4: f85d 7b04 ldr.w r7, [sp], #4
80066f8: 4770 bx lr
080066fa <SWAPBYTE>:
/** @defgroup USBD_DEF_Exported_Macros
* @{
*/
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
{
80066fa: b480 push {r7}
80066fc: b087 sub sp, #28
80066fe: af00 add r7, sp, #0
8006700: 6078 str r0, [r7, #4]
uint16_t _SwapVal;
uint16_t _Byte1;
uint16_t _Byte2;
uint8_t *_pbuff = addr;
8006702: 687b ldr r3, [r7, #4]
8006704: 617b str r3, [r7, #20]
_Byte1 = *(uint8_t *)_pbuff;
8006706: 697b ldr r3, [r7, #20]
8006708: 781b ldrb r3, [r3, #0]
800670a: 827b strh r3, [r7, #18]
_pbuff++;
800670c: 697b ldr r3, [r7, #20]
800670e: 3301 adds r3, #1
8006710: 617b str r3, [r7, #20]
_Byte2 = *(uint8_t *)_pbuff;
8006712: 697b ldr r3, [r7, #20]
8006714: 781b ldrb r3, [r3, #0]
8006716: 823b strh r3, [r7, #16]
_SwapVal = (_Byte2 << 8) | _Byte1;
8006718: f9b7 3010 ldrsh.w r3, [r7, #16]
800671c: 021b lsls r3, r3, #8
800671e: b21a sxth r2, r3
8006720: f9b7 3012 ldrsh.w r3, [r7, #18]
8006724: 4313 orrs r3, r2
8006726: b21b sxth r3, r3
8006728: 81fb strh r3, [r7, #14]
return _SwapVal;
800672a: 89fb ldrh r3, [r7, #14]
}
800672c: 4618 mov r0, r3
800672e: 371c adds r7, #28
8006730: 46bd mov sp, r7
8006732: f85d 7b04 ldr.w r7, [sp], #4
8006736: 4770 bx lr
08006738 <USBD_StdDevReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8006738: b580 push {r7, lr}
800673a: b084 sub sp, #16
800673c: af00 add r7, sp, #0
800673e: 6078 str r0, [r7, #4]
8006740: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8006742: 2300 movs r3, #0
8006744: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8006746: 683b ldr r3, [r7, #0]
8006748: 781b ldrb r3, [r3, #0]
800674a: f003 0360 and.w r3, r3, #96 @ 0x60
800674e: 2b40 cmp r3, #64 @ 0x40
8006750: d005 beq.n 800675e <USBD_StdDevReq+0x26>
8006752: 2b40 cmp r3, #64 @ 0x40
8006754: d857 bhi.n 8006806 <USBD_StdDevReq+0xce>
8006756: 2b00 cmp r3, #0
8006758: d00f beq.n 800677a <USBD_StdDevReq+0x42>
800675a: 2b20 cmp r3, #32
800675c: d153 bne.n 8006806 <USBD_StdDevReq+0xce>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
800675e: 687b ldr r3, [r7, #4]
8006760: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8006764: 687b ldr r3, [r7, #4]
8006766: 32ae adds r2, #174 @ 0xae
8006768: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800676c: 689b ldr r3, [r3, #8]
800676e: 6839 ldr r1, [r7, #0]
8006770: 6878 ldr r0, [r7, #4]
8006772: 4798 blx r3
8006774: 4603 mov r3, r0
8006776: 73fb strb r3, [r7, #15]
break;
8006778: e04a b.n 8006810 <USBD_StdDevReq+0xd8>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
800677a: 683b ldr r3, [r7, #0]
800677c: 785b ldrb r3, [r3, #1]
800677e: 2b09 cmp r3, #9
8006780: d83b bhi.n 80067fa <USBD_StdDevReq+0xc2>
8006782: a201 add r2, pc, #4 @ (adr r2, 8006788 <USBD_StdDevReq+0x50>)
8006784: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006788: 080067dd .word 0x080067dd
800678c: 080067f1 .word 0x080067f1
8006790: 080067fb .word 0x080067fb
8006794: 080067e7 .word 0x080067e7
8006798: 080067fb .word 0x080067fb
800679c: 080067bb .word 0x080067bb
80067a0: 080067b1 .word 0x080067b1
80067a4: 080067fb .word 0x080067fb
80067a8: 080067d3 .word 0x080067d3
80067ac: 080067c5 .word 0x080067c5
{
case USB_REQ_GET_DESCRIPTOR:
USBD_GetDescriptor(pdev, req);
80067b0: 6839 ldr r1, [r7, #0]
80067b2: 6878 ldr r0, [r7, #4]
80067b4: f000 fa3c bl 8006c30 <USBD_GetDescriptor>
break;
80067b8: e024 b.n 8006804 <USBD_StdDevReq+0xcc>
case USB_REQ_SET_ADDRESS:
USBD_SetAddress(pdev, req);
80067ba: 6839 ldr r1, [r7, #0]
80067bc: 6878 ldr r0, [r7, #4]
80067be: f000 fbcb bl 8006f58 <USBD_SetAddress>
break;
80067c2: e01f b.n 8006804 <USBD_StdDevReq+0xcc>
case USB_REQ_SET_CONFIGURATION:
ret = USBD_SetConfig(pdev, req);
80067c4: 6839 ldr r1, [r7, #0]
80067c6: 6878 ldr r0, [r7, #4]
80067c8: f000 fc0a bl 8006fe0 <USBD_SetConfig>
80067cc: 4603 mov r3, r0
80067ce: 73fb strb r3, [r7, #15]
break;
80067d0: e018 b.n 8006804 <USBD_StdDevReq+0xcc>
case USB_REQ_GET_CONFIGURATION:
USBD_GetConfig(pdev, req);
80067d2: 6839 ldr r1, [r7, #0]
80067d4: 6878 ldr r0, [r7, #4]
80067d6: f000 fcad bl 8007134 <USBD_GetConfig>
break;
80067da: e013 b.n 8006804 <USBD_StdDevReq+0xcc>
case USB_REQ_GET_STATUS:
USBD_GetStatus(pdev, req);
80067dc: 6839 ldr r1, [r7, #0]
80067de: 6878 ldr r0, [r7, #4]
80067e0: f000 fcde bl 80071a0 <USBD_GetStatus>
break;
80067e4: e00e b.n 8006804 <USBD_StdDevReq+0xcc>
case USB_REQ_SET_FEATURE:
USBD_SetFeature(pdev, req);
80067e6: 6839 ldr r1, [r7, #0]
80067e8: 6878 ldr r0, [r7, #4]
80067ea: f000 fd0d bl 8007208 <USBD_SetFeature>
break;
80067ee: e009 b.n 8006804 <USBD_StdDevReq+0xcc>
case USB_REQ_CLEAR_FEATURE:
USBD_ClrFeature(pdev, req);
80067f0: 6839 ldr r1, [r7, #0]
80067f2: 6878 ldr r0, [r7, #4]
80067f4: f000 fd31 bl 800725a <USBD_ClrFeature>
break;
80067f8: e004 b.n 8006804 <USBD_StdDevReq+0xcc>
default:
USBD_CtlError(pdev, req);
80067fa: 6839 ldr r1, [r7, #0]
80067fc: 6878 ldr r0, [r7, #4]
80067fe: f000 fd88 bl 8007312 <USBD_CtlError>
break;
8006802: bf00 nop
}
break;
8006804: e004 b.n 8006810 <USBD_StdDevReq+0xd8>
default:
USBD_CtlError(pdev, req);
8006806: 6839 ldr r1, [r7, #0]
8006808: 6878 ldr r0, [r7, #4]
800680a: f000 fd82 bl 8007312 <USBD_CtlError>
break;
800680e: bf00 nop
}
return ret;
8006810: 7bfb ldrb r3, [r7, #15]
}
8006812: 4618 mov r0, r3
8006814: 3710 adds r7, #16
8006816: 46bd mov sp, r7
8006818: bd80 pop {r7, pc}
800681a: bf00 nop
0800681c <USBD_StdItfReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800681c: b580 push {r7, lr}
800681e: b084 sub sp, #16
8006820: af00 add r7, sp, #0
8006822: 6078 str r0, [r7, #4]
8006824: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8006826: 2300 movs r3, #0
8006828: 73fb strb r3, [r7, #15]
uint8_t idx;
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800682a: 683b ldr r3, [r7, #0]
800682c: 781b ldrb r3, [r3, #0]
800682e: f003 0360 and.w r3, r3, #96 @ 0x60
8006832: 2b40 cmp r3, #64 @ 0x40
8006834: d005 beq.n 8006842 <USBD_StdItfReq+0x26>
8006836: 2b40 cmp r3, #64 @ 0x40
8006838: d852 bhi.n 80068e0 <USBD_StdItfReq+0xc4>
800683a: 2b00 cmp r3, #0
800683c: d001 beq.n 8006842 <USBD_StdItfReq+0x26>
800683e: 2b20 cmp r3, #32
8006840: d14e bne.n 80068e0 <USBD_StdItfReq+0xc4>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
case USB_REQ_TYPE_STANDARD:
switch (pdev->dev_state)
8006842: 687b ldr r3, [r7, #4]
8006844: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006848: b2db uxtb r3, r3
800684a: 3b01 subs r3, #1
800684c: 2b02 cmp r3, #2
800684e: d840 bhi.n 80068d2 <USBD_StdItfReq+0xb6>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
8006850: 683b ldr r3, [r7, #0]
8006852: 889b ldrh r3, [r3, #4]
8006854: b2db uxtb r3, r3
8006856: 2b01 cmp r3, #1
8006858: d836 bhi.n 80068c8 <USBD_StdItfReq+0xac>
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
800685a: 683b ldr r3, [r7, #0]
800685c: 889b ldrh r3, [r3, #4]
800685e: b2db uxtb r3, r3
8006860: 4619 mov r1, r3
8006862: 6878 ldr r0, [r7, #4]
8006864: f7ff fedb bl 800661e <USBD_CoreFindIF>
8006868: 4603 mov r3, r0
800686a: 73bb strb r3, [r7, #14]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
800686c: 7bbb ldrb r3, [r7, #14]
800686e: 2bff cmp r3, #255 @ 0xff
8006870: d01d beq.n 80068ae <USBD_StdItfReq+0x92>
8006872: 7bbb ldrb r3, [r7, #14]
8006874: 2b00 cmp r3, #0
8006876: d11a bne.n 80068ae <USBD_StdItfReq+0x92>
{
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
8006878: 7bba ldrb r2, [r7, #14]
800687a: 687b ldr r3, [r7, #4]
800687c: 32ae adds r2, #174 @ 0xae
800687e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006882: 689b ldr r3, [r3, #8]
8006884: 2b00 cmp r3, #0
8006886: d00f beq.n 80068a8 <USBD_StdItfReq+0x8c>
{
pdev->classId = idx;
8006888: 7bba ldrb r2, [r7, #14]
800688a: 687b ldr r3, [r7, #4]
800688c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
8006890: 7bba ldrb r2, [r7, #14]
8006892: 687b ldr r3, [r7, #4]
8006894: 32ae adds r2, #174 @ 0xae
8006896: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800689a: 689b ldr r3, [r3, #8]
800689c: 6839 ldr r1, [r7, #0]
800689e: 6878 ldr r0, [r7, #4]
80068a0: 4798 blx r3
80068a2: 4603 mov r3, r0
80068a4: 73fb strb r3, [r7, #15]
if (pdev->pClass[idx]->Setup != NULL)
80068a6: e004 b.n 80068b2 <USBD_StdItfReq+0x96>
}
else
{
/* should never reach this condition */
ret = USBD_FAIL;
80068a8: 2303 movs r3, #3
80068aa: 73fb strb r3, [r7, #15]
if (pdev->pClass[idx]->Setup != NULL)
80068ac: e001 b.n 80068b2 <USBD_StdItfReq+0x96>
}
}
else
{
/* No relative interface found */
ret = USBD_FAIL;
80068ae: 2303 movs r3, #3
80068b0: 73fb strb r3, [r7, #15]
}
if ((req->wLength == 0U) && (ret == USBD_OK))
80068b2: 683b ldr r3, [r7, #0]
80068b4: 88db ldrh r3, [r3, #6]
80068b6: 2b00 cmp r3, #0
80068b8: d110 bne.n 80068dc <USBD_StdItfReq+0xc0>
80068ba: 7bfb ldrb r3, [r7, #15]
80068bc: 2b00 cmp r3, #0
80068be: d10d bne.n 80068dc <USBD_StdItfReq+0xc0>
{
(void)USBD_CtlSendStatus(pdev);
80068c0: 6878 ldr r0, [r7, #4]
80068c2: f000 fdfd bl 80074c0 <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
break;
80068c6: e009 b.n 80068dc <USBD_StdItfReq+0xc0>
USBD_CtlError(pdev, req);
80068c8: 6839 ldr r1, [r7, #0]
80068ca: 6878 ldr r0, [r7, #4]
80068cc: f000 fd21 bl 8007312 <USBD_CtlError>
break;
80068d0: e004 b.n 80068dc <USBD_StdItfReq+0xc0>
default:
USBD_CtlError(pdev, req);
80068d2: 6839 ldr r1, [r7, #0]
80068d4: 6878 ldr r0, [r7, #4]
80068d6: f000 fd1c bl 8007312 <USBD_CtlError>
break;
80068da: e000 b.n 80068de <USBD_StdItfReq+0xc2>
break;
80068dc: bf00 nop
}
break;
80068de: e004 b.n 80068ea <USBD_StdItfReq+0xce>
default:
USBD_CtlError(pdev, req);
80068e0: 6839 ldr r1, [r7, #0]
80068e2: 6878 ldr r0, [r7, #4]
80068e4: f000 fd15 bl 8007312 <USBD_CtlError>
break;
80068e8: bf00 nop
}
return ret;
80068ea: 7bfb ldrb r3, [r7, #15]
}
80068ec: 4618 mov r0, r3
80068ee: 3710 adds r7, #16
80068f0: 46bd mov sp, r7
80068f2: bd80 pop {r7, pc}
080068f4 <USBD_StdEPReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80068f4: b580 push {r7, lr}
80068f6: b084 sub sp, #16
80068f8: af00 add r7, sp, #0
80068fa: 6078 str r0, [r7, #4]
80068fc: 6039 str r1, [r7, #0]
USBD_EndpointTypeDef *pep;
uint8_t ep_addr;
uint8_t idx;
USBD_StatusTypeDef ret = USBD_OK;
80068fe: 2300 movs r3, #0
8006900: 73fb strb r3, [r7, #15]
ep_addr = LOBYTE(req->wIndex);
8006902: 683b ldr r3, [r7, #0]
8006904: 889b ldrh r3, [r3, #4]
8006906: 73bb strb r3, [r7, #14]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8006908: 683b ldr r3, [r7, #0]
800690a: 781b ldrb r3, [r3, #0]
800690c: f003 0360 and.w r3, r3, #96 @ 0x60
8006910: 2b40 cmp r3, #64 @ 0x40
8006912: d007 beq.n 8006924 <USBD_StdEPReq+0x30>
8006914: 2b40 cmp r3, #64 @ 0x40
8006916: f200 817f bhi.w 8006c18 <USBD_StdEPReq+0x324>
800691a: 2b00 cmp r3, #0
800691c: d02a beq.n 8006974 <USBD_StdEPReq+0x80>
800691e: 2b20 cmp r3, #32
8006920: f040 817a bne.w 8006c18 <USBD_StdEPReq+0x324>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
/* Get the class index relative to this endpoint */
idx = USBD_CoreFindEP(pdev, ep_addr);
8006924: 7bbb ldrb r3, [r7, #14]
8006926: 4619 mov r1, r3
8006928: 6878 ldr r0, [r7, #4]
800692a: f7ff fe85 bl 8006638 <USBD_CoreFindEP>
800692e: 4603 mov r3, r0
8006930: 737b strb r3, [r7, #13]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
8006932: 7b7b ldrb r3, [r7, #13]
8006934: 2bff cmp r3, #255 @ 0xff
8006936: f000 8174 beq.w 8006c22 <USBD_StdEPReq+0x32e>
800693a: 7b7b ldrb r3, [r7, #13]
800693c: 2b00 cmp r3, #0
800693e: f040 8170 bne.w 8006c22 <USBD_StdEPReq+0x32e>
{
pdev->classId = idx;
8006942: 7b7a ldrb r2, [r7, #13]
8006944: 687b ldr r3, [r7, #4]
8006946: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
800694a: 7b7a ldrb r2, [r7, #13]
800694c: 687b ldr r3, [r7, #4]
800694e: 32ae adds r2, #174 @ 0xae
8006950: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006954: 689b ldr r3, [r3, #8]
8006956: 2b00 cmp r3, #0
8006958: f000 8163 beq.w 8006c22 <USBD_StdEPReq+0x32e>
{
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
800695c: 7b7a ldrb r2, [r7, #13]
800695e: 687b ldr r3, [r7, #4]
8006960: 32ae adds r2, #174 @ 0xae
8006962: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006966: 689b ldr r3, [r3, #8]
8006968: 6839 ldr r1, [r7, #0]
800696a: 6878 ldr r0, [r7, #4]
800696c: 4798 blx r3
800696e: 4603 mov r3, r0
8006970: 73fb strb r3, [r7, #15]
}
}
break;
8006972: e156 b.n 8006c22 <USBD_StdEPReq+0x32e>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8006974: 683b ldr r3, [r7, #0]
8006976: 785b ldrb r3, [r3, #1]
8006978: 2b03 cmp r3, #3
800697a: d008 beq.n 800698e <USBD_StdEPReq+0x9a>
800697c: 2b03 cmp r3, #3
800697e: f300 8145 bgt.w 8006c0c <USBD_StdEPReq+0x318>
8006982: 2b00 cmp r3, #0
8006984: f000 809b beq.w 8006abe <USBD_StdEPReq+0x1ca>
8006988: 2b01 cmp r3, #1
800698a: d03c beq.n 8006a06 <USBD_StdEPReq+0x112>
800698c: e13e b.n 8006c0c <USBD_StdEPReq+0x318>
{
case USB_REQ_SET_FEATURE:
switch (pdev->dev_state)
800698e: 687b ldr r3, [r7, #4]
8006990: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006994: b2db uxtb r3, r3
8006996: 2b02 cmp r3, #2
8006998: d002 beq.n 80069a0 <USBD_StdEPReq+0xac>
800699a: 2b03 cmp r3, #3
800699c: d016 beq.n 80069cc <USBD_StdEPReq+0xd8>
800699e: e02c b.n 80069fa <USBD_StdEPReq+0x106>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
80069a0: 7bbb ldrb r3, [r7, #14]
80069a2: 2b00 cmp r3, #0
80069a4: d00d beq.n 80069c2 <USBD_StdEPReq+0xce>
80069a6: 7bbb ldrb r3, [r7, #14]
80069a8: 2b80 cmp r3, #128 @ 0x80
80069aa: d00a beq.n 80069c2 <USBD_StdEPReq+0xce>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
80069ac: 7bbb ldrb r3, [r7, #14]
80069ae: 4619 mov r1, r3
80069b0: 6878 ldr r0, [r7, #4]
80069b2: f001 f9b9 bl 8007d28 <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0x80U);
80069b6: 2180 movs r1, #128 @ 0x80
80069b8: 6878 ldr r0, [r7, #4]
80069ba: f001 f9b5 bl 8007d28 <USBD_LL_StallEP>
80069be: bf00 nop
}
else
{
USBD_CtlError(pdev, req);
}
break;
80069c0: e020 b.n 8006a04 <USBD_StdEPReq+0x110>
USBD_CtlError(pdev, req);
80069c2: 6839 ldr r1, [r7, #0]
80069c4: 6878 ldr r0, [r7, #4]
80069c6: f000 fca4 bl 8007312 <USBD_CtlError>
break;
80069ca: e01b b.n 8006a04 <USBD_StdEPReq+0x110>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
80069cc: 683b ldr r3, [r7, #0]
80069ce: 885b ldrh r3, [r3, #2]
80069d0: 2b00 cmp r3, #0
80069d2: d10e bne.n 80069f2 <USBD_StdEPReq+0xfe>
{
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
80069d4: 7bbb ldrb r3, [r7, #14]
80069d6: 2b00 cmp r3, #0
80069d8: d00b beq.n 80069f2 <USBD_StdEPReq+0xfe>
80069da: 7bbb ldrb r3, [r7, #14]
80069dc: 2b80 cmp r3, #128 @ 0x80
80069de: d008 beq.n 80069f2 <USBD_StdEPReq+0xfe>
80069e0: 683b ldr r3, [r7, #0]
80069e2: 88db ldrh r3, [r3, #6]
80069e4: 2b00 cmp r3, #0
80069e6: d104 bne.n 80069f2 <USBD_StdEPReq+0xfe>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
80069e8: 7bbb ldrb r3, [r7, #14]
80069ea: 4619 mov r1, r3
80069ec: 6878 ldr r0, [r7, #4]
80069ee: f001 f99b bl 8007d28 <USBD_LL_StallEP>
}
}
(void)USBD_CtlSendStatus(pdev);
80069f2: 6878 ldr r0, [r7, #4]
80069f4: f000 fd64 bl 80074c0 <USBD_CtlSendStatus>
break;
80069f8: e004 b.n 8006a04 <USBD_StdEPReq+0x110>
default:
USBD_CtlError(pdev, req);
80069fa: 6839 ldr r1, [r7, #0]
80069fc: 6878 ldr r0, [r7, #4]
80069fe: f000 fc88 bl 8007312 <USBD_CtlError>
break;
8006a02: bf00 nop
}
break;
8006a04: e107 b.n 8006c16 <USBD_StdEPReq+0x322>
case USB_REQ_CLEAR_FEATURE:
switch (pdev->dev_state)
8006a06: 687b ldr r3, [r7, #4]
8006a08: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006a0c: b2db uxtb r3, r3
8006a0e: 2b02 cmp r3, #2
8006a10: d002 beq.n 8006a18 <USBD_StdEPReq+0x124>
8006a12: 2b03 cmp r3, #3
8006a14: d016 beq.n 8006a44 <USBD_StdEPReq+0x150>
8006a16: e04b b.n 8006ab0 <USBD_StdEPReq+0x1bc>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8006a18: 7bbb ldrb r3, [r7, #14]
8006a1a: 2b00 cmp r3, #0
8006a1c: d00d beq.n 8006a3a <USBD_StdEPReq+0x146>
8006a1e: 7bbb ldrb r3, [r7, #14]
8006a20: 2b80 cmp r3, #128 @ 0x80
8006a22: d00a beq.n 8006a3a <USBD_StdEPReq+0x146>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
8006a24: 7bbb ldrb r3, [r7, #14]
8006a26: 4619 mov r1, r3
8006a28: 6878 ldr r0, [r7, #4]
8006a2a: f001 f97d bl 8007d28 <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0x80U);
8006a2e: 2180 movs r1, #128 @ 0x80
8006a30: 6878 ldr r0, [r7, #4]
8006a32: f001 f979 bl 8007d28 <USBD_LL_StallEP>
8006a36: bf00 nop
}
else
{
USBD_CtlError(pdev, req);
}
break;
8006a38: e040 b.n 8006abc <USBD_StdEPReq+0x1c8>
USBD_CtlError(pdev, req);
8006a3a: 6839 ldr r1, [r7, #0]
8006a3c: 6878 ldr r0, [r7, #4]
8006a3e: f000 fc68 bl 8007312 <USBD_CtlError>
break;
8006a42: e03b b.n 8006abc <USBD_StdEPReq+0x1c8>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8006a44: 683b ldr r3, [r7, #0]
8006a46: 885b ldrh r3, [r3, #2]
8006a48: 2b00 cmp r3, #0
8006a4a: d136 bne.n 8006aba <USBD_StdEPReq+0x1c6>
{
if ((ep_addr & 0x7FU) != 0x00U)
8006a4c: 7bbb ldrb r3, [r7, #14]
8006a4e: f003 037f and.w r3, r3, #127 @ 0x7f
8006a52: 2b00 cmp r3, #0
8006a54: d004 beq.n 8006a60 <USBD_StdEPReq+0x16c>
{
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
8006a56: 7bbb ldrb r3, [r7, #14]
8006a58: 4619 mov r1, r3
8006a5a: 6878 ldr r0, [r7, #4]
8006a5c: f001 f99a bl 8007d94 <USBD_LL_ClearStallEP>
}
(void)USBD_CtlSendStatus(pdev);
8006a60: 6878 ldr r0, [r7, #4]
8006a62: f000 fd2d bl 80074c0 <USBD_CtlSendStatus>
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, ep_addr);
8006a66: 7bbb ldrb r3, [r7, #14]
8006a68: 4619 mov r1, r3
8006a6a: 6878 ldr r0, [r7, #4]
8006a6c: f7ff fde4 bl 8006638 <USBD_CoreFindEP>
8006a70: 4603 mov r3, r0
8006a72: 737b strb r3, [r7, #13]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
8006a74: 7b7b ldrb r3, [r7, #13]
8006a76: 2bff cmp r3, #255 @ 0xff
8006a78: d01f beq.n 8006aba <USBD_StdEPReq+0x1c6>
8006a7a: 7b7b ldrb r3, [r7, #13]
8006a7c: 2b00 cmp r3, #0
8006a7e: d11c bne.n 8006aba <USBD_StdEPReq+0x1c6>
{
pdev->classId = idx;
8006a80: 7b7a ldrb r2, [r7, #13]
8006a82: 687b ldr r3, [r7, #4]
8006a84: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
8006a88: 7b7a ldrb r2, [r7, #13]
8006a8a: 687b ldr r3, [r7, #4]
8006a8c: 32ae adds r2, #174 @ 0xae
8006a8e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006a92: 689b ldr r3, [r3, #8]
8006a94: 2b00 cmp r3, #0
8006a96: d010 beq.n 8006aba <USBD_StdEPReq+0x1c6>
{
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
8006a98: 7b7a ldrb r2, [r7, #13]
8006a9a: 687b ldr r3, [r7, #4]
8006a9c: 32ae adds r2, #174 @ 0xae
8006a9e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8006aa2: 689b ldr r3, [r3, #8]
8006aa4: 6839 ldr r1, [r7, #0]
8006aa6: 6878 ldr r0, [r7, #4]
8006aa8: 4798 blx r3
8006aaa: 4603 mov r3, r0
8006aac: 73fb strb r3, [r7, #15]
}
}
}
break;
8006aae: e004 b.n 8006aba <USBD_StdEPReq+0x1c6>
default:
USBD_CtlError(pdev, req);
8006ab0: 6839 ldr r1, [r7, #0]
8006ab2: 6878 ldr r0, [r7, #4]
8006ab4: f000 fc2d bl 8007312 <USBD_CtlError>
break;
8006ab8: e000 b.n 8006abc <USBD_StdEPReq+0x1c8>
break;
8006aba: bf00 nop
}
break;
8006abc: e0ab b.n 8006c16 <USBD_StdEPReq+0x322>
case USB_REQ_GET_STATUS:
switch (pdev->dev_state)
8006abe: 687b ldr r3, [r7, #4]
8006ac0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006ac4: b2db uxtb r3, r3
8006ac6: 2b02 cmp r3, #2
8006ac8: d002 beq.n 8006ad0 <USBD_StdEPReq+0x1dc>
8006aca: 2b03 cmp r3, #3
8006acc: d032 beq.n 8006b34 <USBD_StdEPReq+0x240>
8006ace: e097 b.n 8006c00 <USBD_StdEPReq+0x30c>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8006ad0: 7bbb ldrb r3, [r7, #14]
8006ad2: 2b00 cmp r3, #0
8006ad4: d007 beq.n 8006ae6 <USBD_StdEPReq+0x1f2>
8006ad6: 7bbb ldrb r3, [r7, #14]
8006ad8: 2b80 cmp r3, #128 @ 0x80
8006ada: d004 beq.n 8006ae6 <USBD_StdEPReq+0x1f2>
{
USBD_CtlError(pdev, req);
8006adc: 6839 ldr r1, [r7, #0]
8006ade: 6878 ldr r0, [r7, #4]
8006ae0: f000 fc17 bl 8007312 <USBD_CtlError>
break;
8006ae4: e091 b.n 8006c0a <USBD_StdEPReq+0x316>
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8006ae6: f997 300e ldrsb.w r3, [r7, #14]
8006aea: 2b00 cmp r3, #0
8006aec: da0b bge.n 8006b06 <USBD_StdEPReq+0x212>
8006aee: 7bbb ldrb r3, [r7, #14]
8006af0: f003 027f and.w r2, r3, #127 @ 0x7f
8006af4: 4613 mov r3, r2
8006af6: 009b lsls r3, r3, #2
8006af8: 4413 add r3, r2
8006afa: 009b lsls r3, r3, #2
8006afc: 3310 adds r3, #16
8006afe: 687a ldr r2, [r7, #4]
8006b00: 4413 add r3, r2
8006b02: 3304 adds r3, #4
8006b04: e00b b.n 8006b1e <USBD_StdEPReq+0x22a>
&pdev->ep_out[ep_addr & 0x7FU];
8006b06: 7bbb ldrb r3, [r7, #14]
8006b08: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8006b0c: 4613 mov r3, r2
8006b0e: 009b lsls r3, r3, #2
8006b10: 4413 add r3, r2
8006b12: 009b lsls r3, r3, #2
8006b14: f503 73a8 add.w r3, r3, #336 @ 0x150
8006b18: 687a ldr r2, [r7, #4]
8006b1a: 4413 add r3, r2
8006b1c: 3304 adds r3, #4
8006b1e: 60bb str r3, [r7, #8]
pep->status = 0x0000U;
8006b20: 68bb ldr r3, [r7, #8]
8006b22: 2200 movs r2, #0
8006b24: 601a str r2, [r3, #0]
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
8006b26: 68bb ldr r3, [r7, #8]
8006b28: 2202 movs r2, #2
8006b2a: 4619 mov r1, r3
8006b2c: 6878 ldr r0, [r7, #4]
8006b2e: f000 fc6d bl 800740c <USBD_CtlSendData>
break;
8006b32: e06a b.n 8006c0a <USBD_StdEPReq+0x316>
case USBD_STATE_CONFIGURED:
if ((ep_addr & 0x80U) == 0x80U)
8006b34: f997 300e ldrsb.w r3, [r7, #14]
8006b38: 2b00 cmp r3, #0
8006b3a: da11 bge.n 8006b60 <USBD_StdEPReq+0x26c>
{
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
8006b3c: 7bbb ldrb r3, [r7, #14]
8006b3e: f003 020f and.w r2, r3, #15
8006b42: 6879 ldr r1, [r7, #4]
8006b44: 4613 mov r3, r2
8006b46: 009b lsls r3, r3, #2
8006b48: 4413 add r3, r2
8006b4a: 009b lsls r3, r3, #2
8006b4c: 440b add r3, r1
8006b4e: 3324 adds r3, #36 @ 0x24
8006b50: 881b ldrh r3, [r3, #0]
8006b52: 2b00 cmp r3, #0
8006b54: d117 bne.n 8006b86 <USBD_StdEPReq+0x292>
{
USBD_CtlError(pdev, req);
8006b56: 6839 ldr r1, [r7, #0]
8006b58: 6878 ldr r0, [r7, #4]
8006b5a: f000 fbda bl 8007312 <USBD_CtlError>
break;
8006b5e: e054 b.n 8006c0a <USBD_StdEPReq+0x316>
}
}
else
{
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
8006b60: 7bbb ldrb r3, [r7, #14]
8006b62: f003 020f and.w r2, r3, #15
8006b66: 6879 ldr r1, [r7, #4]
8006b68: 4613 mov r3, r2
8006b6a: 009b lsls r3, r3, #2
8006b6c: 4413 add r3, r2
8006b6e: 009b lsls r3, r3, #2
8006b70: 440b add r3, r1
8006b72: f503 73b2 add.w r3, r3, #356 @ 0x164
8006b76: 881b ldrh r3, [r3, #0]
8006b78: 2b00 cmp r3, #0
8006b7a: d104 bne.n 8006b86 <USBD_StdEPReq+0x292>
{
USBD_CtlError(pdev, req);
8006b7c: 6839 ldr r1, [r7, #0]
8006b7e: 6878 ldr r0, [r7, #4]
8006b80: f000 fbc7 bl 8007312 <USBD_CtlError>
break;
8006b84: e041 b.n 8006c0a <USBD_StdEPReq+0x316>
}
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8006b86: f997 300e ldrsb.w r3, [r7, #14]
8006b8a: 2b00 cmp r3, #0
8006b8c: da0b bge.n 8006ba6 <USBD_StdEPReq+0x2b2>
8006b8e: 7bbb ldrb r3, [r7, #14]
8006b90: f003 027f and.w r2, r3, #127 @ 0x7f
8006b94: 4613 mov r3, r2
8006b96: 009b lsls r3, r3, #2
8006b98: 4413 add r3, r2
8006b9a: 009b lsls r3, r3, #2
8006b9c: 3310 adds r3, #16
8006b9e: 687a ldr r2, [r7, #4]
8006ba0: 4413 add r3, r2
8006ba2: 3304 adds r3, #4
8006ba4: e00b b.n 8006bbe <USBD_StdEPReq+0x2ca>
&pdev->ep_out[ep_addr & 0x7FU];
8006ba6: 7bbb ldrb r3, [r7, #14]
8006ba8: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8006bac: 4613 mov r3, r2
8006bae: 009b lsls r3, r3, #2
8006bb0: 4413 add r3, r2
8006bb2: 009b lsls r3, r3, #2
8006bb4: f503 73a8 add.w r3, r3, #336 @ 0x150
8006bb8: 687a ldr r2, [r7, #4]
8006bba: 4413 add r3, r2
8006bbc: 3304 adds r3, #4
8006bbe: 60bb str r3, [r7, #8]
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
8006bc0: 7bbb ldrb r3, [r7, #14]
8006bc2: 2b00 cmp r3, #0
8006bc4: d002 beq.n 8006bcc <USBD_StdEPReq+0x2d8>
8006bc6: 7bbb ldrb r3, [r7, #14]
8006bc8: 2b80 cmp r3, #128 @ 0x80
8006bca: d103 bne.n 8006bd4 <USBD_StdEPReq+0x2e0>
{
pep->status = 0x0000U;
8006bcc: 68bb ldr r3, [r7, #8]
8006bce: 2200 movs r2, #0
8006bd0: 601a str r2, [r3, #0]
8006bd2: e00e b.n 8006bf2 <USBD_StdEPReq+0x2fe>
}
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
8006bd4: 7bbb ldrb r3, [r7, #14]
8006bd6: 4619 mov r1, r3
8006bd8: 6878 ldr r0, [r7, #4]
8006bda: f001 f911 bl 8007e00 <USBD_LL_IsStallEP>
8006bde: 4603 mov r3, r0
8006be0: 2b00 cmp r3, #0
8006be2: d003 beq.n 8006bec <USBD_StdEPReq+0x2f8>
{
pep->status = 0x0001U;
8006be4: 68bb ldr r3, [r7, #8]
8006be6: 2201 movs r2, #1
8006be8: 601a str r2, [r3, #0]
8006bea: e002 b.n 8006bf2 <USBD_StdEPReq+0x2fe>
}
else
{
pep->status = 0x0000U;
8006bec: 68bb ldr r3, [r7, #8]
8006bee: 2200 movs r2, #0
8006bf0: 601a str r2, [r3, #0]
}
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
8006bf2: 68bb ldr r3, [r7, #8]
8006bf4: 2202 movs r2, #2
8006bf6: 4619 mov r1, r3
8006bf8: 6878 ldr r0, [r7, #4]
8006bfa: f000 fc07 bl 800740c <USBD_CtlSendData>
break;
8006bfe: e004 b.n 8006c0a <USBD_StdEPReq+0x316>
default:
USBD_CtlError(pdev, req);
8006c00: 6839 ldr r1, [r7, #0]
8006c02: 6878 ldr r0, [r7, #4]
8006c04: f000 fb85 bl 8007312 <USBD_CtlError>
break;
8006c08: bf00 nop
}
break;
8006c0a: e004 b.n 8006c16 <USBD_StdEPReq+0x322>
default:
USBD_CtlError(pdev, req);
8006c0c: 6839 ldr r1, [r7, #0]
8006c0e: 6878 ldr r0, [r7, #4]
8006c10: f000 fb7f bl 8007312 <USBD_CtlError>
break;
8006c14: bf00 nop
}
break;
8006c16: e005 b.n 8006c24 <USBD_StdEPReq+0x330>
default:
USBD_CtlError(pdev, req);
8006c18: 6839 ldr r1, [r7, #0]
8006c1a: 6878 ldr r0, [r7, #4]
8006c1c: f000 fb79 bl 8007312 <USBD_CtlError>
break;
8006c20: e000 b.n 8006c24 <USBD_StdEPReq+0x330>
break;
8006c22: bf00 nop
}
return ret;
8006c24: 7bfb ldrb r3, [r7, #15]
}
8006c26: 4618 mov r0, r3
8006c28: 3710 adds r7, #16
8006c2a: 46bd mov sp, r7
8006c2c: bd80 pop {r7, pc}
...
08006c30 <USBD_GetDescriptor>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8006c30: b580 push {r7, lr}
8006c32: b084 sub sp, #16
8006c34: af00 add r7, sp, #0
8006c36: 6078 str r0, [r7, #4]
8006c38: 6039 str r1, [r7, #0]
uint16_t len = 0U;
8006c3a: 2300 movs r3, #0
8006c3c: 813b strh r3, [r7, #8]
uint8_t *pbuf = NULL;
8006c3e: 2300 movs r3, #0
8006c40: 60fb str r3, [r7, #12]
uint8_t err = 0U;
8006c42: 2300 movs r3, #0
8006c44: 72fb strb r3, [r7, #11]
switch (req->wValue >> 8)
8006c46: 683b ldr r3, [r7, #0]
8006c48: 885b ldrh r3, [r3, #2]
8006c4a: 0a1b lsrs r3, r3, #8
8006c4c: b29b uxth r3, r3
8006c4e: 3b01 subs r3, #1
8006c50: 2b0e cmp r3, #14
8006c52: f200 8152 bhi.w 8006efa <USBD_GetDescriptor+0x2ca>
8006c56: a201 add r2, pc, #4 @ (adr r2, 8006c5c <USBD_GetDescriptor+0x2c>)
8006c58: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006c5c: 08006ccd .word 0x08006ccd
8006c60: 08006ce5 .word 0x08006ce5
8006c64: 08006d25 .word 0x08006d25
8006c68: 08006efb .word 0x08006efb
8006c6c: 08006efb .word 0x08006efb
8006c70: 08006e9b .word 0x08006e9b
8006c74: 08006ec7 .word 0x08006ec7
8006c78: 08006efb .word 0x08006efb
8006c7c: 08006efb .word 0x08006efb
8006c80: 08006efb .word 0x08006efb
8006c84: 08006efb .word 0x08006efb
8006c88: 08006efb .word 0x08006efb
8006c8c: 08006efb .word 0x08006efb
8006c90: 08006efb .word 0x08006efb
8006c94: 08006c99 .word 0x08006c99
{
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
case USB_DESC_TYPE_BOS:
if (pdev->pDesc->GetBOSDescriptor != NULL)
8006c98: 687b ldr r3, [r7, #4]
8006c9a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006c9e: 69db ldr r3, [r3, #28]
8006ca0: 2b00 cmp r3, #0
8006ca2: d00b beq.n 8006cbc <USBD_GetDescriptor+0x8c>
{
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
8006ca4: 687b ldr r3, [r7, #4]
8006ca6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006caa: 69db ldr r3, [r3, #28]
8006cac: 687a ldr r2, [r7, #4]
8006cae: 7c12 ldrb r2, [r2, #16]
8006cb0: f107 0108 add.w r1, r7, #8
8006cb4: 4610 mov r0, r2
8006cb6: 4798 blx r3
8006cb8: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006cba: e126 b.n 8006f0a <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
8006cbc: 6839 ldr r1, [r7, #0]
8006cbe: 6878 ldr r0, [r7, #4]
8006cc0: f000 fb27 bl 8007312 <USBD_CtlError>
err++;
8006cc4: 7afb ldrb r3, [r7, #11]
8006cc6: 3301 adds r3, #1
8006cc8: 72fb strb r3, [r7, #11]
break;
8006cca: e11e b.n 8006f0a <USBD_GetDescriptor+0x2da>
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
case USB_DESC_TYPE_DEVICE:
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
8006ccc: 687b ldr r3, [r7, #4]
8006cce: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006cd2: 681b ldr r3, [r3, #0]
8006cd4: 687a ldr r2, [r7, #4]
8006cd6: 7c12 ldrb r2, [r2, #16]
8006cd8: f107 0108 add.w r1, r7, #8
8006cdc: 4610 mov r0, r2
8006cde: 4798 blx r3
8006ce0: 60f8 str r0, [r7, #12]
break;
8006ce2: e112 b.n 8006f0a <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8006ce4: 687b ldr r3, [r7, #4]
8006ce6: 7c1b ldrb r3, [r3, #16]
8006ce8: 2b00 cmp r3, #0
8006cea: d10d bne.n 8006d08 <USBD_GetDescriptor+0xd8>
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
8006cec: 687b ldr r3, [r7, #4]
8006cee: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8006cf2: 6a9b ldr r3, [r3, #40] @ 0x28
8006cf4: f107 0208 add.w r2, r7, #8
8006cf8: 4610 mov r0, r2
8006cfa: 4798 blx r3
8006cfc: 60f8 str r0, [r7, #12]
}
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
8006cfe: 68fb ldr r3, [r7, #12]
8006d00: 3301 adds r3, #1
8006d02: 2202 movs r2, #2
8006d04: 701a strb r2, [r3, #0]
{
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
}
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
}
break;
8006d06: e100 b.n 8006f0a <USBD_GetDescriptor+0x2da>
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
8006d08: 687b ldr r3, [r7, #4]
8006d0a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8006d0e: 6adb ldr r3, [r3, #44] @ 0x2c
8006d10: f107 0208 add.w r2, r7, #8
8006d14: 4610 mov r0, r2
8006d16: 4798 blx r3
8006d18: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
8006d1a: 68fb ldr r3, [r7, #12]
8006d1c: 3301 adds r3, #1
8006d1e: 2202 movs r2, #2
8006d20: 701a strb r2, [r3, #0]
break;
8006d22: e0f2 b.n 8006f0a <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_STRING:
switch ((uint8_t)(req->wValue))
8006d24: 683b ldr r3, [r7, #0]
8006d26: 885b ldrh r3, [r3, #2]
8006d28: b2db uxtb r3, r3
8006d2a: 2b05 cmp r3, #5
8006d2c: f200 80ac bhi.w 8006e88 <USBD_GetDescriptor+0x258>
8006d30: a201 add r2, pc, #4 @ (adr r2, 8006d38 <USBD_GetDescriptor+0x108>)
8006d32: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006d36: bf00 nop
8006d38: 08006d51 .word 0x08006d51
8006d3c: 08006d85 .word 0x08006d85
8006d40: 08006db9 .word 0x08006db9
8006d44: 08006ded .word 0x08006ded
8006d48: 08006e21 .word 0x08006e21
8006d4c: 08006e55 .word 0x08006e55
{
case USBD_IDX_LANGID_STR:
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
8006d50: 687b ldr r3, [r7, #4]
8006d52: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006d56: 685b ldr r3, [r3, #4]
8006d58: 2b00 cmp r3, #0
8006d5a: d00b beq.n 8006d74 <USBD_GetDescriptor+0x144>
{
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
8006d5c: 687b ldr r3, [r7, #4]
8006d5e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006d62: 685b ldr r3, [r3, #4]
8006d64: 687a ldr r2, [r7, #4]
8006d66: 7c12 ldrb r2, [r2, #16]
8006d68: f107 0108 add.w r1, r7, #8
8006d6c: 4610 mov r0, r2
8006d6e: 4798 blx r3
8006d70: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006d72: e091 b.n 8006e98 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8006d74: 6839 ldr r1, [r7, #0]
8006d76: 6878 ldr r0, [r7, #4]
8006d78: f000 facb bl 8007312 <USBD_CtlError>
err++;
8006d7c: 7afb ldrb r3, [r7, #11]
8006d7e: 3301 adds r3, #1
8006d80: 72fb strb r3, [r7, #11]
break;
8006d82: e089 b.n 8006e98 <USBD_GetDescriptor+0x268>
case USBD_IDX_MFC_STR:
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
8006d84: 687b ldr r3, [r7, #4]
8006d86: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006d8a: 689b ldr r3, [r3, #8]
8006d8c: 2b00 cmp r3, #0
8006d8e: d00b beq.n 8006da8 <USBD_GetDescriptor+0x178>
{
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
8006d90: 687b ldr r3, [r7, #4]
8006d92: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006d96: 689b ldr r3, [r3, #8]
8006d98: 687a ldr r2, [r7, #4]
8006d9a: 7c12 ldrb r2, [r2, #16]
8006d9c: f107 0108 add.w r1, r7, #8
8006da0: 4610 mov r0, r2
8006da2: 4798 blx r3
8006da4: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006da6: e077 b.n 8006e98 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8006da8: 6839 ldr r1, [r7, #0]
8006daa: 6878 ldr r0, [r7, #4]
8006dac: f000 fab1 bl 8007312 <USBD_CtlError>
err++;
8006db0: 7afb ldrb r3, [r7, #11]
8006db2: 3301 adds r3, #1
8006db4: 72fb strb r3, [r7, #11]
break;
8006db6: e06f b.n 8006e98 <USBD_GetDescriptor+0x268>
case USBD_IDX_PRODUCT_STR:
if (pdev->pDesc->GetProductStrDescriptor != NULL)
8006db8: 687b ldr r3, [r7, #4]
8006dba: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006dbe: 68db ldr r3, [r3, #12]
8006dc0: 2b00 cmp r3, #0
8006dc2: d00b beq.n 8006ddc <USBD_GetDescriptor+0x1ac>
{
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
8006dc4: 687b ldr r3, [r7, #4]
8006dc6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006dca: 68db ldr r3, [r3, #12]
8006dcc: 687a ldr r2, [r7, #4]
8006dce: 7c12 ldrb r2, [r2, #16]
8006dd0: f107 0108 add.w r1, r7, #8
8006dd4: 4610 mov r0, r2
8006dd6: 4798 blx r3
8006dd8: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006dda: e05d b.n 8006e98 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8006ddc: 6839 ldr r1, [r7, #0]
8006dde: 6878 ldr r0, [r7, #4]
8006de0: f000 fa97 bl 8007312 <USBD_CtlError>
err++;
8006de4: 7afb ldrb r3, [r7, #11]
8006de6: 3301 adds r3, #1
8006de8: 72fb strb r3, [r7, #11]
break;
8006dea: e055 b.n 8006e98 <USBD_GetDescriptor+0x268>
case USBD_IDX_SERIAL_STR:
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
8006dec: 687b ldr r3, [r7, #4]
8006dee: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006df2: 691b ldr r3, [r3, #16]
8006df4: 2b00 cmp r3, #0
8006df6: d00b beq.n 8006e10 <USBD_GetDescriptor+0x1e0>
{
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
8006df8: 687b ldr r3, [r7, #4]
8006dfa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006dfe: 691b ldr r3, [r3, #16]
8006e00: 687a ldr r2, [r7, #4]
8006e02: 7c12 ldrb r2, [r2, #16]
8006e04: f107 0108 add.w r1, r7, #8
8006e08: 4610 mov r0, r2
8006e0a: 4798 blx r3
8006e0c: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006e0e: e043 b.n 8006e98 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8006e10: 6839 ldr r1, [r7, #0]
8006e12: 6878 ldr r0, [r7, #4]
8006e14: f000 fa7d bl 8007312 <USBD_CtlError>
err++;
8006e18: 7afb ldrb r3, [r7, #11]
8006e1a: 3301 adds r3, #1
8006e1c: 72fb strb r3, [r7, #11]
break;
8006e1e: e03b b.n 8006e98 <USBD_GetDescriptor+0x268>
case USBD_IDX_CONFIG_STR:
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
8006e20: 687b ldr r3, [r7, #4]
8006e22: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006e26: 695b ldr r3, [r3, #20]
8006e28: 2b00 cmp r3, #0
8006e2a: d00b beq.n 8006e44 <USBD_GetDescriptor+0x214>
{
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
8006e2c: 687b ldr r3, [r7, #4]
8006e2e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006e32: 695b ldr r3, [r3, #20]
8006e34: 687a ldr r2, [r7, #4]
8006e36: 7c12 ldrb r2, [r2, #16]
8006e38: f107 0108 add.w r1, r7, #8
8006e3c: 4610 mov r0, r2
8006e3e: 4798 blx r3
8006e40: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006e42: e029 b.n 8006e98 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8006e44: 6839 ldr r1, [r7, #0]
8006e46: 6878 ldr r0, [r7, #4]
8006e48: f000 fa63 bl 8007312 <USBD_CtlError>
err++;
8006e4c: 7afb ldrb r3, [r7, #11]
8006e4e: 3301 adds r3, #1
8006e50: 72fb strb r3, [r7, #11]
break;
8006e52: e021 b.n 8006e98 <USBD_GetDescriptor+0x268>
case USBD_IDX_INTERFACE_STR:
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
8006e54: 687b ldr r3, [r7, #4]
8006e56: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006e5a: 699b ldr r3, [r3, #24]
8006e5c: 2b00 cmp r3, #0
8006e5e: d00b beq.n 8006e78 <USBD_GetDescriptor+0x248>
{
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
8006e60: 687b ldr r3, [r7, #4]
8006e62: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8006e66: 699b ldr r3, [r3, #24]
8006e68: 687a ldr r2, [r7, #4]
8006e6a: 7c12 ldrb r2, [r2, #16]
8006e6c: f107 0108 add.w r1, r7, #8
8006e70: 4610 mov r0, r2
8006e72: 4798 blx r3
8006e74: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006e76: e00f b.n 8006e98 <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8006e78: 6839 ldr r1, [r7, #0]
8006e7a: 6878 ldr r0, [r7, #4]
8006e7c: f000 fa49 bl 8007312 <USBD_CtlError>
err++;
8006e80: 7afb ldrb r3, [r7, #11]
8006e82: 3301 adds r3, #1
8006e84: 72fb strb r3, [r7, #11]
break;
8006e86: e007 b.n 8006e98 <USBD_GetDescriptor+0x268>
err++;
}
#endif /* USBD_SUPPORT_USER_STRING_DESC */
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
USBD_CtlError(pdev, req);
8006e88: 6839 ldr r1, [r7, #0]
8006e8a: 6878 ldr r0, [r7, #4]
8006e8c: f000 fa41 bl 8007312 <USBD_CtlError>
err++;
8006e90: 7afb ldrb r3, [r7, #11]
8006e92: 3301 adds r3, #1
8006e94: 72fb strb r3, [r7, #11]
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
break;
8006e96: bf00 nop
}
break;
8006e98: e037 b.n 8006f0a <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_DEVICE_QUALIFIER:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8006e9a: 687b ldr r3, [r7, #4]
8006e9c: 7c1b ldrb r3, [r3, #16]
8006e9e: 2b00 cmp r3, #0
8006ea0: d109 bne.n 8006eb6 <USBD_GetDescriptor+0x286>
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
8006ea2: 687b ldr r3, [r7, #4]
8006ea4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8006ea8: 6b5b ldr r3, [r3, #52] @ 0x34
8006eaa: f107 0208 add.w r2, r7, #8
8006eae: 4610 mov r0, r2
8006eb0: 4798 blx r3
8006eb2: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006eb4: e029 b.n 8006f0a <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
8006eb6: 6839 ldr r1, [r7, #0]
8006eb8: 6878 ldr r0, [r7, #4]
8006eba: f000 fa2a bl 8007312 <USBD_CtlError>
err++;
8006ebe: 7afb ldrb r3, [r7, #11]
8006ec0: 3301 adds r3, #1
8006ec2: 72fb strb r3, [r7, #11]
break;
8006ec4: e021 b.n 8006f0a <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8006ec6: 687b ldr r3, [r7, #4]
8006ec8: 7c1b ldrb r3, [r3, #16]
8006eca: 2b00 cmp r3, #0
8006ecc: d10d bne.n 8006eea <USBD_GetDescriptor+0x2ba>
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
8006ece: 687b ldr r3, [r7, #4]
8006ed0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8006ed4: 6b1b ldr r3, [r3, #48] @ 0x30
8006ed6: f107 0208 add.w r2, r7, #8
8006eda: 4610 mov r0, r2
8006edc: 4798 blx r3
8006ede: 60f8 str r0, [r7, #12]
}
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
8006ee0: 68fb ldr r3, [r7, #12]
8006ee2: 3301 adds r3, #1
8006ee4: 2207 movs r2, #7
8006ee6: 701a strb r2, [r3, #0]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8006ee8: e00f b.n 8006f0a <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
8006eea: 6839 ldr r1, [r7, #0]
8006eec: 6878 ldr r0, [r7, #4]
8006eee: f000 fa10 bl 8007312 <USBD_CtlError>
err++;
8006ef2: 7afb ldrb r3, [r7, #11]
8006ef4: 3301 adds r3, #1
8006ef6: 72fb strb r3, [r7, #11]
break;
8006ef8: e007 b.n 8006f0a <USBD_GetDescriptor+0x2da>
default:
USBD_CtlError(pdev, req);
8006efa: 6839 ldr r1, [r7, #0]
8006efc: 6878 ldr r0, [r7, #4]
8006efe: f000 fa08 bl 8007312 <USBD_CtlError>
err++;
8006f02: 7afb ldrb r3, [r7, #11]
8006f04: 3301 adds r3, #1
8006f06: 72fb strb r3, [r7, #11]
break;
8006f08: bf00 nop
}
if (err != 0U)
8006f0a: 7afb ldrb r3, [r7, #11]
8006f0c: 2b00 cmp r3, #0
8006f0e: d11e bne.n 8006f4e <USBD_GetDescriptor+0x31e>
{
return;
}
if (req->wLength != 0U)
8006f10: 683b ldr r3, [r7, #0]
8006f12: 88db ldrh r3, [r3, #6]
8006f14: 2b00 cmp r3, #0
8006f16: d016 beq.n 8006f46 <USBD_GetDescriptor+0x316>
{
if (len != 0U)
8006f18: 893b ldrh r3, [r7, #8]
8006f1a: 2b00 cmp r3, #0
8006f1c: d00e beq.n 8006f3c <USBD_GetDescriptor+0x30c>
{
len = MIN(len, req->wLength);
8006f1e: 683b ldr r3, [r7, #0]
8006f20: 88da ldrh r2, [r3, #6]
8006f22: 893b ldrh r3, [r7, #8]
8006f24: 4293 cmp r3, r2
8006f26: bf28 it cs
8006f28: 4613 movcs r3, r2
8006f2a: b29b uxth r3, r3
8006f2c: 813b strh r3, [r7, #8]
(void)USBD_CtlSendData(pdev, pbuf, len);
8006f2e: 893b ldrh r3, [r7, #8]
8006f30: 461a mov r2, r3
8006f32: 68f9 ldr r1, [r7, #12]
8006f34: 6878 ldr r0, [r7, #4]
8006f36: f000 fa69 bl 800740c <USBD_CtlSendData>
8006f3a: e009 b.n 8006f50 <USBD_GetDescriptor+0x320>
}
else
{
USBD_CtlError(pdev, req);
8006f3c: 6839 ldr r1, [r7, #0]
8006f3e: 6878 ldr r0, [r7, #4]
8006f40: f000 f9e7 bl 8007312 <USBD_CtlError>
8006f44: e004 b.n 8006f50 <USBD_GetDescriptor+0x320>
}
}
else
{
(void)USBD_CtlSendStatus(pdev);
8006f46: 6878 ldr r0, [r7, #4]
8006f48: f000 faba bl 80074c0 <USBD_CtlSendStatus>
8006f4c: e000 b.n 8006f50 <USBD_GetDescriptor+0x320>
return;
8006f4e: bf00 nop
}
}
8006f50: 3710 adds r7, #16
8006f52: 46bd mov sp, r7
8006f54: bd80 pop {r7, pc}
8006f56: bf00 nop
08006f58 <USBD_SetAddress>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8006f58: b580 push {r7, lr}
8006f5a: b084 sub sp, #16
8006f5c: af00 add r7, sp, #0
8006f5e: 6078 str r0, [r7, #4]
8006f60: 6039 str r1, [r7, #0]
uint8_t dev_addr;
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
8006f62: 683b ldr r3, [r7, #0]
8006f64: 889b ldrh r3, [r3, #4]
8006f66: 2b00 cmp r3, #0
8006f68: d131 bne.n 8006fce <USBD_SetAddress+0x76>
8006f6a: 683b ldr r3, [r7, #0]
8006f6c: 88db ldrh r3, [r3, #6]
8006f6e: 2b00 cmp r3, #0
8006f70: d12d bne.n 8006fce <USBD_SetAddress+0x76>
8006f72: 683b ldr r3, [r7, #0]
8006f74: 885b ldrh r3, [r3, #2]
8006f76: 2b7f cmp r3, #127 @ 0x7f
8006f78: d829 bhi.n 8006fce <USBD_SetAddress+0x76>
{
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
8006f7a: 683b ldr r3, [r7, #0]
8006f7c: 885b ldrh r3, [r3, #2]
8006f7e: b2db uxtb r3, r3
8006f80: f003 037f and.w r3, r3, #127 @ 0x7f
8006f84: 73fb strb r3, [r7, #15]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8006f86: 687b ldr r3, [r7, #4]
8006f88: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8006f8c: b2db uxtb r3, r3
8006f8e: 2b03 cmp r3, #3
8006f90: d104 bne.n 8006f9c <USBD_SetAddress+0x44>
{
USBD_CtlError(pdev, req);
8006f92: 6839 ldr r1, [r7, #0]
8006f94: 6878 ldr r0, [r7, #4]
8006f96: f000 f9bc bl 8007312 <USBD_CtlError>
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8006f9a: e01d b.n 8006fd8 <USBD_SetAddress+0x80>
}
else
{
pdev->dev_address = dev_addr;
8006f9c: 687b ldr r3, [r7, #4]
8006f9e: 7bfa ldrb r2, [r7, #15]
8006fa0: f883 229e strb.w r2, [r3, #670] @ 0x29e
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
8006fa4: 7bfb ldrb r3, [r7, #15]
8006fa6: 4619 mov r1, r3
8006fa8: 6878 ldr r0, [r7, #4]
8006faa: f000 ff55 bl 8007e58 <USBD_LL_SetUSBAddress>
(void)USBD_CtlSendStatus(pdev);
8006fae: 6878 ldr r0, [r7, #4]
8006fb0: f000 fa86 bl 80074c0 <USBD_CtlSendStatus>
if (dev_addr != 0U)
8006fb4: 7bfb ldrb r3, [r7, #15]
8006fb6: 2b00 cmp r3, #0
8006fb8: d004 beq.n 8006fc4 <USBD_SetAddress+0x6c>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
8006fba: 687b ldr r3, [r7, #4]
8006fbc: 2202 movs r2, #2
8006fbe: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8006fc2: e009 b.n 8006fd8 <USBD_SetAddress+0x80>
}
else
{
pdev->dev_state = USBD_STATE_DEFAULT;
8006fc4: 687b ldr r3, [r7, #4]
8006fc6: 2201 movs r2, #1
8006fc8: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8006fcc: e004 b.n 8006fd8 <USBD_SetAddress+0x80>
}
}
}
else
{
USBD_CtlError(pdev, req);
8006fce: 6839 ldr r1, [r7, #0]
8006fd0: 6878 ldr r0, [r7, #4]
8006fd2: f000 f99e bl 8007312 <USBD_CtlError>
}
}
8006fd6: bf00 nop
8006fd8: bf00 nop
8006fda: 3710 adds r7, #16
8006fdc: 46bd mov sp, r7
8006fde: bd80 pop {r7, pc}
08006fe0 <USBD_SetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8006fe0: b580 push {r7, lr}
8006fe2: b084 sub sp, #16
8006fe4: af00 add r7, sp, #0
8006fe6: 6078 str r0, [r7, #4]
8006fe8: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8006fea: 2300 movs r3, #0
8006fec: 73fb strb r3, [r7, #15]
static uint8_t cfgidx;
cfgidx = (uint8_t)(req->wValue);
8006fee: 683b ldr r3, [r7, #0]
8006ff0: 885b ldrh r3, [r3, #2]
8006ff2: b2da uxtb r2, r3
8006ff4: 4b4e ldr r3, [pc, #312] @ (8007130 <USBD_SetConfig+0x150>)
8006ff6: 701a strb r2, [r3, #0]
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
8006ff8: 4b4d ldr r3, [pc, #308] @ (8007130 <USBD_SetConfig+0x150>)
8006ffa: 781b ldrb r3, [r3, #0]
8006ffc: 2b01 cmp r3, #1
8006ffe: d905 bls.n 800700c <USBD_SetConfig+0x2c>
{
USBD_CtlError(pdev, req);
8007000: 6839 ldr r1, [r7, #0]
8007002: 6878 ldr r0, [r7, #4]
8007004: f000 f985 bl 8007312 <USBD_CtlError>
return USBD_FAIL;
8007008: 2303 movs r3, #3
800700a: e08c b.n 8007126 <USBD_SetConfig+0x146>
}
switch (pdev->dev_state)
800700c: 687b ldr r3, [r7, #4]
800700e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007012: b2db uxtb r3, r3
8007014: 2b02 cmp r3, #2
8007016: d002 beq.n 800701e <USBD_SetConfig+0x3e>
8007018: 2b03 cmp r3, #3
800701a: d029 beq.n 8007070 <USBD_SetConfig+0x90>
800701c: e075 b.n 800710a <USBD_SetConfig+0x12a>
{
case USBD_STATE_ADDRESSED:
if (cfgidx != 0U)
800701e: 4b44 ldr r3, [pc, #272] @ (8007130 <USBD_SetConfig+0x150>)
8007020: 781b ldrb r3, [r3, #0]
8007022: 2b00 cmp r3, #0
8007024: d020 beq.n 8007068 <USBD_SetConfig+0x88>
{
pdev->dev_config = cfgidx;
8007026: 4b42 ldr r3, [pc, #264] @ (8007130 <USBD_SetConfig+0x150>)
8007028: 781b ldrb r3, [r3, #0]
800702a: 461a mov r2, r3
800702c: 687b ldr r3, [r7, #4]
800702e: 605a str r2, [r3, #4]
ret = USBD_SetClassConfig(pdev, cfgidx);
8007030: 4b3f ldr r3, [pc, #252] @ (8007130 <USBD_SetConfig+0x150>)
8007032: 781b ldrb r3, [r3, #0]
8007034: 4619 mov r1, r3
8007036: 6878 ldr r0, [r7, #4]
8007038: f7fe ffb9 bl 8005fae <USBD_SetClassConfig>
800703c: 4603 mov r3, r0
800703e: 73fb strb r3, [r7, #15]
if (ret != USBD_OK)
8007040: 7bfb ldrb r3, [r7, #15]
8007042: 2b00 cmp r3, #0
8007044: d008 beq.n 8007058 <USBD_SetConfig+0x78>
{
USBD_CtlError(pdev, req);
8007046: 6839 ldr r1, [r7, #0]
8007048: 6878 ldr r0, [r7, #4]
800704a: f000 f962 bl 8007312 <USBD_CtlError>
pdev->dev_state = USBD_STATE_ADDRESSED;
800704e: 687b ldr r3, [r7, #4]
8007050: 2202 movs r2, #2
8007052: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
else
{
(void)USBD_CtlSendStatus(pdev);
}
break;
8007056: e065 b.n 8007124 <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
8007058: 6878 ldr r0, [r7, #4]
800705a: f000 fa31 bl 80074c0 <USBD_CtlSendStatus>
pdev->dev_state = USBD_STATE_CONFIGURED;
800705e: 687b ldr r3, [r7, #4]
8007060: 2203 movs r2, #3
8007062: f883 229c strb.w r2, [r3, #668] @ 0x29c
break;
8007066: e05d b.n 8007124 <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
8007068: 6878 ldr r0, [r7, #4]
800706a: f000 fa29 bl 80074c0 <USBD_CtlSendStatus>
break;
800706e: e059 b.n 8007124 <USBD_SetConfig+0x144>
case USBD_STATE_CONFIGURED:
if (cfgidx == 0U)
8007070: 4b2f ldr r3, [pc, #188] @ (8007130 <USBD_SetConfig+0x150>)
8007072: 781b ldrb r3, [r3, #0]
8007074: 2b00 cmp r3, #0
8007076: d112 bne.n 800709e <USBD_SetConfig+0xbe>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
8007078: 687b ldr r3, [r7, #4]
800707a: 2202 movs r2, #2
800707c: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->dev_config = cfgidx;
8007080: 4b2b ldr r3, [pc, #172] @ (8007130 <USBD_SetConfig+0x150>)
8007082: 781b ldrb r3, [r3, #0]
8007084: 461a mov r2, r3
8007086: 687b ldr r3, [r7, #4]
8007088: 605a str r2, [r3, #4]
(void)USBD_ClrClassConfig(pdev, cfgidx);
800708a: 4b29 ldr r3, [pc, #164] @ (8007130 <USBD_SetConfig+0x150>)
800708c: 781b ldrb r3, [r3, #0]
800708e: 4619 mov r1, r3
8007090: 6878 ldr r0, [r7, #4]
8007092: f7fe ffa8 bl 8005fe6 <USBD_ClrClassConfig>
(void)USBD_CtlSendStatus(pdev);
8007096: 6878 ldr r0, [r7, #4]
8007098: f000 fa12 bl 80074c0 <USBD_CtlSendStatus>
}
else
{
(void)USBD_CtlSendStatus(pdev);
}
break;
800709c: e042 b.n 8007124 <USBD_SetConfig+0x144>
else if (cfgidx != pdev->dev_config)
800709e: 4b24 ldr r3, [pc, #144] @ (8007130 <USBD_SetConfig+0x150>)
80070a0: 781b ldrb r3, [r3, #0]
80070a2: 461a mov r2, r3
80070a4: 687b ldr r3, [r7, #4]
80070a6: 685b ldr r3, [r3, #4]
80070a8: 429a cmp r2, r3
80070aa: d02a beq.n 8007102 <USBD_SetConfig+0x122>
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
80070ac: 687b ldr r3, [r7, #4]
80070ae: 685b ldr r3, [r3, #4]
80070b0: b2db uxtb r3, r3
80070b2: 4619 mov r1, r3
80070b4: 6878 ldr r0, [r7, #4]
80070b6: f7fe ff96 bl 8005fe6 <USBD_ClrClassConfig>
pdev->dev_config = cfgidx;
80070ba: 4b1d ldr r3, [pc, #116] @ (8007130 <USBD_SetConfig+0x150>)
80070bc: 781b ldrb r3, [r3, #0]
80070be: 461a mov r2, r3
80070c0: 687b ldr r3, [r7, #4]
80070c2: 605a str r2, [r3, #4]
ret = USBD_SetClassConfig(pdev, cfgidx);
80070c4: 4b1a ldr r3, [pc, #104] @ (8007130 <USBD_SetConfig+0x150>)
80070c6: 781b ldrb r3, [r3, #0]
80070c8: 4619 mov r1, r3
80070ca: 6878 ldr r0, [r7, #4]
80070cc: f7fe ff6f bl 8005fae <USBD_SetClassConfig>
80070d0: 4603 mov r3, r0
80070d2: 73fb strb r3, [r7, #15]
if (ret != USBD_OK)
80070d4: 7bfb ldrb r3, [r7, #15]
80070d6: 2b00 cmp r3, #0
80070d8: d00f beq.n 80070fa <USBD_SetConfig+0x11a>
USBD_CtlError(pdev, req);
80070da: 6839 ldr r1, [r7, #0]
80070dc: 6878 ldr r0, [r7, #4]
80070de: f000 f918 bl 8007312 <USBD_CtlError>
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
80070e2: 687b ldr r3, [r7, #4]
80070e4: 685b ldr r3, [r3, #4]
80070e6: b2db uxtb r3, r3
80070e8: 4619 mov r1, r3
80070ea: 6878 ldr r0, [r7, #4]
80070ec: f7fe ff7b bl 8005fe6 <USBD_ClrClassConfig>
pdev->dev_state = USBD_STATE_ADDRESSED;
80070f0: 687b ldr r3, [r7, #4]
80070f2: 2202 movs r2, #2
80070f4: f883 229c strb.w r2, [r3, #668] @ 0x29c
break;
80070f8: e014 b.n 8007124 <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
80070fa: 6878 ldr r0, [r7, #4]
80070fc: f000 f9e0 bl 80074c0 <USBD_CtlSendStatus>
break;
8007100: e010 b.n 8007124 <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
8007102: 6878 ldr r0, [r7, #4]
8007104: f000 f9dc bl 80074c0 <USBD_CtlSendStatus>
break;
8007108: e00c b.n 8007124 <USBD_SetConfig+0x144>
default:
USBD_CtlError(pdev, req);
800710a: 6839 ldr r1, [r7, #0]
800710c: 6878 ldr r0, [r7, #4]
800710e: f000 f900 bl 8007312 <USBD_CtlError>
(void)USBD_ClrClassConfig(pdev, cfgidx);
8007112: 4b07 ldr r3, [pc, #28] @ (8007130 <USBD_SetConfig+0x150>)
8007114: 781b ldrb r3, [r3, #0]
8007116: 4619 mov r1, r3
8007118: 6878 ldr r0, [r7, #4]
800711a: f7fe ff64 bl 8005fe6 <USBD_ClrClassConfig>
ret = USBD_FAIL;
800711e: 2303 movs r3, #3
8007120: 73fb strb r3, [r7, #15]
break;
8007122: bf00 nop
}
return ret;
8007124: 7bfb ldrb r3, [r7, #15]
}
8007126: 4618 mov r0, r3
8007128: 3710 adds r7, #16
800712a: 46bd mov sp, r7
800712c: bd80 pop {r7, pc}
800712e: bf00 nop
8007130: 200001a0 .word 0x200001a0
08007134 <USBD_GetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8007134: b580 push {r7, lr}
8007136: b082 sub sp, #8
8007138: af00 add r7, sp, #0
800713a: 6078 str r0, [r7, #4]
800713c: 6039 str r1, [r7, #0]
if (req->wLength != 1U)
800713e: 683b ldr r3, [r7, #0]
8007140: 88db ldrh r3, [r3, #6]
8007142: 2b01 cmp r3, #1
8007144: d004 beq.n 8007150 <USBD_GetConfig+0x1c>
{
USBD_CtlError(pdev, req);
8007146: 6839 ldr r1, [r7, #0]
8007148: 6878 ldr r0, [r7, #4]
800714a: f000 f8e2 bl 8007312 <USBD_CtlError>
default:
USBD_CtlError(pdev, req);
break;
}
}
}
800714e: e023 b.n 8007198 <USBD_GetConfig+0x64>
switch (pdev->dev_state)
8007150: 687b ldr r3, [r7, #4]
8007152: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007156: b2db uxtb r3, r3
8007158: 2b02 cmp r3, #2
800715a: dc02 bgt.n 8007162 <USBD_GetConfig+0x2e>
800715c: 2b00 cmp r3, #0
800715e: dc03 bgt.n 8007168 <USBD_GetConfig+0x34>
8007160: e015 b.n 800718e <USBD_GetConfig+0x5a>
8007162: 2b03 cmp r3, #3
8007164: d00b beq.n 800717e <USBD_GetConfig+0x4a>
8007166: e012 b.n 800718e <USBD_GetConfig+0x5a>
pdev->dev_default_config = 0U;
8007168: 687b ldr r3, [r7, #4]
800716a: 2200 movs r2, #0
800716c: 609a str r2, [r3, #8]
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
800716e: 687b ldr r3, [r7, #4]
8007170: 3308 adds r3, #8
8007172: 2201 movs r2, #1
8007174: 4619 mov r1, r3
8007176: 6878 ldr r0, [r7, #4]
8007178: f000 f948 bl 800740c <USBD_CtlSendData>
break;
800717c: e00c b.n 8007198 <USBD_GetConfig+0x64>
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
800717e: 687b ldr r3, [r7, #4]
8007180: 3304 adds r3, #4
8007182: 2201 movs r2, #1
8007184: 4619 mov r1, r3
8007186: 6878 ldr r0, [r7, #4]
8007188: f000 f940 bl 800740c <USBD_CtlSendData>
break;
800718c: e004 b.n 8007198 <USBD_GetConfig+0x64>
USBD_CtlError(pdev, req);
800718e: 6839 ldr r1, [r7, #0]
8007190: 6878 ldr r0, [r7, #4]
8007192: f000 f8be bl 8007312 <USBD_CtlError>
break;
8007196: bf00 nop
}
8007198: bf00 nop
800719a: 3708 adds r7, #8
800719c: 46bd mov sp, r7
800719e: bd80 pop {r7, pc}
080071a0 <USBD_GetStatus>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80071a0: b580 push {r7, lr}
80071a2: b082 sub sp, #8
80071a4: af00 add r7, sp, #0
80071a6: 6078 str r0, [r7, #4]
80071a8: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
80071aa: 687b ldr r3, [r7, #4]
80071ac: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80071b0: b2db uxtb r3, r3
80071b2: 3b01 subs r3, #1
80071b4: 2b02 cmp r3, #2
80071b6: d81e bhi.n 80071f6 <USBD_GetStatus+0x56>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wLength != 0x2U)
80071b8: 683b ldr r3, [r7, #0]
80071ba: 88db ldrh r3, [r3, #6]
80071bc: 2b02 cmp r3, #2
80071be: d004 beq.n 80071ca <USBD_GetStatus+0x2a>
{
USBD_CtlError(pdev, req);
80071c0: 6839 ldr r1, [r7, #0]
80071c2: 6878 ldr r0, [r7, #4]
80071c4: f000 f8a5 bl 8007312 <USBD_CtlError>
break;
80071c8: e01a b.n 8007200 <USBD_GetStatus+0x60>
}
#if (USBD_SELF_POWERED == 1U)
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
80071ca: 687b ldr r3, [r7, #4]
80071cc: 2201 movs r2, #1
80071ce: 60da str r2, [r3, #12]
#else
pdev->dev_config_status = 0U;
#endif /* USBD_SELF_POWERED */
if (pdev->dev_remote_wakeup != 0U)
80071d0: 687b ldr r3, [r7, #4]
80071d2: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
80071d6: 2b00 cmp r3, #0
80071d8: d005 beq.n 80071e6 <USBD_GetStatus+0x46>
{
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
80071da: 687b ldr r3, [r7, #4]
80071dc: 68db ldr r3, [r3, #12]
80071de: f043 0202 orr.w r2, r3, #2
80071e2: 687b ldr r3, [r7, #4]
80071e4: 60da str r2, [r3, #12]
}
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
80071e6: 687b ldr r3, [r7, #4]
80071e8: 330c adds r3, #12
80071ea: 2202 movs r2, #2
80071ec: 4619 mov r1, r3
80071ee: 6878 ldr r0, [r7, #4]
80071f0: f000 f90c bl 800740c <USBD_CtlSendData>
break;
80071f4: e004 b.n 8007200 <USBD_GetStatus+0x60>
default:
USBD_CtlError(pdev, req);
80071f6: 6839 ldr r1, [r7, #0]
80071f8: 6878 ldr r0, [r7, #4]
80071fa: f000 f88a bl 8007312 <USBD_CtlError>
break;
80071fe: bf00 nop
}
}
8007200: bf00 nop
8007202: 3708 adds r7, #8
8007204: 46bd mov sp, r7
8007206: bd80 pop {r7, pc}
08007208 <USBD_SetFeature>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8007208: b580 push {r7, lr}
800720a: b082 sub sp, #8
800720c: af00 add r7, sp, #0
800720e: 6078 str r0, [r7, #4]
8007210: 6039 str r1, [r7, #0]
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
8007212: 683b ldr r3, [r7, #0]
8007214: 885b ldrh r3, [r3, #2]
8007216: 2b01 cmp r3, #1
8007218: d107 bne.n 800722a <USBD_SetFeature+0x22>
{
pdev->dev_remote_wakeup = 1U;
800721a: 687b ldr r3, [r7, #4]
800721c: 2201 movs r2, #1
800721e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
(void)USBD_CtlSendStatus(pdev);
8007222: 6878 ldr r0, [r7, #4]
8007224: f000 f94c bl 80074c0 <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
}
8007228: e013 b.n 8007252 <USBD_SetFeature+0x4a>
else if (req->wValue == USB_FEATURE_TEST_MODE)
800722a: 683b ldr r3, [r7, #0]
800722c: 885b ldrh r3, [r3, #2]
800722e: 2b02 cmp r3, #2
8007230: d10b bne.n 800724a <USBD_SetFeature+0x42>
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
8007232: 683b ldr r3, [r7, #0]
8007234: 889b ldrh r3, [r3, #4]
8007236: 0a1b lsrs r3, r3, #8
8007238: b29b uxth r3, r3
800723a: b2da uxtb r2, r3
800723c: 687b ldr r3, [r7, #4]
800723e: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
(void)USBD_CtlSendStatus(pdev);
8007242: 6878 ldr r0, [r7, #4]
8007244: f000 f93c bl 80074c0 <USBD_CtlSendStatus>
}
8007248: e003 b.n 8007252 <USBD_SetFeature+0x4a>
USBD_CtlError(pdev, req);
800724a: 6839 ldr r1, [r7, #0]
800724c: 6878 ldr r0, [r7, #4]
800724e: f000 f860 bl 8007312 <USBD_CtlError>
}
8007252: bf00 nop
8007254: 3708 adds r7, #8
8007256: 46bd mov sp, r7
8007258: bd80 pop {r7, pc}
0800725a <USBD_ClrFeature>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800725a: b580 push {r7, lr}
800725c: b082 sub sp, #8
800725e: af00 add r7, sp, #0
8007260: 6078 str r0, [r7, #4]
8007262: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
8007264: 687b ldr r3, [r7, #4]
8007266: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800726a: b2db uxtb r3, r3
800726c: 3b01 subs r3, #1
800726e: 2b02 cmp r3, #2
8007270: d80b bhi.n 800728a <USBD_ClrFeature+0x30>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
8007272: 683b ldr r3, [r7, #0]
8007274: 885b ldrh r3, [r3, #2]
8007276: 2b01 cmp r3, #1
8007278: d10c bne.n 8007294 <USBD_ClrFeature+0x3a>
{
pdev->dev_remote_wakeup = 0U;
800727a: 687b ldr r3, [r7, #4]
800727c: 2200 movs r2, #0
800727e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
(void)USBD_CtlSendStatus(pdev);
8007282: 6878 ldr r0, [r7, #4]
8007284: f000 f91c bl 80074c0 <USBD_CtlSendStatus>
}
break;
8007288: e004 b.n 8007294 <USBD_ClrFeature+0x3a>
default:
USBD_CtlError(pdev, req);
800728a: 6839 ldr r1, [r7, #0]
800728c: 6878 ldr r0, [r7, #4]
800728e: f000 f840 bl 8007312 <USBD_CtlError>
break;
8007292: e000 b.n 8007296 <USBD_ClrFeature+0x3c>
break;
8007294: bf00 nop
}
}
8007296: bf00 nop
8007298: 3708 adds r7, #8
800729a: 46bd mov sp, r7
800729c: bd80 pop {r7, pc}
0800729e <USBD_ParseSetupRequest>:
* @param req: usb request
* @param pdata: setup data pointer
* @retval None
*/
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
{
800729e: b580 push {r7, lr}
80072a0: b084 sub sp, #16
80072a2: af00 add r7, sp, #0
80072a4: 6078 str r0, [r7, #4]
80072a6: 6039 str r1, [r7, #0]
uint8_t *pbuff = pdata;
80072a8: 683b ldr r3, [r7, #0]
80072aa: 60fb str r3, [r7, #12]
req->bmRequest = *(uint8_t *)(pbuff);
80072ac: 68fb ldr r3, [r7, #12]
80072ae: 781a ldrb r2, [r3, #0]
80072b0: 687b ldr r3, [r7, #4]
80072b2: 701a strb r2, [r3, #0]
pbuff++;
80072b4: 68fb ldr r3, [r7, #12]
80072b6: 3301 adds r3, #1
80072b8: 60fb str r3, [r7, #12]
req->bRequest = *(uint8_t *)(pbuff);
80072ba: 68fb ldr r3, [r7, #12]
80072bc: 781a ldrb r2, [r3, #0]
80072be: 687b ldr r3, [r7, #4]
80072c0: 705a strb r2, [r3, #1]
pbuff++;
80072c2: 68fb ldr r3, [r7, #12]
80072c4: 3301 adds r3, #1
80072c6: 60fb str r3, [r7, #12]
req->wValue = SWAPBYTE(pbuff);
80072c8: 68f8 ldr r0, [r7, #12]
80072ca: f7ff fa16 bl 80066fa <SWAPBYTE>
80072ce: 4603 mov r3, r0
80072d0: 461a mov r2, r3
80072d2: 687b ldr r3, [r7, #4]
80072d4: 805a strh r2, [r3, #2]
pbuff++;
80072d6: 68fb ldr r3, [r7, #12]
80072d8: 3301 adds r3, #1
80072da: 60fb str r3, [r7, #12]
pbuff++;
80072dc: 68fb ldr r3, [r7, #12]
80072de: 3301 adds r3, #1
80072e0: 60fb str r3, [r7, #12]
req->wIndex = SWAPBYTE(pbuff);
80072e2: 68f8 ldr r0, [r7, #12]
80072e4: f7ff fa09 bl 80066fa <SWAPBYTE>
80072e8: 4603 mov r3, r0
80072ea: 461a mov r2, r3
80072ec: 687b ldr r3, [r7, #4]
80072ee: 809a strh r2, [r3, #4]
pbuff++;
80072f0: 68fb ldr r3, [r7, #12]
80072f2: 3301 adds r3, #1
80072f4: 60fb str r3, [r7, #12]
pbuff++;
80072f6: 68fb ldr r3, [r7, #12]
80072f8: 3301 adds r3, #1
80072fa: 60fb str r3, [r7, #12]
req->wLength = SWAPBYTE(pbuff);
80072fc: 68f8 ldr r0, [r7, #12]
80072fe: f7ff f9fc bl 80066fa <SWAPBYTE>
8007302: 4603 mov r3, r0
8007304: 461a mov r2, r3
8007306: 687b ldr r3, [r7, #4]
8007308: 80da strh r2, [r3, #6]
}
800730a: bf00 nop
800730c: 3710 adds r7, #16
800730e: 46bd mov sp, r7
8007310: bd80 pop {r7, pc}
08007312 <USBD_CtlError>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8007312: b580 push {r7, lr}
8007314: b082 sub sp, #8
8007316: af00 add r7, sp, #0
8007318: 6078 str r0, [r7, #4]
800731a: 6039 str r1, [r7, #0]
UNUSED(req);
(void)USBD_LL_StallEP(pdev, 0x80U);
800731c: 2180 movs r1, #128 @ 0x80
800731e: 6878 ldr r0, [r7, #4]
8007320: f000 fd02 bl 8007d28 <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0U);
8007324: 2100 movs r1, #0
8007326: 6878 ldr r0, [r7, #4]
8007328: f000 fcfe bl 8007d28 <USBD_LL_StallEP>
}
800732c: bf00 nop
800732e: 3708 adds r7, #8
8007330: 46bd mov sp, r7
8007332: bd80 pop {r7, pc}
08007334 <USBD_GetString>:
* @param unicode : Formatted string buffer (unicode)
* @param len : descriptor length
* @retval None
*/
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
{
8007334: b580 push {r7, lr}
8007336: b086 sub sp, #24
8007338: af00 add r7, sp, #0
800733a: 60f8 str r0, [r7, #12]
800733c: 60b9 str r1, [r7, #8]
800733e: 607a str r2, [r7, #4]
uint8_t idx = 0U;
8007340: 2300 movs r3, #0
8007342: 75fb strb r3, [r7, #23]
uint8_t *pdesc;
if (desc == NULL)
8007344: 68fb ldr r3, [r7, #12]
8007346: 2b00 cmp r3, #0
8007348: d042 beq.n 80073d0 <USBD_GetString+0x9c>
{
return;
}
pdesc = desc;
800734a: 68fb ldr r3, [r7, #12]
800734c: 613b str r3, [r7, #16]
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
800734e: 6938 ldr r0, [r7, #16]
8007350: f000 f842 bl 80073d8 <USBD_GetLen>
8007354: 4603 mov r3, r0
8007356: 3301 adds r3, #1
8007358: 005b lsls r3, r3, #1
800735a: f5b3 7f00 cmp.w r3, #512 @ 0x200
800735e: d808 bhi.n 8007372 <USBD_GetString+0x3e>
8007360: 6938 ldr r0, [r7, #16]
8007362: f000 f839 bl 80073d8 <USBD_GetLen>
8007366: 4603 mov r3, r0
8007368: 3301 adds r3, #1
800736a: b29b uxth r3, r3
800736c: 005b lsls r3, r3, #1
800736e: b29a uxth r2, r3
8007370: e001 b.n 8007376 <USBD_GetString+0x42>
8007372: f44f 7200 mov.w r2, #512 @ 0x200
8007376: 687b ldr r3, [r7, #4]
8007378: 801a strh r2, [r3, #0]
unicode[idx] = *(uint8_t *)len;
800737a: 7dfb ldrb r3, [r7, #23]
800737c: 68ba ldr r2, [r7, #8]
800737e: 4413 add r3, r2
8007380: 687a ldr r2, [r7, #4]
8007382: 7812 ldrb r2, [r2, #0]
8007384: 701a strb r2, [r3, #0]
idx++;
8007386: 7dfb ldrb r3, [r7, #23]
8007388: 3301 adds r3, #1
800738a: 75fb strb r3, [r7, #23]
unicode[idx] = USB_DESC_TYPE_STRING;
800738c: 7dfb ldrb r3, [r7, #23]
800738e: 68ba ldr r2, [r7, #8]
8007390: 4413 add r3, r2
8007392: 2203 movs r2, #3
8007394: 701a strb r2, [r3, #0]
idx++;
8007396: 7dfb ldrb r3, [r7, #23]
8007398: 3301 adds r3, #1
800739a: 75fb strb r3, [r7, #23]
while (*pdesc != (uint8_t)'\0')
800739c: e013 b.n 80073c6 <USBD_GetString+0x92>
{
unicode[idx] = *pdesc;
800739e: 7dfb ldrb r3, [r7, #23]
80073a0: 68ba ldr r2, [r7, #8]
80073a2: 4413 add r3, r2
80073a4: 693a ldr r2, [r7, #16]
80073a6: 7812 ldrb r2, [r2, #0]
80073a8: 701a strb r2, [r3, #0]
pdesc++;
80073aa: 693b ldr r3, [r7, #16]
80073ac: 3301 adds r3, #1
80073ae: 613b str r3, [r7, #16]
idx++;
80073b0: 7dfb ldrb r3, [r7, #23]
80073b2: 3301 adds r3, #1
80073b4: 75fb strb r3, [r7, #23]
unicode[idx] = 0U;
80073b6: 7dfb ldrb r3, [r7, #23]
80073b8: 68ba ldr r2, [r7, #8]
80073ba: 4413 add r3, r2
80073bc: 2200 movs r2, #0
80073be: 701a strb r2, [r3, #0]
idx++;
80073c0: 7dfb ldrb r3, [r7, #23]
80073c2: 3301 adds r3, #1
80073c4: 75fb strb r3, [r7, #23]
while (*pdesc != (uint8_t)'\0')
80073c6: 693b ldr r3, [r7, #16]
80073c8: 781b ldrb r3, [r3, #0]
80073ca: 2b00 cmp r3, #0
80073cc: d1e7 bne.n 800739e <USBD_GetString+0x6a>
80073ce: e000 b.n 80073d2 <USBD_GetString+0x9e>
return;
80073d0: bf00 nop
}
}
80073d2: 3718 adds r7, #24
80073d4: 46bd mov sp, r7
80073d6: bd80 pop {r7, pc}
080073d8 <USBD_GetLen>:
* return the string length
* @param buf : pointer to the ascii string buffer
* @retval string length
*/
static uint8_t USBD_GetLen(uint8_t *buf)
{
80073d8: b480 push {r7}
80073da: b085 sub sp, #20
80073dc: af00 add r7, sp, #0
80073de: 6078 str r0, [r7, #4]
uint8_t len = 0U;
80073e0: 2300 movs r3, #0
80073e2: 73fb strb r3, [r7, #15]
uint8_t *pbuff = buf;
80073e4: 687b ldr r3, [r7, #4]
80073e6: 60bb str r3, [r7, #8]
while (*pbuff != (uint8_t)'\0')
80073e8: e005 b.n 80073f6 <USBD_GetLen+0x1e>
{
len++;
80073ea: 7bfb ldrb r3, [r7, #15]
80073ec: 3301 adds r3, #1
80073ee: 73fb strb r3, [r7, #15]
pbuff++;
80073f0: 68bb ldr r3, [r7, #8]
80073f2: 3301 adds r3, #1
80073f4: 60bb str r3, [r7, #8]
while (*pbuff != (uint8_t)'\0')
80073f6: 68bb ldr r3, [r7, #8]
80073f8: 781b ldrb r3, [r3, #0]
80073fa: 2b00 cmp r3, #0
80073fc: d1f5 bne.n 80073ea <USBD_GetLen+0x12>
}
return len;
80073fe: 7bfb ldrb r3, [r7, #15]
}
8007400: 4618 mov r0, r3
8007402: 3714 adds r7, #20
8007404: 46bd mov sp, r7
8007406: f85d 7b04 ldr.w r7, [sp], #4
800740a: 4770 bx lr
0800740c <USBD_CtlSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
800740c: b580 push {r7, lr}
800740e: b084 sub sp, #16
8007410: af00 add r7, sp, #0
8007412: 60f8 str r0, [r7, #12]
8007414: 60b9 str r1, [r7, #8]
8007416: 607a str r2, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
8007418: 68fb ldr r3, [r7, #12]
800741a: 2202 movs r2, #2
800741c: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_in[0].total_length = len;
8007420: 68fb ldr r3, [r7, #12]
8007422: 687a ldr r2, [r7, #4]
8007424: 619a str r2, [r3, #24]
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
pdev->ep_in[0].rem_length = 0U;
#else
pdev->ep_in[0].rem_length = len;
8007426: 68fb ldr r3, [r7, #12]
8007428: 687a ldr r2, [r7, #4]
800742a: 61da str r2, [r3, #28]
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
/* Start the transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800742c: 687b ldr r3, [r7, #4]
800742e: 68ba ldr r2, [r7, #8]
8007430: 2100 movs r1, #0
8007432: 68f8 ldr r0, [r7, #12]
8007434: f000 fd46 bl 8007ec4 <USBD_LL_Transmit>
return USBD_OK;
8007438: 2300 movs r3, #0
}
800743a: 4618 mov r0, r3
800743c: 3710 adds r7, #16
800743e: 46bd mov sp, r7
8007440: bd80 pop {r7, pc}
08007442 <USBD_CtlContinueSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
8007442: b580 push {r7, lr}
8007444: b084 sub sp, #16
8007446: af00 add r7, sp, #0
8007448: 60f8 str r0, [r7, #12]
800744a: 60b9 str r1, [r7, #8]
800744c: 607a str r2, [r7, #4]
/* Start the next transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800744e: 687b ldr r3, [r7, #4]
8007450: 68ba ldr r2, [r7, #8]
8007452: 2100 movs r1, #0
8007454: 68f8 ldr r0, [r7, #12]
8007456: f000 fd35 bl 8007ec4 <USBD_LL_Transmit>
return USBD_OK;
800745a: 2300 movs r3, #0
}
800745c: 4618 mov r0, r3
800745e: 3710 adds r7, #16
8007460: 46bd mov sp, r7
8007462: bd80 pop {r7, pc}
08007464 <USBD_CtlPrepareRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
8007464: b580 push {r7, lr}
8007466: b084 sub sp, #16
8007468: af00 add r7, sp, #0
800746a: 60f8 str r0, [r7, #12]
800746c: 60b9 str r1, [r7, #8]
800746e: 607a str r2, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
8007470: 68fb ldr r3, [r7, #12]
8007472: 2203 movs r2, #3
8007474: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_out[0].total_length = len;
8007478: 68fb ldr r3, [r7, #12]
800747a: 687a ldr r2, [r7, #4]
800747c: f8c3 2158 str.w r2, [r3, #344] @ 0x158
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
pdev->ep_out[0].rem_length = 0U;
#else
pdev->ep_out[0].rem_length = len;
8007480: 68fb ldr r3, [r7, #12]
8007482: 687a ldr r2, [r7, #4]
8007484: f8c3 215c str.w r2, [r3, #348] @ 0x15c
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
/* Start the transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
8007488: 687b ldr r3, [r7, #4]
800748a: 68ba ldr r2, [r7, #8]
800748c: 2100 movs r1, #0
800748e: 68f8 ldr r0, [r7, #12]
8007490: f000 fd50 bl 8007f34 <USBD_LL_PrepareReceive>
return USBD_OK;
8007494: 2300 movs r3, #0
}
8007496: 4618 mov r0, r3
8007498: 3710 adds r7, #16
800749a: 46bd mov sp, r7
800749c: bd80 pop {r7, pc}
0800749e <USBD_CtlContinueRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
800749e: b580 push {r7, lr}
80074a0: b084 sub sp, #16
80074a2: af00 add r7, sp, #0
80074a4: 60f8 str r0, [r7, #12]
80074a6: 60b9 str r1, [r7, #8]
80074a8: 607a str r2, [r7, #4]
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
80074aa: 687b ldr r3, [r7, #4]
80074ac: 68ba ldr r2, [r7, #8]
80074ae: 2100 movs r1, #0
80074b0: 68f8 ldr r0, [r7, #12]
80074b2: f000 fd3f bl 8007f34 <USBD_LL_PrepareReceive>
return USBD_OK;
80074b6: 2300 movs r3, #0
}
80074b8: 4618 mov r0, r3
80074ba: 3710 adds r7, #16
80074bc: 46bd mov sp, r7
80074be: bd80 pop {r7, pc}
080074c0 <USBD_CtlSendStatus>:
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
80074c0: b580 push {r7, lr}
80074c2: b082 sub sp, #8
80074c4: af00 add r7, sp, #0
80074c6: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
80074c8: 687b ldr r3, [r7, #4]
80074ca: 2204 movs r2, #4
80074cc: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
80074d0: 2300 movs r3, #0
80074d2: 2200 movs r2, #0
80074d4: 2100 movs r1, #0
80074d6: 6878 ldr r0, [r7, #4]
80074d8: f000 fcf4 bl 8007ec4 <USBD_LL_Transmit>
return USBD_OK;
80074dc: 2300 movs r3, #0
}
80074de: 4618 mov r0, r3
80074e0: 3708 adds r7, #8
80074e2: 46bd mov sp, r7
80074e4: bd80 pop {r7, pc}
080074e6 <USBD_CtlReceiveStatus>:
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
80074e6: b580 push {r7, lr}
80074e8: b082 sub sp, #8
80074ea: af00 add r7, sp, #0
80074ec: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
80074ee: 687b ldr r3, [r7, #4]
80074f0: 2205 movs r2, #5
80074f2: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
80074f6: 2300 movs r3, #0
80074f8: 2200 movs r2, #0
80074fa: 2100 movs r1, #0
80074fc: 6878 ldr r0, [r7, #4]
80074fe: f000 fd19 bl 8007f34 <USBD_LL_PrepareReceive>
return USBD_OK;
8007502: 2300 movs r3, #0
}
8007504: 4618 mov r0, r3
8007506: 3708 adds r7, #8
8007508: 46bd mov sp, r7
800750a: bd80 pop {r7, pc}
0800750c <MX_USB_DEVICE_Init>:
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void MX_USB_DEVICE_Init(void)
{
800750c: b580 push {r7, lr}
800750e: af00 add r7, sp, #0
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
/* USER CODE END USB_DEVICE_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
8007510: 2200 movs r2, #0
8007512: 4912 ldr r1, [pc, #72] @ (800755c <MX_USB_DEVICE_Init+0x50>)
8007514: 4812 ldr r0, [pc, #72] @ (8007560 <MX_USB_DEVICE_Init+0x54>)
8007516: f7fe fccd bl 8005eb4 <USBD_Init>
800751a: 4603 mov r3, r0
800751c: 2b00 cmp r3, #0
800751e: d001 beq.n 8007524 <MX_USB_DEVICE_Init+0x18>
{
Error_Handler();
8007520: f7f8 ff96 bl 8000450 <Error_Handler>
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CUSTOM_HID) != USBD_OK)
8007524: 490f ldr r1, [pc, #60] @ (8007564 <MX_USB_DEVICE_Init+0x58>)
8007526: 480e ldr r0, [pc, #56] @ (8007560 <MX_USB_DEVICE_Init+0x54>)
8007528: f7fe fcf4 bl 8005f14 <USBD_RegisterClass>
800752c: 4603 mov r3, r0
800752e: 2b00 cmp r3, #0
8007530: d001 beq.n 8007536 <MX_USB_DEVICE_Init+0x2a>
{
Error_Handler();
8007532: f7f8 ff8d bl 8000450 <Error_Handler>
}
if (USBD_CUSTOM_HID_RegisterInterface(&hUsbDeviceFS, &USBD_CustomHID_fops_FS) != USBD_OK)
8007536: 490c ldr r1, [pc, #48] @ (8007568 <MX_USB_DEVICE_Init+0x5c>)
8007538: 4809 ldr r0, [pc, #36] @ (8007560 <MX_USB_DEVICE_Init+0x54>)
800753a: f7fe fca1 bl 8005e80 <USBD_CUSTOM_HID_RegisterInterface>
800753e: 4603 mov r3, r0
8007540: 2b00 cmp r3, #0
8007542: d001 beq.n 8007548 <MX_USB_DEVICE_Init+0x3c>
{
Error_Handler();
8007544: f7f8 ff84 bl 8000450 <Error_Handler>
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
8007548: 4805 ldr r0, [pc, #20] @ (8007560 <MX_USB_DEVICE_Init+0x54>)
800754a: f7fe fd19 bl 8005f80 <USBD_Start>
800754e: 4603 mov r3, r0
8007550: 2b00 cmp r3, #0
8007552: d001 beq.n 8007558 <MX_USB_DEVICE_Init+0x4c>
{
Error_Handler();
8007554: f7f8 ff7c bl 8000450 <Error_Handler>
}
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
/* USER CODE END USB_DEVICE_Init_PostTreatment */
}
8007558: bf00 nop
800755a: bd80 pop {r7, pc}
800755c: 200000cc .word 0x200000cc
8007560: 200001a4 .word 0x200001a4
8007564: 2000000c .word 0x2000000c
8007568: 200000bc .word 0x200000bc
0800756c <CUSTOM_HID_Init_FS>:
/**
* @brief Initializes the CUSTOM HID media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CUSTOM_HID_Init_FS(void)
{
800756c: b480 push {r7}
800756e: af00 add r7, sp, #0
/* USER CODE BEGIN 4 */
return (USBD_OK);
8007570: 2300 movs r3, #0
/* USER CODE END 4 */
}
8007572: 4618 mov r0, r3
8007574: 46bd mov sp, r7
8007576: f85d 7b04 ldr.w r7, [sp], #4
800757a: 4770 bx lr
0800757c <CUSTOM_HID_DeInit_FS>:
/**
* @brief DeInitializes the CUSTOM HID media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CUSTOM_HID_DeInit_FS(void)
{
800757c: b480 push {r7}
800757e: af00 add r7, sp, #0
/* USER CODE BEGIN 5 */
return (USBD_OK);
8007580: 2300 movs r3, #0
/* USER CODE END 5 */
}
8007582: 4618 mov r0, r3
8007584: 46bd mov sp, r7
8007586: f85d 7b04 ldr.w r7, [sp], #4
800758a: 4770 bx lr
0800758c <CUSTOM_HID_OutEvent_FS>:
* @param event_idx: Event index
* @param state: Event state
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CUSTOM_HID_OutEvent_FS(uint8_t event_idx, uint8_t state)
{
800758c: b580 push {r7, lr}
800758e: b082 sub sp, #8
8007590: af00 add r7, sp, #0
8007592: 4603 mov r3, r0
8007594: 460a mov r2, r1
8007596: 71fb strb r3, [r7, #7]
8007598: 4613 mov r3, r2
800759a: 71bb strb r3, [r7, #6]
/* USER CODE BEGIN 6 */
UNUSED(event_idx);
UNUSED(state);
/* Start next USB packet transfer once data processing is completed */
USBD_CUSTOM_HID_ReceivePacket(&hUsbDeviceFS);
800759c: 4803 ldr r0, [pc, #12] @ (80075ac <CUSTOM_HID_OutEvent_FS+0x20>)
800759e: f7fe fc0d bl 8005dbc <USBD_CUSTOM_HID_ReceivePacket>
return (USBD_OK);
80075a2: 2300 movs r3, #0
/* USER CODE END 6 */
}
80075a4: 4618 mov r0, r3
80075a6: 3708 adds r7, #8
80075a8: 46bd mov sp, r7
80075aa: bd80 pop {r7, pc}
80075ac: 200001a4 .word 0x200001a4
080075b0 <USBD_CUSTOM_HID_SendReport_FS>:
* @param len: The report length
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
int8_t USBD_CUSTOM_HID_SendReport_FS(uint8_t *report, uint16_t len)
{
80075b0: b580 push {r7, lr}
80075b2: b082 sub sp, #8
80075b4: af00 add r7, sp, #0
80075b6: 6078 str r0, [r7, #4]
80075b8: 460b mov r3, r1
80075ba: 807b strh r3, [r7, #2]
return USBD_CUSTOM_HID_SendReport(&hUsbDeviceFS, report, len);
80075bc: 887b ldrh r3, [r7, #2]
80075be: 461a mov r2, r3
80075c0: 6879 ldr r1, [r7, #4]
80075c2: 4804 ldr r0, [pc, #16] @ (80075d4 <USBD_CUSTOM_HID_SendReport_FS+0x24>)
80075c4: f7fe faee bl 8005ba4 <USBD_CUSTOM_HID_SendReport>
80075c8: 4603 mov r3, r0
80075ca: b25b sxtb r3, r3
}
80075cc: 4618 mov r0, r3
80075ce: 3708 adds r7, #8
80075d0: 46bd mov sp, r7
80075d2: bd80 pop {r7, pc}
80075d4: 200001a4 .word 0x200001a4
080075d8 <USBD_FS_DeviceDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80075d8: b480 push {r7}
80075da: b083 sub sp, #12
80075dc: af00 add r7, sp, #0
80075de: 4603 mov r3, r0
80075e0: 6039 str r1, [r7, #0]
80075e2: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc);
80075e4: 683b ldr r3, [r7, #0]
80075e6: 2212 movs r2, #18
80075e8: 801a strh r2, [r3, #0]
return USBD_FS_DeviceDesc;
80075ea: 4b03 ldr r3, [pc, #12] @ (80075f8 <USBD_FS_DeviceDescriptor+0x20>)
}
80075ec: 4618 mov r0, r3
80075ee: 370c adds r7, #12
80075f0: 46bd mov sp, r7
80075f2: f85d 7b04 ldr.w r7, [sp], #4
80075f6: 4770 bx lr
80075f8: 200000ec .word 0x200000ec
080075fc <USBD_FS_LangIDStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80075fc: b480 push {r7}
80075fe: b083 sub sp, #12
8007600: af00 add r7, sp, #0
8007602: 4603 mov r3, r0
8007604: 6039 str r1, [r7, #0]
8007606: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
8007608: 683b ldr r3, [r7, #0]
800760a: 2204 movs r2, #4
800760c: 801a strh r2, [r3, #0]
return USBD_LangIDDesc;
800760e: 4b03 ldr r3, [pc, #12] @ (800761c <USBD_FS_LangIDStrDescriptor+0x20>)
}
8007610: 4618 mov r0, r3
8007612: 370c adds r7, #12
8007614: 46bd mov sp, r7
8007616: f85d 7b04 ldr.w r7, [sp], #4
800761a: 4770 bx lr
800761c: 2000010c .word 0x2000010c
08007620 <USBD_FS_ProductStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8007620: b580 push {r7, lr}
8007622: b082 sub sp, #8
8007624: af00 add r7, sp, #0
8007626: 4603 mov r3, r0
8007628: 6039 str r1, [r7, #0]
800762a: 71fb strb r3, [r7, #7]
if(speed == 0)
800762c: 79fb ldrb r3, [r7, #7]
800762e: 2b00 cmp r3, #0
8007630: d105 bne.n 800763e <USBD_FS_ProductStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
8007632: 683a ldr r2, [r7, #0]
8007634: 4907 ldr r1, [pc, #28] @ (8007654 <USBD_FS_ProductStrDescriptor+0x34>)
8007636: 4808 ldr r0, [pc, #32] @ (8007658 <USBD_FS_ProductStrDescriptor+0x38>)
8007638: f7ff fe7c bl 8007334 <USBD_GetString>
800763c: e004 b.n 8007648 <USBD_FS_ProductStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800763e: 683a ldr r2, [r7, #0]
8007640: 4904 ldr r1, [pc, #16] @ (8007654 <USBD_FS_ProductStrDescriptor+0x34>)
8007642: 4805 ldr r0, [pc, #20] @ (8007658 <USBD_FS_ProductStrDescriptor+0x38>)
8007644: f7ff fe76 bl 8007334 <USBD_GetString>
}
return USBD_StrDesc;
8007648: 4b02 ldr r3, [pc, #8] @ (8007654 <USBD_FS_ProductStrDescriptor+0x34>)
}
800764a: 4618 mov r0, r3
800764c: 3708 adds r7, #8
800764e: 46bd mov sp, r7
8007650: bd80 pop {r7, pc}
8007652: bf00 nop
8007654: 20000480 .word 0x20000480
8007658: 080080ec .word 0x080080ec
0800765c <USBD_FS_ManufacturerStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800765c: b580 push {r7, lr}
800765e: b082 sub sp, #8
8007660: af00 add r7, sp, #0
8007662: 4603 mov r3, r0
8007664: 6039 str r1, [r7, #0]
8007666: 71fb strb r3, [r7, #7]
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
8007668: 683a ldr r2, [r7, #0]
800766a: 4904 ldr r1, [pc, #16] @ (800767c <USBD_FS_ManufacturerStrDescriptor+0x20>)
800766c: 4804 ldr r0, [pc, #16] @ (8007680 <USBD_FS_ManufacturerStrDescriptor+0x24>)
800766e: f7ff fe61 bl 8007334 <USBD_GetString>
return USBD_StrDesc;
8007672: 4b02 ldr r3, [pc, #8] @ (800767c <USBD_FS_ManufacturerStrDescriptor+0x20>)
}
8007674: 4618 mov r0, r3
8007676: 3708 adds r7, #8
8007678: 46bd mov sp, r7
800767a: bd80 pop {r7, pc}
800767c: 20000480 .word 0x20000480
8007680: 0800810c .word 0x0800810c
08007684 <USBD_FS_SerialStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8007684: b580 push {r7, lr}
8007686: b082 sub sp, #8
8007688: af00 add r7, sp, #0
800768a: 4603 mov r3, r0
800768c: 6039 str r1, [r7, #0]
800768e: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
8007690: 683b ldr r3, [r7, #0]
8007692: 221a movs r2, #26
8007694: 801a strh r2, [r3, #0]
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
8007696: f000 f855 bl 8007744 <Get_SerialNum>
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
/* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
800769a: 4b02 ldr r3, [pc, #8] @ (80076a4 <USBD_FS_SerialStrDescriptor+0x20>)
}
800769c: 4618 mov r0, r3
800769e: 3708 adds r7, #8
80076a0: 46bd mov sp, r7
80076a2: bd80 pop {r7, pc}
80076a4: 20000110 .word 0x20000110
080076a8 <USBD_FS_ConfigStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80076a8: b580 push {r7, lr}
80076aa: b082 sub sp, #8
80076ac: af00 add r7, sp, #0
80076ae: 4603 mov r3, r0
80076b0: 6039 str r1, [r7, #0]
80076b2: 71fb strb r3, [r7, #7]
if(speed == USBD_SPEED_HIGH)
80076b4: 79fb ldrb r3, [r7, #7]
80076b6: 2b00 cmp r3, #0
80076b8: d105 bne.n 80076c6 <USBD_FS_ConfigStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
80076ba: 683a ldr r2, [r7, #0]
80076bc: 4907 ldr r1, [pc, #28] @ (80076dc <USBD_FS_ConfigStrDescriptor+0x34>)
80076be: 4808 ldr r0, [pc, #32] @ (80076e0 <USBD_FS_ConfigStrDescriptor+0x38>)
80076c0: f7ff fe38 bl 8007334 <USBD_GetString>
80076c4: e004 b.n 80076d0 <USBD_FS_ConfigStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
80076c6: 683a ldr r2, [r7, #0]
80076c8: 4904 ldr r1, [pc, #16] @ (80076dc <USBD_FS_ConfigStrDescriptor+0x34>)
80076ca: 4805 ldr r0, [pc, #20] @ (80076e0 <USBD_FS_ConfigStrDescriptor+0x38>)
80076cc: f7ff fe32 bl 8007334 <USBD_GetString>
}
return USBD_StrDesc;
80076d0: 4b02 ldr r3, [pc, #8] @ (80076dc <USBD_FS_ConfigStrDescriptor+0x34>)
}
80076d2: 4618 mov r0, r3
80076d4: 3708 adds r7, #8
80076d6: 46bd mov sp, r7
80076d8: bd80 pop {r7, pc}
80076da: bf00 nop
80076dc: 20000480 .word 0x20000480
80076e0: 08008120 .word 0x08008120
080076e4 <USBD_FS_InterfaceStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80076e4: b580 push {r7, lr}
80076e6: b082 sub sp, #8
80076e8: af00 add r7, sp, #0
80076ea: 4603 mov r3, r0
80076ec: 6039 str r1, [r7, #0]
80076ee: 71fb strb r3, [r7, #7]
if(speed == 0)
80076f0: 79fb ldrb r3, [r7, #7]
80076f2: 2b00 cmp r3, #0
80076f4: d105 bne.n 8007702 <USBD_FS_InterfaceStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
80076f6: 683a ldr r2, [r7, #0]
80076f8: 4907 ldr r1, [pc, #28] @ (8007718 <USBD_FS_InterfaceStrDescriptor+0x34>)
80076fa: 4808 ldr r0, [pc, #32] @ (800771c <USBD_FS_InterfaceStrDescriptor+0x38>)
80076fc: f7ff fe1a bl 8007334 <USBD_GetString>
8007700: e004 b.n 800770c <USBD_FS_InterfaceStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
8007702: 683a ldr r2, [r7, #0]
8007704: 4904 ldr r1, [pc, #16] @ (8007718 <USBD_FS_InterfaceStrDescriptor+0x34>)
8007706: 4805 ldr r0, [pc, #20] @ (800771c <USBD_FS_InterfaceStrDescriptor+0x38>)
8007708: f7ff fe14 bl 8007334 <USBD_GetString>
}
return USBD_StrDesc;
800770c: 4b02 ldr r3, [pc, #8] @ (8007718 <USBD_FS_InterfaceStrDescriptor+0x34>)
}
800770e: 4618 mov r0, r3
8007710: 3708 adds r7, #8
8007712: 46bd mov sp, r7
8007714: bd80 pop {r7, pc}
8007716: bf00 nop
8007718: 20000480 .word 0x20000480
800771c: 08008134 .word 0x08008134
08007720 <USBD_FS_USR_BOSDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8007720: b480 push {r7}
8007722: b083 sub sp, #12
8007724: af00 add r7, sp, #0
8007726: 4603 mov r3, r0
8007728: 6039 str r1, [r7, #0]
800772a: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_BOSDesc);
800772c: 683b ldr r3, [r7, #0]
800772e: 220c movs r2, #12
8007730: 801a strh r2, [r3, #0]
return (uint8_t*)USBD_FS_BOSDesc;
8007732: 4b03 ldr r3, [pc, #12] @ (8007740 <USBD_FS_USR_BOSDescriptor+0x20>)
}
8007734: 4618 mov r0, r3
8007736: 370c adds r7, #12
8007738: 46bd mov sp, r7
800773a: f85d 7b04 ldr.w r7, [sp], #4
800773e: 4770 bx lr
8007740: 20000100 .word 0x20000100
08007744 <Get_SerialNum>:
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
8007744: b580 push {r7, lr}
8007746: b084 sub sp, #16
8007748: af00 add r7, sp, #0
uint32_t deviceserial0;
uint32_t deviceserial1;
uint32_t deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
800774a: 4b0f ldr r3, [pc, #60] @ (8007788 <Get_SerialNum+0x44>)
800774c: 681b ldr r3, [r3, #0]
800774e: 60fb str r3, [r7, #12]
deviceserial1 = *(uint32_t *) DEVICE_ID2;
8007750: 4b0e ldr r3, [pc, #56] @ (800778c <Get_SerialNum+0x48>)
8007752: 681b ldr r3, [r3, #0]
8007754: 60bb str r3, [r7, #8]
deviceserial2 = *(uint32_t *) DEVICE_ID3;
8007756: 4b0e ldr r3, [pc, #56] @ (8007790 <Get_SerialNum+0x4c>)
8007758: 681b ldr r3, [r3, #0]
800775a: 607b str r3, [r7, #4]
deviceserial0 += deviceserial2;
800775c: 68fa ldr r2, [r7, #12]
800775e: 687b ldr r3, [r7, #4]
8007760: 4413 add r3, r2
8007762: 60fb str r3, [r7, #12]
if (deviceserial0 != 0)
8007764: 68fb ldr r3, [r7, #12]
8007766: 2b00 cmp r3, #0
8007768: d009 beq.n 800777e <Get_SerialNum+0x3a>
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
800776a: 2208 movs r2, #8
800776c: 4909 ldr r1, [pc, #36] @ (8007794 <Get_SerialNum+0x50>)
800776e: 68f8 ldr r0, [r7, #12]
8007770: f000 f814 bl 800779c <IntToUnicode>
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
8007774: 2204 movs r2, #4
8007776: 4908 ldr r1, [pc, #32] @ (8007798 <Get_SerialNum+0x54>)
8007778: 68b8 ldr r0, [r7, #8]
800777a: f000 f80f bl 800779c <IntToUnicode>
}
}
800777e: bf00 nop
8007780: 3710 adds r7, #16
8007782: 46bd mov sp, r7
8007784: bd80 pop {r7, pc}
8007786: bf00 nop
8007788: 1fff7590 .word 0x1fff7590
800778c: 1fff7594 .word 0x1fff7594
8007790: 1fff7598 .word 0x1fff7598
8007794: 20000112 .word 0x20000112
8007798: 20000122 .word 0x20000122
0800779c <IntToUnicode>:
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
800779c: b480 push {r7}
800779e: b087 sub sp, #28
80077a0: af00 add r7, sp, #0
80077a2: 60f8 str r0, [r7, #12]
80077a4: 60b9 str r1, [r7, #8]
80077a6: 4613 mov r3, r2
80077a8: 71fb strb r3, [r7, #7]
uint8_t idx = 0;
80077aa: 2300 movs r3, #0
80077ac: 75fb strb r3, [r7, #23]
for (idx = 0; idx < len; idx++)
80077ae: 2300 movs r3, #0
80077b0: 75fb strb r3, [r7, #23]
80077b2: e027 b.n 8007804 <IntToUnicode+0x68>
{
if (((value >> 28)) < 0xA)
80077b4: 68fb ldr r3, [r7, #12]
80077b6: 0f1b lsrs r3, r3, #28
80077b8: 2b09 cmp r3, #9
80077ba: d80b bhi.n 80077d4 <IntToUnicode+0x38>
{
pbuf[2 * idx] = (value >> 28) + '0';
80077bc: 68fb ldr r3, [r7, #12]
80077be: 0f1b lsrs r3, r3, #28
80077c0: b2da uxtb r2, r3
80077c2: 7dfb ldrb r3, [r7, #23]
80077c4: 005b lsls r3, r3, #1
80077c6: 4619 mov r1, r3
80077c8: 68bb ldr r3, [r7, #8]
80077ca: 440b add r3, r1
80077cc: 3230 adds r2, #48 @ 0x30
80077ce: b2d2 uxtb r2, r2
80077d0: 701a strb r2, [r3, #0]
80077d2: e00a b.n 80077ea <IntToUnicode+0x4e>
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
80077d4: 68fb ldr r3, [r7, #12]
80077d6: 0f1b lsrs r3, r3, #28
80077d8: b2da uxtb r2, r3
80077da: 7dfb ldrb r3, [r7, #23]
80077dc: 005b lsls r3, r3, #1
80077de: 4619 mov r1, r3
80077e0: 68bb ldr r3, [r7, #8]
80077e2: 440b add r3, r1
80077e4: 3237 adds r2, #55 @ 0x37
80077e6: b2d2 uxtb r2, r2
80077e8: 701a strb r2, [r3, #0]
}
value = value << 4;
80077ea: 68fb ldr r3, [r7, #12]
80077ec: 011b lsls r3, r3, #4
80077ee: 60fb str r3, [r7, #12]
pbuf[2 * idx + 1] = 0;
80077f0: 7dfb ldrb r3, [r7, #23]
80077f2: 005b lsls r3, r3, #1
80077f4: 3301 adds r3, #1
80077f6: 68ba ldr r2, [r7, #8]
80077f8: 4413 add r3, r2
80077fa: 2200 movs r2, #0
80077fc: 701a strb r2, [r3, #0]
for (idx = 0; idx < len; idx++)
80077fe: 7dfb ldrb r3, [r7, #23]
8007800: 3301 adds r3, #1
8007802: 75fb strb r3, [r7, #23]
8007804: 7dfa ldrb r2, [r7, #23]
8007806: 79fb ldrb r3, [r7, #7]
8007808: 429a cmp r2, r3
800780a: d3d3 bcc.n 80077b4 <IntToUnicode+0x18>
}
}
800780c: bf00 nop
800780e: bf00 nop
8007810: 371c adds r7, #28
8007812: 46bd mov sp, r7
8007814: f85d 7b04 ldr.w r7, [sp], #4
8007818: 4770 bx lr
...
0800781c <HAL_PCD_MspInit>:
LL Driver Callbacks (PCD -> USB Device Library)
*******************************************************************************/
/* MSP Init */
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
800781c: b580 push {r7, lr}
800781e: b0ac sub sp, #176 @ 0xb0
8007820: af00 add r7, sp, #0
8007822: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8007824: f107 039c add.w r3, r7, #156 @ 0x9c
8007828: 2200 movs r2, #0
800782a: 601a str r2, [r3, #0]
800782c: 605a str r2, [r3, #4]
800782e: 609a str r2, [r3, #8]
8007830: 60da str r2, [r3, #12]
8007832: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8007834: f107 0314 add.w r3, r7, #20
8007838: 2288 movs r2, #136 @ 0x88
800783a: 2100 movs r1, #0
800783c: 4618 mov r0, r3
800783e: f000 fc1d bl 800807c <memset>
if(pcdHandle->Instance==USB_OTG_FS)
8007842: 687b ldr r3, [r7, #4]
8007844: 681b ldr r3, [r3, #0]
8007846: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
800784a: d173 bne.n 8007934 <HAL_PCD_MspInit+0x118>
/* USER CODE END USB_OTG_FS_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
800784c: f44f 5300 mov.w r3, #8192 @ 0x2000
8007850: 617b str r3, [r7, #20]
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
8007852: f04f 6380 mov.w r3, #67108864 @ 0x4000000
8007856: f8c7 3080 str.w r3, [r7, #128] @ 0x80
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
800785a: 2301 movs r3, #1
800785c: 61bb str r3, [r7, #24]
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
800785e: 2301 movs r3, #1
8007860: 61fb str r3, [r7, #28]
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
8007862: 2318 movs r3, #24
8007864: 623b str r3, [r7, #32]
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
8007866: 2307 movs r3, #7
8007868: 627b str r3, [r7, #36] @ 0x24
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
800786a: 2302 movs r3, #2
800786c: 62bb str r3, [r7, #40] @ 0x28
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
800786e: 2302 movs r3, #2
8007870: 62fb str r3, [r7, #44] @ 0x2c
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
8007872: f44f 1380 mov.w r3, #1048576 @ 0x100000
8007876: 633b str r3, [r7, #48] @ 0x30
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8007878: f107 0314 add.w r3, r7, #20
800787c: 4618 mov r0, r3
800787e: f7fc f823 bl 80038c8 <HAL_RCCEx_PeriphCLKConfig>
8007882: 4603 mov r3, r0
8007884: 2b00 cmp r3, #0
8007886: d001 beq.n 800788c <HAL_PCD_MspInit+0x70>
{
Error_Handler();
8007888: f7f8 fde2 bl 8000450 <Error_Handler>
}
__HAL_RCC_GPIOA_CLK_ENABLE();
800788c: 4b2b ldr r3, [pc, #172] @ (800793c <HAL_PCD_MspInit+0x120>)
800788e: 6cdb ldr r3, [r3, #76] @ 0x4c
8007890: 4a2a ldr r2, [pc, #168] @ (800793c <HAL_PCD_MspInit+0x120>)
8007892: f043 0301 orr.w r3, r3, #1
8007896: 64d3 str r3, [r2, #76] @ 0x4c
8007898: 4b28 ldr r3, [pc, #160] @ (800793c <HAL_PCD_MspInit+0x120>)
800789a: 6cdb ldr r3, [r3, #76] @ 0x4c
800789c: f003 0301 and.w r3, r3, #1
80078a0: 613b str r3, [r7, #16]
80078a2: 693b ldr r3, [r7, #16]
/**USB_OTG_FS GPIO Configuration
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
80078a4: f44f 53c0 mov.w r3, #6144 @ 0x1800
80078a8: f8c7 309c str.w r3, [r7, #156] @ 0x9c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80078ac: 2302 movs r3, #2
80078ae: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
GPIO_InitStruct.Pull = GPIO_NOPULL;
80078b2: 2300 movs r3, #0
80078b4: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80078b8: 2303 movs r3, #3
80078ba: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
80078be: 230a movs r3, #10
80078c0: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80078c4: f107 039c add.w r3, r7, #156 @ 0x9c
80078c8: 4619 mov r1, r3
80078ca: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80078ce: f7f9 f867 bl 80009a0 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
80078d2: 4b1a ldr r3, [pc, #104] @ (800793c <HAL_PCD_MspInit+0x120>)
80078d4: 6cdb ldr r3, [r3, #76] @ 0x4c
80078d6: 4a19 ldr r2, [pc, #100] @ (800793c <HAL_PCD_MspInit+0x120>)
80078d8: f443 5380 orr.w r3, r3, #4096 @ 0x1000
80078dc: 64d3 str r3, [r2, #76] @ 0x4c
80078de: 4b17 ldr r3, [pc, #92] @ (800793c <HAL_PCD_MspInit+0x120>)
80078e0: 6cdb ldr r3, [r3, #76] @ 0x4c
80078e2: f403 5380 and.w r3, r3, #4096 @ 0x1000
80078e6: 60fb str r3, [r7, #12]
80078e8: 68fb ldr r3, [r7, #12]
/* Enable VDDUSB */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80078ea: 4b14 ldr r3, [pc, #80] @ (800793c <HAL_PCD_MspInit+0x120>)
80078ec: 6d9b ldr r3, [r3, #88] @ 0x58
80078ee: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80078f2: 2b00 cmp r3, #0
80078f4: d114 bne.n 8007920 <HAL_PCD_MspInit+0x104>
{
__HAL_RCC_PWR_CLK_ENABLE();
80078f6: 4b11 ldr r3, [pc, #68] @ (800793c <HAL_PCD_MspInit+0x120>)
80078f8: 6d9b ldr r3, [r3, #88] @ 0x58
80078fa: 4a10 ldr r2, [pc, #64] @ (800793c <HAL_PCD_MspInit+0x120>)
80078fc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8007900: 6593 str r3, [r2, #88] @ 0x58
8007902: 4b0e ldr r3, [pc, #56] @ (800793c <HAL_PCD_MspInit+0x120>)
8007904: 6d9b ldr r3, [r3, #88] @ 0x58
8007906: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800790a: 60bb str r3, [r7, #8]
800790c: 68bb ldr r3, [r7, #8]
HAL_PWREx_EnableVddUSB();
800790e: f7fb f9f7 bl 8002d00 <HAL_PWREx_EnableVddUSB>
__HAL_RCC_PWR_CLK_DISABLE();
8007912: 4b0a ldr r3, [pc, #40] @ (800793c <HAL_PCD_MspInit+0x120>)
8007914: 6d9b ldr r3, [r3, #88] @ 0x58
8007916: 4a09 ldr r2, [pc, #36] @ (800793c <HAL_PCD_MspInit+0x120>)
8007918: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800791c: 6593 str r3, [r2, #88] @ 0x58
800791e: e001 b.n 8007924 <HAL_PCD_MspInit+0x108>
}
else
{
HAL_PWREx_EnableVddUSB();
8007920: f7fb f9ee bl 8002d00 <HAL_PWREx_EnableVddUSB>
}
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
8007924: 2200 movs r2, #0
8007926: 2100 movs r1, #0
8007928: 2043 movs r0, #67 @ 0x43
800792a: f7f9 f802 bl 8000932 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
800792e: 2043 movs r0, #67 @ 0x43
8007930: f7f9 f81b bl 800096a <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
8007934: bf00 nop
8007936: 37b0 adds r7, #176 @ 0xb0
8007938: 46bd mov sp, r7
800793a: bd80 pop {r7, pc}
800793c: 40021000 .word 0x40021000
08007940 <HAL_PCD_SetupStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007940: b580 push {r7, lr}
8007942: b082 sub sp, #8
8007944: af00 add r7, sp, #0
8007946: 6078 str r0, [r7, #4]
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
8007948: 687b ldr r3, [r7, #4]
800794a: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0
800794e: 687b ldr r3, [r7, #4]
8007950: f203 439c addw r3, r3, #1180 @ 0x49c
8007954: 4619 mov r1, r3
8007956: 4610 mov r0, r2
8007958: f7fe fb5f bl 800601a <USBD_LL_SetupStage>
}
800795c: bf00 nop
800795e: 3708 adds r7, #8
8007960: 46bd mov sp, r7
8007962: bd80 pop {r7, pc}
08007964 <HAL_PCD_DataOutStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007964: b580 push {r7, lr}
8007966: b082 sub sp, #8
8007968: af00 add r7, sp, #0
800796a: 6078 str r0, [r7, #4]
800796c: 460b mov r3, r1
800796e: 70fb strb r3, [r7, #3]
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
8007970: 687b ldr r3, [r7, #4]
8007972: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
8007976: 78fa ldrb r2, [r7, #3]
8007978: 6879 ldr r1, [r7, #4]
800797a: 4613 mov r3, r2
800797c: 00db lsls r3, r3, #3
800797e: 4413 add r3, r2
8007980: 009b lsls r3, r3, #2
8007982: 440b add r3, r1
8007984: f503 7318 add.w r3, r3, #608 @ 0x260
8007988: 681a ldr r2, [r3, #0]
800798a: 78fb ldrb r3, [r7, #3]
800798c: 4619 mov r1, r3
800798e: f7fe fb99 bl 80060c4 <USBD_LL_DataOutStage>
}
8007992: bf00 nop
8007994: 3708 adds r7, #8
8007996: 46bd mov sp, r7
8007998: bd80 pop {r7, pc}
0800799a <HAL_PCD_DataInStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800799a: b580 push {r7, lr}
800799c: b082 sub sp, #8
800799e: af00 add r7, sp, #0
80079a0: 6078 str r0, [r7, #4]
80079a2: 460b mov r3, r1
80079a4: 70fb strb r3, [r7, #3]
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
80079a6: 687b ldr r3, [r7, #4]
80079a8: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
80079ac: 78fa ldrb r2, [r7, #3]
80079ae: 6879 ldr r1, [r7, #4]
80079b0: 4613 mov r3, r2
80079b2: 00db lsls r3, r3, #3
80079b4: 4413 add r3, r2
80079b6: 009b lsls r3, r3, #2
80079b8: 440b add r3, r1
80079ba: 3320 adds r3, #32
80079bc: 681a ldr r2, [r3, #0]
80079be: 78fb ldrb r3, [r7, #3]
80079c0: 4619 mov r1, r3
80079c2: f7fe fc32 bl 800622a <USBD_LL_DataInStage>
}
80079c6: bf00 nop
80079c8: 3708 adds r7, #8
80079ca: 46bd mov sp, r7
80079cc: bd80 pop {r7, pc}
080079ce <HAL_PCD_SOFCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
80079ce: b580 push {r7, lr}
80079d0: b082 sub sp, #8
80079d2: af00 add r7, sp, #0
80079d4: 6078 str r0, [r7, #4]
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
80079d6: 687b ldr r3, [r7, #4]
80079d8: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
80079dc: 4618 mov r0, r3
80079de: f7fe fd6c bl 80064ba <USBD_LL_SOF>
}
80079e2: bf00 nop
80079e4: 3708 adds r7, #8
80079e6: 46bd mov sp, r7
80079e8: bd80 pop {r7, pc}
080079ea <HAL_PCD_ResetCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
80079ea: b580 push {r7, lr}
80079ec: b084 sub sp, #16
80079ee: af00 add r7, sp, #0
80079f0: 6078 str r0, [r7, #4]
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
80079f2: 2301 movs r3, #1
80079f4: 73fb strb r3, [r7, #15]
if ( hpcd->Init.speed != PCD_SPEED_FULL)
80079f6: 687b ldr r3, [r7, #4]
80079f8: 79db ldrb r3, [r3, #7]
80079fa: 2b02 cmp r3, #2
80079fc: d001 beq.n 8007a02 <HAL_PCD_ResetCallback+0x18>
{
Error_Handler();
80079fe: f7f8 fd27 bl 8000450 <Error_Handler>
}
/* Set Speed. */
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
8007a02: 687b ldr r3, [r7, #4]
8007a04: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007a08: 7bfa ldrb r2, [r7, #15]
8007a0a: 4611 mov r1, r2
8007a0c: 4618 mov r0, r3
8007a0e: f7fe fd10 bl 8006432 <USBD_LL_SetSpeed>
/* Reset Device. */
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
8007a12: 687b ldr r3, [r7, #4]
8007a14: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007a18: 4618 mov r0, r3
8007a1a: f7fe fcb8 bl 800638e <USBD_LL_Reset>
}
8007a1e: bf00 nop
8007a20: 3710 adds r7, #16
8007a22: 46bd mov sp, r7
8007a24: bd80 pop {r7, pc}
...
08007a28 <HAL_PCD_SuspendCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007a28: b580 push {r7, lr}
8007a2a: b082 sub sp, #8
8007a2c: af00 add r7, sp, #0
8007a2e: 6078 str r0, [r7, #4]
__HAL_PCD_GATE_PHYCLOCK(hpcd);
8007a30: 687b ldr r3, [r7, #4]
8007a32: 681b ldr r3, [r3, #0]
8007a34: f503 6360 add.w r3, r3, #3584 @ 0xe00
8007a38: 681b ldr r3, [r3, #0]
8007a3a: 687a ldr r2, [r7, #4]
8007a3c: 6812 ldr r2, [r2, #0]
8007a3e: f502 6260 add.w r2, r2, #3584 @ 0xe00
8007a42: f043 0301 orr.w r3, r3, #1
8007a46: 6013 str r3, [r2, #0]
/* Inform USB library that core enters in suspend Mode. */
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
8007a48: 687b ldr r3, [r7, #4]
8007a4a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007a4e: 4618 mov r0, r3
8007a50: f7fe fcff bl 8006452 <USBD_LL_Suspend>
/* Enter in STOP mode. */
/* USER CODE BEGIN 2 */
if (hpcd->Init.low_power_enable)
8007a54: 687b ldr r3, [r7, #4]
8007a56: 7adb ldrb r3, [r3, #11]
8007a58: 2b00 cmp r3, #0
8007a5a: d005 beq.n 8007a68 <HAL_PCD_SuspendCallback+0x40>
{
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
8007a5c: 4b04 ldr r3, [pc, #16] @ (8007a70 <HAL_PCD_SuspendCallback+0x48>)
8007a5e: 691b ldr r3, [r3, #16]
8007a60: 4a03 ldr r2, [pc, #12] @ (8007a70 <HAL_PCD_SuspendCallback+0x48>)
8007a62: f043 0306 orr.w r3, r3, #6
8007a66: 6113 str r3, [r2, #16]
}
/* USER CODE END 2 */
}
8007a68: bf00 nop
8007a6a: 3708 adds r7, #8
8007a6c: 46bd mov sp, r7
8007a6e: bd80 pop {r7, pc}
8007a70: e000ed00 .word 0xe000ed00
08007a74 <HAL_PCD_ResumeCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007a74: b580 push {r7, lr}
8007a76: b082 sub sp, #8
8007a78: af00 add r7, sp, #0
8007a7a: 6078 str r0, [r7, #4]
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
8007a7c: 687b ldr r3, [r7, #4]
8007a7e: 681b ldr r3, [r3, #0]
8007a80: f503 6360 add.w r3, r3, #3584 @ 0xe00
8007a84: 681b ldr r3, [r3, #0]
8007a86: 687a ldr r2, [r7, #4]
8007a88: 6812 ldr r2, [r2, #0]
8007a8a: f502 6260 add.w r2, r2, #3584 @ 0xe00
8007a8e: f023 0301 bic.w r3, r3, #1
8007a92: 6013 str r3, [r2, #0]
/* USER CODE BEGIN 3 */
if (hpcd->Init.low_power_enable)
8007a94: 687b ldr r3, [r7, #4]
8007a96: 7adb ldrb r3, [r3, #11]
8007a98: 2b00 cmp r3, #0
8007a9a: d007 beq.n 8007aac <HAL_PCD_ResumeCallback+0x38>
{
/* Reset SLEEPDEEP bit of Cortex System Control Register. */
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
8007a9c: 4b08 ldr r3, [pc, #32] @ (8007ac0 <HAL_PCD_ResumeCallback+0x4c>)
8007a9e: 691b ldr r3, [r3, #16]
8007aa0: 4a07 ldr r2, [pc, #28] @ (8007ac0 <HAL_PCD_ResumeCallback+0x4c>)
8007aa2: f023 0306 bic.w r3, r3, #6
8007aa6: 6113 str r3, [r2, #16]
SystemClockConfig_Resume();
8007aa8: f000 fae2 bl 8008070 <SystemClockConfig_Resume>
}
/* USER CODE END 3 */
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
8007aac: 687b ldr r3, [r7, #4]
8007aae: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007ab2: 4618 mov r0, r3
8007ab4: f7fe fce9 bl 800648a <USBD_LL_Resume>
}
8007ab8: bf00 nop
8007aba: 3708 adds r7, #8
8007abc: 46bd mov sp, r7
8007abe: bd80 pop {r7, pc}
8007ac0: e000ed00 .word 0xe000ed00
08007ac4 <HAL_PCD_ISOOUTIncompleteCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007ac4: b580 push {r7, lr}
8007ac6: b082 sub sp, #8
8007ac8: af00 add r7, sp, #0
8007aca: 6078 str r0, [r7, #4]
8007acc: 460b mov r3, r1
8007ace: 70fb strb r3, [r7, #3]
USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
8007ad0: 687b ldr r3, [r7, #4]
8007ad2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007ad6: 78fa ldrb r2, [r7, #3]
8007ad8: 4611 mov r1, r2
8007ada: 4618 mov r0, r3
8007adc: f7fe fd3f bl 800655e <USBD_LL_IsoOUTIncomplete>
}
8007ae0: bf00 nop
8007ae2: 3708 adds r7, #8
8007ae4: 46bd mov sp, r7
8007ae6: bd80 pop {r7, pc}
08007ae8 <HAL_PCD_ISOINIncompleteCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007ae8: b580 push {r7, lr}
8007aea: b082 sub sp, #8
8007aec: af00 add r7, sp, #0
8007aee: 6078 str r0, [r7, #4]
8007af0: 460b mov r3, r1
8007af2: 70fb strb r3, [r7, #3]
USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
8007af4: 687b ldr r3, [r7, #4]
8007af6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007afa: 78fa ldrb r2, [r7, #3]
8007afc: 4611 mov r1, r2
8007afe: 4618 mov r0, r3
8007b00: f7fe fcfb bl 80064fa <USBD_LL_IsoINIncomplete>
}
8007b04: bf00 nop
8007b06: 3708 adds r7, #8
8007b08: 46bd mov sp, r7
8007b0a: bd80 pop {r7, pc}
08007b0c <HAL_PCD_ConnectCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007b0c: b580 push {r7, lr}
8007b0e: b082 sub sp, #8
8007b10: af00 add r7, sp, #0
8007b12: 6078 str r0, [r7, #4]
USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
8007b14: 687b ldr r3, [r7, #4]
8007b16: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007b1a: 4618 mov r0, r3
8007b1c: f7fe fd51 bl 80065c2 <USBD_LL_DevConnected>
}
8007b20: bf00 nop
8007b22: 3708 adds r7, #8
8007b24: 46bd mov sp, r7
8007b26: bd80 pop {r7, pc}
08007b28 <HAL_PCD_DisconnectCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007b28: b580 push {r7, lr}
8007b2a: b082 sub sp, #8
8007b2c: af00 add r7, sp, #0
8007b2e: 6078 str r0, [r7, #4]
USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
8007b30: 687b ldr r3, [r7, #4]
8007b32: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007b36: 4618 mov r0, r3
8007b38: f7fe fd4e bl 80065d8 <USBD_LL_DevDisconnected>
}
8007b3c: bf00 nop
8007b3e: 3708 adds r7, #8
8007b40: 46bd mov sp, r7
8007b42: bd80 pop {r7, pc}
08007b44 <USBD_LL_Init>:
* @brief Initializes the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
{
8007b44: b580 push {r7, lr}
8007b46: b082 sub sp, #8
8007b48: af00 add r7, sp, #0
8007b4a: 6078 str r0, [r7, #4]
/* Init USB Ip. */
if (pdev->id == DEVICE_FS) {
8007b4c: 687b ldr r3, [r7, #4]
8007b4e: 781b ldrb r3, [r3, #0]
8007b50: 2b00 cmp r3, #0
8007b52: d13c bne.n 8007bce <USBD_LL_Init+0x8a>
/* Enable USB power on Pwrctrl CR2 register. */
/* Link the driver to the stack. */
hpcd_USB_OTG_FS.pData = pdev;
8007b54: 4a20 ldr r2, [pc, #128] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b56: 687b ldr r3, [r7, #4]
8007b58: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0
pdev->pData = &hpcd_USB_OTG_FS;
8007b5c: 687b ldr r3, [r7, #4]
8007b5e: 4a1e ldr r2, [pc, #120] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b60: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
8007b64: 4b1c ldr r3, [pc, #112] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b66: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
8007b6a: 601a str r2, [r3, #0]
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
8007b6c: 4b1a ldr r3, [pc, #104] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b6e: 2206 movs r2, #6
8007b70: 711a strb r2, [r3, #4]
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
8007b72: 4b19 ldr r3, [pc, #100] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b74: 2202 movs r2, #2
8007b76: 71da strb r2, [r3, #7]
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
8007b78: 4b17 ldr r3, [pc, #92] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b7a: 2202 movs r2, #2
8007b7c: 725a strb r2, [r3, #9]
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
8007b7e: 4b16 ldr r3, [pc, #88] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b80: 2200 movs r2, #0
8007b82: 729a strb r2, [r3, #10]
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
8007b84: 4b14 ldr r3, [pc, #80] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b86: 2200 movs r2, #0
8007b88: 72da strb r2, [r3, #11]
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
8007b8a: 4b13 ldr r3, [pc, #76] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b8c: 2200 movs r2, #0
8007b8e: 731a strb r2, [r3, #12]
hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
8007b90: 4b11 ldr r3, [pc, #68] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b92: 2200 movs r2, #0
8007b94: 735a strb r2, [r3, #13]
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
8007b96: 4b10 ldr r3, [pc, #64] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b98: 2200 movs r2, #0
8007b9a: 73da strb r2, [r3, #15]
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
8007b9c: 4b0e ldr r3, [pc, #56] @ (8007bd8 <USBD_LL_Init+0x94>)
8007b9e: 2200 movs r2, #0
8007ba0: 739a strb r2, [r3, #14]
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
8007ba2: 480d ldr r0, [pc, #52] @ (8007bd8 <USBD_LL_Init+0x94>)
8007ba4: f7f9 fec9 bl 800193a <HAL_PCD_Init>
8007ba8: 4603 mov r3, r0
8007baa: 2b00 cmp r3, #0
8007bac: d001 beq.n 8007bb2 <USBD_LL_Init+0x6e>
{
Error_Handler( );
8007bae: f7f8 fc4f bl 8000450 <Error_Handler>
HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
8007bb2: 2180 movs r1, #128 @ 0x80
8007bb4: 4808 ldr r0, [pc, #32] @ (8007bd8 <USBD_LL_Init+0x94>)
8007bb6: f7fb f80a bl 8002bce <HAL_PCDEx_SetRxFiFo>
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
8007bba: 2240 movs r2, #64 @ 0x40
8007bbc: 2100 movs r1, #0
8007bbe: 4806 ldr r0, [pc, #24] @ (8007bd8 <USBD_LL_Init+0x94>)
8007bc0: f7fa ffbe bl 8002b40 <HAL_PCDEx_SetTxFiFo>
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
8007bc4: 2280 movs r2, #128 @ 0x80
8007bc6: 2101 movs r1, #1
8007bc8: 4803 ldr r0, [pc, #12] @ (8007bd8 <USBD_LL_Init+0x94>)
8007bca: f7fa ffb9 bl 8002b40 <HAL_PCDEx_SetTxFiFo>
}
return USBD_OK;
8007bce: 2300 movs r3, #0
}
8007bd0: 4618 mov r0, r3
8007bd2: 3708 adds r7, #8
8007bd4: 46bd mov sp, r7
8007bd6: bd80 pop {r7, pc}
8007bd8: 20000680 .word 0x20000680
08007bdc <USBD_LL_Start>:
* @brief Starts the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
8007bdc: b580 push {r7, lr}
8007bde: b084 sub sp, #16
8007be0: af00 add r7, sp, #0
8007be2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
8007be4: 2300 movs r3, #0
8007be6: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
8007be8: 2300 movs r3, #0
8007bea: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_Start(pdev->pData);
8007bec: 687b ldr r3, [r7, #4]
8007bee: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8007bf2: 4618 mov r0, r3
8007bf4: f7f9 ffb0 bl 8001b58 <HAL_PCD_Start>
8007bf8: 4603 mov r3, r0
8007bfa: 73bb strb r3, [r7, #14]
switch (hal_status) {
8007bfc: 7bbb ldrb r3, [r7, #14]
8007bfe: 2b03 cmp r3, #3
8007c00: d816 bhi.n 8007c30 <USBD_LL_Start+0x54>
8007c02: a201 add r2, pc, #4 @ (adr r2, 8007c08 <USBD_LL_Start+0x2c>)
8007c04: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007c08: 08007c19 .word 0x08007c19
8007c0c: 08007c1f .word 0x08007c1f
8007c10: 08007c25 .word 0x08007c25
8007c14: 08007c2b .word 0x08007c2b
case HAL_OK :
usb_status = USBD_OK;
8007c18: 2300 movs r3, #0
8007c1a: 73fb strb r3, [r7, #15]
break;
8007c1c: e00b b.n 8007c36 <USBD_LL_Start+0x5a>
case HAL_ERROR :
usb_status = USBD_FAIL;
8007c1e: 2303 movs r3, #3
8007c20: 73fb strb r3, [r7, #15]
break;
8007c22: e008 b.n 8007c36 <USBD_LL_Start+0x5a>
case HAL_BUSY :
usb_status = USBD_BUSY;
8007c24: 2301 movs r3, #1
8007c26: 73fb strb r3, [r7, #15]
break;
8007c28: e005 b.n 8007c36 <USBD_LL_Start+0x5a>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
8007c2a: 2303 movs r3, #3
8007c2c: 73fb strb r3, [r7, #15]
break;
8007c2e: e002 b.n 8007c36 <USBD_LL_Start+0x5a>
default :
usb_status = USBD_FAIL;
8007c30: 2303 movs r3, #3
8007c32: 73fb strb r3, [r7, #15]
break;
8007c34: bf00 nop
}
return usb_status;
8007c36: 7bfb ldrb r3, [r7, #15]
}
8007c38: 4618 mov r0, r3
8007c3a: 3710 adds r7, #16
8007c3c: 46bd mov sp, r7
8007c3e: bd80 pop {r7, pc}
08007c40 <USBD_LL_OpenEP>:
* @param ep_type: Endpoint type
* @param ep_mps: Endpoint max packet size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
{
8007c40: b580 push {r7, lr}
8007c42: b084 sub sp, #16
8007c44: af00 add r7, sp, #0
8007c46: 6078 str r0, [r7, #4]
8007c48: 4608 mov r0, r1
8007c4a: 4611 mov r1, r2
8007c4c: 461a mov r2, r3
8007c4e: 4603 mov r3, r0
8007c50: 70fb strb r3, [r7, #3]
8007c52: 460b mov r3, r1
8007c54: 70bb strb r3, [r7, #2]
8007c56: 4613 mov r3, r2
8007c58: 803b strh r3, [r7, #0]
HAL_StatusTypeDef hal_status = HAL_OK;
8007c5a: 2300 movs r3, #0
8007c5c: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
8007c5e: 2300 movs r3, #0
8007c60: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
8007c62: 687b ldr r3, [r7, #4]
8007c64: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
8007c68: 78bb ldrb r3, [r7, #2]
8007c6a: 883a ldrh r2, [r7, #0]
8007c6c: 78f9 ldrb r1, [r7, #3]
8007c6e: f7fa fc5c bl 800252a <HAL_PCD_EP_Open>
8007c72: 4603 mov r3, r0
8007c74: 73bb strb r3, [r7, #14]
switch (hal_status) {
8007c76: 7bbb ldrb r3, [r7, #14]
8007c78: 2b03 cmp r3, #3
8007c7a: d817 bhi.n 8007cac <USBD_LL_OpenEP+0x6c>
8007c7c: a201 add r2, pc, #4 @ (adr r2, 8007c84 <USBD_LL_OpenEP+0x44>)
8007c7e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007c82: bf00 nop
8007c84: 08007c95 .word 0x08007c95
8007c88: 08007c9b .word 0x08007c9b
8007c8c: 08007ca1 .word 0x08007ca1
8007c90: 08007ca7 .word 0x08007ca7
case HAL_OK :
usb_status = USBD_OK;
8007c94: 2300 movs r3, #0
8007c96: 73fb strb r3, [r7, #15]
break;
8007c98: e00b b.n 8007cb2 <USBD_LL_OpenEP+0x72>
case HAL_ERROR :
usb_status = USBD_FAIL;
8007c9a: 2303 movs r3, #3
8007c9c: 73fb strb r3, [r7, #15]
break;
8007c9e: e008 b.n 8007cb2 <USBD_LL_OpenEP+0x72>
case HAL_BUSY :
usb_status = USBD_BUSY;
8007ca0: 2301 movs r3, #1
8007ca2: 73fb strb r3, [r7, #15]
break;
8007ca4: e005 b.n 8007cb2 <USBD_LL_OpenEP+0x72>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
8007ca6: 2303 movs r3, #3
8007ca8: 73fb strb r3, [r7, #15]
break;
8007caa: e002 b.n 8007cb2 <USBD_LL_OpenEP+0x72>
default :
usb_status = USBD_FAIL;
8007cac: 2303 movs r3, #3
8007cae: 73fb strb r3, [r7, #15]
break;
8007cb0: bf00 nop
}
return usb_status;
8007cb2: 7bfb ldrb r3, [r7, #15]
}
8007cb4: 4618 mov r0, r3
8007cb6: 3710 adds r7, #16
8007cb8: 46bd mov sp, r7
8007cba: bd80 pop {r7, pc}
08007cbc <USBD_LL_CloseEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8007cbc: b580 push {r7, lr}
8007cbe: b084 sub sp, #16
8007cc0: af00 add r7, sp, #0
8007cc2: 6078 str r0, [r7, #4]
8007cc4: 460b mov r3, r1
8007cc6: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8007cc8: 2300 movs r3, #0
8007cca: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
8007ccc: 2300 movs r3, #0
8007cce: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
8007cd0: 687b ldr r3, [r7, #4]
8007cd2: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8007cd6: 78fa ldrb r2, [r7, #3]
8007cd8: 4611 mov r1, r2
8007cda: 4618 mov r0, r3
8007cdc: f7fa fc8f bl 80025fe <HAL_PCD_EP_Close>
8007ce0: 4603 mov r3, r0
8007ce2: 73bb strb r3, [r7, #14]
switch (hal_status) {
8007ce4: 7bbb ldrb r3, [r7, #14]
8007ce6: 2b03 cmp r3, #3
8007ce8: d816 bhi.n 8007d18 <USBD_LL_CloseEP+0x5c>
8007cea: a201 add r2, pc, #4 @ (adr r2, 8007cf0 <USBD_LL_CloseEP+0x34>)
8007cec: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007cf0: 08007d01 .word 0x08007d01
8007cf4: 08007d07 .word 0x08007d07
8007cf8: 08007d0d .word 0x08007d0d
8007cfc: 08007d13 .word 0x08007d13
case HAL_OK :
usb_status = USBD_OK;
8007d00: 2300 movs r3, #0
8007d02: 73fb strb r3, [r7, #15]
break;
8007d04: e00b b.n 8007d1e <USBD_LL_CloseEP+0x62>
case HAL_ERROR :
usb_status = USBD_FAIL;
8007d06: 2303 movs r3, #3
8007d08: 73fb strb r3, [r7, #15]
break;
8007d0a: e008 b.n 8007d1e <USBD_LL_CloseEP+0x62>
case HAL_BUSY :
usb_status = USBD_BUSY;
8007d0c: 2301 movs r3, #1
8007d0e: 73fb strb r3, [r7, #15]
break;
8007d10: e005 b.n 8007d1e <USBD_LL_CloseEP+0x62>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
8007d12: 2303 movs r3, #3
8007d14: 73fb strb r3, [r7, #15]
break;
8007d16: e002 b.n 8007d1e <USBD_LL_CloseEP+0x62>
default :
usb_status = USBD_FAIL;
8007d18: 2303 movs r3, #3
8007d1a: 73fb strb r3, [r7, #15]
break;
8007d1c: bf00 nop
}
return usb_status;
8007d1e: 7bfb ldrb r3, [r7, #15]
}
8007d20: 4618 mov r0, r3
8007d22: 3710 adds r7, #16
8007d24: 46bd mov sp, r7
8007d26: bd80 pop {r7, pc}
08007d28 <USBD_LL_StallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8007d28: b580 push {r7, lr}
8007d2a: b084 sub sp, #16
8007d2c: af00 add r7, sp, #0
8007d2e: 6078 str r0, [r7, #4]
8007d30: 460b mov r3, r1
8007d32: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8007d34: 2300 movs r3, #0
8007d36: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
8007d38: 2300 movs r3, #0
8007d3a: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
8007d3c: 687b ldr r3, [r7, #4]
8007d3e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8007d42: 78fa ldrb r2, [r7, #3]
8007d44: 4611 mov r1, r2
8007d46: 4618 mov r0, r3
8007d48: f7fa fd06 bl 8002758 <HAL_PCD_EP_SetStall>
8007d4c: 4603 mov r3, r0
8007d4e: 73bb strb r3, [r7, #14]
switch (hal_status) {
8007d50: 7bbb ldrb r3, [r7, #14]
8007d52: 2b03 cmp r3, #3
8007d54: d816 bhi.n 8007d84 <USBD_LL_StallEP+0x5c>
8007d56: a201 add r2, pc, #4 @ (adr r2, 8007d5c <USBD_LL_StallEP+0x34>)
8007d58: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007d5c: 08007d6d .word 0x08007d6d
8007d60: 08007d73 .word 0x08007d73
8007d64: 08007d79 .word 0x08007d79
8007d68: 08007d7f .word 0x08007d7f
case HAL_OK :
usb_status = USBD_OK;
8007d6c: 2300 movs r3, #0
8007d6e: 73fb strb r3, [r7, #15]
break;
8007d70: e00b b.n 8007d8a <USBD_LL_StallEP+0x62>
case HAL_ERROR :
usb_status = USBD_FAIL;
8007d72: 2303 movs r3, #3
8007d74: 73fb strb r3, [r7, #15]
break;
8007d76: e008 b.n 8007d8a <USBD_LL_StallEP+0x62>
case HAL_BUSY :
usb_status = USBD_BUSY;
8007d78: 2301 movs r3, #1
8007d7a: 73fb strb r3, [r7, #15]
break;
8007d7c: e005 b.n 8007d8a <USBD_LL_StallEP+0x62>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
8007d7e: 2303 movs r3, #3
8007d80: 73fb strb r3, [r7, #15]
break;
8007d82: e002 b.n 8007d8a <USBD_LL_StallEP+0x62>
default :
usb_status = USBD_FAIL;
8007d84: 2303 movs r3, #3
8007d86: 73fb strb r3, [r7, #15]
break;
8007d88: bf00 nop
}
return usb_status;
8007d8a: 7bfb ldrb r3, [r7, #15]
}
8007d8c: 4618 mov r0, r3
8007d8e: 3710 adds r7, #16
8007d90: 46bd mov sp, r7
8007d92: bd80 pop {r7, pc}
08007d94 <USBD_LL_ClearStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8007d94: b580 push {r7, lr}
8007d96: b084 sub sp, #16
8007d98: af00 add r7, sp, #0
8007d9a: 6078 str r0, [r7, #4]
8007d9c: 460b mov r3, r1
8007d9e: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8007da0: 2300 movs r3, #0
8007da2: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
8007da4: 2300 movs r3, #0
8007da6: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
8007da8: 687b ldr r3, [r7, #4]
8007daa: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8007dae: 78fa ldrb r2, [r7, #3]
8007db0: 4611 mov r1, r2
8007db2: 4618 mov r0, r3
8007db4: f7fa fd32 bl 800281c <HAL_PCD_EP_ClrStall>
8007db8: 4603 mov r3, r0
8007dba: 73bb strb r3, [r7, #14]
switch (hal_status) {
8007dbc: 7bbb ldrb r3, [r7, #14]
8007dbe: 2b03 cmp r3, #3
8007dc0: d816 bhi.n 8007df0 <USBD_LL_ClearStallEP+0x5c>
8007dc2: a201 add r2, pc, #4 @ (adr r2, 8007dc8 <USBD_LL_ClearStallEP+0x34>)
8007dc4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007dc8: 08007dd9 .word 0x08007dd9
8007dcc: 08007ddf .word 0x08007ddf
8007dd0: 08007de5 .word 0x08007de5
8007dd4: 08007deb .word 0x08007deb
case HAL_OK :
usb_status = USBD_OK;
8007dd8: 2300 movs r3, #0
8007dda: 73fb strb r3, [r7, #15]
break;
8007ddc: e00b b.n 8007df6 <USBD_LL_ClearStallEP+0x62>
case HAL_ERROR :
usb_status = USBD_FAIL;
8007dde: 2303 movs r3, #3
8007de0: 73fb strb r3, [r7, #15]
break;
8007de2: e008 b.n 8007df6 <USBD_LL_ClearStallEP+0x62>
case HAL_BUSY :
usb_status = USBD_BUSY;
8007de4: 2301 movs r3, #1
8007de6: 73fb strb r3, [r7, #15]
break;
8007de8: e005 b.n 8007df6 <USBD_LL_ClearStallEP+0x62>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
8007dea: 2303 movs r3, #3
8007dec: 73fb strb r3, [r7, #15]
break;
8007dee: e002 b.n 8007df6 <USBD_LL_ClearStallEP+0x62>
default :
usb_status = USBD_FAIL;
8007df0: 2303 movs r3, #3
8007df2: 73fb strb r3, [r7, #15]
break;
8007df4: bf00 nop
}
return usb_status;
8007df6: 7bfb ldrb r3, [r7, #15]
}
8007df8: 4618 mov r0, r3
8007dfa: 3710 adds r7, #16
8007dfc: 46bd mov sp, r7
8007dfe: bd80 pop {r7, pc}
08007e00 <USBD_LL_IsStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Stall (1: Yes, 0: No)
*/
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8007e00: b480 push {r7}
8007e02: b085 sub sp, #20
8007e04: af00 add r7, sp, #0
8007e06: 6078 str r0, [r7, #4]
8007e08: 460b mov r3, r1
8007e0a: 70fb strb r3, [r7, #3]
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
8007e0c: 687b ldr r3, [r7, #4]
8007e0e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8007e12: 60fb str r3, [r7, #12]
if((ep_addr & 0x80) == 0x80)
8007e14: f997 3003 ldrsb.w r3, [r7, #3]
8007e18: 2b00 cmp r3, #0
8007e1a: da0b bge.n 8007e34 <USBD_LL_IsStallEP+0x34>
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
8007e1c: 78fb ldrb r3, [r7, #3]
8007e1e: f003 027f and.w r2, r3, #127 @ 0x7f
8007e22: 68f9 ldr r1, [r7, #12]
8007e24: 4613 mov r3, r2
8007e26: 00db lsls r3, r3, #3
8007e28: 4413 add r3, r2
8007e2a: 009b lsls r3, r3, #2
8007e2c: 440b add r3, r1
8007e2e: 3316 adds r3, #22
8007e30: 781b ldrb r3, [r3, #0]
8007e32: e00b b.n 8007e4c <USBD_LL_IsStallEP+0x4c>
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
8007e34: 78fb ldrb r3, [r7, #3]
8007e36: f003 027f and.w r2, r3, #127 @ 0x7f
8007e3a: 68f9 ldr r1, [r7, #12]
8007e3c: 4613 mov r3, r2
8007e3e: 00db lsls r3, r3, #3
8007e40: 4413 add r3, r2
8007e42: 009b lsls r3, r3, #2
8007e44: 440b add r3, r1
8007e46: f203 2356 addw r3, r3, #598 @ 0x256
8007e4a: 781b ldrb r3, [r3, #0]
}
}
8007e4c: 4618 mov r0, r3
8007e4e: 3714 adds r7, #20
8007e50: 46bd mov sp, r7
8007e52: f85d 7b04 ldr.w r7, [sp], #4
8007e56: 4770 bx lr
08007e58 <USBD_LL_SetUSBAddress>:
* @param pdev: Device handle
* @param dev_addr: Device address
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
{
8007e58: b580 push {r7, lr}
8007e5a: b084 sub sp, #16
8007e5c: af00 add r7, sp, #0
8007e5e: 6078 str r0, [r7, #4]
8007e60: 460b mov r3, r1
8007e62: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8007e64: 2300 movs r3, #0
8007e66: 73bb strb r3, [r7, #14]
USBD_StatusTypeDef usb_status = USBD_OK;
8007e68: 2300 movs r3, #0
8007e6a: 73fb strb r3, [r7, #15]
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
8007e6c: 687b ldr r3, [r7, #4]
8007e6e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8007e72: 78fa ldrb r2, [r7, #3]
8007e74: 4611 mov r1, r2
8007e76: 4618 mov r0, r3
8007e78: f7fa fb33 bl 80024e2 <HAL_PCD_SetAddress>
8007e7c: 4603 mov r3, r0
8007e7e: 73bb strb r3, [r7, #14]
switch (hal_status) {
8007e80: 7bbb ldrb r3, [r7, #14]
8007e82: 2b03 cmp r3, #3
8007e84: d816 bhi.n 8007eb4 <USBD_LL_SetUSBAddress+0x5c>
8007e86: a201 add r2, pc, #4 @ (adr r2, 8007e8c <USBD_LL_SetUSBAddress+0x34>)
8007e88: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007e8c: 08007e9d .word 0x08007e9d
8007e90: 08007ea3 .word 0x08007ea3
8007e94: 08007ea9 .word 0x08007ea9
8007e98: 08007eaf .word 0x08007eaf
case HAL_OK :
usb_status = USBD_OK;
8007e9c: 2300 movs r3, #0
8007e9e: 73fb strb r3, [r7, #15]
break;
8007ea0: e00b b.n 8007eba <USBD_LL_SetUSBAddress+0x62>
case HAL_ERROR :
usb_status = USBD_FAIL;
8007ea2: 2303 movs r3, #3
8007ea4: 73fb strb r3, [r7, #15]
break;
8007ea6: e008 b.n 8007eba <USBD_LL_SetUSBAddress+0x62>
case HAL_BUSY :
usb_status = USBD_BUSY;
8007ea8: 2301 movs r3, #1
8007eaa: 73fb strb r3, [r7, #15]
break;
8007eac: e005 b.n 8007eba <USBD_LL_SetUSBAddress+0x62>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
8007eae: 2303 movs r3, #3
8007eb0: 73fb strb r3, [r7, #15]
break;
8007eb2: e002 b.n 8007eba <USBD_LL_SetUSBAddress+0x62>
default :
usb_status = USBD_FAIL;
8007eb4: 2303 movs r3, #3
8007eb6: 73fb strb r3, [r7, #15]
break;
8007eb8: bf00 nop
}
return usb_status;
8007eba: 7bfb ldrb r3, [r7, #15]
}
8007ebc: 4618 mov r0, r3
8007ebe: 3710 adds r7, #16
8007ec0: 46bd mov sp, r7
8007ec2: bd80 pop {r7, pc}
08007ec4 <USBD_LL_Transmit>:
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
{
8007ec4: b580 push {r7, lr}
8007ec6: b086 sub sp, #24
8007ec8: af00 add r7, sp, #0
8007eca: 60f8 str r0, [r7, #12]
8007ecc: 607a str r2, [r7, #4]
8007ece: 603b str r3, [r7, #0]
8007ed0: 460b mov r3, r1
8007ed2: 72fb strb r3, [r7, #11]
HAL_StatusTypeDef hal_status = HAL_OK;
8007ed4: 2300 movs r3, #0
8007ed6: 75bb strb r3, [r7, #22]
USBD_StatusTypeDef usb_status = USBD_OK;
8007ed8: 2300 movs r3, #0
8007eda: 75fb strb r3, [r7, #23]
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
8007edc: 68fb ldr r3, [r7, #12]
8007ede: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
8007ee2: 7af9 ldrb r1, [r7, #11]
8007ee4: 683b ldr r3, [r7, #0]
8007ee6: 687a ldr r2, [r7, #4]
8007ee8: f7fa fc05 bl 80026f6 <HAL_PCD_EP_Transmit>
8007eec: 4603 mov r3, r0
8007eee: 75bb strb r3, [r7, #22]
switch (hal_status) {
8007ef0: 7dbb ldrb r3, [r7, #22]
8007ef2: 2b03 cmp r3, #3
8007ef4: d816 bhi.n 8007f24 <USBD_LL_Transmit+0x60>
8007ef6: a201 add r2, pc, #4 @ (adr r2, 8007efc <USBD_LL_Transmit+0x38>)
8007ef8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007efc: 08007f0d .word 0x08007f0d
8007f00: 08007f13 .word 0x08007f13
8007f04: 08007f19 .word 0x08007f19
8007f08: 08007f1f .word 0x08007f1f
case HAL_OK :
usb_status = USBD_OK;
8007f0c: 2300 movs r3, #0
8007f0e: 75fb strb r3, [r7, #23]
break;
8007f10: e00b b.n 8007f2a <USBD_LL_Transmit+0x66>
case HAL_ERROR :
usb_status = USBD_FAIL;
8007f12: 2303 movs r3, #3
8007f14: 75fb strb r3, [r7, #23]
break;
8007f16: e008 b.n 8007f2a <USBD_LL_Transmit+0x66>
case HAL_BUSY :
usb_status = USBD_BUSY;
8007f18: 2301 movs r3, #1
8007f1a: 75fb strb r3, [r7, #23]
break;
8007f1c: e005 b.n 8007f2a <USBD_LL_Transmit+0x66>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
8007f1e: 2303 movs r3, #3
8007f20: 75fb strb r3, [r7, #23]
break;
8007f22: e002 b.n 8007f2a <USBD_LL_Transmit+0x66>
default :
usb_status = USBD_FAIL;
8007f24: 2303 movs r3, #3
8007f26: 75fb strb r3, [r7, #23]
break;
8007f28: bf00 nop
}
return usb_status;
8007f2a: 7dfb ldrb r3, [r7, #23]
}
8007f2c: 4618 mov r0, r3
8007f2e: 3718 adds r7, #24
8007f30: 46bd mov sp, r7
8007f32: bd80 pop {r7, pc}
08007f34 <USBD_LL_PrepareReceive>:
* @param pbuf: Pointer to data to be received
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
{
8007f34: b580 push {r7, lr}
8007f36: b086 sub sp, #24
8007f38: af00 add r7, sp, #0
8007f3a: 60f8 str r0, [r7, #12]
8007f3c: 607a str r2, [r7, #4]
8007f3e: 603b str r3, [r7, #0]
8007f40: 460b mov r3, r1
8007f42: 72fb strb r3, [r7, #11]
HAL_StatusTypeDef hal_status = HAL_OK;
8007f44: 2300 movs r3, #0
8007f46: 75bb strb r3, [r7, #22]
USBD_StatusTypeDef usb_status = USBD_OK;
8007f48: 2300 movs r3, #0
8007f4a: 75fb strb r3, [r7, #23]
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
8007f4c: 68fb ldr r3, [r7, #12]
8007f4e: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
8007f52: 7af9 ldrb r1, [r7, #11]
8007f54: 683b ldr r3, [r7, #0]
8007f56: 687a ldr r2, [r7, #4]
8007f58: f7fa fb9b bl 8002692 <HAL_PCD_EP_Receive>
8007f5c: 4603 mov r3, r0
8007f5e: 75bb strb r3, [r7, #22]
switch (hal_status) {
8007f60: 7dbb ldrb r3, [r7, #22]
8007f62: 2b03 cmp r3, #3
8007f64: d816 bhi.n 8007f94 <USBD_LL_PrepareReceive+0x60>
8007f66: a201 add r2, pc, #4 @ (adr r2, 8007f6c <USBD_LL_PrepareReceive+0x38>)
8007f68: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007f6c: 08007f7d .word 0x08007f7d
8007f70: 08007f83 .word 0x08007f83
8007f74: 08007f89 .word 0x08007f89
8007f78: 08007f8f .word 0x08007f8f
case HAL_OK :
usb_status = USBD_OK;
8007f7c: 2300 movs r3, #0
8007f7e: 75fb strb r3, [r7, #23]
break;
8007f80: e00b b.n 8007f9a <USBD_LL_PrepareReceive+0x66>
case HAL_ERROR :
usb_status = USBD_FAIL;
8007f82: 2303 movs r3, #3
8007f84: 75fb strb r3, [r7, #23]
break;
8007f86: e008 b.n 8007f9a <USBD_LL_PrepareReceive+0x66>
case HAL_BUSY :
usb_status = USBD_BUSY;
8007f88: 2301 movs r3, #1
8007f8a: 75fb strb r3, [r7, #23]
break;
8007f8c: e005 b.n 8007f9a <USBD_LL_PrepareReceive+0x66>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
8007f8e: 2303 movs r3, #3
8007f90: 75fb strb r3, [r7, #23]
break;
8007f92: e002 b.n 8007f9a <USBD_LL_PrepareReceive+0x66>
default :
usb_status = USBD_FAIL;
8007f94: 2303 movs r3, #3
8007f96: 75fb strb r3, [r7, #23]
break;
8007f98: bf00 nop
}
return usb_status;
8007f9a: 7dfb ldrb r3, [r7, #23]
}
8007f9c: 4618 mov r0, r3
8007f9e: 3718 adds r7, #24
8007fa0: 46bd mov sp, r7
8007fa2: bd80 pop {r7, pc}
08007fa4 <HAL_PCDEx_LPM_Callback>:
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval None
*/
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
8007fa4: b580 push {r7, lr}
8007fa6: b082 sub sp, #8
8007fa8: af00 add r7, sp, #0
8007faa: 6078 str r0, [r7, #4]
8007fac: 460b mov r3, r1
8007fae: 70fb strb r3, [r7, #3]
switch (msg)
8007fb0: 78fb ldrb r3, [r7, #3]
8007fb2: 2b00 cmp r3, #0
8007fb4: d002 beq.n 8007fbc <HAL_PCDEx_LPM_Callback+0x18>
8007fb6: 2b01 cmp r3, #1
8007fb8: d01f beq.n 8007ffa <HAL_PCDEx_LPM_Callback+0x56>
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
}
break;
}
}
8007fba: e03b b.n 8008034 <HAL_PCDEx_LPM_Callback+0x90>
if (hpcd->Init.low_power_enable)
8007fbc: 687b ldr r3, [r7, #4]
8007fbe: 7adb ldrb r3, [r3, #11]
8007fc0: 2b00 cmp r3, #0
8007fc2: d007 beq.n 8007fd4 <HAL_PCDEx_LPM_Callback+0x30>
SystemClockConfig_Resume();
8007fc4: f000 f854 bl 8008070 <SystemClockConfig_Resume>
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
8007fc8: 4b1c ldr r3, [pc, #112] @ (800803c <HAL_PCDEx_LPM_Callback+0x98>)
8007fca: 691b ldr r3, [r3, #16]
8007fcc: 4a1b ldr r2, [pc, #108] @ (800803c <HAL_PCDEx_LPM_Callback+0x98>)
8007fce: f023 0306 bic.w r3, r3, #6
8007fd2: 6113 str r3, [r2, #16]
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
8007fd4: 687b ldr r3, [r7, #4]
8007fd6: 681b ldr r3, [r3, #0]
8007fd8: f503 6360 add.w r3, r3, #3584 @ 0xe00
8007fdc: 681b ldr r3, [r3, #0]
8007fde: 687a ldr r2, [r7, #4]
8007fe0: 6812 ldr r2, [r2, #0]
8007fe2: f502 6260 add.w r2, r2, #3584 @ 0xe00
8007fe6: f023 0301 bic.w r3, r3, #1
8007fea: 6013 str r3, [r2, #0]
USBD_LL_Resume(hpcd->pData);
8007fec: 687b ldr r3, [r7, #4]
8007fee: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8007ff2: 4618 mov r0, r3
8007ff4: f7fe fa49 bl 800648a <USBD_LL_Resume>
break;
8007ff8: e01c b.n 8008034 <HAL_PCDEx_LPM_Callback+0x90>
__HAL_PCD_GATE_PHYCLOCK(hpcd);
8007ffa: 687b ldr r3, [r7, #4]
8007ffc: 681b ldr r3, [r3, #0]
8007ffe: f503 6360 add.w r3, r3, #3584 @ 0xe00
8008002: 681b ldr r3, [r3, #0]
8008004: 687a ldr r2, [r7, #4]
8008006: 6812 ldr r2, [r2, #0]
8008008: f502 6260 add.w r2, r2, #3584 @ 0xe00
800800c: f043 0301 orr.w r3, r3, #1
8008010: 6013 str r3, [r2, #0]
USBD_LL_Suspend(hpcd->pData);
8008012: 687b ldr r3, [r7, #4]
8008014: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
8008018: 4618 mov r0, r3
800801a: f7fe fa1a bl 8006452 <USBD_LL_Suspend>
if (hpcd->Init.low_power_enable)
800801e: 687b ldr r3, [r7, #4]
8008020: 7adb ldrb r3, [r3, #11]
8008022: 2b00 cmp r3, #0
8008024: d005 beq.n 8008032 <HAL_PCDEx_LPM_Callback+0x8e>
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
8008026: 4b05 ldr r3, [pc, #20] @ (800803c <HAL_PCDEx_LPM_Callback+0x98>)
8008028: 691b ldr r3, [r3, #16]
800802a: 4a04 ldr r2, [pc, #16] @ (800803c <HAL_PCDEx_LPM_Callback+0x98>)
800802c: f043 0306 orr.w r3, r3, #6
8008030: 6113 str r3, [r2, #16]
break;
8008032: bf00 nop
}
8008034: bf00 nop
8008036: 3708 adds r7, #8
8008038: 46bd mov sp, r7
800803a: bd80 pop {r7, pc}
800803c: e000ed00 .word 0xe000ed00
08008040 <USBD_static_malloc>:
* @brief Static single allocation.
* @param size: Size of allocated memory
* @retval None
*/
void *USBD_static_malloc(uint32_t size)
{
8008040: b480 push {r7}
8008042: b083 sub sp, #12
8008044: af00 add r7, sp, #0
8008046: 6078 str r0, [r7, #4]
static uint32_t mem[(sizeof(USBD_CUSTOM_HID_HandleTypeDef)/4+1)];/* On 32-bit boundary */
return mem;
8008048: 4b03 ldr r3, [pc, #12] @ (8008058 <USBD_static_malloc+0x18>)
}
800804a: 4618 mov r0, r3
800804c: 370c adds r7, #12
800804e: 46bd mov sp, r7
8008050: f85d 7b04 ldr.w r7, [sp], #4
8008054: 4770 bx lr
8008056: bf00 nop
8008058: 20000b64 .word 0x20000b64
0800805c <USBD_static_free>:
* @brief Dummy memory free
* @param p: Pointer to allocated memory address
* @retval None
*/
void USBD_static_free(void *p)
{
800805c: b480 push {r7}
800805e: b083 sub sp, #12
8008060: af00 add r7, sp, #0
8008062: 6078 str r0, [r7, #4]
}
8008064: bf00 nop
8008066: 370c adds r7, #12
8008068: 46bd mov sp, r7
800806a: f85d 7b04 ldr.w r7, [sp], #4
800806e: 4770 bx lr
08008070 <SystemClockConfig_Resume>:
* @brief Configures system clock after wake-up from USB resume callBack:
* enable HSI, PLL and select PLL as system clock source.
* @retval None
*/
static void SystemClockConfig_Resume(void)
{
8008070: b580 push {r7, lr}
8008072: af00 add r7, sp, #0
SystemClock_Config();
8008074: f7f8 f936 bl 80002e4 <SystemClock_Config>
}
8008078: bf00 nop
800807a: bd80 pop {r7, pc}
0800807c <memset>:
800807c: 4402 add r2, r0
800807e: 4603 mov r3, r0
8008080: 4293 cmp r3, r2
8008082: d100 bne.n 8008086 <memset+0xa>
8008084: 4770 bx lr
8008086: f803 1b01 strb.w r1, [r3], #1
800808a: e7f9 b.n 8008080 <memset+0x4>
0800808c <__libc_init_array>:
800808c: b570 push {r4, r5, r6, lr}
800808e: 4d0d ldr r5, [pc, #52] @ (80080c4 <__libc_init_array+0x38>)
8008090: 4c0d ldr r4, [pc, #52] @ (80080c8 <__libc_init_array+0x3c>)
8008092: 1b64 subs r4, r4, r5
8008094: 10a4 asrs r4, r4, #2
8008096: 2600 movs r6, #0
8008098: 42a6 cmp r6, r4
800809a: d109 bne.n 80080b0 <__libc_init_array+0x24>
800809c: 4d0b ldr r5, [pc, #44] @ (80080cc <__libc_init_array+0x40>)
800809e: 4c0c ldr r4, [pc, #48] @ (80080d0 <__libc_init_array+0x44>)
80080a0: f000 f818 bl 80080d4 <_init>
80080a4: 1b64 subs r4, r4, r5
80080a6: 10a4 asrs r4, r4, #2
80080a8: 2600 movs r6, #0
80080aa: 42a6 cmp r6, r4
80080ac: d105 bne.n 80080ba <__libc_init_array+0x2e>
80080ae: bd70 pop {r4, r5, r6, pc}
80080b0: f855 3b04 ldr.w r3, [r5], #4
80080b4: 4798 blx r3
80080b6: 3601 adds r6, #1
80080b8: e7ee b.n 8008098 <__libc_init_array+0xc>
80080ba: f855 3b04 ldr.w r3, [r5], #4
80080be: 4798 blx r3
80080c0: 3601 adds r6, #1
80080c2: e7f2 b.n 80080aa <__libc_init_array+0x1e>
80080c4: 0800818c .word 0x0800818c
80080c8: 0800818c .word 0x0800818c
80080cc: 0800818c .word 0x0800818c
80080d0: 08008190 .word 0x08008190
080080d4 <_init>:
80080d4: b5f8 push {r3, r4, r5, r6, r7, lr}
80080d6: bf00 nop
80080d8: bcf8 pop {r3, r4, r5, r6, r7}
80080da: bc08 pop {r3}
80080dc: 469e mov lr, r3
80080de: 4770 bx lr
080080e0 <_fini>:
80080e0: b5f8 push {r3, r4, r5, r6, r7, lr}
80080e2: bf00 nop
80080e4: bcf8 pop {r3, r4, r5, r6, r7}
80080e6: bc08 pop {r3}
80080e8: 469e mov lr, r3
80080ea: 4770 bx lr
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