62 lines
1.6 KiB
Verilog
62 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: Hazard Unit
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// Module Name: hazard
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Manages hazards between memory instructions and any other
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module hazard (
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input [4:0] IF_ID_Rs1,
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input [4:0] IF_ID_Rs2,
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input [4:0] ID_EX_Rd,
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input ID_EX_MemRead,
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input Branch_Taken,
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output reg PC_En,
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output reg IF_ID_En,
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output reg IF_ID_Clr,
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output reg ID_EX_Clr
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);
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always @(*) begin
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PC_En = 1'b1;
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IF_ID_En = 1'b1;
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IF_ID_Clr = 1'b0;
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ID_EX_Clr = 1'b0;
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// si:
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// - se lee de memoria
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// - el Rd no es x0
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// - el Rd es Rs1 o Rs2
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// entonces:
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// bloqueamos para que el dato generado en ME lo pueda coger EX
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if (ID_EX_MemRead && (ID_EX_Rd != 5'b0) &&
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((ID_EX_Rd == IF_ID_Rs1) || (ID_EX_Rd == IF_ID_Rs2))) begin
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PC_En = 1'b0;
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IF_ID_En = 1'b0;
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ID_EX_Clr = 1'b1;
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end
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// si:
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// - salto tomado
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// entonces:
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// flush síncrono al reg IF/ID
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else if (Branch_Taken) begin
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IF_ID_Clr = 1'b1;
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end
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end
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endmodule |