58 lines
1.4 KiB
Verilog
58 lines
1.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: Immediate Generator
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// Module Name: imm_gen
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Retrieves the immediate from the instruction (uses verilog concat)
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module imm_gen(
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input [31:0] inst_in,
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output reg [31:0] imm_out
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);
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always @(*) begin
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case(inst_in[6:0])
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// Formato I
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7'b0010011,
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7'b0000011,
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7'b1100111:
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imm_out = {{20{inst_in[31]}}, inst_in[31:20]};
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// Formato S
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7'b0100011:
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imm_out = {{20{inst_in[31]}}, inst_in[31:25], inst_in[11:7]};
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// Formato B
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7'b1100011:
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imm_out = {{19{inst_in[31]}}, inst_in[31], inst_in[7], inst_in[30:25], inst_in[11:8], 1'b0};
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// Formato J
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7'b1101111:
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imm_out = {{11{inst_in[31]}}, inst_in[31], inst_in[19:12], inst_in[20], inst_in[30:21], 1'b0};
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// Formato U
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7'b0110111,
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7'b0010111:
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imm_out = {inst_in[31:12], 12'b0};
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default:
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imm_out = 32'b0;
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endcase
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end
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endmodule
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