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riscv-ac/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav
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Jose d7e166ca6f refactor: renamed top.v to riscv.v
2026-03-03 04:05:49 +01:00
..
obj
add: uart_tx module
2026-03-03 03:41:56 +01:00
Compile_Options.txt
prototype works
2026-03-02 23:20:54 +01:00
TempBreakPointFile.txt
prototype works
2026-03-02 23:20:54 +01:00
xsim.dbg
add: uart_tx module
2026-03-03 03:41:56 +01:00
xsim.mem
add: uart_tx module
2026-03-03 03:41:56 +01:00
xsim.reloc
add: uart_tx module
2026-03-03 03:41:56 +01:00
xsim.rlx
add: uart_tx module
2026-03-03 03:41:56 +01:00
xsim.rtti
add: uart_tx module
2026-03-03 03:41:56 +01:00
xsim.svtype
prototype works
2026-03-02 23:20:54 +01:00
xsim.type
prototype works
2026-03-02 23:20:54 +01:00
xsim.version
prototype works
2026-03-02 23:20:54 +01:00
xsim.xdbg
add: uart_tx module
2026-03-03 03:41:56 +01:00
xsimk
add: uart_tx module
2026-03-03 03:41:56 +01:00
xsimSettings.ini
refactor: renamed top.v to riscv.v
2026-03-03 04:05:49 +01:00