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2026-03-02 23:20:54 +01:00

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$date
Sun Mar 1 19:39:07 2026
$end
$version
2025.2
$dumpfile ("tb_top.vcd")
$end
$timescale
1ps
$end
$scope module tb_top $end
$var reg 1 ! clk $end
$var reg 1 " rst $end
$scope module uut $end
$var wire 1 # clk $end
$var wire 1 $ rst $end
$var wire 32 % pc_F [31:0] $end
$var wire 32 & pc4_F [31:0] $end
$var wire 32 ' instr_F [31:0] $end
$var wire 32 ( next_pc_F [31:0] $end
$var wire 1 ) PC_En $end
$var wire 1 * IF_ID_En $end
$var wire 1 + IF_ID_Clr $end
$var wire 32 , pc_D [31:0] $end
$var wire 32 - pc4_D [31:0] $end
$var wire 32 . instr_D [31:0] $end
$var wire 5 / rs1_D [4:0] $end
$var wire 5 0 rs2_D [4:0] $end
$var wire 5 1 rd_D [4:0] $end
$var wire 32 2 imm_D [31:0] $end
$var wire 32 3 regA_D [31:0] $end
$var wire 32 4 regB_D [31:0] $end
$var wire 1 5 we_reg_D $end
$var wire 1 6 we_mem_D $end
$var wire 1 7 mem_to_reg_D $end
$var wire 1 8 alu_src_D $end
$var wire 1 9 branch_D $end
$var wire 4 : alu_op_D [3:0] $end
$var wire 1 ; Branch_Taken $end
$var wire 32 < branch_target_D [31:0] $end
$var wire 2 = ID_ForwardA [1:0] $end
$var wire 2 > ID_ForwardB [1:0] $end
$var wire 32 ? cmp_A [31:0] $end
$var wire 32 @ cmp_B [31:0] $end
$var wire 1 A ID_EX_Clr $end
$var wire 32 B pc_E [31:0] $end
$var wire 32 C pc4_E [31:0] $end
$var wire 32 D regA_E [31:0] $end
$var wire 32 E regB_E [31:0] $end
$var wire 32 F imm_E [31:0] $end
$var wire 5 G rs1_E [4:0] $end
$var wire 5 H rs2_E [4:0] $end
$var wire 5 I rd_E [4:0] $end
$var wire 1 J we_reg_E $end
$var wire 1 K we_mem_E $end
$var wire 1 L mem_to_reg_E $end
$var wire 1 M alu_src_E $end
$var wire 1 N branch_E $end
$var wire 4 O alu_op_E [3:0] $end
$var wire 2 P EX_ForwardA [1:0] $end
$var wire 2 Q EX_ForwardB [1:0] $end
$var wire 32 R alu_A [31:0] $end
$var wire 32 S alu_B_temp [31:0] $end
$var wire 32 T alu_B [31:0] $end
$var wire 32 U alu_res_E [31:0] $end
$var wire 1 V alu_zero_E $end
$var wire 32 W alu_res_M [31:0] $end
$var wire 32 X regB_M [31:0] $end
$var wire 32 Y pc4_M [31:0] $end
$var wire 5 Z rd_M [4:0] $end
$var wire 1 [ we_reg_M $end
$var wire 1 \ we_mem_M $end
$var wire 1 ] mem_to_reg_M $end
$var wire 32 ^ mem_data_M [31:0] $end
$var wire 32 _ alu_res_W [31:0] $end
$var wire 32 ` mem_data_W [31:0] $end
$var wire 32 a pc4_W [31:0] $end
$var wire 5 b rd_W [4:0] $end
$var wire 1 c we_reg_W $end
$var wire 1 d mem_to_reg_W $end
$var wire 32 e write_data_W [31:0] $end
$scope module u_pc $end
$var wire 1 # clk $end
$var wire 1 f rst $end
$var wire 32 ( next_pc [31:0] $end
$var reg 32 g imem_addr [31:0] $end
$upscope $end
$scope module u_imem $end
$var wire 1 # clk $end
$var wire 32 % address [31:0] $end
$var wire 1 h we $end
$var wire 32 i write_data [31:0] $end
$var wire 8 j write_addr [7:0] $end
$var wire 32 ' instruction [31:0] $end
$upscope $end
$scope module u_if_id $end
$var wire 1 # clk $end
$var wire 1 $ rst $end
$var wire 1 * en $end
$var wire 1 + clr $end
$var wire 32 % pc_in [31:0] $end
$var wire 32 & pc4_in [31:0] $end
$var wire 32 ' inst_in [31:0] $end
$var reg 32 k pc_out [31:0] $end
$var reg 32 l pc4_out [31:0] $end
$var reg 32 m inst_out [31:0] $end
$upscope $end
$scope module u_control $end
$var wire 7 n opcode [6:0] $end
$var wire 3 o aux [14:12] $end
$var wire 7 p func [31:25] $end
$var reg 1 q we_reg $end
$var reg 1 r we_mem $end
$var reg 1 s mem_to_reg $end
$var reg 1 t alu_src $end
$var reg 4 u alu_op [3:0] $end
$var reg 1 v branch $end
$upscope $end
$scope module u_regfile $end
$var wire 1 w clk $end
$var wire 1 c regwrite $end
$var wire 5 / rs1 [4:0] $end
$var wire 5 0 rs2 [4:0] $end
$var wire 5 b rd [4:0] $end
$var wire 32 e write_data [31:0] $end
$var wire 32 3 read_data_1 [31:0] $end
$var wire 32 4 read_data_2 [31:0] $end
$upscope $end
$scope module u_imm_gen $end
$var wire 32 . instr [31:0] $end
$var reg 32 x imm_out [31:0] $end
$upscope $end
$scope module u_hazard $end
$var wire 5 / IF_ID_Rs1 [4:0] $end
$var wire 5 0 IF_ID_Rs2 [4:0] $end
$var wire 5 I ID_EX_Rd [4:0] $end
$var wire 1 L ID_EX_MemRead $end
$var wire 1 ; Branch_Taken $end
$var reg 1 y PC_En $end
$var reg 1 z IF_ID_En $end
$var reg 1 { IF_ID_Clr $end
$var reg 1 | ID_EX_Clr $end
$upscope $end
$scope module u_id_ex $end
$var wire 1 # clk $end
$var wire 1 $ rst $end
$var wire 1 A clr $end
$var wire 1 5 we_reg_in $end
$var wire 1 6 we_mem_in $end
$var wire 1 7 mem_to_reg_in $end
$var wire 1 8 alu_src_in $end
$var wire 1 9 branch_in $end
$var wire 4 : alu_op_in [3:0] $end
$var reg 1 } we_reg_out $end
$var reg 1 ~ we_mem_out $end
$var reg 1 !! mem_to_reg_out $end
$var reg 1 "! alu_src_out $end
$var reg 1 #! branch_out $end
$var reg 4 $! alu_op_out [3:0] $end
$var wire 32 , pc_in [31:0] $end
$var wire 32 - pc4_in [31:0] $end
$var wire 32 3 regA_in [31:0] $end
$var wire 32 4 regB_in [31:0] $end
$var wire 32 2 imm_in [31:0] $end
$var wire 5 / rs1_in [4:0] $end
$var wire 5 0 rs2_in [4:0] $end
$var wire 5 1 rd_in [4:0] $end
$var reg 32 %! pc_out [31:0] $end
$var reg 32 &! pc4_out [31:0] $end
$var reg 32 '! regA_out [31:0] $end
$var reg 32 (! regB_out [31:0] $end
$var reg 32 )! imm_out [31:0] $end
$var reg 5 *! rs1_out [4:0] $end
$var reg 5 +! rs2_out [4:0] $end
$var reg 5 ,! rd_out [4:0] $end
$upscope $end
$scope module u_forwarding $end
$var wire 5 G ID_EX_Rs1 [4:0] $end
$var wire 5 H ID_EX_Rs2 [4:0] $end
$var wire 5 / IF_ID_Rs1 [4:0] $end
$var wire 5 0 IF_ID_Rs2 [4:0] $end
$var wire 5 Z EX_ME_Rd [4:0] $end
$var wire 1 [ EX_ME_RegWrite $end
$var wire 5 b ME_WB_Rd [4:0] $end
$var wire 1 c ME_WB_RegWrite $end
$var reg 2 -! EX_ForwardA [1:0] $end
$var reg 2 .! EX_ForwardB [1:0] $end
$var reg 2 /! ID_ForwardA [1:0] $end
$var reg 2 0! ID_ForwardB [1:0] $end
$upscope $end
$scope module u_alu $end
$var wire 32 R A [31:0] $end
$var wire 32 T B [31:0] $end
$var wire 4 O sel [3:0] $end
$var reg 32 1! R [31:0] $end
$var wire 1 V zero $end
$upscope $end
$scope module u_ex_me $end
$var wire 1 # clk $end
$var wire 1 $ rst $end
$var wire 1 J we_reg_in $end
$var wire 1 K we_mem_in $end
$var wire 1 L mem_to_reg_in $end
$var reg 1 2! we_reg_out $end
$var reg 1 3! we_mem_out $end
$var reg 1 4! mem_to_reg_out $end
$var wire 32 U alu_res_in [31:0] $end
$var wire 32 S regB_in [31:0] $end
$var wire 32 C pc4_in [31:0] $end
$var wire 5 I rd_in [4:0] $end
$var reg 32 5! alu_res_out [31:0] $end
$var reg 32 6! regB_out [31:0] $end
$var reg 32 7! pc4_out [31:0] $end
$var reg 5 8! rd_out [4:0] $end
$upscope $end
$scope module u_dmem $end
$var wire 1 # clk $end
$var wire 1 \ we $end
$var wire 32 W address [31:0] $end
$var wire 32 X write_data [31:0] $end
$var wire 32 ^ read_data [31:0] $end
$upscope $end
$scope module u_me_wb $end
$var wire 1 # clk $end
$var wire 1 $ rst $end
$var wire 1 [ we_reg_in $end
$var wire 1 ] mem_to_reg_in $end
$var reg 1 9! we_reg_out $end
$var reg 1 :! mem_to_reg_out $end
$var wire 32 W alu_res_in [31:0] $end
$var wire 32 ^ mem_data_in [31:0] $end
$var wire 32 Y pc4_in [31:0] $end
$var wire 5 Z rd_in [4:0] $end
$var reg 32 ;! alu_res_out [31:0] $end
$var reg 32 <! mem_data_out [31:0] $end
$var reg 32 =! pc4_out [31:0] $end
$var reg 5 >! rd_out [4:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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b0 %
b0 %!
b100 &
b0 &!
b10100010011 '
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b0 +!
b0 ,
b0 ,!
b0 -
b0 -!
b0 .
b0 .!
b0 /
b0 /!
b0 0
b0 0!
b0 1
b0 1!
b0 2
02!
b0 3
03!
b0 4
04!
05
b0 5!
06
b0 6!
07
b0 7!
08
b0 8!
09
09!
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b0 ;!
b0 <
b0 <!
b0 =
b0 =!
b0 >
b0 >!
b0 ?
b0 @
0A
b0 B
b0 C
b0 D
b0 E
b0 F
b0 G
b0 H
b0 I
0J
0K
0L
0M
0N
b0 O
b0 P
b0 Q
b0 R
b0 S
b0 T
b0 U
1V
b0 W
b0 X
b0 Y
b0 Z
0[
0\
0]
bx ^
b0 _
b0 `
b0 a
b0 b
0c
0d
b0 e
1f
b0 g
0h
b0 i
b0 j
b0 k
b0 l
b0 m
b0 n
b0 o
b0 p
0q
0r
0s
0t
b0 u
0v
1w
b0 x
1y
1z
0{
0|
0}
0~
$end
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#15000
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#20000
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b100 %
b1000 &
b1100000000000110010011 '
b1000 (
b100 -
b10100010011 .
b1010 1
15
18
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bx `
b100 g
b100 l
b10100010011 m
b10011 n
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#30000
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#35000
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b1000 %
b1100 &
b100 &!
b10010000000000000100010011 '
b1100 (
b100 ,
b1010 ,!
b1000 -
b1100000000000110010011 .
b11 0
b11 1
b11 2
bx 4
b111 <
bx @
b100 C
b1010 I
1J
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b1000 g
b100 k
b1000 l
b1100000000000110010011 m
b10011 n
b0 o
b0 p
0w
b11 x
1}
#40000
0!
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#45000
1!
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b1100 %
b100 %!
b10000 &
b1000 &!
b10001010010001010000011 '
b10000 (
bx (!
b11 )!
b11 +!
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b1100 -
b10010000000000000100010011 .
b100 0
b10 1
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b101100 <
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b1100 g
b1000 k
b1100 l
b10010000000000000100010011 m
b10011 n
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b100100 x
#50000
0!
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#55000
1!
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b10000 %
b1000 %!
b10100 &
b1100 &!
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b10100 (
b100100 )!
b100 +!
b1100 ,
b10 ,!
b10000 -
b10001010010001010000011 .
b1010 /
b1 /!
b101 1
b100100 1!
b100 2
bx 3
b11 5!
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b11 8!
19!
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b100 =!
b1010 >!
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b1000 B
b1100 C
b100100 F
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b11 W
bx X
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b10000 g
b1100 k
b10000 l
b10001010010001010000011 m
b11 n
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b101 /
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b11 0
b1 0!
b1 1
b100 1!
b0 2
bx 3
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b11 ;!
b10000 <
b0 =
b1000 =!
b1 >
b11 >!
bx ?
b11 @
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b1100 B
b10000 C
b100 F
b1010 G
b101 I
1L
b100 T
b100 U
b100100 W
b1100 Y
b10 Z
b11 _
b1000 a
b11 b
b11 e
1f
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b10000 k
b10100 l
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b110011 n
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b1000 &
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b0 /
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bx 1!
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b0 ?
b0 @
b10000 B
b10100 C
bx D
b11 E
b101 G
b11 H
b1 I
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bx R
b11 S
b11 T
bx U
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b0 W
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0]
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1d
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b100 g
b0 k
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#90000
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b1100 &
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b11 0
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12!
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bx 5!
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b0 =!
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b11 @
b0 B
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b0 P
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#100000
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#115000
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17
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b1100 C
bx E
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b100 H
b10 I
bx S
b100100 T
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b11 W
b11 X
b1000 Y
b11 Z
b0 _
b100 a
b1010 b
b0 e
b10000 g
b1100 k
b10000 l
b10001010010001010000011 m
b11 n
b10 o
b0 p
1q
1s
1t
0w
b100 x
#120000
0!
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#125000
1!
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b0 %
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b100 &
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b10000 ,
b101 ,!
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b1100101000000010110011 .
b101 /
b0 /!
b11 0
b1 0!
b1 1
b100 1!
b0 2
bx 3
b11 4
b100100 5!
bx 6!
07
b1100 7!
08
b10 8!
b11 ;!
b10000 <
b0 =
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b1 >
b11 >!
bx ?
b11 @
1A
b1100 B
b10000 C
b100 F
b1010 G
b101 I
1L
b100 T
b100 U
b100100 W
bx X
b1100 Y
b10 Z
b11 _
b1000 a
b11 b
b11 e
1f
b0 g
b10000 k
b10100 l
b1100101000000010110011 m
b110011 n
b0 o
b0 p
1q
0s
0t
0w
b0 x
0y
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1|
#130000
0!
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1!
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b10 =
b1100 =!
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0A
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b0 G
b0 H
b0 I
0J
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b0 T
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1V
b100 W
b10000 Y
b101 Z
1]
b100100 _
b1100 a
b10 b
b100100 e
0f
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1y
1z
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#140000
0!
0#
1w
#145000
1!
1#
b100 %
b10000 %!
b1000 &
b10100 &!
b1100000000000110010011 '
bx '!
b1000 (
b11 (!
b101 *!
b11 +!
b0 ,
b1 ,!
b100 -
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b1010 /
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17
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0)
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b101 /
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07
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08
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1L
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1#
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1]
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0f
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b0 ,
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b0 /
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18
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0]
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1d
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b0 k
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b100 0
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19!
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b1 >!
bx @
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b1000 C
b11 E
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1c
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b1000 k
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b1000 %!
b10100 &
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b1010 /
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17
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b11 8!
b0 ;!
b10000 <
b1 =
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b1010 >!
b1000 B
b1100 C
bx E
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b100 H
b10 I
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b11 W
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b1010 b
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b1100 k
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0)
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b101 ,!
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b101 /
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b11 0
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07
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08
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b100 F
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1L
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1#
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1)
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14!
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b101 8!
b100100 ;!
b10 =
b1100 =!
b0 >
b10 >!
b100 ?
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0A
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b0 E
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b0 G
b0 H
b0 I
0J
0L
0M
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b0 T
b0 U
1V
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b10000 Y
b101 Z
1]
b100100 _
b1100 a
b10 b
b100100 e
0f
0w
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1z
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b10000 %!
b1000 &
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b11 +!
b0 ,
b1 ,!
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b0 /
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bx 1!
02!
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b0 6!
b0 7!
18
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1:!
b100 ;!
b0 <
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bx D
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1J
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0]
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b101 b
1d
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b100 g
b0 k
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b10011 n
b0 o
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b100 ,
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09!
0:!
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b11 @
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0c
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b100 0
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19!
bx ;!
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b1 >!
bx @
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b11 E
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1c
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b1000 k
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b10100 &
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b1010 /
b1 /!
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17
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b10000 <
b1 =
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b1100 C
bx E
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b100 H
b10 I
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b11 X
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b1010 b
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b100 x
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b1100 %!
b100 &
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0)
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b101 /
b0 /!
b11 0
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bx 6!
07
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08
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b11 ;!
b10000 <
b0 =
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b1 >
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bx ?
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b0 /
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b100 0
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b1010 /
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17
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b101 /
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07
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08
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0f
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b0 ,
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b0 /
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18
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0]
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b100 0
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bx @
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b1010 b
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b1100 k
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0f
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b0 /
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17
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0)
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07
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b10000 C
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b10 =
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b0 >
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0L
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b10000 Y
b101 Z
1]
b100100 _
b1100 a
b10 b
b100100 e
0f
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b11 +!
b0 ,
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b0 /
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18
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1:!
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bx D
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1J
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0]
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1d
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b100 g
b0 k
b100 l
b10100010011 m
b10011 n
b0 o
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1#
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b1100 &
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b100 ,
b1010 ,!
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b11 0
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b0 >!
b11 @
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b1100 -
b10010000000000000100010011 .
b100 0
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19!
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b101100 <
b10100 =!
b1 >!
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b1000 C
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1c
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b1000 k
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b1000 %!
b10100 &
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b1010 /
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17
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b0 ;!
b10000 <
b1 =
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b1100 C
bx E
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b100 H
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b11 W
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b1010 b
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b1100 k
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0)
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b101 ,!
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b101 /
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07
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08
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1L
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0y
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1#
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1)
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14!
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b101 8!
b100100 ;!
b10 =
b1100 =!
b0 >
b10 >!
b100 ?
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0A
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b0 G
b0 H
b0 I
0J
0L
0M
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b0 T
b0 U
1V
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b10000 Y
b101 Z
1]
b100100 _
b1100 a
b10 b
b100100 e
0f
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b11 +!
b0 ,
b1 ,!
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b0 /
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bx 1!
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b0 6!
b0 7!
18
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1:!
b100 ;!
b0 <
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b101 >!
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bx D
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b11 H
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1J
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0]
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1d
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b100 g
b0 k
b100 l
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b0 o
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1#
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b0 %!
b1100 &
b100 &!
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b0 +!
b100 ,
b1010 ,!
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b11 0
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09!
0:!
b0 ;!
b111 <
b0 =!
b0 >!
b11 @
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b0 D
b0 E
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1M
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0c
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b100 %!
b10000 &
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b1100 -
b10010000000000000100010011 .
b100 0
b10 1
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bx 4
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b100 7!
b1010 8!
19!
bx ;!
b101100 <
b10100 =!
b1 >!
bx @
b100 B
b1000 C
b11 E
b11 F
b11 H
b11 I
b11 S
b11 T
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b100 Y
b1010 Z
bx _
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b1 b
1c
bx e
b1100 g
b1000 k
b1100 l
b10010000000000000100010011 m
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0#
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1#
b10000 %
b1000 %!
b10100 &
b1100 &!
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bx (!
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b100 +!
b1100 ,
b10 ,!
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b10001010010001010000011 .
b1010 /
b1 /!
b101 1
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b100 2
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b11 6!
17
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b11 8!
b0 ;!
b10000 <
b1 =
b100 =!
b1010 >!
b1000 B
b1100 C
bx E
b100100 F
b100 H
b10 I
bx S
b100100 T
b100100 U
b11 W
b11 X
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b11 Z
b0 _
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b1010 b
b0 e
b10000 g
b1100 k
b10000 l
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b10 o
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1q
1s
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0!
0#
1w
#785000
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1!!
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b1100 %!
b100 &
b10000 &!
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b100 (
0)
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0*
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b10000 ,
b101 ,!
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b101 /
b0 /!
b11 0
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b1 1
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bx 3
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bx 6!
07
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08
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b11 ;!
b10000 <
b0 =
b1000 =!
b1 >
b11 >!
bx ?
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1A
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b10000 C
b100 F
b1010 G
b101 I
1L
b100 T
b100 U
b100100 W
bx X
b1100 Y
b10 Z
b11 _
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b11 b
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1f
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1q
0s
0t
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0y
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0#
1w
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1#
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1)
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1*
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b0 +!
b0 ,!
b10 /!
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14!
b100 5!
b10000 7!
b101 8!
b100100 ;!
b10 =
b1100 =!
b0 >
b10 >!
b100 ?
b11 @
0A
b0 B
b0 C
b0 E
b0 F
b0 G
b0 H
b0 I
0J
0L
0M
b0 S
b0 T
b0 U
1V
b100 W
b10000 Y
b101 Z
1]
b100100 _
b1100 a
b10 b
b100100 e
0f
0w
1y
1z
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0}
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0!
0#
1w
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b100 %
b10000 %!
b1000 &
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bx '!
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b101 *!
b11 +!
b0 ,
b1 ,!
b100 -
b1 -!
b10100010011 .
b0 /
b0 /!
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b1010 1
bx 1!
02!
b0 3
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04!
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b0 6!
b0 7!
18
b0 8!
1:!
b100 ;!
b0 <
b0 =
b10000 =!
b101 >!
b0 ?
b0 @
b10000 B
b10100 C
bx D
b11 E
b101 G
b11 H
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1J
b1 P
bx R
b11 S
b11 T
bx U
xV
b0 W
b0 X
b0 Y
b0 Z
0[
0]
b100 _
b10000 a
b101 b
1d
bx e
b100 g
b0 k
b100 l
b10100010011 m
b10011 n
b0 o
b0 p
1q
1t
0w
1}
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0!
0#
1w
#815000
1!
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1#
b1000 %
b0 %!
b1100 &
b100 &!
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b1100 (
b0 (!
b0 *!
b0 +!
b100 ,
b1010 ,!
b1000 -
b0 -!
b1100000000000110010011 .
b11 0
b11 1
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b11 2
12!
b11 4
bx 5!
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b0 /
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17
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18
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