`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: Arithmetic-Logic Unit
// Module Name: alu
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Main functional unit of the EX stage
// 
// Dependencies: 
// 
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module alu(
     input [31:0] A, B,
     input [3:0] sel,
     output reg [31:0] R,
     output zero
);

always @(*) begin
    case(sel)
        4'b0000: R = A + B;                             // add
        4'b0001: R = A - B;                             // sub
        4'b0010: R = A & B;                             // and
        4'b0011: R = A | B;                             // or
        4'b0100: R = A ^ B;                             // xor
        4'b0101: R = A << B[4:0];                       // sll
        4'b0110: R = A >> B[4:0];                       // srl
        4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt (shift if less than signed)
        4'b1000: R = (A < B) ? 1 : 0;                   // sltu (shift if less than unsigned)
        4'b1001: R = $signed(A) >>> B[4:0];             // sra (shift right arithmetic)
        4'b1010: R = 32'b0;                             // nop
        default: R = 32'b0;                             // default: nop
    endcase
end

assign zero = (R == 0);

endmodule