`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: ME/WB register
// Module Name: me_wb
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Register between ME/WB stages
// 
// Dependencies: 
// 
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module me_wb (
    input clk, rst,
    input we_reg_in, mem_to_reg_in,
    output reg we_reg_out, mem_to_reg_out,
    input [31:0] alu_in, mem_data_in, pc4_in,
    input [4:0] rd_in,
    output reg [31:0] alu_out, mem_data_out, pc4_out,
    output reg [4:0] rd_out
);

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            we_reg_out <= 0; mem_to_reg_out <= 0;
            alu_out <= 0; mem_data_out <= 0; pc4_out <= 0; rd_out <= 0;
        end else begin
            we_reg_out <= we_reg_in; mem_to_reg_out <= mem_to_reg_in;
            alu_out <= alu_in; mem_data_out <= mem_data_in; pc4_out <= pc4_in; rd_out <= rd_in;
        end
    end
endmodule